| File: | lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp |
| Warning: | line 1156, column 5 Value stored to 'N' is never read |
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| 1 | //===- ScheduleDAGRRList.cpp - Reg pressure reduction list scheduler ------===// |
| 2 | // |
| 3 | // The LLVM Compiler Infrastructure |
| 4 | // |
| 5 | // This file is distributed under the University of Illinois Open Source |
| 6 | // License. See LICENSE.TXT for details. |
| 7 | // |
| 8 | //===----------------------------------------------------------------------===// |
| 9 | // |
| 10 | // This implements bottom-up and top-down register pressure reduction list |
| 11 | // schedulers, using standard algorithms. The basic approach uses a priority |
| 12 | // queue of available nodes to schedule. One at a time, nodes are taken from |
| 13 | // the priority queue (thus in priority order), checked for legality to |
| 14 | // schedule, and emitted if legal. |
| 15 | // |
| 16 | //===----------------------------------------------------------------------===// |
| 17 | |
| 18 | #include "ScheduleDAGSDNodes.h" |
| 19 | #include "llvm/ADT/ArrayRef.h" |
| 20 | #include "llvm/ADT/DenseMap.h" |
| 21 | #include "llvm/ADT/STLExtras.h" |
| 22 | #include "llvm/ADT/SmallSet.h" |
| 23 | #include "llvm/ADT/SmallVector.h" |
| 24 | #include "llvm/ADT/Statistic.h" |
| 25 | #include "llvm/CodeGen/ISDOpcodes.h" |
| 26 | #include "llvm/CodeGen/MachineFunction.h" |
| 27 | #include "llvm/CodeGen/MachineOperand.h" |
| 28 | #include "llvm/CodeGen/MachineRegisterInfo.h" |
| 29 | #include "llvm/CodeGen/ScheduleDAG.h" |
| 30 | #include "llvm/CodeGen/ScheduleHazardRecognizer.h" |
| 31 | #include "llvm/CodeGen/SchedulerRegistry.h" |
| 32 | #include "llvm/CodeGen/SelectionDAGISel.h" |
| 33 | #include "llvm/CodeGen/SelectionDAGNodes.h" |
| 34 | #include "llvm/CodeGen/TargetInstrInfo.h" |
| 35 | #include "llvm/CodeGen/TargetLowering.h" |
| 36 | #include "llvm/CodeGen/TargetOpcodes.h" |
| 37 | #include "llvm/CodeGen/TargetRegisterInfo.h" |
| 38 | #include "llvm/CodeGen/TargetSubtargetInfo.h" |
| 39 | #include "llvm/IR/InlineAsm.h" |
| 40 | #include "llvm/MC/MCInstrDesc.h" |
| 41 | #include "llvm/MC/MCRegisterInfo.h" |
| 42 | #include "llvm/Support/Casting.h" |
| 43 | #include "llvm/Support/CodeGen.h" |
| 44 | #include "llvm/Support/CommandLine.h" |
| 45 | #include "llvm/Support/Compiler.h" |
| 46 | #include "llvm/Support/Debug.h" |
| 47 | #include "llvm/Support/ErrorHandling.h" |
| 48 | #include "llvm/Support/MachineValueType.h" |
| 49 | #include "llvm/Support/raw_ostream.h" |
| 50 | #include <algorithm> |
| 51 | #include <cassert> |
| 52 | #include <cstdint> |
| 53 | #include <cstdlib> |
| 54 | #include <iterator> |
| 55 | #include <limits> |
| 56 | #include <memory> |
| 57 | #include <utility> |
| 58 | #include <vector> |
| 59 | |
| 60 | using namespace llvm; |
| 61 | |
| 62 | #define DEBUG_TYPE"pre-RA-sched" "pre-RA-sched" |
| 63 | |
| 64 | STATISTIC(NumBacktracks, "Number of times scheduler backtracked")static llvm::Statistic NumBacktracks = {"pre-RA-sched", "NumBacktracks" , "Number of times scheduler backtracked", {0}, {false}}; |
| 65 | STATISTIC(NumUnfolds, "Number of nodes unfolded")static llvm::Statistic NumUnfolds = {"pre-RA-sched", "NumUnfolds" , "Number of nodes unfolded", {0}, {false}}; |
| 66 | STATISTIC(NumDups, "Number of duplicated nodes")static llvm::Statistic NumDups = {"pre-RA-sched", "NumDups", "Number of duplicated nodes" , {0}, {false}}; |
| 67 | STATISTIC(NumPRCopies, "Number of physical register copies")static llvm::Statistic NumPRCopies = {"pre-RA-sched", "NumPRCopies" , "Number of physical register copies", {0}, {false}}; |
| 68 | |
| 69 | static RegisterScheduler |
| 70 | burrListDAGScheduler("list-burr", |
| 71 | "Bottom-up register reduction list scheduling", |
| 72 | createBURRListDAGScheduler); |
| 73 | |
| 74 | static RegisterScheduler |
| 75 | sourceListDAGScheduler("source", |
| 76 | "Similar to list-burr but schedules in source " |
| 77 | "order when possible", |
| 78 | createSourceListDAGScheduler); |
| 79 | |
| 80 | static RegisterScheduler |
| 81 | hybridListDAGScheduler("list-hybrid", |
| 82 | "Bottom-up register pressure aware list scheduling " |
| 83 | "which tries to balance latency and register pressure", |
| 84 | createHybridListDAGScheduler); |
| 85 | |
| 86 | static RegisterScheduler |
| 87 | ILPListDAGScheduler("list-ilp", |
| 88 | "Bottom-up register pressure aware list scheduling " |
| 89 | "which tries to balance ILP and register pressure", |
| 90 | createILPListDAGScheduler); |
| 91 | |
| 92 | static cl::opt<bool> DisableSchedCycles( |
| 93 | "disable-sched-cycles", cl::Hidden, cl::init(false), |
| 94 | cl::desc("Disable cycle-level precision during preRA scheduling")); |
| 95 | |
| 96 | // Temporary sched=list-ilp flags until the heuristics are robust. |
| 97 | // Some options are also available under sched=list-hybrid. |
| 98 | static cl::opt<bool> DisableSchedRegPressure( |
| 99 | "disable-sched-reg-pressure", cl::Hidden, cl::init(false), |
| 100 | cl::desc("Disable regpressure priority in sched=list-ilp")); |
| 101 | static cl::opt<bool> DisableSchedLiveUses( |
| 102 | "disable-sched-live-uses", cl::Hidden, cl::init(true), |
| 103 | cl::desc("Disable live use priority in sched=list-ilp")); |
| 104 | static cl::opt<bool> DisableSchedVRegCycle( |
| 105 | "disable-sched-vrcycle", cl::Hidden, cl::init(false), |
| 106 | cl::desc("Disable virtual register cycle interference checks")); |
| 107 | static cl::opt<bool> DisableSchedPhysRegJoin( |
| 108 | "disable-sched-physreg-join", cl::Hidden, cl::init(false), |
| 109 | cl::desc("Disable physreg def-use affinity")); |
| 110 | static cl::opt<bool> DisableSchedStalls( |
| 111 | "disable-sched-stalls", cl::Hidden, cl::init(true), |
| 112 | cl::desc("Disable no-stall priority in sched=list-ilp")); |
| 113 | static cl::opt<bool> DisableSchedCriticalPath( |
| 114 | "disable-sched-critical-path", cl::Hidden, cl::init(false), |
| 115 | cl::desc("Disable critical path priority in sched=list-ilp")); |
| 116 | static cl::opt<bool> DisableSchedHeight( |
| 117 | "disable-sched-height", cl::Hidden, cl::init(false), |
| 118 | cl::desc("Disable scheduled-height priority in sched=list-ilp")); |
| 119 | static cl::opt<bool> Disable2AddrHack( |
| 120 | "disable-2addr-hack", cl::Hidden, cl::init(true), |
| 121 | cl::desc("Disable scheduler's two-address hack")); |
| 122 | |
| 123 | static cl::opt<int> MaxReorderWindow( |
| 124 | "max-sched-reorder", cl::Hidden, cl::init(6), |
| 125 | cl::desc("Number of instructions to allow ahead of the critical path " |
| 126 | "in sched=list-ilp")); |
| 127 | |
| 128 | static cl::opt<unsigned> AvgIPC( |
| 129 | "sched-avg-ipc", cl::Hidden, cl::init(1), |
| 130 | cl::desc("Average inst/cycle whan no target itinerary exists.")); |
| 131 | |
| 132 | namespace { |
| 133 | |
| 134 | //===----------------------------------------------------------------------===// |
| 135 | /// ScheduleDAGRRList - The actual register reduction list scheduler |
| 136 | /// implementation. This supports both top-down and bottom-up scheduling. |
| 137 | /// |
| 138 | class ScheduleDAGRRList : public ScheduleDAGSDNodes { |
| 139 | private: |
| 140 | /// NeedLatency - True if the scheduler will make use of latency information. |
| 141 | bool NeedLatency; |
| 142 | |
| 143 | /// AvailableQueue - The priority queue to use for the available SUnits. |
| 144 | SchedulingPriorityQueue *AvailableQueue; |
| 145 | |
| 146 | /// PendingQueue - This contains all of the instructions whose operands have |
| 147 | /// been issued, but their results are not ready yet (due to the latency of |
| 148 | /// the operation). Once the operands becomes available, the instruction is |
| 149 | /// added to the AvailableQueue. |
| 150 | std::vector<SUnit *> PendingQueue; |
| 151 | |
| 152 | /// HazardRec - The hazard recognizer to use. |
| 153 | ScheduleHazardRecognizer *HazardRec; |
| 154 | |
| 155 | /// CurCycle - The current scheduler state corresponds to this cycle. |
| 156 | unsigned CurCycle = 0; |
| 157 | |
| 158 | /// MinAvailableCycle - Cycle of the soonest available instruction. |
| 159 | unsigned MinAvailableCycle; |
| 160 | |
| 161 | /// IssueCount - Count instructions issued in this cycle |
| 162 | /// Currently valid only for bottom-up scheduling. |
| 163 | unsigned IssueCount; |
| 164 | |
| 165 | /// LiveRegDefs - A set of physical registers and their definition |
| 166 | /// that are "live". These nodes must be scheduled before any other nodes that |
| 167 | /// modifies the registers can be scheduled. |
| 168 | unsigned NumLiveRegs; |
| 169 | std::unique_ptr<SUnit*[]> LiveRegDefs; |
| 170 | std::unique_ptr<SUnit*[]> LiveRegGens; |
| 171 | |
| 172 | // Collect interferences between physical register use/defs. |
| 173 | // Each interference is an SUnit and set of physical registers. |
| 174 | SmallVector<SUnit*, 4> Interferences; |
| 175 | |
| 176 | using LRegsMapT = DenseMap<SUnit *, SmallVector<unsigned, 4>>; |
| 177 | |
| 178 | LRegsMapT LRegsMap; |
| 179 | |
| 180 | /// Topo - A topological ordering for SUnits which permits fast IsReachable |
| 181 | /// and similar queries. |
| 182 | ScheduleDAGTopologicalSort Topo; |
| 183 | |
| 184 | // Hack to keep track of the inverse of FindCallSeqStart without more crazy |
| 185 | // DAG crawling. |
| 186 | DenseMap<SUnit*, SUnit*> CallSeqEndForStart; |
| 187 | |
| 188 | public: |
| 189 | ScheduleDAGRRList(MachineFunction &mf, bool needlatency, |
| 190 | SchedulingPriorityQueue *availqueue, |
| 191 | CodeGenOpt::Level OptLevel) |
| 192 | : ScheduleDAGSDNodes(mf), |
| 193 | NeedLatency(needlatency), AvailableQueue(availqueue), |
| 194 | Topo(SUnits, nullptr) { |
| 195 | const TargetSubtargetInfo &STI = mf.getSubtarget(); |
| 196 | if (DisableSchedCycles || !NeedLatency) |
| 197 | HazardRec = new ScheduleHazardRecognizer(); |
| 198 | else |
| 199 | HazardRec = STI.getInstrInfo()->CreateTargetHazardRecognizer(&STI, this); |
| 200 | } |
| 201 | |
| 202 | ~ScheduleDAGRRList() override { |
| 203 | delete HazardRec; |
| 204 | delete AvailableQueue; |
| 205 | } |
| 206 | |
| 207 | void Schedule() override; |
| 208 | |
| 209 | ScheduleHazardRecognizer *getHazardRec() { return HazardRec; } |
| 210 | |
| 211 | /// IsReachable - Checks if SU is reachable from TargetSU. |
| 212 | bool IsReachable(const SUnit *SU, const SUnit *TargetSU) { |
| 213 | return Topo.IsReachable(SU, TargetSU); |
| 214 | } |
| 215 | |
| 216 | /// WillCreateCycle - Returns true if adding an edge from SU to TargetSU will |
| 217 | /// create a cycle. |
| 218 | bool WillCreateCycle(SUnit *SU, SUnit *TargetSU) { |
| 219 | return Topo.WillCreateCycle(SU, TargetSU); |
| 220 | } |
| 221 | |
| 222 | /// AddPred - adds a predecessor edge to SUnit SU. |
| 223 | /// This returns true if this is a new predecessor. |
| 224 | /// Updates the topological ordering if required. |
| 225 | void AddPred(SUnit *SU, const SDep &D) { |
| 226 | Topo.AddPred(SU, D.getSUnit()); |
| 227 | SU->addPred(D); |
| 228 | } |
| 229 | |
| 230 | /// RemovePred - removes a predecessor edge from SUnit SU. |
| 231 | /// This returns true if an edge was removed. |
| 232 | /// Updates the topological ordering if required. |
| 233 | void RemovePred(SUnit *SU, const SDep &D) { |
| 234 | Topo.RemovePred(SU, D.getSUnit()); |
| 235 | SU->removePred(D); |
| 236 | } |
| 237 | |
| 238 | private: |
| 239 | bool isReady(SUnit *SU) { |
| 240 | return DisableSchedCycles || !AvailableQueue->hasReadyFilter() || |
| 241 | AvailableQueue->isReady(SU); |
| 242 | } |
| 243 | |
| 244 | void ReleasePred(SUnit *SU, const SDep *PredEdge); |
| 245 | void ReleasePredecessors(SUnit *SU); |
| 246 | void ReleasePending(); |
| 247 | void AdvanceToCycle(unsigned NextCycle); |
| 248 | void AdvancePastStalls(SUnit *SU); |
| 249 | void EmitNode(SUnit *SU); |
| 250 | void ScheduleNodeBottomUp(SUnit*); |
| 251 | void CapturePred(SDep *PredEdge); |
| 252 | void UnscheduleNodeBottomUp(SUnit*); |
| 253 | void RestoreHazardCheckerBottomUp(); |
| 254 | void BacktrackBottomUp(SUnit*, SUnit*); |
| 255 | SUnit *TryUnfoldSU(SUnit *); |
| 256 | SUnit *CopyAndMoveSuccessors(SUnit*); |
| 257 | void InsertCopiesAndMoveSuccs(SUnit*, unsigned, |
| 258 | const TargetRegisterClass*, |
| 259 | const TargetRegisterClass*, |
| 260 | SmallVectorImpl<SUnit*>&); |
| 261 | bool DelayForLiveRegsBottomUp(SUnit*, SmallVectorImpl<unsigned>&); |
| 262 | |
| 263 | void releaseInterferences(unsigned Reg = 0); |
| 264 | |
| 265 | SUnit *PickNodeToScheduleBottomUp(); |
| 266 | void ListScheduleBottomUp(); |
| 267 | |
| 268 | /// CreateNewSUnit - Creates a new SUnit and returns a pointer to it. |
| 269 | /// Updates the topological ordering if required. |
| 270 | SUnit *CreateNewSUnit(SDNode *N) { |
| 271 | unsigned NumSUnits = SUnits.size(); |
| 272 | SUnit *NewNode = newSUnit(N); |
| 273 | // Update the topological ordering. |
| 274 | if (NewNode->NodeNum >= NumSUnits) |
| 275 | Topo.InitDAGTopologicalSorting(); |
| 276 | return NewNode; |
| 277 | } |
| 278 | |
| 279 | /// CreateClone - Creates a new SUnit from an existing one. |
| 280 | /// Updates the topological ordering if required. |
| 281 | SUnit *CreateClone(SUnit *N) { |
| 282 | unsigned NumSUnits = SUnits.size(); |
| 283 | SUnit *NewNode = Clone(N); |
| 284 | // Update the topological ordering. |
| 285 | if (NewNode->NodeNum >= NumSUnits) |
| 286 | Topo.InitDAGTopologicalSorting(); |
| 287 | return NewNode; |
| 288 | } |
| 289 | |
| 290 | /// forceUnitLatencies - Register-pressure-reducing scheduling doesn't |
| 291 | /// need actual latency information but the hybrid scheduler does. |
| 292 | bool forceUnitLatencies() const override { |
| 293 | return !NeedLatency; |
| 294 | } |
| 295 | }; |
| 296 | |
| 297 | } // end anonymous namespace |
| 298 | |
| 299 | /// GetCostForDef - Looks up the register class and cost for a given definition. |
| 300 | /// Typically this just means looking up the representative register class, |
| 301 | /// but for untyped values (MVT::Untyped) it means inspecting the node's |
| 302 | /// opcode to determine what register class is being generated. |
| 303 | static void GetCostForDef(const ScheduleDAGSDNodes::RegDefIter &RegDefPos, |
| 304 | const TargetLowering *TLI, |
| 305 | const TargetInstrInfo *TII, |
| 306 | const TargetRegisterInfo *TRI, |
| 307 | unsigned &RegClass, unsigned &Cost, |
| 308 | const MachineFunction &MF) { |
| 309 | MVT VT = RegDefPos.GetValue(); |
| 310 | |
| 311 | // Special handling for untyped values. These values can only come from |
| 312 | // the expansion of custom DAG-to-DAG patterns. |
| 313 | if (VT == MVT::Untyped) { |
| 314 | const SDNode *Node = RegDefPos.GetNode(); |
| 315 | |
| 316 | // Special handling for CopyFromReg of untyped values. |
| 317 | if (!Node->isMachineOpcode() && Node->getOpcode() == ISD::CopyFromReg) { |
| 318 | unsigned Reg = cast<RegisterSDNode>(Node->getOperand(1))->getReg(); |
| 319 | const TargetRegisterClass *RC = MF.getRegInfo().getRegClass(Reg); |
| 320 | RegClass = RC->getID(); |
| 321 | Cost = 1; |
| 322 | return; |
| 323 | } |
| 324 | |
| 325 | unsigned Opcode = Node->getMachineOpcode(); |
| 326 | if (Opcode == TargetOpcode::REG_SEQUENCE) { |
| 327 | unsigned DstRCIdx = cast<ConstantSDNode>(Node->getOperand(0))->getZExtValue(); |
| 328 | const TargetRegisterClass *RC = TRI->getRegClass(DstRCIdx); |
| 329 | RegClass = RC->getID(); |
| 330 | Cost = 1; |
| 331 | return; |
| 332 | } |
| 333 | |
| 334 | unsigned Idx = RegDefPos.GetIdx(); |
| 335 | const MCInstrDesc Desc = TII->get(Opcode); |
| 336 | const TargetRegisterClass *RC = TII->getRegClass(Desc, Idx, TRI, MF); |
| 337 | RegClass = RC->getID(); |
| 338 | // FIXME: Cost arbitrarily set to 1 because there doesn't seem to be a |
| 339 | // better way to determine it. |
| 340 | Cost = 1; |
| 341 | } else { |
| 342 | RegClass = TLI->getRepRegClassFor(VT)->getID(); |
| 343 | Cost = TLI->getRepRegClassCostFor(VT); |
| 344 | } |
| 345 | } |
| 346 | |
| 347 | /// Schedule - Schedule the DAG using list scheduling. |
| 348 | void ScheduleDAGRRList::Schedule() { |
| 349 | DEBUG(dbgs() << "********** List Scheduling " << printMBBReference(*BB)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType ("pre-RA-sched")) { dbgs() << "********** List Scheduling " << printMBBReference(*BB) << " '" << BB-> getName() << "' **********\n"; } } while (false) |
| 350 | << " '" << BB->getName() << "' **********\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType ("pre-RA-sched")) { dbgs() << "********** List Scheduling " << printMBBReference(*BB) << " '" << BB-> getName() << "' **********\n"; } } while (false); |
| 351 | |
| 352 | CurCycle = 0; |
| 353 | IssueCount = 0; |
| 354 | MinAvailableCycle = |
| 355 | DisableSchedCycles ? 0 : std::numeric_limits<unsigned>::max(); |
| 356 | NumLiveRegs = 0; |
| 357 | // Allocate slots for each physical register, plus one for a special register |
| 358 | // to track the virtual resource of a calling sequence. |
| 359 | LiveRegDefs.reset(new SUnit*[TRI->getNumRegs() + 1]()); |
| 360 | LiveRegGens.reset(new SUnit*[TRI->getNumRegs() + 1]()); |
| 361 | CallSeqEndForStart.clear(); |
| 362 | assert(Interferences.empty() && LRegsMap.empty() && "stale Interferences")(static_cast <bool> (Interferences.empty() && LRegsMap .empty() && "stale Interferences") ? void (0) : __assert_fail ("Interferences.empty() && LRegsMap.empty() && \"stale Interferences\"" , "/build/llvm-toolchain-snapshot-7~svn329677/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp" , 362, __extension__ __PRETTY_FUNCTION__)); |
| 363 | |
| 364 | // Build the scheduling graph. |
| 365 | BuildSchedGraph(nullptr); |
| 366 | |
| 367 | DEBUG(for (SUnit &SU : SUnits)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType ("pre-RA-sched")) { for (SUnit &SU : SUnits) SU.dumpAll(this ); } } while (false) |
| 368 | SU.dumpAll(this))do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType ("pre-RA-sched")) { for (SUnit &SU : SUnits) SU.dumpAll(this ); } } while (false); |
| 369 | Topo.InitDAGTopologicalSorting(); |
| 370 | |
| 371 | AvailableQueue->initNodes(SUnits); |
| 372 | |
| 373 | HazardRec->Reset(); |
| 374 | |
| 375 | // Execute the actual scheduling loop. |
| 376 | ListScheduleBottomUp(); |
| 377 | |
| 378 | AvailableQueue->releaseState(); |
| 379 | |
| 380 | DEBUG({do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType ("pre-RA-sched")) { { dbgs() << "*** Final schedule ***\n" ; dumpSchedule(); dbgs() << '\n'; }; } } while (false) |
| 381 | dbgs() << "*** Final schedule ***\n";do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType ("pre-RA-sched")) { { dbgs() << "*** Final schedule ***\n" ; dumpSchedule(); dbgs() << '\n'; }; } } while (false) |
| 382 | dumpSchedule();do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType ("pre-RA-sched")) { { dbgs() << "*** Final schedule ***\n" ; dumpSchedule(); dbgs() << '\n'; }; } } while (false) |
| 383 | dbgs() << '\n';do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType ("pre-RA-sched")) { { dbgs() << "*** Final schedule ***\n" ; dumpSchedule(); dbgs() << '\n'; }; } } while (false) |
| 384 | })do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType ("pre-RA-sched")) { { dbgs() << "*** Final schedule ***\n" ; dumpSchedule(); dbgs() << '\n'; }; } } while (false); |
| 385 | } |
| 386 | |
| 387 | //===----------------------------------------------------------------------===// |
| 388 | // Bottom-Up Scheduling |
| 389 | //===----------------------------------------------------------------------===// |
| 390 | |
| 391 | /// ReleasePred - Decrement the NumSuccsLeft count of a predecessor. Add it to |
| 392 | /// the AvailableQueue if the count reaches zero. Also update its cycle bound. |
| 393 | void ScheduleDAGRRList::ReleasePred(SUnit *SU, const SDep *PredEdge) { |
| 394 | SUnit *PredSU = PredEdge->getSUnit(); |
| 395 | |
| 396 | #ifndef NDEBUG |
| 397 | if (PredSU->NumSuccsLeft == 0) { |
| 398 | dbgs() << "*** Scheduling failed! ***\n"; |
| 399 | PredSU->dump(this); |
| 400 | dbgs() << " has been released too many times!\n"; |
| 401 | llvm_unreachable(nullptr)::llvm::llvm_unreachable_internal(nullptr, "/build/llvm-toolchain-snapshot-7~svn329677/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp" , 401); |
| 402 | } |
| 403 | #endif |
| 404 | --PredSU->NumSuccsLeft; |
| 405 | |
| 406 | if (!forceUnitLatencies()) { |
| 407 | // Updating predecessor's height. This is now the cycle when the |
| 408 | // predecessor can be scheduled without causing a pipeline stall. |
| 409 | PredSU->setHeightToAtLeast(SU->getHeight() + PredEdge->getLatency()); |
| 410 | } |
| 411 | |
| 412 | // If all the node's successors are scheduled, this node is ready |
| 413 | // to be scheduled. Ignore the special EntrySU node. |
| 414 | if (PredSU->NumSuccsLeft == 0 && PredSU != &EntrySU) { |
| 415 | PredSU->isAvailable = true; |
| 416 | |
| 417 | unsigned Height = PredSU->getHeight(); |
| 418 | if (Height < MinAvailableCycle) |
| 419 | MinAvailableCycle = Height; |
| 420 | |
| 421 | if (isReady(PredSU)) { |
| 422 | AvailableQueue->push(PredSU); |
| 423 | } |
| 424 | // CapturePred and others may have left the node in the pending queue, avoid |
| 425 | // adding it twice. |
| 426 | else if (!PredSU->isPending) { |
| 427 | PredSU->isPending = true; |
| 428 | PendingQueue.push_back(PredSU); |
| 429 | } |
| 430 | } |
| 431 | } |
| 432 | |
| 433 | /// IsChainDependent - Test if Outer is reachable from Inner through |
| 434 | /// chain dependencies. |
| 435 | static bool IsChainDependent(SDNode *Outer, SDNode *Inner, |
| 436 | unsigned NestLevel, |
| 437 | const TargetInstrInfo *TII) { |
| 438 | SDNode *N = Outer; |
| 439 | while (true) { |
| 440 | if (N == Inner) |
| 441 | return true; |
| 442 | // For a TokenFactor, examine each operand. There may be multiple ways |
| 443 | // to get to the CALLSEQ_BEGIN, but we need to find the path with the |
| 444 | // most nesting in order to ensure that we find the corresponding match. |
| 445 | if (N->getOpcode() == ISD::TokenFactor) { |
| 446 | for (const SDValue &Op : N->op_values()) |
| 447 | if (IsChainDependent(Op.getNode(), Inner, NestLevel, TII)) |
| 448 | return true; |
| 449 | return false; |
| 450 | } |
| 451 | // Check for a lowered CALLSEQ_BEGIN or CALLSEQ_END. |
| 452 | if (N->isMachineOpcode()) { |
| 453 | if (N->getMachineOpcode() == TII->getCallFrameDestroyOpcode()) { |
| 454 | ++NestLevel; |
| 455 | } else if (N->getMachineOpcode() == TII->getCallFrameSetupOpcode()) { |
| 456 | if (NestLevel == 0) |
| 457 | return false; |
| 458 | --NestLevel; |
| 459 | } |
| 460 | } |
| 461 | // Otherwise, find the chain and continue climbing. |
| 462 | for (const SDValue &Op : N->op_values()) |
| 463 | if (Op.getValueType() == MVT::Other) { |
| 464 | N = Op.getNode(); |
| 465 | goto found_chain_operand; |
| 466 | } |
| 467 | return false; |
| 468 | found_chain_operand:; |
| 469 | if (N->getOpcode() == ISD::EntryToken) |
| 470 | return false; |
| 471 | } |
| 472 | } |
| 473 | |
| 474 | /// FindCallSeqStart - Starting from the (lowered) CALLSEQ_END node, locate |
| 475 | /// the corresponding (lowered) CALLSEQ_BEGIN node. |
| 476 | /// |
| 477 | /// NestLevel and MaxNested are used in recursion to indcate the current level |
| 478 | /// of nesting of CALLSEQ_BEGIN and CALLSEQ_END pairs, as well as the maximum |
| 479 | /// level seen so far. |
| 480 | /// |
| 481 | /// TODO: It would be better to give CALLSEQ_END an explicit operand to point |
| 482 | /// to the corresponding CALLSEQ_BEGIN to avoid needing to search for it. |
| 483 | static SDNode * |
| 484 | FindCallSeqStart(SDNode *N, unsigned &NestLevel, unsigned &MaxNest, |
| 485 | const TargetInstrInfo *TII) { |
| 486 | while (true) { |
| 487 | // For a TokenFactor, examine each operand. There may be multiple ways |
| 488 | // to get to the CALLSEQ_BEGIN, but we need to find the path with the |
| 489 | // most nesting in order to ensure that we find the corresponding match. |
| 490 | if (N->getOpcode() == ISD::TokenFactor) { |
| 491 | SDNode *Best = nullptr; |
| 492 | unsigned BestMaxNest = MaxNest; |
| 493 | for (const SDValue &Op : N->op_values()) { |
| 494 | unsigned MyNestLevel = NestLevel; |
| 495 | unsigned MyMaxNest = MaxNest; |
| 496 | if (SDNode *New = FindCallSeqStart(Op.getNode(), |
| 497 | MyNestLevel, MyMaxNest, TII)) |
| 498 | if (!Best || (MyMaxNest > BestMaxNest)) { |
| 499 | Best = New; |
| 500 | BestMaxNest = MyMaxNest; |
| 501 | } |
| 502 | } |
| 503 | assert(Best)(static_cast <bool> (Best) ? void (0) : __assert_fail ( "Best", "/build/llvm-toolchain-snapshot-7~svn329677/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp" , 503, __extension__ __PRETTY_FUNCTION__)); |
| 504 | MaxNest = BestMaxNest; |
| 505 | return Best; |
| 506 | } |
| 507 | // Check for a lowered CALLSEQ_BEGIN or CALLSEQ_END. |
| 508 | if (N->isMachineOpcode()) { |
| 509 | if (N->getMachineOpcode() == TII->getCallFrameDestroyOpcode()) { |
| 510 | ++NestLevel; |
| 511 | MaxNest = std::max(MaxNest, NestLevel); |
| 512 | } else if (N->getMachineOpcode() == TII->getCallFrameSetupOpcode()) { |
| 513 | assert(NestLevel != 0)(static_cast <bool> (NestLevel != 0) ? void (0) : __assert_fail ("NestLevel != 0", "/build/llvm-toolchain-snapshot-7~svn329677/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp" , 513, __extension__ __PRETTY_FUNCTION__)); |
| 514 | --NestLevel; |
| 515 | if (NestLevel == 0) |
| 516 | return N; |
| 517 | } |
| 518 | } |
| 519 | // Otherwise, find the chain and continue climbing. |
| 520 | for (const SDValue &Op : N->op_values()) |
| 521 | if (Op.getValueType() == MVT::Other) { |
| 522 | N = Op.getNode(); |
| 523 | goto found_chain_operand; |
| 524 | } |
| 525 | return nullptr; |
| 526 | found_chain_operand:; |
| 527 | if (N->getOpcode() == ISD::EntryToken) |
| 528 | return nullptr; |
| 529 | } |
| 530 | } |
| 531 | |
| 532 | /// Call ReleasePred for each predecessor, then update register live def/gen. |
| 533 | /// Always update LiveRegDefs for a register dependence even if the current SU |
| 534 | /// also defines the register. This effectively create one large live range |
| 535 | /// across a sequence of two-address node. This is important because the |
| 536 | /// entire chain must be scheduled together. Example: |
| 537 | /// |
| 538 | /// flags = (3) add |
| 539 | /// flags = (2) addc flags |
| 540 | /// flags = (1) addc flags |
| 541 | /// |
| 542 | /// results in |
| 543 | /// |
| 544 | /// LiveRegDefs[flags] = 3 |
| 545 | /// LiveRegGens[flags] = 1 |
| 546 | /// |
| 547 | /// If (2) addc is unscheduled, then (1) addc must also be unscheduled to avoid |
| 548 | /// interference on flags. |
| 549 | void ScheduleDAGRRList::ReleasePredecessors(SUnit *SU) { |
| 550 | // Bottom up: release predecessors |
| 551 | for (SDep &Pred : SU->Preds) { |
| 552 | ReleasePred(SU, &Pred); |
| 553 | if (Pred.isAssignedRegDep()) { |
| 554 | // This is a physical register dependency and it's impossible or |
| 555 | // expensive to copy the register. Make sure nothing that can |
| 556 | // clobber the register is scheduled between the predecessor and |
| 557 | // this node. |
| 558 | SUnit *RegDef = LiveRegDefs[Pred.getReg()]; (void)RegDef; |
| 559 | assert((!RegDef || RegDef == SU || RegDef == Pred.getSUnit()) &&(static_cast <bool> ((!RegDef || RegDef == SU || RegDef == Pred.getSUnit()) && "interference on register dependence" ) ? void (0) : __assert_fail ("(!RegDef || RegDef == SU || RegDef == Pred.getSUnit()) && \"interference on register dependence\"" , "/build/llvm-toolchain-snapshot-7~svn329677/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp" , 560, __extension__ __PRETTY_FUNCTION__)) |
| 560 | "interference on register dependence")(static_cast <bool> ((!RegDef || RegDef == SU || RegDef == Pred.getSUnit()) && "interference on register dependence" ) ? void (0) : __assert_fail ("(!RegDef || RegDef == SU || RegDef == Pred.getSUnit()) && \"interference on register dependence\"" , "/build/llvm-toolchain-snapshot-7~svn329677/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp" , 560, __extension__ __PRETTY_FUNCTION__)); |
| 561 | LiveRegDefs[Pred.getReg()] = Pred.getSUnit(); |
| 562 | if (!LiveRegGens[Pred.getReg()]) { |
| 563 | ++NumLiveRegs; |
| 564 | LiveRegGens[Pred.getReg()] = SU; |
| 565 | } |
| 566 | } |
| 567 | } |
| 568 | |
| 569 | // If we're scheduling a lowered CALLSEQ_END, find the corresponding |
| 570 | // CALLSEQ_BEGIN. Inject an artificial physical register dependence between |
| 571 | // these nodes, to prevent other calls from being interscheduled with them. |
| 572 | unsigned CallResource = TRI->getNumRegs(); |
| 573 | if (!LiveRegDefs[CallResource]) |
| 574 | for (SDNode *Node = SU->getNode(); Node; Node = Node->getGluedNode()) |
| 575 | if (Node->isMachineOpcode() && |
| 576 | Node->getMachineOpcode() == TII->getCallFrameDestroyOpcode()) { |
| 577 | unsigned NestLevel = 0; |
| 578 | unsigned MaxNest = 0; |
| 579 | SDNode *N = FindCallSeqStart(Node, NestLevel, MaxNest, TII); |
| 580 | assert(N && "Must find call sequence start")(static_cast <bool> (N && "Must find call sequence start" ) ? void (0) : __assert_fail ("N && \"Must find call sequence start\"" , "/build/llvm-toolchain-snapshot-7~svn329677/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp" , 580, __extension__ __PRETTY_FUNCTION__)); |
| 581 | |
| 582 | SUnit *Def = &SUnits[N->getNodeId()]; |
| 583 | CallSeqEndForStart[Def] = SU; |
| 584 | |
| 585 | ++NumLiveRegs; |
| 586 | LiveRegDefs[CallResource] = Def; |
| 587 | LiveRegGens[CallResource] = SU; |
| 588 | break; |
| 589 | } |
| 590 | } |
| 591 | |
| 592 | /// Check to see if any of the pending instructions are ready to issue. If |
| 593 | /// so, add them to the available queue. |
| 594 | void ScheduleDAGRRList::ReleasePending() { |
| 595 | if (DisableSchedCycles) { |
| 596 | assert(PendingQueue.empty() && "pending instrs not allowed in this mode")(static_cast <bool> (PendingQueue.empty() && "pending instrs not allowed in this mode" ) ? void (0) : __assert_fail ("PendingQueue.empty() && \"pending instrs not allowed in this mode\"" , "/build/llvm-toolchain-snapshot-7~svn329677/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp" , 596, __extension__ __PRETTY_FUNCTION__)); |
| 597 | return; |
| 598 | } |
| 599 | |
| 600 | // If the available queue is empty, it is safe to reset MinAvailableCycle. |
| 601 | if (AvailableQueue->empty()) |
| 602 | MinAvailableCycle = std::numeric_limits<unsigned>::max(); |
| 603 | |
| 604 | // Check to see if any of the pending instructions are ready to issue. If |
| 605 | // so, add them to the available queue. |
| 606 | for (unsigned i = 0, e = PendingQueue.size(); i != e; ++i) { |
| 607 | unsigned ReadyCycle = PendingQueue[i]->getHeight(); |
| 608 | if (ReadyCycle < MinAvailableCycle) |
| 609 | MinAvailableCycle = ReadyCycle; |
| 610 | |
| 611 | if (PendingQueue[i]->isAvailable) { |
| 612 | if (!isReady(PendingQueue[i])) |
| 613 | continue; |
| 614 | AvailableQueue->push(PendingQueue[i]); |
| 615 | } |
| 616 | PendingQueue[i]->isPending = false; |
| 617 | PendingQueue[i] = PendingQueue.back(); |
| 618 | PendingQueue.pop_back(); |
| 619 | --i; --e; |
| 620 | } |
| 621 | } |
| 622 | |
| 623 | /// Move the scheduler state forward by the specified number of Cycles. |
| 624 | void ScheduleDAGRRList::AdvanceToCycle(unsigned NextCycle) { |
| 625 | if (NextCycle <= CurCycle) |
| 626 | return; |
| 627 | |
| 628 | IssueCount = 0; |
| 629 | AvailableQueue->setCurCycle(NextCycle); |
| 630 | if (!HazardRec->isEnabled()) { |
| 631 | // Bypass lots of virtual calls in case of long latency. |
| 632 | CurCycle = NextCycle; |
| 633 | } |
| 634 | else { |
| 635 | for (; CurCycle != NextCycle; ++CurCycle) { |
| 636 | HazardRec->RecedeCycle(); |
| 637 | } |
| 638 | } |
| 639 | // FIXME: Instead of visiting the pending Q each time, set a dirty flag on the |
| 640 | // available Q to release pending nodes at least once before popping. |
| 641 | ReleasePending(); |
| 642 | } |
| 643 | |
| 644 | /// Move the scheduler state forward until the specified node's dependents are |
| 645 | /// ready and can be scheduled with no resource conflicts. |
| 646 | void ScheduleDAGRRList::AdvancePastStalls(SUnit *SU) { |
| 647 | if (DisableSchedCycles) |
| 648 | return; |
| 649 | |
| 650 | // FIXME: Nodes such as CopyFromReg probably should not advance the current |
| 651 | // cycle. Otherwise, we can wrongly mask real stalls. If the non-machine node |
| 652 | // has predecessors the cycle will be advanced when they are scheduled. |
| 653 | // But given the crude nature of modeling latency though such nodes, we |
| 654 | // currently need to treat these nodes like real instructions. |
| 655 | // if (!SU->getNode() || !SU->getNode()->isMachineOpcode()) return; |
| 656 | |
| 657 | unsigned ReadyCycle = SU->getHeight(); |
| 658 | |
| 659 | // Bump CurCycle to account for latency. We assume the latency of other |
| 660 | // available instructions may be hidden by the stall (not a full pipe stall). |
| 661 | // This updates the hazard recognizer's cycle before reserving resources for |
| 662 | // this instruction. |
| 663 | AdvanceToCycle(ReadyCycle); |
| 664 | |
| 665 | // Calls are scheduled in their preceding cycle, so don't conflict with |
| 666 | // hazards from instructions after the call. EmitNode will reset the |
| 667 | // scoreboard state before emitting the call. |
| 668 | if (SU->isCall) |
| 669 | return; |
| 670 | |
| 671 | // FIXME: For resource conflicts in very long non-pipelined stages, we |
| 672 | // should probably skip ahead here to avoid useless scoreboard checks. |
| 673 | int Stalls = 0; |
| 674 | while (true) { |
| 675 | ScheduleHazardRecognizer::HazardType HT = |
| 676 | HazardRec->getHazardType(SU, -Stalls); |
| 677 | |
| 678 | if (HT == ScheduleHazardRecognizer::NoHazard) |
| 679 | break; |
| 680 | |
| 681 | ++Stalls; |
| 682 | } |
| 683 | AdvanceToCycle(CurCycle + Stalls); |
| 684 | } |
| 685 | |
| 686 | /// Record this SUnit in the HazardRecognizer. |
| 687 | /// Does not update CurCycle. |
| 688 | void ScheduleDAGRRList::EmitNode(SUnit *SU) { |
| 689 | if (!HazardRec->isEnabled()) |
| 690 | return; |
| 691 | |
| 692 | // Check for phys reg copy. |
| 693 | if (!SU->getNode()) |
| 694 | return; |
| 695 | |
| 696 | switch (SU->getNode()->getOpcode()) { |
| 697 | default: |
| 698 | assert(SU->getNode()->isMachineOpcode() &&(static_cast <bool> (SU->getNode()->isMachineOpcode () && "This target-independent node should not be scheduled." ) ? void (0) : __assert_fail ("SU->getNode()->isMachineOpcode() && \"This target-independent node should not be scheduled.\"" , "/build/llvm-toolchain-snapshot-7~svn329677/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp" , 699, __extension__ __PRETTY_FUNCTION__)) |
| 699 | "This target-independent node should not be scheduled.")(static_cast <bool> (SU->getNode()->isMachineOpcode () && "This target-independent node should not be scheduled." ) ? void (0) : __assert_fail ("SU->getNode()->isMachineOpcode() && \"This target-independent node should not be scheduled.\"" , "/build/llvm-toolchain-snapshot-7~svn329677/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp" , 699, __extension__ __PRETTY_FUNCTION__)); |
| 700 | break; |
| 701 | case ISD::MERGE_VALUES: |
| 702 | case ISD::TokenFactor: |
| 703 | case ISD::LIFETIME_START: |
| 704 | case ISD::LIFETIME_END: |
| 705 | case ISD::CopyToReg: |
| 706 | case ISD::CopyFromReg: |
| 707 | case ISD::EH_LABEL: |
| 708 | // Noops don't affect the scoreboard state. Copies are likely to be |
| 709 | // removed. |
| 710 | return; |
| 711 | case ISD::INLINEASM: |
| 712 | // For inline asm, clear the pipeline state. |
| 713 | HazardRec->Reset(); |
| 714 | return; |
| 715 | } |
| 716 | if (SU->isCall) { |
| 717 | // Calls are scheduled with their preceding instructions. For bottom-up |
| 718 | // scheduling, clear the pipeline state before emitting. |
| 719 | HazardRec->Reset(); |
| 720 | } |
| 721 | |
| 722 | HazardRec->EmitInstruction(SU); |
| 723 | } |
| 724 | |
| 725 | static void resetVRegCycle(SUnit *SU); |
| 726 | |
| 727 | /// ScheduleNodeBottomUp - Add the node to the schedule. Decrement the pending |
| 728 | /// count of its predecessors. If a predecessor pending count is zero, add it to |
| 729 | /// the Available queue. |
| 730 | void ScheduleDAGRRList::ScheduleNodeBottomUp(SUnit *SU) { |
| 731 | DEBUG(dbgs() << "\n*** Scheduling [" << CurCycle << "]: ")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType ("pre-RA-sched")) { dbgs() << "\n*** Scheduling [" << CurCycle << "]: "; } } while (false); |
| 732 | DEBUG(SU->dump(this))do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType ("pre-RA-sched")) { SU->dump(this); } } while (false); |
| 733 | |
| 734 | #ifndef NDEBUG |
| 735 | if (CurCycle < SU->getHeight()) |
| 736 | DEBUG(dbgs() << " Height [" << SU->getHeight()do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType ("pre-RA-sched")) { dbgs() << " Height [" << SU ->getHeight() << "] pipeline stall!\n"; } } while (false ) |
| 737 | << "] pipeline stall!\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType ("pre-RA-sched")) { dbgs() << " Height [" << SU ->getHeight() << "] pipeline stall!\n"; } } while (false ); |
| 738 | #endif |
| 739 | |
| 740 | // FIXME: Do not modify node height. It may interfere with |
| 741 | // backtracking. Instead add a "ready cycle" to SUnit. Before scheduling the |
| 742 | // node its ready cycle can aid heuristics, and after scheduling it can |
| 743 | // indicate the scheduled cycle. |
| 744 | SU->setHeightToAtLeast(CurCycle); |
| 745 | |
| 746 | // Reserve resources for the scheduled instruction. |
| 747 | EmitNode(SU); |
| 748 | |
| 749 | Sequence.push_back(SU); |
| 750 | |
| 751 | AvailableQueue->scheduledNode(SU); |
| 752 | |
| 753 | // If HazardRec is disabled, and each inst counts as one cycle, then |
| 754 | // advance CurCycle before ReleasePredecessors to avoid useless pushes to |
| 755 | // PendingQueue for schedulers that implement HasReadyFilter. |
| 756 | if (!HazardRec->isEnabled() && AvgIPC < 2) |
| 757 | AdvanceToCycle(CurCycle + 1); |
| 758 | |
| 759 | // Update liveness of predecessors before successors to avoid treating a |
| 760 | // two-address node as a live range def. |
| 761 | ReleasePredecessors(SU); |
| 762 | |
| 763 | // Release all the implicit physical register defs that are live. |
| 764 | for (SDep &Succ : SU->Succs) { |
| 765 | // LiveRegDegs[Succ.getReg()] != SU when SU is a two-address node. |
| 766 | if (Succ.isAssignedRegDep() && LiveRegDefs[Succ.getReg()] == SU) { |
| 767 | assert(NumLiveRegs > 0 && "NumLiveRegs is already zero!")(static_cast <bool> (NumLiveRegs > 0 && "NumLiveRegs is already zero!" ) ? void (0) : __assert_fail ("NumLiveRegs > 0 && \"NumLiveRegs is already zero!\"" , "/build/llvm-toolchain-snapshot-7~svn329677/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp" , 767, __extension__ __PRETTY_FUNCTION__)); |
| 768 | --NumLiveRegs; |
| 769 | LiveRegDefs[Succ.getReg()] = nullptr; |
| 770 | LiveRegGens[Succ.getReg()] = nullptr; |
| 771 | releaseInterferences(Succ.getReg()); |
| 772 | } |
| 773 | } |
| 774 | // Release the special call resource dependence, if this is the beginning |
| 775 | // of a call. |
| 776 | unsigned CallResource = TRI->getNumRegs(); |
| 777 | if (LiveRegDefs[CallResource] == SU) |
| 778 | for (const SDNode *SUNode = SU->getNode(); SUNode; |
| 779 | SUNode = SUNode->getGluedNode()) { |
| 780 | if (SUNode->isMachineOpcode() && |
| 781 | SUNode->getMachineOpcode() == TII->getCallFrameSetupOpcode()) { |
| 782 | assert(NumLiveRegs > 0 && "NumLiveRegs is already zero!")(static_cast <bool> (NumLiveRegs > 0 && "NumLiveRegs is already zero!" ) ? void (0) : __assert_fail ("NumLiveRegs > 0 && \"NumLiveRegs is already zero!\"" , "/build/llvm-toolchain-snapshot-7~svn329677/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp" , 782, __extension__ __PRETTY_FUNCTION__)); |
| 783 | --NumLiveRegs; |
| 784 | LiveRegDefs[CallResource] = nullptr; |
| 785 | LiveRegGens[CallResource] = nullptr; |
| 786 | releaseInterferences(CallResource); |
| 787 | } |
| 788 | } |
| 789 | |
| 790 | resetVRegCycle(SU); |
| 791 | |
| 792 | SU->isScheduled = true; |
| 793 | |
| 794 | // Conditions under which the scheduler should eagerly advance the cycle: |
| 795 | // (1) No available instructions |
| 796 | // (2) All pipelines full, so available instructions must have hazards. |
| 797 | // |
| 798 | // If HazardRec is disabled, the cycle was pre-advanced before calling |
| 799 | // ReleasePredecessors. In that case, IssueCount should remain 0. |
| 800 | // |
| 801 | // Check AvailableQueue after ReleasePredecessors in case of zero latency. |
| 802 | if (HazardRec->isEnabled() || AvgIPC > 1) { |
| 803 | if (SU->getNode() && SU->getNode()->isMachineOpcode()) |
| 804 | ++IssueCount; |
| 805 | if ((HazardRec->isEnabled() && HazardRec->atIssueLimit()) |
| 806 | || (!HazardRec->isEnabled() && IssueCount == AvgIPC)) |
| 807 | AdvanceToCycle(CurCycle + 1); |
| 808 | } |
| 809 | } |
| 810 | |
| 811 | /// CapturePred - This does the opposite of ReleasePred. Since SU is being |
| 812 | /// unscheduled, increase the succ left count of its predecessors. Remove |
| 813 | /// them from AvailableQueue if necessary. |
| 814 | void ScheduleDAGRRList::CapturePred(SDep *PredEdge) { |
| 815 | SUnit *PredSU = PredEdge->getSUnit(); |
| 816 | if (PredSU->isAvailable) { |
| 817 | PredSU->isAvailable = false; |
| 818 | if (!PredSU->isPending) |
| 819 | AvailableQueue->remove(PredSU); |
| 820 | } |
| 821 | |
| 822 | assert(PredSU->NumSuccsLeft < std::numeric_limits<unsigned>::max() &&(static_cast <bool> (PredSU->NumSuccsLeft < std:: numeric_limits<unsigned>::max() && "NumSuccsLeft will overflow!" ) ? void (0) : __assert_fail ("PredSU->NumSuccsLeft < std::numeric_limits<unsigned>::max() && \"NumSuccsLeft will overflow!\"" , "/build/llvm-toolchain-snapshot-7~svn329677/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp" , 823, __extension__ __PRETTY_FUNCTION__)) |
| 823 | "NumSuccsLeft will overflow!")(static_cast <bool> (PredSU->NumSuccsLeft < std:: numeric_limits<unsigned>::max() && "NumSuccsLeft will overflow!" ) ? void (0) : __assert_fail ("PredSU->NumSuccsLeft < std::numeric_limits<unsigned>::max() && \"NumSuccsLeft will overflow!\"" , "/build/llvm-toolchain-snapshot-7~svn329677/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp" , 823, __extension__ __PRETTY_FUNCTION__)); |
| 824 | ++PredSU->NumSuccsLeft; |
| 825 | } |
| 826 | |
| 827 | /// UnscheduleNodeBottomUp - Remove the node from the schedule, update its and |
| 828 | /// its predecessor states to reflect the change. |
| 829 | void ScheduleDAGRRList::UnscheduleNodeBottomUp(SUnit *SU) { |
| 830 | DEBUG(dbgs() << "*** Unscheduling [" << SU->getHeight() << "]: ")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType ("pre-RA-sched")) { dbgs() << "*** Unscheduling [" << SU->getHeight() << "]: "; } } while (false); |
| 831 | DEBUG(SU->dump(this))do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType ("pre-RA-sched")) { SU->dump(this); } } while (false); |
| 832 | |
| 833 | for (SDep &Pred : SU->Preds) { |
| 834 | CapturePred(&Pred); |
| 835 | if (Pred.isAssignedRegDep() && SU == LiveRegGens[Pred.getReg()]){ |
| 836 | assert(NumLiveRegs > 0 && "NumLiveRegs is already zero!")(static_cast <bool> (NumLiveRegs > 0 && "NumLiveRegs is already zero!" ) ? void (0) : __assert_fail ("NumLiveRegs > 0 && \"NumLiveRegs is already zero!\"" , "/build/llvm-toolchain-snapshot-7~svn329677/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp" , 836, __extension__ __PRETTY_FUNCTION__)); |
| 837 | assert(LiveRegDefs[Pred.getReg()] == Pred.getSUnit() &&(static_cast <bool> (LiveRegDefs[Pred.getReg()] == Pred .getSUnit() && "Physical register dependency violated?" ) ? void (0) : __assert_fail ("LiveRegDefs[Pred.getReg()] == Pred.getSUnit() && \"Physical register dependency violated?\"" , "/build/llvm-toolchain-snapshot-7~svn329677/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp" , 838, __extension__ __PRETTY_FUNCTION__)) |
| 838 | "Physical register dependency violated?")(static_cast <bool> (LiveRegDefs[Pred.getReg()] == Pred .getSUnit() && "Physical register dependency violated?" ) ? void (0) : __assert_fail ("LiveRegDefs[Pred.getReg()] == Pred.getSUnit() && \"Physical register dependency violated?\"" , "/build/llvm-toolchain-snapshot-7~svn329677/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp" , 838, __extension__ __PRETTY_FUNCTION__)); |
| 839 | --NumLiveRegs; |
| 840 | LiveRegDefs[Pred.getReg()] = nullptr; |
| 841 | LiveRegGens[Pred.getReg()] = nullptr; |
| 842 | releaseInterferences(Pred.getReg()); |
| 843 | } |
| 844 | } |
| 845 | |
| 846 | // Reclaim the special call resource dependence, if this is the beginning |
| 847 | // of a call. |
| 848 | unsigned CallResource = TRI->getNumRegs(); |
| 849 | for (const SDNode *SUNode = SU->getNode(); SUNode; |
| 850 | SUNode = SUNode->getGluedNode()) { |
| 851 | if (SUNode->isMachineOpcode() && |
| 852 | SUNode->getMachineOpcode() == TII->getCallFrameSetupOpcode()) { |
| 853 | SUnit *SeqEnd = CallSeqEndForStart[SU]; |
| 854 | assert(SeqEnd && "Call sequence start/end must be known")(static_cast <bool> (SeqEnd && "Call sequence start/end must be known" ) ? void (0) : __assert_fail ("SeqEnd && \"Call sequence start/end must be known\"" , "/build/llvm-toolchain-snapshot-7~svn329677/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp" , 854, __extension__ __PRETTY_FUNCTION__)); |
| 855 | assert(!LiveRegDefs[CallResource])(static_cast <bool> (!LiveRegDefs[CallResource]) ? void (0) : __assert_fail ("!LiveRegDefs[CallResource]", "/build/llvm-toolchain-snapshot-7~svn329677/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp" , 855, __extension__ __PRETTY_FUNCTION__)); |
| 856 | assert(!LiveRegGens[CallResource])(static_cast <bool> (!LiveRegGens[CallResource]) ? void (0) : __assert_fail ("!LiveRegGens[CallResource]", "/build/llvm-toolchain-snapshot-7~svn329677/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp" , 856, __extension__ __PRETTY_FUNCTION__)); |
| 857 | ++NumLiveRegs; |
| 858 | LiveRegDefs[CallResource] = SU; |
| 859 | LiveRegGens[CallResource] = SeqEnd; |
| 860 | } |
| 861 | } |
| 862 | |
| 863 | // Release the special call resource dependence, if this is the end |
| 864 | // of a call. |
| 865 | if (LiveRegGens[CallResource] == SU) |
| 866 | for (const SDNode *SUNode = SU->getNode(); SUNode; |
| 867 | SUNode = SUNode->getGluedNode()) { |
| 868 | if (SUNode->isMachineOpcode() && |
| 869 | SUNode->getMachineOpcode() == TII->getCallFrameDestroyOpcode()) { |
| 870 | assert(NumLiveRegs > 0 && "NumLiveRegs is already zero!")(static_cast <bool> (NumLiveRegs > 0 && "NumLiveRegs is already zero!" ) ? void (0) : __assert_fail ("NumLiveRegs > 0 && \"NumLiveRegs is already zero!\"" , "/build/llvm-toolchain-snapshot-7~svn329677/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp" , 870, __extension__ __PRETTY_FUNCTION__)); |
| 871 | assert(LiveRegDefs[CallResource])(static_cast <bool> (LiveRegDefs[CallResource]) ? void ( 0) : __assert_fail ("LiveRegDefs[CallResource]", "/build/llvm-toolchain-snapshot-7~svn329677/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp" , 871, __extension__ __PRETTY_FUNCTION__)); |
| 872 | assert(LiveRegGens[CallResource])(static_cast <bool> (LiveRegGens[CallResource]) ? void ( 0) : __assert_fail ("LiveRegGens[CallResource]", "/build/llvm-toolchain-snapshot-7~svn329677/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp" , 872, __extension__ __PRETTY_FUNCTION__)); |
| 873 | --NumLiveRegs; |
| 874 | LiveRegDefs[CallResource] = nullptr; |
| 875 | LiveRegGens[CallResource] = nullptr; |
| 876 | releaseInterferences(CallResource); |
| 877 | } |
| 878 | } |
| 879 | |
| 880 | for (auto &Succ : SU->Succs) { |
| 881 | if (Succ.isAssignedRegDep()) { |
| 882 | auto Reg = Succ.getReg(); |
| 883 | if (!LiveRegDefs[Reg]) |
| 884 | ++NumLiveRegs; |
| 885 | // This becomes the nearest def. Note that an earlier def may still be |
| 886 | // pending if this is a two-address node. |
| 887 | LiveRegDefs[Reg] = SU; |
| 888 | |
| 889 | // Update LiveRegGen only if was empty before this unscheduling. |
| 890 | // This is to avoid incorrect updating LiveRegGen set in previous run. |
| 891 | if (!LiveRegGens[Reg]) { |
| 892 | // Find the successor with the lowest height. |
| 893 | LiveRegGens[Reg] = Succ.getSUnit(); |
| 894 | for (auto &Succ2 : SU->Succs) { |
| 895 | if (Succ2.isAssignedRegDep() && Succ2.getReg() == Reg && |
| 896 | Succ2.getSUnit()->getHeight() < LiveRegGens[Reg]->getHeight()) |
| 897 | LiveRegGens[Reg] = Succ2.getSUnit(); |
| 898 | } |
| 899 | } |
| 900 | } |
| 901 | } |
| 902 | if (SU->getHeight() < MinAvailableCycle) |
| 903 | MinAvailableCycle = SU->getHeight(); |
| 904 | |
| 905 | SU->setHeightDirty(); |
| 906 | SU->isScheduled = false; |
| 907 | SU->isAvailable = true; |
| 908 | if (!DisableSchedCycles && AvailableQueue->hasReadyFilter()) { |
| 909 | // Don't make available until backtracking is complete. |
| 910 | SU->isPending = true; |
| 911 | PendingQueue.push_back(SU); |
| 912 | } |
| 913 | else { |
| 914 | AvailableQueue->push(SU); |
| 915 | } |
| 916 | AvailableQueue->unscheduledNode(SU); |
| 917 | } |
| 918 | |
| 919 | /// After backtracking, the hazard checker needs to be restored to a state |
| 920 | /// corresponding the current cycle. |
| 921 | void ScheduleDAGRRList::RestoreHazardCheckerBottomUp() { |
| 922 | HazardRec->Reset(); |
| 923 | |
| 924 | unsigned LookAhead = std::min((unsigned)Sequence.size(), |
| 925 | HazardRec->getMaxLookAhead()); |
| 926 | if (LookAhead == 0) |
| 927 | return; |
| 928 | |
| 929 | std::vector<SUnit *>::const_iterator I = (Sequence.end() - LookAhead); |
| 930 | unsigned HazardCycle = (*I)->getHeight(); |
| 931 | for (auto E = Sequence.end(); I != E; ++I) { |
| 932 | SUnit *SU = *I; |
| 933 | for (; SU->getHeight() > HazardCycle; ++HazardCycle) { |
| 934 | HazardRec->RecedeCycle(); |
| 935 | } |
| 936 | EmitNode(SU); |
| 937 | } |
| 938 | } |
| 939 | |
| 940 | /// BacktrackBottomUp - Backtrack scheduling to a previous cycle specified in |
| 941 | /// BTCycle in order to schedule a specific node. |
| 942 | void ScheduleDAGRRList::BacktrackBottomUp(SUnit *SU, SUnit *BtSU) { |
| 943 | SUnit *OldSU = Sequence.back(); |
| 944 | while (true) { |
| 945 | Sequence.pop_back(); |
| 946 | // FIXME: use ready cycle instead of height |
| 947 | CurCycle = OldSU->getHeight(); |
| 948 | UnscheduleNodeBottomUp(OldSU); |
| 949 | AvailableQueue->setCurCycle(CurCycle); |
| 950 | if (OldSU == BtSU) |
| 951 | break; |
| 952 | OldSU = Sequence.back(); |
| 953 | } |
| 954 | |
| 955 | assert(!SU->isSucc(OldSU) && "Something is wrong!")(static_cast <bool> (!SU->isSucc(OldSU) && "Something is wrong!" ) ? void (0) : __assert_fail ("!SU->isSucc(OldSU) && \"Something is wrong!\"" , "/build/llvm-toolchain-snapshot-7~svn329677/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp" , 955, __extension__ __PRETTY_FUNCTION__)); |
| 956 | |
| 957 | RestoreHazardCheckerBottomUp(); |
| 958 | |
| 959 | ReleasePending(); |
| 960 | |
| 961 | ++NumBacktracks; |
| 962 | } |
| 963 | |
| 964 | static bool isOperandOf(const SUnit *SU, SDNode *N) { |
| 965 | for (const SDNode *SUNode = SU->getNode(); SUNode; |
| 966 | SUNode = SUNode->getGluedNode()) { |
| 967 | if (SUNode->isOperandOf(N)) |
| 968 | return true; |
| 969 | } |
| 970 | return false; |
| 971 | } |
| 972 | |
| 973 | /// TryUnfold - Attempt to unfold |
| 974 | SUnit *ScheduleDAGRRList::TryUnfoldSU(SUnit *SU) { |
| 975 | SDNode *N = SU->getNode(); |
| 976 | // Use while over if to ease fall through. |
| 977 | SmallVector<SDNode *, 2> NewNodes; |
| 978 | if (!TII->unfoldMemoryOperand(*DAG, N, NewNodes)) |
| 979 | return nullptr; |
| 980 | |
| 981 | // unfolding an x86 DEC64m operation results in store, dec, load which |
| 982 | // can't be handled here so quit |
| 983 | if (NewNodes.size() == 3) |
| 984 | return nullptr; |
| 985 | |
| 986 | assert(NewNodes.size() == 2 && "Expected a load folding node!")(static_cast <bool> (NewNodes.size() == 2 && "Expected a load folding node!" ) ? void (0) : __assert_fail ("NewNodes.size() == 2 && \"Expected a load folding node!\"" , "/build/llvm-toolchain-snapshot-7~svn329677/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp" , 986, __extension__ __PRETTY_FUNCTION__)); |
| 987 | |
| 988 | N = NewNodes[1]; |
| 989 | SDNode *LoadNode = NewNodes[0]; |
| 990 | unsigned NumVals = N->getNumValues(); |
| 991 | unsigned OldNumVals = SU->getNode()->getNumValues(); |
| 992 | |
| 993 | // LoadNode may already exist. This can happen when there is another |
| 994 | // load from the same location and producing the same type of value |
| 995 | // but it has different alignment or volatileness. |
| 996 | bool isNewLoad = true; |
| 997 | SUnit *LoadSU; |
| 998 | if (LoadNode->getNodeId() != -1) { |
| 999 | LoadSU = &SUnits[LoadNode->getNodeId()]; |
| 1000 | // If LoadSU has already been scheduled, we should clone it but |
| 1001 | // this would negate the benefit to unfolding so just return SU. |
| 1002 | if (LoadSU->isScheduled) |
| 1003 | return SU; |
| 1004 | isNewLoad = false; |
| 1005 | } else { |
| 1006 | LoadSU = CreateNewSUnit(LoadNode); |
| 1007 | LoadNode->setNodeId(LoadSU->NodeNum); |
| 1008 | |
| 1009 | InitNumRegDefsLeft(LoadSU); |
| 1010 | computeLatency(LoadSU); |
| 1011 | } |
| 1012 | |
| 1013 | DEBUG(dbgs() << "Unfolding SU #" << SU->NodeNum << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType ("pre-RA-sched")) { dbgs() << "Unfolding SU #" << SU->NodeNum << "\n"; } } while (false); |
| 1014 | |
| 1015 | // Now that we are committed to unfolding replace DAG Uses. |
| 1016 | for (unsigned i = 0; i != NumVals; ++i) |
| 1017 | DAG->ReplaceAllUsesOfValueWith(SDValue(SU->getNode(), i), SDValue(N, i)); |
| 1018 | DAG->ReplaceAllUsesOfValueWith(SDValue(SU->getNode(), OldNumVals - 1), |
| 1019 | SDValue(LoadNode, 1)); |
| 1020 | |
| 1021 | SUnit *NewSU = CreateNewSUnit(N); |
| 1022 | assert(N->getNodeId() == -1 && "Node already inserted!")(static_cast <bool> (N->getNodeId() == -1 && "Node already inserted!") ? void (0) : __assert_fail ("N->getNodeId() == -1 && \"Node already inserted!\"" , "/build/llvm-toolchain-snapshot-7~svn329677/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp" , 1022, __extension__ __PRETTY_FUNCTION__)); |
| 1023 | N->setNodeId(NewSU->NodeNum); |
| 1024 | |
| 1025 | const MCInstrDesc &MCID = TII->get(N->getMachineOpcode()); |
| 1026 | for (unsigned i = 0; i != MCID.getNumOperands(); ++i) { |
| 1027 | if (MCID.getOperandConstraint(i, MCOI::TIED_TO) != -1) { |
| 1028 | NewSU->isTwoAddress = true; |
| 1029 | break; |
| 1030 | } |
| 1031 | } |
| 1032 | if (MCID.isCommutable()) |
| 1033 | NewSU->isCommutable = true; |
| 1034 | |
| 1035 | InitNumRegDefsLeft(NewSU); |
| 1036 | computeLatency(NewSU); |
| 1037 | |
| 1038 | // Record all the edges to and from the old SU, by category. |
| 1039 | SmallVector<SDep, 4> ChainPreds; |
| 1040 | SmallVector<SDep, 4> ChainSuccs; |
| 1041 | SmallVector<SDep, 4> LoadPreds; |
| 1042 | SmallVector<SDep, 4> NodePreds; |
| 1043 | SmallVector<SDep, 4> NodeSuccs; |
| 1044 | for (SDep &Pred : SU->Preds) { |
| 1045 | if (Pred.isCtrl()) |
| 1046 | ChainPreds.push_back(Pred); |
| 1047 | else if (isOperandOf(Pred.getSUnit(), LoadNode)) |
| 1048 | LoadPreds.push_back(Pred); |
| 1049 | else |
| 1050 | NodePreds.push_back(Pred); |
| 1051 | } |
| 1052 | for (SDep &Succ : SU->Succs) { |
| 1053 | if (Succ.isCtrl()) |
| 1054 | ChainSuccs.push_back(Succ); |
| 1055 | else |
| 1056 | NodeSuccs.push_back(Succ); |
| 1057 | } |
| 1058 | |
| 1059 | // Now assign edges to the newly-created nodes. |
| 1060 | for (const SDep &Pred : ChainPreds) { |
| 1061 | RemovePred(SU, Pred); |
| 1062 | if (isNewLoad) |
| 1063 | AddPred(LoadSU, Pred); |
| 1064 | } |
| 1065 | for (const SDep &Pred : LoadPreds) { |
| 1066 | RemovePred(SU, Pred); |
| 1067 | if (isNewLoad) |
| 1068 | AddPred(LoadSU, Pred); |
| 1069 | } |
| 1070 | for (const SDep &Pred : NodePreds) { |
| 1071 | RemovePred(SU, Pred); |
| 1072 | AddPred(NewSU, Pred); |
| 1073 | } |
| 1074 | for (SDep D : NodeSuccs) { |
| 1075 | SUnit *SuccDep = D.getSUnit(); |
| 1076 | D.setSUnit(SU); |
| 1077 | RemovePred(SuccDep, D); |
| 1078 | D.setSUnit(NewSU); |
| 1079 | AddPred(SuccDep, D); |
| 1080 | // Balance register pressure. |
| 1081 | if (AvailableQueue->tracksRegPressure() && SuccDep->isScheduled && |
| 1082 | !D.isCtrl() && NewSU->NumRegDefsLeft > 0) |
| 1083 | --NewSU->NumRegDefsLeft; |
| 1084 | } |
| 1085 | for (SDep D : ChainSuccs) { |
| 1086 | SUnit *SuccDep = D.getSUnit(); |
| 1087 | D.setSUnit(SU); |
| 1088 | RemovePred(SuccDep, D); |
| 1089 | if (isNewLoad) { |
| 1090 | D.setSUnit(LoadSU); |
| 1091 | AddPred(SuccDep, D); |
| 1092 | } |
| 1093 | } |
| 1094 | |
| 1095 | // Add a data dependency to reflect that NewSU reads the value defined |
| 1096 | // by LoadSU. |
| 1097 | SDep D(LoadSU, SDep::Data, 0); |
| 1098 | D.setLatency(LoadSU->Latency); |
| 1099 | AddPred(NewSU, D); |
| 1100 | |
| 1101 | if (isNewLoad) |
| 1102 | AvailableQueue->addNode(LoadSU); |
| 1103 | AvailableQueue->addNode(NewSU); |
| 1104 | |
| 1105 | ++NumUnfolds; |
| 1106 | |
| 1107 | if (NewSU->NumSuccsLeft == 0) |
| 1108 | NewSU->isAvailable = true; |
| 1109 | |
| 1110 | return NewSU; |
| 1111 | } |
| 1112 | |
| 1113 | /// CopyAndMoveSuccessors - Clone the specified node and move its scheduled |
| 1114 | /// successors to the newly created node. |
| 1115 | SUnit *ScheduleDAGRRList::CopyAndMoveSuccessors(SUnit *SU) { |
| 1116 | SDNode *N = SU->getNode(); |
| 1117 | if (!N) |
| 1118 | return nullptr; |
| 1119 | |
| 1120 | DEBUG(dbgs() << "Considering duplicating the SU\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType ("pre-RA-sched")) { dbgs() << "Considering duplicating the SU\n" ; } } while (false); |
| 1121 | DEBUG(SU->dump(this))do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType ("pre-RA-sched")) { SU->dump(this); } } while (false); |
| 1122 | |
| 1123 | if (N->getGluedNode() && |
| 1124 | !TII->canCopyGluedNodeDuringSchedule(N)) { |
| 1125 | DEBUG(dbgs()do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType ("pre-RA-sched")) { dbgs() << "Giving up because it has incoming glue and the target does not " "want to copy it\n"; } } while (false) |
| 1126 | << "Giving up because it has incoming glue and the target does not "do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType ("pre-RA-sched")) { dbgs() << "Giving up because it has incoming glue and the target does not " "want to copy it\n"; } } while (false) |
| 1127 | "want to copy it\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType ("pre-RA-sched")) { dbgs() << "Giving up because it has incoming glue and the target does not " "want to copy it\n"; } } while (false); |
| 1128 | return nullptr; |
| 1129 | } |
| 1130 | |
| 1131 | SUnit *NewSU; |
| 1132 | bool TryUnfold = false; |
| 1133 | for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) { |
| 1134 | MVT VT = N->getSimpleValueType(i); |
| 1135 | if (VT == MVT::Glue) { |
| 1136 | DEBUG(dbgs() << "Giving up because it has outgoing glue\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType ("pre-RA-sched")) { dbgs() << "Giving up because it has outgoing glue\n" ; } } while (false); |
| 1137 | return nullptr; |
| 1138 | } else if (VT == MVT::Other) |
| 1139 | TryUnfold = true; |
| 1140 | } |
| 1141 | for (const SDValue &Op : N->op_values()) { |
| 1142 | MVT VT = Op.getNode()->getSimpleValueType(Op.getResNo()); |
| 1143 | if (VT == MVT::Glue && !TII->canCopyGluedNodeDuringSchedule(N)) { |
| 1144 | DEBUG(dbgs() << "Giving up because it one of the operands is glue and "do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType ("pre-RA-sched")) { dbgs() << "Giving up because it one of the operands is glue and " "the target does not want to copy it\n"; } } while (false) |
| 1145 | "the target does not want to copy it\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType ("pre-RA-sched")) { dbgs() << "Giving up because it one of the operands is glue and " "the target does not want to copy it\n"; } } while (false); |
| 1146 | return nullptr; |
| 1147 | } |
| 1148 | } |
| 1149 | |
| 1150 | // If possible unfold instruction. |
| 1151 | if (TryUnfold) { |
| 1152 | SUnit *UnfoldSU = TryUnfoldSU(SU); |
| 1153 | if (!UnfoldSU) |
| 1154 | return nullptr; |
| 1155 | SU = UnfoldSU; |
| 1156 | N = SU->getNode(); |
Value stored to 'N' is never read | |
| 1157 | // If this can be scheduled don't bother duplicating and just return |
| 1158 | if (SU->NumSuccsLeft == 0) |
| 1159 | return SU; |
| 1160 | } |
| 1161 | |
| 1162 | DEBUG(dbgs() << " Duplicating SU #" << SU->NodeNum << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType ("pre-RA-sched")) { dbgs() << " Duplicating SU #" << SU->NodeNum << "\n"; } } while (false); |
| 1163 | NewSU = CreateClone(SU); |
| 1164 | |
| 1165 | // New SUnit has the exact same predecessors. |
| 1166 | for (SDep &Pred : SU->Preds) |
| 1167 | if (!Pred.isArtificial()) |
| 1168 | AddPred(NewSU, Pred); |
| 1169 | |
| 1170 | // Only copy scheduled successors. Cut them from old node's successor |
| 1171 | // list and move them over. |
| 1172 | SmallVector<std::pair<SUnit *, SDep>, 4> DelDeps; |
| 1173 | for (SDep &Succ : SU->Succs) { |
| 1174 | if (Succ.isArtificial()) |
| 1175 | continue; |
| 1176 | SUnit *SuccSU = Succ.getSUnit(); |
| 1177 | if (SuccSU->isScheduled) { |
| 1178 | SDep D = Succ; |
| 1179 | D.setSUnit(NewSU); |
| 1180 | AddPred(SuccSU, D); |
| 1181 | D.setSUnit(SU); |
| 1182 | DelDeps.push_back(std::make_pair(SuccSU, D)); |
| 1183 | } |
| 1184 | } |
| 1185 | for (auto &DelDep : DelDeps) |
| 1186 | RemovePred(DelDep.first, DelDep.second); |
| 1187 | |
| 1188 | AvailableQueue->updateNode(SU); |
| 1189 | AvailableQueue->addNode(NewSU); |
| 1190 | |
| 1191 | ++NumDups; |
| 1192 | return NewSU; |
| 1193 | } |
| 1194 | |
| 1195 | /// InsertCopiesAndMoveSuccs - Insert register copies and move all |
| 1196 | /// scheduled successors of the given SUnit to the last copy. |
| 1197 | void ScheduleDAGRRList::InsertCopiesAndMoveSuccs(SUnit *SU, unsigned Reg, |
| 1198 | const TargetRegisterClass *DestRC, |
| 1199 | const TargetRegisterClass *SrcRC, |
| 1200 | SmallVectorImpl<SUnit*> &Copies) { |
| 1201 | SUnit *CopyFromSU = CreateNewSUnit(nullptr); |
| 1202 | CopyFromSU->CopySrcRC = SrcRC; |
| 1203 | CopyFromSU->CopyDstRC = DestRC; |
| 1204 | |
| 1205 | SUnit *CopyToSU = CreateNewSUnit(nullptr); |
| 1206 | CopyToSU->CopySrcRC = DestRC; |
| 1207 | CopyToSU->CopyDstRC = SrcRC; |
| 1208 | |
| 1209 | // Only copy scheduled successors. Cut them from old node's successor |
| 1210 | // list and move them over. |
| 1211 | SmallVector<std::pair<SUnit *, SDep>, 4> DelDeps; |
| 1212 | for (SDep &Succ : SU->Succs) { |
| 1213 | if (Succ.isArtificial()) |
| 1214 | continue; |
| 1215 | SUnit *SuccSU = Succ.getSUnit(); |
| 1216 | if (SuccSU->isScheduled) { |
| 1217 | SDep D = Succ; |
| 1218 | D.setSUnit(CopyToSU); |
| 1219 | AddPred(SuccSU, D); |
| 1220 | DelDeps.push_back(std::make_pair(SuccSU, Succ)); |
| 1221 | } |
| 1222 | else { |
| 1223 | // Avoid scheduling the def-side copy before other successors. Otherwise |
| 1224 | // we could introduce another physreg interference on the copy and |
| 1225 | // continue inserting copies indefinitely. |
| 1226 | AddPred(SuccSU, SDep(CopyFromSU, SDep::Artificial)); |
| 1227 | } |
| 1228 | } |
| 1229 | for (auto &DelDep : DelDeps) |
| 1230 | RemovePred(DelDep.first, DelDep.second); |
| 1231 | |
| 1232 | SDep FromDep(SU, SDep::Data, Reg); |
| 1233 | FromDep.setLatency(SU->Latency); |
| 1234 | AddPred(CopyFromSU, FromDep); |
| 1235 | SDep ToDep(CopyFromSU, SDep::Data, 0); |
| 1236 | ToDep.setLatency(CopyFromSU->Latency); |
| 1237 | AddPred(CopyToSU, ToDep); |
| 1238 | |
| 1239 | AvailableQueue->updateNode(SU); |
| 1240 | AvailableQueue->addNode(CopyFromSU); |
| 1241 | AvailableQueue->addNode(CopyToSU); |
| 1242 | Copies.push_back(CopyFromSU); |
| 1243 | Copies.push_back(CopyToSU); |
| 1244 | |
| 1245 | ++NumPRCopies; |
| 1246 | } |
| 1247 | |
| 1248 | /// getPhysicalRegisterVT - Returns the ValueType of the physical register |
| 1249 | /// definition of the specified node. |
| 1250 | /// FIXME: Move to SelectionDAG? |
| 1251 | static MVT getPhysicalRegisterVT(SDNode *N, unsigned Reg, |
| 1252 | const TargetInstrInfo *TII) { |
| 1253 | unsigned NumRes; |
| 1254 | if (N->getOpcode() == ISD::CopyFromReg) { |
| 1255 | // CopyFromReg has: "chain, Val, glue" so operand 1 gives the type. |
| 1256 | NumRes = 1; |
| 1257 | } else { |
| 1258 | const MCInstrDesc &MCID = TII->get(N->getMachineOpcode()); |
| 1259 | assert(MCID.ImplicitDefs && "Physical reg def must be in implicit def list!")(static_cast <bool> (MCID.ImplicitDefs && "Physical reg def must be in implicit def list!" ) ? void (0) : __assert_fail ("MCID.ImplicitDefs && \"Physical reg def must be in implicit def list!\"" , "/build/llvm-toolchain-snapshot-7~svn329677/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp" , 1259, __extension__ __PRETTY_FUNCTION__)); |
| 1260 | NumRes = MCID.getNumDefs(); |
| 1261 | for (const MCPhysReg *ImpDef = MCID.getImplicitDefs(); *ImpDef; ++ImpDef) { |
| 1262 | if (Reg == *ImpDef) |
| 1263 | break; |
| 1264 | ++NumRes; |
| 1265 | } |
| 1266 | } |
| 1267 | return N->getSimpleValueType(NumRes); |
| 1268 | } |
| 1269 | |
| 1270 | /// CheckForLiveRegDef - Return true and update live register vector if the |
| 1271 | /// specified register def of the specified SUnit clobbers any "live" registers. |
| 1272 | static void CheckForLiveRegDef(SUnit *SU, unsigned Reg, |
| 1273 | SUnit **LiveRegDefs, |
| 1274 | SmallSet<unsigned, 4> &RegAdded, |
| 1275 | SmallVectorImpl<unsigned> &LRegs, |
| 1276 | const TargetRegisterInfo *TRI) { |
| 1277 | for (MCRegAliasIterator AliasI(Reg, TRI, true); AliasI.isValid(); ++AliasI) { |
| 1278 | |
| 1279 | // Check if Ref is live. |
| 1280 | if (!LiveRegDefs[*AliasI]) continue; |
| 1281 | |
| 1282 | // Allow multiple uses of the same def. |
| 1283 | if (LiveRegDefs[*AliasI] == SU) continue; |
| 1284 | |
| 1285 | // Add Reg to the set of interfering live regs. |
| 1286 | if (RegAdded.insert(*AliasI).second) { |
| 1287 | LRegs.push_back(*AliasI); |
| 1288 | } |
| 1289 | } |
| 1290 | } |
| 1291 | |
| 1292 | /// CheckForLiveRegDefMasked - Check for any live physregs that are clobbered |
| 1293 | /// by RegMask, and add them to LRegs. |
| 1294 | static void CheckForLiveRegDefMasked(SUnit *SU, const uint32_t *RegMask, |
| 1295 | ArrayRef<SUnit*> LiveRegDefs, |
| 1296 | SmallSet<unsigned, 4> &RegAdded, |
| 1297 | SmallVectorImpl<unsigned> &LRegs) { |
| 1298 | // Look at all live registers. Skip Reg0 and the special CallResource. |
| 1299 | for (unsigned i = 1, e = LiveRegDefs.size()-1; i != e; ++i) { |
| 1300 | if (!LiveRegDefs[i]) continue; |
| 1301 | if (LiveRegDefs[i] == SU) continue; |
| 1302 | if (!MachineOperand::clobbersPhysReg(RegMask, i)) continue; |
| 1303 | if (RegAdded.insert(i).second) |
| 1304 | LRegs.push_back(i); |
| 1305 | } |
| 1306 | } |
| 1307 | |
| 1308 | /// getNodeRegMask - Returns the register mask attached to an SDNode, if any. |
| 1309 | static const uint32_t *getNodeRegMask(const SDNode *N) { |
| 1310 | for (const SDValue &Op : N->op_values()) |
| 1311 | if (const auto *RegOp = dyn_cast<RegisterMaskSDNode>(Op.getNode())) |
| 1312 | return RegOp->getRegMask(); |
| 1313 | return nullptr; |
| 1314 | } |
| 1315 | |
| 1316 | /// DelayForLiveRegsBottomUp - Returns true if it is necessary to delay |
| 1317 | /// scheduling of the given node to satisfy live physical register dependencies. |
| 1318 | /// If the specific node is the last one that's available to schedule, do |
| 1319 | /// whatever is necessary (i.e. backtracking or cloning) to make it possible. |
| 1320 | bool ScheduleDAGRRList:: |
| 1321 | DelayForLiveRegsBottomUp(SUnit *SU, SmallVectorImpl<unsigned> &LRegs) { |
| 1322 | if (NumLiveRegs == 0) |
| 1323 | return false; |
| 1324 | |
| 1325 | SmallSet<unsigned, 4> RegAdded; |
| 1326 | // If this node would clobber any "live" register, then it's not ready. |
| 1327 | // |
| 1328 | // If SU is the currently live definition of the same register that it uses, |
| 1329 | // then we are free to schedule it. |
| 1330 | for (SDep &Pred : SU->Preds) { |
| 1331 | if (Pred.isAssignedRegDep() && LiveRegDefs[Pred.getReg()] != SU) |
| 1332 | CheckForLiveRegDef(Pred.getSUnit(), Pred.getReg(), LiveRegDefs.get(), |
| 1333 | RegAdded, LRegs, TRI); |
| 1334 | } |
| 1335 | |
| 1336 | for (SDNode *Node = SU->getNode(); Node; Node = Node->getGluedNode()) { |
| 1337 | if (Node->getOpcode() == ISD::INLINEASM) { |
| 1338 | // Inline asm can clobber physical defs. |
| 1339 | unsigned NumOps = Node->getNumOperands(); |
| 1340 | if (Node->getOperand(NumOps-1).getValueType() == MVT::Glue) |
| 1341 | --NumOps; // Ignore the glue operand. |
| 1342 | |
| 1343 | for (unsigned i = InlineAsm::Op_FirstOperand; i != NumOps;) { |
| 1344 | unsigned Flags = |
| 1345 | cast<ConstantSDNode>(Node->getOperand(i))->getZExtValue(); |
| 1346 | unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags); |
| 1347 | |
| 1348 | ++i; // Skip the ID value. |
| 1349 | if (InlineAsm::isRegDefKind(Flags) || |
| 1350 | InlineAsm::isRegDefEarlyClobberKind(Flags) || |
| 1351 | InlineAsm::isClobberKind(Flags)) { |
| 1352 | // Check for def of register or earlyclobber register. |
| 1353 | for (; NumVals; --NumVals, ++i) { |
| 1354 | unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg(); |
| 1355 | if (TargetRegisterInfo::isPhysicalRegister(Reg)) |
| 1356 | CheckForLiveRegDef(SU, Reg, LiveRegDefs.get(), RegAdded, LRegs, TRI); |
| 1357 | } |
| 1358 | } else |
| 1359 | i += NumVals; |
| 1360 | } |
| 1361 | continue; |
| 1362 | } |
| 1363 | |
| 1364 | if (!Node->isMachineOpcode()) |
| 1365 | continue; |
| 1366 | // If we're in the middle of scheduling a call, don't begin scheduling |
| 1367 | // another call. Also, don't allow any physical registers to be live across |
| 1368 | // the call. |
| 1369 | if (Node->getMachineOpcode() == TII->getCallFrameDestroyOpcode()) { |
| 1370 | // Check the special calling-sequence resource. |
| 1371 | unsigned CallResource = TRI->getNumRegs(); |
| 1372 | if (LiveRegDefs[CallResource]) { |
| 1373 | SDNode *Gen = LiveRegGens[CallResource]->getNode(); |
| 1374 | while (SDNode *Glued = Gen->getGluedNode()) |
| 1375 | Gen = Glued; |
| 1376 | if (!IsChainDependent(Gen, Node, 0, TII) && |
| 1377 | RegAdded.insert(CallResource).second) |
| 1378 | LRegs.push_back(CallResource); |
| 1379 | } |
| 1380 | } |
| 1381 | if (const uint32_t *RegMask = getNodeRegMask(Node)) |
| 1382 | CheckForLiveRegDefMasked(SU, RegMask, |
| 1383 | makeArrayRef(LiveRegDefs.get(), TRI->getNumRegs()), |
| 1384 | RegAdded, LRegs); |
| 1385 | |
| 1386 | const MCInstrDesc &MCID = TII->get(Node->getMachineOpcode()); |
| 1387 | if (MCID.hasOptionalDef()) { |
| 1388 | // Most ARM instructions have an OptionalDef for CPSR, to model the S-bit. |
| 1389 | // This operand can be either a def of CPSR, if the S bit is set; or a use |
| 1390 | // of %noreg. When the OptionalDef is set to a valid register, we need to |
| 1391 | // handle it in the same way as an ImplicitDef. |
| 1392 | for (unsigned i = 0; i < MCID.getNumDefs(); ++i) |
| 1393 | if (MCID.OpInfo[i].isOptionalDef()) { |
| 1394 | const SDValue &OptionalDef = Node->getOperand(i - Node->getNumValues()); |
| 1395 | unsigned Reg = cast<RegisterSDNode>(OptionalDef)->getReg(); |
| 1396 | CheckForLiveRegDef(SU, Reg, LiveRegDefs.get(), RegAdded, LRegs, TRI); |
| 1397 | } |
| 1398 | } |
| 1399 | if (!MCID.ImplicitDefs) |
| 1400 | continue; |
| 1401 | for (const MCPhysReg *Reg = MCID.getImplicitDefs(); *Reg; ++Reg) |
| 1402 | CheckForLiveRegDef(SU, *Reg, LiveRegDefs.get(), RegAdded, LRegs, TRI); |
| 1403 | } |
| 1404 | |
| 1405 | return !LRegs.empty(); |
| 1406 | } |
| 1407 | |
| 1408 | void ScheduleDAGRRList::releaseInterferences(unsigned Reg) { |
| 1409 | // Add the nodes that aren't ready back onto the available list. |
| 1410 | for (unsigned i = Interferences.size(); i > 0; --i) { |
| 1411 | SUnit *SU = Interferences[i-1]; |
| 1412 | LRegsMapT::iterator LRegsPos = LRegsMap.find(SU); |
| 1413 | if (Reg) { |
| 1414 | SmallVectorImpl<unsigned> &LRegs = LRegsPos->second; |
| 1415 | if (!is_contained(LRegs, Reg)) |
| 1416 | continue; |
| 1417 | } |
| 1418 | SU->isPending = false; |
| 1419 | // The interfering node may no longer be available due to backtracking. |
| 1420 | // Furthermore, it may have been made available again, in which case it is |
| 1421 | // now already in the AvailableQueue. |
| 1422 | if (SU->isAvailable && !SU->NodeQueueId) { |
| 1423 | DEBUG(dbgs() << " Repushing SU #" << SU->NodeNum << '\n')do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType ("pre-RA-sched")) { dbgs() << " Repushing SU #" << SU->NodeNum << '\n'; } } while (false); |
| 1424 | AvailableQueue->push(SU); |
| 1425 | } |
| 1426 | if (i < Interferences.size()) |
| 1427 | Interferences[i-1] = Interferences.back(); |
| 1428 | Interferences.pop_back(); |
| 1429 | LRegsMap.erase(LRegsPos); |
| 1430 | } |
| 1431 | } |
| 1432 | |
| 1433 | /// Return a node that can be scheduled in this cycle. Requirements: |
| 1434 | /// (1) Ready: latency has been satisfied |
| 1435 | /// (2) No Hazards: resources are available |
| 1436 | /// (3) No Interferences: may unschedule to break register interferences. |
| 1437 | SUnit *ScheduleDAGRRList::PickNodeToScheduleBottomUp() { |
| 1438 | SUnit *CurSU = AvailableQueue->empty() ? nullptr : AvailableQueue->pop(); |
| 1439 | auto FindAvailableNode = [&]() { |
| 1440 | while (CurSU) { |
| 1441 | SmallVector<unsigned, 4> LRegs; |
| 1442 | if (!DelayForLiveRegsBottomUp(CurSU, LRegs)) |
| 1443 | break; |
| 1444 | DEBUG(dbgs() << " Interfering reg ";do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType ("pre-RA-sched")) { dbgs() << " Interfering reg "; if (LRegs[0] == TRI->getNumRegs()) dbgs() << "CallResource" ; else dbgs() << printReg(LRegs[0], TRI); dbgs() << " SU #" << CurSU->NodeNum << '\n'; } } while ( false) |
| 1445 | if (LRegs[0] == TRI->getNumRegs())do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType ("pre-RA-sched")) { dbgs() << " Interfering reg "; if (LRegs[0] == TRI->getNumRegs()) dbgs() << "CallResource" ; else dbgs() << printReg(LRegs[0], TRI); dbgs() << " SU #" << CurSU->NodeNum << '\n'; } } while ( false) |
| 1446 | dbgs() << "CallResource";do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType ("pre-RA-sched")) { dbgs() << " Interfering reg "; if (LRegs[0] == TRI->getNumRegs()) dbgs() << "CallResource" ; else dbgs() << printReg(LRegs[0], TRI); dbgs() << " SU #" << CurSU->NodeNum << '\n'; } } while ( false) |
| 1447 | elsedo { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType ("pre-RA-sched")) { dbgs() << " Interfering reg "; if (LRegs[0] == TRI->getNumRegs()) dbgs() << "CallResource" ; else dbgs() << printReg(LRegs[0], TRI); dbgs() << " SU #" << CurSU->NodeNum << '\n'; } } while ( false) |
| 1448 | dbgs() << printReg(LRegs[0], TRI);do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType ("pre-RA-sched")) { dbgs() << " Interfering reg "; if (LRegs[0] == TRI->getNumRegs()) dbgs() << "CallResource" ; else dbgs() << printReg(LRegs[0], TRI); dbgs() << " SU #" << CurSU->NodeNum << '\n'; } } while ( false) |
| 1449 | dbgs() << " SU #" << CurSU->NodeNum << '\n')do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType ("pre-RA-sched")) { dbgs() << " Interfering reg "; if (LRegs[0] == TRI->getNumRegs()) dbgs() << "CallResource" ; else dbgs() << printReg(LRegs[0], TRI); dbgs() << " SU #" << CurSU->NodeNum << '\n'; } } while ( false); |
| 1450 | std::pair<LRegsMapT::iterator, bool> LRegsPair = |
| 1451 | LRegsMap.insert(std::make_pair(CurSU, LRegs)); |
| 1452 | if (LRegsPair.second) { |
| 1453 | CurSU->isPending = true; // This SU is not in AvailableQueue right now. |
| 1454 | Interferences.push_back(CurSU); |
| 1455 | } |
| 1456 | else { |
| 1457 | assert(CurSU->isPending && "Interferences are pending")(static_cast <bool> (CurSU->isPending && "Interferences are pending" ) ? void (0) : __assert_fail ("CurSU->isPending && \"Interferences are pending\"" , "/build/llvm-toolchain-snapshot-7~svn329677/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp" , 1457, __extension__ __PRETTY_FUNCTION__)); |
| 1458 | // Update the interference with current live regs. |
| 1459 | LRegsPair.first->second = LRegs; |
| 1460 | } |
| 1461 | CurSU = AvailableQueue->pop(); |
| 1462 | } |
| 1463 | }; |
| 1464 | FindAvailableNode(); |
| 1465 | if (CurSU) |
| 1466 | return CurSU; |
| 1467 | |
| 1468 | // All candidates are delayed due to live physical reg dependencies. |
| 1469 | // Try backtracking, code duplication, or inserting cross class copies |
| 1470 | // to resolve it. |
| 1471 | for (SUnit *TrySU : Interferences) { |
| 1472 | SmallVectorImpl<unsigned> &LRegs = LRegsMap[TrySU]; |
| 1473 | |
| 1474 | // Try unscheduling up to the point where it's safe to schedule |
| 1475 | // this node. |
| 1476 | SUnit *BtSU = nullptr; |
| 1477 | unsigned LiveCycle = std::numeric_limits<unsigned>::max(); |
| 1478 | for (unsigned Reg : LRegs) { |
| 1479 | if (LiveRegGens[Reg]->getHeight() < LiveCycle) { |
| 1480 | BtSU = LiveRegGens[Reg]; |
| 1481 | LiveCycle = BtSU->getHeight(); |
| 1482 | } |
| 1483 | } |
| 1484 | if (!WillCreateCycle(TrySU, BtSU)) { |
| 1485 | // BacktrackBottomUp mutates Interferences! |
| 1486 | BacktrackBottomUp(TrySU, BtSU); |
| 1487 | |
| 1488 | // Force the current node to be scheduled before the node that |
| 1489 | // requires the physical reg dep. |
| 1490 | if (BtSU->isAvailable) { |
| 1491 | BtSU->isAvailable = false; |
| 1492 | if (!BtSU->isPending) |
| 1493 | AvailableQueue->remove(BtSU); |
| 1494 | } |
| 1495 | DEBUG(dbgs() << "ARTIFICIAL edge from SU(" << BtSU->NodeNum << ") to SU("do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType ("pre-RA-sched")) { dbgs() << "ARTIFICIAL edge from SU(" << BtSU->NodeNum << ") to SU(" << TrySU ->NodeNum << ")\n"; } } while (false) |
| 1496 | << TrySU->NodeNum << ")\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType ("pre-RA-sched")) { dbgs() << "ARTIFICIAL edge from SU(" << BtSU->NodeNum << ") to SU(" << TrySU ->NodeNum << ")\n"; } } while (false); |
| 1497 | AddPred(TrySU, SDep(BtSU, SDep::Artificial)); |
| 1498 | |
| 1499 | // If one or more successors has been unscheduled, then the current |
| 1500 | // node is no longer available. |
| 1501 | if (!TrySU->isAvailable || !TrySU->NodeQueueId) { |
| 1502 | DEBUG(dbgs() << "TrySU not available; choosing node from queue\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType ("pre-RA-sched")) { dbgs() << "TrySU not available; choosing node from queue\n" ; } } while (false); |
| 1503 | CurSU = AvailableQueue->pop(); |
| 1504 | } else { |
| 1505 | DEBUG(dbgs() << "TrySU available\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType ("pre-RA-sched")) { dbgs() << "TrySU available\n"; } } while (false); |
| 1506 | // Available and in AvailableQueue |
| 1507 | AvailableQueue->remove(TrySU); |
| 1508 | CurSU = TrySU; |
| 1509 | } |
| 1510 | FindAvailableNode(); |
| 1511 | // Interferences has been mutated. We must break. |
| 1512 | break; |
| 1513 | } |
| 1514 | } |
| 1515 | |
| 1516 | if (!CurSU) { |
| 1517 | // Can't backtrack. If it's too expensive to copy the value, then try |
| 1518 | // duplicate the nodes that produces these "too expensive to copy" |
| 1519 | // values to break the dependency. In case even that doesn't work, |
| 1520 | // insert cross class copies. |
| 1521 | // If it's not too expensive, i.e. cost != -1, issue copies. |
| 1522 | SUnit *TrySU = Interferences[0]; |
| 1523 | SmallVectorImpl<unsigned> &LRegs = LRegsMap[TrySU]; |
| 1524 | assert(LRegs.size() == 1 && "Can't handle this yet!")(static_cast <bool> (LRegs.size() == 1 && "Can't handle this yet!" ) ? void (0) : __assert_fail ("LRegs.size() == 1 && \"Can't handle this yet!\"" , "/build/llvm-toolchain-snapshot-7~svn329677/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp" , 1524, __extension__ __PRETTY_FUNCTION__)); |
| 1525 | unsigned Reg = LRegs[0]; |
| 1526 | SUnit *LRDef = LiveRegDefs[Reg]; |
| 1527 | MVT VT = getPhysicalRegisterVT(LRDef->getNode(), Reg, TII); |
| 1528 | const TargetRegisterClass *RC = |
| 1529 | TRI->getMinimalPhysRegClass(Reg, VT); |
| 1530 | const TargetRegisterClass *DestRC = TRI->getCrossCopyRegClass(RC); |
| 1531 | |
| 1532 | // If cross copy register class is the same as RC, then it must be possible |
| 1533 | // copy the value directly. Do not try duplicate the def. |
| 1534 | // If cross copy register class is not the same as RC, then it's possible to |
| 1535 | // copy the value but it require cross register class copies and it is |
| 1536 | // expensive. |
| 1537 | // If cross copy register class is null, then it's not possible to copy |
| 1538 | // the value at all. |
| 1539 | SUnit *NewDef = nullptr; |
| 1540 | if (DestRC != RC) { |
| 1541 | NewDef = CopyAndMoveSuccessors(LRDef); |
| 1542 | if (!DestRC && !NewDef) |
| 1543 | report_fatal_error("Can't handle live physical register dependency!"); |
| 1544 | } |
| 1545 | if (!NewDef) { |
| 1546 | // Issue copies, these can be expensive cross register class copies. |
| 1547 | SmallVector<SUnit*, 2> Copies; |
| 1548 | InsertCopiesAndMoveSuccs(LRDef, Reg, DestRC, RC, Copies); |
| 1549 | DEBUG(dbgs() << " Adding an edge from SU #" << TrySU->NodeNumdo { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType ("pre-RA-sched")) { dbgs() << " Adding an edge from SU #" << TrySU->NodeNum << " to SU #" << Copies .front()->NodeNum << "\n"; } } while (false) |
| 1550 | << " to SU #" << Copies.front()->NodeNum << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType ("pre-RA-sched")) { dbgs() << " Adding an edge from SU #" << TrySU->NodeNum << " to SU #" << Copies .front()->NodeNum << "\n"; } } while (false); |
| 1551 | AddPred(TrySU, SDep(Copies.front(), SDep::Artificial)); |
| 1552 | NewDef = Copies.back(); |
| 1553 | } |
| 1554 | |
| 1555 | DEBUG(dbgs() << " Adding an edge from SU #" << NewDef->NodeNumdo { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType ("pre-RA-sched")) { dbgs() << " Adding an edge from SU #" << NewDef->NodeNum << " to SU #" << TrySU ->NodeNum << "\n"; } } while (false) |
| 1556 | << " to SU #" << TrySU->NodeNum << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType ("pre-RA-sched")) { dbgs() << " Adding an edge from SU #" << NewDef->NodeNum << " to SU #" << TrySU ->NodeNum << "\n"; } } while (false); |
| 1557 | LiveRegDefs[Reg] = NewDef; |
| 1558 | AddPred(NewDef, SDep(TrySU, SDep::Artificial)); |
| 1559 | TrySU->isAvailable = false; |
| 1560 | CurSU = NewDef; |
| 1561 | } |
| 1562 | assert(CurSU && "Unable to resolve live physical register dependencies!")(static_cast <bool> (CurSU && "Unable to resolve live physical register dependencies!" ) ? void (0) : __assert_fail ("CurSU && \"Unable to resolve live physical register dependencies!\"" , "/build/llvm-toolchain-snapshot-7~svn329677/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp" , 1562, __extension__ __PRETTY_FUNCTION__)); |
| 1563 | return CurSU; |
| 1564 | } |
| 1565 | |
| 1566 | /// ListScheduleBottomUp - The main loop of list scheduling for bottom-up |
| 1567 | /// schedulers. |
| 1568 | void ScheduleDAGRRList::ListScheduleBottomUp() { |
| 1569 | // Release any predecessors of the special Exit node. |
| 1570 | ReleasePredecessors(&ExitSU); |
| 1571 | |
| 1572 | // Add root to Available queue. |
| 1573 | if (!SUnits.empty()) { |
| 1574 | SUnit *RootSU = &SUnits[DAG->getRoot().getNode()->getNodeId()]; |
| 1575 | assert(RootSU->Succs.empty() && "Graph root shouldn't have successors!")(static_cast <bool> (RootSU->Succs.empty() && "Graph root shouldn't have successors!") ? void (0) : __assert_fail ("RootSU->Succs.empty() && \"Graph root shouldn't have successors!\"" , "/build/llvm-toolchain-snapshot-7~svn329677/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp" , 1575, __extension__ __PRETTY_FUNCTION__)); |
| 1576 | RootSU->isAvailable = true; |
| 1577 | AvailableQueue->push(RootSU); |
| 1578 | } |
| 1579 | |
| 1580 | // While Available queue is not empty, grab the node with the highest |
| 1581 | // priority. If it is not ready put it back. Schedule the node. |
| 1582 | Sequence.reserve(SUnits.size()); |
| 1583 | while (!AvailableQueue->empty() || !Interferences.empty()) { |
| 1584 | DEBUG(dbgs() << "\nExamining Available:\n";do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType ("pre-RA-sched")) { dbgs() << "\nExamining Available:\n" ; AvailableQueue->dump(this); } } while (false) |
| 1585 | AvailableQueue->dump(this))do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType ("pre-RA-sched")) { dbgs() << "\nExamining Available:\n" ; AvailableQueue->dump(this); } } while (false); |
| 1586 | |
| 1587 | // Pick the best node to schedule taking all constraints into |
| 1588 | // consideration. |
| 1589 | SUnit *SU = PickNodeToScheduleBottomUp(); |
| 1590 | |
| 1591 | AdvancePastStalls(SU); |
| 1592 | |
| 1593 | ScheduleNodeBottomUp(SU); |
| 1594 | |
| 1595 | while (AvailableQueue->empty() && !PendingQueue.empty()) { |
| 1596 | // Advance the cycle to free resources. Skip ahead to the next ready SU. |
| 1597 | assert(MinAvailableCycle < std::numeric_limits<unsigned>::max() &&(static_cast <bool> (MinAvailableCycle < std::numeric_limits <unsigned>::max() && "MinAvailableCycle uninitialized" ) ? void (0) : __assert_fail ("MinAvailableCycle < std::numeric_limits<unsigned>::max() && \"MinAvailableCycle uninitialized\"" , "/build/llvm-toolchain-snapshot-7~svn329677/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp" , 1598, __extension__ __PRETTY_FUNCTION__)) |
| 1598 | "MinAvailableCycle uninitialized")(static_cast <bool> (MinAvailableCycle < std::numeric_limits <unsigned>::max() && "MinAvailableCycle uninitialized" ) ? void (0) : __assert_fail ("MinAvailableCycle < std::numeric_limits<unsigned>::max() && \"MinAvailableCycle uninitialized\"" , "/build/llvm-toolchain-snapshot-7~svn329677/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp" , 1598, __extension__ __PRETTY_FUNCTION__)); |
| 1599 | AdvanceToCycle(std::max(CurCycle + 1, MinAvailableCycle)); |
| 1600 | } |
| 1601 | } |
| 1602 | |
| 1603 | // Reverse the order if it is bottom up. |
| 1604 | std::reverse(Sequence.begin(), Sequence.end()); |
| 1605 | |
| 1606 | #ifndef NDEBUG |
| 1607 | VerifyScheduledSequence(/*isBottomUp=*/true); |
| 1608 | #endif |
| 1609 | } |
| 1610 | |
| 1611 | namespace { |
| 1612 | |
| 1613 | class RegReductionPQBase; |
| 1614 | |
| 1615 | struct queue_sort { |
| 1616 | bool isReady(SUnit* SU, unsigned CurCycle) const { return true; } |
| 1617 | }; |
| 1618 | |
| 1619 | #ifndef NDEBUG |
| 1620 | template<class SF> |
| 1621 | struct reverse_sort : public queue_sort { |
| 1622 | SF &SortFunc; |
| 1623 | |
| 1624 | reverse_sort(SF &sf) : SortFunc(sf) {} |
| 1625 | |
| 1626 | bool operator()(SUnit* left, SUnit* right) const { |
| 1627 | // reverse left/right rather than simply !SortFunc(left, right) |
| 1628 | // to expose different paths in the comparison logic. |
| 1629 | return SortFunc(right, left); |
| 1630 | } |
| 1631 | }; |
| 1632 | #endif // NDEBUG |
| 1633 | |
| 1634 | /// bu_ls_rr_sort - Priority function for bottom up register pressure |
| 1635 | // reduction scheduler. |
| 1636 | struct bu_ls_rr_sort : public queue_sort { |
| 1637 | enum { |
| 1638 | IsBottomUp = true, |
| 1639 | HasReadyFilter = false |
| 1640 | }; |
| 1641 | |
| 1642 | RegReductionPQBase *SPQ; |
| 1643 | |
| 1644 | bu_ls_rr_sort(RegReductionPQBase *spq) : SPQ(spq) {} |
| 1645 | |
| 1646 | bool operator()(SUnit* left, SUnit* right) const; |
| 1647 | }; |
| 1648 | |
| 1649 | // src_ls_rr_sort - Priority function for source order scheduler. |
| 1650 | struct src_ls_rr_sort : public queue_sort { |
| 1651 | enum { |
| 1652 | IsBottomUp = true, |
| 1653 | HasReadyFilter = false |
| 1654 | }; |
| 1655 | |
| 1656 | RegReductionPQBase *SPQ; |
| 1657 | |
| 1658 | src_ls_rr_sort(RegReductionPQBase *spq) : SPQ(spq) {} |
| 1659 | |
| 1660 | bool operator()(SUnit* left, SUnit* right) const; |
| 1661 | }; |
| 1662 | |
| 1663 | // hybrid_ls_rr_sort - Priority function for hybrid scheduler. |
| 1664 | struct hybrid_ls_rr_sort : public queue_sort { |
| 1665 | enum { |
| 1666 | IsBottomUp = true, |
| 1667 | HasReadyFilter = false |
| 1668 | }; |
| 1669 | |
| 1670 | RegReductionPQBase *SPQ; |
| 1671 | |
| 1672 | hybrid_ls_rr_sort(RegReductionPQBase *spq) : SPQ(spq) {} |
| 1673 | |
| 1674 | bool isReady(SUnit *SU, unsigned CurCycle) const; |
| 1675 | |
| 1676 | bool operator()(SUnit* left, SUnit* right) const; |
| 1677 | }; |
| 1678 | |
| 1679 | // ilp_ls_rr_sort - Priority function for ILP (instruction level parallelism) |
| 1680 | // scheduler. |
| 1681 | struct ilp_ls_rr_sort : public queue_sort { |
| 1682 | enum { |
| 1683 | IsBottomUp = true, |
| 1684 | HasReadyFilter = false |
| 1685 | }; |
| 1686 | |
| 1687 | RegReductionPQBase *SPQ; |
| 1688 | |
| 1689 | ilp_ls_rr_sort(RegReductionPQBase *spq) : SPQ(spq) {} |
| 1690 | |
| 1691 | bool isReady(SUnit *SU, unsigned CurCycle) const; |
| 1692 | |
| 1693 | bool operator()(SUnit* left, SUnit* right) const; |
| 1694 | }; |
| 1695 | |
| 1696 | class RegReductionPQBase : public SchedulingPriorityQueue { |
| 1697 | protected: |
| 1698 | std::vector<SUnit *> Queue; |
| 1699 | unsigned CurQueueId = 0; |
| 1700 | bool TracksRegPressure; |
| 1701 | bool SrcOrder; |
| 1702 | |
| 1703 | // SUnits - The SUnits for the current graph. |
| 1704 | std::vector<SUnit> *SUnits; |
| 1705 | |
| 1706 | MachineFunction &MF; |
| 1707 | const TargetInstrInfo *TII; |
| 1708 | const TargetRegisterInfo *TRI; |
| 1709 | const TargetLowering *TLI; |
| 1710 | ScheduleDAGRRList *scheduleDAG = nullptr; |
| 1711 | |
| 1712 | // SethiUllmanNumbers - The SethiUllman number for each node. |
| 1713 | std::vector<unsigned> SethiUllmanNumbers; |
| 1714 | |
| 1715 | /// RegPressure - Tracking current reg pressure per register class. |
| 1716 | std::vector<unsigned> RegPressure; |
| 1717 | |
| 1718 | /// RegLimit - Tracking the number of allocatable registers per register |
| 1719 | /// class. |
| 1720 | std::vector<unsigned> RegLimit; |
| 1721 | |
| 1722 | public: |
| 1723 | RegReductionPQBase(MachineFunction &mf, |
| 1724 | bool hasReadyFilter, |
| 1725 | bool tracksrp, |
| 1726 | bool srcorder, |
| 1727 | const TargetInstrInfo *tii, |
| 1728 | const TargetRegisterInfo *tri, |
| 1729 | const TargetLowering *tli) |
| 1730 | : SchedulingPriorityQueue(hasReadyFilter), TracksRegPressure(tracksrp), |
| 1731 | SrcOrder(srcorder), MF(mf), TII(tii), TRI(tri), TLI(tli) { |
| 1732 | if (TracksRegPressure) { |
| 1733 | unsigned NumRC = TRI->getNumRegClasses(); |
| 1734 | RegLimit.resize(NumRC); |
| 1735 | RegPressure.resize(NumRC); |
| 1736 | std::fill(RegLimit.begin(), RegLimit.end(), 0); |
| 1737 | std::fill(RegPressure.begin(), RegPressure.end(), 0); |
| 1738 | for (const TargetRegisterClass *RC : TRI->regclasses()) |
| 1739 | RegLimit[RC->getID()] = tri->getRegPressureLimit(RC, MF); |
| 1740 | } |
| 1741 | } |
| 1742 | |
| 1743 | void setScheduleDAG(ScheduleDAGRRList *scheduleDag) { |
| 1744 | scheduleDAG = scheduleDag; |
| 1745 | } |
| 1746 | |
| 1747 | ScheduleHazardRecognizer* getHazardRec() { |
| 1748 | return scheduleDAG->getHazardRec(); |
| 1749 | } |
| 1750 | |
| 1751 | void initNodes(std::vector<SUnit> &sunits) override; |
| 1752 | |
| 1753 | void addNode(const SUnit *SU) override; |
| 1754 | |
| 1755 | void updateNode(const SUnit *SU) override; |
| 1756 | |
| 1757 | void releaseState() override { |
| 1758 | SUnits = nullptr; |
| 1759 | SethiUllmanNumbers.clear(); |
| 1760 | std::fill(RegPressure.begin(), RegPressure.end(), 0); |
| 1761 | } |
| 1762 | |
| 1763 | unsigned getNodePriority(const SUnit *SU) const; |
| 1764 | |
| 1765 | unsigned getNodeOrdering(const SUnit *SU) const { |
| 1766 | if (!SU->getNode()) return 0; |
| 1767 | |
| 1768 | return SU->getNode()->getIROrder(); |
| 1769 | } |
| 1770 | |
| 1771 | bool empty() const override { return Queue.empty(); } |
| 1772 | |
| 1773 | void push(SUnit *U) override { |
| 1774 | assert(!U->NodeQueueId && "Node in the queue already")(static_cast <bool> (!U->NodeQueueId && "Node in the queue already" ) ? void (0) : __assert_fail ("!U->NodeQueueId && \"Node in the queue already\"" , "/build/llvm-toolchain-snapshot-7~svn329677/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp" , 1774, __extension__ __PRETTY_FUNCTION__)); |
| 1775 | U->NodeQueueId = ++CurQueueId; |
| 1776 | Queue.push_back(U); |
| 1777 | } |
| 1778 | |
| 1779 | void remove(SUnit *SU) override { |
| 1780 | assert(!Queue.empty() && "Queue is empty!")(static_cast <bool> (!Queue.empty() && "Queue is empty!" ) ? void (0) : __assert_fail ("!Queue.empty() && \"Queue is empty!\"" , "/build/llvm-toolchain-snapshot-7~svn329677/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp" , 1780, __extension__ __PRETTY_FUNCTION__)); |
| 1781 | assert(SU->NodeQueueId != 0 && "Not in queue!")(static_cast <bool> (SU->NodeQueueId != 0 && "Not in queue!") ? void (0) : __assert_fail ("SU->NodeQueueId != 0 && \"Not in queue!\"" , "/build/llvm-toolchain-snapshot-7~svn329677/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp" , 1781, __extension__ __PRETTY_FUNCTION__)); |
| 1782 | std::vector<SUnit *>::iterator I = llvm::find(Queue, SU); |
| 1783 | if (I != std::prev(Queue.end())) |
| 1784 | std::swap(*I, Queue.back()); |
| 1785 | Queue.pop_back(); |
| 1786 | SU->NodeQueueId = 0; |
| 1787 | } |
| 1788 | |
| 1789 | bool tracksRegPressure() const override { return TracksRegPressure; } |
| 1790 | |
| 1791 | void dumpRegPressure() const; |
| 1792 | |
| 1793 | bool HighRegPressure(const SUnit *SU) const; |
| 1794 | |
| 1795 | bool MayReduceRegPressure(SUnit *SU) const; |
| 1796 | |
| 1797 | int RegPressureDiff(SUnit *SU, unsigned &LiveUses) const; |
| 1798 | |
| 1799 | void scheduledNode(SUnit *SU) override; |
| 1800 | |
| 1801 | void unscheduledNode(SUnit *SU) override; |
| 1802 | |
| 1803 | protected: |
| 1804 | bool canClobber(const SUnit *SU, const SUnit *Op); |
| 1805 | void AddPseudoTwoAddrDeps(); |
| 1806 | void PrescheduleNodesWithMultipleUses(); |
| 1807 | void CalculateSethiUllmanNumbers(); |
| 1808 | }; |
| 1809 | |
| 1810 | template<class SF> |
| 1811 | static SUnit *popFromQueueImpl(std::vector<SUnit *> &Q, SF &Picker) { |
| 1812 | std::vector<SUnit *>::iterator Best = Q.begin(); |
| 1813 | for (auto I = std::next(Q.begin()), E = Q.end(); I != E; ++I) |
| 1814 | if (Picker(*Best, *I)) |
| 1815 | Best = I; |
| 1816 | SUnit *V = *Best; |
| 1817 | if (Best != std::prev(Q.end())) |
| 1818 | std::swap(*Best, Q.back()); |
| 1819 | Q.pop_back(); |
| 1820 | return V; |
| 1821 | } |
| 1822 | |
| 1823 | template<class SF> |
| 1824 | SUnit *popFromQueue(std::vector<SUnit *> &Q, SF &Picker, ScheduleDAG *DAG) { |
| 1825 | #ifndef NDEBUG |
| 1826 | if (DAG->StressSched) { |
| 1827 | reverse_sort<SF> RPicker(Picker); |
| 1828 | return popFromQueueImpl(Q, RPicker); |
| 1829 | } |
| 1830 | #endif |
| 1831 | (void)DAG; |
| 1832 | return popFromQueueImpl(Q, Picker); |
| 1833 | } |
| 1834 | |
| 1835 | //===----------------------------------------------------------------------===// |
| 1836 | // RegReductionPriorityQueue Definition |
| 1837 | //===----------------------------------------------------------------------===// |
| 1838 | // |
| 1839 | // This is a SchedulingPriorityQueue that schedules using Sethi Ullman numbers |
| 1840 | // to reduce register pressure. |
| 1841 | // |
| 1842 | template<class SF> |
| 1843 | class RegReductionPriorityQueue : public RegReductionPQBase { |
| 1844 | SF Picker; |
| 1845 | |
| 1846 | public: |
| 1847 | RegReductionPriorityQueue(MachineFunction &mf, |
| 1848 | bool tracksrp, |
| 1849 | bool srcorder, |
| 1850 | const TargetInstrInfo *tii, |
| 1851 | const TargetRegisterInfo *tri, |
| 1852 | const TargetLowering *tli) |
| 1853 | : RegReductionPQBase(mf, SF::HasReadyFilter, tracksrp, srcorder, |
| 1854 | tii, tri, tli), |
| 1855 | Picker(this) {} |
| 1856 | |
| 1857 | bool isBottomUp() const override { return SF::IsBottomUp; } |
| 1858 | |
| 1859 | bool isReady(SUnit *U) const override { |
| 1860 | return Picker.HasReadyFilter && Picker.isReady(U, getCurCycle()); |
| 1861 | } |
| 1862 | |
| 1863 | SUnit *pop() override { |
| 1864 | if (Queue.empty()) return nullptr; |
| 1865 | |
| 1866 | SUnit *V = popFromQueue(Queue, Picker, scheduleDAG); |
| 1867 | V->NodeQueueId = 0; |
| 1868 | return V; |
| 1869 | } |
| 1870 | |
| 1871 | #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) |
| 1872 | LLVM_DUMP_METHOD__attribute__((noinline)) __attribute__((__used__)) void dump(ScheduleDAG *DAG) const override { |
| 1873 | // Emulate pop() without clobbering NodeQueueIds. |
| 1874 | std::vector<SUnit *> DumpQueue = Queue; |
| 1875 | SF DumpPicker = Picker; |
| 1876 | while (!DumpQueue.empty()) { |
| 1877 | SUnit *SU = popFromQueue(DumpQueue, DumpPicker, scheduleDAG); |
| 1878 | dbgs() << "Height " << SU->getHeight() << ": "; |
| 1879 | SU->dump(DAG); |
| 1880 | } |
| 1881 | } |
| 1882 | #endif |
| 1883 | }; |
| 1884 | |
| 1885 | using BURegReductionPriorityQueue = RegReductionPriorityQueue<bu_ls_rr_sort>; |
| 1886 | using SrcRegReductionPriorityQueue = RegReductionPriorityQueue<src_ls_rr_sort>; |
| 1887 | using HybridBURRPriorityQueue = RegReductionPriorityQueue<hybrid_ls_rr_sort>; |
| 1888 | using ILPBURRPriorityQueue = RegReductionPriorityQueue<ilp_ls_rr_sort>; |
| 1889 | |
| 1890 | } // end anonymous namespace |
| 1891 | |
| 1892 | //===----------------------------------------------------------------------===// |
| 1893 | // Static Node Priority for Register Pressure Reduction |
| 1894 | //===----------------------------------------------------------------------===// |
| 1895 | |
| 1896 | // Check for special nodes that bypass scheduling heuristics. |
| 1897 | // Currently this pushes TokenFactor nodes down, but may be used for other |
| 1898 | // pseudo-ops as well. |
| 1899 | // |
| 1900 | // Return -1 to schedule right above left, 1 for left above right. |
| 1901 | // Return 0 if no bias exists. |
| 1902 | static int checkSpecialNodes(const SUnit *left, const SUnit *right) { |
| 1903 | bool LSchedLow = left->isScheduleLow; |
| 1904 | bool RSchedLow = right->isScheduleLow; |
| 1905 | if (LSchedLow != RSchedLow) |
| 1906 | return LSchedLow < RSchedLow ? 1 : -1; |
| 1907 | return 0; |
| 1908 | } |
| 1909 | |
| 1910 | /// CalcNodeSethiUllmanNumber - Compute Sethi Ullman number. |
| 1911 | /// Smaller number is the higher priority. |
| 1912 | static unsigned |
| 1913 | CalcNodeSethiUllmanNumber(const SUnit *SU, std::vector<unsigned> &SUNumbers) { |
| 1914 | if (SUNumbers[SU->NodeNum] != 0) |
| 1915 | return SUNumbers[SU->NodeNum]; |
| 1916 | |
| 1917 | // Use WorkList to avoid stack overflow on excessively large IRs. |
| 1918 | struct WorkState { |
| 1919 | WorkState(const SUnit *SU) : SU(SU) {} |
| 1920 | const SUnit *SU; |
| 1921 | unsigned PredsProcessed = 0; |
| 1922 | }; |
| 1923 | |
| 1924 | SmallVector<WorkState, 16> WorkList; |
| 1925 | WorkList.push_back(SU); |
| 1926 | while (!WorkList.empty()) { |
| 1927 | auto &Temp = WorkList.back(); |
| 1928 | auto *TempSU = Temp.SU; |
| 1929 | bool AllPredsKnown = true; |
| 1930 | // Try to find a non-evaluated pred and push it into the processing stack. |
| 1931 | for (unsigned P = Temp.PredsProcessed; P < TempSU->Preds.size(); ++P) { |
| 1932 | auto &Pred = TempSU->Preds[P]; |
| 1933 | if (Pred.isCtrl()) continue; // ignore chain preds |
| 1934 | SUnit *PredSU = Pred.getSUnit(); |
| 1935 | if (SUNumbers[PredSU->NodeNum] == 0) { |
| 1936 | #ifndef NDEBUG |
| 1937 | // In debug mode, check that we don't have such element in the stack. |
| 1938 | for (auto It : WorkList) |
| 1939 | assert(It.SU != PredSU && "Trying to push an element twice?")(static_cast <bool> (It.SU != PredSU && "Trying to push an element twice?" ) ? void (0) : __assert_fail ("It.SU != PredSU && \"Trying to push an element twice?\"" , "/build/llvm-toolchain-snapshot-7~svn329677/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp" , 1939, __extension__ __PRETTY_FUNCTION__)); |
| 1940 | #endif |
| 1941 | // Next time start processing this one starting from the next pred. |
| 1942 | Temp.PredsProcessed = P + 1; |
| 1943 | WorkList.push_back(PredSU); |
| 1944 | AllPredsKnown = false; |
| 1945 | break; |
| 1946 | } |
| 1947 | } |
| 1948 | |
| 1949 | if (!AllPredsKnown) |
| 1950 | continue; |
| 1951 | |
| 1952 | // Once all preds are known, we can calculate the answer for this one. |
| 1953 | unsigned SethiUllmanNumber = 0; |
| 1954 | unsigned Extra = 0; |
| 1955 | for (const SDep &Pred : TempSU->Preds) { |
| 1956 | if (Pred.isCtrl()) continue; // ignore chain preds |
| 1957 | SUnit *PredSU = Pred.getSUnit(); |
| 1958 | unsigned PredSethiUllman = SUNumbers[PredSU->NodeNum]; |
| 1959 | assert(PredSethiUllman > 0 && "We should have evaluated this pred!")(static_cast <bool> (PredSethiUllman > 0 && "We should have evaluated this pred!" ) ? void (0) : __assert_fail ("PredSethiUllman > 0 && \"We should have evaluated this pred!\"" , "/build/llvm-toolchain-snapshot-7~svn329677/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp" , 1959, __extension__ __PRETTY_FUNCTION__)); |
| 1960 | if (PredSethiUllman > SethiUllmanNumber) { |
| 1961 | SethiUllmanNumber = PredSethiUllman; |
| 1962 | Extra = 0; |
| 1963 | } else if (PredSethiUllman == SethiUllmanNumber) |
| 1964 | ++Extra; |
| 1965 | } |
| 1966 | |
| 1967 | SethiUllmanNumber += Extra; |
| 1968 | if (SethiUllmanNumber == 0) |
| 1969 | SethiUllmanNumber = 1; |
| 1970 | SUNumbers[TempSU->NodeNum] = SethiUllmanNumber; |
| 1971 | WorkList.pop_back(); |
| 1972 | } |
| 1973 | |
| 1974 | assert(SUNumbers[SU->NodeNum] > 0 && "SethiUllman should never be zero!")(static_cast <bool> (SUNumbers[SU->NodeNum] > 0 && "SethiUllman should never be zero!") ? void (0) : __assert_fail ("SUNumbers[SU->NodeNum] > 0 && \"SethiUllman should never be zero!\"" , "/build/llvm-toolchain-snapshot-7~svn329677/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp" , 1974, __extension__ __PRETTY_FUNCTION__)); |
| 1975 | return SUNumbers[SU->NodeNum]; |
| 1976 | } |
| 1977 | |
| 1978 | /// CalculateSethiUllmanNumbers - Calculate Sethi-Ullman numbers of all |
| 1979 | /// scheduling units. |
| 1980 | void RegReductionPQBase::CalculateSethiUllmanNumbers() { |
| 1981 | SethiUllmanNumbers.assign(SUnits->size(), 0); |
| 1982 | |
| 1983 | for (const SUnit &SU : *SUnits) |
| 1984 | CalcNodeSethiUllmanNumber(&SU, SethiUllmanNumbers); |
| 1985 | } |
| 1986 | |
| 1987 | void RegReductionPQBase::addNode(const SUnit *SU) { |
| 1988 | unsigned SUSize = SethiUllmanNumbers.size(); |
| 1989 | if (SUnits->size() > SUSize) |
| 1990 | SethiUllmanNumbers.resize(SUSize*2, 0); |
| 1991 | CalcNodeSethiUllmanNumber(SU, SethiUllmanNumbers); |
| 1992 | } |
| 1993 | |
| 1994 | void RegReductionPQBase::updateNode(const SUnit *SU) { |
| 1995 | SethiUllmanNumbers[SU->NodeNum] = 0; |
| 1996 | CalcNodeSethiUllmanNumber(SU, SethiUllmanNumbers); |
| 1997 | } |
| 1998 | |
| 1999 | // Lower priority means schedule further down. For bottom-up scheduling, lower |
| 2000 | // priority SUs are scheduled before higher priority SUs. |
| 2001 | unsigned RegReductionPQBase::getNodePriority(const SUnit *SU) const { |
| 2002 | assert(SU->NodeNum < SethiUllmanNumbers.size())(static_cast <bool> (SU->NodeNum < SethiUllmanNumbers .size()) ? void (0) : __assert_fail ("SU->NodeNum < SethiUllmanNumbers.size()" , "/build/llvm-toolchain-snapshot-7~svn329677/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp" , 2002, __extension__ __PRETTY_FUNCTION__)); |
| 2003 | unsigned Opc = SU->getNode() ? SU->getNode()->getOpcode() : 0; |
| 2004 | if (Opc == ISD::TokenFactor || Opc == ISD::CopyToReg) |
| 2005 | // CopyToReg should be close to its uses to facilitate coalescing and |
| 2006 | // avoid spilling. |
| 2007 | return 0; |
| 2008 | if (Opc == TargetOpcode::EXTRACT_SUBREG || |
| 2009 | Opc == TargetOpcode::SUBREG_TO_REG || |
| 2010 | Opc == TargetOpcode::INSERT_SUBREG) |
| 2011 | // EXTRACT_SUBREG, INSERT_SUBREG, and SUBREG_TO_REG nodes should be |
| 2012 | // close to their uses to facilitate coalescing. |
| 2013 | return 0; |
| 2014 | if (SU->NumSuccs == 0 && SU->NumPreds != 0) |
| 2015 | // If SU does not have a register use, i.e. it doesn't produce a value |
| 2016 | // that would be consumed (e.g. store), then it terminates a chain of |
| 2017 | // computation. Give it a large SethiUllman number so it will be |
| 2018 | // scheduled right before its predecessors that it doesn't lengthen |
| 2019 | // their live ranges. |
| 2020 | return 0xffff; |
| 2021 | if (SU->NumPreds == 0 && SU->NumSuccs != 0) |
| 2022 | // If SU does not have a register def, schedule it close to its uses |
| 2023 | // because it does not lengthen any live ranges. |
| 2024 | return 0; |
| 2025 | #if 1 |
| 2026 | return SethiUllmanNumbers[SU->NodeNum]; |
| 2027 | #else |
| 2028 | unsigned Priority = SethiUllmanNumbers[SU->NodeNum]; |
| 2029 | if (SU->isCallOp) { |
| 2030 | // FIXME: This assumes all of the defs are used as call operands. |
| 2031 | int NP = (int)Priority - SU->getNode()->getNumValues(); |
| 2032 | return (NP > 0) ? NP : 0; |
| 2033 | } |
| 2034 | return Priority; |
| 2035 | #endif |
| 2036 | } |
| 2037 | |
| 2038 | //===----------------------------------------------------------------------===// |
| 2039 | // Register Pressure Tracking |
| 2040 | //===----------------------------------------------------------------------===// |
| 2041 | |
| 2042 | #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) |
| 2043 | LLVM_DUMP_METHOD__attribute__((noinline)) __attribute__((__used__)) void RegReductionPQBase::dumpRegPressure() const { |
| 2044 | for (const TargetRegisterClass *RC : TRI->regclasses()) { |
| 2045 | unsigned Id = RC->getID(); |
| 2046 | unsigned RP = RegPressure[Id]; |
| 2047 | if (!RP) continue; |
| 2048 | DEBUG(dbgs() << TRI->getRegClassName(RC) << ": " << RP << " / "do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType ("pre-RA-sched")) { dbgs() << TRI->getRegClassName(RC ) << ": " << RP << " / " << RegLimit[ Id] << '\n'; } } while (false) |
| 2049 | << RegLimit[Id] << '\n')do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType ("pre-RA-sched")) { dbgs() << TRI->getRegClassName(RC ) << ": " << RP << " / " << RegLimit[ Id] << '\n'; } } while (false); |
| 2050 | } |
| 2051 | } |
| 2052 | #endif |
| 2053 | |
| 2054 | bool RegReductionPQBase::HighRegPressure(const SUnit *SU) const { |
| 2055 | if (!TLI) |
| 2056 | return false; |
| 2057 | |
| 2058 | for (const SDep &Pred : SU->Preds) { |
| 2059 | if (Pred.isCtrl()) |
| 2060 | continue; |
| 2061 | SUnit *PredSU = Pred.getSUnit(); |
| 2062 | // NumRegDefsLeft is zero when enough uses of this node have been scheduled |
| 2063 | // to cover the number of registers defined (they are all live). |
| 2064 | if (PredSU->NumRegDefsLeft == 0) { |
| 2065 | continue; |
| 2066 | } |
| 2067 | for (ScheduleDAGSDNodes::RegDefIter RegDefPos(PredSU, scheduleDAG); |
| 2068 | RegDefPos.IsValid(); RegDefPos.Advance()) { |
| 2069 | unsigned RCId, Cost; |
| 2070 | GetCostForDef(RegDefPos, TLI, TII, TRI, RCId, Cost, MF); |
| 2071 | |
| 2072 | if ((RegPressure[RCId] + Cost) >= RegLimit[RCId]) |
| 2073 | return true; |
| 2074 | } |
| 2075 | } |
| 2076 | return false; |
| 2077 | } |
| 2078 | |
| 2079 | bool RegReductionPQBase::MayReduceRegPressure(SUnit *SU) const { |
| 2080 | const SDNode *N = SU->getNode(); |
| 2081 | |
| 2082 | if (!N->isMachineOpcode() || !SU->NumSuccs) |
| 2083 | return false; |
| 2084 | |
| 2085 | unsigned NumDefs = TII->get(N->getMachineOpcode()).getNumDefs(); |
| 2086 | for (unsigned i = 0; i != NumDefs; ++i) { |
| 2087 | MVT VT = N->getSimpleValueType(i); |
| 2088 | if (!N->hasAnyUseOfValue(i)) |
| 2089 | continue; |
| 2090 | unsigned RCId = TLI->getRepRegClassFor(VT)->getID(); |
| 2091 | if (RegPressure[RCId] >= RegLimit[RCId]) |
| 2092 | return true; |
| 2093 | } |
| 2094 | return false; |
| 2095 | } |
| 2096 | |
| 2097 | // Compute the register pressure contribution by this instruction by count up |
| 2098 | // for uses that are not live and down for defs. Only count register classes |
| 2099 | // that are already under high pressure. As a side effect, compute the number of |
| 2100 | // uses of registers that are already live. |
| 2101 | // |
| 2102 | // FIXME: This encompasses the logic in HighRegPressure and MayReduceRegPressure |
| 2103 | // so could probably be factored. |
| 2104 | int RegReductionPQBase::RegPressureDiff(SUnit *SU, unsigned &LiveUses) const { |
| 2105 | LiveUses = 0; |
| 2106 | int PDiff = 0; |
| 2107 | for (const SDep &Pred : SU->Preds) { |
| 2108 | if (Pred.isCtrl()) |
| 2109 | continue; |
| 2110 | SUnit *PredSU = Pred.getSUnit(); |
| 2111 | // NumRegDefsLeft is zero when enough uses of this node have been scheduled |
| 2112 | // to cover the number of registers defined (they are all live). |
| 2113 | if (PredSU->NumRegDefsLeft == 0) { |
| 2114 | if (PredSU->getNode()->isMachineOpcode()) |
| 2115 | ++LiveUses; |
| 2116 | continue; |
| 2117 | } |
| 2118 | for (ScheduleDAGSDNodes::RegDefIter RegDefPos(PredSU, scheduleDAG); |
| 2119 | RegDefPos.IsValid(); RegDefPos.Advance()) { |
| 2120 | MVT VT = RegDefPos.GetValue(); |
| 2121 | unsigned RCId = TLI->getRepRegClassFor(VT)->getID(); |
| 2122 | if (RegPressure[RCId] >= RegLimit[RCId]) |
| 2123 | ++PDiff; |
| 2124 | } |
| 2125 | } |
| 2126 | const SDNode *N = SU->getNode(); |
| 2127 | |
| 2128 | if (!N || !N->isMachineOpcode() || !SU->NumSuccs) |
| 2129 | return PDiff; |
| 2130 | |
| 2131 | unsigned NumDefs = TII->get(N->getMachineOpcode()).getNumDefs(); |
| 2132 | for (unsigned i = 0; i != NumDefs; ++i) { |
| 2133 | MVT VT = N->getSimpleValueType(i); |
| 2134 | if (!N->hasAnyUseOfValue(i)) |
| 2135 | continue; |
| 2136 | unsigned RCId = TLI->getRepRegClassFor(VT)->getID(); |
| 2137 | if (RegPressure[RCId] >= RegLimit[RCId]) |
| 2138 | --PDiff; |
| 2139 | } |
| 2140 | return PDiff; |
| 2141 | } |
| 2142 | |
| 2143 | void RegReductionPQBase::scheduledNode(SUnit *SU) { |
| 2144 | if (!TracksRegPressure) |
| 2145 | return; |
| 2146 | |
| 2147 | if (!SU->getNode()) |
| 2148 | return; |
| 2149 | |
| 2150 | for (const SDep &Pred : SU->Preds) { |
| 2151 | if (Pred.isCtrl()) |
| 2152 | continue; |
| 2153 | SUnit *PredSU = Pred.getSUnit(); |
| 2154 | // NumRegDefsLeft is zero when enough uses of this node have been scheduled |
| 2155 | // to cover the number of registers defined (they are all live). |
| 2156 | if (PredSU->NumRegDefsLeft == 0) { |
| 2157 | continue; |
| 2158 | } |
| 2159 | // FIXME: The ScheduleDAG currently loses information about which of a |
| 2160 | // node's values is consumed by each dependence. Consequently, if the node |
| 2161 | // defines multiple register classes, we don't know which to pressurize |
| 2162 | // here. Instead the following loop consumes the register defs in an |
| 2163 | // arbitrary order. At least it handles the common case of clustered loads |
| 2164 | // to the same class. For precise liveness, each SDep needs to indicate the |
| 2165 | // result number. But that tightly couples the ScheduleDAG with the |
| 2166 | // SelectionDAG making updates tricky. A simpler hack would be to attach a |
| 2167 | // value type or register class to SDep. |
| 2168 | // |
| 2169 | // The most important aspect of register tracking is balancing the increase |
| 2170 | // here with the reduction further below. Note that this SU may use multiple |
| 2171 | // defs in PredSU. The can't be determined here, but we've already |
| 2172 | // compensated by reducing NumRegDefsLeft in PredSU during |
| 2173 | // ScheduleDAGSDNodes::AddSchedEdges. |
| 2174 | --PredSU->NumRegDefsLeft; |
| 2175 | unsigned SkipRegDefs = PredSU->NumRegDefsLeft; |
| 2176 | for (ScheduleDAGSDNodes::RegDefIter RegDefPos(PredSU, scheduleDAG); |
| 2177 | RegDefPos.IsValid(); RegDefPos.Advance(), --SkipRegDefs) { |
| 2178 | if (SkipRegDefs) |
| 2179 | continue; |
| 2180 | |
| 2181 | unsigned RCId, Cost; |
| 2182 | GetCostForDef(RegDefPos, TLI, TII, TRI, RCId, Cost, MF); |
| 2183 | RegPressure[RCId] += Cost; |
| 2184 | break; |
| 2185 | } |
| 2186 | } |
| 2187 | |
| 2188 | // We should have this assert, but there may be dead SDNodes that never |
| 2189 | // materialize as SUnits, so they don't appear to generate liveness. |
| 2190 | //assert(SU->NumRegDefsLeft == 0 && "not all regdefs have scheduled uses"); |
| 2191 | int SkipRegDefs = (int)SU->NumRegDefsLeft; |
| 2192 | for (ScheduleDAGSDNodes::RegDefIter RegDefPos(SU, scheduleDAG); |
| 2193 | RegDefPos.IsValid(); RegDefPos.Advance(), --SkipRegDefs) { |
| 2194 | if (SkipRegDefs > 0) |
| 2195 | continue; |
| 2196 | unsigned RCId, Cost; |
| 2197 | GetCostForDef(RegDefPos, TLI, TII, TRI, RCId, Cost, MF); |
| 2198 | if (RegPressure[RCId] < Cost) { |
| 2199 | // Register pressure tracking is imprecise. This can happen. But we try |
| 2200 | // hard not to let it happen because it likely results in poor scheduling. |
| 2201 | DEBUG(dbgs() << " SU(" << SU->NodeNum << ") has too many regdefs\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType ("pre-RA-sched")) { dbgs() << " SU(" << SU->NodeNum << ") has too many regdefs\n"; } } while (false); |
| 2202 | RegPressure[RCId] = 0; |
| 2203 | } |
| 2204 | else { |
| 2205 | RegPressure[RCId] -= Cost; |
| 2206 | } |
| 2207 | } |
| 2208 | DEBUG(dumpRegPressure())do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType ("pre-RA-sched")) { dumpRegPressure(); } } while (false); |
| 2209 | } |
| 2210 | |
| 2211 | void RegReductionPQBase::unscheduledNode(SUnit *SU) { |
| 2212 | if (!TracksRegPressure) |
| 2213 | return; |
| 2214 | |
| 2215 | const SDNode *N = SU->getNode(); |
| 2216 | if (!N) return; |
| 2217 | |
| 2218 | if (!N->isMachineOpcode()) { |
| 2219 | if (N->getOpcode() != ISD::CopyToReg) |
| 2220 | return; |
| 2221 | } else { |
| 2222 | unsigned Opc = N->getMachineOpcode(); |
| 2223 | if (Opc == TargetOpcode::EXTRACT_SUBREG || |
| 2224 | Opc == TargetOpcode::INSERT_SUBREG || |
| 2225 | Opc == TargetOpcode::SUBREG_TO_REG || |
| 2226 | Opc == TargetOpcode::REG_SEQUENCE || |
| 2227 | Opc == TargetOpcode::IMPLICIT_DEF) |
| 2228 | return; |
| 2229 | } |
| 2230 | |
| 2231 | for (const SDep &Pred : SU->Preds) { |
| 2232 | if (Pred.isCtrl()) |
| 2233 | continue; |
| 2234 | SUnit *PredSU = Pred.getSUnit(); |
| 2235 | // NumSuccsLeft counts all deps. Don't compare it with NumSuccs which only |
| 2236 | // counts data deps. |
| 2237 | if (PredSU->NumSuccsLeft != PredSU->Succs.size()) |
| 2238 | continue; |
| 2239 | const SDNode *PN = PredSU->getNode(); |
| 2240 | if (!PN->isMachineOpcode()) { |
| 2241 | if (PN->getOpcode() == ISD::CopyFromReg) { |
| 2242 | MVT VT = PN->getSimpleValueType(0); |
| 2243 | unsigned RCId = TLI->getRepRegClassFor(VT)->getID(); |
| 2244 | RegPressure[RCId] += TLI->getRepRegClassCostFor(VT); |
| 2245 | } |
| 2246 | continue; |
| 2247 | } |
| 2248 | unsigned POpc = PN->getMachineOpcode(); |
| 2249 | if (POpc == TargetOpcode::IMPLICIT_DEF) |
| 2250 | continue; |
| 2251 | if (POpc == TargetOpcode::EXTRACT_SUBREG || |
| 2252 | POpc == TargetOpcode::INSERT_SUBREG || |
| 2253 | POpc == TargetOpcode::SUBREG_TO_REG) { |
| 2254 | MVT VT = PN->getSimpleValueType(0); |
| 2255 | unsigned RCId = TLI->getRepRegClassFor(VT)->getID(); |
| 2256 | RegPressure[RCId] += TLI->getRepRegClassCostFor(VT); |
| 2257 | continue; |
| 2258 | } |
| 2259 | unsigned NumDefs = TII->get(PN->getMachineOpcode()).getNumDefs(); |
| 2260 | for (unsigned i = 0; i != NumDefs; ++i) { |
| 2261 | MVT VT = PN->getSimpleValueType(i); |
| 2262 | if (!PN->hasAnyUseOfValue(i)) |
| 2263 | continue; |
| 2264 | unsigned RCId = TLI->getRepRegClassFor(VT)->getID(); |
| 2265 | if (RegPressure[RCId] < TLI->getRepRegClassCostFor(VT)) |
| 2266 | // Register pressure tracking is imprecise. This can happen. |
| 2267 | RegPressure[RCId] = 0; |
| 2268 | else |
| 2269 | RegPressure[RCId] -= TLI->getRepRegClassCostFor(VT); |
| 2270 | } |
| 2271 | } |
| 2272 | |
| 2273 | // Check for isMachineOpcode() as PrescheduleNodesWithMultipleUses() |
| 2274 | // may transfer data dependencies to CopyToReg. |
| 2275 | if (SU->NumSuccs && N->isMachineOpcode()) { |
| 2276 | unsigned NumDefs = TII->get(N->getMachineOpcode()).getNumDefs(); |
| 2277 | for (unsigned i = NumDefs, e = N->getNumValues(); i != e; ++i) { |
| 2278 | MVT VT = N->getSimpleValueType(i); |
| 2279 | if (VT == MVT::Glue || VT == MVT::Other) |
| 2280 | continue; |
| 2281 | if (!N->hasAnyUseOfValue(i)) |
| 2282 | continue; |
| 2283 | unsigned RCId = TLI->getRepRegClassFor(VT)->getID(); |
| 2284 | RegPressure[RCId] += TLI->getRepRegClassCostFor(VT); |
| 2285 | } |
| 2286 | } |
| 2287 | |
| 2288 | DEBUG(dumpRegPressure())do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType ("pre-RA-sched")) { dumpRegPressure(); } } while (false); |
| 2289 | } |
| 2290 | |
| 2291 | //===----------------------------------------------------------------------===// |
| 2292 | // Dynamic Node Priority for Register Pressure Reduction |
| 2293 | //===----------------------------------------------------------------------===// |
| 2294 | |
| 2295 | /// closestSucc - Returns the scheduled cycle of the successor which is |
| 2296 | /// closest to the current cycle. |
| 2297 | static unsigned closestSucc(const SUnit *SU) { |
| 2298 | unsigned MaxHeight = 0; |
| 2299 | for (const SDep &Succ : SU->Succs) { |
| 2300 | if (Succ.isCtrl()) continue; // ignore chain succs |
| 2301 | unsigned Height = Succ.getSUnit()->getHeight(); |
| 2302 | // If there are bunch of CopyToRegs stacked up, they should be considered |
| 2303 | // to be at the same position. |
| 2304 | if (Succ.getSUnit()->getNode() && |
| 2305 | Succ.getSUnit()->getNode()->getOpcode() == ISD::CopyToReg) |
| 2306 | Height = closestSucc(Succ.getSUnit())+1; |
| 2307 | if (Height > MaxHeight) |
| 2308 | MaxHeight = Height; |
| 2309 | } |
| 2310 | return MaxHeight; |
| 2311 | } |
| 2312 | |
| 2313 | /// calcMaxScratches - Returns an cost estimate of the worse case requirement |
| 2314 | /// for scratch registers, i.e. number of data dependencies. |
| 2315 | static unsigned calcMaxScratches(const SUnit *SU) { |
| 2316 | unsigned Scratches = 0; |
| 2317 | for (const SDep &Pred : SU->Preds) { |
| 2318 | if (Pred.isCtrl()) continue; // ignore chain preds |
| 2319 | Scratches++; |
| 2320 | } |
| 2321 | return Scratches; |
| 2322 | } |
| 2323 | |
| 2324 | /// hasOnlyLiveInOpers - Return true if SU has only value predecessors that are |
| 2325 | /// CopyFromReg from a virtual register. |
| 2326 | static bool hasOnlyLiveInOpers(const SUnit *SU) { |
| 2327 | bool RetVal = false; |
| 2328 | for (const SDep &Pred : SU->Preds) { |
| 2329 | if (Pred.isCtrl()) continue; |
| 2330 | const SUnit *PredSU = Pred.getSUnit(); |
| 2331 | if (PredSU->getNode() && |
| 2332 | PredSU->getNode()->getOpcode() == ISD::CopyFromReg) { |
| 2333 | unsigned Reg = |
| 2334 | cast<RegisterSDNode>(PredSU->getNode()->getOperand(1))->getReg(); |
| 2335 | if (TargetRegisterInfo::isVirtualRegister(Reg)) { |
| 2336 | RetVal = true; |
| 2337 | continue; |
| 2338 | } |
| 2339 | } |
| 2340 | return false; |
| 2341 | } |
| 2342 | return RetVal; |
| 2343 | } |
| 2344 | |
| 2345 | /// hasOnlyLiveOutUses - Return true if SU has only value successors that are |
| 2346 | /// CopyToReg to a virtual register. This SU def is probably a liveout and |
| 2347 | /// it has no other use. It should be scheduled closer to the terminator. |
| 2348 | static bool hasOnlyLiveOutUses(const SUnit *SU) { |
| 2349 | bool RetVal = false; |
| 2350 | for (const SDep &Succ : SU->Succs) { |
| 2351 | if (Succ.isCtrl()) continue; |
| 2352 | const SUnit *SuccSU = Succ.getSUnit(); |
| 2353 | if (SuccSU->getNode() && SuccSU->getNode()->getOpcode() == ISD::CopyToReg) { |
| 2354 | unsigned Reg = |
| 2355 | cast<RegisterSDNode>(SuccSU->getNode()->getOperand(1))->getReg(); |
| 2356 | if (TargetRegisterInfo::isVirtualRegister(Reg)) { |
| 2357 | RetVal = true; |
| 2358 | continue; |
| 2359 | } |
| 2360 | } |
| 2361 | return false; |
| 2362 | } |
| 2363 | return RetVal; |
| 2364 | } |
| 2365 | |
| 2366 | // Set isVRegCycle for a node with only live in opers and live out uses. Also |
| 2367 | // set isVRegCycle for its CopyFromReg operands. |
| 2368 | // |
| 2369 | // This is only relevant for single-block loops, in which case the VRegCycle |
| 2370 | // node is likely an induction variable in which the operand and target virtual |
| 2371 | // registers should be coalesced (e.g. pre/post increment values). Setting the |
| 2372 | // isVRegCycle flag helps the scheduler prioritize other uses of the same |
| 2373 | // CopyFromReg so that this node becomes the virtual register "kill". This |
| 2374 | // avoids interference between the values live in and out of the block and |
| 2375 | // eliminates a copy inside the loop. |
| 2376 | static void initVRegCycle(SUnit *SU) { |
| 2377 | if (DisableSchedVRegCycle) |
| 2378 | return; |
| 2379 | |
| 2380 | if (!hasOnlyLiveInOpers(SU) || !hasOnlyLiveOutUses(SU)) |
| 2381 | return; |
| 2382 | |
| 2383 | DEBUG(dbgs() << "VRegCycle: SU(" << SU->NodeNum << ")\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType ("pre-RA-sched")) { dbgs() << "VRegCycle: SU(" << SU->NodeNum << ")\n"; } } while (false); |
| 2384 | |
| 2385 | SU->isVRegCycle = true; |
| 2386 | |
| 2387 | for (const SDep &Pred : SU->Preds) { |
| 2388 | if (Pred.isCtrl()) continue; |
| 2389 | Pred.getSUnit()->isVRegCycle = true; |
| 2390 | } |
| 2391 | } |
| 2392 | |
| 2393 | // After scheduling the definition of a VRegCycle, clear the isVRegCycle flag of |
| 2394 | // CopyFromReg operands. We should no longer penalize other uses of this VReg. |
| 2395 | static void resetVRegCycle(SUnit *SU) { |
| 2396 | if (!SU->isVRegCycle) |
| 2397 | return; |
| 2398 | |
| 2399 | for (const SDep &Pred : SU->Preds) { |
| 2400 | if (Pred.isCtrl()) continue; // ignore chain preds |
| 2401 | SUnit *PredSU = Pred.getSUnit(); |
| 2402 | if (PredSU->isVRegCycle) { |
| 2403 | assert(PredSU->getNode()->getOpcode() == ISD::CopyFromReg &&(static_cast <bool> (PredSU->getNode()->getOpcode () == ISD::CopyFromReg && "VRegCycle def must be CopyFromReg" ) ? void (0) : __assert_fail ("PredSU->getNode()->getOpcode() == ISD::CopyFromReg && \"VRegCycle def must be CopyFromReg\"" , "/build/llvm-toolchain-snapshot-7~svn329677/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp" , 2404, __extension__ __PRETTY_FUNCTION__)) |
| 2404 | "VRegCycle def must be CopyFromReg")(static_cast <bool> (PredSU->getNode()->getOpcode () == ISD::CopyFromReg && "VRegCycle def must be CopyFromReg" ) ? void (0) : __assert_fail ("PredSU->getNode()->getOpcode() == ISD::CopyFromReg && \"VRegCycle def must be CopyFromReg\"" , "/build/llvm-toolchain-snapshot-7~svn329677/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp" , 2404, __extension__ __PRETTY_FUNCTION__)); |
| 2405 | Pred.getSUnit()->isVRegCycle = false; |
| 2406 | } |
| 2407 | } |
| 2408 | } |
| 2409 | |
| 2410 | // Return true if this SUnit uses a CopyFromReg node marked as a VRegCycle. This |
| 2411 | // means a node that defines the VRegCycle has not been scheduled yet. |
| 2412 | static bool hasVRegCycleUse(const SUnit *SU) { |
| 2413 | // If this SU also defines the VReg, don't hoist it as a "use". |
| 2414 | if (SU->isVRegCycle) |
| 2415 | return false; |
| 2416 | |
| 2417 | for (const SDep &Pred : SU->Preds) { |
| 2418 | if (Pred.isCtrl()) continue; // ignore chain preds |
| 2419 | if (Pred.getSUnit()->isVRegCycle && |
| 2420 | Pred.getSUnit()->getNode()->getOpcode() == ISD::CopyFromReg) { |
| 2421 | DEBUG(dbgs() << " VReg cycle use: SU (" << SU->NodeNum << ")\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType ("pre-RA-sched")) { dbgs() << " VReg cycle use: SU (" << SU->NodeNum << ")\n"; } } while (false); |
| 2422 | return true; |
| 2423 | } |
| 2424 | } |
| 2425 | return false; |
| 2426 | } |
| 2427 | |
| 2428 | // Check for either a dependence (latency) or resource (hazard) stall. |
| 2429 | // |
| 2430 | // Note: The ScheduleHazardRecognizer interface requires a non-const SU. |
| 2431 | static bool BUHasStall(SUnit *SU, int Height, RegReductionPQBase *SPQ) { |
| 2432 | if ((int)SPQ->getCurCycle() < Height) return true; |
| 2433 | if (SPQ->getHazardRec()->getHazardType(SU, 0) |
| 2434 | != ScheduleHazardRecognizer::NoHazard) |
| 2435 | return true; |
| 2436 | return false; |
| 2437 | } |
| 2438 | |
| 2439 | // Return -1 if left has higher priority, 1 if right has higher priority. |
| 2440 | // Return 0 if latency-based priority is equivalent. |
| 2441 | static int BUCompareLatency(SUnit *left, SUnit *right, bool checkPref, |
| 2442 | RegReductionPQBase *SPQ) { |
| 2443 | // Scheduling an instruction that uses a VReg whose postincrement has not yet |
| 2444 | // been scheduled will induce a copy. Model this as an extra cycle of latency. |
| 2445 | int LPenalty = hasVRegCycleUse(left) ? 1 : 0; |
| 2446 | int RPenalty = hasVRegCycleUse(right) ? 1 : 0; |
| 2447 | int LHeight = (int)left->getHeight() + LPenalty; |
| 2448 | int RHeight = (int)right->getHeight() + RPenalty; |
| 2449 | |
| 2450 | bool LStall = (!checkPref || left->SchedulingPref == Sched::ILP) && |
| 2451 | BUHasStall(left, LHeight, SPQ); |
| 2452 | bool RStall = (!checkPref || right->SchedulingPref == Sched::ILP) && |
| 2453 | BUHasStall(right, RHeight, SPQ); |
| 2454 | |
| 2455 | // If scheduling one of the node will cause a pipeline stall, delay it. |
| 2456 | // If scheduling either one of the node will cause a pipeline stall, sort |
| 2457 | // them according to their height. |
| 2458 | if (LStall) { |
| 2459 | if (!RStall) |
| 2460 | return 1; |
| 2461 | if (LHeight != RHeight) |
| 2462 | return LHeight > RHeight ? 1 : -1; |
| 2463 | } else if (RStall) |
| 2464 | return -1; |
| 2465 | |
| 2466 | // If either node is scheduling for latency, sort them by height/depth |
| 2467 | // and latency. |
| 2468 | if (!checkPref || (left->SchedulingPref == Sched::ILP || |
| 2469 | right->SchedulingPref == Sched::ILP)) { |
| 2470 | // If neither instruction stalls (!LStall && !RStall) and HazardRecognizer |
| 2471 | // is enabled, grouping instructions by cycle, then its height is already |
| 2472 | // covered so only its depth matters. We also reach this point if both stall |
| 2473 | // but have the same height. |
| 2474 | if (!SPQ->getHazardRec()->isEnabled()) { |
| 2475 | if (LHeight != RHeight) |
| 2476 | return LHeight > RHeight ? 1 : -1; |
| 2477 | } |
| 2478 | int LDepth = left->getDepth() - LPenalty; |
| 2479 | int RDepth = right->getDepth() - RPenalty; |
| 2480 | if (LDepth != RDepth) { |
| 2481 | DEBUG(dbgs() << " Comparing latency of SU (" << left->NodeNumdo { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType ("pre-RA-sched")) { dbgs() << " Comparing latency of SU (" << left->NodeNum << ") depth " << LDepth << " vs SU (" << right->NodeNum << ") depth " << RDepth << "\n"; } } while (false) |
| 2482 | << ") depth " << LDepth << " vs SU (" << right->NodeNumdo { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType ("pre-RA-sched")) { dbgs() << " Comparing latency of SU (" << left->NodeNum << ") depth " << LDepth << " vs SU (" << right->NodeNum << ") depth " << RDepth << "\n"; } } while (false) |
| 2483 | << ") depth " << RDepth << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType ("pre-RA-sched")) { dbgs() << " Comparing latency of SU (" << left->NodeNum << ") depth " << LDepth << " vs SU (" << right->NodeNum << ") depth " << RDepth << "\n"; } } while (false); |
| 2484 | return LDepth < RDepth ? 1 : -1; |
| 2485 | } |
| 2486 | if (left->Latency != right->Latency) |
| 2487 | return left->Latency > right->Latency ? 1 : -1; |
| 2488 | } |
| 2489 | return 0; |
| 2490 | } |
| 2491 | |
| 2492 | static bool BURRSort(SUnit *left, SUnit *right, RegReductionPQBase *SPQ) { |
| 2493 | // Schedule physical register definitions close to their use. This is |
| 2494 | // motivated by microarchitectures that can fuse cmp+jump macro-ops. But as |
| 2495 | // long as shortening physreg live ranges is generally good, we can defer |
| 2496 | // creating a subtarget hook. |
| 2497 | if (!DisableSchedPhysRegJoin) { |
| 2498 | bool LHasPhysReg = left->hasPhysRegDefs; |
| 2499 | bool RHasPhysReg = right->hasPhysRegDefs; |
| 2500 | if (LHasPhysReg != RHasPhysReg) { |
| 2501 | #ifndef NDEBUG |
| 2502 | static const char *const PhysRegMsg[] = { " has no physreg", |
| 2503 | " defines a physreg" }; |
| 2504 | #endif |
| 2505 | DEBUG(dbgs() << " SU (" << left->NodeNum << ") "do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType ("pre-RA-sched")) { dbgs() << " SU (" << left-> NodeNum << ") " << PhysRegMsg[LHasPhysReg] << " SU(" << right->NodeNum << ") " << PhysRegMsg [RHasPhysReg] << "\n"; } } while (false) |
| 2506 | << PhysRegMsg[LHasPhysReg] << " SU(" << right->NodeNum << ") "do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType ("pre-RA-sched")) { dbgs() << " SU (" << left-> NodeNum << ") " << PhysRegMsg[LHasPhysReg] << " SU(" << right->NodeNum << ") " << PhysRegMsg [RHasPhysReg] << "\n"; } } while (false) |
| 2507 | << PhysRegMsg[RHasPhysReg] << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType ("pre-RA-sched")) { dbgs() << " SU (" << left-> NodeNum << ") " << PhysRegMsg[LHasPhysReg] << " SU(" << right->NodeNum << ") " << PhysRegMsg [RHasPhysReg] << "\n"; } } while (false); |
| 2508 | return LHasPhysReg < RHasPhysReg; |
| 2509 | } |
| 2510 | } |
| 2511 | |
| 2512 | // Prioritize by Sethi-Ulmann number and push CopyToReg nodes down. |
| 2513 | unsigned LPriority = SPQ->getNodePriority(left); |
| 2514 | unsigned RPriority = SPQ->getNodePriority(right); |
| 2515 | |
| 2516 | // Be really careful about hoisting call operands above previous calls. |
| 2517 | // Only allows it if it would reduce register pressure. |
| 2518 | if (left->isCall && right->isCallOp) { |
| 2519 | unsigned RNumVals = right->getNode()->getNumValues(); |
| 2520 | RPriority = (RPriority > RNumVals) ? (RPriority - RNumVals) : 0; |
| 2521 | } |
| 2522 | if (right->isCall && left->isCallOp) { |
| 2523 | unsigned LNumVals = left->getNode()->getNumValues(); |
| 2524 | LPriority = (LPriority > LNumVals) ? (LPriority - LNumVals) : 0; |
| 2525 | } |
| 2526 | |
| 2527 | if (LPriority != RPriority) |
| 2528 | return LPriority > RPriority; |
| 2529 | |
| 2530 | // One or both of the nodes are calls and their sethi-ullman numbers are the |
| 2531 | // same, then keep source order. |
| 2532 | if (left->isCall || right->isCall) { |
| 2533 | unsigned LOrder = SPQ->getNodeOrdering(left); |
| 2534 | unsigned ROrder = SPQ->getNodeOrdering(right); |
| 2535 | |
| 2536 | // Prefer an ordering where the lower the non-zero order number, the higher |
| 2537 | // the preference. |
| 2538 | if ((LOrder || ROrder) && LOrder != ROrder) |
| 2539 | return LOrder != 0 && (LOrder < ROrder || ROrder == 0); |
| 2540 | } |
| 2541 | |
| 2542 | // Try schedule def + use closer when Sethi-Ullman numbers are the same. |
| 2543 | // e.g. |
| 2544 | // t1 = op t2, c1 |
| 2545 | // t3 = op t4, c2 |
| 2546 | // |
| 2547 | // and the following instructions are both ready. |
| 2548 | // t2 = op c3 |
| 2549 | // t4 = op c4 |
| 2550 | // |
| 2551 | // Then schedule t2 = op first. |
| 2552 | // i.e. |
| 2553 | // t4 = op c4 |
| 2554 | // t2 = op c3 |
| 2555 | // t1 = op t2, c1 |
| 2556 | // t3 = op t4, c2 |
| 2557 | // |
| 2558 | // This creates more short live intervals. |
| 2559 | unsigned LDist = closestSucc(left); |
| 2560 | unsigned RDist = closestSucc(right); |
| 2561 | if (LDist != RDist) |
| 2562 | return LDist < RDist; |
| 2563 | |
| 2564 | // How many registers becomes live when the node is scheduled. |
| 2565 | unsigned LScratch = calcMaxScratches(left); |
| 2566 | unsigned RScratch = calcMaxScratches(right); |
| 2567 | if (LScratch != RScratch) |
| 2568 | return LScratch > RScratch; |
| 2569 | |
| 2570 | // Comparing latency against a call makes little sense unless the node |
| 2571 | // is register pressure-neutral. |
| 2572 | if ((left->isCall && RPriority > 0) || (right->isCall && LPriority > 0)) |
| 2573 | return (left->NodeQueueId > right->NodeQueueId); |
| 2574 | |
| 2575 | // Do not compare latencies when one or both of the nodes are calls. |
| 2576 | if (!DisableSchedCycles && |
| 2577 | !(left->isCall || right->isCall)) { |
| 2578 | int result = BUCompareLatency(left, right, false /*checkPref*/, SPQ); |
| 2579 | if (result != 0) |
| 2580 | return result > 0; |
| 2581 | } |
| 2582 | else { |
| 2583 | if (left->getHeight() != right->getHeight()) |
| 2584 | return left->getHeight() > right->getHeight(); |
| 2585 | |
| 2586 | if (left->getDepth() != right->getDepth()) |
| 2587 | return left->getDepth() < right->getDepth(); |
| 2588 | } |
| 2589 | |
| 2590 | assert(left->NodeQueueId && right->NodeQueueId &&(static_cast <bool> (left->NodeQueueId && right ->NodeQueueId && "NodeQueueId cannot be zero") ? void (0) : __assert_fail ("left->NodeQueueId && right->NodeQueueId && \"NodeQueueId cannot be zero\"" , "/build/llvm-toolchain-snapshot-7~svn329677/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp" , 2591, __extension__ __PRETTY_FUNCTION__)) |
| 2591 | "NodeQueueId cannot be zero")(static_cast <bool> (left->NodeQueueId && right ->NodeQueueId && "NodeQueueId cannot be zero") ? void (0) : __assert_fail ("left->NodeQueueId && right->NodeQueueId && \"NodeQueueId cannot be zero\"" , "/build/llvm-toolchain-snapshot-7~svn329677/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp" , 2591, __extension__ __PRETTY_FUNCTION__)); |
| 2592 | return (left->NodeQueueId > right->NodeQueueId); |
| 2593 | } |
| 2594 | |
| 2595 | // Bottom up |
| 2596 | bool bu_ls_rr_sort::operator()(SUnit *left, SUnit *right) const { |
| 2597 | if (int res = checkSpecialNodes(left, right)) |
| 2598 | return res > 0; |
| 2599 | |
| 2600 | return BURRSort(left, right, SPQ); |
| 2601 | } |
| 2602 | |
| 2603 | // Source order, otherwise bottom up. |
| 2604 | bool src_ls_rr_sort::operator()(SUnit *left, SUnit *right) const { |
| 2605 | if (int res = checkSpecialNodes(left, right)) |
| 2606 | return res > 0; |
| 2607 | |
| 2608 | unsigned LOrder = SPQ->getNodeOrdering(left); |
| 2609 | unsigned ROrder = SPQ->getNodeOrdering(right); |
| 2610 | |
| 2611 | // Prefer an ordering where the lower the non-zero order number, the higher |
| 2612 | // the preference. |
| 2613 | if ((LOrder || ROrder) && LOrder != ROrder) |
| 2614 | return LOrder != 0 && (LOrder < ROrder || ROrder == 0); |
| 2615 | |
| 2616 | return BURRSort(left, right, SPQ); |
| 2617 | } |
| 2618 | |
| 2619 | // If the time between now and when the instruction will be ready can cover |
| 2620 | // the spill code, then avoid adding it to the ready queue. This gives long |
| 2621 | // stalls highest priority and allows hoisting across calls. It should also |
| 2622 | // speed up processing the available queue. |
| 2623 | bool hybrid_ls_rr_sort::isReady(SUnit *SU, unsigned CurCycle) const { |
| 2624 | static const unsigned ReadyDelay = 3; |
| 2625 | |
| 2626 | if (SPQ->MayReduceRegPressure(SU)) return true; |
| 2627 | |
| 2628 | if (SU->getHeight() > (CurCycle + ReadyDelay)) return false; |
| 2629 | |
| 2630 | if (SPQ->getHazardRec()->getHazardType(SU, -ReadyDelay) |
| 2631 | != ScheduleHazardRecognizer::NoHazard) |
| 2632 | return false; |
| 2633 | |
| 2634 | return true; |
| 2635 | } |
| 2636 | |
| 2637 | // Return true if right should be scheduled with higher priority than left. |
| 2638 | bool hybrid_ls_rr_sort::operator()(SUnit *left, SUnit *right) const { |
| 2639 | if (int res = checkSpecialNodes(left, right)) |
| 2640 | return res > 0; |
| 2641 | |
| 2642 | if (left->isCall || right->isCall) |
| 2643 | // No way to compute latency of calls. |
| 2644 | return BURRSort(left, right, SPQ); |
| 2645 | |
| 2646 | bool LHigh = SPQ->HighRegPressure(left); |
| 2647 | bool RHigh = SPQ->HighRegPressure(right); |
| 2648 | // Avoid causing spills. If register pressure is high, schedule for |
| 2649 | // register pressure reduction. |
| 2650 | if (LHigh && !RHigh) { |
| 2651 | DEBUG(dbgs() << " pressure SU(" << left->NodeNum << ") > SU("do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType ("pre-RA-sched")) { dbgs() << " pressure SU(" << left->NodeNum << ") > SU(" << right->NodeNum << ")\n"; } } while (false) |
| 2652 | << right->NodeNum << ")\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType ("pre-RA-sched")) { dbgs() << " pressure SU(" << left->NodeNum << ") > SU(" << right->NodeNum << ")\n"; } } while (false); |
| 2653 | return true; |
| 2654 | } |
| 2655 | else if (!LHigh && RHigh) { |
| 2656 | DEBUG(dbgs() << " pressure SU(" << right->NodeNum << ") > SU("do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType ("pre-RA-sched")) { dbgs() << " pressure SU(" << right->NodeNum << ") > SU(" << left->NodeNum << ")\n"; } } while (false) |
| 2657 | << left->NodeNum << ")\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType ("pre-RA-sched")) { dbgs() << " pressure SU(" << right->NodeNum << ") > SU(" << left->NodeNum << ")\n"; } } while (false); |
| 2658 | return false; |
| 2659 | } |
| 2660 | if (!LHigh && !RHigh) { |
| 2661 | int result = BUCompareLatency(left, right, true /*checkPref*/, SPQ); |
| 2662 | if (result != 0) |
| 2663 | return result > 0; |
| 2664 | } |
| 2665 | return BURRSort(left, right, SPQ); |
| 2666 | } |
| 2667 | |
| 2668 | // Schedule as many instructions in each cycle as possible. So don't make an |
| 2669 | // instruction available unless it is ready in the current cycle. |
| 2670 | bool ilp_ls_rr_sort::isReady(SUnit *SU, unsigned CurCycle) const { |
| 2671 | if (SU->getHeight() > CurCycle) return false; |
| 2672 | |
| 2673 | if (SPQ->getHazardRec()->getHazardType(SU, 0) |
| 2674 | != ScheduleHazardRecognizer::NoHazard) |
| 2675 | return false; |
| 2676 | |
| 2677 | return true; |
| 2678 | } |
| 2679 | |
| 2680 | static bool canEnableCoalescing(SUnit *SU) { |
| 2681 | unsigned Opc = SU->getNode() ? SU->getNode()->getOpcode() : 0; |
| 2682 | if (Opc == ISD::TokenFactor || Opc == ISD::CopyToReg) |
| 2683 | // CopyToReg should be close to its uses to facilitate coalescing and |
| 2684 | // avoid spilling. |
| 2685 | return true; |
| 2686 | |
| 2687 | if (Opc == TargetOpcode::EXTRACT_SUBREG || |
| 2688 | Opc == TargetOpcode::SUBREG_TO_REG || |
| 2689 | Opc == TargetOpcode::INSERT_SUBREG) |
| 2690 | // EXTRACT_SUBREG, INSERT_SUBREG, and SUBREG_TO_REG nodes should be |
| 2691 | // close to their uses to facilitate coalescing. |
| 2692 | return true; |
| 2693 | |
| 2694 | if (SU->NumPreds == 0 && SU->NumSuccs != 0) |
| 2695 | // If SU does not have a register def, schedule it close to its uses |
| 2696 | // because it does not lengthen any live ranges. |
| 2697 | return true; |
| 2698 | |
| 2699 | return false; |
| 2700 | } |
| 2701 | |
| 2702 | // list-ilp is currently an experimental scheduler that allows various |
| 2703 | // heuristics to be enabled prior to the normal register reduction logic. |
| 2704 | bool ilp_ls_rr_sort::operator()(SUnit *left, SUnit *right) const { |
| 2705 | if (int res = checkSpecialNodes(left, right)) |
| 2706 | return res > 0; |
| 2707 | |
| 2708 | if (left->isCall || right->isCall) |
| 2709 | // No way to compute latency of calls. |
| 2710 | return BURRSort(left, right, SPQ); |
| 2711 | |
| 2712 | unsigned LLiveUses = 0, RLiveUses = 0; |
| 2713 | int LPDiff = 0, RPDiff = 0; |
| 2714 | if (!DisableSchedRegPressure || !DisableSchedLiveUses) { |
| 2715 | LPDiff = SPQ->RegPressureDiff(left, LLiveUses); |
| 2716 | RPDiff = SPQ->RegPressureDiff(right, RLiveUses); |
| 2717 | } |
| 2718 | if (!DisableSchedRegPressure && LPDiff != RPDiff) { |
| 2719 | DEBUG(dbgs() << "RegPressureDiff SU(" << left->NodeNum << "): " << LPDiffdo { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType ("pre-RA-sched")) { dbgs() << "RegPressureDiff SU(" << left->NodeNum << "): " << LPDiff << " != SU(" << right->NodeNum << "): " << RPDiff << "\n"; } } while (false) |
| 2720 | << " != SU(" << right->NodeNum << "): " << RPDiff << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType ("pre-RA-sched")) { dbgs() << "RegPressureDiff SU(" << left->NodeNum << "): " << LPDiff << " != SU(" << right->NodeNum << "): " << RPDiff << "\n"; } } while (false); |
| 2721 | return LPDiff > RPDiff; |
| 2722 | } |
| 2723 | |
| 2724 | if (!DisableSchedRegPressure && (LPDiff > 0 || RPDiff > 0)) { |
| 2725 | bool LReduce = canEnableCoalescing(left); |
| 2726 | bool RReduce = canEnableCoalescing(right); |
| 2727 | if (LReduce && !RReduce) return false; |
| 2728 | if (RReduce && !LReduce) return true; |
| 2729 | } |
| 2730 | |
| 2731 | if (!DisableSchedLiveUses && (LLiveUses != RLiveUses)) { |
| 2732 | DEBUG(dbgs() << "Live uses SU(" << left->NodeNum << "): " << LLiveUsesdo { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType ("pre-RA-sched")) { dbgs() << "Live uses SU(" << left ->NodeNum << "): " << LLiveUses << " != SU(" << right->NodeNum << "): " << RLiveUses << "\n"; } } while (false) |
| 2733 | << " != SU(" << right->NodeNum << "): " << RLiveUses << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType ("pre-RA-sched")) { dbgs() << "Live uses SU(" << left ->NodeNum << "): " << LLiveUses << " != SU(" << right->NodeNum << "): " << RLiveUses << "\n"; } } while (false); |
| 2734 | return LLiveUses < RLiveUses; |
| 2735 | } |
| 2736 | |
| 2737 | if (!DisableSchedStalls) { |
| 2738 | bool LStall = BUHasStall(left, left->getHeight(), SPQ); |
| 2739 | bool RStall = BUHasStall(right, right->getHeight(), SPQ); |
| 2740 | if (LStall != RStall) |
| 2741 | return left->getHeight() > right->getHeight(); |
| 2742 | } |
| 2743 | |
| 2744 | if (!DisableSchedCriticalPath) { |
| 2745 | int spread = (int)left->getDepth() - (int)right->getDepth(); |
| 2746 | if (std::abs(spread) > MaxReorderWindow) { |
| 2747 | DEBUG(dbgs() << "Depth of SU(" << left->NodeNum << "): "do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType ("pre-RA-sched")) { dbgs() << "Depth of SU(" << left ->NodeNum << "): " << left->getDepth() << " != SU(" << right->NodeNum << "): " << right->getDepth() << "\n"; } } while (false) |
| 2748 | << left->getDepth() << " != SU(" << right->NodeNum << "): "do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType ("pre-RA-sched")) { dbgs() << "Depth of SU(" << left ->NodeNum << "): " << left->getDepth() << " != SU(" << right->NodeNum << "): " << right->getDepth() << "\n"; } } while (false) |
| 2749 | << right->getDepth() << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType ("pre-RA-sched")) { dbgs() << "Depth of SU(" << left ->NodeNum << "): " << left->getDepth() << " != SU(" << right->NodeNum << "): " << right->getDepth() << "\n"; } } while (false); |
| 2750 | return left->getDepth() < right->getDepth(); |
| 2751 | } |
| 2752 | } |
| 2753 | |
| 2754 | if (!DisableSchedHeight && left->getHeight() != right->getHeight()) { |
| 2755 | int spread = (int)left->getHeight() - (int)right->getHeight(); |
| 2756 | if (std::abs(spread) > MaxReorderWindow) |
| 2757 | return left->getHeight() > right->getHeight(); |
| 2758 | } |
| 2759 | |
| 2760 | return BURRSort(left, right, SPQ); |
| 2761 | } |
| 2762 | |
| 2763 | void RegReductionPQBase::initNodes(std::vector<SUnit> &sunits) { |
| 2764 | SUnits = &sunits; |
| 2765 | // Add pseudo dependency edges for two-address nodes. |
| 2766 | if (!Disable2AddrHack) |
| 2767 | AddPseudoTwoAddrDeps(); |
| 2768 | // Reroute edges to nodes with multiple uses. |
| 2769 | if (!TracksRegPressure && !SrcOrder) |
| 2770 | PrescheduleNodesWithMultipleUses(); |
| 2771 | // Calculate node priorities. |
| 2772 | CalculateSethiUllmanNumbers(); |
| 2773 | |
| 2774 | // For single block loops, mark nodes that look like canonical IV increments. |
| 2775 | if (scheduleDAG->BB->isSuccessor(scheduleDAG->BB)) |
| 2776 | for (SUnit &SU : sunits) |
| 2777 | initVRegCycle(&SU); |
| 2778 | } |
| 2779 | |
| 2780 | //===----------------------------------------------------------------------===// |
| 2781 | // Preschedule for Register Pressure |
| 2782 | //===----------------------------------------------------------------------===// |
| 2783 | |
| 2784 | bool RegReductionPQBase::canClobber(const SUnit *SU, const SUnit *Op) { |
| 2785 | if (SU->isTwoAddress) { |
| 2786 | unsigned Opc = SU->getNode()->getMachineOpcode(); |
| 2787 | const MCInstrDesc &MCID = TII->get(Opc); |
| 2788 | unsigned NumRes = MCID.getNumDefs(); |
| 2789 | unsigned NumOps = MCID.getNumOperands() - NumRes; |
| 2790 | for (unsigned i = 0; i != NumOps; ++i) { |
| 2791 | if (MCID.getOperandConstraint(i+NumRes, MCOI::TIED_TO) != -1) { |
| 2792 | SDNode *DU = SU->getNode()->getOperand(i).getNode(); |
| 2793 | if (DU->getNodeId() != -1 && |
| 2794 | Op->OrigNode == &(*SUnits)[DU->getNodeId()]) |
| 2795 | return true; |
| 2796 | } |
| 2797 | } |
| 2798 | } |
| 2799 | return false; |
| 2800 | } |
| 2801 | |
| 2802 | /// canClobberReachingPhysRegUse - True if SU would clobber one of it's |
| 2803 | /// successor's explicit physregs whose definition can reach DepSU. |
| 2804 | /// i.e. DepSU should not be scheduled above SU. |
| 2805 | static bool canClobberReachingPhysRegUse(const SUnit *DepSU, const SUnit *SU, |
| 2806 | ScheduleDAGRRList *scheduleDAG, |
| 2807 | const TargetInstrInfo *TII, |
| 2808 | const TargetRegisterInfo *TRI) { |
| 2809 | const MCPhysReg *ImpDefs |
| 2810 | = TII->get(SU->getNode()->getMachineOpcode()).getImplicitDefs(); |
| 2811 | const uint32_t *RegMask = getNodeRegMask(SU->getNode()); |
| 2812 | if(!ImpDefs && !RegMask) |
| 2813 | return false; |
| 2814 | |
| 2815 | for (const SDep &Succ : SU->Succs) { |
| 2816 | SUnit *SuccSU = Succ.getSUnit(); |
| 2817 | for (const SDep &SuccPred : SuccSU->Preds) { |
| 2818 | if (!SuccPred.isAssignedRegDep()) |
| 2819 | continue; |
| 2820 | |
| 2821 | if (RegMask && |
| 2822 | MachineOperand::clobbersPhysReg(RegMask, SuccPred.getReg()) && |
| 2823 | scheduleDAG->IsReachable(DepSU, SuccPred.getSUnit())) |
| 2824 | return true; |
| 2825 | |
| 2826 | if (ImpDefs) |
| 2827 | for (const MCPhysReg *ImpDef = ImpDefs; *ImpDef; ++ImpDef) |
| 2828 | // Return true if SU clobbers this physical register use and the |
| 2829 | // definition of the register reaches from DepSU. IsReachable queries |
| 2830 | // a topological forward sort of the DAG (following the successors). |
| 2831 | if (TRI->regsOverlap(*ImpDef, SuccPred.getReg()) && |
| 2832 | scheduleDAG->IsReachable(DepSU, SuccPred.getSUnit())) |
| 2833 | return true; |
| 2834 | } |
| 2835 | } |
| 2836 | return false; |
| 2837 | } |
| 2838 | |
| 2839 | /// canClobberPhysRegDefs - True if SU would clobber one of SuccSU's |
| 2840 | /// physical register defs. |
| 2841 | static bool canClobberPhysRegDefs(const SUnit *SuccSU, const SUnit *SU, |
| 2842 | const TargetInstrInfo *TII, |
| 2843 | const TargetRegisterInfo *TRI) { |
| 2844 | SDNode *N = SuccSU->getNode(); |
| 2845 | unsigned NumDefs = TII->get(N->getMachineOpcode()).getNumDefs(); |
| 2846 | const MCPhysReg *ImpDefs = TII->get(N->getMachineOpcode()).getImplicitDefs(); |
| 2847 | assert(ImpDefs && "Caller should check hasPhysRegDefs")(static_cast <bool> (ImpDefs && "Caller should check hasPhysRegDefs" ) ? void (0) : __assert_fail ("ImpDefs && \"Caller should check hasPhysRegDefs\"" , "/build/llvm-toolchain-snapshot-7~svn329677/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp" , 2847, __extension__ __PRETTY_FUNCTION__)); |
| 2848 | for (const SDNode *SUNode = SU->getNode(); SUNode; |
| 2849 | SUNode = SUNode->getGluedNode()) { |
| 2850 | if (!SUNode->isMachineOpcode()) |
| 2851 | continue; |
| 2852 | const MCPhysReg *SUImpDefs = |
| 2853 | TII->get(SUNode->getMachineOpcode()).getImplicitDefs(); |
| 2854 | const uint32_t *SURegMask = getNodeRegMask(SUNode); |
| 2855 | if (!SUImpDefs && !SURegMask) |
| 2856 | continue; |
| 2857 | for (unsigned i = NumDefs, e = N->getNumValues(); i != e; ++i) { |
| 2858 | MVT VT = N->getSimpleValueType(i); |
| 2859 | if (VT == MVT::Glue || VT == MVT::Other) |
| 2860 | continue; |
| 2861 | if (!N->hasAnyUseOfValue(i)) |
| 2862 | continue; |
| 2863 | unsigned Reg = ImpDefs[i - NumDefs]; |
| 2864 | if (SURegMask && MachineOperand::clobbersPhysReg(SURegMask, Reg)) |
| 2865 | return true; |
| 2866 | if (!SUImpDefs) |
| 2867 | continue; |
| 2868 | for (;*SUImpDefs; ++SUImpDefs) { |
| 2869 | unsigned SUReg = *SUImpDefs; |
| 2870 | if (TRI->regsOverlap(Reg, SUReg)) |
| 2871 | return true; |
| 2872 | } |
| 2873 | } |
| 2874 | } |
| 2875 | return false; |
| 2876 | } |
| 2877 | |
| 2878 | /// PrescheduleNodesWithMultipleUses - Nodes with multiple uses |
| 2879 | /// are not handled well by the general register pressure reduction |
| 2880 | /// heuristics. When presented with code like this: |
| 2881 | /// |
| 2882 | /// N |
| 2883 | /// / | |
| 2884 | /// / | |
| 2885 | /// U store |
| 2886 | /// | |
| 2887 | /// ... |
| 2888 | /// |
| 2889 | /// the heuristics tend to push the store up, but since the |
| 2890 | /// operand of the store has another use (U), this would increase |
| 2891 | /// the length of that other use (the U->N edge). |
| 2892 | /// |
| 2893 | /// This function transforms code like the above to route U's |
| 2894 | /// dependence through the store when possible, like this: |
| 2895 | /// |
| 2896 | /// N |
| 2897 | /// || |
| 2898 | /// || |
| 2899 | /// store |
| 2900 | /// | |
| 2901 | /// U |
| 2902 | /// | |
| 2903 | /// ... |
| 2904 | /// |
| 2905 | /// This results in the store being scheduled immediately |
| 2906 | /// after N, which shortens the U->N live range, reducing |
| 2907 | /// register pressure. |
| 2908 | void RegReductionPQBase::PrescheduleNodesWithMultipleUses() { |
| 2909 | // Visit all the nodes in topological order, working top-down. |
| 2910 | for (SUnit &SU : *SUnits) { |
| 2911 | // For now, only look at nodes with no data successors, such as stores. |
| 2912 | // These are especially important, due to the heuristics in |
| 2913 | // getNodePriority for nodes with no data successors. |
| 2914 | if (SU.NumSuccs != 0) |
| 2915 | continue; |
| 2916 | // For now, only look at nodes with exactly one data predecessor. |
| 2917 | if (SU.NumPreds != 1) |
| 2918 | continue; |
| 2919 | // Avoid prescheduling copies to virtual registers, which don't behave |
| 2920 | // like other nodes from the perspective of scheduling heuristics. |
| 2921 | if (SDNode *N = SU.getNode()) |
| 2922 | if (N->getOpcode() == ISD::CopyToReg && |
| 2923 | TargetRegisterInfo::isVirtualRegister |
| 2924 | (cast<RegisterSDNode>(N->getOperand(1))->getReg())) |
| 2925 | continue; |
| 2926 | |
| 2927 | // Locate the single data predecessor. |
| 2928 | SUnit *PredSU = nullptr; |
| 2929 | for (const SDep &Pred : SU.Preds) |
| 2930 | if (!Pred.isCtrl()) { |
| 2931 | PredSU = Pred.getSUnit(); |
| 2932 | break; |
| 2933 | } |
| 2934 | assert(PredSU)(static_cast <bool> (PredSU) ? void (0) : __assert_fail ("PredSU", "/build/llvm-toolchain-snapshot-7~svn329677/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp" , 2934, __extension__ __PRETTY_FUNCTION__)); |
| 2935 | |
| 2936 | // Don't rewrite edges that carry physregs, because that requires additional |
| 2937 | // support infrastructure. |
| 2938 | if (PredSU->hasPhysRegDefs) |
| 2939 | continue; |
| 2940 | // Short-circuit the case where SU is PredSU's only data successor. |
| 2941 | if (PredSU->NumSuccs == 1) |
| 2942 | continue; |
| 2943 | // Avoid prescheduling to copies from virtual registers, which don't behave |
| 2944 | // like other nodes from the perspective of scheduling heuristics. |
| 2945 | if (SDNode *N = SU.getNode()) |
| 2946 | if (N->getOpcode() == ISD::CopyFromReg && |
| 2947 | TargetRegisterInfo::isVirtualRegister |
| 2948 | (cast<RegisterSDNode>(N->getOperand(1))->getReg())) |
| 2949 | continue; |
| 2950 | |
| 2951 | // Perform checks on the successors of PredSU. |
| 2952 | for (const SDep &PredSucc : PredSU->Succs) { |
| 2953 | SUnit *PredSuccSU = PredSucc.getSUnit(); |
| 2954 | if (PredSuccSU == &SU) continue; |
| 2955 | // If PredSU has another successor with no data successors, for |
| 2956 | // now don't attempt to choose either over the other. |
| 2957 | if (PredSuccSU->NumSuccs == 0) |
| 2958 | goto outer_loop_continue; |
| 2959 | // Don't break physical register dependencies. |
| 2960 | if (SU.hasPhysRegClobbers && PredSuccSU->hasPhysRegDefs) |
| 2961 | if (canClobberPhysRegDefs(PredSuccSU, &SU, TII, TRI)) |
| 2962 | goto outer_loop_continue; |
| 2963 | // Don't introduce graph cycles. |
| 2964 | if (scheduleDAG->IsReachable(&SU, PredSuccSU)) |
| 2965 | goto outer_loop_continue; |
| 2966 | } |
| 2967 | |
| 2968 | // Ok, the transformation is safe and the heuristics suggest it is |
| 2969 | // profitable. Update the graph. |
| 2970 | DEBUG(dbgs() << " Prescheduling SU #" << SU.NodeNumdo { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType ("pre-RA-sched")) { dbgs() << " Prescheduling SU #" << SU.NodeNum << " next to PredSU #" << PredSU-> NodeNum << " to guide scheduling in the presence of multiple uses\n" ; } } while (false) |
| 2971 | << " next to PredSU #" << PredSU->NodeNumdo { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType ("pre-RA-sched")) { dbgs() << " Prescheduling SU #" << SU.NodeNum << " next to PredSU #" << PredSU-> NodeNum << " to guide scheduling in the presence of multiple uses\n" ; } } while (false) |
| 2972 | << " to guide scheduling in the presence of multiple uses\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType ("pre-RA-sched")) { dbgs() << " Prescheduling SU #" << SU.NodeNum << " next to PredSU #" << PredSU-> NodeNum << " to guide scheduling in the presence of multiple uses\n" ; } } while (false); |
| 2973 | for (unsigned i = 0; i != PredSU->Succs.size(); ++i) { |
| 2974 | SDep Edge = PredSU->Succs[i]; |
| 2975 | assert(!Edge.isAssignedRegDep())(static_cast <bool> (!Edge.isAssignedRegDep()) ? void ( 0) : __assert_fail ("!Edge.isAssignedRegDep()", "/build/llvm-toolchain-snapshot-7~svn329677/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp" , 2975, __extension__ __PRETTY_FUNCTION__)); |
| 2976 | SUnit *SuccSU = Edge.getSUnit(); |
| 2977 | if (SuccSU != &SU) { |
| 2978 | Edge.setSUnit(PredSU); |
| 2979 | scheduleDAG->RemovePred(SuccSU, Edge); |
| 2980 | scheduleDAG->AddPred(&SU, Edge); |
| 2981 | Edge.setSUnit(&SU); |
| 2982 | scheduleDAG->AddPred(SuccSU, Edge); |
| 2983 | --i; |
| 2984 | } |
| 2985 | } |
| 2986 | outer_loop_continue:; |
| 2987 | } |
| 2988 | } |
| 2989 | |
| 2990 | /// AddPseudoTwoAddrDeps - If two nodes share an operand and one of them uses |
| 2991 | /// it as a def&use operand. Add a pseudo control edge from it to the other |
| 2992 | /// node (if it won't create a cycle) so the two-address one will be scheduled |
| 2993 | /// first (lower in the schedule). If both nodes are two-address, favor the |
| 2994 | /// one that has a CopyToReg use (more likely to be a loop induction update). |
| 2995 | /// If both are two-address, but one is commutable while the other is not |
| 2996 | /// commutable, favor the one that's not commutable. |
| 2997 | void RegReductionPQBase::AddPseudoTwoAddrDeps() { |
| 2998 | for (SUnit &SU : *SUnits) { |
| 2999 | if (!SU.isTwoAddress) |
| 3000 | continue; |
| 3001 | |
| 3002 | SDNode *Node = SU.getNode(); |
| 3003 | if (!Node || !Node->isMachineOpcode() || SU.getNode()->getGluedNode()) |
| 3004 | continue; |
| 3005 | |
| 3006 | bool isLiveOut = hasOnlyLiveOutUses(&SU); |
| 3007 | unsigned Opc = Node->getMachineOpcode(); |
| 3008 | const MCInstrDesc &MCID = TII->get(Opc); |
| 3009 | unsigned NumRes = MCID.getNumDefs(); |
| 3010 | unsigned NumOps = MCID.getNumOperands() - NumRes; |
| 3011 | for (unsigned j = 0; j != NumOps; ++j) { |
| 3012 | if (MCID.getOperandConstraint(j+NumRes, MCOI::TIED_TO) == -1) |
| 3013 | continue; |
| 3014 | SDNode *DU = SU.getNode()->getOperand(j).getNode(); |
| 3015 | if (DU->getNodeId() == -1) |
| 3016 | continue; |
| 3017 | const SUnit *DUSU = &(*SUnits)[DU->getNodeId()]; |
| 3018 | if (!DUSU) |
| 3019 | continue; |
| 3020 | for (const SDep &Succ : DUSU->Succs) { |
| 3021 | if (Succ.isCtrl()) |
| 3022 | continue; |
| 3023 | SUnit *SuccSU = Succ.getSUnit(); |
| 3024 | if (SuccSU == &SU) |
| 3025 | continue; |
| 3026 | // Be conservative. Ignore if nodes aren't at roughly the same |
| 3027 | // depth and height. |
| 3028 | if (SuccSU->getHeight() < SU.getHeight() && |
| 3029 | (SU.getHeight() - SuccSU->getHeight()) > 1) |
| 3030 | continue; |
| 3031 | // Skip past COPY_TO_REGCLASS nodes, so that the pseudo edge |
| 3032 | // constrains whatever is using the copy, instead of the copy |
| 3033 | // itself. In the case that the copy is coalesced, this |
| 3034 | // preserves the intent of the pseudo two-address heurietics. |
| 3035 | while (SuccSU->Succs.size() == 1 && |
| 3036 | SuccSU->getNode()->isMachineOpcode() && |
| 3037 | SuccSU->getNode()->getMachineOpcode() == |
| 3038 | TargetOpcode::COPY_TO_REGCLASS) |
| 3039 | SuccSU = SuccSU->Succs.front().getSUnit(); |
| 3040 | // Don't constrain non-instruction nodes. |
| 3041 | if (!SuccSU->getNode() || !SuccSU->getNode()->isMachineOpcode()) |
| 3042 | continue; |
| 3043 | // Don't constrain nodes with physical register defs if the |
| 3044 | // predecessor can clobber them. |
| 3045 | if (SuccSU->hasPhysRegDefs && SU.hasPhysRegClobbers) { |
| 3046 | if (canClobberPhysRegDefs(SuccSU, &SU, TII, TRI)) |
| 3047 | continue; |
| 3048 | } |
| 3049 | // Don't constrain EXTRACT_SUBREG, INSERT_SUBREG, and SUBREG_TO_REG; |
| 3050 | // these may be coalesced away. We want them close to their uses. |
| 3051 | unsigned SuccOpc = SuccSU->getNode()->getMachineOpcode(); |
| 3052 | if (SuccOpc == TargetOpcode::EXTRACT_SUBREG || |
| 3053 | SuccOpc == TargetOpcode::INSERT_SUBREG || |
| 3054 | SuccOpc == TargetOpcode::SUBREG_TO_REG) |
| 3055 | continue; |
| 3056 | if (!canClobberReachingPhysRegUse(SuccSU, &SU, scheduleDAG, TII, TRI) && |
| 3057 | (!canClobber(SuccSU, DUSU) || |
| 3058 | (isLiveOut && !hasOnlyLiveOutUses(SuccSU)) || |
| 3059 | (!SU.isCommutable && SuccSU->isCommutable)) && |
| 3060 | !scheduleDAG->IsReachable(SuccSU, &SU)) { |
| 3061 | DEBUG(dbgs() << " Adding a pseudo-two-addr edge from SU #"do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType ("pre-RA-sched")) { dbgs() << " Adding a pseudo-two-addr edge from SU #" << SU.NodeNum << " to SU #" << SuccSU-> NodeNum << "\n"; } } while (false) |
| 3062 | << SU.NodeNum << " to SU #" << SuccSU->NodeNum << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType ("pre-RA-sched")) { dbgs() << " Adding a pseudo-two-addr edge from SU #" << SU.NodeNum << " to SU #" << SuccSU-> NodeNum << "\n"; } } while (false); |
| 3063 | scheduleDAG->AddPred(&SU, SDep(SuccSU, SDep::Artificial)); |
| 3064 | } |
| 3065 | } |
| 3066 | } |
| 3067 | } |
| 3068 | } |
| 3069 | |
| 3070 | //===----------------------------------------------------------------------===// |
| 3071 | // Public Constructor Functions |
| 3072 | //===----------------------------------------------------------------------===// |
| 3073 | |
| 3074 | ScheduleDAGSDNodes * |
| 3075 | llvm::createBURRListDAGScheduler(SelectionDAGISel *IS, |
| 3076 | CodeGenOpt::Level OptLevel) { |
| 3077 | const TargetSubtargetInfo &STI = IS->MF->getSubtarget(); |
| 3078 | const TargetInstrInfo *TII = STI.getInstrInfo(); |
| 3079 | const TargetRegisterInfo *TRI = STI.getRegisterInfo(); |
| 3080 | |
| 3081 | BURegReductionPriorityQueue *PQ = |
| 3082 | new BURegReductionPriorityQueue(*IS->MF, false, false, TII, TRI, nullptr); |
| 3083 | ScheduleDAGRRList *SD = new ScheduleDAGRRList(*IS->MF, false, PQ, OptLevel); |
| 3084 | PQ->setScheduleDAG(SD); |
| 3085 | return SD; |
| 3086 | } |
| 3087 | |
| 3088 | ScheduleDAGSDNodes * |
| 3089 | llvm::createSourceListDAGScheduler(SelectionDAGISel *IS, |
| 3090 | CodeGenOpt::Level OptLevel) { |
| 3091 | const TargetSubtargetInfo &STI = IS->MF->getSubtarget(); |
| 3092 | const TargetInstrInfo *TII = STI.getInstrInfo(); |
| 3093 | const TargetRegisterInfo *TRI = STI.getRegisterInfo(); |
| 3094 | |
| 3095 | SrcRegReductionPriorityQueue *PQ = |
| 3096 | new SrcRegReductionPriorityQueue(*IS->MF, false, true, TII, TRI, nullptr); |
| 3097 | ScheduleDAGRRList *SD = new ScheduleDAGRRList(*IS->MF, false, PQ, OptLevel); |
| 3098 | PQ->setScheduleDAG(SD); |
| 3099 | return SD; |
| 3100 | } |
| 3101 | |
| 3102 | ScheduleDAGSDNodes * |
| 3103 | llvm::createHybridListDAGScheduler(SelectionDAGISel *IS, |
| 3104 | CodeGenOpt::Level OptLevel) { |
| 3105 | const TargetSubtargetInfo &STI = IS->MF->getSubtarget(); |
| 3106 | const TargetInstrInfo *TII = STI.getInstrInfo(); |
| 3107 | const TargetRegisterInfo *TRI = STI.getRegisterInfo(); |
| 3108 | const TargetLowering *TLI = IS->TLI; |
| 3109 | |
| 3110 | HybridBURRPriorityQueue *PQ = |
| 3111 | new HybridBURRPriorityQueue(*IS->MF, true, false, TII, TRI, TLI); |
| 3112 | |
| 3113 | ScheduleDAGRRList *SD = new ScheduleDAGRRList(*IS->MF, true, PQ, OptLevel); |
| 3114 | PQ->setScheduleDAG(SD); |
| 3115 | return SD; |
| 3116 | } |
| 3117 | |
| 3118 | ScheduleDAGSDNodes * |
| 3119 | llvm::createILPListDAGScheduler(SelectionDAGISel *IS, |
| 3120 | CodeGenOpt::Level OptLevel) { |
| 3121 | const TargetSubtargetInfo &STI = IS->MF->getSubtarget(); |
| 3122 | const TargetInstrInfo *TII = STI.getInstrInfo(); |
| 3123 | const TargetRegisterInfo *TRI = STI.getRegisterInfo(); |
| 3124 | const TargetLowering *TLI = IS->TLI; |
| 3125 | |
| 3126 | ILPBURRPriorityQueue *PQ = |
| 3127 | new ILPBURRPriorityQueue(*IS->MF, true, false, TII, TRI, TLI); |
| 3128 | ScheduleDAGRRList *SD = new ScheduleDAGRRList(*IS->MF, true, PQ, OptLevel); |
| 3129 | PQ->setScheduleDAG(SD); |
| 3130 | return SD; |
| 3131 | } |