| File: | lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp |
| Warning: | line 7225, column 14 Forming reference to null pointer |
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| 1 | //===- SelectionDAGBuilder.cpp - Selection-DAG building -------------------===// | |||
| 2 | // | |||
| 3 | // The LLVM Compiler Infrastructure | |||
| 4 | // | |||
| 5 | // This file is distributed under the University of Illinois Open Source | |||
| 6 | // License. See LICENSE.TXT for details. | |||
| 7 | // | |||
| 8 | //===----------------------------------------------------------------------===// | |||
| 9 | // | |||
| 10 | // This implements routines for translating from LLVM IR into SelectionDAG IR. | |||
| 11 | // | |||
| 12 | //===----------------------------------------------------------------------===// | |||
| 13 | ||||
| 14 | #include "SelectionDAGBuilder.h" | |||
| 15 | #include "SDNodeDbgValue.h" | |||
| 16 | #include "llvm/ADT/APFloat.h" | |||
| 17 | #include "llvm/ADT/APInt.h" | |||
| 18 | #include "llvm/ADT/ArrayRef.h" | |||
| 19 | #include "llvm/ADT/BitVector.h" | |||
| 20 | #include "llvm/ADT/DenseMap.h" | |||
| 21 | #include "llvm/ADT/None.h" | |||
| 22 | #include "llvm/ADT/Optional.h" | |||
| 23 | #include "llvm/ADT/STLExtras.h" | |||
| 24 | #include "llvm/ADT/SmallPtrSet.h" | |||
| 25 | #include "llvm/ADT/SmallSet.h" | |||
| 26 | #include "llvm/ADT/SmallVector.h" | |||
| 27 | #include "llvm/ADT/StringRef.h" | |||
| 28 | #include "llvm/ADT/Triple.h" | |||
| 29 | #include "llvm/ADT/Twine.h" | |||
| 30 | #include "llvm/Analysis/AliasAnalysis.h" | |||
| 31 | #include "llvm/Analysis/BranchProbabilityInfo.h" | |||
| 32 | #include "llvm/Analysis/ConstantFolding.h" | |||
| 33 | #include "llvm/Analysis/EHPersonalities.h" | |||
| 34 | #include "llvm/Analysis/Loads.h" | |||
| 35 | #include "llvm/Analysis/MemoryLocation.h" | |||
| 36 | #include "llvm/Analysis/TargetLibraryInfo.h" | |||
| 37 | #include "llvm/Analysis/ValueTracking.h" | |||
| 38 | #include "llvm/Analysis/VectorUtils.h" | |||
| 39 | #include "llvm/CodeGen/Analysis.h" | |||
| 40 | #include "llvm/CodeGen/FunctionLoweringInfo.h" | |||
| 41 | #include "llvm/CodeGen/GCMetadata.h" | |||
| 42 | #include "llvm/CodeGen/ISDOpcodes.h" | |||
| 43 | #include "llvm/CodeGen/MachineBasicBlock.h" | |||
| 44 | #include "llvm/CodeGen/MachineFrameInfo.h" | |||
| 45 | #include "llvm/CodeGen/MachineFunction.h" | |||
| 46 | #include "llvm/CodeGen/MachineInstr.h" | |||
| 47 | #include "llvm/CodeGen/MachineInstrBuilder.h" | |||
| 48 | #include "llvm/CodeGen/MachineJumpTableInfo.h" | |||
| 49 | #include "llvm/CodeGen/MachineMemOperand.h" | |||
| 50 | #include "llvm/CodeGen/MachineModuleInfo.h" | |||
| 51 | #include "llvm/CodeGen/MachineOperand.h" | |||
| 52 | #include "llvm/CodeGen/MachineRegisterInfo.h" | |||
| 53 | #include "llvm/CodeGen/RuntimeLibcalls.h" | |||
| 54 | #include "llvm/CodeGen/SelectionDAG.h" | |||
| 55 | #include "llvm/CodeGen/SelectionDAGNodes.h" | |||
| 56 | #include "llvm/CodeGen/SelectionDAGTargetInfo.h" | |||
| 57 | #include "llvm/CodeGen/StackMaps.h" | |||
| 58 | #include "llvm/CodeGen/TargetFrameLowering.h" | |||
| 59 | #include "llvm/CodeGen/TargetInstrInfo.h" | |||
| 60 | #include "llvm/CodeGen/TargetLowering.h" | |||
| 61 | #include "llvm/CodeGen/TargetOpcodes.h" | |||
| 62 | #include "llvm/CodeGen/TargetRegisterInfo.h" | |||
| 63 | #include "llvm/CodeGen/TargetSubtargetInfo.h" | |||
| 64 | #include "llvm/CodeGen/ValueTypes.h" | |||
| 65 | #include "llvm/CodeGen/WinEHFuncInfo.h" | |||
| 66 | #include "llvm/IR/Argument.h" | |||
| 67 | #include "llvm/IR/Attributes.h" | |||
| 68 | #include "llvm/IR/BasicBlock.h" | |||
| 69 | #include "llvm/IR/CFG.h" | |||
| 70 | #include "llvm/IR/CallSite.h" | |||
| 71 | #include "llvm/IR/CallingConv.h" | |||
| 72 | #include "llvm/IR/Constant.h" | |||
| 73 | #include "llvm/IR/ConstantRange.h" | |||
| 74 | #include "llvm/IR/Constants.h" | |||
| 75 | #include "llvm/IR/DataLayout.h" | |||
| 76 | #include "llvm/IR/DebugInfoMetadata.h" | |||
| 77 | #include "llvm/IR/DebugLoc.h" | |||
| 78 | #include "llvm/IR/DerivedTypes.h" | |||
| 79 | #include "llvm/IR/Function.h" | |||
| 80 | #include "llvm/IR/GetElementPtrTypeIterator.h" | |||
| 81 | #include "llvm/IR/InlineAsm.h" | |||
| 82 | #include "llvm/IR/InstrTypes.h" | |||
| 83 | #include "llvm/IR/Instruction.h" | |||
| 84 | #include "llvm/IR/Instructions.h" | |||
| 85 | #include "llvm/IR/IntrinsicInst.h" | |||
| 86 | #include "llvm/IR/Intrinsics.h" | |||
| 87 | #include "llvm/IR/LLVMContext.h" | |||
| 88 | #include "llvm/IR/Metadata.h" | |||
| 89 | #include "llvm/IR/Module.h" | |||
| 90 | #include "llvm/IR/Operator.h" | |||
| 91 | #include "llvm/IR/Statepoint.h" | |||
| 92 | #include "llvm/IR/Type.h" | |||
| 93 | #include "llvm/IR/User.h" | |||
| 94 | #include "llvm/IR/Value.h" | |||
| 95 | #include "llvm/MC/MCContext.h" | |||
| 96 | #include "llvm/MC/MCSymbol.h" | |||
| 97 | #include "llvm/Support/AtomicOrdering.h" | |||
| 98 | #include "llvm/Support/BranchProbability.h" | |||
| 99 | #include "llvm/Support/Casting.h" | |||
| 100 | #include "llvm/Support/CodeGen.h" | |||
| 101 | #include "llvm/Support/CommandLine.h" | |||
| 102 | #include "llvm/Support/Compiler.h" | |||
| 103 | #include "llvm/Support/Debug.h" | |||
| 104 | #include "llvm/Support/ErrorHandling.h" | |||
| 105 | #include "llvm/Support/MachineValueType.h" | |||
| 106 | #include "llvm/Support/MathExtras.h" | |||
| 107 | #include "llvm/Support/raw_ostream.h" | |||
| 108 | #include "llvm/Target/TargetIntrinsicInfo.h" | |||
| 109 | #include "llvm/Target/TargetMachine.h" | |||
| 110 | #include "llvm/Target/TargetOptions.h" | |||
| 111 | #include <algorithm> | |||
| 112 | #include <cassert> | |||
| 113 | #include <cstddef> | |||
| 114 | #include <cstdint> | |||
| 115 | #include <cstring> | |||
| 116 | #include <iterator> | |||
| 117 | #include <limits> | |||
| 118 | #include <numeric> | |||
| 119 | #include <tuple> | |||
| 120 | #include <utility> | |||
| 121 | #include <vector> | |||
| 122 | ||||
| 123 | using namespace llvm; | |||
| 124 | ||||
| 125 | #define DEBUG_TYPE"isel" "isel" | |||
| 126 | ||||
| 127 | /// LimitFloatPrecision - Generate low-precision inline sequences for | |||
| 128 | /// some float libcalls (6, 8 or 12 bits). | |||
| 129 | static unsigned LimitFloatPrecision; | |||
| 130 | ||||
| 131 | static cl::opt<unsigned, true> | |||
| 132 | LimitFPPrecision("limit-float-precision", | |||
| 133 | cl::desc("Generate low-precision inline sequences " | |||
| 134 | "for some float libcalls"), | |||
| 135 | cl::location(LimitFloatPrecision), cl::Hidden, | |||
| 136 | cl::init(0)); | |||
| 137 | ||||
| 138 | static cl::opt<unsigned> SwitchPeelThreshold( | |||
| 139 | "switch-peel-threshold", cl::Hidden, cl::init(66), | |||
| 140 | cl::desc("Set the case probability threshold for peeling the case from a " | |||
| 141 | "switch statement. A value greater than 100 will void this " | |||
| 142 | "optimization")); | |||
| 143 | ||||
| 144 | // Limit the width of DAG chains. This is important in general to prevent | |||
| 145 | // DAG-based analysis from blowing up. For example, alias analysis and | |||
| 146 | // load clustering may not complete in reasonable time. It is difficult to | |||
| 147 | // recognize and avoid this situation within each individual analysis, and | |||
| 148 | // future analyses are likely to have the same behavior. Limiting DAG width is | |||
| 149 | // the safe approach and will be especially important with global DAGs. | |||
| 150 | // | |||
| 151 | // MaxParallelChains default is arbitrarily high to avoid affecting | |||
| 152 | // optimization, but could be lowered to improve compile time. Any ld-ld-st-st | |||
| 153 | // sequence over this should have been converted to llvm.memcpy by the | |||
| 154 | // frontend. It is easy to induce this behavior with .ll code such as: | |||
| 155 | // %buffer = alloca [4096 x i8] | |||
| 156 | // %data = load [4096 x i8]* %argPtr | |||
| 157 | // store [4096 x i8] %data, [4096 x i8]* %buffer | |||
| 158 | static const unsigned MaxParallelChains = 64; | |||
| 159 | ||||
| 160 | // True if the Value passed requires ABI mangling as it is a parameter to a | |||
| 161 | // function or a return value from a function which is not an intrinsic. | |||
| 162 | static bool isABIRegCopy(const Value *V) { | |||
| 163 | const bool IsRetInst = V && isa<ReturnInst>(V); | |||
| 164 | const bool IsCallInst = V && isa<CallInst>(V); | |||
| 165 | const bool IsInLineAsm = | |||
| 166 | IsCallInst && static_cast<const CallInst *>(V)->isInlineAsm(); | |||
| 167 | const bool IsIndirectFunctionCall = | |||
| 168 | IsCallInst && !IsInLineAsm && | |||
| 169 | !static_cast<const CallInst *>(V)->getCalledFunction(); | |||
| 170 | // It is possible that the call instruction is an inline asm statement or an | |||
| 171 | // indirect function call in which case the return value of | |||
| 172 | // getCalledFunction() would be nullptr. | |||
| 173 | const bool IsInstrinsicCall = | |||
| 174 | IsCallInst && !IsInLineAsm && !IsIndirectFunctionCall && | |||
| 175 | static_cast<const CallInst *>(V)->getCalledFunction()->getIntrinsicID() != | |||
| 176 | Intrinsic::not_intrinsic; | |||
| 177 | ||||
| 178 | return IsRetInst || (IsCallInst && (!IsInLineAsm && !IsInstrinsicCall)); | |||
| 179 | } | |||
| 180 | ||||
| 181 | static SDValue getCopyFromPartsVector(SelectionDAG &DAG, const SDLoc &DL, | |||
| 182 | const SDValue *Parts, unsigned NumParts, | |||
| 183 | MVT PartVT, EVT ValueVT, const Value *V, | |||
| 184 | bool IsABIRegCopy); | |||
| 185 | ||||
| 186 | /// getCopyFromParts - Create a value that contains the specified legal parts | |||
| 187 | /// combined into the value they represent. If the parts combine to a type | |||
| 188 | /// larger than ValueVT then AssertOp can be used to specify whether the extra | |||
| 189 | /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT | |||
| 190 | /// (ISD::AssertSext). | |||
| 191 | static SDValue getCopyFromParts(SelectionDAG &DAG, const SDLoc &DL, | |||
| 192 | const SDValue *Parts, unsigned NumParts, | |||
| 193 | MVT PartVT, EVT ValueVT, const Value *V, | |||
| 194 | Optional<ISD::NodeType> AssertOp = None, | |||
| 195 | bool IsABIRegCopy = false) { | |||
| 196 | if (ValueVT.isVector()) | |||
| 197 | return getCopyFromPartsVector(DAG, DL, Parts, NumParts, | |||
| 198 | PartVT, ValueVT, V, IsABIRegCopy); | |||
| 199 | ||||
| 200 | assert(NumParts > 0 && "No parts to assemble!")(static_cast <bool> (NumParts > 0 && "No parts to assemble!" ) ? void (0) : __assert_fail ("NumParts > 0 && \"No parts to assemble!\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 200, __extension__ __PRETTY_FUNCTION__)); | |||
| 201 | const TargetLowering &TLI = DAG.getTargetLoweringInfo(); | |||
| 202 | SDValue Val = Parts[0]; | |||
| 203 | ||||
| 204 | if (NumParts > 1) { | |||
| 205 | // Assemble the value from multiple parts. | |||
| 206 | if (ValueVT.isInteger()) { | |||
| 207 | unsigned PartBits = PartVT.getSizeInBits(); | |||
| 208 | unsigned ValueBits = ValueVT.getSizeInBits(); | |||
| 209 | ||||
| 210 | // Assemble the power of 2 part. | |||
| 211 | unsigned RoundParts = NumParts & (NumParts - 1) ? | |||
| 212 | 1 << Log2_32(NumParts) : NumParts; | |||
| 213 | unsigned RoundBits = PartBits * RoundParts; | |||
| 214 | EVT RoundVT = RoundBits == ValueBits ? | |||
| 215 | ValueVT : EVT::getIntegerVT(*DAG.getContext(), RoundBits); | |||
| 216 | SDValue Lo, Hi; | |||
| 217 | ||||
| 218 | EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), RoundBits/2); | |||
| 219 | ||||
| 220 | if (RoundParts > 2) { | |||
| 221 | Lo = getCopyFromParts(DAG, DL, Parts, RoundParts / 2, | |||
| 222 | PartVT, HalfVT, V); | |||
| 223 | Hi = getCopyFromParts(DAG, DL, Parts + RoundParts / 2, | |||
| 224 | RoundParts / 2, PartVT, HalfVT, V); | |||
| 225 | } else { | |||
| 226 | Lo = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[0]); | |||
| 227 | Hi = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[1]); | |||
| 228 | } | |||
| 229 | ||||
| 230 | if (DAG.getDataLayout().isBigEndian()) | |||
| 231 | std::swap(Lo, Hi); | |||
| 232 | ||||
| 233 | Val = DAG.getNode(ISD::BUILD_PAIR, DL, RoundVT, Lo, Hi); | |||
| 234 | ||||
| 235 | if (RoundParts < NumParts) { | |||
| 236 | // Assemble the trailing non-power-of-2 part. | |||
| 237 | unsigned OddParts = NumParts - RoundParts; | |||
| 238 | EVT OddVT = EVT::getIntegerVT(*DAG.getContext(), OddParts * PartBits); | |||
| 239 | Hi = getCopyFromParts(DAG, DL, | |||
| 240 | Parts + RoundParts, OddParts, PartVT, OddVT, V); | |||
| 241 | ||||
| 242 | // Combine the round and odd parts. | |||
| 243 | Lo = Val; | |||
| 244 | if (DAG.getDataLayout().isBigEndian()) | |||
| 245 | std::swap(Lo, Hi); | |||
| 246 | EVT TotalVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits); | |||
| 247 | Hi = DAG.getNode(ISD::ANY_EXTEND, DL, TotalVT, Hi); | |||
| 248 | Hi = | |||
| 249 | DAG.getNode(ISD::SHL, DL, TotalVT, Hi, | |||
| 250 | DAG.getConstant(Lo.getValueSizeInBits(), DL, | |||
| 251 | TLI.getPointerTy(DAG.getDataLayout()))); | |||
| 252 | Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, TotalVT, Lo); | |||
| 253 | Val = DAG.getNode(ISD::OR, DL, TotalVT, Lo, Hi); | |||
| 254 | } | |||
| 255 | } else if (PartVT.isFloatingPoint()) { | |||
| 256 | // FP split into multiple FP parts (for ppcf128) | |||
| 257 | assert(ValueVT == EVT(MVT::ppcf128) && PartVT == MVT::f64 &&(static_cast <bool> (ValueVT == EVT(MVT::ppcf128) && PartVT == MVT::f64 && "Unexpected split") ? void (0) : __assert_fail ("ValueVT == EVT(MVT::ppcf128) && PartVT == MVT::f64 && \"Unexpected split\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 258, __extension__ __PRETTY_FUNCTION__)) | |||
| 258 | "Unexpected split")(static_cast <bool> (ValueVT == EVT(MVT::ppcf128) && PartVT == MVT::f64 && "Unexpected split") ? void (0) : __assert_fail ("ValueVT == EVT(MVT::ppcf128) && PartVT == MVT::f64 && \"Unexpected split\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 258, __extension__ __PRETTY_FUNCTION__)); | |||
| 259 | SDValue Lo, Hi; | |||
| 260 | Lo = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[0]); | |||
| 261 | Hi = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[1]); | |||
| 262 | if (TLI.hasBigEndianPartOrdering(ValueVT, DAG.getDataLayout())) | |||
| 263 | std::swap(Lo, Hi); | |||
| 264 | Val = DAG.getNode(ISD::BUILD_PAIR, DL, ValueVT, Lo, Hi); | |||
| 265 | } else { | |||
| 266 | // FP split into integer parts (soft fp) | |||
| 267 | assert(ValueVT.isFloatingPoint() && PartVT.isInteger() &&(static_cast <bool> (ValueVT.isFloatingPoint() && PartVT.isInteger() && !PartVT.isVector() && "Unexpected split" ) ? void (0) : __assert_fail ("ValueVT.isFloatingPoint() && PartVT.isInteger() && !PartVT.isVector() && \"Unexpected split\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 268, __extension__ __PRETTY_FUNCTION__)) | |||
| 268 | !PartVT.isVector() && "Unexpected split")(static_cast <bool> (ValueVT.isFloatingPoint() && PartVT.isInteger() && !PartVT.isVector() && "Unexpected split" ) ? void (0) : __assert_fail ("ValueVT.isFloatingPoint() && PartVT.isInteger() && !PartVT.isVector() && \"Unexpected split\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 268, __extension__ __PRETTY_FUNCTION__)); | |||
| 269 | EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits()); | |||
| 270 | Val = getCopyFromParts(DAG, DL, Parts, NumParts, PartVT, IntVT, V); | |||
| 271 | } | |||
| 272 | } | |||
| 273 | ||||
| 274 | // There is now one part, held in Val. Correct it to match ValueVT. | |||
| 275 | // PartEVT is the type of the register class that holds the value. | |||
| 276 | // ValueVT is the type of the inline asm operation. | |||
| 277 | EVT PartEVT = Val.getValueType(); | |||
| 278 | ||||
| 279 | if (PartEVT == ValueVT) | |||
| 280 | return Val; | |||
| 281 | ||||
| 282 | if (PartEVT.isInteger() && ValueVT.isFloatingPoint() && | |||
| 283 | ValueVT.bitsLT(PartEVT)) { | |||
| 284 | // For an FP value in an integer part, we need to truncate to the right | |||
| 285 | // width first. | |||
| 286 | PartEVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits()); | |||
| 287 | Val = DAG.getNode(ISD::TRUNCATE, DL, PartEVT, Val); | |||
| 288 | } | |||
| 289 | ||||
| 290 | // Handle types that have the same size. | |||
| 291 | if (PartEVT.getSizeInBits() == ValueVT.getSizeInBits()) | |||
| 292 | return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val); | |||
| 293 | ||||
| 294 | // Handle types with different sizes. | |||
| 295 | if (PartEVT.isInteger() && ValueVT.isInteger()) { | |||
| 296 | if (ValueVT.bitsLT(PartEVT)) { | |||
| 297 | // For a truncate, see if we have any information to | |||
| 298 | // indicate whether the truncated bits will always be | |||
| 299 | // zero or sign-extension. | |||
| 300 | if (AssertOp.hasValue()) | |||
| 301 | Val = DAG.getNode(*AssertOp, DL, PartEVT, Val, | |||
| 302 | DAG.getValueType(ValueVT)); | |||
| 303 | return DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val); | |||
| 304 | } | |||
| 305 | return DAG.getNode(ISD::ANY_EXTEND, DL, ValueVT, Val); | |||
| 306 | } | |||
| 307 | ||||
| 308 | if (PartEVT.isFloatingPoint() && ValueVT.isFloatingPoint()) { | |||
| 309 | // FP_ROUND's are always exact here. | |||
| 310 | if (ValueVT.bitsLT(Val.getValueType())) | |||
| 311 | return DAG.getNode( | |||
| 312 | ISD::FP_ROUND, DL, ValueVT, Val, | |||
| 313 | DAG.getTargetConstant(1, DL, TLI.getPointerTy(DAG.getDataLayout()))); | |||
| 314 | ||||
| 315 | return DAG.getNode(ISD::FP_EXTEND, DL, ValueVT, Val); | |||
| 316 | } | |||
| 317 | ||||
| 318 | llvm_unreachable("Unknown mismatch!")::llvm::llvm_unreachable_internal("Unknown mismatch!", "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 318); | |||
| 319 | } | |||
| 320 | ||||
| 321 | static void diagnosePossiblyInvalidConstraint(LLVMContext &Ctx, const Value *V, | |||
| 322 | const Twine &ErrMsg) { | |||
| 323 | const Instruction *I = dyn_cast_or_null<Instruction>(V); | |||
| 324 | if (!V) | |||
| 325 | return Ctx.emitError(ErrMsg); | |||
| 326 | ||||
| 327 | const char *AsmError = ", possible invalid constraint for vector type"; | |||
| 328 | if (const CallInst *CI = dyn_cast<CallInst>(I)) | |||
| 329 | if (isa<InlineAsm>(CI->getCalledValue())) | |||
| 330 | return Ctx.emitError(I, ErrMsg + AsmError); | |||
| 331 | ||||
| 332 | return Ctx.emitError(I, ErrMsg); | |||
| 333 | } | |||
| 334 | ||||
| 335 | /// getCopyFromPartsVector - Create a value that contains the specified legal | |||
| 336 | /// parts combined into the value they represent. If the parts combine to a | |||
| 337 | /// type larger than ValueVT then AssertOp can be used to specify whether the | |||
| 338 | /// extra bits are known to be zero (ISD::AssertZext) or sign extended from | |||
| 339 | /// ValueVT (ISD::AssertSext). | |||
| 340 | static SDValue getCopyFromPartsVector(SelectionDAG &DAG, const SDLoc &DL, | |||
| 341 | const SDValue *Parts, unsigned NumParts, | |||
| 342 | MVT PartVT, EVT ValueVT, const Value *V, | |||
| 343 | bool IsABIRegCopy) { | |||
| 344 | assert(ValueVT.isVector() && "Not a vector value")(static_cast <bool> (ValueVT.isVector() && "Not a vector value" ) ? void (0) : __assert_fail ("ValueVT.isVector() && \"Not a vector value\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 344, __extension__ __PRETTY_FUNCTION__)); | |||
| 345 | assert(NumParts > 0 && "No parts to assemble!")(static_cast <bool> (NumParts > 0 && "No parts to assemble!" ) ? void (0) : __assert_fail ("NumParts > 0 && \"No parts to assemble!\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 345, __extension__ __PRETTY_FUNCTION__)); | |||
| 346 | const TargetLowering &TLI = DAG.getTargetLoweringInfo(); | |||
| 347 | SDValue Val = Parts[0]; | |||
| 348 | ||||
| 349 | // Handle a multi-element vector. | |||
| 350 | if (NumParts > 1) { | |||
| 351 | EVT IntermediateVT; | |||
| 352 | MVT RegisterVT; | |||
| 353 | unsigned NumIntermediates; | |||
| 354 | unsigned NumRegs; | |||
| 355 | ||||
| 356 | if (IsABIRegCopy) { | |||
| 357 | NumRegs = TLI.getVectorTypeBreakdownForCallingConv( | |||
| 358 | *DAG.getContext(), ValueVT, IntermediateVT, NumIntermediates, | |||
| 359 | RegisterVT); | |||
| 360 | } else { | |||
| 361 | NumRegs = | |||
| 362 | TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, IntermediateVT, | |||
| 363 | NumIntermediates, RegisterVT); | |||
| 364 | } | |||
| 365 | ||||
| 366 | assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!")(static_cast <bool> (NumRegs == NumParts && "Part count doesn't match vector breakdown!" ) ? void (0) : __assert_fail ("NumRegs == NumParts && \"Part count doesn't match vector breakdown!\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 366, __extension__ __PRETTY_FUNCTION__)); | |||
| 367 | NumParts = NumRegs; // Silence a compiler warning. | |||
| 368 | assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!")(static_cast <bool> (RegisterVT == PartVT && "Part type doesn't match vector breakdown!" ) ? void (0) : __assert_fail ("RegisterVT == PartVT && \"Part type doesn't match vector breakdown!\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 368, __extension__ __PRETTY_FUNCTION__)); | |||
| 369 | assert(RegisterVT.getSizeInBits() ==(static_cast <bool> (RegisterVT.getSizeInBits() == Parts [0].getSimpleValueType().getSizeInBits() && "Part type sizes don't match!" ) ? void (0) : __assert_fail ("RegisterVT.getSizeInBits() == Parts[0].getSimpleValueType().getSizeInBits() && \"Part type sizes don't match!\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 371, __extension__ __PRETTY_FUNCTION__)) | |||
| 370 | Parts[0].getSimpleValueType().getSizeInBits() &&(static_cast <bool> (RegisterVT.getSizeInBits() == Parts [0].getSimpleValueType().getSizeInBits() && "Part type sizes don't match!" ) ? void (0) : __assert_fail ("RegisterVT.getSizeInBits() == Parts[0].getSimpleValueType().getSizeInBits() && \"Part type sizes don't match!\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 371, __extension__ __PRETTY_FUNCTION__)) | |||
| 371 | "Part type sizes don't match!")(static_cast <bool> (RegisterVT.getSizeInBits() == Parts [0].getSimpleValueType().getSizeInBits() && "Part type sizes don't match!" ) ? void (0) : __assert_fail ("RegisterVT.getSizeInBits() == Parts[0].getSimpleValueType().getSizeInBits() && \"Part type sizes don't match!\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 371, __extension__ __PRETTY_FUNCTION__)); | |||
| 372 | ||||
| 373 | // Assemble the parts into intermediate operands. | |||
| 374 | SmallVector<SDValue, 8> Ops(NumIntermediates); | |||
| 375 | if (NumIntermediates == NumParts) { | |||
| 376 | // If the register was not expanded, truncate or copy the value, | |||
| 377 | // as appropriate. | |||
| 378 | for (unsigned i = 0; i != NumParts; ++i) | |||
| 379 | Ops[i] = getCopyFromParts(DAG, DL, &Parts[i], 1, | |||
| 380 | PartVT, IntermediateVT, V); | |||
| 381 | } else if (NumParts > 0) { | |||
| 382 | // If the intermediate type was expanded, build the intermediate | |||
| 383 | // operands from the parts. | |||
| 384 | assert(NumParts % NumIntermediates == 0 &&(static_cast <bool> (NumParts % NumIntermediates == 0 && "Must expand into a divisible number of parts!") ? void (0) : __assert_fail ("NumParts % NumIntermediates == 0 && \"Must expand into a divisible number of parts!\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 385, __extension__ __PRETTY_FUNCTION__)) | |||
| 385 | "Must expand into a divisible number of parts!")(static_cast <bool> (NumParts % NumIntermediates == 0 && "Must expand into a divisible number of parts!") ? void (0) : __assert_fail ("NumParts % NumIntermediates == 0 && \"Must expand into a divisible number of parts!\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 385, __extension__ __PRETTY_FUNCTION__)); | |||
| 386 | unsigned Factor = NumParts / NumIntermediates; | |||
| 387 | for (unsigned i = 0; i != NumIntermediates; ++i) | |||
| 388 | Ops[i] = getCopyFromParts(DAG, DL, &Parts[i * Factor], Factor, | |||
| 389 | PartVT, IntermediateVT, V); | |||
| 390 | } | |||
| 391 | ||||
| 392 | // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the | |||
| 393 | // intermediate operands. | |||
| 394 | EVT BuiltVectorTy = | |||
| 395 | EVT::getVectorVT(*DAG.getContext(), IntermediateVT.getScalarType(), | |||
| 396 | (IntermediateVT.isVector() | |||
| 397 | ? IntermediateVT.getVectorNumElements() * NumParts | |||
| 398 | : NumIntermediates)); | |||
| 399 | Val = DAG.getNode(IntermediateVT.isVector() ? ISD::CONCAT_VECTORS | |||
| 400 | : ISD::BUILD_VECTOR, | |||
| 401 | DL, BuiltVectorTy, Ops); | |||
| 402 | } | |||
| 403 | ||||
| 404 | // There is now one part, held in Val. Correct it to match ValueVT. | |||
| 405 | EVT PartEVT = Val.getValueType(); | |||
| 406 | ||||
| 407 | if (PartEVT == ValueVT) | |||
| 408 | return Val; | |||
| 409 | ||||
| 410 | if (PartEVT.isVector()) { | |||
| 411 | // If the element type of the source/dest vectors are the same, but the | |||
| 412 | // parts vector has more elements than the value vector, then we have a | |||
| 413 | // vector widening case (e.g. <2 x float> -> <4 x float>). Extract the | |||
| 414 | // elements we want. | |||
| 415 | if (PartEVT.getVectorElementType() == ValueVT.getVectorElementType()) { | |||
| 416 | assert(PartEVT.getVectorNumElements() > ValueVT.getVectorNumElements() &&(static_cast <bool> (PartEVT.getVectorNumElements() > ValueVT.getVectorNumElements() && "Cannot narrow, it would be a lossy transformation" ) ? void (0) : __assert_fail ("PartEVT.getVectorNumElements() > ValueVT.getVectorNumElements() && \"Cannot narrow, it would be a lossy transformation\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 417, __extension__ __PRETTY_FUNCTION__)) | |||
| 417 | "Cannot narrow, it would be a lossy transformation")(static_cast <bool> (PartEVT.getVectorNumElements() > ValueVT.getVectorNumElements() && "Cannot narrow, it would be a lossy transformation" ) ? void (0) : __assert_fail ("PartEVT.getVectorNumElements() > ValueVT.getVectorNumElements() && \"Cannot narrow, it would be a lossy transformation\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 417, __extension__ __PRETTY_FUNCTION__)); | |||
| 418 | return DAG.getNode( | |||
| 419 | ISD::EXTRACT_SUBVECTOR, DL, ValueVT, Val, | |||
| 420 | DAG.getConstant(0, DL, TLI.getVectorIdxTy(DAG.getDataLayout()))); | |||
| 421 | } | |||
| 422 | ||||
| 423 | // Vector/Vector bitcast. | |||
| 424 | if (ValueVT.getSizeInBits() == PartEVT.getSizeInBits()) | |||
| 425 | return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val); | |||
| 426 | ||||
| 427 | assert(PartEVT.getVectorNumElements() == ValueVT.getVectorNumElements() &&(static_cast <bool> (PartEVT.getVectorNumElements() == ValueVT .getVectorNumElements() && "Cannot handle this kind of promotion" ) ? void (0) : __assert_fail ("PartEVT.getVectorNumElements() == ValueVT.getVectorNumElements() && \"Cannot handle this kind of promotion\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 428, __extension__ __PRETTY_FUNCTION__)) | |||
| 428 | "Cannot handle this kind of promotion")(static_cast <bool> (PartEVT.getVectorNumElements() == ValueVT .getVectorNumElements() && "Cannot handle this kind of promotion" ) ? void (0) : __assert_fail ("PartEVT.getVectorNumElements() == ValueVT.getVectorNumElements() && \"Cannot handle this kind of promotion\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 428, __extension__ __PRETTY_FUNCTION__)); | |||
| 429 | // Promoted vector extract | |||
| 430 | return DAG.getAnyExtOrTrunc(Val, DL, ValueVT); | |||
| 431 | ||||
| 432 | } | |||
| 433 | ||||
| 434 | // Trivial bitcast if the types are the same size and the destination | |||
| 435 | // vector type is legal. | |||
| 436 | if (PartEVT.getSizeInBits() == ValueVT.getSizeInBits() && | |||
| 437 | TLI.isTypeLegal(ValueVT)) | |||
| 438 | return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val); | |||
| 439 | ||||
| 440 | if (ValueVT.getVectorNumElements() != 1) { | |||
| 441 | // Certain ABIs require that vectors are passed as integers. For vectors | |||
| 442 | // are the same size, this is an obvious bitcast. | |||
| 443 | if (ValueVT.getSizeInBits() == PartEVT.getSizeInBits()) { | |||
| 444 | return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val); | |||
| 445 | } else if (ValueVT.getSizeInBits() < PartEVT.getSizeInBits()) { | |||
| 446 | // Bitcast Val back the original type and extract the corresponding | |||
| 447 | // vector we want. | |||
| 448 | unsigned Elts = PartEVT.getSizeInBits() / ValueVT.getScalarSizeInBits(); | |||
| 449 | EVT WiderVecType = EVT::getVectorVT(*DAG.getContext(), | |||
| 450 | ValueVT.getVectorElementType(), Elts); | |||
| 451 | Val = DAG.getBitcast(WiderVecType, Val); | |||
| 452 | return DAG.getNode( | |||
| 453 | ISD::EXTRACT_SUBVECTOR, DL, ValueVT, Val, | |||
| 454 | DAG.getConstant(0, DL, TLI.getVectorIdxTy(DAG.getDataLayout()))); | |||
| 455 | } | |||
| 456 | ||||
| 457 | diagnosePossiblyInvalidConstraint( | |||
| 458 | *DAG.getContext(), V, "non-trivial scalar-to-vector conversion"); | |||
| 459 | return DAG.getUNDEF(ValueVT); | |||
| 460 | } | |||
| 461 | ||||
| 462 | // Handle cases such as i8 -> <1 x i1> | |||
| 463 | EVT ValueSVT = ValueVT.getVectorElementType(); | |||
| 464 | if (ValueVT.getVectorNumElements() == 1 && ValueSVT != PartEVT) | |||
| 465 | Val = ValueVT.isFloatingPoint() ? DAG.getFPExtendOrRound(Val, DL, ValueSVT) | |||
| 466 | : DAG.getAnyExtOrTrunc(Val, DL, ValueSVT); | |||
| 467 | ||||
| 468 | return DAG.getBuildVector(ValueVT, DL, Val); | |||
| 469 | } | |||
| 470 | ||||
| 471 | static void getCopyToPartsVector(SelectionDAG &DAG, const SDLoc &dl, | |||
| 472 | SDValue Val, SDValue *Parts, unsigned NumParts, | |||
| 473 | MVT PartVT, const Value *V, bool IsABIRegCopy); | |||
| 474 | ||||
| 475 | /// getCopyToParts - Create a series of nodes that contain the specified value | |||
| 476 | /// split into legal parts. If the parts contain more bits than Val, then, for | |||
| 477 | /// integers, ExtendKind can be used to specify how to generate the extra bits. | |||
| 478 | static void getCopyToParts(SelectionDAG &DAG, const SDLoc &DL, SDValue Val, | |||
| 479 | SDValue *Parts, unsigned NumParts, MVT PartVT, | |||
| 480 | const Value *V, | |||
| 481 | ISD::NodeType ExtendKind = ISD::ANY_EXTEND, | |||
| 482 | bool IsABIRegCopy = false) { | |||
| 483 | EVT ValueVT = Val.getValueType(); | |||
| 484 | ||||
| 485 | // Handle the vector case separately. | |||
| 486 | if (ValueVT.isVector()) | |||
| 487 | return getCopyToPartsVector(DAG, DL, Val, Parts, NumParts, PartVT, V, | |||
| 488 | IsABIRegCopy); | |||
| 489 | ||||
| 490 | unsigned PartBits = PartVT.getSizeInBits(); | |||
| 491 | unsigned OrigNumParts = NumParts; | |||
| 492 | assert(DAG.getTargetLoweringInfo().isTypeLegal(PartVT) &&(static_cast <bool> (DAG.getTargetLoweringInfo().isTypeLegal (PartVT) && "Copying to an illegal type!") ? void (0) : __assert_fail ("DAG.getTargetLoweringInfo().isTypeLegal(PartVT) && \"Copying to an illegal type!\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 493, __extension__ __PRETTY_FUNCTION__)) | |||
| 493 | "Copying to an illegal type!")(static_cast <bool> (DAG.getTargetLoweringInfo().isTypeLegal (PartVT) && "Copying to an illegal type!") ? void (0) : __assert_fail ("DAG.getTargetLoweringInfo().isTypeLegal(PartVT) && \"Copying to an illegal type!\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 493, __extension__ __PRETTY_FUNCTION__)); | |||
| 494 | ||||
| 495 | if (NumParts == 0) | |||
| 496 | return; | |||
| 497 | ||||
| 498 | assert(!ValueVT.isVector() && "Vector case handled elsewhere")(static_cast <bool> (!ValueVT.isVector() && "Vector case handled elsewhere" ) ? void (0) : __assert_fail ("!ValueVT.isVector() && \"Vector case handled elsewhere\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 498, __extension__ __PRETTY_FUNCTION__)); | |||
| 499 | EVT PartEVT = PartVT; | |||
| 500 | if (PartEVT == ValueVT) { | |||
| 501 | assert(NumParts == 1 && "No-op copy with multiple parts!")(static_cast <bool> (NumParts == 1 && "No-op copy with multiple parts!" ) ? void (0) : __assert_fail ("NumParts == 1 && \"No-op copy with multiple parts!\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 501, __extension__ __PRETTY_FUNCTION__)); | |||
| 502 | Parts[0] = Val; | |||
| 503 | return; | |||
| 504 | } | |||
| 505 | ||||
| 506 | if (NumParts * PartBits > ValueVT.getSizeInBits()) { | |||
| 507 | // If the parts cover more bits than the value has, promote the value. | |||
| 508 | if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) { | |||
| 509 | assert(NumParts == 1 && "Do not know what to promote to!")(static_cast <bool> (NumParts == 1 && "Do not know what to promote to!" ) ? void (0) : __assert_fail ("NumParts == 1 && \"Do not know what to promote to!\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 509, __extension__ __PRETTY_FUNCTION__)); | |||
| 510 | Val = DAG.getNode(ISD::FP_EXTEND, DL, PartVT, Val); | |||
| 511 | } else { | |||
| 512 | if (ValueVT.isFloatingPoint()) { | |||
| 513 | // FP values need to be bitcast, then extended if they are being put | |||
| 514 | // into a larger container. | |||
| 515 | ValueVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits()); | |||
| 516 | Val = DAG.getNode(ISD::BITCAST, DL, ValueVT, Val); | |||
| 517 | } | |||
| 518 | assert((PartVT.isInteger() || PartVT == MVT::x86mmx) &&(static_cast <bool> ((PartVT.isInteger() || PartVT == MVT ::x86mmx) && ValueVT.isInteger() && "Unknown mismatch!" ) ? void (0) : __assert_fail ("(PartVT.isInteger() || PartVT == MVT::x86mmx) && ValueVT.isInteger() && \"Unknown mismatch!\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 520, __extension__ __PRETTY_FUNCTION__)) | |||
| 519 | ValueVT.isInteger() &&(static_cast <bool> ((PartVT.isInteger() || PartVT == MVT ::x86mmx) && ValueVT.isInteger() && "Unknown mismatch!" ) ? void (0) : __assert_fail ("(PartVT.isInteger() || PartVT == MVT::x86mmx) && ValueVT.isInteger() && \"Unknown mismatch!\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 520, __extension__ __PRETTY_FUNCTION__)) | |||
| 520 | "Unknown mismatch!")(static_cast <bool> ((PartVT.isInteger() || PartVT == MVT ::x86mmx) && ValueVT.isInteger() && "Unknown mismatch!" ) ? void (0) : __assert_fail ("(PartVT.isInteger() || PartVT == MVT::x86mmx) && ValueVT.isInteger() && \"Unknown mismatch!\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 520, __extension__ __PRETTY_FUNCTION__)); | |||
| 521 | ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits); | |||
| 522 | Val = DAG.getNode(ExtendKind, DL, ValueVT, Val); | |||
| 523 | if (PartVT == MVT::x86mmx) | |||
| 524 | Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val); | |||
| 525 | } | |||
| 526 | } else if (PartBits == ValueVT.getSizeInBits()) { | |||
| 527 | // Different types of the same size. | |||
| 528 | assert(NumParts == 1 && PartEVT != ValueVT)(static_cast <bool> (NumParts == 1 && PartEVT != ValueVT) ? void (0) : __assert_fail ("NumParts == 1 && PartEVT != ValueVT" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 528, __extension__ __PRETTY_FUNCTION__)); | |||
| 529 | Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val); | |||
| 530 | } else if (NumParts * PartBits < ValueVT.getSizeInBits()) { | |||
| 531 | // If the parts cover less bits than value has, truncate the value. | |||
| 532 | assert((PartVT.isInteger() || PartVT == MVT::x86mmx) &&(static_cast <bool> ((PartVT.isInteger() || PartVT == MVT ::x86mmx) && ValueVT.isInteger() && "Unknown mismatch!" ) ? void (0) : __assert_fail ("(PartVT.isInteger() || PartVT == MVT::x86mmx) && ValueVT.isInteger() && \"Unknown mismatch!\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 534, __extension__ __PRETTY_FUNCTION__)) | |||
| 533 | ValueVT.isInteger() &&(static_cast <bool> ((PartVT.isInteger() || PartVT == MVT ::x86mmx) && ValueVT.isInteger() && "Unknown mismatch!" ) ? void (0) : __assert_fail ("(PartVT.isInteger() || PartVT == MVT::x86mmx) && ValueVT.isInteger() && \"Unknown mismatch!\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 534, __extension__ __PRETTY_FUNCTION__)) | |||
| 534 | "Unknown mismatch!")(static_cast <bool> ((PartVT.isInteger() || PartVT == MVT ::x86mmx) && ValueVT.isInteger() && "Unknown mismatch!" ) ? void (0) : __assert_fail ("(PartVT.isInteger() || PartVT == MVT::x86mmx) && ValueVT.isInteger() && \"Unknown mismatch!\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 534, __extension__ __PRETTY_FUNCTION__)); | |||
| 535 | ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits); | |||
| 536 | Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val); | |||
| 537 | if (PartVT == MVT::x86mmx) | |||
| 538 | Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val); | |||
| 539 | } | |||
| 540 | ||||
| 541 | // The value may have changed - recompute ValueVT. | |||
| 542 | ValueVT = Val.getValueType(); | |||
| 543 | assert(NumParts * PartBits == ValueVT.getSizeInBits() &&(static_cast <bool> (NumParts * PartBits == ValueVT.getSizeInBits () && "Failed to tile the value with PartVT!") ? void (0) : __assert_fail ("NumParts * PartBits == ValueVT.getSizeInBits() && \"Failed to tile the value with PartVT!\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 544, __extension__ __PRETTY_FUNCTION__)) | |||
| 544 | "Failed to tile the value with PartVT!")(static_cast <bool> (NumParts * PartBits == ValueVT.getSizeInBits () && "Failed to tile the value with PartVT!") ? void (0) : __assert_fail ("NumParts * PartBits == ValueVT.getSizeInBits() && \"Failed to tile the value with PartVT!\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 544, __extension__ __PRETTY_FUNCTION__)); | |||
| 545 | ||||
| 546 | if (NumParts == 1) { | |||
| 547 | if (PartEVT != ValueVT) { | |||
| 548 | diagnosePossiblyInvalidConstraint(*DAG.getContext(), V, | |||
| 549 | "scalar-to-vector conversion failed"); | |||
| 550 | Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val); | |||
| 551 | } | |||
| 552 | ||||
| 553 | Parts[0] = Val; | |||
| 554 | return; | |||
| 555 | } | |||
| 556 | ||||
| 557 | // Expand the value into multiple parts. | |||
| 558 | if (NumParts & (NumParts - 1)) { | |||
| 559 | // The number of parts is not a power of 2. Split off and copy the tail. | |||
| 560 | assert(PartVT.isInteger() && ValueVT.isInteger() &&(static_cast <bool> (PartVT.isInteger() && ValueVT .isInteger() && "Do not know what to expand to!") ? void (0) : __assert_fail ("PartVT.isInteger() && ValueVT.isInteger() && \"Do not know what to expand to!\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 561, __extension__ __PRETTY_FUNCTION__)) | |||
| 561 | "Do not know what to expand to!")(static_cast <bool> (PartVT.isInteger() && ValueVT .isInteger() && "Do not know what to expand to!") ? void (0) : __assert_fail ("PartVT.isInteger() && ValueVT.isInteger() && \"Do not know what to expand to!\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 561, __extension__ __PRETTY_FUNCTION__)); | |||
| 562 | unsigned RoundParts = 1 << Log2_32(NumParts); | |||
| 563 | unsigned RoundBits = RoundParts * PartBits; | |||
| 564 | unsigned OddParts = NumParts - RoundParts; | |||
| 565 | SDValue OddVal = DAG.getNode(ISD::SRL, DL, ValueVT, Val, | |||
| 566 | DAG.getIntPtrConstant(RoundBits, DL)); | |||
| 567 | getCopyToParts(DAG, DL, OddVal, Parts + RoundParts, OddParts, PartVT, V); | |||
| 568 | ||||
| 569 | if (DAG.getDataLayout().isBigEndian()) | |||
| 570 | // The odd parts were reversed by getCopyToParts - unreverse them. | |||
| 571 | std::reverse(Parts + RoundParts, Parts + NumParts); | |||
| 572 | ||||
| 573 | NumParts = RoundParts; | |||
| 574 | ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits); | |||
| 575 | Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val); | |||
| 576 | } | |||
| 577 | ||||
| 578 | // The number of parts is a power of 2. Repeatedly bisect the value using | |||
| 579 | // EXTRACT_ELEMENT. | |||
| 580 | Parts[0] = DAG.getNode(ISD::BITCAST, DL, | |||
| 581 | EVT::getIntegerVT(*DAG.getContext(), | |||
| 582 | ValueVT.getSizeInBits()), | |||
| 583 | Val); | |||
| 584 | ||||
| 585 | for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) { | |||
| 586 | for (unsigned i = 0; i < NumParts; i += StepSize) { | |||
| 587 | unsigned ThisBits = StepSize * PartBits / 2; | |||
| 588 | EVT ThisVT = EVT::getIntegerVT(*DAG.getContext(), ThisBits); | |||
| 589 | SDValue &Part0 = Parts[i]; | |||
| 590 | SDValue &Part1 = Parts[i+StepSize/2]; | |||
| 591 | ||||
| 592 | Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, | |||
| 593 | ThisVT, Part0, DAG.getIntPtrConstant(1, DL)); | |||
| 594 | Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, | |||
| 595 | ThisVT, Part0, DAG.getIntPtrConstant(0, DL)); | |||
| 596 | ||||
| 597 | if (ThisBits == PartBits && ThisVT != PartVT) { | |||
| 598 | Part0 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part0); | |||
| 599 | Part1 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part1); | |||
| 600 | } | |||
| 601 | } | |||
| 602 | } | |||
| 603 | ||||
| 604 | if (DAG.getDataLayout().isBigEndian()) | |||
| 605 | std::reverse(Parts, Parts + OrigNumParts); | |||
| 606 | } | |||
| 607 | ||||
| 608 | ||||
| 609 | /// getCopyToPartsVector - Create a series of nodes that contain the specified | |||
| 610 | /// value split into legal parts. | |||
| 611 | static void getCopyToPartsVector(SelectionDAG &DAG, const SDLoc &DL, | |||
| 612 | SDValue Val, SDValue *Parts, unsigned NumParts, | |||
| 613 | MVT PartVT, const Value *V, | |||
| 614 | bool IsABIRegCopy) { | |||
| 615 | EVT ValueVT = Val.getValueType(); | |||
| 616 | assert(ValueVT.isVector() && "Not a vector")(static_cast <bool> (ValueVT.isVector() && "Not a vector" ) ? void (0) : __assert_fail ("ValueVT.isVector() && \"Not a vector\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 616, __extension__ __PRETTY_FUNCTION__)); | |||
| 617 | const TargetLowering &TLI = DAG.getTargetLoweringInfo(); | |||
| 618 | ||||
| 619 | if (NumParts == 1) { | |||
| 620 | EVT PartEVT = PartVT; | |||
| 621 | if (PartEVT == ValueVT) { | |||
| 622 | // Nothing to do. | |||
| 623 | } else if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) { | |||
| 624 | // Bitconvert vector->vector case. | |||
| 625 | Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val); | |||
| 626 | } else if (PartVT.isVector() && | |||
| 627 | PartEVT.getVectorElementType() == ValueVT.getVectorElementType() && | |||
| 628 | PartEVT.getVectorNumElements() > ValueVT.getVectorNumElements()) { | |||
| 629 | EVT ElementVT = PartVT.getVectorElementType(); | |||
| 630 | // Vector widening case, e.g. <2 x float> -> <4 x float>. Shuffle in | |||
| 631 | // undef elements. | |||
| 632 | SmallVector<SDValue, 16> Ops; | |||
| 633 | for (unsigned i = 0, e = ValueVT.getVectorNumElements(); i != e; ++i) | |||
| 634 | Ops.push_back(DAG.getNode( | |||
| 635 | ISD::EXTRACT_VECTOR_ELT, DL, ElementVT, Val, | |||
| 636 | DAG.getConstant(i, DL, TLI.getVectorIdxTy(DAG.getDataLayout())))); | |||
| 637 | ||||
| 638 | for (unsigned i = ValueVT.getVectorNumElements(), | |||
| 639 | e = PartVT.getVectorNumElements(); i != e; ++i) | |||
| 640 | Ops.push_back(DAG.getUNDEF(ElementVT)); | |||
| 641 | ||||
| 642 | Val = DAG.getBuildVector(PartVT, DL, Ops); | |||
| 643 | ||||
| 644 | // FIXME: Use CONCAT for 2x -> 4x. | |||
| 645 | ||||
| 646 | //SDValue UndefElts = DAG.getUNDEF(VectorTy); | |||
| 647 | //Val = DAG.getNode(ISD::CONCAT_VECTORS, DL, PartVT, Val, UndefElts); | |||
| 648 | } else if (PartVT.isVector() && | |||
| 649 | PartEVT.getVectorElementType().bitsGE( | |||
| 650 | ValueVT.getVectorElementType()) && | |||
| 651 | PartEVT.getVectorNumElements() == ValueVT.getVectorNumElements()) { | |||
| 652 | ||||
| 653 | // Promoted vector extract | |||
| 654 | Val = DAG.getAnyExtOrTrunc(Val, DL, PartVT); | |||
| 655 | } else { | |||
| 656 | if (ValueVT.getVectorNumElements() == 1) { | |||
| 657 | Val = DAG.getNode( | |||
| 658 | ISD::EXTRACT_VECTOR_ELT, DL, PartVT, Val, | |||
| 659 | DAG.getConstant(0, DL, TLI.getVectorIdxTy(DAG.getDataLayout()))); | |||
| 660 | } else { | |||
| 661 | assert(PartVT.getSizeInBits() > ValueVT.getSizeInBits() &&(static_cast <bool> (PartVT.getSizeInBits() > ValueVT .getSizeInBits() && "lossy conversion of vector to scalar type" ) ? void (0) : __assert_fail ("PartVT.getSizeInBits() > ValueVT.getSizeInBits() && \"lossy conversion of vector to scalar type\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 662, __extension__ __PRETTY_FUNCTION__)) | |||
| 662 | "lossy conversion of vector to scalar type")(static_cast <bool> (PartVT.getSizeInBits() > ValueVT .getSizeInBits() && "lossy conversion of vector to scalar type" ) ? void (0) : __assert_fail ("PartVT.getSizeInBits() > ValueVT.getSizeInBits() && \"lossy conversion of vector to scalar type\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 662, __extension__ __PRETTY_FUNCTION__)); | |||
| 663 | EVT IntermediateType = | |||
| 664 | EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits()); | |||
| 665 | Val = DAG.getBitcast(IntermediateType, Val); | |||
| 666 | Val = DAG.getAnyExtOrTrunc(Val, DL, PartVT); | |||
| 667 | } | |||
| 668 | } | |||
| 669 | ||||
| 670 | assert(Val.getValueType() == PartVT && "Unexpected vector part value type")(static_cast <bool> (Val.getValueType() == PartVT && "Unexpected vector part value type") ? void (0) : __assert_fail ("Val.getValueType() == PartVT && \"Unexpected vector part value type\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 670, __extension__ __PRETTY_FUNCTION__)); | |||
| 671 | Parts[0] = Val; | |||
| 672 | return; | |||
| 673 | } | |||
| 674 | ||||
| 675 | // Handle a multi-element vector. | |||
| 676 | EVT IntermediateVT; | |||
| 677 | MVT RegisterVT; | |||
| 678 | unsigned NumIntermediates; | |||
| 679 | unsigned NumRegs; | |||
| 680 | if (IsABIRegCopy) { | |||
| 681 | NumRegs = TLI.getVectorTypeBreakdownForCallingConv( | |||
| 682 | *DAG.getContext(), ValueVT, IntermediateVT, NumIntermediates, | |||
| 683 | RegisterVT); | |||
| 684 | } else { | |||
| 685 | NumRegs = | |||
| 686 | TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, IntermediateVT, | |||
| 687 | NumIntermediates, RegisterVT); | |||
| 688 | } | |||
| 689 | unsigned NumElements = ValueVT.getVectorNumElements(); | |||
| 690 | ||||
| 691 | assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!")(static_cast <bool> (NumRegs == NumParts && "Part count doesn't match vector breakdown!" ) ? void (0) : __assert_fail ("NumRegs == NumParts && \"Part count doesn't match vector breakdown!\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 691, __extension__ __PRETTY_FUNCTION__)); | |||
| 692 | NumParts = NumRegs; // Silence a compiler warning. | |||
| 693 | assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!")(static_cast <bool> (RegisterVT == PartVT && "Part type doesn't match vector breakdown!" ) ? void (0) : __assert_fail ("RegisterVT == PartVT && \"Part type doesn't match vector breakdown!\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 693, __extension__ __PRETTY_FUNCTION__)); | |||
| 694 | ||||
| 695 | // Convert the vector to the appropiate type if necessary. | |||
| 696 | unsigned DestVectorNoElts = | |||
| 697 | NumIntermediates * | |||
| 698 | (IntermediateVT.isVector() ? IntermediateVT.getVectorNumElements() : 1); | |||
| 699 | EVT BuiltVectorTy = EVT::getVectorVT( | |||
| 700 | *DAG.getContext(), IntermediateVT.getScalarType(), DestVectorNoElts); | |||
| 701 | if (Val.getValueType() != BuiltVectorTy) | |||
| 702 | Val = DAG.getNode(ISD::BITCAST, DL, BuiltVectorTy, Val); | |||
| 703 | ||||
| 704 | // Split the vector into intermediate operands. | |||
| 705 | SmallVector<SDValue, 8> Ops(NumIntermediates); | |||
| 706 | for (unsigned i = 0; i != NumIntermediates; ++i) { | |||
| 707 | if (IntermediateVT.isVector()) | |||
| 708 | Ops[i] = | |||
| 709 | DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, IntermediateVT, Val, | |||
| 710 | DAG.getConstant(i * (NumElements / NumIntermediates), DL, | |||
| 711 | TLI.getVectorIdxTy(DAG.getDataLayout()))); | |||
| 712 | else | |||
| 713 | Ops[i] = DAG.getNode( | |||
| 714 | ISD::EXTRACT_VECTOR_ELT, DL, IntermediateVT, Val, | |||
| 715 | DAG.getConstant(i, DL, TLI.getVectorIdxTy(DAG.getDataLayout()))); | |||
| 716 | } | |||
| 717 | ||||
| 718 | // Split the intermediate operands into legal parts. | |||
| 719 | if (NumParts == NumIntermediates) { | |||
| 720 | // If the register was not expanded, promote or copy the value, | |||
| 721 | // as appropriate. | |||
| 722 | for (unsigned i = 0; i != NumParts; ++i) | |||
| 723 | getCopyToParts(DAG, DL, Ops[i], &Parts[i], 1, PartVT, V); | |||
| 724 | } else if (NumParts > 0) { | |||
| 725 | // If the intermediate type was expanded, split each the value into | |||
| 726 | // legal parts. | |||
| 727 | assert(NumIntermediates != 0 && "division by zero")(static_cast <bool> (NumIntermediates != 0 && "division by zero" ) ? void (0) : __assert_fail ("NumIntermediates != 0 && \"division by zero\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 727, __extension__ __PRETTY_FUNCTION__)); | |||
| 728 | assert(NumParts % NumIntermediates == 0 &&(static_cast <bool> (NumParts % NumIntermediates == 0 && "Must expand into a divisible number of parts!") ? void (0) : __assert_fail ("NumParts % NumIntermediates == 0 && \"Must expand into a divisible number of parts!\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 729, __extension__ __PRETTY_FUNCTION__)) | |||
| 729 | "Must expand into a divisible number of parts!")(static_cast <bool> (NumParts % NumIntermediates == 0 && "Must expand into a divisible number of parts!") ? void (0) : __assert_fail ("NumParts % NumIntermediates == 0 && \"Must expand into a divisible number of parts!\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 729, __extension__ __PRETTY_FUNCTION__)); | |||
| 730 | unsigned Factor = NumParts / NumIntermediates; | |||
| 731 | for (unsigned i = 0; i != NumIntermediates; ++i) | |||
| 732 | getCopyToParts(DAG, DL, Ops[i], &Parts[i*Factor], Factor, PartVT, V); | |||
| 733 | } | |||
| 734 | } | |||
| 735 | ||||
| 736 | RegsForValue::RegsForValue(const SmallVector<unsigned, 4> ®s, MVT regvt, | |||
| 737 | EVT valuevt, bool IsABIMangledValue) | |||
| 738 | : ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs), | |||
| 739 | RegCount(1, regs.size()), IsABIMangled(IsABIMangledValue) {} | |||
| 740 | ||||
| 741 | RegsForValue::RegsForValue(LLVMContext &Context, const TargetLowering &TLI, | |||
| 742 | const DataLayout &DL, unsigned Reg, Type *Ty, | |||
| 743 | bool IsABIMangledValue) { | |||
| 744 | ComputeValueVTs(TLI, DL, Ty, ValueVTs); | |||
| 745 | ||||
| 746 | IsABIMangled = IsABIMangledValue; | |||
| 747 | ||||
| 748 | for (EVT ValueVT : ValueVTs) { | |||
| 749 | unsigned NumRegs = IsABIMangledValue | |||
| 750 | ? TLI.getNumRegistersForCallingConv(Context, ValueVT) | |||
| 751 | : TLI.getNumRegisters(Context, ValueVT); | |||
| 752 | MVT RegisterVT = IsABIMangledValue | |||
| 753 | ? TLI.getRegisterTypeForCallingConv(Context, ValueVT) | |||
| 754 | : TLI.getRegisterType(Context, ValueVT); | |||
| 755 | for (unsigned i = 0; i != NumRegs; ++i) | |||
| 756 | Regs.push_back(Reg + i); | |||
| 757 | RegVTs.push_back(RegisterVT); | |||
| 758 | RegCount.push_back(NumRegs); | |||
| 759 | Reg += NumRegs; | |||
| 760 | } | |||
| 761 | } | |||
| 762 | ||||
| 763 | SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG, | |||
| 764 | FunctionLoweringInfo &FuncInfo, | |||
| 765 | const SDLoc &dl, SDValue &Chain, | |||
| 766 | SDValue *Flag, const Value *V) const { | |||
| 767 | // A Value with type {} or [0 x %t] needs no registers. | |||
| 768 | if (ValueVTs.empty()) | |||
| 769 | return SDValue(); | |||
| 770 | ||||
| 771 | const TargetLowering &TLI = DAG.getTargetLoweringInfo(); | |||
| 772 | ||||
| 773 | // Assemble the legal parts into the final values. | |||
| 774 | SmallVector<SDValue, 4> Values(ValueVTs.size()); | |||
| 775 | SmallVector<SDValue, 8> Parts; | |||
| 776 | for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) { | |||
| 777 | // Copy the legal parts from the registers. | |||
| 778 | EVT ValueVT = ValueVTs[Value]; | |||
| 779 | unsigned NumRegs = RegCount[Value]; | |||
| 780 | MVT RegisterVT = IsABIMangled | |||
| 781 | ? TLI.getRegisterTypeForCallingConv(*DAG.getContext(), RegVTs[Value]) | |||
| 782 | : RegVTs[Value]; | |||
| 783 | ||||
| 784 | Parts.resize(NumRegs); | |||
| 785 | for (unsigned i = 0; i != NumRegs; ++i) { | |||
| 786 | SDValue P; | |||
| 787 | if (!Flag) { | |||
| 788 | P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT); | |||
| 789 | } else { | |||
| 790 | P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT, *Flag); | |||
| 791 | *Flag = P.getValue(2); | |||
| 792 | } | |||
| 793 | ||||
| 794 | Chain = P.getValue(1); | |||
| 795 | Parts[i] = P; | |||
| 796 | ||||
| 797 | // If the source register was virtual and if we know something about it, | |||
| 798 | // add an assert node. | |||
| 799 | if (!TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) || | |||
| 800 | !RegisterVT.isInteger() || RegisterVT.isVector()) | |||
| 801 | continue; | |||
| 802 | ||||
| 803 | const FunctionLoweringInfo::LiveOutInfo *LOI = | |||
| 804 | FuncInfo.GetLiveOutRegInfo(Regs[Part+i]); | |||
| 805 | if (!LOI) | |||
| 806 | continue; | |||
| 807 | ||||
| 808 | unsigned RegSize = RegisterVT.getSizeInBits(); | |||
| 809 | unsigned NumSignBits = LOI->NumSignBits; | |||
| 810 | unsigned NumZeroBits = LOI->Known.countMinLeadingZeros(); | |||
| 811 | ||||
| 812 | if (NumZeroBits == RegSize) { | |||
| 813 | // The current value is a zero. | |||
| 814 | // Explicitly express that as it would be easier for | |||
| 815 | // optimizations to kick in. | |||
| 816 | Parts[i] = DAG.getConstant(0, dl, RegisterVT); | |||
| 817 | continue; | |||
| 818 | } | |||
| 819 | ||||
| 820 | // FIXME: We capture more information than the dag can represent. For | |||
| 821 | // now, just use the tightest assertzext/assertsext possible. | |||
| 822 | bool isSExt; | |||
| 823 | EVT FromVT(MVT::Other); | |||
| 824 | if (NumZeroBits) { | |||
| 825 | FromVT = EVT::getIntegerVT(*DAG.getContext(), RegSize - NumZeroBits); | |||
| 826 | isSExt = false; | |||
| 827 | } else if (NumSignBits > 1) { | |||
| 828 | FromVT = | |||
| 829 | EVT::getIntegerVT(*DAG.getContext(), RegSize - NumSignBits + 1); | |||
| 830 | isSExt = true; | |||
| 831 | } else { | |||
| 832 | continue; | |||
| 833 | } | |||
| 834 | // Add an assertion node. | |||
| 835 | assert(FromVT != MVT::Other)(static_cast <bool> (FromVT != MVT::Other) ? void (0) : __assert_fail ("FromVT != MVT::Other", "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 835, __extension__ __PRETTY_FUNCTION__)); | |||
| 836 | Parts[i] = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl, | |||
| 837 | RegisterVT, P, DAG.getValueType(FromVT)); | |||
| 838 | } | |||
| 839 | ||||
| 840 | Values[Value] = getCopyFromParts(DAG, dl, Parts.begin(), | |||
| 841 | NumRegs, RegisterVT, ValueVT, V); | |||
| 842 | Part += NumRegs; | |||
| 843 | Parts.clear(); | |||
| 844 | } | |||
| 845 | ||||
| 846 | return DAG.getNode(ISD::MERGE_VALUES, dl, DAG.getVTList(ValueVTs), Values); | |||
| 847 | } | |||
| 848 | ||||
| 849 | void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, | |||
| 850 | const SDLoc &dl, SDValue &Chain, SDValue *Flag, | |||
| 851 | const Value *V, | |||
| 852 | ISD::NodeType PreferredExtendType) const { | |||
| 853 | const TargetLowering &TLI = DAG.getTargetLoweringInfo(); | |||
| 854 | ISD::NodeType ExtendKind = PreferredExtendType; | |||
| 855 | ||||
| 856 | // Get the list of the values's legal parts. | |||
| 857 | unsigned NumRegs = Regs.size(); | |||
| 858 | SmallVector<SDValue, 8> Parts(NumRegs); | |||
| 859 | for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) { | |||
| 860 | unsigned NumParts = RegCount[Value]; | |||
| 861 | ||||
| 862 | MVT RegisterVT = IsABIMangled | |||
| 863 | ? TLI.getRegisterTypeForCallingConv(*DAG.getContext(), RegVTs[Value]) | |||
| 864 | : RegVTs[Value]; | |||
| 865 | ||||
| 866 | if (ExtendKind == ISD::ANY_EXTEND && TLI.isZExtFree(Val, RegisterVT)) | |||
| 867 | ExtendKind = ISD::ZERO_EXTEND; | |||
| 868 | ||||
| 869 | getCopyToParts(DAG, dl, Val.getValue(Val.getResNo() + Value), | |||
| 870 | &Parts[Part], NumParts, RegisterVT, V, ExtendKind); | |||
| 871 | Part += NumParts; | |||
| 872 | } | |||
| 873 | ||||
| 874 | // Copy the parts into the registers. | |||
| 875 | SmallVector<SDValue, 8> Chains(NumRegs); | |||
| 876 | for (unsigned i = 0; i != NumRegs; ++i) { | |||
| 877 | SDValue Part; | |||
| 878 | if (!Flag) { | |||
| 879 | Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i]); | |||
| 880 | } else { | |||
| 881 | Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i], *Flag); | |||
| 882 | *Flag = Part.getValue(1); | |||
| 883 | } | |||
| 884 | ||||
| 885 | Chains[i] = Part.getValue(0); | |||
| 886 | } | |||
| 887 | ||||
| 888 | if (NumRegs == 1 || Flag) | |||
| 889 | // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is | |||
| 890 | // flagged to it. That is the CopyToReg nodes and the user are considered | |||
| 891 | // a single scheduling unit. If we create a TokenFactor and return it as | |||
| 892 | // chain, then the TokenFactor is both a predecessor (operand) of the | |||
| 893 | // user as well as a successor (the TF operands are flagged to the user). | |||
| 894 | // c1, f1 = CopyToReg | |||
| 895 | // c2, f2 = CopyToReg | |||
| 896 | // c3 = TokenFactor c1, c2 | |||
| 897 | // ... | |||
| 898 | // = op c3, ..., f2 | |||
| 899 | Chain = Chains[NumRegs-1]; | |||
| 900 | else | |||
| 901 | Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains); | |||
| 902 | } | |||
| 903 | ||||
| 904 | void RegsForValue::AddInlineAsmOperands(unsigned Code, bool HasMatching, | |||
| 905 | unsigned MatchingIdx, const SDLoc &dl, | |||
| 906 | SelectionDAG &DAG, | |||
| 907 | std::vector<SDValue> &Ops) const { | |||
| 908 | const TargetLowering &TLI = DAG.getTargetLoweringInfo(); | |||
| 909 | ||||
| 910 | unsigned Flag = InlineAsm::getFlagWord(Code, Regs.size()); | |||
| 911 | if (HasMatching) | |||
| 912 | Flag = InlineAsm::getFlagWordForMatchingOp(Flag, MatchingIdx); | |||
| 913 | else if (!Regs.empty() && | |||
| 914 | TargetRegisterInfo::isVirtualRegister(Regs.front())) { | |||
| 915 | // Put the register class of the virtual registers in the flag word. That | |||
| 916 | // way, later passes can recompute register class constraints for inline | |||
| 917 | // assembly as well as normal instructions. | |||
| 918 | // Don't do this for tied operands that can use the regclass information | |||
| 919 | // from the def. | |||
| 920 | const MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo(); | |||
| 921 | const TargetRegisterClass *RC = MRI.getRegClass(Regs.front()); | |||
| 922 | Flag = InlineAsm::getFlagWordForRegClass(Flag, RC->getID()); | |||
| 923 | } | |||
| 924 | ||||
| 925 | SDValue Res = DAG.getTargetConstant(Flag, dl, MVT::i32); | |||
| 926 | Ops.push_back(Res); | |||
| 927 | ||||
| 928 | if (Code == InlineAsm::Kind_Clobber) { | |||
| 929 | // Clobbers should always have a 1:1 mapping with registers, and may | |||
| 930 | // reference registers that have illegal (e.g. vector) types. Hence, we | |||
| 931 | // shouldn't try to apply any sort of splitting logic to them. | |||
| 932 | assert(Regs.size() == RegVTs.size() && Regs.size() == ValueVTs.size() &&(static_cast <bool> (Regs.size() == RegVTs.size() && Regs.size() == ValueVTs.size() && "No 1:1 mapping from clobbers to regs?" ) ? void (0) : __assert_fail ("Regs.size() == RegVTs.size() && Regs.size() == ValueVTs.size() && \"No 1:1 mapping from clobbers to regs?\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 933, __extension__ __PRETTY_FUNCTION__)) | |||
| 933 | "No 1:1 mapping from clobbers to regs?")(static_cast <bool> (Regs.size() == RegVTs.size() && Regs.size() == ValueVTs.size() && "No 1:1 mapping from clobbers to regs?" ) ? void (0) : __assert_fail ("Regs.size() == RegVTs.size() && Regs.size() == ValueVTs.size() && \"No 1:1 mapping from clobbers to regs?\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 933, __extension__ __PRETTY_FUNCTION__)); | |||
| 934 | unsigned SP = TLI.getStackPointerRegisterToSaveRestore(); | |||
| 935 | (void)SP; | |||
| 936 | for (unsigned I = 0, E = ValueVTs.size(); I != E; ++I) { | |||
| 937 | Ops.push_back(DAG.getRegister(Regs[I], RegVTs[I])); | |||
| 938 | assert((static_cast <bool> ((Regs[I] != SP || DAG.getMachineFunction ().getFrameInfo().hasOpaqueSPAdjustment()) && "If we clobbered the stack pointer, MFI should know about it." ) ? void (0) : __assert_fail ("(Regs[I] != SP || DAG.getMachineFunction().getFrameInfo().hasOpaqueSPAdjustment()) && \"If we clobbered the stack pointer, MFI should know about it.\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 941, __extension__ __PRETTY_FUNCTION__)) | |||
| 939 | (Regs[I] != SP ||(static_cast <bool> ((Regs[I] != SP || DAG.getMachineFunction ().getFrameInfo().hasOpaqueSPAdjustment()) && "If we clobbered the stack pointer, MFI should know about it." ) ? void (0) : __assert_fail ("(Regs[I] != SP || DAG.getMachineFunction().getFrameInfo().hasOpaqueSPAdjustment()) && \"If we clobbered the stack pointer, MFI should know about it.\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 941, __extension__ __PRETTY_FUNCTION__)) | |||
| 940 | DAG.getMachineFunction().getFrameInfo().hasOpaqueSPAdjustment()) &&(static_cast <bool> ((Regs[I] != SP || DAG.getMachineFunction ().getFrameInfo().hasOpaqueSPAdjustment()) && "If we clobbered the stack pointer, MFI should know about it." ) ? void (0) : __assert_fail ("(Regs[I] != SP || DAG.getMachineFunction().getFrameInfo().hasOpaqueSPAdjustment()) && \"If we clobbered the stack pointer, MFI should know about it.\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 941, __extension__ __PRETTY_FUNCTION__)) | |||
| 941 | "If we clobbered the stack pointer, MFI should know about it.")(static_cast <bool> ((Regs[I] != SP || DAG.getMachineFunction ().getFrameInfo().hasOpaqueSPAdjustment()) && "If we clobbered the stack pointer, MFI should know about it." ) ? void (0) : __assert_fail ("(Regs[I] != SP || DAG.getMachineFunction().getFrameInfo().hasOpaqueSPAdjustment()) && \"If we clobbered the stack pointer, MFI should know about it.\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 941, __extension__ __PRETTY_FUNCTION__)); | |||
| 942 | } | |||
| 943 | return; | |||
| 944 | } | |||
| 945 | ||||
| 946 | for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) { | |||
| 947 | unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVTs[Value]); | |||
| 948 | MVT RegisterVT = RegVTs[Value]; | |||
| 949 | for (unsigned i = 0; i != NumRegs; ++i) { | |||
| 950 | assert(Reg < Regs.size() && "Mismatch in # registers expected")(static_cast <bool> (Reg < Regs.size() && "Mismatch in # registers expected" ) ? void (0) : __assert_fail ("Reg < Regs.size() && \"Mismatch in # registers expected\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 950, __extension__ __PRETTY_FUNCTION__)); | |||
| 951 | unsigned TheReg = Regs[Reg++]; | |||
| 952 | Ops.push_back(DAG.getRegister(TheReg, RegisterVT)); | |||
| 953 | } | |||
| 954 | } | |||
| 955 | } | |||
| 956 | ||||
| 957 | SmallVector<std::pair<unsigned, unsigned>, 4> | |||
| 958 | RegsForValue::getRegsAndSizes() const { | |||
| 959 | SmallVector<std::pair<unsigned, unsigned>, 4> OutVec; | |||
| 960 | unsigned I = 0; | |||
| 961 | for (auto CountAndVT : zip_first(RegCount, RegVTs)) { | |||
| 962 | unsigned RegCount = std::get<0>(CountAndVT); | |||
| 963 | MVT RegisterVT = std::get<1>(CountAndVT); | |||
| 964 | unsigned RegisterSize = RegisterVT.getSizeInBits(); | |||
| 965 | for (unsigned E = I + RegCount; I != E; ++I) | |||
| 966 | OutVec.push_back(std::make_pair(Regs[I], RegisterSize)); | |||
| 967 | } | |||
| 968 | return OutVec; | |||
| 969 | } | |||
| 970 | ||||
| 971 | void SelectionDAGBuilder::init(GCFunctionInfo *gfi, AliasAnalysis *aa, | |||
| 972 | const TargetLibraryInfo *li) { | |||
| 973 | AA = aa; | |||
| 974 | GFI = gfi; | |||
| 975 | LibInfo = li; | |||
| 976 | DL = &DAG.getDataLayout(); | |||
| 977 | Context = DAG.getContext(); | |||
| 978 | LPadToCallSiteMap.clear(); | |||
| 979 | } | |||
| 980 | ||||
| 981 | void SelectionDAGBuilder::clear() { | |||
| 982 | NodeMap.clear(); | |||
| 983 | UnusedArgNodeMap.clear(); | |||
| 984 | PendingLoads.clear(); | |||
| 985 | PendingExports.clear(); | |||
| 986 | CurInst = nullptr; | |||
| 987 | HasTailCall = false; | |||
| 988 | SDNodeOrder = LowestSDNodeOrder; | |||
| 989 | StatepointLowering.clear(); | |||
| 990 | } | |||
| 991 | ||||
| 992 | void SelectionDAGBuilder::clearDanglingDebugInfo() { | |||
| 993 | DanglingDebugInfoMap.clear(); | |||
| 994 | } | |||
| 995 | ||||
| 996 | SDValue SelectionDAGBuilder::getRoot() { | |||
| 997 | if (PendingLoads.empty()) | |||
| 998 | return DAG.getRoot(); | |||
| 999 | ||||
| 1000 | if (PendingLoads.size() == 1) { | |||
| 1001 | SDValue Root = PendingLoads[0]; | |||
| 1002 | DAG.setRoot(Root); | |||
| 1003 | PendingLoads.clear(); | |||
| 1004 | return Root; | |||
| 1005 | } | |||
| 1006 | ||||
| 1007 | // Otherwise, we have to make a token factor node. | |||
| 1008 | SDValue Root = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other, | |||
| 1009 | PendingLoads); | |||
| 1010 | PendingLoads.clear(); | |||
| 1011 | DAG.setRoot(Root); | |||
| 1012 | return Root; | |||
| 1013 | } | |||
| 1014 | ||||
| 1015 | SDValue SelectionDAGBuilder::getControlRoot() { | |||
| 1016 | SDValue Root = DAG.getRoot(); | |||
| 1017 | ||||
| 1018 | if (PendingExports.empty()) | |||
| 1019 | return Root; | |||
| 1020 | ||||
| 1021 | // Turn all of the CopyToReg chains into one factored node. | |||
| 1022 | if (Root.getOpcode() != ISD::EntryToken) { | |||
| 1023 | unsigned i = 0, e = PendingExports.size(); | |||
| 1024 | for (; i != e; ++i) { | |||
| 1025 | assert(PendingExports[i].getNode()->getNumOperands() > 1)(static_cast <bool> (PendingExports[i].getNode()->getNumOperands () > 1) ? void (0) : __assert_fail ("PendingExports[i].getNode()->getNumOperands() > 1" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 1025, __extension__ __PRETTY_FUNCTION__)); | |||
| 1026 | if (PendingExports[i].getNode()->getOperand(0) == Root) | |||
| 1027 | break; // Don't add the root if we already indirectly depend on it. | |||
| 1028 | } | |||
| 1029 | ||||
| 1030 | if (i == e) | |||
| 1031 | PendingExports.push_back(Root); | |||
| 1032 | } | |||
| 1033 | ||||
| 1034 | Root = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other, | |||
| 1035 | PendingExports); | |||
| 1036 | PendingExports.clear(); | |||
| 1037 | DAG.setRoot(Root); | |||
| 1038 | return Root; | |||
| 1039 | } | |||
| 1040 | ||||
| 1041 | void SelectionDAGBuilder::visit(const Instruction &I) { | |||
| 1042 | // Set up outgoing PHI node register values before emitting the terminator. | |||
| 1043 | if (isa<TerminatorInst>(&I)) { | |||
| 1044 | HandlePHINodesInSuccessorBlocks(I.getParent()); | |||
| 1045 | } | |||
| 1046 | ||||
| 1047 | // Increase the SDNodeOrder if dealing with a non-debug instruction. | |||
| 1048 | if (!isa<DbgInfoIntrinsic>(I)) | |||
| 1049 | ++SDNodeOrder; | |||
| 1050 | ||||
| 1051 | CurInst = &I; | |||
| 1052 | ||||
| 1053 | visit(I.getOpcode(), I); | |||
| 1054 | ||||
| 1055 | if (auto *FPMO = dyn_cast<FPMathOperator>(&I)) { | |||
| 1056 | // Propagate the fast-math-flags of this IR instruction to the DAG node that | |||
| 1057 | // maps to this instruction. | |||
| 1058 | // TODO: We could handle all flags (nsw, etc) here. | |||
| 1059 | // TODO: If an IR instruction maps to >1 node, only the final node will have | |||
| 1060 | // flags set. | |||
| 1061 | if (SDNode *Node = getNodeForIRValue(&I)) { | |||
| 1062 | SDNodeFlags IncomingFlags; | |||
| 1063 | IncomingFlags.copyFMF(*FPMO); | |||
| 1064 | if (!Node->getFlags().isDefined()) | |||
| 1065 | Node->setFlags(IncomingFlags); | |||
| 1066 | else | |||
| 1067 | Node->intersectFlagsWith(IncomingFlags); | |||
| 1068 | } | |||
| 1069 | } | |||
| 1070 | ||||
| 1071 | if (!isa<TerminatorInst>(&I) && !HasTailCall && | |||
| 1072 | !isStatepoint(&I)) // statepoints handle their exports internally | |||
| 1073 | CopyToExportRegsIfNeeded(&I); | |||
| 1074 | ||||
| 1075 | CurInst = nullptr; | |||
| 1076 | } | |||
| 1077 | ||||
| 1078 | void SelectionDAGBuilder::visitPHI(const PHINode &) { | |||
| 1079 | llvm_unreachable("SelectionDAGBuilder shouldn't visit PHI nodes!")::llvm::llvm_unreachable_internal("SelectionDAGBuilder shouldn't visit PHI nodes!" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 1079); | |||
| 1080 | } | |||
| 1081 | ||||
| 1082 | void SelectionDAGBuilder::visit(unsigned Opcode, const User &I) { | |||
| 1083 | // Note: this doesn't use InstVisitor, because it has to work with | |||
| 1084 | // ConstantExpr's in addition to instructions. | |||
| 1085 | switch (Opcode) { | |||
| 1086 | default: llvm_unreachable("Unknown instruction type encountered!")::llvm::llvm_unreachable_internal("Unknown instruction type encountered!" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 1086); | |||
| 1087 | // Build the switch statement using the Instruction.def file. | |||
| 1088 | #define HANDLE_INST(NUM, OPCODE, CLASS) \ | |||
| 1089 | case Instruction::OPCODE: visit##OPCODE((const CLASS&)I); break; | |||
| 1090 | #include "llvm/IR/Instruction.def" | |||
| 1091 | } | |||
| 1092 | } | |||
| 1093 | ||||
| 1094 | void SelectionDAGBuilder::dropDanglingDebugInfo(const DILocalVariable *Variable, | |||
| 1095 | const DIExpression *Expr) { | |||
| 1096 | for (auto &DDIMI : DanglingDebugInfoMap) | |||
| 1097 | for (auto &DDI : DDIMI.second) | |||
| 1098 | if (DDI.getDI()) { | |||
| 1099 | const DbgValueInst *DI = DDI.getDI(); | |||
| 1100 | DIVariable *DanglingVariable = DI->getVariable(); | |||
| 1101 | DIExpression *DanglingExpr = DI->getExpression(); | |||
| 1102 | if (DanglingVariable == Variable && | |||
| 1103 | Expr->fragmentsOverlap(DanglingExpr)) { | |||
| 1104 | LLVM_DEBUG(dbgs()do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType ("isel")) { dbgs() << "Dropping dangling debug info for " << *DI << "\n"; } } while (false) | |||
| 1105 | << "Dropping dangling debug info for " << *DI << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType ("isel")) { dbgs() << "Dropping dangling debug info for " << *DI << "\n"; } } while (false); | |||
| 1106 | DDI = DanglingDebugInfo(); | |||
| 1107 | } | |||
| 1108 | } | |||
| 1109 | } | |||
| 1110 | ||||
| 1111 | // resolveDanglingDebugInfo - if we saw an earlier dbg_value referring to V, | |||
| 1112 | // generate the debug data structures now that we've seen its definition. | |||
| 1113 | void SelectionDAGBuilder::resolveDanglingDebugInfo(const Value *V, | |||
| 1114 | SDValue Val) { | |||
| 1115 | DanglingDebugInfoVector &DDIV = DanglingDebugInfoMap[V]; | |||
| 1116 | for (auto &DDI : DDIV) { | |||
| 1117 | if (!DDI.getDI()) | |||
| 1118 | continue; | |||
| 1119 | const DbgValueInst *DI = DDI.getDI(); | |||
| 1120 | DebugLoc dl = DDI.getdl(); | |||
| 1121 | unsigned ValSDNodeOrder = Val.getNode()->getIROrder(); | |||
| 1122 | unsigned DbgSDNodeOrder = DDI.getSDNodeOrder(); | |||
| 1123 | DILocalVariable *Variable = DI->getVariable(); | |||
| 1124 | DIExpression *Expr = DI->getExpression(); | |||
| 1125 | assert(Variable->isValidLocationForIntrinsic(dl) &&(static_cast <bool> (Variable->isValidLocationForIntrinsic (dl) && "Expected inlined-at fields to agree") ? void (0) : __assert_fail ("Variable->isValidLocationForIntrinsic(dl) && \"Expected inlined-at fields to agree\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 1126, __extension__ __PRETTY_FUNCTION__)) | |||
| 1126 | "Expected inlined-at fields to agree")(static_cast <bool> (Variable->isValidLocationForIntrinsic (dl) && "Expected inlined-at fields to agree") ? void (0) : __assert_fail ("Variable->isValidLocationForIntrinsic(dl) && \"Expected inlined-at fields to agree\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 1126, __extension__ __PRETTY_FUNCTION__)); | |||
| 1127 | SDDbgValue *SDV; | |||
| 1128 | if (Val.getNode()) { | |||
| 1129 | if (!EmitFuncArgumentDbgValue(V, Variable, Expr, dl, false, Val)) { | |||
| 1130 | LLVM_DEBUG(dbgs() << "Resolve dangling debug info [order="do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType ("isel")) { dbgs() << "Resolve dangling debug info [order=" << DbgSDNodeOrder << "] for:\n " << *DI << "\n"; } } while (false) | |||
| 1131 | << DbgSDNodeOrder << "] for:\n " << *DI << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType ("isel")) { dbgs() << "Resolve dangling debug info [order=" << DbgSDNodeOrder << "] for:\n " << *DI << "\n"; } } while (false); | |||
| 1132 | LLVM_DEBUG(dbgs() << " By mapping to:\n "; Val.dump())do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType ("isel")) { dbgs() << " By mapping to:\n "; Val.dump (); } } while (false); | |||
| 1133 | // Increase the SDNodeOrder for the DbgValue here to make sure it is | |||
| 1134 | // inserted after the definition of Val when emitting the instructions | |||
| 1135 | // after ISel. An alternative could be to teach | |||
| 1136 | // ScheduleDAGSDNodes::EmitSchedule to delay the insertion properly. | |||
| 1137 | LLVM_DEBUG(if (ValSDNodeOrder > DbgSDNodeOrder) dbgs()do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType ("isel")) { if (ValSDNodeOrder > DbgSDNodeOrder) dbgs() << "changing SDNodeOrder from " << DbgSDNodeOrder << " to " << ValSDNodeOrder << "\n"; } } while (false ) | |||
| 1138 | << "changing SDNodeOrder from " << DbgSDNodeOrder << " to "do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType ("isel")) { if (ValSDNodeOrder > DbgSDNodeOrder) dbgs() << "changing SDNodeOrder from " << DbgSDNodeOrder << " to " << ValSDNodeOrder << "\n"; } } while (false ) | |||
| 1139 | << ValSDNodeOrder << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType ("isel")) { if (ValSDNodeOrder > DbgSDNodeOrder) dbgs() << "changing SDNodeOrder from " << DbgSDNodeOrder << " to " << ValSDNodeOrder << "\n"; } } while (false ); | |||
| 1140 | SDV = getDbgValue(Val, Variable, Expr, dl, | |||
| 1141 | std::max(DbgSDNodeOrder, ValSDNodeOrder)); | |||
| 1142 | DAG.AddDbgValue(SDV, Val.getNode(), false); | |||
| 1143 | } else | |||
| 1144 | LLVM_DEBUG(dbgs() << "Resolved dangling debug info for " << *DIdo { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType ("isel")) { dbgs() << "Resolved dangling debug info for " << *DI << "in EmitFuncArgumentDbgValue\n"; } } while (false) | |||
| 1145 | << "in EmitFuncArgumentDbgValue\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType ("isel")) { dbgs() << "Resolved dangling debug info for " << *DI << "in EmitFuncArgumentDbgValue\n"; } } while (false); | |||
| 1146 | } else | |||
| 1147 | LLVM_DEBUG(dbgs() << "Dropping debug info for " << *DI << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType ("isel")) { dbgs() << "Dropping debug info for " << *DI << "\n"; } } while (false); | |||
| 1148 | } | |||
| 1149 | DanglingDebugInfoMap[V].clear(); | |||
| 1150 | } | |||
| 1151 | ||||
| 1152 | /// getCopyFromRegs - If there was virtual register allocated for the value V | |||
| 1153 | /// emit CopyFromReg of the specified type Ty. Return empty SDValue() otherwise. | |||
| 1154 | SDValue SelectionDAGBuilder::getCopyFromRegs(const Value *V, Type *Ty) { | |||
| 1155 | DenseMap<const Value *, unsigned>::iterator It = FuncInfo.ValueMap.find(V); | |||
| 1156 | SDValue Result; | |||
| 1157 | ||||
| 1158 | if (It != FuncInfo.ValueMap.end()) { | |||
| 1159 | unsigned InReg = It->second; | |||
| 1160 | ||||
| 1161 | RegsForValue RFV(*DAG.getContext(), DAG.getTargetLoweringInfo(), | |||
| 1162 | DAG.getDataLayout(), InReg, Ty, isABIRegCopy(V)); | |||
| 1163 | SDValue Chain = DAG.getEntryNode(); | |||
| 1164 | Result = RFV.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(), Chain, nullptr, | |||
| 1165 | V); | |||
| 1166 | resolveDanglingDebugInfo(V, Result); | |||
| 1167 | } | |||
| 1168 | ||||
| 1169 | return Result; | |||
| 1170 | } | |||
| 1171 | ||||
| 1172 | /// getValue - Return an SDValue for the given Value. | |||
| 1173 | SDValue SelectionDAGBuilder::getValue(const Value *V) { | |||
| 1174 | // If we already have an SDValue for this value, use it. It's important | |||
| 1175 | // to do this first, so that we don't create a CopyFromReg if we already | |||
| 1176 | // have a regular SDValue. | |||
| 1177 | SDValue &N = NodeMap[V]; | |||
| 1178 | if (N.getNode()) return N; | |||
| 1179 | ||||
| 1180 | // If there's a virtual register allocated and initialized for this | |||
| 1181 | // value, use it. | |||
| 1182 | if (SDValue copyFromReg = getCopyFromRegs(V, V->getType())) | |||
| 1183 | return copyFromReg; | |||
| 1184 | ||||
| 1185 | // Otherwise create a new SDValue and remember it. | |||
| 1186 | SDValue Val = getValueImpl(V); | |||
| 1187 | NodeMap[V] = Val; | |||
| 1188 | resolveDanglingDebugInfo(V, Val); | |||
| 1189 | return Val; | |||
| 1190 | } | |||
| 1191 | ||||
| 1192 | // Return true if SDValue exists for the given Value | |||
| 1193 | bool SelectionDAGBuilder::findValue(const Value *V) const { | |||
| 1194 | return (NodeMap.find(V) != NodeMap.end()) || | |||
| 1195 | (FuncInfo.ValueMap.find(V) != FuncInfo.ValueMap.end()); | |||
| 1196 | } | |||
| 1197 | ||||
| 1198 | /// getNonRegisterValue - Return an SDValue for the given Value, but | |||
| 1199 | /// don't look in FuncInfo.ValueMap for a virtual register. | |||
| 1200 | SDValue SelectionDAGBuilder::getNonRegisterValue(const Value *V) { | |||
| 1201 | // If we already have an SDValue for this value, use it. | |||
| 1202 | SDValue &N = NodeMap[V]; | |||
| 1203 | if (N.getNode()) { | |||
| 1204 | if (isa<ConstantSDNode>(N) || isa<ConstantFPSDNode>(N)) { | |||
| 1205 | // Remove the debug location from the node as the node is about to be used | |||
| 1206 | // in a location which may differ from the original debug location. This | |||
| 1207 | // is relevant to Constant and ConstantFP nodes because they can appear | |||
| 1208 | // as constant expressions inside PHI nodes. | |||
| 1209 | N->setDebugLoc(DebugLoc()); | |||
| 1210 | } | |||
| 1211 | return N; | |||
| 1212 | } | |||
| 1213 | ||||
| 1214 | // Otherwise create a new SDValue and remember it. | |||
| 1215 | SDValue Val = getValueImpl(V); | |||
| 1216 | NodeMap[V] = Val; | |||
| 1217 | resolveDanglingDebugInfo(V, Val); | |||
| 1218 | return Val; | |||
| 1219 | } | |||
| 1220 | ||||
| 1221 | /// getValueImpl - Helper function for getValue and getNonRegisterValue. | |||
| 1222 | /// Create an SDValue for the given value. | |||
| 1223 | SDValue SelectionDAGBuilder::getValueImpl(const Value *V) { | |||
| 1224 | const TargetLowering &TLI = DAG.getTargetLoweringInfo(); | |||
| 1225 | ||||
| 1226 | if (const Constant *C = dyn_cast<Constant>(V)) { | |||
| 1227 | EVT VT = TLI.getValueType(DAG.getDataLayout(), V->getType(), true); | |||
| 1228 | ||||
| 1229 | if (const ConstantInt *CI = dyn_cast<ConstantInt>(C)) | |||
| 1230 | return DAG.getConstant(*CI, getCurSDLoc(), VT); | |||
| 1231 | ||||
| 1232 | if (const GlobalValue *GV = dyn_cast<GlobalValue>(C)) | |||
| 1233 | return DAG.getGlobalAddress(GV, getCurSDLoc(), VT); | |||
| 1234 | ||||
| 1235 | if (isa<ConstantPointerNull>(C)) { | |||
| 1236 | unsigned AS = V->getType()->getPointerAddressSpace(); | |||
| 1237 | return DAG.getConstant(0, getCurSDLoc(), | |||
| 1238 | TLI.getPointerTy(DAG.getDataLayout(), AS)); | |||
| 1239 | } | |||
| 1240 | ||||
| 1241 | if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C)) | |||
| 1242 | return DAG.getConstantFP(*CFP, getCurSDLoc(), VT); | |||
| 1243 | ||||
| 1244 | if (isa<UndefValue>(C) && !V->getType()->isAggregateType()) | |||
| 1245 | return DAG.getUNDEF(VT); | |||
| 1246 | ||||
| 1247 | if (const ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) { | |||
| 1248 | visit(CE->getOpcode(), *CE); | |||
| 1249 | SDValue N1 = NodeMap[V]; | |||
| 1250 | assert(N1.getNode() && "visit didn't populate the NodeMap!")(static_cast <bool> (N1.getNode() && "visit didn't populate the NodeMap!" ) ? void (0) : __assert_fail ("N1.getNode() && \"visit didn't populate the NodeMap!\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 1250, __extension__ __PRETTY_FUNCTION__)); | |||
| 1251 | return N1; | |||
| 1252 | } | |||
| 1253 | ||||
| 1254 | if (isa<ConstantStruct>(C) || isa<ConstantArray>(C)) { | |||
| 1255 | SmallVector<SDValue, 4> Constants; | |||
| 1256 | for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end(); | |||
| 1257 | OI != OE; ++OI) { | |||
| 1258 | SDNode *Val = getValue(*OI).getNode(); | |||
| 1259 | // If the operand is an empty aggregate, there are no values. | |||
| 1260 | if (!Val) continue; | |||
| 1261 | // Add each leaf value from the operand to the Constants list | |||
| 1262 | // to form a flattened list of all the values. | |||
| 1263 | for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i) | |||
| 1264 | Constants.push_back(SDValue(Val, i)); | |||
| 1265 | } | |||
| 1266 | ||||
| 1267 | return DAG.getMergeValues(Constants, getCurSDLoc()); | |||
| 1268 | } | |||
| 1269 | ||||
| 1270 | if (const ConstantDataSequential *CDS = | |||
| 1271 | dyn_cast<ConstantDataSequential>(C)) { | |||
| 1272 | SmallVector<SDValue, 4> Ops; | |||
| 1273 | for (unsigned i = 0, e = CDS->getNumElements(); i != e; ++i) { | |||
| 1274 | SDNode *Val = getValue(CDS->getElementAsConstant(i)).getNode(); | |||
| 1275 | // Add each leaf value from the operand to the Constants list | |||
| 1276 | // to form a flattened list of all the values. | |||
| 1277 | for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i) | |||
| 1278 | Ops.push_back(SDValue(Val, i)); | |||
| 1279 | } | |||
| 1280 | ||||
| 1281 | if (isa<ArrayType>(CDS->getType())) | |||
| 1282 | return DAG.getMergeValues(Ops, getCurSDLoc()); | |||
| 1283 | return NodeMap[V] = DAG.getBuildVector(VT, getCurSDLoc(), Ops); | |||
| 1284 | } | |||
| 1285 | ||||
| 1286 | if (C->getType()->isStructTy() || C->getType()->isArrayTy()) { | |||
| 1287 | assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&(static_cast <bool> ((isa<ConstantAggregateZero>( C) || isa<UndefValue>(C)) && "Unknown struct or array constant!" ) ? void (0) : __assert_fail ("(isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) && \"Unknown struct or array constant!\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 1288, __extension__ __PRETTY_FUNCTION__)) | |||
| 1288 | "Unknown struct or array constant!")(static_cast <bool> ((isa<ConstantAggregateZero>( C) || isa<UndefValue>(C)) && "Unknown struct or array constant!" ) ? void (0) : __assert_fail ("(isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) && \"Unknown struct or array constant!\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 1288, __extension__ __PRETTY_FUNCTION__)); | |||
| 1289 | ||||
| 1290 | SmallVector<EVT, 4> ValueVTs; | |||
| 1291 | ComputeValueVTs(TLI, DAG.getDataLayout(), C->getType(), ValueVTs); | |||
| 1292 | unsigned NumElts = ValueVTs.size(); | |||
| 1293 | if (NumElts == 0) | |||
| 1294 | return SDValue(); // empty struct | |||
| 1295 | SmallVector<SDValue, 4> Constants(NumElts); | |||
| 1296 | for (unsigned i = 0; i != NumElts; ++i) { | |||
| 1297 | EVT EltVT = ValueVTs[i]; | |||
| 1298 | if (isa<UndefValue>(C)) | |||
| 1299 | Constants[i] = DAG.getUNDEF(EltVT); | |||
| 1300 | else if (EltVT.isFloatingPoint()) | |||
| 1301 | Constants[i] = DAG.getConstantFP(0, getCurSDLoc(), EltVT); | |||
| 1302 | else | |||
| 1303 | Constants[i] = DAG.getConstant(0, getCurSDLoc(), EltVT); | |||
| 1304 | } | |||
| 1305 | ||||
| 1306 | return DAG.getMergeValues(Constants, getCurSDLoc()); | |||
| 1307 | } | |||
| 1308 | ||||
| 1309 | if (const BlockAddress *BA = dyn_cast<BlockAddress>(C)) | |||
| 1310 | return DAG.getBlockAddress(BA, VT); | |||
| 1311 | ||||
| 1312 | VectorType *VecTy = cast<VectorType>(V->getType()); | |||
| 1313 | unsigned NumElements = VecTy->getNumElements(); | |||
| 1314 | ||||
| 1315 | // Now that we know the number and type of the elements, get that number of | |||
| 1316 | // elements into the Ops array based on what kind of constant it is. | |||
| 1317 | SmallVector<SDValue, 16> Ops; | |||
| 1318 | if (const ConstantVector *CV = dyn_cast<ConstantVector>(C)) { | |||
| 1319 | for (unsigned i = 0; i != NumElements; ++i) | |||
| 1320 | Ops.push_back(getValue(CV->getOperand(i))); | |||
| 1321 | } else { | |||
| 1322 | assert(isa<ConstantAggregateZero>(C) && "Unknown vector constant!")(static_cast <bool> (isa<ConstantAggregateZero>(C ) && "Unknown vector constant!") ? void (0) : __assert_fail ("isa<ConstantAggregateZero>(C) && \"Unknown vector constant!\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 1322, __extension__ __PRETTY_FUNCTION__)); | |||
| 1323 | EVT EltVT = | |||
| 1324 | TLI.getValueType(DAG.getDataLayout(), VecTy->getElementType()); | |||
| 1325 | ||||
| 1326 | SDValue Op; | |||
| 1327 | if (EltVT.isFloatingPoint()) | |||
| 1328 | Op = DAG.getConstantFP(0, getCurSDLoc(), EltVT); | |||
| 1329 | else | |||
| 1330 | Op = DAG.getConstant(0, getCurSDLoc(), EltVT); | |||
| 1331 | Ops.assign(NumElements, Op); | |||
| 1332 | } | |||
| 1333 | ||||
| 1334 | // Create a BUILD_VECTOR node. | |||
| 1335 | return NodeMap[V] = DAG.getBuildVector(VT, getCurSDLoc(), Ops); | |||
| 1336 | } | |||
| 1337 | ||||
| 1338 | // If this is a static alloca, generate it as the frameindex instead of | |||
| 1339 | // computation. | |||
| 1340 | if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) { | |||
| 1341 | DenseMap<const AllocaInst*, int>::iterator SI = | |||
| 1342 | FuncInfo.StaticAllocaMap.find(AI); | |||
| 1343 | if (SI != FuncInfo.StaticAllocaMap.end()) | |||
| 1344 | return DAG.getFrameIndex(SI->second, | |||
| 1345 | TLI.getFrameIndexTy(DAG.getDataLayout())); | |||
| 1346 | } | |||
| 1347 | ||||
| 1348 | // If this is an instruction which fast-isel has deferred, select it now. | |||
| 1349 | if (const Instruction *Inst = dyn_cast<Instruction>(V)) { | |||
| 1350 | unsigned InReg = FuncInfo.InitializeRegForValue(Inst); | |||
| 1351 | ||||
| 1352 | RegsForValue RFV(*DAG.getContext(), TLI, DAG.getDataLayout(), InReg, | |||
| 1353 | Inst->getType(), isABIRegCopy(V)); | |||
| 1354 | SDValue Chain = DAG.getEntryNode(); | |||
| 1355 | return RFV.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(), Chain, nullptr, V); | |||
| 1356 | } | |||
| 1357 | ||||
| 1358 | llvm_unreachable("Can't get register for value!")::llvm::llvm_unreachable_internal("Can't get register for value!" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 1358); | |||
| 1359 | } | |||
| 1360 | ||||
| 1361 | void SelectionDAGBuilder::visitCatchPad(const CatchPadInst &I) { | |||
| 1362 | auto Pers = classifyEHPersonality(FuncInfo.Fn->getPersonalityFn()); | |||
| 1363 | bool IsMSVCCXX = Pers == EHPersonality::MSVC_CXX; | |||
| 1364 | bool IsCoreCLR = Pers == EHPersonality::CoreCLR; | |||
| 1365 | bool IsSEH = isAsynchronousEHPersonality(Pers); | |||
| 1366 | bool IsWasmCXX = Pers == EHPersonality::Wasm_CXX; | |||
| 1367 | MachineBasicBlock *CatchPadMBB = FuncInfo.MBB; | |||
| 1368 | if (!IsSEH) | |||
| 1369 | CatchPadMBB->setIsEHScopeEntry(); | |||
| 1370 | // In MSVC C++ and CoreCLR, catchblocks are funclets and need prologues. | |||
| 1371 | if (IsMSVCCXX || IsCoreCLR) | |||
| 1372 | CatchPadMBB->setIsEHFuncletEntry(); | |||
| 1373 | // Wasm does not need catchpads anymore | |||
| 1374 | if (!IsWasmCXX) | |||
| 1375 | DAG.setRoot(DAG.getNode(ISD::CATCHPAD, getCurSDLoc(), MVT::Other, | |||
| 1376 | getControlRoot())); | |||
| 1377 | } | |||
| 1378 | ||||
| 1379 | void SelectionDAGBuilder::visitCatchRet(const CatchReturnInst &I) { | |||
| 1380 | // Update machine-CFG edge. | |||
| 1381 | MachineBasicBlock *TargetMBB = FuncInfo.MBBMap[I.getSuccessor()]; | |||
| 1382 | FuncInfo.MBB->addSuccessor(TargetMBB); | |||
| 1383 | ||||
| 1384 | auto Pers = classifyEHPersonality(FuncInfo.Fn->getPersonalityFn()); | |||
| 1385 | bool IsSEH = isAsynchronousEHPersonality(Pers); | |||
| 1386 | if (IsSEH) { | |||
| 1387 | // If this is not a fall-through branch or optimizations are switched off, | |||
| 1388 | // emit the branch. | |||
| 1389 | if (TargetMBB != NextBlock(FuncInfo.MBB) || | |||
| 1390 | TM.getOptLevel() == CodeGenOpt::None) | |||
| 1391 | DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other, | |||
| 1392 | getControlRoot(), DAG.getBasicBlock(TargetMBB))); | |||
| 1393 | return; | |||
| 1394 | } | |||
| 1395 | ||||
| 1396 | // Figure out the funclet membership for the catchret's successor. | |||
| 1397 | // This will be used by the FuncletLayout pass to determine how to order the | |||
| 1398 | // BB's. | |||
| 1399 | // A 'catchret' returns to the outer scope's color. | |||
| 1400 | Value *ParentPad = I.getCatchSwitchParentPad(); | |||
| 1401 | const BasicBlock *SuccessorColor; | |||
| 1402 | if (isa<ConstantTokenNone>(ParentPad)) | |||
| 1403 | SuccessorColor = &FuncInfo.Fn->getEntryBlock(); | |||
| 1404 | else | |||
| 1405 | SuccessorColor = cast<Instruction>(ParentPad)->getParent(); | |||
| 1406 | assert(SuccessorColor && "No parent funclet for catchret!")(static_cast <bool> (SuccessorColor && "No parent funclet for catchret!" ) ? void (0) : __assert_fail ("SuccessorColor && \"No parent funclet for catchret!\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 1406, __extension__ __PRETTY_FUNCTION__)); | |||
| 1407 | MachineBasicBlock *SuccessorColorMBB = FuncInfo.MBBMap[SuccessorColor]; | |||
| 1408 | assert(SuccessorColorMBB && "No MBB for SuccessorColor!")(static_cast <bool> (SuccessorColorMBB && "No MBB for SuccessorColor!" ) ? void (0) : __assert_fail ("SuccessorColorMBB && \"No MBB for SuccessorColor!\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 1408, __extension__ __PRETTY_FUNCTION__)); | |||
| 1409 | ||||
| 1410 | // Create the terminator node. | |||
| 1411 | SDValue Ret = DAG.getNode(ISD::CATCHRET, getCurSDLoc(), MVT::Other, | |||
| 1412 | getControlRoot(), DAG.getBasicBlock(TargetMBB), | |||
| 1413 | DAG.getBasicBlock(SuccessorColorMBB)); | |||
| 1414 | DAG.setRoot(Ret); | |||
| 1415 | } | |||
| 1416 | ||||
| 1417 | void SelectionDAGBuilder::visitCleanupPad(const CleanupPadInst &CPI) { | |||
| 1418 | // Don't emit any special code for the cleanuppad instruction. It just marks | |||
| 1419 | // the start of an EH scope/funclet. | |||
| 1420 | FuncInfo.MBB->setIsEHScopeEntry(); | |||
| 1421 | FuncInfo.MBB->setIsEHFuncletEntry(); | |||
| 1422 | FuncInfo.MBB->setIsCleanupFuncletEntry(); | |||
| 1423 | } | |||
| 1424 | ||||
| 1425 | /// When an invoke or a cleanupret unwinds to the next EH pad, there are | |||
| 1426 | /// many places it could ultimately go. In the IR, we have a single unwind | |||
| 1427 | /// destination, but in the machine CFG, we enumerate all the possible blocks. | |||
| 1428 | /// This function skips over imaginary basic blocks that hold catchswitch | |||
| 1429 | /// instructions, and finds all the "real" machine | |||
| 1430 | /// basic block destinations. As those destinations may not be successors of | |||
| 1431 | /// EHPadBB, here we also calculate the edge probability to those destinations. | |||
| 1432 | /// The passed-in Prob is the edge probability to EHPadBB. | |||
| 1433 | static void findUnwindDestinations( | |||
| 1434 | FunctionLoweringInfo &FuncInfo, const BasicBlock *EHPadBB, | |||
| 1435 | BranchProbability Prob, | |||
| 1436 | SmallVectorImpl<std::pair<MachineBasicBlock *, BranchProbability>> | |||
| 1437 | &UnwindDests) { | |||
| 1438 | EHPersonality Personality = | |||
| 1439 | classifyEHPersonality(FuncInfo.Fn->getPersonalityFn()); | |||
| 1440 | bool IsMSVCCXX = Personality == EHPersonality::MSVC_CXX; | |||
| 1441 | bool IsCoreCLR = Personality == EHPersonality::CoreCLR; | |||
| 1442 | bool IsSEH = isAsynchronousEHPersonality(Personality); | |||
| 1443 | ||||
| 1444 | while (EHPadBB) { | |||
| 1445 | const Instruction *Pad = EHPadBB->getFirstNonPHI(); | |||
| 1446 | BasicBlock *NewEHPadBB = nullptr; | |||
| 1447 | if (isa<LandingPadInst>(Pad)) { | |||
| 1448 | // Stop on landingpads. They are not funclets. | |||
| 1449 | UnwindDests.emplace_back(FuncInfo.MBBMap[EHPadBB], Prob); | |||
| 1450 | break; | |||
| 1451 | } else if (isa<CleanupPadInst>(Pad)) { | |||
| 1452 | // Stop on cleanup pads. Cleanups are always funclet entries for all known | |||
| 1453 | // personalities. | |||
| 1454 | UnwindDests.emplace_back(FuncInfo.MBBMap[EHPadBB], Prob); | |||
| 1455 | UnwindDests.back().first->setIsEHScopeEntry(); | |||
| 1456 | UnwindDests.back().first->setIsEHFuncletEntry(); | |||
| 1457 | break; | |||
| 1458 | } else if (auto *CatchSwitch = dyn_cast<CatchSwitchInst>(Pad)) { | |||
| 1459 | // Add the catchpad handlers to the possible destinations. | |||
| 1460 | for (const BasicBlock *CatchPadBB : CatchSwitch->handlers()) { | |||
| 1461 | UnwindDests.emplace_back(FuncInfo.MBBMap[CatchPadBB], Prob); | |||
| 1462 | // For MSVC++ and the CLR, catchblocks are funclets and need prologues. | |||
| 1463 | if (IsMSVCCXX || IsCoreCLR) | |||
| 1464 | UnwindDests.back().first->setIsEHFuncletEntry(); | |||
| 1465 | if (!IsSEH) | |||
| 1466 | UnwindDests.back().first->setIsEHScopeEntry(); | |||
| 1467 | } | |||
| 1468 | NewEHPadBB = CatchSwitch->getUnwindDest(); | |||
| 1469 | } else { | |||
| 1470 | continue; | |||
| 1471 | } | |||
| 1472 | ||||
| 1473 | BranchProbabilityInfo *BPI = FuncInfo.BPI; | |||
| 1474 | if (BPI && NewEHPadBB) | |||
| 1475 | Prob *= BPI->getEdgeProbability(EHPadBB, NewEHPadBB); | |||
| 1476 | EHPadBB = NewEHPadBB; | |||
| 1477 | } | |||
| 1478 | } | |||
| 1479 | ||||
| 1480 | void SelectionDAGBuilder::visitCleanupRet(const CleanupReturnInst &I) { | |||
| 1481 | // Update successor info. | |||
| 1482 | SmallVector<std::pair<MachineBasicBlock *, BranchProbability>, 1> UnwindDests; | |||
| 1483 | auto UnwindDest = I.getUnwindDest(); | |||
| 1484 | BranchProbabilityInfo *BPI = FuncInfo.BPI; | |||
| 1485 | BranchProbability UnwindDestProb = | |||
| 1486 | (BPI && UnwindDest) | |||
| 1487 | ? BPI->getEdgeProbability(FuncInfo.MBB->getBasicBlock(), UnwindDest) | |||
| 1488 | : BranchProbability::getZero(); | |||
| 1489 | findUnwindDestinations(FuncInfo, UnwindDest, UnwindDestProb, UnwindDests); | |||
| 1490 | for (auto &UnwindDest : UnwindDests) { | |||
| 1491 | UnwindDest.first->setIsEHPad(); | |||
| 1492 | addSuccessorWithProb(FuncInfo.MBB, UnwindDest.first, UnwindDest.second); | |||
| 1493 | } | |||
| 1494 | FuncInfo.MBB->normalizeSuccProbs(); | |||
| 1495 | ||||
| 1496 | // Create the terminator node. | |||
| 1497 | SDValue Ret = | |||
| 1498 | DAG.getNode(ISD::CLEANUPRET, getCurSDLoc(), MVT::Other, getControlRoot()); | |||
| 1499 | DAG.setRoot(Ret); | |||
| 1500 | } | |||
| 1501 | ||||
| 1502 | void SelectionDAGBuilder::visitCatchSwitch(const CatchSwitchInst &CSI) { | |||
| 1503 | report_fatal_error("visitCatchSwitch not yet implemented!"); | |||
| 1504 | } | |||
| 1505 | ||||
| 1506 | void SelectionDAGBuilder::visitRet(const ReturnInst &I) { | |||
| 1507 | const TargetLowering &TLI = DAG.getTargetLoweringInfo(); | |||
| 1508 | auto &DL = DAG.getDataLayout(); | |||
| 1509 | SDValue Chain = getControlRoot(); | |||
| 1510 | SmallVector<ISD::OutputArg, 8> Outs; | |||
| 1511 | SmallVector<SDValue, 8> OutVals; | |||
| 1512 | ||||
| 1513 | // Calls to @llvm.experimental.deoptimize don't generate a return value, so | |||
| 1514 | // lower | |||
| 1515 | // | |||
| 1516 | // %val = call <ty> @llvm.experimental.deoptimize() | |||
| 1517 | // ret <ty> %val | |||
| 1518 | // | |||
| 1519 | // differently. | |||
| 1520 | if (I.getParent()->getTerminatingDeoptimizeCall()) { | |||
| 1521 | LowerDeoptimizingReturn(); | |||
| 1522 | return; | |||
| 1523 | } | |||
| 1524 | ||||
| 1525 | if (!FuncInfo.CanLowerReturn) { | |||
| 1526 | unsigned DemoteReg = FuncInfo.DemoteRegister; | |||
| 1527 | const Function *F = I.getParent()->getParent(); | |||
| 1528 | ||||
| 1529 | // Emit a store of the return value through the virtual register. | |||
| 1530 | // Leave Outs empty so that LowerReturn won't try to load return | |||
| 1531 | // registers the usual way. | |||
| 1532 | SmallVector<EVT, 1> PtrValueVTs; | |||
| 1533 | ComputeValueVTs(TLI, DL, | |||
| 1534 | F->getReturnType()->getPointerTo( | |||
| 1535 | DAG.getDataLayout().getAllocaAddrSpace()), | |||
| 1536 | PtrValueVTs); | |||
| 1537 | ||||
| 1538 | SDValue RetPtr = DAG.getCopyFromReg(DAG.getEntryNode(), getCurSDLoc(), | |||
| 1539 | DemoteReg, PtrValueVTs[0]); | |||
| 1540 | SDValue RetOp = getValue(I.getOperand(0)); | |||
| 1541 | ||||
| 1542 | SmallVector<EVT, 4> ValueVTs; | |||
| 1543 | SmallVector<uint64_t, 4> Offsets; | |||
| 1544 | ComputeValueVTs(TLI, DL, I.getOperand(0)->getType(), ValueVTs, &Offsets); | |||
| 1545 | unsigned NumValues = ValueVTs.size(); | |||
| 1546 | ||||
| 1547 | SmallVector<SDValue, 4> Chains(NumValues); | |||
| 1548 | for (unsigned i = 0; i != NumValues; ++i) { | |||
| 1549 | // An aggregate return value cannot wrap around the address space, so | |||
| 1550 | // offsets to its parts don't wrap either. | |||
| 1551 | SDValue Ptr = DAG.getObjectPtrOffset(getCurSDLoc(), RetPtr, Offsets[i]); | |||
| 1552 | Chains[i] = DAG.getStore( | |||
| 1553 | Chain, getCurSDLoc(), SDValue(RetOp.getNode(), RetOp.getResNo() + i), | |||
| 1554 | // FIXME: better loc info would be nice. | |||
| 1555 | Ptr, MachinePointerInfo::getUnknownStack(DAG.getMachineFunction())); | |||
| 1556 | } | |||
| 1557 | ||||
| 1558 | Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), | |||
| 1559 | MVT::Other, Chains); | |||
| 1560 | } else if (I.getNumOperands() != 0) { | |||
| 1561 | SmallVector<EVT, 4> ValueVTs; | |||
| 1562 | ComputeValueVTs(TLI, DL, I.getOperand(0)->getType(), ValueVTs); | |||
| 1563 | unsigned NumValues = ValueVTs.size(); | |||
| 1564 | if (NumValues) { | |||
| 1565 | SDValue RetOp = getValue(I.getOperand(0)); | |||
| 1566 | ||||
| 1567 | const Function *F = I.getParent()->getParent(); | |||
| 1568 | ||||
| 1569 | ISD::NodeType ExtendKind = ISD::ANY_EXTEND; | |||
| 1570 | if (F->getAttributes().hasAttribute(AttributeList::ReturnIndex, | |||
| 1571 | Attribute::SExt)) | |||
| 1572 | ExtendKind = ISD::SIGN_EXTEND; | |||
| 1573 | else if (F->getAttributes().hasAttribute(AttributeList::ReturnIndex, | |||
| 1574 | Attribute::ZExt)) | |||
| 1575 | ExtendKind = ISD::ZERO_EXTEND; | |||
| 1576 | ||||
| 1577 | LLVMContext &Context = F->getContext(); | |||
| 1578 | bool RetInReg = F->getAttributes().hasAttribute( | |||
| 1579 | AttributeList::ReturnIndex, Attribute::InReg); | |||
| 1580 | ||||
| 1581 | for (unsigned j = 0; j != NumValues; ++j) { | |||
| 1582 | EVT VT = ValueVTs[j]; | |||
| 1583 | ||||
| 1584 | if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) | |||
| 1585 | VT = TLI.getTypeForExtReturn(Context, VT, ExtendKind); | |||
| 1586 | ||||
| 1587 | unsigned NumParts = TLI.getNumRegistersForCallingConv(Context, VT); | |||
| 1588 | MVT PartVT = TLI.getRegisterTypeForCallingConv(Context, VT); | |||
| 1589 | SmallVector<SDValue, 4> Parts(NumParts); | |||
| 1590 | getCopyToParts(DAG, getCurSDLoc(), | |||
| 1591 | SDValue(RetOp.getNode(), RetOp.getResNo() + j), | |||
| 1592 | &Parts[0], NumParts, PartVT, &I, ExtendKind, true); | |||
| 1593 | ||||
| 1594 | // 'inreg' on function refers to return value | |||
| 1595 | ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy(); | |||
| 1596 | if (RetInReg) | |||
| 1597 | Flags.setInReg(); | |||
| 1598 | ||||
| 1599 | // Propagate extension type if any | |||
| 1600 | if (ExtendKind == ISD::SIGN_EXTEND) | |||
| 1601 | Flags.setSExt(); | |||
| 1602 | else if (ExtendKind == ISD::ZERO_EXTEND) | |||
| 1603 | Flags.setZExt(); | |||
| 1604 | ||||
| 1605 | for (unsigned i = 0; i < NumParts; ++i) { | |||
| 1606 | Outs.push_back(ISD::OutputArg(Flags, Parts[i].getValueType(), | |||
| 1607 | VT, /*isfixed=*/true, 0, 0)); | |||
| 1608 | OutVals.push_back(Parts[i]); | |||
| 1609 | } | |||
| 1610 | } | |||
| 1611 | } | |||
| 1612 | } | |||
| 1613 | ||||
| 1614 | // Push in swifterror virtual register as the last element of Outs. This makes | |||
| 1615 | // sure swifterror virtual register will be returned in the swifterror | |||
| 1616 | // physical register. | |||
| 1617 | const Function *F = I.getParent()->getParent(); | |||
| 1618 | if (TLI.supportSwiftError() && | |||
| 1619 | F->getAttributes().hasAttrSomewhere(Attribute::SwiftError)) { | |||
| 1620 | assert(FuncInfo.SwiftErrorArg && "Need a swift error argument")(static_cast <bool> (FuncInfo.SwiftErrorArg && "Need a swift error argument" ) ? void (0) : __assert_fail ("FuncInfo.SwiftErrorArg && \"Need a swift error argument\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 1620, __extension__ __PRETTY_FUNCTION__)); | |||
| 1621 | ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy(); | |||
| 1622 | Flags.setSwiftError(); | |||
| 1623 | Outs.push_back(ISD::OutputArg(Flags, EVT(TLI.getPointerTy(DL)) /*vt*/, | |||
| 1624 | EVT(TLI.getPointerTy(DL)) /*argvt*/, | |||
| 1625 | true /*isfixed*/, 1 /*origidx*/, | |||
| 1626 | 0 /*partOffs*/)); | |||
| 1627 | // Create SDNode for the swifterror virtual register. | |||
| 1628 | OutVals.push_back( | |||
| 1629 | DAG.getRegister(FuncInfo.getOrCreateSwiftErrorVRegUseAt( | |||
| 1630 | &I, FuncInfo.MBB, FuncInfo.SwiftErrorArg).first, | |||
| 1631 | EVT(TLI.getPointerTy(DL)))); | |||
| 1632 | } | |||
| 1633 | ||||
| 1634 | bool isVarArg = DAG.getMachineFunction().getFunction().isVarArg(); | |||
| 1635 | CallingConv::ID CallConv = | |||
| 1636 | DAG.getMachineFunction().getFunction().getCallingConv(); | |||
| 1637 | Chain = DAG.getTargetLoweringInfo().LowerReturn( | |||
| 1638 | Chain, CallConv, isVarArg, Outs, OutVals, getCurSDLoc(), DAG); | |||
| 1639 | ||||
| 1640 | // Verify that the target's LowerReturn behaved as expected. | |||
| 1641 | assert(Chain.getNode() && Chain.getValueType() == MVT::Other &&(static_cast <bool> (Chain.getNode() && Chain.getValueType () == MVT::Other && "LowerReturn didn't return a valid chain!" ) ? void (0) : __assert_fail ("Chain.getNode() && Chain.getValueType() == MVT::Other && \"LowerReturn didn't return a valid chain!\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 1642, __extension__ __PRETTY_FUNCTION__)) | |||
| 1642 | "LowerReturn didn't return a valid chain!")(static_cast <bool> (Chain.getNode() && Chain.getValueType () == MVT::Other && "LowerReturn didn't return a valid chain!" ) ? void (0) : __assert_fail ("Chain.getNode() && Chain.getValueType() == MVT::Other && \"LowerReturn didn't return a valid chain!\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 1642, __extension__ __PRETTY_FUNCTION__)); | |||
| 1643 | ||||
| 1644 | // Update the DAG with the new chain value resulting from return lowering. | |||
| 1645 | DAG.setRoot(Chain); | |||
| 1646 | } | |||
| 1647 | ||||
| 1648 | /// CopyToExportRegsIfNeeded - If the given value has virtual registers | |||
| 1649 | /// created for it, emit nodes to copy the value into the virtual | |||
| 1650 | /// registers. | |||
| 1651 | void SelectionDAGBuilder::CopyToExportRegsIfNeeded(const Value *V) { | |||
| 1652 | // Skip empty types | |||
| 1653 | if (V->getType()->isEmptyTy()) | |||
| 1654 | return; | |||
| 1655 | ||||
| 1656 | DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V); | |||
| 1657 | if (VMI != FuncInfo.ValueMap.end()) { | |||
| 1658 | assert(!V->use_empty() && "Unused value assigned virtual registers!")(static_cast <bool> (!V->use_empty() && "Unused value assigned virtual registers!" ) ? void (0) : __assert_fail ("!V->use_empty() && \"Unused value assigned virtual registers!\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 1658, __extension__ __PRETTY_FUNCTION__)); | |||
| 1659 | CopyValueToVirtualRegister(V, VMI->second); | |||
| 1660 | } | |||
| 1661 | } | |||
| 1662 | ||||
| 1663 | /// ExportFromCurrentBlock - If this condition isn't known to be exported from | |||
| 1664 | /// the current basic block, add it to ValueMap now so that we'll get a | |||
| 1665 | /// CopyTo/FromReg. | |||
| 1666 | void SelectionDAGBuilder::ExportFromCurrentBlock(const Value *V) { | |||
| 1667 | // No need to export constants. | |||
| 1668 | if (!isa<Instruction>(V) && !isa<Argument>(V)) return; | |||
| 1669 | ||||
| 1670 | // Already exported? | |||
| 1671 | if (FuncInfo.isExportedInst(V)) return; | |||
| 1672 | ||||
| 1673 | unsigned Reg = FuncInfo.InitializeRegForValue(V); | |||
| 1674 | CopyValueToVirtualRegister(V, Reg); | |||
| 1675 | } | |||
| 1676 | ||||
| 1677 | bool SelectionDAGBuilder::isExportableFromCurrentBlock(const Value *V, | |||
| 1678 | const BasicBlock *FromBB) { | |||
| 1679 | // The operands of the setcc have to be in this block. We don't know | |||
| 1680 | // how to export them from some other block. | |||
| 1681 | if (const Instruction *VI = dyn_cast<Instruction>(V)) { | |||
| 1682 | // Can export from current BB. | |||
| 1683 | if (VI->getParent() == FromBB) | |||
| 1684 | return true; | |||
| 1685 | ||||
| 1686 | // Is already exported, noop. | |||
| 1687 | return FuncInfo.isExportedInst(V); | |||
| 1688 | } | |||
| 1689 | ||||
| 1690 | // If this is an argument, we can export it if the BB is the entry block or | |||
| 1691 | // if it is already exported. | |||
| 1692 | if (isa<Argument>(V)) { | |||
| 1693 | if (FromBB == &FromBB->getParent()->getEntryBlock()) | |||
| 1694 | return true; | |||
| 1695 | ||||
| 1696 | // Otherwise, can only export this if it is already exported. | |||
| 1697 | return FuncInfo.isExportedInst(V); | |||
| 1698 | } | |||
| 1699 | ||||
| 1700 | // Otherwise, constants can always be exported. | |||
| 1701 | return true; | |||
| 1702 | } | |||
| 1703 | ||||
| 1704 | /// Return branch probability calculated by BranchProbabilityInfo for IR blocks. | |||
| 1705 | BranchProbability | |||
| 1706 | SelectionDAGBuilder::getEdgeProbability(const MachineBasicBlock *Src, | |||
| 1707 | const MachineBasicBlock *Dst) const { | |||
| 1708 | BranchProbabilityInfo *BPI = FuncInfo.BPI; | |||
| 1709 | const BasicBlock *SrcBB = Src->getBasicBlock(); | |||
| 1710 | const BasicBlock *DstBB = Dst->getBasicBlock(); | |||
| 1711 | if (!BPI) { | |||
| 1712 | // If BPI is not available, set the default probability as 1 / N, where N is | |||
| 1713 | // the number of successors. | |||
| 1714 | auto SuccSize = std::max<uint32_t>(succ_size(SrcBB), 1); | |||
| 1715 | return BranchProbability(1, SuccSize); | |||
| 1716 | } | |||
| 1717 | return BPI->getEdgeProbability(SrcBB, DstBB); | |||
| 1718 | } | |||
| 1719 | ||||
| 1720 | void SelectionDAGBuilder::addSuccessorWithProb(MachineBasicBlock *Src, | |||
| 1721 | MachineBasicBlock *Dst, | |||
| 1722 | BranchProbability Prob) { | |||
| 1723 | if (!FuncInfo.BPI) | |||
| 1724 | Src->addSuccessorWithoutProb(Dst); | |||
| 1725 | else { | |||
| 1726 | if (Prob.isUnknown()) | |||
| 1727 | Prob = getEdgeProbability(Src, Dst); | |||
| 1728 | Src->addSuccessor(Dst, Prob); | |||
| 1729 | } | |||
| 1730 | } | |||
| 1731 | ||||
| 1732 | static bool InBlock(const Value *V, const BasicBlock *BB) { | |||
| 1733 | if (const Instruction *I = dyn_cast<Instruction>(V)) | |||
| 1734 | return I->getParent() == BB; | |||
| 1735 | return true; | |||
| 1736 | } | |||
| 1737 | ||||
| 1738 | /// EmitBranchForMergedCondition - Helper method for FindMergedConditions. | |||
| 1739 | /// This function emits a branch and is used at the leaves of an OR or an | |||
| 1740 | /// AND operator tree. | |||
| 1741 | void | |||
| 1742 | SelectionDAGBuilder::EmitBranchForMergedCondition(const Value *Cond, | |||
| 1743 | MachineBasicBlock *TBB, | |||
| 1744 | MachineBasicBlock *FBB, | |||
| 1745 | MachineBasicBlock *CurBB, | |||
| 1746 | MachineBasicBlock *SwitchBB, | |||
| 1747 | BranchProbability TProb, | |||
| 1748 | BranchProbability FProb, | |||
| 1749 | bool InvertCond) { | |||
| 1750 | const BasicBlock *BB = CurBB->getBasicBlock(); | |||
| 1751 | ||||
| 1752 | // If the leaf of the tree is a comparison, merge the condition into | |||
| 1753 | // the caseblock. | |||
| 1754 | if (const CmpInst *BOp = dyn_cast<CmpInst>(Cond)) { | |||
| 1755 | // The operands of the cmp have to be in this block. We don't know | |||
| 1756 | // how to export them from some other block. If this is the first block | |||
| 1757 | // of the sequence, no exporting is needed. | |||
| 1758 | if (CurBB == SwitchBB || | |||
| 1759 | (isExportableFromCurrentBlock(BOp->getOperand(0), BB) && | |||
| 1760 | isExportableFromCurrentBlock(BOp->getOperand(1), BB))) { | |||
| 1761 | ISD::CondCode Condition; | |||
| 1762 | if (const ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) { | |||
| 1763 | ICmpInst::Predicate Pred = | |||
| 1764 | InvertCond ? IC->getInversePredicate() : IC->getPredicate(); | |||
| 1765 | Condition = getICmpCondCode(Pred); | |||
| 1766 | } else { | |||
| 1767 | const FCmpInst *FC = cast<FCmpInst>(Cond); | |||
| 1768 | FCmpInst::Predicate Pred = | |||
| 1769 | InvertCond ? FC->getInversePredicate() : FC->getPredicate(); | |||
| 1770 | Condition = getFCmpCondCode(Pred); | |||
| 1771 | if (TM.Options.NoNaNsFPMath) | |||
| 1772 | Condition = getFCmpCodeWithoutNaN(Condition); | |||
| 1773 | } | |||
| 1774 | ||||
| 1775 | CaseBlock CB(Condition, BOp->getOperand(0), BOp->getOperand(1), nullptr, | |||
| 1776 | TBB, FBB, CurBB, getCurSDLoc(), TProb, FProb); | |||
| 1777 | SwitchCases.push_back(CB); | |||
| 1778 | return; | |||
| 1779 | } | |||
| 1780 | } | |||
| 1781 | ||||
| 1782 | // Create a CaseBlock record representing this branch. | |||
| 1783 | ISD::CondCode Opc = InvertCond ? ISD::SETNE : ISD::SETEQ; | |||
| 1784 | CaseBlock CB(Opc, Cond, ConstantInt::getTrue(*DAG.getContext()), | |||
| 1785 | nullptr, TBB, FBB, CurBB, getCurSDLoc(), TProb, FProb); | |||
| 1786 | SwitchCases.push_back(CB); | |||
| 1787 | } | |||
| 1788 | ||||
| 1789 | /// FindMergedConditions - If Cond is an expression like | |||
| 1790 | void SelectionDAGBuilder::FindMergedConditions(const Value *Cond, | |||
| 1791 | MachineBasicBlock *TBB, | |||
| 1792 | MachineBasicBlock *FBB, | |||
| 1793 | MachineBasicBlock *CurBB, | |||
| 1794 | MachineBasicBlock *SwitchBB, | |||
| 1795 | Instruction::BinaryOps Opc, | |||
| 1796 | BranchProbability TProb, | |||
| 1797 | BranchProbability FProb, | |||
| 1798 | bool InvertCond) { | |||
| 1799 | // Skip over not part of the tree and remember to invert op and operands at | |||
| 1800 | // next level. | |||
| 1801 | if (BinaryOperator::isNot(Cond) && Cond->hasOneUse()) { | |||
| 1802 | const Value *CondOp = BinaryOperator::getNotArgument(Cond); | |||
| 1803 | if (InBlock(CondOp, CurBB->getBasicBlock())) { | |||
| 1804 | FindMergedConditions(CondOp, TBB, FBB, CurBB, SwitchBB, Opc, TProb, FProb, | |||
| 1805 | !InvertCond); | |||
| 1806 | return; | |||
| 1807 | } | |||
| 1808 | } | |||
| 1809 | ||||
| 1810 | const Instruction *BOp = dyn_cast<Instruction>(Cond); | |||
| 1811 | // Compute the effective opcode for Cond, taking into account whether it needs | |||
| 1812 | // to be inverted, e.g. | |||
| 1813 | // and (not (or A, B)), C | |||
| 1814 | // gets lowered as | |||
| 1815 | // and (and (not A, not B), C) | |||
| 1816 | unsigned BOpc = 0; | |||
| 1817 | if (BOp) { | |||
| 1818 | BOpc = BOp->getOpcode(); | |||
| 1819 | if (InvertCond) { | |||
| 1820 | if (BOpc == Instruction::And) | |||
| 1821 | BOpc = Instruction::Or; | |||
| 1822 | else if (BOpc == Instruction::Or) | |||
| 1823 | BOpc = Instruction::And; | |||
| 1824 | } | |||
| 1825 | } | |||
| 1826 | ||||
| 1827 | // If this node is not part of the or/and tree, emit it as a branch. | |||
| 1828 | if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) || | |||
| 1829 | BOpc != unsigned(Opc) || !BOp->hasOneUse() || | |||
| 1830 | BOp->getParent() != CurBB->getBasicBlock() || | |||
| 1831 | !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) || | |||
| 1832 | !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) { | |||
| 1833 | EmitBranchForMergedCondition(Cond, TBB, FBB, CurBB, SwitchBB, | |||
| 1834 | TProb, FProb, InvertCond); | |||
| 1835 | return; | |||
| 1836 | } | |||
| 1837 | ||||
| 1838 | // Create TmpBB after CurBB. | |||
| 1839 | MachineFunction::iterator BBI(CurBB); | |||
| 1840 | MachineFunction &MF = DAG.getMachineFunction(); | |||
| 1841 | MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock()); | |||
| 1842 | CurBB->getParent()->insert(++BBI, TmpBB); | |||
| 1843 | ||||
| 1844 | if (Opc == Instruction::Or) { | |||
| 1845 | // Codegen X | Y as: | |||
| 1846 | // BB1: | |||
| 1847 | // jmp_if_X TBB | |||
| 1848 | // jmp TmpBB | |||
| 1849 | // TmpBB: | |||
| 1850 | // jmp_if_Y TBB | |||
| 1851 | // jmp FBB | |||
| 1852 | // | |||
| 1853 | ||||
| 1854 | // We have flexibility in setting Prob for BB1 and Prob for TmpBB. | |||
| 1855 | // The requirement is that | |||
| 1856 | // TrueProb for BB1 + (FalseProb for BB1 * TrueProb for TmpBB) | |||
| 1857 | // = TrueProb for original BB. | |||
| 1858 | // Assuming the original probabilities are A and B, one choice is to set | |||
| 1859 | // BB1's probabilities to A/2 and A/2+B, and set TmpBB's probabilities to | |||
| 1860 | // A/(1+B) and 2B/(1+B). This choice assumes that | |||
| 1861 | // TrueProb for BB1 == FalseProb for BB1 * TrueProb for TmpBB. | |||
| 1862 | // Another choice is to assume TrueProb for BB1 equals to TrueProb for | |||
| 1863 | // TmpBB, but the math is more complicated. | |||
| 1864 | ||||
| 1865 | auto NewTrueProb = TProb / 2; | |||
| 1866 | auto NewFalseProb = TProb / 2 + FProb; | |||
| 1867 | // Emit the LHS condition. | |||
| 1868 | FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, SwitchBB, Opc, | |||
| 1869 | NewTrueProb, NewFalseProb, InvertCond); | |||
| 1870 | ||||
| 1871 | // Normalize A/2 and B to get A/(1+B) and 2B/(1+B). | |||
| 1872 | SmallVector<BranchProbability, 2> Probs{TProb / 2, FProb}; | |||
| 1873 | BranchProbability::normalizeProbabilities(Probs.begin(), Probs.end()); | |||
| 1874 | // Emit the RHS condition into TmpBB. | |||
| 1875 | FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc, | |||
| 1876 | Probs[0], Probs[1], InvertCond); | |||
| 1877 | } else { | |||
| 1878 | assert(Opc == Instruction::And && "Unknown merge op!")(static_cast <bool> (Opc == Instruction::And && "Unknown merge op!") ? void (0) : __assert_fail ("Opc == Instruction::And && \"Unknown merge op!\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 1878, __extension__ __PRETTY_FUNCTION__)); | |||
| 1879 | // Codegen X & Y as: | |||
| 1880 | // BB1: | |||
| 1881 | // jmp_if_X TmpBB | |||
| 1882 | // jmp FBB | |||
| 1883 | // TmpBB: | |||
| 1884 | // jmp_if_Y TBB | |||
| 1885 | // jmp FBB | |||
| 1886 | // | |||
| 1887 | // This requires creation of TmpBB after CurBB. | |||
| 1888 | ||||
| 1889 | // We have flexibility in setting Prob for BB1 and Prob for TmpBB. | |||
| 1890 | // The requirement is that | |||
| 1891 | // FalseProb for BB1 + (TrueProb for BB1 * FalseProb for TmpBB) | |||
| 1892 | // = FalseProb for original BB. | |||
| 1893 | // Assuming the original probabilities are A and B, one choice is to set | |||
| 1894 | // BB1's probabilities to A+B/2 and B/2, and set TmpBB's probabilities to | |||
| 1895 | // 2A/(1+A) and B/(1+A). This choice assumes that FalseProb for BB1 == | |||
| 1896 | // TrueProb for BB1 * FalseProb for TmpBB. | |||
| 1897 | ||||
| 1898 | auto NewTrueProb = TProb + FProb / 2; | |||
| 1899 | auto NewFalseProb = FProb / 2; | |||
| 1900 | // Emit the LHS condition. | |||
| 1901 | FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, SwitchBB, Opc, | |||
| 1902 | NewTrueProb, NewFalseProb, InvertCond); | |||
| 1903 | ||||
| 1904 | // Normalize A and B/2 to get 2A/(1+A) and B/(1+A). | |||
| 1905 | SmallVector<BranchProbability, 2> Probs{TProb, FProb / 2}; | |||
| 1906 | BranchProbability::normalizeProbabilities(Probs.begin(), Probs.end()); | |||
| 1907 | // Emit the RHS condition into TmpBB. | |||
| 1908 | FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc, | |||
| 1909 | Probs[0], Probs[1], InvertCond); | |||
| 1910 | } | |||
| 1911 | } | |||
| 1912 | ||||
| 1913 | /// If the set of cases should be emitted as a series of branches, return true. | |||
| 1914 | /// If we should emit this as a bunch of and/or'd together conditions, return | |||
| 1915 | /// false. | |||
| 1916 | bool | |||
| 1917 | SelectionDAGBuilder::ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases) { | |||
| 1918 | if (Cases.size() != 2) return true; | |||
| 1919 | ||||
| 1920 | // If this is two comparisons of the same values or'd or and'd together, they | |||
| 1921 | // will get folded into a single comparison, so don't emit two blocks. | |||
| 1922 | if ((Cases[0].CmpLHS == Cases[1].CmpLHS && | |||
| 1923 | Cases[0].CmpRHS == Cases[1].CmpRHS) || | |||
| 1924 | (Cases[0].CmpRHS == Cases[1].CmpLHS && | |||
| 1925 | Cases[0].CmpLHS == Cases[1].CmpRHS)) { | |||
| 1926 | return false; | |||
| 1927 | } | |||
| 1928 | ||||
| 1929 | // Handle: (X != null) | (Y != null) --> (X|Y) != 0 | |||
| 1930 | // Handle: (X == null) & (Y == null) --> (X|Y) == 0 | |||
| 1931 | if (Cases[0].CmpRHS == Cases[1].CmpRHS && | |||
| 1932 | Cases[0].CC == Cases[1].CC && | |||
| 1933 | isa<Constant>(Cases[0].CmpRHS) && | |||
| 1934 | cast<Constant>(Cases[0].CmpRHS)->isNullValue()) { | |||
| 1935 | if (Cases[0].CC == ISD::SETEQ && Cases[0].TrueBB == Cases[1].ThisBB) | |||
| 1936 | return false; | |||
| 1937 | if (Cases[0].CC == ISD::SETNE && Cases[0].FalseBB == Cases[1].ThisBB) | |||
| 1938 | return false; | |||
| 1939 | } | |||
| 1940 | ||||
| 1941 | return true; | |||
| 1942 | } | |||
| 1943 | ||||
| 1944 | void SelectionDAGBuilder::visitBr(const BranchInst &I) { | |||
| 1945 | MachineBasicBlock *BrMBB = FuncInfo.MBB; | |||
| 1946 | ||||
| 1947 | // Update machine-CFG edges. | |||
| 1948 | MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)]; | |||
| 1949 | ||||
| 1950 | if (I.isUnconditional()) { | |||
| 1951 | // Update machine-CFG edges. | |||
| 1952 | BrMBB->addSuccessor(Succ0MBB); | |||
| 1953 | ||||
| 1954 | // If this is not a fall-through branch or optimizations are switched off, | |||
| 1955 | // emit the branch. | |||
| 1956 | if (Succ0MBB != NextBlock(BrMBB) || TM.getOptLevel() == CodeGenOpt::None) | |||
| 1957 | DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(), | |||
| 1958 | MVT::Other, getControlRoot(), | |||
| 1959 | DAG.getBasicBlock(Succ0MBB))); | |||
| 1960 | ||||
| 1961 | return; | |||
| 1962 | } | |||
| 1963 | ||||
| 1964 | // If this condition is one of the special cases we handle, do special stuff | |||
| 1965 | // now. | |||
| 1966 | const Value *CondVal = I.getCondition(); | |||
| 1967 | MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)]; | |||
| 1968 | ||||
| 1969 | // If this is a series of conditions that are or'd or and'd together, emit | |||
| 1970 | // this as a sequence of branches instead of setcc's with and/or operations. | |||
| 1971 | // As long as jumps are not expensive, this should improve performance. | |||
| 1972 | // For example, instead of something like: | |||
| 1973 | // cmp A, B | |||
| 1974 | // C = seteq | |||
| 1975 | // cmp D, E | |||
| 1976 | // F = setle | |||
| 1977 | // or C, F | |||
| 1978 | // jnz foo | |||
| 1979 | // Emit: | |||
| 1980 | // cmp A, B | |||
| 1981 | // je foo | |||
| 1982 | // cmp D, E | |||
| 1983 | // jle foo | |||
| 1984 | if (const BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) { | |||
| 1985 | Instruction::BinaryOps Opcode = BOp->getOpcode(); | |||
| 1986 | if (!DAG.getTargetLoweringInfo().isJumpExpensive() && BOp->hasOneUse() && | |||
| 1987 | !I.getMetadata(LLVMContext::MD_unpredictable) && | |||
| 1988 | (Opcode == Instruction::And || Opcode == Instruction::Or)) { | |||
| 1989 | FindMergedConditions(BOp, Succ0MBB, Succ1MBB, BrMBB, BrMBB, | |||
| 1990 | Opcode, | |||
| 1991 | getEdgeProbability(BrMBB, Succ0MBB), | |||
| 1992 | getEdgeProbability(BrMBB, Succ1MBB), | |||
| 1993 | /*InvertCond=*/false); | |||
| 1994 | // If the compares in later blocks need to use values not currently | |||
| 1995 | // exported from this block, export them now. This block should always | |||
| 1996 | // be the first entry. | |||
| 1997 | assert(SwitchCases[0].ThisBB == BrMBB && "Unexpected lowering!")(static_cast <bool> (SwitchCases[0].ThisBB == BrMBB && "Unexpected lowering!") ? void (0) : __assert_fail ("SwitchCases[0].ThisBB == BrMBB && \"Unexpected lowering!\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 1997, __extension__ __PRETTY_FUNCTION__)); | |||
| 1998 | ||||
| 1999 | // Allow some cases to be rejected. | |||
| 2000 | if (ShouldEmitAsBranches(SwitchCases)) { | |||
| 2001 | for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) { | |||
| 2002 | ExportFromCurrentBlock(SwitchCases[i].CmpLHS); | |||
| 2003 | ExportFromCurrentBlock(SwitchCases[i].CmpRHS); | |||
| 2004 | } | |||
| 2005 | ||||
| 2006 | // Emit the branch for this block. | |||
| 2007 | visitSwitchCase(SwitchCases[0], BrMBB); | |||
| 2008 | SwitchCases.erase(SwitchCases.begin()); | |||
| 2009 | return; | |||
| 2010 | } | |||
| 2011 | ||||
| 2012 | // Okay, we decided not to do this, remove any inserted MBB's and clear | |||
| 2013 | // SwitchCases. | |||
| 2014 | for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) | |||
| 2015 | FuncInfo.MF->erase(SwitchCases[i].ThisBB); | |||
| 2016 | ||||
| 2017 | SwitchCases.clear(); | |||
| 2018 | } | |||
| 2019 | } | |||
| 2020 | ||||
| 2021 | // Create a CaseBlock record representing this branch. | |||
| 2022 | CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(*DAG.getContext()), | |||
| 2023 | nullptr, Succ0MBB, Succ1MBB, BrMBB, getCurSDLoc()); | |||
| 2024 | ||||
| 2025 | // Use visitSwitchCase to actually insert the fast branch sequence for this | |||
| 2026 | // cond branch. | |||
| 2027 | visitSwitchCase(CB, BrMBB); | |||
| 2028 | } | |||
| 2029 | ||||
| 2030 | /// visitSwitchCase - Emits the necessary code to represent a single node in | |||
| 2031 | /// the binary search tree resulting from lowering a switch instruction. | |||
| 2032 | void SelectionDAGBuilder::visitSwitchCase(CaseBlock &CB, | |||
| 2033 | MachineBasicBlock *SwitchBB) { | |||
| 2034 | SDValue Cond; | |||
| 2035 | SDValue CondLHS = getValue(CB.CmpLHS); | |||
| 2036 | SDLoc dl = CB.DL; | |||
| 2037 | ||||
| 2038 | // Build the setcc now. | |||
| 2039 | if (!CB.CmpMHS) { | |||
| 2040 | // Fold "(X == true)" to X and "(X == false)" to !X to | |||
| 2041 | // handle common cases produced by branch lowering. | |||
| 2042 | if (CB.CmpRHS == ConstantInt::getTrue(*DAG.getContext()) && | |||
| 2043 | CB.CC == ISD::SETEQ) | |||
| 2044 | Cond = CondLHS; | |||
| 2045 | else if (CB.CmpRHS == ConstantInt::getFalse(*DAG.getContext()) && | |||
| 2046 | CB.CC == ISD::SETEQ) { | |||
| 2047 | SDValue True = DAG.getConstant(1, dl, CondLHS.getValueType()); | |||
| 2048 | Cond = DAG.getNode(ISD::XOR, dl, CondLHS.getValueType(), CondLHS, True); | |||
| 2049 | } else | |||
| 2050 | Cond = DAG.getSetCC(dl, MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC); | |||
| 2051 | } else { | |||
| 2052 | assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now")(static_cast <bool> (CB.CC == ISD::SETLE && "Can handle only LE ranges now" ) ? void (0) : __assert_fail ("CB.CC == ISD::SETLE && \"Can handle only LE ranges now\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 2052, __extension__ __PRETTY_FUNCTION__)); | |||
| 2053 | ||||
| 2054 | const APInt& Low = cast<ConstantInt>(CB.CmpLHS)->getValue(); | |||
| 2055 | const APInt& High = cast<ConstantInt>(CB.CmpRHS)->getValue(); | |||
| 2056 | ||||
| 2057 | SDValue CmpOp = getValue(CB.CmpMHS); | |||
| 2058 | EVT VT = CmpOp.getValueType(); | |||
| 2059 | ||||
| 2060 | if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) { | |||
| 2061 | Cond = DAG.getSetCC(dl, MVT::i1, CmpOp, DAG.getConstant(High, dl, VT), | |||
| 2062 | ISD::SETLE); | |||
| 2063 | } else { | |||
| 2064 | SDValue SUB = DAG.getNode(ISD::SUB, dl, | |||
| 2065 | VT, CmpOp, DAG.getConstant(Low, dl, VT)); | |||
| 2066 | Cond = DAG.getSetCC(dl, MVT::i1, SUB, | |||
| 2067 | DAG.getConstant(High-Low, dl, VT), ISD::SETULE); | |||
| 2068 | } | |||
| 2069 | } | |||
| 2070 | ||||
| 2071 | // Update successor info | |||
| 2072 | addSuccessorWithProb(SwitchBB, CB.TrueBB, CB.TrueProb); | |||
| 2073 | // TrueBB and FalseBB are always different unless the incoming IR is | |||
| 2074 | // degenerate. This only happens when running llc on weird IR. | |||
| 2075 | if (CB.TrueBB != CB.FalseBB) | |||
| 2076 | addSuccessorWithProb(SwitchBB, CB.FalseBB, CB.FalseProb); | |||
| 2077 | SwitchBB->normalizeSuccProbs(); | |||
| 2078 | ||||
| 2079 | // If the lhs block is the next block, invert the condition so that we can | |||
| 2080 | // fall through to the lhs instead of the rhs block. | |||
| 2081 | if (CB.TrueBB == NextBlock(SwitchBB)) { | |||
| 2082 | std::swap(CB.TrueBB, CB.FalseBB); | |||
| 2083 | SDValue True = DAG.getConstant(1, dl, Cond.getValueType()); | |||
| 2084 | Cond = DAG.getNode(ISD::XOR, dl, Cond.getValueType(), Cond, True); | |||
| 2085 | } | |||
| 2086 | ||||
| 2087 | SDValue BrCond = DAG.getNode(ISD::BRCOND, dl, | |||
| 2088 | MVT::Other, getControlRoot(), Cond, | |||
| 2089 | DAG.getBasicBlock(CB.TrueBB)); | |||
| 2090 | ||||
| 2091 | // Insert the false branch. Do this even if it's a fall through branch, | |||
| 2092 | // this makes it easier to do DAG optimizations which require inverting | |||
| 2093 | // the branch condition. | |||
| 2094 | BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond, | |||
| 2095 | DAG.getBasicBlock(CB.FalseBB)); | |||
| 2096 | ||||
| 2097 | DAG.setRoot(BrCond); | |||
| 2098 | } | |||
| 2099 | ||||
| 2100 | /// visitJumpTable - Emit JumpTable node in the current MBB | |||
| 2101 | void SelectionDAGBuilder::visitJumpTable(JumpTable &JT) { | |||
| 2102 | // Emit the code for the jump table | |||
| 2103 | assert(JT.Reg != -1U && "Should lower JT Header first!")(static_cast <bool> (JT.Reg != -1U && "Should lower JT Header first!" ) ? void (0) : __assert_fail ("JT.Reg != -1U && \"Should lower JT Header first!\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 2103, __extension__ __PRETTY_FUNCTION__)); | |||
| 2104 | EVT PTy = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout()); | |||
| 2105 | SDValue Index = DAG.getCopyFromReg(getControlRoot(), getCurSDLoc(), | |||
| 2106 | JT.Reg, PTy); | |||
| 2107 | SDValue Table = DAG.getJumpTable(JT.JTI, PTy); | |||
| 2108 | SDValue BrJumpTable = DAG.getNode(ISD::BR_JT, getCurSDLoc(), | |||
| 2109 | MVT::Other, Index.getValue(1), | |||
| 2110 | Table, Index); | |||
| 2111 | DAG.setRoot(BrJumpTable); | |||
| 2112 | } | |||
| 2113 | ||||
| 2114 | /// visitJumpTableHeader - This function emits necessary code to produce index | |||
| 2115 | /// in the JumpTable from switch case. | |||
| 2116 | void SelectionDAGBuilder::visitJumpTableHeader(JumpTable &JT, | |||
| 2117 | JumpTableHeader &JTH, | |||
| 2118 | MachineBasicBlock *SwitchBB) { | |||
| 2119 | SDLoc dl = getCurSDLoc(); | |||
| 2120 | ||||
| 2121 | // Subtract the lowest switch case value from the value being switched on and | |||
| 2122 | // conditional branch to default mbb if the result is greater than the | |||
| 2123 | // difference between smallest and largest cases. | |||
| 2124 | SDValue SwitchOp = getValue(JTH.SValue); | |||
| 2125 | EVT VT = SwitchOp.getValueType(); | |||
| 2126 | SDValue Sub = DAG.getNode(ISD::SUB, dl, VT, SwitchOp, | |||
| 2127 | DAG.getConstant(JTH.First, dl, VT)); | |||
| 2128 | ||||
| 2129 | // The SDNode we just created, which holds the value being switched on minus | |||
| 2130 | // the smallest case value, needs to be copied to a virtual register so it | |||
| 2131 | // can be used as an index into the jump table in a subsequent basic block. | |||
| 2132 | // This value may be smaller or larger than the target's pointer type, and | |||
| 2133 | // therefore require extension or truncating. | |||
| 2134 | const TargetLowering &TLI = DAG.getTargetLoweringInfo(); | |||
| 2135 | SwitchOp = DAG.getZExtOrTrunc(Sub, dl, TLI.getPointerTy(DAG.getDataLayout())); | |||
| 2136 | ||||
| 2137 | unsigned JumpTableReg = | |||
| 2138 | FuncInfo.CreateReg(TLI.getPointerTy(DAG.getDataLayout())); | |||
| 2139 | SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), dl, | |||
| 2140 | JumpTableReg, SwitchOp); | |||
| 2141 | JT.Reg = JumpTableReg; | |||
| 2142 | ||||
| 2143 | // Emit the range check for the jump table, and branch to the default block | |||
| 2144 | // for the switch statement if the value being switched on exceeds the largest | |||
| 2145 | // case in the switch. | |||
| 2146 | SDValue CMP = DAG.getSetCC( | |||
| 2147 | dl, TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), | |||
| 2148 | Sub.getValueType()), | |||
| 2149 | Sub, DAG.getConstant(JTH.Last - JTH.First, dl, VT), ISD::SETUGT); | |||
| 2150 | ||||
| 2151 | SDValue BrCond = DAG.getNode(ISD::BRCOND, dl, | |||
| 2152 | MVT::Other, CopyTo, CMP, | |||
| 2153 | DAG.getBasicBlock(JT.Default)); | |||
| 2154 | ||||
| 2155 | // Avoid emitting unnecessary branches to the next block. | |||
| 2156 | if (JT.MBB != NextBlock(SwitchBB)) | |||
| 2157 | BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond, | |||
| 2158 | DAG.getBasicBlock(JT.MBB)); | |||
| 2159 | ||||
| 2160 | DAG.setRoot(BrCond); | |||
| 2161 | } | |||
| 2162 | ||||
| 2163 | /// Create a LOAD_STACK_GUARD node, and let it carry the target specific global | |||
| 2164 | /// variable if there exists one. | |||
| 2165 | static SDValue getLoadStackGuard(SelectionDAG &DAG, const SDLoc &DL, | |||
| 2166 | SDValue &Chain) { | |||
| 2167 | const TargetLowering &TLI = DAG.getTargetLoweringInfo(); | |||
| 2168 | EVT PtrTy = TLI.getPointerTy(DAG.getDataLayout()); | |||
| 2169 | MachineFunction &MF = DAG.getMachineFunction(); | |||
| 2170 | Value *Global = TLI.getSDagStackGuard(*MF.getFunction().getParent()); | |||
| 2171 | MachineSDNode *Node = | |||
| 2172 | DAG.getMachineNode(TargetOpcode::LOAD_STACK_GUARD, DL, PtrTy, Chain); | |||
| 2173 | if (Global) { | |||
| 2174 | MachinePointerInfo MPInfo(Global); | |||
| 2175 | MachineInstr::mmo_iterator MemRefs = MF.allocateMemRefsArray(1); | |||
| 2176 | auto Flags = MachineMemOperand::MOLoad | MachineMemOperand::MOInvariant | | |||
| 2177 | MachineMemOperand::MODereferenceable; | |||
| 2178 | *MemRefs = MF.getMachineMemOperand(MPInfo, Flags, PtrTy.getSizeInBits() / 8, | |||
| 2179 | DAG.getEVTAlignment(PtrTy)); | |||
| 2180 | Node->setMemRefs(MemRefs, MemRefs + 1); | |||
| 2181 | } | |||
| 2182 | return SDValue(Node, 0); | |||
| 2183 | } | |||
| 2184 | ||||
| 2185 | /// Codegen a new tail for a stack protector check ParentMBB which has had its | |||
| 2186 | /// tail spliced into a stack protector check success bb. | |||
| 2187 | /// | |||
| 2188 | /// For a high level explanation of how this fits into the stack protector | |||
| 2189 | /// generation see the comment on the declaration of class | |||
| 2190 | /// StackProtectorDescriptor. | |||
| 2191 | void SelectionDAGBuilder::visitSPDescriptorParent(StackProtectorDescriptor &SPD, | |||
| 2192 | MachineBasicBlock *ParentBB) { | |||
| 2193 | ||||
| 2194 | // First create the loads to the guard/stack slot for the comparison. | |||
| 2195 | const TargetLowering &TLI = DAG.getTargetLoweringInfo(); | |||
| 2196 | EVT PtrTy = TLI.getPointerTy(DAG.getDataLayout()); | |||
| 2197 | ||||
| 2198 | MachineFrameInfo &MFI = ParentBB->getParent()->getFrameInfo(); | |||
| 2199 | int FI = MFI.getStackProtectorIndex(); | |||
| 2200 | ||||
| 2201 | SDValue Guard; | |||
| 2202 | SDLoc dl = getCurSDLoc(); | |||
| 2203 | SDValue StackSlotPtr = DAG.getFrameIndex(FI, PtrTy); | |||
| 2204 | const Module &M = *ParentBB->getParent()->getFunction().getParent(); | |||
| 2205 | unsigned Align = DL->getPrefTypeAlignment(Type::getInt8PtrTy(M.getContext())); | |||
| 2206 | ||||
| 2207 | // Generate code to load the content of the guard slot. | |||
| 2208 | SDValue GuardVal = DAG.getLoad( | |||
| 2209 | PtrTy, dl, DAG.getEntryNode(), StackSlotPtr, | |||
| 2210 | MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI), Align, | |||
| 2211 | MachineMemOperand::MOVolatile); | |||
| 2212 | ||||
| 2213 | if (TLI.useStackGuardXorFP()) | |||
| 2214 | GuardVal = TLI.emitStackGuardXorFP(DAG, GuardVal, dl); | |||
| 2215 | ||||
| 2216 | // Retrieve guard check function, nullptr if instrumentation is inlined. | |||
| 2217 | if (const Value *GuardCheck = TLI.getSSPStackGuardCheck(M)) { | |||
| 2218 | // The target provides a guard check function to validate the guard value. | |||
| 2219 | // Generate a call to that function with the content of the guard slot as | |||
| 2220 | // argument. | |||
| 2221 | auto *Fn = cast<Function>(GuardCheck); | |||
| 2222 | FunctionType *FnTy = Fn->getFunctionType(); | |||
| 2223 | assert(FnTy->getNumParams() == 1 && "Invalid function signature")(static_cast <bool> (FnTy->getNumParams() == 1 && "Invalid function signature") ? void (0) : __assert_fail ("FnTy->getNumParams() == 1 && \"Invalid function signature\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 2223, __extension__ __PRETTY_FUNCTION__)); | |||
| 2224 | ||||
| 2225 | TargetLowering::ArgListTy Args; | |||
| 2226 | TargetLowering::ArgListEntry Entry; | |||
| 2227 | Entry.Node = GuardVal; | |||
| 2228 | Entry.Ty = FnTy->getParamType(0); | |||
| 2229 | if (Fn->hasAttribute(1, Attribute::AttrKind::InReg)) | |||
| 2230 | Entry.IsInReg = true; | |||
| 2231 | Args.push_back(Entry); | |||
| 2232 | ||||
| 2233 | TargetLowering::CallLoweringInfo CLI(DAG); | |||
| 2234 | CLI.setDebugLoc(getCurSDLoc()) | |||
| 2235 | .setChain(DAG.getEntryNode()) | |||
| 2236 | .setCallee(Fn->getCallingConv(), FnTy->getReturnType(), | |||
| 2237 | getValue(GuardCheck), std::move(Args)); | |||
| 2238 | ||||
| 2239 | std::pair<SDValue, SDValue> Result = TLI.LowerCallTo(CLI); | |||
| 2240 | DAG.setRoot(Result.second); | |||
| 2241 | return; | |||
| 2242 | } | |||
| 2243 | ||||
| 2244 | // If useLoadStackGuardNode returns true, generate LOAD_STACK_GUARD. | |||
| 2245 | // Otherwise, emit a volatile load to retrieve the stack guard value. | |||
| 2246 | SDValue Chain = DAG.getEntryNode(); | |||
| 2247 | if (TLI.useLoadStackGuardNode()) { | |||
| 2248 | Guard = getLoadStackGuard(DAG, dl, Chain); | |||
| 2249 | } else { | |||
| 2250 | const Value *IRGuard = TLI.getSDagStackGuard(M); | |||
| 2251 | SDValue GuardPtr = getValue(IRGuard); | |||
| 2252 | ||||
| 2253 | Guard = | |||
| 2254 | DAG.getLoad(PtrTy, dl, Chain, GuardPtr, MachinePointerInfo(IRGuard, 0), | |||
| 2255 | Align, MachineMemOperand::MOVolatile); | |||
| 2256 | } | |||
| 2257 | ||||
| 2258 | // Perform the comparison via a subtract/getsetcc. | |||
| 2259 | EVT VT = Guard.getValueType(); | |||
| 2260 | SDValue Sub = DAG.getNode(ISD::SUB, dl, VT, Guard, GuardVal); | |||
| 2261 | ||||
| 2262 | SDValue Cmp = DAG.getSetCC(dl, TLI.getSetCCResultType(DAG.getDataLayout(), | |||
| 2263 | *DAG.getContext(), | |||
| 2264 | Sub.getValueType()), | |||
| 2265 | Sub, DAG.getConstant(0, dl, VT), ISD::SETNE); | |||
| 2266 | ||||
| 2267 | // If the sub is not 0, then we know the guard/stackslot do not equal, so | |||
| 2268 | // branch to failure MBB. | |||
| 2269 | SDValue BrCond = DAG.getNode(ISD::BRCOND, dl, | |||
| 2270 | MVT::Other, GuardVal.getOperand(0), | |||
| 2271 | Cmp, DAG.getBasicBlock(SPD.getFailureMBB())); | |||
| 2272 | // Otherwise branch to success MBB. | |||
| 2273 | SDValue Br = DAG.getNode(ISD::BR, dl, | |||
| 2274 | MVT::Other, BrCond, | |||
| 2275 | DAG.getBasicBlock(SPD.getSuccessMBB())); | |||
| 2276 | ||||
| 2277 | DAG.setRoot(Br); | |||
| 2278 | } | |||
| 2279 | ||||
| 2280 | /// Codegen the failure basic block for a stack protector check. | |||
| 2281 | /// | |||
| 2282 | /// A failure stack protector machine basic block consists simply of a call to | |||
| 2283 | /// __stack_chk_fail(). | |||
| 2284 | /// | |||
| 2285 | /// For a high level explanation of how this fits into the stack protector | |||
| 2286 | /// generation see the comment on the declaration of class | |||
| 2287 | /// StackProtectorDescriptor. | |||
| 2288 | void | |||
| 2289 | SelectionDAGBuilder::visitSPDescriptorFailure(StackProtectorDescriptor &SPD) { | |||
| 2290 | const TargetLowering &TLI = DAG.getTargetLoweringInfo(); | |||
| 2291 | SDValue Chain = | |||
| 2292 | TLI.makeLibCall(DAG, RTLIB::STACKPROTECTOR_CHECK_FAIL, MVT::isVoid, | |||
| 2293 | None, false, getCurSDLoc(), false, false).second; | |||
| 2294 | DAG.setRoot(Chain); | |||
| 2295 | } | |||
| 2296 | ||||
| 2297 | /// visitBitTestHeader - This function emits necessary code to produce value | |||
| 2298 | /// suitable for "bit tests" | |||
| 2299 | void SelectionDAGBuilder::visitBitTestHeader(BitTestBlock &B, | |||
| 2300 | MachineBasicBlock *SwitchBB) { | |||
| 2301 | SDLoc dl = getCurSDLoc(); | |||
| 2302 | ||||
| 2303 | // Subtract the minimum value | |||
| 2304 | SDValue SwitchOp = getValue(B.SValue); | |||
| 2305 | EVT VT = SwitchOp.getValueType(); | |||
| 2306 | SDValue Sub = DAG.getNode(ISD::SUB, dl, VT, SwitchOp, | |||
| 2307 | DAG.getConstant(B.First, dl, VT)); | |||
| 2308 | ||||
| 2309 | // Check range | |||
| 2310 | const TargetLowering &TLI = DAG.getTargetLoweringInfo(); | |||
| 2311 | SDValue RangeCmp = DAG.getSetCC( | |||
| 2312 | dl, TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), | |||
| 2313 | Sub.getValueType()), | |||
| 2314 | Sub, DAG.getConstant(B.Range, dl, VT), ISD::SETUGT); | |||
| 2315 | ||||
| 2316 | // Determine the type of the test operands. | |||
| 2317 | bool UsePtrType = false; | |||
| 2318 | if (!TLI.isTypeLegal(VT)) | |||
| 2319 | UsePtrType = true; | |||
| 2320 | else { | |||
| 2321 | for (unsigned i = 0, e = B.Cases.size(); i != e; ++i) | |||
| 2322 | if (!isUIntN(VT.getSizeInBits(), B.Cases[i].Mask)) { | |||
| 2323 | // Switch table case range are encoded into series of masks. | |||
| 2324 | // Just use pointer type, it's guaranteed to fit. | |||
| 2325 | UsePtrType = true; | |||
| 2326 | break; | |||
| 2327 | } | |||
| 2328 | } | |||
| 2329 | if (UsePtrType) { | |||
| 2330 | VT = TLI.getPointerTy(DAG.getDataLayout()); | |||
| 2331 | Sub = DAG.getZExtOrTrunc(Sub, dl, VT); | |||
| 2332 | } | |||
| 2333 | ||||
| 2334 | B.RegVT = VT.getSimpleVT(); | |||
| 2335 | B.Reg = FuncInfo.CreateReg(B.RegVT); | |||
| 2336 | SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), dl, B.Reg, Sub); | |||
| 2337 | ||||
| 2338 | MachineBasicBlock* MBB = B.Cases[0].ThisBB; | |||
| 2339 | ||||
| 2340 | addSuccessorWithProb(SwitchBB, B.Default, B.DefaultProb); | |||
| 2341 | addSuccessorWithProb(SwitchBB, MBB, B.Prob); | |||
| 2342 | SwitchBB->normalizeSuccProbs(); | |||
| 2343 | ||||
| 2344 | SDValue BrRange = DAG.getNode(ISD::BRCOND, dl, | |||
| 2345 | MVT::Other, CopyTo, RangeCmp, | |||
| 2346 | DAG.getBasicBlock(B.Default)); | |||
| 2347 | ||||
| 2348 | // Avoid emitting unnecessary branches to the next block. | |||
| 2349 | if (MBB != NextBlock(SwitchBB)) | |||
| 2350 | BrRange = DAG.getNode(ISD::BR, dl, MVT::Other, BrRange, | |||
| 2351 | DAG.getBasicBlock(MBB)); | |||
| 2352 | ||||
| 2353 | DAG.setRoot(BrRange); | |||
| 2354 | } | |||
| 2355 | ||||
| 2356 | /// visitBitTestCase - this function produces one "bit test" | |||
| 2357 | void SelectionDAGBuilder::visitBitTestCase(BitTestBlock &BB, | |||
| 2358 | MachineBasicBlock* NextMBB, | |||
| 2359 | BranchProbability BranchProbToNext, | |||
| 2360 | unsigned Reg, | |||
| 2361 | BitTestCase &B, | |||
| 2362 | MachineBasicBlock *SwitchBB) { | |||
| 2363 | SDLoc dl = getCurSDLoc(); | |||
| 2364 | MVT VT = BB.RegVT; | |||
| 2365 | SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), dl, Reg, VT); | |||
| 2366 | SDValue Cmp; | |||
| 2367 | unsigned PopCount = countPopulation(B.Mask); | |||
| 2368 | const TargetLowering &TLI = DAG.getTargetLoweringInfo(); | |||
| 2369 | if (PopCount == 1) { | |||
| 2370 | // Testing for a single bit; just compare the shift count with what it | |||
| 2371 | // would need to be to shift a 1 bit in that position. | |||
| 2372 | Cmp = DAG.getSetCC( | |||
| 2373 | dl, TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT), | |||
| 2374 | ShiftOp, DAG.getConstant(countTrailingZeros(B.Mask), dl, VT), | |||
| 2375 | ISD::SETEQ); | |||
| 2376 | } else if (PopCount == BB.Range) { | |||
| 2377 | // There is only one zero bit in the range, test for it directly. | |||
| 2378 | Cmp = DAG.getSetCC( | |||
| 2379 | dl, TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT), | |||
| 2380 | ShiftOp, DAG.getConstant(countTrailingOnes(B.Mask), dl, VT), | |||
| 2381 | ISD::SETNE); | |||
| 2382 | } else { | |||
| 2383 | // Make desired shift | |||
| 2384 | SDValue SwitchVal = DAG.getNode(ISD::SHL, dl, VT, | |||
| 2385 | DAG.getConstant(1, dl, VT), ShiftOp); | |||
| 2386 | ||||
| 2387 | // Emit bit tests and jumps | |||
| 2388 | SDValue AndOp = DAG.getNode(ISD::AND, dl, | |||
| 2389 | VT, SwitchVal, DAG.getConstant(B.Mask, dl, VT)); | |||
| 2390 | Cmp = DAG.getSetCC( | |||
| 2391 | dl, TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT), | |||
| 2392 | AndOp, DAG.getConstant(0, dl, VT), ISD::SETNE); | |||
| 2393 | } | |||
| 2394 | ||||
| 2395 | // The branch probability from SwitchBB to B.TargetBB is B.ExtraProb. | |||
| 2396 | addSuccessorWithProb(SwitchBB, B.TargetBB, B.ExtraProb); | |||
| 2397 | // The branch probability from SwitchBB to NextMBB is BranchProbToNext. | |||
| 2398 | addSuccessorWithProb(SwitchBB, NextMBB, BranchProbToNext); | |||
| 2399 | // It is not guaranteed that the sum of B.ExtraProb and BranchProbToNext is | |||
| 2400 | // one as they are relative probabilities (and thus work more like weights), | |||
| 2401 | // and hence we need to normalize them to let the sum of them become one. | |||
| 2402 | SwitchBB->normalizeSuccProbs(); | |||
| 2403 | ||||
| 2404 | SDValue BrAnd = DAG.getNode(ISD::BRCOND, dl, | |||
| 2405 | MVT::Other, getControlRoot(), | |||
| 2406 | Cmp, DAG.getBasicBlock(B.TargetBB)); | |||
| 2407 | ||||
| 2408 | // Avoid emitting unnecessary branches to the next block. | |||
| 2409 | if (NextMBB != NextBlock(SwitchBB)) | |||
| 2410 | BrAnd = DAG.getNode(ISD::BR, dl, MVT::Other, BrAnd, | |||
| 2411 | DAG.getBasicBlock(NextMBB)); | |||
| 2412 | ||||
| 2413 | DAG.setRoot(BrAnd); | |||
| 2414 | } | |||
| 2415 | ||||
| 2416 | void SelectionDAGBuilder::visitInvoke(const InvokeInst &I) { | |||
| 2417 | MachineBasicBlock *InvokeMBB = FuncInfo.MBB; | |||
| 2418 | ||||
| 2419 | // Retrieve successors. Look through artificial IR level blocks like | |||
| 2420 | // catchswitch for successors. | |||
| 2421 | MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)]; | |||
| 2422 | const BasicBlock *EHPadBB = I.getSuccessor(1); | |||
| 2423 | ||||
| 2424 | // Deopt bundles are lowered in LowerCallSiteWithDeoptBundle, and we don't | |||
| 2425 | // have to do anything here to lower funclet bundles. | |||
| 2426 | assert(!I.hasOperandBundlesOtherThan((static_cast <bool> (!I.hasOperandBundlesOtherThan( {LLVMContext ::OB_deopt, LLVMContext::OB_funclet}) && "Cannot lower invokes with arbitrary operand bundles yet!" ) ? void (0) : __assert_fail ("!I.hasOperandBundlesOtherThan( {LLVMContext::OB_deopt, LLVMContext::OB_funclet}) && \"Cannot lower invokes with arbitrary operand bundles yet!\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 2428, __extension__ __PRETTY_FUNCTION__)) | |||
| 2427 | {LLVMContext::OB_deopt, LLVMContext::OB_funclet}) &&(static_cast <bool> (!I.hasOperandBundlesOtherThan( {LLVMContext ::OB_deopt, LLVMContext::OB_funclet}) && "Cannot lower invokes with arbitrary operand bundles yet!" ) ? void (0) : __assert_fail ("!I.hasOperandBundlesOtherThan( {LLVMContext::OB_deopt, LLVMContext::OB_funclet}) && \"Cannot lower invokes with arbitrary operand bundles yet!\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 2428, __extension__ __PRETTY_FUNCTION__)) | |||
| 2428 | "Cannot lower invokes with arbitrary operand bundles yet!")(static_cast <bool> (!I.hasOperandBundlesOtherThan( {LLVMContext ::OB_deopt, LLVMContext::OB_funclet}) && "Cannot lower invokes with arbitrary operand bundles yet!" ) ? void (0) : __assert_fail ("!I.hasOperandBundlesOtherThan( {LLVMContext::OB_deopt, LLVMContext::OB_funclet}) && \"Cannot lower invokes with arbitrary operand bundles yet!\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 2428, __extension__ __PRETTY_FUNCTION__)); | |||
| 2429 | ||||
| 2430 | const Value *Callee(I.getCalledValue()); | |||
| 2431 | const Function *Fn = dyn_cast<Function>(Callee); | |||
| 2432 | if (isa<InlineAsm>(Callee)) | |||
| 2433 | visitInlineAsm(&I); | |||
| 2434 | else if (Fn && Fn->isIntrinsic()) { | |||
| 2435 | switch (Fn->getIntrinsicID()) { | |||
| 2436 | default: | |||
| 2437 | llvm_unreachable("Cannot invoke this intrinsic")::llvm::llvm_unreachable_internal("Cannot invoke this intrinsic" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 2437); | |||
| 2438 | case Intrinsic::donothing: | |||
| 2439 | // Ignore invokes to @llvm.donothing: jump directly to the next BB. | |||
| 2440 | break; | |||
| 2441 | case Intrinsic::experimental_patchpoint_void: | |||
| 2442 | case Intrinsic::experimental_patchpoint_i64: | |||
| 2443 | visitPatchpoint(&I, EHPadBB); | |||
| 2444 | break; | |||
| 2445 | case Intrinsic::experimental_gc_statepoint: | |||
| 2446 | LowerStatepoint(ImmutableStatepoint(&I), EHPadBB); | |||
| 2447 | break; | |||
| 2448 | } | |||
| 2449 | } else if (I.countOperandBundlesOfType(LLVMContext::OB_deopt)) { | |||
| 2450 | // Currently we do not lower any intrinsic calls with deopt operand bundles. | |||
| 2451 | // Eventually we will support lowering the @llvm.experimental.deoptimize | |||
| 2452 | // intrinsic, and right now there are no plans to support other intrinsics | |||
| 2453 | // with deopt state. | |||
| 2454 | LowerCallSiteWithDeoptBundle(&I, getValue(Callee), EHPadBB); | |||
| 2455 | } else { | |||
| 2456 | LowerCallTo(&I, getValue(Callee), false, EHPadBB); | |||
| 2457 | } | |||
| 2458 | ||||
| 2459 | // If the value of the invoke is used outside of its defining block, make it | |||
| 2460 | // available as a virtual register. | |||
| 2461 | // We already took care of the exported value for the statepoint instruction | |||
| 2462 | // during call to the LowerStatepoint. | |||
| 2463 | if (!isStatepoint(I)) { | |||
| 2464 | CopyToExportRegsIfNeeded(&I); | |||
| 2465 | } | |||
| 2466 | ||||
| 2467 | SmallVector<std::pair<MachineBasicBlock *, BranchProbability>, 1> UnwindDests; | |||
| 2468 | BranchProbabilityInfo *BPI = FuncInfo.BPI; | |||
| 2469 | BranchProbability EHPadBBProb = | |||
| 2470 | BPI ? BPI->getEdgeProbability(InvokeMBB->getBasicBlock(), EHPadBB) | |||
| 2471 | : BranchProbability::getZero(); | |||
| 2472 | findUnwindDestinations(FuncInfo, EHPadBB, EHPadBBProb, UnwindDests); | |||
| 2473 | ||||
| 2474 | // Update successor info. | |||
| 2475 | addSuccessorWithProb(InvokeMBB, Return); | |||
| 2476 | for (auto &UnwindDest : UnwindDests) { | |||
| 2477 | UnwindDest.first->setIsEHPad(); | |||
| 2478 | addSuccessorWithProb(InvokeMBB, UnwindDest.first, UnwindDest.second); | |||
| 2479 | } | |||
| 2480 | InvokeMBB->normalizeSuccProbs(); | |||
| 2481 | ||||
| 2482 | // Drop into normal successor. | |||
| 2483 | DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(), | |||
| 2484 | MVT::Other, getControlRoot(), | |||
| 2485 | DAG.getBasicBlock(Return))); | |||
| 2486 | } | |||
| 2487 | ||||
| 2488 | void SelectionDAGBuilder::visitResume(const ResumeInst &RI) { | |||
| 2489 | llvm_unreachable("SelectionDAGBuilder shouldn't visit resume instructions!")::llvm::llvm_unreachable_internal("SelectionDAGBuilder shouldn't visit resume instructions!" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 2489); | |||
| 2490 | } | |||
| 2491 | ||||
| 2492 | void SelectionDAGBuilder::visitLandingPad(const LandingPadInst &LP) { | |||
| 2493 | assert(FuncInfo.MBB->isEHPad() &&(static_cast <bool> (FuncInfo.MBB->isEHPad() && "Call to landingpad not in landing pad!") ? void (0) : __assert_fail ("FuncInfo.MBB->isEHPad() && \"Call to landingpad not in landing pad!\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 2494, __extension__ __PRETTY_FUNCTION__)) | |||
| 2494 | "Call to landingpad not in landing pad!")(static_cast <bool> (FuncInfo.MBB->isEHPad() && "Call to landingpad not in landing pad!") ? void (0) : __assert_fail ("FuncInfo.MBB->isEHPad() && \"Call to landingpad not in landing pad!\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 2494, __extension__ __PRETTY_FUNCTION__)); | |||
| 2495 | ||||
| 2496 | MachineBasicBlock *MBB = FuncInfo.MBB; | |||
| 2497 | addLandingPadInfo(LP, *MBB); | |||
| 2498 | ||||
| 2499 | // If there aren't registers to copy the values into (e.g., during SjLj | |||
| 2500 | // exceptions), then don't bother to create these DAG nodes. | |||
| 2501 | const TargetLowering &TLI = DAG.getTargetLoweringInfo(); | |||
| 2502 | const Constant *PersonalityFn = FuncInfo.Fn->getPersonalityFn(); | |||
| 2503 | if (TLI.getExceptionPointerRegister(PersonalityFn) == 0 && | |||
| 2504 | TLI.getExceptionSelectorRegister(PersonalityFn) == 0) | |||
| 2505 | return; | |||
| 2506 | ||||
| 2507 | // If landingpad's return type is token type, we don't create DAG nodes | |||
| 2508 | // for its exception pointer and selector value. The extraction of exception | |||
| 2509 | // pointer or selector value from token type landingpads is not currently | |||
| 2510 | // supported. | |||
| 2511 | if (LP.getType()->isTokenTy()) | |||
| 2512 | return; | |||
| 2513 | ||||
| 2514 | SmallVector<EVT, 2> ValueVTs; | |||
| 2515 | SDLoc dl = getCurSDLoc(); | |||
| 2516 | ComputeValueVTs(TLI, DAG.getDataLayout(), LP.getType(), ValueVTs); | |||
| 2517 | assert(ValueVTs.size() == 2 && "Only two-valued landingpads are supported")(static_cast <bool> (ValueVTs.size() == 2 && "Only two-valued landingpads are supported" ) ? void (0) : __assert_fail ("ValueVTs.size() == 2 && \"Only two-valued landingpads are supported\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 2517, __extension__ __PRETTY_FUNCTION__)); | |||
| 2518 | ||||
| 2519 | // Get the two live-in registers as SDValues. The physregs have already been | |||
| 2520 | // copied into virtual registers. | |||
| 2521 | SDValue Ops[2]; | |||
| 2522 | if (FuncInfo.ExceptionPointerVirtReg) { | |||
| 2523 | Ops[0] = DAG.getZExtOrTrunc( | |||
| 2524 | DAG.getCopyFromReg(DAG.getEntryNode(), dl, | |||
| 2525 | FuncInfo.ExceptionPointerVirtReg, | |||
| 2526 | TLI.getPointerTy(DAG.getDataLayout())), | |||
| 2527 | dl, ValueVTs[0]); | |||
| 2528 | } else { | |||
| 2529 | Ops[0] = DAG.getConstant(0, dl, TLI.getPointerTy(DAG.getDataLayout())); | |||
| 2530 | } | |||
| 2531 | Ops[1] = DAG.getZExtOrTrunc( | |||
| 2532 | DAG.getCopyFromReg(DAG.getEntryNode(), dl, | |||
| 2533 | FuncInfo.ExceptionSelectorVirtReg, | |||
| 2534 | TLI.getPointerTy(DAG.getDataLayout())), | |||
| 2535 | dl, ValueVTs[1]); | |||
| 2536 | ||||
| 2537 | // Merge into one. | |||
| 2538 | SDValue Res = DAG.getNode(ISD::MERGE_VALUES, dl, | |||
| 2539 | DAG.getVTList(ValueVTs), Ops); | |||
| 2540 | setValue(&LP, Res); | |||
| 2541 | } | |||
| 2542 | ||||
| 2543 | void SelectionDAGBuilder::sortAndRangeify(CaseClusterVector &Clusters) { | |||
| 2544 | #ifndef NDEBUG | |||
| 2545 | for (const CaseCluster &CC : Clusters) | |||
| 2546 | assert(CC.Low == CC.High && "Input clusters must be single-case")(static_cast <bool> (CC.Low == CC.High && "Input clusters must be single-case" ) ? void (0) : __assert_fail ("CC.Low == CC.High && \"Input clusters must be single-case\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 2546, __extension__ __PRETTY_FUNCTION__)); | |||
| 2547 | #endif | |||
| 2548 | ||||
| 2549 | llvm::sort(Clusters.begin(), Clusters.end(), | |||
| 2550 | [](const CaseCluster &a, const CaseCluster &b) { | |||
| 2551 | return a.Low->getValue().slt(b.Low->getValue()); | |||
| 2552 | }); | |||
| 2553 | ||||
| 2554 | // Merge adjacent clusters with the same destination. | |||
| 2555 | const unsigned N = Clusters.size(); | |||
| 2556 | unsigned DstIndex = 0; | |||
| 2557 | for (unsigned SrcIndex = 0; SrcIndex < N; ++SrcIndex) { | |||
| 2558 | CaseCluster &CC = Clusters[SrcIndex]; | |||
| 2559 | const ConstantInt *CaseVal = CC.Low; | |||
| 2560 | MachineBasicBlock *Succ = CC.MBB; | |||
| 2561 | ||||
| 2562 | if (DstIndex != 0 && Clusters[DstIndex - 1].MBB == Succ && | |||
| 2563 | (CaseVal->getValue() - Clusters[DstIndex - 1].High->getValue()) == 1) { | |||
| 2564 | // If this case has the same successor and is a neighbour, merge it into | |||
| 2565 | // the previous cluster. | |||
| 2566 | Clusters[DstIndex - 1].High = CaseVal; | |||
| 2567 | Clusters[DstIndex - 1].Prob += CC.Prob; | |||
| 2568 | } else { | |||
| 2569 | std::memmove(&Clusters[DstIndex++], &Clusters[SrcIndex], | |||
| 2570 | sizeof(Clusters[SrcIndex])); | |||
| 2571 | } | |||
| 2572 | } | |||
| 2573 | Clusters.resize(DstIndex); | |||
| 2574 | } | |||
| 2575 | ||||
| 2576 | void SelectionDAGBuilder::UpdateSplitBlock(MachineBasicBlock *First, | |||
| 2577 | MachineBasicBlock *Last) { | |||
| 2578 | // Update JTCases. | |||
| 2579 | for (unsigned i = 0, e = JTCases.size(); i != e; ++i) | |||
| 2580 | if (JTCases[i].first.HeaderBB == First) | |||
| 2581 | JTCases[i].first.HeaderBB = Last; | |||
| 2582 | ||||
| 2583 | // Update BitTestCases. | |||
| 2584 | for (unsigned i = 0, e = BitTestCases.size(); i != e; ++i) | |||
| 2585 | if (BitTestCases[i].Parent == First) | |||
| 2586 | BitTestCases[i].Parent = Last; | |||
| 2587 | } | |||
| 2588 | ||||
| 2589 | void SelectionDAGBuilder::visitIndirectBr(const IndirectBrInst &I) { | |||
| 2590 | MachineBasicBlock *IndirectBrMBB = FuncInfo.MBB; | |||
| 2591 | ||||
| 2592 | // Update machine-CFG edges with unique successors. | |||
| 2593 | SmallSet<BasicBlock*, 32> Done; | |||
| 2594 | for (unsigned i = 0, e = I.getNumSuccessors(); i != e; ++i) { | |||
| 2595 | BasicBlock *BB = I.getSuccessor(i); | |||
| 2596 | bool Inserted = Done.insert(BB).second; | |||
| 2597 | if (!Inserted) | |||
| 2598 | continue; | |||
| 2599 | ||||
| 2600 | MachineBasicBlock *Succ = FuncInfo.MBBMap[BB]; | |||
| 2601 | addSuccessorWithProb(IndirectBrMBB, Succ); | |||
| 2602 | } | |||
| 2603 | IndirectBrMBB->normalizeSuccProbs(); | |||
| 2604 | ||||
| 2605 | DAG.setRoot(DAG.getNode(ISD::BRIND, getCurSDLoc(), | |||
| 2606 | MVT::Other, getControlRoot(), | |||
| 2607 | getValue(I.getAddress()))); | |||
| 2608 | } | |||
| 2609 | ||||
| 2610 | void SelectionDAGBuilder::visitUnreachable(const UnreachableInst &I) { | |||
| 2611 | if (!DAG.getTarget().Options.TrapUnreachable) | |||
| 2612 | return; | |||
| 2613 | ||||
| 2614 | // We may be able to ignore unreachable behind a noreturn call. | |||
| 2615 | if (DAG.getTarget().Options.NoTrapAfterNoreturn) { | |||
| 2616 | const BasicBlock &BB = *I.getParent(); | |||
| 2617 | if (&I != &BB.front()) { | |||
| 2618 | BasicBlock::const_iterator PredI = | |||
| 2619 | std::prev(BasicBlock::const_iterator(&I)); | |||
| 2620 | if (const CallInst *Call = dyn_cast<CallInst>(&*PredI)) { | |||
| 2621 | if (Call->doesNotReturn()) | |||
| 2622 | return; | |||
| 2623 | } | |||
| 2624 | } | |||
| 2625 | } | |||
| 2626 | ||||
| 2627 | DAG.setRoot(DAG.getNode(ISD::TRAP, getCurSDLoc(), MVT::Other, DAG.getRoot())); | |||
| 2628 | } | |||
| 2629 | ||||
| 2630 | void SelectionDAGBuilder::visitFSub(const User &I) { | |||
| 2631 | // -0.0 - X --> fneg | |||
| 2632 | Type *Ty = I.getType(); | |||
| 2633 | if (isa<Constant>(I.getOperand(0)) && | |||
| 2634 | I.getOperand(0) == ConstantFP::getZeroValueForNegation(Ty)) { | |||
| 2635 | SDValue Op2 = getValue(I.getOperand(1)); | |||
| 2636 | setValue(&I, DAG.getNode(ISD::FNEG, getCurSDLoc(), | |||
| 2637 | Op2.getValueType(), Op2)); | |||
| 2638 | return; | |||
| 2639 | } | |||
| 2640 | ||||
| 2641 | visitBinary(I, ISD::FSUB); | |||
| 2642 | } | |||
| 2643 | ||||
| 2644 | /// Checks if the given instruction performs a vector reduction, in which case | |||
| 2645 | /// we have the freedom to alter the elements in the result as long as the | |||
| 2646 | /// reduction of them stays unchanged. | |||
| 2647 | static bool isVectorReductionOp(const User *I) { | |||
| 2648 | const Instruction *Inst = dyn_cast<Instruction>(I); | |||
| 2649 | if (!Inst || !Inst->getType()->isVectorTy()) | |||
| 2650 | return false; | |||
| 2651 | ||||
| 2652 | auto OpCode = Inst->getOpcode(); | |||
| 2653 | switch (OpCode) { | |||
| 2654 | case Instruction::Add: | |||
| 2655 | case Instruction::Mul: | |||
| 2656 | case Instruction::And: | |||
| 2657 | case Instruction::Or: | |||
| 2658 | case Instruction::Xor: | |||
| 2659 | break; | |||
| 2660 | case Instruction::FAdd: | |||
| 2661 | case Instruction::FMul: | |||
| 2662 | if (const FPMathOperator *FPOp = dyn_cast<const FPMathOperator>(Inst)) | |||
| 2663 | if (FPOp->getFastMathFlags().isFast()) | |||
| 2664 | break; | |||
| 2665 | LLVM_FALLTHROUGH[[clang::fallthrough]]; | |||
| 2666 | default: | |||
| 2667 | return false; | |||
| 2668 | } | |||
| 2669 | ||||
| 2670 | unsigned ElemNum = Inst->getType()->getVectorNumElements(); | |||
| 2671 | // Ensure the reduction size is a power of 2. | |||
| 2672 | if (!isPowerOf2_32(ElemNum)) | |||
| 2673 | return false; | |||
| 2674 | ||||
| 2675 | unsigned ElemNumToReduce = ElemNum; | |||
| 2676 | ||||
| 2677 | // Do DFS search on the def-use chain from the given instruction. We only | |||
| 2678 | // allow four kinds of operations during the search until we reach the | |||
| 2679 | // instruction that extracts the first element from the vector: | |||
| 2680 | // | |||
| 2681 | // 1. The reduction operation of the same opcode as the given instruction. | |||
| 2682 | // | |||
| 2683 | // 2. PHI node. | |||
| 2684 | // | |||
| 2685 | // 3. ShuffleVector instruction together with a reduction operation that | |||
| 2686 | // does a partial reduction. | |||
| 2687 | // | |||
| 2688 | // 4. ExtractElement that extracts the first element from the vector, and we | |||
| 2689 | // stop searching the def-use chain here. | |||
| 2690 | // | |||
| 2691 | // 3 & 4 above perform a reduction on all elements of the vector. We push defs | |||
| 2692 | // from 1-3 to the stack to continue the DFS. The given instruction is not | |||
| 2693 | // a reduction operation if we meet any other instructions other than those | |||
| 2694 | // listed above. | |||
| 2695 | ||||
| 2696 | SmallVector<const User *, 16> UsersToVisit{Inst}; | |||
| 2697 | SmallPtrSet<const User *, 16> Visited; | |||
| 2698 | bool ReduxExtracted = false; | |||
| 2699 | ||||
| 2700 | while (!UsersToVisit.empty()) { | |||
| 2701 | auto User = UsersToVisit.back(); | |||
| 2702 | UsersToVisit.pop_back(); | |||
| 2703 | if (!Visited.insert(User).second) | |||
| 2704 | continue; | |||
| 2705 | ||||
| 2706 | for (const auto &U : User->users()) { | |||
| 2707 | auto Inst = dyn_cast<Instruction>(U); | |||
| 2708 | if (!Inst) | |||
| 2709 | return false; | |||
| 2710 | ||||
| 2711 | if (Inst->getOpcode() == OpCode || isa<PHINode>(U)) { | |||
| 2712 | if (const FPMathOperator *FPOp = dyn_cast<const FPMathOperator>(Inst)) | |||
| 2713 | if (!isa<PHINode>(FPOp) && !FPOp->getFastMathFlags().isFast()) | |||
| 2714 | return false; | |||
| 2715 | UsersToVisit.push_back(U); | |||
| 2716 | } else if (const ShuffleVectorInst *ShufInst = | |||
| 2717 | dyn_cast<ShuffleVectorInst>(U)) { | |||
| 2718 | // Detect the following pattern: A ShuffleVector instruction together | |||
| 2719 | // with a reduction that do partial reduction on the first and second | |||
| 2720 | // ElemNumToReduce / 2 elements, and store the result in | |||
| 2721 | // ElemNumToReduce / 2 elements in another vector. | |||
| 2722 | ||||
| 2723 | unsigned ResultElements = ShufInst->getType()->getVectorNumElements(); | |||
| 2724 | if (ResultElements < ElemNum) | |||
| 2725 | return false; | |||
| 2726 | ||||
| 2727 | if (ElemNumToReduce == 1) | |||
| 2728 | return false; | |||
| 2729 | if (!isa<UndefValue>(U->getOperand(1))) | |||
| 2730 | return false; | |||
| 2731 | for (unsigned i = 0; i < ElemNumToReduce / 2; ++i) | |||
| 2732 | if (ShufInst->getMaskValue(i) != int(i + ElemNumToReduce / 2)) | |||
| 2733 | return false; | |||
| 2734 | for (unsigned i = ElemNumToReduce / 2; i < ElemNum; ++i) | |||
| 2735 | if (ShufInst->getMaskValue(i) != -1) | |||
| 2736 | return false; | |||
| 2737 | ||||
| 2738 | // There is only one user of this ShuffleVector instruction, which | |||
| 2739 | // must be a reduction operation. | |||
| 2740 | if (!U->hasOneUse()) | |||
| 2741 | return false; | |||
| 2742 | ||||
| 2743 | auto U2 = dyn_cast<Instruction>(*U->user_begin()); | |||
| 2744 | if (!U2 || U2->getOpcode() != OpCode) | |||
| 2745 | return false; | |||
| 2746 | ||||
| 2747 | // Check operands of the reduction operation. | |||
| 2748 | if ((U2->getOperand(0) == U->getOperand(0) && U2->getOperand(1) == U) || | |||
| 2749 | (U2->getOperand(1) == U->getOperand(0) && U2->getOperand(0) == U)) { | |||
| 2750 | UsersToVisit.push_back(U2); | |||
| 2751 | ElemNumToReduce /= 2; | |||
| 2752 | } else | |||
| 2753 | return false; | |||
| 2754 | } else if (isa<ExtractElementInst>(U)) { | |||
| 2755 | // At this moment we should have reduced all elements in the vector. | |||
| 2756 | if (ElemNumToReduce != 1) | |||
| 2757 | return false; | |||
| 2758 | ||||
| 2759 | const ConstantInt *Val = dyn_cast<ConstantInt>(U->getOperand(1)); | |||
| 2760 | if (!Val || !Val->isZero()) | |||
| 2761 | return false; | |||
| 2762 | ||||
| 2763 | ReduxExtracted = true; | |||
| 2764 | } else | |||
| 2765 | return false; | |||
| 2766 | } | |||
| 2767 | } | |||
| 2768 | return ReduxExtracted; | |||
| 2769 | } | |||
| 2770 | ||||
| 2771 | void SelectionDAGBuilder::visitBinary(const User &I, unsigned Opcode) { | |||
| 2772 | SDNodeFlags Flags; | |||
| 2773 | if (auto *OFBinOp = dyn_cast<OverflowingBinaryOperator>(&I)) { | |||
| 2774 | Flags.setNoSignedWrap(OFBinOp->hasNoSignedWrap()); | |||
| 2775 | Flags.setNoUnsignedWrap(OFBinOp->hasNoUnsignedWrap()); | |||
| 2776 | } | |||
| 2777 | if (auto *ExactOp = dyn_cast<PossiblyExactOperator>(&I)) { | |||
| 2778 | Flags.setExact(ExactOp->isExact()); | |||
| 2779 | } | |||
| 2780 | if (isVectorReductionOp(&I)) { | |||
| 2781 | Flags.setVectorReduction(true); | |||
| 2782 | LLVM_DEBUG(dbgs() << "Detected a reduction operation:" << I << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType ("isel")) { dbgs() << "Detected a reduction operation:" << I << "\n"; } } while (false); | |||
| 2783 | } | |||
| 2784 | ||||
| 2785 | SDValue Op1 = getValue(I.getOperand(0)); | |||
| 2786 | SDValue Op2 = getValue(I.getOperand(1)); | |||
| 2787 | SDValue BinNodeValue = DAG.getNode(Opcode, getCurSDLoc(), Op1.getValueType(), | |||
| 2788 | Op1, Op2, Flags); | |||
| 2789 | setValue(&I, BinNodeValue); | |||
| 2790 | } | |||
| 2791 | ||||
| 2792 | void SelectionDAGBuilder::visitShift(const User &I, unsigned Opcode) { | |||
| 2793 | SDValue Op1 = getValue(I.getOperand(0)); | |||
| 2794 | SDValue Op2 = getValue(I.getOperand(1)); | |||
| 2795 | ||||
| 2796 | EVT ShiftTy = DAG.getTargetLoweringInfo().getShiftAmountTy( | |||
| 2797 | Op2.getValueType(), DAG.getDataLayout()); | |||
| 2798 | ||||
| 2799 | // Coerce the shift amount to the right type if we can. | |||
| 2800 | if (!I.getType()->isVectorTy() && Op2.getValueType() != ShiftTy) { | |||
| 2801 | unsigned ShiftSize = ShiftTy.getSizeInBits(); | |||
| 2802 | unsigned Op2Size = Op2.getValueSizeInBits(); | |||
| 2803 | SDLoc DL = getCurSDLoc(); | |||
| 2804 | ||||
| 2805 | // If the operand is smaller than the shift count type, promote it. | |||
| 2806 | if (ShiftSize > Op2Size) | |||
| 2807 | Op2 = DAG.getNode(ISD::ZERO_EXTEND, DL, ShiftTy, Op2); | |||
| 2808 | ||||
| 2809 | // If the operand is larger than the shift count type but the shift | |||
| 2810 | // count type has enough bits to represent any shift value, truncate | |||
| 2811 | // it now. This is a common case and it exposes the truncate to | |||
| 2812 | // optimization early. | |||
| 2813 | else if (ShiftSize >= Log2_32_Ceil(Op2.getValueSizeInBits())) | |||
| 2814 | Op2 = DAG.getNode(ISD::TRUNCATE, DL, ShiftTy, Op2); | |||
| 2815 | // Otherwise we'll need to temporarily settle for some other convenient | |||
| 2816 | // type. Type legalization will make adjustments once the shiftee is split. | |||
| 2817 | else | |||
| 2818 | Op2 = DAG.getZExtOrTrunc(Op2, DL, MVT::i32); | |||
| 2819 | } | |||
| 2820 | ||||
| 2821 | bool nuw = false; | |||
| 2822 | bool nsw = false; | |||
| 2823 | bool exact = false; | |||
| 2824 | ||||
| 2825 | if (Opcode == ISD::SRL || Opcode == ISD::SRA || Opcode == ISD::SHL) { | |||
| 2826 | ||||
| 2827 | if (const OverflowingBinaryOperator *OFBinOp = | |||
| 2828 | dyn_cast<const OverflowingBinaryOperator>(&I)) { | |||
| 2829 | nuw = OFBinOp->hasNoUnsignedWrap(); | |||
| 2830 | nsw = OFBinOp->hasNoSignedWrap(); | |||
| 2831 | } | |||
| 2832 | if (const PossiblyExactOperator *ExactOp = | |||
| 2833 | dyn_cast<const PossiblyExactOperator>(&I)) | |||
| 2834 | exact = ExactOp->isExact(); | |||
| 2835 | } | |||
| 2836 | SDNodeFlags Flags; | |||
| 2837 | Flags.setExact(exact); | |||
| 2838 | Flags.setNoSignedWrap(nsw); | |||
| 2839 | Flags.setNoUnsignedWrap(nuw); | |||
| 2840 | SDValue Res = DAG.getNode(Opcode, getCurSDLoc(), Op1.getValueType(), Op1, Op2, | |||
| 2841 | Flags); | |||
| 2842 | setValue(&I, Res); | |||
| 2843 | } | |||
| 2844 | ||||
| 2845 | void SelectionDAGBuilder::visitSDiv(const User &I) { | |||
| 2846 | SDValue Op1 = getValue(I.getOperand(0)); | |||
| 2847 | SDValue Op2 = getValue(I.getOperand(1)); | |||
| 2848 | ||||
| 2849 | SDNodeFlags Flags; | |||
| 2850 | Flags.setExact(isa<PossiblyExactOperator>(&I) && | |||
| 2851 | cast<PossiblyExactOperator>(&I)->isExact()); | |||
| 2852 | setValue(&I, DAG.getNode(ISD::SDIV, getCurSDLoc(), Op1.getValueType(), Op1, | |||
| 2853 | Op2, Flags)); | |||
| 2854 | } | |||
| 2855 | ||||
| 2856 | void SelectionDAGBuilder::visitICmp(const User &I) { | |||
| 2857 | ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE; | |||
| 2858 | if (const ICmpInst *IC = dyn_cast<ICmpInst>(&I)) | |||
| 2859 | predicate = IC->getPredicate(); | |||
| 2860 | else if (const ConstantExpr *IC = dyn_cast<ConstantExpr>(&I)) | |||
| 2861 | predicate = ICmpInst::Predicate(IC->getPredicate()); | |||
| 2862 | SDValue Op1 = getValue(I.getOperand(0)); | |||
| 2863 | SDValue Op2 = getValue(I.getOperand(1)); | |||
| 2864 | ISD::CondCode Opcode = getICmpCondCode(predicate); | |||
| 2865 | ||||
| 2866 | EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(), | |||
| 2867 | I.getType()); | |||
| 2868 | setValue(&I, DAG.getSetCC(getCurSDLoc(), DestVT, Op1, Op2, Opcode)); | |||
| 2869 | } | |||
| 2870 | ||||
| 2871 | void SelectionDAGBuilder::visitFCmp(const User &I) { | |||
| 2872 | FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE; | |||
| 2873 | if (const FCmpInst *FC = dyn_cast<FCmpInst>(&I)) | |||
| 2874 | predicate = FC->getPredicate(); | |||
| 2875 | else if (const ConstantExpr *FC = dyn_cast<ConstantExpr>(&I)) | |||
| 2876 | predicate = FCmpInst::Predicate(FC->getPredicate()); | |||
| 2877 | SDValue Op1 = getValue(I.getOperand(0)); | |||
| 2878 | SDValue Op2 = getValue(I.getOperand(1)); | |||
| 2879 | ||||
| 2880 | ISD::CondCode Condition = getFCmpCondCode(predicate); | |||
| 2881 | auto *FPMO = dyn_cast<FPMathOperator>(&I); | |||
| 2882 | if ((FPMO && FPMO->hasNoNaNs()) || TM.Options.NoNaNsFPMath) | |||
| 2883 | Condition = getFCmpCodeWithoutNaN(Condition); | |||
| 2884 | ||||
| 2885 | EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(), | |||
| 2886 | I.getType()); | |||
| 2887 | setValue(&I, DAG.getSetCC(getCurSDLoc(), DestVT, Op1, Op2, Condition)); | |||
| 2888 | } | |||
| 2889 | ||||
| 2890 | // Check if the condition of the select has one use or two users that are both | |||
| 2891 | // selects with the same condition. | |||
| 2892 | static bool hasOnlySelectUsers(const Value *Cond) { | |||
| 2893 | return llvm::all_of(Cond->users(), [](const Value *V) { | |||
| 2894 | return isa<SelectInst>(V); | |||
| 2895 | }); | |||
| 2896 | } | |||
| 2897 | ||||
| 2898 | void SelectionDAGBuilder::visitSelect(const User &I) { | |||
| 2899 | SmallVector<EVT, 4> ValueVTs; | |||
| 2900 | ComputeValueVTs(DAG.getTargetLoweringInfo(), DAG.getDataLayout(), I.getType(), | |||
| 2901 | ValueVTs); | |||
| 2902 | unsigned NumValues = ValueVTs.size(); | |||
| 2903 | if (NumValues == 0) return; | |||
| 2904 | ||||
| 2905 | SmallVector<SDValue, 4> Values(NumValues); | |||
| 2906 | SDValue Cond = getValue(I.getOperand(0)); | |||
| 2907 | SDValue LHSVal = getValue(I.getOperand(1)); | |||
| 2908 | SDValue RHSVal = getValue(I.getOperand(2)); | |||
| 2909 | auto BaseOps = {Cond}; | |||
| 2910 | ISD::NodeType OpCode = Cond.getValueType().isVector() ? | |||
| 2911 | ISD::VSELECT : ISD::SELECT; | |||
| 2912 | ||||
| 2913 | // Min/max matching is only viable if all output VTs are the same. | |||
| 2914 | if (std::equal(ValueVTs.begin(), ValueVTs.end(), ValueVTs.begin())) { | |||
| 2915 | EVT VT = ValueVTs[0]; | |||
| 2916 | LLVMContext &Ctx = *DAG.getContext(); | |||
| 2917 | auto &TLI = DAG.getTargetLoweringInfo(); | |||
| 2918 | ||||
| 2919 | // We care about the legality of the operation after it has been type | |||
| 2920 | // legalized. | |||
| 2921 | while (TLI.getTypeAction(Ctx, VT) != TargetLoweringBase::TypeLegal && | |||
| 2922 | VT != TLI.getTypeToTransformTo(Ctx, VT)) | |||
| 2923 | VT = TLI.getTypeToTransformTo(Ctx, VT); | |||
| 2924 | ||||
| 2925 | // If the vselect is legal, assume we want to leave this as a vector setcc + | |||
| 2926 | // vselect. Otherwise, if this is going to be scalarized, we want to see if | |||
| 2927 | // min/max is legal on the scalar type. | |||
| 2928 | bool UseScalarMinMax = VT.isVector() && | |||
| 2929 | !TLI.isOperationLegalOrCustom(ISD::VSELECT, VT); | |||
| 2930 | ||||
| 2931 | Value *LHS, *RHS; | |||
| 2932 | auto SPR = matchSelectPattern(const_cast<User*>(&I), LHS, RHS); | |||
| 2933 | ISD::NodeType Opc = ISD::DELETED_NODE; | |||
| 2934 | switch (SPR.Flavor) { | |||
| 2935 | case SPF_UMAX: Opc = ISD::UMAX; break; | |||
| 2936 | case SPF_UMIN: Opc = ISD::UMIN; break; | |||
| 2937 | case SPF_SMAX: Opc = ISD::SMAX; break; | |||
| 2938 | case SPF_SMIN: Opc = ISD::SMIN; break; | |||
| 2939 | case SPF_FMINNUM: | |||
| 2940 | switch (SPR.NaNBehavior) { | |||
| 2941 | case SPNB_NA: llvm_unreachable("No NaN behavior for FP op?")::llvm::llvm_unreachable_internal("No NaN behavior for FP op?" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 2941); | |||
| 2942 | case SPNB_RETURNS_NAN: Opc = ISD::FMINNAN; break; | |||
| 2943 | case SPNB_RETURNS_OTHER: Opc = ISD::FMINNUM; break; | |||
| 2944 | case SPNB_RETURNS_ANY: { | |||
| 2945 | if (TLI.isOperationLegalOrCustom(ISD::FMINNUM, VT)) | |||
| 2946 | Opc = ISD::FMINNUM; | |||
| 2947 | else if (TLI.isOperationLegalOrCustom(ISD::FMINNAN, VT)) | |||
| 2948 | Opc = ISD::FMINNAN; | |||
| 2949 | else if (UseScalarMinMax) | |||
| 2950 | Opc = TLI.isOperationLegalOrCustom(ISD::FMINNUM, VT.getScalarType()) ? | |||
| 2951 | ISD::FMINNUM : ISD::FMINNAN; | |||
| 2952 | break; | |||
| 2953 | } | |||
| 2954 | } | |||
| 2955 | break; | |||
| 2956 | case SPF_FMAXNUM: | |||
| 2957 | switch (SPR.NaNBehavior) { | |||
| 2958 | case SPNB_NA: llvm_unreachable("No NaN behavior for FP op?")::llvm::llvm_unreachable_internal("No NaN behavior for FP op?" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 2958); | |||
| 2959 | case SPNB_RETURNS_NAN: Opc = ISD::FMAXNAN; break; | |||
| 2960 | case SPNB_RETURNS_OTHER: Opc = ISD::FMAXNUM; break; | |||
| 2961 | case SPNB_RETURNS_ANY: | |||
| 2962 | ||||
| 2963 | if (TLI.isOperationLegalOrCustom(ISD::FMAXNUM, VT)) | |||
| 2964 | Opc = ISD::FMAXNUM; | |||
| 2965 | else if (TLI.isOperationLegalOrCustom(ISD::FMAXNAN, VT)) | |||
| 2966 | Opc = ISD::FMAXNAN; | |||
| 2967 | else if (UseScalarMinMax) | |||
| 2968 | Opc = TLI.isOperationLegalOrCustom(ISD::FMAXNUM, VT.getScalarType()) ? | |||
| 2969 | ISD::FMAXNUM : ISD::FMAXNAN; | |||
| 2970 | break; | |||
| 2971 | } | |||
| 2972 | break; | |||
| 2973 | default: break; | |||
| 2974 | } | |||
| 2975 | ||||
| 2976 | if (Opc != ISD::DELETED_NODE && | |||
| 2977 | (TLI.isOperationLegalOrCustom(Opc, VT) || | |||
| 2978 | (UseScalarMinMax && | |||
| 2979 | TLI.isOperationLegalOrCustom(Opc, VT.getScalarType()))) && | |||
| 2980 | // If the underlying comparison instruction is used by any other | |||
| 2981 | // instruction, the consumed instructions won't be destroyed, so it is | |||
| 2982 | // not profitable to convert to a min/max. | |||
| 2983 | hasOnlySelectUsers(cast<SelectInst>(I).getCondition())) { | |||
| 2984 | OpCode = Opc; | |||
| 2985 | LHSVal = getValue(LHS); | |||
| 2986 | RHSVal = getValue(RHS); | |||
| 2987 | BaseOps = {}; | |||
| 2988 | } | |||
| 2989 | } | |||
| 2990 | ||||
| 2991 | for (unsigned i = 0; i != NumValues; ++i) { | |||
| 2992 | SmallVector<SDValue, 3> Ops(BaseOps.begin(), BaseOps.end()); | |||
| 2993 | Ops.push_back(SDValue(LHSVal.getNode(), LHSVal.getResNo() + i)); | |||
| 2994 | Ops.push_back(SDValue(RHSVal.getNode(), RHSVal.getResNo() + i)); | |||
| 2995 | Values[i] = DAG.getNode(OpCode, getCurSDLoc(), | |||
| 2996 | LHSVal.getNode()->getValueType(LHSVal.getResNo()+i), | |||
| 2997 | Ops); | |||
| 2998 | } | |||
| 2999 | ||||
| 3000 | setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(), | |||
| 3001 | DAG.getVTList(ValueVTs), Values)); | |||
| 3002 | } | |||
| 3003 | ||||
| 3004 | void SelectionDAGBuilder::visitTrunc(const User &I) { | |||
| 3005 | // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest). | |||
| 3006 | SDValue N = getValue(I.getOperand(0)); | |||
| 3007 | EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(), | |||
| 3008 | I.getType()); | |||
| 3009 | setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), DestVT, N)); | |||
| 3010 | } | |||
| 3011 | ||||
| 3012 | void SelectionDAGBuilder::visitZExt(const User &I) { | |||
| 3013 | // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest). | |||
| 3014 | // ZExt also can't be a cast to bool for same reason. So, nothing much to do | |||
| 3015 | SDValue N = getValue(I.getOperand(0)); | |||
| 3016 | EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(), | |||
| 3017 | I.getType()); | |||
| 3018 | setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurSDLoc(), DestVT, N)); | |||
| 3019 | } | |||
| 3020 | ||||
| 3021 | void SelectionDAGBuilder::visitSExt(const User &I) { | |||
| 3022 | // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest). | |||
| 3023 | // SExt also can't be a cast to bool for same reason. So, nothing much to do | |||
| 3024 | SDValue N = getValue(I.getOperand(0)); | |||
| 3025 | EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(), | |||
| 3026 | I.getType()); | |||
| 3027 | setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurSDLoc(), DestVT, N)); | |||
| 3028 | } | |||
| 3029 | ||||
| 3030 | void SelectionDAGBuilder::visitFPTrunc(const User &I) { | |||
| 3031 | // FPTrunc is never a no-op cast, no need to check | |||
| 3032 | SDValue N = getValue(I.getOperand(0)); | |||
| 3033 | SDLoc dl = getCurSDLoc(); | |||
| 3034 | const TargetLowering &TLI = DAG.getTargetLoweringInfo(); | |||
| 3035 | EVT DestVT = TLI.getValueType(DAG.getDataLayout(), I.getType()); | |||
| 3036 | setValue(&I, DAG.getNode(ISD::FP_ROUND, dl, DestVT, N, | |||
| 3037 | DAG.getTargetConstant( | |||
| 3038 | 0, dl, TLI.getPointerTy(DAG.getDataLayout())))); | |||
| 3039 | } | |||
| 3040 | ||||
| 3041 | void SelectionDAGBuilder::visitFPExt(const User &I) { | |||
| 3042 | // FPExt is never a no-op cast, no need to check | |||
| 3043 | SDValue N = getValue(I.getOperand(0)); | |||
| 3044 | EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(), | |||
| 3045 | I.getType()); | |||
| 3046 | setValue(&I, DAG.getNode(ISD::FP_EXTEND, getCurSDLoc(), DestVT, N)); | |||
| 3047 | } | |||
| 3048 | ||||
| 3049 | void SelectionDAGBuilder::visitFPToUI(const User &I) { | |||
| 3050 | // FPToUI is never a no-op cast, no need to check | |||
| 3051 | SDValue N = getValue(I.getOperand(0)); | |||
| 3052 | EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(), | |||
| 3053 | I.getType()); | |||
| 3054 | setValue(&I, DAG.getNode(ISD::FP_TO_UINT, getCurSDLoc(), DestVT, N)); | |||
| 3055 | } | |||
| 3056 | ||||
| 3057 | void SelectionDAGBuilder::visitFPToSI(const User &I) { | |||
| 3058 | // FPToSI is never a no-op cast, no need to check | |||
| 3059 | SDValue N = getValue(I.getOperand(0)); | |||
| 3060 | EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(), | |||
| 3061 | I.getType()); | |||
| 3062 | setValue(&I, DAG.getNode(ISD::FP_TO_SINT, getCurSDLoc(), DestVT, N)); | |||
| 3063 | } | |||
| 3064 | ||||
| 3065 | void SelectionDAGBuilder::visitUIToFP(const User &I) { | |||
| 3066 | // UIToFP is never a no-op cast, no need to check | |||
| 3067 | SDValue N = getValue(I.getOperand(0)); | |||
| 3068 | EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(), | |||
| 3069 | I.getType()); | |||
| 3070 | setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurSDLoc(), DestVT, N)); | |||
| 3071 | } | |||
| 3072 | ||||
| 3073 | void SelectionDAGBuilder::visitSIToFP(const User &I) { | |||
| 3074 | // SIToFP is never a no-op cast, no need to check | |||
| 3075 | SDValue N = getValue(I.getOperand(0)); | |||
| 3076 | EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(), | |||
| 3077 | I.getType()); | |||
| 3078 | setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurSDLoc(), DestVT, N)); | |||
| 3079 | } | |||
| 3080 | ||||
| 3081 | void SelectionDAGBuilder::visitPtrToInt(const User &I) { | |||
| 3082 | // What to do depends on the size of the integer and the size of the pointer. | |||
| 3083 | // We can either truncate, zero extend, or no-op, accordingly. | |||
| 3084 | SDValue N = getValue(I.getOperand(0)); | |||
| 3085 | EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(), | |||
| 3086 | I.getType()); | |||
| 3087 | setValue(&I, DAG.getZExtOrTrunc(N, getCurSDLoc(), DestVT)); | |||
| 3088 | } | |||
| 3089 | ||||
| 3090 | void SelectionDAGBuilder::visitIntToPtr(const User &I) { | |||
| 3091 | // What to do depends on the size of the integer and the size of the pointer. | |||
| 3092 | // We can either truncate, zero extend, or no-op, accordingly. | |||
| 3093 | SDValue N = getValue(I.getOperand(0)); | |||
| 3094 | EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(), | |||
| 3095 | I.getType()); | |||
| 3096 | setValue(&I, DAG.getZExtOrTrunc(N, getCurSDLoc(), DestVT)); | |||
| 3097 | } | |||
| 3098 | ||||
| 3099 | void SelectionDAGBuilder::visitBitCast(const User &I) { | |||
| 3100 | SDValue N = getValue(I.getOperand(0)); | |||
| 3101 | SDLoc dl = getCurSDLoc(); | |||
| 3102 | EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(), | |||
| 3103 | I.getType()); | |||
| 3104 | ||||
| 3105 | // BitCast assures us that source and destination are the same size so this is | |||
| 3106 | // either a BITCAST or a no-op. | |||
| 3107 | if (DestVT != N.getValueType()) | |||
| 3108 | setValue(&I, DAG.getNode(ISD::BITCAST, dl, | |||
| 3109 | DestVT, N)); // convert types. | |||
| 3110 | // Check if the original LLVM IR Operand was a ConstantInt, because getValue() | |||
| 3111 | // might fold any kind of constant expression to an integer constant and that | |||
| 3112 | // is not what we are looking for. Only recognize a bitcast of a genuine | |||
| 3113 | // constant integer as an opaque constant. | |||
| 3114 | else if(ConstantInt *C = dyn_cast<ConstantInt>(I.getOperand(0))) | |||
| 3115 | setValue(&I, DAG.getConstant(C->getValue(), dl, DestVT, /*isTarget=*/false, | |||
| 3116 | /*isOpaque*/true)); | |||
| 3117 | else | |||
| 3118 | setValue(&I, N); // noop cast. | |||
| 3119 | } | |||
| 3120 | ||||
| 3121 | void SelectionDAGBuilder::visitAddrSpaceCast(const User &I) { | |||
| 3122 | const TargetLowering &TLI = DAG.getTargetLoweringInfo(); | |||
| 3123 | const Value *SV = I.getOperand(0); | |||
| 3124 | SDValue N = getValue(SV); | |||
| 3125 | EVT DestVT = TLI.getValueType(DAG.getDataLayout(), I.getType()); | |||
| 3126 | ||||
| 3127 | unsigned SrcAS = SV->getType()->getPointerAddressSpace(); | |||
| 3128 | unsigned DestAS = I.getType()->getPointerAddressSpace(); | |||
| 3129 | ||||
| 3130 | if (!TLI.isNoopAddrSpaceCast(SrcAS, DestAS)) | |||
| 3131 | N = DAG.getAddrSpaceCast(getCurSDLoc(), DestVT, N, SrcAS, DestAS); | |||
| 3132 | ||||
| 3133 | setValue(&I, N); | |||
| 3134 | } | |||
| 3135 | ||||
| 3136 | void SelectionDAGBuilder::visitInsertElement(const User &I) { | |||
| 3137 | const TargetLowering &TLI = DAG.getTargetLoweringInfo(); | |||
| 3138 | SDValue InVec = getValue(I.getOperand(0)); | |||
| 3139 | SDValue InVal = getValue(I.getOperand(1)); | |||
| 3140 | SDValue InIdx = DAG.getSExtOrTrunc(getValue(I.getOperand(2)), getCurSDLoc(), | |||
| 3141 | TLI.getVectorIdxTy(DAG.getDataLayout())); | |||
| 3142 | setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, getCurSDLoc(), | |||
| 3143 | TLI.getValueType(DAG.getDataLayout(), I.getType()), | |||
| 3144 | InVec, InVal, InIdx)); | |||
| 3145 | } | |||
| 3146 | ||||
| 3147 | void SelectionDAGBuilder::visitExtractElement(const User &I) { | |||
| 3148 | const TargetLowering &TLI = DAG.getTargetLoweringInfo(); | |||
| 3149 | SDValue InVec = getValue(I.getOperand(0)); | |||
| 3150 | SDValue InIdx = DAG.getSExtOrTrunc(getValue(I.getOperand(1)), getCurSDLoc(), | |||
| 3151 | TLI.getVectorIdxTy(DAG.getDataLayout())); | |||
| 3152 | setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurSDLoc(), | |||
| 3153 | TLI.getValueType(DAG.getDataLayout(), I.getType()), | |||
| 3154 | InVec, InIdx)); | |||
| 3155 | } | |||
| 3156 | ||||
| 3157 | void SelectionDAGBuilder::visitShuffleVector(const User &I) { | |||
| 3158 | SDValue Src1 = getValue(I.getOperand(0)); | |||
| 3159 | SDValue Src2 = getValue(I.getOperand(1)); | |||
| 3160 | SDLoc DL = getCurSDLoc(); | |||
| 3161 | ||||
| 3162 | SmallVector<int, 8> Mask; | |||
| 3163 | ShuffleVectorInst::getShuffleMask(cast<Constant>(I.getOperand(2)), Mask); | |||
| 3164 | unsigned MaskNumElts = Mask.size(); | |||
| 3165 | ||||
| 3166 | const TargetLowering &TLI = DAG.getTargetLoweringInfo(); | |||
| 3167 | EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType()); | |||
| 3168 | EVT SrcVT = Src1.getValueType(); | |||
| 3169 | unsigned SrcNumElts = SrcVT.getVectorNumElements(); | |||
| 3170 | ||||
| 3171 | if (SrcNumElts == MaskNumElts) { | |||
| 3172 | setValue(&I, DAG.getVectorShuffle(VT, DL, Src1, Src2, Mask)); | |||
| 3173 | return; | |||
| 3174 | } | |||
| 3175 | ||||
| 3176 | // Normalize the shuffle vector since mask and vector length don't match. | |||
| 3177 | if (SrcNumElts < MaskNumElts) { | |||
| 3178 | // Mask is longer than the source vectors. We can use concatenate vector to | |||
| 3179 | // make the mask and vectors lengths match. | |||
| 3180 | ||||
| 3181 | if (MaskNumElts % SrcNumElts == 0) { | |||
| 3182 | // Mask length is a multiple of the source vector length. | |||
| 3183 | // Check if the shuffle is some kind of concatenation of the input | |||
| 3184 | // vectors. | |||
| 3185 | unsigned NumConcat = MaskNumElts / SrcNumElts; | |||
| 3186 | bool IsConcat = true; | |||
| 3187 | SmallVector<int, 8> ConcatSrcs(NumConcat, -1); | |||
| 3188 | for (unsigned i = 0; i != MaskNumElts; ++i) { | |||
| 3189 | int Idx = Mask[i]; | |||
| 3190 | if (Idx < 0) | |||
| 3191 | continue; | |||
| 3192 | // Ensure the indices in each SrcVT sized piece are sequential and that | |||
| 3193 | // the same source is used for the whole piece. | |||
| 3194 | if ((Idx % SrcNumElts != (i % SrcNumElts)) || | |||
| 3195 | (ConcatSrcs[i / SrcNumElts] >= 0 && | |||
| 3196 | ConcatSrcs[i / SrcNumElts] != (int)(Idx / SrcNumElts))) { | |||
| 3197 | IsConcat = false; | |||
| 3198 | break; | |||
| 3199 | } | |||
| 3200 | // Remember which source this index came from. | |||
| 3201 | ConcatSrcs[i / SrcNumElts] = Idx / SrcNumElts; | |||
| 3202 | } | |||
| 3203 | ||||
| 3204 | // The shuffle is concatenating multiple vectors together. Just emit | |||
| 3205 | // a CONCAT_VECTORS operation. | |||
| 3206 | if (IsConcat) { | |||
| 3207 | SmallVector<SDValue, 8> ConcatOps; | |||
| 3208 | for (auto Src : ConcatSrcs) { | |||
| 3209 | if (Src < 0) | |||
| 3210 | ConcatOps.push_back(DAG.getUNDEF(SrcVT)); | |||
| 3211 | else if (Src == 0) | |||
| 3212 | ConcatOps.push_back(Src1); | |||
| 3213 | else | |||
| 3214 | ConcatOps.push_back(Src2); | |||
| 3215 | } | |||
| 3216 | setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, ConcatOps)); | |||
| 3217 | return; | |||
| 3218 | } | |||
| 3219 | } | |||
| 3220 | ||||
| 3221 | unsigned PaddedMaskNumElts = alignTo(MaskNumElts, SrcNumElts); | |||
| 3222 | unsigned NumConcat = PaddedMaskNumElts / SrcNumElts; | |||
| 3223 | EVT PaddedVT = EVT::getVectorVT(*DAG.getContext(), VT.getScalarType(), | |||
| 3224 | PaddedMaskNumElts); | |||
| 3225 | ||||
| 3226 | // Pad both vectors with undefs to make them the same length as the mask. | |||
| 3227 | SDValue UndefVal = DAG.getUNDEF(SrcVT); | |||
| 3228 | ||||
| 3229 | SmallVector<SDValue, 8> MOps1(NumConcat, UndefVal); | |||
| 3230 | SmallVector<SDValue, 8> MOps2(NumConcat, UndefVal); | |||
| 3231 | MOps1[0] = Src1; | |||
| 3232 | MOps2[0] = Src2; | |||
| 3233 | ||||
| 3234 | Src1 = Src1.isUndef() | |||
| 3235 | ? DAG.getUNDEF(PaddedVT) | |||
| 3236 | : DAG.getNode(ISD::CONCAT_VECTORS, DL, PaddedVT, MOps1); | |||
| 3237 | Src2 = Src2.isUndef() | |||
| 3238 | ? DAG.getUNDEF(PaddedVT) | |||
| 3239 | : DAG.getNode(ISD::CONCAT_VECTORS, DL, PaddedVT, MOps2); | |||
| 3240 | ||||
| 3241 | // Readjust mask for new input vector length. | |||
| 3242 | SmallVector<int, 8> MappedOps(PaddedMaskNumElts, -1); | |||
| 3243 | for (unsigned i = 0; i != MaskNumElts; ++i) { | |||
| 3244 | int Idx = Mask[i]; | |||
| 3245 | if (Idx >= (int)SrcNumElts) | |||
| 3246 | Idx -= SrcNumElts - PaddedMaskNumElts; | |||
| 3247 | MappedOps[i] = Idx; | |||
| 3248 | } | |||
| 3249 | ||||
| 3250 | SDValue Result = DAG.getVectorShuffle(PaddedVT, DL, Src1, Src2, MappedOps); | |||
| 3251 | ||||
| 3252 | // If the concatenated vector was padded, extract a subvector with the | |||
| 3253 | // correct number of elements. | |||
| 3254 | if (MaskNumElts != PaddedMaskNumElts) | |||
| 3255 | Result = DAG.getNode( | |||
| 3256 | ISD::EXTRACT_SUBVECTOR, DL, VT, Result, | |||
| 3257 | DAG.getConstant(0, DL, TLI.getVectorIdxTy(DAG.getDataLayout()))); | |||
| 3258 | ||||
| 3259 | setValue(&I, Result); | |||
| 3260 | return; | |||
| 3261 | } | |||
| 3262 | ||||
| 3263 | if (SrcNumElts > MaskNumElts) { | |||
| 3264 | // Analyze the access pattern of the vector to see if we can extract | |||
| 3265 | // two subvectors and do the shuffle. | |||
| 3266 | int StartIdx[2] = { -1, -1 }; // StartIdx to extract from | |||
| 3267 | bool CanExtract = true; | |||
| 3268 | for (int Idx : Mask) { | |||
| 3269 | unsigned Input = 0; | |||
| 3270 | if (Idx < 0) | |||
| 3271 | continue; | |||
| 3272 | ||||
| 3273 | if (Idx >= (int)SrcNumElts) { | |||
| 3274 | Input = 1; | |||
| 3275 | Idx -= SrcNumElts; | |||
| 3276 | } | |||
| 3277 | ||||
| 3278 | // If all the indices come from the same MaskNumElts sized portion of | |||
| 3279 | // the sources we can use extract. Also make sure the extract wouldn't | |||
| 3280 | // extract past the end of the source. | |||
| 3281 | int NewStartIdx = alignDown(Idx, MaskNumElts); | |||
| 3282 | if (NewStartIdx + MaskNumElts > SrcNumElts || | |||
| 3283 | (StartIdx[Input] >= 0 && StartIdx[Input] != NewStartIdx)) | |||
| 3284 | CanExtract = false; | |||
| 3285 | // Make sure we always update StartIdx as we use it to track if all | |||
| 3286 | // elements are undef. | |||
| 3287 | StartIdx[Input] = NewStartIdx; | |||
| 3288 | } | |||
| 3289 | ||||
| 3290 | if (StartIdx[0] < 0 && StartIdx[1] < 0) { | |||
| 3291 | setValue(&I, DAG.getUNDEF(VT)); // Vectors are not used. | |||
| 3292 | return; | |||
| 3293 | } | |||
| 3294 | if (CanExtract) { | |||
| 3295 | // Extract appropriate subvector and generate a vector shuffle | |||
| 3296 | for (unsigned Input = 0; Input < 2; ++Input) { | |||
| 3297 | SDValue &Src = Input == 0 ? Src1 : Src2; | |||
| 3298 | if (StartIdx[Input] < 0) | |||
| 3299 | Src = DAG.getUNDEF(VT); | |||
| 3300 | else { | |||
| 3301 | Src = DAG.getNode( | |||
| 3302 | ISD::EXTRACT_SUBVECTOR, DL, VT, Src, | |||
| 3303 | DAG.getConstant(StartIdx[Input], DL, | |||
| 3304 | TLI.getVectorIdxTy(DAG.getDataLayout()))); | |||
| 3305 | } | |||
| 3306 | } | |||
| 3307 | ||||
| 3308 | // Calculate new mask. | |||
| 3309 | SmallVector<int, 8> MappedOps(Mask.begin(), Mask.end()); | |||
| 3310 | for (int &Idx : MappedOps) { | |||
| 3311 | if (Idx >= (int)SrcNumElts) | |||
| 3312 | Idx -= SrcNumElts + StartIdx[1] - MaskNumElts; | |||
| 3313 | else if (Idx >= 0) | |||
| 3314 | Idx -= StartIdx[0]; | |||
| 3315 | } | |||
| 3316 | ||||
| 3317 | setValue(&I, DAG.getVectorShuffle(VT, DL, Src1, Src2, MappedOps)); | |||
| 3318 | return; | |||
| 3319 | } | |||
| 3320 | } | |||
| 3321 | ||||
| 3322 | // We can't use either concat vectors or extract subvectors so fall back to | |||
| 3323 | // replacing the shuffle with extract and build vector. | |||
| 3324 | // to insert and build vector. | |||
| 3325 | EVT EltVT = VT.getVectorElementType(); | |||
| 3326 | EVT IdxVT = TLI.getVectorIdxTy(DAG.getDataLayout()); | |||
| 3327 | SmallVector<SDValue,8> Ops; | |||
| 3328 | for (int Idx : Mask) { | |||
| 3329 | SDValue Res; | |||
| 3330 | ||||
| 3331 | if (Idx < 0) { | |||
| 3332 | Res = DAG.getUNDEF(EltVT); | |||
| 3333 | } else { | |||
| 3334 | SDValue &Src = Idx < (int)SrcNumElts ? Src1 : Src2; | |||
| 3335 | if (Idx >= (int)SrcNumElts) Idx -= SrcNumElts; | |||
| 3336 | ||||
| 3337 | Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, | |||
| 3338 | EltVT, Src, DAG.getConstant(Idx, DL, IdxVT)); | |||
| 3339 | } | |||
| 3340 | ||||
| 3341 | Ops.push_back(Res); | |||
| 3342 | } | |||
| 3343 | ||||
| 3344 | setValue(&I, DAG.getBuildVector(VT, DL, Ops)); | |||
| 3345 | } | |||
| 3346 | ||||
| 3347 | void SelectionDAGBuilder::visitInsertValue(const User &I) { | |||
| 3348 | ArrayRef<unsigned> Indices; | |||
| 3349 | if (const InsertValueInst *IV = dyn_cast<InsertValueInst>(&I)) | |||
| 3350 | Indices = IV->getIndices(); | |||
| 3351 | else | |||
| 3352 | Indices = cast<ConstantExpr>(&I)->getIndices(); | |||
| 3353 | ||||
| 3354 | const Value *Op0 = I.getOperand(0); | |||
| 3355 | const Value *Op1 = I.getOperand(1); | |||
| 3356 | Type *AggTy = I.getType(); | |||
| 3357 | Type *ValTy = Op1->getType(); | |||
| 3358 | bool IntoUndef = isa<UndefValue>(Op0); | |||
| 3359 | bool FromUndef = isa<UndefValue>(Op1); | |||
| 3360 | ||||
| 3361 | unsigned LinearIndex = ComputeLinearIndex(AggTy, Indices); | |||
| 3362 | ||||
| 3363 | const TargetLowering &TLI = DAG.getTargetLoweringInfo(); | |||
| 3364 | SmallVector<EVT, 4> AggValueVTs; | |||
| 3365 | ComputeValueVTs(TLI, DAG.getDataLayout(), AggTy, AggValueVTs); | |||
| 3366 | SmallVector<EVT, 4> ValValueVTs; | |||
| 3367 | ComputeValueVTs(TLI, DAG.getDataLayout(), ValTy, ValValueVTs); | |||
| 3368 | ||||
| 3369 | unsigned NumAggValues = AggValueVTs.size(); | |||
| 3370 | unsigned NumValValues = ValValueVTs.size(); | |||
| 3371 | SmallVector<SDValue, 4> Values(NumAggValues); | |||
| 3372 | ||||
| 3373 | // Ignore an insertvalue that produces an empty object | |||
| 3374 | if (!NumAggValues) { | |||
| 3375 | setValue(&I, DAG.getUNDEF(MVT(MVT::Other))); | |||
| 3376 | return; | |||
| 3377 | } | |||
| 3378 | ||||
| 3379 | SDValue Agg = getValue(Op0); | |||
| 3380 | unsigned i = 0; | |||
| 3381 | // Copy the beginning value(s) from the original aggregate. | |||
| 3382 | for (; i != LinearIndex; ++i) | |||
| 3383 | Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) : | |||
| 3384 | SDValue(Agg.getNode(), Agg.getResNo() + i); | |||
| 3385 | // Copy values from the inserted value(s). | |||
| 3386 | if (NumValValues) { | |||
| 3387 | SDValue Val = getValue(Op1); | |||
| 3388 | for (; i != LinearIndex + NumValValues; ++i) | |||
| 3389 | Values[i] = FromUndef ? DAG.getUNDEF(AggValueVTs[i]) : | |||
| 3390 | SDValue(Val.getNode(), Val.getResNo() + i - LinearIndex); | |||
| 3391 | } | |||
| 3392 | // Copy remaining value(s) from the original aggregate. | |||
| 3393 | for (; i != NumAggValues; ++i) | |||
| 3394 | Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) : | |||
| 3395 | SDValue(Agg.getNode(), Agg.getResNo() + i); | |||
| 3396 | ||||
| 3397 | setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(), | |||
| 3398 | DAG.getVTList(AggValueVTs), Values)); | |||
| 3399 | } | |||
| 3400 | ||||
| 3401 | void SelectionDAGBuilder::visitExtractValue(const User &I) { | |||
| 3402 | ArrayRef<unsigned> Indices; | |||
| 3403 | if (const ExtractValueInst *EV = dyn_cast<ExtractValueInst>(&I)) | |||
| 3404 | Indices = EV->getIndices(); | |||
| 3405 | else | |||
| 3406 | Indices = cast<ConstantExpr>(&I)->getIndices(); | |||
| 3407 | ||||
| 3408 | const Value *Op0 = I.getOperand(0); | |||
| 3409 | Type *AggTy = Op0->getType(); | |||
| 3410 | Type *ValTy = I.getType(); | |||
| 3411 | bool OutOfUndef = isa<UndefValue>(Op0); | |||
| 3412 | ||||
| 3413 | unsigned LinearIndex = ComputeLinearIndex(AggTy, Indices); | |||
| 3414 | ||||
| 3415 | const TargetLowering &TLI = DAG.getTargetLoweringInfo(); | |||
| 3416 | SmallVector<EVT, 4> ValValueVTs; | |||
| 3417 | ComputeValueVTs(TLI, DAG.getDataLayout(), ValTy, ValValueVTs); | |||
| 3418 | ||||
| 3419 | unsigned NumValValues = ValValueVTs.size(); | |||
| 3420 | ||||
| 3421 | // Ignore a extractvalue that produces an empty object | |||
| 3422 | if (!NumValValues) { | |||
| 3423 | setValue(&I, DAG.getUNDEF(MVT(MVT::Other))); | |||
| 3424 | return; | |||
| 3425 | } | |||
| 3426 | ||||
| 3427 | SmallVector<SDValue, 4> Values(NumValValues); | |||
| 3428 | ||||
| 3429 | SDValue Agg = getValue(Op0); | |||
| 3430 | // Copy out the selected value(s). | |||
| 3431 | for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i) | |||
| 3432 | Values[i - LinearIndex] = | |||
| 3433 | OutOfUndef ? | |||
| 3434 | DAG.getUNDEF(Agg.getNode()->getValueType(Agg.getResNo() + i)) : | |||
| 3435 | SDValue(Agg.getNode(), Agg.getResNo() + i); | |||
| 3436 | ||||
| 3437 | setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(), | |||
| 3438 | DAG.getVTList(ValValueVTs), Values)); | |||
| 3439 | } | |||
| 3440 | ||||
| 3441 | void SelectionDAGBuilder::visitGetElementPtr(const User &I) { | |||
| 3442 | Value *Op0 = I.getOperand(0); | |||
| 3443 | // Note that the pointer operand may be a vector of pointers. Take the scalar | |||
| 3444 | // element which holds a pointer. | |||
| 3445 | unsigned AS = Op0->getType()->getScalarType()->getPointerAddressSpace(); | |||
| 3446 | SDValue N = getValue(Op0); | |||
| 3447 | SDLoc dl = getCurSDLoc(); | |||
| 3448 | ||||
| 3449 | // Normalize Vector GEP - all scalar operands should be converted to the | |||
| 3450 | // splat vector. | |||
| 3451 | unsigned VectorWidth = I.getType()->isVectorTy() ? | |||
| 3452 | cast<VectorType>(I.getType())->getVectorNumElements() : 0; | |||
| 3453 | ||||
| 3454 | if (VectorWidth && !N.getValueType().isVector()) { | |||
| 3455 | LLVMContext &Context = *DAG.getContext(); | |||
| 3456 | EVT VT = EVT::getVectorVT(Context, N.getValueType(), VectorWidth); | |||
| 3457 | N = DAG.getSplatBuildVector(VT, dl, N); | |||
| 3458 | } | |||
| 3459 | ||||
| 3460 | for (gep_type_iterator GTI = gep_type_begin(&I), E = gep_type_end(&I); | |||
| 3461 | GTI != E; ++GTI) { | |||
| 3462 | const Value *Idx = GTI.getOperand(); | |||
| 3463 | if (StructType *StTy = GTI.getStructTypeOrNull()) { | |||
| 3464 | unsigned Field = cast<Constant>(Idx)->getUniqueInteger().getZExtValue(); | |||
| 3465 | if (Field) { | |||
| 3466 | // N = N + Offset | |||
| 3467 | uint64_t Offset = DL->getStructLayout(StTy)->getElementOffset(Field); | |||
| 3468 | ||||
| 3469 | // In an inbounds GEP with an offset that is nonnegative even when | |||
| 3470 | // interpreted as signed, assume there is no unsigned overflow. | |||
| 3471 | SDNodeFlags Flags; | |||
| 3472 | if (int64_t(Offset) >= 0 && cast<GEPOperator>(I).isInBounds()) | |||
| 3473 | Flags.setNoUnsignedWrap(true); | |||
| 3474 | ||||
| 3475 | N = DAG.getNode(ISD::ADD, dl, N.getValueType(), N, | |||
| 3476 | DAG.getConstant(Offset, dl, N.getValueType()), Flags); | |||
| 3477 | } | |||
| 3478 | } else { | |||
| 3479 | unsigned IdxSize = DAG.getDataLayout().getIndexSizeInBits(AS); | |||
| 3480 | MVT IdxTy = MVT::getIntegerVT(IdxSize); | |||
| 3481 | APInt ElementSize(IdxSize, DL->getTypeAllocSize(GTI.getIndexedType())); | |||
| 3482 | ||||
| 3483 | // If this is a scalar constant or a splat vector of constants, | |||
| 3484 | // handle it quickly. | |||
| 3485 | const auto *CI = dyn_cast<ConstantInt>(Idx); | |||
| 3486 | if (!CI && isa<ConstantDataVector>(Idx) && | |||
| 3487 | cast<ConstantDataVector>(Idx)->getSplatValue()) | |||
| 3488 | CI = cast<ConstantInt>(cast<ConstantDataVector>(Idx)->getSplatValue()); | |||
| 3489 | ||||
| 3490 | if (CI) { | |||
| 3491 | if (CI->isZero()) | |||
| 3492 | continue; | |||
| 3493 | APInt Offs = ElementSize * CI->getValue().sextOrTrunc(IdxSize); | |||
| 3494 | LLVMContext &Context = *DAG.getContext(); | |||
| 3495 | SDValue OffsVal = VectorWidth ? | |||
| 3496 | DAG.getConstant(Offs, dl, EVT::getVectorVT(Context, IdxTy, VectorWidth)) : | |||
| 3497 | DAG.getConstant(Offs, dl, IdxTy); | |||
| 3498 | ||||
| 3499 | // In an inbouds GEP with an offset that is nonnegative even when | |||
| 3500 | // interpreted as signed, assume there is no unsigned overflow. | |||
| 3501 | SDNodeFlags Flags; | |||
| 3502 | if (Offs.isNonNegative() && cast<GEPOperator>(I).isInBounds()) | |||
| 3503 | Flags.setNoUnsignedWrap(true); | |||
| 3504 | ||||
| 3505 | N = DAG.getNode(ISD::ADD, dl, N.getValueType(), N, OffsVal, Flags); | |||
| 3506 | continue; | |||
| 3507 | } | |||
| 3508 | ||||
| 3509 | // N = N + Idx * ElementSize; | |||
| 3510 | SDValue IdxN = getValue(Idx); | |||
| 3511 | ||||
| 3512 | if (!IdxN.getValueType().isVector() && VectorWidth) { | |||
| 3513 | EVT VT = EVT::getVectorVT(*Context, IdxN.getValueType(), VectorWidth); | |||
| 3514 | IdxN = DAG.getSplatBuildVector(VT, dl, IdxN); | |||
| 3515 | } | |||
| 3516 | ||||
| 3517 | // If the index is smaller or larger than intptr_t, truncate or extend | |||
| 3518 | // it. | |||
| 3519 | IdxN = DAG.getSExtOrTrunc(IdxN, dl, N.getValueType()); | |||
| 3520 | ||||
| 3521 | // If this is a multiply by a power of two, turn it into a shl | |||
| 3522 | // immediately. This is a very common case. | |||
| 3523 | if (ElementSize != 1) { | |||
| 3524 | if (ElementSize.isPowerOf2()) { | |||
| 3525 | unsigned Amt = ElementSize.logBase2(); | |||
| 3526 | IdxN = DAG.getNode(ISD::SHL, dl, | |||
| 3527 | N.getValueType(), IdxN, | |||
| 3528 | DAG.getConstant(Amt, dl, IdxN.getValueType())); | |||
| 3529 | } else { | |||
| 3530 | SDValue Scale = DAG.getConstant(ElementSize, dl, IdxN.getValueType()); | |||
| 3531 | IdxN = DAG.getNode(ISD::MUL, dl, | |||
| 3532 | N.getValueType(), IdxN, Scale); | |||
| 3533 | } | |||
| 3534 | } | |||
| 3535 | ||||
| 3536 | N = DAG.getNode(ISD::ADD, dl, | |||
| 3537 | N.getValueType(), N, IdxN); | |||
| 3538 | } | |||
| 3539 | } | |||
| 3540 | ||||
| 3541 | setValue(&I, N); | |||
| 3542 | } | |||
| 3543 | ||||
| 3544 | void SelectionDAGBuilder::visitAlloca(const AllocaInst &I) { | |||
| 3545 | // If this is a fixed sized alloca in the entry block of the function, | |||
| 3546 | // allocate it statically on the stack. | |||
| 3547 | if (FuncInfo.StaticAllocaMap.count(&I)) | |||
| 3548 | return; // getValue will auto-populate this. | |||
| 3549 | ||||
| 3550 | SDLoc dl = getCurSDLoc(); | |||
| 3551 | Type *Ty = I.getAllocatedType(); | |||
| 3552 | const TargetLowering &TLI = DAG.getTargetLoweringInfo(); | |||
| 3553 | auto &DL = DAG.getDataLayout(); | |||
| 3554 | uint64_t TySize = DL.getTypeAllocSize(Ty); | |||
| 3555 | unsigned Align = | |||
| 3556 | std::max((unsigned)DL.getPrefTypeAlignment(Ty), I.getAlignment()); | |||
| 3557 | ||||
| 3558 | SDValue AllocSize = getValue(I.getArraySize()); | |||
| 3559 | ||||
| 3560 | EVT IntPtr = TLI.getPointerTy(DAG.getDataLayout(), DL.getAllocaAddrSpace()); | |||
| 3561 | if (AllocSize.getValueType() != IntPtr) | |||
| 3562 | AllocSize = DAG.getZExtOrTrunc(AllocSize, dl, IntPtr); | |||
| 3563 | ||||
| 3564 | AllocSize = DAG.getNode(ISD::MUL, dl, IntPtr, | |||
| 3565 | AllocSize, | |||
| 3566 | DAG.getConstant(TySize, dl, IntPtr)); | |||
| 3567 | ||||
| 3568 | // Handle alignment. If the requested alignment is less than or equal to | |||
| 3569 | // the stack alignment, ignore it. If the size is greater than or equal to | |||
| 3570 | // the stack alignment, we note this in the DYNAMIC_STACKALLOC node. | |||
| 3571 | unsigned StackAlign = | |||
| 3572 | DAG.getSubtarget().getFrameLowering()->getStackAlignment(); | |||
| 3573 | if (Align <= StackAlign) | |||
| 3574 | Align = 0; | |||
| 3575 | ||||
| 3576 | // Round the size of the allocation up to the stack alignment size | |||
| 3577 | // by add SA-1 to the size. This doesn't overflow because we're computing | |||
| 3578 | // an address inside an alloca. | |||
| 3579 | SDNodeFlags Flags; | |||
| 3580 | Flags.setNoUnsignedWrap(true); | |||
| 3581 | AllocSize = DAG.getNode(ISD::ADD, dl, AllocSize.getValueType(), AllocSize, | |||
| 3582 | DAG.getConstant(StackAlign - 1, dl, IntPtr), Flags); | |||
| 3583 | ||||
| 3584 | // Mask out the low bits for alignment purposes. | |||
| 3585 | AllocSize = | |||
| 3586 | DAG.getNode(ISD::AND, dl, AllocSize.getValueType(), AllocSize, | |||
| 3587 | DAG.getConstant(~(uint64_t)(StackAlign - 1), dl, IntPtr)); | |||
| 3588 | ||||
| 3589 | SDValue Ops[] = {getRoot(), AllocSize, DAG.getConstant(Align, dl, IntPtr)}; | |||
| 3590 | SDVTList VTs = DAG.getVTList(AllocSize.getValueType(), MVT::Other); | |||
| 3591 | SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, dl, VTs, Ops); | |||
| 3592 | setValue(&I, DSA); | |||
| 3593 | DAG.setRoot(DSA.getValue(1)); | |||
| 3594 | ||||
| 3595 | assert(FuncInfo.MF->getFrameInfo().hasVarSizedObjects())(static_cast <bool> (FuncInfo.MF->getFrameInfo().hasVarSizedObjects ()) ? void (0) : __assert_fail ("FuncInfo.MF->getFrameInfo().hasVarSizedObjects()" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 3595, __extension__ __PRETTY_FUNCTION__)); | |||
| 3596 | } | |||
| 3597 | ||||
| 3598 | void SelectionDAGBuilder::visitLoad(const LoadInst &I) { | |||
| 3599 | if (I.isAtomic()) | |||
| 3600 | return visitAtomicLoad(I); | |||
| 3601 | ||||
| 3602 | const TargetLowering &TLI = DAG.getTargetLoweringInfo(); | |||
| 3603 | const Value *SV = I.getOperand(0); | |||
| 3604 | if (TLI.supportSwiftError()) { | |||
| 3605 | // Swifterror values can come from either a function parameter with | |||
| 3606 | // swifterror attribute or an alloca with swifterror attribute. | |||
| 3607 | if (const Argument *Arg = dyn_cast<Argument>(SV)) { | |||
| 3608 | if (Arg->hasSwiftErrorAttr()) | |||
| 3609 | return visitLoadFromSwiftError(I); | |||
| 3610 | } | |||
| 3611 | ||||
| 3612 | if (const AllocaInst *Alloca = dyn_cast<AllocaInst>(SV)) { | |||
| 3613 | if (Alloca->isSwiftError()) | |||
| 3614 | return visitLoadFromSwiftError(I); | |||
| 3615 | } | |||
| 3616 | } | |||
| 3617 | ||||
| 3618 | SDValue Ptr = getValue(SV); | |||
| 3619 | ||||
| 3620 | Type *Ty = I.getType(); | |||
| 3621 | ||||
| 3622 | bool isVolatile = I.isVolatile(); | |||
| 3623 | bool isNonTemporal = I.getMetadata(LLVMContext::MD_nontemporal) != nullptr; | |||
| 3624 | bool isInvariant = I.getMetadata(LLVMContext::MD_invariant_load) != nullptr; | |||
| 3625 | bool isDereferenceable = isDereferenceablePointer(SV, DAG.getDataLayout()); | |||
| 3626 | unsigned Alignment = I.getAlignment(); | |||
| 3627 | ||||
| 3628 | AAMDNodes AAInfo; | |||
| 3629 | I.getAAMetadata(AAInfo); | |||
| 3630 | const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range); | |||
| 3631 | ||||
| 3632 | SmallVector<EVT, 4> ValueVTs; | |||
| 3633 | SmallVector<uint64_t, 4> Offsets; | |||
| 3634 | ComputeValueVTs(TLI, DAG.getDataLayout(), Ty, ValueVTs, &Offsets); | |||
| 3635 | unsigned NumValues = ValueVTs.size(); | |||
| 3636 | if (NumValues == 0) | |||
| 3637 | return; | |||
| 3638 | ||||
| 3639 | SDValue Root; | |||
| 3640 | bool ConstantMemory = false; | |||
| 3641 | if (isVolatile || NumValues > MaxParallelChains) | |||
| 3642 | // Serialize volatile loads with other side effects. | |||
| 3643 | Root = getRoot(); | |||
| 3644 | else if (AA && AA->pointsToConstantMemory(MemoryLocation( | |||
| 3645 | SV, DAG.getDataLayout().getTypeStoreSize(Ty), AAInfo))) { | |||
| 3646 | // Do not serialize (non-volatile) loads of constant memory with anything. | |||
| 3647 | Root = DAG.getEntryNode(); | |||
| 3648 | ConstantMemory = true; | |||
| 3649 | } else { | |||
| 3650 | // Do not serialize non-volatile loads against each other. | |||
| 3651 | Root = DAG.getRoot(); | |||
| 3652 | } | |||
| 3653 | ||||
| 3654 | SDLoc dl = getCurSDLoc(); | |||
| 3655 | ||||
| 3656 | if (isVolatile) | |||
| 3657 | Root = TLI.prepareVolatileOrAtomicLoad(Root, dl, DAG); | |||
| 3658 | ||||
| 3659 | // An aggregate load cannot wrap around the address space, so offsets to its | |||
| 3660 | // parts don't wrap either. | |||
| 3661 | SDNodeFlags Flags; | |||
| 3662 | Flags.setNoUnsignedWrap(true); | |||
| 3663 | ||||
| 3664 | SmallVector<SDValue, 4> Values(NumValues); | |||
| 3665 | SmallVector<SDValue, 4> Chains(std::min(MaxParallelChains, NumValues)); | |||
| 3666 | EVT PtrVT = Ptr.getValueType(); | |||
| 3667 | unsigned ChainI = 0; | |||
| 3668 | for (unsigned i = 0; i != NumValues; ++i, ++ChainI) { | |||
| 3669 | // Serializing loads here may result in excessive register pressure, and | |||
| 3670 | // TokenFactor places arbitrary choke points on the scheduler. SD scheduling | |||
| 3671 | // could recover a bit by hoisting nodes upward in the chain by recognizing | |||
| 3672 | // they are side-effect free or do not alias. The optimizer should really | |||
| 3673 | // avoid this case by converting large object/array copies to llvm.memcpy | |||
| 3674 | // (MaxParallelChains should always remain as failsafe). | |||
| 3675 | if (ChainI == MaxParallelChains) { | |||
| 3676 | assert(PendingLoads.empty() && "PendingLoads must be serialized first")(static_cast <bool> (PendingLoads.empty() && "PendingLoads must be serialized first" ) ? void (0) : __assert_fail ("PendingLoads.empty() && \"PendingLoads must be serialized first\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 3676, __extension__ __PRETTY_FUNCTION__)); | |||
| 3677 | SDValue Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, | |||
| 3678 | makeArrayRef(Chains.data(), ChainI)); | |||
| 3679 | Root = Chain; | |||
| 3680 | ChainI = 0; | |||
| 3681 | } | |||
| 3682 | SDValue A = DAG.getNode(ISD::ADD, dl, | |||
| 3683 | PtrVT, Ptr, | |||
| 3684 | DAG.getConstant(Offsets[i], dl, PtrVT), | |||
| 3685 | Flags); | |||
| 3686 | auto MMOFlags = MachineMemOperand::MONone; | |||
| 3687 | if (isVolatile) | |||
| 3688 | MMOFlags |= MachineMemOperand::MOVolatile; | |||
| 3689 | if (isNonTemporal) | |||
| 3690 | MMOFlags |= MachineMemOperand::MONonTemporal; | |||
| 3691 | if (isInvariant) | |||
| 3692 | MMOFlags |= MachineMemOperand::MOInvariant; | |||
| 3693 | if (isDereferenceable) | |||
| 3694 | MMOFlags |= MachineMemOperand::MODereferenceable; | |||
| 3695 | MMOFlags |= TLI.getMMOFlags(I); | |||
| 3696 | ||||
| 3697 | SDValue L = DAG.getLoad(ValueVTs[i], dl, Root, A, | |||
| 3698 | MachinePointerInfo(SV, Offsets[i]), Alignment, | |||
| 3699 | MMOFlags, AAInfo, Ranges); | |||
| 3700 | ||||
| 3701 | Values[i] = L; | |||
| 3702 | Chains[ChainI] = L.getValue(1); | |||
| 3703 | } | |||
| 3704 | ||||
| 3705 | if (!ConstantMemory) { | |||
| 3706 | SDValue Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, | |||
| 3707 | makeArrayRef(Chains.data(), ChainI)); | |||
| 3708 | if (isVolatile) | |||
| 3709 | DAG.setRoot(Chain); | |||
| 3710 | else | |||
| 3711 | PendingLoads.push_back(Chain); | |||
| 3712 | } | |||
| 3713 | ||||
| 3714 | setValue(&I, DAG.getNode(ISD::MERGE_VALUES, dl, | |||
| 3715 | DAG.getVTList(ValueVTs), Values)); | |||
| 3716 | } | |||
| 3717 | ||||
| 3718 | void SelectionDAGBuilder::visitStoreToSwiftError(const StoreInst &I) { | |||
| 3719 | assert(DAG.getTargetLoweringInfo().supportSwiftError() &&(static_cast <bool> (DAG.getTargetLoweringInfo().supportSwiftError () && "call visitStoreToSwiftError when backend supports swifterror" ) ? void (0) : __assert_fail ("DAG.getTargetLoweringInfo().supportSwiftError() && \"call visitStoreToSwiftError when backend supports swifterror\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 3720, __extension__ __PRETTY_FUNCTION__)) | |||
| 3720 | "call visitStoreToSwiftError when backend supports swifterror")(static_cast <bool> (DAG.getTargetLoweringInfo().supportSwiftError () && "call visitStoreToSwiftError when backend supports swifterror" ) ? void (0) : __assert_fail ("DAG.getTargetLoweringInfo().supportSwiftError() && \"call visitStoreToSwiftError when backend supports swifterror\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 3720, __extension__ __PRETTY_FUNCTION__)); | |||
| 3721 | ||||
| 3722 | SmallVector<EVT, 4> ValueVTs; | |||
| 3723 | SmallVector<uint64_t, 4> Offsets; | |||
| 3724 | const Value *SrcV = I.getOperand(0); | |||
| 3725 | ComputeValueVTs(DAG.getTargetLoweringInfo(), DAG.getDataLayout(), | |||
| 3726 | SrcV->getType(), ValueVTs, &Offsets); | |||
| 3727 | assert(ValueVTs.size() == 1 && Offsets[0] == 0 &&(static_cast <bool> (ValueVTs.size() == 1 && Offsets [0] == 0 && "expect a single EVT for swifterror") ? void (0) : __assert_fail ("ValueVTs.size() == 1 && Offsets[0] == 0 && \"expect a single EVT for swifterror\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 3728, __extension__ __PRETTY_FUNCTION__)) | |||
| 3728 | "expect a single EVT for swifterror")(static_cast <bool> (ValueVTs.size() == 1 && Offsets [0] == 0 && "expect a single EVT for swifterror") ? void (0) : __assert_fail ("ValueVTs.size() == 1 && Offsets[0] == 0 && \"expect a single EVT for swifterror\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 3728, __extension__ __PRETTY_FUNCTION__)); | |||
| 3729 | ||||
| 3730 | SDValue Src = getValue(SrcV); | |||
| 3731 | // Create a virtual register, then update the virtual register. | |||
| 3732 | unsigned VReg; bool CreatedVReg; | |||
| 3733 | std::tie(VReg, CreatedVReg) = FuncInfo.getOrCreateSwiftErrorVRegDefAt(&I); | |||
| 3734 | // Chain, DL, Reg, N or Chain, DL, Reg, N, Glue | |||
| 3735 | // Chain can be getRoot or getControlRoot. | |||
| 3736 | SDValue CopyNode = DAG.getCopyToReg(getRoot(), getCurSDLoc(), VReg, | |||
| 3737 | SDValue(Src.getNode(), Src.getResNo())); | |||
| 3738 | DAG.setRoot(CopyNode); | |||
| 3739 | if (CreatedVReg) | |||
| 3740 | FuncInfo.setCurrentSwiftErrorVReg(FuncInfo.MBB, I.getOperand(1), VReg); | |||
| 3741 | } | |||
| 3742 | ||||
| 3743 | void SelectionDAGBuilder::visitLoadFromSwiftError(const LoadInst &I) { | |||
| 3744 | assert(DAG.getTargetLoweringInfo().supportSwiftError() &&(static_cast <bool> (DAG.getTargetLoweringInfo().supportSwiftError () && "call visitLoadFromSwiftError when backend supports swifterror" ) ? void (0) : __assert_fail ("DAG.getTargetLoweringInfo().supportSwiftError() && \"call visitLoadFromSwiftError when backend supports swifterror\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 3745, __extension__ __PRETTY_FUNCTION__)) | |||
| 3745 | "call visitLoadFromSwiftError when backend supports swifterror")(static_cast <bool> (DAG.getTargetLoweringInfo().supportSwiftError () && "call visitLoadFromSwiftError when backend supports swifterror" ) ? void (0) : __assert_fail ("DAG.getTargetLoweringInfo().supportSwiftError() && \"call visitLoadFromSwiftError when backend supports swifterror\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 3745, __extension__ __PRETTY_FUNCTION__)); | |||
| 3746 | ||||
| 3747 | assert(!I.isVolatile() &&(static_cast <bool> (!I.isVolatile() && I.getMetadata (LLVMContext::MD_nontemporal) == nullptr && I.getMetadata (LLVMContext::MD_invariant_load) == nullptr && "Support volatile, non temporal, invariant for load_from_swift_error" ) ? void (0) : __assert_fail ("!I.isVolatile() && I.getMetadata(LLVMContext::MD_nontemporal) == nullptr && I.getMetadata(LLVMContext::MD_invariant_load) == nullptr && \"Support volatile, non temporal, invariant for load_from_swift_error\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 3750, __extension__ __PRETTY_FUNCTION__)) | |||
| 3748 | I.getMetadata(LLVMContext::MD_nontemporal) == nullptr &&(static_cast <bool> (!I.isVolatile() && I.getMetadata (LLVMContext::MD_nontemporal) == nullptr && I.getMetadata (LLVMContext::MD_invariant_load) == nullptr && "Support volatile, non temporal, invariant for load_from_swift_error" ) ? void (0) : __assert_fail ("!I.isVolatile() && I.getMetadata(LLVMContext::MD_nontemporal) == nullptr && I.getMetadata(LLVMContext::MD_invariant_load) == nullptr && \"Support volatile, non temporal, invariant for load_from_swift_error\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 3750, __extension__ __PRETTY_FUNCTION__)) | |||
| 3749 | I.getMetadata(LLVMContext::MD_invariant_load) == nullptr &&(static_cast <bool> (!I.isVolatile() && I.getMetadata (LLVMContext::MD_nontemporal) == nullptr && I.getMetadata (LLVMContext::MD_invariant_load) == nullptr && "Support volatile, non temporal, invariant for load_from_swift_error" ) ? void (0) : __assert_fail ("!I.isVolatile() && I.getMetadata(LLVMContext::MD_nontemporal) == nullptr && I.getMetadata(LLVMContext::MD_invariant_load) == nullptr && \"Support volatile, non temporal, invariant for load_from_swift_error\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 3750, __extension__ __PRETTY_FUNCTION__)) | |||
| 3750 | "Support volatile, non temporal, invariant for load_from_swift_error")(static_cast <bool> (!I.isVolatile() && I.getMetadata (LLVMContext::MD_nontemporal) == nullptr && I.getMetadata (LLVMContext::MD_invariant_load) == nullptr && "Support volatile, non temporal, invariant for load_from_swift_error" ) ? void (0) : __assert_fail ("!I.isVolatile() && I.getMetadata(LLVMContext::MD_nontemporal) == nullptr && I.getMetadata(LLVMContext::MD_invariant_load) == nullptr && \"Support volatile, non temporal, invariant for load_from_swift_error\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 3750, __extension__ __PRETTY_FUNCTION__)); | |||
| 3751 | ||||
| 3752 | const Value *SV = I.getOperand(0); | |||
| 3753 | Type *Ty = I.getType(); | |||
| 3754 | AAMDNodes AAInfo; | |||
| 3755 | I.getAAMetadata(AAInfo); | |||
| 3756 | assert((!AA || !AA->pointsToConstantMemory(MemoryLocation((static_cast <bool> ((!AA || !AA->pointsToConstantMemory (MemoryLocation( SV, DAG.getDataLayout().getTypeStoreSize(Ty) , AAInfo))) && "load_from_swift_error should not be constant memory" ) ? void (0) : __assert_fail ("(!AA || !AA->pointsToConstantMemory(MemoryLocation( SV, DAG.getDataLayout().getTypeStoreSize(Ty), AAInfo))) && \"load_from_swift_error should not be constant memory\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 3758, __extension__ __PRETTY_FUNCTION__)) | |||
| 3757 | SV, DAG.getDataLayout().getTypeStoreSize(Ty), AAInfo))) &&(static_cast <bool> ((!AA || !AA->pointsToConstantMemory (MemoryLocation( SV, DAG.getDataLayout().getTypeStoreSize(Ty) , AAInfo))) && "load_from_swift_error should not be constant memory" ) ? void (0) : __assert_fail ("(!AA || !AA->pointsToConstantMemory(MemoryLocation( SV, DAG.getDataLayout().getTypeStoreSize(Ty), AAInfo))) && \"load_from_swift_error should not be constant memory\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 3758, __extension__ __PRETTY_FUNCTION__)) | |||
| 3758 | "load_from_swift_error should not be constant memory")(static_cast <bool> ((!AA || !AA->pointsToConstantMemory (MemoryLocation( SV, DAG.getDataLayout().getTypeStoreSize(Ty) , AAInfo))) && "load_from_swift_error should not be constant memory" ) ? void (0) : __assert_fail ("(!AA || !AA->pointsToConstantMemory(MemoryLocation( SV, DAG.getDataLayout().getTypeStoreSize(Ty), AAInfo))) && \"load_from_swift_error should not be constant memory\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 3758, __extension__ __PRETTY_FUNCTION__)); | |||
| 3759 | ||||
| 3760 | SmallVector<EVT, 4> ValueVTs; | |||
| 3761 | SmallVector<uint64_t, 4> Offsets; | |||
| 3762 | ComputeValueVTs(DAG.getTargetLoweringInfo(), DAG.getDataLayout(), Ty, | |||
| 3763 | ValueVTs, &Offsets); | |||
| 3764 | assert(ValueVTs.size() == 1 && Offsets[0] == 0 &&(static_cast <bool> (ValueVTs.size() == 1 && Offsets [0] == 0 && "expect a single EVT for swifterror") ? void (0) : __assert_fail ("ValueVTs.size() == 1 && Offsets[0] == 0 && \"expect a single EVT for swifterror\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 3765, __extension__ __PRETTY_FUNCTION__)) | |||
| 3765 | "expect a single EVT for swifterror")(static_cast <bool> (ValueVTs.size() == 1 && Offsets [0] == 0 && "expect a single EVT for swifterror") ? void (0) : __assert_fail ("ValueVTs.size() == 1 && Offsets[0] == 0 && \"expect a single EVT for swifterror\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 3765, __extension__ __PRETTY_FUNCTION__)); | |||
| 3766 | ||||
| 3767 | // Chain, DL, Reg, VT, Glue or Chain, DL, Reg, VT | |||
| 3768 | SDValue L = DAG.getCopyFromReg( | |||
| 3769 | getRoot(), getCurSDLoc(), | |||
| 3770 | FuncInfo.getOrCreateSwiftErrorVRegUseAt(&I, FuncInfo.MBB, SV).first, | |||
| 3771 | ValueVTs[0]); | |||
| 3772 | ||||
| 3773 | setValue(&I, L); | |||
| 3774 | } | |||
| 3775 | ||||
| 3776 | void SelectionDAGBuilder::visitStore(const StoreInst &I) { | |||
| 3777 | if (I.isAtomic()) | |||
| 3778 | return visitAtomicStore(I); | |||
| 3779 | ||||
| 3780 | const Value *SrcV = I.getOperand(0); | |||
| 3781 | const Value *PtrV = I.getOperand(1); | |||
| 3782 | ||||
| 3783 | const TargetLowering &TLI = DAG.getTargetLoweringInfo(); | |||
| 3784 | if (TLI.supportSwiftError()) { | |||
| 3785 | // Swifterror values can come from either a function parameter with | |||
| 3786 | // swifterror attribute or an alloca with swifterror attribute. | |||
| 3787 | if (const Argument *Arg = dyn_cast<Argument>(PtrV)) { | |||
| 3788 | if (Arg->hasSwiftErrorAttr()) | |||
| 3789 | return visitStoreToSwiftError(I); | |||
| 3790 | } | |||
| 3791 | ||||
| 3792 | if (const AllocaInst *Alloca = dyn_cast<AllocaInst>(PtrV)) { | |||
| 3793 | if (Alloca->isSwiftError()) | |||
| 3794 | return visitStoreToSwiftError(I); | |||
| 3795 | } | |||
| 3796 | } | |||
| 3797 | ||||
| 3798 | SmallVector<EVT, 4> ValueVTs; | |||
| 3799 | SmallVector<uint64_t, 4> Offsets; | |||
| 3800 | ComputeValueVTs(DAG.getTargetLoweringInfo(), DAG.getDataLayout(), | |||
| 3801 | SrcV->getType(), ValueVTs, &Offsets); | |||
| 3802 | unsigned NumValues = ValueVTs.size(); | |||
| 3803 | if (NumValues == 0) | |||
| 3804 | return; | |||
| 3805 | ||||
| 3806 | // Get the lowered operands. Note that we do this after | |||
| 3807 | // checking if NumResults is zero, because with zero results | |||
| 3808 | // the operands won't have values in the map. | |||
| 3809 | SDValue Src = getValue(SrcV); | |||
| 3810 | SDValue Ptr = getValue(PtrV); | |||
| 3811 | ||||
| 3812 | SDValue Root = getRoot(); | |||
| 3813 | SmallVector<SDValue, 4> Chains(std::min(MaxParallelChains, NumValues)); | |||
| 3814 | SDLoc dl = getCurSDLoc(); | |||
| 3815 | EVT PtrVT = Ptr.getValueType(); | |||
| 3816 | unsigned Alignment = I.getAlignment(); | |||
| 3817 | AAMDNodes AAInfo; | |||
| 3818 | I.getAAMetadata(AAInfo); | |||
| 3819 | ||||
| 3820 | auto MMOFlags = MachineMemOperand::MONone; | |||
| 3821 | if (I.isVolatile()) | |||
| 3822 | MMOFlags |= MachineMemOperand::MOVolatile; | |||
| 3823 | if (I.getMetadata(LLVMContext::MD_nontemporal) != nullptr) | |||
| 3824 | MMOFlags |= MachineMemOperand::MONonTemporal; | |||
| 3825 | MMOFlags |= TLI.getMMOFlags(I); | |||
| 3826 | ||||
| 3827 | // An aggregate load cannot wrap around the address space, so offsets to its | |||
| 3828 | // parts don't wrap either. | |||
| 3829 | SDNodeFlags Flags; | |||
| 3830 | Flags.setNoUnsignedWrap(true); | |||
| 3831 | ||||
| 3832 | unsigned ChainI = 0; | |||
| 3833 | for (unsigned i = 0; i != NumValues; ++i, ++ChainI) { | |||
| 3834 | // See visitLoad comments. | |||
| 3835 | if (ChainI == MaxParallelChains) { | |||
| 3836 | SDValue Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, | |||
| 3837 | makeArrayRef(Chains.data(), ChainI)); | |||
| 3838 | Root = Chain; | |||
| 3839 | ChainI = 0; | |||
| 3840 | } | |||
| 3841 | SDValue Add = DAG.getNode(ISD::ADD, dl, PtrVT, Ptr, | |||
| 3842 | DAG.getConstant(Offsets[i], dl, PtrVT), Flags); | |||
| 3843 | SDValue St = DAG.getStore( | |||
| 3844 | Root, dl, SDValue(Src.getNode(), Src.getResNo() + i), Add, | |||
| 3845 | MachinePointerInfo(PtrV, Offsets[i]), Alignment, MMOFlags, AAInfo); | |||
| 3846 | Chains[ChainI] = St; | |||
| 3847 | } | |||
| 3848 | ||||
| 3849 | SDValue StoreNode = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, | |||
| 3850 | makeArrayRef(Chains.data(), ChainI)); | |||
| 3851 | DAG.setRoot(StoreNode); | |||
| 3852 | } | |||
| 3853 | ||||
| 3854 | void SelectionDAGBuilder::visitMaskedStore(const CallInst &I, | |||
| 3855 | bool IsCompressing) { | |||
| 3856 | SDLoc sdl = getCurSDLoc(); | |||
| 3857 | ||||
| 3858 | auto getMaskedStoreOps = [&](Value* &Ptr, Value* &Mask, Value* &Src0, | |||
| 3859 | unsigned& Alignment) { | |||
| 3860 | // llvm.masked.store.*(Src0, Ptr, alignment, Mask) | |||
| 3861 | Src0 = I.getArgOperand(0); | |||
| 3862 | Ptr = I.getArgOperand(1); | |||
| 3863 | Alignment = cast<ConstantInt>(I.getArgOperand(2))->getZExtValue(); | |||
| 3864 | Mask = I.getArgOperand(3); | |||
| 3865 | }; | |||
| 3866 | auto getCompressingStoreOps = [&](Value* &Ptr, Value* &Mask, Value* &Src0, | |||
| 3867 | unsigned& Alignment) { | |||
| 3868 | // llvm.masked.compressstore.*(Src0, Ptr, Mask) | |||
| 3869 | Src0 = I.getArgOperand(0); | |||
| 3870 | Ptr = I.getArgOperand(1); | |||
| 3871 | Mask = I.getArgOperand(2); | |||
| 3872 | Alignment = 0; | |||
| 3873 | }; | |||
| 3874 | ||||
| 3875 | Value *PtrOperand, *MaskOperand, *Src0Operand; | |||
| 3876 | unsigned Alignment; | |||
| 3877 | if (IsCompressing) | |||
| 3878 | getCompressingStoreOps(PtrOperand, MaskOperand, Src0Operand, Alignment); | |||
| 3879 | else | |||
| 3880 | getMaskedStoreOps(PtrOperand, MaskOperand, Src0Operand, Alignment); | |||
| 3881 | ||||
| 3882 | SDValue Ptr = getValue(PtrOperand); | |||
| 3883 | SDValue Src0 = getValue(Src0Operand); | |||
| 3884 | SDValue Mask = getValue(MaskOperand); | |||
| 3885 | ||||
| 3886 | EVT VT = Src0.getValueType(); | |||
| 3887 | if (!Alignment) | |||
| 3888 | Alignment = DAG.getEVTAlignment(VT); | |||
| 3889 | ||||
| 3890 | AAMDNodes AAInfo; | |||
| 3891 | I.getAAMetadata(AAInfo); | |||
| 3892 | ||||
| 3893 | MachineMemOperand *MMO = | |||
| 3894 | DAG.getMachineFunction(). | |||
| 3895 | getMachineMemOperand(MachinePointerInfo(PtrOperand), | |||
| 3896 | MachineMemOperand::MOStore, VT.getStoreSize(), | |||
| 3897 | Alignment, AAInfo); | |||
| 3898 | SDValue StoreNode = DAG.getMaskedStore(getRoot(), sdl, Src0, Ptr, Mask, VT, | |||
| 3899 | MMO, false /* Truncating */, | |||
| 3900 | IsCompressing); | |||
| 3901 | DAG.setRoot(StoreNode); | |||
| 3902 | setValue(&I, StoreNode); | |||
| 3903 | } | |||
| 3904 | ||||
| 3905 | // Get a uniform base for the Gather/Scatter intrinsic. | |||
| 3906 | // The first argument of the Gather/Scatter intrinsic is a vector of pointers. | |||
| 3907 | // We try to represent it as a base pointer + vector of indices. | |||
| 3908 | // Usually, the vector of pointers comes from a 'getelementptr' instruction. | |||
| 3909 | // The first operand of the GEP may be a single pointer or a vector of pointers | |||
| 3910 | // Example: | |||
| 3911 | // %gep.ptr = getelementptr i32, <8 x i32*> %vptr, <8 x i32> %ind | |||
| 3912 | // or | |||
| 3913 | // %gep.ptr = getelementptr i32, i32* %ptr, <8 x i32> %ind | |||
| 3914 | // %res = call <8 x i32> @llvm.masked.gather.v8i32(<8 x i32*> %gep.ptr, .. | |||
| 3915 | // | |||
| 3916 | // When the first GEP operand is a single pointer - it is the uniform base we | |||
| 3917 | // are looking for. If first operand of the GEP is a splat vector - we | |||
| 3918 | // extract the splat value and use it as a uniform base. | |||
| 3919 | // In all other cases the function returns 'false'. | |||
| 3920 | static bool getUniformBase(const Value* &Ptr, SDValue& Base, SDValue& Index, | |||
| 3921 | SDValue &Scale, SelectionDAGBuilder* SDB) { | |||
| 3922 | SelectionDAG& DAG = SDB->DAG; | |||
| 3923 | LLVMContext &Context = *DAG.getContext(); | |||
| 3924 | ||||
| 3925 | assert(Ptr->getType()->isVectorTy() && "Uexpected pointer type")(static_cast <bool> (Ptr->getType()->isVectorTy() && "Uexpected pointer type") ? void (0) : __assert_fail ("Ptr->getType()->isVectorTy() && \"Uexpected pointer type\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 3925, __extension__ __PRETTY_FUNCTION__)); | |||
| 3926 | const GetElementPtrInst *GEP = dyn_cast<GetElementPtrInst>(Ptr); | |||
| 3927 | if (!GEP) | |||
| 3928 | return false; | |||
| 3929 | ||||
| 3930 | const Value *GEPPtr = GEP->getPointerOperand(); | |||
| 3931 | if (!GEPPtr->getType()->isVectorTy()) | |||
| 3932 | Ptr = GEPPtr; | |||
| 3933 | else if (!(Ptr = getSplatValue(GEPPtr))) | |||
| 3934 | return false; | |||
| 3935 | ||||
| 3936 | unsigned FinalIndex = GEP->getNumOperands() - 1; | |||
| 3937 | Value *IndexVal = GEP->getOperand(FinalIndex); | |||
| 3938 | ||||
| 3939 | // Ensure all the other indices are 0. | |||
| 3940 | for (unsigned i = 1; i < FinalIndex; ++i) { | |||
| 3941 | auto *C = dyn_cast<ConstantInt>(GEP->getOperand(i)); | |||
| 3942 | if (!C || !C->isZero()) | |||
| 3943 | return false; | |||
| 3944 | } | |||
| 3945 | ||||
| 3946 | // The operands of the GEP may be defined in another basic block. | |||
| 3947 | // In this case we'll not find nodes for the operands. | |||
| 3948 | if (!SDB->findValue(Ptr) || !SDB->findValue(IndexVal)) | |||
| 3949 | return false; | |||
| 3950 | ||||
| 3951 | const TargetLowering &TLI = DAG.getTargetLoweringInfo(); | |||
| 3952 | const DataLayout &DL = DAG.getDataLayout(); | |||
| 3953 | Scale = DAG.getTargetConstant(DL.getTypeAllocSize(GEP->getResultElementType()), | |||
| 3954 | SDB->getCurSDLoc(), TLI.getPointerTy(DL)); | |||
| 3955 | Base = SDB->getValue(Ptr); | |||
| 3956 | Index = SDB->getValue(IndexVal); | |||
| 3957 | ||||
| 3958 | if (!Index.getValueType().isVector()) { | |||
| 3959 | unsigned GEPWidth = GEP->getType()->getVectorNumElements(); | |||
| 3960 | EVT VT = EVT::getVectorVT(Context, Index.getValueType(), GEPWidth); | |||
| 3961 | Index = DAG.getSplatBuildVector(VT, SDLoc(Index), Index); | |||
| 3962 | } | |||
| 3963 | return true; | |||
| 3964 | } | |||
| 3965 | ||||
| 3966 | void SelectionDAGBuilder::visitMaskedScatter(const CallInst &I) { | |||
| 3967 | SDLoc sdl = getCurSDLoc(); | |||
| 3968 | ||||
| 3969 | // llvm.masked.scatter.*(Src0, Ptrs, alignemt, Mask) | |||
| 3970 | const Value *Ptr = I.getArgOperand(1); | |||
| 3971 | SDValue Src0 = getValue(I.getArgOperand(0)); | |||
| 3972 | SDValue Mask = getValue(I.getArgOperand(3)); | |||
| 3973 | EVT VT = Src0.getValueType(); | |||
| 3974 | unsigned Alignment = (cast<ConstantInt>(I.getArgOperand(2)))->getZExtValue(); | |||
| 3975 | if (!Alignment) | |||
| 3976 | Alignment = DAG.getEVTAlignment(VT); | |||
| 3977 | const TargetLowering &TLI = DAG.getTargetLoweringInfo(); | |||
| 3978 | ||||
| 3979 | AAMDNodes AAInfo; | |||
| 3980 | I.getAAMetadata(AAInfo); | |||
| 3981 | ||||
| 3982 | SDValue Base; | |||
| 3983 | SDValue Index; | |||
| 3984 | SDValue Scale; | |||
| 3985 | const Value *BasePtr = Ptr; | |||
| 3986 | bool UniformBase = getUniformBase(BasePtr, Base, Index, Scale, this); | |||
| 3987 | ||||
| 3988 | const Value *MemOpBasePtr = UniformBase ? BasePtr : nullptr; | |||
| 3989 | MachineMemOperand *MMO = DAG.getMachineFunction(). | |||
| 3990 | getMachineMemOperand(MachinePointerInfo(MemOpBasePtr), | |||
| 3991 | MachineMemOperand::MOStore, VT.getStoreSize(), | |||
| 3992 | Alignment, AAInfo); | |||
| 3993 | if (!UniformBase) { | |||
| 3994 | Base = DAG.getConstant(0, sdl, TLI.getPointerTy(DAG.getDataLayout())); | |||
| 3995 | Index = getValue(Ptr); | |||
| 3996 | Scale = DAG.getTargetConstant(1, sdl, TLI.getPointerTy(DAG.getDataLayout())); | |||
| 3997 | } | |||
| 3998 | SDValue Ops[] = { getRoot(), Src0, Mask, Base, Index, Scale }; | |||
| 3999 | SDValue Scatter = DAG.getMaskedScatter(DAG.getVTList(MVT::Other), VT, sdl, | |||
| 4000 | Ops, MMO); | |||
| 4001 | DAG.setRoot(Scatter); | |||
| 4002 | setValue(&I, Scatter); | |||
| 4003 | } | |||
| 4004 | ||||
| 4005 | void SelectionDAGBuilder::visitMaskedLoad(const CallInst &I, bool IsExpanding) { | |||
| 4006 | SDLoc sdl = getCurSDLoc(); | |||
| 4007 | ||||
| 4008 | auto getMaskedLoadOps = [&](Value* &Ptr, Value* &Mask, Value* &Src0, | |||
| 4009 | unsigned& Alignment) { | |||
| 4010 | // @llvm.masked.load.*(Ptr, alignment, Mask, Src0) | |||
| 4011 | Ptr = I.getArgOperand(0); | |||
| 4012 | Alignment = cast<ConstantInt>(I.getArgOperand(1))->getZExtValue(); | |||
| 4013 | Mask = I.getArgOperand(2); | |||
| 4014 | Src0 = I.getArgOperand(3); | |||
| 4015 | }; | |||
| 4016 | auto getExpandingLoadOps = [&](Value* &Ptr, Value* &Mask, Value* &Src0, | |||
| 4017 | unsigned& Alignment) { | |||
| 4018 | // @llvm.masked.expandload.*(Ptr, Mask, Src0) | |||
| 4019 | Ptr = I.getArgOperand(0); | |||
| 4020 | Alignment = 0; | |||
| 4021 | Mask = I.getArgOperand(1); | |||
| 4022 | Src0 = I.getArgOperand(2); | |||
| 4023 | }; | |||
| 4024 | ||||
| 4025 | Value *PtrOperand, *MaskOperand, *Src0Operand; | |||
| 4026 | unsigned Alignment; | |||
| 4027 | if (IsExpanding) | |||
| 4028 | getExpandingLoadOps(PtrOperand, MaskOperand, Src0Operand, Alignment); | |||
| 4029 | else | |||
| 4030 | getMaskedLoadOps(PtrOperand, MaskOperand, Src0Operand, Alignment); | |||
| 4031 | ||||
| 4032 | SDValue Ptr = getValue(PtrOperand); | |||
| 4033 | SDValue Src0 = getValue(Src0Operand); | |||
| 4034 | SDValue Mask = getValue(MaskOperand); | |||
| 4035 | ||||
| 4036 | EVT VT = Src0.getValueType(); | |||
| 4037 | if (!Alignment) | |||
| 4038 | Alignment = DAG.getEVTAlignment(VT); | |||
| 4039 | ||||
| 4040 | AAMDNodes AAInfo; | |||
| 4041 | I.getAAMetadata(AAInfo); | |||
| 4042 | const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range); | |||
| 4043 | ||||
| 4044 | // Do not serialize masked loads of constant memory with anything. | |||
| 4045 | bool AddToChain = !AA || !AA->pointsToConstantMemory(MemoryLocation( | |||
| 4046 | PtrOperand, DAG.getDataLayout().getTypeStoreSize(I.getType()), AAInfo)); | |||
| 4047 | SDValue InChain = AddToChain ? DAG.getRoot() : DAG.getEntryNode(); | |||
| 4048 | ||||
| 4049 | MachineMemOperand *MMO = | |||
| 4050 | DAG.getMachineFunction(). | |||
| 4051 | getMachineMemOperand(MachinePointerInfo(PtrOperand), | |||
| 4052 | MachineMemOperand::MOLoad, VT.getStoreSize(), | |||
| 4053 | Alignment, AAInfo, Ranges); | |||
| 4054 | ||||
| 4055 | SDValue Load = DAG.getMaskedLoad(VT, sdl, InChain, Ptr, Mask, Src0, VT, MMO, | |||
| 4056 | ISD::NON_EXTLOAD, IsExpanding); | |||
| 4057 | if (AddToChain) { | |||
| 4058 | SDValue OutChain = Load.getValue(1); | |||
| 4059 | DAG.setRoot(OutChain); | |||
| 4060 | } | |||
| 4061 | setValue(&I, Load); | |||
| 4062 | } | |||
| 4063 | ||||
| 4064 | void SelectionDAGBuilder::visitMaskedGather(const CallInst &I) { | |||
| 4065 | SDLoc sdl = getCurSDLoc(); | |||
| 4066 | ||||
| 4067 | // @llvm.masked.gather.*(Ptrs, alignment, Mask, Src0) | |||
| 4068 | const Value *Ptr = I.getArgOperand(0); | |||
| 4069 | SDValue Src0 = getValue(I.getArgOperand(3)); | |||
| 4070 | SDValue Mask = getValue(I.getArgOperand(2)); | |||
| 4071 | ||||
| 4072 | const TargetLowering &TLI = DAG.getTargetLoweringInfo(); | |||
| 4073 | EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType()); | |||
| 4074 | unsigned Alignment = (cast<ConstantInt>(I.getArgOperand(1)))->getZExtValue(); | |||
| 4075 | if (!Alignment) | |||
| 4076 | Alignment = DAG.getEVTAlignment(VT); | |||
| 4077 | ||||
| 4078 | AAMDNodes AAInfo; | |||
| 4079 | I.getAAMetadata(AAInfo); | |||
| 4080 | const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range); | |||
| 4081 | ||||
| 4082 | SDValue Root = DAG.getRoot(); | |||
| 4083 | SDValue Base; | |||
| 4084 | SDValue Index; | |||
| 4085 | SDValue Scale; | |||
| 4086 | const Value *BasePtr = Ptr; | |||
| 4087 | bool UniformBase = getUniformBase(BasePtr, Base, Index, Scale, this); | |||
| 4088 | bool ConstantMemory = false; | |||
| 4089 | if (UniformBase && | |||
| 4090 | AA && AA->pointsToConstantMemory(MemoryLocation( | |||
| 4091 | BasePtr, DAG.getDataLayout().getTypeStoreSize(I.getType()), | |||
| 4092 | AAInfo))) { | |||
| 4093 | // Do not serialize (non-volatile) loads of constant memory with anything. | |||
| 4094 | Root = DAG.getEntryNode(); | |||
| 4095 | ConstantMemory = true; | |||
| 4096 | } | |||
| 4097 | ||||
| 4098 | MachineMemOperand *MMO = | |||
| 4099 | DAG.getMachineFunction(). | |||
| 4100 | getMachineMemOperand(MachinePointerInfo(UniformBase ? BasePtr : nullptr), | |||
| 4101 | MachineMemOperand::MOLoad, VT.getStoreSize(), | |||
| 4102 | Alignment, AAInfo, Ranges); | |||
| 4103 | ||||
| 4104 | if (!UniformBase) { | |||
| 4105 | Base = DAG.getConstant(0, sdl, TLI.getPointerTy(DAG.getDataLayout())); | |||
| 4106 | Index = getValue(Ptr); | |||
| 4107 | Scale = DAG.getTargetConstant(1, sdl, TLI.getPointerTy(DAG.getDataLayout())); | |||
| 4108 | } | |||
| 4109 | SDValue Ops[] = { Root, Src0, Mask, Base, Index, Scale }; | |||
| 4110 | SDValue Gather = DAG.getMaskedGather(DAG.getVTList(VT, MVT::Other), VT, sdl, | |||
| 4111 | Ops, MMO); | |||
| 4112 | ||||
| 4113 | SDValue OutChain = Gather.getValue(1); | |||
| 4114 | if (!ConstantMemory) | |||
| 4115 | PendingLoads.push_back(OutChain); | |||
| 4116 | setValue(&I, Gather); | |||
| 4117 | } | |||
| 4118 | ||||
| 4119 | void SelectionDAGBuilder::visitAtomicCmpXchg(const AtomicCmpXchgInst &I) { | |||
| 4120 | SDLoc dl = getCurSDLoc(); | |||
| 4121 | AtomicOrdering SuccessOrder = I.getSuccessOrdering(); | |||
| 4122 | AtomicOrdering FailureOrder = I.getFailureOrdering(); | |||
| 4123 | SyncScope::ID SSID = I.getSyncScopeID(); | |||
| 4124 | ||||
| 4125 | SDValue InChain = getRoot(); | |||
| 4126 | ||||
| 4127 | MVT MemVT = getValue(I.getCompareOperand()).getSimpleValueType(); | |||
| 4128 | SDVTList VTs = DAG.getVTList(MemVT, MVT::i1, MVT::Other); | |||
| 4129 | SDValue L = DAG.getAtomicCmpSwap( | |||
| 4130 | ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, dl, MemVT, VTs, InChain, | |||
| 4131 | getValue(I.getPointerOperand()), getValue(I.getCompareOperand()), | |||
| 4132 | getValue(I.getNewValOperand()), MachinePointerInfo(I.getPointerOperand()), | |||
| 4133 | /*Alignment=*/ 0, SuccessOrder, FailureOrder, SSID); | |||
| 4134 | ||||
| 4135 | SDValue OutChain = L.getValue(2); | |||
| 4136 | ||||
| 4137 | setValue(&I, L); | |||
| 4138 | DAG.setRoot(OutChain); | |||
| 4139 | } | |||
| 4140 | ||||
| 4141 | void SelectionDAGBuilder::visitAtomicRMW(const AtomicRMWInst &I) { | |||
| 4142 | SDLoc dl = getCurSDLoc(); | |||
| 4143 | ISD::NodeType NT; | |||
| 4144 | switch (I.getOperation()) { | |||
| 4145 | default: llvm_unreachable("Unknown atomicrmw operation")::llvm::llvm_unreachable_internal("Unknown atomicrmw operation" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 4145); | |||
| 4146 | case AtomicRMWInst::Xchg: NT = ISD::ATOMIC_SWAP; break; | |||
| 4147 | case AtomicRMWInst::Add: NT = ISD::ATOMIC_LOAD_ADD; break; | |||
| 4148 | case AtomicRMWInst::Sub: NT = ISD::ATOMIC_LOAD_SUB; break; | |||
| 4149 | case AtomicRMWInst::And: NT = ISD::ATOMIC_LOAD_AND; break; | |||
| 4150 | case AtomicRMWInst::Nand: NT = ISD::ATOMIC_LOAD_NAND; break; | |||
| 4151 | case AtomicRMWInst::Or: NT = ISD::ATOMIC_LOAD_OR; break; | |||
| 4152 | case AtomicRMWInst::Xor: NT = ISD::ATOMIC_LOAD_XOR; break; | |||
| 4153 | case AtomicRMWInst::Max: NT = ISD::ATOMIC_LOAD_MAX; break; | |||
| 4154 | case AtomicRMWInst::Min: NT = ISD::ATOMIC_LOAD_MIN; break; | |||
| 4155 | case AtomicRMWInst::UMax: NT = ISD::ATOMIC_LOAD_UMAX; break; | |||
| 4156 | case AtomicRMWInst::UMin: NT = ISD::ATOMIC_LOAD_UMIN; break; | |||
| 4157 | } | |||
| 4158 | AtomicOrdering Order = I.getOrdering(); | |||
| 4159 | SyncScope::ID SSID = I.getSyncScopeID(); | |||
| 4160 | ||||
| 4161 | SDValue InChain = getRoot(); | |||
| 4162 | ||||
| 4163 | SDValue L = | |||
| 4164 | DAG.getAtomic(NT, dl, | |||
| 4165 | getValue(I.getValOperand()).getSimpleValueType(), | |||
| 4166 | InChain, | |||
| 4167 | getValue(I.getPointerOperand()), | |||
| 4168 | getValue(I.getValOperand()), | |||
| 4169 | I.getPointerOperand(), | |||
| 4170 | /* Alignment=*/ 0, Order, SSID); | |||
| 4171 | ||||
| 4172 | SDValue OutChain = L.getValue(1); | |||
| 4173 | ||||
| 4174 | setValue(&I, L); | |||
| 4175 | DAG.setRoot(OutChain); | |||
| 4176 | } | |||
| 4177 | ||||
| 4178 | void SelectionDAGBuilder::visitFence(const FenceInst &I) { | |||
| 4179 | SDLoc dl = getCurSDLoc(); | |||
| 4180 | const TargetLowering &TLI = DAG.getTargetLoweringInfo(); | |||
| 4181 | SDValue Ops[3]; | |||
| 4182 | Ops[0] = getRoot(); | |||
| 4183 | Ops[1] = DAG.getConstant((unsigned)I.getOrdering(), dl, | |||
| 4184 | TLI.getFenceOperandTy(DAG.getDataLayout())); | |||
| 4185 | Ops[2] = DAG.getConstant(I.getSyncScopeID(), dl, | |||
| 4186 | TLI.getFenceOperandTy(DAG.getDataLayout())); | |||
| 4187 | DAG.setRoot(DAG.getNode(ISD::ATOMIC_FENCE, dl, MVT::Other, Ops)); | |||
| 4188 | } | |||
| 4189 | ||||
| 4190 | void SelectionDAGBuilder::visitAtomicLoad(const LoadInst &I) { | |||
| 4191 | SDLoc dl = getCurSDLoc(); | |||
| 4192 | AtomicOrdering Order = I.getOrdering(); | |||
| 4193 | SyncScope::ID SSID = I.getSyncScopeID(); | |||
| 4194 | ||||
| 4195 | SDValue InChain = getRoot(); | |||
| 4196 | ||||
| 4197 | const TargetLowering &TLI = DAG.getTargetLoweringInfo(); | |||
| 4198 | EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType()); | |||
| 4199 | ||||
| 4200 | if (!TLI.supportsUnalignedAtomics() && | |||
| 4201 | I.getAlignment() < VT.getStoreSize()) | |||
| 4202 | report_fatal_error("Cannot generate unaligned atomic load"); | |||
| 4203 | ||||
| 4204 | MachineMemOperand *MMO = | |||
| 4205 | DAG.getMachineFunction(). | |||
| 4206 | getMachineMemOperand(MachinePointerInfo(I.getPointerOperand()), | |||
| 4207 | MachineMemOperand::MOVolatile | | |||
| 4208 | MachineMemOperand::MOLoad, | |||
| 4209 | VT.getStoreSize(), | |||
| 4210 | I.getAlignment() ? I.getAlignment() : | |||
| 4211 | DAG.getEVTAlignment(VT), | |||
| 4212 | AAMDNodes(), nullptr, SSID, Order); | |||
| 4213 | ||||
| 4214 | InChain = TLI.prepareVolatileOrAtomicLoad(InChain, dl, DAG); | |||
| 4215 | SDValue L = | |||
| 4216 | DAG.getAtomic(ISD::ATOMIC_LOAD, dl, VT, VT, InChain, | |||
| 4217 | getValue(I.getPointerOperand()), MMO); | |||
| 4218 | ||||
| 4219 | SDValue OutChain = L.getValue(1); | |||
| 4220 | ||||
| 4221 | setValue(&I, L); | |||
| 4222 | DAG.setRoot(OutChain); | |||
| 4223 | } | |||
| 4224 | ||||
| 4225 | void SelectionDAGBuilder::visitAtomicStore(const StoreInst &I) { | |||
| 4226 | SDLoc dl = getCurSDLoc(); | |||
| 4227 | ||||
| 4228 | AtomicOrdering Order = I.getOrdering(); | |||
| 4229 | SyncScope::ID SSID = I.getSyncScopeID(); | |||
| 4230 | ||||
| 4231 | SDValue InChain = getRoot(); | |||
| 4232 | ||||
| 4233 | const TargetLowering &TLI = DAG.getTargetLoweringInfo(); | |||
| 4234 | EVT VT = | |||
| 4235 | TLI.getValueType(DAG.getDataLayout(), I.getValueOperand()->getType()); | |||
| 4236 | ||||
| 4237 | if (I.getAlignment() < VT.getStoreSize()) | |||
| 4238 | report_fatal_error("Cannot generate unaligned atomic store"); | |||
| 4239 | ||||
| 4240 | SDValue OutChain = | |||
| 4241 | DAG.getAtomic(ISD::ATOMIC_STORE, dl, VT, | |||
| 4242 | InChain, | |||
| 4243 | getValue(I.getPointerOperand()), | |||
| 4244 | getValue(I.getValueOperand()), | |||
| 4245 | I.getPointerOperand(), I.getAlignment(), | |||
| 4246 | Order, SSID); | |||
| 4247 | ||||
| 4248 | DAG.setRoot(OutChain); | |||
| 4249 | } | |||
| 4250 | ||||
| 4251 | /// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC | |||
| 4252 | /// node. | |||
| 4253 | void SelectionDAGBuilder::visitTargetIntrinsic(const CallInst &I, | |||
| 4254 | unsigned Intrinsic) { | |||
| 4255 | // Ignore the callsite's attributes. A specific call site may be marked with | |||
| 4256 | // readnone, but the lowering code will expect the chain based on the | |||
| 4257 | // definition. | |||
| 4258 | const Function *F = I.getCalledFunction(); | |||
| 4259 | bool HasChain = !F->doesNotAccessMemory(); | |||
| 4260 | bool OnlyLoad = HasChain && F->onlyReadsMemory(); | |||
| 4261 | ||||
| 4262 | // Build the operand list. | |||
| 4263 | SmallVector<SDValue, 8> Ops; | |||
| 4264 | if (HasChain) { // If this intrinsic has side-effects, chainify it. | |||
| 4265 | if (OnlyLoad) { | |||
| 4266 | // We don't need to serialize loads against other loads. | |||
| 4267 | Ops.push_back(DAG.getRoot()); | |||
| 4268 | } else { | |||
| 4269 | Ops.push_back(getRoot()); | |||
| 4270 | } | |||
| 4271 | } | |||
| 4272 | ||||
| 4273 | // Info is set by getTgtMemInstrinsic | |||
| 4274 | TargetLowering::IntrinsicInfo Info; | |||
| 4275 | const TargetLowering &TLI = DAG.getTargetLoweringInfo(); | |||
| 4276 | bool IsTgtIntrinsic = TLI.getTgtMemIntrinsic(Info, I, | |||
| 4277 | DAG.getMachineFunction(), | |||
| 4278 | Intrinsic); | |||
| 4279 | ||||
| 4280 | // Add the intrinsic ID as an integer operand if it's not a target intrinsic. | |||
| 4281 | if (!IsTgtIntrinsic || Info.opc == ISD::INTRINSIC_VOID || | |||
| 4282 | Info.opc == ISD::INTRINSIC_W_CHAIN) | |||
| 4283 | Ops.push_back(DAG.getTargetConstant(Intrinsic, getCurSDLoc(), | |||
| 4284 | TLI.getPointerTy(DAG.getDataLayout()))); | |||
| 4285 | ||||
| 4286 | // Add all operands of the call to the operand list. | |||
| 4287 | for (unsigned i = 0, e = I.getNumArgOperands(); i != e; ++i) { | |||
| 4288 | SDValue Op = getValue(I.getArgOperand(i)); | |||
| 4289 | Ops.push_back(Op); | |||
| 4290 | } | |||
| 4291 | ||||
| 4292 | SmallVector<EVT, 4> ValueVTs; | |||
| 4293 | ComputeValueVTs(TLI, DAG.getDataLayout(), I.getType(), ValueVTs); | |||
| 4294 | ||||
| 4295 | if (HasChain) | |||
| 4296 | ValueVTs.push_back(MVT::Other); | |||
| 4297 | ||||
| 4298 | SDVTList VTs = DAG.getVTList(ValueVTs); | |||
| 4299 | ||||
| 4300 | // Create the node. | |||
| 4301 | SDValue Result; | |||
| 4302 | if (IsTgtIntrinsic) { | |||
| 4303 | // This is target intrinsic that touches memory | |||
| 4304 | Result = DAG.getMemIntrinsicNode(Info.opc, getCurSDLoc(), VTs, | |||
| 4305 | Ops, Info.memVT, | |||
| 4306 | MachinePointerInfo(Info.ptrVal, Info.offset), Info.align, | |||
| 4307 | Info.flags, Info.size); | |||
| 4308 | } else if (!HasChain) { | |||
| 4309 | Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, getCurSDLoc(), VTs, Ops); | |||
| 4310 | } else if (!I.getType()->isVoidTy()) { | |||
| 4311 | Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, getCurSDLoc(), VTs, Ops); | |||
| 4312 | } else { | |||
| 4313 | Result = DAG.getNode(ISD::INTRINSIC_VOID, getCurSDLoc(), VTs, Ops); | |||
| 4314 | } | |||
| 4315 | ||||
| 4316 | if (HasChain) { | |||
| 4317 | SDValue Chain = Result.getValue(Result.getNode()->getNumValues()-1); | |||
| 4318 | if (OnlyLoad) | |||
| 4319 | PendingLoads.push_back(Chain); | |||
| 4320 | else | |||
| 4321 | DAG.setRoot(Chain); | |||
| 4322 | } | |||
| 4323 | ||||
| 4324 | if (!I.getType()->isVoidTy()) { | |||
| 4325 | if (VectorType *PTy = dyn_cast<VectorType>(I.getType())) { | |||
| 4326 | EVT VT = TLI.getValueType(DAG.getDataLayout(), PTy); | |||
| 4327 | Result = DAG.getNode(ISD::BITCAST, getCurSDLoc(), VT, Result); | |||
| 4328 | } else | |||
| 4329 | Result = lowerRangeToAssertZExt(DAG, I, Result); | |||
| 4330 | ||||
| 4331 | setValue(&I, Result); | |||
| 4332 | } | |||
| 4333 | } | |||
| 4334 | ||||
| 4335 | /// GetSignificand - Get the significand and build it into a floating-point | |||
| 4336 | /// number with exponent of 1: | |||
| 4337 | /// | |||
| 4338 | /// Op = (Op & 0x007fffff) | 0x3f800000; | |||
| 4339 | /// | |||
| 4340 | /// where Op is the hexadecimal representation of floating point value. | |||
| 4341 | static SDValue GetSignificand(SelectionDAG &DAG, SDValue Op, const SDLoc &dl) { | |||
| 4342 | SDValue t1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op, | |||
| 4343 | DAG.getConstant(0x007fffff, dl, MVT::i32)); | |||
| 4344 | SDValue t2 = DAG.getNode(ISD::OR, dl, MVT::i32, t1, | |||
| 4345 | DAG.getConstant(0x3f800000, dl, MVT::i32)); | |||
| 4346 | return DAG.getNode(ISD::BITCAST, dl, MVT::f32, t2); | |||
| 4347 | } | |||
| 4348 | ||||
| 4349 | /// GetExponent - Get the exponent: | |||
| 4350 | /// | |||
| 4351 | /// (float)(int)(((Op & 0x7f800000) >> 23) - 127); | |||
| 4352 | /// | |||
| 4353 | /// where Op is the hexadecimal representation of floating point value. | |||
| 4354 | static SDValue GetExponent(SelectionDAG &DAG, SDValue Op, | |||
| 4355 | const TargetLowering &TLI, const SDLoc &dl) { | |||
| 4356 | SDValue t0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op, | |||
| 4357 | DAG.getConstant(0x7f800000, dl, MVT::i32)); | |||
| 4358 | SDValue t1 = DAG.getNode( | |||
| 4359 | ISD::SRL, dl, MVT::i32, t0, | |||
| 4360 | DAG.getConstant(23, dl, TLI.getPointerTy(DAG.getDataLayout()))); | |||
| 4361 | SDValue t2 = DAG.getNode(ISD::SUB, dl, MVT::i32, t1, | |||
| 4362 | DAG.getConstant(127, dl, MVT::i32)); | |||
| 4363 | return DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, t2); | |||
| 4364 | } | |||
| 4365 | ||||
| 4366 | /// getF32Constant - Get 32-bit floating point constant. | |||
| 4367 | static SDValue getF32Constant(SelectionDAG &DAG, unsigned Flt, | |||
| 4368 | const SDLoc &dl) { | |||
| 4369 | return DAG.getConstantFP(APFloat(APFloat::IEEEsingle(), APInt(32, Flt)), dl, | |||
| 4370 | MVT::f32); | |||
| 4371 | } | |||
| 4372 | ||||
| 4373 | static SDValue getLimitedPrecisionExp2(SDValue t0, const SDLoc &dl, | |||
| 4374 | SelectionDAG &DAG) { | |||
| 4375 | // TODO: What fast-math-flags should be set on the floating-point nodes? | |||
| 4376 | ||||
| 4377 | // IntegerPartOfX = ((int32_t)(t0); | |||
| 4378 | SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0); | |||
| 4379 | ||||
| 4380 | // FractionalPartOfX = t0 - (float)IntegerPartOfX; | |||
| 4381 | SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX); | |||
| 4382 | SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1); | |||
| 4383 | ||||
| 4384 | // IntegerPartOfX <<= 23; | |||
| 4385 | IntegerPartOfX = DAG.getNode( | |||
| 4386 | ISD::SHL, dl, MVT::i32, IntegerPartOfX, | |||
| 4387 | DAG.getConstant(23, dl, DAG.getTargetLoweringInfo().getPointerTy( | |||
| 4388 | DAG.getDataLayout()))); | |||
| 4389 | ||||
| 4390 | SDValue TwoToFractionalPartOfX; | |||
| 4391 | if (LimitFloatPrecision <= 6) { | |||
| 4392 | // For floating-point precision of 6: | |||
| 4393 | // | |||
| 4394 | // TwoToFractionalPartOfX = | |||
| 4395 | // 0.997535578f + | |||
| 4396 | // (0.735607626f + 0.252464424f * x) * x; | |||
| 4397 | // | |||
| 4398 | // error 0.0144103317, which is 6 bits | |||
| 4399 | SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, | |||
| 4400 | getF32Constant(DAG, 0x3e814304, dl)); | |||
| 4401 | SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, | |||
| 4402 | getF32Constant(DAG, 0x3f3c50c8, dl)); | |||
| 4403 | SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); | |||
| 4404 | TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, | |||
| 4405 | getF32Constant(DAG, 0x3f7f5e7e, dl)); | |||
| 4406 | } else if (LimitFloatPrecision <= 12) { | |||
| 4407 | // For floating-point precision of 12: | |||
| 4408 | // | |||
| 4409 | // TwoToFractionalPartOfX = | |||
| 4410 | // 0.999892986f + | |||
| 4411 | // (0.696457318f + | |||
| 4412 | // (0.224338339f + 0.792043434e-1f * x) * x) * x; | |||
| 4413 | // | |||
| 4414 | // error 0.000107046256, which is 13 to 14 bits | |||
| 4415 | SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, | |||
| 4416 | getF32Constant(DAG, 0x3da235e3, dl)); | |||
| 4417 | SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, | |||
| 4418 | getF32Constant(DAG, 0x3e65b8f3, dl)); | |||
| 4419 | SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); | |||
| 4420 | SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, | |||
| 4421 | getF32Constant(DAG, 0x3f324b07, dl)); | |||
| 4422 | SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); | |||
| 4423 | TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, | |||
| 4424 | getF32Constant(DAG, 0x3f7ff8fd, dl)); | |||
| 4425 | } else { // LimitFloatPrecision <= 18 | |||
| 4426 | // For floating-point precision of 18: | |||
| 4427 | // | |||
| 4428 | // TwoToFractionalPartOfX = | |||
| 4429 | // 0.999999982f + | |||
| 4430 | // (0.693148872f + | |||
| 4431 | // (0.240227044f + | |||
| 4432 | // (0.554906021e-1f + | |||
| 4433 | // (0.961591928e-2f + | |||
| 4434 | // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x; | |||
| 4435 | // error 2.47208000*10^(-7), which is better than 18 bits | |||
| 4436 | SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, | |||
| 4437 | getF32Constant(DAG, 0x3924b03e, dl)); | |||
| 4438 | SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, | |||
| 4439 | getF32Constant(DAG, 0x3ab24b87, dl)); | |||
| 4440 | SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); | |||
| 4441 | SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, | |||
| 4442 | getF32Constant(DAG, 0x3c1d8c17, dl)); | |||
| 4443 | SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); | |||
| 4444 | SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, | |||
| 4445 | getF32Constant(DAG, 0x3d634a1d, dl)); | |||
| 4446 | SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); | |||
| 4447 | SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, | |||
| 4448 | getF32Constant(DAG, 0x3e75fe14, dl)); | |||
| 4449 | SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); | |||
| 4450 | SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10, | |||
| 4451 | getF32Constant(DAG, 0x3f317234, dl)); | |||
| 4452 | SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X); | |||
| 4453 | TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t12, | |||
| 4454 | getF32Constant(DAG, 0x3f800000, dl)); | |||
| 4455 | } | |||
| 4456 | ||||
| 4457 | // Add the exponent into the result in integer domain. | |||
| 4458 | SDValue t13 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, TwoToFractionalPartOfX); | |||
| 4459 | return DAG.getNode(ISD::BITCAST, dl, MVT::f32, | |||
| 4460 | DAG.getNode(ISD::ADD, dl, MVT::i32, t13, IntegerPartOfX)); | |||
| 4461 | } | |||
| 4462 | ||||
| 4463 | /// expandExp - Lower an exp intrinsic. Handles the special sequences for | |||
| 4464 | /// limited-precision mode. | |||
| 4465 | static SDValue expandExp(const SDLoc &dl, SDValue Op, SelectionDAG &DAG, | |||
| 4466 | const TargetLowering &TLI) { | |||
| 4467 | if (Op.getValueType() == MVT::f32 && | |||
| 4468 | LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { | |||
| 4469 | ||||
| 4470 | // Put the exponent in the right bit position for later addition to the | |||
| 4471 | // final result: | |||
| 4472 | // | |||
| 4473 | // #define LOG2OFe 1.4426950f | |||
| 4474 | // t0 = Op * LOG2OFe | |||
| 4475 | ||||
| 4476 | // TODO: What fast-math-flags should be set here? | |||
| 4477 | SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op, | |||
| 4478 | getF32Constant(DAG, 0x3fb8aa3b, dl)); | |||
| 4479 | return getLimitedPrecisionExp2(t0, dl, DAG); | |||
| 4480 | } | |||
| 4481 | ||||
| 4482 | // No special expansion. | |||
| 4483 | return DAG.getNode(ISD::FEXP, dl, Op.getValueType(), Op); | |||
| 4484 | } | |||
| 4485 | ||||
| 4486 | /// expandLog - Lower a log intrinsic. Handles the special sequences for | |||
| 4487 | /// limited-precision mode. | |||
| 4488 | static SDValue expandLog(const SDLoc &dl, SDValue Op, SelectionDAG &DAG, | |||
| 4489 | const TargetLowering &TLI) { | |||
| 4490 | // TODO: What fast-math-flags should be set on the floating-point nodes? | |||
| 4491 | ||||
| 4492 | if (Op.getValueType() == MVT::f32 && | |||
| 4493 | LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { | |||
| 4494 | SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op); | |||
| 4495 | ||||
| 4496 | // Scale the exponent by log(2) [0.69314718f]. | |||
| 4497 | SDValue Exp = GetExponent(DAG, Op1, TLI, dl); | |||
| 4498 | SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp, | |||
| 4499 | getF32Constant(DAG, 0x3f317218, dl)); | |||
| 4500 | ||||
| 4501 | // Get the significand and build it into a floating-point number with | |||
| 4502 | // exponent of 1. | |||
| 4503 | SDValue X = GetSignificand(DAG, Op1, dl); | |||
| 4504 | ||||
| 4505 | SDValue LogOfMantissa; | |||
| 4506 | if (LimitFloatPrecision <= 6) { | |||
| 4507 | // For floating-point precision of 6: | |||
| 4508 | // | |||
| 4509 | // LogofMantissa = | |||
| 4510 | // -1.1609546f + | |||
| 4511 | // (1.4034025f - 0.23903021f * x) * x; | |||
| 4512 | // | |||
| 4513 | // error 0.0034276066, which is better than 8 bits | |||
| 4514 | SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, | |||
| 4515 | getF32Constant(DAG, 0xbe74c456, dl)); | |||
| 4516 | SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, | |||
| 4517 | getF32Constant(DAG, 0x3fb3a2b1, dl)); | |||
| 4518 | SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); | |||
| 4519 | LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, | |||
| 4520 | getF32Constant(DAG, 0x3f949a29, dl)); | |||
| 4521 | } else if (LimitFloatPrecision <= 12) { | |||
| 4522 | // For floating-point precision of 12: | |||
| 4523 | // | |||
| 4524 | // LogOfMantissa = | |||
| 4525 | // -1.7417939f + | |||
| 4526 | // (2.8212026f + | |||
| 4527 | // (-1.4699568f + | |||
| 4528 | // (0.44717955f - 0.56570851e-1f * x) * x) * x) * x; | |||
| 4529 | // | |||
| 4530 | // error 0.000061011436, which is 14 bits | |||
| 4531 | SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, | |||
| 4532 | getF32Constant(DAG, 0xbd67b6d6, dl)); | |||
| 4533 | SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, | |||
| 4534 | getF32Constant(DAG, 0x3ee4f4b8, dl)); | |||
| 4535 | SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); | |||
| 4536 | SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, | |||
| 4537 | getF32Constant(DAG, 0x3fbc278b, dl)); | |||
| 4538 | SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); | |||
| 4539 | SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, | |||
| 4540 | getF32Constant(DAG, 0x40348e95, dl)); | |||
| 4541 | SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); | |||
| 4542 | LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, | |||
| 4543 | getF32Constant(DAG, 0x3fdef31a, dl)); | |||
| 4544 | } else { // LimitFloatPrecision <= 18 | |||
| 4545 | // For floating-point precision of 18: | |||
| 4546 | // | |||
| 4547 | // LogOfMantissa = | |||
| 4548 | // -2.1072184f + | |||
| 4549 | // (4.2372794f + | |||
| 4550 | // (-3.7029485f + | |||
| 4551 | // (2.2781945f + | |||
| 4552 | // (-0.87823314f + | |||
| 4553 | // (0.19073739f - 0.17809712e-1f * x) * x) * x) * x) * x)*x; | |||
| 4554 | // | |||
| 4555 | // error 0.0000023660568, which is better than 18 bits | |||
| 4556 | SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, | |||
| 4557 | getF32Constant(DAG, 0xbc91e5ac, dl)); | |||
| 4558 | SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, | |||
| 4559 | getF32Constant(DAG, 0x3e4350aa, dl)); | |||
| 4560 | SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); | |||
| 4561 | SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, | |||
| 4562 | getF32Constant(DAG, 0x3f60d3e3, dl)); | |||
| 4563 | SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); | |||
| 4564 | SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, | |||
| 4565 | getF32Constant(DAG, 0x4011cdf0, dl)); | |||
| 4566 | SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); | |||
| 4567 | SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, | |||
| 4568 | getF32Constant(DAG, 0x406cfd1c, dl)); | |||
| 4569 | SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); | |||
| 4570 | SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, | |||
| 4571 | getF32Constant(DAG, 0x408797cb, dl)); | |||
| 4572 | SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); | |||
| 4573 | LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10, | |||
| 4574 | getF32Constant(DAG, 0x4006dcab, dl)); | |||
| 4575 | } | |||
| 4576 | ||||
| 4577 | return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, LogOfMantissa); | |||
| 4578 | } | |||
| 4579 | ||||
| 4580 | // No special expansion. | |||
| 4581 | return DAG.getNode(ISD::FLOG, dl, Op.getValueType(), Op); | |||
| 4582 | } | |||
| 4583 | ||||
| 4584 | /// expandLog2 - Lower a log2 intrinsic. Handles the special sequences for | |||
| 4585 | /// limited-precision mode. | |||
| 4586 | static SDValue expandLog2(const SDLoc &dl, SDValue Op, SelectionDAG &DAG, | |||
| 4587 | const TargetLowering &TLI) { | |||
| 4588 | // TODO: What fast-math-flags should be set on the floating-point nodes? | |||
| 4589 | ||||
| 4590 | if (Op.getValueType() == MVT::f32 && | |||
| 4591 | LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { | |||
| 4592 | SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op); | |||
| 4593 | ||||
| 4594 | // Get the exponent. | |||
| 4595 | SDValue LogOfExponent = GetExponent(DAG, Op1, TLI, dl); | |||
| 4596 | ||||
| 4597 | // Get the significand and build it into a floating-point number with | |||
| 4598 | // exponent of 1. | |||
| 4599 | SDValue X = GetSignificand(DAG, Op1, dl); | |||
| 4600 | ||||
| 4601 | // Different possible minimax approximations of significand in | |||
| 4602 | // floating-point for various degrees of accuracy over [1,2]. | |||
| 4603 | SDValue Log2ofMantissa; | |||
| 4604 | if (LimitFloatPrecision <= 6) { | |||
| 4605 | // For floating-point precision of 6: | |||
| 4606 | // | |||
| 4607 | // Log2ofMantissa = -1.6749035f + (2.0246817f - .34484768f * x) * x; | |||
| 4608 | // | |||
| 4609 | // error 0.0049451742, which is more than 7 bits | |||
| 4610 | SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, | |||
| 4611 | getF32Constant(DAG, 0xbeb08fe0, dl)); | |||
| 4612 | SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, | |||
| 4613 | getF32Constant(DAG, 0x40019463, dl)); | |||
| 4614 | SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); | |||
| 4615 | Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, | |||
| 4616 | getF32Constant(DAG, 0x3fd6633d, dl)); | |||
| 4617 | } else if (LimitFloatPrecision <= 12) { | |||
| 4618 | // For floating-point precision of 12: | |||
| 4619 | // | |||
| 4620 | // Log2ofMantissa = | |||
| 4621 | // -2.51285454f + | |||
| 4622 | // (4.07009056f + | |||
| 4623 | // (-2.12067489f + | |||
| 4624 | // (.645142248f - 0.816157886e-1f * x) * x) * x) * x; | |||
| 4625 | // | |||
| 4626 | // error 0.0000876136000, which is better than 13 bits | |||
| 4627 | SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, | |||
| 4628 | getF32Constant(DAG, 0xbda7262e, dl)); | |||
| 4629 | SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, | |||
| 4630 | getF32Constant(DAG, 0x3f25280b, dl)); | |||
| 4631 | SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); | |||
| 4632 | SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, | |||
| 4633 | getF32Constant(DAG, 0x4007b923, dl)); | |||
| 4634 | SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); | |||
| 4635 | SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, | |||
| 4636 | getF32Constant(DAG, 0x40823e2f, dl)); | |||
| 4637 | SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); | |||
| 4638 | Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, | |||
| 4639 | getF32Constant(DAG, 0x4020d29c, dl)); | |||
| 4640 | } else { // LimitFloatPrecision <= 18 | |||
| 4641 | // For floating-point precision of 18: | |||
| 4642 | // | |||
| 4643 | // Log2ofMantissa = | |||
| 4644 | // -3.0400495f + | |||
| 4645 | // (6.1129976f + | |||
| 4646 | // (-5.3420409f + | |||
| 4647 | // (3.2865683f + | |||
| 4648 | // (-1.2669343f + | |||
| 4649 | // (0.27515199f - | |||
| 4650 | // 0.25691327e-1f * x) * x) * x) * x) * x) * x; | |||
| 4651 | // | |||
| 4652 | // error 0.0000018516, which is better than 18 bits | |||
| 4653 | SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, | |||
| 4654 | getF32Constant(DAG, 0xbcd2769e, dl)); | |||
| 4655 | SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, | |||
| 4656 | getF32Constant(DAG, 0x3e8ce0b9, dl)); | |||
| 4657 | SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); | |||
| 4658 | SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, | |||
| 4659 | getF32Constant(DAG, 0x3fa22ae7, dl)); | |||
| 4660 | SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); | |||
| 4661 | SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, | |||
| 4662 | getF32Constant(DAG, 0x40525723, dl)); | |||
| 4663 | SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); | |||
| 4664 | SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, | |||
| 4665 | getF32Constant(DAG, 0x40aaf200, dl)); | |||
| 4666 | SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); | |||
| 4667 | SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, | |||
| 4668 | getF32Constant(DAG, 0x40c39dad, dl)); | |||
| 4669 | SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); | |||
| 4670 | Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10, | |||
| 4671 | getF32Constant(DAG, 0x4042902c, dl)); | |||
| 4672 | } | |||
| 4673 | ||||
| 4674 | return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, Log2ofMantissa); | |||
| 4675 | } | |||
| 4676 | ||||
| 4677 | // No special expansion. | |||
| 4678 | return DAG.getNode(ISD::FLOG2, dl, Op.getValueType(), Op); | |||
| 4679 | } | |||
| 4680 | ||||
| 4681 | /// expandLog10 - Lower a log10 intrinsic. Handles the special sequences for | |||
| 4682 | /// limited-precision mode. | |||
| 4683 | static SDValue expandLog10(const SDLoc &dl, SDValue Op, SelectionDAG &DAG, | |||
| 4684 | const TargetLowering &TLI) { | |||
| 4685 | // TODO: What fast-math-flags should be set on the floating-point nodes? | |||
| 4686 | ||||
| 4687 | if (Op.getValueType() == MVT::f32 && | |||
| 4688 | LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { | |||
| 4689 | SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op); | |||
| 4690 | ||||
| 4691 | // Scale the exponent by log10(2) [0.30102999f]. | |||
| 4692 | SDValue Exp = GetExponent(DAG, Op1, TLI, dl); | |||
| 4693 | SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp, | |||
| 4694 | getF32Constant(DAG, 0x3e9a209a, dl)); | |||
| 4695 | ||||
| 4696 | // Get the significand and build it into a floating-point number with | |||
| 4697 | // exponent of 1. | |||
| 4698 | SDValue X = GetSignificand(DAG, Op1, dl); | |||
| 4699 | ||||
| 4700 | SDValue Log10ofMantissa; | |||
| 4701 | if (LimitFloatPrecision <= 6) { | |||
| 4702 | // For floating-point precision of 6: | |||
| 4703 | // | |||
| 4704 | // Log10ofMantissa = | |||
| 4705 | // -0.50419619f + | |||
| 4706 | // (0.60948995f - 0.10380950f * x) * x; | |||
| 4707 | // | |||
| 4708 | // error 0.0014886165, which is 6 bits | |||
| 4709 | SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, | |||
| 4710 | getF32Constant(DAG, 0xbdd49a13, dl)); | |||
| 4711 | SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, | |||
| 4712 | getF32Constant(DAG, 0x3f1c0789, dl)); | |||
| 4713 | SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); | |||
| 4714 | Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, | |||
| 4715 | getF32Constant(DAG, 0x3f011300, dl)); | |||
| 4716 | } else if (LimitFloatPrecision <= 12) { | |||
| 4717 | // For floating-point precision of 12: | |||
| 4718 | // | |||
| 4719 | // Log10ofMantissa = | |||
| 4720 | // -0.64831180f + | |||
| 4721 | // (0.91751397f + | |||
| 4722 | // (-0.31664806f + 0.47637168e-1f * x) * x) * x; | |||
| 4723 | // | |||
| 4724 | // error 0.00019228036, which is better than 12 bits | |||
| 4725 | SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, | |||
| 4726 | getF32Constant(DAG, 0x3d431f31, dl)); | |||
| 4727 | SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, | |||
| 4728 | getF32Constant(DAG, 0x3ea21fb2, dl)); | |||
| 4729 | SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); | |||
| 4730 | SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, | |||
| 4731 | getF32Constant(DAG, 0x3f6ae232, dl)); | |||
| 4732 | SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); | |||
| 4733 | Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4, | |||
| 4734 | getF32Constant(DAG, 0x3f25f7c3, dl)); | |||
| 4735 | } else { // LimitFloatPrecision <= 18 | |||
| 4736 | // For floating-point precision of 18: | |||
| 4737 | // | |||
| 4738 | // Log10ofMantissa = | |||
| 4739 | // -0.84299375f + | |||
| 4740 | // (1.5327582f + | |||
| 4741 | // (-1.0688956f + | |||
| 4742 | // (0.49102474f + | |||
| 4743 | // (-0.12539807f + 0.13508273e-1f * x) * x) * x) * x) * x; | |||
| 4744 | // | |||
| 4745 | // error 0.0000037995730, which is better than 18 bits | |||
| 4746 | SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, | |||
| 4747 | getF32Constant(DAG, 0x3c5d51ce, dl)); | |||
| 4748 | SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, | |||
| 4749 | getF32Constant(DAG, 0x3e00685a, dl)); | |||
| 4750 | SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); | |||
| 4751 | SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, | |||
| 4752 | getF32Constant(DAG, 0x3efb6798, dl)); | |||
| 4753 | SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); | |||
| 4754 | SDValue t5 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4, | |||
| 4755 | getF32Constant(DAG, 0x3f88d192, dl)); | |||
| 4756 | SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); | |||
| 4757 | SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, | |||
| 4758 | getF32Constant(DAG, 0x3fc4316c, dl)); | |||
| 4759 | SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); | |||
| 4760 | Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t8, | |||
| 4761 | getF32Constant(DAG, 0x3f57ce70, dl)); | |||
| 4762 | } | |||
| 4763 | ||||
| 4764 | return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, Log10ofMantissa); | |||
| 4765 | } | |||
| 4766 | ||||
| 4767 | // No special expansion. | |||
| 4768 | return DAG.getNode(ISD::FLOG10, dl, Op.getValueType(), Op); | |||
| 4769 | } | |||
| 4770 | ||||
| 4771 | /// expandExp2 - Lower an exp2 intrinsic. Handles the special sequences for | |||
| 4772 | /// limited-precision mode. | |||
| 4773 | static SDValue expandExp2(const SDLoc &dl, SDValue Op, SelectionDAG &DAG, | |||
| 4774 | const TargetLowering &TLI) { | |||
| 4775 | if (Op.getValueType() == MVT::f32 && | |||
| 4776 | LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) | |||
| 4777 | return getLimitedPrecisionExp2(Op, dl, DAG); | |||
| 4778 | ||||
| 4779 | // No special expansion. | |||
| 4780 | return DAG.getNode(ISD::FEXP2, dl, Op.getValueType(), Op); | |||
| 4781 | } | |||
| 4782 | ||||
| 4783 | /// visitPow - Lower a pow intrinsic. Handles the special sequences for | |||
| 4784 | /// limited-precision mode with x == 10.0f. | |||
| 4785 | static SDValue expandPow(const SDLoc &dl, SDValue LHS, SDValue RHS, | |||
| 4786 | SelectionDAG &DAG, const TargetLowering &TLI) { | |||
| 4787 | bool IsExp10 = false; | |||
| 4788 | if (LHS.getValueType() == MVT::f32 && RHS.getValueType() == MVT::f32 && | |||
| 4789 | LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { | |||
| 4790 | if (ConstantFPSDNode *LHSC = dyn_cast<ConstantFPSDNode>(LHS)) { | |||
| 4791 | APFloat Ten(10.0f); | |||
| 4792 | IsExp10 = LHSC->isExactlyValue(Ten); | |||
| 4793 | } | |||
| 4794 | } | |||
| 4795 | ||||
| 4796 | // TODO: What fast-math-flags should be set on the FMUL node? | |||
| 4797 | if (IsExp10) { | |||
| 4798 | // Put the exponent in the right bit position for later addition to the | |||
| 4799 | // final result: | |||
| 4800 | // | |||
| 4801 | // #define LOG2OF10 3.3219281f | |||
| 4802 | // t0 = Op * LOG2OF10; | |||
| 4803 | SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, RHS, | |||
| 4804 | getF32Constant(DAG, 0x40549a78, dl)); | |||
| 4805 | return getLimitedPrecisionExp2(t0, dl, DAG); | |||
| 4806 | } | |||
| 4807 | ||||
| 4808 | // No special expansion. | |||
| 4809 | return DAG.getNode(ISD::FPOW, dl, LHS.getValueType(), LHS, RHS); | |||
| 4810 | } | |||
| 4811 | ||||
| 4812 | /// ExpandPowI - Expand a llvm.powi intrinsic. | |||
| 4813 | static SDValue ExpandPowI(const SDLoc &DL, SDValue LHS, SDValue RHS, | |||
| 4814 | SelectionDAG &DAG) { | |||
| 4815 | // If RHS is a constant, we can expand this out to a multiplication tree, | |||
| 4816 | // otherwise we end up lowering to a call to __powidf2 (for example). When | |||
| 4817 | // optimizing for size, we only want to do this if the expansion would produce | |||
| 4818 | // a small number of multiplies, otherwise we do the full expansion. | |||
| 4819 | if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) { | |||
| 4820 | // Get the exponent as a positive value. | |||
| 4821 | unsigned Val = RHSC->getSExtValue(); | |||
| 4822 | if ((int)Val < 0) Val = -Val; | |||
| 4823 | ||||
| 4824 | // powi(x, 0) -> 1.0 | |||
| 4825 | if (Val == 0) | |||
| 4826 | return DAG.getConstantFP(1.0, DL, LHS.getValueType()); | |||
| 4827 | ||||
| 4828 | const Function &F = DAG.getMachineFunction().getFunction(); | |||
| 4829 | if (!F.optForSize() || | |||
| 4830 | // If optimizing for size, don't insert too many multiplies. | |||
| 4831 | // This inserts up to 5 multiplies. | |||
| 4832 | countPopulation(Val) + Log2_32(Val) < 7) { | |||
| 4833 | // We use the simple binary decomposition method to generate the multiply | |||
| 4834 | // sequence. There are more optimal ways to do this (for example, | |||
| 4835 | // powi(x,15) generates one more multiply than it should), but this has | |||
| 4836 | // the benefit of being both really simple and much better than a libcall. | |||
| 4837 | SDValue Res; // Logically starts equal to 1.0 | |||
| 4838 | SDValue CurSquare = LHS; | |||
| 4839 | // TODO: Intrinsics should have fast-math-flags that propagate to these | |||
| 4840 | // nodes. | |||
| 4841 | while (Val) { | |||
| 4842 | if (Val & 1) { | |||
| 4843 | if (Res.getNode()) | |||
| 4844 | Res = DAG.getNode(ISD::FMUL, DL,Res.getValueType(), Res, CurSquare); | |||
| 4845 | else | |||
| 4846 | Res = CurSquare; // 1.0*CurSquare. | |||
| 4847 | } | |||
| 4848 | ||||
| 4849 | CurSquare = DAG.getNode(ISD::FMUL, DL, CurSquare.getValueType(), | |||
| 4850 | CurSquare, CurSquare); | |||
| 4851 | Val >>= 1; | |||
| 4852 | } | |||
| 4853 | ||||
| 4854 | // If the original was negative, invert the result, producing 1/(x*x*x). | |||
| 4855 | if (RHSC->getSExtValue() < 0) | |||
| 4856 | Res = DAG.getNode(ISD::FDIV, DL, LHS.getValueType(), | |||
| 4857 | DAG.getConstantFP(1.0, DL, LHS.getValueType()), Res); | |||
| 4858 | return Res; | |||
| 4859 | } | |||
| 4860 | } | |||
| 4861 | ||||
| 4862 | // Otherwise, expand to a libcall. | |||
| 4863 | return DAG.getNode(ISD::FPOWI, DL, LHS.getValueType(), LHS, RHS); | |||
| 4864 | } | |||
| 4865 | ||||
| 4866 | // getUnderlyingArgReg - Find underlying register used for a truncated or | |||
| 4867 | // bitcasted argument. | |||
| 4868 | static unsigned getUnderlyingArgReg(const SDValue &N) { | |||
| 4869 | switch (N.getOpcode()) { | |||
| 4870 | case ISD::CopyFromReg: | |||
| 4871 | return cast<RegisterSDNode>(N.getOperand(1))->getReg(); | |||
| 4872 | case ISD::BITCAST: | |||
| 4873 | case ISD::AssertZext: | |||
| 4874 | case ISD::AssertSext: | |||
| 4875 | case ISD::TRUNCATE: | |||
| 4876 | return getUnderlyingArgReg(N.getOperand(0)); | |||
| 4877 | default: | |||
| 4878 | return 0; | |||
| 4879 | } | |||
| 4880 | } | |||
| 4881 | ||||
| 4882 | /// If the DbgValueInst is a dbg_value of a function argument, create the | |||
| 4883 | /// corresponding DBG_VALUE machine instruction for it now. At the end of | |||
| 4884 | /// instruction selection, they will be inserted to the entry BB. | |||
| 4885 | bool SelectionDAGBuilder::EmitFuncArgumentDbgValue( | |||
| 4886 | const Value *V, DILocalVariable *Variable, DIExpression *Expr, | |||
| 4887 | DILocation *DL, bool IsDbgDeclare, const SDValue &N) { | |||
| 4888 | const Argument *Arg = dyn_cast<Argument>(V); | |||
| 4889 | if (!Arg) | |||
| 4890 | return false; | |||
| 4891 | ||||
| 4892 | MachineFunction &MF = DAG.getMachineFunction(); | |||
| 4893 | const TargetInstrInfo *TII = DAG.getSubtarget().getInstrInfo(); | |||
| 4894 | ||||
| 4895 | bool IsIndirect = false; | |||
| 4896 | Optional<MachineOperand> Op; | |||
| 4897 | // Some arguments' frame index is recorded during argument lowering. | |||
| 4898 | int FI = FuncInfo.getArgumentFrameIndex(Arg); | |||
| 4899 | if (FI != std::numeric_limits<int>::max()) | |||
| 4900 | Op = MachineOperand::CreateFI(FI); | |||
| 4901 | ||||
| 4902 | if (!Op && N.getNode()) { | |||
| 4903 | unsigned Reg = getUnderlyingArgReg(N); | |||
| 4904 | if (Reg && TargetRegisterInfo::isVirtualRegister(Reg)) { | |||
| 4905 | MachineRegisterInfo &RegInfo = MF.getRegInfo(); | |||
| 4906 | unsigned PR = RegInfo.getLiveInPhysReg(Reg); | |||
| 4907 | if (PR) | |||
| 4908 | Reg = PR; | |||
| 4909 | } | |||
| 4910 | if (Reg) { | |||
| 4911 | Op = MachineOperand::CreateReg(Reg, false); | |||
| 4912 | IsIndirect = IsDbgDeclare; | |||
| 4913 | } | |||
| 4914 | } | |||
| 4915 | ||||
| 4916 | if (!Op && N.getNode()) | |||
| 4917 | // Check if frame index is available. | |||
| 4918 | if (LoadSDNode *LNode = dyn_cast<LoadSDNode>(N.getNode())) | |||
| 4919 | if (FrameIndexSDNode *FINode = | |||
| 4920 | dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode())) | |||
| 4921 | Op = MachineOperand::CreateFI(FINode->getIndex()); | |||
| 4922 | ||||
| 4923 | if (!Op) { | |||
| 4924 | // Check if ValueMap has reg number. | |||
| 4925 | DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V); | |||
| 4926 | if (VMI != FuncInfo.ValueMap.end()) { | |||
| 4927 | const auto &TLI = DAG.getTargetLoweringInfo(); | |||
| 4928 | RegsForValue RFV(V->getContext(), TLI, DAG.getDataLayout(), VMI->second, | |||
| 4929 | V->getType(), isABIRegCopy(V)); | |||
| 4930 | if (RFV.occupiesMultipleRegs()) { | |||
| 4931 | unsigned Offset = 0; | |||
| 4932 | for (auto RegAndSize : RFV.getRegsAndSizes()) { | |||
| 4933 | Op = MachineOperand::CreateReg(RegAndSize.first, false); | |||
| 4934 | auto FragmentExpr = DIExpression::createFragmentExpression( | |||
| 4935 | Expr, Offset, RegAndSize.second); | |||
| 4936 | if (!FragmentExpr) | |||
| 4937 | continue; | |||
| 4938 | FuncInfo.ArgDbgValues.push_back( | |||
| 4939 | BuildMI(MF, DL, TII->get(TargetOpcode::DBG_VALUE), IsDbgDeclare, | |||
| 4940 | Op->getReg(), Variable, *FragmentExpr)); | |||
| 4941 | Offset += RegAndSize.second; | |||
| 4942 | } | |||
| 4943 | return true; | |||
| 4944 | } | |||
| 4945 | Op = MachineOperand::CreateReg(VMI->second, false); | |||
| 4946 | IsIndirect = IsDbgDeclare; | |||
| 4947 | } | |||
| 4948 | } | |||
| 4949 | ||||
| 4950 | if (!Op) | |||
| 4951 | return false; | |||
| 4952 | ||||
| 4953 | assert(Variable->isValidLocationForIntrinsic(DL) &&(static_cast <bool> (Variable->isValidLocationForIntrinsic (DL) && "Expected inlined-at fields to agree") ? void (0) : __assert_fail ("Variable->isValidLocationForIntrinsic(DL) && \"Expected inlined-at fields to agree\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 4954, __extension__ __PRETTY_FUNCTION__)) | |||
| 4954 | "Expected inlined-at fields to agree")(static_cast <bool> (Variable->isValidLocationForIntrinsic (DL) && "Expected inlined-at fields to agree") ? void (0) : __assert_fail ("Variable->isValidLocationForIntrinsic(DL) && \"Expected inlined-at fields to agree\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 4954, __extension__ __PRETTY_FUNCTION__)); | |||
| 4955 | IsIndirect = (Op->isReg()) ? IsIndirect : true; | |||
| 4956 | FuncInfo.ArgDbgValues.push_back( | |||
| 4957 | BuildMI(MF, DL, TII->get(TargetOpcode::DBG_VALUE), IsIndirect, | |||
| 4958 | *Op, Variable, Expr)); | |||
| 4959 | ||||
| 4960 | return true; | |||
| 4961 | } | |||
| 4962 | ||||
| 4963 | /// Return the appropriate SDDbgValue based on N. | |||
| 4964 | SDDbgValue *SelectionDAGBuilder::getDbgValue(SDValue N, | |||
| 4965 | DILocalVariable *Variable, | |||
| 4966 | DIExpression *Expr, | |||
| 4967 | const DebugLoc &dl, | |||
| 4968 | unsigned DbgSDNodeOrder) { | |||
| 4969 | if (auto *FISDN = dyn_cast<FrameIndexSDNode>(N.getNode())) { | |||
| 4970 | // Construct a FrameIndexDbgValue for FrameIndexSDNodes so we can describe | |||
| 4971 | // stack slot locations as such instead of as indirectly addressed | |||
| 4972 | // locations. | |||
| 4973 | return DAG.getFrameIndexDbgValue(Variable, Expr, FISDN->getIndex(), dl, | |||
| 4974 | DbgSDNodeOrder); | |||
| 4975 | } | |||
| 4976 | return DAG.getDbgValue(Variable, Expr, N.getNode(), N.getResNo(), false, dl, | |||
| 4977 | DbgSDNodeOrder); | |||
| 4978 | } | |||
| 4979 | ||||
| 4980 | // VisualStudio defines setjmp as _setjmp | |||
| 4981 | #if defined(_MSC_VER) && defined(setjmp) && \ | |||
| 4982 | !defined(setjmp_undefined_for_msvc) | |||
| 4983 | # pragma push_macro("setjmp") | |||
| 4984 | # undef setjmp | |||
| 4985 | # define setjmp_undefined_for_msvc | |||
| 4986 | #endif | |||
| 4987 | ||||
| 4988 | /// Lower the call to the specified intrinsic function. If we want to emit this | |||
| 4989 | /// as a call to a named external function, return the name. Otherwise, lower it | |||
| 4990 | /// and return null. | |||
| 4991 | const char * | |||
| 4992 | SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, unsigned Intrinsic) { | |||
| 4993 | const TargetLowering &TLI = DAG.getTargetLoweringInfo(); | |||
| 4994 | SDLoc sdl = getCurSDLoc(); | |||
| 4995 | DebugLoc dl = getCurDebugLoc(); | |||
| 4996 | SDValue Res; | |||
| 4997 | ||||
| 4998 | switch (Intrinsic) { | |||
| 4999 | default: | |||
| 5000 | // By default, turn this into a target intrinsic node. | |||
| 5001 | visitTargetIntrinsic(I, Intrinsic); | |||
| 5002 | return nullptr; | |||
| 5003 | case Intrinsic::vastart: visitVAStart(I); return nullptr; | |||
| 5004 | case Intrinsic::vaend: visitVAEnd(I); return nullptr; | |||
| 5005 | case Intrinsic::vacopy: visitVACopy(I); return nullptr; | |||
| 5006 | case Intrinsic::returnaddress: | |||
| 5007 | setValue(&I, DAG.getNode(ISD::RETURNADDR, sdl, | |||
| 5008 | TLI.getPointerTy(DAG.getDataLayout()), | |||
| 5009 | getValue(I.getArgOperand(0)))); | |||
| 5010 | return nullptr; | |||
| 5011 | case Intrinsic::addressofreturnaddress: | |||
| 5012 | setValue(&I, DAG.getNode(ISD::ADDROFRETURNADDR, sdl, | |||
| 5013 | TLI.getPointerTy(DAG.getDataLayout()))); | |||
| 5014 | return nullptr; | |||
| 5015 | case Intrinsic::frameaddress: | |||
| 5016 | setValue(&I, DAG.getNode(ISD::FRAMEADDR, sdl, | |||
| 5017 | TLI.getPointerTy(DAG.getDataLayout()), | |||
| 5018 | getValue(I.getArgOperand(0)))); | |||
| 5019 | return nullptr; | |||
| 5020 | case Intrinsic::read_register: { | |||
| 5021 | Value *Reg = I.getArgOperand(0); | |||
| 5022 | SDValue Chain = getRoot(); | |||
| 5023 | SDValue RegName = | |||
| 5024 | DAG.getMDNode(cast<MDNode>(cast<MetadataAsValue>(Reg)->getMetadata())); | |||
| 5025 | EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType()); | |||
| 5026 | Res = DAG.getNode(ISD::READ_REGISTER, sdl, | |||
| 5027 | DAG.getVTList(VT, MVT::Other), Chain, RegName); | |||
| 5028 | setValue(&I, Res); | |||
| 5029 | DAG.setRoot(Res.getValue(1)); | |||
| 5030 | return nullptr; | |||
| 5031 | } | |||
| 5032 | case Intrinsic::write_register: { | |||
| 5033 | Value *Reg = I.getArgOperand(0); | |||
| 5034 | Value *RegValue = I.getArgOperand(1); | |||
| 5035 | SDValue Chain = getRoot(); | |||
| 5036 | SDValue RegName = | |||
| 5037 | DAG.getMDNode(cast<MDNode>(cast<MetadataAsValue>(Reg)->getMetadata())); | |||
| 5038 | DAG.setRoot(DAG.getNode(ISD::WRITE_REGISTER, sdl, MVT::Other, Chain, | |||
| 5039 | RegName, getValue(RegValue))); | |||
| 5040 | return nullptr; | |||
| 5041 | } | |||
| 5042 | case Intrinsic::setjmp: | |||
| 5043 | return &"_setjmp"[!TLI.usesUnderscoreSetJmp()]; | |||
| 5044 | case Intrinsic::longjmp: | |||
| 5045 | return &"_longjmp"[!TLI.usesUnderscoreLongJmp()]; | |||
| 5046 | case Intrinsic::memcpy: { | |||
| 5047 | const auto &MCI = cast<MemCpyInst>(I); | |||
| 5048 | SDValue Op1 = getValue(I.getArgOperand(0)); | |||
| 5049 | SDValue Op2 = getValue(I.getArgOperand(1)); | |||
| 5050 | SDValue Op3 = getValue(I.getArgOperand(2)); | |||
| 5051 | // @llvm.memcpy defines 0 and 1 to both mean no alignment. | |||
| 5052 | unsigned DstAlign = std::max<unsigned>(MCI.getDestAlignment(), 1); | |||
| 5053 | unsigned SrcAlign = std::max<unsigned>(MCI.getSourceAlignment(), 1); | |||
| 5054 | unsigned Align = MinAlign(DstAlign, SrcAlign); | |||
| 5055 | bool isVol = MCI.isVolatile(); | |||
| 5056 | bool isTC = I.isTailCall() && isInTailCallPosition(&I, DAG.getTarget()); | |||
| 5057 | // FIXME: Support passing different dest/src alignments to the memcpy DAG | |||
| 5058 | // node. | |||
| 5059 | SDValue MC = DAG.getMemcpy(getRoot(), sdl, Op1, Op2, Op3, Align, isVol, | |||
| 5060 | false, isTC, | |||
| 5061 | MachinePointerInfo(I.getArgOperand(0)), | |||
| 5062 | MachinePointerInfo(I.getArgOperand(1))); | |||
| 5063 | updateDAGForMaybeTailCall(MC); | |||
| 5064 | return nullptr; | |||
| 5065 | } | |||
| 5066 | case Intrinsic::memset: { | |||
| 5067 | const auto &MSI = cast<MemSetInst>(I); | |||
| 5068 | SDValue Op1 = getValue(I.getArgOperand(0)); | |||
| 5069 | SDValue Op2 = getValue(I.getArgOperand(1)); | |||
| 5070 | SDValue Op3 = getValue(I.getArgOperand(2)); | |||
| 5071 | // @llvm.memset defines 0 and 1 to both mean no alignment. | |||
| 5072 | unsigned Align = std::max<unsigned>(MSI.getDestAlignment(), 1); | |||
| 5073 | bool isVol = MSI.isVolatile(); | |||
| 5074 | bool isTC = I.isTailCall() && isInTailCallPosition(&I, DAG.getTarget()); | |||
| 5075 | SDValue MS = DAG.getMemset(getRoot(), sdl, Op1, Op2, Op3, Align, isVol, | |||
| 5076 | isTC, MachinePointerInfo(I.getArgOperand(0))); | |||
| 5077 | updateDAGForMaybeTailCall(MS); | |||
| 5078 | return nullptr; | |||
| 5079 | } | |||
| 5080 | case Intrinsic::memmove: { | |||
| 5081 | const auto &MMI = cast<MemMoveInst>(I); | |||
| 5082 | SDValue Op1 = getValue(I.getArgOperand(0)); | |||
| 5083 | SDValue Op2 = getValue(I.getArgOperand(1)); | |||
| 5084 | SDValue Op3 = getValue(I.getArgOperand(2)); | |||
| 5085 | // @llvm.memmove defines 0 and 1 to both mean no alignment. | |||
| 5086 | unsigned DstAlign = std::max<unsigned>(MMI.getDestAlignment(), 1); | |||
| 5087 | unsigned SrcAlign = std::max<unsigned>(MMI.getSourceAlignment(), 1); | |||
| 5088 | unsigned Align = MinAlign(DstAlign, SrcAlign); | |||
| 5089 | bool isVol = MMI.isVolatile(); | |||
| 5090 | bool isTC = I.isTailCall() && isInTailCallPosition(&I, DAG.getTarget()); | |||
| 5091 | // FIXME: Support passing different dest/src alignments to the memmove DAG | |||
| 5092 | // node. | |||
| 5093 | SDValue MM = DAG.getMemmove(getRoot(), sdl, Op1, Op2, Op3, Align, isVol, | |||
| 5094 | isTC, MachinePointerInfo(I.getArgOperand(0)), | |||
| 5095 | MachinePointerInfo(I.getArgOperand(1))); | |||
| 5096 | updateDAGForMaybeTailCall(MM); | |||
| 5097 | return nullptr; | |||
| 5098 | } | |||
| 5099 | case Intrinsic::memcpy_element_unordered_atomic: { | |||
| 5100 | const AtomicMemCpyInst &MI = cast<AtomicMemCpyInst>(I); | |||
| 5101 | SDValue Dst = getValue(MI.getRawDest()); | |||
| 5102 | SDValue Src = getValue(MI.getRawSource()); | |||
| 5103 | SDValue Length = getValue(MI.getLength()); | |||
| 5104 | ||||
| 5105 | unsigned DstAlign = MI.getDestAlignment(); | |||
| 5106 | unsigned SrcAlign = MI.getSourceAlignment(); | |||
| 5107 | Type *LengthTy = MI.getLength()->getType(); | |||
| 5108 | unsigned ElemSz = MI.getElementSizeInBytes(); | |||
| 5109 | bool isTC = I.isTailCall() && isInTailCallPosition(&I, DAG.getTarget()); | |||
| 5110 | SDValue MC = DAG.getAtomicMemcpy(getRoot(), sdl, Dst, DstAlign, Src, | |||
| 5111 | SrcAlign, Length, LengthTy, ElemSz, isTC, | |||
| 5112 | MachinePointerInfo(MI.getRawDest()), | |||
| 5113 | MachinePointerInfo(MI.getRawSource())); | |||
| 5114 | updateDAGForMaybeTailCall(MC); | |||
| 5115 | return nullptr; | |||
| 5116 | } | |||
| 5117 | case Intrinsic::memmove_element_unordered_atomic: { | |||
| 5118 | auto &MI = cast<AtomicMemMoveInst>(I); | |||
| 5119 | SDValue Dst = getValue(MI.getRawDest()); | |||
| 5120 | SDValue Src = getValue(MI.getRawSource()); | |||
| 5121 | SDValue Length = getValue(MI.getLength()); | |||
| 5122 | ||||
| 5123 | unsigned DstAlign = MI.getDestAlignment(); | |||
| 5124 | unsigned SrcAlign = MI.getSourceAlignment(); | |||
| 5125 | Type *LengthTy = MI.getLength()->getType(); | |||
| 5126 | unsigned ElemSz = MI.getElementSizeInBytes(); | |||
| 5127 | bool isTC = I.isTailCall() && isInTailCallPosition(&I, DAG.getTarget()); | |||
| 5128 | SDValue MC = DAG.getAtomicMemmove(getRoot(), sdl, Dst, DstAlign, Src, | |||
| 5129 | SrcAlign, Length, LengthTy, ElemSz, isTC, | |||
| 5130 | MachinePointerInfo(MI.getRawDest()), | |||
| 5131 | MachinePointerInfo(MI.getRawSource())); | |||
| 5132 | updateDAGForMaybeTailCall(MC); | |||
| 5133 | return nullptr; | |||
| 5134 | } | |||
| 5135 | case Intrinsic::memset_element_unordered_atomic: { | |||
| 5136 | auto &MI = cast<AtomicMemSetInst>(I); | |||
| 5137 | SDValue Dst = getValue(MI.getRawDest()); | |||
| 5138 | SDValue Val = getValue(MI.getValue()); | |||
| 5139 | SDValue Length = getValue(MI.getLength()); | |||
| 5140 | ||||
| 5141 | unsigned DstAlign = MI.getDestAlignment(); | |||
| 5142 | Type *LengthTy = MI.getLength()->getType(); | |||
| 5143 | unsigned ElemSz = MI.getElementSizeInBytes(); | |||
| 5144 | bool isTC = I.isTailCall() && isInTailCallPosition(&I, DAG.getTarget()); | |||
| 5145 | SDValue MC = DAG.getAtomicMemset(getRoot(), sdl, Dst, DstAlign, Val, Length, | |||
| 5146 | LengthTy, ElemSz, isTC, | |||
| 5147 | MachinePointerInfo(MI.getRawDest())); | |||
| 5148 | updateDAGForMaybeTailCall(MC); | |||
| 5149 | return nullptr; | |||
| 5150 | } | |||
| 5151 | case Intrinsic::dbg_addr: | |||
| 5152 | case Intrinsic::dbg_declare: { | |||
| 5153 | const DbgInfoIntrinsic &DI = cast<DbgInfoIntrinsic>(I); | |||
| 5154 | DILocalVariable *Variable = DI.getVariable(); | |||
| 5155 | DIExpression *Expression = DI.getExpression(); | |||
| 5156 | dropDanglingDebugInfo(Variable, Expression); | |||
| 5157 | assert(Variable && "Missing variable")(static_cast <bool> (Variable && "Missing variable" ) ? void (0) : __assert_fail ("Variable && \"Missing variable\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 5157, __extension__ __PRETTY_FUNCTION__)); | |||
| 5158 | ||||
| 5159 | // Check if address has undef value. | |||
| 5160 | const Value *Address = DI.getVariableLocation(); | |||
| 5161 | if (!Address || isa<UndefValue>(Address) || | |||
| 5162 | (Address->use_empty() && !isa<Argument>(Address))) { | |||
| 5163 | LLVM_DEBUG(dbgs() << "Dropping debug info for " << DI << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType ("isel")) { dbgs() << "Dropping debug info for " << DI << "\n"; } } while (false); | |||
| 5164 | return nullptr; | |||
| 5165 | } | |||
| 5166 | ||||
| 5167 | bool isParameter = Variable->isParameter() || isa<Argument>(Address); | |||
| 5168 | ||||
| 5169 | // Check if this variable can be described by a frame index, typically | |||
| 5170 | // either as a static alloca or a byval parameter. | |||
| 5171 | int FI = std::numeric_limits<int>::max(); | |||
| 5172 | if (const auto *AI = | |||
| 5173 | dyn_cast<AllocaInst>(Address->stripInBoundsConstantOffsets())) { | |||
| 5174 | if (AI->isStaticAlloca()) { | |||
| 5175 | auto I = FuncInfo.StaticAllocaMap.find(AI); | |||
| 5176 | if (I != FuncInfo.StaticAllocaMap.end()) | |||
| 5177 | FI = I->second; | |||
| 5178 | } | |||
| 5179 | } else if (const auto *Arg = dyn_cast<Argument>( | |||
| 5180 | Address->stripInBoundsConstantOffsets())) { | |||
| 5181 | FI = FuncInfo.getArgumentFrameIndex(Arg); | |||
| 5182 | } | |||
| 5183 | ||||
| 5184 | // llvm.dbg.addr is control dependent and always generates indirect | |||
| 5185 | // DBG_VALUE instructions. llvm.dbg.declare is handled as a frame index in | |||
| 5186 | // the MachineFunction variable table. | |||
| 5187 | if (FI != std::numeric_limits<int>::max()) { | |||
| 5188 | if (Intrinsic == Intrinsic::dbg_addr) { | |||
| 5189 | SDDbgValue *SDV = DAG.getFrameIndexDbgValue(Variable, Expression, | |||
| 5190 | FI, dl, SDNodeOrder); | |||
| 5191 | DAG.AddDbgValue(SDV, getRoot().getNode(), isParameter); | |||
| 5192 | } | |||
| 5193 | return nullptr; | |||
| 5194 | } | |||
| 5195 | ||||
| 5196 | SDValue &N = NodeMap[Address]; | |||
| 5197 | if (!N.getNode() && isa<Argument>(Address)) | |||
| 5198 | // Check unused arguments map. | |||
| 5199 | N = UnusedArgNodeMap[Address]; | |||
| 5200 | SDDbgValue *SDV; | |||
| 5201 | if (N.getNode()) { | |||
| 5202 | if (const BitCastInst *BCI = dyn_cast<BitCastInst>(Address)) | |||
| 5203 | Address = BCI->getOperand(0); | |||
| 5204 | // Parameters are handled specially. | |||
| 5205 | auto FINode = dyn_cast<FrameIndexSDNode>(N.getNode()); | |||
| 5206 | if (isParameter && FINode) { | |||
| 5207 | // Byval parameter. We have a frame index at this point. | |||
| 5208 | SDV = DAG.getFrameIndexDbgValue(Variable, Expression, | |||
| 5209 | FINode->getIndex(), dl, SDNodeOrder); | |||
| 5210 | } else if (isa<Argument>(Address)) { | |||
| 5211 | // Address is an argument, so try to emit its dbg value using | |||
| 5212 | // virtual register info from the FuncInfo.ValueMap. | |||
| 5213 | EmitFuncArgumentDbgValue(Address, Variable, Expression, dl, true, N); | |||
| 5214 | return nullptr; | |||
| 5215 | } else { | |||
| 5216 | SDV = DAG.getDbgValue(Variable, Expression, N.getNode(), N.getResNo(), | |||
| 5217 | true, dl, SDNodeOrder); | |||
| 5218 | } | |||
| 5219 | DAG.AddDbgValue(SDV, N.getNode(), isParameter); | |||
| 5220 | } else { | |||
| 5221 | // If Address is an argument then try to emit its dbg value using | |||
| 5222 | // virtual register info from the FuncInfo.ValueMap. | |||
| 5223 | if (!EmitFuncArgumentDbgValue(Address, Variable, Expression, dl, true, | |||
| 5224 | N)) { | |||
| 5225 | LLVM_DEBUG(dbgs() << "Dropping debug info for " << DI << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType ("isel")) { dbgs() << "Dropping debug info for " << DI << "\n"; } } while (false); | |||
| 5226 | } | |||
| 5227 | } | |||
| 5228 | return nullptr; | |||
| 5229 | } | |||
| 5230 | case Intrinsic::dbg_label: { | |||
| 5231 | const DbgLabelInst &DI = cast<DbgLabelInst>(I); | |||
| 5232 | DILabel *Label = DI.getLabel(); | |||
| 5233 | assert(Label && "Missing label")(static_cast <bool> (Label && "Missing label") ? void (0) : __assert_fail ("Label && \"Missing label\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 5233, __extension__ __PRETTY_FUNCTION__)); | |||
| 5234 | ||||
| 5235 | SDDbgLabel *SDV; | |||
| 5236 | SDV = DAG.getDbgLabel(Label, dl, SDNodeOrder); | |||
| 5237 | DAG.AddDbgLabel(SDV); | |||
| 5238 | return nullptr; | |||
| 5239 | } | |||
| 5240 | case Intrinsic::dbg_value: { | |||
| 5241 | const DbgValueInst &DI = cast<DbgValueInst>(I); | |||
| 5242 | assert(DI.getVariable() && "Missing variable")(static_cast <bool> (DI.getVariable() && "Missing variable" ) ? void (0) : __assert_fail ("DI.getVariable() && \"Missing variable\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 5242, __extension__ __PRETTY_FUNCTION__)); | |||
| 5243 | ||||
| 5244 | DILocalVariable *Variable = DI.getVariable(); | |||
| 5245 | DIExpression *Expression = DI.getExpression(); | |||
| 5246 | dropDanglingDebugInfo(Variable, Expression); | |||
| 5247 | const Value *V = DI.getValue(); | |||
| 5248 | if (!V) | |||
| 5249 | return nullptr; | |||
| 5250 | ||||
| 5251 | SDDbgValue *SDV; | |||
| 5252 | if (isa<ConstantInt>(V) || isa<ConstantFP>(V) || isa<UndefValue>(V)) { | |||
| 5253 | SDV = DAG.getConstantDbgValue(Variable, Expression, V, dl, SDNodeOrder); | |||
| 5254 | DAG.AddDbgValue(SDV, nullptr, false); | |||
| 5255 | return nullptr; | |||
| 5256 | } | |||
| 5257 | ||||
| 5258 | // Do not use getValue() in here; we don't want to generate code at | |||
| 5259 | // this point if it hasn't been done yet. | |||
| 5260 | SDValue N = NodeMap[V]; | |||
| 5261 | if (!N.getNode() && isa<Argument>(V)) // Check unused arguments map. | |||
| 5262 | N = UnusedArgNodeMap[V]; | |||
| 5263 | if (N.getNode()) { | |||
| 5264 | if (EmitFuncArgumentDbgValue(V, Variable, Expression, dl, false, N)) | |||
| 5265 | return nullptr; | |||
| 5266 | SDV = getDbgValue(N, Variable, Expression, dl, SDNodeOrder); | |||
| 5267 | DAG.AddDbgValue(SDV, N.getNode(), false); | |||
| 5268 | return nullptr; | |||
| 5269 | } | |||
| 5270 | ||||
| 5271 | // PHI nodes have already been selected, so we should know which VReg that | |||
| 5272 | // is assigns to already. | |||
| 5273 | if (isa<PHINode>(V)) { | |||
| 5274 | auto VMI = FuncInfo.ValueMap.find(V); | |||
| 5275 | if (VMI != FuncInfo.ValueMap.end()) { | |||
| 5276 | unsigned Reg = VMI->second; | |||
| 5277 | // The PHI node may be split up into several MI PHI nodes (in | |||
| 5278 | // FunctionLoweringInfo::set). | |||
| 5279 | RegsForValue RFV(V->getContext(), TLI, DAG.getDataLayout(), Reg, | |||
| 5280 | V->getType(), false); | |||
| 5281 | if (RFV.occupiesMultipleRegs()) { | |||
| 5282 | unsigned Offset = 0; | |||
| 5283 | unsigned BitsToDescribe = 0; | |||
| 5284 | if (auto VarSize = Variable->getSizeInBits()) | |||
| 5285 | BitsToDescribe = *VarSize; | |||
| 5286 | if (auto Fragment = Expression->getFragmentInfo()) | |||
| 5287 | BitsToDescribe = Fragment->SizeInBits; | |||
| 5288 | for (auto RegAndSize : RFV.getRegsAndSizes()) { | |||
| 5289 | unsigned RegisterSize = RegAndSize.second; | |||
| 5290 | // Bail out if all bits are described already. | |||
| 5291 | if (Offset >= BitsToDescribe) | |||
| 5292 | break; | |||
| 5293 | unsigned FragmentSize = (Offset + RegisterSize > BitsToDescribe) | |||
| 5294 | ? BitsToDescribe - Offset | |||
| 5295 | : RegisterSize; | |||
| 5296 | auto FragmentExpr = DIExpression::createFragmentExpression( | |||
| 5297 | Expression, Offset, FragmentSize); | |||
| 5298 | if (!FragmentExpr) | |||
| 5299 | continue; | |||
| 5300 | SDV = DAG.getVRegDbgValue(Variable, *FragmentExpr, RegAndSize.first, | |||
| 5301 | false, dl, SDNodeOrder); | |||
| 5302 | DAG.AddDbgValue(SDV, nullptr, false); | |||
| 5303 | Offset += RegisterSize; | |||
| 5304 | } | |||
| 5305 | } else { | |||
| 5306 | SDV = DAG.getVRegDbgValue(Variable, Expression, Reg, false, dl, | |||
| 5307 | SDNodeOrder); | |||
| 5308 | DAG.AddDbgValue(SDV, nullptr, false); | |||
| 5309 | } | |||
| 5310 | return nullptr; | |||
| 5311 | } | |||
| 5312 | } | |||
| 5313 | ||||
| 5314 | // TODO: When we get here we will either drop the dbg.value completely, or | |||
| 5315 | // we try to move it forward by letting it dangle for awhile. So we should | |||
| 5316 | // probably add an extra DbgValue to the DAG here, with a reference to | |||
| 5317 | // "noreg", to indicate that we have lost the debug location for the | |||
| 5318 | // variable. | |||
| 5319 | ||||
| 5320 | if (!V->use_empty() ) { | |||
| 5321 | // Do not call getValue(V) yet, as we don't want to generate code. | |||
| 5322 | // Remember it for later. | |||
| 5323 | DanglingDebugInfo DDI(&DI, dl, SDNodeOrder); | |||
| 5324 | DanglingDebugInfoMap[V].push_back(DDI); | |||
| 5325 | return nullptr; | |||
| 5326 | } | |||
| 5327 | ||||
| 5328 | LLVM_DEBUG(dbgs() << "Dropping debug location info for:\n " << DI << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType ("isel")) { dbgs() << "Dropping debug location info for:\n " << DI << "\n"; } } while (false); | |||
| 5329 | LLVM_DEBUG(dbgs() << " Last seen at:\n " << *V << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType ("isel")) { dbgs() << " Last seen at:\n " << * V << "\n"; } } while (false); | |||
| 5330 | return nullptr; | |||
| 5331 | } | |||
| 5332 | ||||
| 5333 | case Intrinsic::eh_typeid_for: { | |||
| 5334 | // Find the type id for the given typeinfo. | |||
| 5335 | GlobalValue *GV = ExtractTypeInfo(I.getArgOperand(0)); | |||
| 5336 | unsigned TypeID = DAG.getMachineFunction().getTypeIDFor(GV); | |||
| 5337 | Res = DAG.getConstant(TypeID, sdl, MVT::i32); | |||
| 5338 | setValue(&I, Res); | |||
| 5339 | return nullptr; | |||
| 5340 | } | |||
| 5341 | ||||
| 5342 | case Intrinsic::eh_return_i32: | |||
| 5343 | case Intrinsic::eh_return_i64: | |||
| 5344 | DAG.getMachineFunction().setCallsEHReturn(true); | |||
| 5345 | DAG.setRoot(DAG.getNode(ISD::EH_RETURN, sdl, | |||
| 5346 | MVT::Other, | |||
| 5347 | getControlRoot(), | |||
| 5348 | getValue(I.getArgOperand(0)), | |||
| 5349 | getValue(I.getArgOperand(1)))); | |||
| 5350 | return nullptr; | |||
| 5351 | case Intrinsic::eh_unwind_init: | |||
| 5352 | DAG.getMachineFunction().setCallsUnwindInit(true); | |||
| 5353 | return nullptr; | |||
| 5354 | case Intrinsic::eh_dwarf_cfa: | |||
| 5355 | setValue(&I, DAG.getNode(ISD::EH_DWARF_CFA, sdl, | |||
| 5356 | TLI.getPointerTy(DAG.getDataLayout()), | |||
| 5357 | getValue(I.getArgOperand(0)))); | |||
| 5358 | return nullptr; | |||
| 5359 | case Intrinsic::eh_sjlj_callsite: { | |||
| 5360 | MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); | |||
| 5361 | ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(0)); | |||
| 5362 | assert(CI && "Non-constant call site value in eh.sjlj.callsite!")(static_cast <bool> (CI && "Non-constant call site value in eh.sjlj.callsite!" ) ? void (0) : __assert_fail ("CI && \"Non-constant call site value in eh.sjlj.callsite!\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 5362, __extension__ __PRETTY_FUNCTION__)); | |||
| 5363 | assert(MMI.getCurrentCallSite() == 0 && "Overlapping call sites!")(static_cast <bool> (MMI.getCurrentCallSite() == 0 && "Overlapping call sites!") ? void (0) : __assert_fail ("MMI.getCurrentCallSite() == 0 && \"Overlapping call sites!\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 5363, __extension__ __PRETTY_FUNCTION__)); | |||
| 5364 | ||||
| 5365 | MMI.setCurrentCallSite(CI->getZExtValue()); | |||
| 5366 | return nullptr; | |||
| 5367 | } | |||
| 5368 | case Intrinsic::eh_sjlj_functioncontext: { | |||
| 5369 | // Get and store the index of the function context. | |||
| 5370 | MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo(); | |||
| 5371 | AllocaInst *FnCtx = | |||
| 5372 | cast<AllocaInst>(I.getArgOperand(0)->stripPointerCasts()); | |||
| 5373 | int FI = FuncInfo.StaticAllocaMap[FnCtx]; | |||
| 5374 | MFI.setFunctionContextIndex(FI); | |||
| 5375 | return nullptr; | |||
| 5376 | } | |||
| 5377 | case Intrinsic::eh_sjlj_setjmp: { | |||
| 5378 | SDValue Ops[2]; | |||
| 5379 | Ops[0] = getRoot(); | |||
| 5380 | Ops[1] = getValue(I.getArgOperand(0)); | |||
| 5381 | SDValue Op = DAG.getNode(ISD::EH_SJLJ_SETJMP, sdl, | |||
| 5382 | DAG.getVTList(MVT::i32, MVT::Other), Ops); | |||
| 5383 | setValue(&I, Op.getValue(0)); | |||
| 5384 | DAG.setRoot(Op.getValue(1)); | |||
| 5385 | return nullptr; | |||
| 5386 | } | |||
| 5387 | case Intrinsic::eh_sjlj_longjmp: | |||
| 5388 | DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_LONGJMP, sdl, MVT::Other, | |||
| 5389 | getRoot(), getValue(I.getArgOperand(0)))); | |||
| 5390 | return nullptr; | |||
| 5391 | case Intrinsic::eh_sjlj_setup_dispatch: | |||
| 5392 | DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_SETUP_DISPATCH, sdl, MVT::Other, | |||
| 5393 | getRoot())); | |||
| 5394 | return nullptr; | |||
| 5395 | case Intrinsic::masked_gather: | |||
| 5396 | visitMaskedGather(I); | |||
| 5397 | return nullptr; | |||
| 5398 | case Intrinsic::masked_load: | |||
| 5399 | visitMaskedLoad(I); | |||
| 5400 | return nullptr; | |||
| 5401 | case Intrinsic::masked_scatter: | |||
| 5402 | visitMaskedScatter(I); | |||
| 5403 | return nullptr; | |||
| 5404 | case Intrinsic::masked_store: | |||
| 5405 | visitMaskedStore(I); | |||
| 5406 | return nullptr; | |||
| 5407 | case Intrinsic::masked_expandload: | |||
| 5408 | visitMaskedLoad(I, true /* IsExpanding */); | |||
| 5409 | return nullptr; | |||
| 5410 | case Intrinsic::masked_compressstore: | |||
| 5411 | visitMaskedStore(I, true /* IsCompressing */); | |||
| 5412 | return nullptr; | |||
| 5413 | case Intrinsic::x86_mmx_pslli_w: | |||
| 5414 | case Intrinsic::x86_mmx_pslli_d: | |||
| 5415 | case Intrinsic::x86_mmx_pslli_q: | |||
| 5416 | case Intrinsic::x86_mmx_psrli_w: | |||
| 5417 | case Intrinsic::x86_mmx_psrli_d: | |||
| 5418 | case Intrinsic::x86_mmx_psrli_q: | |||
| 5419 | case Intrinsic::x86_mmx_psrai_w: | |||
| 5420 | case Intrinsic::x86_mmx_psrai_d: { | |||
| 5421 | SDValue ShAmt = getValue(I.getArgOperand(1)); | |||
| 5422 | if (isa<ConstantSDNode>(ShAmt)) { | |||
| 5423 | visitTargetIntrinsic(I, Intrinsic); | |||
| 5424 | return nullptr; | |||
| 5425 | } | |||
| 5426 | unsigned NewIntrinsic = 0; | |||
| 5427 | EVT ShAmtVT = MVT::v2i32; | |||
| 5428 | switch (Intrinsic) { | |||
| 5429 | case Intrinsic::x86_mmx_pslli_w: | |||
| 5430 | NewIntrinsic = Intrinsic::x86_mmx_psll_w; | |||
| 5431 | break; | |||
| 5432 | case Intrinsic::x86_mmx_pslli_d: | |||
| 5433 | NewIntrinsic = Intrinsic::x86_mmx_psll_d; | |||
| 5434 | break; | |||
| 5435 | case Intrinsic::x86_mmx_pslli_q: | |||
| 5436 | NewIntrinsic = Intrinsic::x86_mmx_psll_q; | |||
| 5437 | break; | |||
| 5438 | case Intrinsic::x86_mmx_psrli_w: | |||
| 5439 | NewIntrinsic = Intrinsic::x86_mmx_psrl_w; | |||
| 5440 | break; | |||
| 5441 | case Intrinsic::x86_mmx_psrli_d: | |||
| 5442 | NewIntrinsic = Intrinsic::x86_mmx_psrl_d; | |||
| 5443 | break; | |||
| 5444 | case Intrinsic::x86_mmx_psrli_q: | |||
| 5445 | NewIntrinsic = Intrinsic::x86_mmx_psrl_q; | |||
| 5446 | break; | |||
| 5447 | case Intrinsic::x86_mmx_psrai_w: | |||
| 5448 | NewIntrinsic = Intrinsic::x86_mmx_psra_w; | |||
| 5449 | break; | |||
| 5450 | case Intrinsic::x86_mmx_psrai_d: | |||
| 5451 | NewIntrinsic = Intrinsic::x86_mmx_psra_d; | |||
| 5452 | break; | |||
| 5453 | default: llvm_unreachable("Impossible intrinsic")::llvm::llvm_unreachable_internal("Impossible intrinsic", "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 5453); // Can't reach here. | |||
| 5454 | } | |||
| 5455 | ||||
| 5456 | // The vector shift intrinsics with scalars uses 32b shift amounts but | |||
| 5457 | // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits | |||
| 5458 | // to be zero. | |||
| 5459 | // We must do this early because v2i32 is not a legal type. | |||
| 5460 | SDValue ShOps[2]; | |||
| 5461 | ShOps[0] = ShAmt; | |||
| 5462 | ShOps[1] = DAG.getConstant(0, sdl, MVT::i32); | |||
| 5463 | ShAmt = DAG.getBuildVector(ShAmtVT, sdl, ShOps); | |||
| 5464 | EVT DestVT = TLI.getValueType(DAG.getDataLayout(), I.getType()); | |||
| 5465 | ShAmt = DAG.getNode(ISD::BITCAST, sdl, DestVT, ShAmt); | |||
| 5466 | Res = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, sdl, DestVT, | |||
| 5467 | DAG.getConstant(NewIntrinsic, sdl, MVT::i32), | |||
| 5468 | getValue(I.getArgOperand(0)), ShAmt); | |||
| 5469 | setValue(&I, Res); | |||
| 5470 | return nullptr; | |||
| 5471 | } | |||
| 5472 | case Intrinsic::powi: | |||
| 5473 | setValue(&I, ExpandPowI(sdl, getValue(I.getArgOperand(0)), | |||
| 5474 | getValue(I.getArgOperand(1)), DAG)); | |||
| 5475 | return nullptr; | |||
| 5476 | case Intrinsic::log: | |||
| 5477 | setValue(&I, expandLog(sdl, getValue(I.getArgOperand(0)), DAG, TLI)); | |||
| 5478 | return nullptr; | |||
| 5479 | case Intrinsic::log2: | |||
| 5480 | setValue(&I, expandLog2(sdl, getValue(I.getArgOperand(0)), DAG, TLI)); | |||
| 5481 | return nullptr; | |||
| 5482 | case Intrinsic::log10: | |||
| 5483 | setValue(&I, expandLog10(sdl, getValue(I.getArgOperand(0)), DAG, TLI)); | |||
| 5484 | return nullptr; | |||
| 5485 | case Intrinsic::exp: | |||
| 5486 | setValue(&I, expandExp(sdl, getValue(I.getArgOperand(0)), DAG, TLI)); | |||
| 5487 | return nullptr; | |||
| 5488 | case Intrinsic::exp2: | |||
| 5489 | setValue(&I, expandExp2(sdl, getValue(I.getArgOperand(0)), DAG, TLI)); | |||
| 5490 | return nullptr; | |||
| 5491 | case Intrinsic::pow: | |||
| 5492 | setValue(&I, expandPow(sdl, getValue(I.getArgOperand(0)), | |||
| 5493 | getValue(I.getArgOperand(1)), DAG, TLI)); | |||
| 5494 | return nullptr; | |||
| 5495 | case Intrinsic::sqrt: | |||
| 5496 | case Intrinsic::fabs: | |||
| 5497 | case Intrinsic::sin: | |||
| 5498 | case Intrinsic::cos: | |||
| 5499 | case Intrinsic::floor: | |||
| 5500 | case Intrinsic::ceil: | |||
| 5501 | case Intrinsic::trunc: | |||
| 5502 | case Intrinsic::rint: | |||
| 5503 | case Intrinsic::nearbyint: | |||
| 5504 | case Intrinsic::round: | |||
| 5505 | case Intrinsic::canonicalize: { | |||
| 5506 | unsigned Opcode; | |||
| 5507 | switch (Intrinsic) { | |||
| 5508 | default: llvm_unreachable("Impossible intrinsic")::llvm::llvm_unreachable_internal("Impossible intrinsic", "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 5508); // Can't reach here. | |||
| 5509 | case Intrinsic::sqrt: Opcode = ISD::FSQRT; break; | |||
| 5510 | case Intrinsic::fabs: Opcode = ISD::FABS; break; | |||
| 5511 | case Intrinsic::sin: Opcode = ISD::FSIN; break; | |||
| 5512 | case Intrinsic::cos: Opcode = ISD::FCOS; break; | |||
| 5513 | case Intrinsic::floor: Opcode = ISD::FFLOOR; break; | |||
| 5514 | case Intrinsic::ceil: Opcode = ISD::FCEIL; break; | |||
| 5515 | case Intrinsic::trunc: Opcode = ISD::FTRUNC; break; | |||
| 5516 | case Intrinsic::rint: Opcode = ISD::FRINT; break; | |||
| 5517 | case Intrinsic::nearbyint: Opcode = ISD::FNEARBYINT; break; | |||
| 5518 | case Intrinsic::round: Opcode = ISD::FROUND; break; | |||
| 5519 | case Intrinsic::canonicalize: Opcode = ISD::FCANONICALIZE; break; | |||
| 5520 | } | |||
| 5521 | ||||
| 5522 | setValue(&I, DAG.getNode(Opcode, sdl, | |||
| 5523 | getValue(I.getArgOperand(0)).getValueType(), | |||
| 5524 | getValue(I.getArgOperand(0)))); | |||
| 5525 | return nullptr; | |||
| 5526 | } | |||
| 5527 | case Intrinsic::minnum: { | |||
| 5528 | auto VT = getValue(I.getArgOperand(0)).getValueType(); | |||
| 5529 | unsigned Opc = | |||
| 5530 | I.hasNoNaNs() && TLI.isOperationLegalOrCustom(ISD::FMINNAN, VT) | |||
| 5531 | ? ISD::FMINNAN | |||
| 5532 | : ISD::FMINNUM; | |||
| 5533 | setValue(&I, DAG.getNode(Opc, sdl, VT, | |||
| 5534 | getValue(I.getArgOperand(0)), | |||
| 5535 | getValue(I.getArgOperand(1)))); | |||
| 5536 | return nullptr; | |||
| 5537 | } | |||
| 5538 | case Intrinsic::maxnum: { | |||
| 5539 | auto VT = getValue(I.getArgOperand(0)).getValueType(); | |||
| 5540 | unsigned Opc = | |||
| 5541 | I.hasNoNaNs() && TLI.isOperationLegalOrCustom(ISD::FMAXNAN, VT) | |||
| 5542 | ? ISD::FMAXNAN | |||
| 5543 | : ISD::FMAXNUM; | |||
| 5544 | setValue(&I, DAG.getNode(Opc, sdl, VT, | |||
| 5545 | getValue(I.getArgOperand(0)), | |||
| 5546 | getValue(I.getArgOperand(1)))); | |||
| 5547 | return nullptr; | |||
| 5548 | } | |||
| 5549 | case Intrinsic::copysign: | |||
| 5550 | setValue(&I, DAG.getNode(ISD::FCOPYSIGN, sdl, | |||
| 5551 | getValue(I.getArgOperand(0)).getValueType(), | |||
| 5552 | getValue(I.getArgOperand(0)), | |||
| 5553 | getValue(I.getArgOperand(1)))); | |||
| 5554 | return nullptr; | |||
| 5555 | case Intrinsic::fma: | |||
| 5556 | setValue(&I, DAG.getNode(ISD::FMA, sdl, | |||
| 5557 | getValue(I.getArgOperand(0)).getValueType(), | |||
| 5558 | getValue(I.getArgOperand(0)), | |||
| 5559 | getValue(I.getArgOperand(1)), | |||
| 5560 | getValue(I.getArgOperand(2)))); | |||
| 5561 | return nullptr; | |||
| 5562 | case Intrinsic::experimental_constrained_fadd: | |||
| 5563 | case Intrinsic::experimental_constrained_fsub: | |||
| 5564 | case Intrinsic::experimental_constrained_fmul: | |||
| 5565 | case Intrinsic::experimental_constrained_fdiv: | |||
| 5566 | case Intrinsic::experimental_constrained_frem: | |||
| 5567 | case Intrinsic::experimental_constrained_fma: | |||
| 5568 | case Intrinsic::experimental_constrained_sqrt: | |||
| 5569 | case Intrinsic::experimental_constrained_pow: | |||
| 5570 | case Intrinsic::experimental_constrained_powi: | |||
| 5571 | case Intrinsic::experimental_constrained_sin: | |||
| 5572 | case Intrinsic::experimental_constrained_cos: | |||
| 5573 | case Intrinsic::experimental_constrained_exp: | |||
| 5574 | case Intrinsic::experimental_constrained_exp2: | |||
| 5575 | case Intrinsic::experimental_constrained_log: | |||
| 5576 | case Intrinsic::experimental_constrained_log10: | |||
| 5577 | case Intrinsic::experimental_constrained_log2: | |||
| 5578 | case Intrinsic::experimental_constrained_rint: | |||
| 5579 | case Intrinsic::experimental_constrained_nearbyint: | |||
| 5580 | visitConstrainedFPIntrinsic(cast<ConstrainedFPIntrinsic>(I)); | |||
| 5581 | return nullptr; | |||
| 5582 | case Intrinsic::fmuladd: { | |||
| 5583 | EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType()); | |||
| 5584 | if (TM.Options.AllowFPOpFusion != FPOpFusion::Strict && | |||
| 5585 | TLI.isFMAFasterThanFMulAndFAdd(VT)) { | |||
| 5586 | setValue(&I, DAG.getNode(ISD::FMA, sdl, | |||
| 5587 | getValue(I.getArgOperand(0)).getValueType(), | |||
| 5588 | getValue(I.getArgOperand(0)), | |||
| 5589 | getValue(I.getArgOperand(1)), | |||
| 5590 | getValue(I.getArgOperand(2)))); | |||
| 5591 | } else { | |||
| 5592 | // TODO: Intrinsic calls should have fast-math-flags. | |||
| 5593 | SDValue Mul = DAG.getNode(ISD::FMUL, sdl, | |||
| 5594 | getValue(I.getArgOperand(0)).getValueType(), | |||
| 5595 | getValue(I.getArgOperand(0)), | |||
| 5596 | getValue(I.getArgOperand(1))); | |||
| 5597 | SDValue Add = DAG.getNode(ISD::FADD, sdl, | |||
| 5598 | getValue(I.getArgOperand(0)).getValueType(), | |||
| 5599 | Mul, | |||
| 5600 | getValue(I.getArgOperand(2))); | |||
| 5601 | setValue(&I, Add); | |||
| 5602 | } | |||
| 5603 | return nullptr; | |||
| 5604 | } | |||
| 5605 | case Intrinsic::convert_to_fp16: | |||
| 5606 | setValue(&I, DAG.getNode(ISD::BITCAST, sdl, MVT::i16, | |||
| 5607 | DAG.getNode(ISD::FP_ROUND, sdl, MVT::f16, | |||
| 5608 | getValue(I.getArgOperand(0)), | |||
| 5609 | DAG.getTargetConstant(0, sdl, | |||
| 5610 | MVT::i32)))); | |||
| 5611 | return nullptr; | |||
| 5612 | case Intrinsic::convert_from_fp16: | |||
| 5613 | setValue(&I, DAG.getNode(ISD::FP_EXTEND, sdl, | |||
| 5614 | TLI.getValueType(DAG.getDataLayout(), I.getType()), | |||
| 5615 | DAG.getNode(ISD::BITCAST, sdl, MVT::f16, | |||
| 5616 | getValue(I.getArgOperand(0))))); | |||
| 5617 | return nullptr; | |||
| 5618 | case Intrinsic::pcmarker: { | |||
| 5619 | SDValue Tmp = getValue(I.getArgOperand(0)); | |||
| 5620 | DAG.setRoot(DAG.getNode(ISD::PCMARKER, sdl, MVT::Other, getRoot(), Tmp)); | |||
| 5621 | return nullptr; | |||
| 5622 | } | |||
| 5623 | case Intrinsic::readcyclecounter: { | |||
| 5624 | SDValue Op = getRoot(); | |||
| 5625 | Res = DAG.getNode(ISD::READCYCLECOUNTER, sdl, | |||
| 5626 | DAG.getVTList(MVT::i64, MVT::Other), Op); | |||
| 5627 | setValue(&I, Res); | |||
| 5628 | DAG.setRoot(Res.getValue(1)); | |||
| 5629 | return nullptr; | |||
| 5630 | } | |||
| 5631 | case Intrinsic::bitreverse: | |||
| 5632 | setValue(&I, DAG.getNode(ISD::BITREVERSE, sdl, | |||
| 5633 | getValue(I.getArgOperand(0)).getValueType(), | |||
| 5634 | getValue(I.getArgOperand(0)))); | |||
| 5635 | return nullptr; | |||
| 5636 | case Intrinsic::bswap: | |||
| 5637 | setValue(&I, DAG.getNode(ISD::BSWAP, sdl, | |||
| 5638 | getValue(I.getArgOperand(0)).getValueType(), | |||
| 5639 | getValue(I.getArgOperand(0)))); | |||
| 5640 | return nullptr; | |||
| 5641 | case Intrinsic::cttz: { | |||
| 5642 | SDValue Arg = getValue(I.getArgOperand(0)); | |||
| 5643 | ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1)); | |||
| 5644 | EVT Ty = Arg.getValueType(); | |||
| 5645 | setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTTZ : ISD::CTTZ_ZERO_UNDEF, | |||
| 5646 | sdl, Ty, Arg)); | |||
| 5647 | return nullptr; | |||
| 5648 | } | |||
| 5649 | case Intrinsic::ctlz: { | |||
| 5650 | SDValue Arg = getValue(I.getArgOperand(0)); | |||
| 5651 | ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1)); | |||
| 5652 | EVT Ty = Arg.getValueType(); | |||
| 5653 | setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTLZ : ISD::CTLZ_ZERO_UNDEF, | |||
| 5654 | sdl, Ty, Arg)); | |||
| 5655 | return nullptr; | |||
| 5656 | } | |||
| 5657 | case Intrinsic::ctpop: { | |||
| 5658 | SDValue Arg = getValue(I.getArgOperand(0)); | |||
| 5659 | EVT Ty = Arg.getValueType(); | |||
| 5660 | setValue(&I, DAG.getNode(ISD::CTPOP, sdl, Ty, Arg)); | |||
| 5661 | return nullptr; | |||
| 5662 | } | |||
| 5663 | case Intrinsic::fshl: | |||
| 5664 | case Intrinsic::fshr: { | |||
| 5665 | bool IsFSHL = Intrinsic == Intrinsic::fshl; | |||
| 5666 | SDValue X = getValue(I.getArgOperand(0)); | |||
| 5667 | SDValue Y = getValue(I.getArgOperand(1)); | |||
| 5668 | SDValue Z = getValue(I.getArgOperand(2)); | |||
| 5669 | EVT VT = X.getValueType(); | |||
| 5670 | ||||
| 5671 | // TODO: When X == Y, this is rotate. Create the node directly if legal. | |||
| 5672 | ||||
| 5673 | // Get the shift amount and inverse shift amount, modulo the bit-width. | |||
| 5674 | SDValue BitWidthC = DAG.getConstant(VT.getScalarSizeInBits(), sdl, VT); | |||
| 5675 | SDValue ShAmt = DAG.getNode(ISD::UREM, sdl, VT, Z, BitWidthC); | |||
| 5676 | SDValue NegZ = DAG.getNode(ISD::SUB, sdl, VT, BitWidthC, Z); | |||
| 5677 | SDValue InvShAmt = DAG.getNode(ISD::UREM, sdl, VT, NegZ, BitWidthC); | |||
| 5678 | ||||
| 5679 | // fshl: (X << (Z % BW)) | (Y >> ((BW - Z) % BW)) | |||
| 5680 | // fshr: (X << ((BW - Z) % BW)) | (Y >> (Z % BW)) | |||
| 5681 | SDValue ShX = DAG.getNode(ISD::SHL, sdl, VT, X, IsFSHL ? ShAmt : InvShAmt); | |||
| 5682 | SDValue ShY = DAG.getNode(ISD::SRL, sdl, VT, Y, IsFSHL ? InvShAmt : ShAmt); | |||
| 5683 | SDValue Res = DAG.getNode(ISD::OR, sdl, VT, ShX, ShY); | |||
| 5684 | ||||
| 5685 | // If (Z % BW == 0), then (BW - Z) % BW is also zero, so the result would | |||
| 5686 | // be X | Y. If X == Y (rotate), that's fine. If not, we have to select. | |||
| 5687 | if (X != Y) { | |||
| 5688 | SDValue Zero = DAG.getConstant(0, sdl, VT); | |||
| 5689 | EVT CCVT = MVT::i1; | |||
| 5690 | if (VT.isVector()) | |||
| 5691 | CCVT = EVT::getVectorVT(*Context, CCVT, VT.getVectorNumElements()); | |||
| 5692 | // For fshl, 0 shift returns the 1st arg (X). | |||
| 5693 | // For fshr, 0 shift returns the 2nd arg (Y). | |||
| 5694 | SDValue IsZeroShift = DAG.getSetCC(sdl, CCVT, ShAmt, Zero, ISD::SETEQ); | |||
| 5695 | Res = DAG.getSelect(sdl, VT, IsZeroShift, IsFSHL ? X : Y, Res); | |||
| 5696 | } | |||
| 5697 | setValue(&I, Res); | |||
| 5698 | return nullptr; | |||
| 5699 | } | |||
| 5700 | case Intrinsic::stacksave: { | |||
| 5701 | SDValue Op = getRoot(); | |||
| 5702 | Res = DAG.getNode( | |||
| 5703 | ISD::STACKSAVE, sdl, | |||
| 5704 | DAG.getVTList(TLI.getPointerTy(DAG.getDataLayout()), MVT::Other), Op); | |||
| 5705 | setValue(&I, Res); | |||
| 5706 | DAG.setRoot(Res.getValue(1)); | |||
| 5707 | return nullptr; | |||
| 5708 | } | |||
| 5709 | case Intrinsic::stackrestore: | |||
| 5710 | Res = getValue(I.getArgOperand(0)); | |||
| 5711 | DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, sdl, MVT::Other, getRoot(), Res)); | |||
| 5712 | return nullptr; | |||
| 5713 | case Intrinsic::get_dynamic_area_offset: { | |||
| 5714 | SDValue Op = getRoot(); | |||
| 5715 | EVT PtrTy = TLI.getPointerTy(DAG.getDataLayout()); | |||
| 5716 | EVT ResTy = TLI.getValueType(DAG.getDataLayout(), I.getType()); | |||
| 5717 | // Result type for @llvm.get.dynamic.area.offset should match PtrTy for | |||
| 5718 | // target. | |||
| 5719 | if (PtrTy != ResTy) | |||
| 5720 | report_fatal_error("Wrong result type for @llvm.get.dynamic.area.offset" | |||
| 5721 | " intrinsic!"); | |||
| 5722 | Res = DAG.getNode(ISD::GET_DYNAMIC_AREA_OFFSET, sdl, DAG.getVTList(ResTy), | |||
| 5723 | Op); | |||
| 5724 | DAG.setRoot(Op); | |||
| 5725 | setValue(&I, Res); | |||
| 5726 | return nullptr; | |||
| 5727 | } | |||
| 5728 | case Intrinsic::stackguard: { | |||
| 5729 | EVT PtrTy = TLI.getPointerTy(DAG.getDataLayout()); | |||
| 5730 | MachineFunction &MF = DAG.getMachineFunction(); | |||
| 5731 | const Module &M = *MF.getFunction().getParent(); | |||
| 5732 | SDValue Chain = getRoot(); | |||
| 5733 | if (TLI.useLoadStackGuardNode()) { | |||
| 5734 | Res = getLoadStackGuard(DAG, sdl, Chain); | |||
| 5735 | } else { | |||
| 5736 | const Value *Global = TLI.getSDagStackGuard(M); | |||
| 5737 | unsigned Align = DL->getPrefTypeAlignment(Global->getType()); | |||
| 5738 | Res = DAG.getLoad(PtrTy, sdl, Chain, getValue(Global), | |||
| 5739 | MachinePointerInfo(Global, 0), Align, | |||
| 5740 | MachineMemOperand::MOVolatile); | |||
| 5741 | } | |||
| 5742 | if (TLI.useStackGuardXorFP()) | |||
| 5743 | Res = TLI.emitStackGuardXorFP(DAG, Res, sdl); | |||
| 5744 | DAG.setRoot(Chain); | |||
| 5745 | setValue(&I, Res); | |||
| 5746 | return nullptr; | |||
| 5747 | } | |||
| 5748 | case Intrinsic::stackprotector: { | |||
| 5749 | // Emit code into the DAG to store the stack guard onto the stack. | |||
| 5750 | MachineFunction &MF = DAG.getMachineFunction(); | |||
| 5751 | MachineFrameInfo &MFI = MF.getFrameInfo(); | |||
| 5752 | EVT PtrTy = TLI.getPointerTy(DAG.getDataLayout()); | |||
| 5753 | SDValue Src, Chain = getRoot(); | |||
| 5754 | ||||
| 5755 | if (TLI.useLoadStackGuardNode()) | |||
| 5756 | Src = getLoadStackGuard(DAG, sdl, Chain); | |||
| 5757 | else | |||
| 5758 | Src = getValue(I.getArgOperand(0)); // The guard's value. | |||
| 5759 | ||||
| 5760 | AllocaInst *Slot = cast<AllocaInst>(I.getArgOperand(1)); | |||
| 5761 | ||||
| 5762 | int FI = FuncInfo.StaticAllocaMap[Slot]; | |||
| 5763 | MFI.setStackProtectorIndex(FI); | |||
| 5764 | ||||
| 5765 | SDValue FIN = DAG.getFrameIndex(FI, PtrTy); | |||
| 5766 | ||||
| 5767 | // Store the stack protector onto the stack. | |||
| 5768 | Res = DAG.getStore(Chain, sdl, Src, FIN, MachinePointerInfo::getFixedStack( | |||
| 5769 | DAG.getMachineFunction(), FI), | |||
| 5770 | /* Alignment = */ 0, MachineMemOperand::MOVolatile); | |||
| 5771 | setValue(&I, Res); | |||
| 5772 | DAG.setRoot(Res); | |||
| 5773 | return nullptr; | |||
| 5774 | } | |||
| 5775 | case Intrinsic::objectsize: { | |||
| 5776 | // If we don't know by now, we're never going to know. | |||
| 5777 | ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(1)); | |||
| 5778 | ||||
| 5779 | assert(CI && "Non-constant type in __builtin_object_size?")(static_cast <bool> (CI && "Non-constant type in __builtin_object_size?" ) ? void (0) : __assert_fail ("CI && \"Non-constant type in __builtin_object_size?\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 5779, __extension__ __PRETTY_FUNCTION__)); | |||
| 5780 | ||||
| 5781 | SDValue Arg = getValue(I.getCalledValue()); | |||
| 5782 | EVT Ty = Arg.getValueType(); | |||
| 5783 | ||||
| 5784 | if (CI->isZero()) | |||
| 5785 | Res = DAG.getConstant(-1ULL, sdl, Ty); | |||
| 5786 | else | |||
| 5787 | Res = DAG.getConstant(0, sdl, Ty); | |||
| 5788 | ||||
| 5789 | setValue(&I, Res); | |||
| 5790 | return nullptr; | |||
| 5791 | } | |||
| 5792 | case Intrinsic::annotation: | |||
| 5793 | case Intrinsic::ptr_annotation: | |||
| 5794 | case Intrinsic::launder_invariant_group: | |||
| 5795 | case Intrinsic::strip_invariant_group: | |||
| 5796 | // Drop the intrinsic, but forward the value | |||
| 5797 | setValue(&I, getValue(I.getOperand(0))); | |||
| 5798 | return nullptr; | |||
| 5799 | case Intrinsic::assume: | |||
| 5800 | case Intrinsic::var_annotation: | |||
| 5801 | case Intrinsic::sideeffect: | |||
| 5802 | // Discard annotate attributes, assumptions, and artificial side-effects. | |||
| 5803 | return nullptr; | |||
| 5804 | ||||
| 5805 | case Intrinsic::codeview_annotation: { | |||
| 5806 | // Emit a label associated with this metadata. | |||
| 5807 | MachineFunction &MF = DAG.getMachineFunction(); | |||
| 5808 | MCSymbol *Label = | |||
| 5809 | MF.getMMI().getContext().createTempSymbol("annotation", true); | |||
| 5810 | Metadata *MD = cast<MetadataAsValue>(I.getArgOperand(0))->getMetadata(); | |||
| 5811 | MF.addCodeViewAnnotation(Label, cast<MDNode>(MD)); | |||
| 5812 | Res = DAG.getLabelNode(ISD::ANNOTATION_LABEL, sdl, getRoot(), Label); | |||
| 5813 | DAG.setRoot(Res); | |||
| 5814 | return nullptr; | |||
| 5815 | } | |||
| 5816 | ||||
| 5817 | case Intrinsic::init_trampoline: { | |||
| 5818 | const Function *F = cast<Function>(I.getArgOperand(1)->stripPointerCasts()); | |||
| 5819 | ||||
| 5820 | SDValue Ops[6]; | |||
| 5821 | Ops[0] = getRoot(); | |||
| 5822 | Ops[1] = getValue(I.getArgOperand(0)); | |||
| 5823 | Ops[2] = getValue(I.getArgOperand(1)); | |||
| 5824 | Ops[3] = getValue(I.getArgOperand(2)); | |||
| 5825 | Ops[4] = DAG.getSrcValue(I.getArgOperand(0)); | |||
| 5826 | Ops[5] = DAG.getSrcValue(F); | |||
| 5827 | ||||
| 5828 | Res = DAG.getNode(ISD::INIT_TRAMPOLINE, sdl, MVT::Other, Ops); | |||
| 5829 | ||||
| 5830 | DAG.setRoot(Res); | |||
| 5831 | return nullptr; | |||
| 5832 | } | |||
| 5833 | case Intrinsic::adjust_trampoline: | |||
| 5834 | setValue(&I, DAG.getNode(ISD::ADJUST_TRAMPOLINE, sdl, | |||
| 5835 | TLI.getPointerTy(DAG.getDataLayout()), | |||
| 5836 | getValue(I.getArgOperand(0)))); | |||
| 5837 | return nullptr; | |||
| 5838 | case Intrinsic::gcroot: { | |||
| 5839 | assert(DAG.getMachineFunction().getFunction().hasGC() &&(static_cast <bool> (DAG.getMachineFunction().getFunction ().hasGC() && "only valid in functions with gc specified, enforced by Verifier" ) ? void (0) : __assert_fail ("DAG.getMachineFunction().getFunction().hasGC() && \"only valid in functions with gc specified, enforced by Verifier\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 5840, __extension__ __PRETTY_FUNCTION__)) | |||
| 5840 | "only valid in functions with gc specified, enforced by Verifier")(static_cast <bool> (DAG.getMachineFunction().getFunction ().hasGC() && "only valid in functions with gc specified, enforced by Verifier" ) ? void (0) : __assert_fail ("DAG.getMachineFunction().getFunction().hasGC() && \"only valid in functions with gc specified, enforced by Verifier\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 5840, __extension__ __PRETTY_FUNCTION__)); | |||
| 5841 | assert(GFI && "implied by previous")(static_cast <bool> (GFI && "implied by previous" ) ? void (0) : __assert_fail ("GFI && \"implied by previous\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 5841, __extension__ __PRETTY_FUNCTION__)); | |||
| 5842 | const Value *Alloca = I.getArgOperand(0)->stripPointerCasts(); | |||
| 5843 | const Constant *TypeMap = cast<Constant>(I.getArgOperand(1)); | |||
| 5844 | ||||
| 5845 | FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).getNode()); | |||
| 5846 | GFI->addStackRoot(FI->getIndex(), TypeMap); | |||
| 5847 | return nullptr; | |||
| 5848 | } | |||
| 5849 | case Intrinsic::gcread: | |||
| 5850 | case Intrinsic::gcwrite: | |||
| 5851 | llvm_unreachable("GC failed to lower gcread/gcwrite intrinsics!")::llvm::llvm_unreachable_internal("GC failed to lower gcread/gcwrite intrinsics!" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 5851); | |||
| 5852 | case Intrinsic::flt_rounds: | |||
| 5853 | setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, sdl, MVT::i32)); | |||
| 5854 | return nullptr; | |||
| 5855 | ||||
| 5856 | case Intrinsic::expect: | |||
| 5857 | // Just replace __builtin_expect(exp, c) with EXP. | |||
| 5858 | setValue(&I, getValue(I.getArgOperand(0))); | |||
| 5859 | return nullptr; | |||
| 5860 | ||||
| 5861 | case Intrinsic::debugtrap: | |||
| 5862 | case Intrinsic::trap: { | |||
| 5863 | StringRef TrapFuncName = | |||
| 5864 | I.getAttributes() | |||
| 5865 | .getAttribute(AttributeList::FunctionIndex, "trap-func-name") | |||
| 5866 | .getValueAsString(); | |||
| 5867 | if (TrapFuncName.empty()) { | |||
| 5868 | ISD::NodeType Op = (Intrinsic == Intrinsic::trap) ? | |||
| 5869 | ISD::TRAP : ISD::DEBUGTRAP; | |||
| 5870 | DAG.setRoot(DAG.getNode(Op, sdl,MVT::Other, getRoot())); | |||
| 5871 | return nullptr; | |||
| 5872 | } | |||
| 5873 | TargetLowering::ArgListTy Args; | |||
| 5874 | ||||
| 5875 | TargetLowering::CallLoweringInfo CLI(DAG); | |||
| 5876 | CLI.setDebugLoc(sdl).setChain(getRoot()).setLibCallee( | |||
| 5877 | CallingConv::C, I.getType(), | |||
| 5878 | DAG.getExternalSymbol(TrapFuncName.data(), | |||
| 5879 | TLI.getPointerTy(DAG.getDataLayout())), | |||
| 5880 | std::move(Args)); | |||
| 5881 | ||||
| 5882 | std::pair<SDValue, SDValue> Result = TLI.LowerCallTo(CLI); | |||
| 5883 | DAG.setRoot(Result.second); | |||
| 5884 | return nullptr; | |||
| 5885 | } | |||
| 5886 | ||||
| 5887 | case Intrinsic::uadd_with_overflow: | |||
| 5888 | case Intrinsic::sadd_with_overflow: | |||
| 5889 | case Intrinsic::usub_with_overflow: | |||
| 5890 | case Intrinsic::ssub_with_overflow: | |||
| 5891 | case Intrinsic::umul_with_overflow: | |||
| 5892 | case Intrinsic::smul_with_overflow: { | |||
| 5893 | ISD::NodeType Op; | |||
| 5894 | switch (Intrinsic) { | |||
| 5895 | default: llvm_unreachable("Impossible intrinsic")::llvm::llvm_unreachable_internal("Impossible intrinsic", "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 5895); // Can't reach here. | |||
| 5896 | case Intrinsic::uadd_with_overflow: Op = ISD::UADDO; break; | |||
| 5897 | case Intrinsic::sadd_with_overflow: Op = ISD::SADDO; break; | |||
| 5898 | case Intrinsic::usub_with_overflow: Op = ISD::USUBO; break; | |||
| 5899 | case Intrinsic::ssub_with_overflow: Op = ISD::SSUBO; break; | |||
| 5900 | case Intrinsic::umul_with_overflow: Op = ISD::UMULO; break; | |||
| 5901 | case Intrinsic::smul_with_overflow: Op = ISD::SMULO; break; | |||
| 5902 | } | |||
| 5903 | SDValue Op1 = getValue(I.getArgOperand(0)); | |||
| 5904 | SDValue Op2 = getValue(I.getArgOperand(1)); | |||
| 5905 | ||||
| 5906 | SDVTList VTs = DAG.getVTList(Op1.getValueType(), MVT::i1); | |||
| 5907 | setValue(&I, DAG.getNode(Op, sdl, VTs, Op1, Op2)); | |||
| 5908 | return nullptr; | |||
| 5909 | } | |||
| 5910 | case Intrinsic::prefetch: { | |||
| 5911 | SDValue Ops[5]; | |||
| 5912 | unsigned rw = cast<ConstantInt>(I.getArgOperand(1))->getZExtValue(); | |||
| 5913 | auto Flags = rw == 0 ? MachineMemOperand::MOLoad :MachineMemOperand::MOStore; | |||
| 5914 | Ops[0] = DAG.getRoot(); | |||
| 5915 | Ops[1] = getValue(I.getArgOperand(0)); | |||
| 5916 | Ops[2] = getValue(I.getArgOperand(1)); | |||
| 5917 | Ops[3] = getValue(I.getArgOperand(2)); | |||
| 5918 | Ops[4] = getValue(I.getArgOperand(3)); | |||
| 5919 | SDValue Result = DAG.getMemIntrinsicNode(ISD::PREFETCH, sdl, | |||
| 5920 | DAG.getVTList(MVT::Other), Ops, | |||
| 5921 | EVT::getIntegerVT(*Context, 8), | |||
| 5922 | MachinePointerInfo(I.getArgOperand(0)), | |||
| 5923 | 0, /* align */ | |||
| 5924 | Flags); | |||
| 5925 | ||||
| 5926 | // Chain the prefetch in parallell with any pending loads, to stay out of | |||
| 5927 | // the way of later optimizations. | |||
| 5928 | PendingLoads.push_back(Result); | |||
| 5929 | Result = getRoot(); | |||
| 5930 | DAG.setRoot(Result); | |||
| 5931 | return nullptr; | |||
| 5932 | } | |||
| 5933 | case Intrinsic::lifetime_start: | |||
| 5934 | case Intrinsic::lifetime_end: { | |||
| 5935 | bool IsStart = (Intrinsic == Intrinsic::lifetime_start); | |||
| 5936 | // Stack coloring is not enabled in O0, discard region information. | |||
| 5937 | if (TM.getOptLevel() == CodeGenOpt::None) | |||
| 5938 | return nullptr; | |||
| 5939 | ||||
| 5940 | SmallVector<Value *, 4> Allocas; | |||
| 5941 | GetUnderlyingObjects(I.getArgOperand(1), Allocas, *DL); | |||
| 5942 | ||||
| 5943 | for (SmallVectorImpl<Value*>::iterator Object = Allocas.begin(), | |||
| 5944 | E = Allocas.end(); Object != E; ++Object) { | |||
| 5945 | AllocaInst *LifetimeObject = dyn_cast_or_null<AllocaInst>(*Object); | |||
| 5946 | ||||
| 5947 | // Could not find an Alloca. | |||
| 5948 | if (!LifetimeObject) | |||
| 5949 | continue; | |||
| 5950 | ||||
| 5951 | // First check that the Alloca is static, otherwise it won't have a | |||
| 5952 | // valid frame index. | |||
| 5953 | auto SI = FuncInfo.StaticAllocaMap.find(LifetimeObject); | |||
| 5954 | if (SI == FuncInfo.StaticAllocaMap.end()) | |||
| 5955 | return nullptr; | |||
| 5956 | ||||
| 5957 | int FI = SI->second; | |||
| 5958 | ||||
| 5959 | SDValue Ops[2]; | |||
| 5960 | Ops[0] = getRoot(); | |||
| 5961 | Ops[1] = | |||
| 5962 | DAG.getFrameIndex(FI, TLI.getFrameIndexTy(DAG.getDataLayout()), true); | |||
| 5963 | unsigned Opcode = (IsStart ? ISD::LIFETIME_START : ISD::LIFETIME_END); | |||
| 5964 | ||||
| 5965 | Res = DAG.getNode(Opcode, sdl, MVT::Other, Ops); | |||
| 5966 | DAG.setRoot(Res); | |||
| 5967 | } | |||
| 5968 | return nullptr; | |||
| 5969 | } | |||
| 5970 | case Intrinsic::invariant_start: | |||
| 5971 | // Discard region information. | |||
| 5972 | setValue(&I, DAG.getUNDEF(TLI.getPointerTy(DAG.getDataLayout()))); | |||
| 5973 | return nullptr; | |||
| 5974 | case Intrinsic::invariant_end: | |||
| 5975 | // Discard region information. | |||
| 5976 | return nullptr; | |||
| 5977 | case Intrinsic::clear_cache: | |||
| 5978 | return TLI.getClearCacheBuiltinName(); | |||
| 5979 | case Intrinsic::donothing: | |||
| 5980 | // ignore | |||
| 5981 | return nullptr; | |||
| 5982 | case Intrinsic::experimental_stackmap: | |||
| 5983 | visitStackmap(I); | |||
| 5984 | return nullptr; | |||
| 5985 | case Intrinsic::experimental_patchpoint_void: | |||
| 5986 | case Intrinsic::experimental_patchpoint_i64: | |||
| 5987 | visitPatchpoint(&I); | |||
| 5988 | return nullptr; | |||
| 5989 | case Intrinsic::experimental_gc_statepoint: | |||
| 5990 | LowerStatepoint(ImmutableStatepoint(&I)); | |||
| 5991 | return nullptr; | |||
| 5992 | case Intrinsic::experimental_gc_result: | |||
| 5993 | visitGCResult(cast<GCResultInst>(I)); | |||
| 5994 | return nullptr; | |||
| 5995 | case Intrinsic::experimental_gc_relocate: | |||
| 5996 | visitGCRelocate(cast<GCRelocateInst>(I)); | |||
| 5997 | return nullptr; | |||
| 5998 | case Intrinsic::instrprof_increment: | |||
| 5999 | llvm_unreachable("instrprof failed to lower an increment")::llvm::llvm_unreachable_internal("instrprof failed to lower an increment" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 5999); | |||
| 6000 | case Intrinsic::instrprof_value_profile: | |||
| 6001 | llvm_unreachable("instrprof failed to lower a value profiling call")::llvm::llvm_unreachable_internal("instrprof failed to lower a value profiling call" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 6001); | |||
| 6002 | case Intrinsic::localescape: { | |||
| 6003 | MachineFunction &MF = DAG.getMachineFunction(); | |||
| 6004 | const TargetInstrInfo *TII = DAG.getSubtarget().getInstrInfo(); | |||
| 6005 | ||||
| 6006 | // Directly emit some LOCAL_ESCAPE machine instrs. Label assignment emission | |||
| 6007 | // is the same on all targets. | |||
| 6008 | for (unsigned Idx = 0, E = I.getNumArgOperands(); Idx < E; ++Idx) { | |||
| 6009 | Value *Arg = I.getArgOperand(Idx)->stripPointerCasts(); | |||
| 6010 | if (isa<ConstantPointerNull>(Arg)) | |||
| 6011 | continue; // Skip null pointers. They represent a hole in index space. | |||
| 6012 | AllocaInst *Slot = cast<AllocaInst>(Arg); | |||
| 6013 | assert(FuncInfo.StaticAllocaMap.count(Slot) &&(static_cast <bool> (FuncInfo.StaticAllocaMap.count(Slot ) && "can only escape static allocas") ? void (0) : __assert_fail ("FuncInfo.StaticAllocaMap.count(Slot) && \"can only escape static allocas\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 6014, __extension__ __PRETTY_FUNCTION__)) | |||
| 6014 | "can only escape static allocas")(static_cast <bool> (FuncInfo.StaticAllocaMap.count(Slot ) && "can only escape static allocas") ? void (0) : __assert_fail ("FuncInfo.StaticAllocaMap.count(Slot) && \"can only escape static allocas\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 6014, __extension__ __PRETTY_FUNCTION__)); | |||
| 6015 | int FI = FuncInfo.StaticAllocaMap[Slot]; | |||
| 6016 | MCSymbol *FrameAllocSym = | |||
| 6017 | MF.getMMI().getContext().getOrCreateFrameAllocSymbol( | |||
| 6018 | GlobalValue::dropLLVMManglingEscape(MF.getName()), Idx); | |||
| 6019 | BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, dl, | |||
| 6020 | TII->get(TargetOpcode::LOCAL_ESCAPE)) | |||
| 6021 | .addSym(FrameAllocSym) | |||
| 6022 | .addFrameIndex(FI); | |||
| 6023 | } | |||
| 6024 | ||||
| 6025 | return nullptr; | |||
| 6026 | } | |||
| 6027 | ||||
| 6028 | case Intrinsic::localrecover: { | |||
| 6029 | // i8* @llvm.localrecover(i8* %fn, i8* %fp, i32 %idx) | |||
| 6030 | MachineFunction &MF = DAG.getMachineFunction(); | |||
| 6031 | MVT PtrVT = TLI.getPointerTy(DAG.getDataLayout(), 0); | |||
| 6032 | ||||
| 6033 | // Get the symbol that defines the frame offset. | |||
| 6034 | auto *Fn = cast<Function>(I.getArgOperand(0)->stripPointerCasts()); | |||
| 6035 | auto *Idx = cast<ConstantInt>(I.getArgOperand(2)); | |||
| 6036 | unsigned IdxVal = | |||
| 6037 | unsigned(Idx->getLimitedValue(std::numeric_limits<int>::max())); | |||
| 6038 | MCSymbol *FrameAllocSym = | |||
| 6039 | MF.getMMI().getContext().getOrCreateFrameAllocSymbol( | |||
| 6040 | GlobalValue::dropLLVMManglingEscape(Fn->getName()), IdxVal); | |||
| 6041 | ||||
| 6042 | // Create a MCSymbol for the label to avoid any target lowering | |||
| 6043 | // that would make this PC relative. | |||
| 6044 | SDValue OffsetSym = DAG.getMCSymbol(FrameAllocSym, PtrVT); | |||
| 6045 | SDValue OffsetVal = | |||
| 6046 | DAG.getNode(ISD::LOCAL_RECOVER, sdl, PtrVT, OffsetSym); | |||
| 6047 | ||||
| 6048 | // Add the offset to the FP. | |||
| 6049 | Value *FP = I.getArgOperand(1); | |||
| 6050 | SDValue FPVal = getValue(FP); | |||
| 6051 | SDValue Add = DAG.getNode(ISD::ADD, sdl, PtrVT, FPVal, OffsetVal); | |||
| 6052 | setValue(&I, Add); | |||
| 6053 | ||||
| 6054 | return nullptr; | |||
| 6055 | } | |||
| 6056 | ||||
| 6057 | case Intrinsic::eh_exceptionpointer: | |||
| 6058 | case Intrinsic::eh_exceptioncode: { | |||
| 6059 | // Get the exception pointer vreg, copy from it, and resize it to fit. | |||
| 6060 | const auto *CPI = cast<CatchPadInst>(I.getArgOperand(0)); | |||
| 6061 | MVT PtrVT = TLI.getPointerTy(DAG.getDataLayout()); | |||
| 6062 | const TargetRegisterClass *PtrRC = TLI.getRegClassFor(PtrVT); | |||
| 6063 | unsigned VReg = FuncInfo.getCatchPadExceptionPointerVReg(CPI, PtrRC); | |||
| 6064 | SDValue N = | |||
| 6065 | DAG.getCopyFromReg(DAG.getEntryNode(), getCurSDLoc(), VReg, PtrVT); | |||
| 6066 | if (Intrinsic == Intrinsic::eh_exceptioncode) | |||
| 6067 | N = DAG.getZExtOrTrunc(N, getCurSDLoc(), MVT::i32); | |||
| 6068 | setValue(&I, N); | |||
| 6069 | return nullptr; | |||
| 6070 | } | |||
| 6071 | case Intrinsic::xray_customevent: { | |||
| 6072 | // Here we want to make sure that the intrinsic behaves as if it has a | |||
| 6073 | // specific calling convention, and only for x86_64. | |||
| 6074 | // FIXME: Support other platforms later. | |||
| 6075 | const auto &Triple = DAG.getTarget().getTargetTriple(); | |||
| 6076 | if (Triple.getArch() != Triple::x86_64 || !Triple.isOSLinux()) | |||
| 6077 | return nullptr; | |||
| 6078 | ||||
| 6079 | SDLoc DL = getCurSDLoc(); | |||
| 6080 | SmallVector<SDValue, 8> Ops; | |||
| 6081 | ||||
| 6082 | // We want to say that we always want the arguments in registers. | |||
| 6083 | SDValue LogEntryVal = getValue(I.getArgOperand(0)); | |||
| 6084 | SDValue StrSizeVal = getValue(I.getArgOperand(1)); | |||
| 6085 | SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); | |||
| 6086 | SDValue Chain = getRoot(); | |||
| 6087 | Ops.push_back(LogEntryVal); | |||
| 6088 | Ops.push_back(StrSizeVal); | |||
| 6089 | Ops.push_back(Chain); | |||
| 6090 | ||||
| 6091 | // We need to enforce the calling convention for the callsite, so that | |||
| 6092 | // argument ordering is enforced correctly, and that register allocation can | |||
| 6093 | // see that some registers may be assumed clobbered and have to preserve | |||
| 6094 | // them across calls to the intrinsic. | |||
| 6095 | MachineSDNode *MN = DAG.getMachineNode(TargetOpcode::PATCHABLE_EVENT_CALL, | |||
| 6096 | DL, NodeTys, Ops); | |||
| 6097 | SDValue patchableNode = SDValue(MN, 0); | |||
| 6098 | DAG.setRoot(patchableNode); | |||
| 6099 | setValue(&I, patchableNode); | |||
| 6100 | return nullptr; | |||
| 6101 | } | |||
| 6102 | case Intrinsic::xray_typedevent: { | |||
| 6103 | // Here we want to make sure that the intrinsic behaves as if it has a | |||
| 6104 | // specific calling convention, and only for x86_64. | |||
| 6105 | // FIXME: Support other platforms later. | |||
| 6106 | const auto &Triple = DAG.getTarget().getTargetTriple(); | |||
| 6107 | if (Triple.getArch() != Triple::x86_64 || !Triple.isOSLinux()) | |||
| 6108 | return nullptr; | |||
| 6109 | ||||
| 6110 | SDLoc DL = getCurSDLoc(); | |||
| 6111 | SmallVector<SDValue, 8> Ops; | |||
| 6112 | ||||
| 6113 | // We want to say that we always want the arguments in registers. | |||
| 6114 | // It's unclear to me how manipulating the selection DAG here forces callers | |||
| 6115 | // to provide arguments in registers instead of on the stack. | |||
| 6116 | SDValue LogTypeId = getValue(I.getArgOperand(0)); | |||
| 6117 | SDValue LogEntryVal = getValue(I.getArgOperand(1)); | |||
| 6118 | SDValue StrSizeVal = getValue(I.getArgOperand(2)); | |||
| 6119 | SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); | |||
| 6120 | SDValue Chain = getRoot(); | |||
| 6121 | Ops.push_back(LogTypeId); | |||
| 6122 | Ops.push_back(LogEntryVal); | |||
| 6123 | Ops.push_back(StrSizeVal); | |||
| 6124 | Ops.push_back(Chain); | |||
| 6125 | ||||
| 6126 | // We need to enforce the calling convention for the callsite, so that | |||
| 6127 | // argument ordering is enforced correctly, and that register allocation can | |||
| 6128 | // see that some registers may be assumed clobbered and have to preserve | |||
| 6129 | // them across calls to the intrinsic. | |||
| 6130 | MachineSDNode *MN = DAG.getMachineNode( | |||
| 6131 | TargetOpcode::PATCHABLE_TYPED_EVENT_CALL, DL, NodeTys, Ops); | |||
| 6132 | SDValue patchableNode = SDValue(MN, 0); | |||
| 6133 | DAG.setRoot(patchableNode); | |||
| 6134 | setValue(&I, patchableNode); | |||
| 6135 | return nullptr; | |||
| 6136 | } | |||
| 6137 | case Intrinsic::experimental_deoptimize: | |||
| 6138 | LowerDeoptimizeCall(&I); | |||
| 6139 | return nullptr; | |||
| 6140 | ||||
| 6141 | case Intrinsic::experimental_vector_reduce_fadd: | |||
| 6142 | case Intrinsic::experimental_vector_reduce_fmul: | |||
| 6143 | case Intrinsic::experimental_vector_reduce_add: | |||
| 6144 | case Intrinsic::experimental_vector_reduce_mul: | |||
| 6145 | case Intrinsic::experimental_vector_reduce_and: | |||
| 6146 | case Intrinsic::experimental_vector_reduce_or: | |||
| 6147 | case Intrinsic::experimental_vector_reduce_xor: | |||
| 6148 | case Intrinsic::experimental_vector_reduce_smax: | |||
| 6149 | case Intrinsic::experimental_vector_reduce_smin: | |||
| 6150 | case Intrinsic::experimental_vector_reduce_umax: | |||
| 6151 | case Intrinsic::experimental_vector_reduce_umin: | |||
| 6152 | case Intrinsic::experimental_vector_reduce_fmax: | |||
| 6153 | case Intrinsic::experimental_vector_reduce_fmin: | |||
| 6154 | visitVectorReduce(I, Intrinsic); | |||
| 6155 | return nullptr; | |||
| 6156 | ||||
| 6157 | case Intrinsic::icall_branch_funnel: { | |||
| 6158 | SmallVector<SDValue, 16> Ops; | |||
| 6159 | Ops.push_back(DAG.getRoot()); | |||
| 6160 | Ops.push_back(getValue(I.getArgOperand(0))); | |||
| 6161 | ||||
| 6162 | int64_t Offset; | |||
| 6163 | auto *Base = dyn_cast<GlobalObject>(GetPointerBaseWithConstantOffset( | |||
| 6164 | I.getArgOperand(1), Offset, DAG.getDataLayout())); | |||
| 6165 | if (!Base) | |||
| 6166 | report_fatal_error( | |||
| 6167 | "llvm.icall.branch.funnel operand must be a GlobalValue"); | |||
| 6168 | Ops.push_back(DAG.getTargetGlobalAddress(Base, getCurSDLoc(), MVT::i64, 0)); | |||
| 6169 | ||||
| 6170 | struct BranchFunnelTarget { | |||
| 6171 | int64_t Offset; | |||
| 6172 | SDValue Target; | |||
| 6173 | }; | |||
| 6174 | SmallVector<BranchFunnelTarget, 8> Targets; | |||
| 6175 | ||||
| 6176 | for (unsigned Op = 1, N = I.getNumArgOperands(); Op != N; Op += 2) { | |||
| 6177 | auto *ElemBase = dyn_cast<GlobalObject>(GetPointerBaseWithConstantOffset( | |||
| 6178 | I.getArgOperand(Op), Offset, DAG.getDataLayout())); | |||
| 6179 | if (ElemBase != Base) | |||
| 6180 | report_fatal_error("all llvm.icall.branch.funnel operands must refer " | |||
| 6181 | "to the same GlobalValue"); | |||
| 6182 | ||||
| 6183 | SDValue Val = getValue(I.getArgOperand(Op + 1)); | |||
| 6184 | auto *GA = dyn_cast<GlobalAddressSDNode>(Val); | |||
| 6185 | if (!GA) | |||
| 6186 | report_fatal_error( | |||
| 6187 | "llvm.icall.branch.funnel operand must be a GlobalValue"); | |||
| 6188 | Targets.push_back({Offset, DAG.getTargetGlobalAddress( | |||
| 6189 | GA->getGlobal(), getCurSDLoc(), | |||
| 6190 | Val.getValueType(), GA->getOffset())}); | |||
| 6191 | } | |||
| 6192 | llvm::sort(Targets.begin(), Targets.end(), | |||
| 6193 | [](const BranchFunnelTarget &T1, const BranchFunnelTarget &T2) { | |||
| 6194 | return T1.Offset < T2.Offset; | |||
| 6195 | }); | |||
| 6196 | ||||
| 6197 | for (auto &T : Targets) { | |||
| 6198 | Ops.push_back(DAG.getTargetConstant(T.Offset, getCurSDLoc(), MVT::i32)); | |||
| 6199 | Ops.push_back(T.Target); | |||
| 6200 | } | |||
| 6201 | ||||
| 6202 | SDValue N(DAG.getMachineNode(TargetOpcode::ICALL_BRANCH_FUNNEL, | |||
| 6203 | getCurSDLoc(), MVT::Other, Ops), | |||
| 6204 | 0); | |||
| 6205 | DAG.setRoot(N); | |||
| 6206 | setValue(&I, N); | |||
| 6207 | HasTailCall = true; | |||
| 6208 | return nullptr; | |||
| 6209 | } | |||
| 6210 | ||||
| 6211 | case Intrinsic::wasm_landingpad_index: { | |||
| 6212 | // TODO store landing pad index in a map, which will be used when generating | |||
| 6213 | // LSDA information | |||
| 6214 | return nullptr; | |||
| 6215 | } | |||
| 6216 | } | |||
| 6217 | } | |||
| 6218 | ||||
| 6219 | void SelectionDAGBuilder::visitConstrainedFPIntrinsic( | |||
| 6220 | const ConstrainedFPIntrinsic &FPI) { | |||
| 6221 | SDLoc sdl = getCurSDLoc(); | |||
| 6222 | unsigned Opcode; | |||
| 6223 | switch (FPI.getIntrinsicID()) { | |||
| 6224 | default: llvm_unreachable("Impossible intrinsic")::llvm::llvm_unreachable_internal("Impossible intrinsic", "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 6224); // Can't reach here. | |||
| 6225 | case Intrinsic::experimental_constrained_fadd: | |||
| 6226 | Opcode = ISD::STRICT_FADD; | |||
| 6227 | break; | |||
| 6228 | case Intrinsic::experimental_constrained_fsub: | |||
| 6229 | Opcode = ISD::STRICT_FSUB; | |||
| 6230 | break; | |||
| 6231 | case Intrinsic::experimental_constrained_fmul: | |||
| 6232 | Opcode = ISD::STRICT_FMUL; | |||
| 6233 | break; | |||
| 6234 | case Intrinsic::experimental_constrained_fdiv: | |||
| 6235 | Opcode = ISD::STRICT_FDIV; | |||
| 6236 | break; | |||
| 6237 | case Intrinsic::experimental_constrained_frem: | |||
| 6238 | Opcode = ISD::STRICT_FREM; | |||
| 6239 | break; | |||
| 6240 | case Intrinsic::experimental_constrained_fma: | |||
| 6241 | Opcode = ISD::STRICT_FMA; | |||
| 6242 | break; | |||
| 6243 | case Intrinsic::experimental_constrained_sqrt: | |||
| 6244 | Opcode = ISD::STRICT_FSQRT; | |||
| 6245 | break; | |||
| 6246 | case Intrinsic::experimental_constrained_pow: | |||
| 6247 | Opcode = ISD::STRICT_FPOW; | |||
| 6248 | break; | |||
| 6249 | case Intrinsic::experimental_constrained_powi: | |||
| 6250 | Opcode = ISD::STRICT_FPOWI; | |||
| 6251 | break; | |||
| 6252 | case Intrinsic::experimental_constrained_sin: | |||
| 6253 | Opcode = ISD::STRICT_FSIN; | |||
| 6254 | break; | |||
| 6255 | case Intrinsic::experimental_constrained_cos: | |||
| 6256 | Opcode = ISD::STRICT_FCOS; | |||
| 6257 | break; | |||
| 6258 | case Intrinsic::experimental_constrained_exp: | |||
| 6259 | Opcode = ISD::STRICT_FEXP; | |||
| 6260 | break; | |||
| 6261 | case Intrinsic::experimental_constrained_exp2: | |||
| 6262 | Opcode = ISD::STRICT_FEXP2; | |||
| 6263 | break; | |||
| 6264 | case Intrinsic::experimental_constrained_log: | |||
| 6265 | Opcode = ISD::STRICT_FLOG; | |||
| 6266 | break; | |||
| 6267 | case Intrinsic::experimental_constrained_log10: | |||
| 6268 | Opcode = ISD::STRICT_FLOG10; | |||
| 6269 | break; | |||
| 6270 | case Intrinsic::experimental_constrained_log2: | |||
| 6271 | Opcode = ISD::STRICT_FLOG2; | |||
| 6272 | break; | |||
| 6273 | case Intrinsic::experimental_constrained_rint: | |||
| 6274 | Opcode = ISD::STRICT_FRINT; | |||
| 6275 | break; | |||
| 6276 | case Intrinsic::experimental_constrained_nearbyint: | |||
| 6277 | Opcode = ISD::STRICT_FNEARBYINT; | |||
| 6278 | break; | |||
| 6279 | } | |||
| 6280 | const TargetLowering &TLI = DAG.getTargetLoweringInfo(); | |||
| 6281 | SDValue Chain = getRoot(); | |||
| 6282 | SmallVector<EVT, 4> ValueVTs; | |||
| 6283 | ComputeValueVTs(TLI, DAG.getDataLayout(), FPI.getType(), ValueVTs); | |||
| 6284 | ValueVTs.push_back(MVT::Other); // Out chain | |||
| 6285 | ||||
| 6286 | SDVTList VTs = DAG.getVTList(ValueVTs); | |||
| 6287 | SDValue Result; | |||
| 6288 | if (FPI.isUnaryOp()) | |||
| 6289 | Result = DAG.getNode(Opcode, sdl, VTs, | |||
| 6290 | { Chain, getValue(FPI.getArgOperand(0)) }); | |||
| 6291 | else if (FPI.isTernaryOp()) | |||
| 6292 | Result = DAG.getNode(Opcode, sdl, VTs, | |||
| 6293 | { Chain, getValue(FPI.getArgOperand(0)), | |||
| 6294 | getValue(FPI.getArgOperand(1)), | |||
| 6295 | getValue(FPI.getArgOperand(2)) }); | |||
| 6296 | else | |||
| 6297 | Result = DAG.getNode(Opcode, sdl, VTs, | |||
| 6298 | { Chain, getValue(FPI.getArgOperand(0)), | |||
| 6299 | getValue(FPI.getArgOperand(1)) }); | |||
| 6300 | ||||
| 6301 | assert(Result.getNode()->getNumValues() == 2)(static_cast <bool> (Result.getNode()->getNumValues( ) == 2) ? void (0) : __assert_fail ("Result.getNode()->getNumValues() == 2" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 6301, __extension__ __PRETTY_FUNCTION__)); | |||
| 6302 | SDValue OutChain = Result.getValue(1); | |||
| 6303 | DAG.setRoot(OutChain); | |||
| 6304 | SDValue FPResult = Result.getValue(0); | |||
| 6305 | setValue(&FPI, FPResult); | |||
| 6306 | } | |||
| 6307 | ||||
| 6308 | std::pair<SDValue, SDValue> | |||
| 6309 | SelectionDAGBuilder::lowerInvokable(TargetLowering::CallLoweringInfo &CLI, | |||
| 6310 | const BasicBlock *EHPadBB) { | |||
| 6311 | MachineFunction &MF = DAG.getMachineFunction(); | |||
| 6312 | MachineModuleInfo &MMI = MF.getMMI(); | |||
| 6313 | MCSymbol *BeginLabel = nullptr; | |||
| 6314 | ||||
| 6315 | if (EHPadBB) { | |||
| 6316 | // Insert a label before the invoke call to mark the try range. This can be | |||
| 6317 | // used to detect deletion of the invoke via the MachineModuleInfo. | |||
| 6318 | BeginLabel = MMI.getContext().createTempSymbol(); | |||
| 6319 | ||||
| 6320 | // For SjLj, keep track of which landing pads go with which invokes | |||
| 6321 | // so as to maintain the ordering of pads in the LSDA. | |||
| 6322 | unsigned CallSiteIndex = MMI.getCurrentCallSite(); | |||
| 6323 | if (CallSiteIndex) { | |||
| 6324 | MF.setCallSiteBeginLabel(BeginLabel, CallSiteIndex); | |||
| 6325 | LPadToCallSiteMap[FuncInfo.MBBMap[EHPadBB]].push_back(CallSiteIndex); | |||
| 6326 | ||||
| 6327 | // Now that the call site is handled, stop tracking it. | |||
| 6328 | MMI.setCurrentCallSite(0); | |||
| 6329 | } | |||
| 6330 | ||||
| 6331 | // Both PendingLoads and PendingExports must be flushed here; | |||
| 6332 | // this call might not return. | |||
| 6333 | (void)getRoot(); | |||
| 6334 | DAG.setRoot(DAG.getEHLabel(getCurSDLoc(), getControlRoot(), BeginLabel)); | |||
| 6335 | ||||
| 6336 | CLI.setChain(getRoot()); | |||
| 6337 | } | |||
| 6338 | const TargetLowering &TLI = DAG.getTargetLoweringInfo(); | |||
| 6339 | std::pair<SDValue, SDValue> Result = TLI.LowerCallTo(CLI); | |||
| 6340 | ||||
| 6341 | assert((CLI.IsTailCall || Result.second.getNode()) &&(static_cast <bool> ((CLI.IsTailCall || Result.second.getNode ()) && "Non-null chain expected with non-tail call!") ? void (0) : __assert_fail ("(CLI.IsTailCall || Result.second.getNode()) && \"Non-null chain expected with non-tail call!\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 6342, __extension__ __PRETTY_FUNCTION__)) | |||
| 6342 | "Non-null chain expected with non-tail call!")(static_cast <bool> ((CLI.IsTailCall || Result.second.getNode ()) && "Non-null chain expected with non-tail call!") ? void (0) : __assert_fail ("(CLI.IsTailCall || Result.second.getNode()) && \"Non-null chain expected with non-tail call!\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 6342, __extension__ __PRETTY_FUNCTION__)); | |||
| 6343 | assert((Result.second.getNode() || !Result.first.getNode()) &&(static_cast <bool> ((Result.second.getNode() || !Result .first.getNode()) && "Null value expected with tail call!" ) ? void (0) : __assert_fail ("(Result.second.getNode() || !Result.first.getNode()) && \"Null value expected with tail call!\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 6344, __extension__ __PRETTY_FUNCTION__)) | |||
| 6344 | "Null value expected with tail call!")(static_cast <bool> ((Result.second.getNode() || !Result .first.getNode()) && "Null value expected with tail call!" ) ? void (0) : __assert_fail ("(Result.second.getNode() || !Result.first.getNode()) && \"Null value expected with tail call!\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 6344, __extension__ __PRETTY_FUNCTION__)); | |||
| 6345 | ||||
| 6346 | if (!Result.second.getNode()) { | |||
| 6347 | // As a special case, a null chain means that a tail call has been emitted | |||
| 6348 | // and the DAG root is already updated. | |||
| 6349 | HasTailCall = true; | |||
| 6350 | ||||
| 6351 | // Since there's no actual continuation from this block, nothing can be | |||
| 6352 | // relying on us setting vregs for them. | |||
| 6353 | PendingExports.clear(); | |||
| 6354 | } else { | |||
| 6355 | DAG.setRoot(Result.second); | |||
| 6356 | } | |||
| 6357 | ||||
| 6358 | if (EHPadBB) { | |||
| 6359 | // Insert a label at the end of the invoke call to mark the try range. This | |||
| 6360 | // can be used to detect deletion of the invoke via the MachineModuleInfo. | |||
| 6361 | MCSymbol *EndLabel = MMI.getContext().createTempSymbol(); | |||
| 6362 | DAG.setRoot(DAG.getEHLabel(getCurSDLoc(), getRoot(), EndLabel)); | |||
| 6363 | ||||
| 6364 | // Inform MachineModuleInfo of range. | |||
| 6365 | auto Pers = classifyEHPersonality(FuncInfo.Fn->getPersonalityFn()); | |||
| 6366 | // There is a platform (e.g. wasm) that uses funclet style IR but does not | |||
| 6367 | // actually use outlined funclets and their LSDA info style. | |||
| 6368 | if (MF.hasEHFunclets() && isFuncletEHPersonality(Pers)) { | |||
| 6369 | assert(CLI.CS)(static_cast <bool> (CLI.CS) ? void (0) : __assert_fail ("CLI.CS", "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 6369, __extension__ __PRETTY_FUNCTION__)); | |||
| 6370 | WinEHFuncInfo *EHInfo = DAG.getMachineFunction().getWinEHFuncInfo(); | |||
| 6371 | EHInfo->addIPToStateRange(cast<InvokeInst>(CLI.CS.getInstruction()), | |||
| 6372 | BeginLabel, EndLabel); | |||
| 6373 | } else { | |||
| 6374 | MF.addInvoke(FuncInfo.MBBMap[EHPadBB], BeginLabel, EndLabel); | |||
| 6375 | } | |||
| 6376 | } | |||
| 6377 | ||||
| 6378 | return Result; | |||
| 6379 | } | |||
| 6380 | ||||
| 6381 | void SelectionDAGBuilder::LowerCallTo(ImmutableCallSite CS, SDValue Callee, | |||
| 6382 | bool isTailCall, | |||
| 6383 | const BasicBlock *EHPadBB) { | |||
| 6384 | auto &DL = DAG.getDataLayout(); | |||
| 6385 | FunctionType *FTy = CS.getFunctionType(); | |||
| 6386 | Type *RetTy = CS.getType(); | |||
| 6387 | ||||
| 6388 | TargetLowering::ArgListTy Args; | |||
| 6389 | Args.reserve(CS.arg_size()); | |||
| 6390 | ||||
| 6391 | const Value *SwiftErrorVal = nullptr; | |||
| 6392 | const TargetLowering &TLI = DAG.getTargetLoweringInfo(); | |||
| 6393 | ||||
| 6394 | // We can't tail call inside a function with a swifterror argument. Lowering | |||
| 6395 | // does not support this yet. It would have to move into the swifterror | |||
| 6396 | // register before the call. | |||
| 6397 | auto *Caller = CS.getInstruction()->getParent()->getParent(); | |||
| 6398 | if (TLI.supportSwiftError() && | |||
| 6399 | Caller->getAttributes().hasAttrSomewhere(Attribute::SwiftError)) | |||
| 6400 | isTailCall = false; | |||
| 6401 | ||||
| 6402 | for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end(); | |||
| 6403 | i != e; ++i) { | |||
| 6404 | TargetLowering::ArgListEntry Entry; | |||
| 6405 | const Value *V = *i; | |||
| 6406 | ||||
| 6407 | // Skip empty types | |||
| 6408 | if (V->getType()->isEmptyTy()) | |||
| 6409 | continue; | |||
| 6410 | ||||
| 6411 | SDValue ArgNode = getValue(V); | |||
| 6412 | Entry.Node = ArgNode; Entry.Ty = V->getType(); | |||
| 6413 | ||||
| 6414 | Entry.setAttributes(&CS, i - CS.arg_begin()); | |||
| 6415 | ||||
| 6416 | // Use swifterror virtual register as input to the call. | |||
| 6417 | if (Entry.IsSwiftError && TLI.supportSwiftError()) { | |||
| 6418 | SwiftErrorVal = V; | |||
| 6419 | // We find the virtual register for the actual swifterror argument. | |||
| 6420 | // Instead of using the Value, we use the virtual register instead. | |||
| 6421 | Entry.Node = DAG.getRegister(FuncInfo | |||
| 6422 | .getOrCreateSwiftErrorVRegUseAt( | |||
| 6423 | CS.getInstruction(), FuncInfo.MBB, V) | |||
| 6424 | .first, | |||
| 6425 | EVT(TLI.getPointerTy(DL))); | |||
| 6426 | } | |||
| 6427 | ||||
| 6428 | Args.push_back(Entry); | |||
| 6429 | ||||
| 6430 | // If we have an explicit sret argument that is an Instruction, (i.e., it | |||
| 6431 | // might point to function-local memory), we can't meaningfully tail-call. | |||
| 6432 | if (Entry.IsSRet && isa<Instruction>(V)) | |||
| 6433 | isTailCall = false; | |||
| 6434 | } | |||
| 6435 | ||||
| 6436 | // Check if target-independent constraints permit a tail call here. | |||
| 6437 | // Target-dependent constraints are checked within TLI->LowerCallTo. | |||
| 6438 | if (isTailCall && !isInTailCallPosition(CS, DAG.getTarget())) | |||
| 6439 | isTailCall = false; | |||
| 6440 | ||||
| 6441 | // Disable tail calls if there is an swifterror argument. Targets have not | |||
| 6442 | // been updated to support tail calls. | |||
| 6443 | if (TLI.supportSwiftError() && SwiftErrorVal) | |||
| 6444 | isTailCall = false; | |||
| 6445 | ||||
| 6446 | TargetLowering::CallLoweringInfo CLI(DAG); | |||
| 6447 | CLI.setDebugLoc(getCurSDLoc()) | |||
| 6448 | .setChain(getRoot()) | |||
| 6449 | .setCallee(RetTy, FTy, Callee, std::move(Args), CS) | |||
| 6450 | .setTailCall(isTailCall) | |||
| 6451 | .setConvergent(CS.isConvergent()); | |||
| 6452 | std::pair<SDValue, SDValue> Result = lowerInvokable(CLI, EHPadBB); | |||
| 6453 | ||||
| 6454 | if (Result.first.getNode()) { | |||
| 6455 | const Instruction *Inst = CS.getInstruction(); | |||
| 6456 | Result.first = lowerRangeToAssertZExt(DAG, *Inst, Result.first); | |||
| 6457 | setValue(Inst, Result.first); | |||
| 6458 | } | |||
| 6459 | ||||
| 6460 | // The last element of CLI.InVals has the SDValue for swifterror return. | |||
| 6461 | // Here we copy it to a virtual register and update SwiftErrorMap for | |||
| 6462 | // book-keeping. | |||
| 6463 | if (SwiftErrorVal && TLI.supportSwiftError()) { | |||
| 6464 | // Get the last element of InVals. | |||
| 6465 | SDValue Src = CLI.InVals.back(); | |||
| 6466 | unsigned VReg; bool CreatedVReg; | |||
| 6467 | std::tie(VReg, CreatedVReg) = | |||
| 6468 | FuncInfo.getOrCreateSwiftErrorVRegDefAt(CS.getInstruction()); | |||
| 6469 | SDValue CopyNode = CLI.DAG.getCopyToReg(Result.second, CLI.DL, VReg, Src); | |||
| 6470 | // We update the virtual register for the actual swifterror argument. | |||
| 6471 | if (CreatedVReg) | |||
| 6472 | FuncInfo.setCurrentSwiftErrorVReg(FuncInfo.MBB, SwiftErrorVal, VReg); | |||
| 6473 | DAG.setRoot(CopyNode); | |||
| 6474 | } | |||
| 6475 | } | |||
| 6476 | ||||
| 6477 | static SDValue getMemCmpLoad(const Value *PtrVal, MVT LoadVT, | |||
| 6478 | SelectionDAGBuilder &Builder) { | |||
| 6479 | // Check to see if this load can be trivially constant folded, e.g. if the | |||
| 6480 | // input is from a string literal. | |||
| 6481 | if (const Constant *LoadInput = dyn_cast<Constant>(PtrVal)) { | |||
| 6482 | // Cast pointer to the type we really want to load. | |||
| 6483 | Type *LoadTy = | |||
| 6484 | Type::getIntNTy(PtrVal->getContext(), LoadVT.getScalarSizeInBits()); | |||
| 6485 | if (LoadVT.isVector()) | |||
| 6486 | LoadTy = VectorType::get(LoadTy, LoadVT.getVectorNumElements()); | |||
| 6487 | ||||
| 6488 | LoadInput = ConstantExpr::getBitCast(const_cast<Constant *>(LoadInput), | |||
| 6489 | PointerType::getUnqual(LoadTy)); | |||
| 6490 | ||||
| 6491 | if (const Constant *LoadCst = ConstantFoldLoadFromConstPtr( | |||
| 6492 | const_cast<Constant *>(LoadInput), LoadTy, *Builder.DL)) | |||
| 6493 | return Builder.getValue(LoadCst); | |||
| 6494 | } | |||
| 6495 | ||||
| 6496 | // Otherwise, we have to emit the load. If the pointer is to unfoldable but | |||
| 6497 | // still constant memory, the input chain can be the entry node. | |||
| 6498 | SDValue Root; | |||
| 6499 | bool ConstantMemory = false; | |||
| 6500 | ||||
| 6501 | // Do not serialize (non-volatile) loads of constant memory with anything. | |||
| 6502 | if (Builder.AA && Builder.AA->pointsToConstantMemory(PtrVal)) { | |||
| 6503 | Root = Builder.DAG.getEntryNode(); | |||
| 6504 | ConstantMemory = true; | |||
| 6505 | } else { | |||
| 6506 | // Do not serialize non-volatile loads against each other. | |||
| 6507 | Root = Builder.DAG.getRoot(); | |||
| 6508 | } | |||
| 6509 | ||||
| 6510 | SDValue Ptr = Builder.getValue(PtrVal); | |||
| 6511 | SDValue LoadVal = Builder.DAG.getLoad(LoadVT, Builder.getCurSDLoc(), Root, | |||
| 6512 | Ptr, MachinePointerInfo(PtrVal), | |||
| 6513 | /* Alignment = */ 1); | |||
| 6514 | ||||
| 6515 | if (!ConstantMemory) | |||
| 6516 | Builder.PendingLoads.push_back(LoadVal.getValue(1)); | |||
| 6517 | return LoadVal; | |||
| 6518 | } | |||
| 6519 | ||||
| 6520 | /// Record the value for an instruction that produces an integer result, | |||
| 6521 | /// converting the type where necessary. | |||
| 6522 | void SelectionDAGBuilder::processIntegerCallValue(const Instruction &I, | |||
| 6523 | SDValue Value, | |||
| 6524 | bool IsSigned) { | |||
| 6525 | EVT VT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(), | |||
| 6526 | I.getType(), true); | |||
| 6527 | if (IsSigned) | |||
| 6528 | Value = DAG.getSExtOrTrunc(Value, getCurSDLoc(), VT); | |||
| 6529 | else | |||
| 6530 | Value = DAG.getZExtOrTrunc(Value, getCurSDLoc(), VT); | |||
| 6531 | setValue(&I, Value); | |||
| 6532 | } | |||
| 6533 | ||||
| 6534 | /// See if we can lower a memcmp call into an optimized form. If so, return | |||
| 6535 | /// true and lower it. Otherwise return false, and it will be lowered like a | |||
| 6536 | /// normal call. | |||
| 6537 | /// The caller already checked that \p I calls the appropriate LibFunc with a | |||
| 6538 | /// correct prototype. | |||
| 6539 | bool SelectionDAGBuilder::visitMemCmpCall(const CallInst &I) { | |||
| 6540 | const Value *LHS = I.getArgOperand(0), *RHS = I.getArgOperand(1); | |||
| 6541 | const Value *Size = I.getArgOperand(2); | |||
| 6542 | const ConstantInt *CSize = dyn_cast<ConstantInt>(Size); | |||
| 6543 | if (CSize && CSize->getZExtValue() == 0) { | |||
| 6544 | EVT CallVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(), | |||
| 6545 | I.getType(), true); | |||
| 6546 | setValue(&I, DAG.getConstant(0, getCurSDLoc(), CallVT)); | |||
| 6547 | return true; | |||
| 6548 | } | |||
| 6549 | ||||
| 6550 | const SelectionDAGTargetInfo &TSI = DAG.getSelectionDAGInfo(); | |||
| 6551 | std::pair<SDValue, SDValue> Res = TSI.EmitTargetCodeForMemcmp( | |||
| 6552 | DAG, getCurSDLoc(), DAG.getRoot(), getValue(LHS), getValue(RHS), | |||
| 6553 | getValue(Size), MachinePointerInfo(LHS), MachinePointerInfo(RHS)); | |||
| 6554 | if (Res.first.getNode()) { | |||
| 6555 | processIntegerCallValue(I, Res.first, true); | |||
| 6556 | PendingLoads.push_back(Res.second); | |||
| 6557 | return true; | |||
| 6558 | } | |||
| 6559 | ||||
| 6560 | // memcmp(S1,S2,2) != 0 -> (*(short*)LHS != *(short*)RHS) != 0 | |||
| 6561 | // memcmp(S1,S2,4) != 0 -> (*(int*)LHS != *(int*)RHS) != 0 | |||
| 6562 | if (!CSize || !isOnlyUsedInZeroEqualityComparison(&I)) | |||
| 6563 | return false; | |||
| 6564 | ||||
| 6565 | // If the target has a fast compare for the given size, it will return a | |||
| 6566 | // preferred load type for that size. Require that the load VT is legal and | |||
| 6567 | // that the target supports unaligned loads of that type. Otherwise, return | |||
| 6568 | // INVALID. | |||
| 6569 | auto hasFastLoadsAndCompare = [&](unsigned NumBits) { | |||
| 6570 | const TargetLowering &TLI = DAG.getTargetLoweringInfo(); | |||
| 6571 | MVT LVT = TLI.hasFastEqualityCompare(NumBits); | |||
| 6572 | if (LVT != MVT::INVALID_SIMPLE_VALUE_TYPE) { | |||
| 6573 | // TODO: Handle 5 byte compare as 4-byte + 1 byte. | |||
| 6574 | // TODO: Handle 8 byte compare on x86-32 as two 32-bit loads. | |||
| 6575 | // TODO: Check alignment of src and dest ptrs. | |||
| 6576 | unsigned DstAS = LHS->getType()->getPointerAddressSpace(); | |||
| 6577 | unsigned SrcAS = RHS->getType()->getPointerAddressSpace(); | |||
| 6578 | if (!TLI.isTypeLegal(LVT) || | |||
| 6579 | !TLI.allowsMisalignedMemoryAccesses(LVT, SrcAS) || | |||
| 6580 | !TLI.allowsMisalignedMemoryAccesses(LVT, DstAS)) | |||
| 6581 | LVT = MVT::INVALID_SIMPLE_VALUE_TYPE; | |||
| 6582 | } | |||
| 6583 | ||||
| 6584 | return LVT; | |||
| 6585 | }; | |||
| 6586 | ||||
| 6587 | // This turns into unaligned loads. We only do this if the target natively | |||
| 6588 | // supports the MVT we'll be loading or if it is small enough (<= 4) that | |||
| 6589 | // we'll only produce a small number of byte loads. | |||
| 6590 | MVT LoadVT; | |||
| 6591 | unsigned NumBitsToCompare = CSize->getZExtValue() * 8; | |||
| 6592 | switch (NumBitsToCompare) { | |||
| 6593 | default: | |||
| 6594 | return false; | |||
| 6595 | case 16: | |||
| 6596 | LoadVT = MVT::i16; | |||
| 6597 | break; | |||
| 6598 | case 32: | |||
| 6599 | LoadVT = MVT::i32; | |||
| 6600 | break; | |||
| 6601 | case 64: | |||
| 6602 | case 128: | |||
| 6603 | case 256: | |||
| 6604 | LoadVT = hasFastLoadsAndCompare(NumBitsToCompare); | |||
| 6605 | break; | |||
| 6606 | } | |||
| 6607 | ||||
| 6608 | if (LoadVT == MVT::INVALID_SIMPLE_VALUE_TYPE) | |||
| 6609 | return false; | |||
| 6610 | ||||
| 6611 | SDValue LoadL = getMemCmpLoad(LHS, LoadVT, *this); | |||
| 6612 | SDValue LoadR = getMemCmpLoad(RHS, LoadVT, *this); | |||
| 6613 | ||||
| 6614 | // Bitcast to a wide integer type if the loads are vectors. | |||
| 6615 | if (LoadVT.isVector()) { | |||
| 6616 | EVT CmpVT = EVT::getIntegerVT(LHS->getContext(), LoadVT.getSizeInBits()); | |||
| 6617 | LoadL = DAG.getBitcast(CmpVT, LoadL); | |||
| 6618 | LoadR = DAG.getBitcast(CmpVT, LoadR); | |||
| 6619 | } | |||
| 6620 | ||||
| 6621 | SDValue Cmp = DAG.getSetCC(getCurSDLoc(), MVT::i1, LoadL, LoadR, ISD::SETNE); | |||
| 6622 | processIntegerCallValue(I, Cmp, false); | |||
| 6623 | return true; | |||
| 6624 | } | |||
| 6625 | ||||
| 6626 | /// See if we can lower a memchr call into an optimized form. If so, return | |||
| 6627 | /// true and lower it. Otherwise return false, and it will be lowered like a | |||
| 6628 | /// normal call. | |||
| 6629 | /// The caller already checked that \p I calls the appropriate LibFunc with a | |||
| 6630 | /// correct prototype. | |||
| 6631 | bool SelectionDAGBuilder::visitMemChrCall(const CallInst &I) { | |||
| 6632 | const Value *Src = I.getArgOperand(0); | |||
| 6633 | const Value *Char = I.getArgOperand(1); | |||
| 6634 | const Value *Length = I.getArgOperand(2); | |||
| 6635 | ||||
| 6636 | const SelectionDAGTargetInfo &TSI = DAG.getSelectionDAGInfo(); | |||
| 6637 | std::pair<SDValue, SDValue> Res = | |||
| 6638 | TSI.EmitTargetCodeForMemchr(DAG, getCurSDLoc(), DAG.getRoot(), | |||
| 6639 | getValue(Src), getValue(Char), getValue(Length), | |||
| 6640 | MachinePointerInfo(Src)); | |||
| 6641 | if (Res.first.getNode()) { | |||
| 6642 | setValue(&I, Res.first); | |||
| 6643 | PendingLoads.push_back(Res.second); | |||
| 6644 | return true; | |||
| 6645 | } | |||
| 6646 | ||||
| 6647 | return false; | |||
| 6648 | } | |||
| 6649 | ||||
| 6650 | /// See if we can lower a mempcpy call into an optimized form. If so, return | |||
| 6651 | /// true and lower it. Otherwise return false, and it will be lowered like a | |||
| 6652 | /// normal call. | |||
| 6653 | /// The caller already checked that \p I calls the appropriate LibFunc with a | |||
| 6654 | /// correct prototype. | |||
| 6655 | bool SelectionDAGBuilder::visitMemPCpyCall(const CallInst &I) { | |||
| 6656 | SDValue Dst = getValue(I.getArgOperand(0)); | |||
| 6657 | SDValue Src = getValue(I.getArgOperand(1)); | |||
| 6658 | SDValue Size = getValue(I.getArgOperand(2)); | |||
| 6659 | ||||
| 6660 | unsigned DstAlign = DAG.InferPtrAlignment(Dst); | |||
| 6661 | unsigned SrcAlign = DAG.InferPtrAlignment(Src); | |||
| 6662 | unsigned Align = std::min(DstAlign, SrcAlign); | |||
| 6663 | if (Align == 0) // Alignment of one or both could not be inferred. | |||
| 6664 | Align = 1; // 0 and 1 both specify no alignment, but 0 is reserved. | |||
| 6665 | ||||
| 6666 | bool isVol = false; | |||
| 6667 | SDLoc sdl = getCurSDLoc(); | |||
| 6668 | ||||
| 6669 | // In the mempcpy context we need to pass in a false value for isTailCall | |||
| 6670 | // because the return pointer needs to be adjusted by the size of | |||
| 6671 | // the copied memory. | |||
| 6672 | SDValue MC = DAG.getMemcpy(getRoot(), sdl, Dst, Src, Size, Align, isVol, | |||
| 6673 | false, /*isTailCall=*/false, | |||
| 6674 | MachinePointerInfo(I.getArgOperand(0)), | |||
| 6675 | MachinePointerInfo(I.getArgOperand(1))); | |||
| 6676 | assert(MC.getNode() != nullptr &&(static_cast <bool> (MC.getNode() != nullptr && "** memcpy should not be lowered as TailCall in mempcpy context **" ) ? void (0) : __assert_fail ("MC.getNode() != nullptr && \"** memcpy should not be lowered as TailCall in mempcpy context **\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 6677, __extension__ __PRETTY_FUNCTION__)) | |||
| 6677 | "** memcpy should not be lowered as TailCall in mempcpy context **")(static_cast <bool> (MC.getNode() != nullptr && "** memcpy should not be lowered as TailCall in mempcpy context **" ) ? void (0) : __assert_fail ("MC.getNode() != nullptr && \"** memcpy should not be lowered as TailCall in mempcpy context **\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 6677, __extension__ __PRETTY_FUNCTION__)); | |||
| 6678 | DAG.setRoot(MC); | |||
| 6679 | ||||
| 6680 | // Check if Size needs to be truncated or extended. | |||
| 6681 | Size = DAG.getSExtOrTrunc(Size, sdl, Dst.getValueType()); | |||
| 6682 | ||||
| 6683 | // Adjust return pointer to point just past the last dst byte. | |||
| 6684 | SDValue DstPlusSize = DAG.getNode(ISD::ADD, sdl, Dst.getValueType(), | |||
| 6685 | Dst, Size); | |||
| 6686 | setValue(&I, DstPlusSize); | |||
| 6687 | return true; | |||
| 6688 | } | |||
| 6689 | ||||
| 6690 | /// See if we can lower a strcpy call into an optimized form. If so, return | |||
| 6691 | /// true and lower it, otherwise return false and it will be lowered like a | |||
| 6692 | /// normal call. | |||
| 6693 | /// The caller already checked that \p I calls the appropriate LibFunc with a | |||
| 6694 | /// correct prototype. | |||
| 6695 | bool SelectionDAGBuilder::visitStrCpyCall(const CallInst &I, bool isStpcpy) { | |||
| 6696 | const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1); | |||
| 6697 | ||||
| 6698 | const SelectionDAGTargetInfo &TSI = DAG.getSelectionDAGInfo(); | |||
| 6699 | std::pair<SDValue, SDValue> Res = | |||
| 6700 | TSI.EmitTargetCodeForStrcpy(DAG, getCurSDLoc(), getRoot(), | |||
| 6701 | getValue(Arg0), getValue(Arg1), | |||
| 6702 | MachinePointerInfo(Arg0), | |||
| 6703 | MachinePointerInfo(Arg1), isStpcpy); | |||
| 6704 | if (Res.first.getNode()) { | |||
| 6705 | setValue(&I, Res.first); | |||
| 6706 | DAG.setRoot(Res.second); | |||
| 6707 | return true; | |||
| 6708 | } | |||
| 6709 | ||||
| 6710 | return false; | |||
| 6711 | } | |||
| 6712 | ||||
| 6713 | /// See if we can lower a strcmp call into an optimized form. If so, return | |||
| 6714 | /// true and lower it, otherwise return false and it will be lowered like a | |||
| 6715 | /// normal call. | |||
| 6716 | /// The caller already checked that \p I calls the appropriate LibFunc with a | |||
| 6717 | /// correct prototype. | |||
| 6718 | bool SelectionDAGBuilder::visitStrCmpCall(const CallInst &I) { | |||
| 6719 | const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1); | |||
| 6720 | ||||
| 6721 | const SelectionDAGTargetInfo &TSI = DAG.getSelectionDAGInfo(); | |||
| 6722 | std::pair<SDValue, SDValue> Res = | |||
| 6723 | TSI.EmitTargetCodeForStrcmp(DAG, getCurSDLoc(), DAG.getRoot(), | |||
| 6724 | getValue(Arg0), getValue(Arg1), | |||
| 6725 | MachinePointerInfo(Arg0), | |||
| 6726 | MachinePointerInfo(Arg1)); | |||
| 6727 | if (Res.first.getNode()) { | |||
| 6728 | processIntegerCallValue(I, Res.first, true); | |||
| 6729 | PendingLoads.push_back(Res.second); | |||
| 6730 | return true; | |||
| 6731 | } | |||
| 6732 | ||||
| 6733 | return false; | |||
| 6734 | } | |||
| 6735 | ||||
| 6736 | /// See if we can lower a strlen call into an optimized form. If so, return | |||
| 6737 | /// true and lower it, otherwise return false and it will be lowered like a | |||
| 6738 | /// normal call. | |||
| 6739 | /// The caller already checked that \p I calls the appropriate LibFunc with a | |||
| 6740 | /// correct prototype. | |||
| 6741 | bool SelectionDAGBuilder::visitStrLenCall(const CallInst &I) { | |||
| 6742 | const Value *Arg0 = I.getArgOperand(0); | |||
| 6743 | ||||
| 6744 | const SelectionDAGTargetInfo &TSI = DAG.getSelectionDAGInfo(); | |||
| 6745 | std::pair<SDValue, SDValue> Res = | |||
| 6746 | TSI.EmitTargetCodeForStrlen(DAG, getCurSDLoc(), DAG.getRoot(), | |||
| 6747 | getValue(Arg0), MachinePointerInfo(Arg0)); | |||
| 6748 | if (Res.first.getNode()) { | |||
| 6749 | processIntegerCallValue(I, Res.first, false); | |||
| 6750 | PendingLoads.push_back(Res.second); | |||
| 6751 | return true; | |||
| 6752 | } | |||
| 6753 | ||||
| 6754 | return false; | |||
| 6755 | } | |||
| 6756 | ||||
| 6757 | /// See if we can lower a strnlen call into an optimized form. If so, return | |||
| 6758 | /// true and lower it, otherwise return false and it will be lowered like a | |||
| 6759 | /// normal call. | |||
| 6760 | /// The caller already checked that \p I calls the appropriate LibFunc with a | |||
| 6761 | /// correct prototype. | |||
| 6762 | bool SelectionDAGBuilder::visitStrNLenCall(const CallInst &I) { | |||
| 6763 | const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1); | |||
| 6764 | ||||
| 6765 | const SelectionDAGTargetInfo &TSI = DAG.getSelectionDAGInfo(); | |||
| 6766 | std::pair<SDValue, SDValue> Res = | |||
| 6767 | TSI.EmitTargetCodeForStrnlen(DAG, getCurSDLoc(), DAG.getRoot(), | |||
| 6768 | getValue(Arg0), getValue(Arg1), | |||
| 6769 | MachinePointerInfo(Arg0)); | |||
| 6770 | if (Res.first.getNode()) { | |||
| 6771 | processIntegerCallValue(I, Res.first, false); | |||
| 6772 | PendingLoads.push_back(Res.second); | |||
| 6773 | return true; | |||
| 6774 | } | |||
| 6775 | ||||
| 6776 | return false; | |||
| 6777 | } | |||
| 6778 | ||||
| 6779 | /// See if we can lower a unary floating-point operation into an SDNode with | |||
| 6780 | /// the specified Opcode. If so, return true and lower it, otherwise return | |||
| 6781 | /// false and it will be lowered like a normal call. | |||
| 6782 | /// The caller already checked that \p I calls the appropriate LibFunc with a | |||
| 6783 | /// correct prototype. | |||
| 6784 | bool SelectionDAGBuilder::visitUnaryFloatCall(const CallInst &I, | |||
| 6785 | unsigned Opcode) { | |||
| 6786 | // We already checked this call's prototype; verify it doesn't modify errno. | |||
| 6787 | if (!I.onlyReadsMemory()) | |||
| 6788 | return false; | |||
| 6789 | ||||
| 6790 | SDValue Tmp = getValue(I.getArgOperand(0)); | |||
| 6791 | setValue(&I, DAG.getNode(Opcode, getCurSDLoc(), Tmp.getValueType(), Tmp)); | |||
| 6792 | return true; | |||
| 6793 | } | |||
| 6794 | ||||
| 6795 | /// See if we can lower a binary floating-point operation into an SDNode with | |||
| 6796 | /// the specified Opcode. If so, return true and lower it. Otherwise return | |||
| 6797 | /// false, and it will be lowered like a normal call. | |||
| 6798 | /// The caller already checked that \p I calls the appropriate LibFunc with a | |||
| 6799 | /// correct prototype. | |||
| 6800 | bool SelectionDAGBuilder::visitBinaryFloatCall(const CallInst &I, | |||
| 6801 | unsigned Opcode) { | |||
| 6802 | // We already checked this call's prototype; verify it doesn't modify errno. | |||
| 6803 | if (!I.onlyReadsMemory()) | |||
| 6804 | return false; | |||
| 6805 | ||||
| 6806 | SDValue Tmp0 = getValue(I.getArgOperand(0)); | |||
| 6807 | SDValue Tmp1 = getValue(I.getArgOperand(1)); | |||
| 6808 | EVT VT = Tmp0.getValueType(); | |||
| 6809 | setValue(&I, DAG.getNode(Opcode, getCurSDLoc(), VT, Tmp0, Tmp1)); | |||
| 6810 | return true; | |||
| 6811 | } | |||
| 6812 | ||||
| 6813 | void SelectionDAGBuilder::visitCall(const CallInst &I) { | |||
| 6814 | // Handle inline assembly differently. | |||
| 6815 | if (isa<InlineAsm>(I.getCalledValue())) { | |||
| 6816 | visitInlineAsm(&I); | |||
| 6817 | return; | |||
| 6818 | } | |||
| 6819 | ||||
| 6820 | MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); | |||
| 6821 | computeUsesVAFloatArgument(I, MMI); | |||
| 6822 | ||||
| 6823 | const char *RenameFn = nullptr; | |||
| 6824 | if (Function *F = I.getCalledFunction()) { | |||
| 6825 | if (F->isDeclaration()) { | |||
| 6826 | // Is this an LLVM intrinsic or a target-specific intrinsic? | |||
| 6827 | unsigned IID = F->getIntrinsicID(); | |||
| 6828 | if (!IID) | |||
| 6829 | if (const TargetIntrinsicInfo *II = TM.getIntrinsicInfo()) | |||
| 6830 | IID = II->getIntrinsicID(F); | |||
| 6831 | ||||
| 6832 | if (IID) { | |||
| 6833 | RenameFn = visitIntrinsicCall(I, IID); | |||
| 6834 | if (!RenameFn) | |||
| 6835 | return; | |||
| 6836 | } | |||
| 6837 | } | |||
| 6838 | ||||
| 6839 | // Check for well-known libc/libm calls. If the function is internal, it | |||
| 6840 | // can't be a library call. Don't do the check if marked as nobuiltin for | |||
| 6841 | // some reason or the call site requires strict floating point semantics. | |||
| 6842 | LibFunc Func; | |||
| 6843 | if (!I.isNoBuiltin() && !I.isStrictFP() && !F->hasLocalLinkage() && | |||
| 6844 | F->hasName() && LibInfo->getLibFunc(*F, Func) && | |||
| 6845 | LibInfo->hasOptimizedCodeGen(Func)) { | |||
| 6846 | switch (Func) { | |||
| 6847 | default: break; | |||
| 6848 | case LibFunc_copysign: | |||
| 6849 | case LibFunc_copysignf: | |||
| 6850 | case LibFunc_copysignl: | |||
| 6851 | // We already checked this call's prototype; verify it doesn't modify | |||
| 6852 | // errno. | |||
| 6853 | if (I.onlyReadsMemory()) { | |||
| 6854 | SDValue LHS = getValue(I.getArgOperand(0)); | |||
| 6855 | SDValue RHS = getValue(I.getArgOperand(1)); | |||
| 6856 | setValue(&I, DAG.getNode(ISD::FCOPYSIGN, getCurSDLoc(), | |||
| 6857 | LHS.getValueType(), LHS, RHS)); | |||
| 6858 | return; | |||
| 6859 | } | |||
| 6860 | break; | |||
| 6861 | case LibFunc_fabs: | |||
| 6862 | case LibFunc_fabsf: | |||
| 6863 | case LibFunc_fabsl: | |||
| 6864 | if (visitUnaryFloatCall(I, ISD::FABS)) | |||
| 6865 | return; | |||
| 6866 | break; | |||
| 6867 | case LibFunc_fmin: | |||
| 6868 | case LibFunc_fminf: | |||
| 6869 | case LibFunc_fminl: | |||
| 6870 | if (visitBinaryFloatCall(I, ISD::FMINNUM)) | |||
| 6871 | return; | |||
| 6872 | break; | |||
| 6873 | case LibFunc_fmax: | |||
| 6874 | case LibFunc_fmaxf: | |||
| 6875 | case LibFunc_fmaxl: | |||
| 6876 | if (visitBinaryFloatCall(I, ISD::FMAXNUM)) | |||
| 6877 | return; | |||
| 6878 | break; | |||
| 6879 | case LibFunc_sin: | |||
| 6880 | case LibFunc_sinf: | |||
| 6881 | case LibFunc_sinl: | |||
| 6882 | if (visitUnaryFloatCall(I, ISD::FSIN)) | |||
| 6883 | return; | |||
| 6884 | break; | |||
| 6885 | case LibFunc_cos: | |||
| 6886 | case LibFunc_cosf: | |||
| 6887 | case LibFunc_cosl: | |||
| 6888 | if (visitUnaryFloatCall(I, ISD::FCOS)) | |||
| 6889 | return; | |||
| 6890 | break; | |||
| 6891 | case LibFunc_sqrt: | |||
| 6892 | case LibFunc_sqrtf: | |||
| 6893 | case LibFunc_sqrtl: | |||
| 6894 | case LibFunc_sqrt_finite: | |||
| 6895 | case LibFunc_sqrtf_finite: | |||
| 6896 | case LibFunc_sqrtl_finite: | |||
| 6897 | if (visitUnaryFloatCall(I, ISD::FSQRT)) | |||
| 6898 | return; | |||
| 6899 | break; | |||
| 6900 | case LibFunc_floor: | |||
| 6901 | case LibFunc_floorf: | |||
| 6902 | case LibFunc_floorl: | |||
| 6903 | if (visitUnaryFloatCall(I, ISD::FFLOOR)) | |||
| 6904 | return; | |||
| 6905 | break; | |||
| 6906 | case LibFunc_nearbyint: | |||
| 6907 | case LibFunc_nearbyintf: | |||
| 6908 | case LibFunc_nearbyintl: | |||
| 6909 | if (visitUnaryFloatCall(I, ISD::FNEARBYINT)) | |||
| 6910 | return; | |||
| 6911 | break; | |||
| 6912 | case LibFunc_ceil: | |||
| 6913 | case LibFunc_ceilf: | |||
| 6914 | case LibFunc_ceill: | |||
| 6915 | if (visitUnaryFloatCall(I, ISD::FCEIL)) | |||
| 6916 | return; | |||
| 6917 | break; | |||
| 6918 | case LibFunc_rint: | |||
| 6919 | case LibFunc_rintf: | |||
| 6920 | case LibFunc_rintl: | |||
| 6921 | if (visitUnaryFloatCall(I, ISD::FRINT)) | |||
| 6922 | return; | |||
| 6923 | break; | |||
| 6924 | case LibFunc_round: | |||
| 6925 | case LibFunc_roundf: | |||
| 6926 | case LibFunc_roundl: | |||
| 6927 | if (visitUnaryFloatCall(I, ISD::FROUND)) | |||
| 6928 | return; | |||
| 6929 | break; | |||
| 6930 | case LibFunc_trunc: | |||
| 6931 | case LibFunc_truncf: | |||
| 6932 | case LibFunc_truncl: | |||
| 6933 | if (visitUnaryFloatCall(I, ISD::FTRUNC)) | |||
| 6934 | return; | |||
| 6935 | break; | |||
| 6936 | case LibFunc_log2: | |||
| 6937 | case LibFunc_log2f: | |||
| 6938 | case LibFunc_log2l: | |||
| 6939 | if (visitUnaryFloatCall(I, ISD::FLOG2)) | |||
| 6940 | return; | |||
| 6941 | break; | |||
| 6942 | case LibFunc_exp2: | |||
| 6943 | case LibFunc_exp2f: | |||
| 6944 | case LibFunc_exp2l: | |||
| 6945 | if (visitUnaryFloatCall(I, ISD::FEXP2)) | |||
| 6946 | return; | |||
| 6947 | break; | |||
| 6948 | case LibFunc_memcmp: | |||
| 6949 | if (visitMemCmpCall(I)) | |||
| 6950 | return; | |||
| 6951 | break; | |||
| 6952 | case LibFunc_mempcpy: | |||
| 6953 | if (visitMemPCpyCall(I)) | |||
| 6954 | return; | |||
| 6955 | break; | |||
| 6956 | case LibFunc_memchr: | |||
| 6957 | if (visitMemChrCall(I)) | |||
| 6958 | return; | |||
| 6959 | break; | |||
| 6960 | case LibFunc_strcpy: | |||
| 6961 | if (visitStrCpyCall(I, false)) | |||
| 6962 | return; | |||
| 6963 | break; | |||
| 6964 | case LibFunc_stpcpy: | |||
| 6965 | if (visitStrCpyCall(I, true)) | |||
| 6966 | return; | |||
| 6967 | break; | |||
| 6968 | case LibFunc_strcmp: | |||
| 6969 | if (visitStrCmpCall(I)) | |||
| 6970 | return; | |||
| 6971 | break; | |||
| 6972 | case LibFunc_strlen: | |||
| 6973 | if (visitStrLenCall(I)) | |||
| 6974 | return; | |||
| 6975 | break; | |||
| 6976 | case LibFunc_strnlen: | |||
| 6977 | if (visitStrNLenCall(I)) | |||
| 6978 | return; | |||
| 6979 | break; | |||
| 6980 | } | |||
| 6981 | } | |||
| 6982 | } | |||
| 6983 | ||||
| 6984 | SDValue Callee; | |||
| 6985 | if (!RenameFn) | |||
| 6986 | Callee = getValue(I.getCalledValue()); | |||
| 6987 | else | |||
| 6988 | Callee = DAG.getExternalSymbol( | |||
| 6989 | RenameFn, | |||
| 6990 | DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout())); | |||
| 6991 | ||||
| 6992 | // Deopt bundles are lowered in LowerCallSiteWithDeoptBundle, and we don't | |||
| 6993 | // have to do anything here to lower funclet bundles. | |||
| 6994 | assert(!I.hasOperandBundlesOtherThan((static_cast <bool> (!I.hasOperandBundlesOtherThan( {LLVMContext ::OB_deopt, LLVMContext::OB_funclet}) && "Cannot lower calls with arbitrary operand bundles!" ) ? void (0) : __assert_fail ("!I.hasOperandBundlesOtherThan( {LLVMContext::OB_deopt, LLVMContext::OB_funclet}) && \"Cannot lower calls with arbitrary operand bundles!\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 6996, __extension__ __PRETTY_FUNCTION__)) | |||
| 6995 | {LLVMContext::OB_deopt, LLVMContext::OB_funclet}) &&(static_cast <bool> (!I.hasOperandBundlesOtherThan( {LLVMContext ::OB_deopt, LLVMContext::OB_funclet}) && "Cannot lower calls with arbitrary operand bundles!" ) ? void (0) : __assert_fail ("!I.hasOperandBundlesOtherThan( {LLVMContext::OB_deopt, LLVMContext::OB_funclet}) && \"Cannot lower calls with arbitrary operand bundles!\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 6996, __extension__ __PRETTY_FUNCTION__)) | |||
| 6996 | "Cannot lower calls with arbitrary operand bundles!")(static_cast <bool> (!I.hasOperandBundlesOtherThan( {LLVMContext ::OB_deopt, LLVMContext::OB_funclet}) && "Cannot lower calls with arbitrary operand bundles!" ) ? void (0) : __assert_fail ("!I.hasOperandBundlesOtherThan( {LLVMContext::OB_deopt, LLVMContext::OB_funclet}) && \"Cannot lower calls with arbitrary operand bundles!\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 6996, __extension__ __PRETTY_FUNCTION__)); | |||
| 6997 | ||||
| 6998 | if (I.countOperandBundlesOfType(LLVMContext::OB_deopt)) | |||
| 6999 | LowerCallSiteWithDeoptBundle(&I, Callee, nullptr); | |||
| 7000 | else | |||
| 7001 | // Check if we can potentially perform a tail call. More detailed checking | |||
| 7002 | // is be done within LowerCallTo, after more information about the call is | |||
| 7003 | // known. | |||
| 7004 | LowerCallTo(&I, Callee, I.isTailCall()); | |||
| 7005 | } | |||
| 7006 | ||||
| 7007 | namespace { | |||
| 7008 | ||||
| 7009 | /// AsmOperandInfo - This contains information for each constraint that we are | |||
| 7010 | /// lowering. | |||
| 7011 | class SDISelAsmOperandInfo : public TargetLowering::AsmOperandInfo { | |||
| 7012 | public: | |||
| 7013 | /// CallOperand - If this is the result output operand or a clobber | |||
| 7014 | /// this is null, otherwise it is the incoming operand to the CallInst. | |||
| 7015 | /// This gets modified as the asm is processed. | |||
| 7016 | SDValue CallOperand; | |||
| 7017 | ||||
| 7018 | /// AssignedRegs - If this is a register or register class operand, this | |||
| 7019 | /// contains the set of register corresponding to the operand. | |||
| 7020 | RegsForValue AssignedRegs; | |||
| 7021 | ||||
| 7022 | explicit SDISelAsmOperandInfo(const TargetLowering::AsmOperandInfo &info) | |||
| 7023 | : TargetLowering::AsmOperandInfo(info), CallOperand(nullptr, 0) { | |||
| 7024 | } | |||
| 7025 | ||||
| 7026 | /// Whether or not this operand accesses memory | |||
| 7027 | bool hasMemory(const TargetLowering &TLI) const { | |||
| 7028 | // Indirect operand accesses access memory. | |||
| 7029 | if (isIndirect) | |||
| 7030 | return true; | |||
| 7031 | ||||
| 7032 | for (const auto &Code : Codes) | |||
| 7033 | if (TLI.getConstraintType(Code) == TargetLowering::C_Memory) | |||
| 7034 | return true; | |||
| 7035 | ||||
| 7036 | return false; | |||
| 7037 | } | |||
| 7038 | ||||
| 7039 | /// getCallOperandValEVT - Return the EVT of the Value* that this operand | |||
| 7040 | /// corresponds to. If there is no Value* for this operand, it returns | |||
| 7041 | /// MVT::Other. | |||
| 7042 | EVT getCallOperandValEVT(LLVMContext &Context, const TargetLowering &TLI, | |||
| 7043 | const DataLayout &DL) const { | |||
| 7044 | if (!CallOperandVal) return MVT::Other; | |||
| 7045 | ||||
| 7046 | if (isa<BasicBlock>(CallOperandVal)) | |||
| 7047 | return TLI.getPointerTy(DL); | |||
| 7048 | ||||
| 7049 | llvm::Type *OpTy = CallOperandVal->getType(); | |||
| 7050 | ||||
| 7051 | // FIXME: code duplicated from TargetLowering::ParseConstraints(). | |||
| 7052 | // If this is an indirect operand, the operand is a pointer to the | |||
| 7053 | // accessed type. | |||
| 7054 | if (isIndirect) { | |||
| 7055 | PointerType *PtrTy = dyn_cast<PointerType>(OpTy); | |||
| 7056 | if (!PtrTy) | |||
| 7057 | report_fatal_error("Indirect operand for inline asm not a pointer!"); | |||
| 7058 | OpTy = PtrTy->getElementType(); | |||
| 7059 | } | |||
| 7060 | ||||
| 7061 | // Look for vector wrapped in a struct. e.g. { <16 x i8> }. | |||
| 7062 | if (StructType *STy = dyn_cast<StructType>(OpTy)) | |||
| 7063 | if (STy->getNumElements() == 1) | |||
| 7064 | OpTy = STy->getElementType(0); | |||
| 7065 | ||||
| 7066 | // If OpTy is not a single value, it may be a struct/union that we | |||
| 7067 | // can tile with integers. | |||
| 7068 | if (!OpTy->isSingleValueType() && OpTy->isSized()) { | |||
| 7069 | unsigned BitSize = DL.getTypeSizeInBits(OpTy); | |||
| 7070 | switch (BitSize) { | |||
| 7071 | default: break; | |||
| 7072 | case 1: | |||
| 7073 | case 8: | |||
| 7074 | case 16: | |||
| 7075 | case 32: | |||
| 7076 | case 64: | |||
| 7077 | case 128: | |||
| 7078 | OpTy = IntegerType::get(Context, BitSize); | |||
| 7079 | break; | |||
| 7080 | } | |||
| 7081 | } | |||
| 7082 | ||||
| 7083 | return TLI.getValueType(DL, OpTy, true); | |||
| 7084 | } | |||
| 7085 | }; | |||
| 7086 | ||||
| 7087 | using SDISelAsmOperandInfoVector = SmallVector<SDISelAsmOperandInfo, 16>; | |||
| 7088 | ||||
| 7089 | } // end anonymous namespace | |||
| 7090 | ||||
| 7091 | /// Make sure that the output operand \p OpInfo and its corresponding input | |||
| 7092 | /// operand \p MatchingOpInfo have compatible constraint types (otherwise error | |||
| 7093 | /// out). | |||
| 7094 | static void patchMatchingInput(const SDISelAsmOperandInfo &OpInfo, | |||
| 7095 | SDISelAsmOperandInfo &MatchingOpInfo, | |||
| 7096 | SelectionDAG &DAG) { | |||
| 7097 | if (OpInfo.ConstraintVT == MatchingOpInfo.ConstraintVT) | |||
| 7098 | return; | |||
| 7099 | ||||
| 7100 | const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo(); | |||
| 7101 | const auto &TLI = DAG.getTargetLoweringInfo(); | |||
| 7102 | ||||
| 7103 | std::pair<unsigned, const TargetRegisterClass *> MatchRC = | |||
| 7104 | TLI.getRegForInlineAsmConstraint(TRI, OpInfo.ConstraintCode, | |||
| 7105 | OpInfo.ConstraintVT); | |||
| 7106 | std::pair<unsigned, const TargetRegisterClass *> InputRC = | |||
| 7107 | TLI.getRegForInlineAsmConstraint(TRI, MatchingOpInfo.ConstraintCode, | |||
| 7108 | MatchingOpInfo.ConstraintVT); | |||
| 7109 | if ((OpInfo.ConstraintVT.isInteger() != | |||
| 7110 | MatchingOpInfo.ConstraintVT.isInteger()) || | |||
| 7111 | (MatchRC.second != InputRC.second)) { | |||
| 7112 | // FIXME: error out in a more elegant fashion | |||
| 7113 | report_fatal_error("Unsupported asm: input constraint" | |||
| 7114 | " with a matching output constraint of" | |||
| 7115 | " incompatible type!"); | |||
| 7116 | } | |||
| 7117 | MatchingOpInfo.ConstraintVT = OpInfo.ConstraintVT; | |||
| 7118 | } | |||
| 7119 | ||||
| 7120 | /// Get a direct memory input to behave well as an indirect operand. | |||
| 7121 | /// This may introduce stores, hence the need for a \p Chain. | |||
| 7122 | /// \return The (possibly updated) chain. | |||
| 7123 | static SDValue getAddressForMemoryInput(SDValue Chain, const SDLoc &Location, | |||
| 7124 | SDISelAsmOperandInfo &OpInfo, | |||
| 7125 | SelectionDAG &DAG) { | |||
| 7126 | const TargetLowering &TLI = DAG.getTargetLoweringInfo(); | |||
| 7127 | ||||
| 7128 | // If we don't have an indirect input, put it in the constpool if we can, | |||
| 7129 | // otherwise spill it to a stack slot. | |||
| 7130 | // TODO: This isn't quite right. We need to handle these according to | |||
| 7131 | // the addressing mode that the constraint wants. Also, this may take | |||
| 7132 | // an additional register for the computation and we don't want that | |||
| 7133 | // either. | |||
| 7134 | ||||
| 7135 | // If the operand is a float, integer, or vector constant, spill to a | |||
| 7136 | // constant pool entry to get its address. | |||
| 7137 | const Value *OpVal = OpInfo.CallOperandVal; | |||
| 7138 | if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) || | |||
| 7139 | isa<ConstantVector>(OpVal) || isa<ConstantDataVector>(OpVal)) { | |||
| 7140 | OpInfo.CallOperand = DAG.getConstantPool( | |||
| 7141 | cast<Constant>(OpVal), TLI.getPointerTy(DAG.getDataLayout())); | |||
| 7142 | return Chain; | |||
| 7143 | } | |||
| 7144 | ||||
| 7145 | // Otherwise, create a stack slot and emit a store to it before the asm. | |||
| 7146 | Type *Ty = OpVal->getType(); | |||
| 7147 | auto &DL = DAG.getDataLayout(); | |||
| 7148 | uint64_t TySize = DL.getTypeAllocSize(Ty); | |||
| 7149 | unsigned Align = DL.getPrefTypeAlignment(Ty); | |||
| 7150 | MachineFunction &MF = DAG.getMachineFunction(); | |||
| 7151 | int SSFI = MF.getFrameInfo().CreateStackObject(TySize, Align, false); | |||
| 7152 | SDValue StackSlot = DAG.getFrameIndex(SSFI, TLI.getFrameIndexTy(DL)); | |||
| 7153 | Chain = DAG.getStore(Chain, Location, OpInfo.CallOperand, StackSlot, | |||
| 7154 | MachinePointerInfo::getFixedStack(MF, SSFI)); | |||
| 7155 | OpInfo.CallOperand = StackSlot; | |||
| 7156 | ||||
| 7157 | return Chain; | |||
| 7158 | } | |||
| 7159 | ||||
| 7160 | /// GetRegistersForValue - Assign registers (virtual or physical) for the | |||
| 7161 | /// specified operand. We prefer to assign virtual registers, to allow the | |||
| 7162 | /// register allocator to handle the assignment process. However, if the asm | |||
| 7163 | /// uses features that we can't model on machineinstrs, we have SDISel do the | |||
| 7164 | /// allocation. This produces generally horrible, but correct, code. | |||
| 7165 | /// | |||
| 7166 | /// OpInfo describes the operand. | |||
| 7167 | static void GetRegistersForValue(SelectionDAG &DAG, const TargetLowering &TLI, | |||
| 7168 | const SDLoc &DL, | |||
| 7169 | SDISelAsmOperandInfo &OpInfo) { | |||
| 7170 | LLVMContext &Context = *DAG.getContext(); | |||
| 7171 | ||||
| 7172 | MachineFunction &MF = DAG.getMachineFunction(); | |||
| 7173 | SmallVector<unsigned, 4> Regs; | |||
| 7174 | const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo(); | |||
| 7175 | ||||
| 7176 | // If this is a constraint for a single physreg, or a constraint for a | |||
| 7177 | // register class, find it. | |||
| 7178 | std::pair<unsigned, const TargetRegisterClass *> PhysReg = | |||
| 7179 | TLI.getRegForInlineAsmConstraint(&TRI, OpInfo.ConstraintCode, | |||
| 7180 | OpInfo.ConstraintVT); | |||
| 7181 | ||||
| 7182 | unsigned NumRegs = 1; | |||
| 7183 | if (OpInfo.ConstraintVT != MVT::Other) { | |||
| 7184 | // If this is a FP input in an integer register (or visa versa) insert a bit | |||
| 7185 | // cast of the input value. More generally, handle any case where the input | |||
| 7186 | // value disagrees with the register class we plan to stick this in. | |||
| 7187 | if (OpInfo.Type == InlineAsm::isInput && PhysReg.second && | |||
| 7188 | !TRI.isTypeLegalForClass(*PhysReg.second, OpInfo.ConstraintVT)) { | |||
| 7189 | // Try to convert to the first EVT that the reg class contains. If the | |||
| 7190 | // types are identical size, use a bitcast to convert (e.g. two differing | |||
| 7191 | // vector types). | |||
| 7192 | MVT RegVT = *TRI.legalclasstypes_begin(*PhysReg.second); | |||
| 7193 | if (RegVT.getSizeInBits() == OpInfo.CallOperand.getValueSizeInBits()) { | |||
| 7194 | OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL, | |||
| 7195 | RegVT, OpInfo.CallOperand); | |||
| 7196 | OpInfo.ConstraintVT = RegVT; | |||
| 7197 | } else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) { | |||
| 7198 | // If the input is a FP value and we want it in FP registers, do a | |||
| 7199 | // bitcast to the corresponding integer type. This turns an f64 value | |||
| 7200 | // into i64, which can be passed with two i32 values on a 32-bit | |||
| 7201 | // machine. | |||
| 7202 | RegVT = MVT::getIntegerVT(OpInfo.ConstraintVT.getSizeInBits()); | |||
| 7203 | OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL, | |||
| 7204 | RegVT, OpInfo.CallOperand); | |||
| 7205 | OpInfo.ConstraintVT = RegVT; | |||
| 7206 | } | |||
| 7207 | } | |||
| 7208 | ||||
| 7209 | NumRegs = TLI.getNumRegisters(Context, OpInfo.ConstraintVT); | |||
| 7210 | } | |||
| 7211 | ||||
| 7212 | MVT RegVT; | |||
| 7213 | EVT ValueVT = OpInfo.ConstraintVT; | |||
| 7214 | ||||
| 7215 | // If this is a constraint for a specific physical register, like {r17}, | |||
| 7216 | // assign it now. | |||
| 7217 | if (unsigned AssignedReg = PhysReg.first) { | |||
| 7218 | const TargetRegisterClass *RC = PhysReg.second; | |||
| 7219 | if (OpInfo.ConstraintVT == MVT::Other) | |||
| 7220 | ValueVT = *TRI.legalclasstypes_begin(*RC); | |||
| 7221 | ||||
| 7222 | // Get the actual register value type. This is important, because the user | |||
| 7223 | // may have asked for (e.g.) the AX register in i32 type. We need to | |||
| 7224 | // remember that AX is actually i16 to get the right extension. | |||
| 7225 | RegVT = *TRI.legalclasstypes_begin(*RC); | |||
| ||||
| 7226 | ||||
| 7227 | // This is a explicit reference to a physical register. | |||
| 7228 | Regs.push_back(AssignedReg); | |||
| 7229 | ||||
| 7230 | // If this is an expanded reference, add the rest of the regs to Regs. | |||
| 7231 | if (NumRegs != 1) { | |||
| 7232 | TargetRegisterClass::iterator I = RC->begin(); | |||
| 7233 | for (; *I != AssignedReg; ++I) | |||
| 7234 | assert(I != RC->end() && "Didn't find reg!")(static_cast <bool> (I != RC->end() && "Didn't find reg!" ) ? void (0) : __assert_fail ("I != RC->end() && \"Didn't find reg!\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 7234, __extension__ __PRETTY_FUNCTION__)); | |||
| 7235 | ||||
| 7236 | // Already added the first reg. | |||
| 7237 | --NumRegs; ++I; | |||
| 7238 | for (; NumRegs; --NumRegs, ++I) { | |||
| 7239 | assert(I != RC->end() && "Ran out of registers to allocate!")(static_cast <bool> (I != RC->end() && "Ran out of registers to allocate!" ) ? void (0) : __assert_fail ("I != RC->end() && \"Ran out of registers to allocate!\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 7239, __extension__ __PRETTY_FUNCTION__)); | |||
| 7240 | Regs.push_back(*I); | |||
| 7241 | } | |||
| 7242 | } | |||
| 7243 | ||||
| 7244 | OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT); | |||
| 7245 | return; | |||
| 7246 | } | |||
| 7247 | ||||
| 7248 | // Otherwise, if this was a reference to an LLVM register class, create vregs | |||
| 7249 | // for this reference. | |||
| 7250 | if (const TargetRegisterClass *RC = PhysReg.second) { | |||
| 7251 | RegVT = *TRI.legalclasstypes_begin(*RC); | |||
| 7252 | if (OpInfo.ConstraintVT == MVT::Other) | |||
| 7253 | ValueVT = RegVT; | |||
| 7254 | ||||
| 7255 | // Create the appropriate number of virtual registers. | |||
| 7256 | MachineRegisterInfo &RegInfo = MF.getRegInfo(); | |||
| 7257 | for (; NumRegs; --NumRegs) | |||
| 7258 | Regs.push_back(RegInfo.createVirtualRegister(RC)); | |||
| 7259 | ||||
| 7260 | OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT); | |||
| 7261 | return; | |||
| 7262 | } | |||
| 7263 | ||||
| 7264 | // Otherwise, we couldn't allocate enough registers for this. | |||
| 7265 | } | |||
| 7266 | ||||
| 7267 | static unsigned | |||
| 7268 | findMatchingInlineAsmOperand(unsigned OperandNo, | |||
| 7269 | const std::vector<SDValue> &AsmNodeOperands) { | |||
| 7270 | // Scan until we find the definition we already emitted of this operand. | |||
| 7271 | unsigned CurOp = InlineAsm::Op_FirstOperand; | |||
| 7272 | for (; OperandNo; --OperandNo) { | |||
| 7273 | // Advance to the next operand. | |||
| 7274 | unsigned OpFlag = | |||
| 7275 | cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue(); | |||
| 7276 | assert((InlineAsm::isRegDefKind(OpFlag) ||(static_cast <bool> ((InlineAsm::isRegDefKind(OpFlag) || InlineAsm::isRegDefEarlyClobberKind(OpFlag) || InlineAsm::isMemKind (OpFlag)) && "Skipped past definitions?") ? void (0) : __assert_fail ("(InlineAsm::isRegDefKind(OpFlag) || InlineAsm::isRegDefEarlyClobberKind(OpFlag) || InlineAsm::isMemKind(OpFlag)) && \"Skipped past definitions?\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 7279, __extension__ __PRETTY_FUNCTION__)) | |||
| 7277 | InlineAsm::isRegDefEarlyClobberKind(OpFlag) ||(static_cast <bool> ((InlineAsm::isRegDefKind(OpFlag) || InlineAsm::isRegDefEarlyClobberKind(OpFlag) || InlineAsm::isMemKind (OpFlag)) && "Skipped past definitions?") ? void (0) : __assert_fail ("(InlineAsm::isRegDefKind(OpFlag) || InlineAsm::isRegDefEarlyClobberKind(OpFlag) || InlineAsm::isMemKind(OpFlag)) && \"Skipped past definitions?\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 7279, __extension__ __PRETTY_FUNCTION__)) | |||
| 7278 | InlineAsm::isMemKind(OpFlag)) &&(static_cast <bool> ((InlineAsm::isRegDefKind(OpFlag) || InlineAsm::isRegDefEarlyClobberKind(OpFlag) || InlineAsm::isMemKind (OpFlag)) && "Skipped past definitions?") ? void (0) : __assert_fail ("(InlineAsm::isRegDefKind(OpFlag) || InlineAsm::isRegDefEarlyClobberKind(OpFlag) || InlineAsm::isMemKind(OpFlag)) && \"Skipped past definitions?\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 7279, __extension__ __PRETTY_FUNCTION__)) | |||
| 7279 | "Skipped past definitions?")(static_cast <bool> ((InlineAsm::isRegDefKind(OpFlag) || InlineAsm::isRegDefEarlyClobberKind(OpFlag) || InlineAsm::isMemKind (OpFlag)) && "Skipped past definitions?") ? void (0) : __assert_fail ("(InlineAsm::isRegDefKind(OpFlag) || InlineAsm::isRegDefEarlyClobberKind(OpFlag) || InlineAsm::isMemKind(OpFlag)) && \"Skipped past definitions?\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 7279, __extension__ __PRETTY_FUNCTION__)); | |||
| 7280 | CurOp += InlineAsm::getNumOperandRegisters(OpFlag) + 1; | |||
| 7281 | } | |||
| 7282 | return CurOp; | |||
| 7283 | } | |||
| 7284 | ||||
| 7285 | /// Fill \p Regs with \p NumRegs new virtual registers of type \p RegVT | |||
| 7286 | /// \return true if it has succeeded, false otherwise | |||
| 7287 | static bool createVirtualRegs(SmallVector<unsigned, 4> &Regs, unsigned NumRegs, | |||
| 7288 | MVT RegVT, SelectionDAG &DAG) { | |||
| 7289 | const TargetLowering &TLI = DAG.getTargetLoweringInfo(); | |||
| 7290 | MachineRegisterInfo &RegInfo = DAG.getMachineFunction().getRegInfo(); | |||
| 7291 | for (unsigned i = 0, e = NumRegs; i != e; ++i) { | |||
| 7292 | if (const TargetRegisterClass *RC = TLI.getRegClassFor(RegVT)) | |||
| 7293 | Regs.push_back(RegInfo.createVirtualRegister(RC)); | |||
| 7294 | else | |||
| 7295 | return false; | |||
| 7296 | } | |||
| 7297 | return true; | |||
| 7298 | } | |||
| 7299 | ||||
| 7300 | namespace { | |||
| 7301 | ||||
| 7302 | class ExtraFlags { | |||
| 7303 | unsigned Flags = 0; | |||
| 7304 | ||||
| 7305 | public: | |||
| 7306 | explicit ExtraFlags(ImmutableCallSite CS) { | |||
| 7307 | const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue()); | |||
| 7308 | if (IA->hasSideEffects()) | |||
| 7309 | Flags |= InlineAsm::Extra_HasSideEffects; | |||
| 7310 | if (IA->isAlignStack()) | |||
| 7311 | Flags |= InlineAsm::Extra_IsAlignStack; | |||
| 7312 | if (CS.isConvergent()) | |||
| 7313 | Flags |= InlineAsm::Extra_IsConvergent; | |||
| 7314 | Flags |= IA->getDialect() * InlineAsm::Extra_AsmDialect; | |||
| 7315 | } | |||
| 7316 | ||||
| 7317 | void update(const TargetLowering::AsmOperandInfo &OpInfo) { | |||
| 7318 | // Ideally, we would only check against memory constraints. However, the | |||
| 7319 | // meaning of an Other constraint can be target-specific and we can't easily | |||
| 7320 | // reason about it. Therefore, be conservative and set MayLoad/MayStore | |||
| 7321 | // for Other constraints as well. | |||
| 7322 | if (OpInfo.ConstraintType == TargetLowering::C_Memory || | |||
| 7323 | OpInfo.ConstraintType == TargetLowering::C_Other) { | |||
| 7324 | if (OpInfo.Type == InlineAsm::isInput) | |||
| 7325 | Flags |= InlineAsm::Extra_MayLoad; | |||
| 7326 | else if (OpInfo.Type == InlineAsm::isOutput) | |||
| 7327 | Flags |= InlineAsm::Extra_MayStore; | |||
| 7328 | else if (OpInfo.Type == InlineAsm::isClobber) | |||
| 7329 | Flags |= (InlineAsm::Extra_MayLoad | InlineAsm::Extra_MayStore); | |||
| 7330 | } | |||
| 7331 | } | |||
| 7332 | ||||
| 7333 | unsigned get() const { return Flags; } | |||
| 7334 | }; | |||
| 7335 | ||||
| 7336 | } // end anonymous namespace | |||
| 7337 | ||||
| 7338 | /// visitInlineAsm - Handle a call to an InlineAsm object. | |||
| 7339 | void SelectionDAGBuilder::visitInlineAsm(ImmutableCallSite CS) { | |||
| 7340 | const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue()); | |||
| 7341 | ||||
| 7342 | /// ConstraintOperands - Information about all of the constraints. | |||
| 7343 | SDISelAsmOperandInfoVector ConstraintOperands; | |||
| 7344 | ||||
| 7345 | const TargetLowering &TLI = DAG.getTargetLoweringInfo(); | |||
| 7346 | TargetLowering::AsmOperandInfoVector TargetConstraints = TLI.ParseConstraints( | |||
| 7347 | DAG.getDataLayout(), DAG.getSubtarget().getRegisterInfo(), CS); | |||
| 7348 | ||||
| 7349 | bool hasMemory = false; | |||
| 7350 | ||||
| 7351 | // Remember the HasSideEffect, AlignStack, AsmDialect, MayLoad and MayStore | |||
| 7352 | ExtraFlags ExtraInfo(CS); | |||
| 7353 | ||||
| 7354 | unsigned ArgNo = 0; // ArgNo - The argument of the CallInst. | |||
| 7355 | unsigned ResNo = 0; // ResNo - The result number of the next output. | |||
| 7356 | for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) { | |||
| ||||
| 7357 | ConstraintOperands.push_back(SDISelAsmOperandInfo(TargetConstraints[i])); | |||
| 7358 | SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back(); | |||
| 7359 | ||||
| 7360 | MVT OpVT = MVT::Other; | |||
| 7361 | ||||
| 7362 | // Compute the value type for each operand. | |||
| 7363 | if (OpInfo.Type == InlineAsm::isInput || | |||
| 7364 | (OpInfo.Type == InlineAsm::isOutput && OpInfo.isIndirect)) { | |||
| 7365 | OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++)); | |||
| 7366 | ||||
| 7367 | // Process the call argument. BasicBlocks are labels, currently appearing | |||
| 7368 | // only in asm's. | |||
| 7369 | if (const BasicBlock *BB = dyn_cast<BasicBlock>(OpInfo.CallOperandVal)) { | |||
| 7370 | OpInfo.CallOperand = DAG.getBasicBlock(FuncInfo.MBBMap[BB]); | |||
| 7371 | } else { | |||
| 7372 | OpInfo.CallOperand = getValue(OpInfo.CallOperandVal); | |||
| 7373 | } | |||
| 7374 | ||||
| 7375 | OpVT = | |||
| 7376 | OpInfo | |||
| 7377 | .getCallOperandValEVT(*DAG.getContext(), TLI, DAG.getDataLayout()) | |||
| 7378 | .getSimpleVT(); | |||
| 7379 | } | |||
| 7380 | ||||
| 7381 | if (OpInfo.Type == InlineAsm::isOutput && !OpInfo.isIndirect) { | |||
| 7382 | // The return value of the call is this value. As such, there is no | |||
| 7383 | // corresponding argument. | |||
| 7384 | assert(!CS.getType()->isVoidTy() && "Bad inline asm!")(static_cast <bool> (!CS.getType()->isVoidTy() && "Bad inline asm!") ? void (0) : __assert_fail ("!CS.getType()->isVoidTy() && \"Bad inline asm!\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 7384, __extension__ __PRETTY_FUNCTION__)); | |||
| 7385 | if (StructType *STy = dyn_cast<StructType>(CS.getType())) { | |||
| 7386 | OpVT = TLI.getSimpleValueType(DAG.getDataLayout(), | |||
| 7387 | STy->getElementType(ResNo)); | |||
| 7388 | } else { | |||
| 7389 | assert(ResNo == 0 && "Asm only has one result!")(static_cast <bool> (ResNo == 0 && "Asm only has one result!" ) ? void (0) : __assert_fail ("ResNo == 0 && \"Asm only has one result!\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 7389, __extension__ __PRETTY_FUNCTION__)); | |||
| 7390 | OpVT = TLI.getSimpleValueType(DAG.getDataLayout(), CS.getType()); | |||
| 7391 | } | |||
| 7392 | ++ResNo; | |||
| 7393 | } | |||
| 7394 | ||||
| 7395 | OpInfo.ConstraintVT = OpVT; | |||
| 7396 | ||||
| 7397 | if (!hasMemory) | |||
| 7398 | hasMemory = OpInfo.hasMemory(TLI); | |||
| 7399 | ||||
| 7400 | // Determine if this InlineAsm MayLoad or MayStore based on the constraints. | |||
| 7401 | // FIXME: Could we compute this on OpInfo rather than TargetConstraints[i]? | |||
| 7402 | auto TargetConstraint = TargetConstraints[i]; | |||
| 7403 | ||||
| 7404 | // Compute the constraint code and ConstraintType to use. | |||
| 7405 | TLI.ComputeConstraintToUse(TargetConstraint, SDValue()); | |||
| 7406 | ||||
| 7407 | ExtraInfo.update(TargetConstraint); | |||
| 7408 | } | |||
| 7409 | ||||
| 7410 | SDValue Chain, Flag; | |||
| 7411 | ||||
| 7412 | // We won't need to flush pending loads if this asm doesn't touch | |||
| 7413 | // memory and is nonvolatile. | |||
| 7414 | if (hasMemory || IA->hasSideEffects()) | |||
| 7415 | Chain = getRoot(); | |||
| 7416 | else | |||
| 7417 | Chain = DAG.getRoot(); | |||
| 7418 | ||||
| 7419 | // Second pass over the constraints: compute which constraint option to use | |||
| 7420 | // and assign registers to constraints that want a specific physreg. | |||
| 7421 | for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) { | |||
| 7422 | SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i]; | |||
| 7423 | ||||
| 7424 | // If this is an output operand with a matching input operand, look up the | |||
| 7425 | // matching input. If their types mismatch, e.g. one is an integer, the | |||
| 7426 | // other is floating point, or their sizes are different, flag it as an | |||
| 7427 | // error. | |||
| 7428 | if (OpInfo.hasMatchingInput()) { | |||
| 7429 | SDISelAsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput]; | |||
| 7430 | patchMatchingInput(OpInfo, Input, DAG); | |||
| 7431 | } | |||
| 7432 | ||||
| 7433 | // Compute the constraint code and ConstraintType to use. | |||
| 7434 | TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, &DAG); | |||
| 7435 | ||||
| 7436 | if (OpInfo.ConstraintType == TargetLowering::C_Memory && | |||
| 7437 | OpInfo.Type == InlineAsm::isClobber) | |||
| 7438 | continue; | |||
| 7439 | ||||
| 7440 | // If this is a memory input, and if the operand is not indirect, do what we | |||
| 7441 | // need to provide an address for the memory input. | |||
| 7442 | if (OpInfo.ConstraintType == TargetLowering::C_Memory && | |||
| 7443 | !OpInfo.isIndirect) { | |||
| 7444 | assert((OpInfo.isMultipleAlternative ||(static_cast <bool> ((OpInfo.isMultipleAlternative || ( OpInfo.Type == InlineAsm::isInput)) && "Can only indirectify direct input operands!" ) ? void (0) : __assert_fail ("(OpInfo.isMultipleAlternative || (OpInfo.Type == InlineAsm::isInput)) && \"Can only indirectify direct input operands!\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 7446, __extension__ __PRETTY_FUNCTION__)) | |||
| 7445 | (OpInfo.Type == InlineAsm::isInput)) &&(static_cast <bool> ((OpInfo.isMultipleAlternative || ( OpInfo.Type == InlineAsm::isInput)) && "Can only indirectify direct input operands!" ) ? void (0) : __assert_fail ("(OpInfo.isMultipleAlternative || (OpInfo.Type == InlineAsm::isInput)) && \"Can only indirectify direct input operands!\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 7446, __extension__ __PRETTY_FUNCTION__)) | |||
| 7446 | "Can only indirectify direct input operands!")(static_cast <bool> ((OpInfo.isMultipleAlternative || ( OpInfo.Type == InlineAsm::isInput)) && "Can only indirectify direct input operands!" ) ? void (0) : __assert_fail ("(OpInfo.isMultipleAlternative || (OpInfo.Type == InlineAsm::isInput)) && \"Can only indirectify direct input operands!\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 7446, __extension__ __PRETTY_FUNCTION__)); | |||
| 7447 | ||||
| 7448 | // Memory operands really want the address of the value. | |||
| 7449 | Chain = getAddressForMemoryInput(Chain, getCurSDLoc(), OpInfo, DAG); | |||
| 7450 | ||||
| 7451 | // There is no longer a Value* corresponding to this operand. | |||
| 7452 | OpInfo.CallOperandVal = nullptr; | |||
| 7453 | ||||
| 7454 | // It is now an indirect operand. | |||
| 7455 | OpInfo.isIndirect = true; | |||
| 7456 | } | |||
| 7457 | ||||
| 7458 | // If this constraint is for a specific register, allocate it before | |||
| 7459 | // anything else. | |||
| 7460 | if (OpInfo.ConstraintType == TargetLowering::C_Register) | |||
| 7461 | GetRegistersForValue(DAG, TLI, getCurSDLoc(), OpInfo); | |||
| 7462 | } | |||
| 7463 | ||||
| 7464 | // Third pass - Loop over all of the operands, assigning virtual or physregs | |||
| 7465 | // to register class operands. | |||
| 7466 | for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) { | |||
| 7467 | SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i]; | |||
| 7468 | ||||
| 7469 | // C_Register operands have already been allocated, Other/Memory don't need | |||
| 7470 | // to be. | |||
| 7471 | if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass) | |||
| 7472 | GetRegistersForValue(DAG, TLI, getCurSDLoc(), OpInfo); | |||
| 7473 | } | |||
| 7474 | ||||
| 7475 | // AsmNodeOperands - The operands for the ISD::INLINEASM node. | |||
| 7476 | std::vector<SDValue> AsmNodeOperands; | |||
| 7477 | AsmNodeOperands.push_back(SDValue()); // reserve space for input chain | |||
| 7478 | AsmNodeOperands.push_back(DAG.getTargetExternalSymbol( | |||
| 7479 | IA->getAsmString().c_str(), TLI.getPointerTy(DAG.getDataLayout()))); | |||
| 7480 | ||||
| 7481 | // If we have a !srcloc metadata node associated with it, we want to attach | |||
| 7482 | // this to the ultimately generated inline asm machineinstr. To do this, we | |||
| 7483 | // pass in the third operand as this (potentially null) inline asm MDNode. | |||
| 7484 | const MDNode *SrcLoc = CS.getInstruction()->getMetadata("srcloc"); | |||
| 7485 | AsmNodeOperands.push_back(DAG.getMDNode(SrcLoc)); | |||
| 7486 | ||||
| 7487 | // Remember the HasSideEffect, AlignStack, AsmDialect, MayLoad and MayStore | |||
| 7488 | // bits as operand 3. | |||
| 7489 | AsmNodeOperands.push_back(DAG.getTargetConstant( | |||
| 7490 | ExtraInfo.get(), getCurSDLoc(), TLI.getPointerTy(DAG.getDataLayout()))); | |||
| 7491 | ||||
| 7492 | // Loop over all of the inputs, copying the operand values into the | |||
| 7493 | // appropriate registers and processing the output regs. | |||
| 7494 | RegsForValue RetValRegs; | |||
| 7495 | ||||
| 7496 | // IndirectStoresToEmit - The set of stores to emit after the inline asm node. | |||
| 7497 | std::vector<std::pair<RegsForValue, Value *>> IndirectStoresToEmit; | |||
| 7498 | ||||
| 7499 | for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) { | |||
| 7500 | SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i]; | |||
| 7501 | ||||
| 7502 | switch (OpInfo.Type) { | |||
| 7503 | case InlineAsm::isOutput: | |||
| 7504 | if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass && | |||
| 7505 | OpInfo.ConstraintType != TargetLowering::C_Register) { | |||
| 7506 | // Memory output, or 'other' output (e.g. 'X' constraint). | |||
| 7507 | assert(OpInfo.isIndirect && "Memory output must be indirect operand")(static_cast <bool> (OpInfo.isIndirect && "Memory output must be indirect operand" ) ? void (0) : __assert_fail ("OpInfo.isIndirect && \"Memory output must be indirect operand\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 7507, __extension__ __PRETTY_FUNCTION__)); | |||
| 7508 | ||||
| 7509 | unsigned ConstraintID = | |||
| 7510 | TLI.getInlineAsmMemConstraint(OpInfo.ConstraintCode); | |||
| 7511 | assert(ConstraintID != InlineAsm::Constraint_Unknown &&(static_cast <bool> (ConstraintID != InlineAsm::Constraint_Unknown && "Failed to convert memory constraint code to constraint id." ) ? void (0) : __assert_fail ("ConstraintID != InlineAsm::Constraint_Unknown && \"Failed to convert memory constraint code to constraint id.\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 7512, __extension__ __PRETTY_FUNCTION__)) | |||
| 7512 | "Failed to convert memory constraint code to constraint id.")(static_cast <bool> (ConstraintID != InlineAsm::Constraint_Unknown && "Failed to convert memory constraint code to constraint id." ) ? void (0) : __assert_fail ("ConstraintID != InlineAsm::Constraint_Unknown && \"Failed to convert memory constraint code to constraint id.\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 7512, __extension__ __PRETTY_FUNCTION__)); | |||
| 7513 | ||||
| 7514 | // Add information to the INLINEASM node to know about this output. | |||
| 7515 | unsigned OpFlags = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1); | |||
| 7516 | OpFlags = InlineAsm::getFlagWordForMem(OpFlags, ConstraintID); | |||
| 7517 | AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlags, getCurSDLoc(), | |||
| 7518 | MVT::i32)); | |||
| 7519 | AsmNodeOperands.push_back(OpInfo.CallOperand); | |||
| 7520 | break; | |||
| 7521 | } | |||
| 7522 | ||||
| 7523 | // Otherwise, this is a register or register class output. | |||
| 7524 | ||||
| 7525 | // Copy the output from the appropriate register. Find a register that | |||
| 7526 | // we can use. | |||
| 7527 | if (OpInfo.AssignedRegs.Regs.empty()) { | |||
| 7528 | emitInlineAsmError( | |||
| 7529 | CS, "couldn't allocate output register for constraint '" + | |||
| 7530 | Twine(OpInfo.ConstraintCode) + "'"); | |||
| 7531 | return; | |||
| 7532 | } | |||
| 7533 | ||||
| 7534 | // If this is an indirect operand, store through the pointer after the | |||
| 7535 | // asm. | |||
| 7536 | if (OpInfo.isIndirect) { | |||
| 7537 | IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs, | |||
| 7538 | OpInfo.CallOperandVal)); | |||
| 7539 | } else { | |||
| 7540 | // This is the result value of the call. | |||
| 7541 | assert(!CS.getType()->isVoidTy() && "Bad inline asm!")(static_cast <bool> (!CS.getType()->isVoidTy() && "Bad inline asm!") ? void (0) : __assert_fail ("!CS.getType()->isVoidTy() && \"Bad inline asm!\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 7541, __extension__ __PRETTY_FUNCTION__)); | |||
| 7542 | // Concatenate this output onto the outputs list. | |||
| 7543 | RetValRegs.append(OpInfo.AssignedRegs); | |||
| 7544 | } | |||
| 7545 | ||||
| 7546 | // Add information to the INLINEASM node to know that this register is | |||
| 7547 | // set. | |||
| 7548 | OpInfo.AssignedRegs | |||
| 7549 | .AddInlineAsmOperands(OpInfo.isEarlyClobber | |||
| 7550 | ? InlineAsm::Kind_RegDefEarlyClobber | |||
| 7551 | : InlineAsm::Kind_RegDef, | |||
| 7552 | false, 0, getCurSDLoc(), DAG, AsmNodeOperands); | |||
| 7553 | break; | |||
| 7554 | ||||
| 7555 | case InlineAsm::isInput: { | |||
| 7556 | SDValue InOperandVal = OpInfo.CallOperand; | |||
| 7557 | ||||
| 7558 | if (OpInfo.isMatchingInputConstraint()) { | |||
| 7559 | // If this is required to match an output register we have already set, | |||
| 7560 | // just use its register. | |||
| 7561 | auto CurOp = findMatchingInlineAsmOperand(OpInfo.getMatchedOperand(), | |||
| 7562 | AsmNodeOperands); | |||
| 7563 | unsigned OpFlag = | |||
| 7564 | cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue(); | |||
| 7565 | if (InlineAsm::isRegDefKind(OpFlag) || | |||
| 7566 | InlineAsm::isRegDefEarlyClobberKind(OpFlag)) { | |||
| 7567 | // Add (OpFlag&0xffff)>>3 registers to MatchedRegs. | |||
| 7568 | if (OpInfo.isIndirect) { | |||
| 7569 | // This happens on gcc/testsuite/gcc.dg/pr8788-1.c | |||
| 7570 | emitInlineAsmError(CS, "inline asm not supported yet:" | |||
| 7571 | " don't know how to handle tied " | |||
| 7572 | "indirect register inputs"); | |||
| 7573 | return; | |||
| 7574 | } | |||
| 7575 | ||||
| 7576 | MVT RegVT = AsmNodeOperands[CurOp+1].getSimpleValueType(); | |||
| 7577 | SmallVector<unsigned, 4> Regs; | |||
| 7578 | ||||
| 7579 | if (!createVirtualRegs(Regs, | |||
| 7580 | InlineAsm::getNumOperandRegisters(OpFlag), | |||
| 7581 | RegVT, DAG)) { | |||
| 7582 | emitInlineAsmError(CS, "inline asm error: This value type register " | |||
| 7583 | "class is not natively supported!"); | |||
| 7584 | return; | |||
| 7585 | } | |||
| 7586 | ||||
| 7587 | RegsForValue MatchedRegs(Regs, RegVT, InOperandVal.getValueType()); | |||
| 7588 | ||||
| 7589 | SDLoc dl = getCurSDLoc(); | |||
| 7590 | // Use the produced MatchedRegs object to | |||
| 7591 | MatchedRegs.getCopyToRegs(InOperandVal, DAG, dl, Chain, &Flag, | |||
| 7592 | CS.getInstruction()); | |||
| 7593 | MatchedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse, | |||
| 7594 | true, OpInfo.getMatchedOperand(), dl, | |||
| 7595 | DAG, AsmNodeOperands); | |||
| 7596 | break; | |||
| 7597 | } | |||
| 7598 | ||||
| 7599 | assert(InlineAsm::isMemKind(OpFlag) && "Unknown matching constraint!")(static_cast <bool> (InlineAsm::isMemKind(OpFlag) && "Unknown matching constraint!") ? void (0) : __assert_fail ( "InlineAsm::isMemKind(OpFlag) && \"Unknown matching constraint!\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 7599, __extension__ __PRETTY_FUNCTION__)); | |||
| 7600 | assert(InlineAsm::getNumOperandRegisters(OpFlag) == 1 &&(static_cast <bool> (InlineAsm::getNumOperandRegisters( OpFlag) == 1 && "Unexpected number of operands") ? void (0) : __assert_fail ("InlineAsm::getNumOperandRegisters(OpFlag) == 1 && \"Unexpected number of operands\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 7601, __extension__ __PRETTY_FUNCTION__)) | |||
| 7601 | "Unexpected number of operands")(static_cast <bool> (InlineAsm::getNumOperandRegisters( OpFlag) == 1 && "Unexpected number of operands") ? void (0) : __assert_fail ("InlineAsm::getNumOperandRegisters(OpFlag) == 1 && \"Unexpected number of operands\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 7601, __extension__ __PRETTY_FUNCTION__)); | |||
| 7602 | // Add information to the INLINEASM node to know about this input. | |||
| 7603 | // See InlineAsm.h isUseOperandTiedToDef. | |||
| 7604 | OpFlag = InlineAsm::convertMemFlagWordToMatchingFlagWord(OpFlag); | |||
| 7605 | OpFlag = InlineAsm::getFlagWordForMatchingOp(OpFlag, | |||
| 7606 | OpInfo.getMatchedOperand()); | |||
| 7607 | AsmNodeOperands.push_back(DAG.getTargetConstant( | |||
| 7608 | OpFlag, getCurSDLoc(), TLI.getPointerTy(DAG.getDataLayout()))); | |||
| 7609 | AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]); | |||
| 7610 | break; | |||
| 7611 | } | |||
| 7612 | ||||
| 7613 | // Treat indirect 'X' constraint as memory. | |||
| 7614 | if (OpInfo.ConstraintType == TargetLowering::C_Other && | |||
| 7615 | OpInfo.isIndirect) | |||
| 7616 | OpInfo.ConstraintType = TargetLowering::C_Memory; | |||
| 7617 | ||||
| 7618 | if (OpInfo.ConstraintType == TargetLowering::C_Other) { | |||
| 7619 | std::vector<SDValue> Ops; | |||
| 7620 | TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode, | |||
| 7621 | Ops, DAG); | |||
| 7622 | if (Ops.empty()) { | |||
| 7623 | emitInlineAsmError(CS, "invalid operand for inline asm constraint '" + | |||
| 7624 | Twine(OpInfo.ConstraintCode) + "'"); | |||
| 7625 | return; | |||
| 7626 | } | |||
| 7627 | ||||
| 7628 | // Add information to the INLINEASM node to know about this input. | |||
| 7629 | unsigned ResOpType = | |||
| 7630 | InlineAsm::getFlagWord(InlineAsm::Kind_Imm, Ops.size()); | |||
| 7631 | AsmNodeOperands.push_back(DAG.getTargetConstant( | |||
| 7632 | ResOpType, getCurSDLoc(), TLI.getPointerTy(DAG.getDataLayout()))); | |||
| 7633 | AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end()); | |||
| 7634 | break; | |||
| 7635 | } | |||
| 7636 | ||||
| 7637 | if (OpInfo.ConstraintType == TargetLowering::C_Memory) { | |||
| 7638 | assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!")(static_cast <bool> (OpInfo.isIndirect && "Operand must be indirect to be a mem!" ) ? void (0) : __assert_fail ("OpInfo.isIndirect && \"Operand must be indirect to be a mem!\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 7638, __extension__ __PRETTY_FUNCTION__)); | |||
| 7639 | assert(InOperandVal.getValueType() ==(static_cast <bool> (InOperandVal.getValueType() == TLI .getPointerTy(DAG.getDataLayout()) && "Memory operands expect pointer values" ) ? void (0) : __assert_fail ("InOperandVal.getValueType() == TLI.getPointerTy(DAG.getDataLayout()) && \"Memory operands expect pointer values\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 7641, __extension__ __PRETTY_FUNCTION__)) | |||
| 7640 | TLI.getPointerTy(DAG.getDataLayout()) &&(static_cast <bool> (InOperandVal.getValueType() == TLI .getPointerTy(DAG.getDataLayout()) && "Memory operands expect pointer values" ) ? void (0) : __assert_fail ("InOperandVal.getValueType() == TLI.getPointerTy(DAG.getDataLayout()) && \"Memory operands expect pointer values\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 7641, __extension__ __PRETTY_FUNCTION__)) | |||
| 7641 | "Memory operands expect pointer values")(static_cast <bool> (InOperandVal.getValueType() == TLI .getPointerTy(DAG.getDataLayout()) && "Memory operands expect pointer values" ) ? void (0) : __assert_fail ("InOperandVal.getValueType() == TLI.getPointerTy(DAG.getDataLayout()) && \"Memory operands expect pointer values\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 7641, __extension__ __PRETTY_FUNCTION__)); | |||
| 7642 | ||||
| 7643 | unsigned ConstraintID = | |||
| 7644 | TLI.getInlineAsmMemConstraint(OpInfo.ConstraintCode); | |||
| 7645 | assert(ConstraintID != InlineAsm::Constraint_Unknown &&(static_cast <bool> (ConstraintID != InlineAsm::Constraint_Unknown && "Failed to convert memory constraint code to constraint id." ) ? void (0) : __assert_fail ("ConstraintID != InlineAsm::Constraint_Unknown && \"Failed to convert memory constraint code to constraint id.\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 7646, __extension__ __PRETTY_FUNCTION__)) | |||
| 7646 | "Failed to convert memory constraint code to constraint id.")(static_cast <bool> (ConstraintID != InlineAsm::Constraint_Unknown && "Failed to convert memory constraint code to constraint id." ) ? void (0) : __assert_fail ("ConstraintID != InlineAsm::Constraint_Unknown && \"Failed to convert memory constraint code to constraint id.\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 7646, __extension__ __PRETTY_FUNCTION__)); | |||
| 7647 | ||||
| 7648 | // Add information to the INLINEASM node to know about this input. | |||
| 7649 | unsigned ResOpType = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1); | |||
| 7650 | ResOpType = InlineAsm::getFlagWordForMem(ResOpType, ConstraintID); | |||
| 7651 | AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType, | |||
| 7652 | getCurSDLoc(), | |||
| 7653 | MVT::i32)); | |||
| 7654 | AsmNodeOperands.push_back(InOperandVal); | |||
| 7655 | break; | |||
| 7656 | } | |||
| 7657 | ||||
| 7658 | assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass ||(static_cast <bool> ((OpInfo.ConstraintType == TargetLowering ::C_RegisterClass || OpInfo.ConstraintType == TargetLowering:: C_Register) && "Unknown constraint type!") ? void (0) : __assert_fail ("(OpInfo.ConstraintType == TargetLowering::C_RegisterClass || OpInfo.ConstraintType == TargetLowering::C_Register) && \"Unknown constraint type!\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 7660, __extension__ __PRETTY_FUNCTION__)) | |||
| 7659 | OpInfo.ConstraintType == TargetLowering::C_Register) &&(static_cast <bool> ((OpInfo.ConstraintType == TargetLowering ::C_RegisterClass || OpInfo.ConstraintType == TargetLowering:: C_Register) && "Unknown constraint type!") ? void (0) : __assert_fail ("(OpInfo.ConstraintType == TargetLowering::C_RegisterClass || OpInfo.ConstraintType == TargetLowering::C_Register) && \"Unknown constraint type!\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 7660, __extension__ __PRETTY_FUNCTION__)) | |||
| 7660 | "Unknown constraint type!")(static_cast <bool> ((OpInfo.ConstraintType == TargetLowering ::C_RegisterClass || OpInfo.ConstraintType == TargetLowering:: C_Register) && "Unknown constraint type!") ? void (0) : __assert_fail ("(OpInfo.ConstraintType == TargetLowering::C_RegisterClass || OpInfo.ConstraintType == TargetLowering::C_Register) && \"Unknown constraint type!\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 7660, __extension__ __PRETTY_FUNCTION__)); | |||
| 7661 | ||||
| 7662 | // TODO: Support this. | |||
| 7663 | if (OpInfo.isIndirect) { | |||
| 7664 | emitInlineAsmError( | |||
| 7665 | CS, "Don't know how to handle indirect register inputs yet " | |||
| 7666 | "for constraint '" + | |||
| 7667 | Twine(OpInfo.ConstraintCode) + "'"); | |||
| 7668 | return; | |||
| 7669 | } | |||
| 7670 | ||||
| 7671 | // Copy the input into the appropriate registers. | |||
| 7672 | if (OpInfo.AssignedRegs.Regs.empty()) { | |||
| 7673 | emitInlineAsmError(CS, "couldn't allocate input reg for constraint '" + | |||
| 7674 | Twine(OpInfo.ConstraintCode) + "'"); | |||
| 7675 | return; | |||
| 7676 | } | |||
| 7677 | ||||
| 7678 | SDLoc dl = getCurSDLoc(); | |||
| 7679 | ||||
| 7680 | OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, dl, | |||
| 7681 | Chain, &Flag, CS.getInstruction()); | |||
| 7682 | ||||
| 7683 | OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse, false, 0, | |||
| 7684 | dl, DAG, AsmNodeOperands); | |||
| 7685 | break; | |||
| 7686 | } | |||
| 7687 | case InlineAsm::isClobber: | |||
| 7688 | // Add the clobbered value to the operand list, so that the register | |||
| 7689 | // allocator is aware that the physreg got clobbered. | |||
| 7690 | if (!OpInfo.AssignedRegs.Regs.empty()) | |||
| 7691 | OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_Clobber, | |||
| 7692 | false, 0, getCurSDLoc(), DAG, | |||
| 7693 | AsmNodeOperands); | |||
| 7694 | break; | |||
| 7695 | } | |||
| 7696 | } | |||
| 7697 | ||||
| 7698 | // Finish up input operands. Set the input chain and add the flag last. | |||
| 7699 | AsmNodeOperands[InlineAsm::Op_InputChain] = Chain; | |||
| 7700 | if (Flag.getNode()) AsmNodeOperands.push_back(Flag); | |||
| 7701 | ||||
| 7702 | Chain = DAG.getNode(ISD::INLINEASM, getCurSDLoc(), | |||
| 7703 | DAG.getVTList(MVT::Other, MVT::Glue), AsmNodeOperands); | |||
| 7704 | Flag = Chain.getValue(1); | |||
| 7705 | ||||
| 7706 | // If this asm returns a register value, copy the result from that register | |||
| 7707 | // and set it as the value of the call. | |||
| 7708 | if (!RetValRegs.Regs.empty()) { | |||
| 7709 | SDValue Val = RetValRegs.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(), | |||
| 7710 | Chain, &Flag, CS.getInstruction()); | |||
| 7711 | ||||
| 7712 | // FIXME: Why don't we do this for inline asms with MRVs? | |||
| 7713 | if (CS.getType()->isSingleValueType() && CS.getType()->isSized()) { | |||
| 7714 | EVT ResultType = TLI.getValueType(DAG.getDataLayout(), CS.getType()); | |||
| 7715 | ||||
| 7716 | // If any of the results of the inline asm is a vector, it may have the | |||
| 7717 | // wrong width/num elts. This can happen for register classes that can | |||
| 7718 | // contain multiple different value types. The preg or vreg allocated may | |||
| 7719 | // not have the same VT as was expected. Convert it to the right type | |||
| 7720 | // with bit_convert. | |||
| 7721 | if (ResultType != Val.getValueType() && Val.getValueType().isVector()) { | |||
| 7722 | Val = DAG.getNode(ISD::BITCAST, getCurSDLoc(), | |||
| 7723 | ResultType, Val); | |||
| 7724 | ||||
| 7725 | } else if (ResultType != Val.getValueType() && | |||
| 7726 | ResultType.isInteger() && Val.getValueType().isInteger()) { | |||
| 7727 | // If a result value was tied to an input value, the computed result may | |||
| 7728 | // have a wider width than the expected result. Extract the relevant | |||
| 7729 | // portion. | |||
| 7730 | Val = DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), ResultType, Val); | |||
| 7731 | } | |||
| 7732 | ||||
| 7733 | assert(ResultType == Val.getValueType() && "Asm result value mismatch!")(static_cast <bool> (ResultType == Val.getValueType() && "Asm result value mismatch!") ? void (0) : __assert_fail ("ResultType == Val.getValueType() && \"Asm result value mismatch!\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 7733, __extension__ __PRETTY_FUNCTION__)); | |||
| 7734 | } | |||
| 7735 | ||||
| 7736 | setValue(CS.getInstruction(), Val); | |||
| 7737 | // Don't need to use this as a chain in this case. | |||
| 7738 | if (!IA->hasSideEffects() && !hasMemory && IndirectStoresToEmit.empty()) | |||
| 7739 | return; | |||
| 7740 | } | |||
| 7741 | ||||
| 7742 | std::vector<std::pair<SDValue, const Value *>> StoresToEmit; | |||
| 7743 | ||||
| 7744 | // Process indirect outputs, first output all of the flagged copies out of | |||
| 7745 | // physregs. | |||
| 7746 | for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) { | |||
| 7747 | RegsForValue &OutRegs = IndirectStoresToEmit[i].first; | |||
| 7748 | const Value *Ptr = IndirectStoresToEmit[i].second; | |||
| 7749 | SDValue OutVal = OutRegs.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(), | |||
| 7750 | Chain, &Flag, IA); | |||
| 7751 | StoresToEmit.push_back(std::make_pair(OutVal, Ptr)); | |||
| 7752 | } | |||
| 7753 | ||||
| 7754 | // Emit the non-flagged stores from the physregs. | |||
| 7755 | SmallVector<SDValue, 8> OutChains; | |||
| 7756 | for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i) { | |||
| 7757 | SDValue Val = DAG.getStore(Chain, getCurSDLoc(), StoresToEmit[i].first, | |||
| 7758 | getValue(StoresToEmit[i].second), | |||
| 7759 | MachinePointerInfo(StoresToEmit[i].second)); | |||
| 7760 | OutChains.push_back(Val); | |||
| 7761 | } | |||
| 7762 | ||||
| 7763 | if (!OutChains.empty()) | |||
| 7764 | Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other, OutChains); | |||
| 7765 | ||||
| 7766 | DAG.setRoot(Chain); | |||
| 7767 | } | |||
| 7768 | ||||
| 7769 | void SelectionDAGBuilder::emitInlineAsmError(ImmutableCallSite CS, | |||
| 7770 | const Twine &Message) { | |||
| 7771 | LLVMContext &Ctx = *DAG.getContext(); | |||
| 7772 | Ctx.emitError(CS.getInstruction(), Message); | |||
| 7773 | ||||
| 7774 | // Make sure we leave the DAG in a valid state | |||
| 7775 | const TargetLowering &TLI = DAG.getTargetLoweringInfo(); | |||
| 7776 | SmallVector<EVT, 1> ValueVTs; | |||
| 7777 | ComputeValueVTs(TLI, DAG.getDataLayout(), CS->getType(), ValueVTs); | |||
| 7778 | ||||
| 7779 | if (ValueVTs.empty()) | |||
| 7780 | return; | |||
| 7781 | ||||
| 7782 | SmallVector<SDValue, 1> Ops; | |||
| 7783 | for (unsigned i = 0, e = ValueVTs.size(); i != e; ++i) | |||
| 7784 | Ops.push_back(DAG.getUNDEF(ValueVTs[i])); | |||
| 7785 | ||||
| 7786 | setValue(CS.getInstruction(), DAG.getMergeValues(Ops, getCurSDLoc())); | |||
| 7787 | } | |||
| 7788 | ||||
| 7789 | void SelectionDAGBuilder::visitVAStart(const CallInst &I) { | |||
| 7790 | DAG.setRoot(DAG.getNode(ISD::VASTART, getCurSDLoc(), | |||
| 7791 | MVT::Other, getRoot(), | |||
| 7792 | getValue(I.getArgOperand(0)), | |||
| 7793 | DAG.getSrcValue(I.getArgOperand(0)))); | |||
| 7794 | } | |||
| 7795 | ||||
| 7796 | void SelectionDAGBuilder::visitVAArg(const VAArgInst &I) { | |||
| 7797 | const TargetLowering &TLI = DAG.getTargetLoweringInfo(); | |||
| 7798 | const DataLayout &DL = DAG.getDataLayout(); | |||
| 7799 | SDValue V = DAG.getVAArg(TLI.getValueType(DAG.getDataLayout(), I.getType()), | |||
| 7800 | getCurSDLoc(), getRoot(), getValue(I.getOperand(0)), | |||
| 7801 | DAG.getSrcValue(I.getOperand(0)), | |||
| 7802 | DL.getABITypeAlignment(I.getType())); | |||
| 7803 | setValue(&I, V); | |||
| 7804 | DAG.setRoot(V.getValue(1)); | |||
| 7805 | } | |||
| 7806 | ||||
| 7807 | void SelectionDAGBuilder::visitVAEnd(const CallInst &I) { | |||
| 7808 | DAG.setRoot(DAG.getNode(ISD::VAEND, getCurSDLoc(), | |||
| 7809 | MVT::Other, getRoot(), | |||
| 7810 | getValue(I.getArgOperand(0)), | |||
| 7811 | DAG.getSrcValue(I.getArgOperand(0)))); | |||
| 7812 | } | |||
| 7813 | ||||
| 7814 | void SelectionDAGBuilder::visitVACopy(const CallInst &I) { | |||
| 7815 | DAG.setRoot(DAG.getNode(ISD::VACOPY, getCurSDLoc(), | |||
| 7816 | MVT::Other, getRoot(), | |||
| 7817 | getValue(I.getArgOperand(0)), | |||
| 7818 | getValue(I.getArgOperand(1)), | |||
| 7819 | DAG.getSrcValue(I.getArgOperand(0)), | |||
| 7820 | DAG.getSrcValue(I.getArgOperand(1)))); | |||
| 7821 | } | |||
| 7822 | ||||
| 7823 | SDValue SelectionDAGBuilder::lowerRangeToAssertZExt(SelectionDAG &DAG, | |||
| 7824 | const Instruction &I, | |||
| 7825 | SDValue Op) { | |||
| 7826 | const MDNode *Range = I.getMetadata(LLVMContext::MD_range); | |||
| 7827 | if (!Range) | |||
| 7828 | return Op; | |||
| 7829 | ||||
| 7830 | ConstantRange CR = getConstantRangeFromMetadata(*Range); | |||
| 7831 | if (CR.isFullSet() || CR.isEmptySet() || CR.isWrappedSet()) | |||
| 7832 | return Op; | |||
| 7833 | ||||
| 7834 | APInt Lo = CR.getUnsignedMin(); | |||
| 7835 | if (!Lo.isMinValue()) | |||
| 7836 | return Op; | |||
| 7837 | ||||
| 7838 | APInt Hi = CR.getUnsignedMax(); | |||
| 7839 | unsigned Bits = Hi.getActiveBits(); | |||
| 7840 | ||||
| 7841 | EVT SmallVT = EVT::getIntegerVT(*DAG.getContext(), Bits); | |||
| 7842 | ||||
| 7843 | SDLoc SL = getCurSDLoc(); | |||
| 7844 | ||||
| 7845 | SDValue ZExt = DAG.getNode(ISD::AssertZext, SL, Op.getValueType(), Op, | |||
| 7846 | DAG.getValueType(SmallVT)); | |||
| 7847 | unsigned NumVals = Op.getNode()->getNumValues(); | |||
| 7848 | if (NumVals == 1) | |||
| 7849 | return ZExt; | |||
| 7850 | ||||
| 7851 | SmallVector<SDValue, 4> Ops; | |||
| 7852 | ||||
| 7853 | Ops.push_back(ZExt); | |||
| 7854 | for (unsigned I = 1; I != NumVals; ++I) | |||
| 7855 | Ops.push_back(Op.getValue(I)); | |||
| 7856 | ||||
| 7857 | return DAG.getMergeValues(Ops, SL); | |||
| 7858 | } | |||
| 7859 | ||||
| 7860 | /// Populate a CallLowerinInfo (into \p CLI) based on the properties of | |||
| 7861 | /// the call being lowered. | |||
| 7862 | /// | |||
| 7863 | /// This is a helper for lowering intrinsics that follow a target calling | |||
| 7864 | /// convention or require stack pointer adjustment. Only a subset of the | |||
| 7865 | /// intrinsic's operands need to participate in the calling convention. | |||
| 7866 | void SelectionDAGBuilder::populateCallLoweringInfo( | |||
| 7867 | TargetLowering::CallLoweringInfo &CLI, ImmutableCallSite CS, | |||
| 7868 | unsigned ArgIdx, unsigned NumArgs, SDValue Callee, Type *ReturnTy, | |||
| 7869 | bool IsPatchPoint) { | |||
| 7870 | TargetLowering::ArgListTy Args; | |||
| 7871 | Args.reserve(NumArgs); | |||
| 7872 | ||||
| 7873 | // Populate the argument list. | |||
| 7874 | // Attributes for args start at offset 1, after the return attribute. | |||
| 7875 | for (unsigned ArgI = ArgIdx, ArgE = ArgIdx + NumArgs; | |||
| 7876 | ArgI != ArgE; ++ArgI) { | |||
| 7877 | const Value *V = CS->getOperand(ArgI); | |||
| 7878 | ||||
| 7879 | assert(!V->getType()->isEmptyTy() && "Empty type passed to intrinsic.")(static_cast <bool> (!V->getType()->isEmptyTy() && "Empty type passed to intrinsic.") ? void (0) : __assert_fail ("!V->getType()->isEmptyTy() && \"Empty type passed to intrinsic.\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 7879, __extension__ __PRETTY_FUNCTION__)); | |||
| 7880 | ||||
| 7881 | TargetLowering::ArgListEntry Entry; | |||
| 7882 | Entry.Node = getValue(V); | |||
| 7883 | Entry.Ty = V->getType(); | |||
| 7884 | Entry.setAttributes(&CS, ArgI); | |||
| 7885 | Args.push_back(Entry); | |||
| 7886 | } | |||
| 7887 | ||||
| 7888 | CLI.setDebugLoc(getCurSDLoc()) | |||
| 7889 | .setChain(getRoot()) | |||
| 7890 | .setCallee(CS.getCallingConv(), ReturnTy, Callee, std::move(Args)) | |||
| 7891 | .setDiscardResult(CS->use_empty()) | |||
| 7892 | .setIsPatchPoint(IsPatchPoint); | |||
| 7893 | } | |||
| 7894 | ||||
| 7895 | /// Add a stack map intrinsic call's live variable operands to a stackmap | |||
| 7896 | /// or patchpoint target node's operand list. | |||
| 7897 | /// | |||
| 7898 | /// Constants are converted to TargetConstants purely as an optimization to | |||
| 7899 | /// avoid constant materialization and register allocation. | |||
| 7900 | /// | |||
| 7901 | /// FrameIndex operands are converted to TargetFrameIndex so that ISEL does not | |||
| 7902 | /// generate addess computation nodes, and so ExpandISelPseudo can convert the | |||
| 7903 | /// TargetFrameIndex into a DirectMemRefOp StackMap location. This avoids | |||
| 7904 | /// address materialization and register allocation, but may also be required | |||
| 7905 | /// for correctness. If a StackMap (or PatchPoint) intrinsic directly uses an | |||
| 7906 | /// alloca in the entry block, then the runtime may assume that the alloca's | |||
| 7907 | /// StackMap location can be read immediately after compilation and that the | |||
| 7908 | /// location is valid at any point during execution (this is similar to the | |||
| 7909 | /// assumption made by the llvm.gcroot intrinsic). If the alloca's location were | |||
| 7910 | /// only available in a register, then the runtime would need to trap when | |||
| 7911 | /// execution reaches the StackMap in order to read the alloca's location. | |||
| 7912 | static void addStackMapLiveVars(ImmutableCallSite CS, unsigned StartIdx, | |||
| 7913 | const SDLoc &DL, SmallVectorImpl<SDValue> &Ops, | |||
| 7914 | SelectionDAGBuilder &Builder) { | |||
| 7915 | for (unsigned i = StartIdx, e = CS.arg_size(); i != e; ++i) { | |||
| 7916 | SDValue OpVal = Builder.getValue(CS.getArgument(i)); | |||
| 7917 | if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(OpVal)) { | |||
| 7918 | Ops.push_back( | |||
| 7919 | Builder.DAG.getTargetConstant(StackMaps::ConstantOp, DL, MVT::i64)); | |||
| 7920 | Ops.push_back( | |||
| 7921 | Builder.DAG.getTargetConstant(C->getSExtValue(), DL, MVT::i64)); | |||
| 7922 | } else if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(OpVal)) { | |||
| 7923 | const TargetLowering &TLI = Builder.DAG.getTargetLoweringInfo(); | |||
| 7924 | Ops.push_back(Builder.DAG.getTargetFrameIndex( | |||
| 7925 | FI->getIndex(), TLI.getFrameIndexTy(Builder.DAG.getDataLayout()))); | |||
| 7926 | } else | |||
| 7927 | Ops.push_back(OpVal); | |||
| 7928 | } | |||
| 7929 | } | |||
| 7930 | ||||
| 7931 | /// Lower llvm.experimental.stackmap directly to its target opcode. | |||
| 7932 | void SelectionDAGBuilder::visitStackmap(const CallInst &CI) { | |||
| 7933 | // void @llvm.experimental.stackmap(i32 <id>, i32 <numShadowBytes>, | |||
| 7934 | // [live variables...]) | |||
| 7935 | ||||
| 7936 | assert(CI.getType()->isVoidTy() && "Stackmap cannot return a value.")(static_cast <bool> (CI.getType()->isVoidTy() && "Stackmap cannot return a value.") ? void (0) : __assert_fail ("CI.getType()->isVoidTy() && \"Stackmap cannot return a value.\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 7936, __extension__ __PRETTY_FUNCTION__)); | |||
| 7937 | ||||
| 7938 | SDValue Chain, InFlag, Callee, NullPtr; | |||
| 7939 | SmallVector<SDValue, 32> Ops; | |||
| 7940 | ||||
| 7941 | SDLoc DL = getCurSDLoc(); | |||
| 7942 | Callee = getValue(CI.getCalledValue()); | |||
| 7943 | NullPtr = DAG.getIntPtrConstant(0, DL, true); | |||
| 7944 | ||||
| 7945 | // The stackmap intrinsic only records the live variables (the arguemnts | |||
| 7946 | // passed to it) and emits NOPS (if requested). Unlike the patchpoint | |||
| 7947 | // intrinsic, this won't be lowered to a function call. This means we don't | |||
| 7948 | // have to worry about calling conventions and target specific lowering code. | |||
| 7949 | // Instead we perform the call lowering right here. | |||
| 7950 | // | |||
| 7951 | // chain, flag = CALLSEQ_START(chain, 0, 0) | |||
| 7952 | // chain, flag = STACKMAP(id, nbytes, ..., chain, flag) | |||
| 7953 | // chain, flag = CALLSEQ_END(chain, 0, 0, flag) | |||
| 7954 | // | |||
| 7955 | Chain = DAG.getCALLSEQ_START(getRoot(), 0, 0, DL); | |||
| 7956 | InFlag = Chain.getValue(1); | |||
| 7957 | ||||
| 7958 | // Add the <id> and <numBytes> constants. | |||
| 7959 | SDValue IDVal = getValue(CI.getOperand(PatchPointOpers::IDPos)); | |||
| 7960 | Ops.push_back(DAG.getTargetConstant( | |||
| 7961 | cast<ConstantSDNode>(IDVal)->getZExtValue(), DL, MVT::i64)); | |||
| 7962 | SDValue NBytesVal = getValue(CI.getOperand(PatchPointOpers::NBytesPos)); | |||
| 7963 | Ops.push_back(DAG.getTargetConstant( | |||
| 7964 | cast<ConstantSDNode>(NBytesVal)->getZExtValue(), DL, | |||
| 7965 | MVT::i32)); | |||
| 7966 | ||||
| 7967 | // Push live variables for the stack map. | |||
| 7968 | addStackMapLiveVars(&CI, 2, DL, Ops, *this); | |||
| 7969 | ||||
| 7970 | // We are not pushing any register mask info here on the operands list, | |||
| 7971 | // because the stackmap doesn't clobber anything. | |||
| 7972 | ||||
| 7973 | // Push the chain and the glue flag. | |||
| 7974 | Ops.push_back(Chain); | |||
| 7975 | Ops.push_back(InFlag); | |||
| 7976 | ||||
| 7977 | // Create the STACKMAP node. | |||
| 7978 | SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); | |||
| 7979 | SDNode *SM = DAG.getMachineNode(TargetOpcode::STACKMAP, DL, NodeTys, Ops); | |||
| 7980 | Chain = SDValue(SM, 0); | |||
| 7981 | InFlag = Chain.getValue(1); | |||
| 7982 | ||||
| 7983 | Chain = DAG.getCALLSEQ_END(Chain, NullPtr, NullPtr, InFlag, DL); | |||
| 7984 | ||||
| 7985 | // Stackmaps don't generate values, so nothing goes into the NodeMap. | |||
| 7986 | ||||
| 7987 | // Set the root to the target-lowered call chain. | |||
| 7988 | DAG.setRoot(Chain); | |||
| 7989 | ||||
| 7990 | // Inform the Frame Information that we have a stackmap in this function. | |||
| 7991 | FuncInfo.MF->getFrameInfo().setHasStackMap(); | |||
| 7992 | } | |||
| 7993 | ||||
| 7994 | /// Lower llvm.experimental.patchpoint directly to its target opcode. | |||
| 7995 | void SelectionDAGBuilder::visitPatchpoint(ImmutableCallSite CS, | |||
| 7996 | const BasicBlock *EHPadBB) { | |||
| 7997 | // void|i64 @llvm.experimental.patchpoint.void|i64(i64 <id>, | |||
| 7998 | // i32 <numBytes>, | |||
| 7999 | // i8* <target>, | |||
| 8000 | // i32 <numArgs>, | |||
| 8001 | // [Args...], | |||
| 8002 | // [live variables...]) | |||
| 8003 | ||||
| 8004 | CallingConv::ID CC = CS.getCallingConv(); | |||
| 8005 | bool IsAnyRegCC = CC == CallingConv::AnyReg; | |||
| 8006 | bool HasDef = !CS->getType()->isVoidTy(); | |||
| 8007 | SDLoc dl = getCurSDLoc(); | |||
| 8008 | SDValue Callee = getValue(CS->getOperand(PatchPointOpers::TargetPos)); | |||
| 8009 | ||||
| 8010 | // Handle immediate and symbolic callees. | |||
| 8011 | if (auto* ConstCallee = dyn_cast<ConstantSDNode>(Callee)) | |||
| 8012 | Callee = DAG.getIntPtrConstant(ConstCallee->getZExtValue(), dl, | |||
| 8013 | /*isTarget=*/true); | |||
| 8014 | else if (auto* SymbolicCallee = dyn_cast<GlobalAddressSDNode>(Callee)) | |||
| 8015 | Callee = DAG.getTargetGlobalAddress(SymbolicCallee->getGlobal(), | |||
| 8016 | SDLoc(SymbolicCallee), | |||
| 8017 | SymbolicCallee->getValueType(0)); | |||
| 8018 | ||||
| 8019 | // Get the real number of arguments participating in the call <numArgs> | |||
| 8020 | SDValue NArgVal = getValue(CS.getArgument(PatchPointOpers::NArgPos)); | |||
| 8021 | unsigned NumArgs = cast<ConstantSDNode>(NArgVal)->getZExtValue(); | |||
| 8022 | ||||
| 8023 | // Skip the four meta args: <id>, <numNopBytes>, <target>, <numArgs> | |||
| 8024 | // Intrinsics include all meta-operands up to but not including CC. | |||
| 8025 | unsigned NumMetaOpers = PatchPointOpers::CCPos; | |||
| 8026 | assert(CS.arg_size() >= NumMetaOpers + NumArgs &&(static_cast <bool> (CS.arg_size() >= NumMetaOpers + NumArgs && "Not enough arguments provided to the patchpoint intrinsic" ) ? void (0) : __assert_fail ("CS.arg_size() >= NumMetaOpers + NumArgs && \"Not enough arguments provided to the patchpoint intrinsic\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 8027, __extension__ __PRETTY_FUNCTION__)) | |||
| 8027 | "Not enough arguments provided to the patchpoint intrinsic")(static_cast <bool> (CS.arg_size() >= NumMetaOpers + NumArgs && "Not enough arguments provided to the patchpoint intrinsic" ) ? void (0) : __assert_fail ("CS.arg_size() >= NumMetaOpers + NumArgs && \"Not enough arguments provided to the patchpoint intrinsic\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 8027, __extension__ __PRETTY_FUNCTION__)); | |||
| 8028 | ||||
| 8029 | // For AnyRegCC the arguments are lowered later on manually. | |||
| 8030 | unsigned NumCallArgs = IsAnyRegCC ? 0 : NumArgs; | |||
| 8031 | Type *ReturnTy = | |||
| 8032 | IsAnyRegCC ? Type::getVoidTy(*DAG.getContext()) : CS->getType(); | |||
| 8033 | ||||
| 8034 | TargetLowering::CallLoweringInfo CLI(DAG); | |||
| 8035 | populateCallLoweringInfo(CLI, CS, NumMetaOpers, NumCallArgs, Callee, ReturnTy, | |||
| 8036 | true); | |||
| 8037 | std::pair<SDValue, SDValue> Result = lowerInvokable(CLI, EHPadBB); | |||
| 8038 | ||||
| 8039 | SDNode *CallEnd = Result.second.getNode(); | |||
| 8040 | if (HasDef && (CallEnd->getOpcode() == ISD::CopyFromReg)) | |||
| 8041 | CallEnd = CallEnd->getOperand(0).getNode(); | |||
| 8042 | ||||
| 8043 | /// Get a call instruction from the call sequence chain. | |||
| 8044 | /// Tail calls are not allowed. | |||
| 8045 | assert(CallEnd->getOpcode() == ISD::CALLSEQ_END &&(static_cast <bool> (CallEnd->getOpcode() == ISD::CALLSEQ_END && "Expected a callseq node.") ? void (0) : __assert_fail ("CallEnd->getOpcode() == ISD::CALLSEQ_END && \"Expected a callseq node.\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 8046, __extension__ __PRETTY_FUNCTION__)) | |||
| 8046 | "Expected a callseq node.")(static_cast <bool> (CallEnd->getOpcode() == ISD::CALLSEQ_END && "Expected a callseq node.") ? void (0) : __assert_fail ("CallEnd->getOpcode() == ISD::CALLSEQ_END && \"Expected a callseq node.\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 8046, __extension__ __PRETTY_FUNCTION__)); | |||
| 8047 | SDNode *Call = CallEnd->getOperand(0).getNode(); | |||
| 8048 | bool HasGlue = Call->getGluedNode(); | |||
| 8049 | ||||
| 8050 | // Replace the target specific call node with the patchable intrinsic. | |||
| 8051 | SmallVector<SDValue, 8> Ops; | |||
| 8052 | ||||
| 8053 | // Add the <id> and <numBytes> constants. | |||
| 8054 | SDValue IDVal = getValue(CS->getOperand(PatchPointOpers::IDPos)); | |||
| 8055 | Ops.push_back(DAG.getTargetConstant( | |||
| 8056 | cast<ConstantSDNode>(IDVal)->getZExtValue(), dl, MVT::i64)); | |||
| 8057 | SDValue NBytesVal = getValue(CS->getOperand(PatchPointOpers::NBytesPos)); | |||
| 8058 | Ops.push_back(DAG.getTargetConstant( | |||
| 8059 | cast<ConstantSDNode>(NBytesVal)->getZExtValue(), dl, | |||
| 8060 | MVT::i32)); | |||
| 8061 | ||||
| 8062 | // Add the callee. | |||
| 8063 | Ops.push_back(Callee); | |||
| 8064 | ||||
| 8065 | // Adjust <numArgs> to account for any arguments that have been passed on the | |||
| 8066 | // stack instead. | |||
| 8067 | // Call Node: Chain, Target, {Args}, RegMask, [Glue] | |||
| 8068 | unsigned NumCallRegArgs = Call->getNumOperands() - (HasGlue ? 4 : 3); | |||
| 8069 | NumCallRegArgs = IsAnyRegCC ? NumArgs : NumCallRegArgs; | |||
| 8070 | Ops.push_back(DAG.getTargetConstant(NumCallRegArgs, dl, MVT::i32)); | |||
| 8071 | ||||
| 8072 | // Add the calling convention | |||
| 8073 | Ops.push_back(DAG.getTargetConstant((unsigned)CC, dl, MVT::i32)); | |||
| 8074 | ||||
| 8075 | // Add the arguments we omitted previously. The register allocator should | |||
| 8076 | // place these in any free register. | |||
| 8077 | if (IsAnyRegCC) | |||
| 8078 | for (unsigned i = NumMetaOpers, e = NumMetaOpers + NumArgs; i != e; ++i) | |||
| 8079 | Ops.push_back(getValue(CS.getArgument(i))); | |||
| 8080 | ||||
| 8081 | // Push the arguments from the call instruction up to the register mask. | |||
| 8082 | SDNode::op_iterator e = HasGlue ? Call->op_end()-2 : Call->op_end()-1; | |||
| 8083 | Ops.append(Call->op_begin() + 2, e); | |||
| 8084 | ||||
| 8085 | // Push live variables for the stack map. | |||
| 8086 | addStackMapLiveVars(CS, NumMetaOpers + NumArgs, dl, Ops, *this); | |||
| 8087 | ||||
| 8088 | // Push the register mask info. | |||
| 8089 | if (HasGlue) | |||
| 8090 | Ops.push_back(*(Call->op_end()-2)); | |||
| 8091 | else | |||
| 8092 | Ops.push_back(*(Call->op_end()-1)); | |||
| 8093 | ||||
| 8094 | // Push the chain (this is originally the first operand of the call, but | |||
| 8095 | // becomes now the last or second to last operand). | |||
| 8096 | Ops.push_back(*(Call->op_begin())); | |||
| 8097 | ||||
| 8098 | // Push the glue flag (last operand). | |||
| 8099 | if (HasGlue) | |||
| 8100 | Ops.push_back(*(Call->op_end()-1)); | |||
| 8101 | ||||
| 8102 | SDVTList NodeTys; | |||
| 8103 | if (IsAnyRegCC && HasDef) { | |||
| 8104 | // Create the return types based on the intrinsic definition | |||
| 8105 | const TargetLowering &TLI = DAG.getTargetLoweringInfo(); | |||
| 8106 | SmallVector<EVT, 3> ValueVTs; | |||
| 8107 | ComputeValueVTs(TLI, DAG.getDataLayout(), CS->getType(), ValueVTs); | |||
| 8108 | assert(ValueVTs.size() == 1 && "Expected only one return value type.")(static_cast <bool> (ValueVTs.size() == 1 && "Expected only one return value type." ) ? void (0) : __assert_fail ("ValueVTs.size() == 1 && \"Expected only one return value type.\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 8108, __extension__ __PRETTY_FUNCTION__)); | |||
| 8109 | ||||
| 8110 | // There is always a chain and a glue type at the end | |||
| 8111 | ValueVTs.push_back(MVT::Other); | |||
| 8112 | ValueVTs.push_back(MVT::Glue); | |||
| 8113 | NodeTys = DAG.getVTList(ValueVTs); | |||
| 8114 | } else | |||
| 8115 | NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); | |||
| 8116 | ||||
| 8117 | // Replace the target specific call node with a PATCHPOINT node. | |||
| 8118 | MachineSDNode *MN = DAG.getMachineNode(TargetOpcode::PATCHPOINT, | |||
| 8119 | dl, NodeTys, Ops); | |||
| 8120 | ||||
| 8121 | // Update the NodeMap. | |||
| 8122 | if (HasDef) { | |||
| 8123 | if (IsAnyRegCC) | |||
| 8124 | setValue(CS.getInstruction(), SDValue(MN, 0)); | |||
| 8125 | else | |||
| 8126 | setValue(CS.getInstruction(), Result.first); | |||
| 8127 | } | |||
| 8128 | ||||
| 8129 | // Fixup the consumers of the intrinsic. The chain and glue may be used in the | |||
| 8130 | // call sequence. Furthermore the location of the chain and glue can change | |||
| 8131 | // when the AnyReg calling convention is used and the intrinsic returns a | |||
| 8132 | // value. | |||
| 8133 | if (IsAnyRegCC && HasDef) { | |||
| 8134 | SDValue From[] = {SDValue(Call, 0), SDValue(Call, 1)}; | |||
| 8135 | SDValue To[] = {SDValue(MN, 1), SDValue(MN, 2)}; | |||
| 8136 | DAG.ReplaceAllUsesOfValuesWith(From, To, 2); | |||
| 8137 | } else | |||
| 8138 | DAG.ReplaceAllUsesWith(Call, MN); | |||
| 8139 | DAG.DeleteNode(Call); | |||
| 8140 | ||||
| 8141 | // Inform the Frame Information that we have a patchpoint in this function. | |||
| 8142 | FuncInfo.MF->getFrameInfo().setHasPatchPoint(); | |||
| 8143 | } | |||
| 8144 | ||||
| 8145 | void SelectionDAGBuilder::visitVectorReduce(const CallInst &I, | |||
| 8146 | unsigned Intrinsic) { | |||
| 8147 | const TargetLowering &TLI = DAG.getTargetLoweringInfo(); | |||
| 8148 | SDValue Op1 = getValue(I.getArgOperand(0)); | |||
| 8149 | SDValue Op2; | |||
| 8150 | if (I.getNumArgOperands() > 1) | |||
| 8151 | Op2 = getValue(I.getArgOperand(1)); | |||
| 8152 | SDLoc dl = getCurSDLoc(); | |||
| 8153 | EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType()); | |||
| 8154 | SDValue Res; | |||
| 8155 | FastMathFlags FMF; | |||
| 8156 | if (isa<FPMathOperator>(I)) | |||
| 8157 | FMF = I.getFastMathFlags(); | |||
| 8158 | ||||
| 8159 | switch (Intrinsic) { | |||
| 8160 | case Intrinsic::experimental_vector_reduce_fadd: | |||
| 8161 | if (FMF.isFast()) | |||
| 8162 | Res = DAG.getNode(ISD::VECREDUCE_FADD, dl, VT, Op2); | |||
| 8163 | else | |||
| 8164 | Res = DAG.getNode(ISD::VECREDUCE_STRICT_FADD, dl, VT, Op1, Op2); | |||
| 8165 | break; | |||
| 8166 | case Intrinsic::experimental_vector_reduce_fmul: | |||
| 8167 | if (FMF.isFast()) | |||
| 8168 | Res = DAG.getNode(ISD::VECREDUCE_FMUL, dl, VT, Op2); | |||
| 8169 | else | |||
| 8170 | Res = DAG.getNode(ISD::VECREDUCE_STRICT_FMUL, dl, VT, Op1, Op2); | |||
| 8171 | break; | |||
| 8172 | case Intrinsic::experimental_vector_reduce_add: | |||
| 8173 | Res = DAG.getNode(ISD::VECREDUCE_ADD, dl, VT, Op1); | |||
| 8174 | break; | |||
| 8175 | case Intrinsic::experimental_vector_reduce_mul: | |||
| 8176 | Res = DAG.getNode(ISD::VECREDUCE_MUL, dl, VT, Op1); | |||
| 8177 | break; | |||
| 8178 | case Intrinsic::experimental_vector_reduce_and: | |||
| 8179 | Res = DAG.getNode(ISD::VECREDUCE_AND, dl, VT, Op1); | |||
| 8180 | break; | |||
| 8181 | case Intrinsic::experimental_vector_reduce_or: | |||
| 8182 | Res = DAG.getNode(ISD::VECREDUCE_OR, dl, VT, Op1); | |||
| 8183 | break; | |||
| 8184 | case Intrinsic::experimental_vector_reduce_xor: | |||
| 8185 | Res = DAG.getNode(ISD::VECREDUCE_XOR, dl, VT, Op1); | |||
| 8186 | break; | |||
| 8187 | case Intrinsic::experimental_vector_reduce_smax: | |||
| 8188 | Res = DAG.getNode(ISD::VECREDUCE_SMAX, dl, VT, Op1); | |||
| 8189 | break; | |||
| 8190 | case Intrinsic::experimental_vector_reduce_smin: | |||
| 8191 | Res = DAG.getNode(ISD::VECREDUCE_SMIN, dl, VT, Op1); | |||
| 8192 | break; | |||
| 8193 | case Intrinsic::experimental_vector_reduce_umax: | |||
| 8194 | Res = DAG.getNode(ISD::VECREDUCE_UMAX, dl, VT, Op1); | |||
| 8195 | break; | |||
| 8196 | case Intrinsic::experimental_vector_reduce_umin: | |||
| 8197 | Res = DAG.getNode(ISD::VECREDUCE_UMIN, dl, VT, Op1); | |||
| 8198 | break; | |||
| 8199 | case Intrinsic::experimental_vector_reduce_fmax: | |||
| 8200 | Res = DAG.getNode(ISD::VECREDUCE_FMAX, dl, VT, Op1); | |||
| 8201 | break; | |||
| 8202 | case Intrinsic::experimental_vector_reduce_fmin: | |||
| 8203 | Res = DAG.getNode(ISD::VECREDUCE_FMIN, dl, VT, Op1); | |||
| 8204 | break; | |||
| 8205 | default: | |||
| 8206 | llvm_unreachable("Unhandled vector reduce intrinsic")::llvm::llvm_unreachable_internal("Unhandled vector reduce intrinsic" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 8206); | |||
| 8207 | } | |||
| 8208 | setValue(&I, Res); | |||
| 8209 | } | |||
| 8210 | ||||
| 8211 | /// Returns an AttributeList representing the attributes applied to the return | |||
| 8212 | /// value of the given call. | |||
| 8213 | static AttributeList getReturnAttrs(TargetLowering::CallLoweringInfo &CLI) { | |||
| 8214 | SmallVector<Attribute::AttrKind, 2> Attrs; | |||
| 8215 | if (CLI.RetSExt) | |||
| 8216 | Attrs.push_back(Attribute::SExt); | |||
| 8217 | if (CLI.RetZExt) | |||
| 8218 | Attrs.push_back(Attribute::ZExt); | |||
| 8219 | if (CLI.IsInReg) | |||
| 8220 | Attrs.push_back(Attribute::InReg); | |||
| 8221 | ||||
| 8222 | return AttributeList::get(CLI.RetTy->getContext(), AttributeList::ReturnIndex, | |||
| 8223 | Attrs); | |||
| 8224 | } | |||
| 8225 | ||||
| 8226 | /// TargetLowering::LowerCallTo - This is the default LowerCallTo | |||
| 8227 | /// implementation, which just calls LowerCall. | |||
| 8228 | /// FIXME: When all targets are | |||
| 8229 | /// migrated to using LowerCall, this hook should be integrated into SDISel. | |||
| 8230 | std::pair<SDValue, SDValue> | |||
| 8231 | TargetLowering::LowerCallTo(TargetLowering::CallLoweringInfo &CLI) const { | |||
| 8232 | // Handle the incoming return values from the call. | |||
| 8233 | CLI.Ins.clear(); | |||
| 8234 | Type *OrigRetTy = CLI.RetTy; | |||
| 8235 | SmallVector<EVT, 4> RetTys; | |||
| 8236 | SmallVector<uint64_t, 4> Offsets; | |||
| 8237 | auto &DL = CLI.DAG.getDataLayout(); | |||
| 8238 | ComputeValueVTs(*this, DL, CLI.RetTy, RetTys, &Offsets); | |||
| 8239 | ||||
| 8240 | if (CLI.IsPostTypeLegalization) { | |||
| 8241 | // If we are lowering a libcall after legalization, split the return type. | |||
| 8242 | SmallVector<EVT, 4> OldRetTys = std::move(RetTys); | |||
| 8243 | SmallVector<uint64_t, 4> OldOffsets = std::move(Offsets); | |||
| 8244 | for (size_t i = 0, e = OldRetTys.size(); i != e; ++i) { | |||
| 8245 | EVT RetVT = OldRetTys[i]; | |||
| 8246 | uint64_t Offset = OldOffsets[i]; | |||
| 8247 | MVT RegisterVT = getRegisterType(CLI.RetTy->getContext(), RetVT); | |||
| 8248 | unsigned NumRegs = getNumRegisters(CLI.RetTy->getContext(), RetVT); | |||
| 8249 | unsigned RegisterVTByteSZ = RegisterVT.getSizeInBits() / 8; | |||
| 8250 | RetTys.append(NumRegs, RegisterVT); | |||
| 8251 | for (unsigned j = 0; j != NumRegs; ++j) | |||
| 8252 | Offsets.push_back(Offset + j * RegisterVTByteSZ); | |||
| 8253 | } | |||
| 8254 | } | |||
| 8255 | ||||
| 8256 | SmallVector<ISD::OutputArg, 4> Outs; | |||
| 8257 | GetReturnInfo(CLI.RetTy, getReturnAttrs(CLI), Outs, *this, DL); | |||
| 8258 | ||||
| 8259 | bool CanLowerReturn = | |||
| 8260 | this->CanLowerReturn(CLI.CallConv, CLI.DAG.getMachineFunction(), | |||
| 8261 | CLI.IsVarArg, Outs, CLI.RetTy->getContext()); | |||
| 8262 | ||||
| 8263 | SDValue DemoteStackSlot; | |||
| 8264 | int DemoteStackIdx = -100; | |||
| 8265 | if (!CanLowerReturn) { | |||
| 8266 | // FIXME: equivalent assert? | |||
| 8267 | // assert(!CS.hasInAllocaArgument() && | |||
| 8268 | // "sret demotion is incompatible with inalloca"); | |||
| 8269 | uint64_t TySize = DL.getTypeAllocSize(CLI.RetTy); | |||
| 8270 | unsigned Align = DL.getPrefTypeAlignment(CLI.RetTy); | |||
| 8271 | MachineFunction &MF = CLI.DAG.getMachineFunction(); | |||
| 8272 | DemoteStackIdx = MF.getFrameInfo().CreateStackObject(TySize, Align, false); | |||
| 8273 | Type *StackSlotPtrType = PointerType::getUnqual(CLI.RetTy); | |||
| 8274 | ||||
| 8275 | DemoteStackSlot = CLI.DAG.getFrameIndex(DemoteStackIdx, getFrameIndexTy(DL)); | |||
| 8276 | ArgListEntry Entry; | |||
| 8277 | Entry.Node = DemoteStackSlot; | |||
| 8278 | Entry.Ty = StackSlotPtrType; | |||
| 8279 | Entry.IsSExt = false; | |||
| 8280 | Entry.IsZExt = false; | |||
| 8281 | Entry.IsInReg = false; | |||
| 8282 | Entry.IsSRet = true; | |||
| 8283 | Entry.IsNest = false; | |||
| 8284 | Entry.IsByVal = false; | |||
| 8285 | Entry.IsReturned = false; | |||
| 8286 | Entry.IsSwiftSelf = false; | |||
| 8287 | Entry.IsSwiftError = false; | |||
| 8288 | Entry.Alignment = Align; | |||
| 8289 | CLI.getArgs().insert(CLI.getArgs().begin(), Entry); | |||
| 8290 | CLI.NumFixedArgs += 1; | |||
| 8291 | CLI.RetTy = Type::getVoidTy(CLI.RetTy->getContext()); | |||
| 8292 | ||||
| 8293 | // sret demotion isn't compatible with tail-calls, since the sret argument | |||
| 8294 | // points into the callers stack frame. | |||
| 8295 | CLI.IsTailCall = false; | |||
| 8296 | } else { | |||
| 8297 | for (unsigned I = 0, E = RetTys.size(); I != E; ++I) { | |||
| 8298 | EVT VT = RetTys[I]; | |||
| 8299 | MVT RegisterVT = | |||
| 8300 | getRegisterTypeForCallingConv(CLI.RetTy->getContext(), VT); | |||
| 8301 | unsigned NumRegs = | |||
| 8302 | getNumRegistersForCallingConv(CLI.RetTy->getContext(), VT); | |||
| 8303 | for (unsigned i = 0; i != NumRegs; ++i) { | |||
| 8304 | ISD::InputArg MyFlags; | |||
| 8305 | MyFlags.VT = RegisterVT; | |||
| 8306 | MyFlags.ArgVT = VT; | |||
| 8307 | MyFlags.Used = CLI.IsReturnValueUsed; | |||
| 8308 | if (CLI.RetSExt) | |||
| 8309 | MyFlags.Flags.setSExt(); | |||
| 8310 | if (CLI.RetZExt) | |||
| 8311 | MyFlags.Flags.setZExt(); | |||
| 8312 | if (CLI.IsInReg) | |||
| 8313 | MyFlags.Flags.setInReg(); | |||
| 8314 | CLI.Ins.push_back(MyFlags); | |||
| 8315 | } | |||
| 8316 | } | |||
| 8317 | } | |||
| 8318 | ||||
| 8319 | // We push in swifterror return as the last element of CLI.Ins. | |||
| 8320 | ArgListTy &Args = CLI.getArgs(); | |||
| 8321 | if (supportSwiftError()) { | |||
| 8322 | for (unsigned i = 0, e = Args.size(); i != e; ++i) { | |||
| 8323 | if (Args[i].IsSwiftError) { | |||
| 8324 | ISD::InputArg MyFlags; | |||
| 8325 | MyFlags.VT = getPointerTy(DL); | |||
| 8326 | MyFlags.ArgVT = EVT(getPointerTy(DL)); | |||
| 8327 | MyFlags.Flags.setSwiftError(); | |||
| 8328 | CLI.Ins.push_back(MyFlags); | |||
| 8329 | } | |||
| 8330 | } | |||
| 8331 | } | |||
| 8332 | ||||
| 8333 | // Handle all of the outgoing arguments. | |||
| 8334 | CLI.Outs.clear(); | |||
| 8335 | CLI.OutVals.clear(); | |||
| 8336 | for (unsigned i = 0, e = Args.size(); i != e; ++i) { | |||
| 8337 | SmallVector<EVT, 4> ValueVTs; | |||
| 8338 | ComputeValueVTs(*this, DL, Args[i].Ty, ValueVTs); | |||
| 8339 | // FIXME: Split arguments if CLI.IsPostTypeLegalization | |||
| 8340 | Type *FinalType = Args[i].Ty; | |||
| 8341 | if (Args[i].IsByVal) | |||
| 8342 | FinalType = cast<PointerType>(Args[i].Ty)->getElementType(); | |||
| 8343 | bool NeedsRegBlock = functionArgumentNeedsConsecutiveRegisters( | |||
| 8344 | FinalType, CLI.CallConv, CLI.IsVarArg); | |||
| 8345 | for (unsigned Value = 0, NumValues = ValueVTs.size(); Value != NumValues; | |||
| 8346 | ++Value) { | |||
| 8347 | EVT VT = ValueVTs[Value]; | |||
| 8348 | Type *ArgTy = VT.getTypeForEVT(CLI.RetTy->getContext()); | |||
| 8349 | SDValue Op = SDValue(Args[i].Node.getNode(), | |||
| 8350 | Args[i].Node.getResNo() + Value); | |||
| 8351 | ISD::ArgFlagsTy Flags; | |||
| 8352 | ||||
| 8353 | // Certain targets (such as MIPS), may have a different ABI alignment | |||
| 8354 | // for a type depending on the context. Give the target a chance to | |||
| 8355 | // specify the alignment it wants. | |||
| 8356 | unsigned OriginalAlignment = getABIAlignmentForCallingConv(ArgTy, DL); | |||
| 8357 | ||||
| 8358 | if (Args[i].IsZExt) | |||
| 8359 | Flags.setZExt(); | |||
| 8360 | if (Args[i].IsSExt) | |||
| 8361 | Flags.setSExt(); | |||
| 8362 | if (Args[i].IsInReg) { | |||
| 8363 | // If we are using vectorcall calling convention, a structure that is | |||
| 8364 | // passed InReg - is surely an HVA | |||
| 8365 | if (CLI.CallConv == CallingConv::X86_VectorCall && | |||
| 8366 | isa<StructType>(FinalType)) { | |||
| 8367 | // The first value of a structure is marked | |||
| 8368 | if (0 == Value) | |||
| 8369 | Flags.setHvaStart(); | |||
| 8370 | Flags.setHva(); | |||
| 8371 | } | |||
| 8372 | // Set InReg Flag | |||
| 8373 | Flags.setInReg(); | |||
| 8374 | } | |||
| 8375 | if (Args[i].IsSRet) | |||
| 8376 | Flags.setSRet(); | |||
| 8377 | if (Args[i].IsSwiftSelf) | |||
| 8378 | Flags.setSwiftSelf(); | |||
| 8379 | if (Args[i].IsSwiftError) | |||
| 8380 | Flags.setSwiftError(); | |||
| 8381 | if (Args[i].IsByVal) | |||
| 8382 | Flags.setByVal(); | |||
| 8383 | if (Args[i].IsInAlloca) { | |||
| 8384 | Flags.setInAlloca(); | |||
| 8385 | // Set the byval flag for CCAssignFn callbacks that don't know about | |||
| 8386 | // inalloca. This way we can know how many bytes we should've allocated | |||
| 8387 | // and how many bytes a callee cleanup function will pop. If we port | |||
| 8388 | // inalloca to more targets, we'll have to add custom inalloca handling | |||
| 8389 | // in the various CC lowering callbacks. | |||
| 8390 | Flags.setByVal(); | |||
| 8391 | } | |||
| 8392 | if (Args[i].IsByVal || Args[i].IsInAlloca) { | |||
| 8393 | PointerType *Ty = cast<PointerType>(Args[i].Ty); | |||
| 8394 | Type *ElementTy = Ty->getElementType(); | |||
| 8395 | Flags.setByValSize(DL.getTypeAllocSize(ElementTy)); | |||
| 8396 | // For ByVal, alignment should come from FE. BE will guess if this | |||
| 8397 | // info is not there but there are cases it cannot get right. | |||
| 8398 | unsigned FrameAlign; | |||
| 8399 | if (Args[i].Alignment) | |||
| 8400 | FrameAlign = Args[i].Alignment; | |||
| 8401 | else | |||
| 8402 | FrameAlign = getByValTypeAlignment(ElementTy, DL); | |||
| 8403 | Flags.setByValAlign(FrameAlign); | |||
| 8404 | } | |||
| 8405 | if (Args[i].IsNest) | |||
| 8406 | Flags.setNest(); | |||
| 8407 | if (NeedsRegBlock) | |||
| 8408 | Flags.setInConsecutiveRegs(); | |||
| 8409 | Flags.setOrigAlign(OriginalAlignment); | |||
| 8410 | ||||
| 8411 | MVT PartVT = getRegisterTypeForCallingConv(CLI.RetTy->getContext(), VT); | |||
| 8412 | unsigned NumParts = | |||
| 8413 | getNumRegistersForCallingConv(CLI.RetTy->getContext(), VT); | |||
| 8414 | SmallVector<SDValue, 4> Parts(NumParts); | |||
| 8415 | ISD::NodeType ExtendKind = ISD::ANY_EXTEND; | |||
| 8416 | ||||
| 8417 | if (Args[i].IsSExt) | |||
| 8418 | ExtendKind = ISD::SIGN_EXTEND; | |||
| 8419 | else if (Args[i].IsZExt) | |||
| 8420 | ExtendKind = ISD::ZERO_EXTEND; | |||
| 8421 | ||||
| 8422 | // Conservatively only handle 'returned' on non-vectors that can be lowered, | |||
| 8423 | // for now. | |||
| 8424 | if (Args[i].IsReturned && !Op.getValueType().isVector() && | |||
| 8425 | CanLowerReturn) { | |||
| 8426 | assert(CLI.RetTy == Args[i].Ty && RetTys.size() == NumValues &&(static_cast <bool> (CLI.RetTy == Args[i].Ty && RetTys.size() == NumValues && "unexpected use of 'returned'" ) ? void (0) : __assert_fail ("CLI.RetTy == Args[i].Ty && RetTys.size() == NumValues && \"unexpected use of 'returned'\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 8427, __extension__ __PRETTY_FUNCTION__)) | |||
| 8427 | "unexpected use of 'returned'")(static_cast <bool> (CLI.RetTy == Args[i].Ty && RetTys.size() == NumValues && "unexpected use of 'returned'" ) ? void (0) : __assert_fail ("CLI.RetTy == Args[i].Ty && RetTys.size() == NumValues && \"unexpected use of 'returned'\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 8427, __extension__ __PRETTY_FUNCTION__)); | |||
| 8428 | // Before passing 'returned' to the target lowering code, ensure that | |||
| 8429 | // either the register MVT and the actual EVT are the same size or that | |||
| 8430 | // the return value and argument are extended in the same way; in these | |||
| 8431 | // cases it's safe to pass the argument register value unchanged as the | |||
| 8432 | // return register value (although it's at the target's option whether | |||
| 8433 | // to do so) | |||
| 8434 | // TODO: allow code generation to take advantage of partially preserved | |||
| 8435 | // registers rather than clobbering the entire register when the | |||
| 8436 | // parameter extension method is not compatible with the return | |||
| 8437 | // extension method | |||
| 8438 | if ((NumParts * PartVT.getSizeInBits() == VT.getSizeInBits()) || | |||
| 8439 | (ExtendKind != ISD::ANY_EXTEND && CLI.RetSExt == Args[i].IsSExt && | |||
| 8440 | CLI.RetZExt == Args[i].IsZExt)) | |||
| 8441 | Flags.setReturned(); | |||
| 8442 | } | |||
| 8443 | ||||
| 8444 | getCopyToParts(CLI.DAG, CLI.DL, Op, &Parts[0], NumParts, PartVT, | |||
| 8445 | CLI.CS.getInstruction(), ExtendKind, true); | |||
| 8446 | ||||
| 8447 | for (unsigned j = 0; j != NumParts; ++j) { | |||
| 8448 | // if it isn't first piece, alignment must be 1 | |||
| 8449 | ISD::OutputArg MyFlags(Flags, Parts[j].getValueType(), VT, | |||
| 8450 | i < CLI.NumFixedArgs, | |||
| 8451 | i, j*Parts[j].getValueType().getStoreSize()); | |||
| 8452 | if (NumParts > 1 && j == 0) | |||
| 8453 | MyFlags.Flags.setSplit(); | |||
| 8454 | else if (j != 0) { | |||
| 8455 | MyFlags.Flags.setOrigAlign(1); | |||
| 8456 | if (j == NumParts - 1) | |||
| 8457 | MyFlags.Flags.setSplitEnd(); | |||
| 8458 | } | |||
| 8459 | ||||
| 8460 | CLI.Outs.push_back(MyFlags); | |||
| 8461 | CLI.OutVals.push_back(Parts[j]); | |||
| 8462 | } | |||
| 8463 | ||||
| 8464 | if (NeedsRegBlock && Value == NumValues - 1) | |||
| 8465 | CLI.Outs[CLI.Outs.size() - 1].Flags.setInConsecutiveRegsLast(); | |||
| 8466 | } | |||
| 8467 | } | |||
| 8468 | ||||
| 8469 | SmallVector<SDValue, 4> InVals; | |||
| 8470 | CLI.Chain = LowerCall(CLI, InVals); | |||
| 8471 | ||||
| 8472 | // Update CLI.InVals to use outside of this function. | |||
| 8473 | CLI.InVals = InVals; | |||
| 8474 | ||||
| 8475 | // Verify that the target's LowerCall behaved as expected. | |||
| 8476 | assert(CLI.Chain.getNode() && CLI.Chain.getValueType() == MVT::Other &&(static_cast <bool> (CLI.Chain.getNode() && CLI .Chain.getValueType() == MVT::Other && "LowerCall didn't return a valid chain!" ) ? void (0) : __assert_fail ("CLI.Chain.getNode() && CLI.Chain.getValueType() == MVT::Other && \"LowerCall didn't return a valid chain!\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 8477, __extension__ __PRETTY_FUNCTION__)) | |||
| 8477 | "LowerCall didn't return a valid chain!")(static_cast <bool> (CLI.Chain.getNode() && CLI .Chain.getValueType() == MVT::Other && "LowerCall didn't return a valid chain!" ) ? void (0) : __assert_fail ("CLI.Chain.getNode() && CLI.Chain.getValueType() == MVT::Other && \"LowerCall didn't return a valid chain!\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 8477, __extension__ __PRETTY_FUNCTION__)); | |||
| 8478 | assert((!CLI.IsTailCall || InVals.empty()) &&(static_cast <bool> ((!CLI.IsTailCall || InVals.empty() ) && "LowerCall emitted a return value for a tail call!" ) ? void (0) : __assert_fail ("(!CLI.IsTailCall || InVals.empty()) && \"LowerCall emitted a return value for a tail call!\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 8479, __extension__ __PRETTY_FUNCTION__)) | |||
| 8479 | "LowerCall emitted a return value for a tail call!")(static_cast <bool> ((!CLI.IsTailCall || InVals.empty() ) && "LowerCall emitted a return value for a tail call!" ) ? void (0) : __assert_fail ("(!CLI.IsTailCall || InVals.empty()) && \"LowerCall emitted a return value for a tail call!\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 8479, __extension__ __PRETTY_FUNCTION__)); | |||
| 8480 | assert((CLI.IsTailCall || InVals.size() == CLI.Ins.size()) &&(static_cast <bool> ((CLI.IsTailCall || InVals.size() == CLI.Ins.size()) && "LowerCall didn't emit the correct number of values!" ) ? void (0) : __assert_fail ("(CLI.IsTailCall || InVals.size() == CLI.Ins.size()) && \"LowerCall didn't emit the correct number of values!\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 8481, __extension__ __PRETTY_FUNCTION__)) | |||
| 8481 | "LowerCall didn't emit the correct number of values!")(static_cast <bool> ((CLI.IsTailCall || InVals.size() == CLI.Ins.size()) && "LowerCall didn't emit the correct number of values!" ) ? void (0) : __assert_fail ("(CLI.IsTailCall || InVals.size() == CLI.Ins.size()) && \"LowerCall didn't emit the correct number of values!\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 8481, __extension__ __PRETTY_FUNCTION__)); | |||
| 8482 | ||||
| 8483 | // For a tail call, the return value is merely live-out and there aren't | |||
| 8484 | // any nodes in the DAG representing it. Return a special value to | |||
| 8485 | // indicate that a tail call has been emitted and no more Instructions | |||
| 8486 | // should be processed in the current block. | |||
| 8487 | if (CLI.IsTailCall) { | |||
| 8488 | CLI.DAG.setRoot(CLI.Chain); | |||
| 8489 | return std::make_pair(SDValue(), SDValue()); | |||
| 8490 | } | |||
| 8491 | ||||
| 8492 | #ifndef NDEBUG | |||
| 8493 | for (unsigned i = 0, e = CLI.Ins.size(); i != e; ++i) { | |||
| 8494 | assert(InVals[i].getNode() && "LowerCall emitted a null value!")(static_cast <bool> (InVals[i].getNode() && "LowerCall emitted a null value!" ) ? void (0) : __assert_fail ("InVals[i].getNode() && \"LowerCall emitted a null value!\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 8494, __extension__ __PRETTY_FUNCTION__)); | |||
| 8495 | assert(EVT(CLI.Ins[i].VT) == InVals[i].getValueType() &&(static_cast <bool> (EVT(CLI.Ins[i].VT) == InVals[i].getValueType () && "LowerCall emitted a value with the wrong type!" ) ? void (0) : __assert_fail ("EVT(CLI.Ins[i].VT) == InVals[i].getValueType() && \"LowerCall emitted a value with the wrong type!\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 8496, __extension__ __PRETTY_FUNCTION__)) | |||
| 8496 | "LowerCall emitted a value with the wrong type!")(static_cast <bool> (EVT(CLI.Ins[i].VT) == InVals[i].getValueType () && "LowerCall emitted a value with the wrong type!" ) ? void (0) : __assert_fail ("EVT(CLI.Ins[i].VT) == InVals[i].getValueType() && \"LowerCall emitted a value with the wrong type!\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 8496, __extension__ __PRETTY_FUNCTION__)); | |||
| 8497 | } | |||
| 8498 | #endif | |||
| 8499 | ||||
| 8500 | SmallVector<SDValue, 4> ReturnValues; | |||
| 8501 | if (!CanLowerReturn) { | |||
| 8502 | // The instruction result is the result of loading from the | |||
| 8503 | // hidden sret parameter. | |||
| 8504 | SmallVector<EVT, 1> PVTs; | |||
| 8505 | Type *PtrRetTy = OrigRetTy->getPointerTo(DL.getAllocaAddrSpace()); | |||
| 8506 | ||||
| 8507 | ComputeValueVTs(*this, DL, PtrRetTy, PVTs); | |||
| 8508 | assert(PVTs.size() == 1 && "Pointers should fit in one register")(static_cast <bool> (PVTs.size() == 1 && "Pointers should fit in one register" ) ? void (0) : __assert_fail ("PVTs.size() == 1 && \"Pointers should fit in one register\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 8508, __extension__ __PRETTY_FUNCTION__)); | |||
| 8509 | EVT PtrVT = PVTs[0]; | |||
| 8510 | ||||
| 8511 | unsigned NumValues = RetTys.size(); | |||
| 8512 | ReturnValues.resize(NumValues); | |||
| 8513 | SmallVector<SDValue, 4> Chains(NumValues); | |||
| 8514 | ||||
| 8515 | // An aggregate return value cannot wrap around the address space, so | |||
| 8516 | // offsets to its parts don't wrap either. | |||
| 8517 | SDNodeFlags Flags; | |||
| 8518 | Flags.setNoUnsignedWrap(true); | |||
| 8519 | ||||
| 8520 | for (unsigned i = 0; i < NumValues; ++i) { | |||
| 8521 | SDValue Add = CLI.DAG.getNode(ISD::ADD, CLI.DL, PtrVT, DemoteStackSlot, | |||
| 8522 | CLI.DAG.getConstant(Offsets[i], CLI.DL, | |||
| 8523 | PtrVT), Flags); | |||
| 8524 | SDValue L = CLI.DAG.getLoad( | |||
| 8525 | RetTys[i], CLI.DL, CLI.Chain, Add, | |||
| 8526 | MachinePointerInfo::getFixedStack(CLI.DAG.getMachineFunction(), | |||
| 8527 | DemoteStackIdx, Offsets[i]), | |||
| 8528 | /* Alignment = */ 1); | |||
| 8529 | ReturnValues[i] = L; | |||
| 8530 | Chains[i] = L.getValue(1); | |||
| 8531 | } | |||
| 8532 | ||||
| 8533 | CLI.Chain = CLI.DAG.getNode(ISD::TokenFactor, CLI.DL, MVT::Other, Chains); | |||
| 8534 | } else { | |||
| 8535 | // Collect the legal value parts into potentially illegal values | |||
| 8536 | // that correspond to the original function's return values. | |||
| 8537 | Optional<ISD::NodeType> AssertOp; | |||
| 8538 | if (CLI.RetSExt) | |||
| 8539 | AssertOp = ISD::AssertSext; | |||
| 8540 | else if (CLI.RetZExt) | |||
| 8541 | AssertOp = ISD::AssertZext; | |||
| 8542 | unsigned CurReg = 0; | |||
| 8543 | for (unsigned I = 0, E = RetTys.size(); I != E; ++I) { | |||
| 8544 | EVT VT = RetTys[I]; | |||
| 8545 | MVT RegisterVT = | |||
| 8546 | getRegisterTypeForCallingConv(CLI.RetTy->getContext(), VT); | |||
| 8547 | unsigned NumRegs = | |||
| 8548 | getNumRegistersForCallingConv(CLI.RetTy->getContext(), VT); | |||
| 8549 | ||||
| 8550 | ReturnValues.push_back(getCopyFromParts(CLI.DAG, CLI.DL, &InVals[CurReg], | |||
| 8551 | NumRegs, RegisterVT, VT, nullptr, | |||
| 8552 | AssertOp, true)); | |||
| 8553 | CurReg += NumRegs; | |||
| 8554 | } | |||
| 8555 | ||||
| 8556 | // For a function returning void, there is no return value. We can't create | |||
| 8557 | // such a node, so we just return a null return value in that case. In | |||
| 8558 | // that case, nothing will actually look at the value. | |||
| 8559 | if (ReturnValues.empty()) | |||
| 8560 | return std::make_pair(SDValue(), CLI.Chain); | |||
| 8561 | } | |||
| 8562 | ||||
| 8563 | SDValue Res = CLI.DAG.getNode(ISD::MERGE_VALUES, CLI.DL, | |||
| 8564 | CLI.DAG.getVTList(RetTys), ReturnValues); | |||
| 8565 | return std::make_pair(Res, CLI.Chain); | |||
| 8566 | } | |||
| 8567 | ||||
| 8568 | void TargetLowering::LowerOperationWrapper(SDNode *N, | |||
| 8569 | SmallVectorImpl<SDValue> &Results, | |||
| 8570 | SelectionDAG &DAG) const { | |||
| 8571 | if (SDValue Res = LowerOperation(SDValue(N, 0), DAG)) | |||
| 8572 | Results.push_back(Res); | |||
| 8573 | } | |||
| 8574 | ||||
| 8575 | SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { | |||
| 8576 | llvm_unreachable("LowerOperation not implemented for this target!")::llvm::llvm_unreachable_internal("LowerOperation not implemented for this target!" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 8576); | |||
| 8577 | } | |||
| 8578 | ||||
| 8579 | void | |||
| 8580 | SelectionDAGBuilder::CopyValueToVirtualRegister(const Value *V, unsigned Reg) { | |||
| 8581 | SDValue Op = getNonRegisterValue(V); | |||
| 8582 | assert((Op.getOpcode() != ISD::CopyFromReg ||(static_cast <bool> ((Op.getOpcode() != ISD::CopyFromReg || cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) && "Copy from a reg to the same reg!") ? void (0) : __assert_fail ("(Op.getOpcode() != ISD::CopyFromReg || cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) && \"Copy from a reg to the same reg!\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 8584, __extension__ __PRETTY_FUNCTION__)) | |||
| 8583 | cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&(static_cast <bool> ((Op.getOpcode() != ISD::CopyFromReg || cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) && "Copy from a reg to the same reg!") ? void (0) : __assert_fail ("(Op.getOpcode() != ISD::CopyFromReg || cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) && \"Copy from a reg to the same reg!\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 8584, __extension__ __PRETTY_FUNCTION__)) | |||
| 8584 | "Copy from a reg to the same reg!")(static_cast <bool> ((Op.getOpcode() != ISD::CopyFromReg || cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) && "Copy from a reg to the same reg!") ? void (0) : __assert_fail ("(Op.getOpcode() != ISD::CopyFromReg || cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) && \"Copy from a reg to the same reg!\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 8584, __extension__ __PRETTY_FUNCTION__)); | |||
| 8585 | assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg")(static_cast <bool> (!TargetRegisterInfo::isPhysicalRegister (Reg) && "Is a physreg") ? void (0) : __assert_fail ( "!TargetRegisterInfo::isPhysicalRegister(Reg) && \"Is a physreg\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 8585, __extension__ __PRETTY_FUNCTION__)); | |||
| 8586 | ||||
| 8587 | const TargetLowering &TLI = DAG.getTargetLoweringInfo(); | |||
| 8588 | // If this is an InlineAsm we have to match the registers required, not the | |||
| 8589 | // notional registers required by the type. | |||
| 8590 | ||||
| 8591 | RegsForValue RFV(V->getContext(), TLI, DAG.getDataLayout(), Reg, | |||
| 8592 | V->getType(), isABIRegCopy(V)); | |||
| 8593 | SDValue Chain = DAG.getEntryNode(); | |||
| 8594 | ||||
| 8595 | ISD::NodeType ExtendType = (FuncInfo.PreferredExtendType.find(V) == | |||
| 8596 | FuncInfo.PreferredExtendType.end()) | |||
| 8597 | ? ISD::ANY_EXTEND | |||
| 8598 | : FuncInfo.PreferredExtendType[V]; | |||
| 8599 | RFV.getCopyToRegs(Op, DAG, getCurSDLoc(), Chain, nullptr, V, ExtendType); | |||
| 8600 | PendingExports.push_back(Chain); | |||
| 8601 | } | |||
| 8602 | ||||
| 8603 | #include "llvm/CodeGen/SelectionDAGISel.h" | |||
| 8604 | ||||
| 8605 | /// isOnlyUsedInEntryBlock - If the specified argument is only used in the | |||
| 8606 | /// entry block, return true. This includes arguments used by switches, since | |||
| 8607 | /// the switch may expand into multiple basic blocks. | |||
| 8608 | static bool isOnlyUsedInEntryBlock(const Argument *A, bool FastISel) { | |||
| 8609 | // With FastISel active, we may be splitting blocks, so force creation | |||
| 8610 | // of virtual registers for all non-dead arguments. | |||
| 8611 | if (FastISel) | |||
| 8612 | return A->use_empty(); | |||
| 8613 | ||||
| 8614 | const BasicBlock &Entry = A->getParent()->front(); | |||
| 8615 | for (const User *U : A->users()) | |||
| 8616 | if (cast<Instruction>(U)->getParent() != &Entry || isa<SwitchInst>(U)) | |||
| 8617 | return false; // Use not in entry block. | |||
| 8618 | ||||
| 8619 | return true; | |||
| 8620 | } | |||
| 8621 | ||||
| 8622 | using ArgCopyElisionMapTy = | |||
| 8623 | DenseMap<const Argument *, | |||
| 8624 | std::pair<const AllocaInst *, const StoreInst *>>; | |||
| 8625 | ||||
| 8626 | /// Scan the entry block of the function in FuncInfo for arguments that look | |||
| 8627 | /// like copies into a local alloca. Record any copied arguments in | |||
| 8628 | /// ArgCopyElisionCandidates. | |||
| 8629 | static void | |||
| 8630 | findArgumentCopyElisionCandidates(const DataLayout &DL, | |||
| 8631 | FunctionLoweringInfo *FuncInfo, | |||
| 8632 | ArgCopyElisionMapTy &ArgCopyElisionCandidates) { | |||
| 8633 | // Record the state of every static alloca used in the entry block. Argument | |||
| 8634 | // allocas are all used in the entry block, so we need approximately as many | |||
| 8635 | // entries as we have arguments. | |||
| 8636 | enum StaticAllocaInfo { Unknown, Clobbered, Elidable }; | |||
| 8637 | SmallDenseMap<const AllocaInst *, StaticAllocaInfo, 8> StaticAllocas; | |||
| 8638 | unsigned NumArgs = FuncInfo->Fn->arg_size(); | |||
| 8639 | StaticAllocas.reserve(NumArgs * 2); | |||
| 8640 | ||||
| 8641 | auto GetInfoIfStaticAlloca = [&](const Value *V) -> StaticAllocaInfo * { | |||
| 8642 | if (!V) | |||
| 8643 | return nullptr; | |||
| 8644 | V = V->stripPointerCasts(); | |||
| 8645 | const auto *AI = dyn_cast<AllocaInst>(V); | |||
| 8646 | if (!AI || !AI->isStaticAlloca() || !FuncInfo->StaticAllocaMap.count(AI)) | |||
| 8647 | return nullptr; | |||
| 8648 | auto Iter = StaticAllocas.insert({AI, Unknown}); | |||
| 8649 | return &Iter.first->second; | |||
| 8650 | }; | |||
| 8651 | ||||
| 8652 | // Look for stores of arguments to static allocas. Look through bitcasts and | |||
| 8653 | // GEPs to handle type coercions, as long as the alloca is fully initialized | |||
| 8654 | // by the store. Any non-store use of an alloca escapes it and any subsequent | |||
| 8655 | // unanalyzed store might write it. | |||
| 8656 | // FIXME: Handle structs initialized with multiple stores. | |||
| 8657 | for (const Instruction &I : FuncInfo->Fn->getEntryBlock()) { | |||
| 8658 | // Look for stores, and handle non-store uses conservatively. | |||
| 8659 | const auto *SI = dyn_cast<StoreInst>(&I); | |||
| 8660 | if (!SI) { | |||
| 8661 | // We will look through cast uses, so ignore them completely. | |||
| 8662 | if (I.isCast()) | |||
| 8663 | continue; | |||
| 8664 | // Ignore debug info intrinsics, they don't escape or store to allocas. | |||
| 8665 | if (isa<DbgInfoIntrinsic>(I)) | |||
| 8666 | continue; | |||
| 8667 | // This is an unknown instruction. Assume it escapes or writes to all | |||
| 8668 | // static alloca operands. | |||
| 8669 | for (const Use &U : I.operands()) { | |||
| 8670 | if (StaticAllocaInfo *Info = GetInfoIfStaticAlloca(U)) | |||
| 8671 | *Info = StaticAllocaInfo::Clobbered; | |||
| 8672 | } | |||
| 8673 | continue; | |||
| 8674 | } | |||
| 8675 | ||||
| 8676 | // If the stored value is a static alloca, mark it as escaped. | |||
| 8677 | if (StaticAllocaInfo *Info = GetInfoIfStaticAlloca(SI->getValueOperand())) | |||
| 8678 | *Info = StaticAllocaInfo::Clobbered; | |||
| 8679 | ||||
| 8680 | // Check if the destination is a static alloca. | |||
| 8681 | const Value *Dst = SI->getPointerOperand()->stripPointerCasts(); | |||
| 8682 | StaticAllocaInfo *Info = GetInfoIfStaticAlloca(Dst); | |||
| 8683 | if (!Info) | |||
| 8684 | continue; | |||
| 8685 | const AllocaInst *AI = cast<AllocaInst>(Dst); | |||
| 8686 | ||||
| 8687 | // Skip allocas that have been initialized or clobbered. | |||
| 8688 | if (*Info != StaticAllocaInfo::Unknown) | |||
| 8689 | continue; | |||
| 8690 | ||||
| 8691 | // Check if the stored value is an argument, and that this store fully | |||
| 8692 | // initializes the alloca. Don't elide copies from the same argument twice. | |||
| 8693 | const Value *Val = SI->getValueOperand()->stripPointerCasts(); | |||
| 8694 | const auto *Arg = dyn_cast<Argument>(Val); | |||
| 8695 | if (!Arg || Arg->hasInAllocaAttr() || Arg->hasByValAttr() || | |||
| 8696 | Arg->getType()->isEmptyTy() || | |||
| 8697 | DL.getTypeStoreSize(Arg->getType()) != | |||
| 8698 | DL.getTypeAllocSize(AI->getAllocatedType()) || | |||
| 8699 | ArgCopyElisionCandidates.count(Arg)) { | |||
| 8700 | *Info = StaticAllocaInfo::Clobbered; | |||
| 8701 | continue; | |||
| 8702 | } | |||
| 8703 | ||||
| 8704 | LLVM_DEBUG(dbgs() << "Found argument copy elision candidate: " << *AIdo { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType ("isel")) { dbgs() << "Found argument copy elision candidate: " << *AI << '\n'; } } while (false) | |||
| 8705 | << '\n')do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType ("isel")) { dbgs() << "Found argument copy elision candidate: " << *AI << '\n'; } } while (false); | |||
| 8706 | ||||
| 8707 | // Mark this alloca and store for argument copy elision. | |||
| 8708 | *Info = StaticAllocaInfo::Elidable; | |||
| 8709 | ArgCopyElisionCandidates.insert({Arg, {AI, SI}}); | |||
| 8710 | ||||
| 8711 | // Stop scanning if we've seen all arguments. This will happen early in -O0 | |||
| 8712 | // builds, which is useful, because -O0 builds have large entry blocks and | |||
| 8713 | // many allocas. | |||
| 8714 | if (ArgCopyElisionCandidates.size() == NumArgs) | |||
| 8715 | break; | |||
| 8716 | } | |||
| 8717 | } | |||
| 8718 | ||||
| 8719 | /// Try to elide argument copies from memory into a local alloca. Succeeds if | |||
| 8720 | /// ArgVal is a load from a suitable fixed stack object. | |||
| 8721 | static void tryToElideArgumentCopy( | |||
| 8722 | FunctionLoweringInfo *FuncInfo, SmallVectorImpl<SDValue> &Chains, | |||
| 8723 | DenseMap<int, int> &ArgCopyElisionFrameIndexMap, | |||
| 8724 | SmallPtrSetImpl<const Instruction *> &ElidedArgCopyInstrs, | |||
| 8725 | ArgCopyElisionMapTy &ArgCopyElisionCandidates, const Argument &Arg, | |||
| 8726 | SDValue ArgVal, bool &ArgHasUses) { | |||
| 8727 | // Check if this is a load from a fixed stack object. | |||
| 8728 | auto *LNode = dyn_cast<LoadSDNode>(ArgVal); | |||
| 8729 | if (!LNode) | |||
| 8730 | return; | |||
| 8731 | auto *FINode = dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode()); | |||
| 8732 | if (!FINode) | |||
| 8733 | return; | |||
| 8734 | ||||
| 8735 | // Check that the fixed stack object is the right size and alignment. | |||
| 8736 | // Look at the alignment that the user wrote on the alloca instead of looking | |||
| 8737 | // at the stack object. | |||
| 8738 | auto ArgCopyIter = ArgCopyElisionCandidates.find(&Arg); | |||
| 8739 | assert(ArgCopyIter != ArgCopyElisionCandidates.end())(static_cast <bool> (ArgCopyIter != ArgCopyElisionCandidates .end()) ? void (0) : __assert_fail ("ArgCopyIter != ArgCopyElisionCandidates.end()" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 8739, __extension__ __PRETTY_FUNCTION__)); | |||
| 8740 | const AllocaInst *AI = ArgCopyIter->second.first; | |||
| 8741 | int FixedIndex = FINode->getIndex(); | |||
| 8742 | int &AllocaIndex = FuncInfo->StaticAllocaMap[AI]; | |||
| 8743 | int OldIndex = AllocaIndex; | |||
| 8744 | MachineFrameInfo &MFI = FuncInfo->MF->getFrameInfo(); | |||
| 8745 | if (MFI.getObjectSize(FixedIndex) != MFI.getObjectSize(OldIndex)) { | |||
| 8746 | LLVM_DEBUG(do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType ("isel")) { dbgs() << " argument copy elision failed due to bad fixed stack " "object size\n"; } } while (false) | |||
| 8747 | dbgs() << " argument copy elision failed due to bad fixed stack "do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType ("isel")) { dbgs() << " argument copy elision failed due to bad fixed stack " "object size\n"; } } while (false) | |||
| 8748 | "object size\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType ("isel")) { dbgs() << " argument copy elision failed due to bad fixed stack " "object size\n"; } } while (false); | |||
| 8749 | return; | |||
| 8750 | } | |||
| 8751 | unsigned RequiredAlignment = AI->getAlignment(); | |||
| 8752 | if (!RequiredAlignment) { | |||
| 8753 | RequiredAlignment = FuncInfo->MF->getDataLayout().getABITypeAlignment( | |||
| 8754 | AI->getAllocatedType()); | |||
| 8755 | } | |||
| 8756 | if (MFI.getObjectAlignment(FixedIndex) < RequiredAlignment) { | |||
| 8757 | LLVM_DEBUG(dbgs() << " argument copy elision failed: alignment of alloca "do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType ("isel")) { dbgs() << " argument copy elision failed: alignment of alloca " "greater than stack argument alignment (" << RequiredAlignment << " vs " << MFI.getObjectAlignment(FixedIndex) << ")\n"; } } while (false) | |||
| 8758 | "greater than stack argument alignment ("do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType ("isel")) { dbgs() << " argument copy elision failed: alignment of alloca " "greater than stack argument alignment (" << RequiredAlignment << " vs " << MFI.getObjectAlignment(FixedIndex) << ")\n"; } } while (false) | |||
| 8759 | << RequiredAlignment << " vs "do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType ("isel")) { dbgs() << " argument copy elision failed: alignment of alloca " "greater than stack argument alignment (" << RequiredAlignment << " vs " << MFI.getObjectAlignment(FixedIndex) << ")\n"; } } while (false) | |||
| 8760 | << MFI.getObjectAlignment(FixedIndex) << ")\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType ("isel")) { dbgs() << " argument copy elision failed: alignment of alloca " "greater than stack argument alignment (" << RequiredAlignment << " vs " << MFI.getObjectAlignment(FixedIndex) << ")\n"; } } while (false); | |||
| 8761 | return; | |||
| 8762 | } | |||
| 8763 | ||||
| 8764 | // Perform the elision. Delete the old stack object and replace its only use | |||
| 8765 | // in the variable info map. Mark the stack object as mutable. | |||
| 8766 | LLVM_DEBUG({do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType ("isel")) { { dbgs() << "Eliding argument copy from " << Arg << " to " << *AI << '\n' << " Replacing frame index " << OldIndex << " with " << FixedIndex << '\n'; }; } } while (false) | |||
| 8767 | dbgs() << "Eliding argument copy from " << Arg << " to " << *AI << '\n'do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType ("isel")) { { dbgs() << "Eliding argument copy from " << Arg << " to " << *AI << '\n' << " Replacing frame index " << OldIndex << " with " << FixedIndex << '\n'; }; } } while (false) | |||
| 8768 | << " Replacing frame index " << OldIndex << " with " << FixedIndexdo { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType ("isel")) { { dbgs() << "Eliding argument copy from " << Arg << " to " << *AI << '\n' << " Replacing frame index " << OldIndex << " with " << FixedIndex << '\n'; }; } } while (false) | |||
| 8769 | << '\n';do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType ("isel")) { { dbgs() << "Eliding argument copy from " << Arg << " to " << *AI << '\n' << " Replacing frame index " << OldIndex << " with " << FixedIndex << '\n'; }; } } while (false) | |||
| 8770 | })do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType ("isel")) { { dbgs() << "Eliding argument copy from " << Arg << " to " << *AI << '\n' << " Replacing frame index " << OldIndex << " with " << FixedIndex << '\n'; }; } } while (false); | |||
| 8771 | MFI.RemoveStackObject(OldIndex); | |||
| 8772 | MFI.setIsImmutableObjectIndex(FixedIndex, false); | |||
| 8773 | AllocaIndex = FixedIndex; | |||
| 8774 | ArgCopyElisionFrameIndexMap.insert({OldIndex, FixedIndex}); | |||
| 8775 | Chains.push_back(ArgVal.getValue(1)); | |||
| 8776 | ||||
| 8777 | // Avoid emitting code for the store implementing the copy. | |||
| 8778 | const StoreInst *SI = ArgCopyIter->second.second; | |||
| 8779 | ElidedArgCopyInstrs.insert(SI); | |||
| 8780 | ||||
| 8781 | // Check for uses of the argument again so that we can avoid exporting ArgVal | |||
| 8782 | // if it is't used by anything other than the store. | |||
| 8783 | for (const Value *U : Arg.users()) { | |||
| 8784 | if (U != SI) { | |||
| 8785 | ArgHasUses = true; | |||
| 8786 | break; | |||
| 8787 | } | |||
| 8788 | } | |||
| 8789 | } | |||
| 8790 | ||||
| 8791 | void SelectionDAGISel::LowerArguments(const Function &F) { | |||
| 8792 | SelectionDAG &DAG = SDB->DAG; | |||
| 8793 | SDLoc dl = SDB->getCurSDLoc(); | |||
| 8794 | const DataLayout &DL = DAG.getDataLayout(); | |||
| 8795 | SmallVector<ISD::InputArg, 16> Ins; | |||
| 8796 | ||||
| 8797 | if (!FuncInfo->CanLowerReturn) { | |||
| 8798 | // Put in an sret pointer parameter before all the other parameters. | |||
| 8799 | SmallVector<EVT, 1> ValueVTs; | |||
| 8800 | ComputeValueVTs(*TLI, DAG.getDataLayout(), | |||
| 8801 | F.getReturnType()->getPointerTo( | |||
| 8802 | DAG.getDataLayout().getAllocaAddrSpace()), | |||
| 8803 | ValueVTs); | |||
| 8804 | ||||
| 8805 | // NOTE: Assuming that a pointer will never break down to more than one VT | |||
| 8806 | // or one register. | |||
| 8807 | ISD::ArgFlagsTy Flags; | |||
| 8808 | Flags.setSRet(); | |||
| 8809 | MVT RegisterVT = TLI->getRegisterType(*DAG.getContext(), ValueVTs[0]); | |||
| 8810 | ISD::InputArg RetArg(Flags, RegisterVT, ValueVTs[0], true, | |||
| 8811 | ISD::InputArg::NoArgIndex, 0); | |||
| 8812 | Ins.push_back(RetArg); | |||
| 8813 | } | |||
| 8814 | ||||
| 8815 | // Look for stores of arguments to static allocas. Mark such arguments with a | |||
| 8816 | // flag to ask the target to give us the memory location of that argument if | |||
| 8817 | // available. | |||
| 8818 | ArgCopyElisionMapTy ArgCopyElisionCandidates; | |||
| 8819 | findArgumentCopyElisionCandidates(DL, FuncInfo, ArgCopyElisionCandidates); | |||
| 8820 | ||||
| 8821 | // Set up the incoming argument description vector. | |||
| 8822 | for (const Argument &Arg : F.args()) { | |||
| 8823 | unsigned ArgNo = Arg.getArgNo(); | |||
| 8824 | SmallVector<EVT, 4> ValueVTs; | |||
| 8825 | ComputeValueVTs(*TLI, DAG.getDataLayout(), Arg.getType(), ValueVTs); | |||
| 8826 | bool isArgValueUsed = !Arg.use_empty(); | |||
| 8827 | unsigned PartBase = 0; | |||
| 8828 | Type *FinalType = Arg.getType(); | |||
| 8829 | if (Arg.hasAttribute(Attribute::ByVal)) | |||
| 8830 | FinalType = cast<PointerType>(FinalType)->getElementType(); | |||
| 8831 | bool NeedsRegBlock = TLI->functionArgumentNeedsConsecutiveRegisters( | |||
| 8832 | FinalType, F.getCallingConv(), F.isVarArg()); | |||
| 8833 | for (unsigned Value = 0, NumValues = ValueVTs.size(); | |||
| 8834 | Value != NumValues; ++Value) { | |||
| 8835 | EVT VT = ValueVTs[Value]; | |||
| 8836 | Type *ArgTy = VT.getTypeForEVT(*DAG.getContext()); | |||
| 8837 | ISD::ArgFlagsTy Flags; | |||
| 8838 | ||||
| 8839 | // Certain targets (such as MIPS), may have a different ABI alignment | |||
| 8840 | // for a type depending on the context. Give the target a chance to | |||
| 8841 | // specify the alignment it wants. | |||
| 8842 | unsigned OriginalAlignment = | |||
| 8843 | TLI->getABIAlignmentForCallingConv(ArgTy, DL); | |||
| 8844 | ||||
| 8845 | if (Arg.hasAttribute(Attribute::ZExt)) | |||
| 8846 | Flags.setZExt(); | |||
| 8847 | if (Arg.hasAttribute(Attribute::SExt)) | |||
| 8848 | Flags.setSExt(); | |||
| 8849 | if (Arg.hasAttribute(Attribute::InReg)) { | |||
| 8850 | // If we are using vectorcall calling convention, a structure that is | |||
| 8851 | // passed InReg - is surely an HVA | |||
| 8852 | if (F.getCallingConv() == CallingConv::X86_VectorCall && | |||
| 8853 | isa<StructType>(Arg.getType())) { | |||
| 8854 | // The first value of a structure is marked | |||
| 8855 | if (0 == Value) | |||
| 8856 | Flags.setHvaStart(); | |||
| 8857 | Flags.setHva(); | |||
| 8858 | } | |||
| 8859 | // Set InReg Flag | |||
| 8860 | Flags.setInReg(); | |||
| 8861 | } | |||
| 8862 | if (Arg.hasAttribute(Attribute::StructRet)) | |||
| 8863 | Flags.setSRet(); | |||
| 8864 | if (Arg.hasAttribute(Attribute::SwiftSelf)) | |||
| 8865 | Flags.setSwiftSelf(); | |||
| 8866 | if (Arg.hasAttribute(Attribute::SwiftError)) | |||
| 8867 | Flags.setSwiftError(); | |||
| 8868 | if (Arg.hasAttribute(Attribute::ByVal)) | |||
| 8869 | Flags.setByVal(); | |||
| 8870 | if (Arg.hasAttribute(Attribute::InAlloca)) { | |||
| 8871 | Flags.setInAlloca(); | |||
| 8872 | // Set the byval flag for CCAssignFn callbacks that don't know about | |||
| 8873 | // inalloca. This way we can know how many bytes we should've allocated | |||
| 8874 | // and how many bytes a callee cleanup function will pop. If we port | |||
| 8875 | // inalloca to more targets, we'll have to add custom inalloca handling | |||
| 8876 | // in the various CC lowering callbacks. | |||
| 8877 | Flags.setByVal(); | |||
| 8878 | } | |||
| 8879 | if (F.getCallingConv() == CallingConv::X86_INTR) { | |||
| 8880 | // IA Interrupt passes frame (1st parameter) by value in the stack. | |||
| 8881 | if (ArgNo == 0) | |||
| 8882 | Flags.setByVal(); | |||
| 8883 | } | |||
| 8884 | if (Flags.isByVal() || Flags.isInAlloca()) { | |||
| 8885 | PointerType *Ty = cast<PointerType>(Arg.getType()); | |||
| 8886 | Type *ElementTy = Ty->getElementType(); | |||
| 8887 | Flags.setByValSize(DL.getTypeAllocSize(ElementTy)); | |||
| 8888 | // For ByVal, alignment should be passed from FE. BE will guess if | |||
| 8889 | // this info is not there but there are cases it cannot get right. | |||
| 8890 | unsigned FrameAlign; | |||
| 8891 | if (Arg.getParamAlignment()) | |||
| 8892 | FrameAlign = Arg.getParamAlignment(); | |||
| 8893 | else | |||
| 8894 | FrameAlign = TLI->getByValTypeAlignment(ElementTy, DL); | |||
| 8895 | Flags.setByValAlign(FrameAlign); | |||
| 8896 | } | |||
| 8897 | if (Arg.hasAttribute(Attribute::Nest)) | |||
| 8898 | Flags.setNest(); | |||
| 8899 | if (NeedsRegBlock) | |||
| 8900 | Flags.setInConsecutiveRegs(); | |||
| 8901 | Flags.setOrigAlign(OriginalAlignment); | |||
| 8902 | if (ArgCopyElisionCandidates.count(&Arg)) | |||
| 8903 | Flags.setCopyElisionCandidate(); | |||
| 8904 | ||||
| 8905 | MVT RegisterVT = | |||
| 8906 | TLI->getRegisterTypeForCallingConv(*CurDAG->getContext(), VT); | |||
| 8907 | unsigned NumRegs = | |||
| 8908 | TLI->getNumRegistersForCallingConv(*CurDAG->getContext(), VT); | |||
| 8909 | for (unsigned i = 0; i != NumRegs; ++i) { | |||
| 8910 | ISD::InputArg MyFlags(Flags, RegisterVT, VT, isArgValueUsed, | |||
| 8911 | ArgNo, PartBase+i*RegisterVT.getStoreSize()); | |||
| 8912 | if (NumRegs > 1 && i == 0) | |||
| 8913 | MyFlags.Flags.setSplit(); | |||
| 8914 | // if it isn't first piece, alignment must be 1 | |||
| 8915 | else if (i > 0) { | |||
| 8916 | MyFlags.Flags.setOrigAlign(1); | |||
| 8917 | if (i == NumRegs - 1) | |||
| 8918 | MyFlags.Flags.setSplitEnd(); | |||
| 8919 | } | |||
| 8920 | Ins.push_back(MyFlags); | |||
| 8921 | } | |||
| 8922 | if (NeedsRegBlock && Value == NumValues - 1) | |||
| 8923 | Ins[Ins.size() - 1].Flags.setInConsecutiveRegsLast(); | |||
| 8924 | PartBase += VT.getStoreSize(); | |||
| 8925 | } | |||
| 8926 | } | |||
| 8927 | ||||
| 8928 | // Call the target to set up the argument values. | |||
| 8929 | SmallVector<SDValue, 8> InVals; | |||
| 8930 | SDValue NewRoot = TLI->LowerFormalArguments( | |||
| 8931 | DAG.getRoot(), F.getCallingConv(), F.isVarArg(), Ins, dl, DAG, InVals); | |||
| 8932 | ||||
| 8933 | // Verify that the target's LowerFormalArguments behaved as expected. | |||
| 8934 | assert(NewRoot.getNode() && NewRoot.getValueType() == MVT::Other &&(static_cast <bool> (NewRoot.getNode() && NewRoot .getValueType() == MVT::Other && "LowerFormalArguments didn't return a valid chain!" ) ? void (0) : __assert_fail ("NewRoot.getNode() && NewRoot.getValueType() == MVT::Other && \"LowerFormalArguments didn't return a valid chain!\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 8935, __extension__ __PRETTY_FUNCTION__)) | |||
| 8935 | "LowerFormalArguments didn't return a valid chain!")(static_cast <bool> (NewRoot.getNode() && NewRoot .getValueType() == MVT::Other && "LowerFormalArguments didn't return a valid chain!" ) ? void (0) : __assert_fail ("NewRoot.getNode() && NewRoot.getValueType() == MVT::Other && \"LowerFormalArguments didn't return a valid chain!\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 8935, __extension__ __PRETTY_FUNCTION__)); | |||
| 8936 | assert(InVals.size() == Ins.size() &&(static_cast <bool> (InVals.size() == Ins.size() && "LowerFormalArguments didn't emit the correct number of values!" ) ? void (0) : __assert_fail ("InVals.size() == Ins.size() && \"LowerFormalArguments didn't emit the correct number of values!\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 8937, __extension__ __PRETTY_FUNCTION__)) | |||
| 8937 | "LowerFormalArguments didn't emit the correct number of values!")(static_cast <bool> (InVals.size() == Ins.size() && "LowerFormalArguments didn't emit the correct number of values!" ) ? void (0) : __assert_fail ("InVals.size() == Ins.size() && \"LowerFormalArguments didn't emit the correct number of values!\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 8937, __extension__ __PRETTY_FUNCTION__)); | |||
| 8938 | LLVM_DEBUG({do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType ("isel")) { { for (unsigned i = 0, e = Ins.size(); i != e; ++ i) { (static_cast <bool> (InVals[i].getNode() && "LowerFormalArguments emitted a null value!") ? void (0) : __assert_fail ("InVals[i].getNode() && \"LowerFormalArguments emitted a null value!\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 8941, __extension__ __PRETTY_FUNCTION__)); (static_cast < bool> (EVT(Ins[i].VT) == InVals[i].getValueType() && "LowerFormalArguments emitted a value with the wrong type!") ? void (0) : __assert_fail ("EVT(Ins[i].VT) == InVals[i].getValueType() && \"LowerFormalArguments emitted a value with the wrong type!\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 8943, __extension__ __PRETTY_FUNCTION__)); } }; } } while ( false) | |||
| 8939 | for (unsigned i = 0, e = Ins.size(); i != e; ++i) {do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType ("isel")) { { for (unsigned i = 0, e = Ins.size(); i != e; ++ i) { (static_cast <bool> (InVals[i].getNode() && "LowerFormalArguments emitted a null value!") ? void (0) : __assert_fail ("InVals[i].getNode() && \"LowerFormalArguments emitted a null value!\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 8941, __extension__ __PRETTY_FUNCTION__)); (static_cast < bool> (EVT(Ins[i].VT) == InVals[i].getValueType() && "LowerFormalArguments emitted a value with the wrong type!") ? void (0) : __assert_fail ("EVT(Ins[i].VT) == InVals[i].getValueType() && \"LowerFormalArguments emitted a value with the wrong type!\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 8943, __extension__ __PRETTY_FUNCTION__)); } }; } } while ( false) | |||
| 8940 | assert(InVals[i].getNode() &&do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType ("isel")) { { for (unsigned i = 0, e = Ins.size(); i != e; ++ i) { (static_cast <bool> (InVals[i].getNode() && "LowerFormalArguments emitted a null value!") ? void (0) : __assert_fail ("InVals[i].getNode() && \"LowerFormalArguments emitted a null value!\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 8941, __extension__ __PRETTY_FUNCTION__)); (static_cast < bool> (EVT(Ins[i].VT) == InVals[i].getValueType() && "LowerFormalArguments emitted a value with the wrong type!") ? void (0) : __assert_fail ("EVT(Ins[i].VT) == InVals[i].getValueType() && \"LowerFormalArguments emitted a value with the wrong type!\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 8943, __extension__ __PRETTY_FUNCTION__)); } }; } } while ( false) | |||
| 8941 | "LowerFormalArguments emitted a null value!");do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType ("isel")) { { for (unsigned i = 0, e = Ins.size(); i != e; ++ i) { (static_cast <bool> (InVals[i].getNode() && "LowerFormalArguments emitted a null value!") ? void (0) : __assert_fail ("InVals[i].getNode() && \"LowerFormalArguments emitted a null value!\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 8941, __extension__ __PRETTY_FUNCTION__)); (static_cast < bool> (EVT(Ins[i].VT) == InVals[i].getValueType() && "LowerFormalArguments emitted a value with the wrong type!") ? void (0) : __assert_fail ("EVT(Ins[i].VT) == InVals[i].getValueType() && \"LowerFormalArguments emitted a value with the wrong type!\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 8943, __extension__ __PRETTY_FUNCTION__)); } }; } } while ( false) | |||
| 8942 | assert(EVT(Ins[i].VT) == InVals[i].getValueType() &&do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType ("isel")) { { for (unsigned i = 0, e = Ins.size(); i != e; ++ i) { (static_cast <bool> (InVals[i].getNode() && "LowerFormalArguments emitted a null value!") ? void (0) : __assert_fail ("InVals[i].getNode() && \"LowerFormalArguments emitted a null value!\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 8941, __extension__ __PRETTY_FUNCTION__)); (static_cast < bool> (EVT(Ins[i].VT) == InVals[i].getValueType() && "LowerFormalArguments emitted a value with the wrong type!") ? void (0) : __assert_fail ("EVT(Ins[i].VT) == InVals[i].getValueType() && \"LowerFormalArguments emitted a value with the wrong type!\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 8943, __extension__ __PRETTY_FUNCTION__)); } }; } } while ( false) | |||
| 8943 | "LowerFormalArguments emitted a value with the wrong type!");do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType ("isel")) { { for (unsigned i = 0, e = Ins.size(); i != e; ++ i) { (static_cast <bool> (InVals[i].getNode() && "LowerFormalArguments emitted a null value!") ? void (0) : __assert_fail ("InVals[i].getNode() && \"LowerFormalArguments emitted a null value!\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 8941, __extension__ __PRETTY_FUNCTION__)); (static_cast < bool> (EVT(Ins[i].VT) == InVals[i].getValueType() && "LowerFormalArguments emitted a value with the wrong type!") ? void (0) : __assert_fail ("EVT(Ins[i].VT) == InVals[i].getValueType() && \"LowerFormalArguments emitted a value with the wrong type!\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 8943, __extension__ __PRETTY_FUNCTION__)); } }; } } while ( false) | |||
| 8944 | }do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType ("isel")) { { for (unsigned i = 0, e = Ins.size(); i != e; ++ i) { (static_cast <bool> (InVals[i].getNode() && "LowerFormalArguments emitted a null value!") ? void (0) : __assert_fail ("InVals[i].getNode() && \"LowerFormalArguments emitted a null value!\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 8941, __extension__ __PRETTY_FUNCTION__)); (static_cast < bool> (EVT(Ins[i].VT) == InVals[i].getValueType() && "LowerFormalArguments emitted a value with the wrong type!") ? void (0) : __assert_fail ("EVT(Ins[i].VT) == InVals[i].getValueType() && \"LowerFormalArguments emitted a value with the wrong type!\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 8943, __extension__ __PRETTY_FUNCTION__)); } }; } } while ( false) | |||
| 8945 | })do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType ("isel")) { { for (unsigned i = 0, e = Ins.size(); i != e; ++ i) { (static_cast <bool> (InVals[i].getNode() && "LowerFormalArguments emitted a null value!") ? void (0) : __assert_fail ("InVals[i].getNode() && \"LowerFormalArguments emitted a null value!\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 8941, __extension__ __PRETTY_FUNCTION__)); (static_cast < bool> (EVT(Ins[i].VT) == InVals[i].getValueType() && "LowerFormalArguments emitted a value with the wrong type!") ? void (0) : __assert_fail ("EVT(Ins[i].VT) == InVals[i].getValueType() && \"LowerFormalArguments emitted a value with the wrong type!\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 8943, __extension__ __PRETTY_FUNCTION__)); } }; } } while ( false); | |||
| 8946 | ||||
| 8947 | // Update the DAG with the new chain value resulting from argument lowering. | |||
| 8948 | DAG.setRoot(NewRoot); | |||
| 8949 | ||||
| 8950 | // Set up the argument values. | |||
| 8951 | unsigned i = 0; | |||
| 8952 | if (!FuncInfo->CanLowerReturn) { | |||
| 8953 | // Create a virtual register for the sret pointer, and put in a copy | |||
| 8954 | // from the sret argument into it. | |||
| 8955 | SmallVector<EVT, 1> ValueVTs; | |||
| 8956 | ComputeValueVTs(*TLI, DAG.getDataLayout(), | |||
| 8957 | F.getReturnType()->getPointerTo( | |||
| 8958 | DAG.getDataLayout().getAllocaAddrSpace()), | |||
| 8959 | ValueVTs); | |||
| 8960 | MVT VT = ValueVTs[0].getSimpleVT(); | |||
| 8961 | MVT RegVT = TLI->getRegisterType(*CurDAG->getContext(), VT); | |||
| 8962 | Optional<ISD::NodeType> AssertOp = None; | |||
| 8963 | SDValue ArgValue = getCopyFromParts(DAG, dl, &InVals[0], 1, | |||
| 8964 | RegVT, VT, nullptr, AssertOp); | |||
| 8965 | ||||
| 8966 | MachineFunction& MF = SDB->DAG.getMachineFunction(); | |||
| 8967 | MachineRegisterInfo& RegInfo = MF.getRegInfo(); | |||
| 8968 | unsigned SRetReg = RegInfo.createVirtualRegister(TLI->getRegClassFor(RegVT)); | |||
| 8969 | FuncInfo->DemoteRegister = SRetReg; | |||
| 8970 | NewRoot = | |||
| 8971 | SDB->DAG.getCopyToReg(NewRoot, SDB->getCurSDLoc(), SRetReg, ArgValue); | |||
| 8972 | DAG.setRoot(NewRoot); | |||
| 8973 | ||||
| 8974 | // i indexes lowered arguments. Bump it past the hidden sret argument. | |||
| 8975 | ++i; | |||
| 8976 | } | |||
| 8977 | ||||
| 8978 | SmallVector<SDValue, 4> Chains; | |||
| 8979 | DenseMap<int, int> ArgCopyElisionFrameIndexMap; | |||
| 8980 | for (const Argument &Arg : F.args()) { | |||
| 8981 | SmallVector<SDValue, 4> ArgValues; | |||
| 8982 | SmallVector<EVT, 4> ValueVTs; | |||
| 8983 | ComputeValueVTs(*TLI, DAG.getDataLayout(), Arg.getType(), ValueVTs); | |||
| 8984 | unsigned NumValues = ValueVTs.size(); | |||
| 8985 | if (NumValues == 0) | |||
| 8986 | continue; | |||
| 8987 | ||||
| 8988 | bool ArgHasUses = !Arg.use_empty(); | |||
| 8989 | ||||
| 8990 | // Elide the copying store if the target loaded this argument from a | |||
| 8991 | // suitable fixed stack object. | |||
| 8992 | if (Ins[i].Flags.isCopyElisionCandidate()) { | |||
| 8993 | tryToElideArgumentCopy(FuncInfo, Chains, ArgCopyElisionFrameIndexMap, | |||
| 8994 | ElidedArgCopyInstrs, ArgCopyElisionCandidates, Arg, | |||
| 8995 | InVals[i], ArgHasUses); | |||
| 8996 | } | |||
| 8997 | ||||
| 8998 | // If this argument is unused then remember its value. It is used to generate | |||
| 8999 | // debugging information. | |||
| 9000 | bool isSwiftErrorArg = | |||
| 9001 | TLI->supportSwiftError() && | |||
| 9002 | Arg.hasAttribute(Attribute::SwiftError); | |||
| 9003 | if (!ArgHasUses && !isSwiftErrorArg) { | |||
| 9004 | SDB->setUnusedArgValue(&Arg, InVals[i]); | |||
| 9005 | ||||
| 9006 | // Also remember any frame index for use in FastISel. | |||
| 9007 | if (FrameIndexSDNode *FI = | |||
| 9008 | dyn_cast<FrameIndexSDNode>(InVals[i].getNode())) | |||
| 9009 | FuncInfo->setArgumentFrameIndex(&Arg, FI->getIndex()); | |||
| 9010 | } | |||
| 9011 | ||||
| 9012 | for (unsigned Val = 0; Val != NumValues; ++Val) { | |||
| 9013 | EVT VT = ValueVTs[Val]; | |||
| 9014 | MVT PartVT = | |||
| 9015 | TLI->getRegisterTypeForCallingConv(*CurDAG->getContext(), VT); | |||
| 9016 | unsigned NumParts = | |||
| 9017 | TLI->getNumRegistersForCallingConv(*CurDAG->getContext(), VT); | |||
| 9018 | ||||
| 9019 | // Even an apparant 'unused' swifterror argument needs to be returned. So | |||
| 9020 | // we do generate a copy for it that can be used on return from the | |||
| 9021 | // function. | |||
| 9022 | if (ArgHasUses || isSwiftErrorArg) { | |||
| 9023 | Optional<ISD::NodeType> AssertOp; | |||
| 9024 | if (Arg.hasAttribute(Attribute::SExt)) | |||
| 9025 | AssertOp = ISD::AssertSext; | |||
| 9026 | else if (Arg.hasAttribute(Attribute::ZExt)) | |||
| 9027 | AssertOp = ISD::AssertZext; | |||
| 9028 | ||||
| 9029 | ArgValues.push_back(getCopyFromParts(DAG, dl, &InVals[i], NumParts, | |||
| 9030 | PartVT, VT, nullptr, AssertOp, | |||
| 9031 | true)); | |||
| 9032 | } | |||
| 9033 | ||||
| 9034 | i += NumParts; | |||
| 9035 | } | |||
| 9036 | ||||
| 9037 | // We don't need to do anything else for unused arguments. | |||
| 9038 | if (ArgValues.empty()) | |||
| 9039 | continue; | |||
| 9040 | ||||
| 9041 | // Note down frame index. | |||
| 9042 | if (FrameIndexSDNode *FI = | |||
| 9043 | dyn_cast<FrameIndexSDNode>(ArgValues[0].getNode())) | |||
| 9044 | FuncInfo->setArgumentFrameIndex(&Arg, FI->getIndex()); | |||
| 9045 | ||||
| 9046 | SDValue Res = DAG.getMergeValues(makeArrayRef(ArgValues.data(), NumValues), | |||
| 9047 | SDB->getCurSDLoc()); | |||
| 9048 | ||||
| 9049 | SDB->setValue(&Arg, Res); | |||
| 9050 | if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::BUILD_PAIR) { | |||
| 9051 | // We want to associate the argument with the frame index, among | |||
| 9052 | // involved operands, that correspond to the lowest address. The | |||
| 9053 | // getCopyFromParts function, called earlier, is swapping the order of | |||
| 9054 | // the operands to BUILD_PAIR depending on endianness. The result of | |||
| 9055 | // that swapping is that the least significant bits of the argument will | |||
| 9056 | // be in the first operand of the BUILD_PAIR node, and the most | |||
| 9057 | // significant bits will be in the second operand. | |||
| 9058 | unsigned LowAddressOp = DAG.getDataLayout().isBigEndian() ? 1 : 0; | |||
| 9059 | if (LoadSDNode *LNode = | |||
| 9060 | dyn_cast<LoadSDNode>(Res.getOperand(LowAddressOp).getNode())) | |||
| 9061 | if (FrameIndexSDNode *FI = | |||
| 9062 | dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode())) | |||
| 9063 | FuncInfo->setArgumentFrameIndex(&Arg, FI->getIndex()); | |||
| 9064 | } | |||
| 9065 | ||||
| 9066 | // Update the SwiftErrorVRegDefMap. | |||
| 9067 | if (Res.getOpcode() == ISD::CopyFromReg && isSwiftErrorArg) { | |||
| 9068 | unsigned Reg = cast<RegisterSDNode>(Res.getOperand(1))->getReg(); | |||
| 9069 | if (TargetRegisterInfo::isVirtualRegister(Reg)) | |||
| 9070 | FuncInfo->setCurrentSwiftErrorVReg(FuncInfo->MBB, | |||
| 9071 | FuncInfo->SwiftErrorArg, Reg); | |||
| 9072 | } | |||
| 9073 | ||||
| 9074 | // If this argument is live outside of the entry block, insert a copy from | |||
| 9075 | // wherever we got it to the vreg that other BB's will reference it as. | |||
| 9076 | if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::CopyFromReg) { | |||
| 9077 | // If we can, though, try to skip creating an unnecessary vreg. | |||
| 9078 | // FIXME: This isn't very clean... it would be nice to make this more | |||
| 9079 | // general. It's also subtly incompatible with the hacks FastISel | |||
| 9080 | // uses with vregs. | |||
| 9081 | unsigned Reg = cast<RegisterSDNode>(Res.getOperand(1))->getReg(); | |||
| 9082 | if (TargetRegisterInfo::isVirtualRegister(Reg)) { | |||
| 9083 | FuncInfo->ValueMap[&Arg] = Reg; | |||
| 9084 | continue; | |||
| 9085 | } | |||
| 9086 | } | |||
| 9087 | if (!isOnlyUsedInEntryBlock(&Arg, TM.Options.EnableFastISel)) { | |||
| 9088 | FuncInfo->InitializeRegForValue(&Arg); | |||
| 9089 | SDB->CopyToExportRegsIfNeeded(&Arg); | |||
| 9090 | } | |||
| 9091 | } | |||
| 9092 | ||||
| 9093 | if (!Chains.empty()) { | |||
| 9094 | Chains.push_back(NewRoot); | |||
| 9095 | NewRoot = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains); | |||
| 9096 | } | |||
| 9097 | ||||
| 9098 | DAG.setRoot(NewRoot); | |||
| 9099 | ||||
| 9100 | assert(i == InVals.size() && "Argument register count mismatch!")(static_cast <bool> (i == InVals.size() && "Argument register count mismatch!" ) ? void (0) : __assert_fail ("i == InVals.size() && \"Argument register count mismatch!\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 9100, __extension__ __PRETTY_FUNCTION__)); | |||
| 9101 | ||||
| 9102 | // If any argument copy elisions occurred and we have debug info, update the | |||
| 9103 | // stale frame indices used in the dbg.declare variable info table. | |||
| 9104 | MachineFunction::VariableDbgInfoMapTy &DbgDeclareInfo = MF->getVariableDbgInfo(); | |||
| 9105 | if (!DbgDeclareInfo.empty() && !ArgCopyElisionFrameIndexMap.empty()) { | |||
| 9106 | for (MachineFunction::VariableDbgInfo &VI : DbgDeclareInfo) { | |||
| 9107 | auto I = ArgCopyElisionFrameIndexMap.find(VI.Slot); | |||
| 9108 | if (I != ArgCopyElisionFrameIndexMap.end()) | |||
| 9109 | VI.Slot = I->second; | |||
| 9110 | } | |||
| 9111 | } | |||
| 9112 | ||||
| 9113 | // Finally, if the target has anything special to do, allow it to do so. | |||
| 9114 | EmitFunctionEntryCode(); | |||
| 9115 | } | |||
| 9116 | ||||
| 9117 | /// Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to | |||
| 9118 | /// ensure constants are generated when needed. Remember the virtual registers | |||
| 9119 | /// that need to be added to the Machine PHI nodes as input. We cannot just | |||
| 9120 | /// directly add them, because expansion might result in multiple MBB's for one | |||
| 9121 | /// BB. As such, the start of the BB might correspond to a different MBB than | |||
| 9122 | /// the end. | |||
| 9123 | void | |||
| 9124 | SelectionDAGBuilder::HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB) { | |||
| 9125 | const TerminatorInst *TI = LLVMBB->getTerminator(); | |||
| 9126 | ||||
| 9127 | SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled; | |||
| 9128 | ||||
| 9129 | // Check PHI nodes in successors that expect a value to be available from this | |||
| 9130 | // block. | |||
| 9131 | for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) { | |||
| 9132 | const BasicBlock *SuccBB = TI->getSuccessor(succ); | |||
| 9133 | if (!isa<PHINode>(SuccBB->begin())) continue; | |||
| 9134 | MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB]; | |||
| 9135 | ||||
| 9136 | // If this terminator has multiple identical successors (common for | |||
| 9137 | // switches), only handle each succ once. | |||
| 9138 | if (!SuccsHandled.insert(SuccMBB).second) | |||
| 9139 | continue; | |||
| 9140 | ||||
| 9141 | MachineBasicBlock::iterator MBBI = SuccMBB->begin(); | |||
| 9142 | ||||
| 9143 | // At this point we know that there is a 1-1 correspondence between LLVM PHI | |||
| 9144 | // nodes and Machine PHI nodes, but the incoming operands have not been | |||
| 9145 | // emitted yet. | |||
| 9146 | for (const PHINode &PN : SuccBB->phis()) { | |||
| 9147 | // Ignore dead phi's. | |||
| 9148 | if (PN.use_empty()) | |||
| 9149 | continue; | |||
| 9150 | ||||
| 9151 | // Skip empty types | |||
| 9152 | if (PN.getType()->isEmptyTy()) | |||
| 9153 | continue; | |||
| 9154 | ||||
| 9155 | unsigned Reg; | |||
| 9156 | const Value *PHIOp = PN.getIncomingValueForBlock(LLVMBB); | |||
| 9157 | ||||
| 9158 | if (const Constant *C = dyn_cast<Constant>(PHIOp)) { | |||
| 9159 | unsigned &RegOut = ConstantsOut[C]; | |||
| 9160 | if (RegOut == 0) { | |||
| 9161 | RegOut = FuncInfo.CreateRegs(C->getType()); | |||
| 9162 | CopyValueToVirtualRegister(C, RegOut); | |||
| 9163 | } | |||
| 9164 | Reg = RegOut; | |||
| 9165 | } else { | |||
| 9166 | DenseMap<const Value *, unsigned>::iterator I = | |||
| 9167 | FuncInfo.ValueMap.find(PHIOp); | |||
| 9168 | if (I != FuncInfo.ValueMap.end()) | |||
| 9169 | Reg = I->second; | |||
| 9170 | else { | |||
| 9171 | assert(isa<AllocaInst>(PHIOp) &&(static_cast <bool> (isa<AllocaInst>(PHIOp) && FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp) ) && "Didn't codegen value into a register!??") ? void (0) : __assert_fail ("isa<AllocaInst>(PHIOp) && FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) && \"Didn't codegen value into a register!??\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 9173, __extension__ __PRETTY_FUNCTION__)) | |||
| 9172 | FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&(static_cast <bool> (isa<AllocaInst>(PHIOp) && FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp) ) && "Didn't codegen value into a register!??") ? void (0) : __assert_fail ("isa<AllocaInst>(PHIOp) && FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) && \"Didn't codegen value into a register!??\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 9173, __extension__ __PRETTY_FUNCTION__)) | |||
| 9173 | "Didn't codegen value into a register!??")(static_cast <bool> (isa<AllocaInst>(PHIOp) && FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp) ) && "Didn't codegen value into a register!??") ? void (0) : __assert_fail ("isa<AllocaInst>(PHIOp) && FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) && \"Didn't codegen value into a register!??\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 9173, __extension__ __PRETTY_FUNCTION__)); | |||
| 9174 | Reg = FuncInfo.CreateRegs(PHIOp->getType()); | |||
| 9175 | CopyValueToVirtualRegister(PHIOp, Reg); | |||
| 9176 | } | |||
| 9177 | } | |||
| 9178 | ||||
| 9179 | // Remember that this register needs to added to the machine PHI node as | |||
| 9180 | // the input for this MBB. | |||
| 9181 | SmallVector<EVT, 4> ValueVTs; | |||
| 9182 | const TargetLowering &TLI = DAG.getTargetLoweringInfo(); | |||
| 9183 | ComputeValueVTs(TLI, DAG.getDataLayout(), PN.getType(), ValueVTs); | |||
| 9184 | for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) { | |||
| 9185 | EVT VT = ValueVTs[vti]; | |||
| 9186 | unsigned NumRegisters = TLI.getNumRegisters(*DAG.getContext(), VT); | |||
| 9187 | for (unsigned i = 0, e = NumRegisters; i != e; ++i) | |||
| 9188 | FuncInfo.PHINodesToUpdate.push_back( | |||
| 9189 | std::make_pair(&*MBBI++, Reg + i)); | |||
| 9190 | Reg += NumRegisters; | |||
| 9191 | } | |||
| 9192 | } | |||
| 9193 | } | |||
| 9194 | ||||
| 9195 | ConstantsOut.clear(); | |||
| 9196 | } | |||
| 9197 | ||||
| 9198 | /// Add a successor MBB to ParentMBB< creating a new MachineBB for BB if SuccMBB | |||
| 9199 | /// is 0. | |||
| 9200 | MachineBasicBlock * | |||
| 9201 | SelectionDAGBuilder::StackProtectorDescriptor:: | |||
| 9202 | AddSuccessorMBB(const BasicBlock *BB, | |||
| 9203 | MachineBasicBlock *ParentMBB, | |||
| 9204 | bool IsLikely, | |||
| 9205 | MachineBasicBlock *SuccMBB) { | |||
| 9206 | // If SuccBB has not been created yet, create it. | |||
| 9207 | if (!SuccMBB) { | |||
| 9208 | MachineFunction *MF = ParentMBB->getParent(); | |||
| 9209 | MachineFunction::iterator BBI(ParentMBB); | |||
| 9210 | SuccMBB = MF->CreateMachineBasicBlock(BB); | |||
| 9211 | MF->insert(++BBI, SuccMBB); | |||
| 9212 | } | |||
| 9213 | // Add it as a successor of ParentMBB. | |||
| 9214 | ParentMBB->addSuccessor( | |||
| 9215 | SuccMBB, BranchProbabilityInfo::getBranchProbStackProtector(IsLikely)); | |||
| 9216 | return SuccMBB; | |||
| 9217 | } | |||
| 9218 | ||||
| 9219 | MachineBasicBlock *SelectionDAGBuilder::NextBlock(MachineBasicBlock *MBB) { | |||
| 9220 | MachineFunction::iterator I(MBB); | |||
| 9221 | if (++I == FuncInfo.MF->end()) | |||
| 9222 | return nullptr; | |||
| 9223 | return &*I; | |||
| 9224 | } | |||
| 9225 | ||||
| 9226 | /// During lowering new call nodes can be created (such as memset, etc.). | |||
| 9227 | /// Those will become new roots of the current DAG, but complications arise | |||
| 9228 | /// when they are tail calls. In such cases, the call lowering will update | |||
| 9229 | /// the root, but the builder still needs to know that a tail call has been | |||
| 9230 | /// lowered in order to avoid generating an additional return. | |||
| 9231 | void SelectionDAGBuilder::updateDAGForMaybeTailCall(SDValue MaybeTC) { | |||
| 9232 | // If the node is null, we do have a tail call. | |||
| 9233 | if (MaybeTC.getNode() != nullptr) | |||
| 9234 | DAG.setRoot(MaybeTC); | |||
| 9235 | else | |||
| 9236 | HasTailCall = true; | |||
| 9237 | } | |||
| 9238 | ||||
| 9239 | uint64_t | |||
| 9240 | SelectionDAGBuilder::getJumpTableRange(const CaseClusterVector &Clusters, | |||
| 9241 | unsigned First, unsigned Last) const { | |||
| 9242 | assert(Last >= First)(static_cast <bool> (Last >= First) ? void (0) : __assert_fail ("Last >= First", "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 9242, __extension__ __PRETTY_FUNCTION__)); | |||
| 9243 | const APInt &LowCase = Clusters[First].Low->getValue(); | |||
| 9244 | const APInt &HighCase = Clusters[Last].High->getValue(); | |||
| 9245 | assert(LowCase.getBitWidth() == HighCase.getBitWidth())(static_cast <bool> (LowCase.getBitWidth() == HighCase. getBitWidth()) ? void (0) : __assert_fail ("LowCase.getBitWidth() == HighCase.getBitWidth()" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 9245, __extension__ __PRETTY_FUNCTION__)); | |||
| 9246 | ||||
| 9247 | // FIXME: A range of consecutive cases has 100% density, but only requires one | |||
| 9248 | // comparison to lower. We should discriminate against such consecutive ranges | |||
| 9249 | // in jump tables. | |||
| 9250 | ||||
| 9251 | return (HighCase - LowCase).getLimitedValue((UINT64_MAX(18446744073709551615UL) - 1) / 100) + 1; | |||
| 9252 | } | |||
| 9253 | ||||
| 9254 | uint64_t SelectionDAGBuilder::getJumpTableNumCases( | |||
| 9255 | const SmallVectorImpl<unsigned> &TotalCases, unsigned First, | |||
| 9256 | unsigned Last) const { | |||
| 9257 | assert(Last >= First)(static_cast <bool> (Last >= First) ? void (0) : __assert_fail ("Last >= First", "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 9257, __extension__ __PRETTY_FUNCTION__)); | |||
| 9258 | assert(TotalCases[Last] >= TotalCases[First])(static_cast <bool> (TotalCases[Last] >= TotalCases[ First]) ? void (0) : __assert_fail ("TotalCases[Last] >= TotalCases[First]" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 9258, __extension__ __PRETTY_FUNCTION__)); | |||
| 9259 | uint64_t NumCases = | |||
| 9260 | TotalCases[Last] - (First == 0 ? 0 : TotalCases[First - 1]); | |||
| 9261 | return NumCases; | |||
| 9262 | } | |||
| 9263 | ||||
| 9264 | bool SelectionDAGBuilder::buildJumpTable(const CaseClusterVector &Clusters, | |||
| 9265 | unsigned First, unsigned Last, | |||
| 9266 | const SwitchInst *SI, | |||
| 9267 | MachineBasicBlock *DefaultMBB, | |||
| 9268 | CaseCluster &JTCluster) { | |||
| 9269 | assert(First <= Last)(static_cast <bool> (First <= Last) ? void (0) : __assert_fail ("First <= Last", "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 9269, __extension__ __PRETTY_FUNCTION__)); | |||
| 9270 | ||||
| 9271 | auto Prob = BranchProbability::getZero(); | |||
| 9272 | unsigned NumCmps = 0; | |||
| 9273 | std::vector<MachineBasicBlock*> Table; | |||
| 9274 | DenseMap<MachineBasicBlock*, BranchProbability> JTProbs; | |||
| 9275 | ||||
| 9276 | // Initialize probabilities in JTProbs. | |||
| 9277 | for (unsigned I = First; I <= Last; ++I) | |||
| 9278 | JTProbs[Clusters[I].MBB] = BranchProbability::getZero(); | |||
| 9279 | ||||
| 9280 | for (unsigned I = First; I <= Last; ++I) { | |||
| 9281 | assert(Clusters[I].Kind == CC_Range)(static_cast <bool> (Clusters[I].Kind == CC_Range) ? void (0) : __assert_fail ("Clusters[I].Kind == CC_Range", "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 9281, __extension__ __PRETTY_FUNCTION__)); | |||
| 9282 | Prob += Clusters[I].Prob; | |||
| 9283 | const APInt &Low = Clusters[I].Low->getValue(); | |||
| 9284 | const APInt &High = Clusters[I].High->getValue(); | |||
| 9285 | NumCmps += (Low == High) ? 1 : 2; | |||
| 9286 | if (I != First) { | |||
| 9287 | // Fill the gap between this and the previous cluster. | |||
| 9288 | const APInt &PreviousHigh = Clusters[I - 1].High->getValue(); | |||
| 9289 | assert(PreviousHigh.slt(Low))(static_cast <bool> (PreviousHigh.slt(Low)) ? void (0) : __assert_fail ("PreviousHigh.slt(Low)", "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 9289, __extension__ __PRETTY_FUNCTION__)); | |||
| 9290 | uint64_t Gap = (Low - PreviousHigh).getLimitedValue() - 1; | |||
| 9291 | for (uint64_t J = 0; J < Gap; J++) | |||
| 9292 | Table.push_back(DefaultMBB); | |||
| 9293 | } | |||
| 9294 | uint64_t ClusterSize = (High - Low).getLimitedValue() + 1; | |||
| 9295 | for (uint64_t J = 0; J < ClusterSize; ++J) | |||
| 9296 | Table.push_back(Clusters[I].MBB); | |||
| 9297 | JTProbs[Clusters[I].MBB] += Clusters[I].Prob; | |||
| 9298 | } | |||
| 9299 | ||||
| 9300 | const TargetLowering &TLI = DAG.getTargetLoweringInfo(); | |||
| 9301 | unsigned NumDests = JTProbs.size(); | |||
| 9302 | if (TLI.isSuitableForBitTests( | |||
| 9303 | NumDests, NumCmps, Clusters[First].Low->getValue(), | |||
| 9304 | Clusters[Last].High->getValue(), DAG.getDataLayout())) { | |||
| 9305 | // Clusters[First..Last] should be lowered as bit tests instead. | |||
| 9306 | return false; | |||
| 9307 | } | |||
| 9308 | ||||
| 9309 | // Create the MBB that will load from and jump through the table. | |||
| 9310 | // Note: We create it here, but it's not inserted into the function yet. | |||
| 9311 | MachineFunction *CurMF = FuncInfo.MF; | |||
| 9312 | MachineBasicBlock *JumpTableMBB = | |||
| 9313 | CurMF->CreateMachineBasicBlock(SI->getParent()); | |||
| 9314 | ||||
| 9315 | // Add successors. Note: use table order for determinism. | |||
| 9316 | SmallPtrSet<MachineBasicBlock *, 8> Done; | |||
| 9317 | for (MachineBasicBlock *Succ : Table) { | |||
| 9318 | if (Done.count(Succ)) | |||
| 9319 | continue; | |||
| 9320 | addSuccessorWithProb(JumpTableMBB, Succ, JTProbs[Succ]); | |||
| 9321 | Done.insert(Succ); | |||
| 9322 | } | |||
| 9323 | JumpTableMBB->normalizeSuccProbs(); | |||
| 9324 | ||||
| 9325 | unsigned JTI = CurMF->getOrCreateJumpTableInfo(TLI.getJumpTableEncoding()) | |||
| 9326 | ->createJumpTableIndex(Table); | |||
| 9327 | ||||
| 9328 | // Set up the jump table info. | |||
| 9329 | JumpTable JT(-1U, JTI, JumpTableMBB, nullptr); | |||
| 9330 | JumpTableHeader JTH(Clusters[First].Low->getValue(), | |||
| 9331 | Clusters[Last].High->getValue(), SI->getCondition(), | |||
| 9332 | nullptr, false); | |||
| 9333 | JTCases.emplace_back(std::move(JTH), std::move(JT)); | |||
| 9334 | ||||
| 9335 | JTCluster = CaseCluster::jumpTable(Clusters[First].Low, Clusters[Last].High, | |||
| 9336 | JTCases.size() - 1, Prob); | |||
| 9337 | return true; | |||
| 9338 | } | |||
| 9339 | ||||
| 9340 | void SelectionDAGBuilder::findJumpTables(CaseClusterVector &Clusters, | |||
| 9341 | const SwitchInst *SI, | |||
| 9342 | MachineBasicBlock *DefaultMBB) { | |||
| 9343 | #ifndef NDEBUG | |||
| 9344 | // Clusters must be non-empty, sorted, and only contain Range clusters. | |||
| 9345 | assert(!Clusters.empty())(static_cast <bool> (!Clusters.empty()) ? void (0) : __assert_fail ("!Clusters.empty()", "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 9345, __extension__ __PRETTY_FUNCTION__)); | |||
| 9346 | for (CaseCluster &C : Clusters) | |||
| 9347 | assert(C.Kind == CC_Range)(static_cast <bool> (C.Kind == CC_Range) ? void (0) : __assert_fail ("C.Kind == CC_Range", "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 9347, __extension__ __PRETTY_FUNCTION__)); | |||
| 9348 | for (unsigned i = 1, e = Clusters.size(); i < e; ++i) | |||
| 9349 | assert(Clusters[i - 1].High->getValue().slt(Clusters[i].Low->getValue()))(static_cast <bool> (Clusters[i - 1].High->getValue( ).slt(Clusters[i].Low->getValue())) ? void (0) : __assert_fail ("Clusters[i - 1].High->getValue().slt(Clusters[i].Low->getValue())" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 9349, __extension__ __PRETTY_FUNCTION__)); | |||
| 9350 | #endif | |||
| 9351 | ||||
| 9352 | const TargetLowering &TLI = DAG.getTargetLoweringInfo(); | |||
| 9353 | if (!TLI.areJTsAllowed(SI->getParent()->getParent())) | |||
| 9354 | return; | |||
| 9355 | ||||
| 9356 | const int64_t N = Clusters.size(); | |||
| 9357 | const unsigned MinJumpTableEntries = TLI.getMinimumJumpTableEntries(); | |||
| 9358 | const unsigned SmallNumberOfEntries = MinJumpTableEntries / 2; | |||
| 9359 | ||||
| 9360 | if (N < 2 || N < MinJumpTableEntries) | |||
| 9361 | return; | |||
| 9362 | ||||
| 9363 | // TotalCases[i]: Total nbr of cases in Clusters[0..i]. | |||
| 9364 | SmallVector<unsigned, 8> TotalCases(N); | |||
| 9365 | for (unsigned i = 0; i < N; ++i) { | |||
| 9366 | const APInt &Hi = Clusters[i].High->getValue(); | |||
| 9367 | const APInt &Lo = Clusters[i].Low->getValue(); | |||
| 9368 | TotalCases[i] = (Hi - Lo).getLimitedValue() + 1; | |||
| 9369 | if (i != 0) | |||
| 9370 | TotalCases[i] += TotalCases[i - 1]; | |||
| 9371 | } | |||
| 9372 | ||||
| 9373 | // Cheap case: the whole range may be suitable for jump table. | |||
| 9374 | uint64_t Range = getJumpTableRange(Clusters,0, N - 1); | |||
| 9375 | uint64_t NumCases = getJumpTableNumCases(TotalCases, 0, N - 1); | |||
| 9376 | assert(NumCases < UINT64_MAX / 100)(static_cast <bool> (NumCases < (18446744073709551615UL ) / 100) ? void (0) : __assert_fail ("NumCases < UINT64_MAX / 100" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 9376, __extension__ __PRETTY_FUNCTION__)); | |||
| 9377 | assert(Range >= NumCases)(static_cast <bool> (Range >= NumCases) ? void (0) : __assert_fail ("Range >= NumCases", "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 9377, __extension__ __PRETTY_FUNCTION__)); | |||
| 9378 | if (TLI.isSuitableForJumpTable(SI, NumCases, Range)) { | |||
| 9379 | CaseCluster JTCluster; | |||
| 9380 | if (buildJumpTable(Clusters, 0, N - 1, SI, DefaultMBB, JTCluster)) { | |||
| 9381 | Clusters[0] = JTCluster; | |||
| 9382 | Clusters.resize(1); | |||
| 9383 | return; | |||
| 9384 | } | |||
| 9385 | } | |||
| 9386 | ||||
| 9387 | // The algorithm below is not suitable for -O0. | |||
| 9388 | if (TM.getOptLevel() == CodeGenOpt::None) | |||
| 9389 | return; | |||
| 9390 | ||||
| 9391 | // Split Clusters into minimum number of dense partitions. The algorithm uses | |||
| 9392 | // the same idea as Kannan & Proebsting "Correction to 'Producing Good Code | |||
| 9393 | // for the Case Statement'" (1994), but builds the MinPartitions array in | |||
| 9394 | // reverse order to make it easier to reconstruct the partitions in ascending | |||
| 9395 | // order. In the choice between two optimal partitionings, it picks the one | |||
| 9396 | // which yields more jump tables. | |||
| 9397 | ||||
| 9398 | // MinPartitions[i] is the minimum nbr of partitions of Clusters[i..N-1]. | |||
| 9399 | SmallVector<unsigned, 8> MinPartitions(N); | |||
| 9400 | // LastElement[i] is the last element of the partition starting at i. | |||
| 9401 | SmallVector<unsigned, 8> LastElement(N); | |||
| 9402 | // PartitionsScore[i] is used to break ties when choosing between two | |||
| 9403 | // partitionings resulting in the same number of partitions. | |||
| 9404 | SmallVector<unsigned, 8> PartitionsScore(N); | |||
| 9405 | // For PartitionsScore, a small number of comparisons is considered as good as | |||
| 9406 | // a jump table and a single comparison is considered better than a jump | |||
| 9407 | // table. | |||
| 9408 | enum PartitionScores : unsigned { | |||
| 9409 | NoTable = 0, | |||
| 9410 | Table = 1, | |||
| 9411 | FewCases = 1, | |||
| 9412 | SingleCase = 2 | |||
| 9413 | }; | |||
| 9414 | ||||
| 9415 | // Base case: There is only one way to partition Clusters[N-1]. | |||
| 9416 | MinPartitions[N - 1] = 1; | |||
| 9417 | LastElement[N - 1] = N - 1; | |||
| 9418 | PartitionsScore[N - 1] = PartitionScores::SingleCase; | |||
| 9419 | ||||
| 9420 | // Note: loop indexes are signed to avoid underflow. | |||
| 9421 | for (int64_t i = N - 2; i >= 0; i--) { | |||
| 9422 | // Find optimal partitioning of Clusters[i..N-1]. | |||
| 9423 | // Baseline: Put Clusters[i] into a partition on its own. | |||
| 9424 | MinPartitions[i] = MinPartitions[i + 1] + 1; | |||
| 9425 | LastElement[i] = i; | |||
| 9426 | PartitionsScore[i] = PartitionsScore[i + 1] + PartitionScores::SingleCase; | |||
| 9427 | ||||
| 9428 | // Search for a solution that results in fewer partitions. | |||
| 9429 | for (int64_t j = N - 1; j > i; j--) { | |||
| 9430 | // Try building a partition from Clusters[i..j]. | |||
| 9431 | uint64_t Range = getJumpTableRange(Clusters, i, j); | |||
| 9432 | uint64_t NumCases = getJumpTableNumCases(TotalCases, i, j); | |||
| 9433 | assert(NumCases < UINT64_MAX / 100)(static_cast <bool> (NumCases < (18446744073709551615UL ) / 100) ? void (0) : __assert_fail ("NumCases < UINT64_MAX / 100" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 9433, __extension__ __PRETTY_FUNCTION__)); | |||
| 9434 | assert(Range >= NumCases)(static_cast <bool> (Range >= NumCases) ? void (0) : __assert_fail ("Range >= NumCases", "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 9434, __extension__ __PRETTY_FUNCTION__)); | |||
| 9435 | if (TLI.isSuitableForJumpTable(SI, NumCases, Range)) { | |||
| 9436 | unsigned NumPartitions = 1 + (j == N - 1 ? 0 : MinPartitions[j + 1]); | |||
| 9437 | unsigned Score = j == N - 1 ? 0 : PartitionsScore[j + 1]; | |||
| 9438 | int64_t NumEntries = j - i + 1; | |||
| 9439 | ||||
| 9440 | if (NumEntries == 1) | |||
| 9441 | Score += PartitionScores::SingleCase; | |||
| 9442 | else if (NumEntries <= SmallNumberOfEntries) | |||
| 9443 | Score += PartitionScores::FewCases; | |||
| 9444 | else if (NumEntries >= MinJumpTableEntries) | |||
| 9445 | Score += PartitionScores::Table; | |||
| 9446 | ||||
| 9447 | // If this leads to fewer partitions, or to the same number of | |||
| 9448 | // partitions with better score, it is a better partitioning. | |||
| 9449 | if (NumPartitions < MinPartitions[i] || | |||
| 9450 | (NumPartitions == MinPartitions[i] && Score > PartitionsScore[i])) { | |||
| 9451 | MinPartitions[i] = NumPartitions; | |||
| 9452 | LastElement[i] = j; | |||
| 9453 | PartitionsScore[i] = Score; | |||
| 9454 | } | |||
| 9455 | } | |||
| 9456 | } | |||
| 9457 | } | |||
| 9458 | ||||
| 9459 | // Iterate over the partitions, replacing some with jump tables in-place. | |||
| 9460 | unsigned DstIndex = 0; | |||
| 9461 | for (unsigned First = 0, Last; First < N; First = Last + 1) { | |||
| 9462 | Last = LastElement[First]; | |||
| 9463 | assert(Last >= First)(static_cast <bool> (Last >= First) ? void (0) : __assert_fail ("Last >= First", "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 9463, __extension__ __PRETTY_FUNCTION__)); | |||
| 9464 | assert(DstIndex <= First)(static_cast <bool> (DstIndex <= First) ? void (0) : __assert_fail ("DstIndex <= First", "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 9464, __extension__ __PRETTY_FUNCTION__)); | |||
| 9465 | unsigned NumClusters = Last - First + 1; | |||
| 9466 | ||||
| 9467 | CaseCluster JTCluster; | |||
| 9468 | if (NumClusters >= MinJumpTableEntries && | |||
| 9469 | buildJumpTable(Clusters, First, Last, SI, DefaultMBB, JTCluster)) { | |||
| 9470 | Clusters[DstIndex++] = JTCluster; | |||
| 9471 | } else { | |||
| 9472 | for (unsigned I = First; I <= Last; ++I) | |||
| 9473 | std::memmove(&Clusters[DstIndex++], &Clusters[I], sizeof(Clusters[I])); | |||
| 9474 | } | |||
| 9475 | } | |||
| 9476 | Clusters.resize(DstIndex); | |||
| 9477 | } | |||
| 9478 | ||||
| 9479 | bool SelectionDAGBuilder::buildBitTests(CaseClusterVector &Clusters, | |||
| 9480 | unsigned First, unsigned Last, | |||
| 9481 | const SwitchInst *SI, | |||
| 9482 | CaseCluster &BTCluster) { | |||
| 9483 | assert(First <= Last)(static_cast <bool> (First <= Last) ? void (0) : __assert_fail ("First <= Last", "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 9483, __extension__ __PRETTY_FUNCTION__)); | |||
| 9484 | if (First == Last) | |||
| 9485 | return false; | |||
| 9486 | ||||
| 9487 | BitVector Dests(FuncInfo.MF->getNumBlockIDs()); | |||
| 9488 | unsigned NumCmps = 0; | |||
| 9489 | for (int64_t I = First; I <= Last; ++I) { | |||
| 9490 | assert(Clusters[I].Kind == CC_Range)(static_cast <bool> (Clusters[I].Kind == CC_Range) ? void (0) : __assert_fail ("Clusters[I].Kind == CC_Range", "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 9490, __extension__ __PRETTY_FUNCTION__)); | |||
| 9491 | Dests.set(Clusters[I].MBB->getNumber()); | |||
| 9492 | NumCmps += (Clusters[I].Low == Clusters[I].High) ? 1 : 2; | |||
| 9493 | } | |||
| 9494 | unsigned NumDests = Dests.count(); | |||
| 9495 | ||||
| 9496 | APInt Low = Clusters[First].Low->getValue(); | |||
| 9497 | APInt High = Clusters[Last].High->getValue(); | |||
| 9498 | assert(Low.slt(High))(static_cast <bool> (Low.slt(High)) ? void (0) : __assert_fail ("Low.slt(High)", "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 9498, __extension__ __PRETTY_FUNCTION__)); | |||
| 9499 | ||||
| 9500 | const TargetLowering &TLI = DAG.getTargetLoweringInfo(); | |||
| 9501 | const DataLayout &DL = DAG.getDataLayout(); | |||
| 9502 | if (!TLI.isSuitableForBitTests(NumDests, NumCmps, Low, High, DL)) | |||
| 9503 | return false; | |||
| 9504 | ||||
| 9505 | APInt LowBound; | |||
| 9506 | APInt CmpRange; | |||
| 9507 | ||||
| 9508 | const int BitWidth = TLI.getPointerTy(DL).getSizeInBits(); | |||
| 9509 | assert(TLI.rangeFitsInWord(Low, High, DL) &&(static_cast <bool> (TLI.rangeFitsInWord(Low, High, DL) && "Case range must fit in bit mask!") ? void (0) : __assert_fail ("TLI.rangeFitsInWord(Low, High, DL) && \"Case range must fit in bit mask!\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 9510, __extension__ __PRETTY_FUNCTION__)) | |||
| 9510 | "Case range must fit in bit mask!")(static_cast <bool> (TLI.rangeFitsInWord(Low, High, DL) && "Case range must fit in bit mask!") ? void (0) : __assert_fail ("TLI.rangeFitsInWord(Low, High, DL) && \"Case range must fit in bit mask!\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 9510, __extension__ __PRETTY_FUNCTION__)); | |||
| 9511 | ||||
| 9512 | // Check if the clusters cover a contiguous range such that no value in the | |||
| 9513 | // range will jump to the default statement. | |||
| 9514 | bool ContiguousRange = true; | |||
| 9515 | for (int64_t I = First + 1; I <= Last; ++I) { | |||
| 9516 | if (Clusters[I].Low->getValue() != Clusters[I - 1].High->getValue() + 1) { | |||
| 9517 | ContiguousRange = false; | |||
| 9518 | break; | |||
| 9519 | } | |||
| 9520 | } | |||
| 9521 | ||||
| 9522 | if (Low.isStrictlyPositive() && High.slt(BitWidth)) { | |||
| 9523 | // Optimize the case where all the case values fit in a word without having | |||
| 9524 | // to subtract minValue. In this case, we can optimize away the subtraction. | |||
| 9525 | LowBound = APInt::getNullValue(Low.getBitWidth()); | |||
| 9526 | CmpRange = High; | |||
| 9527 | ContiguousRange = false; | |||
| 9528 | } else { | |||
| 9529 | LowBound = Low; | |||
| 9530 | CmpRange = High - Low; | |||
| 9531 | } | |||
| 9532 | ||||
| 9533 | CaseBitsVector CBV; | |||
| 9534 | auto TotalProb = BranchProbability::getZero(); | |||
| 9535 | for (unsigned i = First; i <= Last; ++i) { | |||
| 9536 | // Find the CaseBits for this destination. | |||
| 9537 | unsigned j; | |||
| 9538 | for (j = 0; j < CBV.size(); ++j) | |||
| 9539 | if (CBV[j].BB == Clusters[i].MBB) | |||
| 9540 | break; | |||
| 9541 | if (j == CBV.size()) | |||
| 9542 | CBV.push_back( | |||
| 9543 | CaseBits(0, Clusters[i].MBB, 0, BranchProbability::getZero())); | |||
| 9544 | CaseBits *CB = &CBV[j]; | |||
| 9545 | ||||
| 9546 | // Update Mask, Bits and ExtraProb. | |||
| 9547 | uint64_t Lo = (Clusters[i].Low->getValue() - LowBound).getZExtValue(); | |||
| 9548 | uint64_t Hi = (Clusters[i].High->getValue() - LowBound).getZExtValue(); | |||
| 9549 | assert(Hi >= Lo && Hi < 64 && "Invalid bit case!")(static_cast <bool> (Hi >= Lo && Hi < 64 && "Invalid bit case!") ? void (0) : __assert_fail ("Hi >= Lo && Hi < 64 && \"Invalid bit case!\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 9549, __extension__ __PRETTY_FUNCTION__)); | |||
| 9550 | CB->Mask |= (-1ULL >> (63 - (Hi - Lo))) << Lo; | |||
| 9551 | CB->Bits += Hi - Lo + 1; | |||
| 9552 | CB->ExtraProb += Clusters[i].Prob; | |||
| 9553 | TotalProb += Clusters[i].Prob; | |||
| 9554 | } | |||
| 9555 | ||||
| 9556 | BitTestInfo BTI; | |||
| 9557 | llvm::sort(CBV.begin(), CBV.end(), [](const CaseBits &a, const CaseBits &b) { | |||
| 9558 | // Sort by probability first, number of bits second, bit mask third. | |||
| 9559 | if (a.ExtraProb != b.ExtraProb) | |||
| 9560 | return a.ExtraProb > b.ExtraProb; | |||
| 9561 | if (a.Bits != b.Bits) | |||
| 9562 | return a.Bits > b.Bits; | |||
| 9563 | return a.Mask < b.Mask; | |||
| 9564 | }); | |||
| 9565 | ||||
| 9566 | for (auto &CB : CBV) { | |||
| 9567 | MachineBasicBlock *BitTestBB = | |||
| 9568 | FuncInfo.MF->CreateMachineBasicBlock(SI->getParent()); | |||
| 9569 | BTI.push_back(BitTestCase(CB.Mask, BitTestBB, CB.BB, CB.ExtraProb)); | |||
| 9570 | } | |||
| 9571 | BitTestCases.emplace_back(std::move(LowBound), std::move(CmpRange), | |||
| 9572 | SI->getCondition(), -1U, MVT::Other, false, | |||
| 9573 | ContiguousRange, nullptr, nullptr, std::move(BTI), | |||
| 9574 | TotalProb); | |||
| 9575 | ||||
| 9576 | BTCluster = CaseCluster::bitTests(Clusters[First].Low, Clusters[Last].High, | |||
| 9577 | BitTestCases.size() - 1, TotalProb); | |||
| 9578 | return true; | |||
| 9579 | } | |||
| 9580 | ||||
| 9581 | void SelectionDAGBuilder::findBitTestClusters(CaseClusterVector &Clusters, | |||
| 9582 | const SwitchInst *SI) { | |||
| 9583 | // Partition Clusters into as few subsets as possible, where each subset has a | |||
| 9584 | // range that fits in a machine word and has <= 3 unique destinations. | |||
| 9585 | ||||
| 9586 | #ifndef NDEBUG | |||
| 9587 | // Clusters must be sorted and contain Range or JumpTable clusters. | |||
| 9588 | assert(!Clusters.empty())(static_cast <bool> (!Clusters.empty()) ? void (0) : __assert_fail ("!Clusters.empty()", "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 9588, __extension__ __PRETTY_FUNCTION__)); | |||
| 9589 | assert(Clusters[0].Kind == CC_Range || Clusters[0].Kind == CC_JumpTable)(static_cast <bool> (Clusters[0].Kind == CC_Range || Clusters [0].Kind == CC_JumpTable) ? void (0) : __assert_fail ("Clusters[0].Kind == CC_Range || Clusters[0].Kind == CC_JumpTable" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 9589, __extension__ __PRETTY_FUNCTION__)); | |||
| 9590 | for (const CaseCluster &C : Clusters) | |||
| 9591 | assert(C.Kind == CC_Range || C.Kind == CC_JumpTable)(static_cast <bool> (C.Kind == CC_Range || C.Kind == CC_JumpTable ) ? void (0) : __assert_fail ("C.Kind == CC_Range || C.Kind == CC_JumpTable" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 9591, __extension__ __PRETTY_FUNCTION__)); | |||
| 9592 | for (unsigned i = 1; i < Clusters.size(); ++i) | |||
| 9593 | assert(Clusters[i-1].High->getValue().slt(Clusters[i].Low->getValue()))(static_cast <bool> (Clusters[i-1].High->getValue(). slt(Clusters[i].Low->getValue())) ? void (0) : __assert_fail ("Clusters[i-1].High->getValue().slt(Clusters[i].Low->getValue())" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 9593, __extension__ __PRETTY_FUNCTION__)); | |||
| 9594 | #endif | |||
| 9595 | ||||
| 9596 | // The algorithm below is not suitable for -O0. | |||
| 9597 | if (TM.getOptLevel() == CodeGenOpt::None) | |||
| 9598 | return; | |||
| 9599 | ||||
| 9600 | // If target does not have legal shift left, do not emit bit tests at all. | |||
| 9601 | const TargetLowering &TLI = DAG.getTargetLoweringInfo(); | |||
| 9602 | const DataLayout &DL = DAG.getDataLayout(); | |||
| 9603 | ||||
| 9604 | EVT PTy = TLI.getPointerTy(DL); | |||
| 9605 | if (!TLI.isOperationLegal(ISD::SHL, PTy)) | |||
| 9606 | return; | |||
| 9607 | ||||
| 9608 | int BitWidth = PTy.getSizeInBits(); | |||
| 9609 | const int64_t N = Clusters.size(); | |||
| 9610 | ||||
| 9611 | // MinPartitions[i] is the minimum nbr of partitions of Clusters[i..N-1]. | |||
| 9612 | SmallVector<unsigned, 8> MinPartitions(N); | |||
| 9613 | // LastElement[i] is the last element of the partition starting at i. | |||
| 9614 | SmallVector<unsigned, 8> LastElement(N); | |||
| 9615 | ||||
| 9616 | // FIXME: This might not be the best algorithm for finding bit test clusters. | |||
| 9617 | ||||
| 9618 | // Base case: There is only one way to partition Clusters[N-1]. | |||
| 9619 | MinPartitions[N - 1] = 1; | |||
| 9620 | LastElement[N - 1] = N - 1; | |||
| 9621 | ||||
| 9622 | // Note: loop indexes are signed to avoid underflow. | |||
| 9623 | for (int64_t i = N - 2; i >= 0; --i) { | |||
| 9624 | // Find optimal partitioning of Clusters[i..N-1]. | |||
| 9625 | // Baseline: Put Clusters[i] into a partition on its own. | |||
| 9626 | MinPartitions[i] = MinPartitions[i + 1] + 1; | |||
| 9627 | LastElement[i] = i; | |||
| 9628 | ||||
| 9629 | // Search for a solution that results in fewer partitions. | |||
| 9630 | // Note: the search is limited by BitWidth, reducing time complexity. | |||
| 9631 | for (int64_t j = std::min(N - 1, i + BitWidth - 1); j > i; --j) { | |||
| 9632 | // Try building a partition from Clusters[i..j]. | |||
| 9633 | ||||
| 9634 | // Check the range. | |||
| 9635 | if (!TLI.rangeFitsInWord(Clusters[i].Low->getValue(), | |||
| 9636 | Clusters[j].High->getValue(), DL)) | |||
| 9637 | continue; | |||
| 9638 | ||||
| 9639 | // Check nbr of destinations and cluster types. | |||
| 9640 | // FIXME: This works, but doesn't seem very efficient. | |||
| 9641 | bool RangesOnly = true; | |||
| 9642 | BitVector Dests(FuncInfo.MF->getNumBlockIDs()); | |||
| 9643 | for (int64_t k = i; k <= j; k++) { | |||
| 9644 | if (Clusters[k].Kind != CC_Range) { | |||
| 9645 | RangesOnly = false; | |||
| 9646 | break; | |||
| 9647 | } | |||
| 9648 | Dests.set(Clusters[k].MBB->getNumber()); | |||
| 9649 | } | |||
| 9650 | if (!RangesOnly || Dests.count() > 3) | |||
| 9651 | break; | |||
| 9652 | ||||
| 9653 | // Check if it's a better partition. | |||
| 9654 | unsigned NumPartitions = 1 + (j == N - 1 ? 0 : MinPartitions[j + 1]); | |||
| 9655 | if (NumPartitions < MinPartitions[i]) { | |||
| 9656 | // Found a better partition. | |||
| 9657 | MinPartitions[i] = NumPartitions; | |||
| 9658 | LastElement[i] = j; | |||
| 9659 | } | |||
| 9660 | } | |||
| 9661 | } | |||
| 9662 | ||||
| 9663 | // Iterate over the partitions, replacing with bit-test clusters in-place. | |||
| 9664 | unsigned DstIndex = 0; | |||
| 9665 | for (unsigned First = 0, Last; First < N; First = Last + 1) { | |||
| 9666 | Last = LastElement[First]; | |||
| 9667 | assert(First <= Last)(static_cast <bool> (First <= Last) ? void (0) : __assert_fail ("First <= Last", "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 9667, __extension__ __PRETTY_FUNCTION__)); | |||
| 9668 | assert(DstIndex <= First)(static_cast <bool> (DstIndex <= First) ? void (0) : __assert_fail ("DstIndex <= First", "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 9668, __extension__ __PRETTY_FUNCTION__)); | |||
| 9669 | ||||
| 9670 | CaseCluster BitTestCluster; | |||
| 9671 | if (buildBitTests(Clusters, First, Last, SI, BitTestCluster)) { | |||
| 9672 | Clusters[DstIndex++] = BitTestCluster; | |||
| 9673 | } else { | |||
| 9674 | size_t NumClusters = Last - First + 1; | |||
| 9675 | std::memmove(&Clusters[DstIndex], &Clusters[First], | |||
| 9676 | sizeof(Clusters[0]) * NumClusters); | |||
| 9677 | DstIndex += NumClusters; | |||
| 9678 | } | |||
| 9679 | } | |||
| 9680 | Clusters.resize(DstIndex); | |||
| 9681 | } | |||
| 9682 | ||||
| 9683 | void SelectionDAGBuilder::lowerWorkItem(SwitchWorkListItem W, Value *Cond, | |||
| 9684 | MachineBasicBlock *SwitchMBB, | |||
| 9685 | MachineBasicBlock *DefaultMBB) { | |||
| 9686 | MachineFunction *CurMF = FuncInfo.MF; | |||
| 9687 | MachineBasicBlock *NextMBB = nullptr; | |||
| 9688 | MachineFunction::iterator BBI(W.MBB); | |||
| 9689 | if (++BBI != FuncInfo.MF->end()) | |||
| 9690 | NextMBB = &*BBI; | |||
| 9691 | ||||
| 9692 | unsigned Size = W.LastCluster - W.FirstCluster + 1; | |||
| 9693 | ||||
| 9694 | BranchProbabilityInfo *BPI = FuncInfo.BPI; | |||
| 9695 | ||||
| 9696 | if (Size == 2 && W.MBB == SwitchMBB) { | |||
| 9697 | // If any two of the cases has the same destination, and if one value | |||
| 9698 | // is the same as the other, but has one bit unset that the other has set, | |||
| 9699 | // use bit manipulation to do two compares at once. For example: | |||
| 9700 | // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)" | |||
| 9701 | // TODO: This could be extended to merge any 2 cases in switches with 3 | |||
| 9702 | // cases. | |||
| 9703 | // TODO: Handle cases where W.CaseBB != SwitchBB. | |||
| 9704 | CaseCluster &Small = *W.FirstCluster; | |||
| 9705 | CaseCluster &Big = *W.LastCluster; | |||
| 9706 | ||||
| 9707 | if (Small.Low == Small.High && Big.Low == Big.High && | |||
| 9708 | Small.MBB == Big.MBB) { | |||
| 9709 | const APInt &SmallValue = Small.Low->getValue(); | |||
| 9710 | const APInt &BigValue = Big.Low->getValue(); | |||
| 9711 | ||||
| 9712 | // Check that there is only one bit different. | |||
| 9713 | APInt CommonBit = BigValue ^ SmallValue; | |||
| 9714 | if (CommonBit.isPowerOf2()) { | |||
| 9715 | SDValue CondLHS = getValue(Cond); | |||
| 9716 | EVT VT = CondLHS.getValueType(); | |||
| 9717 | SDLoc DL = getCurSDLoc(); | |||
| 9718 | ||||
| 9719 | SDValue Or = DAG.getNode(ISD::OR, DL, VT, CondLHS, | |||
| 9720 | DAG.getConstant(CommonBit, DL, VT)); | |||
| 9721 | SDValue Cond = DAG.getSetCC( | |||
| 9722 | DL, MVT::i1, Or, DAG.getConstant(BigValue | SmallValue, DL, VT), | |||
| 9723 | ISD::SETEQ); | |||
| 9724 | ||||
| 9725 | // Update successor info. | |||
| 9726 | // Both Small and Big will jump to Small.BB, so we sum up the | |||
| 9727 | // probabilities. | |||
| 9728 | addSuccessorWithProb(SwitchMBB, Small.MBB, Small.Prob + Big.Prob); | |||
| 9729 | if (BPI) | |||
| 9730 | addSuccessorWithProb( | |||
| 9731 | SwitchMBB, DefaultMBB, | |||
| 9732 | // The default destination is the first successor in IR. | |||
| 9733 | BPI->getEdgeProbability(SwitchMBB->getBasicBlock(), (unsigned)0)); | |||
| 9734 | else | |||
| 9735 | addSuccessorWithProb(SwitchMBB, DefaultMBB); | |||
| 9736 | ||||
| 9737 | // Insert the true branch. | |||
| 9738 | SDValue BrCond = | |||
| 9739 | DAG.getNode(ISD::BRCOND, DL, MVT::Other, getControlRoot(), Cond, | |||
| 9740 | DAG.getBasicBlock(Small.MBB)); | |||
| 9741 | // Insert the false branch. | |||
| 9742 | BrCond = DAG.getNode(ISD::BR, DL, MVT::Other, BrCond, | |||
| 9743 | DAG.getBasicBlock(DefaultMBB)); | |||
| 9744 | ||||
| 9745 | DAG.setRoot(BrCond); | |||
| 9746 | return; | |||
| 9747 | } | |||
| 9748 | } | |||
| 9749 | } | |||
| 9750 | ||||
| 9751 | if (TM.getOptLevel() != CodeGenOpt::None) { | |||
| 9752 | // Here, we order cases by probability so the most likely case will be | |||
| 9753 | // checked first. However, two clusters can have the same probability in | |||
| 9754 | // which case their relative ordering is non-deterministic. So we use Low | |||
| 9755 | // as a tie-breaker as clusters are guaranteed to never overlap. | |||
| 9756 | llvm::sort(W.FirstCluster, W.LastCluster + 1, | |||
| 9757 | [](const CaseCluster &a, const CaseCluster &b) { | |||
| 9758 | return a.Prob != b.Prob ? | |||
| 9759 | a.Prob > b.Prob : | |||
| 9760 | a.Low->getValue().slt(b.Low->getValue()); | |||
| 9761 | }); | |||
| 9762 | ||||
| 9763 | // Rearrange the case blocks so that the last one falls through if possible | |||
| 9764 | // without changing the order of probabilities. | |||
| 9765 | for (CaseClusterIt I = W.LastCluster; I > W.FirstCluster; ) { | |||
| 9766 | --I; | |||
| 9767 | if (I->Prob > W.LastCluster->Prob) | |||
| 9768 | break; | |||
| 9769 | if (I->Kind == CC_Range && I->MBB == NextMBB) { | |||
| 9770 | std::swap(*I, *W.LastCluster); | |||
| 9771 | break; | |||
| 9772 | } | |||
| 9773 | } | |||
| 9774 | } | |||
| 9775 | ||||
| 9776 | // Compute total probability. | |||
| 9777 | BranchProbability DefaultProb = W.DefaultProb; | |||
| 9778 | BranchProbability UnhandledProbs = DefaultProb; | |||
| 9779 | for (CaseClusterIt I = W.FirstCluster; I <= W.LastCluster; ++I) | |||
| 9780 | UnhandledProbs += I->Prob; | |||
| 9781 | ||||
| 9782 | MachineBasicBlock *CurMBB = W.MBB; | |||
| 9783 | for (CaseClusterIt I = W.FirstCluster, E = W.LastCluster; I <= E; ++I) { | |||
| 9784 | MachineBasicBlock *Fallthrough; | |||
| 9785 | if (I == W.LastCluster) { | |||
| 9786 | // For the last cluster, fall through to the default destination. | |||
| 9787 | Fallthrough = DefaultMBB; | |||
| 9788 | } else { | |||
| 9789 | Fallthrough = CurMF->CreateMachineBasicBlock(CurMBB->getBasicBlock()); | |||
| 9790 | CurMF->insert(BBI, Fallthrough); | |||
| 9791 | // Put Cond in a virtual register to make it available from the new blocks. | |||
| 9792 | ExportFromCurrentBlock(Cond); | |||
| 9793 | } | |||
| 9794 | UnhandledProbs -= I->Prob; | |||
| 9795 | ||||
| 9796 | switch (I->Kind) { | |||
| 9797 | case CC_JumpTable: { | |||
| 9798 | // FIXME: Optimize away range check based on pivot comparisons. | |||
| 9799 | JumpTableHeader *JTH = &JTCases[I->JTCasesIndex].first; | |||
| 9800 | JumpTable *JT = &JTCases[I->JTCasesIndex].second; | |||
| 9801 | ||||
| 9802 | // The jump block hasn't been inserted yet; insert it here. | |||
| 9803 | MachineBasicBlock *JumpMBB = JT->MBB; | |||
| 9804 | CurMF->insert(BBI, JumpMBB); | |||
| 9805 | ||||
| 9806 | auto JumpProb = I->Prob; | |||
| 9807 | auto FallthroughProb = UnhandledProbs; | |||
| 9808 | ||||
| 9809 | // If the default statement is a target of the jump table, we evenly | |||
| 9810 | // distribute the default probability to successors of CurMBB. Also | |||
| 9811 | // update the probability on the edge from JumpMBB to Fallthrough. | |||
| 9812 | for (MachineBasicBlock::succ_iterator SI = JumpMBB->succ_begin(), | |||
| 9813 | SE = JumpMBB->succ_end(); | |||
| 9814 | SI != SE; ++SI) { | |||
| 9815 | if (*SI == DefaultMBB) { | |||
| 9816 | JumpProb += DefaultProb / 2; | |||
| 9817 | FallthroughProb -= DefaultProb / 2; | |||
| 9818 | JumpMBB->setSuccProbability(SI, DefaultProb / 2); | |||
| 9819 | JumpMBB->normalizeSuccProbs(); | |||
| 9820 | break; | |||
| 9821 | } | |||
| 9822 | } | |||
| 9823 | ||||
| 9824 | addSuccessorWithProb(CurMBB, Fallthrough, FallthroughProb); | |||
| 9825 | addSuccessorWithProb(CurMBB, JumpMBB, JumpProb); | |||
| 9826 | CurMBB->normalizeSuccProbs(); | |||
| 9827 | ||||
| 9828 | // The jump table header will be inserted in our current block, do the | |||
| 9829 | // range check, and fall through to our fallthrough block. | |||
| 9830 | JTH->HeaderBB = CurMBB; | |||
| 9831 | JT->Default = Fallthrough; // FIXME: Move Default to JumpTableHeader. | |||
| 9832 | ||||
| 9833 | // If we're in the right place, emit the jump table header right now. | |||
| 9834 | if (CurMBB == SwitchMBB) { | |||
| 9835 | visitJumpTableHeader(*JT, *JTH, SwitchMBB); | |||
| 9836 | JTH->Emitted = true; | |||
| 9837 | } | |||
| 9838 | break; | |||
| 9839 | } | |||
| 9840 | case CC_BitTests: { | |||
| 9841 | // FIXME: Optimize away range check based on pivot comparisons. | |||
| 9842 | BitTestBlock *BTB = &BitTestCases[I->BTCasesIndex]; | |||
| 9843 | ||||
| 9844 | // The bit test blocks haven't been inserted yet; insert them here. | |||
| 9845 | for (BitTestCase &BTC : BTB->Cases) | |||
| 9846 | CurMF->insert(BBI, BTC.ThisBB); | |||
| 9847 | ||||
| 9848 | // Fill in fields of the BitTestBlock. | |||
| 9849 | BTB->Parent = CurMBB; | |||
| 9850 | BTB->Default = Fallthrough; | |||
| 9851 | ||||
| 9852 | BTB->DefaultProb = UnhandledProbs; | |||
| 9853 | // If the cases in bit test don't form a contiguous range, we evenly | |||
| 9854 | // distribute the probability on the edge to Fallthrough to two | |||
| 9855 | // successors of CurMBB. | |||
| 9856 | if (!BTB->ContiguousRange) { | |||
| 9857 | BTB->Prob += DefaultProb / 2; | |||
| 9858 | BTB->DefaultProb -= DefaultProb / 2; | |||
| 9859 | } | |||
| 9860 | ||||
| 9861 | // If we're in the right place, emit the bit test header right now. | |||
| 9862 | if (CurMBB == SwitchMBB) { | |||
| 9863 | visitBitTestHeader(*BTB, SwitchMBB); | |||
| 9864 | BTB->Emitted = true; | |||
| 9865 | } | |||
| 9866 | break; | |||
| 9867 | } | |||
| 9868 | case CC_Range: { | |||
| 9869 | const Value *RHS, *LHS, *MHS; | |||
| 9870 | ISD::CondCode CC; | |||
| 9871 | if (I->Low == I->High) { | |||
| 9872 | // Check Cond == I->Low. | |||
| 9873 | CC = ISD::SETEQ; | |||
| 9874 | LHS = Cond; | |||
| 9875 | RHS=I->Low; | |||
| 9876 | MHS = nullptr; | |||
| 9877 | } else { | |||
| 9878 | // Check I->Low <= Cond <= I->High. | |||
| 9879 | CC = ISD::SETLE; | |||
| 9880 | LHS = I->Low; | |||
| 9881 | MHS = Cond; | |||
| 9882 | RHS = I->High; | |||
| 9883 | } | |||
| 9884 | ||||
| 9885 | // The false probability is the sum of all unhandled cases. | |||
| 9886 | CaseBlock CB(CC, LHS, RHS, MHS, I->MBB, Fallthrough, CurMBB, | |||
| 9887 | getCurSDLoc(), I->Prob, UnhandledProbs); | |||
| 9888 | ||||
| 9889 | if (CurMBB == SwitchMBB) | |||
| 9890 | visitSwitchCase(CB, SwitchMBB); | |||
| 9891 | else | |||
| 9892 | SwitchCases.push_back(CB); | |||
| 9893 | ||||
| 9894 | break; | |||
| 9895 | } | |||
| 9896 | } | |||
| 9897 | CurMBB = Fallthrough; | |||
| 9898 | } | |||
| 9899 | } | |||
| 9900 | ||||
| 9901 | unsigned SelectionDAGBuilder::caseClusterRank(const CaseCluster &CC, | |||
| 9902 | CaseClusterIt First, | |||
| 9903 | CaseClusterIt Last) { | |||
| 9904 | return std::count_if(First, Last + 1, [&](const CaseCluster &X) { | |||
| 9905 | if (X.Prob != CC.Prob) | |||
| 9906 | return X.Prob > CC.Prob; | |||
| 9907 | ||||
| 9908 | // Ties are broken by comparing the case value. | |||
| 9909 | return X.Low->getValue().slt(CC.Low->getValue()); | |||
| 9910 | }); | |||
| 9911 | } | |||
| 9912 | ||||
| 9913 | void SelectionDAGBuilder::splitWorkItem(SwitchWorkList &WorkList, | |||
| 9914 | const SwitchWorkListItem &W, | |||
| 9915 | Value *Cond, | |||
| 9916 | MachineBasicBlock *SwitchMBB) { | |||
| 9917 | assert(W.FirstCluster->Low->getValue().slt(W.LastCluster->Low->getValue()) &&(static_cast <bool> (W.FirstCluster->Low->getValue ().slt(W.LastCluster->Low->getValue()) && "Clusters not sorted?" ) ? void (0) : __assert_fail ("W.FirstCluster->Low->getValue().slt(W.LastCluster->Low->getValue()) && \"Clusters not sorted?\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 9918, __extension__ __PRETTY_FUNCTION__)) | |||
| 9918 | "Clusters not sorted?")(static_cast <bool> (W.FirstCluster->Low->getValue ().slt(W.LastCluster->Low->getValue()) && "Clusters not sorted?" ) ? void (0) : __assert_fail ("W.FirstCluster->Low->getValue().slt(W.LastCluster->Low->getValue()) && \"Clusters not sorted?\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 9918, __extension__ __PRETTY_FUNCTION__)); | |||
| 9919 | ||||
| 9920 | assert(W.LastCluster - W.FirstCluster + 1 >= 2 && "Too small to split!")(static_cast <bool> (W.LastCluster - W.FirstCluster + 1 >= 2 && "Too small to split!") ? void (0) : __assert_fail ("W.LastCluster - W.FirstCluster + 1 >= 2 && \"Too small to split!\"" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 9920, __extension__ __PRETTY_FUNCTION__)); | |||
| 9921 | ||||
| 9922 | // Balance the tree based on branch probabilities to create a near-optimal (in | |||
| 9923 | // terms of search time given key frequency) binary search tree. See e.g. Kurt | |||
| 9924 | // Mehlhorn "Nearly Optimal Binary Search Trees" (1975). | |||
| 9925 | CaseClusterIt LastLeft = W.FirstCluster; | |||
| 9926 | CaseClusterIt FirstRight = W.LastCluster; | |||
| 9927 | auto LeftProb = LastLeft->Prob + W.DefaultProb / 2; | |||
| 9928 | auto RightProb = FirstRight->Prob + W.DefaultProb / 2; | |||
| 9929 | ||||
| 9930 | // Move LastLeft and FirstRight towards each other from opposite directions to | |||
| 9931 | // find a partitioning of the clusters which balances the probability on both | |||
| 9932 | // sides. If LeftProb and RightProb are equal, alternate which side is | |||
| 9933 | // taken to ensure 0-probability nodes are distributed evenly. | |||
| 9934 | unsigned I = 0; | |||
| 9935 | while (LastLeft + 1 < FirstRight) { | |||
| 9936 | if (LeftProb < RightProb || (LeftProb == RightProb && (I & 1))) | |||
| 9937 | LeftProb += (++LastLeft)->Prob; | |||
| 9938 | else | |||
| 9939 | RightProb += (--FirstRight)->Prob; | |||
| 9940 | I++; | |||
| 9941 | } | |||
| 9942 | ||||
| 9943 | while (true) { | |||
| 9944 | // Our binary search tree differs from a typical BST in that ours can have up | |||
| 9945 | // to three values in each leaf. The pivot selection above doesn't take that | |||
| 9946 | // into account, which means the tree might require more nodes and be less | |||
| 9947 | // efficient. We compensate for this here. | |||
| 9948 | ||||
| 9949 | unsigned NumLeft = LastLeft - W.FirstCluster + 1; | |||
| 9950 | unsigned NumRight = W.LastCluster - FirstRight + 1; | |||
| 9951 | ||||
| 9952 | if (std::min(NumLeft, NumRight) < 3 && std::max(NumLeft, NumRight) > 3) { | |||
| 9953 | // If one side has less than 3 clusters, and the other has more than 3, | |||
| 9954 | // consider taking a cluster from the other side. | |||
| 9955 | ||||
| 9956 | if (NumLeft < NumRight) { | |||
| 9957 | // Consider moving the first cluster on the right to the left side. | |||
| 9958 | CaseCluster &CC = *FirstRight; | |||
| 9959 | unsigned RightSideRank = caseClusterRank(CC, FirstRight, W.LastCluster); | |||
| 9960 | unsigned LeftSideRank = caseClusterRank(CC, W.FirstCluster, LastLeft); | |||
| 9961 | if (LeftSideRank <= RightSideRank) { | |||
| 9962 | // Moving the cluster to the left does not demote it. | |||
| 9963 | ++LastLeft; | |||
| 9964 | ++FirstRight; | |||
| 9965 | continue; | |||
| 9966 | } | |||
| 9967 | } else { | |||
| 9968 | assert(NumRight < NumLeft)(static_cast <bool> (NumRight < NumLeft) ? void (0) : __assert_fail ("NumRight < NumLeft", "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 9968, __extension__ __PRETTY_FUNCTION__)); | |||
| 9969 | // Consider moving the last element on the left to the right side. | |||
| 9970 | CaseCluster &CC = *LastLeft; | |||
| 9971 | unsigned LeftSideRank = caseClusterRank(CC, W.FirstCluster, LastLeft); | |||
| 9972 | unsigned RightSideRank = caseClusterRank(CC, FirstRight, W.LastCluster); | |||
| 9973 | if (RightSideRank <= LeftSideRank) { | |||
| 9974 | // Moving the cluster to the right does not demot it. | |||
| 9975 | --LastLeft; | |||
| 9976 | --FirstRight; | |||
| 9977 | continue; | |||
| 9978 | } | |||
| 9979 | } | |||
| 9980 | } | |||
| 9981 | break; | |||
| 9982 | } | |||
| 9983 | ||||
| 9984 | assert(LastLeft + 1 == FirstRight)(static_cast <bool> (LastLeft + 1 == FirstRight) ? void (0) : __assert_fail ("LastLeft + 1 == FirstRight", "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 9984, __extension__ __PRETTY_FUNCTION__)); | |||
| 9985 | assert(LastLeft >= W.FirstCluster)(static_cast <bool> (LastLeft >= W.FirstCluster) ? void (0) : __assert_fail ("LastLeft >= W.FirstCluster", "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 9985, __extension__ __PRETTY_FUNCTION__)); | |||
| 9986 | assert(FirstRight <= W.LastCluster)(static_cast <bool> (FirstRight <= W.LastCluster) ? void (0) : __assert_fail ("FirstRight <= W.LastCluster", "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 9986, __extension__ __PRETTY_FUNCTION__)); | |||
| 9987 | ||||
| 9988 | // Use the first element on the right as pivot since we will make less-than | |||
| 9989 | // comparisons against it. | |||
| 9990 | CaseClusterIt PivotCluster = FirstRight; | |||
| 9991 | assert(PivotCluster > W.FirstCluster)(static_cast <bool> (PivotCluster > W.FirstCluster) ? void (0) : __assert_fail ("PivotCluster > W.FirstCluster" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 9991, __extension__ __PRETTY_FUNCTION__)); | |||
| 9992 | assert(PivotCluster <= W.LastCluster)(static_cast <bool> (PivotCluster <= W.LastCluster) ? void (0) : __assert_fail ("PivotCluster <= W.LastCluster" , "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 9992, __extension__ __PRETTY_FUNCTION__)); | |||
| 9993 | ||||
| 9994 | CaseClusterIt FirstLeft = W.FirstCluster; | |||
| 9995 | CaseClusterIt LastRight = W.LastCluster; | |||
| 9996 | ||||
| 9997 | const ConstantInt *Pivot = PivotCluster->Low; | |||
| 9998 | ||||
| 9999 | // New blocks will be inserted immediately after the current one. | |||
| 10000 | MachineFunction::iterator BBI(W.MBB); | |||
| 10001 | ++BBI; | |||
| 10002 | ||||
| 10003 | // We will branch to the LHS if Value < Pivot. If LHS is a single cluster, | |||
| 10004 | // we can branch to its destination directly if it's squeezed exactly in | |||
| 10005 | // between the known lower bound and Pivot - 1. | |||
| 10006 | MachineBasicBlock *LeftMBB; | |||
| 10007 | if (FirstLeft == LastLeft && FirstLeft->Kind == CC_Range && | |||
| 10008 | FirstLeft->Low == W.GE && | |||
| 10009 | (FirstLeft->High->getValue() + 1LL) == Pivot->getValue()) { | |||
| 10010 | LeftMBB = FirstLeft->MBB; | |||
| 10011 | } else { | |||
| 10012 | LeftMBB = FuncInfo.MF->CreateMachineBasicBlock(W.MBB->getBasicBlock()); | |||
| 10013 | FuncInfo.MF->insert(BBI, LeftMBB); | |||
| 10014 | WorkList.push_back( | |||
| 10015 | {LeftMBB, FirstLeft, LastLeft, W.GE, Pivot, W.DefaultProb / 2}); | |||
| 10016 | // Put Cond in a virtual register to make it available from the new blocks. | |||
| 10017 | ExportFromCurrentBlock(Cond); | |||
| 10018 | } | |||
| 10019 | ||||
| 10020 | // Similarly, we will branch to the RHS if Value >= Pivot. If RHS is a | |||
| 10021 | // single cluster, RHS.Low == Pivot, and we can branch to its destination | |||
| 10022 | // directly if RHS.High equals the current upper bound. | |||
| 10023 | MachineBasicBlock *RightMBB; | |||
| 10024 | if (FirstRight == LastRight && FirstRight->Kind == CC_Range && | |||
| 10025 | W.LT && (FirstRight->High->getValue() + 1ULL) == W.LT->getValue()) { | |||
| 10026 | RightMBB = FirstRight->MBB; | |||
| 10027 | } else { | |||
| 10028 | RightMBB = FuncInfo.MF->CreateMachineBasicBlock(W.MBB->getBasicBlock()); | |||
| 10029 | FuncInfo.MF->insert(BBI, RightMBB); | |||
| 10030 | WorkList.push_back( | |||
| 10031 | {RightMBB, FirstRight, LastRight, Pivot, W.LT, W.DefaultProb / 2}); | |||
| 10032 | // Put Cond in a virtual register to make it available from the new blocks. | |||
| 10033 | ExportFromCurrentBlock(Cond); | |||
| 10034 | } | |||
| 10035 | ||||
| 10036 | // Create the CaseBlock record that will be used to lower the branch. | |||
| 10037 | CaseBlock CB(ISD::SETLT, Cond, Pivot, nullptr, LeftMBB, RightMBB, W.MBB, | |||
| 10038 | getCurSDLoc(), LeftProb, RightProb); | |||
| 10039 | ||||
| 10040 | if (W.MBB == SwitchMBB) | |||
| 10041 | visitSwitchCase(CB, SwitchMBB); | |||
| 10042 | else | |||
| 10043 | SwitchCases.push_back(CB); | |||
| 10044 | } | |||
| 10045 | ||||
| 10046 | // Scale CaseProb after peeling a case with the probablity of PeeledCaseProb | |||
| 10047 | // from the swith statement. | |||
| 10048 | static BranchProbability scaleCaseProbality(BranchProbability CaseProb, | |||
| 10049 | BranchProbability PeeledCaseProb) { | |||
| 10050 | if (PeeledCaseProb == BranchProbability::getOne()) | |||
| 10051 | return BranchProbability::getZero(); | |||
| 10052 | BranchProbability SwitchProb = PeeledCaseProb.getCompl(); | |||
| 10053 | ||||
| 10054 | uint32_t Numerator = CaseProb.getNumerator(); | |||
| 10055 | uint32_t Denominator = SwitchProb.scale(CaseProb.getDenominator()); | |||
| 10056 | return BranchProbability(Numerator, std::max(Numerator, Denominator)); | |||
| 10057 | } | |||
| 10058 | ||||
| 10059 | // Try to peel the top probability case if it exceeds the threshold. | |||
| 10060 | // Return current MachineBasicBlock for the switch statement if the peeling | |||
| 10061 | // does not occur. | |||
| 10062 | // If the peeling is performed, return the newly created MachineBasicBlock | |||
| 10063 | // for the peeled switch statement. Also update Clusters to remove the peeled | |||
| 10064 | // case. PeeledCaseProb is the BranchProbability for the peeled case. | |||
| 10065 | MachineBasicBlock *SelectionDAGBuilder::peelDominantCaseCluster( | |||
| 10066 | const SwitchInst &SI, CaseClusterVector &Clusters, | |||
| 10067 | BranchProbability &PeeledCaseProb) { | |||
| 10068 | MachineBasicBlock *SwitchMBB = FuncInfo.MBB; | |||
| 10069 | // Don't perform if there is only one cluster or optimizing for size. | |||
| 10070 | if (SwitchPeelThreshold > 100 || !FuncInfo.BPI || Clusters.size() < 2 || | |||
| 10071 | TM.getOptLevel() == CodeGenOpt::None || | |||
| 10072 | SwitchMBB->getParent()->getFunction().optForMinSize()) | |||
| 10073 | return SwitchMBB; | |||
| 10074 | ||||
| 10075 | BranchProbability TopCaseProb = BranchProbability(SwitchPeelThreshold, 100); | |||
| 10076 | unsigned PeeledCaseIndex = 0; | |||
| 10077 | bool SwitchPeeled = false; | |||
| 10078 | for (unsigned Index = 0; Index < Clusters.size(); ++Index) { | |||
| 10079 | CaseCluster &CC = Clusters[Index]; | |||
| 10080 | if (CC.Prob < TopCaseProb) | |||
| 10081 | continue; | |||
| 10082 | TopCaseProb = CC.Prob; | |||
| 10083 | PeeledCaseIndex = Index; | |||
| 10084 | SwitchPeeled = true; | |||
| 10085 | } | |||
| 10086 | if (!SwitchPeeled) | |||
| 10087 | return SwitchMBB; | |||
| 10088 | ||||
| 10089 | LLVM_DEBUG(dbgs() << "Peeled one top case in switch stmt, prob: "do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType ("isel")) { dbgs() << "Peeled one top case in switch stmt, prob: " << TopCaseProb << "\n"; } } while (false) | |||
| 10090 | << TopCaseProb << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType ("isel")) { dbgs() << "Peeled one top case in switch stmt, prob: " << TopCaseProb << "\n"; } } while (false); | |||
| 10091 | ||||
| 10092 | // Record the MBB for the peeled switch statement. | |||
| 10093 | MachineFunction::iterator BBI(SwitchMBB); | |||
| 10094 | ++BBI; | |||
| 10095 | MachineBasicBlock *PeeledSwitchMBB = | |||
| 10096 | FuncInfo.MF->CreateMachineBasicBlock(SwitchMBB->getBasicBlock()); | |||
| 10097 | FuncInfo.MF->insert(BBI, PeeledSwitchMBB); | |||
| 10098 | ||||
| 10099 | ExportFromCurrentBlock(SI.getCondition()); | |||
| 10100 | auto PeeledCaseIt = Clusters.begin() + PeeledCaseIndex; | |||
| 10101 | SwitchWorkListItem W = {SwitchMBB, PeeledCaseIt, PeeledCaseIt, | |||
| 10102 | nullptr, nullptr, TopCaseProb.getCompl()}; | |||
| 10103 | lowerWorkItem(W, SI.getCondition(), SwitchMBB, PeeledSwitchMBB); | |||
| 10104 | ||||
| 10105 | Clusters.erase(PeeledCaseIt); | |||
| 10106 | for (CaseCluster &CC : Clusters) { | |||
| 10107 | LLVM_DEBUG(do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType ("isel")) { dbgs() << "Scale the probablity for one cluster, before scaling: " << CC.Prob << "\n"; } } while (false) | |||
| 10108 | dbgs() << "Scale the probablity for one cluster, before scaling: "do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType ("isel")) { dbgs() << "Scale the probablity for one cluster, before scaling: " << CC.Prob << "\n"; } } while (false) | |||
| 10109 | << CC.Prob << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType ("isel")) { dbgs() << "Scale the probablity for one cluster, before scaling: " << CC.Prob << "\n"; } } while (false); | |||
| 10110 | CC.Prob = scaleCaseProbality(CC.Prob, TopCaseProb); | |||
| 10111 | LLVM_DEBUG(dbgs() << "After scaling: " << CC.Prob << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType ("isel")) { dbgs() << "After scaling: " << CC.Prob << "\n"; } } while (false); | |||
| 10112 | } | |||
| 10113 | PeeledCaseProb = TopCaseProb; | |||
| 10114 | return PeeledSwitchMBB; | |||
| 10115 | } | |||
| 10116 | ||||
| 10117 | void SelectionDAGBuilder::visitSwitch(const SwitchInst &SI) { | |||
| 10118 | // Extract cases from the switch. | |||
| 10119 | BranchProbabilityInfo *BPI = FuncInfo.BPI; | |||
| 10120 | CaseClusterVector Clusters; | |||
| 10121 | Clusters.reserve(SI.getNumCases()); | |||
| 10122 | for (auto I : SI.cases()) { | |||
| 10123 | MachineBasicBlock *Succ = FuncInfo.MBBMap[I.getCaseSuccessor()]; | |||
| 10124 | const ConstantInt *CaseVal = I.getCaseValue(); | |||
| 10125 | BranchProbability Prob = | |||
| 10126 | BPI ? BPI->getEdgeProbability(SI.getParent(), I.getSuccessorIndex()) | |||
| 10127 | : BranchProbability(1, SI.getNumCases() + 1); | |||
| 10128 | Clusters.push_back(CaseCluster::range(CaseVal, CaseVal, Succ, Prob)); | |||
| 10129 | } | |||
| 10130 | ||||
| 10131 | MachineBasicBlock *DefaultMBB = FuncInfo.MBBMap[SI.getDefaultDest()]; | |||
| 10132 | ||||
| 10133 | // Cluster adjacent cases with the same destination. We do this at all | |||
| 10134 | // optimization levels because it's cheap to do and will make codegen faster | |||
| 10135 | // if there are many clusters. | |||
| 10136 | sortAndRangeify(Clusters); | |||
| 10137 | ||||
| 10138 | if (TM.getOptLevel() != CodeGenOpt::None) { | |||
| 10139 | // Replace an unreachable default with the most popular destination. | |||
| 10140 | // FIXME: Exploit unreachable default more aggressively. | |||
| 10141 | bool UnreachableDefault = | |||
| 10142 | isa<UnreachableInst>(SI.getDefaultDest()->getFirstNonPHIOrDbg()); | |||
| 10143 | if (UnreachableDefault && !Clusters.empty()) { | |||
| 10144 | DenseMap<const BasicBlock *, unsigned> Popularity; | |||
| 10145 | unsigned MaxPop = 0; | |||
| 10146 | const BasicBlock *MaxBB = nullptr; | |||
| 10147 | for (auto I : SI.cases()) { | |||
| 10148 | const BasicBlock *BB = I.getCaseSuccessor(); | |||
| 10149 | if (++Popularity[BB] > MaxPop) { | |||
| 10150 | MaxPop = Popularity[BB]; | |||
| 10151 | MaxBB = BB; | |||
| 10152 | } | |||
| 10153 | } | |||
| 10154 | // Set new default. | |||
| 10155 | assert(MaxPop > 0 && MaxBB)(static_cast <bool> (MaxPop > 0 && MaxBB) ? void (0) : __assert_fail ("MaxPop > 0 && MaxBB", "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 10155, __extension__ __PRETTY_FUNCTION__)); | |||
| 10156 | DefaultMBB = FuncInfo.MBBMap[MaxBB]; | |||
| 10157 | ||||
| 10158 | // Remove cases that were pointing to the destination that is now the | |||
| 10159 | // default. | |||
| 10160 | CaseClusterVector New; | |||
| 10161 | New.reserve(Clusters.size()); | |||
| 10162 | for (CaseCluster &CC : Clusters) { | |||
| 10163 | if (CC.MBB != DefaultMBB) | |||
| 10164 | New.push_back(CC); | |||
| 10165 | } | |||
| 10166 | Clusters = std::move(New); | |||
| 10167 | } | |||
| 10168 | } | |||
| 10169 | ||||
| 10170 | // The branch probablity of the peeled case. | |||
| 10171 | BranchProbability PeeledCaseProb = BranchProbability::getZero(); | |||
| 10172 | MachineBasicBlock *PeeledSwitchMBB = | |||
| 10173 | peelDominantCaseCluster(SI, Clusters, PeeledCaseProb); | |||
| 10174 | ||||
| 10175 | // If there is only the default destination, jump there directly. | |||
| 10176 | MachineBasicBlock *SwitchMBB = FuncInfo.MBB; | |||
| 10177 | if (Clusters.empty()) { | |||
| 10178 | assert(PeeledSwitchMBB == SwitchMBB)(static_cast <bool> (PeeledSwitchMBB == SwitchMBB) ? void (0) : __assert_fail ("PeeledSwitchMBB == SwitchMBB", "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 10178, __extension__ __PRETTY_FUNCTION__)); | |||
| 10179 | SwitchMBB->addSuccessor(DefaultMBB); | |||
| 10180 | if (DefaultMBB != NextBlock(SwitchMBB)) { | |||
| 10181 | DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other, | |||
| 10182 | getControlRoot(), DAG.getBasicBlock(DefaultMBB))); | |||
| 10183 | } | |||
| 10184 | return; | |||
| 10185 | } | |||
| 10186 | ||||
| 10187 | findJumpTables(Clusters, &SI, DefaultMBB); | |||
| 10188 | findBitTestClusters(Clusters, &SI); | |||
| 10189 | ||||
| 10190 | LLVM_DEBUG({do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType ("isel")) { { dbgs() << "Case clusters: "; for (const CaseCluster &C : Clusters) { if (C.Kind == CC_JumpTable) dbgs() << "JT:"; if (C.Kind == CC_BitTests) dbgs() << "BT:"; C.Low ->getValue().print(dbgs(), true); if (C.Low != C.High) { dbgs () << '-'; C.High->getValue().print(dbgs(), true); } dbgs() << ' '; } dbgs() << '\n'; }; } } while (false ) | |||
| 10191 | dbgs() << "Case clusters: ";do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType ("isel")) { { dbgs() << "Case clusters: "; for (const CaseCluster &C : Clusters) { if (C.Kind == CC_JumpTable) dbgs() << "JT:"; if (C.Kind == CC_BitTests) dbgs() << "BT:"; C.Low ->getValue().print(dbgs(), true); if (C.Low != C.High) { dbgs () << '-'; C.High->getValue().print(dbgs(), true); } dbgs() << ' '; } dbgs() << '\n'; }; } } while (false ) | |||
| 10192 | for (const CaseCluster &C : Clusters) {do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType ("isel")) { { dbgs() << "Case clusters: "; for (const CaseCluster &C : Clusters) { if (C.Kind == CC_JumpTable) dbgs() << "JT:"; if (C.Kind == CC_BitTests) dbgs() << "BT:"; C.Low ->getValue().print(dbgs(), true); if (C.Low != C.High) { dbgs () << '-'; C.High->getValue().print(dbgs(), true); } dbgs() << ' '; } dbgs() << '\n'; }; } } while (false ) | |||
| 10193 | if (C.Kind == CC_JumpTable)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType ("isel")) { { dbgs() << "Case clusters: "; for (const CaseCluster &C : Clusters) { if (C.Kind == CC_JumpTable) dbgs() << "JT:"; if (C.Kind == CC_BitTests) dbgs() << "BT:"; C.Low ->getValue().print(dbgs(), true); if (C.Low != C.High) { dbgs () << '-'; C.High->getValue().print(dbgs(), true); } dbgs() << ' '; } dbgs() << '\n'; }; } } while (false ) | |||
| 10194 | dbgs() << "JT:";do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType ("isel")) { { dbgs() << "Case clusters: "; for (const CaseCluster &C : Clusters) { if (C.Kind == CC_JumpTable) dbgs() << "JT:"; if (C.Kind == CC_BitTests) dbgs() << "BT:"; C.Low ->getValue().print(dbgs(), true); if (C.Low != C.High) { dbgs () << '-'; C.High->getValue().print(dbgs(), true); } dbgs() << ' '; } dbgs() << '\n'; }; } } while (false ) | |||
| 10195 | if (C.Kind == CC_BitTests)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType ("isel")) { { dbgs() << "Case clusters: "; for (const CaseCluster &C : Clusters) { if (C.Kind == CC_JumpTable) dbgs() << "JT:"; if (C.Kind == CC_BitTests) dbgs() << "BT:"; C.Low ->getValue().print(dbgs(), true); if (C.Low != C.High) { dbgs () << '-'; C.High->getValue().print(dbgs(), true); } dbgs() << ' '; } dbgs() << '\n'; }; } } while (false ) | |||
| 10196 | dbgs() << "BT:";do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType ("isel")) { { dbgs() << "Case clusters: "; for (const CaseCluster &C : Clusters) { if (C.Kind == CC_JumpTable) dbgs() << "JT:"; if (C.Kind == CC_BitTests) dbgs() << "BT:"; C.Low ->getValue().print(dbgs(), true); if (C.Low != C.High) { dbgs () << '-'; C.High->getValue().print(dbgs(), true); } dbgs() << ' '; } dbgs() << '\n'; }; } } while (false ) | |||
| 10197 | ||||
| 10198 | C.Low->getValue().print(dbgs(), true);do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType ("isel")) { { dbgs() << "Case clusters: "; for (const CaseCluster &C : Clusters) { if (C.Kind == CC_JumpTable) dbgs() << "JT:"; if (C.Kind == CC_BitTests) dbgs() << "BT:"; C.Low ->getValue().print(dbgs(), true); if (C.Low != C.High) { dbgs () << '-'; C.High->getValue().print(dbgs(), true); } dbgs() << ' '; } dbgs() << '\n'; }; } } while (false ) | |||
| 10199 | if (C.Low != C.High) {do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType ("isel")) { { dbgs() << "Case clusters: "; for (const CaseCluster &C : Clusters) { if (C.Kind == CC_JumpTable) dbgs() << "JT:"; if (C.Kind == CC_BitTests) dbgs() << "BT:"; C.Low ->getValue().print(dbgs(), true); if (C.Low != C.High) { dbgs () << '-'; C.High->getValue().print(dbgs(), true); } dbgs() << ' '; } dbgs() << '\n'; }; } } while (false ) | |||
| 10200 | dbgs() << '-';do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType ("isel")) { { dbgs() << "Case clusters: "; for (const CaseCluster &C : Clusters) { if (C.Kind == CC_JumpTable) dbgs() << "JT:"; if (C.Kind == CC_BitTests) dbgs() << "BT:"; C.Low ->getValue().print(dbgs(), true); if (C.Low != C.High) { dbgs () << '-'; C.High->getValue().print(dbgs(), true); } dbgs() << ' '; } dbgs() << '\n'; }; } } while (false ) | |||
| 10201 | C.High->getValue().print(dbgs(), true);do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType ("isel")) { { dbgs() << "Case clusters: "; for (const CaseCluster &C : Clusters) { if (C.Kind == CC_JumpTable) dbgs() << "JT:"; if (C.Kind == CC_BitTests) dbgs() << "BT:"; C.Low ->getValue().print(dbgs(), true); if (C.Low != C.High) { dbgs () << '-'; C.High->getValue().print(dbgs(), true); } dbgs() << ' '; } dbgs() << '\n'; }; } } while (false ) | |||
| 10202 | }do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType ("isel")) { { dbgs() << "Case clusters: "; for (const CaseCluster &C : Clusters) { if (C.Kind == CC_JumpTable) dbgs() << "JT:"; if (C.Kind == CC_BitTests) dbgs() << "BT:"; C.Low ->getValue().print(dbgs(), true); if (C.Low != C.High) { dbgs () << '-'; C.High->getValue().print(dbgs(), true); } dbgs() << ' '; } dbgs() << '\n'; }; } } while (false ) | |||
| 10203 | dbgs() << ' ';do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType ("isel")) { { dbgs() << "Case clusters: "; for (const CaseCluster &C : Clusters) { if (C.Kind == CC_JumpTable) dbgs() << "JT:"; if (C.Kind == CC_BitTests) dbgs() << "BT:"; C.Low ->getValue().print(dbgs(), true); if (C.Low != C.High) { dbgs () << '-'; C.High->getValue().print(dbgs(), true); } dbgs() << ' '; } dbgs() << '\n'; }; } } while (false ) | |||
| 10204 | }do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType ("isel")) { { dbgs() << "Case clusters: "; for (const CaseCluster &C : Clusters) { if (C.Kind == CC_JumpTable) dbgs() << "JT:"; if (C.Kind == CC_BitTests) dbgs() << "BT:"; C.Low ->getValue().print(dbgs(), true); if (C.Low != C.High) { dbgs () << '-'; C.High->getValue().print(dbgs(), true); } dbgs() << ' '; } dbgs() << '\n'; }; } } while (false ) | |||
| 10205 | dbgs() << '\n';do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType ("isel")) { { dbgs() << "Case clusters: "; for (const CaseCluster &C : Clusters) { if (C.Kind == CC_JumpTable) dbgs() << "JT:"; if (C.Kind == CC_BitTests) dbgs() << "BT:"; C.Low ->getValue().print(dbgs(), true); if (C.Low != C.High) { dbgs () << '-'; C.High->getValue().print(dbgs(), true); } dbgs() << ' '; } dbgs() << '\n'; }; } } while (false ) | |||
| 10206 | })do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType ("isel")) { { dbgs() << "Case clusters: "; for (const CaseCluster &C : Clusters) { if (C.Kind == CC_JumpTable) dbgs() << "JT:"; if (C.Kind == CC_BitTests) dbgs() << "BT:"; C.Low ->getValue().print(dbgs(), true); if (C.Low != C.High) { dbgs () << '-'; C.High->getValue().print(dbgs(), true); } dbgs() << ' '; } dbgs() << '\n'; }; } } while (false ); | |||
| 10207 | ||||
| 10208 | assert(!Clusters.empty())(static_cast <bool> (!Clusters.empty()) ? void (0) : __assert_fail ("!Clusters.empty()", "/build/llvm-toolchain-snapshot-7~svn337657/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp" , 10208, __extension__ __PRETTY_FUNCTION__)); | |||
| 10209 | SwitchWorkList WorkList; | |||
| 10210 | CaseClusterIt First = Clusters.begin(); | |||
| 10211 | CaseClusterIt Last = Clusters.end() - 1; | |||
| 10212 | auto DefaultProb = getEdgeProbability(PeeledSwitchMBB, DefaultMBB); | |||
| 10213 | // Scale the branchprobability for DefaultMBB if the peel occurs and | |||
| 10214 | // DefaultMBB is not replaced. | |||
| 10215 | if (PeeledCaseProb != BranchProbability::getZero() && | |||
| 10216 | DefaultMBB == FuncInfo.MBBMap[SI.getDefaultDest()]) | |||
| 10217 | DefaultProb = scaleCaseProbality(DefaultProb, PeeledCaseProb); | |||
| 10218 | WorkList.push_back( | |||
| 10219 | {PeeledSwitchMBB, First, Last, nullptr, nullptr, DefaultProb}); | |||
| 10220 | ||||
| 10221 | while (!WorkList.empty()) { | |||
| 10222 | SwitchWorkListItem W = WorkList.back(); | |||
| 10223 | WorkList.pop_back(); | |||
| 10224 | unsigned NumClusters = W.LastCluster - W.FirstCluster + 1; | |||
| 10225 | ||||
| 10226 | if (NumClusters > 3 && TM.getOptLevel() != CodeGenOpt::None && | |||
| 10227 | !DefaultMBB->getParent()->getFunction().optForMinSize()) { | |||
| 10228 | // For optimized builds, lower large range as a balanced binary tree. | |||
| 10229 | splitWorkItem(WorkList, W, SI.getCondition(), SwitchMBB); | |||
| 10230 | continue; | |||
| 10231 | } | |||
| 10232 | ||||
| 10233 | lowerWorkItem(W, SI.getCondition(), SwitchMBB, DefaultMBB); | |||
| 10234 | } | |||
| 10235 | } |