Bug Summary

File:llvm/include/llvm/CodeGen/SelectionDAGNodes.h
Warning:line 1132, column 10
Called C++ object pointer is null

Annotated Source Code

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clang -cc1 -cc1 -triple x86_64-pc-linux-gnu -analyze -disable-free -clear-ast-before-backend -disable-llvm-verifier -discard-value-names -main-file-name ARMISelLowering.cpp -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=cplusplus -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -analyzer-config-compatibility-mode=true -mrelocation-model pic -pic-level 2 -mframe-pointer=none -fmath-errno -ffp-contract=on -fno-rounding-math -mconstructor-aliases -funwind-tables=2 -target-cpu x86-64 -tune-cpu generic -debugger-tuning=gdb -ffunction-sections -fdata-sections -fcoverage-compilation-dir=/build/llvm-toolchain-snapshot-14~++20220116100644+5f782d25a742/build-llvm/tools/clang/stage2-bins -resource-dir /usr/lib/llvm-14/lib/clang/14.0.0 -D _DEBUG -D _GNU_SOURCE -D __STDC_CONSTANT_MACROS -D __STDC_FORMAT_MACROS -D __STDC_LIMIT_MACROS -I lib/Target/ARM -I /build/llvm-toolchain-snapshot-14~++20220116100644+5f782d25a742/llvm/lib/Target/ARM -I include -I /build/llvm-toolchain-snapshot-14~++20220116100644+5f782d25a742/llvm/include -D _FORTIFY_SOURCE=2 -D NDEBUG -U NDEBUG -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/10/../../../../include/c++/10 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/10/../../../../include/x86_64-linux-gnu/c++/10 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/10/../../../../include/c++/10/backward -internal-isystem /usr/lib/llvm-14/lib/clang/14.0.0/include -internal-isystem /usr/local/include -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/10/../../../../x86_64-linux-gnu/include -internal-externc-isystem /usr/include/x86_64-linux-gnu -internal-externc-isystem /include -internal-externc-isystem /usr/include -fmacro-prefix-map=/build/llvm-toolchain-snapshot-14~++20220116100644+5f782d25a742/build-llvm/tools/clang/stage2-bins=build-llvm/tools/clang/stage2-bins -fmacro-prefix-map=/build/llvm-toolchain-snapshot-14~++20220116100644+5f782d25a742/= -fcoverage-prefix-map=/build/llvm-toolchain-snapshot-14~++20220116100644+5f782d25a742/build-llvm/tools/clang/stage2-bins=build-llvm/tools/clang/stage2-bins -fcoverage-prefix-map=/build/llvm-toolchain-snapshot-14~++20220116100644+5f782d25a742/= -O3 -Wno-unused-command-line-argument -Wno-unused-parameter -Wwrite-strings -Wno-missing-field-initializers -Wno-long-long -Wno-maybe-uninitialized -Wno-class-memaccess -Wno-redundant-move -Wno-pessimizing-move -Wno-noexcept-type -Wno-comment -std=c++14 -fdeprecated-macro -fdebug-compilation-dir=/build/llvm-toolchain-snapshot-14~++20220116100644+5f782d25a742/build-llvm/tools/clang/stage2-bins -fdebug-prefix-map=/build/llvm-toolchain-snapshot-14~++20220116100644+5f782d25a742/build-llvm/tools/clang/stage2-bins=build-llvm/tools/clang/stage2-bins -fdebug-prefix-map=/build/llvm-toolchain-snapshot-14~++20220116100644+5f782d25a742/= -ferror-limit 19 -fvisibility hidden -fvisibility-inlines-hidden -stack-protector 2 -fgnuc-version=4.2.1 -fcolor-diagnostics -vectorize-loops -vectorize-slp -analyzer-output=html -analyzer-config stable-report-filename=true -faddrsig -D__GCC_HAVE_DWARF2_CFI_ASM=1 -o /tmp/scan-build-2022-01-16-232930-107970-1 -x c++ /build/llvm-toolchain-snapshot-14~++20220116100644+5f782d25a742/llvm/lib/Target/ARM/ARMISelLowering.cpp

/build/llvm-toolchain-snapshot-14~++20220116100644+5f782d25a742/llvm/lib/Target/ARM/ARMISelLowering.cpp

1//===- ARMISelLowering.cpp - ARM DAG Lowering Implementation --------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines the interfaces that ARM uses to lower LLVM code into a
10// selection DAG.
11//
12//===----------------------------------------------------------------------===//
13
14#include "ARMISelLowering.h"
15#include "ARMBaseInstrInfo.h"
16#include "ARMBaseRegisterInfo.h"
17#include "ARMCallingConv.h"
18#include "ARMConstantPoolValue.h"
19#include "ARMMachineFunctionInfo.h"
20#include "ARMPerfectShuffle.h"
21#include "ARMRegisterInfo.h"
22#include "ARMSelectionDAGInfo.h"
23#include "ARMSubtarget.h"
24#include "ARMTargetTransformInfo.h"
25#include "MCTargetDesc/ARMAddressingModes.h"
26#include "MCTargetDesc/ARMBaseInfo.h"
27#include "Utils/ARMBaseInfo.h"
28#include "llvm/ADT/APFloat.h"
29#include "llvm/ADT/APInt.h"
30#include "llvm/ADT/ArrayRef.h"
31#include "llvm/ADT/BitVector.h"
32#include "llvm/ADT/DenseMap.h"
33#include "llvm/ADT/STLExtras.h"
34#include "llvm/ADT/SmallPtrSet.h"
35#include "llvm/ADT/SmallVector.h"
36#include "llvm/ADT/Statistic.h"
37#include "llvm/ADT/StringExtras.h"
38#include "llvm/ADT/StringRef.h"
39#include "llvm/ADT/StringSwitch.h"
40#include "llvm/ADT/Triple.h"
41#include "llvm/ADT/Twine.h"
42#include "llvm/Analysis/VectorUtils.h"
43#include "llvm/CodeGen/CallingConvLower.h"
44#include "llvm/CodeGen/ISDOpcodes.h"
45#include "llvm/CodeGen/IntrinsicLowering.h"
46#include "llvm/CodeGen/MachineBasicBlock.h"
47#include "llvm/CodeGen/MachineConstantPool.h"
48#include "llvm/CodeGen/MachineFrameInfo.h"
49#include "llvm/CodeGen/MachineFunction.h"
50#include "llvm/CodeGen/MachineInstr.h"
51#include "llvm/CodeGen/MachineInstrBuilder.h"
52#include "llvm/CodeGen/MachineJumpTableInfo.h"
53#include "llvm/CodeGen/MachineMemOperand.h"
54#include "llvm/CodeGen/MachineOperand.h"
55#include "llvm/CodeGen/MachineRegisterInfo.h"
56#include "llvm/CodeGen/RuntimeLibcalls.h"
57#include "llvm/CodeGen/SelectionDAG.h"
58#include "llvm/CodeGen/SelectionDAGAddressAnalysis.h"
59#include "llvm/CodeGen/SelectionDAGNodes.h"
60#include "llvm/CodeGen/TargetInstrInfo.h"
61#include "llvm/CodeGen/TargetLowering.h"
62#include "llvm/CodeGen/TargetOpcodes.h"
63#include "llvm/CodeGen/TargetRegisterInfo.h"
64#include "llvm/CodeGen/TargetSubtargetInfo.h"
65#include "llvm/CodeGen/ValueTypes.h"
66#include "llvm/IR/Attributes.h"
67#include "llvm/IR/CallingConv.h"
68#include "llvm/IR/Constant.h"
69#include "llvm/IR/Constants.h"
70#include "llvm/IR/DataLayout.h"
71#include "llvm/IR/DebugLoc.h"
72#include "llvm/IR/DerivedTypes.h"
73#include "llvm/IR/Function.h"
74#include "llvm/IR/GlobalAlias.h"
75#include "llvm/IR/GlobalValue.h"
76#include "llvm/IR/GlobalVariable.h"
77#include "llvm/IR/IRBuilder.h"
78#include "llvm/IR/InlineAsm.h"
79#include "llvm/IR/Instruction.h"
80#include "llvm/IR/Instructions.h"
81#include "llvm/IR/IntrinsicInst.h"
82#include "llvm/IR/Intrinsics.h"
83#include "llvm/IR/IntrinsicsARM.h"
84#include "llvm/IR/Module.h"
85#include "llvm/IR/PatternMatch.h"
86#include "llvm/IR/Type.h"
87#include "llvm/IR/User.h"
88#include "llvm/IR/Value.h"
89#include "llvm/MC/MCInstrDesc.h"
90#include "llvm/MC/MCInstrItineraries.h"
91#include "llvm/MC/MCRegisterInfo.h"
92#include "llvm/MC/MCSchedule.h"
93#include "llvm/Support/AtomicOrdering.h"
94#include "llvm/Support/BranchProbability.h"
95#include "llvm/Support/Casting.h"
96#include "llvm/Support/CodeGen.h"
97#include "llvm/Support/CommandLine.h"
98#include "llvm/Support/Compiler.h"
99#include "llvm/Support/Debug.h"
100#include "llvm/Support/ErrorHandling.h"
101#include "llvm/Support/KnownBits.h"
102#include "llvm/Support/MachineValueType.h"
103#include "llvm/Support/MathExtras.h"
104#include "llvm/Support/raw_ostream.h"
105#include "llvm/Target/TargetMachine.h"
106#include "llvm/Target/TargetOptions.h"
107#include <algorithm>
108#include <cassert>
109#include <cstdint>
110#include <cstdlib>
111#include <iterator>
112#include <limits>
113#include <string>
114#include <tuple>
115#include <utility>
116#include <vector>
117
118using namespace llvm;
119using namespace llvm::PatternMatch;
120
121#define DEBUG_TYPE"arm-isel" "arm-isel"
122
123STATISTIC(NumTailCalls, "Number of tail calls")static llvm::Statistic NumTailCalls = {"arm-isel", "NumTailCalls"
, "Number of tail calls"}
;
124STATISTIC(NumMovwMovt, "Number of GAs materialized with movw + movt")static llvm::Statistic NumMovwMovt = {"arm-isel", "NumMovwMovt"
, "Number of GAs materialized with movw + movt"}
;
125STATISTIC(NumLoopByVals, "Number of loops generated for byval arguments")static llvm::Statistic NumLoopByVals = {"arm-isel", "NumLoopByVals"
, "Number of loops generated for byval arguments"}
;
126STATISTIC(NumConstpoolPromoted,static llvm::Statistic NumConstpoolPromoted = {"arm-isel", "NumConstpoolPromoted"
, "Number of constants with their storage promoted into constant pools"
}
127 "Number of constants with their storage promoted into constant pools")static llvm::Statistic NumConstpoolPromoted = {"arm-isel", "NumConstpoolPromoted"
, "Number of constants with their storage promoted into constant pools"
}
;
128
129static cl::opt<bool>
130ARMInterworking("arm-interworking", cl::Hidden,
131 cl::desc("Enable / disable ARM interworking (for debugging only)"),
132 cl::init(true));
133
134static cl::opt<bool> EnableConstpoolPromotion(
135 "arm-promote-constant", cl::Hidden,
136 cl::desc("Enable / disable promotion of unnamed_addr constants into "
137 "constant pools"),
138 cl::init(false)); // FIXME: set to true by default once PR32780 is fixed
139static cl::opt<unsigned> ConstpoolPromotionMaxSize(
140 "arm-promote-constant-max-size", cl::Hidden,
141 cl::desc("Maximum size of constant to promote into a constant pool"),
142 cl::init(64));
143static cl::opt<unsigned> ConstpoolPromotionMaxTotal(
144 "arm-promote-constant-max-total", cl::Hidden,
145 cl::desc("Maximum size of ALL constants to promote into a constant pool"),
146 cl::init(128));
147
148cl::opt<unsigned>
149MVEMaxSupportedInterleaveFactor("mve-max-interleave-factor", cl::Hidden,
150 cl::desc("Maximum interleave factor for MVE VLDn to generate."),
151 cl::init(2));
152
153// The APCS parameter registers.
154static const MCPhysReg GPRArgRegs[] = {
155 ARM::R0, ARM::R1, ARM::R2, ARM::R3
156};
157
158void ARMTargetLowering::addTypeForNEON(MVT VT, MVT PromotedLdStVT) {
159 if (VT != PromotedLdStVT) {
160 setOperationAction(ISD::LOAD, VT, Promote);
161 AddPromotedToType (ISD::LOAD, VT, PromotedLdStVT);
162
163 setOperationAction(ISD::STORE, VT, Promote);
164 AddPromotedToType (ISD::STORE, VT, PromotedLdStVT);
165 }
166
167 MVT ElemTy = VT.getVectorElementType();
168 if (ElemTy != MVT::f64)
169 setOperationAction(ISD::SETCC, VT, Custom);
170 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
171 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
172 if (ElemTy == MVT::i32) {
173 setOperationAction(ISD::SINT_TO_FP, VT, Custom);
174 setOperationAction(ISD::UINT_TO_FP, VT, Custom);
175 setOperationAction(ISD::FP_TO_SINT, VT, Custom);
176 setOperationAction(ISD::FP_TO_UINT, VT, Custom);
177 } else {
178 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
179 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
180 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
181 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
182 }
183 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
184 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
185 setOperationAction(ISD::CONCAT_VECTORS, VT, Legal);
186 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
187 setOperationAction(ISD::SELECT, VT, Expand);
188 setOperationAction(ISD::SELECT_CC, VT, Expand);
189 setOperationAction(ISD::VSELECT, VT, Expand);
190 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand);
191 if (VT.isInteger()) {
192 setOperationAction(ISD::SHL, VT, Custom);
193 setOperationAction(ISD::SRA, VT, Custom);
194 setOperationAction(ISD::SRL, VT, Custom);
195 }
196
197 // Neon does not support vector divide/remainder operations.
198 setOperationAction(ISD::SDIV, VT, Expand);
199 setOperationAction(ISD::UDIV, VT, Expand);
200 setOperationAction(ISD::FDIV, VT, Expand);
201 setOperationAction(ISD::SREM, VT, Expand);
202 setOperationAction(ISD::UREM, VT, Expand);
203 setOperationAction(ISD::FREM, VT, Expand);
204 setOperationAction(ISD::SDIVREM, VT, Expand);
205 setOperationAction(ISD::UDIVREM, VT, Expand);
206
207 if (!VT.isFloatingPoint() &&
208 VT != MVT::v2i64 && VT != MVT::v1i64)
209 for (auto Opcode : {ISD::ABS, ISD::SMIN, ISD::SMAX, ISD::UMIN, ISD::UMAX})
210 setOperationAction(Opcode, VT, Legal);
211 if (!VT.isFloatingPoint())
212 for (auto Opcode : {ISD::SADDSAT, ISD::UADDSAT, ISD::SSUBSAT, ISD::USUBSAT})
213 setOperationAction(Opcode, VT, Legal);
214}
215
216void ARMTargetLowering::addDRTypeForNEON(MVT VT) {
217 addRegisterClass(VT, &ARM::DPRRegClass);
218 addTypeForNEON(VT, MVT::f64);
219}
220
221void ARMTargetLowering::addQRTypeForNEON(MVT VT) {
222 addRegisterClass(VT, &ARM::DPairRegClass);
223 addTypeForNEON(VT, MVT::v2f64);
224}
225
226void ARMTargetLowering::setAllExpand(MVT VT) {
227 for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc)
228 setOperationAction(Opc, VT, Expand);
229
230 // We support these really simple operations even on types where all
231 // the actual arithmetic has to be broken down into simpler
232 // operations or turned into library calls.
233 setOperationAction(ISD::BITCAST, VT, Legal);
234 setOperationAction(ISD::LOAD, VT, Legal);
235 setOperationAction(ISD::STORE, VT, Legal);
236 setOperationAction(ISD::UNDEF, VT, Legal);
237}
238
239void ARMTargetLowering::addAllExtLoads(const MVT From, const MVT To,
240 LegalizeAction Action) {
241 setLoadExtAction(ISD::EXTLOAD, From, To, Action);
242 setLoadExtAction(ISD::ZEXTLOAD, From, To, Action);
243 setLoadExtAction(ISD::SEXTLOAD, From, To, Action);
244}
245
246void ARMTargetLowering::addMVEVectorTypes(bool HasMVEFP) {
247 const MVT IntTypes[] = { MVT::v16i8, MVT::v8i16, MVT::v4i32 };
248
249 for (auto VT : IntTypes) {
250 addRegisterClass(VT, &ARM::MQPRRegClass);
251 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
252 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
253 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
254 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
255 setOperationAction(ISD::SHL, VT, Custom);
256 setOperationAction(ISD::SRA, VT, Custom);
257 setOperationAction(ISD::SRL, VT, Custom);
258 setOperationAction(ISD::SMIN, VT, Legal);
259 setOperationAction(ISD::SMAX, VT, Legal);
260 setOperationAction(ISD::UMIN, VT, Legal);
261 setOperationAction(ISD::UMAX, VT, Legal);
262 setOperationAction(ISD::ABS, VT, Legal);
263 setOperationAction(ISD::SETCC, VT, Custom);
264 setOperationAction(ISD::MLOAD, VT, Custom);
265 setOperationAction(ISD::MSTORE, VT, Legal);
266 setOperationAction(ISD::CTLZ, VT, Legal);
267 setOperationAction(ISD::CTTZ, VT, Custom);
268 setOperationAction(ISD::BITREVERSE, VT, Legal);
269 setOperationAction(ISD::BSWAP, VT, Legal);
270 setOperationAction(ISD::SADDSAT, VT, Legal);
271 setOperationAction(ISD::UADDSAT, VT, Legal);
272 setOperationAction(ISD::SSUBSAT, VT, Legal);
273 setOperationAction(ISD::USUBSAT, VT, Legal);
274 setOperationAction(ISD::ABDS, VT, Legal);
275 setOperationAction(ISD::ABDU, VT, Legal);
276
277 // No native support for these.
278 setOperationAction(ISD::UDIV, VT, Expand);
279 setOperationAction(ISD::SDIV, VT, Expand);
280 setOperationAction(ISD::UREM, VT, Expand);
281 setOperationAction(ISD::SREM, VT, Expand);
282 setOperationAction(ISD::UDIVREM, VT, Expand);
283 setOperationAction(ISD::SDIVREM, VT, Expand);
284 setOperationAction(ISD::CTPOP, VT, Expand);
285 setOperationAction(ISD::SELECT, VT, Expand);
286 setOperationAction(ISD::SELECT_CC, VT, Expand);
287
288 // Vector reductions
289 setOperationAction(ISD::VECREDUCE_ADD, VT, Legal);
290 setOperationAction(ISD::VECREDUCE_SMAX, VT, Legal);
291 setOperationAction(ISD::VECREDUCE_UMAX, VT, Legal);
292 setOperationAction(ISD::VECREDUCE_SMIN, VT, Legal);
293 setOperationAction(ISD::VECREDUCE_UMIN, VT, Legal);
294 setOperationAction(ISD::VECREDUCE_MUL, VT, Custom);
295 setOperationAction(ISD::VECREDUCE_AND, VT, Custom);
296 setOperationAction(ISD::VECREDUCE_OR, VT, Custom);
297 setOperationAction(ISD::VECREDUCE_XOR, VT, Custom);
298
299 if (!HasMVEFP) {
300 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
301 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
302 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
303 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
304 } else {
305 setOperationAction(ISD::FP_TO_SINT_SAT, VT, Custom);
306 setOperationAction(ISD::FP_TO_UINT_SAT, VT, Custom);
307 }
308
309 // Pre and Post inc are supported on loads and stores
310 for (unsigned im = (unsigned)ISD::PRE_INC;
311 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
312 setIndexedLoadAction(im, VT, Legal);
313 setIndexedStoreAction(im, VT, Legal);
314 setIndexedMaskedLoadAction(im, VT, Legal);
315 setIndexedMaskedStoreAction(im, VT, Legal);
316 }
317 }
318
319 const MVT FloatTypes[] = { MVT::v8f16, MVT::v4f32 };
320 for (auto VT : FloatTypes) {
321 addRegisterClass(VT, &ARM::MQPRRegClass);
322 if (!HasMVEFP)
323 setAllExpand(VT);
324
325 // These are legal or custom whether we have MVE.fp or not
326 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
327 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
328 setOperationAction(ISD::INSERT_VECTOR_ELT, VT.getVectorElementType(), Custom);
329 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
330 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
331 setOperationAction(ISD::BUILD_VECTOR, VT.getVectorElementType(), Custom);
332 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Legal);
333 setOperationAction(ISD::SETCC, VT, Custom);
334 setOperationAction(ISD::MLOAD, VT, Custom);
335 setOperationAction(ISD::MSTORE, VT, Legal);
336 setOperationAction(ISD::SELECT, VT, Expand);
337 setOperationAction(ISD::SELECT_CC, VT, Expand);
338
339 // Pre and Post inc are supported on loads and stores
340 for (unsigned im = (unsigned)ISD::PRE_INC;
341 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
342 setIndexedLoadAction(im, VT, Legal);
343 setIndexedStoreAction(im, VT, Legal);
344 setIndexedMaskedLoadAction(im, VT, Legal);
345 setIndexedMaskedStoreAction(im, VT, Legal);
346 }
347
348 if (HasMVEFP) {
349 setOperationAction(ISD::FMINNUM, VT, Legal);
350 setOperationAction(ISD::FMAXNUM, VT, Legal);
351 setOperationAction(ISD::FROUND, VT, Legal);
352 setOperationAction(ISD::VECREDUCE_FADD, VT, Custom);
353 setOperationAction(ISD::VECREDUCE_FMUL, VT, Custom);
354 setOperationAction(ISD::VECREDUCE_FMIN, VT, Custom);
355 setOperationAction(ISD::VECREDUCE_FMAX, VT, Custom);
356
357 // No native support for these.
358 setOperationAction(ISD::FDIV, VT, Expand);
359 setOperationAction(ISD::FREM, VT, Expand);
360 setOperationAction(ISD::FSQRT, VT, Expand);
361 setOperationAction(ISD::FSIN, VT, Expand);
362 setOperationAction(ISD::FCOS, VT, Expand);
363 setOperationAction(ISD::FPOW, VT, Expand);
364 setOperationAction(ISD::FLOG, VT, Expand);
365 setOperationAction(ISD::FLOG2, VT, Expand);
366 setOperationAction(ISD::FLOG10, VT, Expand);
367 setOperationAction(ISD::FEXP, VT, Expand);
368 setOperationAction(ISD::FEXP2, VT, Expand);
369 setOperationAction(ISD::FNEARBYINT, VT, Expand);
370 }
371 }
372
373 // Custom Expand smaller than legal vector reductions to prevent false zero
374 // items being added.
375 setOperationAction(ISD::VECREDUCE_FADD, MVT::v4f16, Custom);
376 setOperationAction(ISD::VECREDUCE_FMUL, MVT::v4f16, Custom);
377 setOperationAction(ISD::VECREDUCE_FMIN, MVT::v4f16, Custom);
378 setOperationAction(ISD::VECREDUCE_FMAX, MVT::v4f16, Custom);
379 setOperationAction(ISD::VECREDUCE_FADD, MVT::v2f16, Custom);
380 setOperationAction(ISD::VECREDUCE_FMUL, MVT::v2f16, Custom);
381 setOperationAction(ISD::VECREDUCE_FMIN, MVT::v2f16, Custom);
382 setOperationAction(ISD::VECREDUCE_FMAX, MVT::v2f16, Custom);
383
384 // We 'support' these types up to bitcast/load/store level, regardless of
385 // MVE integer-only / float support. Only doing FP data processing on the FP
386 // vector types is inhibited at integer-only level.
387 const MVT LongTypes[] = { MVT::v2i64, MVT::v2f64 };
388 for (auto VT : LongTypes) {
389 addRegisterClass(VT, &ARM::MQPRRegClass);
390 setAllExpand(VT);
391 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
392 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
393 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
394 setOperationAction(ISD::VSELECT, VT, Legal);
395 }
396 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2f64, Legal);
397
398 // We can do bitwise operations on v2i64 vectors
399 setOperationAction(ISD::AND, MVT::v2i64, Legal);
400 setOperationAction(ISD::OR, MVT::v2i64, Legal);
401 setOperationAction(ISD::XOR, MVT::v2i64, Legal);
402
403 // It is legal to extload from v4i8 to v4i16 or v4i32.
404 addAllExtLoads(MVT::v8i16, MVT::v8i8, Legal);
405 addAllExtLoads(MVT::v4i32, MVT::v4i16, Legal);
406 addAllExtLoads(MVT::v4i32, MVT::v4i8, Legal);
407
408 // It is legal to sign extend from v4i8/v4i16 to v4i32 or v8i8 to v8i16.
409 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i8, Legal);
410 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i16, Legal);
411 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i32, Legal);
412 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v8i8, Legal);
413 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v8i16, Legal);
414
415 // Some truncating stores are legal too.
416 setTruncStoreAction(MVT::v4i32, MVT::v4i16, Legal);
417 setTruncStoreAction(MVT::v4i32, MVT::v4i8, Legal);
418 setTruncStoreAction(MVT::v8i16, MVT::v8i8, Legal);
419
420 // Pre and Post inc on these are legal, given the correct extends
421 for (unsigned im = (unsigned)ISD::PRE_INC;
422 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
423 for (auto VT : {MVT::v8i8, MVT::v4i8, MVT::v4i16}) {
424 setIndexedLoadAction(im, VT, Legal);
425 setIndexedStoreAction(im, VT, Legal);
426 setIndexedMaskedLoadAction(im, VT, Legal);
427 setIndexedMaskedStoreAction(im, VT, Legal);
428 }
429 }
430
431 // Predicate types
432 const MVT pTypes[] = {MVT::v16i1, MVT::v8i1, MVT::v4i1, MVT::v2i1};
433 for (auto VT : pTypes) {
434 addRegisterClass(VT, &ARM::VCCRRegClass);
435 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
436 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
437 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
438 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
439 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
440 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
441 setOperationAction(ISD::SETCC, VT, Custom);
442 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Expand);
443 setOperationAction(ISD::LOAD, VT, Custom);
444 setOperationAction(ISD::STORE, VT, Custom);
445 setOperationAction(ISD::TRUNCATE, VT, Custom);
446 setOperationAction(ISD::VSELECT, VT, Expand);
447 setOperationAction(ISD::SELECT, VT, Expand);
448 }
449 setOperationAction(ISD::SETCC, MVT::v2i1, Expand);
450 setOperationAction(ISD::TRUNCATE, MVT::v2i1, Expand);
451 setOperationAction(ISD::AND, MVT::v2i1, Expand);
452 setOperationAction(ISD::OR, MVT::v2i1, Expand);
453 setOperationAction(ISD::XOR, MVT::v2i1, Expand);
454 setOperationAction(ISD::SINT_TO_FP, MVT::v2i1, Expand);
455 setOperationAction(ISD::UINT_TO_FP, MVT::v2i1, Expand);
456 setOperationAction(ISD::FP_TO_SINT, MVT::v2i1, Expand);
457 setOperationAction(ISD::FP_TO_UINT, MVT::v2i1, Expand);
458
459 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i32, Custom);
460 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
461 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom);
462 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
463 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i16, Custom);
464 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i32, Custom);
465 setOperationAction(ISD::TRUNCATE, MVT::v8i32, Custom);
466 setOperationAction(ISD::TRUNCATE, MVT::v16i16, Custom);
467}
468
469ARMTargetLowering::ARMTargetLowering(const TargetMachine &TM,
470 const ARMSubtarget &STI)
471 : TargetLowering(TM), Subtarget(&STI) {
472 RegInfo = Subtarget->getRegisterInfo();
473 Itins = Subtarget->getInstrItineraryData();
474
475 setBooleanContents(ZeroOrOneBooleanContent);
476 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
477
478 if (!Subtarget->isTargetDarwin() && !Subtarget->isTargetIOS() &&
479 !Subtarget->isTargetWatchOS()) {
480 bool IsHFTarget = TM.Options.FloatABIType == FloatABI::Hard;
481 for (int LCID = 0; LCID < RTLIB::UNKNOWN_LIBCALL; ++LCID)
482 setLibcallCallingConv(static_cast<RTLIB::Libcall>(LCID),
483 IsHFTarget ? CallingConv::ARM_AAPCS_VFP
484 : CallingConv::ARM_AAPCS);
485 }
486
487 if (Subtarget->isTargetMachO()) {
488 // Uses VFP for Thumb libfuncs if available.
489 if (Subtarget->isThumb() && Subtarget->hasVFP2Base() &&
490 Subtarget->hasARMOps() && !Subtarget->useSoftFloat()) {
491 static const struct {
492 const RTLIB::Libcall Op;
493 const char * const Name;
494 const ISD::CondCode Cond;
495 } LibraryCalls[] = {
496 // Single-precision floating-point arithmetic.
497 { RTLIB::ADD_F32, "__addsf3vfp", ISD::SETCC_INVALID },
498 { RTLIB::SUB_F32, "__subsf3vfp", ISD::SETCC_INVALID },
499 { RTLIB::MUL_F32, "__mulsf3vfp", ISD::SETCC_INVALID },
500 { RTLIB::DIV_F32, "__divsf3vfp", ISD::SETCC_INVALID },
501
502 // Double-precision floating-point arithmetic.
503 { RTLIB::ADD_F64, "__adddf3vfp", ISD::SETCC_INVALID },
504 { RTLIB::SUB_F64, "__subdf3vfp", ISD::SETCC_INVALID },
505 { RTLIB::MUL_F64, "__muldf3vfp", ISD::SETCC_INVALID },
506 { RTLIB::DIV_F64, "__divdf3vfp", ISD::SETCC_INVALID },
507
508 // Single-precision comparisons.
509 { RTLIB::OEQ_F32, "__eqsf2vfp", ISD::SETNE },
510 { RTLIB::UNE_F32, "__nesf2vfp", ISD::SETNE },
511 { RTLIB::OLT_F32, "__ltsf2vfp", ISD::SETNE },
512 { RTLIB::OLE_F32, "__lesf2vfp", ISD::SETNE },
513 { RTLIB::OGE_F32, "__gesf2vfp", ISD::SETNE },
514 { RTLIB::OGT_F32, "__gtsf2vfp", ISD::SETNE },
515 { RTLIB::UO_F32, "__unordsf2vfp", ISD::SETNE },
516
517 // Double-precision comparisons.
518 { RTLIB::OEQ_F64, "__eqdf2vfp", ISD::SETNE },
519 { RTLIB::UNE_F64, "__nedf2vfp", ISD::SETNE },
520 { RTLIB::OLT_F64, "__ltdf2vfp", ISD::SETNE },
521 { RTLIB::OLE_F64, "__ledf2vfp", ISD::SETNE },
522 { RTLIB::OGE_F64, "__gedf2vfp", ISD::SETNE },
523 { RTLIB::OGT_F64, "__gtdf2vfp", ISD::SETNE },
524 { RTLIB::UO_F64, "__unorddf2vfp", ISD::SETNE },
525
526 // Floating-point to integer conversions.
527 // i64 conversions are done via library routines even when generating VFP
528 // instructions, so use the same ones.
529 { RTLIB::FPTOSINT_F64_I32, "__fixdfsivfp", ISD::SETCC_INVALID },
530 { RTLIB::FPTOUINT_F64_I32, "__fixunsdfsivfp", ISD::SETCC_INVALID },
531 { RTLIB::FPTOSINT_F32_I32, "__fixsfsivfp", ISD::SETCC_INVALID },
532 { RTLIB::FPTOUINT_F32_I32, "__fixunssfsivfp", ISD::SETCC_INVALID },
533
534 // Conversions between floating types.
535 { RTLIB::FPROUND_F64_F32, "__truncdfsf2vfp", ISD::SETCC_INVALID },
536 { RTLIB::FPEXT_F32_F64, "__extendsfdf2vfp", ISD::SETCC_INVALID },
537
538 // Integer to floating-point conversions.
539 // i64 conversions are done via library routines even when generating VFP
540 // instructions, so use the same ones.
541 // FIXME: There appears to be some naming inconsistency in ARM libgcc:
542 // e.g., __floatunsidf vs. __floatunssidfvfp.
543 { RTLIB::SINTTOFP_I32_F64, "__floatsidfvfp", ISD::SETCC_INVALID },
544 { RTLIB::UINTTOFP_I32_F64, "__floatunssidfvfp", ISD::SETCC_INVALID },
545 { RTLIB::SINTTOFP_I32_F32, "__floatsisfvfp", ISD::SETCC_INVALID },
546 { RTLIB::UINTTOFP_I32_F32, "__floatunssisfvfp", ISD::SETCC_INVALID },
547 };
548
549 for (const auto &LC : LibraryCalls) {
550 setLibcallName(LC.Op, LC.Name);
551 if (LC.Cond != ISD::SETCC_INVALID)
552 setCmpLibcallCC(LC.Op, LC.Cond);
553 }
554 }
555 }
556
557 // These libcalls are not available in 32-bit.
558 setLibcallName(RTLIB::SHL_I128, nullptr);
559 setLibcallName(RTLIB::SRL_I128, nullptr);
560 setLibcallName(RTLIB::SRA_I128, nullptr);
561 setLibcallName(RTLIB::MUL_I128, nullptr);
562 setLibcallName(RTLIB::MULO_I64, nullptr);
563 setLibcallName(RTLIB::MULO_I128, nullptr);
564
565 // RTLIB
566 if (Subtarget->isAAPCS_ABI() &&
567 (Subtarget->isTargetAEABI() || Subtarget->isTargetGNUAEABI() ||
568 Subtarget->isTargetMuslAEABI() || Subtarget->isTargetAndroid())) {
569 static const struct {
570 const RTLIB::Libcall Op;
571 const char * const Name;
572 const CallingConv::ID CC;
573 const ISD::CondCode Cond;
574 } LibraryCalls[] = {
575 // Double-precision floating-point arithmetic helper functions
576 // RTABI chapter 4.1.2, Table 2
577 { RTLIB::ADD_F64, "__aeabi_dadd", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
578 { RTLIB::DIV_F64, "__aeabi_ddiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
579 { RTLIB::MUL_F64, "__aeabi_dmul", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
580 { RTLIB::SUB_F64, "__aeabi_dsub", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
581
582 // Double-precision floating-point comparison helper functions
583 // RTABI chapter 4.1.2, Table 3
584 { RTLIB::OEQ_F64, "__aeabi_dcmpeq", CallingConv::ARM_AAPCS, ISD::SETNE },
585 { RTLIB::UNE_F64, "__aeabi_dcmpeq", CallingConv::ARM_AAPCS, ISD::SETEQ },
586 { RTLIB::OLT_F64, "__aeabi_dcmplt", CallingConv::ARM_AAPCS, ISD::SETNE },
587 { RTLIB::OLE_F64, "__aeabi_dcmple", CallingConv::ARM_AAPCS, ISD::SETNE },
588 { RTLIB::OGE_F64, "__aeabi_dcmpge", CallingConv::ARM_AAPCS, ISD::SETNE },
589 { RTLIB::OGT_F64, "__aeabi_dcmpgt", CallingConv::ARM_AAPCS, ISD::SETNE },
590 { RTLIB::UO_F64, "__aeabi_dcmpun", CallingConv::ARM_AAPCS, ISD::SETNE },
591
592 // Single-precision floating-point arithmetic helper functions
593 // RTABI chapter 4.1.2, Table 4
594 { RTLIB::ADD_F32, "__aeabi_fadd", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
595 { RTLIB::DIV_F32, "__aeabi_fdiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
596 { RTLIB::MUL_F32, "__aeabi_fmul", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
597 { RTLIB::SUB_F32, "__aeabi_fsub", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
598
599 // Single-precision floating-point comparison helper functions
600 // RTABI chapter 4.1.2, Table 5
601 { RTLIB::OEQ_F32, "__aeabi_fcmpeq", CallingConv::ARM_AAPCS, ISD::SETNE },
602 { RTLIB::UNE_F32, "__aeabi_fcmpeq", CallingConv::ARM_AAPCS, ISD::SETEQ },
603 { RTLIB::OLT_F32, "__aeabi_fcmplt", CallingConv::ARM_AAPCS, ISD::SETNE },
604 { RTLIB::OLE_F32, "__aeabi_fcmple", CallingConv::ARM_AAPCS, ISD::SETNE },
605 { RTLIB::OGE_F32, "__aeabi_fcmpge", CallingConv::ARM_AAPCS, ISD::SETNE },
606 { RTLIB::OGT_F32, "__aeabi_fcmpgt", CallingConv::ARM_AAPCS, ISD::SETNE },
607 { RTLIB::UO_F32, "__aeabi_fcmpun", CallingConv::ARM_AAPCS, ISD::SETNE },
608
609 // Floating-point to integer conversions.
610 // RTABI chapter 4.1.2, Table 6
611 { RTLIB::FPTOSINT_F64_I32, "__aeabi_d2iz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
612 { RTLIB::FPTOUINT_F64_I32, "__aeabi_d2uiz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
613 { RTLIB::FPTOSINT_F64_I64, "__aeabi_d2lz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
614 { RTLIB::FPTOUINT_F64_I64, "__aeabi_d2ulz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
615 { RTLIB::FPTOSINT_F32_I32, "__aeabi_f2iz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
616 { RTLIB::FPTOUINT_F32_I32, "__aeabi_f2uiz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
617 { RTLIB::FPTOSINT_F32_I64, "__aeabi_f2lz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
618 { RTLIB::FPTOUINT_F32_I64, "__aeabi_f2ulz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
619
620 // Conversions between floating types.
621 // RTABI chapter 4.1.2, Table 7
622 { RTLIB::FPROUND_F64_F32, "__aeabi_d2f", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
623 { RTLIB::FPROUND_F64_F16, "__aeabi_d2h", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
624 { RTLIB::FPEXT_F32_F64, "__aeabi_f2d", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
625
626 // Integer to floating-point conversions.
627 // RTABI chapter 4.1.2, Table 8
628 { RTLIB::SINTTOFP_I32_F64, "__aeabi_i2d", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
629 { RTLIB::UINTTOFP_I32_F64, "__aeabi_ui2d", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
630 { RTLIB::SINTTOFP_I64_F64, "__aeabi_l2d", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
631 { RTLIB::UINTTOFP_I64_F64, "__aeabi_ul2d", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
632 { RTLIB::SINTTOFP_I32_F32, "__aeabi_i2f", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
633 { RTLIB::UINTTOFP_I32_F32, "__aeabi_ui2f", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
634 { RTLIB::SINTTOFP_I64_F32, "__aeabi_l2f", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
635 { RTLIB::UINTTOFP_I64_F32, "__aeabi_ul2f", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
636
637 // Long long helper functions
638 // RTABI chapter 4.2, Table 9
639 { RTLIB::MUL_I64, "__aeabi_lmul", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
640 { RTLIB::SHL_I64, "__aeabi_llsl", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
641 { RTLIB::SRL_I64, "__aeabi_llsr", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
642 { RTLIB::SRA_I64, "__aeabi_lasr", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
643
644 // Integer division functions
645 // RTABI chapter 4.3.1
646 { RTLIB::SDIV_I8, "__aeabi_idiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
647 { RTLIB::SDIV_I16, "__aeabi_idiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
648 { RTLIB::SDIV_I32, "__aeabi_idiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
649 { RTLIB::SDIV_I64, "__aeabi_ldivmod", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
650 { RTLIB::UDIV_I8, "__aeabi_uidiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
651 { RTLIB::UDIV_I16, "__aeabi_uidiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
652 { RTLIB::UDIV_I32, "__aeabi_uidiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
653 { RTLIB::UDIV_I64, "__aeabi_uldivmod", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
654 };
655
656 for (const auto &LC : LibraryCalls) {
657 setLibcallName(LC.Op, LC.Name);
658 setLibcallCallingConv(LC.Op, LC.CC);
659 if (LC.Cond != ISD::SETCC_INVALID)
660 setCmpLibcallCC(LC.Op, LC.Cond);
661 }
662
663 // EABI dependent RTLIB
664 if (TM.Options.EABIVersion == EABI::EABI4 ||
665 TM.Options.EABIVersion == EABI::EABI5) {
666 static const struct {
667 const RTLIB::Libcall Op;
668 const char *const Name;
669 const CallingConv::ID CC;
670 const ISD::CondCode Cond;
671 } MemOpsLibraryCalls[] = {
672 // Memory operations
673 // RTABI chapter 4.3.4
674 { RTLIB::MEMCPY, "__aeabi_memcpy", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
675 { RTLIB::MEMMOVE, "__aeabi_memmove", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
676 { RTLIB::MEMSET, "__aeabi_memset", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
677 };
678
679 for (const auto &LC : MemOpsLibraryCalls) {
680 setLibcallName(LC.Op, LC.Name);
681 setLibcallCallingConv(LC.Op, LC.CC);
682 if (LC.Cond != ISD::SETCC_INVALID)
683 setCmpLibcallCC(LC.Op, LC.Cond);
684 }
685 }
686 }
687
688 if (Subtarget->isTargetWindows()) {
689 static const struct {
690 const RTLIB::Libcall Op;
691 const char * const Name;
692 const CallingConv::ID CC;
693 } LibraryCalls[] = {
694 { RTLIB::FPTOSINT_F32_I64, "__stoi64", CallingConv::ARM_AAPCS_VFP },
695 { RTLIB::FPTOSINT_F64_I64, "__dtoi64", CallingConv::ARM_AAPCS_VFP },
696 { RTLIB::FPTOUINT_F32_I64, "__stou64", CallingConv::ARM_AAPCS_VFP },
697 { RTLIB::FPTOUINT_F64_I64, "__dtou64", CallingConv::ARM_AAPCS_VFP },
698 { RTLIB::SINTTOFP_I64_F32, "__i64tos", CallingConv::ARM_AAPCS_VFP },
699 { RTLIB::SINTTOFP_I64_F64, "__i64tod", CallingConv::ARM_AAPCS_VFP },
700 { RTLIB::UINTTOFP_I64_F32, "__u64tos", CallingConv::ARM_AAPCS_VFP },
701 { RTLIB::UINTTOFP_I64_F64, "__u64tod", CallingConv::ARM_AAPCS_VFP },
702 };
703
704 for (const auto &LC : LibraryCalls) {
705 setLibcallName(LC.Op, LC.Name);
706 setLibcallCallingConv(LC.Op, LC.CC);
707 }
708 }
709
710 // Use divmod compiler-rt calls for iOS 5.0 and later.
711 if (Subtarget->isTargetMachO() &&
712 !(Subtarget->isTargetIOS() &&
713 Subtarget->getTargetTriple().isOSVersionLT(5, 0))) {
714 setLibcallName(RTLIB::SDIVREM_I32, "__divmodsi4");
715 setLibcallName(RTLIB::UDIVREM_I32, "__udivmodsi4");
716 }
717
718 // The half <-> float conversion functions are always soft-float on
719 // non-watchos platforms, but are needed for some targets which use a
720 // hard-float calling convention by default.
721 if (!Subtarget->isTargetWatchABI()) {
722 if (Subtarget->isAAPCS_ABI()) {
723 setLibcallCallingConv(RTLIB::FPROUND_F32_F16, CallingConv::ARM_AAPCS);
724 setLibcallCallingConv(RTLIB::FPROUND_F64_F16, CallingConv::ARM_AAPCS);
725 setLibcallCallingConv(RTLIB::FPEXT_F16_F32, CallingConv::ARM_AAPCS);
726 } else {
727 setLibcallCallingConv(RTLIB::FPROUND_F32_F16, CallingConv::ARM_APCS);
728 setLibcallCallingConv(RTLIB::FPROUND_F64_F16, CallingConv::ARM_APCS);
729 setLibcallCallingConv(RTLIB::FPEXT_F16_F32, CallingConv::ARM_APCS);
730 }
731 }
732
733 // In EABI, these functions have an __aeabi_ prefix, but in GNUEABI they have
734 // a __gnu_ prefix (which is the default).
735 if (Subtarget->isTargetAEABI()) {
736 static const struct {
737 const RTLIB::Libcall Op;
738 const char * const Name;
739 const CallingConv::ID CC;
740 } LibraryCalls[] = {
741 { RTLIB::FPROUND_F32_F16, "__aeabi_f2h", CallingConv::ARM_AAPCS },
742 { RTLIB::FPROUND_F64_F16, "__aeabi_d2h", CallingConv::ARM_AAPCS },
743 { RTLIB::FPEXT_F16_F32, "__aeabi_h2f", CallingConv::ARM_AAPCS },
744 };
745
746 for (const auto &LC : LibraryCalls) {
747 setLibcallName(LC.Op, LC.Name);
748 setLibcallCallingConv(LC.Op, LC.CC);
749 }
750 }
751
752 if (Subtarget->isThumb1Only())
753 addRegisterClass(MVT::i32, &ARM::tGPRRegClass);
754 else
755 addRegisterClass(MVT::i32, &ARM::GPRRegClass);
756
757 if (!Subtarget->useSoftFloat() && !Subtarget->isThumb1Only() &&
758 Subtarget->hasFPRegs()) {
759 addRegisterClass(MVT::f32, &ARM::SPRRegClass);
760 addRegisterClass(MVT::f64, &ARM::DPRRegClass);
761
762 setOperationAction(ISD::FP_TO_SINT_SAT, MVT::i32, Custom);
763 setOperationAction(ISD::FP_TO_UINT_SAT, MVT::i32, Custom);
764 setOperationAction(ISD::FP_TO_SINT_SAT, MVT::i64, Custom);
765 setOperationAction(ISD::FP_TO_UINT_SAT, MVT::i64, Custom);
766
767 if (!Subtarget->hasVFP2Base())
768 setAllExpand(MVT::f32);
769 if (!Subtarget->hasFP64())
770 setAllExpand(MVT::f64);
771 }
772
773 if (Subtarget->hasFullFP16()) {
774 addRegisterClass(MVT::f16, &ARM::HPRRegClass);
775 setOperationAction(ISD::BITCAST, MVT::i16, Custom);
776 setOperationAction(ISD::BITCAST, MVT::f16, Custom);
777
778 setOperationAction(ISD::FMINNUM, MVT::f16, Legal);
779 setOperationAction(ISD::FMAXNUM, MVT::f16, Legal);
780 }
781
782 if (Subtarget->hasBF16()) {
783 addRegisterClass(MVT::bf16, &ARM::HPRRegClass);
784 setAllExpand(MVT::bf16);
785 if (!Subtarget->hasFullFP16())
786 setOperationAction(ISD::BITCAST, MVT::bf16, Custom);
787 }
788
789 for (MVT VT : MVT::fixedlen_vector_valuetypes()) {
790 for (MVT InnerVT : MVT::fixedlen_vector_valuetypes()) {
791 setTruncStoreAction(VT, InnerVT, Expand);
792 addAllExtLoads(VT, InnerVT, Expand);
793 }
794
795 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
796 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
797
798 setOperationAction(ISD::BSWAP, VT, Expand);
799 }
800
801 setOperationAction(ISD::ConstantFP, MVT::f32, Custom);
802 setOperationAction(ISD::ConstantFP, MVT::f64, Custom);
803
804 setOperationAction(ISD::READ_REGISTER, MVT::i64, Custom);
805 setOperationAction(ISD::WRITE_REGISTER, MVT::i64, Custom);
806
807 if (Subtarget->hasMVEIntegerOps())
808 addMVEVectorTypes(Subtarget->hasMVEFloatOps());
809
810 // Combine low-overhead loop intrinsics so that we can lower i1 types.
811 if (Subtarget->hasLOB()) {
812 setTargetDAGCombine(ISD::BRCOND);
813 setTargetDAGCombine(ISD::BR_CC);
814 }
815
816 if (Subtarget->hasNEON()) {
817 addDRTypeForNEON(MVT::v2f32);
818 addDRTypeForNEON(MVT::v8i8);
819 addDRTypeForNEON(MVT::v4i16);
820 addDRTypeForNEON(MVT::v2i32);
821 addDRTypeForNEON(MVT::v1i64);
822
823 addQRTypeForNEON(MVT::v4f32);
824 addQRTypeForNEON(MVT::v2f64);
825 addQRTypeForNEON(MVT::v16i8);
826 addQRTypeForNEON(MVT::v8i16);
827 addQRTypeForNEON(MVT::v4i32);
828 addQRTypeForNEON(MVT::v2i64);
829
830 if (Subtarget->hasFullFP16()) {
831 addQRTypeForNEON(MVT::v8f16);
832 addDRTypeForNEON(MVT::v4f16);
833 }
834
835 if (Subtarget->hasBF16()) {
836 addQRTypeForNEON(MVT::v8bf16);
837 addDRTypeForNEON(MVT::v4bf16);
838 }
839 }
840
841 if (Subtarget->hasMVEIntegerOps() || Subtarget->hasNEON()) {
842 // v2f64 is legal so that QR subregs can be extracted as f64 elements, but
843 // none of Neon, MVE or VFP supports any arithmetic operations on it.
844 setOperationAction(ISD::FADD, MVT::v2f64, Expand);
845 setOperationAction(ISD::FSUB, MVT::v2f64, Expand);
846 setOperationAction(ISD::FMUL, MVT::v2f64, Expand);
847 // FIXME: Code duplication: FDIV and FREM are expanded always, see
848 // ARMTargetLowering::addTypeForNEON method for details.
849 setOperationAction(ISD::FDIV, MVT::v2f64, Expand);
850 setOperationAction(ISD::FREM, MVT::v2f64, Expand);
851 // FIXME: Create unittest.
852 // In another words, find a way when "copysign" appears in DAG with vector
853 // operands.
854 setOperationAction(ISD::FCOPYSIGN, MVT::v2f64, Expand);
855 // FIXME: Code duplication: SETCC has custom operation action, see
856 // ARMTargetLowering::addTypeForNEON method for details.
857 setOperationAction(ISD::SETCC, MVT::v2f64, Expand);
858 // FIXME: Create unittest for FNEG and for FABS.
859 setOperationAction(ISD::FNEG, MVT::v2f64, Expand);
860 setOperationAction(ISD::FABS, MVT::v2f64, Expand);
861 setOperationAction(ISD::FSQRT, MVT::v2f64, Expand);
862 setOperationAction(ISD::FSIN, MVT::v2f64, Expand);
863 setOperationAction(ISD::FCOS, MVT::v2f64, Expand);
864 setOperationAction(ISD::FPOW, MVT::v2f64, Expand);
865 setOperationAction(ISD::FLOG, MVT::v2f64, Expand);
866 setOperationAction(ISD::FLOG2, MVT::v2f64, Expand);
867 setOperationAction(ISD::FLOG10, MVT::v2f64, Expand);
868 setOperationAction(ISD::FEXP, MVT::v2f64, Expand);
869 setOperationAction(ISD::FEXP2, MVT::v2f64, Expand);
870 // FIXME: Create unittest for FCEIL, FTRUNC, FRINT, FNEARBYINT, FFLOOR.
871 setOperationAction(ISD::FCEIL, MVT::v2f64, Expand);
872 setOperationAction(ISD::FTRUNC, MVT::v2f64, Expand);
873 setOperationAction(ISD::FRINT, MVT::v2f64, Expand);
874 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Expand);
875 setOperationAction(ISD::FFLOOR, MVT::v2f64, Expand);
876 setOperationAction(ISD::FMA, MVT::v2f64, Expand);
877 }
878
879 if (Subtarget->hasNEON()) {
880 // The same with v4f32. But keep in mind that vadd, vsub, vmul are natively
881 // supported for v4f32.
882 setOperationAction(ISD::FSQRT, MVT::v4f32, Expand);
883 setOperationAction(ISD::FSIN, MVT::v4f32, Expand);
884 setOperationAction(ISD::FCOS, MVT::v4f32, Expand);
885 setOperationAction(ISD::FPOW, MVT::v4f32, Expand);
886 setOperationAction(ISD::FLOG, MVT::v4f32, Expand);
887 setOperationAction(ISD::FLOG2, MVT::v4f32, Expand);
888 setOperationAction(ISD::FLOG10, MVT::v4f32, Expand);
889 setOperationAction(ISD::FEXP, MVT::v4f32, Expand);
890 setOperationAction(ISD::FEXP2, MVT::v4f32, Expand);
891 setOperationAction(ISD::FCEIL, MVT::v4f32, Expand);
892 setOperationAction(ISD::FTRUNC, MVT::v4f32, Expand);
893 setOperationAction(ISD::FRINT, MVT::v4f32, Expand);
894 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Expand);
895 setOperationAction(ISD::FFLOOR, MVT::v4f32, Expand);
896
897 // Mark v2f32 intrinsics.
898 setOperationAction(ISD::FSQRT, MVT::v2f32, Expand);
899 setOperationAction(ISD::FSIN, MVT::v2f32, Expand);
900 setOperationAction(ISD::FCOS, MVT::v2f32, Expand);
901 setOperationAction(ISD::FPOW, MVT::v2f32, Expand);
902 setOperationAction(ISD::FLOG, MVT::v2f32, Expand);
903 setOperationAction(ISD::FLOG2, MVT::v2f32, Expand);
904 setOperationAction(ISD::FLOG10, MVT::v2f32, Expand);
905 setOperationAction(ISD::FEXP, MVT::v2f32, Expand);
906 setOperationAction(ISD::FEXP2, MVT::v2f32, Expand);
907 setOperationAction(ISD::FCEIL, MVT::v2f32, Expand);
908 setOperationAction(ISD::FTRUNC, MVT::v2f32, Expand);
909 setOperationAction(ISD::FRINT, MVT::v2f32, Expand);
910 setOperationAction(ISD::FNEARBYINT, MVT::v2f32, Expand);
911 setOperationAction(ISD::FFLOOR, MVT::v2f32, Expand);
912
913 // Neon does not support some operations on v1i64 and v2i64 types.
914 setOperationAction(ISD::MUL, MVT::v1i64, Expand);
915 // Custom handling for some quad-vector types to detect VMULL.
916 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
917 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
918 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
919 // Custom handling for some vector types to avoid expensive expansions
920 setOperationAction(ISD::SDIV, MVT::v4i16, Custom);
921 setOperationAction(ISD::SDIV, MVT::v8i8, Custom);
922 setOperationAction(ISD::UDIV, MVT::v4i16, Custom);
923 setOperationAction(ISD::UDIV, MVT::v8i8, Custom);
924 // Neon does not have single instruction SINT_TO_FP and UINT_TO_FP with
925 // a destination type that is wider than the source, and nor does
926 // it have a FP_TO_[SU]INT instruction with a narrower destination than
927 // source.
928 setOperationAction(ISD::SINT_TO_FP, MVT::v4i16, Custom);
929 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Custom);
930 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
931 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom);
932 setOperationAction(ISD::FP_TO_UINT, MVT::v4i16, Custom);
933 setOperationAction(ISD::FP_TO_UINT, MVT::v8i16, Custom);
934 setOperationAction(ISD::FP_TO_SINT, MVT::v4i16, Custom);
935 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Custom);
936
937 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Expand);
938 setOperationAction(ISD::FP_EXTEND, MVT::v2f64, Expand);
939
940 // NEON does not have single instruction CTPOP for vectors with element
941 // types wider than 8-bits. However, custom lowering can leverage the
942 // v8i8/v16i8 vcnt instruction.
943 setOperationAction(ISD::CTPOP, MVT::v2i32, Custom);
944 setOperationAction(ISD::CTPOP, MVT::v4i32, Custom);
945 setOperationAction(ISD::CTPOP, MVT::v4i16, Custom);
946 setOperationAction(ISD::CTPOP, MVT::v8i16, Custom);
947 setOperationAction(ISD::CTPOP, MVT::v1i64, Custom);
948 setOperationAction(ISD::CTPOP, MVT::v2i64, Custom);
949
950 setOperationAction(ISD::CTLZ, MVT::v1i64, Expand);
951 setOperationAction(ISD::CTLZ, MVT::v2i64, Expand);
952
953 // NEON does not have single instruction CTTZ for vectors.
954 setOperationAction(ISD::CTTZ, MVT::v8i8, Custom);
955 setOperationAction(ISD::CTTZ, MVT::v4i16, Custom);
956 setOperationAction(ISD::CTTZ, MVT::v2i32, Custom);
957 setOperationAction(ISD::CTTZ, MVT::v1i64, Custom);
958
959 setOperationAction(ISD::CTTZ, MVT::v16i8, Custom);
960 setOperationAction(ISD::CTTZ, MVT::v8i16, Custom);
961 setOperationAction(ISD::CTTZ, MVT::v4i32, Custom);
962 setOperationAction(ISD::CTTZ, MVT::v2i64, Custom);
963
964 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v8i8, Custom);
965 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v4i16, Custom);
966 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v2i32, Custom);
967 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v1i64, Custom);
968
969 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v16i8, Custom);
970 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v8i16, Custom);
971 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v4i32, Custom);
972 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v2i64, Custom);
973
974 for (MVT VT : MVT::fixedlen_vector_valuetypes()) {
975 setOperationAction(ISD::MULHS, VT, Expand);
976 setOperationAction(ISD::MULHU, VT, Expand);
977 }
978
979 // NEON only has FMA instructions as of VFP4.
980 if (!Subtarget->hasVFP4Base()) {
981 setOperationAction(ISD::FMA, MVT::v2f32, Expand);
982 setOperationAction(ISD::FMA, MVT::v4f32, Expand);
983 }
984
985 setTargetDAGCombine(ISD::SHL);
986 setTargetDAGCombine(ISD::SRL);
987 setTargetDAGCombine(ISD::SRA);
988 setTargetDAGCombine(ISD::FP_TO_SINT);
989 setTargetDAGCombine(ISD::FP_TO_UINT);
990 setTargetDAGCombine(ISD::FDIV);
991 setTargetDAGCombine(ISD::LOAD);
992
993 // It is legal to extload from v4i8 to v4i16 or v4i32.
994 for (MVT Ty : {MVT::v8i8, MVT::v4i8, MVT::v2i8, MVT::v4i16, MVT::v2i16,
995 MVT::v2i32}) {
996 for (MVT VT : MVT::integer_fixedlen_vector_valuetypes()) {
997 setLoadExtAction(ISD::EXTLOAD, VT, Ty, Legal);
998 setLoadExtAction(ISD::ZEXTLOAD, VT, Ty, Legal);
999 setLoadExtAction(ISD::SEXTLOAD, VT, Ty, Legal);
1000 }
1001 }
1002 }
1003
1004 if (Subtarget->hasNEON() || Subtarget->hasMVEIntegerOps()) {
1005 setTargetDAGCombine(ISD::BUILD_VECTOR);
1006 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1007 setTargetDAGCombine(ISD::INSERT_SUBVECTOR);
1008 setTargetDAGCombine(ISD::INSERT_VECTOR_ELT);
1009 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1010 setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
1011 setTargetDAGCombine(ISD::STORE);
1012 setTargetDAGCombine(ISD::SIGN_EXTEND);
1013 setTargetDAGCombine(ISD::ZERO_EXTEND);
1014 setTargetDAGCombine(ISD::ANY_EXTEND);
1015 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
1016 setTargetDAGCombine(ISD::INTRINSIC_W_CHAIN);
1017 setTargetDAGCombine(ISD::INTRINSIC_VOID);
1018 setTargetDAGCombine(ISD::VECREDUCE_ADD);
1019 setTargetDAGCombine(ISD::ADD);
1020 setTargetDAGCombine(ISD::BITCAST);
1021 }
1022 if (Subtarget->hasMVEIntegerOps()) {
1023 setTargetDAGCombine(ISD::SMIN);
1024 setTargetDAGCombine(ISD::UMIN);
1025 setTargetDAGCombine(ISD::SMAX);
1026 setTargetDAGCombine(ISD::UMAX);
1027 setTargetDAGCombine(ISD::FP_EXTEND);
1028 setTargetDAGCombine(ISD::SELECT);
1029 setTargetDAGCombine(ISD::SELECT_CC);
1030 setTargetDAGCombine(ISD::SETCC);
1031 }
1032 if (Subtarget->hasMVEFloatOps()) {
1033 setTargetDAGCombine(ISD::FADD);
1034 }
1035
1036 if (!Subtarget->hasFP64()) {
1037 // When targeting a floating-point unit with only single-precision
1038 // operations, f64 is legal for the few double-precision instructions which
1039 // are present However, no double-precision operations other than moves,
1040 // loads and stores are provided by the hardware.
1041 setOperationAction(ISD::FADD, MVT::f64, Expand);
1042 setOperationAction(ISD::FSUB, MVT::f64, Expand);
1043 setOperationAction(ISD::FMUL, MVT::f64, Expand);
1044 setOperationAction(ISD::FMA, MVT::f64, Expand);
1045 setOperationAction(ISD::FDIV, MVT::f64, Expand);
1046 setOperationAction(ISD::FREM, MVT::f64, Expand);
1047 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
1048 setOperationAction(ISD::FGETSIGN, MVT::f64, Expand);
1049 setOperationAction(ISD::FNEG, MVT::f64, Expand);
1050 setOperationAction(ISD::FABS, MVT::f64, Expand);
1051 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
1052 setOperationAction(ISD::FSIN, MVT::f64, Expand);
1053 setOperationAction(ISD::FCOS, MVT::f64, Expand);
1054 setOperationAction(ISD::FPOW, MVT::f64, Expand);
1055 setOperationAction(ISD::FLOG, MVT::f64, Expand);
1056 setOperationAction(ISD::FLOG2, MVT::f64, Expand);
1057 setOperationAction(ISD::FLOG10, MVT::f64, Expand);
1058 setOperationAction(ISD::FEXP, MVT::f64, Expand);
1059 setOperationAction(ISD::FEXP2, MVT::f64, Expand);
1060 setOperationAction(ISD::FCEIL, MVT::f64, Expand);
1061 setOperationAction(ISD::FTRUNC, MVT::f64, Expand);
1062 setOperationAction(ISD::FRINT, MVT::f64, Expand);
1063 setOperationAction(ISD::FNEARBYINT, MVT::f64, Expand);
1064 setOperationAction(ISD::FFLOOR, MVT::f64, Expand);
1065 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
1066 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
1067 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
1068 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
1069 setOperationAction(ISD::FP_TO_SINT, MVT::f64, Custom);
1070 setOperationAction(ISD::FP_TO_UINT, MVT::f64, Custom);
1071 setOperationAction(ISD::FP_ROUND, MVT::f32, Custom);
1072 setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::i32, Custom);
1073 setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::i32, Custom);
1074 setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::f64, Custom);
1075 setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::f64, Custom);
1076 setOperationAction(ISD::STRICT_FP_ROUND, MVT::f32, Custom);
1077 }
1078
1079 if (!Subtarget->hasFP64() || !Subtarget->hasFPARMv8Base()) {
1080 setOperationAction(ISD::FP_EXTEND, MVT::f64, Custom);
1081 setOperationAction(ISD::STRICT_FP_EXTEND, MVT::f64, Custom);
1082 if (Subtarget->hasFullFP16()) {
1083 setOperationAction(ISD::FP_ROUND, MVT::f16, Custom);
1084 setOperationAction(ISD::STRICT_FP_ROUND, MVT::f16, Custom);
1085 }
1086 }
1087
1088 if (!Subtarget->hasFP16()) {
1089 setOperationAction(ISD::FP_EXTEND, MVT::f32, Custom);
1090 setOperationAction(ISD::STRICT_FP_EXTEND, MVT::f32, Custom);
1091 }
1092
1093 computeRegisterProperties(Subtarget->getRegisterInfo());
1094
1095 // ARM does not have floating-point extending loads.
1096 for (MVT VT : MVT::fp_valuetypes()) {
1097 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f32, Expand);
1098 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f16, Expand);
1099 }
1100
1101 // ... or truncating stores
1102 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
1103 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
1104 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
1105
1106 // ARM does not have i1 sign extending load.
1107 for (MVT VT : MVT::integer_valuetypes())
1108 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
1109
1110 // ARM supports all 4 flavors of integer indexed load / store.
1111 if (!Subtarget->isThumb1Only()) {
1112 for (unsigned im = (unsigned)ISD::PRE_INC;
1113 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
1114 setIndexedLoadAction(im, MVT::i1, Legal);
1115 setIndexedLoadAction(im, MVT::i8, Legal);
1116 setIndexedLoadAction(im, MVT::i16, Legal);
1117 setIndexedLoadAction(im, MVT::i32, Legal);
1118 setIndexedStoreAction(im, MVT::i1, Legal);
1119 setIndexedStoreAction(im, MVT::i8, Legal);
1120 setIndexedStoreAction(im, MVT::i16, Legal);
1121 setIndexedStoreAction(im, MVT::i32, Legal);
1122 }
1123 } else {
1124 // Thumb-1 has limited post-inc load/store support - LDM r0!, {r1}.
1125 setIndexedLoadAction(ISD::POST_INC, MVT::i32, Legal);
1126 setIndexedStoreAction(ISD::POST_INC, MVT::i32, Legal);
1127 }
1128
1129 setOperationAction(ISD::SADDO, MVT::i32, Custom);
1130 setOperationAction(ISD::UADDO, MVT::i32, Custom);
1131 setOperationAction(ISD::SSUBO, MVT::i32, Custom);
1132 setOperationAction(ISD::USUBO, MVT::i32, Custom);
1133
1134 setOperationAction(ISD::ADDCARRY, MVT::i32, Custom);
1135 setOperationAction(ISD::SUBCARRY, MVT::i32, Custom);
1136 if (Subtarget->hasDSP()) {
1137 setOperationAction(ISD::SADDSAT, MVT::i8, Custom);
1138 setOperationAction(ISD::SSUBSAT, MVT::i8, Custom);
1139 setOperationAction(ISD::SADDSAT, MVT::i16, Custom);
1140 setOperationAction(ISD::SSUBSAT, MVT::i16, Custom);
1141 setOperationAction(ISD::UADDSAT, MVT::i8, Custom);
1142 setOperationAction(ISD::USUBSAT, MVT::i8, Custom);
1143 setOperationAction(ISD::UADDSAT, MVT::i16, Custom);
1144 setOperationAction(ISD::USUBSAT, MVT::i16, Custom);
1145 }
1146 if (Subtarget->hasBaseDSP()) {
1147 setOperationAction(ISD::SADDSAT, MVT::i32, Legal);
1148 setOperationAction(ISD::SSUBSAT, MVT::i32, Legal);
1149 }
1150
1151 // i64 operation support.
1152 setOperationAction(ISD::MUL, MVT::i64, Expand);
1153 setOperationAction(ISD::MULHU, MVT::i32, Expand);
1154 if (Subtarget->isThumb1Only()) {
1155 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
1156 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
1157 }
1158 if (Subtarget->isThumb1Only() || !Subtarget->hasV6Ops()
1159 || (Subtarget->isThumb2() && !Subtarget->hasDSP()))
1160 setOperationAction(ISD::MULHS, MVT::i32, Expand);
1161
1162 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
1163 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
1164 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
1165 setOperationAction(ISD::SRL, MVT::i64, Custom);
1166 setOperationAction(ISD::SRA, MVT::i64, Custom);
1167 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
1168 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i64, Custom);
1169 setOperationAction(ISD::LOAD, MVT::i64, Custom);
1170 setOperationAction(ISD::STORE, MVT::i64, Custom);
1171
1172 // MVE lowers 64 bit shifts to lsll and lsrl
1173 // assuming that ISD::SRL and SRA of i64 are already marked custom
1174 if (Subtarget->hasMVEIntegerOps())
1175 setOperationAction(ISD::SHL, MVT::i64, Custom);
1176
1177 // Expand to __aeabi_l{lsl,lsr,asr} calls for Thumb1.
1178 if (Subtarget->isThumb1Only()) {
1179 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
1180 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
1181 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
1182 }
1183
1184 if (!Subtarget->isThumb1Only() && Subtarget->hasV6T2Ops())
1185 setOperationAction(ISD::BITREVERSE, MVT::i32, Legal);
1186
1187 // ARM does not have ROTL.
1188 setOperationAction(ISD::ROTL, MVT::i32, Expand);
1189 for (MVT VT : MVT::fixedlen_vector_valuetypes()) {
1190 setOperationAction(ISD::ROTL, VT, Expand);
1191 setOperationAction(ISD::ROTR, VT, Expand);
1192 }
1193 setOperationAction(ISD::CTTZ, MVT::i32, Custom);
1194 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
1195 if (!Subtarget->hasV5TOps() || Subtarget->isThumb1Only()) {
1196 setOperationAction(ISD::CTLZ, MVT::i32, Expand);
1197 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, LibCall);
1198 }
1199
1200 // @llvm.readcyclecounter requires the Performance Monitors extension.
1201 // Default to the 0 expansion on unsupported platforms.
1202 // FIXME: Technically there are older ARM CPUs that have
1203 // implementation-specific ways of obtaining this information.
1204 if (Subtarget->hasPerfMon())
1205 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Custom);
1206
1207 // Only ARMv6 has BSWAP.
1208 if (!Subtarget->hasV6Ops())
1209 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
1210
1211 bool hasDivide = Subtarget->isThumb() ? Subtarget->hasDivideInThumbMode()
1212 : Subtarget->hasDivideInARMMode();
1213 if (!hasDivide) {
1214 // These are expanded into libcalls if the cpu doesn't have HW divider.
1215 setOperationAction(ISD::SDIV, MVT::i32, LibCall);
1216 setOperationAction(ISD::UDIV, MVT::i32, LibCall);
1217 }
1218
1219 if (Subtarget->isTargetWindows() && !Subtarget->hasDivideInThumbMode()) {
1220 setOperationAction(ISD::SDIV, MVT::i32, Custom);
1221 setOperationAction(ISD::UDIV, MVT::i32, Custom);
1222
1223 setOperationAction(ISD::SDIV, MVT::i64, Custom);
1224 setOperationAction(ISD::UDIV, MVT::i64, Custom);
1225 }
1226
1227 setOperationAction(ISD::SREM, MVT::i32, Expand);
1228 setOperationAction(ISD::UREM, MVT::i32, Expand);
1229
1230 // Register based DivRem for AEABI (RTABI 4.2)
1231 if (Subtarget->isTargetAEABI() || Subtarget->isTargetAndroid() ||
1232 Subtarget->isTargetGNUAEABI() || Subtarget->isTargetMuslAEABI() ||
1233 Subtarget->isTargetWindows()) {
1234 setOperationAction(ISD::SREM, MVT::i64, Custom);
1235 setOperationAction(ISD::UREM, MVT::i64, Custom);
1236 HasStandaloneRem = false;
1237
1238 if (Subtarget->isTargetWindows()) {
1239 const struct {
1240 const RTLIB::Libcall Op;
1241 const char * const Name;
1242 const CallingConv::ID CC;
1243 } LibraryCalls[] = {
1244 { RTLIB::SDIVREM_I8, "__rt_sdiv", CallingConv::ARM_AAPCS },
1245 { RTLIB::SDIVREM_I16, "__rt_sdiv", CallingConv::ARM_AAPCS },
1246 { RTLIB::SDIVREM_I32, "__rt_sdiv", CallingConv::ARM_AAPCS },
1247 { RTLIB::SDIVREM_I64, "__rt_sdiv64", CallingConv::ARM_AAPCS },
1248
1249 { RTLIB::UDIVREM_I8, "__rt_udiv", CallingConv::ARM_AAPCS },
1250 { RTLIB::UDIVREM_I16, "__rt_udiv", CallingConv::ARM_AAPCS },
1251 { RTLIB::UDIVREM_I32, "__rt_udiv", CallingConv::ARM_AAPCS },
1252 { RTLIB::UDIVREM_I64, "__rt_udiv64", CallingConv::ARM_AAPCS },
1253 };
1254
1255 for (const auto &LC : LibraryCalls) {
1256 setLibcallName(LC.Op, LC.Name);
1257 setLibcallCallingConv(LC.Op, LC.CC);
1258 }
1259 } else {
1260 const struct {
1261 const RTLIB::Libcall Op;
1262 const char * const Name;
1263 const CallingConv::ID CC;
1264 } LibraryCalls[] = {
1265 { RTLIB::SDIVREM_I8, "__aeabi_idivmod", CallingConv::ARM_AAPCS },
1266 { RTLIB::SDIVREM_I16, "__aeabi_idivmod", CallingConv::ARM_AAPCS },
1267 { RTLIB::SDIVREM_I32, "__aeabi_idivmod", CallingConv::ARM_AAPCS },
1268 { RTLIB::SDIVREM_I64, "__aeabi_ldivmod", CallingConv::ARM_AAPCS },
1269
1270 { RTLIB::UDIVREM_I8, "__aeabi_uidivmod", CallingConv::ARM_AAPCS },
1271 { RTLIB::UDIVREM_I16, "__aeabi_uidivmod", CallingConv::ARM_AAPCS },
1272 { RTLIB::UDIVREM_I32, "__aeabi_uidivmod", CallingConv::ARM_AAPCS },
1273 { RTLIB::UDIVREM_I64, "__aeabi_uldivmod", CallingConv::ARM_AAPCS },
1274 };
1275
1276 for (const auto &LC : LibraryCalls) {
1277 setLibcallName(LC.Op, LC.Name);
1278 setLibcallCallingConv(LC.Op, LC.CC);
1279 }
1280 }
1281
1282 setOperationAction(ISD::SDIVREM, MVT::i32, Custom);
1283 setOperationAction(ISD::UDIVREM, MVT::i32, Custom);
1284 setOperationAction(ISD::SDIVREM, MVT::i64, Custom);
1285 setOperationAction(ISD::UDIVREM, MVT::i64, Custom);
1286 } else {
1287 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
1288 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
1289 }
1290
1291 if (Subtarget->getTargetTriple().isOSMSVCRT()) {
1292 // MSVCRT doesn't have powi; fall back to pow
1293 setLibcallName(RTLIB::POWI_F32, nullptr);
1294 setLibcallName(RTLIB::POWI_F64, nullptr);
1295 }
1296
1297 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
1298 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
1299 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
1300 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
1301
1302 setOperationAction(ISD::TRAP, MVT::Other, Legal);
1303 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
1304
1305 // Use the default implementation.
1306 setOperationAction(ISD::VASTART, MVT::Other, Custom);
1307 setOperationAction(ISD::VAARG, MVT::Other, Expand);
1308 setOperationAction(ISD::VACOPY, MVT::Other, Expand);
1309 setOperationAction(ISD::VAEND, MVT::Other, Expand);
1310 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
1311 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
1312
1313 if (Subtarget->isTargetWindows())
1314 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
1315 else
1316 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
1317
1318 // ARMv6 Thumb1 (except for CPUs that support dmb / dsb) and earlier use
1319 // the default expansion.
1320 InsertFencesForAtomic = false;
1321 if (Subtarget->hasAnyDataBarrier() &&
1322 (!Subtarget->isThumb() || Subtarget->hasV8MBaselineOps())) {
1323 // ATOMIC_FENCE needs custom lowering; the others should have been expanded
1324 // to ldrex/strex loops already.
1325 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom);
1326 if (!Subtarget->isThumb() || !Subtarget->isMClass())
1327 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i64, Custom);
1328
1329 // On v8, we have particularly efficient implementations of atomic fences
1330 // if they can be combined with nearby atomic loads and stores.
1331 if (!Subtarget->hasAcquireRelease() ||
1332 getTargetMachine().getOptLevel() == 0) {
1333 // Automatically insert fences (dmb ish) around ATOMIC_SWAP etc.
1334 InsertFencesForAtomic = true;
1335 }
1336 } else {
1337 // If there's anything we can use as a barrier, go through custom lowering
1338 // for ATOMIC_FENCE.
1339 // If target has DMB in thumb, Fences can be inserted.
1340 if (Subtarget->hasDataBarrier())
1341 InsertFencesForAtomic = true;
1342
1343 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other,
1344 Subtarget->hasAnyDataBarrier() ? Custom : Expand);
1345
1346 // Set them all for expansion, which will force libcalls.
1347 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Expand);
1348 setOperationAction(ISD::ATOMIC_SWAP, MVT::i32, Expand);
1349 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i32, Expand);
1350 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Expand);
1351 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i32, Expand);
1352 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i32, Expand);
1353 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i32, Expand);
1354 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i32, Expand);
1355 setOperationAction(ISD::ATOMIC_LOAD_MIN, MVT::i32, Expand);
1356 setOperationAction(ISD::ATOMIC_LOAD_MAX, MVT::i32, Expand);
1357 setOperationAction(ISD::ATOMIC_LOAD_UMIN, MVT::i32, Expand);
1358 setOperationAction(ISD::ATOMIC_LOAD_UMAX, MVT::i32, Expand);
1359 // Mark ATOMIC_LOAD and ATOMIC_STORE custom so we can handle the
1360 // Unordered/Monotonic case.
1361 if (!InsertFencesForAtomic) {
1362 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Custom);
1363 setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Custom);
1364 }
1365 }
1366
1367 setOperationAction(ISD::PREFETCH, MVT::Other, Custom);
1368
1369 // Requires SXTB/SXTH, available on v6 and up in both ARM and Thumb modes.
1370 if (!Subtarget->hasV6Ops()) {
1371 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
1372 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
1373 }
1374 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
1375
1376 if (!Subtarget->useSoftFloat() && Subtarget->hasFPRegs() &&
1377 !Subtarget->isThumb1Only()) {
1378 // Turn f64->i64 into VMOVRRD, i64 -> f64 to VMOVDRR
1379 // iff target supports vfp2.
1380 setOperationAction(ISD::BITCAST, MVT::i64, Custom);
1381 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
1382 setOperationAction(ISD::SET_ROUNDING, MVT::Other, Custom);
1383 }
1384
1385 // We want to custom lower some of our intrinsics.
1386 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1387 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
1388 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
1389 setOperationAction(ISD::EH_SJLJ_SETUP_DISPATCH, MVT::Other, Custom);
1390 if (Subtarget->useSjLjEH())
1391 setLibcallName(RTLIB::UNWIND_RESUME, "_Unwind_SjLj_Resume");
1392
1393 setOperationAction(ISD::SETCC, MVT::i32, Expand);
1394 setOperationAction(ISD::SETCC, MVT::f32, Expand);
1395 setOperationAction(ISD::SETCC, MVT::f64, Expand);
1396 setOperationAction(ISD::SELECT, MVT::i32, Custom);
1397 setOperationAction(ISD::SELECT, MVT::f32, Custom);
1398 setOperationAction(ISD::SELECT, MVT::f64, Custom);
1399 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
1400 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
1401 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
1402 if (Subtarget->hasFullFP16()) {
1403 setOperationAction(ISD::SETCC, MVT::f16, Expand);
1404 setOperationAction(ISD::SELECT, MVT::f16, Custom);
1405 setOperationAction(ISD::SELECT_CC, MVT::f16, Custom);
1406 }
1407
1408 setOperationAction(ISD::SETCCCARRY, MVT::i32, Custom);
1409
1410 setOperationAction(ISD::BRCOND, MVT::Other, Custom);
1411 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
1412 if (Subtarget->hasFullFP16())
1413 setOperationAction(ISD::BR_CC, MVT::f16, Custom);
1414 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
1415 setOperationAction(ISD::BR_CC, MVT::f64, Custom);
1416 setOperationAction(ISD::BR_JT, MVT::Other, Custom);
1417
1418 // We don't support sin/cos/fmod/copysign/pow
1419 setOperationAction(ISD::FSIN, MVT::f64, Expand);
1420 setOperationAction(ISD::FSIN, MVT::f32, Expand);
1421 setOperationAction(ISD::FCOS, MVT::f32, Expand);
1422 setOperationAction(ISD::FCOS, MVT::f64, Expand);
1423 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
1424 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
1425 setOperationAction(ISD::FREM, MVT::f64, Expand);
1426 setOperationAction(ISD::FREM, MVT::f32, Expand);
1427 if (!Subtarget->useSoftFloat() && Subtarget->hasVFP2Base() &&
1428 !Subtarget->isThumb1Only()) {
1429 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
1430 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
1431 }
1432 setOperationAction(ISD::FPOW, MVT::f64, Expand);
1433 setOperationAction(ISD::FPOW, MVT::f32, Expand);
1434
1435 if (!Subtarget->hasVFP4Base()) {
1436 setOperationAction(ISD::FMA, MVT::f64, Expand);
1437 setOperationAction(ISD::FMA, MVT::f32, Expand);
1438 }
1439
1440 // Various VFP goodness
1441 if (!Subtarget->useSoftFloat() && !Subtarget->isThumb1Only()) {
1442 // FP-ARMv8 adds f64 <-> f16 conversion. Before that it should be expanded.
1443 if (!Subtarget->hasFPARMv8Base() || !Subtarget->hasFP64()) {
1444 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
1445 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
1446 }
1447
1448 // fp16 is a special v7 extension that adds f16 <-> f32 conversions.
1449 if (!Subtarget->hasFP16()) {
1450 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
1451 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
1452 }
1453
1454 // Strict floating-point comparisons need custom lowering.
1455 setOperationAction(ISD::STRICT_FSETCC, MVT::f16, Custom);
1456 setOperationAction(ISD::STRICT_FSETCCS, MVT::f16, Custom);
1457 setOperationAction(ISD::STRICT_FSETCC, MVT::f32, Custom);
1458 setOperationAction(ISD::STRICT_FSETCCS, MVT::f32, Custom);
1459 setOperationAction(ISD::STRICT_FSETCC, MVT::f64, Custom);
1460 setOperationAction(ISD::STRICT_FSETCCS, MVT::f64, Custom);
1461 }
1462
1463 // Use __sincos_stret if available.
1464 if (getLibcallName(RTLIB::SINCOS_STRET_F32) != nullptr &&
1465 getLibcallName(RTLIB::SINCOS_STRET_F64) != nullptr) {
1466 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
1467 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
1468 }
1469
1470 // FP-ARMv8 implements a lot of rounding-like FP operations.
1471 if (Subtarget->hasFPARMv8Base()) {
1472 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
1473 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
1474 setOperationAction(ISD::FROUND, MVT::f32, Legal);
1475 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
1476 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
1477 setOperationAction(ISD::FRINT, MVT::f32, Legal);
1478 setOperationAction(ISD::FMINNUM, MVT::f32, Legal);
1479 setOperationAction(ISD::FMAXNUM, MVT::f32, Legal);
1480 if (Subtarget->hasNEON()) {
1481 setOperationAction(ISD::FMINNUM, MVT::v2f32, Legal);
1482 setOperationAction(ISD::FMAXNUM, MVT::v2f32, Legal);
1483 setOperationAction(ISD::FMINNUM, MVT::v4f32, Legal);
1484 setOperationAction(ISD::FMAXNUM, MVT::v4f32, Legal);
1485 }
1486
1487 if (Subtarget->hasFP64()) {
1488 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
1489 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
1490 setOperationAction(ISD::FROUND, MVT::f64, Legal);
1491 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
1492 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
1493 setOperationAction(ISD::FRINT, MVT::f64, Legal);
1494 setOperationAction(ISD::FMINNUM, MVT::f64, Legal);
1495 setOperationAction(ISD::FMAXNUM, MVT::f64, Legal);
1496 }
1497 }
1498
1499 // FP16 often need to be promoted to call lib functions
1500 if (Subtarget->hasFullFP16()) {
1501 setOperationAction(ISD::FREM, MVT::f16, Promote);
1502 setOperationAction(ISD::FCOPYSIGN, MVT::f16, Expand);
1503 setOperationAction(ISD::FSIN, MVT::f16, Promote);
1504 setOperationAction(ISD::FCOS, MVT::f16, Promote);
1505 setOperationAction(ISD::FSINCOS, MVT::f16, Promote);
1506 setOperationAction(ISD::FPOWI, MVT::f16, Promote);
1507 setOperationAction(ISD::FPOW, MVT::f16, Promote);
1508 setOperationAction(ISD::FEXP, MVT::f16, Promote);
1509 setOperationAction(ISD::FEXP2, MVT::f16, Promote);
1510 setOperationAction(ISD::FLOG, MVT::f16, Promote);
1511 setOperationAction(ISD::FLOG10, MVT::f16, Promote);
1512 setOperationAction(ISD::FLOG2, MVT::f16, Promote);
1513
1514 setOperationAction(ISD::FROUND, MVT::f16, Legal);
1515 }
1516
1517 if (Subtarget->hasNEON()) {
1518 // vmin and vmax aren't available in a scalar form, so we can use
1519 // a NEON instruction with an undef lane instead. This has a performance
1520 // penalty on some cores, so we don't do this unless we have been
1521 // asked to by the core tuning model.
1522 if (Subtarget->useNEONForSinglePrecisionFP()) {
1523 setOperationAction(ISD::FMINIMUM, MVT::f32, Legal);
1524 setOperationAction(ISD::FMAXIMUM, MVT::f32, Legal);
1525 setOperationAction(ISD::FMINIMUM, MVT::f16, Legal);
1526 setOperationAction(ISD::FMAXIMUM, MVT::f16, Legal);
1527 }
1528 setOperationAction(ISD::FMINIMUM, MVT::v2f32, Legal);
1529 setOperationAction(ISD::FMAXIMUM, MVT::v2f32, Legal);
1530 setOperationAction(ISD::FMINIMUM, MVT::v4f32, Legal);
1531 setOperationAction(ISD::FMAXIMUM, MVT::v4f32, Legal);
1532
1533 if (Subtarget->hasFullFP16()) {
1534 setOperationAction(ISD::FMINNUM, MVT::v4f16, Legal);
1535 setOperationAction(ISD::FMAXNUM, MVT::v4f16, Legal);
1536 setOperationAction(ISD::FMINNUM, MVT::v8f16, Legal);
1537 setOperationAction(ISD::FMAXNUM, MVT::v8f16, Legal);
1538
1539 setOperationAction(ISD::FMINIMUM, MVT::v4f16, Legal);
1540 setOperationAction(ISD::FMAXIMUM, MVT::v4f16, Legal);
1541 setOperationAction(ISD::FMINIMUM, MVT::v8f16, Legal);
1542 setOperationAction(ISD::FMAXIMUM, MVT::v8f16, Legal);
1543 }
1544 }
1545
1546 // We have target-specific dag combine patterns for the following nodes:
1547 // ARMISD::VMOVRRD - No need to call setTargetDAGCombine
1548 setTargetDAGCombine(ISD::ADD);
1549 setTargetDAGCombine(ISD::SUB);
1550 setTargetDAGCombine(ISD::MUL);
1551 setTargetDAGCombine(ISD::AND);
1552 setTargetDAGCombine(ISD::OR);
1553 setTargetDAGCombine(ISD::XOR);
1554
1555 if (Subtarget->hasMVEIntegerOps())
1556 setTargetDAGCombine(ISD::VSELECT);
1557
1558 if (Subtarget->hasV6Ops())
1559 setTargetDAGCombine(ISD::SRL);
1560 if (Subtarget->isThumb1Only())
1561 setTargetDAGCombine(ISD::SHL);
1562
1563 setStackPointerRegisterToSaveRestore(ARM::SP);
1564
1565 if (Subtarget->useSoftFloat() || Subtarget->isThumb1Only() ||
1566 !Subtarget->hasVFP2Base() || Subtarget->hasMinSize())
1567 setSchedulingPreference(Sched::RegPressure);
1568 else
1569 setSchedulingPreference(Sched::Hybrid);
1570
1571 //// temporary - rewrite interface to use type
1572 MaxStoresPerMemset = 8;
1573 MaxStoresPerMemsetOptSize = 4;
1574 MaxStoresPerMemcpy = 4; // For @llvm.memcpy -> sequence of stores
1575 MaxStoresPerMemcpyOptSize = 2;
1576 MaxStoresPerMemmove = 4; // For @llvm.memmove -> sequence of stores
1577 MaxStoresPerMemmoveOptSize = 2;
1578
1579 // On ARM arguments smaller than 4 bytes are extended, so all arguments
1580 // are at least 4 bytes aligned.
1581 setMinStackArgumentAlignment(Align(4));
1582
1583 // Prefer likely predicted branches to selects on out-of-order cores.
1584 PredictableSelectIsExpensive = Subtarget->getSchedModel().isOutOfOrder();
1585
1586 setPrefLoopAlignment(Align(1ULL << Subtarget->getPrefLoopLogAlignment()));
1587
1588 setMinFunctionAlignment(Subtarget->isThumb() ? Align(2) : Align(4));
1589
1590 if (Subtarget->isThumb() || Subtarget->isThumb2())
1591 setTargetDAGCombine(ISD::ABS);
1592}
1593
1594bool ARMTargetLowering::useSoftFloat() const {
1595 return Subtarget->useSoftFloat();
1596}
1597
1598// FIXME: It might make sense to define the representative register class as the
1599// nearest super-register that has a non-null superset. For example, DPR_VFP2 is
1600// a super-register of SPR, and DPR is a superset if DPR_VFP2. Consequently,
1601// SPR's representative would be DPR_VFP2. This should work well if register
1602// pressure tracking were modified such that a register use would increment the
1603// pressure of the register class's representative and all of it's super
1604// classes' representatives transitively. We have not implemented this because
1605// of the difficulty prior to coalescing of modeling operand register classes
1606// due to the common occurrence of cross class copies and subregister insertions
1607// and extractions.
1608std::pair<const TargetRegisterClass *, uint8_t>
1609ARMTargetLowering::findRepresentativeClass(const TargetRegisterInfo *TRI,
1610 MVT VT) const {
1611 const TargetRegisterClass *RRC = nullptr;
1612 uint8_t Cost = 1;
1613 switch (VT.SimpleTy) {
1614 default:
1615 return TargetLowering::findRepresentativeClass(TRI, VT);
1616 // Use DPR as representative register class for all floating point
1617 // and vector types. Since there are 32 SPR registers and 32 DPR registers so
1618 // the cost is 1 for both f32 and f64.
1619 case MVT::f32: case MVT::f64: case MVT::v8i8: case MVT::v4i16:
1620 case MVT::v2i32: case MVT::v1i64: case MVT::v2f32:
1621 RRC = &ARM::DPRRegClass;
1622 // When NEON is used for SP, only half of the register file is available
1623 // because operations that define both SP and DP results will be constrained
1624 // to the VFP2 class (D0-D15). We currently model this constraint prior to
1625 // coalescing by double-counting the SP regs. See the FIXME above.
1626 if (Subtarget->useNEONForSinglePrecisionFP())
1627 Cost = 2;
1628 break;
1629 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1630 case MVT::v4f32: case MVT::v2f64:
1631 RRC = &ARM::DPRRegClass;
1632 Cost = 2;
1633 break;
1634 case MVT::v4i64:
1635 RRC = &ARM::DPRRegClass;
1636 Cost = 4;
1637 break;
1638 case MVT::v8i64:
1639 RRC = &ARM::DPRRegClass;
1640 Cost = 8;
1641 break;
1642 }
1643 return std::make_pair(RRC, Cost);
1644}
1645
1646const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const {
1647#define MAKE_CASE(V) \
1648 case V: \
1649 return #V;
1650 switch ((ARMISD::NodeType)Opcode) {
1651 case ARMISD::FIRST_NUMBER:
1652 break;
1653 MAKE_CASE(ARMISD::Wrapper)
1654 MAKE_CASE(ARMISD::WrapperPIC)
1655 MAKE_CASE(ARMISD::WrapperJT)
1656 MAKE_CASE(ARMISD::COPY_STRUCT_BYVAL)
1657 MAKE_CASE(ARMISD::CALL)
1658 MAKE_CASE(ARMISD::CALL_PRED)
1659 MAKE_CASE(ARMISD::CALL_NOLINK)
1660 MAKE_CASE(ARMISD::tSECALL)
1661 MAKE_CASE(ARMISD::t2CALL_BTI)
1662 MAKE_CASE(ARMISD::BRCOND)
1663 MAKE_CASE(ARMISD::BR_JT)
1664 MAKE_CASE(ARMISD::BR2_JT)
1665 MAKE_CASE(ARMISD::RET_FLAG)
1666 MAKE_CASE(ARMISD::SERET_FLAG)
1667 MAKE_CASE(ARMISD::INTRET_FLAG)
1668 MAKE_CASE(ARMISD::PIC_ADD)
1669 MAKE_CASE(ARMISD::CMP)
1670 MAKE_CASE(ARMISD::CMN)
1671 MAKE_CASE(ARMISD::CMPZ)
1672 MAKE_CASE(ARMISD::CMPFP)
1673 MAKE_CASE(ARMISD::CMPFPE)
1674 MAKE_CASE(ARMISD::CMPFPw0)
1675 MAKE_CASE(ARMISD::CMPFPEw0)
1676 MAKE_CASE(ARMISD::BCC_i64)
1677 MAKE_CASE(ARMISD::FMSTAT)
1678 MAKE_CASE(ARMISD::CMOV)
1679 MAKE_CASE(ARMISD::SUBS)
1680 MAKE_CASE(ARMISD::SSAT)
1681 MAKE_CASE(ARMISD::USAT)
1682 MAKE_CASE(ARMISD::ASRL)
1683 MAKE_CASE(ARMISD::LSRL)
1684 MAKE_CASE(ARMISD::LSLL)
1685 MAKE_CASE(ARMISD::SRL_FLAG)
1686 MAKE_CASE(ARMISD::SRA_FLAG)
1687 MAKE_CASE(ARMISD::RRX)
1688 MAKE_CASE(ARMISD::ADDC)
1689 MAKE_CASE(ARMISD::ADDE)
1690 MAKE_CASE(ARMISD::SUBC)
1691 MAKE_CASE(ARMISD::SUBE)
1692 MAKE_CASE(ARMISD::LSLS)
1693 MAKE_CASE(ARMISD::VMOVRRD)
1694 MAKE_CASE(ARMISD::VMOVDRR)
1695 MAKE_CASE(ARMISD::VMOVhr)
1696 MAKE_CASE(ARMISD::VMOVrh)
1697 MAKE_CASE(ARMISD::VMOVSR)
1698 MAKE_CASE(ARMISD::EH_SJLJ_SETJMP)
1699 MAKE_CASE(ARMISD::EH_SJLJ_LONGJMP)
1700 MAKE_CASE(ARMISD::EH_SJLJ_SETUP_DISPATCH)
1701 MAKE_CASE(ARMISD::TC_RETURN)
1702 MAKE_CASE(ARMISD::THREAD_POINTER)
1703 MAKE_CASE(ARMISD::DYN_ALLOC)
1704 MAKE_CASE(ARMISD::MEMBARRIER_MCR)
1705 MAKE_CASE(ARMISD::PRELOAD)
1706 MAKE_CASE(ARMISD::LDRD)
1707 MAKE_CASE(ARMISD::STRD)
1708 MAKE_CASE(ARMISD::WIN__CHKSTK)
1709 MAKE_CASE(ARMISD::WIN__DBZCHK)
1710 MAKE_CASE(ARMISD::PREDICATE_CAST)
1711 MAKE_CASE(ARMISD::VECTOR_REG_CAST)
1712 MAKE_CASE(ARMISD::MVESEXT)
1713 MAKE_CASE(ARMISD::MVEZEXT)
1714 MAKE_CASE(ARMISD::MVETRUNC)
1715 MAKE_CASE(ARMISD::VCMP)
1716 MAKE_CASE(ARMISD::VCMPZ)
1717 MAKE_CASE(ARMISD::VTST)
1718 MAKE_CASE(ARMISD::VSHLs)
1719 MAKE_CASE(ARMISD::VSHLu)
1720 MAKE_CASE(ARMISD::VSHLIMM)
1721 MAKE_CASE(ARMISD::VSHRsIMM)
1722 MAKE_CASE(ARMISD::VSHRuIMM)
1723 MAKE_CASE(ARMISD::VRSHRsIMM)
1724 MAKE_CASE(ARMISD::VRSHRuIMM)
1725 MAKE_CASE(ARMISD::VRSHRNIMM)
1726 MAKE_CASE(ARMISD::VQSHLsIMM)
1727 MAKE_CASE(ARMISD::VQSHLuIMM)
1728 MAKE_CASE(ARMISD::VQSHLsuIMM)
1729 MAKE_CASE(ARMISD::VQSHRNsIMM)
1730 MAKE_CASE(ARMISD::VQSHRNuIMM)
1731 MAKE_CASE(ARMISD::VQSHRNsuIMM)
1732 MAKE_CASE(ARMISD::VQRSHRNsIMM)
1733 MAKE_CASE(ARMISD::VQRSHRNuIMM)
1734 MAKE_CASE(ARMISD::VQRSHRNsuIMM)
1735 MAKE_CASE(ARMISD::VSLIIMM)
1736 MAKE_CASE(ARMISD::VSRIIMM)
1737 MAKE_CASE(ARMISD::VGETLANEu)
1738 MAKE_CASE(ARMISD::VGETLANEs)
1739 MAKE_CASE(ARMISD::VMOVIMM)
1740 MAKE_CASE(ARMISD::VMVNIMM)
1741 MAKE_CASE(ARMISD::VMOVFPIMM)
1742 MAKE_CASE(ARMISD::VDUP)
1743 MAKE_CASE(ARMISD::VDUPLANE)
1744 MAKE_CASE(ARMISD::VEXT)
1745 MAKE_CASE(ARMISD::VREV64)
1746 MAKE_CASE(ARMISD::VREV32)
1747 MAKE_CASE(ARMISD::VREV16)
1748 MAKE_CASE(ARMISD::VZIP)
1749 MAKE_CASE(ARMISD::VUZP)
1750 MAKE_CASE(ARMISD::VTRN)
1751 MAKE_CASE(ARMISD::VTBL1)
1752 MAKE_CASE(ARMISD::VTBL2)
1753 MAKE_CASE(ARMISD::VMOVN)
1754 MAKE_CASE(ARMISD::VQMOVNs)
1755 MAKE_CASE(ARMISD::VQMOVNu)
1756 MAKE_CASE(ARMISD::VCVTN)
1757 MAKE_CASE(ARMISD::VCVTL)
1758 MAKE_CASE(ARMISD::VIDUP)
1759 MAKE_CASE(ARMISD::VMULLs)
1760 MAKE_CASE(ARMISD::VMULLu)
1761 MAKE_CASE(ARMISD::VQDMULH)
1762 MAKE_CASE(ARMISD::VADDVs)
1763 MAKE_CASE(ARMISD::VADDVu)
1764 MAKE_CASE(ARMISD::VADDVps)
1765 MAKE_CASE(ARMISD::VADDVpu)
1766 MAKE_CASE(ARMISD::VADDLVs)
1767 MAKE_CASE(ARMISD::VADDLVu)
1768 MAKE_CASE(ARMISD::VADDLVAs)
1769 MAKE_CASE(ARMISD::VADDLVAu)
1770 MAKE_CASE(ARMISD::VADDLVps)
1771 MAKE_CASE(ARMISD::VADDLVpu)
1772 MAKE_CASE(ARMISD::VADDLVAps)
1773 MAKE_CASE(ARMISD::VADDLVApu)
1774 MAKE_CASE(ARMISD::VMLAVs)
1775 MAKE_CASE(ARMISD::VMLAVu)
1776 MAKE_CASE(ARMISD::VMLAVps)
1777 MAKE_CASE(ARMISD::VMLAVpu)
1778 MAKE_CASE(ARMISD::VMLALVs)
1779 MAKE_CASE(ARMISD::VMLALVu)
1780 MAKE_CASE(ARMISD::VMLALVps)
1781 MAKE_CASE(ARMISD::VMLALVpu)
1782 MAKE_CASE(ARMISD::VMLALVAs)
1783 MAKE_CASE(ARMISD::VMLALVAu)
1784 MAKE_CASE(ARMISD::VMLALVAps)
1785 MAKE_CASE(ARMISD::VMLALVApu)
1786 MAKE_CASE(ARMISD::VMINVu)
1787 MAKE_CASE(ARMISD::VMINVs)
1788 MAKE_CASE(ARMISD::VMAXVu)
1789 MAKE_CASE(ARMISD::VMAXVs)
1790 MAKE_CASE(ARMISD::UMAAL)
1791 MAKE_CASE(ARMISD::UMLAL)
1792 MAKE_CASE(ARMISD::SMLAL)
1793 MAKE_CASE(ARMISD::SMLALBB)
1794 MAKE_CASE(ARMISD::SMLALBT)
1795 MAKE_CASE(ARMISD::SMLALTB)
1796 MAKE_CASE(ARMISD::SMLALTT)
1797 MAKE_CASE(ARMISD::SMULWB)
1798 MAKE_CASE(ARMISD::SMULWT)
1799 MAKE_CASE(ARMISD::SMLALD)
1800 MAKE_CASE(ARMISD::SMLALDX)
1801 MAKE_CASE(ARMISD::SMLSLD)
1802 MAKE_CASE(ARMISD::SMLSLDX)
1803 MAKE_CASE(ARMISD::SMMLAR)
1804 MAKE_CASE(ARMISD::SMMLSR)
1805 MAKE_CASE(ARMISD::QADD16b)
1806 MAKE_CASE(ARMISD::QSUB16b)
1807 MAKE_CASE(ARMISD::QADD8b)
1808 MAKE_CASE(ARMISD::QSUB8b)
1809 MAKE_CASE(ARMISD::UQADD16b)
1810 MAKE_CASE(ARMISD::UQSUB16b)
1811 MAKE_CASE(ARMISD::UQADD8b)
1812 MAKE_CASE(ARMISD::UQSUB8b)
1813 MAKE_CASE(ARMISD::BUILD_VECTOR)
1814 MAKE_CASE(ARMISD::BFI)
1815 MAKE_CASE(ARMISD::VORRIMM)
1816 MAKE_CASE(ARMISD::VBICIMM)
1817 MAKE_CASE(ARMISD::VBSP)
1818 MAKE_CASE(ARMISD::MEMCPY)
1819 MAKE_CASE(ARMISD::VLD1DUP)
1820 MAKE_CASE(ARMISD::VLD2DUP)
1821 MAKE_CASE(ARMISD::VLD3DUP)
1822 MAKE_CASE(ARMISD::VLD4DUP)
1823 MAKE_CASE(ARMISD::VLD1_UPD)
1824 MAKE_CASE(ARMISD::VLD2_UPD)
1825 MAKE_CASE(ARMISD::VLD3_UPD)
1826 MAKE_CASE(ARMISD::VLD4_UPD)
1827 MAKE_CASE(ARMISD::VLD1x2_UPD)
1828 MAKE_CASE(ARMISD::VLD1x3_UPD)
1829 MAKE_CASE(ARMISD::VLD1x4_UPD)
1830 MAKE_CASE(ARMISD::VLD2LN_UPD)
1831 MAKE_CASE(ARMISD::VLD3LN_UPD)
1832 MAKE_CASE(ARMISD::VLD4LN_UPD)
1833 MAKE_CASE(ARMISD::VLD1DUP_UPD)
1834 MAKE_CASE(ARMISD::VLD2DUP_UPD)
1835 MAKE_CASE(ARMISD::VLD3DUP_UPD)
1836 MAKE_CASE(ARMISD::VLD4DUP_UPD)
1837 MAKE_CASE(ARMISD::VST1_UPD)
1838 MAKE_CASE(ARMISD::VST2_UPD)
1839 MAKE_CASE(ARMISD::VST3_UPD)
1840 MAKE_CASE(ARMISD::VST4_UPD)
1841 MAKE_CASE(ARMISD::VST1x2_UPD)
1842 MAKE_CASE(ARMISD::VST1x3_UPD)
1843 MAKE_CASE(ARMISD::VST1x4_UPD)
1844 MAKE_CASE(ARMISD::VST2LN_UPD)
1845 MAKE_CASE(ARMISD::VST3LN_UPD)
1846 MAKE_CASE(ARMISD::VST4LN_UPD)
1847 MAKE_CASE(ARMISD::WLS)
1848 MAKE_CASE(ARMISD::WLSSETUP)
1849 MAKE_CASE(ARMISD::LE)
1850 MAKE_CASE(ARMISD::LOOP_DEC)
1851 MAKE_CASE(ARMISD::CSINV)
1852 MAKE_CASE(ARMISD::CSNEG)
1853 MAKE_CASE(ARMISD::CSINC)
1854 MAKE_CASE(ARMISD::MEMCPYLOOP)
1855 MAKE_CASE(ARMISD::MEMSETLOOP)
1856#undef MAKE_CASE
1857 }
1858 return nullptr;
1859}
1860
1861EVT ARMTargetLowering::getSetCCResultType(const DataLayout &DL, LLVMContext &,
1862 EVT VT) const {
1863 if (!VT.isVector())
1864 return getPointerTy(DL);
1865
1866 // MVE has a predicate register.
1867 if ((Subtarget->hasMVEIntegerOps() &&
1868 (VT == MVT::v2i64 || VT == MVT::v4i32 || VT == MVT::v8i16 ||
1869 VT == MVT::v16i8)) ||
1870 (Subtarget->hasMVEFloatOps() &&
1871 (VT == MVT::v2f64 || VT == MVT::v4f32 || VT == MVT::v8f16)))
1872 return MVT::getVectorVT(MVT::i1, VT.getVectorElementCount());
1873 return VT.changeVectorElementTypeToInteger();
1874}
1875
1876/// getRegClassFor - Return the register class that should be used for the
1877/// specified value type.
1878const TargetRegisterClass *
1879ARMTargetLowering::getRegClassFor(MVT VT, bool isDivergent) const {
1880 (void)isDivergent;
1881 // Map v4i64 to QQ registers but do not make the type legal. Similarly map
1882 // v8i64 to QQQQ registers. v4i64 and v8i64 are only used for REG_SEQUENCE to
1883 // load / store 4 to 8 consecutive NEON D registers, or 2 to 4 consecutive
1884 // MVE Q registers.
1885 if (Subtarget->hasNEON()) {
1886 if (VT == MVT::v4i64)
1887 return &ARM::QQPRRegClass;
1888 if (VT == MVT::v8i64)
1889 return &ARM::QQQQPRRegClass;
1890 }
1891 if (Subtarget->hasMVEIntegerOps()) {
1892 if (VT == MVT::v4i64)
1893 return &ARM::MQQPRRegClass;
1894 if (VT == MVT::v8i64)
1895 return &ARM::MQQQQPRRegClass;
1896 }
1897 return TargetLowering::getRegClassFor(VT);
1898}
1899
1900// memcpy, and other memory intrinsics, typically tries to use LDM/STM if the
1901// source/dest is aligned and the copy size is large enough. We therefore want
1902// to align such objects passed to memory intrinsics.
1903bool ARMTargetLowering::shouldAlignPointerArgs(CallInst *CI, unsigned &MinSize,
1904 unsigned &PrefAlign) const {
1905 if (!isa<MemIntrinsic>(CI))
1906 return false;
1907 MinSize = 8;
1908 // On ARM11 onwards (excluding M class) 8-byte aligned LDM is typically 1
1909 // cycle faster than 4-byte aligned LDM.
1910 PrefAlign = (Subtarget->hasV6Ops() && !Subtarget->isMClass() ? 8 : 4);
1911 return true;
1912}
1913
1914// Create a fast isel object.
1915FastISel *
1916ARMTargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
1917 const TargetLibraryInfo *libInfo) const {
1918 return ARM::createFastISel(funcInfo, libInfo);
1919}
1920
1921Sched::Preference ARMTargetLowering::getSchedulingPreference(SDNode *N) const {
1922 unsigned NumVals = N->getNumValues();
1923 if (!NumVals)
1924 return Sched::RegPressure;
1925
1926 for (unsigned i = 0; i != NumVals; ++i) {
1927 EVT VT = N->getValueType(i);
1928 if (VT == MVT::Glue || VT == MVT::Other)
1929 continue;
1930 if (VT.isFloatingPoint() || VT.isVector())
1931 return Sched::ILP;
1932 }
1933
1934 if (!N->isMachineOpcode())
1935 return Sched::RegPressure;
1936
1937 // Load are scheduled for latency even if there instruction itinerary
1938 // is not available.
1939 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
1940 const MCInstrDesc &MCID = TII->get(N->getMachineOpcode());
1941
1942 if (MCID.getNumDefs() == 0)
1943 return Sched::RegPressure;
1944 if (!Itins->isEmpty() &&
1945 Itins->getOperandCycle(MCID.getSchedClass(), 0) > 2)
1946 return Sched::ILP;
1947
1948 return Sched::RegPressure;
1949}
1950
1951//===----------------------------------------------------------------------===//
1952// Lowering Code
1953//===----------------------------------------------------------------------===//
1954
1955static bool isSRL16(const SDValue &Op) {
1956 if (Op.getOpcode() != ISD::SRL)
1957 return false;
1958 if (auto Const = dyn_cast<ConstantSDNode>(Op.getOperand(1)))
1959 return Const->getZExtValue() == 16;
1960 return false;
1961}
1962
1963static bool isSRA16(const SDValue &Op) {
1964 if (Op.getOpcode() != ISD::SRA)
1965 return false;
1966 if (auto Const = dyn_cast<ConstantSDNode>(Op.getOperand(1)))
1967 return Const->getZExtValue() == 16;
1968 return false;
1969}
1970
1971static bool isSHL16(const SDValue &Op) {
1972 if (Op.getOpcode() != ISD::SHL)
1973 return false;
1974 if (auto Const = dyn_cast<ConstantSDNode>(Op.getOperand(1)))
1975 return Const->getZExtValue() == 16;
1976 return false;
1977}
1978
1979// Check for a signed 16-bit value. We special case SRA because it makes it
1980// more simple when also looking for SRAs that aren't sign extending a
1981// smaller value. Without the check, we'd need to take extra care with
1982// checking order for some operations.
1983static bool isS16(const SDValue &Op, SelectionDAG &DAG) {
1984 if (isSRA16(Op))
1985 return isSHL16(Op.getOperand(0));
1986 return DAG.ComputeNumSignBits(Op) == 17;
1987}
1988
1989/// IntCCToARMCC - Convert a DAG integer condition code to an ARM CC
1990static ARMCC::CondCodes IntCCToARMCC(ISD::CondCode CC) {
1991 switch (CC) {
1992 default: llvm_unreachable("Unknown condition code!")::llvm::llvm_unreachable_internal("Unknown condition code!", "llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 1992)
;
1993 case ISD::SETNE: return ARMCC::NE;
1994 case ISD::SETEQ: return ARMCC::EQ;
1995 case ISD::SETGT: return ARMCC::GT;
1996 case ISD::SETGE: return ARMCC::GE;
1997 case ISD::SETLT: return ARMCC::LT;
1998 case ISD::SETLE: return ARMCC::LE;
1999 case ISD::SETUGT: return ARMCC::HI;
2000 case ISD::SETUGE: return ARMCC::HS;
2001 case ISD::SETULT: return ARMCC::LO;
2002 case ISD::SETULE: return ARMCC::LS;
2003 }
2004}
2005
2006/// FPCCToARMCC - Convert a DAG fp condition code to an ARM CC.
2007static void FPCCToARMCC(ISD::CondCode CC, ARMCC::CondCodes &CondCode,
2008 ARMCC::CondCodes &CondCode2) {
2009 CondCode2 = ARMCC::AL;
2010 switch (CC) {
2011 default: llvm_unreachable("Unknown FP condition!")::llvm::llvm_unreachable_internal("Unknown FP condition!", "llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2011)
;
2012 case ISD::SETEQ:
2013 case ISD::SETOEQ: CondCode = ARMCC::EQ; break;
2014 case ISD::SETGT:
2015 case ISD::SETOGT: CondCode = ARMCC::GT; break;
2016 case ISD::SETGE:
2017 case ISD::SETOGE: CondCode = ARMCC::GE; break;
2018 case ISD::SETOLT: CondCode = ARMCC::MI; break;
2019 case ISD::SETOLE: CondCode = ARMCC::LS; break;
2020 case ISD::SETONE: CondCode = ARMCC::MI; CondCode2 = ARMCC::GT; break;
2021 case ISD::SETO: CondCode = ARMCC::VC; break;
2022 case ISD::SETUO: CondCode = ARMCC::VS; break;
2023 case ISD::SETUEQ: CondCode = ARMCC::EQ; CondCode2 = ARMCC::VS; break;
2024 case ISD::SETUGT: CondCode = ARMCC::HI; break;
2025 case ISD::SETUGE: CondCode = ARMCC::PL; break;
2026 case ISD::SETLT:
2027 case ISD::SETULT: CondCode = ARMCC::LT; break;
2028 case ISD::SETLE:
2029 case ISD::SETULE: CondCode = ARMCC::LE; break;
2030 case ISD::SETNE:
2031 case ISD::SETUNE: CondCode = ARMCC::NE; break;
2032 }
2033}
2034
2035//===----------------------------------------------------------------------===//
2036// Calling Convention Implementation
2037//===----------------------------------------------------------------------===//
2038
2039/// getEffectiveCallingConv - Get the effective calling convention, taking into
2040/// account presence of floating point hardware and calling convention
2041/// limitations, such as support for variadic functions.
2042CallingConv::ID
2043ARMTargetLowering::getEffectiveCallingConv(CallingConv::ID CC,
2044 bool isVarArg) const {
2045 switch (CC) {
2046 default:
2047 report_fatal_error("Unsupported calling convention");
2048 case CallingConv::ARM_AAPCS:
2049 case CallingConv::ARM_APCS:
2050 case CallingConv::GHC:
2051 case CallingConv::CFGuard_Check:
2052 return CC;
2053 case CallingConv::PreserveMost:
2054 return CallingConv::PreserveMost;
2055 case CallingConv::ARM_AAPCS_VFP:
2056 case CallingConv::Swift:
2057 case CallingConv::SwiftTail:
2058 return isVarArg ? CallingConv::ARM_AAPCS : CallingConv::ARM_AAPCS_VFP;
2059 case CallingConv::C:
2060 case CallingConv::Tail:
2061 if (!Subtarget->isAAPCS_ABI())
2062 return CallingConv::ARM_APCS;
2063 else if (Subtarget->hasVFP2Base() && !Subtarget->isThumb1Only() &&
2064 getTargetMachine().Options.FloatABIType == FloatABI::Hard &&
2065 !isVarArg)
2066 return CallingConv::ARM_AAPCS_VFP;
2067 else
2068 return CallingConv::ARM_AAPCS;
2069 case CallingConv::Fast:
2070 case CallingConv::CXX_FAST_TLS:
2071 if (!Subtarget->isAAPCS_ABI()) {
2072 if (Subtarget->hasVFP2Base() && !Subtarget->isThumb1Only() && !isVarArg)
2073 return CallingConv::Fast;
2074 return CallingConv::ARM_APCS;
2075 } else if (Subtarget->hasVFP2Base() &&
2076 !Subtarget->isThumb1Only() && !isVarArg)
2077 return CallingConv::ARM_AAPCS_VFP;
2078 else
2079 return CallingConv::ARM_AAPCS;
2080 }
2081}
2082
2083CCAssignFn *ARMTargetLowering::CCAssignFnForCall(CallingConv::ID CC,
2084 bool isVarArg) const {
2085 return CCAssignFnForNode(CC, false, isVarArg);
2086}
2087
2088CCAssignFn *ARMTargetLowering::CCAssignFnForReturn(CallingConv::ID CC,
2089 bool isVarArg) const {
2090 return CCAssignFnForNode(CC, true, isVarArg);
2091}
2092
2093/// CCAssignFnForNode - Selects the correct CCAssignFn for the given
2094/// CallingConvention.
2095CCAssignFn *ARMTargetLowering::CCAssignFnForNode(CallingConv::ID CC,
2096 bool Return,
2097 bool isVarArg) const {
2098 switch (getEffectiveCallingConv(CC, isVarArg)) {
2099 default:
2100 report_fatal_error("Unsupported calling convention");
2101 case CallingConv::ARM_APCS:
2102 return (Return ? RetCC_ARM_APCS : CC_ARM_APCS);
2103 case CallingConv::ARM_AAPCS:
2104 return (Return ? RetCC_ARM_AAPCS : CC_ARM_AAPCS);
2105 case CallingConv::ARM_AAPCS_VFP:
2106 return (Return ? RetCC_ARM_AAPCS_VFP : CC_ARM_AAPCS_VFP);
2107 case CallingConv::Fast:
2108 return (Return ? RetFastCC_ARM_APCS : FastCC_ARM_APCS);
2109 case CallingConv::GHC:
2110 return (Return ? RetCC_ARM_APCS : CC_ARM_APCS_GHC);
2111 case CallingConv::PreserveMost:
2112 return (Return ? RetCC_ARM_AAPCS : CC_ARM_AAPCS);
2113 case CallingConv::CFGuard_Check:
2114 return (Return ? RetCC_ARM_AAPCS : CC_ARM_Win32_CFGuard_Check);
2115 }
2116}
2117
2118SDValue ARMTargetLowering::MoveToHPR(const SDLoc &dl, SelectionDAG &DAG,
2119 MVT LocVT, MVT ValVT, SDValue Val) const {
2120 Val = DAG.getNode(ISD::BITCAST, dl, MVT::getIntegerVT(LocVT.getSizeInBits()),
2121 Val);
2122 if (Subtarget->hasFullFP16()) {
2123 Val = DAG.getNode(ARMISD::VMOVhr, dl, ValVT, Val);
2124 } else {
2125 Val = DAG.getNode(ISD::TRUNCATE, dl,
2126 MVT::getIntegerVT(ValVT.getSizeInBits()), Val);
2127 Val = DAG.getNode(ISD::BITCAST, dl, ValVT, Val);
2128 }
2129 return Val;
2130}
2131
2132SDValue ARMTargetLowering::MoveFromHPR(const SDLoc &dl, SelectionDAG &DAG,
2133 MVT LocVT, MVT ValVT,
2134 SDValue Val) const {
2135 if (Subtarget->hasFullFP16()) {
2136 Val = DAG.getNode(ARMISD::VMOVrh, dl,
2137 MVT::getIntegerVT(LocVT.getSizeInBits()), Val);
2138 } else {
2139 Val = DAG.getNode(ISD::BITCAST, dl,
2140 MVT::getIntegerVT(ValVT.getSizeInBits()), Val);
2141 Val = DAG.getNode(ISD::ZERO_EXTEND, dl,
2142 MVT::getIntegerVT(LocVT.getSizeInBits()), Val);
2143 }
2144 return DAG.getNode(ISD::BITCAST, dl, LocVT, Val);
2145}
2146
2147/// LowerCallResult - Lower the result values of a call into the
2148/// appropriate copies out of appropriate physical registers.
2149SDValue ARMTargetLowering::LowerCallResult(
2150 SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg,
2151 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
2152 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals, bool isThisReturn,
2153 SDValue ThisVal) const {
2154 // Assign locations to each value returned by this call.
2155 SmallVector<CCValAssign, 16> RVLocs;
2156 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2157 *DAG.getContext());
2158 CCInfo.AnalyzeCallResult(Ins, CCAssignFnForReturn(CallConv, isVarArg));
2159
2160 // Copy all of the result registers out of their specified physreg.
2161 for (unsigned i = 0; i != RVLocs.size(); ++i) {
2162 CCValAssign VA = RVLocs[i];
2163
2164 // Pass 'this' value directly from the argument to return value, to avoid
2165 // reg unit interference
2166 if (i == 0 && isThisReturn) {
2167 assert(!VA.needsCustom() && VA.getLocVT() == MVT::i32 &&(static_cast <bool> (!VA.needsCustom() && VA.getLocVT
() == MVT::i32 && "unexpected return calling convention register assignment"
) ? void (0) : __assert_fail ("!VA.needsCustom() && VA.getLocVT() == MVT::i32 && \"unexpected return calling convention register assignment\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 2168, __extension__
__PRETTY_FUNCTION__))
2168 "unexpected return calling convention register assignment")(static_cast <bool> (!VA.needsCustom() && VA.getLocVT
() == MVT::i32 && "unexpected return calling convention register assignment"
) ? void (0) : __assert_fail ("!VA.needsCustom() && VA.getLocVT() == MVT::i32 && \"unexpected return calling convention register assignment\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 2168, __extension__
__PRETTY_FUNCTION__))
;
2169 InVals.push_back(ThisVal);
2170 continue;
2171 }
2172
2173 SDValue Val;
2174 if (VA.needsCustom() &&
2175 (VA.getLocVT() == MVT::f64 || VA.getLocVT() == MVT::v2f64)) {
2176 // Handle f64 or half of a v2f64.
2177 SDValue Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
2178 InFlag);
2179 Chain = Lo.getValue(1);
2180 InFlag = Lo.getValue(2);
2181 VA = RVLocs[++i]; // skip ahead to next loc
2182 SDValue Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
2183 InFlag);
2184 Chain = Hi.getValue(1);
2185 InFlag = Hi.getValue(2);
2186 if (!Subtarget->isLittle())
2187 std::swap (Lo, Hi);
2188 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
2189
2190 if (VA.getLocVT() == MVT::v2f64) {
2191 SDValue Vec = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
2192 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
2193 DAG.getConstant(0, dl, MVT::i32));
2194
2195 VA = RVLocs[++i]; // skip ahead to next loc
2196 Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
2197 Chain = Lo.getValue(1);
2198 InFlag = Lo.getValue(2);
2199 VA = RVLocs[++i]; // skip ahead to next loc
2200 Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
2201 Chain = Hi.getValue(1);
2202 InFlag = Hi.getValue(2);
2203 if (!Subtarget->isLittle())
2204 std::swap (Lo, Hi);
2205 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
2206 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
2207 DAG.getConstant(1, dl, MVT::i32));
2208 }
2209 } else {
2210 Val = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getLocVT(),
2211 InFlag);
2212 Chain = Val.getValue(1);
2213 InFlag = Val.getValue(2);
2214 }
2215
2216 switch (VA.getLocInfo()) {
2217 default: llvm_unreachable("Unknown loc info!")::llvm::llvm_unreachable_internal("Unknown loc info!", "llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2217)
;
2218 case CCValAssign::Full: break;
2219 case CCValAssign::BCvt:
2220 Val = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), Val);
2221 break;
2222 }
2223
2224 // f16 arguments have their size extended to 4 bytes and passed as if they
2225 // had been copied to the LSBs of a 32-bit register.
2226 // For that, it's passed extended to i32 (soft ABI) or to f32 (hard ABI)
2227 if (VA.needsCustom() &&
2228 (VA.getValVT() == MVT::f16 || VA.getValVT() == MVT::bf16))
2229 Val = MoveToHPR(dl, DAG, VA.getLocVT(), VA.getValVT(), Val);
2230
2231 InVals.push_back(Val);
2232 }
2233
2234 return Chain;
2235}
2236
2237std::pair<SDValue, MachinePointerInfo> ARMTargetLowering::computeAddrForCallArg(
2238 const SDLoc &dl, SelectionDAG &DAG, const CCValAssign &VA, SDValue StackPtr,
2239 bool IsTailCall, int SPDiff) const {
2240 SDValue DstAddr;
2241 MachinePointerInfo DstInfo;
2242 int32_t Offset = VA.getLocMemOffset();
2243 MachineFunction &MF = DAG.getMachineFunction();
2244
2245 if (IsTailCall) {
2246 Offset += SPDiff;
2247 auto PtrVT = getPointerTy(DAG.getDataLayout());
2248 int Size = VA.getLocVT().getFixedSizeInBits() / 8;
2249 int FI = MF.getFrameInfo().CreateFixedObject(Size, Offset, true);
2250 DstAddr = DAG.getFrameIndex(FI, PtrVT);
2251 DstInfo =
2252 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI);
2253 } else {
2254 SDValue PtrOff = DAG.getIntPtrConstant(Offset, dl);
2255 DstAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(DAG.getDataLayout()),
2256 StackPtr, PtrOff);
2257 DstInfo =
2258 MachinePointerInfo::getStack(DAG.getMachineFunction(), Offset);
2259 }
2260
2261 return std::make_pair(DstAddr, DstInfo);
2262}
2263
2264void ARMTargetLowering::PassF64ArgInRegs(const SDLoc &dl, SelectionDAG &DAG,
2265 SDValue Chain, SDValue &Arg,
2266 RegsToPassVector &RegsToPass,
2267 CCValAssign &VA, CCValAssign &NextVA,
2268 SDValue &StackPtr,
2269 SmallVectorImpl<SDValue> &MemOpChains,
2270 bool IsTailCall,
2271 int SPDiff) const {
2272 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl,
2273 DAG.getVTList(MVT::i32, MVT::i32), Arg);
2274 unsigned id = Subtarget->isLittle() ? 0 : 1;
2275 RegsToPass.push_back(std::make_pair(VA.getLocReg(), fmrrd.getValue(id)));
2276
2277 if (NextVA.isRegLoc())
2278 RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), fmrrd.getValue(1-id)));
2279 else {
2280 assert(NextVA.isMemLoc())(static_cast <bool> (NextVA.isMemLoc()) ? void (0) : __assert_fail
("NextVA.isMemLoc()", "llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2280, __extension__ __PRETTY_FUNCTION__))
;
2281 if (!StackPtr.getNode())
2282 StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP,
2283 getPointerTy(DAG.getDataLayout()));
2284
2285 SDValue DstAddr;
2286 MachinePointerInfo DstInfo;
2287 std::tie(DstAddr, DstInfo) =
2288 computeAddrForCallArg(dl, DAG, NextVA, StackPtr, IsTailCall, SPDiff);
2289 MemOpChains.push_back(
2290 DAG.getStore(Chain, dl, fmrrd.getValue(1 - id), DstAddr, DstInfo));
2291 }
2292}
2293
2294static bool canGuaranteeTCO(CallingConv::ID CC, bool GuaranteeTailCalls) {
2295 return (CC == CallingConv::Fast && GuaranteeTailCalls) ||
2296 CC == CallingConv::Tail || CC == CallingConv::SwiftTail;
2297}
2298
2299/// LowerCall - Lowering a call into a callseq_start <-
2300/// ARMISD:CALL <- callseq_end chain. Also add input and output parameter
2301/// nodes.
2302SDValue
2303ARMTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2304 SmallVectorImpl<SDValue> &InVals) const {
2305 SelectionDAG &DAG = CLI.DAG;
2306 SDLoc &dl = CLI.DL;
2307 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
2308 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
2309 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
2310 SDValue Chain = CLI.Chain;
2311 SDValue Callee = CLI.Callee;
2312 bool &isTailCall = CLI.IsTailCall;
2313 CallingConv::ID CallConv = CLI.CallConv;
2314 bool doesNotRet = CLI.DoesNotReturn;
2315 bool isVarArg = CLI.IsVarArg;
2316
2317 MachineFunction &MF = DAG.getMachineFunction();
2318 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2319 MachineFunction::CallSiteInfo CSInfo;
2320 bool isStructRet = (Outs.empty()) ? false : Outs[0].Flags.isSRet();
2321 bool isThisReturn = false;
2322 bool isCmseNSCall = false;
2323 bool isSibCall = false;
2324 bool PreferIndirect = false;
2325 bool GuardWithBTI = false;
2326
2327 // Lower 'returns_twice' calls to a pseudo-instruction.
2328 if (CLI.CB && CLI.CB->getAttributes().hasFnAttr(Attribute::ReturnsTwice) &&
2329 !Subtarget->getNoBTIAtReturnTwice())
2330 GuardWithBTI = AFI->branchTargetEnforcement();
2331
2332 // Determine whether this is a non-secure function call.
2333 if (CLI.CB && CLI.CB->getAttributes().hasFnAttr("cmse_nonsecure_call"))
2334 isCmseNSCall = true;
2335
2336 // Disable tail calls if they're not supported.
2337 if (!Subtarget->supportsTailCall())
2338 isTailCall = false;
2339
2340 // For both the non-secure calls and the returns from a CMSE entry function,
2341 // the function needs to do some extra work afte r the call, or before the
2342 // return, respectively, thus it cannot end with atail call
2343 if (isCmseNSCall || AFI->isCmseNSEntryFunction())
2344 isTailCall = false;
2345
2346 if (isa<GlobalAddressSDNode>(Callee)) {
2347 // If we're optimizing for minimum size and the function is called three or
2348 // more times in this block, we can improve codesize by calling indirectly
2349 // as BLXr has a 16-bit encoding.
2350 auto *GV = cast<GlobalAddressSDNode>(Callee)->getGlobal();
2351 if (CLI.CB) {
2352 auto *BB = CLI.CB->getParent();
2353 PreferIndirect = Subtarget->isThumb() && Subtarget->hasMinSize() &&
2354 count_if(GV->users(), [&BB](const User *U) {
2355 return isa<Instruction>(U) &&
2356 cast<Instruction>(U)->getParent() == BB;
2357 }) > 2;
2358 }
2359 }
2360 if (isTailCall) {
2361 // Check if it's really possible to do a tail call.
2362 isTailCall = IsEligibleForTailCallOptimization(
2363 Callee, CallConv, isVarArg, isStructRet,
2364 MF.getFunction().hasStructRetAttr(), Outs, OutVals, Ins, DAG,
2365 PreferIndirect);
2366
2367 if (isTailCall && !getTargetMachine().Options.GuaranteedTailCallOpt &&
2368 CallConv != CallingConv::Tail && CallConv != CallingConv::SwiftTail)
2369 isSibCall = true;
2370
2371 // We don't support GuaranteedTailCallOpt for ARM, only automatically
2372 // detected sibcalls.
2373 if (isTailCall)
2374 ++NumTailCalls;
2375 }
2376
2377 if (!isTailCall && CLI.CB && CLI.CB->isMustTailCall())
2378 report_fatal_error("failed to perform tail call elimination on a call "
2379 "site marked musttail");
2380 // Analyze operands of the call, assigning locations to each operand.
2381 SmallVector<CCValAssign, 16> ArgLocs;
2382 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
2383 *DAG.getContext());
2384 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForCall(CallConv, isVarArg));
2385
2386 // Get a count of how many bytes are to be pushed on the stack.
2387 unsigned NumBytes = CCInfo.getNextStackOffset();
2388
2389 // SPDiff is the byte offset of the call's argument area from the callee's.
2390 // Stores to callee stack arguments will be placed in FixedStackSlots offset
2391 // by this amount for a tail call. In a sibling call it must be 0 because the
2392 // caller will deallocate the entire stack and the callee still expects its
2393 // arguments to begin at SP+0. Completely unused for non-tail calls.
2394 int SPDiff = 0;
2395
2396 if (isTailCall && !isSibCall) {
2397 auto FuncInfo = MF.getInfo<ARMFunctionInfo>();
2398 unsigned NumReusableBytes = FuncInfo->getArgumentStackSize();
2399
2400 // Since callee will pop argument stack as a tail call, we must keep the
2401 // popped size 16-byte aligned.
2402 Align StackAlign = DAG.getDataLayout().getStackAlignment();
2403 NumBytes = alignTo(NumBytes, StackAlign);
2404
2405 // SPDiff will be negative if this tail call requires more space than we
2406 // would automatically have in our incoming argument space. Positive if we
2407 // can actually shrink the stack.
2408 SPDiff = NumReusableBytes - NumBytes;
2409
2410 // If this call requires more stack than we have available from
2411 // LowerFormalArguments, tell FrameLowering to reserve space for it.
2412 if (SPDiff < 0 && AFI->getArgRegsSaveSize() < (unsigned)-SPDiff)
2413 AFI->setArgRegsSaveSize(-SPDiff);
2414 }
2415
2416 if (isSibCall) {
2417 // For sibling tail calls, memory operands are available in our caller's stack.
2418 NumBytes = 0;
2419 } else {
2420 // Adjust the stack pointer for the new arguments...
2421 // These operations are automatically eliminated by the prolog/epilog pass
2422 Chain = DAG.getCALLSEQ_START(Chain, isTailCall ? 0 : NumBytes, 0, dl);
2423 }
2424
2425 SDValue StackPtr =
2426 DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy(DAG.getDataLayout()));
2427
2428 RegsToPassVector RegsToPass;
2429 SmallVector<SDValue, 8> MemOpChains;
2430
2431 // During a tail call, stores to the argument area must happen after all of
2432 // the function's incoming arguments have been loaded because they may alias.
2433 // This is done by folding in a TokenFactor from LowerFormalArguments, but
2434 // there's no point in doing so repeatedly so this tracks whether that's
2435 // happened yet.
2436 bool AfterFormalArgLoads = false;
2437
2438 // Walk the register/memloc assignments, inserting copies/loads. In the case
2439 // of tail call optimization, arguments are handled later.
2440 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size();
2441 i != e;
2442 ++i, ++realArgIdx) {
2443 CCValAssign &VA = ArgLocs[i];
2444 SDValue Arg = OutVals[realArgIdx];
2445 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
2446 bool isByVal = Flags.isByVal();
2447
2448 // Promote the value if needed.
2449 switch (VA.getLocInfo()) {
2450 default: llvm_unreachable("Unknown loc info!")::llvm::llvm_unreachable_internal("Unknown loc info!", "llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2450)
;
2451 case CCValAssign::Full: break;
2452 case CCValAssign::SExt:
2453 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
2454 break;
2455 case CCValAssign::ZExt:
2456 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
2457 break;
2458 case CCValAssign::AExt:
2459 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
2460 break;
2461 case CCValAssign::BCvt:
2462 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
2463 break;
2464 }
2465
2466 if (isTailCall && VA.isMemLoc() && !AfterFormalArgLoads) {
2467 Chain = DAG.getStackArgumentTokenFactor(Chain);
2468 AfterFormalArgLoads = true;
2469 }
2470
2471 // f16 arguments have their size extended to 4 bytes and passed as if they
2472 // had been copied to the LSBs of a 32-bit register.
2473 // For that, it's passed extended to i32 (soft ABI) or to f32 (hard ABI)
2474 if (VA.needsCustom() &&
2475 (VA.getValVT() == MVT::f16 || VA.getValVT() == MVT::bf16)) {
2476 Arg = MoveFromHPR(dl, DAG, VA.getLocVT(), VA.getValVT(), Arg);
2477 } else {
2478 // f16 arguments could have been extended prior to argument lowering.
2479 // Mask them arguments if this is a CMSE nonsecure call.
2480 auto ArgVT = Outs[realArgIdx].ArgVT;
2481 if (isCmseNSCall && (ArgVT == MVT::f16)) {
2482 auto LocBits = VA.getLocVT().getSizeInBits();
2483 auto MaskValue = APInt::getLowBitsSet(LocBits, ArgVT.getSizeInBits());
2484 SDValue Mask =
2485 DAG.getConstant(MaskValue, dl, MVT::getIntegerVT(LocBits));
2486 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::getIntegerVT(LocBits), Arg);
2487 Arg = DAG.getNode(ISD::AND, dl, MVT::getIntegerVT(LocBits), Arg, Mask);
2488 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
2489 }
2490 }
2491
2492 // f64 and v2f64 might be passed in i32 pairs and must be split into pieces
2493 if (VA.needsCustom() && VA.getLocVT() == MVT::v2f64) {
2494 SDValue Op0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
2495 DAG.getConstant(0, dl, MVT::i32));
2496 SDValue Op1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
2497 DAG.getConstant(1, dl, MVT::i32));
2498
2499 PassF64ArgInRegs(dl, DAG, Chain, Op0, RegsToPass, VA, ArgLocs[++i],
2500 StackPtr, MemOpChains, isTailCall, SPDiff);
2501
2502 VA = ArgLocs[++i]; // skip ahead to next loc
2503 if (VA.isRegLoc()) {
2504 PassF64ArgInRegs(dl, DAG, Chain, Op1, RegsToPass, VA, ArgLocs[++i],
2505 StackPtr, MemOpChains, isTailCall, SPDiff);
2506 } else {
2507 assert(VA.isMemLoc())(static_cast <bool> (VA.isMemLoc()) ? void (0) : __assert_fail
("VA.isMemLoc()", "llvm/lib/Target/ARM/ARMISelLowering.cpp",
2507, __extension__ __PRETTY_FUNCTION__))
;
2508 SDValue DstAddr;
2509 MachinePointerInfo DstInfo;
2510 std::tie(DstAddr, DstInfo) =
2511 computeAddrForCallArg(dl, DAG, VA, StackPtr, isTailCall, SPDiff);
2512 MemOpChains.push_back(DAG.getStore(Chain, dl, Op1, DstAddr, DstInfo));
2513 }
2514 } else if (VA.needsCustom() && VA.getLocVT() == MVT::f64) {
2515 PassF64ArgInRegs(dl, DAG, Chain, Arg, RegsToPass, VA, ArgLocs[++i],
2516 StackPtr, MemOpChains, isTailCall, SPDiff);
2517 } else if (VA.isRegLoc()) {
2518 if (realArgIdx == 0 && Flags.isReturned() && !Flags.isSwiftSelf() &&
2519 Outs[0].VT == MVT::i32) {
2520 assert(VA.getLocVT() == MVT::i32 &&(static_cast <bool> (VA.getLocVT() == MVT::i32 &&
"unexpected calling convention register assignment") ? void (
0) : __assert_fail ("VA.getLocVT() == MVT::i32 && \"unexpected calling convention register assignment\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 2521, __extension__
__PRETTY_FUNCTION__))
2521 "unexpected calling convention register assignment")(static_cast <bool> (VA.getLocVT() == MVT::i32 &&
"unexpected calling convention register assignment") ? void (
0) : __assert_fail ("VA.getLocVT() == MVT::i32 && \"unexpected calling convention register assignment\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 2521, __extension__
__PRETTY_FUNCTION__))
;
2522 assert(!Ins.empty() && Ins[0].VT == MVT::i32 &&(static_cast <bool> (!Ins.empty() && Ins[0].VT ==
MVT::i32 && "unexpected use of 'returned'") ? void (
0) : __assert_fail ("!Ins.empty() && Ins[0].VT == MVT::i32 && \"unexpected use of 'returned'\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 2523, __extension__
__PRETTY_FUNCTION__))
2523 "unexpected use of 'returned'")(static_cast <bool> (!Ins.empty() && Ins[0].VT ==
MVT::i32 && "unexpected use of 'returned'") ? void (
0) : __assert_fail ("!Ins.empty() && Ins[0].VT == MVT::i32 && \"unexpected use of 'returned'\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 2523, __extension__
__PRETTY_FUNCTION__))
;
2524 isThisReturn = true;
2525 }
2526 const TargetOptions &Options = DAG.getTarget().Options;
2527 if (Options.EmitCallSiteInfo)
2528 CSInfo.emplace_back(VA.getLocReg(), i);
2529 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2530 } else if (isByVal) {
2531 assert(VA.isMemLoc())(static_cast <bool> (VA.isMemLoc()) ? void (0) : __assert_fail
("VA.isMemLoc()", "llvm/lib/Target/ARM/ARMISelLowering.cpp",
2531, __extension__ __PRETTY_FUNCTION__))
;
2532 unsigned offset = 0;
2533
2534 // True if this byval aggregate will be split between registers
2535 // and memory.
2536 unsigned ByValArgsCount = CCInfo.getInRegsParamsCount();
2537 unsigned CurByValIdx = CCInfo.getInRegsParamsProcessed();
2538
2539 if (CurByValIdx < ByValArgsCount) {
2540
2541 unsigned RegBegin, RegEnd;
2542 CCInfo.getInRegsParamInfo(CurByValIdx, RegBegin, RegEnd);
2543
2544 EVT PtrVT =
2545 DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
2546 unsigned int i, j;
2547 for (i = 0, j = RegBegin; j < RegEnd; i++, j++) {
2548 SDValue Const = DAG.getConstant(4*i, dl, MVT::i32);
2549 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
2550 SDValue Load =
2551 DAG.getLoad(PtrVT, dl, Chain, AddArg, MachinePointerInfo(),
2552 DAG.InferPtrAlign(AddArg));
2553 MemOpChains.push_back(Load.getValue(1));
2554 RegsToPass.push_back(std::make_pair(j, Load));
2555 }
2556
2557 // If parameter size outsides register area, "offset" value
2558 // helps us to calculate stack slot for remained part properly.
2559 offset = RegEnd - RegBegin;
2560
2561 CCInfo.nextInRegsParam();
2562 }
2563
2564 if (Flags.getByValSize() > 4*offset) {
2565 auto PtrVT = getPointerTy(DAG.getDataLayout());
2566 SDValue Dst;
2567 MachinePointerInfo DstInfo;
2568 std::tie(Dst, DstInfo) =
2569 computeAddrForCallArg(dl, DAG, VA, StackPtr, isTailCall, SPDiff);
2570 SDValue SrcOffset = DAG.getIntPtrConstant(4*offset, dl);
2571 SDValue Src = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, SrcOffset);
2572 SDValue SizeNode = DAG.getConstant(Flags.getByValSize() - 4*offset, dl,
2573 MVT::i32);
2574 SDValue AlignNode =
2575 DAG.getConstant(Flags.getNonZeroByValAlign().value(), dl, MVT::i32);
2576
2577 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
2578 SDValue Ops[] = { Chain, Dst, Src, SizeNode, AlignNode};
2579 MemOpChains.push_back(DAG.getNode(ARMISD::COPY_STRUCT_BYVAL, dl, VTs,
2580 Ops));
2581 }
2582 } else {
2583 assert(VA.isMemLoc())(static_cast <bool> (VA.isMemLoc()) ? void (0) : __assert_fail
("VA.isMemLoc()", "llvm/lib/Target/ARM/ARMISelLowering.cpp",
2583, __extension__ __PRETTY_FUNCTION__))
;
2584 SDValue DstAddr;
2585 MachinePointerInfo DstInfo;
2586 std::tie(DstAddr, DstInfo) =
2587 computeAddrForCallArg(dl, DAG, VA, StackPtr, isTailCall, SPDiff);
2588
2589 SDValue Store = DAG.getStore(Chain, dl, Arg, DstAddr, DstInfo);
2590 MemOpChains.push_back(Store);
2591 }
2592 }
2593
2594 if (!MemOpChains.empty())
2595 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
2596
2597 // Build a sequence of copy-to-reg nodes chained together with token chain
2598 // and flag operands which copy the outgoing args into the appropriate regs.
2599 SDValue InFlag;
2600 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2601 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2602 RegsToPass[i].second, InFlag);
2603 InFlag = Chain.getValue(1);
2604 }
2605
2606 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
2607 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
2608 // node so that legalize doesn't hack it.
2609 bool isDirect = false;
2610
2611 const TargetMachine &TM = getTargetMachine();
2612 const Module *Mod = MF.getFunction().getParent();
2613 const GlobalValue *GV = nullptr;
2614 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
2615 GV = G->getGlobal();
2616 bool isStub =
2617 !TM.shouldAssumeDSOLocal(*Mod, GV) && Subtarget->isTargetMachO();
2618
2619 bool isARMFunc = !Subtarget->isThumb() || (isStub && !Subtarget->isMClass());
2620 bool isLocalARMFunc = false;
2621 auto PtrVt = getPointerTy(DAG.getDataLayout());
2622
2623 if (Subtarget->genLongCalls()) {
2624 assert((!isPositionIndependent() || Subtarget->isTargetWindows()) &&(static_cast <bool> ((!isPositionIndependent() || Subtarget
->isTargetWindows()) && "long-calls codegen is not position independent!"
) ? void (0) : __assert_fail ("(!isPositionIndependent() || Subtarget->isTargetWindows()) && \"long-calls codegen is not position independent!\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 2625, __extension__
__PRETTY_FUNCTION__))
2625 "long-calls codegen is not position independent!")(static_cast <bool> ((!isPositionIndependent() || Subtarget
->isTargetWindows()) && "long-calls codegen is not position independent!"
) ? void (0) : __assert_fail ("(!isPositionIndependent() || Subtarget->isTargetWindows()) && \"long-calls codegen is not position independent!\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 2625, __extension__
__PRETTY_FUNCTION__))
;
2626 // Handle a global address or an external symbol. If it's not one of
2627 // those, the target's already in a register, so we don't need to do
2628 // anything extra.
2629 if (isa<GlobalAddressSDNode>(Callee)) {
2630 // Create a constant pool entry for the callee address
2631 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2632 ARMConstantPoolValue *CPV =
2633 ARMConstantPoolConstant::Create(GV, ARMPCLabelIndex, ARMCP::CPValue, 0);
2634
2635 // Get the address of the callee into a register
2636 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVt, Align(4));
2637 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2638 Callee = DAG.getLoad(
2639 PtrVt, dl, DAG.getEntryNode(), CPAddr,
2640 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
2641 } else if (ExternalSymbolSDNode *S=dyn_cast<ExternalSymbolSDNode>(Callee)) {
2642 const char *Sym = S->getSymbol();
2643
2644 // Create a constant pool entry for the callee address
2645 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2646 ARMConstantPoolValue *CPV =
2647 ARMConstantPoolSymbol::Create(*DAG.getContext(), Sym,
2648 ARMPCLabelIndex, 0);
2649 // Get the address of the callee into a register
2650 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVt, Align(4));
2651 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2652 Callee = DAG.getLoad(
2653 PtrVt, dl, DAG.getEntryNode(), CPAddr,
2654 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
2655 }
2656 } else if (isa<GlobalAddressSDNode>(Callee)) {
2657 if (!PreferIndirect) {
2658 isDirect = true;
2659 bool isDef = GV->isStrongDefinitionForLinker();
2660
2661 // ARM call to a local ARM function is predicable.
2662 isLocalARMFunc = !Subtarget->isThumb() && (isDef || !ARMInterworking);
2663 // tBX takes a register source operand.
2664 if (isStub && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) {
2665 assert(Subtarget->isTargetMachO() && "WrapperPIC use on non-MachO?")(static_cast <bool> (Subtarget->isTargetMachO() &&
"WrapperPIC use on non-MachO?") ? void (0) : __assert_fail (
"Subtarget->isTargetMachO() && \"WrapperPIC use on non-MachO?\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 2665, __extension__
__PRETTY_FUNCTION__))
;
2666 Callee = DAG.getNode(
2667 ARMISD::WrapperPIC, dl, PtrVt,
2668 DAG.getTargetGlobalAddress(GV, dl, PtrVt, 0, ARMII::MO_NONLAZY));
2669 Callee = DAG.getLoad(
2670 PtrVt, dl, DAG.getEntryNode(), Callee,
2671 MachinePointerInfo::getGOT(DAG.getMachineFunction()), MaybeAlign(),
2672 MachineMemOperand::MODereferenceable |
2673 MachineMemOperand::MOInvariant);
2674 } else if (Subtarget->isTargetCOFF()) {
2675 assert(Subtarget->isTargetWindows() &&(static_cast <bool> (Subtarget->isTargetWindows() &&
"Windows is the only supported COFF target") ? void (0) : __assert_fail
("Subtarget->isTargetWindows() && \"Windows is the only supported COFF target\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 2676, __extension__
__PRETTY_FUNCTION__))
2676 "Windows is the only supported COFF target")(static_cast <bool> (Subtarget->isTargetWindows() &&
"Windows is the only supported COFF target") ? void (0) : __assert_fail
("Subtarget->isTargetWindows() && \"Windows is the only supported COFF target\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 2676, __extension__
__PRETTY_FUNCTION__))
;
2677 unsigned TargetFlags = ARMII::MO_NO_FLAG;
2678 if (GV->hasDLLImportStorageClass())
2679 TargetFlags = ARMII::MO_DLLIMPORT;
2680 else if (!TM.shouldAssumeDSOLocal(*GV->getParent(), GV))
2681 TargetFlags = ARMII::MO_COFFSTUB;
2682 Callee = DAG.getTargetGlobalAddress(GV, dl, PtrVt, /*offset=*/0,
2683 TargetFlags);
2684 if (TargetFlags & (ARMII::MO_DLLIMPORT | ARMII::MO_COFFSTUB))
2685 Callee =
2686 DAG.getLoad(PtrVt, dl, DAG.getEntryNode(),
2687 DAG.getNode(ARMISD::Wrapper, dl, PtrVt, Callee),
2688 MachinePointerInfo::getGOT(DAG.getMachineFunction()));
2689 } else {
2690 Callee = DAG.getTargetGlobalAddress(GV, dl, PtrVt, 0, 0);
2691 }
2692 }
2693 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2694 isDirect = true;
2695 // tBX takes a register source operand.
2696 const char *Sym = S->getSymbol();
2697 if (isARMFunc && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) {
2698 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2699 ARMConstantPoolValue *CPV =
2700 ARMConstantPoolSymbol::Create(*DAG.getContext(), Sym,
2701 ARMPCLabelIndex, 4);
2702 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVt, Align(4));
2703 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2704 Callee = DAG.getLoad(
2705 PtrVt, dl, DAG.getEntryNode(), CPAddr,
2706 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
2707 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, dl, MVT::i32);
2708 Callee = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVt, Callee, PICLabel);
2709 } else {
2710 Callee = DAG.getTargetExternalSymbol(Sym, PtrVt, 0);
2711 }
2712 }
2713
2714 if (isCmseNSCall) {
2715 assert(!isARMFunc && !isDirect &&(static_cast <bool> (!isARMFunc && !isDirect &&
"Cannot handle call to ARM function or direct call") ? void (
0) : __assert_fail ("!isARMFunc && !isDirect && \"Cannot handle call to ARM function or direct call\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 2716, __extension__
__PRETTY_FUNCTION__))
2716 "Cannot handle call to ARM function or direct call")(static_cast <bool> (!isARMFunc && !isDirect &&
"Cannot handle call to ARM function or direct call") ? void (
0) : __assert_fail ("!isARMFunc && !isDirect && \"Cannot handle call to ARM function or direct call\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 2716, __extension__
__PRETTY_FUNCTION__))
;
2717 if (NumBytes > 0) {
2718 DiagnosticInfoUnsupported Diag(DAG.getMachineFunction().getFunction(),
2719 "call to non-secure function would "
2720 "require passing arguments on stack",
2721 dl.getDebugLoc());
2722 DAG.getContext()->diagnose(Diag);
2723 }
2724 if (isStructRet) {
2725 DiagnosticInfoUnsupported Diag(
2726 DAG.getMachineFunction().getFunction(),
2727 "call to non-secure function would return value through pointer",
2728 dl.getDebugLoc());
2729 DAG.getContext()->diagnose(Diag);
2730 }
2731 }
2732
2733 // FIXME: handle tail calls differently.
2734 unsigned CallOpc;
2735 if (Subtarget->isThumb()) {
2736 if (GuardWithBTI)
2737 CallOpc = ARMISD::t2CALL_BTI;
2738 else if (isCmseNSCall)
2739 CallOpc = ARMISD::tSECALL;
2740 else if ((!isDirect || isARMFunc) && !Subtarget->hasV5TOps())
2741 CallOpc = ARMISD::CALL_NOLINK;
2742 else
2743 CallOpc = ARMISD::CALL;
2744 } else {
2745 if (!isDirect && !Subtarget->hasV5TOps())
2746 CallOpc = ARMISD::CALL_NOLINK;
2747 else if (doesNotRet && isDirect && Subtarget->hasRetAddrStack() &&
2748 // Emit regular call when code size is the priority
2749 !Subtarget->hasMinSize())
2750 // "mov lr, pc; b _foo" to avoid confusing the RSP
2751 CallOpc = ARMISD::CALL_NOLINK;
2752 else
2753 CallOpc = isLocalARMFunc ? ARMISD::CALL_PRED : ARMISD::CALL;
2754 }
2755
2756 // We don't usually want to end the call-sequence here because we would tidy
2757 // the frame up *after* the call, however in the ABI-changing tail-call case
2758 // we've carefully laid out the parameters so that when sp is reset they'll be
2759 // in the correct location.
2760 if (isTailCall && !isSibCall) {
2761 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, dl, true),
2762 DAG.getIntPtrConstant(0, dl, true), InFlag, dl);
2763 InFlag = Chain.getValue(1);
2764 }
2765
2766 std::vector<SDValue> Ops;
2767 Ops.push_back(Chain);
2768 Ops.push_back(Callee);
2769
2770 if (isTailCall) {
2771 Ops.push_back(DAG.getTargetConstant(SPDiff, dl, MVT::i32));
2772 }
2773
2774 // Add argument registers to the end of the list so that they are known live
2775 // into the call.
2776 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2777 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2778 RegsToPass[i].second.getValueType()));
2779
2780 // Add a register mask operand representing the call-preserved registers.
2781 if (!isTailCall) {
2782 const uint32_t *Mask;
2783 const ARMBaseRegisterInfo *ARI = Subtarget->getRegisterInfo();
2784 if (isThisReturn) {
2785 // For 'this' returns, use the R0-preserving mask if applicable
2786 Mask = ARI->getThisReturnPreservedMask(MF, CallConv);
2787 if (!Mask) {
2788 // Set isThisReturn to false if the calling convention is not one that
2789 // allows 'returned' to be modeled in this way, so LowerCallResult does
2790 // not try to pass 'this' straight through
2791 isThisReturn = false;
2792 Mask = ARI->getCallPreservedMask(MF, CallConv);
2793 }
2794 } else
2795 Mask = ARI->getCallPreservedMask(MF, CallConv);
2796
2797 assert(Mask && "Missing call preserved mask for calling convention")(static_cast <bool> (Mask && "Missing call preserved mask for calling convention"
) ? void (0) : __assert_fail ("Mask && \"Missing call preserved mask for calling convention\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 2797, __extension__
__PRETTY_FUNCTION__))
;
2798 Ops.push_back(DAG.getRegisterMask(Mask));
2799 }
2800
2801 if (InFlag.getNode())
2802 Ops.push_back(InFlag);
2803
2804 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2805 if (isTailCall) {
2806 MF.getFrameInfo().setHasTailCall();
2807 SDValue Ret = DAG.getNode(ARMISD::TC_RETURN, dl, NodeTys, Ops);
2808 DAG.addCallSiteInfo(Ret.getNode(), std::move(CSInfo));
2809 return Ret;
2810 }
2811
2812 // Returns a chain and a flag for retval copy to use.
2813 Chain = DAG.getNode(CallOpc, dl, NodeTys, Ops);
2814 DAG.addNoMergeSiteInfo(Chain.getNode(), CLI.NoMerge);
2815 InFlag = Chain.getValue(1);
2816 DAG.addCallSiteInfo(Chain.getNode(), std::move(CSInfo));
2817
2818 // If we're guaranteeing tail-calls will be honoured, the callee must
2819 // pop its own argument stack on return. But this call is *not* a tail call so
2820 // we need to undo that after it returns to restore the status-quo.
2821 bool TailCallOpt = getTargetMachine().Options.GuaranteedTailCallOpt;
2822 uint64_t CalleePopBytes =
2823 canGuaranteeTCO(CallConv, TailCallOpt) ? alignTo(NumBytes, 16) : -1ULL;
2824
2825 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, dl, true),
2826 DAG.getIntPtrConstant(CalleePopBytes, dl, true),
2827 InFlag, dl);
2828 if (!Ins.empty())
2829 InFlag = Chain.getValue(1);
2830
2831 // Handle result values, copying them out of physregs into vregs that we
2832 // return.
2833 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins, dl, DAG,
2834 InVals, isThisReturn,
2835 isThisReturn ? OutVals[0] : SDValue());
2836}
2837
2838/// HandleByVal - Every parameter *after* a byval parameter is passed
2839/// on the stack. Remember the next parameter register to allocate,
2840/// and then confiscate the rest of the parameter registers to insure
2841/// this.
2842void ARMTargetLowering::HandleByVal(CCState *State, unsigned &Size,
2843 Align Alignment) const {
2844 // Byval (as with any stack) slots are always at least 4 byte aligned.
2845 Alignment = std::max(Alignment, Align(4));
2846
2847 unsigned Reg = State->AllocateReg(GPRArgRegs);
2848 if (!Reg)
2849 return;
2850
2851 unsigned AlignInRegs = Alignment.value() / 4;
2852 unsigned Waste = (ARM::R4 - Reg) % AlignInRegs;
2853 for (unsigned i = 0; i < Waste; ++i)
2854 Reg = State->AllocateReg(GPRArgRegs);
2855
2856 if (!Reg)
2857 return;
2858
2859 unsigned Excess = 4 * (ARM::R4 - Reg);
2860
2861 // Special case when NSAA != SP and parameter size greater than size of
2862 // all remained GPR regs. In that case we can't split parameter, we must
2863 // send it to stack. We also must set NCRN to R4, so waste all
2864 // remained registers.
2865 const unsigned NSAAOffset = State->getNextStackOffset();
2866 if (NSAAOffset != 0 && Size > Excess) {
2867 while (State->AllocateReg(GPRArgRegs))
2868 ;
2869 return;
2870 }
2871
2872 // First register for byval parameter is the first register that wasn't
2873 // allocated before this method call, so it would be "reg".
2874 // If parameter is small enough to be saved in range [reg, r4), then
2875 // the end (first after last) register would be reg + param-size-in-regs,
2876 // else parameter would be splitted between registers and stack,
2877 // end register would be r4 in this case.
2878 unsigned ByValRegBegin = Reg;
2879 unsigned ByValRegEnd = std::min<unsigned>(Reg + Size / 4, ARM::R4);
2880 State->addInRegsParamInfo(ByValRegBegin, ByValRegEnd);
2881 // Note, first register is allocated in the beginning of function already,
2882 // allocate remained amount of registers we need.
2883 for (unsigned i = Reg + 1; i != ByValRegEnd; ++i)
2884 State->AllocateReg(GPRArgRegs);
2885 // A byval parameter that is split between registers and memory needs its
2886 // size truncated here.
2887 // In the case where the entire structure fits in registers, we set the
2888 // size in memory to zero.
2889 Size = std::max<int>(Size - Excess, 0);
2890}
2891
2892/// MatchingStackOffset - Return true if the given stack call argument is
2893/// already available in the same position (relatively) of the caller's
2894/// incoming argument stack.
2895static
2896bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
2897 MachineFrameInfo &MFI, const MachineRegisterInfo *MRI,
2898 const TargetInstrInfo *TII) {
2899 unsigned Bytes = Arg.getValueSizeInBits() / 8;
2900 int FI = std::numeric_limits<int>::max();
2901 if (Arg.getOpcode() == ISD::CopyFromReg) {
2902 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
2903 if (!Register::isVirtualRegister(VR))
2904 return false;
2905 MachineInstr *Def = MRI->getVRegDef(VR);
2906 if (!Def)
2907 return false;
2908 if (!Flags.isByVal()) {
2909 if (!TII->isLoadFromStackSlot(*Def, FI))
2910 return false;
2911 } else {
2912 return false;
2913 }
2914 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
2915 if (Flags.isByVal())
2916 // ByVal argument is passed in as a pointer but it's now being
2917 // dereferenced. e.g.
2918 // define @foo(%struct.X* %A) {
2919 // tail call @bar(%struct.X* byval %A)
2920 // }
2921 return false;
2922 SDValue Ptr = Ld->getBasePtr();
2923 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
2924 if (!FINode)
2925 return false;
2926 FI = FINode->getIndex();
2927 } else
2928 return false;
2929
2930 assert(FI != std::numeric_limits<int>::max())(static_cast <bool> (FI != std::numeric_limits<int>
::max()) ? void (0) : __assert_fail ("FI != std::numeric_limits<int>::max()"
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 2930, __extension__
__PRETTY_FUNCTION__))
;
2931 if (!MFI.isFixedObjectIndex(FI))
2932 return false;
2933 return Offset == MFI.getObjectOffset(FI) && Bytes == MFI.getObjectSize(FI);
2934}
2935
2936/// IsEligibleForTailCallOptimization - Check whether the call is eligible
2937/// for tail call optimization. Targets which want to do tail call
2938/// optimization should implement this function.
2939bool ARMTargetLowering::IsEligibleForTailCallOptimization(
2940 SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg,
2941 bool isCalleeStructRet, bool isCallerStructRet,
2942 const SmallVectorImpl<ISD::OutputArg> &Outs,
2943 const SmallVectorImpl<SDValue> &OutVals,
2944 const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG,
2945 const bool isIndirect) const {
2946 MachineFunction &MF = DAG.getMachineFunction();
2947 const Function &CallerF = MF.getFunction();
2948 CallingConv::ID CallerCC = CallerF.getCallingConv();
2949
2950 assert(Subtarget->supportsTailCall())(static_cast <bool> (Subtarget->supportsTailCall()) ?
void (0) : __assert_fail ("Subtarget->supportsTailCall()"
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 2950, __extension__
__PRETTY_FUNCTION__))
;
2951
2952 // Indirect tail calls cannot be optimized for Thumb1 if the args
2953 // to the call take up r0-r3. The reason is that there are no legal registers
2954 // left to hold the pointer to the function to be called.
2955 // Similarly, if the function uses return address sign and authentication,
2956 // r12 is needed to hold the PAC and is not available to hold the callee
2957 // address.
2958 if (Outs.size() >= 4 &&
2959 (!isa<GlobalAddressSDNode>(Callee.getNode()) || isIndirect)) {
2960 if (Subtarget->isThumb1Only())
2961 return false;
2962 // Conservatively assume the function spills LR.
2963 if (MF.getInfo<ARMFunctionInfo>()->shouldSignReturnAddress(true))
2964 return false;
2965 }
2966
2967 // Look for obvious safe cases to perform tail call optimization that do not
2968 // require ABI changes. This is what gcc calls sibcall.
2969
2970 // Exception-handling functions need a special set of instructions to indicate
2971 // a return to the hardware. Tail-calling another function would probably
2972 // break this.
2973 if (CallerF.hasFnAttribute("interrupt"))
2974 return false;
2975
2976 if (canGuaranteeTCO(CalleeCC, getTargetMachine().Options.GuaranteedTailCallOpt))
2977 return CalleeCC == CallerCC;
2978
2979 // Also avoid sibcall optimization if either caller or callee uses struct
2980 // return semantics.
2981 if (isCalleeStructRet || isCallerStructRet)
2982 return false;
2983
2984 // Externally-defined functions with weak linkage should not be
2985 // tail-called on ARM when the OS does not support dynamic
2986 // pre-emption of symbols, as the AAELF spec requires normal calls
2987 // to undefined weak functions to be replaced with a NOP or jump to the
2988 // next instruction. The behaviour of branch instructions in this
2989 // situation (as used for tail calls) is implementation-defined, so we
2990 // cannot rely on the linker replacing the tail call with a return.
2991 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2992 const GlobalValue *GV = G->getGlobal();
2993 const Triple &TT = getTargetMachine().getTargetTriple();
2994 if (GV->hasExternalWeakLinkage() &&
2995 (!TT.isOSWindows() || TT.isOSBinFormatELF() || TT.isOSBinFormatMachO()))
2996 return false;
2997 }
2998
2999 // Check that the call results are passed in the same way.
3000 LLVMContext &C = *DAG.getContext();
3001 if (!CCState::resultsCompatible(
3002 getEffectiveCallingConv(CalleeCC, isVarArg),
3003 getEffectiveCallingConv(CallerCC, CallerF.isVarArg()), MF, C, Ins,
3004 CCAssignFnForReturn(CalleeCC, isVarArg),
3005 CCAssignFnForReturn(CallerCC, CallerF.isVarArg())))
3006 return false;
3007 // The callee has to preserve all registers the caller needs to preserve.
3008 const ARMBaseRegisterInfo *TRI = Subtarget->getRegisterInfo();
3009 const uint32_t *CallerPreserved = TRI->getCallPreservedMask(MF, CallerCC);
3010 if (CalleeCC != CallerCC) {
3011 const uint32_t *CalleePreserved = TRI->getCallPreservedMask(MF, CalleeCC);
3012 if (!TRI->regmaskSubsetEqual(CallerPreserved, CalleePreserved))
3013 return false;
3014 }
3015
3016 // If Caller's vararg or byval argument has been split between registers and
3017 // stack, do not perform tail call, since part of the argument is in caller's
3018 // local frame.
3019 const ARMFunctionInfo *AFI_Caller = MF.getInfo<ARMFunctionInfo>();
3020 if (AFI_Caller->getArgRegsSaveSize())
3021 return false;
3022
3023 // If the callee takes no arguments then go on to check the results of the
3024 // call.
3025 if (!Outs.empty()) {
3026 // Check if stack adjustment is needed. For now, do not do this if any
3027 // argument is passed on the stack.
3028 SmallVector<CCValAssign, 16> ArgLocs;
3029 CCState CCInfo(CalleeCC, isVarArg, MF, ArgLocs, C);
3030 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForCall(CalleeCC, isVarArg));
3031 if (CCInfo.getNextStackOffset()) {
3032 // Check if the arguments are already laid out in the right way as
3033 // the caller's fixed stack objects.
3034 MachineFrameInfo &MFI = MF.getFrameInfo();
3035 const MachineRegisterInfo *MRI = &MF.getRegInfo();
3036 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
3037 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size();
3038 i != e;
3039 ++i, ++realArgIdx) {
3040 CCValAssign &VA = ArgLocs[i];
3041 EVT RegVT = VA.getLocVT();
3042 SDValue Arg = OutVals[realArgIdx];
3043 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
3044 if (VA.getLocInfo() == CCValAssign::Indirect)
3045 return false;
3046 if (VA.needsCustom() && (RegVT == MVT::f64 || RegVT == MVT::v2f64)) {
3047 // f64 and vector types are split into multiple registers or
3048 // register/stack-slot combinations. The types will not match
3049 // the registers; give up on memory f64 refs until we figure
3050 // out what to do about this.
3051 if (!VA.isRegLoc())
3052 return false;
3053 if (!ArgLocs[++i].isRegLoc())
3054 return false;
3055 if (RegVT == MVT::v2f64) {
3056 if (!ArgLocs[++i].isRegLoc())
3057 return false;
3058 if (!ArgLocs[++i].isRegLoc())
3059 return false;
3060 }
3061 } else if (!VA.isRegLoc()) {
3062 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
3063 MFI, MRI, TII))
3064 return false;
3065 }
3066 }
3067 }
3068
3069 const MachineRegisterInfo &MRI = MF.getRegInfo();
3070 if (!parametersInCSRMatch(MRI, CallerPreserved, ArgLocs, OutVals))
3071 return false;
3072 }
3073
3074 return true;
3075}
3076
3077bool
3078ARMTargetLowering::CanLowerReturn(CallingConv::ID CallConv,
3079 MachineFunction &MF, bool isVarArg,
3080 const SmallVectorImpl<ISD::OutputArg> &Outs,
3081 LLVMContext &Context) const {
3082 SmallVector<CCValAssign, 16> RVLocs;
3083 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
3084 return CCInfo.CheckReturn(Outs, CCAssignFnForReturn(CallConv, isVarArg));
3085}
3086
3087static SDValue LowerInterruptReturn(SmallVectorImpl<SDValue> &RetOps,
3088 const SDLoc &DL, SelectionDAG &DAG) {
3089 const MachineFunction &MF = DAG.getMachineFunction();
3090 const Function &F = MF.getFunction();
3091
3092 StringRef IntKind = F.getFnAttribute("interrupt").getValueAsString();
3093
3094 // See ARM ARM v7 B1.8.3. On exception entry LR is set to a possibly offset
3095 // version of the "preferred return address". These offsets affect the return
3096 // instruction if this is a return from PL1 without hypervisor extensions.
3097 // IRQ/FIQ: +4 "subs pc, lr, #4"
3098 // SWI: 0 "subs pc, lr, #0"
3099 // ABORT: +4 "subs pc, lr, #4"
3100 // UNDEF: +4/+2 "subs pc, lr, #0"
3101 // UNDEF varies depending on where the exception came from ARM or Thumb
3102 // mode. Alongside GCC, we throw our hands up in disgust and pretend it's 0.
3103
3104 int64_t LROffset;
3105 if (IntKind == "" || IntKind == "IRQ" || IntKind == "FIQ" ||
3106 IntKind == "ABORT")
3107 LROffset = 4;
3108 else if (IntKind == "SWI" || IntKind == "UNDEF")
3109 LROffset = 0;
3110 else
3111 report_fatal_error("Unsupported interrupt attribute. If present, value "
3112 "must be one of: IRQ, FIQ, SWI, ABORT or UNDEF");
3113
3114 RetOps.insert(RetOps.begin() + 1,
3115 DAG.getConstant(LROffset, DL, MVT::i32, false));
3116
3117 return DAG.getNode(ARMISD::INTRET_FLAG, DL, MVT::Other, RetOps);
3118}
3119
3120SDValue
3121ARMTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
3122 bool isVarArg,
3123 const SmallVectorImpl<ISD::OutputArg> &Outs,
3124 const SmallVectorImpl<SDValue> &OutVals,
3125 const SDLoc &dl, SelectionDAG &DAG) const {
3126 // CCValAssign - represent the assignment of the return value to a location.
3127 SmallVector<CCValAssign, 16> RVLocs;
3128
3129 // CCState - Info about the registers and stack slots.
3130 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
3131 *DAG.getContext());
3132
3133 // Analyze outgoing return values.
3134 CCInfo.AnalyzeReturn(Outs, CCAssignFnForReturn(CallConv, isVarArg));
3135
3136 SDValue Flag;
3137 SmallVector<SDValue, 4> RetOps;
3138 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
3139 bool isLittleEndian = Subtarget->isLittle();
3140
3141 MachineFunction &MF = DAG.getMachineFunction();
3142 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
3143 AFI->setReturnRegsCount(RVLocs.size());
3144
3145 // Report error if cmse entry function returns structure through first ptr arg.
3146 if (AFI->isCmseNSEntryFunction() && MF.getFunction().hasStructRetAttr()) {
3147 // Note: using an empty SDLoc(), as the first line of the function is a
3148 // better place to report than the last line.
3149 DiagnosticInfoUnsupported Diag(
3150 DAG.getMachineFunction().getFunction(),
3151 "secure entry function would return value through pointer",
3152 SDLoc().getDebugLoc());
3153 DAG.getContext()->diagnose(Diag);
3154 }
3155
3156 // Copy the result values into the output registers.
3157 for (unsigned i = 0, realRVLocIdx = 0;
3158 i != RVLocs.size();
3159 ++i, ++realRVLocIdx) {
3160 CCValAssign &VA = RVLocs[i];
3161 assert(VA.isRegLoc() && "Can only return in registers!")(static_cast <bool> (VA.isRegLoc() && "Can only return in registers!"
) ? void (0) : __assert_fail ("VA.isRegLoc() && \"Can only return in registers!\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 3161, __extension__
__PRETTY_FUNCTION__))
;
3162
3163 SDValue Arg = OutVals[realRVLocIdx];
3164 bool ReturnF16 = false;
3165
3166 if (Subtarget->hasFullFP16() && Subtarget->isTargetHardFloat()) {
3167 // Half-precision return values can be returned like this:
3168 //
3169 // t11 f16 = fadd ...
3170 // t12: i16 = bitcast t11
3171 // t13: i32 = zero_extend t12
3172 // t14: f32 = bitcast t13 <~~~~~~~ Arg
3173 //
3174 // to avoid code generation for bitcasts, we simply set Arg to the node
3175 // that produces the f16 value, t11 in this case.
3176 //
3177 if (Arg.getValueType() == MVT::f32 && Arg.getOpcode() == ISD::BITCAST) {
3178 SDValue ZE = Arg.getOperand(0);
3179 if (ZE.getOpcode() == ISD::ZERO_EXTEND && ZE.getValueType() == MVT::i32) {
3180 SDValue BC = ZE.getOperand(0);
3181 if (BC.getOpcode() == ISD::BITCAST && BC.getValueType() == MVT::i16) {
3182 Arg = BC.getOperand(0);
3183 ReturnF16 = true;
3184 }
3185 }
3186 }
3187 }
3188
3189 switch (VA.getLocInfo()) {
3190 default: llvm_unreachable("Unknown loc info!")::llvm::llvm_unreachable_internal("Unknown loc info!", "llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3190)
;
3191 case CCValAssign::Full: break;
3192 case CCValAssign::BCvt:
3193 if (!ReturnF16)
3194 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
3195 break;
3196 }
3197
3198 // Mask f16 arguments if this is a CMSE nonsecure entry.
3199 auto RetVT = Outs[realRVLocIdx].ArgVT;
3200 if (AFI->isCmseNSEntryFunction() && (RetVT == MVT::f16)) {
3201 if (VA.needsCustom() && VA.getValVT() == MVT::f16) {
3202 Arg = MoveFromHPR(dl, DAG, VA.getLocVT(), VA.getValVT(), Arg);
3203 } else {
3204 auto LocBits = VA.getLocVT().getSizeInBits();
3205 auto MaskValue = APInt::getLowBitsSet(LocBits, RetVT.getSizeInBits());
3206 SDValue Mask =
3207 DAG.getConstant(MaskValue, dl, MVT::getIntegerVT(LocBits));
3208 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::getIntegerVT(LocBits), Arg);
3209 Arg = DAG.getNode(ISD::AND, dl, MVT::getIntegerVT(LocBits), Arg, Mask);
3210 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
3211 }
3212 }
3213
3214 if (VA.needsCustom() &&
3215 (VA.getLocVT() == MVT::v2f64 || VA.getLocVT() == MVT::f64)) {
3216 if (VA.getLocVT() == MVT::v2f64) {
3217 // Extract the first half and return it in two registers.
3218 SDValue Half = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
3219 DAG.getConstant(0, dl, MVT::i32));
3220 SDValue HalfGPRs = DAG.getNode(ARMISD::VMOVRRD, dl,
3221 DAG.getVTList(MVT::i32, MVT::i32), Half);
3222
3223 Chain =
3224 DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
3225 HalfGPRs.getValue(isLittleEndian ? 0 : 1), Flag);
3226 Flag = Chain.getValue(1);
3227 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
3228 VA = RVLocs[++i]; // skip ahead to next loc
3229 Chain =
3230 DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
3231 HalfGPRs.getValue(isLittleEndian ? 1 : 0), Flag);
3232 Flag = Chain.getValue(1);
3233 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
3234 VA = RVLocs[++i]; // skip ahead to next loc
3235
3236 // Extract the 2nd half and fall through to handle it as an f64 value.
3237 Arg = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
3238 DAG.getConstant(1, dl, MVT::i32));
3239 }
3240 // Legalize ret f64 -> ret 2 x i32. We always have fmrrd if f64 is
3241 // available.
3242 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl,
3243 DAG.getVTList(MVT::i32, MVT::i32), Arg);
3244 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
3245 fmrrd.getValue(isLittleEndian ? 0 : 1), Flag);
3246 Flag = Chain.getValue(1);
3247 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
3248 VA = RVLocs[++i]; // skip ahead to next loc
3249 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
3250 fmrrd.getValue(isLittleEndian ? 1 : 0), Flag);
3251 } else
3252 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag);
3253
3254 // Guarantee that all emitted copies are
3255 // stuck together, avoiding something bad.
3256 Flag = Chain.getValue(1);
3257 RetOps.push_back(DAG.getRegister(
3258 VA.getLocReg(), ReturnF16 ? Arg.getValueType() : VA.getLocVT()));
3259 }
3260 const ARMBaseRegisterInfo *TRI = Subtarget->getRegisterInfo();
3261 const MCPhysReg *I =
3262 TRI->getCalleeSavedRegsViaCopy(&DAG.getMachineFunction());
3263 if (I) {
3264 for (; *I; ++I) {
3265 if (ARM::GPRRegClass.contains(*I))
3266 RetOps.push_back(DAG.getRegister(*I, MVT::i32));
3267 else if (ARM::DPRRegClass.contains(*I))
3268 RetOps.push_back(DAG.getRegister(*I, MVT::getFloatingPointVT(64)));
3269 else
3270 llvm_unreachable("Unexpected register class in CSRsViaCopy!")::llvm::llvm_unreachable_internal("Unexpected register class in CSRsViaCopy!"
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 3270)
;
3271 }
3272 }
3273
3274 // Update chain and glue.
3275 RetOps[0] = Chain;
3276 if (Flag.getNode())
3277 RetOps.push_back(Flag);
3278
3279 // CPUs which aren't M-class use a special sequence to return from
3280 // exceptions (roughly, any instruction setting pc and cpsr simultaneously,
3281 // though we use "subs pc, lr, #N").
3282 //
3283 // M-class CPUs actually use a normal return sequence with a special
3284 // (hardware-provided) value in LR, so the normal code path works.
3285 if (DAG.getMachineFunction().getFunction().hasFnAttribute("interrupt") &&
3286 !Subtarget->isMClass()) {
3287 if (Subtarget->isThumb1Only())
3288 report_fatal_error("interrupt attribute is not supported in Thumb1");
3289 return LowerInterruptReturn(RetOps, dl, DAG);
3290 }
3291
3292 ARMISD::NodeType RetNode = AFI->isCmseNSEntryFunction() ? ARMISD::SERET_FLAG :
3293 ARMISD::RET_FLAG;
3294 return DAG.getNode(RetNode, dl, MVT::Other, RetOps);
3295}
3296
3297bool ARMTargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
3298 if (N->getNumValues() != 1)
3299 return false;
3300 if (!N->hasNUsesOfValue(1, 0))
3301 return false;
3302
3303 SDValue TCChain = Chain;
3304 SDNode *Copy = *N->use_begin();
3305 if (Copy->getOpcode() == ISD::CopyToReg) {
3306 // If the copy has a glue operand, we conservatively assume it isn't safe to
3307 // perform a tail call.
3308 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
3309 return false;
3310 TCChain = Copy->getOperand(0);
3311 } else if (Copy->getOpcode() == ARMISD::VMOVRRD) {
3312 SDNode *VMov = Copy;
3313 // f64 returned in a pair of GPRs.
3314 SmallPtrSet<SDNode*, 2> Copies;
3315 for (SDNode *U : VMov->uses()) {
3316 if (U->getOpcode() != ISD::CopyToReg)
3317 return false;
3318 Copies.insert(U);
3319 }
3320 if (Copies.size() > 2)
3321 return false;
3322
3323 for (SDNode *U : VMov->uses()) {
3324 SDValue UseChain = U->getOperand(0);
3325 if (Copies.count(UseChain.getNode()))
3326 // Second CopyToReg
3327 Copy = U;
3328 else {
3329 // We are at the top of this chain.
3330 // If the copy has a glue operand, we conservatively assume it
3331 // isn't safe to perform a tail call.
3332 if (U->getOperand(U->getNumOperands() - 1).getValueType() == MVT::Glue)
3333 return false;
3334 // First CopyToReg
3335 TCChain = UseChain;
3336 }
3337 }
3338 } else if (Copy->getOpcode() == ISD::BITCAST) {
3339 // f32 returned in a single GPR.
3340 if (!Copy->hasOneUse())
3341 return false;
3342 Copy = *Copy->use_begin();
3343 if (Copy->getOpcode() != ISD::CopyToReg || !Copy->hasNUsesOfValue(1, 0))
3344 return false;
3345 // If the copy has a glue operand, we conservatively assume it isn't safe to
3346 // perform a tail call.
3347 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
3348 return false;
3349 TCChain = Copy->getOperand(0);
3350 } else {
3351 return false;
3352 }
3353
3354 bool HasRet = false;
3355 for (const SDNode *U : Copy->uses()) {
3356 if (U->getOpcode() != ARMISD::RET_FLAG &&
3357 U->getOpcode() != ARMISD::INTRET_FLAG)
3358 return false;
3359 HasRet = true;
3360 }
3361
3362 if (!HasRet)
3363 return false;
3364
3365 Chain = TCChain;
3366 return true;
3367}
3368
3369bool ARMTargetLowering::mayBeEmittedAsTailCall(const CallInst *CI) const {
3370 if (!Subtarget->supportsTailCall())
3371 return false;
3372
3373 if (!CI->isTailCall())
3374 return false;
3375
3376 return true;
3377}
3378
3379// Trying to write a 64 bit value so need to split into two 32 bit values first,
3380// and pass the lower and high parts through.
3381static SDValue LowerWRITE_REGISTER(SDValue Op, SelectionDAG &DAG) {
3382 SDLoc DL(Op);
3383 SDValue WriteValue = Op->getOperand(2);
3384
3385 // This function is only supposed to be called for i64 type argument.
3386 assert(WriteValue.getValueType() == MVT::i64(static_cast <bool> (WriteValue.getValueType() == MVT::
i64 && "LowerWRITE_REGISTER called for non-i64 type argument."
) ? void (0) : __assert_fail ("WriteValue.getValueType() == MVT::i64 && \"LowerWRITE_REGISTER called for non-i64 type argument.\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 3387, __extension__
__PRETTY_FUNCTION__))
3387 && "LowerWRITE_REGISTER called for non-i64 type argument.")(static_cast <bool> (WriteValue.getValueType() == MVT::
i64 && "LowerWRITE_REGISTER called for non-i64 type argument."
) ? void (0) : __assert_fail ("WriteValue.getValueType() == MVT::i64 && \"LowerWRITE_REGISTER called for non-i64 type argument.\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 3387, __extension__
__PRETTY_FUNCTION__))
;
3388
3389 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, WriteValue,
3390 DAG.getConstant(0, DL, MVT::i32));
3391 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, WriteValue,
3392 DAG.getConstant(1, DL, MVT::i32));
3393 SDValue Ops[] = { Op->getOperand(0), Op->getOperand(1), Lo, Hi };
3394 return DAG.getNode(ISD::WRITE_REGISTER, DL, MVT::Other, Ops);
3395}
3396
3397// ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
3398// their target counterpart wrapped in the ARMISD::Wrapper node. Suppose N is
3399// one of the above mentioned nodes. It has to be wrapped because otherwise
3400// Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
3401// be used to form addressing mode. These wrapped nodes will be selected
3402// into MOVi.
3403SDValue ARMTargetLowering::LowerConstantPool(SDValue Op,
3404 SelectionDAG &DAG) const {
3405 EVT PtrVT = Op.getValueType();
3406 // FIXME there is no actual debug info here
3407 SDLoc dl(Op);
3408 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
3409 SDValue Res;
3410
3411 // When generating execute-only code Constant Pools must be promoted to the
3412 // global data section. It's a bit ugly that we can't share them across basic
3413 // blocks, but this way we guarantee that execute-only behaves correct with
3414 // position-independent addressing modes.
3415 if (Subtarget->genExecuteOnly()) {
3416 auto AFI = DAG.getMachineFunction().getInfo<ARMFunctionInfo>();
3417 auto T = const_cast<Type*>(CP->getType());
3418 auto C = const_cast<Constant*>(CP->getConstVal());
3419 auto M = const_cast<Module*>(DAG.getMachineFunction().
3420 getFunction().getParent());
3421 auto GV = new GlobalVariable(
3422 *M, T, /*isConstant=*/true, GlobalVariable::InternalLinkage, C,
3423 Twine(DAG.getDataLayout().getPrivateGlobalPrefix()) + "CP" +
3424 Twine(DAG.getMachineFunction().getFunctionNumber()) + "_" +
3425 Twine(AFI->createPICLabelUId())
3426 );
3427 SDValue GA = DAG.getTargetGlobalAddress(dyn_cast<GlobalValue>(GV),
3428 dl, PtrVT);
3429 return LowerGlobalAddress(GA, DAG);
3430 }
3431
3432 if (CP->isMachineConstantPoolEntry())
3433 Res =
3434 DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT, CP->getAlign());
3435 else
3436 Res = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CP->getAlign());
3437 return DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Res);
3438}
3439
3440unsigned ARMTargetLowering::getJumpTableEncoding() const {
3441 return MachineJumpTableInfo::EK_Inline;
3442}
3443
3444SDValue ARMTargetLowering::LowerBlockAddress(SDValue Op,
3445 SelectionDAG &DAG) const {
3446 MachineFunction &MF = DAG.getMachineFunction();
3447 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
3448 unsigned ARMPCLabelIndex = 0;
3449 SDLoc DL(Op);
3450 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3451 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
3452 SDValue CPAddr;
3453 bool IsPositionIndependent = isPositionIndependent() || Subtarget->isROPI();
3454 if (!IsPositionIndependent) {
3455 CPAddr = DAG.getTargetConstantPool(BA, PtrVT, Align(4));
3456 } else {
3457 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8;
3458 ARMPCLabelIndex = AFI->createPICLabelUId();
3459 ARMConstantPoolValue *CPV =
3460 ARMConstantPoolConstant::Create(BA, ARMPCLabelIndex,
3461 ARMCP::CPBlockAddress, PCAdj);
3462 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, Align(4));
3463 }
3464 CPAddr = DAG.getNode(ARMISD::Wrapper, DL, PtrVT, CPAddr);
3465 SDValue Result = DAG.getLoad(
3466 PtrVT, DL, DAG.getEntryNode(), CPAddr,
3467 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
3468 if (!IsPositionIndependent)
3469 return Result;
3470 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, DL, MVT::i32);
3471 return DAG.getNode(ARMISD::PIC_ADD, DL, PtrVT, Result, PICLabel);
3472}
3473
3474/// Convert a TLS address reference into the correct sequence of loads
3475/// and calls to compute the variable's address for Darwin, and return an
3476/// SDValue containing the final node.
3477
3478/// Darwin only has one TLS scheme which must be capable of dealing with the
3479/// fully general situation, in the worst case. This means:
3480/// + "extern __thread" declaration.
3481/// + Defined in a possibly unknown dynamic library.
3482///
3483/// The general system is that each __thread variable has a [3 x i32] descriptor
3484/// which contains information used by the runtime to calculate the address. The
3485/// only part of this the compiler needs to know about is the first word, which
3486/// contains a function pointer that must be called with the address of the
3487/// entire descriptor in "r0".
3488///
3489/// Since this descriptor may be in a different unit, in general access must
3490/// proceed along the usual ARM rules. A common sequence to produce is:
3491///
3492/// movw rT1, :lower16:_var$non_lazy_ptr
3493/// movt rT1, :upper16:_var$non_lazy_ptr
3494/// ldr r0, [rT1]
3495/// ldr rT2, [r0]
3496/// blx rT2
3497/// [...address now in r0...]
3498SDValue
3499ARMTargetLowering::LowerGlobalTLSAddressDarwin(SDValue Op,
3500 SelectionDAG &DAG) const {
3501 assert(Subtarget->isTargetDarwin() &&(static_cast <bool> (Subtarget->isTargetDarwin() &&
"This function expects a Darwin target") ? void (0) : __assert_fail
("Subtarget->isTargetDarwin() && \"This function expects a Darwin target\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 3502, __extension__
__PRETTY_FUNCTION__))
3502 "This function expects a Darwin target")(static_cast <bool> (Subtarget->isTargetDarwin() &&
"This function expects a Darwin target") ? void (0) : __assert_fail
("Subtarget->isTargetDarwin() && \"This function expects a Darwin target\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 3502, __extension__
__PRETTY_FUNCTION__))
;
3503 SDLoc DL(Op);
3504
3505 // First step is to get the address of the actua global symbol. This is where
3506 // the TLS descriptor lives.
3507 SDValue DescAddr = LowerGlobalAddressDarwin(Op, DAG);
3508
3509 // The first entry in the descriptor is a function pointer that we must call
3510 // to obtain the address of the variable.
3511 SDValue Chain = DAG.getEntryNode();
3512 SDValue FuncTLVGet = DAG.getLoad(
3513 MVT::i32, DL, Chain, DescAddr,
3514 MachinePointerInfo::getGOT(DAG.getMachineFunction()), Align(4),
3515 MachineMemOperand::MONonTemporal | MachineMemOperand::MODereferenceable |
3516 MachineMemOperand::MOInvariant);
3517 Chain = FuncTLVGet.getValue(1);
3518
3519 MachineFunction &F = DAG.getMachineFunction();
3520 MachineFrameInfo &MFI = F.getFrameInfo();
3521 MFI.setAdjustsStack(true);
3522
3523 // TLS calls preserve all registers except those that absolutely must be
3524 // trashed: R0 (it takes an argument), LR (it's a call) and CPSR (let's not be
3525 // silly).
3526 auto TRI =
3527 getTargetMachine().getSubtargetImpl(F.getFunction())->getRegisterInfo();
3528 auto ARI = static_cast<const ARMRegisterInfo *>(TRI);
3529 const uint32_t *Mask = ARI->getTLSCallPreservedMask(DAG.getMachineFunction());
3530
3531 // Finally, we can make the call. This is just a degenerate version of a
3532 // normal AArch64 call node: r0 takes the address of the descriptor, and
3533 // returns the address of the variable in this thread.
3534 Chain = DAG.getCopyToReg(Chain, DL, ARM::R0, DescAddr, SDValue());
3535 Chain =
3536 DAG.getNode(ARMISD::CALL, DL, DAG.getVTList(MVT::Other, MVT::Glue),
3537 Chain, FuncTLVGet, DAG.getRegister(ARM::R0, MVT::i32),
3538 DAG.getRegisterMask(Mask), Chain.getValue(1));
3539 return DAG.getCopyFromReg(Chain, DL, ARM::R0, MVT::i32, Chain.getValue(1));
3540}
3541
3542SDValue
3543ARMTargetLowering::LowerGlobalTLSAddressWindows(SDValue Op,
3544 SelectionDAG &DAG) const {
3545 assert(Subtarget->isTargetWindows() && "Windows specific TLS lowering")(static_cast <bool> (Subtarget->isTargetWindows() &&
"Windows specific TLS lowering") ? void (0) : __assert_fail (
"Subtarget->isTargetWindows() && \"Windows specific TLS lowering\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 3545, __extension__
__PRETTY_FUNCTION__))
;
3546
3547 SDValue Chain = DAG.getEntryNode();
3548 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3549 SDLoc DL(Op);
3550
3551 // Load the current TEB (thread environment block)
3552 SDValue Ops[] = {Chain,
3553 DAG.getTargetConstant(Intrinsic::arm_mrc, DL, MVT::i32),
3554 DAG.getTargetConstant(15, DL, MVT::i32),
3555 DAG.getTargetConstant(0, DL, MVT::i32),
3556 DAG.getTargetConstant(13, DL, MVT::i32),
3557 DAG.getTargetConstant(0, DL, MVT::i32),
3558 DAG.getTargetConstant(2, DL, MVT::i32)};
3559 SDValue CurrentTEB = DAG.getNode(ISD::INTRINSIC_W_CHAIN, DL,
3560 DAG.getVTList(MVT::i32, MVT::Other), Ops);
3561
3562 SDValue TEB = CurrentTEB.getValue(0);
3563 Chain = CurrentTEB.getValue(1);
3564
3565 // Load the ThreadLocalStoragePointer from the TEB
3566 // A pointer to the TLS array is located at offset 0x2c from the TEB.
3567 SDValue TLSArray =
3568 DAG.getNode(ISD::ADD, DL, PtrVT, TEB, DAG.getIntPtrConstant(0x2c, DL));
3569 TLSArray = DAG.getLoad(PtrVT, DL, Chain, TLSArray, MachinePointerInfo());
3570
3571 // The pointer to the thread's TLS data area is at the TLS Index scaled by 4
3572 // offset into the TLSArray.
3573
3574 // Load the TLS index from the C runtime
3575 SDValue TLSIndex =
3576 DAG.getTargetExternalSymbol("_tls_index", PtrVT, ARMII::MO_NO_FLAG);
3577 TLSIndex = DAG.getNode(ARMISD::Wrapper, DL, PtrVT, TLSIndex);
3578 TLSIndex = DAG.getLoad(PtrVT, DL, Chain, TLSIndex, MachinePointerInfo());
3579
3580 SDValue Slot = DAG.getNode(ISD::SHL, DL, PtrVT, TLSIndex,
3581 DAG.getConstant(2, DL, MVT::i32));
3582 SDValue TLS = DAG.getLoad(PtrVT, DL, Chain,
3583 DAG.getNode(ISD::ADD, DL, PtrVT, TLSArray, Slot),
3584 MachinePointerInfo());
3585
3586 // Get the offset of the start of the .tls section (section base)
3587 const auto *GA = cast<GlobalAddressSDNode>(Op);
3588 auto *CPV = ARMConstantPoolConstant::Create(GA->getGlobal(), ARMCP::SECREL);
3589 SDValue Offset = DAG.getLoad(
3590 PtrVT, DL, Chain,
3591 DAG.getNode(ARMISD::Wrapper, DL, MVT::i32,
3592 DAG.getTargetConstantPool(CPV, PtrVT, Align(4))),
3593 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
3594
3595 return DAG.getNode(ISD::ADD, DL, PtrVT, TLS, Offset);
3596}
3597
3598// Lower ISD::GlobalTLSAddress using the "general dynamic" model
3599SDValue
3600ARMTargetLowering::LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
3601 SelectionDAG &DAG) const {
3602 SDLoc dl(GA);
3603 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3604 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
3605 MachineFunction &MF = DAG.getMachineFunction();
3606 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
3607 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
3608 ARMConstantPoolValue *CPV =
3609 ARMConstantPoolConstant::Create(GA->getGlobal(), ARMPCLabelIndex,
3610 ARMCP::CPValue, PCAdj, ARMCP::TLSGD, true);
3611 SDValue Argument = DAG.getTargetConstantPool(CPV, PtrVT, Align(4));
3612 Argument = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Argument);
3613 Argument = DAG.getLoad(
3614 PtrVT, dl, DAG.getEntryNode(), Argument,
3615 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
3616 SDValue Chain = Argument.getValue(1);
3617
3618 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, dl, MVT::i32);
3619 Argument = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Argument, PICLabel);
3620
3621 // call __tls_get_addr.
3622 ArgListTy Args;
3623 ArgListEntry Entry;
3624 Entry.Node = Argument;
3625 Entry.Ty = (Type *) Type::getInt32Ty(*DAG.getContext());
3626 Args.push_back(Entry);
3627
3628 // FIXME: is there useful debug info available here?
3629 TargetLowering::CallLoweringInfo CLI(DAG);
3630 CLI.setDebugLoc(dl).setChain(Chain).setLibCallee(
3631 CallingConv::C, Type::getInt32Ty(*DAG.getContext()),
3632 DAG.getExternalSymbol("__tls_get_addr", PtrVT), std::move(Args));
3633
3634 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
3635 return CallResult.first;
3636}
3637
3638// Lower ISD::GlobalTLSAddress using the "initial exec" or
3639// "local exec" model.
3640SDValue
3641ARMTargetLowering::LowerToTLSExecModels(GlobalAddressSDNode *GA,
3642 SelectionDAG &DAG,
3643 TLSModel::Model model) const {
3644 const GlobalValue *GV = GA->getGlobal();
3645 SDLoc dl(GA);
3646 SDValue Offset;
3647 SDValue Chain = DAG.getEntryNode();
3648 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3649 // Get the Thread Pointer
3650 SDValue ThreadPointer = DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
3651
3652 if (model == TLSModel::InitialExec) {
3653 MachineFunction &MF = DAG.getMachineFunction();
3654 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
3655 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
3656 // Initial exec model.
3657 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
3658 ARMConstantPoolValue *CPV =
3659 ARMConstantPoolConstant::Create(GA->getGlobal(), ARMPCLabelIndex,
3660 ARMCP::CPValue, PCAdj, ARMCP::GOTTPOFF,
3661 true);
3662 Offset = DAG.getTargetConstantPool(CPV, PtrVT, Align(4));
3663 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
3664 Offset = DAG.getLoad(
3665 PtrVT, dl, Chain, Offset,
3666 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
3667 Chain = Offset.getValue(1);
3668
3669 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, dl, MVT::i32);
3670 Offset = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Offset, PICLabel);
3671
3672 Offset = DAG.getLoad(
3673 PtrVT, dl, Chain, Offset,
3674 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
3675 } else {
3676 // local exec model
3677 assert(model == TLSModel::LocalExec)(static_cast <bool> (model == TLSModel::LocalExec) ? void
(0) : __assert_fail ("model == TLSModel::LocalExec", "llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3677, __extension__ __PRETTY_FUNCTION__))
;
3678 ARMConstantPoolValue *CPV =
3679 ARMConstantPoolConstant::Create(GV, ARMCP::TPOFF);
3680 Offset = DAG.getTargetConstantPool(CPV, PtrVT, Align(4));
3681 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
3682 Offset = DAG.getLoad(
3683 PtrVT, dl, Chain, Offset,
3684 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
3685 }
3686
3687 // The address of the thread local variable is the add of the thread
3688 // pointer with the offset of the variable.
3689 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
3690}
3691
3692SDValue
3693ARMTargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
3694 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
3695 if (DAG.getTarget().useEmulatedTLS())
3696 return LowerToTLSEmulatedModel(GA, DAG);
3697
3698 if (Subtarget->isTargetDarwin())
3699 return LowerGlobalTLSAddressDarwin(Op, DAG);
3700
3701 if (Subtarget->isTargetWindows())
3702 return LowerGlobalTLSAddressWindows(Op, DAG);
3703
3704 // TODO: implement the "local dynamic" model
3705 assert(Subtarget->isTargetELF() && "Only ELF implemented here")(static_cast <bool> (Subtarget->isTargetELF() &&
"Only ELF implemented here") ? void (0) : __assert_fail ("Subtarget->isTargetELF() && \"Only ELF implemented here\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 3705, __extension__
__PRETTY_FUNCTION__))
;
3706 TLSModel::Model model = getTargetMachine().getTLSModel(GA->getGlobal());
3707
3708 switch (model) {
3709 case TLSModel::GeneralDynamic:
3710 case TLSModel::LocalDynamic:
3711 return LowerToTLSGeneralDynamicModel(GA, DAG);
3712 case TLSModel::InitialExec:
3713 case TLSModel::LocalExec:
3714 return LowerToTLSExecModels(GA, DAG, model);
3715 }
3716 llvm_unreachable("bogus TLS model")::llvm::llvm_unreachable_internal("bogus TLS model", "llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3716)
;
3717}
3718
3719/// Return true if all users of V are within function F, looking through
3720/// ConstantExprs.
3721static bool allUsersAreInFunction(const Value *V, const Function *F) {
3722 SmallVector<const User*,4> Worklist(V->users());
3723 while (!Worklist.empty()) {
3724 auto *U = Worklist.pop_back_val();
3725 if (isa<ConstantExpr>(U)) {
3726 append_range(Worklist, U->users());
3727 continue;
3728 }
3729
3730 auto *I = dyn_cast<Instruction>(U);
3731 if (!I || I->getParent()->getParent() != F)
3732 return false;
3733 }
3734 return true;
3735}
3736
3737static SDValue promoteToConstantPool(const ARMTargetLowering *TLI,
3738 const GlobalValue *GV, SelectionDAG &DAG,
3739 EVT PtrVT, const SDLoc &dl) {
3740 // If we're creating a pool entry for a constant global with unnamed address,
3741 // and the global is small enough, we can emit it inline into the constant pool
3742 // to save ourselves an indirection.
3743 //
3744 // This is a win if the constant is only used in one function (so it doesn't
3745 // need to be duplicated) or duplicating the constant wouldn't increase code
3746 // size (implying the constant is no larger than 4 bytes).
3747 const Function &F = DAG.getMachineFunction().getFunction();
3748
3749 // We rely on this decision to inline being idemopotent and unrelated to the
3750 // use-site. We know that if we inline a variable at one use site, we'll
3751 // inline it elsewhere too (and reuse the constant pool entry). Fast-isel
3752 // doesn't know about this optimization, so bail out if it's enabled else
3753 // we could decide to inline here (and thus never emit the GV) but require
3754 // the GV from fast-isel generated code.
3755 if (!EnableConstpoolPromotion ||
3756 DAG.getMachineFunction().getTarget().Options.EnableFastISel)
3757 return SDValue();
3758
3759 auto *GVar = dyn_cast<GlobalVariable>(GV);
3760 if (!GVar || !GVar->hasInitializer() ||
3761 !GVar->isConstant() || !GVar->hasGlobalUnnamedAddr() ||
3762 !GVar->hasLocalLinkage())
3763 return SDValue();
3764
3765 // If we inline a value that contains relocations, we move the relocations
3766 // from .data to .text. This is not allowed in position-independent code.
3767 auto *Init = GVar->getInitializer();
3768 if ((TLI->isPositionIndependent() || TLI->getSubtarget()->isROPI()) &&
3769 Init->needsDynamicRelocation())
3770 return SDValue();
3771
3772 // The constant islands pass can only really deal with alignment requests
3773 // <= 4 bytes and cannot pad constants itself. Therefore we cannot promote
3774 // any type wanting greater alignment requirements than 4 bytes. We also
3775 // can only promote constants that are multiples of 4 bytes in size or
3776 // are paddable to a multiple of 4. Currently we only try and pad constants
3777 // that are strings for simplicity.
3778 auto *CDAInit = dyn_cast<ConstantDataArray>(Init);
3779 unsigned Size = DAG.getDataLayout().getTypeAllocSize(Init->getType());
3780 Align PrefAlign = DAG.getDataLayout().getPreferredAlign(GVar);
3781 unsigned RequiredPadding = 4 - (Size % 4);
3782 bool PaddingPossible =
3783 RequiredPadding == 4 || (CDAInit && CDAInit->isString());
3784 if (!PaddingPossible || PrefAlign > 4 || Size > ConstpoolPromotionMaxSize ||
3785 Size == 0)
3786 return SDValue();
3787
3788 unsigned PaddedSize = Size + ((RequiredPadding == 4) ? 0 : RequiredPadding);
3789 MachineFunction &MF = DAG.getMachineFunction();
3790 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
3791
3792 // We can't bloat the constant pool too much, else the ConstantIslands pass
3793 // may fail to converge. If we haven't promoted this global yet (it may have
3794 // multiple uses), and promoting it would increase the constant pool size (Sz
3795 // > 4), ensure we have space to do so up to MaxTotal.
3796 if (!AFI->getGlobalsPromotedToConstantPool().count(GVar) && Size > 4)
3797 if (AFI->getPromotedConstpoolIncrease() + PaddedSize - 4 >=
3798 ConstpoolPromotionMaxTotal)
3799 return SDValue();
3800
3801 // This is only valid if all users are in a single function; we can't clone
3802 // the constant in general. The LLVM IR unnamed_addr allows merging
3803 // constants, but not cloning them.
3804 //
3805 // We could potentially allow cloning if we could prove all uses of the
3806 // constant in the current function don't care about the address, like
3807 // printf format strings. But that isn't implemented for now.
3808 if (!allUsersAreInFunction(GVar, &F))
3809 return SDValue();
3810
3811 // We're going to inline this global. Pad it out if needed.
3812 if (RequiredPadding != 4) {
3813 StringRef S = CDAInit->getAsString();
3814
3815 SmallVector<uint8_t,16> V(S.size());
3816 std::copy(S.bytes_begin(), S.bytes_end(), V.begin());
3817 while (RequiredPadding--)
3818 V.push_back(0);
3819 Init = ConstantDataArray::get(*DAG.getContext(), V);
3820 }
3821
3822 auto CPVal = ARMConstantPoolConstant::Create(GVar, Init);
3823 SDValue CPAddr = DAG.getTargetConstantPool(CPVal, PtrVT, Align(4));
3824 if (!AFI->getGlobalsPromotedToConstantPool().count(GVar)) {
3825 AFI->markGlobalAsPromotedToConstantPool(GVar);
3826 AFI->setPromotedConstpoolIncrease(AFI->getPromotedConstpoolIncrease() +
3827 PaddedSize - 4);
3828 }
3829 ++NumConstpoolPromoted;
3830 return DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
3831}
3832
3833bool ARMTargetLowering::isReadOnly(const GlobalValue *GV) const {
3834 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
3835 if (!(GV = GA->getAliaseeObject()))
3836 return false;
3837 if (const auto *V = dyn_cast<GlobalVariable>(GV))
3838 return V->isConstant();
3839 return isa<Function>(GV);
3840}
3841
3842SDValue ARMTargetLowering::LowerGlobalAddress(SDValue Op,
3843 SelectionDAG &DAG) const {
3844 switch (Subtarget->getTargetTriple().getObjectFormat()) {
3845 default: llvm_unreachable("unknown object format")::llvm::llvm_unreachable_internal("unknown object format", "llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3845)
;
3846 case Triple::COFF:
3847 return LowerGlobalAddressWindows(Op, DAG);
3848 case Triple::ELF:
3849 return LowerGlobalAddressELF(Op, DAG);
3850 case Triple::MachO:
3851 return LowerGlobalAddressDarwin(Op, DAG);
3852 }
3853}
3854
3855SDValue ARMTargetLowering::LowerGlobalAddressELF(SDValue Op,
3856 SelectionDAG &DAG) const {
3857 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3858 SDLoc dl(Op);
3859 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
3860 const TargetMachine &TM = getTargetMachine();
3861 bool IsRO = isReadOnly(GV);
3862
3863 // promoteToConstantPool only if not generating XO text section
3864 if (TM.shouldAssumeDSOLocal(*GV->getParent(), GV) && !Subtarget->genExecuteOnly())
3865 if (SDValue V = promoteToConstantPool(this, GV, DAG, PtrVT, dl))
3866 return V;
3867
3868 if (isPositionIndependent()) {
3869 bool UseGOT_PREL = !TM.shouldAssumeDSOLocal(*GV->getParent(), GV);
3870 SDValue G = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
3871 UseGOT_PREL ? ARMII::MO_GOT : 0);
3872 SDValue Result = DAG.getNode(ARMISD::WrapperPIC, dl, PtrVT, G);
3873 if (UseGOT_PREL)
3874 Result =
3875 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Result,
3876 MachinePointerInfo::getGOT(DAG.getMachineFunction()));
3877 return Result;
3878 } else if (Subtarget->isROPI() && IsRO) {
3879 // PC-relative.
3880 SDValue G = DAG.getTargetGlobalAddress(GV, dl, PtrVT);
3881 SDValue Result = DAG.getNode(ARMISD::WrapperPIC, dl, PtrVT, G);
3882 return Result;
3883 } else if (Subtarget->isRWPI() && !IsRO) {
3884 // SB-relative.
3885 SDValue RelAddr;
3886 if (Subtarget->useMovt()) {
3887 ++NumMovwMovt;
3888 SDValue G = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, ARMII::MO_SBREL);
3889 RelAddr = DAG.getNode(ARMISD::Wrapper, dl, PtrVT, G);
3890 } else { // use literal pool for address constant
3891 ARMConstantPoolValue *CPV =
3892 ARMConstantPoolConstant::Create(GV, ARMCP::SBREL);
3893 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, Align(4));
3894 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
3895 RelAddr = DAG.getLoad(
3896 PtrVT, dl, DAG.getEntryNode(), CPAddr,
3897 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
3898 }
3899 SDValue SB = DAG.getCopyFromReg(DAG.getEntryNode(), dl, ARM::R9, PtrVT);
3900 SDValue Result = DAG.getNode(ISD::ADD, dl, PtrVT, SB, RelAddr);
3901 return Result;
3902 }
3903
3904 // If we have T2 ops, we can materialize the address directly via movt/movw
3905 // pair. This is always cheaper.
3906 if (Subtarget->useMovt()) {
3907 ++NumMovwMovt;
3908 // FIXME: Once remat is capable of dealing with instructions with register
3909 // operands, expand this into two nodes.
3910 return DAG.getNode(ARMISD::Wrapper, dl, PtrVT,
3911 DAG.getTargetGlobalAddress(GV, dl, PtrVT));
3912 } else {
3913 SDValue CPAddr = DAG.getTargetConstantPool(GV, PtrVT, Align(4));
3914 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
3915 return DAG.getLoad(
3916 PtrVT, dl, DAG.getEntryNode(), CPAddr,
3917 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
3918 }
3919}
3920
3921SDValue ARMTargetLowering::LowerGlobalAddressDarwin(SDValue Op,
3922 SelectionDAG &DAG) const {
3923 assert(!Subtarget->isROPI() && !Subtarget->isRWPI() &&(static_cast <bool> (!Subtarget->isROPI() &&
!Subtarget->isRWPI() && "ROPI/RWPI not currently supported for Darwin"
) ? void (0) : __assert_fail ("!Subtarget->isROPI() && !Subtarget->isRWPI() && \"ROPI/RWPI not currently supported for Darwin\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 3924, __extension__
__PRETTY_FUNCTION__))
3924 "ROPI/RWPI not currently supported for Darwin")(static_cast <bool> (!Subtarget->isROPI() &&
!Subtarget->isRWPI() && "ROPI/RWPI not currently supported for Darwin"
) ? void (0) : __assert_fail ("!Subtarget->isROPI() && !Subtarget->isRWPI() && \"ROPI/RWPI not currently supported for Darwin\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 3924, __extension__
__PRETTY_FUNCTION__))
;
3925 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3926 SDLoc dl(Op);
3927 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
3928
3929 if (Subtarget->useMovt())
3930 ++NumMovwMovt;
3931
3932 // FIXME: Once remat is capable of dealing with instructions with register
3933 // operands, expand this into multiple nodes
3934 unsigned Wrapper =
3935 isPositionIndependent() ? ARMISD::WrapperPIC : ARMISD::Wrapper;
3936
3937 SDValue G = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, ARMII::MO_NONLAZY);
3938 SDValue Result = DAG.getNode(Wrapper, dl, PtrVT, G);
3939
3940 if (Subtarget->isGVIndirectSymbol(GV))
3941 Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Result,
3942 MachinePointerInfo::getGOT(DAG.getMachineFunction()));
3943 return Result;
3944}
3945
3946SDValue ARMTargetLowering::LowerGlobalAddressWindows(SDValue Op,
3947 SelectionDAG &DAG) const {
3948 assert(Subtarget->isTargetWindows() && "non-Windows COFF is not supported")(static_cast <bool> (Subtarget->isTargetWindows() &&
"non-Windows COFF is not supported") ? void (0) : __assert_fail
("Subtarget->isTargetWindows() && \"non-Windows COFF is not supported\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 3948, __extension__
__PRETTY_FUNCTION__))
;
3949 assert(Subtarget->useMovt() &&(static_cast <bool> (Subtarget->useMovt() &&
"Windows on ARM expects to use movw/movt") ? void (0) : __assert_fail
("Subtarget->useMovt() && \"Windows on ARM expects to use movw/movt\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 3950, __extension__
__PRETTY_FUNCTION__))
3950 "Windows on ARM expects to use movw/movt")(static_cast <bool> (Subtarget->useMovt() &&
"Windows on ARM expects to use movw/movt") ? void (0) : __assert_fail
("Subtarget->useMovt() && \"Windows on ARM expects to use movw/movt\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 3950, __extension__
__PRETTY_FUNCTION__))
;
3951 assert(!Subtarget->isROPI() && !Subtarget->isRWPI() &&(static_cast <bool> (!Subtarget->isROPI() &&
!Subtarget->isRWPI() && "ROPI/RWPI not currently supported for Windows"
) ? void (0) : __assert_fail ("!Subtarget->isROPI() && !Subtarget->isRWPI() && \"ROPI/RWPI not currently supported for Windows\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 3952, __extension__
__PRETTY_FUNCTION__))
3952 "ROPI/RWPI not currently supported for Windows")(static_cast <bool> (!Subtarget->isROPI() &&
!Subtarget->isRWPI() && "ROPI/RWPI not currently supported for Windows"
) ? void (0) : __assert_fail ("!Subtarget->isROPI() && !Subtarget->isRWPI() && \"ROPI/RWPI not currently supported for Windows\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 3952, __extension__
__PRETTY_FUNCTION__))
;
3953
3954 const TargetMachine &TM = getTargetMachine();
3955 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
3956 ARMII::TOF TargetFlags = ARMII::MO_NO_FLAG;
3957 if (GV->hasDLLImportStorageClass())
3958 TargetFlags = ARMII::MO_DLLIMPORT;
3959 else if (!TM.shouldAssumeDSOLocal(*GV->getParent(), GV))
3960 TargetFlags = ARMII::MO_COFFSTUB;
3961 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3962 SDValue Result;
3963 SDLoc DL(Op);
3964
3965 ++NumMovwMovt;
3966
3967 // FIXME: Once remat is capable of dealing with instructions with register
3968 // operands, expand this into two nodes.
3969 Result = DAG.getNode(ARMISD::Wrapper, DL, PtrVT,
3970 DAG.getTargetGlobalAddress(GV, DL, PtrVT, /*offset=*/0,
3971 TargetFlags));
3972 if (TargetFlags & (ARMII::MO_DLLIMPORT | ARMII::MO_COFFSTUB))
3973 Result = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Result,
3974 MachinePointerInfo::getGOT(DAG.getMachineFunction()));
3975 return Result;
3976}
3977
3978SDValue
3979ARMTargetLowering::LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const {
3980 SDLoc dl(Op);
3981 SDValue Val = DAG.getConstant(0, dl, MVT::i32);
3982 return DAG.getNode(ARMISD::EH_SJLJ_SETJMP, dl,
3983 DAG.getVTList(MVT::i32, MVT::Other), Op.getOperand(0),
3984 Op.getOperand(1), Val);
3985}
3986
3987SDValue
3988ARMTargetLowering::LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const {
3989 SDLoc dl(Op);
3990 return DAG.getNode(ARMISD::EH_SJLJ_LONGJMP, dl, MVT::Other, Op.getOperand(0),
3991 Op.getOperand(1), DAG.getConstant(0, dl, MVT::i32));
3992}
3993
3994SDValue ARMTargetLowering::LowerEH_SJLJ_SETUP_DISPATCH(SDValue Op,
3995 SelectionDAG &DAG) const {
3996 SDLoc dl(Op);
3997 return DAG.getNode(ARMISD::EH_SJLJ_SETUP_DISPATCH, dl, MVT::Other,
3998 Op.getOperand(0));
3999}
4000
4001SDValue ARMTargetLowering::LowerINTRINSIC_VOID(
4002 SDValue Op, SelectionDAG &DAG, const ARMSubtarget *Subtarget) const {
4003 unsigned IntNo =
4004 cast<ConstantSDNode>(
4005 Op.getOperand(Op.getOperand(0).getValueType() == MVT::Other))
4006 ->getZExtValue();
4007 switch (IntNo) {
4008 default:
4009 return SDValue(); // Don't custom lower most intrinsics.
4010 case Intrinsic::arm_gnu_eabi_mcount: {
4011 MachineFunction &MF = DAG.getMachineFunction();
4012 EVT PtrVT = getPointerTy(DAG.getDataLayout());
4013 SDLoc dl(Op);
4014 SDValue Chain = Op.getOperand(0);
4015 // call "\01__gnu_mcount_nc"
4016 const ARMBaseRegisterInfo *ARI = Subtarget->getRegisterInfo();
4017 const uint32_t *Mask =
4018 ARI->getCallPreservedMask(DAG.getMachineFunction(), CallingConv::C);
4019 assert(Mask && "Missing call preserved mask for calling convention")(static_cast <bool> (Mask && "Missing call preserved mask for calling convention"
) ? void (0) : __assert_fail ("Mask && \"Missing call preserved mask for calling convention\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 4019, __extension__
__PRETTY_FUNCTION__))
;
4020 // Mark LR an implicit live-in.
4021 unsigned Reg = MF.addLiveIn(ARM::LR, getRegClassFor(MVT::i32));
4022 SDValue ReturnAddress =
4023 DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg, PtrVT);
4024 constexpr EVT ResultTys[] = {MVT::Other, MVT::Glue};
4025 SDValue Callee =
4026 DAG.getTargetExternalSymbol("\01__gnu_mcount_nc", PtrVT, 0);
4027 SDValue RegisterMask = DAG.getRegisterMask(Mask);
4028 if (Subtarget->isThumb())
4029 return SDValue(
4030 DAG.getMachineNode(
4031 ARM::tBL_PUSHLR, dl, ResultTys,
4032 {ReturnAddress, DAG.getTargetConstant(ARMCC::AL, dl, PtrVT),
4033 DAG.getRegister(0, PtrVT), Callee, RegisterMask, Chain}),
4034 0);
4035 return SDValue(
4036 DAG.getMachineNode(ARM::BL_PUSHLR, dl, ResultTys,
4037 {ReturnAddress, Callee, RegisterMask, Chain}),
4038 0);
4039 }
4040 }
4041}
4042
4043SDValue
4044ARMTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG,
4045 const ARMSubtarget *Subtarget) const {
4046 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
4047 SDLoc dl(Op);
4048 switch (IntNo) {
4049 default: return SDValue(); // Don't custom lower most intrinsics.
4050 case Intrinsic::thread_pointer: {
4051 EVT PtrVT = getPointerTy(DAG.getDataLayout());
4052 return DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
4053 }
4054 case Intrinsic::arm_cls: {
4055 const SDValue &Operand = Op.getOperand(1);
4056 const EVT VTy = Op.getValueType();
4057 SDValue SRA =
4058 DAG.getNode(ISD::SRA, dl, VTy, Operand, DAG.getConstant(31, dl, VTy));
4059 SDValue XOR = DAG.getNode(ISD::XOR, dl, VTy, SRA, Operand);
4060 SDValue SHL =
4061 DAG.getNode(ISD::SHL, dl, VTy, XOR, DAG.getConstant(1, dl, VTy));
4062 SDValue OR =
4063 DAG.getNode(ISD::OR, dl, VTy, SHL, DAG.getConstant(1, dl, VTy));
4064 SDValue Result = DAG.getNode(ISD::CTLZ, dl, VTy, OR);
4065 return Result;
4066 }
4067 case Intrinsic::arm_cls64: {
4068 // cls(x) = if cls(hi(x)) != 31 then cls(hi(x))
4069 // else 31 + clz(if hi(x) == 0 then lo(x) else not(lo(x)))
4070 const SDValue &Operand = Op.getOperand(1);
4071 const EVT VTy = Op.getValueType();
4072
4073 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VTy, Operand,
4074 DAG.getConstant(1, dl, VTy));
4075 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VTy, Operand,
4076 DAG.getConstant(0, dl, VTy));
4077 SDValue Constant0 = DAG.getConstant(0, dl, VTy);
4078 SDValue Constant1 = DAG.getConstant(1, dl, VTy);
4079 SDValue Constant31 = DAG.getConstant(31, dl, VTy);
4080 SDValue SRAHi = DAG.getNode(ISD::SRA, dl, VTy, Hi, Constant31);
4081 SDValue XORHi = DAG.getNode(ISD::XOR, dl, VTy, SRAHi, Hi);
4082 SDValue SHLHi = DAG.getNode(ISD::SHL, dl, VTy, XORHi, Constant1);
4083 SDValue ORHi = DAG.getNode(ISD::OR, dl, VTy, SHLHi, Constant1);
4084 SDValue CLSHi = DAG.getNode(ISD::CTLZ, dl, VTy, ORHi);
4085 SDValue CheckLo =
4086 DAG.getSetCC(dl, MVT::i1, CLSHi, Constant31, ISD::CondCode::SETEQ);
4087 SDValue HiIsZero =
4088 DAG.getSetCC(dl, MVT::i1, Hi, Constant0, ISD::CondCode::SETEQ);
4089 SDValue AdjustedLo =
4090 DAG.getSelect(dl, VTy, HiIsZero, Lo, DAG.getNOT(dl, Lo, VTy));
4091 SDValue CLZAdjustedLo = DAG.getNode(ISD::CTLZ, dl, VTy, AdjustedLo);
4092 SDValue Result =
4093 DAG.getSelect(dl, VTy, CheckLo,
4094 DAG.getNode(ISD::ADD, dl, VTy, CLZAdjustedLo, Constant31), CLSHi);
4095 return Result;
4096 }
4097 case Intrinsic::eh_sjlj_lsda: {
4098 MachineFunction &MF = DAG.getMachineFunction();
4099 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
4100 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
4101 EVT PtrVT = getPointerTy(DAG.getDataLayout());
4102 SDValue CPAddr;
4103 bool IsPositionIndependent = isPositionIndependent();
4104 unsigned PCAdj = IsPositionIndependent ? (Subtarget->isThumb() ? 4 : 8) : 0;
4105 ARMConstantPoolValue *CPV =
4106 ARMConstantPoolConstant::Create(&MF.getFunction(), ARMPCLabelIndex,
4107 ARMCP::CPLSDA, PCAdj);
4108 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, Align(4));
4109 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
4110 SDValue Result = DAG.getLoad(
4111 PtrVT, dl, DAG.getEntryNode(), CPAddr,
4112 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
4113
4114 if (IsPositionIndependent) {
4115 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, dl, MVT::i32);
4116 Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
4117 }
4118 return Result;
4119 }
4120 case Intrinsic::arm_neon_vabs:
4121 return DAG.getNode(ISD::ABS, SDLoc(Op), Op.getValueType(),
4122 Op.getOperand(1));
4123 case Intrinsic::arm_neon_vmulls:
4124 case Intrinsic::arm_neon_vmullu: {
4125 unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vmulls)
4126 ? ARMISD::VMULLs : ARMISD::VMULLu;
4127 return DAG.getNode(NewOpc, SDLoc(Op), Op.getValueType(),
4128 Op.getOperand(1), Op.getOperand(2));
4129 }
4130 case Intrinsic::arm_neon_vminnm:
4131 case Intrinsic::arm_neon_vmaxnm: {
4132 unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vminnm)
4133 ? ISD::FMINNUM : ISD::FMAXNUM;
4134 return DAG.getNode(NewOpc, SDLoc(Op), Op.getValueType(),
4135 Op.getOperand(1), Op.getOperand(2));
4136 }
4137 case Intrinsic::arm_neon_vminu:
4138 case Intrinsic::arm_neon_vmaxu: {
4139 if (Op.getValueType().isFloatingPoint())
4140 return SDValue();
4141 unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vminu)
4142 ? ISD::UMIN : ISD::UMAX;
4143 return DAG.getNode(NewOpc, SDLoc(Op), Op.getValueType(),
4144 Op.getOperand(1), Op.getOperand(2));
4145 }
4146 case Intrinsic::arm_neon_vmins:
4147 case Intrinsic::arm_neon_vmaxs: {
4148 // v{min,max}s is overloaded between signed integers and floats.
4149 if (!Op.getValueType().isFloatingPoint()) {
4150 unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vmins)
4151 ? ISD::SMIN : ISD::SMAX;
4152 return DAG.getNode(NewOpc, SDLoc(Op), Op.getValueType(),
4153 Op.getOperand(1), Op.getOperand(2));
4154 }
4155 unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vmins)
4156 ? ISD::FMINIMUM : ISD::FMAXIMUM;
4157 return DAG.getNode(NewOpc, SDLoc(Op), Op.getValueType(),
4158 Op.getOperand(1), Op.getOperand(2));
4159 }
4160 case Intrinsic::arm_neon_vtbl1:
4161 return DAG.getNode(ARMISD::VTBL1, SDLoc(Op), Op.getValueType(),
4162 Op.getOperand(1), Op.getOperand(2));
4163 case Intrinsic::arm_neon_vtbl2:
4164 return DAG.getNode(ARMISD::VTBL2, SDLoc(Op), Op.getValueType(),
4165 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
4166 case Intrinsic::arm_mve_pred_i2v:
4167 case Intrinsic::arm_mve_pred_v2i:
4168 return DAG.getNode(ARMISD::PREDICATE_CAST, SDLoc(Op), Op.getValueType(),
4169 Op.getOperand(1));
4170 case Intrinsic::arm_mve_vreinterpretq:
4171 return DAG.getNode(ARMISD::VECTOR_REG_CAST, SDLoc(Op), Op.getValueType(),
4172 Op.getOperand(1));
4173 case Intrinsic::arm_mve_lsll:
4174 return DAG.getNode(ARMISD::LSLL, SDLoc(Op), Op->getVTList(),
4175 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
4176 case Intrinsic::arm_mve_asrl:
4177 return DAG.getNode(ARMISD::ASRL, SDLoc(Op), Op->getVTList(),
4178 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
4179 }
4180}
4181
4182static SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG,
4183 const ARMSubtarget *Subtarget) {
4184 SDLoc dl(Op);
4185 ConstantSDNode *SSIDNode = cast<ConstantSDNode>(Op.getOperand(2));
4186 auto SSID = static_cast<SyncScope::ID>(SSIDNode->getZExtValue());
4187 if (SSID == SyncScope::SingleThread)
4188 return Op;
4189
4190 if (!Subtarget->hasDataBarrier()) {
4191 // Some ARMv6 cpus can support data barriers with an mcr instruction.
4192 // Thumb1 and pre-v6 ARM mode use a libcall instead and should never get
4193 // here.
4194 assert(Subtarget->hasV6Ops() && !Subtarget->isThumb() &&(static_cast <bool> (Subtarget->hasV6Ops() &&
!Subtarget->isThumb() && "Unexpected ISD::ATOMIC_FENCE encountered. Should be libcall!"
) ? void (0) : __assert_fail ("Subtarget->hasV6Ops() && !Subtarget->isThumb() && \"Unexpected ISD::ATOMIC_FENCE encountered. Should be libcall!\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 4195, __extension__
__PRETTY_FUNCTION__))
4195 "Unexpected ISD::ATOMIC_FENCE encountered. Should be libcall!")(static_cast <bool> (Subtarget->hasV6Ops() &&
!Subtarget->isThumb() && "Unexpected ISD::ATOMIC_FENCE encountered. Should be libcall!"
) ? void (0) : __assert_fail ("Subtarget->hasV6Ops() && !Subtarget->isThumb() && \"Unexpected ISD::ATOMIC_FENCE encountered. Should be libcall!\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 4195, __extension__
__PRETTY_FUNCTION__))
;
4196 return DAG.getNode(ARMISD::MEMBARRIER_MCR, dl, MVT::Other, Op.getOperand(0),
4197 DAG.getConstant(0, dl, MVT::i32));
4198 }
4199
4200 ConstantSDNode *OrdN = cast<ConstantSDNode>(Op.getOperand(1));
4201 AtomicOrdering Ord = static_cast<AtomicOrdering>(OrdN->getZExtValue());
4202 ARM_MB::MemBOpt Domain = ARM_MB::ISH;
4203 if (Subtarget->isMClass()) {
4204 // Only a full system barrier exists in the M-class architectures.
4205 Domain = ARM_MB::SY;
4206 } else if (Subtarget->preferISHSTBarriers() &&
4207 Ord == AtomicOrdering::Release) {
4208 // Swift happens to implement ISHST barriers in a way that's compatible with
4209 // Release semantics but weaker than ISH so we'd be fools not to use
4210 // it. Beware: other processors probably don't!
4211 Domain = ARM_MB::ISHST;
4212 }
4213
4214 return DAG.getNode(ISD::INTRINSIC_VOID, dl, MVT::Other, Op.getOperand(0),
4215 DAG.getConstant(Intrinsic::arm_dmb, dl, MVT::i32),
4216 DAG.getConstant(Domain, dl, MVT::i32));
4217}
4218
4219static SDValue LowerPREFETCH(SDValue Op, SelectionDAG &DAG,
4220 const ARMSubtarget *Subtarget) {
4221 // ARM pre v5TE and Thumb1 does not have preload instructions.
4222 if (!(Subtarget->isThumb2() ||
4223 (!Subtarget->isThumb1Only() && Subtarget->hasV5TEOps())))
4224 // Just preserve the chain.
4225 return Op.getOperand(0);
4226
4227 SDLoc dl(Op);
4228 unsigned isRead = ~cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue() & 1;
4229 if (!isRead &&
4230 (!Subtarget->hasV7Ops() || !Subtarget->hasMPExtension()))
4231 // ARMv7 with MP extension has PLDW.
4232 return Op.getOperand(0);
4233
4234 unsigned isData = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue();
4235 if (Subtarget->isThumb()) {
4236 // Invert the bits.
4237 isRead = ~isRead & 1;
4238 isData = ~isData & 1;
4239 }
4240
4241 return DAG.getNode(ARMISD::PRELOAD, dl, MVT::Other, Op.getOperand(0),
4242 Op.getOperand(1), DAG.getConstant(isRead, dl, MVT::i32),
4243 DAG.getConstant(isData, dl, MVT::i32));
4244}
4245
4246static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) {
4247 MachineFunction &MF = DAG.getMachineFunction();
4248 ARMFunctionInfo *FuncInfo = MF.getInfo<ARMFunctionInfo>();
4249
4250 // vastart just stores the address of the VarArgsFrameIndex slot into the
4251 // memory location argument.
4252 SDLoc dl(Op);
4253 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
4254 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
4255 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
4256 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1),
4257 MachinePointerInfo(SV));
4258}
4259
4260SDValue ARMTargetLowering::GetF64FormalArgument(CCValAssign &VA,
4261 CCValAssign &NextVA,
4262 SDValue &Root,
4263 SelectionDAG &DAG,
4264 const SDLoc &dl) const {
4265 MachineFunction &MF = DAG.getMachineFunction();
4266 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
4267
4268 const TargetRegisterClass *RC;
4269 if (AFI->isThumb1OnlyFunction())
4270 RC = &ARM::tGPRRegClass;
4271 else
4272 RC = &ARM::GPRRegClass;
4273
4274 // Transform the arguments stored in physical registers into virtual ones.
4275 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
4276 SDValue ArgValue = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
4277
4278 SDValue ArgValue2;
4279 if (NextVA.isMemLoc()) {
4280 MachineFrameInfo &MFI = MF.getFrameInfo();
4281 int FI = MFI.CreateFixedObject(4, NextVA.getLocMemOffset(), true);
4282
4283 // Create load node to retrieve arguments from the stack.
4284 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
4285 ArgValue2 = DAG.getLoad(
4286 MVT::i32, dl, Root, FIN,
4287 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI));
4288 } else {
4289 Reg = MF.addLiveIn(NextVA.getLocReg(), RC);
4290 ArgValue2 = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
4291 }
4292 if (!Subtarget->isLittle())
4293 std::swap (ArgValue, ArgValue2);
4294 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, ArgValue, ArgValue2);
4295}
4296
4297// The remaining GPRs hold either the beginning of variable-argument
4298// data, or the beginning of an aggregate passed by value (usually
4299// byval). Either way, we allocate stack slots adjacent to the data
4300// provided by our caller, and store the unallocated registers there.
4301// If this is a variadic function, the va_list pointer will begin with
4302// these values; otherwise, this reassembles a (byval) structure that
4303// was split between registers and memory.
4304// Return: The frame index registers were stored into.
4305int ARMTargetLowering::StoreByValRegs(CCState &CCInfo, SelectionDAG &DAG,
4306 const SDLoc &dl, SDValue &Chain,
4307 const Value *OrigArg,
4308 unsigned InRegsParamRecordIdx,
4309 int ArgOffset, unsigned ArgSize) const {
4310 // Currently, two use-cases possible:
4311 // Case #1. Non-var-args function, and we meet first byval parameter.
4312 // Setup first unallocated register as first byval register;
4313 // eat all remained registers
4314 // (these two actions are performed by HandleByVal method).
4315 // Then, here, we initialize stack frame with
4316 // "store-reg" instructions.
4317 // Case #2. Var-args function, that doesn't contain byval parameters.
4318 // The same: eat all remained unallocated registers,
4319 // initialize stack frame.
4320
4321 MachineFunction &MF = DAG.getMachineFunction();
4322 MachineFrameInfo &MFI = MF.getFrameInfo();
4323 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
4324 unsigned RBegin, REnd;
4325 if (InRegsParamRecordIdx < CCInfo.getInRegsParamsCount()) {
4326 CCInfo.getInRegsParamInfo(InRegsParamRecordIdx, RBegin, REnd);
4327 } else {
4328 unsigned RBeginIdx = CCInfo.getFirstUnallocated(GPRArgRegs);
4329 RBegin = RBeginIdx == 4 ? (unsigned)ARM::R4 : GPRArgRegs[RBeginIdx];
4330 REnd = ARM::R4;
4331 }
4332
4333 if (REnd != RBegin)
4334 ArgOffset = -4 * (ARM::R4 - RBegin);
4335
4336 auto PtrVT = getPointerTy(DAG.getDataLayout());
4337 int FrameIndex = MFI.CreateFixedObject(ArgSize, ArgOffset, false);
4338 SDValue FIN = DAG.getFrameIndex(FrameIndex, PtrVT);
4339
4340 SmallVector<SDValue, 4> MemOps;
4341 const TargetRegisterClass *RC =
4342 AFI->isThumb1OnlyFunction() ? &ARM::tGPRRegClass : &ARM::GPRRegClass;
4343
4344 for (unsigned Reg = RBegin, i = 0; Reg < REnd; ++Reg, ++i) {
4345 unsigned VReg = MF.addLiveIn(Reg, RC);
4346 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
4347 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
4348 MachinePointerInfo(OrigArg, 4 * i));
4349 MemOps.push_back(Store);
4350 FIN = DAG.getNode(ISD::ADD, dl, PtrVT, FIN, DAG.getConstant(4, dl, PtrVT));
4351 }
4352
4353 if (!MemOps.empty())
4354 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
4355 return FrameIndex;
4356}
4357
4358// Setup stack frame, the va_list pointer will start from.
4359void ARMTargetLowering::VarArgStyleRegisters(CCState &CCInfo, SelectionDAG &DAG,
4360 const SDLoc &dl, SDValue &Chain,
4361 unsigned ArgOffset,
4362 unsigned TotalArgRegsSaveSize,
4363 bool ForceMutable) const {
4364 MachineFunction &MF = DAG.getMachineFunction();
4365 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
4366
4367 // Try to store any remaining integer argument regs
4368 // to their spots on the stack so that they may be loaded by dereferencing
4369 // the result of va_next.
4370 // If there is no regs to be stored, just point address after last
4371 // argument passed via stack.
4372 int FrameIndex = StoreByValRegs(CCInfo, DAG, dl, Chain, nullptr,
4373 CCInfo.getInRegsParamsCount(),
4374 CCInfo.getNextStackOffset(),
4375 std::max(4U, TotalArgRegsSaveSize));
4376 AFI->setVarArgsFrameIndex(FrameIndex);
4377}
4378
4379bool ARMTargetLowering::splitValueIntoRegisterParts(
4380 SelectionDAG &DAG, const SDLoc &DL, SDValue Val, SDValue *Parts,
4381 unsigned NumParts, MVT PartVT, Optional<CallingConv::ID> CC) const {
4382 bool IsABIRegCopy = CC.hasValue();
4383 EVT ValueVT = Val.getValueType();
4384 if (IsABIRegCopy && (ValueVT == MVT::f16 || ValueVT == MVT::bf16) &&
4385 PartVT == MVT::f32) {
4386 unsigned ValueBits = ValueVT.getSizeInBits();
4387 unsigned PartBits = PartVT.getSizeInBits();
4388 Val = DAG.getNode(ISD::BITCAST, DL, MVT::getIntegerVT(ValueBits), Val);
4389 Val = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::getIntegerVT(PartBits), Val);
4390 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
4391 Parts[0] = Val;
4392 return true;
4393 }
4394 return false;
4395}
4396
4397SDValue ARMTargetLowering::joinRegisterPartsIntoValue(
4398 SelectionDAG &DAG, const SDLoc &DL, const SDValue *Parts, unsigned NumParts,
4399 MVT PartVT, EVT ValueVT, Optional<CallingConv::ID> CC) const {
4400 bool IsABIRegCopy = CC.hasValue();
4401 if (IsABIRegCopy && (ValueVT == MVT::f16 || ValueVT == MVT::bf16) &&
4402 PartVT == MVT::f32) {
4403 unsigned ValueBits = ValueVT.getSizeInBits();
4404 unsigned PartBits = PartVT.getSizeInBits();
4405 SDValue Val = Parts[0];
4406
4407 Val = DAG.getNode(ISD::BITCAST, DL, MVT::getIntegerVT(PartBits), Val);
4408 Val = DAG.getNode(ISD::TRUNCATE, DL, MVT::getIntegerVT(ValueBits), Val);
4409 Val = DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
4410 return Val;
4411 }
4412 return SDValue();
4413}
4414
4415SDValue ARMTargetLowering::LowerFormalArguments(
4416 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
4417 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
4418 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
4419 MachineFunction &MF = DAG.getMachineFunction();
4420 MachineFrameInfo &MFI = MF.getFrameInfo();
4421
4422 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
4423
4424 // Assign locations to all of the incoming arguments.
4425 SmallVector<CCValAssign, 16> ArgLocs;
4426 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
4427 *DAG.getContext());
4428 CCInfo.AnalyzeFormalArguments(Ins, CCAssignFnForCall(CallConv, isVarArg));
4429
4430 SmallVector<SDValue, 16> ArgValues;
4431 SDValue ArgValue;
4432 Function::const_arg_iterator CurOrigArg = MF.getFunction().arg_begin();
4433 unsigned CurArgIdx = 0;
4434
4435 // Initially ArgRegsSaveSize is zero.
4436 // Then we increase this value each time we meet byval parameter.
4437 // We also increase this value in case of varargs function.
4438 AFI->setArgRegsSaveSize(0);
4439
4440 // Calculate the amount of stack space that we need to allocate to store
4441 // byval and variadic arguments that are passed in registers.
4442 // We need to know this before we allocate the first byval or variadic
4443 // argument, as they will be allocated a stack slot below the CFA (Canonical
4444 // Frame Address, the stack pointer at entry to the function).
4445 unsigned ArgRegBegin = ARM::R4;
4446 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
4447 if (CCInfo.getInRegsParamsProcessed() >= CCInfo.getInRegsParamsCount())
4448 break;
4449
4450 CCValAssign &VA = ArgLocs[i];
4451 unsigned Index = VA.getValNo();
4452 ISD::ArgFlagsTy Flags = Ins[Index].Flags;
4453 if (!Flags.isByVal())
4454 continue;
4455
4456 assert(VA.isMemLoc() && "unexpected byval pointer in reg")(static_cast <bool> (VA.isMemLoc() && "unexpected byval pointer in reg"
) ? void (0) : __assert_fail ("VA.isMemLoc() && \"unexpected byval pointer in reg\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 4456, __extension__
__PRETTY_FUNCTION__))
;
4457 unsigned RBegin, REnd;
4458 CCInfo.getInRegsParamInfo(CCInfo.getInRegsParamsProcessed(), RBegin, REnd);
4459 ArgRegBegin = std::min(ArgRegBegin, RBegin);
4460
4461 CCInfo.nextInRegsParam();
4462 }
4463 CCInfo.rewindByValRegsInfo();
4464
4465 int lastInsIndex = -1;
4466 if (isVarArg && MFI.hasVAStart()) {
4467 unsigned RegIdx = CCInfo.getFirstUnallocated(GPRArgRegs);
4468 if (RegIdx != array_lengthof(GPRArgRegs))
4469 ArgRegBegin = std::min(ArgRegBegin, (unsigned)GPRArgRegs[RegIdx]);
4470 }
4471
4472 unsigned TotalArgRegsSaveSize = 4 * (ARM::R4 - ArgRegBegin);
4473 AFI->setArgRegsSaveSize(TotalArgRegsSaveSize);
4474 auto PtrVT = getPointerTy(DAG.getDataLayout());
4475
4476 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
4477 CCValAssign &VA = ArgLocs[i];
4478 if (Ins[VA.getValNo()].isOrigArg()) {
4479 std::advance(CurOrigArg,
4480 Ins[VA.getValNo()].getOrigArgIndex() - CurArgIdx);
4481 CurArgIdx = Ins[VA.getValNo()].getOrigArgIndex();
4482 }
4483 // Arguments stored in registers.
4484 if (VA.isRegLoc()) {
4485 EVT RegVT = VA.getLocVT();
4486
4487 if (VA.needsCustom() && VA.getLocVT() == MVT::v2f64) {
4488 // f64 and vector types are split up into multiple registers or
4489 // combinations of registers and stack slots.
4490 SDValue ArgValue1 =
4491 GetF64FormalArgument(VA, ArgLocs[++i], Chain, DAG, dl);
4492 VA = ArgLocs[++i]; // skip ahead to next loc
4493 SDValue ArgValue2;
4494 if (VA.isMemLoc()) {
4495 int FI = MFI.CreateFixedObject(8, VA.getLocMemOffset(), true);
4496 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
4497 ArgValue2 = DAG.getLoad(
4498 MVT::f64, dl, Chain, FIN,
4499 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI));
4500 } else {
4501 ArgValue2 = GetF64FormalArgument(VA, ArgLocs[++i], Chain, DAG, dl);
4502 }
4503 ArgValue = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
4504 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, ArgValue,
4505 ArgValue1, DAG.getIntPtrConstant(0, dl));
4506 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, ArgValue,
4507 ArgValue2, DAG.getIntPtrConstant(1, dl));
4508 } else if (VA.needsCustom() && VA.getLocVT() == MVT::f64) {
4509 ArgValue = GetF64FormalArgument(VA, ArgLocs[++i], Chain, DAG, dl);
4510 } else {
4511 const TargetRegisterClass *RC;
4512
4513 if (RegVT == MVT::f16 || RegVT == MVT::bf16)
4514 RC = &ARM::HPRRegClass;
4515 else if (RegVT == MVT::f32)
4516 RC = &ARM::SPRRegClass;
4517 else if (RegVT == MVT::f64 || RegVT == MVT::v4f16 ||
4518 RegVT == MVT::v4bf16)
4519 RC = &ARM::DPRRegClass;
4520 else if (RegVT == MVT::v2f64 || RegVT == MVT::v8f16 ||
4521 RegVT == MVT::v8bf16)
4522 RC = &ARM::QPRRegClass;
4523 else if (RegVT == MVT::i32)
4524 RC = AFI->isThumb1OnlyFunction() ? &ARM::tGPRRegClass
4525 : &ARM::GPRRegClass;
4526 else
4527 llvm_unreachable("RegVT not supported by FORMAL_ARGUMENTS Lowering")::llvm::llvm_unreachable_internal("RegVT not supported by FORMAL_ARGUMENTS Lowering"
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 4527)
;
4528
4529 // Transform the arguments in physical registers into virtual ones.
4530 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
4531 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
4532
4533 // If this value is passed in r0 and has the returned attribute (e.g.
4534 // C++ 'structors), record this fact for later use.
4535 if (VA.getLocReg() == ARM::R0 && Ins[VA.getValNo()].Flags.isReturned()) {
4536 AFI->setPreservesR0();
4537 }
4538 }
4539
4540 // If this is an 8 or 16-bit value, it is really passed promoted
4541 // to 32 bits. Insert an assert[sz]ext to capture this, then
4542 // truncate to the right size.
4543 switch (VA.getLocInfo()) {
4544 default: llvm_unreachable("Unknown loc info!")::llvm::llvm_unreachable_internal("Unknown loc info!", "llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 4544)
;
4545 case CCValAssign::Full: break;
4546 case CCValAssign::BCvt:
4547 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
4548 break;
4549 case CCValAssign::SExt:
4550 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
4551 DAG.getValueType(VA.getValVT()));
4552 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
4553 break;
4554 case CCValAssign::ZExt:
4555 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
4556 DAG.getValueType(VA.getValVT()));
4557 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
4558 break;
4559 }
4560
4561 // f16 arguments have their size extended to 4 bytes and passed as if they
4562 // had been copied to the LSBs of a 32-bit register.
4563 // For that, it's passed extended to i32 (soft ABI) or to f32 (hard ABI)
4564 if (VA.needsCustom() &&
4565 (VA.getValVT() == MVT::f16 || VA.getValVT() == MVT::bf16))
4566 ArgValue = MoveToHPR(dl, DAG, VA.getLocVT(), VA.getValVT(), ArgValue);
4567
4568 InVals.push_back(ArgValue);
4569 } else { // VA.isRegLoc()
4570 // Only arguments passed on the stack should make it here.
4571 assert(VA.isMemLoc())(static_cast <bool> (VA.isMemLoc()) ? void (0) : __assert_fail
("VA.isMemLoc()", "llvm/lib/Target/ARM/ARMISelLowering.cpp",
4571, __extension__ __PRETTY_FUNCTION__))
;
4572 assert(VA.getValVT() != MVT::i64 && "i64 should already be lowered")(static_cast <bool> (VA.getValVT() != MVT::i64 &&
"i64 should already be lowered") ? void (0) : __assert_fail (
"VA.getValVT() != MVT::i64 && \"i64 should already be lowered\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 4572, __extension__
__PRETTY_FUNCTION__))
;
4573
4574 int index = VA.getValNo();
4575
4576 // Some Ins[] entries become multiple ArgLoc[] entries.
4577 // Process them only once.
4578 if (index != lastInsIndex)
4579 {
4580 ISD::ArgFlagsTy Flags = Ins[index].Flags;
4581 // FIXME: For now, all byval parameter objects are marked mutable.
4582 // This can be changed with more analysis.
4583 // In case of tail call optimization mark all arguments mutable.
4584 // Since they could be overwritten by lowering of arguments in case of
4585 // a tail call.
4586 if (Flags.isByVal()) {
4587 assert(Ins[index].isOrigArg() &&(static_cast <bool> (Ins[index].isOrigArg() && "Byval arguments cannot be implicit"
) ? void (0) : __assert_fail ("Ins[index].isOrigArg() && \"Byval arguments cannot be implicit\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 4588, __extension__
__PRETTY_FUNCTION__))
4588 "Byval arguments cannot be implicit")(static_cast <bool> (Ins[index].isOrigArg() && "Byval arguments cannot be implicit"
) ? void (0) : __assert_fail ("Ins[index].isOrigArg() && \"Byval arguments cannot be implicit\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 4588, __extension__
__PRETTY_FUNCTION__))
;
4589 unsigned CurByValIndex = CCInfo.getInRegsParamsProcessed();
4590
4591 int FrameIndex = StoreByValRegs(
4592 CCInfo, DAG, dl, Chain, &*CurOrigArg, CurByValIndex,
4593 VA.getLocMemOffset(), Flags.getByValSize());
4594 InVals.push_back(DAG.getFrameIndex(FrameIndex, PtrVT));
4595 CCInfo.nextInRegsParam();
4596 } else {
4597 unsigned FIOffset = VA.getLocMemOffset();
4598 int FI = MFI.CreateFixedObject(VA.getLocVT().getSizeInBits()/8,
4599 FIOffset, true);
4600
4601 // Create load nodes to retrieve arguments from the stack.
4602 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
4603 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
4604 MachinePointerInfo::getFixedStack(
4605 DAG.getMachineFunction(), FI)));
4606 }
4607 lastInsIndex = index;
4608 }
4609 }
4610 }
4611
4612 // varargs
4613 if (isVarArg && MFI.hasVAStart()) {
4614 VarArgStyleRegisters(CCInfo, DAG, dl, Chain, CCInfo.getNextStackOffset(),
4615 TotalArgRegsSaveSize);
4616 if (AFI->isCmseNSEntryFunction()) {
4617 DiagnosticInfoUnsupported Diag(
4618 DAG.getMachineFunction().getFunction(),
4619 "secure entry function must not be variadic", dl.getDebugLoc());
4620 DAG.getContext()->diagnose(Diag);
4621 }
4622 }
4623
4624 unsigned StackArgSize = CCInfo.getNextStackOffset();
4625 bool TailCallOpt = MF.getTarget().Options.GuaranteedTailCallOpt;
4626 if (canGuaranteeTCO(CallConv, TailCallOpt)) {
4627 // The only way to guarantee a tail call is if the callee restores its
4628 // argument area, but it must also keep the stack aligned when doing so.
4629 const DataLayout &DL = DAG.getDataLayout();
4630 StackArgSize = alignTo(StackArgSize, DL.getStackAlignment());
4631
4632 AFI->setArgumentStackToRestore(StackArgSize);
4633 }
4634 AFI->setArgumentStackSize(StackArgSize);
4635
4636 if (CCInfo.getNextStackOffset() > 0 && AFI->isCmseNSEntryFunction()) {
4637 DiagnosticInfoUnsupported Diag(
4638 DAG.getMachineFunction().getFunction(),
4639 "secure entry function requires arguments on stack", dl.getDebugLoc());
4640 DAG.getContext()->diagnose(Diag);
4641 }
4642
4643 return Chain;
4644}
4645
4646/// isFloatingPointZero - Return true if this is +0.0.
4647static bool isFloatingPointZero(SDValue Op) {
4648 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
3
Calling 'dyn_cast<llvm::ConstantFPSDNode, llvm::SDValue>'
18
Returning from 'dyn_cast<llvm::ConstantFPSDNode, llvm::SDValue>'
19
Assuming 'CFP' is null
4649 return CFP->getValueAPF().isPosZero();
4650 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
4651 // Maybe this has already been legalized into the constant pool?
4652 if (Op.getOperand(1).getOpcode() == ARMISD::Wrapper) {
20
Calling 'SDValue::getOperand'
4653 SDValue WrapperOp = Op.getOperand(1).getOperand(0);
4654 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(WrapperOp))
4655 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
4656 return CFP->getValueAPF().isPosZero();
4657 }
4658 } else if (Op->getOpcode() == ISD::BITCAST &&
4659 Op->getValueType(0) == MVT::f64) {
4660 // Handle (ISD::BITCAST (ARMISD::VMOVIMM (ISD::TargetConstant 0)) MVT::f64)
4661 // created by LowerConstantFP().
4662 SDValue BitcastOp = Op->getOperand(0);
4663 if (BitcastOp->getOpcode() == ARMISD::VMOVIMM &&
4664 isNullConstant(BitcastOp->getOperand(0)))
4665 return true;
4666 }
4667 return false;
4668}
4669
4670/// Returns appropriate ARM CMP (cmp) and corresponding condition code for
4671/// the given operands.
4672SDValue ARMTargetLowering::getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
4673 SDValue &ARMcc, SelectionDAG &DAG,
4674 const SDLoc &dl) const {
4675 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.getNode())) {
4676 unsigned C = RHSC->getZExtValue();
4677 if (!isLegalICmpImmediate((int32_t)C)) {
4678 // Constant does not fit, try adjusting it by one.
4679 switch (CC) {
4680 default: break;
4681 case ISD::SETLT:
4682 case ISD::SETGE:
4683 if (C != 0x80000000 && isLegalICmpImmediate(C-1)) {
4684 CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT;
4685 RHS = DAG.getConstant(C - 1, dl, MVT::i32);
4686 }
4687 break;
4688 case ISD::SETULT:
4689 case ISD::SETUGE:
4690 if (C != 0 && isLegalICmpImmediate(C-1)) {
4691 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT;
4692 RHS = DAG.getConstant(C - 1, dl, MVT::i32);
4693 }
4694 break;
4695 case ISD::SETLE:
4696 case ISD::SETGT:
4697 if (C != 0x7fffffff && isLegalICmpImmediate(C+1)) {
4698 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE;
4699 RHS = DAG.getConstant(C + 1, dl, MVT::i32);
4700 }
4701 break;
4702 case ISD::SETULE:
4703 case ISD::SETUGT:
4704 if (C != 0xffffffff && isLegalICmpImmediate(C+1)) {
4705 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
4706 RHS = DAG.getConstant(C + 1, dl, MVT::i32);
4707 }
4708 break;
4709 }
4710 }
4711 } else if ((ARM_AM::getShiftOpcForNode(LHS.getOpcode()) != ARM_AM::no_shift) &&
4712 (ARM_AM::getShiftOpcForNode(RHS.getOpcode()) == ARM_AM::no_shift)) {
4713 // In ARM and Thumb-2, the compare instructions can shift their second
4714 // operand.
4715 CC = ISD::getSetCCSwappedOperands(CC);
4716 std::swap(LHS, RHS);
4717 }
4718
4719 // Thumb1 has very limited immediate modes, so turning an "and" into a
4720 // shift can save multiple instructions.
4721 //
4722 // If we have (x & C1), and C1 is an appropriate mask, we can transform it
4723 // into "((x << n) >> n)". But that isn't necessarily profitable on its
4724 // own. If it's the operand to an unsigned comparison with an immediate,
4725 // we can eliminate one of the shifts: we transform
4726 // "((x << n) >> n) == C2" to "(x << n) == (C2 << n)".
4727 //
4728 // We avoid transforming cases which aren't profitable due to encoding
4729 // details:
4730 //
4731 // 1. C2 fits into the immediate field of a cmp, and the transformed version
4732 // would not; in that case, we're essentially trading one immediate load for
4733 // another.
4734 // 2. C1 is 255 or 65535, so we can use uxtb or uxth.
4735 // 3. C2 is zero; we have other code for this special case.
4736 //
4737 // FIXME: Figure out profitability for Thumb2; we usually can't save an
4738 // instruction, since the AND is always one instruction anyway, but we could
4739 // use narrow instructions in some cases.
4740 if (Subtarget->isThumb1Only() && LHS->getOpcode() == ISD::AND &&
4741 LHS->hasOneUse() && isa<ConstantSDNode>(LHS.getOperand(1)) &&
4742 LHS.getValueType() == MVT::i32 && isa<ConstantSDNode>(RHS) &&
4743 !isSignedIntSetCC(CC)) {
4744 unsigned Mask = cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue();
4745 auto *RHSC = cast<ConstantSDNode>(RHS.getNode());
4746 uint64_t RHSV = RHSC->getZExtValue();
4747 if (isMask_32(Mask) && (RHSV & ~Mask) == 0 && Mask != 255 && Mask != 65535) {
4748 unsigned ShiftBits = countLeadingZeros(Mask);
4749 if (RHSV && (RHSV > 255 || (RHSV << ShiftBits) <= 255)) {
4750 SDValue ShiftAmt = DAG.getConstant(ShiftBits, dl, MVT::i32);
4751 LHS = DAG.getNode(ISD::SHL, dl, MVT::i32, LHS.getOperand(0), ShiftAmt);
4752 RHS = DAG.getConstant(RHSV << ShiftBits, dl, MVT::i32);
4753 }
4754 }
4755 }
4756
4757 // The specific comparison "(x<<c) > 0x80000000U" can be optimized to a
4758 // single "lsls x, c+1". The shift sets the "C" and "Z" flags the same
4759 // way a cmp would.
4760 // FIXME: Add support for ARM/Thumb2; this would need isel patterns, and
4761 // some tweaks to the heuristics for the previous and->shift transform.
4762 // FIXME: Optimize cases where the LHS isn't a shift.
4763 if (Subtarget->isThumb1Only() && LHS->getOpcode() == ISD::SHL &&
4764 isa<ConstantSDNode>(RHS) &&
4765 cast<ConstantSDNode>(RHS)->getZExtValue() == 0x80000000U &&
4766 CC == ISD::SETUGT && isa<ConstantSDNode>(LHS.getOperand(1)) &&
4767 cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue() < 31) {
4768 unsigned ShiftAmt =
4769 cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue() + 1;
4770 SDValue Shift = DAG.getNode(ARMISD::LSLS, dl,
4771 DAG.getVTList(MVT::i32, MVT::i32),
4772 LHS.getOperand(0),
4773 DAG.getConstant(ShiftAmt, dl, MVT::i32));
4774 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, ARM::CPSR,
4775 Shift.getValue(1), SDValue());
4776 ARMcc = DAG.getConstant(ARMCC::HI, dl, MVT::i32);
4777 return Chain.getValue(1);
4778 }
4779
4780 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
4781
4782 // If the RHS is a constant zero then the V (overflow) flag will never be
4783 // set. This can allow us to simplify GE to PL or LT to MI, which can be
4784 // simpler for other passes (like the peephole optimiser) to deal with.
4785 if (isNullConstant(RHS)) {
4786 switch (CondCode) {
4787 default: break;
4788 case ARMCC::GE:
4789 CondCode = ARMCC::PL;
4790 break;
4791 case ARMCC::LT:
4792 CondCode = ARMCC::MI;
4793 break;
4794 }
4795 }
4796
4797 ARMISD::NodeType CompareType;
4798 switch (CondCode) {
4799 default:
4800 CompareType = ARMISD::CMP;
4801 break;
4802 case ARMCC::EQ:
4803 case ARMCC::NE:
4804 // Uses only Z Flag
4805 CompareType = ARMISD::CMPZ;
4806 break;
4807 }
4808 ARMcc = DAG.getConstant(CondCode, dl, MVT::i32);
4809 return DAG.getNode(CompareType, dl, MVT::Glue, LHS, RHS);
4810}
4811
4812/// Returns a appropriate VFP CMP (fcmp{s|d}+fmstat) for the given operands.
4813SDValue ARMTargetLowering::getVFPCmp(SDValue LHS, SDValue RHS,
4814 SelectionDAG &DAG, const SDLoc &dl,
4815 bool Signaling) const {
4816 assert(Subtarget->hasFP64() || RHS.getValueType() != MVT::f64)(static_cast <bool> (Subtarget->hasFP64() || RHS.getValueType
() != MVT::f64) ? void (0) : __assert_fail ("Subtarget->hasFP64() || RHS.getValueType() != MVT::f64"
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 4816, __extension__
__PRETTY_FUNCTION__))
;
4817 SDValue Cmp;
4818 if (!isFloatingPointZero(RHS))
4819 Cmp = DAG.getNode(Signaling ? ARMISD::CMPFPE : ARMISD::CMPFP,
4820 dl, MVT::Glue, LHS, RHS);
4821 else
4822 Cmp = DAG.getNode(Signaling ? ARMISD::CMPFPEw0 : ARMISD::CMPFPw0,
4823 dl, MVT::Glue, LHS);
4824 return DAG.getNode(ARMISD::FMSTAT, dl, MVT::Glue, Cmp);
4825}
4826
4827/// duplicateCmp - Glue values can have only one use, so this function
4828/// duplicates a comparison node.
4829SDValue
4830ARMTargetLowering::duplicateCmp(SDValue Cmp, SelectionDAG &DAG) const {
4831 unsigned Opc = Cmp.getOpcode();
4832 SDLoc DL(Cmp);
4833 if (Opc == ARMISD::CMP || Opc == ARMISD::CMPZ)
4834 return DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0),Cmp.getOperand(1));
4835
4836 assert(Opc == ARMISD::FMSTAT && "unexpected comparison operation")(static_cast <bool> (Opc == ARMISD::FMSTAT && "unexpected comparison operation"
) ? void (0) : __assert_fail ("Opc == ARMISD::FMSTAT && \"unexpected comparison operation\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 4836, __extension__
__PRETTY_FUNCTION__))
;
4837 Cmp = Cmp.getOperand(0);
4838 Opc = Cmp.getOpcode();
4839 if (Opc == ARMISD::CMPFP)
4840 Cmp = DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0),Cmp.getOperand(1));
4841 else {
4842 assert(Opc == ARMISD::CMPFPw0 && "unexpected operand of FMSTAT")(static_cast <bool> (Opc == ARMISD::CMPFPw0 && "unexpected operand of FMSTAT"
) ? void (0) : __assert_fail ("Opc == ARMISD::CMPFPw0 && \"unexpected operand of FMSTAT\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 4842, __extension__
__PRETTY_FUNCTION__))
;
4843 Cmp = DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0));
4844 }
4845 return DAG.getNode(ARMISD::FMSTAT, DL, MVT::Glue, Cmp);
4846}
4847
4848// This function returns three things: the arithmetic computation itself
4849// (Value), a comparison (OverflowCmp), and a condition code (ARMcc). The
4850// comparison and the condition code define the case in which the arithmetic
4851// computation *does not* overflow.
4852std::pair<SDValue, SDValue>
4853ARMTargetLowering::getARMXALUOOp(SDValue Op, SelectionDAG &DAG,
4854 SDValue &ARMcc) const {
4855 assert(Op.getValueType() == MVT::i32 && "Unsupported value type")(static_cast <bool> (Op.getValueType() == MVT::i32 &&
"Unsupported value type") ? void (0) : __assert_fail ("Op.getValueType() == MVT::i32 && \"Unsupported value type\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 4855, __extension__
__PRETTY_FUNCTION__))
;
4856
4857 SDValue Value, OverflowCmp;
4858 SDValue LHS = Op.getOperand(0);
4859 SDValue RHS = Op.getOperand(1);
4860 SDLoc dl(Op);
4861
4862 // FIXME: We are currently always generating CMPs because we don't support
4863 // generating CMN through the backend. This is not as good as the natural
4864 // CMP case because it causes a register dependency and cannot be folded
4865 // later.
4866
4867 switch (Op.getOpcode()) {
4868 default:
4869 llvm_unreachable("Unknown overflow instruction!")::llvm::llvm_unreachable_internal("Unknown overflow instruction!"
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 4869)
;
4870 case ISD::SADDO:
4871 ARMcc = DAG.getConstant(ARMCC::VC, dl, MVT::i32);
4872 Value = DAG.getNode(ISD::ADD, dl, Op.getValueType(), LHS, RHS);
4873 OverflowCmp = DAG.getNode(ARMISD::CMP, dl, MVT::Glue, Value, LHS);
4874 break;
4875 case ISD::UADDO:
4876 ARMcc = DAG.getConstant(ARMCC::HS, dl, MVT::i32);
4877 // We use ADDC here to correspond to its use in LowerUnsignedALUO.
4878 // We do not use it in the USUBO case as Value may not be used.
4879 Value = DAG.getNode(ARMISD::ADDC, dl,
4880 DAG.getVTList(Op.getValueType(), MVT::i32), LHS, RHS)
4881 .getValue(0);
4882 OverflowCmp = DAG.getNode(ARMISD::CMP, dl, MVT::Glue, Value, LHS);
4883 break;
4884 case ISD::SSUBO:
4885 ARMcc = DAG.getConstant(ARMCC::VC, dl, MVT::i32);
4886 Value = DAG.getNode(ISD::SUB, dl, Op.getValueType(), LHS, RHS);
4887 OverflowCmp = DAG.getNode(ARMISD::CMP, dl, MVT::Glue, LHS, RHS);
4888 break;
4889 case ISD::USUBO:
4890 ARMcc = DAG.getConstant(ARMCC::HS, dl, MVT::i32);
4891 Value = DAG.getNode(ISD::SUB, dl, Op.getValueType(), LHS, RHS);
4892 OverflowCmp = DAG.getNode(ARMISD::CMP, dl, MVT::Glue, LHS, RHS);
4893 break;
4894 case ISD::UMULO:
4895 // We generate a UMUL_LOHI and then check if the high word is 0.
4896 ARMcc = DAG.getConstant(ARMCC::EQ, dl, MVT::i32);
4897 Value = DAG.getNode(ISD::UMUL_LOHI, dl,
4898 DAG.getVTList(Op.getValueType(), Op.getValueType()),
4899 LHS, RHS);
4900 OverflowCmp = DAG.getNode(ARMISD::CMP, dl, MVT::Glue, Value.getValue(1),
4901 DAG.getConstant(0, dl, MVT::i32));
4902 Value = Value.getValue(0); // We only want the low 32 bits for the result.
4903 break;
4904 case ISD::SMULO:
4905 // We generate a SMUL_LOHI and then check if all the bits of the high word
4906 // are the same as the sign bit of the low word.
4907 ARMcc = DAG.getConstant(ARMCC::EQ, dl, MVT::i32);
4908 Value = DAG.getNode(ISD::SMUL_LOHI, dl,
4909 DAG.getVTList(Op.getValueType(), Op.getValueType()),
4910 LHS, RHS);
4911 OverflowCmp = DAG.getNode(ARMISD::CMP, dl, MVT::Glue, Value.getValue(1),
4912 DAG.getNode(ISD::SRA, dl, Op.getValueType(),
4913 Value.getValue(0),
4914 DAG.getConstant(31, dl, MVT::i32)));
4915 Value = Value.getValue(0); // We only want the low 32 bits for the result.
4916 break;
4917 } // switch (...)
4918
4919 return std::make_pair(Value, OverflowCmp);
4920}
4921
4922SDValue
4923ARMTargetLowering::LowerSignedALUO(SDValue Op, SelectionDAG &DAG) const {
4924 // Let legalize expand this if it isn't a legal type yet.
4925 if (!DAG.getTargetLoweringInfo().isTypeLegal(Op.getValueType()))
4926 return SDValue();
4927
4928 SDValue Value, OverflowCmp;
4929 SDValue ARMcc;
4930 std::tie(Value, OverflowCmp) = getARMXALUOOp(Op, DAG, ARMcc);
4931 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
4932 SDLoc dl(Op);
4933 // We use 0 and 1 as false and true values.
4934 SDValue TVal = DAG.getConstant(1, dl, MVT::i32);
4935 SDValue FVal = DAG.getConstant(0, dl, MVT::i32);
4936 EVT VT = Op.getValueType();
4937
4938 SDValue Overflow = DAG.getNode(ARMISD::CMOV, dl, VT, TVal, FVal,
4939 ARMcc, CCR, OverflowCmp);
4940
4941 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
4942 return DAG.getNode(ISD::MERGE_VALUES, dl, VTs, Value, Overflow);
4943}
4944
4945static SDValue ConvertBooleanCarryToCarryFlag(SDValue BoolCarry,
4946 SelectionDAG &DAG) {
4947 SDLoc DL(BoolCarry);
4948 EVT CarryVT = BoolCarry.getValueType();
4949
4950 // This converts the boolean value carry into the carry flag by doing
4951 // ARMISD::SUBC Carry, 1
4952 SDValue Carry = DAG.getNode(ARMISD::SUBC, DL,
4953 DAG.getVTList(CarryVT, MVT::i32),
4954 BoolCarry, DAG.getConstant(1, DL, CarryVT));
4955 return Carry.getValue(1);
4956}
4957
4958static SDValue ConvertCarryFlagToBooleanCarry(SDValue Flags, EVT VT,
4959 SelectionDAG &DAG) {
4960 SDLoc DL(Flags);
4961
4962 // Now convert the carry flag into a boolean carry. We do this
4963 // using ARMISD:ADDE 0, 0, Carry
4964 return DAG.getNode(ARMISD::ADDE, DL, DAG.getVTList(VT, MVT::i32),
4965 DAG.getConstant(0, DL, MVT::i32),
4966 DAG.getConstant(0, DL, MVT::i32), Flags);
4967}
4968
4969SDValue ARMTargetLowering::LowerUnsignedALUO(SDValue Op,
4970 SelectionDAG &DAG) const {
4971 // Let legalize expand this if it isn't a legal type yet.
4972 if (!DAG.getTargetLoweringInfo().isTypeLegal(Op.getValueType()))
4973 return SDValue();
4974
4975 SDValue LHS = Op.getOperand(0);
4976 SDValue RHS = Op.getOperand(1);
4977 SDLoc dl(Op);
4978
4979 EVT VT = Op.getValueType();
4980 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
4981 SDValue Value;
4982 SDValue Overflow;
4983 switch (Op.getOpcode()) {
4984 default:
4985 llvm_unreachable("Unknown overflow instruction!")::llvm::llvm_unreachable_internal("Unknown overflow instruction!"
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 4985)
;
4986 case ISD::UADDO:
4987 Value = DAG.getNode(ARMISD::ADDC, dl, VTs, LHS, RHS);
4988 // Convert the carry flag into a boolean value.
4989 Overflow = ConvertCarryFlagToBooleanCarry(Value.getValue(1), VT, DAG);
4990 break;
4991 case ISD::USUBO: {
4992 Value = DAG.getNode(ARMISD::SUBC, dl, VTs, LHS, RHS);
4993 // Convert the carry flag into a boolean value.
4994 Overflow = ConvertCarryFlagToBooleanCarry(Value.getValue(1), VT, DAG);
4995 // ARMISD::SUBC returns 0 when we have to borrow, so make it an overflow
4996 // value. So compute 1 - C.
4997 Overflow = DAG.getNode(ISD::SUB, dl, MVT::i32,
4998 DAG.getConstant(1, dl, MVT::i32), Overflow);
4999 break;
5000 }
5001 }
5002
5003 return DAG.getNode(ISD::MERGE_VALUES, dl, VTs, Value, Overflow);
5004}
5005
5006static SDValue LowerADDSUBSAT(SDValue Op, SelectionDAG &DAG,
5007 const ARMSubtarget *Subtarget) {
5008 EVT VT = Op.getValueType();
5009 if (!Subtarget->hasV6Ops() || !Subtarget->hasDSP())
5010 return SDValue();
5011 if (!VT.isSimple())
5012 return SDValue();
5013
5014 unsigned NewOpcode;
5015 switch (VT.getSimpleVT().SimpleTy) {
5016 default:
5017 return SDValue();
5018 case MVT::i8:
5019 switch (Op->getOpcode()) {
5020 case ISD::UADDSAT:
5021 NewOpcode = ARMISD::UQADD8b;
5022 break;
5023 case ISD::SADDSAT:
5024 NewOpcode = ARMISD::QADD8b;
5025 break;
5026 case ISD::USUBSAT:
5027 NewOpcode = ARMISD::UQSUB8b;
5028 break;
5029 case ISD::SSUBSAT:
5030 NewOpcode = ARMISD::QSUB8b;
5031 break;
5032 }
5033 break;
5034 case MVT::i16:
5035 switch (Op->getOpcode()) {
5036 case ISD::UADDSAT:
5037 NewOpcode = ARMISD::UQADD16b;
5038 break;
5039 case ISD::SADDSAT:
5040 NewOpcode = ARMISD::QADD16b;
5041 break;
5042 case ISD::USUBSAT:
5043 NewOpcode = ARMISD::UQSUB16b;
5044 break;
5045 case ISD::SSUBSAT:
5046 NewOpcode = ARMISD::QSUB16b;
5047 break;
5048 }
5049 break;
5050 }
5051
5052 SDLoc dl(Op);
5053 SDValue Add =
5054 DAG.getNode(NewOpcode, dl, MVT::i32,
5055 DAG.getSExtOrTrunc(Op->getOperand(0), dl, MVT::i32),
5056 DAG.getSExtOrTrunc(Op->getOperand(1), dl, MVT::i32));
5057 return DAG.getNode(ISD::TRUNCATE, dl, VT, Add);
5058}
5059
5060SDValue ARMTargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
5061 SDValue Cond = Op.getOperand(0);
5062 SDValue SelectTrue = Op.getOperand(1);
5063 SDValue SelectFalse = Op.getOperand(2);
5064 SDLoc dl(Op);
5065 unsigned Opc = Cond.getOpcode();
5066
5067 if (Cond.getResNo() == 1 &&
5068 (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO ||
5069 Opc == ISD::USUBO)) {
5070 if (!DAG.getTargetLoweringInfo().isTypeLegal(Cond->getValueType(0)))
5071 return SDValue();
5072
5073 SDValue Value, OverflowCmp;
5074 SDValue ARMcc;
5075 std::tie(Value, OverflowCmp) = getARMXALUOOp(Cond, DAG, ARMcc);
5076 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
5077 EVT VT = Op.getValueType();
5078
5079 return getCMOV(dl, VT, SelectTrue, SelectFalse, ARMcc, CCR,
5080 OverflowCmp, DAG);
5081 }
5082
5083 // Convert:
5084 //
5085 // (select (cmov 1, 0, cond), t, f) -> (cmov t, f, cond)
5086 // (select (cmov 0, 1, cond), t, f) -> (cmov f, t, cond)
5087 //
5088 if (Cond.getOpcode() == ARMISD::CMOV && Cond.hasOneUse()) {
5089 const ConstantSDNode *CMOVTrue =
5090 dyn_cast<ConstantSDNode>(Cond.getOperand(0));
5091 const ConstantSDNode *CMOVFalse =
5092 dyn_cast<ConstantSDNode>(Cond.getOperand(1));
5093
5094 if (CMOVTrue && CMOVFalse) {
5095 unsigned CMOVTrueVal = CMOVTrue->getZExtValue();
5096 unsigned CMOVFalseVal = CMOVFalse->getZExtValue();
5097
5098 SDValue True;
5099 SDValue False;
5100 if (CMOVTrueVal == 1 && CMOVFalseVal == 0) {
5101 True = SelectTrue;
5102 False = SelectFalse;
5103 } else if (CMOVTrueVal == 0 && CMOVFalseVal == 1) {
5104 True = SelectFalse;
5105 False = SelectTrue;
5106 }
5107
5108 if (True.getNode() && False.getNode()) {
5109 EVT VT = Op.getValueType();
5110 SDValue ARMcc = Cond.getOperand(2);
5111 SDValue CCR = Cond.getOperand(3);
5112 SDValue Cmp = duplicateCmp(Cond.getOperand(4), DAG);
5113 assert(True.getValueType() == VT)(static_cast <bool> (True.getValueType() == VT) ? void (
0) : __assert_fail ("True.getValueType() == VT", "llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 5113, __extension__ __PRETTY_FUNCTION__))
;
5114 return getCMOV(dl, VT, True, False, ARMcc, CCR, Cmp, DAG);
5115 }
5116 }
5117 }
5118
5119 // ARM's BooleanContents value is UndefinedBooleanContent. Mask out the
5120 // undefined bits before doing a full-word comparison with zero.
5121 Cond = DAG.getNode(ISD::AND, dl, Cond.getValueType(), Cond,
5122 DAG.getConstant(1, dl, Cond.getValueType()));
5123
5124 return DAG.getSelectCC(dl, Cond,
5125 DAG.getConstant(0, dl, Cond.getValueType()),
5126 SelectTrue, SelectFalse, ISD::SETNE);
5127}
5128
5129static void checkVSELConstraints(ISD::CondCode CC, ARMCC::CondCodes &CondCode,
5130 bool &swpCmpOps, bool &swpVselOps) {
5131 // Start by selecting the GE condition code for opcodes that return true for
5132 // 'equality'
5133 if (CC == ISD::SETUGE || CC == ISD::SETOGE || CC == ISD::SETOLE ||
5134 CC == ISD::SETULE || CC == ISD::SETGE || CC == ISD::SETLE)
5135 CondCode = ARMCC::GE;
5136
5137 // and GT for opcodes that return false for 'equality'.
5138 else if (CC == ISD::SETUGT || CC == ISD::SETOGT || CC == ISD::SETOLT ||
5139 CC == ISD::SETULT || CC == ISD::SETGT || CC == ISD::SETLT)
5140 CondCode = ARMCC::GT;
5141
5142 // Since we are constrained to GE/GT, if the opcode contains 'less', we need
5143 // to swap the compare operands.
5144 if (CC == ISD::SETOLE || CC == ISD::SETULE || CC == ISD::SETOLT ||
5145 CC == ISD::SETULT || CC == ISD::SETLE || CC == ISD::SETLT)
5146 swpCmpOps = true;
5147
5148 // Both GT and GE are ordered comparisons, and return false for 'unordered'.
5149 // If we have an unordered opcode, we need to swap the operands to the VSEL
5150 // instruction (effectively negating the condition).
5151 //
5152 // This also has the effect of swapping which one of 'less' or 'greater'
5153 // returns true, so we also swap the compare operands. It also switches
5154 // whether we return true for 'equality', so we compensate by picking the
5155 // opposite condition code to our original choice.
5156 if (CC == ISD::SETULE || CC == ISD::SETULT || CC == ISD::SETUGE ||
5157 CC == ISD::SETUGT) {
5158 swpCmpOps = !swpCmpOps;
5159 swpVselOps = !swpVselOps;
5160 CondCode = CondCode == ARMCC::GT ? ARMCC::GE : ARMCC::GT;
5161 }
5162
5163 // 'ordered' is 'anything but unordered', so use the VS condition code and
5164 // swap the VSEL operands.
5165 if (CC == ISD::SETO) {
5166 CondCode = ARMCC::VS;
5167 swpVselOps = true;
5168 }
5169
5170 // 'unordered or not equal' is 'anything but equal', so use the EQ condition
5171 // code and swap the VSEL operands. Also do this if we don't care about the
5172 // unordered case.
5173 if (CC == ISD::SETUNE || CC == ISD::SETNE) {
5174 CondCode = ARMCC::EQ;
5175 swpVselOps = true;
5176 }
5177}
5178
5179SDValue ARMTargetLowering::getCMOV(const SDLoc &dl, EVT VT, SDValue FalseVal,
5180 SDValue TrueVal, SDValue ARMcc, SDValue CCR,
5181 SDValue Cmp, SelectionDAG &DAG) const {
5182 if (!Subtarget->hasFP64() && VT == MVT::f64) {
5183 FalseVal = DAG.getNode(ARMISD::VMOVRRD, dl,
5184 DAG.getVTList(MVT::i32, MVT::i32), FalseVal);
5185 TrueVal = DAG.getNode(ARMISD::VMOVRRD, dl,
5186 DAG.getVTList(MVT::i32, MVT::i32), TrueVal);
5187
5188 SDValue TrueLow = TrueVal.getValue(0);
5189 SDValue TrueHigh = TrueVal.getValue(1);
5190 SDValue FalseLow = FalseVal.getValue(0);
5191 SDValue FalseHigh = FalseVal.getValue(1);
5192
5193 SDValue Low = DAG.getNode(ARMISD::CMOV, dl, MVT::i32, FalseLow, TrueLow,
5194 ARMcc, CCR, Cmp);
5195 SDValue High = DAG.getNode(ARMISD::CMOV, dl, MVT::i32, FalseHigh, TrueHigh,
5196 ARMcc, CCR, duplicateCmp(Cmp, DAG));
5197
5198 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Low, High);
5199 } else {
5200 return DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMcc, CCR,
5201 Cmp);
5202 }
5203}
5204
5205static bool isGTorGE(ISD::CondCode CC) {
5206 return CC == ISD::SETGT || CC == ISD::SETGE;
5207}
5208
5209static bool isLTorLE(ISD::CondCode CC) {
5210 return CC == ISD::SETLT || CC == ISD::SETLE;
5211}
5212
5213// See if a conditional (LHS CC RHS ? TrueVal : FalseVal) is lower-saturating.
5214// All of these conditions (and their <= and >= counterparts) will do:
5215// x < k ? k : x
5216// x > k ? x : k
5217// k < x ? x : k
5218// k > x ? k : x
5219static bool isLowerSaturate(const SDValue LHS, const SDValue RHS,
5220 const SDValue TrueVal, const SDValue FalseVal,
5221 const ISD::CondCode CC, const SDValue K) {
5222 return (isGTorGE(CC) &&
5223 ((K == LHS && K == TrueVal) || (K == RHS && K == FalseVal))) ||
5224 (isLTorLE(CC) &&
5225 ((K == RHS && K == TrueVal) || (K == LHS && K == FalseVal)));
5226}
5227
5228// Check if two chained conditionals could be converted into SSAT or USAT.
5229//
5230// SSAT can replace a set of two conditional selectors that bound a number to an
5231// interval of type [k, ~k] when k + 1 is a power of 2. Here are some examples:
5232//
5233// x < -k ? -k : (x > k ? k : x)
5234// x < -k ? -k : (x < k ? x : k)
5235// x > -k ? (x > k ? k : x) : -k
5236// x < k ? (x < -k ? -k : x) : k
5237// etc.
5238//
5239// LLVM canonicalizes these to either a min(max()) or a max(min())
5240// pattern. This function tries to match one of these and will return a SSAT
5241// node if successful.
5242//
5243// USAT works similarily to SSAT but bounds on the interval [0, k] where k + 1
5244// is a power of 2.
5245static SDValue LowerSaturatingConditional(SDValue Op, SelectionDAG &DAG) {
5246 EVT VT = Op.getValueType();
5247 SDValue V1 = Op.getOperand(0);
5248 SDValue K1 = Op.getOperand(1);
5249 SDValue TrueVal1 = Op.getOperand(2);
5250 SDValue FalseVal1 = Op.getOperand(3);
5251 ISD::CondCode CC1 = cast<CondCodeSDNode>(Op.getOperand(4))->get();
5252
5253 const SDValue Op2 = isa<ConstantSDNode>(TrueVal1) ? FalseVal1 : TrueVal1;
5254 if (Op2.getOpcode() != ISD::SELECT_CC)
5255 return SDValue();
5256
5257 SDValue V2 = Op2.getOperand(0);
5258 SDValue K2 = Op2.getOperand(1);
5259 SDValue TrueVal2 = Op2.getOperand(2);
5260 SDValue FalseVal2 = Op2.getOperand(3);
5261 ISD::CondCode CC2 = cast<CondCodeSDNode>(Op2.getOperand(4))->get();
5262
5263 SDValue V1Tmp = V1;
5264 SDValue V2Tmp = V2;
5265
5266 // Check that the registers and the constants match a max(min()) or min(max())
5267 // pattern
5268 if (V1Tmp != TrueVal1 || V2Tmp != TrueVal2 || K1 != FalseVal1 ||
5269 K2 != FalseVal2 ||
5270 !((isGTorGE(CC1) && isLTorLE(CC2)) || (isLTorLE(CC1) && isGTorGE(CC2))))
5271 return SDValue();
5272
5273 // Check that the constant in the lower-bound check is
5274 // the opposite of the constant in the upper-bound check
5275 // in 1's complement.
5276 if (!isa<ConstantSDNode>(K1) || !isa<ConstantSDNode>(K2))
5277 return SDValue();
5278
5279 int64_t Val1 = cast<ConstantSDNode>(K1)->getSExtValue();
5280 int64_t Val2 = cast<ConstantSDNode>(K2)->getSExtValue();
5281 int64_t PosVal = std::max(Val1, Val2);
5282 int64_t NegVal = std::min(Val1, Val2);
5283
5284 if (!((Val1 > Val2 && isLTorLE(CC1)) || (Val1 < Val2 && isLTorLE(CC2))) ||
5285 !isPowerOf2_64(PosVal + 1))
5286 return SDValue();
5287
5288 // Handle the difference between USAT (unsigned) and SSAT (signed)
5289 // saturation
5290 // At this point, PosVal is guaranteed to be positive
5291 uint64_t K = PosVal;
5292 SDLoc dl(Op);
5293 if (Val1 == ~Val2)
5294 return DAG.getNode(ARMISD::SSAT, dl, VT, V2Tmp,
5295 DAG.getConstant(countTrailingOnes(K), dl, VT));
5296 if (NegVal == 0)
5297 return DAG.getNode(ARMISD::USAT, dl, VT, V2Tmp,
5298 DAG.getConstant(countTrailingOnes(K), dl, VT));
5299
5300 return SDValue();
5301}
5302
5303// Check if a condition of the type x < k ? k : x can be converted into a
5304// bit operation instead of conditional moves.
5305// Currently this is allowed given:
5306// - The conditions and values match up
5307// - k is 0 or -1 (all ones)
5308// This function will not check the last condition, thats up to the caller
5309// It returns true if the transformation can be made, and in such case
5310// returns x in V, and k in SatK.
5311static bool isLowerSaturatingConditional(const SDValue &Op, SDValue &V,
5312 SDValue &SatK)
5313{
5314 SDValue LHS = Op.getOperand(0);
5315 SDValue RHS = Op.getOperand(1);
5316 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
5317 SDValue TrueVal = Op.getOperand(2);
5318 SDValue FalseVal = Op.getOperand(3);
5319
5320 SDValue *K = isa<ConstantSDNode>(LHS) ? &LHS : isa<ConstantSDNode>(RHS)
5321 ? &RHS
5322 : nullptr;
5323
5324 // No constant operation in comparison, early out
5325 if (!K)
5326 return false;
5327
5328 SDValue KTmp = isa<ConstantSDNode>(TrueVal) ? TrueVal : FalseVal;
5329 V = (KTmp == TrueVal) ? FalseVal : TrueVal;
5330 SDValue VTmp = (K && *K == LHS) ? RHS : LHS;
5331
5332 // If the constant on left and right side, or variable on left and right,
5333 // does not match, early out
5334 if (*K != KTmp || V != VTmp)
5335 return false;
5336
5337 if (isLowerSaturate(LHS, RHS, TrueVal, FalseVal, CC, *K)) {
5338 SatK = *K;
5339 return true;
5340 }
5341
5342 return false;
5343}
5344
5345bool ARMTargetLowering::isUnsupportedFloatingType(EVT VT) const {
5346 if (VT == MVT::f32)
5347 return !Subtarget->hasVFP2Base();
5348 if (VT == MVT::f64)
5349 return !Subtarget->hasFP64();
5350 if (VT == MVT::f16)
5351 return !Subtarget->hasFullFP16();
5352 return false;
5353}
5354
5355SDValue ARMTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
5356 EVT VT = Op.getValueType();
5357 SDLoc dl(Op);
5358
5359 // Try to convert two saturating conditional selects into a single SSAT
5360 if ((!Subtarget->isThumb() && Subtarget->hasV6Ops()) || Subtarget->isThumb2())
5361 if (SDValue SatValue = LowerSaturatingConditional(Op, DAG))
5362 return SatValue;
5363
5364 // Try to convert expressions of the form x < k ? k : x (and similar forms)
5365 // into more efficient bit operations, which is possible when k is 0 or -1
5366 // On ARM and Thumb-2 which have flexible operand 2 this will result in
5367 // single instructions. On Thumb the shift and the bit operation will be two
5368 // instructions.
5369 // Only allow this transformation on full-width (32-bit) operations
5370 SDValue LowerSatConstant;
5371 SDValue SatValue;
5372 if (VT == MVT::i32 &&
5373 isLowerSaturatingConditional(Op, SatValue, LowerSatConstant)) {
5374 SDValue ShiftV = DAG.getNode(ISD::SRA, dl, VT, SatValue,
5375 DAG.getConstant(31, dl, VT));
5376 if (isNullConstant(LowerSatConstant)) {
5377 SDValue NotShiftV = DAG.getNode(ISD::XOR, dl, VT, ShiftV,
5378 DAG.getAllOnesConstant(dl, VT));
5379 return DAG.getNode(ISD::AND, dl, VT, SatValue, NotShiftV);
5380 } else if (isAllOnesConstant(LowerSatConstant))
5381 return DAG.getNode(ISD::OR, dl, VT, SatValue, ShiftV);
5382 }
5383
5384 SDValue LHS = Op.getOperand(0);
5385 SDValue RHS = Op.getOperand(1);
5386 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
5387 SDValue TrueVal = Op.getOperand(2);
5388 SDValue FalseVal = Op.getOperand(3);
5389 ConstantSDNode *CFVal = dyn_cast<ConstantSDNode>(FalseVal);
5390 ConstantSDNode *CTVal = dyn_cast<ConstantSDNode>(TrueVal);
5391
5392 if (Subtarget->hasV8_1MMainlineOps() && CFVal && CTVal &&
5393 LHS.getValueType() == MVT::i32 && RHS.getValueType() == MVT::i32) {
5394 unsigned TVal = CTVal->getZExtValue();
5395 unsigned FVal = CFVal->getZExtValue();
5396 unsigned Opcode = 0;
5397
5398 if (TVal == ~FVal) {
5399 Opcode = ARMISD::CSINV;
5400 } else if (TVal == ~FVal + 1) {
5401 Opcode = ARMISD::CSNEG;
5402 } else if (TVal + 1 == FVal) {
5403 Opcode = ARMISD::CSINC;
5404 } else if (TVal == FVal + 1) {
5405 Opcode = ARMISD::CSINC;
5406 std::swap(TrueVal, FalseVal);
5407 std::swap(TVal, FVal);
5408 CC = ISD::getSetCCInverse(CC, LHS.getValueType());
5409 }
5410
5411 if (Opcode) {
5412 // If one of the constants is cheaper than another, materialise the
5413 // cheaper one and let the csel generate the other.
5414 if (Opcode != ARMISD::CSINC &&
5415 HasLowerConstantMaterializationCost(FVal, TVal, Subtarget)) {
5416 std::swap(TrueVal, FalseVal);
5417 std::swap(TVal, FVal);
5418 CC = ISD::getSetCCInverse(CC, LHS.getValueType());
5419 }
5420
5421 // Attempt to use ZR checking TVal is 0, possibly inverting the condition
5422 // to get there. CSINC not is invertable like the other two (~(~a) == a,
5423 // -(-a) == a, but (a+1)+1 != a).
5424 if (FVal == 0 && Opcode != ARMISD::CSINC) {
5425 std::swap(TrueVal, FalseVal);
5426 std::swap(TVal, FVal);
5427 CC = ISD::getSetCCInverse(CC, LHS.getValueType());
5428 }
5429
5430 // Drops F's value because we can get it by inverting/negating TVal.
5431 FalseVal = TrueVal;
5432
5433 SDValue ARMcc;
5434 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
5435 EVT VT = TrueVal.getValueType();
5436 return DAG.getNode(Opcode, dl, VT, TrueVal, FalseVal, ARMcc, Cmp);
5437 }
5438 }
5439
5440 if (isUnsupportedFloatingType(LHS.getValueType())) {
5441 DAG.getTargetLoweringInfo().softenSetCCOperands(
5442 DAG, LHS.getValueType(), LHS, RHS, CC, dl, LHS, RHS);
5443
5444 // If softenSetCCOperands only returned one value, we should compare it to
5445 // zero.
5446 if (!RHS.getNode()) {
5447 RHS = DAG.getConstant(0, dl, LHS.getValueType());
5448 CC = ISD::SETNE;
5449 }
5450 }
5451
5452 if (LHS.getValueType() == MVT::i32) {
5453 // Try to generate VSEL on ARMv8.
5454 // The VSEL instruction can't use all the usual ARM condition
5455 // codes: it only has two bits to select the condition code, so it's
5456 // constrained to use only GE, GT, VS and EQ.
5457 //
5458 // To implement all the various ISD::SETXXX opcodes, we sometimes need to
5459 // swap the operands of the previous compare instruction (effectively
5460 // inverting the compare condition, swapping 'less' and 'greater') and
5461 // sometimes need to swap the operands to the VSEL (which inverts the
5462 // condition in the sense of firing whenever the previous condition didn't)
5463 if (Subtarget->hasFPARMv8Base() && (TrueVal.getValueType() == MVT::f16 ||
5464 TrueVal.getValueType() == MVT::f32 ||
5465 TrueVal.getValueType() == MVT::f64)) {
5466 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
5467 if (CondCode == ARMCC::LT || CondCode == ARMCC::LE ||
5468 CondCode == ARMCC::VC || CondCode == ARMCC::NE) {
5469 CC = ISD::getSetCCInverse(CC, LHS.getValueType());
5470 std::swap(TrueVal, FalseVal);
5471 }
5472 }
5473
5474 SDValue ARMcc;
5475 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
5476 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
5477 // Choose GE over PL, which vsel does now support
5478 if (cast<ConstantSDNode>(ARMcc)->getZExtValue() == ARMCC::PL)
5479 ARMcc = DAG.getConstant(ARMCC::GE, dl, MVT::i32);
5480 return getCMOV(dl, VT, FalseVal, TrueVal, ARMcc, CCR, Cmp, DAG);
5481 }
5482
5483 ARMCC::CondCodes CondCode, CondCode2;
5484 FPCCToARMCC(CC, CondCode, CondCode2);
5485
5486 // Normalize the fp compare. If RHS is zero we prefer to keep it there so we
5487 // match CMPFPw0 instead of CMPFP, though we don't do this for f16 because we
5488 // must use VSEL (limited condition codes), due to not having conditional f16
5489 // moves.
5490 if (Subtarget->hasFPARMv8Base() &&
5491 !(isFloatingPointZero(RHS) && TrueVal.getValueType() != MVT::f16) &&
5492 (TrueVal.getValueType() == MVT::f16 ||
5493 TrueVal.getValueType() == MVT::f32 ||
5494 TrueVal.getValueType() == MVT::f64)) {
5495 bool swpCmpOps = false;
5496 bool swpVselOps = false;
5497 checkVSELConstraints(CC, CondCode, swpCmpOps, swpVselOps);
5498
5499 if (CondCode == ARMCC::GT || CondCode == ARMCC::GE ||
5500 CondCode == ARMCC::VS || CondCode == ARMCC::EQ) {
5501 if (swpCmpOps)
5502 std::swap(LHS, RHS);
5503 if (swpVselOps)
5504 std::swap(TrueVal, FalseVal);
5505 }
5506 }
5507
5508 SDValue ARMcc = DAG.getConstant(CondCode, dl, MVT::i32);
5509 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
5510 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
5511 SDValue Result = getCMOV(dl, VT, FalseVal, TrueVal, ARMcc, CCR, Cmp, DAG);
5512 if (CondCode2 != ARMCC::AL) {
5513 SDValue ARMcc2 = DAG.getConstant(CondCode2, dl, MVT::i32);
5514 // FIXME: Needs another CMP because flag can have but one use.
5515 SDValue Cmp2 = getVFPCmp(LHS, RHS, DAG, dl);
5516 Result = getCMOV(dl, VT, Result, TrueVal, ARMcc2, CCR, Cmp2, DAG);
5517 }
5518 return Result;
5519}
5520
5521/// canChangeToInt - Given the fp compare operand, return true if it is suitable
5522/// to morph to an integer compare sequence.
5523static bool canChangeToInt(SDValue Op, bool &SeenZero,
5524 const ARMSubtarget *Subtarget) {
5525 SDNode *N = Op.getNode();
5526 if (!N->hasOneUse())
5527 // Otherwise it requires moving the value from fp to integer registers.
5528 return false;
5529 if (!N->getNumValues())
5530 return false;
5531 EVT VT = Op.getValueType();
5532 if (VT != MVT::f32 && !Subtarget->isFPBrccSlow())
5533 // f32 case is generally profitable. f64 case only makes sense when vcmpe +
5534 // vmrs are very slow, e.g. cortex-a8.
5535 return false;
5536
5537 if (isFloatingPointZero(Op)) {
5538 SeenZero = true;
5539 return true;
5540 }
5541 return ISD::isNormalLoad(N);
5542}
5543
5544static SDValue bitcastf32Toi32(SDValue Op, SelectionDAG &DAG) {
5545 if (isFloatingPointZero(Op))
1
Value assigned to 'Op.Node'
2
Calling 'isFloatingPointZero'
5546 return DAG.getConstant(0, SDLoc(Op), MVT::i32);
5547
5548 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Op))
5549 return DAG.getLoad(MVT::i32, SDLoc(Op), Ld->getChain(), Ld->getBasePtr(),
5550 Ld->getPointerInfo(), Ld->getAlignment(),
5551 Ld->getMemOperand()->getFlags());
5552
5553 llvm_unreachable("Unknown VFP cmp argument!")::llvm::llvm_unreachable_internal("Unknown VFP cmp argument!"
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 5553)
;
5554}
5555
5556static void expandf64Toi32(SDValue Op, SelectionDAG &DAG,
5557 SDValue &RetVal1, SDValue &RetVal2) {
5558 SDLoc dl(Op);
5559
5560 if (isFloatingPointZero(Op)) {
5561 RetVal1 = DAG.getConstant(0, dl, MVT::i32);
5562 RetVal2 = DAG.getConstant(0, dl, MVT::i32);
5563 return;
5564 }
5565
5566 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Op)) {
5567 SDValue Ptr = Ld->getBasePtr();
5568 RetVal1 =
5569 DAG.getLoad(MVT::i32, dl, Ld->getChain(), Ptr, Ld->getPointerInfo(),
5570 Ld->getAlignment(), Ld->getMemOperand()->getFlags());
5571
5572 EVT PtrType = Ptr.getValueType();
5573 unsigned NewAlign = MinAlign(Ld->getAlignment(), 4);
5574 SDValue NewPtr = DAG.getNode(ISD::ADD, dl,
5575 PtrType, Ptr, DAG.getConstant(4, dl, PtrType));
5576 RetVal2 = DAG.getLoad(MVT::i32, dl, Ld->getChain(), NewPtr,
5577 Ld->getPointerInfo().getWithOffset(4), NewAlign,
5578 Ld->getMemOperand()->getFlags());
5579 return;
5580 }
5581
5582 llvm_unreachable("Unknown VFP cmp argument!")::llvm::llvm_unreachable_internal("Unknown VFP cmp argument!"
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 5582)
;
5583}
5584
5585/// OptimizeVFPBrcond - With -enable-unsafe-fp-math, it's legal to optimize some
5586/// f32 and even f64 comparisons to integer ones.
5587SDValue
5588ARMTargetLowering::OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const {
5589 SDValue Chain = Op.getOperand(0);
5590 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
5591 SDValue LHS = Op.getOperand(2);
5592 SDValue RHS = Op.getOperand(3);
5593 SDValue Dest = Op.getOperand(4);
5594 SDLoc dl(Op);
5595
5596 bool LHSSeenZero = false;
5597 bool LHSOk = canChangeToInt(LHS, LHSSeenZero, Subtarget);
5598 bool RHSSeenZero = false;
5599 bool RHSOk = canChangeToInt(RHS, RHSSeenZero, Subtarget);
5600 if (LHSOk && RHSOk && (LHSSeenZero || RHSSeenZero)) {
5601 // If unsafe fp math optimization is enabled and there are no other uses of
5602 // the CMP operands, and the condition code is EQ or NE, we can optimize it
5603 // to an integer comparison.
5604 if (CC == ISD::SETOEQ)
5605 CC = ISD::SETEQ;
5606 else if (CC == ISD::SETUNE)
5607 CC = ISD::SETNE;
5608
5609 SDValue Mask = DAG.getConstant(0x7fffffff, dl, MVT::i32);
5610 SDValue ARMcc;
5611 if (LHS.getValueType() == MVT::f32) {
5612 LHS = DAG.getNode(ISD::AND, dl, MVT::i32,
5613 bitcastf32Toi32(LHS, DAG), Mask);
5614 RHS = DAG.getNode(ISD::AND, dl, MVT::i32,
5615 bitcastf32Toi32(RHS, DAG), Mask);
5616 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
5617 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
5618 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other,
5619 Chain, Dest, ARMcc, CCR, Cmp);
5620 }
5621
5622 SDValue LHS1, LHS2;
5623 SDValue RHS1, RHS2;
5624 expandf64Toi32(LHS, DAG, LHS1, LHS2);
5625 expandf64Toi32(RHS, DAG, RHS1, RHS2);
5626 LHS2 = DAG.getNode(ISD::AND, dl, MVT::i32, LHS2, Mask);
5627 RHS2 = DAG.getNode(ISD::AND, dl, MVT::i32, RHS2, Mask);
5628 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
5629 ARMcc = DAG.getConstant(CondCode, dl, MVT::i32);
5630 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Glue);
5631 SDValue Ops[] = { Chain, ARMcc, LHS1, LHS2, RHS1, RHS2, Dest };
5632 return DAG.getNode(ARMISD::BCC_i64, dl, VTList, Ops);
5633 }
5634
5635 return SDValue();
5636}
5637
5638SDValue ARMTargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
5639 SDValue Chain = Op.getOperand(0);
5640 SDValue Cond = Op.getOperand(1);
5641 SDValue Dest = Op.getOperand(2);
5642 SDLoc dl(Op);
5643
5644 // Optimize {s|u}{add|sub|mul}.with.overflow feeding into a branch
5645 // instruction.
5646 unsigned Opc = Cond.getOpcode();
5647 bool OptimizeMul = (Opc == ISD::SMULO || Opc == ISD::UMULO) &&
5648 !Subtarget->isThumb1Only();
5649 if (Cond.getResNo() == 1 &&
5650 (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO ||
5651 Opc == ISD::USUBO || OptimizeMul)) {
5652 // Only lower legal XALUO ops.
5653 if (!DAG.getTargetLoweringInfo().isTypeLegal(Cond->getValueType(0)))
5654 return SDValue();
5655
5656 // The actual operation with overflow check.
5657 SDValue Value, OverflowCmp;
5658 SDValue ARMcc;
5659 std::tie(Value, OverflowCmp) = getARMXALUOOp(Cond, DAG, ARMcc);
5660
5661 // Reverse the condition code.
5662 ARMCC::CondCodes CondCode =
5663 (ARMCC::CondCodes)cast<const ConstantSDNode>(ARMcc)->getZExtValue();
5664 CondCode = ARMCC::getOppositeCondition(CondCode);
5665 ARMcc = DAG.getConstant(CondCode, SDLoc(ARMcc), MVT::i32);
5666 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
5667
5668 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other, Chain, Dest, ARMcc, CCR,
5669 OverflowCmp);
5670 }
5671
5672 return SDValue();
5673}
5674
5675SDValue ARMTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
5676 SDValue Chain = Op.getOperand(0);
5677 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
5678 SDValue LHS = Op.getOperand(2);
5679 SDValue RHS = Op.getOperand(3);
5680 SDValue Dest = Op.getOperand(4);
5681 SDLoc dl(Op);
5682
5683 if (isUnsupportedFloatingType(LHS.getValueType())) {
5684 DAG.getTargetLoweringInfo().softenSetCCOperands(
5685 DAG, LHS.getValueType(), LHS, RHS, CC, dl, LHS, RHS);
5686
5687 // If softenSetCCOperands only returned one value, we should compare it to
5688 // zero.
5689 if (!RHS.getNode()) {
5690 RHS = DAG.getConstant(0, dl, LHS.getValueType());
5691 CC = ISD::SETNE;
5692 }
5693 }
5694
5695 // Optimize {s|u}{add|sub|mul}.with.overflow feeding into a branch
5696 // instruction.
5697 unsigned Opc = LHS.getOpcode();
5698 bool OptimizeMul = (Opc == ISD::SMULO || Opc == ISD::UMULO) &&
5699 !Subtarget->isThumb1Only();
5700 if (LHS.getResNo() == 1 && (isOneConstant(RHS) || isNullConstant(RHS)) &&
5701 (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO ||
5702 Opc == ISD::USUBO || OptimizeMul) &&
5703 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
5704 // Only lower legal XALUO ops.
5705 if (!DAG.getTargetLoweringInfo().isTypeLegal(LHS->getValueType(0)))
5706 return SDValue();
5707
5708 // The actual operation with overflow check.
5709 SDValue Value, OverflowCmp;
5710 SDValue ARMcc;
5711 std::tie(Value, OverflowCmp) = getARMXALUOOp(LHS.getValue(0), DAG, ARMcc);
5712
5713 if ((CC == ISD::SETNE) != isOneConstant(RHS)) {
5714 // Reverse the condition code.
5715 ARMCC::CondCodes CondCode =
5716 (ARMCC::CondCodes)cast<const ConstantSDNode>(ARMcc)->getZExtValue();
5717 CondCode = ARMCC::getOppositeCondition(CondCode);
5718 ARMcc = DAG.getConstant(CondCode, SDLoc(ARMcc), MVT::i32);
5719 }
5720 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
5721
5722 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other, Chain, Dest, ARMcc, CCR,
5723 OverflowCmp);
5724 }
5725
5726 if (LHS.getValueType() == MVT::i32) {
5727 SDValue ARMcc;
5728 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
5729 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
5730 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other,
5731 Chain, Dest, ARMcc, CCR, Cmp);
5732 }
5733
5734 if (getTargetMachine().Options.UnsafeFPMath &&
5735 (CC == ISD::SETEQ || CC == ISD::SETOEQ ||
5736 CC == ISD::SETNE || CC == ISD::SETUNE)) {
5737 if (SDValue Result = OptimizeVFPBrcond(Op, DAG))
5738 return Result;
5739 }
5740
5741 ARMCC::CondCodes CondCode, CondCode2;
5742 FPCCToARMCC(CC, CondCode, CondCode2);
5743
5744 SDValue ARMcc = DAG.getConstant(CondCode, dl, MVT::i32);
5745 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
5746 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
5747 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Glue);
5748 SDValue Ops[] = { Chain, Dest, ARMcc, CCR, Cmp };
5749 SDValue Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops);
5750 if (CondCode2 != ARMCC::AL) {
5751 ARMcc = DAG.getConstant(CondCode2, dl, MVT::i32);
5752 SDValue Ops[] = { Res, Dest, ARMcc, CCR, Res.getValue(1) };
5753 Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops);
5754 }
5755 return Res;
5756}
5757
5758SDValue ARMTargetLowering::LowerBR_JT(SDValue Op, SelectionDAG &DAG) const {
5759 SDValue Chain = Op.getOperand(0);
5760 SDValue Table = Op.getOperand(1);
5761 SDValue Index = Op.getOperand(2);
5762 SDLoc dl(Op);
5763
5764 EVT PTy = getPointerTy(DAG.getDataLayout());
5765 JumpTableSDNode *JT = cast<JumpTableSDNode>(Table);
5766 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PTy);
5767 Table = DAG.getNode(ARMISD::WrapperJT, dl, MVT::i32, JTI);
5768 Index = DAG.getNode(ISD::MUL, dl, PTy, Index, DAG.getConstant(4, dl, PTy));
5769 SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Table, Index);
5770 if (Subtarget->isThumb2() || (Subtarget->hasV8MBaselineOps() && Subtarget->isThumb())) {
5771 // Thumb2 and ARMv8-M use a two-level jump. That is, it jumps into the jump table
5772 // which does another jump to the destination. This also makes it easier
5773 // to translate it to TBB / TBH later (Thumb2 only).
5774 // FIXME: This might not work if the function is extremely large.
5775 return DAG.getNode(ARMISD::BR2_JT, dl, MVT::Other, Chain,
5776 Addr, Op.getOperand(2), JTI);
5777 }
5778 if (isPositionIndependent() || Subtarget->isROPI()) {
5779 Addr =
5780 DAG.getLoad((EVT)MVT::i32, dl, Chain, Addr,
5781 MachinePointerInfo::getJumpTable(DAG.getMachineFunction()));
5782 Chain = Addr.getValue(1);
5783 Addr = DAG.getNode(ISD::ADD, dl, PTy, Table, Addr);
5784 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI);
5785 } else {
5786 Addr =
5787 DAG.getLoad(PTy, dl, Chain, Addr,
5788 MachinePointerInfo::getJumpTable(DAG.getMachineFunction()));
5789 Chain = Addr.getValue(1);
5790 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI);
5791 }
5792}
5793
5794static SDValue LowerVectorFP_TO_INT(SDValue Op, SelectionDAG &DAG) {
5795 EVT VT = Op.getValueType();
5796 SDLoc dl(Op);
5797
5798 if (Op.getValueType().getVectorElementType() == MVT::i32) {
5799 if (Op.getOperand(0).getValueType().getVectorElementType() == MVT::f32)
5800 return Op;
5801 return DAG.UnrollVectorOp(Op.getNode());
5802 }
5803
5804 const bool HasFullFP16 =
5805 static_cast<const ARMSubtarget&>(DAG.getSubtarget()).hasFullFP16();
5806
5807 EVT NewTy;
5808 const EVT OpTy = Op.getOperand(0).getValueType();
5809 if (OpTy == MVT::v4f32)
5810 NewTy = MVT::v4i32;
5811 else if (OpTy == MVT::v4f16 && HasFullFP16)
5812 NewTy = MVT::v4i16;
5813 else if (OpTy == MVT::v8f16 && HasFullFP16)
5814 NewTy = MVT::v8i16;
5815 else
5816 llvm_unreachable("Invalid type for custom lowering!")::llvm::llvm_unreachable_internal("Invalid type for custom lowering!"
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 5816)
;
5817
5818 if (VT != MVT::v4i16 && VT != MVT::v8i16)
5819 return DAG.UnrollVectorOp(Op.getNode());
5820
5821 Op = DAG.getNode(Op.getOpcode(), dl, NewTy, Op.getOperand(0));
5822 return DAG.getNode(ISD::TRUNCATE, dl, VT, Op);
5823}
5824
5825SDValue ARMTargetLowering::LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) const {
5826 EVT VT = Op.getValueType();
5827 if (VT.isVector())
5828 return LowerVectorFP_TO_INT(Op, DAG);
5829
5830 bool IsStrict = Op->isStrictFPOpcode();
5831 SDValue SrcVal = Op.getOperand(IsStrict ? 1 : 0);
5832
5833 if (isUnsupportedFloatingType(SrcVal.getValueType())) {
5834 RTLIB::Libcall LC;
5835 if (Op.getOpcode() == ISD::FP_TO_SINT ||
5836 Op.getOpcode() == ISD::STRICT_FP_TO_SINT)
5837 LC = RTLIB::getFPTOSINT(SrcVal.getValueType(),
5838 Op.getValueType());
5839 else
5840 LC = RTLIB::getFPTOUINT(SrcVal.getValueType(),
5841 Op.getValueType());
5842 SDLoc Loc(Op);
5843 MakeLibCallOptions CallOptions;
5844 SDValue Chain = IsStrict ? Op.getOperand(0) : SDValue();
5845 SDValue Result;
5846 std::tie(Result, Chain) = makeLibCall(DAG, LC, Op.getValueType(), SrcVal,
5847 CallOptions, Loc, Chain);
5848 return IsStrict ? DAG.getMergeValues({Result, Chain}, Loc) : Result;
5849 }
5850
5851 // FIXME: Remove this when we have strict fp instruction selection patterns
5852 if (IsStrict) {
5853 SDLoc Loc(Op);
5854 SDValue Result =
5855 DAG.getNode(Op.getOpcode() == ISD::STRICT_FP_TO_SINT ? ISD::FP_TO_SINT
5856 : ISD::FP_TO_UINT,
5857 Loc, Op.getValueType(), SrcVal);
5858 return DAG.getMergeValues({Result, Op.getOperand(0)}, Loc);
5859 }
5860
5861 return Op;
5862}
5863
5864static SDValue LowerFP_TO_INT_SAT(SDValue Op, SelectionDAG &DAG,
5865 const ARMSubtarget *Subtarget) {
5866 EVT VT = Op.getValueType();
5867 EVT ToVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
5868 EVT FromVT = Op.getOperand(0).getValueType();
5869
5870 if (VT == MVT::i32 && ToVT == MVT::i32 && FromVT == MVT::f32)
5871 return Op;
5872 if (VT == MVT::i32 && ToVT == MVT::i32 && FromVT == MVT::f64 &&
5873 Subtarget->hasFP64())
5874 return Op;
5875 if (VT == MVT::i32 && ToVT == MVT::i32 && FromVT == MVT::f16 &&
5876 Subtarget->hasFullFP16())
5877 return Op;
5878 if (VT == MVT::v4i32 && ToVT == MVT::i32 && FromVT == MVT::v4f32 &&
5879 Subtarget->hasMVEFloatOps())
5880 return Op;
5881 if (VT == MVT::v8i16 && ToVT == MVT::i16 && FromVT == MVT::v8f16 &&
5882 Subtarget->hasMVEFloatOps())
5883 return Op;
5884
5885 if (FromVT != MVT::v4f32 && FromVT != MVT::v8f16)
5886 return SDValue();
5887
5888 SDLoc DL(Op);
5889 bool IsSigned = Op.getOpcode() == ISD::FP_TO_SINT_SAT;
5890 unsigned BW = ToVT.getScalarSizeInBits() - IsSigned;
5891 SDValue CVT = DAG.getNode(Op.getOpcode(), DL, VT, Op.getOperand(0),
5892 DAG.getValueType(VT.getScalarType()));
5893 SDValue Max = DAG.getNode(IsSigned ? ISD::SMIN : ISD::UMIN, DL, VT, CVT,
5894 DAG.getConstant((1 << BW) - 1, DL, VT));
5895 if (IsSigned)
5896 Max = DAG.getNode(ISD::SMAX, DL, VT, Max,
5897 DAG.getConstant(-(1 << BW), DL, VT));
5898 return Max;
5899}
5900
5901static SDValue LowerVectorINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
5902 EVT VT = Op.getValueType();
5903 SDLoc dl(Op);
5904
5905 if (Op.getOperand(0).getValueType().getVectorElementType() == MVT::i32) {
5906 if (VT.getVectorElementType() == MVT::f32)
5907 return Op;
5908 return DAG.UnrollVectorOp(Op.getNode());
5909 }
5910
5911 assert((Op.getOperand(0).getValueType() == MVT::v4i16 ||(static_cast <bool> ((Op.getOperand(0).getValueType() ==
MVT::v4i16 || Op.getOperand(0).getValueType() == MVT::v8i16)
&& "Invalid type for custom lowering!") ? void (0) :
__assert_fail ("(Op.getOperand(0).getValueType() == MVT::v4i16 || Op.getOperand(0).getValueType() == MVT::v8i16) && \"Invalid type for custom lowering!\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 5913, __extension__
__PRETTY_FUNCTION__))
5912 Op.getOperand(0).getValueType() == MVT::v8i16) &&(static_cast <bool> ((Op.getOperand(0).getValueType() ==
MVT::v4i16 || Op.getOperand(0).getValueType() == MVT::v8i16)
&& "Invalid type for custom lowering!") ? void (0) :
__assert_fail ("(Op.getOperand(0).getValueType() == MVT::v4i16 || Op.getOperand(0).getValueType() == MVT::v8i16) && \"Invalid type for custom lowering!\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 5913, __extension__
__PRETTY_FUNCTION__))
5913 "Invalid type for custom lowering!")(static_cast <bool> ((Op.getOperand(0).getValueType() ==
MVT::v4i16 || Op.getOperand(0).getValueType() == MVT::v8i16)
&& "Invalid type for custom lowering!") ? void (0) :
__assert_fail ("(Op.getOperand(0).getValueType() == MVT::v4i16 || Op.getOperand(0).getValueType() == MVT::v8i16) && \"Invalid type for custom lowering!\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 5913, __extension__
__PRETTY_FUNCTION__))
;
5914
5915 const bool HasFullFP16 =
5916 static_cast<const ARMSubtarget&>(DAG.getSubtarget()).hasFullFP16();
5917
5918 EVT DestVecType;
5919 if (VT == MVT::v4f32)
5920 DestVecType = MVT::v4i32;
5921 else if (VT == MVT::v4f16 && HasFullFP16)
5922 DestVecType = MVT::v4i16;
5923 else if (VT == MVT::v8f16 && HasFullFP16)
5924 DestVecType = MVT::v8i16;
5925 else
5926 return DAG.UnrollVectorOp(Op.getNode());
5927
5928 unsigned CastOpc;
5929 unsigned Opc;
5930 switch (Op.getOpcode()) {
5931 default: llvm_unreachable("Invalid opcode!")::llvm::llvm_unreachable_internal("Invalid opcode!", "llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 5931)
;
5932 case ISD::SINT_TO_FP:
5933 CastOpc = ISD::SIGN_EXTEND;
5934 Opc = ISD::SINT_TO_FP;
5935 break;
5936 case ISD::UINT_TO_FP:
5937 CastOpc = ISD::ZERO_EXTEND;
5938 Opc = ISD::UINT_TO_FP;
5939 break;
5940 }
5941
5942 Op = DAG.getNode(CastOpc, dl, DestVecType, Op.getOperand(0));
5943 return DAG.getNode(Opc, dl, VT, Op);
5944}
5945
5946SDValue ARMTargetLowering::LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) const {
5947 EVT VT = Op.getValueType();
5948 if (VT.isVector())
5949 return LowerVectorINT_TO_FP(Op, DAG);
5950 if (isUnsupportedFloatingType(VT)) {
5951 RTLIB::Libcall LC;
5952 if (Op.getOpcode() == ISD::SINT_TO_FP)
5953 LC = RTLIB::getSINTTOFP(Op.getOperand(0).getValueType(),
5954 Op.getValueType());
5955 else
5956 LC = RTLIB::getUINTTOFP(Op.getOperand(0).getValueType(),
5957 Op.getValueType());
5958 MakeLibCallOptions CallOptions;
5959 return makeLibCall(DAG, LC, Op.getValueType(), Op.getOperand(0),
5960 CallOptions, SDLoc(Op)).first;
5961 }
5962
5963 return Op;
5964}
5965
5966SDValue ARMTargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
5967 // Implement fcopysign with a fabs and a conditional fneg.
5968 SDValue Tmp0 = Op.getOperand(0);
5969 SDValue Tmp1 = Op.getOperand(1);
5970 SDLoc dl(Op);
5971 EVT VT = Op.getValueType();
5972 EVT SrcVT = Tmp1.getValueType();
5973 bool InGPR = Tmp0.getOpcode() == ISD::BITCAST ||
5974 Tmp0.getOpcode() == ARMISD::VMOVDRR;
5975 bool UseNEON = !InGPR && Subtarget->hasNEON();
5976
5977 if (UseNEON) {
5978 // Use VBSL to copy the sign bit.
5979 unsigned EncodedVal = ARM_AM::createVMOVModImm(0x6, 0x80);
5980 SDValue Mask = DAG.getNode(ARMISD::VMOVIMM, dl, MVT::v2i32,
5981 DAG.getTargetConstant(EncodedVal, dl, MVT::i32));
5982 EVT OpVT = (VT == MVT::f32) ? MVT::v2i32 : MVT::v1i64;
5983 if (VT == MVT::f64)
5984 Mask = DAG.getNode(ARMISD::VSHLIMM, dl, OpVT,
5985 DAG.getNode(ISD::BITCAST, dl, OpVT, Mask),
5986 DAG.getConstant(32, dl, MVT::i32));
5987 else /*if (VT == MVT::f32)*/
5988 Tmp0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f32, Tmp0);
5989 if (SrcVT == MVT::f32) {
5990 Tmp1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f32, Tmp1);
5991 if (VT == MVT::f64)
5992 Tmp1 = DAG.getNode(ARMISD::VSHLIMM, dl, OpVT,
5993 DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp1),
5994 DAG.getConstant(32, dl, MVT::i32));
5995 } else if (VT == MVT::f32)
5996 Tmp1 = DAG.getNode(ARMISD::VSHRuIMM, dl, MVT::v1i64,
5997 DAG.getNode(ISD::BITCAST, dl, MVT::v1i64, Tmp1),
5998 DAG.getConstant(32, dl, MVT::i32));
5999 Tmp0 = DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp0);
6000 Tmp1 = DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp1);
6001
6002 SDValue AllOnes = DAG.getTargetConstant(ARM_AM::createVMOVModImm(0xe, 0xff),
6003 dl, MVT::i32);
6004 AllOnes = DAG.getNode(ARMISD::VMOVIMM, dl, MVT::v8i8, AllOnes);
6005 SDValue MaskNot = DAG.getNode(ISD::XOR, dl, OpVT, Mask,
6006 DAG.getNode(ISD::BITCAST, dl, OpVT, AllOnes));
6007
6008 SDValue Res = DAG.getNode(ISD::OR, dl, OpVT,
6009 DAG.getNode(ISD::AND, dl, OpVT, Tmp1, Mask),
6010 DAG.getNode(ISD::AND, dl, OpVT, Tmp0, MaskNot));
6011 if (VT == MVT::f32) {
6012 Res = DAG.getNode(ISD::BITCAST, dl, MVT::v2f32, Res);
6013 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, Res,
6014 DAG.getConstant(0, dl, MVT::i32));
6015 } else {
6016 Res = DAG.getNode(ISD::BITCAST, dl, MVT::f64, Res);
6017 }
6018
6019 return Res;
6020 }
6021
6022 // Bitcast operand 1 to i32.
6023 if (SrcVT == MVT::f64)
6024 Tmp1 = DAG.getNode(ARMISD::VMOVRRD, dl, DAG.getVTList(MVT::i32, MVT::i32),
6025 Tmp1).getValue(1);
6026 Tmp1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Tmp1);
6027
6028 // Or in the signbit with integer operations.
6029 SDValue Mask1 = DAG.getConstant(0x80000000, dl, MVT::i32);
6030 SDValue Mask2 = DAG.getConstant(0x7fffffff, dl, MVT::i32);
6031 Tmp1 = DAG.getNode(ISD::AND, dl, MVT::i32, Tmp1, Mask1);
6032 if (VT == MVT::f32) {
6033 Tmp0 = DAG.getNode(ISD::AND, dl, MVT::i32,
6034 DAG.getNode(ISD::BITCAST, dl, MVT::i32, Tmp0), Mask2);
6035 return DAG.getNode(ISD::BITCAST, dl, MVT::f32,
6036 DAG.getNode(ISD::OR, dl, MVT::i32, Tmp0, Tmp1));
6037 }
6038
6039 // f64: Or the high part with signbit and then combine two parts.
6040 Tmp0 = DAG.getNode(ARMISD::VMOVRRD, dl, DAG.getVTList(MVT::i32, MVT::i32),
6041 Tmp0);
6042 SDValue Lo = Tmp0.getValue(0);
6043 SDValue Hi = DAG.getNode(ISD::AND, dl, MVT::i32, Tmp0.getValue(1), Mask2);
6044 Hi = DAG.getNode(ISD::OR, dl, MVT::i32, Hi, Tmp1);
6045 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
6046}
6047
6048SDValue ARMTargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const{
6049 MachineFunction &MF = DAG.getMachineFunction();
6050 MachineFrameInfo &MFI = MF.getFrameInfo();
6051 MFI.setReturnAddressIsTaken(true);
6052
6053 if (ver