Bug Summary

File:build/llvm-toolchain-snapshot-16~++20220904122748+c444af1c20b3/llvm/include/llvm/CodeGen/SelectionDAGNodes.h
Warning:line 1147, column 10
Called C++ object pointer is null

Annotated Source Code

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clang -cc1 -cc1 -triple x86_64-pc-linux-gnu -analyze -disable-free -clear-ast-before-backend -disable-llvm-verifier -discard-value-names -main-file-name ARMISelLowering.cpp -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=cplusplus -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -analyzer-config-compatibility-mode=true -mrelocation-model pic -pic-level 2 -mframe-pointer=none -fmath-errno -ffp-contract=on -fno-rounding-math -mconstructor-aliases -funwind-tables=2 -target-cpu x86-64 -tune-cpu generic -debugger-tuning=gdb -ffunction-sections -fdata-sections -fcoverage-compilation-dir=/build/llvm-toolchain-snapshot-16~++20220904122748+c444af1c20b3/build-llvm/tools/clang/stage2-bins -resource-dir /usr/lib/llvm-16/lib/clang/16.0.0 -D _DEBUG -D _GNU_SOURCE -D __STDC_CONSTANT_MACROS -D __STDC_FORMAT_MACROS -D __STDC_LIMIT_MACROS -I lib/Target/ARM -I /build/llvm-toolchain-snapshot-16~++20220904122748+c444af1c20b3/llvm/lib/Target/ARM -I include -I /build/llvm-toolchain-snapshot-16~++20220904122748+c444af1c20b3/llvm/include -D _FORTIFY_SOURCE=2 -D NDEBUG -U NDEBUG -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/10/../../../../include/c++/10 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/10/../../../../include/x86_64-linux-gnu/c++/10 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/10/../../../../include/c++/10/backward -internal-isystem /usr/lib/llvm-16/lib/clang/16.0.0/include -internal-isystem /usr/local/include -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/10/../../../../x86_64-linux-gnu/include -internal-externc-isystem /usr/include/x86_64-linux-gnu -internal-externc-isystem /include -internal-externc-isystem /usr/include -fmacro-prefix-map=/build/llvm-toolchain-snapshot-16~++20220904122748+c444af1c20b3/build-llvm/tools/clang/stage2-bins=build-llvm/tools/clang/stage2-bins -fmacro-prefix-map=/build/llvm-toolchain-snapshot-16~++20220904122748+c444af1c20b3/= -fcoverage-prefix-map=/build/llvm-toolchain-snapshot-16~++20220904122748+c444af1c20b3/build-llvm/tools/clang/stage2-bins=build-llvm/tools/clang/stage2-bins -fcoverage-prefix-map=/build/llvm-toolchain-snapshot-16~++20220904122748+c444af1c20b3/= -O2 -Wno-unused-command-line-argument -Wno-unused-parameter -Wwrite-strings -Wno-missing-field-initializers -Wno-long-long -Wno-maybe-uninitialized -Wno-class-memaccess -Wno-redundant-move -Wno-pessimizing-move -Wno-noexcept-type -Wno-comment -Wno-misleading-indentation -std=c++17 -fdeprecated-macro -fdebug-compilation-dir=/build/llvm-toolchain-snapshot-16~++20220904122748+c444af1c20b3/build-llvm/tools/clang/stage2-bins -fdebug-prefix-map=/build/llvm-toolchain-snapshot-16~++20220904122748+c444af1c20b3/build-llvm/tools/clang/stage2-bins=build-llvm/tools/clang/stage2-bins -fdebug-prefix-map=/build/llvm-toolchain-snapshot-16~++20220904122748+c444af1c20b3/= -ferror-limit 19 -fvisibility=hidden -fvisibility-inlines-hidden -stack-protector 2 -fgnuc-version=4.2.1 -fcolor-diagnostics -vectorize-loops -vectorize-slp -analyzer-output=html -analyzer-config stable-report-filename=true -faddrsig -D__GCC_HAVE_DWARF2_CFI_ASM=1 -o /tmp/scan-build-2022-09-04-125545-48738-1 -x c++ /build/llvm-toolchain-snapshot-16~++20220904122748+c444af1c20b3/llvm/lib/Target/ARM/ARMISelLowering.cpp

/build/llvm-toolchain-snapshot-16~++20220904122748+c444af1c20b3/llvm/lib/Target/ARM/ARMISelLowering.cpp

1//===- ARMISelLowering.cpp - ARM DAG Lowering Implementation --------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines the interfaces that ARM uses to lower LLVM code into a
10// selection DAG.
11//
12//===----------------------------------------------------------------------===//
13
14#include "ARMISelLowering.h"
15#include "ARMBaseInstrInfo.h"
16#include "ARMBaseRegisterInfo.h"
17#include "ARMCallingConv.h"
18#include "ARMConstantPoolValue.h"
19#include "ARMMachineFunctionInfo.h"
20#include "ARMPerfectShuffle.h"
21#include "ARMRegisterInfo.h"
22#include "ARMSelectionDAGInfo.h"
23#include "ARMSubtarget.h"
24#include "ARMTargetTransformInfo.h"
25#include "MCTargetDesc/ARMAddressingModes.h"
26#include "MCTargetDesc/ARMBaseInfo.h"
27#include "Utils/ARMBaseInfo.h"
28#include "llvm/ADT/APFloat.h"
29#include "llvm/ADT/APInt.h"
30#include "llvm/ADT/ArrayRef.h"
31#include "llvm/ADT/BitVector.h"
32#include "llvm/ADT/DenseMap.h"
33#include "llvm/ADT/STLExtras.h"
34#include "llvm/ADT/SmallPtrSet.h"
35#include "llvm/ADT/SmallVector.h"
36#include "llvm/ADT/Statistic.h"
37#include "llvm/ADT/StringExtras.h"
38#include "llvm/ADT/StringRef.h"
39#include "llvm/ADT/StringSwitch.h"
40#include "llvm/ADT/Triple.h"
41#include "llvm/ADT/Twine.h"
42#include "llvm/Analysis/VectorUtils.h"
43#include "llvm/CodeGen/CallingConvLower.h"
44#include "llvm/CodeGen/ISDOpcodes.h"
45#include "llvm/CodeGen/IntrinsicLowering.h"
46#include "llvm/CodeGen/MachineBasicBlock.h"
47#include "llvm/CodeGen/MachineConstantPool.h"
48#include "llvm/CodeGen/MachineFrameInfo.h"
49#include "llvm/CodeGen/MachineFunction.h"
50#include "llvm/CodeGen/MachineInstr.h"
51#include "llvm/CodeGen/MachineInstrBuilder.h"
52#include "llvm/CodeGen/MachineJumpTableInfo.h"
53#include "llvm/CodeGen/MachineMemOperand.h"
54#include "llvm/CodeGen/MachineOperand.h"
55#include "llvm/CodeGen/MachineRegisterInfo.h"
56#include "llvm/CodeGen/RuntimeLibcalls.h"
57#include "llvm/CodeGen/SelectionDAG.h"
58#include "llvm/CodeGen/SelectionDAGAddressAnalysis.h"
59#include "llvm/CodeGen/SelectionDAGNodes.h"
60#include "llvm/CodeGen/TargetInstrInfo.h"
61#include "llvm/CodeGen/TargetLowering.h"
62#include "llvm/CodeGen/TargetOpcodes.h"
63#include "llvm/CodeGen/TargetRegisterInfo.h"
64#include "llvm/CodeGen/TargetSubtargetInfo.h"
65#include "llvm/CodeGen/ValueTypes.h"
66#include "llvm/IR/Attributes.h"
67#include "llvm/IR/CallingConv.h"
68#include "llvm/IR/Constant.h"
69#include "llvm/IR/Constants.h"
70#include "llvm/IR/DataLayout.h"
71#include "llvm/IR/DebugLoc.h"
72#include "llvm/IR/DerivedTypes.h"
73#include "llvm/IR/Function.h"
74#include "llvm/IR/GlobalAlias.h"
75#include "llvm/IR/GlobalValue.h"
76#include "llvm/IR/GlobalVariable.h"
77#include "llvm/IR/IRBuilder.h"
78#include "llvm/IR/InlineAsm.h"
79#include "llvm/IR/Instruction.h"
80#include "llvm/IR/Instructions.h"
81#include "llvm/IR/IntrinsicInst.h"
82#include "llvm/IR/Intrinsics.h"
83#include "llvm/IR/IntrinsicsARM.h"
84#include "llvm/IR/Module.h"
85#include "llvm/IR/PatternMatch.h"
86#include "llvm/IR/Type.h"
87#include "llvm/IR/User.h"
88#include "llvm/IR/Value.h"
89#include "llvm/MC/MCInstrDesc.h"
90#include "llvm/MC/MCInstrItineraries.h"
91#include "llvm/MC/MCRegisterInfo.h"
92#include "llvm/MC/MCSchedule.h"
93#include "llvm/Support/AtomicOrdering.h"
94#include "llvm/Support/BranchProbability.h"
95#include "llvm/Support/Casting.h"
96#include "llvm/Support/CodeGen.h"
97#include "llvm/Support/CommandLine.h"
98#include "llvm/Support/Compiler.h"
99#include "llvm/Support/Debug.h"
100#include "llvm/Support/ErrorHandling.h"
101#include "llvm/Support/KnownBits.h"
102#include "llvm/Support/MachineValueType.h"
103#include "llvm/Support/MathExtras.h"
104#include "llvm/Support/raw_ostream.h"
105#include "llvm/Target/TargetMachine.h"
106#include "llvm/Target/TargetOptions.h"
107#include <algorithm>
108#include <cassert>
109#include <cstdint>
110#include <cstdlib>
111#include <iterator>
112#include <limits>
113#include <string>
114#include <tuple>
115#include <utility>
116#include <vector>
117
118using namespace llvm;
119using namespace llvm::PatternMatch;
120
121#define DEBUG_TYPE"arm-isel" "arm-isel"
122
123STATISTIC(NumTailCalls, "Number of tail calls")static llvm::Statistic NumTailCalls = {"arm-isel", "NumTailCalls"
, "Number of tail calls"}
;
124STATISTIC(NumMovwMovt, "Number of GAs materialized with movw + movt")static llvm::Statistic NumMovwMovt = {"arm-isel", "NumMovwMovt"
, "Number of GAs materialized with movw + movt"}
;
125STATISTIC(NumLoopByVals, "Number of loops generated for byval arguments")static llvm::Statistic NumLoopByVals = {"arm-isel", "NumLoopByVals"
, "Number of loops generated for byval arguments"}
;
126STATISTIC(NumConstpoolPromoted,static llvm::Statistic NumConstpoolPromoted = {"arm-isel", "NumConstpoolPromoted"
, "Number of constants with their storage promoted into constant pools"
}
127 "Number of constants with their storage promoted into constant pools")static llvm::Statistic NumConstpoolPromoted = {"arm-isel", "NumConstpoolPromoted"
, "Number of constants with their storage promoted into constant pools"
}
;
128
129static cl::opt<bool>
130ARMInterworking("arm-interworking", cl::Hidden,
131 cl::desc("Enable / disable ARM interworking (for debugging only)"),
132 cl::init(true));
133
134static cl::opt<bool> EnableConstpoolPromotion(
135 "arm-promote-constant", cl::Hidden,
136 cl::desc("Enable / disable promotion of unnamed_addr constants into "
137 "constant pools"),
138 cl::init(false)); // FIXME: set to true by default once PR32780 is fixed
139static cl::opt<unsigned> ConstpoolPromotionMaxSize(
140 "arm-promote-constant-max-size", cl::Hidden,
141 cl::desc("Maximum size of constant to promote into a constant pool"),
142 cl::init(64));
143static cl::opt<unsigned> ConstpoolPromotionMaxTotal(
144 "arm-promote-constant-max-total", cl::Hidden,
145 cl::desc("Maximum size of ALL constants to promote into a constant pool"),
146 cl::init(128));
147
148cl::opt<unsigned>
149MVEMaxSupportedInterleaveFactor("mve-max-interleave-factor", cl::Hidden,
150 cl::desc("Maximum interleave factor for MVE VLDn to generate."),
151 cl::init(2));
152
153// The APCS parameter registers.
154static const MCPhysReg GPRArgRegs[] = {
155 ARM::R0, ARM::R1, ARM::R2, ARM::R3
156};
157
158void ARMTargetLowering::addTypeForNEON(MVT VT, MVT PromotedLdStVT) {
159 if (VT != PromotedLdStVT) {
160 setOperationAction(ISD::LOAD, VT, Promote);
161 AddPromotedToType (ISD::LOAD, VT, PromotedLdStVT);
162
163 setOperationAction(ISD::STORE, VT, Promote);
164 AddPromotedToType (ISD::STORE, VT, PromotedLdStVT);
165 }
166
167 MVT ElemTy = VT.getVectorElementType();
168 if (ElemTy != MVT::f64)
169 setOperationAction(ISD::SETCC, VT, Custom);
170 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
171 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
172 if (ElemTy == MVT::i32) {
173 setOperationAction(ISD::SINT_TO_FP, VT, Custom);
174 setOperationAction(ISD::UINT_TO_FP, VT, Custom);
175 setOperationAction(ISD::FP_TO_SINT, VT, Custom);
176 setOperationAction(ISD::FP_TO_UINT, VT, Custom);
177 } else {
178 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
179 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
180 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
181 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
182 }
183 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
184 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
185 setOperationAction(ISD::CONCAT_VECTORS, VT, Legal);
186 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
187 setOperationAction(ISD::SELECT, VT, Expand);
188 setOperationAction(ISD::SELECT_CC, VT, Expand);
189 setOperationAction(ISD::VSELECT, VT, Expand);
190 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand);
191 if (VT.isInteger()) {
192 setOperationAction(ISD::SHL, VT, Custom);
193 setOperationAction(ISD::SRA, VT, Custom);
194 setOperationAction(ISD::SRL, VT, Custom);
195 }
196
197 // Neon does not support vector divide/remainder operations.
198 setOperationAction(ISD::SDIV, VT, Expand);
199 setOperationAction(ISD::UDIV, VT, Expand);
200 setOperationAction(ISD::FDIV, VT, Expand);
201 setOperationAction(ISD::SREM, VT, Expand);
202 setOperationAction(ISD::UREM, VT, Expand);
203 setOperationAction(ISD::FREM, VT, Expand);
204 setOperationAction(ISD::SDIVREM, VT, Expand);
205 setOperationAction(ISD::UDIVREM, VT, Expand);
206
207 if (!VT.isFloatingPoint() &&
208 VT != MVT::v2i64 && VT != MVT::v1i64)
209 for (auto Opcode : {ISD::ABS, ISD::SMIN, ISD::SMAX, ISD::UMIN, ISD::UMAX})
210 setOperationAction(Opcode, VT, Legal);
211 if (!VT.isFloatingPoint())
212 for (auto Opcode : {ISD::SADDSAT, ISD::UADDSAT, ISD::SSUBSAT, ISD::USUBSAT})
213 setOperationAction(Opcode, VT, Legal);
214}
215
216void ARMTargetLowering::addDRTypeForNEON(MVT VT) {
217 addRegisterClass(VT, &ARM::DPRRegClass);
218 addTypeForNEON(VT, MVT::f64);
219}
220
221void ARMTargetLowering::addQRTypeForNEON(MVT VT) {
222 addRegisterClass(VT, &ARM::DPairRegClass);
223 addTypeForNEON(VT, MVT::v2f64);
224}
225
226void ARMTargetLowering::setAllExpand(MVT VT) {
227 for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc)
228 setOperationAction(Opc, VT, Expand);
229
230 // We support these really simple operations even on types where all
231 // the actual arithmetic has to be broken down into simpler
232 // operations or turned into library calls.
233 setOperationAction(ISD::BITCAST, VT, Legal);
234 setOperationAction(ISD::LOAD, VT, Legal);
235 setOperationAction(ISD::STORE, VT, Legal);
236 setOperationAction(ISD::UNDEF, VT, Legal);
237}
238
239void ARMTargetLowering::addAllExtLoads(const MVT From, const MVT To,
240 LegalizeAction Action) {
241 setLoadExtAction(ISD::EXTLOAD, From, To, Action);
242 setLoadExtAction(ISD::ZEXTLOAD, From, To, Action);
243 setLoadExtAction(ISD::SEXTLOAD, From, To, Action);
244}
245
246void ARMTargetLowering::addMVEVectorTypes(bool HasMVEFP) {
247 const MVT IntTypes[] = { MVT::v16i8, MVT::v8i16, MVT::v4i32 };
248
249 for (auto VT : IntTypes) {
250 addRegisterClass(VT, &ARM::MQPRRegClass);
251 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
252 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
253 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
254 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
255 setOperationAction(ISD::SHL, VT, Custom);
256 setOperationAction(ISD::SRA, VT, Custom);
257 setOperationAction(ISD::SRL, VT, Custom);
258 setOperationAction(ISD::SMIN, VT, Legal);
259 setOperationAction(ISD::SMAX, VT, Legal);
260 setOperationAction(ISD::UMIN, VT, Legal);
261 setOperationAction(ISD::UMAX, VT, Legal);
262 setOperationAction(ISD::ABS, VT, Legal);
263 setOperationAction(ISD::SETCC, VT, Custom);
264 setOperationAction(ISD::MLOAD, VT, Custom);
265 setOperationAction(ISD::MSTORE, VT, Legal);
266 setOperationAction(ISD::CTLZ, VT, Legal);
267 setOperationAction(ISD::CTTZ, VT, Custom);
268 setOperationAction(ISD::BITREVERSE, VT, Legal);
269 setOperationAction(ISD::BSWAP, VT, Legal);
270 setOperationAction(ISD::SADDSAT, VT, Legal);
271 setOperationAction(ISD::UADDSAT, VT, Legal);
272 setOperationAction(ISD::SSUBSAT, VT, Legal);
273 setOperationAction(ISD::USUBSAT, VT, Legal);
274 setOperationAction(ISD::ABDS, VT, Legal);
275 setOperationAction(ISD::ABDU, VT, Legal);
276 setOperationAction(ISD::AVGFLOORS, VT, Legal);
277 setOperationAction(ISD::AVGFLOORU, VT, Legal);
278 setOperationAction(ISD::AVGCEILS, VT, Legal);
279 setOperationAction(ISD::AVGCEILU, VT, Legal);
280
281 // No native support for these.
282 setOperationAction(ISD::UDIV, VT, Expand);
283 setOperationAction(ISD::SDIV, VT, Expand);
284 setOperationAction(ISD::UREM, VT, Expand);
285 setOperationAction(ISD::SREM, VT, Expand);
286 setOperationAction(ISD::UDIVREM, VT, Expand);
287 setOperationAction(ISD::SDIVREM, VT, Expand);
288 setOperationAction(ISD::CTPOP, VT, Expand);
289 setOperationAction(ISD::SELECT, VT, Expand);
290 setOperationAction(ISD::SELECT_CC, VT, Expand);
291
292 // Vector reductions
293 setOperationAction(ISD::VECREDUCE_ADD, VT, Legal);
294 setOperationAction(ISD::VECREDUCE_SMAX, VT, Legal);
295 setOperationAction(ISD::VECREDUCE_UMAX, VT, Legal);
296 setOperationAction(ISD::VECREDUCE_SMIN, VT, Legal);
297 setOperationAction(ISD::VECREDUCE_UMIN, VT, Legal);
298 setOperationAction(ISD::VECREDUCE_MUL, VT, Custom);
299 setOperationAction(ISD::VECREDUCE_AND, VT, Custom);
300 setOperationAction(ISD::VECREDUCE_OR, VT, Custom);
301 setOperationAction(ISD::VECREDUCE_XOR, VT, Custom);
302
303 if (!HasMVEFP) {
304 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
305 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
306 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
307 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
308 } else {
309 setOperationAction(ISD::FP_TO_SINT_SAT, VT, Custom);
310 setOperationAction(ISD::FP_TO_UINT_SAT, VT, Custom);
311 }
312
313 // Pre and Post inc are supported on loads and stores
314 for (unsigned im = (unsigned)ISD::PRE_INC;
315 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
316 setIndexedLoadAction(im, VT, Legal);
317 setIndexedStoreAction(im, VT, Legal);
318 setIndexedMaskedLoadAction(im, VT, Legal);
319 setIndexedMaskedStoreAction(im, VT, Legal);
320 }
321 }
322
323 const MVT FloatTypes[] = { MVT::v8f16, MVT::v4f32 };
324 for (auto VT : FloatTypes) {
325 addRegisterClass(VT, &ARM::MQPRRegClass);
326 if (!HasMVEFP)
327 setAllExpand(VT);
328
329 // These are legal or custom whether we have MVE.fp or not
330 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
331 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
332 setOperationAction(ISD::INSERT_VECTOR_ELT, VT.getVectorElementType(), Custom);
333 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
334 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
335 setOperationAction(ISD::BUILD_VECTOR, VT.getVectorElementType(), Custom);
336 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Legal);
337 setOperationAction(ISD::SETCC, VT, Custom);
338 setOperationAction(ISD::MLOAD, VT, Custom);
339 setOperationAction(ISD::MSTORE, VT, Legal);
340 setOperationAction(ISD::SELECT, VT, Expand);
341 setOperationAction(ISD::SELECT_CC, VT, Expand);
342
343 // Pre and Post inc are supported on loads and stores
344 for (unsigned im = (unsigned)ISD::PRE_INC;
345 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
346 setIndexedLoadAction(im, VT, Legal);
347 setIndexedStoreAction(im, VT, Legal);
348 setIndexedMaskedLoadAction(im, VT, Legal);
349 setIndexedMaskedStoreAction(im, VT, Legal);
350 }
351
352 if (HasMVEFP) {
353 setOperationAction(ISD::FMINNUM, VT, Legal);
354 setOperationAction(ISD::FMAXNUM, VT, Legal);
355 setOperationAction(ISD::FROUND, VT, Legal);
356 setOperationAction(ISD::VECREDUCE_FADD, VT, Custom);
357 setOperationAction(ISD::VECREDUCE_FMUL, VT, Custom);
358 setOperationAction(ISD::VECREDUCE_FMIN, VT, Custom);
359 setOperationAction(ISD::VECREDUCE_FMAX, VT, Custom);
360
361 // No native support for these.
362 setOperationAction(ISD::FDIV, VT, Expand);
363 setOperationAction(ISD::FREM, VT, Expand);
364 setOperationAction(ISD::FSQRT, VT, Expand);
365 setOperationAction(ISD::FSIN, VT, Expand);
366 setOperationAction(ISD::FCOS, VT, Expand);
367 setOperationAction(ISD::FPOW, VT, Expand);
368 setOperationAction(ISD::FLOG, VT, Expand);
369 setOperationAction(ISD::FLOG2, VT, Expand);
370 setOperationAction(ISD::FLOG10, VT, Expand);
371 setOperationAction(ISD::FEXP, VT, Expand);
372 setOperationAction(ISD::FEXP2, VT, Expand);
373 setOperationAction(ISD::FNEARBYINT, VT, Expand);
374 }
375 }
376
377 // Custom Expand smaller than legal vector reductions to prevent false zero
378 // items being added.
379 setOperationAction(ISD::VECREDUCE_FADD, MVT::v4f16, Custom);
380 setOperationAction(ISD::VECREDUCE_FMUL, MVT::v4f16, Custom);
381 setOperationAction(ISD::VECREDUCE_FMIN, MVT::v4f16, Custom);
382 setOperationAction(ISD::VECREDUCE_FMAX, MVT::v4f16, Custom);
383 setOperationAction(ISD::VECREDUCE_FADD, MVT::v2f16, Custom);
384 setOperationAction(ISD::VECREDUCE_FMUL, MVT::v2f16, Custom);
385 setOperationAction(ISD::VECREDUCE_FMIN, MVT::v2f16, Custom);
386 setOperationAction(ISD::VECREDUCE_FMAX, MVT::v2f16, Custom);
387
388 // We 'support' these types up to bitcast/load/store level, regardless of
389 // MVE integer-only / float support. Only doing FP data processing on the FP
390 // vector types is inhibited at integer-only level.
391 const MVT LongTypes[] = { MVT::v2i64, MVT::v2f64 };
392 for (auto VT : LongTypes) {
393 addRegisterClass(VT, &ARM::MQPRRegClass);
394 setAllExpand(VT);
395 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
396 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
397 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
398 setOperationAction(ISD::VSELECT, VT, Legal);
399 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
400 }
401 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2f64, Legal);
402
403 // We can do bitwise operations on v2i64 vectors
404 setOperationAction(ISD::AND, MVT::v2i64, Legal);
405 setOperationAction(ISD::OR, MVT::v2i64, Legal);
406 setOperationAction(ISD::XOR, MVT::v2i64, Legal);
407
408 // It is legal to extload from v4i8 to v4i16 or v4i32.
409 addAllExtLoads(MVT::v8i16, MVT::v8i8, Legal);
410 addAllExtLoads(MVT::v4i32, MVT::v4i16, Legal);
411 addAllExtLoads(MVT::v4i32, MVT::v4i8, Legal);
412
413 // It is legal to sign extend from v4i8/v4i16 to v4i32 or v8i8 to v8i16.
414 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i8, Legal);
415 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i16, Legal);
416 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i32, Legal);
417 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v8i8, Legal);
418 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v8i16, Legal);
419
420 // Some truncating stores are legal too.
421 setTruncStoreAction(MVT::v4i32, MVT::v4i16, Legal);
422 setTruncStoreAction(MVT::v4i32, MVT::v4i8, Legal);
423 setTruncStoreAction(MVT::v8i16, MVT::v8i8, Legal);
424
425 // Pre and Post inc on these are legal, given the correct extends
426 for (unsigned im = (unsigned)ISD::PRE_INC;
427 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
428 for (auto VT : {MVT::v8i8, MVT::v4i8, MVT::v4i16}) {
429 setIndexedLoadAction(im, VT, Legal);
430 setIndexedStoreAction(im, VT, Legal);
431 setIndexedMaskedLoadAction(im, VT, Legal);
432 setIndexedMaskedStoreAction(im, VT, Legal);
433 }
434 }
435
436 // Predicate types
437 const MVT pTypes[] = {MVT::v16i1, MVT::v8i1, MVT::v4i1, MVT::v2i1};
438 for (auto VT : pTypes) {
439 addRegisterClass(VT, &ARM::VCCRRegClass);
440 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
441 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
442 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
443 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
444 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
445 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
446 setOperationAction(ISD::SETCC, VT, Custom);
447 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Expand);
448 setOperationAction(ISD::LOAD, VT, Custom);
449 setOperationAction(ISD::STORE, VT, Custom);
450 setOperationAction(ISD::TRUNCATE, VT, Custom);
451 setOperationAction(ISD::VSELECT, VT, Expand);
452 setOperationAction(ISD::SELECT, VT, Expand);
453 setOperationAction(ISD::SELECT_CC, VT, Expand);
454
455 if (!HasMVEFP) {
456 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
457 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
458 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
459 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
460 }
461 }
462 setOperationAction(ISD::SETCC, MVT::v2i1, Expand);
463 setOperationAction(ISD::TRUNCATE, MVT::v2i1, Expand);
464 setOperationAction(ISD::AND, MVT::v2i1, Expand);
465 setOperationAction(ISD::OR, MVT::v2i1, Expand);
466 setOperationAction(ISD::XOR, MVT::v2i1, Expand);
467 setOperationAction(ISD::SINT_TO_FP, MVT::v2i1, Expand);
468 setOperationAction(ISD::UINT_TO_FP, MVT::v2i1, Expand);
469 setOperationAction(ISD::FP_TO_SINT, MVT::v2i1, Expand);
470 setOperationAction(ISD::FP_TO_UINT, MVT::v2i1, Expand);
471
472 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i32, Custom);
473 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
474 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom);
475 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
476 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i16, Custom);
477 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i32, Custom);
478 setOperationAction(ISD::TRUNCATE, MVT::v8i32, Custom);
479 setOperationAction(ISD::TRUNCATE, MVT::v16i16, Custom);
480}
481
482ARMTargetLowering::ARMTargetLowering(const TargetMachine &TM,
483 const ARMSubtarget &STI)
484 : TargetLowering(TM), Subtarget(&STI) {
485 RegInfo = Subtarget->getRegisterInfo();
486 Itins = Subtarget->getInstrItineraryData();
487
488 setBooleanContents(ZeroOrOneBooleanContent);
489 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
490
491 if (!Subtarget->isTargetDarwin() && !Subtarget->isTargetIOS() &&
492 !Subtarget->isTargetWatchOS() && !Subtarget->isTargetDriverKit()) {
493 bool IsHFTarget = TM.Options.FloatABIType == FloatABI::Hard;
494 for (int LCID = 0; LCID < RTLIB::UNKNOWN_LIBCALL; ++LCID)
495 setLibcallCallingConv(static_cast<RTLIB::Libcall>(LCID),
496 IsHFTarget ? CallingConv::ARM_AAPCS_VFP
497 : CallingConv::ARM_AAPCS);
498 }
499
500 if (Subtarget->isTargetMachO()) {
501 // Uses VFP for Thumb libfuncs if available.
502 if (Subtarget->isThumb() && Subtarget->hasVFP2Base() &&
503 Subtarget->hasARMOps() && !Subtarget->useSoftFloat()) {
504 static const struct {
505 const RTLIB::Libcall Op;
506 const char * const Name;
507 const ISD::CondCode Cond;
508 } LibraryCalls[] = {
509 // Single-precision floating-point arithmetic.
510 { RTLIB::ADD_F32, "__addsf3vfp", ISD::SETCC_INVALID },
511 { RTLIB::SUB_F32, "__subsf3vfp", ISD::SETCC_INVALID },
512 { RTLIB::MUL_F32, "__mulsf3vfp", ISD::SETCC_INVALID },
513 { RTLIB::DIV_F32, "__divsf3vfp", ISD::SETCC_INVALID },
514
515 // Double-precision floating-point arithmetic.
516 { RTLIB::ADD_F64, "__adddf3vfp", ISD::SETCC_INVALID },
517 { RTLIB::SUB_F64, "__subdf3vfp", ISD::SETCC_INVALID },
518 { RTLIB::MUL_F64, "__muldf3vfp", ISD::SETCC_INVALID },
519 { RTLIB::DIV_F64, "__divdf3vfp", ISD::SETCC_INVALID },
520
521 // Single-precision comparisons.
522 { RTLIB::OEQ_F32, "__eqsf2vfp", ISD::SETNE },
523 { RTLIB::UNE_F32, "__nesf2vfp", ISD::SETNE },
524 { RTLIB::OLT_F32, "__ltsf2vfp", ISD::SETNE },
525 { RTLIB::OLE_F32, "__lesf2vfp", ISD::SETNE },
526 { RTLIB::OGE_F32, "__gesf2vfp", ISD::SETNE },
527 { RTLIB::OGT_F32, "__gtsf2vfp", ISD::SETNE },
528 { RTLIB::UO_F32, "__unordsf2vfp", ISD::SETNE },
529
530 // Double-precision comparisons.
531 { RTLIB::OEQ_F64, "__eqdf2vfp", ISD::SETNE },
532 { RTLIB::UNE_F64, "__nedf2vfp", ISD::SETNE },
533 { RTLIB::OLT_F64, "__ltdf2vfp", ISD::SETNE },
534 { RTLIB::OLE_F64, "__ledf2vfp", ISD::SETNE },
535 { RTLIB::OGE_F64, "__gedf2vfp", ISD::SETNE },
536 { RTLIB::OGT_F64, "__gtdf2vfp", ISD::SETNE },
537 { RTLIB::UO_F64, "__unorddf2vfp", ISD::SETNE },
538
539 // Floating-point to integer conversions.
540 // i64 conversions are done via library routines even when generating VFP
541 // instructions, so use the same ones.
542 { RTLIB::FPTOSINT_F64_I32, "__fixdfsivfp", ISD::SETCC_INVALID },
543 { RTLIB::FPTOUINT_F64_I32, "__fixunsdfsivfp", ISD::SETCC_INVALID },
544 { RTLIB::FPTOSINT_F32_I32, "__fixsfsivfp", ISD::SETCC_INVALID },
545 { RTLIB::FPTOUINT_F32_I32, "__fixunssfsivfp", ISD::SETCC_INVALID },
546
547 // Conversions between floating types.
548 { RTLIB::FPROUND_F64_F32, "__truncdfsf2vfp", ISD::SETCC_INVALID },
549 { RTLIB::FPEXT_F32_F64, "__extendsfdf2vfp", ISD::SETCC_INVALID },
550
551 // Integer to floating-point conversions.
552 // i64 conversions are done via library routines even when generating VFP
553 // instructions, so use the same ones.
554 // FIXME: There appears to be some naming inconsistency in ARM libgcc:
555 // e.g., __floatunsidf vs. __floatunssidfvfp.
556 { RTLIB::SINTTOFP_I32_F64, "__floatsidfvfp", ISD::SETCC_INVALID },
557 { RTLIB::UINTTOFP_I32_F64, "__floatunssidfvfp", ISD::SETCC_INVALID },
558 { RTLIB::SINTTOFP_I32_F32, "__floatsisfvfp", ISD::SETCC_INVALID },
559 { RTLIB::UINTTOFP_I32_F32, "__floatunssisfvfp", ISD::SETCC_INVALID },
560 };
561
562 for (const auto &LC : LibraryCalls) {
563 setLibcallName(LC.Op, LC.Name);
564 if (LC.Cond != ISD::SETCC_INVALID)
565 setCmpLibcallCC(LC.Op, LC.Cond);
566 }
567 }
568 }
569
570 // These libcalls are not available in 32-bit.
571 setLibcallName(RTLIB::SHL_I128, nullptr);
572 setLibcallName(RTLIB::SRL_I128, nullptr);
573 setLibcallName(RTLIB::SRA_I128, nullptr);
574 setLibcallName(RTLIB::MUL_I128, nullptr);
575 setLibcallName(RTLIB::MULO_I64, nullptr);
576 setLibcallName(RTLIB::MULO_I128, nullptr);
577
578 // RTLIB
579 if (Subtarget->isAAPCS_ABI() &&
580 (Subtarget->isTargetAEABI() || Subtarget->isTargetGNUAEABI() ||
581 Subtarget->isTargetMuslAEABI() || Subtarget->isTargetAndroid())) {
582 static const struct {
583 const RTLIB::Libcall Op;
584 const char * const Name;
585 const CallingConv::ID CC;
586 const ISD::CondCode Cond;
587 } LibraryCalls[] = {
588 // Double-precision floating-point arithmetic helper functions
589 // RTABI chapter 4.1.2, Table 2
590 { RTLIB::ADD_F64, "__aeabi_dadd", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
591 { RTLIB::DIV_F64, "__aeabi_ddiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
592 { RTLIB::MUL_F64, "__aeabi_dmul", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
593 { RTLIB::SUB_F64, "__aeabi_dsub", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
594
595 // Double-precision floating-point comparison helper functions
596 // RTABI chapter 4.1.2, Table 3
597 { RTLIB::OEQ_F64, "__aeabi_dcmpeq", CallingConv::ARM_AAPCS, ISD::SETNE },
598 { RTLIB::UNE_F64, "__aeabi_dcmpeq", CallingConv::ARM_AAPCS, ISD::SETEQ },
599 { RTLIB::OLT_F64, "__aeabi_dcmplt", CallingConv::ARM_AAPCS, ISD::SETNE },
600 { RTLIB::OLE_F64, "__aeabi_dcmple", CallingConv::ARM_AAPCS, ISD::SETNE },
601 { RTLIB::OGE_F64, "__aeabi_dcmpge", CallingConv::ARM_AAPCS, ISD::SETNE },
602 { RTLIB::OGT_F64, "__aeabi_dcmpgt", CallingConv::ARM_AAPCS, ISD::SETNE },
603 { RTLIB::UO_F64, "__aeabi_dcmpun", CallingConv::ARM_AAPCS, ISD::SETNE },
604
605 // Single-precision floating-point arithmetic helper functions
606 // RTABI chapter 4.1.2, Table 4
607 { RTLIB::ADD_F32, "__aeabi_fadd", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
608 { RTLIB::DIV_F32, "__aeabi_fdiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
609 { RTLIB::MUL_F32, "__aeabi_fmul", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
610 { RTLIB::SUB_F32, "__aeabi_fsub", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
611
612 // Single-precision floating-point comparison helper functions
613 // RTABI chapter 4.1.2, Table 5
614 { RTLIB::OEQ_F32, "__aeabi_fcmpeq", CallingConv::ARM_AAPCS, ISD::SETNE },
615 { RTLIB::UNE_F32, "__aeabi_fcmpeq", CallingConv::ARM_AAPCS, ISD::SETEQ },
616 { RTLIB::OLT_F32, "__aeabi_fcmplt", CallingConv::ARM_AAPCS, ISD::SETNE },
617 { RTLIB::OLE_F32, "__aeabi_fcmple", CallingConv::ARM_AAPCS, ISD::SETNE },
618 { RTLIB::OGE_F32, "__aeabi_fcmpge", CallingConv::ARM_AAPCS, ISD::SETNE },
619 { RTLIB::OGT_F32, "__aeabi_fcmpgt", CallingConv::ARM_AAPCS, ISD::SETNE },
620 { RTLIB::UO_F32, "__aeabi_fcmpun", CallingConv::ARM_AAPCS, ISD::SETNE },
621
622 // Floating-point to integer conversions.
623 // RTABI chapter 4.1.2, Table 6
624 { RTLIB::FPTOSINT_F64_I32, "__aeabi_d2iz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
625 { RTLIB::FPTOUINT_F64_I32, "__aeabi_d2uiz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
626 { RTLIB::FPTOSINT_F64_I64, "__aeabi_d2lz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
627 { RTLIB::FPTOUINT_F64_I64, "__aeabi_d2ulz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
628 { RTLIB::FPTOSINT_F32_I32, "__aeabi_f2iz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
629 { RTLIB::FPTOUINT_F32_I32, "__aeabi_f2uiz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
630 { RTLIB::FPTOSINT_F32_I64, "__aeabi_f2lz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
631 { RTLIB::FPTOUINT_F32_I64, "__aeabi_f2ulz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
632
633 // Conversions between floating types.
634 // RTABI chapter 4.1.2, Table 7
635 { RTLIB::FPROUND_F64_F32, "__aeabi_d2f", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
636 { RTLIB::FPROUND_F64_F16, "__aeabi_d2h", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
637 { RTLIB::FPEXT_F32_F64, "__aeabi_f2d", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
638
639 // Integer to floating-point conversions.
640 // RTABI chapter 4.1.2, Table 8
641 { RTLIB::SINTTOFP_I32_F64, "__aeabi_i2d", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
642 { RTLIB::UINTTOFP_I32_F64, "__aeabi_ui2d", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
643 { RTLIB::SINTTOFP_I64_F64, "__aeabi_l2d", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
644 { RTLIB::UINTTOFP_I64_F64, "__aeabi_ul2d", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
645 { RTLIB::SINTTOFP_I32_F32, "__aeabi_i2f", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
646 { RTLIB::UINTTOFP_I32_F32, "__aeabi_ui2f", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
647 { RTLIB::SINTTOFP_I64_F32, "__aeabi_l2f", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
648 { RTLIB::UINTTOFP_I64_F32, "__aeabi_ul2f", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
649
650 // Long long helper functions
651 // RTABI chapter 4.2, Table 9
652 { RTLIB::MUL_I64, "__aeabi_lmul", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
653 { RTLIB::SHL_I64, "__aeabi_llsl", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
654 { RTLIB::SRL_I64, "__aeabi_llsr", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
655 { RTLIB::SRA_I64, "__aeabi_lasr", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
656
657 // Integer division functions
658 // RTABI chapter 4.3.1
659 { RTLIB::SDIV_I8, "__aeabi_idiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
660 { RTLIB::SDIV_I16, "__aeabi_idiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
661 { RTLIB::SDIV_I32, "__aeabi_idiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
662 { RTLIB::SDIV_I64, "__aeabi_ldivmod", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
663 { RTLIB::UDIV_I8, "__aeabi_uidiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
664 { RTLIB::UDIV_I16, "__aeabi_uidiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
665 { RTLIB::UDIV_I32, "__aeabi_uidiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
666 { RTLIB::UDIV_I64, "__aeabi_uldivmod", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
667 };
668
669 for (const auto &LC : LibraryCalls) {
670 setLibcallName(LC.Op, LC.Name);
671 setLibcallCallingConv(LC.Op, LC.CC);
672 if (LC.Cond != ISD::SETCC_INVALID)
673 setCmpLibcallCC(LC.Op, LC.Cond);
674 }
675
676 // EABI dependent RTLIB
677 if (TM.Options.EABIVersion == EABI::EABI4 ||
678 TM.Options.EABIVersion == EABI::EABI5) {
679 static const struct {
680 const RTLIB::Libcall Op;
681 const char *const Name;
682 const CallingConv::ID CC;
683 const ISD::CondCode Cond;
684 } MemOpsLibraryCalls[] = {
685 // Memory operations
686 // RTABI chapter 4.3.4
687 { RTLIB::MEMCPY, "__aeabi_memcpy", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
688 { RTLIB::MEMMOVE, "__aeabi_memmove", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
689 { RTLIB::MEMSET, "__aeabi_memset", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
690 };
691
692 for (const auto &LC : MemOpsLibraryCalls) {
693 setLibcallName(LC.Op, LC.Name);
694 setLibcallCallingConv(LC.Op, LC.CC);
695 if (LC.Cond != ISD::SETCC_INVALID)
696 setCmpLibcallCC(LC.Op, LC.Cond);
697 }
698 }
699 }
700
701 if (Subtarget->isTargetWindows()) {
702 static const struct {
703 const RTLIB::Libcall Op;
704 const char * const Name;
705 const CallingConv::ID CC;
706 } LibraryCalls[] = {
707 { RTLIB::FPTOSINT_F32_I64, "__stoi64", CallingConv::ARM_AAPCS_VFP },
708 { RTLIB::FPTOSINT_F64_I64, "__dtoi64", CallingConv::ARM_AAPCS_VFP },
709 { RTLIB::FPTOUINT_F32_I64, "__stou64", CallingConv::ARM_AAPCS_VFP },
710 { RTLIB::FPTOUINT_F64_I64, "__dtou64", CallingConv::ARM_AAPCS_VFP },
711 { RTLIB::SINTTOFP_I64_F32, "__i64tos", CallingConv::ARM_AAPCS_VFP },
712 { RTLIB::SINTTOFP_I64_F64, "__i64tod", CallingConv::ARM_AAPCS_VFP },
713 { RTLIB::UINTTOFP_I64_F32, "__u64tos", CallingConv::ARM_AAPCS_VFP },
714 { RTLIB::UINTTOFP_I64_F64, "__u64tod", CallingConv::ARM_AAPCS_VFP },
715 };
716
717 for (const auto &LC : LibraryCalls) {
718 setLibcallName(LC.Op, LC.Name);
719 setLibcallCallingConv(LC.Op, LC.CC);
720 }
721 }
722
723 // Use divmod compiler-rt calls for iOS 5.0 and later.
724 if (Subtarget->isTargetMachO() &&
725 !(Subtarget->isTargetIOS() &&
726 Subtarget->getTargetTriple().isOSVersionLT(5, 0))) {
727 setLibcallName(RTLIB::SDIVREM_I32, "__divmodsi4");
728 setLibcallName(RTLIB::UDIVREM_I32, "__udivmodsi4");
729 }
730
731 // The half <-> float conversion functions are always soft-float on
732 // non-watchos platforms, but are needed for some targets which use a
733 // hard-float calling convention by default.
734 if (!Subtarget->isTargetWatchABI()) {
735 if (Subtarget->isAAPCS_ABI()) {
736 setLibcallCallingConv(RTLIB::FPROUND_F32_F16, CallingConv::ARM_AAPCS);
737 setLibcallCallingConv(RTLIB::FPROUND_F64_F16, CallingConv::ARM_AAPCS);
738 setLibcallCallingConv(RTLIB::FPEXT_F16_F32, CallingConv::ARM_AAPCS);
739 } else {
740 setLibcallCallingConv(RTLIB::FPROUND_F32_F16, CallingConv::ARM_APCS);
741 setLibcallCallingConv(RTLIB::FPROUND_F64_F16, CallingConv::ARM_APCS);
742 setLibcallCallingConv(RTLIB::FPEXT_F16_F32, CallingConv::ARM_APCS);
743 }
744 }
745
746 // In EABI, these functions have an __aeabi_ prefix, but in GNUEABI they have
747 // a __gnu_ prefix (which is the default).
748 if (Subtarget->isTargetAEABI()) {
749 static const struct {
750 const RTLIB::Libcall Op;
751 const char * const Name;
752 const CallingConv::ID CC;
753 } LibraryCalls[] = {
754 { RTLIB::FPROUND_F32_F16, "__aeabi_f2h", CallingConv::ARM_AAPCS },
755 { RTLIB::FPROUND_F64_F16, "__aeabi_d2h", CallingConv::ARM_AAPCS },
756 { RTLIB::FPEXT_F16_F32, "__aeabi_h2f", CallingConv::ARM_AAPCS },
757 };
758
759 for (const auto &LC : LibraryCalls) {
760 setLibcallName(LC.Op, LC.Name);
761 setLibcallCallingConv(LC.Op, LC.CC);
762 }
763 }
764
765 if (Subtarget->isThumb1Only())
766 addRegisterClass(MVT::i32, &ARM::tGPRRegClass);
767 else
768 addRegisterClass(MVT::i32, &ARM::GPRRegClass);
769
770 if (!Subtarget->useSoftFloat() && !Subtarget->isThumb1Only() &&
771 Subtarget->hasFPRegs()) {
772 addRegisterClass(MVT::f32, &ARM::SPRRegClass);
773 addRegisterClass(MVT::f64, &ARM::DPRRegClass);
774
775 setOperationAction(ISD::FP_TO_SINT_SAT, MVT::i32, Custom);
776 setOperationAction(ISD::FP_TO_UINT_SAT, MVT::i32, Custom);
777 setOperationAction(ISD::FP_TO_SINT_SAT, MVT::i64, Custom);
778 setOperationAction(ISD::FP_TO_UINT_SAT, MVT::i64, Custom);
779
780 if (!Subtarget->hasVFP2Base())
781 setAllExpand(MVT::f32);
782 if (!Subtarget->hasFP64())
783 setAllExpand(MVT::f64);
784 }
785
786 if (Subtarget->hasFullFP16()) {
787 addRegisterClass(MVT::f16, &ARM::HPRRegClass);
788 setOperationAction(ISD::BITCAST, MVT::i16, Custom);
789 setOperationAction(ISD::BITCAST, MVT::f16, Custom);
790
791 setOperationAction(ISD::FMINNUM, MVT::f16, Legal);
792 setOperationAction(ISD::FMAXNUM, MVT::f16, Legal);
793 }
794
795 if (Subtarget->hasBF16()) {
796 addRegisterClass(MVT::bf16, &ARM::HPRRegClass);
797 setAllExpand(MVT::bf16);
798 if (!Subtarget->hasFullFP16())
799 setOperationAction(ISD::BITCAST, MVT::bf16, Custom);
800 }
801
802 for (MVT VT : MVT::fixedlen_vector_valuetypes()) {
803 for (MVT InnerVT : MVT::fixedlen_vector_valuetypes()) {
804 setTruncStoreAction(VT, InnerVT, Expand);
805 addAllExtLoads(VT, InnerVT, Expand);
806 }
807
808 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
809 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
810
811 setOperationAction(ISD::BSWAP, VT, Expand);
812 }
813
814 setOperationAction(ISD::ConstantFP, MVT::f32, Custom);
815 setOperationAction(ISD::ConstantFP, MVT::f64, Custom);
816
817 setOperationAction(ISD::READ_REGISTER, MVT::i64, Custom);
818 setOperationAction(ISD::WRITE_REGISTER, MVT::i64, Custom);
819
820 if (Subtarget->hasMVEIntegerOps())
821 addMVEVectorTypes(Subtarget->hasMVEFloatOps());
822
823 // Combine low-overhead loop intrinsics so that we can lower i1 types.
824 if (Subtarget->hasLOB()) {
825 setTargetDAGCombine({ISD::BRCOND, ISD::BR_CC});
826 }
827
828 if (Subtarget->hasNEON()) {
829 addDRTypeForNEON(MVT::v2f32);
830 addDRTypeForNEON(MVT::v8i8);
831 addDRTypeForNEON(MVT::v4i16);
832 addDRTypeForNEON(MVT::v2i32);
833 addDRTypeForNEON(MVT::v1i64);
834
835 addQRTypeForNEON(MVT::v4f32);
836 addQRTypeForNEON(MVT::v2f64);
837 addQRTypeForNEON(MVT::v16i8);
838 addQRTypeForNEON(MVT::v8i16);
839 addQRTypeForNEON(MVT::v4i32);
840 addQRTypeForNEON(MVT::v2i64);
841
842 if (Subtarget->hasFullFP16()) {
843 addQRTypeForNEON(MVT::v8f16);
844 addDRTypeForNEON(MVT::v4f16);
845 }
846
847 if (Subtarget->hasBF16()) {
848 addQRTypeForNEON(MVT::v8bf16);
849 addDRTypeForNEON(MVT::v4bf16);
850 }
851 }
852
853 if (Subtarget->hasMVEIntegerOps() || Subtarget->hasNEON()) {
854 // v2f64 is legal so that QR subregs can be extracted as f64 elements, but
855 // none of Neon, MVE or VFP supports any arithmetic operations on it.
856 setOperationAction(ISD::FADD, MVT::v2f64, Expand);
857 setOperationAction(ISD::FSUB, MVT::v2f64, Expand);
858 setOperationAction(ISD::FMUL, MVT::v2f64, Expand);
859 // FIXME: Code duplication: FDIV and FREM are expanded always, see
860 // ARMTargetLowering::addTypeForNEON method for details.
861 setOperationAction(ISD::FDIV, MVT::v2f64, Expand);
862 setOperationAction(ISD::FREM, MVT::v2f64, Expand);
863 // FIXME: Create unittest.
864 // In another words, find a way when "copysign" appears in DAG with vector
865 // operands.
866 setOperationAction(ISD::FCOPYSIGN, MVT::v2f64, Expand);
867 // FIXME: Code duplication: SETCC has custom operation action, see
868 // ARMTargetLowering::addTypeForNEON method for details.
869 setOperationAction(ISD::SETCC, MVT::v2f64, Expand);
870 // FIXME: Create unittest for FNEG and for FABS.
871 setOperationAction(ISD::FNEG, MVT::v2f64, Expand);
872 setOperationAction(ISD::FABS, MVT::v2f64, Expand);
873 setOperationAction(ISD::FSQRT, MVT::v2f64, Expand);
874 setOperationAction(ISD::FSIN, MVT::v2f64, Expand);
875 setOperationAction(ISD::FCOS, MVT::v2f64, Expand);
876 setOperationAction(ISD::FPOW, MVT::v2f64, Expand);
877 setOperationAction(ISD::FLOG, MVT::v2f64, Expand);
878 setOperationAction(ISD::FLOG2, MVT::v2f64, Expand);
879 setOperationAction(ISD::FLOG10, MVT::v2f64, Expand);
880 setOperationAction(ISD::FEXP, MVT::v2f64, Expand);
881 setOperationAction(ISD::FEXP2, MVT::v2f64, Expand);
882 // FIXME: Create unittest for FCEIL, FTRUNC, FRINT, FNEARBYINT, FFLOOR.
883 setOperationAction(ISD::FCEIL, MVT::v2f64, Expand);
884 setOperationAction(ISD::FTRUNC, MVT::v2f64, Expand);
885 setOperationAction(ISD::FRINT, MVT::v2f64, Expand);
886 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Expand);
887 setOperationAction(ISD::FFLOOR, MVT::v2f64, Expand);
888 setOperationAction(ISD::FMA, MVT::v2f64, Expand);
889 }
890
891 if (Subtarget->hasNEON()) {
892 // The same with v4f32. But keep in mind that vadd, vsub, vmul are natively
893 // supported for v4f32.
894 setOperationAction(ISD::FSQRT, MVT::v4f32, Expand);
895 setOperationAction(ISD::FSIN, MVT::v4f32, Expand);
896 setOperationAction(ISD::FCOS, MVT::v4f32, Expand);
897 setOperationAction(ISD::FPOW, MVT::v4f32, Expand);
898 setOperationAction(ISD::FLOG, MVT::v4f32, Expand);
899 setOperationAction(ISD::FLOG2, MVT::v4f32, Expand);
900 setOperationAction(ISD::FLOG10, MVT::v4f32, Expand);
901 setOperationAction(ISD::FEXP, MVT::v4f32, Expand);
902 setOperationAction(ISD::FEXP2, MVT::v4f32, Expand);
903 setOperationAction(ISD::FCEIL, MVT::v4f32, Expand);
904 setOperationAction(ISD::FTRUNC, MVT::v4f32, Expand);
905 setOperationAction(ISD::FRINT, MVT::v4f32, Expand);
906 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Expand);
907 setOperationAction(ISD::FFLOOR, MVT::v4f32, Expand);
908
909 // Mark v2f32 intrinsics.
910 setOperationAction(ISD::FSQRT, MVT::v2f32, Expand);
911 setOperationAction(ISD::FSIN, MVT::v2f32, Expand);
912 setOperationAction(ISD::FCOS, MVT::v2f32, Expand);
913 setOperationAction(ISD::FPOW, MVT::v2f32, Expand);
914 setOperationAction(ISD::FLOG, MVT::v2f32, Expand);
915 setOperationAction(ISD::FLOG2, MVT::v2f32, Expand);
916 setOperationAction(ISD::FLOG10, MVT::v2f32, Expand);
917 setOperationAction(ISD::FEXP, MVT::v2f32, Expand);
918 setOperationAction(ISD::FEXP2, MVT::v2f32, Expand);
919 setOperationAction(ISD::FCEIL, MVT::v2f32, Expand);
920 setOperationAction(ISD::FTRUNC, MVT::v2f32, Expand);
921 setOperationAction(ISD::FRINT, MVT::v2f32, Expand);
922 setOperationAction(ISD::FNEARBYINT, MVT::v2f32, Expand);
923 setOperationAction(ISD::FFLOOR, MVT::v2f32, Expand);
924
925 // Neon does not support some operations on v1i64 and v2i64 types.
926 setOperationAction(ISD::MUL, MVT::v1i64, Expand);
927 // Custom handling for some quad-vector types to detect VMULL.
928 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
929 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
930 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
931 // Custom handling for some vector types to avoid expensive expansions
932 setOperationAction(ISD::SDIV, MVT::v4i16, Custom);
933 setOperationAction(ISD::SDIV, MVT::v8i8, Custom);
934 setOperationAction(ISD::UDIV, MVT::v4i16, Custom);
935 setOperationAction(ISD::UDIV, MVT::v8i8, Custom);
936 // Neon does not have single instruction SINT_TO_FP and UINT_TO_FP with
937 // a destination type that is wider than the source, and nor does
938 // it have a FP_TO_[SU]INT instruction with a narrower destination than
939 // source.
940 setOperationAction(ISD::SINT_TO_FP, MVT::v4i16, Custom);
941 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Custom);
942 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
943 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom);
944 setOperationAction(ISD::FP_TO_UINT, MVT::v4i16, Custom);
945 setOperationAction(ISD::FP_TO_UINT, MVT::v8i16, Custom);
946 setOperationAction(ISD::FP_TO_SINT, MVT::v4i16, Custom);
947 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Custom);
948
949 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Expand);
950 setOperationAction(ISD::FP_EXTEND, MVT::v2f64, Expand);
951
952 // NEON does not have single instruction CTPOP for vectors with element
953 // types wider than 8-bits. However, custom lowering can leverage the
954 // v8i8/v16i8 vcnt instruction.
955 setOperationAction(ISD::CTPOP, MVT::v2i32, Custom);
956 setOperationAction(ISD::CTPOP, MVT::v4i32, Custom);
957 setOperationAction(ISD::CTPOP, MVT::v4i16, Custom);
958 setOperationAction(ISD::CTPOP, MVT::v8i16, Custom);
959 setOperationAction(ISD::CTPOP, MVT::v1i64, Custom);
960 setOperationAction(ISD::CTPOP, MVT::v2i64, Custom);
961
962 setOperationAction(ISD::CTLZ, MVT::v1i64, Expand);
963 setOperationAction(ISD::CTLZ, MVT::v2i64, Expand);
964
965 // NEON does not have single instruction CTTZ for vectors.
966 setOperationAction(ISD::CTTZ, MVT::v8i8, Custom);
967 setOperationAction(ISD::CTTZ, MVT::v4i16, Custom);
968 setOperationAction(ISD::CTTZ, MVT::v2i32, Custom);
969 setOperationAction(ISD::CTTZ, MVT::v1i64, Custom);
970
971 setOperationAction(ISD::CTTZ, MVT::v16i8, Custom);
972 setOperationAction(ISD::CTTZ, MVT::v8i16, Custom);
973 setOperationAction(ISD::CTTZ, MVT::v4i32, Custom);
974 setOperationAction(ISD::CTTZ, MVT::v2i64, Custom);
975
976 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v8i8, Custom);
977 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v4i16, Custom);
978 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v2i32, Custom);
979 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v1i64, Custom);
980
981 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v16i8, Custom);
982 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v8i16, Custom);
983 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v4i32, Custom);
984 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v2i64, Custom);
985
986 for (MVT VT : MVT::fixedlen_vector_valuetypes()) {
987 setOperationAction(ISD::MULHS, VT, Expand);
988 setOperationAction(ISD::MULHU, VT, Expand);
989 }
990
991 // NEON only has FMA instructions as of VFP4.
992 if (!Subtarget->hasVFP4Base()) {
993 setOperationAction(ISD::FMA, MVT::v2f32, Expand);
994 setOperationAction(ISD::FMA, MVT::v4f32, Expand);
995 }
996
997 setTargetDAGCombine({ISD::SHL, ISD::SRL, ISD::SRA, ISD::FP_TO_SINT,
998 ISD::FP_TO_UINT, ISD::FDIV, ISD::LOAD});
999
1000 // It is legal to extload from v4i8 to v4i16 or v4i32.
1001 for (MVT Ty : {MVT::v8i8, MVT::v4i8, MVT::v2i8, MVT::v4i16, MVT::v2i16,
1002 MVT::v2i32}) {
1003 for (MVT VT : MVT::integer_fixedlen_vector_valuetypes()) {
1004 setLoadExtAction(ISD::EXTLOAD, VT, Ty, Legal);
1005 setLoadExtAction(ISD::ZEXTLOAD, VT, Ty, Legal);
1006 setLoadExtAction(ISD::SEXTLOAD, VT, Ty, Legal);
1007 }
1008 }
1009 }
1010
1011 if (Subtarget->hasNEON() || Subtarget->hasMVEIntegerOps()) {
1012 setTargetDAGCombine(
1013 {ISD::BUILD_VECTOR, ISD::VECTOR_SHUFFLE, ISD::INSERT_SUBVECTOR,
1014 ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT,
1015 ISD::SIGN_EXTEND_INREG, ISD::STORE, ISD::SIGN_EXTEND, ISD::ZERO_EXTEND,
1016 ISD::ANY_EXTEND, ISD::INTRINSIC_WO_CHAIN, ISD::INTRINSIC_W_CHAIN,
1017 ISD::INTRINSIC_VOID, ISD::VECREDUCE_ADD, ISD::ADD, ISD::BITCAST});
1018 }
1019 if (Subtarget->hasMVEIntegerOps()) {
1020 setTargetDAGCombine({ISD::SMIN, ISD::UMIN, ISD::SMAX, ISD::UMAX,
1021 ISD::FP_EXTEND, ISD::SELECT, ISD::SELECT_CC,
1022 ISD::SETCC});
1023 }
1024 if (Subtarget->hasMVEFloatOps()) {
1025 setTargetDAGCombine(ISD::FADD);
1026 }
1027
1028 if (!Subtarget->hasFP64()) {
1029 // When targeting a floating-point unit with only single-precision
1030 // operations, f64 is legal for the few double-precision instructions which
1031 // are present However, no double-precision operations other than moves,
1032 // loads and stores are provided by the hardware.
1033 setOperationAction(ISD::FADD, MVT::f64, Expand);
1034 setOperationAction(ISD::FSUB, MVT::f64, Expand);
1035 setOperationAction(ISD::FMUL, MVT::f64, Expand);
1036 setOperationAction(ISD::FMA, MVT::f64, Expand);
1037 setOperationAction(ISD::FDIV, MVT::f64, Expand);
1038 setOperationAction(ISD::FREM, MVT::f64, Expand);
1039 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
1040 setOperationAction(ISD::FGETSIGN, MVT::f64, Expand);
1041 setOperationAction(ISD::FNEG, MVT::f64, Expand);
1042 setOperationAction(ISD::FABS, MVT::f64, Expand);
1043 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
1044 setOperationAction(ISD::FSIN, MVT::f64, Expand);
1045 setOperationAction(ISD::FCOS, MVT::f64, Expand);
1046 setOperationAction(ISD::FPOW, MVT::f64, Expand);
1047 setOperationAction(ISD::FLOG, MVT::f64, Expand);
1048 setOperationAction(ISD::FLOG2, MVT::f64, Expand);
1049 setOperationAction(ISD::FLOG10, MVT::f64, Expand);
1050 setOperationAction(ISD::FEXP, MVT::f64, Expand);
1051 setOperationAction(ISD::FEXP2, MVT::f64, Expand);
1052 setOperationAction(ISD::FCEIL, MVT::f64, Expand);
1053 setOperationAction(ISD::FTRUNC, MVT::f64, Expand);
1054 setOperationAction(ISD::FRINT, MVT::f64, Expand);
1055 setOperationAction(ISD::FNEARBYINT, MVT::f64, Expand);
1056 setOperationAction(ISD::FFLOOR, MVT::f64, Expand);
1057 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
1058 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
1059 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
1060 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
1061 setOperationAction(ISD::FP_TO_SINT, MVT::f64, Custom);
1062 setOperationAction(ISD::FP_TO_UINT, MVT::f64, Custom);
1063 setOperationAction(ISD::FP_ROUND, MVT::f32, Custom);
1064 setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::i32, Custom);
1065 setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::i32, Custom);
1066 setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::f64, Custom);
1067 setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::f64, Custom);
1068 setOperationAction(ISD::STRICT_FP_ROUND, MVT::f32, Custom);
1069 }
1070
1071 if (!Subtarget->hasFP64() || !Subtarget->hasFPARMv8Base()) {
1072 setOperationAction(ISD::FP_EXTEND, MVT::f64, Custom);
1073 setOperationAction(ISD::STRICT_FP_EXTEND, MVT::f64, Custom);
1074 if (Subtarget->hasFullFP16()) {
1075 setOperationAction(ISD::FP_ROUND, MVT::f16, Custom);
1076 setOperationAction(ISD::STRICT_FP_ROUND, MVT::f16, Custom);
1077 }
1078 }
1079
1080 if (!Subtarget->hasFP16()) {
1081 setOperationAction(ISD::FP_EXTEND, MVT::f32, Custom);
1082 setOperationAction(ISD::STRICT_FP_EXTEND, MVT::f32, Custom);
1083 }
1084
1085 computeRegisterProperties(Subtarget->getRegisterInfo());
1086
1087 // ARM does not have floating-point extending loads.
1088 for (MVT VT : MVT::fp_valuetypes()) {
1089 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f32, Expand);
1090 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f16, Expand);
1091 }
1092
1093 // ... or truncating stores
1094 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
1095 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
1096 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
1097
1098 // ARM does not have i1 sign extending load.
1099 for (MVT VT : MVT::integer_valuetypes())
1100 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
1101
1102 // ARM supports all 4 flavors of integer indexed load / store.
1103 if (!Subtarget->isThumb1Only()) {
1104 for (unsigned im = (unsigned)ISD::PRE_INC;
1105 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
1106 setIndexedLoadAction(im, MVT::i1, Legal);
1107 setIndexedLoadAction(im, MVT::i8, Legal);
1108 setIndexedLoadAction(im, MVT::i16, Legal);
1109 setIndexedLoadAction(im, MVT::i32, Legal);
1110 setIndexedStoreAction(im, MVT::i1, Legal);
1111 setIndexedStoreAction(im, MVT::i8, Legal);
1112 setIndexedStoreAction(im, MVT::i16, Legal);
1113 setIndexedStoreAction(im, MVT::i32, Legal);
1114 }
1115 } else {
1116 // Thumb-1 has limited post-inc load/store support - LDM r0!, {r1}.
1117 setIndexedLoadAction(ISD::POST_INC, MVT::i32, Legal);
1118 setIndexedStoreAction(ISD::POST_INC, MVT::i32, Legal);
1119 }
1120
1121 setOperationAction(ISD::SADDO, MVT::i32, Custom);
1122 setOperationAction(ISD::UADDO, MVT::i32, Custom);
1123 setOperationAction(ISD::SSUBO, MVT::i32, Custom);
1124 setOperationAction(ISD::USUBO, MVT::i32, Custom);
1125
1126 setOperationAction(ISD::ADDCARRY, MVT::i32, Custom);
1127 setOperationAction(ISD::SUBCARRY, MVT::i32, Custom);
1128 if (Subtarget->hasDSP()) {
1129 setOperationAction(ISD::SADDSAT, MVT::i8, Custom);
1130 setOperationAction(ISD::SSUBSAT, MVT::i8, Custom);
1131 setOperationAction(ISD::SADDSAT, MVT::i16, Custom);
1132 setOperationAction(ISD::SSUBSAT, MVT::i16, Custom);
1133 setOperationAction(ISD::UADDSAT, MVT::i8, Custom);
1134 setOperationAction(ISD::USUBSAT, MVT::i8, Custom);
1135 setOperationAction(ISD::UADDSAT, MVT::i16, Custom);
1136 setOperationAction(ISD::USUBSAT, MVT::i16, Custom);
1137 }
1138 if (Subtarget->hasBaseDSP()) {
1139 setOperationAction(ISD::SADDSAT, MVT::i32, Legal);
1140 setOperationAction(ISD::SSUBSAT, MVT::i32, Legal);
1141 }
1142
1143 // i64 operation support.
1144 setOperationAction(ISD::MUL, MVT::i64, Expand);
1145 setOperationAction(ISD::MULHU, MVT::i32, Expand);
1146 if (Subtarget->isThumb1Only()) {
1147 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
1148 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
1149 }
1150 if (Subtarget->isThumb1Only() || !Subtarget->hasV6Ops()
1151 || (Subtarget->isThumb2() && !Subtarget->hasDSP()))
1152 setOperationAction(ISD::MULHS, MVT::i32, Expand);
1153
1154 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
1155 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
1156 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
1157 setOperationAction(ISD::SRL, MVT::i64, Custom);
1158 setOperationAction(ISD::SRA, MVT::i64, Custom);
1159 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
1160 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i64, Custom);
1161 setOperationAction(ISD::LOAD, MVT::i64, Custom);
1162 setOperationAction(ISD::STORE, MVT::i64, Custom);
1163
1164 // MVE lowers 64 bit shifts to lsll and lsrl
1165 // assuming that ISD::SRL and SRA of i64 are already marked custom
1166 if (Subtarget->hasMVEIntegerOps())
1167 setOperationAction(ISD::SHL, MVT::i64, Custom);
1168
1169 // Expand to __aeabi_l{lsl,lsr,asr} calls for Thumb1.
1170 if (Subtarget->isThumb1Only()) {
1171 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
1172 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
1173 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
1174 }
1175
1176 if (!Subtarget->isThumb1Only() && Subtarget->hasV6T2Ops())
1177 setOperationAction(ISD::BITREVERSE, MVT::i32, Legal);
1178
1179 // ARM does not have ROTL.
1180 setOperationAction(ISD::ROTL, MVT::i32, Expand);
1181 for (MVT VT : MVT::fixedlen_vector_valuetypes()) {
1182 setOperationAction(ISD::ROTL, VT, Expand);
1183 setOperationAction(ISD::ROTR, VT, Expand);
1184 }
1185 setOperationAction(ISD::CTTZ, MVT::i32, Custom);
1186 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
1187 if (!Subtarget->hasV5TOps() || Subtarget->isThumb1Only()) {
1188 setOperationAction(ISD::CTLZ, MVT::i32, Expand);
1189 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, LibCall);
1190 }
1191
1192 // @llvm.readcyclecounter requires the Performance Monitors extension.
1193 // Default to the 0 expansion on unsupported platforms.
1194 // FIXME: Technically there are older ARM CPUs that have
1195 // implementation-specific ways of obtaining this information.
1196 if (Subtarget->hasPerfMon())
1197 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Custom);
1198
1199 // Only ARMv6 has BSWAP.
1200 if (!Subtarget->hasV6Ops())
1201 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
1202
1203 bool hasDivide = Subtarget->isThumb() ? Subtarget->hasDivideInThumbMode()
1204 : Subtarget->hasDivideInARMMode();
1205 if (!hasDivide) {
1206 // These are expanded into libcalls if the cpu doesn't have HW divider.
1207 setOperationAction(ISD::SDIV, MVT::i32, LibCall);
1208 setOperationAction(ISD::UDIV, MVT::i32, LibCall);
1209 }
1210
1211 if (Subtarget->isTargetWindows() && !Subtarget->hasDivideInThumbMode()) {
1212 setOperationAction(ISD::SDIV, MVT::i32, Custom);
1213 setOperationAction(ISD::UDIV, MVT::i32, Custom);
1214
1215 setOperationAction(ISD::SDIV, MVT::i64, Custom);
1216 setOperationAction(ISD::UDIV, MVT::i64, Custom);
1217 }
1218
1219 setOperationAction(ISD::SREM, MVT::i32, Expand);
1220 setOperationAction(ISD::UREM, MVT::i32, Expand);
1221
1222 // Register based DivRem for AEABI (RTABI 4.2)
1223 if (Subtarget->isTargetAEABI() || Subtarget->isTargetAndroid() ||
1224 Subtarget->isTargetGNUAEABI() || Subtarget->isTargetMuslAEABI() ||
1225 Subtarget->isTargetWindows()) {
1226 setOperationAction(ISD::SREM, MVT::i64, Custom);
1227 setOperationAction(ISD::UREM, MVT::i64, Custom);
1228 HasStandaloneRem = false;
1229
1230 if (Subtarget->isTargetWindows()) {
1231 const struct {
1232 const RTLIB::Libcall Op;
1233 const char * const Name;
1234 const CallingConv::ID CC;
1235 } LibraryCalls[] = {
1236 { RTLIB::SDIVREM_I8, "__rt_sdiv", CallingConv::ARM_AAPCS },
1237 { RTLIB::SDIVREM_I16, "__rt_sdiv", CallingConv::ARM_AAPCS },
1238 { RTLIB::SDIVREM_I32, "__rt_sdiv", CallingConv::ARM_AAPCS },
1239 { RTLIB::SDIVREM_I64, "__rt_sdiv64", CallingConv::ARM_AAPCS },
1240
1241 { RTLIB::UDIVREM_I8, "__rt_udiv", CallingConv::ARM_AAPCS },
1242 { RTLIB::UDIVREM_I16, "__rt_udiv", CallingConv::ARM_AAPCS },
1243 { RTLIB::UDIVREM_I32, "__rt_udiv", CallingConv::ARM_AAPCS },
1244 { RTLIB::UDIVREM_I64, "__rt_udiv64", CallingConv::ARM_AAPCS },
1245 };
1246
1247 for (const auto &LC : LibraryCalls) {
1248 setLibcallName(LC.Op, LC.Name);
1249 setLibcallCallingConv(LC.Op, LC.CC);
1250 }
1251 } else {
1252 const struct {
1253 const RTLIB::Libcall Op;
1254 const char * const Name;
1255 const CallingConv::ID CC;
1256 } LibraryCalls[] = {
1257 { RTLIB::SDIVREM_I8, "__aeabi_idivmod", CallingConv::ARM_AAPCS },
1258 { RTLIB::SDIVREM_I16, "__aeabi_idivmod", CallingConv::ARM_AAPCS },
1259 { RTLIB::SDIVREM_I32, "__aeabi_idivmod", CallingConv::ARM_AAPCS },
1260 { RTLIB::SDIVREM_I64, "__aeabi_ldivmod", CallingConv::ARM_AAPCS },
1261
1262 { RTLIB::UDIVREM_I8, "__aeabi_uidivmod", CallingConv::ARM_AAPCS },
1263 { RTLIB::UDIVREM_I16, "__aeabi_uidivmod", CallingConv::ARM_AAPCS },
1264 { RTLIB::UDIVREM_I32, "__aeabi_uidivmod", CallingConv::ARM_AAPCS },
1265 { RTLIB::UDIVREM_I64, "__aeabi_uldivmod", CallingConv::ARM_AAPCS },
1266 };
1267
1268 for (const auto &LC : LibraryCalls) {
1269 setLibcallName(LC.Op, LC.Name);
1270 setLibcallCallingConv(LC.Op, LC.CC);
1271 }
1272 }
1273
1274 setOperationAction(ISD::SDIVREM, MVT::i32, Custom);
1275 setOperationAction(ISD::UDIVREM, MVT::i32, Custom);
1276 setOperationAction(ISD::SDIVREM, MVT::i64, Custom);
1277 setOperationAction(ISD::UDIVREM, MVT::i64, Custom);
1278 } else {
1279 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
1280 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
1281 }
1282
1283 if (Subtarget->getTargetTriple().isOSMSVCRT()) {
1284 // MSVCRT doesn't have powi; fall back to pow
1285 setLibcallName(RTLIB::POWI_F32, nullptr);
1286 setLibcallName(RTLIB::POWI_F64, nullptr);
1287 }
1288
1289 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
1290 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
1291 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
1292 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
1293
1294 setOperationAction(ISD::TRAP, MVT::Other, Legal);
1295 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
1296
1297 // Use the default implementation.
1298 setOperationAction(ISD::VASTART, MVT::Other, Custom);
1299 setOperationAction(ISD::VAARG, MVT::Other, Expand);
1300 setOperationAction(ISD::VACOPY, MVT::Other, Expand);
1301 setOperationAction(ISD::VAEND, MVT::Other, Expand);
1302 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
1303 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
1304
1305 if (Subtarget->isTargetWindows())
1306 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
1307 else
1308 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
1309
1310 // ARMv6 Thumb1 (except for CPUs that support dmb / dsb) and earlier use
1311 // the default expansion.
1312 InsertFencesForAtomic = false;
1313 if (Subtarget->hasAnyDataBarrier() &&
1314 (!Subtarget->isThumb() || Subtarget->hasV8MBaselineOps())) {
1315 // ATOMIC_FENCE needs custom lowering; the others should have been expanded
1316 // to ldrex/strex loops already.
1317 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom);
1318 if (!Subtarget->isThumb() || !Subtarget->isMClass())
1319 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i64, Custom);
1320
1321 // On v8, we have particularly efficient implementations of atomic fences
1322 // if they can be combined with nearby atomic loads and stores.
1323 if (!Subtarget->hasAcquireRelease() ||
1324 getTargetMachine().getOptLevel() == 0) {
1325 // Automatically insert fences (dmb ish) around ATOMIC_SWAP etc.
1326 InsertFencesForAtomic = true;
1327 }
1328 } else {
1329 // If there's anything we can use as a barrier, go through custom lowering
1330 // for ATOMIC_FENCE.
1331 // If target has DMB in thumb, Fences can be inserted.
1332 if (Subtarget->hasDataBarrier())
1333 InsertFencesForAtomic = true;
1334
1335 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other,
1336 Subtarget->hasAnyDataBarrier() ? Custom : Expand);
1337
1338 // Set them all for expansion, which will force libcalls.
1339 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Expand);
1340 setOperationAction(ISD::ATOMIC_SWAP, MVT::i32, Expand);
1341 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i32, Expand);
1342 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Expand);
1343 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i32, Expand);
1344 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i32, Expand);
1345 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i32, Expand);
1346 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i32, Expand);
1347 setOperationAction(ISD::ATOMIC_LOAD_MIN, MVT::i32, Expand);
1348 setOperationAction(ISD::ATOMIC_LOAD_MAX, MVT::i32, Expand);
1349 setOperationAction(ISD::ATOMIC_LOAD_UMIN, MVT::i32, Expand);
1350 setOperationAction(ISD::ATOMIC_LOAD_UMAX, MVT::i32, Expand);
1351 // Mark ATOMIC_LOAD and ATOMIC_STORE custom so we can handle the
1352 // Unordered/Monotonic case.
1353 if (!InsertFencesForAtomic) {
1354 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Custom);
1355 setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Custom);
1356 }
1357 }
1358
1359 // Compute supported atomic widths.
1360 if (Subtarget->isTargetLinux() ||
1361 (!Subtarget->isMClass() && Subtarget->hasV6Ops())) {
1362 // For targets where __sync_* routines are reliably available, we use them
1363 // if necessary.
1364 //
1365 // ARM Linux always supports 64-bit atomics through kernel-assisted atomic
1366 // routines (kernel 3.1 or later). FIXME: Not with compiler-rt?
1367 //
1368 // ARMv6 targets have native instructions in ARM mode. For Thumb mode,
1369 // such targets should provide __sync_* routines, which use the ARM mode
1370 // instructions. (ARMv6 doesn't have dmb, but it has an equivalent
1371 // encoding; see ARMISD::MEMBARRIER_MCR.)
1372 setMaxAtomicSizeInBitsSupported(64);
1373 } else if ((Subtarget->isMClass() && Subtarget->hasV8MBaselineOps()) ||
1374 Subtarget->hasForced32BitAtomics()) {
1375 // Cortex-M (besides Cortex-M0) have 32-bit atomics.
1376 setMaxAtomicSizeInBitsSupported(32);
1377 } else {
1378 // We can't assume anything about other targets; just use libatomic
1379 // routines.
1380 setMaxAtomicSizeInBitsSupported(0);
1381 }
1382
1383 setOperationAction(ISD::PREFETCH, MVT::Other, Custom);
1384
1385 // Requires SXTB/SXTH, available on v6 and up in both ARM and Thumb modes.
1386 if (!Subtarget->hasV6Ops()) {
1387 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
1388 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
1389 }
1390 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
1391
1392 if (!Subtarget->useSoftFloat() && Subtarget->hasFPRegs() &&
1393 !Subtarget->isThumb1Only()) {
1394 // Turn f64->i64 into VMOVRRD, i64 -> f64 to VMOVDRR
1395 // iff target supports vfp2.
1396 setOperationAction(ISD::BITCAST, MVT::i64, Custom);
1397 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
1398 setOperationAction(ISD::SET_ROUNDING, MVT::Other, Custom);
1399 }
1400
1401 // We want to custom lower some of our intrinsics.
1402 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1403 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
1404 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
1405 setOperationAction(ISD::EH_SJLJ_SETUP_DISPATCH, MVT::Other, Custom);
1406 if (Subtarget->useSjLjEH())
1407 setLibcallName(RTLIB::UNWIND_RESUME, "_Unwind_SjLj_Resume");
1408
1409 setOperationAction(ISD::SETCC, MVT::i32, Expand);
1410 setOperationAction(ISD::SETCC, MVT::f32, Expand);
1411 setOperationAction(ISD::SETCC, MVT::f64, Expand);
1412 setOperationAction(ISD::SELECT, MVT::i32, Custom);
1413 setOperationAction(ISD::SELECT, MVT::f32, Custom);
1414 setOperationAction(ISD::SELECT, MVT::f64, Custom);
1415 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
1416 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
1417 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
1418 if (Subtarget->hasFullFP16()) {
1419 setOperationAction(ISD::SETCC, MVT::f16, Expand);
1420 setOperationAction(ISD::SELECT, MVT::f16, Custom);
1421 setOperationAction(ISD::SELECT_CC, MVT::f16, Custom);
1422 }
1423
1424 setOperationAction(ISD::SETCCCARRY, MVT::i32, Custom);
1425
1426 setOperationAction(ISD::BRCOND, MVT::Other, Custom);
1427 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
1428 if (Subtarget->hasFullFP16())
1429 setOperationAction(ISD::BR_CC, MVT::f16, Custom);
1430 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
1431 setOperationAction(ISD::BR_CC, MVT::f64, Custom);
1432 setOperationAction(ISD::BR_JT, MVT::Other, Custom);
1433
1434 // We don't support sin/cos/fmod/copysign/pow
1435 setOperationAction(ISD::FSIN, MVT::f64, Expand);
1436 setOperationAction(ISD::FSIN, MVT::f32, Expand);
1437 setOperationAction(ISD::FCOS, MVT::f32, Expand);
1438 setOperationAction(ISD::FCOS, MVT::f64, Expand);
1439 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
1440 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
1441 setOperationAction(ISD::FREM, MVT::f64, Expand);
1442 setOperationAction(ISD::FREM, MVT::f32, Expand);
1443 if (!Subtarget->useSoftFloat() && Subtarget->hasVFP2Base() &&
1444 !Subtarget->isThumb1Only()) {
1445 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
1446 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
1447 }
1448 setOperationAction(ISD::FPOW, MVT::f64, Expand);
1449 setOperationAction(ISD::FPOW, MVT::f32, Expand);
1450
1451 if (!Subtarget->hasVFP4Base()) {
1452 setOperationAction(ISD::FMA, MVT::f64, Expand);
1453 setOperationAction(ISD::FMA, MVT::f32, Expand);
1454 }
1455
1456 // Various VFP goodness
1457 if (!Subtarget->useSoftFloat() && !Subtarget->isThumb1Only()) {
1458 // FP-ARMv8 adds f64 <-> f16 conversion. Before that it should be expanded.
1459 if (!Subtarget->hasFPARMv8Base() || !Subtarget->hasFP64()) {
1460 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
1461 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
1462 }
1463
1464 // fp16 is a special v7 extension that adds f16 <-> f32 conversions.
1465 if (!Subtarget->hasFP16()) {
1466 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
1467 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
1468 }
1469
1470 // Strict floating-point comparisons need custom lowering.
1471 setOperationAction(ISD::STRICT_FSETCC, MVT::f16, Custom);
1472 setOperationAction(ISD::STRICT_FSETCCS, MVT::f16, Custom);
1473 setOperationAction(ISD::STRICT_FSETCC, MVT::f32, Custom);
1474 setOperationAction(ISD::STRICT_FSETCCS, MVT::f32, Custom);
1475 setOperationAction(ISD::STRICT_FSETCC, MVT::f64, Custom);
1476 setOperationAction(ISD::STRICT_FSETCCS, MVT::f64, Custom);
1477 }
1478
1479 // Use __sincos_stret if available.
1480 if (getLibcallName(RTLIB::SINCOS_STRET_F32) != nullptr &&
1481 getLibcallName(RTLIB::SINCOS_STRET_F64) != nullptr) {
1482 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
1483 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
1484 }
1485
1486 // FP-ARMv8 implements a lot of rounding-like FP operations.
1487 if (Subtarget->hasFPARMv8Base()) {
1488 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
1489 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
1490 setOperationAction(ISD::FROUND, MVT::f32, Legal);
1491 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
1492 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
1493 setOperationAction(ISD::FRINT, MVT::f32, Legal);
1494 setOperationAction(ISD::FMINNUM, MVT::f32, Legal);
1495 setOperationAction(ISD::FMAXNUM, MVT::f32, Legal);
1496 if (Subtarget->hasNEON()) {
1497 setOperationAction(ISD::FMINNUM, MVT::v2f32, Legal);
1498 setOperationAction(ISD::FMAXNUM, MVT::v2f32, Legal);
1499 setOperationAction(ISD::FMINNUM, MVT::v4f32, Legal);
1500 setOperationAction(ISD::FMAXNUM, MVT::v4f32, Legal);
1501 }
1502
1503 if (Subtarget->hasFP64()) {
1504 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
1505 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
1506 setOperationAction(ISD::FROUND, MVT::f64, Legal);
1507 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
1508 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
1509 setOperationAction(ISD::FRINT, MVT::f64, Legal);
1510 setOperationAction(ISD::FMINNUM, MVT::f64, Legal);
1511 setOperationAction(ISD::FMAXNUM, MVT::f64, Legal);
1512 }
1513 }
1514
1515 // FP16 often need to be promoted to call lib functions
1516 if (Subtarget->hasFullFP16()) {
1517 setOperationAction(ISD::FREM, MVT::f16, Promote);
1518 setOperationAction(ISD::FCOPYSIGN, MVT::f16, Expand);
1519 setOperationAction(ISD::FSIN, MVT::f16, Promote);
1520 setOperationAction(ISD::FCOS, MVT::f16, Promote);
1521 setOperationAction(ISD::FSINCOS, MVT::f16, Promote);
1522 setOperationAction(ISD::FPOWI, MVT::f16, Promote);
1523 setOperationAction(ISD::FPOW, MVT::f16, Promote);
1524 setOperationAction(ISD::FEXP, MVT::f16, Promote);
1525 setOperationAction(ISD::FEXP2, MVT::f16, Promote);
1526 setOperationAction(ISD::FLOG, MVT::f16, Promote);
1527 setOperationAction(ISD::FLOG10, MVT::f16, Promote);
1528 setOperationAction(ISD::FLOG2, MVT::f16, Promote);
1529
1530 setOperationAction(ISD::FROUND, MVT::f16, Legal);
1531 }
1532
1533 if (Subtarget->hasNEON()) {
1534 // vmin and vmax aren't available in a scalar form, so we can use
1535 // a NEON instruction with an undef lane instead. This has a performance
1536 // penalty on some cores, so we don't do this unless we have been
1537 // asked to by the core tuning model.
1538 if (Subtarget->useNEONForSinglePrecisionFP()) {
1539 setOperationAction(ISD::FMINIMUM, MVT::f32, Legal);
1540 setOperationAction(ISD::FMAXIMUM, MVT::f32, Legal);
1541 setOperationAction(ISD::FMINIMUM, MVT::f16, Legal);
1542 setOperationAction(ISD::FMAXIMUM, MVT::f16, Legal);
1543 }
1544 setOperationAction(ISD::FMINIMUM, MVT::v2f32, Legal);
1545 setOperationAction(ISD::FMAXIMUM, MVT::v2f32, Legal);
1546 setOperationAction(ISD::FMINIMUM, MVT::v4f32, Legal);
1547 setOperationAction(ISD::FMAXIMUM, MVT::v4f32, Legal);
1548
1549 if (Subtarget->hasFullFP16()) {
1550 setOperationAction(ISD::FMINNUM, MVT::v4f16, Legal);
1551 setOperationAction(ISD::FMAXNUM, MVT::v4f16, Legal);
1552 setOperationAction(ISD::FMINNUM, MVT::v8f16, Legal);
1553 setOperationAction(ISD::FMAXNUM, MVT::v8f16, Legal);
1554
1555 setOperationAction(ISD::FMINIMUM, MVT::v4f16, Legal);
1556 setOperationAction(ISD::FMAXIMUM, MVT::v4f16, Legal);
1557 setOperationAction(ISD::FMINIMUM, MVT::v8f16, Legal);
1558 setOperationAction(ISD::FMAXIMUM, MVT::v8f16, Legal);
1559 }
1560 }
1561
1562 // We have target-specific dag combine patterns for the following nodes:
1563 // ARMISD::VMOVRRD - No need to call setTargetDAGCombine
1564 setTargetDAGCombine(
1565 {ISD::ADD, ISD::SUB, ISD::MUL, ISD::AND, ISD::OR, ISD::XOR});
1566
1567 if (Subtarget->hasMVEIntegerOps())
1568 setTargetDAGCombine(ISD::VSELECT);
1569
1570 if (Subtarget->hasV6Ops())
1571 setTargetDAGCombine(ISD::SRL);
1572 if (Subtarget->isThumb1Only())
1573 setTargetDAGCombine(ISD::SHL);
1574 // Attempt to lower smin/smax to ssat/usat
1575 if ((!Subtarget->isThumb() && Subtarget->hasV6Ops()) ||
1576 Subtarget->isThumb2()) {
1577 setTargetDAGCombine({ISD::SMIN, ISD::SMAX});
1578 }
1579
1580 setStackPointerRegisterToSaveRestore(ARM::SP);
1581
1582 if (Subtarget->useSoftFloat() || Subtarget->isThumb1Only() ||
1583 !Subtarget->hasVFP2Base() || Subtarget->hasMinSize())
1584 setSchedulingPreference(Sched::RegPressure);
1585 else
1586 setSchedulingPreference(Sched::Hybrid);
1587
1588 //// temporary - rewrite interface to use type
1589 MaxStoresPerMemset = 8;
1590 MaxStoresPerMemsetOptSize = 4;
1591 MaxStoresPerMemcpy = 4; // For @llvm.memcpy -> sequence of stores
1592 MaxStoresPerMemcpyOptSize = 2;
1593 MaxStoresPerMemmove = 4; // For @llvm.memmove -> sequence of stores
1594 MaxStoresPerMemmoveOptSize = 2;
1595
1596 // On ARM arguments smaller than 4 bytes are extended, so all arguments
1597 // are at least 4 bytes aligned.
1598 setMinStackArgumentAlignment(Align(4));
1599
1600 // Prefer likely predicted branches to selects on out-of-order cores.
1601 PredictableSelectIsExpensive = Subtarget->getSchedModel().isOutOfOrder();
1602
1603 setPrefLoopAlignment(Align(1ULL << Subtarget->getPrefLoopLogAlignment()));
1604
1605 setMinFunctionAlignment(Subtarget->isThumb() ? Align(2) : Align(4));
1606
1607 if (Subtarget->isThumb() || Subtarget->isThumb2())
1608 setTargetDAGCombine(ISD::ABS);
1609}
1610
1611bool ARMTargetLowering::useSoftFloat() const {
1612 return Subtarget->useSoftFloat();
1613}
1614
1615// FIXME: It might make sense to define the representative register class as the
1616// nearest super-register that has a non-null superset. For example, DPR_VFP2 is
1617// a super-register of SPR, and DPR is a superset if DPR_VFP2. Consequently,
1618// SPR's representative would be DPR_VFP2. This should work well if register
1619// pressure tracking were modified such that a register use would increment the
1620// pressure of the register class's representative and all of it's super
1621// classes' representatives transitively. We have not implemented this because
1622// of the difficulty prior to coalescing of modeling operand register classes
1623// due to the common occurrence of cross class copies and subregister insertions
1624// and extractions.
1625std::pair<const TargetRegisterClass *, uint8_t>
1626ARMTargetLowering::findRepresentativeClass(const TargetRegisterInfo *TRI,
1627 MVT VT) const {
1628 const TargetRegisterClass *RRC = nullptr;
1629 uint8_t Cost = 1;
1630 switch (VT.SimpleTy) {
1631 default:
1632 return TargetLowering::findRepresentativeClass(TRI, VT);
1633 // Use DPR as representative register class for all floating point
1634 // and vector types. Since there are 32 SPR registers and 32 DPR registers so
1635 // the cost is 1 for both f32 and f64.
1636 case MVT::f32: case MVT::f64: case MVT::v8i8: case MVT::v4i16:
1637 case MVT::v2i32: case MVT::v1i64: case MVT::v2f32:
1638 RRC = &ARM::DPRRegClass;
1639 // When NEON is used for SP, only half of the register file is available
1640 // because operations that define both SP and DP results will be constrained
1641 // to the VFP2 class (D0-D15). We currently model this constraint prior to
1642 // coalescing by double-counting the SP regs. See the FIXME above.
1643 if (Subtarget->useNEONForSinglePrecisionFP())
1644 Cost = 2;
1645 break;
1646 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1647 case MVT::v4f32: case MVT::v2f64:
1648 RRC = &ARM::DPRRegClass;
1649 Cost = 2;
1650 break;
1651 case MVT::v4i64:
1652 RRC = &ARM::DPRRegClass;
1653 Cost = 4;
1654 break;
1655 case MVT::v8i64:
1656 RRC = &ARM::DPRRegClass;
1657 Cost = 8;
1658 break;
1659 }
1660 return std::make_pair(RRC, Cost);
1661}
1662
1663const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const {
1664#define MAKE_CASE(V) \
1665 case V: \
1666 return #V;
1667 switch ((ARMISD::NodeType)Opcode) {
1668 case ARMISD::FIRST_NUMBER:
1669 break;
1670 MAKE_CASE(ARMISD::Wrapper)
1671 MAKE_CASE(ARMISD::WrapperPIC)
1672 MAKE_CASE(ARMISD::WrapperJT)
1673 MAKE_CASE(ARMISD::COPY_STRUCT_BYVAL)
1674 MAKE_CASE(ARMISD::CALL)
1675 MAKE_CASE(ARMISD::CALL_PRED)
1676 MAKE_CASE(ARMISD::CALL_NOLINK)
1677 MAKE_CASE(ARMISD::tSECALL)
1678 MAKE_CASE(ARMISD::t2CALL_BTI)
1679 MAKE_CASE(ARMISD::BRCOND)
1680 MAKE_CASE(ARMISD::BR_JT)
1681 MAKE_CASE(ARMISD::BR2_JT)
1682 MAKE_CASE(ARMISD::RET_FLAG)
1683 MAKE_CASE(ARMISD::SERET_FLAG)
1684 MAKE_CASE(ARMISD::INTRET_FLAG)
1685 MAKE_CASE(ARMISD::PIC_ADD)
1686 MAKE_CASE(ARMISD::CMP)
1687 MAKE_CASE(ARMISD::CMN)
1688 MAKE_CASE(ARMISD::CMPZ)
1689 MAKE_CASE(ARMISD::CMPFP)
1690 MAKE_CASE(ARMISD::CMPFPE)
1691 MAKE_CASE(ARMISD::CMPFPw0)
1692 MAKE_CASE(ARMISD::CMPFPEw0)
1693 MAKE_CASE(ARMISD::BCC_i64)
1694 MAKE_CASE(ARMISD::FMSTAT)
1695 MAKE_CASE(ARMISD::CMOV)
1696 MAKE_CASE(ARMISD::SUBS)
1697 MAKE_CASE(ARMISD::SSAT)
1698 MAKE_CASE(ARMISD::USAT)
1699 MAKE_CASE(ARMISD::ASRL)
1700 MAKE_CASE(ARMISD::LSRL)
1701 MAKE_CASE(ARMISD::LSLL)
1702 MAKE_CASE(ARMISD::SRL_FLAG)
1703 MAKE_CASE(ARMISD::SRA_FLAG)
1704 MAKE_CASE(ARMISD::RRX)
1705 MAKE_CASE(ARMISD::ADDC)
1706 MAKE_CASE(ARMISD::ADDE)
1707 MAKE_CASE(ARMISD::SUBC)
1708 MAKE_CASE(ARMISD::SUBE)
1709 MAKE_CASE(ARMISD::LSLS)
1710 MAKE_CASE(ARMISD::VMOVRRD)
1711 MAKE_CASE(ARMISD::VMOVDRR)
1712 MAKE_CASE(ARMISD::VMOVhr)
1713 MAKE_CASE(ARMISD::VMOVrh)
1714 MAKE_CASE(ARMISD::VMOVSR)
1715 MAKE_CASE(ARMISD::EH_SJLJ_SETJMP)
1716 MAKE_CASE(ARMISD::EH_SJLJ_LONGJMP)
1717 MAKE_CASE(ARMISD::EH_SJLJ_SETUP_DISPATCH)
1718 MAKE_CASE(ARMISD::TC_RETURN)
1719 MAKE_CASE(ARMISD::THREAD_POINTER)
1720 MAKE_CASE(ARMISD::DYN_ALLOC)
1721 MAKE_CASE(ARMISD::MEMBARRIER_MCR)
1722 MAKE_CASE(ARMISD::PRELOAD)
1723 MAKE_CASE(ARMISD::LDRD)
1724 MAKE_CASE(ARMISD::STRD)
1725 MAKE_CASE(ARMISD::WIN__CHKSTK)
1726 MAKE_CASE(ARMISD::WIN__DBZCHK)
1727 MAKE_CASE(ARMISD::PREDICATE_CAST)
1728 MAKE_CASE(ARMISD::VECTOR_REG_CAST)
1729 MAKE_CASE(ARMISD::MVESEXT)
1730 MAKE_CASE(ARMISD::MVEZEXT)
1731 MAKE_CASE(ARMISD::MVETRUNC)
1732 MAKE_CASE(ARMISD::VCMP)
1733 MAKE_CASE(ARMISD::VCMPZ)
1734 MAKE_CASE(ARMISD::VTST)
1735 MAKE_CASE(ARMISD::VSHLs)
1736 MAKE_CASE(ARMISD::VSHLu)
1737 MAKE_CASE(ARMISD::VSHLIMM)
1738 MAKE_CASE(ARMISD::VSHRsIMM)
1739 MAKE_CASE(ARMISD::VSHRuIMM)
1740 MAKE_CASE(ARMISD::VRSHRsIMM)
1741 MAKE_CASE(ARMISD::VRSHRuIMM)
1742 MAKE_CASE(ARMISD::VRSHRNIMM)
1743 MAKE_CASE(ARMISD::VQSHLsIMM)
1744 MAKE_CASE(ARMISD::VQSHLuIMM)
1745 MAKE_CASE(ARMISD::VQSHLsuIMM)
1746 MAKE_CASE(ARMISD::VQSHRNsIMM)
1747 MAKE_CASE(ARMISD::VQSHRNuIMM)
1748 MAKE_CASE(ARMISD::VQSHRNsuIMM)
1749 MAKE_CASE(ARMISD::VQRSHRNsIMM)
1750 MAKE_CASE(ARMISD::VQRSHRNuIMM)
1751 MAKE_CASE(ARMISD::VQRSHRNsuIMM)
1752 MAKE_CASE(ARMISD::VSLIIMM)
1753 MAKE_CASE(ARMISD::VSRIIMM)
1754 MAKE_CASE(ARMISD::VGETLANEu)
1755 MAKE_CASE(ARMISD::VGETLANEs)
1756 MAKE_CASE(ARMISD::VMOVIMM)
1757 MAKE_CASE(ARMISD::VMVNIMM)
1758 MAKE_CASE(ARMISD::VMOVFPIMM)
1759 MAKE_CASE(ARMISD::VDUP)
1760 MAKE_CASE(ARMISD::VDUPLANE)
1761 MAKE_CASE(ARMISD::VEXT)
1762 MAKE_CASE(ARMISD::VREV64)
1763 MAKE_CASE(ARMISD::VREV32)
1764 MAKE_CASE(ARMISD::VREV16)
1765 MAKE_CASE(ARMISD::VZIP)
1766 MAKE_CASE(ARMISD::VUZP)
1767 MAKE_CASE(ARMISD::VTRN)
1768 MAKE_CASE(ARMISD::VTBL1)
1769 MAKE_CASE(ARMISD::VTBL2)
1770 MAKE_CASE(ARMISD::VMOVN)
1771 MAKE_CASE(ARMISD::VQMOVNs)
1772 MAKE_CASE(ARMISD::VQMOVNu)
1773 MAKE_CASE(ARMISD::VCVTN)
1774 MAKE_CASE(ARMISD::VCVTL)
1775 MAKE_CASE(ARMISD::VIDUP)
1776 MAKE_CASE(ARMISD::VMULLs)
1777 MAKE_CASE(ARMISD::VMULLu)
1778 MAKE_CASE(ARMISD::VQDMULH)
1779 MAKE_CASE(ARMISD::VADDVs)
1780 MAKE_CASE(ARMISD::VADDVu)
1781 MAKE_CASE(ARMISD::VADDVps)
1782 MAKE_CASE(ARMISD::VADDVpu)
1783 MAKE_CASE(ARMISD::VADDLVs)
1784 MAKE_CASE(ARMISD::VADDLVu)
1785 MAKE_CASE(ARMISD::VADDLVAs)
1786 MAKE_CASE(ARMISD::VADDLVAu)
1787 MAKE_CASE(ARMISD::VADDLVps)
1788 MAKE_CASE(ARMISD::VADDLVpu)
1789 MAKE_CASE(ARMISD::VADDLVAps)
1790 MAKE_CASE(ARMISD::VADDLVApu)
1791 MAKE_CASE(ARMISD::VMLAVs)
1792 MAKE_CASE(ARMISD::VMLAVu)
1793 MAKE_CASE(ARMISD::VMLAVps)
1794 MAKE_CASE(ARMISD::VMLAVpu)
1795 MAKE_CASE(ARMISD::VMLALVs)
1796 MAKE_CASE(ARMISD::VMLALVu)
1797 MAKE_CASE(ARMISD::VMLALVps)
1798 MAKE_CASE(ARMISD::VMLALVpu)
1799 MAKE_CASE(ARMISD::VMLALVAs)
1800 MAKE_CASE(ARMISD::VMLALVAu)
1801 MAKE_CASE(ARMISD::VMLALVAps)
1802 MAKE_CASE(ARMISD::VMLALVApu)
1803 MAKE_CASE(ARMISD::VMINVu)
1804 MAKE_CASE(ARMISD::VMINVs)
1805 MAKE_CASE(ARMISD::VMAXVu)
1806 MAKE_CASE(ARMISD::VMAXVs)
1807 MAKE_CASE(ARMISD::UMAAL)
1808 MAKE_CASE(ARMISD::UMLAL)
1809 MAKE_CASE(ARMISD::SMLAL)
1810 MAKE_CASE(ARMISD::SMLALBB)
1811 MAKE_CASE(ARMISD::SMLALBT)
1812 MAKE_CASE(ARMISD::SMLALTB)
1813 MAKE_CASE(ARMISD::SMLALTT)
1814 MAKE_CASE(ARMISD::SMULWB)
1815 MAKE_CASE(ARMISD::SMULWT)
1816 MAKE_CASE(ARMISD::SMLALD)
1817 MAKE_CASE(ARMISD::SMLALDX)
1818 MAKE_CASE(ARMISD::SMLSLD)
1819 MAKE_CASE(ARMISD::SMLSLDX)
1820 MAKE_CASE(ARMISD::SMMLAR)
1821 MAKE_CASE(ARMISD::SMMLSR)
1822 MAKE_CASE(ARMISD::QADD16b)
1823 MAKE_CASE(ARMISD::QSUB16b)
1824 MAKE_CASE(ARMISD::QADD8b)
1825 MAKE_CASE(ARMISD::QSUB8b)
1826 MAKE_CASE(ARMISD::UQADD16b)
1827 MAKE_CASE(ARMISD::UQSUB16b)
1828 MAKE_CASE(ARMISD::UQADD8b)
1829 MAKE_CASE(ARMISD::UQSUB8b)
1830 MAKE_CASE(ARMISD::BUILD_VECTOR)
1831 MAKE_CASE(ARMISD::BFI)
1832 MAKE_CASE(ARMISD::VORRIMM)
1833 MAKE_CASE(ARMISD::VBICIMM)
1834 MAKE_CASE(ARMISD::VBSP)
1835 MAKE_CASE(ARMISD::MEMCPY)
1836 MAKE_CASE(ARMISD::VLD1DUP)
1837 MAKE_CASE(ARMISD::VLD2DUP)
1838 MAKE_CASE(ARMISD::VLD3DUP)
1839 MAKE_CASE(ARMISD::VLD4DUP)
1840 MAKE_CASE(ARMISD::VLD1_UPD)
1841 MAKE_CASE(ARMISD::VLD2_UPD)
1842 MAKE_CASE(ARMISD::VLD3_UPD)
1843 MAKE_CASE(ARMISD::VLD4_UPD)
1844 MAKE_CASE(ARMISD::VLD1x2_UPD)
1845 MAKE_CASE(ARMISD::VLD1x3_UPD)
1846 MAKE_CASE(ARMISD::VLD1x4_UPD)
1847 MAKE_CASE(ARMISD::VLD2LN_UPD)
1848 MAKE_CASE(ARMISD::VLD3LN_UPD)
1849 MAKE_CASE(ARMISD::VLD4LN_UPD)
1850 MAKE_CASE(ARMISD::VLD1DUP_UPD)
1851 MAKE_CASE(ARMISD::VLD2DUP_UPD)
1852 MAKE_CASE(ARMISD::VLD3DUP_UPD)
1853 MAKE_CASE(ARMISD::VLD4DUP_UPD)
1854 MAKE_CASE(ARMISD::VST1_UPD)
1855 MAKE_CASE(ARMISD::VST2_UPD)
1856 MAKE_CASE(ARMISD::VST3_UPD)
1857 MAKE_CASE(ARMISD::VST4_UPD)
1858 MAKE_CASE(ARMISD::VST1x2_UPD)
1859 MAKE_CASE(ARMISD::VST1x3_UPD)
1860 MAKE_CASE(ARMISD::VST1x4_UPD)
1861 MAKE_CASE(ARMISD::VST2LN_UPD)
1862 MAKE_CASE(ARMISD::VST3LN_UPD)
1863 MAKE_CASE(ARMISD::VST4LN_UPD)
1864 MAKE_CASE(ARMISD::WLS)
1865 MAKE_CASE(ARMISD::WLSSETUP)
1866 MAKE_CASE(ARMISD::LE)
1867 MAKE_CASE(ARMISD::LOOP_DEC)
1868 MAKE_CASE(ARMISD::CSINV)
1869 MAKE_CASE(ARMISD::CSNEG)
1870 MAKE_CASE(ARMISD::CSINC)
1871 MAKE_CASE(ARMISD::MEMCPYLOOP)
1872 MAKE_CASE(ARMISD::MEMSETLOOP)
1873#undef MAKE_CASE
1874 }
1875 return nullptr;
1876}
1877
1878EVT ARMTargetLowering::getSetCCResultType(const DataLayout &DL, LLVMContext &,
1879 EVT VT) const {
1880 if (!VT.isVector())
1881 return getPointerTy(DL);
1882
1883 // MVE has a predicate register.
1884 if ((Subtarget->hasMVEIntegerOps() &&
1885 (VT == MVT::v2i64 || VT == MVT::v4i32 || VT == MVT::v8i16 ||
1886 VT == MVT::v16i8)) ||
1887 (Subtarget->hasMVEFloatOps() &&
1888 (VT == MVT::v2f64 || VT == MVT::v4f32 || VT == MVT::v8f16)))
1889 return MVT::getVectorVT(MVT::i1, VT.getVectorElementCount());
1890 return VT.changeVectorElementTypeToInteger();
1891}
1892
1893/// getRegClassFor - Return the register class that should be used for the
1894/// specified value type.
1895const TargetRegisterClass *
1896ARMTargetLowering::getRegClassFor(MVT VT, bool isDivergent) const {
1897 (void)isDivergent;
1898 // Map v4i64 to QQ registers but do not make the type legal. Similarly map
1899 // v8i64 to QQQQ registers. v4i64 and v8i64 are only used for REG_SEQUENCE to
1900 // load / store 4 to 8 consecutive NEON D registers, or 2 to 4 consecutive
1901 // MVE Q registers.
1902 if (Subtarget->hasNEON()) {
1903 if (VT == MVT::v4i64)
1904 return &ARM::QQPRRegClass;
1905 if (VT == MVT::v8i64)
1906 return &ARM::QQQQPRRegClass;
1907 }
1908 if (Subtarget->hasMVEIntegerOps()) {
1909 if (VT == MVT::v4i64)
1910 return &ARM::MQQPRRegClass;
1911 if (VT == MVT::v8i64)
1912 return &ARM::MQQQQPRRegClass;
1913 }
1914 return TargetLowering::getRegClassFor(VT);
1915}
1916
1917// memcpy, and other memory intrinsics, typically tries to use LDM/STM if the
1918// source/dest is aligned and the copy size is large enough. We therefore want
1919// to align such objects passed to memory intrinsics.
1920bool ARMTargetLowering::shouldAlignPointerArgs(CallInst *CI, unsigned &MinSize,
1921 Align &PrefAlign) const {
1922 if (!isa<MemIntrinsic>(CI))
1923 return false;
1924 MinSize = 8;
1925 // On ARM11 onwards (excluding M class) 8-byte aligned LDM is typically 1
1926 // cycle faster than 4-byte aligned LDM.
1927 PrefAlign =
1928 (Subtarget->hasV6Ops() && !Subtarget->isMClass() ? Align(8) : Align(4));
1929 return true;
1930}
1931
1932// Create a fast isel object.
1933FastISel *
1934ARMTargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
1935 const TargetLibraryInfo *libInfo) const {
1936 return ARM::createFastISel(funcInfo, libInfo);
1937}
1938
1939Sched::Preference ARMTargetLowering::getSchedulingPreference(SDNode *N) const {
1940 unsigned NumVals = N->getNumValues();
1941 if (!NumVals)
1942 return Sched::RegPressure;
1943
1944 for (unsigned i = 0; i != NumVals; ++i) {
1945 EVT VT = N->getValueType(i);
1946 if (VT == MVT::Glue || VT == MVT::Other)
1947 continue;
1948 if (VT.isFloatingPoint() || VT.isVector())
1949 return Sched::ILP;
1950 }
1951
1952 if (!N->isMachineOpcode())
1953 return Sched::RegPressure;
1954
1955 // Load are scheduled for latency even if there instruction itinerary
1956 // is not available.
1957 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
1958 const MCInstrDesc &MCID = TII->get(N->getMachineOpcode());
1959
1960 if (MCID.getNumDefs() == 0)
1961 return Sched::RegPressure;
1962 if (!Itins->isEmpty() &&
1963 Itins->getOperandCycle(MCID.getSchedClass(), 0) > 2)
1964 return Sched::ILP;
1965
1966 return Sched::RegPressure;
1967}
1968
1969//===----------------------------------------------------------------------===//
1970// Lowering Code
1971//===----------------------------------------------------------------------===//
1972
1973static bool isSRL16(const SDValue &Op) {
1974 if (Op.getOpcode() != ISD::SRL)
1975 return false;
1976 if (auto Const = dyn_cast<ConstantSDNode>(Op.getOperand(1)))
1977 return Const->getZExtValue() == 16;
1978 return false;
1979}
1980
1981static bool isSRA16(const SDValue &Op) {
1982 if (Op.getOpcode() != ISD::SRA)
1983 return false;
1984 if (auto Const = dyn_cast<ConstantSDNode>(Op.getOperand(1)))
1985 return Const->getZExtValue() == 16;
1986 return false;
1987}
1988
1989static bool isSHL16(const SDValue &Op) {
1990 if (Op.getOpcode() != ISD::SHL)
1991 return false;
1992 if (auto Const = dyn_cast<ConstantSDNode>(Op.getOperand(1)))
1993 return Const->getZExtValue() == 16;
1994 return false;
1995}
1996
1997// Check for a signed 16-bit value. We special case SRA because it makes it
1998// more simple when also looking for SRAs that aren't sign extending a
1999// smaller value. Without the check, we'd need to take extra care with
2000// checking order for some operations.
2001static bool isS16(const SDValue &Op, SelectionDAG &DAG) {
2002 if (isSRA16(Op))
2003 return isSHL16(Op.getOperand(0));
2004 return DAG.ComputeNumSignBits(Op) == 17;
2005}
2006
2007/// IntCCToARMCC - Convert a DAG integer condition code to an ARM CC
2008static ARMCC::CondCodes IntCCToARMCC(ISD::CondCode CC) {
2009 switch (CC) {
2010 default: llvm_unreachable("Unknown condition code!")::llvm::llvm_unreachable_internal("Unknown condition code!", "llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2010)
;
2011 case ISD::SETNE: return ARMCC::NE;
2012 case ISD::SETEQ: return ARMCC::EQ;
2013 case ISD::SETGT: return ARMCC::GT;
2014 case ISD::SETGE: return ARMCC::GE;
2015 case ISD::SETLT: return ARMCC::LT;
2016 case ISD::SETLE: return ARMCC::LE;
2017 case ISD::SETUGT: return ARMCC::HI;
2018 case ISD::SETUGE: return ARMCC::HS;
2019 case ISD::SETULT: return ARMCC::LO;
2020 case ISD::SETULE: return ARMCC::LS;
2021 }
2022}
2023
2024/// FPCCToARMCC - Convert a DAG fp condition code to an ARM CC.
2025static void FPCCToARMCC(ISD::CondCode CC, ARMCC::CondCodes &CondCode,
2026 ARMCC::CondCodes &CondCode2) {
2027 CondCode2 = ARMCC::AL;
2028 switch (CC) {
2029 default: llvm_unreachable("Unknown FP condition!")::llvm::llvm_unreachable_internal("Unknown FP condition!", "llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2029)
;
2030 case ISD::SETEQ:
2031 case ISD::SETOEQ: CondCode = ARMCC::EQ; break;
2032 case ISD::SETGT:
2033 case ISD::SETOGT: CondCode = ARMCC::GT; break;
2034 case ISD::SETGE:
2035 case ISD::SETOGE: CondCode = ARMCC::GE; break;
2036 case ISD::SETOLT: CondCode = ARMCC::MI; break;
2037 case ISD::SETOLE: CondCode = ARMCC::LS; break;
2038 case ISD::SETONE: CondCode = ARMCC::MI; CondCode2 = ARMCC::GT; break;
2039 case ISD::SETO: CondCode = ARMCC::VC; break;
2040 case ISD::SETUO: CondCode = ARMCC::VS; break;
2041 case ISD::SETUEQ: CondCode = ARMCC::EQ; CondCode2 = ARMCC::VS; break;
2042 case ISD::SETUGT: CondCode = ARMCC::HI; break;
2043 case ISD::SETUGE: CondCode = ARMCC::PL; break;
2044 case ISD::SETLT:
2045 case ISD::SETULT: CondCode = ARMCC::LT; break;
2046 case ISD::SETLE:
2047 case ISD::SETULE: CondCode = ARMCC::LE; break;
2048 case ISD::SETNE:
2049 case ISD::SETUNE: CondCode = ARMCC::NE; break;
2050 }
2051}
2052
2053//===----------------------------------------------------------------------===//
2054// Calling Convention Implementation
2055//===----------------------------------------------------------------------===//
2056
2057/// getEffectiveCallingConv - Get the effective calling convention, taking into
2058/// account presence of floating point hardware and calling convention
2059/// limitations, such as support for variadic functions.
2060CallingConv::ID
2061ARMTargetLowering::getEffectiveCallingConv(CallingConv::ID CC,
2062 bool isVarArg) const {
2063 switch (CC) {
2064 default:
2065 report_fatal_error("Unsupported calling convention");
2066 case CallingConv::ARM_AAPCS:
2067 case CallingConv::ARM_APCS:
2068 case CallingConv::GHC:
2069 case CallingConv::CFGuard_Check:
2070 return CC;
2071 case CallingConv::PreserveMost:
2072 return CallingConv::PreserveMost;
2073 case CallingConv::ARM_AAPCS_VFP:
2074 case CallingConv::Swift:
2075 case CallingConv::SwiftTail:
2076 return isVarArg ? CallingConv::ARM_AAPCS : CallingConv::ARM_AAPCS_VFP;
2077 case CallingConv::C:
2078 case CallingConv::Tail:
2079 if (!Subtarget->isAAPCS_ABI())
2080 return CallingConv::ARM_APCS;
2081 else if (Subtarget->hasVFP2Base() && !Subtarget->isThumb1Only() &&
2082 getTargetMachine().Options.FloatABIType == FloatABI::Hard &&
2083 !isVarArg)
2084 return CallingConv::ARM_AAPCS_VFP;
2085 else
2086 return CallingConv::ARM_AAPCS;
2087 case CallingConv::Fast:
2088 case CallingConv::CXX_FAST_TLS:
2089 if (!Subtarget->isAAPCS_ABI()) {
2090 if (Subtarget->hasVFP2Base() && !Subtarget->isThumb1Only() && !isVarArg)
2091 return CallingConv::Fast;
2092 return CallingConv::ARM_APCS;
2093 } else if (Subtarget->hasVFP2Base() &&
2094 !Subtarget->isThumb1Only() && !isVarArg)
2095 return CallingConv::ARM_AAPCS_VFP;
2096 else
2097 return CallingConv::ARM_AAPCS;
2098 }
2099}
2100
2101CCAssignFn *ARMTargetLowering::CCAssignFnForCall(CallingConv::ID CC,
2102 bool isVarArg) const {
2103 return CCAssignFnForNode(CC, false, isVarArg);
2104}
2105
2106CCAssignFn *ARMTargetLowering::CCAssignFnForReturn(CallingConv::ID CC,
2107 bool isVarArg) const {
2108 return CCAssignFnForNode(CC, true, isVarArg);
2109}
2110
2111/// CCAssignFnForNode - Selects the correct CCAssignFn for the given
2112/// CallingConvention.
2113CCAssignFn *ARMTargetLowering::CCAssignFnForNode(CallingConv::ID CC,
2114 bool Return,
2115 bool isVarArg) const {
2116 switch (getEffectiveCallingConv(CC, isVarArg)) {
2117 default:
2118 report_fatal_error("Unsupported calling convention");
2119 case CallingConv::ARM_APCS:
2120 return (Return ? RetCC_ARM_APCS : CC_ARM_APCS);
2121 case CallingConv::ARM_AAPCS:
2122 return (Return ? RetCC_ARM_AAPCS : CC_ARM_AAPCS);
2123 case CallingConv::ARM_AAPCS_VFP:
2124 return (Return ? RetCC_ARM_AAPCS_VFP : CC_ARM_AAPCS_VFP);
2125 case CallingConv::Fast:
2126 return (Return ? RetFastCC_ARM_APCS : FastCC_ARM_APCS);
2127 case CallingConv::GHC:
2128 return (Return ? RetCC_ARM_APCS : CC_ARM_APCS_GHC);
2129 case CallingConv::PreserveMost:
2130 return (Return ? RetCC_ARM_AAPCS : CC_ARM_AAPCS);
2131 case CallingConv::CFGuard_Check:
2132 return (Return ? RetCC_ARM_AAPCS : CC_ARM_Win32_CFGuard_Check);
2133 }
2134}
2135
2136SDValue ARMTargetLowering::MoveToHPR(const SDLoc &dl, SelectionDAG &DAG,
2137 MVT LocVT, MVT ValVT, SDValue Val) const {
2138 Val = DAG.getNode(ISD::BITCAST, dl, MVT::getIntegerVT(LocVT.getSizeInBits()),
2139 Val);
2140 if (Subtarget->hasFullFP16()) {
2141 Val = DAG.getNode(ARMISD::VMOVhr, dl, ValVT, Val);
2142 } else {
2143 Val = DAG.getNode(ISD::TRUNCATE, dl,
2144 MVT::getIntegerVT(ValVT.getSizeInBits()), Val);
2145 Val = DAG.getNode(ISD::BITCAST, dl, ValVT, Val);
2146 }
2147 return Val;
2148}
2149
2150SDValue ARMTargetLowering::MoveFromHPR(const SDLoc &dl, SelectionDAG &DAG,
2151 MVT LocVT, MVT ValVT,
2152 SDValue Val) const {
2153 if (Subtarget->hasFullFP16()) {
2154 Val = DAG.getNode(ARMISD::VMOVrh, dl,
2155 MVT::getIntegerVT(LocVT.getSizeInBits()), Val);
2156 } else {
2157 Val = DAG.getNode(ISD::BITCAST, dl,
2158 MVT::getIntegerVT(ValVT.getSizeInBits()), Val);
2159 Val = DAG.getNode(ISD::ZERO_EXTEND, dl,
2160 MVT::getIntegerVT(LocVT.getSizeInBits()), Val);
2161 }
2162 return DAG.getNode(ISD::BITCAST, dl, LocVT, Val);
2163}
2164
2165/// LowerCallResult - Lower the result values of a call into the
2166/// appropriate copies out of appropriate physical registers.
2167SDValue ARMTargetLowering::LowerCallResult(
2168 SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg,
2169 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
2170 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals, bool isThisReturn,
2171 SDValue ThisVal) const {
2172 // Assign locations to each value returned by this call.
2173 SmallVector<CCValAssign, 16> RVLocs;
2174 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2175 *DAG.getContext());
2176 CCInfo.AnalyzeCallResult(Ins, CCAssignFnForReturn(CallConv, isVarArg));
2177
2178 // Copy all of the result registers out of their specified physreg.
2179 for (unsigned i = 0; i != RVLocs.size(); ++i) {
2180 CCValAssign VA = RVLocs[i];
2181
2182 // Pass 'this' value directly from the argument to return value, to avoid
2183 // reg unit interference
2184 if (i == 0 && isThisReturn) {
2185 assert(!VA.needsCustom() && VA.getLocVT() == MVT::i32 &&(static_cast <bool> (!VA.needsCustom() && VA.getLocVT
() == MVT::i32 && "unexpected return calling convention register assignment"
) ? void (0) : __assert_fail ("!VA.needsCustom() && VA.getLocVT() == MVT::i32 && \"unexpected return calling convention register assignment\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 2186, __extension__
__PRETTY_FUNCTION__))
2186 "unexpected return calling convention register assignment")(static_cast <bool> (!VA.needsCustom() && VA.getLocVT
() == MVT::i32 && "unexpected return calling convention register assignment"
) ? void (0) : __assert_fail ("!VA.needsCustom() && VA.getLocVT() == MVT::i32 && \"unexpected return calling convention register assignment\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 2186, __extension__
__PRETTY_FUNCTION__))
;
2187 InVals.push_back(ThisVal);
2188 continue;
2189 }
2190
2191 SDValue Val;
2192 if (VA.needsCustom() &&
2193 (VA.getLocVT() == MVT::f64 || VA.getLocVT() == MVT::v2f64)) {
2194 // Handle f64 or half of a v2f64.
2195 SDValue Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
2196 InFlag);
2197 Chain = Lo.getValue(1);
2198 InFlag = Lo.getValue(2);
2199 VA = RVLocs[++i]; // skip ahead to next loc
2200 SDValue Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
2201 InFlag);
2202 Chain = Hi.getValue(1);
2203 InFlag = Hi.getValue(2);
2204 if (!Subtarget->isLittle())
2205 std::swap (Lo, Hi);
2206 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
2207
2208 if (VA.getLocVT() == MVT::v2f64) {
2209 SDValue Vec = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
2210 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
2211 DAG.getConstant(0, dl, MVT::i32));
2212
2213 VA = RVLocs[++i]; // skip ahead to next loc
2214 Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
2215 Chain = Lo.getValue(1);
2216 InFlag = Lo.getValue(2);
2217 VA = RVLocs[++i]; // skip ahead to next loc
2218 Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
2219 Chain = Hi.getValue(1);
2220 InFlag = Hi.getValue(2);
2221 if (!Subtarget->isLittle())
2222 std::swap (Lo, Hi);
2223 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
2224 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
2225 DAG.getConstant(1, dl, MVT::i32));
2226 }
2227 } else {
2228 Val = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getLocVT(),
2229 InFlag);
2230 Chain = Val.getValue(1);
2231 InFlag = Val.getValue(2);
2232 }
2233
2234 switch (VA.getLocInfo()) {
2235 default: llvm_unreachable("Unknown loc info!")::llvm::llvm_unreachable_internal("Unknown loc info!", "llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2235)
;
2236 case CCValAssign::Full: break;
2237 case CCValAssign::BCvt:
2238 Val = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), Val);
2239 break;
2240 }
2241
2242 // f16 arguments have their size extended to 4 bytes and passed as if they
2243 // had been copied to the LSBs of a 32-bit register.
2244 // For that, it's passed extended to i32 (soft ABI) or to f32 (hard ABI)
2245 if (VA.needsCustom() &&
2246 (VA.getValVT() == MVT::f16 || VA.getValVT() == MVT::bf16))
2247 Val = MoveToHPR(dl, DAG, VA.getLocVT(), VA.getValVT(), Val);
2248
2249 InVals.push_back(Val);
2250 }
2251
2252 return Chain;
2253}
2254
2255std::pair<SDValue, MachinePointerInfo> ARMTargetLowering::computeAddrForCallArg(
2256 const SDLoc &dl, SelectionDAG &DAG, const CCValAssign &VA, SDValue StackPtr,
2257 bool IsTailCall, int SPDiff) const {
2258 SDValue DstAddr;
2259 MachinePointerInfo DstInfo;
2260 int32_t Offset = VA.getLocMemOffset();
2261 MachineFunction &MF = DAG.getMachineFunction();
2262
2263 if (IsTailCall) {
2264 Offset += SPDiff;
2265 auto PtrVT = getPointerTy(DAG.getDataLayout());
2266 int Size = VA.getLocVT().getFixedSizeInBits() / 8;
2267 int FI = MF.getFrameInfo().CreateFixedObject(Size, Offset, true);
2268 DstAddr = DAG.getFrameIndex(FI, PtrVT);
2269 DstInfo =
2270 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI);
2271 } else {
2272 SDValue PtrOff = DAG.getIntPtrConstant(Offset, dl);
2273 DstAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(DAG.getDataLayout()),
2274 StackPtr, PtrOff);
2275 DstInfo =
2276 MachinePointerInfo::getStack(DAG.getMachineFunction(), Offset);
2277 }
2278
2279 return std::make_pair(DstAddr, DstInfo);
2280}
2281
2282void ARMTargetLowering::PassF64ArgInRegs(const SDLoc &dl, SelectionDAG &DAG,
2283 SDValue Chain, SDValue &Arg,
2284 RegsToPassVector &RegsToPass,
2285 CCValAssign &VA, CCValAssign &NextVA,
2286 SDValue &StackPtr,
2287 SmallVectorImpl<SDValue> &MemOpChains,
2288 bool IsTailCall,
2289 int SPDiff) const {
2290 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl,
2291 DAG.getVTList(MVT::i32, MVT::i32), Arg);
2292 unsigned id = Subtarget->isLittle() ? 0 : 1;
2293 RegsToPass.push_back(std::make_pair(VA.getLocReg(), fmrrd.getValue(id)));
2294
2295 if (NextVA.isRegLoc())
2296 RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), fmrrd.getValue(1-id)));
2297 else {
2298 assert(NextVA.isMemLoc())(static_cast <bool> (NextVA.isMemLoc()) ? void (0) : __assert_fail
("NextVA.isMemLoc()", "llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2298, __extension__ __PRETTY_FUNCTION__))
;
2299 if (!StackPtr.getNode())
2300 StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP,
2301 getPointerTy(DAG.getDataLayout()));
2302
2303 SDValue DstAddr;
2304 MachinePointerInfo DstInfo;
2305 std::tie(DstAddr, DstInfo) =
2306 computeAddrForCallArg(dl, DAG, NextVA, StackPtr, IsTailCall, SPDiff);
2307 MemOpChains.push_back(
2308 DAG.getStore(Chain, dl, fmrrd.getValue(1 - id), DstAddr, DstInfo));
2309 }
2310}
2311
2312static bool canGuaranteeTCO(CallingConv::ID CC, bool GuaranteeTailCalls) {
2313 return (CC == CallingConv::Fast && GuaranteeTailCalls) ||
2314 CC == CallingConv::Tail || CC == CallingConv::SwiftTail;
2315}
2316
2317/// LowerCall - Lowering a call into a callseq_start <-
2318/// ARMISD:CALL <- callseq_end chain. Also add input and output parameter
2319/// nodes.
2320SDValue
2321ARMTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2322 SmallVectorImpl<SDValue> &InVals) const {
2323 SelectionDAG &DAG = CLI.DAG;
2324 SDLoc &dl = CLI.DL;
2325 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
2326 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
2327 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
2328 SDValue Chain = CLI.Chain;
2329 SDValue Callee = CLI.Callee;
2330 bool &isTailCall = CLI.IsTailCall;
2331 CallingConv::ID CallConv = CLI.CallConv;
2332 bool doesNotRet = CLI.DoesNotReturn;
2333 bool isVarArg = CLI.IsVarArg;
2334
2335 MachineFunction &MF = DAG.getMachineFunction();
2336 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2337 MachineFunction::CallSiteInfo CSInfo;
2338 bool isStructRet = (Outs.empty()) ? false : Outs[0].Flags.isSRet();
2339 bool isThisReturn = false;
2340 bool isCmseNSCall = false;
2341 bool isSibCall = false;
2342 bool PreferIndirect = false;
2343 bool GuardWithBTI = false;
2344
2345 // Lower 'returns_twice' calls to a pseudo-instruction.
2346 if (CLI.CB && CLI.CB->getAttributes().hasFnAttr(Attribute::ReturnsTwice) &&
2347 !Subtarget->noBTIAtReturnTwice())
2348 GuardWithBTI = AFI->branchTargetEnforcement();
2349
2350 // Determine whether this is a non-secure function call.
2351 if (CLI.CB && CLI.CB->getAttributes().hasFnAttr("cmse_nonsecure_call"))
2352 isCmseNSCall = true;
2353
2354 // Disable tail calls if they're not supported.
2355 if (!Subtarget->supportsTailCall())
2356 isTailCall = false;
2357
2358 // For both the non-secure calls and the returns from a CMSE entry function,
2359 // the function needs to do some extra work afte r the call, or before the
2360 // return, respectively, thus it cannot end with atail call
2361 if (isCmseNSCall || AFI->isCmseNSEntryFunction())
2362 isTailCall = false;
2363
2364 if (isa<GlobalAddressSDNode>(Callee)) {
2365 // If we're optimizing for minimum size and the function is called three or
2366 // more times in this block, we can improve codesize by calling indirectly
2367 // as BLXr has a 16-bit encoding.
2368 auto *GV = cast<GlobalAddressSDNode>(Callee)->getGlobal();
2369 if (CLI.CB) {
2370 auto *BB = CLI.CB->getParent();
2371 PreferIndirect = Subtarget->isThumb() && Subtarget->hasMinSize() &&
2372 count_if(GV->users(), [&BB](const User *U) {
2373 return isa<Instruction>(U) &&
2374 cast<Instruction>(U)->getParent() == BB;
2375 }) > 2;
2376 }
2377 }
2378 if (isTailCall) {
2379 // Check if it's really possible to do a tail call.
2380 isTailCall = IsEligibleForTailCallOptimization(
2381 Callee, CallConv, isVarArg, isStructRet,
2382 MF.getFunction().hasStructRetAttr(), Outs, OutVals, Ins, DAG,
2383 PreferIndirect);
2384
2385 if (isTailCall && !getTargetMachine().Options.GuaranteedTailCallOpt &&
2386 CallConv != CallingConv::Tail && CallConv != CallingConv::SwiftTail)
2387 isSibCall = true;
2388
2389 // We don't support GuaranteedTailCallOpt for ARM, only automatically
2390 // detected sibcalls.
2391 if (isTailCall)
2392 ++NumTailCalls;
2393 }
2394
2395 if (!isTailCall && CLI.CB && CLI.CB->isMustTailCall())
2396 report_fatal_error("failed to perform tail call elimination on a call "
2397 "site marked musttail");
2398 // Analyze operands of the call, assigning locations to each operand.
2399 SmallVector<CCValAssign, 16> ArgLocs;
2400 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
2401 *DAG.getContext());
2402 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForCall(CallConv, isVarArg));
2403
2404 // Get a count of how many bytes are to be pushed on the stack.
2405 unsigned NumBytes = CCInfo.getNextStackOffset();
2406
2407 // SPDiff is the byte offset of the call's argument area from the callee's.
2408 // Stores to callee stack arguments will be placed in FixedStackSlots offset
2409 // by this amount for a tail call. In a sibling call it must be 0 because the
2410 // caller will deallocate the entire stack and the callee still expects its
2411 // arguments to begin at SP+0. Completely unused for non-tail calls.
2412 int SPDiff = 0;
2413
2414 if (isTailCall && !isSibCall) {
2415 auto FuncInfo = MF.getInfo<ARMFunctionInfo>();
2416 unsigned NumReusableBytes = FuncInfo->getArgumentStackSize();
2417
2418 // Since callee will pop argument stack as a tail call, we must keep the
2419 // popped size 16-byte aligned.
2420 Align StackAlign = DAG.getDataLayout().getStackAlignment();
2421 NumBytes = alignTo(NumBytes, StackAlign);
2422
2423 // SPDiff will be negative if this tail call requires more space than we
2424 // would automatically have in our incoming argument space. Positive if we
2425 // can actually shrink the stack.
2426 SPDiff = NumReusableBytes - NumBytes;
2427
2428 // If this call requires more stack than we have available from
2429 // LowerFormalArguments, tell FrameLowering to reserve space for it.
2430 if (SPDiff < 0 && AFI->getArgRegsSaveSize() < (unsigned)-SPDiff)
2431 AFI->setArgRegsSaveSize(-SPDiff);
2432 }
2433
2434 if (isSibCall) {
2435 // For sibling tail calls, memory operands are available in our caller's stack.
2436 NumBytes = 0;
2437 } else {
2438 // Adjust the stack pointer for the new arguments...
2439 // These operations are automatically eliminated by the prolog/epilog pass
2440 Chain = DAG.getCALLSEQ_START(Chain, isTailCall ? 0 : NumBytes, 0, dl);
2441 }
2442
2443 SDValue StackPtr =
2444 DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy(DAG.getDataLayout()));
2445
2446 RegsToPassVector RegsToPass;
2447 SmallVector<SDValue, 8> MemOpChains;
2448
2449 // During a tail call, stores to the argument area must happen after all of
2450 // the function's incoming arguments have been loaded because they may alias.
2451 // This is done by folding in a TokenFactor from LowerFormalArguments, but
2452 // there's no point in doing so repeatedly so this tracks whether that's
2453 // happened yet.
2454 bool AfterFormalArgLoads = false;
2455
2456 // Walk the register/memloc assignments, inserting copies/loads. In the case
2457 // of tail call optimization, arguments are handled later.
2458 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size();
2459 i != e;
2460 ++i, ++realArgIdx) {
2461 CCValAssign &VA = ArgLocs[i];
2462 SDValue Arg = OutVals[realArgIdx];
2463 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
2464 bool isByVal = Flags.isByVal();
2465
2466 // Promote the value if needed.
2467 switch (VA.getLocInfo()) {
2468 default: llvm_unreachable("Unknown loc info!")::llvm::llvm_unreachable_internal("Unknown loc info!", "llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2468)
;
2469 case CCValAssign::Full: break;
2470 case CCValAssign::SExt:
2471 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
2472 break;
2473 case CCValAssign::ZExt:
2474 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
2475 break;
2476 case CCValAssign::AExt:
2477 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
2478 break;
2479 case CCValAssign::BCvt:
2480 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
2481 break;
2482 }
2483
2484 if (isTailCall && VA.isMemLoc() && !AfterFormalArgLoads) {
2485 Chain = DAG.getStackArgumentTokenFactor(Chain);
2486 AfterFormalArgLoads = true;
2487 }
2488
2489 // f16 arguments have their size extended to 4 bytes and passed as if they
2490 // had been copied to the LSBs of a 32-bit register.
2491 // For that, it's passed extended to i32 (soft ABI) or to f32 (hard ABI)
2492 if (VA.needsCustom() &&
2493 (VA.getValVT() == MVT::f16 || VA.getValVT() == MVT::bf16)) {
2494 Arg = MoveFromHPR(dl, DAG, VA.getLocVT(), VA.getValVT(), Arg);
2495 } else {
2496 // f16 arguments could have been extended prior to argument lowering.
2497 // Mask them arguments if this is a CMSE nonsecure call.
2498 auto ArgVT = Outs[realArgIdx].ArgVT;
2499 if (isCmseNSCall && (ArgVT == MVT::f16)) {
2500 auto LocBits = VA.getLocVT().getSizeInBits();
2501 auto MaskValue = APInt::getLowBitsSet(LocBits, ArgVT.getSizeInBits());
2502 SDValue Mask =
2503 DAG.getConstant(MaskValue, dl, MVT::getIntegerVT(LocBits));
2504 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::getIntegerVT(LocBits), Arg);
2505 Arg = DAG.getNode(ISD::AND, dl, MVT::getIntegerVT(LocBits), Arg, Mask);
2506 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
2507 }
2508 }
2509
2510 // f64 and v2f64 might be passed in i32 pairs and must be split into pieces
2511 if (VA.needsCustom() && VA.getLocVT() == MVT::v2f64) {
2512 SDValue Op0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
2513 DAG.getConstant(0, dl, MVT::i32));
2514 SDValue Op1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
2515 DAG.getConstant(1, dl, MVT::i32));
2516
2517 PassF64ArgInRegs(dl, DAG, Chain, Op0, RegsToPass, VA, ArgLocs[++i],
2518 StackPtr, MemOpChains, isTailCall, SPDiff);
2519
2520 VA = ArgLocs[++i]; // skip ahead to next loc
2521 if (VA.isRegLoc()) {
2522 PassF64ArgInRegs(dl, DAG, Chain, Op1, RegsToPass, VA, ArgLocs[++i],
2523 StackPtr, MemOpChains, isTailCall, SPDiff);
2524 } else {
2525 assert(VA.isMemLoc())(static_cast <bool> (VA.isMemLoc()) ? void (0) : __assert_fail
("VA.isMemLoc()", "llvm/lib/Target/ARM/ARMISelLowering.cpp",
2525, __extension__ __PRETTY_FUNCTION__))
;
2526 SDValue DstAddr;
2527 MachinePointerInfo DstInfo;
2528 std::tie(DstAddr, DstInfo) =
2529 computeAddrForCallArg(dl, DAG, VA, StackPtr, isTailCall, SPDiff);
2530 MemOpChains.push_back(DAG.getStore(Chain, dl, Op1, DstAddr, DstInfo));
2531 }
2532 } else if (VA.needsCustom() && VA.getLocVT() == MVT::f64) {
2533 PassF64ArgInRegs(dl, DAG, Chain, Arg, RegsToPass, VA, ArgLocs[++i],
2534 StackPtr, MemOpChains, isTailCall, SPDiff);
2535 } else if (VA.isRegLoc()) {
2536 if (realArgIdx == 0 && Flags.isReturned() && !Flags.isSwiftSelf() &&
2537 Outs[0].VT == MVT::i32) {
2538 assert(VA.getLocVT() == MVT::i32 &&(static_cast <bool> (VA.getLocVT() == MVT::i32 &&
"unexpected calling convention register assignment") ? void (
0) : __assert_fail ("VA.getLocVT() == MVT::i32 && \"unexpected calling convention register assignment\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 2539, __extension__
__PRETTY_FUNCTION__))
2539 "unexpected calling convention register assignment")(static_cast <bool> (VA.getLocVT() == MVT::i32 &&
"unexpected calling convention register assignment") ? void (
0) : __assert_fail ("VA.getLocVT() == MVT::i32 && \"unexpected calling convention register assignment\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 2539, __extension__
__PRETTY_FUNCTION__))
;
2540 assert(!Ins.empty() && Ins[0].VT == MVT::i32 &&(static_cast <bool> (!Ins.empty() && Ins[0].VT ==
MVT::i32 && "unexpected use of 'returned'") ? void (
0) : __assert_fail ("!Ins.empty() && Ins[0].VT == MVT::i32 && \"unexpected use of 'returned'\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 2541, __extension__
__PRETTY_FUNCTION__))
2541 "unexpected use of 'returned'")(static_cast <bool> (!Ins.empty() && Ins[0].VT ==
MVT::i32 && "unexpected use of 'returned'") ? void (
0) : __assert_fail ("!Ins.empty() && Ins[0].VT == MVT::i32 && \"unexpected use of 'returned'\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 2541, __extension__
__PRETTY_FUNCTION__))
;
2542 isThisReturn = true;
2543 }
2544 const TargetOptions &Options = DAG.getTarget().Options;
2545 if (Options.EmitCallSiteInfo)
2546 CSInfo.emplace_back(VA.getLocReg(), i);
2547 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2548 } else if (isByVal) {
2549 assert(VA.isMemLoc())(static_cast <bool> (VA.isMemLoc()) ? void (0) : __assert_fail
("VA.isMemLoc()", "llvm/lib/Target/ARM/ARMISelLowering.cpp",
2549, __extension__ __PRETTY_FUNCTION__))
;
2550 unsigned offset = 0;
2551
2552 // True if this byval aggregate will be split between registers
2553 // and memory.
2554 unsigned ByValArgsCount = CCInfo.getInRegsParamsCount();
2555 unsigned CurByValIdx = CCInfo.getInRegsParamsProcessed();
2556
2557 if (CurByValIdx < ByValArgsCount) {
2558
2559 unsigned RegBegin, RegEnd;
2560 CCInfo.getInRegsParamInfo(CurByValIdx, RegBegin, RegEnd);
2561
2562 EVT PtrVT =
2563 DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
2564 unsigned int i, j;
2565 for (i = 0, j = RegBegin; j < RegEnd; i++, j++) {
2566 SDValue Const = DAG.getConstant(4*i, dl, MVT::i32);
2567 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
2568 SDValue Load =
2569 DAG.getLoad(PtrVT, dl, Chain, AddArg, MachinePointerInfo(),
2570 DAG.InferPtrAlign(AddArg));
2571 MemOpChains.push_back(Load.getValue(1));
2572 RegsToPass.push_back(std::make_pair(j, Load));
2573 }
2574
2575 // If parameter size outsides register area, "offset" value
2576 // helps us to calculate stack slot for remained part properly.
2577 offset = RegEnd - RegBegin;
2578
2579 CCInfo.nextInRegsParam();
2580 }
2581
2582 if (Flags.getByValSize() > 4*offset) {
2583 auto PtrVT = getPointerTy(DAG.getDataLayout());
2584 SDValue Dst;
2585 MachinePointerInfo DstInfo;
2586 std::tie(Dst, DstInfo) =
2587 computeAddrForCallArg(dl, DAG, VA, StackPtr, isTailCall, SPDiff);
2588 SDValue SrcOffset = DAG.getIntPtrConstant(4*offset, dl);
2589 SDValue Src = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, SrcOffset);
2590 SDValue SizeNode = DAG.getConstant(Flags.getByValSize() - 4*offset, dl,
2591 MVT::i32);
2592 SDValue AlignNode =
2593 DAG.getConstant(Flags.getNonZeroByValAlign().value(), dl, MVT::i32);
2594
2595 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
2596 SDValue Ops[] = { Chain, Dst, Src, SizeNode, AlignNode};
2597 MemOpChains.push_back(DAG.getNode(ARMISD::COPY_STRUCT_BYVAL, dl, VTs,
2598 Ops));
2599 }
2600 } else {
2601 assert(VA.isMemLoc())(static_cast <bool> (VA.isMemLoc()) ? void (0) : __assert_fail
("VA.isMemLoc()", "llvm/lib/Target/ARM/ARMISelLowering.cpp",
2601, __extension__ __PRETTY_FUNCTION__))
;
2602 SDValue DstAddr;
2603 MachinePointerInfo DstInfo;
2604 std::tie(DstAddr, DstInfo) =
2605 computeAddrForCallArg(dl, DAG, VA, StackPtr, isTailCall, SPDiff);
2606
2607 SDValue Store = DAG.getStore(Chain, dl, Arg, DstAddr, DstInfo);
2608 MemOpChains.push_back(Store);
2609 }
2610 }
2611
2612 if (!MemOpChains.empty())
2613 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
2614
2615 // Build a sequence of copy-to-reg nodes chained together with token chain
2616 // and flag operands which copy the outgoing args into the appropriate regs.
2617 SDValue InFlag;
2618 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2619 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2620 RegsToPass[i].second, InFlag);
2621 InFlag = Chain.getValue(1);
2622 }
2623
2624 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
2625 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
2626 // node so that legalize doesn't hack it.
2627 bool isDirect = false;
2628
2629 const TargetMachine &TM = getTargetMachine();
2630 const Module *Mod = MF.getFunction().getParent();
2631 const GlobalValue *GV = nullptr;
2632 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
2633 GV = G->getGlobal();
2634 bool isStub =
2635 !TM.shouldAssumeDSOLocal(*Mod, GV) && Subtarget->isTargetMachO();
2636
2637 bool isARMFunc = !Subtarget->isThumb() || (isStub && !Subtarget->isMClass());
2638 bool isLocalARMFunc = false;
2639 auto PtrVt = getPointerTy(DAG.getDataLayout());
2640
2641 if (Subtarget->genLongCalls()) {
2642 assert((!isPositionIndependent() || Subtarget->isTargetWindows()) &&(static_cast <bool> ((!isPositionIndependent() || Subtarget
->isTargetWindows()) && "long-calls codegen is not position independent!"
) ? void (0) : __assert_fail ("(!isPositionIndependent() || Subtarget->isTargetWindows()) && \"long-calls codegen is not position independent!\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 2643, __extension__
__PRETTY_FUNCTION__))
2643 "long-calls codegen is not position independent!")(static_cast <bool> ((!isPositionIndependent() || Subtarget
->isTargetWindows()) && "long-calls codegen is not position independent!"
) ? void (0) : __assert_fail ("(!isPositionIndependent() || Subtarget->isTargetWindows()) && \"long-calls codegen is not position independent!\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 2643, __extension__
__PRETTY_FUNCTION__))
;
2644 // Handle a global address or an external symbol. If it's not one of
2645 // those, the target's already in a register, so we don't need to do
2646 // anything extra.
2647 if (isa<GlobalAddressSDNode>(Callee)) {
2648 // Create a constant pool entry for the callee address
2649 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2650 ARMConstantPoolValue *CPV =
2651 ARMConstantPoolConstant::Create(GV, ARMPCLabelIndex, ARMCP::CPValue, 0);
2652
2653 // Get the address of the callee into a register
2654 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVt, Align(4));
2655 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2656 Callee = DAG.getLoad(
2657 PtrVt, dl, DAG.getEntryNode(), CPAddr,
2658 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
2659 } else if (ExternalSymbolSDNode *S=dyn_cast<ExternalSymbolSDNode>(Callee)) {
2660 const char *Sym = S->getSymbol();
2661
2662 // Create a constant pool entry for the callee address
2663 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2664 ARMConstantPoolValue *CPV =
2665 ARMConstantPoolSymbol::Create(*DAG.getContext(), Sym,
2666 ARMPCLabelIndex, 0);
2667 // Get the address of the callee into a register
2668 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVt, Align(4));
2669 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2670 Callee = DAG.getLoad(
2671 PtrVt, dl, DAG.getEntryNode(), CPAddr,
2672 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
2673 }
2674 } else if (isa<GlobalAddressSDNode>(Callee)) {
2675 if (!PreferIndirect) {
2676 isDirect = true;
2677 bool isDef = GV->isStrongDefinitionForLinker();
2678
2679 // ARM call to a local ARM function is predicable.
2680 isLocalARMFunc = !Subtarget->isThumb() && (isDef || !ARMInterworking);
2681 // tBX takes a register source operand.
2682 if (isStub && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) {
2683 assert(Subtarget->isTargetMachO() && "WrapperPIC use on non-MachO?")(static_cast <bool> (Subtarget->isTargetMachO() &&
"WrapperPIC use on non-MachO?") ? void (0) : __assert_fail (
"Subtarget->isTargetMachO() && \"WrapperPIC use on non-MachO?\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 2683, __extension__
__PRETTY_FUNCTION__))
;
2684 Callee = DAG.getNode(
2685 ARMISD::WrapperPIC, dl, PtrVt,
2686 DAG.getTargetGlobalAddress(GV, dl, PtrVt, 0, ARMII::MO_NONLAZY));
2687 Callee = DAG.getLoad(
2688 PtrVt, dl, DAG.getEntryNode(), Callee,
2689 MachinePointerInfo::getGOT(DAG.getMachineFunction()), MaybeAlign(),
2690 MachineMemOperand::MODereferenceable |
2691 MachineMemOperand::MOInvariant);
2692 } else if (Subtarget->isTargetCOFF()) {
2693 assert(Subtarget->isTargetWindows() &&(static_cast <bool> (Subtarget->isTargetWindows() &&
"Windows is the only supported COFF target") ? void (0) : __assert_fail
("Subtarget->isTargetWindows() && \"Windows is the only supported COFF target\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 2694, __extension__
__PRETTY_FUNCTION__))
2694 "Windows is the only supported COFF target")(static_cast <bool> (Subtarget->isTargetWindows() &&
"Windows is the only supported COFF target") ? void (0) : __assert_fail
("Subtarget->isTargetWindows() && \"Windows is the only supported COFF target\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 2694, __extension__
__PRETTY_FUNCTION__))
;
2695 unsigned TargetFlags = ARMII::MO_NO_FLAG;
2696 if (GV->hasDLLImportStorageClass())
2697 TargetFlags = ARMII::MO_DLLIMPORT;
2698 else if (!TM.shouldAssumeDSOLocal(*GV->getParent(), GV))
2699 TargetFlags = ARMII::MO_COFFSTUB;
2700 Callee = DAG.getTargetGlobalAddress(GV, dl, PtrVt, /*offset=*/0,
2701 TargetFlags);
2702 if (TargetFlags & (ARMII::MO_DLLIMPORT | ARMII::MO_COFFSTUB))
2703 Callee =
2704 DAG.getLoad(PtrVt, dl, DAG.getEntryNode(),
2705 DAG.getNode(ARMISD::Wrapper, dl, PtrVt, Callee),
2706 MachinePointerInfo::getGOT(DAG.getMachineFunction()));
2707 } else {
2708 Callee = DAG.getTargetGlobalAddress(GV, dl, PtrVt, 0, 0);
2709 }
2710 }
2711 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2712 isDirect = true;
2713 // tBX takes a register source operand.
2714 const char *Sym = S->getSymbol();
2715 if (isARMFunc && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) {
2716 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2717 ARMConstantPoolValue *CPV =
2718 ARMConstantPoolSymbol::Create(*DAG.getContext(), Sym,
2719 ARMPCLabelIndex, 4);
2720 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVt, Align(4));
2721 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2722 Callee = DAG.getLoad(
2723 PtrVt, dl, DAG.getEntryNode(), CPAddr,
2724 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
2725 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, dl, MVT::i32);
2726 Callee = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVt, Callee, PICLabel);
2727 } else {
2728 Callee = DAG.getTargetExternalSymbol(Sym, PtrVt, 0);
2729 }
2730 }
2731
2732 if (isCmseNSCall) {
2733 assert(!isARMFunc && !isDirect &&(static_cast <bool> (!isARMFunc && !isDirect &&
"Cannot handle call to ARM function or direct call") ? void (
0) : __assert_fail ("!isARMFunc && !isDirect && \"Cannot handle call to ARM function or direct call\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 2734, __extension__
__PRETTY_FUNCTION__))
2734 "Cannot handle call to ARM function or direct call")(static_cast <bool> (!isARMFunc && !isDirect &&
"Cannot handle call to ARM function or direct call") ? void (
0) : __assert_fail ("!isARMFunc && !isDirect && \"Cannot handle call to ARM function or direct call\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 2734, __extension__
__PRETTY_FUNCTION__))
;
2735 if (NumBytes > 0) {
2736 DiagnosticInfoUnsupported Diag(DAG.getMachineFunction().getFunction(),
2737 "call to non-secure function would "
2738 "require passing arguments on stack",
2739 dl.getDebugLoc());
2740 DAG.getContext()->diagnose(Diag);
2741 }
2742 if (isStructRet) {
2743 DiagnosticInfoUnsupported Diag(
2744 DAG.getMachineFunction().getFunction(),
2745 "call to non-secure function would return value through pointer",
2746 dl.getDebugLoc());
2747 DAG.getContext()->diagnose(Diag);
2748 }
2749 }
2750
2751 // FIXME: handle tail calls differently.
2752 unsigned CallOpc;
2753 if (Subtarget->isThumb()) {
2754 if (GuardWithBTI)
2755 CallOpc = ARMISD::t2CALL_BTI;
2756 else if (isCmseNSCall)
2757 CallOpc = ARMISD::tSECALL;
2758 else if ((!isDirect || isARMFunc) && !Subtarget->hasV5TOps())
2759 CallOpc = ARMISD::CALL_NOLINK;
2760 else
2761 CallOpc = ARMISD::CALL;
2762 } else {
2763 if (!isDirect && !Subtarget->hasV5TOps())
2764 CallOpc = ARMISD::CALL_NOLINK;
2765 else if (doesNotRet && isDirect && Subtarget->hasRetAddrStack() &&
2766 // Emit regular call when code size is the priority
2767 !Subtarget->hasMinSize())
2768 // "mov lr, pc; b _foo" to avoid confusing the RSP
2769 CallOpc = ARMISD::CALL_NOLINK;
2770 else
2771 CallOpc = isLocalARMFunc ? ARMISD::CALL_PRED : ARMISD::CALL;
2772 }
2773
2774 // We don't usually want to end the call-sequence here because we would tidy
2775 // the frame up *after* the call, however in the ABI-changing tail-call case
2776 // we've carefully laid out the parameters so that when sp is reset they'll be
2777 // in the correct location.
2778 if (isTailCall && !isSibCall) {
2779 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, dl, true),
2780 DAG.getIntPtrConstant(0, dl, true), InFlag, dl);
2781 InFlag = Chain.getValue(1);
2782 }
2783
2784 std::vector<SDValue> Ops;
2785 Ops.push_back(Chain);
2786 Ops.push_back(Callee);
2787
2788 if (isTailCall) {
2789 Ops.push_back(DAG.getTargetConstant(SPDiff, dl, MVT::i32));
2790 }
2791
2792 // Add argument registers to the end of the list so that they are known live
2793 // into the call.
2794 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2795 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2796 RegsToPass[i].second.getValueType()));
2797
2798 // Add a register mask operand representing the call-preserved registers.
2799 const uint32_t *Mask;
2800 const ARMBaseRegisterInfo *ARI = Subtarget->getRegisterInfo();
2801 if (isThisReturn) {
2802 // For 'this' returns, use the R0-preserving mask if applicable
2803 Mask = ARI->getThisReturnPreservedMask(MF, CallConv);
2804 if (!Mask) {
2805 // Set isThisReturn to false if the calling convention is not one that
2806 // allows 'returned' to be modeled in this way, so LowerCallResult does
2807 // not try to pass 'this' straight through
2808 isThisReturn = false;
2809 Mask = ARI->getCallPreservedMask(MF, CallConv);
2810 }
2811 } else
2812 Mask = ARI->getCallPreservedMask(MF, CallConv);
2813
2814 assert(Mask && "Missing call preserved mask for calling convention")(static_cast <bool> (Mask && "Missing call preserved mask for calling convention"
) ? void (0) : __assert_fail ("Mask && \"Missing call preserved mask for calling convention\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 2814, __extension__
__PRETTY_FUNCTION__))
;
2815 Ops.push_back(DAG.getRegisterMask(Mask));
2816
2817 if (InFlag.getNode())
2818 Ops.push_back(InFlag);
2819
2820 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2821 if (isTailCall) {
2822 MF.getFrameInfo().setHasTailCall();
2823 SDValue Ret = DAG.getNode(ARMISD::TC_RETURN, dl, NodeTys, Ops);
2824 DAG.addCallSiteInfo(Ret.getNode(), std::move(CSInfo));
2825 return Ret;
2826 }
2827
2828 // Returns a chain and a flag for retval copy to use.
2829 Chain = DAG.getNode(CallOpc, dl, NodeTys, Ops);
2830 DAG.addNoMergeSiteInfo(Chain.getNode(), CLI.NoMerge);
2831 InFlag = Chain.getValue(1);
2832 DAG.addCallSiteInfo(Chain.getNode(), std::move(CSInfo));
2833
2834 // If we're guaranteeing tail-calls will be honoured, the callee must
2835 // pop its own argument stack on return. But this call is *not* a tail call so
2836 // we need to undo that after it returns to restore the status-quo.
2837 bool TailCallOpt = getTargetMachine().Options.GuaranteedTailCallOpt;
2838 uint64_t CalleePopBytes =
2839 canGuaranteeTCO(CallConv, TailCallOpt) ? alignTo(NumBytes, 16) : -1ULL;
2840
2841 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, dl, true),
2842 DAG.getIntPtrConstant(CalleePopBytes, dl, true),
2843 InFlag, dl);
2844 if (!Ins.empty())
2845 InFlag = Chain.getValue(1);
2846
2847 // Handle result values, copying them out of physregs into vregs that we
2848 // return.
2849 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins, dl, DAG,
2850 InVals, isThisReturn,
2851 isThisReturn ? OutVals[0] : SDValue());
2852}
2853
2854/// HandleByVal - Every parameter *after* a byval parameter is passed
2855/// on the stack. Remember the next parameter register to allocate,
2856/// and then confiscate the rest of the parameter registers to insure
2857/// this.
2858void ARMTargetLowering::HandleByVal(CCState *State, unsigned &Size,
2859 Align Alignment) const {
2860 // Byval (as with any stack) slots are always at least 4 byte aligned.
2861 Alignment = std::max(Alignment, Align(4));
2862
2863 unsigned Reg = State->AllocateReg(GPRArgRegs);
2864 if (!Reg)
2865 return;
2866
2867 unsigned AlignInRegs = Alignment.value() / 4;
2868 unsigned Waste = (ARM::R4 - Reg) % AlignInRegs;
2869 for (unsigned i = 0; i < Waste; ++i)
2870 Reg = State->AllocateReg(GPRArgRegs);
2871
2872 if (!Reg)
2873 return;
2874
2875 unsigned Excess = 4 * (ARM::R4 - Reg);
2876
2877 // Special case when NSAA != SP and parameter size greater than size of
2878 // all remained GPR regs. In that case we can't split parameter, we must
2879 // send it to stack. We also must set NCRN to R4, so waste all
2880 // remained registers.
2881 const unsigned NSAAOffset = State->getNextStackOffset();
2882 if (NSAAOffset != 0 && Size > Excess) {
2883 while (State->AllocateReg(GPRArgRegs))
2884 ;
2885 return;
2886 }
2887
2888 // First register for byval parameter is the first register that wasn't
2889 // allocated before this method call, so it would be "reg".
2890 // If parameter is small enough to be saved in range [reg, r4), then
2891 // the end (first after last) register would be reg + param-size-in-regs,
2892 // else parameter would be splitted between registers and stack,
2893 // end register would be r4 in this case.
2894 unsigned ByValRegBegin = Reg;
2895 unsigned ByValRegEnd = std::min<unsigned>(Reg + Size / 4, ARM::R4);
2896 State->addInRegsParamInfo(ByValRegBegin, ByValRegEnd);
2897 // Note, first register is allocated in the beginning of function already,
2898 // allocate remained amount of registers we need.
2899 for (unsigned i = Reg + 1; i != ByValRegEnd; ++i)
2900 State->AllocateReg(GPRArgRegs);
2901 // A byval parameter that is split between registers and memory needs its
2902 // size truncated here.
2903 // In the case where the entire structure fits in registers, we set the
2904 // size in memory to zero.
2905 Size = std::max<int>(Size - Excess, 0);
2906}
2907
2908/// MatchingStackOffset - Return true if the given stack call argument is
2909/// already available in the same position (relatively) of the caller's
2910/// incoming argument stack.
2911static
2912bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
2913 MachineFrameInfo &MFI, const MachineRegisterInfo *MRI,
2914 const TargetInstrInfo *TII) {
2915 unsigned Bytes = Arg.getValueSizeInBits() / 8;
2916 int FI = std::numeric_limits<int>::max();
2917 if (Arg.getOpcode() == ISD::CopyFromReg) {
2918 Register VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
2919 if (!Register::isVirtualRegister(VR))
2920 return false;
2921 MachineInstr *Def = MRI->getVRegDef(VR);
2922 if (!Def)
2923 return false;
2924 if (!Flags.isByVal()) {
2925 if (!TII->isLoadFromStackSlot(*Def, FI))
2926 return false;
2927 } else {
2928 return false;
2929 }
2930 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
2931 if (Flags.isByVal())
2932 // ByVal argument is passed in as a pointer but it's now being
2933 // dereferenced. e.g.
2934 // define @foo(%struct.X* %A) {
2935 // tail call @bar(%struct.X* byval %A)
2936 // }
2937 return false;
2938 SDValue Ptr = Ld->getBasePtr();
2939 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
2940 if (!FINode)
2941 return false;
2942 FI = FINode->getIndex();
2943 } else
2944 return false;
2945
2946 assert(FI != std::numeric_limits<int>::max())(static_cast <bool> (FI != std::numeric_limits<int>
::max()) ? void (0) : __assert_fail ("FI != std::numeric_limits<int>::max()"
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 2946, __extension__
__PRETTY_FUNCTION__))
;
2947 if (!MFI.isFixedObjectIndex(FI))
2948 return false;
2949 return Offset == MFI.getObjectOffset(FI) && Bytes == MFI.getObjectSize(FI);
2950}
2951
2952/// IsEligibleForTailCallOptimization - Check whether the call is eligible
2953/// for tail call optimization. Targets which want to do tail call
2954/// optimization should implement this function.
2955bool ARMTargetLowering::IsEligibleForTailCallOptimization(
2956 SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg,
2957 bool isCalleeStructRet, bool isCallerStructRet,
2958 const SmallVectorImpl<ISD::OutputArg> &Outs,
2959 const SmallVectorImpl<SDValue> &OutVals,
2960 const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG,
2961 const bool isIndirect) const {
2962 MachineFunction &MF = DAG.getMachineFunction();
2963 const Function &CallerF = MF.getFunction();
2964 CallingConv::ID CallerCC = CallerF.getCallingConv();
2965
2966 assert(Subtarget->supportsTailCall())(static_cast <bool> (Subtarget->supportsTailCall()) ?
void (0) : __assert_fail ("Subtarget->supportsTailCall()"
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 2966, __extension__
__PRETTY_FUNCTION__))
;
2967
2968 // Indirect tail calls cannot be optimized for Thumb1 if the args
2969 // to the call take up r0-r3. The reason is that there are no legal registers
2970 // left to hold the pointer to the function to be called.
2971 // Similarly, if the function uses return address sign and authentication,
2972 // r12 is needed to hold the PAC and is not available to hold the callee
2973 // address.
2974 if (Outs.size() >= 4 &&
2975 (!isa<GlobalAddressSDNode>(Callee.getNode()) || isIndirect)) {
2976 if (Subtarget->isThumb1Only())
2977 return false;
2978 // Conservatively assume the function spills LR.
2979 if (MF.getInfo<ARMFunctionInfo>()->shouldSignReturnAddress(true))
2980 return false;
2981 }
2982
2983 // Look for obvious safe cases to perform tail call optimization that do not
2984 // require ABI changes. This is what gcc calls sibcall.
2985
2986 // Exception-handling functions need a special set of instructions to indicate
2987 // a return to the hardware. Tail-calling another function would probably
2988 // break this.
2989 if (CallerF.hasFnAttribute("interrupt"))
2990 return false;
2991
2992 if (canGuaranteeTCO(CalleeCC, getTargetMachine().Options.GuaranteedTailCallOpt))
2993 return CalleeCC == CallerCC;
2994
2995 // Also avoid sibcall optimization if either caller or callee uses struct
2996 // return semantics.
2997 if (isCalleeStructRet || isCallerStructRet)
2998 return false;
2999
3000 // Externally-defined functions with weak linkage should not be
3001 // tail-called on ARM when the OS does not support dynamic
3002 // pre-emption of symbols, as the AAELF spec requires normal calls
3003 // to undefined weak functions to be replaced with a NOP or jump to the
3004 // next instruction. The behaviour of branch instructions in this
3005 // situation (as used for tail calls) is implementation-defined, so we
3006 // cannot rely on the linker replacing the tail call with a return.
3007 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
3008 const GlobalValue *GV = G->getGlobal();
3009 const Triple &TT = getTargetMachine().getTargetTriple();
3010 if (GV->hasExternalWeakLinkage() &&
3011 (!TT.isOSWindows() || TT.isOSBinFormatELF() || TT.isOSBinFormatMachO()))
3012 return false;
3013 }
3014
3015 // Check that the call results are passed in the same way.
3016 LLVMContext &C = *DAG.getContext();
3017 if (!CCState::resultsCompatible(
3018 getEffectiveCallingConv(CalleeCC, isVarArg),
3019 getEffectiveCallingConv(CallerCC, CallerF.isVarArg()), MF, C, Ins,
3020 CCAssignFnForReturn(CalleeCC, isVarArg),
3021 CCAssignFnForReturn(CallerCC, CallerF.isVarArg())))
3022 return false;
3023 // The callee has to preserve all registers the caller needs to preserve.
3024 const ARMBaseRegisterInfo *TRI = Subtarget->getRegisterInfo();
3025 const uint32_t *CallerPreserved = TRI->getCallPreservedMask(MF, CallerCC);
3026 if (CalleeCC != CallerCC) {
3027 const uint32_t *CalleePreserved = TRI->getCallPreservedMask(MF, CalleeCC);
3028 if (!TRI->regmaskSubsetEqual(CallerPreserved, CalleePreserved))
3029 return false;
3030 }
3031
3032 // If Caller's vararg or byval argument has been split between registers and
3033 // stack, do not perform tail call, since part of the argument is in caller's
3034 // local frame.
3035 const ARMFunctionInfo *AFI_Caller = MF.getInfo<ARMFunctionInfo>();
3036 if (AFI_Caller->getArgRegsSaveSize())
3037 return false;
3038
3039 // If the callee takes no arguments then go on to check the results of the
3040 // call.
3041 if (!Outs.empty()) {
3042 // Check if stack adjustment is needed. For now, do not do this if any
3043 // argument is passed on the stack.
3044 SmallVector<CCValAssign, 16> ArgLocs;
3045 CCState CCInfo(CalleeCC, isVarArg, MF, ArgLocs, C);
3046 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForCall(CalleeCC, isVarArg));
3047 if (CCInfo.getNextStackOffset()) {
3048 // Check if the arguments are already laid out in the right way as
3049 // the caller's fixed stack objects.
3050 MachineFrameInfo &MFI = MF.getFrameInfo();
3051 const MachineRegisterInfo *MRI = &MF.getRegInfo();
3052 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
3053 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size();
3054 i != e;
3055 ++i, ++realArgIdx) {
3056 CCValAssign &VA = ArgLocs[i];
3057 EVT RegVT = VA.getLocVT();
3058 SDValue Arg = OutVals[realArgIdx];
3059 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
3060 if (VA.getLocInfo() == CCValAssign::Indirect)
3061 return false;
3062 if (VA.needsCustom() && (RegVT == MVT::f64 || RegVT == MVT::v2f64)) {
3063 // f64 and vector types are split into multiple registers or
3064 // register/stack-slot combinations. The types will not match
3065 // the registers; give up on memory f64 refs until we figure
3066 // out what to do about this.
3067 if (!VA.isRegLoc())
3068 return false;
3069 if (!ArgLocs[++i].isRegLoc())
3070 return false;
3071 if (RegVT == MVT::v2f64) {
3072 if (!ArgLocs[++i].isRegLoc())
3073 return false;
3074 if (!ArgLocs[++i].isRegLoc())
3075 return false;
3076 }
3077 } else if (!VA.isRegLoc()) {
3078 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
3079 MFI, MRI, TII))
3080 return false;
3081 }
3082 }
3083 }
3084
3085 const MachineRegisterInfo &MRI = MF.getRegInfo();
3086 if (!parametersInCSRMatch(MRI, CallerPreserved, ArgLocs, OutVals))
3087 return false;
3088 }
3089
3090 return true;
3091}
3092
3093bool
3094ARMTargetLowering::CanLowerReturn(CallingConv::ID CallConv,
3095 MachineFunction &MF, bool isVarArg,
3096 const SmallVectorImpl<ISD::OutputArg> &Outs,
3097 LLVMContext &Context) const {
3098 SmallVector<CCValAssign, 16> RVLocs;
3099 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
3100 return CCInfo.CheckReturn(Outs, CCAssignFnForReturn(CallConv, isVarArg));
3101}
3102
3103static SDValue LowerInterruptReturn(SmallVectorImpl<SDValue> &RetOps,
3104 const SDLoc &DL, SelectionDAG &DAG) {
3105 const MachineFunction &MF = DAG.getMachineFunction();
3106 const Function &F = MF.getFunction();
3107
3108 StringRef IntKind = F.getFnAttribute("interrupt").getValueAsString();
3109
3110 // See ARM ARM v7 B1.8.3. On exception entry LR is set to a possibly offset
3111 // version of the "preferred return address". These offsets affect the return
3112 // instruction if this is a return from PL1 without hypervisor extensions.
3113 // IRQ/FIQ: +4 "subs pc, lr, #4"
3114 // SWI: 0 "subs pc, lr, #0"
3115 // ABORT: +4 "subs pc, lr, #4"
3116 // UNDEF: +4/+2 "subs pc, lr, #0"
3117 // UNDEF varies depending on where the exception came from ARM or Thumb
3118 // mode. Alongside GCC, we throw our hands up in disgust and pretend it's 0.
3119
3120 int64_t LROffset;
3121 if (IntKind == "" || IntKind == "IRQ" || IntKind == "FIQ" ||
3122 IntKind == "ABORT")
3123 LROffset = 4;
3124 else if (IntKind == "SWI" || IntKind == "UNDEF")
3125 LROffset = 0;
3126 else
3127 report_fatal_error("Unsupported interrupt attribute. If present, value "
3128 "must be one of: IRQ, FIQ, SWI, ABORT or UNDEF");
3129
3130 RetOps.insert(RetOps.begin() + 1,
3131 DAG.getConstant(LROffset, DL, MVT::i32, false));
3132
3133 return DAG.getNode(ARMISD::INTRET_FLAG, DL, MVT::Other, RetOps);
3134}
3135
3136SDValue
3137ARMTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
3138 bool isVarArg,
3139 const SmallVectorImpl<ISD::OutputArg> &Outs,
3140 const SmallVectorImpl<SDValue> &OutVals,
3141 const SDLoc &dl, SelectionDAG &DAG) const {
3142 // CCValAssign - represent the assignment of the return value to a location.
3143 SmallVector<CCValAssign, 16> RVLocs;
3144
3145 // CCState - Info about the registers and stack slots.
3146 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
3147 *DAG.getContext());
3148
3149 // Analyze outgoing return values.
3150 CCInfo.AnalyzeReturn(Outs, CCAssignFnForReturn(CallConv, isVarArg));
3151
3152 SDValue Flag;
3153 SmallVector<SDValue, 4> RetOps;
3154 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
3155 bool isLittleEndian = Subtarget->isLittle();
3156
3157 MachineFunction &MF = DAG.getMachineFunction();
3158 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
3159 AFI->setReturnRegsCount(RVLocs.size());
3160
3161 // Report error if cmse entry function returns structure through first ptr arg.
3162 if (AFI->isCmseNSEntryFunction() && MF.getFunction().hasStructRetAttr()) {
3163 // Note: using an empty SDLoc(), as the first line of the function is a
3164 // better place to report than the last line.
3165 DiagnosticInfoUnsupported Diag(
3166 DAG.getMachineFunction().getFunction(),
3167 "secure entry function would return value through pointer",
3168 SDLoc().getDebugLoc());
3169 DAG.getContext()->diagnose(Diag);
3170 }
3171
3172 // Copy the result values into the output registers.
3173 for (unsigned i = 0, realRVLocIdx = 0;
3174 i != RVLocs.size();
3175 ++i, ++realRVLocIdx) {
3176 CCValAssign &VA = RVLocs[i];
3177 assert(VA.isRegLoc() && "Can only return in registers!")(static_cast <bool> (VA.isRegLoc() && "Can only return in registers!"
) ? void (0) : __assert_fail ("VA.isRegLoc() && \"Can only return in registers!\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 3177, __extension__
__PRETTY_FUNCTION__))
;
3178
3179 SDValue Arg = OutVals[realRVLocIdx];
3180 bool ReturnF16 = false;
3181
3182 if (Subtarget->hasFullFP16() && Subtarget->isTargetHardFloat()) {
3183 // Half-precision return values can be returned like this:
3184 //
3185 // t11 f16 = fadd ...
3186 // t12: i16 = bitcast t11
3187 // t13: i32 = zero_extend t12
3188 // t14: f32 = bitcast t13 <~~~~~~~ Arg
3189 //
3190 // to avoid code generation for bitcasts, we simply set Arg to the node
3191 // that produces the f16 value, t11 in this case.
3192 //
3193 if (Arg.getValueType() == MVT::f32 && Arg.getOpcode() == ISD::BITCAST) {
3194 SDValue ZE = Arg.getOperand(0);
3195 if (ZE.getOpcode() == ISD::ZERO_EXTEND && ZE.getValueType() == MVT::i32) {
3196 SDValue BC = ZE.getOperand(0);
3197 if (BC.getOpcode() == ISD::BITCAST && BC.getValueType() == MVT::i16) {
3198 Arg = BC.getOperand(0);
3199 ReturnF16 = true;
3200 }
3201 }
3202 }
3203 }
3204
3205 switch (VA.getLocInfo()) {
3206 default: llvm_unreachable("Unknown loc info!")::llvm::llvm_unreachable_internal("Unknown loc info!", "llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3206)
;
3207 case CCValAssign::Full: break;
3208 case CCValAssign::BCvt:
3209 if (!ReturnF16)
3210 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
3211 break;
3212 }
3213
3214 // Mask f16 arguments if this is a CMSE nonsecure entry.
3215 auto RetVT = Outs[realRVLocIdx].ArgVT;
3216 if (AFI->isCmseNSEntryFunction() && (RetVT == MVT::f16)) {
3217 if (VA.needsCustom() && VA.getValVT() == MVT::f16) {
3218 Arg = MoveFromHPR(dl, DAG, VA.getLocVT(), VA.getValVT(), Arg);
3219 } else {
3220 auto LocBits = VA.getLocVT().getSizeInBits();
3221 auto MaskValue = APInt::getLowBitsSet(LocBits, RetVT.getSizeInBits());
3222 SDValue Mask =
3223 DAG.getConstant(MaskValue, dl, MVT::getIntegerVT(LocBits));
3224 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::getIntegerVT(LocBits), Arg);
3225 Arg = DAG.getNode(ISD::AND, dl, MVT::getIntegerVT(LocBits), Arg, Mask);
3226 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
3227 }
3228 }
3229
3230 if (VA.needsCustom() &&
3231 (VA.getLocVT() == MVT::v2f64 || VA.getLocVT() == MVT::f64)) {
3232 if (VA.getLocVT() == MVT::v2f64) {
3233 // Extract the first half and return it in two registers.
3234 SDValue Half = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
3235 DAG.getConstant(0, dl, MVT::i32));
3236 SDValue HalfGPRs = DAG.getNode(ARMISD::VMOVRRD, dl,
3237 DAG.getVTList(MVT::i32, MVT::i32), Half);
3238
3239 Chain =
3240 DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
3241 HalfGPRs.getValue(isLittleEndian ? 0 : 1), Flag);
3242 Flag = Chain.getValue(1);
3243 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
3244 VA = RVLocs[++i]; // skip ahead to next loc
3245 Chain =
3246 DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
3247 HalfGPRs.getValue(isLittleEndian ? 1 : 0), Flag);
3248 Flag = Chain.getValue(1);
3249 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
3250 VA = RVLocs[++i]; // skip ahead to next loc
3251
3252 // Extract the 2nd half and fall through to handle it as an f64 value.
3253 Arg = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
3254 DAG.getConstant(1, dl, MVT::i32));
3255 }
3256 // Legalize ret f64 -> ret 2 x i32. We always have fmrrd if f64 is
3257 // available.
3258 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl,
3259 DAG.getVTList(MVT::i32, MVT::i32), Arg);
3260 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
3261 fmrrd.getValue(isLittleEndian ? 0 : 1), Flag);
3262 Flag = Chain.getValue(1);
3263 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
3264 VA = RVLocs[++i]; // skip ahead to next loc
3265 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
3266 fmrrd.getValue(isLittleEndian ? 1 : 0), Flag);
3267 } else
3268 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag);
3269
3270 // Guarantee that all emitted copies are
3271 // stuck together, avoiding something bad.
3272 Flag = Chain.getValue(1);
3273 RetOps.push_back(DAG.getRegister(
3274 VA.getLocReg(), ReturnF16 ? Arg.getValueType() : VA.getLocVT()));
3275 }
3276 const ARMBaseRegisterInfo *TRI = Subtarget->getRegisterInfo();
3277 const MCPhysReg *I =
3278 TRI->getCalleeSavedRegsViaCopy(&DAG.getMachineFunction());
3279 if (I) {
3280 for (; *I; ++I) {
3281 if (ARM::GPRRegClass.contains(*I))
3282 RetOps.push_back(DAG.getRegister(*I, MVT::i32));
3283 else if (ARM::DPRRegClass.contains(*I))
3284 RetOps.push_back(DAG.getRegister(*I, MVT::getFloatingPointVT(64)));
3285 else
3286 llvm_unreachable("Unexpected register class in CSRsViaCopy!")::llvm::llvm_unreachable_internal("Unexpected register class in CSRsViaCopy!"
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 3286)
;
3287 }
3288 }
3289
3290 // Update chain and glue.
3291 RetOps[0] = Chain;
3292 if (Flag.getNode())
3293 RetOps.push_back(Flag);
3294
3295 // CPUs which aren't M-class use a special sequence to return from
3296 // exceptions (roughly, any instruction setting pc and cpsr simultaneously,
3297 // though we use "subs pc, lr, #N").
3298 //
3299 // M-class CPUs actually use a normal return sequence with a special
3300 // (hardware-provided) value in LR, so the normal code path works.
3301 if (DAG.getMachineFunction().getFunction().hasFnAttribute("interrupt") &&
3302 !Subtarget->isMClass()) {
3303 if (Subtarget->isThumb1Only())
3304 report_fatal_error("interrupt attribute is not supported in Thumb1");
3305 return LowerInterruptReturn(RetOps, dl, DAG);
3306 }
3307
3308 ARMISD::NodeType RetNode = AFI->isCmseNSEntryFunction() ? ARMISD::SERET_FLAG :
3309 ARMISD::RET_FLAG;
3310 return DAG.getNode(RetNode, dl, MVT::Other, RetOps);
3311}
3312
3313bool ARMTargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
3314 if (N->getNumValues() != 1)
3315 return false;
3316 if (!N->hasNUsesOfValue(1, 0))
3317 return false;
3318
3319 SDValue TCChain = Chain;
3320 SDNode *Copy = *N->use_begin();
3321 if (Copy->getOpcode() == ISD::CopyToReg) {
3322 // If the copy has a glue operand, we conservatively assume it isn't safe to
3323 // perform a tail call.
3324 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
3325 return false;
3326 TCChain = Copy->getOperand(0);
3327 } else if (Copy->getOpcode() == ARMISD::VMOVRRD) {
3328 SDNode *VMov = Copy;
3329 // f64 returned in a pair of GPRs.
3330 SmallPtrSet<SDNode*, 2> Copies;
3331 for (SDNode *U : VMov->uses()) {
3332 if (U->getOpcode() != ISD::CopyToReg)
3333 return false;
3334 Copies.insert(U);
3335 }
3336 if (Copies.size() > 2)
3337 return false;
3338
3339 for (SDNode *U : VMov->uses()) {
3340 SDValue UseChain = U->getOperand(0);
3341 if (Copies.count(UseChain.getNode()))
3342 // Second CopyToReg
3343 Copy = U;
3344 else {
3345 // We are at the top of this chain.
3346 // If the copy has a glue operand, we conservatively assume it
3347 // isn't safe to perform a tail call.
3348 if (U->getOperand(U->getNumOperands() - 1).getValueType() == MVT::Glue)
3349 return false;
3350 // First CopyToReg
3351 TCChain = UseChain;
3352 }
3353 }
3354 } else if (Copy->getOpcode() == ISD::BITCAST) {
3355 // f32 returned in a single GPR.
3356 if (!Copy->hasOneUse())
3357 return false;
3358 Copy = *Copy->use_begin();
3359 if (Copy->getOpcode() != ISD::CopyToReg || !Copy->hasNUsesOfValue(1, 0))
3360 return false;
3361 // If the copy has a glue operand, we conservatively assume it isn't safe to
3362 // perform a tail call.
3363 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
3364 return false;
3365 TCChain = Copy->getOperand(0);
3366 } else {
3367 return false;
3368 }
3369
3370 bool HasRet = false;
3371 for (const SDNode *U : Copy->uses()) {
3372 if (U->getOpcode() != ARMISD::RET_FLAG &&
3373 U->getOpcode() != ARMISD::INTRET_FLAG)
3374 return false;
3375 HasRet = true;
3376 }
3377
3378 if (!HasRet)
3379 return false;
3380
3381 Chain = TCChain;
3382 return true;
3383}
3384
3385bool ARMTargetLowering::mayBeEmittedAsTailCall(const CallInst *CI) const {
3386 if (!Subtarget->supportsTailCall())
3387 return false;
3388
3389 if (!CI->isTailCall())
3390 return false;
3391
3392 return true;
3393}
3394
3395// Trying to write a 64 bit value so need to split into two 32 bit values first,
3396// and pass the lower and high parts through.
3397static SDValue LowerWRITE_REGISTER(SDValue Op, SelectionDAG &DAG) {
3398 SDLoc DL(Op);
3399 SDValue WriteValue = Op->getOperand(2);
3400
3401 // This function is only supposed to be called for i64 type argument.
3402 assert(WriteValue.getValueType() == MVT::i64(static_cast <bool> (WriteValue.getValueType() == MVT::
i64 && "LowerWRITE_REGISTER called for non-i64 type argument."
) ? void (0) : __assert_fail ("WriteValue.getValueType() == MVT::i64 && \"LowerWRITE_REGISTER called for non-i64 type argument.\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 3403, __extension__
__PRETTY_FUNCTION__))
3403 && "LowerWRITE_REGISTER called for non-i64 type argument.")(static_cast <bool> (WriteValue.getValueType() == MVT::
i64 && "LowerWRITE_REGISTER called for non-i64 type argument."
) ? void (0) : __assert_fail ("WriteValue.getValueType() == MVT::i64 && \"LowerWRITE_REGISTER called for non-i64 type argument.\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 3403, __extension__
__PRETTY_FUNCTION__))
;
3404
3405 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, WriteValue,
3406 DAG.getConstant(0, DL, MVT::i32));
3407 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, WriteValue,
3408 DAG.getConstant(1, DL, MVT::i32));
3409 SDValue Ops[] = { Op->getOperand(0), Op->getOperand(1), Lo, Hi };
3410 return DAG.getNode(ISD::WRITE_REGISTER, DL, MVT::Other, Ops);
3411}
3412
3413// ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
3414// their target counterpart wrapped in the ARMISD::Wrapper node. Suppose N is
3415// one of the above mentioned nodes. It has to be wrapped because otherwise
3416// Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
3417// be used to form addressing mode. These wrapped nodes will be selected
3418// into MOVi.
3419SDValue ARMTargetLowering::LowerConstantPool(SDValue Op,
3420 SelectionDAG &DAG) const {
3421 EVT PtrVT = Op.getValueType();
3422 // FIXME there is no actual debug info here
3423 SDLoc dl(Op);
3424 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
3425 SDValue Res;
3426
3427 // When generating execute-only code Constant Pools must be promoted to the
3428 // global data section. It's a bit ugly that we can't share them across basic
3429 // blocks, but this way we guarantee that execute-only behaves correct with
3430 // position-independent addressing modes.
3431 if (Subtarget->genExecuteOnly()) {
3432 auto AFI = DAG.getMachineFunction().getInfo<ARMFunctionInfo>();
3433 auto T = const_cast<Type*>(CP->getType());
3434 auto C = const_cast<Constant*>(CP->getConstVal());
3435 auto M = const_cast<Module*>(DAG.getMachineFunction().
3436 getFunction().getParent());
3437 auto GV = new GlobalVariable(
3438 *M, T, /*isConstant=*/true, GlobalVariable::InternalLinkage, C,
3439 Twine(DAG.getDataLayout().getPrivateGlobalPrefix()) + "CP" +
3440 Twine(DAG.getMachineFunction().getFunctionNumber()) + "_" +
3441 Twine(AFI->createPICLabelUId())
3442 );
3443 SDValue GA = DAG.getTargetGlobalAddress(dyn_cast<GlobalValue>(GV),
3444 dl, PtrVT);
3445 return LowerGlobalAddress(GA, DAG);
3446 }
3447
3448 if (CP->isMachineConstantPoolEntry())
3449 Res =
3450 DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT, CP->getAlign());
3451 else
3452 Res = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CP->getAlign());
3453 return DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Res);
3454}
3455
3456unsigned ARMTargetLowering::getJumpTableEncoding() const {
3457 return MachineJumpTableInfo::EK_Inline;
3458}
3459
3460SDValue ARMTargetLowering::LowerBlockAddress(SDValue Op,
3461 SelectionDAG &DAG) const {
3462 MachineFunction &MF = DAG.getMachineFunction();
3463 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
3464 unsigned ARMPCLabelIndex = 0;
3465 SDLoc DL(Op);
3466 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3467 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
3468 SDValue CPAddr;
3469 bool IsPositionIndependent = isPositionIndependent() || Subtarget->isROPI();
3470 if (!IsPositionIndependent) {
3471 CPAddr = DAG.getTargetConstantPool(BA, PtrVT, Align(4));
3472 } else {
3473 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8;
3474 ARMPCLabelIndex = AFI->createPICLabelUId();
3475 ARMConstantPoolValue *CPV =
3476 ARMConstantPoolConstant::Create(BA, ARMPCLabelIndex,
3477 ARMCP::CPBlockAddress, PCAdj);
3478 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, Align(4));
3479 }
3480 CPAddr = DAG.getNode(ARMISD::Wrapper, DL, PtrVT, CPAddr);
3481 SDValue Result = DAG.getLoad(
3482 PtrVT, DL, DAG.getEntryNode(), CPAddr,
3483 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
3484 if (!IsPositionIndependent)
3485 return Result;
3486 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, DL, MVT::i32);
3487 return DAG.getNode(ARMISD::PIC_ADD, DL, PtrVT, Result, PICLabel);
3488}
3489
3490/// Convert a TLS address reference into the correct sequence of loads
3491/// and calls to compute the variable's address for Darwin, and return an
3492/// SDValue containing the final node.
3493
3494/// Darwin only has one TLS scheme which must be capable of dealing with the
3495/// fully general situation, in the worst case. This means:
3496/// + "extern __thread" declaration.
3497/// + Defined in a possibly unknown dynamic library.
3498///
3499/// The general system is that each __thread variable has a [3 x i32] descriptor
3500/// which contains information used by the runtime to calculate the address. The
3501/// only part of this the compiler needs to know about is the first word, which
3502/// contains a function pointer that must be called with the address of the
3503/// entire descriptor in "r0".
3504///
3505/// Since this descriptor may be in a different unit, in general access must
3506/// proceed along the usual ARM rules. A common sequence to produce is:
3507///
3508/// movw rT1, :lower16:_var$non_lazy_ptr
3509/// movt rT1, :upper16:_var$non_lazy_ptr
3510/// ldr r0, [rT1]
3511/// ldr rT2, [r0]
3512/// blx rT2
3513/// [...address now in r0...]
3514SDValue
3515ARMTargetLowering::LowerGlobalTLSAddressDarwin(SDValue Op,
3516 SelectionDAG &DAG) const {
3517 assert(Subtarget->isTargetDarwin() &&(static_cast <bool> (Subtarget->isTargetDarwin() &&
"This function expects a Darwin target") ? void (0) : __assert_fail
("Subtarget->isTargetDarwin() && \"This function expects a Darwin target\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 3518, __extension__
__PRETTY_FUNCTION__))
3518 "This function expects a Darwin target")(static_cast <bool> (Subtarget->isTargetDarwin() &&
"This function expects a Darwin target") ? void (0) : __assert_fail
("Subtarget->isTargetDarwin() && \"This function expects a Darwin target\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 3518, __extension__
__PRETTY_FUNCTION__))
;
3519 SDLoc DL(Op);
3520
3521 // First step is to get the address of the actua global symbol. This is where
3522 // the TLS descriptor lives.
3523 SDValue DescAddr = LowerGlobalAddressDarwin(Op, DAG);
3524
3525 // The first entry in the descriptor is a function pointer that we must call
3526 // to obtain the address of the variable.
3527 SDValue Chain = DAG.getEntryNode();
3528 SDValue FuncTLVGet = DAG.getLoad(
3529 MVT::i32, DL, Chain, DescAddr,
3530 MachinePointerInfo::getGOT(DAG.getMachineFunction()), Align(4),
3531 MachineMemOperand::MONonTemporal | MachineMemOperand::MODereferenceable |
3532 MachineMemOperand::MOInvariant);
3533 Chain = FuncTLVGet.getValue(1);
3534
3535 MachineFunction &F = DAG.getMachineFunction();
3536 MachineFrameInfo &MFI = F.getFrameInfo();
3537 MFI.setAdjustsStack(true);
3538
3539 // TLS calls preserve all registers except those that absolutely must be
3540 // trashed: R0 (it takes an argument), LR (it's a call) and CPSR (let's not be
3541 // silly).
3542 auto TRI =
3543 getTargetMachine().getSubtargetImpl(F.getFunction())->getRegisterInfo();
3544 auto ARI = static_cast<const ARMRegisterInfo *>(TRI);
3545 const uint32_t *Mask = ARI->getTLSCallPreservedMask(DAG.getMachineFunction());
3546
3547 // Finally, we can make the call. This is just a degenerate version of a
3548 // normal AArch64 call node: r0 takes the address of the descriptor, and
3549 // returns the address of the variable in this thread.
3550 Chain = DAG.getCopyToReg(Chain, DL, ARM::R0, DescAddr, SDValue());
3551 Chain =
3552 DAG.getNode(ARMISD::CALL, DL, DAG.getVTList(MVT::Other, MVT::Glue),
3553 Chain, FuncTLVGet, DAG.getRegister(ARM::R0, MVT::i32),
3554 DAG.getRegisterMask(Mask), Chain.getValue(1));
3555 return DAG.getCopyFromReg(Chain, DL, ARM::R0, MVT::i32, Chain.getValue(1));
3556}
3557
3558SDValue
3559ARMTargetLowering::LowerGlobalTLSAddressWindows(SDValue Op,
3560 SelectionDAG &DAG) const {
3561 assert(Subtarget->isTargetWindows() && "Windows specific TLS lowering")(static_cast <bool> (Subtarget->isTargetWindows() &&
"Windows specific TLS lowering") ? void (0) : __assert_fail (
"Subtarget->isTargetWindows() && \"Windows specific TLS lowering\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 3561, __extension__
__PRETTY_FUNCTION__))
;
3562
3563 SDValue Chain = DAG.getEntryNode();
3564 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3565 SDLoc DL(Op);
3566
3567 // Load the current TEB (thread environment block)
3568 SDValue Ops[] = {Chain,
3569 DAG.getTargetConstant(Intrinsic::arm_mrc, DL, MVT::i32),
3570 DAG.getTargetConstant(15, DL, MVT::i32),
3571 DAG.getTargetConstant(0, DL, MVT::i32),
3572 DAG.getTargetConstant(13, DL, MVT::i32),
3573 DAG.getTargetConstant(0, DL, MVT::i32),
3574 DAG.getTargetConstant(2, DL, MVT::i32)};
3575 SDValue CurrentTEB = DAG.getNode(ISD::INTRINSIC_W_CHAIN, DL,
3576 DAG.getVTList(MVT::i32, MVT::Other), Ops);
3577
3578 SDValue TEB = CurrentTEB.getValue(0);
3579 Chain = CurrentTEB.getValue(1);
3580
3581 // Load the ThreadLocalStoragePointer from the TEB
3582 // A pointer to the TLS array is located at offset 0x2c from the TEB.
3583 SDValue TLSArray =
3584 DAG.getNode(ISD::ADD, DL, PtrVT, TEB, DAG.getIntPtrConstant(0x2c, DL));
3585 TLSArray = DAG.getLoad(PtrVT, DL, Chain, TLSArray, MachinePointerInfo());
3586
3587 // The pointer to the thread's TLS data area is at the TLS Index scaled by 4
3588 // offset into the TLSArray.
3589
3590 // Load the TLS index from the C runtime
3591 SDValue TLSIndex =
3592 DAG.getTargetExternalSymbol("_tls_index", PtrVT, ARMII::MO_NO_FLAG);
3593 TLSIndex = DAG.getNode(ARMISD::Wrapper, DL, PtrVT, TLSIndex);
3594 TLSIndex = DAG.getLoad(PtrVT, DL, Chain, TLSIndex, MachinePointerInfo());
3595
3596 SDValue Slot = DAG.getNode(ISD::SHL, DL, PtrVT, TLSIndex,
3597 DAG.getConstant(2, DL, MVT::i32));
3598 SDValue TLS = DAG.getLoad(PtrVT, DL, Chain,
3599 DAG.getNode(ISD::ADD, DL, PtrVT, TLSArray, Slot),
3600 MachinePointerInfo());
3601
3602 // Get the offset of the start of the .tls section (section base)
3603 const auto *GA = cast<GlobalAddressSDNode>(Op);
3604 auto *CPV = ARMConstantPoolConstant::Create(GA->getGlobal(), ARMCP::SECREL);
3605 SDValue Offset = DAG.getLoad(
3606 PtrVT, DL, Chain,
3607 DAG.getNode(ARMISD::Wrapper, DL, MVT::i32,
3608 DAG.getTargetConstantPool(CPV, PtrVT, Align(4))),
3609 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
3610
3611 return DAG.getNode(ISD::ADD, DL, PtrVT, TLS, Offset);
3612}
3613
3614// Lower ISD::GlobalTLSAddress using the "general dynamic" model
3615SDValue
3616ARMTargetLowering::LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
3617 SelectionDAG &DAG) const {
3618 SDLoc dl(GA);
3619 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3620 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
3621 MachineFunction &MF = DAG.getMachineFunction();
3622 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
3623 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
3624 ARMConstantPoolValue *CPV =
3625 ARMConstantPoolConstant::Create(GA->getGlobal(), ARMPCLabelIndex,
3626 ARMCP::CPValue, PCAdj, ARMCP::TLSGD, true);
3627 SDValue Argument = DAG.getTargetConstantPool(CPV, PtrVT, Align(4));
3628 Argument = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Argument);
3629 Argument = DAG.getLoad(
3630 PtrVT, dl, DAG.getEntryNode(), Argument,
3631 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
3632 SDValue Chain = Argument.getValue(1);
3633
3634 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, dl, MVT::i32);
3635 Argument = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Argument, PICLabel);
3636
3637 // call __tls_get_addr.
3638 ArgListTy Args;
3639 ArgListEntry Entry;
3640 Entry.Node = Argument;
3641 Entry.Ty = (Type *) Type::getInt32Ty(*DAG.getContext());
3642 Args.push_back(Entry);
3643
3644 // FIXME: is there useful debug info available here?
3645 TargetLowering::CallLoweringInfo CLI(DAG);
3646 CLI.setDebugLoc(dl).setChain(Chain).setLibCallee(
3647 CallingConv::C, Type::getInt32Ty(*DAG.getContext()),
3648 DAG.getExternalSymbol("__tls_get_addr", PtrVT), std::move(Args));
3649
3650 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
3651 return CallResult.first;
3652}
3653
3654// Lower ISD::GlobalTLSAddress using the "initial exec" or
3655// "local exec" model.
3656SDValue
3657ARMTargetLowering::LowerToTLSExecModels(GlobalAddressSDNode *GA,
3658 SelectionDAG &DAG,
3659 TLSModel::Model model) const {
3660 const GlobalValue *GV = GA->getGlobal();
3661 SDLoc dl(GA);
3662 SDValue Offset;
3663 SDValue Chain = DAG.getEntryNode();
3664 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3665 // Get the Thread Pointer
3666 SDValue ThreadPointer = DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
3667
3668 if (model == TLSModel::InitialExec) {
3669 MachineFunction &MF = DAG.getMachineFunction();
3670 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
3671 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
3672 // Initial exec model.
3673 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
3674 ARMConstantPoolValue *CPV =
3675 ARMConstantPoolConstant::Create(GA->getGlobal(), ARMPCLabelIndex,
3676 ARMCP::CPValue, PCAdj, ARMCP::GOTTPOFF,
3677 true);
3678 Offset = DAG.getTargetConstantPool(CPV, PtrVT, Align(4));
3679 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
3680 Offset = DAG.getLoad(
3681 PtrVT, dl, Chain, Offset,
3682 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
3683 Chain = Offset.getValue(1);
3684
3685 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, dl, MVT::i32);
3686 Offset = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Offset, PICLabel);
3687
3688 Offset = DAG.getLoad(
3689 PtrVT, dl, Chain, Offset,
3690 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
3691 } else {
3692 // local exec model
3693 assert(model == TLSModel::LocalExec)(static_cast <bool> (model == TLSModel::LocalExec) ? void
(0) : __assert_fail ("model == TLSModel::LocalExec", "llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3693, __extension__ __PRETTY_FUNCTION__))
;
3694 ARMConstantPoolValue *CPV =
3695 ARMConstantPoolConstant::Create(GV, ARMCP::TPOFF);
3696 Offset = DAG.getTargetConstantPool(CPV, PtrVT, Align(4));
3697 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
3698 Offset = DAG.getLoad(
3699 PtrVT, dl, Chain, Offset,
3700 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
3701 }
3702
3703 // The address of the thread local variable is the add of the thread
3704 // pointer with the offset of the variable.
3705 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
3706}
3707
3708SDValue
3709ARMTargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
3710 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
3711 if (DAG.getTarget().useEmulatedTLS())
3712 return LowerToTLSEmulatedModel(GA, DAG);
3713
3714 if (Subtarget->isTargetDarwin())
3715 return LowerGlobalTLSAddressDarwin(Op, DAG);
3716
3717 if (Subtarget->isTargetWindows())
3718 return LowerGlobalTLSAddressWindows(Op, DAG);
3719
3720 // TODO: implement the "local dynamic" model
3721 assert(Subtarget->isTargetELF() && "Only ELF implemented here")(static_cast <bool> (Subtarget->isTargetELF() &&
"Only ELF implemented here") ? void (0) : __assert_fail ("Subtarget->isTargetELF() && \"Only ELF implemented here\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 3721, __extension__
__PRETTY_FUNCTION__))
;
3722 TLSModel::Model model = getTargetMachine().getTLSModel(GA->getGlobal());
3723
3724 switch (model) {
3725 case TLSModel::GeneralDynamic:
3726 case TLSModel::LocalDynamic:
3727 return LowerToTLSGeneralDynamicModel(GA, DAG);
3728 case TLSModel::InitialExec:
3729 case TLSModel::LocalExec:
3730 return LowerToTLSExecModels(GA, DAG, model);
3731 }
3732 llvm_unreachable("bogus TLS model")::llvm::llvm_unreachable_internal("bogus TLS model", "llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3732)
;
3733}
3734
3735/// Return true if all users of V are within function F, looking through
3736/// ConstantExprs.
3737static bool allUsersAreInFunction(const Value *V, const Function *F) {
3738 SmallVector<const User*,4> Worklist(V->users());
3739 while (!Worklist.empty()) {
3740 auto *U = Worklist.pop_back_val();
3741 if (isa<ConstantExpr>(U)) {
3742 append_range(Worklist, U->users());
3743 continue;
3744 }
3745
3746 auto *I = dyn_cast<Instruction>(U);
3747 if (!I || I->getParent()->getParent() != F)
3748 return false;
3749 }
3750 return true;
3751}
3752
3753static SDValue promoteToConstantPool(const ARMTargetLowering *TLI,
3754 const GlobalValue *GV, SelectionDAG &DAG,
3755 EVT PtrVT, const SDLoc &dl) {
3756 // If we're creating a pool entry for a constant global with unnamed address,
3757 // and the global is small enough, we can emit it inline into the constant pool
3758 // to save ourselves an indirection.
3759 //
3760 // This is a win if the constant is only used in one function (so it doesn't
3761 // need to be duplicated) or duplicating the constant wouldn't increase code
3762 // size (implying the constant is no larger than 4 bytes).
3763 const Function &F = DAG.getMachineFunction().getFunction();
3764
3765 // We rely on this decision to inline being idemopotent and unrelated to the
3766 // use-site. We know that if we inline a variable at one use site, we'll
3767 // inline it elsewhere too (and reuse the constant pool entry). Fast-isel
3768 // doesn't know about this optimization, so bail out if it's enabled else
3769 // we could decide to inline here (and thus never emit the GV) but require
3770 // the GV from fast-isel generated code.
3771 if (!EnableConstpoolPromotion ||
3772 DAG.getMachineFunction().getTarget().Options.EnableFastISel)
3773 return SDValue();
3774
3775 auto *GVar = dyn_cast<GlobalVariable>(GV);
3776 if (!GVar || !GVar->hasInitializer() ||
3777 !GVar->isConstant() || !GVar->hasGlobalUnnamedAddr() ||
3778 !GVar->hasLocalLinkage())
3779 return SDValue();
3780
3781 // If we inline a value that contains relocations, we move the relocations
3782 // from .data to .text. This is not allowed in position-independent code.
3783 auto *Init = GVar->getInitializer();
3784 if ((TLI->isPositionIndependent() || TLI->getSubtarget()->isROPI()) &&
3785 Init->needsDynamicRelocation())
3786 return SDValue();
3787
3788 // The constant islands pass can only really deal with alignment requests
3789 // <= 4 bytes and cannot pad constants itself. Therefore we cannot promote
3790 // any type wanting greater alignment requirements than 4 bytes. We also
3791 // can only promote constants that are multiples of 4 bytes in size or
3792 // are paddable to a multiple of 4. Currently we only try and pad constants
3793 // that are strings for simplicity.
3794 auto *CDAInit = dyn_cast<ConstantDataArray>(Init);
3795 unsigned Size = DAG.getDataLayout().getTypeAllocSize(Init->getType());
3796 Align PrefAlign = DAG.getDataLayout().getPreferredAlign(GVar);
3797 unsigned RequiredPadding = 4 - (Size % 4);
3798 bool PaddingPossible =
3799 RequiredPadding == 4 || (CDAInit && CDAInit->isString());
3800 if (!PaddingPossible || PrefAlign > 4 || Size > ConstpoolPromotionMaxSize ||
3801 Size == 0)
3802 return SDValue();
3803
3804 unsigned PaddedSize = Size + ((RequiredPadding == 4) ? 0 : RequiredPadding);
3805 MachineFunction &MF = DAG.getMachineFunction();
3806 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
3807
3808 // We can't bloat the constant pool too much, else the ConstantIslands pass
3809 // may fail to converge. If we haven't promoted this global yet (it may have
3810 // multiple uses), and promoting it would increase the constant pool size (Sz
3811 // > 4), ensure we have space to do so up to MaxTotal.
3812 if (!AFI->getGlobalsPromotedToConstantPool().count(GVar) && Size > 4)
3813 if (AFI->getPromotedConstpoolIncrease() + PaddedSize - 4 >=
3814 ConstpoolPromotionMaxTotal)
3815 return SDValue();
3816
3817 // This is only valid if all users are in a single function; we can't clone
3818 // the constant in general. The LLVM IR unnamed_addr allows merging
3819 // constants, but not cloning them.
3820 //
3821 // We could potentially allow cloning if we could prove all uses of the
3822 // constant in the current function don't care about the address, like
3823 // printf format strings. But that isn't implemented for now.
3824 if (!allUsersAreInFunction(GVar, &F))
3825 return SDValue();
3826
3827 // We're going to inline this global. Pad it out if needed.
3828 if (RequiredPadding != 4) {
3829 StringRef S = CDAInit->getAsString();
3830
3831 SmallVector<uint8_t,16> V(S.size());
3832 std::copy(S.bytes_begin(), S.bytes_end(), V.begin());
3833 while (RequiredPadding--)
3834 V.push_back(0);
3835 Init = ConstantDataArray::get(*DAG.getContext(), V);
3836 }
3837
3838 auto CPVal = ARMConstantPoolConstant::Create(GVar, Init);
3839 SDValue CPAddr = DAG.getTargetConstantPool(CPVal, PtrVT, Align(4));
3840 if (!AFI->getGlobalsPromotedToConstantPool().count(GVar)) {
3841 AFI->markGlobalAsPromotedToConstantPool(GVar);
3842 AFI->setPromotedConstpoolIncrease(AFI->getPromotedConstpoolIncrease() +
3843 PaddedSize - 4);
3844 }
3845 ++NumConstpoolPromoted;
3846 return DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
3847}
3848
3849bool ARMTargetLowering::isReadOnly(const GlobalValue *GV) const {
3850 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
3851 if (!(GV = GA->getAliaseeObject()))
3852 return false;
3853 if (const auto *V = dyn_cast<GlobalVariable>(GV))
3854 return V->isConstant();
3855 return isa<Function>(GV);
3856}
3857
3858SDValue ARMTargetLowering::LowerGlobalAddress(SDValue Op,
3859 SelectionDAG &DAG) const {
3860 switch (Subtarget->getTargetTriple().getObjectFormat()) {
3861 default: llvm_unreachable("unknown object format")::llvm::llvm_unreachable_internal("unknown object format", "llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3861)
;
3862 case Triple::COFF:
3863 return LowerGlobalAddressWindows(Op, DAG);
3864 case Triple::ELF:
3865 return LowerGlobalAddressELF(Op, DAG);
3866 case Triple::MachO:
3867 return LowerGlobalAddressDarwin(Op, DAG);
3868 }
3869}
3870
3871SDValue ARMTargetLowering::LowerGlobalAddressELF(SDValue Op,
3872 SelectionDAG &DAG) const {
3873 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3874 SDLoc dl(Op);
3875 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
3876 const TargetMachine &TM = getTargetMachine();
3877 bool IsRO = isReadOnly(GV);
3878
3879 // promoteToConstantPool only if not generating XO text section
3880 if (TM.shouldAssumeDSOLocal(*GV->getParent(), GV) && !Subtarget->genExecuteOnly())
3881 if (SDValue V = promoteToConstantPool(this, GV, DAG, PtrVT, dl))
3882 return V;
3883
3884 if (isPositionIndependent()) {
3885 bool UseGOT_PREL = !TM.shouldAssumeDSOLocal(*GV->getParent(), GV);
3886 SDValue G = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
3887 UseGOT_PREL ? ARMII::MO_GOT : 0);
3888 SDValue Result = DAG.getNode(ARMISD::WrapperPIC, dl, PtrVT, G);
3889 if (UseGOT_PREL)
3890 Result =
3891 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Result,
3892 MachinePointerInfo::getGOT(DAG.getMachineFunction()));
3893 return Result;
3894 } else if (Subtarget->isROPI() && IsRO) {
3895 // PC-relative.
3896 SDValue G = DAG.getTargetGlobalAddress(GV, dl, PtrVT);
3897 SDValue Result = DAG.getNode(ARMISD::WrapperPIC, dl, PtrVT, G);
3898 return Result;
3899 } else if (Subtarget->isRWPI() && !IsRO) {
3900 // SB-relative.
3901 SDValue RelAddr;
3902 if (Subtarget->useMovt()) {
3903 ++NumMovwMovt;
3904 SDValue G = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, ARMII::MO_SBREL);
3905 RelAddr = DAG.getNode(ARMISD::Wrapper, dl, PtrVT, G);
3906 } else { // use literal pool for address constant
3907 ARMConstantPoolValue *CPV =
3908 ARMConstantPoolConstant::Create(GV, ARMCP::SBREL);
3909 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, Align(4));
3910 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
3911 RelAddr = DAG.getLoad(
3912 PtrVT, dl, DAG.getEntryNode(), CPAddr,
3913 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
3914 }
3915 SDValue SB = DAG.getCopyFromReg(DAG.getEntryNode(), dl, ARM::R9, PtrVT);
3916 SDValue Result = DAG.getNode(ISD::ADD, dl, PtrVT, SB, RelAddr);
3917 return Result;
3918 }
3919
3920 // If we have T2 ops, we can materialize the address directly via movt/movw
3921 // pair. This is always cheaper.
3922 if (Subtarget->useMovt()) {
3923 ++NumMovwMovt;
3924 // FIXME: Once remat is capable of dealing with instructions with register
3925 // operands, expand this into two nodes.
3926 return DAG.getNode(ARMISD::Wrapper, dl, PtrVT,
3927 DAG.getTargetGlobalAddress(GV, dl, PtrVT));
3928 } else {
3929 SDValue CPAddr = DAG.getTargetConstantPool(GV, PtrVT, Align(4));
3930 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
3931 return DAG.getLoad(
3932 PtrVT, dl, DAG.getEntryNode(), CPAddr,
3933 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
3934 }
3935}
3936
3937SDValue ARMTargetLowering::LowerGlobalAddressDarwin(SDValue Op,
3938 SelectionDAG &DAG) const {
3939 assert(!Subtarget->isROPI() && !Subtarget->isRWPI() &&(static_cast <bool> (!Subtarget->isROPI() &&
!Subtarget->isRWPI() && "ROPI/RWPI not currently supported for Darwin"
) ? void (0) : __assert_fail ("!Subtarget->isROPI() && !Subtarget->isRWPI() && \"ROPI/RWPI not currently supported for Darwin\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 3940, __extension__
__PRETTY_FUNCTION__))
3940 "ROPI/RWPI not currently supported for Darwin")(static_cast <bool> (!Subtarget->isROPI() &&
!Subtarget->isRWPI() && "ROPI/RWPI not currently supported for Darwin"
) ? void (0) : __assert_fail ("!Subtarget->isROPI() && !Subtarget->isRWPI() && \"ROPI/RWPI not currently supported for Darwin\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 3940, __extension__
__PRETTY_FUNCTION__))
;
3941 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3942 SDLoc dl(Op);
3943 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
3944
3945 if (Subtarget->useMovt())
3946 ++NumMovwMovt;
3947
3948 // FIXME: Once remat is capable of dealing with instructions with register
3949 // operands, expand this into multiple nodes
3950 unsigned Wrapper =
3951 isPositionIndependent() ? ARMISD::WrapperPIC : ARMISD::Wrapper;
3952
3953 SDValue G = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, ARMII::MO_NONLAZY);
3954 SDValue Result = DAG.getNode(Wrapper, dl, PtrVT, G);
3955
3956 if (Subtarget->isGVIndirectSymbol(GV))
3957 Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Result,
3958 MachinePointerInfo::getGOT(DAG.getMachineFunction()));
3959 return Result;
3960}
3961
3962SDValue ARMTargetLowering::LowerGlobalAddressWindows(SDValue Op,
3963 SelectionDAG &DAG) const {
3964 assert(Subtarget->isTargetWindows() && "non-Windows COFF is not supported")(static_cast <bool> (Subtarget->isTargetWindows() &&
"non-Windows COFF is not supported") ? void (0) : __assert_fail
("Subtarget->isTargetWindows() && \"non-Windows COFF is not supported\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 3964, __extension__
__PRETTY_FUNCTION__))
;
3965 assert(Subtarget->useMovt() &&(static_cast <bool> (Subtarget->useMovt() &&
"Windows on ARM expects to use movw/movt") ? void (0) : __assert_fail
("Subtarget->useMovt() && \"Windows on ARM expects to use movw/movt\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 3966, __extension__
__PRETTY_FUNCTION__))
3966 "Windows on ARM expects to use movw/movt")(static_cast <bool> (Subtarget->useMovt() &&
"Windows on ARM expects to use movw/movt") ? void (0) : __assert_fail
("Subtarget->useMovt() && \"Windows on ARM expects to use movw/movt\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 3966, __extension__
__PRETTY_FUNCTION__))
;
3967 assert(!Subtarget->isROPI() && !Subtarget->isRWPI() &&(static_cast <bool> (!Subtarget->isROPI() &&
!Subtarget->isRWPI() && "ROPI/RWPI not currently supported for Windows"
) ? void (0) : __assert_fail ("!Subtarget->isROPI() && !Subtarget->isRWPI() && \"ROPI/RWPI not currently supported for Windows\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 3968, __extension__
__PRETTY_FUNCTION__))
3968 "ROPI/RWPI not currently supported for Windows")(static_cast <bool> (!Subtarget->isROPI() &&
!Subtarget->isRWPI() && "ROPI/RWPI not currently supported for Windows"
) ? void (0) : __assert_fail ("!Subtarget->isROPI() && !Subtarget->isRWPI() && \"ROPI/RWPI not currently supported for Windows\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 3968, __extension__
__PRETTY_FUNCTION__))
;
3969
3970 const TargetMachine &TM = getTargetMachine();
3971 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
3972 ARMII::TOF TargetFlags = ARMII::MO_NO_FLAG;
3973 if (GV->hasDLLImportStorageClass())
3974 TargetFlags = ARMII::MO_DLLIMPORT;
3975 else if (!TM.shouldAssumeDSOLocal(*GV->getParent(), GV))
3976 TargetFlags = ARMII::MO_COFFSTUB;
3977 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3978 SDValue Result;
3979 SDLoc DL(Op);
3980
3981 ++NumMovwMovt;
3982
3983 // FIXME: Once remat is capable of dealing with instructions with register
3984 // operands, expand this into two nodes.
3985 Result = DAG.getNode(ARMISD::Wrapper, DL, PtrVT,
3986 DAG.getTargetGlobalAddress(GV, DL, PtrVT, /*offset=*/0,
3987 TargetFlags));
3988 if (TargetFlags & (ARMII::MO_DLLIMPORT | ARMII::MO_COFFSTUB))
3989 Result = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Result,
3990 MachinePointerInfo::getGOT(DAG.getMachineFunction()));
3991 return Result;
3992}
3993
3994SDValue
3995ARMTargetLowering::LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const {
3996 SDLoc dl(Op);
3997 SDValue Val = DAG.getConstant(0, dl, MVT::i32);
3998 return DAG.getNode(ARMISD::EH_SJLJ_SETJMP, dl,
3999 DAG.getVTList(MVT::i32, MVT::Other), Op.getOperand(0),
4000 Op.getOperand(1), Val);
4001}
4002
4003SDValue
4004ARMTargetLowering::LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const {
4005 SDLoc dl(Op);
4006 return DAG.getNode(ARMISD::EH_SJLJ_LONGJMP, dl, MVT::Other, Op.getOperand(0),
4007 Op.getOperand(1), DAG.getConstant(0, dl, MVT::i32));
4008}
4009
4010SDValue ARMTargetLowering::LowerEH_SJLJ_SETUP_DISPATCH(SDValue Op,
4011 SelectionDAG &DAG) const {
4012 SDLoc dl(Op);
4013 return DAG.getNode(ARMISD::EH_SJLJ_SETUP_DISPATCH, dl, MVT::Other,
4014 Op.getOperand(0));
4015}
4016
4017SDValue ARMTargetLowering::LowerINTRINSIC_VOID(
4018 SDValue Op, SelectionDAG &DAG, const ARMSubtarget *Subtarget) const {
4019 unsigned IntNo =
4020 cast<ConstantSDNode>(
4021 Op.getOperand(Op.getOperand(0).getValueType() == MVT::Other))
4022 ->getZExtValue();
4023 switch (IntNo) {
4024 default:
4025 return SDValue(); // Don't custom lower most intrinsics.
4026 case Intrinsic::arm_gnu_eabi_mcount: {
4027 MachineFunction &MF = DAG.getMachineFunction();
4028 EVT PtrVT = getPointerTy(DAG.getDataLayout());
4029 SDLoc dl(Op);
4030 SDValue Chain = Op.getOperand(0);
4031 // call "\01__gnu_mcount_nc"
4032 const ARMBaseRegisterInfo *ARI = Subtarget->getRegisterInfo();
4033 const uint32_t *Mask =
4034 ARI->getCallPreservedMask(DAG.getMachineFunction(), CallingConv::C);
4035 assert(Mask && "Missing call preserved mask for calling convention")(static_cast <bool> (Mask && "Missing call preserved mask for calling convention"
) ? void (0) : __assert_fail ("Mask && \"Missing call preserved mask for calling convention\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 4035, __extension__
__PRETTY_FUNCTION__))
;
4036 // Mark LR an implicit live-in.
4037 Register Reg = MF.addLiveIn(ARM::LR, getRegClassFor(MVT::i32));
4038 SDValue ReturnAddress =
4039 DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg, PtrVT);
4040 constexpr EVT ResultTys[] = {MVT::Other, MVT::Glue};
4041 SDValue Callee =
4042 DAG.getTargetExternalSymbol("\01__gnu_mcount_nc", PtrVT, 0);
4043 SDValue RegisterMask = DAG.getRegisterMask(Mask);
4044 if (Subtarget->isThumb())
4045 return SDValue(
4046 DAG.getMachineNode(
4047 ARM::tBL_PUSHLR, dl, ResultTys,
4048 {ReturnAddress, DAG.getTargetConstant(ARMCC::AL, dl, PtrVT),
4049 DAG.getRegister(0, PtrVT), Callee, RegisterMask, Chain}),
4050 0);
4051 return SDValue(
4052 DAG.getMachineNode(ARM::BL_PUSHLR, dl, ResultTys,
4053 {ReturnAddress, Callee, RegisterMask, Chain}),
4054 0);
4055 }
4056 }
4057}
4058
4059SDValue
4060ARMTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG,
4061 const ARMSubtarget *Subtarget) const {
4062 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
4063 SDLoc dl(Op);
4064 switch (IntNo) {
4065 default: return SDValue(); // Don't custom lower most intrinsics.
4066 case Intrinsic::thread_pointer: {
4067 EVT PtrVT = getPointerTy(DAG.getDataLayout());
4068 return DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
4069 }
4070 case Intrinsic::arm_cls: {
4071 const SDValue &Operand = Op.getOperand(1);
4072 const EVT VTy = Op.getValueType();
4073 SDValue SRA =
4074 DAG.getNode(ISD::SRA, dl, VTy, Operand, DAG.getConstant(31, dl, VTy));
4075 SDValue XOR = DAG.getNode(ISD::XOR, dl, VTy, SRA, Operand);
4076 SDValue SHL =
4077 DAG.getNode(ISD::SHL, dl, VTy, XOR, DAG.getConstant(1, dl, VTy));
4078 SDValue OR =
4079 DAG.getNode(ISD::OR, dl, VTy, SHL, DAG.getConstant(1, dl, VTy));
4080 SDValue Result = DAG.getNode(ISD::CTLZ, dl, VTy, OR);
4081 return Result;
4082 }
4083 case Intrinsic::arm_cls64: {
4084 // cls(x) = if cls(hi(x)) != 31 then cls(hi(x))
4085 // else 31 + clz(if hi(x) == 0 then lo(x) else not(lo(x)))
4086 const SDValue &Operand = Op.getOperand(1);
4087 const EVT VTy = Op.getValueType();
4088
4089 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VTy, Operand,
4090 DAG.getConstant(1, dl, VTy));
4091 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VTy, Operand,
4092 DAG.getConstant(0, dl, VTy));
4093 SDValue Constant0 = DAG.getConstant(0, dl, VTy);
4094 SDValue Constant1 = DAG.getConstant(1, dl, VTy);
4095 SDValue Constant31 = DAG.getConstant(31, dl, VTy);
4096 SDValue SRAHi = DAG.getNode(ISD::SRA, dl, VTy, Hi, Constant31);
4097 SDValue XORHi = DAG.getNode(ISD::XOR, dl, VTy, SRAHi, Hi);
4098 SDValue SHLHi = DAG.getNode(ISD::SHL, dl, VTy, XORHi, Constant1);
4099 SDValue ORHi = DAG.getNode(ISD::OR, dl, VTy, SHLHi, Constant1);
4100 SDValue CLSHi = DAG.getNode(ISD::CTLZ, dl, VTy, ORHi);
4101 SDValue CheckLo =
4102 DAG.getSetCC(dl, MVT::i1, CLSHi, Constant31, ISD::CondCode::SETEQ);
4103 SDValue HiIsZero =
4104 DAG.getSetCC(dl, MVT::i1, Hi, Constant0, ISD::CondCode::SETEQ);
4105 SDValue AdjustedLo =
4106 DAG.getSelect(dl, VTy, HiIsZero, Lo, DAG.getNOT(dl, Lo, VTy));
4107 SDValue CLZAdjustedLo = DAG.getNode(ISD::CTLZ, dl, VTy, AdjustedLo);
4108 SDValue Result =
4109 DAG.getSelect(dl, VTy, CheckLo,
4110 DAG.getNode(ISD::ADD, dl, VTy, CLZAdjustedLo, Constant31), CLSHi);
4111 return Result;
4112 }
4113 case Intrinsic::eh_sjlj_lsda: {
4114 MachineFunction &MF = DAG.getMachineFunction();
4115 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
4116 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
4117 EVT PtrVT = getPointerTy(DAG.getDataLayout());
4118 SDValue CPAddr;
4119 bool IsPositionIndependent = isPositionIndependent();
4120 unsigned PCAdj = IsPositionIndependent ? (Subtarget->isThumb() ? 4 : 8) : 0;
4121 ARMConstantPoolValue *CPV =
4122 ARMConstantPoolConstant::Create(&MF.getFunction(), ARMPCLabelIndex,
4123 ARMCP::CPLSDA, PCAdj);
4124 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, Align(4));
4125 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
4126 SDValue Result = DAG.getLoad(
4127 PtrVT, dl, DAG.getEntryNode(), CPAddr,
4128 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
4129
4130 if (IsPositionIndependent) {
4131 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, dl, MVT::i32);
4132 Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
4133 }
4134 return Result;
4135 }
4136 case Intrinsic::arm_neon_vabs:
4137 return DAG.getNode(ISD::ABS, SDLoc(Op), Op.getValueType(),
4138 Op.getOperand(1));
4139 case Intrinsic::arm_neon_vmulls:
4140 case Intrinsic::arm_neon_vmullu: {
4141 unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vmulls)
4142 ? ARMISD::VMULLs : ARMISD::VMULLu;
4143 return DAG.getNode(NewOpc, SDLoc(Op), Op.getValueType(),
4144 Op.getOperand(1), Op.getOperand(2));
4145 }
4146 case Intrinsic::arm_neon_vminnm:
4147 case Intrinsic::arm_neon_vmaxnm: {
4148 unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vminnm)
4149 ? ISD::FMINNUM : ISD::FMAXNUM;
4150 return DAG.getNode(NewOpc, SDLoc(Op), Op.getValueType(),
4151 Op.getOperand(1), Op.getOperand(2));
4152 }
4153 case Intrinsic::arm_neon_vminu:
4154 case Intrinsic::arm_neon_vmaxu: {
4155 if (Op.getValueType().isFloatingPoint())
4156 return SDValue();
4157 unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vminu)
4158 ? ISD::UMIN : ISD::UMAX;
4159 return DAG.getNode(NewOpc, SDLoc(Op), Op.getValueType(),
4160 Op.getOperand(1), Op.getOperand(2));
4161 }
4162 case Intrinsic::arm_neon_vmins:
4163 case Intrinsic::arm_neon_vmaxs: {
4164 // v{min,max}s is overloaded between signed integers and floats.
4165 if (!Op.getValueType().isFloatingPoint()) {
4166 unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vmins)
4167 ? ISD::SMIN : ISD::SMAX;
4168 return DAG.getNode(NewOpc, SDLoc(Op), Op.getValueType(),
4169 Op.getOperand(1), Op.getOperand(2));
4170 }
4171 unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vmins)
4172 ? ISD::FMINIMUM : ISD::FMAXIMUM;
4173 return DAG.getNode(NewOpc, SDLoc(Op), Op.getValueType(),
4174 Op.getOperand(1), Op.getOperand(2));
4175 }
4176 case Intrinsic::arm_neon_vtbl1:
4177 return DAG.getNode(ARMISD::VTBL1, SDLoc(Op), Op.getValueType(),
4178 Op.getOperand(1), Op.getOperand(2));
4179 case Intrinsic::arm_neon_vtbl2:
4180 return DAG.getNode(ARMISD::VTBL2, SDLoc(Op), Op.getValueType(),
4181 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
4182 case Intrinsic::arm_mve_pred_i2v:
4183 case Intrinsic::arm_mve_pred_v2i:
4184 return DAG.getNode(ARMISD::PREDICATE_CAST, SDLoc(Op), Op.getValueType(),
4185 Op.getOperand(1));
4186 case Intrinsic::arm_mve_vreinterpretq:
4187 return DAG.getNode(ARMISD::VECTOR_REG_CAST, SDLoc(Op), Op.getValueType(),
4188 Op.getOperand(1));
4189 case Intrinsic::arm_mve_lsll:
4190 return DAG.getNode(ARMISD::LSLL, SDLoc(Op), Op->getVTList(),
4191 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
4192 case Intrinsic::arm_mve_asrl:
4193 return DAG.getNode(ARMISD::ASRL, SDLoc(Op), Op->getVTList(),
4194 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
4195 }
4196}
4197
4198static SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG,
4199 const ARMSubtarget *Subtarget) {
4200 SDLoc dl(Op);
4201 ConstantSDNode *SSIDNode = cast<ConstantSDNode>(Op.getOperand(2));
4202 auto SSID = static_cast<SyncScope::ID>(SSIDNode->getZExtValue());
4203 if (SSID == SyncScope::SingleThread)
4204 return Op;
4205
4206 if (!Subtarget->hasDataBarrier()) {
4207 // Some ARMv6 cpus can support data barriers with an mcr instruction.
4208 // Thumb1 and pre-v6 ARM mode use a libcall instead and should never get
4209 // here.
4210 assert(Subtarget->hasV6Ops() && !Subtarget->isThumb() &&(static_cast <bool> (Subtarget->hasV6Ops() &&
!Subtarget->isThumb() && "Unexpected ISD::ATOMIC_FENCE encountered. Should be libcall!"
) ? void (0) : __assert_fail ("Subtarget->hasV6Ops() && !Subtarget->isThumb() && \"Unexpected ISD::ATOMIC_FENCE encountered. Should be libcall!\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 4211, __extension__
__PRETTY_FUNCTION__))
4211 "Unexpected ISD::ATOMIC_FENCE encountered. Should be libcall!")(static_cast <bool> (Subtarget->hasV6Ops() &&
!Subtarget->isThumb() && "Unexpected ISD::ATOMIC_FENCE encountered. Should be libcall!"
) ? void (0) : __assert_fail ("Subtarget->hasV6Ops() && !Subtarget->isThumb() && \"Unexpected ISD::ATOMIC_FENCE encountered. Should be libcall!\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 4211, __extension__
__PRETTY_FUNCTION__))
;
4212 return DAG.getNode(ARMISD::MEMBARRIER_MCR, dl, MVT::Other, Op.getOperand(0),
4213 DAG.getConstant(0, dl, MVT::i32));
4214 }
4215
4216 ConstantSDNode *OrdN = cast<ConstantSDNode>(Op.getOperand(1));
4217 AtomicOrdering Ord = static_cast<AtomicOrdering>(OrdN->getZExtValue());
4218 ARM_MB::MemBOpt Domain = ARM_MB::ISH;
4219 if (Subtarget->isMClass()) {
4220 // Only a full system barrier exists in the M-class architectures.
4221 Domain = ARM_MB::SY;
4222 } else if (Subtarget->preferISHSTBarriers() &&
4223 Ord == AtomicOrdering::Release) {
4224 // Swift happens to implement ISHST barriers in a way that's compatible with
4225 // Release semantics but weaker than ISH so we'd be fools not to use
4226 // it. Beware: other processors probably don't!
4227 Domain = ARM_MB::ISHST;
4228 }
4229
4230 return DAG.getNode(ISD::INTRINSIC_VOID, dl, MVT::Other, Op.getOperand(0),
4231 DAG.getConstant(Intrinsic::arm_dmb, dl, MVT::i32),
4232 DAG.getConstant(Domain, dl, MVT::i32));
4233}
4234
4235static SDValue LowerPREFETCH(SDValue Op, SelectionDAG &DAG,
4236 const ARMSubtarget *Subtarget) {
4237 // ARM pre v5TE and Thumb1 does not have preload instructions.
4238 if (!(Subtarget->isThumb2() ||
4239 (!Subtarget->isThumb1Only() && Subtarget->hasV5TEOps())))
4240 // Just preserve the chain.
4241 return Op.getOperand(0);
4242
4243 SDLoc dl(Op);
4244 unsigned isRead = ~cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue() & 1;
4245 if (!isRead &&
4246 (!Subtarget->hasV7Ops() || !Subtarget->hasMPExtension()))
4247 // ARMv7 with MP extension has PLDW.
4248 return Op.getOperand(0);
4249
4250 unsigned isData = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue();
4251 if (Subtarget->isThumb()) {
4252 // Invert the bits.
4253 isRead = ~isRead & 1;
4254 isData = ~isData & 1;
4255 }
4256
4257 return DAG.getNode(ARMISD::PRELOAD, dl, MVT::Other, Op.getOperand(0),
4258 Op.getOperand(1), DAG.getConstant(isRead, dl, MVT::i32),
4259 DAG.getConstant(isData, dl, MVT::i32));
4260}
4261
4262static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) {
4263 MachineFunction &MF = DAG.getMachineFunction();
4264 ARMFunctionInfo *FuncInfo = MF.getInfo<ARMFunctionInfo>();
4265
4266 // vastart just stores the address of the VarArgsFrameIndex slot into the
4267 // memory location argument.
4268 SDLoc dl(Op);
4269 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
4270 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
4271 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
4272 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1),
4273 MachinePointerInfo(SV));
4274}
4275
4276SDValue ARMTargetLowering::GetF64FormalArgument(CCValAssign &VA,
4277 CCValAssign &NextVA,
4278 SDValue &Root,
4279 SelectionDAG &DAG,
4280 const SDLoc &dl) const {
4281 MachineFunction &MF = DAG.getMachineFunction();
4282 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
4283
4284 const TargetRegisterClass *RC;
4285 if (AFI->isThumb1OnlyFunction())
4286 RC = &ARM::tGPRRegClass;
4287 else
4288 RC = &ARM::GPRRegClass;
4289
4290 // Transform the arguments stored in physical registers into virtual ones.
4291 Register Reg = MF.addLiveIn(VA.getLocReg(), RC);
4292 SDValue ArgValue = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
4293
4294 SDValue ArgValue2;
4295 if (NextVA.isMemLoc()) {
4296 MachineFrameInfo &MFI = MF.getFrameInfo();
4297 int FI = MFI.CreateFixedObject(4, NextVA.getLocMemOffset(), true);
4298
4299 // Create load node to retrieve arguments from the stack.
4300 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
4301 ArgValue2 = DAG.getLoad(
4302 MVT::i32, dl, Root, FIN,
4303 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI));
4304 } else {
4305 Reg = MF.addLiveIn(NextVA.getLocReg(), RC);
4306 ArgValue2 = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
4307 }
4308 if (!Subtarget->isLittle())
4309 std::swap (ArgValue, ArgValue2);
4310 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, ArgValue, ArgValue2);
4311}
4312
4313// The remaining GPRs hold either the beginning of variable-argument
4314// data, or the beginning of an aggregate passed by value (usually
4315// byval). Either way, we allocate stack slots adjacent to the data
4316// provided by our caller, and store the unallocated registers there.
4317// If this is a variadic function, the va_list pointer will begin with
4318// these values; otherwise, this reassembles a (byval) structure that
4319// was split between registers and memory.
4320// Return: The frame index registers were stored into.
4321int ARMTargetLowering::StoreByValRegs(CCState &CCInfo, SelectionDAG &DAG,
4322 const SDLoc &dl, SDValue &Chain,
4323 const Value *OrigArg,
4324 unsigned InRegsParamRecordIdx,
4325 int ArgOffset, unsigned ArgSize) const {
4326 // Currently, two use-cases possible:
4327 // Case #1. Non-var-args function, and we meet first byval parameter.
4328 // Setup first unallocated register as first byval register;
4329 // eat all remained registers
4330 // (these two actions are performed by HandleByVal method).
4331 // Then, here, we initialize stack frame with
4332 // "store-reg" instructions.
4333 // Case #2. Var-args function, that doesn't contain byval parameters.
4334 // The same: eat all remained unallocated registers,
4335 // initialize stack frame.
4336
4337 MachineFunction &MF = DAG.getMachineFunction();
4338 MachineFrameInfo &MFI = MF.getFrameInfo();
4339 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
4340 unsigned RBegin, REnd;
4341 if (InRegsParamRecordIdx < CCInfo.getInRegsParamsCount()) {
4342 CCInfo.getInRegsParamInfo(InRegsParamRecordIdx, RBegin, REnd);
4343 } else {
4344 unsigned RBeginIdx = CCInfo.getFirstUnallocated(GPRArgRegs);
4345 RBegin = RBeginIdx == 4 ? (unsigned)ARM::R4 : GPRArgRegs[RBeginIdx];
4346 REnd = ARM::R4;
4347 }
4348
4349 if (REnd != RBegin)
4350 ArgOffset = -4 * (ARM::R4 - RBegin);
4351
4352 auto PtrVT = getPointerTy(DAG.getDataLayout());
4353 int FrameIndex = MFI.CreateFixedObject(ArgSize, ArgOffset, false);
4354 SDValue FIN = DAG.getFrameIndex(FrameIndex, PtrVT);
4355
4356 SmallVector<SDValue, 4> MemOps;
4357 const TargetRegisterClass *RC =
4358 AFI->isThumb1OnlyFunction() ? &ARM::tGPRRegClass : &ARM::GPRRegClass;
4359
4360 for (unsigned Reg = RBegin, i = 0; Reg < REnd; ++Reg, ++i) {
4361 Register VReg = MF.addLiveIn(Reg, RC);
4362 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
4363 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
4364 MachinePointerInfo(OrigArg, 4 * i));
4365 MemOps.push_back(Store);
4366 FIN = DAG.getNode(ISD::ADD, dl, PtrVT, FIN, DAG.getConstant(4, dl, PtrVT));
4367 }
4368
4369 if (!MemOps.empty())
4370 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
4371 return FrameIndex;
4372}
4373
4374// Setup stack frame, the va_list pointer will start from.
4375void ARMTargetLowering::VarArgStyleRegisters(CCState &CCInfo, SelectionDAG &DAG,
4376 const SDLoc &dl, SDValue &Chain,
4377 unsigned ArgOffset,
4378 unsigned TotalArgRegsSaveSize,
4379 bool ForceMutable) const {
4380 MachineFunction &MF = DAG.getMachineFunction();
4381 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
4382
4383 // Try to store any remaining integer argument regs
4384 // to their spots on the stack so that they may be loaded by dereferencing
4385 // the result of va_next.
4386 // If there is no regs to be stored, just point address after last
4387 // argument passed via stack.
4388 int FrameIndex = StoreByValRegs(CCInfo, DAG, dl, Chain, nullptr,
4389 CCInfo.getInRegsParamsCount(),
4390 CCInfo.getNextStackOffset(),
4391 std::max(4U, TotalArgRegsSaveSize));
4392 AFI->setVarArgsFrameIndex(FrameIndex);
4393}
4394
4395bool ARMTargetLowering::splitValueIntoRegisterParts(
4396 SelectionDAG &DAG, const SDLoc &DL, SDValue Val, SDValue *Parts,
4397 unsigned NumParts, MVT PartVT, Optional<CallingConv::ID> CC) const {
4398 bool IsABIRegCopy = CC.has_value();
4399 EVT ValueVT = Val.getValueType();
4400 if (IsABIRegCopy && (ValueVT == MVT::f16 || ValueVT == MVT::bf16) &&
4401 PartVT == MVT::f32) {
4402 unsigned ValueBits = ValueVT.getSizeInBits();
4403 unsigned PartBits = PartVT.getSizeInBits();
4404 Val = DAG.getNode(ISD::BITCAST, DL, MVT::getIntegerVT(ValueBits), Val);
4405 Val = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::getIntegerVT(PartBits), Val);
4406 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
4407 Parts[0] = Val;
4408 return true;
4409 }
4410 return false;
4411}
4412
4413SDValue ARMTargetLowering::joinRegisterPartsIntoValue(
4414 SelectionDAG &DAG, const SDLoc &DL, const SDValue *Parts, unsigned NumParts,
4415 MVT PartVT, EVT ValueVT, Optional<CallingConv::ID> CC) const {
4416 bool IsABIRegCopy = CC.has_value();
4417 if (IsABIRegCopy && (ValueVT == MVT::f16 || ValueVT == MVT::bf16) &&
4418 PartVT == MVT::f32) {
4419 unsigned ValueBits = ValueVT.getSizeInBits();
4420 unsigned PartBits = PartVT.getSizeInBits();
4421 SDValue Val = Parts[0];
4422
4423 Val = DAG.getNode(ISD::BITCAST, DL, MVT::getIntegerVT(PartBits), Val);
4424 Val = DAG.getNode(ISD::TRUNCATE, DL, MVT::getIntegerVT(ValueBits), Val);
4425 Val = DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
4426 return Val;
4427 }
4428 return SDValue();
4429}
4430
4431SDValue ARMTargetLowering::LowerFormalArguments(
4432 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
4433 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
4434 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
4435 MachineFunction &MF = DAG.getMachineFunction();
4436 MachineFrameInfo &MFI = MF.getFrameInfo();
4437
4438 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
4439
4440 // Assign locations to all of the incoming arguments.
4441 SmallVector<CCValAssign, 16> ArgLocs;
4442 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
4443 *DAG.getContext());
4444 CCInfo.AnalyzeFormalArguments(Ins, CCAssignFnForCall(CallConv, isVarArg));
4445
4446 SmallVector<SDValue, 16> ArgValues;
4447 SDValue ArgValue;
4448 Function::const_arg_iterator CurOrigArg = MF.getFunction().arg_begin();
4449 unsigned CurArgIdx = 0;
4450
4451 // Initially ArgRegsSaveSize is zero.
4452 // Then we increase this value each time we meet byval parameter.
4453 // We also increase this value in case of varargs function.
4454 AFI->setArgRegsSaveSize(0);
4455
4456 // Calculate the amount of stack space that we need to allocate to store
4457 // byval and variadic arguments that are passed in registers.
4458 // We need to know this before we allocate the first byval or variadic
4459 // argument, as they will be allocated a stack slot below the CFA (Canonical
4460 // Frame Address, the stack pointer at entry to the function).
4461 unsigned ArgRegBegin = ARM::R4;
4462 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
4463 if (CCInfo.getInRegsParamsProcessed() >= CCInfo.getInRegsParamsCount())
4464 break;
4465
4466 CCValAssign &VA = ArgLocs[i];
4467 unsigned Index = VA.getValNo();
4468 ISD::ArgFlagsTy Flags = Ins[Index].Flags;
4469 if (!Flags.isByVal())
4470 continue;
4471
4472 assert(VA.isMemLoc() && "unexpected byval pointer in reg")(static_cast <bool> (VA.isMemLoc() && "unexpected byval pointer in reg"
) ? void (0) : __assert_fail ("VA.isMemLoc() && \"unexpected byval pointer in reg\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 4472, __extension__
__PRETTY_FUNCTION__))
;
4473 unsigned RBegin, REnd;
4474 CCInfo.getInRegsParamInfo(CCInfo.getInRegsParamsProcessed(), RBegin, REnd);
4475 ArgRegBegin = std::min(ArgRegBegin, RBegin);
4476
4477 CCInfo.nextInRegsParam();
4478 }
4479 CCInfo.rewindByValRegsInfo();
4480
4481 int lastInsIndex = -1;
4482 if (isVarArg && MFI.hasVAStart()) {
4483 unsigned RegIdx = CCInfo.getFirstUnallocated(GPRArgRegs);
4484 if (RegIdx != array_lengthof(GPRArgRegs))
4485 ArgRegBegin = std::min(ArgRegBegin, (unsigned)GPRArgRegs[RegIdx]);
4486 }
4487
4488 unsigned TotalArgRegsSaveSize = 4 * (ARM::R4 - ArgRegBegin);
4489 AFI->setArgRegsSaveSize(TotalArgRegsSaveSize);
4490 auto PtrVT = getPointerTy(DAG.getDataLayout());
4491
4492 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
4493 CCValAssign &VA = ArgLocs[i];
4494 if (Ins[VA.getValNo()].isOrigArg()) {
4495 std::advance(CurOrigArg,
4496 Ins[VA.getValNo()].getOrigArgIndex() - CurArgIdx);
4497 CurArgIdx = Ins[VA.getValNo()].getOrigArgIndex();
4498 }
4499 // Arguments stored in registers.
4500 if (VA.isRegLoc()) {
4501 EVT RegVT = VA.getLocVT();
4502
4503 if (VA.needsCustom() && VA.getLocVT() == MVT::v2f64) {
4504 // f64 and vector types are split up into multiple registers or
4505 // combinations of registers and stack slots.
4506 SDValue ArgValue1 =
4507 GetF64FormalArgument(VA, ArgLocs[++i], Chain, DAG, dl);
4508 VA = ArgLocs[++i]; // skip ahead to next loc
4509 SDValue ArgValue2;
4510 if (VA.isMemLoc()) {
4511 int FI = MFI.CreateFixedObject(8, VA.getLocMemOffset(), true);
4512 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
4513 ArgValue2 = DAG.getLoad(
4514 MVT::f64, dl, Chain, FIN,
4515 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI));
4516 } else {
4517 ArgValue2 = GetF64FormalArgument(VA, ArgLocs[++i], Chain, DAG, dl);
4518 }
4519 ArgValue = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
4520 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, ArgValue,
4521 ArgValue1, DAG.getIntPtrConstant(0, dl));
4522 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, ArgValue,
4523 ArgValue2, DAG.getIntPtrConstant(1, dl));
4524 } else if (VA.needsCustom() && VA.getLocVT() == MVT::f64) {
4525 ArgValue = GetF64FormalArgument(VA, ArgLocs[++i], Chain, DAG, dl);
4526 } else {
4527 const TargetRegisterClass *RC;
4528
4529 if (RegVT == MVT::f16 || RegVT == MVT::bf16)
4530 RC = &ARM::HPRRegClass;
4531 else if (RegVT == MVT::f32)
4532 RC = &ARM::SPRRegClass;
4533 else if (RegVT == MVT::f64 || RegVT == MVT::v4f16 ||
4534 RegVT == MVT::v4bf16)
4535 RC = &ARM::DPRRegClass;
4536 else if (RegVT == MVT::v2f64 || RegVT == MVT::v8f16 ||
4537 RegVT == MVT::v8bf16)
4538 RC = &ARM::QPRRegClass;
4539 else if (RegVT == MVT::i32)
4540 RC = AFI->isThumb1OnlyFunction() ? &ARM::tGPRRegClass
4541 : &ARM::GPRRegClass;
4542 else
4543 llvm_unreachable("RegVT not supported by FORMAL_ARGUMENTS Lowering")::llvm::llvm_unreachable_internal("RegVT not supported by FORMAL_ARGUMENTS Lowering"
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 4543)
;
4544
4545 // Transform the arguments in physical registers into virtual ones.
4546 Register Reg = MF.addLiveIn(VA.getLocReg(), RC);
4547 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
4548
4549 // If this value is passed in r0 and has the returned attribute (e.g.
4550 // C++ 'structors), record this fact for later use.
4551 if (VA.getLocReg() == ARM::R0 && Ins[VA.getValNo()].Flags.isReturned()) {
4552 AFI->setPreservesR0();
4553 }
4554 }
4555
4556 // If this is an 8 or 16-bit value, it is really passed promoted
4557 // to 32 bits. Insert an assert[sz]ext to capture this, then
4558 // truncate to the right size.
4559 switch (VA.getLocInfo()) {
4560 default: llvm_unreachable("Unknown loc info!")::llvm::llvm_unreachable_internal("Unknown loc info!", "llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 4560)
;
4561 case CCValAssign::Full: break;
4562 case CCValAssign::BCvt:
4563 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
4564 break;
4565 case CCValAssign::SExt:
4566 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
4567 DAG.getValueType(VA.getValVT()));
4568 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
4569 break;
4570 case CCValAssign::ZExt:
4571 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
4572 DAG.getValueType(VA.getValVT()));
4573 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
4574 break;
4575 }
4576
4577 // f16 arguments have their size extended to 4 bytes and passed as if they
4578 // had been copied to the LSBs of a 32-bit register.
4579 // For that, it's passed extended to i32 (soft ABI) or to f32 (hard ABI)
4580 if (VA.needsCustom() &&
4581 (VA.getValVT() == MVT::f16 || VA.getValVT() == MVT::bf16))
4582 ArgValue = MoveToHPR(dl, DAG, VA.getLocVT(), VA.getValVT(), ArgValue);
4583
4584 InVals.push_back(ArgValue);
4585 } else { // VA.isRegLoc()
4586 // Only arguments passed on the stack should make it here.
4587 assert(VA.isMemLoc())(static_cast <bool> (VA.isMemLoc()) ? void (0) : __assert_fail
("VA.isMemLoc()", "llvm/lib/Target/ARM/ARMISelLowering.cpp",
4587, __extension__ __PRETTY_FUNCTION__))
;
4588 assert(VA.getValVT() != MVT::i64 && "i64 should already be lowered")(static_cast <bool> (VA.getValVT() != MVT::i64 &&
"i64 should already be lowered") ? void (0) : __assert_fail (
"VA.getValVT() != MVT::i64 && \"i64 should already be lowered\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 4588, __extension__
__PRETTY_FUNCTION__))
;
4589
4590 int index = VA.getValNo();
4591
4592 // Some Ins[] entries become multiple ArgLoc[] entries.
4593 // Process them only once.
4594 if (index != lastInsIndex)
4595 {
4596 ISD::ArgFlagsTy Flags = Ins[index].Flags;
4597 // FIXME: For now, all byval parameter objects are marked mutable.
4598 // This can be changed with more analysis.
4599 // In case of tail call optimization mark all arguments mutable.
4600 // Since they could be overwritten by lowering of arguments in case of
4601 // a tail call.
4602 if (Flags.isByVal()) {
4603 assert(Ins[index].isOrigArg() &&(static_cast <bool> (Ins[index].isOrigArg() && "Byval arguments cannot be implicit"
) ? void (0) : __assert_fail ("Ins[index].isOrigArg() && \"Byval arguments cannot be implicit\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 4604, __extension__
__PRETTY_FUNCTION__))
4604 "Byval arguments cannot be implicit")(static_cast <bool> (Ins[index].isOrigArg() && "Byval arguments cannot be implicit"
) ? void (0) : __assert_fail ("Ins[index].isOrigArg() && \"Byval arguments cannot be implicit\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 4604, __extension__
__PRETTY_FUNCTION__))
;
4605 unsigned CurByValIndex = CCInfo.getInRegsParamsProcessed();
4606
4607 int FrameIndex = StoreByValRegs(
4608 CCInfo, DAG, dl, Chain, &*CurOrigArg, CurByValIndex,
4609 VA.getLocMemOffset(), Flags.getByValSize());
4610 InVals.push_back(DAG.getFrameIndex(FrameIndex, PtrVT));
4611 CCInfo.nextInRegsParam();
4612 } else {
4613 unsigned FIOffset = VA.getLocMemOffset();
4614 int FI = MFI.CreateFixedObject(VA.getLocVT().getSizeInBits()/8,
4615 FIOffset, true);
4616
4617 // Create load nodes to retrieve arguments from the stack.
4618 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
4619 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
4620 MachinePointerInfo::getFixedStack(
4621 DAG.getMachineFunction(), FI)));
4622 }
4623 lastInsIndex = index;
4624 }
4625 }
4626 }
4627
4628 // varargs
4629 if (isVarArg && MFI.hasVAStart()) {
4630 VarArgStyleRegisters(CCInfo, DAG, dl, Chain, CCInfo.getNextStackOffset(),
4631 TotalArgRegsSaveSize);
4632 if (AFI->isCmseNSEntryFunction()) {
4633 DiagnosticInfoUnsupported Diag(
4634 DAG.getMachineFunction().getFunction(),
4635 "secure entry function must not be variadic", dl.getDebugLoc());
4636 DAG.getContext()->diagnose(Diag);
4637 }
4638 }
4639
4640 unsigned StackArgSize = CCInfo.getNextStackOffset();
4641 bool TailCallOpt = MF.getTarget().Options.GuaranteedTailCallOpt;
4642 if (canGuaranteeTCO(CallConv, TailCallOpt)) {
4643 // The only way to guarantee a tail call is if the callee restores its
4644 // argument area, but it must also keep the stack aligned when doing so.
4645 const DataLayout &DL = DAG.getDataLayout();
4646 StackArgSize = alignTo(StackArgSize, DL.getStackAlignment());
4647
4648 AFI->setArgumentStackToRestore(StackArgSize);
4649 }
4650 AFI->setArgumentStackSize(StackArgSize);
4651
4652 if (CCInfo.getNextStackOffset() > 0 && AFI->isCmseNSEntryFunction()) {
4653 DiagnosticInfoUnsupported Diag(
4654 DAG.getMachineFunction().getFunction(),
4655 "secure entry function requires arguments on stack", dl.getDebugLoc());
4656 DAG.getContext()->diagnose(Diag);
4657 }
4658
4659 return Chain;
4660}
4661
4662/// isFloatingPointZero - Return true if this is +0.0.
4663static bool isFloatingPointZero(SDValue Op) {
4664 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
11
Calling 'dyn_cast<llvm::ConstantFPSDNode, llvm::SDValue>'
19
Returning from 'dyn_cast<llvm::ConstantFPSDNode, llvm::SDValue>'
20
Assuming 'CFP' is null
4665 return CFP->getValueAPF().isPosZero();
4666 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
4667 // Maybe this has already been legalized into the constant pool?
4668 if (Op.getOperand(1).getOpcode() == ARMISD::Wrapper) {
21
Calling 'SDValue::getOperand'
4669 SDValue WrapperOp = Op.getOperand(1).getOperand(0);
4670 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(WrapperOp))
4671 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
4672 return CFP->getValueAPF().isPosZero();
4673 }
4674 } else if (Op->getOpcode() == ISD::BITCAST &&
4675 Op->getValueType(0) == MVT::f64) {
4676 // Handle (ISD::BITCAST (ARMISD::VMOVIMM (ISD::TargetConstant 0)) MVT::f64)
4677 // created by LowerConstantFP().
4678 SDValue BitcastOp = Op->getOperand(0);
4679 if (BitcastOp->getOpcode() == ARMISD::VMOVIMM &&
4680 isNullConstant(BitcastOp->getOperand(0)))
4681 return true;
4682 }
4683 return false;
4684}
4685
4686/// Returns appropriate ARM CMP (cmp) and corresponding condition code for
4687/// the given operands.
4688SDValue ARMTargetLowering::getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
4689 SDValue &ARMcc, SelectionDAG &DAG,
4690 const SDLoc &dl) const {
4691 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.getNode())) {
4692 unsigned C = RHSC->getZExtValue();
4693 if (!isLegalICmpImmediate((int32_t)C)) {
4694 // Constant does not fit, try adjusting it by one.
4695 switch (CC) {
4696 default: break;
4697 case ISD::SETLT:
4698 case ISD::SETGE:
4699 if (C != 0x80000000 && isLegalICmpImmediate(C-1)) {
4700 CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT;
4701 RHS = DAG.getConstant(C - 1, dl, MVT::i32);
4702 }
4703 break;
4704 case ISD::SETULT:
4705 case ISD::SETUGE:
4706 if (C != 0 && isLegalICmpImmediate(C-1)) {
4707 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT;
4708 RHS = DAG.getConstant(C - 1, dl, MVT::i32);
4709 }
4710 break;
4711 case ISD::SETLE:
4712 case ISD::SETGT:
4713 if (C != 0x7fffffff && isLegalICmpImmediate(C+1)) {
4714 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE;
4715 RHS = DAG.getConstant(C + 1, dl, MVT::i32);
4716 }
4717 break;
4718 case ISD::SETULE:
4719 case ISD::SETUGT:
4720 if (C != 0xffffffff && isLegalICmpImmediate(C+1)) {
4721 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
4722 RHS = DAG.getConstant(C + 1, dl, MVT::i32);
4723 }
4724 break;
4725 }
4726 }
4727 } else if ((ARM_AM::getShiftOpcForNode(LHS.getOpcode()) != ARM_AM::no_shift) &&
4728 (ARM_AM::getShiftOpcForNode(RHS.getOpcode()) == ARM_AM::no_shift)) {
4729 // In ARM and Thumb-2, the compare instructions can shift their second
4730 // operand.
4731 CC = ISD::getSetCCSwappedOperands(CC);
4732 std::swap(LHS, RHS);
4733 }
4734
4735 // Thumb1 has very limited immediate modes, so turning an "and" into a
4736 // shift can save multiple instructions.
4737 //
4738 // If we have (x & C1), and C1 is an appropriate mask, we can transform it
4739 // into "((x << n) >> n)". But that isn't necessarily profitable on its
4740 // own. If it's the operand to an unsigned comparison with an immediate,
4741 // we can eliminate one of the shifts: we transform
4742 // "((x << n) >> n) == C2" to "(x << n) == (C2 << n)".
4743 //
4744 // We avoid transforming cases which aren't profitable due to encoding
4745 // details:
4746 //
4747 // 1. C2 fits into the immediate field of a cmp, and the transformed version
4748 // would not; in that case, we're essentially trading one immediate load for
4749 // another.
4750 // 2. C1 is 255 or 65535, so we can use uxtb or uxth.
4751 // 3. C2 is zero; we have other code for this special case.
4752 //
4753 // FIXME: Figure out profitability for Thumb2; we usually can't save an
4754 // instruction, since the AND is always one instruction anyway, but we could
4755 // use narrow instructions in some cases.
4756 if (Subtarget->isThumb1Only() && LHS->getOpcode() == ISD::AND &&
4757 LHS->hasOneUse() && isa<ConstantSDNode>(LHS.getOperand(1)) &&
4758 LHS.getValueType() == MVT::i32 && isa<ConstantSDNode>(RHS) &&
4759 !isSignedIntSetCC(CC)) {
4760 unsigned Mask = cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue();
4761 auto *RHSC = cast<ConstantSDNode>(RHS.getNode());
4762 uint64_t RHSV = RHSC->getZExtValue();
4763 if (isMask_32(Mask) && (RHSV & ~Mask) == 0 && Mask != 255 && Mask != 65535) {
4764 unsigned ShiftBits = countLeadingZeros(Mask);
4765 if (RHSV && (RHSV > 255 || (RHSV << ShiftBits) <= 255)) {
4766 SDValue ShiftAmt = DAG.getConstant(ShiftBits, dl, MVT::i32);
4767 LHS = DAG.getNode(ISD::SHL, dl, MVT::i32, LHS.getOperand(0), ShiftAmt);
4768 RHS = DAG.getConstant(RHSV << ShiftBits, dl, MVT::i32);
4769 }
4770 }
4771 }
4772
4773 // The specific comparison "(x<<c) > 0x80000000U" can be optimized to a
4774 // single "lsls x, c+1". The shift sets the "C" and "Z" flags the same
4775 // way a cmp would.
4776 // FIXME: Add support for ARM/Thumb2; this would need isel patterns, and
4777 // some tweaks to the heuristics for the previous and->shift transform.
4778 // FIXME: Optimize cases where the LHS isn't a shift.
4779 if (Subtarget->isThumb1Only() && LHS->getOpcode() == ISD::SHL &&
4780 isa<ConstantSDNode>(RHS) &&
4781 cast<ConstantSDNode>(RHS)->getZExtValue() == 0x80000000U &&
4782 CC == ISD::SETUGT && isa<ConstantSDNode>(LHS.getOperand(1)) &&
4783 cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue() < 31) {
4784 unsigned ShiftAmt =
4785 cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue() + 1;
4786 SDValue Shift = DAG.getNode(ARMISD::LSLS, dl,
4787 DAG.getVTList(MVT::i32, MVT::i32),
4788 LHS.getOperand(0),
4789 DAG.getConstant(ShiftAmt, dl, MVT::i32));
4790 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, ARM::CPSR,
4791 Shift.getValue(1), SDValue());
4792 ARMcc = DAG.getConstant(ARMCC::HI, dl, MVT::i32);
4793 return Chain.getValue(1);
4794 }
4795
4796 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
4797
4798 // If the RHS is a constant zero then the V (overflow) flag will never be
4799 // set. This can allow us to simplify GE to PL or LT to MI, which can be
4800 // simpler for other passes (like the peephole optimiser) to deal with.
4801 if (isNullConstant(RHS)) {
4802 switch (CondCode) {
4803 default: break;
4804 case ARMCC::GE:
4805 CondCode = ARMCC::PL;
4806 break;
4807 case ARMCC::LT:
4808 CondCode = ARMCC::MI;
4809 break;
4810 }
4811 }
4812
4813 ARMISD::NodeType CompareType;
4814 switch (CondCode) {
4815 default:
4816 CompareType = ARMISD::CMP;
4817 break;
4818 case ARMCC::EQ:
4819 case ARMCC::NE:
4820 // Uses only Z Flag
4821 CompareType = ARMISD::CMPZ;
4822 break;
4823 }
4824 ARMcc = DAG.getConstant(CondCode, dl, MVT::i32);
4825 return DAG.getNode(CompareType, dl, MVT::Glue, LHS, RHS);
4826}
4827
4828/// Returns a appropriate VFP CMP (fcmp{s|d}+fmstat) for the given operands.
4829SDValue ARMTargetLowering::getVFPCmp(SDValue LHS, SDValue RHS,
4830 SelectionDAG &DAG, const SDLoc &dl,
4831 bool Signaling) const {
4832 assert(Subtarget->hasFP64() || RHS.getValueType() != MVT::f64)(static_cast <bool> (Subtarget->hasFP64() || RHS.getValueType
() != MVT::f64) ? void (0) : __assert_fail ("Subtarget->hasFP64() || RHS.getValueType() != MVT::f64"
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 4832, __extension__
__PRETTY_FUNCTION__))
;
7
Assuming the condition is true
8
'?' condition is true
4833 SDValue Cmp;
4834 if (!isFloatingPointZero(RHS))
9
Value assigned to 'Op.Node'
10
Calling 'isFloatingPointZero'
4835 Cmp = DAG.getNode(Signaling ? ARMISD::CMPFPE : ARMISD::CMPFP,
4836 dl, MVT::Glue, LHS, RHS);
4837 else
4838 Cmp = DAG.getNode(Signaling ? ARMISD::CMPFPEw0 : ARMISD::CMPFPw0,
4839 dl, MVT::Glue, LHS);
4840 return DAG.getNode(ARMISD::FMSTAT, dl, MVT::Glue, Cmp);
4841}
4842
4843/// duplicateCmp - Glue values can have only one use, so this function
4844/// duplicates a comparison node.
4845SDValue
4846ARMTargetLowering::duplicateCmp(SDValue Cmp, SelectionDAG &DAG) const {
4847 unsigned Opc = Cmp.getOpcode();
4848 SDLoc DL(Cmp);
4849 if (Opc == ARMISD::CMP || Opc == ARMISD::CMPZ)
4850 return DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0),Cmp.getOperand(1));
4851
4852 assert(Opc == ARMISD::FMSTAT && "unexpected comparison operation")(static_cast <bool> (Opc == ARMISD::FMSTAT && "unexpected comparison operation"
) ? void (0) : __assert_fail ("Opc == ARMISD::FMSTAT && \"unexpected comparison operation\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 4852, __extension__
__PRETTY_FUNCTION__))
;
4853 Cmp = Cmp.getOperand(0);
4854 Opc = Cmp.getOpcode();
4855 if (Opc == ARMISD::CMPFP)
4856 Cmp = DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0),Cmp.getOperand(1));
4857 else {
4858 assert(Opc == ARMISD::CMPFPw0 && "unexpected operand of FMSTAT")(static_cast <bool> (Opc == ARMISD::CMPFPw0 && "unexpected operand of FMSTAT"
) ? void (0) : __assert_fail ("Opc == ARMISD::CMPFPw0 && \"unexpected operand of FMSTAT\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 4858, __extension__
__PRETTY_FUNCTION__))
;
4859 Cmp = DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0));
4860 }
4861 return DAG.getNode(ARMISD::FMSTAT, DL, MVT::Glue, Cmp);
4862}
4863
4864// This function returns three things: the arithmetic computation itself
4865// (Value), a comparison (OverflowCmp), and a condition code (ARMcc). The
4866// comparison and the condition code define the case in which the arithmetic
4867// computation *does not* overflow.
4868std::pair<SDValue, SDValue>
4869ARMTargetLowering::getARMXALUOOp(SDValue Op, SelectionDAG &DAG,
4870 SDValue &ARMcc) const {
4871 assert(Op.getValueType() == MVT::i32 && "Unsupported value type")(static_cast <bool> (Op.getValueType() == MVT::i32 &&
"Unsupported value type") ? void (0) : __assert_fail ("Op.getValueType() == MVT::i32 && \"Unsupported value type\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 4871, __extension__
__PRETTY_FUNCTION__))
;
4872
4873 SDValue Value, OverflowCmp;
4874 SDValue LHS = Op.getOperand(0);
4875 SDValue RHS = Op.getOperand(1);
4876 SDLoc dl(Op);
4877
4878 // FIXME: We are currently always generating CMPs because we don't support
4879 // generating CMN through the backend. This is not as good as the natural
4880 // CMP case because it causes a register dependency and cannot be folded
4881 // later.
4882
4883 switch (Op.getOpcode()) {
4884 default:
4885 llvm_unreachable("Unknown overflow instruction!")::llvm::llvm_unreachable_internal("Unknown overflow instruction!"
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 4885)
;
4886 case ISD::SADDO:
4887 ARMcc = DAG.getConstant(ARMCC::VC, dl, MVT::i32);
4888 Value = DAG.getNode(ISD::ADD, dl, Op.getValueType(), LHS, RHS);
4889 OverflowCmp = DAG.getNode(ARMISD::CMP, dl, MVT::Glue, Value, LHS);
4890 break;
4891 case ISD::UADDO:
4892 ARMcc = DAG.getConstant(ARMCC::HS, dl, MVT::i32);
4893 // We use ADDC here to correspond to its use in LowerUnsignedALUO.
4894 // We do not use it in the USUBO case as Value may not be used.
4895 Value = DAG.getNode(ARMISD::ADDC, dl,
4896 DAG.getVTList(Op.getValueType(), MVT::i32), LHS, RHS)
4897 .getValue(0);
4898 OverflowCmp = DAG.getNode(ARMISD::CMP, dl, MVT::Glue, Value, LHS);
4899 break;
4900 case ISD::SSUBO:
4901 ARMcc = DAG.getConstant(ARMCC::VC, dl, MVT::i32);
4902 Value = DAG.getNode(ISD::SUB, dl, Op.getValueType(), LHS, RHS);
4903 OverflowCmp = DAG.getNode(ARMISD::CMP, dl, MVT::Glue, LHS, RHS);
4904 break;
4905 case ISD::USUBO:
4906 ARMcc = DAG.getConstant(ARMCC::HS, dl, MVT::i32);
4907 Value = DAG.getNode(ISD::SUB, dl, Op.getValueType(), LHS, RHS);
4908 OverflowCmp = DAG.getNode(ARMISD::CMP, dl, MVT::Glue, LHS, RHS);
4909 break;
4910 case ISD::UMULO:
4911 // We generate a UMUL_LOHI and then check if the high word is 0.
4912 ARMcc = DAG.getConstant(ARMCC::EQ, dl, MVT::i32);
4913 Value = DAG.getNode(ISD::UMUL_LOHI, dl,
4914 DAG.getVTList(Op.getValueType(), Op.getValueType()),
4915 LHS, RHS);
4916 OverflowCmp = DAG.getNode(ARMISD::CMP, dl, MVT::Glue, Value.getValue(1),
4917 DAG.getConstant(0, dl, MVT::i32));
4918 Value = Value.getValue(0); // We only want the low 32 bits for the result.
4919 break;
4920 case ISD::SMULO:
4921 // We generate a SMUL_LOHI and then check if all the bits of the high word
4922 // are the same as the sign bit of the low word.
4923 ARMcc = DAG.getConstant(ARMCC::EQ, dl, MVT::i32);
4924 Value = DAG.getNode(ISD::SMUL_LOHI, dl,
4925 DAG.getVTList(Op.getValueType(), Op.getValueType()),
4926 LHS, RHS);
4927 OverflowCmp = DAG.getNode(ARMISD::CMP, dl, MVT::Glue, Value.getValue(1),
4928 DAG.getNode(ISD::SRA, dl, Op.getValueType(),
4929 Value.getValue(0),
4930 DAG.getConstant(31, dl, MVT::i32)));
4931 Value = Value.getValue(0); // We only want the low 32 bits for the result.
4932 break;
4933 } // switch (...)
4934
4935 return std::make_pair(Value, OverflowCmp);
4936}
4937
4938SDValue
4939ARMTargetLowering::LowerSignedALUO(SDValue Op, SelectionDAG &DAG) const {
4940 // Let legalize expand this if it isn't a legal type yet.
4941 if (!DAG.getTargetLoweringInfo().isTypeLegal(Op.getValueType()))
4942 return SDValue();
4943
4944 SDValue Value, OverflowCmp;
4945 SDValue ARMcc;
4946 std::tie(Value, OverflowCmp) = getARMXALUOOp(Op, DAG, ARMcc);
4947 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
4948 SDLoc dl(Op);
4949 // We use 0 and 1 as false and true values.
4950 SDValue TVal = DAG.getConstant(1, dl, MVT::i32);
4951 SDValue FVal = DAG.getConstant(0, dl, MVT::i32);
4952 EVT VT = Op.getValueType();
4953
4954 SDValue Overflow = DAG.getNode(ARMISD::CMOV, dl, VT, TVal, FVal,
4955 ARMcc, CCR, OverflowCmp);
4956
4957 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
4958 return DAG.getNode(ISD::MERGE_VALUES, dl, VTs, Value, Overflow);
4959}
4960
4961static SDValue ConvertBooleanCarryToCarryFlag(SDValue BoolCarry,
4962 SelectionDAG &DAG) {
4963 SDLoc DL(BoolCarry);
4964 EVT CarryVT = BoolCarry.getValueType();
4965
4966 // This converts the boolean value carry into the carry flag by doing
4967 // ARMISD::SUBC Carry, 1
4968 SDValue Carry = DAG.getNode(ARMISD::SUBC, DL,
4969 DAG.getVTList(CarryVT, MVT::i32),
4970 BoolCarry, DAG.getConstant(1, DL, CarryVT));
4971 return Carry.getValue(1);
4972}
4973
4974static SDValue ConvertCarryFlagToBooleanCarry(SDValue Flags, EVT VT,
4975 SelectionDAG &DAG) {
4976 SDLoc DL(Flags);
4977
4978 // Now convert the carry flag into a boolean carry. We do this
4979 // using ARMISD:ADDE 0, 0, Carry
4980 return DAG.getNode(ARMISD::ADDE, DL, DAG.getVTList(VT, MVT::i32),
4981 DAG.getConstant(0, DL, MVT::i32),
4982 DAG.getConstant(0, DL, MVT::i32), Flags);
4983}
4984
4985SDValue ARMTargetLowering::LowerUnsignedALUO(SDValue Op,
4986 SelectionDAG &DAG) const {
4987 // Let legalize expand this if it isn't a legal type yet.
4988 if (!DAG.getTargetLoweringInfo().isTypeLegal(Op.getValueType()))
4989 return SDValue();
4990
4991 SDValue LHS = Op.getOperand(0);
4992 SDValue RHS = Op.getOperand(1);
4993 SDLoc dl(Op);
4994
4995 EVT VT = Op.getValueType();
4996 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
4997 SDValue Value;
4998 SDValue Overflow;
4999 switch (Op.getOpcode()) {
5000 default:
5001 llvm_unreachable("Unknown overflow instruction!")::llvm::llvm_unreachable_internal("Unknown overflow instruction!"
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 5001)
;
5002 case ISD::UADDO:
5003 Value = DAG.getNode(ARMISD::ADDC, dl, VTs, LHS, RHS);
5004 // Convert the carry flag into a boolean value.
5005 Overflow = ConvertCarryFlagToBooleanCarry(Value.getValue(1), VT, DAG);
5006 break;
5007 case ISD::USUBO: {
5008 Value = DAG.getNode(ARMISD::SUBC, dl, VTs, LHS, RHS);
5009 // Convert the carry flag into a boolean value.
5010 Overflow = ConvertCarryFlagToBooleanCarry(Value.getValue(1), VT, DAG);
5011 // ARMISD::SUBC returns 0 when we have to borrow, so make it an overflow
5012 // value. So compute 1 - C.
5013 Overflow = DAG.getNode(ISD::SUB, dl, MVT::i32,
5014 DAG.getConstant(1, dl, MVT::i32), Overflow);
5015 break;
5016 }
5017 }
5018
5019 return DAG.getNode(ISD::MERGE_VALUES, dl, VTs, Value, Overflow);
5020}
5021
5022static SDValue LowerADDSUBSAT(SDValue Op, SelectionDAG &DAG,
5023 const ARMSubtarget *Subtarget) {
5024 EVT VT = Op.getValueType();
5025 if (!Subtarget->hasV6Ops() || !Subtarget->hasDSP())
5026 return SDValue();
5027 if (!VT.isSimple())
5028 return SDValue();
5029
5030 unsigned NewOpcode;
5031 switch (VT.getSimpleVT().SimpleTy) {
5032 default:
5033 return SDValue();
5034 case MVT::i8:
5035 switch (Op->getOpcode()) {
5036 case ISD::UADDSAT:
5037 NewOpcode = ARMISD::UQADD8b;
5038 break;
5039 case ISD::SADDSAT:
5040 NewOpcode = ARMISD::QADD8b;
5041 break;
5042 case ISD::USUBSAT:
5043 NewOpcode = ARMISD::UQSUB8b;
5044 break;
5045 case ISD::SSUBSAT:
5046 NewOpcode = ARMISD::QSUB8b;
5047 break;
5048 }
5049 break;
5050 case MVT::i16:
5051 switch (Op->getOpcode()) {
5052 case ISD::UADDSAT:
5053 NewOpcode = ARMISD::UQADD16b;
5054 break;
5055 case ISD::SADDSAT:
5056 NewOpcode = ARMISD::QADD16b;
5057 break;
5058 case ISD::USUBSAT:
5059 NewOpcode = ARMISD::UQSUB16b;
5060 break;
5061 case ISD::SSUBSAT:
5062 NewOpcode = ARMISD::QSUB16b;
5063 break;
5064 }
5065 break;
5066 }
5067
5068 SDLoc dl(Op);
5069 SDValue Add =
5070 DAG.getNode(NewOpcode, dl, MVT::i32,
5071 DAG.getSExtOrTrunc(Op->getOperand(0), dl, MVT::i32),
5072 DAG.getSExtOrTrunc(Op->getOperand(1), dl, MVT::i32));
5073 return DAG.getNode(ISD::TRUNCATE, dl, VT, Add);
5074}
5075
5076SDValue ARMTargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
5077 SDValue Cond = Op.getOperand(0);
5078 SDValue SelectTrue = Op.getOperand(1);
5079 SDValue SelectFalse = Op.getOperand(2);
5080 SDLoc dl(Op);
5081 unsigned Opc = Cond.getOpcode();
5082
5083 if (Cond.getResNo() == 1 &&
5084 (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO ||
5085 Opc == ISD::USUBO)) {
5086 if (!DAG.getTargetLoweringInfo().isTypeLegal(Cond->getValueType(0)))
5087 return SDValue();
5088
5089 SDValue Value, OverflowCmp;
5090 SDValue ARMcc;
5091 std::tie(Value, OverflowCmp) = getARMXALUOOp(Cond, DAG, ARMcc);
5092 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
5093 EVT VT = Op.getValueType();
5094
5095 return getCMOV(dl, VT, SelectTrue, SelectFalse, ARMcc, CCR,
5096 OverflowCmp, DAG);
5097 }
5098
5099 // Convert:
5100 //
5101 // (select (cmov 1, 0, cond), t, f) -> (cmov t, f, cond)
5102 // (select (cmov 0, 1, cond), t, f) -> (cmov f, t, cond)
5103 //
5104 if (Cond.getOpcode() == ARMISD::CMOV && Cond.hasOneUse()) {
5105 const ConstantSDNode *CMOVTrue =
5106 dyn_cast<ConstantSDNode>(Cond.getOperand(0));
5107 const ConstantSDNode *CMOVFalse =
5108 dyn_cast<ConstantSDNode>(Cond.getOperand(1));
5109
5110 if (CMOVTrue && CMOVFalse) {
5111 unsigned CMOVTrueVal = CMOVTrue->getZExtValue();
5112 unsigned CMOVFalseVal = CMOVFalse->getZExtValue();
5113
5114 SDValue True;
5115 SDValue False;
5116 if (CMOVTrueVal == 1 && CMOVFalseVal == 0) {
5117 True = SelectTrue;
5118 False = SelectFalse;
5119 } else if (CMOVTrueVal == 0 && CMOVFalseVal == 1) {
5120 True = SelectFalse;
5121 False = SelectTrue;
5122 }
5123
5124 if (True.getNode() && False.getNode()) {
5125 EVT VT = Op.getValueType();
5126 SDValue ARMcc = Cond.getOperand(2);
5127 SDValue CCR = Cond.getOperand(3);
5128 SDValue Cmp = duplicateCmp(Cond.getOperand(4), DAG);
5129 assert(True.getValueType() == VT)(static_cast <bool> (True.getValueType() == VT) ? void (
0) : __assert_fail ("True.getValueType() == VT", "llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 5129, __extension__ __PRETTY_FUNCTION__))
;
5130 return getCMOV(dl, VT, True, False, ARMcc, CCR, Cmp, DAG);
5131 }
5132 }
5133 }
5134
5135 // ARM's BooleanContents value is UndefinedBooleanContent. Mask out the
5136 // undefined bits before doing a full-word comparison with zero.
5137 Cond = DAG.getNode(ISD::AND, dl, Cond.getValueType(), Cond,
5138 DAG.getConstant(1, dl, Cond.getValueType()));
5139
5140 return DAG.getSelectCC(dl, Cond,
5141 DAG.getConstant(0, dl, Cond.getValueType()),
5142 SelectTrue, SelectFalse, ISD::SETNE);
5143}
5144
5145static void checkVSELConstraints(ISD::CondCode CC, ARMCC::CondCodes &CondCode,
5146 bool &swpCmpOps, bool &swpVselOps) {
5147 // Start by selecting the GE condition code for opcodes that return true for
5148 // 'equality'
5149 if (CC == ISD::SETUGE || CC == ISD::SETOGE || CC == ISD::SETOLE ||
5150 CC == ISD::SETULE || CC == ISD::SETGE || CC == ISD::SETLE)
5151 CondCode = ARMCC::GE;
5152
5153 // and GT for opcodes that return false for 'equality'.
5154 else if (CC == ISD::SETUGT || CC == ISD::SETOGT || CC == ISD::SETOLT ||
5155 CC == ISD::SETULT || CC == ISD::SETGT || CC == ISD::SETLT)
5156 CondCode = ARMCC::GT;
5157
5158 // Since we are constrained to GE/GT, if the opcode contains 'less', we need
5159 // to swap the compare operands.
5160 if (CC == ISD::SETOLE || CC == ISD::SETULE || CC == ISD::SETOLT ||
5161 CC == ISD::SETULT || CC == ISD::SETLE || CC == ISD::SETLT)
5162 swpCmpOps = true;
5163
5164 // Both GT and GE are ordered comparisons, and return false for 'unordered'.
5165 // If we have an unordered opcode, we need to swap the operands to the VSEL
5166 // instruction (effectively negating the condition).
5167 //
5168 // This also has the effect of swapping which one of 'less' or 'greater'
5169 // returns true, so we also swap the compare operands. It also switches
5170 // whether we return true for 'equality', so we compensate by picking the
5171 // opposite condition code to our original choice.
5172 if (CC == ISD::SETULE || CC == ISD::SETULT || CC == ISD::SETUGE ||
5173 CC == ISD::SETUGT) {
5174 swpCmpOps = !swpCmpOps;
5175 swpVselOps = !swpVselOps;
5176 CondCode = CondCode == ARMCC::GT ? ARMCC::GE : ARMCC::GT;
5177 }
5178
5179 // 'ordered' is 'anything but unordered', so use the VS condition code and
5180 // swap the VSEL operands.
5181 if (CC == ISD::SETO) {
5182 CondCode = ARMCC::VS;
5183 swpVselOps = true;
5184 }
5185
5186 // 'unordered or not equal' is 'anything but equal', so use the EQ condition
5187 // code and swap the VSEL operands. Also do this if we don't care about the
5188 // unordered case.
5189 if (CC == ISD::SETUNE || CC == ISD::SETNE) {
5190 CondCode = ARMCC::EQ;
5191 swpVselOps = true;
5192 }
5193}
5194
5195SDValue ARMTargetLowering::getCMOV(const SDLoc &dl, EVT VT, SDValue FalseVal,
5196 SDValue TrueVal, SDValue ARMcc, SDValue CCR,
5197 SDValue Cmp, SelectionDAG &DAG) const {
5198 if (!Subtarget->hasFP64() && VT == MVT::f64) {
5199 FalseVal = DAG.getNode(ARMISD::VMOVRRD, dl,
5200 DAG.getVTList(MVT::i32, MVT::i32), FalseVal);
5201 TrueVal = DAG.getNode(ARMISD::VMOVRRD, dl,
5202 DAG.getVTList(MVT::i32, MVT::i32), TrueVal);
5203
5204 SDValue TrueLow = TrueVal.getValue(0);
5205 SDValue TrueHigh = TrueVal.getValue(1);
5206 SDValue FalseLow = FalseVal.getValue(0);
5207 SDValue FalseHigh = FalseVal.getValue(1);
5208
5209 SDValue Low = DAG.getNode(ARMISD::CMOV, dl, MVT::i32, FalseLow, TrueLow,
5210 ARMcc, CCR, Cmp);
5211 SDValue High = DAG.getNode(ARMISD::CMOV, dl, MVT::i32, FalseHigh, TrueHigh,
5212 ARMcc, CCR, duplicateCmp(Cmp, DAG));
5213
5214 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Low, High);
5215 } else {
5216 return DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMcc, CCR,
5217 Cmp);
5218 }
5219}
5220
5221static bool isGTorGE(ISD::CondCode CC) {
5222 return CC == ISD::SETGT || CC == ISD::SETGE;
5223}
5224
5225static bool isLTorLE(ISD::CondCode CC) {
5226 return CC == ISD::SETLT || CC == ISD::SETLE;
5227}
5228
5229// See if a conditional (LHS CC RHS ? TrueVal : FalseVal) is lower-saturating.
5230// All of these conditions (and their <= and >= counterparts) will do:
5231// x < k ? k : x
5232// x > k ? x : k
5233// k < x ? x : k
5234// k > x ? k : x
5235static bool isLowerSaturate(const SDValue LHS, const SDValue RHS,
5236 const SDValue TrueVal, const SDValue FalseVal,
5237 const ISD::CondCode CC, const SDValue K) {
5238 return (isGTorGE(CC) &&
5239 ((K == LHS && K == TrueVal) || (K == RHS && K == FalseVal))) ||
5240 (isLTorLE(CC) &&
5241 ((K == RHS && K == TrueVal) || (K == LHS && K == FalseVal)));
5242}
5243
5244// Check if two chained conditionals could be converted into SSAT or USAT.
5245//
5246// SSAT can replace a set of two conditional selectors that bound a number to an
5247// interval of type [k, ~k] when k + 1 is a power of 2. Here are some examples:
5248//
5249// x < -k ? -k : (x > k ? k : x)
5250// x < -k ? -k : (x < k ? x : k)
5251// x > -k ? (x > k ? k : x) : -k
5252// x < k ? (x < -k ? -k : x) : k
5253// etc.
5254//
5255// LLVM canonicalizes these to either a min(max()) or a max(min())
5256// pattern. This function tries to match one of these and will return a SSAT
5257// node if successful.
5258//
5259// USAT works similarily to SSAT but bounds on the interval [0, k] where k + 1
5260// is a power of 2.
5261static SDValue LowerSaturatingConditional(SDValue Op, SelectionDAG &DAG) {
5262 EVT VT = Op.getValueType();
5263 SDValue V1 = Op.getOperand(0);
5264 SDValue K1 = Op.getOperand(1);
5265 SDValue TrueVal1 = Op.getOperand(2);
5266 SDValue FalseVal1 = Op.getOperand(3);
5267 ISD::CondCode CC1 = cast<CondCodeSDNode>(Op.getOperand(4))->get();
5268
5269 const SDValue Op2 = isa<ConstantSDNode>(TrueVal1) ? FalseVal1 : TrueVal1;
5270 if (Op2.getOpcode() != ISD::SELECT_CC)
5271 return SDValue();
5272
5273 SDValue V2 = Op2.getOperand(0);
5274 SDValue K2 = Op2.getOperand(1);
5275 SDValue TrueVal2 = Op2.getOperand(2);
5276 SDValue FalseVal2 = Op2.getOperand(3);
5277 ISD::CondCode CC2 = cast<CondCodeSDNode>(Op2.getOperand(4))->get();
5278
5279 SDValue V1Tmp = V1;
5280 SDValue V2Tmp = V2;
5281
5282 // Check that the registers and the constants match a max(min()) or min(max())
5283 // pattern
5284 if (V1Tmp != TrueVal1 || V2Tmp != TrueVal2 || K1 != FalseVal1 ||
5285 K2 != FalseVal2 ||
5286 !((isGTorGE(CC1) && isLTorLE(CC2)) || (isLTorLE(CC1) && isGTorGE(CC2))))
5287 return SDValue();
5288
5289 // Check that the constant in the lower-bound check is
5290 // the opposite of the constant in the upper-bound check
5291 // in 1's complement.
5292 if (!isa<ConstantSDNode>(K1) || !isa<ConstantSDNode>(K2))
5293 return SDValue();
5294
5295 int64_t Val1 = cast<ConstantSDNode>(K1)->getSExtValue();
5296 int64_t Val2 = cast<ConstantSDNode>(K2)->getSExtValue();
5297 int64_t PosVal = std::max(Val1, Val2);
5298 int64_t NegVal = std::min(Val1, Val2);
5299
5300 if (!((Val1 > Val2 && isLTorLE(CC1)) || (Val1 < Val2 && isLTorLE(CC2))) ||
5301 !isPowerOf2_64(PosVal + 1))
5302 return SDValue();
5303
5304 // Handle the difference between USAT (unsigned) and SSAT (signed)
5305 // saturation
5306 // At this point, PosVal is guaranteed to be positive
5307 uint64_t K = PosVal;
5308 SDLoc dl(Op);
5309 if (Val1 == ~Val2)
5310 return DAG.getNode(ARMISD::SSAT, dl, VT, V2Tmp,
5311 DAG.getConstant(countTrailingOnes(K), dl, VT));
5312 if (NegVal == 0)
5313 return DAG.getNode(ARMISD::USAT, dl, VT, V2Tmp,
5314 DAG.getConstant(countTrailingOnes(K), dl, VT));
5315
5316 return SDValue();
5317}
5318
5319// Check if a condition of the type x < k ? k : x can be converted into a
5320// bit operation instead of conditional moves.
5321// Currently this is allowed given:
5322// - The conditions and values match up
5323// - k is 0 or -1 (all ones)
5324// This function will not check the last condition, thats up to the caller
5325// It returns true if the transformation can be made, and in such case
5326// returns x in V, and k in SatK.
5327static bool isLowerSaturatingConditional(const SDValue &Op, SDValue &V,
5328 SDValue &SatK)
5329{
5330 SDValue LHS = Op.getOperand(0);
5331 SDValue RHS = Op.getOperand(1);
5332 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
5333 SDValue TrueVal = Op.getOperand(2);
5334 SDValue FalseVal = Op.getOperand(3);
5335
5336 SDValue *K = isa<ConstantSDNode>(LHS) ? &LHS : isa<ConstantSDNode>(RHS)
5337 ? &RHS
5338 : nullptr;
5339
5340 // No constant operation in comparison, early out
5341 if (!K)
5342 return false;
5343
5344 SDValue KTmp = isa<ConstantSDNode>(TrueVal) ? TrueVal : FalseVal;
5345 V = (KTmp == TrueVal) ? FalseVal : TrueVal;
5346 SDValue VTmp = (K && *K == LHS) ? RHS : LHS;
5347
5348 // If the constant on left and right side, or variable on left and right,
5349 // does not match, early out
5350 if (*K != KTmp || V != VTmp)
5351 return false;
5352
5353 if (isLowerSaturate(LHS, RHS, TrueVal, FalseVal, CC, *K)) {
5354 SatK = *K;
5355 return true;
5356 }
5357
5358 return false;
5359}
5360
5361bool ARMTargetLowering::isUnsupportedFloatingType(EVT VT) const {
5362 if (VT == MVT::f32)
5363 return !Subtarget->hasVFP2Base();
5364 if (VT == MVT::f64)
5365 return !Subtarget->hasFP64();
5366 if (VT == MVT::f16)
5367 return !Subtarget->hasFullFP16();
5368 return false;
5369}
5370
5371SDValue ARMTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
5372 EVT VT = Op.getValueType();
5373 SDLoc dl(Op);
5374
5375 // Try to convert two saturating conditional selects into a single SSAT
5376 if ((!Subtarget->isThumb() && Subtarget->hasV6Ops()) || Subtarget->isThumb2())
5377 if (SDValue SatValue = LowerSaturatingConditional(Op, DAG))
5378 return SatValue;
5379
5380 // Try to convert expressions of the form x < k ? k : x (and similar forms)
5381 // into more efficient bit operations, which is possible when k is 0 or -1
5382 // On ARM and Thumb-2 which have flexible operand 2 this will result in
5383 // single instructions. On Thumb the shift and the bit operation will be two
5384 // instructions.
5385 // Only allow this transformation on full-width (32-bit) operations
5386 SDValue LowerSatConstant;
5387 SDValue SatValue;
5388 if (VT == MVT::i32 &&
5389 isLowerSaturatingConditional(Op, SatValue, LowerSatConstant)) {
5390 SDValue ShiftV = DAG.getNode(ISD::SRA, dl, VT, SatValue,
5391 DAG.getConstant(31, dl, VT));
5392 if (isNullConstant(LowerSatConstant)) {
5393 SDValue NotShiftV = DAG.getNode(ISD::XOR, dl, VT, ShiftV,
5394 DAG.getAllOnesConstant(dl, VT));
5395 return DAG.getNode(ISD::AND, dl, VT, SatValue, NotShiftV);
5396 } else if (isAllOnesConstant(LowerSatConstant))
5397 return DAG.getNode(ISD::OR, dl, VT, SatValue, ShiftV);
5398 }
5399
5400 SDValue LHS = Op.getOperand(0);
5401 SDValue RHS = Op.getOperand(1);
5402 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
5403 SDValue TrueVal = Op.getOperand(2);
5404 SDValue FalseVal = Op.getOperand(3);
5405 ConstantSDNode *CFVal = dyn_cast<ConstantSDNode>(FalseVal);
5406 ConstantSDNode *CTVal = dyn_cast<ConstantSDNode>(TrueVal);
5407
5408 if (Subtarget->hasV8_1MMainlineOps() && CFVal && CTVal &&
5409 LHS.getValueType() == MVT::i32 && RHS.getValueType() == MVT::i32) {
5410 unsigned TVal = CTVal->getZExtValue();
5411 unsigned FVal = CFVal->getZExtValue();
5412 unsigned Opcode = 0;
5413
5414 if (TVal == ~FVal) {
5415 Opcode = ARMISD::CSINV;
5416 } else if (TVal == ~FVal + 1) {
5417 Opcode = ARMISD::CSNEG;
5418 } else if (TVal + 1 == FVal) {
5419 Opcode = ARMISD::CSINC;
5420 } else if (TVal == FVal + 1) {
5421 Opcode = ARMISD::CSINC;
5422 std::swap(TrueVal, FalseVal);
5423 std::swap(TVal, FVal);
5424 CC = ISD::getSetCCInverse(CC, LHS.getValueType());
5425 }
5426
5427 if (Opcode) {
5428 // If one of the constants is cheaper than another, materialise the
5429 // cheaper one and let the csel generate the other.
5430 if (Opcode != ARMISD::CSINC &&
5431 HasLowerConstantMaterializationCost(FVal, TVal, Subtarget)) {
5432 std::swap(TrueVal, FalseVal);
5433 std::swap(TVal, FVal);
5434 CC = ISD::getSetCCInverse(CC, LHS.getValueType());
5435 }
5436
5437 // Attempt to use ZR checking TVal is 0, possibly inverting the condition
5438 // to get there. CSINC not is invertable like the other two (~(~a) == a,
5439 // -(-a) == a, but (a+1)+1 != a).
5440 if (FVal == 0 && Opcode != ARMISD::CSINC) {
5441 std::swap(TrueVal, FalseVal);
5442 std::swap(TVal, FVal);
5443 CC = ISD::getSetCCInverse(CC, LHS.getValueType());
5444 }
5445
5446 // Drops F's value because we can get it by inverting/negating TVal.
5447 FalseVal = TrueVal;
5448
5449 SDValue ARMcc;
5450 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
5451 EVT VT = TrueVal.getValueType();
5452 return DAG.getNode(Opcode, dl, VT, TrueVal, FalseVal, ARMcc, Cmp);
5453 }
5454 }
5455
5456 if (isUnsupportedFloatingType(LHS.getValueType())) {
5457 DAG.getTargetLoweringInfo().softenSetCCOperands(
5458 DAG, LHS.getValueType(), LHS, RHS, CC, dl, LHS, RHS);
5459
5460 // If softenSetCCOperands only returned one value, we should compare it to
5461 // zero.
5462 if (!RHS.getNode()) {
5463 RHS = DAG.getConstant(0, dl, LHS.getValueType());
5464 CC = ISD::SETNE;
5465 }
5466 }
5467
5468 if (LHS.getValueType() == MVT::i32) {
5469 // Try to generate VSEL on ARMv8.
5470 // The VSEL instruction can't use all the usual ARM condition
5471 // codes: it only has two bits to select the condition code, so it's
5472 // constrained to use only GE, GT, VS and EQ.
5473 //
5474 // To implement all the various ISD::SETXXX opcodes, we sometimes need to
5475 // swap the operands of the previous compare instruction (effectively
5476 // inverting the compare condition, swapping 'less' and 'greater') and
5477 // sometimes need to swap the operands to the VSEL (which inverts the
5478 // condition in the sense of firing whenever the previous condition didn't)
5479 if (Subtarget->hasFPARMv8Base() && (TrueVal.getValueType() == MVT::f16 ||
5480 TrueVal.getValueType() == MVT::f32 ||
5481 TrueVal.getValueType() == MVT::f64)) {
5482 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
5483 if (CondCode == ARMCC::LT || CondCode == ARMCC::LE ||
5484 CondCode == ARMCC::VC || CondCode == ARMCC::NE) {
5485 CC = ISD::getSetCCInverse(CC, LHS.getValueType());
5486 std::swap(TrueVal, FalseVal);
5487 }
5488 }
5489
5490 SDValue ARMcc;
5491 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
5492 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
5493 // Choose GE over PL, which vsel does now support
5494 if (cast<ConstantSDNode>(ARMcc)->getZExtValue() == ARMCC::PL)
5495 ARMcc = DAG.getConstant(ARMCC::GE, dl, MVT::i32);
5496 return getCMOV(dl, VT, FalseVal, TrueVal, ARMcc, CCR, Cmp, DAG);
5497 }
5498
5499 ARMCC::CondCodes CondCode, CondCode2;
5500 FPCCToARMCC(CC, CondCode, CondCode2);
5501
5502 // Normalize the fp compare. If RHS is zero we prefer to keep it there so we
5503 // match CMPFPw0 instead of CMPFP, though we don't do this for f16 because we
5504 // must use VSEL (limited condition codes), due to not having conditional f16
5505 // moves.
5506 if (Subtarget->hasFPARMv8Base() &&
5507 !(isFloatingPointZero(RHS) && TrueVal.getValueType() != MVT::f16) &&
5508 (TrueVal.getValueType() == MVT::f16 ||
5509 TrueVal.getValueType() == MVT::f32 ||
5510 TrueVal.getValueType() == MVT::f64)) {
5511 bool swpCmpOps = false;
5512 bool swpVselOps = false;
5513 checkVSELConstraints(CC, CondCode, swpCmpOps, swpVselOps);
5514
5515 if (CondCode == ARMCC::GT || CondCode == ARMCC::GE ||
5516 CondCode == ARMCC::VS || CondCode == ARMCC::EQ) {
5517 if (swpCmpOps)
5518 std::swap(LHS, RHS);
5519 if (swpVselOps)
5520 std::swap(TrueVal, FalseVal);
5521 }
5522 }
5523
5524 SDValue ARMcc = DAG.getConstant(CondCode, dl, MVT::i32);
5525 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
5526 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
5527 SDValue Result = getCMOV(dl, VT, FalseVal, TrueVal, ARMcc, CCR, Cmp, DAG);
5528 if (CondCode2 != ARMCC::AL) {
5529 SDValue ARMcc2 = DAG.getConstant(CondCode2, dl, MVT::i32);
5530 // FIXME: Needs another CMP because flag can have but one use.
5531 SDValue Cmp2 = getVFPCmp(LHS, RHS, DAG, dl);
5532 Result = getCMOV(dl, VT, Result, TrueVal, ARMcc2, CCR, Cmp2, DAG);
5533 }
5534 return Result;
5535}
5536
5537/// canChangeToInt - Given the fp compare operand, return true if it is suitable
5538/// to morph to an integer compare sequence.
5539static bool canChangeToInt(SDValue Op, bool &SeenZero,
5540 const ARMSubtarget *Subtarget) {
5541 SDNode *N = Op.getNode();
5542 if (!N->hasOneUse())
5543 // Otherwise it requires moving the value from fp to integer registers.
5544 return false;
5545 if (!N->getNumValues())
5546 return false;
5547 EVT VT = Op.getValueType();
5548 if (VT != MVT::f32 && !Subtarget->isFPBrccSlow())
5549 // f32 case is generally profitable. f64 case only makes sense when vcmpe +
5550 // vmrs are very slow, e.g. cortex-a8.
5551 return false;
5552
5553 if (isFloatingPointZero(Op)) {
5554 SeenZero = true;
5555 return true;
5556 }
5557 return ISD::isNormalLoad(N);
5558}
5559
5560static SDValue bitcastf32Toi32(SDValue Op, SelectionDAG &DAG) {
5561 if (isFloatingPointZero(Op))
5562 return DAG.getConstant(0, SDLoc(Op), MVT::i32);
5563
5564 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Op))
5565 return DAG.getLoad(MVT::i32, SDLoc(Op), Ld->getChain(), Ld->getBasePtr(),
5566 Ld->getPointerInfo(), Ld->getAlign(),
5567 Ld->getMemOperand()->getFlags());
5568
5569 llvm_unreachable("Unknown VFP cmp argument!")::llvm::llvm_unreachable_internal("Unknown VFP cmp argument!"
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 5569)
;
5570}
5571
5572static void expandf64Toi32(SDValue Op, SelectionDAG &DAG,
5573 SDValue &RetVal1, SDValue &RetVal2) {
5574 SDLoc dl(Op);
5575
5576 if (isFloatingPointZero(Op)) {
5577 RetVal1 = DAG.getConstant(0, dl, MVT::i32);
5578 RetVal2 = DAG.getConstant(0, dl, MVT::i32);
5579 return;
5580 }
5581
5582 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Op)) {
5583 SDValue Ptr = Ld->getBasePtr();
5584 RetVal1 =
5585 DAG.getLoad(MVT::i32, dl, Ld->getChain(), Ptr, Ld->getPointerInfo(),
5586 Ld->getAlign(), Ld->getMemOperand()->getFlags());
5587
5588 EVT PtrType = Ptr.getValueType();
5589 SDValue NewPtr = DAG.getNode(ISD::ADD, dl,
5590 PtrType, Ptr, DAG.getConstant(4, dl, PtrType));
5591 RetVal2 = DAG.getLoad(MVT::i32, dl, Ld->getChain(), NewPtr,
5592 Ld->getPointerInfo().getWithOffset(4),
5593 commonAlignment(Ld->getAlign(), 4),
5594 Ld->getMemOperand()->getFlags());
5595 return;
5596 }
5597
5598 llvm_unreachable("Unknown VFP cmp argument!")::llvm::llvm_unreachable_internal("Unknown VFP cmp argument!"
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 5598)
;
5599}
5600
5601/// OptimizeVFPBrcond - With -enable-unsafe-fp-math, it's legal to optimize some
5602/// f32 and even f64 comparisons to integer ones.
5603SDValue
5604ARMTargetLowering::OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const {
5605 SDValue Chain = Op.getOperand(0);
5606 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
5607 SDValue LHS = Op.getOperand(2);
5608 SDValue RHS = Op.getOperand(3);
5609 SDValue Dest = Op.getOperand(4);
5610 SDLoc dl(Op);
5611
5612 bool LHSSeenZero = false;
5613 bool LHSOk = canChangeToInt(LHS, LHSSeenZero, Subtarget);
5614 bool RHSSeenZero = false;
5615 bool RHSOk = canChangeToInt(RHS, RHSSeenZero, Subtarget);
5616 if (LHSOk && RHSOk && (LHSSeenZero || RHSSeenZero)) {
5617 // If unsafe fp math optimization is enabled and there are no other uses of
5618 // the CMP operands, and the condition code is EQ or NE, we can optimize it
5619 // to an integer comparison.
5620 if (CC == ISD::SETOEQ)
5621 CC = ISD::SETEQ;
5622 else if (CC == ISD::SETUNE)
5623 CC = ISD::SETNE;
5624
5625 SDValue Mask = DAG.getConstant(0x7fffffff, dl, MVT::i32);
5626 SDValue ARMcc;
5627 if (LHS.getValueType() == MVT::f32) {
5628 LHS = DAG.getNode(ISD::AND, dl, MVT::i32,
5629 bitcastf32Toi32(LHS, DAG), Mask);
5630 RHS = DAG.getNode(ISD::AND, dl, MVT::i32,
5631 bitcastf32Toi32(RHS, DAG), Mask);
5632 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
5633 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
5634 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other,
5635 Chain, Dest, ARMcc, CCR, Cmp);
5636 }
5637
5638 SDValue LHS1, LHS2;
5639 SDValue RHS1, RHS2;
5640 expandf64Toi32(LHS, DAG, LHS1, LHS2);
5641 expandf64Toi32(RHS, DAG, RHS1, RHS2);
5642 LHS2 = DAG.getNode(ISD::AND, dl, MVT::i32, LHS2, Mask);
5643 RHS2 = DAG.getNode(ISD::AND, dl, MVT::i32, RHS2, Mask);
5644 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
5645 ARMcc = DAG.getConstant(CondCode, dl, MVT::i32);
5646 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Glue);
5647 SDValue Ops[] = { Chain, ARMcc, LHS1, LHS2, RHS1, RHS2, Dest };
5648 return DAG.getNode(ARMISD::BCC_i64, dl, VTList, Ops);
5649 }
5650
5651 return SDValue();
5652}
5653
5654SDValue ARMTargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
5655 SDValue Chain = Op.getOperand(0);
5656 SDValue Cond = Op.getOperand(1);
5657 SDValue Dest = Op.getOperand(2);
5658 SDLoc dl(Op);
5659
5660 // Optimize {s|u}{add|sub|mul}.with.overflow feeding into a branch
5661 // instruction.
5662 unsigned Opc = Cond.getOpcode();
5663 bool OptimizeMul = (Opc == ISD::SMULO || Opc == ISD::UMULO) &&
5664 !Subtarget->isThumb1Only();
5665 if (Cond.getResNo() == 1 &&
5666 (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO ||
5667 Opc == ISD::USUBO || OptimizeMul)) {
5668 // Only lower legal XALUO ops.
5669 if (!DAG.getTargetLoweringInfo().isTypeLegal(Cond->getValueType(0)))
5670 return SDValue();
5671
5672 // The actual operation with overflow check.
5673 SDValue Value, OverflowCmp;
5674 SDValue ARMcc;
5675 std::tie(Value, OverflowCmp) = getARMXALUOOp(Cond, DAG, ARMcc);
5676
5677 // Reverse the condition code.
5678 ARMCC::CondCodes CondCode =
5679 (ARMCC::CondCodes)cast<const ConstantSDNode>(ARMcc)->getZExtValue();
5680 CondCode = ARMCC::getOppositeCondition(CondCode);
5681 ARMcc = DAG.getConstant(CondCode, SDLoc(ARMcc), MVT::i32);
5682 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
5683
5684 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other, Chain, Dest, ARMcc, CCR,
5685 OverflowCmp);
5686 }
5687
5688 return SDValue();
5689}
5690
5691SDValue ARMTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
5692 SDValue Chain = Op.getOperand(0);
5693 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
5694 SDValue LHS = Op.getOperand(2);
5695 SDValue RHS = Op.getOperand(3);
5696 SDValue Dest = Op.getOperand(4);
5697 SDLoc dl(Op);
5698
5699 if (isUnsupportedFloatingType(LHS.getValueType())) {
5700 DAG.getTargetLoweringInfo().softenSetCCOperands(
5701 DAG, LHS.getValueType(), LHS, RHS, CC, dl, LHS, RHS);
5702
5703 // If softenSetCCOperands only returned one value, we should compare it to
5704 // zero.
5705 if (!RHS.getNode()) {
5706 RHS = DAG.getConstant(0, dl, LHS.getValueType());
5707 CC = ISD::SETNE;
5708 }
5709 }
5710
5711 // Optimize {s|u}{add|sub|mul}.with.overflow feeding into a branch
5712 // instruction.
5713 unsigned Opc = LHS.getOpcode();
5714 bool OptimizeMul = (Opc == ISD::SMULO || Opc == ISD::UMULO) &&
5715 !Subtarget->isThumb1Only();
5716 if (LHS.getResNo() == 1 && (isOneConstant(RHS) || isNullConstant(RHS)) &&
5717 (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO ||
5718 Opc == ISD::USUBO || OptimizeMul) &&
5719 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
5720 // Only lower legal XALUO ops.
5721 if (!DAG.getTargetLoweringInfo().isTypeLegal(LHS->getValueType(0)))
5722 return SDValue();
5723
5724 // The actual operation with overflow check.
5725 SDValue Value, OverflowCmp;
5726 SDValue ARMcc;
5727 std::tie(Value, OverflowCmp) = getARMXALUOOp(LHS.getValue(0), DAG, ARMcc);
5728
5729 if ((CC == ISD::SETNE) != isOneConstant(RHS)) {
5730 // Reverse the condition code.
5731 ARMCC::CondCodes CondCode =
5732 (ARMCC::CondCodes)cast<const ConstantSDNode>(ARMcc)->getZExtValue();
5733 CondCode = ARMCC::getOppositeCondition(CondCode);
5734 ARMcc = DAG.getConstant(CondCode, SDLoc(ARMcc), MVT::i32);
5735 }
5736 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
5737
5738 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other, Chain, Dest, ARMcc, CCR,
5739 OverflowCmp);
5740 }
5741
5742 if (LHS.getValueType() == MVT::i32) {
5743 SDValue ARMcc;
5744 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
5745 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
5746 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other,
5747 Chain, Dest, ARMcc, CCR, Cmp);
5748 }
5749
5750 if (getTargetMachine().Options.UnsafeFPMath &&
5751 (CC == ISD::SETEQ || CC == ISD::SETOEQ ||
5752 CC == ISD::SETNE || CC == ISD::SETUNE)) {
5753 if (SDValue Result = OptimizeVFPBrcond(Op, DAG))
5754 return Result;
5755 }
5756
5757 ARMCC::CondCodes CondCode, CondCode2;
5758 FPCCToARMCC(CC, CondCode, CondCode2);
5759
5760 SDValue ARMcc = DAG.getConstant(CondCode, dl, MVT::i32);
5761 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
5762 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
5763 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Glue);
5764 SDValue Ops[] = { Chain, Dest, ARMcc, CCR, Cmp };
5765 SDValue Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops);
5766 if (CondCode2 != ARMCC::AL) {
5767 ARMcc = DAG.getConstant(CondCode2, dl, MVT::i32);
5768 SDValue Ops[] = { Res, Dest, ARMcc, CCR, Res.getValue(1) };
5769 Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops);
5770 }
5771 return Res;
5772}
5773
5774SDValue ARMTargetLowering::LowerBR_JT(SDValue Op, SelectionDAG &DAG) const {
5775 SDValue Chain = Op.getOperand(0);
5776 SDValue Table = Op.getOperand(1);
5777 SDValue Index = Op.getOperand(2);
5778 SDLoc dl(Op);
5779
5780 EVT PTy = getPointerTy(DAG.getDataLayout());
5781 JumpTableSDNode *JT = cast<JumpTableSDNode>(Table);
5782 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PTy);
5783 Table = DAG.getNode(ARMISD::WrapperJT, dl, MVT::i32, JTI);
5784 Index = DAG.getNode(ISD::MUL, dl, PTy, Index, DAG.getConstant(4, dl, PTy));
5785 SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Table, Index);
5786 if (Subtarget->isThumb2() || (Subtarget->hasV8MBaselineOps() && Subtarget->isThumb())) {
5787 // Thumb2 and ARMv8-M use a two-level jump. That is, it jumps into the jump table
5788 // which does another jump to the destination. This also makes it easier
5789 // to translate it to TBB / TBH later (Thumb2 only).
5790 // FIXME: This might not work if the function is extremely large.
5791 return DAG.getNode(ARMISD::BR2_JT, dl, MVT::Other, Chain,
5792 Addr, Op.getOperand(2), JTI);
5793 }
5794 if (isPositionIndependent() || Subtarget->isROPI()) {
5795 Addr =
5796 DAG.getLoad((EVT)MVT::i32, dl, Chain, Addr,
5797 MachinePointerInfo::getJumpTable(DAG.getMachineFunction()));
5798 Chain = Addr.getValue(1);
5799 Addr = DAG.getNode(ISD::ADD, dl, PTy, Table, Addr);
5800 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI);
5801 } else {
5802 Addr =
5803 DAG.getLoad(PTy, dl, Chain, Addr,
5804 MachinePointerInfo::getJumpTable(DAG.getMachineFunction()));
5805 Chain = Addr.getValue(1);
5806 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI);
5807 }
5808}
5809
5810static SDValue LowerVectorFP_TO_INT(SDValue Op, SelectionDAG &DAG) {
5811 EVT VT = Op.getValueType();
5812 SDLoc dl(Op);
5813
5814 if (Op.getValueType().getVectorElementType() == MVT::i32) {
5815 if (Op.getOperand(0).getValueType().getVectorElementType() == MVT::f32)
5816 return Op;
5817 return DAG.UnrollVectorOp(Op.getNode());
5818 }
5819
5820 const bool HasFullFP16 = DAG.getSubtarget<ARMSubtarget>().hasFullFP16();
5821
5822 EVT NewTy;
5823 const EVT OpTy = Op.getOperand(0).getValueType();
5824 if (OpTy == MVT::v4f32)
5825 NewTy = MVT::v4i32;
5826 else if (OpTy == MVT::v4f16 && HasFullFP16)
5827 NewTy = MVT::v4i16;
5828 else if (OpTy == MVT::v8f16 && HasFullFP16)
5829 NewTy = MVT::v8i16;
5830 else
5831 llvm_unreachable("Invalid type for custom lowering!")::llvm::llvm_unreachable_internal("Invalid type for custom lowering!"
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 5831)
;
5832
5833 if (VT != MVT::v4i16 && VT != MVT::v8i16)
5834 return DAG.UnrollVectorOp(Op.getNode());
5835
5836 Op = DAG.getNode(Op.getOpcode(), dl, NewTy, Op.getOperand(0));
5837 return DAG.getNode(ISD::TRUNCATE, dl, VT, Op);
5838}
5839
5840SDValue ARMTargetLowering::LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) const {
5841 EVT VT = Op.getValueType();
5842 if (VT.isVector())
5843 return LowerVectorFP_TO_INT(Op, DAG);
5844
5845 bool IsStrict = Op->isStrictFPOpcode();
5846 SDValue SrcVal = Op.getOperand(IsStrict ? 1 : 0);
5847
5848 if (isUnsupportedFloatingType(SrcVal.getValueType())) {
5849 RTLIB::Libcall LC;
5850 if (Op.getOpcode() == ISD::FP_TO_SINT ||
5851 Op.getOpcode() == ISD::STRICT_FP_TO_SINT)
5852 LC = RTLIB::getFPTOSINT(SrcVal.getValueType(),
5853 Op.getValueType());
5854 else
5855 LC = RTLIB::getFPTOUINT(SrcVal.getValueType(),
5856 Op.getValueType());
5857 SDLoc Loc(Op);
5858 MakeLibCallOptions CallOptions;
5859 SDValue Chain = IsStrict ? Op.getOperand(0) : SDValue();
5860 SDValue Result;
5861 std::tie(Result, Chain) = makeLibCall(DAG, LC, Op.getValueType(), SrcVal,
5862 CallOptions, Loc, Chain);
5863 return IsStrict ? DAG.getMergeValues({Result, Chain}, Loc) : Result;
5864 }
5865
5866 // FIXME: Remove this when we have strict fp instruction selection patterns
5867 if (IsStrict) {
5868 SDLoc Loc(Op);
5869 SDValue Result =
5870 DAG.getNode(Op.getOpcode() == ISD::STRICT_FP_TO_SINT ? ISD::FP_TO_SINT
5871 : ISD::FP_TO_UINT,
5872 Loc, Op.getValueType(), SrcVal);
5873 return DAG.getMergeValues({Result, Op.getOperand(0)}, Loc);
5874 }
5875
5876 return Op;
5877}
5878
5879static SDValue LowerFP_TO_INT_SAT(SDValue Op, SelectionDAG &DAG,
5880 const ARMSubtarget *Subtarget) {
5881 EVT VT = Op.getValueType();
5882 EVT ToVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
5883 EVT FromVT = Op.getOperand(0).getValueType();
5884
5885 if (VT == MVT::i32 && ToVT == MVT::i32 && FromVT == MVT::f32)
5886 return Op;
5887 if (VT == MVT::i32 && ToVT == MVT::i32 && FromVT == MVT::f64 &&
5888 Subtarget->hasFP64())
5889 return Op;
5890 if (VT == MVT::i32 && ToVT == MVT::i32 && FromVT == MVT::f16 &&
5891 Subtarget->hasFullFP16())
5892 return Op;
5893 if (VT == MVT::v4i32 && ToVT == MVT::i32 && FromVT == MVT::v4f32 &&
5894 Subtarget->hasMVEFloatOps())
5895 return Op;
5896 if (VT == MVT::v8i16 && ToVT == MVT::i16 && FromVT == MVT::v8f16 &&
5897 Subtarget->hasMVEFloatOps())
5898 return Op;
5899
5900 if (FromVT != MVT::v4f32 && FromVT != MVT::v8f16)
5901 return SDValue();
5902
5903 SDLoc DL(Op);
5904 bool IsSigned = Op.getOpcode() == ISD::FP_TO_SINT_SAT;
5905 unsigned BW = ToVT.getScalarSizeInBits() - IsSigned;
5906 SDValue CVT = DAG.getNode(Op.getOpcode(), DL, VT, Op.getOperand(0),
5907 DAG.getValueType(VT.getScalarType()));
5908 SDValue Max = DAG.getNode(IsSigned ? ISD::SMIN : ISD::UMIN, DL, VT, CVT,
5909 DAG.getConstant((1 << BW) - 1, DL, VT));
5910 if (IsSigned)
5911 Max = DAG.getNode(ISD::SMAX, DL, VT, Max,
5912 DAG.getConstant(-(1 << BW), DL, VT));
5913 return Max;
5914}
5915
5916static SDValue LowerVectorINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
5917 EVT VT = Op.getValueType();
5918 SDLoc dl(Op);
5919
5920 if (Op.getOperand(0).getValueType().getVectorElementType() == MVT::i32) {
5921 if (VT.getVectorElementType() == MVT::f32)
5922 return Op;
5923 return DAG.UnrollVectorOp(Op.getNode());
5924 }
5925
5926 assert((Op.getOperand(0).getValueType() == MVT::v4i16 ||(static_cast <bool> ((Op.getOperand(0).getValueType() ==
MVT::v4i16 || Op.getOperand(0).getValueType() == MVT::v8i16)
&& "Invalid type for custom lowering!") ? void (0) :
__assert_fail ("(Op.getOperand(0).getValueType() == MVT::v4i16 || Op.getOperand(0).getValueType() == MVT::v8i16) && \"Invalid type for custom lowering!\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 5928, __extension__
__PRETTY_FUNCTION__))
5927 Op.getOperand(0).getValueType() == MVT::v8i16) &&(static_cast <bool> ((Op.getOperand(0).getValueType() ==
MVT::v4i16 || Op.getOperand(0).getValueType() == MVT::v8i16)
&& "Invalid type for custom lowering!") ? void (0) :
__assert_fail ("(Op.getOperand(0).getValueType() == MVT::v4i16 || Op.getOperand(0).getValueType() == MVT::v8i16) && \"Invalid type for custom lowering!\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 5928, __extension__
__PRETTY_FUNCTION__))
5928 "Invalid type for custom lowering!")(static_cast <bool> ((Op.getOperand(0).getValueType() ==
MVT::v4i16 || Op.getOperand(0).getValueType() == MVT::v8i16)
&& "Invalid type for custom lowering!") ? void (0) :
__assert_fail ("(Op.getOperand(0).getValueType() == MVT::v4i16 || Op.getOperand(0).getValueType() == MVT::v8i16) && \"Invalid type for custom lowering!\""
, "llvm/lib/Target/ARM/ARMISelLowering.cpp", 5928, __extension__
__PRETTY_FUNCTION__))
;
5929
5930 const bool HasFullFP16 = DAG.getSubtarget<ARMSubtarget>().hasFullFP16();
5931
5932 EVT DestVecType;
5933 if (VT == MVT::v4f32)
5934 DestVecType = MVT::v4i32;
5935 else if (VT == MVT::v4f16 && HasFullFP16)
5936 DestVecType = MVT::v4i16;
5937 else if (VT == MVT::v8f16 && HasFullFP16)
5938 DestVecType = MVT::v8i16;
5939 else
5940 return DAG.UnrollVectorOp(Op.getNode());
5941
5942 unsigned CastOpc;
5943 unsigned Opc;
5944 switch (Op.getOpcode()) {
5945 default: llvm_unreachable("Invalid opcode!")::llvm::llvm_unreachable_internal("Invalid opcode!", "llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 5945)
;
5946 case ISD::SINT_TO_FP:
5947 CastOpc = ISD::SIGN_EXTEND;
5948 Opc = ISD::SINT_TO_FP;
5949 break;
5950 case ISD::UINT_TO_FP:
5951 CastOpc = ISD::ZERO_EXTEND;
5952 Opc = ISD::UINT_TO_FP;
5953 break;
5954 }
5955
5956 Op = DAG.getNode(CastOpc, dl, DestVecType, Op.getOperand(0));
5957 return DAG.getNode(Opc, dl, VT, Op);
5958}
5959
5960SDValue ARMTargetLowering::LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) const {
5961 EVT VT = Op.getValueType();
5962 if (VT.isVector())
5963 return LowerVectorINT_TO_FP(Op, DAG);
5964 if (isUnsupportedFloatingType(VT)) {
5965 RTLIB::Libcall LC;
5966 if (Op.getOpcode() == ISD::SINT_TO_FP)
5967 LC = RTLIB::getSINTTOFP(Op.getOperand(0).getValueType(),
5968 Op.getValueType());
5969 else
5970 LC = RTLIB::getUINTTOFP(Op.getOperand(0).getValueType(),
5971 Op.getValueType());
5972 MakeLibCallOptions CallOptions;
5973 return makeLibCall(DAG, LC, Op.getValueType(), Op.getOperand(0),
5974 CallOptions, SDLoc(Op)).first;
5975 }
5976
5977 return Op;
5978}
5979
5980SDValue ARMTargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
5981 // Implement fcopysign with a fabs and a conditional fneg.
5982 SDValue Tmp0 = Op.getOperand(0);
5983 SDValue Tmp1 = Op.getOperand(1);
5984 SDLoc dl(Op);
5985 EVT VT = Op.getValueType();
5986 EVT SrcVT = Tmp1.getValueType();
5987 bool InGPR = Tmp0.getOpcode() == ISD::BITCAST ||
5988 Tmp0.getOpcode() == ARMISD::VMOVDRR;
5989 bool UseNEON = !InGPR && Subtarget->hasNEON();
5990
5991 if (UseNEON) {
5992 // Use VBSL to copy the sign bit.
5993 unsigned EncodedVal = ARM_AM::createVMOVModImm(0x6, 0x80);
5994 SDValue Mask = DAG.getNode(ARMISD::VMOVIMM, dl, MVT::v2i32,
5995 DAG.getTargetConstant(EncodedVal, dl, MVT::i32));
5996 EVT OpVT = (VT == MVT::f32) ? MVT::v2i32 : MVT::v1i64;
5997 if (VT == MVT::f64)
5998 Mask = DAG.getNode(ARMISD::VSHLIMM, dl, OpVT,
5999 DAG.getNode(ISD::BITCAST, dl, OpVT, Mask),
6000 DAG.getConstant(32, dl, MVT::i32));
6001 else /*if (VT == MVT::f32)*/
6002 Tmp0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f32, Tmp0);
6003 if (SrcVT == MVT::f32) {
6004 Tmp1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f32, Tmp1);
6005 if (VT == MVT::f64)
6006 Tmp1 = DAG.getNode(ARMISD::VSHLIMM, dl, OpVT,
6007 DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp1),
6008 DAG.getConstant(32, dl, MVT::i32));
6009 } else if (VT == MVT::f32)
6010 Tmp1 = DAG.getNode(ARMISD::VSHRuIMM, dl, MVT::v1i64,
6011 DAG.getNode(ISD::BITCAST, dl, MVT::v1i64, Tmp1),
6012 DAG.getConstant(32, dl, MVT::i32));
6013 Tmp0 = DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp0);
6014 Tmp1 = DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp1);
6015
6016 SDValue AllOnes = DAG.getTargetConstant(ARM_AM::createVMOVModImm(0xe, 0xff),
6017 dl, MVT::i32);
6018 AllOnes = DAG.getNode(ARMISD::VMOVIMM, dl, MVT::v8i8, AllOnes);
6019 SDValue MaskNot = DAG.getNode(ISD::XOR, dl, OpVT, Mask,
6020 DAG.getNode(ISD::BITCAST, dl, OpVT, AllOnes));
6021
6022 SDValue Res = DAG.getNode(ISD::OR, dl, OpVT,
6023 DAG.getNode(ISD::AND, dl, OpVT, Tmp1, Mask),
6024 DAG.getNode(ISD::AND, dl, OpVT, Tmp0, MaskNot));
6025 if (VT == MVT::f32) {
6026 Res = DAG.getNode(ISD::BITCAST, dl, MVT::v2f32, Res);
6027 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, Res,
6028 DAG.getConstant(0, dl, MVT::i32));
6029 } else {
6030 Res = DAG.getNode(ISD::BITCAST, dl, MVT::f64, Res);
6031 }
6032
6033