Bug Summary

File:llvm/include/llvm/CodeGen/SelectionDAGNodes.h
Warning:line 1124, column 10
Called C++ object pointer is null

Annotated Source Code

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clang -cc1 -cc1 -triple x86_64-pc-linux-gnu -analyze -disable-free -clear-ast-before-backend -disable-llvm-verifier -discard-value-names -main-file-name LegalizeIntegerTypes.cpp -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=cplusplus -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -analyzer-config-compatibility-mode=true -mrelocation-model pic -pic-level 2 -mframe-pointer=none -fmath-errno -ffp-contract=on -fno-rounding-math -mconstructor-aliases -funwind-tables=2 -target-cpu x86-64 -tune-cpu generic -debugger-tuning=gdb -ffunction-sections -fdata-sections -fcoverage-compilation-dir=/build/llvm-toolchain-snapshot-14~++20220116100644+5f782d25a742/build-llvm -resource-dir /usr/lib/llvm-14/lib/clang/14.0.0 -D _DEBUG -D _GNU_SOURCE -D __STDC_CONSTANT_MACROS -D __STDC_FORMAT_MACROS -D __STDC_LIMIT_MACROS -I lib/CodeGen/SelectionDAG -I /build/llvm-toolchain-snapshot-14~++20220116100644+5f782d25a742/llvm/lib/CodeGen/SelectionDAG -I include -I /build/llvm-toolchain-snapshot-14~++20220116100644+5f782d25a742/llvm/include -D _FORTIFY_SOURCE=2 -D NDEBUG -U NDEBUG -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/10/../../../../include/c++/10 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/10/../../../../include/x86_64-linux-gnu/c++/10 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/10/../../../../include/c++/10/backward -internal-isystem /usr/lib/llvm-14/lib/clang/14.0.0/include -internal-isystem /usr/local/include -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/10/../../../../x86_64-linux-gnu/include -internal-externc-isystem /usr/include/x86_64-linux-gnu -internal-externc-isystem /include -internal-externc-isystem /usr/include -fmacro-prefix-map=/build/llvm-toolchain-snapshot-14~++20220116100644+5f782d25a742/build-llvm=build-llvm -fmacro-prefix-map=/build/llvm-toolchain-snapshot-14~++20220116100644+5f782d25a742/= -fcoverage-prefix-map=/build/llvm-toolchain-snapshot-14~++20220116100644+5f782d25a742/build-llvm=build-llvm -fcoverage-prefix-map=/build/llvm-toolchain-snapshot-14~++20220116100644+5f782d25a742/= -O3 -Wno-unused-command-line-argument -Wno-unused-parameter -Wwrite-strings -Wno-missing-field-initializers -Wno-long-long -Wno-maybe-uninitialized -Wno-class-memaccess -Wno-redundant-move -Wno-pessimizing-move -Wno-noexcept-type -Wno-comment -std=c++14 -fdeprecated-macro -fdebug-compilation-dir=/build/llvm-toolchain-snapshot-14~++20220116100644+5f782d25a742/build-llvm -fdebug-prefix-map=/build/llvm-toolchain-snapshot-14~++20220116100644+5f782d25a742/build-llvm=build-llvm -fdebug-prefix-map=/build/llvm-toolchain-snapshot-14~++20220116100644+5f782d25a742/= -ferror-limit 19 -fvisibility-inlines-hidden -stack-protector 2 -fgnuc-version=4.2.1 -fcolor-diagnostics -vectorize-loops -vectorize-slp -analyzer-output=html -analyzer-config stable-report-filename=true -faddrsig -D__GCC_HAVE_DWARF2_CFI_ASM=1 -o /tmp/scan-build-2022-01-16-232930-107970-1 -x c++ /build/llvm-toolchain-snapshot-14~++20220116100644+5f782d25a742/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp

/build/llvm-toolchain-snapshot-14~++20220116100644+5f782d25a742/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp

1//===----- LegalizeIntegerTypes.cpp - Legalization of integer types -------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements integer type expansion and promotion for LegalizeTypes.
10// Promotion is the act of changing a computation in an illegal type into a
11// computation in a larger type. For example, implementing i8 arithmetic in an
12// i32 register (often needed on powerpc).
13// Expansion is the act of changing a computation in an illegal type into a
14// computation in two identical registers of a smaller type. For example,
15// implementing i64 arithmetic in two i32 registers (often needed on 32-bit
16// targets).
17//
18//===----------------------------------------------------------------------===//
19
20#include "LegalizeTypes.h"
21#include "llvm/Analysis/TargetLibraryInfo.h"
22#include "llvm/IR/DerivedTypes.h"
23#include "llvm/Support/ErrorHandling.h"
24#include "llvm/Support/KnownBits.h"
25#include "llvm/Support/raw_ostream.h"
26#include <algorithm>
27using namespace llvm;
28
29#define DEBUG_TYPE"legalize-types" "legalize-types"
30
31//===----------------------------------------------------------------------===//
32// Integer Result Promotion
33//===----------------------------------------------------------------------===//
34
35/// PromoteIntegerResult - This method is called when a result of a node is
36/// found to be in need of promotion to a larger type. At this point, the node
37/// may also have invalid operands or may have other results that need
38/// expansion, we just know that (at least) one result needs promotion.
39void DAGTypeLegalizer::PromoteIntegerResult(SDNode *N, unsigned ResNo) {
40 LLVM_DEBUG(dbgs() << "Promote integer result: "; N->dump(&DAG);do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("legalize-types")) { dbgs() << "Promote integer result: "
; N->dump(&DAG); dbgs() << "\n"; } } while (false
)
41 dbgs() << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("legalize-types")) { dbgs() << "Promote integer result: "
; N->dump(&DAG); dbgs() << "\n"; } } while (false
)
;
42 SDValue Res = SDValue();
43
44 // See if the target wants to custom expand this node.
45 if (CustomLowerNode(N, N->getValueType(ResNo), true)) {
46 LLVM_DEBUG(dbgs() << "Node has been custom expanded, done\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("legalize-types")) { dbgs() << "Node has been custom expanded, done\n"
; } } while (false)
;
47 return;
48 }
49
50 switch (N->getOpcode()) {
51 default:
52#ifndef NDEBUG
53 dbgs() << "PromoteIntegerResult #" << ResNo << ": ";
54 N->dump(&DAG); dbgs() << "\n";
55#endif
56 llvm_unreachable("Do not know how to promote this operator!")::llvm::llvm_unreachable_internal("Do not know how to promote this operator!"
, "llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp", 56
)
;
57 case ISD::MERGE_VALUES:Res = PromoteIntRes_MERGE_VALUES(N, ResNo); break;
58 case ISD::AssertSext: Res = PromoteIntRes_AssertSext(N); break;
59 case ISD::AssertZext: Res = PromoteIntRes_AssertZext(N); break;
60 case ISD::BITCAST: Res = PromoteIntRes_BITCAST(N); break;
61 case ISD::BITREVERSE: Res = PromoteIntRes_BITREVERSE(N); break;
62 case ISD::BSWAP: Res = PromoteIntRes_BSWAP(N); break;
63 case ISD::BUILD_PAIR: Res = PromoteIntRes_BUILD_PAIR(N); break;
64 case ISD::Constant: Res = PromoteIntRes_Constant(N); break;
65 case ISD::CTLZ_ZERO_UNDEF:
66 case ISD::CTLZ: Res = PromoteIntRes_CTLZ(N); break;
67 case ISD::PARITY:
68 case ISD::CTPOP: Res = PromoteIntRes_CTPOP_PARITY(N); break;
69 case ISD::CTTZ_ZERO_UNDEF:
70 case ISD::CTTZ: Res = PromoteIntRes_CTTZ(N); break;
71 case ISD::EXTRACT_VECTOR_ELT:
72 Res = PromoteIntRes_EXTRACT_VECTOR_ELT(N); break;
73 case ISD::LOAD: Res = PromoteIntRes_LOAD(cast<LoadSDNode>(N)); break;
74 case ISD::MLOAD: Res = PromoteIntRes_MLOAD(cast<MaskedLoadSDNode>(N));
75 break;
76 case ISD::MGATHER: Res = PromoteIntRes_MGATHER(cast<MaskedGatherSDNode>(N));
77 break;
78 case ISD::SELECT:
79 case ISD::VSELECT:
80 case ISD::VP_SELECT:
81 Res = PromoteIntRes_Select(N);
82 break;
83 case ISD::SELECT_CC: Res = PromoteIntRes_SELECT_CC(N); break;
84 case ISD::STRICT_FSETCC:
85 case ISD::STRICT_FSETCCS:
86 case ISD::SETCC: Res = PromoteIntRes_SETCC(N); break;
87 case ISD::SMIN:
88 case ISD::SMAX: Res = PromoteIntRes_SExtIntBinOp(N); break;
89 case ISD::UMIN:
90 case ISD::UMAX: Res = PromoteIntRes_UMINUMAX(N); break;
91
92 case ISD::SHL:
93 case ISD::VP_SHL: Res = PromoteIntRes_SHL(N); break;
94 case ISD::SIGN_EXTEND_INREG:
95 Res = PromoteIntRes_SIGN_EXTEND_INREG(N); break;
96 case ISD::SRA:
97 case ISD::VP_ASHR: Res = PromoteIntRes_SRA(N); break;
98 case ISD::SRL:
99 case ISD::VP_LSHR: Res = PromoteIntRes_SRL(N); break;
100 case ISD::TRUNCATE: Res = PromoteIntRes_TRUNCATE(N); break;
101 case ISD::UNDEF: Res = PromoteIntRes_UNDEF(N); break;
102 case ISD::VAARG: Res = PromoteIntRes_VAARG(N); break;
103 case ISD::VSCALE: Res = PromoteIntRes_VSCALE(N); break;
104
105 case ISD::EXTRACT_SUBVECTOR:
106 Res = PromoteIntRes_EXTRACT_SUBVECTOR(N); break;
107 case ISD::INSERT_SUBVECTOR:
108 Res = PromoteIntRes_INSERT_SUBVECTOR(N); break;
109 case ISD::VECTOR_REVERSE:
110 Res = PromoteIntRes_VECTOR_REVERSE(N); break;
111 case ISD::VECTOR_SHUFFLE:
112 Res = PromoteIntRes_VECTOR_SHUFFLE(N); break;
113 case ISD::VECTOR_SPLICE:
114 Res = PromoteIntRes_VECTOR_SPLICE(N); break;
115 case ISD::INSERT_VECTOR_ELT:
116 Res = PromoteIntRes_INSERT_VECTOR_ELT(N); break;
117 case ISD::BUILD_VECTOR:
118 Res = PromoteIntRes_BUILD_VECTOR(N); break;
119 case ISD::SCALAR_TO_VECTOR:
120 Res = PromoteIntRes_SCALAR_TO_VECTOR(N); break;
121 case ISD::SPLAT_VECTOR:
122 Res = PromoteIntRes_SPLAT_VECTOR(N); break;
123 case ISD::STEP_VECTOR: Res = PromoteIntRes_STEP_VECTOR(N); break;
124 case ISD::CONCAT_VECTORS:
125 Res = PromoteIntRes_CONCAT_VECTORS(N); break;
126
127 case ISD::ANY_EXTEND_VECTOR_INREG:
128 case ISD::SIGN_EXTEND_VECTOR_INREG:
129 case ISD::ZERO_EXTEND_VECTOR_INREG:
130 Res = PromoteIntRes_EXTEND_VECTOR_INREG(N); break;
131
132 case ISD::SIGN_EXTEND:
133 case ISD::ZERO_EXTEND:
134 case ISD::ANY_EXTEND: Res = PromoteIntRes_INT_EXTEND(N); break;
135
136 case ISD::STRICT_FP_TO_SINT:
137 case ISD::STRICT_FP_TO_UINT:
138 case ISD::FP_TO_SINT:
139 case ISD::FP_TO_UINT: Res = PromoteIntRes_FP_TO_XINT(N); break;
140
141 case ISD::FP_TO_SINT_SAT:
142 case ISD::FP_TO_UINT_SAT:
143 Res = PromoteIntRes_FP_TO_XINT_SAT(N); break;
144
145 case ISD::FP_TO_FP16: Res = PromoteIntRes_FP_TO_FP16(N); break;
146
147 case ISD::FLT_ROUNDS_: Res = PromoteIntRes_FLT_ROUNDS(N); break;
148
149 case ISD::AND:
150 case ISD::OR:
151 case ISD::XOR:
152 case ISD::ADD:
153 case ISD::SUB:
154 case ISD::MUL:
155 case ISD::VP_AND:
156 case ISD::VP_OR:
157 case ISD::VP_XOR:
158 case ISD::VP_ADD:
159 case ISD::VP_SUB:
160 case ISD::VP_MUL: Res = PromoteIntRes_SimpleIntBinOp(N); break;
161
162 case ISD::SDIV:
163 case ISD::SREM:
164 case ISD::VP_SDIV:
165 case ISD::VP_SREM: Res = PromoteIntRes_SExtIntBinOp(N); break;
166
167 case ISD::UDIV:
168 case ISD::UREM:
169 case ISD::VP_UDIV:
170 case ISD::VP_UREM: Res = PromoteIntRes_ZExtIntBinOp(N); break;
171
172 case ISD::SADDO:
173 case ISD::SSUBO: Res = PromoteIntRes_SADDSUBO(N, ResNo); break;
174 case ISD::UADDO:
175 case ISD::USUBO: Res = PromoteIntRes_UADDSUBO(N, ResNo); break;
176 case ISD::SMULO:
177 case ISD::UMULO: Res = PromoteIntRes_XMULO(N, ResNo); break;
178
179 case ISD::ADDE:
180 case ISD::SUBE:
181 case ISD::ADDCARRY:
182 case ISD::SUBCARRY: Res = PromoteIntRes_ADDSUBCARRY(N, ResNo); break;
183
184 case ISD::SADDO_CARRY:
185 case ISD::SSUBO_CARRY: Res = PromoteIntRes_SADDSUBO_CARRY(N, ResNo); break;
186
187 case ISD::SADDSAT:
188 case ISD::UADDSAT:
189 case ISD::SSUBSAT:
190 case ISD::USUBSAT:
191 case ISD::SSHLSAT:
192 case ISD::USHLSAT: Res = PromoteIntRes_ADDSUBSHLSAT(N); break;
193
194 case ISD::SMULFIX:
195 case ISD::SMULFIXSAT:
196 case ISD::UMULFIX:
197 case ISD::UMULFIXSAT: Res = PromoteIntRes_MULFIX(N); break;
198
199 case ISD::SDIVFIX:
200 case ISD::SDIVFIXSAT:
201 case ISD::UDIVFIX:
202 case ISD::UDIVFIXSAT: Res = PromoteIntRes_DIVFIX(N); break;
203
204 case ISD::ABS: Res = PromoteIntRes_ABS(N); break;
205
206 case ISD::ATOMIC_LOAD:
207 Res = PromoteIntRes_Atomic0(cast<AtomicSDNode>(N)); break;
208
209 case ISD::ATOMIC_LOAD_ADD:
210 case ISD::ATOMIC_LOAD_SUB:
211 case ISD::ATOMIC_LOAD_AND:
212 case ISD::ATOMIC_LOAD_CLR:
213 case ISD::ATOMIC_LOAD_OR:
214 case ISD::ATOMIC_LOAD_XOR:
215 case ISD::ATOMIC_LOAD_NAND:
216 case ISD::ATOMIC_LOAD_MIN:
217 case ISD::ATOMIC_LOAD_MAX:
218 case ISD::ATOMIC_LOAD_UMIN:
219 case ISD::ATOMIC_LOAD_UMAX:
220 case ISD::ATOMIC_SWAP:
221 Res = PromoteIntRes_Atomic1(cast<AtomicSDNode>(N)); break;
222
223 case ISD::ATOMIC_CMP_SWAP:
224 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
225 Res = PromoteIntRes_AtomicCmpSwap(cast<AtomicSDNode>(N), ResNo);
226 break;
227
228 case ISD::VECREDUCE_ADD:
229 case ISD::VECREDUCE_MUL:
230 case ISD::VECREDUCE_AND:
231 case ISD::VECREDUCE_OR:
232 case ISD::VECREDUCE_XOR:
233 case ISD::VECREDUCE_SMAX:
234 case ISD::VECREDUCE_SMIN:
235 case ISD::VECREDUCE_UMAX:
236 case ISD::VECREDUCE_UMIN:
237 Res = PromoteIntRes_VECREDUCE(N);
238 break;
239
240 case ISD::VP_REDUCE_ADD:
241 case ISD::VP_REDUCE_MUL:
242 case ISD::VP_REDUCE_AND:
243 case ISD::VP_REDUCE_OR:
244 case ISD::VP_REDUCE_XOR:
245 case ISD::VP_REDUCE_SMAX:
246 case ISD::VP_REDUCE_SMIN:
247 case ISD::VP_REDUCE_UMAX:
248 case ISD::VP_REDUCE_UMIN:
249 Res = PromoteIntRes_VP_REDUCE(N);
250 break;
251
252 case ISD::FREEZE:
253 Res = PromoteIntRes_FREEZE(N);
254 break;
255
256 case ISD::ROTL:
257 case ISD::ROTR:
258 Res = PromoteIntRes_Rotate(N);
259 break;
260
261 case ISD::FSHL:
262 case ISD::FSHR:
263 Res = PromoteIntRes_FunnelShift(N);
264 break;
265 }
266
267 // If the result is null then the sub-method took care of registering it.
268 if (Res.getNode())
269 SetPromotedInteger(SDValue(N, ResNo), Res);
270}
271
272SDValue DAGTypeLegalizer::PromoteIntRes_MERGE_VALUES(SDNode *N,
273 unsigned ResNo) {
274 SDValue Op = DisintegrateMERGE_VALUES(N, ResNo);
275 return GetPromotedInteger(Op);
276}
277
278SDValue DAGTypeLegalizer::PromoteIntRes_AssertSext(SDNode *N) {
279 // Sign-extend the new bits, and continue the assertion.
280 SDValue Op = SExtPromotedInteger(N->getOperand(0));
281 return DAG.getNode(ISD::AssertSext, SDLoc(N),
282 Op.getValueType(), Op, N->getOperand(1));
283}
284
285SDValue DAGTypeLegalizer::PromoteIntRes_AssertZext(SDNode *N) {
286 // Zero the new bits, and continue the assertion.
287 SDValue Op = ZExtPromotedInteger(N->getOperand(0));
288 return DAG.getNode(ISD::AssertZext, SDLoc(N),
289 Op.getValueType(), Op, N->getOperand(1));
290}
291
292SDValue DAGTypeLegalizer::PromoteIntRes_Atomic0(AtomicSDNode *N) {
293 EVT ResVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
294 SDValue Res = DAG.getAtomic(N->getOpcode(), SDLoc(N),
295 N->getMemoryVT(), ResVT,
296 N->getChain(), N->getBasePtr(),
297 N->getMemOperand());
298 // Legalize the chain result - switch anything that used the old chain to
299 // use the new one.
300 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
301 return Res;
302}
303
304SDValue DAGTypeLegalizer::PromoteIntRes_Atomic1(AtomicSDNode *N) {
305 SDValue Op2 = GetPromotedInteger(N->getOperand(2));
306 SDValue Res = DAG.getAtomic(N->getOpcode(), SDLoc(N),
307 N->getMemoryVT(),
308 N->getChain(), N->getBasePtr(),
309 Op2, N->getMemOperand());
310 // Legalize the chain result - switch anything that used the old chain to
311 // use the new one.
312 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
313 return Res;
314}
315
316SDValue DAGTypeLegalizer::PromoteIntRes_AtomicCmpSwap(AtomicSDNode *N,
317 unsigned ResNo) {
318 if (ResNo == 1) {
319 assert(N->getOpcode() == ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS)(static_cast <bool> (N->getOpcode() == ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS
) ? void (0) : __assert_fail ("N->getOpcode() == ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS"
, "llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp", 319
, __extension__ __PRETTY_FUNCTION__))
;
320 EVT SVT = getSetCCResultType(N->getOperand(2).getValueType());
321 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(1));
322
323 // Only use the result of getSetCCResultType if it is legal,
324 // otherwise just use the promoted result type (NVT).
325 if (!TLI.isTypeLegal(SVT))
326 SVT = NVT;
327
328 SDVTList VTs = DAG.getVTList(N->getValueType(0), SVT, MVT::Other);
329 SDValue Res = DAG.getAtomicCmpSwap(
330 ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, SDLoc(N), N->getMemoryVT(), VTs,
331 N->getChain(), N->getBasePtr(), N->getOperand(2), N->getOperand(3),
332 N->getMemOperand());
333 ReplaceValueWith(SDValue(N, 0), Res.getValue(0));
334 ReplaceValueWith(SDValue(N, 2), Res.getValue(2));
335 return Res.getValue(1);
336 }
337
338 // Op2 is used for the comparison and thus must be extended according to the
339 // target's atomic operations. Op3 is merely stored and so can be left alone.
340 SDValue Op2 = N->getOperand(2);
341 SDValue Op3 = GetPromotedInteger(N->getOperand(3));
342 switch (TLI.getExtendForAtomicCmpSwapArg()) {
343 case ISD::SIGN_EXTEND:
344 Op2 = SExtPromotedInteger(Op2);
345 break;
346 case ISD::ZERO_EXTEND:
347 Op2 = ZExtPromotedInteger(Op2);
348 break;
349 case ISD::ANY_EXTEND:
350 Op2 = GetPromotedInteger(Op2);
351 break;
352 default:
353 llvm_unreachable("Invalid atomic op extension")::llvm::llvm_unreachable_internal("Invalid atomic op extension"
, "llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp", 353
)
;
354 }
355
356 SDVTList VTs =
357 DAG.getVTList(Op2.getValueType(), N->getValueType(1), MVT::Other);
358 SDValue Res = DAG.getAtomicCmpSwap(
359 N->getOpcode(), SDLoc(N), N->getMemoryVT(), VTs, N->getChain(),
360 N->getBasePtr(), Op2, Op3, N->getMemOperand());
361 // Update the use to N with the newly created Res.
362 for (unsigned i = 1, NumResults = N->getNumValues(); i < NumResults; ++i)
363 ReplaceValueWith(SDValue(N, i), Res.getValue(i));
364 return Res;
365}
366
367SDValue DAGTypeLegalizer::PromoteIntRes_BITCAST(SDNode *N) {
368 SDValue InOp = N->getOperand(0);
369 EVT InVT = InOp.getValueType();
370 EVT NInVT = TLI.getTypeToTransformTo(*DAG.getContext(), InVT);
371 EVT OutVT = N->getValueType(0);
372 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
373 SDLoc dl(N);
374
375 switch (getTypeAction(InVT)) {
376 case TargetLowering::TypeLegal:
377 break;
378 case TargetLowering::TypePromoteInteger:
379 if (NOutVT.bitsEq(NInVT) && !NOutVT.isVector() && !NInVT.isVector())
380 // The input promotes to the same size. Convert the promoted value.
381 return DAG.getNode(ISD::BITCAST, dl, NOutVT, GetPromotedInteger(InOp));
382 break;
383 case TargetLowering::TypeSoftenFloat:
384 // Promote the integer operand by hand.
385 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, GetSoftenedFloat(InOp));
386 case TargetLowering::TypeSoftPromoteHalf:
387 // Promote the integer operand by hand.
388 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, GetSoftPromotedHalf(InOp));
389 case TargetLowering::TypePromoteFloat: {
390 // Convert the promoted float by hand.
391 if (!NOutVT.isVector())
392 return DAG.getNode(ISD::FP_TO_FP16, dl, NOutVT, GetPromotedFloat(InOp));
393 break;
394 }
395 case TargetLowering::TypeExpandInteger:
396 case TargetLowering::TypeExpandFloat:
397 break;
398 case TargetLowering::TypeScalarizeVector:
399 // Convert the element to an integer and promote it by hand.
400 if (!NOutVT.isVector())
401 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT,
402 BitConvertToInteger(GetScalarizedVector(InOp)));
403 break;
404 case TargetLowering::TypeScalarizeScalableVector:
405 report_fatal_error("Scalarization of scalable vectors is not supported.");
406 case TargetLowering::TypeSplitVector: {
407 if (!NOutVT.isVector()) {
408 // For example, i32 = BITCAST v2i16 on alpha. Convert the split
409 // pieces of the input into integers and reassemble in the final type.
410 SDValue Lo, Hi;
411 GetSplitVector(N->getOperand(0), Lo, Hi);
412 Lo = BitConvertToInteger(Lo);
413 Hi = BitConvertToInteger(Hi);
414
415 if (DAG.getDataLayout().isBigEndian())
416 std::swap(Lo, Hi);
417
418 InOp = DAG.getNode(ISD::ANY_EXTEND, dl,
419 EVT::getIntegerVT(*DAG.getContext(),
420 NOutVT.getSizeInBits()),
421 JoinIntegers(Lo, Hi));
422 return DAG.getNode(ISD::BITCAST, dl, NOutVT, InOp);
423 }
424 break;
425 }
426 case TargetLowering::TypeWidenVector:
427 // The input is widened to the same size. Convert to the widened value.
428 // Make sure that the outgoing value is not a vector, because this would
429 // make us bitcast between two vectors which are legalized in different ways.
430 if (NOutVT.bitsEq(NInVT) && !NOutVT.isVector()) {
431 SDValue Res =
432 DAG.getNode(ISD::BITCAST, dl, NOutVT, GetWidenedVector(InOp));
433
434 // For big endian targets we need to shift the casted value or the
435 // interesting bits will end up at the wrong place.
436 if (DAG.getDataLayout().isBigEndian()) {
437 unsigned ShiftAmt = NInVT.getSizeInBits() - InVT.getSizeInBits();
438 EVT ShiftAmtTy = TLI.getShiftAmountTy(NOutVT, DAG.getDataLayout());
439 assert(ShiftAmt < NOutVT.getSizeInBits() && "Too large shift amount!")(static_cast <bool> (ShiftAmt < NOutVT.getSizeInBits
() && "Too large shift amount!") ? void (0) : __assert_fail
("ShiftAmt < NOutVT.getSizeInBits() && \"Too large shift amount!\""
, "llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp", 439
, __extension__ __PRETTY_FUNCTION__))
;
440 Res = DAG.getNode(ISD::SRL, dl, NOutVT, Res,
441 DAG.getConstant(ShiftAmt, dl, ShiftAmtTy));
442 }
443 return Res;
444 }
445 // If the output type is also a vector and widening it to the same size
446 // as the widened input type would be a legal type, we can widen the bitcast
447 // and handle the promotion after.
448 if (NOutVT.isVector()) {
449 unsigned WidenInSize = NInVT.getSizeInBits();
450 unsigned OutSize = OutVT.getSizeInBits();
451 if (WidenInSize % OutSize == 0) {
452 unsigned Scale = WidenInSize / OutSize;
453 EVT WideOutVT = EVT::getVectorVT(*DAG.getContext(),
454 OutVT.getVectorElementType(),
455 OutVT.getVectorNumElements() * Scale);
456 if (isTypeLegal(WideOutVT)) {
457 InOp = DAG.getBitcast(WideOutVT, GetWidenedVector(InOp));
458 InOp = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, OutVT, InOp,
459 DAG.getVectorIdxConstant(0, dl));
460 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, InOp);
461 }
462 }
463 }
464 }
465
466 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT,
467 CreateStackStoreLoad(InOp, OutVT));
468}
469
470SDValue DAGTypeLegalizer::PromoteIntRes_FREEZE(SDNode *N) {
471 SDValue V = GetPromotedInteger(N->getOperand(0));
472 return DAG.getNode(ISD::FREEZE, SDLoc(N),
473 V.getValueType(), V);
474}
475
476SDValue DAGTypeLegalizer::PromoteIntRes_BSWAP(SDNode *N) {
477 SDValue Op = GetPromotedInteger(N->getOperand(0));
478 EVT OVT = N->getValueType(0);
479 EVT NVT = Op.getValueType();
480 SDLoc dl(N);
481
482 // If the larger BSWAP isn't supported by the target, try to expand now.
483 // If we expand later we'll end up with more operations since we lost the
484 // original type. We only do this for scalars since we have a shuffle
485 // based lowering for vectors in LegalizeVectorOps.
486 if (!OVT.isVector() &&
487 !TLI.isOperationLegalOrCustomOrPromote(ISD::BSWAP, NVT)) {
488 if (SDValue Res = TLI.expandBSWAP(N, DAG))
489 return DAG.getNode(ISD::ANY_EXTEND, dl, NVT, Res);
490 }
491
492 unsigned DiffBits = NVT.getScalarSizeInBits() - OVT.getScalarSizeInBits();
493 EVT ShiftVT = TLI.getShiftAmountTy(NVT, DAG.getDataLayout());
494 return DAG.getNode(ISD::SRL, dl, NVT, DAG.getNode(ISD::BSWAP, dl, NVT, Op),
495 DAG.getConstant(DiffBits, dl, ShiftVT));
496}
497
498SDValue DAGTypeLegalizer::PromoteIntRes_BITREVERSE(SDNode *N) {
499 SDValue Op = GetPromotedInteger(N->getOperand(0));
500 EVT OVT = N->getValueType(0);
501 EVT NVT = Op.getValueType();
502 SDLoc dl(N);
503
504 // If the larger BITREVERSE isn't supported by the target, try to expand now.
505 // If we expand later we'll end up with more operations since we lost the
506 // original type. We only do this for scalars since we have a shuffle
507 // based lowering for vectors in LegalizeVectorOps.
508 if (!OVT.isVector() && OVT.isSimple() &&
509 !TLI.isOperationLegalOrCustomOrPromote(ISD::BITREVERSE, NVT)) {
510 if (SDValue Res = TLI.expandBITREVERSE(N, DAG))
511 return DAG.getNode(ISD::ANY_EXTEND, dl, NVT, Res);
512 }
513
514 unsigned DiffBits = NVT.getScalarSizeInBits() - OVT.getScalarSizeInBits();
515 EVT ShiftVT = TLI.getShiftAmountTy(NVT, DAG.getDataLayout());
516 return DAG.getNode(ISD::SRL, dl, NVT,
517 DAG.getNode(ISD::BITREVERSE, dl, NVT, Op),
518 DAG.getConstant(DiffBits, dl, ShiftVT));
519}
520
521SDValue DAGTypeLegalizer::PromoteIntRes_BUILD_PAIR(SDNode *N) {
522 // The pair element type may be legal, or may not promote to the same type as
523 // the result, for example i14 = BUILD_PAIR (i7, i7). Handle all cases.
524 return DAG.getNode(ISD::ANY_EXTEND, SDLoc(N),
525 TLI.getTypeToTransformTo(*DAG.getContext(),
526 N->getValueType(0)), JoinIntegers(N->getOperand(0),
527 N->getOperand(1)));
528}
529
530SDValue DAGTypeLegalizer::PromoteIntRes_Constant(SDNode *N) {
531 EVT VT = N->getValueType(0);
532 // FIXME there is no actual debug info here
533 SDLoc dl(N);
534 // Zero extend things like i1, sign extend everything else. It shouldn't
535 // matter in theory which one we pick, but this tends to give better code?
536 unsigned Opc = VT.isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
537 SDValue Result = DAG.getNode(Opc, dl,
538 TLI.getTypeToTransformTo(*DAG.getContext(), VT),
539 SDValue(N, 0));
540 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold ext?")(static_cast <bool> (isa<ConstantSDNode>(Result) &&
"Didn't constant fold ext?") ? void (0) : __assert_fail ("isa<ConstantSDNode>(Result) && \"Didn't constant fold ext?\""
, "llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp", 540
, __extension__ __PRETTY_FUNCTION__))
;
541 return Result;
542}
543
544SDValue DAGTypeLegalizer::PromoteIntRes_CTLZ(SDNode *N) {
545 EVT OVT = N->getValueType(0);
546 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), OVT);
547 SDLoc dl(N);
548
549 // If the larger CTLZ isn't supported by the target, try to expand now.
550 // If we expand later we'll end up with more operations since we lost the
551 // original type.
552 if (!OVT.isVector() && TLI.isTypeLegal(NVT) &&
553 !TLI.isOperationLegalOrCustomOrPromote(ISD::CTLZ, NVT) &&
554 !TLI.isOperationLegalOrCustomOrPromote(ISD::CTLZ_ZERO_UNDEF, NVT)) {
555 if (SDValue Result = TLI.expandCTLZ(N, DAG)) {
556 Result = DAG.getNode(ISD::ANY_EXTEND, dl, NVT, Result);
557 return Result;
558 }
559 }
560
561 // Zero extend to the promoted type and do the count there.
562 SDValue Op = ZExtPromotedInteger(N->getOperand(0));
563 Op = DAG.getNode(N->getOpcode(), dl, NVT, Op);
564 // Subtract off the extra leading bits in the bigger type.
565 return DAG.getNode(
566 ISD::SUB, dl, NVT, Op,
567 DAG.getConstant(NVT.getScalarSizeInBits() - OVT.getScalarSizeInBits(), dl,
568 NVT));
569}
570
571SDValue DAGTypeLegalizer::PromoteIntRes_CTPOP_PARITY(SDNode *N) {
572 EVT OVT = N->getValueType(0);
573 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), OVT);
574
575 // If the larger CTPOP isn't supported by the target, try to expand now.
576 // If we expand later we'll end up with more operations since we lost the
577 // original type.
578 // TODO: Expand ISD::PARITY. Need to move ExpandPARITY from LegalizeDAG to
579 // TargetLowering.
580 if (N->getOpcode() == ISD::CTPOP && !OVT.isVector() && TLI.isTypeLegal(NVT) &&
581 !TLI.isOperationLegalOrCustomOrPromote(ISD::CTPOP, NVT)) {
582 if (SDValue Result = TLI.expandCTPOP(N, DAG)) {
583 Result = DAG.getNode(ISD::ANY_EXTEND, SDLoc(N), NVT, Result);
584 return Result;
585 }
586 }
587
588 // Zero extend to the promoted type and do the count or parity there.
589 SDValue Op = ZExtPromotedInteger(N->getOperand(0));
590 return DAG.getNode(N->getOpcode(), SDLoc(N), Op.getValueType(), Op);
591}
592
593SDValue DAGTypeLegalizer::PromoteIntRes_CTTZ(SDNode *N) {
594 SDValue Op = GetPromotedInteger(N->getOperand(0));
595 EVT OVT = N->getValueType(0);
596 EVT NVT = Op.getValueType();
597 SDLoc dl(N);
598
599 // If the larger CTTZ isn't supported by the target, try to expand now.
600 // If we expand later we'll end up with more operations since we lost the
601 // original type. Don't expand if we can use CTPOP or CTLZ expansion on the
602 // larger type.
603 if (!OVT.isVector() && TLI.isTypeLegal(NVT) &&
604 !TLI.isOperationLegalOrCustomOrPromote(ISD::CTTZ, NVT) &&
605 !TLI.isOperationLegalOrCustomOrPromote(ISD::CTTZ_ZERO_UNDEF, NVT) &&
606 !TLI.isOperationLegal(ISD::CTPOP, NVT) &&
607 !TLI.isOperationLegal(ISD::CTLZ, NVT)) {
608 if (SDValue Result = TLI.expandCTTZ(N, DAG)) {
609 Result = DAG.getNode(ISD::ANY_EXTEND, dl, NVT, Result);
610 return Result;
611 }
612 }
613
614 if (N->getOpcode() == ISD::CTTZ) {
615 // The count is the same in the promoted type except if the original
616 // value was zero. This can be handled by setting the bit just off
617 // the top of the original type.
618 auto TopBit = APInt::getOneBitSet(NVT.getScalarSizeInBits(),
619 OVT.getScalarSizeInBits());
620 Op = DAG.getNode(ISD::OR, dl, NVT, Op, DAG.getConstant(TopBit, dl, NVT));
621 }
622 return DAG.getNode(N->getOpcode(), dl, NVT, Op);
623}
624
625SDValue DAGTypeLegalizer::PromoteIntRes_EXTRACT_VECTOR_ELT(SDNode *N) {
626 SDLoc dl(N);
627 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
628
629 SDValue Op0 = N->getOperand(0);
630 SDValue Op1 = N->getOperand(1);
631
632 // If the input also needs to be promoted, do that first so we can get a
633 // get a good idea for the output type.
634 if (TLI.getTypeAction(*DAG.getContext(), Op0.getValueType())
635 == TargetLowering::TypePromoteInteger) {
636 SDValue In = GetPromotedInteger(Op0);
637
638 // If the new type is larger than NVT, use it. We probably won't need to
639 // promote it again.
640 EVT SVT = In.getValueType().getScalarType();
641 if (SVT.bitsGE(NVT)) {
642 SDValue Ext = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT, In, Op1);
643 return DAG.getAnyExtOrTrunc(Ext, dl, NVT);
644 }
645 }
646
647 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NVT, Op0, Op1);
648}
649
650SDValue DAGTypeLegalizer::PromoteIntRes_FP_TO_XINT(SDNode *N) {
651 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
652 unsigned NewOpc = N->getOpcode();
653 SDLoc dl(N);
654
655 // If we're promoting a UINT to a larger size and the larger FP_TO_UINT is
656 // not Legal, check to see if we can use FP_TO_SINT instead. (If both UINT
657 // and SINT conversions are Custom, there is no way to tell which is
658 // preferable. We choose SINT because that's the right thing on PPC.)
659 if (N->getOpcode() == ISD::FP_TO_UINT &&
660 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) &&
661 TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NVT))
662 NewOpc = ISD::FP_TO_SINT;
663
664 if (N->getOpcode() == ISD::STRICT_FP_TO_UINT &&
665 !TLI.isOperationLegal(ISD::STRICT_FP_TO_UINT, NVT) &&
666 TLI.isOperationLegalOrCustom(ISD::STRICT_FP_TO_SINT, NVT))
667 NewOpc = ISD::STRICT_FP_TO_SINT;
668
669 SDValue Res;
670 if (N->isStrictFPOpcode()) {
671 Res = DAG.getNode(NewOpc, dl, {NVT, MVT::Other},
672 {N->getOperand(0), N->getOperand(1)});
673 // Legalize the chain result - switch anything that used the old chain to
674 // use the new one.
675 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
676 } else
677 Res = DAG.getNode(NewOpc, dl, NVT, N->getOperand(0));
678
679 // Assert that the converted value fits in the original type. If it doesn't
680 // (eg: because the value being converted is too big), then the result of the
681 // original operation was undefined anyway, so the assert is still correct.
682 //
683 // NOTE: fp-to-uint to fp-to-sint promotion guarantees zero extend. For example:
684 // before legalization: fp-to-uint16, 65534. -> 0xfffe
685 // after legalization: fp-to-sint32, 65534. -> 0x0000fffe
686 return DAG.getNode((N->getOpcode() == ISD::FP_TO_UINT ||
687 N->getOpcode() == ISD::STRICT_FP_TO_UINT) ?
688 ISD::AssertZext : ISD::AssertSext, dl, NVT, Res,
689 DAG.getValueType(N->getValueType(0).getScalarType()));
690}
691
692SDValue DAGTypeLegalizer::PromoteIntRes_FP_TO_XINT_SAT(SDNode *N) {
693 // Promote the result type, while keeping the original width in Op1.
694 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
695 SDLoc dl(N);
696 return DAG.getNode(N->getOpcode(), dl, NVT, N->getOperand(0),
697 N->getOperand(1));
698}
699
700SDValue DAGTypeLegalizer::PromoteIntRes_FP_TO_FP16(SDNode *N) {
701 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
702 SDLoc dl(N);
703
704 return DAG.getNode(N->getOpcode(), dl, NVT, N->getOperand(0));
705}
706
707SDValue DAGTypeLegalizer::PromoteIntRes_FLT_ROUNDS(SDNode *N) {
708 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
709 SDLoc dl(N);
710
711 SDValue Res =
712 DAG.getNode(N->getOpcode(), dl, {NVT, MVT::Other}, N->getOperand(0));
713
714 // Legalize the chain result - switch anything that used the old chain to
715 // use the new one.
716 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
717 return Res;
718}
719
720SDValue DAGTypeLegalizer::PromoteIntRes_INT_EXTEND(SDNode *N) {
721 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
722 SDLoc dl(N);
723
724 if (getTypeAction(N->getOperand(0).getValueType())
725 == TargetLowering::TypePromoteInteger) {
726 SDValue Res = GetPromotedInteger(N->getOperand(0));
727 assert(Res.getValueType().bitsLE(NVT) && "Extension doesn't make sense!")(static_cast <bool> (Res.getValueType().bitsLE(NVT) &&
"Extension doesn't make sense!") ? void (0) : __assert_fail (
"Res.getValueType().bitsLE(NVT) && \"Extension doesn't make sense!\""
, "llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp", 727
, __extension__ __PRETTY_FUNCTION__))
;
728
729 // If the result and operand types are the same after promotion, simplify
730 // to an in-register extension.
731 if (NVT == Res.getValueType()) {
732 // The high bits are not guaranteed to be anything. Insert an extend.
733 if (N->getOpcode() == ISD::SIGN_EXTEND)
734 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Res,
735 DAG.getValueType(N->getOperand(0).getValueType()));
736 if (N->getOpcode() == ISD::ZERO_EXTEND)
737 return DAG.getZeroExtendInReg(Res, dl, N->getOperand(0).getValueType());
738 assert(N->getOpcode() == ISD::ANY_EXTEND && "Unknown integer extension!")(static_cast <bool> (N->getOpcode() == ISD::ANY_EXTEND
&& "Unknown integer extension!") ? void (0) : __assert_fail
("N->getOpcode() == ISD::ANY_EXTEND && \"Unknown integer extension!\""
, "llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp", 738
, __extension__ __PRETTY_FUNCTION__))
;
739 return Res;
740 }
741 }
742
743 // Otherwise, just extend the original operand all the way to the larger type.
744 return DAG.getNode(N->getOpcode(), dl, NVT, N->getOperand(0));
745}
746
747SDValue DAGTypeLegalizer::PromoteIntRes_LOAD(LoadSDNode *N) {
748 assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!")(static_cast <bool> (ISD::isUNINDEXEDLoad(N) &&
"Indexed load during type legalization!") ? void (0) : __assert_fail
("ISD::isUNINDEXEDLoad(N) && \"Indexed load during type legalization!\""
, "llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp", 748
, __extension__ __PRETTY_FUNCTION__))
;
749 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
750 ISD::LoadExtType ExtType =
751 ISD::isNON_EXTLoad(N) ? ISD::EXTLOAD : N->getExtensionType();
752 SDLoc dl(N);
753 SDValue Res = DAG.getExtLoad(ExtType, dl, NVT, N->getChain(), N->getBasePtr(),
754 N->getMemoryVT(), N->getMemOperand());
755
756 // Legalize the chain result - switch anything that used the old chain to
757 // use the new one.
758 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
759 return Res;
760}
761
762SDValue DAGTypeLegalizer::PromoteIntRes_MLOAD(MaskedLoadSDNode *N) {
763 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
764 SDValue ExtPassThru = GetPromotedInteger(N->getPassThru());
765
766 ISD::LoadExtType ExtType = N->getExtensionType();
767 if (ExtType == ISD::NON_EXTLOAD)
768 ExtType = ISD::EXTLOAD;
769
770 SDLoc dl(N);
771 SDValue Res = DAG.getMaskedLoad(NVT, dl, N->getChain(), N->getBasePtr(),
772 N->getOffset(), N->getMask(), ExtPassThru,
773 N->getMemoryVT(), N->getMemOperand(),
774 N->getAddressingMode(), ExtType,
775 N->isExpandingLoad());
776 // Legalize the chain result - switch anything that used the old chain to
777 // use the new one.
778 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
779 return Res;
780}
781
782SDValue DAGTypeLegalizer::PromoteIntRes_MGATHER(MaskedGatherSDNode *N) {
783 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
784 SDValue ExtPassThru = GetPromotedInteger(N->getPassThru());
785 assert(NVT == ExtPassThru.getValueType() &&(static_cast <bool> (NVT == ExtPassThru.getValueType() &&
"Gather result type and the passThru argument type should be the same"
) ? void (0) : __assert_fail ("NVT == ExtPassThru.getValueType() && \"Gather result type and the passThru argument type should be the same\""
, "llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp", 786
, __extension__ __PRETTY_FUNCTION__))
786 "Gather result type and the passThru argument type should be the same")(static_cast <bool> (NVT == ExtPassThru.getValueType() &&
"Gather result type and the passThru argument type should be the same"
) ? void (0) : __assert_fail ("NVT == ExtPassThru.getValueType() && \"Gather result type and the passThru argument type should be the same\""
, "llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp", 786
, __extension__ __PRETTY_FUNCTION__))
;
787
788 ISD::LoadExtType ExtType = N->getExtensionType();
789 if (ExtType == ISD::NON_EXTLOAD)
790 ExtType = ISD::EXTLOAD;
791
792 SDLoc dl(N);
793 SDValue Ops[] = {N->getChain(), ExtPassThru, N->getMask(), N->getBasePtr(),
794 N->getIndex(), N->getScale() };
795 SDValue Res = DAG.getMaskedGather(DAG.getVTList(NVT, MVT::Other),
796 N->getMemoryVT(), dl, Ops,
797 N->getMemOperand(), N->getIndexType(),
798 ExtType);
799 // Legalize the chain result - switch anything that used the old chain to
800 // use the new one.
801 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
802 return Res;
803}
804
805/// Promote the overflow flag of an overflowing arithmetic node.
806SDValue DAGTypeLegalizer::PromoteIntRes_Overflow(SDNode *N) {
807 // Change the return type of the boolean result while obeying
808 // getSetCCResultType.
809 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(1));
810 EVT VT = N->getValueType(0);
811 EVT SVT = getSetCCResultType(VT);
812 SDValue Ops[3] = { N->getOperand(0), N->getOperand(1) };
813 unsigned NumOps = N->getNumOperands();
814 assert(NumOps <= 3 && "Too many operands")(static_cast <bool> (NumOps <= 3 && "Too many operands"
) ? void (0) : __assert_fail ("NumOps <= 3 && \"Too many operands\""
, "llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp", 814
, __extension__ __PRETTY_FUNCTION__))
;
815 if (NumOps == 3)
816 Ops[2] = N->getOperand(2);
817
818 SDLoc dl(N);
819 SDValue Res = DAG.getNode(N->getOpcode(), dl, DAG.getVTList(VT, SVT),
820 makeArrayRef(Ops, NumOps));
821
822 // Modified the sum result - switch anything that used the old sum to use
823 // the new one.
824 ReplaceValueWith(SDValue(N, 0), Res);
825
826 // Convert to the expected type.
827 return DAG.getBoolExtOrTrunc(Res.getValue(1), dl, NVT, VT);
828}
829
830SDValue DAGTypeLegalizer::PromoteIntRes_ADDSUBSHLSAT(SDNode *N) {
831 // If the promoted type is legal, we can convert this to:
832 // 1. ANY_EXTEND iN to iM
833 // 2. SHL by M-N
834 // 3. [US][ADD|SUB|SHL]SAT
835 // 4. L/ASHR by M-N
836 // Else it is more efficient to convert this to a min and a max
837 // operation in the higher precision arithmetic.
838 SDLoc dl(N);
839 SDValue Op1 = N->getOperand(0);
840 SDValue Op2 = N->getOperand(1);
841 unsigned OldBits = Op1.getScalarValueSizeInBits();
842
843 unsigned Opcode = N->getOpcode();
844 bool IsShift = Opcode == ISD::USHLSAT || Opcode == ISD::SSHLSAT;
845
846 SDValue Op1Promoted, Op2Promoted;
847 if (IsShift) {
848 Op1Promoted = GetPromotedInteger(Op1);
849 Op2Promoted = ZExtPromotedInteger(Op2);
850 } else if (Opcode == ISD::UADDSAT || Opcode == ISD::USUBSAT) {
851 Op1Promoted = ZExtPromotedInteger(Op1);
852 Op2Promoted = ZExtPromotedInteger(Op2);
853 } else {
854 Op1Promoted = SExtPromotedInteger(Op1);
855 Op2Promoted = SExtPromotedInteger(Op2);
856 }
857 EVT PromotedType = Op1Promoted.getValueType();
858 unsigned NewBits = PromotedType.getScalarSizeInBits();
859
860 if (Opcode == ISD::UADDSAT) {
861 APInt MaxVal = APInt::getAllOnes(OldBits).zext(NewBits);
862 SDValue SatMax = DAG.getConstant(MaxVal, dl, PromotedType);
863 SDValue Add =
864 DAG.getNode(ISD::ADD, dl, PromotedType, Op1Promoted, Op2Promoted);
865 return DAG.getNode(ISD::UMIN, dl, PromotedType, Add, SatMax);
866 }
867
868 // USUBSAT can always be promoted as long as we have zero-extended the args.
869 if (Opcode == ISD::USUBSAT)
870 return DAG.getNode(ISD::USUBSAT, dl, PromotedType, Op1Promoted,
871 Op2Promoted);
872
873 // Shift cannot use a min/max expansion, we can't detect overflow if all of
874 // the bits have been shifted out.
875 if (IsShift || TLI.isOperationLegal(Opcode, PromotedType)) {
876 unsigned ShiftOp;
877 switch (Opcode) {
878 case ISD::SADDSAT:
879 case ISD::SSUBSAT:
880 case ISD::SSHLSAT:
881 ShiftOp = ISD::SRA;
882 break;
883 case ISD::USHLSAT:
884 ShiftOp = ISD::SRL;
885 break;
886 default:
887 llvm_unreachable("Expected opcode to be signed or unsigned saturation "::llvm::llvm_unreachable_internal("Expected opcode to be signed or unsigned saturation "
"addition, subtraction or left shift", "llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 888)
888 "addition, subtraction or left shift")::llvm::llvm_unreachable_internal("Expected opcode to be signed or unsigned saturation "
"addition, subtraction or left shift", "llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 888)
;
889 }
890
891 unsigned SHLAmount = NewBits - OldBits;
892 EVT SHVT = TLI.getShiftAmountTy(PromotedType, DAG.getDataLayout());
893 SDValue ShiftAmount = DAG.getConstant(SHLAmount, dl, SHVT);
894 Op1Promoted =
895 DAG.getNode(ISD::SHL, dl, PromotedType, Op1Promoted, ShiftAmount);
896 if (!IsShift)
897 Op2Promoted =
898 DAG.getNode(ISD::SHL, dl, PromotedType, Op2Promoted, ShiftAmount);
899
900 SDValue Result =
901 DAG.getNode(Opcode, dl, PromotedType, Op1Promoted, Op2Promoted);
902 return DAG.getNode(ShiftOp, dl, PromotedType, Result, ShiftAmount);
903 }
904
905 unsigned AddOp = Opcode == ISD::SADDSAT ? ISD::ADD : ISD::SUB;
906 APInt MinVal = APInt::getSignedMinValue(OldBits).sext(NewBits);
907 APInt MaxVal = APInt::getSignedMaxValue(OldBits).sext(NewBits);
908 SDValue SatMin = DAG.getConstant(MinVal, dl, PromotedType);
909 SDValue SatMax = DAG.getConstant(MaxVal, dl, PromotedType);
910 SDValue Result =
911 DAG.getNode(AddOp, dl, PromotedType, Op1Promoted, Op2Promoted);
912 Result = DAG.getNode(ISD::SMIN, dl, PromotedType, Result, SatMax);
913 Result = DAG.getNode(ISD::SMAX, dl, PromotedType, Result, SatMin);
914 return Result;
915}
916
917SDValue DAGTypeLegalizer::PromoteIntRes_MULFIX(SDNode *N) {
918 // Can just promote the operands then continue with operation.
919 SDLoc dl(N);
920 SDValue Op1Promoted, Op2Promoted;
921 bool Signed =
922 N->getOpcode() == ISD::SMULFIX || N->getOpcode() == ISD::SMULFIXSAT;
923 bool Saturating =
924 N->getOpcode() == ISD::SMULFIXSAT || N->getOpcode() == ISD::UMULFIXSAT;
925 if (Signed) {
926 Op1Promoted = SExtPromotedInteger(N->getOperand(0));
927 Op2Promoted = SExtPromotedInteger(N->getOperand(1));
928 } else {
929 Op1Promoted = ZExtPromotedInteger(N->getOperand(0));
930 Op2Promoted = ZExtPromotedInteger(N->getOperand(1));
931 }
932 EVT OldType = N->getOperand(0).getValueType();
933 EVT PromotedType = Op1Promoted.getValueType();
934 unsigned DiffSize =
935 PromotedType.getScalarSizeInBits() - OldType.getScalarSizeInBits();
936
937 if (Saturating) {
938 // Promoting the operand and result values changes the saturation width,
939 // which is extends the values that we clamp to on saturation. This could be
940 // resolved by shifting one of the operands the same amount, which would
941 // also shift the result we compare against, then shifting back.
942 EVT ShiftTy = TLI.getShiftAmountTy(PromotedType, DAG.getDataLayout());
943 Op1Promoted = DAG.getNode(ISD::SHL, dl, PromotedType, Op1Promoted,
944 DAG.getConstant(DiffSize, dl, ShiftTy));
945 SDValue Result = DAG.getNode(N->getOpcode(), dl, PromotedType, Op1Promoted,
946 Op2Promoted, N->getOperand(2));
947 unsigned ShiftOp = Signed ? ISD::SRA : ISD::SRL;
948 return DAG.getNode(ShiftOp, dl, PromotedType, Result,
949 DAG.getConstant(DiffSize, dl, ShiftTy));
950 }
951 return DAG.getNode(N->getOpcode(), dl, PromotedType, Op1Promoted, Op2Promoted,
952 N->getOperand(2));
953}
954
955static SDValue SaturateWidenedDIVFIX(SDValue V, SDLoc &dl,
956 unsigned SatW, bool Signed,
957 const TargetLowering &TLI,
958 SelectionDAG &DAG) {
959 EVT VT = V.getValueType();
960 unsigned VTW = VT.getScalarSizeInBits();
961
962 if (!Signed) {
963 // Saturate to the unsigned maximum by getting the minimum of V and the
964 // maximum.
965 return DAG.getNode(ISD::UMIN, dl, VT, V,
966 DAG.getConstant(APInt::getLowBitsSet(VTW, SatW),
967 dl, VT));
968 }
969
970 // Saturate to the signed maximum (the low SatW - 1 bits) by taking the
971 // signed minimum of it and V.
972 V = DAG.getNode(ISD::SMIN, dl, VT, V,
973 DAG.getConstant(APInt::getLowBitsSet(VTW, SatW - 1),
974 dl, VT));
975 // Saturate to the signed minimum (the high SatW + 1 bits) by taking the
976 // signed maximum of it and V.
977 V = DAG.getNode(ISD::SMAX, dl, VT, V,
978 DAG.getConstant(APInt::getHighBitsSet(VTW, VTW - SatW + 1),
979 dl, VT));
980 return V;
981}
982
983static SDValue earlyExpandDIVFIX(SDNode *N, SDValue LHS, SDValue RHS,
984 unsigned Scale, const TargetLowering &TLI,
985 SelectionDAG &DAG, unsigned SatW = 0) {
986 EVT VT = LHS.getValueType();
987 unsigned VTSize = VT.getScalarSizeInBits();
988 bool Signed = N->getOpcode() == ISD::SDIVFIX ||
989 N->getOpcode() == ISD::SDIVFIXSAT;
990 bool Saturating = N->getOpcode() == ISD::SDIVFIXSAT ||
991 N->getOpcode() == ISD::UDIVFIXSAT;
992
993 SDLoc dl(N);
994 // Widen the types by a factor of two. This is guaranteed to expand, since it
995 // will always have enough high bits in the LHS to shift into.
996 EVT WideVT = EVT::getIntegerVT(*DAG.getContext(), VTSize * 2);
997 if (VT.isVector())
998 WideVT = EVT::getVectorVT(*DAG.getContext(), WideVT,
999 VT.getVectorElementCount());
1000 if (Signed) {
1001 LHS = DAG.getSExtOrTrunc(LHS, dl, WideVT);
1002 RHS = DAG.getSExtOrTrunc(RHS, dl, WideVT);
1003 } else {
1004 LHS = DAG.getZExtOrTrunc(LHS, dl, WideVT);
1005 RHS = DAG.getZExtOrTrunc(RHS, dl, WideVT);
1006 }
1007
1008 SDValue Res = TLI.expandFixedPointDiv(N->getOpcode(), dl, LHS, RHS, Scale,
1009 DAG);
1010 assert(Res && "Expanding DIVFIX with wide type failed?")(static_cast <bool> (Res && "Expanding DIVFIX with wide type failed?"
) ? void (0) : __assert_fail ("Res && \"Expanding DIVFIX with wide type failed?\""
, "llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp", 1010
, __extension__ __PRETTY_FUNCTION__))
;
1011 if (Saturating) {
1012 // If the caller has told us to saturate at something less, use that width
1013 // instead of the type before doubling. However, it cannot be more than
1014 // what we just widened!
1015 assert(SatW <= VTSize &&(static_cast <bool> (SatW <= VTSize && "Tried to saturate to more than the original type?"
) ? void (0) : __assert_fail ("SatW <= VTSize && \"Tried to saturate to more than the original type?\""
, "llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp", 1016
, __extension__ __PRETTY_FUNCTION__))
1016 "Tried to saturate to more than the original type?")(static_cast <bool> (SatW <= VTSize && "Tried to saturate to more than the original type?"
) ? void (0) : __assert_fail ("SatW <= VTSize && \"Tried to saturate to more than the original type?\""
, "llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp", 1016
, __extension__ __PRETTY_FUNCTION__))
;
1017 Res = SaturateWidenedDIVFIX(Res, dl, SatW == 0 ? VTSize : SatW, Signed,
1018 TLI, DAG);
1019 }
1020 return DAG.getZExtOrTrunc(Res, dl, VT);
1021}
1022
1023SDValue DAGTypeLegalizer::PromoteIntRes_DIVFIX(SDNode *N) {
1024 SDLoc dl(N);
1025 SDValue Op1Promoted, Op2Promoted;
1026 bool Signed = N->getOpcode() == ISD::SDIVFIX ||
1027 N->getOpcode() == ISD::SDIVFIXSAT;
1028 bool Saturating = N->getOpcode() == ISD::SDIVFIXSAT ||
1029 N->getOpcode() == ISD::UDIVFIXSAT;
1030 if (Signed) {
1031 Op1Promoted = SExtPromotedInteger(N->getOperand(0));
1032 Op2Promoted = SExtPromotedInteger(N->getOperand(1));
1033 } else {
1034 Op1Promoted = ZExtPromotedInteger(N->getOperand(0));
1035 Op2Promoted = ZExtPromotedInteger(N->getOperand(1));
1036 }
1037 EVT PromotedType = Op1Promoted.getValueType();
1038 unsigned Scale = N->getConstantOperandVal(2);
1039
1040 // If the type is already legal and the operation is legal in that type, we
1041 // should not early expand.
1042 if (TLI.isTypeLegal(PromotedType)) {
1043 TargetLowering::LegalizeAction Action =
1044 TLI.getFixedPointOperationAction(N->getOpcode(), PromotedType, Scale);
1045 if (Action == TargetLowering::Legal || Action == TargetLowering::Custom) {
1046 EVT ShiftTy = TLI.getShiftAmountTy(PromotedType, DAG.getDataLayout());
1047 unsigned Diff = PromotedType.getScalarSizeInBits() -
1048 N->getValueType(0).getScalarSizeInBits();
1049 if (Saturating)
1050 Op1Promoted = DAG.getNode(ISD::SHL, dl, PromotedType, Op1Promoted,
1051 DAG.getConstant(Diff, dl, ShiftTy));
1052 SDValue Res = DAG.getNode(N->getOpcode(), dl, PromotedType, Op1Promoted,
1053 Op2Promoted, N->getOperand(2));
1054 if (Saturating)
1055 Res = DAG.getNode(Signed ? ISD::SRA : ISD::SRL, dl, PromotedType, Res,
1056 DAG.getConstant(Diff, dl, ShiftTy));
1057 return Res;
1058 }
1059 }
1060
1061 // See if we can perform the division in this type without expanding.
1062 if (SDValue Res = TLI.expandFixedPointDiv(N->getOpcode(), dl, Op1Promoted,
1063 Op2Promoted, Scale, DAG)) {
1064 if (Saturating)
1065 Res = SaturateWidenedDIVFIX(Res, dl,
1066 N->getValueType(0).getScalarSizeInBits(),
1067 Signed, TLI, DAG);
1068 return Res;
1069 }
1070 // If we cannot, expand it to twice the type width. If we are saturating, give
1071 // it the original width as a saturating width so we don't need to emit
1072 // two saturations.
1073 return earlyExpandDIVFIX(N, Op1Promoted, Op2Promoted, Scale, TLI, DAG,
1074 N->getValueType(0).getScalarSizeInBits());
1075}
1076
1077SDValue DAGTypeLegalizer::PromoteIntRes_SADDSUBO(SDNode *N, unsigned ResNo) {
1078 if (ResNo == 1)
1079 return PromoteIntRes_Overflow(N);
1080
1081 // The operation overflowed iff the result in the larger type is not the
1082 // sign extension of its truncation to the original type.
1083 SDValue LHS = SExtPromotedInteger(N->getOperand(0));
1084 SDValue RHS = SExtPromotedInteger(N->getOperand(1));
1085 EVT OVT = N->getOperand(0).getValueType();
1086 EVT NVT = LHS.getValueType();
1087 SDLoc dl(N);
1088
1089 // Do the arithmetic in the larger type.
1090 unsigned Opcode = N->getOpcode() == ISD::SADDO ? ISD::ADD : ISD::SUB;
1091 SDValue Res = DAG.getNode(Opcode, dl, NVT, LHS, RHS);
1092
1093 // Calculate the overflow flag: sign extend the arithmetic result from
1094 // the original type.
1095 SDValue Ofl = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Res,
1096 DAG.getValueType(OVT));
1097 // Overflowed if and only if this is not equal to Res.
1098 Ofl = DAG.getSetCC(dl, N->getValueType(1), Ofl, Res, ISD::SETNE);
1099
1100 // Use the calculated overflow everywhere.
1101 ReplaceValueWith(SDValue(N, 1), Ofl);
1102
1103 return Res;
1104}
1105
1106SDValue DAGTypeLegalizer::PromoteIntRes_Select(SDNode *N) {
1107 SDValue Mask = N->getOperand(0);
1108
1109 SDValue LHS = GetPromotedInteger(N->getOperand(1));
1110 SDValue RHS = GetPromotedInteger(N->getOperand(2));
1111
1112 unsigned Opcode = N->getOpcode();
1113 return Opcode == ISD::VP_SELECT
1114 ? DAG.getNode(Opcode, SDLoc(N), LHS.getValueType(), Mask, LHS, RHS,
1115 N->getOperand(3))
1116 : DAG.getNode(Opcode, SDLoc(N), LHS.getValueType(), Mask, LHS,
1117 RHS);
1118}
1119
1120SDValue DAGTypeLegalizer::PromoteIntRes_SELECT_CC(SDNode *N) {
1121 SDValue LHS = GetPromotedInteger(N->getOperand(2));
1122 SDValue RHS = GetPromotedInteger(N->getOperand(3));
1123 return DAG.getNode(ISD::SELECT_CC, SDLoc(N),
1124 LHS.getValueType(), N->getOperand(0),
1125 N->getOperand(1), LHS, RHS, N->getOperand(4));
1126}
1127
1128SDValue DAGTypeLegalizer::PromoteIntRes_SETCC(SDNode *N) {
1129 unsigned OpNo = N->isStrictFPOpcode() ? 1 : 0;
1130 EVT InVT = N->getOperand(OpNo).getValueType();
1131 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1132
1133 EVT SVT = getSetCCResultType(InVT);
1134
1135 // If we got back a type that needs to be promoted, this likely means the
1136 // the input type also needs to be promoted. So get the promoted type for
1137 // the input and try the query again.
1138 if (getTypeAction(SVT) == TargetLowering::TypePromoteInteger) {
1139 if (getTypeAction(InVT) == TargetLowering::TypePromoteInteger) {
1140 InVT = TLI.getTypeToTransformTo(*DAG.getContext(), InVT);
1141 SVT = getSetCCResultType(InVT);
1142 } else {
1143 // Input type isn't promoted, just use the default promoted type.
1144 SVT = NVT;
1145 }
1146 }
1147
1148 SDLoc dl(N);
1149 assert(SVT.isVector() == N->getOperand(OpNo).getValueType().isVector() &&(static_cast <bool> (SVT.isVector() == N->getOperand
(OpNo).getValueType().isVector() && "Vector compare must return a vector result!"
) ? void (0) : __assert_fail ("SVT.isVector() == N->getOperand(OpNo).getValueType().isVector() && \"Vector compare must return a vector result!\""
, "llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp", 1150
, __extension__ __PRETTY_FUNCTION__))
1150 "Vector compare must return a vector result!")(static_cast <bool> (SVT.isVector() == N->getOperand
(OpNo).getValueType().isVector() && "Vector compare must return a vector result!"
) ? void (0) : __assert_fail ("SVT.isVector() == N->getOperand(OpNo).getValueType().isVector() && \"Vector compare must return a vector result!\""
, "llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp", 1150
, __extension__ __PRETTY_FUNCTION__))
;
1151
1152 // Get the SETCC result using the canonical SETCC type.
1153 SDValue SetCC;
1154 if (N->isStrictFPOpcode()) {
1155 EVT VTs[] = {SVT, MVT::Other};
1156 SDValue Opers[] = {N->getOperand(0), N->getOperand(1),
1157 N->getOperand(2), N->getOperand(3)};
1158 SetCC = DAG.getNode(N->getOpcode(), dl, VTs, Opers);
1159 // Legalize the chain result - switch anything that used the old chain to
1160 // use the new one.
1161 ReplaceValueWith(SDValue(N, 1), SetCC.getValue(1));
1162 } else
1163 SetCC = DAG.getNode(N->getOpcode(), dl, SVT, N->getOperand(0),
1164 N->getOperand(1), N->getOperand(2));
1165
1166 // Convert to the expected type.
1167 return DAG.getSExtOrTrunc(SetCC, dl, NVT);
1168}
1169
1170SDValue DAGTypeLegalizer::PromoteIntRes_SHL(SDNode *N) {
1171 SDValue LHS = GetPromotedInteger(N->getOperand(0));
1172 SDValue RHS = N->getOperand(1);
1173 if (getTypeAction(RHS.getValueType()) == TargetLowering::TypePromoteInteger)
1174 RHS = ZExtPromotedInteger(RHS);
1175 if (N->getOpcode() != ISD::VP_SHL)
1176 return DAG.getNode(N->getOpcode(), SDLoc(N), LHS.getValueType(), LHS, RHS);
1177 return DAG.getNode(N->getOpcode(), SDLoc(N), LHS.getValueType(), LHS, RHS,
1178 N->getOperand(2), N->getOperand(3));
1179}
1180
1181SDValue DAGTypeLegalizer::PromoteIntRes_SIGN_EXTEND_INREG(SDNode *N) {
1182 SDValue Op = GetPromotedInteger(N->getOperand(0));
1183 return DAG.getNode(ISD::SIGN_EXTEND_INREG, SDLoc(N),
1184 Op.getValueType(), Op, N->getOperand(1));
1185}
1186
1187SDValue DAGTypeLegalizer::PromoteIntRes_SimpleIntBinOp(SDNode *N) {
1188 // The input may have strange things in the top bits of the registers, but
1189 // these operations don't care. They may have weird bits going out, but
1190 // that too is okay if they are integer operations.
1191 SDValue LHS = GetPromotedInteger(N->getOperand(0));
1192 SDValue RHS = GetPromotedInteger(N->getOperand(1));
1193 if (N->getNumOperands() == 2)
1194 return DAG.getNode(N->getOpcode(), SDLoc(N), LHS.getValueType(), LHS, RHS);
1195 assert(N->getNumOperands() == 4 && "Unexpected number of operands!")(static_cast <bool> (N->getNumOperands() == 4 &&
"Unexpected number of operands!") ? void (0) : __assert_fail
("N->getNumOperands() == 4 && \"Unexpected number of operands!\""
, "llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp", 1195
, __extension__ __PRETTY_FUNCTION__))
;
1196 assert(N->isVPOpcode() && "Expected VP opcode")(static_cast <bool> (N->isVPOpcode() && "Expected VP opcode"
) ? void (0) : __assert_fail ("N->isVPOpcode() && \"Expected VP opcode\""
, "llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp", 1196
, __extension__ __PRETTY_FUNCTION__))
;
1197 return DAG.getNode(N->getOpcode(), SDLoc(N), LHS.getValueType(), LHS, RHS,
1198 N->getOperand(2), N->getOperand(3));
1199}
1200
1201SDValue DAGTypeLegalizer::PromoteIntRes_SExtIntBinOp(SDNode *N) {
1202 // Sign extend the input.
1203 SDValue LHS = SExtPromotedInteger(N->getOperand(0));
1204 SDValue RHS = SExtPromotedInteger(N->getOperand(1));
1205 if (N->getNumOperands() == 2)
1206 return DAG.getNode(N->getOpcode(), SDLoc(N), LHS.getValueType(), LHS, RHS);
1207 assert(N->getNumOperands() == 4 && "Unexpected number of operands!")(static_cast <bool> (N->getNumOperands() == 4 &&
"Unexpected number of operands!") ? void (0) : __assert_fail
("N->getNumOperands() == 4 && \"Unexpected number of operands!\""
, "llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp", 1207
, __extension__ __PRETTY_FUNCTION__))
;
1208 assert(N->isVPOpcode() && "Expected VP opcode")(static_cast <bool> (N->isVPOpcode() && "Expected VP opcode"
) ? void (0) : __assert_fail ("N->isVPOpcode() && \"Expected VP opcode\""
, "llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp", 1208
, __extension__ __PRETTY_FUNCTION__))
;
1209 return DAG.getNode(N->getOpcode(), SDLoc(N), LHS.getValueType(), LHS, RHS,
1210 N->getOperand(2), N->getOperand(3));
1211}
1212
1213SDValue DAGTypeLegalizer::PromoteIntRes_ZExtIntBinOp(SDNode *N) {
1214 // Zero extend the input.
1215 SDValue LHS = ZExtPromotedInteger(N->getOperand(0));
1216 SDValue RHS = ZExtPromotedInteger(N->getOperand(1));
1217 if (N->getNumOperands() == 2)
1218 return DAG.getNode(N->getOpcode(), SDLoc(N), LHS.getValueType(), LHS, RHS);
1219 assert(N->getNumOperands() == 4 && "Unexpected number of operands!")(static_cast <bool> (N->getNumOperands() == 4 &&
"Unexpected number of operands!") ? void (0) : __assert_fail
("N->getNumOperands() == 4 && \"Unexpected number of operands!\""
, "llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp", 1219
, __extension__ __PRETTY_FUNCTION__))
;
1220 assert(N->isVPOpcode() && "Expected VP opcode")(static_cast <bool> (N->isVPOpcode() && "Expected VP opcode"
) ? void (0) : __assert_fail ("N->isVPOpcode() && \"Expected VP opcode\""
, "llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp", 1220
, __extension__ __PRETTY_FUNCTION__))
;
1221 return DAG.getNode(N->getOpcode(), SDLoc(N), LHS.getValueType(), LHS, RHS,
1222 N->getOperand(2), N->getOperand(3));
1223}
1224
1225SDValue DAGTypeLegalizer::PromoteIntRes_UMINUMAX(SDNode *N) {
1226 // It doesn't matter if we sign extend or zero extend in the inputs. So do
1227 // whatever is best for the target.
1228 SDValue LHS = SExtOrZExtPromotedInteger(N->getOperand(0));
1229 SDValue RHS = SExtOrZExtPromotedInteger(N->getOperand(1));
1230 return DAG.getNode(N->getOpcode(), SDLoc(N),
1231 LHS.getValueType(), LHS, RHS);
1232}
1233
1234SDValue DAGTypeLegalizer::PromoteIntRes_SRA(SDNode *N) {
1235 // The input value must be properly sign extended.
1236 SDValue LHS = SExtPromotedInteger(N->getOperand(0));
1237 SDValue RHS = N->getOperand(1);
1238 if (getTypeAction(RHS.getValueType()) == TargetLowering::TypePromoteInteger)
1239 RHS = ZExtPromotedInteger(RHS);
1240 if (N->getOpcode() != ISD::VP_ASHR)
1241 return DAG.getNode(N->getOpcode(), SDLoc(N), LHS.getValueType(), LHS, RHS);
1242 return DAG.getNode(N->getOpcode(), SDLoc(N), LHS.getValueType(), LHS, RHS,
1243 N->getOperand(2), N->getOperand(3));
1244}
1245
1246SDValue DAGTypeLegalizer::PromoteIntRes_SRL(SDNode *N) {
1247 // The input value must be properly zero extended.
1248 SDValue LHS = ZExtPromotedInteger(N->getOperand(0));
1249 SDValue RHS = N->getOperand(1);
1250 if (getTypeAction(RHS.getValueType()) == TargetLowering::TypePromoteInteger)
1251 RHS = ZExtPromotedInteger(RHS);
1252 if (N->getOpcode() != ISD::VP_LSHR)
1253 return DAG.getNode(N->getOpcode(), SDLoc(N), LHS.getValueType(), LHS, RHS);
1254 return DAG.getNode(N->getOpcode(), SDLoc(N), LHS.getValueType(), LHS, RHS,
1255 N->getOperand(2), N->getOperand(3));
1256}
1257
1258SDValue DAGTypeLegalizer::PromoteIntRes_Rotate(SDNode *N) {
1259 // Lower the rotate to shifts and ORs which can be promoted.
1260 SDValue Res = TLI.expandROT(N, true /*AllowVectorOps*/, DAG);
1261 ReplaceValueWith(SDValue(N, 0), Res);
1262 return SDValue();
1263}
1264
1265SDValue DAGTypeLegalizer::PromoteIntRes_FunnelShift(SDNode *N) {
1266 SDValue Hi = GetPromotedInteger(N->getOperand(0));
1267 SDValue Lo = GetPromotedInteger(N->getOperand(1));
1268 SDValue Amt = GetPromotedInteger(N->getOperand(2));
1269
1270 SDLoc DL(N);
1271 EVT OldVT = N->getOperand(0).getValueType();
1272 EVT VT = Lo.getValueType();
1273 unsigned Opcode = N->getOpcode();
1274 bool IsFSHR = Opcode == ISD::FSHR;
1275 unsigned OldBits = OldVT.getScalarSizeInBits();
1276 unsigned NewBits = VT.getScalarSizeInBits();
1277
1278 // Amount has to be interpreted modulo the old bit width.
1279 Amt = DAG.getNode(ISD::UREM, DL, VT, Amt, DAG.getConstant(OldBits, DL, VT));
1280
1281 // If the promoted type is twice the size (or more), then we use the
1282 // traditional funnel 'double' shift codegen. This isn't necessary if the
1283 // shift amount is constant.
1284 // fshl(x,y,z) -> (((aext(x) << bw) | zext(y)) << (z % bw)) >> bw.
1285 // fshr(x,y,z) -> (((aext(x) << bw) | zext(y)) >> (z % bw)).
1286 if (NewBits >= (2 * OldBits) && !isa<ConstantSDNode>(Amt) &&
1287 !TLI.isOperationLegalOrCustom(Opcode, VT)) {
1288 SDValue HiShift = DAG.getConstant(OldBits, DL, VT);
1289 Hi = DAG.getNode(ISD::SHL, DL, VT, Hi, HiShift);
1290 Lo = DAG.getZeroExtendInReg(Lo, DL, OldVT);
1291 SDValue Res = DAG.getNode(ISD::OR, DL, VT, Hi, Lo);
1292 Res = DAG.getNode(IsFSHR ? ISD::SRL : ISD::SHL, DL, VT, Res, Amt);
1293 if (!IsFSHR)
1294 Res = DAG.getNode(ISD::SRL, DL, VT, Res, HiShift);
1295 return Res;
1296 }
1297
1298 // Shift Lo up to occupy the upper bits of the promoted type.
1299 SDValue ShiftOffset = DAG.getConstant(NewBits - OldBits, DL, VT);
1300 Lo = DAG.getNode(ISD::SHL, DL, VT, Lo, ShiftOffset);
1301
1302 // Increase Amount to shift the result into the lower bits of the promoted
1303 // type.
1304 if (IsFSHR)
1305 Amt = DAG.getNode(ISD::ADD, DL, VT, Amt, ShiftOffset);
1306
1307 return DAG.getNode(Opcode, DL, VT, Hi, Lo, Amt);
1308}
1309
1310SDValue DAGTypeLegalizer::PromoteIntRes_TRUNCATE(SDNode *N) {
1311 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1312 SDValue Res;
1313 SDValue InOp = N->getOperand(0);
1314 SDLoc dl(N);
1315
1316 switch (getTypeAction(InOp.getValueType())) {
1317 default: llvm_unreachable("Unknown type action!")::llvm::llvm_unreachable_internal("Unknown type action!", "llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 1317)
;
1318 case TargetLowering::TypeLegal:
1319 case TargetLowering::TypeExpandInteger:
1320 Res = InOp;
1321 break;
1322 case TargetLowering::TypePromoteInteger:
1323 Res = GetPromotedInteger(InOp);
1324 break;
1325 case TargetLowering::TypeSplitVector: {
1326 EVT InVT = InOp.getValueType();
1327 assert(InVT.isVector() && "Cannot split scalar types")(static_cast <bool> (InVT.isVector() && "Cannot split scalar types"
) ? void (0) : __assert_fail ("InVT.isVector() && \"Cannot split scalar types\""
, "llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp", 1327
, __extension__ __PRETTY_FUNCTION__))
;
1328 ElementCount NumElts = InVT.getVectorElementCount();
1329 assert(NumElts == NVT.getVectorElementCount() &&(static_cast <bool> (NumElts == NVT.getVectorElementCount
() && "Dst and Src must have the same number of elements"
) ? void (0) : __assert_fail ("NumElts == NVT.getVectorElementCount() && \"Dst and Src must have the same number of elements\""
, "llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp", 1330
, __extension__ __PRETTY_FUNCTION__))
1330 "Dst and Src must have the same number of elements")(static_cast <bool> (NumElts == NVT.getVectorElementCount
() && "Dst and Src must have the same number of elements"
) ? void (0) : __assert_fail ("NumElts == NVT.getVectorElementCount() && \"Dst and Src must have the same number of elements\""
, "llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp", 1330
, __extension__ __PRETTY_FUNCTION__))
;
1331 assert(isPowerOf2_32(NumElts.getKnownMinValue()) &&(static_cast <bool> (isPowerOf2_32(NumElts.getKnownMinValue
()) && "Promoted vector type must be a power of two")
? void (0) : __assert_fail ("isPowerOf2_32(NumElts.getKnownMinValue()) && \"Promoted vector type must be a power of two\""
, "llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp", 1332
, __extension__ __PRETTY_FUNCTION__))
1332 "Promoted vector type must be a power of two")(static_cast <bool> (isPowerOf2_32(NumElts.getKnownMinValue
()) && "Promoted vector type must be a power of two")
? void (0) : __assert_fail ("isPowerOf2_32(NumElts.getKnownMinValue()) && \"Promoted vector type must be a power of two\""
, "llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp", 1332
, __extension__ __PRETTY_FUNCTION__))
;
1333
1334 SDValue EOp1, EOp2;
1335 GetSplitVector(InOp, EOp1, EOp2);
1336
1337 EVT HalfNVT = EVT::getVectorVT(*DAG.getContext(), NVT.getScalarType(),
1338 NumElts.divideCoefficientBy(2));
1339 EOp1 = DAG.getNode(ISD::TRUNCATE, dl, HalfNVT, EOp1);
1340 EOp2 = DAG.getNode(ISD::TRUNCATE, dl, HalfNVT, EOp2);
1341
1342 return DAG.getNode(ISD::CONCAT_VECTORS, dl, NVT, EOp1, EOp2);
1343 }
1344 case TargetLowering::TypeWidenVector: {
1345 SDValue WideInOp = GetWidenedVector(InOp);
1346
1347 // Truncate widened InOp.
1348 unsigned NumElem = WideInOp.getValueType().getVectorNumElements();
1349 EVT TruncVT = EVT::getVectorVT(*DAG.getContext(),
1350 N->getValueType(0).getScalarType(), NumElem);
1351 SDValue WideTrunc = DAG.getNode(ISD::TRUNCATE, dl, TruncVT, WideInOp);
1352
1353 // Zero extend so that the elements are of same type as those of NVT
1354 EVT ExtVT = EVT::getVectorVT(*DAG.getContext(), NVT.getVectorElementType(),
1355 NumElem);
1356 SDValue WideExt = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVT, WideTrunc);
1357
1358 // Extract the low NVT subvector.
1359 SDValue ZeroIdx = DAG.getVectorIdxConstant(0, dl);
1360 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NVT, WideExt, ZeroIdx);
1361 }
1362 }
1363
1364 // Truncate to NVT instead of VT
1365 return DAG.getNode(ISD::TRUNCATE, dl, NVT, Res);
1366}
1367
1368SDValue DAGTypeLegalizer::PromoteIntRes_UADDSUBO(SDNode *N, unsigned ResNo) {
1369 if (ResNo == 1)
1370 return PromoteIntRes_Overflow(N);
1371
1372 // The operation overflowed iff the result in the larger type is not the
1373 // zero extension of its truncation to the original type.
1374 SDValue LHS = ZExtPromotedInteger(N->getOperand(0));
1375 SDValue RHS = ZExtPromotedInteger(N->getOperand(1));
1376 EVT OVT = N->getOperand(0).getValueType();
1377 EVT NVT = LHS.getValueType();
1378 SDLoc dl(N);
1379
1380 // Do the arithmetic in the larger type.
1381 unsigned Opcode = N->getOpcode() == ISD::UADDO ? ISD::ADD : ISD::SUB;
1382 SDValue Res = DAG.getNode(Opcode, dl, NVT, LHS, RHS);
1383
1384 // Calculate the overflow flag: zero extend the arithmetic result from
1385 // the original type.
1386 SDValue Ofl = DAG.getZeroExtendInReg(Res, dl, OVT);
1387 // Overflowed if and only if this is not equal to Res.
1388 Ofl = DAG.getSetCC(dl, N->getValueType(1), Ofl, Res, ISD::SETNE);
1389
1390 // Use the calculated overflow everywhere.
1391 ReplaceValueWith(SDValue(N, 1), Ofl);
1392
1393 return Res;
1394}
1395
1396// Handle promotion for the ADDE/SUBE/ADDCARRY/SUBCARRY nodes. Notice that
1397// the third operand of ADDE/SUBE nodes is carry flag, which differs from
1398// the ADDCARRY/SUBCARRY nodes in that the third operand is carry Boolean.
1399SDValue DAGTypeLegalizer::PromoteIntRes_ADDSUBCARRY(SDNode *N, unsigned ResNo) {
1400 if (ResNo == 1)
1401 return PromoteIntRes_Overflow(N);
1402
1403 // We need to sign-extend the operands so the carry value computed by the
1404 // wide operation will be equivalent to the carry value computed by the
1405 // narrow operation.
1406 // An ADDCARRY can generate carry only if any of the operands has its
1407 // most significant bit set. Sign extension propagates the most significant
1408 // bit into the higher bits which means the extra bit that the narrow
1409 // addition would need (i.e. the carry) will be propagated through the higher
1410 // bits of the wide addition.
1411 // A SUBCARRY can generate borrow only if LHS < RHS and this property will be
1412 // preserved by sign extension.
1413 SDValue LHS = SExtPromotedInteger(N->getOperand(0));
1414 SDValue RHS = SExtPromotedInteger(N->getOperand(1));
1415
1416 EVT ValueVTs[] = {LHS.getValueType(), N->getValueType(1)};
1417
1418 // Do the arithmetic in the wide type.
1419 SDValue Res = DAG.getNode(N->getOpcode(), SDLoc(N), DAG.getVTList(ValueVTs),
1420 LHS, RHS, N->getOperand(2));
1421
1422 // Update the users of the original carry/borrow value.
1423 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
1424
1425 return SDValue(Res.getNode(), 0);
1426}
1427
1428SDValue DAGTypeLegalizer::PromoteIntRes_SADDSUBO_CARRY(SDNode *N,
1429 unsigned ResNo) {
1430 assert(ResNo == 1 && "Don't know how to promote other results yet.")(static_cast <bool> (ResNo == 1 && "Don't know how to promote other results yet."
) ? void (0) : __assert_fail ("ResNo == 1 && \"Don't know how to promote other results yet.\""
, "llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp", 1430
, __extension__ __PRETTY_FUNCTION__))
;
1431 return PromoteIntRes_Overflow(N);
1432}
1433
1434SDValue DAGTypeLegalizer::PromoteIntRes_ABS(SDNode *N) {
1435 SDValue Op0 = SExtPromotedInteger(N->getOperand(0));
1436 return DAG.getNode(ISD::ABS, SDLoc(N), Op0.getValueType(), Op0);
1437}
1438
1439SDValue DAGTypeLegalizer::PromoteIntRes_XMULO(SDNode *N, unsigned ResNo) {
1440 // Promote the overflow bit trivially.
1441 if (ResNo == 1)
1442 return PromoteIntRes_Overflow(N);
1443
1444 SDValue LHS = N->getOperand(0), RHS = N->getOperand(1);
1445 SDLoc DL(N);
1446 EVT SmallVT = LHS.getValueType();
1447
1448 // To determine if the result overflowed in a larger type, we extend the
1449 // input to the larger type, do the multiply (checking if it overflows),
1450 // then also check the high bits of the result to see if overflow happened
1451 // there.
1452 if (N->getOpcode() == ISD::SMULO) {
1453 LHS = SExtPromotedInteger(LHS);
1454 RHS = SExtPromotedInteger(RHS);
1455 } else {
1456 LHS = ZExtPromotedInteger(LHS);
1457 RHS = ZExtPromotedInteger(RHS);
1458 }
1459 SDVTList VTs = DAG.getVTList(LHS.getValueType(), N->getValueType(1));
1460 SDValue Mul = DAG.getNode(N->getOpcode(), DL, VTs, LHS, RHS);
1461
1462 // Overflow occurred if it occurred in the larger type, or if the high part
1463 // of the result does not zero/sign-extend the low part. Check this second
1464 // possibility first.
1465 SDValue Overflow;
1466 if (N->getOpcode() == ISD::UMULO) {
1467 // Unsigned overflow occurred if the high part is non-zero.
1468 unsigned Shift = SmallVT.getScalarSizeInBits();
1469 EVT ShiftTy = TLI.getShiftAmountTy(Mul.getValueType(), DAG.getDataLayout());
1470 SDValue Hi = DAG.getNode(ISD::SRL, DL, Mul.getValueType(), Mul,
1471 DAG.getConstant(Shift, DL, ShiftTy));
1472 Overflow = DAG.getSetCC(DL, N->getValueType(1), Hi,
1473 DAG.getConstant(0, DL, Hi.getValueType()),
1474 ISD::SETNE);
1475 } else {
1476 // Signed overflow occurred if the high part does not sign extend the low.
1477 SDValue SExt = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, Mul.getValueType(),
1478 Mul, DAG.getValueType(SmallVT));
1479 Overflow = DAG.getSetCC(DL, N->getValueType(1), SExt, Mul, ISD::SETNE);
1480 }
1481
1482 // The only other way for overflow to occur is if the multiplication in the
1483 // larger type itself overflowed.
1484 Overflow = DAG.getNode(ISD::OR, DL, N->getValueType(1), Overflow,
1485 SDValue(Mul.getNode(), 1));
1486
1487 // Use the calculated overflow everywhere.
1488 ReplaceValueWith(SDValue(N, 1), Overflow);
1489 return Mul;
1490}
1491
1492SDValue DAGTypeLegalizer::PromoteIntRes_UNDEF(SDNode *N) {
1493 return DAG.getUNDEF(TLI.getTypeToTransformTo(*DAG.getContext(),
1494 N->getValueType(0)));
1495}
1496
1497SDValue DAGTypeLegalizer::PromoteIntRes_VSCALE(SDNode *N) {
1498 EVT VT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1499
1500 APInt MulImm = cast<ConstantSDNode>(N->getOperand(0))->getAPIntValue();
1501 return DAG.getVScale(SDLoc(N), VT, MulImm.sextOrSelf(VT.getSizeInBits()));
1502}
1503
1504SDValue DAGTypeLegalizer::PromoteIntRes_VAARG(SDNode *N) {
1505 SDValue Chain = N->getOperand(0); // Get the chain.
1506 SDValue Ptr = N->getOperand(1); // Get the pointer.
1507 EVT VT = N->getValueType(0);
1508 SDLoc dl(N);
1509
1510 MVT RegVT = TLI.getRegisterType(*DAG.getContext(), VT);
1511 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), VT);
1512 // The argument is passed as NumRegs registers of type RegVT.
1513
1514 SmallVector<SDValue, 8> Parts(NumRegs);
1515 for (unsigned i = 0; i < NumRegs; ++i) {
1516 Parts[i] = DAG.getVAArg(RegVT, dl, Chain, Ptr, N->getOperand(2),
1517 N->getConstantOperandVal(3));
1518 Chain = Parts[i].getValue(1);
1519 }
1520
1521 // Handle endianness of the load.
1522 if (DAG.getDataLayout().isBigEndian())
1523 std::reverse(Parts.begin(), Parts.end());
1524
1525 // Assemble the parts in the promoted type.
1526 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1527 SDValue Res = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Parts[0]);
1528 for (unsigned i = 1; i < NumRegs; ++i) {
1529 SDValue Part = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Parts[i]);
1530 // Shift it to the right position and "or" it in.
1531 Part = DAG.getNode(ISD::SHL, dl, NVT, Part,
1532 DAG.getConstant(i * RegVT.getSizeInBits(), dl,
1533 TLI.getPointerTy(DAG.getDataLayout())));
1534 Res = DAG.getNode(ISD::OR, dl, NVT, Res, Part);
1535 }
1536
1537 // Modified the chain result - switch anything that used the old chain to
1538 // use the new one.
1539 ReplaceValueWith(SDValue(N, 1), Chain);
1540
1541 return Res;
1542}
1543
1544//===----------------------------------------------------------------------===//
1545// Integer Operand Promotion
1546//===----------------------------------------------------------------------===//
1547
1548/// PromoteIntegerOperand - This method is called when the specified operand of
1549/// the specified node is found to need promotion. At this point, all of the
1550/// result types of the node are known to be legal, but other operands of the
1551/// node may need promotion or expansion as well as the specified one.
1552bool DAGTypeLegalizer::PromoteIntegerOperand(SDNode *N, unsigned OpNo) {
1553 LLVM_DEBUG(dbgs() << "Promote integer operand: "; N->dump(&DAG);do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("legalize-types")) { dbgs() << "Promote integer operand: "
; N->dump(&DAG); dbgs() << "\n"; } } while (false
)
1554 dbgs() << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("legalize-types")) { dbgs() << "Promote integer operand: "
; N->dump(&DAG); dbgs() << "\n"; } } while (false
)
;
1555 SDValue Res = SDValue();
1556 if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false)) {
1557 LLVM_DEBUG(dbgs() << "Node has been custom lowered, done\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("legalize-types")) { dbgs() << "Node has been custom lowered, done\n"
; } } while (false)
;
1558 return false;
1559 }
1560
1561 switch (N->getOpcode()) {
1562 default:
1563 #ifndef NDEBUG
1564 dbgs() << "PromoteIntegerOperand Op #" << OpNo << ": ";
1565 N->dump(&DAG); dbgs() << "\n";
1566 #endif
1567 llvm_unreachable("Do not know how to promote this operator's operand!")::llvm::llvm_unreachable_internal("Do not know how to promote this operator's operand!"
, "llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp", 1567
)
;
1568
1569 case ISD::ANY_EXTEND: Res = PromoteIntOp_ANY_EXTEND(N); break;
1570 case ISD::ATOMIC_STORE:
1571 Res = PromoteIntOp_ATOMIC_STORE(cast<AtomicSDNode>(N));
1572 break;
1573 case ISD::BITCAST: Res = PromoteIntOp_BITCAST(N); break;
1574 case ISD::BR_CC: Res = PromoteIntOp_BR_CC(N, OpNo); break;
1575 case ISD::BRCOND: Res = PromoteIntOp_BRCOND(N, OpNo); break;
1576 case ISD::BUILD_PAIR: Res = PromoteIntOp_BUILD_PAIR(N); break;
1577 case ISD::BUILD_VECTOR: Res = PromoteIntOp_BUILD_VECTOR(N); break;
1578 case ISD::CONCAT_VECTORS: Res = PromoteIntOp_CONCAT_VECTORS(N); break;
1579 case ISD::EXTRACT_VECTOR_ELT: Res = PromoteIntOp_EXTRACT_VECTOR_ELT(N); break;
1580 case ISD::INSERT_VECTOR_ELT:
1581 Res = PromoteIntOp_INSERT_VECTOR_ELT(N, OpNo);break;
1582 case ISD::SCALAR_TO_VECTOR:
1583 Res = PromoteIntOp_SCALAR_TO_VECTOR(N); break;
1584 case ISD::SPLAT_VECTOR:
1585 Res = PromoteIntOp_SPLAT_VECTOR(N); break;
1586 case ISD::VSELECT:
1587 case ISD::SELECT: Res = PromoteIntOp_SELECT(N, OpNo); break;
1588 case ISD::SELECT_CC: Res = PromoteIntOp_SELECT_CC(N, OpNo); break;
1589 case ISD::SETCC: Res = PromoteIntOp_SETCC(N, OpNo); break;
1590 case ISD::SIGN_EXTEND: Res = PromoteIntOp_SIGN_EXTEND(N); break;
1591 case ISD::SINT_TO_FP: Res = PromoteIntOp_SINT_TO_FP(N); break;
1592 case ISD::STRICT_SINT_TO_FP: Res = PromoteIntOp_STRICT_SINT_TO_FP(N); break;
1593 case ISD::STORE: Res = PromoteIntOp_STORE(cast<StoreSDNode>(N),
1594 OpNo); break;
1595 case ISD::MSTORE: Res = PromoteIntOp_MSTORE(cast<MaskedStoreSDNode>(N),
1596 OpNo); break;
1597 case ISD::MLOAD: Res = PromoteIntOp_MLOAD(cast<MaskedLoadSDNode>(N),
1598 OpNo); break;
1599 case ISD::MGATHER: Res = PromoteIntOp_MGATHER(cast<MaskedGatherSDNode>(N),
1600 OpNo); break;
1601 case ISD::MSCATTER: Res = PromoteIntOp_MSCATTER(cast<MaskedScatterSDNode>(N),
1602 OpNo); break;
1603 case ISD::TRUNCATE: Res = PromoteIntOp_TRUNCATE(N); break;
1604 case ISD::FP16_TO_FP:
1605 case ISD::UINT_TO_FP: Res = PromoteIntOp_UINT_TO_FP(N); break;
1606 case ISD::STRICT_UINT_TO_FP: Res = PromoteIntOp_STRICT_UINT_TO_FP(N); break;
1607 case ISD::ZERO_EXTEND: Res = PromoteIntOp_ZERO_EXTEND(N); break;
1608 case ISD::EXTRACT_SUBVECTOR: Res = PromoteIntOp_EXTRACT_SUBVECTOR(N); break;
1609 case ISD::INSERT_SUBVECTOR: Res = PromoteIntOp_INSERT_SUBVECTOR(N); break;
1610
1611 case ISD::SHL:
1612 case ISD::SRA:
1613 case ISD::SRL:
1614 case ISD::ROTL:
1615 case ISD::ROTR: Res = PromoteIntOp_Shift(N); break;
1616
1617 case ISD::SADDO_CARRY:
1618 case ISD::SSUBO_CARRY:
1619 case ISD::ADDCARRY:
1620 case ISD::SUBCARRY: Res = PromoteIntOp_ADDSUBCARRY(N, OpNo); break;
1621
1622 case ISD::FRAMEADDR:
1623 case ISD::RETURNADDR: Res = PromoteIntOp_FRAMERETURNADDR(N); break;
1624
1625 case ISD::PREFETCH: Res = PromoteIntOp_PREFETCH(N, OpNo); break;
1626
1627 case ISD::SMULFIX:
1628 case ISD::SMULFIXSAT:
1629 case ISD::UMULFIX:
1630 case ISD::UMULFIXSAT:
1631 case ISD::SDIVFIX:
1632 case ISD::SDIVFIXSAT:
1633 case ISD::UDIVFIX:
1634 case ISD::UDIVFIXSAT: Res = PromoteIntOp_FIX(N); break;
1635
1636 case ISD::FPOWI:
1637 case ISD::STRICT_FPOWI: Res = PromoteIntOp_FPOWI(N); break;
1638
1639 case ISD::VECREDUCE_ADD:
1640 case ISD::VECREDUCE_MUL:
1641 case ISD::VECREDUCE_AND:
1642 case ISD::VECREDUCE_OR:
1643 case ISD::VECREDUCE_XOR:
1644 case ISD::VECREDUCE_SMAX:
1645 case ISD::VECREDUCE_SMIN:
1646 case ISD::VECREDUCE_UMAX:
1647 case ISD::VECREDUCE_UMIN: Res = PromoteIntOp_VECREDUCE(N); break;
1648 case ISD::VP_REDUCE_ADD:
1649 case ISD::VP_REDUCE_MUL:
1650 case ISD::VP_REDUCE_AND:
1651 case ISD::VP_REDUCE_OR:
1652 case ISD::VP_REDUCE_XOR:
1653 case ISD::VP_REDUCE_SMAX:
1654 case ISD::VP_REDUCE_SMIN:
1655 case ISD::VP_REDUCE_UMAX:
1656 case ISD::VP_REDUCE_UMIN:
1657 Res = PromoteIntOp_VP_REDUCE(N, OpNo);
1658 break;
1659
1660 case ISD::SET_ROUNDING: Res = PromoteIntOp_SET_ROUNDING(N); break;
1661 }
1662
1663 // If the result is null, the sub-method took care of registering results etc.
1664 if (!Res.getNode()) return false;
1665
1666 // If the result is N, the sub-method updated N in place. Tell the legalizer
1667 // core about this.
1668 if (Res.getNode() == N)
1669 return true;
1670
1671 const bool IsStrictFp = N->isStrictFPOpcode();
1672 assert(Res.getValueType() == N->getValueType(0) &&(static_cast <bool> (Res.getValueType() == N->getValueType
(0) && N->getNumValues() == (IsStrictFp ? 2 : 1) &&
"Invalid operand expansion") ? void (0) : __assert_fail ("Res.getValueType() == N->getValueType(0) && N->getNumValues() == (IsStrictFp ? 2 : 1) && \"Invalid operand expansion\""
, "llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp", 1674
, __extension__ __PRETTY_FUNCTION__))
1673 N->getNumValues() == (IsStrictFp ? 2 : 1) &&(static_cast <bool> (Res.getValueType() == N->getValueType
(0) && N->getNumValues() == (IsStrictFp ? 2 : 1) &&
"Invalid operand expansion") ? void (0) : __assert_fail ("Res.getValueType() == N->getValueType(0) && N->getNumValues() == (IsStrictFp ? 2 : 1) && \"Invalid operand expansion\""
, "llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp", 1674
, __extension__ __PRETTY_FUNCTION__))
1674 "Invalid operand expansion")(static_cast <bool> (Res.getValueType() == N->getValueType
(0) && N->getNumValues() == (IsStrictFp ? 2 : 1) &&
"Invalid operand expansion") ? void (0) : __assert_fail ("Res.getValueType() == N->getValueType(0) && N->getNumValues() == (IsStrictFp ? 2 : 1) && \"Invalid operand expansion\""
, "llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp", 1674
, __extension__ __PRETTY_FUNCTION__))
;
1675 LLVM_DEBUG(dbgs() << "Replacing: "; N->dump(&DAG); dbgs() << " with: ";do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("legalize-types")) { dbgs() << "Replacing: "; N->dump
(&DAG); dbgs() << " with: "; Res.dump(); } } while
(false)
1676 Res.dump())do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("legalize-types")) { dbgs() << "Replacing: "; N->dump
(&DAG); dbgs() << " with: "; Res.dump(); } } while
(false)
;
1677
1678 ReplaceValueWith(SDValue(N, 0), Res);
1679 if (IsStrictFp)
1680 ReplaceValueWith(SDValue(N, 1), SDValue(Res.getNode(), 1));
1681
1682 return false;
1683}
1684
1685/// PromoteSetCCOperands - Promote the operands of a comparison. This code is
1686/// shared among BR_CC, SELECT_CC, and SETCC handlers.
1687void DAGTypeLegalizer::PromoteSetCCOperands(SDValue &LHS, SDValue &RHS,
1688 ISD::CondCode CCCode) {
1689 // We have to insert explicit sign or zero extends. Note that we could
1690 // insert sign extends for ALL conditions. For those operations where either
1691 // zero or sign extension would be valid, we ask the target which extension
1692 // it would prefer.
1693
1694 // Signed comparisons always require sign extension.
1695 if (ISD::isSignedIntSetCC(CCCode)) {
1696 LHS = SExtPromotedInteger(LHS);
1697 RHS = SExtPromotedInteger(RHS);
1698 return;
1699 }
1700
1701 assert((ISD::isUnsignedIntSetCC(CCCode) || ISD::isIntEqualitySetCC(CCCode)) &&(static_cast <bool> ((ISD::isUnsignedIntSetCC(CCCode) ||
ISD::isIntEqualitySetCC(CCCode)) && "Unknown integer comparison!"
) ? void (0) : __assert_fail ("(ISD::isUnsignedIntSetCC(CCCode) || ISD::isIntEqualitySetCC(CCCode)) && \"Unknown integer comparison!\""
, "llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp", 1702
, __extension__ __PRETTY_FUNCTION__))
1702 "Unknown integer comparison!")(static_cast <bool> ((ISD::isUnsignedIntSetCC(CCCode) ||
ISD::isIntEqualitySetCC(CCCode)) && "Unknown integer comparison!"
) ? void (0) : __assert_fail ("(ISD::isUnsignedIntSetCC(CCCode) || ISD::isIntEqualitySetCC(CCCode)) && \"Unknown integer comparison!\""
, "llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp", 1702
, __extension__ __PRETTY_FUNCTION__))
;
1703
1704 SDValue OpL = GetPromotedInteger(LHS);
1705 SDValue OpR = GetPromotedInteger(RHS);
1706
1707 if (TLI.isSExtCheaperThanZExt(LHS.getValueType(), OpL.getValueType())) {
1708 // The target would prefer to promote the comparison operand with sign
1709 // extension. Honor that unless the promoted values are already zero
1710 // extended.
1711 unsigned OpLEffectiveBits =
1712 DAG.computeKnownBits(OpL).countMaxActiveBits();
1713 unsigned OpREffectiveBits =
1714 DAG.computeKnownBits(OpR).countMaxActiveBits();
1715 if (OpLEffectiveBits <= LHS.getScalarValueSizeInBits() &&
1716 OpREffectiveBits <= RHS.getScalarValueSizeInBits()) {
1717 LHS = OpL;
1718 RHS = OpR;
1719 return;
1720 }
1721
1722 // The promoted values aren't zero extended, use a sext_inreg.
1723 LHS = SExtPromotedInteger(LHS);
1724 RHS = SExtPromotedInteger(RHS);
1725 return;
1726 }
1727
1728 // Prefer to promote the comparison operand with zero extension.
1729
1730 // If the width of OpL/OpR excluding the duplicated sign bits is no greater
1731 // than the width of LHS/RHS, we can avoid/ inserting a zext_inreg operation
1732 // that we might not be able to remove.
1733 unsigned OpLEffectiveBits = DAG.ComputeMaxSignificantBits(OpL);
1734 unsigned OpREffectiveBits = DAG.ComputeMaxSignificantBits(OpR);
1735 if (OpLEffectiveBits <= LHS.getScalarValueSizeInBits() &&
1736 OpREffectiveBits <= RHS.getScalarValueSizeInBits()) {
1737 LHS = OpL;
1738 RHS = OpR;
1739 return;
1740 }
1741
1742 // Otherwise, use zext_inreg.
1743 LHS = ZExtPromotedInteger(LHS);
1744 RHS = ZExtPromotedInteger(RHS);
1745}
1746
1747SDValue DAGTypeLegalizer::PromoteIntOp_ANY_EXTEND(SDNode *N) {
1748 SDValue Op = GetPromotedInteger(N->getOperand(0));
1749 return DAG.getNode(ISD::ANY_EXTEND, SDLoc(N), N->getValueType(0), Op);
1750}
1751
1752SDValue DAGTypeLegalizer::PromoteIntOp_ATOMIC_STORE(AtomicSDNode *N) {
1753 SDValue Op2 = GetPromotedInteger(N->getOperand(2));
1754 return DAG.getAtomic(N->getOpcode(), SDLoc(N), N->getMemoryVT(),
1755 N->getChain(), N->getBasePtr(), Op2, N->getMemOperand());
1756}
1757
1758SDValue DAGTypeLegalizer::PromoteIntOp_BITCAST(SDNode *N) {
1759 // This should only occur in unusual situations like bitcasting to an
1760 // x86_fp80, so just turn it into a store+load
1761 return CreateStackStoreLoad(N->getOperand(0), N->getValueType(0));
1762}
1763
1764SDValue DAGTypeLegalizer::PromoteIntOp_BR_CC(SDNode *N, unsigned OpNo) {
1765 assert(OpNo == 2 && "Don't know how to promote this operand!")(static_cast <bool> (OpNo == 2 && "Don't know how to promote this operand!"
) ? void (0) : __assert_fail ("OpNo == 2 && \"Don't know how to promote this operand!\""
, "llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp", 1765
, __extension__ __PRETTY_FUNCTION__))
;
1766
1767 SDValue LHS = N->getOperand(2);
1768 SDValue RHS = N->getOperand(3);
1769 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(1))->get());
1770
1771 // The chain (Op#0), CC (#1) and basic block destination (Op#4) are always
1772 // legal types.
1773 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
1774 N->getOperand(1), LHS, RHS, N->getOperand(4)),
1775 0);
1776}
1777
1778SDValue DAGTypeLegalizer::PromoteIntOp_BRCOND(SDNode *N, unsigned OpNo) {
1779 assert(OpNo == 1 && "only know how to promote condition")(static_cast <bool> (OpNo == 1 && "only know how to promote condition"
) ? void (0) : __assert_fail ("OpNo == 1 && \"only know how to promote condition\""
, "llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp", 1779
, __extension__ __PRETTY_FUNCTION__))
;
1780
1781 // Promote all the way up to the canonical SetCC type.
1782 SDValue Cond = PromoteTargetBoolean(N->getOperand(1), MVT::Other);
1783
1784 // The chain (Op#0) and basic block destination (Op#2) are always legal types.
1785 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0), Cond,
1786 N->getOperand(2)), 0);
1787}
1788
1789SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_PAIR(SDNode *N) {
1790 // Since the result type is legal, the operands must promote to it.
1791 EVT OVT = N->getOperand(0).getValueType();
1792 SDValue Lo = ZExtPromotedInteger(N->getOperand(0));
1793 SDValue Hi = GetPromotedInteger(N->getOperand(1));
1794 assert(Lo.getValueType() == N->getValueType(0) && "Operand over promoted?")(static_cast <bool> (Lo.getValueType() == N->getValueType
(0) && "Operand over promoted?") ? void (0) : __assert_fail
("Lo.getValueType() == N->getValueType(0) && \"Operand over promoted?\""
, "llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp", 1794
, __extension__ __PRETTY_FUNCTION__))
;
1795 SDLoc dl(N);
1796
1797 Hi = DAG.getNode(ISD::SHL, dl, N->getValueType(0), Hi,
1798 DAG.getConstant(OVT.getSizeInBits(), dl,
1799 TLI.getPointerTy(DAG.getDataLayout())));
1800 return DAG.getNode(ISD::OR, dl, N->getValueType(0), Lo, Hi);
1801}
1802
1803SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_VECTOR(SDNode *N) {
1804 // The vector type is legal but the element type is not. This implies
1805 // that the vector is a power-of-two in length and that the element
1806 // type does not have a strange size (eg: it is not i1).
1807 EVT VecVT = N->getValueType(0);
1808 unsigned NumElts = VecVT.getVectorNumElements();
1809 assert(!((NumElts & 1) && (!TLI.isTypeLegal(VecVT))) &&(static_cast <bool> (!((NumElts & 1) && (!TLI
.isTypeLegal(VecVT))) && "Legal vector of one illegal element?"
) ? void (0) : __assert_fail ("!((NumElts & 1) && (!TLI.isTypeLegal(VecVT))) && \"Legal vector of one illegal element?\""
, "llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp", 1810
, __extension__ __PRETTY_FUNCTION__))
1810 "Legal vector of one illegal element?")(static_cast <bool> (!((NumElts & 1) && (!TLI
.isTypeLegal(VecVT))) && "Legal vector of one illegal element?"
) ? void (0) : __assert_fail ("!((NumElts & 1) && (!TLI.isTypeLegal(VecVT))) && \"Legal vector of one illegal element?\""
, "llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp", 1810
, __extension__ __PRETTY_FUNCTION__))
;
1811
1812 // Promote the inserted value. The type does not need to match the
1813 // vector element type. Check that any extra bits introduced will be
1814 // truncated away.
1815 assert(N->getOperand(0).getValueSizeInBits() >=(static_cast <bool> (N->getOperand(0).getValueSizeInBits
() >= N->getValueType(0).getScalarSizeInBits() &&
"Type of inserted value narrower than vector element type!")
? void (0) : __assert_fail ("N->getOperand(0).getValueSizeInBits() >= N->getValueType(0).getScalarSizeInBits() && \"Type of inserted value narrower than vector element type!\""
, "llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp", 1817
, __extension__ __PRETTY_FUNCTION__))
1816 N->getValueType(0).getScalarSizeInBits() &&(static_cast <bool> (N->getOperand(0).getValueSizeInBits
() >= N->getValueType(0).getScalarSizeInBits() &&
"Type of inserted value narrower than vector element type!")
? void (0) : __assert_fail ("N->getOperand(0).getValueSizeInBits() >= N->getValueType(0).getScalarSizeInBits() && \"Type of inserted value narrower than vector element type!\""
, "llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp", 1817
, __extension__ __PRETTY_FUNCTION__))
1817 "Type of inserted value narrower than vector element type!")(static_cast <bool> (N->getOperand(0).getValueSizeInBits
() >= N->getValueType(0).getScalarSizeInBits() &&
"Type of inserted value narrower than vector element type!")
? void (0) : __assert_fail ("N->getOperand(0).getValueSizeInBits() >= N->getValueType(0).getScalarSizeInBits() && \"Type of inserted value narrower than vector element type!\""
, "llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp", 1817
, __extension__ __PRETTY_FUNCTION__))
;
1818
1819 SmallVector<SDValue, 16> NewOps;
1820 for (unsigned i = 0; i < NumElts; ++i)
1821 NewOps.push_back(GetPromotedInteger(N->getOperand(i)));
1822
1823 return SDValue(DAG.UpdateNodeOperands(N, NewOps), 0);
1824}
1825
1826SDValue DAGTypeLegalizer::PromoteIntOp_INSERT_VECTOR_ELT(SDNode *N,
1827 unsigned OpNo) {
1828 if (OpNo == 1) {
1829 // Promote the inserted value. This is valid because the type does not
1830 // have to match the vector element type.
1831
1832 // Check that any extra bits introduced will be truncated away.
1833 assert(N->getOperand(1).getValueSizeInBits() >=(static_cast <bool> (N->getOperand(1).getValueSizeInBits
() >= N->getValueType(0).getScalarSizeInBits() &&
"Type of inserted value narrower than vector element type!")
? void (0) : __assert_fail ("N->getOperand(1).getValueSizeInBits() >= N->getValueType(0).getScalarSizeInBits() && \"Type of inserted value narrower than vector element type!\""
, "llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp", 1835
, __extension__ __PRETTY_FUNCTION__))
1834 N->getValueType(0).getScalarSizeInBits() &&(static_cast <bool> (N->getOperand(1).getValueSizeInBits
() >= N->getValueType(0).getScalarSizeInBits() &&
"Type of inserted value narrower than vector element type!")
? void (0) : __assert_fail ("N->getOperand(1).getValueSizeInBits() >= N->getValueType(0).getScalarSizeInBits() && \"Type of inserted value narrower than vector element type!\""
, "llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp", 1835
, __extension__ __PRETTY_FUNCTION__))
1835 "Type of inserted value narrower than vector element type!")(static_cast <bool> (N->getOperand(1).getValueSizeInBits
() >= N->getValueType(0).getScalarSizeInBits() &&
"Type of inserted value narrower than vector element type!")
? void (0) : __assert_fail ("N->getOperand(1).getValueSizeInBits() >= N->getValueType(0).getScalarSizeInBits() && \"Type of inserted value narrower than vector element type!\""
, "llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp", 1835
, __extension__ __PRETTY_FUNCTION__))
;
1836 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
1837 GetPromotedInteger(N->getOperand(1)),
1838 N->getOperand(2)),
1839 0);
1840 }
1841
1842 assert(OpNo == 2 && "Different operand and result vector types?")(static_cast <bool> (OpNo == 2 && "Different operand and result vector types?"
) ? void (0) : __assert_fail ("OpNo == 2 && \"Different operand and result vector types?\""
, "llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp", 1842
, __extension__ __PRETTY_FUNCTION__))
;
1843
1844 // Promote the index.
1845 SDValue Idx = DAG.getZExtOrTrunc(N->getOperand(2), SDLoc(N),
1846 TLI.getVectorIdxTy(DAG.getDataLayout()));
1847 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
1848 N->getOperand(1), Idx), 0);
1849}
1850
1851SDValue DAGTypeLegalizer::PromoteIntOp_SCALAR_TO_VECTOR(SDNode *N) {
1852 // Integer SCALAR_TO_VECTOR operands are implicitly truncated, so just promote
1853 // the operand in place.
1854 return SDValue(DAG.UpdateNodeOperands(N,
1855 GetPromotedInteger(N->getOperand(0))), 0);
1856}
1857
1858SDValue DAGTypeLegalizer::PromoteIntOp_SPLAT_VECTOR(SDNode *N) {
1859 // Integer SPLAT_VECTOR operands are implicitly truncated, so just promote the
1860 // operand in place.
1861 return SDValue(
1862 DAG.UpdateNodeOperands(N, GetPromotedInteger(N->getOperand(0))), 0);
1863}
1864
1865SDValue DAGTypeLegalizer::PromoteIntOp_SELECT(SDNode *N, unsigned OpNo) {
1866 assert(OpNo == 0 && "Only know how to promote the condition!")(static_cast <bool> (OpNo == 0 && "Only know how to promote the condition!"
) ? void (0) : __assert_fail ("OpNo == 0 && \"Only know how to promote the condition!\""
, "llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp", 1866
, __extension__ __PRETTY_FUNCTION__))
;
1867 SDValue Cond = N->getOperand(0);
1868 EVT OpTy = N->getOperand(1).getValueType();
1869
1870 if (N->getOpcode() == ISD::VSELECT)
1871 if (SDValue Res = WidenVSELECTMask(N))
1872 return DAG.getNode(N->getOpcode(), SDLoc(N), N->getValueType(0),
1873 Res, N->getOperand(1), N->getOperand(2));
1874
1875 // Promote all the way up to the canonical SetCC type.
1876 EVT OpVT = N->getOpcode() == ISD::SELECT ? OpTy.getScalarType() : OpTy;
1877 Cond = PromoteTargetBoolean(Cond, OpVT);
1878
1879 return SDValue(DAG.UpdateNodeOperands(N, Cond, N->getOperand(1),
1880 N->getOperand(2)), 0);
1881}
1882
1883SDValue DAGTypeLegalizer::PromoteIntOp_SELECT_CC(SDNode *N, unsigned OpNo) {
1884 assert(OpNo == 0 && "Don't know how to promote this operand!")(static_cast <bool> (OpNo == 0 && "Don't know how to promote this operand!"
) ? void (0) : __assert_fail ("OpNo == 0 && \"Don't know how to promote this operand!\""
, "llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp", 1884
, __extension__ __PRETTY_FUNCTION__))
;
1885
1886 SDValue LHS = N->getOperand(0);
1887 SDValue RHS = N->getOperand(1);
1888 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(4))->get());
1889
1890 // The CC (#4) and the possible return values (#2 and #3) have legal types.
1891 return SDValue(DAG.UpdateNodeOperands(N, LHS, RHS, N->getOperand(2),
1892 N->getOperand(3), N->getOperand(4)), 0);
1893}
1894
1895SDValue DAGTypeLegalizer::PromoteIntOp_SETCC(SDNode *N, unsigned OpNo) {
1896 assert(OpNo == 0 && "Don't know how to promote this operand!")(static_cast <bool> (OpNo == 0 && "Don't know how to promote this operand!"
) ? void (0) : __assert_fail ("OpNo == 0 && \"Don't know how to promote this operand!\""
, "llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp", 1896
, __extension__ __PRETTY_FUNCTION__))
;
1897
1898 SDValue LHS = N->getOperand(0);
1899 SDValue RHS = N->getOperand(1);
1900 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(2))->get());
1901
1902 // The CC (#2) is always legal.
1903 return SDValue(DAG.UpdateNodeOperands(N, LHS, RHS, N->getOperand(2)), 0);
1904}
1905
1906SDValue DAGTypeLegalizer::PromoteIntOp_Shift(SDNode *N) {
1907 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
1908 ZExtPromotedInteger(N->getOperand(1))), 0);
1909}
1910
1911SDValue DAGTypeLegalizer::PromoteIntOp_SIGN_EXTEND(SDNode *N) {
1912 SDValue Op = GetPromotedInteger(N->getOperand(0));
1913 SDLoc dl(N);
1914 Op = DAG.getNode(ISD::ANY_EXTEND, dl, N->getValueType(0), Op);
1915 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Op.getValueType(),
1916 Op, DAG.getValueType(N->getOperand(0).getValueType()));
1917}
1918
1919SDValue DAGTypeLegalizer::PromoteIntOp_SINT_TO_FP(SDNode *N) {
1920 return SDValue(DAG.UpdateNodeOperands(N,
1921 SExtPromotedInteger(N->getOperand(0))), 0);
1922}
1923
1924SDValue DAGTypeLegalizer::PromoteIntOp_STRICT_SINT_TO_FP(SDNode *N) {
1925 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
1926 SExtPromotedInteger(N->getOperand(1))), 0);
1927}
1928
1929SDValue DAGTypeLegalizer::PromoteIntOp_STORE(StoreSDNode *N, unsigned OpNo){
1930 assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!")(static_cast <bool> (ISD::isUNINDEXEDStore(N) &&
"Indexed store during type legalization!") ? void (0) : __assert_fail
("ISD::isUNINDEXEDStore(N) && \"Indexed store during type legalization!\""
, "llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp", 1930
, __extension__ __PRETTY_FUNCTION__))
;
1931 SDValue Ch = N->getChain(), Ptr = N->getBasePtr();
1932 SDLoc dl(N);
1933
1934 SDValue Val = GetPromotedInteger(N->getValue()); // Get promoted value.
1935
1936 // Truncate the value and store the result.
1937 return DAG.getTruncStore(Ch, dl, Val, Ptr,
1938 N->getMemoryVT(), N->getMemOperand());
1939}
1940
1941SDValue DAGTypeLegalizer::PromoteIntOp_MSTORE(MaskedStoreSDNode *N,
1942 unsigned OpNo) {
1943 SDValue DataOp = N->getValue();
1944 SDValue Mask = N->getMask();
1945
1946 if (OpNo == 4) {
1947 // The Mask. Update in place.
1948 EVT DataVT = DataOp.getValueType();
1949 Mask = PromoteTargetBoolean(Mask, DataVT);
1950 SmallVector<SDValue, 4> NewOps(N->op_begin(), N->op_end());
1951 NewOps[4] = Mask;
1952 return SDValue(DAG.UpdateNodeOperands(N, NewOps), 0);
1953 }
1954
1955 assert(OpNo == 1 && "Unexpected operand for promotion")(static_cast <bool> (OpNo == 1 && "Unexpected operand for promotion"
) ? void (0) : __assert_fail ("OpNo == 1 && \"Unexpected operand for promotion\""
, "llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp", 1955
, __extension__ __PRETTY_FUNCTION__))
;
1956 DataOp = GetPromotedInteger(DataOp);
1957
1958 return DAG.getMaskedStore(N->getChain(), SDLoc(N), DataOp, N->getBasePtr(),
1959 N->getOffset(), Mask, N->getMemoryVT(),
1960 N->getMemOperand(), N->getAddressingMode(),
1961 /*IsTruncating*/ true, N->isCompressingStore());
1962}
1963
1964SDValue DAGTypeLegalizer::PromoteIntOp_MLOAD(MaskedLoadSDNode *N,
1965 unsigned OpNo) {
1966 assert(OpNo == 3 && "Only know how to promote the mask!")(static_cast <bool> (OpNo == 3 && "Only know how to promote the mask!"
) ? void (0) : __assert_fail ("OpNo == 3 && \"Only know how to promote the mask!\""
, "llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp", 1966
, __extension__ __PRETTY_FUNCTION__))
;
1967 EVT DataVT = N->getValueType(0);
1968 SDValue Mask = PromoteTargetBoolean(N->getOperand(OpNo), DataVT);
1969 SmallVector<SDValue, 4> NewOps(N->op_begin(), N->op_end());
1970 NewOps[OpNo] = Mask;
1971 SDNode *Res = DAG.UpdateNodeOperands(N, NewOps);
1972 if (Res == N)
1973 return SDValue(Res, 0);
1974
1975 // Update triggered CSE, do our own replacement since caller can't.
1976 ReplaceValueWith(SDValue(N, 0), SDValue(Res, 0));
1977 ReplaceValueWith(SDValue(N, 1), SDValue(Res, 1));
1978 return SDValue();
1979}
1980
1981SDValue DAGTypeLegalizer::PromoteIntOp_MGATHER(MaskedGatherSDNode *N,
1982 unsigned OpNo) {
1983
1984 SmallVector<SDValue, 5> NewOps(N->op_begin(), N->op_end());
1985 if (OpNo == 2) {
1986 // The Mask
1987 EVT DataVT = N->getValueType(0);
1988 NewOps[OpNo] = PromoteTargetBoolean(N->getOperand(OpNo), DataVT);
1989 } else if (OpNo == 4) {
1990 // The Index
1991 if (N->isIndexSigned())
1992 // Need to sign extend the index since the bits will likely be used.
1993 NewOps[OpNo] = SExtPromotedInteger(N->getOperand(OpNo));
1994 else
1995 NewOps[OpNo] = ZExtPromotedInteger(N->getOperand(OpNo));
1996 } else
1997 NewOps[OpNo] = GetPromotedInteger(N->getOperand(OpNo));
1998
1999 SDNode *Res = DAG.UpdateNodeOperands(N, NewOps);
2000 if (Res == N)
2001 return SDValue(Res, 0);
2002
2003 // Update triggered CSE, do our own replacement since caller can't.
2004 ReplaceValueWith(SDValue(N, 0), SDValue(Res, 0));
2005 ReplaceValueWith(SDValue(N, 1), SDValue(Res, 1));
2006 return SDValue();
2007}
2008
2009SDValue DAGTypeLegalizer::PromoteIntOp_MSCATTER(MaskedScatterSDNode *N,
2010 unsigned OpNo) {
2011 bool TruncateStore = N->isTruncatingStore();
2012 SmallVector<SDValue, 5> NewOps(N->op_begin(), N->op_end());
2013 if (OpNo == 2) {
2014 // The Mask
2015 EVT DataVT = N->getValue().getValueType();
2016 NewOps[OpNo] = PromoteTargetBoolean(N->getOperand(OpNo), DataVT);
2017 } else if (OpNo == 4) {
2018 // The Index
2019 if (N->isIndexSigned())
2020 // Need to sign extend the index since the bits will likely be used.
2021 NewOps[OpNo] = SExtPromotedInteger(N->getOperand(OpNo));
2022 else
2023 NewOps[OpNo] = ZExtPromotedInteger(N->getOperand(OpNo));
2024
2025 N->setIndexType(TLI.getCanonicalIndexType(N->getIndexType(),
2026 N->getMemoryVT(), NewOps[OpNo]));
2027 } else {
2028 NewOps[OpNo] = GetPromotedInteger(N->getOperand(OpNo));
2029 TruncateStore = true;
2030 }
2031
2032 return DAG.getMaskedScatter(DAG.getVTList(MVT::Other), N->getMemoryVT(),
2033 SDLoc(N), NewOps, N->getMemOperand(),
2034 N->getIndexType(), TruncateStore);
2035}
2036
2037SDValue DAGTypeLegalizer::PromoteIntOp_TRUNCATE(SDNode *N) {
2038 SDValue Op = GetPromotedInteger(N->getOperand(0));
2039 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), N->getValueType(0), Op);
2040}
2041
2042SDValue DAGTypeLegalizer::PromoteIntOp_UINT_TO_FP(SDNode *N) {
2043 return SDValue(DAG.UpdateNodeOperands(N,
2044 ZExtPromotedInteger(N->getOperand(0))), 0);
2045}
2046
2047SDValue DAGTypeLegalizer::PromoteIntOp_STRICT_UINT_TO_FP(SDNode *N) {
2048 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
2049 ZExtPromotedInteger(N->getOperand(1))), 0);
2050}
2051
2052SDValue DAGTypeLegalizer::PromoteIntOp_ZERO_EXTEND(SDNode *N) {
2053 SDLoc dl(N);
2054 SDValue Op = GetPromotedInteger(N->getOperand(0));
2055 Op = DAG.getNode(ISD::ANY_EXTEND, dl, N->getValueType(0), Op);
2056 return DAG.getZeroExtendInReg(Op, dl, N->getOperand(0).getValueType());
2057}
2058
2059SDValue DAGTypeLegalizer::PromoteIntOp_ADDSUBCARRY(SDNode *N, unsigned OpNo) {
2060 assert(OpNo == 2 && "Don't know how to promote this operand!")(static_cast <bool> (OpNo == 2 && "Don't know how to promote this operand!"
) ? void (0) : __assert_fail ("OpNo == 2 && \"Don't know how to promote this operand!\""
, "llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp", 2060
, __extension__ __PRETTY_FUNCTION__))
;
2061
2062 SDValue LHS = N->getOperand(0);
2063 SDValue RHS = N->getOperand(1);
2064 SDValue Carry = N->getOperand(2);
2065 SDLoc DL(N);
2066
2067 Carry = PromoteTargetBoolean(Carry, LHS.getValueType());
2068
2069 return SDValue(DAG.UpdateNodeOperands(N, LHS, RHS, Carry), 0);
2070}
2071
2072SDValue DAGTypeLegalizer::PromoteIntOp_FIX(SDNode *N) {
2073 SDValue Op2 = ZExtPromotedInteger(N->getOperand(2));
2074 return SDValue(
2075 DAG.UpdateNodeOperands(N, N->getOperand(0), N->getOperand(1), Op2), 0);
2076}
2077
2078SDValue DAGTypeLegalizer::PromoteIntOp_FRAMERETURNADDR(SDNode *N) {
2079 // Promote the RETURNADDR/FRAMEADDR argument to a supported integer width.
2080 SDValue Op = ZExtPromotedInteger(N->getOperand(0));
2081 return SDValue(DAG.UpdateNodeOperands(N, Op), 0);
2082}
2083
2084SDValue DAGTypeLegalizer::PromoteIntOp_PREFETCH(SDNode *N, unsigned OpNo) {
2085 assert(OpNo > 1 && "Don't know how to promote this operand!")(static_cast <bool> (OpNo > 1 && "Don't know how to promote this operand!"
) ? void (0) : __assert_fail ("OpNo > 1 && \"Don't know how to promote this operand!\""
, "llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp", 2085
, __extension__ __PRETTY_FUNCTION__))
;
2086 // Promote the rw, locality, and cache type arguments to a supported integer
2087 // width.
2088 SDValue Op2 = ZExtPromotedInteger(N->getOperand(2));
2089 SDValue Op3 = ZExtPromotedInteger(N->getOperand(3));
2090 SDValue Op4 = ZExtPromotedInteger(N->getOperand(4));
2091 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0), N->getOperand(1),
2092 Op2, Op3, Op4),
2093 0);
2094}
2095
2096SDValue DAGTypeLegalizer::PromoteIntOp_FPOWI(SDNode *N) {
2097 bool IsStrict = N->isStrictFPOpcode();
2098 SDValue Chain = IsStrict ? N->getOperand(0) : SDValue();
2099
2100 // The integer operand is the last operand in FPOWI (so the result and
2101 // floating point operand is already type legalized).
2102
2103 // We can't just promote the exponent type in FPOWI, since we want to lower
2104 // the node to a libcall and we if we promote to a type larger than
2105 // sizeof(int) the libcall might not be according to the targets ABI. Instead
2106 // we rewrite to a libcall here directly, letting makeLibCall handle promotion
2107 // if the target accepts it according to shouldSignExtendTypeInLibCall.
2108 RTLIB::Libcall LC = RTLIB::getPOWI(N->getValueType(0));
2109 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fpowi.")(static_cast <bool> (LC != RTLIB::UNKNOWN_LIBCALL &&
"Unexpected fpowi.") ? void (0) : __assert_fail ("LC != RTLIB::UNKNOWN_LIBCALL && \"Unexpected fpowi.\""
, "llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp", 2109
, __extension__ __PRETTY_FUNCTION__))
;
2110 if (!TLI.getLibcallName(LC)) {
2111 // Some targets don't have a powi libcall; use pow instead.
2112 // FIXME: Implement this if some target needs it.
2113 DAG.getContext()->emitError("Don't know how to promote fpowi to fpow");
2114 return DAG.getUNDEF(N->getValueType(0));
2115 }
2116 unsigned OpOffset = IsStrict ? 1 : 0;
2117 // The exponent should fit in a sizeof(int) type for the libcall to be valid.
2118 assert(DAG.getLibInfo().getIntSize() ==(static_cast <bool> (DAG.getLibInfo().getIntSize() == N
->getOperand(1 + OpOffset).getValueType().getSizeInBits() &&
"POWI exponent should match with sizeof(int) when doing the libcall."
) ? void (0) : __assert_fail ("DAG.getLibInfo().getIntSize() == N->getOperand(1 + OpOffset).getValueType().getSizeInBits() && \"POWI exponent should match with sizeof(int) when doing the libcall.\""
, "llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp", 2120
, __extension__ __PRETTY_FUNCTION__))
2119 N->getOperand(1 + OpOffset).getValueType().getSizeInBits() &&(static_cast <bool> (DAG.getLibInfo().getIntSize() == N
->getOperand(1 + OpOffset).getValueType().getSizeInBits() &&
"POWI exponent should match with sizeof(int) when doing the libcall."
) ? void (0) : __assert_fail ("DAG.getLibInfo().getIntSize() == N->getOperand(1 + OpOffset).getValueType().getSizeInBits() && \"POWI exponent should match with sizeof(int) when doing the libcall.\""
, "llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp", 2120
, __extension__ __PRETTY_FUNCTION__))
2120 "POWI exponent should match with sizeof(int) when doing the libcall.")(static_cast <bool> (DAG.getLibInfo().getIntSize() == N
->getOperand(1 + OpOffset).getValueType().getSizeInBits() &&
"POWI exponent should match with sizeof(int) when doing the libcall."
) ? void (0) : __assert_fail ("DAG.getLibInfo().getIntSize() == N->getOperand(1 + OpOffset).getValueType().getSizeInBits() && \"POWI exponent should match with sizeof(int) when doing the libcall.\""
, "llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp", 2120
, __extension__ __PRETTY_FUNCTION__))
;
2121 TargetLowering::MakeLibCallOptions CallOptions;
2122 CallOptions.setSExt(true);
2123 SDValue Ops[2] = {N->getOperand(0 + OpOffset), N->getOperand(1 + OpOffset)};
2124 std::pair<SDValue, SDValue> Tmp = TLI.makeLibCall(
2125 DAG, LC, N->getValueType(0), Ops, CallOptions, SDLoc(N), Chain);
2126 ReplaceValueWith(SDValue(N, 0), Tmp.first);
2127 if (IsStrict)
2128 ReplaceValueWith(SDValue(N, 1), Tmp.second);
2129 return SDValue();
2130}
2131
2132static unsigned getExtendForIntVecReduction(SDNode *N) {
2133 switch (N->getOpcode()) {
2134 default:
2135 llvm_unreachable("Expected integer vector reduction")::llvm::llvm_unreachable_internal("Expected integer vector reduction"
, "llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp", 2135
)
;
2136 case ISD::VECREDUCE_ADD:
2137 case ISD::VECREDUCE_MUL:
2138 case ISD::VECREDUCE_AND:
2139 case ISD::VECREDUCE_OR:
2140 case ISD::VECREDUCE_XOR:
2141 case ISD::VP_REDUCE_ADD:
2142 case ISD::VP_REDUCE_MUL:
2143 case ISD::VP_REDUCE_AND:
2144 case ISD::VP_REDUCE_OR:
2145 case ISD::VP_REDUCE_XOR:
2146 return ISD::ANY_EXTEND;
2147 case ISD::VECREDUCE_SMAX:
2148 case ISD::VECREDUCE_SMIN:
2149 case ISD::VP_REDUCE_SMAX:
2150 case ISD::VP_REDUCE_SMIN:
2151 return ISD::SIGN_EXTEND;
2152 case ISD::VECREDUCE_UMAX:
2153 case ISD::VECREDUCE_UMIN:
2154 case ISD::VP_REDUCE_UMAX:
2155 case ISD::VP_REDUCE_UMIN:
2156 return ISD::ZERO_EXTEND;
2157 }
2158}
2159
2160SDValue DAGTypeLegalizer::PromoteIntOpVectorReduction(SDNode *N, SDValue V) {
2161 switch (getExtendForIntVecReduction(N)) {
2162 default:
2163 llvm_unreachable("Impossible extension kind for integer reduction")::llvm::llvm_unreachable_internal("Impossible extension kind for integer reduction"
, "llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp", 2163
)
;
2164 case ISD::ANY_EXTEND:
2165 return GetPromotedInteger(V);
2166 case ISD::SIGN_EXTEND:
2167 return SExtPromotedInteger(V);
2168 case ISD::ZERO_EXTEND:
2169 return ZExtPromotedInteger(V);
2170 }
2171}
2172
2173SDValue DAGTypeLegalizer::PromoteIntOp_VECREDUCE(SDNode *N) {
2174 SDLoc dl(N);
2175 SDValue Op = PromoteIntOpVectorReduction(N, N->getOperand(0));
2176
2177 EVT EltVT = Op.getValueType().getVectorElementType();
2178 EVT VT = N->getValueType(0);
2179
2180 if (VT.bitsGE(EltVT))
2181 return DAG.getNode(N->getOpcode(), SDLoc(N), VT, Op);
2182
2183 // Result size must be >= element size. If this is not the case after
2184 // promotion, also promote the result type and then truncate.
2185 SDValue Reduce = DAG.getNode(N->getOpcode(), dl, EltVT, Op);
2186 return DAG.getNode(ISD::TRUNCATE, dl, VT, Reduce);
2187}
2188
2189SDValue DAGTypeLegalizer::PromoteIntOp_VP_REDUCE(SDNode *N, unsigned OpNo) {
2190 SDLoc DL(N);
2191 SDValue Op = N->getOperand(OpNo);
2192 SmallVector<SDValue, 4> NewOps(N->op_begin(), N->op_end());
2193
2194 if (OpNo == 2) { // Mask
2195 // Update in place.
2196 NewOps[2] = PromoteTargetBoolean(Op, N->getOperand(1).getValueType());
2197 return SDValue(DAG.UpdateNodeOperands(N, NewOps), 0);
2198 }
2199
2200 assert(OpNo == 1 && "Unexpected operand for promotion")(static_cast <bool> (OpNo == 1 && "Unexpected operand for promotion"
) ? void (0) : __assert_fail ("OpNo == 1 && \"Unexpected operand for promotion\""
, "llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp", 2200
, __extension__ __PRETTY_FUNCTION__))
;
2201
2202 Op = PromoteIntOpVectorReduction(N, Op);
2203
2204 NewOps[OpNo] = Op;
2205
2206 EVT VT = N->getValueType(0);
2207 EVT EltVT = Op.getValueType().getScalarType();
2208
2209 if (VT.bitsGE(EltVT))
2210 return DAG.getNode(N->getOpcode(), SDLoc(N), VT, NewOps);
2211
2212 // Result size must be >= element/start-value size. If this is not the case
2213 // after promotion, also promote both the start value and result type and
2214 // then truncate.
2215 NewOps[0] =
2216 DAG.getNode(getExtendForIntVecReduction(N), DL, EltVT, N->getOperand(0));
2217 SDValue Reduce = DAG.getNode(N->getOpcode(), DL, EltVT, NewOps);
2218 return DAG.getNode(ISD::TRUNCATE, DL, VT, Reduce);
2219}
2220
2221SDValue DAGTypeLegalizer::PromoteIntOp_SET_ROUNDING(SDNode *N) {
2222 SDValue Op = ZExtPromotedInteger(N->getOperand(1));
2223 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0), Op), 0);
2224}
2225
2226//===----------------------------------------------------------------------===//
2227// Integer Result Expansion
2228//===----------------------------------------------------------------------===//
2229
2230/// ExpandIntegerResult - This method is called when the specified result of the
2231/// specified node is found to need expansion. At this point, the node may also
2232/// have invalid operands or may have other results that need promotion, we just
2233/// know that (at least) one result needs expansion.
2234void DAGTypeLegalizer::ExpandIntegerResult(SDNode *N, unsigned ResNo) {
2235 LLVM_DEBUG(dbgs() << "Expand integer result: "; N->dump(&DAG);do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("legalize-types")) { dbgs() << "Expand integer result: "
; N->dump(&DAG); dbgs() << "\n"; } } while (false
)
1
Assuming 'DebugFlag' is false
2
Loop condition is false. Exiting loop
2236 dbgs() << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("legalize-types")) { dbgs() << "Expand integer result: "
; N->dump(&DAG); dbgs() << "\n"; } } while (false
)
;
2237 SDValue Lo, Hi;
2238 Lo = Hi = SDValue();
2239
2240 // See if the target wants to custom expand this node.
2241 if (CustomLowerNode(N, N->getValueType(ResNo), true))
3
Assuming the condition is false
4
Taking false branch
2242 return;
2243
2244 switch (N->getOpcode()) {
5
Control jumps to 'case SHL:' at line 2365
2245 default:
2246#ifndef NDEBUG
2247 dbgs() << "ExpandIntegerResult #" << ResNo << ": ";
2248 N->dump(&DAG); dbgs() << "\n";
2249#endif
2250 report_fatal_error("Do not know how to expand the result of this "
2251 "operator!");
2252
2253 case ISD::ARITH_FENCE: SplitRes_ARITH_FENCE(N, Lo, Hi); break;
2254 case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, ResNo, Lo, Hi); break;
2255 case ISD::SELECT: SplitRes_Select(N, Lo, Hi); break;
2256 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break;
2257 case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break;
2258 case ISD::FREEZE: SplitRes_FREEZE(N, Lo, Hi); break;
2259
2260 case ISD::BITCAST: ExpandRes_BITCAST(N, Lo, Hi); break;
2261 case ISD::BUILD_PAIR: ExpandRes_BUILD_PAIR(N, Lo, Hi); break;
2262 case ISD::EXTRACT_ELEMENT: ExpandRes_EXTRACT_ELEMENT(N, Lo, Hi); break;
2263 case ISD::EXTRACT_VECTOR_ELT: ExpandRes_EXTRACT_VECTOR_ELT(N, Lo, Hi); break;
2264 case ISD::VAARG: ExpandRes_VAARG(N, Lo, Hi); break;
2265
2266 case ISD::ANY_EXTEND: ExpandIntRes_ANY_EXTEND(N, Lo, Hi); break;
2267 case ISD::AssertSext: ExpandIntRes_AssertSext(N, Lo, Hi); break;
2268 case ISD::AssertZext: ExpandIntRes_AssertZext(N, Lo, Hi); break;
2269 case ISD::BITREVERSE: ExpandIntRes_BITREVERSE(N, Lo, Hi); break;
2270 case ISD::BSWAP: ExpandIntRes_BSWAP(N, Lo, Hi); break;
2271 case ISD::PARITY: ExpandIntRes_PARITY(N, Lo, Hi); break;
2272 case ISD::Constant: ExpandIntRes_Constant(N, Lo, Hi); break;
2273 case ISD::ABS: ExpandIntRes_ABS(N, Lo, Hi); break;
2274 case ISD::CTLZ_ZERO_UNDEF:
2275 case ISD::CTLZ: ExpandIntRes_CTLZ(N, Lo, Hi); break;
2276 case ISD::CTPOP: ExpandIntRes_CTPOP(N, Lo, Hi); break;
2277 case ISD::CTTZ_ZERO_UNDEF:
2278 case ISD::CTTZ: ExpandIntRes_CTTZ(N, Lo, Hi); break;
2279 case ISD::FLT_ROUNDS_: ExpandIntRes_FLT_ROUNDS(N, Lo, Hi); break;
2280 case ISD::STRICT_FP_TO_SINT:
2281 case ISD::FP_TO_SINT: ExpandIntRes_FP_TO_SINT(N, Lo, Hi); break;
2282 case ISD::STRICT_FP_TO_UINT:
2283 case ISD::FP_TO_UINT: ExpandIntRes_FP_TO_UINT(N, Lo, Hi); break;
2284 case ISD::FP_TO_SINT_SAT:
2285 case ISD::FP_TO_UINT_SAT: ExpandIntRes_FP_TO_XINT_SAT(N, Lo, Hi); break;
2286 case ISD::STRICT_LLROUND:
2287 case ISD::STRICT_LLRINT:
2288 case ISD::LLROUND:
2289 case ISD::LLRINT: ExpandIntRes_LLROUND_LLRINT(N, Lo, Hi); break;
2290 case ISD::LOAD: ExpandIntRes_LOAD(cast<LoadSDNode>(N), Lo, Hi); break;
2291 case ISD::MUL: ExpandIntRes_MUL(N, Lo, Hi); break;
2292 case ISD::READCYCLECOUNTER: ExpandIntRes_READCYCLECOUNTER(N, Lo, Hi); break;
2293 case ISD::SDIV: ExpandIntRes_SDIV(N, Lo, Hi); break;
2294 case ISD::SIGN_EXTEND: ExpandIntRes_SIGN_EXTEND(N, Lo, Hi); break;
2295 case ISD::SIGN_EXTEND_INREG: ExpandIntRes_SIGN_EXTEND_INREG(N, Lo, Hi); break;
2296 case ISD::SREM: ExpandIntRes_SREM(N, Lo, Hi); break;
2297 case ISD::TRUNCATE: ExpandIntRes_TRUNCATE(N, Lo, Hi); break;
2298 case ISD::UDIV: ExpandIntRes_UDIV(N, Lo, Hi); break;
2299 case ISD::UREM: ExpandIntRes_UREM(N, Lo, Hi); break;
2300 case ISD::ZERO_EXTEND: ExpandIntRes_ZERO_EXTEND(N, Lo, Hi); break;
2301 case ISD::ATOMIC_LOAD: ExpandIntRes_ATOMIC_LOAD(N, Lo, Hi); break;
2302
2303 case ISD::ATOMIC_LOAD_ADD:
2304 case ISD::ATOMIC_LOAD_SUB:
2305 case ISD::ATOMIC_LOAD_AND:
2306 case ISD::ATOMIC_LOAD_CLR:
2307 case ISD::ATOMIC_LOAD_OR:
2308 case ISD::ATOMIC_LOAD_XOR:
2309 case ISD::ATOMIC_LOAD_NAND:
2310 case ISD::ATOMIC_LOAD_MIN:
2311 case ISD::ATOMIC_LOAD_MAX:
2312 case ISD::ATOMIC_LOAD_UMIN:
2313 case ISD::ATOMIC_LOAD_UMAX:
2314 case ISD::ATOMIC_SWAP:
2315 case ISD::ATOMIC_CMP_SWAP: {
2316 std::pair<SDValue, SDValue> Tmp = ExpandAtomic(N);
2317 SplitInteger(Tmp.first, Lo, Hi);
2318 ReplaceValueWith(SDValue(N, 1), Tmp.second);
2319 break;
2320 }
2321 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: {
2322 AtomicSDNode *AN = cast<AtomicSDNode>(N);
2323 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::Other);
2324 SDValue Tmp = DAG.getAtomicCmpSwap(
2325 ISD::ATOMIC_CMP_SWAP, SDLoc(N), AN->getMemoryVT(), VTs,
2326 N->getOperand(0), N->getOperand(1), N->getOperand(2), N->getOperand(3),
2327 AN->getMemOperand());
2328
2329 // Expanding to the strong ATOMIC_CMP_SWAP node means we can determine
2330 // success simply by comparing the loaded value against the ingoing
2331 // comparison.
2332 SDValue Success = DAG.getSetCC(SDLoc(N), N->getValueType(1), Tmp,
2333 N->getOperand(2), ISD::SETEQ);
2334
2335 SplitInteger(Tmp, Lo, Hi);
2336 ReplaceValueWith(SDValue(N, 1), Success);
2337 ReplaceValueWith(SDValue(N, 2), Tmp.getValue(1));
2338 break;
2339 }
2340
2341 case ISD::AND:
2342 case ISD::OR:
2343 case ISD::XOR: ExpandIntRes_Logical(N, Lo, Hi); break;
2344
2345 case ISD::UMAX:
2346 case ISD::SMAX:
2347 case ISD::UMIN:
2348 case ISD::SMIN: ExpandIntRes_MINMAX(N, Lo, Hi); break;
2349
2350 case ISD::ADD:
2351 case ISD::SUB: ExpandIntRes_ADDSUB(N, Lo, Hi); break;
2352
2353 case ISD::ADDC:
2354 case ISD::SUBC: ExpandIntRes_ADDSUBC(N, Lo, Hi); break;
2355
2356 case ISD::ADDE:
2357 case ISD::SUBE: ExpandIntRes_ADDSUBE(N, Lo, Hi); break;
2358
2359 case ISD::ADDCARRY:
2360 case ISD::SUBCARRY: ExpandIntRes_ADDSUBCARRY(N, Lo, Hi); break;
2361
2362 case ISD::SADDO_CARRY:
2363 case ISD::SSUBO_CARRY: ExpandIntRes_SADDSUBO_CARRY(N, Lo, Hi); break;
2364
2365 case ISD::SHL:
2366 case ISD::SRA:
2367 case ISD::SRL: ExpandIntRes_Shift(N, Lo, Hi); break;
6
Calling 'DAGTypeLegalizer::ExpandIntRes_Shift'
2368
2369 case ISD::SADDO:
2370 case ISD::SSUBO: ExpandIntRes_SADDSUBO(N, Lo, Hi); break;
2371 case ISD::UADDO:
2372 case ISD::USUBO: ExpandIntRes_UADDSUBO(N, Lo, Hi); break;
2373 case ISD::UMULO:
2374 case ISD::SMULO: ExpandIntRes_XMULO(N, Lo, Hi); break;
2375
2376 case ISD::SADDSAT:
2377 case ISD::UADDSAT:
2378 case ISD::SSUBSAT:
2379 case ISD::USUBSAT: ExpandIntRes_ADDSUBSAT(N, Lo, Hi); break;
2380
2381 case ISD::SSHLSAT:
2382 case ISD::USHLSAT: ExpandIntRes_SHLSAT(N, Lo, Hi); break;
2383
2384 case ISD::SMULFIX:
2385 case ISD::SMULFIXSAT:
2386 case ISD::UMULFIX:
2387 case ISD::UMULFIXSAT: ExpandIntRes_MULFIX(N, Lo, Hi); break;
2388
2389 case ISD::SDIVFIX:
2390 case ISD::SDIVFIXSAT:
2391 case ISD::UDIVFIX:
2392 case ISD::UDIVFIXSAT: ExpandIntRes_DIVFIX(N, Lo, Hi); break;
2393
2394 case ISD::VECREDUCE_ADD:
2395 case ISD::VECREDUCE_MUL:
2396 case ISD::VECREDUCE_AND:
2397 case ISD::VECREDUCE_OR:
2398 case ISD::VECREDUCE_XOR:
2399 case ISD::VECREDUCE_SMAX:
2400 case ISD::VECREDUCE_SMIN:
2401 case ISD::VECREDUCE_UMAX:
2402 case ISD::VECREDUCE_UMIN: ExpandIntRes_VECREDUCE(N, Lo, Hi); break;
2403
2404 case ISD::ROTL:
2405 case ISD::ROTR:
2406 ExpandIntRes_Rotate(N, Lo, Hi);
2407 break;
2408
2409 case ISD::FSHL:
2410 case ISD::FSHR:
2411 ExpandIntRes_FunnelShift(N, Lo, Hi);
2412 break;
2413
2414 case ISD::VSCALE:
2415 ExpandIntRes_VSCALE(N, Lo, Hi);
2416 break;
2417 }
2418
2419 // If Lo/Hi is null, the sub-method took care of registering results etc.
2420 if (Lo.getNode())
2421 SetExpandedInteger(SDValue(N, ResNo), Lo, Hi);
2422}
2423
2424/// Lower an atomic node to the appropriate builtin call.
2425std::pair <SDValue, SDValue> DAGTypeLegalizer::ExpandAtomic(SDNode *Node) {
2426 unsigned Opc = Node->getOpcode();
2427 MVT VT = cast<AtomicSDNode>(Node)->getMemoryVT().getSimpleVT();
2428 AtomicOrdering order = cast<AtomicSDNode>(Node)->getMergedOrdering();
2429 // Lower to outline atomic libcall if outline atomics enabled,
2430 // or to sync libcall otherwise
2431 RTLIB::Libcall LC = RTLIB::getOUTLINE_ATOMIC(Opc, order, VT);
2432 EVT RetVT = Node->getValueType(0);
2433 TargetLowering::MakeLibCallOptions CallOptions;
2434 SmallVector<SDValue, 4> Ops;
2435 if (TLI.getLibcallName(LC)) {
2436 Ops.append(Node->op_begin() + 2, Node->op_end());
2437 Ops.push_back(Node->getOperand(1));
2438 } else {
2439 LC = RTLIB::getSYNC(Opc, VT);
2440 assert(LC != RTLIB::UNKNOWN_LIBCALL &&(static_cast <bool> (LC != RTLIB::UNKNOWN_LIBCALL &&
"Unexpected atomic op or value type!") ? void (0) : __assert_fail
("LC != RTLIB::UNKNOWN_LIBCALL && \"Unexpected atomic op or value type!\""
, "llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp", 2441
, __extension__ __PRETTY_FUNCTION__))
2441 "Unexpected atomic op or value type!")(static_cast <bool> (LC != RTLIB::UNKNOWN_LIBCALL &&
"Unexpected atomic op or value type!") ? void (0) : __assert_fail
("LC != RTLIB::UNKNOWN_LIBCALL && \"Unexpected atomic op or value type!\""
, "llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp", 2441
, __extension__ __PRETTY_FUNCTION__))
;
2442 Ops.append(Node->op_begin() + 1, Node->op_end());
2443 }
2444 return TLI.makeLibCall(DAG, LC, RetVT, Ops, CallOptions, SDLoc(Node),
2445 Node->getOperand(0));
2446}
2447
2448/// N is a shift by a value that needs to be expanded,
2449/// and the shift amount is a constant 'Amt'. Expand the operation.
2450void DAGTypeLegalizer::ExpandShiftByConstant(SDNode *N, const APInt &Amt,
2451 SDValue &Lo, SDValue &Hi) {
2452 SDLoc DL(N);
2453 // Expand the incoming operand to be shifted, so that we have its parts
2454 SDValue InL, InH;
2455 GetExpandedInteger(N->getOperand(0), InL, InH);
2456
2457 // Though Amt shouldn't usually be 0, it's possible. E.g. when legalization
2458 // splitted a vector shift, like this: <op1, op2> SHL <0, 2>.
2459 if (!Amt) {
2460 Lo = InL;
2461 Hi = InH;
2462 return;
2463 }
2464
2465 EVT NVT = InL.getValueType();
2466 unsigned VTBits = N->getValueType(0).getSizeInBits();
2467 unsigned NVTBits = NVT.getSizeInBits();
2468 EVT ShTy = N->getOperand(1).getValueType();
2469
2470 if (N->getOpcode() == ISD::SHL) {
2471 if (Amt.ugt(VTBits)) {
2472 Lo = Hi = DAG.getConstant(0, DL, NVT);
2473 } else if (Amt.ugt(NVTBits)) {
2474 Lo = DAG.getConstant(0, DL, NVT);
2475 Hi = DAG.getNode(ISD::SHL, DL,
2476 NVT, InL, DAG.getConstant(Amt - NVTBits, DL, ShTy));
2477 } else if (Amt == NVTBits) {
2478 Lo = DAG.getConstant(0, DL, NVT);
2479 Hi = InL;
2480 } else {
2481 Lo = DAG.getNode(ISD::SHL, DL, NVT, InL, DAG.getConstant(Amt, DL, ShTy));
2482 Hi = DAG.getNode(ISD::OR, DL, NVT,
2483 DAG.getNode(ISD::SHL, DL, NVT, InH,
2484 DAG.getConstant(Amt, DL, ShTy)),
2485 DAG.getNode(ISD::SRL, DL, NVT, InL,
2486 DAG.getConstant(-Amt + NVTBits, DL, ShTy)));
2487 }
2488 return;
2489 }
2490
2491 if (N->getOpcode() == ISD::SRL) {
2492 if (Amt.ugt(VTBits)) {
2493 Lo = Hi = DAG.getConstant(0, DL, NVT);
2494 } else if (Amt.ugt(NVTBits)) {
2495 Lo = DAG.getNode(ISD::SRL, DL,
2496 NVT, InH, DAG.getConstant(Amt - NVTBits, DL, ShTy));
2497 Hi = DAG.getConstant(0, DL, NVT);
2498 } else if (Amt == NVTBits) {
2499 Lo = InH;
2500 Hi = DAG.getConstant(0, DL, NVT);
2501 } else {
2502 Lo = DAG.getNode(ISD::OR, DL, NVT,
2503 DAG.getNode(ISD::SRL, DL, NVT, InL,
2504 DAG.getConstant(Amt, DL, ShTy)),
2505 DAG.getNode(ISD::SHL, DL, NVT, InH,
2506 DAG.getConstant(-Amt + NVTBits, DL, ShTy)));
2507 Hi = DAG.getNode(ISD::SRL, DL, NVT, InH, DAG.getConstant(Amt, DL, ShTy));
2508 }
2509 return;
2510 }
2511
2512 assert(N->getOpcode() == ISD::SRA && "Unknown shift!")(static_cast <bool> (N->getOpcode() == ISD::SRA &&
"Unknown shift!") ? void (0) : __assert_fail ("N->getOpcode() == ISD::SRA && \"Unknown shift!\""
, "llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp", 2512
, __extension__ __PRETTY_FUNCTION__))
;
2513 if (Amt.ugt(VTBits)) {
2514 Hi = Lo = DAG.getNode(ISD::SRA, DL, NVT, InH,
2515 DAG.getConstant(NVTBits - 1, DL, ShTy));
2516 } else if (Amt.ugt(NVTBits)) {
2517 Lo = DAG.getNode(ISD::SRA, DL, NVT, InH,
2518 DAG.getConstant(Amt - NVTBits, DL, ShTy));
2519 Hi = DAG.getNode(ISD::SRA, DL, NVT, InH,
2520 DAG.getConstant(NVTBits - 1, DL, ShTy));
2521 } else if (Amt == NVTBits) {
2522 Lo = InH;
2523 Hi = DAG.getNode(ISD::SRA, DL, NVT, InH,
2524 DAG.getConstant(NVTBits - 1, DL, ShTy));
2525 } else {
2526 Lo = DAG.getNode(ISD::OR, DL, NVT,
2527 DAG.getNode(ISD::SRL, DL, NVT, InL,
2528 DAG.getConstant(Amt, DL, ShTy)),
2529 DAG.getNode(ISD::SHL, DL, NVT, InH,
2530 DAG.getConstant(-Amt + NVTBits, DL, ShTy)));
2531 Hi = DAG.getNode(ISD::SRA, DL, NVT, InH, DAG.getConstant(Amt, DL, ShTy));
2532 }
2533}
2534
2535/// ExpandShiftWithKnownAmountBit - Try to determine whether we can simplify
2536/// this shift based on knowledge of the high bit of the shift amount. If we
2537/// can tell this, we know that it is >= 32 or < 32, without knowing the actual
2538/// shift amount.
2539bool DAGTypeLegalizer::
2540ExpandShiftWithKnownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) {
2541 SDValue Amt = N->getOperand(1);
10
Value assigned to 'Amt.Node'
2542 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2543 EVT ShTy = Amt.getValueType();
11
Calling 'SDValue::getValueType'
2544 unsigned ShBits = ShTy.getScalarSizeInBits();
2545 unsigned NVTBits = NVT.getScalarSizeInBits();
2546 assert(isPowerOf2_32(NVTBits) &&(static_cast <bool> (isPowerOf2_32(NVTBits) && "Expanded integer type size not a power of two!"
) ? void (0) : __assert_fail ("isPowerOf2_32(NVTBits) && \"Expanded integer type size not a power of two!\""
, "llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp", 2547
, __extension__ __PRETTY_FUNCTION__))
2547 "Expanded integer type size not a power of two!")(static_cast <bool> (isPowerOf2_32(NVTBits) && "Expanded integer type size not a power of two!"
) ? void (0) : __assert_fail ("isPowerOf2_32(NVTBits) && \"Expanded integer type size not a power of two!\""
, "llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp", 2547
, __extension__ __PRETTY_FUNCTION__))
;
2548 SDLoc dl(N);
2549
2550 APInt HighBitMask = APInt::getHighBitsSet(ShBits, ShBits - Log2_32(NVTBits));
2551 KnownBits Known = DAG.computeKnownBits(N->getOperand(1));
2552
2553 // If we don't know anything about the high bits, exit.
2554 if (((Known.Zero|Known.One) & HighBitMask) == 0)
2555 return false;
2556
2557 // Get the incoming operand to be shifted.
2558 SDValue InL, InH;
2559 GetExpandedInteger(N->getOperand(0), InL, InH);
2560
2561 // If we know that any of the high bits of the shift amount are one, then we
2562 // can do this as a couple of simple shifts.
2563 if (Known.One.intersects(HighBitMask)) {
2564 // Mask out the high bit, which we know is set.
2565 Amt = DAG.getNode(ISD::AND, dl, ShTy, Amt,
2566 DAG.getConstant(~HighBitMask, dl, ShTy));
2567
2568 switch (N->getOpcode()) {
2569 default: llvm_unreachable("Unknown shift")::llvm::llvm_unreachable_internal("Unknown shift", "llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 2569)
;
2570 case ISD::SHL:
2571 Lo = DAG.getConstant(0, dl, NVT); // Low part is zero.
2572 Hi = DAG.getNode(ISD::SHL, dl, NVT, InL, Amt); // High part from Lo part.
2573 return true;
2574 case ISD::SRL:
2575 Hi = DAG.getConstant(0, dl, NVT); // Hi part is zero.
2576 Lo = DAG.getNode(ISD::SRL, dl, NVT, InH, Amt); // Lo part from Hi part.
2577 return true;
2578 case ISD::SRA:
2579 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH, // Sign extend high part.
2580 DAG.getConstant(NVTBits - 1, dl, ShTy));
2581 Lo = DAG.getNode(ISD::SRA, dl, NVT, InH, Amt); // Lo part from Hi part.
2582 return true;
2583 }
2584 }
2585
2586 // If we know that all of the high bits of the shift amount are zero, then we
2587 // can do this as a couple of simple shifts.
2588 if (HighBitMask.isSubsetOf(Known.Zero)) {
2589 // Calculate 31-x. 31 is used instead of 32 to avoid creating an undefined
2590 // shift if x is zero. We can use XOR here because x is known to be smaller
2591 // than 32.
2592 SDValue Amt2 = DAG.getNode(ISD::XOR, dl, ShTy, Amt,
2593 DAG.getConstant(NVTBits - 1, dl, ShTy));
2594
2595 unsigned Op1, Op2;
2596 switch (N->getOpcode()) {
2597 default: llvm_unreachable("Unknown shift")::llvm::llvm_unreachable_internal("Unknown shift", "llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 2597)
;
2598 case ISD::SHL: Op1 = ISD::SHL; Op2 = ISD::SRL; break;
2599 case ISD::SRL:
2600 case ISD::SRA: Op1 = ISD::SRL; Op2 = ISD::SHL; break;
2601 }
2602
2603 // When shifting right the arithmetic for Lo and Hi is swapped.
2604 if (N->getOpcode() != ISD::SHL)
2605 std::swap(InL, InH);
2606
2607 // Use a little trick to get the bits that move from Lo to Hi. First
2608 // shift by one bit.
2609 SDValue Sh1 = DAG.getNode(Op2, dl, NVT, InL, DAG.getConstant(1, dl, ShTy));
2610 // Then compute the remaining shift with amount-1.
2611 SDValue Sh2 = DAG.getNode(Op2, dl, NVT, Sh1, Amt2);
2612
2613 Lo = DAG.getNode(N->getOpcode(), dl, NVT, InL, Amt);
2614 Hi = DAG.getNode(ISD::OR, dl, NVT, DAG.getNode(Op1, dl, NVT, InH, Amt),Sh2);
2615
2616 if (N->getOpcode() != ISD::SHL)
2617 std::swap(Hi, Lo);
2618 return true;
2619 }
2620
2621 return false;
2622}
2623
2624/// ExpandShiftWithUnknownAmountBit - Fully general expansion of integer shift
2625/// of any size.
2626bool DAGTypeLegalizer::
2627ExpandShiftWithUnknownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) {
2628 SDValue Amt = N->getOperand(1);
2629 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2630 EVT ShTy = Amt.getValueType();
2631 unsigned NVTBits = NVT.getSizeInBits();
2632 assert(isPowerOf2_32(NVTBits) &&(static_cast <bool> (isPowerOf2_32(NVTBits) && "Expanded integer type size not a power of two!"
) ? void (0) : __assert_fail ("isPowerOf2_32(NVTBits) && \"Expanded integer type size not a power of two!\""
, "llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp", 2633
, __extension__ __PRETTY_FUNCTION__))
2633 "Expanded integer type size not a power of two!")(static_cast <bool> (isPowerOf2_32(NVTBits) && "Expanded integer type size not a power of two!"
) ? void (0) : __assert_fail ("isPowerOf2_32(NVTBits) && \"Expanded integer type size not a power of two!\""
, "llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp", 2633
, __extension__ __PRETTY_FUNCTION__))
;
2634 SDLoc dl(N);
2635
2636 // Get the incoming operand to be shifted.
2637 SDValue InL, InH;
2638 GetExpandedInteger(N->getOperand(0), InL, InH);
2639
2640 SDValue NVBitsNode = DAG.getConstant(NVTBits, dl, ShTy);
2641 SDValue AmtExcess = DAG.getNode(ISD::SUB, dl, ShTy, Amt, NVBitsNode);
2642 SDValue AmtLack = DAG.getNode(ISD::SUB, dl, ShTy, NVBitsNode, Amt);
2643 SDValue isShort = DAG.getSetCC(dl, getSetCCResultType(ShTy),
2644 Amt, NVBitsNode, ISD::SETULT);
2645 SDValue isZero = DAG.getSetCC(dl, getSetCCResultType(ShTy),
2646 Amt, DAG.getConstant(0, dl, ShTy),
2647 ISD::SETEQ);
2648
2649 SDValue LoS, HiS, LoL, HiL;
2650 switch (N->getOpcode()) {
2651 default: llvm_unreachable("Unknown shift")::llvm::llvm_unreachable_internal("Unknown shift", "llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 2651)
;
2652 case ISD::SHL:
2653 // Short: ShAmt < NVTBits
2654 LoS = DAG.getNode(ISD::SHL, dl, NVT, InL, Amt);
2655 HiS = DAG.getNode(ISD::OR, dl, NVT,
2656 DAG.getNode(ISD::SHL, dl, NVT, InH, Amt),
2657 DAG.getNode(ISD::SRL, dl, NVT, InL, AmtLack));
2658
2659 // Long: ShAmt >= NVTBits
2660 LoL = DAG.getConstant(0, dl, NVT); // Lo part is zero.
2661 HiL = DAG.getNode(ISD::SHL, dl, NVT, InL, AmtExcess); // Hi from Lo part.
2662
2663 Lo = DAG.getSelect(dl, NVT, isShort, LoS, LoL);
2664 Hi = DAG.getSelect(dl, NVT, isZero, InH,
2665 DAG.getSelect(dl, NVT, isShort, HiS, HiL));
2666 return true;
2667 case ISD::SRL:
2668 // Short: ShAmt < NVTBits
2669 HiS = DAG.getNode(ISD::SRL, dl, NVT, InH, Amt);
2670 LoS = DAG.getNode(ISD::OR, dl, NVT,
2671 DAG.getNode(ISD::SRL, dl, NVT, InL, Amt),
2672 // FIXME: If Amt is zero, the following shift generates an undefined result
2673 // on some architectures.
2674 DAG.getNode(ISD::SHL, dl, NVT, InH, AmtLack));
2675
2676 // Long: ShAmt >= NVTBits
2677 HiL = DAG.getConstant(0, dl, NVT); // Hi part is zero.
2678 LoL = DAG.getNode(ISD::SRL, dl, NVT, InH, AmtExcess); // Lo from Hi part.
2679
2680 Lo = DAG.getSelect(dl, NVT, isZero, InL,
2681 DAG.getSelect(dl, NVT, isShort, LoS, LoL));
2682 Hi = DAG.getSelect(dl, NVT, isShort, HiS, HiL);
2683 return true;
2684 case ISD::SRA:
2685 // Short: ShAmt < NVTBits
2686 HiS = DAG.getNode(ISD::SRA, dl, NVT, InH, Amt);
2687 LoS = DAG.getNode(ISD::OR, dl, NVT,
2688 DAG.getNode(ISD::SRL, dl, NVT, InL, Amt),
2689 DAG.getNode(ISD::SHL, dl, NVT, InH, AmtLack));
2690
2691 // Long: ShAmt >= NVTBits
2692 HiL = DAG.getNode(ISD::SRA, dl, NVT, InH, // Sign of Hi part.
2693 DAG.getConstant(NVTBits - 1, dl, ShTy));
2694 LoL = DAG.getNode(ISD::SRA, dl, NVT, InH, AmtExcess); // Lo from Hi part.
2695
2696 Lo = DAG.getSelect(dl, NVT, isZero, InL,
2697 DAG.getSelect(dl, NVT, isShort, LoS, LoL));
2698 Hi = DAG.getSelect(dl, NVT, isShort, HiS, HiL);
2699 return true;
2700 }
2701}
2702
2703static std::pair<ISD::CondCode, ISD::NodeType> getExpandedMinMaxOps(int Op) {
2704
2705 switch (Op) {
2706 default: llvm_unreachable("invalid min/max opcode")::llvm::llvm_unreachable_internal("invalid min/max opcode", "llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 2706)
;
2707 case ISD::SMAX:
2708 return std::make_pair(ISD::SETGT, ISD::UMAX);
2709 case ISD::UMAX:
2710 return std::make_pair(ISD::SETUGT, ISD::UMAX);
2711 case ISD::SMIN:
2712 return std::make_pair(ISD::SETLT, ISD::UMIN);
2713 case ISD::UMIN:
2714 return std::make_pair(ISD::SETULT, ISD::UMIN);
2715 }
2716}
2717
2718void DAGTypeLegalizer::ExpandIntRes_MINMAX(SDNode *N,
2719 SDValue &Lo, SDValue &Hi) {
2720 SDLoc DL(N);
2721 ISD::NodeType LoOpc;
2722 ISD::CondCode CondC;
2723 std::tie(CondC, LoOpc) = getExpandedMinMaxOps(N->getOpcode());
2724
2725 // Expand the subcomponents.
2726 SDValue LHSL, LHSH, RHSL, RHSH;
2727 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
2728 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
2729
2730 // Value types
2731 EVT NVT = LHSL.getValueType();
2732 EVT CCT = getSetCCResultType(NVT);
2733
2734 // Hi part is always the same op
2735 Hi = DAG.getNode(N->getOpcode(), DL, NVT, {LHSH, RHSH});
2736
2737 // We need to know whether to select Lo part that corresponds to 'winning'
2738 // Hi part or if Hi parts are equal.
2739 SDValue IsHiLeft = DAG.getSetCC(DL, CCT, LHSH, RHSH, CondC);
2740 SDValue IsHiEq = DAG.getSetCC(DL, CCT, LHSH, RHSH, ISD::SETEQ);
2741
2742 // Lo part corresponding to the 'winning' Hi part
2743 SDValue LoCmp = DAG.getSelect(DL, NVT, IsHiLeft, LHSL, RHSL);
2744
2745 // Recursed Lo part if Hi parts are equal, this uses unsigned version
2746 SDValue LoMinMax = DAG.getNode(LoOpc, DL, NVT, {LHSL, RHSL});
2747
2748 Lo = DAG.getSelect(DL, NVT, IsHiEq, LoMinMax, LoCmp);
2749}
2750
2751void DAGTypeLegalizer::ExpandIntRes_ADDSUB(SDNode *N,
2752 SDValue &Lo, SDValue &Hi) {
2753 SDLoc dl(N);
2754 // Expand the subcomponents.
2755 SDValue LHSL, LHSH, RHSL, RHSH;
2756 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
2757 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
2758
2759 EVT NVT = LHSL.getValueType();
2760 SDValue LoOps[2] = { LHSL, RHSL };
2761 SDValue HiOps[3] = { LHSH, RHSH };
2762
2763 bool HasOpCarry = TLI.isOperationLegalOrCustom(
2764 N->getOpcode() == ISD::ADD ? ISD::ADDCARRY : ISD::SUBCARRY,
2765 TLI.getTypeToExpandTo(*DAG.getContext(), NVT));
2766 if (HasOpCarry) {
2767 SDVTList VTList = DAG.getVTList(NVT, getSetCCResultType(NVT));
2768 if (N->getOpcode() == ISD::ADD) {
2769 Lo = DAG.getNode(ISD::UADDO, dl, VTList, LoOps);
2770 HiOps[2] = Lo.getValue(1);
2771 Hi = DAG.getNode(ISD::ADDCARRY, dl, VTList, HiOps);
2772 } else {
2773 Lo = DAG.getNode(ISD::USUBO, dl, VTList, LoOps);
2774 HiOps[2] = Lo.getValue(1);
2775 Hi = DAG.getNode(ISD::SUBCARRY, dl, VTList, HiOps);
2776 }
2777 return;
2778 }
2779
2780 // Do not generate ADDC/ADDE or SUBC/SUBE if the target does not support
2781 // them. TODO: Teach operation legalization how to expand unsupported
2782 // ADDC/ADDE/SUBC/SUBE. The problem is that these operations generate
2783 // a carry of type MVT::Glue, but there doesn't seem to be any way to
2784 // generate a value of this type in the expanded code sequence.
2785 bool hasCarry =
2786 TLI.isOperationLegalOrCustom(N->getOpcode() == ISD::ADD ?
2787 ISD::ADDC : ISD::SUBC,
2788 TLI.getTypeToExpandTo(*DAG.getContext(), NVT));
2789
2790 if (hasCarry) {
2791 SDVTList VTList = DAG.getVTList(NVT, MVT::Glue);
2792 if (N->getOpcode() == ISD::ADD) {
2793 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps);
2794 HiOps[2] = Lo.getValue(1);
2795 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps);
2796 } else {
2797 Lo = DAG.getNode(ISD::SUBC, dl, VTList, LoOps);
2798 HiOps[2] = Lo.getValue(1);
2799 Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps);
2800 }
2801 return;
2802 }
2803
2804 bool hasOVF =
2805 TLI.isOperationLegalOrCustom(N->getOpcode() == ISD::ADD ?
2806 ISD::UADDO : ISD::USUBO,
2807 TLI.getTypeToExpandTo(*DAG.getContext(), NVT));
2808 TargetLoweringBase::BooleanContent BoolType = TLI.getBooleanContents(NVT);
2809
2810 if (hasOVF) {
2811 EVT OvfVT = getSetCCResultType(NVT);
2812 SDVTList VTList = DAG.getVTList(NVT, OvfVT);
2813 int RevOpc;
2814 if (N->getOpcode() == ISD::ADD) {
2815 RevOpc = ISD::SUB;
2816 Lo = DAG.getNode(ISD::UADDO, dl, VTList, LoOps);
2817 Hi = DAG.getNode(ISD::ADD, dl, NVT, makeArrayRef(HiOps, 2));
2818 } else {
2819 RevOpc = ISD::ADD;
2820 Lo = DAG.getNode(ISD::USUBO, dl, VTList, LoOps);
2821 Hi = DAG.getNode(ISD::SUB, dl, NVT, makeArrayRef(HiOps, 2));
2822 }
2823 SDValue OVF = Lo.getValue(1);
2824
2825 switch (BoolType) {
2826 case TargetLoweringBase::UndefinedBooleanContent:
2827 OVF = DAG.getNode(ISD::AND, dl, OvfVT, DAG.getConstant(1, dl, OvfVT), OVF);
2828 LLVM_FALLTHROUGH[[gnu::fallthrough]];
2829 case TargetLoweringBase::ZeroOrOneBooleanContent:
2830 OVF = DAG.getZExtOrTrunc(OVF, dl, NVT);
2831 Hi = DAG.getNode(N->getOpcode(), dl, NVT, Hi, OVF);
2832 break;
2833 case TargetLoweringBase::ZeroOrNegativeOneBooleanContent:
2834 OVF = DAG.getSExtOrTrunc(OVF, dl, NVT);
2835 Hi = DAG.getNode(RevOpc, dl, NVT, Hi, OVF);
2836 }
2837 return;
2838 }
2839
2840 if (N->getOpcode() == ISD::ADD) {
2841 Lo = DAG.getNode(ISD::ADD, dl, NVT, LoOps);
2842 Hi = DAG.getNode(ISD::ADD, dl, NVT, makeArrayRef(HiOps, 2));
2843 SDValue Cmp1 = DAG.getSetCC(dl, getSetCCResultType(NVT), Lo, LoOps[0],
2844 ISD::SETULT);
2845
2846 if (BoolType == TargetLoweringBase::ZeroOrOneBooleanContent) {
2847 SDValue Carry = DAG.getZExtOrTrunc(Cmp1, dl, NVT);
2848 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, Carry);
2849 return;
2850 }
2851
2852 SDValue Carry1 = DAG.getSelect(dl, NVT, Cmp1,
2853 DAG.getConstant(1, dl, NVT),
2854 DAG.getConstant(0, dl, NVT));
2855 SDValue Cmp2 = DAG.getSetCC(dl, getSetCCResultType(NVT), Lo, LoOps[1],
2856 ISD::SETULT);
2857 SDValue Carry2 = DAG.getSelect(dl, NVT, Cmp2,
2858 DAG.getConstant(1, dl, NVT), Carry1);
2859 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, Carry2);
2860 } else {
2861 Lo = DAG.getNode(ISD::SUB, dl, NVT, LoOps);
2862 Hi = DAG.getNode(ISD::SUB, dl, NVT, makeArrayRef(HiOps, 2));
2863 SDValue Cmp =
2864 DAG.getSetCC(dl, getSetCCResultType(LoOps[0].getValueType()),
2865 LoOps[0], LoOps[1], ISD::SETULT);
2866
2867 SDValue Borrow;
2868 if (BoolType == TargetLoweringBase::ZeroOrOneBooleanContent)
2869 Borrow = DAG.getZExtOrTrunc(Cmp, dl, NVT);
2870 else
2871 Borrow = DAG.getSelect(dl, NVT, Cmp, DAG.getConstant(1, dl, NVT),
2872 DAG.getConstant(0, dl, NVT));
2873
2874 Hi = DAG.getNode(ISD::SUB, dl, NVT, Hi, Borrow);
2875 }
2876}
2877
2878void DAGTypeLegalizer::ExpandIntRes_ADDSUBC(SDNode *N,
2879 SDValue &Lo, SDValue &Hi) {
2880 // Expand the subcomponents.
2881 SDValue LHSL, LHSH, RHSL, RHSH;
2882 SDLoc dl(N);
2883 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
2884 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
2885 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Glue);
2886 SDValue LoOps[2] = { LHSL, RHSL };
2887 SDValue HiOps[3] = { LHSH, RHSH };
2888
2889 if (N->getOpcode() == ISD::ADDC) {
2890 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps);
2891 HiOps[2] = Lo.getValue(1);
2892 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps);
2893 } else {
2894 Lo = DAG.getNode(ISD::SUBC, dl, VTList, LoOps);
2895 HiOps[2] = Lo.getValue(1);
2896 Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps);
2897 }
2898
2899 // Legalized the flag result - switch anything that used the old flag to
2900 // use the new one.
2901 ReplaceValueWith(SDValue(N, 1), Hi.getValue(1));
2902}
2903
2904void DAGTypeLegalizer::ExpandIntRes_ADDSUBE(SDNode *N,
2905 SDValue &Lo, SDValue &Hi) {
2906 // Expand the subcomponents.
2907 SDValue LHSL, LHSH, RHSL, RHSH;
2908 SDLoc dl(N);
2909 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
2910 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
2911 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Glue);
2912 SDValue LoOps[3] = { LHSL, RHSL, N->getOperand(2) };
2913 SDValue HiOps[3] = { LHSH, RHSH };
2914
2915 Lo = DAG.getNode(N->getOpcode(), dl, VTList, LoOps);
2916 HiOps[2] = Lo.getValue(1);
2917 Hi = DAG.getNode(N->getOpcode(), dl, VTList, HiOps);
2918
2919 // Legalized the flag result - switch anything that used the old flag to
2920 // use the new one.
2921 ReplaceValueWith(SDValue(N, 1), Hi.getValue(1));
2922}
2923
2924void DAGTypeLegalizer::ExpandIntRes_UADDSUBO(SDNode *N,
2925 SDValue &Lo, SDValue &Hi) {
2926 SDValue LHS = N->getOperand(0);
2927 SDValue RHS = N->getOperand(1);
2928 SDLoc dl(N);
2929
2930 SDValue Ovf;
2931
2932 unsigned CarryOp, NoCarryOp;
2933 ISD::CondCode Cond;
2934 switch(N->getOpcode()) {
2935 case ISD::UADDO:
2936 CarryOp = ISD::ADDCARRY;
2937 NoCarryOp = ISD::ADD;
2938 Cond = ISD::SETULT;
2939 break;
2940 case ISD::USUBO:
2941 CarryOp = ISD::SUBCARRY;
2942 NoCarryOp = ISD::SUB;
2943 Cond = ISD::SETUGT;
2944 break;
2945 default:
2946 llvm_unreachable("Node has unexpected Opcode")::llvm::llvm_unreachable_internal("Node has unexpected Opcode"
, "llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp", 2946
)
;
2947 }
2948
2949 bool HasCarryOp = TLI.isOperationLegalOrCustom(
2950 CarryOp, TLI.getTypeToExpandTo(*DAG.getContext(), LHS.getValueType()));
2951
2952 if (HasCarryOp) {
2953 // Expand the subcomponents.
2954 SDValue LHSL, LHSH, RHSL, RHSH;
2955 GetExpandedInteger(LHS, LHSL, LHSH);
2956 GetExpandedInteger(RHS, RHSL, RHSH);
2957 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), N->getValueType(1));
2958 SDValue LoOps[2] = { LHSL, RHSL };
2959 SDValue HiOps[3] = { LHSH, RHSH };
2960
2961 Lo = DAG.getNode(N->getOpcode(), dl, VTList, LoOps);
2962 HiOps[2] = Lo.getValue(1);
2963 Hi = DAG.getNode(CarryOp, dl, VTList, HiOps);
2964
2965 Ovf = Hi.getValue(1);
2966 } else {
2967 // Expand the result by simply replacing it with the equivalent
2968 // non-overflow-checking operation.
2969 SDValue Sum = DAG.getNode(NoCarryOp, dl, LHS.getValueType(), LHS, RHS);
2970 SplitInteger(Sum, Lo, Hi);
2971
2972 // Calculate the overflow: addition overflows iff a + b < a, and subtraction
2973 // overflows iff a - b > a.
2974 Ovf = DAG.getSetCC(dl, N->getValueType(1), Sum, LHS, Cond);
2975 }
2976
2977 // Legalized the flag result - switch anything that used the old flag to
2978 // use the new one.
2979 ReplaceValueWith(SDValue(N, 1), Ovf);
2980}
2981
2982void DAGTypeLegalizer::ExpandIntRes_ADDSUBCARRY(SDNode *N,
2983 SDValue &Lo, SDValue &Hi) {
2984 // Expand the subcomponents.
2985 SDValue LHSL, LHSH, RHSL, RHSH;
2986 SDLoc dl(N);
2987 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
2988 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
2989 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), N->getValueType(1));
2990 SDValue LoOps[3] = { LHSL, RHSL, N->getOperand(2) };
2991 SDValue HiOps[3] = { LHSH, RHSH, SDValue() };
2992
2993 Lo = DAG.getNode(N->getOpcode(), dl, VTList, LoOps);
2994 HiOps[2] = Lo.getValue(1);
2995 Hi = DAG.getNode(N->getOpcode(), dl, VTList, HiOps);
2996
2997 // Legalized the flag result - switch anything that used the old flag to
2998 // use the new one.
2999 ReplaceValueWith(SDValue(N, 1), Hi.getValue(1));
3000}
3001
3002void DAGTypeLegalizer::ExpandIntRes_SADDSUBO_CARRY(SDNode *N,
3003 SDValue &Lo, SDValue &Hi) {
3004 // Expand the subcomponents.
3005 SDValue LHSL, LHSH, RHSL, RHSH;
3006 SDLoc dl(N);
3007 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
3008 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
3009 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), N->getValueType(1));
3010
3011 // We need to use an unsigned carry op for the lo part.
3012 unsigned CarryOp = N->getOpcode() == ISD::SADDO_CARRY ? ISD::ADDCARRY
3013 : ISD::SUBCARRY;
3014 Lo = DAG.getNode(CarryOp, dl, VTList, { LHSL, RHSL, N->getOperand(2) });
3015 Hi = DAG.getNode(N->getOpcode(), dl, VTList, { LHSH, RHSH, Lo.getValue(1) });
3016
3017 // Legalized the flag result - switch anything that used the old flag to
3018 // use the new one.
3019 ReplaceValueWith(SDValue(N, 1), Hi.getValue(1));
3020}
3021
3022void DAGTypeLegalizer::ExpandIntRes_ANY_EXTEND(SDNode *N,
3023 SDValue &Lo, SDValue &Hi) {
3024 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
3025 SDLoc dl(N);
3026 SDValue Op = N->getOperand(0);
3027 if (Op.getValueType().bitsLE(NVT)) {
3028 // The low part is any extension of the input (which degenerates to a copy).
3029 Lo = DAG.getNode(ISD::ANY_EXTEND, dl, NVT, Op);
3030 Hi = DAG.getUNDEF(NVT); // The high part is undefined.
3031 } else {
3032 // For example, extension of an i48 to an i64. The operand type necessarily
3033 // promotes to the result type, so will end up being expanded too.
3034 assert(getTypeAction(Op.getValueType()) ==(static_cast <bool> (getTypeAction(Op.getValueType()) ==
TargetLowering::TypePromoteInteger && "Only know how to promote this result!"
) ? void (0) : __assert_fail ("getTypeAction(Op.getValueType()) == TargetLowering::TypePromoteInteger && \"Only know how to promote this result!\""
, "llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp", 3036
, __extension__ __PRETTY_FUNCTION__))
3035 TargetLowering::TypePromoteInteger &&(static_cast <bool> (getTypeAction(Op.getValueType()) ==
TargetLowering::TypePromoteInteger && "Only know how to promote this result!"
) ? void (0) : __assert_fail ("getTypeAction(Op.getValueType()) == TargetLowering::TypePromoteInteger && \"Only know how to promote this result!\""
, "llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp", 3036
, __extension__ __PRETTY_FUNCTION__))
3036 "Only know how to promote this result!")(static_cast <bool> (getTypeAction(Op.getValueType()) ==
TargetLowering::TypePromoteInteger && "Only know how to promote this result!"
) ? void (0) : __assert_fail ("getTypeAction(Op.getValueType()) == TargetLowering::TypePromoteInteger && \"Only know how to promote this result!\""
, "llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp", 3036
, __extension__ __PRETTY_FUNCTION__))
;
3037 SDValue Res = GetPromotedInteger(Op);
3038 assert(Res.getValueType() == N->getValueType(0) &&(static_cast <bool> (Res.getValueType() == N->getValueType
(0) && "Operand over promoted?") ? void (0) : __assert_fail
("Res.getValueType() == N->getValueType(0) && \"Operand over promoted?\""
, "llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp", 3039
, __extension__ __PRETTY_FUNCTION__))
3039 "Operand over promoted?")(static_cast <bool> (Res.getValueType() == N->getValueType
(0) && "Operand over promoted?") ? void (0) : __assert_fail
("Res.getValueType() == N->getValueType(0) && \"Operand over promoted?\""
, "llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp", 3039
, __extension__ __PRETTY_FUNCTION__))
;
3040 // Split the promoted operand. This will simplify when it is expanded.
3041 SplitInteger(Res, Lo, Hi);
3042 }
3043}
3044
3045void DAGTypeLegalizer::ExpandIntRes_AssertSext(SDNode *N,
3046 SDValue &Lo, SDValue &Hi) {
3047 SDLoc dl(N);
3048 GetExpandedInteger(N->getOperand(0), Lo, Hi);
3049 EVT NVT = Lo.getValueType();
3050 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
3051 unsigned NVTBits = NVT.getSizeInBits();
3052 unsigned EVTBits = EVT.getSizeInBits();
3053
3054 if (NVTBits < EVTBits) {
3055 Hi = DAG.getNode(ISD::AssertSext, dl, NVT, Hi,
3056 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(),
3057 EVTBits - NVTBits)));
3058 } else {
3059 Lo = DAG.getNode(ISD::AssertSext, dl, NVT, Lo, DAG.getValueType(EVT));
3060 // The high part replicates the sign bit of Lo, make it explicit.
3061 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
3062 DAG.getConstant(NVTBits - 1, dl,
3063 TLI.getPointerTy(DAG.getDataLayout())));
3064 }
3065}
3066
3067void DAGTypeLegalizer::ExpandIntRes_AssertZext(SDNode *N,
3068 SDValue &Lo, SDValue &Hi) {
3069 SDLoc dl(N);
3070 GetExpandedInteger(N->getOperand(0), Lo, Hi);
3071 EVT NVT = Lo.getValueType();
3072 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
3073 unsigned NVTBits = NVT.getSizeInBits();
3074 unsigned EVTBits = EVT.getSizeInBits();
3075
3076 if (NVTBits < EVTBits) {
3077 Hi = DAG.getNode(ISD::AssertZext, dl, NVT, Hi,
3078 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(),
3079 EVTBits - NVTBits)));
3080 } else {
3081 Lo = DAG.getNode(ISD::AssertZext, dl, NVT, Lo, DAG.getValueType(EVT));
3082 // The high part must be zero, make it explicit.
3083 Hi = DAG.getConstant(0, dl, NVT);
3084 }
3085}
3086
3087void DAGTypeLegalizer::ExpandIntRes_BITREVERSE(SDNode *N,
3088 SDValue &Lo, SDValue &Hi) {
3089 SDLoc dl(N);
3090 GetExpandedInteger(N->getOperand(0), Hi, Lo); // Note swapped operands.
3091 Lo = DAG.getNode(ISD::BITREVERSE, dl, Lo.getValueType(), Lo);
3092 Hi = DAG.getNode(ISD::BITREVERSE, dl, Hi.getValueType(), Hi);
3093}
3094
3095void DAGTypeLegalizer::ExpandIntRes_BSWAP(SDNode *N,
3096 SDValue &Lo, SDValue &Hi) {
3097 SDLoc dl(N);
3098 GetExpandedInteger(N->getOperand(0), Hi, Lo); // Note swapped operands.
3099 Lo = DAG.getNode(ISD::BSWAP, dl, Lo.getValueType(), Lo);
3100 Hi = DAG.getNode(ISD::BSWAP, dl, Hi.getValueType(), Hi);
3101}
3102
3103void DAGTypeLegalizer::ExpandIntRes_PARITY(SDNode *N, SDValue &Lo,
3104 SDValue &Hi) {
3105 SDLoc dl(N);
3106 // parity(HiLo) -> parity(Lo^Hi)
3107 GetExpandedInteger(N->getOperand(0), Lo, Hi);
3108 EVT NVT = Lo.getValueType();
3109 Lo =
3110 DAG.getNode(ISD::PARITY, dl, NVT, DAG.getNode(ISD::XOR, dl, NVT, Lo, Hi));
3111 Hi = DAG.getConstant(0, dl, NVT);
3112}
3113
3114void DAGTypeLegalizer::ExpandIntRes_Constant(SDNode *N,
3115 SDValue &Lo, SDValue &Hi) {
3116 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
3117 unsigned NBitWidth = NVT.getSizeInBits();
3118 auto Constant = cast<ConstantSDNode>(N);
3119 const APInt &Cst = Constant->getAPIntValue();
3120 bool IsTarget = Constant->isTargetOpcode();
3121 bool IsOpaque = Constant->isOpaque();
3122 SDLoc dl(N);
3123 Lo = DAG.getConstant(Cst.trunc(NBitWidth), dl, NVT, IsTarget, IsOpaque);
3124 Hi = DAG.getConstant(Cst.lshr(NBitWidth).trunc(NBitWidth), dl, NVT, IsTarget,
3125 IsOpaque);
3126}
3127
3128void DAGTypeLegalizer::ExpandIntRes_ABS(SDNode *N, SDValue &Lo, SDValue &Hi) {
3129 SDLoc dl(N);
3130
3131 SDValue N0 = N->getOperand(0);
3132 GetExpandedInteger(N0, Lo, Hi);
3133 EVT NVT = Lo.getValueType();
3134
3135 // If we have ADDCARRY, use the expanded form of the sra+add+xor sequence we
3136 // use in LegalizeDAG. The ADD part of the expansion is based on
3137 // ExpandIntRes_ADDSUB which also uses ADDCARRY/UADDO after checking that
3138 // ADDCARRY is LegalOrCustom. Each of the pieces here can be further expanded
3139 // if needed. Shift expansion has a special case for filling with sign bits
3140 // so that we will only end up with one SRA.
3141 bool HasAddCarry = TLI.isOperationLegalOrCustom(
3142 ISD::ADDCARRY, TLI.getTypeToExpandTo(*DAG.getContext(), NVT));
3143 if (HasAddCarry) {
3144 EVT ShiftAmtTy = TLI.getShiftAmountTy(NVT, DAG.getDataLayout());
3145 SDValue Sign =
3146 DAG.getNode(ISD::SRA, dl, NVT, Hi,
3147 DAG.getConstant(NVT.getSizeInBits() - 1, dl, ShiftAmtTy));
3148 SDVTList VTList = DAG.getVTList(NVT, getSetCCResultType(NVT));
3149 Lo = DAG.getNode(ISD::UADDO, dl, VTList, Lo, Sign);
3150 Hi = DAG.getNode(ISD::ADDCARRY, dl, VTList, Hi, Sign, Lo.getValue(1));
3151 Lo = DAG.getNode(ISD::XOR, dl, NVT, Lo, Sign);
3152 Hi = DAG.getNode(ISD::XOR, dl, NVT, Hi, Sign);
3153 return;
3154 }
3155
3156 // abs(HiLo) -> (Hi < 0 ? -HiLo : HiLo)
3157 EVT VT = N->getValueType(0);
3158 SDValue Neg = DAG.getNode(ISD::SUB, dl, VT,
3159 DAG.getConstant(0, dl, VT), N0);
3160 SDValue NegLo, NegHi;
3161 SplitInteger(Neg, NegLo, NegHi);
3162
3163 SDValue HiIsNeg = DAG.getSetCC(dl, getSetCCResultType(NVT),
3164 DAG.getConstant(0, dl, NVT), Hi, ISD::SETGT);
3165 Lo = DAG.getSelect(dl, NVT, HiIsNeg, NegLo, Lo);
3166 Hi = DAG.getSelect(dl, NVT, HiIsNeg, NegHi, Hi);
3167}
3168
3169void DAGTypeLegalizer::ExpandIntRes_CTLZ(SDNode *N,
3170 SDValue &Lo, SDValue &Hi) {
3171 SDLoc dl(N);
3172 // ctlz (HiLo) -> Hi != 0 ? ctlz(Hi) : (ctlz(Lo)+32)
3173 GetExpandedInteger(N->getOperand(0), Lo, Hi);
3174 EVT NVT = Lo.getValueType();
3175
3176 SDValue HiNotZero = DAG.getSetCC(dl, getSetCCResultType(NVT), Hi,
3177 DAG.getConstant(0, dl, NVT), ISD::SETNE);
3178
3179 SDValue LoLZ = DAG.getNode(N->getOpcode(), dl, NVT, Lo);
3180 SDValue HiLZ = DAG.getNode(ISD::CTLZ_ZERO_UNDEF, dl, NVT, Hi);
3181
3182 Lo = DAG.getSelect(dl, NVT, HiNotZero, HiLZ,
3183 DAG.getNode(ISD::ADD, dl, NVT, LoLZ,
3184 DAG.getConstant(NVT.getSizeInBits(), dl,
3185 NVT)));
3186 Hi = DAG.getConstant(0, dl, NVT);
3187}
3188
3189void DAGTypeLegalizer::ExpandIntRes_CTPOP(SDNode *N,
3190 SDValue &Lo, SDValue &Hi) {
3191 SDLoc dl(N);
3192 // ctpop(HiLo) -> ctpop(Hi)+ctpop(Lo)
3193 GetExpandedInteger(N->getOperand(0), Lo, Hi);
3194 EVT NVT = Lo.getValueType();
3195 Lo = DAG.getNode(ISD::ADD, dl, NVT, DAG.getNode(ISD::CTPOP, dl, NVT, Lo),
3196 DAG.getNode(ISD::CTPOP, dl, NVT, Hi));
3197 Hi = DAG.getConstant(0, dl, NVT);
3198}
3199
3200void DAGTypeLegalizer::ExpandIntRes_CTTZ(SDNode *N,
3201 SDValue &Lo, SDValue &Hi) {
3202 SDLoc dl(N);
3203 // cttz (HiLo) -> Lo != 0 ? cttz(Lo) : (cttz(Hi)+32)
3204 GetExpandedInteger(N->getOperand(0), Lo, Hi);
3205 EVT NVT = Lo.getValueType();
3206
3207 SDValue LoNotZero = DAG.getSetCC(dl, getSetCCResultType(NVT), Lo,
3208 DAG.getConstant(0, dl, NVT), ISD::SETNE);
3209
3210 SDValue LoLZ = DAG.getNode(ISD::CTTZ_ZERO_UNDEF, dl, NVT, Lo);
3211 SDValue HiLZ = DAG.getNode(N->getOpcode(), dl, NVT, Hi);
3212
3213 Lo = DAG.getSelect(dl, NVT, LoNotZero, LoLZ,
3214 DAG.getNode(ISD::ADD, dl, NVT, HiLZ,
3215 DAG.getConstant(NVT.getSizeInBits(), dl,
3216 NVT)));
3217 Hi = DAG.getConstant(0, dl, NVT);
3218}
3219
3220void DAGTypeLegalizer::ExpandIntRes_FLT_ROUNDS(SDNode *N, SDValue &Lo,
3221 SDValue &Hi) {
3222 SDLoc dl(N);
3223 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
3224 unsigned NBitWidth = NVT.getSizeInBits();
3225
3226 EVT ShiftAmtTy = TLI.getShiftAmountTy(NVT, DAG.getDataLayout());
3227 Lo = DAG.getNode(ISD::FLT_ROUNDS_, dl, {NVT, MVT::Other}, N->getOperand(0));
3228 SDValue Chain = Lo.getValue(1);
3229 // The high part is the sign of Lo, as -1 is a valid value for FLT_ROUNDS
3230 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
3231 DAG.getConstant(NBitWidth - 1, dl, ShiftAmtTy));
3232
3233 // Legalize the chain result - switch anything that used the old chain to
3234 // use the new one.
3235 ReplaceValueWith(SDValue(N, 1), Chain);
3236}
3237
3238void DAGTypeLegalizer::ExpandIntRes_FP_TO_SINT(SDNode *N, SDValue &Lo,
3239 SDValue &Hi) {
3240 SDLoc dl(N);
3241 EVT VT = N->getValueType(0);
3242
3243 bool IsStrict = N->isStrictFPOpcode();
3244 SDValue Chain = IsStrict ? N->getOperand(0) : SDValue();
3245 SDValue Op = N->getOperand(IsStrict ? 1 : 0);
3246 if (getTypeAction(Op.getValueType()) == TargetLowering::TypePromoteFloat)
3247 Op = GetPromotedFloat(Op);
3248
3249 if (getTypeAction(Op.getValueType()) == TargetLowering::TypeSoftPromoteHalf) {
3250 EVT NFPVT = TLI.getTypeToTransformTo(*DAG.getContext(), Op.getValueType());
3251 Op = GetSoftPromotedHalf(Op);
3252 Op = DAG.getNode(ISD::FP16_TO_FP, dl, NFPVT, Op);
3253 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
3254 SplitInteger(Op, Lo, Hi);
3255 return;
3256 }
3257
3258 RTLIB::Libcall LC = RTLIB::getFPTOSINT(Op.getValueType(), VT);
3259 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-sint conversion!")(static_cast <bool> (LC != RTLIB::UNKNOWN_LIBCALL &&
"Unexpected fp-to-sint conversion!") ? void (0) : __assert_fail
("LC != RTLIB::UNKNOWN_LIBCALL && \"Unexpected fp-to-sint conversion!\""
, "llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp", 3259
, __extension__ __PRETTY_FUNCTION__))
;
3260 TargetLowering::MakeLibCallOptions CallOptions;
3261 CallOptions.setSExt(true);
3262 std::pair<SDValue, SDValue> Tmp = TLI.makeLibCall(DAG, LC, VT, Op,
3263 CallOptions, dl, Chain);
3264 SplitInteger(Tmp.first, Lo, Hi);
3265
3266 if (IsStrict)
3267 ReplaceValueWith(SDValue(N, 1), Tmp.second);
3268}
3269
3270void DAGTypeLegalizer::ExpandIntRes_FP_TO_UINT(SDNode *N, SDValue &Lo,
3271 SDValue &Hi) {
3272 SDLoc dl(N);
3273 EVT VT = N->getValueType(0);
3274
3275 bool IsStrict = N->isStrictFPOpcode();
3276 SDValue Chain = IsStrict ? N->getOperand(0) : SDValue();
3277 SDValue Op = N->getOperand(IsStrict ? 1 : 0);
3278 if (getTypeAction(Op.getValueType()) == TargetLowering::TypePromoteFloat)
3279 Op = GetPromotedFloat(Op);
3280
3281 if (getTypeAction(Op.getValueType()) == TargetLowering::TypeSoftPromoteHalf) {
3282 EVT NFPVT = TLI.getTypeToTransformTo(*DAG.getContext(), Op.getValueType());
3283 Op = GetSoftPromotedHalf(Op);
3284 Op = DAG.getNode(ISD::FP16_TO_FP, dl, NFPVT, Op);
3285 Op = DAG.getNode(ISD::FP_TO_UINT, dl, VT, Op);
3286 SplitInteger(Op, Lo, Hi);
3287 return;
3288 }
3289
3290 RTLIB::Libcall LC = RTLIB::getFPTOUINT(Op.getValueType(), VT);
3291 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-uint conversion!")(static_cast <bool> (LC != RTLIB::UNKNOWN_LIBCALL &&
"Unexpected fp-to-uint conversion!") ? void (0) : __assert_fail
("LC != RTLIB::UNKNOWN_LIBCALL && \"Unexpected fp-to-uint conversion!\""
, "llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp", 3291
, __extension__ __PRETTY_FUNCTION__))
;
3292 TargetLowering::MakeLibCallOptions CallOptions;
3293 std::pair<SDValue, SDValue> Tmp = TLI.makeLibCall(DAG, LC, VT, Op,
3294 CallOptions, dl, Chain);
3295 SplitInteger(Tmp.first, Lo, Hi);
3296
3297 if (IsStrict)
3298 ReplaceValueWith(SDValue(N, 1), Tmp.second);
3299}
3300
3301void DAGTypeLegalizer::ExpandIntRes_FP_TO_XINT_SAT(SDNode *N, SDValue &Lo,
3302 SDValue &Hi) {
3303 SDValue Res = TLI.expandFP_TO_INT_SAT(N, DAG);
3304 SplitInteger(Res, Lo, Hi);
3305}
3306
3307void DAGTypeLegalizer::ExpandIntRes_LLROUND_LLRINT(SDNode *N, SDValue &Lo,
3308 SDValue &Hi) {
3309 SDValue Op = N->getOperand(N->isStrictFPOpcode() ? 1 : 0);
3310
3311 assert(getTypeAction(Op.getValueType()) != TargetLowering::TypePromoteFloat &&(static_cast <bool> (getTypeAction(Op.getValueType()) !=
TargetLowering::TypePromoteFloat && "Input type needs to be promoted!"
) ? void (0) : __assert_fail ("getTypeAction(Op.getValueType()) != TargetLowering::TypePromoteFloat && \"Input type needs to be promoted!\""
, "llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp", 3312
, __extension__ __PRETTY_FUNCTION__))
3312 "Input type needs to be promoted!")(static_cast <bool> (getTypeAction(Op.getValueType()) !=
TargetLowering::TypePromoteFloat && "Input type needs to be promoted!"
) ? void (0) : __assert_fail ("getTypeAction(Op.getValueType()) != TargetLowering::TypePromoteFloat && \"Input type needs to be promoted!\""
, "llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp", 3312
, __extension__ __PRETTY_FUNCTION__))
;
3313
3314 EVT VT = Op.getValueType();
3315
3316 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3317 if (N->getOpcode() == ISD::LLROUND ||
3318 N->getOpcode() == ISD::STRICT_LLROUND) {
3319 if (VT == MVT::f32)
3320 LC = RTLIB::LLROUND_F32;
3321 else if (VT == MVT::f64)
3322 LC = RTLIB::LLROUND_F64;
3323 else if (VT == MVT::f80)
3324 LC = RTLIB::LLROUND_F80;
3325 else if (VT == MVT::f128)
3326 LC = RTLIB::LLROUND_F128;
3327 else if (VT == MVT::ppcf128)
3328 LC = RTLIB::LLROUND_PPCF128;
3329 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected llround input type!")(static_cast <bool> (LC != RTLIB::UNKNOWN_LIBCALL &&
"Unexpected llround input type!") ? void (0) : __assert_fail
("LC != RTLIB::UNKNOWN_LIBCALL && \"Unexpected llround input type!\""
, "llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp", 3329
, __extension__ __PRETTY_FUNCTION__))
;
3330 } else if (N->getOpcode() == ISD::LLRINT ||
3331 N->getOpcode() == ISD::STRICT_LLRINT) {
3332 if (VT == MVT::f32)
3333 LC = RTLIB::LLRINT_F32;
3334 else if (VT == MVT::f64)
3335 LC = RTLIB::LLRINT_F64;
3336 else if (VT == MVT::f80)
3337 LC = RTLIB::LLRINT_F80;
3338 else if (VT == MVT::f128)
3339 LC = RTLIB::LLRINT_F128;
3340 else if (VT == MVT::ppcf128)
3341 LC = RTLIB::LLRINT_PPCF128;
3342 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected llrint input type!")(static_cast <bool> (LC != RTLIB::UNKNOWN_LIBCALL &&
"Unexpected llrint input type!") ? void (0) : __assert_fail (
"LC != RTLIB::UNKNOWN_LIBCALL && \"Unexpected llrint input type!\""
, "llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp", 3342
, __extension__ __PRETTY_FUNCTION__))
;
3343 } else
3344 llvm_unreachable("Unexpected opcode!")::llvm::llvm_unreachable_internal("Unexpected opcode!", "llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 3344)
;
3345
3346 SDLoc dl(N);
3347 EVT RetVT = N->getValueType(0);
3348 SDValue Chain = N->isStrictFPOpcode() ? N->getOperand(0) : SDValue();
3349
3350 TargetLowering::MakeLibCallOptions CallOptions;
3351 CallOptions.setSExt(true);
3352 std::pair<SDValue, SDValue> Tmp = TLI.makeLibCall(DAG, LC, RetVT,
3353 Op, CallOptions, dl,
3354 Chain);
3355 SplitInteger(Tmp.first, Lo, Hi);
3356
3357 if (N->isStrictFPOpcode())
3358 ReplaceValueWith(SDValue(N, 1), Tmp.second);
3359}
3360
3361void DAGTypeLegalizer::ExpandIntRes_LOAD(LoadSDNode *N,
3362 SDValue &Lo, SDValue &Hi) {
3363 if (N->isAtomic()) {
3364 // It's typical to have larger CAS than atomic load instructions.
3365 SDLoc dl(N);
3366 EVT VT = N->getMemoryVT();
3367 SDVTList VTs = DAG.getVTList(VT, MVT::i1, MVT::Other);
3368 SDValue Zero = DAG.getConstant(0, dl, VT);
3369 SDValue Swap = DAG.getAtomicCmpSwap(
3370 ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, dl,
3371 VT, VTs, N->getOperand(0),
3372 N->getOperand(1), Zero, Zero, N->getMemOperand());
3373 ReplaceValueWith(SDValue(N, 0), Swap.getValue(0));
3374 ReplaceValueWith(SDValue(N, 1), Swap.getValue(2));
3375 return;
3376 }
3377
3378 if (ISD::isNormalLoad(N)) {
3379 ExpandRes_NormalLoad(N, Lo, Hi);
3380 return;
3381 }
3382
3383 assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!")(static_cast <bool> (ISD::isUNINDEXEDLoad(N) &&
"Indexed load during type legalization!") ? void (0) : __assert_fail
("ISD::isUNINDEXEDLoad(N) && \"Indexed load during type legalization!\""
, "llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp", 3383
, __extension__ __PRETTY_FUNCTION__))
;
3384
3385 EVT VT = N->getValueType(0);
3386 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
3387 SDValue Ch = N->getChain();
3388 SDValue Ptr = N->getBasePtr();
3389 ISD::LoadExtType ExtType = N->getExtensionType();
3390 MachineMemOperand::Flags MMOFlags = N->getMemOperand()->getFlags();
3391 AAMDNodes AAInfo = N->getAAInfo();
3392 SDLoc dl(N);
3393
3394 assert(NVT.isByteSized() && "Expanded type not byte sized!")(static_cast <bool> (NVT.isByteSized() && "Expanded type not byte sized!"
) ? void (0) : __assert_fail ("NVT.isByteSized() && \"Expanded type not byte sized!\""
, "llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp", 3394
, __extension__ __PRETTY_FUNCTION__))
;
3395
3396 if (N->getMemoryVT().bitsLE(NVT)) {
3397 EVT MemVT = N->getMemoryVT();
3398
3399 Lo = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, N->getPointerInfo(), MemVT,
3400 N->getOriginalAlign(), MMOFlags, AAInfo);
3401
3402 // Remember the chain.
3403 Ch = Lo.getValue(1);
3404
3405 if (ExtType == ISD::SEXTLOAD) {
3406 // The high part is obtained by SRA'ing all but one of the bits of the
3407 // lo part.
3408 unsigned LoSize = Lo.getValueSizeInBits();
3409 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
3410 DAG.getConstant(LoSize - 1, dl,
3411 TLI.getPointerTy(DAG.getDataLayout())));
3412 } else if (ExtType == ISD::ZEXTLOAD) {
3413 // The high part is just a zero.
3414 Hi = DAG.getConstant(0, dl, NVT);
3415 } else {
3416 assert(ExtType == ISD::EXTLOAD && "Unknown extload!")(static_cast <bool> (ExtType == ISD::EXTLOAD &&
"Unknown extload!") ? void (0) : __assert_fail ("ExtType == ISD::EXTLOAD && \"Unknown extload!\""
, "llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp", 3416
, __extension__ __PRETTY_FUNCTION__))
;
3417 // The high part is undefined.
3418 Hi = DAG.getUNDEF(NVT);
3419 }
3420 } else if (DAG.getDataLayout().isLittleEndian()) {
3421 // Little-endian - low bits are at low addresses.
3422 Lo = DAG.getLoad(NVT, dl, Ch, Ptr, N->getPointerInfo(),
3423 N->getOriginalAlign(), MMOFlags, AAInfo);
3424
3425 unsigned ExcessBits =
3426 N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits();
3427 EVT NEVT = EVT::getIntegerVT(*DAG.getContext(), ExcessBits);
3428
3429 // Increment the pointer to the other half.
3430 unsigned IncrementSize = NVT.getSizeInBits()/8;
3431 Ptr = DAG.getMemBasePlusOffset(Ptr, TypeSize::Fixed(IncrementSize), dl);
3432 Hi = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr,
3433 N->getPointerInfo().getWithOffset(IncrementSize), NEVT,
3434 N->getOriginalAlign(), MMOFlags, AAInfo);
3435
3436 // Build a factor node to remember that this load is independent of the
3437 // other one.
3438 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
3439 Hi.getValue(1));
3440 } else {
3441 // Big-endian - high bits are at low addresses. Favor aligned loads at
3442 // the cost of some bit-fiddling.
3443 EVT MemVT = N->getMemoryVT();
3444 unsigned EBytes = MemVT.getStoreSize();
3445 unsigned IncrementSize = NVT.getSizeInBits()/8;
3446 unsigned ExcessBits = (EBytes - IncrementSize)*8;
3447
3448 // Load both the high bits and maybe some of the low bits.
3449 Hi = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, N->getPointerInfo(),
3450 EVT::getIntegerVT(*DAG.getContext(),
3451 MemVT.getSizeInBits() - ExcessBits),
3452 N->getOriginalAlign(), MMOFlags, AAInfo);
3453
3454 // Increment the pointer to the other half.
3455 Ptr = DAG.getMemBasePlusOffset(Ptr, TypeSize::Fixed(IncrementSize), dl);
3456 // Load the rest of the low bits.
3457 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, NVT, Ch, Ptr,
3458 N->getPointerInfo().getWithOffset(IncrementSize),
3459 EVT::getIntegerVT(*DAG.getContext(), ExcessBits),
3460 N->getOriginalAlign(), MMOFlags, AAInfo);
3461
3462 // Build a factor node to remember that this load is independent of the
3463 // other one.
3464 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
3465 Hi.getValue(1));
3466
3467 if (ExcessBits < NVT.getSizeInBits()) {
3468 // Transfer low bits from the bottom of Hi to the top of Lo.
3469 Lo = DAG.getNode(
3470 ISD::OR, dl, NVT, Lo,
3471 DAG.getNode(ISD::SHL, dl, NVT, Hi,
3472 DAG.getConstant(ExcessBits, dl,
3473 TLI.getPointerTy(DAG.getDataLayout()))));
3474 // Move high bits to the right position in Hi.
3475 Hi = DAG.getNode(ExtType == ISD::SEXTLOAD ? ISD::SRA : ISD::SRL, dl, NVT,
3476 Hi,
3477 DAG.getConstant(NVT.getSizeInBits() - ExcessBits, dl,
3478 TLI.getPointerTy(DAG.getDataLayout())));
3479 }
3480 }
3481
3482 // Legalize the chain result - switch anything that used the old chain to
3483 // use the new one.
3484 ReplaceValueWith(SDValue(N, 1), Ch);
3485}
3486
3487void DAGTypeLegalizer::ExpandIntRes_Logical(SDNode *N,
3488 SDValue &Lo, SDValue &Hi) {
3489 SDLoc dl(N);
3490 SDValue LL, LH, RL, RH;
3491 GetExpandedInteger(N->getOperand(0), LL, LH);
3492 GetExpandedInteger(N->getOperand(1), RL, RH);
3493 Lo = DAG.getNode(N->getOpcode(), dl, LL.getValueType(), LL, RL);
3494 Hi = DAG.getNode(N->getOpcode(), dl, LL.getValueType(), LH, RH);
3495}
3496
3497void DAGTypeLegalizer::ExpandIntRes_MUL(SDNode *N,
3498 SDValue &Lo, SDValue &Hi) {
3499 EVT VT = N->getValueType(0);
3500 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
3501 SDLoc dl(N);
3502
3503 SDValue LL, LH, RL, RH;
3504 GetExpandedInteger(N->getOperand(0), LL, LH);
3505 GetExpandedInteger(N->getOperand(1), RL, RH);
3506
3507 if (TLI.expandMUL(N, Lo, Hi, NVT, DAG,
3508 TargetLowering::MulExpansionKind::OnlyLegalOrCustom,
3509 LL, LH, RL, RH))
3510 return;
3511
3512 // If nothing else, we can make a libcall.
3513 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3514 if (VT == MVT::i16)
3515 LC = RTLIB::MUL_I16;
3516 else if (VT == MVT::i32)
3517 LC = RTLIB::MUL_I32;
3518 else if (VT == MVT::i64)
3519 LC = RTLIB::MUL_I64;
3520 else if (VT == MVT::i128)
3521 LC = RTLIB::MUL_I128;
3522
3523 if (LC == RTLIB::UNKNOWN_LIBCALL || !TLI.getLibcallName(LC)) {
3524 // We'll expand the multiplication by brute force because we have no other
3525 // options. This is a trivially-generalized version of the code from
3526 // Hacker's Delight (itself derived from Knuth's Algorithm M from section
3527 // 4.3.1).
3528 unsigned Bits = NVT.getSizeInBits();
3529 unsigned HalfBits = Bits >> 1;
3530 SDValue Mask = DAG.getConstant(APInt::getLowBitsSet(Bits, HalfBits), dl,
3531 NVT);
3532 SDValue LLL = DAG.getNode(ISD::AND, dl, NVT, LL, Mask);
3533 SDValue RLL = DAG.getNode(ISD::AND, dl, NVT, RL, Mask);
3534
3535 SDValue T = DAG.getNode(ISD::MUL, dl, NVT, LLL, RLL);
3536 SDValue TL = DAG.getNode(ISD::AND, dl, NVT, T, Mask);
3537
3538 EVT ShiftAmtTy = TLI.getShiftAmountTy(NVT, DAG.getDataLayout());
3539 SDValue Shift = DAG.getConstant(HalfBits, dl, ShiftAmtTy);
3540 SDValue TH = DAG.getNode(ISD::SRL, dl, NVT, T, Shift);
3541 SDValue LLH = DAG.getNode(ISD::SRL, dl, NVT, LL, Shift);
3542 SDValue RLH = DAG.getNode(ISD::SRL, dl, NVT, RL, Shift);
3543
3544 SDValue U = DAG.getNode(ISD::ADD, dl, NVT,
3545 DAG.getNode(ISD::MUL, dl, NVT, LLH, RLL), TH);
3546 SDValue UL = DAG.getNode(ISD::AND, dl, NVT, U, Mask);
3547 SDValue UH = DAG.getNode(ISD::SRL, dl, NVT, U, Shift);
3548
3549 SDValue V = DAG.getNode(ISD::ADD, dl, NVT,
3550 DAG.getNode(ISD::MUL, dl, NVT, LLL, RLH), UL);
3551 SDValue VH = DAG.getNode(ISD::SRL, dl, NVT, V, Shift);
3552
3553 SDValue W = DAG.getNode(ISD::ADD, dl, NVT,
3554 DAG.getNode(ISD::MUL, dl, NVT, LLH, RLH),
3555 DAG.getNode(ISD::ADD, dl, NVT, UH, VH));
3556 Lo = DAG.getNode(ISD::ADD, dl, NVT, TL,
3557 DAG.getNode(ISD::SHL, dl, NVT, V, Shift));
3558
3559 Hi = DAG.getNode(ISD::ADD, dl, NVT, W,
3560 DAG.getNode(ISD::ADD, dl, NVT,
3561 DAG.getNode(ISD::MUL, dl, NVT, RH, LL),
3562 DAG.getNode(ISD::MUL, dl, NVT, RL, LH)));
3563 return;
3564 }
3565
3566 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
3567 TargetLowering::MakeLibCallOptions CallOptions;
3568 CallOptions.setSExt(true);
3569 SplitInteger(TLI.makeLibCall(DAG, LC, VT, Ops, CallOptions, dl).first,
3570 Lo, Hi);
3571}
3572
3573void DAGTypeLegalizer::ExpandIntRes_READCYCLECOUNTER(SDNode *N, SDValue &Lo,
3574 SDValue &Hi) {
3575 SDLoc DL(N);
3576 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
3577 SDVTList VTs = DAG.getVTList(NVT, NVT, MVT::Other);
3578 SDValue R = DAG.getNode(N->getOpcode(), DL, VTs, N->getOperand(0));
3579 Lo = R.getValue(0);
3580 Hi = R.getValue(1);
3581 ReplaceValueWith(SDValue(N, 1), R.getValue(2));
3582}
3583
3584void DAGTypeLegalizer::ExpandIntRes_ADDSUBSAT(SDNode *N, SDValue &Lo,
3585 SDValue &Hi) {
3586 SDValue Result = TLI.expandAddSubSat(N, DAG);
3587 SplitInteger(Result, Lo, Hi);
3588}
3589
3590void DAGTypeLegalizer::ExpandIntRes_SHLSAT(SDNode *N, SDValue &Lo,
3591 SDValue &Hi) {
3592 SDValue Result = TLI.expandShlSat(N, DAG);
3593 SplitInteger(Result, Lo, Hi);
3594}
3595
3596/// This performs an expansion of the integer result for a fixed point
3597/// multiplication. The default expansion performs rounding down towards
3598/// negative infinity, though targets that do care about rounding should specify
3599/// a target hook for rounding and provide their own expansion or lowering of
3600/// fixed point multiplication to be consistent with rounding.
3601void DAGTypeLegalizer::ExpandIntRes_MULFIX(SDNode *N, SDValue &Lo,
3602 SDValue &Hi) {
3603 SDLoc dl(N);
3604 EVT VT = N->getValueType(0);
3605 unsigned VTSize = VT.getScalarSizeInBits();
3606 SDValue LHS = N->getOperand(0);
3607 SDValue RHS = N->getOperand(1);
3608 uint64_t Scale = N->getConstantOperandVal(2);
3609 bool Saturating = (N->getOpcode() == ISD::SMULFIXSAT ||
3610 N->getOpcode() == ISD::UMULFIXSAT);
3611 bool Signed = (N->getOpcode() == ISD::SMULFIX ||
3612 N->getOpcode() == ISD::SMULFIXSAT);
3613
3614 // Handle special case when scale is equal to zero.
3615 if (!Scale) {
3616 SDValue Result;
3617 if (!Saturating) {
3618 Result = DAG.getNode(ISD::MUL, dl, VT, LHS, RHS);
3619 } else {
3620 EVT BoolVT = getSetCCResultType(VT);
3621 unsigned MulOp = Signed ? ISD::SMULO : ISD::UMULO;
3622 Result = DAG.getNode(MulOp, dl, DAG.getVTList(VT, BoolVT), LHS, RHS);
3623 SDValue Product = Result.getValue(0);
3624 SDValue Overflow = Result.getValue(1);
3625 if (Signed) {
3626 APInt MinVal = APInt::getSignedMinValue(VTSize);
3627 APInt MaxVal = APInt::getSignedMaxValue(VTSize);
3628 SDValue SatMin = DAG.getConstant(MinVal, dl, VT);
3629 SDValue SatMax = DAG.getConstant(MaxVal, dl, VT);
3630 SDValue Zero = DAG.getConstant(0, dl, VT);
3631 // Xor the inputs, if resulting sign bit is 0 the product will be
3632 // positive, else negative.
3633 SDValue Xor = DAG.getNode(ISD::XOR, dl, VT, LHS, RHS);
3634 SDValue ProdNeg = DAG.getSetCC(dl, BoolVT, Xor, Zero, ISD::SETLT);
3635 Result = DAG.getSelect(dl, VT, ProdNeg, SatMin, SatMax);
3636 Result = DAG.getSelect(dl, VT, Overflow, Result, Product);
3637 } else {
3638 // For unsigned multiplication, we only need to check the max since we
3639 // can't really overflow towards zero.
3640 APInt MaxVal = APInt::getMaxValue(VTSize);
3641 SDValue SatMax = DAG.getConstant(MaxVal, dl, VT);
3642 Result = DAG.getSelect(dl, VT, Overflow, SatMax, Product);
3643 }
3644 }
3645 SplitInteger(Result, Lo, Hi);
3646 return;
3647 }
3648
3649 // For SMULFIX[SAT] we only expect to find Scale<VTSize, but this assert will
3650 // cover for unhandled cases below, while still being valid for UMULFIX[SAT].
3651 assert(Scale <= VTSize && "Scale can't be larger than the value type size.")(static_cast <bool> (Scale <= VTSize && "Scale can't be larger than the value type size."
) ? void (0) : __assert_fail ("Scale <= VTSize && \"Scale can't be larger than the value type size.\""
, "llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp", 3651
, __extension__ __PRETTY_FUNCTION__))
;
3652
3653 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
3654 SDValue LL, LH, RL, RH;
3655 GetExpandedInteger(LHS, LL, LH);
3656 GetExpandedInteger(RHS, RL, RH);
3657 SmallVector<SDValue, 4> Result;
3658
3659 unsigned LoHiOp = Signed ? ISD::SMUL_LOHI : ISD::UMUL_LOHI;
3660 if (!TLI.expandMUL_LOHI(LoHiOp, VT, dl, LHS, RHS, Result, NVT, DAG,
3661 TargetLowering::MulExpansionKind::OnlyLegalOrCustom,
3662 LL, LH, RL, RH)) {
3663 report_fatal_error("Unable to expand MUL_FIX using MUL_LOHI.");
3664 return;
3665 }
3666
3667 unsigned NVTSize = NVT.getScalarSizeInBits();
3668 assert((VTSize == NVTSize * 2) && "Expected the new value type to be half "(static_cast <bool> ((VTSize == NVTSize * 2) &&
"Expected the new value type to be half " "the size of the current value type"
) ? void (0) : __assert_fail ("(VTSize == NVTSize * 2) && \"Expected the new value type to be half \" \"the size of the current value type\""
, "llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp", 3669
, __extension__ __PRETTY_FUNCTION__))
3669 "the size of the current value type")(static_cast <bool> ((VTSize == NVTSize * 2) &&
"Expected the new value type to be half " "the size of the current value type"
) ? void (0) : __assert_fail ("(VTSize == NVTSize * 2) && \"Expected the new value type to be half \" \"the size of the current value type\""
, "llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp", 3669
, __extension__ __PRETTY_FUNCTION__))
;
3670 EVT ShiftTy = TLI.getShiftAmountTy(NVT, DAG.getDataLayout());
3671
3672 // After getting the multiplication result in 4 parts, we need to perform a
3673 // shift right by the amount of the scale to get the result in that scale.
3674 //
3675 // Let's say we multiply 2 64 bit numbers. The resulting value can be held in
3676 // 128 bits that are cut into 4 32-bit parts:
3677 //
3678 // HH HL LH LL
3679 // |---32---|---32---|---32---|---32---|
3680 // 128 96 64 32 0
3681 //
3682 // |------VTSize-----|
3683 //
3684 // |NVTSize-|
3685 //
3686 // The resulting Lo and Hi would normally be in LL and LH after the shift. But
3687 // to avoid unneccessary shifting of all 4 parts, we can adjust the shift
3688 // amount and get Lo and Hi using two funnel shifts. Or for the special case
3689 // when Scale is a multiple of NVTSize we can just pick the result without
3690 // shifting.
3691 uint64_t Part0 = Scale / NVTSize; // Part holding lowest bit needed.
3692 if (Scale % NVTSize) {
3693 SDValue ShiftAmount = DAG.getConstant(Scale % NVTSize, dl, ShiftTy);
3694 Lo = DAG.getNode(ISD::FSHR, dl, NVT, Result[Part0 + 1], Result[Part0],
3695 ShiftAmount);
3696 Hi = DAG.getNode(ISD::FSHR, dl, NVT, Result[Part0 + 2], Result[Part0 + 1],
3697 ShiftAmount);
3698 } else {
3699 Lo = Result[Part0];
3700 Hi = Result[Part0 + 1];
3701 }
3702
3703 // Unless saturation is requested we are done. The result is in <Hi,Lo>.
3704 if (!Saturating)
3705 return;
3706
3707 // Can not overflow when there is no integer part.
3708 if (Scale == VTSize)
3709 return;
3710
3711 // To handle saturation we must check for overflow in the multiplication.
3712 //
3713 // Unsigned overflow happened if the upper (VTSize - Scale) bits (of Result)
3714 // aren't all zeroes.
3715 //
3716 // Signed overflow happened if the upper (VTSize - Scale + 1) bits (of Result)
3717 // aren't all ones or all zeroes.
3718 //
3719 // We cannot overflow past HH when multiplying 2 ints of size VTSize, so the
3720 // highest bit of HH determines saturation direction in the event of signed
3721 // saturation.
3722
3723 SDValue ResultHL = Result[2];
3724 SDValue ResultHH = Result[3];
3725
3726 SDValue SatMax, SatMin;
3727 SDValue NVTZero = DAG.getConstant(0, dl, NVT);
3728 SDValue NVTNeg1 = DAG.getConstant(-1, dl, NVT);
3729 EVT BoolNVT = getSetCCResultType(NVT);
3730
3731 if (!Signed) {
3732 if (Scale < NVTSize) {
3733 // Overflow happened if ((HH | (HL >> Scale)) != 0).
3734 SDValue HLAdjusted = DAG.getNode(ISD::SRL, dl, NVT, ResultHL,
3735 DAG.getConstant(Scale, dl, ShiftTy));
3736 SDValue Tmp = DAG.getNode(ISD::OR, dl, NVT, HLAdjusted, ResultHH);
3737 SatMax = DAG.getSetCC(dl, BoolNVT, Tmp, NVTZero, ISD::SETNE);
3738 } else if (Scale == NVTSize) {
3739 // Overflow happened if (HH != 0).
3740 SatMax = DAG.getSetCC(dl, BoolNVT, ResultHH, NVTZero, ISD::SETNE);
3741 } else if (Scale < VTSize) {
3742 // Overflow happened if ((HH >> (Scale - NVTSize)) != 0).
3743 SDValue HLAdjusted = DAG.getNode(ISD::SRL, dl, NVT, ResultHL,
3744 DAG.getConstant(Scale - NVTSize, dl,
3745 ShiftTy));
3746 SatMax = DAG.getSetCC(dl, BoolNVT, HLAdjusted, NVTZero, ISD::SETNE);
3747 } else
3748 llvm_unreachable("Scale must be less or equal to VTSize for UMULFIXSAT"::llvm::llvm_unreachable_internal("Scale must be less or equal to VTSize for UMULFIXSAT"
"(and saturation can't happen with Scale==VTSize).", "llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 3749)
3749 "(and saturation can't happen with Scale==VTSize).")::llvm::llvm_unreachable_internal("Scale must be less or equal to VTSize for UMULFIXSAT"
"(and saturation can't happen with Scale==VTSize).", "llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 3749)
;
3750
3751 Hi = DAG.getSelect(dl, NVT, SatMax, NVTNeg1, Hi);
3752 Lo = DAG.getSelect(dl, NVT, SatMax, NVTNeg1, Lo);
3753 return;
3754 }
3755
3756 if (Scale < NVTSize) {
3757 // The number of overflow bits we can check are VTSize - Scale + 1 (we
3758 // include the sign bit). If these top bits are > 0, then we overflowed past
3759 // the max value. If these top bits are < -1, then we overflowed past the
3760 // min value. Otherwise, we did not overflow.
3761 unsigned OverflowBits = VTSize - Scale + 1;
3762 assert(OverflowBits <= VTSize && OverflowBits > NVTSize &&(static_cast <bool> (OverflowBits <= VTSize &&
OverflowBits > NVTSize && "Extent of overflow bits must start within HL"
) ? void (0) : __assert_fail ("OverflowBits <= VTSize && OverflowBits > NVTSize && \"Extent of overflow bits must start within HL\""
, "llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp", 3763
, __extension__ __PRETTY_FUNCTION__))
3763 "Extent of overflow bits must start within HL")(static_cast <bool> (OverflowBits <= VTSize &&
OverflowBits > NVTSize && "Extent of overflow bits must start within HL"
) ? void (0) : __assert_fail ("OverflowBits <= VTSize && OverflowBits > NVTSize && \"Extent of overflow bits must start within HL\""
, "llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp", 3763
, __extension__ __PRETTY_FUNCTION__))
;
3764 SDValue HLHiMask = DAG.getConstant(
3765 APInt::getHighBitsSet(NVTSize, OverflowBits - NVTSize), dl, NVT);
3766 SDValue HLLoMask = DAG.getConstant(
3767 APInt::getLowBitsSet(NVTSize, VTSize - OverflowBits), dl, NVT);
3768 // We overflow max if HH > 0 or (HH == 0 && HL > HLLoMask).
3769 SDValue HHGT0 = DAG.getSetCC(dl, BoolNVT, ResultHH, NVTZero, ISD::SETGT);
3770 SDValue HHEQ0 = DAG.getSetCC(dl, BoolNVT, ResultHH, NVTZero, ISD::SETEQ);
3771 SDValue HLUGT = DAG.getSetCC(dl, BoolNVT, ResultHL, HLLoMask, ISD::SETUGT);
3772 SatMax = DAG.getNode(ISD::OR, dl, BoolNVT, HHGT0,
3773 DAG.getNode(ISD::AND, dl, BoolNVT, HHEQ0, HLUGT));
3774 // We overflow min if HH < -1 or (HH == -1 && HL < HLHiMask).
3775 SDValue HHLT = DAG.getSetCC(dl, BoolNVT, ResultHH, NVTNeg1, ISD::SETLT);
3776 SDValue HHEQ = DAG.getSetCC(dl, BoolNVT, ResultHH, NVTNeg1, ISD::SETEQ);
3777 SDValue HLULT = DAG.getSetCC(dl, BoolNVT, ResultHL, HLHiMask, ISD::SETULT);
3778 SatMin = DAG.getNode(ISD::OR, dl, BoolNVT, HHLT,
3779 DAG.getNode(ISD::AND, dl, BoolNVT, HHEQ, HLULT));
3780 } else if (Scale == NVTSize) {
3781 // We overflow max if HH > 0 or (HH == 0 && HL sign bit is 1).
3782 SDValue HHGT0 = DAG.getSetCC(dl, BoolNVT, ResultHH, NVTZero, ISD::SETGT);
3783 SDValue HHEQ0 = DAG.getSetCC(dl, BoolNVT, ResultHH, NVTZero, ISD::SETEQ);
3784 SDValue HLNeg = DAG.getSetCC(dl, BoolNVT, ResultHL, NVTZero, ISD::SETLT);
3785 SatMax = DAG.getNode(ISD::OR, dl, BoolNVT, HHGT0,
3786 DAG.getNode(ISD::AND, dl, BoolNVT, HHEQ0, HLNeg));
3787 // We overflow min if HH < -1 or (HH == -1 && HL sign bit is 0).
3788 SDValue HHLT = DAG.getSetCC(dl, BoolNVT, ResultHH, NVTNeg1, ISD::SETLT);
3789 SDValue HHEQ = DAG.getSetCC(dl, BoolNVT, ResultHH, NVTNeg1, ISD::SETEQ);
3790 SDValue HLPos = DAG.getSetCC(dl, BoolNVT, ResultHL, NVTZero, ISD::SETGE);
3791 SatMin = DAG.getNode(ISD::OR, dl, BoolNVT, HHLT,
3792 DAG.getNode(ISD::AND, dl, BoolNVT, HHEQ, HLPos));
3793 } else if (Scale < VTSize) {
3794 // This is similar to the case when we saturate if Scale < NVTSize, but we
3795 // only need to check HH.
3796 unsigned OverflowBits = VTSize - Scale + 1;
3797 SDValue HHHiMask = DAG.getConstant(
3798 APInt::getHighBitsSet(NVTSize, OverflowBits), dl, NVT);
3799 SDValue HHLoMask = DAG.getConstant(
3800 APInt::getLowBitsSet(NVTSize, NVTSize - OverflowBits), dl, NVT);
3801 SatMax = DAG.getSetCC(dl, BoolNVT, ResultHH, HHLoMask, ISD::SETGT);
3802 SatMin = DAG.getSetCC(dl, BoolNVT, ResultHH, HHHiMask, ISD::SETLT);
3803 } else
3804 llvm_unreachable("Illegal scale for signed fixed point mul.")::llvm::llvm_unreachable_internal("Illegal scale for signed fixed point mul."
, "llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp", 3804
)
;
3805
3806 // Saturate to signed maximum.
3807 APInt MaxHi = APInt::getSignedMaxValue(NVTSize);
3808 APInt MaxLo = APInt::getAllOnes(NVTSize);
3809 Hi = DAG.getSelect(dl, NVT, SatMax, DAG.getConstant(MaxHi, dl, NVT), Hi);
3810 Lo = DAG.getSelect(dl, NVT, SatMax, DAG.getConstant(MaxLo, dl, NVT), Lo);
3811 // Saturate to signed minimum.
3812 APInt MinHi = APInt::getSignedMinValue(NVTSize);
3813 Hi = DAG.getSelect(dl, NVT, SatMin, DAG.getConstant(MinHi, dl, NVT), Hi);
3814 Lo = DAG.getSelect(dl, NVT, SatMin, NVTZero, Lo);
3815}
3816
3817void DAGTypeLegalizer::ExpandIntRes_DIVFIX(SDNode *N, SDValue &Lo,
3818 SDValue &Hi) {
3819 SDLoc dl(N);
3820 // Try expanding in the existing type first.
3821 SDValue Res = TLI.expandFixedPointDiv(N->getOpcode(), dl, N->getOperand(0),
3822 N->getOperand(1),
3823 N->getConstantOperandVal(2), DAG);
3824
3825 if (!Res)
3826 Res = earlyExpandDIVFIX(N, N->getOperand(0), N->getOperand(1),
3827 N->getConstantOperandVal(2), TLI, DAG);
3828 SplitInteger(Res, Lo, Hi);
3829}
3830
3831void DAGTypeLegalizer::ExpandIntRes_SADDSUBO(SDNode *Node,
3832 SDValue &Lo, SDValue &Hi) {
3833 assert((Node->getOpcode() == ISD::SADDO || Node->getOpcode() == ISD::SSUBO) &&(static_cast <bool> ((Node->getOpcode() == ISD::SADDO
|| Node->getOpcode() == ISD::SSUBO) && "Node has unexpected Opcode"
) ? void (0) : __assert_fail ("(Node->getOpcode() == ISD::SADDO || Node->getOpcode() == ISD::SSUBO) && \"Node has unexpected Opcode\""
, "llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp", 3834
, __extension__ __PRETTY_FUNCTION__))
3834 "Node has unexpected Opcode")(static_cast <bool> ((Node->getOpcode() == ISD::SADDO
|| Node->getOpcode() == ISD::SSUBO) && "Node has unexpected Opcode"
) ? void (0) : __assert_fail ("(Node->getOpcode() == ISD::SADDO || Node->getOpcode() == ISD::SSUBO) && \"Node has unexpected Opcode\""
, "llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp", 3834
, __extension__ __PRETTY_FUNCTION__))
;
3835 SDValue LHS = Node->getOperand(0);
3836 SDValue RHS = Node->getOperand(1);
3837 SDLoc dl(Node);
3838
3839 SDValue Ovf;
3840
3841 bool IsAdd = Node->getOpcode() == ISD::SADDO;
3842 unsigned CarryOp = IsAdd ? ISD::SADDO_CARRY : ISD::SSUBO_CARRY;
3843
3844 bool HasCarryOp = TLI.isOperationLegalOrCustom(
3845 CarryOp, TLI.getTypeToExpandTo(*DAG.getContext(), LHS.getValueType()));
3846
3847 if (HasCarryOp) {
3848 // Expand the subcomponents.
3849 SDValue LHSL, LHSH, RHSL, RHSH;
3850 GetExpandedInteger(LHS, LHSL, LHSH);
3851 GetExpandedInteger(RHS, RHSL, RHSH);
3852 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), Node->getValueType(1));
3853
3854 Lo = DAG.getNode(IsAdd ? ISD::UADDO : ISD::USUBO, dl, VTList, {LHSL, RHSL});
3855 Hi = DAG.getNode(CarryOp, dl, VTList, { LHSH, RHSH, Lo.getValue(1) });
3856
3857 Ovf = Hi.getValue(1);
3858 } else {
3859 // Expand the result by simply replacing it with the equivalent
3860 // non-overflow-checking operation.
3861 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::SADDO ?
3862 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
3863 LHS, RHS);
3864 SplitInteger(Sum, Lo, Hi);
3865
3866 // Compute the overflow.
3867 //
3868 // LHSSign -> LHS < 0
3869 // RHSSign -> RHS < 0
3870 // SumSign -> Sum < 0
3871 //
3872 // Add:
3873 // Overflow -> (LHSSign == RHSSign) && (LHSSign != SumSign)
3874 // Sub:
3875 // Overflow -> (LHSSign != RHSSign) && (LHSSign != SumSign)
3876 //
3877 // To get better codegen we can rewrite this by doing bitwise math on
3878 // the integers and extract the final sign bit at the end. So the
3879 // above becomes:
3880 //
3881 // Add:
3882 // Overflow -> (~(LHS ^ RHS) & (LHS ^ Sum)) < 0
3883 // Sub:
3884 // Overflow -> ((LHS ^ RHS) & (LHS ^ Sum)) < 0
3885 //
3886 // NOTE: This is different than the expansion we do in expandSADDSUBO
3887 // because it is more costly to determine the RHS is > 0 for SSUBO with the
3888 // integers split.
3889 EVT VT = LHS.getValueType();
3890 SDValue SignsMatch = DAG.getNode(ISD::XOR, dl, VT, LHS, RHS);
3891 if (IsAdd)
3892 SignsMatch = DAG.getNOT(dl, SignsMatch, VT);
3893
3894 SDValue SumSignNE = DAG.getNode(ISD::XOR, dl, VT, LHS, Sum);
3895 Ovf = DAG.getNode(ISD::AND, dl, VT, SignsMatch, SumSignNE);
3896 EVT OType = Node->getValueType(1);
3897 Ovf = DAG.getSetCC(dl, OType, Ovf, DAG.getConstant(0, dl, VT), ISD::SETLT);
3898 }
3899
3900 // Use the calculated overflow everywhere.
3901 ReplaceValueWith(SDValue(Node, 1), Ovf);
3902}
3903
3904void DAGTypeLegalizer::ExpandIntRes_SDIV(SDNode *N,
3905 SDValue &Lo, SDValue &Hi) {
3906 EVT VT = N->getValueType(0);
3907 SDLoc dl(N);
3908 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
3909
3910 if (TLI.getOperationAction(ISD::SDIVREM, VT) == TargetLowering::Custom) {
3911 SDValue Res = DAG.getNode(ISD::SDIVREM, dl, DAG.getVTList(VT, VT), Ops);
3912 SplitInteger(Res.getValue(0), Lo, Hi);
3913 return;
3914 }
3915
3916 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3917 if (VT == MVT::i16)
3918 LC = RTLIB::SDIV_I16;
3919 else if (VT == MVT::i32)
3920 LC = RTLIB::SDIV_I32;
3921 else if (VT == MVT::i64)
3922 LC = RTLIB::SDIV_I64;
3923 else if (VT == MVT::i128)
3924 LC = RTLIB::SDIV_I128;
3925 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SDIV!")(static_cast <bool> (LC != RTLIB::UNKNOWN_LIBCALL &&
"Unsupported SDIV!") ? void (0) : __assert_fail ("LC != RTLIB::UNKNOWN_LIBCALL && \"Unsupported SDIV!\""
, "llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp", 3925
, __extension__ __PRETTY_FUNCTION__))
;
3926
3927 TargetLowering::MakeLibCallOptions CallOptions;
3928 CallOptions.setSExt(true);
3929 SplitInteger(TLI.makeLibCall(DAG, LC, VT, Ops, CallOptions, dl).first, Lo, Hi);
3930}
3931
3932void DAGTypeLegalizer::ExpandIntRes_Shift(SDNode *N,
3933 SDValue &Lo, SDValue &Hi) {
3934 EVT VT = N->getValueType(0);
3935 SDLoc dl(N);
3936
3937 // If we can emit an efficient shift operation, do so now. Check to see if
3938 // the RHS is a constant.
3939 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1)))
7
Assuming 'CN' is null
8
Taking false branch
3940 return ExpandShiftByConstant(N, CN->getAPIntValue(), Lo, Hi);
3941
3942 // If we can determine that the high bit of the shift is zero or one, even if
3943 // the low bits are variable, emit this shift in an optimized form.
3944 if (ExpandShiftWithKnownAmountBit(N, Lo, Hi))
9
Calling 'DAGTypeLegalizer::ExpandShiftWithKnownAmountBit'
3945 return;
3946
3947 // If this target supports shift_PARTS, use it. First, map to the _PARTS opc.
3948 unsigned PartsOpc;
3949 if (N->getOpcode() == ISD::SHL) {
3950 PartsOpc = ISD::SHL_PARTS;
3951 } else if (N->getOpcode() == ISD::SRL) {
3952 PartsOpc = ISD::SRL_PARTS;
3953 } else {
3954 assert(N->getOpcode() == ISD::SRA && "Unknown shift!")(static_cast <bool> (N->getOpcode() == ISD::SRA &&
"Unknown shift!") ? void (0) : __assert_fail ("N->getOpcode() == ISD::SRA && \"Unknown shift!\""
, "llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp", 3954
, __extension__ __PRETTY_FUNCTION__))
;
3955 PartsOpc = ISD::SRA_PARTS;
3956 }
3957
3958 // Next check to see if the target supports this SHL_PARTS operation or if it
3959 // will custom expand it. Don't lower this to SHL_PARTS when we optimise for
3960 // size, but create a libcall instead.
3961 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
3962 TargetLowering::LegalizeAction Action = TLI.getOperationAction(PartsOpc, NVT);
3963 const bool LegalOrCustom =
3964 (Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
3965 Action == TargetLowering::Custom;
3966
3967 if (LegalOrCustom && TLI.shouldExpandShift(DAG, N)) {
3968 // Expand the subcomponents.
3969 SDValue LHSL, LHSH;
3970 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
3971 EVT VT = LHSL.getValueType();
3972
3973 // If the shift amount operand is coming from a vector legalization it may
3974 // have an illegal type. Fix that first by casting the operand, otherwise
3975 // the new SHL_PARTS operation would need further legalization.
3976 SDValue ShiftOp = N->getOperand(1);
3977 EVT ShiftTy = TLI.getShiftAmountTy(VT, DAG.getDataLayout());
3978 if (ShiftOp.getValueType() != ShiftTy)
3979 ShiftOp = DAG.getZExtOrTrunc(ShiftOp, dl, ShiftTy);
3980
3981 SDValue Ops[] = { LHSL, LHSH, ShiftOp };
3982 Lo = DAG.getNode(PartsOpc, dl, DAG.getVTList(VT, VT), Ops);
3983 Hi = Lo.getValue(1);
3984 return;
3985 }
3986
3987 // Otherwise, emit a libcall.
3988 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3989 bool isSigned;
3990 if (N->getOpcode() == ISD::SHL) {
3991 isSigned = false; /*sign irrelevant*/
3992 if (VT == MVT::i16)
3993 LC = RTLIB::SHL_I16;
3994 else if (VT == MVT::i32)
3995 LC = RTLIB::SHL_I32;
3996 else if (VT == MVT::i64)
3997 LC = RTLIB::SHL_I64;
3998 else if (VT == MVT::i128)
3999 LC = RTLIB::SHL_I128;
4000 } else if (N->getOpcode() == ISD::SRL) {
4001 isSigned = false;
4002 if (VT == MVT::i16)
4003 LC = RTLIB::SRL_I16;
4004 else if (VT == MVT::i32)
4005 LC = RTLIB::SRL_I32;
4006 else if (VT == MVT::i64)
4007 LC = RTLIB::SRL_I64;
4008 else if (VT == MVT::i128)
4009 LC = RTLIB::SRL_I128;
4010 } else {
4011 assert(N->getOpcode() == ISD::SRA && "Unknown shift!")(static_cast <bool> (N->getOpcode() == ISD::SRA &&
"Unknown shift!") ? void (0) : __assert_fail ("N->getOpcode() == ISD::SRA && \"Unknown shift!\""
, "llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp", 4011
, __extension__ __PRETTY_FUNCTION__))
;
4012 isSigned = true;
4013 if (VT == MVT::i16)
4014 LC = RTLIB::SRA_I16;
4015 else if (VT == MVT::i32)
4016 LC = RTLIB::SRA_I32;
4017 else if (VT == MVT::i64)
4018 LC = RTLIB::SRA_I64;
4019 else if (VT == MVT::i128)
4020 LC = RTLIB::SRA_I128;
4021 }
4022
4023 if (LC != RTLIB::UNKNOWN_LIBCALL && TLI.getLibcallName(LC)) {
4024 EVT ShAmtTy =
4025 EVT::getIntegerVT(*DAG.getContext(), DAG.getLibInfo().getIntSize());
4026 SDValue ShAmt = DAG.getZExtOrTrunc(N->getOperand(1), dl, ShAmtTy);
4027 SDValue Ops[2] = {N->getOperand(0), ShAmt};
4028 TargetLowering::MakeLibCallOptions CallOptions;
4029 CallOptions.setSExt(isSigned);
4030 SplitInteger(TLI.makeLibCall(DAG, LC, VT, Ops, CallOptions, dl).first, Lo, Hi);
4031 return;
4032 }
4033
4034 if (!ExpandShiftWithUnknownAmountBit(N, Lo, Hi))
4035 llvm_unreachable("Unsupported shift!")::llvm::llvm_unreachable_internal("Unsupported shift!", "llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 4035)
;
4036}
4037
4038void DAGTypeLegalizer::ExpandIntRes_SIGN_EXTEND(SDNode *N,
4039 SDValue &Lo, SDValue &Hi) {
4040 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
4041 SDLoc dl(N);
4042 SDValue Op = N->getOperand(0);
4043 if (Op.getValueType().bitsLE(NVT)) {
4044 // The low part is sign extension of the input (degenerates to a copy).
4045 Lo = DAG.getNode(ISD::SIGN_EXTEND, dl, NVT, N->getOperand(0));
4046 // The high part is obtained by SRA'ing all but one of the bits of low part.
4047 unsigned LoSize = NVT.getSizeInBits();
4048 Hi = DAG.getNode(
4049 ISD::SRA, dl, NVT, Lo,
4050 DAG.getConstant(LoSize - 1, dl, TLI.getPointerTy(DAG.getDataLayout())));
4051 } else {
4052 // For example, extension of an i48 to an i64. The operand type necessarily
4053 // promotes to the result type, so will end up being expanded too.
4054 assert(getTypeAction(Op.getValueType()) ==(static_cast <bool> (getTypeAction(Op.getValueType()) ==
TargetLowering::TypePromoteInteger && "Only know how to promote this result!"
) ? void (0) : __assert_fail ("getTypeAction(Op.getValueType()) == TargetLowering::TypePromoteInteger && \"Only know how to promote this result!\""
, "llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp", 4056
, __extension__ __PRETTY_FUNCTION__))
4055 TargetLowering::TypePromoteInteger &&(static_cast <bool> (getTypeAction(Op.getValueType()) ==
TargetLowering::TypePromoteInteger && "Only know how to promote this result!"
) ? void (0) : __assert_fail ("getTypeAction(Op.getValueType()) == TargetLowering::TypePromoteInteger && \"Only know how to promote this result!\""
, "llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp", 4056
, __extension__ __PRETTY_FUNCTION__))
4056 "Only know how to promote this result!")(static_cast <bool> (getTypeAction(Op.getValueType()) ==
TargetLowering::TypePromoteInteger && "Only know how to promote this result!"
) ? void (0) : __assert_fail ("getTypeAction(Op.getValueType()) == TargetLowering::TypePromoteInteger && \"Only know how to promote this result!\""
, "llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp", 4056
, __extension__ __PRETTY_FUNCTION__))
;
4057 SDValue Res = GetPromotedInteger(Op);
4058 assert(Res.getValueType() == N->getValueType(0) &&(static_cast <bool> (Res.getValueType() == N->getValueType
(0) && "Operand over promoted?") ? void (0) : __assert_fail
("Res.getValueType() == N->getValueType(0) && \"Operand over promoted?\""
, "llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp", 4059
, __extension__ __PRETTY_FUNCTION__))
4059 "Operand over promoted?")(static_cast <bool> (Res.getValueType() == N->getValueType
(0) && "Operand over promoted?") ? void (0) : __assert_fail
("Res.getValueType() == N->getValueType(0) && \"Operand over promoted?\""
, "llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp", 4059
, __extension__ __PRETTY_FUNCTION__))
;
4060 // Split the promoted operand. This will simplify when it is expanded.
4061 SplitInteger(Res, Lo, Hi);
4062 unsigned ExcessBits = Op.getValueSizeInBits() - NVT.getSizeInBits();
4063 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Hi.getValueType(), Hi,
4064 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(),
4065 ExcessBits)));
4066 }
4067}
4068
4069void DAGTypeLegalizer::
4070ExpandIntRes_SIGN_EXTEND_INREG(SDNode *N, SDValue &Lo, SDValue &Hi) {
4071 SDLoc dl(N);
4072 GetExpandedInteger(N->getOperand(0), Lo, Hi);
4073 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
4074
4075 if (EVT.bitsLE(Lo.getValueType())) {
4076 // sext_inreg the low part if needed.
4077 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Lo.getValueType(), Lo,
4078 N->getOperand(1));
4079
4080 // The high part gets the sign extension from the lo-part. This handles
4081 // things like sextinreg V:i64 from i8.
4082 Hi = DAG.getNode(ISD::SRA, dl, Hi.getValueType(), Lo,
4083 DAG.getConstant(Hi.getValueSizeInBits() - 1, dl,
4084 TLI.getPointerTy(DAG.getDataLayout())));
4085 } else {
4086 // For example, extension of an i48 to an i64. Leave the low part alone,
4087 // sext_inreg the high part.
4088 unsigned ExcessBits = EVT.getSizeInBits() - Lo.getValueSizeInBits();
4089 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Hi.getValueType(), Hi,
4090 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(),
4091 ExcessBits)));
4092 }
4093}
4094
4095void DAGTypeLegalizer::ExpandIntRes_SREM(SDNode *N,
4096 SDValue &Lo, SDValue &Hi) {
4097 EVT VT = N->getValueType(0);
4098 SDLoc dl(N);
4099 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
4100
4101 if (TLI.getOperationAction(ISD::SDIVREM, VT) == TargetLowering::Custom) {
4102 SDValue Res = DAG.getNode(ISD::SDIVREM, dl, DAG.getVTList(VT, VT), Ops);
4103 SplitInteger(Res.getValue(1), Lo, Hi);
4104 return;
4105 }
4106
4107 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
4108 if (VT == MVT::i16)
4109 LC = RTLIB::SREM_I16;
4110 else if (VT == MVT::i32)
4111 LC = RTLIB::SREM_I32;
4112 else if (VT == MVT::i64)
4113 LC = RTLIB::SREM_I64;
4114 else if (VT == MVT::i128)
4115 LC = RTLIB::SREM_I128;
4116 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SREM!")(static_cast <bool> (LC != RTLIB::UNKNOWN_LIBCALL &&
"Unsupported SREM!") ? void (0) : __assert_fail ("LC != RTLIB::UNKNOWN_LIBCALL && \"Unsupported SREM!\""
, "llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp", 4116
, __extension__ __PRETTY_FUNCTION__))
;
4117
4118 TargetLowering::MakeLibCallOptions CallOptions;
4119 CallOptions.setSExt(true);
4120 SplitInteger(TLI.makeLibCall(DAG, LC, VT, Ops, CallOptions, dl).first, Lo, Hi);
4121}
4122
4123void DAGTypeLegalizer::ExpandIntRes_TRUNCATE(SDNode *N,
4124 SDValue &Lo, SDValue &Hi) {
4125 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
4126 SDLoc dl(N);
4127 Lo = DAG.getNode(ISD::TRUNCATE, dl, NVT, N->getOperand(0));
4128 Hi = DAG.getNode(ISD::SRL, dl, N->getOperand(0).getValueType(),
4129 N->getOperand(0),
4130 DAG.getConstant(NVT.getSizeInBits(), dl,
4131 TLI.getPointerTy(DAG.getDataLayout())));
4132 Hi = DAG.getNode(ISD::TRUNCATE, dl, NVT, Hi);
4133}
4134
4135void DAGTypeLegalizer::ExpandIntRes_XMULO(SDNode *N,
4136 SDValue &Lo, SDValue &Hi) {
4137 EVT VT = N->getValueType(0);
4138 SDLoc dl(N);
4139
4140 if (N->getOpcode() == ISD::UMULO) {
4141 // This section expands the operation into the following sequence of
4142 // instructions. `iNh` here refers to a type which has half the bit width of
4143 // the type the original operation operated on.
4144 //
4145 // %0 = %LHS.HI != 0 && %RHS.HI != 0
4146 // %1 = { iNh, i1 } @umul.with.overflow.iNh(iNh %LHS.HI, iNh %RHS.LO)
4147 // %2 = { iNh, i1 } @umul.with.overflow.iNh(iNh %RHS.HI, iNh %LHS.LO)
4148 // %3 = mul nuw iN (%LHS.LOW as iN), (%RHS.LOW as iN)
4149 // %4 = add iNh %1.0, %2.0 as iN
4150 // %5 = { iNh, i1 } @uadd.with.overflow.iNh(iNh %4, iNh %3.HIGH)
4151 //
4152 // %lo = %3.LO
4153 // %hi = %5.0
4154 // %ovf = %0 || %1.1 || %2.1 || %5.1
4155 SDValue LHS = N->getOperand(0), RHS = N->getOperand(1);
4156 SDValue LHSHigh, LHSLow, RHSHigh, RHSLow;
4157 GetExpandedInteger(LHS, LHSLow, LHSHigh);
4158 GetExpandedInteger(RHS, RHSLow, RHSHigh);
4159 EVT HalfVT = LHSLow.getValueType();
4160 EVT BitVT = N->getValueType(1);
4161 SDVTList VTHalfWithO = DAG.getVTList(HalfVT, BitVT);
4162
4163 SDValue HalfZero = DAG.getConstant(0, dl, HalfVT);
4164 SDValue Overflow = DAG.getNode(ISD::AND, dl, BitVT,
4165 DAG.getSetCC(dl, BitVT, LHSHigh, HalfZero, ISD::SETNE),
4166 DAG.getSetCC(dl, BitVT, RHSHigh, HalfZero, ISD::SETNE));
4167
4168 SDValue One = DAG.getNode(ISD::UMULO, dl, VTHalfWithO, LHSHigh, RHSLow);
4169 Overflow = DAG.getNode(ISD::OR, dl, BitVT, Overflow, One.getValue(1));
4170
4171 SDValue Two = DAG.getNode(ISD::UMULO, dl, VTHalfWithO, RHSHigh, LHSLow);
4172 Overflow = DAG.getNode(ISD::OR, dl, BitVT, Overflow, Two.getValue(1));
4173
4174 SDValue HighSum = DAG.getNode(ISD::ADD, dl, HalfVT, One, Two);
4175
4176 // Cannot use `UMUL_LOHI` directly, because some 32-bit targets (ARM) do not
4177 // know how to expand `i64,i64 = umul_lohi a, b` and abort (why isn’t this
4178 // operation recursively legalized?).
4179 //
4180 // Many backends understand this pattern and will convert into LOHI
4181 // themselves, if applicable.
4182 SDValue Three = DAG.getNode(ISD::MUL, dl, VT,
4183 DAG.getNode(ISD::ZERO_EXTEND, dl, VT, LHSLow),
4184 DAG.getNode(ISD::ZERO_EXTEND, dl, VT, RHSLow));
4185 SplitInteger(Three, Lo, Hi);
4186
4187 Hi = DAG.getNode(ISD::UADDO, dl, VTHalfWithO, Hi, HighSum);
4188 Overflow = DAG.getNode(ISD::OR, dl, BitVT, Overflow, Hi.getValue(1));
4189 ReplaceValueWith(SDValue(N, 1), Overflow);
4190 return;
4191 }
4192
4193 Type *RetTy = VT.getTypeForEVT(*DAG.getContext());
4194 EVT PtrVT = TLI.getPointerTy(DAG.getDataLayout());
4195 Type *PtrTy = PtrVT.getTypeForEVT(*DAG.getContext());
4196
4197 // Replace this with a libcall that will check overflow.
4198 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
4199 if (VT == MVT::i32)
4200 LC = RTLIB::MULO_I32;
4201 else if (VT == MVT::i64)
4202 LC = RTLIB::MULO_I64;
4203 else if (VT == MVT::i128)
4204 LC = RTLIB::MULO_I128;
4205
4206 if (LC == RTLIB::UNKNOWN_LIBCALL || !TLI.getLibcallName(LC)) {
4207 // FIXME: This is not an optimal expansion, but better than crashing.
4208 EVT WideVT =
4209 EVT::getIntegerVT(*DAG.getContext(), VT.getScalarSizeInBits() * 2);
4210 SDValue LHS = DAG.getNode(ISD::SIGN_EXTEND, dl, WideVT, N->getOperand(0));
4211 SDValue RHS = DAG.getNode(ISD::SIGN_EXTEND, dl, WideVT, N->getOperand(1));
4212 SDValue Mul = DAG.getNode(ISD::MUL, dl, WideVT, LHS, RHS);
4213 SDValue MulLo, MulHi;
4214 SplitInteger(Mul, MulLo, MulHi);
4215 SDValue SRA =
4216 DAG.getNode(ISD::SRA, dl, VT, MulLo,
4217 DAG.getConstant(VT.getScalarSizeInBits() - 1, dl, VT));
4218 SDValue Overflow =
4219 DAG.getSetCC(dl, N->getValueType(1), MulHi, SRA, ISD::SETNE);
4220 SplitInteger(MulLo, Lo, Hi);
4221 ReplaceValueWith(SDValue(N, 1), Overflow);
4222 return;
4223 }
4224
4225 SDValue Temp = DAG.CreateStackTemporary(PtrVT);
4226 // Temporary for the overflow value, default it to zero.
4227 SDValue Chain =
4228 DAG.getStore(DAG.getEntryNode(), dl, DAG.getConstant(0, dl, PtrVT), Temp,
4229 MachinePointerInfo());
4230
4231 TargetLowering::ArgListTy Args;
4232 TargetLowering::ArgListEntry Entry;
4233 for (const SDValue &Op : N->op_values()) {
4234 EVT ArgVT = Op.getValueType();
4235 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
4236 Entry.Node = Op;
4237 Entry.Ty = ArgTy;
4238 Entry.IsSExt = true;
4239 Entry.IsZExt = false;
4240 Args.push_back(Entry);
4241 }
4242
4243 // Also pass the address of the overflow check.
4244 Entry.Node = Temp;
4245 Entry.Ty = PtrTy->getPointerTo();
4246 Entry.IsSExt = true;
4247 Entry.IsZExt = false;
4248 Args.push_back(Entry);
4249
4250 SDValue Func = DAG.getExternalSymbol(TLI.getLibcallName(LC), PtrVT);
4251
4252 TargetLowering::CallLoweringInfo CLI(DAG);
4253 CLI.setDebugLoc(dl)
4254 .setChain(Chain)
4255 .setLibCallee(TLI.getLibcallCallingConv(LC), RetTy, Func, std::move(Args))
4256 .setSExtResult();
4257
4258 std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI);
4259
4260 SplitInteger(CallInfo.first, Lo, Hi);
4261 SDValue Temp2 =
4262 DAG.getLoad(PtrVT, dl, CallInfo.second, Temp, MachinePointerInfo());
4263 SDValue Ofl = DAG.getSetCC(dl, N->getValueType(1), Temp2,
4264 DAG.getConstant(0, dl, PtrVT),
4265 ISD::SETNE);
4266 // Use the overflow from the libcall everywhere.
4267 ReplaceValueWith(SDValue(N, 1), Ofl);
4268}
4269
4270void DAGTypeLegalizer::ExpandIntRes_UDIV(SDNode *N,
4271 SDValue &Lo, SDValue &Hi) {
4272 EVT VT = N->getValueType(0);
4273 SDLoc dl(N);
4274 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
4275
4276 if (TLI.getOperationAction(ISD::UDIVREM, VT) == TargetLowering::Custom) {
4277 SDValue Res = DAG.getNode(ISD::UDIVREM, dl, DAG.getVTList(VT, VT), Ops);
4278 SplitInteger(Res.getValue(0), Lo, Hi);
4279 return;
4280 }
4281
4282 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
4283 if (VT == MVT::i16)
4284 LC = RTLIB::UDIV_I16;
4285 else if (VT == MVT::i32)
4286 LC = RTLIB::UDIV_I32;
4287 else if (VT == MVT::i64)
4288 LC = RTLIB::UDIV_I64;
4289 else if (VT == MVT::i128)
4290 LC = RTLIB::UDIV_I128;
4291 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UDIV!")(static_cast <bool> (LC != RTLIB::UNKNOWN_LIBCALL &&
"Unsupported UDIV!") ? void (0) : __assert_fail ("LC != RTLIB::UNKNOWN_LIBCALL && \"Unsupported UDIV!\""
, "llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp", 4291
, __extension__ __PRETTY_FUNCTION__))
;
4292
4293 TargetLowering::MakeLibCallOptions CallOptions;
4294 SplitInteger(TLI.makeLibCall(DAG, LC, VT, Ops, CallOptions, dl).first, Lo, Hi);
4295}
4296
4297void DAGTypeLegalizer::ExpandIntRes_UREM(SDNode *N,
4298 SDValue &Lo, SDValue &Hi) {
4299 EVT VT = N->getValueType(0);
4300 SDLoc dl(N);
4301 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
4302
4303 if (TLI.getOperationAction(ISD::UDIVREM, VT) == TargetLowering::Custom) {
4304 SDValue Res = DAG.getNode(ISD::UDIVREM, dl, DAG.getVTList(VT, VT), Ops);
4305 SplitInteger(Res.getValue(1), Lo, Hi);
4306 return;
4307 }
4308
4309 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
4310 if (VT == MVT::i16)
4311 LC = RTLIB::UREM_I16;
4312 else if (VT == MVT::i32)
4313 LC = RTLIB::UREM_I32;
4314 else if (VT == MVT::i64)
4315 LC = RTLIB::UREM_I64;
4316 else if (VT == MVT::i128)
4317 LC = RTLIB::UREM_I128;
4318 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UREM!")(static_cast <bool> (LC != RTLIB::UNKNOWN_LIBCALL &&
"Unsupported UREM!") ? void (0) : __assert_fail ("LC != RTLIB::UNKNOWN_LIBCALL && \"Unsupported UREM!\""
, "llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp", 4318
, __extension__ __PRETTY_FUNCTION__))
;
4319
4320 TargetLowering::MakeLibCallOptions CallOptions;
4321 SplitInteger(TLI.makeLibCall(DAG, LC, VT, Ops, CallOptions, dl).first, Lo, Hi);
4322}
4323
4324void DAGTypeLegalizer::ExpandIntRes_ZERO_EXTEND(SDNode *N,
4325 SDValue &Lo, SDValue &Hi) {
4326 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
4327 SDLoc dl(N);
4328 SDValue Op = N->getOperand(0);
4329 if (Op.getValueType().bitsLE(NVT)) {
4330 // The low part is zero extension of the input (degenerates to a copy).
4331 Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N->getOperand(0));
4332 Hi = DAG.getConstant(0, dl, NVT); // The high part is just a zero.
4333 } else {
4334 // For example, extension of an i48 to an i64. The operand type necessarily
4335 // promotes to the result type, so will end up being expanded too.
4336 assert(getTypeAction(Op.getValueType()) ==(static_cast <bool> (getTypeAction(Op.getValueType()) ==
TargetLowering::TypePromoteInteger && "Only know how to promote this result!"
) ? void (0) : __assert_fail ("getTypeAction(Op.getValueType()) == TargetLowering::TypePromoteInteger && \"Only know how to promote this result!\""
, "llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp", 4338
, __extension__ __PRETTY_FUNCTION__))
4337 TargetLowering::TypePromoteInteger &&(static_cast <bool> (getTypeAction(Op.getValueType()) ==
TargetLowering::TypePromoteInteger && "Only know how to promote this result!"
) ? void (0) : __assert_fail ("getTypeAction(Op.getValueType()) == TargetLowering::TypePromoteInteger && \"Only know how to promote this result!\""
, "llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp", 4338
, __extension__ __PRETTY_FUNCTION__))
4338 "Only know how to promote this result!")(static_cast <bool> (getTypeAction(Op.getValueType()) ==
TargetLowering::TypePromoteInteger && "Only know how to promote this result!"
) ? void (0) : __assert_fail ("getTypeAction(Op.getValueType()) == TargetLowering::TypePromoteInteger && \"Only know how to promote this result!\""
, "llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp", 4338
, __extension__ __PRETTY_FUNCTION__))
;
4339 SDValue Res = GetPromotedInteger(Op);
4340 assert(Res.getValueType() == N->getValueType(0) &&(static_cast <bool> (Res.getValueType() == N->getValueType
(0) && "Operand over promoted?") ? void (0) : __assert_fail
("Res.getValueType() == N->getValueType(0) && \"Operand over promoted?\""
, "llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp", 4341
, __extension__ __PRETTY_FUNCTION__))
4341 "Operand over promoted?")(static_cast <bool> (Res.getValueType() == N->getValueType
(0) && "Operand over promoted?") ? void (0) : __assert_fail
("Res.getValueType() == N->getValueType(0) && \"Operand over promoted?\""
, "llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp", 4341
, __extension__ __PRETTY_FUNCTION__))
;
4342 // Split the promoted operand. This will simplify when it is expanded.
4343 SplitInteger(Res, Lo, Hi);
4344 unsigned ExcessBits = Op.getValueSizeInBits() - NVT.getSizeInBits();
4345 Hi = DAG.getZeroExtendInReg(Hi, dl,
4346 EVT::getIntegerVT(*DAG.getContext(),
4347 ExcessBits));
4348 }
4349}
4350
4351void DAGTypeLegalizer::ExpandIntRes_ATOMIC_LOAD(SDNode *N,
4352 SDValue &Lo, SDValue &Hi) {
4353 SDLoc dl(N);
4354 EVT VT = cast<AtomicSDNode>(N)->getMemoryVT();
4355 SDVTList VTs = DAG.getVTList(VT, MVT::i1, MVT::Other);
4356 SDValue Zero = DAG.getConstant(0, dl, VT);
4357 SDValue Swap = DAG.getAtomicCmpSwap(
4358 ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, dl,
4359 cast<AtomicSDNode>(N)->getMemoryVT(), VTs, N->getOperand(0),
4360 N->getOperand(1), Zero, Zero, cast<AtomicSDNode>(N)->getMemOperand());
4361
4362 ReplaceValueWith(SDValue(N, 0), Swap.getValue(0));
4363 ReplaceValueWith(SDValue(N, 1), Swap.getValue(2));
4364}
4365
4366void DAGTypeLegalizer::ExpandIntRes_VECREDUCE(SDNode *N,
4367 SDValue &Lo, SDValue &Hi) {
4368 // TODO For VECREDUCE_(AND|OR|XOR) we could split the vector and calculate
4369 // both halves independently.
4370 SDValue Res = TLI.expandVecReduce(N, DAG);
4371 SplitInteger(Res, Lo, Hi);
4372}
4373
4374void DAGTypeLegalizer::ExpandIntRes_Rotate(SDNode *N,
4375 SDValue &Lo, SDValue &Hi) {
4376 // Delegate to funnel-shift expansion.
4377 SDLoc DL(N);
4378 unsigned Opcode = N->getOpcode() == ISD::ROTL ? ISD::FSHL : ISD::FSHR;
4379 SDValue Res = DAG.getNode(Opcode, DL, N->getValueType(0), N->getOperand(0),
4380 N->getOperand(0), N->getOperand(1));
4381 SplitInteger(Res, Lo, Hi);
4382}
4383
4384void DAGTypeLegalizer::ExpandIntRes_FunnelShift(SDNode *N, SDValue &Lo,
4385 SDValue &Hi) {
4386 // Values numbered from least significant to most significant.
4387 SDValue In1, In2, In3, In4;
4388 GetExpandedInteger(N->getOperand(0), In3, In4);
4389 GetExpandedInteger(N->getOperand(1), In1, In2);
4390 EVT HalfVT = In1.getValueType();
4391
4392 SDLoc DL(N);
4393 unsigned Opc = N->getOpcode();
4394 SDValue ShAmt = N->getOperand(2);
4395 EVT ShAmtVT = ShAmt.getValueType();
4396 EVT ShAmtCCVT = getSetCCResultType(ShAmtVT);
4397
4398 // If the shift amount is at least half the bitwidth, swap the inputs.
4399 unsigned HalfVTBits = HalfVT.getScalarSizeInBits();
4400 SDValue AndNode = DAG.getNode(ISD::AND, DL, ShAmtVT, ShAmt,
4401 DAG.getConstant(HalfVTBits, DL, ShAmtVT));
4402 SDValue Cond =
4403 DAG.getSetCC(DL, ShAmtCCVT, AndNode, DAG.getConstant(0, DL, ShAmtVT),
4404 Opc == ISD::FSHL ? ISD::SETNE : ISD::SETEQ);
4405
4406 // Expand to a pair of funnel shifts.
4407 EVT NewShAmtVT = TLI.getShiftAmountTy(HalfVT, DAG.getDataLayout());
4408 SDValue NewShAmt = DAG.getAnyExtOrTrunc(ShAmt, DL, NewShAmtVT);
4409
4410 SDValue Select1 = DAG.getNode(ISD::SELECT, DL, HalfVT, Cond, In1, In2);
4411 SDValue Select2 = DAG.getNode(ISD::SELECT, DL, HalfVT, Cond, In2, In3);
4412 SDValue Select3 = DAG.getNode(ISD::SELECT, DL, HalfVT, Cond, In3, In4);
4413 Lo = DAG.getNode(Opc, DL, HalfVT, Select2, Select1, NewShAmt);
4414 Hi = DAG.getNode(Opc, DL, HalfVT, Select3, Select2, NewShAmt);
4415}
4416
4417void DAGTypeLegalizer::ExpandIntRes_VSCALE(SDNode *N, SDValue &Lo,
4418 SDValue &Hi) {
4419 EVT VT = N->getValueType(0);
4420 EVT HalfVT =
4421 EVT::getIntegerVT(*DAG.getContext(), N->getValueSizeInBits(0) / 2);
4422 SDLoc dl(N);
4423
4424 // We assume VSCALE(1) fits into a legal integer.
4425 APInt One(HalfVT.getSizeInBits(), 1);
4426 SDValue VScaleBase = DAG.getVScale(dl, HalfVT, One);
4427 VScaleBase = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, VScaleBase);
4428 SDValue Res = DAG.getNode(ISD::MUL, dl, VT, VScaleBase, N->getOperand(0));
4429 SplitInteger(Res, Lo, Hi);
4430}
4431
4432//===----------------------------------------------------------------------===//
4433// Integer Operand Expansion
4434//===----------------------------------------------------------------------===//
4435
4436/// ExpandIntegerOperand - This method is called when the specified operand of
4437/// the specified node is found to need expansion. At this point, all of the
4438/// result types of the node are known to be legal, but other operands of the
4439/// node may need promotion or expansion as well as the specified one.
4440bool DAGTypeLegalizer::ExpandIntegerOperand(SDNode *N, unsigned OpNo) {
4441 LLVM_DEBUG(dbgs() << "Expand integer operand: "; N->dump(&DAG);do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("legalize-types")) { dbgs() << "Expand integer operand: "
; N->dump(&DAG); dbgs() << "\n"; } } while (false
)
4442 dbgs() << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("legalize-types")) { dbgs() << "Expand integer operand: "
; N->dump(&DAG); dbgs() << "\n"; } } while (false
)
;
4443 SDValue Res = SDValue();
4444
4445 if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false))
4446 return false;
4447
4448 switch (N->getOpcode()) {
4449 default:
4450 #ifndef NDEBUG
4451 dbgs() << "ExpandIntegerOperand Op #" << OpNo << ": ";
4452 N->dump(&DAG); dbgs() << "\n";
4453 #endif
4454 report_fatal_error("Do not know how to expand this operator's operand!");
4455
4456 case ISD::BITCAST: Res = ExpandOp_BITCAST(N); break;
4457 case ISD::BR_CC: Res = ExpandIntOp_BR_CC(N); break;
4458 case ISD::BUILD_VECTOR: Res = ExpandOp_BUILD_VECTOR(N); break;
4459 case ISD::EXTRACT_ELEMENT: Res = ExpandOp_EXTRACT_ELEMENT(N); break;
4460 case ISD::INSERT_VECTOR_ELT: Res = ExpandOp_INSERT_VECTOR_ELT(N); break;
4461 case ISD::SCALAR_TO_VECTOR: Res = ExpandOp_SCALAR_TO_VECTOR(N); break;
4462 case ISD::SPLAT_VECTOR: Res = ExpandIntOp_SPLAT_VECTOR(N); break;
4463 case ISD::SELECT_CC: Res = ExpandIntOp_SELECT_CC(N); break;
4464 case ISD::SETCC: Res = ExpandIntOp_SETCC(N); break;
4465 case ISD::SETCCCARRY: Res = ExpandIntOp_SETCCCARRY(N); break;
4466 case ISD::STRICT_SINT_TO_FP:
4467 case ISD::SINT_TO_FP: Res = ExpandIntOp_SINT_TO_FP(N); break;
4468 case ISD::STORE: Res = ExpandIntOp_STORE(cast<StoreSDNode>(N), OpNo); break;
4469 case ISD::TRUNCATE: Res = ExpandIntOp_TRUNCATE(N); break;
4470 case ISD::STRICT_UINT_TO_FP:
4471 case ISD::UINT_TO_FP: Res = ExpandIntOp_UINT_TO_FP(N); break;
4472
4473 case ISD::SHL:
4474 case ISD::SRA:
4475 case ISD::SRL:
4476 case ISD::ROTL:
4477 case ISD::ROTR: Res = ExpandIntOp_Shift(N); break;
4478 case ISD::RETURNADDR:
4479 case ISD::FRAMEADDR: Res = ExpandIntOp_RETURNADDR(N); break;
4480
4481 case ISD::ATOMIC_STORE: Res = ExpandIntOp_ATOMIC_STORE(N); break;
4482 }
4483
4484 // If the result is null, the sub-method took care of registering results etc.
4485 if (!Res.getNode()) return false;
4486
4487 // If the result is N, the sub-method updated N in place. Tell the legalizer
4488 // core about this.
4489 if (Res.getNode() == N)
4490 return true;
4491
4492 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&(static_cast <bool> (Res.getValueType() == N->getValueType
(0) && N->getNumValues() == 1 && "Invalid operand expansion"
) ? void (0) : __assert_fail ("Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 && \"Invalid operand expansion\""
, "llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp", 4493
, __extension__ __PRETTY_FUNCTION__))
4493 "Invalid operand expansion")(static_cast <bool> (Res.getValueType() == N->getValueType
(0) && N->getNumValues() == 1 && "Invalid operand expansion"
) ? void (0) : __assert_fail ("Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 && \"Invalid operand expansion\""
, "llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp", 4493
, __extension__ __PRETTY_FUNCTION__))
;
4494
4495 ReplaceValueWith(SDValue(N, 0), Res);
4496 return false;
4497}
4498
4499/// IntegerExpandSetCCOperands - Expand the operands of a comparison. This code
4500/// is shared among BR_CC, SELECT_CC, and SETCC handlers.
4501void DAGTypeLegalizer::IntegerExpandSetCCOperands(SDValue &NewLHS,
4502 SDValue &NewRHS,
4503 ISD::CondCode &CCCode,
4504 const SDLoc &dl) {
4505 SDValue LHSLo, LHSHi, RHSLo, RHSHi;
4506 GetExpandedInteger(NewLHS, LHSLo, LHSHi);
4507 GetExpandedInteger(NewRHS, RHSLo, RHSHi);
4508
4509 if (CCCode == ISD::SETEQ || CCCode == ISD::SETNE) {
4510 if (RHSLo == RHSHi) {
4511 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo)) {
4512 if (RHSCST->isAllOnes()) {
4513 // Equality comparison to -1.
4514 NewLHS = DAG.getNode(ISD::AND, dl,
4515 LHSLo.getValueType(), LHSLo, LHSHi);
4516 NewRHS = RHSLo;
4517 return;
4518 }
4519 }
4520 }
4521
4522 NewLHS = DAG.getNode(ISD::XOR, dl, LHSLo.getValueType(), LHSLo, RHSLo);
4523 NewRHS = DAG.getNode(ISD::XOR, dl, LHSLo.getValueType(), LHSHi, RHSHi);
4524 NewLHS = DAG.getNode(ISD::OR, dl, NewLHS.getValueType(), NewLHS, NewRHS);
4525 NewRHS = DAG.getConstant(0, dl, NewLHS.getValueType());
4526 return;
4527 }
4528
4529 // If this is a comparison of the sign bit, just look at the top part.
4530 // X > -1, x < 0
4531 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(NewRHS))
4532 if ((CCCode == ISD::SETLT && CST->isZero()) || // X < 0
4533 (CCCode == ISD::SETGT && CST->isAllOnes())) { // X > -1
4534 NewLHS = LHSHi;
4535 NewRHS = RHSHi;
4536 return;
4537 }
4538
4539 // FIXME: This generated code sucks.
4540 ISD::CondCode LowCC;
4541 switch (CCCode) {
4542 default: llvm_unreachable("Unknown integer setcc!")::llvm::llvm_unreachable_internal("Unknown integer setcc!", "llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 4542)
;
4543 case ISD::SETLT:
4544 case ISD::SETULT: LowCC = ISD::SETULT; break;
4545 case ISD::SETGT:
4546 case ISD::SETUGT: LowCC = ISD::SETUGT; break;
4547 case ISD::SETLE:
4548 case ISD::SETULE: LowCC = ISD::SETULE; break;
4549 case ISD::SETGE:
4550 case ISD::SETUGE: LowCC = ISD::SETUGE; break;
4551 }
4552
4553 // LoCmp = lo(op1) < lo(op2) // Always unsigned comparison
4554 // HiCmp = hi(op1) < hi(op2) // Signedness depends on operands
4555 // dest = hi(op1) == hi(op2) ? LoCmp : HiCmp;
4556
4557 // NOTE: on targets without efficient SELECT of bools, we can always use
4558 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3)
4559 TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, AfterLegalizeTypes, true,
4560 nullptr);
4561 SDValue LoCmp, HiCmp;
4562 if (TLI.isTypeLegal(LHSLo.getValueType()) &&
4563 TLI.isTypeLegal(RHSLo.getValueType()))
4564 LoCmp = TLI.SimplifySetCC(getSetCCResultType(LHSLo.getValueType()), LHSLo,
4565 RHSLo, LowCC, false, DagCombineInfo, dl);
4566 if (!LoCmp.getNode())
4567 LoCmp = DAG.getSetCC(dl, getSetCCResultType(LHSLo.getValueType()), LHSLo,
4568 RHSLo, LowCC);
4569 if (TLI.isTypeLegal(LHSHi.getValueType()) &&
4570 TLI.isTypeLegal(RHSHi.getValueType()))
4571 HiCmp = TLI.SimplifySetCC(getSetCCResultType(LHSHi.getValueType()), LHSHi,
4572 RHSHi, CCCode, false, DagCombineInfo, dl);
4573 if (!HiCmp.getNode())
4574 HiCmp =
4575 DAG.getNode(ISD::SETCC, dl, getSetCCResultType(LHSHi.getValueType()),
4576 LHSHi, RHSHi, DAG.getCondCode(CCCode));
4577
4578 ConstantSDNode *LoCmpC = dyn_cast<ConstantSDNode>(LoCmp.getNode());
4579 ConstantSDNode *HiCmpC = dyn_cast<ConstantSDNode>(HiCmp.getNode());
4580
4581 bool EqAllowed = (CCCode == ISD::SETLE || CCCode == ISD::SETGE ||
4582 CCCode == ISD::SETUGE || CCCode == ISD::SETULE);
4583
4584 // FIXME: Is the HiCmpC->isOne() here correct for
4585 // ZeroOrNegativeOneBooleanContent.
4586 if ((EqAllowed && (HiCmpC && HiCmpC->isZero())) ||
4587 (!EqAllowed &&
4588 ((HiCmpC && HiCmpC->isOne()) || (LoCmpC && LoCmpC->isZero())))) {
4589 // For LE / GE, if high part is known false, ignore the low part.
4590 // For LT / GT: if low part is known false, return the high part.
4591 // if high part is known true, ignore the low part.
4592 NewLHS = HiCmp;
4593 NewRHS = SDValue();
4594 return;
4595 }
4596
4597 if (LHSHi == RHSHi) {
4598 // Comparing the low bits is enough.
4599 NewLHS = LoCmp;
4600 NewRHS = SDValue();
4601 return;
4602 }
4603
4604 // Lower with SETCCCARRY if the target supports it.
4605 EVT HiVT = LHSHi.getValueType();
4606 EVT ExpandVT = TLI.getTypeToExpandTo(*DAG.getContext(), HiVT);
4607 bool HasSETCCCARRY = TLI.isOperationLegalOrCustom(ISD::SETCCCARRY, ExpandVT);
4608
4609 // FIXME: Make all targets support this, then remove the other lowering.
4610 if (HasSETCCCARRY) {
4611 // SETCCCARRY can detect < and >= directly. For > and <=, flip
4612 // operands and condition code.
4613 bool FlipOperands = false;
4614 switch (CCCode) {
4615 case ISD::SETGT: CCCode = ISD::SETLT; FlipOperands = true; break;
4616 case ISD::SETUGT: CCCode = ISD::SETULT; FlipOperands = true; break;
4617 case ISD::SETLE: CCCode = ISD::SETGE; FlipOperands = true; break;
4618 case ISD::SETULE: CCCode = ISD::SETUGE; FlipOperands = true; break;
4619 default: break;
4620 }
4621 if (FlipOperands) {
4622 std::swap(LHSLo, RHSLo);
4623 std::swap(LHSHi, RHSHi);
4624 }
4625 // Perform a wide subtraction, feeding the carry from the low part into
4626 // SETCCCARRY. The SETCCCARRY operation is essentially looking at the high
4627 // part of the result of LHS - RHS. It is negative iff LHS < RHS. It is
4628 // zero or positive iff LHS >= RHS.
4629 EVT LoVT = LHSLo.getValueType();
4630 SDVTList VTList = DAG.getVTList(LoVT, getSetCCResultType(LoVT));
4631 SDValue LowCmp = DAG.getNode(ISD::USUBO, dl, VTList, LHSLo, RHSLo);
4632 SDValue Res = DAG.getNode(ISD::SETCCCARRY, dl, getSetCCResultType(HiVT),
4633 LHSHi, RHSHi, LowCmp.getValue(1),
4634 DAG.getCondCode(CCCode));
4635 NewLHS = Res;
4636 NewRHS = SDValue();
4637 return;
4638 }
4639
4640 NewLHS = TLI.SimplifySetCC(getSetCCResultType(HiVT), LHSHi, RHSHi, ISD::SETEQ,
4641 false, DagCombineInfo, dl);
4642 if (!NewLHS.getNode())
4643 NewLHS =
4644 DAG.getSetCC(dl, getSetCCResultType(HiVT), LHSHi, RHSHi, ISD::SETEQ);
4645 NewLHS = DAG.getSelect(dl, LoCmp.getValueType(), NewLHS, LoCmp, HiCmp);
4646 NewRHS = SDValue();
4647}
4648
4649SDValue DAGTypeLegalizer::ExpandIntOp_BR_CC(SDNode *N) {
4650 SDValue NewLHS = N->getOperand(2), NewRHS = N->getOperand(3);
4651 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(1))->get();
4652 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, SDLoc(N));
4653
4654 // If ExpandSetCCOperands returned a scalar, we need to compare the result
4655 // against zero to select between true and false values.
4656 if (!NewRHS.getNode()) {
4657 NewRHS = DAG.getConstant(0, SDLoc(N), NewLHS.getValueType());
4658 CCCode = ISD::SETNE;
4659 }
4660
4661 // Update N to have the operands specified.
4662 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
4663 DAG.getCondCode(CCCode), NewLHS, NewRHS,
4664 N->getOperand(4)), 0);
4665}
4666
4667SDValue DAGTypeLegalizer::ExpandIntOp_SELECT_CC(SDNode *N) {
4668 SDValue NewLHS = N->getOperand(0), NewRHS = N->getOperand(1);
4669 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(4))->get();
4670 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, SDLoc(N));
4671
4672 // If ExpandSetCCOperands returned a scalar, we need to compare the result
4673 // against zero to select between true and false values.
4674 if (!NewRHS.getNode()) {
4675 NewRHS = DAG.getConstant(0, SDLoc(N), NewLHS.getValueType());
4676 CCCode = ISD::SETNE;
4677 }
4678
4679 // Update N to have the operands specified.
4680 return SDValue(DAG.UpdateNodeOperands(N, NewLHS, NewRHS,
4681 N->getOperand(2), N->getOperand(3),
4682 DAG.getCondCode(CCCode)), 0);
4683}
4684
4685SDValue DAGTypeLegalizer::ExpandIntOp_SETCC(SDNode *N) {
4686 SDValue NewLHS = N->getOperand(0), NewRHS = N->getOperand(1);
4687 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(2))->get();
4688 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, SDLoc(N));
4689
4690 // If ExpandSetCCOperands returned a scalar, use it.
4691 if (!NewRHS.getNode()) {
4692 assert(NewLHS.getValueType() == N->getValueType(0) &&(static_cast <bool> (NewLHS.getValueType() == N->getValueType
(0) && "Unexpected setcc expansion!") ? void (0) : __assert_fail
("NewLHS.getValueType() == N->getValueType(0) && \"Unexpected setcc expansion!\""
, "llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp", 4693
, __extension__ __PRETTY_FUNCTION__))
4693 "Unexpected setcc expansion!")(static_cast <bool> (NewLHS.getValueType() == N->getValueType
(0) && "Unexpected setcc expansion!") ? void (0) : __assert_fail
("NewLHS.getValueType() == N->getValueType(0) && \"Unexpected setcc expansion!\""
, "llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp", 4693
, __extension__ __PRETTY_FUNCTION__))
;
4694 return NewLHS;
4695 }
4696
4697 // Otherwise, update N to have the operands specified.
4698 return SDValue(
4699 DAG.UpdateNodeOperands(N, NewLHS, NewRHS, DAG.getCondCode(CCCode)), 0);
4700}
4701
4702SDValue DAGTypeLegalizer::ExpandIntOp_SETCCCARRY(SDNode *N) {
4703 SDValue LHS = N->getOperand(0);
4704 SDValue RHS = N->getOperand(1);
4705 SDValue Carry = N->getOperand(2);
4706 SDValue Cond = N->getOperand(3);
4707 SDLoc dl = SDLoc(N);
4708
4709 SDValue LHSLo, LHSHi, RHSLo, RHSHi;
4710 GetExpandedInteger(LHS, LHSLo, LHSHi);
4711 GetExpandedInteger(RHS, RHSLo, RHSHi);
4712
4713 // Expand to a SUBE for the low part and a smaller SETCCCARRY for the high.
4714 SDVTList VTList = DAG.getVTList(LHSLo.getValueType(), Carry.getValueType());
4715 SDValue LowCmp = DAG.getNode(ISD::SUBCARRY, dl, VTList, LHSLo, RHSLo, Carry);
4716 return DAG.getNode(ISD::SETCCCARRY, dl, N->getValueType(0), LHSHi, RHSHi,
4717 LowCmp.getValue(1), Cond);
4718}
4719
4720SDValue DAGTypeLegalizer::ExpandIntOp_SPLAT_VECTOR(SDNode *N) {
4721 // Split the operand and replace with SPLAT_VECTOR_PARTS.
4722 SDValue Lo, Hi;
4723 GetExpandedInteger(N->getOperand(0), Lo, Hi);
4724 return DAG.getNode(ISD::SPLAT_VECTOR_PARTS, SDLoc(N), N->getValueType(0), Lo,
4725 Hi);
4726}
4727
4728SDValue DAGTypeLegalizer::ExpandIntOp_Shift(SDNode *N) {
4729 // The value being shifted is legal, but the shift amount is too big.
4730 // It follows that either the result of the shift is undefined, or the
4731 // upper half of the shift amount is zero. Just use the lower half.
4732 SDValue Lo, Hi;
4733 GetExpandedInteger(N->getOperand(1), Lo, Hi);
4734 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0), Lo), 0);
4735}
4736
4737SDValue DAGTypeLegalizer::ExpandIntOp_RETURNADDR(SDNode *N) {
4738 // The argument of RETURNADDR / FRAMEADDR builtin is 32 bit contant. This
4739 // surely makes pretty nice problems on 8/16 bit targets. Just truncate this
4740 // constant to valid type.
4741 SDValue Lo, Hi;
4742 GetExpandedInteger(N->getOperand(0), Lo, Hi);
4743 return SDValue(DAG.UpdateNodeOperands(N, Lo), 0);
4744}
4745
4746SDValue DAGTypeLegalizer::ExpandIntOp_SINT_TO_FP(SDNode *N) {
4747 bool IsStrict = N->isStrictFPOpcode();
4748 SDValue Chain = IsStrict ? N->getOperand(0) : SDValue();
4749 SDValue Op = N->getOperand(IsStrict ? 1 : 0);
4750 EVT DstVT = N->getValueType(0);
4751 RTLIB::Libcall LC = RTLIB::getSINTTOFP(Op.getValueType(), DstVT);
4752 assert(LC != RTLIB::UNKNOWN_LIBCALL &&(static_cast <bool> (LC != RTLIB::UNKNOWN_LIBCALL &&
"Don't know how to expand this SINT_TO_FP!") ? void (0) : __assert_fail
("LC != RTLIB::UNKNOWN_LIBCALL && \"Don't know how to expand this SINT_TO_FP!\""
, "llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp", 4753
, __extension__ __PRETTY_FUNCTION__))
4753 "Don't know how to expand this SINT_TO_FP!")(static_cast <bool> (LC != RTLIB::UNKNOWN_LIBCALL &&
"Don't know how to expand this SINT_TO_FP!") ? void (0) : __assert_fail
("LC != RTLIB::UNKNOWN_LIBCALL && \"Don't know how to expand this SINT_TO_FP!\""
, "llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp", 4753
, __extension__ __PRETTY_FUNCTION__))
;
4754 TargetLowering::MakeLibCallOptions CallOptions;
4755 CallOptions.setSExt(true);
4756 std::pair<SDValue, SDValue> Tmp =
4757 TLI.makeLibCall(DAG, LC, DstVT, Op, CallOptions, SDLoc(N), Chain);
4758
4759 if (!IsStrict)
4760 return Tmp.first;
4761
4762 ReplaceValueWith(SDValue(N, 1), Tmp.second);
4763 ReplaceValueWith(SDValue(N, 0), Tmp.first);
4764 return SDValue();
4765}
4766
4767SDValue DAGTypeLegalizer::ExpandIntOp_STORE(StoreSDNode *N, unsigned OpNo) {
4768 if (N->isAtomic()) {
4769 // It's typical to have larger CAS than atomic store instructions.
4770 SDLoc dl(N);
4771 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
4772 N->getMemoryVT(),
4773 N->getOperand(0), N->getOperand(2),
4774 N->getOperand(1),
4775 N->getMemOperand());
4776 return Swap.getValue(1);
4777 }
4778 if (ISD::isNormalStore(N))
4779 return ExpandOp_NormalStore(N, OpNo);
4780
4781 assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!")(static_cast <bool> (ISD::isUNINDEXEDStore(N) &&
"Indexed store during type legalization!") ? void (0) : __assert_fail
("ISD::isUNINDEXEDStore(N) && \"Indexed store during type legalization!\""
, "llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp", 4781
, __extension__ __PRETTY_FUNCTION__))
;
4782 assert(OpNo == 1 && "Can only expand the stored value so far")(static_cast <bool> (OpNo == 1 && "Can only expand the stored value so far"
) ? void (0) : __assert_fail ("OpNo == 1 && \"Can only expand the stored value so far\""
, "llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp", 4782
, __extension__ __PRETTY_FUNCTION__))
;
4783
4784 EVT VT = N->getOperand(1).getValueType();
4785 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
4786 SDValue Ch = N->getChain();
4787 SDValue Ptr = N->getBasePtr();
4788 MachineMemOperand::Flags MMOFlags = N->getMemOperand()->getFlags();
4789 AAMDNodes AAInfo = N->getAAInfo();
4790 SDLoc dl(N);
4791 SDValue Lo, Hi;
4792
4793 assert(NVT.isByteSized() && "Expanded type not byte sized!")(static_cast <bool> (NVT.isByteSized() && "Expanded type not byte sized!"
) ? void (0) : __assert_fail ("NVT.isByteSized() && \"Expanded type not byte sized!\""
, "llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp", 4793
, __extension__ __PRETTY_FUNCTION__))
;
4794
4795 if (N->getMemoryVT().bitsLE(NVT)) {
4796 GetExpandedInteger(N->getValue(), Lo, Hi);
4797 return DAG.getTruncStore(Ch, dl, Lo, Ptr, N->getPointerInfo(),
4798 N->getMemoryVT(), N->getOriginalAlign(), MMOFlags,
4799 AAInfo);
4800 }
4801
4802 if (DAG.getDataLayout().isLittleEndian()) {
4803 // Little-endian - low bits are at low addresses.
4804 GetExpandedInteger(N->getValue(), Lo, Hi);
4805
4806 Lo = DAG.getStore(Ch, dl, Lo, Ptr, N->getPointerInfo(),
4807 N->getOriginalAlign(), MMOFlags, AAInfo);
4808
4809 unsigned ExcessBits =
4810 N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits();
4811 EVT NEVT = EVT::getIntegerVT(*DAG.getContext(), ExcessBits);
4812
4813 // Increment the pointer to the other half.
4814 unsigned IncrementSize = NVT.getSizeInBits()/8;
4815 Ptr = DAG.getObjectPtrOffset(dl, Ptr, TypeSize::Fixed(IncrementSize));
4816 Hi = DAG.getTruncStore(Ch, dl, Hi, Ptr,
4817 N->getPointerInfo().getWithOffset(IncrementSize),
4818 NEVT, N->getOriginalAlign(), MMOFlags, AAInfo);
4819 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
4820 }
4821
4822 // Big-endian - high bits are at low addresses. Favor aligned stores at
4823 // the cost of some bit-fiddling.
4824 GetExpandedInteger(N->getValue(), Lo, Hi);
4825
4826 EVT ExtVT = N->getMemoryVT();
4827 unsigned EBytes = ExtVT.getStoreSize();
4828 unsigned IncrementSize = NVT.getSizeInBits()/8;
4829 unsigned ExcessBits = (EBytes - IncrementSize)*8;
4830 EVT HiVT = EVT::getIntegerVT(*DAG.getContext(),
4831 ExtVT.getSizeInBits() - ExcessBits);
4832
4833 if (ExcessBits < NVT.getSizeInBits()) {
4834 // Transfer high bits from the top of Lo to the bottom of Hi.
4835 Hi = DAG.getNode(ISD::SHL, dl, NVT, Hi,
4836 DAG.getConstant(NVT.getSizeInBits() - ExcessBits, dl,
4837 TLI.getPointerTy(DAG.getDataLayout())));
4838 Hi = DAG.getNode(
4839 ISD::OR, dl, NVT, Hi,
4840 DAG.getNode(ISD::SRL, dl, NVT, Lo,
4841 DAG.getConstant(ExcessBits, dl,
4842 TLI.getPointerTy(DAG.getDataLayout()))));
4843 }
4844
4845 // Store both the high bits and maybe some of the low bits.
4846 Hi = DAG.getTruncStore(Ch, dl, Hi, Ptr, N->getPointerInfo(), HiVT,
4847 N->getOriginalAlign(), MMOFlags, AAInfo);
4848
4849 // Increment the pointer to the other half.
4850 Ptr = DAG.getObjectPtrOffset(dl, Ptr, TypeSize::Fixed(IncrementSize));
4851 // Store the lowest ExcessBits bits in the second half.
4852 Lo = DAG.getTruncStore(Ch, dl, Lo, Ptr,
4853 N->getPointerInfo().getWithOffset(IncrementSize),
4854 EVT::getIntegerVT(*DAG.getContext(), ExcessBits),
4855 N->getOriginalAlign(), MMOFlags, AAInfo);
4856 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
4857}
4858
4859SDValue DAGTypeLegalizer::ExpandIntOp_TRUNCATE(SDNode *N) {
4860 SDValue InL, InH;
4861 GetExpandedInteger(N->getOperand(0), InL, InH);
4862 // Just truncate the low part of the source.
4863 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), N->getValueType(0), InL);
4864}
4865
4866SDValue DAGTypeLegalizer::ExpandIntOp_UINT_TO_FP(SDNode *N) {
4867 bool IsStrict = N->isStrictFPOpcode();
4868 SDValue Chain = IsStrict ? N->getOperand(0) : SDValue();
4869 SDValue Op = N->getOperand(IsStrict ? 1 : 0);
4870 EVT DstVT = N->getValueType(0);
4871 RTLIB::Libcall LC = RTLIB::getUINTTOFP(Op.getValueType(), DstVT);
4872 assert(LC != RTLIB::UNKNOWN_LIBCALL &&(static_cast <bool> (LC != RTLIB::UNKNOWN_LIBCALL &&
"Don't know how to expand this UINT_TO_FP!") ? void (0) : __assert_fail
("LC != RTLIB::UNKNOWN_LIBCALL && \"Don't know how to expand this UINT_TO_FP!\""
, "llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp", 4873
, __extension__ __PRETTY_FUNCTION__))
4873 "Don't know how to expand this UINT_TO_FP!")(static_cast <bool> (LC != RTLIB::UNKNOWN_LIBCALL &&
"Don't know how to expand this UINT_TO_FP!") ? void (0) : __assert_fail
("LC != RTLIB::UNKNOWN_LIBCALL && \"Don't know how to expand this UINT_TO_FP!\""
, "llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp", 4873
, __extension__ __PRETTY_FUNCTION__))
;
4874 TargetLowering::MakeLibCallOptions CallOptions;
4875 CallOptions.setSExt(true);
4876 std::pair<SDValue, SDValue> Tmp =
4877 TLI.makeLibCall(DAG, LC, DstVT, Op, CallOptions, SDLoc(N), Chain);
4878
4879 if (!IsStrict)
4880 return Tmp.first;
4881
4882 ReplaceValueWith(SDValue(N, 1), Tmp.second);
4883 ReplaceValueWith(SDValue(N, 0), Tmp.first);
4884 return SDValue();
4885}
4886
4887SDValue DAGTypeLegalizer::ExpandIntOp_ATOMIC_STORE(SDNode *N) {
4888 SDLoc dl(N);
4889 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
4890 cast<AtomicSDNode>(N)->getMemoryVT(),
4891 N->getOperand(0),
4892 N->getOperand(1), N->getOperand(2),
4893 cast<AtomicSDNode>(N)->getMemOperand());
4894 return Swap.getValue(1);
4895}
4896
4897SDValue DAGTypeLegalizer::PromoteIntRes_VECTOR_SPLICE(SDNode *N) {
4898 SDLoc dl(N);
4899
4900 SDValue V0 = GetPromotedInteger(N->getOperand(0));
4901 SDValue V1 = GetPromotedInteger(N->getOperand(1));
4902 EVT OutVT = V0.getValueType();
4903
4904 return DAG.getNode(ISD::VECTOR_SPLICE, dl, OutVT, V0, V1, N->getOperand(2));
4905}
4906
4907SDValue DAGTypeLegalizer::PromoteIntRes_EXTRACT_SUBVECTOR(SDNode *N) {
4908
4909 EVT OutVT = N->getValueType(0);
4910 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
4911 assert(NOutVT.isVector() && "This type must be promoted to a vector type")(static_cast <bool> (NOutVT.isVector() && "This type must be promoted to a vector type"
) ? void (0) : __assert_fail ("NOutVT.isVector() && \"This type must be promoted to a vector type\""
, "llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp", 4911
, __extension__ __PRETTY_FUNCTION__))
;
4912 EVT NOutVTElem = NOutVT.getVectorElementType();
4913
4914 SDLoc dl(N);
4915 SDValue BaseIdx = N->getOperand(1);
4916
4917 // TODO: We may be able to use this for types other than scalable
4918 // vectors and fix those tests that expect BUILD_VECTOR to be used
4919 if (OutVT.isScalableVector()) {
4920 SDValue InOp0 = N->getOperand(0);
4921 EVT InVT = InOp0.getValueType();
4922
4923 // Try and extract from a smaller type so that it eventually falls
4924 // into the promotion code below.
4925 if (getTypeAction(InVT) == TargetLowering::TypeSplitVector ||
4926 getTypeAction(InVT) == TargetLowering::TypeLegal) {
4927 EVT NInVT = InVT.getHalfNumVectorElementsVT(*DAG.getContext());
4928 unsigned NElts = NInVT.getVectorMinNumElements();
4929 uint64_t IdxVal = cast<ConstantSDNode>(BaseIdx)->getZExtValue();
4930
4931 SDValue Step1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NInVT, InOp0,
4932 DAG.getConstant(alignDown(IdxVal, NElts), dl,
4933 BaseIdx.getValueType()));
4934 SDValue Step2 = DAG.getNode(
4935 ISD::EXTRACT_SUBVECTOR, dl, OutVT, Step1,
4936 DAG.getConstant(IdxVal % NElts, dl, BaseIdx.getValueType()));
4937 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, Step2);
4938 }
4939
4940 // Try and extract from a widened type.
4941 if (getTypeAction(InVT) == TargetLowering::TypeWidenVector) {
4942 SDValue Ops[] = {GetWidenedVector(InOp0), BaseIdx};
4943 SDValue Ext = DAG.getNode(ISD::EXTRACT_SUBVECTOR, SDLoc(N), OutVT, Ops);
4944 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, Ext);
4945 }
4946
4947 // Promote operands and see if this is handled by target lowering,
4948 // Otherwise, use the BUILD_VECTOR approach below
4949 if (getTypeAction(InVT) == TargetLowering::TypePromoteInteger) {
4950 // Collect the (promoted) operands
4951 SDValue Ops[] = { GetPromotedInteger(InOp0), BaseIdx };
4952
4953 EVT PromEltVT = Ops[0].getValueType().getVectorElementType();
4954 assert(PromEltVT.bitsLE(NOutVTElem) &&(static_cast <bool> (PromEltVT.bitsLE(NOutVTElem) &&
"Promoted operand has an element type greater than result") ?
void (0) : __assert_fail ("PromEltVT.bitsLE(NOutVTElem) && \"Promoted operand has an element type greater than result\""
, "llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp", 4955
, __extension__ __PRETTY_FUNCTION__))
4955 "Promoted operand has an element type greater than result")(static_cast <bool> (PromEltVT.bitsLE(NOutVTElem) &&
"Promoted operand has an element type greater than result") ?
void (0) : __assert_fail ("PromEltVT.bitsLE(NOutVTElem) && \"Promoted operand has an element type greater than result\""
, "llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp", 4955
, __extension__ __PRETTY_FUNCTION__))
;
4956
4957 EVT ExtVT = NOutVT.changeVectorElementType(PromEltVT);
4958 SDValue Ext = DAG.getNode(ISD::EXTRACT_SUBVECTOR, SDLoc(N), ExtVT, Ops);
4959 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, Ext);
4960 }
4961 }
4962
4963 if (OutVT.isScalableVector())
4964 report_fatal_error("Unable to promote scalable types using BUILD_VECTOR");
4965
4966 SDValue InOp0 = N->getOperand(0);
4967 if (getTypeAction(InOp0.getValueType()) == TargetLowering::TypePromoteInteger)
4968 InOp0 = GetPromotedInteger(N->getOperand(0));
4969
4970 EVT InVT = InOp0.getValueType();
4971
4972 unsigned OutNumElems = OutVT.getVectorNumElements();
4973 SmallVector<SDValue, 8> Ops;
4974 Ops.reserve(OutNumElems);
4975 for (unsigned i = 0; i != OutNumElems; ++i) {
4976
4977 // Extract the element from the original vector.
4978 SDValue Index = DAG.getNode(ISD::ADD, dl, BaseIdx.getValueType(),
4979 BaseIdx, DAG.getConstant(i, dl, BaseIdx.getValueType()));
4980 SDValue Ext = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
4981 InVT.getVectorElementType(), N->getOperand(0), Index);
4982
4983 SDValue Op = DAG.getAnyExtOrTrunc(Ext, dl, NOutVTElem);
4984 // Insert the converted element to the new vector.
4985 Ops.push_back(Op);
4986 }
4987
4988 return DAG.getBuildVector(NOutVT, dl, Ops);
4989}
4990
4991SDValue DAGTypeLegalizer::PromoteIntRes_INSERT_SUBVECTOR(SDNode *N) {
4992 EVT OutVT = N->getValueType(0);
4993 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
4994 assert(NOutVT.isVector() && "This type must be promoted to a vector type")(static_cast <bool> (NOutVT.isVector() && "This type must be promoted to a vector type"
) ? void (0) : __assert_fail ("NOutVT.isVector() && \"This type must be promoted to a vector type\""
, "llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp", 4994
, __extension__ __PRETTY_FUNCTION__))
;
4995
4996 SDLoc dl(N);
4997 SDValue Vec = N->getOperand(0);
4998 SDValue SubVec = N->getOperand(1);
4999 SDValue Idx = N->getOperand(2);
5000
5001 EVT SubVecVT = SubVec.getValueType();
5002 EVT NSubVT =
5003 EVT::getVectorVT(*DAG.getContext(), NOutVT.getVectorElementType(),
5004 SubVecVT.getVectorElementCount());
5005
5006 Vec = GetPromotedInteger(Vec);
5007 SubVec = DAG.getNode(ISD::ANY_EXTEND, dl, NSubVT, SubVec);
5008
5009 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, NOutVT, Vec, SubVec, Idx);
5010}
5011
5012SDValue DAGTypeLegalizer::PromoteIntRes_VECTOR_REVERSE(SDNode *N) {
5013 SDLoc dl(N);
5014
5015 SDValue V0 = GetPromotedInteger(N->getOperand(0));
5016 EVT OutVT = V0.getValueType();
5017
5018 return DAG.getNode(ISD::VECTOR_REVERSE, dl, OutVT, V0);
5019}
5020
5021SDValue DAGTypeLegalizer::PromoteIntRes_VECTOR_SHUFFLE(SDNode *N) {
5022 ShuffleVectorSDNode *SV = cast<ShuffleVectorSDNode>(N);
5023 EVT VT = N->getValueType(0);
5024 SDLoc dl(N);
5025
5026 ArrayRef<int> NewMask = SV->getMask().slice(0, VT.getVectorNumElements());
5027
5028 SDValue V0 = GetPromotedInteger(N->getOperand(0));
5029 SDValue V1 = GetPromotedInteger(N->getOperand(1));
5030 EVT OutVT = V0.getValueType();
5031
5032 return DAG.getVectorShuffle(OutVT, dl, V0, V1, NewMask);
5033}
5034
5035
5036SDValue DAGTypeLegalizer::PromoteIntRes_BUILD_VECTOR(SDNode *N) {
5037 EVT OutVT = N->getValueType(0);
5038 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
5039 assert(NOutVT.isVector() && "This type must be promoted to a vector type")(static_cast <bool> (NOutVT.isVector() && "This type must be promoted to a vector type"
) ? void (0) : __assert_fail ("NOutVT.isVector() && \"This type must be promoted to a vector type\""
, "llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp", 5039
, __extension__ __PRETTY_FUNCTION__))
;
5040 unsigned NumElems = N->getNumOperands();
5041 EVT NOutVTElem = NOutVT.getVectorElementType();
5042
5043 SDLoc dl(N);
5044
5045 SmallVector<SDValue, 8> Ops;
5046 Ops.reserve(NumElems);
5047 for (unsigned i = 0; i != NumElems; ++i) {
5048 SDValue Op;
5049 // BUILD_VECTOR integer operand types are allowed to be larger than the
5050 // result's element type. This may still be true after the promotion. For
5051 // example, we might be promoting (<v?i1> = BV <i32>, <i32>, ...) to
5052 // (v?i16 = BV <i32>, <i32>, ...), and we can't any_extend <i32> to <i16>.
5053 if (N->getOperand(i).getValueType().bitsLT(NOutVTElem))
5054 Op = DAG.getNode(ISD::ANY_EXTEND, dl, NOutVTElem, N->getOperand(i));
5055 else
5056 Op = N->getOperand(i);
5057 Ops.push_back(Op);
5058 }
5059
5060 return DAG.getBuildVector(NOutVT, dl, Ops);
5061}
5062
5063SDValue DAGTypeLegalizer::PromoteIntRes_SCALAR_TO_VECTOR(SDNode *N) {
5064
5065 SDLoc dl(N);
5066
5067 assert(!N->getOperand(0).getValueType().isVector() &&(static_cast <bool> (!N->getOperand(0).getValueType(
).isVector() && "Input must be a scalar") ? void (0) :
__assert_fail ("!N->getOperand(0).getValueType().isVector() && \"Input must be a scalar\""
, "llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp", 5068
, __extension__ __PRETTY_FUNCTION__))
5068 "Input must be a scalar")(static_cast <bool> (!N->getOperand(0).getValueType(
).isVector() && "Input must be a scalar") ? void (0) :
__assert_fail ("!N->getOperand(0).getValueType().isVector() && \"Input must be a scalar\""
, "llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp", 5068
, __extension__ __PRETTY_FUNCTION__))
;
5069
5070 EVT OutVT = N->getValueType(0);
5071 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
5072 assert(NOutVT.isVector() && "This type must be promoted to a vector type")(static_cast <bool> (NOutVT.isVector() && "This type must be promoted to a vector type"
) ? void (0) : __assert_fail ("NOutVT.isVector() && \"This type must be promoted to a vector type\""
, "llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp", 5072
, __extension__ __PRETTY_FUNCTION__))
;
5073 EVT NOutVTElem = NOutVT.getVectorElementType();
5074
5075 SDValue Op = DAG.getNode(ISD::ANY_EXTEND, dl, NOutVTElem, N->getOperand(0));
5076
5077 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, NOutVT, Op);
5078}
5079
5080SDValue DAGTypeLegalizer::PromoteIntRes_SPLAT_VECTOR(SDNode *N) {
5081 SDLoc dl(N);
5082
5083 SDValue SplatVal = N->getOperand(0);
5084
5085 assert(!SplatVal.getValueType().isVector() && "Input must be a scalar")(static_cast <bool> (!SplatVal.getValueType().isVector(
) && "Input must be a scalar") ? void (0) : __assert_fail
("!SplatVal.getValueType().isVector() && \"Input must be a scalar\""
, "llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp", 5085
, __extension__ __PRETTY_FUNCTION__))
;
5086
5087 EVT OutVT = N->getValueType(0);
5088 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
5089 assert(NOutVT.isVector() && "Type must be promoted to a vector type")(static_cast <bool> (NOutVT.isVector() && "Type must be promoted to a vector type"
) ? void (0) : __assert_fail ("NOutVT.isVector() && \"Type must be promoted to a vector type\""
, "llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp", 5089
, __extension__ __PRETTY_FUNCTION__))
;
5090 EVT NOutElemVT = NOutVT.getVectorElementType();
5091
5092 SDValue Op = DAG.getNode(ISD::ANY_EXTEND, dl, NOutElemVT, SplatVal);
5093
5094 return DAG.getNode(ISD::SPLAT_VECTOR, dl, NOutVT, Op);
5095}
5096
5097SDValue DAGTypeLegalizer::PromoteIntRes_STEP_VECTOR(SDNode *N) {
5098 SDLoc dl(N);
5099 EVT OutVT = N->getValueType(0);
5100 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
5101 assert(NOutVT.isVector() && "Type must be promoted to a vector type")(static_cast <bool> (NOutVT.isVector() && "Type must be promoted to a vector type"
) ? void (0) : __assert_fail ("NOutVT.isVector() && \"Type must be promoted to a vector type\""
, "llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp", 5101
, __extension__ __PRETTY_FUNCTION__))
;
5102 APInt StepVal = cast<ConstantSDNode>(N->getOperand(0))->getAPIntValue();
5103 return DAG.getStepVector(dl, NOutVT,
5104 StepVal.sext(NOutVT.getScalarSizeInBits()));
5105}
5106
5107SDValue DAGTypeLegalizer::PromoteIntRes_CONCAT_VECTORS(SDNode *N) {
5108 SDLoc dl(N);
5109
5110 EVT OutVT = N->getValueType(0);
5111 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
5112 assert(NOutVT.isVector() && "This type must be promoted to a vector type")(static_cast <bool> (NOutVT.isVector() && "This type must be promoted to a vector type"
) ? void (0) : __assert_fail ("NOutVT.isVector() && \"This type must be promoted to a vector type\""
, "llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp", 5112
, __extension__ __PRETTY_FUNCTION__))
;
5113
5114 unsigned NumOperands = N->getNumOperands();
5115 unsigned NumOutElem = NOutVT.getVectorMinNumElements();
5116 EVT OutElemTy = NOutVT.getVectorElementType();
5117 if (OutVT.isScalableVector()) {
5118 // Find the largest promoted element type for each of the operands.
5119 SDUse *MaxSizedValue = std::max_element(
5120 N->op_begin(), N->op_end(), [](const SDValue &A, const SDValue &B) {
5121 EVT AVT = A.getValueType().getVectorElementType();
5122 EVT BVT = B.getValueType().getVectorElementType();
5123 return AVT.getScalarSizeInBits() < BVT.getScalarSizeInBits();
5124 });
5125 EVT MaxElementVT = MaxSizedValue->getValueType().getVectorElementType();
5126
5127 // Then promote all vectors to the largest element type.
5128 SmallVector<SDValue, 8> Ops;
5129 for (unsigned I = 0; I < NumOperands; ++I) {
5130 SDValue Op = N->getOperand(I);
5131 EVT OpVT = Op.getValueType();
5132 if (getTypeAction(OpVT) == TargetLowering::TypePromoteInteger)
5133 Op = GetPromotedInteger(Op);
5134 else
5135 assert(getTypeAction(OpVT) == TargetLowering::TypeLegal &&(static_cast <bool> (getTypeAction(OpVT) == TargetLowering
::TypeLegal && "Unhandled legalization type") ? void (
0) : __assert_fail ("getTypeAction(OpVT) == TargetLowering::TypeLegal && \"Unhandled legalization type\""
, "llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp", 5136
, __extension__ __PRETTY_FUNCTION__))
5136 "Unhandled legalization type")(static_cast <bool> (getTypeAction(OpVT) == TargetLowering
::TypeLegal && "Unhandled legalization type") ? void (
0) : __assert_fail ("getTypeAction(OpVT) == TargetLowering::TypeLegal && \"Unhandled legalization type\""
, "llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp", 5136
, __extension__ __PRETTY_FUNCTION__))
;
5137
5138 if (OpVT.getVectorElementType().getScalarSizeInBits() <
5139 MaxElementVT.getScalarSizeInBits())
5140 Op = DAG.getAnyExtOrTrunc(Op, dl,
5141 OpVT.changeVectorElementType(MaxElementVT));
5142 Ops.push_back(Op);
5143 }
5144
5145 // Do the CONCAT on the promoted type and finally truncate to (the promoted)
5146 // NOutVT.
5147 return DAG.getAnyExtOrTrunc(
5148 DAG.getNode(ISD::CONCAT_VECTORS, dl,
5149 OutVT.changeVectorElementType(MaxElementVT), Ops),
5150 dl, NOutVT);
5151 }
5152
5153 unsigned NumElem = N->getOperand(0).getValueType().getVectorNumElements();
5154 assert(NumElem * NumOperands == NumOutElem &&(static_cast <bool> (NumElem * NumOperands == NumOutElem
&& "Unexpected number of elements") ? void (0) : __assert_fail
("NumElem * NumOperands == NumOutElem && \"Unexpected number of elements\""
, "llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp", 5155
, __extension__ __PRETTY_FUNCTION__))
5155 "Unexpected number of elements")(static_cast <bool> (NumElem * NumOperands == NumOutElem
&& "Unexpected number of elements") ? void (0) : __assert_fail
("NumElem * NumOperands == NumOutElem && \"Unexpected number of elements\""
, "llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp", 5155
, __extension__ __PRETTY_FUNCTION__))
;
5156
5157 // Take the elements from the first vector.
5158 SmallVector<SDValue, 8> Ops(NumOutElem);
5159 for (unsigned i = 0; i < NumOperands; ++i) {
5160 SDValue Op = N->getOperand(i);
5161 if (getTypeAction(Op.getValueType()) == TargetLowering::TypePromoteInteger)
5162 Op = GetPromotedInteger(Op);
5163 EVT SclrTy = Op.getValueType().getVectorElementType();
5164 assert(NumElem == Op.getValueType().getVectorNumElements() &&(static_cast <bool> (NumElem == Op.getValueType().getVectorNumElements
() && "Unexpected number of elements") ? void (0) : __assert_fail
("NumElem == Op.getValueType().getVectorNumElements() && \"Unexpected number of elements\""
, "llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp", 5165
, __extension__ __PRETTY_FUNCTION__))
5165 "Unexpected number of elements")(static_cast <bool> (NumElem == Op.getValueType().getVectorNumElements
() && "Unexpected number of elements") ? void (0) : __assert_fail
("NumElem == Op.getValueType().getVectorNumElements() && \"Unexpected number of elements\""
, "llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp", 5165
, __extension__ __PRETTY_FUNCTION__))
;
5166
5167 for (unsigned j = 0; j < NumElem; ++j) {
5168 SDValue Ext = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SclrTy, Op,
5169 DAG.getVectorIdxConstant(j, dl));
5170 Ops[i * NumElem + j] = DAG.getAnyExtOrTrunc(Ext, dl, OutElemTy);
5171 }
5172 }
5173
5174 return DAG.getBuildVector(NOutVT, dl, Ops);
5175}
5176
5177SDValue DAGTypeLegalizer::PromoteIntRes_EXTEND_VECTOR_INREG(SDNode *N) {
5178 EVT VT = N->getValueType(0);
5179 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
5180 assert(NVT.isVector() && "This type must be promoted to a vector type")(static_cast <bool> (NVT.isVector() && "This type must be promoted to a vector type"
) ? void (0) : __assert_fail ("NVT.isVector() && \"This type must be promoted to a vector type\""
, "llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp", 5180
, __extension__ __PRETTY_FUNCTION__))
;
5181
5182 SDLoc dl(N);
5183
5184 // For operands whose TypeAction is to promote, extend the promoted node
5185 // appropriately (ZERO_EXTEND or SIGN_EXTEND) from the original pre-promotion
5186 // type, and then construct a new *_EXTEND_VECTOR_INREG node to the promote-to
5187 // type..
5188 if (getTypeAction(N->getOperand(0).getValueType())
5189 == TargetLowering::TypePromoteInteger) {
5190 SDValue Promoted;
5191
5192 switch(N->getOpcode()) {
5193 case ISD::SIGN_EXTEND_VECTOR_INREG:
5194 Promoted = SExtPromotedInteger(N->getOperand(0));
5195 break;
5196 case ISD::ZERO_EXTEND_VECTOR_INREG:
5197 Promoted = ZExtPromotedInteger(N->getOperand(0));
5198 break;
5199 case ISD::ANY_EXTEND_VECTOR_INREG:
5200 Promoted = GetPromotedInteger(N->getOperand(0));
5201 break;
5202 default:
5203 llvm_unreachable("Node has unexpected Opcode")::llvm::llvm_unreachable_internal("Node has unexpected Opcode"
, "llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp", 5203
)
;
5204 }
5205 return DAG.getNode(N->getOpcode(), dl, NVT, Promoted);
5206 }
5207
5208 // Directly extend to the appropriate transform-to type.
5209 return DAG.getNode(N->getOpcode(), dl, NVT, N->getOperand(0));
5210}
5211
5212SDValue DAGTypeLegalizer::PromoteIntRes_INSERT_VECTOR_ELT(SDNode *N) {
5213 EVT OutVT = N->getValueType(0);
5214 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
5215 assert(NOutVT.isVector() && "This type must be promoted to a vector type")(static_cast <bool> (NOutVT.isVector() && "This type must be promoted to a vector type"
) ? void (0) : __assert_fail ("NOutVT.isVector() && \"This type must be promoted to a vector type\""
, "llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp", 5215
, __extension__ __PRETTY_FUNCTION__))
;
5216
5217 EVT NOutVTElem = NOutVT.getVectorElementType();
5218
5219 SDLoc dl(N);
5220 SDValue V0 = GetPromotedInteger(N->getOperand(0));
5221
5222 SDValue ConvElem = DAG.getNode(ISD::ANY_EXTEND, dl,
5223 NOutVTElem, N->getOperand(1));
5224 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NOutVT,
5225 V0, ConvElem, N->getOperand(2));
5226}
5227
5228SDValue DAGTypeLegalizer::PromoteIntRes_VECREDUCE(SDNode *N) {
5229 // The VECREDUCE result size may be larger than the element size, so
5230 // we can simply change the result type.
5231 SDLoc dl(N);
5232 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
5233 return DAG.getNode(N->getOpcode(), dl, NVT, N->ops());
5234}
5235
5236SDValue DAGTypeLegalizer::PromoteIntRes_VP_REDUCE(SDNode *N) {
5237 // The VP_REDUCE result size may be larger than the element size, so we can
5238 // simply change the result type. However the start value and result must be
5239 // the same.
5240 SDLoc DL(N);
5241 SDValue Start = PromoteIntOpVectorReduction(N, N->getOperand(0));
5242 return DAG.getNode(N->getOpcode(), DL, Start.getValueType(), Start,
5243 N->getOperand(1), N->getOperand(2), N->getOperand(3));
5244}
5245
5246SDValue DAGTypeLegalizer::PromoteIntOp_EXTRACT_VECTOR_ELT(SDNode *N) {
5247 SDLoc dl(N);
5248 SDValue V0 = GetPromotedInteger(N->getOperand(0));
5249 SDValue V1 = DAG.getZExtOrTrunc(N->getOperand(1), dl,
5250 TLI.getVectorIdxTy(DAG.getDataLayout()));
5251 SDValue Ext = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
5252 V0->getValueType(0).getScalarType(), V0, V1);
5253
5254 // EXTRACT_VECTOR_ELT can return types which are wider than the incoming
5255 // element types. If this is the case then we need to expand the outgoing
5256 // value and not truncate it.
5257 return DAG.getAnyExtOrTrunc(Ext, dl, N->getValueType(0));
5258}
5259
5260SDValue DAGTypeLegalizer::PromoteIntOp_INSERT_SUBVECTOR(SDNode *N) {
5261 SDLoc dl(N);
5262 // The result type is equal to the first input operand's type, so the
5263 // type that needs promoting must be the second source vector.
5264 SDValue V0 = N->getOperand(0);
5265 SDValue V1 = GetPromotedInteger(N->getOperand(1));
5266 SDValue Idx = N->getOperand(2);
5267 EVT PromVT = EVT::getVectorVT(*DAG.getContext(),
5268 V1.getValueType().getVectorElementType(),
5269 V0.getValueType().getVectorElementCount());
5270 V0 = DAG.getAnyExtOrTrunc(V0, dl, PromVT);
5271 SDValue Ext = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, PromVT, V0, V1, Idx);
5272 return DAG.getAnyExtOrTrunc(Ext, dl, N->getValueType(0));
5273}
5274
5275SDValue DAGTypeLegalizer::PromoteIntOp_EXTRACT_SUBVECTOR(SDNode *N) {
5276 SDLoc dl(N);
5277 SDValue V0 = GetPromotedInteger(N->getOperand(0));
5278 MVT InVT = V0.getValueType().getSimpleVT();
5279 MVT OutVT = MVT::getVectorVT(InVT.getVectorElementType(),
5280 N->getValueType(0).getVectorNumElements());
5281 SDValue Ext = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, OutVT, V0, N->getOperand(1));
5282 return DAG.getNode(ISD::TRUNCATE, dl, N->getValueType(0), Ext);
5283}
5284
5285SDValue DAGTypeLegalizer::PromoteIntOp_CONCAT_VECTORS(SDNode *N) {
5286 SDLoc dl(N);
5287
5288 EVT ResVT = N->getValueType(0);
5289 unsigned NumElems = N->getNumOperands();
5290
5291 if (ResVT.isScalableVector()) {
5292 SDValue ResVec = DAG.getUNDEF(ResVT);
5293
5294 for (unsigned OpIdx = 0; OpIdx < NumElems; ++OpIdx) {
5295 SDValue Op = N->getOperand(OpIdx);
5296 unsigned OpNumElts = Op.getValueType().getVectorMinNumElements();
5297 ResVec = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, ResVec, Op,
5298 DAG.getIntPtrConstant(OpIdx * OpNumElts, dl));
5299 }
5300
5301 return ResVec;
5302 }
5303
5304 EVT RetSclrTy = N->getValueType(0).getVectorElementType();
5305
5306 SmallVector<SDValue, 8> NewOps;
5307 NewOps.reserve(NumElems);
5308
5309 // For each incoming vector
5310 for (unsigned VecIdx = 0; VecIdx != NumElems; ++VecIdx) {
5311 SDValue Incoming = GetPromotedInteger(N->getOperand(VecIdx));
5312 EVT SclrTy = Incoming->getValueType(0).getVectorElementType();
5313 unsigned NumElem = Incoming->getValueType(0).getVectorNumElements();
5314
5315 for (unsigned i=0; i<NumElem; ++i) {
5316 // Extract element from incoming vector
5317 SDValue Ex = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SclrTy, Incoming,
5318 DAG.getVectorIdxConstant(i, dl));
5319 SDValue Tr = DAG.getNode(ISD::TRUNCATE, dl, RetSclrTy, Ex);
5320 NewOps.push_back(Tr);
5321 }
5322 }
5323
5324 return DAG.getBuildVector(N->getValueType(0), dl, NewOps);
5325}

/build/llvm-toolchain-snapshot-14~++20220116100644+5f782d25a742/llvm/include/llvm/CodeGen/SelectionDAGNodes.h

1//===- llvm/CodeGen/SelectionDAGNodes.h - SelectionDAG Nodes ----*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file declares the SDNode class and derived classes, which are used to
10// represent the nodes and operations present in a SelectionDAG. These nodes
11// and operations are machine code level operations, with some similarities to
12// the GCC RTL representation.
13//
14// Clients should include the SelectionDAG.h file instead of this file directly.
15//
16//===----------------------------------------------------------------------===//
17
18#ifndef LLVM_CODEGEN_SELECTIONDAGNODES_H
19#define LLVM_CODEGEN_SELECTIONDAGNODES_H
20
21#include "llvm/ADT/APFloat.h"
22#include "llvm/ADT/ArrayRef.h"
23#include "llvm/ADT/BitVector.h"
24#include "llvm/ADT/FoldingSet.h"
25#include "llvm/ADT/GraphTraits.h"
26#include "llvm/ADT/SmallPtrSet.h"
27#include "llvm/ADT/SmallVector.h"
28#include "llvm/ADT/ilist_node.h"
29#include "llvm/ADT/iterator.h"
30#include "llvm/ADT/iterator_range.h"
31#include "llvm/CodeGen/ISDOpcodes.h"
32#include "llvm/CodeGen/MachineMemOperand.h"
33#include "llvm/CodeGen/Register.h"
34#include "llvm/CodeGen/ValueTypes.h"
35#include "llvm/IR/Constants.h"
36#include "llvm/IR/DebugLoc.h"
37#include "llvm/IR/Instruction.h"
38#include "llvm/IR/Instructions.h"
39#include "llvm/IR/Metadata.h"
40#include "llvm/IR/Operator.h"
41#include "llvm/Support/AlignOf.h"
42#include "llvm/Support/AtomicOrdering.h"
43#include "llvm/Support/Casting.h"
44#include "llvm/Support/ErrorHandling.h"
45#include "llvm/Support/MachineValueType.h"
46#include "llvm/Support/TypeSize.h"
47#include <algorithm>
48#include <cassert>
49#include <climits>
50#include <cstddef>
51#include <cstdint>
52#include <cstring>
53#include <iterator>
54#include <string>
55#include <tuple>
56
57namespace llvm {
58
59class APInt;
60class Constant;
61class GlobalValue;
62class MachineBasicBlock;
63class MachineConstantPoolValue;
64class MCSymbol;
65class raw_ostream;
66class SDNode;
67class SelectionDAG;
68class Type;
69class Value;
70
71void checkForCycles(const SDNode *N, const SelectionDAG *DAG = nullptr,
72 bool force = false);
73
74/// This represents a list of ValueType's that has been intern'd by
75/// a SelectionDAG. Instances of this simple value class are returned by
76/// SelectionDAG::getVTList(...).
77///
78struct SDVTList {
79 const EVT *VTs;
80 unsigned int NumVTs;
81};
82
83namespace ISD {
84
85 /// Node predicates
86
87/// If N is a BUILD_VECTOR or SPLAT_VECTOR node whose elements are all the
88/// same constant or undefined, return true and return the constant value in
89/// \p SplatValue.
90bool isConstantSplatVector(const SDNode *N, APInt &SplatValue);
91
92/// Return true if the specified node is a BUILD_VECTOR or SPLAT_VECTOR where
93/// all of the elements are ~0 or undef. If \p BuildVectorOnly is set to
94/// true, it only checks BUILD_VECTOR.
95bool isConstantSplatVectorAllOnes(const SDNode *N,
96 bool BuildVectorOnly = false);
97
98/// Return true if the specified node is a BUILD_VECTOR or SPLAT_VECTOR where
99/// all of the elements are 0 or undef. If \p BuildVectorOnly is set to true, it
100/// only checks BUILD_VECTOR.
101bool isConstantSplatVectorAllZeros(const SDNode *N,
102 bool BuildVectorOnly = false);
103
104/// Return true if the specified node is a BUILD_VECTOR where all of the
105/// elements are ~0 or undef.
106bool isBuildVectorAllOnes(const SDNode *N);
107
108/// Return true if the specified node is a BUILD_VECTOR where all of the
109/// elements are 0 or undef.
110bool isBuildVectorAllZeros(const SDNode *N);
111
112/// Return true if the specified node is a BUILD_VECTOR node of all
113/// ConstantSDNode or undef.
114bool isBuildVectorOfConstantSDNodes(const SDNode *N);
115
116/// Return true if the specified node is a BUILD_VECTOR node of all
117/// ConstantFPSDNode or undef.
118bool isBuildVectorOfConstantFPSDNodes(const SDNode *N);
119
120/// Return true if the node has at least one operand and all operands of the
121/// specified node are ISD::UNDEF.
122bool allOperandsUndef(const SDNode *N);
123
124} // end namespace ISD
125
126//===----------------------------------------------------------------------===//
127/// Unlike LLVM values, Selection DAG nodes may return multiple
128/// values as the result of a computation. Many nodes return multiple values,
129/// from loads (which define a token and a return value) to ADDC (which returns
130/// a result and a carry value), to calls (which may return an arbitrary number
131/// of values).
132///
133/// As such, each use of a SelectionDAG computation must indicate the node that
134/// computes it as well as which return value to use from that node. This pair
135/// of information is represented with the SDValue value type.
136///
137class SDValue {
138 friend struct DenseMapInfo<SDValue>;
139
140 SDNode *Node = nullptr; // The node defining the value we are using.
141 unsigned ResNo = 0; // Which return value of the node we are using.
142
143public:
144 SDValue() = default;
145 SDValue(SDNode *node, unsigned resno);
146
147 /// get the index which selects a specific result in the SDNode
148 unsigned getResNo() const { return ResNo; }
149
150 /// get the SDNode which holds the desired result
151 SDNode *getNode() const { return Node; }
152
153 /// set the SDNode
154 void setNode(SDNode *N) { Node = N; }
155
156 inline SDNode *operator->() const { return Node; }
157
158 bool operator==(const SDValue &O) const {
159 return Node == O.Node && ResNo == O.ResNo;
160 }
161 bool operator!=(const SDValue &O) const {
162 return !operator==(O);
163 }
164 bool operator<(const SDValue &O) const {
165 return std::tie(Node, ResNo) < std::tie(O.Node, O.ResNo);
166 }
167 explicit operator bool() const {
168 return Node != nullptr;
169 }
170
171 SDValue getValue(unsigned R) const {
172 return SDValue(Node, R);
173 }
174
175 /// Return true if this node is an operand of N.
176 bool isOperandOf(const SDNode *N) const;
177
178 /// Return the ValueType of the referenced return value.
179 inline EVT getValueType() const;
180
181 /// Return the simple ValueType of the referenced return value.
182 MVT getSimpleValueType() const {
183 return getValueType().getSimpleVT();
184 }
185
186 /// Returns the size of the value in bits.
187 ///
188 /// If the value type is a scalable vector type, the scalable property will
189 /// be set and the runtime size will be a positive integer multiple of the
190 /// base size.
191 TypeSize getValueSizeInBits() const {
192 return getValueType().getSizeInBits();
193 }
194
195 uint64_t getScalarValueSizeInBits() const {
196 return getValueType().getScalarType().getFixedSizeInBits();
197 }
198
199 // Forwarding methods - These forward to the corresponding methods in SDNode.
200 inline unsigned getOpcode() const;
201 inline unsigned getNumOperands() const;
202 inline const SDValue &getOperand(unsigned i) const;
203 inline uint64_t getConstantOperandVal(unsigned i) const;
204 inline const APInt &getConstantOperandAPInt(unsigned i) const;
205 inline bool isTargetMemoryOpcode() const;
206 inline bool isTargetOpcode() const;
207 inline bool isMachineOpcode() const;
208 inline bool isUndef() const;
209 inline unsigned getMachineOpcode() const;
210 inline const DebugLoc &getDebugLoc() const;
211 inline void dump() const;
212 inline void dump(const SelectionDAG *G) const;
213 inline void dumpr() const;
214 inline void dumpr(const SelectionDAG *G) const;
215
216 /// Return true if this operand (which must be a chain) reaches the
217 /// specified operand without crossing any side-effecting instructions.
218 /// In practice, this looks through token factors and non-volatile loads.
219 /// In order to remain efficient, this only
220 /// looks a couple of nodes in, it does not do an exhaustive search.
221 bool reachesChainWithoutSideEffects(SDValue Dest,
222 unsigned Depth = 2) const;
223
224 /// Return true if there are no nodes using value ResNo of Node.
225 inline bool use_empty() const;
226
227 /// Return true if there is exactly one node using value ResNo of Node.
228 inline bool hasOneUse() const;
229};
230
231template<> struct DenseMapInfo<SDValue> {
232 static inline SDValue getEmptyKey() {
233 SDValue V;
234 V.ResNo = -1U;
235 return V;
236 }
237
238 static inline SDValue getTombstoneKey() {
239 SDValue V;
240 V.ResNo = -2U;
241 return V;
242 }
243
244 static unsigned getHashValue(const SDValue &Val) {
245 return ((unsigned)((uintptr_t)Val.getNode() >> 4) ^
246 (unsigned)((uintptr_t)Val.getNode() >> 9)) + Val.getResNo();
247 }
248
249 static bool isEqual(const SDValue &LHS, const SDValue &RHS) {
250 return LHS == RHS;
251 }
252};
253
254/// Allow casting operators to work directly on
255/// SDValues as if they were SDNode*'s.
256template<> struct simplify_type<SDValue> {
257 using SimpleType = SDNode *;
258
259 static SimpleType getSimplifiedValue(SDValue &Val) {
260 return Val.getNode();
261 }
262};
263template<> struct simplify_type<const SDValue> {
264 using SimpleType = /*const*/ SDNode *;
265
266 static SimpleType getSimplifiedValue(const SDValue &Val) {
267 return Val.getNode();
268 }
269};
270
271/// Represents a use of a SDNode. This class holds an SDValue,
272/// which records the SDNode being used and the result number, a
273/// pointer to the SDNode using the value, and Next and Prev pointers,
274/// which link together all the uses of an SDNode.
275///
276class SDUse {
277 /// Val - The value being used.
278 SDValue Val;
279 /// User - The user of this value.
280 SDNode *User = nullptr;
281 /// Prev, Next - Pointers to the uses list of the SDNode referred by
282 /// this operand.
283 SDUse **Prev = nullptr;
284 SDUse *Next = nullptr;
285
286public:
287 SDUse() = default;
288 SDUse(const SDUse &U) = delete;
289 SDUse &operator=(const SDUse &) = delete;
290
291 /// Normally SDUse will just implicitly convert to an SDValue that it holds.
292 operator const SDValue&() const { return Val; }
293
294 /// If implicit conversion to SDValue doesn't work, the get() method returns
295 /// the SDValue.
296 const SDValue &get() const { return Val; }
297
298 /// This returns the SDNode that contains this Use.
299 SDNode *getUser() { return User; }
300
301 /// Get the next SDUse in the use list.
302 SDUse *getNext() const { return Next; }
303
304 /// Convenience function for get().getNode().
305 SDNode *getNode() const { return Val.getNode(); }
306 /// Convenience function for get().getResNo().
307 unsigned getResNo() const { return Val.getResNo(); }
308 /// Convenience function for get().getValueType().
309 EVT getValueType() const { return Val.getValueType(); }
310
311 /// Convenience function for get().operator==
312 bool operator==(const SDValue &V) const {
313 return Val == V;
314 }
315
316 /// Convenience function for get().operator!=
317 bool operator!=(const SDValue &V) const {
318 return Val != V;
319 }
320
321 /// Convenience function for get().operator<
322 bool operator<(const SDValue &V) const {
323 return Val < V;
324 }
325
326private:
327 friend class SelectionDAG;
328 friend class SDNode;
329 // TODO: unfriend HandleSDNode once we fix its operand handling.
330 friend class HandleSDNode;
331
332 void setUser(SDNode *p) { User = p; }
333
334 /// Remove this use from its existing use list, assign it the
335 /// given value, and add it to the new value's node's use list.
336 inline void set(const SDValue &V);
337 /// Like set, but only supports initializing a newly-allocated
338 /// SDUse with a non-null value.
339 inline void setInitial(const SDValue &V);
340 /// Like set, but only sets the Node portion of the value,
341 /// leaving the ResNo portion unmodified.
342 inline void setNode(SDNode *N);
343
344 void addToList(SDUse **List) {
345 Next = *List;
346 if (Next) Next->Prev = &Next;
347 Prev = List;
348 *List = this;
349 }
350
351 void removeFromList() {
352 *Prev = Next;
353 if (Next) Next->Prev = Prev;
354 }
355};
356
357/// simplify_type specializations - Allow casting operators to work directly on
358/// SDValues as if they were SDNode*'s.
359template<> struct simplify_type<SDUse> {
360 using SimpleType = SDNode *;
361
362 static SimpleType getSimplifiedValue(SDUse &Val) {
363 return Val.getNode();
364 }
365};
366
367/// These are IR-level optimization flags that may be propagated to SDNodes.
368/// TODO: This data structure should be shared by the IR optimizer and the
369/// the backend.
370struct SDNodeFlags {
371private:
372 bool NoUnsignedWrap : 1;
373 bool NoSignedWrap : 1;
374 bool Exact : 1;
375 bool NoNaNs : 1;
376 bool NoInfs : 1;
377 bool NoSignedZeros : 1;
378 bool AllowReciprocal : 1;
379 bool AllowContract : 1;
380 bool ApproximateFuncs : 1;
381 bool AllowReassociation : 1;
382
383 // We assume instructions do not raise floating-point exceptions by default,
384 // and only those marked explicitly may do so. We could choose to represent
385 // this via a positive "FPExcept" flags like on the MI level, but having a
386 // negative "NoFPExcept" flag here (that defaults to true) makes the flag
387 // intersection logic more straightforward.
388 bool NoFPExcept : 1;
389
390public:
391 /// Default constructor turns off all optimization flags.
392 SDNodeFlags()
393 : NoUnsignedWrap(false), NoSignedWrap(false), Exact(false), NoNaNs(false),
394 NoInfs(false), NoSignedZeros(false), AllowReciprocal(false),
395 AllowContract(false), ApproximateFuncs(false),
396 AllowReassociation(false), NoFPExcept(false) {}
397
398 /// Propagate the fast-math-flags from an IR FPMathOperator.
399 void copyFMF(const FPMathOperator &FPMO) {
400 setNoNaNs(FPMO.hasNoNaNs());
401 setNoInfs(FPMO.hasNoInfs());
402 setNoSignedZeros(FPMO.hasNoSignedZeros());
403 setAllowReciprocal(FPMO.hasAllowReciprocal());
404 setAllowContract(FPMO.hasAllowContract());
405 setApproximateFuncs(FPMO.hasApproxFunc());
406 setAllowReassociation(FPMO.hasAllowReassoc());
407 }
408
409 // These are mutators for each flag.
410 void setNoUnsignedWrap(bool b) { NoUnsignedWrap = b; }
411 void setNoSignedWrap(bool b) { NoSignedWrap = b; }
412 void setExact(bool b) { Exact = b; }
413 void setNoNaNs(bool b) { NoNaNs = b; }
414 void setNoInfs(bool b) { NoInfs = b; }
415 void setNoSignedZeros(bool b) { NoSignedZeros = b; }
416 void setAllowReciprocal(bool b) { AllowReciprocal = b; }
417 void setAllowContract(bool b) { AllowContract = b; }
418 void setApproximateFuncs(bool b) { ApproximateFuncs = b; }
419 void setAllowReassociation(bool b) { AllowReassociation = b; }
420 void setNoFPExcept(bool b) { NoFPExcept = b; }
421
422 // These are accessors for each flag.
423 bool hasNoUnsignedWrap() const { return NoUnsignedWrap; }
424 bool hasNoSignedWrap() const { return NoSignedWrap; }
425 bool hasExact() const { return Exact; }
426 bool hasNoNaNs() const { return NoNaNs; }
427 bool hasNoInfs() const { return NoInfs; }
428 bool hasNoSignedZeros() const { return NoSignedZeros; }
429 bool hasAllowReciprocal() const { return AllowReciprocal; }
430 bool hasAllowContract() const { return AllowContract; }
431 bool hasApproximateFuncs() const { return ApproximateFuncs; }
432 bool hasAllowReassociation() const { return AllowReassociation; }
433 bool hasNoFPExcept() const { return NoFPExcept; }
434
435 /// Clear any flags in this flag set that aren't also set in Flags. All
436 /// flags will be cleared if Flags are undefined.
437 void intersectWith(const SDNodeFlags Flags) {
438 NoUnsignedWrap &= Flags.NoUnsignedWrap;
439 NoSignedWrap &= Flags.NoSignedWrap;
440 Exact &= Flags.Exact;
441 NoNaNs &= Flags.NoNaNs;
442 NoInfs &= Flags.NoInfs;
443 NoSignedZeros &= Flags.NoSignedZeros;
444 AllowReciprocal &= Flags.AllowReciprocal;
445 AllowContract &= Flags.AllowContract;
446 ApproximateFuncs &= Flags.ApproximateFuncs;
447 AllowReassociation &= Flags.AllowReassociation;
448 NoFPExcept &= Flags.NoFPExcept;
449 }
450};
451
452/// Represents one node in the SelectionDAG.
453///
454class SDNode : public FoldingSetNode, public ilist_node<SDNode> {
455private:
456 /// The operation that this node performs.
457 int16_t NodeType;
458
459protected:
460 // We define a set of mini-helper classes to help us interpret the bits in our
461 // SubclassData. These are designed to fit within a uint16_t so they pack
462 // with NodeType.
463
464#if defined(_AIX) && (!defined(__GNUC__4) || defined(__clang__1))
465// Except for GCC; by default, AIX compilers store bit-fields in 4-byte words
466// and give the `pack` pragma push semantics.
467#define BEGIN_TWO_BYTE_PACK() _Pragma("pack(2)")pack(2)
468#define END_TWO_BYTE_PACK() _Pragma("pack(pop)")pack(pop)
469#else
470#define BEGIN_TWO_BYTE_PACK()
471#define END_TWO_BYTE_PACK()
472#endif
473
474BEGIN_TWO_BYTE_PACK()
475 class SDNodeBitfields {
476 friend class SDNode;
477 friend class MemIntrinsicSDNode;
478 friend class MemSDNode;
479 friend class SelectionDAG;
480
481 uint16_t HasDebugValue : 1;
482 uint16_t IsMemIntrinsic : 1;
483 uint16_t IsDivergent : 1;
484 };
485 enum { NumSDNodeBits = 3 };
486
487 class ConstantSDNodeBitfields {
488 friend class ConstantSDNode;
489
490 uint16_t : NumSDNodeBits;
491
492 uint16_t IsOpaque : 1;
493 };
494
495 class MemSDNodeBitfields {
496 friend class MemSDNode;
497 friend class MemIntrinsicSDNode;
498 friend class AtomicSDNode;
499
500 uint16_t : NumSDNodeBits;
501
502 uint16_t IsVolatile : 1;
503 uint16_t IsNonTemporal : 1;
504 uint16_t IsDereferenceable : 1;
505 uint16_t IsInvariant : 1;
506 };
507 enum { NumMemSDNodeBits = NumSDNodeBits + 4 };
508
509 class LSBaseSDNodeBitfields {
510 friend class LSBaseSDNode;
511 friend class VPLoadStoreSDNode;
512 friend class MaskedLoadStoreSDNode;
513 friend class MaskedGatherScatterSDNode;
514 friend class VPGatherScatterSDNode;
515
516 uint16_t : NumMemSDNodeBits;
517
518 // This storage is shared between disparate class hierarchies to hold an
519 // enumeration specific to the class hierarchy in use.
520 // LSBaseSDNode => enum ISD::MemIndexedMode
521 // VPLoadStoreBaseSDNode => enum ISD::MemIndexedMode
522 // MaskedLoadStoreBaseSDNode => enum ISD::MemIndexedMode
523 // VPGatherScatterSDNode => enum ISD::MemIndexType
524 // MaskedGatherScatterSDNode => enum ISD::MemIndexType
525 uint16_t AddressingMode : 3;
526 };