Bug Summary

File:llvm/include/llvm/CodeGen/SelectionDAGNodes.h
Warning:line 1166, column 10
Called C++ object pointer is null

Annotated Source Code

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clang -cc1 -cc1 -triple x86_64-pc-linux-gnu -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name AMDGPUISelLowering.cpp -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=cplusplus -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -analyzer-config-compatibility-mode=true -mrelocation-model pic -pic-level 2 -mframe-pointer=none -fmath-errno -fno-rounding-math -mconstructor-aliases -munwind-tables -target-cpu x86-64 -tune-cpu generic -debugger-tuning=gdb -ffunction-sections -fdata-sections -fcoverage-compilation-dir=/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/build-llvm -resource-dir /usr/lib/llvm-14/lib/clang/14.0.0 -D _DEBUG -D _GNU_SOURCE -D __STDC_CONSTANT_MACROS -D __STDC_FORMAT_MACROS -D __STDC_LIMIT_MACROS -I lib/Target/AMDGPU -I /build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/AMDGPU -I include -I /build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/include -D NDEBUG -U NDEBUG -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/10/../../../../include/c++/10 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/10/../../../../include/x86_64-linux-gnu/c++/10 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/10/../../../../include/c++/10/backward -internal-isystem /usr/lib/llvm-14/lib/clang/14.0.0/include -internal-isystem /usr/local/include -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/10/../../../../x86_64-linux-gnu/include -internal-externc-isystem /usr/include/x86_64-linux-gnu -internal-externc-isystem /include -internal-externc-isystem /usr/include -O2 -Wno-unused-command-line-argument -Wno-unknown-warning-option -Wno-unused-parameter -Wwrite-strings -Wno-missing-field-initializers -Wno-long-long -Wno-maybe-uninitialized -Wno-class-memaccess -Wno-redundant-move -Wno-pessimizing-move -Wno-noexcept-type -Wno-comment -std=c++14 -fdeprecated-macro -fdebug-compilation-dir=/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/build-llvm -ferror-limit 19 -fvisibility hidden -fvisibility-inlines-hidden -fgnuc-version=4.2.1 -fcolor-diagnostics -vectorize-loops -vectorize-slp -analyzer-output=html -analyzer-config stable-report-filename=true -faddrsig -D__GCC_HAVE_DWARF2_CFI_ASM=1 -o /tmp/scan-build-2021-09-26-234817-15343-1 -x c++ /build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp

/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp

1//===-- AMDGPUISelLowering.cpp - AMDGPU Common DAG lowering functions -----===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9/// \file
10/// This is the parent TargetLowering class for hardware code gen
11/// targets.
12//
13//===----------------------------------------------------------------------===//
14
15#include "AMDGPUISelLowering.h"
16#include "AMDGPU.h"
17#include "AMDGPUInstrInfo.h"
18#include "AMDGPUMachineFunction.h"
19#include "GCNSubtarget.h"
20#include "SIMachineFunctionInfo.h"
21#include "llvm/CodeGen/Analysis.h"
22#include "llvm/IR/DiagnosticInfo.h"
23#include "llvm/IR/IntrinsicsAMDGPU.h"
24#include "llvm/Support/CommandLine.h"
25#include "llvm/Support/KnownBits.h"
26#include "llvm/Target/TargetMachine.h"
27
28using namespace llvm;
29
30#include "AMDGPUGenCallingConv.inc"
31
32static cl::opt<bool> AMDGPUBypassSlowDiv(
33 "amdgpu-bypass-slow-div",
34 cl::desc("Skip 64-bit divide for dynamic 32-bit values"),
35 cl::init(true));
36
37// Find a larger type to do a load / store of a vector with.
38EVT AMDGPUTargetLowering::getEquivalentMemType(LLVMContext &Ctx, EVT VT) {
39 unsigned StoreSize = VT.getStoreSizeInBits();
40 if (StoreSize <= 32)
41 return EVT::getIntegerVT(Ctx, StoreSize);
42
43 assert(StoreSize % 32 == 0 && "Store size not a multiple of 32")(static_cast <bool> (StoreSize % 32 == 0 && "Store size not a multiple of 32"
) ? void (0) : __assert_fail ("StoreSize % 32 == 0 && \"Store size not a multiple of 32\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp"
, 43, __extension__ __PRETTY_FUNCTION__))
;
44 return EVT::getVectorVT(Ctx, MVT::i32, StoreSize / 32);
45}
46
47unsigned AMDGPUTargetLowering::numBitsUnsigned(SDValue Op, SelectionDAG &DAG) {
48 EVT VT = Op.getValueType();
49 KnownBits Known = DAG.computeKnownBits(Op);
50 return VT.getSizeInBits() - Known.countMinLeadingZeros();
51}
52
53unsigned AMDGPUTargetLowering::numBitsSigned(SDValue Op, SelectionDAG &DAG) {
54 EVT VT = Op.getValueType();
55
56 // In order for this to be a signed 24-bit value, bit 23, must
57 // be a sign bit.
58 return VT.getSizeInBits() - DAG.ComputeNumSignBits(Op);
59}
60
61AMDGPUTargetLowering::AMDGPUTargetLowering(const TargetMachine &TM,
62 const AMDGPUSubtarget &STI)
63 : TargetLowering(TM), Subtarget(&STI) {
64 // Lower floating point store/load to integer store/load to reduce the number
65 // of patterns in tablegen.
66 setOperationAction(ISD::LOAD, MVT::f32, Promote);
67 AddPromotedToType(ISD::LOAD, MVT::f32, MVT::i32);
68
69 setOperationAction(ISD::LOAD, MVT::v2f32, Promote);
70 AddPromotedToType(ISD::LOAD, MVT::v2f32, MVT::v2i32);
71
72 setOperationAction(ISD::LOAD, MVT::v3f32, Promote);
73 AddPromotedToType(ISD::LOAD, MVT::v3f32, MVT::v3i32);
74
75 setOperationAction(ISD::LOAD, MVT::v4f32, Promote);
76 AddPromotedToType(ISD::LOAD, MVT::v4f32, MVT::v4i32);
77
78 setOperationAction(ISD::LOAD, MVT::v5f32, Promote);
79 AddPromotedToType(ISD::LOAD, MVT::v5f32, MVT::v5i32);
80
81 setOperationAction(ISD::LOAD, MVT::v6f32, Promote);
82 AddPromotedToType(ISD::LOAD, MVT::v6f32, MVT::v6i32);
83
84 setOperationAction(ISD::LOAD, MVT::v7f32, Promote);
85 AddPromotedToType(ISD::LOAD, MVT::v7f32, MVT::v7i32);
86
87 setOperationAction(ISD::LOAD, MVT::v8f32, Promote);
88 AddPromotedToType(ISD::LOAD, MVT::v8f32, MVT::v8i32);
89
90 setOperationAction(ISD::LOAD, MVT::v16f32, Promote);
91 AddPromotedToType(ISD::LOAD, MVT::v16f32, MVT::v16i32);
92
93 setOperationAction(ISD::LOAD, MVT::v32f32, Promote);
94 AddPromotedToType(ISD::LOAD, MVT::v32f32, MVT::v32i32);
95
96 setOperationAction(ISD::LOAD, MVT::i64, Promote);
97 AddPromotedToType(ISD::LOAD, MVT::i64, MVT::v2i32);
98
99 setOperationAction(ISD::LOAD, MVT::v2i64, Promote);
100 AddPromotedToType(ISD::LOAD, MVT::v2i64, MVT::v4i32);
101
102 setOperationAction(ISD::LOAD, MVT::f64, Promote);
103 AddPromotedToType(ISD::LOAD, MVT::f64, MVT::v2i32);
104
105 setOperationAction(ISD::LOAD, MVT::v2f64, Promote);
106 AddPromotedToType(ISD::LOAD, MVT::v2f64, MVT::v4i32);
107
108 setOperationAction(ISD::LOAD, MVT::v3i64, Promote);
109 AddPromotedToType(ISD::LOAD, MVT::v3i64, MVT::v6i32);
110
111 setOperationAction(ISD::LOAD, MVT::v4i64, Promote);
112 AddPromotedToType(ISD::LOAD, MVT::v4i64, MVT::v8i32);
113
114 setOperationAction(ISD::LOAD, MVT::v3f64, Promote);
115 AddPromotedToType(ISD::LOAD, MVT::v3f64, MVT::v6i32);
116
117 setOperationAction(ISD::LOAD, MVT::v4f64, Promote);
118 AddPromotedToType(ISD::LOAD, MVT::v4f64, MVT::v8i32);
119
120 setOperationAction(ISD::LOAD, MVT::v8i64, Promote);
121 AddPromotedToType(ISD::LOAD, MVT::v8i64, MVT::v16i32);
122
123 setOperationAction(ISD::LOAD, MVT::v8f64, Promote);
124 AddPromotedToType(ISD::LOAD, MVT::v8f64, MVT::v16i32);
125
126 setOperationAction(ISD::LOAD, MVT::v16i64, Promote);
127 AddPromotedToType(ISD::LOAD, MVT::v16i64, MVT::v32i32);
128
129 setOperationAction(ISD::LOAD, MVT::v16f64, Promote);
130 AddPromotedToType(ISD::LOAD, MVT::v16f64, MVT::v32i32);
131
132 // There are no 64-bit extloads. These should be done as a 32-bit extload and
133 // an extension to 64-bit.
134 for (MVT VT : MVT::integer_valuetypes()) {
135 setLoadExtAction(ISD::EXTLOAD, MVT::i64, VT, Expand);
136 setLoadExtAction(ISD::SEXTLOAD, MVT::i64, VT, Expand);
137 setLoadExtAction(ISD::ZEXTLOAD, MVT::i64, VT, Expand);
138 }
139
140 for (MVT VT : MVT::integer_valuetypes()) {
141 if (VT == MVT::i64)
142 continue;
143
144 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
145 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i8, Legal);
146 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i16, Legal);
147 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i32, Expand);
148
149 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote);
150 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i8, Legal);
151 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i16, Legal);
152 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i32, Expand);
153
154 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote);
155 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i8, Legal);
156 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i16, Legal);
157 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i32, Expand);
158 }
159
160 for (MVT VT : MVT::integer_fixedlen_vector_valuetypes()) {
161 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i8, Expand);
162 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i8, Expand);
163 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::v2i8, Expand);
164 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i8, Expand);
165 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i8, Expand);
166 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::v4i8, Expand);
167 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i16, Expand);
168 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i16, Expand);
169 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::v2i16, Expand);
170 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v3i16, Expand);
171 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v3i16, Expand);
172 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::v3i16, Expand);
173 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i16, Expand);
174 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i16, Expand);
175 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::v4i16, Expand);
176 }
177
178 setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Expand);
179 setLoadExtAction(ISD::EXTLOAD, MVT::v2f32, MVT::v2f16, Expand);
180 setLoadExtAction(ISD::EXTLOAD, MVT::v3f32, MVT::v3f16, Expand);
181 setLoadExtAction(ISD::EXTLOAD, MVT::v4f32, MVT::v4f16, Expand);
182 setLoadExtAction(ISD::EXTLOAD, MVT::v8f32, MVT::v8f16, Expand);
183 setLoadExtAction(ISD::EXTLOAD, MVT::v16f32, MVT::v16f16, Expand);
184 setLoadExtAction(ISD::EXTLOAD, MVT::v32f32, MVT::v32f16, Expand);
185
186 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f32, Expand);
187 setLoadExtAction(ISD::EXTLOAD, MVT::v2f64, MVT::v2f32, Expand);
188 setLoadExtAction(ISD::EXTLOAD, MVT::v3f64, MVT::v3f32, Expand);
189 setLoadExtAction(ISD::EXTLOAD, MVT::v4f64, MVT::v4f32, Expand);
190 setLoadExtAction(ISD::EXTLOAD, MVT::v8f64, MVT::v8f32, Expand);
191 setLoadExtAction(ISD::EXTLOAD, MVT::v16f64, MVT::v16f32, Expand);
192
193 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Expand);
194 setLoadExtAction(ISD::EXTLOAD, MVT::v2f64, MVT::v2f16, Expand);
195 setLoadExtAction(ISD::EXTLOAD, MVT::v3f64, MVT::v3f16, Expand);
196 setLoadExtAction(ISD::EXTLOAD, MVT::v4f64, MVT::v4f16, Expand);
197 setLoadExtAction(ISD::EXTLOAD, MVT::v8f64, MVT::v8f16, Expand);
198 setLoadExtAction(ISD::EXTLOAD, MVT::v16f64, MVT::v16f16, Expand);
199
200 setOperationAction(ISD::STORE, MVT::f32, Promote);
201 AddPromotedToType(ISD::STORE, MVT::f32, MVT::i32);
202
203 setOperationAction(ISD::STORE, MVT::v2f32, Promote);
204 AddPromotedToType(ISD::STORE, MVT::v2f32, MVT::v2i32);
205
206 setOperationAction(ISD::STORE, MVT::v3f32, Promote);
207 AddPromotedToType(ISD::STORE, MVT::v3f32, MVT::v3i32);
208
209 setOperationAction(ISD::STORE, MVT::v4f32, Promote);
210 AddPromotedToType(ISD::STORE, MVT::v4f32, MVT::v4i32);
211
212 setOperationAction(ISD::STORE, MVT::v5f32, Promote);
213 AddPromotedToType(ISD::STORE, MVT::v5f32, MVT::v5i32);
214
215 setOperationAction(ISD::STORE, MVT::v6f32, Promote);
216 AddPromotedToType(ISD::STORE, MVT::v6f32, MVT::v6i32);
217
218 setOperationAction(ISD::STORE, MVT::v7f32, Promote);
219 AddPromotedToType(ISD::STORE, MVT::v7f32, MVT::v7i32);
220
221 setOperationAction(ISD::STORE, MVT::v8f32, Promote);
222 AddPromotedToType(ISD::STORE, MVT::v8f32, MVT::v8i32);
223
224 setOperationAction(ISD::STORE, MVT::v16f32, Promote);
225 AddPromotedToType(ISD::STORE, MVT::v16f32, MVT::v16i32);
226
227 setOperationAction(ISD::STORE, MVT::v32f32, Promote);
228 AddPromotedToType(ISD::STORE, MVT::v32f32, MVT::v32i32);
229
230 setOperationAction(ISD::STORE, MVT::i64, Promote);
231 AddPromotedToType(ISD::STORE, MVT::i64, MVT::v2i32);
232
233 setOperationAction(ISD::STORE, MVT::v2i64, Promote);
234 AddPromotedToType(ISD::STORE, MVT::v2i64, MVT::v4i32);
235
236 setOperationAction(ISD::STORE, MVT::f64, Promote);
237 AddPromotedToType(ISD::STORE, MVT::f64, MVT::v2i32);
238
239 setOperationAction(ISD::STORE, MVT::v2f64, Promote);
240 AddPromotedToType(ISD::STORE, MVT::v2f64, MVT::v4i32);
241
242 setOperationAction(ISD::STORE, MVT::v3i64, Promote);
243 AddPromotedToType(ISD::STORE, MVT::v3i64, MVT::v6i32);
244
245 setOperationAction(ISD::STORE, MVT::v3f64, Promote);
246 AddPromotedToType(ISD::STORE, MVT::v3f64, MVT::v6i32);
247
248 setOperationAction(ISD::STORE, MVT::v4i64, Promote);
249 AddPromotedToType(ISD::STORE, MVT::v4i64, MVT::v8i32);
250
251 setOperationAction(ISD::STORE, MVT::v4f64, Promote);
252 AddPromotedToType(ISD::STORE, MVT::v4f64, MVT::v8i32);
253
254 setOperationAction(ISD::STORE, MVT::v8i64, Promote);
255 AddPromotedToType(ISD::STORE, MVT::v8i64, MVT::v16i32);
256
257 setOperationAction(ISD::STORE, MVT::v8f64, Promote);
258 AddPromotedToType(ISD::STORE, MVT::v8f64, MVT::v16i32);
259
260 setOperationAction(ISD::STORE, MVT::v16i64, Promote);
261 AddPromotedToType(ISD::STORE, MVT::v16i64, MVT::v32i32);
262
263 setOperationAction(ISD::STORE, MVT::v16f64, Promote);
264 AddPromotedToType(ISD::STORE, MVT::v16f64, MVT::v32i32);
265
266 setTruncStoreAction(MVT::i64, MVT::i1, Expand);
267 setTruncStoreAction(MVT::i64, MVT::i8, Expand);
268 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
269 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
270
271 setTruncStoreAction(MVT::v2i64, MVT::v2i1, Expand);
272 setTruncStoreAction(MVT::v2i64, MVT::v2i8, Expand);
273 setTruncStoreAction(MVT::v2i64, MVT::v2i16, Expand);
274 setTruncStoreAction(MVT::v2i64, MVT::v2i32, Expand);
275
276 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
277 setTruncStoreAction(MVT::v2f32, MVT::v2f16, Expand);
278 setTruncStoreAction(MVT::v3f32, MVT::v3f16, Expand);
279 setTruncStoreAction(MVT::v4f32, MVT::v4f16, Expand);
280 setTruncStoreAction(MVT::v8f32, MVT::v8f16, Expand);
281 setTruncStoreAction(MVT::v16f32, MVT::v16f16, Expand);
282 setTruncStoreAction(MVT::v32f32, MVT::v32f16, Expand);
283
284 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
285 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
286
287 setTruncStoreAction(MVT::v2f64, MVT::v2f32, Expand);
288 setTruncStoreAction(MVT::v2f64, MVT::v2f16, Expand);
289
290 setTruncStoreAction(MVT::v3i64, MVT::v3i32, Expand);
291 setTruncStoreAction(MVT::v3i64, MVT::v3i16, Expand);
292 setTruncStoreAction(MVT::v3f64, MVT::v3f32, Expand);
293 setTruncStoreAction(MVT::v3f64, MVT::v3f16, Expand);
294
295 setTruncStoreAction(MVT::v4i64, MVT::v4i32, Expand);
296 setTruncStoreAction(MVT::v4i64, MVT::v4i16, Expand);
297 setTruncStoreAction(MVT::v4f64, MVT::v4f32, Expand);
298 setTruncStoreAction(MVT::v4f64, MVT::v4f16, Expand);
299
300 setTruncStoreAction(MVT::v8f64, MVT::v8f32, Expand);
301 setTruncStoreAction(MVT::v8f64, MVT::v8f16, Expand);
302
303 setTruncStoreAction(MVT::v16f64, MVT::v16f32, Expand);
304 setTruncStoreAction(MVT::v16f64, MVT::v16f16, Expand);
305 setTruncStoreAction(MVT::v16i64, MVT::v16i16, Expand);
306 setTruncStoreAction(MVT::v16i64, MVT::v16i16, Expand);
307 setTruncStoreAction(MVT::v16i64, MVT::v16i8, Expand);
308 setTruncStoreAction(MVT::v16i64, MVT::v16i8, Expand);
309 setTruncStoreAction(MVT::v16i64, MVT::v16i1, Expand);
310
311 setOperationAction(ISD::Constant, MVT::i32, Legal);
312 setOperationAction(ISD::Constant, MVT::i64, Legal);
313 setOperationAction(ISD::ConstantFP, MVT::f32, Legal);
314 setOperationAction(ISD::ConstantFP, MVT::f64, Legal);
315
316 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
317 setOperationAction(ISD::BRIND, MVT::Other, Expand);
318
319 // This is totally unsupported, just custom lower to produce an error.
320 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
321
322 // Library functions. These default to Expand, but we have instructions
323 // for them.
324 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
325 setOperationAction(ISD::FEXP2, MVT::f32, Legal);
326 setOperationAction(ISD::FPOW, MVT::f32, Legal);
327 setOperationAction(ISD::FLOG2, MVT::f32, Legal);
328 setOperationAction(ISD::FABS, MVT::f32, Legal);
329 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
330 setOperationAction(ISD::FRINT, MVT::f32, Legal);
331 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
332 setOperationAction(ISD::FMINNUM, MVT::f32, Legal);
333 setOperationAction(ISD::FMAXNUM, MVT::f32, Legal);
334
335 setOperationAction(ISD::FROUND, MVT::f32, Custom);
336 setOperationAction(ISD::FROUND, MVT::f64, Custom);
337
338 setOperationAction(ISD::FLOG, MVT::f32, Custom);
339 setOperationAction(ISD::FLOG10, MVT::f32, Custom);
340 setOperationAction(ISD::FEXP, MVT::f32, Custom);
341
342
343 setOperationAction(ISD::FNEARBYINT, MVT::f32, Custom);
344 setOperationAction(ISD::FNEARBYINT, MVT::f64, Custom);
345
346 setOperationAction(ISD::FREM, MVT::f16, Custom);
347 setOperationAction(ISD::FREM, MVT::f32, Custom);
348 setOperationAction(ISD::FREM, MVT::f64, Custom);
349
350 // Expand to fneg + fadd.
351 setOperationAction(ISD::FSUB, MVT::f64, Expand);
352
353 setOperationAction(ISD::CONCAT_VECTORS, MVT::v3i32, Custom);
354 setOperationAction(ISD::CONCAT_VECTORS, MVT::v3f32, Custom);
355 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Custom);
356 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4f32, Custom);
357 setOperationAction(ISD::CONCAT_VECTORS, MVT::v5i32, Custom);
358 setOperationAction(ISD::CONCAT_VECTORS, MVT::v5f32, Custom);
359 setOperationAction(ISD::CONCAT_VECTORS, MVT::v6i32, Custom);
360 setOperationAction(ISD::CONCAT_VECTORS, MVT::v6f32, Custom);
361 setOperationAction(ISD::CONCAT_VECTORS, MVT::v7i32, Custom);
362 setOperationAction(ISD::CONCAT_VECTORS, MVT::v7f32, Custom);
363 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i32, Custom);
364 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f32, Custom);
365 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v2f16, Custom);
366 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v2i16, Custom);
367 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v2f32, Custom);
368 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v2i32, Custom);
369 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v3f32, Custom);
370 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v3i32, Custom);
371 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v4f32, Custom);
372 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v4i32, Custom);
373 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v5f32, Custom);
374 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v5i32, Custom);
375 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v6f32, Custom);
376 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v6i32, Custom);
377 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v7f32, Custom);
378 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v7i32, Custom);
379 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v8f32, Custom);
380 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v8i32, Custom);
381 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v16f32, Custom);
382 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v16i32, Custom);
383 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v32f32, Custom);
384 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v32i32, Custom);
385 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v2f64, Custom);
386 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v2i64, Custom);
387 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v3f64, Custom);
388 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v3i64, Custom);
389 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v4f64, Custom);
390 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v4i64, Custom);
391 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v8f64, Custom);
392 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v8i64, Custom);
393 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v16f64, Custom);
394 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v16i64, Custom);
395
396 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
397 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Custom);
398 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Custom);
399
400 const MVT ScalarIntVTs[] = { MVT::i32, MVT::i64 };
401 for (MVT VT : ScalarIntVTs) {
402 // These should use [SU]DIVREM, so set them to expand
403 setOperationAction(ISD::SDIV, VT, Expand);
404 setOperationAction(ISD::UDIV, VT, Expand);
405 setOperationAction(ISD::SREM, VT, Expand);
406 setOperationAction(ISD::UREM, VT, Expand);
407
408 // GPU does not have divrem function for signed or unsigned.
409 setOperationAction(ISD::SDIVREM, VT, Custom);
410 setOperationAction(ISD::UDIVREM, VT, Custom);
411
412 // GPU does not have [S|U]MUL_LOHI functions as a single instruction.
413 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
414 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
415
416 setOperationAction(ISD::BSWAP, VT, Expand);
417 setOperationAction(ISD::CTTZ, VT, Expand);
418 setOperationAction(ISD::CTLZ, VT, Expand);
419
420 // AMDGPU uses ADDC/SUBC/ADDE/SUBE
421 setOperationAction(ISD::ADDC, VT, Legal);
422 setOperationAction(ISD::SUBC, VT, Legal);
423 setOperationAction(ISD::ADDE, VT, Legal);
424 setOperationAction(ISD::SUBE, VT, Legal);
425 }
426
427 // The hardware supports 32-bit FSHR, but not FSHL.
428 setOperationAction(ISD::FSHR, MVT::i32, Legal);
429
430 // The hardware supports 32-bit ROTR, but not ROTL.
431 setOperationAction(ISD::ROTL, MVT::i32, Expand);
432 setOperationAction(ISD::ROTL, MVT::i64, Expand);
433 setOperationAction(ISD::ROTR, MVT::i64, Expand);
434
435 setOperationAction(ISD::MULHU, MVT::i16, Expand);
436 setOperationAction(ISD::MULHS, MVT::i16, Expand);
437
438 setOperationAction(ISD::MUL, MVT::i64, Expand);
439 setOperationAction(ISD::MULHU, MVT::i64, Expand);
440 setOperationAction(ISD::MULHS, MVT::i64, Expand);
441 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
442 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
443 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
444 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
445 setOperationAction(ISD::SELECT_CC, MVT::i64, Expand);
446
447 setOperationAction(ISD::SMIN, MVT::i32, Legal);
448 setOperationAction(ISD::UMIN, MVT::i32, Legal);
449 setOperationAction(ISD::SMAX, MVT::i32, Legal);
450 setOperationAction(ISD::UMAX, MVT::i32, Legal);
451
452 setOperationAction(ISD::CTTZ, MVT::i64, Custom);
453 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Custom);
454 setOperationAction(ISD::CTLZ, MVT::i64, Custom);
455 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
456
457 static const MVT::SimpleValueType VectorIntTypes[] = {
458 MVT::v2i32, MVT::v3i32, MVT::v4i32, MVT::v5i32, MVT::v6i32, MVT::v7i32};
459
460 for (MVT VT : VectorIntTypes) {
461 // Expand the following operations for the current type by default.
462 setOperationAction(ISD::ADD, VT, Expand);
463 setOperationAction(ISD::AND, VT, Expand);
464 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
465 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
466 setOperationAction(ISD::MUL, VT, Expand);
467 setOperationAction(ISD::MULHU, VT, Expand);
468 setOperationAction(ISD::MULHS, VT, Expand);
469 setOperationAction(ISD::OR, VT, Expand);
470 setOperationAction(ISD::SHL, VT, Expand);
471 setOperationAction(ISD::SRA, VT, Expand);
472 setOperationAction(ISD::SRL, VT, Expand);
473 setOperationAction(ISD::ROTL, VT, Expand);
474 setOperationAction(ISD::ROTR, VT, Expand);
475 setOperationAction(ISD::SUB, VT, Expand);
476 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
477 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
478 setOperationAction(ISD::SDIV, VT, Expand);
479 setOperationAction(ISD::UDIV, VT, Expand);
480 setOperationAction(ISD::SREM, VT, Expand);
481 setOperationAction(ISD::UREM, VT, Expand);
482 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
483 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
484 setOperationAction(ISD::SDIVREM, VT, Expand);
485 setOperationAction(ISD::UDIVREM, VT, Expand);
486 setOperationAction(ISD::SELECT, VT, Expand);
487 setOperationAction(ISD::VSELECT, VT, Expand);
488 setOperationAction(ISD::SELECT_CC, VT, Expand);
489 setOperationAction(ISD::XOR, VT, Expand);
490 setOperationAction(ISD::BSWAP, VT, Expand);
491 setOperationAction(ISD::CTPOP, VT, Expand);
492 setOperationAction(ISD::CTTZ, VT, Expand);
493 setOperationAction(ISD::CTLZ, VT, Expand);
494 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
495 setOperationAction(ISD::SETCC, VT, Expand);
496 }
497
498 static const MVT::SimpleValueType FloatVectorTypes[] = {
499 MVT::v2f32, MVT::v3f32, MVT::v4f32, MVT::v5f32, MVT::v6f32, MVT::v7f32};
500
501 for (MVT VT : FloatVectorTypes) {
502 setOperationAction(ISD::FABS, VT, Expand);
503 setOperationAction(ISD::FMINNUM, VT, Expand);
504 setOperationAction(ISD::FMAXNUM, VT, Expand);
505 setOperationAction(ISD::FADD, VT, Expand);
506 setOperationAction(ISD::FCEIL, VT, Expand);
507 setOperationAction(ISD::FCOS, VT, Expand);
508 setOperationAction(ISD::FDIV, VT, Expand);
509 setOperationAction(ISD::FEXP2, VT, Expand);
510 setOperationAction(ISD::FEXP, VT, Expand);
511 setOperationAction(ISD::FLOG2, VT, Expand);
512 setOperationAction(ISD::FREM, VT, Expand);
513 setOperationAction(ISD::FLOG, VT, Expand);
514 setOperationAction(ISD::FLOG10, VT, Expand);
515 setOperationAction(ISD::FPOW, VT, Expand);
516 setOperationAction(ISD::FFLOOR, VT, Expand);
517 setOperationAction(ISD::FTRUNC, VT, Expand);
518 setOperationAction(ISD::FMUL, VT, Expand);
519 setOperationAction(ISD::FMA, VT, Expand);
520 setOperationAction(ISD::FRINT, VT, Expand);
521 setOperationAction(ISD::FNEARBYINT, VT, Expand);
522 setOperationAction(ISD::FSQRT, VT, Expand);
523 setOperationAction(ISD::FSIN, VT, Expand);
524 setOperationAction(ISD::FSUB, VT, Expand);
525 setOperationAction(ISD::FNEG, VT, Expand);
526 setOperationAction(ISD::VSELECT, VT, Expand);
527 setOperationAction(ISD::SELECT_CC, VT, Expand);
528 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
529 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
530 setOperationAction(ISD::SETCC, VT, Expand);
531 setOperationAction(ISD::FCANONICALIZE, VT, Expand);
532 }
533
534 // This causes using an unrolled select operation rather than expansion with
535 // bit operations. This is in general better, but the alternative using BFI
536 // instructions may be better if the select sources are SGPRs.
537 setOperationAction(ISD::SELECT, MVT::v2f32, Promote);
538 AddPromotedToType(ISD::SELECT, MVT::v2f32, MVT::v2i32);
539
540 setOperationAction(ISD::SELECT, MVT::v3f32, Promote);
541 AddPromotedToType(ISD::SELECT, MVT::v3f32, MVT::v3i32);
542
543 setOperationAction(ISD::SELECT, MVT::v4f32, Promote);
544 AddPromotedToType(ISD::SELECT, MVT::v4f32, MVT::v4i32);
545
546 setOperationAction(ISD::SELECT, MVT::v5f32, Promote);
547 AddPromotedToType(ISD::SELECT, MVT::v5f32, MVT::v5i32);
548
549 setOperationAction(ISD::SELECT, MVT::v6f32, Promote);
550 AddPromotedToType(ISD::SELECT, MVT::v6f32, MVT::v6i32);
551
552 setOperationAction(ISD::SELECT, MVT::v7f32, Promote);
553 AddPromotedToType(ISD::SELECT, MVT::v7f32, MVT::v7i32);
554
555 // There are no libcalls of any kind.
556 for (int I = 0; I < RTLIB::UNKNOWN_LIBCALL; ++I)
557 setLibcallName(static_cast<RTLIB::Libcall>(I), nullptr);
558
559 setSchedulingPreference(Sched::RegPressure);
560 setJumpIsExpensive(true);
561
562 // FIXME: This is only partially true. If we have to do vector compares, any
563 // SGPR pair can be a condition register. If we have a uniform condition, we
564 // are better off doing SALU operations, where there is only one SCC. For now,
565 // we don't have a way of knowing during instruction selection if a condition
566 // will be uniform and we always use vector compares. Assume we are using
567 // vector compares until that is fixed.
568 setHasMultipleConditionRegisters(true);
569
570 setMinCmpXchgSizeInBits(32);
571 setSupportsUnalignedAtomics(false);
572
573 PredictableSelectIsExpensive = false;
574
575 // We want to find all load dependencies for long chains of stores to enable
576 // merging into very wide vectors. The problem is with vectors with > 4
577 // elements. MergeConsecutiveStores will attempt to merge these because x8/x16
578 // vectors are a legal type, even though we have to split the loads
579 // usually. When we can more precisely specify load legality per address
580 // space, we should be able to make FindBetterChain/MergeConsecutiveStores
581 // smarter so that they can figure out what to do in 2 iterations without all
582 // N > 4 stores on the same chain.
583 GatherAllAliasesMaxDepth = 16;
584
585 // memcpy/memmove/memset are expanded in the IR, so we shouldn't need to worry
586 // about these during lowering.
587 MaxStoresPerMemcpy = 0xffffffff;
588 MaxStoresPerMemmove = 0xffffffff;
589 MaxStoresPerMemset = 0xffffffff;
590
591 // The expansion for 64-bit division is enormous.
592 if (AMDGPUBypassSlowDiv)
593 addBypassSlowDiv(64, 32);
594
595 setTargetDAGCombine(ISD::BITCAST);
596 setTargetDAGCombine(ISD::SHL);
597 setTargetDAGCombine(ISD::SRA);
598 setTargetDAGCombine(ISD::SRL);
599 setTargetDAGCombine(ISD::TRUNCATE);
600 setTargetDAGCombine(ISD::MUL);
601 setTargetDAGCombine(ISD::MULHU);
602 setTargetDAGCombine(ISD::MULHS);
603 setTargetDAGCombine(ISD::SELECT);
604 setTargetDAGCombine(ISD::SELECT_CC);
605 setTargetDAGCombine(ISD::STORE);
606 setTargetDAGCombine(ISD::FADD);
607 setTargetDAGCombine(ISD::FSUB);
608 setTargetDAGCombine(ISD::FNEG);
609 setTargetDAGCombine(ISD::FABS);
610 setTargetDAGCombine(ISD::AssertZext);
611 setTargetDAGCombine(ISD::AssertSext);
612 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
613}
614
615bool AMDGPUTargetLowering::mayIgnoreSignedZero(SDValue Op) const {
616 if (getTargetMachine().Options.NoSignedZerosFPMath)
617 return true;
618
619 const auto Flags = Op.getNode()->getFlags();
620 if (Flags.hasNoSignedZeros())
621 return true;
622
623 return false;
624}
625
626//===----------------------------------------------------------------------===//
627// Target Information
628//===----------------------------------------------------------------------===//
629
630LLVM_READNONE__attribute__((__const__))
631static bool fnegFoldsIntoOp(unsigned Opc) {
632 switch (Opc) {
633 case ISD::FADD:
634 case ISD::FSUB:
635 case ISD::FMUL:
636 case ISD::FMA:
637 case ISD::FMAD:
638 case ISD::FMINNUM:
639 case ISD::FMAXNUM:
640 case ISD::FMINNUM_IEEE:
641 case ISD::FMAXNUM_IEEE:
642 case ISD::FSIN:
643 case ISD::FTRUNC:
644 case ISD::FRINT:
645 case ISD::FNEARBYINT:
646 case ISD::FCANONICALIZE:
647 case AMDGPUISD::RCP:
648 case AMDGPUISD::RCP_LEGACY:
649 case AMDGPUISD::RCP_IFLAG:
650 case AMDGPUISD::SIN_HW:
651 case AMDGPUISD::FMUL_LEGACY:
652 case AMDGPUISD::FMIN_LEGACY:
653 case AMDGPUISD::FMAX_LEGACY:
654 case AMDGPUISD::FMED3:
655 // TODO: handle llvm.amdgcn.fma.legacy
656 return true;
657 default:
658 return false;
659 }
660}
661
662/// \p returns true if the operation will definitely need to use a 64-bit
663/// encoding, and thus will use a VOP3 encoding regardless of the source
664/// modifiers.
665LLVM_READONLY__attribute__((__pure__))
666static bool opMustUseVOP3Encoding(const SDNode *N, MVT VT) {
667 return N->getNumOperands() > 2 || VT == MVT::f64;
668}
669
670// Most FP instructions support source modifiers, but this could be refined
671// slightly.
672LLVM_READONLY__attribute__((__pure__))
673static bool hasSourceMods(const SDNode *N) {
674 if (isa<MemSDNode>(N))
675 return false;
676
677 switch (N->getOpcode()) {
678 case ISD::CopyToReg:
679 case ISD::SELECT:
680 case ISD::FDIV:
681 case ISD::FREM:
682 case ISD::INLINEASM:
683 case ISD::INLINEASM_BR:
684 case AMDGPUISD::DIV_SCALE:
685 case ISD::INTRINSIC_W_CHAIN:
686
687 // TODO: Should really be looking at the users of the bitcast. These are
688 // problematic because bitcasts are used to legalize all stores to integer
689 // types.
690 case ISD::BITCAST:
691 return false;
692 case ISD::INTRINSIC_WO_CHAIN: {
693 switch (cast<ConstantSDNode>(N->getOperand(0))->getZExtValue()) {
694 case Intrinsic::amdgcn_interp_p1:
695 case Intrinsic::amdgcn_interp_p2:
696 case Intrinsic::amdgcn_interp_mov:
697 case Intrinsic::amdgcn_interp_p1_f16:
698 case Intrinsic::amdgcn_interp_p2_f16:
699 return false;
700 default:
701 return true;
702 }
703 }
704 default:
705 return true;
706 }
707}
708
709bool AMDGPUTargetLowering::allUsesHaveSourceMods(const SDNode *N,
710 unsigned CostThreshold) {
711 // Some users (such as 3-operand FMA/MAD) must use a VOP3 encoding, and thus
712 // it is truly free to use a source modifier in all cases. If there are
713 // multiple users but for each one will necessitate using VOP3, there will be
714 // a code size increase. Try to avoid increasing code size unless we know it
715 // will save on the instruction count.
716 unsigned NumMayIncreaseSize = 0;
717 MVT VT = N->getValueType(0).getScalarType().getSimpleVT();
718
719 // XXX - Should this limit number of uses to check?
720 for (const SDNode *U : N->uses()) {
721 if (!hasSourceMods(U))
722 return false;
723
724 if (!opMustUseVOP3Encoding(U, VT)) {
725 if (++NumMayIncreaseSize > CostThreshold)
726 return false;
727 }
728 }
729
730 return true;
731}
732
733EVT AMDGPUTargetLowering::getTypeForExtReturn(LLVMContext &Context, EVT VT,
734 ISD::NodeType ExtendKind) const {
735 assert(!VT.isVector() && "only scalar expected")(static_cast <bool> (!VT.isVector() && "only scalar expected"
) ? void (0) : __assert_fail ("!VT.isVector() && \"only scalar expected\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp"
, 735, __extension__ __PRETTY_FUNCTION__))
;
736
737 // Round to the next multiple of 32-bits.
738 unsigned Size = VT.getSizeInBits();
739 if (Size <= 32)
740 return MVT::i32;
741 return EVT::getIntegerVT(Context, 32 * ((Size + 31) / 32));
742}
743
744MVT AMDGPUTargetLowering::getVectorIdxTy(const DataLayout &) const {
745 return MVT::i32;
746}
747
748bool AMDGPUTargetLowering::isSelectSupported(SelectSupportKind SelType) const {
749 return true;
750}
751
752// The backend supports 32 and 64 bit floating point immediates.
753// FIXME: Why are we reporting vectors of FP immediates as legal?
754bool AMDGPUTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT,
755 bool ForCodeSize) const {
756 EVT ScalarVT = VT.getScalarType();
757 return (ScalarVT == MVT::f32 || ScalarVT == MVT::f64 ||
758 (ScalarVT == MVT::f16 && Subtarget->has16BitInsts()));
759}
760
761// We don't want to shrink f64 / f32 constants.
762bool AMDGPUTargetLowering::ShouldShrinkFPConstant(EVT VT) const {
763 EVT ScalarVT = VT.getScalarType();
764 return (ScalarVT != MVT::f32 && ScalarVT != MVT::f64);
765}
766
767bool AMDGPUTargetLowering::shouldReduceLoadWidth(SDNode *N,
768 ISD::LoadExtType ExtTy,
769 EVT NewVT) const {
770 // TODO: This may be worth removing. Check regression tests for diffs.
771 if (!TargetLoweringBase::shouldReduceLoadWidth(N, ExtTy, NewVT))
772 return false;
773
774 unsigned NewSize = NewVT.getStoreSizeInBits();
775
776 // If we are reducing to a 32-bit load or a smaller multi-dword load,
777 // this is always better.
778 if (NewSize >= 32)
779 return true;
780
781 EVT OldVT = N->getValueType(0);
782 unsigned OldSize = OldVT.getStoreSizeInBits();
783
784 MemSDNode *MN = cast<MemSDNode>(N);
785 unsigned AS = MN->getAddressSpace();
786 // Do not shrink an aligned scalar load to sub-dword.
787 // Scalar engine cannot do sub-dword loads.
788 if (OldSize >= 32 && NewSize < 32 && MN->getAlignment() >= 4 &&
789 (AS == AMDGPUAS::CONSTANT_ADDRESS ||
790 AS == AMDGPUAS::CONSTANT_ADDRESS_32BIT ||
791 (isa<LoadSDNode>(N) &&
792 AS == AMDGPUAS::GLOBAL_ADDRESS && MN->isInvariant())) &&
793 AMDGPUInstrInfo::isUniformMMO(MN->getMemOperand()))
794 return false;
795
796 // Don't produce extloads from sub 32-bit types. SI doesn't have scalar
797 // extloads, so doing one requires using a buffer_load. In cases where we
798 // still couldn't use a scalar load, using the wider load shouldn't really
799 // hurt anything.
800
801 // If the old size already had to be an extload, there's no harm in continuing
802 // to reduce the width.
803 return (OldSize < 32);
804}
805
806bool AMDGPUTargetLowering::isLoadBitCastBeneficial(EVT LoadTy, EVT CastTy,
807 const SelectionDAG &DAG,
808 const MachineMemOperand &MMO) const {
809
810 assert(LoadTy.getSizeInBits() == CastTy.getSizeInBits())(static_cast <bool> (LoadTy.getSizeInBits() == CastTy.getSizeInBits
()) ? void (0) : __assert_fail ("LoadTy.getSizeInBits() == CastTy.getSizeInBits()"
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp"
, 810, __extension__ __PRETTY_FUNCTION__))
;
811
812 if (LoadTy.getScalarType() == MVT::i32)
813 return false;
814
815 unsigned LScalarSize = LoadTy.getScalarSizeInBits();
816 unsigned CastScalarSize = CastTy.getScalarSizeInBits();
817
818 if ((LScalarSize >= CastScalarSize) && (CastScalarSize < 32))
819 return false;
820
821 bool Fast = false;
822 return allowsMemoryAccessForAlignment(*DAG.getContext(), DAG.getDataLayout(),
823 CastTy, MMO, &Fast) &&
824 Fast;
825}
826
827// SI+ has instructions for cttz / ctlz for 32-bit values. This is probably also
828// profitable with the expansion for 64-bit since it's generally good to
829// speculate things.
830// FIXME: These should really have the size as a parameter.
831bool AMDGPUTargetLowering::isCheapToSpeculateCttz() const {
832 return true;
833}
834
835bool AMDGPUTargetLowering::isCheapToSpeculateCtlz() const {
836 return true;
837}
838
839bool AMDGPUTargetLowering::isSDNodeAlwaysUniform(const SDNode *N) const {
840 switch (N->getOpcode()) {
841 case ISD::EntryToken:
842 case ISD::TokenFactor:
843 return true;
844 case ISD::INTRINSIC_WO_CHAIN: {
845 unsigned IntrID = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
846 switch (IntrID) {
847 case Intrinsic::amdgcn_readfirstlane:
848 case Intrinsic::amdgcn_readlane:
849 return true;
850 }
851 return false;
852 }
853 case ISD::LOAD:
854 if (cast<LoadSDNode>(N)->getMemOperand()->getAddrSpace() ==
855 AMDGPUAS::CONSTANT_ADDRESS_32BIT)
856 return true;
857 return false;
858 }
859 return false;
860}
861
862SDValue AMDGPUTargetLowering::getNegatedExpression(
863 SDValue Op, SelectionDAG &DAG, bool LegalOperations, bool ForCodeSize,
864 NegatibleCost &Cost, unsigned Depth) const {
865
866 switch (Op.getOpcode()) {
867 case ISD::FMA:
868 case ISD::FMAD: {
869 // Negating a fma is not free if it has users without source mods.
870 if (!allUsesHaveSourceMods(Op.getNode()))
871 return SDValue();
872 break;
873 }
874 default:
875 break;
876 }
877
878 return TargetLowering::getNegatedExpression(Op, DAG, LegalOperations,
879 ForCodeSize, Cost, Depth);
880}
881
882//===---------------------------------------------------------------------===//
883// Target Properties
884//===---------------------------------------------------------------------===//
885
886bool AMDGPUTargetLowering::isFAbsFree(EVT VT) const {
887 assert(VT.isFloatingPoint())(static_cast <bool> (VT.isFloatingPoint()) ? void (0) :
__assert_fail ("VT.isFloatingPoint()", "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp"
, 887, __extension__ __PRETTY_FUNCTION__))
;
888
889 // Packed operations do not have a fabs modifier.
890 return VT == MVT::f32 || VT == MVT::f64 ||
891 (Subtarget->has16BitInsts() && VT == MVT::f16);
892}
893
894bool AMDGPUTargetLowering::isFNegFree(EVT VT) const {
895 assert(VT.isFloatingPoint())(static_cast <bool> (VT.isFloatingPoint()) ? void (0) :
__assert_fail ("VT.isFloatingPoint()", "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp"
, 895, __extension__ __PRETTY_FUNCTION__))
;
896 // Report this based on the end legalized type.
897 VT = VT.getScalarType();
898 return VT == MVT::f32 || VT == MVT::f64 || VT == MVT::f16;
899}
900
901bool AMDGPUTargetLowering:: storeOfVectorConstantIsCheap(EVT MemVT,
902 unsigned NumElem,
903 unsigned AS) const {
904 return true;
905}
906
907bool AMDGPUTargetLowering::aggressivelyPreferBuildVectorSources(EVT VecVT) const {
908 // There are few operations which truly have vector input operands. Any vector
909 // operation is going to involve operations on each component, and a
910 // build_vector will be a copy per element, so it always makes sense to use a
911 // build_vector input in place of the extracted element to avoid a copy into a
912 // super register.
913 //
914 // We should probably only do this if all users are extracts only, but this
915 // should be the common case.
916 return true;
917}
918
919bool AMDGPUTargetLowering::isTruncateFree(EVT Source, EVT Dest) const {
920 // Truncate is just accessing a subregister.
921
922 unsigned SrcSize = Source.getSizeInBits();
923 unsigned DestSize = Dest.getSizeInBits();
924
925 return DestSize < SrcSize && DestSize % 32 == 0 ;
926}
927
928bool AMDGPUTargetLowering::isTruncateFree(Type *Source, Type *Dest) const {
929 // Truncate is just accessing a subregister.
930
931 unsigned SrcSize = Source->getScalarSizeInBits();
932 unsigned DestSize = Dest->getScalarSizeInBits();
933
934 if (DestSize== 16 && Subtarget->has16BitInsts())
935 return SrcSize >= 32;
936
937 return DestSize < SrcSize && DestSize % 32 == 0;
938}
939
940bool AMDGPUTargetLowering::isZExtFree(Type *Src, Type *Dest) const {
941 unsigned SrcSize = Src->getScalarSizeInBits();
942 unsigned DestSize = Dest->getScalarSizeInBits();
943
944 if (SrcSize == 16 && Subtarget->has16BitInsts())
945 return DestSize >= 32;
946
947 return SrcSize == 32 && DestSize == 64;
948}
949
950bool AMDGPUTargetLowering::isZExtFree(EVT Src, EVT Dest) const {
951 // Any register load of a 64-bit value really requires 2 32-bit moves. For all
952 // practical purposes, the extra mov 0 to load a 64-bit is free. As used,
953 // this will enable reducing 64-bit operations the 32-bit, which is always
954 // good.
955
956 if (Src == MVT::i16)
957 return Dest == MVT::i32 ||Dest == MVT::i64 ;
958
959 return Src == MVT::i32 && Dest == MVT::i64;
960}
961
962bool AMDGPUTargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
963 return isZExtFree(Val.getValueType(), VT2);
964}
965
966bool AMDGPUTargetLowering::isNarrowingProfitable(EVT SrcVT, EVT DestVT) const {
967 // There aren't really 64-bit registers, but pairs of 32-bit ones and only a
968 // limited number of native 64-bit operations. Shrinking an operation to fit
969 // in a single 32-bit register should always be helpful. As currently used,
970 // this is much less general than the name suggests, and is only used in
971 // places trying to reduce the sizes of loads. Shrinking loads to < 32-bits is
972 // not profitable, and may actually be harmful.
973 return SrcVT.getSizeInBits() > 32 && DestVT.getSizeInBits() == 32;
974}
975
976//===---------------------------------------------------------------------===//
977// TargetLowering Callbacks
978//===---------------------------------------------------------------------===//
979
980CCAssignFn *AMDGPUCallLowering::CCAssignFnForCall(CallingConv::ID CC,
981 bool IsVarArg) {
982 switch (CC) {
983 case CallingConv::AMDGPU_VS:
984 case CallingConv::AMDGPU_GS:
985 case CallingConv::AMDGPU_PS:
986 case CallingConv::AMDGPU_CS:
987 case CallingConv::AMDGPU_HS:
988 case CallingConv::AMDGPU_ES:
989 case CallingConv::AMDGPU_LS:
990 return CC_AMDGPU;
991 case CallingConv::C:
992 case CallingConv::Fast:
993 case CallingConv::Cold:
994 return CC_AMDGPU_Func;
995 case CallingConv::AMDGPU_Gfx:
996 return CC_SI_Gfx;
997 case CallingConv::AMDGPU_KERNEL:
998 case CallingConv::SPIR_KERNEL:
999 default:
1000 report_fatal_error("Unsupported calling convention for call");
1001 }
1002}
1003
1004CCAssignFn *AMDGPUCallLowering::CCAssignFnForReturn(CallingConv::ID CC,
1005 bool IsVarArg) {
1006 switch (CC) {
1007 case CallingConv::AMDGPU_KERNEL:
1008 case CallingConv::SPIR_KERNEL:
1009 llvm_unreachable("kernels should not be handled here")::llvm::llvm_unreachable_internal("kernels should not be handled here"
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp"
, 1009)
;
1010 case CallingConv::AMDGPU_VS:
1011 case CallingConv::AMDGPU_GS:
1012 case CallingConv::AMDGPU_PS:
1013 case CallingConv::AMDGPU_CS:
1014 case CallingConv::AMDGPU_HS:
1015 case CallingConv::AMDGPU_ES:
1016 case CallingConv::AMDGPU_LS:
1017 return RetCC_SI_Shader;
1018 case CallingConv::AMDGPU_Gfx:
1019 return RetCC_SI_Gfx;
1020 case CallingConv::C:
1021 case CallingConv::Fast:
1022 case CallingConv::Cold:
1023 return RetCC_AMDGPU_Func;
1024 default:
1025 report_fatal_error("Unsupported calling convention.");
1026 }
1027}
1028
1029/// The SelectionDAGBuilder will automatically promote function arguments
1030/// with illegal types. However, this does not work for the AMDGPU targets
1031/// since the function arguments are stored in memory as these illegal types.
1032/// In order to handle this properly we need to get the original types sizes
1033/// from the LLVM IR Function and fixup the ISD:InputArg values before
1034/// passing them to AnalyzeFormalArguments()
1035
1036/// When the SelectionDAGBuilder computes the Ins, it takes care of splitting
1037/// input values across multiple registers. Each item in the Ins array
1038/// represents a single value that will be stored in registers. Ins[x].VT is
1039/// the value type of the value that will be stored in the register, so
1040/// whatever SDNode we lower the argument to needs to be this type.
1041///
1042/// In order to correctly lower the arguments we need to know the size of each
1043/// argument. Since Ins[x].VT gives us the size of the register that will
1044/// hold the value, we need to look at Ins[x].ArgVT to see the 'real' type
1045/// for the original function argument so that we can deduce the correct memory
1046/// type to use for Ins[x]. In most cases the correct memory type will be
1047/// Ins[x].ArgVT. However, this will not always be the case. If, for example,
1048/// we have a kernel argument of type v8i8, this argument will be split into
1049/// 8 parts and each part will be represented by its own item in the Ins array.
1050/// For each part the Ins[x].ArgVT will be the v8i8, which is the full type of
1051/// the argument before it was split. From this, we deduce that the memory type
1052/// for each individual part is i8. We pass the memory type as LocVT to the
1053/// calling convention analysis function and the register type (Ins[x].VT) as
1054/// the ValVT.
1055void AMDGPUTargetLowering::analyzeFormalArgumentsCompute(
1056 CCState &State,
1057 const SmallVectorImpl<ISD::InputArg> &Ins) const {
1058 const MachineFunction &MF = State.getMachineFunction();
1059 const Function &Fn = MF.getFunction();
1060 LLVMContext &Ctx = Fn.getParent()->getContext();
1061 const AMDGPUSubtarget &ST = AMDGPUSubtarget::get(MF);
1062 const unsigned ExplicitOffset = ST.getExplicitKernelArgOffset(Fn);
1063 CallingConv::ID CC = Fn.getCallingConv();
1064
1065 Align MaxAlign = Align(1);
1066 uint64_t ExplicitArgOffset = 0;
1067 const DataLayout &DL = Fn.getParent()->getDataLayout();
1068
1069 unsigned InIndex = 0;
1070
1071 for (const Argument &Arg : Fn.args()) {
1072 const bool IsByRef = Arg.hasByRefAttr();
1073 Type *BaseArgTy = Arg.getType();
1074 Type *MemArgTy = IsByRef ? Arg.getParamByRefType() : BaseArgTy;
1075 MaybeAlign Alignment = IsByRef ? Arg.getParamAlign() : None;
1076 if (!Alignment)
1077 Alignment = DL.getABITypeAlign(MemArgTy);
1078 MaxAlign = max(Alignment, MaxAlign);
1079 uint64_t AllocSize = DL.getTypeAllocSize(MemArgTy);
1080
1081 uint64_t ArgOffset = alignTo(ExplicitArgOffset, Alignment) + ExplicitOffset;
1082 ExplicitArgOffset = alignTo(ExplicitArgOffset, Alignment) + AllocSize;
1083
1084 // We're basically throwing away everything passed into us and starting over
1085 // to get accurate in-memory offsets. The "PartOffset" is completely useless
1086 // to us as computed in Ins.
1087 //
1088 // We also need to figure out what type legalization is trying to do to get
1089 // the correct memory offsets.
1090
1091 SmallVector<EVT, 16> ValueVTs;
1092 SmallVector<uint64_t, 16> Offsets;
1093 ComputeValueVTs(*this, DL, BaseArgTy, ValueVTs, &Offsets, ArgOffset);
1094
1095 for (unsigned Value = 0, NumValues = ValueVTs.size();
1096 Value != NumValues; ++Value) {
1097 uint64_t BasePartOffset = Offsets[Value];
1098
1099 EVT ArgVT = ValueVTs[Value];
1100 EVT MemVT = ArgVT;
1101 MVT RegisterVT = getRegisterTypeForCallingConv(Ctx, CC, ArgVT);
1102 unsigned NumRegs = getNumRegistersForCallingConv(Ctx, CC, ArgVT);
1103
1104 if (NumRegs == 1) {
1105 // This argument is not split, so the IR type is the memory type.
1106 if (ArgVT.isExtended()) {
1107 // We have an extended type, like i24, so we should just use the
1108 // register type.
1109 MemVT = RegisterVT;
1110 } else {
1111 MemVT = ArgVT;
1112 }
1113 } else if (ArgVT.isVector() && RegisterVT.isVector() &&
1114 ArgVT.getScalarType() == RegisterVT.getScalarType()) {
1115 assert(ArgVT.getVectorNumElements() > RegisterVT.getVectorNumElements())(static_cast <bool> (ArgVT.getVectorNumElements() > RegisterVT
.getVectorNumElements()) ? void (0) : __assert_fail ("ArgVT.getVectorNumElements() > RegisterVT.getVectorNumElements()"
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp"
, 1115, __extension__ __PRETTY_FUNCTION__))
;
1116 // We have a vector value which has been split into a vector with
1117 // the same scalar type, but fewer elements. This should handle
1118 // all the floating-point vector types.
1119 MemVT = RegisterVT;
1120 } else if (ArgVT.isVector() &&
1121 ArgVT.getVectorNumElements() == NumRegs) {
1122 // This arg has been split so that each element is stored in a separate
1123 // register.
1124 MemVT = ArgVT.getScalarType();
1125 } else if (ArgVT.isExtended()) {
1126 // We have an extended type, like i65.
1127 MemVT = RegisterVT;
1128 } else {
1129 unsigned MemoryBits = ArgVT.getStoreSizeInBits() / NumRegs;
1130 assert(ArgVT.getStoreSizeInBits() % NumRegs == 0)(static_cast <bool> (ArgVT.getStoreSizeInBits() % NumRegs
== 0) ? void (0) : __assert_fail ("ArgVT.getStoreSizeInBits() % NumRegs == 0"
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp"
, 1130, __extension__ __PRETTY_FUNCTION__))
;
1131 if (RegisterVT.isInteger()) {
1132 MemVT = EVT::getIntegerVT(State.getContext(), MemoryBits);
1133 } else if (RegisterVT.isVector()) {
1134 assert(!RegisterVT.getScalarType().isFloatingPoint())(static_cast <bool> (!RegisterVT.getScalarType().isFloatingPoint
()) ? void (0) : __assert_fail ("!RegisterVT.getScalarType().isFloatingPoint()"
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp"
, 1134, __extension__ __PRETTY_FUNCTION__))
;
1135 unsigned NumElements = RegisterVT.getVectorNumElements();
1136 assert(MemoryBits % NumElements == 0)(static_cast <bool> (MemoryBits % NumElements == 0) ? void
(0) : __assert_fail ("MemoryBits % NumElements == 0", "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp"
, 1136, __extension__ __PRETTY_FUNCTION__))
;
1137 // This vector type has been split into another vector type with
1138 // a different elements size.
1139 EVT ScalarVT = EVT::getIntegerVT(State.getContext(),
1140 MemoryBits / NumElements);
1141 MemVT = EVT::getVectorVT(State.getContext(), ScalarVT, NumElements);
1142 } else {
1143 llvm_unreachable("cannot deduce memory type.")::llvm::llvm_unreachable_internal("cannot deduce memory type."
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp"
, 1143)
;
1144 }
1145 }
1146
1147 // Convert one element vectors to scalar.
1148 if (MemVT.isVector() && MemVT.getVectorNumElements() == 1)
1149 MemVT = MemVT.getScalarType();
1150
1151 // Round up vec3/vec5 argument.
1152 if (MemVT.isVector() && !MemVT.isPow2VectorType()) {
1153 assert(MemVT.getVectorNumElements() == 3 ||(static_cast <bool> (MemVT.getVectorNumElements() == 3 ||
MemVT.getVectorNumElements() == 5) ? void (0) : __assert_fail
("MemVT.getVectorNumElements() == 3 || MemVT.getVectorNumElements() == 5"
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp"
, 1154, __extension__ __PRETTY_FUNCTION__))
1154 MemVT.getVectorNumElements() == 5)(static_cast <bool> (MemVT.getVectorNumElements() == 3 ||
MemVT.getVectorNumElements() == 5) ? void (0) : __assert_fail
("MemVT.getVectorNumElements() == 3 || MemVT.getVectorNumElements() == 5"
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp"
, 1154, __extension__ __PRETTY_FUNCTION__))
;
1155 MemVT = MemVT.getPow2VectorType(State.getContext());
1156 } else if (!MemVT.isSimple() && !MemVT.isVector()) {
1157 MemVT = MemVT.getRoundIntegerType(State.getContext());
1158 }
1159
1160 unsigned PartOffset = 0;
1161 for (unsigned i = 0; i != NumRegs; ++i) {
1162 State.addLoc(CCValAssign::getCustomMem(InIndex++, RegisterVT,
1163 BasePartOffset + PartOffset,
1164 MemVT.getSimpleVT(),
1165 CCValAssign::Full));
1166 PartOffset += MemVT.getStoreSize();
1167 }
1168 }
1169 }
1170}
1171
1172SDValue AMDGPUTargetLowering::LowerReturn(
1173 SDValue Chain, CallingConv::ID CallConv,
1174 bool isVarArg,
1175 const SmallVectorImpl<ISD::OutputArg> &Outs,
1176 const SmallVectorImpl<SDValue> &OutVals,
1177 const SDLoc &DL, SelectionDAG &DAG) const {
1178 // FIXME: Fails for r600 tests
1179 //assert(!isVarArg && Outs.empty() && OutVals.empty() &&
1180 // "wave terminate should not have return values");
1181 return DAG.getNode(AMDGPUISD::ENDPGM, DL, MVT::Other, Chain);
1182}
1183
1184//===---------------------------------------------------------------------===//
1185// Target specific lowering
1186//===---------------------------------------------------------------------===//
1187
1188/// Selects the correct CCAssignFn for a given CallingConvention value.
1189CCAssignFn *AMDGPUTargetLowering::CCAssignFnForCall(CallingConv::ID CC,
1190 bool IsVarArg) {
1191 return AMDGPUCallLowering::CCAssignFnForCall(CC, IsVarArg);
1192}
1193
1194CCAssignFn *AMDGPUTargetLowering::CCAssignFnForReturn(CallingConv::ID CC,
1195 bool IsVarArg) {
1196 return AMDGPUCallLowering::CCAssignFnForReturn(CC, IsVarArg);
1197}
1198
1199SDValue AMDGPUTargetLowering::addTokenForArgument(SDValue Chain,
1200 SelectionDAG &DAG,
1201 MachineFrameInfo &MFI,
1202 int ClobberedFI) const {
1203 SmallVector<SDValue, 8> ArgChains;
1204 int64_t FirstByte = MFI.getObjectOffset(ClobberedFI);
1205 int64_t LastByte = FirstByte + MFI.getObjectSize(ClobberedFI) - 1;
1206
1207 // Include the original chain at the beginning of the list. When this is
1208 // used by target LowerCall hooks, this helps legalize find the
1209 // CALLSEQ_BEGIN node.
1210 ArgChains.push_back(Chain);
1211
1212 // Add a chain value for each stack argument corresponding
1213 for (SDNode::use_iterator U = DAG.getEntryNode().getNode()->use_begin(),
1214 UE = DAG.getEntryNode().getNode()->use_end();
1215 U != UE; ++U) {
1216 if (LoadSDNode *L = dyn_cast<LoadSDNode>(*U)) {
1217 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(L->getBasePtr())) {
1218 if (FI->getIndex() < 0) {
1219 int64_t InFirstByte = MFI.getObjectOffset(FI->getIndex());
1220 int64_t InLastByte = InFirstByte;
1221 InLastByte += MFI.getObjectSize(FI->getIndex()) - 1;
1222
1223 if ((InFirstByte <= FirstByte && FirstByte <= InLastByte) ||
1224 (FirstByte <= InFirstByte && InFirstByte <= LastByte))
1225 ArgChains.push_back(SDValue(L, 1));
1226 }
1227 }
1228 }
1229 }
1230
1231 // Build a tokenfactor for all the chains.
1232 return DAG.getNode(ISD::TokenFactor, SDLoc(Chain), MVT::Other, ArgChains);
1233}
1234
1235SDValue AMDGPUTargetLowering::lowerUnhandledCall(CallLoweringInfo &CLI,
1236 SmallVectorImpl<SDValue> &InVals,
1237 StringRef Reason) const {
1238 SDValue Callee = CLI.Callee;
1239 SelectionDAG &DAG = CLI.DAG;
1240
1241 const Function &Fn = DAG.getMachineFunction().getFunction();
1242
1243 StringRef FuncName("<unknown>");
1244
1245 if (const ExternalSymbolSDNode *G = dyn_cast<ExternalSymbolSDNode>(Callee))
1246 FuncName = G->getSymbol();
1247 else if (const GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
1248 FuncName = G->getGlobal()->getName();
1249
1250 DiagnosticInfoUnsupported NoCalls(
1251 Fn, Reason + FuncName, CLI.DL.getDebugLoc());
1252 DAG.getContext()->diagnose(NoCalls);
1253
1254 if (!CLI.IsTailCall) {
1255 for (unsigned I = 0, E = CLI.Ins.size(); I != E; ++I)
1256 InVals.push_back(DAG.getUNDEF(CLI.Ins[I].VT));
1257 }
1258
1259 return DAG.getEntryNode();
1260}
1261
1262SDValue AMDGPUTargetLowering::LowerCall(CallLoweringInfo &CLI,
1263 SmallVectorImpl<SDValue> &InVals) const {
1264 return lowerUnhandledCall(CLI, InVals, "unsupported call to function ");
1265}
1266
1267SDValue AMDGPUTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
1268 SelectionDAG &DAG) const {
1269 const Function &Fn = DAG.getMachineFunction().getFunction();
1270
1271 DiagnosticInfoUnsupported NoDynamicAlloca(Fn, "unsupported dynamic alloca",
1272 SDLoc(Op).getDebugLoc());
1273 DAG.getContext()->diagnose(NoDynamicAlloca);
1274 auto Ops = {DAG.getConstant(0, SDLoc(), Op.getValueType()), Op.getOperand(0)};
1275 return DAG.getMergeValues(Ops, SDLoc());
1276}
1277
1278SDValue AMDGPUTargetLowering::LowerOperation(SDValue Op,
1279 SelectionDAG &DAG) const {
1280 switch (Op.getOpcode()) {
1281 default:
1282 Op->print(errs(), &DAG);
1283 llvm_unreachable("Custom lowering code for this "::llvm::llvm_unreachable_internal("Custom lowering code for this "
"instruction is not implemented yet!", "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp"
, 1284)
1284 "instruction is not implemented yet!")::llvm::llvm_unreachable_internal("Custom lowering code for this "
"instruction is not implemented yet!", "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp"
, 1284)
;
1285 break;
1286 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op, DAG);
1287 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
1288 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op, DAG);
1289 case ISD::UDIVREM: return LowerUDIVREM(Op, DAG);
1290 case ISD::SDIVREM: return LowerSDIVREM(Op, DAG);
1291 case ISD::FREM: return LowerFREM(Op, DAG);
1292 case ISD::FCEIL: return LowerFCEIL(Op, DAG);
1293 case ISD::FTRUNC: return LowerFTRUNC(Op, DAG);
1294 case ISD::FRINT: return LowerFRINT(Op, DAG);
1295 case ISD::FNEARBYINT: return LowerFNEARBYINT(Op, DAG);
1296 case ISD::FROUND: return LowerFROUND(Op, DAG);
1297 case ISD::FFLOOR: return LowerFFLOOR(Op, DAG);
1298 case ISD::FLOG:
1299 return LowerFLOG(Op, DAG, numbers::ln2f);
1300 case ISD::FLOG10:
1301 return LowerFLOG(Op, DAG, numbers::ln2f / numbers::ln10f);
1302 case ISD::FEXP:
1303 return lowerFEXP(Op, DAG);
1304 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
1305 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
1306 case ISD::FP_TO_FP16: return LowerFP_TO_FP16(Op, DAG);
1307 case ISD::FP_TO_SINT:
1308 case ISD::FP_TO_UINT:
1309 return LowerFP_TO_INT(Op, DAG);
1310 case ISD::CTTZ:
1311 case ISD::CTTZ_ZERO_UNDEF:
1312 case ISD::CTLZ:
1313 case ISD::CTLZ_ZERO_UNDEF:
1314 return LowerCTLZ_CTTZ(Op, DAG);
1315 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
1316 }
1317 return Op;
1318}
1319
1320void AMDGPUTargetLowering::ReplaceNodeResults(SDNode *N,
1321 SmallVectorImpl<SDValue> &Results,
1322 SelectionDAG &DAG) const {
1323 switch (N->getOpcode()) {
1324 case ISD::SIGN_EXTEND_INREG:
1325 // Different parts of legalization seem to interpret which type of
1326 // sign_extend_inreg is the one to check for custom lowering. The extended
1327 // from type is what really matters, but some places check for custom
1328 // lowering of the result type. This results in trying to use
1329 // ReplaceNodeResults to sext_in_reg to an illegal type, so we'll just do
1330 // nothing here and let the illegal result integer be handled normally.
1331 return;
1332 default:
1333 return;
1334 }
1335}
1336
1337bool AMDGPUTargetLowering::hasDefinedInitializer(const GlobalValue *GV) {
1338 const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV);
1339 if (!GVar || !GVar->hasInitializer())
1340 return false;
1341
1342 return !isa<UndefValue>(GVar->getInitializer());
1343}
1344
1345SDValue AMDGPUTargetLowering::LowerGlobalAddress(AMDGPUMachineFunction* MFI,
1346 SDValue Op,
1347 SelectionDAG &DAG) const {
1348
1349 const DataLayout &DL = DAG.getDataLayout();
1350 GlobalAddressSDNode *G = cast<GlobalAddressSDNode>(Op);
1351 const GlobalValue *GV = G->getGlobal();
1352
1353 if (G->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS ||
1354 G->getAddressSpace() == AMDGPUAS::REGION_ADDRESS) {
1355 if (!MFI->isModuleEntryFunction() &&
1356 !GV->getName().equals("llvm.amdgcn.module.lds")) {
1357 SDLoc DL(Op);
1358 const Function &Fn = DAG.getMachineFunction().getFunction();
1359 DiagnosticInfoUnsupported BadLDSDecl(
1360 Fn, "local memory global used by non-kernel function",
1361 DL.getDebugLoc(), DS_Warning);
1362 DAG.getContext()->diagnose(BadLDSDecl);
1363
1364 // We currently don't have a way to correctly allocate LDS objects that
1365 // aren't directly associated with a kernel. We do force inlining of
1366 // functions that use local objects. However, if these dead functions are
1367 // not eliminated, we don't want a compile time error. Just emit a warning
1368 // and a trap, since there should be no callable path here.
1369 SDValue Trap = DAG.getNode(ISD::TRAP, DL, MVT::Other, DAG.getEntryNode());
1370 SDValue OutputChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
1371 Trap, DAG.getRoot());
1372 DAG.setRoot(OutputChain);
1373 return DAG.getUNDEF(Op.getValueType());
1374 }
1375
1376 // XXX: What does the value of G->getOffset() mean?
1377 assert(G->getOffset() == 0 &&(static_cast <bool> (G->getOffset() == 0 && "Do not know what to do with an non-zero offset"
) ? void (0) : __assert_fail ("G->getOffset() == 0 && \"Do not know what to do with an non-zero offset\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp"
, 1378, __extension__ __PRETTY_FUNCTION__))
1378 "Do not know what to do with an non-zero offset")(static_cast <bool> (G->getOffset() == 0 && "Do not know what to do with an non-zero offset"
) ? void (0) : __assert_fail ("G->getOffset() == 0 && \"Do not know what to do with an non-zero offset\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp"
, 1378, __extension__ __PRETTY_FUNCTION__))
;
1379
1380 // TODO: We could emit code to handle the initialization somewhere.
1381 // We ignore the initializer for now and legalize it to allow selection.
1382 // The initializer will anyway get errored out during assembly emission.
1383 unsigned Offset = MFI->allocateLDSGlobal(DL, *cast<GlobalVariable>(GV));
1384 return DAG.getConstant(Offset, SDLoc(Op), Op.getValueType());
1385 }
1386 return SDValue();
1387}
1388
1389SDValue AMDGPUTargetLowering::LowerCONCAT_VECTORS(SDValue Op,
1390 SelectionDAG &DAG) const {
1391 SmallVector<SDValue, 8> Args;
1392
1393 EVT VT = Op.getValueType();
1394 if (VT == MVT::v4i16 || VT == MVT::v4f16) {
1395 SDLoc SL(Op);
1396 SDValue Lo = DAG.getNode(ISD::BITCAST, SL, MVT::i32, Op.getOperand(0));
1397 SDValue Hi = DAG.getNode(ISD::BITCAST, SL, MVT::i32, Op.getOperand(1));
1398
1399 SDValue BV = DAG.getBuildVector(MVT::v2i32, SL, { Lo, Hi });
1400 return DAG.getNode(ISD::BITCAST, SL, VT, BV);
1401 }
1402
1403 for (const SDUse &U : Op->ops())
1404 DAG.ExtractVectorElements(U.get(), Args);
1405
1406 return DAG.getBuildVector(Op.getValueType(), SDLoc(Op), Args);
1407}
1408
1409SDValue AMDGPUTargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op,
1410 SelectionDAG &DAG) const {
1411
1412 SmallVector<SDValue, 8> Args;
1413 unsigned Start = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
1414 EVT VT = Op.getValueType();
1415 EVT SrcVT = Op.getOperand(0).getValueType();
1416
1417 // For these types, we have some TableGen patterns except if the index is 1
1418 if (((SrcVT == MVT::v4f16 && VT == MVT::v2f16) ||
1419 (SrcVT == MVT::v4i16 && VT == MVT::v2i16)) &&
1420 Start != 1)
1421 return Op;
1422
1423 DAG.ExtractVectorElements(Op.getOperand(0), Args, Start,
1424 VT.getVectorNumElements());
1425
1426 return DAG.getBuildVector(Op.getValueType(), SDLoc(Op), Args);
1427}
1428
1429/// Generate Min/Max node
1430SDValue AMDGPUTargetLowering::combineFMinMaxLegacy(const SDLoc &DL, EVT VT,
1431 SDValue LHS, SDValue RHS,
1432 SDValue True, SDValue False,
1433 SDValue CC,
1434 DAGCombinerInfo &DCI) const {
1435 if (!(LHS == True && RHS == False) && !(LHS == False && RHS == True))
1436 return SDValue();
1437
1438 SelectionDAG &DAG = DCI.DAG;
1439 ISD::CondCode CCOpcode = cast<CondCodeSDNode>(CC)->get();
1440 switch (CCOpcode) {
1441 case ISD::SETOEQ:
1442 case ISD::SETONE:
1443 case ISD::SETUNE:
1444 case ISD::SETNE:
1445 case ISD::SETUEQ:
1446 case ISD::SETEQ:
1447 case ISD::SETFALSE:
1448 case ISD::SETFALSE2:
1449 case ISD::SETTRUE:
1450 case ISD::SETTRUE2:
1451 case ISD::SETUO:
1452 case ISD::SETO:
1453 break;
1454 case ISD::SETULE:
1455 case ISD::SETULT: {
1456 if (LHS == True)
1457 return DAG.getNode(AMDGPUISD::FMIN_LEGACY, DL, VT, RHS, LHS);
1458 return DAG.getNode(AMDGPUISD::FMAX_LEGACY, DL, VT, LHS, RHS);
1459 }
1460 case ISD::SETOLE:
1461 case ISD::SETOLT:
1462 case ISD::SETLE:
1463 case ISD::SETLT: {
1464 // Ordered. Assume ordered for undefined.
1465
1466 // Only do this after legalization to avoid interfering with other combines
1467 // which might occur.
1468 if (DCI.getDAGCombineLevel() < AfterLegalizeDAG &&
1469 !DCI.isCalledByLegalizer())
1470 return SDValue();
1471
1472 // We need to permute the operands to get the correct NaN behavior. The
1473 // selected operand is the second one based on the failing compare with NaN,
1474 // so permute it based on the compare type the hardware uses.
1475 if (LHS == True)
1476 return DAG.getNode(AMDGPUISD::FMIN_LEGACY, DL, VT, LHS, RHS);
1477 return DAG.getNode(AMDGPUISD::FMAX_LEGACY, DL, VT, RHS, LHS);
1478 }
1479 case ISD::SETUGE:
1480 case ISD::SETUGT: {
1481 if (LHS == True)
1482 return DAG.getNode(AMDGPUISD::FMAX_LEGACY, DL, VT, RHS, LHS);
1483 return DAG.getNode(AMDGPUISD::FMIN_LEGACY, DL, VT, LHS, RHS);
1484 }
1485 case ISD::SETGT:
1486 case ISD::SETGE:
1487 case ISD::SETOGE:
1488 case ISD::SETOGT: {
1489 if (DCI.getDAGCombineLevel() < AfterLegalizeDAG &&
1490 !DCI.isCalledByLegalizer())
1491 return SDValue();
1492
1493 if (LHS == True)
1494 return DAG.getNode(AMDGPUISD::FMAX_LEGACY, DL, VT, LHS, RHS);
1495 return DAG.getNode(AMDGPUISD::FMIN_LEGACY, DL, VT, RHS, LHS);
1496 }
1497 case ISD::SETCC_INVALID:
1498 llvm_unreachable("Invalid setcc condcode!")::llvm::llvm_unreachable_internal("Invalid setcc condcode!", "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp"
, 1498)
;
1499 }
1500 return SDValue();
1501}
1502
1503std::pair<SDValue, SDValue>
1504AMDGPUTargetLowering::split64BitValue(SDValue Op, SelectionDAG &DAG) const {
1505 SDLoc SL(Op);
1506
1507 SDValue Vec = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Op);
1508
1509 const SDValue Zero = DAG.getConstant(0, SL, MVT::i32);
1510 const SDValue One = DAG.getConstant(1, SL, MVT::i32);
1511
1512 SDValue Lo = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, Vec, Zero);
1513 SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, Vec, One);
1514
1515 return std::make_pair(Lo, Hi);
1516}
1517
1518SDValue AMDGPUTargetLowering::getLoHalf64(SDValue Op, SelectionDAG &DAG) const {
1519 SDLoc SL(Op);
1520
1521 SDValue Vec = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Op);
1522 const SDValue Zero = DAG.getConstant(0, SL, MVT::i32);
1523 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, Vec, Zero);
1524}
1525
1526SDValue AMDGPUTargetLowering::getHiHalf64(SDValue Op, SelectionDAG &DAG) const {
1527 SDLoc SL(Op);
1528
1529 SDValue Vec = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Op);
1530 const SDValue One = DAG.getConstant(1, SL, MVT::i32);
1531 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, Vec, One);
1532}
1533
1534// Split a vector type into two parts. The first part is a power of two vector.
1535// The second part is whatever is left over, and is a scalar if it would
1536// otherwise be a 1-vector.
1537std::pair<EVT, EVT>
1538AMDGPUTargetLowering::getSplitDestVTs(const EVT &VT, SelectionDAG &DAG) const {
1539 EVT LoVT, HiVT;
1540 EVT EltVT = VT.getVectorElementType();
1541 unsigned NumElts = VT.getVectorNumElements();
1542 unsigned LoNumElts = PowerOf2Ceil((NumElts + 1) / 2);
1543 LoVT = EVT::getVectorVT(*DAG.getContext(), EltVT, LoNumElts);
1544 HiVT = NumElts - LoNumElts == 1
1545 ? EltVT
1546 : EVT::getVectorVT(*DAG.getContext(), EltVT, NumElts - LoNumElts);
1547 return std::make_pair(LoVT, HiVT);
1548}
1549
1550// Split a vector value into two parts of types LoVT and HiVT. HiVT could be
1551// scalar.
1552std::pair<SDValue, SDValue>
1553AMDGPUTargetLowering::splitVector(const SDValue &N, const SDLoc &DL,
1554 const EVT &LoVT, const EVT &HiVT,
1555 SelectionDAG &DAG) const {
1556 assert(LoVT.getVectorNumElements() +(static_cast <bool> (LoVT.getVectorNumElements() + (HiVT
.isVector() ? HiVT.getVectorNumElements() : 1) <= N.getValueType
().getVectorNumElements() && "More vector elements requested than available!"
) ? void (0) : __assert_fail ("LoVT.getVectorNumElements() + (HiVT.isVector() ? HiVT.getVectorNumElements() : 1) <= N.getValueType().getVectorNumElements() && \"More vector elements requested than available!\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp"
, 1559, __extension__ __PRETTY_FUNCTION__))
1557 (HiVT.isVector() ? HiVT.getVectorNumElements() : 1) <=(static_cast <bool> (LoVT.getVectorNumElements() + (HiVT
.isVector() ? HiVT.getVectorNumElements() : 1) <= N.getValueType
().getVectorNumElements() && "More vector elements requested than available!"
) ? void (0) : __assert_fail ("LoVT.getVectorNumElements() + (HiVT.isVector() ? HiVT.getVectorNumElements() : 1) <= N.getValueType().getVectorNumElements() && \"More vector elements requested than available!\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp"
, 1559, __extension__ __PRETTY_FUNCTION__))
1558 N.getValueType().getVectorNumElements() &&(static_cast <bool> (LoVT.getVectorNumElements() + (HiVT
.isVector() ? HiVT.getVectorNumElements() : 1) <= N.getValueType
().getVectorNumElements() && "More vector elements requested than available!"
) ? void (0) : __assert_fail ("LoVT.getVectorNumElements() + (HiVT.isVector() ? HiVT.getVectorNumElements() : 1) <= N.getValueType().getVectorNumElements() && \"More vector elements requested than available!\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp"
, 1559, __extension__ __PRETTY_FUNCTION__))
1559 "More vector elements requested than available!")(static_cast <bool> (LoVT.getVectorNumElements() + (HiVT
.isVector() ? HiVT.getVectorNumElements() : 1) <= N.getValueType
().getVectorNumElements() && "More vector elements requested than available!"
) ? void (0) : __assert_fail ("LoVT.getVectorNumElements() + (HiVT.isVector() ? HiVT.getVectorNumElements() : 1) <= N.getValueType().getVectorNumElements() && \"More vector elements requested than available!\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp"
, 1559, __extension__ __PRETTY_FUNCTION__))
;
1560 SDValue Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, LoVT, N,
1561 DAG.getVectorIdxConstant(0, DL));
1562 SDValue Hi = DAG.getNode(
1563 HiVT.isVector() ? ISD::EXTRACT_SUBVECTOR : ISD::EXTRACT_VECTOR_ELT, DL,
1564 HiVT, N, DAG.getVectorIdxConstant(LoVT.getVectorNumElements(), DL));
1565 return std::make_pair(Lo, Hi);
1566}
1567
1568SDValue AMDGPUTargetLowering::SplitVectorLoad(const SDValue Op,
1569 SelectionDAG &DAG) const {
1570 LoadSDNode *Load = cast<LoadSDNode>(Op);
1571 EVT VT = Op.getValueType();
1572 SDLoc SL(Op);
1573
1574
1575 // If this is a 2 element vector, we really want to scalarize and not create
1576 // weird 1 element vectors.
1577 if (VT.getVectorNumElements() == 2) {
1578 SDValue Ops[2];
1579 std::tie(Ops[0], Ops[1]) = scalarizeVectorLoad(Load, DAG);
1580 return DAG.getMergeValues(Ops, SL);
1581 }
1582
1583 SDValue BasePtr = Load->getBasePtr();
1584 EVT MemVT = Load->getMemoryVT();
1585
1586 const MachinePointerInfo &SrcValue = Load->getMemOperand()->getPointerInfo();
1587
1588 EVT LoVT, HiVT;
1589 EVT LoMemVT, HiMemVT;
1590 SDValue Lo, Hi;
1591
1592 std::tie(LoVT, HiVT) = getSplitDestVTs(VT, DAG);
1593 std::tie(LoMemVT, HiMemVT) = getSplitDestVTs(MemVT, DAG);
1594 std::tie(Lo, Hi) = splitVector(Op, SL, LoVT, HiVT, DAG);
1595
1596 unsigned Size = LoMemVT.getStoreSize();
1597 unsigned BaseAlign = Load->getAlignment();
1598 unsigned HiAlign = MinAlign(BaseAlign, Size);
1599
1600 SDValue LoLoad = DAG.getExtLoad(Load->getExtensionType(), SL, LoVT,
1601 Load->getChain(), BasePtr, SrcValue, LoMemVT,
1602 BaseAlign, Load->getMemOperand()->getFlags());
1603 SDValue HiPtr = DAG.getObjectPtrOffset(SL, BasePtr, TypeSize::Fixed(Size));
1604 SDValue HiLoad =
1605 DAG.getExtLoad(Load->getExtensionType(), SL, HiVT, Load->getChain(),
1606 HiPtr, SrcValue.getWithOffset(LoMemVT.getStoreSize()),
1607 HiMemVT, HiAlign, Load->getMemOperand()->getFlags());
1608
1609 SDValue Join;
1610 if (LoVT == HiVT) {
1611 // This is the case that the vector is power of two so was evenly split.
1612 Join = DAG.getNode(ISD::CONCAT_VECTORS, SL, VT, LoLoad, HiLoad);
1613 } else {
1614 Join = DAG.getNode(ISD::INSERT_SUBVECTOR, SL, VT, DAG.getUNDEF(VT), LoLoad,
1615 DAG.getVectorIdxConstant(0, SL));
1616 Join = DAG.getNode(
1617 HiVT.isVector() ? ISD::INSERT_SUBVECTOR : ISD::INSERT_VECTOR_ELT, SL,
1618 VT, Join, HiLoad,
1619 DAG.getVectorIdxConstant(LoVT.getVectorNumElements(), SL));
1620 }
1621
1622 SDValue Ops[] = {Join, DAG.getNode(ISD::TokenFactor, SL, MVT::Other,
1623 LoLoad.getValue(1), HiLoad.getValue(1))};
1624
1625 return DAG.getMergeValues(Ops, SL);
1626}
1627
1628SDValue AMDGPUTargetLowering::WidenOrSplitVectorLoad(SDValue Op,
1629 SelectionDAG &DAG) const {
1630 LoadSDNode *Load = cast<LoadSDNode>(Op);
1631 EVT VT = Op.getValueType();
1632 SDValue BasePtr = Load->getBasePtr();
1633 EVT MemVT = Load->getMemoryVT();
1634 SDLoc SL(Op);
1635 const MachinePointerInfo &SrcValue = Load->getMemOperand()->getPointerInfo();
1636 unsigned BaseAlign = Load->getAlignment();
1637 unsigned NumElements = MemVT.getVectorNumElements();
1638
1639 // Widen from vec3 to vec4 when the load is at least 8-byte aligned
1640 // or 16-byte fully dereferenceable. Otherwise, split the vector load.
1641 if (NumElements != 3 ||
1642 (BaseAlign < 8 &&
1643 !SrcValue.isDereferenceable(16, *DAG.getContext(), DAG.getDataLayout())))
1644 return SplitVectorLoad(Op, DAG);
1645
1646 assert(NumElements == 3)(static_cast <bool> (NumElements == 3) ? void (0) : __assert_fail
("NumElements == 3", "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp"
, 1646, __extension__ __PRETTY_FUNCTION__))
;
1647
1648 EVT WideVT =
1649 EVT::getVectorVT(*DAG.getContext(), VT.getVectorElementType(), 4);
1650 EVT WideMemVT =
1651 EVT::getVectorVT(*DAG.getContext(), MemVT.getVectorElementType(), 4);
1652 SDValue WideLoad = DAG.getExtLoad(
1653 Load->getExtensionType(), SL, WideVT, Load->getChain(), BasePtr, SrcValue,
1654 WideMemVT, BaseAlign, Load->getMemOperand()->getFlags());
1655 return DAG.getMergeValues(
1656 {DAG.getNode(ISD::EXTRACT_SUBVECTOR, SL, VT, WideLoad,
1657 DAG.getVectorIdxConstant(0, SL)),
1658 WideLoad.getValue(1)},
1659 SL);
1660}
1661
1662SDValue AMDGPUTargetLowering::SplitVectorStore(SDValue Op,
1663 SelectionDAG &DAG) const {
1664 StoreSDNode *Store = cast<StoreSDNode>(Op);
1665 SDValue Val = Store->getValue();
1666 EVT VT = Val.getValueType();
1667
1668 // If this is a 2 element vector, we really want to scalarize and not create
1669 // weird 1 element vectors.
1670 if (VT.getVectorNumElements() == 2)
1671 return scalarizeVectorStore(Store, DAG);
1672
1673 EVT MemVT = Store->getMemoryVT();
1674 SDValue Chain = Store->getChain();
1675 SDValue BasePtr = Store->getBasePtr();
1676 SDLoc SL(Op);
1677
1678 EVT LoVT, HiVT;
1679 EVT LoMemVT, HiMemVT;
1680 SDValue Lo, Hi;
1681
1682 std::tie(LoVT, HiVT) = getSplitDestVTs(VT, DAG);
1683 std::tie(LoMemVT, HiMemVT) = getSplitDestVTs(MemVT, DAG);
1684 std::tie(Lo, Hi) = splitVector(Val, SL, LoVT, HiVT, DAG);
1685
1686 SDValue HiPtr = DAG.getObjectPtrOffset(SL, BasePtr, LoMemVT.getStoreSize());
1687
1688 const MachinePointerInfo &SrcValue = Store->getMemOperand()->getPointerInfo();
1689 unsigned BaseAlign = Store->getAlignment();
1690 unsigned Size = LoMemVT.getStoreSize();
1691 unsigned HiAlign = MinAlign(BaseAlign, Size);
1692
1693 SDValue LoStore =
1694 DAG.getTruncStore(Chain, SL, Lo, BasePtr, SrcValue, LoMemVT, BaseAlign,
1695 Store->getMemOperand()->getFlags());
1696 SDValue HiStore =
1697 DAG.getTruncStore(Chain, SL, Hi, HiPtr, SrcValue.getWithOffset(Size),
1698 HiMemVT, HiAlign, Store->getMemOperand()->getFlags());
1699
1700 return DAG.getNode(ISD::TokenFactor, SL, MVT::Other, LoStore, HiStore);
1701}
1702
1703// This is a shortcut for integer division because we have fast i32<->f32
1704// conversions, and fast f32 reciprocal instructions. The fractional part of a
1705// float is enough to accurately represent up to a 24-bit signed integer.
1706SDValue AMDGPUTargetLowering::LowerDIVREM24(SDValue Op, SelectionDAG &DAG,
1707 bool Sign) const {
1708 SDLoc DL(Op);
1709 EVT VT = Op.getValueType();
1710 SDValue LHS = Op.getOperand(0);
1711 SDValue RHS = Op.getOperand(1);
1712 MVT IntVT = MVT::i32;
1713 MVT FltVT = MVT::f32;
1714
1715 unsigned LHSSignBits = DAG.ComputeNumSignBits(LHS);
1716 if (LHSSignBits < 9)
1717 return SDValue();
1718
1719 unsigned RHSSignBits = DAG.ComputeNumSignBits(RHS);
1720 if (RHSSignBits < 9)
1721 return SDValue();
1722
1723 unsigned BitSize = VT.getSizeInBits();
1724 unsigned SignBits = std::min(LHSSignBits, RHSSignBits);
1725 unsigned DivBits = BitSize - SignBits;
1726 if (Sign)
1727 ++DivBits;
1728
1729 ISD::NodeType ToFp = Sign ? ISD::SINT_TO_FP : ISD::UINT_TO_FP;
1730 ISD::NodeType ToInt = Sign ? ISD::FP_TO_SINT : ISD::FP_TO_UINT;
1731
1732 SDValue jq = DAG.getConstant(1, DL, IntVT);
1733
1734 if (Sign) {
1735 // char|short jq = ia ^ ib;
1736 jq = DAG.getNode(ISD::XOR, DL, VT, LHS, RHS);
1737
1738 // jq = jq >> (bitsize - 2)
1739 jq = DAG.getNode(ISD::SRA, DL, VT, jq,
1740 DAG.getConstant(BitSize - 2, DL, VT));
1741
1742 // jq = jq | 0x1
1743 jq = DAG.getNode(ISD::OR, DL, VT, jq, DAG.getConstant(1, DL, VT));
1744 }
1745
1746 // int ia = (int)LHS;
1747 SDValue ia = LHS;
1748
1749 // int ib, (int)RHS;
1750 SDValue ib = RHS;
1751
1752 // float fa = (float)ia;
1753 SDValue fa = DAG.getNode(ToFp, DL, FltVT, ia);
1754
1755 // float fb = (float)ib;
1756 SDValue fb = DAG.getNode(ToFp, DL, FltVT, ib);
1757
1758 SDValue fq = DAG.getNode(ISD::FMUL, DL, FltVT,
1759 fa, DAG.getNode(AMDGPUISD::RCP, DL, FltVT, fb));
1760
1761 // fq = trunc(fq);
1762 fq = DAG.getNode(ISD::FTRUNC, DL, FltVT, fq);
1763
1764 // float fqneg = -fq;
1765 SDValue fqneg = DAG.getNode(ISD::FNEG, DL, FltVT, fq);
1766
1767 MachineFunction &MF = DAG.getMachineFunction();
1768 const AMDGPUMachineFunction *MFI = MF.getInfo<AMDGPUMachineFunction>();
1769
1770 // float fr = mad(fqneg, fb, fa);
1771 unsigned OpCode = !Subtarget->hasMadMacF32Insts() ?
1772 (unsigned)ISD::FMA :
1773 !MFI->getMode().allFP32Denormals() ?
1774 (unsigned)ISD::FMAD :
1775 (unsigned)AMDGPUISD::FMAD_FTZ;
1776 SDValue fr = DAG.getNode(OpCode, DL, FltVT, fqneg, fb, fa);
1777
1778 // int iq = (int)fq;
1779 SDValue iq = DAG.getNode(ToInt, DL, IntVT, fq);
1780
1781 // fr = fabs(fr);
1782 fr = DAG.getNode(ISD::FABS, DL, FltVT, fr);
1783
1784 // fb = fabs(fb);
1785 fb = DAG.getNode(ISD::FABS, DL, FltVT, fb);
1786
1787 EVT SetCCVT = getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT);
1788
1789 // int cv = fr >= fb;
1790 SDValue cv = DAG.getSetCC(DL, SetCCVT, fr, fb, ISD::SETOGE);
1791
1792 // jq = (cv ? jq : 0);
1793 jq = DAG.getNode(ISD::SELECT, DL, VT, cv, jq, DAG.getConstant(0, DL, VT));
1794
1795 // dst = iq + jq;
1796 SDValue Div = DAG.getNode(ISD::ADD, DL, VT, iq, jq);
1797
1798 // Rem needs compensation, it's easier to recompute it
1799 SDValue Rem = DAG.getNode(ISD::MUL, DL, VT, Div, RHS);
1800 Rem = DAG.getNode(ISD::SUB, DL, VT, LHS, Rem);
1801
1802 // Truncate to number of bits this divide really is.
1803 if (Sign) {
1804 SDValue InRegSize
1805 = DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(), DivBits));
1806 Div = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT, Div, InRegSize);
1807 Rem = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT, Rem, InRegSize);
1808 } else {
1809 SDValue TruncMask = DAG.getConstant((UINT64_C(1)1UL << DivBits) - 1, DL, VT);
1810 Div = DAG.getNode(ISD::AND, DL, VT, Div, TruncMask);
1811 Rem = DAG.getNode(ISD::AND, DL, VT, Rem, TruncMask);
1812 }
1813
1814 return DAG.getMergeValues({ Div, Rem }, DL);
1815}
1816
1817void AMDGPUTargetLowering::LowerUDIVREM64(SDValue Op,
1818 SelectionDAG &DAG,
1819 SmallVectorImpl<SDValue> &Results) const {
1820 SDLoc DL(Op);
1821 EVT VT = Op.getValueType();
1822
1823 assert(VT == MVT::i64 && "LowerUDIVREM64 expects an i64")(static_cast <bool> (VT == MVT::i64 && "LowerUDIVREM64 expects an i64"
) ? void (0) : __assert_fail ("VT == MVT::i64 && \"LowerUDIVREM64 expects an i64\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp"
, 1823, __extension__ __PRETTY_FUNCTION__))
;
1824
1825 EVT HalfVT = VT.getHalfSizedIntegerVT(*DAG.getContext());
1826
1827 SDValue One = DAG.getConstant(1, DL, HalfVT);
1828 SDValue Zero = DAG.getConstant(0, DL, HalfVT);
1829
1830 //HiLo split
1831 SDValue LHS = Op.getOperand(0);
1832 SDValue LHS_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, LHS, Zero);
1833 SDValue LHS_Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, LHS, One);
1834
1835 SDValue RHS = Op.getOperand(1);
1836 SDValue RHS_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, RHS, Zero);
1837 SDValue RHS_Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, RHS, One);
1838
1839 if (DAG.MaskedValueIsZero(RHS, APInt::getHighBitsSet(64, 32)) &&
1840 DAG.MaskedValueIsZero(LHS, APInt::getHighBitsSet(64, 32))) {
1841
1842 SDValue Res = DAG.getNode(ISD::UDIVREM, DL, DAG.getVTList(HalfVT, HalfVT),
1843 LHS_Lo, RHS_Lo);
1844
1845 SDValue DIV = DAG.getBuildVector(MVT::v2i32, DL, {Res.getValue(0), Zero});
1846 SDValue REM = DAG.getBuildVector(MVT::v2i32, DL, {Res.getValue(1), Zero});
1847
1848 Results.push_back(DAG.getNode(ISD::BITCAST, DL, MVT::i64, DIV));
1849 Results.push_back(DAG.getNode(ISD::BITCAST, DL, MVT::i64, REM));
1850 return;
1851 }
1852
1853 if (isTypeLegal(MVT::i64)) {
1854 MachineFunction &MF = DAG.getMachineFunction();
1855 const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
1856
1857 // Compute denominator reciprocal.
1858 unsigned FMAD = !Subtarget->hasMadMacF32Insts() ?
1859 (unsigned)ISD::FMA :
1860 !MFI->getMode().allFP32Denormals() ?
1861 (unsigned)ISD::FMAD :
1862 (unsigned)AMDGPUISD::FMAD_FTZ;
1863
1864 SDValue Cvt_Lo = DAG.getNode(ISD::UINT_TO_FP, DL, MVT::f32, RHS_Lo);
1865 SDValue Cvt_Hi = DAG.getNode(ISD::UINT_TO_FP, DL, MVT::f32, RHS_Hi);
1866 SDValue Mad1 = DAG.getNode(FMAD, DL, MVT::f32, Cvt_Hi,
1867 DAG.getConstantFP(APInt(32, 0x4f800000).bitsToFloat(), DL, MVT::f32),
1868 Cvt_Lo);
1869 SDValue Rcp = DAG.getNode(AMDGPUISD::RCP, DL, MVT::f32, Mad1);
1870 SDValue Mul1 = DAG.getNode(ISD::FMUL, DL, MVT::f32, Rcp,
1871 DAG.getConstantFP(APInt(32, 0x5f7ffffc).bitsToFloat(), DL, MVT::f32));
1872 SDValue Mul2 = DAG.getNode(ISD::FMUL, DL, MVT::f32, Mul1,
1873 DAG.getConstantFP(APInt(32, 0x2f800000).bitsToFloat(), DL, MVT::f32));
1874 SDValue Trunc = DAG.getNode(ISD::FTRUNC, DL, MVT::f32, Mul2);
1875 SDValue Mad2 = DAG.getNode(FMAD, DL, MVT::f32, Trunc,
1876 DAG.getConstantFP(APInt(32, 0xcf800000).bitsToFloat(), DL, MVT::f32),
1877 Mul1);
1878 SDValue Rcp_Lo = DAG.getNode(ISD::FP_TO_UINT, DL, HalfVT, Mad2);
1879 SDValue Rcp_Hi = DAG.getNode(ISD::FP_TO_UINT, DL, HalfVT, Trunc);
1880 SDValue Rcp64 = DAG.getBitcast(VT,
1881 DAG.getBuildVector(MVT::v2i32, DL, {Rcp_Lo, Rcp_Hi}));
1882
1883 SDValue Zero64 = DAG.getConstant(0, DL, VT);
1884 SDValue One64 = DAG.getConstant(1, DL, VT);
1885 SDValue Zero1 = DAG.getConstant(0, DL, MVT::i1);
1886 SDVTList HalfCarryVT = DAG.getVTList(HalfVT, MVT::i1);
1887
1888 SDValue Neg_RHS = DAG.getNode(ISD::SUB, DL, VT, Zero64, RHS);
1889 SDValue Mullo1 = DAG.getNode(ISD::MUL, DL, VT, Neg_RHS, Rcp64);
1890 SDValue Mulhi1 = DAG.getNode(ISD::MULHU, DL, VT, Rcp64, Mullo1);
1891 SDValue Mulhi1_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, Mulhi1,
1892 Zero);
1893 SDValue Mulhi1_Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, Mulhi1,
1894 One);
1895
1896 SDValue Add1_Lo = DAG.getNode(ISD::ADDCARRY, DL, HalfCarryVT, Rcp_Lo,
1897 Mulhi1_Lo, Zero1);
1898 SDValue Add1_Hi = DAG.getNode(ISD::ADDCARRY, DL, HalfCarryVT, Rcp_Hi,
1899 Mulhi1_Hi, Add1_Lo.getValue(1));
1900 SDValue Add1_HiNc = DAG.getNode(ISD::ADD, DL, HalfVT, Rcp_Hi, Mulhi1_Hi);
1901 SDValue Add1 = DAG.getBitcast(VT,
1902 DAG.getBuildVector(MVT::v2i32, DL, {Add1_Lo, Add1_Hi}));
1903
1904 SDValue Mullo2 = DAG.getNode(ISD::MUL, DL, VT, Neg_RHS, Add1);
1905 SDValue Mulhi2 = DAG.getNode(ISD::MULHU, DL, VT, Add1, Mullo2);
1906 SDValue Mulhi2_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, Mulhi2,
1907 Zero);
1908 SDValue Mulhi2_Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, Mulhi2,
1909 One);
1910
1911 SDValue Add2_Lo = DAG.getNode(ISD::ADDCARRY, DL, HalfCarryVT, Add1_Lo,
1912 Mulhi2_Lo, Zero1);
1913 SDValue Add2_HiC = DAG.getNode(ISD::ADDCARRY, DL, HalfCarryVT, Add1_HiNc,
1914 Mulhi2_Hi, Add1_Lo.getValue(1));
1915 SDValue Add2_Hi = DAG.getNode(ISD::ADDCARRY, DL, HalfCarryVT, Add2_HiC,
1916 Zero, Add2_Lo.getValue(1));
1917 SDValue Add2 = DAG.getBitcast(VT,
1918 DAG.getBuildVector(MVT::v2i32, DL, {Add2_Lo, Add2_Hi}));
1919 SDValue Mulhi3 = DAG.getNode(ISD::MULHU, DL, VT, LHS, Add2);
1920
1921 SDValue Mul3 = DAG.getNode(ISD::MUL, DL, VT, RHS, Mulhi3);
1922
1923 SDValue Mul3_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, Mul3, Zero);
1924 SDValue Mul3_Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, Mul3, One);
1925 SDValue Sub1_Lo = DAG.getNode(ISD::SUBCARRY, DL, HalfCarryVT, LHS_Lo,
1926 Mul3_Lo, Zero1);
1927 SDValue Sub1_Hi = DAG.getNode(ISD::SUBCARRY, DL, HalfCarryVT, LHS_Hi,
1928 Mul3_Hi, Sub1_Lo.getValue(1));
1929 SDValue Sub1_Mi = DAG.getNode(ISD::SUB, DL, HalfVT, LHS_Hi, Mul3_Hi);
1930 SDValue Sub1 = DAG.getBitcast(VT,
1931 DAG.getBuildVector(MVT::v2i32, DL, {Sub1_Lo, Sub1_Hi}));
1932
1933 SDValue MinusOne = DAG.getConstant(0xffffffffu, DL, HalfVT);
1934 SDValue C1 = DAG.getSelectCC(DL, Sub1_Hi, RHS_Hi, MinusOne, Zero,
1935 ISD::SETUGE);
1936 SDValue C2 = DAG.getSelectCC(DL, Sub1_Lo, RHS_Lo, MinusOne, Zero,
1937 ISD::SETUGE);
1938 SDValue C3 = DAG.getSelectCC(DL, Sub1_Hi, RHS_Hi, C2, C1, ISD::SETEQ);
1939
1940 // TODO: Here and below portions of the code can be enclosed into if/endif.
1941 // Currently control flow is unconditional and we have 4 selects after
1942 // potential endif to substitute PHIs.
1943
1944 // if C3 != 0 ...
1945 SDValue Sub2_Lo = DAG.getNode(ISD::SUBCARRY, DL, HalfCarryVT, Sub1_Lo,
1946 RHS_Lo, Zero1);
1947 SDValue Sub2_Mi = DAG.getNode(ISD::SUBCARRY, DL, HalfCarryVT, Sub1_Mi,
1948 RHS_Hi, Sub1_Lo.getValue(1));
1949 SDValue Sub2_Hi = DAG.getNode(ISD::SUBCARRY, DL, HalfCarryVT, Sub2_Mi,
1950 Zero, Sub2_Lo.getValue(1));
1951 SDValue Sub2 = DAG.getBitcast(VT,
1952 DAG.getBuildVector(MVT::v2i32, DL, {Sub2_Lo, Sub2_Hi}));
1953
1954 SDValue Add3 = DAG.getNode(ISD::ADD, DL, VT, Mulhi3, One64);
1955
1956 SDValue C4 = DAG.getSelectCC(DL, Sub2_Hi, RHS_Hi, MinusOne, Zero,
1957 ISD::SETUGE);
1958 SDValue C5 = DAG.getSelectCC(DL, Sub2_Lo, RHS_Lo, MinusOne, Zero,
1959 ISD::SETUGE);
1960 SDValue C6 = DAG.getSelectCC(DL, Sub2_Hi, RHS_Hi, C5, C4, ISD::SETEQ);
1961
1962 // if (C6 != 0)
1963 SDValue Add4 = DAG.getNode(ISD::ADD, DL, VT, Add3, One64);
1964
1965 SDValue Sub3_Lo = DAG.getNode(ISD::SUBCARRY, DL, HalfCarryVT, Sub2_Lo,
1966 RHS_Lo, Zero1);
1967 SDValue Sub3_Mi = DAG.getNode(ISD::SUBCARRY, DL, HalfCarryVT, Sub2_Mi,
1968 RHS_Hi, Sub2_Lo.getValue(1));
1969 SDValue Sub3_Hi = DAG.getNode(ISD::SUBCARRY, DL, HalfCarryVT, Sub3_Mi,
1970 Zero, Sub3_Lo.getValue(1));
1971 SDValue Sub3 = DAG.getBitcast(VT,
1972 DAG.getBuildVector(MVT::v2i32, DL, {Sub3_Lo, Sub3_Hi}));
1973
1974 // endif C6
1975 // endif C3
1976
1977 SDValue Sel1 = DAG.getSelectCC(DL, C6, Zero, Add4, Add3, ISD::SETNE);
1978 SDValue Div = DAG.getSelectCC(DL, C3, Zero, Sel1, Mulhi3, ISD::SETNE);
1979
1980 SDValue Sel2 = DAG.getSelectCC(DL, C6, Zero, Sub3, Sub2, ISD::SETNE);
1981 SDValue Rem = DAG.getSelectCC(DL, C3, Zero, Sel2, Sub1, ISD::SETNE);
1982
1983 Results.push_back(Div);
1984 Results.push_back(Rem);
1985
1986 return;
1987 }
1988
1989 // r600 expandion.
1990 // Get Speculative values
1991 SDValue DIV_Part = DAG.getNode(ISD::UDIV, DL, HalfVT, LHS_Hi, RHS_Lo);
1992 SDValue REM_Part = DAG.getNode(ISD::UREM, DL, HalfVT, LHS_Hi, RHS_Lo);
1993
1994 SDValue REM_Lo = DAG.getSelectCC(DL, RHS_Hi, Zero, REM_Part, LHS_Hi, ISD::SETEQ);
1995 SDValue REM = DAG.getBuildVector(MVT::v2i32, DL, {REM_Lo, Zero});
1996 REM = DAG.getNode(ISD::BITCAST, DL, MVT::i64, REM);
1997
1998 SDValue DIV_Hi = DAG.getSelectCC(DL, RHS_Hi, Zero, DIV_Part, Zero, ISD::SETEQ);
1999 SDValue DIV_Lo = Zero;
2000
2001 const unsigned halfBitWidth = HalfVT.getSizeInBits();
2002
2003 for (unsigned i = 0; i < halfBitWidth; ++i) {
2004 const unsigned bitPos = halfBitWidth - i - 1;
2005 SDValue POS = DAG.getConstant(bitPos, DL, HalfVT);
2006 // Get value of high bit
2007 SDValue HBit = DAG.getNode(ISD::SRL, DL, HalfVT, LHS_Lo, POS);
2008 HBit = DAG.getNode(ISD::AND, DL, HalfVT, HBit, One);
2009 HBit = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, HBit);
2010
2011 // Shift
2012 REM = DAG.getNode(ISD::SHL, DL, VT, REM, DAG.getConstant(1, DL, VT));
2013 // Add LHS high bit
2014 REM = DAG.getNode(ISD::OR, DL, VT, REM, HBit);
2015
2016 SDValue BIT = DAG.getConstant(1ULL << bitPos, DL, HalfVT);
2017 SDValue realBIT = DAG.getSelectCC(DL, REM, RHS, BIT, Zero, ISD::SETUGE);
2018
2019 DIV_Lo = DAG.getNode(ISD::OR, DL, HalfVT, DIV_Lo, realBIT);
2020
2021 // Update REM
2022 SDValue REM_sub = DAG.getNode(ISD::SUB, DL, VT, REM, RHS);
2023 REM = DAG.getSelectCC(DL, REM, RHS, REM_sub, REM, ISD::SETUGE);
2024 }
2025
2026 SDValue DIV = DAG.getBuildVector(MVT::v2i32, DL, {DIV_Lo, DIV_Hi});
2027 DIV = DAG.getNode(ISD::BITCAST, DL, MVT::i64, DIV);
2028 Results.push_back(DIV);
2029 Results.push_back(REM);
2030}
2031
2032SDValue AMDGPUTargetLowering::LowerUDIVREM(SDValue Op,
2033 SelectionDAG &DAG) const {
2034 SDLoc DL(Op);
2035 EVT VT = Op.getValueType();
2036
2037 if (VT == MVT::i64) {
2038 SmallVector<SDValue, 2> Results;
2039 LowerUDIVREM64(Op, DAG, Results);
2040 return DAG.getMergeValues(Results, DL);
2041 }
2042
2043 if (VT == MVT::i32) {
2044 if (SDValue Res = LowerDIVREM24(Op, DAG, false))
2045 return Res;
2046 }
2047
2048 SDValue X = Op.getOperand(0);
2049 SDValue Y = Op.getOperand(1);
2050
2051 // See AMDGPUCodeGenPrepare::expandDivRem32 for a description of the
2052 // algorithm used here.
2053
2054 // Initial estimate of inv(y).
2055 SDValue Z = DAG.getNode(AMDGPUISD::URECIP, DL, VT, Y);
2056
2057 // One round of UNR.
2058 SDValue NegY = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT), Y);
2059 SDValue NegYZ = DAG.getNode(ISD::MUL, DL, VT, NegY, Z);
2060 Z = DAG.getNode(ISD::ADD, DL, VT, Z,
2061 DAG.getNode(ISD::MULHU, DL, VT, Z, NegYZ));
2062
2063 // Quotient/remainder estimate.
2064 SDValue Q = DAG.getNode(ISD::MULHU, DL, VT, X, Z);
2065 SDValue R =
2066 DAG.getNode(ISD::SUB, DL, VT, X, DAG.getNode(ISD::MUL, DL, VT, Q, Y));
2067
2068 // First quotient/remainder refinement.
2069 EVT CCVT = getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT);
2070 SDValue One = DAG.getConstant(1, DL, VT);
2071 SDValue Cond = DAG.getSetCC(DL, CCVT, R, Y, ISD::SETUGE);
2072 Q = DAG.getNode(ISD::SELECT, DL, VT, Cond,
2073 DAG.getNode(ISD::ADD, DL, VT, Q, One), Q);
2074 R = DAG.getNode(ISD::SELECT, DL, VT, Cond,
2075 DAG.getNode(ISD::SUB, DL, VT, R, Y), R);
2076
2077 // Second quotient/remainder refinement.
2078 Cond = DAG.getSetCC(DL, CCVT, R, Y, ISD::SETUGE);
2079 Q = DAG.getNode(ISD::SELECT, DL, VT, Cond,
2080 DAG.getNode(ISD::ADD, DL, VT, Q, One), Q);
2081 R = DAG.getNode(ISD::SELECT, DL, VT, Cond,
2082 DAG.getNode(ISD::SUB, DL, VT, R, Y), R);
2083
2084 return DAG.getMergeValues({Q, R}, DL);
2085}
2086
2087SDValue AMDGPUTargetLowering::LowerSDIVREM(SDValue Op,
2088 SelectionDAG &DAG) const {
2089 SDLoc DL(Op);
2090 EVT VT = Op.getValueType();
2091
2092 SDValue LHS = Op.getOperand(0);
2093 SDValue RHS = Op.getOperand(1);
2094
2095 SDValue Zero = DAG.getConstant(0, DL, VT);
2096 SDValue NegOne = DAG.getConstant(-1, DL, VT);
2097
2098 if (VT == MVT::i32) {
2099 if (SDValue Res = LowerDIVREM24(Op, DAG, true))
2100 return Res;
2101 }
2102
2103 if (VT == MVT::i64 &&
2104 DAG.ComputeNumSignBits(LHS) > 32 &&
2105 DAG.ComputeNumSignBits(RHS) > 32) {
2106 EVT HalfVT = VT.getHalfSizedIntegerVT(*DAG.getContext());
2107
2108 //HiLo split
2109 SDValue LHS_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, LHS, Zero);
2110 SDValue RHS_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, RHS, Zero);
2111 SDValue DIVREM = DAG.getNode(ISD::SDIVREM, DL, DAG.getVTList(HalfVT, HalfVT),
2112 LHS_Lo, RHS_Lo);
2113 SDValue Res[2] = {
2114 DAG.getNode(ISD::SIGN_EXTEND, DL, VT, DIVREM.getValue(0)),
2115 DAG.getNode(ISD::SIGN_EXTEND, DL, VT, DIVREM.getValue(1))
2116 };
2117 return DAG.getMergeValues(Res, DL);
2118 }
2119
2120 SDValue LHSign = DAG.getSelectCC(DL, LHS, Zero, NegOne, Zero, ISD::SETLT);
2121 SDValue RHSign = DAG.getSelectCC(DL, RHS, Zero, NegOne, Zero, ISD::SETLT);
2122 SDValue DSign = DAG.getNode(ISD::XOR, DL, VT, LHSign, RHSign);
2123 SDValue RSign = LHSign; // Remainder sign is the same as LHS
2124
2125 LHS = DAG.getNode(ISD::ADD, DL, VT, LHS, LHSign);
2126 RHS = DAG.getNode(ISD::ADD, DL, VT, RHS, RHSign);
2127
2128 LHS = DAG.getNode(ISD::XOR, DL, VT, LHS, LHSign);
2129 RHS = DAG.getNode(ISD::XOR, DL, VT, RHS, RHSign);
2130
2131 SDValue Div = DAG.getNode(ISD::UDIVREM, DL, DAG.getVTList(VT, VT), LHS, RHS);
2132 SDValue Rem = Div.getValue(1);
2133
2134 Div = DAG.getNode(ISD::XOR, DL, VT, Div, DSign);
2135 Rem = DAG.getNode(ISD::XOR, DL, VT, Rem, RSign);
2136
2137 Div = DAG.getNode(ISD::SUB, DL, VT, Div, DSign);
2138 Rem = DAG.getNode(ISD::SUB, DL, VT, Rem, RSign);
2139
2140 SDValue Res[2] = {
2141 Div,
2142 Rem
2143 };
2144 return DAG.getMergeValues(Res, DL);
2145}
2146
2147// (frem x, y) -> (fma (fneg (ftrunc (fdiv x, y))), y, x)
2148SDValue AMDGPUTargetLowering::LowerFREM(SDValue Op, SelectionDAG &DAG) const {
2149 SDLoc SL(Op);
2150 EVT VT = Op.getValueType();
2151 auto Flags = Op->getFlags();
2152 SDValue X = Op.getOperand(0);
2153 SDValue Y = Op.getOperand(1);
2154
2155 SDValue Div = DAG.getNode(ISD::FDIV, SL, VT, X, Y, Flags);
2156 SDValue Trunc = DAG.getNode(ISD::FTRUNC, SL, VT, Div, Flags);
2157 SDValue Neg = DAG.getNode(ISD::FNEG, SL, VT, Trunc, Flags);
2158 // TODO: For f32 use FMAD instead if !hasFastFMA32?
2159 return DAG.getNode(ISD::FMA, SL, VT, Neg, Y, X, Flags);
2160}
2161
2162SDValue AMDGPUTargetLowering::LowerFCEIL(SDValue Op, SelectionDAG &DAG) const {
2163 SDLoc SL(Op);
2164 SDValue Src = Op.getOperand(0);
2165
2166 // result = trunc(src)
2167 // if (src > 0.0 && src != result)
2168 // result += 1.0
2169
2170 SDValue Trunc = DAG.getNode(ISD::FTRUNC, SL, MVT::f64, Src);
2171
2172 const SDValue Zero = DAG.getConstantFP(0.0, SL, MVT::f64);
2173 const SDValue One = DAG.getConstantFP(1.0, SL, MVT::f64);
2174
2175 EVT SetCCVT =
2176 getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), MVT::f64);
2177
2178 SDValue Lt0 = DAG.getSetCC(SL, SetCCVT, Src, Zero, ISD::SETOGT);
2179 SDValue NeTrunc = DAG.getSetCC(SL, SetCCVT, Src, Trunc, ISD::SETONE);
2180 SDValue And = DAG.getNode(ISD::AND, SL, SetCCVT, Lt0, NeTrunc);
2181
2182 SDValue Add = DAG.getNode(ISD::SELECT, SL, MVT::f64, And, One, Zero);
2183 // TODO: Should this propagate fast-math-flags?
2184 return DAG.getNode(ISD::FADD, SL, MVT::f64, Trunc, Add);
2185}
2186
2187static SDValue extractF64Exponent(SDValue Hi, const SDLoc &SL,
2188 SelectionDAG &DAG) {
2189 const unsigned FractBits = 52;
2190 const unsigned ExpBits = 11;
2191
2192 SDValue ExpPart = DAG.getNode(AMDGPUISD::BFE_U32, SL, MVT::i32,
2193 Hi,
2194 DAG.getConstant(FractBits - 32, SL, MVT::i32),
2195 DAG.getConstant(ExpBits, SL, MVT::i32));
2196 SDValue Exp = DAG.getNode(ISD::SUB, SL, MVT::i32, ExpPart,
2197 DAG.getConstant(1023, SL, MVT::i32));
2198
2199 return Exp;
2200}
2201
2202SDValue AMDGPUTargetLowering::LowerFTRUNC(SDValue Op, SelectionDAG &DAG) const {
2203 SDLoc SL(Op);
2204 SDValue Src = Op.getOperand(0);
2205
2206 assert(Op.getValueType() == MVT::f64)(static_cast <bool> (Op.getValueType() == MVT::f64) ? void
(0) : __assert_fail ("Op.getValueType() == MVT::f64", "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp"
, 2206, __extension__ __PRETTY_FUNCTION__))
;
2207
2208 const SDValue Zero = DAG.getConstant(0, SL, MVT::i32);
2209
2210 // Extract the upper half, since this is where we will find the sign and
2211 // exponent.
2212 SDValue Hi = getHiHalf64(Src, DAG);
2213
2214 SDValue Exp = extractF64Exponent(Hi, SL, DAG);
2215
2216 const unsigned FractBits = 52;
2217
2218 // Extract the sign bit.
2219 const SDValue SignBitMask = DAG.getConstant(UINT32_C(1)1U << 31, SL, MVT::i32);
2220 SDValue SignBit = DAG.getNode(ISD::AND, SL, MVT::i32, Hi, SignBitMask);
2221
2222 // Extend back to 64-bits.
2223 SDValue SignBit64 = DAG.getBuildVector(MVT::v2i32, SL, {Zero, SignBit});
2224 SignBit64 = DAG.getNode(ISD::BITCAST, SL, MVT::i64, SignBit64);
2225
2226 SDValue BcInt = DAG.getNode(ISD::BITCAST, SL, MVT::i64, Src);
2227 const SDValue FractMask
2228 = DAG.getConstant((UINT64_C(1)1UL << FractBits) - 1, SL, MVT::i64);
2229
2230 SDValue Shr = DAG.getNode(ISD::SRA, SL, MVT::i64, FractMask, Exp);
2231 SDValue Not = DAG.getNOT(SL, Shr, MVT::i64);
2232 SDValue Tmp0 = DAG.getNode(ISD::AND, SL, MVT::i64, BcInt, Not);
2233
2234 EVT SetCCVT =
2235 getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), MVT::i32);
2236
2237 const SDValue FiftyOne = DAG.getConstant(FractBits - 1, SL, MVT::i32);
2238
2239 SDValue ExpLt0 = DAG.getSetCC(SL, SetCCVT, Exp, Zero, ISD::SETLT);
2240 SDValue ExpGt51 = DAG.getSetCC(SL, SetCCVT, Exp, FiftyOne, ISD::SETGT);
2241
2242 SDValue Tmp1 = DAG.getNode(ISD::SELECT, SL, MVT::i64, ExpLt0, SignBit64, Tmp0);
2243 SDValue Tmp2 = DAG.getNode(ISD::SELECT, SL, MVT::i64, ExpGt51, BcInt, Tmp1);
2244
2245 return DAG.getNode(ISD::BITCAST, SL, MVT::f64, Tmp2);
2246}
2247
2248SDValue AMDGPUTargetLowering::LowerFRINT(SDValue Op, SelectionDAG &DAG) const {
2249 SDLoc SL(Op);
2250 SDValue Src = Op.getOperand(0);
2251
2252 assert(Op.getValueType() == MVT::f64)(static_cast <bool> (Op.getValueType() == MVT::f64) ? void
(0) : __assert_fail ("Op.getValueType() == MVT::f64", "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp"
, 2252, __extension__ __PRETTY_FUNCTION__))
;
2253
2254 APFloat C1Val(APFloat::IEEEdouble(), "0x1.0p+52");
2255 SDValue C1 = DAG.getConstantFP(C1Val, SL, MVT::f64);
2256 SDValue CopySign = DAG.getNode(ISD::FCOPYSIGN, SL, MVT::f64, C1, Src);
2257
2258 // TODO: Should this propagate fast-math-flags?
2259
2260 SDValue Tmp1 = DAG.getNode(ISD::FADD, SL, MVT::f64, Src, CopySign);
2261 SDValue Tmp2 = DAG.getNode(ISD::FSUB, SL, MVT::f64, Tmp1, CopySign);
2262
2263 SDValue Fabs = DAG.getNode(ISD::FABS, SL, MVT::f64, Src);
2264
2265 APFloat C2Val(APFloat::IEEEdouble(), "0x1.fffffffffffffp+51");
2266 SDValue C2 = DAG.getConstantFP(C2Val, SL, MVT::f64);
2267
2268 EVT SetCCVT =
2269 getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), MVT::f64);
2270 SDValue Cond = DAG.getSetCC(SL, SetCCVT, Fabs, C2, ISD::SETOGT);
2271
2272 return DAG.getSelect(SL, MVT::f64, Cond, Src, Tmp2);
2273}
2274
2275SDValue AMDGPUTargetLowering::LowerFNEARBYINT(SDValue Op, SelectionDAG &DAG) const {
2276 // FNEARBYINT and FRINT are the same, except in their handling of FP
2277 // exceptions. Those aren't really meaningful for us, and OpenCL only has
2278 // rint, so just treat them as equivalent.
2279 return DAG.getNode(ISD::FRINT, SDLoc(Op), Op.getValueType(), Op.getOperand(0));
2280}
2281
2282// XXX - May require not supporting f32 denormals?
2283
2284// Don't handle v2f16. The extra instructions to scalarize and repack around the
2285// compare and vselect end up producing worse code than scalarizing the whole
2286// operation.
2287SDValue AMDGPUTargetLowering::LowerFROUND(SDValue Op, SelectionDAG &DAG) const {
2288 SDLoc SL(Op);
2289 SDValue X = Op.getOperand(0);
2290 EVT VT = Op.getValueType();
2291
2292 SDValue T = DAG.getNode(ISD::FTRUNC, SL, VT, X);
2293
2294 // TODO: Should this propagate fast-math-flags?
2295
2296 SDValue Diff = DAG.getNode(ISD::FSUB, SL, VT, X, T);
2297
2298 SDValue AbsDiff = DAG.getNode(ISD::FABS, SL, VT, Diff);
2299
2300 const SDValue Zero = DAG.getConstantFP(0.0, SL, VT);
2301 const SDValue One = DAG.getConstantFP(1.0, SL, VT);
2302 const SDValue Half = DAG.getConstantFP(0.5, SL, VT);
2303
2304 SDValue SignOne = DAG.getNode(ISD::FCOPYSIGN, SL, VT, One, X);
2305
2306 EVT SetCCVT =
2307 getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT);
2308
2309 SDValue Cmp = DAG.getSetCC(SL, SetCCVT, AbsDiff, Half, ISD::SETOGE);
2310
2311 SDValue Sel = DAG.getNode(ISD::SELECT, SL, VT, Cmp, SignOne, Zero);
2312
2313 return DAG.getNode(ISD::FADD, SL, VT, T, Sel);
2314}
2315
2316SDValue AMDGPUTargetLowering::LowerFFLOOR(SDValue Op, SelectionDAG &DAG) const {
2317 SDLoc SL(Op);
2318 SDValue Src = Op.getOperand(0);
2319
2320 // result = trunc(src);
2321 // if (src < 0.0 && src != result)
2322 // result += -1.0.
2323
2324 SDValue Trunc = DAG.getNode(ISD::FTRUNC, SL, MVT::f64, Src);
2325
2326 const SDValue Zero = DAG.getConstantFP(0.0, SL, MVT::f64);
2327 const SDValue NegOne = DAG.getConstantFP(-1.0, SL, MVT::f64);
2328
2329 EVT SetCCVT =
2330 getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), MVT::f64);
2331
2332 SDValue Lt0 = DAG.getSetCC(SL, SetCCVT, Src, Zero, ISD::SETOLT);
2333 SDValue NeTrunc = DAG.getSetCC(SL, SetCCVT, Src, Trunc, ISD::SETONE);
2334 SDValue And = DAG.getNode(ISD::AND, SL, SetCCVT, Lt0, NeTrunc);
2335
2336 SDValue Add = DAG.getNode(ISD::SELECT, SL, MVT::f64, And, NegOne, Zero);
2337 // TODO: Should this propagate fast-math-flags?
2338 return DAG.getNode(ISD::FADD, SL, MVT::f64, Trunc, Add);
2339}
2340
2341SDValue AMDGPUTargetLowering::LowerFLOG(SDValue Op, SelectionDAG &DAG,
2342 double Log2BaseInverted) const {
2343 EVT VT = Op.getValueType();
2344
2345 SDLoc SL(Op);
2346 SDValue Operand = Op.getOperand(0);
2347 SDValue Log2Operand = DAG.getNode(ISD::FLOG2, SL, VT, Operand);
2348 SDValue Log2BaseInvertedOperand = DAG.getConstantFP(Log2BaseInverted, SL, VT);
2349
2350 return DAG.getNode(ISD::FMUL, SL, VT, Log2Operand, Log2BaseInvertedOperand);
2351}
2352
2353// exp2(M_LOG2E_F * f);
2354SDValue AMDGPUTargetLowering::lowerFEXP(SDValue Op, SelectionDAG &DAG) const {
2355 EVT VT = Op.getValueType();
2356 SDLoc SL(Op);
2357 SDValue Src = Op.getOperand(0);
2358
2359 const SDValue K = DAG.getConstantFP(numbers::log2e, SL, VT);
2360 SDValue Mul = DAG.getNode(ISD::FMUL, SL, VT, Src, K, Op->getFlags());
2361 return DAG.getNode(ISD::FEXP2, SL, VT, Mul, Op->getFlags());
2362}
2363
2364static bool isCtlzOpc(unsigned Opc) {
2365 return Opc == ISD::CTLZ || Opc == ISD::CTLZ_ZERO_UNDEF;
2366}
2367
2368static bool isCttzOpc(unsigned Opc) {
2369 return Opc == ISD::CTTZ || Opc == ISD::CTTZ_ZERO_UNDEF;
2370}
2371
2372SDValue AMDGPUTargetLowering::LowerCTLZ_CTTZ(SDValue Op, SelectionDAG &DAG) const {
2373 SDLoc SL(Op);
2374 SDValue Src = Op.getOperand(0);
2375
2376 assert(isCtlzOpc(Op.getOpcode()) || isCttzOpc(Op.getOpcode()))(static_cast <bool> (isCtlzOpc(Op.getOpcode()) || isCttzOpc
(Op.getOpcode())) ? void (0) : __assert_fail ("isCtlzOpc(Op.getOpcode()) || isCttzOpc(Op.getOpcode())"
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp"
, 2376, __extension__ __PRETTY_FUNCTION__))
;
2377 bool Ctlz = isCtlzOpc(Op.getOpcode());
2378 unsigned NewOpc = Ctlz ? AMDGPUISD::FFBH_U32 : AMDGPUISD::FFBL_B32;
2379
2380 bool ZeroUndef = Op.getOpcode() == ISD::CTLZ_ZERO_UNDEF ||
2381 Op.getOpcode() == ISD::CTTZ_ZERO_UNDEF;
2382
2383 if (Src.getValueType() == MVT::i32) {
2384 // (ctlz hi:lo) -> (umin (ffbh src), 32)
2385 // (cttz hi:lo) -> (umin (ffbl src), 32)
2386 // (ctlz_zero_undef src) -> (ffbh src)
2387 // (cttz_zero_undef src) -> (ffbl src)
2388 SDValue NewOpr = DAG.getNode(NewOpc, SL, MVT::i32, Src);
2389 if (!ZeroUndef) {
2390 const SDValue Const32 = DAG.getConstant(32, SL, MVT::i32);
2391 NewOpr = DAG.getNode(ISD::UMIN, SL, MVT::i32, NewOpr, Const32);
2392 }
2393 return NewOpr;
2394 }
2395
2396 SDValue Lo, Hi;
2397 std::tie(Lo, Hi) = split64BitValue(Src, DAG);
2398
2399 SDValue OprLo = DAG.getNode(NewOpc, SL, MVT::i32, Lo);
2400 SDValue OprHi = DAG.getNode(NewOpc, SL, MVT::i32, Hi);
2401
2402 // (ctlz hi:lo) -> (umin3 (ffbh hi), (uaddsat (ffbh lo), 32), 64)
2403 // (cttz hi:lo) -> (umin3 (uaddsat (ffbl hi), 32), (ffbl lo), 64)
2404 // (ctlz_zero_undef hi:lo) -> (umin (ffbh hi), (add (ffbh lo), 32))
2405 // (cttz_zero_undef hi:lo) -> (umin (add (ffbl hi), 32), (ffbl lo))
2406
2407 unsigned AddOpc = ZeroUndef ? ISD::ADD : ISD::UADDSAT;
2408 const SDValue Const32 = DAG.getConstant(32, SL, MVT::i32);
2409 if (Ctlz)
2410 OprLo = DAG.getNode(AddOpc, SL, MVT::i32, OprLo, Const32);
2411 else
2412 OprHi = DAG.getNode(AddOpc, SL, MVT::i32, OprHi, Const32);
2413
2414 SDValue NewOpr;
2415 NewOpr = DAG.getNode(ISD::UMIN, SL, MVT::i32, OprLo, OprHi);
2416 if (!ZeroUndef) {
2417 const SDValue Const64 = DAG.getConstant(64, SL, MVT::i32);
2418 NewOpr = DAG.getNode(ISD::UMIN, SL, MVT::i32, NewOpr, Const64);
2419 }
2420
2421 return DAG.getNode(ISD::ZERO_EXTEND, SL, MVT::i64, NewOpr);
2422}
2423
2424SDValue AMDGPUTargetLowering::LowerINT_TO_FP32(SDValue Op, SelectionDAG &DAG,
2425 bool Signed) const {
2426 // The regular method converting a 64-bit integer to float roughly consists of
2427 // 2 steps: normalization and rounding. In fact, after normalization, the
2428 // conversion from a 64-bit integer to a float is essentially the same as the
2429 // one from a 32-bit integer. The only difference is that it has more
2430 // trailing bits to be rounded. To leverage the native 32-bit conversion, a
2431 // 64-bit integer could be preprocessed and fit into a 32-bit integer then
2432 // converted into the correct float number. The basic steps for the unsigned
2433 // conversion are illustrated in the following pseudo code:
2434 //
2435 // f32 uitofp(i64 u) {
2436 // i32 hi, lo = split(u);
2437 // // Only count the leading zeros in hi as we have native support of the
2438 // // conversion from i32 to f32. If hi is all 0s, the conversion is
2439 // // reduced to a 32-bit one automatically.
2440 // i32 shamt = clz(hi); // Return 32 if hi is all 0s.
2441 // u <<= shamt;
2442 // hi, lo = split(u);
2443 // hi |= (lo != 0) ? 1 : 0; // Adjust rounding bit in hi based on lo.
2444 // // convert it as a 32-bit integer and scale the result back.
2445 // return uitofp(hi) * 2^(32 - shamt);
2446 // }
2447 //
2448 // The signed one follows the same principle but uses 'ffbh_i32' to count its
2449 // sign bits instead. If 'ffbh_i32' is not available, its absolute value is
2450 // converted instead followed by negation based its sign bit.
2451
2452 SDLoc SL(Op);
2453 SDValue Src = Op.getOperand(0);
2454
2455 SDValue Lo, Hi;
2456 std::tie(Lo, Hi) = split64BitValue(Src, DAG);
2457 SDValue Sign;
2458 SDValue ShAmt;
2459 if (Signed && Subtarget->isGCN()) {
2460 // We also need to consider the sign bit in Lo if Hi has just sign bits,
2461 // i.e. Hi is 0 or -1. However, that only needs to take the MSB into
2462 // account. That is, the maximal shift is
2463 // - 32 if Lo and Hi have opposite signs;
2464 // - 33 if Lo and Hi have the same sign.
2465 //
2466 // Or, MaxShAmt = 33 + OppositeSign, where
2467 //
2468 // OppositeSign is defined as ((Lo ^ Hi) >> 31), which is
2469 // - -1 if Lo and Hi have opposite signs; and
2470 // - 0 otherwise.
2471 //
2472 // All in all, ShAmt is calculated as
2473 //
2474 // umin(sffbh(Hi), 33 + (Lo^Hi)>>31) - 1.
2475 //
2476 // or
2477 //
2478 // umin(sffbh(Hi) - 1, 32 + (Lo^Hi)>>31).
2479 //
2480 // to reduce the critical path.
2481 SDValue OppositeSign = DAG.getNode(
2482 ISD::SRA, SL, MVT::i32, DAG.getNode(ISD::XOR, SL, MVT::i32, Lo, Hi),
2483 DAG.getConstant(31, SL, MVT::i32));
2484 SDValue MaxShAmt =
2485 DAG.getNode(ISD::ADD, SL, MVT::i32, DAG.getConstant(32, SL, MVT::i32),
2486 OppositeSign);
2487 // Count the leading sign bits.
2488 ShAmt = DAG.getNode(AMDGPUISD::FFBH_I32, SL, MVT::i32, Hi);
2489 // Different from unsigned conversion, the shift should be one bit less to
2490 // preserve the sign bit.
2491 ShAmt = DAG.getNode(ISD::SUB, SL, MVT::i32, ShAmt,
2492 DAG.getConstant(1, SL, MVT::i32));
2493 ShAmt = DAG.getNode(ISD::UMIN, SL, MVT::i32, ShAmt, MaxShAmt);
2494 } else {
2495 if (Signed) {
2496 // Without 'ffbh_i32', only leading zeros could be counted. Take the
2497 // absolute value first.
2498 Sign = DAG.getNode(ISD::SRA, SL, MVT::i64, Src,
2499 DAG.getConstant(63, SL, MVT::i64));
2500 SDValue Abs =
2501 DAG.getNode(ISD::XOR, SL, MVT::i64,
2502 DAG.getNode(ISD::ADD, SL, MVT::i64, Src, Sign), Sign);
2503 std::tie(Lo, Hi) = split64BitValue(Abs, DAG);
2504 }
2505 // Count the leading zeros.
2506 ShAmt = DAG.getNode(ISD::CTLZ, SL, MVT::i32, Hi);
2507 // The shift amount for signed integers is [0, 32].
2508 }
2509 // Normalize the given 64-bit integer.
2510 SDValue Norm = DAG.getNode(ISD::SHL, SL, MVT::i64, Src, ShAmt);
2511 // Split it again.
2512 std::tie(Lo, Hi) = split64BitValue(Norm, DAG);
2513 // Calculate the adjust bit for rounding.
2514 // (lo != 0) ? 1 : 0 => (lo >= 1) ? 1 : 0 => umin(1, lo)
2515 SDValue Adjust = DAG.getNode(ISD::UMIN, SL, MVT::i32,
2516 DAG.getConstant(1, SL, MVT::i32), Lo);
2517 // Get the 32-bit normalized integer.
2518 Norm = DAG.getNode(ISD::OR, SL, MVT::i32, Hi, Adjust);
2519 // Convert the normalized 32-bit integer into f32.
2520 unsigned Opc =
2521 (Signed && Subtarget->isGCN()) ? ISD::SINT_TO_FP : ISD::UINT_TO_FP;
2522 SDValue FVal = DAG.getNode(Opc, SL, MVT::f32, Norm);
2523
2524 // Finally, need to scale back the converted floating number as the original
2525 // 64-bit integer is converted as a 32-bit one.
2526 ShAmt = DAG.getNode(ISD::SUB, SL, MVT::i32, DAG.getConstant(32, SL, MVT::i32),
2527 ShAmt);
2528 // On GCN, use LDEXP directly.
2529 if (Subtarget->isGCN())
2530 return DAG.getNode(AMDGPUISD::LDEXP, SL, MVT::f32, FVal, ShAmt);
2531
2532 // Otherwise, align 'ShAmt' to the exponent part and add it into the exponent
2533 // part directly to emulate the multiplication of 2^ShAmt. That 8-bit
2534 // exponent is enough to avoid overflowing into the sign bit.
2535 SDValue Exp = DAG.getNode(ISD::SHL, SL, MVT::i32, ShAmt,
2536 DAG.getConstant(23, SL, MVT::i32));
2537 SDValue IVal =
2538 DAG.getNode(ISD::ADD, SL, MVT::i32,
2539 DAG.getNode(ISD::BITCAST, SL, MVT::i32, FVal), Exp);
2540 if (Signed) {
2541 // Set the sign bit.
2542 Sign = DAG.getNode(ISD::SHL, SL, MVT::i32,
2543 DAG.getNode(ISD::TRUNCATE, SL, MVT::i32, Sign),
2544 DAG.getConstant(31, SL, MVT::i32));
2545 IVal = DAG.getNode(ISD::OR, SL, MVT::i32, IVal, Sign);
2546 }
2547 return DAG.getNode(ISD::BITCAST, SL, MVT::f32, IVal);
2548}
2549
2550SDValue AMDGPUTargetLowering::LowerINT_TO_FP64(SDValue Op, SelectionDAG &DAG,
2551 bool Signed) const {
2552 SDLoc SL(Op);
2553 SDValue Src = Op.getOperand(0);
2554
2555 SDValue Lo, Hi;
2556 std::tie(Lo, Hi) = split64BitValue(Src, DAG);
2557
2558 SDValue CvtHi = DAG.getNode(Signed ? ISD::SINT_TO_FP : ISD::UINT_TO_FP,
2559 SL, MVT::f64, Hi);
2560
2561 SDValue CvtLo = DAG.getNode(ISD::UINT_TO_FP, SL, MVT::f64, Lo);
2562
2563 SDValue LdExp = DAG.getNode(AMDGPUISD::LDEXP, SL, MVT::f64, CvtHi,
2564 DAG.getConstant(32, SL, MVT::i32));
2565 // TODO: Should this propagate fast-math-flags?
2566 return DAG.getNode(ISD::FADD, SL, MVT::f64, LdExp, CvtLo);
2567}
2568
2569SDValue AMDGPUTargetLowering::LowerUINT_TO_FP(SDValue Op,
2570 SelectionDAG &DAG) const {
2571 // TODO: Factor out code common with LowerSINT_TO_FP.
2572 EVT DestVT = Op.getValueType();
2573 SDValue Src = Op.getOperand(0);
2574 EVT SrcVT = Src.getValueType();
2575
2576 if (SrcVT == MVT::i16) {
2577 if (DestVT == MVT::f16)
2578 return Op;
2579 SDLoc DL(Op);
2580
2581 // Promote src to i32
2582 SDValue Ext = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, Src);
2583 return DAG.getNode(ISD::UINT_TO_FP, DL, DestVT, Ext);
2584 }
2585
2586 assert(SrcVT == MVT::i64 && "operation should be legal")(static_cast <bool> (SrcVT == MVT::i64 && "operation should be legal"
) ? void (0) : __assert_fail ("SrcVT == MVT::i64 && \"operation should be legal\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp"
, 2586, __extension__ __PRETTY_FUNCTION__))
;
2587
2588 if (Subtarget->has16BitInsts() && DestVT == MVT::f16) {
2589 SDLoc DL(Op);
2590
2591 SDValue IntToFp32 = DAG.getNode(Op.getOpcode(), DL, MVT::f32, Src);
2592 SDValue FPRoundFlag = DAG.getIntPtrConstant(0, SDLoc(Op));
2593 SDValue FPRound =
2594 DAG.getNode(ISD::FP_ROUND, DL, MVT::f16, IntToFp32, FPRoundFlag);
2595
2596 return FPRound;
2597 }
2598
2599 if (DestVT == MVT::f32)
2600 return LowerINT_TO_FP32(Op, DAG, false);
2601
2602 assert(DestVT == MVT::f64)(static_cast <bool> (DestVT == MVT::f64) ? void (0) : __assert_fail
("DestVT == MVT::f64", "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp"
, 2602, __extension__ __PRETTY_FUNCTION__))
;
2603 return LowerINT_TO_FP64(Op, DAG, false);
2604}
2605
2606SDValue AMDGPUTargetLowering::LowerSINT_TO_FP(SDValue Op,
2607 SelectionDAG &DAG) const {
2608 EVT DestVT = Op.getValueType();
2609
2610 SDValue Src = Op.getOperand(0);
2611 EVT SrcVT = Src.getValueType();
2612
2613 if (SrcVT == MVT::i16) {
2614 if (DestVT == MVT::f16)
2615 return Op;
2616
2617 SDLoc DL(Op);
2618 // Promote src to i32
2619 SDValue Ext = DAG.getNode(ISD::SIGN_EXTEND, DL, MVT::i32, Src);
2620 return DAG.getNode(ISD::SINT_TO_FP, DL, DestVT, Ext);
2621 }
2622
2623 assert(SrcVT == MVT::i64 && "operation should be legal")(static_cast <bool> (SrcVT == MVT::i64 && "operation should be legal"
) ? void (0) : __assert_fail ("SrcVT == MVT::i64 && \"operation should be legal\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp"
, 2623, __extension__ __PRETTY_FUNCTION__))
;
2624
2625 // TODO: Factor out code common with LowerUINT_TO_FP.
2626
2627 if (Subtarget->has16BitInsts() && DestVT == MVT::f16) {
2628 SDLoc DL(Op);
2629 SDValue Src = Op.getOperand(0);
2630
2631 SDValue IntToFp32 = DAG.getNode(Op.getOpcode(), DL, MVT::f32, Src);
2632 SDValue FPRoundFlag = DAG.getIntPtrConstant(0, SDLoc(Op));
2633 SDValue FPRound =
2634 DAG.getNode(ISD::FP_ROUND, DL, MVT::f16, IntToFp32, FPRoundFlag);
2635
2636 return FPRound;
2637 }
2638
2639 if (DestVT == MVT::f32)
2640 return LowerINT_TO_FP32(Op, DAG, true);
2641
2642 assert(DestVT == MVT::f64)(static_cast <bool> (DestVT == MVT::f64) ? void (0) : __assert_fail
("DestVT == MVT::f64", "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp"
, 2642, __extension__ __PRETTY_FUNCTION__))
;
2643 return LowerINT_TO_FP64(Op, DAG, true);
2644}
2645
2646SDValue AMDGPUTargetLowering::LowerFP_TO_INT64(SDValue Op, SelectionDAG &DAG,
2647 bool Signed) const {
2648 SDLoc SL(Op);
2649
2650 SDValue Src = Op.getOperand(0);
2651 EVT SrcVT = Src.getValueType();
2652
2653 assert(SrcVT == MVT::f32 || SrcVT == MVT::f64)(static_cast <bool> (SrcVT == MVT::f32 || SrcVT == MVT::
f64) ? void (0) : __assert_fail ("SrcVT == MVT::f32 || SrcVT == MVT::f64"
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp"
, 2653, __extension__ __PRETTY_FUNCTION__))
;
2654
2655 // The basic idea of converting a floating point number into a pair of 32-bit
2656 // integers is illustrated as follows:
2657 //
2658 // tf := trunc(val);
2659 // hif := floor(tf * 2^-32);
2660 // lof := tf - hif * 2^32; // lof is always positive due to floor.
2661 // hi := fptoi(hif);
2662 // lo := fptoi(lof);
2663 //
2664 SDValue Trunc = DAG.getNode(ISD::FTRUNC, SL, SrcVT, Src);
2665 SDValue Sign;
2666 if (Signed && SrcVT == MVT::f32) {
2667 // However, a 32-bit floating point number has only 23 bits mantissa and
2668 // it's not enough to hold all the significant bits of `lof` if val is
2669 // negative. To avoid the loss of precision, We need to take the absolute
2670 // value after truncating and flip the result back based on the original
2671 // signedness.
2672 Sign = DAG.getNode(ISD::SRA, SL, MVT::i32,
2673 DAG.getNode(ISD::BITCAST, SL, MVT::i32, Trunc),
2674 DAG.getConstant(31, SL, MVT::i32));
2675 Trunc = DAG.getNode(ISD::FABS, SL, SrcVT, Trunc);
2676 }
2677
2678 SDValue K0, K1;
2679 if (SrcVT == MVT::f64) {
2680 K0 = DAG.getConstantFP(BitsToDouble(UINT64_C(/*2^-32*/ 0x3df0000000000000)0x3df0000000000000UL),
2681 SL, SrcVT);
2682 K1 = DAG.getConstantFP(BitsToDouble(UINT64_C(/*-2^32*/ 0xc1f0000000000000)0xc1f0000000000000UL),
2683 SL, SrcVT);
2684 } else {
2685 K0 = DAG.getConstantFP(BitsToFloat(UINT32_C(/*2^-32*/ 0x2f800000)0x2f800000U), SL,
2686 SrcVT);
2687 K1 = DAG.getConstantFP(BitsToFloat(UINT32_C(/*-2^32*/ 0xcf800000)0xcf800000U), SL,
2688 SrcVT);
2689 }
2690 // TODO: Should this propagate fast-math-flags?
2691 SDValue Mul = DAG.getNode(ISD::FMUL, SL, SrcVT, Trunc, K0);
2692
2693 SDValue FloorMul = DAG.getNode(ISD::FFLOOR, SL, SrcVT, Mul);
2694
2695 SDValue Fma = DAG.getNode(ISD::FMA, SL, SrcVT, FloorMul, K1, Trunc);
2696
2697 SDValue Hi = DAG.getNode((Signed && SrcVT == MVT::f64) ? ISD::FP_TO_SINT
2698 : ISD::FP_TO_UINT,
2699 SL, MVT::i32, FloorMul);
2700 SDValue Lo = DAG.getNode(ISD::FP_TO_UINT, SL, MVT::i32, Fma);
2701
2702 SDValue Result = DAG.getNode(ISD::BITCAST, SL, MVT::i64,
2703 DAG.getBuildVector(MVT::v2i32, SL, {Lo, Hi}));
2704
2705 if (Signed && SrcVT == MVT::f32) {
2706 assert(Sign)(static_cast <bool> (Sign) ? void (0) : __assert_fail (
"Sign", "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp"
, 2706, __extension__ __PRETTY_FUNCTION__))
;
2707 // Flip the result based on the signedness, which is either all 0s or 1s.
2708 Sign = DAG.getNode(ISD::BITCAST, SL, MVT::i64,
2709 DAG.getBuildVector(MVT::v2i32, SL, {Sign, Sign}));
2710 // r := xor(r, sign) - sign;
2711 Result =
2712 DAG.getNode(ISD::SUB, SL, MVT::i64,
2713 DAG.getNode(ISD::XOR, SL, MVT::i64, Result, Sign), Sign);
2714 }
2715
2716 return Result;
2717}
2718
2719SDValue AMDGPUTargetLowering::LowerFP_TO_FP16(SDValue Op, SelectionDAG &DAG) const {
2720 SDLoc DL(Op);
2721 SDValue N0 = Op.getOperand(0);
2722
2723 // Convert to target node to get known bits
2724 if (N0.getValueType() == MVT::f32)
2725 return DAG.getNode(AMDGPUISD::FP_TO_FP16, DL, Op.getValueType(), N0);
2726
2727 if (getTargetMachine().Options.UnsafeFPMath) {
2728 // There is a generic expand for FP_TO_FP16 with unsafe fast math.
2729 return SDValue();
2730 }
2731
2732 assert(N0.getSimpleValueType() == MVT::f64)(static_cast <bool> (N0.getSimpleValueType() == MVT::f64
) ? void (0) : __assert_fail ("N0.getSimpleValueType() == MVT::f64"
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp"
, 2732, __extension__ __PRETTY_FUNCTION__))
;
2733
2734 // f64 -> f16 conversion using round-to-nearest-even rounding mode.
2735 const unsigned ExpMask = 0x7ff;
2736 const unsigned ExpBiasf64 = 1023;
2737 const unsigned ExpBiasf16 = 15;
2738 SDValue Zero = DAG.getConstant(0, DL, MVT::i32);
2739 SDValue One = DAG.getConstant(1, DL, MVT::i32);
2740 SDValue U = DAG.getNode(ISD::BITCAST, DL, MVT::i64, N0);
2741 SDValue UH = DAG.getNode(ISD::SRL, DL, MVT::i64, U,
2742 DAG.getConstant(32, DL, MVT::i64));
2743 UH = DAG.getZExtOrTrunc(UH, DL, MVT::i32);
2744 U = DAG.getZExtOrTrunc(U, DL, MVT::i32);
2745 SDValue E = DAG.getNode(ISD::SRL, DL, MVT::i32, UH,
2746 DAG.getConstant(20, DL, MVT::i64));
2747 E = DAG.getNode(ISD::AND, DL, MVT::i32, E,
2748 DAG.getConstant(ExpMask, DL, MVT::i32));
2749 // Subtract the fp64 exponent bias (1023) to get the real exponent and
2750 // add the f16 bias (15) to get the biased exponent for the f16 format.
2751 E = DAG.getNode(ISD::ADD, DL, MVT::i32, E,
2752 DAG.getConstant(-ExpBiasf64 + ExpBiasf16, DL, MVT::i32));
2753
2754 SDValue M = DAG.getNode(ISD::SRL, DL, MVT::i32, UH,
2755 DAG.getConstant(8, DL, MVT::i32));
2756 M = DAG.getNode(ISD::AND, DL, MVT::i32, M,
2757 DAG.getConstant(0xffe, DL, MVT::i32));
2758
2759 SDValue MaskedSig = DAG.getNode(ISD::AND, DL, MVT::i32, UH,
2760 DAG.getConstant(0x1ff, DL, MVT::i32));
2761 MaskedSig = DAG.getNode(ISD::OR, DL, MVT::i32, MaskedSig, U);
2762
2763 SDValue Lo40Set = DAG.getSelectCC(DL, MaskedSig, Zero, Zero, One, ISD::SETEQ);
2764 M = DAG.getNode(ISD::OR, DL, MVT::i32, M, Lo40Set);
2765
2766 // (M != 0 ? 0x0200 : 0) | 0x7c00;
2767 SDValue I = DAG.getNode(ISD::OR, DL, MVT::i32,
2768 DAG.getSelectCC(DL, M, Zero, DAG.getConstant(0x0200, DL, MVT::i32),
2769 Zero, ISD::SETNE), DAG.getConstant(0x7c00, DL, MVT::i32));
2770
2771 // N = M | (E << 12);
2772 SDValue N = DAG.getNode(ISD::OR, DL, MVT::i32, M,
2773 DAG.getNode(ISD::SHL, DL, MVT::i32, E,
2774 DAG.getConstant(12, DL, MVT::i32)));
2775
2776 // B = clamp(1-E, 0, 13);
2777 SDValue OneSubExp = DAG.getNode(ISD::SUB, DL, MVT::i32,
2778 One, E);
2779 SDValue B = DAG.getNode(ISD::SMAX, DL, MVT::i32, OneSubExp, Zero);
2780 B = DAG.getNode(ISD::SMIN, DL, MVT::i32, B,
2781 DAG.getConstant(13, DL, MVT::i32));
2782
2783 SDValue SigSetHigh = DAG.getNode(ISD::OR, DL, MVT::i32, M,
2784 DAG.getConstant(0x1000, DL, MVT::i32));
2785
2786 SDValue D = DAG.getNode(ISD::SRL, DL, MVT::i32, SigSetHigh, B);
2787 SDValue D0 = DAG.getNode(ISD::SHL, DL, MVT::i32, D, B);
2788 SDValue D1 = DAG.getSelectCC(DL, D0, SigSetHigh, One, Zero, ISD::SETNE);
2789 D = DAG.getNode(ISD::OR, DL, MVT::i32, D, D1);
2790
2791 SDValue V = DAG.getSelectCC(DL, E, One, D, N, ISD::SETLT);
2792 SDValue VLow3 = DAG.getNode(ISD::AND, DL, MVT::i32, V,
2793 DAG.getConstant(0x7, DL, MVT::i32));
2794 V = DAG.getNode(ISD::SRL, DL, MVT::i32, V,
2795 DAG.getConstant(2, DL, MVT::i32));
2796 SDValue V0 = DAG.getSelectCC(DL, VLow3, DAG.getConstant(3, DL, MVT::i32),
2797 One, Zero, ISD::SETEQ);
2798 SDValue V1 = DAG.getSelectCC(DL, VLow3, DAG.getConstant(5, DL, MVT::i32),
2799 One, Zero, ISD::SETGT);
2800 V1 = DAG.getNode(ISD::OR, DL, MVT::i32, V0, V1);
2801 V = DAG.getNode(ISD::ADD, DL, MVT::i32, V, V1);
2802
2803 V = DAG.getSelectCC(DL, E, DAG.getConstant(30, DL, MVT::i32),
2804 DAG.getConstant(0x7c00, DL, MVT::i32), V, ISD::SETGT);
2805 V = DAG.getSelectCC(DL, E, DAG.getConstant(1039, DL, MVT::i32),
2806 I, V, ISD::SETEQ);
2807
2808 // Extract the sign bit.
2809 SDValue Sign = DAG.getNode(ISD::SRL, DL, MVT::i32, UH,
2810 DAG.getConstant(16, DL, MVT::i32));
2811 Sign = DAG.getNode(ISD::AND, DL, MVT::i32, Sign,
2812 DAG.getConstant(0x8000, DL, MVT::i32));
2813
2814 V = DAG.getNode(ISD::OR, DL, MVT::i32, Sign, V);
2815 return DAG.getZExtOrTrunc(V, DL, Op.getValueType());
2816}
2817
2818SDValue AMDGPUTargetLowering::LowerFP_TO_INT(SDValue Op,
2819 SelectionDAG &DAG) const {
2820 SDValue Src = Op.getOperand(0);
2821 unsigned OpOpcode = Op.getOpcode();
2822 EVT SrcVT = Src.getValueType();
2823 EVT DestVT = Op.getValueType();
2824
2825 // Will be selected natively
2826 if (SrcVT == MVT::f16 && DestVT == MVT::i16)
2827 return Op;
2828
2829 // Promote i16 to i32
2830 if (DestVT == MVT::i16 && (SrcVT == MVT::f32 || SrcVT == MVT::f64)) {
2831 SDLoc DL(Op);
2832
2833 SDValue FpToInt32 = DAG.getNode(OpOpcode, DL, MVT::i32, Src);
2834 return DAG.getNode(ISD::TRUNCATE, DL, MVT::i16, FpToInt32);
2835 }
2836
2837 if (SrcVT == MVT::f16 ||
2838 (SrcVT == MVT::f32 && Src.getOpcode() == ISD::FP16_TO_FP)) {
2839 SDLoc DL(Op);
2840
2841 SDValue FpToInt32 = DAG.getNode(OpOpcode, DL, MVT::i32, Src);
2842 unsigned Ext =
2843 OpOpcode == ISD::FP_TO_SINT ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
2844 return DAG.getNode(Ext, DL, MVT::i64, FpToInt32);
2845 }
2846
2847 if (DestVT == MVT::i64 && (SrcVT == MVT::f32 || SrcVT == MVT::f64))
2848 return LowerFP_TO_INT64(Op, DAG, OpOpcode == ISD::FP_TO_SINT);
2849
2850 return SDValue();
2851}
2852
2853SDValue AMDGPUTargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
2854 SelectionDAG &DAG) const {
2855 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
2856 MVT VT = Op.getSimpleValueType();
2857 MVT ScalarVT = VT.getScalarType();
2858
2859 assert(VT.isVector())(static_cast <bool> (VT.isVector()) ? void (0) : __assert_fail
("VT.isVector()", "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp"
, 2859, __extension__ __PRETTY_FUNCTION__))
;
2860
2861 SDValue Src = Op.getOperand(0);
2862 SDLoc DL(Op);
2863
2864 // TODO: Don't scalarize on Evergreen?
2865 unsigned NElts = VT.getVectorNumElements();
2866 SmallVector<SDValue, 8> Args;
2867 DAG.ExtractVectorElements(Src, Args, 0, NElts);
2868
2869 SDValue VTOp = DAG.getValueType(ExtraVT.getScalarType());
2870 for (unsigned I = 0; I < NElts; ++I)
2871 Args[I] = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, ScalarVT, Args[I], VTOp);
2872
2873 return DAG.getBuildVector(VT, DL, Args);
2874}
2875
2876//===----------------------------------------------------------------------===//
2877// Custom DAG optimizations
2878//===----------------------------------------------------------------------===//
2879
2880static bool isU24(SDValue Op, SelectionDAG &DAG) {
2881 return AMDGPUTargetLowering::numBitsUnsigned(Op, DAG) <= 24;
2882}
2883
2884static bool isI24(SDValue Op, SelectionDAG &DAG) {
2885 EVT VT = Op.getValueType();
2886 return VT.getSizeInBits() >= 24 && // Types less than 24-bit should be treated
2887 // as unsigned 24-bit values.
2888 AMDGPUTargetLowering::numBitsSigned(Op, DAG) < 24;
2889}
2890
2891static SDValue simplifyMul24(SDNode *Node24,
2892 TargetLowering::DAGCombinerInfo &DCI) {
2893 SelectionDAG &DAG = DCI.DAG;
2894 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2895 bool IsIntrin = Node24->getOpcode() == ISD::INTRINSIC_WO_CHAIN;
2896
2897 SDValue LHS = IsIntrin ? Node24->getOperand(1) : Node24->getOperand(0);
2898 SDValue RHS = IsIntrin ? Node24->getOperand(2) : Node24->getOperand(1);
2899 unsigned NewOpcode = Node24->getOpcode();
2900 if (IsIntrin) {
2901 unsigned IID = cast<ConstantSDNode>(Node24->getOperand(0))->getZExtValue();
2902 NewOpcode = IID == Intrinsic::amdgcn_mul_i24 ?
2903 AMDGPUISD::MUL_I24 : AMDGPUISD::MUL_U24;
2904 }
2905
2906 APInt Demanded = APInt::getLowBitsSet(LHS.getValueSizeInBits(), 24);
2907
2908 // First try to simplify using SimplifyMultipleUseDemandedBits which allows
2909 // the operands to have other uses, but will only perform simplifications that
2910 // involve bypassing some nodes for this user.
2911 SDValue DemandedLHS = TLI.SimplifyMultipleUseDemandedBits(LHS, Demanded, DAG);
2912 SDValue DemandedRHS = TLI.SimplifyMultipleUseDemandedBits(RHS, Demanded, DAG);
2913 if (DemandedLHS || DemandedRHS)
2914 return DAG.getNode(NewOpcode, SDLoc(Node24), Node24->getVTList(),
2915 DemandedLHS ? DemandedLHS : LHS,
2916 DemandedRHS ? DemandedRHS : RHS);
2917
2918 // Now try SimplifyDemandedBits which can simplify the nodes used by our
2919 // operands if this node is the only user.
2920 if (TLI.SimplifyDemandedBits(LHS, Demanded, DCI))
2921 return SDValue(Node24, 0);
2922 if (TLI.SimplifyDemandedBits(RHS, Demanded, DCI))
2923 return SDValue(Node24, 0);
2924
2925 return SDValue();
2926}
2927
2928template <typename IntTy>
2929static SDValue constantFoldBFE(SelectionDAG &DAG, IntTy Src0, uint32_t Offset,
2930 uint32_t Width, const SDLoc &DL) {
2931 if (Width + Offset < 32) {
2932 uint32_t Shl = static_cast<uint32_t>(Src0) << (32 - Offset - Width);
2933 IntTy Result = static_cast<IntTy>(Shl) >> (32 - Width);
2934 return DAG.getConstant(Result, DL, MVT::i32);
2935 }
2936
2937 return DAG.getConstant(Src0 >> Offset, DL, MVT::i32);
2938}
2939
2940static bool hasVolatileUser(SDNode *Val) {
2941 for (SDNode *U : Val->uses()) {
2942 if (MemSDNode *M = dyn_cast<MemSDNode>(U)) {
2943 if (M->isVolatile())
2944 return true;
2945 }
2946 }
2947
2948 return false;
2949}
2950
2951bool AMDGPUTargetLowering::shouldCombineMemoryType(EVT VT) const {
2952 // i32 vectors are the canonical memory type.
2953 if (VT.getScalarType() == MVT::i32 || isTypeLegal(VT))
2954 return false;
2955
2956 if (!VT.isByteSized())
2957 return false;
2958
2959 unsigned Size = VT.getStoreSize();
2960
2961 if ((Size == 1 || Size == 2 || Size == 4) && !VT.isVector())
2962 return false;
2963
2964 if (Size == 3 || (Size > 4 && (Size % 4 != 0)))
2965 return false;
2966
2967 return true;
2968}
2969
2970// Replace load of an illegal type with a store of a bitcast to a friendlier
2971// type.
2972SDValue AMDGPUTargetLowering::performLoadCombine(SDNode *N,
2973 DAGCombinerInfo &DCI) const {
2974 if (!DCI.isBeforeLegalize())
2975 return SDValue();
2976
2977 LoadSDNode *LN = cast<LoadSDNode>(N);
2978 if (!LN->isSimple() || !ISD::isNormalLoad(LN) || hasVolatileUser(LN))
2979 return SDValue();
2980
2981 SDLoc SL(N);
2982 SelectionDAG &DAG = DCI.DAG;
2983 EVT VT = LN->getMemoryVT();
2984
2985 unsigned Size = VT.getStoreSize();
2986 Align Alignment = LN->getAlign();
2987 if (Alignment < Size && isTypeLegal(VT)) {
2988 bool IsFast;
2989 unsigned AS = LN->getAddressSpace();
2990
2991 // Expand unaligned loads earlier than legalization. Due to visitation order
2992 // problems during legalization, the emitted instructions to pack and unpack
2993 // the bytes again are not eliminated in the case of an unaligned copy.
2994 if (!allowsMisalignedMemoryAccesses(
2995 VT, AS, Alignment, LN->getMemOperand()->getFlags(), &IsFast)) {
2996 SDValue Ops[2];
2997
2998 if (VT.isVector())
2999 std::tie(Ops[0], Ops[1]) = scalarizeVectorLoad(LN, DAG);
3000 else
3001 std::tie(Ops[0], Ops[1]) = expandUnalignedLoad(LN, DAG);
3002
3003 return DAG.getMergeValues(Ops, SDLoc(N));
3004 }
3005
3006 if (!IsFast)
3007 return SDValue();
3008 }
3009
3010 if (!shouldCombineMemoryType(VT))
3011 return SDValue();
3012
3013 EVT NewVT = getEquivalentMemType(*DAG.getContext(), VT);
3014
3015 SDValue NewLoad
3016 = DAG.getLoad(NewVT, SL, LN->getChain(),
3017 LN->getBasePtr(), LN->getMemOperand());
3018
3019 SDValue BC = DAG.getNode(ISD::BITCAST, SL, VT, NewLoad);
3020 DCI.CombineTo(N, BC, NewLoad.getValue(1));
3021 return SDValue(N, 0);
3022}
3023
3024// Replace store of an illegal type with a store of a bitcast to a friendlier
3025// type.
3026SDValue AMDGPUTargetLowering::performStoreCombine(SDNode *N,
3027 DAGCombinerInfo &DCI) const {
3028 if (!DCI.isBeforeLegalize())
3029 return SDValue();
3030
3031 StoreSDNode *SN = cast<StoreSDNode>(N);
3032 if (!SN->isSimple() || !ISD::isNormalStore(SN))
3033 return SDValue();
3034
3035 EVT VT = SN->getMemoryVT();
3036 unsigned Size = VT.getStoreSize();
3037
3038 SDLoc SL(N);
3039 SelectionDAG &DAG = DCI.DAG;
3040 Align Alignment = SN->getAlign();
3041 if (Alignment < Size && isTypeLegal(VT)) {
3042 bool IsFast;
3043 unsigned AS = SN->getAddressSpace();
3044
3045 // Expand unaligned stores earlier than legalization. Due to visitation
3046 // order problems during legalization, the emitted instructions to pack and
3047 // unpack the bytes again are not eliminated in the case of an unaligned
3048 // copy.
3049 if (!allowsMisalignedMemoryAccesses(
3050 VT, AS, Alignment, SN->getMemOperand()->getFlags(), &IsFast)) {
3051 if (VT.isVector())
3052 return scalarizeVectorStore(SN, DAG);
3053
3054 return expandUnalignedStore(SN, DAG);
3055 }
3056
3057 if (!IsFast)
3058 return SDValue();
3059 }
3060
3061 if (!shouldCombineMemoryType(VT))
3062 return SDValue();
3063
3064 EVT NewVT = getEquivalentMemType(*DAG.getContext(), VT);
3065 SDValue Val = SN->getValue();
3066
3067 //DCI.AddToWorklist(Val.getNode());
3068
3069 bool OtherUses = !Val.hasOneUse();
3070 SDValue CastVal = DAG.getNode(ISD::BITCAST, SL, NewVT, Val);
3071 if (OtherUses) {
3072 SDValue CastBack = DAG.getNode(ISD::BITCAST, SL, VT, CastVal);
3073 DAG.ReplaceAllUsesOfValueWith(Val, CastBack);
3074 }
3075
3076 return DAG.getStore(SN->getChain(), SL, CastVal,
3077 SN->getBasePtr(), SN->getMemOperand());
3078}
3079
3080// FIXME: This should go in generic DAG combiner with an isTruncateFree check,
3081// but isTruncateFree is inaccurate for i16 now because of SALU vs. VALU
3082// issues.
3083SDValue AMDGPUTargetLowering::performAssertSZExtCombine(SDNode *N,
3084 DAGCombinerInfo &DCI) const {
3085 SelectionDAG &DAG = DCI.DAG;
3086 SDValue N0 = N->getOperand(0);
3087
3088 // (vt2 (assertzext (truncate vt0:x), vt1)) ->
3089 // (vt2 (truncate (assertzext vt0:x, vt1)))
3090 if (N0.getOpcode() == ISD::TRUNCATE) {
3091 SDValue N1 = N->getOperand(1);
3092 EVT ExtVT = cast<VTSDNode>(N1)->getVT();
3093 SDLoc SL(N);
3094
3095 SDValue Src = N0.getOperand(0);
3096 EVT SrcVT = Src.getValueType();
3097 if (SrcVT.bitsGE(ExtVT)) {
3098 SDValue NewInReg = DAG.getNode(N->getOpcode(), SL, SrcVT, Src, N1);
3099 return DAG.getNode(ISD::TRUNCATE, SL, N->getValueType(0), NewInReg);
3100 }
3101 }
3102
3103 return SDValue();
3104}
3105
3106SDValue AMDGPUTargetLowering::performIntrinsicWOChainCombine(
3107 SDNode *N, DAGCombinerInfo &DCI) const {
3108 unsigned IID = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
3109 switch (IID) {
3110 case Intrinsic::amdgcn_mul_i24:
3111 case Intrinsic::amdgcn_mul_u24:
3112 return simplifyMul24(N, DCI);
3113 case Intrinsic::amdgcn_fract:
3114 case Intrinsic::amdgcn_rsq:
3115 case Intrinsic::amdgcn_rcp_legacy:
3116 case Intrinsic::amdgcn_rsq_legacy:
3117 case Intrinsic::amdgcn_rsq_clamp:
3118 case Intrinsic::amdgcn_ldexp: {
3119 // FIXME: This is probably wrong. If src is an sNaN, it won't be quieted
3120 SDValue Src = N->getOperand(1);
3121 return Src.isUndef() ? Src : SDValue();
3122 }
3123 default:
3124 return SDValue();
3125 }
3126}
3127
3128/// Split the 64-bit value \p LHS into two 32-bit components, and perform the
3129/// binary operation \p Opc to it with the corresponding constant operands.
3130SDValue AMDGPUTargetLowering::splitBinaryBitConstantOpImpl(
3131 DAGCombinerInfo &DCI, const SDLoc &SL,
3132 unsigned Opc, SDValue LHS,
3133 uint32_t ValLo, uint32_t ValHi) const {
3134 SelectionDAG &DAG = DCI.DAG;
3135 SDValue Lo, Hi;
3136 std::tie(Lo, Hi) = split64BitValue(LHS, DAG);
3137
3138 SDValue LoRHS = DAG.getConstant(ValLo, SL, MVT::i32);
3139 SDValue HiRHS = DAG.getConstant(ValHi, SL, MVT::i32);
3140
3141 SDValue LoAnd = DAG.getNode(Opc, SL, MVT::i32, Lo, LoRHS);
3142 SDValue HiAnd = DAG.getNode(Opc, SL, MVT::i32, Hi, HiRHS);
3143
3144 // Re-visit the ands. It's possible we eliminated one of them and it could
3145 // simplify the vector.
3146 DCI.AddToWorklist(Lo.getNode());
3147 DCI.AddToWorklist(Hi.getNode());
3148
3149 SDValue Vec = DAG.getBuildVector(MVT::v2i32, SL, {LoAnd, HiAnd});
3150 return DAG.getNode(ISD::BITCAST, SL, MVT::i64, Vec);
3151}
3152
3153SDValue AMDGPUTargetLowering::performShlCombine(SDNode *N,
3154 DAGCombinerInfo &DCI) const {
3155 EVT VT = N->getValueType(0);
3156
3157 ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N->getOperand(1));
3158 if (!RHS)
3159 return SDValue();
3160
3161 SDValue LHS = N->getOperand(0);
3162 unsigned RHSVal = RHS->getZExtValue();
3163 if (!RHSVal)
3164 return LHS;
3165
3166 SDLoc SL(N);
3167 SelectionDAG &DAG = DCI.DAG;
3168
3169 switch (LHS->getOpcode()) {
3170 default:
3171 break;
3172 case ISD::ZERO_EXTEND:
3173 case ISD::SIGN_EXTEND:
3174 case ISD::ANY_EXTEND: {
3175 SDValue X = LHS->getOperand(0);
3176
3177 if (VT == MVT::i32 && RHSVal == 16 && X.getValueType() == MVT::i16 &&
3178 isOperationLegal(ISD::BUILD_VECTOR, MVT::v2i16)) {
3179 // Prefer build_vector as the canonical form if packed types are legal.
3180 // (shl ([asz]ext i16:x), 16 -> build_vector 0, x
3181 SDValue Vec = DAG.getBuildVector(MVT::v2i16, SL,
3182 { DAG.getConstant(0, SL, MVT::i16), LHS->getOperand(0) });
3183 return DAG.getNode(ISD::BITCAST, SL, MVT::i32, Vec);
3184 }
3185
3186 // shl (ext x) => zext (shl x), if shift does not overflow int
3187 if (VT != MVT::i64)
3188 break;
3189 KnownBits Known = DAG.computeKnownBits(X);
3190 unsigned LZ = Known.countMinLeadingZeros();
3191 if (LZ < RHSVal)
3192 break;
3193 EVT XVT = X.getValueType();
3194 SDValue Shl = DAG.getNode(ISD::SHL, SL, XVT, X, SDValue(RHS, 0));
3195 return DAG.getZExtOrTrunc(Shl, SL, VT);
3196 }
3197 }
3198
3199 if (VT != MVT::i64)
3200 return SDValue();
3201
3202 // i64 (shl x, C) -> (build_pair 0, (shl x, C -32))
3203
3204 // On some subtargets, 64-bit shift is a quarter rate instruction. In the
3205 // common case, splitting this into a move and a 32-bit shift is faster and
3206 // the same code size.
3207 if (RHSVal < 32)
3208 return SDValue();
3209
3210 SDValue ShiftAmt = DAG.getConstant(RHSVal - 32, SL, MVT::i32);
3211
3212 SDValue Lo = DAG.getNode(ISD::TRUNCATE, SL, MVT::i32, LHS);
3213 SDValue NewShift = DAG.getNode(ISD::SHL, SL, MVT::i32, Lo, ShiftAmt);
3214
3215 const SDValue Zero = DAG.getConstant(0, SL, MVT::i32);
3216
3217 SDValue Vec = DAG.getBuildVector(MVT::v2i32, SL, {Zero, NewShift});
3218 return DAG.getNode(ISD::BITCAST, SL, MVT::i64, Vec);
3219}
3220
3221SDValue AMDGPUTargetLowering::performSraCombine(SDNode *N,
3222 DAGCombinerInfo &DCI) const {
3223 if (N->getValueType(0) != MVT::i64)
3224 return SDValue();
3225
3226 const ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N->getOperand(1));
3227 if (!RHS)
3228 return SDValue();
3229
3230 SelectionDAG &DAG = DCI.DAG;
3231 SDLoc SL(N);
3232 unsigned RHSVal = RHS->getZExtValue();
3233
3234 // (sra i64:x, 32) -> build_pair x, (sra hi_32(x), 31)
3235 if (RHSVal == 32) {
3236 SDValue Hi = getHiHalf64(N->getOperand(0), DAG);
3237 SDValue NewShift = DAG.getNode(ISD::SRA, SL, MVT::i32, Hi,
3238 DAG.getConstant(31, SL, MVT::i32));
3239
3240 SDValue BuildVec = DAG.getBuildVector(MVT::v2i32, SL, {Hi, NewShift});
3241 return DAG.getNode(ISD::BITCAST, SL, MVT::i64, BuildVec);
3242 }
3243
3244 // (sra i64:x, 63) -> build_pair (sra hi_32(x), 31), (sra hi_32(x), 31)
3245 if (RHSVal == 63) {
3246 SDValue Hi = getHiHalf64(N->getOperand(0), DAG);
3247 SDValue NewShift = DAG.getNode(ISD::SRA, SL, MVT::i32, Hi,
3248 DAG.getConstant(31, SL, MVT::i32));
3249 SDValue BuildVec = DAG.getBuildVector(MVT::v2i32, SL, {NewShift, NewShift});
3250 return DAG.getNode(ISD::BITCAST, SL, MVT::i64, BuildVec);
3251 }
3252
3253 return SDValue();
3254}
3255
3256SDValue AMDGPUTargetLowering::performSrlCombine(SDNode *N,
3257 DAGCombinerInfo &DCI) const {
3258 auto *RHS = dyn_cast<ConstantSDNode>(N->getOperand(1));
3259 if (!RHS)
3260 return SDValue();
3261
3262 EVT VT = N->getValueType(0);
3263 SDValue LHS = N->getOperand(0);
3264 unsigned ShiftAmt = RHS->getZExtValue();
3265 SelectionDAG &DAG = DCI.DAG;
3266 SDLoc SL(N);
3267
3268 // fold (srl (and x, c1 << c2), c2) -> (and (srl(x, c2), c1)
3269 // this improves the ability to match BFE patterns in isel.
3270 if (LHS.getOpcode() == ISD::AND) {
3271 if (auto *Mask = dyn_cast<ConstantSDNode>(LHS.getOperand(1))) {
3272 if (Mask->getAPIntValue().isShiftedMask() &&
3273 Mask->getAPIntValue().countTrailingZeros() == ShiftAmt) {
3274 return DAG.getNode(
3275 ISD::AND, SL, VT,
3276 DAG.getNode(ISD::SRL, SL, VT, LHS.getOperand(0), N->getOperand(1)),
3277 DAG.getNode(ISD::SRL, SL, VT, LHS.getOperand(1), N->getOperand(1)));
3278 }
3279 }
3280 }
3281
3282 if (VT != MVT::i64)
3283 return SDValue();
3284
3285 if (ShiftAmt < 32)
3286 return SDValue();
3287
3288 // srl i64:x, C for C >= 32
3289 // =>
3290 // build_pair (srl hi_32(x), C - 32), 0
3291 SDValue Zero = DAG.getConstant(0, SL, MVT::i32);
3292
3293 SDValue Hi = getHiHalf64(LHS, DAG);
3294
3295 SDValue NewConst = DAG.getConstant(ShiftAmt - 32, SL, MVT::i32);
3296 SDValue NewShift = DAG.getNode(ISD::SRL, SL, MVT::i32, Hi, NewConst);
3297
3298 SDValue BuildPair = DAG.getBuildVector(MVT::v2i32, SL, {NewShift, Zero});
3299
3300 return DAG.getNode(ISD::BITCAST, SL, MVT::i64, BuildPair);
3301}
3302
3303SDValue AMDGPUTargetLowering::performTruncateCombine(
3304 SDNode *N, DAGCombinerInfo &DCI) const {
3305 SDLoc SL(N);
3306 SelectionDAG &DAG = DCI.DAG;
3307 EVT VT = N->getValueType(0);
3308 SDValue Src = N->getOperand(0);
3309
3310 // vt1 (truncate (bitcast (build_vector vt0:x, ...))) -> vt1 (bitcast vt0:x)
3311 if (Src.getOpcode() == ISD::BITCAST && !VT.isVector()) {
3312 SDValue Vec = Src.getOperand(0);
3313 if (Vec.getOpcode() == ISD::BUILD_VECTOR) {
3314 SDValue Elt0 = Vec.getOperand(0);
3315 EVT EltVT = Elt0.getValueType();
3316 if (VT.getFixedSizeInBits() <= EltVT.getFixedSizeInBits()) {
3317 if (EltVT.isFloatingPoint()) {
3318 Elt0 = DAG.getNode(ISD::BITCAST, SL,
3319 EltVT.changeTypeToInteger(), Elt0);
3320 }
3321
3322 return DAG.getNode(ISD::TRUNCATE, SL, VT, Elt0);
3323 }
3324 }
3325 }
3326
3327 // Equivalent of above for accessing the high element of a vector as an
3328 // integer operation.
3329 // trunc (srl (bitcast (build_vector x, y))), 16 -> trunc (bitcast y)
3330 if (Src.getOpcode() == ISD::SRL && !VT.isVector()) {
3331 if (auto K = isConstOrConstSplat(Src.getOperand(1))) {
3332 if (2 * K->getZExtValue() == Src.getValueType().getScalarSizeInBits()) {
3333 SDValue BV = stripBitcast(Src.getOperand(0));
3334 if (BV.getOpcode() == ISD::BUILD_VECTOR &&
3335 BV.getValueType().getVectorNumElements() == 2) {
3336 SDValue SrcElt = BV.getOperand(1);
3337 EVT SrcEltVT = SrcElt.getValueType();
3338 if (SrcEltVT.isFloatingPoint()) {
3339 SrcElt = DAG.getNode(ISD::BITCAST, SL,
3340 SrcEltVT.changeTypeToInteger(), SrcElt);
3341 }
3342
3343 return DAG.getNode(ISD::TRUNCATE, SL, VT, SrcElt);
3344 }
3345 }
3346 }
3347 }
3348
3349 // Partially shrink 64-bit shifts to 32-bit if reduced to 16-bit.
3350 //
3351 // i16 (trunc (srl i64:x, K)), K <= 16 ->
3352 // i16 (trunc (srl (i32 (trunc x), K)))
3353 if (VT.getScalarSizeInBits() < 32) {
3354 EVT SrcVT = Src.getValueType();
3355 if (SrcVT.getScalarSizeInBits() > 32 &&
3356 (Src.getOpcode() == ISD::SRL ||
3357 Src.getOpcode() == ISD::SRA ||
3358 Src.getOpcode() == ISD::SHL)) {
3359 SDValue Amt = Src.getOperand(1);
3360 KnownBits Known = DAG.computeKnownBits(Amt);
3361 unsigned Size = VT.getScalarSizeInBits();
3362 if ((Known.isConstant() && Known.getConstant().ule(Size)) ||
3363 (Known.getBitWidth() - Known.countMinLeadingZeros() <= Log2_32(Size))) {
3364 EVT MidVT = VT.isVector() ?
3365 EVT::getVectorVT(*DAG.getContext(), MVT::i32,
3366 VT.getVectorNumElements()) : MVT::i32;
3367
3368 EVT NewShiftVT = getShiftAmountTy(MidVT, DAG.getDataLayout());
3369 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, SL, MidVT,
3370 Src.getOperand(0));
3371 DCI.AddToWorklist(Trunc.getNode());
3372
3373 if (Amt.getValueType() != NewShiftVT) {
3374 Amt = DAG.getZExtOrTrunc(Amt, SL, NewShiftVT);
3375 DCI.AddToWorklist(Amt.getNode());
3376 }
3377
3378 SDValue ShrunkShift = DAG.getNode(Src.getOpcode(), SL, MidVT,
3379 Trunc, Amt);
3380 return DAG.getNode(ISD::TRUNCATE, SL, VT, ShrunkShift);
3381 }
3382 }
3383 }
3384
3385 return SDValue();
3386}
3387
3388// We need to specifically handle i64 mul here to avoid unnecessary conversion
3389// instructions. If we only match on the legalized i64 mul expansion,
3390// SimplifyDemandedBits will be unable to remove them because there will be
3391// multiple uses due to the separate mul + mulh[su].
3392static SDValue getMul24(SelectionDAG &DAG, const SDLoc &SL,
3393 SDValue N0, SDValue N1, unsigned Size, bool Signed) {
3394 if (Size <= 32) {
3395 unsigned MulOpc = Signed ? AMDGPUISD::MUL_I24 : AMDGPUISD::MUL_U24;
3396 return DAG.getNode(MulOpc, SL, MVT::i32, N0, N1);
3397 }
3398
3399 unsigned MulLoOpc = Signed ? AMDGPUISD::MUL_I24 : AMDGPUISD::MUL_U24;
3400 unsigned MulHiOpc = Signed ? AMDGPUISD::MULHI_I24 : AMDGPUISD::MULHI_U24;
3401
3402 SDValue MulLo = DAG.getNode(MulLoOpc, SL, MVT::i32, N0, N1);
3403 SDValue MulHi = DAG.getNode(MulHiOpc, SL, MVT::i32, N0, N1);
3404
3405 return DAG.getNode(ISD::BUILD_PAIR, SL, MVT::i64, MulLo, MulHi);
3406}
3407
3408SDValue AMDGPUTargetLowering::performMulCombine(SDNode *N,
3409 DAGCombinerInfo &DCI) const {
3410 EVT VT = N->getValueType(0);
3411
3412 // Don't generate 24-bit multiplies on values that are in SGPRs, since
3413 // we only have a 32-bit scalar multiply (avoid values being moved to VGPRs
3414 // unnecessarily). isDivergent() is used as an approximation of whether the
3415 // value is in an SGPR.
3416 if (!N->isDivergent())
3417 return SDValue();
3418
3419 unsigned Size = VT.getSizeInBits();
3420 if (VT.isVector() || Size > 64)
3421 return SDValue();
3422
3423 // There are i16 integer mul/mad.
3424 if (Subtarget->has16BitInsts() && VT.getScalarType().bitsLE(MVT::i16))
3425 return SDValue();
3426
3427 SelectionDAG &DAG = DCI.DAG;
3428 SDLoc DL(N);
3429
3430 SDValue N0 = N->getOperand(0);
3431 SDValue N1 = N->getOperand(1);
3432
3433 // SimplifyDemandedBits has the annoying habit of turning useful zero_extends
3434 // in the source into any_extends if the result of the mul is truncated. Since
3435 // we can assume the high bits are whatever we want, use the underlying value
3436 // to avoid the unknown high bits from interfering.
3437 if (N0.getOpcode() == ISD::ANY_EXTEND)
3438 N0 = N0.getOperand(0);
3439
3440 if (N1.getOpcode() == ISD::ANY_EXTEND)
3441 N1 = N1.getOperand(0);
3442
3443 SDValue Mul;
3444
3445 if (Subtarget->hasMulU24() && isU24(N0, DAG) && isU24(N1, DAG)) {
3446 N0 = DAG.getZExtOrTrunc(N0, DL, MVT::i32);
3447 N1 = DAG.getZExtOrTrunc(N1, DL, MVT::i32);
3448 Mul = getMul24(DAG, DL, N0, N1, Size, false);
3449 } else if (Subtarget->hasMulI24() && isI24(N0, DAG) && isI24(N1, DAG)) {
3450 N0 = DAG.getSExtOrTrunc(N0, DL, MVT::i32);
3451 N1 = DAG.getSExtOrTrunc(N1, DL, MVT::i32);
3452 Mul = getMul24(DAG, DL, N0, N1, Size, true);
3453 } else {
3454 return SDValue();
3455 }
3456
3457 // We need to use sext even for MUL_U24, because MUL_U24 is used
3458 // for signed multiply of 8 and 16-bit types.
3459 return DAG.getSExtOrTrunc(Mul, DL, VT);
3460}
3461
3462SDValue AMDGPUTargetLowering::performMulhsCombine(SDNode *N,
3463 DAGCombinerInfo &DCI) const {
3464 EVT VT = N->getValueType(0);
3465
3466 if (!Subtarget->hasMulI24() || VT.isVector())
3467 return SDValue();
3468
3469 // Don't generate 24-bit multiplies on values that are in SGPRs, since
3470 // we only have a 32-bit scalar multiply (avoid values being moved to VGPRs
3471 // unnecessarily). isDivergent() is used as an approximation of whether the
3472 // value is in an SGPR.
3473 // This doesn't apply if no s_mul_hi is available (since we'll end up with a
3474 // valu op anyway)
3475 if (Subtarget->hasSMulHi() && !N->isDivergent())
3476 return SDValue();
3477
3478 SelectionDAG &DAG = DCI.DAG;
3479 SDLoc DL(N);
3480
3481 SDValue N0 = N->getOperand(0);
3482 SDValue N1 = N->getOperand(1);
3483
3484 if (!isI24(N0, DAG) || !isI24(N1, DAG))
3485 return SDValue();
3486
3487 N0 = DAG.getSExtOrTrunc(N0, DL, MVT::i32);
3488 N1 = DAG.getSExtOrTrunc(N1, DL, MVT::i32);
3489
3490 SDValue Mulhi = DAG.getNode(AMDGPUISD::MULHI_I24, DL, MVT::i32, N0, N1);
3491 DCI.AddToWorklist(Mulhi.getNode());
3492 return DAG.getSExtOrTrunc(Mulhi, DL, VT);
3493}
3494
3495SDValue AMDGPUTargetLowering::performMulhuCombine(SDNode *N,
3496 DAGCombinerInfo &DCI) const {
3497 EVT VT = N->getValueType(0);
3498
3499 if (!Subtarget->hasMulU24() || VT.isVector() || VT.getSizeInBits() > 32)
3500 return SDValue();
3501
3502 // Don't generate 24-bit multiplies on values that are in SGPRs, since
3503 // we only have a 32-bit scalar multiply (avoid values being moved to VGPRs
3504 // unnecessarily). isDivergent() is used as an approximation of whether the
3505 // value is in an SGPR.
3506 // This doesn't apply if no s_mul_hi is available (since we'll end up with a
3507 // valu op anyway)
3508 if (Subtarget->hasSMulHi() && !N->isDivergent())
3509 return SDValue();
3510
3511 SelectionDAG &DAG = DCI.DAG;
3512 SDLoc DL(N);
3513
3514 SDValue N0 = N->getOperand(0);
3515 SDValue N1 = N->getOperand(1);
3516
3517 if (!isU24(N0, DAG) || !isU24(N1, DAG))
3518 return SDValue();
3519
3520 N0 = DAG.getZExtOrTrunc(N0, DL, MVT::i32);
3521 N1 = DAG.getZExtOrTrunc(N1, DL, MVT::i32);
3522
3523 SDValue Mulhi = DAG.getNode(AMDGPUISD::MULHI_U24, DL, MVT::i32, N0, N1);
3524 DCI.AddToWorklist(Mulhi.getNode());
3525 return DAG.getZExtOrTrunc(Mulhi, DL, VT);
3526}
3527
3528static bool isNegativeOne(SDValue Val) {
3529 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Val))
3530 return C->isAllOnes();
3531 return false;
3532}
3533
3534SDValue AMDGPUTargetLowering::getFFBX_U32(SelectionDAG &DAG,
3535 SDValue Op,
3536 const SDLoc &DL,
3537 unsigned Opc) const {
3538 EVT VT = Op.getValueType();
3539 EVT LegalVT = getTypeToTransformTo(*DAG.getContext(), VT);
3540 if (LegalVT != MVT::i32 && (Subtarget->has16BitInsts() &&
3541 LegalVT != MVT::i16))
3542 return SDValue();
3543
3544 if (VT != MVT::i32)
3545 Op = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, Op);
3546
3547 SDValue FFBX = DAG.getNode(Opc, DL, MVT::i32, Op);
3548 if (VT != MVT::i32)
3549 FFBX = DAG.getNode(ISD::TRUNCATE, DL, VT, FFBX);
3550
3551 return FFBX;
3552}
3553
3554// The native instructions return -1 on 0 input. Optimize out a select that
3555// produces -1 on 0.
3556//
3557// TODO: If zero is not undef, we could also do this if the output is compared
3558// against the bitwidth.
3559//
3560// TODO: Should probably combine against FFBH_U32 instead of ctlz directly.
3561SDValue AMDGPUTargetLowering::performCtlz_CttzCombine(const SDLoc &SL, SDValue Cond,
3562 SDValue LHS, SDValue RHS,
3563 DAGCombinerInfo &DCI) const {
3564 ConstantSDNode *CmpRhs = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
3565 if (!CmpRhs || !CmpRhs->isZero())
3566 return SDValue();
3567
3568 SelectionDAG &DAG = DCI.DAG;
3569 ISD::CondCode CCOpcode = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
3570 SDValue CmpLHS = Cond.getOperand(0);
3571
3572 // select (setcc x, 0, eq), -1, (ctlz_zero_undef x) -> ffbh_u32 x
3573 // select (setcc x, 0, eq), -1, (cttz_zero_undef x) -> ffbl_u32 x
3574 if (CCOpcode == ISD::SETEQ &&
3575 (isCtlzOpc(RHS.getOpcode()) || isCttzOpc(RHS.getOpcode())) &&
3576 RHS.getOperand(0) == CmpLHS && isNegativeOne(LHS)) {
3577 unsigned Opc =
3578 isCttzOpc(RHS.getOpcode()) ? AMDGPUISD::FFBL_B32 : AMDGPUISD::FFBH_U32;
3579 return getFFBX_U32(DAG, CmpLHS, SL, Opc);
3580 }
3581
3582 // select (setcc x, 0, ne), (ctlz_zero_undef x), -1 -> ffbh_u32 x
3583 // select (setcc x, 0, ne), (cttz_zero_undef x), -1 -> ffbl_u32 x
3584 if (CCOpcode == ISD::SETNE &&
3585 (isCtlzOpc(LHS.getOpcode()) || isCttzOpc(LHS.getOpcode())) &&
3586 LHS.getOperand(0) == CmpLHS && isNegativeOne(RHS)) {
3587 unsigned Opc =
3588 isCttzOpc(LHS.getOpcode()) ? AMDGPUISD::FFBL_B32 : AMDGPUISD::FFBH_U32;
3589
3590 return getFFBX_U32(DAG, CmpLHS, SL, Opc);
3591 }
3592
3593 return SDValue();
3594}
3595
3596static SDValue distributeOpThroughSelect(TargetLowering::DAGCombinerInfo &DCI,
3597 unsigned Op,
3598 const SDLoc &SL,
3599 SDValue Cond,
3600 SDValue N1,
3601 SDValue N2) {
3602 SelectionDAG &DAG = DCI.DAG;
3603 EVT VT = N1.getValueType();
3604
3605 SDValue NewSelect = DAG.getNode(ISD::SELECT, SL, VT, Cond,
3606 N1.getOperand(0), N2.getOperand(0));
3607 DCI.AddToWorklist(NewSelect.getNode());
3608 return DAG.getNode(Op, SL, VT, NewSelect);
3609}
3610
3611// Pull a free FP operation out of a select so it may fold into uses.
3612//
3613// select c, (fneg x), (fneg y) -> fneg (select c, x, y)
3614// select c, (fneg x), k -> fneg (select c, x, (fneg k))
3615//
3616// select c, (fabs x), (fabs y) -> fabs (select c, x, y)
3617// select c, (fabs x), +k -> fabs (select c, x, k)
3618static SDValue foldFreeOpFromSelect(TargetLowering::DAGCombinerInfo &DCI,
3619 SDValue N) {
3620 SelectionDAG &DAG = DCI.DAG;
3621 SDValue Cond = N.getOperand(0);
3622 SDValue LHS = N.getOperand(1);
3623 SDValue RHS = N.getOperand(2);
3624
3625 EVT VT = N.getValueType();
3626 if ((LHS.getOpcode() == ISD::FABS && RHS.getOpcode() == ISD::FABS) ||
3627 (LHS.getOpcode() == ISD::FNEG && RHS.getOpcode() == ISD::FNEG)) {
3628 return distributeOpThroughSelect(DCI, LHS.getOpcode(),
3629 SDLoc(N), Cond, LHS, RHS);
3630 }
3631
3632 bool Inv = false;
3633 if (RHS.getOpcode() == ISD::FABS || RHS.getOpcode() == ISD::FNEG) {
3634 std::swap(LHS, RHS);
3635 Inv = true;
3636 }
3637
3638 // TODO: Support vector constants.
3639 ConstantFPSDNode *CRHS = dyn_cast<ConstantFPSDNode>(RHS);
3640 if ((LHS.getOpcode() == ISD::FNEG || LHS.getOpcode() == ISD::FABS) && CRHS) {
3641 SDLoc SL(N);
3642 // If one side is an fneg/fabs and the other is a constant, we can push the
3643 // fneg/fabs down. If it's an fabs, the constant needs to be non-negative.
3644 SDValue NewLHS = LHS.getOperand(0);
3645 SDValue NewRHS = RHS;
3646
3647 // Careful: if the neg can be folded up, don't try to pull it back down.
3648 bool ShouldFoldNeg = true;
3649
3650 if (NewLHS.hasOneUse()) {
3651 unsigned Opc = NewLHS.getOpcode();
3652 if (LHS.getOpcode() == ISD::FNEG && fnegFoldsIntoOp(Opc))
3653 ShouldFoldNeg = false;
3654 if (LHS.getOpcode() == ISD::FABS && Opc == ISD::FMUL)
3655 ShouldFoldNeg = false;
3656 }
3657
3658 if (ShouldFoldNeg) {
3659 if (LHS.getOpcode() == ISD::FNEG)
3660 NewRHS = DAG.getNode(ISD::FNEG, SL, VT, RHS);
3661 else if (CRHS->isNegative())
3662 return SDValue();
3663
3664 if (Inv)
3665 std::swap(NewLHS, NewRHS);
3666
3667 SDValue NewSelect = DAG.getNode(ISD::SELECT, SL, VT,
3668 Cond, NewLHS, NewRHS);
3669 DCI.AddToWorklist(NewSelect.getNode());
3670 return DAG.getNode(LHS.getOpcode(), SL, VT, NewSelect);
3671 }
3672 }
3673
3674 return SDValue();
3675}
3676
3677
3678SDValue AMDGPUTargetLowering::performSelectCombine(SDNode *N,
3679 DAGCombinerInfo &DCI) const {
3680 if (SDValue Folded = foldFreeOpFromSelect(DCI, SDValue(N, 0)))
3681 return Folded;
3682
3683 SDValue Cond = N->getOperand(0);
3684 if (Cond.getOpcode() != ISD::SETCC)
3685 return SDValue();
3686
3687 EVT VT = N->getValueType(0);
3688 SDValue LHS = Cond.getOperand(0);
3689 SDValue RHS = Cond.getOperand(1);
3690 SDValue CC = Cond.getOperand(2);
3691
3692 SDValue True = N->getOperand(1);
3693 SDValue False = N->getOperand(2);
3694
3695 if (Cond.hasOneUse()) { // TODO: Look for multiple select uses.
3696 SelectionDAG &DAG = DCI.DAG;
3697 if (DAG.isConstantValueOfAnyType(True) &&
3698 !DAG.isConstantValueOfAnyType(False)) {
3699 // Swap cmp + select pair to move constant to false input.
3700 // This will allow using VOPC cndmasks more often.
3701 // select (setcc x, y), k, x -> select (setccinv x, y), x, k
3702
3703 SDLoc SL(N);
3704 ISD::CondCode NewCC =
3705 getSetCCInverse(cast<CondCodeSDNode>(CC)->get(), LHS.getValueType());
3706
3707 SDValue NewCond = DAG.getSetCC(SL, Cond.getValueType(), LHS, RHS, NewCC);
3708 return DAG.getNode(ISD::SELECT, SL, VT, NewCond, False, True);
3709 }
3710
3711 if (VT == MVT::f32 && Subtarget->hasFminFmaxLegacy()) {
3712 SDValue MinMax
3713 = combineFMinMaxLegacy(SDLoc(N), VT, LHS, RHS, True, False, CC, DCI);
3714 // Revisit this node so we can catch min3/max3/med3 patterns.
3715 //DCI.AddToWorklist(MinMax.getNode());
3716 return MinMax;
3717 }
3718 }
3719
3720 // There's no reason to not do this if the condition has other uses.
3721 return performCtlz_CttzCombine(SDLoc(N), Cond, True, False, DCI);
3722}
3723
3724static bool isInv2Pi(const APFloat &APF) {
3725 static const APFloat KF16(APFloat::IEEEhalf(), APInt(16, 0x3118));
3726 static const APFloat KF32(APFloat::IEEEsingle(), APInt(32, 0x3e22f983));
3727 static const APFloat KF64(APFloat::IEEEdouble(), APInt(64, 0x3fc45f306dc9c882));
3728
3729 return APF.bitwiseIsEqual(KF16) ||
3730 APF.bitwiseIsEqual(KF32) ||
3731 APF.bitwiseIsEqual(KF64);
3732}
3733
3734// 0 and 1.0 / (0.5 * pi) do not have inline immmediates, so there is an
3735// additional cost to negate them.
3736bool AMDGPUTargetLowering::isConstantCostlierToNegate(SDValue N) const {
3737 if (const ConstantFPSDNode *C = isConstOrConstSplatFP(N)) {
3738 if (C->isZero() && !C->isNegative())
3739 return true;
3740
3741 if (Subtarget->hasInv2PiInlineImm() && isInv2Pi(C->getValueAPF()))
3742 return true;
3743 }
3744
3745 return false;
3746}
3747
3748static unsigned inverseMinMax(unsigned Opc) {
3749 switch (Opc) {
3750 case ISD::FMAXNUM:
3751 return ISD::FMINNUM;
3752 case ISD::FMINNUM:
3753 return ISD::FMAXNUM;
3754 case ISD::FMAXNUM_IEEE:
3755 return ISD::FMINNUM_IEEE;
3756 case ISD::FMINNUM_IEEE:
3757 return ISD::FMAXNUM_IEEE;
3758 case AMDGPUISD::FMAX_LEGACY:
3759 return AMDGPUISD::FMIN_LEGACY;
3760 case AMDGPUISD::FMIN_LEGACY:
3761 return AMDGPUISD::FMAX_LEGACY;
3762 default:
3763 llvm_unreachable("invalid min/max opcode")::llvm::llvm_unreachable_internal("invalid min/max opcode", "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp"
, 3763)
;
3764 }
3765}
3766
3767SDValue AMDGPUTargetLowering::performFNegCombine(SDNode *N,
3768 DAGCombinerInfo &DCI) const {
3769 SelectionDAG &DAG = DCI.DAG;
3770 SDValue N0 = N->getOperand(0);
3771 EVT VT = N->getValueType(0);
3772
3773 unsigned Opc = N0.getOpcode();
3774
3775 // If the input has multiple uses and we can either fold the negate down, or
3776 // the other uses cannot, give up. This both prevents unprofitable
3777 // transformations and infinite loops: we won't repeatedly try to fold around
3778 // a negate that has no 'good' form.
3779 if (N0.hasOneUse()) {
3780 // This may be able to fold into the source, but at a code size cost. Don't
3781 // fold if the fold into the user is free.
3782 if (allUsesHaveSourceMods(N, 0))
3783 return SDValue();
3784 } else {
3785 if (fnegFoldsIntoOp(Opc) &&
3786 (allUsesHaveSourceMods(N) || !allUsesHaveSourceMods(N0.getNode())))
3787 return SDValue();
3788 }
3789
3790 SDLoc SL(N);
3791 switch (Opc) {
3792 case ISD::FADD: {
3793 if (!mayIgnoreSignedZero(N0))
3794 return SDValue();
3795
3796 // (fneg (fadd x, y)) -> (fadd (fneg x), (fneg y))
3797 SDValue LHS = N0.getOperand(0);
3798 SDValue RHS = N0.getOperand(1);
3799
3800 if (LHS.getOpcode() != ISD::FNEG)
3801 LHS = DAG.getNode(ISD::FNEG, SL, VT, LHS);
3802 else
3803 LHS = LHS.getOperand(0);
3804
3805 if (RHS.getOpcode() != ISD::FNEG)
3806 RHS = DAG.getNode(ISD::FNEG, SL, VT, RHS);
3807 else
3808 RHS = RHS.getOperand(0);
3809
3810 SDValue Res = DAG.getNode(ISD::FADD, SL, VT, LHS, RHS, N0->getFlags());
3811 if (Res.getOpcode() != ISD::FADD)
3812 return SDValue(); // Op got folded away.
3813 if (!N0.hasOneUse())
3814 DAG.ReplaceAllUsesWith(N0, DAG.getNode(ISD::FNEG, SL, VT, Res));
3815 return Res;
3816 }
3817 case ISD::FMUL:
3818 case AMDGPUISD::FMUL_LEGACY: {
3819 // (fneg (fmul x, y)) -> (fmul x, (fneg y))
3820 // (fneg (fmul_legacy x, y)) -> (fmul_legacy x, (fneg y))
3821 SDValue LHS = N0.getOperand(0);
3822 SDValue RHS = N0.getOperand(1);
3823
3824 if (LHS.getOpcode() == ISD::FNEG)
3825 LHS = LHS.getOperand(0);
3826 else if (RHS.getOpcode() == ISD::FNEG)
3827 RHS = RHS.getOperand(0);
3828 else
3829 RHS = DAG.getNode(ISD::FNEG, SL, VT, RHS);
3830
3831 SDValue Res = DAG.getNode(Opc, SL, VT, LHS, RHS, N0->getFlags());
3832 if (Res.getOpcode() != Opc)
3833 return SDValue(); // Op got folded away.
3834 if (!N0.hasOneUse())
3835 DAG.ReplaceAllUsesWith(N0, DAG.getNode(ISD::FNEG, SL, VT, Res));
3836 return Res;
3837 }
3838 case ISD::FMA:
3839 case ISD::FMAD: {
3840 // TODO: handle llvm.amdgcn.fma.legacy
3841 if (!mayIgnoreSignedZero(N0))
3842 return SDValue();
3843
3844 // (fneg (fma x, y, z)) -> (fma x, (fneg y), (fneg z))
3845 SDValue LHS = N0.getOperand(0);
3846 SDValue MHS = N0.getOperand(1);
3847 SDValue RHS = N0.getOperand(2);
3848
3849 if (LHS.getOpcode() == ISD::FNEG)
3850 LHS = LHS.getOperand(0);
3851 else if (MHS.getOpcode() == ISD::FNEG)
3852 MHS = MHS.getOperand(0);
3853 else
3854 MHS = DAG.getNode(ISD::FNEG, SL, VT, MHS);
3855
3856 if (RHS.getOpcode() != ISD::FNEG)
3857 RHS = DAG.getNode(ISD::FNEG, SL, VT, RHS);
3858 else
3859 RHS = RHS.getOperand(0);
3860
3861 SDValue Res = DAG.getNode(Opc, SL, VT, LHS, MHS, RHS);
3862 if (Res.getOpcode() != Opc)
3863 return SDValue(); // Op got folded away.
3864 if (!N0.hasOneUse())
3865 DAG.ReplaceAllUsesWith(N0, DAG.getNode(ISD::FNEG, SL, VT, Res));
3866 return Res;
3867 }
3868 case ISD::FMAXNUM:
3869 case ISD::FMINNUM:
3870 case ISD::FMAXNUM_IEEE:
3871 case ISD::FMINNUM_IEEE:
3872 case AMDGPUISD::FMAX_LEGACY:
3873 case AMDGPUISD::FMIN_LEGACY: {
3874 // fneg (fmaxnum x, y) -> fminnum (fneg x), (fneg y)
3875 // fneg (fminnum x, y) -> fmaxnum (fneg x), (fneg y)
3876 // fneg (fmax_legacy x, y) -> fmin_legacy (fneg x), (fneg y)
3877 // fneg (fmin_legacy x, y) -> fmax_legacy (fneg x), (fneg y)
3878
3879 SDValue LHS = N0.getOperand(0);
3880 SDValue RHS = N0.getOperand(1);
3881
3882 // 0 doesn't have a negated inline immediate.
3883 // TODO: This constant check should be generalized to other operations.
3884 if (isConstantCostlierToNegate(RHS))
3885 return SDValue();
3886
3887 SDValue NegLHS = DAG.getNode(ISD::FNEG, SL, VT, LHS);
3888 SDValue NegRHS = DAG.getNode(ISD::FNEG, SL, VT, RHS);
3889 unsigned Opposite = inverseMinMax(Opc);
3890
3891 SDValue Res = DAG.getNode(Opposite, SL, VT, NegLHS, NegRHS, N0->getFlags());
3892 if (Res.getOpcode() != Opposite)
3893 return SDValue(); // Op got folded away.
3894 if (!N0.hasOneUse())
3895 DAG.ReplaceAllUsesWith(N0, DAG.getNode(ISD::FNEG, SL, VT, Res));
3896 return Res;
3897 }
3898 case AMDGPUISD::FMED3: {
3899 SDValue Ops[3];
3900 for (unsigned I = 0; I < 3; ++I)
3901 Ops[I] = DAG.getNode(ISD::FNEG, SL, VT, N0->getOperand(I), N0->getFlags());
3902
3903 SDValue Res = DAG.getNode(AMDGPUISD::FMED3, SL, VT, Ops, N0->getFlags());
3904 if (Res.getOpcode() != AMDGPUISD::FMED3)
3905 return SDValue(); // Op got folded away.
3906
3907 if (!N0.hasOneUse()) {
3908 SDValue Neg = DAG.getNode(ISD::FNEG, SL, VT, Res);
3909 DAG.ReplaceAllUsesWith(N0, Neg);
3910
3911 for (SDNode *U : Neg->uses())
3912 DCI.AddToWorklist(U);
3913 }
3914
3915 return Res;
3916 }
3917 case ISD::FP_EXTEND:
3918 case ISD::FTRUNC:
3919 case ISD::FRINT:
3920 case ISD::FNEARBYINT: // XXX - Should fround be handled?
3921 case ISD::FSIN:
3922 case ISD::FCANONICALIZE:
3923 case AMDGPUISD::RCP:
3924 case AMDGPUISD::RCP_LEGACY:
3925 case AMDGPUISD::RCP_IFLAG:
3926 case AMDGPUISD::SIN_HW: {
3927 SDValue CvtSrc = N0.getOperand(0);
3928 if (CvtSrc.getOpcode() == ISD::FNEG) {
3929 // (fneg (fp_extend (fneg x))) -> (fp_extend x)
3930 // (fneg (rcp (fneg x))) -> (rcp x)
3931 return DAG.getNode(Opc, SL, VT, CvtSrc.getOperand(0));
3932 }
3933
3934 if (!N0.hasOneUse())
3935 return SDValue();
3936
3937 // (fneg (fp_extend x)) -> (fp_extend (fneg x))
3938 // (fneg (rcp x)) -> (rcp (fneg x))
3939 SDValue Neg = DAG.getNode(ISD::FNEG, SL, CvtSrc.getValueType(), CvtSrc);
3940 return DAG.getNode(Opc, SL, VT, Neg, N0->getFlags());
3941 }
3942 case ISD::FP_ROUND: {
3943 SDValue CvtSrc = N0.getOperand(0);
3944
3945 if (CvtSrc.getOpcode() == ISD::FNEG) {
3946 // (fneg (fp_round (fneg x))) -> (fp_round x)
3947 return DAG.getNode(ISD::FP_ROUND, SL, VT,
3948 CvtSrc.getOperand(0), N0.getOperand(1));
3949 }
3950
3951 if (!N0.hasOneUse())
3952 return SDValue();
3953
3954 // (fneg (fp_round x)) -> (fp_round (fneg x))
3955 SDValue Neg = DAG.getNode(ISD::FNEG, SL, CvtSrc.getValueType(), CvtSrc);
3956 return DAG.getNode(ISD::FP_ROUND, SL, VT, Neg, N0.getOperand(1));
3957 }
3958 case ISD::FP16_TO_FP: {
3959 // v_cvt_f32_f16 supports source modifiers on pre-VI targets without legal
3960 // f16, but legalization of f16 fneg ends up pulling it out of the source.
3961 // Put the fneg back as a legal source operation that can be matched later.
3962 SDLoc SL(N);
3963
3964 SDValue Src = N0.getOperand(0);
3965 EVT SrcVT = Src.getValueType();
3966
3967 // fneg (fp16_to_fp x) -> fp16_to_fp (xor x, 0x8000)
3968 SDValue IntFNeg = DAG.getNode(ISD::XOR, SL, SrcVT, Src,
3969 DAG.getConstant(0x8000, SL, SrcVT));
3970 return DAG.getNode(ISD::FP16_TO_FP, SL, N->getValueType(0), IntFNeg);
3971 }
3972 default:
3973 return SDValue();
3974 }
3975}
3976
3977SDValue AMDGPUTargetLowering::performFAbsCombine(SDNode *N,
3978 DAGCombinerInfo &DCI) const {
3979 SelectionDAG &DAG = DCI.DAG;
3980 SDValue N0 = N->getOperand(0);
3981
3982 if (!N0.hasOneUse())
3983 return SDValue();
3984
3985 switch (N0.getOpcode()) {
3986 case ISD::FP16_TO_FP: {
3987 assert(!Subtarget->has16BitInsts() && "should only see if f16 is illegal")(static_cast <bool> (!Subtarget->has16BitInsts() &&
"should only see if f16 is illegal") ? void (0) : __assert_fail
("!Subtarget->has16BitInsts() && \"should only see if f16 is illegal\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp"
, 3987, __extension__ __PRETTY_FUNCTION__))
;
3988 SDLoc SL(N);
3989 SDValue Src = N0.getOperand(0);
3990 EVT SrcVT = Src.getValueType();
3991
3992 // fabs (fp16_to_fp x) -> fp16_to_fp (and x, 0x7fff)
3993 SDValue IntFAbs = DAG.getNode(ISD::AND, SL, SrcVT, Src,
3994 DAG.getConstant(0x7fff, SL, SrcVT));
3995 return DAG.getNode(ISD::FP16_TO_FP, SL, N->getValueType(0), IntFAbs);
3996 }
3997 default:
3998 return SDValue();
3999 }
4000}
4001
4002SDValue AMDGPUTargetLowering::performRcpCombine(SDNode *N,
4003 DAGCombinerInfo &DCI) const {
4004 const auto *CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0));
4005 if (!CFP)
4006 return SDValue();
4007
4008 // XXX - Should this flush denormals?
4009 const APFloat &Val = CFP->getValueAPF();
4010 APFloat One(Val.getSemantics(), "1.0");
4011 return DCI.DAG.getConstantFP(One / Val, SDLoc(N), N->getValueType(0));
4012}
4013
4014SDValue AMDGPUTargetLowering::PerformDAGCombine(SDNode *N,
4015 DAGCombinerInfo &DCI) const {
4016 SelectionDAG &DAG = DCI.DAG;
4017 SDLoc DL(N);
4018
4019 switch(N->getOpcode()) {
1
Control jumps to 'case BFE_I32:' at line 4118
4020 default:
4021 break;
4022 case ISD::BITCAST: {
4023 EVT DestVT = N->getValueType(0);
4024
4025 // Push casts through vector builds. This helps avoid emitting a large
4026 // number of copies when materializing floating point vector constants.
4027 //
4028 // vNt1 bitcast (vNt0 (build_vector t0:x, t0:y)) =>
4029 // vnt1 = build_vector (t1 (bitcast t0:x)), (t1 (bitcast t0:y))
4030 if (DestVT.isVector()) {
4031 SDValue Src = N->getOperand(0);
4032 if (Src.getOpcode() == ISD::BUILD_VECTOR) {
4033 EVT SrcVT = Src.getValueType();
4034 unsigned NElts = DestVT.getVectorNumElements();
4035
4036 if (SrcVT.getVectorNumElements() == NElts) {
4037 EVT DestEltVT = DestVT.getVectorElementType();
4038
4039 SmallVector<SDValue, 8> CastedElts;
4040 SDLoc SL(N);
4041 for (unsigned I = 0, E = SrcVT.getVectorNumElements(); I != E; ++I) {
4042 SDValue Elt = Src.getOperand(I);
4043 CastedElts.push_back(DAG.getNode(ISD::BITCAST, DL, DestEltVT, Elt));
4044 }
4045
4046 return DAG.getBuildVector(DestVT, SL, CastedElts);
4047 }
4048 }
4049 }
4050
4051 if (DestVT.getSizeInBits() != 64 || !DestVT.isVector())
4052 break;
4053
4054 // Fold bitcasts of constants.
4055 //
4056 // v2i32 (bitcast i64:k) -> build_vector lo_32(k), hi_32(k)
4057 // TODO: Generalize and move to DAGCombiner
4058 SDValue Src = N->getOperand(0);
4059 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Src)) {
4060 SDLoc SL(N);
4061 uint64_t CVal = C->getZExtValue();
4062 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, SL, MVT::v2i32,
4063 DAG.getConstant(Lo_32(CVal), SL, MVT::i32),
4064 DAG.getConstant(Hi_32(CVal), SL, MVT::i32));
4065 return DAG.getNode(ISD::BITCAST, SL, DestVT, BV);
4066 }
4067
4068 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(Src)) {
4069 const APInt &Val = C->getValueAPF().bitcastToAPInt();
4070 SDLoc SL(N);
4071 uint64_t CVal = Val.getZExtValue();
4072 SDValue Vec = DAG.getNode(ISD::BUILD_VECTOR, SL, MVT::v2i32,
4073 DAG.getConstant(Lo_32(CVal), SL, MVT::i32),
4074 DAG.getConstant(Hi_32(CVal), SL, MVT::i32));
4075
4076 return DAG.getNode(ISD::BITCAST, SL, DestVT, Vec);
4077 }
4078
4079 break;
4080 }
4081 case ISD::SHL: {
4082 if (DCI.getDAGCombineLevel() < AfterLegalizeDAG)
4083 break;
4084
4085 return performShlCombine(N, DCI);
4086 }
4087 case ISD::SRL: {
4088 if (DCI.getDAGCombineLevel() < AfterLegalizeDAG)
4089 break;
4090
4091 return performSrlCombine(N, DCI);
4092 }
4093 case ISD::SRA: {
4094 if (DCI.getDAGCombineLevel() < AfterLegalizeDAG)
4095 break;
4096
4097 return performSraCombine(N, DCI);
4098 }
4099 case ISD::TRUNCATE:
4100 return performTruncateCombine(N, DCI);
4101 case ISD::MUL:
4102 return performMulCombine(N, DCI);
4103 case ISD::MULHS:
4104 return performMulhsCombine(N, DCI);
4105 case ISD::MULHU:
4106 return performMulhuCombine(N, DCI);
4107 case AMDGPUISD::MUL_I24:
4108 case AMDGPUISD::MUL_U24:
4109 case AMDGPUISD::MULHI_I24:
4110 case AMDGPUISD::MULHI_U24:
4111 return simplifyMul24(N, DCI);
4112 case ISD::SELECT:
4113 return performSelectCombine(N, DCI);
4114 case ISD::FNEG:
4115 return performFNegCombine(N, DCI);
4116 case ISD::FABS:
4117 return performFAbsCombine(N, DCI);
4118 case AMDGPUISD::BFE_I32:
4119 case AMDGPUISD::BFE_U32: {
4120 assert(!N->getValueType(0).isVector() &&(static_cast <bool> (!N->getValueType(0).isVector() &&
"Vector handling of BFE not implemented") ? void (0) : __assert_fail
("!N->getValueType(0).isVector() && \"Vector handling of BFE not implemented\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp"
, 4121, __extension__ __PRETTY_FUNCTION__))
2
Assuming the condition is true
3
'?' condition is true
4121 "Vector handling of BFE not implemented")(static_cast <bool> (!N->getValueType(0).isVector() &&
"Vector handling of BFE not implemented") ? void (0) : __assert_fail
("!N->getValueType(0).isVector() && \"Vector handling of BFE not implemented\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp"
, 4121, __extension__ __PRETTY_FUNCTION__))
;
4122 ConstantSDNode *Width = dyn_cast<ConstantSDNode>(N->getOperand(2));
4123 if (!Width)
4
Assuming 'Width' is non-null
5
Taking false branch
4124 break;
4125
4126 uint32_t WidthVal = Width->getZExtValue() & 0x1f;
4127 if (WidthVal == 0)
6
Assuming 'WidthVal' is not equal to 0
7
Taking false branch
4128 return DAG.getConstant(0, DL, MVT::i32);
4129
4130 ConstantSDNode *Offset = dyn_cast<ConstantSDNode>(N->getOperand(1));
4131 if (!Offset)
8
Assuming 'Offset' is non-null
9
Taking false branch
4132 break;
4133
4134 SDValue BitsFrom = N->getOperand(0);
10
Value assigned to 'BitsFrom.Node'
4135 uint32_t OffsetVal = Offset->getZExtValue() & 0x1f;
4136
4137 bool Signed = N->getOpcode() == AMDGPUISD::BFE_I32;
4138
4139 if (OffsetVal == 0) {
11
Assuming 'OffsetVal' is not equal to 0
12
Taking false branch
4140 // This is already sign / zero extended, so try to fold away extra BFEs.
4141 unsigned SignBits = Signed ? (32 - WidthVal + 1) : (32 - WidthVal);
4142
4143 unsigned OpSignBits = DAG.ComputeNumSignBits(BitsFrom);
4144 if (OpSignBits >= SignBits)
4145 return BitsFrom;
4146
4147 EVT SmallVT = EVT::getIntegerVT(*DAG.getContext(), WidthVal);
4148 if (Signed) {
4149 // This is a sign_extend_inreg. Replace it to take advantage of existing
4150 // DAG Combines. If not eliminated, we will match back to BFE during
4151 // selection.
4152
4153 // TODO: The sext_inreg of extended types ends, although we can could
4154 // handle them in a single BFE.
4155 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, MVT::i32, BitsFrom,
4156 DAG.getValueType(SmallVT));
4157 }
4158
4159 return DAG.getZeroExtendInReg(BitsFrom, DL, SmallVT);
4160 }
4161
4162 if (ConstantSDNode *CVal = dyn_cast<ConstantSDNode>(BitsFrom)) {
13
Calling 'dyn_cast<llvm::ConstantSDNode, llvm::SDValue>'
28
Returning from 'dyn_cast<llvm::ConstantSDNode, llvm::SDValue>'
29
Assuming 'CVal' is null
4163 if (Signed) {
4164 return constantFoldBFE<int32_t>(DAG,
4165 CVal->getSExtValue(),
4166 OffsetVal,
4167 WidthVal,
4168 DL);
4169 }
4170
4171 return constantFoldBFE<uint32_t>(DAG,
4172 CVal->getZExtValue(),
4173 OffsetVal,
4174 WidthVal,
4175 DL);
4176 }
4177
4178 if ((OffsetVal + WidthVal) >= 32 &&
30
Assuming the condition is false
4179 !(Subtarget->hasSDWA() && OffsetVal == 16 && WidthVal == 16)) {
4180 SDValue ShiftVal = DAG.getConstant(OffsetVal, DL, MVT::i32);
4181 return DAG.getNode(Signed ? ISD::SRA : ISD::SRL, DL, MVT::i32,
4182 BitsFrom, ShiftVal);
4183 }
4184
4185 if (BitsFrom.hasOneUse()) {
31
Calling 'SDValue::hasOneUse'
4186 APInt Demanded = APInt::getBitsSet(32,
4187 OffsetVal,
4188 OffsetVal + WidthVal);
4189
4190 KnownBits Known;
4191 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
4192 !DCI.isBeforeLegalizeOps());
4193 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4194 if (TLI.ShrinkDemandedConstant(BitsFrom, Demanded, TLO) ||
4195 TLI.SimplifyDemandedBits(BitsFrom, Demanded, Known, TLO)) {
4196 DCI.CommitTargetLoweringOpt(TLO);
4197 }
4198 }
4199
4200 break;
4201 }
4202 case ISD::LOAD:
4203 return performLoadCombine(N, DCI);
4204 case ISD::STORE:
4205 return performStoreCombine(N, DCI);
4206 case AMDGPUISD::RCP:
4207 case AMDGPUISD::RCP_IFLAG:
4208 return performRcpCombine(N, DCI);
4209 case ISD::AssertZext:
4210 case ISD::AssertSext:
4211 return performAssertSZExtCombine(N, DCI);
4212 case ISD::INTRINSIC_WO_CHAIN:
4213 return performIntrinsicWOChainCombine(N, DCI);
4214 }
4215 return SDValue();
4216}
4217
4218//===----------------------------------------------------------------------===//
4219// Helper functions
4220//===----------------------------------------------------------------------===//
4221
4222SDValue AMDGPUTargetLowering::CreateLiveInRegister(SelectionDAG &DAG,
4223 const TargetRegisterClass *RC,
4224 Register Reg, EVT VT,
4225 const SDLoc &SL,
4226 bool RawReg) const {
4227 MachineFunction &MF = DAG.getMachineFunction();
4228 MachineRegisterInfo &MRI = MF.getRegInfo();
4229 Register VReg;
4230
4231 if (!MRI.isLiveIn(Reg)) {
4232 VReg = MRI.createVirtualRegister(RC);
4233 MRI.addLiveIn(Reg, VReg);
4234 } else {
4235 VReg = MRI.getLiveInVirtReg(Reg);
4236 }
4237
4238 if (RawReg)
4239 return DAG.getRegister(VReg, VT);
4240
4241 return DAG.getCopyFromReg(DAG.getEntryNode(), SL, VReg, VT);
4242}
4243
4244// This may be called multiple times, and nothing prevents creating multiple
4245// objects at the same offset. See if we already defined this object.
4246static int getOrCreateFixedStackObject(MachineFrameInfo &MFI, unsigned Size,
4247 int64_t Offset) {
4248 for (int I = MFI.getObjectIndexBegin(); I < 0; ++I) {
4249 if (MFI.getObjectOffset(I) == Offset) {
4250 assert(MFI.getObjectSize(I) == Size)(static_cast <bool> (MFI.getObjectSize(I) == Size) ? void
(0) : __assert_fail ("MFI.getObjectSize(I) == Size", "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp"
, 4250, __extension__ __PRETTY_FUNCTION__))
;
4251 return I;
4252 }
4253 }
4254
4255 return MFI.CreateFixedObject(Size, Offset, true);
4256}
4257
4258SDValue AMDGPUTargetLowering::loadStackInputValue(SelectionDAG &DAG,
4259 EVT VT,
4260 const SDLoc &SL,
4261 int64_t Offset) const {
4262 MachineFunction &MF = DAG.getMachineFunction();
4263 MachineFrameInfo &MFI = MF.getFrameInfo();
4264 int FI = getOrCreateFixedStackObject(MFI, VT.getStoreSize(), Offset);
4265
4266 auto SrcPtrInfo = MachinePointerInfo::getStack(MF, Offset);
4267 SDValue Ptr = DAG.getFrameIndex(FI, MVT::i32);
4268
4269 return DAG.getLoad(VT, SL, DAG.getEntryNode(), Ptr, SrcPtrInfo, Align(4),
4270 MachineMemOperand::MODereferenceable |
4271 MachineMemOperand::MOInvariant);
4272}
4273
4274SDValue AMDGPUTargetLowering::storeStackInputValue(SelectionDAG &DAG,
4275 const SDLoc &SL,
4276 SDValue Chain,
4277 SDValue ArgVal,
4278 int64_t Offset) const {
4279 MachineFunction &MF = DAG.getMachineFunction();
4280 MachinePointerInfo DstInfo = MachinePointerInfo::getStack(MF, Offset);
4281 const SIMachineFunctionInfo *Info = MF.getInfo<SIMachineFunctionInfo>();
4282
4283 SDValue Ptr = DAG.getConstant(Offset, SL, MVT::i32);
4284 // Stores to the argument stack area are relative to the stack pointer.
4285 SDValue SP =
4286 DAG.getCopyFromReg(Chain, SL, Info->getStackPtrOffsetReg(), MVT::i32);
4287 Ptr = DAG.getNode(ISD::ADD, SL, MVT::i32, SP, Ptr);
4288 SDValue Store = DAG.getStore(Chain, SL, ArgVal, Ptr, DstInfo, Align(4),
4289 MachineMemOperand::MODereferenceable);
4290 return Store;
4291}
4292
4293SDValue AMDGPUTargetLowering::loadInputValue(SelectionDAG &DAG,
4294 const TargetRegisterClass *RC,
4295 EVT VT, const SDLoc &SL,
4296 const ArgDescriptor &Arg) const {
4297 assert(Arg && "Attempting to load missing argument")(static_cast <bool> (Arg && "Attempting to load missing argument"
) ? void (0) : __assert_fail ("Arg && \"Attempting to load missing argument\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp"
, 4297, __extension__ __PRETTY_FUNCTION__))
;
4298
4299 SDValue V = Arg.isRegister() ?
4300 CreateLiveInRegister(DAG, RC, Arg.getRegister(), VT, SL) :
4301 loadStackInputValue(DAG, VT, SL, Arg.getStackOffset());
4302
4303 if (!Arg.isMasked())
4304 return V;
4305
4306 unsigned Mask = Arg.getMask();
4307 unsigned Shift = countTrailingZeros<unsigned>(Mask);
4308 V = DAG.getNode(ISD::SRL, SL, VT, V,
4309 DAG.getShiftAmountConstant(Shift, VT, SL));
4310 return DAG.getNode(ISD::AND, SL, VT, V,
4311 DAG.getConstant(Mask >> Shift, SL, VT));
4312}
4313
4314uint32_t AMDGPUTargetLowering::getImplicitParameterOffset(
4315 const MachineFunction &MF, const ImplicitParameter Param) const {
4316 const AMDGPUMachineFunction *MFI = MF.getInfo<AMDGPUMachineFunction>();
4317 const AMDGPUSubtarget &ST =
4318 AMDGPUSubtarget::get(getTargetMachine(), MF.getFunction());
4319 unsigned ExplicitArgOffset = ST.getExplicitKernelArgOffset(MF.getFunction());
4320 const Align Alignment = ST.getAlignmentForImplicitArgPtr();
4321 uint64_t ArgOffset = alignTo(MFI->getExplicitKernArgSize(), Alignment) +
4322 ExplicitArgOffset;
4323 switch (Param) {
4324 case GRID_DIM:
4325 return ArgOffset;
4326 case GRID_OFFSET:
4327 return ArgOffset + 4;
4328 }
4329 llvm_unreachable("unexpected implicit parameter type")::llvm::llvm_unreachable_internal("unexpected implicit parameter type"
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp"
, 4329)
;
4330}
4331
4332#define NODE_NAME_CASE(node)case AMDGPUISD::node: return "node"; case AMDGPUISD::node: return #node;
4333
4334const char* AMDGPUTargetLowering::getTargetNodeName(unsigned Opcode) const {
4335 switch ((AMDGPUISD::NodeType)Opcode) {
4336 case AMDGPUISD::FIRST_NUMBER: break;
4337 // AMDIL DAG nodes
4338 NODE_NAME_CASE(UMUL)case AMDGPUISD::UMUL: return "UMUL";;
4339 NODE_NAME_CASE(BRANCH_COND)case AMDGPUISD::BRANCH_COND: return "BRANCH_COND";;
4340
4341 // AMDGPU DAG nodes
4342 NODE_NAME_CASE(IF)case AMDGPUISD::IF: return "IF";
4343 NODE_NAME_CASE(ELSE)case AMDGPUISD::ELSE: return "ELSE";
4344 NODE_NAME_CASE(LOOP)case AMDGPUISD::LOOP: return "LOOP";
4345 NODE_NAME_CASE(CALL)case AMDGPUISD::CALL: return "CALL";
4346 NODE_NAME_CASE(TC_RETURN)case AMDGPUISD::TC_RETURN: return "TC_RETURN";
4347 NODE_NAME_CASE(TRAP)case AMDGPUISD::TRAP: return "TRAP";
4348 NODE_NAME_CASE(RET_FLAG)case AMDGPUISD::RET_FLAG: return "RET_FLAG";
4349 NODE_NAME_CASE(RETURN_TO_EPILOG)case AMDGPUISD::RETURN_TO_EPILOG: return "RETURN_TO_EPILOG";
4350 NODE_NAME_CASE(ENDPGM)case AMDGPUISD::ENDPGM: return "ENDPGM";
4351 NODE_NAME_CASE(DWORDADDR)case AMDGPUISD::DWORDADDR: return "DWORDADDR";
4352 NODE_NAME_CASE(FRACT)case AMDGPUISD::FRACT: return "FRACT";
4353 NODE_NAME_CASE(SETCC)case AMDGPUISD::SETCC: return "SETCC";
4354 NODE_NAME_CASE(SETREG)case AMDGPUISD::SETREG: return "SETREG";
4355 NODE_NAME_CASE(DENORM_MODE)case AMDGPUISD::DENORM_MODE: return "DENORM_MODE";
4356 NODE_NAME_CASE(FMA_W_CHAIN)case AMDGPUISD::FMA_W_CHAIN: return "FMA_W_CHAIN";
4357 NODE_NAME_CASE(FMUL_W_CHAIN)case AMDGPUISD::FMUL_W_CHAIN: return "FMUL_W_CHAIN";
4358 NODE_NAME_CASE(CLAMP)case AMDGPUISD::CLAMP: return "CLAMP";
4359 NODE_NAME_CASE(COS_HW)case AMDGPUISD::COS_HW: return "COS_HW";
4360 NODE_NAME_CASE(SIN_HW)case AMDGPUISD::SIN_HW: return "SIN_HW";
4361 NODE_NAME_CASE(FMAX_LEGACY)case AMDGPUISD::FMAX_LEGACY: return "FMAX_LEGACY";
4362 NODE_NAME_CASE(FMIN_LEGACY)case AMDGPUISD::FMIN_LEGACY: return "FMIN_LEGACY";
4363 NODE_NAME_CASE(FMAX3)case AMDGPUISD::FMAX3: return "FMAX3";
4364 NODE_NAME_CASE(SMAX3)case AMDGPUISD::SMAX3: return "SMAX3";
4365 NODE_NAME_CASE(UMAX3)case AMDGPUISD::UMAX3: return "UMAX3";
4366 NODE_NAME_CASE(FMIN3)case AMDGPUISD::FMIN3: return "FMIN3";
4367 NODE_NAME_CASE(SMIN3)case AMDGPUISD::SMIN3: return "SMIN3";
4368 NODE_NAME_CASE(UMIN3)case AMDGPUISD::UMIN3: return "UMIN3";
4369 NODE_NAME_CASE(FMED3)case AMDGPUISD::FMED3: return "FMED3";
4370 NODE_NAME_CASE(SMED3)case AMDGPUISD::SMED3: return "SMED3";
4371 NODE_NAME_CASE(UMED3)case AMDGPUISD::UMED3: return "UMED3";
4372 NODE_NAME_CASE(FDOT2)case AMDGPUISD::FDOT2: return "FDOT2";
4373 NODE_NAME_CASE(URECIP)case AMDGPUISD::URECIP: return "URECIP";
4374 NODE_NAME_CASE(DIV_SCALE)case AMDGPUISD::DIV_SCALE: return "DIV_SCALE";
4375 NODE_NAME_CASE(DIV_FMAS)case AMDGPUISD::DIV_FMAS: return "DIV_FMAS";
4376 NODE_NAME_CASE(DIV_FIXUP)case AMDGPUISD::DIV_FIXUP: return "DIV_FIXUP";
4377 NODE_NAME_CASE(FMAD_FTZ)case AMDGPUISD::FMAD_FTZ: return "FMAD_FTZ";
4378 NODE_NAME_CASE(RCP)case AMDGPUISD::RCP: return "RCP";
4379 NODE_NAME_CASE(RSQ)case AMDGPUISD::RSQ: return "RSQ";
4380 NODE_NAME_CASE(RCP_LEGACY)case AMDGPUISD::RCP_LEGACY: return "RCP_LEGACY";
4381 NODE_NAME_CASE(RCP_IFLAG)case AMDGPUISD::RCP_IFLAG: return "RCP_IFLAG";
4382 NODE_NAME_CASE(FMUL_LEGACY)case AMDGPUISD::FMUL_LEGACY: return "FMUL_LEGACY";
4383 NODE_NAME_CASE(RSQ_CLAMP)case AMDGPUISD::RSQ_CLAMP: return "RSQ_CLAMP";
4384 NODE_NAME_CASE(LDEXP)case AMDGPUISD::LDEXP: return "LDEXP";
4385 NODE_NAME_CASE(FP_CLASS)case AMDGPUISD::FP_CLASS: return "FP_CLASS";
4386 NODE_NAME_CASE(DOT4)case AMDGPUISD::DOT4: return "DOT4";
4387 NODE_NAME_CASE(CARRY)case AMDGPUISD::CARRY: return "CARRY";
4388 NODE_NAME_CASE(BORROW)case AMDGPUISD::BORROW: return "BORROW";
4389 NODE_NAME_CASE(BFE_U32)case AMDGPUISD::BFE_U32: return "BFE_U32";
4390 NODE_NAME_CASE(BFE_I32)case AMDGPUISD::BFE_I32: return "BFE_I32";
4391 NODE_NAME_CASE(BFI)case AMDGPUISD::BFI: return "BFI";
4392 NODE_NAME_CASE(BFM)case AMDGPUISD::BFM: return "BFM";
4393 NODE_NAME_CASE(FFBH_U32)case AMDGPUISD::FFBH_U32: return "FFBH_U32";
4394 NODE_NAME_CASE(FFBH_I32)case AMDGPUISD::FFBH_I32: return "FFBH_I32";
4395 NODE_NAME_CASE(FFBL_B32)case AMDGPUISD::FFBL_B32: return "FFBL_B32";
4396 NODE_NAME_CASE(MUL_U24)case AMDGPUISD::MUL_U24: return "MUL_U24";
4397 NODE_NAME_CASE(MUL_I24)case AMDGPUISD::MUL_I24: return "MUL_I24";
4398 NODE_NAME_CASE(MULHI_U24)case AMDGPUISD::MULHI_U24: return "MULHI_U24";
4399 NODE_NAME_CASE(MULHI_I24)case AMDGPUISD::MULHI_I24: return "MULHI_I24";
4400 NODE_NAME_CASE(MAD_U24)case AMDGPUISD::MAD_U24: return "MAD_U24";
4401 NODE_NAME_CASE(MAD_I24)case AMDGPUISD::MAD_I24: return "MAD_I24";
4402 NODE_NAME_CASE(MAD_I64_I32)case AMDGPUISD::MAD_I64_I32: return "MAD_I64_I32";
4403 NODE_NAME_CASE(MAD_U64_U32)case AMDGPUISD::MAD_U64_U32: return "MAD_U64_U32";
4404 NODE_NAME_CASE(PERM)case AMDGPUISD::PERM: return "PERM";
4405 NODE_NAME_CASE(TEXTURE_FETCH)case AMDGPUISD::TEXTURE_FETCH: return "TEXTURE_FETCH";
4406 NODE_NAME_CASE(R600_EXPORT)case AMDGPUISD::R600_EXPORT: return "R600_EXPORT";
4407 NODE_NAME_CASE(CONST_ADDRESS)case AMDGPUISD::CONST_ADDRESS: return "CONST_ADDRESS";
4408 NODE_NAME_CASE(REGISTER_LOAD)case AMDGPUISD::REGISTER_LOAD: return "REGISTER_LOAD";
4409 NODE_NAME_CASE(REGISTER_STORE)case AMDGPUISD::REGISTER_STORE: return "REGISTER_STORE";
4410 NODE_NAME_CASE(SAMPLE)case AMDGPUISD::SAMPLE: return "SAMPLE";
4411 NODE_NAME_CASE(SAMPLEB)case AMDGPUISD::SAMPLEB: return "SAMPLEB";
4412 NODE_NAME_CASE(SAMPLED)case AMDGPUISD::SAMPLED: return "SAMPLED";
4413 NODE_NAME_CASE(SAMPLEL)case AMDGPUISD::SAMPLEL: return "SAMPLEL";
4414 NODE_NAME_CASE(CVT_F32_UBYTE0)case AMDGPUISD::CVT_F32_UBYTE0: return "CVT_F32_UBYTE0";
4415 NODE_NAME_CASE(CVT_F32_UBYTE1)case AMDGPUISD::CVT_F32_UBYTE1: return "CVT_F32_UBYTE1";
4416 NODE_NAME_CASE(CVT_F32_UBYTE2)case AMDGPUISD::CVT_F32_UBYTE2: return "CVT_F32_UBYTE2";
4417 NODE_NAME_CASE(CVT_F32_UBYTE3)case AMDGPUISD::CVT_F32_UBYTE3: return "CVT_F32_UBYTE3";
4418 NODE_NAME_CASE(CVT_PKRTZ_F16_F32)case AMDGPUISD::CVT_PKRTZ_F16_F32: return "CVT_PKRTZ_F16_F32"
;
4419 NODE_NAME_CASE(CVT_PKNORM_I16_F32)case AMDGPUISD::CVT_PKNORM_I16_F32: return "CVT_PKNORM_I16_F32"
;
4420 NODE_NAME_CASE(CVT_PKNORM_U16_F32)case AMDGPUISD::CVT_PKNORM_U16_F32: return "CVT_PKNORM_U16_F32"
;
4421 NODE_NAME_CASE(CVT_PK_I16_I32)case AMDGPUISD::CVT_PK_I16_I32: return "CVT_PK_I16_I32";
4422 NODE_NAME_CASE(CVT_PK_U16_U32)case AMDGPUISD::CVT_PK_U16_U32: return "CVT_PK_U16_U32";
4423 NODE_NAME_CASE(FP_TO_FP16)case AMDGPUISD::FP_TO_FP16: return "FP_TO_FP16";
4424 NODE_NAME_CASE(BUILD_VERTICAL_VECTOR)case AMDGPUISD::BUILD_VERTICAL_VECTOR: return "BUILD_VERTICAL_VECTOR"
;
4425 NODE_NAME_CASE(CONST_DATA_PTR)case AMDGPUISD::CONST_DATA_PTR: return "CONST_DATA_PTR";
4426 NODE_NAME_CASE(PC_ADD_REL_OFFSET)case AMDGPUISD::PC_ADD_REL_OFFSET: return "PC_ADD_REL_OFFSET"
;
4427 NODE_NAME_CASE(LDS)case AMDGPUISD::LDS: return "LDS";
4428 NODE_NAME_CASE(DUMMY_CHAIN)case AMDGPUISD::DUMMY_CHAIN: return "DUMMY_CHAIN";
4429 case AMDGPUISD::FIRST_MEM_OPCODE_NUMBER: break;
4430 NODE_NAME_CASE(LOAD_D16_HI)case AMDGPUISD::LOAD_D16_HI: return "LOAD_D16_HI";
4431 NODE_NAME_CASE(LOAD_D16_LO)case AMDGPUISD::LOAD_D16_LO: return "LOAD_D16_LO";
4432 NODE_NAME_CASE(LOAD_D16_HI_I8)case AMDGPUISD::LOAD_D16_HI_I8: return "LOAD_D16_HI_I8";
4433 NODE_NAME_CASE(LOAD_D16_HI_U8)case AMDGPUISD::LOAD_D16_HI_U8: return "LOAD_D16_HI_U8";
4434 NODE_NAME_CASE(LOAD_D16_LO_I8)case AMDGPUISD::LOAD_D16_LO_I8: return "LOAD_D16_LO_I8";
4435 NODE_NAME_CASE(LOAD_D16_LO_U8)case AMDGPUISD::LOAD_D16_LO_U8: return "LOAD_D16_LO_U8";
4436 NODE_NAME_CASE(STORE_MSKOR)case AMDGPUISD::STORE_MSKOR: return "STORE_MSKOR";
4437 NODE_NAME_CASE(LOAD_CONSTANT)case AMDGPUISD::LOAD_CONSTANT: return "LOAD_CONSTANT";
4438 NODE_NAME_CASE(TBUFFER_STORE_FORMAT)case AMDGPUISD::TBUFFER_STORE_FORMAT: return "TBUFFER_STORE_FORMAT"
;
4439 NODE_NAME_CASE(TBUFFER_STORE_FORMAT_D16)case AMDGPUISD::TBUFFER_STORE_FORMAT_D16: return "TBUFFER_STORE_FORMAT_D16"
;
4440 NODE_NAME_CASE(TBUFFER_LOAD_FORMAT)case AMDGPUISD::TBUFFER_LOAD_FORMAT: return "TBUFFER_LOAD_FORMAT"
;
4441 NODE_NAME_CASE(TBUFFER_LOAD_FORMAT_D16)case AMDGPUISD::TBUFFER_LOAD_FORMAT_D16: return "TBUFFER_LOAD_FORMAT_D16"
;
4442 NODE_NAME_CASE(DS_ORDERED_COUNT)case AMDGPUISD::DS_ORDERED_COUNT: return "DS_ORDERED_COUNT";
4443 NODE_NAME_CASE(ATOMIC_CMP_SWAP)case AMDGPUISD::ATOMIC_CMP_SWAP: return "ATOMIC_CMP_SWAP";
4444 NODE_NAME_CASE(ATOMIC_INC)case AMDGPUISD::ATOMIC_INC: return "ATOMIC_INC";
4445 NODE_NAME_CASE(ATOMIC_DEC)case AMDGPUISD::ATOMIC_DEC: return "ATOMIC_DEC";
4446 NODE_NAME_CASE(ATOMIC_LOAD_FMIN)case AMDGPUISD::ATOMIC_LOAD_FMIN: return "ATOMIC_LOAD_FMIN";
4447 NODE_NAME_CASE(ATOMIC_LOAD_FMAX)case AMDGPUISD::ATOMIC_LOAD_FMAX: return "ATOMIC_LOAD_FMAX";
4448 NODE_NAME_CASE(BUFFER_LOAD)case AMDGPUISD::BUFFER_LOAD: return "BUFFER_LOAD";
4449 NODE_NAME_CASE(BUFFER_LOAD_UBYTE)case AMDGPUISD::BUFFER_LOAD_UBYTE: return "BUFFER_LOAD_UBYTE"
;
4450 NODE_NAME_CASE(BUFFER_LOAD_USHORT)case AMDGPUISD::BUFFER_LOAD_USHORT: return "BUFFER_LOAD_USHORT"
;
4451 NODE_NAME_CASE(BUFFER_LOAD_BYTE)case AMDGPUISD::BUFFER_LOAD_BYTE: return "BUFFER_LOAD_BYTE";
4452 NODE_NAME_CASE(BUFFER_LOAD_SHORT)case AMDGPUISD::BUFFER_LOAD_SHORT: return "BUFFER_LOAD_SHORT"
;
4453 NODE_NAME_CASE(BUFFER_LOAD_FORMAT)case AMDGPUISD::BUFFER_LOAD_FORMAT: return "BUFFER_LOAD_FORMAT"
;
4454 NODE_NAME_CASE(BUFFER_LOAD_FORMAT_D16)case AMDGPUISD::BUFFER_LOAD_FORMAT_D16: return "BUFFER_LOAD_FORMAT_D16"
;
4455 NODE_NAME_CASE(SBUFFER_LOAD)case AMDGPUISD::SBUFFER_LOAD: return "SBUFFER_LOAD";
4456 NODE_NAME_CASE(BUFFER_STORE)case AMDGPUISD::BUFFER_STORE: return "BUFFER_STORE";
4457 NODE_NAME_CASE(BUFFER_STORE_BYTE)case AMDGPUISD::BUFFER_STORE_BYTE: return "BUFFER_STORE_BYTE"
;
4458 NODE_NAME_CASE(BUFFER_STORE_SHORT)case AMDGPUISD::BUFFER_STORE_SHORT: return "BUFFER_STORE_SHORT"
;
4459 NODE_NAME_CASE(BUFFER_STORE_FORMAT)case AMDGPUISD::BUFFER_STORE_FORMAT: return "BUFFER_STORE_FORMAT"
;
4460 NODE_NAME_CASE(BUFFER_STORE_FORMAT_D16)case AMDGPUISD::BUFFER_STORE_FORMAT_D16: return "BUFFER_STORE_FORMAT_D16"
;
4461 NODE_NAME_CASE(BUFFER_ATOMIC_SWAP)case AMDGPUISD::BUFFER_ATOMIC_SWAP: return "BUFFER_ATOMIC_SWAP"
;
4462 NODE_NAME_CASE(BUFFER_ATOMIC_ADD)case AMDGPUISD::BUFFER_ATOMIC_ADD: return "BUFFER_ATOMIC_ADD"
;
4463 NODE_NAME_CASE(BUFFER_ATOMIC_SUB)case AMDGPUISD::BUFFER_ATOMIC_SUB: return "BUFFER_ATOMIC_SUB"
;
4464 NODE_NAME_CASE(BUFFER_ATOMIC_SMIN)case AMDGPUISD::BUFFER_ATOMIC_SMIN: return "BUFFER_ATOMIC_SMIN"
;
4465 NODE_NAME_CASE(BUFFER_ATOMIC_UMIN)case AMDGPUISD::BUFFER_ATOMIC_UMIN: return "BUFFER_ATOMIC_UMIN"
;
4466 NODE_NAME_CASE(BUFFER_ATOMIC_SMAX)case AMDGPUISD::BUFFER_ATOMIC_SMAX: return "BUFFER_ATOMIC_SMAX"
;
4467 NODE_NAME_CASE(BUFFER_ATOMIC_UMAX)case AMDGPUISD::BUFFER_ATOMIC_UMAX: return "BUFFER_ATOMIC_UMAX"
;
4468 NODE_NAME_CASE(BUFFER_ATOMIC_AND)case AMDGPUISD::BUFFER_ATOMIC_AND: return "BUFFER_ATOMIC_AND"
;
4469 NODE_NAME_CASE(BUFFER_ATOMIC_OR)case AMDGPUISD::BUFFER_ATOMIC_OR: return "BUFFER_ATOMIC_OR";
4470 NODE_NAME_CASE(BUFFER_ATOMIC_XOR)case AMDGPUISD::BUFFER_ATOMIC_XOR: return "BUFFER_ATOMIC_XOR"
;
4471 NODE_NAME_CASE(BUFFER_ATOMIC_INC)case AMDGPUISD::BUFFER_ATOMIC_INC: return "BUFFER_ATOMIC_INC"
;
4472 NODE_NAME_CASE(BUFFER_ATOMIC_DEC)case AMDGPUISD::BUFFER_ATOMIC_DEC: return "BUFFER_ATOMIC_DEC"
;
4473 NODE_NAME_CASE(BUFFER_ATOMIC_CMPSWAP)case AMDGPUISD::BUFFER_ATOMIC_CMPSWAP: return "BUFFER_ATOMIC_CMPSWAP"
;
4474 NODE_NAME_CASE(BUFFER_ATOMIC_CSUB)case AMDGPUISD::BUFFER_ATOMIC_CSUB: return "BUFFER_ATOMIC_CSUB"
;
4475 NODE_NAME_CASE(BUFFER_ATOMIC_FADD)case AMDGPUISD::BUFFER_ATOMIC_FADD: return "BUFFER_ATOMIC_FADD"
;
4476 NODE_NAME_CASE(BUFFER_ATOMIC_FMIN)case AMDGPUISD::BUFFER_ATOMIC_FMIN: return "BUFFER_ATOMIC_FMIN"
;
4477 NODE_NAME_CASE(BUFFER_ATOMIC_FMAX)case AMDGPUISD::BUFFER_ATOMIC_FMAX: return "BUFFER_ATOMIC_FMAX"
;
4478
4479 case AMDGPUISD::LAST_AMDGPU_ISD_NUMBER: break;
4480 }
4481 return nullptr;
4482}
4483
4484SDValue AMDGPUTargetLowering::getSqrtEstimate(SDValue Operand,
4485 SelectionDAG &DAG, int Enabled,
4486 int &RefinementSteps,
4487 bool &UseOneConstNR,
4488 bool Reciprocal) const {
4489 EVT VT = Operand.getValueType();
4490
4491 if (VT == MVT::f32) {
4492 RefinementSteps = 0;
4493 return DAG.getNode(AMDGPUISD::RSQ, SDLoc(Operand), VT, Operand);
4494 }
4495
4496 // TODO: There is also f64 rsq instruction, but the documentation is less
4497 // clear on its precision.
4498
4499 return SDValue();
4500}
4501
4502SDValue AMDGPUTargetLowering::getRecipEstimate(SDValue Operand,
4503 SelectionDAG &DAG, int Enabled,
4504 int &RefinementSteps) const {
4505 EVT VT = Operand.getValueType();
4506
4507 if (VT == MVT::f32) {
4508 // Reciprocal, < 1 ulp error.
4509 //
4510 // This reciprocal approximation converges to < 0.5 ulp error with one
4511 // newton rhapson performed with two fused multiple adds (FMAs).
4512
4513 RefinementSteps = 0;
4514 return DAG.getNode(AMDGPUISD::RCP, SDLoc(Operand), VT, Operand);
4515 }
4516
4517 // TODO: There is also f64 rcp instruction, but the documentation is less
4518 // clear on its precision.
4519
4520 return SDValue();
4521}
4522
4523void AMDGPUTargetLowering::computeKnownBitsForTargetNode(
4524 const SDValue Op, KnownBits &Known,
4525 const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth) const {
4526
4527 Known.resetAll(); // Don't know anything.
4528
4529 unsigned Opc = Op.getOpcode();
4530
4531 switch (Opc) {
4532 default:
4533 break;
4534 case AMDGPUISD::CARRY:
4535 case AMDGPUISD::BORROW: {
4536 Known.Zero = APInt::getHighBitsSet(32, 31);
4537 break;
4538 }
4539
4540 case AMDGPUISD::BFE_I32:
4541 case AMDGPUISD::BFE_U32: {
4542 ConstantSDNode *CWidth = dyn_cast<ConstantSDNode>(Op.getOperand(2));
4543 if (!CWidth)
4544 return;
4545
4546 uint32_t Width = CWidth->getZExtValue() & 0x1f;
4547
4548 if (Opc == AMDGPUISD::BFE_U32)
4549 Known.Zero = APInt::getHighBitsSet(32, 32 - Width);
4550
4551 break;
4552 }
4553 case AMDGPUISD::FP_TO_FP16: {
4554 unsigned BitWidth = Known.getBitWidth();
4555
4556 // High bits are zero.
4557 Known.Zero = APInt::getHighBitsSet(BitWidth, BitWidth - 16);
4558 break;
4559 }
4560 case AMDGPUISD::MUL_U24:
4561 case AMDGPUISD::MUL_I24: {
4562 KnownBits LHSKnown = DAG.computeKnownBits(Op.getOperand(0), Depth + 1);
4563 KnownBits RHSKnown = DAG.computeKnownBits(Op.getOperand(1), Depth + 1);
4564 unsigned TrailZ = LHSKnown.countMinTrailingZeros() +
4565 RHSKnown.countMinTrailingZeros();
4566 Known.Zero.setLowBits(std::min(TrailZ, 32u));
4567 // Skip extra check if all bits are known zeros.
4568 if (TrailZ >= 32)
4569 break;
4570
4571 // Truncate to 24 bits.
4572 LHSKnown = LHSKnown.trunc(24);
4573 RHSKnown = RHSKnown.trunc(24);
4574
4575 if (Opc == AMDGPUISD::MUL_I24) {
4576 unsigned LHSValBits = 24 - LHSKnown.countMinSignBits();
4577 unsigned RHSValBits = 24 - RHSKnown.countMinSignBits();
4578 unsigned MaxValBits = std::min(LHSValBits + RHSValBits, 32u);
4579 if (MaxValBits >= 32)
4580 break;
4581 bool LHSNegative = LHSKnown.isNegative();
4582 bool LHSNonNegative = LHSKnown.isNonNegative();
4583 bool LHSPositive = LHSKnown.isStrictlyPositive();
4584 bool RHSNegative = RHSKnown.isNegative();
4585 bool RHSNonNegative = RHSKnown.isNonNegative();
4586 bool RHSPositive = RHSKnown.isStrictlyPositive();
4587
4588 if ((LHSNonNegative && RHSNonNegative) || (LHSNegative && RHSNegative))
4589 Known.Zero.setHighBits(32 - MaxValBits);
4590 else if ((LHSNegative && RHSPositive) || (LHSPositive && RHSNegative))
4591 Known.One.setHighBits(32 - MaxValBits);
4592 } else {
4593 unsigned LHSValBits = 24 - LHSKnown.countMinLeadingZeros();
4594 unsigned RHSValBits = 24 - RHSKnown.countMinLeadingZeros();
4595 unsigned MaxValBits = std::min(LHSValBits + RHSValBits, 32u);
4596 if (MaxValBits >= 32)
4597 break;
4598 Known.Zero.setHighBits(32 - MaxValBits);
4599 }
4600 break;
4601 }
4602 case AMDGPUISD::PERM: {
4603 ConstantSDNode *CMask = dyn_cast<ConstantSDNode>(Op.getOperand(2));
4604 if (!CMask)
4605 return;
4606
4607 KnownBits LHSKnown = DAG.computeKnownBits(Op.getOperand(0), Depth + 1);
4608 KnownBits RHSKnown = DAG.computeKnownBits(Op.getOperand(1), Depth + 1);
4609 unsigned Sel = CMask->getZExtValue();
4610
4611 for (unsigned I = 0; I < 32; I += 8) {
4612 unsigned SelBits = Sel & 0xff;
4613 if (SelBits < 4) {
4614 SelBits *= 8;
4615 Known.One |= ((RHSKnown.One.getZExtValue() >> SelBits) & 0xff) << I;
4616 Known.Zero |= ((RHSKnown.Zero.getZExtValue() >> SelBits) & 0xff) << I;
4617 } else if (SelBits < 7) {
4618 SelBits = (SelBits & 3) * 8;
4619 Known.One |= ((LHSKnown.One.getZExtValue() >> SelBits) & 0xff) << I;
4620 Known.Zero |= ((LHSKnown.Zero.getZExtValue() >> SelBits) & 0xff) << I;
4621 } else if (SelBits == 0x0c) {
4622 Known.Zero |= 0xFFull << I;
4623 } else if (SelBits > 0x0c) {
4624 Known.One |= 0xFFull << I;
4625 }
4626 Sel >>= 8;
4627 }
4628 break;
4629 }
4630 case AMDGPUISD::BUFFER_LOAD_UBYTE: {
4631 Known.Zero.setHighBits(24);
4632 break;
4633 }
4634 case AMDGPUISD::BUFFER_LOAD_USHORT: {
4635 Known.Zero.setHighBits(16);
4636 break;
4637 }
4638 case AMDGPUISD::LDS: {
4639 auto GA = cast<GlobalAddressSDNode>(Op.getOperand(0).getNode());
4640 Align Alignment = GA->getGlobal()->getPointerAlignment(DAG.getDataLayout());
4641
4642 Known.Zero.setHighBits(16);
4643 Known.Zero.setLowBits(Log2(Alignment));
4644 break;
4645 }
4646 case ISD::INTRINSIC_WO_CHAIN: {
4647 unsigned IID = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
4648 switch (IID) {
4649 case Intrinsic::amdgcn_mbcnt_lo:
4650 case Intrinsic::amdgcn_mbcnt_hi: {
4651 const GCNSubtarget &ST =
4652 DAG.getMachineFunction().getSubtarget<GCNSubtarget>();
4653 // These return at most the wavefront size - 1.
4654 unsigned Size = Op.getValueType().getSizeInBits();
4655 Known.Zero.setHighBits(Size - ST.getWavefrontSizeLog2());
4656 break;
4657 }
4658 default:
4659 break;
4660 }
4661 }
4662 }
4663}
4664
4665unsigned AMDGPUTargetLowering::ComputeNumSignBitsForTargetNode(
4666 SDValue Op, const APInt &DemandedElts, const SelectionDAG &DAG,
4667 unsigned Depth) const {
4668 switch (Op.getOpcode()) {
4669 case AMDGPUISD::BFE_I32: {
4670 ConstantSDNode *Width = dyn_cast<ConstantSDNode>(Op.getOperand(2));
4671 if (!Width)
4672 return 1;
4673
4674 unsigned SignBits = 32 - Width->getZExtValue() + 1;
4675 if (!isNullConstant(Op.getOperand(1)))
4676 return SignBits;
4677
4678 // TODO: Could probably figure something out with non-0 offsets.
4679 unsigned Op0SignBits = DAG.ComputeNumSignBits(Op.getOperand(0), Depth + 1);
4680 return std::max(SignBits, Op0SignBits);
4681 }
4682
4683 case AMDGPUISD::BFE_U32: {
4684 ConstantSDNode *Width = dyn_cast<ConstantSDNode>(Op.getOperand(2));
4685 return Width ? 32 - (Width->getZExtValue() & 0x1f) : 1;
4686 }
4687
4688 case AMDGPUISD::CARRY:
4689 case AMDGPUISD::BORROW:
4690 return 31;
4691 case AMDGPUISD::BUFFER_LOAD_BYTE:
4692 return 25;
4693 case AMDGPUISD::BUFFER_LOAD_SHORT:
4694 return 17;
4695 case AMDGPUISD::BUFFER_LOAD_UBYTE:
4696 return 24;
4697 case AMDGPUISD::BUFFER_LOAD_USHORT:
4698 return 16;
4699 case AMDGPUISD::FP_TO_FP16:
4700 return 16;
4701 default:
4702 return 1;
4703 }
4704}
4705
4706unsigned AMDGPUTargetLowering::computeNumSignBitsForTargetInstr(
4707 GISelKnownBits &Analysis, Register R,
4708 const APInt &DemandedElts, const MachineRegisterInfo &MRI,
4709 unsigned Depth) const {
4710 const MachineInstr *MI = MRI.getVRegDef(R);
4711 if (!MI)
4712 return 1;
4713
4714 // TODO: Check range metadata on MMO.
4715 switch (MI->getOpcode()) {
4716 case AMDGPU::G_AMDGPU_BUFFER_LOAD_SBYTE:
4717 return 25;
4718 case AMDGPU::G_AMDGPU_BUFFER_LOAD_SSHORT:
4719 return 17;
4720 case AMDGPU::G_AMDGPU_BUFFER_LOAD_UBYTE:
4721 return 24;
4722 case AMDGPU::G_AMDGPU_BUFFER_LOAD_USHORT:
4723 return 16;
4724 default:
4725 return 1;
4726 }
4727}
4728
4729bool AMDGPUTargetLowering::isKnownNeverNaNForTargetNode(SDValue Op,
4730 const SelectionDAG &DAG,
4731 bool SNaN,
4732 unsigned Depth) const {
4733 unsigned Opcode = Op.getOpcode();
4734 switch (Opcode) {
4735 case AMDGPUISD::FMIN_LEGACY:
4736 case AMDGPUISD::FMAX_LEGACY: {
4737 if (SNaN)
4738 return true;
4739
4740 // TODO: Can check no nans on one of the operands for each one, but which
4741 // one?
4742 return false;
4743 }
4744 case AMDGPUISD::FMUL_LEGACY:
4745 case AMDGPUISD::CVT_PKRTZ_F16_F32: {
4746 if (SNaN)
4747 return true;
4748 return DAG.isKnownNeverNaN(Op.getOperand(0), SNaN, Depth + 1) &&
4749 DAG.isKnownNeverNaN(Op.getOperand(1), SNaN, Depth + 1);
4750 }
4751 case AMDGPUISD::FMED3:
4752 case AMDGPUISD::FMIN3:
4753 case AMDGPUISD::FMAX3:
4754 case AMDGPUISD::FMAD_FTZ: {
4755 if (SNaN)
4756 return true;
4757 return DAG.isKnownNeverNaN(Op.getOperand(0), SNaN, Depth + 1) &&
4758 DAG.isKnownNeverNaN(Op.getOperand(1), SNaN, Depth + 1) &&
4759 DAG.isKnownNeverNaN(Op.getOperand(2), SNaN, Depth + 1);
4760 }
4761 case AMDGPUISD::CVT_F32_UBYTE0:
4762 case AMDGPUISD::CVT_F32_UBYTE1:
4763 case AMDGPUISD::CVT_F32_UBYTE2:
4764 case AMDGPUISD::CVT_F32_UBYTE3:
4765 return true;
4766
4767 case AMDGPUISD::RCP:
4768 case AMDGPUISD::RSQ:
4769 case AMDGPUISD::RCP_LEGACY:
4770 case AMDGPUISD::RSQ_CLAMP: {
4771 if (SNaN)
4772 return true;
4773
4774 // TODO: Need is known positive check.
4775 return false;
4776 }
4777 case AMDGPUISD::LDEXP:
4778 case AMDGPUISD::FRACT: {
4779 if (SNaN)
4780 return true;
4781 return DAG.isKnownNeverNaN(Op.getOperand(0), SNaN, Depth + 1);
4782 }
4783 case AMDGPUISD::DIV_SCALE:
4784 case AMDGPUISD::DIV_FMAS:
4785 case AMDGPUISD::DIV_FIXUP:
4786 // TODO: Refine on operands.
4787 return SNaN;
4788 case AMDGPUISD::SIN_HW:
4789 case AMDGPUISD::COS_HW: {
4790 // TODO: Need check for infinity
4791 return SNaN;
4792 }
4793 case ISD::INTRINSIC_WO_CHAIN: {
4794 unsigned IntrinsicID
4795 = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
4796 // TODO: Handle more intrinsics
4797 switch (IntrinsicID) {
4798 case Intrinsic::amdgcn_cubeid:
4799 return true;
4800
4801 case Intrinsic::amdgcn_frexp_mant: {
4802 if (SNaN)
4803 return true;
4804 return DAG.isKnownNeverNaN(Op.getOperand(1), SNaN, Depth + 1);
4805 }
4806 case Intrinsic::amdgcn_cvt_pkrtz: {
4807 if (SNaN)
4808 return true;
4809 return DAG.isKnownNeverNaN(Op.getOperand(1), SNaN, Depth + 1) &&
4810 DAG.isKnownNeverNaN(Op.getOperand(2), SNaN, Depth + 1);
4811 }
4812 case Intrinsic::amdgcn_rcp:
4813 case Intrinsic::amdgcn_rsq:
4814 case Intrinsic::amdgcn_rcp_legacy:
4815 case Intrinsic::amdgcn_rsq_legacy:
4816 case Intrinsic::amdgcn_rsq_clamp: {
4817 if (SNaN)
4818 return true;
4819
4820 // TODO: Need is known positive check.
4821 return false;
4822 }
4823 case Intrinsic::amdgcn_trig_preop:
4824 case Intrinsic::amdgcn_fdot2:
4825 // TODO: Refine on operand
4826 return SNaN;
4827 case Intrinsic::amdgcn_fma_legacy:
4828 if (SNaN)
4829 return true;
4830 return DAG.isKnownNeverNaN(Op.getOperand(1), SNaN, Depth + 1) &&
4831 DAG.isKnownNeverNaN(Op.getOperand(2), SNaN, Depth + 1) &&
4832 DAG.isKnownNeverNaN(Op.getOperand(3), SNaN, Depth + 1);
4833 default:
4834 return false;
4835 }
4836 }
4837 default:
4838 return false;
4839 }
4840}
4841
4842TargetLowering::AtomicExpansionKind
4843AMDGPUTargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *RMW) const {
4844 switch (RMW->getOperation()) {
4845 case AtomicRMWInst::Nand:
4846 case AtomicRMWInst::FAdd:
4847 case AtomicRMWInst::FSub:
4848 return AtomicExpansionKind::CmpXChg;
4849 default:
4850 return AtomicExpansionKind::None;
4851 }
4852}
4853
4854bool AMDGPUTargetLowering::isConstantUnsignedBitfieldExtactLegal(
4855 unsigned Opc, LLT Ty1, LLT Ty2) const {
4856 return Ty1 == Ty2 && (Ty1 == LLT::scalar(32) || Ty1 == LLT::scalar(64));
4857}

/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/include/llvm/Support/Casting.h

1//===- llvm/Support/Casting.h - Allow flexible, checked, casts --*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines the isa<X>(), cast<X>(), dyn_cast<X>(), cast_or_null<X>(),
10// and dyn_cast_or_null<X>() templates.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_SUPPORT_CASTING_H
15#define LLVM_SUPPORT_CASTING_H
16
17#include "llvm/Support/Compiler.h"
18#include "llvm/Support/type_traits.h"
19#include <cassert>
20#include <memory>
21#include <type_traits>
22
23namespace llvm {
24
25//===----------------------------------------------------------------------===//
26// isa<x> Support Templates
27//===----------------------------------------------------------------------===//
28
29// Define a template that can be specialized by smart pointers to reflect the
30// fact that they are automatically dereferenced, and are not involved with the
31// template selection process... the default implementation is a noop.
32//
33template<typename From> struct simplify_type {
34 using SimpleType = From; // The real type this represents...
35
36 // An accessor to get the real value...
37 static SimpleType &getSimplifiedValue(From &Val) { return Val; }
38};
39
40template<typename From> struct simplify_type<const From> {
41 using NonConstSimpleType = typename simplify_type<From>::SimpleType;
42 using SimpleType =
43 typename add_const_past_pointer<NonConstSimpleType>::type;
44 using RetType =
45 typename add_lvalue_reference_if_not_pointer<SimpleType>::type;
46
47 static RetType getSimplifiedValue(const From& Val) {
48 return simplify_type<From>::getSimplifiedValue(const_cast<From&>(Val));
49 }
50};
51
52// The core of the implementation of isa<X> is here; To and From should be
53// the names of classes. This template can be specialized to customize the
54// implementation of isa<> without rewriting it from scratch.
55template <typename To, typename From, typename Enabler = void>
56struct isa_impl {
57 static inline bool doit(const From &Val) {
58 return To::classof(&Val);
59 }
60};
61
62/// Always allow upcasts, and perform no dynamic check for them.
63template <typename To, typename From>
64struct isa_impl<To, From, std::enable_if_t<std::is_base_of<To, From>::value>> {
65 static inline bool doit(const From &) { return true; }
66};
67
68template <typename To, typename From> struct isa_impl_cl {
69 static inline bool doit(const From &Val) {
70 return isa_impl<To, From>::doit(Val);
71 }
72};
73
74template <typename To, typename From> struct isa_impl_cl<To, const From> {
75 static inline bool doit(const From &Val) {
76 return isa_impl<To, From>::doit(Val);
77 }
78};
79
80template <typename To, typename From>
81struct isa_impl_cl<To, const std::unique_ptr<From>> {
82 static inline bool doit(const std::unique_ptr<From> &Val) {
83 assert(Val && "isa<> used on a null pointer")(static_cast <bool> (Val && "isa<> used on a null pointer"
) ? void (0) : __assert_fail ("Val && \"isa<> used on a null pointer\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/include/llvm/Support/Casting.h"
, 83, __extension__ __PRETTY_FUNCTION__))
;
84 return isa_impl_cl<To, From>::doit(*Val);
85 }
86};
87
88template <typename To, typename From> struct isa_impl_cl<To, From*> {
89 static inline bool doit(const From *Val) {
90 assert(Val && "isa<> used on a null pointer")(static_cast <bool> (Val && "isa<> used on a null pointer"
) ? void (0) : __assert_fail ("Val && \"isa<> used on a null pointer\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/include/llvm/Support/Casting.h"
, 90, __extension__ __PRETTY_FUNCTION__))
;
91 return isa_impl<To, From>::doit(*Val);
92 }
93};
94
95template <typename To, typename From> struct isa_impl_cl<To, From*const> {
96 static inline bool doit(const From *Val) {
97 assert(Val && "isa<> used on a null pointer")(static_cast <bool> (Val && "isa<> used on a null pointer"
) ? void (0) : __assert_fail ("Val && \"isa<> used on a null pointer\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/include/llvm/Support/Casting.h"
, 97, __extension__ __PRETTY_FUNCTION__))
;
98 return isa_impl<To, From>::doit(*Val);
99 }
100};
101
102template <typename To, typename From> struct isa_impl_cl<To, const From*> {
103 static inline bool doit(const From *Val) {
104 assert(Val && "isa<> used on a null pointer")(static_cast <bool> (Val && "isa<> used on a null pointer"
) ? void (0) : __assert_fail ("Val && \"isa<> used on a null pointer\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/include/llvm/Support/Casting.h"
, 104, __extension__ __PRETTY_FUNCTION__))
;
105 return isa_impl<To, From>::doit(*Val);
106 }
107};
108
109template <typename To, typename From> struct isa_impl_cl<To, const From*const> {
110 static inline bool doit(const From *Val) {
111 assert(Val && "isa<> used on a null pointer")(static_cast <bool> (Val && "isa<> used on a null pointer"
) ? void (0) : __assert_fail ("Val && \"isa<> used on a null pointer\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/include/llvm/Support/Casting.h"
, 111, __extension__ __PRETTY_FUNCTION__))
;
112 return isa_impl<To, From>::doit(*Val);
113 }
114};
115
116template<typename To, typename From, typename SimpleFrom>
117struct isa_impl_wrap {
118 // When From != SimplifiedType, we can simplify the type some more by using
119 // the simplify_type template.
120 static bool doit(const From &Val) {
121 return isa_impl_wrap<To, SimpleFrom,
122 typename simplify_type<SimpleFrom>::SimpleType>::doit(
123 simplify_type<const From>::getSimplifiedValue(Val));
124 }
125};
126
127template<typename To, typename FromTy>
128struct isa_impl_wrap<To, FromTy, FromTy> {
129 // When From == SimpleType, we are as simple as we are going to get.
130 static bool doit(const FromTy &Val) {
131 return isa_impl_cl<To,FromTy>::doit(Val);
132 }
133};
134
135// isa<X> - Return true if the parameter to the template is an instance of one
136// of the template type arguments. Used like this:
137//
138// if (isa<Type>(myVal)) { ... }
139// if (isa<Type0, Type1, Type2>(myVal)) { ... }
140//
141template <class X, class Y> LLVM_NODISCARD[[clang::warn_unused_result]] inline bool isa(const Y &Val) {
142 return isa_impl_wrap<X, const Y,
143 typename simplify_type<const Y>::SimpleType>::doit(Val);
144}
145
146template <typename First, typename Second, typename... Rest, typename Y>
147LLVM_NODISCARD[[clang::warn_unused_result]] inline bool isa(const Y &Val) {
148 return isa<First>(Val) || isa<Second, Rest...>(Val);
149}
150
151// isa_and_nonnull<X> - Functionally identical to isa, except that a null value
152// is accepted.
153//
154template <typename... X, class Y>
155LLVM_NODISCARD[[clang::warn_unused_result]] inline bool isa_and_nonnull(const Y &Val) {
156 if (!Val)
157 return false;
158 return isa<X...>(Val);
159}
160
161//===----------------------------------------------------------------------===//
162// cast<x> Support Templates
163//===----------------------------------------------------------------------===//
164
165template<class To, class From> struct cast_retty;
166
167// Calculate what type the 'cast' function should return, based on a requested
168// type of To and a source type of From.
169template<class To, class From> struct cast_retty_impl {
170 using ret_type = To &; // Normal case, return Ty&
171};
172template<class To, class From> struct cast_retty_impl<To, const From> {
173 using ret_type = const To &; // Normal case, return Ty&
174};
175
176template<class To, class From> struct cast_retty_impl<To, From*> {
177 using ret_type = To *; // Pointer arg case, return Ty*
178};
179
180template<class To, class From> struct cast_retty_impl<To, const From*> {
181 using ret_type = const To *; // Constant pointer arg case, return const Ty*
182};
183
184template<class To, class From> struct cast_retty_impl<To, const From*const> {
185 using ret_type = const To *; // Constant pointer arg case, return const Ty*
186};
187
188template <class To, class From>
189struct cast_retty_impl<To, std::unique_ptr<From>> {
190private:
191 using PointerType = typename cast_retty_impl<To, From *>::ret_type;
192 using ResultType = std::remove_pointer_t<PointerType>;
193
194public:
195 using ret_type = std::unique_ptr<ResultType>;
196};
197
198template<class To, class From, class SimpleFrom>
199struct cast_retty_wrap {
200 // When the simplified type and the from type are not the same, use the type
201 // simplifier to reduce the type, then reuse cast_retty_impl to get the
202 // resultant type.
203 using ret_type = typename cast_retty<To, SimpleFrom>::ret_type;
204};
205
206template<class To, class FromTy>
207struct cast_retty_wrap<To, FromTy, FromTy> {
208 // When the simplified type is equal to the from type, use it directly.
209 using ret_type = typename cast_retty_impl<To,FromTy>::ret_type;
210};
211
212template<class To, class From>
213struct cast_retty {
214 using ret_type = typename cast_retty_wrap<
215 To, From, typename simplify_type<From>::SimpleType>::ret_type;
216};
217
218// Ensure the non-simple values are converted using the simplify_type template
219// that may be specialized by smart pointers...
220//
221template<class To, class From, class SimpleFrom> struct cast_convert_val {
222 // This is not a simple type, use the template to simplify it...
223 static typename cast_retty<To, From>::ret_type doit(From &Val) {
224 return cast_convert_val<To, SimpleFrom,
23
Returning without writing to 'Val.Node'
225 typename simplify_type<SimpleFrom>::SimpleType>::doit(
226 simplify_type<From>::getSimplifiedValue(Val));
20
Calling 'simplify_type::getSimplifiedValue'
22
Returning from 'simplify_type::getSimplifiedValue'
227 }
228};
229
230template<class To, class FromTy> struct cast_convert_val<To,FromTy,FromTy> {
231 // This _is_ a simple type, just cast it.
232 static typename cast_retty<To, FromTy>::ret_type doit(const FromTy &Val) {
233 typename cast_retty<To, FromTy>::ret_type Res2
234 = (typename cast_retty<To, FromTy>::ret_type)const_cast<FromTy&>(Val);
235 return Res2;
236 }
237};
238
239template <class X> struct is_simple_type {
240 static const bool value =
241 std::is_same<X, typename simplify_type<X>::SimpleType>::value;
242};
243
244// cast<X> - Return the argument parameter cast to the specified type. This
245// casting operator asserts that the type is correct, so it does not return null
246// on failure. It does not allow a null argument (use cast_or_null for that).
247// It is typically used like this:
248//
249// cast<Instruction>(myVal)->getParent()
250//
251template <class X, class Y>
252inline std::enable_if_t<!is_simple_type<Y>::value,
253 typename cast_retty<X, const Y>::ret_type>
254cast(const Y &Val) {
255 assert(isa<X>(Val) && "cast<Ty>() argument of incompatible type!")(static_cast <bool> (isa<X>(Val) && "cast<Ty>() argument of incompatible type!"
) ? void (0) : __assert_fail ("isa<X>(Val) && \"cast<Ty>() argument of incompatible type!\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/include/llvm/Support/Casting.h"
, 255, __extension__ __PRETTY_FUNCTION__))
;
256 return cast_convert_val<
257 X, const Y, typename simplify_type<const Y>::SimpleType>::doit(Val);
258}
259
260template <class X, class Y>
261inline typename cast_retty<X, Y>::ret_type cast(Y &Val) {
262 assert(isa<X>(Val) && "cast<Ty>() argument of incompatible type!")(static_cast <bool> (isa<X>(Val) && "cast<Ty>() argument of incompatible type!"
) ? void (0) : __assert_fail ("isa<X>(Val) && \"cast<Ty>() argument of incompatible type!\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/include/llvm/Support/Casting.h"
, 262, __extension__ __PRETTY_FUNCTION__))
;
17
Assuming 'Val' is a 'ConstantSDNode'
18
'?' condition is true
263 return cast_convert_val<X, Y,
19
Calling 'cast_convert_val::doit'
24
Returning from 'cast_convert_val::doit'
25
Returning without writing to 'Val.Node'
264 typename simplify_type<Y>::SimpleType>::doit(Val);
265}
266
267template <class X, class Y>
268inline typename cast_retty<X, Y *>::ret_type cast(Y *Val) {
269 assert(isa<X>(Val) && "cast<Ty>() argument of incompatible type!")(static_cast <bool> (isa<X>(Val) && "cast<Ty>() argument of incompatible type!"
) ? void (0) : __assert_fail ("isa<X>(Val) && \"cast<Ty>() argument of incompatible type!\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/include/llvm/Support/Casting.h"
, 269, __extension__ __PRETTY_FUNCTION__))
;
270 return cast_convert_val<X, Y*,
271 typename simplify_type<Y*>::SimpleType>::doit(Val);
272}
273
274template <class X, class Y>
275inline typename cast_retty<X, std::unique_ptr<Y>>::ret_type
276cast(std::unique_ptr<Y> &&Val) {
277 assert(isa<X>(Val.get()) && "cast<Ty>() argument of incompatible type!")(static_cast <bool> (isa<X>(Val.get()) &&
"cast<Ty>() argument of incompatible type!") ? void (0
) : __assert_fail ("isa<X>(Val.get()) && \"cast<Ty>() argument of incompatible type!\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/include/llvm/Support/Casting.h"
, 277, __extension__ __PRETTY_FUNCTION__))
;
278 using ret_type = typename cast_retty<X, std::unique_ptr<Y>>::ret_type;
279 return ret_type(
280 cast_convert_val<X, Y *, typename simplify_type<Y *>::SimpleType>::doit(
281 Val.release()));
282}
283
284// cast_or_null<X> - Functionally identical to cast, except that a null value is
285// accepted.
286//
287template <class X, class Y>
288LLVM_NODISCARD[[clang::warn_unused_result]] inline std::enable_if_t<
289 !is_simple_type<Y>::value, typename cast_retty<X, const Y>::ret_type>
290cast_or_null(const Y &Val) {
291 if (!Val)
292 return nullptr;
293 assert(isa<X>(Val) && "cast_or_null<Ty>() argument of incompatible type!")(static_cast <bool> (isa<X>(Val) && "cast_or_null<Ty>() argument of incompatible type!"
) ? void (0) : __assert_fail ("isa<X>(Val) && \"cast_or_null<Ty>() argument of incompatible type!\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/include/llvm/Support/Casting.h"
, 293, __extension__ __PRETTY_FUNCTION__))
;
294 return cast<X>(Val);
295}
296
297template <class X, class Y>
298LLVM_NODISCARD[[clang::warn_unused_result]] inline std::enable_if_t<!is_simple_type<Y>::value,
299 typename cast_retty<X, Y>::ret_type>
300cast_or_null(Y &Val) {
301 if (!Val)
302 return nullptr;
303 assert(isa<X>(Val) && "cast_or_null<Ty>() argument of incompatible type!")(static_cast <bool> (isa<X>(Val) && "cast_or_null<Ty>() argument of incompatible type!"
) ? void (0) : __assert_fail ("isa<X>(Val) && \"cast_or_null<Ty>() argument of incompatible type!\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/include/llvm/Support/Casting.h"
, 303, __extension__ __PRETTY_FUNCTION__))
;
304 return cast<X>(Val);
305}
306
307template <class X, class Y>
308LLVM_NODISCARD[[clang::warn_unused_result]] inline typename cast_retty<X, Y *>::ret_type
309cast_or_null(Y *Val) {
310 if (!Val) return nullptr;
311 assert(isa<X>(Val) && "cast_or_null<Ty>() argument of incompatible type!")(static_cast <bool> (isa<X>(Val) && "cast_or_null<Ty>() argument of incompatible type!"
) ? void (0) : __assert_fail ("isa<X>(Val) && \"cast_or_null<Ty>() argument of incompatible type!\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/include/llvm/Support/Casting.h"
, 311, __extension__ __PRETTY_FUNCTION__))
;
312 return cast<X>(Val);
313}
314
315template <class X, class Y>
316inline typename cast_retty<X, std::unique_ptr<Y>>::ret_type
317cast_or_null(std::unique_ptr<Y> &&Val) {
318 if (!Val)
319 return nullptr;
320 return cast<X>(std::move(Val));
321}
322
323// dyn_cast<X> - Return the argument parameter cast to the specified type. This
324// casting operator returns null if the argument is of the wrong type, so it can
325// be used to test for a type as well as cast if successful. This should be
326// used in the context of an if statement like this:
327//
328// if (const Instruction *I = dyn_cast<Instruction>(myVal)) { ... }
329//
330
331template <class X, class Y>
332LLVM_NODISCARD[[clang::warn_unused_result]] inline std::enable_if_t<
333 !is_simple_type<Y>::value, typename cast_retty<X, const Y>::ret_type>
334dyn_cast(const Y &Val) {
335 return isa<X>(Val) ? cast<X>(Val) : nullptr;
336}
337
338template <class X, class Y>
339LLVM_NODISCARD[[clang::warn_unused_result]] inline typename cast_retty<X, Y>::ret_type dyn_cast(Y &Val) {
340 return isa<X>(Val) ? cast<X>(Val) : nullptr;
14
Assuming 'Val' is a 'ConstantSDNode'
15
'?' condition is true
16
Calling 'cast<llvm::ConstantSDNode, llvm::SDValue>'
26
Returning from 'cast<llvm::ConstantSDNode, llvm::SDValue>'
27
Returning without writing to 'Val.Node'
341}
342
343template <class X, class Y>
344LLVM_NODISCARD[[clang::warn_unused_result]] inline typename cast_retty<X, Y *>::ret_type dyn_cast(Y *Val) {
345 return isa<X>(Val) ? cast<X>(Val) : nullptr;
346}
347
348// dyn_cast_or_null<X> - Functionally identical to dyn_cast, except that a null
349// value is accepted.
350//
351template <class X, class Y>
352LLVM_NODISCARD[[clang::warn_unused_result]] inline std::enable_if_t<
353 !is_simple_type<Y>::value, typename cast_retty<X, const Y>::ret_type>
354dyn_cast_or_null(const Y &Val) {
355 return (Val && isa<X>(Val)) ? cast<X>(Val) : nullptr;
356}
357
358template <class X, class Y>
359LLVM_NODISCARD[[clang::warn_unused_result]] inline std::enable_if_t<!is_simple_type<Y>::value,
360 typename cast_retty<X, Y>::ret_type>
361dyn_cast_or_null(Y &Val) {
362 return (Val && isa<X>(Val)) ? cast<X>(Val) : nullptr;
363}
364
365template <class X, class Y>
366LLVM_NODISCARD[[clang::warn_unused_result]] inline typename cast_retty<X, Y *>::ret_type
367dyn_cast_or_null(Y *Val) {
368 return (Val && isa<X>(Val)) ? cast<X>(Val) : nullptr;
369}
370
371// unique_dyn_cast<X> - Given a unique_ptr<Y>, try to return a unique_ptr<X>,
372// taking ownership of the input pointer iff isa<X>(Val) is true. If the
373// cast is successful, From refers to nullptr on exit and the casted value
374// is returned. If the cast is unsuccessful, the function returns nullptr
375// and From is unchanged.
376template <class X, class Y>
377LLVM_NODISCARD[[clang::warn_unused_result]] inline auto unique_dyn_cast(std::unique_ptr<Y> &Val)
378 -> decltype(cast<X>(Val)) {
379 if (!isa<X>(Val))
380 return nullptr;
381 return cast<X>(std::move(Val));
382}
383
384template <class X, class Y>
385LLVM_NODISCARD[[clang::warn_unused_result]] inline auto unique_dyn_cast(std::unique_ptr<Y> &&Val) {
386 return unique_dyn_cast<X, Y>(Val);
387}
388
389// dyn_cast_or_null<X> - Functionally identical to unique_dyn_cast, except that
390// a null value is accepted.
391template <class X, class Y>
392LLVM_NODISCARD[[clang::warn_unused_result]] inline auto unique_dyn_cast_or_null(std::unique_ptr<Y> &Val)
393 -> decltype(cast<X>(Val)) {
394 if (!Val)
395 return nullptr;
396 return unique_dyn_cast<X, Y>(Val);
397}
398
399template <class X, class Y>
400LLVM_NODISCARD[[clang::warn_unused_result]] inline auto unique_dyn_cast_or_null(std::unique_ptr<Y> &&Val) {
401 return unique_dyn_cast_or_null<X, Y>(Val);
402}
403
404} // end namespace llvm
405
406#endif // LLVM_SUPPORT_CASTING_H

/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/include/llvm/CodeGen/SelectionDAGNodes.h

</
1//===- llvm/CodeGen/SelectionDAGNodes.h - SelectionDAG Nodes ----*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file declares the SDNode class and derived classes, which are used to
10// represent the nodes and operations present in a SelectionDAG. These nodes
11// and operations are machine code level operations, with some similarities to
12// the GCC RTL representation.
13//
14// Clients should include the SelectionDAG.h file instead of this file directly.
15//
16//===----------------------------------------------------------------------===//
17
18#ifndef LLVM_CODEGEN_SELECTIONDAGNODES_H
19#define LLVM_CODEGEN_SELECTIONDAGNODES_H
20
21#include "llvm/ADT/APFloat.h"
22#include "llvm/ADT/ArrayRef.h"
23#include "llvm/ADT/BitVector.h"
24#include "llvm/ADT/FoldingSet.h"
25#include "llvm/ADT/GraphTraits.h"
26#include "llvm/ADT/SmallPtrSet.h"
27#include "llvm/ADT/SmallVector.h"
28#include "llvm/ADT/ilist_node.h"
29#include "llvm/ADT/iterator.h"
30#include "llvm/ADT/iterator_range.h"
31#include "llvm/CodeGen/ISDOpcodes.h"
32#include "llvm/CodeGen/MachineMemOperand.h"
33#include "llvm/CodeGen/Register.h"
34#include "llvm/CodeGen/ValueTypes.h"
35#include "llvm/IR/Constants.h"
36#include "llvm/IR/DebugLoc.h"
37#include "llvm/IR/Instruction.h"
38#include "llvm/IR/Instructions.h"
39#include "llvm/IR/Metadata.h"
40#include "llvm/IR/Operator.h"
41#include "llvm/Support/AlignOf.h"
42#include "llvm/Support/AtomicOrdering.h"
43#include "llvm/Support/Casting.h"
44#include "llvm/Support/ErrorHandling.h"
45#include "llvm/Support/MachineValueType.h"
46#include "llvm/Support/TypeSize.h"
47#include <algorithm>
48#include <cassert>
49#include <climits>
50#include <cstddef>
51#include <cstdint>
52#include <cstring>
53#include <iterator>
54#include <string>
55#include <tuple>
56
57namespace llvm {
58
59class APInt;
60class Constant;
61template <typename T> struct DenseMapInfo;
62class GlobalValue;
63class MachineBasicBlock;
64class MachineConstantPoolValue;
65class MCSymbol;
66class raw_ostream;
67class SDNode;
68class SelectionDAG;
69class Type;
70class Value;
71
72void checkForCycles(const SDNode *N, const SelectionDAG *DAG = nullptr,
73 bool force = false);
74
75/// This represents a list of ValueType's that has been intern'd by
76/// a SelectionDAG. Instances of this simple value class are returned by
77/// SelectionDAG::getVTList(...).
78///
79struct SDVTList {
80 const EVT *VTs;
81 unsigned int NumVTs;
82};
83
84namespace ISD {
85
86 /// Node predicates
87
88/// If N is a BUILD_VECTOR or SPLAT_VECTOR node whose elements are all the
89/// same constant or undefined, return true and return the constant value in
90/// \p SplatValue.
91bool isConstantSplatVector(const SDNode *N, APInt &SplatValue);
92
93/// Return true if the specified node is a BUILD_VECTOR or SPLAT_VECTOR where
94/// all of the elements are ~0 or undef. If \p BuildVectorOnly is set to
95/// true, it only checks BUILD_VECTOR.
96bool isConstantSplatVectorAllOnes(const SDNode *N,
97 bool BuildVectorOnly = false);
98
99/// Return true if the specified node is a BUILD_VECTOR or SPLAT_VECTOR where
100/// all of the elements are 0 or undef. If \p BuildVectorOnly is set to true, it
101/// only checks BUILD_VECTOR.
102bool isConstantSplatVectorAllZeros(const SDNode *N,
103 bool BuildVectorOnly = false);
104
105/// Return true if the specified node is a BUILD_VECTOR where all of the
106/// elements are ~0 or undef.
107bool isBuildVectorAllOnes(const SDNode *N);
108
109/// Return true if the specified node is a BUILD_VECTOR where all of the
110/// elements are 0 or undef.
111bool isBuildVectorAllZeros(const SDNode *N);
112
113/// Return true if the specified node is a BUILD_VECTOR node of all
114/// ConstantSDNode or undef.
115bool isBuildVectorOfConstantSDNodes(const SDNode *N);
116
117/// Return true if the specified node is a BUILD_VECTOR node of all
118/// ConstantFPSDNode or undef.
119bool isBuildVectorOfConstantFPSDNodes(const SDNode *N);
120
121/// Return true if the node has at least one operand and all operands of the
122/// specified node are ISD::UNDEF.
123bool allOperandsUndef(const SDNode *N);
124
125} // end namespace ISD
126
127//===----------------------------------------------------------------------===//
128/// Unlike LLVM values, Selection DAG nodes may return multiple
129/// values as the result of a computation. Many nodes return multiple values,
130/// from loads (which define a token and a return value) to ADDC (which returns
131/// a result and a carry value), to calls (which may return an arbitrary number
132/// of values).
133///
134/// As such, each use of a SelectionDAG computation must indicate the node that
135/// computes it as well as which return value to use from that node. This pair
136/// of information is represented with the SDValue value type.
137///
138class SDValue {
139 friend struct DenseMapInfo<SDValue>;
140
141 SDNode *Node = nullptr; // The node defining the value we are using.
142 unsigned ResNo = 0; // Which return value of the node we are using.
143
144public:
145 SDValue() = default;
146 SDValue(SDNode *node, unsigned resno);
147
148 /// get the index which selects a specific result in the SDNode
149 unsigned getResNo() const { return ResNo; }
150
151 /// get the SDNode which holds the desired result
152 SDNode *getNode() const { return Node; }
153
154 /// set the SDNode
155 void setNode(SDNode *N) { Node = N; }
156
157 inline SDNode *operator->() const { return Node; }
158
159 bool operator==(const SDValue &O) const {
160 return Node == O.Node && ResNo == O.ResNo;
161 }
162 bool operator!=(const SDValue &O) const {
163 return !operator==(O);
164 }
165 bool operator<(const SDValue &O) const {
166 return std::tie(Node, ResNo) < std::tie(O.Node, O.ResNo);
167 }
168 explicit operator bool() const {
169 return Node != nullptr;
170 }
171
172 SDValue getValue(unsigned R) const {
173 return SDValue(Node, R);
174 }
175
176 /// Return true if this node is an operand of N.
177 bool isOperandOf(const SDNode *N) const;
178
179 /// Return the ValueType of the referenced return value.
180 inline EVT getValueType() const;
181
182 /// Return the simple ValueType of the referenced return value.
183 MVT getSimpleValueType() const {
184 return getValueType().getSimpleVT();
185 }
186
187 /// Returns the size of the value in bits.
188 ///
189 /// If the value type is a scalable vector type, the scalable property will
190 /// be set and the runtime size will be a positive integer multiple of the
191 /// base size.
192 TypeSize getValueSizeInBits() const {
193 return getValueType().getSizeInBits();
194 }
195
196 uint64_t getScalarValueSizeInBits() const {
197 return getValueType().getScalarType().getFixedSizeInBits();
198 }
199
200 // Forwarding methods - These forward to the corresponding methods in SDNode.
201 inline unsigned getOpcode() const;
202 inline unsigned getNumOperands() const;
203 inline const SDValue &getOperand(unsigned i) const;
204 inline uint64_t getConstantOperandVal(unsigned i) const;
205 inline const APInt &getConstantOperandAPInt(unsigned i) const;
206 inline bool isTargetMemoryOpcode() const;
207 inline bool isTargetOpcode() const;
208 inline bool isMachineOpcode() const;
209 inline bool isUndef() const;
210 inline unsigned getMachineOpcode() const;
211 inline const DebugLoc &getDebugLoc() const;
212 inline void dump() const;
213 inline void dump(const SelectionDAG *G) const;
214 inline void dumpr() const;
215 inline void dumpr(const SelectionDAG *G) const;
216
217 /// Return true if this operand (which must be a chain) reaches the
218 /// specified operand without crossing any side-effecting instructions.
219 /// In practice, this looks through token factors and non-volatile loads.
220 /// In order to remain efficient, this only
221 /// looks a couple of nodes in, it does not do an exhaustive search.
222 bool reachesChainWithoutSideEffects(SDValue Dest,
223 unsigned Depth = 2) const;
224
225 /// Return true if there are no nodes using value ResNo of Node.
226 inline bool use_empty() const;
227
228 /// Return true if there is exactly one node using value ResNo of Node.
229 inline bool hasOneUse() const;
230};
231
232template<> struct DenseMapInfo<SDValue> {
233 static inline SDValue getEmptyKey() {
234 SDValue V;
235 V.ResNo = -1U;
236 return V;
237 }
238
239 static inline SDValue getTombstoneKey() {
240 SDValue V;
241 V.ResNo = -2U;
242 return V;
243 }
244
245 static unsigned getHashValue(const SDValue &Val) {
246 return ((unsigned)((uintptr_t)Val.getNode() >> 4) ^
247 (unsigned)((uintptr_t)Val.getNode() >> 9)) + Val.getResNo();
248 }
249
250 static bool isEqual(const SDValue &LHS, const SDValue &RHS) {
251 return LHS == RHS;
252 }
253};
254
255/// Allow casting operators to work directly on
256/// SDValues as if they were SDNode*'s.
257template<> struct simplify_type<SDValue> {
258 using SimpleType = SDNode *;
259
260 static SimpleType getSimplifiedValue(SDValue &Val) {
261 return Val.getNode();
21
Returning without writing to 'Val.Node'
262 }
263};
264template<> struct simplify_type<const SDValue> {
265 using SimpleType = /*const*/ SDNode *;
266
267 static SimpleType getSimplifiedValue(const SDValue &Val) {
268 return Val.getNode();
269 }
270};
271
272/// Represents a use of a SDNode. This class holds an SDValue,
273/// which records the SDNode being used and the result number, a
274/// pointer to the SDNode using the value, and Next and Prev pointers,
275/// which link together all the uses of an SDNode.
276///
277class SDUse {
278 /// Val - The value being used.
279 SDValue Val;
280 /// User - The user of this value.
281 SDNode *User = nullptr;
282 /// Prev, Next - Pointers to the uses list of the SDNode referred by
283 /// this operand.
284 SDUse **Prev = nullptr;
285 SDUse *Next = nullptr;
286
287public:
288 SDUse() = default;
289 SDUse(const SDUse &U) = delete;
290 SDUse &operator=(const SDUse &) = delete;
291
292 /// Normally SDUse will just implicitly convert to an SDValue that it holds.
293 operator const SDValue&() const { return Val; }
294
295 /// If implicit conversion to SDValue doesn't work, the get() method returns
296 /// the SDValue.
297 const SDValue &get() const { return Val; }
298
299 /// This returns the SDNode that contains this Use.
300 SDNode *getUser() { return User; }
301
302 /// Get the next SDUse in the use list.
303 SDUse *getNext() const { return Next; }
304
305 /// Convenience function for get().getNode().
306 SDNode *getNode() const { return Val.getNode(); }
307 /// Convenience function for get().getResNo().
308 unsigned getResNo() const { return Val.getResNo(); }
309 /// Convenience function for get().getValueType().
310 EVT getValueType() const { return Val.getValueType(); }
311
312 /// Convenience function for get().operator==
313 bool operator==(const SDValue &V) const {
314 return Val == V;
315 }
316
317 /// Convenience function for get().operator!=
318 bool operator!=(const SDValue &V) const {
319 return Val != V;
320 }
321
322 /// Convenience function for get().operator<
323 bool operator<(const SDValue &V) const {
324 return Val < V;
325 }
326
327private:
328 friend class SelectionDAG;
329 friend class SDNode;
330 // TODO: unfriend HandleSDNode once we fix its operand handling.
331 friend class HandleSDNode;
332
333 void setUser(SDNode *p) { User = p; }
334
335 /// Remove this use from its existing use list, assign it the
336 /// given value, and add it to the new value's node's use list.
337 inline void set(const SDValue &V);
338 /// Like set, but only supports initializing a newly-allocated
339 /// SDUse with a non-null value.
340 inline void setInitial(const SDValue &V);
341 /// Like set, but only sets the Node portion of the value,
342 /// leaving the ResNo portion unmodified.
343 inline void setNode(SDNode *N);
344
345 void addToList(SDUse **List) {
346 Next = *List;
347 if (Next) Next->Prev = &Next;
348 Prev = List;
349 *List = this;
350 }
351
352 void removeFromList() {
353 *Prev = Next;
354 if (Next) Next->Prev = Prev;
355 }
356};
357
358/// simplify_type specializations - Allow casting operators to work directly on
359/// SDValues as if they were SDNode*'s.
360template<> struct simplify_type<SDUse> {
361 using SimpleType = SDNode *;
362
363 static SimpleType getSimplifiedValue(SDUse &Val) {
364 return Val.getNode();
365 }
366};
367
368/// These are IR-level optimization flags that may be propagated to SDNodes.
369/// TODO: This data structure should be shared by the IR optimizer and the
370/// the backend.
371struct SDNodeFlags {
372private:
373 bool NoUnsignedWrap : 1;
374 bool NoSignedWrap : 1;
375 bool Exact : 1;
376 bool NoNaNs : 1;
377 bool NoInfs : 1;
378 bool NoSignedZeros : 1;
379 bool AllowReciprocal : 1;
380 bool AllowContract : 1;
381 bool ApproximateFuncs : 1;
382 bool AllowReassociation : 1;
383
384 // We assume instructions do not raise floating-point exceptions by default,
385 // and only those marked explicitly may do so. We could choose to represent
386 // this via a positive "FPExcept" flags like on the MI level, but having a
387 // negative "NoFPExcept" flag here (that defaults to true) makes the flag
388 // intersection logic more straightforward.
389 bool NoFPExcept : 1;
390
391public:
392 /// Default constructor turns off all optimization flags.
393 SDNodeFlags()
394 : NoUnsignedWrap(false), NoSignedWrap(false), Exact(false), NoNaNs(false),
395 NoInfs(false), NoSignedZeros(false), AllowReciprocal(false),
396 AllowContract(false), ApproximateFuncs(false),
397 AllowReassociation(false), NoFPExcept(false) {}
398
399 /// Propagate the fast-math-flags from an IR FPMathOperator.
400 void copyFMF(const FPMathOperator &FPMO) {
401 setNoNaNs(FPMO.hasNoNaNs());
402 setNoInfs(FPMO.hasNoInfs());
403 setNoSignedZeros(FPMO.hasNoSignedZeros());
404 setAllowReciprocal(FPMO.hasAllowReciprocal());
405 setAllowContract(FPMO.hasAllowContract());
406 setApproximateFuncs(FPMO.hasApproxFunc());
407 setAllowReassociation(FPMO.hasAllowReassoc());
408 }
409
410 // These are mutators for each flag.
411 void setNoUnsignedWrap(bool b) { NoUnsignedWrap = b; }
412 void setNoSignedWrap(bool b) { NoSignedWrap = b; }
413 void setExact(bool b) { Exact = b; }
414 void setNoNaNs(bool b) { NoNaNs = b; }
415 void setNoInfs(bool b) { NoInfs = b; }
416 void setNoSignedZeros(bool b) { NoSignedZeros = b; }
417 void setAllowReciprocal(bool b) { AllowReciprocal = b; }
418 void setAllowContract(bool b) { AllowContract = b; }
419 void setApproximateFuncs(bool b) { ApproximateFuncs = b; }
420 void setAllowReassociation(bool b) { AllowReassociation = b; }
421 void setNoFPExcept(bool b) { NoFPExcept = b; }
422
423 // These are accessors for each flag.
424 bool hasNoUnsignedWrap() const { return NoUnsignedWrap; }
425 bool hasNoSignedWrap() const { return NoSignedWrap; }
426 bool hasExact() const { return Exact; }
427 bool hasNoNaNs() const { return NoNaNs; }
428 bool hasNoInfs() const { return NoInfs; }
429 bool hasNoSignedZeros() const { return NoSignedZeros; }
430 bool hasAllowReciprocal() const { return AllowReciprocal; }
431 bool hasAllowContract() const { return AllowContract; }
432 bool hasApproximateFuncs() const { return ApproximateFuncs; }
433 bool hasAllowReassociation() const { return AllowReassociation; }
434 bool hasNoFPExcept() const { return NoFPExcept; }
435
436 /// Clear any flags in this flag set that aren't also set in Flags. All
437 /// flags will be cleared if Flags are undefined.
438 void intersectWith(const SDNodeFlags Flags) {
439 NoUnsignedWrap &= Flags.NoUnsignedWrap;
440 NoSignedWrap &= Flags.NoSignedWrap;
441 Exact &= Flags.Exact;
442 NoNaNs &= Flags.NoNaNs;
443 NoInfs &= Flags.NoInfs;
444 NoSignedZeros &= Flags.NoSignedZeros;
445 AllowReciprocal &= Flags.AllowReciprocal;
446 AllowContract &= Flags.AllowContract;
447 ApproximateFuncs &= Flags.ApproximateFuncs;
448 AllowReassociation &= Flags.AllowReassociation;
449 NoFPExcept &= Flags.NoFPExcept;
450 }
451};
452
453/// Represents one node in the SelectionDAG.
454///
455class SDNode : public FoldingSetNode, public ilist_node<SDNode> {
456private:
457 /// The operation that this node performs.
458 int16_t NodeType;
459
460protected:
461 // We define a set of mini-helper classes to help us interpret the bits in our
462 // SubclassData. These are designed to fit within a uint16_t so they pack
463 // with NodeType.
464
465#if defined(_AIX) && (!defined(__GNUC__4) || defined(__clang__1))
466// Except for GCC; by default, AIX compilers store bit-fields in 4-byte words
467// and give the `pack` pragma push semantics.
468#define BEGIN_TWO_BYTE_PACK() _Pragma("pack(2)")pack(2)
469#define END_TWO_BYTE_PACK() _Pragma("pack(pop)")pack(pop)
470#else
471#define BEGIN_TWO_BYTE_PACK()
472#define END_TWO_BYTE_PACK()
473#endif
474
475BEGIN_TWO_BYTE_PACK()
476 class SDNodeBitfields {
477 friend class SDNode;
478 friend class MemIntrinsicSDNode;
479 friend class MemSDNode;
480 friend class SelectionDAG;
481
482 uint16_t HasDebugValue : 1;
483 uint16_t IsMemIntrinsic : 1;
484 uint16_t IsDivergent : 1;
485 };
486 enum { NumSDNodeBits = 3 };
487
488 class ConstantSDNodeBitfields {
489 friend class ConstantSDNode;
490
491 uint16_t : NumSDNodeBits;
492
493 uint16_t IsOpaque : 1;
494 };
495
496 class MemSDNodeBitfields {
497 friend class MemSDNode;
498 friend class MemIntrinsicSDNode;
499 friend class AtomicSDNode;
500
501 uint16_t : NumSDNodeBits;
502
503 uint16_t IsVolatile : 1;
504 uint16_t IsNonTemporal : 1;
505 uint16_t IsDereferenceable : 1;
506 uint16_t IsInvariant : 1;
507 };
508 enum { NumMemSDNodeBits = NumSDNodeBits + 4 };
509
510 class LSBaseSDNodeBitfields {
511 friend class LSBaseSDNode;
512 friend class VPLoadStoreSDNode;
513 friend class MaskedLoadStoreSDNode;
514 friend class MaskedGatherScatterSDNode;
515 friend class VPGatherScatterSDNode;
516
517 uint16_t : NumMemSDNodeBits;
518
519 // This storage is shared between disparate class hierarchies to hold an
520 // enumeration specific to the class hierarchy in use.
521 // LSBaseSDNode => enum ISD::MemIndexedMode
522 // VPLoadStoreBaseSDNode => enum ISD::MemIndexedMode
523 // MaskedLoadStoreBaseSDNode => enum ISD::MemIndexedMode
524 // VPGatherScatterSDNode => enum ISD::MemIndexType
525 // MaskedGatherScatterSDNode => enum ISD::MemIndexType
526 uint16_t AddressingMode : 3;
527 };
528 enum { NumLSBaseSDNodeBits = NumMemSDNodeBits + 3 };
529
530 class LoadSDNodeBitfields {
531 friend class LoadSDNode;
532 friend class VPLoadSDNode;
533 friend class MaskedLoadSDNode;
534 friend class MaskedGatherSDNode;
535 friend class VPGatherSDNode;
536
537 uint16_t : NumLSBaseSDNodeBits;
538
539 uint16_t ExtTy : 2; // enum ISD::LoadExtType
540 uint16_t IsExpanding : 1;
541 };
542
543 class StoreSDNodeBitfields {
544 friend class StoreSDNode;
545 friend class VPStoreSDNode;
546 friend class MaskedStoreSDNode;
547 friend class MaskedScatterSDNode;
548 friend class VPScatterSDNode;
549
550 uint16_t : NumLSBaseSDNodeBits;
551
552 uint16_t IsTruncating : 1;
553 uint16_t IsCompressing : 1;
554 };
555
556 union {
557 char RawSDNodeBits[sizeof(uint16_t)];
558 SDNodeBitfields SDNodeBits;
559 ConstantSDNodeBitfields ConstantSDNodeBits;
560 MemSDNodeBitfields MemSDNodeBits;
561 LSBaseSDNodeBitfields LSBaseSDNodeBits;
562 LoadSDNodeBitfields LoadSDNodeBits;
563 StoreSDNodeBitfields StoreSDNodeBits;
564 };
565END_TWO_BYTE_PACK()
566#undef BEGIN_TWO_BYTE_PACK
567#undef END_TWO_BYTE_PACK
568
569 // RawSDNodeBits must cover the entirety of the union. This means that all of
570 // the union's members must have size <= RawSDNodeBits. We write the RHS as
571 // "2" instead of sizeof(RawSDNodeBits) because MSVC can't handle the latter.
572 static_assert(sizeof(SDNodeBitfields) <= 2, "field too wide");
573 static_assert(sizeof(ConstantSDNodeBitfields) <= 2, "field too wide");
574 static_assert(sizeof(MemSDNodeBitfields) <= 2, "field too wide");
575 static_assert(sizeof(LSBaseSDNodeBitfields) <= 2, "field too wide");
576 static_assert(sizeof(LoadSDNodeBitfields) <= 2, "field too wide");
577 static_assert(sizeof(StoreSDNodeBitfields) <= 2, "field too wide");
578
579private:
580 friend class SelectionDAG;
581 // TODO: unfriend HandleSDNode once we fix its operand handling.
582 friend class HandleSDNode;
583
584 /// Unique id per SDNode in the DAG.
585 int NodeId = -1;
586
587 /// The values that are used by this operation.
588 SDUse *OperandList = nullptr;
589
590 /// The types of the values this node defines. SDNode's may
591 /// define multiple values simultaneously.
592 const EVT *ValueList;
593
594 /// List of uses for this SDNode.
595 SDUse *UseList = nullptr;
596
597 /// The number of entries in the Operand/Value list.
598 unsigned short NumOperands = 0;
599 unsigned short NumValues;
600
601 // The ordering of the SDNodes. It roughly corresponds to the ordering of the
602 // original LLVM instructions.
603 // This is used for turning off scheduling, because we'll forgo
604 // the normal scheduling algorithms and output the instructions according to
605 // this ordering.
606 unsigned IROrder;
607
608 /// Source line information.
609 DebugLoc debugLoc;
610
611 /// Return a pointer to the specified value type.
612 static const EVT *getValueTypeList(EVT VT);
613
614 SDNodeFlags Flags;
615
616public:
617 /// Unique and persistent id per SDNode in the DAG.
618 /// Used for debug printing.
619 uint16_t PersistentId;
620
621 //===--------------------------------------------------------------------===//
622 // Accessors
623 //
624
625 /// Return the SelectionDAG opcode value for this node. For
626 /// pre-isel nodes (those for which isMachineOpcode returns false), these
627 /// are the opcode values in the ISD and <target>ISD namespaces. For
628 /// post-isel opcodes, see getMachineOpcode.
629 unsigned getOpcode() const { return (unsigned short)NodeType; }
630
631 /// Test if this node has a target-specific opcode (in the
632 /// \<target\>ISD namespace).
633 bool isTargetOpcode() const { return NodeType >= ISD::BUILTIN_OP_END; }
634
635 /// Test if this node has a target-specific opcode that may raise
636 /// FP exceptions (in the \<target\>ISD namespace and greater than
637 /// FIRST_TARGET_STRICTFP_OPCODE). Note that all target memory
638 /// opcode are currently automatically considered to possibly raise
639 /// FP exceptions as well.
640 bool isTargetStrictFPOpcode() const {
641 return NodeType >= ISD::FIRST_TARGET_STRICTFP_OPCODE;
642 }
643
644 /// Test if this node has a target-specific
645 /// memory-referencing opcode (in the \<target\>ISD namespace and
646 /// greater than FIRST_TARGET_MEMORY_OPCODE).
647 bool isTargetMemoryOpcode() const {
648 return NodeType >= ISD::FIRST_TARGET_MEMORY_OPCODE;
649 }
650
651 /// Return true if the type of the node type undefined.
652 bool isUndef() const { return NodeType == ISD::UNDEF; }
653
654 /// Test if this node is a memory intrinsic (with valid pointer information).
655 /// INTRINSIC_W_CHAIN and INTRINSIC_VOID nodes are sometimes created for
656 /// non-memory intrinsics (with chains) that are not really instances of
657 /// MemSDNode. For such nodes, we need some extra state to determine the
658 /// proper classof relationship.
659 bool isMemIntrinsic() const {
660 return (NodeType == ISD::INTRINSIC_W_CHAIN ||
661 NodeType == ISD::INTRINSIC_VOID) &&
662 SDNodeBits.IsMemIntrinsic;
663 }
664
665 /// Test if this node is a strict floating point pseudo-op.
666 bool isStrictFPOpcode() {
667 switch (NodeType) {
668 default:
669 return false;
670 case ISD::STRICT_FP16_TO_FP:
671 case ISD::STRICT_FP_TO_FP16:
672#define DAG_INSTRUCTION(NAME, NARG, ROUND_MODE, INTRINSIC, DAGN) \
673 case ISD::STRICT_##DAGN:
674#include "llvm/IR/ConstrainedOps.def"
675 return true;
676 }
677 }
678
679 /// Test if this node has a post-isel opcode, directly
680 /// corresponding to a MachineInstr opcode.
681 bool isMachineOpcode() const { return NodeType < 0; }
682