Bug Summary

File:llvm/include/llvm/CodeGen/SelectionDAGNodes.h
Warning:line 1150, column 10
Called C++ object pointer is null

Annotated Source Code

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clang -cc1 -cc1 -triple x86_64-pc-linux-gnu -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name InstrEmitter.cpp -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=cplusplus -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -analyzer-config-compatibility-mode=true -mrelocation-model pic -pic-level 2 -mframe-pointer=none -fmath-errno -fno-rounding-math -mconstructor-aliases -munwind-tables -target-cpu x86-64 -tune-cpu generic -debugger-tuning=gdb -ffunction-sections -fdata-sections -fcoverage-compilation-dir=/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/build-llvm -resource-dir /usr/lib/llvm-14/lib/clang/14.0.0 -D _DEBUG -D _GNU_SOURCE -D __STDC_CONSTANT_MACROS -D __STDC_FORMAT_MACROS -D __STDC_LIMIT_MACROS -I lib/CodeGen/SelectionDAG -I /build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/CodeGen/SelectionDAG -I include -I /build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/include -D NDEBUG -U NDEBUG -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/10/../../../../include/c++/10 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/10/../../../../include/x86_64-linux-gnu/c++/10 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/10/../../../../include/c++/10/backward -internal-isystem /usr/lib/llvm-14/lib/clang/14.0.0/include -internal-isystem /usr/local/include -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/10/../../../../x86_64-linux-gnu/include -internal-externc-isystem /usr/include/x86_64-linux-gnu -internal-externc-isystem /include -internal-externc-isystem /usr/include -O2 -Wno-unused-command-line-argument -Wno-unknown-warning-option -Wno-unused-parameter -Wwrite-strings -Wno-missing-field-initializers -Wno-long-long -Wno-maybe-uninitialized -Wno-class-memaccess -Wno-redundant-move -Wno-pessimizing-move -Wno-noexcept-type -Wno-comment -std=c++14 -fdeprecated-macro -fdebug-compilation-dir=/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/build-llvm -ferror-limit 19 -fvisibility-inlines-hidden -fgnuc-version=4.2.1 -fcolor-diagnostics -vectorize-loops -vectorize-slp -analyzer-output=html -analyzer-config stable-report-filename=true -faddrsig -D__GCC_HAVE_DWARF2_CFI_ASM=1 -o /tmp/scan-build-2021-09-26-234817-15343-1 -x c++ /build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp

/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp

1//==--- InstrEmitter.cpp - Emit MachineInstrs for the SelectionDAG class ---==//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This implements the Emit routines for the SelectionDAG class, which creates
10// MachineInstrs based on the decisions of the SelectionDAG instruction
11// selection.
12//
13//===----------------------------------------------------------------------===//
14
15#include "InstrEmitter.h"
16#include "SDNodeDbgValue.h"
17#include "llvm/ADT/Statistic.h"
18#include "llvm/CodeGen/MachineConstantPool.h"
19#include "llvm/CodeGen/MachineFunction.h"
20#include "llvm/CodeGen/MachineInstrBuilder.h"
21#include "llvm/CodeGen/MachineRegisterInfo.h"
22#include "llvm/CodeGen/SelectionDAG.h"
23#include "llvm/CodeGen/StackMaps.h"
24#include "llvm/CodeGen/TargetInstrInfo.h"
25#include "llvm/CodeGen/TargetLowering.h"
26#include "llvm/CodeGen/TargetSubtargetInfo.h"
27#include "llvm/IR/DataLayout.h"
28#include "llvm/IR/DebugInfo.h"
29#include "llvm/IR/PseudoProbe.h"
30#include "llvm/Support/Debug.h"
31#include "llvm/Support/ErrorHandling.h"
32#include "llvm/Support/MathExtras.h"
33#include "llvm/Target/TargetMachine.h"
34using namespace llvm;
35
36#define DEBUG_TYPE"instr-emitter" "instr-emitter"
37
38/// MinRCSize - Smallest register class we allow when constraining virtual
39/// registers. If satisfying all register class constraints would require
40/// using a smaller register class, emit a COPY to a new virtual register
41/// instead.
42const unsigned MinRCSize = 4;
43
44/// CountResults - The results of target nodes have register or immediate
45/// operands first, then an optional chain, and optional glue operands (which do
46/// not go into the resulting MachineInstr).
47unsigned InstrEmitter::CountResults(SDNode *Node) {
48 unsigned N = Node->getNumValues();
49 while (N && Node->getValueType(N - 1) == MVT::Glue)
50 --N;
51 if (N && Node->getValueType(N - 1) == MVT::Other)
52 --N; // Skip over chain result.
53 return N;
54}
55
56/// countOperands - The inputs to target nodes have any actual inputs first,
57/// followed by an optional chain operand, then an optional glue operand.
58/// Compute the number of actual operands that will go into the resulting
59/// MachineInstr.
60///
61/// Also count physreg RegisterSDNode and RegisterMaskSDNode operands preceding
62/// the chain and glue. These operands may be implicit on the machine instr.
63static unsigned countOperands(SDNode *Node, unsigned NumExpUses,
64 unsigned &NumImpUses) {
65 unsigned N = Node->getNumOperands();
66 while (N && Node->getOperand(N - 1).getValueType() == MVT::Glue)
67 --N;
68 if (N && Node->getOperand(N - 1).getValueType() == MVT::Other)
69 --N; // Ignore chain if it exists.
70
71 // Count RegisterSDNode and RegisterMaskSDNode operands for NumImpUses.
72 NumImpUses = N - NumExpUses;
73 for (unsigned I = N; I > NumExpUses; --I) {
74 if (isa<RegisterMaskSDNode>(Node->getOperand(I - 1)))
75 continue;
76 if (RegisterSDNode *RN = dyn_cast<RegisterSDNode>(Node->getOperand(I - 1)))
77 if (Register::isPhysicalRegister(RN->getReg()))
78 continue;
79 NumImpUses = N - I;
80 break;
81 }
82
83 return N;
84}
85
86/// EmitCopyFromReg - Generate machine code for an CopyFromReg node or an
87/// implicit physical register output.
88void InstrEmitter::
89EmitCopyFromReg(SDNode *Node, unsigned ResNo, bool IsClone, bool IsCloned,
90 Register SrcReg, DenseMap<SDValue, Register> &VRBaseMap) {
91 Register VRBase;
92 if (SrcReg.isVirtual()) {
93 // Just use the input register directly!
94 SDValue Op(Node, ResNo);
95 if (IsClone)
96 VRBaseMap.erase(Op);
97 bool isNew = VRBaseMap.insert(std::make_pair(Op, SrcReg)).second;
98 (void)isNew; // Silence compiler warning.
99 assert(isNew && "Node emitted out of order - early")(static_cast <bool> (isNew && "Node emitted out of order - early"
) ? void (0) : __assert_fail ("isNew && \"Node emitted out of order - early\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp"
, 99, __extension__ __PRETTY_FUNCTION__))
;
100 return;
101 }
102
103 // If the node is only used by a CopyToReg and the dest reg is a vreg, use
104 // the CopyToReg'd destination register instead of creating a new vreg.
105 bool MatchReg = true;
106 const TargetRegisterClass *UseRC = nullptr;
107 MVT VT = Node->getSimpleValueType(ResNo);
108
109 // Stick to the preferred register classes for legal types.
110 if (TLI->isTypeLegal(VT))
111 UseRC = TLI->getRegClassFor(VT, Node->isDivergent());
112
113 if (!IsClone && !IsCloned)
114 for (SDNode *User : Node->uses()) {
115 bool Match = true;
116 if (User->getOpcode() == ISD::CopyToReg &&
117 User->getOperand(2).getNode() == Node &&
118 User->getOperand(2).getResNo() == ResNo) {
119 Register DestReg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
120 if (DestReg.isVirtual()) {
121 VRBase = DestReg;
122 Match = false;
123 } else if (DestReg != SrcReg)
124 Match = false;
125 } else {
126 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
127 SDValue Op = User->getOperand(i);
128 if (Op.getNode() != Node || Op.getResNo() != ResNo)
129 continue;
130 MVT VT = Node->getSimpleValueType(Op.getResNo());
131 if (VT == MVT::Other || VT == MVT::Glue)
132 continue;
133 Match = false;
134 if (User->isMachineOpcode()) {
135 const MCInstrDesc &II = TII->get(User->getMachineOpcode());
136 const TargetRegisterClass *RC = nullptr;
137 if (i+II.getNumDefs() < II.getNumOperands()) {
138 RC = TRI->getAllocatableClass(
139 TII->getRegClass(II, i+II.getNumDefs(), TRI, *MF));
140 }
141 if (!UseRC)
142 UseRC = RC;
143 else if (RC) {
144 const TargetRegisterClass *ComRC =
145 TRI->getCommonSubClass(UseRC, RC);
146 // If multiple uses expect disjoint register classes, we emit
147 // copies in AddRegisterOperand.
148 if (ComRC)
149 UseRC = ComRC;
150 }
151 }
152 }
153 }
154 MatchReg &= Match;
155 if (VRBase)
156 break;
157 }
158
159 const TargetRegisterClass *SrcRC = nullptr, *DstRC = nullptr;
160 SrcRC = TRI->getMinimalPhysRegClass(SrcReg, VT);
161
162 // Figure out the register class to create for the destreg.
163 if (VRBase) {
164 DstRC = MRI->getRegClass(VRBase);
165 } else if (UseRC) {
166 assert(TRI->isTypeLegalForClass(*UseRC, VT) &&(static_cast <bool> (TRI->isTypeLegalForClass(*UseRC
, VT) && "Incompatible phys register def and uses!") ?
void (0) : __assert_fail ("TRI->isTypeLegalForClass(*UseRC, VT) && \"Incompatible phys register def and uses!\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp"
, 167, __extension__ __PRETTY_FUNCTION__))
167 "Incompatible phys register def and uses!")(static_cast <bool> (TRI->isTypeLegalForClass(*UseRC
, VT) && "Incompatible phys register def and uses!") ?
void (0) : __assert_fail ("TRI->isTypeLegalForClass(*UseRC, VT) && \"Incompatible phys register def and uses!\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp"
, 167, __extension__ __PRETTY_FUNCTION__))
;
168 DstRC = UseRC;
169 } else
170 DstRC = SrcRC;
171
172 // If all uses are reading from the src physical register and copying the
173 // register is either impossible or very expensive, then don't create a copy.
174 if (MatchReg && SrcRC->getCopyCost() < 0) {
175 VRBase = SrcReg;
176 } else {
177 // Create the reg, emit the copy.
178 VRBase = MRI->createVirtualRegister(DstRC);
179 BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TargetOpcode::COPY),
180 VRBase).addReg(SrcReg);
181 }
182
183 SDValue Op(Node, ResNo);
184 if (IsClone)
185 VRBaseMap.erase(Op);
186 bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second;
187 (void)isNew; // Silence compiler warning.
188 assert(isNew && "Node emitted out of order - early")(static_cast <bool> (isNew && "Node emitted out of order - early"
) ? void (0) : __assert_fail ("isNew && \"Node emitted out of order - early\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp"
, 188, __extension__ __PRETTY_FUNCTION__))
;
189}
190
191void InstrEmitter::CreateVirtualRegisters(SDNode *Node,
192 MachineInstrBuilder &MIB,
193 const MCInstrDesc &II,
194 bool IsClone, bool IsCloned,
195 DenseMap<SDValue, Register> &VRBaseMap) {
196 assert(Node->getMachineOpcode() != TargetOpcode::IMPLICIT_DEF &&(static_cast <bool> (Node->getMachineOpcode() != TargetOpcode
::IMPLICIT_DEF && "IMPLICIT_DEF should have been handled as a special case elsewhere!"
) ? void (0) : __assert_fail ("Node->getMachineOpcode() != TargetOpcode::IMPLICIT_DEF && \"IMPLICIT_DEF should have been handled as a special case elsewhere!\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp"
, 197, __extension__ __PRETTY_FUNCTION__))
197 "IMPLICIT_DEF should have been handled as a special case elsewhere!")(static_cast <bool> (Node->getMachineOpcode() != TargetOpcode
::IMPLICIT_DEF && "IMPLICIT_DEF should have been handled as a special case elsewhere!"
) ? void (0) : __assert_fail ("Node->getMachineOpcode() != TargetOpcode::IMPLICIT_DEF && \"IMPLICIT_DEF should have been handled as a special case elsewhere!\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp"
, 197, __extension__ __PRETTY_FUNCTION__))
;
198
199 unsigned NumResults = CountResults(Node);
200 bool HasVRegVariadicDefs = !MF->getTarget().usesPhysRegsForValues() &&
201 II.isVariadic() && II.variadicOpsAreDefs();
202 unsigned NumVRegs = HasVRegVariadicDefs ? NumResults : II.getNumDefs();
203 if (Node->getMachineOpcode() == TargetOpcode::STATEPOINT)
204 NumVRegs = NumResults;
205 for (unsigned i = 0; i < NumVRegs; ++i) {
206 // If the specific node value is only used by a CopyToReg and the dest reg
207 // is a vreg in the same register class, use the CopyToReg'd destination
208 // register instead of creating a new vreg.
209 Register VRBase;
210 const TargetRegisterClass *RC =
211 TRI->getAllocatableClass(TII->getRegClass(II, i, TRI, *MF));
212 // Always let the value type influence the used register class. The
213 // constraints on the instruction may be too lax to represent the value
214 // type correctly. For example, a 64-bit float (X86::FR64) can't live in
215 // the 32-bit float super-class (X86::FR32).
216 if (i < NumResults && TLI->isTypeLegal(Node->getSimpleValueType(i))) {
217 const TargetRegisterClass *VTRC = TLI->getRegClassFor(
218 Node->getSimpleValueType(i),
219 (Node->isDivergent() || (RC && TRI->isDivergentRegClass(RC))));
220 if (RC)
221 VTRC = TRI->getCommonSubClass(RC, VTRC);
222 if (VTRC)
223 RC = VTRC;
224 }
225
226 if (II.OpInfo != nullptr && II.OpInfo[i].isOptionalDef()) {
227 // Optional def must be a physical register.
228 VRBase = cast<RegisterSDNode>(Node->getOperand(i-NumResults))->getReg();
229 assert(VRBase.isPhysical())(static_cast <bool> (VRBase.isPhysical()) ? void (0) : __assert_fail
("VRBase.isPhysical()", "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp"
, 229, __extension__ __PRETTY_FUNCTION__))
;
230 MIB.addReg(VRBase, RegState::Define);
231 }
232
233 if (!VRBase && !IsClone && !IsCloned)
234 for (SDNode *User : Node->uses()) {
235 if (User->getOpcode() == ISD::CopyToReg &&
236 User->getOperand(2).getNode() == Node &&
237 User->getOperand(2).getResNo() == i) {
238 unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
239 if (Register::isVirtualRegister(Reg)) {
240 const TargetRegisterClass *RegRC = MRI->getRegClass(Reg);
241 if (RegRC == RC) {
242 VRBase = Reg;
243 MIB.addReg(VRBase, RegState::Define);
244 break;
245 }
246 }
247 }
248 }
249
250 // Create the result registers for this node and add the result regs to
251 // the machine instruction.
252 if (VRBase == 0) {
253 assert(RC && "Isn't a register operand!")(static_cast <bool> (RC && "Isn't a register operand!"
) ? void (0) : __assert_fail ("RC && \"Isn't a register operand!\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp"
, 253, __extension__ __PRETTY_FUNCTION__))
;
254 VRBase = MRI->createVirtualRegister(RC);
255 MIB.addReg(VRBase, RegState::Define);
256 }
257
258 // If this def corresponds to a result of the SDNode insert the VRBase into
259 // the lookup map.
260 if (i < NumResults) {
261 SDValue Op(Node, i);
262 if (IsClone)
263 VRBaseMap.erase(Op);
264 bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second;
265 (void)isNew; // Silence compiler warning.
266 assert(isNew && "Node emitted out of order - early")(static_cast <bool> (isNew && "Node emitted out of order - early"
) ? void (0) : __assert_fail ("isNew && \"Node emitted out of order - early\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp"
, 266, __extension__ __PRETTY_FUNCTION__))
;
267 }
268 }
269}
270
271/// getVR - Return the virtual register corresponding to the specified result
272/// of the specified node.
273Register InstrEmitter::getVR(SDValue Op,
274 DenseMap<SDValue, Register> &VRBaseMap) {
275 if (Op.isMachineOpcode() &&
6
Calling 'SDValue::isMachineOpcode'
276 Op.getMachineOpcode() == TargetOpcode::IMPLICIT_DEF) {
277 // Add an IMPLICIT_DEF instruction before every use.
278 // IMPLICIT_DEF can produce any type of result so its MCInstrDesc
279 // does not include operand register class info.
280 const TargetRegisterClass *RC = TLI->getRegClassFor(
281 Op.getSimpleValueType(), Op.getNode()->isDivergent());
282 Register VReg = MRI->createVirtualRegister(RC);
283 BuildMI(*MBB, InsertPos, Op.getDebugLoc(),
284 TII->get(TargetOpcode::IMPLICIT_DEF), VReg);
285 return VReg;
286 }
287
288 DenseMap<SDValue, Register>::iterator I = VRBaseMap.find(Op);
289 assert(I != VRBaseMap.end() && "Node emitted out of order - late")(static_cast <bool> (I != VRBaseMap.end() && "Node emitted out of order - late"
) ? void (0) : __assert_fail ("I != VRBaseMap.end() && \"Node emitted out of order - late\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp"
, 289, __extension__ __PRETTY_FUNCTION__))
;
290 return I->second;
291}
292
293
294/// AddRegisterOperand - Add the specified register as an operand to the
295/// specified machine instr. Insert register copies if the register is
296/// not in the required register class.
297void
298InstrEmitter::AddRegisterOperand(MachineInstrBuilder &MIB,
299 SDValue Op,
300 unsigned IIOpNum,
301 const MCInstrDesc *II,
302 DenseMap<SDValue, Register> &VRBaseMap,
303 bool IsDebug, bool IsClone, bool IsCloned) {
304 assert(Op.getValueType() != MVT::Other &&(static_cast <bool> (Op.getValueType() != MVT::Other &&
Op.getValueType() != MVT::Glue && "Chain and glue operands should occur at end of operand list!"
) ? void (0) : __assert_fail ("Op.getValueType() != MVT::Other && Op.getValueType() != MVT::Glue && \"Chain and glue operands should occur at end of operand list!\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp"
, 306, __extension__ __PRETTY_FUNCTION__))
305 Op.getValueType() != MVT::Glue &&(static_cast <bool> (Op.getValueType() != MVT::Other &&
Op.getValueType() != MVT::Glue && "Chain and glue operands should occur at end of operand list!"
) ? void (0) : __assert_fail ("Op.getValueType() != MVT::Other && Op.getValueType() != MVT::Glue && \"Chain and glue operands should occur at end of operand list!\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp"
, 306, __extension__ __PRETTY_FUNCTION__))
306 "Chain and glue operands should occur at end of operand list!")(static_cast <bool> (Op.getValueType() != MVT::Other &&
Op.getValueType() != MVT::Glue && "Chain and glue operands should occur at end of operand list!"
) ? void (0) : __assert_fail ("Op.getValueType() != MVT::Other && Op.getValueType() != MVT::Glue && \"Chain and glue operands should occur at end of operand list!\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp"
, 306, __extension__ __PRETTY_FUNCTION__))
;
307 // Get/emit the operand.
308 Register VReg = getVR(Op, VRBaseMap);
309
310 const MCInstrDesc &MCID = MIB->getDesc();
311 bool isOptDef = IIOpNum < MCID.getNumOperands() &&
312 MCID.OpInfo[IIOpNum].isOptionalDef();
313
314 // If the instruction requires a register in a different class, create
315 // a new virtual register and copy the value into it, but first attempt to
316 // shrink VReg's register class within reason. For example, if VReg == GR32
317 // and II requires a GR32_NOSP, just constrain VReg to GR32_NOSP.
318 if (II) {
319 const TargetRegisterClass *OpRC = nullptr;
320 if (IIOpNum < II->getNumOperands())
321 OpRC = TII->getRegClass(*II, IIOpNum, TRI, *MF);
322
323 if (OpRC) {
324 const TargetRegisterClass *ConstrainedRC
325 = MRI->constrainRegClass(VReg, OpRC, MinRCSize);
326 if (!ConstrainedRC) {
327 OpRC = TRI->getAllocatableClass(OpRC);
328 assert(OpRC && "Constraints cannot be fulfilled for allocation")(static_cast <bool> (OpRC && "Constraints cannot be fulfilled for allocation"
) ? void (0) : __assert_fail ("OpRC && \"Constraints cannot be fulfilled for allocation\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp"
, 328, __extension__ __PRETTY_FUNCTION__))
;
329 Register NewVReg = MRI->createVirtualRegister(OpRC);
330 BuildMI(*MBB, InsertPos, Op.getNode()->getDebugLoc(),
331 TII->get(TargetOpcode::COPY), NewVReg).addReg(VReg);
332 VReg = NewVReg;
333 } else {
334 assert(ConstrainedRC->isAllocatable() &&(static_cast <bool> (ConstrainedRC->isAllocatable() &&
"Constraining an allocatable VReg produced an unallocatable class?"
) ? void (0) : __assert_fail ("ConstrainedRC->isAllocatable() && \"Constraining an allocatable VReg produced an unallocatable class?\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp"
, 335, __extension__ __PRETTY_FUNCTION__))
335 "Constraining an allocatable VReg produced an unallocatable class?")(static_cast <bool> (ConstrainedRC->isAllocatable() &&
"Constraining an allocatable VReg produced an unallocatable class?"
) ? void (0) : __assert_fail ("ConstrainedRC->isAllocatable() && \"Constraining an allocatable VReg produced an unallocatable class?\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp"
, 335, __extension__ __PRETTY_FUNCTION__))
;
336 }
337 }
338 }
339
340 // If this value has only one use, that use is a kill. This is a
341 // conservative approximation. InstrEmitter does trivial coalescing
342 // with CopyFromReg nodes, so don't emit kill flags for them.
343 // Avoid kill flags on Schedule cloned nodes, since there will be
344 // multiple uses.
345 // Tied operands are never killed, so we need to check that. And that
346 // means we need to determine the index of the operand.
347 bool isKill = Op.hasOneUse() &&
348 Op.getNode()->getOpcode() != ISD::CopyFromReg &&
349 !IsDebug &&
350 !(IsClone || IsCloned);
351 if (isKill) {
352 unsigned Idx = MIB->getNumOperands();
353 while (Idx > 0 &&
354 MIB->getOperand(Idx-1).isReg() &&
355 MIB->getOperand(Idx-1).isImplicit())
356 --Idx;
357 bool isTied = MCID.getOperandConstraint(Idx, MCOI::TIED_TO) != -1;
358 if (isTied)
359 isKill = false;
360 }
361
362 MIB.addReg(VReg, getDefRegState(isOptDef) | getKillRegState(isKill) |
363 getDebugRegState(IsDebug));
364}
365
366/// AddOperand - Add the specified operand to the specified machine instr. II
367/// specifies the instruction information for the node, and IIOpNum is the
368/// operand number (in the II) that we are adding.
369void InstrEmitter::AddOperand(MachineInstrBuilder &MIB,
370 SDValue Op,
371 unsigned IIOpNum,
372 const MCInstrDesc *II,
373 DenseMap<SDValue, Register> &VRBaseMap,
374 bool IsDebug, bool IsClone, bool IsCloned) {
375 if (Op.isMachineOpcode()) {
376 AddRegisterOperand(MIB, Op, IIOpNum, II, VRBaseMap,
377 IsDebug, IsClone, IsCloned);
378 } else if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
379 MIB.addImm(C->getSExtValue());
380 } else if (ConstantFPSDNode *F = dyn_cast<ConstantFPSDNode>(Op)) {
381 MIB.addFPImm(F->getConstantFPValue());
382 } else if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(Op)) {
383 Register VReg = R->getReg();
384 MVT OpVT = Op.getSimpleValueType();
385 const TargetRegisterClass *IIRC =
386 II ? TRI->getAllocatableClass(TII->getRegClass(*II, IIOpNum, TRI, *MF))
387 : nullptr;
388 const TargetRegisterClass *OpRC =
389 TLI->isTypeLegal(OpVT)
390 ? TLI->getRegClassFor(OpVT,
391 Op.getNode()->isDivergent() ||
392 (IIRC && TRI->isDivergentRegClass(IIRC)))
393 : nullptr;
394
395 if (OpRC && IIRC && OpRC != IIRC && Register::isVirtualRegister(VReg)) {
396 Register NewVReg = MRI->createVirtualRegister(IIRC);
397 BuildMI(*MBB, InsertPos, Op.getNode()->getDebugLoc(),
398 TII->get(TargetOpcode::COPY), NewVReg).addReg(VReg);
399 VReg = NewVReg;
400 }
401 // Turn additional physreg operands into implicit uses on non-variadic
402 // instructions. This is used by call and return instructions passing
403 // arguments in registers.
404 bool Imp = II && (IIOpNum >= II->getNumOperands() && !II->isVariadic());
405 MIB.addReg(VReg, getImplRegState(Imp));
406 } else if (RegisterMaskSDNode *RM = dyn_cast<RegisterMaskSDNode>(Op)) {
407 MIB.addRegMask(RM->getRegMask());
408 } else if (GlobalAddressSDNode *TGA = dyn_cast<GlobalAddressSDNode>(Op)) {
409 MIB.addGlobalAddress(TGA->getGlobal(), TGA->getOffset(),
410 TGA->getTargetFlags());
411 } else if (BasicBlockSDNode *BBNode = dyn_cast<BasicBlockSDNode>(Op)) {
412 MIB.addMBB(BBNode->getBasicBlock());
413 } else if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Op)) {
414 MIB.addFrameIndex(FI->getIndex());
415 } else if (JumpTableSDNode *JT = dyn_cast<JumpTableSDNode>(Op)) {
416 MIB.addJumpTableIndex(JT->getIndex(), JT->getTargetFlags());
417 } else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op)) {
418 int Offset = CP->getOffset();
419 Align Alignment = CP->getAlign();
420
421 unsigned Idx;
422 MachineConstantPool *MCP = MF->getConstantPool();
423 if (CP->isMachineConstantPoolEntry())
424 Idx = MCP->getConstantPoolIndex(CP->getMachineCPVal(), Alignment);
425 else
426 Idx = MCP->getConstantPoolIndex(CP->getConstVal(), Alignment);
427 MIB.addConstantPoolIndex(Idx, Offset, CP->getTargetFlags());
428 } else if (ExternalSymbolSDNode *ES = dyn_cast<ExternalSymbolSDNode>(Op)) {
429 MIB.addExternalSymbol(ES->getSymbol(), ES->getTargetFlags());
430 } else if (auto *SymNode = dyn_cast<MCSymbolSDNode>(Op)) {
431 MIB.addSym(SymNode->getMCSymbol());
432 } else if (BlockAddressSDNode *BA = dyn_cast<BlockAddressSDNode>(Op)) {
433 MIB.addBlockAddress(BA->getBlockAddress(),
434 BA->getOffset(),
435 BA->getTargetFlags());
436 } else if (TargetIndexSDNode *TI = dyn_cast<TargetIndexSDNode>(Op)) {
437 MIB.addTargetIndex(TI->getIndex(), TI->getOffset(), TI->getTargetFlags());
438 } else {
439 assert(Op.getValueType() != MVT::Other &&(static_cast <bool> (Op.getValueType() != MVT::Other &&
Op.getValueType() != MVT::Glue && "Chain and glue operands should occur at end of operand list!"
) ? void (0) : __assert_fail ("Op.getValueType() != MVT::Other && Op.getValueType() != MVT::Glue && \"Chain and glue operands should occur at end of operand list!\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp"
, 441, __extension__ __PRETTY_FUNCTION__))
440 Op.getValueType() != MVT::Glue &&(static_cast <bool> (Op.getValueType() != MVT::Other &&
Op.getValueType() != MVT::Glue && "Chain and glue operands should occur at end of operand list!"
) ? void (0) : __assert_fail ("Op.getValueType() != MVT::Other && Op.getValueType() != MVT::Glue && \"Chain and glue operands should occur at end of operand list!\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp"
, 441, __extension__ __PRETTY_FUNCTION__))
441 "Chain and glue operands should occur at end of operand list!")(static_cast <bool> (Op.getValueType() != MVT::Other &&
Op.getValueType() != MVT::Glue && "Chain and glue operands should occur at end of operand list!"
) ? void (0) : __assert_fail ("Op.getValueType() != MVT::Other && Op.getValueType() != MVT::Glue && \"Chain and glue operands should occur at end of operand list!\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp"
, 441, __extension__ __PRETTY_FUNCTION__))
;
442 AddRegisterOperand(MIB, Op, IIOpNum, II, VRBaseMap,
443 IsDebug, IsClone, IsCloned);
444 }
445}
446
447Register InstrEmitter::ConstrainForSubReg(Register VReg, unsigned SubIdx,
448 MVT VT, bool isDivergent, const DebugLoc &DL) {
449 const TargetRegisterClass *VRC = MRI->getRegClass(VReg);
450 const TargetRegisterClass *RC = TRI->getSubClassWithSubReg(VRC, SubIdx);
451
452 // RC is a sub-class of VRC that supports SubIdx. Try to constrain VReg
453 // within reason.
454 if (RC && RC != VRC)
455 RC = MRI->constrainRegClass(VReg, RC, MinRCSize);
456
457 // VReg has been adjusted. It can be used with SubIdx operands now.
458 if (RC)
459 return VReg;
460
461 // VReg couldn't be reasonably constrained. Emit a COPY to a new virtual
462 // register instead.
463 RC = TRI->getSubClassWithSubReg(TLI->getRegClassFor(VT, isDivergent), SubIdx);
464 assert(RC && "No legal register class for VT supports that SubIdx")(static_cast <bool> (RC && "No legal register class for VT supports that SubIdx"
) ? void (0) : __assert_fail ("RC && \"No legal register class for VT supports that SubIdx\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp"
, 464, __extension__ __PRETTY_FUNCTION__))
;
465 Register NewReg = MRI->createVirtualRegister(RC);
466 BuildMI(*MBB, InsertPos, DL, TII->get(TargetOpcode::COPY), NewReg)
467 .addReg(VReg);
468 return NewReg;
469}
470
471/// EmitSubregNode - Generate machine code for subreg nodes.
472///
473void InstrEmitter::EmitSubregNode(SDNode *Node,
474 DenseMap<SDValue, Register> &VRBaseMap,
475 bool IsClone, bool IsCloned) {
476 Register VRBase;
477 unsigned Opc = Node->getMachineOpcode();
478
479 // If the node is only used by a CopyToReg and the dest reg is a vreg, use
480 // the CopyToReg'd destination register instead of creating a new vreg.
481 for (SDNode *User : Node->uses()) {
482 if (User->getOpcode() == ISD::CopyToReg &&
483 User->getOperand(2).getNode() == Node) {
484 Register DestReg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
485 if (DestReg.isVirtual()) {
486 VRBase = DestReg;
487 break;
488 }
489 }
490 }
491
492 if (Opc == TargetOpcode::EXTRACT_SUBREG) {
493 // EXTRACT_SUBREG is lowered as %dst = COPY %src:sub. There are no
494 // constraints on the %dst register, COPY can target all legal register
495 // classes.
496 unsigned SubIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();
497 const TargetRegisterClass *TRC =
498 TLI->getRegClassFor(Node->getSimpleValueType(0), Node->isDivergent());
499
500 Register Reg;
501 MachineInstr *DefMI;
502 RegisterSDNode *R = dyn_cast<RegisterSDNode>(Node->getOperand(0));
503 if (R && Register::isPhysicalRegister(R->getReg())) {
504 Reg = R->getReg();
505 DefMI = nullptr;
506 } else {
507 Reg = R ? R->getReg() : getVR(Node->getOperand(0), VRBaseMap);
508 DefMI = MRI->getVRegDef(Reg);
509 }
510
511 Register SrcReg, DstReg;
512 unsigned DefSubIdx;
513 if (DefMI &&
514 TII->isCoalescableExtInstr(*DefMI, SrcReg, DstReg, DefSubIdx) &&
515 SubIdx == DefSubIdx &&
516 TRC == MRI->getRegClass(SrcReg)) {
517 // Optimize these:
518 // r1025 = s/zext r1024, 4
519 // r1026 = extract_subreg r1025, 4
520 // to a copy
521 // r1026 = copy r1024
522 VRBase = MRI->createVirtualRegister(TRC);
523 BuildMI(*MBB, InsertPos, Node->getDebugLoc(),
524 TII->get(TargetOpcode::COPY), VRBase).addReg(SrcReg);
525 MRI->clearKillFlags(SrcReg);
526 } else {
527 // Reg may not support a SubIdx sub-register, and we may need to
528 // constrain its register class or issue a COPY to a compatible register
529 // class.
530 if (Reg.isVirtual())
531 Reg = ConstrainForSubReg(Reg, SubIdx,
532 Node->getOperand(0).getSimpleValueType(),
533 Node->isDivergent(), Node->getDebugLoc());
534 // Create the destreg if it is missing.
535 if (!VRBase)
536 VRBase = MRI->createVirtualRegister(TRC);
537
538 // Create the extract_subreg machine instruction.
539 MachineInstrBuilder CopyMI =
540 BuildMI(*MBB, InsertPos, Node->getDebugLoc(),
541 TII->get(TargetOpcode::COPY), VRBase);
542 if (Reg.isVirtual())
543 CopyMI.addReg(Reg, 0, SubIdx);
544 else
545 CopyMI.addReg(TRI->getSubReg(Reg, SubIdx));
546 }
547 } else if (Opc == TargetOpcode::INSERT_SUBREG ||
548 Opc == TargetOpcode::SUBREG_TO_REG) {
549 SDValue N0 = Node->getOperand(0);
550 SDValue N1 = Node->getOperand(1);
551 SDValue N2 = Node->getOperand(2);
552 unsigned SubIdx = cast<ConstantSDNode>(N2)->getZExtValue();
553
554 // Figure out the register class to create for the destreg. It should be
555 // the largest legal register class supporting SubIdx sub-registers.
556 // RegisterCoalescer will constrain it further if it decides to eliminate
557 // the INSERT_SUBREG instruction.
558 //
559 // %dst = INSERT_SUBREG %src, %sub, SubIdx
560 //
561 // is lowered by TwoAddressInstructionPass to:
562 //
563 // %dst = COPY %src
564 // %dst:SubIdx = COPY %sub
565 //
566 // There is no constraint on the %src register class.
567 //
568 const TargetRegisterClass *SRC =
569 TLI->getRegClassFor(Node->getSimpleValueType(0), Node->isDivergent());
570 SRC = TRI->getSubClassWithSubReg(SRC, SubIdx);
571 assert(SRC && "No register class supports VT and SubIdx for INSERT_SUBREG")(static_cast <bool> (SRC && "No register class supports VT and SubIdx for INSERT_SUBREG"
) ? void (0) : __assert_fail ("SRC && \"No register class supports VT and SubIdx for INSERT_SUBREG\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp"
, 571, __extension__ __PRETTY_FUNCTION__))
;
572
573 if (VRBase == 0 || !SRC->hasSubClassEq(MRI->getRegClass(VRBase)))
574 VRBase = MRI->createVirtualRegister(SRC);
575
576 // Create the insert_subreg or subreg_to_reg machine instruction.
577 MachineInstrBuilder MIB =
578 BuildMI(*MF, Node->getDebugLoc(), TII->get(Opc), VRBase);
579
580 // If creating a subreg_to_reg, then the first input operand
581 // is an implicit value immediate, otherwise it's a register
582 if (Opc == TargetOpcode::SUBREG_TO_REG) {
583 const ConstantSDNode *SD = cast<ConstantSDNode>(N0);
584 MIB.addImm(SD->getZExtValue());
585 } else
586 AddOperand(MIB, N0, 0, nullptr, VRBaseMap, /*IsDebug=*/false,
587 IsClone, IsCloned);
588 // Add the subregister being inserted
589 AddOperand(MIB, N1, 0, nullptr, VRBaseMap, /*IsDebug=*/false,
590 IsClone, IsCloned);
591 MIB.addImm(SubIdx);
592 MBB->insert(InsertPos, MIB);
593 } else
594 llvm_unreachable("Node is not insert_subreg, extract_subreg, or subreg_to_reg")::llvm::llvm_unreachable_internal("Node is not insert_subreg, extract_subreg, or subreg_to_reg"
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp"
, 594)
;
595
596 SDValue Op(Node, 0);
597 bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second;
598 (void)isNew; // Silence compiler warning.
599 assert(isNew && "Node emitted out of order - early")(static_cast <bool> (isNew && "Node emitted out of order - early"
) ? void (0) : __assert_fail ("isNew && \"Node emitted out of order - early\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp"
, 599, __extension__ __PRETTY_FUNCTION__))
;
600}
601
602/// EmitCopyToRegClassNode - Generate machine code for COPY_TO_REGCLASS nodes.
603/// COPY_TO_REGCLASS is just a normal copy, except that the destination
604/// register is constrained to be in a particular register class.
605///
606void
607InstrEmitter::EmitCopyToRegClassNode(SDNode *Node,
608 DenseMap<SDValue, Register> &VRBaseMap) {
609 unsigned VReg = getVR(Node->getOperand(0), VRBaseMap);
610
611 // Create the new VReg in the destination class and emit a copy.
612 unsigned DstRCIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();
613 const TargetRegisterClass *DstRC =
614 TRI->getAllocatableClass(TRI->getRegClass(DstRCIdx));
615 Register NewVReg = MRI->createVirtualRegister(DstRC);
616 BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TargetOpcode::COPY),
617 NewVReg).addReg(VReg);
618
619 SDValue Op(Node, 0);
620 bool isNew = VRBaseMap.insert(std::make_pair(Op, NewVReg)).second;
621 (void)isNew; // Silence compiler warning.
622 assert(isNew && "Node emitted out of order - early")(static_cast <bool> (isNew && "Node emitted out of order - early"
) ? void (0) : __assert_fail ("isNew && \"Node emitted out of order - early\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp"
, 622, __extension__ __PRETTY_FUNCTION__))
;
623}
624
625/// EmitRegSequence - Generate machine code for REG_SEQUENCE nodes.
626///
627void InstrEmitter::EmitRegSequence(SDNode *Node,
628 DenseMap<SDValue, Register> &VRBaseMap,
629 bool IsClone, bool IsCloned) {
630 unsigned DstRCIdx = cast<ConstantSDNode>(Node->getOperand(0))->getZExtValue();
631 const TargetRegisterClass *RC = TRI->getRegClass(DstRCIdx);
632 Register NewVReg = MRI->createVirtualRegister(TRI->getAllocatableClass(RC));
633 const MCInstrDesc &II = TII->get(TargetOpcode::REG_SEQUENCE);
634 MachineInstrBuilder MIB = BuildMI(*MF, Node->getDebugLoc(), II, NewVReg);
635 unsigned NumOps = Node->getNumOperands();
636 // If the input pattern has a chain, then the root of the corresponding
637 // output pattern will get a chain as well. This can happen to be a
638 // REG_SEQUENCE (which is not "guarded" by countOperands/CountResults).
639 if (NumOps && Node->getOperand(NumOps-1).getValueType() == MVT::Other)
640 --NumOps; // Ignore chain if it exists.
641
642 assert((NumOps & 1) == 1 &&(static_cast <bool> ((NumOps & 1) == 1 && "REG_SEQUENCE must have an odd number of operands!"
) ? void (0) : __assert_fail ("(NumOps & 1) == 1 && \"REG_SEQUENCE must have an odd number of operands!\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp"
, 643, __extension__ __PRETTY_FUNCTION__))
643 "REG_SEQUENCE must have an odd number of operands!")(static_cast <bool> ((NumOps & 1) == 1 && "REG_SEQUENCE must have an odd number of operands!"
) ? void (0) : __assert_fail ("(NumOps & 1) == 1 && \"REG_SEQUENCE must have an odd number of operands!\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp"
, 643, __extension__ __PRETTY_FUNCTION__))
;
644 for (unsigned i = 1; i != NumOps; ++i) {
645 SDValue Op = Node->getOperand(i);
646 if ((i & 1) == 0) {
647 RegisterSDNode *R = dyn_cast<RegisterSDNode>(Node->getOperand(i-1));
648 // Skip physical registers as they don't have a vreg to get and we'll
649 // insert copies for them in TwoAddressInstructionPass anyway.
650 if (!R || !Register::isPhysicalRegister(R->getReg())) {
651 unsigned SubIdx = cast<ConstantSDNode>(Op)->getZExtValue();
652 unsigned SubReg = getVR(Node->getOperand(i-1), VRBaseMap);
653 const TargetRegisterClass *TRC = MRI->getRegClass(SubReg);
654 const TargetRegisterClass *SRC =
655 TRI->getMatchingSuperRegClass(RC, TRC, SubIdx);
656 if (SRC && SRC != RC) {
657 MRI->setRegClass(NewVReg, SRC);
658 RC = SRC;
659 }
660 }
661 }
662 AddOperand(MIB, Op, i+1, &II, VRBaseMap, /*IsDebug=*/false,
663 IsClone, IsCloned);
664 }
665
666 MBB->insert(InsertPos, MIB);
667 SDValue Op(Node, 0);
668 bool isNew = VRBaseMap.insert(std::make_pair(Op, NewVReg)).second;
669 (void)isNew; // Silence compiler warning.
670 assert(isNew && "Node emitted out of order - early")(static_cast <bool> (isNew && "Node emitted out of order - early"
) ? void (0) : __assert_fail ("isNew && \"Node emitted out of order - early\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp"
, 670, __extension__ __PRETTY_FUNCTION__))
;
671}
672
673/// EmitDbgValue - Generate machine instruction for a dbg_value node.
674///
675MachineInstr *
676InstrEmitter::EmitDbgValue(SDDbgValue *SD,
677 DenseMap<SDValue, Register> &VRBaseMap) {
678 MDNode *Var = SD->getVariable();
679 MDNode *Expr = SD->getExpression();
680 DebugLoc DL = SD->getDebugLoc();
681 assert(cast<DILocalVariable>(Var)->isValidLocationForIntrinsic(DL) &&(static_cast <bool> (cast<DILocalVariable>(Var)->
isValidLocationForIntrinsic(DL) && "Expected inlined-at fields to agree"
) ? void (0) : __assert_fail ("cast<DILocalVariable>(Var)->isValidLocationForIntrinsic(DL) && \"Expected inlined-at fields to agree\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp"
, 682, __extension__ __PRETTY_FUNCTION__))
682 "Expected inlined-at fields to agree")(static_cast <bool> (cast<DILocalVariable>(Var)->
isValidLocationForIntrinsic(DL) && "Expected inlined-at fields to agree"
) ? void (0) : __assert_fail ("cast<DILocalVariable>(Var)->isValidLocationForIntrinsic(DL) && \"Expected inlined-at fields to agree\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp"
, 682, __extension__ __PRETTY_FUNCTION__))
;
683
684 SD->setIsEmitted();
685
686 ArrayRef<SDDbgOperand> LocationOps = SD->getLocationOps();
687 assert(!LocationOps.empty() && "dbg_value with no location operands?")(static_cast <bool> (!LocationOps.empty() && "dbg_value with no location operands?"
) ? void (0) : __assert_fail ("!LocationOps.empty() && \"dbg_value with no location operands?\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp"
, 687, __extension__ __PRETTY_FUNCTION__))
;
688
689 if (SD->isInvalidated())
690 return EmitDbgNoLocation(SD);
691
692 // Emit variadic dbg_value nodes as DBG_VALUE_LIST.
693 if (SD->isVariadic()) {
694 // DBG_VALUE_LIST := "DBG_VALUE_LIST" var, expression, loc (, loc)*
695 const MCInstrDesc &DbgValDesc = TII->get(TargetOpcode::DBG_VALUE_LIST);
696 // Build the DBG_VALUE_LIST instruction base.
697 auto MIB = BuildMI(*MF, DL, DbgValDesc);
698 MIB.addMetadata(Var);
699 MIB.addMetadata(Expr);
700 AddDbgValueLocationOps(MIB, DbgValDesc, LocationOps, VRBaseMap);
701 return &*MIB;
702 }
703
704 // Attempt to produce a DBG_INSTR_REF if we've been asked to.
705 // We currently exclude the possibility of instruction references for
706 // variadic nodes; if at some point we enable them, this should be moved
707 // above the variadic block.
708 if (EmitDebugInstrRefs)
709 if (auto *InstrRef = EmitDbgInstrRef(SD, VRBaseMap))
710 return InstrRef;
711
712 return EmitDbgValueFromSingleOp(SD, VRBaseMap);
713}
714
715void InstrEmitter::AddDbgValueLocationOps(
716 MachineInstrBuilder &MIB, const MCInstrDesc &DbgValDesc,
717 ArrayRef<SDDbgOperand> LocationOps,
718 DenseMap<SDValue, Register> &VRBaseMap) {
719 for (const SDDbgOperand &Op : LocationOps) {
720 switch (Op.getKind()) {
721 case SDDbgOperand::FRAMEIX:
722 MIB.addFrameIndex(Op.getFrameIx());
723 break;
724 case SDDbgOperand::VREG:
725 MIB.addReg(Op.getVReg(), RegState::Debug);
726 break;
727 case SDDbgOperand::SDNODE: {
728 SDValue V = SDValue(Op.getSDNode(), Op.getResNo());
729 // It's possible we replaced this SDNode with other(s) and therefore
730 // didn't generate code for it. It's better to catch these cases where
731 // they happen and transfer the debug info, but trying to guarantee that
732 // in all cases would be very fragile; this is a safeguard for any
733 // that were missed.
734 if (VRBaseMap.count(V) == 0)
735 MIB.addReg(0U); // undef
736 else
737 AddOperand(MIB, V, (*MIB).getNumOperands(), &DbgValDesc, VRBaseMap,
738 /*IsDebug=*/true, /*IsClone=*/false, /*IsCloned=*/false);
739 } break;
740 case SDDbgOperand::CONST: {
741 const Value *V = Op.getConst();
742 if (const ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
743 if (CI->getBitWidth() > 64)
744 MIB.addCImm(CI);
745 else
746 MIB.addImm(CI->getSExtValue());
747 } else if (const ConstantFP *CF = dyn_cast<ConstantFP>(V)) {
748 MIB.addFPImm(CF);
749 } else if (isa<ConstantPointerNull>(V)) {
750 // Note: This assumes that all nullptr constants are zero-valued.
751 MIB.addImm(0);
752 } else {
753 // Could be an Undef. In any case insert an Undef so we can see what we
754 // dropped.
755 MIB.addReg(0U);
756 }
757 } break;
758 }
759 }
760}
761
762MachineInstr *
763InstrEmitter::EmitDbgInstrRef(SDDbgValue *SD,
764 DenseMap<SDValue, Register> &VRBaseMap) {
765 assert(!SD->isVariadic())(static_cast <bool> (!SD->isVariadic()) ? void (0) :
__assert_fail ("!SD->isVariadic()", "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp"
, 765, __extension__ __PRETTY_FUNCTION__))
;
766 SDDbgOperand DbgOperand = SD->getLocationOps()[0];
767 MDNode *Var = SD->getVariable();
768 MDNode *Expr = SD->getExpression();
769 DebugLoc DL = SD->getDebugLoc();
770 const MCInstrDesc &RefII = TII->get(TargetOpcode::DBG_INSTR_REF);
771
772 // Handle variable locations that don't actually depend on the instructions
773 // in the program: constants and stack locations.
774 if (DbgOperand.getKind() == SDDbgOperand::FRAMEIX ||
775 DbgOperand.getKind() == SDDbgOperand::CONST)
776 return EmitDbgValueFromSingleOp(SD, VRBaseMap);
777
778 // It may not be immediately possible to identify the MachineInstr that
779 // defines a VReg, it can depend for example on the order blocks are
780 // emitted in. When this happens, or when further analysis is needed later,
781 // produce an instruction like this:
782 //
783 // DBG_INSTR_REF %0:gr64, 0, !123, !456
784 //
785 // i.e., point the instruction at the vreg, and patch it up later in
786 // MachineFunction::finalizeDebugInstrRefs.
787 auto EmitHalfDoneInstrRef = [&](unsigned VReg) -> MachineInstr * {
788 auto MIB = BuildMI(*MF, DL, RefII);
789 MIB.addReg(VReg);
790 MIB.addImm(0);
791 MIB.addMetadata(Var);
792 MIB.addMetadata(Expr);
793 return MIB;
794 };
795
796 // Try to find both the defined register and the instruction defining it.
797 MachineInstr *DefMI = nullptr;
798 unsigned VReg;
799
800 if (DbgOperand.getKind() == SDDbgOperand::VREG) {
801 VReg = DbgOperand.getVReg();
802
803 // No definition means that block hasn't been emitted yet. Leave a vreg
804 // reference to be fixed later.
805 if (!MRI->hasOneDef(VReg))
806 return EmitHalfDoneInstrRef(VReg);
807
808 DefMI = &*MRI->def_instr_begin(VReg);
809 } else {
810 assert(DbgOperand.getKind() == SDDbgOperand::SDNODE)(static_cast <bool> (DbgOperand.getKind() == SDDbgOperand
::SDNODE) ? void (0) : __assert_fail ("DbgOperand.getKind() == SDDbgOperand::SDNODE"
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp"
, 810, __extension__ __PRETTY_FUNCTION__))
;
811 // Look up the corresponding VReg for the given SDNode, if any.
812 SDNode *Node = DbgOperand.getSDNode();
813 SDValue Op = SDValue(Node, DbgOperand.getResNo());
814 DenseMap<SDValue, Register>::iterator I = VRBaseMap.find(Op);
815 // No VReg -> produce a DBG_VALUE $noreg instead.
816 if (I==VRBaseMap.end())
817 return EmitDbgNoLocation(SD);
818
819 // Try to pick out a defining instruction at this point.
820 VReg = getVR(Op, VRBaseMap);
821
822 // Again, if there's no instruction defining the VReg right now, fix it up
823 // later.
824 if (!MRI->hasOneDef(VReg))
825 return EmitHalfDoneInstrRef(VReg);
826
827 DefMI = &*MRI->def_instr_begin(VReg);
828 }
829
830 // Avoid copy like instructions: they don't define values, only move them.
831 // Leave a virtual-register reference until it can be fixed up later, to find
832 // the underlying value definition.
833 if (DefMI->isCopyLike() || TII->isCopyInstr(*DefMI))
834 return EmitHalfDoneInstrRef(VReg);
835
836 auto MIB = BuildMI(*MF, DL, RefII);
837
838 // Find the operand number which defines the specified VReg.
839 unsigned OperandIdx = 0;
840 for (const auto &MO : DefMI->operands()) {
841 if (MO.isReg() && MO.isDef() && MO.getReg() == VReg)
842 break;
843 ++OperandIdx;
844 }
845 assert(OperandIdx < DefMI->getNumOperands())(static_cast <bool> (OperandIdx < DefMI->getNumOperands
()) ? void (0) : __assert_fail ("OperandIdx < DefMI->getNumOperands()"
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp"
, 845, __extension__ __PRETTY_FUNCTION__))
;
846
847 // Make the DBG_INSTR_REF refer to that instruction, and that operand.
848 unsigned InstrNum = DefMI->getDebugInstrNum();
849 MIB.addImm(InstrNum);
850 MIB.addImm(OperandIdx);
851 MIB.addMetadata(Var);
852 MIB.addMetadata(Expr);
853 return &*MIB;
854}
855
856MachineInstr *InstrEmitter::EmitDbgNoLocation(SDDbgValue *SD) {
857 // An invalidated SDNode must generate an undef DBG_VALUE: although the
858 // original value is no longer computed, earlier DBG_VALUEs live ranges
859 // must not leak into later code.
860 MDNode *Var = SD->getVariable();
861 MDNode *Expr = SD->getExpression();
862 DebugLoc DL = SD->getDebugLoc();
863 auto MIB = BuildMI(*MF, DL, TII->get(TargetOpcode::DBG_VALUE));
864 MIB.addReg(0U);
865 MIB.addReg(0U, RegState::Debug);
866 MIB.addMetadata(Var);
867 MIB.addMetadata(Expr);
868 return &*MIB;
869}
870
871MachineInstr *
872InstrEmitter::EmitDbgValueFromSingleOp(SDDbgValue *SD,
873 DenseMap<SDValue, Register> &VRBaseMap) {
874 MDNode *Var = SD->getVariable();
875 DIExpression *Expr = SD->getExpression();
876 DebugLoc DL = SD->getDebugLoc();
877 const MCInstrDesc &II = TII->get(TargetOpcode::DBG_VALUE);
878
879 assert(SD->getLocationOps().size() == 1 &&(static_cast <bool> (SD->getLocationOps().size() == 1
&& "Non variadic dbg_value should have only one location op"
) ? void (0) : __assert_fail ("SD->getLocationOps().size() == 1 && \"Non variadic dbg_value should have only one location op\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp"
, 880, __extension__ __PRETTY_FUNCTION__))
880 "Non variadic dbg_value should have only one location op")(static_cast <bool> (SD->getLocationOps().size() == 1
&& "Non variadic dbg_value should have only one location op"
) ? void (0) : __assert_fail ("SD->getLocationOps().size() == 1 && \"Non variadic dbg_value should have only one location op\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp"
, 880, __extension__ __PRETTY_FUNCTION__))
;
881
882 // See about constant-folding the expression.
883 // Copy the location operand in case we replace it.
884 SmallVector<SDDbgOperand, 1> LocationOps(1, SD->getLocationOps()[0]);
885 if (Expr && LocationOps[0].getKind() == SDDbgOperand::CONST) {
886 const Value *V = LocationOps[0].getConst();
887 if (auto *C = dyn_cast<ConstantInt>(V)) {
888 std::tie(Expr, C) = Expr->constantFold(C);
889 LocationOps[0] = SDDbgOperand::fromConst(C);
890 }
891 }
892
893 // Emit non-variadic dbg_value nodes as DBG_VALUE.
894 // DBG_VALUE := "DBG_VALUE" loc, isIndirect, var, expr
895 auto MIB = BuildMI(*MF, DL, II);
896 AddDbgValueLocationOps(MIB, II, LocationOps, VRBaseMap);
897
898 if (SD->isIndirect())
899 MIB.addImm(0U);
900 else
901 MIB.addReg(0U, RegState::Debug);
902
903 return MIB.addMetadata(Var).addMetadata(Expr);
904}
905
906MachineInstr *
907InstrEmitter::EmitDbgLabel(SDDbgLabel *SD) {
908 MDNode *Label = SD->getLabel();
909 DebugLoc DL = SD->getDebugLoc();
910 assert(cast<DILabel>(Label)->isValidLocationForIntrinsic(DL) &&(static_cast <bool> (cast<DILabel>(Label)->isValidLocationForIntrinsic
(DL) && "Expected inlined-at fields to agree") ? void
(0) : __assert_fail ("cast<DILabel>(Label)->isValidLocationForIntrinsic(DL) && \"Expected inlined-at fields to agree\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp"
, 911, __extension__ __PRETTY_FUNCTION__))
911 "Expected inlined-at fields to agree")(static_cast <bool> (cast<DILabel>(Label)->isValidLocationForIntrinsic
(DL) && "Expected inlined-at fields to agree") ? void
(0) : __assert_fail ("cast<DILabel>(Label)->isValidLocationForIntrinsic(DL) && \"Expected inlined-at fields to agree\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp"
, 911, __extension__ __PRETTY_FUNCTION__))
;
912
913 const MCInstrDesc &II = TII->get(TargetOpcode::DBG_LABEL);
914 MachineInstrBuilder MIB = BuildMI(*MF, DL, II);
915 MIB.addMetadata(Label);
916
917 return &*MIB;
918}
919
920/// EmitMachineNode - Generate machine code for a target-specific node and
921/// needed dependencies.
922///
923void InstrEmitter::
924EmitMachineNode(SDNode *Node, bool IsClone, bool IsCloned,
925 DenseMap<SDValue, Register> &VRBaseMap) {
926 unsigned Opc = Node->getMachineOpcode();
927
928 // Handle subreg insert/extract specially
929 if (Opc == TargetOpcode::EXTRACT_SUBREG ||
930 Opc == TargetOpcode::INSERT_SUBREG ||
931 Opc == TargetOpcode::SUBREG_TO_REG) {
932 EmitSubregNode(Node, VRBaseMap, IsClone, IsCloned);
933 return;
934 }
935
936 // Handle COPY_TO_REGCLASS specially.
937 if (Opc == TargetOpcode::COPY_TO_REGCLASS) {
938 EmitCopyToRegClassNode(Node, VRBaseMap);
939 return;
940 }
941
942 // Handle REG_SEQUENCE specially.
943 if (Opc == TargetOpcode::REG_SEQUENCE) {
944 EmitRegSequence(Node, VRBaseMap, IsClone, IsCloned);
945 return;
946 }
947
948 if (Opc == TargetOpcode::IMPLICIT_DEF)
949 // We want a unique VR for each IMPLICIT_DEF use.
950 return;
951
952 const MCInstrDesc &II = TII->get(Opc);
953 unsigned NumResults = CountResults(Node);
954 unsigned NumDefs = II.getNumDefs();
955 const MCPhysReg *ScratchRegs = nullptr;
956
957 // Handle STACKMAP and PATCHPOINT specially and then use the generic code.
958 if (Opc == TargetOpcode::STACKMAP || Opc == TargetOpcode::PATCHPOINT) {
959 // Stackmaps do not have arguments and do not preserve their calling
960 // convention. However, to simplify runtime support, they clobber the same
961 // scratch registers as AnyRegCC.
962 unsigned CC = CallingConv::AnyReg;
963 if (Opc == TargetOpcode::PATCHPOINT) {
964 CC = Node->getConstantOperandVal(PatchPointOpers::CCPos);
965 NumDefs = NumResults;
966 }
967 ScratchRegs = TLI->getScratchRegisters((CallingConv::ID) CC);
968 } else if (Opc == TargetOpcode::STATEPOINT) {
969 NumDefs = NumResults;
970 }
971
972 unsigned NumImpUses = 0;
973 unsigned NodeOperands =
974 countOperands(Node, II.getNumOperands() - NumDefs, NumImpUses);
975 bool HasVRegVariadicDefs = !MF->getTarget().usesPhysRegsForValues() &&
976 II.isVariadic() && II.variadicOpsAreDefs();
977 bool HasPhysRegOuts = NumResults > NumDefs &&
978 II.getImplicitDefs() != nullptr && !HasVRegVariadicDefs;
979#ifndef NDEBUG
980 unsigned NumMIOperands = NodeOperands + NumResults;
981 if (II.isVariadic())
982 assert(NumMIOperands >= II.getNumOperands() &&(static_cast <bool> (NumMIOperands >= II.getNumOperands
() && "Too few operands for a variadic node!") ? void
(0) : __assert_fail ("NumMIOperands >= II.getNumOperands() && \"Too few operands for a variadic node!\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp"
, 983, __extension__ __PRETTY_FUNCTION__))
983 "Too few operands for a variadic node!")(static_cast <bool> (NumMIOperands >= II.getNumOperands
() && "Too few operands for a variadic node!") ? void
(0) : __assert_fail ("NumMIOperands >= II.getNumOperands() && \"Too few operands for a variadic node!\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp"
, 983, __extension__ __PRETTY_FUNCTION__))
;
984 else
985 assert(NumMIOperands >= II.getNumOperands() &&(static_cast <bool> (NumMIOperands >= II.getNumOperands
() && NumMIOperands <= II.getNumOperands() + II.getNumImplicitDefs
() + NumImpUses && "#operands for dag node doesn't match .td file!"
) ? void (0) : __assert_fail ("NumMIOperands >= II.getNumOperands() && NumMIOperands <= II.getNumOperands() + II.getNumImplicitDefs() + NumImpUses && \"#operands for dag node doesn't match .td file!\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp"
, 988, __extension__ __PRETTY_FUNCTION__))
986 NumMIOperands <= II.getNumOperands() + II.getNumImplicitDefs() +(static_cast <bool> (NumMIOperands >= II.getNumOperands
() && NumMIOperands <= II.getNumOperands() + II.getNumImplicitDefs
() + NumImpUses && "#operands for dag node doesn't match .td file!"
) ? void (0) : __assert_fail ("NumMIOperands >= II.getNumOperands() && NumMIOperands <= II.getNumOperands() + II.getNumImplicitDefs() + NumImpUses && \"#operands for dag node doesn't match .td file!\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp"
, 988, __extension__ __PRETTY_FUNCTION__))
987 NumImpUses &&(static_cast <bool> (NumMIOperands >= II.getNumOperands
() && NumMIOperands <= II.getNumOperands() + II.getNumImplicitDefs
() + NumImpUses && "#operands for dag node doesn't match .td file!"
) ? void (0) : __assert_fail ("NumMIOperands >= II.getNumOperands() && NumMIOperands <= II.getNumOperands() + II.getNumImplicitDefs() + NumImpUses && \"#operands for dag node doesn't match .td file!\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp"
, 988, __extension__ __PRETTY_FUNCTION__))
988 "#operands for dag node doesn't match .td file!")(static_cast <bool> (NumMIOperands >= II.getNumOperands
() && NumMIOperands <= II.getNumOperands() + II.getNumImplicitDefs
() + NumImpUses && "#operands for dag node doesn't match .td file!"
) ? void (0) : __assert_fail ("NumMIOperands >= II.getNumOperands() && NumMIOperands <= II.getNumOperands() + II.getNumImplicitDefs() + NumImpUses && \"#operands for dag node doesn't match .td file!\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp"
, 988, __extension__ __PRETTY_FUNCTION__))
;
989#endif
990
991 // Create the new machine instruction.
992 MachineInstrBuilder MIB = BuildMI(*MF, Node->getDebugLoc(), II);
993
994 // Add result register values for things that are defined by this
995 // instruction.
996 if (NumResults) {
997 CreateVirtualRegisters(Node, MIB, II, IsClone, IsCloned, VRBaseMap);
998
999 // Transfer any IR flags from the SDNode to the MachineInstr
1000 MachineInstr *MI = MIB.getInstr();
1001 const SDNodeFlags Flags = Node->getFlags();
1002 if (Flags.hasNoSignedZeros())
1003 MI->setFlag(MachineInstr::MIFlag::FmNsz);
1004
1005 if (Flags.hasAllowReciprocal())
1006 MI->setFlag(MachineInstr::MIFlag::FmArcp);
1007
1008 if (Flags.hasNoNaNs())
1009 MI->setFlag(MachineInstr::MIFlag::FmNoNans);
1010
1011 if (Flags.hasNoInfs())
1012 MI->setFlag(MachineInstr::MIFlag::FmNoInfs);
1013
1014 if (Flags.hasAllowContract())
1015 MI->setFlag(MachineInstr::MIFlag::FmContract);
1016
1017 if (Flags.hasApproximateFuncs())
1018 MI->setFlag(MachineInstr::MIFlag::FmAfn);
1019
1020 if (Flags.hasAllowReassociation())
1021 MI->setFlag(MachineInstr::MIFlag::FmReassoc);
1022
1023 if (Flags.hasNoUnsignedWrap())
1024 MI->setFlag(MachineInstr::MIFlag::NoUWrap);
1025
1026 if (Flags.hasNoSignedWrap())
1027 MI->setFlag(MachineInstr::MIFlag::NoSWrap);
1028
1029 if (Flags.hasExact())
1030 MI->setFlag(MachineInstr::MIFlag::IsExact);
1031
1032 if (Flags.hasNoFPExcept())
1033 MI->setFlag(MachineInstr::MIFlag::NoFPExcept);
1034 }
1035
1036 // Emit all of the actual operands of this instruction, adding them to the
1037 // instruction as appropriate.
1038 bool HasOptPRefs = NumDefs > NumResults;
1039 assert((!HasOptPRefs || !HasPhysRegOuts) &&(static_cast <bool> ((!HasOptPRefs || !HasPhysRegOuts) &&
"Unable to cope with optional defs and phys regs defs!") ? void
(0) : __assert_fail ("(!HasOptPRefs || !HasPhysRegOuts) && \"Unable to cope with optional defs and phys regs defs!\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp"
, 1040, __extension__ __PRETTY_FUNCTION__))
1040 "Unable to cope with optional defs and phys regs defs!")(static_cast <bool> ((!HasOptPRefs || !HasPhysRegOuts) &&
"Unable to cope with optional defs and phys regs defs!") ? void
(0) : __assert_fail ("(!HasOptPRefs || !HasPhysRegOuts) && \"Unable to cope with optional defs and phys regs defs!\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp"
, 1040, __extension__ __PRETTY_FUNCTION__))
;
1041 unsigned NumSkip = HasOptPRefs ? NumDefs - NumResults : 0;
1042 for (unsigned i = NumSkip; i != NodeOperands; ++i)
1043 AddOperand(MIB, Node->getOperand(i), i-NumSkip+NumDefs, &II,
1044 VRBaseMap, /*IsDebug=*/false, IsClone, IsCloned);
1045
1046 // Add scratch registers as implicit def and early clobber
1047 if (ScratchRegs)
1048 for (unsigned i = 0; ScratchRegs[i]; ++i)
1049 MIB.addReg(ScratchRegs[i], RegState::ImplicitDefine |
1050 RegState::EarlyClobber);
1051
1052 // Set the memory reference descriptions of this instruction now that it is
1053 // part of the function.
1054 MIB.setMemRefs(cast<MachineSDNode>(Node)->memoperands());
1055
1056 // Insert the instruction into position in the block. This needs to
1057 // happen before any custom inserter hook is called so that the
1058 // hook knows where in the block to insert the replacement code.
1059 MBB->insert(InsertPos, MIB);
1060
1061 // The MachineInstr may also define physregs instead of virtregs. These
1062 // physreg values can reach other instructions in different ways:
1063 //
1064 // 1. When there is a use of a Node value beyond the explicitly defined
1065 // virtual registers, we emit a CopyFromReg for one of the implicitly
1066 // defined physregs. This only happens when HasPhysRegOuts is true.
1067 //
1068 // 2. A CopyFromReg reading a physreg may be glued to this instruction.
1069 //
1070 // 3. A glued instruction may implicitly use a physreg.
1071 //
1072 // 4. A glued instruction may use a RegisterSDNode operand.
1073 //
1074 // Collect all the used physreg defs, and make sure that any unused physreg
1075 // defs are marked as dead.
1076 SmallVector<Register, 8> UsedRegs;
1077
1078 // Additional results must be physical register defs.
1079 if (HasPhysRegOuts) {
1080 for (unsigned i = NumDefs; i < NumResults; ++i) {
1081 Register Reg = II.getImplicitDefs()[i - NumDefs];
1082 if (!Node->hasAnyUseOfValue(i))
1083 continue;
1084 // This implicitly defined physreg has a use.
1085 UsedRegs.push_back(Reg);
1086 EmitCopyFromReg(Node, i, IsClone, IsCloned, Reg, VRBaseMap);
1087 }
1088 }
1089
1090 // Scan the glue chain for any used physregs.
1091 if (Node->getValueType(Node->getNumValues()-1) == MVT::Glue) {
1092 for (SDNode *F = Node->getGluedUser(); F; F = F->getGluedUser()) {
1093 if (F->getOpcode() == ISD::CopyFromReg) {
1094 UsedRegs.push_back(cast<RegisterSDNode>(F->getOperand(1))->getReg());
1095 continue;
1096 } else if (F->getOpcode() == ISD::CopyToReg) {
1097 // Skip CopyToReg nodes that are internal to the glue chain.
1098 continue;
1099 }
1100 // Collect declared implicit uses.
1101 const MCInstrDesc &MCID = TII->get(F->getMachineOpcode());
1102 UsedRegs.append(MCID.getImplicitUses(),
1103 MCID.getImplicitUses() + MCID.getNumImplicitUses());
1104 // In addition to declared implicit uses, we must also check for
1105 // direct RegisterSDNode operands.
1106 for (unsigned i = 0, e = F->getNumOperands(); i != e; ++i)
1107 if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(F->getOperand(i))) {
1108 Register Reg = R->getReg();
1109 if (Reg.isPhysical())
1110 UsedRegs.push_back(Reg);
1111 }
1112 }
1113 }
1114
1115 // Finally mark unused registers as dead.
1116 if (!UsedRegs.empty() || II.getImplicitDefs() || II.hasOptionalDef())
1117 MIB->setPhysRegsDeadExcept(UsedRegs, *TRI);
1118
1119 // STATEPOINT is too 'dynamic' to have meaningful machine description.
1120 // We have to manually tie operands.
1121 if (Opc == TargetOpcode::STATEPOINT && NumDefs > 0) {
1122 assert(!HasPhysRegOuts && "STATEPOINT mishandled")(static_cast <bool> (!HasPhysRegOuts && "STATEPOINT mishandled"
) ? void (0) : __assert_fail ("!HasPhysRegOuts && \"STATEPOINT mishandled\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp"
, 1122, __extension__ __PRETTY_FUNCTION__))
;
1123 MachineInstr *MI = MIB;
1124 unsigned Def = 0;
1125 int First = StatepointOpers(MI).getFirstGCPtrIdx();
1126 assert(First > 0 && "Statepoint has Defs but no GC ptr list")(static_cast <bool> (First > 0 && "Statepoint has Defs but no GC ptr list"
) ? void (0) : __assert_fail ("First > 0 && \"Statepoint has Defs but no GC ptr list\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp"
, 1126, __extension__ __PRETTY_FUNCTION__))
;
1127 unsigned Use = (unsigned)First;
1128 while (Def < NumDefs) {
1129 if (MI->getOperand(Use).isReg())
1130 MI->tieOperands(Def++, Use);
1131 Use = StackMaps::getNextMetaArgIdx(MI, Use);
1132 }
1133 }
1134
1135 // Run post-isel target hook to adjust this instruction if needed.
1136 if (II.hasPostISelHook())
1137 TLI->AdjustInstrPostInstrSelection(*MIB, Node);
1138}
1139
1140/// EmitSpecialNode - Generate machine code for a target-independent node and
1141/// needed dependencies.
1142void InstrEmitter::
1143EmitSpecialNode(SDNode *Node, bool IsClone, bool IsCloned,
1144 DenseMap<SDValue, Register> &VRBaseMap) {
1145 switch (Node->getOpcode()) {
1
Control jumps to 'case CopyToReg:' at line 1156
1146 default:
1147#ifndef NDEBUG
1148 Node->dump();
1149#endif
1150 llvm_unreachable("This target-independent node should have been selected!")::llvm::llvm_unreachable_internal("This target-independent node should have been selected!"
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp"
, 1150)
;
1151 case ISD::EntryToken:
1152 llvm_unreachable("EntryToken should have been excluded from the schedule!")::llvm::llvm_unreachable_internal("EntryToken should have been excluded from the schedule!"
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp"
, 1152)
;
1153 case ISD::MERGE_VALUES:
1154 case ISD::TokenFactor: // fall thru
1155 break;
1156 case ISD::CopyToReg: {
1157 Register DestReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
1158 SDValue SrcVal = Node->getOperand(2);
1159 if (Register::isVirtualRegister(DestReg) && SrcVal.isMachineOpcode() &&
1160 SrcVal.getMachineOpcode() == TargetOpcode::IMPLICIT_DEF) {
1161 // Instead building a COPY to that vreg destination, build an
1162 // IMPLICIT_DEF instruction instead.
1163 BuildMI(*MBB, InsertPos, Node->getDebugLoc(),
1164 TII->get(TargetOpcode::IMPLICIT_DEF), DestReg);
1165 break;
1166 }
1167 Register SrcReg;
1168 if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(SrcVal))
2
Assuming 'R' is null
3
Taking false branch
1169 SrcReg = R->getReg();
1170 else
1171 SrcReg = getVR(SrcVal, VRBaseMap);
4
The value of 'SrcVal' is assigned to 'Op.Node'
5
Calling 'InstrEmitter::getVR'
1172
1173 if (SrcReg == DestReg) // Coalesced away the copy? Ignore.
1174 break;
1175
1176 BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TargetOpcode::COPY),
1177 DestReg).addReg(SrcReg);
1178 break;
1179 }
1180 case ISD::CopyFromReg: {
1181 unsigned SrcReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
1182 EmitCopyFromReg(Node, 0, IsClone, IsCloned, SrcReg, VRBaseMap);
1183 break;
1184 }
1185 case ISD::EH_LABEL:
1186 case ISD::ANNOTATION_LABEL: {
1187 unsigned Opc = (Node->getOpcode() == ISD::EH_LABEL)
1188 ? TargetOpcode::EH_LABEL
1189 : TargetOpcode::ANNOTATION_LABEL;
1190 MCSymbol *S = cast<LabelSDNode>(Node)->getLabel();
1191 BuildMI(*MBB, InsertPos, Node->getDebugLoc(),
1192 TII->get(Opc)).addSym(S);
1193 break;
1194 }
1195
1196 case ISD::LIFETIME_START:
1197 case ISD::LIFETIME_END: {
1198 unsigned TarOp = (Node->getOpcode() == ISD::LIFETIME_START)
1199 ? TargetOpcode::LIFETIME_START
1200 : TargetOpcode::LIFETIME_END;
1201 auto *FI = cast<FrameIndexSDNode>(Node->getOperand(1));
1202 BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TarOp))
1203 .addFrameIndex(FI->getIndex());
1204 break;
1205 }
1206
1207 case ISD::PSEUDO_PROBE: {
1208 unsigned TarOp = TargetOpcode::PSEUDO_PROBE;
1209 auto Guid = cast<PseudoProbeSDNode>(Node)->getGuid();
1210 auto Index = cast<PseudoProbeSDNode>(Node)->getIndex();
1211 auto Attr = cast<PseudoProbeSDNode>(Node)->getAttributes();
1212
1213 BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TarOp))
1214 .addImm(Guid)
1215 .addImm(Index)
1216 .addImm((uint8_t)PseudoProbeType::Block)
1217 .addImm(Attr);
1218 break;
1219 }
1220
1221 case ISD::INLINEASM:
1222 case ISD::INLINEASM_BR: {
1223 unsigned NumOps = Node->getNumOperands();
1224 if (Node->getOperand(NumOps-1).getValueType() == MVT::Glue)
1225 --NumOps; // Ignore the glue operand.
1226
1227 // Create the inline asm machine instruction.
1228 unsigned TgtOpc = Node->getOpcode() == ISD::INLINEASM_BR
1229 ? TargetOpcode::INLINEASM_BR
1230 : TargetOpcode::INLINEASM;
1231 MachineInstrBuilder MIB =
1232 BuildMI(*MF, Node->getDebugLoc(), TII->get(TgtOpc));
1233
1234 // Add the asm string as an external symbol operand.
1235 SDValue AsmStrV = Node->getOperand(InlineAsm::Op_AsmString);
1236 const char *AsmStr = cast<ExternalSymbolSDNode>(AsmStrV)->getSymbol();
1237 MIB.addExternalSymbol(AsmStr);
1238
1239 // Add the HasSideEffect, isAlignStack, AsmDialect, MayLoad and MayStore
1240 // bits.
1241 int64_t ExtraInfo =
1242 cast<ConstantSDNode>(Node->getOperand(InlineAsm::Op_ExtraInfo))->
1243 getZExtValue();
1244 MIB.addImm(ExtraInfo);
1245
1246 // Remember to operand index of the group flags.
1247 SmallVector<unsigned, 8> GroupIdx;
1248
1249 // Remember registers that are part of early-clobber defs.
1250 SmallVector<unsigned, 8> ECRegs;
1251
1252 // Add all of the operand registers to the instruction.
1253 for (unsigned i = InlineAsm::Op_FirstOperand; i != NumOps;) {
1254 unsigned Flags =
1255 cast<ConstantSDNode>(Node->getOperand(i))->getZExtValue();
1256 const unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
1257
1258 GroupIdx.push_back(MIB->getNumOperands());
1259 MIB.addImm(Flags);
1260 ++i; // Skip the ID value.
1261
1262 switch (InlineAsm::getKind(Flags)) {
1263 default: llvm_unreachable("Bad flags!")::llvm::llvm_unreachable_internal("Bad flags!", "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp"
, 1263)
;
1264 case InlineAsm::Kind_RegDef:
1265 for (unsigned j = 0; j != NumVals; ++j, ++i) {
1266 unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
1267 // FIXME: Add dead flags for physical and virtual registers defined.
1268 // For now, mark physical register defs as implicit to help fast
1269 // regalloc. This makes inline asm look a lot like calls.
1270 MIB.addReg(Reg,
1271 RegState::Define |
1272 getImplRegState(Register::isPhysicalRegister(Reg)));
1273 }
1274 break;
1275 case InlineAsm::Kind_RegDefEarlyClobber:
1276 case InlineAsm::Kind_Clobber:
1277 for (unsigned j = 0; j != NumVals; ++j, ++i) {
1278 unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
1279 MIB.addReg(Reg,
1280 RegState::Define | RegState::EarlyClobber |
1281 getImplRegState(Register::isPhysicalRegister(Reg)));
1282 ECRegs.push_back(Reg);
1283 }
1284 break;
1285 case InlineAsm::Kind_RegUse: // Use of register.
1286 case InlineAsm::Kind_Imm: // Immediate.
1287 case InlineAsm::Kind_Mem: // Addressing mode.
1288 // The addressing mode has been selected, just add all of the
1289 // operands to the machine instruction.
1290 for (unsigned j = 0; j != NumVals; ++j, ++i)
1291 AddOperand(MIB, Node->getOperand(i), 0, nullptr, VRBaseMap,
1292 /*IsDebug=*/false, IsClone, IsCloned);
1293
1294 // Manually set isTied bits.
1295 if (InlineAsm::getKind(Flags) == InlineAsm::Kind_RegUse) {
1296 unsigned DefGroup = 0;
1297 if (InlineAsm::isUseOperandTiedToDef(Flags, DefGroup)) {
1298 unsigned DefIdx = GroupIdx[DefGroup] + 1;
1299 unsigned UseIdx = GroupIdx.back() + 1;
1300 for (unsigned j = 0; j != NumVals; ++j)
1301 MIB->tieOperands(DefIdx + j, UseIdx + j);
1302 }
1303 }
1304 break;
1305 }
1306 }
1307
1308 // GCC inline assembly allows input operands to also be early-clobber
1309 // output operands (so long as the operand is written only after it's
1310 // used), but this does not match the semantics of our early-clobber flag.
1311 // If an early-clobber operand register is also an input operand register,
1312 // then remove the early-clobber flag.
1313 for (unsigned Reg : ECRegs) {
1314 if (MIB->readsRegister(Reg, TRI)) {
1315 MachineOperand *MO =
1316 MIB->findRegisterDefOperand(Reg, false, false, TRI);
1317 assert(MO && "No def operand for clobbered register?")(static_cast <bool> (MO && "No def operand for clobbered register?"
) ? void (0) : __assert_fail ("MO && \"No def operand for clobbered register?\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp"
, 1317, __extension__ __PRETTY_FUNCTION__))
;
1318 MO->setIsEarlyClobber(false);
1319 }
1320 }
1321
1322 // Get the mdnode from the asm if it exists and add it to the instruction.
1323 SDValue MDV = Node->getOperand(InlineAsm::Op_MDNode);
1324 const MDNode *MD = cast<MDNodeSDNode>(MDV)->getMD();
1325 if (MD)
1326 MIB.addMetadata(MD);
1327
1328 MBB->insert(InsertPos, MIB);
1329 break;
1330 }
1331 }
1332}
1333
1334/// InstrEmitter - Construct an InstrEmitter and set it to start inserting
1335/// at the given position in the given block.
1336InstrEmitter::InstrEmitter(const TargetMachine &TM, MachineBasicBlock *mbb,
1337 MachineBasicBlock::iterator insertpos)
1338 : MF(mbb->getParent()), MRI(&MF->getRegInfo()),
1339 TII(MF->getSubtarget().getInstrInfo()),
1340 TRI(MF->getSubtarget().getRegisterInfo()),
1341 TLI(MF->getSubtarget().getTargetLowering()), MBB(mbb),
1342 InsertPos(insertpos) {
1343 EmitDebugInstrRefs = MF->useDebugInstrRef();
1344}

/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/include/llvm/CodeGen/SelectionDAGNodes.h

1//===- llvm/CodeGen/SelectionDAGNodes.h - SelectionDAG Nodes ----*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file declares the SDNode class and derived classes, which are used to
10// represent the nodes and operations present in a SelectionDAG. These nodes
11// and operations are machine code level operations, with some similarities to
12// the GCC RTL representation.
13//
14// Clients should include the SelectionDAG.h file instead of this file directly.
15//
16//===----------------------------------------------------------------------===//
17
18#ifndef LLVM_CODEGEN_SELECTIONDAGNODES_H
19#define LLVM_CODEGEN_SELECTIONDAGNODES_H
20
21#include "llvm/ADT/APFloat.h"
22#include "llvm/ADT/ArrayRef.h"
23#include "llvm/ADT/BitVector.h"
24#include "llvm/ADT/FoldingSet.h"
25#include "llvm/ADT/GraphTraits.h"
26#include "llvm/ADT/SmallPtrSet.h"
27#include "llvm/ADT/SmallVector.h"
28#include "llvm/ADT/ilist_node.h"
29#include "llvm/ADT/iterator.h"
30#include "llvm/ADT/iterator_range.h"
31#include "llvm/CodeGen/ISDOpcodes.h"
32#include "llvm/CodeGen/MachineMemOperand.h"
33#include "llvm/CodeGen/Register.h"
34#include "llvm/CodeGen/ValueTypes.h"
35#include "llvm/IR/Constants.h"
36#include "llvm/IR/DebugLoc.h"
37#include "llvm/IR/Instruction.h"
38#include "llvm/IR/Instructions.h"
39#include "llvm/IR/Metadata.h"
40#include "llvm/IR/Operator.h"
41#include "llvm/Support/AlignOf.h"
42#include "llvm/Support/AtomicOrdering.h"
43#include "llvm/Support/Casting.h"
44#include "llvm/Support/ErrorHandling.h"
45#include "llvm/Support/MachineValueType.h"
46#include "llvm/Support/TypeSize.h"
47#include <algorithm>
48#include <cassert>
49#include <climits>
50#include <cstddef>
51#include <cstdint>
52#include <cstring>
53#include <iterator>
54#include <string>
55#include <tuple>
56
57namespace llvm {
58
59class APInt;
60class Constant;
61template <typename T> struct DenseMapInfo;
62class GlobalValue;
63class MachineBasicBlock;
64class MachineConstantPoolValue;
65class MCSymbol;
66class raw_ostream;
67class SDNode;
68class SelectionDAG;
69class Type;
70class Value;
71
72void checkForCycles(const SDNode *N, const SelectionDAG *DAG = nullptr,
73 bool force = false);
74
75/// This represents a list of ValueType's that has been intern'd by
76/// a SelectionDAG. Instances of this simple value class are returned by
77/// SelectionDAG::getVTList(...).
78///
79struct SDVTList {
80 const EVT *VTs;
81 unsigned int NumVTs;
82};
83
84namespace ISD {
85
86 /// Node predicates
87
88/// If N is a BUILD_VECTOR or SPLAT_VECTOR node whose elements are all the
89/// same constant or undefined, return true and return the constant value in
90/// \p SplatValue.
91bool isConstantSplatVector(const SDNode *N, APInt &SplatValue);
92
93/// Return true if the specified node is a BUILD_VECTOR or SPLAT_VECTOR where
94/// all of the elements are ~0 or undef. If \p BuildVectorOnly is set to
95/// true, it only checks BUILD_VECTOR.
96bool isConstantSplatVectorAllOnes(const SDNode *N,
97 bool BuildVectorOnly = false);
98
99/// Return true if the specified node is a BUILD_VECTOR or SPLAT_VECTOR where
100/// all of the elements are 0 or undef. If \p BuildVectorOnly is set to true, it
101/// only checks BUILD_VECTOR.
102bool isConstantSplatVectorAllZeros(const SDNode *N,
103 bool BuildVectorOnly = false);
104
105/// Return true if the specified node is a BUILD_VECTOR where all of the
106/// elements are ~0 or undef.
107bool isBuildVectorAllOnes(const SDNode *N);
108
109/// Return true if the specified node is a BUILD_VECTOR where all of the
110/// elements are 0 or undef.
111bool isBuildVectorAllZeros(const SDNode *N);
112
113/// Return true if the specified node is a BUILD_VECTOR node of all
114/// ConstantSDNode or undef.
115bool isBuildVectorOfConstantSDNodes(const SDNode *N);
116
117/// Return true if the specified node is a BUILD_VECTOR node of all
118/// ConstantFPSDNode or undef.
119bool isBuildVectorOfConstantFPSDNodes(const SDNode *N);
120
121/// Return true if the node has at least one operand and all operands of the
122/// specified node are ISD::UNDEF.
123bool allOperandsUndef(const SDNode *N);
124
125} // end namespace ISD
126
127//===----------------------------------------------------------------------===//
128/// Unlike LLVM values, Selection DAG nodes may return multiple
129/// values as the result of a computation. Many nodes return multiple values,
130/// from loads (which define a token and a return value) to ADDC (which returns
131/// a result and a carry value), to calls (which may return an arbitrary number
132/// of values).
133///
134/// As such, each use of a SelectionDAG computation must indicate the node that
135/// computes it as well as which return value to use from that node. This pair
136/// of information is represented with the SDValue value type.
137///
138class SDValue {
139 friend struct DenseMapInfo<SDValue>;
140
141 SDNode *Node = nullptr; // The node defining the value we are using.
142 unsigned ResNo = 0; // Which return value of the node we are using.
143
144public:
145 SDValue() = default;
146 SDValue(SDNode *node, unsigned resno);
147
148 /// get the index which selects a specific result in the SDNode
149 unsigned getResNo() const { return ResNo; }
150
151 /// get the SDNode which holds the desired result
152 SDNode *getNode() const { return Node; }
153
154 /// set the SDNode
155 void setNode(SDNode *N) { Node = N; }
156
157 inline SDNode *operator->() const { return Node; }
158
159 bool operator==(const SDValue &O) const {
160 return Node == O.Node && ResNo == O.ResNo;
161 }
162 bool operator!=(const SDValue &O) const {
163 return !operator==(O);
164 }
165 bool operator<(const SDValue &O) const {
166 return std::tie(Node, ResNo) < std::tie(O.Node, O.ResNo);
167 }
168 explicit operator bool() const {
169 return Node != nullptr;
170 }
171
172 SDValue getValue(unsigned R) const {
173 return SDValue(Node, R);
174 }
175
176 /// Return true if this node is an operand of N.
177 bool isOperandOf(const SDNode *N) const;
178
179 /// Return the ValueType of the referenced return value.
180 inline EVT getValueType() const;
181
182 /// Return the simple ValueType of the referenced return value.
183 MVT getSimpleValueType() const {
184 return getValueType().getSimpleVT();
185 }
186
187 /// Returns the size of the value in bits.
188 ///
189 /// If the value type is a scalable vector type, the scalable property will
190 /// be set and the runtime size will be a positive integer multiple of the
191 /// base size.
192 TypeSize getValueSizeInBits() const {
193 return getValueType().getSizeInBits();
194 }
195
196 uint64_t getScalarValueSizeInBits() const {
197 return getValueType().getScalarType().getFixedSizeInBits();
198 }
199
200 // Forwarding methods - These forward to the corresponding methods in SDNode.
201 inline unsigned getOpcode() const;
202 inline unsigned getNumOperands() const;
203 inline const SDValue &getOperand(unsigned i) const;
204 inline uint64_t getConstantOperandVal(unsigned i) const;
205 inline const APInt &getConstantOperandAPInt(unsigned i) const;
206 inline bool isTargetMemoryOpcode() const;
207 inline bool isTargetOpcode() const;
208 inline bool isMachineOpcode() const;
209 inline bool isUndef() const;
210 inline unsigned getMachineOpcode() const;
211 inline const DebugLoc &getDebugLoc() const;
212 inline void dump() const;
213 inline void dump(const SelectionDAG *G) const;
214 inline void dumpr() const;
215 inline void dumpr(const SelectionDAG *G) const;
216
217 /// Return true if this operand (which must be a chain) reaches the
218 /// specified operand without crossing any side-effecting instructions.
219 /// In practice, this looks through token factors and non-volatile loads.
220 /// In order to remain efficient, this only
221 /// looks a couple of nodes in, it does not do an exhaustive search.
222 bool reachesChainWithoutSideEffects(SDValue Dest,
223 unsigned Depth = 2) const;
224
225 /// Return true if there are no nodes using value ResNo of Node.
226 inline bool use_empty() const;
227
228 /// Return true if there is exactly one node using value ResNo of Node.
229 inline bool hasOneUse() const;
230};
231
232template<> struct DenseMapInfo<SDValue> {
233 static inline SDValue getEmptyKey() {
234 SDValue V;
235 V.ResNo = -1U;
236 return V;
237 }
238
239 static inline SDValue getTombstoneKey() {
240 SDValue V;
241 V.ResNo = -2U;
242 return V;
243 }
244
245 static unsigned getHashValue(const SDValue &Val) {
246 return ((unsigned)((uintptr_t)Val.getNode() >> 4) ^
247 (unsigned)((uintptr_t)Val.getNode() >> 9)) + Val.getResNo();
248 }
249
250 static bool isEqual(const SDValue &LHS, const SDValue &RHS) {
251 return LHS == RHS;
252 }
253};
254
255/// Allow casting operators to work directly on
256/// SDValues as if they were SDNode*'s.
257template<> struct simplify_type<SDValue> {
258 using SimpleType = SDNode *;
259
260 static SimpleType getSimplifiedValue(SDValue &Val) {
261 return Val.getNode();
262 }
263};
264template<> struct simplify_type<const SDValue> {
265 using SimpleType = /*const*/ SDNode *;
266
267 static SimpleType getSimplifiedValue(const SDValue &Val) {
268 return Val.getNode();
269 }
270};
271
272/// Represents a use of a SDNode. This class holds an SDValue,
273/// which records the SDNode being used and the result number, a
274/// pointer to the SDNode using the value, and Next and Prev pointers,
275/// which link together all the uses of an SDNode.
276///
277class SDUse {
278 /// Val - The value being used.
279 SDValue Val;
280 /// User - The user of this value.
281 SDNode *User = nullptr;
282 /// Prev, Next - Pointers to the uses list of the SDNode referred by
283 /// this operand.
284 SDUse **Prev = nullptr;
285 SDUse *Next = nullptr;
286
287public:
288 SDUse() = default;
289 SDUse(const SDUse &U) = delete;
290 SDUse &operator=(const SDUse &) = delete;
291
292 /// Normally SDUse will just implicitly convert to an SDValue that it holds.
293 operator const SDValue&() const { return Val; }
294
295 /// If implicit conversion to SDValue doesn't work, the get() method returns
296 /// the SDValue.
297 const SDValue &get() const { return Val; }
298
299 /// This returns the SDNode that contains this Use.
300 SDNode *getUser() { return User; }
301
302 /// Get the next SDUse in the use list.
303 SDUse *getNext() const { return Next; }
304
305 /// Convenience function for get().getNode().
306 SDNode *getNode() const { return Val.getNode(); }
307 /// Convenience function for get().getResNo().
308 unsigned getResNo() const { return Val.getResNo(); }
309 /// Convenience function for get().getValueType().
310 EVT getValueType() const { return Val.getValueType(); }
311
312 /// Convenience function for get().operator==
313 bool operator==(const SDValue &V) const {
314 return Val == V;
315 }
316
317 /// Convenience function for get().operator!=
318 bool operator!=(const SDValue &V) const {
319 return Val != V;
320 }
321
322 /// Convenience function for get().operator<
323 bool operator<(const SDValue &V) const {
324 return Val < V;
325 }
326
327private:
328 friend class SelectionDAG;
329 friend class SDNode;
330 // TODO: unfriend HandleSDNode once we fix its operand handling.
331 friend class HandleSDNode;
332
333 void setUser(SDNode *p) { User = p; }
334
335 /// Remove this use from its existing use list, assign it the
336 /// given value, and add it to the new value's node's use list.
337 inline void set(const SDValue &V);
338 /// Like set, but only supports initializing a newly-allocated
339 /// SDUse with a non-null value.
340 inline void setInitial(const SDValue &V);
341 /// Like set, but only sets the Node portion of the value,
342 /// leaving the ResNo portion unmodified.
343 inline void setNode(SDNode *N);
344
345 void addToList(SDUse **List) {
346 Next = *List;
347 if (Next) Next->Prev = &Next;
348 Prev = List;
349 *List = this;
350 }
351
352 void removeFromList() {
353 *Prev = Next;
354 if (Next) Next->Prev = Prev;
355 }
356};
357
358/// simplify_type specializations - Allow casting operators to work directly on
359/// SDValues as if they were SDNode*'s.
360template<> struct simplify_type<SDUse> {
361 using SimpleType = SDNode *;
362
363 static SimpleType getSimplifiedValue(SDUse &Val) {
364 return Val.getNode();
365 }
366};
367
368/// These are IR-level optimization flags that may be propagated to SDNodes.
369/// TODO: This data structure should be shared by the IR optimizer and the
370/// the backend.
371struct SDNodeFlags {
372private:
373 bool NoUnsignedWrap : 1;
374 bool NoSignedWrap : 1;
375 bool Exact : 1;
376 bool NoNaNs : 1;
377 bool NoInfs : 1;
378 bool NoSignedZeros : 1;
379 bool AllowReciprocal : 1;
380 bool AllowContract : 1;
381 bool ApproximateFuncs : 1;
382 bool AllowReassociation : 1;
383
384 // We assume instructions do not raise floating-point exceptions by default,
385 // and only those marked explicitly may do so. We could choose to represent
386 // this via a positive "FPExcept" flags like on the MI level, but having a
387 // negative "NoFPExcept" flag here (that defaults to true) makes the flag
388 // intersection logic more straightforward.
389 bool NoFPExcept : 1;
390
391public:
392 /// Default constructor turns off all optimization flags.
393 SDNodeFlags()
394 : NoUnsignedWrap(false), NoSignedWrap(false), Exact(false), NoNaNs(false),
395 NoInfs(false), NoSignedZeros(false), AllowReciprocal(false),
396 AllowContract(false), ApproximateFuncs(false),
397 AllowReassociation(false), NoFPExcept(false) {}
398
399 /// Propagate the fast-math-flags from an IR FPMathOperator.
400 void copyFMF(const FPMathOperator &FPMO) {
401 setNoNaNs(FPMO.hasNoNaNs());
402 setNoInfs(FPMO.hasNoInfs());
403 setNoSignedZeros(FPMO.hasNoSignedZeros());
404 setAllowReciprocal(FPMO.hasAllowReciprocal());
405 setAllowContract(FPMO.hasAllowContract());
406 setApproximateFuncs(FPMO.hasApproxFunc());
407 setAllowReassociation(FPMO.hasAllowReassoc());
408 }
409
410 // These are mutators for each flag.
411 void setNoUnsignedWrap(bool b) { NoUnsignedWrap = b; }
412 void setNoSignedWrap(bool b) { NoSignedWrap = b; }
413 void setExact(bool b) { Exact = b; }
414 void setNoNaNs(bool b) { NoNaNs = b; }
415 void setNoInfs(bool b) { NoInfs = b; }
416 void setNoSignedZeros(bool b) { NoSignedZeros = b; }
417 void setAllowReciprocal(bool b) { AllowReciprocal = b; }
418 void setAllowContract(bool b) { AllowContract = b; }
419 void setApproximateFuncs(bool b) { ApproximateFuncs = b; }
420 void setAllowReassociation(bool b) { AllowReassociation = b; }
421 void setNoFPExcept(bool b) { NoFPExcept = b; }
422
423 // These are accessors for each flag.
424 bool hasNoUnsignedWrap() const { return NoUnsignedWrap; }
425 bool hasNoSignedWrap() const { return NoSignedWrap; }
426 bool hasExact() const { return Exact; }
427 bool hasNoNaNs() const { return NoNaNs; }
428 bool hasNoInfs() const { return NoInfs; }
429 bool hasNoSignedZeros() const { return NoSignedZeros; }
430 bool hasAllowReciprocal() const { return AllowReciprocal; }
431 bool hasAllowContract() const { return AllowContract; }
432 bool hasApproximateFuncs() const { return ApproximateFuncs; }
433 bool hasAllowReassociation() const { return AllowReassociation; }
434 bool hasNoFPExcept() const { return NoFPExcept; }
435
436 /// Clear any flags in this flag set that aren't also set in Flags. All
437 /// flags will be cleared if Flags are undefined.
438 void intersectWith(const SDNodeFlags Flags) {
439 NoUnsignedWrap &= Flags.NoUnsignedWrap;
440 NoSignedWrap &= Flags.NoSignedWrap;
441 Exact &= Flags.Exact;
442 NoNaNs &= Flags.NoNaNs;
443 NoInfs &= Flags.NoInfs;
444 NoSignedZeros &= Flags.NoSignedZeros;
445 AllowReciprocal &= Flags.AllowReciprocal;
446 AllowContract &= Flags.AllowContract;
447 ApproximateFuncs &= Flags.ApproximateFuncs;
448 AllowReassociation &= Flags.AllowReassociation;
449 NoFPExcept &= Flags.NoFPExcept;
450 }
451};
452
453/// Represents one node in the SelectionDAG.
454///
455class SDNode : public FoldingSetNode, public ilist_node<SDNode> {
456private:
457 /// The operation that this node performs.
458 int16_t NodeType;
459
460protected:
461 // We define a set of mini-helper classes to help us interpret the bits in our
462 // SubclassData. These are designed to fit within a uint16_t so they pack
463 // with NodeType.
464
465#if defined(_AIX) && (!defined(__GNUC__4) || defined(__clang__1))
466// Except for GCC; by default, AIX compilers store bit-fields in 4-byte words
467// and give the `pack` pragma push semantics.
468#define BEGIN_TWO_BYTE_PACK() _Pragma("pack(2)")pack(2)
469#define END_TWO_BYTE_PACK() _Pragma("pack(pop)")pack(pop)
470#else
471#define BEGIN_TWO_BYTE_PACK()
472#define END_TWO_BYTE_PACK()
473#endif
474
475BEGIN_TWO_BYTE_PACK()
476 class SDNodeBitfields {
477 friend class SDNode;
478 friend class MemIntrinsicSDNode;
479 friend class MemSDNode;
480 friend class SelectionDAG;
481
482 uint16_t HasDebugValue : 1;
483 uint16_t IsMemIntrinsic : 1;
484 uint16_t IsDivergent : 1;
485 };
486 enum { NumSDNodeBits = 3 };
487
488 class ConstantSDNodeBitfields {
489 friend class ConstantSDNode;
490
491 uint16_t : NumSDNodeBits;
492
493 uint16_t IsOpaque : 1;
494 };
495
496 class MemSDNodeBitfields {
497 friend class MemSDNode;
498 friend class MemIntrinsicSDNode;
499 friend class AtomicSDNode;
500
501 uint16_t : NumSDNodeBits;
502
503 uint16_t IsVolatile : 1;
504 uint16_t IsNonTemporal : 1;
505 uint16_t IsDereferenceable : 1;
506 uint16_t IsInvariant : 1;
507 };
508 enum { NumMemSDNodeBits = NumSDNodeBits + 4 };
509
510 class LSBaseSDNodeBitfields {
511 friend class LSBaseSDNode;
512 friend class VPLoadStoreSDNode;
513 friend class MaskedLoadStoreSDNode;
514 friend class MaskedGatherScatterSDNode;
515 friend class VPGatherScatterSDNode;
516
517 uint16_t : NumMemSDNodeBits;
518
519 // This storage is shared between disparate class hierarchies to hold an
520 // enumeration specific to the class hierarchy in use.
521 // LSBaseSDNode => enum ISD::MemIndexedMode
522 // VPLoadStoreBaseSDNode => enum ISD::MemIndexedMode
523 // MaskedLoadStoreBaseSDNode => enum ISD::MemIndexedMode
524 // VPGatherScatterSDNode => enum ISD::MemIndexType
525 // MaskedGatherScatterSDNode => enum ISD::MemIndexType
526 uint16_t AddressingMode : 3;
527 };
528 enum { NumLSBaseSDNodeBits = NumMemSDNodeBits + 3 };
529
530 class LoadSDNodeBitfields {
531 friend class LoadSDNode;
532 friend class VPLoadSDNode;
533 friend class MaskedLoadSDNode;
534 friend class MaskedGatherSDNode;
535 friend class VPGatherSDNode;
536
537 uint16_t : NumLSBaseSDNodeBits;
538
539 uint16_t ExtTy : 2; // enum ISD::LoadExtType
540 uint16_t IsExpanding : 1;
541 };
542
543 class StoreSDNodeBitfields {
544 friend class StoreSDNode;
545 friend class VPStoreSDNode;
546 friend class MaskedStoreSDNode;
547 friend class MaskedScatterSDNode;
548 friend class VPScatterSDNode;
549
550 uint16_t : NumLSBaseSDNodeBits;
551
552 uint16_t IsTruncating : 1;
553 uint16_t IsCompressing : 1;
554 };
555
556 union {
557 char RawSDNodeBits[sizeof(uint16_t)];
558 SDNodeBitfields SDNodeBits;
559 ConstantSDNodeBitfields ConstantSDNodeBits;
560 MemSDNodeBitfields MemSDNodeBits;
561 LSBaseSDNodeBitfields LSBaseSDNodeBits;
562 LoadSDNodeBitfields LoadSDNodeBits;
563 StoreSDNodeBitfields StoreSDNodeBits;
564 };
565END_TWO_BYTE_PACK()
566#undef BEGIN_TWO_BYTE_PACK
567#undef END_TWO_BYTE_PACK
568
569 // RawSDNodeBits must cover the entirety of the union. This means that all of
570 // the union's members must have size <= RawSDNodeBits. We write the RHS as
571 // "2" instead of sizeof(RawSDNodeBits) because MSVC can't handle the latter.
572 static_assert(sizeof(SDNodeBitfields) <= 2, "field too wide");
573 static_assert(sizeof(ConstantSDNodeBitfields) <= 2, "field too wide");
574 static_assert(sizeof(MemSDNodeBitfields) <= 2, "field too wide");
575 static_assert(sizeof(LSBaseSDNodeBitfields) <= 2, "field too wide");
576 static_assert(sizeof(LoadSDNodeBitfields) <= 2, "field too wide");
577 static_assert(sizeof(StoreSDNodeBitfields) <= 2, "field too wide");
578
579private:
580 friend class SelectionDAG;
581 // TODO: unfriend HandleSDNode once we fix its operand handling.
582 friend class HandleSDNode;
583
584 /// Unique id per SDNode in the DAG.
585 int NodeId = -1;
586
587 /// The values that are used by this operation.
588 SDUse *OperandList = nullptr;
589
590 /// The types of the values this node defines. SDNode's may
591 /// define multiple values simultaneously.
592 const EVT *ValueList;
593
594 /// List of uses for this SDNode.
595 SDUse *UseList = nullptr;
596
597 /// The number of entries in the Operand/Value list.
598 unsigned short NumOperands = 0;
599 unsigned short NumValues;
600
601 // The ordering of the SDNodes. It roughly corresponds to the ordering of the
602 // original LLVM instructions.
603 // This is used for turning off scheduling, because we'll forgo
604 // the normal scheduling algorithms and output the instructions according to
605 // this ordering.
606 unsigned IROrder;
607
608 /// Source line information.
609 DebugLoc debugLoc;
610
611 /// Return a pointer to the specified value type.
612 static const EVT *getValueTypeList(EVT VT);
613
614 SDNodeFlags Flags;
615
616public:
617 /// Unique and persistent id per SDNode in the DAG.
618 /// Used for debug printing.
619 uint16_t PersistentId;
620
621 //===--------------------------------------------------------------------===//
622 // Accessors
623 //
624
625 /// Return the SelectionDAG opcode value for this node. For
626 /// pre-isel nodes (those for which isMachineOpcode returns false), these
627 /// are the opcode values in the ISD and <target>ISD namespaces. For
628 /// post-isel opcodes, see getMachineOpcode.
629 unsigned getOpcode() const { return (unsigned short)NodeType; }
630
631 /// Test if this node has a target-specific opcode (in the
632 /// \<target\>ISD namespace).
633 bool isTargetOpcode() const { return NodeType >= ISD::BUILTIN_OP_END; }
634
635 /// Test if this node has a target-specific opcode that may raise
636 /// FP exceptions (in the \<target\>ISD namespace and greater than
637 /// FIRST_TARGET_STRICTFP_OPCODE). Note that all target memory
638 /// opcode are currently automatically considered to possibly raise
639 /// FP exceptions as well.
640 bool isTargetStrictFPOpcode() const {
641 return NodeType >= ISD::FIRST_TARGET_STRICTFP_OPCODE;
642 }
643
644 /// Test if this node has a target-specific
645 /// memory-referencing opcode (in the \<target\>ISD namespace and
646 /// greater than FIRST_TARGET_MEMORY_OPCODE).
647 bool isTargetMemoryOpcode() const {
648 return NodeType >= ISD::FIRST_TARGET_MEMORY_OPCODE;
649 }
650
651 /// Return true if the type of the node type undefined.
652 bool isUndef() const { return NodeType == ISD::UNDEF; }
653
654 /// Test if this node is a memory intrinsic (with valid pointer information).
655 /// INTRINSIC_W_CHAIN and INTRINSIC_VOID nodes are sometimes created for
656 /// non-memory intrinsics (with chains) that are not really instances of
657 /// MemSDNode. For such nodes, we need some extra state to determine the
658 /// proper classof relationship.
659 bool isMemIntrinsic() const {
660 return (NodeType == ISD::INTRINSIC_W_CHAIN ||
661 NodeType == ISD::INTRINSIC_VOID) &&
662 SDNodeBits.IsMemIntrinsic;
663 }
664
665 /// Test if this node is a strict floating point pseudo-op.
666 bool isStrictFPOpcode() {
667 switch (NodeType) {
668 default:
669 return false;
670 case ISD::STRICT_FP16_TO_FP:
671 case ISD::STRICT_FP_TO_FP16:
672#define DAG_INSTRUCTION(NAME, NARG, ROUND_MODE, INTRINSIC, DAGN) \
673 case ISD::STRICT_##DAGN:
674#include "llvm/IR/ConstrainedOps.def"
675 return true;
676 }
677 }
678
679 /// Test if this node has a post-isel opcode, directly
680 /// corresponding to a MachineInstr opcode.
681 bool isMachineOpcode() const { return NodeType < 0; }
682
683 /// This may only be called if isMachineOpcode returns
684 /// true. It returns the MachineInstr opcode value that the node's opcode
685 /// corresponds to.
686 unsigned getMachineOpcode() const {
687 assert(isMachineOpcode() && "Not a MachineInstr opcode!")(static_cast <bool> (isMachineOpcode() && "Not a MachineInstr opcode!"
) ? void (0) : __assert_fail ("isMachineOpcode() && \"Not a MachineInstr opcode!\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 687, __extension__ __PRETTY_FUNCTION__))
;
688 return ~NodeType;
689 }
690
691 bool getHasDebugValue() const { return SDNodeBits.HasDebugValue; }
692 void setHasDebugValue(bool b) { SDNodeBits.HasDebugValue = b; }
693
694 bool isDivergent() const { return SDNodeBits.IsDivergent; }
695
696 /// Return true if there are no uses of this node.
697 bool use_empty() const { return UseList == nullptr; }
698
699 /// Return true if there is exactly one use of this node.
700 bool hasOneUse() const { return hasSingleElement(uses()); }
701
702 /// Return the number of uses of this node. This method takes
703 /// time proportional to the number of uses.
704 size_t use_size() const { return std::distance(use_begin(), use_end()); }
705
706 /// Return the unique node id.
707 int getNodeId() const { return NodeId; }
708
709 /// Set unique node id.
710 void setNodeId(int Id) { NodeId = Id; }
711
712 /// Return the node ordering.
713 unsigned getIROrder() const { return IROrder; }
714
715 /// Set the node ordering.
716 void setIROrder(unsigned Order) { IROrder = Order; }
717
718 /// Return the source location info.
719 const DebugLoc &getDebugLoc() const { return debugLoc; }
720
721 /// Set source location info. Try to avoid this, putting
722 /// it in the constructor is preferable.
723 void setDebugLoc(DebugLoc dl) { debugLoc = std::move(dl); }
724
725 /// This class provides iterator support for SDUse
726 /// operands that use a specific SDNode.
727 class use_iterator {
728 friend class SDNode;
729
730 SDUse *Op = nullptr;
731
732 explicit use_iterator(SDUse *op) : Op(op) {}
733
734 public:
735 using iterator_category = std::forward_iterator_tag;
736 using value_type = SDUse;
737 using difference_type = std::ptrdiff_t;
738 using pointer = value_type *;
739 using reference = value_type &;
740
741 use_iterator() = default;
742 use_iterator(const use_iterator &I) : Op(I.Op) {}
743
744 bool operator==(const use_iterator &x) const {
745 return Op == x.Op;
746 }
747 bool operator!=(const use_iterator &x) const {
748 return !operator==(x);
749 }
750
751 /// Return true if this iterator is at the end of uses list.
752 bool atEnd() const { return Op == nullptr; }
753
754 // Iterator traversal: forward iteration only.
755 use_iterator &operator++() { // Preincrement
756 assert(Op && "Cannot increment end iterator!")(static_cast <bool> (Op && "Cannot increment end iterator!"
) ? void (0) : __assert_fail ("Op && \"Cannot increment end iterator!\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 756, __extension__ __PRETTY_FUNCTION__))
;
757 Op = Op->getNext();
758 return *this;
759 }
760
761 use_iterator operator++(int) { // Postincrement
762 use_iterator tmp = *this; ++*this; return tmp;
763 }
764
765 /// Retrieve a pointer to the current user node.
766 SDNode *operator*() const {
767 assert(Op && "Cannot dereference end iterator!")(static_cast <bool> (Op && "Cannot dereference end iterator!"
) ? void (0) : __assert_fail ("Op && \"Cannot dereference end iterator!\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 767, __extension__ __PRETTY_FUNCTION__))
;
768 return Op->getUser();
769 }
770
771 SDNode *operator->() const { return operator*(); }
772
773 SDUse &getUse() const { return *Op; }
774
775 /// Retrieve the operand # of this use in its user.
776 unsigned getOperandNo() const {
777 assert(Op && "Cannot dereference end iterator!")(static_cast <bool> (Op && "Cannot dereference end iterator!"
) ? void (0) : __assert_fail ("Op && \"Cannot dereference end iterator!\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 777, __extension__ __PRETTY_FUNCTION__))
;
778 return (unsigned)(Op - Op->getUser()->OperandList);
779 }
780 };
781
782 /// Provide iteration support to walk over all uses of an SDNode.
783 use_iterator use_begin() const {
784 return use_iterator(UseList);
785 }
786
787 static use_iterator use_end() { return use_iterator(nullptr); }
788
789 inline iterator_range<use_iterator> uses() {
790 return make_range(use_begin(), use_end());
791 }
792 inline iterator_range<use_iterator> uses() const {
793 return make_range(use_begin(), use_end());
794 }
795
796 /// Return true if there are exactly NUSES uses of the indicated value.
797 /// This method ignores uses of other values defined by this operation.
798 bool hasNUsesOfValue(unsigned NUses, unsigned Value) const;
799
800 /// Return true if there are any use of the indicated value.
801 /// This method ignores uses of other values defined by this operation.
802 bool hasAnyUseOfValue(unsigned Value) const;
803
804 /// Return true if this node is the only use of N.
805 bool isOnlyUserOf(const SDNode *N) const;
806
807 /// Return true if this node is an operand of N.
808 bool isOperandOf(const SDNode *N) const;
809
810 /// Return true if this node is a predecessor of N.
811 /// NOTE: Implemented on top of hasPredecessor and every bit as
812 /// expensive. Use carefully.
813 bool isPredecessorOf(const SDNode *N) const {
814 return N->hasPredecessor(this);
815 }
816
817 /// Return true if N is a predecessor of this node.
818 /// N is either an operand of this node, or can be reached by recursively
819 /// traversing up the operands.
820 /// NOTE: This is an expensive method. Use it carefully.
821 bool hasPredecessor(const SDNode *N) const;
822
823 /// Returns true if N is a predecessor of any node in Worklist. This
824 /// helper keeps Visited and Worklist sets externally to allow unions
825 /// searches to be performed in parallel, caching of results across
826 /// queries and incremental addition to Worklist. Stops early if N is
827 /// found but will resume. Remember to clear Visited and Worklists
828 /// if DAG changes. MaxSteps gives a maximum number of nodes to visit before
829 /// giving up. The TopologicalPrune flag signals that positive NodeIds are
830 /// topologically ordered (Operands have strictly smaller node id) and search
831 /// can be pruned leveraging this.
832 static bool hasPredecessorHelper(const SDNode *N,
833 SmallPtrSetImpl<const SDNode *> &Visited,
834 SmallVectorImpl<const SDNode *> &Worklist,
835 unsigned int MaxSteps = 0,
836 bool TopologicalPrune = false) {
837 SmallVector<const SDNode *, 8> DeferredNodes;
838 if (Visited.count(N))
839 return true;
840
841 // Node Id's are assigned in three places: As a topological
842 // ordering (> 0), during legalization (results in values set to
843 // 0), new nodes (set to -1). If N has a topolgical id then we
844 // know that all nodes with ids smaller than it cannot be
845 // successors and we need not check them. Filter out all node
846 // that can't be matches. We add them to the worklist before exit
847 // in case of multiple calls. Note that during selection the topological id
848 // may be violated if a node's predecessor is selected before it. We mark
849 // this at selection negating the id of unselected successors and
850 // restricting topological pruning to positive ids.
851
852 int NId = N->getNodeId();
853 // If we Invalidated the Id, reconstruct original NId.
854 if (NId < -1)
855 NId = -(NId + 1);
856
857 bool Found = false;
858 while (!Worklist.empty()) {
859 const SDNode *M = Worklist.pop_back_val();
860 int MId = M->getNodeId();
861 if (TopologicalPrune && M->getOpcode() != ISD::TokenFactor && (NId > 0) &&
862 (MId > 0) && (MId < NId)) {
863 DeferredNodes.push_back(M);
864 continue;
865 }
866 for (const SDValue &OpV : M->op_values()) {
867 SDNode *Op = OpV.getNode();
868 if (Visited.insert(Op).second)
869 Worklist.push_back(Op);
870 if (Op == N)
871 Found = true;
872 }
873 if (Found)
874 break;
875 if (MaxSteps != 0 && Visited.size() >= MaxSteps)
876 break;
877 }
878 // Push deferred nodes back on worklist.
879 Worklist.append(DeferredNodes.begin(), DeferredNodes.end());
880 // If we bailed early, conservatively return found.
881 if (MaxSteps != 0 && Visited.size() >= MaxSteps)
882 return true;
883 return Found;
884 }
885
886 /// Return true if all the users of N are contained in Nodes.
887 /// NOTE: Requires at least one match, but doesn't require them all.
888 static bool areOnlyUsersOf(ArrayRef<const SDNode *> Nodes, const SDNode *N);
889
890 /// Return the number of values used by this operation.
891 unsigned getNumOperands() const { return NumOperands; }
892
893 /// Return the maximum number of operands that a SDNode can hold.
894 static constexpr size_t getMaxNumOperands() {
895 return std::numeric_limits<decltype(SDNode::NumOperands)>::max();
896 }
897
898 /// Helper method returns the integer value of a ConstantSDNode operand.
899 inline uint64_t getConstantOperandVal(unsigned Num) const;
900
901 /// Helper method returns the APInt of a ConstantSDNode operand.
902 inline const APInt &getConstantOperandAPInt(unsigned Num) const;
903
904 const SDValue &getOperand(unsigned Num) const {
905 assert(Num < NumOperands && "Invalid child # of SDNode!")(static_cast <bool> (Num < NumOperands && "Invalid child # of SDNode!"
) ? void (0) : __assert_fail ("Num < NumOperands && \"Invalid child # of SDNode!\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 905, __extension__ __PRETTY_FUNCTION__))
;
906 return OperandList[Num];
907 }
908
909 using op_iterator = SDUse *;
910
911 op_iterator op_begin() const { return OperandList; }
912 op_iterator op_end() const { return OperandList+NumOperands; }
913 ArrayRef<SDUse> ops() const { return makeArrayRef(op_begin(), op_end()); }
914
915 /// Iterator for directly iterating over the operand SDValue's.
916 struct value_op_iterator
917 : iterator_adaptor_base<value_op_iterator, op_iterator,
918 std::random_access_iterator_tag, SDValue,
919 ptrdiff_t, value_op_iterator *,
920 value_op_iterator *> {
921 explicit value_op_iterator(SDUse *U = nullptr)
922 : iterator_adaptor_base(U) {}
923
924 const SDValue &operator*() const { return I->get(); }
925 };
926
927 iterator_range<value_op_iterator> op_values() const {
928 return make_range(value_op_iterator(op_begin()),
929 value_op_iterator(op_end()));
930 }
931
932 SDVTList getVTList() const {
933 SDVTList X = { ValueList, NumValues };
934 return X;
935 }
936
937 /// If this node has a glue operand, return the node
938 /// to which the glue operand points. Otherwise return NULL.
939 SDNode *getGluedNode() const {
940 if (getNumOperands() != 0 &&
941 getOperand(getNumOperands()-1).getValueType() == MVT::Glue)
942 return getOperand(getNumOperands()-1).getNode();
943 return nullptr;
944 }
945
946 /// If this node has a glue value with a user, return
947 /// the user (there is at most one). Otherwise return NULL.
948 SDNode *getGluedUser() const {
949 for (use_iterator UI = use_begin(), UE = use_end(); UI != UE; ++UI)
950 if (UI.getUse().get().getValueType() == MVT::Glue)
951 return *UI;
952 return nullptr;
953 }
954
955 SDNodeFlags getFlags() const { return Flags; }
956 void setFlags(SDNodeFlags NewFlags) { Flags = NewFlags; }
957
958 /// Clear any flags in this node that aren't also set in Flags.
959 /// If Flags is not in a defined state then this has no effect.
960 void intersectFlagsWith(const SDNodeFlags Flags);
961
962 /// Return the number of values defined/returned by this operator.
963 unsigned getNumValues() const { return NumValues; }
964
965 /// Return the type of a specified result.
966 EVT getValueType(unsigned ResNo) const {
967 assert(ResNo < NumValues && "Illegal result number!")(static_cast <bool> (ResNo < NumValues && "Illegal result number!"
) ? void (0) : __assert_fail ("ResNo < NumValues && \"Illegal result number!\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 967, __extension__ __PRETTY_FUNCTION__))
;
968 return ValueList[ResNo];
969 }
970
971 /// Return the type of a specified result as a simple type.
972 MVT getSimpleValueType(unsigned ResNo) const {
973 return getValueType(ResNo).getSimpleVT();
974 }
975
976 /// Returns MVT::getSizeInBits(getValueType(ResNo)).
977 ///
978 /// If the value type is a scalable vector type, the scalable property will
979 /// be set and the runtime size will be a positive integer multiple of the
980 /// base size.
981 TypeSize getValueSizeInBits(unsigned ResNo) const {
982 return getValueType(ResNo).getSizeInBits();
983 }
984
985 using value_iterator = const EVT *;
986
987 value_iterator value_begin() const { return ValueList; }
988 value_iterator value_end() const { return ValueList+NumValues; }
989 iterator_range<value_iterator> values() const {
990 return llvm::make_range(value_begin(), value_end());
991 }
992
993 /// Return the opcode of this operation for printing.
994 std::string getOperationName(const SelectionDAG *G = nullptr) const;
995 static const char* getIndexedModeName(ISD::MemIndexedMode AM);
996 void print_types(raw_ostream &OS, const SelectionDAG *G) const;
997 void print_details(raw_ostream &OS, const SelectionDAG *G) const;
998 void print(raw_ostream &OS, const SelectionDAG *G = nullptr) const;
999 void printr(raw_ostream &OS, const SelectionDAG *G = nullptr) const;
1000
1001 /// Print a SelectionDAG node and all children down to
1002 /// the leaves. The given SelectionDAG allows target-specific nodes
1003 /// to be printed in human-readable form. Unlike printr, this will
1004 /// print the whole DAG, including children that appear multiple
1005 /// times.
1006 ///
1007 void printrFull(raw_ostream &O, const SelectionDAG *G = nullptr) const;
1008
1009 /// Print a SelectionDAG node and children up to
1010 /// depth "depth." The given SelectionDAG allows target-specific
1011 /// nodes to be printed in human-readable form. Unlike printr, this
1012 /// will print children that appear multiple times wherever they are
1013 /// used.
1014 ///
1015 void printrWithDepth(raw_ostream &O, const SelectionDAG *G = nullptr,
1016 unsigned depth = 100) const;
1017
1018 /// Dump this node, for debugging.
1019 void dump() const;
1020
1021 /// Dump (recursively) this node and its use-def subgraph.
1022 void dumpr() const;
1023
1024 /// Dump this node, for debugging.
1025 /// The given SelectionDAG allows target-specific nodes to be printed
1026 /// in human-readable form.
1027 void dump(const SelectionDAG *G) const;
1028
1029 /// Dump (recursively) this node and its use-def subgraph.
1030 /// The given SelectionDAG allows target-specific nodes to be printed
1031 /// in human-readable form.
1032 void dumpr(const SelectionDAG *G) const;
1033
1034 /// printrFull to dbgs(). The given SelectionDAG allows
1035 /// target-specific nodes to be printed in human-readable form.
1036 /// Unlike dumpr, this will print the whole DAG, including children
1037 /// that appear multiple times.
1038 void dumprFull(const SelectionDAG *G = nullptr) const;
1039
1040 /// printrWithDepth to dbgs(). The given
1041 /// SelectionDAG allows target-specific nodes to be printed in
1042 /// human-readable form. Unlike dumpr, this will print children
1043 /// that appear multiple times wherever they are used.
1044 ///
1045 void dumprWithDepth(const SelectionDAG *G = nullptr,
1046 unsigned depth = 100) const;
1047
1048 /// Gather unique data for the node.
1049 void Profile(FoldingSetNodeID &ID) const;
1050
1051 /// This method should only be used by the SDUse class.
1052 void addUse(SDUse &U) { U.addToList(&UseList); }
1053
1054protected:
1055 static SDVTList getSDVTList(EVT VT) {
1056 SDVTList Ret = { getValueTypeList(VT), 1 };
1057 return Ret;
1058 }
1059
1060 /// Create an SDNode.
1061 ///
1062 /// SDNodes are created without any operands, and never own the operand
1063 /// storage. To add operands, see SelectionDAG::createOperands.
1064 SDNode(unsigned Opc, unsigned Order, DebugLoc dl, SDVTList VTs)
1065 : NodeType(Opc), ValueList(VTs.VTs), NumValues(VTs.NumVTs),
1066 IROrder(Order), debugLoc(std::move(dl)) {
1067 memset(&RawSDNodeBits, 0, sizeof(RawSDNodeBits));
1068 assert(debugLoc.hasTrivialDestructor() && "Expected trivial destructor")(static_cast <bool> (debugLoc.hasTrivialDestructor() &&
"Expected trivial destructor") ? void (0) : __assert_fail ("debugLoc.hasTrivialDestructor() && \"Expected trivial destructor\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1068, __extension__ __PRETTY_FUNCTION__))
;
1069 assert(NumValues == VTs.NumVTs &&(static_cast <bool> (NumValues == VTs.NumVTs &&
"NumValues wasn't wide enough for its operands!") ? void (0)
: __assert_fail ("NumValues == VTs.NumVTs && \"NumValues wasn't wide enough for its operands!\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1070, __extension__ __PRETTY_FUNCTION__))
1070 "NumValues wasn't wide enough for its operands!")(static_cast <bool> (NumValues == VTs.NumVTs &&
"NumValues wasn't wide enough for its operands!") ? void (0)
: __assert_fail ("NumValues == VTs.NumVTs && \"NumValues wasn't wide enough for its operands!\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1070, __extension__ __PRETTY_FUNCTION__))
;
1071 }
1072
1073 /// Release the operands and set this node to have zero operands.
1074 void DropOperands();
1075};
1076
1077/// Wrapper class for IR location info (IR ordering and DebugLoc) to be passed
1078/// into SDNode creation functions.
1079/// When an SDNode is created from the DAGBuilder, the DebugLoc is extracted
1080/// from the original Instruction, and IROrder is the ordinal position of
1081/// the instruction.
1082/// When an SDNode is created after the DAG is being built, both DebugLoc and
1083/// the IROrder are propagated from the original SDNode.
1084/// So SDLoc class provides two constructors besides the default one, one to
1085/// be used by the DAGBuilder, the other to be used by others.
1086class SDLoc {
1087private:
1088 DebugLoc DL;
1089 int IROrder = 0;
1090
1091public:
1092 SDLoc() = default;
1093 SDLoc(const SDNode *N) : DL(N->getDebugLoc()), IROrder(N->getIROrder()) {}
1094 SDLoc(const SDValue V) : SDLoc(V.getNode()) {}
1095 SDLoc(const Instruction *I, int Order) : IROrder(Order) {
1096 assert(Order >= 0 && "bad IROrder")(static_cast <bool> (Order >= 0 && "bad IROrder"
) ? void (0) : __assert_fail ("Order >= 0 && \"bad IROrder\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1096, __extension__ __PRETTY_FUNCTION__))
;
1097 if (I)
1098 DL = I->getDebugLoc();
1099 }
1100
1101 unsigned getIROrder() const { return IROrder; }
1102 const DebugLoc &getDebugLoc() const { return DL; }
1103};
1104
1105// Define inline functions from the SDValue class.
1106
1107inline SDValue::SDValue(SDNode *node, unsigned resno)
1108 : Node(node), ResNo(resno) {
1109 // Explicitly check for !ResNo to avoid use-after-free, because there are
1110 // callers that use SDValue(N, 0) with a deleted N to indicate successful
1111 // combines.
1112 assert((!Node || !ResNo || ResNo < Node->getNumValues()) &&(static_cast <bool> ((!Node || !ResNo || ResNo < Node
->getNumValues()) && "Invalid result number for the given node!"
) ? void (0) : __assert_fail ("(!Node || !ResNo || ResNo < Node->getNumValues()) && \"Invalid result number for the given node!\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1113, __extension__ __PRETTY_FUNCTION__))
1113 "Invalid result number for the given node!")(static_cast <bool> ((!Node || !ResNo || ResNo < Node
->getNumValues()) && "Invalid result number for the given node!"
) ? void (0) : __assert_fail ("(!Node || !ResNo || ResNo < Node->getNumValues()) && \"Invalid result number for the given node!\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1113, __extension__ __PRETTY_FUNCTION__))
;
1114 assert(ResNo < -2U && "Cannot use result numbers reserved for DenseMaps.")(static_cast <bool> (ResNo < -2U && "Cannot use result numbers reserved for DenseMaps."
) ? void (0) : __assert_fail ("ResNo < -2U && \"Cannot use result numbers reserved for DenseMaps.\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1114, __extension__ __PRETTY_FUNCTION__))
;
1115}
1116
1117inline unsigned SDValue::getOpcode() const {
1118 return Node->getOpcode();
1119}
1120
1121inline EVT SDValue::getValueType() const {
1122 return Node->getValueType(ResNo);
1123}
1124
1125inline unsigned SDValue::getNumOperands() const {
1126 return Node->getNumOperands();
1127}
1128
1129inline const SDValue &SDValue::getOperand(unsigned i) const {
1130 return Node->getOperand(i);
1131}
1132
1133inline uint64_t SDValue::getConstantOperandVal(unsigned i) const {
1134 return Node->getConstantOperandVal(i);
1135}
1136
1137inline const APInt &SDValue::getConstantOperandAPInt(unsigned i) const {
1138 return Node->getConstantOperandAPInt(i);
1139}
1140
1141inline bool SDValue::isTargetOpcode() const {
1142 return Node->isTargetOpcode();
1143}
1144
1145inline bool SDValue::isTargetMemoryOpcode() const {
1146 return Node->isTargetMemoryOpcode();
1147}
1148
1149inline bool SDValue::isMachineOpcode() const {
1150 return Node->isMachineOpcode();
7
Called C++ object pointer is null
1151}
1152
1153inline unsigned SDValue::getMachineOpcode() const {
1154 return Node->getMachineOpcode();
1155}
1156
1157inline bool SDValue::isUndef() const {
1158 return Node->isUndef();
1159}
1160
1161inline bool SDValue::use_empty() const {
1162 return !Node->hasAnyUseOfValue(ResNo);
1163}
1164
1165inline bool SDValue::hasOneUse() const {
1166 return Node->hasNUsesOfValue(1, ResNo);
1167}
1168
1169inline const DebugLoc &SDValue::getDebugLoc() const {
1170 return Node->getDebugLoc();
1171}
1172
1173inline void SDValue::dump() const {
1174 return Node->dump();
1175}
1176
1177inline void SDValue::dump(const SelectionDAG *G) const {
1178 return Node->dump(G);
1179}
1180
1181inline void SDValue::dumpr() const {
1182 return Node->dumpr();
1183}
1184
1185inline void SDValue::dumpr(const SelectionDAG *G) const {
1186 return Node->dumpr(G);
1187}
1188
1189// Define inline functions from the SDUse class.
1190
1191inline void SDUse::set(const SDValue &V) {
1192 if (Val.getNode()) removeFromList();
1193 Val = V;
1194 if (V.getNode()) V.getNode()->addUse(*this);
1195}
1196
1197inline void SDUse::setInitial(const SDValue &V) {
1198 Val = V;
1199 V.getNode()->addUse(*this);
1200}
1201
1202inline void SDUse::setNode(SDNode *N) {
1203 if (Val.getNode()) removeFromList();
1204 Val.setNode(N);
1205 if (N) N->addUse(*this);
1206}
1207
1208/// This class is used to form a handle around another node that
1209/// is persistent and is updated across invocations of replaceAllUsesWith on its
1210/// operand. This node should be directly created by end-users and not added to
1211/// the AllNodes list.
1212class HandleSDNode : public SDNode {
1213 SDUse Op;
1214
1215public:
1216 explicit HandleSDNode(SDValue X)
1217 : SDNode(ISD::HANDLENODE, 0, DebugLoc(), getSDVTList(MVT::Other)) {
1218 // HandleSDNodes are never inserted into the DAG, so they won't be
1219 // auto-numbered. Use ID 65535 as a sentinel.
1220 PersistentId = 0xffff;
1221
1222 // Manually set up the operand list. This node type is special in that it's
1223 // always stack allocated and SelectionDAG does not manage its operands.
1224 // TODO: This should either (a) not be in the SDNode hierarchy, or (b) not
1225 // be so special.
1226 Op.setUser(this);
1227 Op.setInitial(X);
1228 NumOperands = 1;
1229 OperandList = &Op;
1230 }
1231 ~HandleSDNode();
1232
1233 const SDValue &getValue() const { return Op; }
1234};
1235
1236class AddrSpaceCastSDNode : public SDNode {
1237private:
1238 unsigned SrcAddrSpace;
1239 unsigned DestAddrSpace;
1240
1241public:
1242 AddrSpaceCastSDNode(unsigned Order, const DebugLoc &dl, EVT VT,
1243 unsigned SrcAS, unsigned DestAS);
1244
1245 unsigned getSrcAddressSpace() const { return SrcAddrSpace; }
1246 unsigned getDestAddressSpace() const { return DestAddrSpace; }
1247
1248 static bool classof(const SDNode *N) {
1249 return N->getOpcode() == ISD::ADDRSPACECAST;
1250 }
1251};
1252
1253/// This is an abstract virtual class for memory operations.
1254class MemSDNode : public SDNode {
1255private:
1256 // VT of in-memory value.
1257 EVT MemoryVT;
1258
1259protected:
1260 /// Memory reference information.
1261 MachineMemOperand *MMO;
1262
1263public:
1264 MemSDNode(unsigned Opc, unsigned Order, const DebugLoc &dl, SDVTList VTs,
1265 EVT memvt, MachineMemOperand *MMO);
1266
1267 bool readMem() const { return MMO->isLoad(); }
1268 bool writeMem() const { return MMO->isStore(); }
1269
1270 /// Returns alignment and volatility of the memory access
1271 Align getOriginalAlign() const { return MMO->getBaseAlign(); }
1272 Align getAlign() const { return MMO->getAlign(); }
1273 // FIXME: Remove once transition to getAlign is over.
1274 unsigned getAlignment() const { return MMO->getAlign().value(); }
1275
1276 /// Return the SubclassData value, without HasDebugValue. This contains an
1277 /// encoding of the volatile flag, as well as bits used by subclasses. This
1278 /// function should only be used to compute a FoldingSetNodeID value.
1279 /// The HasDebugValue bit is masked out because CSE map needs to match
1280 /// nodes with debug info with nodes without debug info. Same is about
1281 /// isDivergent bit.
1282 unsigned getRawSubclassData() const {
1283 uint16_t Data;
1284 union {
1285 char RawSDNodeBits[sizeof(uint16_t)];
1286 SDNodeBitfields SDNodeBits;
1287 };
1288 memcpy(&RawSDNodeBits, &this->RawSDNodeBits, sizeof(this->RawSDNodeBits));
1289 SDNodeBits.HasDebugValue = 0;
1290 SDNodeBits.IsDivergent = false;
1291 memcpy(&Data, &RawSDNodeBits, sizeof(RawSDNodeBits));
1292 return Data;
1293 }
1294
1295 bool isVolatile() const { return MemSDNodeBits.IsVolatile; }
1296 bool isNonTemporal() const { return MemSDNodeBits.IsNonTemporal; }
1297 bool isDereferenceable() const { return MemSDNodeBits.IsDereferenceable; }
1298 bool isInvariant() const { return MemSDNodeBits.IsInvariant; }
1299
1300 // Returns the offset from the location of the access.
1301 int64_t getSrcValueOffset() const { return MMO->getOffset(); }
1302
1303 /// Returns the AA info that describes the dereference.
1304 AAMDNodes getAAInfo() const { return MMO->getAAInfo(); }
1305
1306 /// Returns the Ranges that describes the dereference.
1307 const MDNode *getRanges() const { return MMO->getRanges(); }
1308
1309 /// Returns the synchronization scope ID for this memory operation.
1310 SyncScope::ID getSyncScopeID() const { return MMO->getSyncScopeID(); }
1311
1312 /// Return the atomic ordering requirements for this memory operation. For
1313 /// cmpxchg atomic operations, return the atomic ordering requirements when
1314 /// store occurs.
1315 AtomicOrdering getSuccessOrdering() const {
1316 return MMO->getSuccessOrdering();
1317 }
1318
1319 /// Return a single atomic ordering that is at least as strong as both the
1320 /// success and failure orderings for an atomic operation. (For operations
1321 /// other than cmpxchg, this is equivalent to getSuccessOrdering().)
1322 AtomicOrdering getMergedOrdering() const { return MMO->getMergedOrdering(); }
1323
1324 /// Return true if the memory operation ordering is Unordered or higher.
1325 bool isAtomic() const { return MMO->isAtomic(); }
1326
1327 /// Returns true if the memory operation doesn't imply any ordering
1328 /// constraints on surrounding memory operations beyond the normal memory
1329 /// aliasing rules.
1330 bool isUnordered() const { return MMO->isUnordered(); }
1331
1332 /// Returns true if the memory operation is neither atomic or volatile.
1333 bool isSimple() const { return !isAtomic() && !isVolatile(); }
1334
1335 /// Return the type of the in-memory value.
1336 EVT getMemoryVT() const { return MemoryVT; }
1337
1338 /// Return a MachineMemOperand object describing the memory
1339 /// reference performed by operation.
1340 MachineMemOperand *getMemOperand() const { return MMO; }
1341
1342 const MachinePointerInfo &getPointerInfo() const {
1343 return MMO->getPointerInfo();
1344 }
1345
1346 /// Return the address space for the associated pointer
1347 unsigned getAddressSpace() const {
1348 return getPointerInfo().getAddrSpace();
1349 }
1350
1351 /// Update this MemSDNode's MachineMemOperand information
1352 /// to reflect the alignment of NewMMO, if it has a greater alignment.
1353 /// This must only be used when the new alignment applies to all users of
1354 /// this MachineMemOperand.
1355 void refineAlignment(const MachineMemOperand *NewMMO) {
1356 MMO->refineAlignment(NewMMO);
1357 }
1358
1359 const SDValue &getChain() const { return getOperand(0); }
1360
1361 const SDValue &getBasePtr() const {
1362 switch (getOpcode()) {
1363 case ISD::STORE:
1364 case ISD::VP_STORE:
1365 case ISD::MSTORE:
1366 case ISD::VP_SCATTER:
1367 return getOperand(2);
1368 case ISD::MGATHER:
1369 case ISD::MSCATTER:
1370 return getOperand(3);
1371 default:
1372 return getOperand(1);
1373 }
1374 }
1375
1376 // Methods to support isa and dyn_cast
1377 static bool classof(const SDNode *N) {
1378 // For some targets, we lower some target intrinsics to a MemIntrinsicNode
1379 // with either an intrinsic or a target opcode.
1380 switch (N->getOpcode()) {
1381 case ISD::LOAD:
1382 case ISD::STORE:
1383 case ISD::PREFETCH:
1384 case ISD::ATOMIC_CMP_SWAP:
1385 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
1386 case ISD::ATOMIC_SWAP:
1387 case ISD::ATOMIC_LOAD_ADD:
1388 case ISD::ATOMIC_LOAD_SUB:
1389 case ISD::ATOMIC_LOAD_AND:
1390 case ISD::ATOMIC_LOAD_CLR:
1391 case ISD::ATOMIC_LOAD_OR:
1392 case ISD::ATOMIC_LOAD_XOR:
1393 case ISD::ATOMIC_LOAD_NAND:
1394 case ISD::ATOMIC_LOAD_MIN:
1395 case ISD::ATOMIC_LOAD_MAX:
1396 case ISD::ATOMIC_LOAD_UMIN:
1397 case ISD::ATOMIC_LOAD_UMAX:
1398 case ISD::ATOMIC_LOAD_FADD:
1399 case ISD::ATOMIC_LOAD_FSUB:
1400 case ISD::ATOMIC_LOAD:
1401 case ISD::ATOMIC_STORE:
1402 case ISD::MLOAD:
1403 case ISD::MSTORE:
1404 case ISD::MGATHER:
1405 case ISD::MSCATTER:
1406 case ISD::VP_LOAD:
1407 case ISD::VP_STORE:
1408 case ISD::VP_GATHER:
1409 case ISD::VP_SCATTER:
1410 return true;
1411 default:
1412 return N->isMemIntrinsic() || N->isTargetMemoryOpcode();
1413 }
1414 }
1415};
1416
1417/// This is an SDNode representing atomic operations.
1418class AtomicSDNode : public MemSDNode {
1419public:
1420 AtomicSDNode(unsigned Opc, unsigned Order, const DebugLoc &dl, SDVTList VTL,
1421 EVT MemVT, MachineMemOperand *MMO)
1422 : MemSDNode(Opc, Order, dl, VTL, MemVT, MMO) {
1423 assert(((Opc != ISD::ATOMIC_LOAD && Opc != ISD::ATOMIC_STORE) ||(static_cast <bool> (((Opc != ISD::ATOMIC_LOAD &&
Opc != ISD::ATOMIC_STORE) || MMO->isAtomic()) && "then why are we using an AtomicSDNode?"
) ? void (0) : __assert_fail ("((Opc != ISD::ATOMIC_LOAD && Opc != ISD::ATOMIC_STORE) || MMO->isAtomic()) && \"then why are we using an AtomicSDNode?\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1424, __extension__ __PRETTY_FUNCTION__))
1424 MMO->isAtomic()) && "then why are we using an AtomicSDNode?")(static_cast <bool> (((Opc != ISD::ATOMIC_LOAD &&
Opc != ISD::ATOMIC_STORE) || MMO->isAtomic()) && "then why are we using an AtomicSDNode?"
) ? void (0) : __assert_fail ("((Opc != ISD::ATOMIC_LOAD && Opc != ISD::ATOMIC_STORE) || MMO->isAtomic()) && \"then why are we using an AtomicSDNode?\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1424, __extension__ __PRETTY_FUNCTION__))
;
1425 }
1426
1427 const SDValue &getBasePtr() const { return getOperand(1); }
1428 const SDValue &getVal() const { return getOperand(2); }
1429
1430 /// Returns true if this SDNode represents cmpxchg atomic operation, false
1431 /// otherwise.
1432 bool isCompareAndSwap() const {
1433 unsigned Op = getOpcode();
1434 return Op == ISD::ATOMIC_CMP_SWAP ||
1435 Op == ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS;
1436 }
1437
1438 /// For cmpxchg atomic operations, return the atomic ordering requirements
1439 /// when store does not occur.
1440 AtomicOrdering getFailureOrdering() const {
1441 assert(isCompareAndSwap() && "Must be cmpxchg operation")(static_cast <bool> (isCompareAndSwap() && "Must be cmpxchg operation"
) ? void (0) : __assert_fail ("isCompareAndSwap() && \"Must be cmpxchg operation\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1441, __extension__ __PRETTY_FUNCTION__))
;
1442 return MMO->getFailureOrdering();
1443 }
1444
1445 // Methods to support isa and dyn_cast
1446 static bool classof(const SDNode *N) {
1447 return N->getOpcode() == ISD::ATOMIC_CMP_SWAP ||
1448 N->getOpcode() == ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS ||
1449 N->getOpcode() == ISD::ATOMIC_SWAP ||
1450 N->getOpcode() == ISD::ATOMIC_LOAD_ADD ||
1451 N->getOpcode() == ISD::ATOMIC_LOAD_SUB ||
1452 N->getOpcode() == ISD::ATOMIC_LOAD_AND ||
1453 N->getOpcode() == ISD::ATOMIC_LOAD_CLR ||
1454 N->getOpcode() == ISD::ATOMIC_LOAD_OR ||
1455 N->getOpcode() == ISD::ATOMIC_LOAD_XOR ||
1456 N->getOpcode() == ISD::ATOMIC_LOAD_NAND ||
1457 N->getOpcode() == ISD::ATOMIC_LOAD_MIN ||
1458 N->getOpcode() == ISD::ATOMIC_LOAD_MAX ||
1459 N->getOpcode() == ISD::ATOMIC_LOAD_UMIN ||
1460 N->getOpcode() == ISD::ATOMIC_LOAD_UMAX ||
1461 N->getOpcode() == ISD::ATOMIC_LOAD_FADD ||
1462 N->getOpcode() == ISD::ATOMIC_LOAD_FSUB ||
1463 N->getOpcode() == ISD::ATOMIC_LOAD ||
1464 N->getOpcode() == ISD::ATOMIC_STORE;
1465 }
1466};
1467
1468/// This SDNode is used for target intrinsics that touch
1469/// memory and need an associated MachineMemOperand. Its opcode may be
1470/// INTRINSIC_VOID, INTRINSIC_W_CHAIN, PREFETCH, or a target-specific opcode
1471/// with a value not less than FIRST_TARGET_MEMORY_OPCODE.
1472class MemIntrinsicSDNode : public MemSDNode {
1473public:
1474 MemIntrinsicSDNode(unsigned Opc, unsigned Order, const DebugLoc &dl,
1475 SDVTList VTs, EVT MemoryVT, MachineMemOperand *MMO)
1476 : MemSDNode(Opc, Order, dl, VTs, MemoryVT, MMO) {
1477 SDNodeBits.IsMemIntrinsic = true;
1478 }
1479
1480 // Methods to support isa and dyn_cast
1481 static bool classof(const SDNode *N) {
1482 // We lower some target intrinsics to their target opcode
1483 // early a node with a target opcode can be of this class
1484 return N->isMemIntrinsic() ||
1485 N->getOpcode() == ISD::PREFETCH ||
1486 N->isTargetMemoryOpcode();
1487 }
1488};
1489
1490/// This SDNode is used to implement the code generator
1491/// support for the llvm IR shufflevector instruction. It combines elements
1492/// from two input vectors into a new input vector, with the selection and
1493/// ordering of elements determined by an array of integers, referred to as
1494/// the shuffle mask. For input vectors of width N, mask indices of 0..N-1
1495/// refer to elements from the LHS input, and indices from N to 2N-1 the RHS.
1496/// An index of -1 is treated as undef, such that the code generator may put
1497/// any value in the corresponding element of the result.
1498class ShuffleVectorSDNode : public SDNode {
1499 // The memory for Mask is owned by the SelectionDAG's OperandAllocator, and
1500 // is freed when the SelectionDAG object is destroyed.
1501 const int *Mask;
1502
1503protected:
1504 friend class SelectionDAG;
1505
1506 ShuffleVectorSDNode(EVT VT, unsigned Order, const DebugLoc &dl, const int *M)
1507 : SDNode(ISD::VECTOR_SHUFFLE, Order, dl, getSDVTList(VT)), Mask(M) {}
1508
1509public:
1510 ArrayRef<int> getMask() const {
1511 EVT VT = getValueType(0);
1512 return makeArrayRef(Mask, VT.getVectorNumElements());
1513 }
1514
1515 int getMaskElt(unsigned Idx) const {
1516 assert(Idx < getValueType(0).getVectorNumElements() && "Idx out of range!")(static_cast <bool> (Idx < getValueType(0).getVectorNumElements
() && "Idx out of range!") ? void (0) : __assert_fail
("Idx < getValueType(0).getVectorNumElements() && \"Idx out of range!\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1516, __extension__ __PRETTY_FUNCTION__))
;
1517 return Mask[Idx];
1518 }
1519
1520 bool isSplat() const { return isSplatMask(Mask, getValueType(0)); }
1521
1522 int getSplatIndex() const {
1523 assert(isSplat() && "Cannot get splat index for non-splat!")(static_cast <bool> (isSplat() && "Cannot get splat index for non-splat!"
) ? void (0) : __assert_fail ("isSplat() && \"Cannot get splat index for non-splat!\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1523, __extension__ __PRETTY_FUNCTION__))
;
1524 EVT VT = getValueType(0);
1525 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
1526 if (Mask[i] >= 0)
1527 return Mask[i];
1528
1529 // We can choose any index value here and be correct because all elements
1530 // are undefined. Return 0 for better potential for callers to simplify.
1531 return 0;
1532 }
1533
1534 static bool isSplatMask(const int *Mask, EVT VT);
1535
1536 /// Change values in a shuffle permute mask assuming
1537 /// the two vector operands have swapped position.
1538 static void commuteMask(MutableArrayRef<int> Mask) {
1539 unsigned NumElems = Mask.size();
1540 for (unsigned i = 0; i != NumElems; ++i) {
1541 int idx = Mask[i];
1542 if (idx < 0)
1543 continue;
1544 else if (idx < (int)NumElems)
1545 Mask[i] = idx + NumElems;
1546 else
1547 Mask[i] = idx - NumElems;
1548 }
1549 }
1550
1551 static bool classof(const SDNode *N) {
1552 return N->getOpcode() == ISD::VECTOR_SHUFFLE;
1553 }
1554};
1555
1556class ConstantSDNode : public SDNode {
1557 friend class SelectionDAG;
1558
1559 const ConstantInt *Value;
1560
1561 ConstantSDNode(bool isTarget, bool isOpaque, const ConstantInt *val, EVT VT)
1562 : SDNode(isTarget ? ISD::TargetConstant : ISD::Constant, 0, DebugLoc(),
1563 getSDVTList(VT)),
1564 Value(val) {
1565 ConstantSDNodeBits.IsOpaque = isOpaque;
1566 }
1567
1568public:
1569 const ConstantInt *getConstantIntValue() const { return Value; }
1570 const APInt &getAPIntValue() const { return Value->getValue(); }
1571 uint64_t getZExtValue() const { return Value->getZExtValue(); }
1572 int64_t getSExtValue() const { return Value->getSExtValue(); }
1573 uint64_t getLimitedValue(uint64_t Limit = UINT64_MAX(18446744073709551615UL)) {
1574 return Value->getLimitedValue(Limit);
1575 }
1576 MaybeAlign getMaybeAlignValue() const { return Value->getMaybeAlignValue(); }
1577 Align getAlignValue() const { return Value->getAlignValue(); }
1578
1579 bool isOne() const { return Value->isOne(); }
1580 bool isZero() const { return Value->isZero(); }
1581 // NOTE: This is soft-deprecated. Please use `isZero()` instead.
1582 bool isNullValue() const { return isZero(); }
1583 bool isAllOnes() const { return Value->isMinusOne(); }
1584 // NOTE: This is soft-deprecated. Please use `isAllOnes()` instead.
1585 bool isAllOnesValue() const { return isAllOnes(); }
1586 bool isMaxSignedValue() const { return Value->isMaxValue(true); }
1587 bool isMinSignedValue() const { return Value->isMinValue(true); }
1588
1589 bool isOpaque() const { return ConstantSDNodeBits.IsOpaque; }
1590
1591 static bool classof(const SDNode *N) {
1592 return N->getOpcode() == ISD::Constant ||
1593 N->getOpcode() == ISD::TargetConstant;
1594 }
1595};
1596
1597uint64_t SDNode::getConstantOperandVal(unsigned Num) const {
1598 return cast<ConstantSDNode>(getOperand(Num))->getZExtValue();
1599}
1600
1601const APInt &SDNode::getConstantOperandAPInt(unsigned Num) const {
1602 return cast<ConstantSDNode>(getOperand(Num))->getAPIntValue();
1603}
1604
1605class ConstantFPSDNode : public SDNode {
1606 friend class SelectionDAG;
1607
1608 const ConstantFP *Value;
1609
1610 ConstantFPSDNode(bool isTarget, const ConstantFP *val, EVT VT)
1611 : SDNode(isTarget ? ISD::TargetConstantFP : ISD::ConstantFP, 0,
1612 DebugLoc(), getSDVTList(VT)),
1613 Value(val) {}
1614
1615public:
1616 const APFloat& getValueAPF() const { return Value->getValueAPF(); }
1617 const ConstantFP *getConstantFPValue() const { return Value; }
1618
1619 /// Return true if the value is positive or negative zero.
1620 bool isZero() const { return Value->isZero(); }
1621
1622 /// Return true if the value is a NaN.
1623 bool isNaN() const { return Value->isNaN(); }
1624
1625 /// Return true if the value is an infinity
1626 bool isInfinity() const { return Value->isInfinity(); }
1627
1628 /// Return true if the value is negative.
1629 bool isNegative() const { return Value->isNegative(); }
1630
1631 /// We don't rely on operator== working on double values, as
1632 /// it returns true for things that are clearly not equal, like -0.0 and 0.0.
1633 /// As such, this method can be used to do an exact bit-for-bit comparison of
1634 /// two floating point values.
1635
1636 /// We leave the version with the double argument here because it's just so
1637 /// convenient to write "2.0" and the like. Without this function we'd
1638 /// have to duplicate its logic everywhere it's called.
1639 bool isExactlyValue(double V) const {
1640 return Value->getValueAPF().isExactlyValue(V);
1641 }
1642 bool isExactlyValue(const APFloat& V) const;
1643
1644 static bool isValueValidForType(EVT VT, const APFloat& Val);
1645
1646 static bool classof(const SDNode *N) {
1647 return N->getOpcode() == ISD::ConstantFP ||
1648 N->getOpcode() == ISD::TargetConstantFP;
1649 }
1650};
1651
1652/// Returns true if \p V is a constant integer zero.
1653bool isNullConstant(SDValue V);
1654
1655/// Returns true if \p V is an FP constant with a value of positive zero.
1656bool isNullFPConstant(SDValue V);
1657
1658/// Returns true if \p V is an integer constant with all bits set.
1659bool isAllOnesConstant(SDValue V);
1660
1661/// Returns true if \p V is a constant integer one.
1662bool isOneConstant(SDValue V);
1663
1664/// Return the non-bitcasted source operand of \p V if it exists.
1665/// If \p V is not a bitcasted value, it is returned as-is.
1666SDValue peekThroughBitcasts(SDValue V);
1667
1668/// Return the non-bitcasted and one-use source operand of \p V if it exists.
1669/// If \p V is not a bitcasted one-use value, it is returned as-is.
1670SDValue peekThroughOneUseBitcasts(SDValue V);
1671
1672/// Return the non-extracted vector source operand of \p V if it exists.
1673/// If \p V is not an extracted subvector, it is returned as-is.
1674SDValue peekThroughExtractSubvectors(SDValue V);
1675
1676/// Returns true if \p V is a bitwise not operation. Assumes that an all ones
1677/// constant is canonicalized to be operand 1.
1678bool isBitwiseNot(SDValue V, bool AllowUndefs = false);
1679
1680/// Returns the SDNode if it is a constant splat BuildVector or constant int.
1681ConstantSDNode *isConstOrConstSplat(SDValue N, bool AllowUndefs = false,
1682 bool AllowTruncation = false);
1683
1684/// Returns the SDNode if it is a demanded constant splat BuildVector or
1685/// constant int.
1686ConstantSDNode *isConstOrConstSplat(SDValue N, const APInt &DemandedElts,
1687 bool AllowUndefs = false,
1688 bool AllowTruncation = false);
1689
1690/// Returns the SDNode if it is a constant splat BuildVector or constant float.
1691ConstantFPSDNode *isConstOrConstSplatFP(SDValue N, bool AllowUndefs = false);
1692
1693/// Returns the SDNode if it is a demanded constant splat BuildVector or
1694/// constant float.
1695ConstantFPSDNode *isConstOrConstSplatFP(SDValue N, const APInt &DemandedElts,
1696 bool AllowUndefs = false);
1697
1698/// Return true if the value is a constant 0 integer or a splatted vector of
1699/// a constant 0 integer (with no undefs by default).
1700/// Build vector implicit truncation is not an issue for null values.
1701bool isNullOrNullSplat(SDValue V, bool AllowUndefs = false);
1702
1703/// Return true if the value is a constant 1 integer or a splatted vector of a
1704/// constant 1 integer (with no undefs).
1705/// Does not permit build vector implicit truncation.
1706bool isOneOrOneSplat(SDValue V, bool AllowUndefs = false);
1707
1708/// Return true if the value is a constant -1 integer or a splatted vector of a
1709/// constant -1 integer (with no undefs).
1710/// Does not permit build vector implicit truncation.
1711bool isAllOnesOrAllOnesSplat(SDValue V, bool AllowUndefs = false);
1712
1713/// Return true if \p V is either a integer or FP constant.
1714inline bool isIntOrFPConstant(SDValue V) {
1715 return isa<ConstantSDNode>(V) || isa<ConstantFPSDNode>(V);
1716}
1717
1718class GlobalAddressSDNode : public SDNode {
1719 friend class SelectionDAG;
1720
1721 const GlobalValue *TheGlobal;
1722 int64_t Offset;
1723 unsigned TargetFlags;
1724
1725 GlobalAddressSDNode(unsigned Opc, unsigned Order, const DebugLoc &DL,
1726 const GlobalValue *GA, EVT VT, int64_t o,
1727 unsigned TF);
1728
1729public:
1730 const GlobalValue *getGlobal() const { return TheGlobal; }
1731 int64_t getOffset() const { return Offset; }
1732 unsigned getTargetFlags() const { return TargetFlags; }
1733 // Return the address space this GlobalAddress belongs to.
1734 unsigned getAddressSpace() const;
1735
1736 static bool classof(const SDNode *N) {
1737 return N->getOpcode() == ISD::GlobalAddress ||
1738 N->getOpcode() == ISD::TargetGlobalAddress ||
1739 N->getOpcode() == ISD::GlobalTLSAddress ||
1740 N->getOpcode() == ISD::TargetGlobalTLSAddress;
1741 }
1742};
1743
1744class FrameIndexSDNode : public SDNode {
1745 friend class SelectionDAG;
1746
1747 int FI;
1748
1749 FrameIndexSDNode(int fi, EVT VT, bool isTarg)
1750 : SDNode(isTarg ? ISD::TargetFrameIndex : ISD::FrameIndex,
1751 0, DebugLoc(), getSDVTList(VT)), FI(fi) {
1752 }
1753
1754public:
1755 int getIndex() const { return FI; }
1756
1757 static bool classof(const SDNode *N) {
1758 return N->getOpcode() == ISD::FrameIndex ||
1759 N->getOpcode() == ISD::TargetFrameIndex;
1760 }
1761};
1762
1763/// This SDNode is used for LIFETIME_START/LIFETIME_END values, which indicate
1764/// the offet and size that are started/ended in the underlying FrameIndex.
1765class LifetimeSDNode : public SDNode {
1766 friend class SelectionDAG;
1767 int64_t Size;
1768 int64_t Offset; // -1 if offset is unknown.
1769
1770 LifetimeSDNode(unsigned Opcode, unsigned Order, const DebugLoc &dl,
1771 SDVTList VTs, int64_t Size, int64_t Offset)
1772 : SDNode(Opcode, Order, dl, VTs), Size(Size), Offset(Offset) {}
1773public:
1774 int64_t getFrameIndex() const {
1775 return cast<FrameIndexSDNode>(getOperand(1))->getIndex();
1776 }
1777
1778 bool hasOffset() const { return Offset >= 0; }
1779 int64_t getOffset() const {
1780 assert(hasOffset() && "offset is unknown")(static_cast <bool> (hasOffset() && "offset is unknown"
) ? void (0) : __assert_fail ("hasOffset() && \"offset is unknown\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1780, __extension__ __PRETTY_FUNCTION__))
;
1781 return Offset;
1782 }
1783 int64_t getSize() const {
1784 assert(hasOffset() && "offset is unknown")(static_cast <bool> (hasOffset() && "offset is unknown"
) ? void (0) : __assert_fail ("hasOffset() && \"offset is unknown\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1784, __extension__ __PRETTY_FUNCTION__))
;
1785 return Size;
1786 }
1787
1788 // Methods to support isa and dyn_cast
1789 static bool classof(const SDNode *N) {
1790 return N->getOpcode() == ISD::LIFETIME_START ||
1791 N->getOpcode() == ISD::LIFETIME_END;
1792 }
1793};
1794
1795/// This SDNode is used for PSEUDO_PROBE values, which are the function guid and
1796/// the index of the basic block being probed. A pseudo probe serves as a place
1797/// holder and will be removed at the end of compilation. It does not have any
1798/// operand because we do not want the instruction selection to deal with any.
1799class PseudoProbeSDNode : public SDNode {
1800 friend class SelectionDAG;
1801 uint64_t Guid;
1802 uint64_t Index;
1803 uint32_t Attributes;
1804
1805 PseudoProbeSDNode(unsigned Opcode, unsigned Order, const DebugLoc &Dl,
1806 SDVTList VTs, uint64_t Guid, uint64_t Index, uint32_t Attr)
1807 : SDNode(Opcode, Order, Dl, VTs), Guid(Guid), Index(Index),
1808 Attributes(Attr) {}
1809
1810public:
1811 uint64_t getGuid() const { return Guid; }
1812 uint64_t getIndex() const { return Index; }
1813 uint32_t getAttributes() const { return Attributes; }
1814
1815 // Methods to support isa and dyn_cast
1816 static bool classof(const SDNode *N) {
1817 return N->getOpcode() == ISD::PSEUDO_PROBE;
1818 }
1819};
1820
1821class JumpTableSDNode : public SDNode {
1822 friend class SelectionDAG;
1823
1824 int JTI;
1825 unsigned TargetFlags;
1826
1827 JumpTableSDNode(int jti, EVT VT, bool isTarg, unsigned TF)
1828 : SDNode(isTarg ? ISD::TargetJumpTable : ISD::JumpTable,
1829 0, DebugLoc(), getSDVTList(VT)), JTI(jti), TargetFlags(TF) {
1830 }
1831
1832public:
1833 int getIndex() const { return JTI; }
1834 unsigned getTargetFlags() const { return TargetFlags; }
1835
1836 static bool classof(const SDNode *N) {
1837 return N->getOpcode() == ISD::JumpTable ||
1838 N->getOpcode() == ISD::TargetJumpTable;
1839 }
1840};
1841
1842class ConstantPoolSDNode : public SDNode {
1843 friend class SelectionDAG;
1844
1845 union {
1846 const Constant *ConstVal;
1847 MachineConstantPoolValue *MachineCPVal;
1848 } Val;
1849 int Offset; // It's a MachineConstantPoolValue if top bit is set.
1850 Align Alignment; // Minimum alignment requirement of CP.
1851 unsigned TargetFlags;
1852
1853 ConstantPoolSDNode(bool isTarget, const Constant *c, EVT VT, int o,
1854 Align Alignment, unsigned TF)
1855 : SDNode(isTarget ? ISD::TargetConstantPool : ISD::ConstantPool, 0,
1856 DebugLoc(), getSDVTList(VT)),
1857 Offset(o), Alignment(Alignment), TargetFlags(TF) {
1858 assert(Offset >= 0 && "Offset is too large")(static_cast <bool> (Offset >= 0 && "Offset is too large"
) ? void (0) : __assert_fail ("Offset >= 0 && \"Offset is too large\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1858, __extension__ __PRETTY_FUNCTION__))
;
1859 Val.ConstVal = c;
1860 }
1861
1862 ConstantPoolSDNode(bool isTarget, MachineConstantPoolValue *v, EVT VT, int o,
1863 Align Alignment, unsigned TF)
1864 : SDNode(isTarget ? ISD::TargetConstantPool : ISD::ConstantPool, 0,
1865 DebugLoc(), getSDVTList(VT)),
1866 Offset(o), Alignment(Alignment), TargetFlags(TF) {
1867 assert(Offset >= 0 && "Offset is too large")(static_cast <bool> (Offset >= 0 && "Offset is too large"
) ? void (0) : __assert_fail ("Offset >= 0 && \"Offset is too large\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1867, __extension__ __PRETTY_FUNCTION__))
;
1868 Val.MachineCPVal = v;
1869 Offset |= 1 << (sizeof(unsigned)*CHAR_BIT8-1);
1870 }
1871
1872public:
1873 bool isMachineConstantPoolEntry() const {
1874 return Offset < 0;
1875 }
1876
1877 const Constant *getConstVal() const {
1878 assert(!isMachineConstantPoolEntry() && "Wrong constantpool type")(static_cast <bool> (!isMachineConstantPoolEntry() &&
"Wrong constantpool type") ? void (0) : __assert_fail ("!isMachineConstantPoolEntry() && \"Wrong constantpool type\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1878, __extension__ __PRETTY_FUNCTION__))
;
1879 return Val.ConstVal;
1880 }
1881
1882 MachineConstantPoolValue *getMachineCPVal() const {
1883 assert(isMachineConstantPoolEntry() && "Wrong constantpool type")(static_cast <bool> (isMachineConstantPoolEntry() &&
"Wrong constantpool type") ? void (0) : __assert_fail ("isMachineConstantPoolEntry() && \"Wrong constantpool type\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1883, __extension__ __PRETTY_FUNCTION__))
;
1884 return Val.MachineCPVal;
1885 }
1886
1887 int getOffset() const {
1888 return Offset & ~(1 << (sizeof(unsigned)*CHAR_BIT8-1));
1889 }
1890
1891 // Return the alignment of this constant pool object, which is either 0 (for
1892 // default alignment) or the desired value.
1893 Align getAlign() const { return Alignment; }
1894 unsigned getTargetFlags() const { return TargetFlags; }
1895
1896 Type *getType() const;
1897
1898 static bool classof(const SDNode *N) {
1899 return N->getOpcode() == ISD::ConstantPool ||
1900 N->getOpcode() == ISD::TargetConstantPool;
1901 }
1902};
1903
1904/// Completely target-dependent object reference.
1905class TargetIndexSDNode : public SDNode {
1906 friend class SelectionDAG;
1907
1908 unsigned TargetFlags;
1909 int Index;
1910 int64_t Offset;
1911
1912public:
1913 TargetIndexSDNode(int Idx, EVT VT, int64_t Ofs, unsigned TF)
1914 : SDNode(ISD::TargetIndex, 0, DebugLoc(), getSDVTList(VT)),
1915 TargetFlags(TF), Index(Idx), Offset(Ofs) {}
1916
1917 unsigned getTargetFlags() const { return TargetFlags; }
1918 int getIndex() const { return Index; }
1919 int64_t getOffset() const { return Offset; }
1920
1921 static bool classof(const SDNode *N) {
1922 return N->getOpcode() == ISD::TargetIndex;
1923 }
1924};
1925
1926class BasicBlockSDNode : public SDNode {
1927 friend class SelectionDAG;
1928
1929 MachineBasicBlock *MBB;
1930
1931 /// Debug info is meaningful and potentially useful here, but we create
1932 /// blocks out of order when they're jumped to, which makes it a bit
1933 /// harder. Let's see if we need it first.
1934 explicit BasicBlockSDNode(MachineBasicBlock *mbb)
1935 : SDNode(ISD::BasicBlock, 0, DebugLoc(), getSDVTList(MVT::Other)), MBB(mbb)
1936 {}
1937
1938public:
1939 MachineBasicBlock *getBasicBlock() const { return MBB; }
1940
1941 static bool classof(const SDNode *N) {
1942 return N->getOpcode() == ISD::BasicBlock;
1943 }
1944};
1945
1946/// A "pseudo-class" with methods for operating on BUILD_VECTORs.
1947class BuildVectorSDNode : public SDNode {
1948public:
1949 // These are constructed as SDNodes and then cast to BuildVectorSDNodes.
1950 explicit BuildVectorSDNode() = delete;
1951
1952 /// Check if this is a constant splat, and if so, find the
1953 /// smallest element size that splats the vector. If MinSplatBits is
1954 /// nonzero, the element size must be at least that large. Note that the
1955 /// splat element may be the entire vector (i.e., a one element vector).
1956 /// Returns the splat element value in SplatValue. Any undefined bits in
1957 /// that value are zero, and the corresponding bits in the SplatUndef mask
1958 /// are set. The SplatBitSize value is set to the splat element size in
1959 /// bits. HasAnyUndefs is set to true if any bits in the vector are
1960 /// undefined. isBigEndian describes the endianness of the target.
1961 bool isConstantSplat(APInt &SplatValue, APInt &SplatUndef,
1962 unsigned &SplatBitSize, bool &HasAnyUndefs,
1963 unsigned MinSplatBits = 0,
1964 bool isBigEndian = false) const;
1965
1966 /// Returns the demanded splatted value or a null value if this is not a
1967 /// splat.
1968 ///
1969 /// The DemandedElts mask indicates the elements that must be in the splat.
1970 /// If passed a non-null UndefElements bitvector, it will resize it to match
1971 /// the vector width and set the bits where elements are undef.
1972 SDValue getSplatValue(const APInt &DemandedElts,
1973 BitVector *UndefElements = nullptr) const;
1974
1975 /// Returns the splatted value or a null value if this is not a splat.
1976 ///
1977 /// If passed a non-null UndefElements bitvector, it will resize it to match
1978 /// the vector width and set the bits where elements are undef.
1979 SDValue getSplatValue(BitVector *UndefElements = nullptr) const;
1980
1981 /// Find the shortest repeating sequence of values in the build vector.
1982 ///
1983 /// e.g. { u, X, u, X, u, u, X, u } -> { X }
1984 /// { X, Y, u, Y, u, u, X, u } -> { X, Y }
1985 ///
1986 /// Currently this must be a power-of-2 build vector.
1987 /// The DemandedElts mask indicates the elements that must be present,
1988 /// undemanded elements in Sequence may be null (SDValue()). If passed a
1989 /// non-null UndefElements bitvector, it will resize it to match the original
1990 /// vector width and set the bits where elements are undef. If result is
1991 /// false, Sequence will be empty.
1992 bool getRepeatedSequence(const APInt &DemandedElts,
1993 SmallVectorImpl<SDValue> &Sequence,
1994 BitVector *UndefElements = nullptr) const;
1995
1996 /// Find the shortest repeating sequence of values in the build vector.
1997 ///
1998 /// e.g. { u, X, u, X, u, u, X, u } -> { X }
1999 /// { X, Y, u, Y, u, u, X, u } -> { X, Y }
2000 ///
2001 /// Currently this must be a power-of-2 build vector.
2002 /// If passed a non-null UndefElements bitvector, it will resize it to match
2003 /// the original vector width and set the bits where elements are undef.
2004 /// If result is false, Sequence will be empty.
2005 bool getRepeatedSequence(SmallVectorImpl<SDValue> &Sequence,
2006 BitVector *UndefElements = nullptr) const;
2007
2008 /// Returns the demanded splatted constant or null if this is not a constant
2009 /// splat.
2010 ///
2011 /// The DemandedElts mask indicates the elements that must be in the splat.
2012 /// If passed a non-null UndefElements bitvector, it will resize it to match
2013 /// the vector width and set the bits where elements are undef.
2014 ConstantSDNode *
2015 getConstantSplatNode(const APInt &DemandedElts,
2016 BitVector *UndefElements = nullptr) const;
2017
2018 /// Returns the splatted constant or null if this is not a constant
2019 /// splat.
2020 ///
2021 /// If passed a non-null UndefElements bitvector, it will resize it to match
2022 /// the vector width and set the bits where elements are undef.
2023 ConstantSDNode *
2024 getConstantSplatNode(BitVector *UndefElements = nullptr) const;
2025
2026 /// Returns the demanded splatted constant FP or null if this is not a
2027 /// constant FP splat.
2028 ///
2029 /// The DemandedElts mask indicates the elements that must be in the splat.
2030 /// If passed a non-null UndefElements bitvector, it will resize it to match
2031 /// the vector width and set the bits where elements are undef.
2032 ConstantFPSDNode *
2033 getConstantFPSplatNode(const APInt &DemandedElts,
2034 BitVector *UndefElements = nullptr) const;
2035
2036 /// Returns the splatted constant FP or null if this is not a constant
2037 /// FP splat.
2038 ///
2039 /// If passed a non-null UndefElements bitvector, it will resize it to match
2040 /// the vector width and set the bits where elements are undef.
2041 ConstantFPSDNode *
2042 getConstantFPSplatNode(BitVector *UndefElements = nullptr) const;
2043
2044 /// If this is a constant FP splat and the splatted constant FP is an
2045 /// exact power or 2, return the log base 2 integer value. Otherwise,
2046 /// return -1.
2047 ///
2048 /// The BitWidth specifies the necessary bit precision.
2049 int32_t getConstantFPSplatPow2ToLog2Int(BitVector *UndefElements,
2050 uint32_t BitWidth) const;
2051
2052 bool isConstant() const;
2053
2054 static bool classof(const SDNode *N) {
2055 return N->getOpcode() == ISD::BUILD_VECTOR;
2056 }
2057};
2058
2059/// An SDNode that holds an arbitrary LLVM IR Value. This is
2060/// used when the SelectionDAG needs to make a simple reference to something
2061/// in the LLVM IR representation.
2062///
2063class SrcValueSDNode : public SDNode {
2064 friend class SelectionDAG;
2065
2066 const Value *V;
2067
2068 /// Create a SrcValue for a general value.
2069 explicit SrcValueSDNode(const Value *v)
2070 : SDNode(ISD::SRCVALUE, 0, DebugLoc(), getSDVTList(MVT::Other)), V(v) {}
2071
2072public:
2073 /// Return the contained Value.
2074 const Value *getValue() const { return V; }
2075
2076 static bool classof(const SDNode *N) {
2077 return N->getOpcode() == ISD::SRCVALUE;
2078 }
2079};
2080
2081class MDNodeSDNode : public SDNode {
2082 friend class SelectionDAG;
2083
2084 const MDNode *MD;
2085
2086 explicit MDNodeSDNode(const MDNode *md)
2087 : SDNode(ISD::MDNODE_SDNODE, 0, DebugLoc(), getSDVTList(MVT::Other)), MD(md)
2088 {}
2089
2090public:
2091 const MDNode *getMD() const { return MD; }
2092
2093 static bool classof(const SDNode *N) {
2094 return N->getOpcode() == ISD::MDNODE_SDNODE;
2095 }
2096};
2097
2098class RegisterSDNode : public SDNode {
2099 friend class SelectionDAG;
2100
2101 Register Reg;
2102
2103 RegisterSDNode(Register reg, EVT VT)
2104 : SDNode(ISD::Register, 0, DebugLoc(), getSDVTList(VT)), Reg(reg) {}
2105
2106public:
2107 Register getReg() const { return Reg; }
2108
2109 static bool classof(const SDNode *N) {
2110 return N->getOpcode() == ISD::Register;
2111 }
2112};
2113
2114class RegisterMaskSDNode : public SDNode {
2115 friend class SelectionDAG;
2116
2117 // The memory for RegMask is not owned by the node.
2118 const uint32_t *RegMask;
2119
2120 RegisterMaskSDNode(const uint32_t *mask)
2121 : SDNode(ISD::RegisterMask, 0, DebugLoc(), getSDVTList(MVT::Untyped)),
2122 RegMask(mask) {}
2123
2124public:
2125 const uint32_t *getRegMask() const { return RegMask; }
2126
2127 static bool classof(const SDNode *N) {
2128 return N->getOpcode() == ISD::RegisterMask;
2129 }
2130};
2131
2132class BlockAddressSDNode : public SDNode {
2133 friend class SelectionDAG;
2134
2135 const BlockAddress *BA;
2136 int64_t Offset;
2137 unsigned TargetFlags;
2138
2139 BlockAddressSDNode(unsigned NodeTy, EVT VT, const BlockAddress *ba,
2140 int64_t o, unsigned Flags)
2141 : SDNode(NodeTy, 0, DebugLoc(), getSDVTList(VT)),
2142 BA(ba), Offset(o), TargetFlags(Flags) {}
2143
2144public:
2145 const BlockAddress *getBlockAddress() const { return BA; }
2146 int64_t getOffset() const { return Offset; }
2147 unsigned getTargetFlags() const { return TargetFlags; }
2148
2149 static bool classof(const SDNode *N) {
2150 return N->getOpcode() == ISD::BlockAddress ||
2151 N->getOpcode() == ISD::TargetBlockAddress;
2152 }
2153};
2154
2155class LabelSDNode : public SDNode {
2156 friend class SelectionDAG;
2157
2158 MCSymbol *Label;
2159
2160 LabelSDNode(unsigned Opcode, unsigned Order, const DebugLoc &dl, MCSymbol *L)
2161 : SDNode(Opcode, Order, dl, getSDVTList(MVT::Other)), Label(L) {
2162 assert(LabelSDNode::classof(this) && "not a label opcode")(static_cast <bool> (LabelSDNode::classof(this) &&
"not a label opcode") ? void (0) : __assert_fail ("LabelSDNode::classof(this) && \"not a label opcode\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 2162, __extension__ __PRETTY_FUNCTION__))
;
2163 }
2164
2165public:
2166 MCSymbol *getLabel() const { return Label; }
2167
2168 static bool classof(const SDNode *N) {
2169 return N->getOpcode() == ISD::EH_LABEL ||
2170 N->getOpcode() == ISD::ANNOTATION_LABEL;
2171 }
2172};
2173
2174class ExternalSymbolSDNode : public SDNode {
2175 friend class SelectionDAG;
2176
2177 const char *Symbol;
2178 unsigned TargetFlags;
2179
2180 ExternalSymbolSDNode(bool isTarget, const char *Sym, unsigned TF, EVT VT)
2181 : SDNode(isTarget ? ISD::TargetExternalSymbol : ISD::ExternalSymbol, 0,
2182 DebugLoc(), getSDVTList(VT)),
2183 Symbol(Sym), TargetFlags(TF) {}
2184
2185public:
2186 const char *getSymbol() const { return Symbol; }
2187 unsigned getTargetFlags() const { return TargetFlags; }
2188
2189 static bool classof(const SDNode *N) {
2190 return N->getOpcode() == ISD::ExternalSymbol ||
2191 N->getOpcode() == ISD::TargetExternalSymbol;
2192 }
2193};
2194
2195class MCSymbolSDNode : public SDNode {
2196 friend class SelectionDAG;
2197
2198 MCSymbol *Symbol;
2199
2200 MCSymbolSDNode(MCSymbol *Symbol, EVT VT)
2201 : SDNode(ISD::MCSymbol, 0, DebugLoc(), getSDVTList(VT)), Symbol(Symbol) {}
2202
2203public:
2204 MCSymbol *getMCSymbol() const { return Symbol; }
2205
2206 static bool classof(const SDNode *N) {
2207 return N->getOpcode() == ISD::MCSymbol;
2208 }
2209};
2210
2211class CondCodeSDNode : public SDNode {
2212 friend class SelectionDAG;
2213
2214 ISD::CondCode Condition;
2215
2216 explicit CondCodeSDNode(ISD::CondCode Cond)
2217 : SDNode(ISD::CONDCODE, 0, DebugLoc(), getSDVTList(MVT::Other)),
2218 Condition(Cond) {}
2219
2220public:
2221 ISD::CondCode get() const { return Condition; }
2222
2223 static bool classof(const SDNode *N) {
2224 return N->getOpcode() == ISD::CONDCODE;
2225 }
2226};
2227
2228/// This class is used to represent EVT's, which are used
2229/// to parameterize some operations.
2230class VTSDNode : public SDNode {
2231 friend class SelectionDAG;
2232
2233 EVT ValueType;
2234
2235 explicit VTSDNode(EVT VT)
2236 : SDNode(ISD::VALUETYPE, 0, DebugLoc(), getSDVTList(MVT::Other)),
2237 ValueType(VT) {}
2238
2239public:
2240 EVT getVT() const { return ValueType; }
2241
2242 static bool classof(const SDNode *N) {
2243 return N->getOpcode() == ISD::VALUETYPE;
2244 }
2245};
2246
2247/// Base class for LoadSDNode and StoreSDNode
2248class LSBaseSDNode : public MemSDNode {
2249public:
2250 LSBaseSDNode(ISD::NodeType NodeTy, unsigned Order, const DebugLoc &dl,
2251 SDVTList VTs, ISD::MemIndexedMode AM, EVT MemVT,
2252 MachineMemOperand *MMO)
2253 : MemSDNode(NodeTy, Order, dl, VTs, MemVT, MMO) {
2254 LSBaseSDNodeBits.AddressingMode = AM;
2255 assert(getAddressingMode() == AM && "Value truncated")(static_cast <bool> (getAddressingMode() == AM &&
"Value truncated") ? void (0) : __assert_fail ("getAddressingMode() == AM && \"Value truncated\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 2255, __extension__ __PRETTY_FUNCTION__))
;
2256 }
2257
2258 const SDValue &getOffset() const {
2259 return getOperand(getOpcode() == ISD::LOAD ? 2 : 3);
2260 }
2261
2262 /// Return the addressing mode for this load or store:
2263 /// unindexed, pre-inc, pre-dec, post-inc, or post-dec.
2264 ISD::MemIndexedMode getAddressingMode() const {
2265 return static_cast<ISD::MemIndexedMode>(LSBaseSDNodeBits.AddressingMode);
2266 }
2267
2268 /// Return true if this is a pre/post inc/dec load/store.
2269 bool isIndexed() const { return getAddressingMode() != ISD::UNINDEXED; }
2270
2271 /// Return true if this is NOT a pre/post inc/dec load/store.
2272 bool isUnindexed() const { return getAddressingMode() == ISD::UNINDEXED; }
2273
2274 static bool classof(const SDNode *N) {
2275 return N->getOpcode() == ISD::LOAD ||
2276 N->getOpcode() == ISD::STORE;
2277 }
2278};
2279
2280/// This class is used to represent ISD::LOAD nodes.
2281class LoadSDNode : public LSBaseSDNode {
2282 friend class SelectionDAG;
2283
2284 LoadSDNode(unsigned Order, const DebugLoc &dl, SDVTList VTs,
2285 ISD::MemIndexedMode AM, ISD::LoadExtType ETy, EVT MemVT,
2286 MachineMemOperand *MMO)
2287 : LSBaseSDNode(ISD::LOAD, Order, dl, VTs, AM, MemVT, MMO) {
2288 LoadSDNodeBits.ExtTy = ETy;
2289 assert(readMem() && "Load MachineMemOperand is not a load!")(static_cast <bool> (readMem() && "Load MachineMemOperand is not a load!"
) ? void (0) : __assert_fail ("readMem() && \"Load MachineMemOperand is not a load!\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 2289, __extension__ __PRETTY_FUNCTION__))
;
2290 assert(!writeMem() && "Load MachineMemOperand is a store!")(static_cast <bool> (!writeMem() && "Load MachineMemOperand is a store!"
) ? void (0) : __assert_fail ("!writeMem() && \"Load MachineMemOperand is a store!\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 2290, __extension__ __PRETTY_FUNCTION__))
;
2291 }
2292
2293public:
2294 /// Return whether this is a plain node,
2295 /// or one of the varieties of value-extending loads.
2296 ISD::LoadExtType getExtensionType() const {
2297 return static_cast<ISD::LoadExtType>(LoadSDNodeBits.ExtTy);
2298 }
2299
2300 const SDValue &getBasePtr() const { return getOperand(1); }
2301 const SDValue &getOffset() const { return getOperand(2); }
2302
2303 static bool classof(const SDNode *N) {
2304 return N->getOpcode() == ISD::LOAD;
2305 }
2306};
2307
2308/// This class is used to represent ISD::STORE nodes.
2309class StoreSDNode : public LSBaseSDNode {
2310 friend class SelectionDAG;
2311
2312 StoreSDNode(unsigned Order, const DebugLoc &dl, SDVTList VTs,
2313 ISD::MemIndexedMode AM, bool isTrunc, EVT MemVT,
2314 MachineMemOperand *MMO)
2315 : LSBaseSDNode(ISD::STORE, Order, dl, VTs, AM, MemVT, MMO) {
2316 StoreSDNodeBits.IsTruncating = isTrunc;
2317 assert(!readMem() && "Store MachineMemOperand is a load!")(static_cast <bool> (!readMem() && "Store MachineMemOperand is a load!"
) ? void (0) : __assert_fail ("!readMem() && \"Store MachineMemOperand is a load!\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 2317, __extension__ __PRETTY_FUNCTION__))
;
2318 assert(writeMem() && "Store MachineMemOperand is not a store!")(static_cast <bool> (writeMem() && "Store MachineMemOperand is not a store!"
) ? void (0) : __assert_fail ("writeMem() && \"Store MachineMemOperand is not a store!\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 2318, __extension__ __PRETTY_FUNCTION__))
;
2319 }
2320
2321public:
2322 /// Return true if the op does a truncation before store.
2323 /// For integers this is the same as doing a TRUNCATE and storing the result.
2324 /// For floats, it is the same as doing an FP_ROUND and storing the result.
2325 bool isTruncatingStore() const { return StoreSDNodeBits.IsTruncating; }
2326 void setTruncatingStore(bool Truncating) {
2327 StoreSDNodeBits.IsTruncating = Truncating;
2328 }
2329
2330 const SDValue &getValue() const { return getOperand(1); }
2331 const SDValue &getBasePtr() const { return getOperand(2); }
2332 const SDValue &getOffset() const { return getOperand(3); }
2333
2334 static bool classof(const SDNode *N) {
2335 return N->getOpcode() == ISD::STORE;
2336 }
2337};
2338
2339/// This base class is used to represent VP_LOAD and VP_STORE nodes
2340class VPLoadStoreSDNode : public MemSDNode {
2341public:
2342 friend class SelectionDAG;
2343
2344 VPLoadStoreSDNode(ISD::NodeType NodeTy, unsigned Order, const DebugLoc &dl,
2345 SDVTList VTs, ISD::MemIndexedMode AM, EVT MemVT,
2346 MachineMemOperand *MMO)
2347 : MemSDNode(NodeTy, Order, dl, VTs, MemVT, MMO) {
2348 LSBaseSDNodeBits.AddressingMode = AM;
2349 assert(getAddressingMode() == AM && "Value truncated")(static_cast <bool> (getAddressingMode() == AM &&
"Value truncated") ? void (0) : __assert_fail ("getAddressingMode() == AM && \"Value truncated\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 2349, __extension__ __PRETTY_FUNCTION__))
;
2350 }
2351
2352 // VPLoadSDNode (Chain, Ptr, Offset, Mask, EVL)
2353 // VPStoreSDNode (Chain, Data, Ptr, Offset, Mask, EVL)
2354 // Mask is a vector of i1 elements;
2355 // the type of EVL is TLI.getVPExplicitVectorLengthTy().
2356 const SDValue &getOffset() const {
2357 return getOperand(getOpcode() == ISD::MLOAD ? 2 : 3);
2358 }
2359 const SDValue &getBasePtr() const {
2360 return getOperand(getOpcode() == ISD::VP_LOAD ? 1 : 2);
2361 }
2362 const SDValue &getMask() const {
2363 return getOperand(getOpcode() == ISD::VP_LOAD ? 3 : 4);
2364 }
2365 const SDValue &getVectorLength() const {
2366 return getOperand(getOpcode() == ISD::VP_LOAD ? 4 : 5);
2367 }
2368
2369 /// Return the addressing mode for this load or store:
2370 /// unindexed, pre-inc, pre-dec, post-inc, or post-dec.
2371 ISD::MemIndexedMode getAddressingMode() const {
2372 return static_cast<ISD::MemIndexedMode>(LSBaseSDNodeBits.AddressingMode);
2373 }
2374
2375 /// Return true if this is a pre/post inc/dec load/store.
2376 bool isIndexed() const { return getAddressingMode() != ISD::UNINDEXED; }
2377
2378 /// Return true if this is NOT a pre/post inc/dec load/store.
2379 bool isUnindexed() const { return getAddressingMode() == ISD::UNINDEXED; }
2380
2381 static bool classof(const SDNode *N) {
2382 return N->getOpcode() == ISD::VP_LOAD || N->getOpcode() == ISD::VP_STORE;
2383 }
2384};
2385
2386/// This class is used to represent a VP_LOAD node
2387class VPLoadSDNode : public VPLoadStoreSDNode {
2388public:
2389 friend class SelectionDAG;
2390
2391 VPLoadSDNode(unsigned Order, const DebugLoc &dl, SDVTList VTs,
2392 ISD::MemIndexedMode AM, ISD::LoadExtType ETy, bool isExpanding,
2393 EVT MemVT, MachineMemOperand *MMO)
2394 : VPLoadStoreSDNode(ISD::VP_LOAD, Order, dl, VTs, AM, MemVT, MMO) {
2395 LoadSDNodeBits.ExtTy = ETy;
2396 LoadSDNodeBits.IsExpanding = isExpanding;
2397 }
2398
2399 ISD::LoadExtType getExtensionType() const {
2400 return static_cast<ISD::LoadExtType>(LoadSDNodeBits.ExtTy);
2401 }
2402
2403 const SDValue &getBasePtr() const { return getOperand(1); }
2404 const SDValue &getOffset() const { return getOperand(2); }
2405 const SDValue &getMask() const { return getOperand(3); }
2406 const SDValue &getVectorLength() const { return getOperand(4); }
2407
2408 static bool classof(const SDNode *N) {
2409 return N->getOpcode() == ISD::VP_LOAD;
2410 }
2411 bool isExpandingLoad() const { return LoadSDNodeBits.IsExpanding; }
2412};
2413
2414/// This class is used to represent a VP_STORE node
2415class VPStoreSDNode : public VPLoadStoreSDNode {
2416public:
2417 friend class SelectionDAG;
2418
2419 VPStoreSDNode(unsigned Order, const DebugLoc &dl, SDVTList VTs,
2420 ISD::MemIndexedMode AM, bool isTrunc, bool isCompressing,
2421 EVT MemVT, MachineMemOperand *MMO)
2422 : VPLoadStoreSDNode(ISD::VP_STORE, Order, dl, VTs, AM, MemVT, MMO) {
2423 StoreSDNodeBits.IsTruncating = isTrunc;
2424 StoreSDNodeBits.IsCompressing = isCompressing;
2425 }
2426
2427 /// Return true if this is a truncating store.
2428 /// For integers this is the same as doing a TRUNCATE and storing the result.
2429 /// For floats, it is the same as doing an FP_ROUND and storing the result.
2430 bool isTruncatingStore() const { return StoreSDNodeBits.IsTruncating; }
2431
2432 /// Returns true if the op does a compression to the vector before storing.
2433 /// The node contiguously stores the active elements (integers or floats)
2434 /// in src (those with their respective bit set in writemask k) to unaligned
2435 /// memory at base_addr.
2436 bool isCompressingStore() const { return StoreSDNodeBits.IsCompressing; }
2437
2438 const SDValue &getValue() const { return getOperand(1); }
2439 const SDValue &getBasePtr() const { return getOperand(2); }
2440 const SDValue &getOffset() const { return getOperand(3); }
2441 const SDValue &getMask() const { return getOperand(4); }
2442 const SDValue &getVectorLength() const { return getOperand(5); }
2443
2444 static bool classof(const SDNode *N) {
2445 return N->getOpcode() == ISD::VP_STORE;
2446 }
2447};
2448
2449/// This base class is used to represent MLOAD and MSTORE nodes
2450class MaskedLoadStoreSDNode : public MemSDNode {
2451public:
2452 friend class SelectionDAG;
2453
2454 MaskedLoadStoreSDNode(ISD::NodeType NodeTy, unsigned Order,
2455 const DebugLoc &dl, SDVTList VTs,
2456 ISD::MemIndexedMode AM, EVT MemVT,
2457 MachineMemOperand *MMO)
2458 : MemSDNode(NodeTy, Order, dl, VTs, MemVT, MMO) {
2459 LSBaseSDNodeBits.AddressingMode = AM;
2460 assert(getAddressingMode() == AM && "Value truncated")(static_cast <bool> (getAddressingMode() == AM &&
"Value truncated") ? void (0) : __assert_fail ("getAddressingMode() == AM && \"Value truncated\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 2460, __extension__ __PRETTY_FUNCTION__))
;
2461 }
2462
2463 // MaskedLoadSDNode (Chain, ptr, offset, mask, passthru)
2464 // MaskedStoreSDNode (Chain, data, ptr, offset, mask)
2465 // Mask is a vector of i1 elements
2466 const SDValue &getOffset() const {
2467 return getOperand(getOpcode() == ISD::MLOAD ? 2 : 3);
2468 }
2469 const SDValue &getMask() const {
2470 return getOperand(getOpcode() == ISD::MLOAD ? 3 : 4);
2471 }
2472
2473 /// Return the addressing mode for this load or store:
2474 /// unindexed, pre-inc, pre-dec, post-inc, or post-dec.
2475 ISD::MemIndexedMode getAddressingMode() const {
2476 return static_cast<ISD::MemIndexedMode>(LSBaseSDNodeBits.AddressingMode);
2477 }
2478
2479 /// Return true if this is a pre/post inc/dec load/store.
2480 bool isIndexed() const { return getAddressingMode() != ISD::UNINDEXED; }
2481
2482 /// Return true if this is NOT a pre/post inc/dec load/store.
2483 bool isUnindexed() const { return getAddressingMode() == ISD::UNINDEXED; }
2484
2485 static bool classof(const SDNode *N) {
2486 return N->getOpcode() == ISD::MLOAD ||
2487 N->getOpcode() == ISD::MSTORE;
2488 }
2489};
2490
2491/// This class is used to represent an MLOAD node
2492class MaskedLoadSDNode : public MaskedLoadStoreSDNode {
2493public:
2494 friend class SelectionDAG;
2495
2496 MaskedLoadSDNode(unsigned Order, const DebugLoc &dl, SDVTList VTs,
2497 ISD::MemIndexedMode AM, ISD::LoadExtType ETy,
2498 bool IsExpanding, EVT MemVT, MachineMemOperand *MMO)
2499 : MaskedLoadStoreSDNode(ISD::MLOAD, Order, dl, VTs, AM, MemVT, MMO) {
2500 LoadSDNodeBits.ExtTy = ETy;
2501 LoadSDNodeBits.IsExpanding = IsExpanding;
2502 }
2503
2504 ISD::LoadExtType getExtensionType() const {
2505 return static_cast<ISD::LoadExtType>(LoadSDNodeBits.ExtTy);
2506 }
2507
2508 const SDValue &getBasePtr() const { return getOperand(1); }
2509 const SDValue &getOffset() const { return getOperand(2); }
2510 const SDValue &getMask() const { return getOperand(3); }
2511 const SDValue &getPassThru() const { return getOperand(4); }
2512
2513 static bool classof(const SDNode *N) {
2514 return N->getOpcode() == ISD::MLOAD;
2515 }
2516
2517 bool isExpandingLoad() const { return LoadSDNodeBits.IsExpanding; }
2518};
2519
2520/// This class is used to represent an MSTORE node
2521class MaskedStoreSDNode : public MaskedLoadStoreSDNode {
2522public:
2523 friend class SelectionDAG;
2524
2525 MaskedStoreSDNode(unsigned Order, const DebugLoc &dl, SDVTList VTs,
2526 ISD::MemIndexedMode AM, bool isTrunc, bool isCompressing,
2527 EVT MemVT, MachineMemOperand *MMO)
2528 : MaskedLoadStoreSDNode(ISD::MSTORE, Order, dl, VTs, AM, MemVT, MMO) {
2529 StoreSDNodeBits.IsTruncating = isTrunc;
2530 StoreSDNodeBits.IsCompressing = isCompressing;
2531 }
2532
2533 /// Return true if the op does a truncation before store.
2534 /// For integers this is the same as doing a TRUNCATE and storing the result.
2535 /// For floats, it is the same as doing an FP_ROUND and storing the result.
2536 bool isTruncatingStore() const { return StoreSDNodeBits.IsTruncating; }
2537
2538 /// Returns true if the op does a compression to the vector before storing.
2539 /// The node contiguously stores the active elements (integers or floats)
2540 /// in src (those with their respective bit set in writemask k) to unaligned
2541 /// memory at base_addr.
2542 bool isCompressingStore() const { return StoreSDNodeBits.IsCompressing; }
2543
2544 const SDValue &getValue() const { return getOperand(1); }
2545 const SDValue &getBasePtr() const { return getOperand(2); }
2546 const SDValue &getOffset() const { return getOperand(3); }
2547 const SDValue &getMask() const { return getOperand(4); }
2548
2549 static bool classof(const SDNode *N) {
2550 return N->getOpcode() == ISD::MSTORE;
2551 }
2552};
2553
2554/// This is a base class used to represent
2555/// VP_GATHER and VP_SCATTER nodes
2556///
2557class VPGatherScatterSDNode : public MemSDNode {
2558public:
2559 friend class SelectionDAG;
2560
2561 VPGatherScatterSDNode(ISD::NodeType NodeTy, unsigned Order,
2562 const DebugLoc &dl, SDVTList VTs, EVT MemVT,
2563 MachineMemOperand *MMO, ISD::MemIndexType IndexType)
2564 : MemSDNode(NodeTy, Order, dl, VTs, MemVT, MMO) {
2565 LSBaseSDNodeBits.AddressingMode = IndexType;
2566 assert(getIndexType() == IndexType && "Value truncated")(static_cast <bool> (getIndexType() == IndexType &&
"Value truncated") ? void (0) : __assert_fail ("getIndexType() == IndexType && \"Value truncated\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 2566, __extension__ __PRETTY_FUNCTION__))
;
2567 }
2568
2569 /// How is Index applied to BasePtr when computing addresses.
2570 ISD::MemIndexType getIndexType() const {
2571 return static_cast<ISD::MemIndexType>(LSBaseSDNodeBits.AddressingMode);
2572 }
2573 bool isIndexScaled() const {
2574 return (getIndexType() == ISD::SIGNED_SCALED) ||
2575 (getIndexType() == ISD::UNSIGNED_SCALED);
2576 }
2577 bool isIndexSigned() const {
2578 return (getIndexType() == ISD::SIGNED_SCALED) ||
2579 (getIndexType() == ISD::SIGNED_UNSCALED);
2580 }
2581
2582 // In the both nodes address is Op1, mask is Op2:
2583 // VPGatherSDNode (Chain, base, index, scale, mask, vlen)
2584 // VPScatterSDNode (Chain, value, base, index, scale, mask, vlen)
2585 // Mask is a vector of i1 elements
2586 const SDValue &getBasePtr() const {
2587 return getOperand((getOpcode() == ISD::VP_GATHER) ? 1 : 2);
2588 }
2589 const SDValue &getIndex() const {
2590 return getOperand((getOpcode() == ISD::VP_GATHER) ? 2 : 3);
2591 }
2592 const SDValue &getScale() const {
2593 return getOperand((getOpcode() == ISD::VP_GATHER) ? 3 : 4);
2594 }
2595 const SDValue &getMask() const {
2596 return getOperand((getOpcode() == ISD::VP_GATHER) ? 4 : 5);
2597 }
2598 const SDValue &getVectorLength() const {
2599 return getOperand((getOpcode() == ISD::VP_GATHER) ? 5 : 6);
2600 }
2601
2602 static bool classof(const SDNode *N) {
2603 return N->getOpcode() == ISD::VP_GATHER ||
2604 N->getOpcode() == ISD::VP_SCATTER;
2605 }
2606};
2607
2608/// This class is used to represent an VP_GATHER node
2609///
2610class VPGatherSDNode : public VPGatherScatterSDNode {
2611public:
2612 friend class SelectionDAG;
2613
2614 VPGatherSDNode(unsigned Order, const DebugLoc &dl, SDVTList VTs, EVT MemVT,
2615 MachineMemOperand *MMO, ISD::MemIndexType IndexType)
2616 : VPGatherScatterSDNode(ISD::VP_GATHER, Order, dl, VTs, MemVT, MMO,
2617 IndexType) {}
2618
2619 static bool classof(const SDNode *N) {
2620 return N->getOpcode() == ISD::VP_GATHER;
2621 }
2622};
2623
2624/// This class is used to represent an VP_SCATTER node
2625///
2626class VPScatterSDNode : public VPGatherScatterSDNode {
2627public:
2628 friend class SelectionDAG;
2629
2630 VPScatterSDNode(unsigned Order, const DebugLoc &dl, SDVTList VTs, EVT MemVT,
2631 MachineMemOperand *MMO, ISD::MemIndexType IndexType)
2632 : VPGatherScatterSDNode(ISD::VP_SCATTER, Order, dl, VTs, MemVT, MMO,
2633 IndexType) {}
2634
2635 const SDValue &getValue() const { return getOperand(1); }
2636
2637 static bool classof(const SDNode *N) {
2638 return N->getOpcode() == ISD::VP_SCATTER;
2639 }
2640};
2641
2642/// This is a base class used to represent
2643/// MGATHER and MSCATTER nodes
2644///
2645class MaskedGatherScatterSDNode : public MemSDNode {
2646public:
2647 friend class SelectionDAG;
2648
2649 MaskedGatherScatterSDNode(ISD::NodeType NodeTy, unsigned Order,
2650 const DebugLoc &dl, SDVTList VTs, EVT MemVT,
2651 MachineMemOperand *MMO, ISD::MemIndexType IndexType)
2652 : MemSDNode(NodeTy, Order, dl, VTs, MemVT, MMO) {
2653 LSBaseSDNodeBits.AddressingMode = IndexType;
2654 assert(getIndexType() == IndexType && "Value truncated")(static_cast <bool> (getIndexType() == IndexType &&
"Value truncated") ? void (0) : __assert_fail ("getIndexType() == IndexType && \"Value truncated\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 2654, __extension__ __PRETTY_FUNCTION__))
;
2655 }
2656
2657 /// How is Index applied to BasePtr when computing addresses.
2658 ISD::MemIndexType getIndexType() const {
2659 return static_cast<ISD::MemIndexType>(LSBaseSDNodeBits.AddressingMode);
2660 }
2661 void setIndexType(ISD::MemIndexType IndexType) {
2662 LSBaseSDNodeBits.AddressingMode = IndexType;
2663 }
2664 bool isIndexScaled() const {
2665 return (getIndexType() == ISD::SIGNED_SCALED) ||
2666 (getIndexType() == ISD::UNSIGNED_SCALED);
2667 }
2668 bool isIndexSigned() const {
2669 return (getIndexType() == ISD::SIGNED_SCALED) ||
2670 (getIndexType() == ISD::SIGNED_UNSCALED);
2671 }
2672
2673 // In the both nodes address is Op1, mask is Op2:
2674 // MaskedGatherSDNode (Chain, passthru, mask, base, index, scale)
2675 // MaskedScatterSDNode (Chain, value, mask, base, index, scale)
2676 // Mask is a vector of i1 elements
2677 const SDValue &getBasePtr() const { return getOperand(3); }
2678 const SDValue &getIndex() const { return getOperand(4); }
2679 const SDValue &getMask() const { return getOperand(2); }
2680 const SDValue &getScale() const { return getOperand(5); }
2681
2682 static bool classof(const SDNode *N) {
2683 return N->getOpcode() == ISD::MGATHER ||
2684 N->getOpcode() == ISD::MSCATTER;
2685 }
2686};
2687
2688/// This class is used to represent an MGATHER node
2689///
2690class MaskedGatherSDNode : public MaskedGatherScatterSDNode {
2691public:
2692 friend class SelectionDAG;
2693
2694 MaskedGatherSDNode(unsigned Order, const DebugLoc &dl, SDVTList VTs,
2695 EVT MemVT, MachineMemOperand *MMO,
2696 ISD::MemIndexType IndexType, ISD::LoadExtType ETy)
2697 : MaskedGatherScatterSDNode(ISD::MGATHER, Order, dl, VTs, MemVT, MMO,
2698 IndexType) {
2699 LoadSDNodeBits.ExtTy = ETy;
2700 }
2701
2702 const SDValue &getPassThru() const { return getOperand(1); }
2703
2704 ISD::LoadExtType getExtensionType() const {
2705 return ISD::LoadExtType(LoadSDNodeBits.ExtTy);
2706 }
2707
2708 static bool classof(const SDNode *N) {
2709 return N->getOpcode() == ISD::MGATHER;
2710 }
2711};
2712
2713/// This class is used to represent an MSCATTER node
2714///
2715class MaskedScatterSDNode : public MaskedGatherScatterSDNode {
2716public:
2717 friend class SelectionDAG;
2718
2719 MaskedScatterSDNode(unsigned Order, const DebugLoc &dl, SDVTList VTs,
2720 EVT MemVT, MachineMemOperand *MMO,
2721 ISD::MemIndexType IndexType, bool IsTrunc)
2722 : MaskedGatherScatterSDNode(ISD::MSCATTER, Order, dl, VTs, MemVT, MMO,
2723 IndexType) {
2724 StoreSDNodeBits.IsTruncating = IsTrunc;
2725 }
2726
2727 /// Return true if the op does a truncation before store.
2728 /// For integers this is the same as doing a TRUNCATE and storing the result.
2729 /// For floats, it is the same as doing an FP_ROUND and storing the result.
2730 bool isTruncatingStore() const { return StoreSDNodeBits.IsTruncating; }
2731
2732 const SDValue &getValue() const { return getOperand(1); }
2733
2734 static bool classof(const SDNode *N) {
2735 return N->getOpcode() == ISD::MSCATTER;
2736 }
2737};
2738
2739/// An SDNode that represents everything that will be needed
2740/// to construct a MachineInstr. These nodes are created during the
2741/// instruction selection proper phase.
2742///
2743/// Note that the only supported way to set the `memoperands` is by calling the
2744/// `SelectionDAG::setNodeMemRefs` function as the memory management happens
2745/// inside the DAG rather than in the node.
2746class MachineSDNode : public SDNode {
2747private:
2748 friend class SelectionDAG;
2749
2750 MachineSDNode(unsigned Opc, unsigned Order, const DebugLoc &DL, SDVTList VTs)
2751 : SDNode(Opc, Order, DL, VTs) {}
2752
2753 // We use a pointer union between a single `MachineMemOperand` pointer and
2754 // a pointer to an array of `MachineMemOperand` pointers. This is null when
2755 // the number of these is zero, the single pointer variant used when the
2756 // number is one, and the array is used for larger numbers.
2757 //
2758 // The array is allocated via the `SelectionDAG`'s allocator and so will
2759 // always live until the DAG is cleaned up and doesn't require ownership here.
2760 //
2761 // We can't use something simpler like `TinyPtrVector` here because `SDNode`
2762 // subclasses aren't managed in a conforming C++ manner. See the comments on
2763 // `SelectionDAG::MorphNodeTo` which details what all goes on, but the
2764 // constraint here is that these don't manage memory with their constructor or
2765 // destructor and can be initialized to a good state even if they start off
2766 // uninitialized.
2767 PointerUnion<MachineMemOperand *, MachineMemOperand **> MemRefs = {};
2768
2769 // Note that this could be folded into the above `MemRefs` member if doing so
2770 // is advantageous at some point. We don't need to store this in most cases.
2771 // However, at the moment this doesn't appear to make the allocation any
2772 // smaller and makes the code somewhat simpler to read.
2773 int NumMemRefs = 0;
2774
2775public:
2776 using mmo_iterator = ArrayRef<MachineMemOperand *>::const_iterator;
2777
2778 ArrayRef<MachineMemOperand *> memoperands() const {
2779 // Special case the common cases.
2780 if (NumMemRefs == 0)
2781 return {};
2782 if (NumMemRefs == 1)
2783 return makeArrayRef(MemRefs.getAddrOfPtr1(), 1);
2784
2785 // Otherwise we have an actual array.
2786 return makeArrayRef(MemRefs.get<MachineMemOperand **>(), NumMemRefs);
2787 }
2788 mmo_iterator memoperands_begin() const { return memoperands().begin(); }
2789 mmo_iterator memoperands_end() const { return memoperands().end(); }
2790 bool memoperands_empty() const { return memoperands().empty(); }
2791
2792 /// Clear out the memory reference descriptor list.
2793 void clearMemRefs() {
2794 MemRefs = nullptr;
2795 NumMemRefs = 0;
2796 }
2797
2798 static bool classof(const SDNode *N) {
2799 return N->isMachineOpcode();
2800 }
2801};
2802
2803/// An SDNode that records if a register contains a value that is guaranteed to
2804/// be aligned accordingly.
2805class AssertAlignSDNode : public SDNode {
2806 Align Alignment;
2807
2808public:
2809 AssertAlignSDNode(unsigned Order, const DebugLoc &DL, EVT VT, Align A)
2810 : SDNode(ISD::AssertAlign, Order, DL, getSDVTList(VT)), Alignment(A) {}
2811
2812 Align getAlign() const { return Alignment; }
2813
2814 static bool classof(const SDNode *N) {
2815 return N->getOpcode() == ISD::AssertAlign;
2816 }
2817};
2818
2819class SDNodeIterator {
2820 const SDNode *Node;
2821 unsigned Operand;
2822
2823 SDNodeIterator(const SDNode *N, unsigned Op) : Node(N), Operand(Op) {}
2824
2825public:
2826 using iterator_category = std::forward_iterator_tag;
2827 using value_type = SDNode;
2828 using difference_type = std::ptrdiff_t;
2829 using pointer = value_type *;
2830 using reference = value_type &;
2831
2832 bool operator==(const SDNodeIterator& x) const {
2833 return Operand == x.Operand;
2834 }
2835 bool operator!=(const SDNodeIterator& x) const { return !operator==(x); }
2836
2837 pointer operator*() const {
2838 return Node->getOperand(Operand).getNode();
2839 }
2840 pointer operator->() const { return operator*(); }
2841
2842 SDNodeIterator& operator++() { // Preincrement
2843 ++Operand;
2844 return *this;
2845 }
2846 SDNodeIterator operator++(int) { // Postincrement
2847 SDNodeIterator tmp = *this; ++*this; return tmp;
2848 }
2849 size_t operator-(SDNodeIterator Other) const {
2850 assert(Node == Other.Node &&(static_cast <bool> (Node == Other.Node && "Cannot compare iterators of two different nodes!"
) ? void (0) : __assert_fail ("Node == Other.Node && \"Cannot compare iterators of two different nodes!\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 2851, __extension__ __PRETTY_FUNCTION__))
2851 "Cannot compare iterators of two different nodes!")(static_cast <bool> (Node == Other.Node && "Cannot compare iterators of two different nodes!"
) ? void (0) : __assert_fail ("Node == Other.Node && \"Cannot compare iterators of two different nodes!\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 2851, __extension__ __PRETTY_FUNCTION__))
;
2852 return Operand - Other.Operand;
2853 }
2854
2855 static SDNodeIterator begin(const SDNode *N) { return SDNodeIterator(N, 0); }
2856 static SDNodeIterator end (const SDNode *N) {
2857 return SDNodeIterator(N, N->getNumOperands());
2858 }
2859
2860 unsigned getOperand() const { return Operand; }
2861 const SDNode *getNode() const { return Node; }
2862};
2863
2864template <> struct GraphTraits<SDNode*> {
2865 using NodeRef = SDNode *;
2866 using ChildIteratorType = SDNodeIterator;
2867
2868 static NodeRef getEntryNode(SDNode *N) { return N; }
2869
2870 static ChildIteratorType child_begin(NodeRef N) {
2871 return SDNodeIterator::begin(N);
2872 }
2873
2874 static ChildIteratorType child_end(NodeRef N) {
2875 return SDNodeIterator::end(N);
2876 }
2877};
2878
2879/// A representation of the largest SDNode, for use in sizeof().
2880///
2881/// This needs to be a union because the largest node differs on 32 bit systems
2882/// with 4 and 8 byte pointer alignment, respectively.
2883using LargestSDNode = AlignedCharArrayUnion<AtomicSDNode, TargetIndexSDNode,
2884 BlockAddressSDNode,
2885 GlobalAddressSDNode,
2886 PseudoProbeSDNode>;
2887
2888/// The SDNode class with the greatest alignment requirement.
2889using MostAlignedSDNode = GlobalAddressSDNode;
2890
2891namespace ISD {
2892
2893 /// Returns true if the specified node is a non-extending and unindexed load.
2894 inline bool isNormalLoad(const SDNode *N) {
2895 const LoadSDNode *Ld = dyn_cast<LoadSDNode>(N);
2896 return Ld && Ld->getExtensionType() == ISD::NON_EXTLOAD &&
2897 Ld->getAddressingMode() == ISD::UNINDEXED;
2898 }
2899
2900 /// Returns true if the specified node is a non-extending load.
2901 inline bool isNON_EXTLoad(const SDNode *N) {
2902 return isa<LoadSDNode>(N) &&
2903 cast<LoadSDNode>(N)->getExtensionType() == ISD::NON_EXTLOAD;
2904 }
2905
2906 /// Returns true if the specified node is a EXTLOAD.
2907 inline bool isEXTLoad(const SDNode *N) {
2908 return isa<LoadSDNode>(N) &&
2909 cast<LoadSDNode>(N)->getExtensionType() == ISD::EXTLOAD;
2910 }
2911
2912 /// Returns true if the specified node is a SEXTLOAD.
2913 inline bool isSEXTLoad(const SDNode *N) {
2914 return isa<LoadSDNode>(N) &&
2915 cast<LoadSDNode>(N)->getExtensionType() == ISD::SEXTLOAD;
2916 }
2917
2918 /// Returns true if the specified node is a ZEXTLOAD.
2919 inline bool isZEXTLoad(const SDNode *N) {
2920 return isa<LoadSDNode>(N) &&
2921 cast<LoadSDNode>(N)->getExtensionType() == ISD::ZEXTLOAD;
2922 }
2923
2924 /// Returns true if the specified node is an unindexed load.
2925 inline bool isUNINDEXEDLoad(const SDNode *N) {
2926 return isa<LoadSDNode>(N) &&
2927 cast<LoadSDNode>(N)->getAddressingMode() == ISD::UNINDEXED;
2928 }
2929
2930 /// Returns true if the specified node is a non-truncating
2931 /// and unindexed store.
2932 inline bool isNormalStore(const SDNode *N) {
2933 const StoreSDNode *St = dyn_cast<StoreSDNode>(N);
2934 return St && !St->isTruncatingStore() &&
2935 St->getAddressingMode() == ISD::UNINDEXED;
2936 }
2937
2938 /// Returns true if the specified node is an unindexed store.
2939 inline bool isUNINDEXEDStore(const SDNode *N) {
2940 return isa<StoreSDNode>(N) &&
2941 cast<StoreSDNode>(N)->getAddressingMode() == ISD::UNINDEXED;
2942 }
2943
2944 /// Attempt to match a unary predicate against a scalar/splat constant or
2945 /// every element of a constant BUILD_VECTOR.
2946 /// If AllowUndef is true, then UNDEF elements will pass nullptr to Match.
2947 bool matchUnaryPredicate(SDValue Op,
2948 std::function<bool(ConstantSDNode *)> Match,
2949 bool AllowUndefs = false);
2950
2951 /// Attempt to match a binary predicate against a pair of scalar/splat
2952 /// constants or every element of a pair of constant BUILD_VECTORs.
2953 /// If AllowUndef is true, then UNDEF elements will pass nullptr to Match.
2954 /// If AllowTypeMismatch is true then RetType + ArgTypes don't need to match.
2955 bool matchBinaryPredicate(
2956 SDValue LHS, SDValue RHS,
2957 std::function<bool(ConstantSDNode *, ConstantSDNode *)> Match,
2958 bool AllowUndefs = false, bool AllowTypeMismatch = false);
2959
2960 /// Returns true if the specified value is the overflow result from one
2961 /// of the overflow intrinsic nodes.
2962 inline bool isOverflowIntrOpRes(SDValue Op) {
2963 unsigned Opc = Op.getOpcode();
2964 return (Op.getResNo() == 1 &&
2965 (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO ||
2966 Opc == ISD::USUBO || Opc == ISD::SMULO || Opc == ISD::UMULO));
2967 }
2968
2969} // end namespace ISD
2970
2971} // end namespace llvm
2972
2973#endif // LLVM_CODEGEN_SELECTIONDAGNODES_H