Bug Summary

File:llvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp
Warning:line 1095, column 17
The left operand of '==' is a garbage value

Annotated Source Code

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clang -cc1 -cc1 -triple x86_64-pc-linux-gnu -analyze -disable-free -clear-ast-before-backend -disable-llvm-verifier -discard-value-names -main-file-name SystemZAsmParser.cpp -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=cplusplus -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -analyzer-config-compatibility-mode=true -mrelocation-model pic -pic-level 2 -mframe-pointer=none -fmath-errno -ffp-contract=on -fno-rounding-math -mconstructor-aliases -funwind-tables=2 -target-cpu x86-64 -tune-cpu generic -debugger-tuning=gdb -ffunction-sections -fdata-sections -fcoverage-compilation-dir=/build/llvm-toolchain-snapshot-14~++20220116100644+5f782d25a742/build-llvm/tools/clang/stage2-bins -resource-dir /usr/lib/llvm-14/lib/clang/14.0.0 -D _DEBUG -D _GNU_SOURCE -D __STDC_CONSTANT_MACROS -D __STDC_FORMAT_MACROS -D __STDC_LIMIT_MACROS -I lib/Target/SystemZ/AsmParser -I /build/llvm-toolchain-snapshot-14~++20220116100644+5f782d25a742/llvm/lib/Target/SystemZ/AsmParser -I /build/llvm-toolchain-snapshot-14~++20220116100644+5f782d25a742/llvm/lib/Target/SystemZ -I lib/Target/SystemZ -I include -I /build/llvm-toolchain-snapshot-14~++20220116100644+5f782d25a742/llvm/include -D _FORTIFY_SOURCE=2 -D NDEBUG -U NDEBUG -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/10/../../../../include/c++/10 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/10/../../../../include/x86_64-linux-gnu/c++/10 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/10/../../../../include/c++/10/backward -internal-isystem /usr/lib/llvm-14/lib/clang/14.0.0/include -internal-isystem /usr/local/include -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/10/../../../../x86_64-linux-gnu/include -internal-externc-isystem /usr/include/x86_64-linux-gnu -internal-externc-isystem /include -internal-externc-isystem /usr/include -fmacro-prefix-map=/build/llvm-toolchain-snapshot-14~++20220116100644+5f782d25a742/build-llvm/tools/clang/stage2-bins=build-llvm/tools/clang/stage2-bins -fmacro-prefix-map=/build/llvm-toolchain-snapshot-14~++20220116100644+5f782d25a742/= -fcoverage-prefix-map=/build/llvm-toolchain-snapshot-14~++20220116100644+5f782d25a742/build-llvm/tools/clang/stage2-bins=build-llvm/tools/clang/stage2-bins -fcoverage-prefix-map=/build/llvm-toolchain-snapshot-14~++20220116100644+5f782d25a742/= -O3 -Wno-unused-command-line-argument -Wno-unused-parameter -Wwrite-strings -Wno-missing-field-initializers -Wno-long-long -Wno-maybe-uninitialized -Wno-class-memaccess -Wno-redundant-move -Wno-pessimizing-move -Wno-noexcept-type -Wno-comment -std=c++14 -fdeprecated-macro -fdebug-compilation-dir=/build/llvm-toolchain-snapshot-14~++20220116100644+5f782d25a742/build-llvm/tools/clang/stage2-bins -fdebug-prefix-map=/build/llvm-toolchain-snapshot-14~++20220116100644+5f782d25a742/build-llvm/tools/clang/stage2-bins=build-llvm/tools/clang/stage2-bins -fdebug-prefix-map=/build/llvm-toolchain-snapshot-14~++20220116100644+5f782d25a742/= -ferror-limit 19 -fvisibility hidden -fvisibility-inlines-hidden -stack-protector 2 -fgnuc-version=4.2.1 -fcolor-diagnostics -vectorize-loops -vectorize-slp -analyzer-output=html -analyzer-config stable-report-filename=true -faddrsig -D__GCC_HAVE_DWARF2_CFI_ASM=1 -o /tmp/scan-build-2022-01-16-232930-107970-1 -x c++ /build/llvm-toolchain-snapshot-14~++20220116100644+5f782d25a742/llvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp
1//===-- SystemZAsmParser.cpp - Parse SystemZ assembly instructions --------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9#include "MCTargetDesc/SystemZInstPrinter.h"
10#include "MCTargetDesc/SystemZMCAsmInfo.h"
11#include "MCTargetDesc/SystemZMCTargetDesc.h"
12#include "SystemZTargetStreamer.h"
13#include "TargetInfo/SystemZTargetInfo.h"
14#include "llvm/ADT/STLExtras.h"
15#include "llvm/ADT/SmallVector.h"
16#include "llvm/ADT/StringRef.h"
17#include "llvm/MC/MCAsmInfo.h"
18#include "llvm/MC/MCContext.h"
19#include "llvm/MC/MCExpr.h"
20#include "llvm/MC/MCInst.h"
21#include "llvm/MC/MCInstBuilder.h"
22#include "llvm/MC/MCParser/MCAsmLexer.h"
23#include "llvm/MC/MCParser/MCAsmParser.h"
24#include "llvm/MC/MCParser/MCAsmParserExtension.h"
25#include "llvm/MC/MCParser/MCParsedAsmOperand.h"
26#include "llvm/MC/MCParser/MCTargetAsmParser.h"
27#include "llvm/MC/MCStreamer.h"
28#include "llvm/MC/MCSubtargetInfo.h"
29#include "llvm/MC/TargetRegistry.h"
30#include "llvm/Support/Casting.h"
31#include "llvm/Support/ErrorHandling.h"
32#include "llvm/Support/SMLoc.h"
33#include <algorithm>
34#include <cassert>
35#include <cstddef>
36#include <cstdint>
37#include <iterator>
38#include <memory>
39#include <string>
40
41using namespace llvm;
42
43// Return true if Expr is in the range [MinValue, MaxValue]. If AllowSymbol
44// is true any MCExpr is accepted (address displacement).
45static bool inRange(const MCExpr *Expr, int64_t MinValue, int64_t MaxValue,
46 bool AllowSymbol = false) {
47 if (auto *CE = dyn_cast<MCConstantExpr>(Expr)) {
48 int64_t Value = CE->getValue();
49 return Value >= MinValue && Value <= MaxValue;
50 }
51 return AllowSymbol;
52}
53
54namespace {
55
56enum RegisterKind {
57 GR32Reg,
58 GRH32Reg,
59 GR64Reg,
60 GR128Reg,
61 FP32Reg,
62 FP64Reg,
63 FP128Reg,
64 VR32Reg,
65 VR64Reg,
66 VR128Reg,
67 AR32Reg,
68 CR64Reg,
69};
70
71enum MemoryKind {
72 BDMem,
73 BDXMem,
74 BDLMem,
75 BDRMem,
76 BDVMem
77};
78
79class SystemZOperand : public MCParsedAsmOperand {
80private:
81 enum OperandKind {
82 KindInvalid,
83 KindToken,
84 KindReg,
85 KindImm,
86 KindImmTLS,
87 KindMem
88 };
89
90 OperandKind Kind;
91 SMLoc StartLoc, EndLoc;
92
93 // A string of length Length, starting at Data.
94 struct TokenOp {
95 const char *Data;
96 unsigned Length;
97 };
98
99 // LLVM register Num, which has kind Kind. In some ways it might be
100 // easier for this class to have a register bank (general, floating-point
101 // or access) and a raw register number (0-15). This would postpone the
102 // interpretation of the operand to the add*() methods and avoid the need
103 // for context-dependent parsing. However, we do things the current way
104 // because of the virtual getReg() method, which needs to distinguish
105 // between (say) %r0 used as a single register and %r0 used as a pair.
106 // Context-dependent parsing can also give us slightly better error
107 // messages when invalid pairs like %r1 are used.
108 struct RegOp {
109 RegisterKind Kind;
110 unsigned Num;
111 };
112
113 // Base + Disp + Index, where Base and Index are LLVM registers or 0.
114 // MemKind says what type of memory this is and RegKind says what type
115 // the base register has (GR32Reg or GR64Reg). Length is the operand
116 // length for D(L,B)-style operands, otherwise it is null.
117 struct MemOp {
118 unsigned Base : 12;
119 unsigned Index : 12;
120 unsigned MemKind : 4;
121 unsigned RegKind : 4;
122 const MCExpr *Disp;
123 union {
124 const MCExpr *Imm;
125 unsigned Reg;
126 } Length;
127 };
128
129 // Imm is an immediate operand, and Sym is an optional TLS symbol
130 // for use with a __tls_get_offset marker relocation.
131 struct ImmTLSOp {
132 const MCExpr *Imm;
133 const MCExpr *Sym;
134 };
135
136 union {
137 TokenOp Token;
138 RegOp Reg;
139 const MCExpr *Imm;
140 ImmTLSOp ImmTLS;
141 MemOp Mem;
142 };
143
144 void addExpr(MCInst &Inst, const MCExpr *Expr) const {
145 // Add as immediates when possible. Null MCExpr = 0.
146 if (!Expr)
147 Inst.addOperand(MCOperand::createImm(0));
148 else if (auto *CE = dyn_cast<MCConstantExpr>(Expr))
149 Inst.addOperand(MCOperand::createImm(CE->getValue()));
150 else
151 Inst.addOperand(MCOperand::createExpr(Expr));
152 }
153
154public:
155 SystemZOperand(OperandKind kind, SMLoc startLoc, SMLoc endLoc)
156 : Kind(kind), StartLoc(startLoc), EndLoc(endLoc) {}
157
158 // Create particular kinds of operand.
159 static std::unique_ptr<SystemZOperand> createInvalid(SMLoc StartLoc,
160 SMLoc EndLoc) {
161 return std::make_unique<SystemZOperand>(KindInvalid, StartLoc, EndLoc);
162 }
163
164 static std::unique_ptr<SystemZOperand> createToken(StringRef Str, SMLoc Loc) {
165 auto Op = std::make_unique<SystemZOperand>(KindToken, Loc, Loc);
166 Op->Token.Data = Str.data();
167 Op->Token.Length = Str.size();
168 return Op;
169 }
170
171 static std::unique_ptr<SystemZOperand>
172 createReg(RegisterKind Kind, unsigned Num, SMLoc StartLoc, SMLoc EndLoc) {
173 auto Op = std::make_unique<SystemZOperand>(KindReg, StartLoc, EndLoc);
174 Op->Reg.Kind = Kind;
175 Op->Reg.Num = Num;
176 return Op;
177 }
178
179 static std::unique_ptr<SystemZOperand>
180 createImm(const MCExpr *Expr, SMLoc StartLoc, SMLoc EndLoc) {
181 auto Op = std::make_unique<SystemZOperand>(KindImm, StartLoc, EndLoc);
182 Op->Imm = Expr;
183 return Op;
184 }
185
186 static std::unique_ptr<SystemZOperand>
187 createMem(MemoryKind MemKind, RegisterKind RegKind, unsigned Base,
188 const MCExpr *Disp, unsigned Index, const MCExpr *LengthImm,
189 unsigned LengthReg, SMLoc StartLoc, SMLoc EndLoc) {
190 auto Op = std::make_unique<SystemZOperand>(KindMem, StartLoc, EndLoc);
191 Op->Mem.MemKind = MemKind;
192 Op->Mem.RegKind = RegKind;
193 Op->Mem.Base = Base;
194 Op->Mem.Index = Index;
195 Op->Mem.Disp = Disp;
196 if (MemKind == BDLMem)
197 Op->Mem.Length.Imm = LengthImm;
198 if (MemKind == BDRMem)
199 Op->Mem.Length.Reg = LengthReg;
200 return Op;
201 }
202
203 static std::unique_ptr<SystemZOperand>
204 createImmTLS(const MCExpr *Imm, const MCExpr *Sym,
205 SMLoc StartLoc, SMLoc EndLoc) {
206 auto Op = std::make_unique<SystemZOperand>(KindImmTLS, StartLoc, EndLoc);
207 Op->ImmTLS.Imm = Imm;
208 Op->ImmTLS.Sym = Sym;
209 return Op;
210 }
211
212 // Token operands
213 bool isToken() const override {
214 return Kind == KindToken;
215 }
216 StringRef getToken() const {
217 assert(Kind == KindToken && "Not a token")(static_cast <bool> (Kind == KindToken && "Not a token"
) ? void (0) : __assert_fail ("Kind == KindToken && \"Not a token\""
, "llvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp", 217
, __extension__ __PRETTY_FUNCTION__))
;
218 return StringRef(Token.Data, Token.Length);
219 }
220
221 // Register operands.
222 bool isReg() const override {
223 return Kind == KindReg;
224 }
225 bool isReg(RegisterKind RegKind) const {
226 return Kind == KindReg && Reg.Kind == RegKind;
227 }
228 unsigned getReg() const override {
229 assert(Kind == KindReg && "Not a register")(static_cast <bool> (Kind == KindReg && "Not a register"
) ? void (0) : __assert_fail ("Kind == KindReg && \"Not a register\""
, "llvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp", 229
, __extension__ __PRETTY_FUNCTION__))
;
230 return Reg.Num;
231 }
232
233 // Immediate operands.
234 bool isImm() const override {
235 return Kind == KindImm;
236 }
237 bool isImm(int64_t MinValue, int64_t MaxValue) const {
238 return Kind == KindImm && inRange(Imm, MinValue, MaxValue);
239 }
240 const MCExpr *getImm() const {
241 assert(Kind == KindImm && "Not an immediate")(static_cast <bool> (Kind == KindImm && "Not an immediate"
) ? void (0) : __assert_fail ("Kind == KindImm && \"Not an immediate\""
, "llvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp", 241
, __extension__ __PRETTY_FUNCTION__))
;
242 return Imm;
243 }
244
245 // Immediate operands with optional TLS symbol.
246 bool isImmTLS() const {
247 return Kind == KindImmTLS;
248 }
249
250 const ImmTLSOp getImmTLS() const {
251 assert(Kind == KindImmTLS && "Not a TLS immediate")(static_cast <bool> (Kind == KindImmTLS && "Not a TLS immediate"
) ? void (0) : __assert_fail ("Kind == KindImmTLS && \"Not a TLS immediate\""
, "llvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp", 251
, __extension__ __PRETTY_FUNCTION__))
;
252 return ImmTLS;
253 }
254
255 // Memory operands.
256 bool isMem() const override {
257 return Kind == KindMem;
258 }
259 bool isMem(MemoryKind MemKind) const {
260 return (Kind == KindMem &&
261 (Mem.MemKind == MemKind ||
262 // A BDMem can be treated as a BDXMem in which the index
263 // register field is 0.
264 (Mem.MemKind == BDMem && MemKind == BDXMem)));
265 }
266 bool isMem(MemoryKind MemKind, RegisterKind RegKind) const {
267 return isMem(MemKind) && Mem.RegKind == RegKind;
268 }
269 bool isMemDisp12(MemoryKind MemKind, RegisterKind RegKind) const {
270 return isMem(MemKind, RegKind) && inRange(Mem.Disp, 0, 0xfff, true);
271 }
272 bool isMemDisp20(MemoryKind MemKind, RegisterKind RegKind) const {
273 return isMem(MemKind, RegKind) && inRange(Mem.Disp, -524288, 524287, true);
274 }
275 bool isMemDisp12Len4(RegisterKind RegKind) const {
276 return isMemDisp12(BDLMem, RegKind) && inRange(Mem.Length.Imm, 1, 0x10);
277 }
278 bool isMemDisp12Len8(RegisterKind RegKind) const {
279 return isMemDisp12(BDLMem, RegKind) && inRange(Mem.Length.Imm, 1, 0x100);
280 }
281
282 const MemOp& getMem() const {
283 assert(Kind == KindMem && "Not a Mem operand")(static_cast <bool> (Kind == KindMem && "Not a Mem operand"
) ? void (0) : __assert_fail ("Kind == KindMem && \"Not a Mem operand\""
, "llvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp", 283
, __extension__ __PRETTY_FUNCTION__))
;
284 return Mem;
285 }
286
287 // Override MCParsedAsmOperand.
288 SMLoc getStartLoc() const override { return StartLoc; }
289 SMLoc getEndLoc() const override { return EndLoc; }
290 void print(raw_ostream &OS) const override;
291
292 /// getLocRange - Get the range between the first and last token of this
293 /// operand.
294 SMRange getLocRange() const { return SMRange(StartLoc, EndLoc); }
295
296 // Used by the TableGen code to add particular types of operand
297 // to an instruction.
298 void addRegOperands(MCInst &Inst, unsigned N) const {
299 assert(N == 1 && "Invalid number of operands")(static_cast <bool> (N == 1 && "Invalid number of operands"
) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands\""
, "llvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp", 299
, __extension__ __PRETTY_FUNCTION__))
;
300 Inst.addOperand(MCOperand::createReg(getReg()));
301 }
302 void addImmOperands(MCInst &Inst, unsigned N) const {
303 assert(N == 1 && "Invalid number of operands")(static_cast <bool> (N == 1 && "Invalid number of operands"
) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands\""
, "llvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp", 303
, __extension__ __PRETTY_FUNCTION__))
;
304 addExpr(Inst, getImm());
305 }
306 void addBDAddrOperands(MCInst &Inst, unsigned N) const {
307 assert(N == 2 && "Invalid number of operands")(static_cast <bool> (N == 2 && "Invalid number of operands"
) ? void (0) : __assert_fail ("N == 2 && \"Invalid number of operands\""
, "llvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp", 307
, __extension__ __PRETTY_FUNCTION__))
;
308 assert(isMem(BDMem) && "Invalid operand type")(static_cast <bool> (isMem(BDMem) && "Invalid operand type"
) ? void (0) : __assert_fail ("isMem(BDMem) && \"Invalid operand type\""
, "llvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp", 308
, __extension__ __PRETTY_FUNCTION__))
;
309 Inst.addOperand(MCOperand::createReg(Mem.Base));
310 addExpr(Inst, Mem.Disp);
311 }
312 void addBDXAddrOperands(MCInst &Inst, unsigned N) const {
313 assert(N == 3 && "Invalid number of operands")(static_cast <bool> (N == 3 && "Invalid number of operands"
) ? void (0) : __assert_fail ("N == 3 && \"Invalid number of operands\""
, "llvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp", 313
, __extension__ __PRETTY_FUNCTION__))
;
314 assert(isMem(BDXMem) && "Invalid operand type")(static_cast <bool> (isMem(BDXMem) && "Invalid operand type"
) ? void (0) : __assert_fail ("isMem(BDXMem) && \"Invalid operand type\""
, "llvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp", 314
, __extension__ __PRETTY_FUNCTION__))
;
315 Inst.addOperand(MCOperand::createReg(Mem.Base));
316 addExpr(Inst, Mem.Disp);
317 Inst.addOperand(MCOperand::createReg(Mem.Index));
318 }
319 void addBDLAddrOperands(MCInst &Inst, unsigned N) const {
320 assert(N == 3 && "Invalid number of operands")(static_cast <bool> (N == 3 && "Invalid number of operands"
) ? void (0) : __assert_fail ("N == 3 && \"Invalid number of operands\""
, "llvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp", 320
, __extension__ __PRETTY_FUNCTION__))
;
321 assert(isMem(BDLMem) && "Invalid operand type")(static_cast <bool> (isMem(BDLMem) && "Invalid operand type"
) ? void (0) : __assert_fail ("isMem(BDLMem) && \"Invalid operand type\""
, "llvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp", 321
, __extension__ __PRETTY_FUNCTION__))
;
322 Inst.addOperand(MCOperand::createReg(Mem.Base));
323 addExpr(Inst, Mem.Disp);
324 addExpr(Inst, Mem.Length.Imm);
325 }
326 void addBDRAddrOperands(MCInst &Inst, unsigned N) const {
327 assert(N == 3 && "Invalid number of operands")(static_cast <bool> (N == 3 && "Invalid number of operands"
) ? void (0) : __assert_fail ("N == 3 && \"Invalid number of operands\""
, "llvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp", 327
, __extension__ __PRETTY_FUNCTION__))
;
328 assert(isMem(BDRMem) && "Invalid operand type")(static_cast <bool> (isMem(BDRMem) && "Invalid operand type"
) ? void (0) : __assert_fail ("isMem(BDRMem) && \"Invalid operand type\""
, "llvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp", 328
, __extension__ __PRETTY_FUNCTION__))
;
329 Inst.addOperand(MCOperand::createReg(Mem.Base));
330 addExpr(Inst, Mem.Disp);
331 Inst.addOperand(MCOperand::createReg(Mem.Length.Reg));
332 }
333 void addBDVAddrOperands(MCInst &Inst, unsigned N) const {
334 assert(N == 3 && "Invalid number of operands")(static_cast <bool> (N == 3 && "Invalid number of operands"
) ? void (0) : __assert_fail ("N == 3 && \"Invalid number of operands\""
, "llvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp", 334
, __extension__ __PRETTY_FUNCTION__))
;
335 assert(isMem(BDVMem) && "Invalid operand type")(static_cast <bool> (isMem(BDVMem) && "Invalid operand type"
) ? void (0) : __assert_fail ("isMem(BDVMem) && \"Invalid operand type\""
, "llvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp", 335
, __extension__ __PRETTY_FUNCTION__))
;
336 Inst.addOperand(MCOperand::createReg(Mem.Base));
337 addExpr(Inst, Mem.Disp);
338 Inst.addOperand(MCOperand::createReg(Mem.Index));
339 }
340 void addImmTLSOperands(MCInst &Inst, unsigned N) const {
341 assert(N == 2 && "Invalid number of operands")(static_cast <bool> (N == 2 && "Invalid number of operands"
) ? void (0) : __assert_fail ("N == 2 && \"Invalid number of operands\""
, "llvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp", 341
, __extension__ __PRETTY_FUNCTION__))
;
342 assert(Kind == KindImmTLS && "Invalid operand type")(static_cast <bool> (Kind == KindImmTLS && "Invalid operand type"
) ? void (0) : __assert_fail ("Kind == KindImmTLS && \"Invalid operand type\""
, "llvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp", 342
, __extension__ __PRETTY_FUNCTION__))
;
343 addExpr(Inst, ImmTLS.Imm);
344 if (ImmTLS.Sym)
345 addExpr(Inst, ImmTLS.Sym);
346 }
347
348 // Used by the TableGen code to check for particular operand types.
349 bool isGR32() const { return isReg(GR32Reg); }
350 bool isGRH32() const { return isReg(GRH32Reg); }
351 bool isGRX32() const { return false; }
352 bool isGR64() const { return isReg(GR64Reg); }
353 bool isGR128() const { return isReg(GR128Reg); }
354 bool isADDR32() const { return isReg(GR32Reg); }
355 bool isADDR64() const { return isReg(GR64Reg); }
356 bool isADDR128() const { return false; }
357 bool isFP32() const { return isReg(FP32Reg); }
358 bool isFP64() const { return isReg(FP64Reg); }
359 bool isFP128() const { return isReg(FP128Reg); }
360 bool isVR32() const { return isReg(VR32Reg); }
361 bool isVR64() const { return isReg(VR64Reg); }
362 bool isVF128() const { return false; }
363 bool isVR128() const { return isReg(VR128Reg); }
364 bool isAR32() const { return isReg(AR32Reg); }
365 bool isCR64() const { return isReg(CR64Reg); }
366 bool isAnyReg() const { return (isReg() || isImm(0, 15)); }
367 bool isBDAddr32Disp12() const { return isMemDisp12(BDMem, GR32Reg); }
368 bool isBDAddr32Disp20() const { return isMemDisp20(BDMem, GR32Reg); }
369 bool isBDAddr64Disp12() const { return isMemDisp12(BDMem, GR64Reg); }
370 bool isBDAddr64Disp20() const { return isMemDisp20(BDMem, GR64Reg); }
371 bool isBDXAddr64Disp12() const { return isMemDisp12(BDXMem, GR64Reg); }
372 bool isBDXAddr64Disp20() const { return isMemDisp20(BDXMem, GR64Reg); }
373 bool isBDLAddr64Disp12Len4() const { return isMemDisp12Len4(GR64Reg); }
374 bool isBDLAddr64Disp12Len8() const { return isMemDisp12Len8(GR64Reg); }
375 bool isBDRAddr64Disp12() const { return isMemDisp12(BDRMem, GR64Reg); }
376 bool isBDVAddr64Disp12() const { return isMemDisp12(BDVMem, GR64Reg); }
377 bool isU1Imm() const { return isImm(0, 1); }
378 bool isU2Imm() const { return isImm(0, 3); }
379 bool isU3Imm() const { return isImm(0, 7); }
380 bool isU4Imm() const { return isImm(0, 15); }
381 bool isU6Imm() const { return isImm(0, 63); }
382 bool isU8Imm() const { return isImm(0, 255); }
383 bool isS8Imm() const { return isImm(-128, 127); }
384 bool isU12Imm() const { return isImm(0, 4095); }
385 bool isU16Imm() const { return isImm(0, 65535); }
386 bool isS16Imm() const { return isImm(-32768, 32767); }
387 bool isU32Imm() const { return isImm(0, (1LL << 32) - 1); }
388 bool isS32Imm() const { return isImm(-(1LL << 31), (1LL << 31) - 1); }
389 bool isU48Imm() const { return isImm(0, (1LL << 48) - 1); }
390};
391
392class SystemZAsmParser : public MCTargetAsmParser {
393#define GET_ASSEMBLER_HEADER
394#include "SystemZGenAsmMatcher.inc"
395
396private:
397 MCAsmParser &Parser;
398 enum RegisterGroup {
399 RegGR,
400 RegFP,
401 RegV,
402 RegAR,
403 RegCR
404 };
405 struct Register {
406 RegisterGroup Group;
407 unsigned Num;
408 SMLoc StartLoc, EndLoc;
409 };
410
411 SystemZTargetStreamer &getTargetStreamer() {
412 assert(getParser().getStreamer().getTargetStreamer() &&(static_cast <bool> (getParser().getStreamer().getTargetStreamer
() && "do not have a target streamer") ? void (0) : __assert_fail
("getParser().getStreamer().getTargetStreamer() && \"do not have a target streamer\""
, "llvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp", 413
, __extension__ __PRETTY_FUNCTION__))
413 "do not have a target streamer")(static_cast <bool> (getParser().getStreamer().getTargetStreamer
() && "do not have a target streamer") ? void (0) : __assert_fail
("getParser().getStreamer().getTargetStreamer() && \"do not have a target streamer\""
, "llvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp", 413
, __extension__ __PRETTY_FUNCTION__))
;
414 MCTargetStreamer &TS = *getParser().getStreamer().getTargetStreamer();
415 return static_cast<SystemZTargetStreamer &>(TS);
416 }
417
418 bool parseRegister(Register &Reg, bool RestoreOnFailure = false);
419
420 bool parseIntegerRegister(Register &Reg, RegisterGroup Group);
421
422 OperandMatchResultTy parseRegister(OperandVector &Operands,
423 RegisterKind Kind);
424
425 OperandMatchResultTy parseAnyRegister(OperandVector &Operands);
426
427 bool parseAddress(bool &HaveReg1, Register &Reg1, bool &HaveReg2,
428 Register &Reg2, const MCExpr *&Disp, const MCExpr *&Length,
429 bool HasLength = false, bool HasVectorIndex = false);
430 bool parseAddressRegister(Register &Reg);
431
432 bool ParseDirectiveInsn(SMLoc L);
433 bool ParseDirectiveMachine(SMLoc L);
434
435 OperandMatchResultTy parseAddress(OperandVector &Operands,
436 MemoryKind MemKind,
437 RegisterKind RegKind);
438
439 OperandMatchResultTy parsePCRel(OperandVector &Operands, int64_t MinVal,
440 int64_t MaxVal, bool AllowTLS);
441
442 bool parseOperand(OperandVector &Operands, StringRef Mnemonic);
443
444 // Both the hlasm and att variants still rely on the basic gnu asm
445 // format with respect to inputs, clobbers, outputs etc.
446 //
447 // However, calling the overriden getAssemblerDialect() method in
448 // AsmParser is problematic. It either returns the AssemblerDialect field
449 // in the MCAsmInfo instance if the AssemblerDialect field in AsmParser is
450 // unset, otherwise it returns the private AssemblerDialect field in
451 // AsmParser.
452 //
453 // The problematic part is because, we forcibly set the inline asm dialect
454 // in the AsmParser instance in AsmPrinterInlineAsm.cpp. Soo any query
455 // to the overriden getAssemblerDialect function in AsmParser.cpp, will
456 // not return the assembler dialect set in the respective MCAsmInfo instance.
457 //
458 // For this purpose, we explicitly query the SystemZMCAsmInfo instance
459 // here, to get the "correct" assembler dialect, and use it in various
460 // functions.
461 unsigned getMAIAssemblerDialect() {
462 return Parser.getContext().getAsmInfo()->getAssemblerDialect();
463 }
464
465 // An alphabetic character in HLASM is a letter from 'A' through 'Z',
466 // or from 'a' through 'z', or '$', '_','#', or '@'.
467 inline bool isHLASMAlpha(char C) {
468 return isAlpha(C) || llvm::is_contained("_@#$", C);
469 }
470
471 // A digit in HLASM is a number from 0 to 9.
472 inline bool isHLASMAlnum(char C) { return isHLASMAlpha(C) || isDigit(C); }
473
474 // Are we parsing using the AD_HLASM dialect?
475 inline bool isParsingHLASM() { return getMAIAssemblerDialect() == AD_HLASM; }
476
477 // Are we parsing using the AD_ATT dialect?
478 inline bool isParsingATT() { return getMAIAssemblerDialect() == AD_ATT; }
479
480public:
481 SystemZAsmParser(const MCSubtargetInfo &sti, MCAsmParser &parser,
482 const MCInstrInfo &MII,
483 const MCTargetOptions &Options)
484 : MCTargetAsmParser(Options, sti, MII), Parser(parser) {
485 MCAsmParserExtension::Initialize(Parser);
486
487 // Alias the .word directive to .short.
488 parser.addAliasForDirective(".word", ".short");
489
490 // Initialize the set of available features.
491 setAvailableFeatures(ComputeAvailableFeatures(getSTI().getFeatureBits()));
492 }
493
494 // Override MCTargetAsmParser.
495 bool ParseDirective(AsmToken DirectiveID) override;
496 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
497 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc,
498 bool RestoreOnFailure);
499 OperandMatchResultTy tryParseRegister(unsigned &RegNo, SMLoc &StartLoc,
500 SMLoc &EndLoc) override;
501 bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
502 SMLoc NameLoc, OperandVector &Operands) override;
503 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
504 OperandVector &Operands, MCStreamer &Out,
505 uint64_t &ErrorInfo,
506 bool MatchingInlineAsm) override;
507 bool isLabel(AsmToken &Token) override;
508
509 // Used by the TableGen code to parse particular operand types.
510 OperandMatchResultTy parseGR32(OperandVector &Operands) {
511 return parseRegister(Operands, GR32Reg);
512 }
513 OperandMatchResultTy parseGRH32(OperandVector &Operands) {
514 return parseRegister(Operands, GRH32Reg);
515 }
516 OperandMatchResultTy parseGRX32(OperandVector &Operands) {
517 llvm_unreachable("GRX32 should only be used for pseudo instructions")::llvm::llvm_unreachable_internal("GRX32 should only be used for pseudo instructions"
, "llvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp", 517
)
;
518 }
519 OperandMatchResultTy parseGR64(OperandVector &Operands) {
520 return parseRegister(Operands, GR64Reg);
521 }
522 OperandMatchResultTy parseGR128(OperandVector &Operands) {
523 return parseRegister(Operands, GR128Reg);
524 }
525 OperandMatchResultTy parseADDR32(OperandVector &Operands) {
526 // For the AsmParser, we will accept %r0 for ADDR32 as well.
527 return parseRegister(Operands, GR32Reg);
528 }
529 OperandMatchResultTy parseADDR64(OperandVector &Operands) {
530 // For the AsmParser, we will accept %r0 for ADDR64 as well.
531 return parseRegister(Operands, GR64Reg);
532 }
533 OperandMatchResultTy parseADDR128(OperandVector &Operands) {
534 llvm_unreachable("Shouldn't be used as an operand")::llvm::llvm_unreachable_internal("Shouldn't be used as an operand"
, "llvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp", 534
)
;
535 }
536 OperandMatchResultTy parseFP32(OperandVector &Operands) {
537 return parseRegister(Operands, FP32Reg);
538 }
539 OperandMatchResultTy parseFP64(OperandVector &Operands) {
540 return parseRegister(Operands, FP64Reg);
541 }
542 OperandMatchResultTy parseFP128(OperandVector &Operands) {
543 return parseRegister(Operands, FP128Reg);
544 }
545 OperandMatchResultTy parseVR32(OperandVector &Operands) {
546 return parseRegister(Operands, VR32Reg);
547 }
548 OperandMatchResultTy parseVR64(OperandVector &Operands) {
549 return parseRegister(Operands, VR64Reg);
550 }
551 OperandMatchResultTy parseVF128(OperandVector &Operands) {
552 llvm_unreachable("Shouldn't be used as an operand")::llvm::llvm_unreachable_internal("Shouldn't be used as an operand"
, "llvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp", 552
)
;
553 }
554 OperandMatchResultTy parseVR128(OperandVector &Operands) {
555 return parseRegister(Operands, VR128Reg);
556 }
557 OperandMatchResultTy parseAR32(OperandVector &Operands) {
558 return parseRegister(Operands, AR32Reg);
559 }
560 OperandMatchResultTy parseCR64(OperandVector &Operands) {
561 return parseRegister(Operands, CR64Reg);
562 }
563 OperandMatchResultTy parseAnyReg(OperandVector &Operands) {
564 return parseAnyRegister(Operands);
565 }
566 OperandMatchResultTy parseBDAddr32(OperandVector &Operands) {
567 return parseAddress(Operands, BDMem, GR32Reg);
568 }
569 OperandMatchResultTy parseBDAddr64(OperandVector &Operands) {
570 return parseAddress(Operands, BDMem, GR64Reg);
571 }
572 OperandMatchResultTy parseBDXAddr64(OperandVector &Operands) {
573 return parseAddress(Operands, BDXMem, GR64Reg);
20
Calling 'SystemZAsmParser::parseAddress'
574 }
575 OperandMatchResultTy parseBDLAddr64(OperandVector &Operands) {
576 return parseAddress(Operands, BDLMem, GR64Reg);
577 }
578 OperandMatchResultTy parseBDRAddr64(OperandVector &Operands) {
579 return parseAddress(Operands, BDRMem, GR64Reg);
580 }
581 OperandMatchResultTy parseBDVAddr64(OperandVector &Operands) {
582 return parseAddress(Operands, BDVMem, GR64Reg);
583 }
584 OperandMatchResultTy parsePCRel12(OperandVector &Operands) {
585 return parsePCRel(Operands, -(1LL << 12), (1LL << 12) - 1, false);
586 }
587 OperandMatchResultTy parsePCRel16(OperandVector &Operands) {
588 return parsePCRel(Operands, -(1LL << 16), (1LL << 16) - 1, false);
589 }
590 OperandMatchResultTy parsePCRel24(OperandVector &Operands) {
591 return parsePCRel(Operands, -(1LL << 24), (1LL << 24) - 1, false);
592 }
593 OperandMatchResultTy parsePCRel32(OperandVector &Operands) {
594 return parsePCRel(Operands, -(1LL << 32), (1LL << 32) - 1, false);
595 }
596 OperandMatchResultTy parsePCRelTLS16(OperandVector &Operands) {
597 return parsePCRel(Operands, -(1LL << 16), (1LL << 16) - 1, true);
598 }
599 OperandMatchResultTy parsePCRelTLS32(OperandVector &Operands) {
600 return parsePCRel(Operands, -(1LL << 32), (1LL << 32) - 1, true);
601 }
602};
603
604} // end anonymous namespace
605
606#define GET_REGISTER_MATCHER
607#define GET_SUBTARGET_FEATURE_NAME
608#define GET_MATCHER_IMPLEMENTATION
609#define GET_MNEMONIC_SPELL_CHECKER
610#include "SystemZGenAsmMatcher.inc"
611
612// Used for the .insn directives; contains information needed to parse the
613// operands in the directive.
614struct InsnMatchEntry {
615 StringRef Format;
616 uint64_t Opcode;
617 int32_t NumOperands;
618 MatchClassKind OperandKinds[7];
619};
620
621// For equal_range comparison.
622struct CompareInsn {
623 bool operator() (const InsnMatchEntry &LHS, StringRef RHS) {
624 return LHS.Format < RHS;
625 }
626 bool operator() (StringRef LHS, const InsnMatchEntry &RHS) {
627 return LHS < RHS.Format;
628 }
629 bool operator() (const InsnMatchEntry &LHS, const InsnMatchEntry &RHS) {
630 return LHS.Format < RHS.Format;
631 }
632};
633
634// Table initializing information for parsing the .insn directive.
635static struct InsnMatchEntry InsnMatchTable[] = {
636 /* Format, Opcode, NumOperands, OperandKinds */
637 { "e", SystemZ::InsnE, 1,
638 { MCK_U16Imm } },
639 { "ri", SystemZ::InsnRI, 3,
640 { MCK_U32Imm, MCK_AnyReg, MCK_S16Imm } },
641 { "rie", SystemZ::InsnRIE, 4,
642 { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_PCRel16 } },
643 { "ril", SystemZ::InsnRIL, 3,
644 { MCK_U48Imm, MCK_AnyReg, MCK_PCRel32 } },
645 { "rilu", SystemZ::InsnRILU, 3,
646 { MCK_U48Imm, MCK_AnyReg, MCK_U32Imm } },
647 { "ris", SystemZ::InsnRIS, 5,
648 { MCK_U48Imm, MCK_AnyReg, MCK_S8Imm, MCK_U4Imm, MCK_BDAddr64Disp12 } },
649 { "rr", SystemZ::InsnRR, 3,
650 { MCK_U16Imm, MCK_AnyReg, MCK_AnyReg } },
651 { "rre", SystemZ::InsnRRE, 3,
652 { MCK_U32Imm, MCK_AnyReg, MCK_AnyReg } },
653 { "rrf", SystemZ::InsnRRF, 5,
654 { MCK_U32Imm, MCK_AnyReg, MCK_AnyReg, MCK_AnyReg, MCK_U4Imm } },
655 { "rrs", SystemZ::InsnRRS, 5,
656 { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_U4Imm, MCK_BDAddr64Disp12 } },
657 { "rs", SystemZ::InsnRS, 4,
658 { MCK_U32Imm, MCK_AnyReg, MCK_AnyReg, MCK_BDAddr64Disp12 } },
659 { "rse", SystemZ::InsnRSE, 4,
660 { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_BDAddr64Disp12 } },
661 { "rsi", SystemZ::InsnRSI, 4,
662 { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_PCRel16 } },
663 { "rsy", SystemZ::InsnRSY, 4,
664 { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_BDAddr64Disp20 } },
665 { "rx", SystemZ::InsnRX, 3,
666 { MCK_U32Imm, MCK_AnyReg, MCK_BDXAddr64Disp12 } },
667 { "rxe", SystemZ::InsnRXE, 3,
668 { MCK_U48Imm, MCK_AnyReg, MCK_BDXAddr64Disp12 } },
669 { "rxf", SystemZ::InsnRXF, 4,
670 { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_BDXAddr64Disp12 } },
671 { "rxy", SystemZ::InsnRXY, 3,
672 { MCK_U48Imm, MCK_AnyReg, MCK_BDXAddr64Disp20 } },
673 { "s", SystemZ::InsnS, 2,
674 { MCK_U32Imm, MCK_BDAddr64Disp12 } },
675 { "si", SystemZ::InsnSI, 3,
676 { MCK_U32Imm, MCK_BDAddr64Disp12, MCK_S8Imm } },
677 { "sil", SystemZ::InsnSIL, 3,
678 { MCK_U48Imm, MCK_BDAddr64Disp12, MCK_U16Imm } },
679 { "siy", SystemZ::InsnSIY, 3,
680 { MCK_U48Imm, MCK_BDAddr64Disp20, MCK_U8Imm } },
681 { "ss", SystemZ::InsnSS, 4,
682 { MCK_U48Imm, MCK_BDXAddr64Disp12, MCK_BDAddr64Disp12, MCK_AnyReg } },
683 { "sse", SystemZ::InsnSSE, 3,
684 { MCK_U48Imm, MCK_BDAddr64Disp12, MCK_BDAddr64Disp12 } },
685 { "ssf", SystemZ::InsnSSF, 4,
686 { MCK_U48Imm, MCK_BDAddr64Disp12, MCK_BDAddr64Disp12, MCK_AnyReg } },
687 { "vri", SystemZ::InsnVRI, 6,
688 { MCK_U48Imm, MCK_VR128, MCK_VR128, MCK_U12Imm, MCK_U4Imm, MCK_U4Imm } },
689 { "vrr", SystemZ::InsnVRR, 7,
690 { MCK_U48Imm, MCK_VR128, MCK_VR128, MCK_VR128, MCK_U4Imm, MCK_U4Imm,
691 MCK_U4Imm } },
692 { "vrs", SystemZ::InsnVRS, 5,
693 { MCK_U48Imm, MCK_AnyReg, MCK_VR128, MCK_BDAddr64Disp12, MCK_U4Imm } },
694 { "vrv", SystemZ::InsnVRV, 4,
695 { MCK_U48Imm, MCK_VR128, MCK_BDVAddr64Disp12, MCK_U4Imm } },
696 { "vrx", SystemZ::InsnVRX, 4,
697 { MCK_U48Imm, MCK_VR128, MCK_BDXAddr64Disp12, MCK_U4Imm } },
698 { "vsi", SystemZ::InsnVSI, 4,
699 { MCK_U48Imm, MCK_VR128, MCK_BDAddr64Disp12, MCK_U8Imm } }
700};
701
702static void printMCExpr(const MCExpr *E, raw_ostream &OS) {
703 if (!E)
704 return;
705 if (auto *CE = dyn_cast<MCConstantExpr>(E))
706 OS << *CE;
707 else if (auto *UE = dyn_cast<MCUnaryExpr>(E))
708 OS << *UE;
709 else if (auto *BE = dyn_cast<MCBinaryExpr>(E))
710 OS << *BE;
711 else if (auto *SRE = dyn_cast<MCSymbolRefExpr>(E))
712 OS << *SRE;
713 else
714 OS << *E;
715}
716
717void SystemZOperand::print(raw_ostream &OS) const {
718 switch (Kind) {
719 case KindToken:
720 OS << "Token:" << getToken();
721 break;
722 case KindReg:
723 OS << "Reg:" << SystemZInstPrinter::getRegisterName(getReg());
724 break;
725 case KindImm:
726 OS << "Imm:";
727 printMCExpr(getImm(), OS);
728 break;
729 case KindImmTLS:
730 OS << "ImmTLS:";
731 printMCExpr(getImmTLS().Imm, OS);
732 if (getImmTLS().Sym) {
733 OS << ", ";
734 printMCExpr(getImmTLS().Sym, OS);
735 }
736 break;
737 case KindMem: {
738 const MemOp &Op = getMem();
739 OS << "Mem:" << *cast<MCConstantExpr>(Op.Disp);
740 if (Op.Base) {
741 OS << "(";
742 if (Op.MemKind == BDLMem)
743 OS << *cast<MCConstantExpr>(Op.Length.Imm) << ",";
744 else if (Op.MemKind == BDRMem)
745 OS << SystemZInstPrinter::getRegisterName(Op.Length.Reg) << ",";
746 if (Op.Index)
747 OS << SystemZInstPrinter::getRegisterName(Op.Index) << ",";
748 OS << SystemZInstPrinter::getRegisterName(Op.Base);
749 OS << ")";
750 }
751 break;
752 }
753 case KindInvalid:
754 break;
755 }
756}
757
758// Parse one register of the form %<prefix><number>.
759bool SystemZAsmParser::parseRegister(Register &Reg, bool RestoreOnFailure) {
760 Reg.StartLoc = Parser.getTok().getLoc();
761
762 // Eat the % prefix.
763 if (Parser.getTok().isNot(AsmToken::Percent))
764 return Error(Parser.getTok().getLoc(), "register expected");
765 const AsmToken &PercentTok = Parser.getTok();
766 Parser.Lex();
767
768 // Expect a register name.
769 if (Parser.getTok().isNot(AsmToken::Identifier)) {
770 if (RestoreOnFailure)
771 getLexer().UnLex(PercentTok);
772 return Error(Reg.StartLoc, "invalid register");
773 }
774
775 // Check that there's a prefix.
776 StringRef Name = Parser.getTok().getString();
777 if (Name.size() < 2) {
778 if (RestoreOnFailure)
779 getLexer().UnLex(PercentTok);
780 return Error(Reg.StartLoc, "invalid register");
781 }
782 char Prefix = Name[0];
783
784 // Treat the rest of the register name as a register number.
785 if (Name.substr(1).getAsInteger(10, Reg.Num)) {
786 if (RestoreOnFailure)
787 getLexer().UnLex(PercentTok);
788 return Error(Reg.StartLoc, "invalid register");
789 }
790
791 // Look for valid combinations of prefix and number.
792 if (Prefix == 'r' && Reg.Num < 16)
793 Reg.Group = RegGR;
794 else if (Prefix == 'f' && Reg.Num < 16)
795 Reg.Group = RegFP;
796 else if (Prefix == 'v' && Reg.Num < 32)
797 Reg.Group = RegV;
798 else if (Prefix == 'a' && Reg.Num < 16)
799 Reg.Group = RegAR;
800 else if (Prefix == 'c' && Reg.Num < 16)
801 Reg.Group = RegCR;
802 else {
803 if (RestoreOnFailure)
804 getLexer().UnLex(PercentTok);
805 return Error(Reg.StartLoc, "invalid register");
806 }
807
808 Reg.EndLoc = Parser.getTok().getLoc();
809 Parser.Lex();
810 return false;
811}
812
813// Parse a register of kind Kind and add it to Operands.
814OperandMatchResultTy
815SystemZAsmParser::parseRegister(OperandVector &Operands, RegisterKind Kind) {
816 Register Reg;
817 RegisterGroup Group;
818 switch (Kind) {
819 case GR32Reg:
820 case GRH32Reg:
821 case GR64Reg:
822 case GR128Reg:
823 Group = RegGR;
824 break;
825 case FP32Reg:
826 case FP64Reg:
827 case FP128Reg:
828 Group = RegFP;
829 break;
830 case VR32Reg:
831 case VR64Reg:
832 case VR128Reg:
833 Group = RegV;
834 break;
835 case AR32Reg:
836 Group = RegAR;
837 break;
838 case CR64Reg:
839 Group = RegCR;
840 break;
841 }
842
843 // Handle register names of the form %<prefix><number>
844 if (isParsingATT() && Parser.getTok().is(AsmToken::Percent)) {
845 if (parseRegister(Reg))
846 return MatchOperand_ParseFail;
847
848 // Check the parsed register group "Reg.Group" with the expected "Group"
849 // Have to error out if user specified wrong prefix.
850 switch (Group) {
851 case RegGR:
852 case RegFP:
853 case RegAR:
854 case RegCR:
855 if (Group != Reg.Group) {
856 Error(Reg.StartLoc, "invalid operand for instruction");
857 return MatchOperand_ParseFail;
858 }
859 break;
860 case RegV:
861 if (Reg.Group != RegV && Reg.Group != RegFP) {
862 Error(Reg.StartLoc, "invalid operand for instruction");
863 return MatchOperand_ParseFail;
864 }
865 break;
866 }
867 } else if (Parser.getTok().is(AsmToken::Integer)) {
868 if (parseIntegerRegister(Reg, Group))
869 return MatchOperand_ParseFail;
870 }
871 // Otherwise we didn't match a register operand.
872 else
873 return MatchOperand_NoMatch;
874
875 // Determine the LLVM register number according to Kind.
876 const unsigned *Regs;
877 switch (Kind) {
878 case GR32Reg: Regs = SystemZMC::GR32Regs; break;
879 case GRH32Reg: Regs = SystemZMC::GRH32Regs; break;
880 case GR64Reg: Regs = SystemZMC::GR64Regs; break;
881 case GR128Reg: Regs = SystemZMC::GR128Regs; break;
882 case FP32Reg: Regs = SystemZMC::FP32Regs; break;
883 case FP64Reg: Regs = SystemZMC::FP64Regs; break;
884 case FP128Reg: Regs = SystemZMC::FP128Regs; break;
885 case VR32Reg: Regs = SystemZMC::VR32Regs; break;
886 case VR64Reg: Regs = SystemZMC::VR64Regs; break;
887 case VR128Reg: Regs = SystemZMC::VR128Regs; break;
888 case AR32Reg: Regs = SystemZMC::AR32Regs; break;
889 case CR64Reg: Regs = SystemZMC::CR64Regs; break;
890 }
891 if (Regs[Reg.Num] == 0) {
892 Error(Reg.StartLoc, "invalid register pair");
893 return MatchOperand_ParseFail;
894 }
895
896 Operands.push_back(
897 SystemZOperand::createReg(Kind, Regs[Reg.Num], Reg.StartLoc, Reg.EndLoc));
898 return MatchOperand_Success;
899}
900
901// Parse any type of register (including integers) and add it to Operands.
902OperandMatchResultTy
903SystemZAsmParser::parseAnyRegister(OperandVector &Operands) {
904 SMLoc StartLoc = Parser.getTok().getLoc();
905
906 // Handle integer values.
907 if (Parser.getTok().is(AsmToken::Integer)) {
908 const MCExpr *Register;
909 if (Parser.parseExpression(Register))
910 return MatchOperand_ParseFail;
911
912 if (auto *CE = dyn_cast<MCConstantExpr>(Register)) {
913 int64_t Value = CE->getValue();
914 if (Value < 0 || Value > 15) {
915 Error(StartLoc, "invalid register");
916 return MatchOperand_ParseFail;
917 }
918 }
919
920 SMLoc EndLoc =
921 SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
922
923 Operands.push_back(SystemZOperand::createImm(Register, StartLoc, EndLoc));
924 }
925 else {
926 if (isParsingHLASM())
927 return MatchOperand_NoMatch;
928
929 Register Reg;
930 if (parseRegister(Reg))
931 return MatchOperand_ParseFail;
932
933 if (Reg.Num > 15) {
934 Error(StartLoc, "invalid register");
935 return MatchOperand_ParseFail;
936 }
937
938 // Map to the correct register kind.
939 RegisterKind Kind;
940 unsigned RegNo;
941 if (Reg.Group == RegGR) {
942 Kind = GR64Reg;
943 RegNo = SystemZMC::GR64Regs[Reg.Num];
944 }
945 else if (Reg.Group == RegFP) {
946 Kind = FP64Reg;
947 RegNo = SystemZMC::FP64Regs[Reg.Num];
948 }
949 else if (Reg.Group == RegV) {
950 Kind = VR128Reg;
951 RegNo = SystemZMC::VR128Regs[Reg.Num];
952 }
953 else if (Reg.Group == RegAR) {
954 Kind = AR32Reg;
955 RegNo = SystemZMC::AR32Regs[Reg.Num];
956 }
957 else if (Reg.Group == RegCR) {
958 Kind = CR64Reg;
959 RegNo = SystemZMC::CR64Regs[Reg.Num];
960 }
961 else {
962 return MatchOperand_ParseFail;
963 }
964
965 Operands.push_back(SystemZOperand::createReg(Kind, RegNo,
966 Reg.StartLoc, Reg.EndLoc));
967 }
968 return MatchOperand_Success;
969}
970
971bool SystemZAsmParser::parseIntegerRegister(Register &Reg,
972 RegisterGroup Group) {
973 Reg.StartLoc = Parser.getTok().getLoc();
974 // We have an integer token
975 const MCExpr *Register;
976 if (Parser.parseExpression(Register))
977 return true;
978
979 const auto *CE = dyn_cast<MCConstantExpr>(Register);
980 if (!CE)
981 return true;
982
983 int64_t MaxRegNum = (Group == RegV) ? 31 : 15;
984 int64_t Value = CE->getValue();
985 if (Value < 0 || Value > MaxRegNum) {
986 Error(Parser.getTok().getLoc(), "invalid register");
987 return true;
988 }
989
990 // Assign the Register Number
991 Reg.Num = (unsigned)Value;
992 Reg.Group = Group;
993 Reg.EndLoc = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
994
995 // At this point, successfully parsed an integer register.
996 return false;
997}
998
999// Parse a memory operand into Reg1, Reg2, Disp, and Length.
1000bool SystemZAsmParser::parseAddress(bool &HaveReg1, Register &Reg1,
1001 bool &HaveReg2, Register &Reg2,
1002 const MCExpr *&Disp, const MCExpr *&Length,
1003 bool HasLength, bool HasVectorIndex) {
1004 // Parse the displacement, which must always be present.
1005 if (getParser().parseExpression(Disp))
24
Assuming the condition is false
25
Taking false branch
1006 return true;
1007
1008 // Parse the optional base and index.
1009 HaveReg1 = false;
1010 HaveReg2 = false;
1011 Length = nullptr;
1012
1013 // If we have a scenario as below:
1014 // vgef %v0, 0(0), 0
1015 // This is an example of a "BDVMem" instruction type.
1016 //
1017 // So when we parse this as an integer register, the register group
1018 // needs to be tied to "RegV". Usually when the prefix is passed in
1019 // as %<prefix><reg-number> its easy to check which group it should belong to
1020 // However, if we're passing in just the integer there's no real way to
1021 // "check" what register group it should belong to.
1022 //
1023 // When the user passes in the register as an integer, the user assumes that
1024 // the compiler is responsible for substituting it as the right kind of
1025 // register. Whereas, when the user specifies a "prefix", the onus is on
1026 // the user to make sure they pass in the right kind of register.
1027 //
1028 // The restriction only applies to the first Register (i.e. Reg1). Reg2 is
1029 // always a general register. Reg1 should be of group RegV if "HasVectorIndex"
1030 // (i.e. insn is of type BDVMem) is true.
1031 RegisterGroup RegGroup = HasVectorIndex
25.1
'HasVectorIndex' is false
? RegV : RegGR;
26
'?' condition is false
1032
1033 if (getLexer().is(AsmToken::LParen)) {
27
Taking true branch
1034 Parser.Lex();
1035
1036 if (isParsingATT() && getLexer().is(AsmToken::Percent)) {
1037 // Parse the first register.
1038 HaveReg1 = true;
1039 if (parseRegister(Reg1))
1040 return true;
1041 }
1042 // So if we have an integer as the first token in ([tok1], ..), it could:
1043 // 1. Refer to a "Register" (i.e X,R,V fields in BD[X|R|V]Mem type of
1044 // instructions)
1045 // 2. Refer to a "Length" field (i.e L field in BDLMem type of instructions)
1046 else if (getLexer().is(AsmToken::Integer)) {
28
Taking false branch
1047 if (HasLength) {
1048 // Instruction has a "Length" field, safe to parse the first token as
1049 // the "Length" field
1050 if (getParser().parseExpression(Length))
1051 return true;
1052 } else {
1053 // Otherwise, if the instruction has no "Length" field, parse the
1054 // token as a "Register". We don't have to worry about whether the
1055 // instruction is invalid here, because the caller will take care of
1056 // error reporting.
1057 HaveReg1 = true;
1058 if (parseIntegerRegister(Reg1, RegGroup))
1059 return true;
1060 }
1061 } else {
1062 // If its not an integer or a percent token, then if the instruction
1063 // is reported to have a "Length" then, parse it as "Length".
1064 if (HasLength
28.1
'HasLength' is false
) {
29
Taking false branch
1065 if (getParser().parseExpression(Length))
1066 return true;
1067 }
1068 }
1069
1070 // Check whether there's a second register.
1071 if (getLexer().is(AsmToken::Comma)) {
30
Taking true branch
1072 Parser.Lex();
1073 HaveReg2 = true;
1074
1075 if (getLexer().is(AsmToken::Integer)) {
1076 if (parseIntegerRegister(Reg2, RegGR))
1077 return true;
1078 } else {
1079 if (isParsingATT() && parseRegister(Reg2))
1080 return true;
1081 }
1082 }
1083
1084 // Consume the closing bracket.
1085 if (getLexer().isNot(AsmToken::RParen))
31
Taking false branch
1086 return Error(Parser.getTok().getLoc(), "unexpected token in address");
1087 Parser.Lex();
1088 }
1089 return false;
32
Returning without writing to 'Reg2.Group'
1090}
1091
1092// Verify that Reg is a valid address register (base or index).
1093bool
1094SystemZAsmParser::parseAddressRegister(Register &Reg) {
1095 if (Reg.Group == RegV) {
41
The left operand of '==' is a garbage value
1096 Error(Reg.StartLoc, "invalid use of vector addressing");
1097 return true;
1098 } else if (Reg.Group != RegGR) {
1099 Error(Reg.StartLoc, "invalid address register");
1100 return true;
1101 }
1102 return false;
1103}
1104
1105// Parse a memory operand and add it to Operands. The other arguments
1106// are as above.
1107OperandMatchResultTy
1108SystemZAsmParser::parseAddress(OperandVector &Operands, MemoryKind MemKind,
1109 RegisterKind RegKind) {
1110 SMLoc StartLoc = Parser.getTok().getLoc();
1111 unsigned Base = 0, Index = 0, LengthReg = 0;
1112 Register Reg1, Reg2;
1113 bool HaveReg1, HaveReg2;
1114 const MCExpr *Disp;
1115 const MCExpr *Length;
1116
1117 bool HasLength = (MemKind
20.1
'MemKind' is not equal to BDLMem
== BDLMem) ? true : false;
21
'?' condition is false
1118 bool HasVectorIndex = (MemKind
21.1
'MemKind' is not equal to BDVMem
== BDVMem) ? true : false;
22
'?' condition is false
1119 if (parseAddress(HaveReg1, Reg1, HaveReg2, Reg2, Disp, Length, HasLength,
23
Calling 'SystemZAsmParser::parseAddress'
33
Returning from 'SystemZAsmParser::parseAddress'
34
Taking false branch
1120 HasVectorIndex))
1121 return MatchOperand_ParseFail;
1122
1123 const unsigned *Regs;
1124 switch (RegKind) {
35
Control jumps to 'case GR64Reg:' at line 1126
1125 case GR32Reg: Regs = SystemZMC::GR32Regs; break;
1126 case GR64Reg: Regs = SystemZMC::GR64Regs; break;
1127 default: llvm_unreachable("invalid RegKind")::llvm::llvm_unreachable_internal("invalid RegKind", "llvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp"
, 1127)
;
1128 }
1129
1130 switch (MemKind) {
37
Control jumps to 'case BDXMem:' at line 1144
1131 case BDMem:
1132 // If we have Reg1, it must be an address register.
1133 if (HaveReg1) {
1134 if (parseAddressRegister(Reg1))
1135 return MatchOperand_ParseFail;
1136 Base = Regs[Reg1.Num];
1137 }
1138 // There must be no Reg2.
1139 if (HaveReg2) {
1140 Error(StartLoc, "invalid use of indexed addressing");
1141 return MatchOperand_ParseFail;
1142 }
1143 break;
1144 case BDXMem:
1145 // If we have Reg1, it must be an address register.
1146 if (HaveReg1
37.1
'HaveReg1' is false
) {
36
Execution continues on line 1130
38
Taking false branch
1147 if (parseAddressRegister(Reg1))
1148 return MatchOperand_ParseFail;
1149 // If the are two registers, the first one is the index and the
1150 // second is the base.
1151 if (HaveReg2)
1152 Index = Regs[Reg1.Num];
1153 else
1154 Base = Regs[Reg1.Num];
1155 }
1156 // If we have Reg2, it must be an address register.
1157 if (HaveReg2
38.1
'HaveReg2' is true
) {
39
Taking true branch
1158 if (parseAddressRegister(Reg2))
40
Calling 'SystemZAsmParser::parseAddressRegister'
1159 return MatchOperand_ParseFail;
1160 Base = Regs[Reg2.Num];
1161 }
1162 break;
1163 case BDLMem:
1164 // If we have Reg2, it must be an address register.
1165 if (HaveReg2) {
1166 if (parseAddressRegister(Reg2))
1167 return MatchOperand_ParseFail;
1168 Base = Regs[Reg2.Num];
1169 }
1170 // We cannot support base+index addressing.
1171 if (HaveReg1 && HaveReg2) {
1172 Error(StartLoc, "invalid use of indexed addressing");
1173 return MatchOperand_ParseFail;
1174 }
1175 // We must have a length.
1176 if (!Length) {
1177 Error(StartLoc, "missing length in address");
1178 return MatchOperand_ParseFail;
1179 }
1180 break;
1181 case BDRMem:
1182 // We must have Reg1, and it must be a GPR.
1183 if (!HaveReg1 || Reg1.Group != RegGR) {
1184 Error(StartLoc, "invalid operand for instruction");
1185 return MatchOperand_ParseFail;
1186 }
1187 LengthReg = SystemZMC::GR64Regs[Reg1.Num];
1188 // If we have Reg2, it must be an address register.
1189 if (HaveReg2) {
1190 if (parseAddressRegister(Reg2))
1191 return MatchOperand_ParseFail;
1192 Base = Regs[Reg2.Num];
1193 }
1194 break;
1195 case BDVMem:
1196 // We must have Reg1, and it must be a vector register.
1197 if (!HaveReg1 || Reg1.Group != RegV) {
1198 Error(StartLoc, "vector index required in address");
1199 return MatchOperand_ParseFail;
1200 }
1201 Index = SystemZMC::VR128Regs[Reg1.Num];
1202 // If we have Reg2, it must be an address register.
1203 if (HaveReg2) {
1204 if (parseAddressRegister(Reg2))
1205 return MatchOperand_ParseFail;
1206 Base = Regs[Reg2.Num];
1207 }
1208 break;
1209 }
1210
1211 SMLoc EndLoc =
1212 SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1213 Operands.push_back(SystemZOperand::createMem(MemKind, RegKind, Base, Disp,
1214 Index, Length, LengthReg,
1215 StartLoc, EndLoc));
1216 return MatchOperand_Success;
1217}
1218
1219bool SystemZAsmParser::ParseDirective(AsmToken DirectiveID) {
1220 StringRef IDVal = DirectiveID.getIdentifier();
1221
1222 if (IDVal == ".insn")
1
Assuming the condition is true
2
Taking true branch
1223 return ParseDirectiveInsn(DirectiveID.getLoc());
3
Calling 'SystemZAsmParser::ParseDirectiveInsn'
1224 if (IDVal == ".machine")
1225 return ParseDirectiveMachine(DirectiveID.getLoc());
1226
1227 return true;
1228}
1229
1230/// ParseDirectiveInsn
1231/// ::= .insn [ format, encoding, (operands (, operands)*) ]
1232bool SystemZAsmParser::ParseDirectiveInsn(SMLoc L) {
1233 MCAsmParser &Parser = getParser();
1234
1235 // Expect instruction format as identifier.
1236 StringRef Format;
1237 SMLoc ErrorLoc = Parser.getTok().getLoc();
1238 if (Parser.parseIdentifier(Format))
4
Assuming the condition is false
5
Taking false branch
1239 return Error(ErrorLoc, "expected instruction format");
1240
1241 SmallVector<std::unique_ptr<MCParsedAsmOperand>, 8> Operands;
1242
1243 // Find entry for this format in InsnMatchTable.
1244 auto EntryRange =
1245 std::equal_range(std::begin(InsnMatchTable), std::end(InsnMatchTable),
1246 Format, CompareInsn());
1247
1248 // If first == second, couldn't find a match in the table.
1249 if (EntryRange.first == EntryRange.second)
6
Assuming field 'first' is not equal to field 'second'
7
Taking false branch
1250 return Error(ErrorLoc, "unrecognized format");
1251
1252 struct InsnMatchEntry *Entry = EntryRange.first;
1253
1254 // Format should match from equal_range.
1255 assert(Entry->Format == Format)(static_cast <bool> (Entry->Format == Format) ? void
(0) : __assert_fail ("Entry->Format == Format", "llvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp"
, 1255, __extension__ __PRETTY_FUNCTION__))
;
8
Assuming the condition is true
9
'?' condition is true
1256
1257 // Parse the following operands using the table's information.
1258 for (int i = 0; i < Entry->NumOperands; i++) {
10
Assuming 'i' is < field 'NumOperands'
11
Loop condition is true. Entering loop body
1259 MatchClassKind Kind = Entry->OperandKinds[i];
1260
1261 SMLoc StartLoc = Parser.getTok().getLoc();
1262
1263 // Always expect commas as separators for operands.
1264 if (getLexer().isNot(AsmToken::Comma))
12
Taking false branch
1265 return Error(StartLoc, "unexpected token in directive");
1266 Lex();
1267
1268 // Parse operands.
1269 OperandMatchResultTy ResTy;
1270 if (Kind == MCK_AnyReg)
13
Assuming 'Kind' is not equal to MCK_AnyReg
14
Taking false branch
1271 ResTy = parseAnyReg(Operands);
1272 else if (Kind == MCK_VR128)
15
Assuming 'Kind' is not equal to MCK_VR128
1273 ResTy = parseVR128(Operands);
1274 else if (Kind == MCK_BDXAddr64Disp12 || Kind == MCK_BDXAddr64Disp20)
16
Assuming 'Kind' is not equal to MCK_BDXAddr64Disp12
17
Assuming 'Kind' is equal to MCK_BDXAddr64Disp20
18
Taking true branch
1275 ResTy = parseBDXAddr64(Operands);
19
Calling 'SystemZAsmParser::parseBDXAddr64'
1276 else if (Kind == MCK_BDAddr64Disp12 || Kind == MCK_BDAddr64Disp20)
1277 ResTy = parseBDAddr64(Operands);
1278 else if (Kind == MCK_BDVAddr64Disp12)
1279 ResTy = parseBDVAddr64(Operands);
1280 else if (Kind == MCK_PCRel32)
1281 ResTy = parsePCRel32(Operands);
1282 else if (Kind == MCK_PCRel16)
1283 ResTy = parsePCRel16(Operands);
1284 else {
1285 // Only remaining operand kind is an immediate.
1286 const MCExpr *Expr;
1287 SMLoc StartLoc = Parser.getTok().getLoc();
1288
1289 // Expect immediate expression.
1290 if (Parser.parseExpression(Expr))
1291 return Error(StartLoc, "unexpected token in directive");
1292
1293 SMLoc EndLoc =
1294 SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1295
1296 Operands.push_back(SystemZOperand::createImm(Expr, StartLoc, EndLoc));
1297 ResTy = MatchOperand_Success;
1298 }
1299
1300 if (ResTy != MatchOperand_Success)
1301 return true;
1302 }
1303
1304 // Build the instruction with the parsed operands.
1305 MCInst Inst = MCInstBuilder(Entry->Opcode);
1306
1307 for (size_t i = 0; i < Operands.size(); i++) {
1308 MCParsedAsmOperand &Operand = *Operands[i];
1309 MatchClassKind Kind = Entry->OperandKinds[i];
1310
1311 // Verify operand.
1312 unsigned Res = validateOperandClass(Operand, Kind);
1313 if (Res != Match_Success)
1314 return Error(Operand.getStartLoc(), "unexpected operand type");
1315
1316 // Add operands to instruction.
1317 SystemZOperand &ZOperand = static_cast<SystemZOperand &>(Operand);
1318 if (ZOperand.isReg())
1319 ZOperand.addRegOperands(Inst, 1);
1320 else if (ZOperand.isMem(BDMem))
1321 ZOperand.addBDAddrOperands(Inst, 2);
1322 else if (ZOperand.isMem(BDXMem))
1323 ZOperand.addBDXAddrOperands(Inst, 3);
1324 else if (ZOperand.isMem(BDVMem))
1325 ZOperand.addBDVAddrOperands(Inst, 3);
1326 else if (ZOperand.isImm())
1327 ZOperand.addImmOperands(Inst, 1);
1328 else
1329 llvm_unreachable("unexpected operand type")::llvm::llvm_unreachable_internal("unexpected operand type", "llvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp"
, 1329)
;
1330 }
1331
1332 // Emit as a regular instruction.
1333 Parser.getStreamer().emitInstruction(Inst, getSTI());
1334
1335 return false;
1336}
1337
1338/// ParseDirectiveMachine
1339/// ::= .machine [ mcpu ]
1340bool SystemZAsmParser::ParseDirectiveMachine(SMLoc L) {
1341 MCAsmParser &Parser = getParser();
1342 if (Parser.getTok().isNot(AsmToken::Identifier) &&
1343 Parser.getTok().isNot(AsmToken::String))
1344 return Error(L, "unexpected token in '.machine' directive");
1345
1346 StringRef CPU = Parser.getTok().getIdentifier();
1347 Parser.Lex();
1348 if (parseToken(AsmToken::EndOfStatement))
1349 return addErrorSuffix(" in '.machine' directive");
1350
1351 MCSubtargetInfo &STI = copySTI();
1352 STI.setDefaultFeatures(CPU, /*TuneCPU*/ CPU, "");
1353 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
1354
1355 getTargetStreamer().emitMachine(CPU);
1356
1357 return false;
1358}
1359
1360bool SystemZAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc,
1361 SMLoc &EndLoc, bool RestoreOnFailure) {
1362 Register Reg;
1363 if (parseRegister(Reg, RestoreOnFailure))
1364 return true;
1365 if (Reg.Group == RegGR)
1366 RegNo = SystemZMC::GR64Regs[Reg.Num];
1367 else if (Reg.Group == RegFP)
1368 RegNo = SystemZMC::FP64Regs[Reg.Num];
1369 else if (Reg.Group == RegV)
1370 RegNo = SystemZMC::VR128Regs[Reg.Num];
1371 else if (Reg.Group == RegAR)
1372 RegNo = SystemZMC::AR32Regs[Reg.Num];
1373 else if (Reg.Group == RegCR)
1374 RegNo = SystemZMC::CR64Regs[Reg.Num];
1375 StartLoc = Reg.StartLoc;
1376 EndLoc = Reg.EndLoc;
1377 return false;
1378}
1379
1380bool SystemZAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc,
1381 SMLoc &EndLoc) {
1382 return ParseRegister(RegNo, StartLoc, EndLoc, /*RestoreOnFailure=*/false);
1383}
1384
1385OperandMatchResultTy SystemZAsmParser::tryParseRegister(unsigned &RegNo,
1386 SMLoc &StartLoc,
1387 SMLoc &EndLoc) {
1388 bool Result =
1389 ParseRegister(RegNo, StartLoc, EndLoc, /*RestoreOnFailure=*/true);
1390 bool PendingErrors = getParser().hasPendingError();
1391 getParser().clearPendingErrors();
1392 if (PendingErrors)
1393 return MatchOperand_ParseFail;
1394 if (Result)
1395 return MatchOperand_NoMatch;
1396 return MatchOperand_Success;
1397}
1398
1399bool SystemZAsmParser::ParseInstruction(ParseInstructionInfo &Info,
1400 StringRef Name, SMLoc NameLoc,
1401 OperandVector &Operands) {
1402
1403 // Apply mnemonic aliases first, before doing anything else, in
1404 // case the target uses it.
1405 applyMnemonicAliases(Name, getAvailableFeatures(), getMAIAssemblerDialect());
1406
1407 Operands.push_back(SystemZOperand::createToken(Name, NameLoc));
1408
1409 // Read the remaining operands.
1410 if (getLexer().isNot(AsmToken::EndOfStatement)) {
1411 // Read the first operand.
1412 if (parseOperand(Operands, Name)) {
1413 return true;
1414 }
1415
1416 // Read any subsequent operands.
1417 while (getLexer().is(AsmToken::Comma)) {
1418 Parser.Lex();
1419
1420 if (isParsingHLASM() && getLexer().is(AsmToken::Space))
1421 return Error(
1422 Parser.getTok().getLoc(),
1423 "No space allowed between comma that separates operand entries");
1424
1425 if (parseOperand(Operands, Name)) {
1426 return true;
1427 }
1428 }
1429
1430 // Under the HLASM variant, we could have the remark field
1431 // The remark field occurs after the operation entries
1432 // There is a space that separates the operation entries and the
1433 // remark field.
1434 if (isParsingHLASM() && getTok().is(AsmToken::Space)) {
1435 // We've confirmed that there is a Remark field.
1436 StringRef Remark(getLexer().LexUntilEndOfStatement());
1437 Parser.Lex();
1438
1439 // If there is nothing after the space, then there is nothing to emit
1440 // We could have a situation as this:
1441 // " \n"
1442 // After lexing above, we will have
1443 // "\n"
1444 // This isn't an explicit remark field, so we don't have to output
1445 // this as a comment.
1446 if (Remark.size())
1447 // Output the entire Remarks Field as a comment
1448 getStreamer().AddComment(Remark);
1449 }
1450
1451 if (getLexer().isNot(AsmToken::EndOfStatement)) {
1452 SMLoc Loc = getLexer().getLoc();
1453 return Error(Loc, "unexpected token in argument list");
1454 }
1455 }
1456
1457 // Consume the EndOfStatement.
1458 Parser.Lex();
1459 return false;
1460}
1461
1462bool SystemZAsmParser::parseOperand(OperandVector &Operands,
1463 StringRef Mnemonic) {
1464 // Check if the current operand has a custom associated parser, if so, try to
1465 // custom parse the operand, or fallback to the general approach. Force all
1466 // features to be available during the operand check, or else we will fail to
1467 // find the custom parser, and then we will later get an InvalidOperand error
1468 // instead of a MissingFeature errror.
1469 FeatureBitset AvailableFeatures = getAvailableFeatures();
1470 FeatureBitset All;
1471 All.set();
1472 setAvailableFeatures(All);
1473 OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
1474 setAvailableFeatures(AvailableFeatures);
1475 if (ResTy == MatchOperand_Success)
1476 return false;
1477
1478 // If there wasn't a custom match, try the generic matcher below. Otherwise,
1479 // there was a match, but an error occurred, in which case, just return that
1480 // the operand parsing failed.
1481 if (ResTy == MatchOperand_ParseFail)
1482 return true;
1483
1484 // Check for a register. All real register operands should have used
1485 // a context-dependent parse routine, which gives the required register
1486 // class. The code is here to mop up other cases, like those where
1487 // the instruction isn't recognized.
1488 if (isParsingATT() && Parser.getTok().is(AsmToken::Percent)) {
1489 Register Reg;
1490 if (parseRegister(Reg))
1491 return true;
1492 Operands.push_back(SystemZOperand::createInvalid(Reg.StartLoc, Reg.EndLoc));
1493 return false;
1494 }
1495
1496 // The only other type of operand is an immediate or address. As above,
1497 // real address operands should have used a context-dependent parse routine,
1498 // so we treat any plain expression as an immediate.
1499 SMLoc StartLoc = Parser.getTok().getLoc();
1500 Register Reg1, Reg2;
1501 bool HaveReg1, HaveReg2;
1502 const MCExpr *Expr;
1503 const MCExpr *Length;
1504 if (parseAddress(HaveReg1, Reg1, HaveReg2, Reg2, Expr, Length,
1505 /*HasLength*/ true, /*HasVectorIndex*/ true))
1506 return true;
1507 // If the register combination is not valid for any instruction, reject it.
1508 // Otherwise, fall back to reporting an unrecognized instruction.
1509 if (HaveReg1 && Reg1.Group != RegGR && Reg1.Group != RegV
1510 && parseAddressRegister(Reg1))
1511 return true;
1512 if (HaveReg2 && parseAddressRegister(Reg2))
1513 return true;
1514
1515 SMLoc EndLoc =
1516 SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1517 if (HaveReg1 || HaveReg2 || Length)
1518 Operands.push_back(SystemZOperand::createInvalid(StartLoc, EndLoc));
1519 else
1520 Operands.push_back(SystemZOperand::createImm(Expr, StartLoc, EndLoc));
1521 return false;
1522}
1523
1524bool SystemZAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
1525 OperandVector &Operands,
1526 MCStreamer &Out,
1527 uint64_t &ErrorInfo,
1528 bool MatchingInlineAsm) {
1529 MCInst Inst;
1530 unsigned MatchResult;
1531
1532 unsigned Dialect = getMAIAssemblerDialect();
1533
1534 FeatureBitset MissingFeatures;
1535 MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo, MissingFeatures,
1536 MatchingInlineAsm, Dialect);
1537 switch (MatchResult) {
1538 case Match_Success:
1539 Inst.setLoc(IDLoc);
1540 Out.emitInstruction(Inst, getSTI());
1541 return false;
1542
1543 case Match_MissingFeature: {
1544 assert(MissingFeatures.any() && "Unknown missing feature!")(static_cast <bool> (MissingFeatures.any() && "Unknown missing feature!"
) ? void (0) : __assert_fail ("MissingFeatures.any() && \"Unknown missing feature!\""
, "llvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp", 1544
, __extension__ __PRETTY_FUNCTION__))
;
1545 // Special case the error message for the very common case where only
1546 // a single subtarget feature is missing
1547 std::string Msg = "instruction requires:";
1548 for (unsigned I = 0, E = MissingFeatures.size(); I != E; ++I) {
1549 if (MissingFeatures[I]) {
1550 Msg += " ";
1551 Msg += getSubtargetFeatureName(I);
1552 }
1553 }
1554 return Error(IDLoc, Msg);
1555 }
1556
1557 case Match_InvalidOperand: {
1558 SMLoc ErrorLoc = IDLoc;
1559 if (ErrorInfo != ~0ULL) {
1560 if (ErrorInfo >= Operands.size())
1561 return Error(IDLoc, "too few operands for instruction");
1562
1563 ErrorLoc = ((SystemZOperand &)*Operands[ErrorInfo]).getStartLoc();
1564 if (ErrorLoc == SMLoc())
1565 ErrorLoc = IDLoc;
1566 }
1567 return Error(ErrorLoc, "invalid operand for instruction");
1568 }
1569
1570 case Match_MnemonicFail: {
1571 FeatureBitset FBS = ComputeAvailableFeatures(getSTI().getFeatureBits());
1572 std::string Suggestion = SystemZMnemonicSpellCheck(
1573 ((SystemZOperand &)*Operands[0]).getToken(), FBS, Dialect);
1574 return Error(IDLoc, "invalid instruction" + Suggestion,
1575 ((SystemZOperand &)*Operands[0]).getLocRange());
1576 }
1577 }
1578
1579 llvm_unreachable("Unexpected match type")::llvm::llvm_unreachable_internal("Unexpected match type", "llvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp"
, 1579)
;
1580}
1581
1582OperandMatchResultTy
1583SystemZAsmParser::parsePCRel(OperandVector &Operands, int64_t MinVal,
1584 int64_t MaxVal, bool AllowTLS) {
1585 MCContext &Ctx = getContext();
1586 MCStreamer &Out = getStreamer();
1587 const MCExpr *Expr;
1588 SMLoc StartLoc = Parser.getTok().getLoc();
1589 if (getParser().parseExpression(Expr))
1590 return MatchOperand_NoMatch;
1591
1592 auto isOutOfRangeConstant = [&](const MCExpr *E) -> bool {
1593 if (auto *CE = dyn_cast<MCConstantExpr>(E)) {
1594 int64_t Value = CE->getValue();
1595 if ((Value & 1) || Value < MinVal || Value > MaxVal)
1596 return true;
1597 }
1598 return false;
1599 };
1600
1601 // For consistency with the GNU assembler, treat immediates as offsets
1602 // from ".".
1603 if (auto *CE = dyn_cast<MCConstantExpr>(Expr)) {
1604 if (isParsingHLASM()) {
1605 Error(StartLoc, "Expected PC-relative expression");
1606 return MatchOperand_ParseFail;
1607 }
1608 if (isOutOfRangeConstant(CE)) {
1609 Error(StartLoc, "offset out of range");
1610 return MatchOperand_ParseFail;
1611 }
1612 int64_t Value = CE->getValue();
1613 MCSymbol *Sym = Ctx.createTempSymbol();
1614 Out.emitLabel(Sym);
1615 const MCExpr *Base = MCSymbolRefExpr::create(Sym, MCSymbolRefExpr::VK_None,
1616 Ctx);
1617 Expr = Value == 0 ? Base : MCBinaryExpr::createAdd(Base, Expr, Ctx);
1618 }
1619
1620 // For consistency with the GNU assembler, conservatively assume that a
1621 // constant offset must by itself be within the given size range.
1622 if (const auto *BE = dyn_cast<MCBinaryExpr>(Expr))
1623 if (isOutOfRangeConstant(BE->getLHS()) ||
1624 isOutOfRangeConstant(BE->getRHS())) {
1625 Error(StartLoc, "offset out of range");
1626 return MatchOperand_ParseFail;
1627 }
1628
1629 // Optionally match :tls_gdcall: or :tls_ldcall: followed by a TLS symbol.
1630 const MCExpr *Sym = nullptr;
1631 if (AllowTLS && getLexer().is(AsmToken::Colon)) {
1632 Parser.Lex();
1633
1634 if (Parser.getTok().isNot(AsmToken::Identifier)) {
1635 Error(Parser.getTok().getLoc(), "unexpected token");
1636 return MatchOperand_ParseFail;
1637 }
1638
1639 MCSymbolRefExpr::VariantKind Kind = MCSymbolRefExpr::VK_None;
1640 StringRef Name = Parser.getTok().getString();
1641 if (Name == "tls_gdcall")
1642 Kind = MCSymbolRefExpr::VK_TLSGD;
1643 else if (Name == "tls_ldcall")
1644 Kind = MCSymbolRefExpr::VK_TLSLDM;
1645 else {
1646 Error(Parser.getTok().getLoc(), "unknown TLS tag");
1647 return MatchOperand_ParseFail;
1648 }
1649 Parser.Lex();
1650
1651 if (Parser.getTok().isNot(AsmToken::Colon)) {
1652 Error(Parser.getTok().getLoc(), "unexpected token");
1653 return MatchOperand_ParseFail;
1654 }
1655 Parser.Lex();
1656
1657 if (Parser.getTok().isNot(AsmToken::Identifier)) {
1658 Error(Parser.getTok().getLoc(), "unexpected token");
1659 return MatchOperand_ParseFail;
1660 }
1661
1662 StringRef Identifier = Parser.getTok().getString();
1663 Sym = MCSymbolRefExpr::create(Ctx.getOrCreateSymbol(Identifier),
1664 Kind, Ctx);
1665 Parser.Lex();
1666 }
1667
1668 SMLoc EndLoc =
1669 SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1670
1671 if (AllowTLS)
1672 Operands.push_back(SystemZOperand::createImmTLS(Expr, Sym,
1673 StartLoc, EndLoc));
1674 else
1675 Operands.push_back(SystemZOperand::createImm(Expr, StartLoc, EndLoc));
1676
1677 return MatchOperand_Success;
1678}
1679
1680bool SystemZAsmParser::isLabel(AsmToken &Token) {
1681 if (isParsingATT())
1682 return true;
1683
1684 // HLASM labels are ordinary symbols.
1685 // An HLASM label always starts at column 1.
1686 // An ordinary symbol syntax is laid out as follows:
1687 // Rules:
1688 // 1. Has to start with an "alphabetic character". Can be followed by up to
1689 // 62 alphanumeric characters. An "alphabetic character", in this scenario,
1690 // is a letter from 'A' through 'Z', or from 'a' through 'z',
1691 // or '$', '_', '#', or '@'
1692 // 2. Labels are case-insensitive. E.g. "lab123", "LAB123", "lAb123", etc.
1693 // are all treated as the same symbol. However, the processing for the case
1694 // folding will not be done in this function.
1695 StringRef RawLabel = Token.getString();
1696 SMLoc Loc = Token.getLoc();
1697
1698 // An HLASM label cannot be empty.
1699 if (!RawLabel.size())
1700 return !Error(Loc, "HLASM Label cannot be empty");
1701
1702 // An HLASM label cannot exceed greater than 63 characters.
1703 if (RawLabel.size() > 63)
1704 return !Error(Loc, "Maximum length for HLASM Label is 63 characters");
1705
1706 // A label must start with an "alphabetic character".
1707 if (!isHLASMAlpha(RawLabel[0]))
1708 return !Error(Loc, "HLASM Label has to start with an alphabetic "
1709 "character or the underscore character");
1710
1711 // Now, we've established that the length is valid
1712 // and the first character is alphabetic.
1713 // Check whether remaining string is alphanumeric.
1714 for (unsigned I = 1; I < RawLabel.size(); ++I)
1715 if (!isHLASMAlnum(RawLabel[I]))
1716 return !Error(Loc, "HLASM Label has to be alphanumeric");
1717
1718 return true;
1719}
1720
1721// Force static initialization.
1722extern "C" LLVM_EXTERNAL_VISIBILITY__attribute__((visibility("default"))) void LLVMInitializeSystemZAsmParser() {
1723 RegisterMCAsmParser<SystemZAsmParser> X(getTheSystemZTarget());
1724}