Bug Summary

File:lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp
Warning:line 805, column 19
The left operand of '==' is a garbage value

Annotated Source Code

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clang -cc1 -triple x86_64-pc-linux-gnu -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name SystemZAsmParser.cpp -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=cplusplus -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -mrelocation-model pic -pic-level 2 -mthread-model posix -fmath-errno -masm-verbose -mconstructor-aliases -munwind-tables -fuse-init-array -target-cpu x86-64 -dwarf-column-info -debugger-tuning=gdb -momit-leaf-frame-pointer -ffunction-sections -fdata-sections -resource-dir /usr/lib/llvm-8/lib/clang/8.0.0 -D _DEBUG -D _GNU_SOURCE -D __STDC_CONSTANT_MACROS -D __STDC_FORMAT_MACROS -D __STDC_LIMIT_MACROS -I /build/llvm-toolchain-snapshot-8~svn345461/build-llvm/lib/Target/SystemZ/AsmParser -I /build/llvm-toolchain-snapshot-8~svn345461/lib/Target/SystemZ/AsmParser -I /build/llvm-toolchain-snapshot-8~svn345461/lib/Target/SystemZ -I /build/llvm-toolchain-snapshot-8~svn345461/build-llvm/lib/Target/SystemZ -I /build/llvm-toolchain-snapshot-8~svn345461/build-llvm/include -I /build/llvm-toolchain-snapshot-8~svn345461/include -U NDEBUG -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/x86_64-linux-gnu/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/x86_64-linux-gnu/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/c++/6.3.0/backward -internal-isystem /usr/include/clang/8.0.0/include/ -internal-isystem /usr/local/include -internal-isystem /usr/lib/llvm-8/lib/clang/8.0.0/include -internal-externc-isystem /usr/include/x86_64-linux-gnu -internal-externc-isystem /include -internal-externc-isystem /usr/include -O2 -Wno-unused-parameter -Wwrite-strings -Wno-missing-field-initializers -Wno-long-long -Wno-maybe-uninitialized -Wno-comment -std=c++11 -fdeprecated-macro -fdebug-compilation-dir /build/llvm-toolchain-snapshot-8~svn345461/build-llvm/lib/Target/SystemZ/AsmParser -ferror-limit 19 -fmessage-length 0 -fvisibility-inlines-hidden -fobjc-runtime=gcc -fdiagnostics-show-option -vectorize-loops -vectorize-slp -analyzer-output=html -analyzer-config stable-report-filename=true -o /tmp/scan-build-2018-10-27-211344-32123-1 -x c++ /build/llvm-toolchain-snapshot-8~svn345461/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp -faddrsig
1//===-- SystemZAsmParser.cpp - Parse SystemZ assembly instructions --------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
10#include "InstPrinter/SystemZInstPrinter.h"
11#include "MCTargetDesc/SystemZMCTargetDesc.h"
12#include "llvm/ADT/STLExtras.h"
13#include "llvm/ADT/SmallVector.h"
14#include "llvm/ADT/StringRef.h"
15#include "llvm/MC/MCContext.h"
16#include "llvm/MC/MCExpr.h"
17#include "llvm/MC/MCInst.h"
18#include "llvm/MC/MCInstBuilder.h"
19#include "llvm/MC/MCParser/MCAsmLexer.h"
20#include "llvm/MC/MCParser/MCAsmParser.h"
21#include "llvm/MC/MCParser/MCAsmParserExtension.h"
22#include "llvm/MC/MCParser/MCParsedAsmOperand.h"
23#include "llvm/MC/MCParser/MCTargetAsmParser.h"
24#include "llvm/MC/MCStreamer.h"
25#include "llvm/MC/MCSubtargetInfo.h"
26#include "llvm/Support/Casting.h"
27#include "llvm/Support/ErrorHandling.h"
28#include "llvm/Support/SMLoc.h"
29#include "llvm/Support/TargetRegistry.h"
30#include <algorithm>
31#include <cassert>
32#include <cstddef>
33#include <cstdint>
34#include <iterator>
35#include <memory>
36#include <string>
37
38using namespace llvm;
39
40// Return true if Expr is in the range [MinValue, MaxValue].
41static bool inRange(const MCExpr *Expr, int64_t MinValue, int64_t MaxValue) {
42 if (auto *CE = dyn_cast<MCConstantExpr>(Expr)) {
43 int64_t Value = CE->getValue();
44 return Value >= MinValue && Value <= MaxValue;
45 }
46 return false;
47}
48
49namespace {
50
51enum RegisterKind {
52 GR32Reg,
53 GRH32Reg,
54 GR64Reg,
55 GR128Reg,
56 ADDR32Reg,
57 ADDR64Reg,
58 FP32Reg,
59 FP64Reg,
60 FP128Reg,
61 VR32Reg,
62 VR64Reg,
63 VR128Reg,
64 AR32Reg,
65 CR64Reg,
66};
67
68enum MemoryKind {
69 BDMem,
70 BDXMem,
71 BDLMem,
72 BDRMem,
73 BDVMem
74};
75
76class SystemZOperand : public MCParsedAsmOperand {
77private:
78 enum OperandKind {
79 KindInvalid,
80 KindToken,
81 KindReg,
82 KindImm,
83 KindImmTLS,
84 KindMem
85 };
86
87 OperandKind Kind;
88 SMLoc StartLoc, EndLoc;
89
90 // A string of length Length, starting at Data.
91 struct TokenOp {
92 const char *Data;
93 unsigned Length;
94 };
95
96 // LLVM register Num, which has kind Kind. In some ways it might be
97 // easier for this class to have a register bank (general, floating-point
98 // or access) and a raw register number (0-15). This would postpone the
99 // interpretation of the operand to the add*() methods and avoid the need
100 // for context-dependent parsing. However, we do things the current way
101 // because of the virtual getReg() method, which needs to distinguish
102 // between (say) %r0 used as a single register and %r0 used as a pair.
103 // Context-dependent parsing can also give us slightly better error
104 // messages when invalid pairs like %r1 are used.
105 struct RegOp {
106 RegisterKind Kind;
107 unsigned Num;
108 };
109
110 // Base + Disp + Index, where Base and Index are LLVM registers or 0.
111 // MemKind says what type of memory this is and RegKind says what type
112 // the base register has (ADDR32Reg or ADDR64Reg). Length is the operand
113 // length for D(L,B)-style operands, otherwise it is null.
114 struct MemOp {
115 unsigned Base : 12;
116 unsigned Index : 12;
117 unsigned MemKind : 4;
118 unsigned RegKind : 4;
119 const MCExpr *Disp;
120 union {
121 const MCExpr *Imm;
122 unsigned Reg;
123 } Length;
124 };
125
126 // Imm is an immediate operand, and Sym is an optional TLS symbol
127 // for use with a __tls_get_offset marker relocation.
128 struct ImmTLSOp {
129 const MCExpr *Imm;
130 const MCExpr *Sym;
131 };
132
133 union {
134 TokenOp Token;
135 RegOp Reg;
136 const MCExpr *Imm;
137 ImmTLSOp ImmTLS;
138 MemOp Mem;
139 };
140
141 void addExpr(MCInst &Inst, const MCExpr *Expr) const {
142 // Add as immediates when possible. Null MCExpr = 0.
143 if (!Expr)
144 Inst.addOperand(MCOperand::createImm(0));
145 else if (auto *CE = dyn_cast<MCConstantExpr>(Expr))
146 Inst.addOperand(MCOperand::createImm(CE->getValue()));
147 else
148 Inst.addOperand(MCOperand::createExpr(Expr));
149 }
150
151public:
152 SystemZOperand(OperandKind kind, SMLoc startLoc, SMLoc endLoc)
153 : Kind(kind), StartLoc(startLoc), EndLoc(endLoc) {}
154
155 // Create particular kinds of operand.
156 static std::unique_ptr<SystemZOperand> createInvalid(SMLoc StartLoc,
157 SMLoc EndLoc) {
158 return make_unique<SystemZOperand>(KindInvalid, StartLoc, EndLoc);
159 }
160
161 static std::unique_ptr<SystemZOperand> createToken(StringRef Str, SMLoc Loc) {
162 auto Op = make_unique<SystemZOperand>(KindToken, Loc, Loc);
163 Op->Token.Data = Str.data();
164 Op->Token.Length = Str.size();
165 return Op;
166 }
167
168 static std::unique_ptr<SystemZOperand>
169 createReg(RegisterKind Kind, unsigned Num, SMLoc StartLoc, SMLoc EndLoc) {
170 auto Op = make_unique<SystemZOperand>(KindReg, StartLoc, EndLoc);
171 Op->Reg.Kind = Kind;
172 Op->Reg.Num = Num;
173 return Op;
174 }
175
176 static std::unique_ptr<SystemZOperand>
177 createImm(const MCExpr *Expr, SMLoc StartLoc, SMLoc EndLoc) {
178 auto Op = make_unique<SystemZOperand>(KindImm, StartLoc, EndLoc);
179 Op->Imm = Expr;
180 return Op;
181 }
182
183 static std::unique_ptr<SystemZOperand>
184 createMem(MemoryKind MemKind, RegisterKind RegKind, unsigned Base,
185 const MCExpr *Disp, unsigned Index, const MCExpr *LengthImm,
186 unsigned LengthReg, SMLoc StartLoc, SMLoc EndLoc) {
187 auto Op = make_unique<SystemZOperand>(KindMem, StartLoc, EndLoc);
188 Op->Mem.MemKind = MemKind;
189 Op->Mem.RegKind = RegKind;
190 Op->Mem.Base = Base;
191 Op->Mem.Index = Index;
192 Op->Mem.Disp = Disp;
193 if (MemKind == BDLMem)
194 Op->Mem.Length.Imm = LengthImm;
195 if (MemKind == BDRMem)
196 Op->Mem.Length.Reg = LengthReg;
197 return Op;
198 }
199
200 static std::unique_ptr<SystemZOperand>
201 createImmTLS(const MCExpr *Imm, const MCExpr *Sym,
202 SMLoc StartLoc, SMLoc EndLoc) {
203 auto Op = make_unique<SystemZOperand>(KindImmTLS, StartLoc, EndLoc);
204 Op->ImmTLS.Imm = Imm;
205 Op->ImmTLS.Sym = Sym;
206 return Op;
207 }
208
209 // Token operands
210 bool isToken() const override {
211 return Kind == KindToken;
212 }
213 StringRef getToken() const {
214 assert(Kind == KindToken && "Not a token")((Kind == KindToken && "Not a token") ? static_cast<
void> (0) : __assert_fail ("Kind == KindToken && \"Not a token\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp"
, 214, __PRETTY_FUNCTION__))
;
215 return StringRef(Token.Data, Token.Length);
216 }
217
218 // Register operands.
219 bool isReg() const override {
220 return Kind == KindReg;
221 }
222 bool isReg(RegisterKind RegKind) const {
223 return Kind == KindReg && Reg.Kind == RegKind;
224 }
225 unsigned getReg() const override {
226 assert(Kind == KindReg && "Not a register")((Kind == KindReg && "Not a register") ? static_cast<
void> (0) : __assert_fail ("Kind == KindReg && \"Not a register\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp"
, 226, __PRETTY_FUNCTION__))
;
227 return Reg.Num;
228 }
229
230 // Immediate operands.
231 bool isImm() const override {
232 return Kind == KindImm;
233 }
234 bool isImm(int64_t MinValue, int64_t MaxValue) const {
235 return Kind == KindImm && inRange(Imm, MinValue, MaxValue);
236 }
237 const MCExpr *getImm() const {
238 assert(Kind == KindImm && "Not an immediate")((Kind == KindImm && "Not an immediate") ? static_cast
<void> (0) : __assert_fail ("Kind == KindImm && \"Not an immediate\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp"
, 238, __PRETTY_FUNCTION__))
;
239 return Imm;
240 }
241
242 // Immediate operands with optional TLS symbol.
243 bool isImmTLS() const {
244 return Kind == KindImmTLS;
245 }
246
247 const ImmTLSOp getImmTLS() const {
248 assert(Kind == KindImmTLS && "Not a TLS immediate")((Kind == KindImmTLS && "Not a TLS immediate") ? static_cast
<void> (0) : __assert_fail ("Kind == KindImmTLS && \"Not a TLS immediate\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp"
, 248, __PRETTY_FUNCTION__))
;
249 return ImmTLS;
250 }
251
252 // Memory operands.
253 bool isMem() const override {
254 return Kind == KindMem;
255 }
256 bool isMem(MemoryKind MemKind) const {
257 return (Kind == KindMem &&
258 (Mem.MemKind == MemKind ||
259 // A BDMem can be treated as a BDXMem in which the index
260 // register field is 0.
261 (Mem.MemKind == BDMem && MemKind == BDXMem)));
262 }
263 bool isMem(MemoryKind MemKind, RegisterKind RegKind) const {
264 return isMem(MemKind) && Mem.RegKind == RegKind;
265 }
266 bool isMemDisp12(MemoryKind MemKind, RegisterKind RegKind) const {
267 return isMem(MemKind, RegKind) && inRange(Mem.Disp, 0, 0xfff);
268 }
269 bool isMemDisp20(MemoryKind MemKind, RegisterKind RegKind) const {
270 return isMem(MemKind, RegKind) && inRange(Mem.Disp, -524288, 524287);
271 }
272 bool isMemDisp12Len4(RegisterKind RegKind) const {
273 return isMemDisp12(BDLMem, RegKind) && inRange(Mem.Length.Imm, 1, 0x10);
274 }
275 bool isMemDisp12Len8(RegisterKind RegKind) const {
276 return isMemDisp12(BDLMem, RegKind) && inRange(Mem.Length.Imm, 1, 0x100);
277 }
278
279 const MemOp& getMem() const {
280 assert(Kind == KindMem && "Not a Mem operand")((Kind == KindMem && "Not a Mem operand") ? static_cast
<void> (0) : __assert_fail ("Kind == KindMem && \"Not a Mem operand\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp"
, 280, __PRETTY_FUNCTION__))
;
281 return Mem;
282 }
283
284 // Override MCParsedAsmOperand.
285 SMLoc getStartLoc() const override { return StartLoc; }
286 SMLoc getEndLoc() const override { return EndLoc; }
287 void print(raw_ostream &OS) const override;
288
289 /// getLocRange - Get the range between the first and last token of this
290 /// operand.
291 SMRange getLocRange() const { return SMRange(StartLoc, EndLoc); }
292
293 // Used by the TableGen code to add particular types of operand
294 // to an instruction.
295 void addRegOperands(MCInst &Inst, unsigned N) const {
296 assert(N == 1 && "Invalid number of operands")((N == 1 && "Invalid number of operands") ? static_cast
<void> (0) : __assert_fail ("N == 1 && \"Invalid number of operands\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp"
, 296, __PRETTY_FUNCTION__))
;
297 Inst.addOperand(MCOperand::createReg(getReg()));
298 }
299 void addImmOperands(MCInst &Inst, unsigned N) const {
300 assert(N == 1 && "Invalid number of operands")((N == 1 && "Invalid number of operands") ? static_cast
<void> (0) : __assert_fail ("N == 1 && \"Invalid number of operands\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp"
, 300, __PRETTY_FUNCTION__))
;
301 addExpr(Inst, getImm());
302 }
303 void addBDAddrOperands(MCInst &Inst, unsigned N) const {
304 assert(N == 2 && "Invalid number of operands")((N == 2 && "Invalid number of operands") ? static_cast
<void> (0) : __assert_fail ("N == 2 && \"Invalid number of operands\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp"
, 304, __PRETTY_FUNCTION__))
;
305 assert(isMem(BDMem) && "Invalid operand type")((isMem(BDMem) && "Invalid operand type") ? static_cast
<void> (0) : __assert_fail ("isMem(BDMem) && \"Invalid operand type\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp"
, 305, __PRETTY_FUNCTION__))
;
306 Inst.addOperand(MCOperand::createReg(Mem.Base));
307 addExpr(Inst, Mem.Disp);
308 }
309 void addBDXAddrOperands(MCInst &Inst, unsigned N) const {
310 assert(N == 3 && "Invalid number of operands")((N == 3 && "Invalid number of operands") ? static_cast
<void> (0) : __assert_fail ("N == 3 && \"Invalid number of operands\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp"
, 310, __PRETTY_FUNCTION__))
;
311 assert(isMem(BDXMem) && "Invalid operand type")((isMem(BDXMem) && "Invalid operand type") ? static_cast
<void> (0) : __assert_fail ("isMem(BDXMem) && \"Invalid operand type\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp"
, 311, __PRETTY_FUNCTION__))
;
312 Inst.addOperand(MCOperand::createReg(Mem.Base));
313 addExpr(Inst, Mem.Disp);
314 Inst.addOperand(MCOperand::createReg(Mem.Index));
315 }
316 void addBDLAddrOperands(MCInst &Inst, unsigned N) const {
317 assert(N == 3 && "Invalid number of operands")((N == 3 && "Invalid number of operands") ? static_cast
<void> (0) : __assert_fail ("N == 3 && \"Invalid number of operands\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp"
, 317, __PRETTY_FUNCTION__))
;
318 assert(isMem(BDLMem) && "Invalid operand type")((isMem(BDLMem) && "Invalid operand type") ? static_cast
<void> (0) : __assert_fail ("isMem(BDLMem) && \"Invalid operand type\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp"
, 318, __PRETTY_FUNCTION__))
;
319 Inst.addOperand(MCOperand::createReg(Mem.Base));
320 addExpr(Inst, Mem.Disp);
321 addExpr(Inst, Mem.Length.Imm);
322 }
323 void addBDRAddrOperands(MCInst &Inst, unsigned N) const {
324 assert(N == 3 && "Invalid number of operands")((N == 3 && "Invalid number of operands") ? static_cast
<void> (0) : __assert_fail ("N == 3 && \"Invalid number of operands\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp"
, 324, __PRETTY_FUNCTION__))
;
325 assert(isMem(BDRMem) && "Invalid operand type")((isMem(BDRMem) && "Invalid operand type") ? static_cast
<void> (0) : __assert_fail ("isMem(BDRMem) && \"Invalid operand type\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp"
, 325, __PRETTY_FUNCTION__))
;
326 Inst.addOperand(MCOperand::createReg(Mem.Base));
327 addExpr(Inst, Mem.Disp);
328 Inst.addOperand(MCOperand::createReg(Mem.Length.Reg));
329 }
330 void addBDVAddrOperands(MCInst &Inst, unsigned N) const {
331 assert(N == 3 && "Invalid number of operands")((N == 3 && "Invalid number of operands") ? static_cast
<void> (0) : __assert_fail ("N == 3 && \"Invalid number of operands\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp"
, 331, __PRETTY_FUNCTION__))
;
332 assert(isMem(BDVMem) && "Invalid operand type")((isMem(BDVMem) && "Invalid operand type") ? static_cast
<void> (0) : __assert_fail ("isMem(BDVMem) && \"Invalid operand type\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp"
, 332, __PRETTY_FUNCTION__))
;
333 Inst.addOperand(MCOperand::createReg(Mem.Base));
334 addExpr(Inst, Mem.Disp);
335 Inst.addOperand(MCOperand::createReg(Mem.Index));
336 }
337 void addImmTLSOperands(MCInst &Inst, unsigned N) const {
338 assert(N == 2 && "Invalid number of operands")((N == 2 && "Invalid number of operands") ? static_cast
<void> (0) : __assert_fail ("N == 2 && \"Invalid number of operands\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp"
, 338, __PRETTY_FUNCTION__))
;
339 assert(Kind == KindImmTLS && "Invalid operand type")((Kind == KindImmTLS && "Invalid operand type") ? static_cast
<void> (0) : __assert_fail ("Kind == KindImmTLS && \"Invalid operand type\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp"
, 339, __PRETTY_FUNCTION__))
;
340 addExpr(Inst, ImmTLS.Imm);
341 if (ImmTLS.Sym)
342 addExpr(Inst, ImmTLS.Sym);
343 }
344
345 // Used by the TableGen code to check for particular operand types.
346 bool isGR32() const { return isReg(GR32Reg); }
347 bool isGRH32() const { return isReg(GRH32Reg); }
348 bool isGRX32() const { return false; }
349 bool isGR64() const { return isReg(GR64Reg); }
350 bool isGR128() const { return isReg(GR128Reg); }
351 bool isADDR32() const { return isReg(ADDR32Reg); }
352 bool isADDR64() const { return isReg(ADDR64Reg); }
353 bool isADDR128() const { return false; }
354 bool isFP32() const { return isReg(FP32Reg); }
355 bool isFP64() const { return isReg(FP64Reg); }
356 bool isFP128() const { return isReg(FP128Reg); }
357 bool isVR32() const { return isReg(VR32Reg); }
358 bool isVR64() const { return isReg(VR64Reg); }
359 bool isVF128() const { return false; }
360 bool isVR128() const { return isReg(VR128Reg); }
361 bool isAR32() const { return isReg(AR32Reg); }
362 bool isCR64() const { return isReg(CR64Reg); }
363 bool isAnyReg() const { return (isReg() || isImm(0, 15)); }
364 bool isBDAddr32Disp12() const { return isMemDisp12(BDMem, ADDR32Reg); }
365 bool isBDAddr32Disp20() const { return isMemDisp20(BDMem, ADDR32Reg); }
366 bool isBDAddr64Disp12() const { return isMemDisp12(BDMem, ADDR64Reg); }
367 bool isBDAddr64Disp20() const { return isMemDisp20(BDMem, ADDR64Reg); }
368 bool isBDXAddr64Disp12() const { return isMemDisp12(BDXMem, ADDR64Reg); }
369 bool isBDXAddr64Disp20() const { return isMemDisp20(BDXMem, ADDR64Reg); }
370 bool isBDLAddr64Disp12Len4() const { return isMemDisp12Len4(ADDR64Reg); }
371 bool isBDLAddr64Disp12Len8() const { return isMemDisp12Len8(ADDR64Reg); }
372 bool isBDRAddr64Disp12() const { return isMemDisp12(BDRMem, ADDR64Reg); }
373 bool isBDVAddr64Disp12() const { return isMemDisp12(BDVMem, ADDR64Reg); }
374 bool isU1Imm() const { return isImm(0, 1); }
375 bool isU2Imm() const { return isImm(0, 3); }
376 bool isU3Imm() const { return isImm(0, 7); }
377 bool isU4Imm() const { return isImm(0, 15); }
378 bool isU6Imm() const { return isImm(0, 63); }
379 bool isU8Imm() const { return isImm(0, 255); }
380 bool isS8Imm() const { return isImm(-128, 127); }
381 bool isU12Imm() const { return isImm(0, 4095); }
382 bool isU16Imm() const { return isImm(0, 65535); }
383 bool isS16Imm() const { return isImm(-32768, 32767); }
384 bool isU32Imm() const { return isImm(0, (1LL << 32) - 1); }
385 bool isS32Imm() const { return isImm(-(1LL << 31), (1LL << 31) - 1); }
386 bool isU48Imm() const { return isImm(0, (1LL << 48) - 1); }
387};
388
389class SystemZAsmParser : public MCTargetAsmParser {
390#define GET_ASSEMBLER_HEADER
391#include "SystemZGenAsmMatcher.inc"
392
393private:
394 MCAsmParser &Parser;
395 enum RegisterGroup {
396 RegGR,
397 RegFP,
398 RegV,
399 RegAR,
400 RegCR
401 };
402 struct Register {
403 RegisterGroup Group;
404 unsigned Num;
405 SMLoc StartLoc, EndLoc;
406 };
407
408 bool parseRegister(Register &Reg);
409
410 bool parseRegister(Register &Reg, RegisterGroup Group, const unsigned *Regs,
411 bool IsAddress = false);
412
413 OperandMatchResultTy parseRegister(OperandVector &Operands,
414 RegisterGroup Group, const unsigned *Regs,
415 RegisterKind Kind);
416
417 OperandMatchResultTy parseAnyRegister(OperandVector &Operands);
418
419 bool parseAddress(bool &HaveReg1, Register &Reg1,
420 bool &HaveReg2, Register &Reg2,
421 const MCExpr *&Disp, const MCExpr *&Length);
422 bool parseAddressRegister(Register &Reg);
423
424 bool ParseDirectiveInsn(SMLoc L);
425
426 OperandMatchResultTy parseAddress(OperandVector &Operands,
427 MemoryKind MemKind, const unsigned *Regs,
428 RegisterKind RegKind);
429
430 OperandMatchResultTy parsePCRel(OperandVector &Operands, int64_t MinVal,
431 int64_t MaxVal, bool AllowTLS);
432
433 bool parseOperand(OperandVector &Operands, StringRef Mnemonic);
434
435public:
436 SystemZAsmParser(const MCSubtargetInfo &sti, MCAsmParser &parser,
437 const MCInstrInfo &MII,
438 const MCTargetOptions &Options)
439 : MCTargetAsmParser(Options, sti, MII), Parser(parser) {
440 MCAsmParserExtension::Initialize(Parser);
441
442 // Alias the .word directive to .short.
443 parser.addAliasForDirective(".word", ".short");
444
445 // Initialize the set of available features.
446 setAvailableFeatures(ComputeAvailableFeatures(getSTI().getFeatureBits()));
447 }
448
449 // Override MCTargetAsmParser.
450 bool ParseDirective(AsmToken DirectiveID) override;
451 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
452 bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
453 SMLoc NameLoc, OperandVector &Operands) override;
454 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
455 OperandVector &Operands, MCStreamer &Out,
456 uint64_t &ErrorInfo,
457 bool MatchingInlineAsm) override;
458
459 // Used by the TableGen code to parse particular operand types.
460 OperandMatchResultTy parseGR32(OperandVector &Operands) {
461 return parseRegister(Operands, RegGR, SystemZMC::GR32Regs, GR32Reg);
462 }
463 OperandMatchResultTy parseGRH32(OperandVector &Operands) {
464 return parseRegister(Operands, RegGR, SystemZMC::GRH32Regs, GRH32Reg);
465 }
466 OperandMatchResultTy parseGRX32(OperandVector &Operands) {
467 llvm_unreachable("GRX32 should only be used for pseudo instructions")::llvm::llvm_unreachable_internal("GRX32 should only be used for pseudo instructions"
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp"
, 467)
;
468 }
469 OperandMatchResultTy parseGR64(OperandVector &Operands) {
470 return parseRegister(Operands, RegGR, SystemZMC::GR64Regs, GR64Reg);
471 }
472 OperandMatchResultTy parseGR128(OperandVector &Operands) {
473 return parseRegister(Operands, RegGR, SystemZMC::GR128Regs, GR128Reg);
474 }
475 OperandMatchResultTy parseADDR32(OperandVector &Operands) {
476 return parseRegister(Operands, RegGR, SystemZMC::GR32Regs, ADDR32Reg);
477 }
478 OperandMatchResultTy parseADDR64(OperandVector &Operands) {
479 return parseRegister(Operands, RegGR, SystemZMC::GR64Regs, ADDR64Reg);
480 }
481 OperandMatchResultTy parseADDR128(OperandVector &Operands) {
482 llvm_unreachable("Shouldn't be used as an operand")::llvm::llvm_unreachable_internal("Shouldn't be used as an operand"
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp"
, 482)
;
483 }
484 OperandMatchResultTy parseFP32(OperandVector &Operands) {
485 return parseRegister(Operands, RegFP, SystemZMC::FP32Regs, FP32Reg);
486 }
487 OperandMatchResultTy parseFP64(OperandVector &Operands) {
488 return parseRegister(Operands, RegFP, SystemZMC::FP64Regs, FP64Reg);
489 }
490 OperandMatchResultTy parseFP128(OperandVector &Operands) {
491 return parseRegister(Operands, RegFP, SystemZMC::FP128Regs, FP128Reg);
492 }
493 OperandMatchResultTy parseVR32(OperandVector &Operands) {
494 return parseRegister(Operands, RegV, SystemZMC::VR32Regs, VR32Reg);
495 }
496 OperandMatchResultTy parseVR64(OperandVector &Operands) {
497 return parseRegister(Operands, RegV, SystemZMC::VR64Regs, VR64Reg);
498 }
499 OperandMatchResultTy parseVF128(OperandVector &Operands) {
500 llvm_unreachable("Shouldn't be used as an operand")::llvm::llvm_unreachable_internal("Shouldn't be used as an operand"
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp"
, 500)
;
501 }
502 OperandMatchResultTy parseVR128(OperandVector &Operands) {
503 return parseRegister(Operands, RegV, SystemZMC::VR128Regs, VR128Reg);
504 }
505 OperandMatchResultTy parseAR32(OperandVector &Operands) {
506 return parseRegister(Operands, RegAR, SystemZMC::AR32Regs, AR32Reg);
507 }
508 OperandMatchResultTy parseCR64(OperandVector &Operands) {
509 return parseRegister(Operands, RegCR, SystemZMC::CR64Regs, CR64Reg);
510 }
511 OperandMatchResultTy parseAnyReg(OperandVector &Operands) {
512 return parseAnyRegister(Operands);
14
Calling 'SystemZAsmParser::parseAnyRegister'
513 }
514 OperandMatchResultTy parseBDAddr32(OperandVector &Operands) {
515 return parseAddress(Operands, BDMem, SystemZMC::GR32Regs, ADDR32Reg);
516 }
517 OperandMatchResultTy parseBDAddr64(OperandVector &Operands) {
518 return parseAddress(Operands, BDMem, SystemZMC::GR64Regs, ADDR64Reg);
519 }
520 OperandMatchResultTy parseBDXAddr64(OperandVector &Operands) {
521 return parseAddress(Operands, BDXMem, SystemZMC::GR64Regs, ADDR64Reg);
522 }
523 OperandMatchResultTy parseBDLAddr64(OperandVector &Operands) {
524 return parseAddress(Operands, BDLMem, SystemZMC::GR64Regs, ADDR64Reg);
525 }
526 OperandMatchResultTy parseBDRAddr64(OperandVector &Operands) {
527 return parseAddress(Operands, BDRMem, SystemZMC::GR64Regs, ADDR64Reg);
528 }
529 OperandMatchResultTy parseBDVAddr64(OperandVector &Operands) {
530 return parseAddress(Operands, BDVMem, SystemZMC::GR64Regs, ADDR64Reg);
531 }
532 OperandMatchResultTy parsePCRel12(OperandVector &Operands) {
533 return parsePCRel(Operands, -(1LL << 12), (1LL << 12) - 1, false);
534 }
535 OperandMatchResultTy parsePCRel16(OperandVector &Operands) {
536 return parsePCRel(Operands, -(1LL << 16), (1LL << 16) - 1, false);
537 }
538 OperandMatchResultTy parsePCRel24(OperandVector &Operands) {
539 return parsePCRel(Operands, -(1LL << 24), (1LL << 24) - 1, false);
540 }
541 OperandMatchResultTy parsePCRel32(OperandVector &Operands) {
542 return parsePCRel(Operands, -(1LL << 32), (1LL << 32) - 1, false);
543 }
544 OperandMatchResultTy parsePCRelTLS16(OperandVector &Operands) {
545 return parsePCRel(Operands, -(1LL << 16), (1LL << 16) - 1, true);
546 }
547 OperandMatchResultTy parsePCRelTLS32(OperandVector &Operands) {
548 return parsePCRel(Operands, -(1LL << 32), (1LL << 32) - 1, true);
549 }
550};
551
552} // end anonymous namespace
553
554#define GET_REGISTER_MATCHER
555#define GET_SUBTARGET_FEATURE_NAME
556#define GET_MATCHER_IMPLEMENTATION
557#define GET_MNEMONIC_SPELL_CHECKER
558#include "SystemZGenAsmMatcher.inc"
559
560// Used for the .insn directives; contains information needed to parse the
561// operands in the directive.
562struct InsnMatchEntry {
563 StringRef Format;
564 uint64_t Opcode;
565 int32_t NumOperands;
566 MatchClassKind OperandKinds[5];
567};
568
569// For equal_range comparison.
570struct CompareInsn {
571 bool operator() (const InsnMatchEntry &LHS, StringRef RHS) {
572 return LHS.Format < RHS;
573 }
574 bool operator() (StringRef LHS, const InsnMatchEntry &RHS) {
575 return LHS < RHS.Format;
576 }
577 bool operator() (const InsnMatchEntry &LHS, const InsnMatchEntry &RHS) {
578 return LHS.Format < RHS.Format;
579 }
580};
581
582// Table initializing information for parsing the .insn directive.
583static struct InsnMatchEntry InsnMatchTable[] = {
584 /* Format, Opcode, NumOperands, OperandKinds */
585 { "e", SystemZ::InsnE, 1,
586 { MCK_U16Imm } },
587 { "ri", SystemZ::InsnRI, 3,
588 { MCK_U32Imm, MCK_AnyReg, MCK_S16Imm } },
589 { "rie", SystemZ::InsnRIE, 4,
590 { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_PCRel16 } },
591 { "ril", SystemZ::InsnRIL, 3,
592 { MCK_U48Imm, MCK_AnyReg, MCK_PCRel32 } },
593 { "rilu", SystemZ::InsnRILU, 3,
594 { MCK_U48Imm, MCK_AnyReg, MCK_U32Imm } },
595 { "ris", SystemZ::InsnRIS, 5,
596 { MCK_U48Imm, MCK_AnyReg, MCK_S8Imm, MCK_U4Imm, MCK_BDAddr64Disp12 } },
597 { "rr", SystemZ::InsnRR, 3,
598 { MCK_U16Imm, MCK_AnyReg, MCK_AnyReg } },
599 { "rre", SystemZ::InsnRRE, 3,
600 { MCK_U32Imm, MCK_AnyReg, MCK_AnyReg } },
601 { "rrf", SystemZ::InsnRRF, 5,
602 { MCK_U32Imm, MCK_AnyReg, MCK_AnyReg, MCK_AnyReg, MCK_U4Imm } },
603 { "rrs", SystemZ::InsnRRS, 5,
604 { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_U4Imm, MCK_BDAddr64Disp12 } },
605 { "rs", SystemZ::InsnRS, 4,
606 { MCK_U32Imm, MCK_AnyReg, MCK_AnyReg, MCK_BDAddr64Disp12 } },
607 { "rse", SystemZ::InsnRSE, 4,
608 { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_BDAddr64Disp12 } },
609 { "rsi", SystemZ::InsnRSI, 4,
610 { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_PCRel16 } },
611 { "rsy", SystemZ::InsnRSY, 4,
612 { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_BDAddr64Disp20 } },
613 { "rx", SystemZ::InsnRX, 3,
614 { MCK_U32Imm, MCK_AnyReg, MCK_BDXAddr64Disp12 } },
615 { "rxe", SystemZ::InsnRXE, 3,
616 { MCK_U48Imm, MCK_AnyReg, MCK_BDXAddr64Disp12 } },
617 { "rxf", SystemZ::InsnRXF, 4,
618 { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_BDXAddr64Disp12 } },
619 { "rxy", SystemZ::InsnRXY, 3,
620 { MCK_U48Imm, MCK_AnyReg, MCK_BDXAddr64Disp20 } },
621 { "s", SystemZ::InsnS, 2,
622 { MCK_U32Imm, MCK_BDAddr64Disp12 } },
623 { "si", SystemZ::InsnSI, 3,
624 { MCK_U32Imm, MCK_BDAddr64Disp12, MCK_S8Imm } },
625 { "sil", SystemZ::InsnSIL, 3,
626 { MCK_U48Imm, MCK_BDAddr64Disp12, MCK_U16Imm } },
627 { "siy", SystemZ::InsnSIY, 3,
628 { MCK_U48Imm, MCK_BDAddr64Disp20, MCK_U8Imm } },
629 { "ss", SystemZ::InsnSS, 4,
630 { MCK_U48Imm, MCK_BDXAddr64Disp12, MCK_BDAddr64Disp12, MCK_AnyReg } },
631 { "sse", SystemZ::InsnSSE, 3,
632 { MCK_U48Imm, MCK_BDAddr64Disp12, MCK_BDAddr64Disp12 } },
633 { "ssf", SystemZ::InsnSSF, 4,
634 { MCK_U48Imm, MCK_BDAddr64Disp12, MCK_BDAddr64Disp12, MCK_AnyReg } }
635};
636
637static void printMCExpr(const MCExpr *E, raw_ostream &OS) {
638 if (!E)
639 return;
640 if (auto *CE = dyn_cast<MCConstantExpr>(E))
641 OS << *CE;
642 else if (auto *UE = dyn_cast<MCUnaryExpr>(E))
643 OS << *UE;
644 else if (auto *BE = dyn_cast<MCBinaryExpr>(E))
645 OS << *BE;
646 else if (auto *SRE = dyn_cast<MCSymbolRefExpr>(E))
647 OS << *SRE;
648 else
649 OS << *E;
650}
651
652void SystemZOperand::print(raw_ostream &OS) const {
653 switch (Kind) {
654 break;
655 case KindToken:
656 OS << "Token:" << getToken();
657 break;
658 case KindReg:
659 OS << "Reg:" << SystemZInstPrinter::getRegisterName(getReg());
660 break;
661 case KindImm:
662 OS << "Imm:";
663 printMCExpr(getImm(), OS);
664 break;
665 case KindImmTLS:
666 OS << "ImmTLS:";
667 printMCExpr(getImmTLS().Imm, OS);
668 if (getImmTLS().Sym) {
669 OS << ", ";
670 printMCExpr(getImmTLS().Sym, OS);
671 }
672 break;
673 case KindMem: {
674 const MemOp &Op = getMem();
675 OS << "Mem:" << *cast<MCConstantExpr>(Op.Disp);
676 if (Op.Base) {
677 OS << "(";
678 if (Op.MemKind == BDLMem)
679 OS << *cast<MCConstantExpr>(Op.Length.Imm) << ",";
680 else if (Op.MemKind == BDRMem)
681 OS << SystemZInstPrinter::getRegisterName(Op.Length.Reg) << ",";
682 if (Op.Index)
683 OS << SystemZInstPrinter::getRegisterName(Op.Index) << ",";
684 OS << SystemZInstPrinter::getRegisterName(Op.Base);
685 OS << ")";
686 }
687 break;
688 }
689 case KindInvalid:
690 break;
691 }
692}
693
694// Parse one register of the form %<prefix><number>.
695bool SystemZAsmParser::parseRegister(Register &Reg) {
696 Reg.StartLoc = Parser.getTok().getLoc();
697
698 // Eat the % prefix.
699 if (Parser.getTok().isNot(AsmToken::Percent))
17
Taking true branch
700 return Error(Parser.getTok().getLoc(), "register expected");
18
Returning without writing to 'Reg.Group'
701 Parser.Lex();
702
703 // Expect a register name.
704 if (Parser.getTok().isNot(AsmToken::Identifier))
705 return Error(Reg.StartLoc, "invalid register");
706
707 // Check that there's a prefix.
708 StringRef Name = Parser.getTok().getString();
709 if (Name.size() < 2)
710 return Error(Reg.StartLoc, "invalid register");
711 char Prefix = Name[0];
712
713 // Treat the rest of the register name as a register number.
714 if (Name.substr(1).getAsInteger(10, Reg.Num))
715 return Error(Reg.StartLoc, "invalid register");
716
717 // Look for valid combinations of prefix and number.
718 if (Prefix == 'r' && Reg.Num < 16)
719 Reg.Group = RegGR;
720 else if (Prefix == 'f' && Reg.Num < 16)
721 Reg.Group = RegFP;
722 else if (Prefix == 'v' && Reg.Num < 32)
723 Reg.Group = RegV;
724 else if (Prefix == 'a' && Reg.Num < 16)
725 Reg.Group = RegAR;
726 else if (Prefix == 'c' && Reg.Num < 16)
727 Reg.Group = RegCR;
728 else
729 return Error(Reg.StartLoc, "invalid register");
730
731 Reg.EndLoc = Parser.getTok().getLoc();
732 Parser.Lex();
733 return false;
734}
735
736// Parse a register of group Group. If Regs is nonnull, use it to map
737// the raw register number to LLVM numbering, with zero entries
738// indicating an invalid register. IsAddress says whether the
739// register appears in an address context. Allow FP Group if expecting
740// RegV Group, since the f-prefix yields the FP group even while used
741// with vector instructions.
742bool SystemZAsmParser::parseRegister(Register &Reg, RegisterGroup Group,
743 const unsigned *Regs, bool IsAddress) {
744 if (parseRegister(Reg))
745 return true;
746 if (Reg.Group != Group && !(Reg.Group == RegFP && Group == RegV))
747 return Error(Reg.StartLoc, "invalid operand for instruction");
748 if (Regs && Regs[Reg.Num] == 0)
749 return Error(Reg.StartLoc, "invalid register pair");
750 if (Reg.Num == 0 && IsAddress)
751 return Error(Reg.StartLoc, "%r0 used in an address");
752 if (Regs)
753 Reg.Num = Regs[Reg.Num];
754 return false;
755}
756
757// Parse a register and add it to Operands. The other arguments are as above.
758OperandMatchResultTy
759SystemZAsmParser::parseRegister(OperandVector &Operands, RegisterGroup Group,
760 const unsigned *Regs, RegisterKind Kind) {
761 if (Parser.getTok().isNot(AsmToken::Percent))
762 return MatchOperand_NoMatch;
763
764 Register Reg;
765 bool IsAddress = (Kind == ADDR32Reg || Kind == ADDR64Reg);
766 if (parseRegister(Reg, Group, Regs, IsAddress))
767 return MatchOperand_ParseFail;
768
769 Operands.push_back(SystemZOperand::createReg(Kind, Reg.Num,
770 Reg.StartLoc, Reg.EndLoc));
771 return MatchOperand_Success;
772}
773
774// Parse any type of register (including integers) and add it to Operands.
775OperandMatchResultTy
776SystemZAsmParser::parseAnyRegister(OperandVector &Operands) {
777 // Handle integer values.
778 if (Parser.getTok().is(AsmToken::Integer)) {
15
Taking false branch
779 const MCExpr *Register;
780 SMLoc StartLoc = Parser.getTok().getLoc();
781 if (Parser.parseExpression(Register))
782 return MatchOperand_ParseFail;
783
784 if (auto *CE = dyn_cast<MCConstantExpr>(Register)) {
785 int64_t Value = CE->getValue();
786 if (Value < 0 || Value > 15) {
787 Error(StartLoc, "invalid register");
788 return MatchOperand_ParseFail;
789 }
790 }
791
792 SMLoc EndLoc =
793 SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
794
795 Operands.push_back(SystemZOperand::createImm(Register, StartLoc, EndLoc));
796 }
797 else {
798 Register Reg;
799 if (parseRegister(Reg))
16
Calling 'SystemZAsmParser::parseRegister'
19
Returning from 'SystemZAsmParser::parseRegister'
20
Assuming the condition is false
21
Taking false branch
800 return MatchOperand_ParseFail;
801
802 // Map to the correct register kind.
803 RegisterKind Kind;
804 unsigned RegNo;
805 if (Reg.Group == RegGR) {
22
The left operand of '==' is a garbage value
806 Kind = GR64Reg;
807 RegNo = SystemZMC::GR64Regs[Reg.Num];
808 }
809 else if (Reg.Group == RegFP) {
810 Kind = FP64Reg;
811 RegNo = SystemZMC::FP64Regs[Reg.Num];
812 }
813 else if (Reg.Group == RegV) {
814 Kind = VR128Reg;
815 RegNo = SystemZMC::VR128Regs[Reg.Num];
816 }
817 else if (Reg.Group == RegAR) {
818 Kind = AR32Reg;
819 RegNo = SystemZMC::AR32Regs[Reg.Num];
820 }
821 else if (Reg.Group == RegCR) {
822 Kind = CR64Reg;
823 RegNo = SystemZMC::CR64Regs[Reg.Num];
824 }
825 else {
826 return MatchOperand_ParseFail;
827 }
828
829 Operands.push_back(SystemZOperand::createReg(Kind, RegNo,
830 Reg.StartLoc, Reg.EndLoc));
831 }
832 return MatchOperand_Success;
833}
834
835// Parse a memory operand into Reg1, Reg2, Disp, and Length.
836bool SystemZAsmParser::parseAddress(bool &HaveReg1, Register &Reg1,
837 bool &HaveReg2, Register &Reg2,
838 const MCExpr *&Disp,
839 const MCExpr *&Length) {
840 // Parse the displacement, which must always be present.
841 if (getParser().parseExpression(Disp))
842 return true;
843
844 // Parse the optional base and index.
845 HaveReg1 = false;
846 HaveReg2 = false;
847 Length = nullptr;
848 if (getLexer().is(AsmToken::LParen)) {
849 Parser.Lex();
850
851 if (getLexer().is(AsmToken::Percent)) {
852 // Parse the first register.
853 HaveReg1 = true;
854 if (parseRegister(Reg1))
855 return true;
856 } else {
857 // Parse the length.
858 if (getParser().parseExpression(Length))
859 return true;
860 }
861
862 // Check whether there's a second register.
863 if (getLexer().is(AsmToken::Comma)) {
864 Parser.Lex();
865 HaveReg2 = true;
866 if (parseRegister(Reg2))
867 return true;
868 }
869
870 // Consume the closing bracket.
871 if (getLexer().isNot(AsmToken::RParen))
872 return Error(Parser.getTok().getLoc(), "unexpected token in address");
873 Parser.Lex();
874 }
875 return false;
876}
877
878// Verify that Reg is a valid address register (base or index).
879bool
880SystemZAsmParser::parseAddressRegister(Register &Reg) {
881 if (Reg.Group == RegV) {
882 Error(Reg.StartLoc, "invalid use of vector addressing");
883 return true;
884 } else if (Reg.Group != RegGR) {
885 Error(Reg.StartLoc, "invalid address register");
886 return true;
887 } else if (Reg.Num == 0) {
888 Error(Reg.StartLoc, "%r0 used in an address");
889 return true;
890 }
891 return false;
892}
893
894// Parse a memory operand and add it to Operands. The other arguments
895// are as above.
896OperandMatchResultTy
897SystemZAsmParser::parseAddress(OperandVector &Operands, MemoryKind MemKind,
898 const unsigned *Regs, RegisterKind RegKind) {
899 SMLoc StartLoc = Parser.getTok().getLoc();
900 unsigned Base = 0, Index = 0, LengthReg = 0;
901 Register Reg1, Reg2;
902 bool HaveReg1, HaveReg2;
903 const MCExpr *Disp;
904 const MCExpr *Length;
905 if (parseAddress(HaveReg1, Reg1, HaveReg2, Reg2, Disp, Length))
906 return MatchOperand_ParseFail;
907
908 switch (MemKind) {
909 case BDMem:
910 // If we have Reg1, it must be an address register.
911 if (HaveReg1) {
912 if (parseAddressRegister(Reg1))
913 return MatchOperand_ParseFail;
914 Base = Regs[Reg1.Num];
915 }
916 // There must be no Reg2 or length.
917 if (Length) {
918 Error(StartLoc, "invalid use of length addressing");
919 return MatchOperand_ParseFail;
920 }
921 if (HaveReg2) {
922 Error(StartLoc, "invalid use of indexed addressing");
923 return MatchOperand_ParseFail;
924 }
925 break;
926 case BDXMem:
927 // If we have Reg1, it must be an address register.
928 if (HaveReg1) {
929 if (parseAddressRegister(Reg1))
930 return MatchOperand_ParseFail;
931 // If the are two registers, the first one is the index and the
932 // second is the base.
933 if (HaveReg2)
934 Index = Regs[Reg1.Num];
935 else
936 Base = Regs[Reg1.Num];
937 }
938 // If we have Reg2, it must be an address register.
939 if (HaveReg2) {
940 if (parseAddressRegister(Reg2))
941 return MatchOperand_ParseFail;
942 Base = Regs[Reg2.Num];
943 }
944 // There must be no length.
945 if (Length) {
946 Error(StartLoc, "invalid use of length addressing");
947 return MatchOperand_ParseFail;
948 }
949 break;
950 case BDLMem:
951 // If we have Reg2, it must be an address register.
952 if (HaveReg2) {
953 if (parseAddressRegister(Reg2))
954 return MatchOperand_ParseFail;
955 Base = Regs[Reg2.Num];
956 }
957 // We cannot support base+index addressing.
958 if (HaveReg1 && HaveReg2) {
959 Error(StartLoc, "invalid use of indexed addressing");
960 return MatchOperand_ParseFail;
961 }
962 // We must have a length.
963 if (!Length) {
964 Error(StartLoc, "missing length in address");
965 return MatchOperand_ParseFail;
966 }
967 break;
968 case BDRMem:
969 // We must have Reg1, and it must be a GPR.
970 if (!HaveReg1 || Reg1.Group != RegGR) {
971 Error(StartLoc, "invalid operand for instruction");
972 return MatchOperand_ParseFail;
973 }
974 LengthReg = SystemZMC::GR64Regs[Reg1.Num];
975 // If we have Reg2, it must be an address register.
976 if (HaveReg2) {
977 if (parseAddressRegister(Reg2))
978 return MatchOperand_ParseFail;
979 Base = Regs[Reg2.Num];
980 }
981 // There must be no length.
982 if (Length) {
983 Error(StartLoc, "invalid use of length addressing");
984 return MatchOperand_ParseFail;
985 }
986 break;
987 case BDVMem:
988 // We must have Reg1, and it must be a vector register.
989 if (!HaveReg1 || Reg1.Group != RegV) {
990 Error(StartLoc, "vector index required in address");
991 return MatchOperand_ParseFail;
992 }
993 Index = SystemZMC::VR128Regs[Reg1.Num];
994 // If we have Reg2, it must be an address register.
995 if (HaveReg2) {
996 if (parseAddressRegister(Reg2))
997 return MatchOperand_ParseFail;
998 Base = Regs[Reg2.Num];
999 }
1000 // There must be no length.
1001 if (Length) {
1002 Error(StartLoc, "invalid use of length addressing");
1003 return MatchOperand_ParseFail;
1004 }
1005 break;
1006 }
1007
1008 SMLoc EndLoc =
1009 SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1010 Operands.push_back(SystemZOperand::createMem(MemKind, RegKind, Base, Disp,
1011 Index, Length, LengthReg,
1012 StartLoc, EndLoc));
1013 return MatchOperand_Success;
1014}
1015
1016bool SystemZAsmParser::ParseDirective(AsmToken DirectiveID) {
1017 StringRef IDVal = DirectiveID.getIdentifier();
1018
1019 if (IDVal == ".insn")
1
Assuming the condition is true
2
Taking true branch
1020 return ParseDirectiveInsn(DirectiveID.getLoc());
3
Calling 'SystemZAsmParser::ParseDirectiveInsn'
1021
1022 return true;
1023}
1024
1025/// ParseDirectiveInsn
1026/// ::= .insn [ format, encoding, (operands (, operands)*) ]
1027bool SystemZAsmParser::ParseDirectiveInsn(SMLoc L) {
1028 MCAsmParser &Parser = getParser();
1029
1030 // Expect instruction format as identifier.
1031 StringRef Format;
1032 SMLoc ErrorLoc = Parser.getTok().getLoc();
1033 if (Parser.parseIdentifier(Format))
4
Assuming the condition is false
5
Taking false branch
1034 return Error(ErrorLoc, "expected instruction format");
1035
1036 SmallVector<std::unique_ptr<MCParsedAsmOperand>, 8> Operands;
1037
1038 // Find entry for this format in InsnMatchTable.
1039 auto EntryRange =
1040 std::equal_range(std::begin(InsnMatchTable), std::end(InsnMatchTable),
1041 Format, CompareInsn());
1042
1043 // If first == second, couldn't find a match in the table.
1044 if (EntryRange.first == EntryRange.second)
6
Assuming the condition is false
7
Taking false branch
1045 return Error(ErrorLoc, "unrecognized format");
1046
1047 struct InsnMatchEntry *Entry = EntryRange.first;
1048
1049 // Format should match from equal_range.
1050 assert(Entry->Format == Format)((Entry->Format == Format) ? static_cast<void> (0) :
__assert_fail ("Entry->Format == Format", "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp"
, 1050, __PRETTY_FUNCTION__))
;
1051
1052 // Parse the following operands using the table's information.
1053 for (int i = 0; i < Entry->NumOperands; i++) {
8
Assuming the condition is true
9
Loop condition is true. Entering loop body
1054 MatchClassKind Kind = Entry->OperandKinds[i];
1055
1056 SMLoc StartLoc = Parser.getTok().getLoc();
1057
1058 // Always expect commas as separators for operands.
1059 if (getLexer().isNot(AsmToken::Comma))
10
Taking false branch
1060 return Error(StartLoc, "unexpected token in directive");
1061 Lex();
1062
1063 // Parse operands.
1064 OperandMatchResultTy ResTy;
1065 if (Kind == MCK_AnyReg)
11
Assuming 'Kind' is equal to MCK_AnyReg
12
Taking true branch
1066 ResTy = parseAnyReg(Operands);
13
Calling 'SystemZAsmParser::parseAnyReg'
1067 else if (Kind == MCK_BDXAddr64Disp12 || Kind == MCK_BDXAddr64Disp20)
1068 ResTy = parseBDXAddr64(Operands);
1069 else if (Kind == MCK_BDAddr64Disp12 || Kind == MCK_BDAddr64Disp20)
1070 ResTy = parseBDAddr64(Operands);
1071 else if (Kind == MCK_PCRel32)
1072 ResTy = parsePCRel32(Operands);
1073 else if (Kind == MCK_PCRel16)
1074 ResTy = parsePCRel16(Operands);
1075 else {
1076 // Only remaining operand kind is an immediate.
1077 const MCExpr *Expr;
1078 SMLoc StartLoc = Parser.getTok().getLoc();
1079
1080 // Expect immediate expression.
1081 if (Parser.parseExpression(Expr))
1082 return Error(StartLoc, "unexpected token in directive");
1083
1084 SMLoc EndLoc =
1085 SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1086
1087 Operands.push_back(SystemZOperand::createImm(Expr, StartLoc, EndLoc));
1088 ResTy = MatchOperand_Success;
1089 }
1090
1091 if (ResTy != MatchOperand_Success)
1092 return true;
1093 }
1094
1095 // Build the instruction with the parsed operands.
1096 MCInst Inst = MCInstBuilder(Entry->Opcode);
1097
1098 for (size_t i = 0; i < Operands.size(); i++) {
1099 MCParsedAsmOperand &Operand = *Operands[i];
1100 MatchClassKind Kind = Entry->OperandKinds[i];
1101
1102 // Verify operand.
1103 unsigned Res = validateOperandClass(Operand, Kind);
1104 if (Res != Match_Success)
1105 return Error(Operand.getStartLoc(), "unexpected operand type");
1106
1107 // Add operands to instruction.
1108 SystemZOperand &ZOperand = static_cast<SystemZOperand &>(Operand);
1109 if (ZOperand.isReg())
1110 ZOperand.addRegOperands(Inst, 1);
1111 else if (ZOperand.isMem(BDMem))
1112 ZOperand.addBDAddrOperands(Inst, 2);
1113 else if (ZOperand.isMem(BDXMem))
1114 ZOperand.addBDXAddrOperands(Inst, 3);
1115 else if (ZOperand.isImm())
1116 ZOperand.addImmOperands(Inst, 1);
1117 else
1118 llvm_unreachable("unexpected operand type")::llvm::llvm_unreachable_internal("unexpected operand type", "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp"
, 1118)
;
1119 }
1120
1121 // Emit as a regular instruction.
1122 Parser.getStreamer().EmitInstruction(Inst, getSTI());
1123
1124 return false;
1125}
1126
1127bool SystemZAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc,
1128 SMLoc &EndLoc) {
1129 Register Reg;
1130 if (parseRegister(Reg))
1131 return true;
1132 if (Reg.Group == RegGR)
1133 RegNo = SystemZMC::GR64Regs[Reg.Num];
1134 else if (Reg.Group == RegFP)
1135 RegNo = SystemZMC::FP64Regs[Reg.Num];
1136 else if (Reg.Group == RegV)
1137 RegNo = SystemZMC::VR128Regs[Reg.Num];
1138 else if (Reg.Group == RegAR)
1139 RegNo = SystemZMC::AR32Regs[Reg.Num];
1140 else if (Reg.Group == RegCR)
1141 RegNo = SystemZMC::CR64Regs[Reg.Num];
1142 StartLoc = Reg.StartLoc;
1143 EndLoc = Reg.EndLoc;
1144 return false;
1145}
1146
1147bool SystemZAsmParser::ParseInstruction(ParseInstructionInfo &Info,
1148 StringRef Name, SMLoc NameLoc,
1149 OperandVector &Operands) {
1150 Operands.push_back(SystemZOperand::createToken(Name, NameLoc));
1151
1152 // Read the remaining operands.
1153 if (getLexer().isNot(AsmToken::EndOfStatement)) {
1154 // Read the first operand.
1155 if (parseOperand(Operands, Name)) {
1156 return true;
1157 }
1158
1159 // Read any subsequent operands.
1160 while (getLexer().is(AsmToken::Comma)) {
1161 Parser.Lex();
1162 if (parseOperand(Operands, Name)) {
1163 return true;
1164 }
1165 }
1166 if (getLexer().isNot(AsmToken::EndOfStatement)) {
1167 SMLoc Loc = getLexer().getLoc();
1168 return Error(Loc, "unexpected token in argument list");
1169 }
1170 }
1171
1172 // Consume the EndOfStatement.
1173 Parser.Lex();
1174 return false;
1175}
1176
1177bool SystemZAsmParser::parseOperand(OperandVector &Operands,
1178 StringRef Mnemonic) {
1179 // Check if the current operand has a custom associated parser, if so, try to
1180 // custom parse the operand, or fallback to the general approach. Force all
1181 // features to be available during the operand check, or else we will fail to
1182 // find the custom parser, and then we will later get an InvalidOperand error
1183 // instead of a MissingFeature errror.
1184 uint64_t AvailableFeatures = getAvailableFeatures();
1185 setAvailableFeatures(~(uint64_t)0);
1186 OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
1187 setAvailableFeatures(AvailableFeatures);
1188 if (ResTy == MatchOperand_Success)
1189 return false;
1190
1191 // If there wasn't a custom match, try the generic matcher below. Otherwise,
1192 // there was a match, but an error occurred, in which case, just return that
1193 // the operand parsing failed.
1194 if (ResTy == MatchOperand_ParseFail)
1195 return true;
1196
1197 // Check for a register. All real register operands should have used
1198 // a context-dependent parse routine, which gives the required register
1199 // class. The code is here to mop up other cases, like those where
1200 // the instruction isn't recognized.
1201 if (Parser.getTok().is(AsmToken::Percent)) {
1202 Register Reg;
1203 if (parseRegister(Reg))
1204 return true;
1205 Operands.push_back(SystemZOperand::createInvalid(Reg.StartLoc, Reg.EndLoc));
1206 return false;
1207 }
1208
1209 // The only other type of operand is an immediate or address. As above,
1210 // real address operands should have used a context-dependent parse routine,
1211 // so we treat any plain expression as an immediate.
1212 SMLoc StartLoc = Parser.getTok().getLoc();
1213 Register Reg1, Reg2;
1214 bool HaveReg1, HaveReg2;
1215 const MCExpr *Expr;
1216 const MCExpr *Length;
1217 if (parseAddress(HaveReg1, Reg1, HaveReg2, Reg2, Expr, Length))
1218 return true;
1219 // If the register combination is not valid for any instruction, reject it.
1220 // Otherwise, fall back to reporting an unrecognized instruction.
1221 if (HaveReg1 && Reg1.Group != RegGR && Reg1.Group != RegV
1222 && parseAddressRegister(Reg1))
1223 return true;
1224 if (HaveReg2 && parseAddressRegister(Reg2))
1225 return true;
1226
1227 SMLoc EndLoc =
1228 SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1229 if (HaveReg1 || HaveReg2 || Length)
1230 Operands.push_back(SystemZOperand::createInvalid(StartLoc, EndLoc));
1231 else
1232 Operands.push_back(SystemZOperand::createImm(Expr, StartLoc, EndLoc));
1233 return false;
1234}
1235
1236static std::string SystemZMnemonicSpellCheck(StringRef S, uint64_t FBS,
1237 unsigned VariantID = 0);
1238
1239bool SystemZAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
1240 OperandVector &Operands,
1241 MCStreamer &Out,
1242 uint64_t &ErrorInfo,
1243 bool MatchingInlineAsm) {
1244 MCInst Inst;
1245 unsigned MatchResult;
1246
1247 MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo,
1248 MatchingInlineAsm);
1249 switch (MatchResult) {
1250 case Match_Success:
1251 Inst.setLoc(IDLoc);
1252 Out.EmitInstruction(Inst, getSTI());
1253 return false;
1254
1255 case Match_MissingFeature: {
1256 assert(ErrorInfo && "Unknown missing feature!")((ErrorInfo && "Unknown missing feature!") ? static_cast
<void> (0) : __assert_fail ("ErrorInfo && \"Unknown missing feature!\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp"
, 1256, __PRETTY_FUNCTION__))
;
1257 // Special case the error message for the very common case where only
1258 // a single subtarget feature is missing
1259 std::string Msg = "instruction requires:";
1260 uint64_t Mask = 1;
1261 for (unsigned I = 0; I < sizeof(ErrorInfo) * 8 - 1; ++I) {
1262 if (ErrorInfo & Mask) {
1263 Msg += " ";
1264 Msg += getSubtargetFeatureName(ErrorInfo & Mask);
1265 }
1266 Mask <<= 1;
1267 }
1268 return Error(IDLoc, Msg);
1269 }
1270
1271 case Match_InvalidOperand: {
1272 SMLoc ErrorLoc = IDLoc;
1273 if (ErrorInfo != ~0ULL) {
1274 if (ErrorInfo >= Operands.size())
1275 return Error(IDLoc, "too few operands for instruction");
1276
1277 ErrorLoc = ((SystemZOperand &)*Operands[ErrorInfo]).getStartLoc();
1278 if (ErrorLoc == SMLoc())
1279 ErrorLoc = IDLoc;
1280 }
1281 return Error(ErrorLoc, "invalid operand for instruction");
1282 }
1283
1284 case Match_MnemonicFail: {
1285 uint64_t FBS = ComputeAvailableFeatures(getSTI().getFeatureBits());
1286 std::string Suggestion = SystemZMnemonicSpellCheck(
1287 ((SystemZOperand &)*Operands[0]).getToken(), FBS);
1288 return Error(IDLoc, "invalid instruction" + Suggestion,
1289 ((SystemZOperand &)*Operands[0]).getLocRange());
1290 }
1291 }
1292
1293 llvm_unreachable("Unexpected match type")::llvm::llvm_unreachable_internal("Unexpected match type", "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp"
, 1293)
;
1294}
1295
1296OperandMatchResultTy
1297SystemZAsmParser::parsePCRel(OperandVector &Operands, int64_t MinVal,
1298 int64_t MaxVal, bool AllowTLS) {
1299 MCContext &Ctx = getContext();
1300 MCStreamer &Out = getStreamer();
1301 const MCExpr *Expr;
1302 SMLoc StartLoc = Parser.getTok().getLoc();
1303 if (getParser().parseExpression(Expr))
1304 return MatchOperand_NoMatch;
1305
1306 // For consistency with the GNU assembler, treat immediates as offsets
1307 // from ".".
1308 if (auto *CE = dyn_cast<MCConstantExpr>(Expr)) {
1309 int64_t Value = CE->getValue();
1310 if ((Value & 1) || Value < MinVal || Value > MaxVal) {
1311 Error(StartLoc, "offset out of range");
1312 return MatchOperand_ParseFail;
1313 }
1314 MCSymbol *Sym = Ctx.createTempSymbol();
1315 Out.EmitLabel(Sym);
1316 const MCExpr *Base = MCSymbolRefExpr::create(Sym, MCSymbolRefExpr::VK_None,
1317 Ctx);
1318 Expr = Value == 0 ? Base : MCBinaryExpr::createAdd(Base, Expr, Ctx);
1319 }
1320
1321 // Optionally match :tls_gdcall: or :tls_ldcall: followed by a TLS symbol.
1322 const MCExpr *Sym = nullptr;
1323 if (AllowTLS && getLexer().is(AsmToken::Colon)) {
1324 Parser.Lex();
1325
1326 if (Parser.getTok().isNot(AsmToken::Identifier)) {
1327 Error(Parser.getTok().getLoc(), "unexpected token");
1328 return MatchOperand_ParseFail;
1329 }
1330
1331 MCSymbolRefExpr::VariantKind Kind = MCSymbolRefExpr::VK_None;
1332 StringRef Name = Parser.getTok().getString();
1333 if (Name == "tls_gdcall")
1334 Kind = MCSymbolRefExpr::VK_TLSGD;
1335 else if (Name == "tls_ldcall")
1336 Kind = MCSymbolRefExpr::VK_TLSLDM;
1337 else {
1338 Error(Parser.getTok().getLoc(), "unknown TLS tag");
1339 return MatchOperand_ParseFail;
1340 }
1341 Parser.Lex();
1342
1343 if (Parser.getTok().isNot(AsmToken::Colon)) {
1344 Error(Parser.getTok().getLoc(), "unexpected token");
1345 return MatchOperand_ParseFail;
1346 }
1347 Parser.Lex();
1348
1349 if (Parser.getTok().isNot(AsmToken::Identifier)) {
1350 Error(Parser.getTok().getLoc(), "unexpected token");
1351 return MatchOperand_ParseFail;
1352 }
1353
1354 StringRef Identifier = Parser.getTok().getString();
1355 Sym = MCSymbolRefExpr::create(Ctx.getOrCreateSymbol(Identifier),
1356 Kind, Ctx);
1357 Parser.Lex();
1358 }
1359
1360 SMLoc EndLoc =
1361 SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1362
1363 if (AllowTLS)
1364 Operands.push_back(SystemZOperand::createImmTLS(Expr, Sym,
1365 StartLoc, EndLoc));
1366 else
1367 Operands.push_back(SystemZOperand::createImm(Expr, StartLoc, EndLoc));
1368
1369 return MatchOperand_Success;
1370}
1371
1372// Force static initialization.
1373extern "C" void LLVMInitializeSystemZAsmParser() {
1374 RegisterMCAsmParser<SystemZAsmParser> X(getTheSystemZTarget());
1375}