/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/include/llvm/CodeGen/SelectionDAGNodes.h

Bug Summary

File:	llvm/include/llvm/CodeGen/SelectionDAGNodes.h
Warning:	line 1114, column 10 Called C++ object pointer is null

Annotated Source Code

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clang -cc1 -cc1 -triple x86_64-pc-linux-gnu -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name SystemZISelLowering.cpp -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=cplusplus -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -analyzer-config-compatibility-mode=true -mrelocation-model pic -pic-level 2 -mframe-pointer=none -fmath-errno -fno-rounding-math -mconstructor-aliases -munwind-tables -target-cpu x86-64 -tune-cpu generic -debugger-tuning=gdb -ffunction-sections -fdata-sections -fcoverage-compilation-dir=/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/build-llvm/lib/Target/SystemZ -resource-dir /usr/lib/llvm-14/lib/clang/14.0.0 -D _DEBUG -D _GNU_SOURCE -D __STDC_CONSTANT_MACROS -D __STDC_FORMAT_MACROS -D __STDC_LIMIT_MACROS -I /build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/build-llvm/lib/Target/SystemZ -I /build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/SystemZ -I /build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/build-llvm/include -I /build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/include -D NDEBUG -U NDEBUG -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/10/../../../../include/c++/10 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/10/../../../../include/x86_64-linux-gnu/c++/10 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/10/../../../../include/c++/10/backward -internal-isystem /usr/lib/llvm-14/lib/clang/14.0.0/include -internal-isystem /usr/local/include -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/10/../../../../x86_64-linux-gnu/include -internal-externc-isystem /usr/include/x86_64-linux-gnu -internal-externc-isystem /include -internal-externc-isystem /usr/include -O2 -Wno-unused-parameter -Wwrite-strings -Wno-missing-field-initializers -Wno-long-long -Wno-maybe-uninitialized -Wno-class-memaccess -Wno-redundant-move -Wno-pessimizing-move -Wno-noexcept-type -Wno-comment -std=c++14 -fdeprecated-macro -fdebug-compilation-dir=/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/build-llvm/lib/Target/SystemZ -fdebug-prefix-map=/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0=. -ferror-limit 19 -fvisibility hidden -fvisibility-inlines-hidden -stack-protector 2 -fgnuc-version=4.2.1 -vectorize-loops -vectorize-slp -analyzer-output=html -analyzer-config stable-report-filename=true -faddrsig -D__GCC_HAVE_DWARF2_CFI_ASM=1 -o /tmp/scan-build-2021-08-28-193554-24367-1 -x c++ /build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp

/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp

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1//===-- SystemZISelLowering.cpp - SystemZ DAG lowering implementation -----===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements the SystemZTargetLowering class.
10//
11//===----------------------------------------------------------------------===//

13#include "SystemZISelLowering.h"
14#include "SystemZCallingConv.h"
15#include "SystemZConstantPoolValue.h"
16#include "SystemZMachineFunctionInfo.h"
17#include "SystemZTargetMachine.h"
18#include "llvm/CodeGen/CallingConvLower.h"
19#include "llvm/CodeGen/MachineInstrBuilder.h"
20#include "llvm/CodeGen/MachineRegisterInfo.h"
21#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
22#include "llvm/IR/IntrinsicInst.h"
23#include "llvm/IR/Intrinsics.h"
24#include "llvm/IR/IntrinsicsS390.h"
25#include "llvm/Support/CommandLine.h"
26#include "llvm/Support/KnownBits.h"
27#include <cctype>

29using namespace llvm;

31#define DEBUG_TYPE"systemz-lower" "systemz-lower"

33namespace {
34// Represents information about a comparison.
35struct Comparison {
Comparison(SDValue Op0In, SDValue Op1In, SDValue ChainIn)
  : Op0(Op0In), Op1(Op1In), Chain(ChainIn),
    Opcode(0), ICmpType(0), CCValid(0), CCMask(0) {}

// The operands to the comparison.
SDValue Op0, Op1;

// Chain if this is a strict floating-point comparison.
SDValue Chain;

// The opcode that should be used to compare Op0 and Op1.
unsigned Opcode;

// A SystemZICMP value.  Only used for integer comparisons.
unsigned ICmpType;

// The mask of CC values that Opcode can produce.
unsigned CCValid;

// The mask of CC values for which the original condition is true.
unsigned CCMask;
57};
58} // end anonymous namespace

60// Classify VT as either 32 or 64 bit.
61static bool is32Bit(EVT VT) {
switch (VT.getSimpleVT().SimpleTy) {
case MVT::i32:
  return true;
case MVT::i64:
  return false;
default:
  llvm_unreachable("Unsupported type")::llvm::llvm_unreachable_internal("Unsupported type", "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp"
, 68);
}
70}

72// Return a version of MachineOperand that can be safely used before the
73// final use.
74static MachineOperand earlyUseOperand(MachineOperand Op) {
if (Op.isReg())
  Op.setIsKill(false);
return Op;
78}

80SystemZTargetLowering::SystemZTargetLowering(const TargetMachine &TM,
                                           const SystemZSubtarget &STI)
  : TargetLowering(TM), Subtarget(STI) {
MVT PtrVT = MVT::getIntegerVT(8 * TM.getPointerSize(0));

// Set up the register classes.
if (Subtarget.hasHighWord())
  addRegisterClass(MVT::i32, &SystemZ::GRX32BitRegClass);
else
  addRegisterClass(MVT::i32, &SystemZ::GR32BitRegClass);
addRegisterClass(MVT::i64, &SystemZ::GR64BitRegClass);
if (!useSoftFloat()) {
  if (Subtarget.hasVector()) {
    addRegisterClass(MVT::f32, &SystemZ::VR32BitRegClass);
    addRegisterClass(MVT::f64, &SystemZ::VR64BitRegClass);
  } else {
    addRegisterClass(MVT::f32, &SystemZ::FP32BitRegClass);
    addRegisterClass(MVT::f64, &SystemZ::FP64BitRegClass);
  }
  if (Subtarget.hasVectorEnhancements1())
    addRegisterClass(MVT::f128, &SystemZ::VR128BitRegClass);
  else
    addRegisterClass(MVT::f128, &SystemZ::FP128BitRegClass);

  if (Subtarget.hasVector()) {
    addRegisterClass(MVT::v16i8, &SystemZ::VR128BitRegClass);
    addRegisterClass(MVT::v8i16, &SystemZ::VR128BitRegClass);
    addRegisterClass(MVT::v4i32, &SystemZ::VR128BitRegClass);
    addRegisterClass(MVT::v2i64, &SystemZ::VR128BitRegClass);
    addRegisterClass(MVT::v4f32, &SystemZ::VR128BitRegClass);
    addRegisterClass(MVT::v2f64, &SystemZ::VR128BitRegClass);
  }
}

// Compute derived properties from the register classes
computeRegisterProperties(Subtarget.getRegisterInfo());

// Set up special registers.
setStackPointerRegisterToSaveRestore(SystemZ::R15D);

// TODO: It may be better to default to latency-oriented scheduling, however
// LLVM's current latency-oriented scheduler can't handle physreg definitions
// such as SystemZ has with CC, so set this to the register-pressure
// scheduler, because it can.
setSchedulingPreference(Sched::RegPressure);

setBooleanContents(ZeroOrOneBooleanContent);
setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);

// Instructions are strings of 2-byte aligned 2-byte values.
setMinFunctionAlignment(Align(2));
// For performance reasons we prefer 16-byte alignment.
setPrefFunctionAlignment(Align(16));

// Handle operations that are handled in a similar way for all types.
for (unsigned I = MVT::FIRST_INTEGER_VALUETYPE;
     I <= MVT::LAST_FP_VALUETYPE;
     ++I) {
  MVT VT = MVT::SimpleValueType(I);
  if (isTypeLegal(VT)) {
    // Lower SET_CC into an IPM-based sequence.
    setOperationAction(ISD::SETCC, VT, Custom);
    setOperationAction(ISD::STRICT_FSETCC, VT, Custom);
    setOperationAction(ISD::STRICT_FSETCCS, VT, Custom);

    // Expand SELECT(C, A, B) into SELECT_CC(X, 0, A, B, NE).
    setOperationAction(ISD::SELECT, VT, Expand);

    // Lower SELECT_CC and BR_CC into separate comparisons and branches.
    setOperationAction(ISD::SELECT_CC, VT, Custom);
    setOperationAction(ISD::BR_CC,     VT, Custom);
  }
}

// Expand jump table branches as address arithmetic followed by an
// indirect jump.
setOperationAction(ISD::BR_JT, MVT::Other, Expand);

// Expand BRCOND into a BR_CC (see above).
setOperationAction(ISD::BRCOND, MVT::Other, Expand);

// Handle integer types.
for (unsigned I = MVT::FIRST_INTEGER_VALUETYPE;
     I <= MVT::LAST_INTEGER_VALUETYPE;
     ++I) {
  MVT VT = MVT::SimpleValueType(I);
  if (isTypeLegal(VT)) {
    setOperationAction(ISD::ABS, VT, Legal);

    // Expand individual DIV and REMs into DIVREMs.
    setOperationAction(ISD::SDIV, VT, Expand);
    setOperationAction(ISD::UDIV, VT, Expand);
    setOperationAction(ISD::SREM, VT, Expand);
    setOperationAction(ISD::UREM, VT, Expand);
    setOperationAction(ISD::SDIVREM, VT, Custom);
    setOperationAction(ISD::UDIVREM, VT, Custom);

    // Support addition/subtraction with overflow.
    setOperationAction(ISD::SADDO, VT, Custom);
    setOperationAction(ISD::SSUBO, VT, Custom);

    // Support addition/subtraction with carry.
    setOperationAction(ISD::UADDO, VT, Custom);
    setOperationAction(ISD::USUBO, VT, Custom);

    // Support carry in as value rather than glue.
    setOperationAction(ISD::ADDCARRY, VT, Custom);
    setOperationAction(ISD::SUBCARRY, VT, Custom);

    // Lower ATOMIC_LOAD and ATOMIC_STORE into normal volatile loads and
    // stores, putting a serialization instruction after the stores.
    setOperationAction(ISD::ATOMIC_LOAD,  VT, Custom);
    setOperationAction(ISD::ATOMIC_STORE, VT, Custom);

    // Lower ATOMIC_LOAD_SUB into ATOMIC_LOAD_ADD if LAA and LAAG are
    // available, or if the operand is constant.
    setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);

    // Use POPCNT on z196 and above.
    if (Subtarget.hasPopulationCount())
      setOperationAction(ISD::CTPOP, VT, Custom);
    else
      setOperationAction(ISD::CTPOP, VT, Expand);

    // No special instructions for these.
    setOperationAction(ISD::CTTZ,            VT, Expand);
    setOperationAction(ISD::ROTR,            VT, Expand);

    // Use *MUL_LOHI where possible instead of MULH*.
    setOperationAction(ISD::MULHS, VT, Expand);
    setOperationAction(ISD::MULHU, VT, Expand);
    setOperationAction(ISD::SMUL_LOHI, VT, Custom);
    setOperationAction(ISD::UMUL_LOHI, VT, Custom);

    // Only z196 and above have native support for conversions to unsigned.
    // On z10, promoting to i64 doesn't generate an inexact condition for
    // values that are outside the i32 range but in the i64 range, so use
    // the default expansion.
    if (!Subtarget.hasFPExtension())
      setOperationAction(ISD::FP_TO_UINT, VT, Expand);

    // Mirror those settings for STRICT_FP_TO_[SU]INT.  Note that these all
    // default to Expand, so need to be modified to Legal where appropriate.
    setOperationAction(ISD::STRICT_FP_TO_SINT, VT, Legal);
    if (Subtarget.hasFPExtension())
      setOperationAction(ISD::STRICT_FP_TO_UINT, VT, Legal);

    // And similarly for STRICT_[SU]INT_TO_FP.
    setOperationAction(ISD::STRICT_SINT_TO_FP, VT, Legal);
    if (Subtarget.hasFPExtension())
      setOperationAction(ISD::STRICT_UINT_TO_FP, VT, Legal);
  }
}

// Type legalization will convert 8- and 16-bit atomic operations into
// forms that operate on i32s (but still keeping the original memory VT).
// Lower them into full i32 operations.
setOperationAction(ISD::ATOMIC_SWAP,      MVT::i32, Custom);
setOperationAction(ISD::ATOMIC_LOAD_ADD,  MVT::i32, Custom);
setOperationAction(ISD::ATOMIC_LOAD_SUB,  MVT::i32, Custom);
setOperationAction(ISD::ATOMIC_LOAD_AND,  MVT::i32, Custom);
setOperationAction(ISD::ATOMIC_LOAD_OR,   MVT::i32, Custom);
setOperationAction(ISD::ATOMIC_LOAD_XOR,  MVT::i32, Custom);
setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i32, Custom);
setOperationAction(ISD::ATOMIC_LOAD_MIN,  MVT::i32, Custom);
setOperationAction(ISD::ATOMIC_LOAD_MAX,  MVT::i32, Custom);
setOperationAction(ISD::ATOMIC_LOAD_UMIN, MVT::i32, Custom);
setOperationAction(ISD::ATOMIC_LOAD_UMAX, MVT::i32, Custom);

// Even though i128 is not a legal type, we still need to custom lower
// the atomic operations in order to exploit SystemZ instructions.
setOperationAction(ISD::ATOMIC_LOAD,     MVT::i128, Custom);
setOperationAction(ISD::ATOMIC_STORE,    MVT::i128, Custom);

// We can use the CC result of compare-and-swap to implement
// the "success" result of ATOMIC_CMP_SWAP_WITH_SUCCESS.
setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, MVT::i32, Custom);
setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, MVT::i64, Custom);
setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, MVT::i128, Custom);

setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom);

// Traps are legal, as we will convert them to "j .+2".
setOperationAction(ISD::TRAP, MVT::Other, Legal);

// z10 has instructions for signed but not unsigned FP conversion.
// Handle unsigned 32-bit types as signed 64-bit types.
if (!Subtarget.hasFPExtension()) {
  setOperationAction(ISD::UINT_TO_FP, MVT::i32, Promote);
  setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
  setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::i32, Promote);
  setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::i64, Expand);
}

// We have native support for a 64-bit CTLZ, via FLOGR.
setOperationAction(ISD::CTLZ, MVT::i32, Promote);
setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Promote);
setOperationAction(ISD::CTLZ, MVT::i64, Legal);

// On z15 we have native support for a 64-bit CTPOP.
if (Subtarget.hasMiscellaneousExtensions3()) {
  setOperationAction(ISD::CTPOP, MVT::i32, Promote);
  setOperationAction(ISD::CTPOP, MVT::i64, Legal);
}

// Give LowerOperation the chance to replace 64-bit ORs with subregs.
setOperationAction(ISD::OR, MVT::i64, Custom);

// Expand 128 bit shifts without using a libcall.
setOperationAction(ISD::SRL_PARTS, MVT::i64, Expand);
setOperationAction(ISD::SHL_PARTS, MVT::i64, Expand);
setOperationAction(ISD::SRA_PARTS, MVT::i64, Expand);
setLibcallName(RTLIB::SRL_I128, nullptr);
setLibcallName(RTLIB::SHL_I128, nullptr);
setLibcallName(RTLIB::SRA_I128, nullptr);

// We have native instructions for i8, i16 and i32 extensions, but not i1.
setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
for (MVT VT : MVT::integer_valuetypes()) {
  setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
  setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote);
  setLoadExtAction(ISD::EXTLOAD,  VT, MVT::i1, Promote);
}

// Handle the various types of symbolic address.
setOperationAction(ISD::ConstantPool,     PtrVT, Custom);
setOperationAction(ISD::GlobalAddress,    PtrVT, Custom);
setOperationAction(ISD::GlobalTLSAddress, PtrVT, Custom);
setOperationAction(ISD::BlockAddress,     PtrVT, Custom);
setOperationAction(ISD::JumpTable,        PtrVT, Custom);

// We need to handle dynamic allocations specially because of the
// 160-byte area at the bottom of the stack.
setOperationAction(ISD::DYNAMIC_STACKALLOC, PtrVT, Custom);
setOperationAction(ISD::GET_DYNAMIC_AREA_OFFSET, PtrVT, Custom);

// Use custom expanders so that we can force the function to use
// a frame pointer.
setOperationAction(ISD::STACKSAVE,    MVT::Other, Custom);
setOperationAction(ISD::STACKRESTORE, MVT::Other, Custom);

// Handle prefetches with PFD or PFDRL.
setOperationAction(ISD::PREFETCH, MVT::Other, Custom);

for (MVT VT : MVT::fixedlen_vector_valuetypes()) {
  // Assume by default that all vector operations need to be expanded.
  for (unsigned Opcode = 0; Opcode < ISD::BUILTIN_OP_END; ++Opcode)
    if (getOperationAction(Opcode, VT) == Legal)
      setOperationAction(Opcode, VT, Expand);

  // Likewise all truncating stores and extending loads.
  for (MVT InnerVT : MVT::fixedlen_vector_valuetypes()) {
    setTruncStoreAction(VT, InnerVT, Expand);
    setLoadExtAction(ISD::SEXTLOAD, VT, InnerVT, Expand);
    setLoadExtAction(ISD::ZEXTLOAD, VT, InnerVT, Expand);
    setLoadExtAction(ISD::EXTLOAD, VT, InnerVT, Expand);
  }

  if (isTypeLegal(VT)) {
    // These operations are legal for anything that can be stored in a
    // vector register, even if there is no native support for the format
    // as such.  In particular, we can do these for v4f32 even though there
    // are no specific instructions for that format.
    setOperationAction(ISD::LOAD, VT, Legal);
    setOperationAction(ISD::STORE, VT, Legal);
    setOperationAction(ISD::VSELECT, VT, Legal);
    setOperationAction(ISD::BITCAST, VT, Legal);
    setOperationAction(ISD::UNDEF, VT, Legal);

    // Likewise, except that we need to replace the nodes with something
    // more specific.
    setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
    setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
  }
}

// Handle integer vector types.
for (MVT VT : MVT::integer_fixedlen_vector_valuetypes()) {
  if (isTypeLegal(VT)) {
    // These operations have direct equivalents.
    setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Legal);
    setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Legal);
    setOperationAction(ISD::ADD, VT, Legal);
    setOperationAction(ISD::SUB, VT, Legal);
    if (VT != MVT::v2i64)
      setOperationAction(ISD::MUL, VT, Legal);
    setOperationAction(ISD::ABS, VT, Legal);
    setOperationAction(ISD::AND, VT, Legal);
    setOperationAction(ISD::OR, VT, Legal);
    setOperationAction(ISD::XOR, VT, Legal);
    if (Subtarget.hasVectorEnhancements1())
      setOperationAction(ISD::CTPOP, VT, Legal);
    else
      setOperationAction(ISD::CTPOP, VT, Custom);
    setOperationAction(ISD::CTTZ, VT, Legal);
    setOperationAction(ISD::CTLZ, VT, Legal);

    // Convert a GPR scalar to a vector by inserting it into element 0.
    setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);

    // Use a series of unpacks for extensions.
    setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, VT, Custom);
    setOperationAction(ISD::ZERO_EXTEND_VECTOR_INREG, VT, Custom);

    // Detect shifts by a scalar amount and convert them into
    // V*_BY_SCALAR.
    setOperationAction(ISD::SHL, VT, Custom);
    setOperationAction(ISD::SRA, VT, Custom);
    setOperationAction(ISD::SRL, VT, Custom);

    // At present ROTL isn't matched by DAGCombiner.  ROTR should be
    // converted into ROTL.
    setOperationAction(ISD::ROTL, VT, Expand);
    setOperationAction(ISD::ROTR, VT, Expand);

    // Map SETCCs onto one of VCE, VCH or VCHL, swapping the operands
    // and inverting the result as necessary.
    setOperationAction(ISD::SETCC, VT, Custom);
    setOperationAction(ISD::STRICT_FSETCC, VT, Custom);
    if (Subtarget.hasVectorEnhancements1())
      setOperationAction(ISD::STRICT_FSETCCS, VT, Custom);
  }
}

if (Subtarget.hasVector()) {
  // There should be no need to check for float types other than v2f64
  // since <2 x f32> isn't a legal type.
  setOperationAction(ISD::FP_TO_SINT, MVT::v2i64, Legal);
  setOperationAction(ISD::FP_TO_SINT, MVT::v2f64, Legal);
  setOperationAction(ISD::FP_TO_UINT, MVT::v2i64, Legal);
  setOperationAction(ISD::FP_TO_UINT, MVT::v2f64, Legal);
  setOperationAction(ISD::SINT_TO_FP, MVT::v2i64, Legal);
  setOperationAction(ISD::SINT_TO_FP, MVT::v2f64, Legal);
  setOperationAction(ISD::UINT_TO_FP, MVT::v2i64, Legal);
  setOperationAction(ISD::UINT_TO_FP, MVT::v2f64, Legal);

  setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::v2i64, Legal);
  setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::v2f64, Legal);
  setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::v2i64, Legal);
  setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::v2f64, Legal);
  setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::v2i64, Legal);
  setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::v2f64, Legal);
  setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::v2i64, Legal);
  setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::v2f64, Legal);
}

if (Subtarget.hasVectorEnhancements2()) {
  setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
  setOperationAction(ISD::FP_TO_SINT, MVT::v4f32, Legal);
  setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
  setOperationAction(ISD::FP_TO_UINT, MVT::v4f32, Legal);
  setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
  setOperationAction(ISD::SINT_TO_FP, MVT::v4f32, Legal);
  setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
  setOperationAction(ISD::UINT_TO_FP, MVT::v4f32, Legal);

  setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::v4i32, Legal);
  setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::v4f32, Legal);
  setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::v4i32, Legal);
  setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::v4f32, Legal);
  setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::v4i32, Legal);
  setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::v4f32, Legal);
  setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::v4i32, Legal);
  setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::v4f32, Legal);
}

// Handle floating-point types.
for (unsigned I = MVT::FIRST_FP_VALUETYPE;
     I <= MVT::LAST_FP_VALUETYPE;
     ++I) {
  MVT VT = MVT::SimpleValueType(I);
  if (isTypeLegal(VT)) {
    // We can use FI for FRINT.
    setOperationAction(ISD::FRINT, VT, Legal);

    // We can use the extended form of FI for other rounding operations.
    if (Subtarget.hasFPExtension()) {
      setOperationAction(ISD::FNEARBYINT, VT, Legal);
      setOperationAction(ISD::FFLOOR, VT, Legal);
      setOperationAction(ISD::FCEIL, VT, Legal);
      setOperationAction(ISD::FTRUNC, VT, Legal);
      setOperationAction(ISD::FROUND, VT, Legal);
    }

    // No special instructions for these.
    setOperationAction(ISD::FSIN, VT, Expand);
    setOperationAction(ISD::FCOS, VT, Expand);
    setOperationAction(ISD::FSINCOS, VT, Expand);
    setOperationAction(ISD::FREM, VT, Expand);
    setOperationAction(ISD::FPOW, VT, Expand);

    // Handle constrained floating-point operations.
    setOperationAction(ISD::STRICT_FADD, VT, Legal);
    setOperationAction(ISD::STRICT_FSUB, VT, Legal);
    setOperationAction(ISD::STRICT_FMUL, VT, Legal);
    setOperationAction(ISD::STRICT_FDIV, VT, Legal);
    setOperationAction(ISD::STRICT_FMA, VT, Legal);
    setOperationAction(ISD::STRICT_FSQRT, VT, Legal);
    setOperationAction(ISD::STRICT_FRINT, VT, Legal);
    setOperationAction(ISD::STRICT_FP_ROUND, VT, Legal);
    setOperationAction(ISD::STRICT_FP_EXTEND, VT, Legal);
    if (Subtarget.hasFPExtension()) {
      setOperationAction(ISD::STRICT_FNEARBYINT, VT, Legal);
      setOperationAction(ISD::STRICT_FFLOOR, VT, Legal);
      setOperationAction(ISD::STRICT_FCEIL, VT, Legal);
      setOperationAction(ISD::STRICT_FROUND, VT, Legal);
      setOperationAction(ISD::STRICT_FTRUNC, VT, Legal);
    }
  }
}

// Handle floating-point vector types.
if (Subtarget.hasVector()) {
  // Scalar-to-vector conversion is just a subreg.
  setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Legal);
  setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2f64, Legal);

  // Some insertions and extractions can be done directly but others
  // need to go via integers.
  setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
  setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
  setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
  setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);

  // These operations have direct equivalents.
  setOperationAction(ISD::FADD, MVT::v2f64, Legal);
  setOperationAction(ISD::FNEG, MVT::v2f64, Legal);
  setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
  setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
  setOperationAction(ISD::FMA, MVT::v2f64, Legal);
  setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
  setOperationAction(ISD::FABS, MVT::v2f64, Legal);
  setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
  setOperationAction(ISD::FRINT, MVT::v2f64, Legal);
  setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal);
  setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
  setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
  setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
  setOperationAction(ISD::FROUND, MVT::v2f64, Legal);

  // Handle constrained floating-point operations.
  setOperationAction(ISD::STRICT_FADD, MVT::v2f64, Legal);
  setOperationAction(ISD::STRICT_FSUB, MVT::v2f64, Legal);
  setOperationAction(ISD::STRICT_FMUL, MVT::v2f64, Legal);
  setOperationAction(ISD::STRICT_FMA, MVT::v2f64, Legal);
  setOperationAction(ISD::STRICT_FDIV, MVT::v2f64, Legal);
  setOperationAction(ISD::STRICT_FSQRT, MVT::v2f64, Legal);
  setOperationAction(ISD::STRICT_FRINT, MVT::v2f64, Legal);
  setOperationAction(ISD::STRICT_FNEARBYINT, MVT::v2f64, Legal);
  setOperationAction(ISD::STRICT_FFLOOR, MVT::v2f64, Legal);
  setOperationAction(ISD::STRICT_FCEIL, MVT::v2f64, Legal);
  setOperationAction(ISD::STRICT_FTRUNC, MVT::v2f64, Legal);
  setOperationAction(ISD::STRICT_FROUND, MVT::v2f64, Legal);
}

// The vector enhancements facility 1 has instructions for these.
if (Subtarget.hasVectorEnhancements1()) {
  setOperationAction(ISD::FADD, MVT::v4f32, Legal);
  setOperationAction(ISD::FNEG, MVT::v4f32, Legal);
  setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
  setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
  setOperationAction(ISD::FMA, MVT::v4f32, Legal);
  setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
  setOperationAction(ISD::FABS, MVT::v4f32, Legal);
  setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
  setOperationAction(ISD::FRINT, MVT::v4f32, Legal);
  setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
  setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
  setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
  setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
  setOperationAction(ISD::FROUND, MVT::v4f32, Legal);

  setOperationAction(ISD::FMAXNUM, MVT::f64, Legal);
  setOperationAction(ISD::FMAXIMUM, MVT::f64, Legal);
  setOperationAction(ISD::FMINNUM, MVT::f64, Legal);
  setOperationAction(ISD::FMINIMUM, MVT::f64, Legal);

  setOperationAction(ISD::FMAXNUM, MVT::v2f64, Legal);
  setOperationAction(ISD::FMAXIMUM, MVT::v2f64, Legal);
  setOperationAction(ISD::FMINNUM, MVT::v2f64, Legal);
  setOperationAction(ISD::FMINIMUM, MVT::v2f64, Legal);

  setOperationAction(ISD::FMAXNUM, MVT::f32, Legal);
  setOperationAction(ISD::FMAXIMUM, MVT::f32, Legal);
  setOperationAction(ISD::FMINNUM, MVT::f32, Legal);
  setOperationAction(ISD::FMINIMUM, MVT::f32, Legal);

  setOperationAction(ISD::FMAXNUM, MVT::v4f32, Legal);
  setOperationAction(ISD::FMAXIMUM, MVT::v4f32, Legal);
  setOperationAction(ISD::FMINNUM, MVT::v4f32, Legal);
  setOperationAction(ISD::FMINIMUM, MVT::v4f32, Legal);

  setOperationAction(ISD::FMAXNUM, MVT::f128, Legal);
  setOperationAction(ISD::FMAXIMUM, MVT::f128, Legal);
  setOperationAction(ISD::FMINNUM, MVT::f128, Legal);
  setOperationAction(ISD::FMINIMUM, MVT::f128, Legal);

  // Handle constrained floating-point operations.
  setOperationAction(ISD::STRICT_FADD, MVT::v4f32, Legal);
  setOperationAction(ISD::STRICT_FSUB, MVT::v4f32, Legal);
  setOperationAction(ISD::STRICT_FMUL, MVT::v4f32, Legal);
  setOperationAction(ISD::STRICT_FMA, MVT::v4f32, Legal);
  setOperationAction(ISD::STRICT_FDIV, MVT::v4f32, Legal);
  setOperationAction(ISD::STRICT_FSQRT, MVT::v4f32, Legal);
  setOperationAction(ISD::STRICT_FRINT, MVT::v4f32, Legal);
  setOperationAction(ISD::STRICT_FNEARBYINT, MVT::v4f32, Legal);
  setOperationAction(ISD::STRICT_FFLOOR, MVT::v4f32, Legal);
  setOperationAction(ISD::STRICT_FCEIL, MVT::v4f32, Legal);
  setOperationAction(ISD::STRICT_FROUND, MVT::v4f32, Legal);
  setOperationAction(ISD::STRICT_FTRUNC, MVT::v4f32, Legal);
  for (auto VT : { MVT::f32, MVT::f64, MVT::f128,
                   MVT::v4f32, MVT::v2f64 }) {
    setOperationAction(ISD::STRICT_FMAXNUM, VT, Legal);
    setOperationAction(ISD::STRICT_FMINNUM, VT, Legal);
    setOperationAction(ISD::STRICT_FMAXIMUM, VT, Legal);
    setOperationAction(ISD::STRICT_FMINIMUM, VT, Legal);
  }
}

// We only have fused f128 multiply-addition on vector registers.
if (!Subtarget.hasVectorEnhancements1()) {
  setOperationAction(ISD::FMA, MVT::f128, Expand);
  setOperationAction(ISD::STRICT_FMA, MVT::f128, Expand);
}

// We don't have a copysign instruction on vector registers.
if (Subtarget.hasVectorEnhancements1())
  setOperationAction(ISD::FCOPYSIGN, MVT::f128, Expand);

// Needed so that we don't try to implement f128 constant loads using
// a load-and-extend of a f80 constant (in cases where the constant
// would fit in an f80).
for (MVT VT : MVT::fp_valuetypes())
  setLoadExtAction(ISD::EXTLOAD, VT, MVT::f80, Expand);

// We don't have extending load instruction on vector registers.
if (Subtarget.hasVectorEnhancements1()) {
  setLoadExtAction(ISD::EXTLOAD, MVT::f128, MVT::f32, Expand);
  setLoadExtAction(ISD::EXTLOAD, MVT::f128, MVT::f64, Expand);
}

// Floating-point truncation and stores need to be done separately.
setTruncStoreAction(MVT::f64,  MVT::f32, Expand);
setTruncStoreAction(MVT::f128, MVT::f32, Expand);
setTruncStoreAction(MVT::f128, MVT::f64, Expand);

// We have 64-bit FPR<->GPR moves, but need special handling for
// 32-bit forms.
if (!Subtarget.hasVector()) {
  setOperationAction(ISD::BITCAST, MVT::i32, Custom);
  setOperationAction(ISD::BITCAST, MVT::f32, Custom);
}

// VASTART and VACOPY need to deal with the SystemZ-specific varargs
// structure, but VAEND is a no-op.
setOperationAction(ISD::VASTART, MVT::Other, Custom);
setOperationAction(ISD::VACOPY,  MVT::Other, Custom);
setOperationAction(ISD::VAEND,   MVT::Other, Expand);

// Codes for which we want to perform some z-specific combinations.
setTargetDAGCombine(ISD::ZERO_EXTEND);
setTargetDAGCombine(ISD::SIGN_EXTEND);
setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
setTargetDAGCombine(ISD::LOAD);
setTargetDAGCombine(ISD::STORE);
setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
setTargetDAGCombine(ISD::FP_ROUND);
setTargetDAGCombine(ISD::STRICT_FP_ROUND);
setTargetDAGCombine(ISD::FP_EXTEND);
setTargetDAGCombine(ISD::SINT_TO_FP);
setTargetDAGCombine(ISD::UINT_TO_FP);
setTargetDAGCombine(ISD::STRICT_FP_EXTEND);
setTargetDAGCombine(ISD::BSWAP);
setTargetDAGCombine(ISD::SDIV);
setTargetDAGCombine(ISD::UDIV);
setTargetDAGCombine(ISD::SREM);
setTargetDAGCombine(ISD::UREM);
setTargetDAGCombine(ISD::INTRINSIC_VOID);
setTargetDAGCombine(ISD::INTRINSIC_W_CHAIN);

// Handle intrinsics.
setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);

// We want to use MVC in preference to even a single load/store pair.
MaxStoresPerMemcpy = 0;
MaxStoresPerMemcpyOptSize = 0;

// The main memset sequence is a byte store followed by an MVC.
// Two STC or MV..I stores win over that, but the kind of fused stores
// generated by target-independent code don't when the byte value is
// variable.  E.g.  "STC <reg>;MHI <reg>,257;STH <reg>" is not better
// than "STC;MVC".  Handle the choice in target-specific code instead.
MaxStoresPerMemset = 0;
MaxStoresPerMemsetOptSize = 0;

// Default to having -disable-strictnode-mutation on
IsStrictFPEnabled = true;
679}

681bool SystemZTargetLowering::useSoftFloat() const {
return Subtarget.hasSoftFloat();
683}

685EVT SystemZTargetLowering::getSetCCResultType(const DataLayout &DL,
                                            LLVMContext &, EVT VT) const {
if (!VT.isVector())
  return MVT::i32;
return VT.changeVectorElementTypeToInteger();
690}

692bool SystemZTargetLowering::isFMAFasterThanFMulAndFAdd(
  const MachineFunction &MF, EVT VT) const {
VT = VT.getScalarType();

if (!VT.isSimple())
  return false;

switch (VT.getSimpleVT().SimpleTy) {
case MVT::f32:
case MVT::f64:
  return true;
case MVT::f128:
  return Subtarget.hasVectorEnhancements1();
default:
  break;
}

return false;
710}

712// Return true if the constant can be generated with a vector instruction,
713// such as VGM, VGMB or VREPI.
714bool SystemZVectorConstantInfo::isVectorConstantLegal(
  const SystemZSubtarget &Subtarget) {
const SystemZInstrInfo *TII =
    static_cast<const SystemZInstrInfo *>(Subtarget.getInstrInfo());
if (!Subtarget.hasVector() ||
    (isFP128 && !Subtarget.hasVectorEnhancements1()))
  return false;

// Try using VECTOR GENERATE BYTE MASK.  This is the architecturally-
// preferred way of creating all-zero and all-one vectors so give it
// priority over other methods below.
unsigned Mask = 0;
unsigned I = 0;
for (; I < SystemZ::VectorBytes; ++I) {
  uint64_t Byte = IntBits.lshr(I * 8).trunc(8).getZExtValue();
  if (Byte == 0xff)
    Mask |= 1ULL << I;
  else if (Byte != 0)
    break;
}
if (I == SystemZ::VectorBytes) {
  Opcode = SystemZISD::BYTE_MASK;
  OpVals.push_back(Mask);
  VecVT = MVT::getVectorVT(MVT::getIntegerVT(8), 16);
  return true;
}

if (SplatBitSize > 64)
  return false;

auto tryValue = [&](uint64_t Value) -> bool {
  // Try VECTOR REPLICATE IMMEDIATE
  int64_t SignedValue = SignExtend64(Value, SplatBitSize);
  if (isInt<16>(SignedValue)) {
    OpVals.push_back(((unsigned) SignedValue));
    Opcode = SystemZISD::REPLICATE;
    VecVT = MVT::getVectorVT(MVT::getIntegerVT(SplatBitSize),
                             SystemZ::VectorBits / SplatBitSize);
    return true;
  }
  // Try VECTOR GENERATE MASK
  unsigned Start, End;
  if (TII->isRxSBGMask(Value, SplatBitSize, Start, End)) {
    // isRxSBGMask returns the bit numbers for a full 64-bit value, with 0
    // denoting 1 << 63 and 63 denoting 1.  Convert them to bit numbers for
    // an SplatBitSize value, so that 0 denotes 1 << (SplatBitSize-1).
    OpVals.push_back(Start - (64 - SplatBitSize));
    OpVals.push_back(End - (64 - SplatBitSize));
    Opcode = SystemZISD::ROTATE_MASK;
    VecVT = MVT::getVectorVT(MVT::getIntegerVT(SplatBitSize),
                             SystemZ::VectorBits / SplatBitSize);
    return true;
  }
  return false;
};

// First try assuming that any undefined bits above the highest set bit
// and below the lowest set bit are 1s.  This increases the likelihood of
// being able to use a sign-extended element value in VECTOR REPLICATE
// IMMEDIATE or a wraparound mask in VECTOR GENERATE MASK.
uint64_t SplatBitsZ = SplatBits.getZExtValue();
uint64_t SplatUndefZ = SplatUndef.getZExtValue();
uint64_t Lower =
    (SplatUndefZ & ((uint64_t(1) << findFirstSet(SplatBitsZ)) - 1));
uint64_t Upper =
    (SplatUndefZ & ~((uint64_t(1) << findLastSet(SplatBitsZ)) - 1));
if (tryValue(SplatBitsZ | Upper | Lower))
  return true;

// Now try assuming that any undefined bits between the first and
// last defined set bits are set.  This increases the chances of
// using a non-wraparound mask.
uint64_t Middle = SplatUndefZ & ~Upper & ~Lower;
return tryValue(SplatBitsZ | Middle);
788}

790SystemZVectorConstantInfo::SystemZVectorConstantInfo(APFloat FPImm) {
IntBits = FPImm.bitcastToAPInt().zextOrSelf(128);
isFP128 = (&FPImm.getSemantics() == &APFloat::IEEEquad());
SplatBits = FPImm.bitcastToAPInt();
unsigned Width = SplatBits.getBitWidth();
IntBits <<= (SystemZ::VectorBits - Width);

// Find the smallest splat.
while (Width > 8) {
  unsigned HalfSize = Width / 2;
  APInt HighValue = SplatBits.lshr(HalfSize).trunc(HalfSize);
  APInt LowValue = SplatBits.trunc(HalfSize);

  // If the two halves do not match, stop here.
  if (HighValue != LowValue || 8 > HalfSize)
    break;

  SplatBits = HighValue;
  Width = HalfSize;
}
SplatUndef = 0;
SplatBitSize = Width;
812}

814SystemZVectorConstantInfo::SystemZVectorConstantInfo(BuildVectorSDNode *BVN) {
assert(BVN->isConstant() && "Expected a constant BUILD_VECTOR")(static_cast <bool> (BVN->isConstant() && "Expected a constant BUILD_VECTOR"
) ? void (0) : __assert_fail ("BVN->isConstant() && \"Expected a constant BUILD_VECTOR\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp"
, 815, __extension__ __PRETTY_FUNCTION__));
bool HasAnyUndefs;

// Get IntBits by finding the 128 bit splat.
BVN->isConstantSplat(IntBits, SplatUndef, SplatBitSize, HasAnyUndefs, 128,
                     true);

// Get SplatBits by finding the 8 bit or greater splat.
BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs, 8,
                     true);
825}

827bool SystemZTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT,
                                       bool ForCodeSize) const {
// We can load zero using LZ?R and negative zero using LZ?R;LC?BR.
if (Imm.isZero() || Imm.isNegZero())
  return true;

return SystemZVectorConstantInfo(Imm).isVectorConstantLegal(Subtarget);
834}

836/// Returns true if stack probing through inline assembly is requested.
837bool SystemZTargetLowering::hasInlineStackProbe(MachineFunction &MF) const {
// If the function specifically requests inline stack probes, emit them.
if (MF.getFunction().hasFnAttribute("probe-stack"))
  return MF.getFunction().getFnAttribute("probe-stack").getValueAsString() ==
         "inline-asm";
return false;
843}

845bool SystemZTargetLowering::isLegalICmpImmediate(int64_t Imm) const {
// We can use CGFI or CLGFI.
return isInt<32>(Imm) || isUInt<32>(Imm);
848}

850bool SystemZTargetLowering::isLegalAddImmediate(int64_t Imm) const {
// We can use ALGFI or SLGFI.
return isUInt<32>(Imm) || isUInt<32>(-Imm);
853}

855bool SystemZTargetLowering::allowsMisalignedMemoryAccesses(
  EVT VT, unsigned, Align, MachineMemOperand::Flags, bool *Fast) const {
// Unaligned accesses should never be slower than the expanded version.
// We check specifically for aligned accesses in the few cases where
// they are required.
if (Fast)
  *Fast = true;
return true;
863}

865// Information about the addressing mode for a memory access.
866struct AddressingMode {
// True if a long displacement is supported.
bool LongDisplacement;

// True if use of index register is supported.
bool IndexReg;

AddressingMode(bool LongDispl, bool IdxReg) :
  LongDisplacement(LongDispl), IndexReg(IdxReg) {}
875};

877// Return the desired addressing mode for a Load which has only one use (in
878// the same block) which is a Store.
879static AddressingMode getLoadStoreAddrMode(bool HasVector,
                                        Type *Ty) {
// With vector support a Load->Store combination may be combined to either
// an MVC or vector operations and it seems to work best to allow the
// vector addressing mode.
if (HasVector)
  return AddressingMode(false/*LongDispl*/, true/*IdxReg*/);

// Otherwise only the MVC case is special.
bool MVC = Ty->isIntegerTy(8);
return AddressingMode(!MVC/*LongDispl*/, !MVC/*IdxReg*/);
890}

892// Return the addressing mode which seems most desirable given an LLVM
893// Instruction pointer.
894static AddressingMode
895supportedAddressingMode(Instruction *I, bool HasVector) {
if (IntrinsicInst *II = dyn_cast<IntrinsicInst>(I)) {
  switch (II->getIntrinsicID()) {
  default: break;
  case Intrinsic::memset:
  case Intrinsic::memmove:
  case Intrinsic::memcpy:
    return AddressingMode(false/*LongDispl*/, false/*IdxReg*/);
  }
}

if (isa<LoadInst>(I) && I->hasOneUse()) {
  auto *SingleUser = cast<Instruction>(*I->user_begin());
  if (SingleUser->getParent() == I->getParent()) {
    if (isa<ICmpInst>(SingleUser)) {
      if (auto *C = dyn_cast<ConstantInt>(SingleUser->getOperand(1)))
        if (C->getBitWidth() <= 64 &&
            (isInt<16>(C->getSExtValue()) || isUInt<16>(C->getZExtValue())))
          // Comparison of memory with 16 bit signed / unsigned immediate
          return AddressingMode(false/*LongDispl*/, false/*IdxReg*/);
    } else if (isa<StoreInst>(SingleUser))
      // Load->Store
      return getLoadStoreAddrMode(HasVector, I->getType());
  }
} else if (auto *StoreI = dyn_cast<StoreInst>(I)) {
  if (auto *LoadI = dyn_cast<LoadInst>(StoreI->getValueOperand()))
    if (LoadI->hasOneUse() && LoadI->getParent() == I->getParent())
      // Load->Store
      return getLoadStoreAddrMode(HasVector, LoadI->getType());
}

if (HasVector && (isa<LoadInst>(I) || isa<StoreInst>(I))) {

  // * Use LDE instead of LE/LEY for z13 to avoid partial register
  //   dependencies (LDE only supports small offsets).
  // * Utilize the vector registers to hold floating point
  //   values (vector load / store instructions only support small
  //   offsets).

  Type *MemAccessTy = (isa<LoadInst>(I) ? I->getType() :
                       I->getOperand(0)->getType());
  bool IsFPAccess = MemAccessTy->isFloatingPointTy();
  bool IsVectorAccess = MemAccessTy->isVectorTy();

  // A store of an extracted vector element will be combined into a VSTE type
  // instruction.
  if (!IsVectorAccess && isa<StoreInst>(I)) {
    Value *DataOp = I->getOperand(0);
    if (isa<ExtractElementInst>(DataOp))
      IsVectorAccess = true;
  }

  // A load which gets inserted into a vector element will be combined into a
  // VLE type instruction.
  if (!IsVectorAccess && isa<LoadInst>(I) && I->hasOneUse()) {
    User *LoadUser = *I->user_begin();
    if (isa<InsertElementInst>(LoadUser))
      IsVectorAccess = true;
  }

  if (IsFPAccess || IsVectorAccess)
    return AddressingMode(false/*LongDispl*/, true/*IdxReg*/);
}

return AddressingMode(true/*LongDispl*/, true/*IdxReg*/);
960}

962bool SystemZTargetLowering::isLegalAddressingMode(const DataLayout &DL,
     const AddrMode &AM, Type *Ty, unsigned AS, Instruction *I) const {
// Punt on globals for now, although they can be used in limited
// RELATIVE LONG cases.
if (AM.BaseGV)
  return false;

// Require a 20-bit signed offset.
if (!isInt<20>(AM.BaseOffs))
  return false;

AddressingMode SupportedAM(true, true);
if (I != nullptr)
  SupportedAM = supportedAddressingMode(I, Subtarget.hasVector());

if (!SupportedAM.LongDisplacement && !isUInt<12>(AM.BaseOffs))
  return false;

if (!SupportedAM.IndexReg)
  // No indexing allowed.
  return AM.Scale == 0;
else
  // Indexing is OK but no scale factor can be applied.
  return AM.Scale == 0 || AM.Scale == 1;
986}

988bool SystemZTargetLowering::isTruncateFree(Type *FromType, Type *ToType) const {
if (!FromType->isIntegerTy() || !ToType->isIntegerTy())
  return false;
unsigned FromBits = FromType->getPrimitiveSizeInBits().getFixedSize();
unsigned ToBits = ToType->getPrimitiveSizeInBits().getFixedSize();
return FromBits > ToBits;
994}

996bool SystemZTargetLowering::isTruncateFree(EVT FromVT, EVT ToVT) const {
if (!FromVT.isInteger() || !ToVT.isInteger())
  return false;
unsigned FromBits = FromVT.getFixedSizeInBits();
unsigned ToBits = ToVT.getFixedSizeInBits();
return FromBits > ToBits;
1002}

1004//===----------------------------------------------------------------------===//
1005// Inline asm support
1006//===----------------------------------------------------------------------===//

1008TargetLowering::ConstraintType
1009SystemZTargetLowering::getConstraintType(StringRef Constraint) const {
if (Constraint.size() == 1) {
  switch (Constraint[0]) {
  case 'a': // Address register
  case 'd': // Data register (equivalent to 'r')
  case 'f': // Floating-point register
  case 'h': // High-part register
  case 'r': // General-purpose register
  case 'v': // Vector register
    return C_RegisterClass;

  case 'Q': // Memory with base and unsigned 12-bit displacement
  case 'R': // Likewise, plus an index
  case 'S': // Memory with base and signed 20-bit displacement
  case 'T': // Likewise, plus an index
  case 'm': // Equivalent to 'T'.
    return C_Memory;

  case 'I': // Unsigned 8-bit constant
  case 'J': // Unsigned 12-bit constant
  case 'K': // Signed 16-bit constant
  case 'L': // Signed 20-bit displacement (on all targets we support)
  case 'M': // 0x7fffffff
    return C_Immediate;

  default:
    break;
  }
}
return TargetLowering::getConstraintType(Constraint);
1039}

1041TargetLowering::ConstraintWeight SystemZTargetLowering::
1042getSingleConstraintMatchWeight(AsmOperandInfo &info,
                             const char *constraint) const {
ConstraintWeight weight = CW_Invalid;
Value *CallOperandVal = info.CallOperandVal;
// If we don't have a value, we can't do a match,
// but allow it at the lowest weight.
if (!CallOperandVal)
  return CW_Default;
Type *type = CallOperandVal->getType();
// Look at the constraint type.
switch (*constraint) {
default:
  weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
  break;

case 'a': // Address register
case 'd': // Data register (equivalent to 'r')
case 'h': // High-part register
case 'r': // General-purpose register
  if (CallOperandVal->getType()->isIntegerTy())
    weight = CW_Register;
  break;

case 'f': // Floating-point register
  if (type->isFloatingPointTy())
    weight = CW_Register;
  break;

case 'v': // Vector register
  if ((type->isVectorTy() || type->isFloatingPointTy()) &&
      Subtarget.hasVector())
    weight = CW_Register;
  break;

case 'I': // Unsigned 8-bit constant
  if (auto *C = dyn_cast<ConstantInt>(CallOperandVal))
    if (isUInt<8>(C->getZExtValue()))
      weight = CW_Constant;
  break;

case 'J': // Unsigned 12-bit constant
  if (auto *C = dyn_cast<ConstantInt>(CallOperandVal))
    if (isUInt<12>(C->getZExtValue()))
      weight = CW_Constant;
  break;

case 'K': // Signed 16-bit constant
  if (auto *C = dyn_cast<ConstantInt>(CallOperandVal))
    if (isInt<16>(C->getSExtValue()))
      weight = CW_Constant;
  break;

case 'L': // Signed 20-bit displacement (on all targets we support)
  if (auto *C = dyn_cast<ConstantInt>(CallOperandVal))
    if (isInt<20>(C->getSExtValue()))
      weight = CW_Constant;
  break;

case 'M': // 0x7fffffff
  if (auto *C = dyn_cast<ConstantInt>(CallOperandVal))
    if (C->getZExtValue() == 0x7fffffff)
      weight = CW_Constant;
  break;
}
return weight;
1107}

1109// Parse a "{tNNN}" register constraint for which the register type "t"
1110// has already been verified.  MC is the class associated with "t" and
1111// Map maps 0-based register numbers to LLVM register numbers.
1112static std::pair<unsigned, const TargetRegisterClass *>
1113parseRegisterNumber(StringRef Constraint, const TargetRegisterClass *RC,
                  const unsigned *Map, unsigned Size) {
assert(*(Constraint.end()-1) == '}' && "Missing '}'")(static_cast <bool> (*(Constraint.end()-1) == '}' &&
 "Missing '}'") ? void (0) : __assert_fail ("*(Constraint.end()-1) == '}' && \"Missing '}'\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp"
, 1115, __extension__ __PRETTY_FUNCTION__));
if (isdigit(Constraint[2])) {
  unsigned Index;
  bool Failed =
      Constraint.slice(2, Constraint.size() - 1).getAsInteger(10, Index);
  if (!Failed && Index < Size && Map[Index])
    return std::make_pair(Map[Index], RC);
}
return std::make_pair(0U, nullptr);
1124}

1126std::pair<unsigned, const TargetRegisterClass *>
1127SystemZTargetLowering::getRegForInlineAsmConstraint(
  const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const {
if (Constraint.size() == 1) {
  // GCC Constraint Letters
  switch (Constraint[0]) {
  default: break;
  case 'd': // Data register (equivalent to 'r')
  case 'r': // General-purpose register
    if (VT == MVT::i64)
      return std::make_pair(0U, &SystemZ::GR64BitRegClass);
    else if (VT == MVT::i128)
      return std::make_pair(0U, &SystemZ::GR128BitRegClass);
    return std::make_pair(0U, &SystemZ::GR32BitRegClass);

  case 'a': // Address register
    if (VT == MVT::i64)
      return std::make_pair(0U, &SystemZ::ADDR64BitRegClass);
    else if (VT == MVT::i128)
      return std::make_pair(0U, &SystemZ::ADDR128BitRegClass);
    return std::make_pair(0U, &SystemZ::ADDR32BitRegClass);

  case 'h': // High-part register (an LLVM extension)
    return std::make_pair(0U, &SystemZ::GRH32BitRegClass);

  case 'f': // Floating-point register
    if (!useSoftFloat()) {
      if (VT == MVT::f64)
        return std::make_pair(0U, &SystemZ::FP64BitRegClass);
      else if (VT == MVT::f128)
        return std::make_pair(0U, &SystemZ::FP128BitRegClass);
      return std::make_pair(0U, &SystemZ::FP32BitRegClass);
    }
    break;
  case 'v': // Vector register
    if (Subtarget.hasVector()) {
      if (VT == MVT::f32)
        return std::make_pair(0U, &SystemZ::VR32BitRegClass);
      if (VT == MVT::f64)
        return std::make_pair(0U, &SystemZ::VR64BitRegClass);
      return std::make_pair(0U, &SystemZ::VR128BitRegClass);
    }
    break;
  }
}
if (Constraint.size() > 0 && Constraint[0] == '{') {
  // We need to override the default register parsing for GPRs and FPRs
  // because the interpretation depends on VT.  The internal names of
  // the registers are also different from the external names
  // (F0D and F0S instead of F0, etc.).
  if (Constraint[1] == 'r') {
    if (VT == MVT::i32)
      return parseRegisterNumber(Constraint, &SystemZ::GR32BitRegClass,
                                 SystemZMC::GR32Regs, 16);
    if (VT == MVT::i128)
      return parseRegisterNumber(Constraint, &SystemZ::GR128BitRegClass,
                                 SystemZMC::GR128Regs, 16);
    return parseRegisterNumber(Constraint, &SystemZ::GR64BitRegClass,
                               SystemZMC::GR64Regs, 16);
  }
  if (Constraint[1] == 'f') {
    if (useSoftFloat())
      return std::make_pair(
          0u, static_cast<const TargetRegisterClass *>(nullptr));
    if (VT == MVT::f32)
      return parseRegisterNumber(Constraint, &SystemZ::FP32BitRegClass,
                                 SystemZMC::FP32Regs, 16);
    if (VT == MVT::f128)
      return parseRegisterNumber(Constraint, &SystemZ::FP128BitRegClass,
                                 SystemZMC::FP128Regs, 16);
    return parseRegisterNumber(Constraint, &SystemZ::FP64BitRegClass,
                               SystemZMC::FP64Regs, 16);
  }
  if (Constraint[1] == 'v') {
    if (!Subtarget.hasVector())
      return std::make_pair(
          0u, static_cast<const TargetRegisterClass *>(nullptr));
    if (VT == MVT::f32)
      return parseRegisterNumber(Constraint, &SystemZ::VR32BitRegClass,
                                 SystemZMC::VR32Regs, 32);
    if (VT == MVT::f64)
      return parseRegisterNumber(Constraint, &SystemZ::VR64BitRegClass,
                                 SystemZMC::VR64Regs, 32);
    return parseRegisterNumber(Constraint, &SystemZ::VR128BitRegClass,
                               SystemZMC::VR128Regs, 32);
  }
}
return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
1214}

1216// FIXME? Maybe this could be a TableGen attribute on some registers and
1217// this table could be generated automatically from RegInfo.
1218Register SystemZTargetLowering::getRegisterByName(const char *RegName, LLT VT,
                                                const MachineFunction &MF) const {

Register Reg = StringSwitch<Register>(RegName)
                 .Case("r15", SystemZ::R15D)
                 .Default(0);
if (Reg)
  return Reg;
report_fatal_error("Invalid register name global variable");
1227}

1229void SystemZTargetLowering::
1230LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
                           std::vector<SDValue> &Ops,
                           SelectionDAG &DAG) const {
// Only support length 1 constraints for now.
if (Constraint.length() == 1) {
  switch (Constraint[0]) {
  case 'I': // Unsigned 8-bit constant
    if (auto *C = dyn_cast<ConstantSDNode>(Op))
      if (isUInt<8>(C->getZExtValue()))
        Ops.push_back(DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
                                            Op.getValueType()));
    return;

  case 'J': // Unsigned 12-bit constant
    if (auto *C = dyn_cast<ConstantSDNode>(Op))
      if (isUInt<12>(C->getZExtValue()))
        Ops.push_back(DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
                                            Op.getValueType()));
    return;

  case 'K': // Signed 16-bit constant
    if (auto *C = dyn_cast<ConstantSDNode>(Op))
      if (isInt<16>(C->getSExtValue()))
        Ops.push_back(DAG.getTargetConstant(C->getSExtValue(), SDLoc(Op),
                                            Op.getValueType()));
    return;

  case 'L': // Signed 20-bit displacement (on all targets we support)
    if (auto *C = dyn_cast<ConstantSDNode>(Op))
      if (isInt<20>(C->getSExtValue()))
        Ops.push_back(DAG.getTargetConstant(C->getSExtValue(), SDLoc(Op),
                                            Op.getValueType()));
    return;

  case 'M': // 0x7fffffff
    if (auto *C = dyn_cast<ConstantSDNode>(Op))
      if (C->getZExtValue() == 0x7fffffff)
        Ops.push_back(DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
                                            Op.getValueType()));
    return;
  }
}
TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
1273}

1275//===----------------------------------------------------------------------===//
1276// Calling conventions
1277//===----------------------------------------------------------------------===//

1279#include "SystemZGenCallingConv.inc"

1281const MCPhysReg *SystemZTargetLowering::getScratchRegisters(
CallingConv::ID) const {
static const MCPhysReg ScratchRegs[] = { SystemZ::R0D, SystemZ::R1D,
                                         SystemZ::R14D, 0 };
return ScratchRegs;
1286}

1288bool SystemZTargetLowering::allowTruncateForTailCall(Type *FromType,
                                                   Type *ToType) const {
return isTruncateFree(FromType, ToType);
1291}

1293bool SystemZTargetLowering::mayBeEmittedAsTailCall(const CallInst *CI) const {
return CI->isTailCall();
1295}

1297// We do not yet support 128-bit single-element vector types.  If the user
1298// attempts to use such types as function argument or return type, prefer
1299// to error out instead of emitting code violating the ABI.
1300static void VerifyVectorType(MVT VT, EVT ArgVT) {
if (ArgVT.isVector() && !VT.isVector())
  report_fatal_error("Unsupported vector argument or return type");
1303}

1305static void VerifyVectorTypes(const SmallVectorImpl<ISD::InputArg> &Ins) {
for (unsigned i = 0; i < Ins.size(); ++i)
  VerifyVectorType(Ins[i].VT, Ins[i].ArgVT);
1308}

1310static void VerifyVectorTypes(const SmallVectorImpl<ISD::OutputArg> &Outs) {
for (unsigned i = 0; i < Outs.size(); ++i)
  VerifyVectorType(Outs[i].VT, Outs[i].ArgVT);
1313}

1315// Value is a value that has been passed to us in the location described by VA
1316// (and so has type VA.getLocVT()).  Convert Value to VA.getValVT(), chaining
1317// any loads onto Chain.
1318static SDValue convertLocVTToValVT(SelectionDAG &DAG, const SDLoc &DL,
                                 CCValAssign &VA, SDValue Chain,
                                 SDValue Value) {
// If the argument has been promoted from a smaller type, insert an
// assertion to capture this.
if (VA.getLocInfo() == CCValAssign::SExt)
  Value = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Value,
                      DAG.getValueType(VA.getValVT()));
else if (VA.getLocInfo() == CCValAssign::ZExt)
  Value = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Value,
                      DAG.getValueType(VA.getValVT()));

if (VA.isExtInLoc())
  Value = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Value);
else if (VA.getLocInfo() == CCValAssign::BCvt) {
  // If this is a short vector argument loaded from the stack,
  // extend from i64 to full vector size and then bitcast.
  assert(VA.getLocVT() == MVT::i64)(static_cast <bool> (VA.getLocVT() == MVT::i64) ? void (
0) : __assert_fail ("VA.getLocVT() == MVT::i64", "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp"
, 1335, __extension__ __PRETTY_FUNCTION__));
  assert(VA.getValVT().isVector())(static_cast <bool> (VA.getValVT().isVector()) ? void (
0) : __assert_fail ("VA.getValVT().isVector()", "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp"
, 1336, __extension__ __PRETTY_FUNCTION__));
  Value = DAG.getBuildVector(MVT::v2i64, DL, {Value, DAG.getUNDEF(MVT::i64)});
  Value = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), Value);
} else
  assert(VA.getLocInfo() == CCValAssign::Full && "Unsupported getLocInfo")(static_cast <bool> (VA.getLocInfo() == CCValAssign::Full
 && "Unsupported getLocInfo") ? void (0) : __assert_fail
 ("VA.getLocInfo() == CCValAssign::Full && \"Unsupported getLocInfo\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp"
, 1340, __extension__ __PRETTY_FUNCTION__));
return Value;
1342}

1344// Value is a value of type VA.getValVT() that we need to copy into
1345// the location described by VA.  Return a copy of Value converted to
1346// VA.getValVT().  The caller is responsible for handling indirect values.
1347static SDValue convertValVTToLocVT(SelectionDAG &DAG, const SDLoc &DL,
                                 CCValAssign &VA, SDValue Value) {
switch (VA.getLocInfo()) {
case CCValAssign::SExt:
  return DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Value);
case CCValAssign::ZExt:
  return DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Value);
case CCValAssign::AExt:
  return DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Value);
case CCValAssign::BCvt:
  // If this is a short vector argument to be stored to the stack,
  // bitcast to v2i64 and then extract first element.
  assert(VA.getLocVT() == MVT::i64)(static_cast <bool> (VA.getLocVT() == MVT::i64) ? void (
0) : __assert_fail ("VA.getLocVT() == MVT::i64", "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp"
, 1359, __extension__ __PRETTY_FUNCTION__));
  assert(VA.getValVT().isVector())(static_cast <bool> (VA.getValVT().isVector()) ? void (
0) : __assert_fail ("VA.getValVT().isVector()", "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp"
, 1360, __extension__ __PRETTY_FUNCTION__));
  Value = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, Value);
  return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VA.getLocVT(), Value,
                     DAG.getConstant(0, DL, MVT::i32));
case CCValAssign::Full:
  return Value;
default:
  llvm_unreachable("Unhandled getLocInfo()")::llvm::llvm_unreachable_internal("Unhandled getLocInfo()", "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp"
, 1367);
}
1369}

1371static SDValue lowerI128ToGR128(SelectionDAG &DAG, SDValue In) {
SDLoc DL(In);
SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i64, In,
                         DAG.getIntPtrConstant(0, DL));
SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i64, In,
                         DAG.getIntPtrConstant(1, DL));
SDNode *Pair = DAG.getMachineNode(SystemZ::PAIR128, DL,
                                  MVT::Untyped, Hi, Lo);
return SDValue(Pair, 0);
1380}

1382static SDValue lowerGR128ToI128(SelectionDAG &DAG, SDValue In) {
SDLoc DL(In);
SDValue Hi = DAG.getTargetExtractSubreg(SystemZ::subreg_h64,
                                        DL, MVT::i64, In);
SDValue Lo = DAG.getTargetExtractSubreg(SystemZ::subreg_l64,
                                        DL, MVT::i64, In);
return DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i128, Lo, Hi);
1389}

1391bool SystemZTargetLowering::splitValueIntoRegisterParts(
  SelectionDAG &DAG, const SDLoc &DL, SDValue Val, SDValue *Parts,
  unsigned NumParts, MVT PartVT, Optional<CallingConv::ID> CC) const {
EVT ValueVT = Val.getValueType();
assert((ValueVT != MVT::i128 ||(static_cast <bool> ((ValueVT != MVT::i128 || ((NumParts
 == 1 && PartVT == MVT::Untyped) || (NumParts == 2 &&
 PartVT == MVT::i64))) && "Unknown handling of i128 value."
) ? void (0) : __assert_fail ("(ValueVT != MVT::i128 || ((NumParts == 1 && PartVT == MVT::Untyped) || (NumParts == 2 && PartVT == MVT::i64))) && \"Unknown handling of i128 value.\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp"
, 1398, __extension__ __PRETTY_FUNCTION__))
        ((NumParts == 1 && PartVT == MVT::Untyped) ||(static_cast <bool> ((ValueVT != MVT::i128 || ((NumParts
 == 1 && PartVT == MVT::Untyped) || (NumParts == 2 &&
 PartVT == MVT::i64))) && "Unknown handling of i128 value."
) ? void (0) : __assert_fail ("(ValueVT != MVT::i128 || ((NumParts == 1 && PartVT == MVT::Untyped) || (NumParts == 2 && PartVT == MVT::i64))) && \"Unknown handling of i128 value.\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp"
, 1398, __extension__ __PRETTY_FUNCTION__))
         (NumParts == 2 && PartVT == MVT::i64))) &&(static_cast <bool> ((ValueVT != MVT::i128 || ((NumParts
 == 1 && PartVT == MVT::Untyped) || (NumParts == 2 &&
 PartVT == MVT::i64))) && "Unknown handling of i128 value."
) ? void (0) : __assert_fail ("(ValueVT != MVT::i128 || ((NumParts == 1 && PartVT == MVT::Untyped) || (NumParts == 2 && PartVT == MVT::i64))) && \"Unknown handling of i128 value.\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp"
, 1398, __extension__ __PRETTY_FUNCTION__))
       "Unknown handling of i128 value.")(static_cast <bool> ((ValueVT != MVT::i128 || ((NumParts
 == 1 && PartVT == MVT::Untyped) || (NumParts == 2 &&
 PartVT == MVT::i64))) && "Unknown handling of i128 value."
) ? void (0) : __assert_fail ("(ValueVT != MVT::i128 || ((NumParts == 1 && PartVT == MVT::Untyped) || (NumParts == 2 && PartVT == MVT::i64))) && \"Unknown handling of i128 value.\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp"
, 1398, __extension__ __PRETTY_FUNCTION__));
if (ValueVT == MVT::i128 && NumParts == 1) {
  // Inline assembly operand.
  Parts[0] = lowerI128ToGR128(DAG, Val);
  return true;
}
return false;
1405}

1407SDValue SystemZTargetLowering::joinRegisterPartsIntoValue(
  SelectionDAG &DAG, const SDLoc &DL, const SDValue *Parts, unsigned NumParts,
  MVT PartVT, EVT ValueVT, Optional<CallingConv::ID> CC) const {
assert((ValueVT != MVT::i128 ||(static_cast <bool> ((ValueVT != MVT::i128 || ((NumParts
 == 1 && PartVT == MVT::Untyped) || (NumParts == 2 &&
 PartVT == MVT::i64))) && "Unknown handling of i128 value."
) ? void (0) : __assert_fail ("(ValueVT != MVT::i128 || ((NumParts == 1 && PartVT == MVT::Untyped) || (NumParts == 2 && PartVT == MVT::i64))) && \"Unknown handling of i128 value.\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp"
, 1413, __extension__ __PRETTY_FUNCTION__))
        ((NumParts == 1 && PartVT == MVT::Untyped) ||(static_cast <bool> ((ValueVT != MVT::i128 || ((NumParts
 == 1 && PartVT == MVT::Untyped) || (NumParts == 2 &&
 PartVT == MVT::i64))) && "Unknown handling of i128 value."
) ? void (0) : __assert_fail ("(ValueVT != MVT::i128 || ((NumParts == 1 && PartVT == MVT::Untyped) || (NumParts == 2 && PartVT == MVT::i64))) && \"Unknown handling of i128 value.\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp"
, 1413, __extension__ __PRETTY_FUNCTION__))
         (NumParts == 2 && PartVT == MVT::i64))) &&(static_cast <bool> ((ValueVT != MVT::i128 || ((NumParts
 == 1 && PartVT == MVT::Untyped) || (NumParts == 2 &&
 PartVT == MVT::i64))) && "Unknown handling of i128 value."
) ? void (0) : __assert_fail ("(ValueVT != MVT::i128 || ((NumParts == 1 && PartVT == MVT::Untyped) || (NumParts == 2 && PartVT == MVT::i64))) && \"Unknown handling of i128 value.\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp"
, 1413, __extension__ __PRETTY_FUNCTION__))
       "Unknown handling of i128 value.")(static_cast <bool> ((ValueVT != MVT::i128 || ((NumParts
 == 1 && PartVT == MVT::Untyped) || (NumParts == 2 &&
 PartVT == MVT::i64))) && "Unknown handling of i128 value."
) ? void (0) : __assert_fail ("(ValueVT != MVT::i128 || ((NumParts == 1 && PartVT == MVT::Untyped) || (NumParts == 2 && PartVT == MVT::i64))) && \"Unknown handling of i128 value.\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp"
, 1413, __extension__ __PRETTY_FUNCTION__));
if (ValueVT == MVT::i128 && NumParts == 1)
  // Inline assembly operand.
  return lowerGR128ToI128(DAG, Parts[0]);
return SDValue();
1418}

1420SDValue SystemZTargetLowering::LowerFormalArguments(
  SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
  const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
  SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
MachineFunction &MF = DAG.getMachineFunction();
MachineFrameInfo &MFI = MF.getFrameInfo();
MachineRegisterInfo &MRI = MF.getRegInfo();
SystemZMachineFunctionInfo *FuncInfo =
    MF.getInfo<SystemZMachineFunctionInfo>();
auto *TFL =
    static_cast<const SystemZFrameLowering *>(Subtarget.getFrameLowering());
EVT PtrVT = getPointerTy(DAG.getDataLayout());

// Detect unsupported vector argument types.
if (Subtarget.hasVector())
  VerifyVectorTypes(Ins);

// Assign locations to all of the incoming arguments.
SmallVector<CCValAssign, 16> ArgLocs;
SystemZCCState CCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext());
CCInfo.AnalyzeFormalArguments(Ins, CC_SystemZ);

unsigned NumFixedGPRs = 0;
unsigned NumFixedFPRs = 0;
for (unsigned I = 0, E = ArgLocs.size(); I != E; ++I) {
  SDValue ArgValue;
  CCValAssign &VA = ArgLocs[I];
  EVT LocVT = VA.getLocVT();
  if (VA.isRegLoc()) {
    // Arguments passed in registers
    const TargetRegisterClass *RC;
    switch (LocVT.getSimpleVT().SimpleTy) {
    default:
      // Integers smaller than i64 should be promoted to i64.
      llvm_unreachable("Unexpected argument type")::llvm::llvm_unreachable_internal("Unexpected argument type",
 "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp"
, 1454);
    case MVT::i32:
      NumFixedGPRs += 1;
      RC = &SystemZ::GR32BitRegClass;
      break;
    case MVT::i64:
      NumFixedGPRs += 1;
      RC = &SystemZ::GR64BitRegClass;
      break;
    case MVT::f32:
      NumFixedFPRs += 1;
      RC = &SystemZ::FP32BitRegClass;
      break;
    case MVT::f64:
      NumFixedFPRs += 1;
      RC = &SystemZ::FP64BitRegClass;
      break;
    case MVT::v16i8:
    case MVT::v8i16:
    case MVT::v4i32:
    case MVT::v2i64:
    case MVT::v4f32:
    case MVT::v2f64:
      RC = &SystemZ::VR128BitRegClass;
      break;
    }

    Register VReg = MRI.createVirtualRegister(RC);
    MRI.addLiveIn(VA.getLocReg(), VReg);
    ArgValue = DAG.getCopyFromReg(Chain, DL, VReg, LocVT);
  } else {
    assert(VA.isMemLoc() && "Argument not register or memory")(static_cast <bool> (VA.isMemLoc() && "Argument not register or memory"
) ? void (0) : __assert_fail ("VA.isMemLoc() && \"Argument not register or memory\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp"
, 1485, __extension__ __PRETTY_FUNCTION__));

    // Create the frame index object for this incoming parameter.
    int FI = MFI.CreateFixedObject(LocVT.getSizeInBits() / 8,
                                   VA.getLocMemOffset(), true);

    // Create the SelectionDAG nodes corresponding to a load
    // from this parameter.  Unpromoted ints and floats are
    // passed as right-justified 8-byte values.
    SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
    if (VA.getLocVT() == MVT::i32 || VA.getLocVT() == MVT::f32)
      FIN = DAG.getNode(ISD::ADD, DL, PtrVT, FIN,
                        DAG.getIntPtrConstant(4, DL));
    ArgValue = DAG.getLoad(LocVT, DL, Chain, FIN,
                           MachinePointerInfo::getFixedStack(MF, FI));
  }

  // Convert the value of the argument register into the value that's
  // being passed.
  if (VA.getLocInfo() == CCValAssign::Indirect) {
    InVals.push_back(DAG.getLoad(VA.getValVT(), DL, Chain, ArgValue,
                                 MachinePointerInfo()));
    // If the original argument was split (e.g. i128), we need
    // to load all parts of it here (using the same address).
    unsigned ArgIndex = Ins[I].OrigArgIndex;
    assert (Ins[I].PartOffset == 0)(static_cast <bool> (Ins[I].PartOffset == 0) ? void (0)
 : __assert_fail ("Ins[I].PartOffset == 0", "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp"
, 1510, __extension__ __PRETTY_FUNCTION__));
    while (I + 1 != E && Ins[I + 1].OrigArgIndex == ArgIndex) {
      CCValAssign &PartVA = ArgLocs[I + 1];
      unsigned PartOffset = Ins[I + 1].PartOffset;
      SDValue Address = DAG.getNode(ISD::ADD, DL, PtrVT, ArgValue,
                                    DAG.getIntPtrConstant(PartOffset, DL));
      InVals.push_back(DAG.getLoad(PartVA.getValVT(), DL, Chain, Address,
                                   MachinePointerInfo()));
      ++I;
    }
  } else
    InVals.push_back(convertLocVTToValVT(DAG, DL, VA, Chain, ArgValue));
}

if (IsVarArg) {
  // Save the number of non-varargs registers for later use by va_start, etc.
  FuncInfo->setVarArgsFirstGPR(NumFixedGPRs);
  FuncInfo->setVarArgsFirstFPR(NumFixedFPRs);

  // Likewise the address (in the form of a frame index) of where the
  // first stack vararg would be.  The 1-byte size here is arbitrary.
  int64_t StackSize = CCInfo.getNextStackOffset();
  FuncInfo->setVarArgsFrameIndex(MFI.CreateFixedObject(1, StackSize, true));

  // ...and a similar frame index for the caller-allocated save area
  // that will be used to store the incoming registers.
  int64_t RegSaveOffset =
    -SystemZMC::ELFCallFrameSize + TFL->getRegSpillOffset(MF, SystemZ::R2D) - 16;
  unsigned RegSaveIndex = MFI.CreateFixedObject(1, RegSaveOffset, true);
  FuncInfo->setRegSaveFrameIndex(RegSaveIndex);

  // Store the FPR varargs in the reserved frame slots.  (We store the
  // GPRs as part of the prologue.)
  if (NumFixedFPRs < SystemZ::ELFNumArgFPRs && !useSoftFloat()) {
    SDValue MemOps[SystemZ::ELFNumArgFPRs];
    for (unsigned I = NumFixedFPRs; I < SystemZ::ELFNumArgFPRs; ++I) {
      unsigned Offset = TFL->getRegSpillOffset(MF, SystemZ::ELFArgFPRs[I]);
      int FI =
        MFI.CreateFixedObject(8, -SystemZMC::ELFCallFrameSize + Offset, true);
      SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
      unsigned VReg = MF.addLiveIn(SystemZ::ELFArgFPRs[I],
                                   &SystemZ::FP64BitRegClass);
      SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, VReg, MVT::f64);
      MemOps[I] = DAG.getStore(ArgValue.getValue(1), DL, ArgValue, FIN,
                               MachinePointerInfo::getFixedStack(MF, FI));
    }
    // Join the stores, which are independent of one another.
    Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
                        makeArrayRef(&MemOps[NumFixedFPRs],
                                     SystemZ::ELFNumArgFPRs-NumFixedFPRs));
  }
}

return Chain;
1564}

1566static bool canUseSiblingCall(const CCState &ArgCCInfo,
                            SmallVectorImpl<CCValAssign> &ArgLocs,
                            SmallVectorImpl<ISD::OutputArg> &Outs) {
// Punt if there are any indirect or stack arguments, or if the call
// needs the callee-saved argument register R6, or if the call uses
// the callee-saved register arguments SwiftSelf and SwiftError.
for (unsigned I = 0, E = ArgLocs.size(); I != E; ++I) {
  CCValAssign &VA = ArgLocs[I];
  if (VA.getLocInfo() == CCValAssign::Indirect)
    return false;
  if (!VA.isRegLoc())
    return false;
  Register Reg = VA.getLocReg();
  if (Reg == SystemZ::R6H || Reg == SystemZ::R6L || Reg == SystemZ::R6D)
    return false;
  if (Outs[I].Flags.isSwiftSelf() || Outs[I].Flags.isSwiftError())
    return false;
}
return true;
1585}

1587SDValue
1588SystemZTargetLowering::LowerCall(CallLoweringInfo &CLI,
                               SmallVectorImpl<SDValue> &InVals) const {
SelectionDAG &DAG = CLI.DAG;
SDLoc &DL = CLI.DL;
SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
SDValue Chain = CLI.Chain;
SDValue Callee = CLI.Callee;
bool &IsTailCall = CLI.IsTailCall;
CallingConv::ID CallConv = CLI.CallConv;
bool IsVarArg = CLI.IsVarArg;
MachineFunction &MF = DAG.getMachineFunction();
EVT PtrVT = getPointerTy(MF.getDataLayout());
LLVMContext &Ctx = *DAG.getContext();

// Detect unsupported vector argument and return types.
if (Subtarget.hasVector()) {
1
Assuming the condition is false→
2
←
Taking false branch→
  VerifyVectorTypes(Outs);
  VerifyVectorTypes(Ins);
}

// Analyze the operands of the call, assigning locations to each operand.
SmallVector<CCValAssign, 16> ArgLocs;
SystemZCCState ArgCCInfo(CallConv, IsVarArg, MF, ArgLocs, Ctx);
ArgCCInfo.AnalyzeCallOperands(Outs, CC_SystemZ);

// We don't support GuaranteedTailCallOpt, only automatically-detected
// sibling calls.
if (IsTailCall && !canUseSiblingCall(ArgCCInfo, ArgLocs, Outs))
3
←
Assuming 'IsTailCall' is true→
4
←
Taking false branch→
  IsTailCall = false;

// Get a count of how many bytes are to be pushed on the stack.
unsigned NumBytes = ArgCCInfo.getNextStackOffset();

// Mark the start of the call.
if (!IsTailCall4.1
'IsTailCall' is true
1
'IsTailCall' is true
1
'IsTailCall' is true
)
5
←
Taking false branch→
  Chain = DAG.getCALLSEQ_START(Chain, NumBytes, 0, DL);

// Copy argument values to their designated locations.
SmallVector<std::pair<unsigned, SDValue>, 9> RegsToPass;
SmallVector<SDValue, 8> MemOpChains;
SDValue StackPtr;
for (unsigned I = 0, E = ArgLocs.size(); I != E; ++I) {
6
←
Loop condition is false. Execution continues on line 1696→
  CCValAssign &VA = ArgLocs[I];
  SDValue ArgValue = OutVals[I];

  if (VA.getLocInfo() == CCValAssign::Indirect) {
    // Store the argument in a stack slot and pass its address.
    unsigned ArgIndex = Outs[I].OrigArgIndex;
    EVT SlotVT;
    if (I + 1 != E && Outs[I + 1].OrigArgIndex == ArgIndex) {
      // Allocate the full stack space for a promoted (and split) argument.
      Type *OrigArgType = CLI.Args[Outs[I].OrigArgIndex].Ty;
      EVT OrigArgVT = getValueType(MF.getDataLayout(), OrigArgType);
      MVT PartVT = getRegisterTypeForCallingConv(Ctx, CLI.CallConv, OrigArgVT);
      unsigned N = getNumRegistersForCallingConv(Ctx, CLI.CallConv, OrigArgVT);
      SlotVT = EVT::getIntegerVT(Ctx, PartVT.getSizeInBits() * N);
    } else {
      SlotVT = Outs[I].ArgVT;
    }
    SDValue SpillSlot = DAG.CreateStackTemporary(SlotVT);
    int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
    MemOpChains.push_back(
        DAG.getStore(Chain, DL, ArgValue, SpillSlot,
                     MachinePointerInfo::getFixedStack(MF, FI)));
    // If the original argument was split (e.g. i128), we need
    // to store all parts of it here (and pass just one address).
    assert (Outs[I].PartOffset == 0)(static_cast <bool> (Outs[I].PartOffset == 0) ? void (0
) : __assert_fail ("Outs[I].PartOffset == 0", "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp"
, 1656, __extension__ __PRETTY_FUNCTION__));
    while (I + 1 != E && Outs[I + 1].OrigArgIndex == ArgIndex) {
      SDValue PartValue = OutVals[I + 1];
      unsigned PartOffset = Outs[I + 1].PartOffset;
      SDValue Address = DAG.getNode(ISD::ADD, DL, PtrVT, SpillSlot,
                                    DAG.getIntPtrConstant(PartOffset, DL));
      MemOpChains.push_back(
          DAG.getStore(Chain, DL, PartValue, Address,
                       MachinePointerInfo::getFixedStack(MF, FI)));
      assert((PartOffset + PartValue.getValueType().getStoreSize() <=(static_cast <bool> ((PartOffset + PartValue.getValueType
().getStoreSize() <= SlotVT.getStoreSize()) && "Not enough space for argument part!"
) ? void (0) : __assert_fail ("(PartOffset + PartValue.getValueType().getStoreSize() <= SlotVT.getStoreSize()) && \"Not enough space for argument part!\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp"
, 1666, __extension__ __PRETTY_FUNCTION__))
              SlotVT.getStoreSize()) && "Not enough space for argument part!")(static_cast <bool> ((PartOffset + PartValue.getValueType
().getStoreSize() <= SlotVT.getStoreSize()) && "Not enough space for argument part!"
) ? void (0) : __assert_fail ("(PartOffset + PartValue.getValueType().getStoreSize() <= SlotVT.getStoreSize()) && \"Not enough space for argument part!\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp"
, 1666, __extension__ __PRETTY_FUNCTION__));
      ++I;
    }
    ArgValue = SpillSlot;
  } else
    ArgValue = convertValVTToLocVT(DAG, DL, VA, ArgValue);

  if (VA.isRegLoc())
    // Queue up the argument copies and emit them at the end.
    RegsToPass.push_back(std::make_pair(VA.getLocReg(), ArgValue));
  else {
    assert(VA.isMemLoc() && "Argument not register or memory")(static_cast <bool> (VA.isMemLoc() && "Argument not register or memory"
) ? void (0) : __assert_fail ("VA.isMemLoc() && \"Argument not register or memory\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp"
, 1677, __extension__ __PRETTY_FUNCTION__));

    // Work out the address of the stack slot.  Unpromoted ints and
    // floats are passed as right-justified 8-byte values.
    if (!StackPtr.getNode())
      StackPtr = DAG.getCopyFromReg(Chain, DL, SystemZ::R15D, PtrVT);
    unsigned Offset = SystemZMC::ELFCallFrameSize + VA.getLocMemOffset();
    if (VA.getLocVT() == MVT::i32 || VA.getLocVT() == MVT::f32)
      Offset += 4;
    SDValue Address = DAG.getNode(ISD::ADD, DL, PtrVT, StackPtr,
                                  DAG.getIntPtrConstant(Offset, DL));

    // Emit the store.
    MemOpChains.push_back(
        DAG.getStore(Chain, DL, ArgValue, Address, MachinePointerInfo()));
  }
}

// Join the stores, which are independent of one another.
if (!MemOpChains.empty())
7
←
Taking false branch→
  Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOpChains);

// Accept direct calls by converting symbolic call addresses to the
// associated Target* opcodes.  Force %r1 to be used for indirect
// tail calls.
SDValue Glue;
if (auto *G7.1
'G' is null
1
'G' is null
1
'G' is null
 = dyn_cast<GlobalAddressSDNode>(Callee)) {
8
←
Taking false branch→
  Callee = DAG.getTargetGlobalAddress(G->getGlobal(), DL, PtrVT);
  Callee = DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Callee);
} else if (auto *E = dyn_cast<ExternalSymbolSDNode>(Callee)) {
9
←
Assuming 'E' is null→
10
←
Taking false branch→
  Callee = DAG.getTargetExternalSymbol(E->getSymbol(), PtrVT);
  Callee = DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Callee);
} else if (IsTailCall10.1
'IsTailCall' is true
1
'IsTailCall' is true
1
'IsTailCall' is true
) {
11
←
Taking true branch→
  Chain = DAG.getCopyToReg(Chain, DL, SystemZ::R1D, Callee, Glue);
12
←
The value of 'Callee' is assigned to 'N.Node'→
13
←
Calling 'SelectionDAG::getCopyToReg'→
  Glue = Chain.getValue(1);
  Callee = DAG.getRegister(SystemZ::R1D, Callee.getValueType());
}

// Build a sequence of copy-to-reg nodes, chained and glued together.
for (unsigned I = 0, E = RegsToPass.size(); I != E; ++I) {
  Chain = DAG.getCopyToReg(Chain, DL, RegsToPass[I].first,
                           RegsToPass[I].second, Glue);
  Glue = Chain.getValue(1);
}

// The first call operand is the chain and the second is the target address.
SmallVector<SDValue, 8> Ops;
Ops.push_back(Chain);
Ops.push_back(Callee);

// Add argument registers to the end of the list so that they are
// known live into the call.
for (unsigned I = 0, E = RegsToPass.size(); I != E; ++I)
  Ops.push_back(DAG.getRegister(RegsToPass[I].first,
                                RegsToPass[I].second.getValueType()));

// Add a register mask operand representing the call-preserved registers.
const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
const uint32_t *Mask = TRI->getCallPreservedMask(MF, CallConv);
assert(Mask && "Missing call preserved mask for calling convention")(static_cast <bool> (Mask && "Missing call preserved mask for calling convention"
) ? void (0) : __assert_fail ("Mask && \"Missing call preserved mask for calling convention\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp"
, 1736, __extension__ __PRETTY_FUNCTION__));
Ops.push_back(DAG.getRegisterMask(Mask));

// Glue the call to the argument copies, if any.
if (Glue.getNode())
  Ops.push_back(Glue);

// Emit the call.
SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
if (IsTailCall)
  return DAG.getNode(SystemZISD::SIBCALL, DL, NodeTys, Ops);
Chain = DAG.getNode(SystemZISD::CALL, DL, NodeTys, Ops);
DAG.addNoMergeSiteInfo(Chain.getNode(), CLI.NoMerge);
Glue = Chain.getValue(1);

// Mark the end of the call, which is glued to the call itself.
Chain = DAG.getCALLSEQ_END(Chain,
                           DAG.getConstant(NumBytes, DL, PtrVT, true),
                           DAG.getConstant(0, DL, PtrVT, true),
                           Glue, DL);
Glue = Chain.getValue(1);

// Assign locations to each value returned by this call.
SmallVector<CCValAssign, 16> RetLocs;
CCState RetCCInfo(CallConv, IsVarArg, MF, RetLocs, Ctx);
RetCCInfo.AnalyzeCallResult(Ins, RetCC_SystemZ);

// Copy all of the result registers out of their specified physreg.
for (unsigned I = 0, E = RetLocs.size(); I != E; ++I) {
  CCValAssign &VA = RetLocs[I];

  // Copy the value out, gluing the copy to the end of the call sequence.
  SDValue RetValue = DAG.getCopyFromReg(Chain, DL, VA.getLocReg(),
                                        VA.getLocVT(), Glue);
  Chain = RetValue.getValue(1);
  Glue = RetValue.getValue(2);

  // Convert the value of the return register into the value that's
  // being returned.
  InVals.push_back(convertLocVTToValVT(DAG, DL, VA, Chain, RetValue));
}

return Chain;
1779}

1781bool SystemZTargetLowering::
1782CanLowerReturn(CallingConv::ID CallConv,
             MachineFunction &MF, bool isVarArg,
             const SmallVectorImpl<ISD::OutputArg> &Outs,
             LLVMContext &Context) const {
// Detect unsupported vector return types.
if (Subtarget.hasVector())
  VerifyVectorTypes(Outs);

// Special case that we cannot easily detect in RetCC_SystemZ since
// i128 is not a legal type.
for (auto &Out : Outs)
  if (Out.ArgVT == MVT::i128)
    return false;

SmallVector<CCValAssign, 16> RetLocs;
CCState RetCCInfo(CallConv, isVarArg, MF, RetLocs, Context);
return RetCCInfo.CheckReturn(Outs, RetCC_SystemZ);
1799}

1801SDValue
1802SystemZTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
                                 bool IsVarArg,
                                 const SmallVectorImpl<ISD::OutputArg> &Outs,
                                 const SmallVectorImpl<SDValue> &OutVals,
                                 const SDLoc &DL, SelectionDAG &DAG) const {
MachineFunction &MF = DAG.getMachineFunction();

// Detect unsupported vector return types.
if (Subtarget.hasVector())
  VerifyVectorTypes(Outs);

// Assign locations to each returned value.
SmallVector<CCValAssign, 16> RetLocs;
CCState RetCCInfo(CallConv, IsVarArg, MF, RetLocs, *DAG.getContext());
RetCCInfo.AnalyzeReturn(Outs, RetCC_SystemZ);

// Quick exit for void returns
if (RetLocs.empty())
  return DAG.getNode(SystemZISD::RET_FLAG, DL, MVT::Other, Chain);

if (CallConv == CallingConv::GHC)
  report_fatal_error("GHC functions return void only");

// Copy the result values into the output registers.
SDValue Glue;
SmallVector<SDValue, 4> RetOps;
RetOps.push_back(Chain);
for (unsigned I = 0, E = RetLocs.size(); I != E; ++I) {
  CCValAssign &VA = RetLocs[I];
  SDValue RetValue = OutVals[I];

  // Make the return register live on exit.
  assert(VA.isRegLoc() && "Can only return in registers!")(static_cast <bool> (VA.isRegLoc() && "Can only return in registers!"
) ? void (0) : __assert_fail ("VA.isRegLoc() && \"Can only return in registers!\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp"
, 1834, __extension__ __PRETTY_FUNCTION__));

  // Promote the value as required.
  RetValue = convertValVTToLocVT(DAG, DL, VA, RetValue);

  // Chain and glue the copies together.
  Register Reg = VA.getLocReg();
  Chain = DAG.getCopyToReg(Chain, DL, Reg, RetValue, Glue);
  Glue = Chain.getValue(1);
  RetOps.push_back(DAG.getRegister(Reg, VA.getLocVT()));
}

// Update chain and glue.
RetOps[0] = Chain;
if (Glue.getNode())
  RetOps.push_back(Glue);

return DAG.getNode(SystemZISD::RET_FLAG, DL, MVT::Other, RetOps);
1852}

1854// Return true if Op is an intrinsic node with chain that returns the CC value
1855// as its only (other) argument.  Provide the associated SystemZISD opcode and
1856// the mask of valid CC values if so.
1857static bool isIntrinsicWithCCAndChain(SDValue Op, unsigned &Opcode,
                                    unsigned &CCValid) {
unsigned Id = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
switch (Id) {
case Intrinsic::s390_tbegin:
  Opcode = SystemZISD::TBEGIN;
  CCValid = SystemZ::CCMASK_TBEGIN;
  return true;

case Intrinsic::s390_tbegin_nofloat:
  Opcode = SystemZISD::TBEGIN_NOFLOAT;
  CCValid = SystemZ::CCMASK_TBEGIN;
  return true;

case Intrinsic::s390_tend:
  Opcode = SystemZISD::TEND;
  CCValid = SystemZ::CCMASK_TEND;
  return true;

default:
  return false;
}
1879}

1881// Return true if Op is an intrinsic node without chain that returns the
1882// CC value as its final argument.  Provide the associated SystemZISD
1883// opcode and the mask of valid CC values if so.
1884static bool isIntrinsicWithCC(SDValue Op, unsigned &Opcode, unsigned &CCValid) {
unsigned Id = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
switch (Id) {
case Intrinsic::s390_vpkshs:
case Intrinsic::s390_vpksfs:
case Intrinsic::s390_vpksgs:
  Opcode = SystemZISD::PACKS_CC;
  CCValid = SystemZ::CCMASK_VCMP;
  return true;

case Intrinsic::s390_vpklshs:
case Intrinsic::s390_vpklsfs:
case Intrinsic::s390_vpklsgs:
  Opcode = SystemZISD::PACKLS_CC;
  CCValid = SystemZ::CCMASK_VCMP;
  return true;

case Intrinsic::s390_vceqbs:
case Intrinsic::s390_vceqhs:
case Intrinsic::s390_vceqfs:
case Intrinsic::s390_vceqgs:
  Opcode = SystemZISD::VICMPES;
  CCValid = SystemZ::CCMASK_VCMP;
  return true;

case Intrinsic::s390_vchbs:
case Intrinsic::s390_vchhs:
case Intrinsic::s390_vchfs:
case Intrinsic::s390_vchgs:
  Opcode = SystemZISD::VICMPHS;
  CCValid = SystemZ::CCMASK_VCMP;
  return true;

case Intrinsic::s390_vchlbs:
case Intrinsic::s390_vchlhs:
case Intrinsic::s390_vchlfs:
case Intrinsic::s390_vchlgs:
  Opcode = SystemZISD::VICMPHLS;
  CCValid = SystemZ::CCMASK_VCMP;
  return true;

case Intrinsic::s390_vtm:
  Opcode = SystemZISD::VTM;
  CCValid = SystemZ::CCMASK_VCMP;
  return true;

case Intrinsic::s390_vfaebs:
case Intrinsic::s390_vfaehs:
case Intrinsic::s390_vfaefs:
  Opcode = SystemZISD::VFAE_CC;
  CCValid = SystemZ::CCMASK_ANY;
  return true;

case Intrinsic::s390_vfaezbs:
case Intrinsic::s390_vfaezhs:
case Intrinsic::s390_vfaezfs:
  Opcode = SystemZISD::VFAEZ_CC;
  CCValid = SystemZ::CCMASK_ANY;
  return true;

case Intrinsic::s390_vfeebs:
case Intrinsic::s390_vfeehs:
case Intrinsic::s390_vfeefs:
  Opcode = SystemZISD::VFEE_CC;
  CCValid = SystemZ::CCMASK_ANY;
  return true;

case Intrinsic::s390_vfeezbs:
case Intrinsic::s390_vfeezhs:
case Intrinsic::s390_vfeezfs:
  Opcode = SystemZISD::VFEEZ_CC;
  CCValid = SystemZ::CCMASK_ANY;
  return true;

case Intrinsic::s390_vfenebs:
case Intrinsic::s390_vfenehs:
case Intrinsic::s390_vfenefs:
  Opcode = SystemZISD::VFENE_CC;
  CCValid = SystemZ::CCMASK_ANY;
  return true;

case Intrinsic::s390_vfenezbs:
case Intrinsic::s390_vfenezhs:
case Intrinsic::s390_vfenezfs:
  Opcode = SystemZISD::VFENEZ_CC;
  CCValid = SystemZ::CCMASK_ANY;
  return true;

case Intrinsic::s390_vistrbs:
case Intrinsic::s390_vistrhs:
case Intrinsic::s390_vistrfs:
  Opcode = SystemZISD::VISTR_CC;
  CCValid = SystemZ::CCMASK_0 | SystemZ::CCMASK_3;
  return true;

case Intrinsic::s390_vstrcbs:
case Intrinsic::s390_vstrchs:
case Intrinsic::s390_vstrcfs:
  Opcode = SystemZISD::VSTRC_CC;
  CCValid = SystemZ::CCMASK_ANY;
  return true;

case Intrinsic::s390_vstrczbs:
case Intrinsic::s390_vstrczhs:
case Intrinsic::s390_vstrczfs:
  Opcode = SystemZISD::VSTRCZ_CC;
  CCValid = SystemZ::CCMASK_ANY;
  return true;

case Intrinsic::s390_vstrsb:
case Intrinsic::s390_vstrsh:
case Intrinsic::s390_vstrsf:
  Opcode = SystemZISD::VSTRS_CC;
  CCValid = SystemZ::CCMASK_ANY;
  return true;

case Intrinsic::s390_vstrszb:
case Intrinsic::s390_vstrszh:
case Intrinsic::s390_vstrszf:
  Opcode = SystemZISD::VSTRSZ_CC;
  CCValid = SystemZ::CCMASK_ANY;
  return true;

case Intrinsic::s390_vfcedbs:
case Intrinsic::s390_vfcesbs:
  Opcode = SystemZISD::VFCMPES;
  CCValid = SystemZ::CCMASK_VCMP;
  return true;

case Intrinsic::s390_vfchdbs:
case Intrinsic::s390_vfchsbs:
  Opcode = SystemZISD::VFCMPHS;
  CCValid = SystemZ::CCMASK_VCMP;
  return true;

case Intrinsic::s390_vfchedbs:
case Intrinsic::s390_vfchesbs:
  Opcode = SystemZISD::VFCMPHES;
  CCValid = SystemZ::CCMASK_VCMP;
  return true;

case Intrinsic::s390_vftcidb:
case Intrinsic::s390_vftcisb:
  Opcode = SystemZISD::VFTCI;
  CCValid = SystemZ::CCMASK_VCMP;
  return true;

case Intrinsic::s390_tdc:
  Opcode = SystemZISD::TDC;
  CCValid = SystemZ::CCMASK_TDC;
  return true;

default:
  return false;
}
2039}

2041// Emit an intrinsic with chain and an explicit CC register result.
2042static SDNode *emitIntrinsicWithCCAndChain(SelectionDAG &DAG, SDValue Op,
                                         unsigned Opcode) {
// Copy all operands except the intrinsic ID.
unsigned NumOps = Op.getNumOperands();
SmallVector<SDValue, 6> Ops;
Ops.reserve(NumOps - 1);
Ops.push_back(Op.getOperand(0));
for (unsigned I = 2; I < NumOps; ++I)
  Ops.push_back(Op.getOperand(I));

assert(Op->getNumValues() == 2 && "Expected only CC result and chain")(static_cast <bool> (Op->getNumValues() == 2 &&
 "Expected only CC result and chain") ? void (0) : __assert_fail
 ("Op->getNumValues() == 2 && \"Expected only CC result and chain\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp"
, 2052, __extension__ __PRETTY_FUNCTION__));
SDVTList RawVTs = DAG.getVTList(MVT::i32, MVT::Other);
SDValue Intr = DAG.getNode(Opcode, SDLoc(Op), RawVTs, Ops);
SDValue OldChain = SDValue(Op.getNode(), 1);
SDValue NewChain = SDValue(Intr.getNode(), 1);
DAG.ReplaceAllUsesOfValueWith(OldChain, NewChain);
return Intr.getNode();
2059}

2061// Emit an intrinsic with an explicit CC register result.
2062static SDNode *emitIntrinsicWithCC(SelectionDAG &DAG, SDValue Op,
                                 unsigned Opcode) {
// Copy all operands except the intrinsic ID.
unsigned NumOps = Op.getNumOperands();
SmallVector<SDValue, 6> Ops;
Ops.reserve(NumOps - 1);
for (unsigned I = 1; I < NumOps; ++I)
  Ops.push_back(Op.getOperand(I));

SDValue Intr = DAG.getNode(Opcode, SDLoc(Op), Op->getVTList(), Ops);
return Intr.getNode();
2073}

2075// CC is a comparison that will be implemented using an integer or
2076// floating-point comparison.  Return the condition code mask for
2077// a branch on true.  In the integer case, CCMASK_CMP_UO is set for
2078// unsigned comparisons and clear for signed ones.  In the floating-point
2079// case, CCMASK_CMP_UO has its normal mask meaning (unordered).
2080static unsigned CCMaskForCondCode(ISD::CondCode CC) {
2081#define CONV(X) \
case ISD::SET##X: return SystemZ::CCMASK_CMP_##X; \
case ISD::SETO##X: return SystemZ::CCMASK_CMP_##X; \
case ISD::SETU##X: return SystemZ::CCMASK_CMP_UO | SystemZ::CCMASK_CMP_##X

switch (CC) {
default:
  llvm_unreachable("Invalid integer condition!")::llvm::llvm_unreachable_internal("Invalid integer condition!"
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp"
, 2088);

CONV(EQ);
CONV(NE);
CONV(GT);
CONV(GE);
CONV(LT);
CONV(LE);

case ISD::SETO:  return SystemZ::CCMASK_CMP_O;
case ISD::SETUO: return SystemZ::CCMASK_CMP_UO;
}
2100#undef CONV
2101}

2103// If C can be converted to a comparison against zero, adjust the operands
2104// as necessary.
2105static void adjustZeroCmp(SelectionDAG &DAG, const SDLoc &DL, Comparison &C) {
if (C.ICmpType == SystemZICMP::UnsignedOnly)
  return;

auto *ConstOp1 = dyn_cast<ConstantSDNode>(C.Op1.getNode());
if (!ConstOp1)
  return;

int64_t Value = ConstOp1->getSExtValue();
if ((Value == -1 && C.CCMask == SystemZ::CCMASK_CMP_GT) ||
    (Value == -1 && C.CCMask == SystemZ::CCMASK_CMP_LE) ||
    (Value == 1 && C.CCMask == SystemZ::CCMASK_CMP_LT) ||
    (Value == 1 && C.CCMask == SystemZ::CCMASK_CMP_GE)) {
  C.CCMask ^= SystemZ::CCMASK_CMP_EQ;
  C.Op1 = DAG.getConstant(0, DL, C.Op1.getValueType());
}
2121}

2123// If a comparison described by C is suitable for CLI(Y), CHHSI or CLHHSI,
2124// adjust the operands as necessary.
2125static void adjustSubwordCmp(SelectionDAG &DAG, const SDLoc &DL,
                           Comparison &C) {
// For us to make any changes, it must a comparison between a single-use
// load and a constant.
if (!C.Op0.hasOneUse() ||
    C.Op0.getOpcode() != ISD::LOAD ||
    C.Op1.getOpcode() != ISD::Constant)
  return;

// We must have an 8- or 16-bit load.
auto *Load = cast<LoadSDNode>(C.Op0);
unsigned NumBits = Load->getMemoryVT().getSizeInBits();
if ((NumBits != 8 && NumBits != 16) ||
    NumBits != Load->getMemoryVT().getStoreSizeInBits())
  return;

// The load must be an extending one and the constant must be within the
// range of the unextended value.
auto *ConstOp1 = cast<ConstantSDNode>(C.Op1);
uint64_t Value = ConstOp1->getZExtValue();
uint64_t Mask = (1 << NumBits) - 1;
if (Load->getExtensionType() == ISD::SEXTLOAD) {
  // Make sure that ConstOp1 is in range of C.Op0.
  int64_t SignedValue = ConstOp1->getSExtValue();
  if (uint64_t(SignedValue) + (uint64_t(1) << (NumBits - 1)) > Mask)
    return;
  if (C.ICmpType != SystemZICMP::SignedOnly) {
    // Unsigned comparison between two sign-extended values is equivalent
    // to unsigned comparison between two zero-extended values.
    Value &= Mask;
  } else if (NumBits == 8) {
    // Try to treat the comparison as unsigned, so that we can use CLI.
    // Adjust CCMask and Value as necessary.
    if (Value == 0 && C.CCMask == SystemZ::CCMASK_CMP_LT)
      // Test whether the high bit of the byte is set.
      Value = 127, C.CCMask = SystemZ::CCMASK_CMP_GT;
    else if (Value == 0 && C.CCMask == SystemZ::CCMASK_CMP_GE)
      // Test whether the high bit of the byte is clear.
      Value = 128, C.CCMask = SystemZ::CCMASK_CMP_LT;
    else
      // No instruction exists for this combination.
      return;
    C.ICmpType = SystemZICMP::UnsignedOnly;
  }
} else if (Load->getExtensionType() == ISD::ZEXTLOAD) {
  if (Value > Mask)
    return;
  // If the constant is in range, we can use any comparison.
  C.ICmpType = SystemZICMP::Any;
} else
  return;

// Make sure that the first operand is an i32 of the right extension type.
ISD::LoadExtType ExtType = (C.ICmpType == SystemZICMP::SignedOnly ?
                            ISD::SEXTLOAD :
                            ISD::ZEXTLOAD);
if (C.Op0.getValueType() != MVT::i32 ||
    Load->getExtensionType() != ExtType) {
  C.Op0 = DAG.getExtLoad(ExtType, SDLoc(Load), MVT::i32, Load->getChain(),
                         Load->getBasePtr(), Load->getPointerInfo(),
                         Load->getMemoryVT(), Load->getAlignment(),
                         Load->getMemOperand()->getFlags());
  // Update the chain uses.
  DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 1), C.Op0.getValue(1));
}

// Make sure that the second operand is an i32 with the right value.
if (C.Op1.getValueType() != MVT::i32 ||
    Value != ConstOp1->getZExtValue())
  C.Op1 = DAG.getConstant(Value, DL, MVT::i32);
2195}

2197// Return true if Op is either an unextended load, or a load suitable
2198// for integer register-memory comparisons of type ICmpType.
2199static bool isNaturalMemoryOperand(SDValue Op, unsigned ICmpType) {
auto *Load = dyn_cast<LoadSDNode>(Op.getNode());
if (Load) {
  // There are no instructions to compare a register with a memory byte.
  if (Load->getMemoryVT() == MVT::i8)
    return false;
  // Otherwise decide on extension type.
  switch (Load->getExtensionType()) {
  case ISD::NON_EXTLOAD:
    return true;
  case ISD::SEXTLOAD:
    return ICmpType != SystemZICMP::UnsignedOnly;
  case ISD::ZEXTLOAD:
    return ICmpType != SystemZICMP::SignedOnly;
  default:
    break;
  }
}
return false;
2218}

2220// Return true if it is better to swap the operands of C.
2221static bool shouldSwapCmpOperands(const Comparison &C) {
// Leave f128 comparisons alone, since they have no memory forms.
if (C.Op0.getValueType() == MVT::f128)
  return false;

// Always keep a floating-point constant second, since comparisons with
// zero can use LOAD TEST and comparisons with other constants make a
// natural memory operand.
if (isa<ConstantFPSDNode>(C.Op1))
  return false;

// Never swap comparisons with zero since there are many ways to optimize
// those later.
auto *ConstOp1 = dyn_cast<ConstantSDNode>(C.Op1);
if (ConstOp1 && ConstOp1->getZExtValue() == 0)
  return false;

// Also keep natural memory operands second if the loaded value is
// only used here.  Several comparisons have memory forms.
if (isNaturalMemoryOperand(C.Op1, C.ICmpType) && C.Op1.hasOneUse())
  return false;

// Look for cases where Cmp0 is a single-use load and Cmp1 isn't.
// In that case we generally prefer the memory to be second.
if (isNaturalMemoryOperand(C.Op0, C.ICmpType) && C.Op0.hasOneUse()) {
  // The only exceptions are when the second operand is a constant and
  // we can use things like CHHSI.
  if (!ConstOp1)
    return true;
  // The unsigned memory-immediate instructions can handle 16-bit
  // unsigned integers.
  if (C.ICmpType != SystemZICMP::SignedOnly &&
      isUInt<16>(ConstOp1->getZExtValue()))
    return false;
  // The signed memory-immediate instructions can handle 16-bit
  // signed integers.
  if (C.ICmpType != SystemZICMP::UnsignedOnly &&
      isInt<16>(ConstOp1->getSExtValue()))
    return false;
  return true;
}

// Try to promote the use of CGFR and CLGFR.
unsigned Opcode0 = C.Op0.getOpcode();
if (C.ICmpType != SystemZICMP::UnsignedOnly && Opcode0 == ISD::SIGN_EXTEND)
  return true;
if (C.ICmpType != SystemZICMP::SignedOnly && Opcode0 == ISD::ZERO_EXTEND)
  return true;
if (C.ICmpType != SystemZICMP::SignedOnly &&
    Opcode0 == ISD::AND &&
    C.Op0.getOperand(1).getOpcode() == ISD::Constant &&
    cast<ConstantSDNode>(C.Op0.getOperand(1))->getZExtValue() == 0xffffffff)
  return true;

return false;
2276}

2278// Check whether C tests for equality between X and Y and whether X - Y
2279// or Y - X is also computed.  In that case it's better to compare the
2280// result of the subtraction against zero.
2281static void adjustForSubtraction(SelectionDAG &DAG, const SDLoc &DL,
                               Comparison &C) {
if (C.CCMask == SystemZ::CCMASK_CMP_EQ ||
    C.CCMask == SystemZ::CCMASK_CMP_NE) {
  for (auto I = C.Op0->use_begin(), E = C.Op0->use_end(); I != E; ++I) {
    SDNode *N = *I;
    if (N->getOpcode() == ISD::SUB &&
        ((N->getOperand(0) == C.Op0 && N->getOperand(1) == C.Op1) ||
         (N->getOperand(0) == C.Op1 && N->getOperand(1) == C.Op0))) {
      C.Op0 = SDValue(N, 0);
      C.Op1 = DAG.getConstant(0, DL, N->getValueType(0));
      return;
    }
  }
}
2296}

2298// Check whether C compares a floating-point value with zero and if that
2299// floating-point value is also negated.  In this case we can use the
2300// negation to set CC, so avoiding separate LOAD AND TEST and
2301// LOAD (NEGATIVE/COMPLEMENT) instructions.
2302static void adjustForFNeg(Comparison &C) {
// This optimization is invalid for strict comparisons, since FNEG
// does not raise any exceptions.
if (C.Chain)
  return;
auto *C1 = dyn_cast<ConstantFPSDNode>(C.Op1);
if (C1 && C1->isZero()) {
  for (auto I = C.Op0->use_begin(), E = C.Op0->use_end(); I != E; ++I) {
    SDNode *N = *I;
    if (N->getOpcode() == ISD::FNEG) {
      C.Op0 = SDValue(N, 0);
      C.CCMask = SystemZ::reverseCCMask(C.CCMask);
      return;
    }
  }
}
2318}

2320// Check whether C compares (shl X, 32) with 0 and whether X is
2321// also sign-extended.  In that case it is better to test the result
2322// of the sign extension using LTGFR.
2323//
2324// This case is important because InstCombine transforms a comparison
2325// with (sext (trunc X)) into a comparison with (shl X, 32).
2326static void adjustForLTGFR(Comparison &C) {
// Check for a comparison between (shl X, 32) and 0.
if (C.Op0.getOpcode() == ISD::SHL &&
    C.Op0.getValueType() == MVT::i64 &&
    C.Op1.getOpcode() == ISD::Constant &&
    cast<ConstantSDNode>(C.Op1)->getZExtValue() == 0) {
  auto *C1 = dyn_cast<ConstantSDNode>(C.Op0.getOperand(1));
  if (C1 && C1->getZExtValue() == 32) {
    SDValue ShlOp0 = C.Op0.getOperand(0);
    // See whether X has any SIGN_EXTEND_INREG uses.
    for (auto I = ShlOp0->use_begin(), E = ShlOp0->use_end(); I != E; ++I) {
      SDNode *N = *I;
      if (N->getOpcode() == ISD::SIGN_EXTEND_INREG &&
          cast<VTSDNode>(N->getOperand(1))->getVT() == MVT::i32) {
        C.Op0 = SDValue(N, 0);
        return;
      }
    }
  }
}
2346}

2348// If C compares the truncation of an extending load, try to compare
2349// the untruncated value instead.  This exposes more opportunities to
2350// reuse CC.
2351static void adjustICmpTruncate(SelectionDAG &DAG, const SDLoc &DL,
                             Comparison &C) {
if (C.Op0.getOpcode() == ISD::TRUNCATE &&
    C.Op0.getOperand(0).getOpcode() == ISD::LOAD &&
    C.Op1.getOpcode() == ISD::Constant &&
    cast<ConstantSDNode>(C.Op1)->getZExtValue() == 0) {
  auto *L = cast<LoadSDNode>(C.Op0.getOperand(0));
  if (L->getMemoryVT().getStoreSizeInBits().getFixedSize() <=
      C.Op0.getValueSizeInBits().getFixedSize()) {
    unsigned Type = L->getExtensionType();
    if ((Type == ISD::ZEXTLOAD && C.ICmpType != SystemZICMP::SignedOnly) ||
        (Type == ISD::SEXTLOAD && C.ICmpType != SystemZICMP::UnsignedOnly)) {
      C.Op0 = C.Op0.getOperand(0);
      C.Op1 = DAG.getConstant(0, DL, C.Op0.getValueType());
    }
  }
}
2368}

2370// Return true if shift operation N has an in-range constant shift value.
2371// Store it in ShiftVal if so.
2372static bool isSimpleShift(SDValue N, unsigned &ShiftVal) {
auto *Shift = dyn_cast<ConstantSDNode>(N.getOperand(1));
if (!Shift)
  return false;

uint64_t Amount = Shift->getZExtValue();
if (Amount >= N.getValueSizeInBits())
  return false;

ShiftVal = Amount;
return true;
2383}

2385// Check whether an AND with Mask is suitable for a TEST UNDER MASK
2386// instruction and whether the CC value is descriptive enough to handle
2387// a comparison of type Opcode between the AND result and CmpVal.
2388// CCMask says which comparison result is being tested and BitSize is
2389// the number of bits in the operands.  If TEST UNDER MASK can be used,
2390// return the corresponding CC mask, otherwise return 0.
2391static unsigned getTestUnderMaskCond(unsigned BitSize, unsigned CCMask,
                                   uint64_t Mask, uint64_t CmpVal,
                                   unsigned ICmpType) {
assert(Mask != 0 && "ANDs with zero should have been removed by now")(static_cast <bool> (Mask != 0 && "ANDs with zero should have been removed by now"
) ? void (0) : __assert_fail ("Mask != 0 && \"ANDs with zero should have been removed by now\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp"
, 2394, __extension__ __PRETTY_FUNCTION__));

// Check whether the mask is suitable for TMHH, TMHL, TMLH or TMLL.
if (!SystemZ::isImmLL(Mask) && !SystemZ::isImmLH(Mask) &&
    !SystemZ::isImmHL(Mask) && !SystemZ::isImmHH(Mask))
  return 0;

// Work out the masks for the lowest and highest bits.
unsigned HighShift = 63 - countLeadingZeros(Mask);
uint64_t High = uint64_t(1) << HighShift;
uint64_t Low = uint64_t(1) << countTrailingZeros(Mask);

// Signed ordered comparisons are effectively unsigned if the sign
// bit is dropped.
bool EffectivelyUnsigned = (ICmpType != SystemZICMP::SignedOnly);

// Check for equality comparisons with 0, or the equivalent.
if (CmpVal == 0) {
  if (CCMask == SystemZ::CCMASK_CMP_EQ)
    return SystemZ::CCMASK_TM_ALL_0;
  if (CCMask == SystemZ::CCMASK_CMP_NE)
    return SystemZ::CCMASK_TM_SOME_1;
}
if (EffectivelyUnsigned && CmpVal > 0 && CmpVal <= Low) {
  if (CCMask == SystemZ::CCMASK_CMP_LT)
    return SystemZ::CCMASK_TM_ALL_0;
  if (CCMask == SystemZ::CCMASK_CMP_GE)
    return SystemZ::CCMASK_TM_SOME_1;
}
if (EffectivelyUnsigned && CmpVal < Low) {
  if (CCMask == SystemZ::CCMASK_CMP_LE)
    return SystemZ::CCMASK_TM_ALL_0;
  if (CCMask == SystemZ::CCMASK_CMP_GT)
    return SystemZ::CCMASK_TM_SOME_1;
}

// Check for equality comparisons with the mask, or the equivalent.
if (CmpVal == Mask) {
  if (CCMask == SystemZ::CCMASK_CMP_EQ)
    return SystemZ::CCMASK_TM_ALL_1;
  if (CCMask == SystemZ::CCMASK_CMP_NE)
    return SystemZ::CCMASK_TM_SOME_0;
}
if (EffectivelyUnsigned && CmpVal >= Mask - Low && CmpVal < Mask) {
  if (CCMask == SystemZ::CCMASK_CMP_GT)
    return SystemZ::CCMASK_TM_ALL_1;
  if (CCMask == SystemZ::CCMASK_CMP_LE)
    return SystemZ::CCMASK_TM_SOME_0;
}
if (EffectivelyUnsigned && CmpVal > Mask - Low && CmpVal <= Mask) {
  if (CCMask == SystemZ::CCMASK_CMP_GE)
    return SystemZ::CCMASK_TM_ALL_1;
  if (CCMask == SystemZ::CCMASK_CMP_LT)
    return SystemZ::CCMASK_TM_SOME_0;
}

// Check for ordered comparisons with the top bit.
if (EffectivelyUnsigned && CmpVal >= Mask - High && CmpVal < High) {
  if (CCMask == SystemZ::CCMASK_CMP_LE)
    return SystemZ::CCMASK_TM_MSB_0;
  if (CCMask == SystemZ::CCMASK_CMP_GT)
    return SystemZ::CCMASK_TM_MSB_1;
}
if (EffectivelyUnsigned && CmpVal > Mask - High && CmpVal <= High) {
  if (CCMask == SystemZ::CCMASK_CMP_LT)
    return SystemZ::CCMASK_TM_MSB_0;
  if (CCMask == SystemZ::CCMASK_CMP_GE)
    return SystemZ::CCMASK_TM_MSB_1;
}

// If there are just two bits, we can do equality checks for Low and High
// as well.
if (Mask == Low + High) {
  if (CCMask == SystemZ::CCMASK_CMP_EQ && CmpVal == Low)
    return SystemZ::CCMASK_TM_MIXED_MSB_0;
  if (CCMask == SystemZ::CCMASK_CMP_NE && CmpVal == Low)
    return SystemZ::CCMASK_TM_MIXED_MSB_0 ^ SystemZ::CCMASK_ANY;
  if (CCMask == SystemZ::CCMASK_CMP_EQ && CmpVal == High)
    return SystemZ::CCMASK_TM_MIXED_MSB_1;
  if (CCMask == SystemZ::CCMASK_CMP_NE && CmpVal == High)
    return SystemZ::CCMASK_TM_MIXED_MSB_1 ^ SystemZ::CCMASK_ANY;
}

// Looks like we've exhausted our options.
return 0;
2479}

2481// See whether C can be implemented as a TEST UNDER MASK instruction.
2482// Update the arguments with the TM version if so.
2483static void adjustForTestUnderMask(SelectionDAG &DAG, const SDLoc &DL,
                                 Comparison &C) {
// Check that we have a comparison with a constant.
auto *ConstOp1 = dyn_cast<ConstantSDNode>(C.Op1);
if (!ConstOp1)
  return;
uint64_t CmpVal = ConstOp1->getZExtValue();

// Check whether the nonconstant input is an AND with a constant mask.
Comparison NewC(C);
uint64_t MaskVal;
ConstantSDNode *Mask = nullptr;
if (C.Op0.getOpcode() == ISD::AND) {
  NewC.Op0 = C.Op0.getOperand(0);
  NewC.Op1 = C.Op0.getOperand(1);
  Mask = dyn_cast<ConstantSDNode>(NewC.Op1);
  if (!Mask)
    return;
  MaskVal = Mask->getZExtValue();
} else {
  // There is no instruction to compare with a 64-bit immediate
  // so use TMHH instead if possible.  We need an unsigned ordered
  // comparison with an i64 immediate.
  if (NewC.Op0.getValueType() != MVT::i64 ||
      NewC.CCMask == SystemZ::CCMASK_CMP_EQ ||
      NewC.CCMask == SystemZ::CCMASK_CMP_NE ||
      NewC.ICmpType == SystemZICMP::SignedOnly)
    return;
  // Convert LE and GT comparisons into LT and GE.
  if (NewC.CCMask == SystemZ::CCMASK_CMP_LE ||
      NewC.CCMask == SystemZ::CCMASK_CMP_GT) {
    if (CmpVal == uint64_t(-1))
      return;
    CmpVal += 1;
    NewC.CCMask ^= SystemZ::CCMASK_CMP_EQ;
  }
  // If the low N bits of Op1 are zero than the low N bits of Op0 can
  // be masked off without changing the result.
  MaskVal = -(CmpVal & -CmpVal);
  NewC.ICmpType = SystemZICMP::UnsignedOnly;
}
if (!MaskVal)
  return;

// Check whether the combination of mask, comparison value and comparison
// type are suitable.
unsigned BitSize = NewC.Op0.getValueSizeInBits();
unsigned NewCCMask, ShiftVal;
if (NewC.ICmpType != SystemZICMP::SignedOnly &&
    NewC.Op0.getOpcode() == ISD::SHL &&
    isSimpleShift(NewC.Op0, ShiftVal) &&
    (MaskVal >> ShiftVal != 0) &&
    ((CmpVal >> ShiftVal) << ShiftVal) == CmpVal &&
    (NewCCMask = getTestUnderMaskCond(BitSize, NewC.CCMask,
                                      MaskVal >> ShiftVal,
                                      CmpVal >> ShiftVal,
                                      SystemZICMP::Any))) {
  NewC.Op0 = NewC.Op0.getOperand(0);
  MaskVal >>= ShiftVal;
} else if (NewC.ICmpType != SystemZICMP::SignedOnly &&
           NewC.Op0.getOpcode() == ISD::SRL &&
           isSimpleShift(NewC.Op0, ShiftVal) &&
           (MaskVal << ShiftVal != 0) &&
           ((CmpVal << ShiftVal) >> ShiftVal) == CmpVal &&
           (NewCCMask = getTestUnderMaskCond(BitSize, NewC.CCMask,
                                             MaskVal << ShiftVal,
                                             CmpVal << ShiftVal,
                                             SystemZICMP::UnsignedOnly))) {
  NewC.Op0 = NewC.Op0.getOperand(0);
  MaskVal <<= ShiftVal;
} else {
  NewCCMask = getTestUnderMaskCond(BitSize, NewC.CCMask, MaskVal, CmpVal,
                                   NewC.ICmpType);
  if (!NewCCMask)
    return;
}

// Go ahead and make the change.
C.Opcode = SystemZISD::TM;
C.Op0 = NewC.Op0;
if (Mask && Mask->getZExtValue() == MaskVal)
  C.Op1 = SDValue(Mask, 0);
else
  C.Op1 = DAG.getConstant(MaskVal, DL, C.Op0.getValueType());
C.CCValid = SystemZ::CCMASK_TM;
C.CCMask = NewCCMask;
2569}

2571// See whether the comparison argument contains a redundant AND
2572// and remove it if so.  This sometimes happens due to the generic
2573// BRCOND expansion.
2574static void adjustForRedundantAnd(SelectionDAG &DAG, const SDLoc &DL,
                                Comparison &C) {
if (C.Op0.getOpcode() != ISD::AND)
  return;
auto *Mask = dyn_cast<ConstantSDNode>(C.Op0.getOperand(1));
if (!Mask)
  return;
KnownBits Known = DAG.computeKnownBits(C.Op0.getOperand(0));
if ((~Known.Zero).getZExtValue() & ~Mask->getZExtValue())
  return;

C.Op0 = C.Op0.getOperand(0);
2586}

2588// Return a Comparison that tests the condition-code result of intrinsic
2589// node Call against constant integer CC using comparison code Cond.
2590// Opcode is the opcode of the SystemZISD operation for the intrinsic
2591// and CCValid is the set of possible condition-code results.
2592static Comparison getIntrinsicCmp(SelectionDAG &DAG, unsigned Opcode,
                                SDValue Call, unsigned CCValid, uint64_t CC,
                                ISD::CondCode Cond) {
Comparison C(Call, SDValue(), SDValue());
C.Opcode = Opcode;
C.CCValid = CCValid;
if (Cond == ISD::SETEQ)
  // bit 3 for CC==0, bit 0 for CC==3, always false for CC>3.
  C.CCMask = CC < 4 ? 1 << (3 - CC) : 0;
else if (Cond == ISD::SETNE)
  // ...and the inverse of that.
  C.CCMask = CC < 4 ? ~(1 << (3 - CC)) : -1;
else if (Cond == ISD::SETLT || Cond == ISD::SETULT)
  // bits above bit 3 for CC==0 (always false), bits above bit 0 for CC==3,
  // always true for CC>3.
  C.CCMask = CC < 4 ? ~0U << (4 - CC) : -1;
else if (Cond == ISD::SETGE || Cond == ISD::SETUGE)
  // ...and the inverse of that.
  C.CCMask = CC < 4 ? ~(~0U << (4 - CC)) : 0;
else if (Cond == ISD::SETLE || Cond == ISD::SETULE)
  // bit 3 and above for CC==0, bit 0 and above for CC==3 (always true),
  // always true for CC>3.
  C.CCMask = CC < 4 ? ~0U << (3 - CC) : -1;
else if (Cond == ISD::SETGT || Cond == ISD::SETUGT)
  // ...and the inverse of that.
  C.CCMask = CC < 4 ? ~(~0U << (3 - CC)) : 0;
else
  llvm_unreachable("Unexpected integer comparison type")::llvm::llvm_unreachable_internal("Unexpected integer comparison type"
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp"
, 2619);
C.CCMask &= CCValid;
return C;
2622}

2624// Decide how to implement a comparison of type Cond between CmpOp0 with CmpOp1.
2625static Comparison getCmp(SelectionDAG &DAG, SDValue CmpOp0, SDValue CmpOp1,
                       ISD::CondCode Cond, const SDLoc &DL,
                       SDValue Chain = SDValue(),
                       bool IsSignaling = false) {
if (CmpOp1.getOpcode() == ISD::Constant) {
  assert(!Chain)(static_cast <bool> (!Chain) ? void (0) : __assert_fail
 ("!Chain", "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp"
, 2630, __extension__ __PRETTY_FUNCTION__));
  uint64_t Constant = cast<ConstantSDNode>(CmpOp1)->getZExtValue();
  unsigned Opcode, CCValid;
  if (CmpOp0.getOpcode() == ISD::INTRINSIC_W_CHAIN &&
      CmpOp0.getResNo() == 0 && CmpOp0->hasNUsesOfValue(1, 0) &&
      isIntrinsicWithCCAndChain(CmpOp0, Opcode, CCValid))
    return getIntrinsicCmp(DAG, Opcode, CmpOp0, CCValid, Constant, Cond);
  if (CmpOp0.getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
      CmpOp0.getResNo() == CmpOp0->getNumValues() - 1 &&
      isIntrinsicWithCC(CmpOp0, Opcode, CCValid))
    return getIntrinsicCmp(DAG, Opcode, CmpOp0, CCValid, Constant, Cond);
}
Comparison C(CmpOp0, CmpOp1, Chain);
C.CCMask = CCMaskForCondCode(Cond);
if (C.Op0.getValueType().isFloatingPoint()) {
  C.CCValid = SystemZ::CCMASK_FCMP;
  if (!C.Chain)
    C.Opcode = SystemZISD::FCMP;
  else if (!IsSignaling)
    C.Opcode = SystemZISD::STRICT_FCMP;
  else
    C.Opcode = SystemZISD::STRICT_FCMPS;
  adjustForFNeg(C);
} else {
  assert(!C.Chain)(static_cast <bool> (!C.Chain) ? void (0) : __assert_fail
 ("!C.Chain", "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp"
, 2654, __extension__ __PRETTY_FUNCTION__));
  C.CCValid = SystemZ::CCMASK_ICMP;
  C.Opcode = SystemZISD::ICMP;
  // Choose the type of comparison.  Equality and inequality tests can
  // use either signed or unsigned comparisons.  The choice also doesn't
  // matter if both sign bits are known to be clear.  In those cases we
  // want to give the main isel code the freedom to choose whichever
  // form fits best.
  if (C.CCMask == SystemZ::CCMASK_CMP_EQ ||
      C.CCMask == SystemZ::CCMASK_CMP_NE ||
      (DAG.SignBitIsZero(C.Op0) && DAG.SignBitIsZero(C.Op1)))
    C.ICmpType = SystemZICMP::Any;
  else if (C.CCMask & SystemZ::CCMASK_CMP_UO)
    C.ICmpType = SystemZICMP::UnsignedOnly;
  else
    C.ICmpType = SystemZICMP::SignedOnly;
  C.CCMask &= ~SystemZ::CCMASK_CMP_UO;
  adjustForRedundantAnd(DAG, DL, C);
  adjustZeroCmp(DAG, DL, C);
  adjustSubwordCmp(DAG, DL, C);
  adjustForSubtraction(DAG, DL, C);
  adjustForLTGFR(C);
  adjustICmpTruncate(DAG, DL, C);
}

if (shouldSwapCmpOperands(C)) {
  std::swap(C.Op0, C.Op1);
  C.CCMask = SystemZ::reverseCCMask(C.CCMask);
}

adjustForTestUnderMask(DAG, DL, C);
return C;
2686}

2688// Emit the comparison instruction described by C.
2689static SDValue emitCmp(SelectionDAG &DAG, const SDLoc &DL, Comparison &C) {
if (!C.Op1.getNode()) {
  SDNode *Node;
  switch (C.Op0.getOpcode()) {
  case ISD::INTRINSIC_W_CHAIN:
    Node = emitIntrinsicWithCCAndChain(DAG, C.Op0, C.Opcode);
    return SDValue(Node, 0);
  case ISD::INTRINSIC_WO_CHAIN:
    Node = emitIntrinsicWithCC(DAG, C.Op0, C.Opcode);
    return SDValue(Node, Node->getNumValues() - 1);
  default:
    llvm_unreachable("Invalid comparison operands")::llvm::llvm_unreachable_internal("Invalid comparison operands"
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp"
, 2700);
  }
}
if (C.Opcode == SystemZISD::ICMP)
  return DAG.getNode(SystemZISD::ICMP, DL, MVT::i32, C.Op0, C.Op1,
                     DAG.getTargetConstant(C.ICmpType, DL, MVT::i32));
if (C.Opcode == SystemZISD::TM) {
  bool RegisterOnly = (bool(C.CCMask & SystemZ::CCMASK_TM_MIXED_MSB_0) !=
                       bool(C.CCMask & SystemZ::CCMASK_TM_MIXED_MSB_1));
  return DAG.getNode(SystemZISD::TM, DL, MVT::i32, C.Op0, C.Op1,
                     DAG.getTargetConstant(RegisterOnly, DL, MVT::i32));
}
if (C.Chain) {
  SDVTList VTs = DAG.getVTList(MVT::i32, MVT::Other);
  return DAG.getNode(C.Opcode, DL, VTs, C.Chain, C.Op0, C.Op1);
}
return DAG.getNode(C.Opcode, DL, MVT::i32, C.Op0, C.Op1);
2717}

2719// Implement a 32-bit *MUL_LOHI operation by extending both operands to
2720// 64 bits.  Extend is the extension type to use.  Store the high part
2721// in Hi and the low part in Lo.
2722static void lowerMUL_LOHI32(SelectionDAG &DAG, const SDLoc &DL, unsigned Extend,
                          SDValue Op0, SDValue Op1, SDValue &Hi,
                          SDValue &Lo) {
Op0 = DAG.getNode(Extend, DL, MVT::i64, Op0);
Op1 = DAG.getNode(Extend, DL, MVT::i64, Op1);
SDValue Mul = DAG.getNode(ISD::MUL, DL, MVT::i64, Op0, Op1);
Hi = DAG.getNode(ISD::SRL, DL, MVT::i64, Mul,
                 DAG.getConstant(32, DL, MVT::i64));
Hi = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Hi);
Lo = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Mul);
2732}

2734// Lower a binary operation that produces two VT results, one in each
2735// half of a GR128 pair.  Op0 and Op1 are the VT operands to the operation,
2736// and Opcode performs the GR128 operation.  Store the even register result
2737// in Even and the odd register result in Odd.
2738static void lowerGR128Binary(SelectionDAG &DAG, const SDLoc &DL, EVT VT,
                           unsigned Opcode, SDValue Op0, SDValue Op1,
                           SDValue &Even, SDValue &Odd) {
SDValue Result = DAG.getNode(Opcode, DL, MVT::Untyped, Op0, Op1);
bool Is32Bit = is32Bit(VT);
Even = DAG.getTargetExtractSubreg(SystemZ::even128(Is32Bit), DL, VT, Result);
Odd = DAG.getTargetExtractSubreg(SystemZ::odd128(Is32Bit), DL, VT, Result);
2745}

2747// Return an i32 value that is 1 if the CC value produced by CCReg is
2748// in the mask CCMask and 0 otherwise.  CC is known to have a value
2749// in CCValid, so other values can be ignored.
2750static SDValue emitSETCC(SelectionDAG &DAG, const SDLoc &DL, SDValue CCReg,
                       unsigned CCValid, unsigned CCMask) {
SDValue Ops[] = {DAG.getConstant(1, DL, MVT::i32),
                 DAG.getConstant(0, DL, MVT::i32),
                 DAG.getTargetConstant(CCValid, DL, MVT::i32),
                 DAG.getTargetConstant(CCMask, DL, MVT::i32), CCReg};
return DAG.getNode(SystemZISD::SELECT_CCMASK, DL, MVT::i32, Ops);
2757}

2759// Return the SystemISD vector comparison operation for CC, or 0 if it cannot
2760// be done directly.  Mode is CmpMode::Int for integer comparisons, CmpMode::FP
2761// for regular floating-point comparisons, CmpMode::StrictFP for strict (quiet)
2762// floating-point comparisons, and CmpMode::SignalingFP for strict signaling
2763// floating-point comparisons.
2764enum class CmpMode { Int, FP, StrictFP, SignalingFP };
2765static unsigned getVectorComparison(ISD::CondCode CC, CmpMode Mode) {
switch (CC) {
case ISD::SETOEQ:
case ISD::SETEQ:
  switch (Mode) {
  case CmpMode::Int:         return SystemZISD::VICMPE;
  case CmpMode::FP:          return SystemZISD::VFCMPE;
  case CmpMode::StrictFP:    return SystemZISD::STRICT_VFCMPE;
  case CmpMode::SignalingFP: return SystemZISD::STRICT_VFCMPES;
  }
  llvm_unreachable("Bad mode")::llvm::llvm_unreachable_internal("Bad mode", "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp"
, 2775);

case ISD::SETOGE:
case ISD::SETGE:
  switch (Mode) {
  case CmpMode::Int:         return 0;
  case CmpMode::FP:          return SystemZISD::VFCMPHE;
  case CmpMode::StrictFP:    return SystemZISD::STRICT_VFCMPHE;
  case CmpMode::SignalingFP: return SystemZISD::STRICT_VFCMPHES;
  }
  llvm_unreachable("Bad mode")::llvm::llvm_unreachable_internal("Bad mode", "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp"
, 2785);

case ISD::SETOGT:
case ISD::SETGT:
  switch (Mode) {
  case CmpMode::Int:         return SystemZISD::VICMPH;
  case CmpMode::FP:          return SystemZISD::VFCMPH;
  case CmpMode::StrictFP:    return SystemZISD::STRICT_VFCMPH;
  case CmpMode::SignalingFP: return SystemZISD::STRICT_VFCMPHS;
  }
  llvm_unreachable("Bad mode")::llvm::llvm_unreachable_internal("Bad mode", "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp"
, 2795);

case ISD::SETUGT:
  switch (Mode) {
  case CmpMode::Int:         return SystemZISD::VICMPHL;
  case CmpMode::FP:          return 0;
  case CmpMode::StrictFP:    return 0;
  case CmpMode::SignalingFP: return 0;
  }
  llvm_unreachable("Bad mode")::llvm::llvm_unreachable_internal("Bad mode", "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp"
, 2804);

default:
  return 0;
}
2809}

2811// Return the SystemZISD vector comparison operation for CC or its inverse,
2812// or 0 if neither can be done directly.  Indicate in Invert whether the
2813// result is for the inverse of CC.  Mode is as above.
2814static unsigned getVectorComparisonOrInvert(ISD::CondCode CC, CmpMode Mode,
                                          bool &Invert) {
if (unsigned Opcode = getVectorComparison(CC, Mode)) {
  Invert = false;
  return Opcode;
}

CC = ISD::getSetCCInverse(CC, Mode == CmpMode::Int ? MVT::i32 : MVT::f32);
if (unsigned Opcode = getVectorComparison(CC, Mode)) {
  Invert = true;
  return Opcode;
}

return 0;
2828}

2830// Return a v2f64 that contains the extended form of elements Start and Start+1
2831// of v4f32 value Op.  If Chain is nonnull, return the strict form.
2832static SDValue expandV4F32ToV2F64(SelectionDAG &DAG, int Start, const SDLoc &DL,
                                SDValue Op, SDValue Chain) {
int Mask[] = { Start, -1, Start + 1, -1 };
Op = DAG.getVectorShuffle(MVT::v4f32, DL, Op, DAG.getUNDEF(MVT::v4f32), Mask);
if (Chain) {
  SDVTList VTs = DAG.getVTList(MVT::v2f64, MVT::Other);
  return DAG.getNode(SystemZISD::STRICT_VEXTEND, DL, VTs, Chain, Op);
}
return DAG.getNode(SystemZISD::VEXTEND, DL, MVT::v2f64, Op);
2841}

2843// Build a comparison of vectors CmpOp0 and CmpOp1 using opcode Opcode,
2844// producing a result of type VT.  If Chain is nonnull, return the strict form.
2845SDValue SystemZTargetLowering::getVectorCmp(SelectionDAG &DAG, unsigned Opcode,
                                          const SDLoc &DL, EVT VT,
                                          SDValue CmpOp0,
                                          SDValue CmpOp1,
                                          SDValue Chain) const {
// There is no hardware support for v4f32 (unless we have the vector
// enhancements facility 1), so extend the vector into two v2f64s
// and compare those.
if (CmpOp0.getValueType() == MVT::v4f32 &&
    !Subtarget.hasVectorEnhancements1()) {
  SDValue H0 = expandV4F32ToV2F64(DAG, 0, DL, CmpOp0, Chain);
  SDValue L0 = expandV4F32ToV2F64(DAG, 2, DL, CmpOp0, Chain);
  SDValue H1 = expandV4F32ToV2F64(DAG, 0, DL, CmpOp1, Chain);
  SDValue L1 = expandV4F32ToV2F64(DAG, 2, DL, CmpOp1, Chain);
  if (Chain) {
    SDVTList VTs = DAG.getVTList(MVT::v2i64, MVT::Other);
    SDValue HRes = DAG.getNode(Opcode, DL, VTs, Chain, H0, H1);
    SDValue LRes = DAG.getNode(Opcode, DL, VTs, Chain, L0, L1);
    SDValue Res = DAG.getNode(SystemZISD::PACK, DL, VT, HRes, LRes);
    SDValue Chains[6] = { H0.getValue(1), L0.getValue(1),
                          H1.getValue(1), L1.getValue(1),
                          HRes.getValue(1), LRes.getValue(1) };
    SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Chains);
    SDValue Ops[2] = { Res, NewChain };
    return DAG.getMergeValues(Ops, DL);
  }
  SDValue HRes = DAG.getNode(Opcode, DL, MVT::v2i64, H0, H1);
  SDValue LRes = DAG.getNode(Opcode, DL, MVT::v2i64, L0, L1);
  return DAG.getNode(SystemZISD::PACK, DL, VT, HRes, LRes);
}
if (Chain) {
  SDVTList VTs = DAG.getVTList(VT, MVT::Other);
  return DAG.getNode(Opcode, DL, VTs, Chain, CmpOp0, CmpOp1);
}
return DAG.getNode(Opcode, DL, VT, CmpOp0, CmpOp1);
2880}

2882// Lower a vector comparison of type CC between CmpOp0 and CmpOp1, producing
2883// an integer mask of type VT.  If Chain is nonnull, we have a strict
2884// floating-point comparison.  If in addition IsSignaling is true, we have
2885// a strict signaling floating-point comparison.
2886SDValue SystemZTargetLowering::lowerVectorSETCC(SelectionDAG &DAG,
                                              const SDLoc &DL, EVT VT,
                                              ISD::CondCode CC,
                                              SDValue CmpOp0,
                                              SDValue CmpOp1,
                                              SDValue Chain,
                                              bool IsSignaling) const {
bool IsFP = CmpOp0.getValueType().isFloatingPoint();
assert (!Chain || IsFP)(static_cast <bool> (!Chain || IsFP) ? void (0) : __assert_fail
 ("!Chain || IsFP", "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp"
, 2894, __extension__ __PRETTY_FUNCTION__));
assert (!IsSignaling || Chain)(static_cast <bool> (!IsSignaling || Chain) ? void (0) :
 __assert_fail ("!IsSignaling || Chain", "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp"
, 2895, __extension__ __PRETTY_FUNCTION__));
CmpMode Mode = IsSignaling ? CmpMode::SignalingFP :
               Chain ? CmpMode::StrictFP : IsFP ? CmpMode::FP : CmpMode::Int;
bool Invert = false;
SDValue Cmp;
switch (CC) {
  // Handle tests for order using (or (ogt y x) (oge x y)).
case ISD::SETUO:
  Invert = true;
  LLVM_FALLTHROUGH[[gnu::fallthrough]];
case ISD::SETO: {
  assert(IsFP && "Unexpected integer comparison")(static_cast <bool> (IsFP && "Unexpected integer comparison"
) ? void (0) : __assert_fail ("IsFP && \"Unexpected integer comparison\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp"
, 2906, __extension__ __PRETTY_FUNCTION__));
  SDValue LT = getVectorCmp(DAG, getVectorComparison(ISD::SETOGT, Mode),
                            DL, VT, CmpOp1, CmpOp0, Chain);
  SDValue GE = getVectorCmp(DAG, getVectorComparison(ISD::SETOGE, Mode),
                            DL, VT, CmpOp0, CmpOp1, Chain);
  Cmp = DAG.getNode(ISD::OR, DL, VT, LT, GE);
  if (Chain)
    Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
                        LT.getValue(1), GE.getValue(1));
  break;
}

  // Handle <> tests using (or (ogt y x) (ogt x y)).
case ISD::SETUEQ:
  Invert = true;
  LLVM_FALLTHROUGH[[gnu::fallthrough]];
case ISD::SETONE: {
  assert(IsFP && "Unexpected integer comparison")(static_cast <bool> (IsFP && "Unexpected integer comparison"
) ? void (0) : __assert_fail ("IsFP && \"Unexpected integer comparison\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp"
, 2923, __extension__ __PRETTY_FUNCTION__));
  SDValue LT = getVectorCmp(DAG, getVectorComparison(ISD::SETOGT, Mode),
                            DL, VT, CmpOp1, CmpOp0, Chain);
  SDValue GT = getVectorCmp(DAG, getVectorComparison(ISD::SETOGT, Mode),
                            DL, VT, CmpOp0, CmpOp1, Chain);
  Cmp = DAG.getNode(ISD::OR, DL, VT, LT, GT);
  if (Chain)
    Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
                        LT.getValue(1), GT.getValue(1));
  break;
}

  // Otherwise a single comparison is enough.  It doesn't really
  // matter whether we try the inversion or the swap first, since
  // there are no cases where both work.
default:
  if (unsigned Opcode = getVectorComparisonOrInvert(CC, Mode, Invert))
    Cmp = getVectorCmp(DAG, Opcode, DL, VT, CmpOp0, CmpOp1, Chain);
  else {
    CC = ISD::getSetCCSwappedOperands(CC);
    if (unsigned Opcode = getVectorComparisonOrInvert(CC, Mode, Invert))
      Cmp = getVectorCmp(DAG, Opcode, DL, VT, CmpOp1, CmpOp0, Chain);
    else
      llvm_unreachable("Unhandled comparison")::llvm::llvm_unreachable_internal("Unhandled comparison", "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp"
, 2946);
  }
  if (Chain)
    Chain = Cmp.getValue(1);
  break;
}
if (Invert) {
  SDValue Mask =
    DAG.getSplatBuildVector(VT, DL, DAG.getConstant(-1, DL, MVT::i64));
  Cmp = DAG.getNode(ISD::XOR, DL, VT, Cmp, Mask);
}
if (Chain && Chain.getNode() != Cmp.getNode()) {
  SDValue Ops[2] = { Cmp, Chain };
  Cmp = DAG.getMergeValues(Ops, DL);
}
return Cmp;
2962}

2964SDValue SystemZTargetLowering::lowerSETCC(SDValue Op,
                                        SelectionDAG &DAG) const {
SDValue CmpOp0   = Op.getOperand(0);
SDValue CmpOp1   = Op.getOperand(1);
ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
SDLoc DL(Op);
EVT VT = Op.getValueType();
if (VT.isVector())
  return lowerVectorSETCC(DAG, DL, VT, CC, CmpOp0, CmpOp1);

Comparison C(getCmp(DAG, CmpOp0, CmpOp1, CC, DL));
SDValue CCReg = emitCmp(DAG, DL, C);
return emitSETCC(DAG, DL, CCReg, C.CCValid, C.CCMask);
2977}

2979SDValue SystemZTargetLowering::lowerSTRICT_FSETCC(SDValue Op,
                                                SelectionDAG &DAG,
                                                bool IsSignaling) const {
SDValue Chain    = Op.getOperand(0);
SDValue CmpOp0   = Op.getOperand(1);
SDValue CmpOp1   = Op.getOperand(2);
ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(3))->get();
SDLoc DL(Op);
EVT VT = Op.getNode()->getValueType(0);
if (VT.isVector()) {
  SDValue Res = lowerVectorSETCC(DAG, DL, VT, CC, CmpOp0, CmpOp1,
                                 Chain, IsSignaling);
  return Res.getValue(Op.getResNo());
}

Comparison C(getCmp(DAG, CmpOp0, CmpOp1, CC, DL, Chain, IsSignaling));
SDValue CCReg = emitCmp(DAG, DL, C);
CCReg->setFlags(Op->getFlags());
SDValue Result = emitSETCC(DAG, DL, CCReg, C.CCValid, C.CCMask);
SDValue Ops[2] = { Result, CCReg.getValue(1) };
return DAG.getMergeValues(Ops, DL);
3000}

3002SDValue SystemZTargetLowering::lowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
SDValue CmpOp0   = Op.getOperand(2);
SDValue CmpOp1   = Op.getOperand(3);
SDValue Dest     = Op.getOperand(4);
SDLoc DL(Op);

Comparison C(getCmp(DAG, CmpOp0, CmpOp1, CC, DL));
SDValue CCReg = emitCmp(DAG, DL, C);
return DAG.getNode(
    SystemZISD::BR_CCMASK, DL, Op.getValueType(), Op.getOperand(0),
    DAG.getTargetConstant(C.CCValid, DL, MVT::i32),
    DAG.getTargetConstant(C.CCMask, DL, MVT::i32), Dest, CCReg);
3015}

3017// Return true if Pos is CmpOp and Neg is the negative of CmpOp,
3018// allowing Pos and Neg to be wider than CmpOp.
3019static bool isAbsolute(SDValue CmpOp, SDValue Pos, SDValue Neg) {
return (Neg.getOpcode() == ISD::SUB &&
        Neg.getOperand(0).getOpcode() == ISD::Constant &&
        cast<ConstantSDNode>(Neg.getOperand(0))->getZExtValue() == 0 &&
        Neg.getOperand(1) == Pos &&
        (Pos == CmpOp ||
         (Pos.getOpcode() == ISD::SIGN_EXTEND &&
          Pos.getOperand(0) == CmpOp)));
3027}

3029// Return the absolute or negative absolute of Op; IsNegative decides which.
3030static SDValue getAbsolute(SelectionDAG &DAG, const SDLoc &DL, SDValue Op,
                         bool IsNegative) {
Op = DAG.getNode(ISD::ABS, DL, Op.getValueType(), Op);
if (IsNegative)
  Op = DAG.getNode(ISD::SUB, DL, Op.getValueType(),
                   DAG.getConstant(0, DL, Op.getValueType()), Op);
return Op;
3037}

3039SDValue SystemZTargetLowering::lowerSELECT_CC(SDValue Op,
                                            SelectionDAG &DAG) const {
SDValue CmpOp0   = Op.getOperand(0);
SDValue CmpOp1   = Op.getOperand(1);
SDValue TrueOp   = Op.getOperand(2);
SDValue FalseOp  = Op.getOperand(3);
ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
SDLoc DL(Op);

Comparison C(getCmp(DAG, CmpOp0, CmpOp1, CC, DL));

// Check for absolute and negative-absolute selections, including those
// where the comparison value is sign-extended (for LPGFR and LNGFR).
// This check supplements the one in DAGCombiner.
if (C.Opcode == SystemZISD::ICMP &&
    C.CCMask != SystemZ::CCMASK_CMP_EQ &&
    C.CCMask != SystemZ::CCMASK_CMP_NE &&
    C.Op1.getOpcode() == ISD::Constant &&
    cast<ConstantSDNode>(C.Op1)->getZExtValue() == 0) {
  if (isAbsolute(C.Op0, TrueOp, FalseOp))
    return getAbsolute(DAG, DL, TrueOp, C.CCMask & SystemZ::CCMASK_CMP_LT);
  if (isAbsolute(C.Op0, FalseOp, TrueOp))
    return getAbsolute(DAG, DL, FalseOp, C.CCMask & SystemZ::CCMASK_CMP_GT);
}

SDValue CCReg = emitCmp(DAG, DL, C);
SDValue Ops[] = {TrueOp, FalseOp,
                 DAG.getTargetConstant(C.CCValid, DL, MVT::i32),
                 DAG.getTargetConstant(C.CCMask, DL, MVT::i32), CCReg};

return DAG.getNode(SystemZISD::SELECT_CCMASK, DL, Op.getValueType(), Ops);
3070}

3072SDValue SystemZTargetLowering::lowerGlobalAddress(GlobalAddressSDNode *Node,
                                                SelectionDAG &DAG) const {
SDLoc DL(Node);
const GlobalValue *GV = Node->getGlobal();
int64_t Offset = Node->getOffset();
EVT PtrVT = getPointerTy(DAG.getDataLayout());
CodeModel::Model CM = DAG.getTarget().getCodeModel();

SDValue Result;
if (Subtarget.isPC32DBLSymbol(GV, CM)) {
  if (isInt<32>(Offset)) {
    // Assign anchors at 1<<12 byte boundaries.
    uint64_t Anchor = Offset & ~uint64_t(0xfff);
    Result = DAG.getTargetGlobalAddress(GV, DL, PtrVT, Anchor);
    Result = DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Result);

    // The offset can be folded into the address if it is aligned to a
    // halfword.
    Offset -= Anchor;
    if (Offset != 0 && (Offset & 1) == 0) {
      SDValue Full =
        DAG.getTargetGlobalAddress(GV, DL, PtrVT, Anchor + Offset);
      Result = DAG.getNode(SystemZISD::PCREL_OFFSET, DL, PtrVT, Full, Result);
      Offset = 0;
    }
  } else {
    // Conservatively load a constant offset greater than 32 bits into a
    // register below.
    Result = DAG.getTargetGlobalAddress(GV, DL, PtrVT);
    Result = DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Result);
  }
} else {
  Result = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, SystemZII::MO_GOT);
  Result = DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Result);
  Result = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Result,
                       MachinePointerInfo::getGOT(DAG.getMachineFunction()));
}

// If there was a non-zero offset that we didn't fold, create an explicit
// addition for it.
if (Offset != 0)
  Result = DAG.getNode(ISD::ADD, DL, PtrVT, Result,
                       DAG.getConstant(Offset, DL, PtrVT));

return Result;
3117}

3119SDValue SystemZTargetLowering::lowerTLSGetOffset(GlobalAddressSDNode *Node,
                                               SelectionDAG &DAG,
                                               unsigned Opcode,
                                               SDValue GOTOffset) const {
SDLoc DL(Node);
EVT PtrVT = getPointerTy(DAG.getDataLayout());
SDValue Chain = DAG.getEntryNode();
SDValue Glue;

if (DAG.getMachineFunction().getFunction().getCallingConv() ==
    CallingConv::GHC)
  report_fatal_error("In GHC calling convention TLS is not supported");

// __tls_get_offset takes the GOT offset in %r2 and the GOT in %r12.
SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(PtrVT);
Chain = DAG.getCopyToReg(Chain, DL, SystemZ::R12D, GOT, Glue);
Glue = Chain.getValue(1);
Chain = DAG.getCopyToReg(Chain, DL, SystemZ::R2D, GOTOffset, Glue);
Glue = Chain.getValue(1);

// The first call operand is the chain and the second is the TLS symbol.
SmallVector<SDValue, 8> Ops;
Ops.push_back(Chain);
Ops.push_back(DAG.getTargetGlobalAddress(Node->getGlobal(), DL,
                                         Node->getValueType(0),
                                         0, 0));

// Add argument registers to the end of the list so that they are
// known live into the call.
Ops.push_back(DAG.getRegister(SystemZ::R2D, PtrVT));
Ops.push_back(DAG.getRegister(SystemZ::R12D, PtrVT));

// Add a register mask operand representing the call-preserved registers.
const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
const uint32_t *Mask =
    TRI->getCallPreservedMask(DAG.getMachineFunction(), CallingConv::C);
assert(Mask && "Missing call preserved mask for calling convention")(static_cast <bool> (Mask && "Missing call preserved mask for calling convention"
) ? void (0) : __assert_fail ("Mask && \"Missing call preserved mask for calling convention\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp"
, 3155, __extension__ __PRETTY_FUNCTION__));
Ops.push_back(DAG.getRegisterMask(Mask));

// Glue the call to the argument copies.
Ops.push_back(Glue);

// Emit the call.
SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
Chain = DAG.getNode(Opcode, DL, NodeTys, Ops);
Glue = Chain.getValue(1);

// Copy the return value from %r2.
return DAG.getCopyFromReg(Chain, DL, SystemZ::R2D, PtrVT, Glue);
3168}

3170SDValue SystemZTargetLowering::lowerThreadPointer(const SDLoc &DL,
                                                SelectionDAG &DAG) const {
SDValue Chain = DAG.getEntryNode();
EVT PtrVT = getPointerTy(DAG.getDataLayout());

// The high part of the thread pointer is in access register 0.
SDValue TPHi = DAG.getCopyFromReg(Chain, DL, SystemZ::A0, MVT::i32);
TPHi = DAG.getNode(ISD::ANY_EXTEND, DL, PtrVT, TPHi);

// The low part of the thread pointer is in access register 1.
SDValue TPLo = DAG.getCopyFromReg(Chain, DL, SystemZ::A1, MVT::i32);
TPLo = DAG.getNode(ISD::ZERO_EXTEND, DL, PtrVT, TPLo);

// Merge them into a single 64-bit address.
SDValue TPHiShifted = DAG.getNode(ISD::SHL, DL, PtrVT, TPHi,
                                  DAG.getConstant(32, DL, PtrVT));
return DAG.getNode(ISD::OR, DL, PtrVT, TPHiShifted, TPLo);
3187}

3189SDValue SystemZTargetLowering::lowerGlobalTLSAddress(GlobalAddressSDNode *Node,
                                                   SelectionDAG &DAG) const {
if (DAG.getTarget().useEmulatedTLS())
  return LowerToTLSEmulatedModel(Node, DAG);
SDLoc DL(Node);
const GlobalValue *GV = Node->getGlobal();
EVT PtrVT = getPointerTy(DAG.getDataLayout());
TLSModel::Model model = DAG.getTarget().getTLSModel(GV);

if (DAG.getMachineFunction().getFunction().getCallingConv() ==
    CallingConv::GHC)
  report_fatal_error("In GHC calling convention TLS is not supported");

SDValue TP = lowerThreadPointer(DL, DAG);

// Get the offset of GA from the thread pointer, based on the TLS model.
SDValue Offset;
switch (model) {
  case TLSModel::GeneralDynamic: {
    // Load the GOT offset of the tls_index (module ID / per-symbol offset).
    SystemZConstantPoolValue *CPV =
      SystemZConstantPoolValue::Create(GV, SystemZCP::TLSGD);

    Offset = DAG.getConstantPool(CPV, PtrVT, Align(8));
    Offset = DAG.getLoad(
        PtrVT, DL, DAG.getEntryNode(), Offset,
        MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));

    // Call __tls_get_offset to retrieve the offset.
    Offset = lowerTLSGetOffset(Node, DAG, SystemZISD::TLS_GDCALL, Offset);
    break;
  }

  case TLSModel::LocalDynamic: {
    // Load the GOT offset of the module ID.
    SystemZConstantPoolValue *CPV =
      SystemZConstantPoolValue::Create(GV, SystemZCP::TLSLDM);

    Offset = DAG.getConstantPool(CPV, PtrVT, Align(8));
    Offset = DAG.getLoad(
        PtrVT, DL, DAG.getEntryNode(), Offset,
        MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));

    // Call __tls_get_offset to retrieve the module base offset.
    Offset = lowerTLSGetOffset(Node, DAG, SystemZISD::TLS_LDCALL, Offset);

    // Note: The SystemZLDCleanupPass will remove redundant computations
    // of the module base offset.  Count total number of local-dynamic
    // accesses to trigger execution of that pass.
    SystemZMachineFunctionInfo* MFI =
      DAG.getMachineFunction().getInfo<SystemZMachineFunctionInfo>();
    MFI->incNumLocalDynamicTLSAccesses();

    // Add the per-symbol offset.
    CPV = SystemZConstantPoolValue::Create(GV, SystemZCP::DTPOFF);

    SDValue DTPOffset = DAG.getConstantPool(CPV, PtrVT, Align(8));
    DTPOffset = DAG.getLoad(
        PtrVT, DL, DAG.getEntryNode(), DTPOffset,
        MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));

    Offset = DAG.getNode(ISD::ADD, DL, PtrVT, Offset, DTPOffset);
    break;
  }

  case TLSModel::InitialExec: {
    // Load the offset from the GOT.
    Offset = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
                                        SystemZII::MO_INDNTPOFF);
    Offset = DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Offset);
    Offset =
        DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Offset,
                    MachinePointerInfo::getGOT(DAG.getMachineFunction()));
    break;
  }

  case TLSModel::LocalExec: {
    // Force the offset into the constant pool and load it from there.
    SystemZConstantPoolValue *CPV =
      SystemZConstantPoolValue::Create(GV, SystemZCP::NTPOFF);

    Offset = DAG.getConstantPool(CPV, PtrVT, Align(8));
    Offset = DAG.getLoad(
        PtrVT, DL, DAG.getEntryNode(), Offset,
        MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
    break;
  }
}

// Add the base and offset together.
return DAG.getNode(ISD::ADD, DL, PtrVT, TP, Offset);
3280}

3282SDValue SystemZTargetLowering::lowerBlockAddress(BlockAddressSDNode *Node,
                                               SelectionDAG &DAG) const {
SDLoc DL(Node);
const BlockAddress *BA = Node->getBlockAddress();
int64_t Offset = Node->getOffset();
EVT PtrVT = getPointerTy(DAG.getDataLayout());

SDValue Result = DAG.getTargetBlockAddress(BA, PtrVT, Offset);
Result = DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Result);
return Result;
3292}

3294SDValue SystemZTargetLowering::lowerJumpTable(JumpTableSDNode *JT,
                                            SelectionDAG &DAG) const {
SDLoc DL(JT);
EVT PtrVT = getPointerTy(DAG.getDataLayout());
SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);

// Use LARL to load the address of the table.
return DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Result);
3302}

3304SDValue SystemZTargetLowering::lowerConstantPool(ConstantPoolSDNode *CP,
                                               SelectionDAG &DAG) const {
SDLoc DL(CP);
EVT PtrVT = getPointerTy(DAG.getDataLayout());

SDValue Result;
if (CP->isMachineConstantPoolEntry())
  Result =
      DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT, CP->getAlign());
else
  Result = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CP->getAlign(),
                                     CP->getOffset());

// Use LARL to load the address of the constant pool entry.
return DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Result);
3319}

3321SDValue SystemZTargetLowering::lowerFRAMEADDR(SDValue Op,
                                            SelectionDAG &DAG) const {
auto *TFL =
    static_cast<const SystemZFrameLowering *>(Subtarget.getFrameLowering());
MachineFunction &MF = DAG.getMachineFunction();
MachineFrameInfo &MFI = MF.getFrameInfo();
MFI.setFrameAddressIsTaken(true);

SDLoc DL(Op);
unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
EVT PtrVT = getPointerTy(DAG.getDataLayout());

// By definition, the frame address is the address of the back chain.  (In
// the case of packed stack without backchain, return the address where the
// backchain would have been stored. This will either be an unused space or
// contain a saved register).
int BackChainIdx = TFL->getOrCreateFramePointerSaveIndex(MF);
SDValue BackChain = DAG.getFrameIndex(BackChainIdx, PtrVT);

// FIXME The frontend should detect this case.
if (Depth > 0) {
  report_fatal_error("Unsupported stack frame traversal count");
}

return BackChain;
3346}

3348SDValue SystemZTargetLowering::lowerRETURNADDR(SDValue Op,
                                             SelectionDAG &DAG) const {
MachineFunction &MF = DAG.getMachineFunction();
MachineFrameInfo &MFI = MF.getFrameInfo();
MFI.setReturnAddressIsTaken(true);

if (verifyReturnAddressArgumentIsConstant(Op, DAG))
  return SDValue();

SDLoc DL(Op);
unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
EVT PtrVT = getPointerTy(DAG.getDataLayout());

// FIXME The frontend should detect this case.
if (Depth > 0) {
  report_fatal_error("Unsupported stack frame traversal count");
}

// Return R14D, which has the return address. Mark it an implicit live-in.
unsigned LinkReg = MF.addLiveIn(SystemZ::R14D, &SystemZ::GR64BitRegClass);
return DAG.getCopyFromReg(DAG.getEntryNode(), DL, LinkReg, PtrVT);
3369}

3371SDValue SystemZTargetLowering::lowerBITCAST(SDValue Op,
                                          SelectionDAG &DAG) const {
SDLoc DL(Op);
SDValue In = Op.getOperand(0);
EVT InVT = In.getValueType();
EVT ResVT = Op.getValueType();

// Convert loads directly.  This is normally done by DAGCombiner,
// but we need this case for bitcasts that are created during lowering
// and which are then lowered themselves.
if (auto *LoadN = dyn_cast<LoadSDNode>(In))
  if (ISD::isNormalLoad(LoadN)) {
    SDValue NewLoad = DAG.getLoad(ResVT, DL, LoadN->getChain(),
                                  LoadN->getBasePtr(), LoadN->getMemOperand());
    // Update the chain uses.
    DAG.ReplaceAllUsesOfValueWith(SDValue(LoadN, 1), NewLoad.getValue(1));
    return NewLoad;
  }

if (InVT == MVT::i32 && ResVT == MVT::f32) {
  SDValue In64;
  if (Subtarget.hasHighWord()) {
    SDNode *U64 = DAG.getMachineNode(TargetOpcode::IMPLICIT_DEF, DL,
                                     MVT::i64);
    In64 = DAG.getTargetInsertSubreg(SystemZ::subreg_h32, DL,
                                     MVT::i64, SDValue(U64, 0), In);
  } else {
    In64 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, In);
    In64 = DAG.getNode(ISD::SHL, DL, MVT::i64, In64,
                       DAG.getConstant(32, DL, MVT::i64));
  }
  SDValue Out64 = DAG.getNode(ISD::BITCAST, DL, MVT::f64, In64);
  return DAG.getTargetExtractSubreg(SystemZ::subreg_h32,
                                    DL, MVT::f32, Out64);
}
if (InVT == MVT::f32 && ResVT == MVT::i32) {
  SDNode *U64 = DAG.getMachineNode(TargetOpcode::IMPLICIT_DEF, DL, MVT::f64);
  SDValue In64 = DAG.getTargetInsertSubreg(SystemZ::subreg_h32, DL,
                                           MVT::f64, SDValue(U64, 0), In);
  SDValue Out64 = DAG.getNode(ISD::BITCAST, DL, MVT::i64, In64);
  if (Subtarget.hasHighWord())
    return DAG.getTargetExtractSubreg(SystemZ::subreg_h32, DL,
                                      MVT::i32, Out64);
  SDValue Shift = DAG.getNode(ISD::SRL, DL, MVT::i64, Out64,
                              DAG.getConstant(32, DL, MVT::i64));
  return DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Shift);
}
llvm_unreachable("Unexpected bitcast combination")::llvm::llvm_unreachable_internal("Unexpected bitcast combination"
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp"
, 3418);
3419}

3421SDValue SystemZTargetLowering::lowerVASTART(SDValue Op,
                                          SelectionDAG &DAG) const {
MachineFunction &MF = DAG.getMachineFunction();
SystemZMachineFunctionInfo *FuncInfo =
  MF.getInfo<SystemZMachineFunctionInfo>();
EVT PtrVT = getPointerTy(DAG.getDataLayout());

SDValue Chain   = Op.getOperand(0);
SDValue Addr    = Op.getOperand(1);
const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
SDLoc DL(Op);

// The initial values of each field.
const unsigned NumFields = 4;
SDValue Fields[NumFields] = {
  DAG.getConstant(FuncInfo->getVarArgsFirstGPR(), DL, PtrVT),
  DAG.getConstant(FuncInfo->getVarArgsFirstFPR(), DL, PtrVT),
  DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT),
  DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(), PtrVT)
};

// Store each field into its respective slot.
SDValue MemOps[NumFields];
unsigned Offset = 0;
for (unsigned I = 0; I < NumFields; ++I) {
  SDValue FieldAddr = Addr;
  if (Offset != 0)
    FieldAddr = DAG.getNode(ISD::ADD, DL, PtrVT, FieldAddr,
                            DAG.getIntPtrConstant(Offset, DL));
  MemOps[I] = DAG.getStore(Chain, DL, Fields[I], FieldAddr,
                           MachinePointerInfo(SV, Offset));
  Offset += 8;
}
return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
3455}

3457SDValue SystemZTargetLowering::lowerVACOPY(SDValue Op,
                                         SelectionDAG &DAG) const {
SDValue Chain      = Op.getOperand(0);
SDValue DstPtr     = Op.getOperand(1);
SDValue SrcPtr     = Op.getOperand(2);
const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
SDLoc DL(Op);

return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr, DAG.getIntPtrConstant(32, DL),
                     Align(8), /*isVolatile*/ false, /*AlwaysInline*/ false,
                     /*isTailCall*/ false, MachinePointerInfo(DstSV),
                     MachinePointerInfo(SrcSV));
3470}

3472SDValue SystemZTargetLowering::
3473lowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const {
const TargetFrameLowering *TFI = Subtarget.getFrameLowering();
MachineFunction &MF = DAG.getMachineFunction();
bool RealignOpt = !MF.getFunction().hasFnAttribute("no-realign-stack");
bool StoreBackchain = MF.getFunction().hasFnAttribute("backchain");

SDValue Chain = Op.getOperand(0);
SDValue Size  = Op.getOperand(1);
SDValue Align = Op.getOperand(2);
SDLoc DL(Op);

// If user has set the no alignment function attribute, ignore
// alloca alignments.
uint64_t AlignVal =
    (RealignOpt ? cast<ConstantSDNode>(Align)->getZExtValue() : 0);

uint64_t StackAlign = TFI->getStackAlignment();
uint64_t RequiredAlign = std::max(AlignVal, StackAlign);
uint64_t ExtraAlignSpace = RequiredAlign - StackAlign;

Register SPReg = getStackPointerRegisterToSaveRestore();
SDValue NeededSpace = Size;

// Get a reference to the stack pointer.
SDValue OldSP = DAG.getCopyFromReg(Chain, DL, SPReg, MVT::i64);

// If we need a backchain, save it now.
SDValue Backchain;
if (StoreBackchain)
  Backchain = DAG.getLoad(MVT::i64, DL, Chain, getBackchainAddress(OldSP, DAG),
                          MachinePointerInfo());

// Add extra space for alignment if needed.
if (ExtraAlignSpace)
  NeededSpace = DAG.getNode(ISD::ADD, DL, MVT::i64, NeededSpace,
                            DAG.getConstant(ExtraAlignSpace, DL, MVT::i64));

// Get the new stack pointer value.
SDValue NewSP;
if (hasInlineStackProbe(MF)) {
  NewSP = DAG.getNode(SystemZISD::PROBED_ALLOCA, DL,
              DAG.getVTList(MVT::i64, MVT::Other), Chain, OldSP, NeededSpace);
  Chain = NewSP.getValue(1);
}
else {
  NewSP = DAG.getNode(ISD::SUB, DL, MVT::i64, OldSP, NeededSpace);
  // Copy the new stack pointer back.
  Chain = DAG.getCopyToReg(Chain, DL, SPReg, NewSP);
}

// The allocated data lives above the 160 bytes allocated for the standard
// frame, plus any outgoing stack arguments.  We don't know how much that
// amounts to yet, so emit a special ADJDYNALLOC placeholder.
SDValue ArgAdjust = DAG.getNode(SystemZISD::ADJDYNALLOC, DL, MVT::i64);
SDValue Result = DAG.getNode(ISD::ADD, DL, MVT::i64, NewSP, ArgAdjust);

// Dynamically realign if needed.
if (RequiredAlign > StackAlign) {
  Result =
    DAG.getNode(ISD::ADD, DL, MVT::i64, Result,
                DAG.getConstant(ExtraAlignSpace, DL, MVT::i64));
  Result =
    DAG.getNode(ISD::AND, DL, MVT::i64, Result,
                DAG.getConstant(~(RequiredAlign - 1), DL, MVT::i64));
}

if (StoreBackchain)
  Chain = DAG.getStore(Chain, DL, Backchain, getBackchainAddress(NewSP, DAG),
                       MachinePointerInfo());

SDValue Ops[2] = { Result, Chain };
return DAG.getMergeValues(Ops, DL);
3545}

3547SDValue SystemZTargetLowering::lowerGET_DYNAMIC_AREA_OFFSET(
  SDValue Op, SelectionDAG &DAG) const {
SDLoc DL(Op);

return DAG.getNode(SystemZISD::ADJDYNALLOC, DL, MVT::i64);
3552}

3554SDValue SystemZTargetLowering::lowerSMUL_LOHI(SDValue Op,
                                            SelectionDAG &DAG) const {
EVT VT = Op.getValueType();
SDLoc DL(Op);
SDValue Ops[2];
if (is32Bit(VT))
  // Just do a normal 64-bit multiplication and extract the results.
  // We define this so that it can be used for constant division.
  lowerMUL_LOHI32(DAG, DL, ISD::SIGN_EXTEND, Op.getOperand(0),
                  Op.getOperand(1), Ops[1], Ops[0]);
else if (Subtarget.hasMiscellaneousExtensions2())
  // SystemZISD::SMUL_LOHI returns the low result in the odd register and
  // the high result in the even register.  ISD::SMUL_LOHI is defined to
  // return the low half first, so the results are in reverse order.
  lowerGR128Binary(DAG, DL, VT, SystemZISD::SMUL_LOHI,
                   Op.getOperand(0), Op.getOperand(1), Ops[1], Ops[0]);
else {
  // Do a full 128-bit multiplication based on SystemZISD::UMUL_LOHI:
  //
  //   (ll * rl) + ((lh * rl) << 64) + ((ll * rh) << 64)
  //
  // but using the fact that the upper halves are either all zeros
  // or all ones:
  //
  //   (ll * rl) - ((lh & rl) << 64) - ((ll & rh) << 64)
  //
  // and grouping the right terms together since they are quicker than the
  // multiplication:
  //
  //   (ll * rl) - (((lh & rl) + (ll & rh)) << 64)
  SDValue C63 = DAG.getConstant(63, DL, MVT::i64);
  SDValue LL = Op.getOperand(0);
  SDValue RL = Op.getOperand(1);
  SDValue LH = DAG.getNode(ISD::SRA, DL, VT, LL, C63);
  SDValue RH = DAG.getNode(ISD::SRA, DL, VT, RL, C63);
  // SystemZISD::UMUL_LOHI returns the low result in the odd register and
  // the high result in the even register.  ISD::SMUL_LOHI is defined to
  // return the low half first, so the results are in reverse order.
  lowerGR128Binary(DAG, DL, VT, SystemZISD::UMUL_LOHI,
                   LL, RL, Ops[1], Ops[0]);
  SDValue NegLLTimesRH = DAG.getNode(ISD::AND, DL, VT, LL, RH);
  SDValue NegLHTimesRL = DAG.getNode(ISD::AND, DL, VT, LH, RL);
  SDValue NegSum = DAG.getNode(ISD::ADD, DL, VT, NegLLTimesRH, NegLHTimesRL);
  Ops[1] = DAG.getNode(ISD::SUB, DL, VT, Ops[1], NegSum);
}
return DAG.getMergeValues(Ops, DL);
3600}

3602SDValue SystemZTargetLowering::lowerUMUL_LOHI(SDValue Op,
                                            SelectionDAG &DAG) const {
EVT VT = Op.getValueType();
SDLoc DL(Op);
SDValue Ops[2];
if (is32Bit(VT))
  // Just do a normal 64-bit multiplication and extract the results.
  // We define this so that it can be used for constant division.
  lowerMUL_LOHI32(DAG, DL, ISD::ZERO_EXTEND, Op.getOperand(0),
                  Op.getOperand(1), Ops[1], Ops[0]);
else
  // SystemZISD::UMUL_LOHI returns the low result in the odd register and
  // the high result in the even register.  ISD::UMUL_LOHI is defined to
  // return the low half first, so the results are in reverse order.
  lowerGR128Binary(DAG, DL, VT, SystemZISD::UMUL_LOHI,
                   Op.getOperand(0), Op.getOperand(1), Ops[1], Ops[0]);
return DAG.getMergeValues(Ops, DL);
3619}

3621SDValue SystemZTargetLowering::lowerSDIVREM(SDValue Op,
                                          SelectionDAG &DAG) const {
SDValue Op0 = Op.getOperand(0);
SDValue Op1 = Op.getOperand(1);
EVT VT = Op.getValueType();
SDLoc DL(Op);

// We use DSGF for 32-bit division.  This means the first operand must
// always be 64-bit, and the second operand should be 32-bit whenever
// that is possible, to improve performance.
if (is32Bit(VT))
  Op0 = DAG.getNode(ISD::SIGN_EXTEND, DL, MVT::i64, Op0);
else if (DAG.ComputeNumSignBits(Op1) > 32)
  Op1 = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Op1);

// DSG(F) returns the remainder in the even register and the
// quotient in the odd register.
SDValue Ops[2];
lowerGR128Binary(DAG, DL, VT, SystemZISD::SDIVREM, Op0, Op1, Ops[1], Ops[0]);
return DAG.getMergeValues(Ops, DL);
3641}

3643SDValue SystemZTargetLowering::lowerUDIVREM(SDValue Op,
                                          SelectionDAG &DAG) const {
EVT VT = Op.getValueType();
SDLoc DL(Op);

// DL(G) returns the remainder in the even register and the
// quotient in the odd register.
SDValue Ops[2];
lowerGR128Binary(DAG, DL, VT, SystemZISD::UDIVREM,
                 Op.getOperand(0), Op.getOperand(1), Ops[1], Ops[0]);
return DAG.getMergeValues(Ops, DL);
3654}

3656SDValue SystemZTargetLowering::lowerOR(SDValue Op, SelectionDAG &DAG) const {
assert(Op.getValueType() == MVT::i64 && "Should be 64-bit operation")(static_cast <bool> (Op.getValueType() == MVT::i64 &&
 "Should be 64-bit operation") ? void (0) : __assert_fail ("Op.getValueType() == MVT::i64 && \"Should be 64-bit operation\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp"
, 3657, __extension__ __PRETTY_FUNCTION__));

// Get the known-zero masks for each operand.
SDValue Ops[] = {Op.getOperand(0), Op.getOperand(1)};
KnownBits Known[2] = {DAG.computeKnownBits(Ops[0]),
                      DAG.computeKnownBits(Ops[1])};

// See if the upper 32 bits of one operand and the lower 32 bits of the
// other are known zero.  They are the low and high operands respectively.
uint64_t Masks[] = { Known[0].Zero.getZExtValue(),
                     Known[1].Zero.getZExtValue() };
unsigned High, Low;
if ((Masks[0] >> 32) == 0xffffffff && uint32_t(Masks[1]) == 0xffffffff)
  High = 1, Low = 0;
else if ((Masks[1] >> 32) == 0xffffffff && uint32_t(Masks[0]) == 0xffffffff)
  High = 0, Low = 1;
else
  return Op;

SDValue LowOp = Ops[Low];
SDValue HighOp = Ops[High];

// If the high part is a constant, we're better off using IILH.
if (HighOp.getOpcode() == ISD::Constant)
  return Op;

// If the low part is a constant that is outside the range of LHI,
// then we're better off using IILF.
if (LowOp.getOpcode() == ISD::Constant) {
  int64_t Value = int32_t(cast<ConstantSDNode>(LowOp)->getZExtValue());
  if (!isInt<16>(Value))
    return Op;
}

// Check whether the high part is an AND that doesn't change the
// high 32 bits and just masks out low bits.  We can skip it if so.
if (HighOp.getOpcode() == ISD::AND &&
    HighOp.getOperand(1).getOpcode() == ISD::Constant) {
  SDValue HighOp0 = HighOp.getOperand(0);
  uint64_t Mask = cast<ConstantSDNode>(HighOp.getOperand(1))->getZExtValue();
  if (DAG.MaskedValueIsZero(HighOp0, APInt(64, ~(Mask | 0xffffffff))))
    HighOp = HighOp0;
}

// Take advantage of the fact that all GR32 operations only change the
// low 32 bits by truncating Low to an i32 and inserting it directly
// using a subreg.  The interesting cases are those where the truncation
// can be folded.
SDLoc DL(Op);
SDValue Low32 = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, LowOp);
return DAG.getTargetInsertSubreg(SystemZ::subreg_l32, DL,
                                 MVT::i64, HighOp, Low32);
3709}

3711// Lower SADDO/SSUBO/UADDO/USUBO nodes.
3712SDValue SystemZTargetLowering::lowerXALUO(SDValue Op,
                                        SelectionDAG &DAG) const {
SDNode *N = Op.getNode();
SDValue LHS = N->getOperand(0);
SDValue RHS = N->getOperand(1);
SDLoc DL(N);
unsigned BaseOp = 0;
unsigned CCValid = 0;
unsigned CCMask = 0;

switch (Op.getOpcode()) {
default: llvm_unreachable("Unknown instruction!")::llvm::llvm_unreachable_internal("Unknown instruction!", "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp"
, 3723);
case ISD::SADDO:
  BaseOp = SystemZISD::SADDO;
  CCValid = SystemZ::CCMASK_ARITH;
  CCMask = SystemZ::CCMASK_ARITH_OVERFLOW;
  break;
case ISD::SSUBO:
  BaseOp = SystemZISD::SSUBO;
  CCValid = SystemZ::CCMASK_ARITH;
  CCMask = SystemZ::CCMASK_ARITH_OVERFLOW;
  break;
case ISD::UADDO:
  BaseOp = SystemZISD::UADDO;
  CCValid = SystemZ::CCMASK_LOGICAL;
  CCMask = SystemZ::CCMASK_LOGICAL_CARRY;
  break;
case ISD::USUBO:
  BaseOp = SystemZISD::USUBO;
  CCValid = SystemZ::CCMASK_LOGICAL;
  CCMask = SystemZ::CCMASK_LOGICAL_BORROW;
  break;
}

SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
SDValue Result = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);

SDValue SetCC = emitSETCC(DAG, DL, Result.getValue(1), CCValid, CCMask);
if (N->getValueType(1) == MVT::i1)
  SetCC = DAG.getNode(ISD::TRUNCATE, DL, MVT::i1, SetCC);

return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Result, SetCC);
3754}

3756static bool isAddCarryChain(SDValue Carry) {
while (Carry.getOpcode() == ISD::ADDCARRY)
  Carry = Carry.getOperand(2);
return Carry.getOpcode() == ISD::UADDO;
3760}

3762static bool isSubBorrowChain(SDValue Carry) {
while (Carry.getOpcode() == ISD::SUBCARRY)
  Carry = Carry.getOperand(2);
return Carry.getOpcode() == ISD::USUBO;
3766}

3768// Lower ADDCARRY/SUBCARRY nodes.
3769SDValue SystemZTargetLowering::lowerADDSUBCARRY(SDValue Op,
                                              SelectionDAG &DAG) const {

SDNode *N = Op.getNode();
MVT VT = N->getSimpleValueType(0);

// Let legalize expand this if it isn't a legal type yet.
if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
  return SDValue();

SDValue LHS = N->getOperand(0);
SDValue RHS = N->getOperand(1);
SDValue Carry = Op.getOperand(2);
SDLoc DL(N);
unsigned BaseOp = 0;
unsigned CCValid = 0;
unsigned CCMask = 0;

switch (Op.getOpcode()) {
default: llvm_unreachable("Unknown instruction!")::llvm::llvm_unreachable_internal("Unknown instruction!", "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp"
, 3788);
case ISD::ADDCARRY:
  if (!isAddCarryChain(Carry))
    return SDValue();

  BaseOp = SystemZISD::ADDCARRY;
  CCValid = SystemZ::CCMASK_LOGICAL;
  CCMask = SystemZ::CCMASK_LOGICAL_CARRY;
  break;
case ISD::SUBCARRY:
  if (!isSubBorrowChain(Carry))
    return SDValue();

  BaseOp = SystemZISD::SUBCARRY;
  CCValid = SystemZ::CCMASK_LOGICAL;
  CCMask = SystemZ::CCMASK_LOGICAL_BORROW;
  break;
}

// Set the condition code from the carry flag.
Carry = DAG.getNode(SystemZISD::GET_CCMASK, DL, MVT::i32, Carry,
                    DAG.getConstant(CCValid, DL, MVT::i32),
                    DAG.getConstant(CCMask, DL, MVT::i32));

SDVTList VTs = DAG.getVTList(VT, MVT::i32);
SDValue Result = DAG.getNode(BaseOp, DL, VTs, LHS, RHS, Carry);

SDValue SetCC = emitSETCC(DAG, DL, Result.getValue(1), CCValid, CCMask);
if (N->getValueType(1) == MVT::i1)
  SetCC = DAG.getNode(ISD::TRUNCATE, DL, MVT::i1, SetCC);

return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Result, SetCC);
3820}

3822SDValue SystemZTargetLowering::lowerCTPOP(SDValue Op,
                                        SelectionDAG &DAG) const {
EVT VT = Op.getValueType();
SDLoc DL(Op);
Op = Op.getOperand(0);

// Handle vector types via VPOPCT.
if (VT.isVector()) {
  Op = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Op);
  Op = DAG.getNode(SystemZISD::POPCNT, DL, MVT::v16i8, Op);
  switch (VT.getScalarSizeInBits()) {
  case 8:
    break;
  case 16: {
    Op = DAG.getNode(ISD::BITCAST, DL, VT, Op);
    SDValue Shift = DAG.getConstant(8, DL, MVT::i32);
    SDValue Tmp = DAG.getNode(SystemZISD::VSHL_BY_SCALAR, DL, VT, Op, Shift);
    Op = DAG.getNode(ISD::ADD, DL, VT, Op, Tmp);
    Op = DAG.getNode(SystemZISD::VSRL_BY_SCALAR, DL, VT, Op, Shift);
    break;
  }
  case 32: {
    SDValue Tmp = DAG.getSplatBuildVector(MVT::v16i8, DL,
                                          DAG.getConstant(0, DL, MVT::i32));
    Op = DAG.getNode(SystemZISD::VSUM, DL, VT, Op, Tmp);
    break;
  }
  case 64: {
    SDValue Tmp = DAG.getSplatBuildVector(MVT::v16i8, DL,
                                          DAG.getConstant(0, DL, MVT::i32));
    Op = DAG.getNode(SystemZISD::VSUM, DL, MVT::v4i32, Op, Tmp);
    Op = DAG.getNode(SystemZISD::VSUM, DL, VT, Op, Tmp);
    break;
  }
  default:
    llvm_unreachable("Unexpected type")::llvm::llvm_unreachable_internal("Unexpected type", "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp"
, 3857);
  }
  return Op;
}

// Get the known-zero mask for the operand.
KnownBits Known = DAG.computeKnownBits(Op);
unsigned NumSignificantBits = Known.getMaxValue().getActiveBits();
if (NumSignificantBits == 0)
  return DAG.getConstant(0, DL, VT);

// Skip known-zero high parts of the operand.
int64_t OrigBitSize = VT.getSizeInBits();
int64_t BitSize = (int64_t)1 << Log2_32_Ceil(NumSignificantBits);
BitSize = std::min(BitSize, OrigBitSize);

// The POPCNT instruction counts the number of bits in each byte.
Op = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, Op);
Op = DAG.getNode(SystemZISD::POPCNT, DL, MVT::i64, Op);
Op = DAG.getNode(ISD::TRUNCATE, DL, VT, Op);

// Add up per-byte counts in a binary tree.  All bits of Op at
// position larger than BitSize remain zero throughout.
for (int64_t I = BitSize / 2; I >= 8; I = I / 2) {
  SDValue Tmp = DAG.getNode(ISD::SHL, DL, VT, Op, DAG.getConstant(I, DL, VT));
  if (BitSize != OrigBitSize)
    Tmp = DAG.getNode(ISD::AND, DL, VT, Tmp,
                      DAG.getConstant(((uint64_t)1 << BitSize) - 1, DL, VT));
  Op = DAG.getNode(ISD::ADD, DL, VT, Op, Tmp);
}

// Extract overall result from high byte.
if (BitSize > 8)
  Op = DAG.getNode(ISD::SRL, DL, VT, Op,
                   DAG.getConstant(BitSize - 8, DL, VT));

return Op;
3894}

3896SDValue SystemZTargetLowering::lowerATOMIC_FENCE(SDValue Op,
                                               SelectionDAG &DAG) const {
SDLoc DL(Op);
AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
  cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
SyncScope::ID FenceSSID = static_cast<SyncScope::ID>(
  cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());

// The only fence that needs an instruction is a sequentially-consistent
// cross-thread fence.
if (FenceOrdering == AtomicOrdering::SequentiallyConsistent &&
    FenceSSID == SyncScope::System) {
  return SDValue(DAG.getMachineNode(SystemZ::Serialize, DL, MVT::Other,
                                    Op.getOperand(0)),
                 0);
}

// MEMBARRIER is a compiler barrier; it codegens to a no-op.
return DAG.getNode(SystemZISD::MEMBARRIER, DL, MVT::Other, Op.getOperand(0));
3915}

3917// Op is an atomic load.  Lower it into a normal volatile load.
3918SDValue SystemZTargetLowering::lowerATOMIC_LOAD(SDValue Op,
                                              SelectionDAG &DAG) const {
auto *Node = cast<AtomicSDNode>(Op.getNode());
return DAG.getExtLoad(ISD::EXTLOAD, SDLoc(Op), Op.getValueType(),
                      Node->getChain(), Node->getBasePtr(),
                      Node->getMemoryVT(), Node->getMemOperand());
3924}

3926// Op is an atomic store.  Lower it into a normal volatile store.
3927SDValue SystemZTargetLowering::lowerATOMIC_STORE(SDValue Op,
                                               SelectionDAG &DAG) const {
auto *Node = cast<AtomicSDNode>(Op.getNode());
SDValue Chain = DAG.getTruncStore(Node->getChain(), SDLoc(Op), Node->getVal(),
                                  Node->getBasePtr(), Node->getMemoryVT(),
                                  Node->getMemOperand());
// We have to enforce sequential consistency by performing a
// serialization operation after the store.
if (Node->getSuccessOrdering() == AtomicOrdering::SequentiallyConsistent)
  Chain = SDValue(DAG.getMachineNode(SystemZ::Serialize, SDLoc(Op),
                                     MVT::Other, Chain), 0);
return Chain;
3939}

3941// Op is an 8-, 16-bit or 32-bit ATOMIC_LOAD_* operation.  Lower the first
3942// two into the fullword ATOMIC_LOADW_* operation given by Opcode.
3943SDValue SystemZTargetLowering::lowerATOMIC_LOAD_OP(SDValue Op,
                                                 SelectionDAG &DAG,
                                                 unsigned Opcode) const {
auto *Node = cast<AtomicSDNode>(Op.getNode());

// 32-bit operations need no code outside the main loop.
EVT NarrowVT = Node->getMemoryVT();
EVT WideVT = MVT::i32;
if (NarrowVT == WideVT)
  return Op;

int64_t BitSize = NarrowVT.getSizeInBits();
SDValue ChainIn = Node->getChain();
SDValue Addr = Node->getBasePtr();
SDValue Src2 = Node->getVal();
MachineMemOperand *MMO = Node->getMemOperand();
SDLoc DL(Node);
EVT PtrVT = Addr.getValueType();

// Convert atomic subtracts of constants into additions.
if (Opcode == SystemZISD::ATOMIC_LOADW_SUB)
  if (auto *Const = dyn_cast<ConstantSDNode>(Src2)) {
    Opcode = SystemZISD::ATOMIC_LOADW_ADD;
    Src2 = DAG.getConstant(-Const->getSExtValue(), DL, Src2.getValueType());
  }

// Get the address of the containing word.
SDValue AlignedAddr = DAG.getNode(ISD::AND, DL, PtrVT, Addr,
                                  DAG.getConstant(-4, DL, PtrVT));

// Get the number of bits that the word must be rotated left in order
// to bring the field to the top bits of a GR32.
SDValue BitShift = DAG.getNode(ISD::SHL, DL, PtrVT, Addr,
                               DAG.getConstant(3, DL, PtrVT));
BitShift = DAG.getNode(ISD::TRUNCATE, DL, WideVT, BitShift);

// Get the complementing shift amount, for rotating a field in the top
// bits back to its proper position.
SDValue NegBitShift = DAG.getNode(ISD::SUB, DL, WideVT,
                                  DAG.getConstant(0, DL, WideVT), BitShift);

// Extend the source operand to 32 bits and prepare it for the inner loop.
// ATOMIC_SWAPW uses RISBG to rotate the field left, but all other
// operations require the source to be shifted in advance.  (This shift
// can be folded if the source is constant.)  For AND and NAND, the lower
// bits must be set, while for other opcodes they should be left clear.
if (Opcode != SystemZISD::ATOMIC_SWAPW)
  Src2 = DAG.getNode(ISD::SHL, DL, WideVT, Src2,
                     DAG.getConstant(32 - BitSize, DL, WideVT));
if (Opcode == SystemZISD::ATOMIC_LOADW_AND ||
    Opcode == SystemZISD::ATOMIC_LOADW_NAND)
  Src2 = DAG.getNode(ISD::OR, DL, WideVT, Src2,
                     DAG.getConstant(uint32_t(-1) >> BitSize, DL, WideVT));

// Construct the ATOMIC_LOADW_* node.
SDVTList VTList = DAG.getVTList(WideVT, MVT::Other);
SDValue Ops[] = { ChainIn, AlignedAddr, Src2, BitShift, NegBitShift,
                  DAG.getConstant(BitSize, DL, WideVT) };
SDValue AtomicOp = DAG.getMemIntrinsicNode(Opcode, DL, VTList, Ops,
                                           NarrowVT, MMO);

// Rotate the result of the final CS so that the field is in the lower
// bits of a GR32, then truncate it.
SDValue ResultShift = DAG.getNode(ISD::ADD, DL, WideVT, BitShift,
                                  DAG.getConstant(BitSize, DL, WideVT));
SDValue Result = DAG.getNode(ISD::ROTL, DL, WideVT, AtomicOp, ResultShift);

SDValue RetOps[2] = { Result, AtomicOp.getValue(1) };
return DAG.getMergeValues(RetOps, DL);
4012}

4014// Op is an ATOMIC_LOAD_SUB operation.  Lower 8- and 16-bit operations
4015// into ATOMIC_LOADW_SUBs and decide whether to convert 32- and 64-bit
4016// operations into additions.
4017SDValue SystemZTargetLowering::lowerATOMIC_LOAD_SUB(SDValue Op,
                                                  SelectionDAG &DAG) const {
auto *Node = cast<AtomicSDNode>(Op.getNode());
EVT MemVT = Node->getMemoryVT();
if (MemVT == MVT::i32 || MemVT == MVT::i64) {
  // A full-width operation.
  assert(Op.getValueType() == MemVT && "Mismatched VTs")(static_cast <bool> (Op.getValueType() == MemVT &&
 "Mismatched VTs") ? void (0) : __assert_fail ("Op.getValueType() == MemVT && \"Mismatched VTs\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp"
, 4023, __extension__ __PRETTY_FUNCTION__));
  SDValue Src2 = Node->getVal();
  SDValue NegSrc2;
  SDLoc DL(Src2);

  if (auto *Op2 = dyn_cast<ConstantSDNode>(Src2)) {
    // Use an addition if the operand is constant and either LAA(G) is
    // available or the negative value is in the range of A(G)FHI.
    int64_t Value = (-Op2->getAPIntValue()).getSExtValue();
    if (isInt<32>(Value) || Subtarget.hasInterlockedAccess1())
      NegSrc2 = DAG.getConstant(Value, DL, MemVT);
  } else if (Subtarget.hasInterlockedAccess1())
    // Use LAA(G) if available.
    NegSrc2 = DAG.getNode(ISD::SUB, DL, MemVT, DAG.getConstant(0, DL, MemVT),
                          Src2);

  if (NegSrc2.getNode())
    return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, DL, MemVT,
                         Node->getChain(), Node->getBasePtr(), NegSrc2,
                         Node->getMemOperand());

  // Use the node as-is.
  return Op;
}

return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_LOADW_SUB);
4049}

4051// Lower 8/16/32/64-bit ATOMIC_CMP_SWAP_WITH_SUCCESS node.
4052SDValue SystemZTargetLowering::lowerATOMIC_CMP_SWAP(SDValue Op,
                                                  SelectionDAG &DAG) const {
auto *Node = cast<AtomicSDNode>(Op.getNode());
SDValue ChainIn = Node->getOperand(0);
SDValue Addr = Node->getOperand(1);
SDValue CmpVal = Node->getOperand(2);
SDValue SwapVal = Node->getOperand(3);
MachineMemOperand *MMO = Node->getMemOperand();
SDLoc DL(Node);

// We have native support for 32-bit and 64-bit compare and swap, but we
// still need to expand extracting the "success" result from the CC.
EVT NarrowVT = Node->getMemoryVT();
EVT WideVT = NarrowVT == MVT::i64 ? MVT::i64 : MVT::i32;
if (NarrowVT == WideVT) {
  SDVTList Tys = DAG.getVTList(WideVT, MVT::i32, MVT::Other);
  SDValue Ops[] = { ChainIn, Addr, CmpVal, SwapVal };
  SDValue AtomicOp = DAG.getMemIntrinsicNode(SystemZISD::ATOMIC_CMP_SWAP,
                                             DL, Tys, Ops, NarrowVT, MMO);
  SDValue Success = emitSETCC(DAG, DL, AtomicOp.getValue(1),
                              SystemZ::CCMASK_CS, SystemZ::CCMASK_CS_EQ);

  DAG.ReplaceAllUsesOfValueWith(Op.getValue(0), AtomicOp.getValue(0));
  DAG.ReplaceAllUsesOfValueWith(Op.getValue(1), Success);
  DAG.ReplaceAllUsesOfValueWith(Op.getValue(2), AtomicOp.getValue(2));
  return SDValue();
}

// Convert 8-bit and 16-bit compare and swap to a loop, implemented
// via a fullword ATOMIC_CMP_SWAPW operation.
int64_t BitSize = NarrowVT.getSizeInBits();
EVT PtrVT = Addr.getValueType();

// Get the address of the containing word.
SDValue AlignedAddr = DAG.getNode(ISD::AND, DL, PtrVT, Addr,
                                  DAG.getConstant(-4, DL, PtrVT));

// Get the number of bits that the word must be rotated left in order
// to bring the field to the top bits of a GR32.
SDValue BitShift = DAG.getNode(ISD::SHL, DL, PtrVT, Addr,
                               DAG.getConstant(3, DL, PtrVT));
BitShift = DAG.getNode(ISD::TRUNCATE, DL, WideVT, BitShift);

// Get the complementing shift amount, for rotating a field in the top
// bits back to its proper position.
SDValue NegBitShift = DAG.getNode(ISD::SUB, DL, WideVT,
                                  DAG.getConstant(0, DL, WideVT), BitShift);

// Construct the ATOMIC_CMP_SWAPW node.
SDVTList VTList = DAG.getVTList(WideVT, MVT::i32, MVT::Other);
SDValue Ops[] = { ChainIn, AlignedAddr, CmpVal, SwapVal, BitShift,
                  NegBitShift, DAG.getConstant(BitSize, DL, WideVT) };
SDValue AtomicOp = DAG.getMemIntrinsicNode(SystemZISD::ATOMIC_CMP_SWAPW, DL,
                                           VTList, Ops, NarrowVT, MMO);
SDValue Success = emitSETCC(DAG, DL, AtomicOp.getValue(1),
                            SystemZ::CCMASK_ICMP, SystemZ::CCMASK_CMP_EQ);

// emitAtomicCmpSwapW() will zero extend the result (original value).
SDValue OrigVal = DAG.getNode(ISD::AssertZext, DL, WideVT, AtomicOp.getValue(0),
                              DAG.getValueType(NarrowVT));
DAG.ReplaceAllUsesOfValueWith(Op.getValue(0), OrigVal);
DAG.ReplaceAllUsesOfValueWith(Op.getValue(1), Success);
DAG.ReplaceAllUsesOfValueWith(Op.getValue(2), AtomicOp.getValue(2));
return SDValue();
4116}

4118MachineMemOperand::Flags
4119SystemZTargetLowering::getTargetMMOFlags(const Instruction &I) const {
// Because of how we convert atomic_load and atomic_store to normal loads and
// stores in the DAG, we need to ensure that the MMOs are marked volatile
// since DAGCombine hasn't been updated to account for atomic, but non
// volatile loads.  (See D57601)
if (auto *SI = dyn_cast<StoreInst>(&I))
  if (SI->isAtomic())
    return MachineMemOperand::MOVolatile;
if (auto *LI = dyn_cast<LoadInst>(&I))
  if (LI->isAtomic())
    return MachineMemOperand::MOVolatile;
if (auto *AI = dyn_cast<AtomicRMWInst>(&I))
  if (AI->isAtomic())
    return MachineMemOperand::MOVolatile;
if (auto *AI = dyn_cast<AtomicCmpXchgInst>(&I))
  if (AI->isAtomic())
    return MachineMemOperand::MOVolatile;
return MachineMemOperand::MONone;
4137}

4139SDValue SystemZTargetLowering::lowerSTACKSAVE(SDValue Op,
                                            SelectionDAG &DAG) const {
MachineFunction &MF = DAG.getMachineFunction();
MF.getInfo<SystemZMachineFunctionInfo>()->setManipulatesSP(true);
if (MF.getFunction().getCallingConv() == CallingConv::GHC)
  report_fatal_error("Variable-sized stack allocations are not supported "
                     "in GHC calling convention");
return DAG.getCopyFromReg(Op.getOperand(0), SDLoc(Op),
                          SystemZ::R15D, Op.getValueType());
4148}

4150SDValue SystemZTargetLowering::lowerSTACKRESTORE(SDValue Op,
                                               SelectionDAG &DAG) const {
MachineFunction &MF = DAG.getMachineFunction();
MF.getInfo<SystemZMachineFunctionInfo>()->setManipulatesSP(true);
bool StoreBackchain = MF.getFunction().hasFnAttribute("backchain");

if (MF.getFunction().getCallingConv() == CallingConv::GHC)
  report_fatal_error("Variable-sized stack allocations are not supported "
                     "in GHC calling convention");

SDValue Chain = Op.getOperand(0);
SDValue NewSP = Op.getOperand(1);
SDValue Backchain;
SDLoc DL(Op);

if (StoreBackchain) {
  SDValue OldSP = DAG.getCopyFromReg(Chain, DL, SystemZ::R15D, MVT::i64);
  Backchain = DAG.getLoad(MVT::i64, DL, Chain, getBackchainAddress(OldSP, DAG),
                          MachinePointerInfo());
}

Chain = DAG.getCopyToReg(Chain, DL, SystemZ::R15D, NewSP);

if (StoreBackchain)
  Chain = DAG.getStore(Chain, DL, Backchain, getBackchainAddress(NewSP, DAG),
                       MachinePointerInfo());

return Chain;
4178}

4180SDValue SystemZTargetLowering::lowerPREFETCH(SDValue Op,
                                           SelectionDAG &DAG) const {
bool IsData = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue();
if (!IsData)
  // Just preserve the chain.
  return Op.getOperand(0);

SDLoc DL(Op);
bool IsWrite = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
unsigned Code = IsWrite ? SystemZ::PFD_WRITE : SystemZ::PFD_READ;
auto *Node = cast<MemIntrinsicSDNode>(Op.getNode());
SDValue Ops[] = {Op.getOperand(0), DAG.getTargetConstant(Code, DL, MVT::i32),
                 Op.getOperand(1)};
return DAG.getMemIntrinsicNode(SystemZISD::PREFETCH, DL,
                               Node->getVTList(), Ops,
                               Node->getMemoryVT(), Node->getMemOperand());
4196}

4198// Convert condition code in CCReg to an i32 value.
4199static SDValue getCCResult(SelectionDAG &DAG, SDValue CCReg) {
SDLoc DL(CCReg);
SDValue IPM = DAG.getNode(SystemZISD::IPM, DL, MVT::i32, CCReg);
return DAG.getNode(ISD::SRL, DL, MVT::i32, IPM,
                   DAG.getConstant(SystemZ::IPM_CC, DL, MVT::i32));
4204}

4206SDValue
4207SystemZTargetLowering::lowerINTRINSIC_W_CHAIN(SDValue Op,
                                            SelectionDAG &DAG) const {
unsigned Opcode, CCValid;
if (isIntrinsicWithCCAndChain(Op, Opcode, CCValid)) {
  assert(Op->getNumValues() == 2 && "Expected only CC result and chain")(static_cast <bool> (Op->getNumValues() == 2 &&
 "Expected only CC result and chain") ? void (0) : __assert_fail
 ("Op->getNumValues() == 2 && \"Expected only CC result and chain\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp"
, 4211, __extension__ __PRETTY_FUNCTION__));
  SDNode *Node = emitIntrinsicWithCCAndChain(DAG, Op, Opcode);
  SDValue CC = getCCResult(DAG, SDValue(Node, 0));
  DAG.ReplaceAllUsesOfValueWith(SDValue(Op.getNode(), 0), CC);
  return SDValue();
}

return SDValue();
4219}

4221SDValue
4222SystemZTargetLowering::lowerINTRINSIC_WO_CHAIN(SDValue Op,
                                             SelectionDAG &DAG) const {
unsigned Opcode, CCValid;
if (isIntrinsicWithCC(Op, Opcode, CCValid)) {
  SDNode *Node = emitIntrinsicWithCC(DAG, Op, Opcode);
  if (Op->getNumValues() == 1)
    return getCCResult(DAG, SDValue(Node, 0));
  assert(Op->getNumValues() == 2 && "Expected a CC and non-CC result")(static_cast <bool> (Op->getNumValues() == 2 &&
 "Expected a CC and non-CC result") ? void (0) : __assert_fail
 ("Op->getNumValues() == 2 && \"Expected a CC and non-CC result\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp"
, 4229, __extension__ __PRETTY_FUNCTION__));
  return DAG.getNode(ISD::MERGE_VALUES, SDLoc(Op), Op->getVTList(),
                     SDValue(Node, 0), getCCResult(DAG, SDValue(Node, 1)));
}

unsigned Id = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
switch (Id) {
case Intrinsic::thread_pointer:
  return lowerThreadPointer(SDLoc(Op), DAG);

case Intrinsic::s390_vpdi:
  return DAG.getNode(SystemZISD::PERMUTE_DWORDS, SDLoc(Op), Op.getValueType(),
                     Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));

case Intrinsic::s390_vperm:
  return DAG.getNode(SystemZISD::PERMUTE, SDLoc(Op), Op.getValueType(),
                     Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));

case Intrinsic::s390_vuphb:
case Intrinsic::s390_vuphh:
case Intrinsic::s390_vuphf:
  return DAG.getNode(SystemZISD::UNPACK_HIGH, SDLoc(Op), Op.getValueType(),
                     Op.getOperand(1));

case Intrinsic::s390_vuplhb:
case Intrinsic::s390_vuplhh:
case Intrinsic::s390_vuplhf:
  return DAG.getNode(SystemZISD::UNPACKL_HIGH, SDLoc(Op), Op.getValueType(),
                     Op.getOperand(1));

case Intrinsic::s390_vuplb:
case Intrinsic::s390_vuplhw:
case Intrinsic::s390_vuplf:
  return DAG.getNode(SystemZISD::UNPACK_LOW, SDLoc(Op), Op.getValueType(),
                     Op.getOperand(1));

case Intrinsic::s390_vupllb:
case Intrinsic::s390_vupllh:
case Intrinsic::s390_vupllf:
  return DAG.getNode(SystemZISD::UNPACKL_LOW, SDLoc(Op), Op.getValueType(),
                     Op.getOperand(1));

case Intrinsic::s390_vsumb:
case Intrinsic::s390_vsumh:
case Intrinsic::s390_vsumgh:
case Intrinsic::s390_vsumgf:
case Intrinsic::s390_vsumqf:
case Intrinsic::s390_vsumqg:
  return DAG.getNode(SystemZISD::VSUM, SDLoc(Op), Op.getValueType(),
                     Op.getOperand(1), Op.getOperand(2));
}

return SDValue();
4282}

4284namespace {
4285// Says that SystemZISD operation Opcode can be used to perform the equivalent
4286// of a VPERM with permute vector Bytes.  If Opcode takes three operands,
4287// Operand is the constant third operand, otherwise it is the number of
4288// bytes in each element of the result.
4289struct Permute {
unsigned Opcode;
unsigned Operand;
unsigned char Bytes[SystemZ::VectorBytes];
4293};
4294}

4296static const Permute PermuteForms[] = {
// VMRHG
{ SystemZISD::MERGE_HIGH, 8,
  { 0, 1, 2, 3, 4, 5, 6, 7, 16, 17, 18, 19, 20, 21, 22, 23 } },
// VMRHF
{ SystemZISD::MERGE_HIGH, 4,
  { 0, 1, 2, 3, 16, 17, 18, 19, 4, 5, 6, 7, 20, 21, 22, 23 } },
// VMRHH
{ SystemZISD::MERGE_HIGH, 2,
  { 0, 1, 16, 17, 2, 3, 18, 19, 4, 5, 20, 21, 6, 7, 22, 23 } },
// VMRHB
{ SystemZISD::MERGE_HIGH, 1,
  { 0, 16, 1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23 } },
// VMRLG
{ SystemZISD::MERGE_LOW, 8,
  { 8, 9, 10, 11, 12, 13, 14, 15, 24, 25, 26, 27, 28, 29, 30, 31 } },
// VMRLF
{ SystemZISD::MERGE_LOW, 4,
  { 8, 9, 10, 11, 24, 25, 26, 27, 12, 13, 14, 15, 28, 29, 30, 31 } },
// VMRLH
{ SystemZISD::MERGE_LOW, 2,
  { 8, 9, 24, 25, 10, 11, 26, 27, 12, 13, 28, 29, 14, 15, 30, 31 } },
// VMRLB
{ SystemZISD::MERGE_LOW, 1,
  { 8, 24, 9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31 } },
// VPKG
{ SystemZISD::PACK, 4,
  { 4, 5, 6, 7, 12, 13, 14, 15, 20, 21, 22, 23, 28, 29, 30, 31 } },
// VPKF
{ SystemZISD::PACK, 2,
  { 2, 3, 6, 7, 10, 11, 14, 15, 18, 19, 22, 23, 26, 27, 30, 31 } },
// VPKH
{ SystemZISD::PACK, 1,
  { 1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31 } },
// VPDI V1, V2, 4  (low half of V1, high half of V2)
{ SystemZISD::PERMUTE_DWORDS, 4,
  { 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23 } },
// VPDI V1, V2, 1  (high half of V1, low half of V2)
{ SystemZISD::PERMUTE_DWORDS, 1,
  { 0, 1, 2, 3, 4, 5, 6, 7, 24, 25, 26, 27, 28, 29, 30, 31 } }
4336};

4338// Called after matching a vector shuffle against a particular pattern.
4339// Both the original shuffle and the pattern have two vector operands.
4340// OpNos[0] is the operand of the original shuffle that should be used for
4341// operand 0 of the pattern, or -1 if operand 0 of the pattern can be anything.
4342// OpNos[1] is the same for operand 1 of the pattern.  Resolve these -1s and
4343// set OpNo0 and OpNo1 to the shuffle operands that should actually be used
4344// for operands 0 and 1 of the pattern.
4345static bool chooseShuffleOpNos(int *OpNos, unsigned &OpNo0, unsigned &OpNo1) {
if (OpNos[0] < 0) {
  if (OpNos[1] < 0)
    return false;
  OpNo0 = OpNo1 = OpNos[1];
} else if (OpNos[1] < 0) {
  OpNo0 = OpNo1 = OpNos[0];
} else {
  OpNo0 = OpNos[0];
  OpNo1 = OpNos[1];
}
return true;
4357}

4359// Bytes is a VPERM-like permute vector, except that -1 is used for
4360// undefined bytes.  Return true if the VPERM can be implemented using P.
4361// When returning true set OpNo0 to the VPERM operand that should be
4362// used for operand 0 of P and likewise OpNo1 for operand 1 of P.
4363//
4364// For example, if swapping the VPERM operands allows P to match, OpNo0
4365// will be 1 and OpNo1 will be 0.  If instead Bytes only refers to one
4366// operand, but rewriting it to use two duplicated operands allows it to
4367// match P, then OpNo0 and OpNo1 will be the same.
4368static bool matchPermute(const SmallVectorImpl<int> &Bytes, const Permute &P,
                       unsigned &OpNo0, unsigned &OpNo1) {
int OpNos[] = { -1, -1 };
for (unsigned I = 0; I < SystemZ::VectorBytes; ++I) {
  int Elt = Bytes[I];
  if (Elt >= 0) {
    // Make sure that the two permute vectors use the same suboperand
    // byte number.  Only the operand numbers (the high bits) are
    // allowed to differ.
    if ((Elt ^ P.Bytes[I]) & (SystemZ::VectorBytes - 1))
      return false;
    int ModelOpNo = P.Bytes[I] / SystemZ::VectorBytes;
    int RealOpNo = unsigned(Elt) / SystemZ::VectorBytes;
    // Make sure that the operand mappings are consistent with previous
    // elements.
    if (OpNos[ModelOpNo] == 1 - RealOpNo)
      return false;
    OpNos[ModelOpNo] = RealOpNo;
  }
}
return chooseShuffleOpNos(OpNos, OpNo0, OpNo1);
4389}

4391// As above, but search for a matching permute.
4392static const Permute *matchPermute(const SmallVectorImpl<int> &Bytes,
                                 unsigned &OpNo0, unsigned &OpNo1) {
for (auto &P : PermuteForms)
  if (matchPermute(Bytes, P, OpNo0, OpNo1))
    return &P;
return nullptr;
4398}

4400// Bytes is a VPERM-like permute vector, except that -1 is used for
4401// undefined bytes.  This permute is an operand of an outer permute.
4402// See whether redistributing the -1 bytes gives a shuffle that can be
4403// implemented using P.  If so, set Transform to a VPERM-like permute vector
4404// that, when applied to the result of P, gives the original permute in Bytes.
4405static bool matchDoublePermute(const SmallVectorImpl<int> &Bytes,
                             const Permute &P,
                             SmallVectorImpl<int> &Transform) {
unsigned To = 0;
for (unsigned From = 0; From < SystemZ::VectorBytes; ++From) {
  int Elt = Bytes[From];
  if (Elt < 0)
    // Byte number From of the result is undefined.
    Transform[From] = -1;
  else {
    while (P.Bytes[To] != Elt) {
      To += 1;
      if (To == SystemZ::VectorBytes)
        return false;
    }
    Transform[From] = To;
  }
}
return true;
4424}

4426// As above, but search for a matching permute.
4427static const Permute *matchDoublePermute(const SmallVectorImpl<int> &Bytes,
                                       SmallVectorImpl<int> &Transform) {
for (auto &P : PermuteForms)
  if (matchDoublePermute(Bytes, P, Transform))
    return &P;
return nullptr;
4433}

4435// Convert the mask of the given shuffle op into a byte-level mask,
4436// as if it had type vNi8.
4437static bool getVPermMask(SDValue ShuffleOp,
                       SmallVectorImpl<int> &Bytes) {
EVT VT = ShuffleOp.getValueType();
unsigned NumElements = VT.getVectorNumElements();
unsigned BytesPerElement = VT.getVectorElementType().getStoreSize();

if (auto *VSN = dyn_cast<ShuffleVectorSDNode>(ShuffleOp)) {
  Bytes.resize(NumElements * BytesPerElement, -1);
  for (unsigned I = 0; I < NumElements; ++I) {
    int Index = VSN->getMaskElt(I);
    if (Index >= 0)
      for (unsigned J = 0; J < BytesPerElement; ++J)
        Bytes[I * BytesPerElement + J] = Index * BytesPerElement + J;
  }
  return true;
}
if (SystemZISD::SPLAT == ShuffleOp.getOpcode() &&
    isa<ConstantSDNode>(ShuffleOp.getOperand(1))) {
  unsigned Index = ShuffleOp.getConstantOperandVal(1);
  Bytes.resize(NumElements * BytesPerElement, -1);
  for (unsigned I = 0; I < NumElements; ++I)
    for (unsigned J = 0; J < BytesPerElement; ++J)
      Bytes[I * BytesPerElement + J] = Index * BytesPerElement + J;
  return true;
}
return false;
4463}

4465// Bytes is a VPERM-like permute vector, except that -1 is used for
4466// undefined bytes.  See whether bytes [Start, Start + BytesPerElement) of
4467// the result come from a contiguous sequence of bytes from one input.
4468// Set Base to the selector for the first byte if so.
4469static bool getShuffleInput(const SmallVectorImpl<int> &Bytes, unsigned Start,
                          unsigned BytesPerElement, int &Base) {
Base = -1;
for (unsigned I = 0; I < BytesPerElement; ++I) {
  if (Bytes[Start + I] >= 0) {
    unsigned Elem = Bytes[Start + I];
    if (Base < 0) {
      Base = Elem - I;
      // Make sure the bytes would come from one input operand.
      if (unsigned(Base) % Bytes.size() + BytesPerElement > Bytes.size())
        return false;
    } else if (unsigned(Base) != Elem - I)
      return false;
  }
}
return true;
4485}

4487// Bytes is a VPERM-like permute vector, except that -1 is used for
4488// undefined bytes.  Return true if it can be performed using VSLDB.
4489// When returning true, set StartIndex to the shift amount and OpNo0
4490// and OpNo1 to the VPERM operands that should be used as the first
4491// and second shift operand respectively.
4492static bool isShlDoublePermute(const SmallVectorImpl<int> &Bytes,
                             unsigned &StartIndex, unsigned &OpNo0,
                             unsigned &OpNo1) {
int OpNos[] = { -1, -1 };
int Shift = -1;
for (unsigned I = 0; I < 16; ++I) {
  int Index = Bytes[I];
  if (Index >= 0) {
    int ExpectedShift = (Index - I) % SystemZ::VectorBytes;
    int ModelOpNo = unsigned(ExpectedShift + I) / SystemZ::VectorBytes;
    int RealOpNo = unsigned(Index) / SystemZ::VectorBytes;
    if (Shift < 0)
      Shift = ExpectedShift;
    else if (Shift != ExpectedShift)
      return false;
    // Make sure that the operand mappings are consistent with previous
    // elements.
    if (OpNos[ModelOpNo] == 1 - RealOpNo)
      return false;
    OpNos[ModelOpNo] = RealOpNo;
  }
}
StartIndex = Shift;
return chooseShuffleOpNos(OpNos, OpNo0, OpNo1);
4516}

4518// Create a node that performs P on operands Op0 and Op1, casting the
4519// operands to the appropriate type.  The type of the result is determined by P.
4520static SDValue getPermuteNode(SelectionDAG &DAG, const SDLoc &DL,
                            const Permute &P, SDValue Op0, SDValue Op1) {
// VPDI (PERMUTE_DWORDS) always operates on v2i64s.  The input
// elements of a PACK are twice as wide as the outputs.
unsigned InBytes = (P.Opcode == SystemZISD::PERMUTE_DWORDS ? 8 :
                    P.Opcode == SystemZISD::PACK ? P.Operand * 2 :
                    P.Operand);
// Cast both operands to the appropriate type.
MVT InVT = MVT::getVectorVT(MVT::getIntegerVT(InBytes * 8),
                            SystemZ::VectorBytes / InBytes);
Op0 = DAG.getNode(ISD::BITCAST, DL, InVT, Op0);
Op1 = DAG.getNode(ISD::BITCAST, DL, InVT, Op1);
SDValue Op;
if (P.Opcode == SystemZISD::PERMUTE_DWORDS) {
  SDValue Op2 = DAG.getTargetConstant(P.Operand, DL, MVT::i32);
  Op = DAG.getNode(SystemZISD::PERMUTE_DWORDS, DL, InVT, Op0, Op1, Op2);
} else if (P.Opcode == SystemZISD::PACK) {
  MVT OutVT = MVT::getVectorVT(MVT::getIntegerVT(P.Operand * 8),
                               SystemZ::VectorBytes / P.Operand);
  Op = DAG.getNode(SystemZISD::PACK, DL, OutVT, Op0, Op1);
} else {
  Op = DAG.getNode(P.Opcode, DL, InVT, Op0, Op1);
}
return Op;
4544}

4546static bool isZeroVector(SDValue N) {
if (N->getOpcode() == ISD::BITCAST)
  N = N->getOperand(0);
if (N->getOpcode() == ISD::SPLAT_VECTOR)
  if (auto *Op = dyn_cast<ConstantSDNode>(N->getOperand(0)))
    return Op->getZExtValue() == 0;
return ISD::isBuildVectorAllZeros(N.getNode());
4553}

4555// Return the index of the zero/undef vector, or UINT32_MAX if not found.
4556static uint32_t findZeroVectorIdx(SDValue *Ops, unsigned Num) {
for (unsigned I = 0; I < Num ; I++)
  if (isZeroVector(Ops[I]))
    return I;
return UINT32_MAX(4294967295U);
4561}

4563// Bytes is a VPERM-like permute vector, except that -1 is used for
4564// undefined bytes.  Implement it on operands Ops[0] and Ops[1] using
4565// VSLDB or VPERM.
4566static SDValue getGeneralPermuteNode(SelectionDAG &DAG, const SDLoc &DL,
                                   SDValue *Ops,
                                   const SmallVectorImpl<int> &Bytes) {
for (unsigned I = 0; I < 2; ++I)
  Ops[I] = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Ops[I]);

// First see whether VSLDB can be used.
unsigned StartIndex, OpNo0, OpNo1;
if (isShlDoublePermute(Bytes, StartIndex, OpNo0, OpNo1))
  return DAG.getNode(SystemZISD::SHL_DOUBLE, DL, MVT::v16i8, Ops[OpNo0],
                     Ops[OpNo1],
                     DAG.getTargetConstant(StartIndex, DL, MVT::i32));

// Fall back on VPERM.  Construct an SDNode for the permute vector.  Try to
// eliminate a zero vector by reusing any zero index in the permute vector.
unsigned ZeroVecIdx = findZeroVectorIdx(&Ops[0], 2);
if (ZeroVecIdx != UINT32_MAX(4294967295U)) {
  bool MaskFirst = true;
  int ZeroIdx = -1;
  for (unsigned I = 0; I < SystemZ::VectorBytes; ++I) {
    unsigned OpNo = unsigned(Bytes[I]) / SystemZ::VectorBytes;
    unsigned Byte = unsigned(Bytes[I]) % SystemZ::VectorBytes;
    if (OpNo == ZeroVecIdx && I == 0) {
      // If the first byte is zero, use mask as first operand.
      ZeroIdx = 0;
      break;
    }
    if (OpNo != ZeroVecIdx && Byte == 0) {
      // If mask contains a zero, use it by placing that vector first.
      ZeroIdx = I + SystemZ::VectorBytes;
      MaskFirst = false;
      break;
    }
  }
  if (ZeroIdx != -1) {
    SDValue IndexNodes[SystemZ::VectorBytes];
    for (unsigned I = 0; I < SystemZ::VectorBytes; ++I) {
      if (Bytes[I] >= 0) {
        unsigned OpNo = unsigned(Bytes[I]) / SystemZ::VectorBytes;
        unsigned Byte = unsigned(Bytes[I]) % SystemZ::VectorBytes;
        if (OpNo == ZeroVecIdx)
          IndexNodes[I] = DAG.getConstant(ZeroIdx, DL, MVT::i32);
        else {
          unsigned BIdx = MaskFirst ? Byte + SystemZ::VectorBytes : Byte;
          IndexNodes[I] = DAG.getConstant(BIdx, DL, MVT::i32);
        }
      } else
        IndexNodes[I] = DAG.getUNDEF(MVT::i32);
    }
    SDValue Mask = DAG.getBuildVector(MVT::v16i8, DL, IndexNodes);
    SDValue Src = ZeroVecIdx == 0 ? Ops[1] : Ops[0];
    if (MaskFirst)
      return DAG.getNode(SystemZISD::PERMUTE, DL, MVT::v16i8, Mask, Src,
                         Mask);
    else
      return DAG.getNode(SystemZISD::PERMUTE, DL, MVT::v16i8, Src, Mask,
                         Mask);
  }
}

SDValue IndexNodes[SystemZ::VectorBytes];
for (unsigned I = 0; I < SystemZ::VectorBytes; ++I)
  if (Bytes[I] >= 0)
    IndexNodes[I] = DAG.getConstant(Bytes[I], DL, MVT::i32);
  else
    IndexNodes[I] = DAG.getUNDEF(MVT::i32);
SDValue Op2 = DAG.getBuildVector(MVT::v16i8, DL, IndexNodes);
return DAG.getNode(SystemZISD::PERMUTE, DL, MVT::v16i8, Ops[0],
                   (!Ops[1].isUndef() ? Ops[1] : Ops[0]), Op2);
4635}

4637namespace {
4638// Describes a general N-operand vector shuffle.
4639struct GeneralShuffle {
GeneralShuffle(EVT vt) : VT(vt), UnpackFromEltSize(UINT_MAX(2147483647 *2U +1U)) {}
void addUndef();
bool add(SDValue, unsigned);
SDValue getNode(SelectionDAG &, const SDLoc &);
void tryPrepareForUnpack();
bool unpackWasPrepared() { return UnpackFromEltSize <= 4; }
SDValue insertUnpackIfPrepared(SelectionDAG &DAG, const SDLoc &DL, SDValue Op);

// The operands of the shuffle.
SmallVector<SDValue, SystemZ::VectorBytes> Ops;

// Index I is -1 if byte I of the result is undefined.  Otherwise the
// result comes from byte Bytes[I] % SystemZ::VectorBytes of operand
// Bytes[I] / SystemZ::VectorBytes.
SmallVector<int, SystemZ::VectorBytes> Bytes;

// The type of the shuffle result.
EVT VT;

// Holds a value of 1, 2 or 4 if a final unpack has been prepared for.
unsigned UnpackFromEltSize;
4661};
4662}

4664// Add an extra undefined element to the shuffle.
4665void GeneralShuffle::addUndef() {
unsigned BytesPerElement = VT.getVectorElementType().getStoreSize();
for (unsigned I = 0; I < BytesPerElement; ++I)
  Bytes.push_back(-1);
4669}

4671// Add an extra element to the shuffle, taking it from element Elem of Op.
4672// A null Op indicates a vector input whose value will be calculated later;
4673// there is at most one such input per shuffle and it always has the same
4674// type as the result. Aborts and returns false if the source vector elements
4675// of an EXTRACT_VECTOR_ELT are smaller than the destination elements. Per
4676// LLVM they become implicitly extended, but this is rare and not optimized.
4677bool GeneralShuffle::add(SDValue Op, unsigned Elem) {
unsigned BytesPerElement = VT.getVectorElementType().getStoreSize();

// The source vector can have wider elements than the result,
// either through an explicit TRUNCATE or because of type legalization.
// We want the least significant part.
EVT FromVT = Op.getNode() ? Op.getValueType() : VT;
unsigned FromBytesPerElement = FromVT.getVectorElementType().getStoreSize();

// Return false if the source elements are smaller than their destination
// elements.
if (FromBytesPerElement < BytesPerElement)
  return false;

unsigned Byte = ((Elem * FromBytesPerElement) % SystemZ::VectorBytes +
                 (FromBytesPerElement - BytesPerElement));

// Look through things like shuffles and bitcasts.
while (Op.getNode()) {
  if (Op.getOpcode() == ISD::BITCAST)
    Op = Op.getOperand(0);
  else if (Op.getOpcode() == ISD::VECTOR_SHUFFLE && Op.hasOneUse()) {
    // See whether the bytes we need come from a contiguous part of one
    // operand.
    SmallVector<int, SystemZ::VectorBytes> OpBytes;
    if (!getVPermMask(Op, OpBytes))
      break;
    int NewByte;
    if (!getShuffleInput(OpBytes, Byte, BytesPerElement, NewByte))
      break;
    if (NewByte < 0) {
      addUndef();
      return true;
    }
    Op = Op.getOperand(unsigned(NewByte) / SystemZ::VectorBytes);
    Byte = unsigned(NewByte) % SystemZ::VectorBytes;
  } else if (Op.isUndef()) {
    addUndef();
    return true;
  } else
    break;
}

// Make sure that the source of the extraction is in Ops.
unsigned OpNo = 0;
for (; OpNo < Ops.size(); ++OpNo)
  if (Ops[OpNo] == Op)
    break;
if (OpNo == Ops.size())
  Ops.push_back(Op);

// Add the element to Bytes.
unsigned Base = OpNo * SystemZ::VectorBytes + Byte;
for (unsigned I = 0; I < BytesPerElement; ++I)
  Bytes.push_back(Base + I);

return true;
4734}

4736// Return SDNodes for the completed shuffle.
4737SDValue GeneralShuffle::getNode(SelectionDAG &DAG, const SDLoc &DL) {
assert(Bytes.size() == SystemZ::VectorBytes && "Incomplete vector")(static_cast <bool> (Bytes.size() == SystemZ::VectorBytes
 && "Incomplete vector") ? void (0) : __assert_fail (
"Bytes.size() == SystemZ::VectorBytes && \"Incomplete vector\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp"
, 4738, __extension__ __PRETTY_FUNCTION__));

if (Ops.size() == 0)
  return DAG.getUNDEF(VT);

// Use a single unpack if possible as the last operation.
tryPrepareForUnpack();

// Make sure that there are at least two shuffle operands.
if (Ops.size() == 1)
  Ops.push_back(DAG.getUNDEF(MVT::v16i8));

// Create a tree of shuffles, deferring root node until after the loop.
// Try to redistribute the undefined elements of non-root nodes so that
// the non-root shuffles match something like a pack or merge, then adjust
// the parent node's permute vector to compensate for the new order.
// Among other things, this copes with vectors like <2 x i16> that were
// padded with undefined elements during type legalization.
//
// In the best case this redistribution will lead to the whole tree
// using packs and merges.  It should rarely be a loss in other cases.
unsigned Stride = 1;
for (; Stride * 2 < Ops.size(); Stride *= 2) {
  for (unsigned I = 0; I < Ops.size() - Stride; I += Stride * 2) {
    SDValue SubOps[] = { Ops[I], Ops[I + Stride] };

    // Create a mask for just these two operands.
    SmallVector<int, SystemZ::VectorBytes> NewBytes(SystemZ::VectorBytes);
    for (unsigned J = 0; J < SystemZ::VectorBytes; ++J) {
      unsigned OpNo = unsigned(Bytes[J]) / SystemZ::VectorBytes;
      unsigned Byte = unsigned(Bytes[J]) % SystemZ::VectorBytes;
      if (OpNo == I)
        NewBytes[J] = Byte;
      else if (OpNo == I + Stride)
        NewBytes[J] = SystemZ::VectorBytes + Byte;
      else
        NewBytes[J] = -1;
    }
    // See if it would be better to reorganize NewMask to avoid using VPERM.
    SmallVector<int, SystemZ::VectorBytes> NewBytesMap(SystemZ::VectorBytes);
    if (const Permute *P = matchDoublePermute(NewBytes, NewBytesMap)) {
      Ops[I] = getPermuteNode(DAG, DL, *P, SubOps[0], SubOps[1]);
      // Applying NewBytesMap to Ops[I] gets back to NewBytes.
      for (unsigned J = 0; J < SystemZ::VectorBytes; ++J) {
        if (NewBytes[J] >= 0) {
          assert(unsigned(NewBytesMap[J]) < SystemZ::VectorBytes &&(static_cast <bool> (unsigned(NewBytesMap[J]) < SystemZ
::VectorBytes && "Invalid double permute") ? void (0)
 : __assert_fail ("unsigned(NewBytesMap[J]) < SystemZ::VectorBytes && \"Invalid double permute\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp"
, 4784, __extension__ __PRETTY_FUNCTION__))
                 "Invalid double permute")(static_cast <bool> (unsigned(NewBytesMap[J]) < SystemZ
::VectorBytes && "Invalid double permute") ? void (0)
 : __assert_fail ("unsigned(NewBytesMap[J]) < SystemZ::VectorBytes && \"Invalid double permute\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp"
, 4784, __extension__ __PRETTY_FUNCTION__));
          Bytes[J] = I * SystemZ::VectorBytes + NewBytesMap[J];
        } else
          assert(NewBytesMap[J] < 0 && "Invalid double permute")(static_cast <bool> (NewBytesMap[J] < 0 && "Invalid double permute"
) ? void (0) : __assert_fail ("NewBytesMap[J] < 0 && \"Invalid double permute\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp"
, 4787, __extension__ __PRETTY_FUNCTION__));
      }
    } else {
      // Just use NewBytes on the operands.
      Ops[I] = getGeneralPermuteNode(DAG, DL, SubOps, NewBytes);
      for (unsigned J = 0; J < SystemZ::VectorBytes; ++J)
        if (NewBytes[J] >= 0)
          Bytes[J] = I * SystemZ::VectorBytes + J;
    }
  }
}

// Now we just have 2 inputs.  Put the second operand in Ops[1].
if (Stride > 1) {
  Ops[1] = Ops[Stride];
  for (unsigned I = 0; I < SystemZ::VectorBytes; ++I)
    if (Bytes[I] >= int(SystemZ::VectorBytes))
      Bytes[I] -= (Stride - 1) * SystemZ::VectorBytes;
}

// Look for an instruction that can do the permute without resorting
// to VPERM.
unsigned OpNo0, OpNo1;
SDValue Op;
if (unpackWasPrepared() && Ops[1].isUndef())
  Op = Ops[0];
else if (const Permute *P = matchPermute(Bytes, OpNo0, OpNo1))
  Op = getPermuteNode(DAG, DL, *P, Ops[OpNo0], Ops[OpNo1]);
else
  Op = getGeneralPermuteNode(DAG, DL, &Ops[0], Bytes);

Op = insertUnpackIfPrepared(DAG, DL, Op);

return DAG.getNode(ISD::BITCAST, DL, VT, Op);
4821}

4823#ifndef NDEBUG
4824static void dumpBytes(const SmallVectorImpl<int> &Bytes, std::string Msg) {
dbgs() << Msg.c_str() << " { ";
for (unsigned i = 0; i < Bytes.size(); i++)
  dbgs() << Bytes[i] << " ";
dbgs() << "}\n";
4829}
4830#endif

4832// If the Bytes vector matches an unpack operation, prepare to do the unpack
4833// after all else by removing the zero vector and the effect of the unpack on
4834// Bytes.
4835void GeneralShuffle::tryPrepareForUnpack() {
uint32_t ZeroVecOpNo = findZeroVectorIdx(&Ops[0], Ops.size());
if (ZeroVecOpNo == UINT32_MAX(4294967295U) || Ops.size() == 1)
  return;

// Only do this if removing the zero vector reduces the depth, otherwise
// the critical path will increase with the final unpack.
if (Ops.size() > 2 &&
    Log2_32_Ceil(Ops.size()) == Log2_32_Ceil(Ops.size() - 1))
  return;

// Find an unpack that would allow removing the zero vector from Ops.
UnpackFromEltSize = 1;
for (; UnpackFromEltSize <= 4; UnpackFromEltSize *= 2) {
  bool MatchUnpack = true;
  SmallVector<int, SystemZ::VectorBytes> SrcBytes;
  for (unsigned Elt = 0; Elt < SystemZ::VectorBytes; Elt++) {
    unsigned ToEltSize = UnpackFromEltSize * 2;
    bool IsZextByte = (Elt % ToEltSize) < UnpackFromEltSize;
    if (!IsZextByte)
      SrcBytes.push_back(Bytes[Elt]);
    if (Bytes[Elt] != -1) {
      unsigned OpNo = unsigned(Bytes[Elt]) / SystemZ::VectorBytes;
      if (IsZextByte != (OpNo == ZeroVecOpNo)) {
        MatchUnpack = false;
        break;
      }
    }
  }
  if (MatchUnpack) {
    if (Ops.size() == 2) {
      // Don't use unpack if a single source operand needs rearrangement.
      for (unsigned i = 0; i < SystemZ::VectorBytes / 2; i++)
        if (SrcBytes[i] != -1 && SrcBytes[i] % 16 != int(i)) {
          UnpackFromEltSize = UINT_MAX(2147483647 *2U +1U);
          return;
        }
    }
    break;
  }
}
if (UnpackFromEltSize > 4)
  return;

LLVM_DEBUG(dbgs() << "Preparing for final unpack of element size "do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("systemz-lower")) { dbgs() << "Preparing for final unpack of element size "
 << UnpackFromEltSize << ". Zero vector is Op#" <<
 ZeroVecOpNo << ".\n"; dumpBytes(Bytes, "Original Bytes vector:"
);; } } while (false)
           << UnpackFromEltSize << ". Zero vector is Op#" << ZeroVecOpNodo { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("systemz-lower")) { dbgs() << "Preparing for final unpack of element size "
 << UnpackFromEltSize << ". Zero vector is Op#" <<
 ZeroVecOpNo << ".\n"; dumpBytes(Bytes, "Original Bytes vector:"
);; } } while (false)
           << ".\n";do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("systemz-lower")) { dbgs() << "Preparing for final unpack of element size "
 << UnpackFromEltSize << ". Zero vector is Op#" <<
 ZeroVecOpNo << ".\n"; dumpBytes(Bytes, "Original Bytes vector:"
);; } } while (false)
           dumpBytes(Bytes, "Original Bytes vector:");)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("systemz-lower")) { dbgs() << "Preparing for final unpack of element size "
 << UnpackFromEltSize << ". Zero vector is Op#" <<
 ZeroVecOpNo << ".\n"; dumpBytes(Bytes, "Original Bytes vector:"
);; } } while (false);

// Apply the unpack in reverse to the Bytes array.
unsigned B = 0;
for (unsigned Elt = 0; Elt < SystemZ::VectorBytes;) {
  Elt += UnpackFromEltSize;
  for (unsigned i = 0; i < UnpackFromEltSize; i++, Elt++, B++)
    Bytes[B] = Bytes[Elt];
}
while (B < SystemZ::VectorBytes)
  Bytes[B++] = -1;

// Remove the zero vector from Ops
Ops.erase(&Ops[ZeroVecOpNo]);
for (unsigned I = 0; I < SystemZ::VectorBytes; ++I)
  if (Bytes[I] >= 0) {
    unsigned OpNo = unsigned(Bytes[I]) / SystemZ::VectorBytes;
    if (OpNo > ZeroVecOpNo)
      Bytes[I] -= SystemZ::VectorBytes;
  }

LLVM_DEBUG(dumpBytes(Bytes, "Resulting Bytes vector, zero vector removed:");do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("systemz-lower")) { dumpBytes(Bytes, "Resulting Bytes vector, zero vector removed:"
); dbgs() << "\n";; } } while (false)
           dbgs() << "\n";)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("systemz-lower")) { dumpBytes(Bytes, "Resulting Bytes vector, zero vector removed:"
); dbgs() << "\n";; } } while (false);
4905}

4907SDValue GeneralShuffle::insertUnpackIfPrepared(SelectionDAG &DAG,
                                             const SDLoc &DL,
                                             SDValue Op) {
if (!unpackWasPrepared())
  return Op;
unsigned InBits = UnpackFromEltSize * 8;
EVT InVT = MVT::getVectorVT(MVT::getIntegerVT(InBits),
                              SystemZ::VectorBits / InBits);
SDValue PackedOp = DAG.getNode(ISD::BITCAST, DL, InVT, Op);
unsigned OutBits = InBits * 2;
EVT OutVT = MVT::getVectorVT(MVT::getIntegerVT(OutBits),
                             SystemZ::VectorBits / OutBits);
return DAG.getNode(SystemZISD::UNPACKL_HIGH, DL, OutVT, PackedOp);
4920}

4922// Return true if the given BUILD_VECTOR is a scalar-to-vector conversion.
4923static bool isScalarToVector(SDValue Op) {
for (unsigned I = 1, E = Op.getNumOperands(); I != E; ++I)
  if (!Op.getOperand(I).isUndef())
    return false;
return true;
4928}

4930// Return a vector of type VT that contains Value in the first element.
4931// The other elements don't matter.
4932static SDValue buildScalarToVector(SelectionDAG &DAG, const SDLoc &DL, EVT VT,
                                 SDValue Value) {
// If we have a constant, replicate it to all elements and let the
// BUILD_VECTOR lowering take care of it.
if (Value.getOpcode() == ISD::Constant ||
    Value.getOpcode() == ISD::ConstantFP) {
  SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Value);
  return DAG.getBuildVector(VT, DL, Ops);
}
if (Value.isUndef())
  return DAG.getUNDEF(VT);
return DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VT, Value);
4944}

4946// Return a vector of type VT in which Op0 is in element 0 and Op1 is in
4947// element 1.  Used for cases in which replication is cheap.
4948static SDValue buildMergeScalars(SelectionDAG &DAG, const SDLoc &DL, EVT VT,
                               SDValue Op0, SDValue Op1) {
if (Op0.isUndef()) {
  if (Op1.isUndef())
    return DAG.getUNDEF(VT);
  return DAG.getNode(SystemZISD::REPLICATE, DL, VT, Op1);
}
if (Op1.isUndef())
  return DAG.getNode(SystemZISD::REPLICATE, DL, VT, Op0);
return DAG.getNode(SystemZISD::MERGE_HIGH, DL, VT,
                   buildScalarToVector(DAG, DL, VT, Op0),
                   buildScalarToVector(DAG, DL, VT, Op1));
4960}

4962// Extend GPR scalars Op0 and Op1 to doublewords and return a v2i64
4963// vector for them.
4964static SDValue joinDwords(SelectionDAG &DAG, const SDLoc &DL, SDValue Op0,
                        SDValue Op1) {
if (Op0.isUndef() && Op1.isUndef())
  return DAG.getUNDEF(MVT::v2i64);
// If one of the two inputs is undefined then replicate the other one,
// in order to avoid using another register unnecessarily.
if (Op0.isUndef())
  Op0 = Op1 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, Op1);
else if (Op1.isUndef())
  Op0 = Op1 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, Op0);
else {
  Op0 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, Op0);
  Op1 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, Op1);
}
return DAG.getNode(SystemZISD::JOIN_DWORDS, DL, MVT::v2i64, Op0, Op1);
4979}

4981// If a BUILD_VECTOR contains some EXTRACT_VECTOR_ELTs, it's usually
4982// better to use VECTOR_SHUFFLEs on them, only using BUILD_VECTOR for
4983// the non-EXTRACT_VECTOR_ELT elements.  See if the given BUILD_VECTOR
4984// would benefit from this representation and return it if so.
4985static SDValue tryBuildVectorShuffle(SelectionDAG &DAG,
                                   BuildVectorSDNode *BVN) {
EVT VT = BVN->getValueType(0);
unsigned NumElements = VT.getVectorNumElements();

// Represent the BUILD_VECTOR as an N-operand VECTOR_SHUFFLE-like operation
// on byte vectors.  If there are non-EXTRACT_VECTOR_ELT elements that still
// need a BUILD_VECTOR, add an additional placeholder operand for that
// BUILD_VECTOR and store its operands in ResidueOps.
GeneralShuffle GS(VT);
SmallVector<SDValue, SystemZ::VectorBytes> ResidueOps;
bool FoundOne = false;
for (unsigned I = 0; I < NumElements; ++I) {
  SDValue Op = BVN->getOperand(I);
  if (Op.getOpcode() == ISD::TRUNCATE)
    Op = Op.getOperand(0);
  if (Op.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
      Op.getOperand(1).getOpcode() == ISD::Constant) {
    unsigned Elem = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
    if (!GS.add(Op.getOperand(0), Elem))
      return SDValue();
    FoundOne = true;
  } else if (Op.isUndef()) {
    GS.addUndef();
  } else {
    if (!GS.add(SDValue(), ResidueOps.size()))
      return SDValue();
    ResidueOps.push_back(BVN->getOperand(I));
  }
}

// Nothing to do if there are no EXTRACT_VECTOR_ELTs.
if (!FoundOne)
  return SDValue();

// Create the BUILD_VECTOR for the remaining elements, if any.
if (!ResidueOps.empty()) {
  while (ResidueOps.size() < NumElements)
    ResidueOps.push_back(DAG.getUNDEF(ResidueOps[0].getValueType()));
  for (auto &Op : GS.Ops) {
    if (!Op.getNode()) {
      Op = DAG.getBuildVector(VT, SDLoc(BVN), ResidueOps);
      break;
    }
  }
}
return GS.getNode(DAG, SDLoc(BVN));
5032}

5034bool SystemZTargetLowering::isVectorElementLoad(SDValue Op) const {
if (Op.getOpcode() == ISD::LOAD && cast<LoadSDNode>(Op)->isUnindexed())
  return true;
if (Subtarget.hasVectorEnhancements2() && Op.getOpcode() == SystemZISD::LRV)
  return true;
return false;
5040}

5042// Combine GPR scalar values Elems into a vector of type VT.
5043SDValue
5044SystemZTargetLowering::buildVector(SelectionDAG &DAG, const SDLoc &DL, EVT VT,
                                 SmallVectorImpl<SDValue> &Elems) const {
// See whether there is a single replicated value.
SDValue Single;
unsigned int NumElements = Elems.size();
unsigned int Count = 0;
for (auto Elem : Elems) {
  if (!Elem.isUndef()) {
    if (!Single.getNode())
      Single = Elem;
    else if (Elem != Single) {
      Single = SDValue();
      break;
    }
    Count += 1;
  }
}
// There are three cases here:
//
// - if the only defined element is a loaded one, the best sequence
//   is a replicating load.
//
// - otherwise, if the only defined element is an i64 value, we will
//   end up with the same VLVGP sequence regardless of whether we short-cut
//   for replication or fall through to the later code.
//
// - otherwise, if the only defined element is an i32 or smaller value,
//   we would need 2 instructions to replicate it: VLVGP followed by VREPx.
//   This is only a win if the single defined element is used more than once.
//   In other cases we're better off using a single VLVGx.
if (Single.getNode() && (Count > 1 || isVectorElementLoad(Single)))
  return DAG.getNode(SystemZISD::REPLICATE, DL, VT, Single);

// If all elements are loads, use VLREP/VLEs (below).
bool AllLoads = true;
for (auto Elem : Elems)
  if (!isVectorElementLoad(Elem)) {
    AllLoads = false;
    break;
  }

// The best way of building a v2i64 from two i64s is to use VLVGP.
if (VT == MVT::v2i64 && !AllLoads)
  return joinDwords(DAG, DL, Elems[0], Elems[1]);

// Use a 64-bit merge high to combine two doubles.
if (VT == MVT::v2f64 && !AllLoads)
  return buildMergeScalars(DAG, DL, VT, Elems[0], Elems[1]);

// Build v4f32 values directly from the FPRs:
//
//   <Axxx> <Bxxx> <Cxxxx> <Dxxx>
//         V              V         VMRHF
//      <ABxx>         <CDxx>
//                V                 VMRHG
//              <ABCD>
if (VT == MVT::v4f32 && !AllLoads) {
  SDValue Op01 = buildMergeScalars(DAG, DL, VT, Elems[0], Elems[1]);
  SDValue Op23 = buildMergeScalars(DAG, DL, VT, Elems[2], Elems[3]);
  // Avoid unnecessary undefs by reusing the other operand.
  if (Op01.isUndef())
    Op01 = Op23;
  else if (Op23.isUndef())
    Op23 = Op01;
  // Merging identical replications is a no-op.
  if (Op01.getOpcode() == SystemZISD::REPLICATE && Op01 == Op23)
    return Op01;
  Op01 = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, Op01);
  Op23 = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, Op23);
  SDValue Op = DAG.getNode(SystemZISD::MERGE_HIGH,
                           DL, MVT::v2i64, Op01, Op23);
  return DAG.getNode(ISD::BITCAST, DL, VT, Op);
}

// Collect the constant terms.
SmallVector<SDValue, SystemZ::VectorBytes> Constants(NumElements, SDValue());
SmallVector<bool, SystemZ::VectorBytes> Done(NumElements, false);

unsigned NumConstants = 0;
for (unsigned I = 0; I < NumElements; ++I) {
  SDValue Elem = Elems[I];
  if (Elem.getOpcode() == ISD::Constant ||
      Elem.getOpcode() == ISD::ConstantFP) {
    NumConstants += 1;
    Constants[I] = Elem;
    Done[I] = true;
  }
}
// If there was at least one constant, fill in the other elements of
// Constants with undefs to get a full vector constant and use that
// as the starting point.
SDValue Result;
SDValue ReplicatedVal;
if (NumConstants > 0) {
  for (unsigned I = 0; I < NumElements; ++I)
    if (!Constants[I].getNode())
      Constants[I] = DAG.getUNDEF(Elems[I].getValueType());
  Result = DAG.getBuildVector(VT, DL, Constants);
} else {
  // Otherwise try to use VLREP or VLVGP to start the sequence in order to
  // avoid a false dependency on any previous contents of the vector
  // register.

  // Use a VLREP if at least one element is a load. Make sure to replicate
  // the load with the most elements having its value.
  std::map<const SDNode*, unsigned> UseCounts;
  SDNode *LoadMaxUses = nullptr;
  for (unsigned I = 0; I < NumElements; ++I)
    if (isVectorElementLoad(Elems[I])) {
      SDNode *Ld = Elems[I].getNode();
      UseCounts[Ld]++;
      if (LoadMaxUses == nullptr || UseCounts[LoadMaxUses] < UseCounts[Ld])
        LoadMaxUses = Ld;
    }
  if (LoadMaxUses != nullptr) {
    ReplicatedVal = SDValue(LoadMaxUses, 0);
    Result = DAG.getNode(SystemZISD::REPLICATE, DL, VT, ReplicatedVal);
  } else {
    // Try to use VLVGP.
    unsigned I1 = NumElements / 2 - 1;
    unsigned I2 = NumElements - 1;
    bool Def1 = !Elems[I1].isUndef();
    bool Def2 = !Elems[I2].isUndef();
    if (Def1 || Def2) {
      SDValue Elem1 = Elems[Def1 ? I1 : I2];
      SDValue Elem2 = Elems[Def2 ? I2 : I1];
      Result = DAG.getNode(ISD::BITCAST, DL, VT,
                           joinDwords(DAG, DL, Elem1, Elem2));
      Done[I1] = true;
      Done[I2] = true;
    } else
      Result = DAG.getUNDEF(VT);
  }
}

// Use VLVGx to insert the other elements.
for (unsigned I = 0; I < NumElements; ++I)
  if (!Done[I] && !Elems[I].isUndef() && Elems[I] != ReplicatedVal)
    Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, Result, Elems[I],
                         DAG.getConstant(I, DL, MVT::i32));
return Result;
5185}

5187SDValue SystemZTargetLowering::lowerBUILD_VECTOR(SDValue Op,
                                               SelectionDAG &DAG) const {
auto *BVN = cast<BuildVectorSDNode>(Op.getNode());
SDLoc DL(Op);
EVT VT = Op.getValueType();

if (BVN->isConstant()) {
  if (SystemZVectorConstantInfo(BVN).isVectorConstantLegal(Subtarget))
    return Op;

  // Fall back to loading it from memory.
  return SDValue();
}

// See if we should use shuffles to construct the vector from other vectors.
if (SDValue Res = tryBuildVectorShuffle(DAG, BVN))
  return Res;

// Detect SCALAR_TO_VECTOR conversions.
if (isOperationLegal(ISD::SCALAR_TO_VECTOR, VT) && isScalarToVector(Op))
  return buildScalarToVector(DAG, DL, VT, Op.getOperand(0));

// Otherwise use buildVector to build the vector up from GPRs.
unsigned NumElements = Op.getNumOperands();
SmallVector<SDValue, SystemZ::VectorBytes> Ops(NumElements);
for (unsigned I = 0; I < NumElements; ++I)
  Ops[I] = Op.getOperand(I);
return buildVector(DAG, DL, VT, Ops);
5215}

5217SDValue SystemZTargetLowering::lowerVECTOR_SHUFFLE(SDValue Op,
                                                 SelectionDAG &DAG) const {
auto *VSN = cast<ShuffleVectorSDNode>(Op.getNode());
SDLoc DL(Op);
EVT VT = Op.getValueType();
unsigned NumElements = VT.getVectorNumElements();

if (VSN->isSplat()) {
  SDValue Op0 = Op.getOperand(0);
  unsigned Index = VSN->getSplatIndex();
  assert(Index < VT.getVectorNumElements() &&(static_cast <bool> (Index < VT.getVectorNumElements
() && "Splat index should be defined and in first operand"
) ? void (0) : __assert_fail ("Index < VT.getVectorNumElements() && \"Splat index should be defined and in first operand\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp"
, 5228, __extension__ __PRETTY_FUNCTION__))
         "Splat index should be defined and in first operand")(static_cast <bool> (Index < VT.getVectorNumElements
() && "Splat index should be defined and in first operand"
) ? void (0) : __assert_fail ("Index < VT.getVectorNumElements() && \"Splat index should be defined and in first operand\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp"
, 5228, __extension__ __PRETTY_FUNCTION__));
  // See whether the value we're splatting is directly available as a scalar.
  if ((Index == 0 && Op0.getOpcode() == ISD::SCALAR_TO_VECTOR) ||
      Op0.getOpcode() == ISD::BUILD_VECTOR)
    return DAG.getNode(SystemZISD::REPLICATE, DL, VT, Op0.getOperand(Index));
  // Otherwise keep it as a vector-to-vector operation.
  return DAG.getNode(SystemZISD::SPLAT, DL, VT, Op.getOperand(0),
                     DAG.getTargetConstant(Index, DL, MVT::i32));
}

GeneralShuffle GS(VT);
for (unsigned I = 0; I < NumElements; ++I) {
  int Elt = VSN->getMaskElt(I);
  if (Elt < 0)
    GS.addUndef();
  else if (!GS.add(Op.getOperand(unsigned(Elt) / NumElements),
                   unsigned(Elt) % NumElements))
    return SDValue();
}
return GS.getNode(DAG, SDLoc(VSN));
5248}

5250SDValue SystemZTargetLowering::lowerSCALAR_TO_VECTOR(SDValue Op,
                                                   SelectionDAG &DAG) const {
SDLoc DL(Op);
// Just insert the scalar into element 0 of an undefined vector.
return DAG.getNode(ISD::INSERT_VECTOR_ELT, DL,
                   Op.getValueType(), DAG.getUNDEF(Op.getValueType()),
                   Op.getOperand(0), DAG.getConstant(0, DL, MVT::i32));
5257}

5259SDValue SystemZTargetLowering::lowerINSERT_VECTOR_ELT(SDValue Op,
                                                    SelectionDAG &DAG) const {
// Handle insertions of floating-point values.
SDLoc DL(Op);
SDValue Op0 = Op.getOperand(0);
SDValue Op1 = Op.getOperand(1);
SDValue Op2 = Op.getOperand(2);
EVT VT = Op.getValueType();

// Insertions into constant indices of a v2f64 can be done using VPDI.
// However, if the inserted value is a bitcast or a constant then it's
// better to use GPRs, as below.
if (VT == MVT::v2f64 &&
    Op1.getOpcode() != ISD::BITCAST &&
    Op1.getOpcode() != ISD::ConstantFP &&
    Op2.getOpcode() == ISD::Constant) {
  uint64_t Index = cast<ConstantSDNode>(Op2)->getZExtValue();
  unsigned Mask = VT.getVectorNumElements() - 1;
  if (Index <= Mask)
    return Op;
}

// Otherwise bitcast to the equivalent integer form and insert via a GPR.
MVT IntVT = MVT::getIntegerVT(VT.getScalarSizeInBits());
MVT IntVecVT = MVT::getVectorVT(IntVT, VT.getVectorNumElements());
SDValue Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, IntVecVT,
                          DAG.getNode(ISD::BITCAST, DL, IntVecVT, Op0),
                          DAG.getNode(ISD::BITCAST, DL, IntVT, Op1), Op2);
return DAG.getNode(ISD::BITCAST, DL, VT, Res);
5288}

5290SDValue
5291SystemZTargetLowering::lowerEXTRACT_VECTOR_ELT(SDValue Op,
                                             SelectionDAG &DAG) const {
// Handle extractions of floating-point values.
SDLoc DL(Op);
SDValue Op0 = Op.getOperand(0);
SDValue Op1 = Op.getOperand(1);
EVT VT = Op.getValueType();
EVT VecVT = Op0.getValueType();

// Extractions of constant indices can be done directly.
if (auto *CIndexN = dyn_cast<ConstantSDNode>(Op1)) {
  uint64_t Index = CIndexN->getZExtValue();
  unsigned Mask = VecVT.getVectorNumElements() - 1;
  if (Index <= Mask)
    return Op;
}

// Otherwise bitcast to the equivalent integer form and extract via a GPR.
MVT IntVT = MVT::getIntegerVT(VT.getSizeInBits());
MVT IntVecVT = MVT::getVectorVT(IntVT, VecVT.getVectorNumElements());
SDValue Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, IntVT,
                          DAG.getNode(ISD::BITCAST, DL, IntVecVT, Op0), Op1);
return DAG.getNode(ISD::BITCAST, DL, VT, Res);
5314}

5316SDValue SystemZTargetLowering::
5317lowerSIGN_EXTEND_VECTOR_INREG(SDValue Op, SelectionDAG &DAG) const {
SDValue PackedOp = Op.getOperand(0);
EVT OutVT = Op.getValueType();
EVT InVT = PackedOp.getValueType();
unsigned ToBits = OutVT.getScalarSizeInBits();
unsigned FromBits = InVT.getScalarSizeInBits();
do {
  FromBits *= 2;
  EVT OutVT = MVT::getVectorVT(MVT::getIntegerVT(FromBits),
                               SystemZ::VectorBits / FromBits);
  PackedOp =
    DAG.getNode(SystemZISD::UNPACK_HIGH, SDLoc(PackedOp), OutVT, PackedOp);
} while (FromBits != ToBits);
return PackedOp;
5331}

5333// Lower a ZERO_EXTEND_VECTOR_INREG to a vector shuffle with a zero vector.
5334SDValue SystemZTargetLowering::
5335lowerZERO_EXTEND_VECTOR_INREG(SDValue Op, SelectionDAG &DAG) const {
SDValue PackedOp = Op.getOperand(0);
SDLoc DL(Op);
EVT OutVT = Op.getValueType();
EVT InVT = PackedOp.getValueType();
unsigned InNumElts = InVT.getVectorNumElements();
unsigned OutNumElts = OutVT.getVectorNumElements();
unsigned NumInPerOut = InNumElts / OutNumElts;

SDValue ZeroVec =
  DAG.getSplatVector(InVT, DL, DAG.getConstant(0, DL, InVT.getScalarType()));

SmallVector<int, 16> Mask(InNumElts);
unsigned ZeroVecElt = InNumElts;
for (unsigned PackedElt = 0; PackedElt < OutNumElts; PackedElt++) {
  unsigned MaskElt = PackedElt * NumInPerOut;
  unsigned End = MaskElt + NumInPerOut - 1;
  for (; MaskElt < End; MaskElt++)
    Mask[MaskElt] = ZeroVecElt++;
  Mask[MaskElt] = PackedElt;
}
SDValue Shuf = DAG.getVectorShuffle(InVT, DL, PackedOp, ZeroVec, Mask);
return DAG.getNode(ISD::BITCAST, DL, OutVT, Shuf);
5358}

5360SDValue SystemZTargetLowering::lowerShift(SDValue Op, SelectionDAG &DAG,
                                        unsigned ByScalar) const {
// Look for cases where a vector shift can use the *_BY_SCALAR form.
SDValue Op0 = Op.getOperand(0);
SDValue Op1 = Op.getOperand(1);
SDLoc DL(Op);
EVT VT = Op.getValueType();
unsigned ElemBitSize = VT.getScalarSizeInBits();

// See whether the shift vector is a splat represented as BUILD_VECTOR.
if (auto *BVN = dyn_cast<BuildVectorSDNode>(Op1)) {
  APInt SplatBits, SplatUndef;
  unsigned SplatBitSize;
  bool HasAnyUndefs;
  // Check for constant splats.  Use ElemBitSize as the minimum element
  // width and reject splats that need wider elements.
  if (BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs,
                           ElemBitSize, true) &&
      SplatBitSize == ElemBitSize) {
    SDValue Shift = DAG.getConstant(SplatBits.getZExtValue() & 0xfff,
                                    DL, MVT::i32);
    return DAG.getNode(ByScalar, DL, VT, Op0, Shift);
  }
  // Check for variable splats.
  BitVector UndefElements;
  SDValue Splat = BVN->getSplatValue(&UndefElements);
  if (Splat) {
    // Since i32 is the smallest legal type, we either need a no-op
    // or a truncation.
    SDValue Shift = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Splat);
    return DAG.getNode(ByScalar, DL, VT, Op0, Shift);
  }
}

// See whether the shift vector is a splat represented as SHUFFLE_VECTOR,
// and the shift amount is directly available in a GPR.
if (auto *VSN = dyn_cast<ShuffleVectorSDNode>(Op1)) {
  if (VSN->isSplat()) {
    SDValue VSNOp0 = VSN->getOperand(0);
    unsigned Index = VSN->getSplatIndex();
    assert(Index < VT.getVectorNumElements() &&(static_cast <bool> (Index < VT.getVectorNumElements
() && "Splat index should be defined and in first operand"
) ? void (0) : __assert_fail ("Index < VT.getVectorNumElements() && \"Splat index should be defined and in first operand\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp"
, 5401, __extension__ __PRETTY_FUNCTION__))
           "Splat index should be defined and in first operand")(static_cast <bool> (Index < VT.getVectorNumElements
() && "Splat index should be defined and in first operand"
) ? void (0) : __assert_fail ("Index < VT.getVectorNumElements() && \"Splat index should be defined and in first operand\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp"
, 5401, __extension__ __PRETTY_FUNCTION__));
    if ((Index == 0 && VSNOp0.getOpcode() == ISD::SCALAR_TO_VECTOR) ||
        VSNOp0.getOpcode() == ISD::BUILD_VECTOR) {
      // Since i32 is the smallest legal type, we either need a no-op
      // or a truncation.
      SDValue Shift = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32,
                                  VSNOp0.getOperand(Index));
      return DAG.getNode(ByScalar, DL, VT, Op0, Shift);
    }
  }
}

// Otherwise just treat the current form as legal.
return Op;
5415}

5417SDValue SystemZTargetLowering::LowerOperation(SDValue Op,
                                            SelectionDAG &DAG) const {
switch (Op.getOpcode()) {
case ISD::FRAMEADDR:
  return lowerFRAMEADDR(Op, DAG);
case ISD::RETURNADDR:
  return lowerRETURNADDR(Op, DAG);
case ISD::BR_CC:
  return lowerBR_CC(Op, DAG);
case ISD::SELECT_CC:
  return lowerSELECT_CC(Op, DAG);
case ISD::SETCC:
  return lowerSETCC(Op, DAG);
case ISD::STRICT_FSETCC:
  return lowerSTRICT_FSETCC(Op, DAG, false);
case ISD::STRICT_FSETCCS:
  return lowerSTRICT_FSETCC(Op, DAG, true);
case ISD::GlobalAddress:
  return lowerGlobalAddress(cast<GlobalAddressSDNode>(Op), DAG);
case ISD::GlobalTLSAddress:
  return lowerGlobalTLSAddress(cast<GlobalAddressSDNode>(Op), DAG);
case ISD::BlockAddress:
  return lowerBlockAddress(cast<BlockAddressSDNode>(Op), DAG);
case ISD::JumpTable:
  return lowerJumpTable(cast<JumpTableSDNode>(Op), DAG);
case ISD::ConstantPool:
  return lowerConstantPool(cast<ConstantPoolSDNode>(Op), DAG);
case ISD::BITCAST:
  return lowerBITCAST(Op, DAG);
case ISD::VASTART:
  return lowerVASTART(Op, DAG);
case ISD::VACOPY:
  return lowerVACOPY(Op, DAG);
case ISD::DYNAMIC_STACKALLOC:
  return lowerDYNAMIC_STACKALLOC(Op, DAG);
case ISD::GET_DYNAMIC_AREA_OFFSET:
  return lowerGET_DYNAMIC_AREA_OFFSET(Op, DAG);
case ISD::SMUL_LOHI:
  return lowerSMUL_LOHI(Op, DAG);
case ISD::UMUL_LOHI:
  return lowerUMUL_LOHI(Op, DAG);
case ISD::SDIVREM:
  return lowerSDIVREM(Op, DAG);
case ISD::UDIVREM:
  return lowerUDIVREM(Op, DAG);
case ISD::SADDO:
case ISD::SSUBO:
case ISD::UADDO:
case ISD::USUBO:
  return lowerXALUO(Op, DAG);
case ISD::ADDCARRY:
case ISD::SUBCARRY:
  return lowerADDSUBCARRY(Op, DAG);
case ISD::OR:
  return lowerOR(Op, DAG);
case ISD::CTPOP:
  return lowerCTPOP(Op, DAG);
case ISD::ATOMIC_FENCE:
  return lowerATOMIC_FENCE(Op, DAG);
case ISD::ATOMIC_SWAP:
  return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_SWAPW);
case ISD::ATOMIC_STORE:
  return lowerATOMIC_STORE(Op, DAG);
case ISD::ATOMIC_LOAD:
  return lowerATOMIC_LOAD(Op, DAG);
case ISD::ATOMIC_LOAD_ADD:
  return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_LOADW_ADD);
case ISD::ATOMIC_LOAD_SUB:
  return lowerATOMIC_LOAD_SUB(Op, DAG);
case ISD::ATOMIC_LOAD_AND:
  return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_LOADW_AND);
case ISD::ATOMIC_LOAD_OR:
  return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_LOADW_OR);
case ISD::ATOMIC_LOAD_XOR:
  return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_LOADW_XOR);
case ISD::ATOMIC_LOAD_NAND:
  return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_LOADW_NAND);
case ISD::ATOMIC_LOAD_MIN:
  return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_LOADW_MIN);
case ISD::ATOMIC_LOAD_MAX:
  return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_LOADW_MAX);
case ISD::ATOMIC_LOAD_UMIN:
  return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_LOADW_UMIN);
case ISD::ATOMIC_LOAD_UMAX:
  return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_LOADW_UMAX);
case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
  return lowerATOMIC_CMP_SWAP(Op, DAG);
case ISD::STACKSAVE:
  return lowerSTACKSAVE(Op, DAG);
case ISD::STACKRESTORE:
  return lowerSTACKRESTORE(Op, DAG);
case ISD::PREFETCH:
  return lowerPREFETCH(Op, DAG);
case ISD::INTRINSIC_W_CHAIN:
  return lowerINTRINSIC_W_CHAIN(Op, DAG);
case ISD::INTRINSIC_WO_CHAIN:
  return lowerINTRINSIC_WO_CHAIN(Op, DAG);
case ISD::BUILD_VECTOR:
  return lowerBUILD_VECTOR(Op, DAG);
case ISD::VECTOR_SHUFFLE:
  return lowerVECTOR_SHUFFLE(Op, DAG);
case ISD::SCALAR_TO_VECTOR:
  return lowerSCALAR_TO_VECTOR(Op, DAG);
case ISD::INSERT_VECTOR_ELT:
  return lowerINSERT_VECTOR_ELT(Op, DAG);
case ISD::EXTRACT_VECTOR_ELT:
  return lowerEXTRACT_VECTOR_ELT(Op, DAG);
case ISD::SIGN_EXTEND_VECTOR_INREG:
  return lowerSIGN_EXTEND_VECTOR_INREG(Op, DAG);
case ISD::ZERO_EXTEND_VECTOR_INREG:
  return lowerZERO_EXTEND_VECTOR_INREG(Op, DAG);
case ISD::SHL:
  return lowerShift(Op, DAG, SystemZISD::VSHL_BY_SCALAR);
case ISD::SRL:
  return lowerShift(Op, DAG, SystemZISD::VSRL_BY_SCALAR);
case ISD::SRA:
  return lowerShift(Op, DAG, SystemZISD::VSRA_BY_SCALAR);
default:
  llvm_unreachable("Unexpected node to lower")::llvm::llvm_unreachable_internal("Unexpected node to lower",
 "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp"
, 5535);
}
5537}

5539// Lower operations with invalid operand or result types (currently used
5540// only for 128-bit integer types).
5541void
5542SystemZTargetLowering::LowerOperationWrapper(SDNode *N,
                                           SmallVectorImpl<SDValue> &Results,
                                           SelectionDAG &DAG) const {
switch (N->getOpcode()) {
case ISD::ATOMIC_LOAD: {
  SDLoc DL(N);
  SDVTList Tys = DAG.getVTList(MVT::Untyped, MVT::Other);
  SDValue Ops[] = { N->getOperand(0), N->getOperand(1) };
  MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
  SDValue Res = DAG.getMemIntrinsicNode(SystemZISD::ATOMIC_LOAD_128,
                                        DL, Tys, Ops, MVT::i128, MMO);
  Results.push_back(lowerGR128ToI128(DAG, Res));
  Results.push_back(Res.getValue(1));
  break;
}
case ISD::ATOMIC_STORE: {
  SDLoc DL(N);
  SDVTList Tys = DAG.getVTList(MVT::Other);
  SDValue Ops[] = { N->getOperand(0),
                    lowerI128ToGR128(DAG, N->getOperand(2)),
                    N->getOperand(1) };
  MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
  SDValue Res = DAG.getMemIntrinsicNode(SystemZISD::ATOMIC_STORE_128,
                                        DL, Tys, Ops, MVT::i128, MMO);
  // We have to enforce sequential consistency by performing a
  // serialization operation after the store.
  if (cast<AtomicSDNode>(N)->getSuccessOrdering() ==
      AtomicOrdering::SequentiallyConsistent)
    Res = SDValue(DAG.getMachineNode(SystemZ::Serialize, DL,
                                     MVT::Other, Res), 0);
  Results.push_back(Res);
  break;
}
case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: {
  SDLoc DL(N);
  SDVTList Tys = DAG.getVTList(MVT::Untyped, MVT::i32, MVT::Other);
  SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
                    lowerI128ToGR128(DAG, N->getOperand(2)),
                    lowerI128ToGR128(DAG, N->getOperand(3)) };
  MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
  SDValue Res = DAG.getMemIntrinsicNode(SystemZISD::ATOMIC_CMP_SWAP_128,
                                        DL, Tys, Ops, MVT::i128, MMO);
  SDValue Success = emitSETCC(DAG, DL, Res.getValue(1),
                              SystemZ::CCMASK_CS, SystemZ::CCMASK_CS_EQ);
  Success = DAG.getZExtOrTrunc(Success, DL, N->getValueType(1));
  Results.push_back(lowerGR128ToI128(DAG, Res));
  Results.push_back(Success);
  Results.push_back(Res.getValue(2));
  break;
}
default:
  llvm_unreachable("Unexpected node to lower")::llvm::llvm_unreachable_internal("Unexpected node to lower",
 "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp"
, 5593);
}
5595}

5597void
5598SystemZTargetLowering::ReplaceNodeResults(SDNode *N,
                                        SmallVectorImpl<SDValue> &Results,
                                        SelectionDAG &DAG) const {
return LowerOperationWrapper(N, Results, DAG);
5602}

5604const char *SystemZTargetLowering::getTargetNodeName(unsigned Opcode) const {
5605#define OPCODE(NAME) case SystemZISD::NAME: return "SystemZISD::" #NAME
switch ((SystemZISD::NodeType)Opcode) {
  case SystemZISD::FIRST_NUMBER: break;
  OPCODE(RET_FLAG);
  OPCODE(CALL);
  OPCODE(SIBCALL);
  OPCODE(TLS_GDCALL);
  OPCODE(TLS_LDCALL);
  OPCODE(PCREL_WRAPPER);
  OPCODE(PCREL_OFFSET);
  OPCODE(ICMP);
  OPCODE(FCMP);
  OPCODE(STRICT_FCMP);
  OPCODE(STRICT_FCMPS);
  OPCODE(TM);
  OPCODE(BR_CCMASK);
  OPCODE(SELECT_CCMASK);
  OPCODE(ADJDYNALLOC);
  OPCODE(PROBED_ALLOCA);
  OPCODE(POPCNT);
  OPCODE(SMUL_LOHI);
  OPCODE(UMUL_LOHI);
  OPCODE(SDIVREM);
  OPCODE(UDIVREM);
  OPCODE(SADDO);
  OPCODE(SSUBO);
  OPCODE(UADDO);
  OPCODE(USUBO);
  OPCODE(ADDCARRY);
  OPCODE(SUBCARRY);
  OPCODE(GET_CCMASK);
  OPCODE(MVC);
  OPCODE(MVC_LOOP);
  OPCODE(NC);
  OPCODE(NC_LOOP);
  OPCODE(OC);
  OPCODE(OC_LOOP);
  OPCODE(XC);
  OPCODE(XC_LOOP);
  OPCODE(CLC);
  OPCODE(CLC_LOOP);
  OPCODE(STPCPY);
  OPCODE(STRCMP);
  OPCODE(SEARCH_STRING);
  OPCODE(IPM);
  OPCODE(MEMBARRIER);
  OPCODE(TBEGIN);
  OPCODE(TBEGIN_NOFLOAT);
  OPCODE(TEND);
  OPCODE(BYTE_MASK);
  OPCODE(ROTATE_MASK);
  OPCODE(REPLICATE);
  OPCODE(JOIN_DWORDS);
  OPCODE(SPLAT);
  OPCODE(MERGE_HIGH);
  OPCODE(MERGE_LOW);
  OPCODE(SHL_DOUBLE);
  OPCODE(PERMUTE_DWORDS);
  OPCODE(PERMUTE);
  OPCODE(PACK);
  OPCODE(PACKS_CC);
  OPCODE(PACKLS_CC);
  OPCODE(UNPACK_HIGH);
  OPCODE(UNPACKL_HIGH);
  OPCODE(UNPACK_LOW);
  OPCODE(UNPACKL_LOW);
  OPCODE(VSHL_BY_SCALAR);
  OPCODE(VSRL_BY_SCALAR);
  OPCODE(VSRA_BY_SCALAR);
  OPCODE(VSUM);
  OPCODE(VICMPE);
  OPCODE(VICMPH);
  OPCODE(VICMPHL);
  OPCODE(VICMPES);
  OPCODE(VICMPHS);
  OPCODE(VICMPHLS);
  OPCODE(VFCMPE);
  OPCODE(STRICT_VFCMPE);
  OPCODE(STRICT_VFCMPES);
  OPCODE(VFCMPH);
  OPCODE(STRICT_VFCMPH);
  OPCODE(STRICT_VFCMPHS);
  OPCODE(VFCMPHE);
  OPCODE(STRICT_VFCMPHE);
  OPCODE(STRICT_VFCMPHES);
  OPCODE(VFCMPES);
  OPCODE(VFCMPHS);
  OPCODE(VFCMPHES);
  OPCODE(VFTCI);
  OPCODE(VEXTEND);
  OPCODE(STRICT_VEXTEND);
  OPCODE(VROUND);
  OPCODE(STRICT_VROUND);
  OPCODE(VTM);
  OPCODE(VFAE_CC);
  OPCODE(VFAEZ_CC);
  OPCODE(VFEE_CC);
  OPCODE(VFEEZ_CC);
  OPCODE(VFENE_CC);
  OPCODE(VFENEZ_CC);
  OPCODE(VISTR_CC);
  OPCODE(VSTRC_CC);
  OPCODE(VSTRCZ_CC);
  OPCODE(VSTRS_CC);
  OPCODE(VSTRSZ_CC);
  OPCODE(TDC);
  OPCODE(ATOMIC_SWAPW);
  OPCODE(ATOMIC_LOADW_ADD);
  OPCODE(ATOMIC_LOADW_SUB);
  OPCODE(ATOMIC_LOADW_AND);
  OPCODE(ATOMIC_LOADW_OR);
  OPCODE(ATOMIC_LOADW_XOR);
  OPCODE(ATOMIC_LOADW_NAND);
  OPCODE(ATOMIC_LOADW_MIN);
  OPCODE(ATOMIC_LOADW_MAX);
  OPCODE(ATOMIC_LOADW_UMIN);
  OPCODE(ATOMIC_LOADW_UMAX);
  OPCODE(ATOMIC_CMP_SWAPW);
  OPCODE(ATOMIC_CMP_SWAP);
  OPCODE(ATOMIC_LOAD_128);
  OPCODE(ATOMIC_STORE_128);
  OPCODE(ATOMIC_CMP_SWAP_128);
  OPCODE(LRV);
  OPCODE(STRV);
  OPCODE(VLER);
  OPCODE(VSTER);
  OPCODE(PREFETCH);
}
return nullptr;
5734#undef OPCODE
5735}

5737// Return true if VT is a vector whose elements are a whole number of bytes
5738// in width. Also check for presence of vector support.
5739bool SystemZTargetLowering::canTreatAsByteVector(EVT VT) const {
if (!Subtarget.hasVector())
  return false;

return VT.isVector() && VT.getScalarSizeInBits() % 8 == 0 && VT.isSimple();
5744}

5746// Try to simplify an EXTRACT_VECTOR_ELT from a vector of type VecVT
5747// producing a result of type ResVT.  Op is a possibly bitcast version
5748// of the input vector and Index is the index (based on type VecVT) that
5749// should be extracted.  Return the new extraction if a simplification
5750// was possible or if Force is true.
5751SDValue SystemZTargetLowering::combineExtract(const SDLoc &DL, EVT ResVT,
                                            EVT VecVT, SDValue Op,
                                            unsigned Index,
                                            DAGCombinerInfo &DCI,
                                            bool Force) const {
SelectionDAG &DAG = DCI.DAG;

// The number of bytes being extracted.
unsigned BytesPerElement = VecVT.getVectorElementType().getStoreSize();

for (;;) {
  unsigned Opcode = Op.getOpcode();
  if (Opcode == ISD::BITCAST)
    // Look through bitcasts.
    Op = Op.getOperand(0);
  else if ((Opcode == ISD::VECTOR_SHUFFLE || Opcode == SystemZISD::SPLAT) &&
           canTreatAsByteVector(Op.getValueType())) {
    // Get a VPERM-like permute mask and see whether the bytes covered
    // by the extracted element are a contiguous sequence from one
    // source operand.
    SmallVector<int, SystemZ::VectorBytes> Bytes;
    if (!getVPermMask(Op, Bytes))
      break;
    int First;
    if (!getShuffleInput(Bytes, Index * BytesPerElement,
                         BytesPerElement, First))
      break;
    if (First < 0)
      return DAG.getUNDEF(ResVT);
    // Make sure the contiguous sequence starts at a multiple of the
    // original element size.
    unsigned Byte = unsigned(First) % Bytes.size();
    if (Byte % BytesPerElement != 0)
      break;
    // We can get the extracted value directly from an input.
    Index = Byte / BytesPerElement;
    Op = Op.getOperand(unsigned(First) / Bytes.size());
    Force = true;
  } else if (Opcode == ISD::BUILD_VECTOR &&
             canTreatAsByteVector(Op.getValueType())) {
    // We can only optimize this case if the BUILD_VECTOR elements are
    // at least as wide as the extracted value.
    EVT OpVT = Op.getValueType();
    unsigned OpBytesPerElement = OpVT.getVectorElementType().getStoreSize();
    if (OpBytesPerElement < BytesPerElement)
      break;
    // Make sure that the least-significant bit of the extracted value
    // is the least significant bit of an input.
    unsigned End = (Index + 1) * BytesPerElement;
    if (End % OpBytesPerElement != 0)
      break;
    // We're extracting the low part of one operand of the BUILD_VECTOR.
    Op = Op.getOperand(End / OpBytesPerElement - 1);
    if (!Op.getValueType().isInteger()) {
      EVT VT = MVT::getIntegerVT(Op.getValueSizeInBits());
      Op = DAG.getNode(ISD::BITCAST, DL, VT, Op);
      DCI.AddToWorklist(Op.getNode());
    }
    EVT VT = MVT::getIntegerVT(ResVT.getSizeInBits());
    Op = DAG.getNode(ISD::TRUNCATE, DL, VT, Op);
    if (VT != ResVT) {
      DCI.AddToWorklist(Op.getNode());
      Op = DAG.getNode(ISD::BITCAST, DL, ResVT, Op);
    }
    return Op;
  } else if ((Opcode == ISD::SIGN_EXTEND_VECTOR_INREG ||
              Opcode == ISD::ZERO_EXTEND_VECTOR_INREG ||
              Opcode == ISD::ANY_EXTEND_VECTOR_INREG) &&
             canTreatAsByteVector(Op.getValueType()) &&
             canTreatAsByteVector(Op.getOperand(0).getValueType())) {
    // Make sure that only the unextended bits are significant.
    EVT ExtVT = Op.getValueType();
    EVT OpVT = Op.getOperand(0).getValueType();
    unsigned ExtBytesPerElement = ExtVT.getVectorElementType().getStoreSize();
    unsigned OpBytesPerElement = OpVT.getVectorElementType().getStoreSize();
    unsigned Byte = Index * BytesPerElement;
    unsigned SubByte = Byte % ExtBytesPerElement;
    unsigned MinSubByte = ExtBytesPerElement - OpBytesPerElement;
    if (SubByte < MinSubByte ||
        SubByte + BytesPerElement > ExtBytesPerElement)
      break;
    // Get the byte offset of the unextended element
    Byte = Byte / ExtBytesPerElement * OpBytesPerElement;
    // ...then add the byte offset relative to that element.
    Byte += SubByte - MinSubByte;
    if (Byte % BytesPerElement != 0)
      break;
    Op = Op.getOperand(0);
    Index = Byte / BytesPerElement;
    Force = true;
  } else
    break;
}
if (Force) {
  if (Op.getValueType() != VecVT) {
    Op = DAG.getNode(ISD::BITCAST, DL, VecVT, Op);
    DCI.AddToWorklist(Op.getNode());
  }
  return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ResVT, Op,
                     DAG.getConstant(Index, DL, MVT::i32));
}
return SDValue();
5853}

5855// Optimize vector operations in scalar value Op on the basis that Op
5856// is truncated to TruncVT.
5857SDValue SystemZTargetLowering::combineTruncateExtract(
  const SDLoc &DL, EVT TruncVT, SDValue Op, DAGCombinerInfo &DCI) const {
// If we have (trunc (extract_vector_elt X, Y)), try to turn it into
// (extract_vector_elt (bitcast X), Y'), where (bitcast X) has elements
// of type TruncVT.
if (Op.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
    TruncVT.getSizeInBits() % 8 == 0) {
  SDValue Vec = Op.getOperand(0);
  EVT VecVT = Vec.getValueType();
  if (canTreatAsByteVector(VecVT)) {
    if (auto *IndexN = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
      unsigned BytesPerElement = VecVT.getVectorElementType().getStoreSize();
      unsigned TruncBytes = TruncVT.getStoreSize();
      if (BytesPerElement % TruncBytes == 0) {
        // Calculate the value of Y' in the above description.  We are
        // splitting the original elements into Scale equal-sized pieces
        // and for truncation purposes want the last (least-significant)
        // of these pieces for IndexN.  This is easiest to do by calculating
        // the start index of the following element and then subtracting 1.
        unsigned Scale = BytesPerElement / TruncBytes;
        unsigned NewIndex = (IndexN->getZExtValue() + 1) * Scale - 1;

        // Defer the creation of the bitcast from X to combineExtract,
        // which might be able to optimize the extraction.
        VecVT = MVT::getVectorVT(MVT::getIntegerVT(TruncBytes * 8),
                                 VecVT.getStoreSize() / TruncBytes);
        EVT ResVT = (TruncBytes < 4 ? MVT::i32 : TruncVT);
        return combineExtract(DL, ResVT, VecVT, Vec, NewIndex, DCI, true);
      }
    }
  }
}
return SDValue();
5890}

5892SDValue SystemZTargetLowering::combineZERO_EXTEND(
  SDNode *N, DAGCombinerInfo &DCI) const {
// Convert (zext (select_ccmask C1, C2)) into (select_ccmask C1', C2')
SelectionDAG &DAG = DCI.DAG;
SDValue N0 = N->getOperand(0);
EVT VT = N->getValueType(0);
if (N0.getOpcode() == SystemZISD::SELECT_CCMASK) {
  auto *TrueOp = dyn_cast<ConstantSDNode>(N0.getOperand(0));
  auto *FalseOp = dyn_cast<ConstantSDNode>(N0.getOperand(1));
  if (TrueOp && FalseOp) {
    SDLoc DL(N0);
    SDValue Ops[] = { DAG.getConstant(TrueOp->getZExtValue(), DL, VT),
                      DAG.getConstant(FalseOp->getZExtValue(), DL, VT),
                      N0.getOperand(2), N0.getOperand(3), N0.getOperand(4) };
    SDValue NewSelect = DAG.getNode(SystemZISD::SELECT_CCMASK, DL, VT, Ops);
    // If N0 has multiple uses, change other uses as well.
    if (!N0.hasOneUse()) {
      SDValue TruncSelect =
        DAG.getNode(ISD::TRUNCATE, DL, N0.getValueType(), NewSelect);
      DCI.CombineTo(N0.getNode(), TruncSelect);
    }
    return NewSelect;
  }
}
return SDValue();
5917}

5919SDValue SystemZTargetLowering::combineSIGN_EXTEND_INREG(
  SDNode *N, DAGCombinerInfo &DCI) const {
// Convert (sext_in_reg (setcc LHS, RHS, COND), i1)
// and (sext_in_reg (any_extend (setcc LHS, RHS, COND)), i1)
// into (select_cc LHS, RHS, -1, 0, COND)
SelectionDAG &DAG = DCI.DAG;
SDValue N0 = N->getOperand(0);
EVT VT = N->getValueType(0);
EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
if (N0.hasOneUse() && N0.getOpcode() == ISD::ANY_EXTEND)
  N0 = N0.getOperand(0);
if (EVT == MVT::i1 && N0.hasOneUse() && N0.getOpcode() == ISD::SETCC) {
  SDLoc DL(N0);
  SDValue Ops[] = { N0.getOperand(0), N0.getOperand(1),
                    DAG.getConstant(-1, DL, VT), DAG.getConstant(0, DL, VT),
                    N0.getOperand(2) };
  return DAG.getNode(ISD::SELECT_CC, DL, VT, Ops);
}
return SDValue();
5938}

5940SDValue SystemZTargetLowering::combineSIGN_EXTEND(
  SDNode *N, DAGCombinerInfo &DCI) const {
// Convert (sext (ashr (shl X, C1), C2)) to
// (ashr (shl (anyext X), C1'), C2')), since wider shifts are as
// cheap as narrower ones.
SelectionDAG &DAG = DCI.DAG;
SDValue N0 = N->getOperand(0);
EVT VT = N->getValueType(0);
if (N0.hasOneUse() && N0.getOpcode() == ISD::SRA) {
  auto *SraAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1));
  SDValue Inner = N0.getOperand(0);
  if (SraAmt && Inner.hasOneUse() && Inner.getOpcode() == ISD::SHL) {
    if (auto *ShlAmt = dyn_cast<ConstantSDNode>(Inner.getOperand(1))) {
      unsigned Extra = (VT.getSizeInBits() - N0.getValueSizeInBits());
      unsigned NewShlAmt = ShlAmt->getZExtValue() + Extra;
      unsigned NewSraAmt = SraAmt->getZExtValue() + Extra;
      EVT ShiftVT = N0.getOperand(1).getValueType();
      SDValue Ext = DAG.getNode(ISD::ANY_EXTEND, SDLoc(Inner), VT,
                                Inner.getOperand(0));
      SDValue Shl = DAG.getNode(ISD::SHL, SDLoc(Inner), VT, Ext,
                                DAG.getConstant(NewShlAmt, SDLoc(Inner),
                                                ShiftVT));
      return DAG.getNode(ISD::SRA, SDLoc(N0), VT, Shl,
                         DAG.getConstant(NewSraAmt, SDLoc(N0), ShiftVT));
    }
  }
}
return SDValue();
5968}

5970SDValue SystemZTargetLowering::combineMERGE(
  SDNode *N, DAGCombinerInfo &DCI) const {
SelectionDAG &DAG = DCI.DAG;
unsigned Opcode = N->getOpcode();
SDValue Op0 = N->getOperand(0);
SDValue Op1 = N->getOperand(1);
if (Op0.getOpcode() == ISD::BITCAST)
  Op0 = Op0.getOperand(0);
if (ISD::isBuildVectorAllZeros(Op0.getNode())) {
  // (z_merge_* 0, 0) -> 0.  This is mostly useful for using VLLEZF
  // for v4f32.
  if (Op1 == N->getOperand(0))
    return Op1;
  // (z_merge_? 0, X) -> (z_unpackl_? 0, X).
  EVT VT = Op1.getValueType();
  unsigned ElemBytes = VT.getVectorElementType().getStoreSize();
  if (ElemBytes <= 4) {
    Opcode = (Opcode == SystemZISD::MERGE_HIGH ?
              SystemZISD::UNPACKL_HIGH : SystemZISD::UNPACKL_LOW);
    EVT InVT = VT.changeVectorElementTypeToInteger();
    EVT OutVT = MVT::getVectorVT(MVT::getIntegerVT(ElemBytes * 16),
                                 SystemZ::VectorBytes / ElemBytes / 2);
    if (VT != InVT) {
      Op1 = DAG.getNode(ISD::BITCAST, SDLoc(N), InVT, Op1);
      DCI.AddToWorklist(Op1.getNode());
    }
    SDValue Op = DAG.getNode(Opcode, SDLoc(N), OutVT, Op1);
    DCI.AddToWorklist(Op.getNode());
    return DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op);
  }
}
return SDValue();
6002}

6004SDValue SystemZTargetLowering::combineLOAD(
  SDNode *N, DAGCombinerInfo &DCI) const {
SelectionDAG &DAG = DCI.DAG;
EVT LdVT = N->getValueType(0);
if (LdVT.isVector() || LdVT.isInteger())
  return SDValue();
// Transform a scalar load that is REPLICATEd as well as having other
// use(s) to the form where the other use(s) use the first element of the
// REPLICATE instead of the load. Otherwise instruction selection will not
// produce a VLREP. Avoid extracting to a GPR, so only do this for floating
// point loads.

SDValue Replicate;
SmallVector<SDNode*, 8> OtherUses;
for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
     UI != UE; ++UI) {
  if (UI->getOpcode() == SystemZISD::REPLICATE) {
    if (Replicate)
      return SDValue(); // Should never happen
    Replicate = SDValue(*UI, 0);
  }
  else if (UI.getUse().getResNo() == 0)
    OtherUses.push_back(*UI);
}
if (!Replicate || OtherUses.empty())
  return SDValue();

SDLoc DL(N);
SDValue Extract0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, LdVT,
                            Replicate, DAG.getConstant(0, DL, MVT::i32));
// Update uses of the loaded Value while preserving old chains.
for (SDNode *U : OtherUses) {
  SmallVector<SDValue, 8> Ops;
  for (SDValue Op : U->ops())
    Ops.push_back((Op.getNode() == N && Op.getResNo() == 0) ? Extract0 : Op);
  DAG.UpdateNodeOperands(U, Ops);
}
return SDValue(N, 0);
6042}

6044bool SystemZTargetLowering::canLoadStoreByteSwapped(EVT VT) const {
if (VT == MVT::i16 || VT == MVT::i32 || VT == MVT::i64)
  return true;
if (Subtarget.hasVectorEnhancements2())
  if (VT == MVT::v8i16 || VT == MVT::v4i32 || VT == MVT::v2i64)
    return true;
return false;
6051}

6053static bool isVectorElementSwap(ArrayRef<int> M, EVT VT) {
if (!VT.isVector() || !VT.isSimple() ||
    VT.getSizeInBits() != 128 ||
    VT.getScalarSizeInBits() % 8 != 0)
  return false;

unsigned NumElts = VT.getVectorNumElements();
for (unsigned i = 0; i < NumElts; ++i) {
  if (M[i] < 0) continue; // ignore UNDEF indices
  if ((unsigned) M[i] != NumElts - 1 - i)
    return false;
}

return true;
6067}

6069SDValue SystemZTargetLowering::combineSTORE(
  SDNode *N, DAGCombinerInfo &DCI) const {
SelectionDAG &DAG = DCI.DAG;
auto *SN = cast<StoreSDNode>(N);
auto &Op1 = N->getOperand(1);
EVT MemVT = SN->getMemoryVT();
// If we have (truncstoreiN (extract_vector_elt X, Y), Z) then it is better
// for the extraction to be done on a vMiN value, so that we can use VSTE.
// If X has wider elements then convert it to:
// (truncstoreiN (extract_vector_elt (bitcast X), Y2), Z).
if (MemVT.isInteger() && SN->isTruncatingStore()) {
  if (SDValue Value =
          combineTruncateExtract(SDLoc(N), MemVT, SN->getValue(), DCI)) {
    DCI.AddToWorklist(Value.getNode());

    // Rewrite the store with the new form of stored value.
    return DAG.getTruncStore(SN->getChain(), SDLoc(SN), Value,
                             SN->getBasePtr(), SN->getMemoryVT(),
                             SN->getMemOperand());
  }
}
// Combine STORE (BSWAP) into STRVH/STRV/STRVG/VSTBR
if (!SN->isTruncatingStore() &&
    Op1.getOpcode() == ISD::BSWAP &&
    Op1.getNode()->hasOneUse() &&
    canLoadStoreByteSwapped(Op1.getValueType())) {

    SDValue BSwapOp = Op1.getOperand(0);

    if (BSwapOp.getValueType() == MVT::i16)
      BSwapOp = DAG.getNode(ISD::ANY_EXTEND, SDLoc(N), MVT::i32, BSwapOp);

    SDValue Ops[] = {
      N->getOperand(0), BSwapOp, N->getOperand(2)
    };

    return
      DAG.getMemIntrinsicNode(SystemZISD::STRV, SDLoc(N), DAG.getVTList(MVT::Other),
                              Ops, MemVT, SN->getMemOperand());
  }
// Combine STORE (element-swap) into VSTER
if (!SN->isTruncatingStore() &&
    Op1.getOpcode() == ISD::VECTOR_SHUFFLE &&
    Op1.getNode()->hasOneUse() &&
    Subtarget.hasVectorEnhancements2()) {
  ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(Op1.getNode());
  ArrayRef<int> ShuffleMask = SVN->getMask();
  if (isVectorElementSwap(ShuffleMask, Op1.getValueType())) {
    SDValue Ops[] = {
      N->getOperand(0), Op1.getOperand(0), N->getOperand(2)
    };

    return DAG.getMemIntrinsicNode(SystemZISD::VSTER, SDLoc(N),
                                   DAG.getVTList(MVT::Other),
                                   Ops, MemVT, SN->getMemOperand());
  }
}

return SDValue();
6128}

6130SDValue SystemZTargetLowering::combineVECTOR_SHUFFLE(
  SDNode *N, DAGCombinerInfo &DCI) const {
SelectionDAG &DAG = DCI.DAG;
// Combine element-swap (LOAD) into VLER
if (ISD::isNON_EXTLoad(N->getOperand(0).getNode()) &&
    N->getOperand(0).hasOneUse() &&
    Subtarget.hasVectorEnhancements2()) {
  ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N);
  ArrayRef<int> ShuffleMask = SVN->getMask();
  if (isVectorElementSwap(ShuffleMask, N->getValueType(0))) {
    SDValue Load = N->getOperand(0);
    LoadSDNode *LD = cast<LoadSDNode>(Load);

    // Create the element-swapping load.
    SDValue Ops[] = {
      LD->getChain(),    // Chain
      LD->getBasePtr()   // Ptr
    };
    SDValue ESLoad =
      DAG.getMemIntrinsicNode(SystemZISD::VLER, SDLoc(N),
                              DAG.getVTList(LD->getValueType(0), MVT::Other),
                              Ops, LD->getMemoryVT(), LD->getMemOperand());

    // First, combine the VECTOR_SHUFFLE away.  This makes the value produced
    // by the load dead.
    DCI.CombineTo(N, ESLoad);

    // Next, combine the load away, we give it a bogus result value but a real
    // chain result.  The result value is dead because the shuffle is dead.
    DCI.CombineTo(Load.getNode(), ESLoad, ESLoad.getValue(1));

    // Return N so it doesn't get rechecked!
    return SDValue(N, 0);
  }
}

return SDValue();
6167}

6169SDValue SystemZTargetLowering::combineEXTRACT_VECTOR_ELT(
  SDNode *N, DAGCombinerInfo &DCI) const {
SelectionDAG &DAG = DCI.DAG;

if (!Subtarget.hasVector())
  return SDValue();

// Look through bitcasts that retain the number of vector elements.
SDValue Op = N->getOperand(0);
if (Op.getOpcode() == ISD::BITCAST &&
    Op.getValueType().isVector() &&
    Op.getOperand(0).getValueType().isVector() &&
    Op.getValueType().getVectorNumElements() ==
    Op.getOperand(0).getValueType().getVectorNumElements())
  Op = Op.getOperand(0);

// Pull BSWAP out of a vector extraction.
if (Op.getOpcode() == ISD::BSWAP && Op.hasOneUse()) {
  EVT VecVT = Op.getValueType();
  EVT EltVT = VecVT.getVectorElementType();
  Op = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(N), EltVT,
                   Op.getOperand(0), N->getOperand(1));
  DCI.AddToWorklist(Op.getNode());
  Op = DAG.getNode(ISD::BSWAP, SDLoc(N), EltVT, Op);
  if (EltVT != N->getValueType(0)) {
    DCI.AddToWorklist(Op.getNode());
    Op = DAG.getNode(ISD::BITCAST, SDLoc(N), N->getValueType(0), Op);
  }
  return Op;
}

// Try to simplify a vector extraction.
if (auto *IndexN = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
  SDValue Op0 = N->getOperand(0);
  EVT VecVT = Op0.getValueType();
  return combineExtract(SDLoc(N), N->getValueType(0), VecVT, Op0,
                        IndexN->getZExtValue(), DCI, false);
}
return SDValue();
6208}

6210SDValue SystemZTargetLowering::combineJOIN_DWORDS(
  SDNode *N, DAGCombinerInfo &DCI) const {
SelectionDAG &DAG = DCI.DAG;
// (join_dwords X, X) == (replicate X)
if (N->getOperand(0) == N->getOperand(1))
  return DAG.getNode(SystemZISD::REPLICATE, SDLoc(N), N->getValueType(0),
                     N->getOperand(0));
return SDValue();
6218}

6220static SDValue MergeInputChains(SDNode *N1, SDNode *N2) {
SDValue Chain1 = N1->getOperand(0);
SDValue Chain2 = N2->getOperand(0);

// Trivial case: both nodes take the same chain.
if (Chain1 == Chain2)
  return Chain1;

// FIXME - we could handle more complex cases via TokenFactor,
// assuming we can verify that this would not create a cycle.
return SDValue();
6231}

6233SDValue SystemZTargetLowering::combineFP_ROUND(
  SDNode *N, DAGCombinerInfo &DCI) const {

if (!Subtarget.hasVector())
  return SDValue();

// (fpround (extract_vector_elt X 0))
// (fpround (extract_vector_elt X 1)) ->
// (extract_vector_elt (VROUND X) 0)
// (extract_vector_elt (VROUND X) 2)
//
// This is a special case since the target doesn't really support v2f32s.
unsigned OpNo = N->isStrictFPOpcode() ? 1 : 0;
SelectionDAG &DAG = DCI.DAG;
SDValue Op0 = N->getOperand(OpNo);
if (N->getValueType(0) == MVT::f32 &&
    Op0.hasOneUse() &&
    Op0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
    Op0.getOperand(0).getValueType() == MVT::v2f64 &&
    Op0.getOperand(1).getOpcode() == ISD::Constant &&
    cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue() == 0) {
  SDValue Vec = Op0.getOperand(0);
  for (auto *U : Vec->uses()) {
    if (U != Op0.getNode() &&
        U->hasOneUse() &&
        U->getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
        U->getOperand(0) == Vec &&
        U->getOperand(1).getOpcode() == ISD::Constant &&
        cast<ConstantSDNode>(U->getOperand(1))->getZExtValue() == 1) {
      SDValue OtherRound = SDValue(*U->use_begin(), 0);
      if (OtherRound.getOpcode() == N->getOpcode() &&
          OtherRound.getOperand(OpNo) == SDValue(U, 0) &&
          OtherRound.getValueType() == MVT::f32) {
        SDValue VRound, Chain;
        if (N->isStrictFPOpcode()) {
          Chain = MergeInputChains(N, OtherRound.getNode());
          if (!Chain)
            continue;
          VRound = DAG.getNode(SystemZISD::STRICT_VROUND, SDLoc(N),
                               {MVT::v4f32, MVT::Other}, {Chain, Vec});
          Chain = VRound.getValue(1);
        } else
          VRound = DAG.getNode(SystemZISD::VROUND, SDLoc(N),
                               MVT::v4f32, Vec);
        DCI.AddToWorklist(VRound.getNode());
        SDValue Extract1 =
          DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(U), MVT::f32,
                      VRound, DAG.getConstant(2, SDLoc(U), MVT::i32));
        DCI.AddToWorklist(Extract1.getNode());
        DAG.ReplaceAllUsesOfValueWith(OtherRound, Extract1);
        if (Chain)
          DAG.ReplaceAllUsesOfValueWith(OtherRound.getValue(1), Chain);
        SDValue Extract0 =
          DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(Op0), MVT::f32,
                      VRound, DAG.getConstant(0, SDLoc(Op0), MVT::i32));
        if (Chain)
          return DAG.getNode(ISD::MERGE_VALUES, SDLoc(Op0),
                             N->getVTList(), Extract0, Chain);
        return Extract0;
      }
    }
  }
}
return SDValue();
6297}

6299SDValue SystemZTargetLowering::combineFP_EXTEND(
  SDNode *N, DAGCombinerInfo &DCI) const {

if (!Subtarget.hasVector())
  return SDValue();

// (fpextend (extract_vector_elt X 0))
// (fpextend (extract_vector_elt X 2)) ->
// (extract_vector_elt (VEXTEND X) 0)
// (extract_vector_elt (VEXTEND X) 1)
//
// This is a special case since the target doesn't really support v2f32s.
unsigned OpNo = N->isStrictFPOpcode() ? 1 : 0;
SelectionDAG &DAG = DCI.DAG;
SDValue Op0 = N->getOperand(OpNo);
if (N->getValueType(0) == MVT::f64 &&
    Op0.hasOneUse() &&
    Op0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
    Op0.getOperand(0).getValueType() == MVT::v4f32 &&
    Op0.getOperand(1).getOpcode() == ISD::Constant &&
    cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue() == 0) {
  SDValue Vec = Op0.getOperand(0);
  for (auto *U : Vec->uses()) {
    if (U != Op0.getNode() &&
        U->hasOneUse() &&
        U->getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
        U->getOperand(0) == Vec &&
        U->getOperand(1).getOpcode() == ISD::Constant &&
        cast<ConstantSDNode>(U->getOperand(1))->getZExtValue() == 2) {
      SDValue OtherExtend = SDValue(*U->use_begin(), 0);
      if (OtherExtend.getOpcode() == N->getOpcode() &&
          OtherExtend.getOperand(OpNo) == SDValue(U, 0) &&
          OtherExtend.getValueType() == MVT::f64) {
        SDValue VExtend, Chain;
        if (N->isStrictFPOpcode()) {
          Chain = MergeInputChains(N, OtherExtend.getNode());
          if (!Chain)
            continue;
          VExtend = DAG.getNode(SystemZISD::STRICT_VEXTEND, SDLoc(N),
                                {MVT::v2f64, MVT::Other}, {Chain, Vec});
          Chain = VExtend.getValue(1);
        } else
          VExtend = DAG.getNode(SystemZISD::VEXTEND, SDLoc(N),
                                MVT::v2f64, Vec);
        DCI.AddToWorklist(VExtend.getNode());
        SDValue Extract1 =
          DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(U), MVT::f64,
                      VExtend, DAG.getConstant(1, SDLoc(U), MVT::i32));
        DCI.AddToWorklist(Extract1.getNode());
        DAG.ReplaceAllUsesOfValueWith(OtherExtend, Extract1);
        if (Chain)
          DAG.ReplaceAllUsesOfValueWith(OtherExtend.getValue(1), Chain);
        SDValue Extract0 =
          DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(Op0), MVT::f64,
                      VExtend, DAG.getConstant(0, SDLoc(Op0), MVT::i32));
        if (Chain)
          return DAG.getNode(ISD::MERGE_VALUES, SDLoc(Op0),
                             N->getVTList(), Extract0, Chain);
        return Extract0;
      }
    }
  }
}
return SDValue();
6363}

6365SDValue SystemZTargetLowering::combineINT_TO_FP(
  SDNode *N, DAGCombinerInfo &DCI) const {
if (DCI.Level != BeforeLegalizeTypes)
  return SDValue();
unsigned Opcode = N->getOpcode();
EVT OutVT = N->getValueType(0);
SelectionDAG &DAG = DCI.DAG;
SDValue Op = N->getOperand(0);
unsigned OutScalarBits = OutVT.getScalarSizeInBits();
unsigned InScalarBits = Op->getValueType(0).getScalarSizeInBits();

// Insert an extension before type-legalization to avoid scalarization, e.g.:
// v2f64 = uint_to_fp v2i16
// =>
// v2f64 = uint_to_fp (v2i64 zero_extend v2i16)
if (OutVT.isVector() && OutScalarBits > InScalarBits) {
  MVT ExtVT = MVT::getVectorVT(MVT::getIntegerVT(OutVT.getScalarSizeInBits()),
                               OutVT.getVectorNumElements());
  unsigned ExtOpcode =
    (Opcode == ISD::UINT_TO_FP ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND);
  SDValue ExtOp = DAG.getNode(ExtOpcode, SDLoc(N), ExtVT, Op);
  return DAG.getNode(Opcode, SDLoc(N), OutVT, ExtOp);
}
return SDValue();
6389}

6391SDValue SystemZTargetLowering::combineBSWAP(
  SDNode *N, DAGCombinerInfo &DCI) const {
SelectionDAG &DAG = DCI.DAG;
// Combine BSWAP (LOAD) into LRVH/LRV/LRVG/VLBR
if (ISD::isNON_EXTLoad(N->getOperand(0).getNode()) &&
    N->getOperand(0).hasOneUse() &&
    canLoadStoreByteSwapped(N->getValueType(0))) {
    SDValue Load = N->getOperand(0);
    LoadSDNode *LD = cast<LoadSDNode>(Load);

    // Create the byte-swapping load.
    SDValue Ops[] = {
      LD->getChain(),    // Chain
      LD->getBasePtr()   // Ptr
    };
    EVT LoadVT = N->getValueType(0);
    if (LoadVT == MVT::i16)
      LoadVT = MVT::i32;
    SDValue BSLoad =
      DAG.getMemIntrinsicNode(SystemZISD::LRV, SDLoc(N),
                              DAG.getVTList(LoadVT, MVT::Other),
                              Ops, LD->getMemoryVT(), LD->getMemOperand());

    // If this is an i16 load, insert the truncate.
    SDValue ResVal = BSLoad;
    if (N->getValueType(0) == MVT::i16)
      ResVal = DAG.getNode(ISD::TRUNCATE, SDLoc(N), MVT::i16, BSLoad);

    // First, combine the bswap away.  This makes the value produced by the
    // load dead.
    DCI.CombineTo(N, ResVal);

    // Next, combine the load away, we give it a bogus result value but a real
    // chain result.  The result value is dead because the bswap is dead.
    DCI.CombineTo(Load.getNode(), ResVal, BSLoad.getValue(1));

    // Return N so it doesn't get rechecked!
    return SDValue(N, 0);
  }

// Look through bitcasts that retain the number of vector elements.
SDValue Op = N->getOperand(0);
if (Op.getOpcode() == ISD::BITCAST &&
    Op.getValueType().isVector() &&
    Op.getOperand(0).getValueType().isVector() &&
    Op.getValueType().getVectorNumElements() ==
    Op.getOperand(0).getValueType().getVectorNumElements())
  Op = Op.getOperand(0);

// Push BSWAP into a vector insertion if at least one side then simplifies.
if (Op.getOpcode() == ISD::INSERT_VECTOR_ELT && Op.hasOneUse()) {
  SDValue Vec = Op.getOperand(0);
  SDValue Elt = Op.getOperand(1);
  SDValue Idx = Op.getOperand(2);

  if (DAG.isConstantIntBuildVectorOrConstantInt(Vec) ||
      Vec.getOpcode() == ISD::BSWAP || Vec.isUndef() ||
      DAG.isConstantIntBuildVectorOrConstantInt(Elt) ||
      Elt.getOpcode() == ISD::BSWAP || Elt.isUndef() ||
      (canLoadStoreByteSwapped(N->getValueType(0)) &&
       ISD::isNON_EXTLoad(Elt.getNode()) && Elt.hasOneUse())) {
    EVT VecVT = N->getValueType(0);
    EVT EltVT = N->getValueType(0).getVectorElementType();
    if (VecVT != Vec.getValueType()) {
      Vec = DAG.getNode(ISD::BITCAST, SDLoc(N), VecVT, Vec);
      DCI.AddToWorklist(Vec.getNode());
    }
    if (EltVT != Elt.getValueType()) {
      Elt = DAG.getNode(ISD::BITCAST, SDLoc(N), EltVT, Elt);
      DCI.AddToWorklist(Elt.getNode());
    }
    Vec = DAG.getNode(ISD::BSWAP, SDLoc(N), VecVT, Vec);
    DCI.AddToWorklist(Vec.getNode());
    Elt = DAG.getNode(ISD::BSWAP, SDLoc(N), EltVT, Elt);
    DCI.AddToWorklist(Elt.getNode());
    return DAG.getNode(ISD::INSERT_VECTOR_ELT, SDLoc(N), VecVT,
                       Vec, Elt, Idx);
  }
}

// Push BSWAP into a vector shuffle if at least one side then simplifies.
ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(Op);
if (SV && Op.hasOneUse()) {
  SDValue Op0 = Op.getOperand(0);
  SDValue Op1 = Op.getOperand(1);

  if (DAG.isConstantIntBuildVectorOrConstantInt(Op0) ||
      Op0.getOpcode() == ISD::BSWAP || Op0.isUndef() ||
      DAG.isConstantIntBuildVectorOrConstantInt(Op1) ||
      Op1.getOpcode() == ISD::BSWAP || Op1.isUndef()) {
    EVT VecVT = N->getValueType(0);
    if (VecVT != Op0.getValueType()) {
      Op0 = DAG.getNode(ISD::BITCAST, SDLoc(N), VecVT, Op0);
      DCI.AddToWorklist(Op0.getNode());
    }
    if (VecVT != Op1.getValueType()) {
      Op1 = DAG.getNode(ISD::BITCAST, SDLoc(N), VecVT, Op1);
      DCI.AddToWorklist(Op1.getNode());
    }
    Op0 = DAG.getNode(ISD::BSWAP, SDLoc(N), VecVT, Op0);
    DCI.AddToWorklist(Op0.getNode());
    Op1 = DAG.getNode(ISD::BSWAP, SDLoc(N), VecVT, Op1);
    DCI.AddToWorklist(Op1.getNode());
    return DAG.getVectorShuffle(VecVT, SDLoc(N), Op0, Op1, SV->getMask());
  }
}

return SDValue();
6499}

6501static bool combineCCMask(SDValue &CCReg, int &CCValid, int &CCMask) {
// We have a SELECT_CCMASK or BR_CCMASK comparing the condition code
// set by the CCReg instruction using the CCValid / CCMask masks,
// If the CCReg instruction is itself a ICMP testing the condition
// code set by some other instruction, see whether we can directly
// use that condition code.

// Verify that we have an ICMP against some constant.
if (CCValid != SystemZ::CCMASK_ICMP)
  return false;
auto *ICmp = CCReg.getNode();
if (ICmp->getOpcode() != SystemZISD::ICMP)
  return false;
auto *CompareLHS = ICmp->getOperand(0).getNode();
auto *CompareRHS = dyn_cast<ConstantSDNode>(ICmp->getOperand(1));
if (!CompareRHS)
  return false;

// Optimize the case where CompareLHS is a SELECT_CCMASK.
if (CompareLHS->getOpcode() == SystemZISD::SELECT_CCMASK) {
  // Verify that we have an appropriate mask for a EQ or NE comparison.
  bool Invert = false;
  if (CCMask == SystemZ::CCMASK_CMP_NE)
    Invert = !Invert;
  else if (CCMask != SystemZ::CCMASK_CMP_EQ)
    return false;

  // Verify that the ICMP compares against one of select values.
  auto *TrueVal = dyn_cast<ConstantSDNode>(CompareLHS->getOperand(0));
  if (!TrueVal)
    return false;
  auto *FalseVal = dyn_cast<ConstantSDNode>(CompareLHS->getOperand(1));
  if (!FalseVal)
    return false;
  if (CompareRHS->getZExtValue() == FalseVal->getZExtValue())
    Invert = !Invert;
  else if (CompareRHS->getZExtValue() != TrueVal->getZExtValue())
    return false;

  // Compute the effective CC mask for the new branch or select.
  auto *NewCCValid = dyn_cast<ConstantSDNode>(CompareLHS->getOperand(2));
  auto *NewCCMask = dyn_cast<ConstantSDNode>(CompareLHS->getOperand(3));
  if (!NewCCValid || !NewCCMask)
    return false;
  CCValid = NewCCValid->getZExtValue();
  CCMask = NewCCMask->getZExtValue();
  if (Invert)
    CCMask ^= CCValid;

  // Return the updated CCReg link.
  CCReg = CompareLHS->getOperand(4);
  return true;
}

// Optimize the case where CompareRHS is (SRA (SHL (IPM))).
if (CompareLHS->getOpcode() == ISD::SRA) {
  auto *SRACount = dyn_cast<ConstantSDNode>(CompareLHS->getOperand(1));
  if (!SRACount || SRACount->getZExtValue() != 30)
    return false;
  auto *SHL = CompareLHS->getOperand(0).getNode();
  if (SHL->getOpcode() != ISD::SHL)
    return false;
  auto *SHLCount = dyn_cast<ConstantSDNode>(SHL->getOperand(1));
  if (!SHLCount || SHLCount->getZExtValue() != 30 - SystemZ::IPM_CC)
    return false;
  auto *IPM = SHL->getOperand(0).getNode();
  if (IPM->getOpcode() != SystemZISD::IPM)
    return false;

  // Avoid introducing CC spills (because SRA would clobber CC).
  if (!CompareLHS->hasOneUse())
    return false;
  // Verify that the ICMP compares against zero.
  if (CompareRHS->getZExtValue() != 0)
    return false;

  // Compute the effective CC mask for the new branch or select.
  CCMask = SystemZ::reverseCCMask(CCMask);

  // Return the updated CCReg link.
  CCReg = IPM->getOperand(0);
  return true;
}

return false;
6586}

6588SDValue SystemZTargetLowering::combineBR_CCMASK(
  SDNode *N, DAGCombinerInfo &DCI) const {
SelectionDAG &DAG = DCI.DAG;

// Combine BR_CCMASK (ICMP (SELECT_CCMASK)) into a single BR_CCMASK.
auto *CCValid = dyn_cast<ConstantSDNode>(N->getOperand(1));
auto *CCMask = dyn_cast<ConstantSDNode>(N->getOperand(2));
if (!CCValid || !CCMask)
  return SDValue();

int CCValidVal = CCValid->getZExtValue();
int CCMaskVal = CCMask->getZExtValue();
SDValue Chain = N->getOperand(0);
SDValue CCReg = N->getOperand(4);

if (combineCCMask(CCReg, CCValidVal, CCMaskVal))
  return DAG.getNode(SystemZISD::BR_CCMASK, SDLoc(N), N->getValueType(0),
                     Chain,
                     DAG.getTargetConstant(CCValidVal, SDLoc(N), MVT::i32),
                     DAG.getTargetConstant(CCMaskVal, SDLoc(N), MVT::i32),
                     N->getOperand(3), CCReg);
return SDValue();
6610}

6612SDValue SystemZTargetLowering::combineSELECT_CCMASK(
  SDNode *N, DAGCombinerInfo &DCI) const {
SelectionDAG &DAG = DCI.DAG;

// Combine SELECT_CCMASK (ICMP (SELECT_CCMASK)) into a single SELECT_CCMASK.
auto *CCValid = dyn_cast<ConstantSDNode>(N->getOperand(2));
auto *CCMask = dyn_cast<ConstantSDNode>(N->getOperand(3));
if (!CCValid || !CCMask)
  return SDValue();

int CCValidVal = CCValid->getZExtValue();
int CCMaskVal = CCMask->getZExtValue();
SDValue CCReg = N->getOperand(4);

if (combineCCMask(CCReg, CCValidVal, CCMaskVal))
  return DAG.getNode(SystemZISD::SELECT_CCMASK, SDLoc(N), N->getValueType(0),
                     N->getOperand(0), N->getOperand(1),
                     DAG.getTargetConstant(CCValidVal, SDLoc(N), MVT::i32),
                     DAG.getTargetConstant(CCMaskVal, SDLoc(N), MVT::i32),
                     CCReg);
return SDValue();
6633}


6636SDValue SystemZTargetLowering::combineGET_CCMASK(
  SDNode *N, DAGCombinerInfo &DCI) const {

// Optimize away GET_CCMASK (SELECT_CCMASK) if the CC masks are compatible
auto *CCValid = dyn_cast<ConstantSDNode>(N->getOperand(1));
auto *CCMask = dyn_cast<ConstantSDNode>(N->getOperand(2));
if (!CCValid || !CCMask)
  return SDValue();
int CCValidVal = CCValid->getZExtValue();
int CCMaskVal = CCMask->getZExtValue();

SDValue Select = N->getOperand(0);
if (Select->getOpcode() != SystemZISD::SELECT_CCMASK)
  return SDValue();

auto *SelectCCValid = dyn_cast<ConstantSDNode>(Select->getOperand(2));
auto *SelectCCMask = dyn_cast<ConstantSDNode>(Select->getOperand(3));
if (!SelectCCValid || !SelectCCMask)
  return SDValue();
int SelectCCValidVal = SelectCCValid->getZExtValue();
int SelectCCMaskVal = SelectCCMask->getZExtValue();

auto *TrueVal = dyn_cast<ConstantSDNode>(Select->getOperand(0));
auto *FalseVal = dyn_cast<ConstantSDNode>(Select->getOperand(1));
if (!TrueVal || !FalseVal)
  return SDValue();
if (TrueVal->getZExtValue() != 0 && FalseVal->getZExtValue() == 0)
  ;
else if (TrueVal->getZExtValue() == 0 && FalseVal->getZExtValue() != 0)
  SelectCCMaskVal ^= SelectCCValidVal;
else
  return SDValue();

if (SelectCCValidVal & ~CCValidVal)
  return SDValue();
if (SelectCCMaskVal != (CCMaskVal & SelectCCValidVal))
  return SDValue();

return Select->getOperand(4);
6675}

6677SDValue SystemZTargetLowering::combineIntDIVREM(
  SDNode *N, DAGCombinerInfo &DCI) const {
SelectionDAG &DAG = DCI.DAG;
EVT VT = N->getValueType(0);
// In the case where the divisor is a vector of constants a cheaper
// sequence of instructions can replace the divide. BuildSDIV is called to
// do this during DAG combining, but it only succeeds when it can build a
// multiplication node. The only option for SystemZ is ISD::SMUL_LOHI, and
// since it is not Legal but Custom it can only happen before
// legalization. Therefore we must scalarize this early before Combine
// 1. For widened vectors, this is already the result of type legalization.
if (DCI.Level == BeforeLegalizeTypes && VT.isVector() && isTypeLegal(VT) &&
    DAG.isConstantIntBuildVectorOrConstantInt(N->getOperand(1)))
  return DAG.UnrollVectorOp(N);
return SDValue();
6692}

6694SDValue SystemZTargetLowering::combineINTRINSIC(
  SDNode *N, DAGCombinerInfo &DCI) const {
SelectionDAG &DAG = DCI.DAG;

unsigned Id = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
switch (Id) {
// VECTOR LOAD (RIGHTMOST) WITH LENGTH with a length operand of 15
// or larger is simply a vector load.
case Intrinsic::s390_vll:
case Intrinsic::s390_vlrl:
  if (auto *C = dyn_cast<ConstantSDNode>(N->getOperand(2)))
    if (C->getZExtValue() >= 15)
      return DAG.getLoad(N->getValueType(0), SDLoc(N), N->getOperand(0),
                         N->getOperand(3), MachinePointerInfo());
  break;
// Likewise for VECTOR STORE (RIGHTMOST) WITH LENGTH.
case Intrinsic::s390_vstl:
case Intrinsic::s390_vstrl:
  if (auto *C = dyn_cast<ConstantSDNode>(N->getOperand(3)))
    if (C->getZExtValue() >= 15)
      return DAG.getStore(N->getOperand(0), SDLoc(N), N->getOperand(2),
                          N->getOperand(4), MachinePointerInfo());
  break;
}

return SDValue();
6720}

6722SDValue SystemZTargetLowering::unwrapAddress(SDValue N) const {
if (N->getOpcode() == SystemZISD::PCREL_WRAPPER)
  return N->getOperand(0);
return N;
6726}

6728SDValue SystemZTargetLowering::PerformDAGCombine(SDNode *N,
                                               DAGCombinerInfo &DCI) const {
switch(N->getOpcode()) {
default: break;
case ISD::ZERO_EXTEND:        return combineZERO_EXTEND(N, DCI);
case ISD::SIGN_EXTEND:        return combineSIGN_EXTEND(N, DCI);
case ISD::SIGN_EXTEND_INREG:  return combineSIGN_EXTEND_INREG(N, DCI);
case SystemZISD::MERGE_HIGH:
case SystemZISD::MERGE_LOW:   return combineMERGE(N, DCI);
case ISD::LOAD:               return combineLOAD(N, DCI);
case ISD::STORE:              return combineSTORE(N, DCI);
case ISD::VECTOR_SHUFFLE:     return combineVECTOR_SHUFFLE(N, DCI);
case ISD::EXTRACT_VECTOR_ELT: return combineEXTRACT_VECTOR_ELT(N, DCI);
case SystemZISD::JOIN_DWORDS: return combineJOIN_DWORDS(N, DCI);
case ISD::STRICT_FP_ROUND:
case ISD::FP_ROUND:           return combineFP_ROUND(N, DCI);
case ISD::STRICT_FP_EXTEND:
case ISD::FP_EXTEND:          return combineFP_EXTEND(N, DCI);
case ISD::SINT_TO_FP:
case ISD::UINT_TO_FP:         return combineINT_TO_FP(N, DCI);
case ISD::BSWAP:              return combineBSWAP(N, DCI);
case SystemZISD::BR_CCMASK:   return combineBR_CCMASK(N, DCI);
case SystemZISD::SELECT_CCMASK: return combineSELECT_CCMASK(N, DCI);
case SystemZISD::GET_CCMASK:  return combineGET_CCMASK(N, DCI);
case ISD::SDIV:
case ISD::UDIV:
case ISD::SREM:
case ISD::UREM:               return combineIntDIVREM(N, DCI);
case ISD::INTRINSIC_W_CHAIN:
case ISD::INTRINSIC_VOID:     return combineINTRINSIC(N, DCI);
}

return SDValue();
6761}

6763// Return the demanded elements for the OpNo source operand of Op. DemandedElts
6764// are for Op.
6765static APInt getDemandedSrcElements(SDValue Op, const APInt &DemandedElts,
                                  unsigned OpNo) {
EVT VT = Op.getValueType();
unsigned NumElts = (VT.isVector() ? VT.getVectorNumElements() : 1);
APInt SrcDemE;
unsigned Opcode = Op.getOpcode();
if (Opcode == ISD::INTRINSIC_WO_CHAIN) {
  unsigned Id = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
  switch (Id) {
  case Intrinsic::s390_vpksh:   // PACKS
  case Intrinsic::s390_vpksf:
  case Intrinsic::s390_vpksg:
  case Intrinsic::s390_vpkshs:  // PACKS_CC
  case Intrinsic::s390_vpksfs:
  case Intrinsic::s390_vpksgs:
  case Intrinsic::s390_vpklsh:  // PACKLS
  case Intrinsic::s390_vpklsf:
  case Intrinsic::s390_vpklsg:
  case Intrinsic::s390_vpklshs: // PACKLS_CC
  case Intrinsic::s390_vpklsfs:
  case Intrinsic::s390_vpklsgs:
    // VECTOR PACK truncates the elements of two source vectors into one.
    SrcDemE = DemandedElts;
    if (OpNo == 2)
      SrcDemE.lshrInPlace(NumElts / 2);
    SrcDemE = SrcDemE.trunc(NumElts / 2);
    break;
    // VECTOR UNPACK extends half the elements of the source vector.
  case Intrinsic::s390_vuphb:  // VECTOR UNPACK HIGH
  case Intrinsic::s390_vuphh:
  case Intrinsic::s390_vuphf:
  case Intrinsic::s390_vuplhb: // VECTOR UNPACK LOGICAL HIGH
  case Intrinsic::s390_vuplhh:
  case Intrinsic::s390_vuplhf:
    SrcDemE = APInt(NumElts * 2, 0);
    SrcDemE.insertBits(DemandedElts, 0);
    break;
  case Intrinsic::s390_vuplb:  // VECTOR UNPACK LOW
  case Intrinsic::s390_vuplhw:
  case Intrinsic::s390_vuplf:
  case Intrinsic::s390_vupllb: // VECTOR UNPACK LOGICAL LOW
  case Intrinsic::s390_vupllh:
  case Intrinsic::s390_vupllf:
    SrcDemE = APInt(NumElts * 2, 0);
    SrcDemE.insertBits(DemandedElts, NumElts);
    break;
  case Intrinsic::s390_vpdi: {
    // VECTOR PERMUTE DWORD IMMEDIATE selects one element from each source.
    SrcDemE = APInt(NumElts, 0);
    if (!DemandedElts[OpNo - 1])
      break;
    unsigned Mask = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue();
    unsigned MaskBit = ((OpNo - 1) ? 1 : 4);
    // Demand input element 0 or 1, given by the mask bit value.
    SrcDemE.setBit((Mask & MaskBit)? 1 : 0);
    break;
  }
  case Intrinsic::s390_vsldb: {
    // VECTOR SHIFT LEFT DOUBLE BY BYTE
    assert(VT == MVT::v16i8 && "Unexpected type.")(static_cast <bool> (VT == MVT::v16i8 && "Unexpected type."
) ? void (0) : __assert_fail ("VT == MVT::v16i8 && \"Unexpected type.\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp"
, 6824, __extension__ __PRETTY_FUNCTION__));
    unsigned FirstIdx = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue();
    assert (FirstIdx > 0 && FirstIdx < 16 && "Unused operand.")(static_cast <bool> (FirstIdx > 0 && FirstIdx
 < 16 && "Unused operand.") ? void (0) : __assert_fail
 ("FirstIdx > 0 && FirstIdx < 16 && \"Unused operand.\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp"
, 6826, __extension__ __PRETTY_FUNCTION__));
    unsigned NumSrc0Els = 16 - FirstIdx;
    SrcDemE = APInt(NumElts, 0);
    if (OpNo == 1) {
      APInt DemEls = DemandedElts.trunc(NumSrc0Els);
      SrcDemE.insertBits(DemEls, FirstIdx);
    } else {
      APInt DemEls = DemandedElts.lshr(NumSrc0Els);
      SrcDemE.insertBits(DemEls, 0);
    }
    break;
  }
  case Intrinsic::s390_vperm:
    SrcDemE = APInt(NumElts, 1);
    break;
  default:
    llvm_unreachable("Unhandled intrinsic.")::llvm::llvm_unreachable_internal("Unhandled intrinsic.", "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp"
, 6842);
    break;
  }
} else {
  switch (Opcode) {
  case SystemZISD::JOIN_DWORDS:
    // Scalar operand.
    SrcDemE = APInt(1, 1);
    break;
  case SystemZISD::SELECT_CCMASK:
    SrcDemE = DemandedElts;
    break;
  default:
    llvm_unreachable("Unhandled opcode.")::llvm::llvm_unreachable_internal("Unhandled opcode.", "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp"
, 6855);
    break;
  }
}
return SrcDemE;
6860}

6862static void computeKnownBitsBinOp(const SDValue Op, KnownBits &Known,
                                const APInt &DemandedElts,
                                const SelectionDAG &DAG, unsigned Depth,
                                unsigned OpNo) {
APInt Src0DemE = getDemandedSrcElements(Op, DemandedElts, OpNo);
APInt Src1DemE = getDemandedSrcElements(Op, DemandedElts, OpNo + 1);
KnownBits LHSKnown =
    DAG.computeKnownBits(Op.getOperand(OpNo), Src0DemE, Depth + 1);
KnownBits RHSKnown =
    DAG.computeKnownBits(Op.getOperand(OpNo + 1), Src1DemE, Depth + 1);
Known = KnownBits::commonBits(LHSKnown, RHSKnown);
6873}

6875void
6876SystemZTargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
                                                   KnownBits &Known,
                                                   const APInt &DemandedElts,
                                                   const SelectionDAG &DAG,
                                                   unsigned Depth) const {
Known.resetAll();

// Intrinsic CC result is returned in the two low bits.
unsigned tmp0, tmp1; // not used
if (Op.getResNo() == 1 && isIntrinsicWithCC(Op, tmp0, tmp1)) {
  Known.Zero.setBitsFrom(2);
  return;
}
EVT VT = Op.getValueType();
if (Op.getResNo() != 0 || VT == MVT::Untyped)
  return;
assert (Known.getBitWidth() == VT.getScalarSizeInBits() &&(static_cast <bool> (Known.getBitWidth() == VT.getScalarSizeInBits
() && "KnownBits does not match VT in bitwidth") ? void
 (0) : __assert_fail ("Known.getBitWidth() == VT.getScalarSizeInBits() && \"KnownBits does not match VT in bitwidth\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp"
, 6893, __extension__ __PRETTY_FUNCTION__))
        "KnownBits does not match VT in bitwidth")(static_cast <bool> (Known.getBitWidth() == VT.getScalarSizeInBits
() && "KnownBits does not match VT in bitwidth") ? void
 (0) : __assert_fail ("Known.getBitWidth() == VT.getScalarSizeInBits() && \"KnownBits does not match VT in bitwidth\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp"
, 6893, __extension__ __PRETTY_FUNCTION__));
assert ((!VT.isVector() ||(static_cast <bool> ((!VT.isVector() || (DemandedElts.getBitWidth
() == VT.getVectorNumElements())) && "DemandedElts does not match VT number of elements"
) ? void (0) : __assert_fail ("(!VT.isVector() || (DemandedElts.getBitWidth() == VT.getVectorNumElements())) && \"DemandedElts does not match VT number of elements\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp"
, 6896, __extension__ __PRETTY_FUNCTION__))
         (DemandedElts.getBitWidth() == VT.getVectorNumElements())) &&(static_cast <bool> ((!VT.isVector() || (DemandedElts.getBitWidth
() == VT.getVectorNumElements())) && "DemandedElts does not match VT number of elements"
) ? void (0) : __assert_fail ("(!VT.isVector() || (DemandedElts.getBitWidth() == VT.getVectorNumElements())) && \"DemandedElts does not match VT number of elements\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp"
, 6896, __extension__ __PRETTY_FUNCTION__))
        "DemandedElts does not match VT number of elements")(static_cast <bool> ((!VT.isVector() || (DemandedElts.getBitWidth
() == VT.getVectorNumElements())) && "DemandedElts does not match VT number of elements"
) ? void (0) : __assert_fail ("(!VT.isVector() || (DemandedElts.getBitWidth() == VT.getVectorNumElements())) && \"DemandedElts does not match VT number of elements\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp"
, 6896, __extension__ __PRETTY_FUNCTION__));
unsigned BitWidth = Known.getBitWidth();
unsigned Opcode = Op.getOpcode();
if (Opcode == ISD::INTRINSIC_WO_CHAIN) {
  bool IsLogical = false;
  unsigned Id = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
  switch (Id) {
  case Intrinsic::s390_vpksh:   // PACKS
  case Intrinsic::s390_vpksf:
  case Intrinsic::s390_vpksg:
  case Intrinsic::s390_vpkshs:  // PACKS_CC
  case Intrinsic::s390_vpksfs:
  case Intrinsic::s390_vpksgs:
  case Intrinsic::s390_vpklsh:  // PACKLS
  case Intrinsic::s390_vpklsf:
  case Intrinsic::s390_vpklsg:
  case Intrinsic::s390_vpklshs: // PACKLS_CC
  case Intrinsic::s390_vpklsfs:
  case Intrinsic::s390_vpklsgs:
  case Intrinsic::s390_vpdi:
  case Intrinsic::s390_vsldb:
  case Intrinsic::s390_vperm:
    computeKnownBitsBinOp(Op, Known, DemandedElts, DAG, Depth, 1);
    break;
  case Intrinsic::s390_vuplhb: // VECTOR UNPACK LOGICAL HIGH
  case Intrinsic::s390_vuplhh:
  case Intrinsic::s390_vuplhf:
  case Intrinsic::s390_vupllb: // VECTOR UNPACK LOGICAL LOW
  case Intrinsic::s390_vupllh:
  case Intrinsic::s390_vupllf:
    IsLogical = true;
    LLVM_FALLTHROUGH[[gnu::fallthrough]];
  case Intrinsic::s390_vuphb:  // VECTOR UNPACK HIGH
  case Intrinsic::s390_vuphh:
  case Intrinsic::s390_vuphf:
  case Intrinsic::s390_vuplb:  // VECTOR UNPACK LOW
  case Intrinsic::s390_vuplhw:
  case Intrinsic::s390_vuplf: {
    SDValue SrcOp = Op.getOperand(1);
    APInt SrcDemE = getDemandedSrcElements(Op, DemandedElts, 0);
    Known = DAG.computeKnownBits(SrcOp, SrcDemE, Depth + 1);
    if (IsLogical) {
      Known = Known.zext(BitWidth);
    } else
      Known = Known.sext(BitWidth);
    break;
  }
  default:
    break;
  }
} else {
  switch (Opcode) {
  case SystemZISD::JOIN_DWORDS:
  case SystemZISD::SELECT_CCMASK:
    computeKnownBitsBinOp(Op, Known, DemandedElts, DAG, Depth, 0);
    break;
  case SystemZISD::REPLICATE: {
    SDValue SrcOp = Op.getOperand(0);
    Known = DAG.computeKnownBits(SrcOp, Depth + 1);
    if (Known.getBitWidth() < BitWidth && isa<ConstantSDNode>(SrcOp))
      Known = Known.sext(BitWidth); // VREPI sign extends the immedate.
    break;
  }
  default:
    break;
  }
}

// Known has the width of the source operand(s). Adjust if needed to match
// the passed bitwidth.
if (Known.getBitWidth() != BitWidth)
  Known = Known.anyextOrTrunc(BitWidth);
6968}

6970static unsigned computeNumSignBitsBinOp(SDValue Op, const APInt &DemandedElts,
                                      const SelectionDAG &DAG, unsigned Depth,
                                      unsigned OpNo) {
APInt Src0DemE = getDemandedSrcElements(Op, DemandedElts, OpNo);
unsigned LHS = DAG.ComputeNumSignBits(Op.getOperand(OpNo), Src0DemE, Depth + 1);
if (LHS == 1) return 1; // Early out.
APInt Src1DemE = getDemandedSrcElements(Op, DemandedElts, OpNo + 1);
unsigned RHS = DAG.ComputeNumSignBits(Op.getOperand(OpNo + 1), Src1DemE, Depth + 1);
if (RHS == 1) return 1; // Early out.
unsigned Common = std::min(LHS, RHS);
unsigned SrcBitWidth = Op.getOperand(OpNo).getScalarValueSizeInBits();
EVT VT = Op.getValueType();
unsigned VTBits = VT.getScalarSizeInBits();
if (SrcBitWidth > VTBits) { // PACK
  unsigned SrcExtraBits = SrcBitWidth - VTBits;
  if (Common > SrcExtraBits)
    return (Common - SrcExtraBits);
  return 1;
}
assert (SrcBitWidth == VTBits && "Expected operands of same bitwidth.")(static_cast <bool> (SrcBitWidth == VTBits && "Expected operands of same bitwidth."
) ? void (0) : __assert_fail ("SrcBitWidth == VTBits && \"Expected operands of same bitwidth.\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp"
, 6989, __extension__ __PRETTY_FUNCTION__));
return Common;
6991}

6993unsigned
6994SystemZTargetLowering::ComputeNumSignBitsForTargetNode(
  SDValue Op, const APInt &DemandedElts, const SelectionDAG &DAG,
  unsigned Depth) const {
if (Op.getResNo() != 0)
  return 1;
unsigned Opcode = Op.getOpcode();
if (Opcode == ISD::INTRINSIC_WO_CHAIN) {
  unsigned Id = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
  switch (Id) {
  case Intrinsic::s390_vpksh:   // PACKS
  case Intrinsic::s390_vpksf:
  case Intrinsic::s390_vpksg:
  case Intrinsic::s390_vpkshs:  // PACKS_CC
  case Intrinsic::s390_vpksfs:
  case Intrinsic::s390_vpksgs:
  case Intrinsic::s390_vpklsh:  // PACKLS
  case Intrinsic::s390_vpklsf:
  case Intrinsic::s390_vpklsg:
  case Intrinsic::s390_vpklshs: // PACKLS_CC
  case Intrinsic::s390_vpklsfs:
  case Intrinsic::s390_vpklsgs:
  case Intrinsic::s390_vpdi:
  case Intrinsic::s390_vsldb:
  case Intrinsic::s390_vperm:
    return computeNumSignBitsBinOp(Op, DemandedElts, DAG, Depth, 1);
  case Intrinsic::s390_vuphb:  // VECTOR UNPACK HIGH
  case Intrinsic::s390_vuphh:
  case Intrinsic::s390_vuphf:
  case Intrinsic::s390_vuplb:  // VECTOR UNPACK LOW
  case Intrinsic::s390_vuplhw:
  case Intrinsic::s390_vuplf: {
    SDValue PackedOp = Op.getOperand(1);
    APInt SrcDemE = getDemandedSrcElements(Op, DemandedElts, 1);
    unsigned Tmp = DAG.ComputeNumSignBits(PackedOp, SrcDemE, Depth + 1);
    EVT VT = Op.getValueType();
    unsigned VTBits = VT.getScalarSizeInBits();
    Tmp += VTBits - PackedOp.getScalarValueSizeInBits();
    return Tmp;
  }
  default:
    break;
  }
} else {
  switch (Opcode) {
  case SystemZISD::SELECT_CCMASK:
    return computeNumSignBitsBinOp(Op, DemandedElts, DAG, Depth, 0);
  default:
    break;
  }
}

return 1;
7046}

7048unsigned
7049SystemZTargetLowering::getStackProbeSize(MachineFunction &MF) const {
const TargetFrameLowering *TFI = Subtarget.getFrameLowering();
unsigned StackAlign = TFI->getStackAlignment();
assert(StackAlign >=1 && isPowerOf2_32(StackAlign) &&(static_cast <bool> (StackAlign >=1 && isPowerOf2_32
(StackAlign) && "Unexpected stack alignment") ? void (
0) : __assert_fail ("StackAlign >=1 && isPowerOf2_32(StackAlign) && \"Unexpected stack alignment\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp"
, 7053, __extension__ __PRETTY_FUNCTION__))
       "Unexpected stack alignment")(static_cast <bool> (StackAlign >=1 && isPowerOf2_32
(StackAlign) && "Unexpected stack alignment") ? void (
0) : __assert_fail ("StackAlign >=1 && isPowerOf2_32(StackAlign) && \"Unexpected stack alignment\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp"
, 7053, __extension__ __PRETTY_FUNCTION__));
// The default stack probe size is 4096 if the function has no
// stack-probe-size attribute.
unsigned StackProbeSize = 4096;
const Function &Fn = MF.getFunction();
if (Fn.hasFnAttribute("stack-probe-size"))
  Fn.getFnAttribute("stack-probe-size")
      .getValueAsString()
      .getAsInteger(0, StackProbeSize);
// Round down to the stack alignment.
StackProbeSize &= ~(StackAlign - 1);
return StackProbeSize ? StackProbeSize : StackAlign;
7065}

7067//===----------------------------------------------------------------------===//
7068// Custom insertion
7069//===----------------------------------------------------------------------===//

7071// Force base value Base into a register before MI.  Return the register.
7072static Register forceReg(MachineInstr &MI, MachineOperand &Base,
                       const SystemZInstrInfo *TII) {
if (Base.isReg())
  return Base.getReg();

MachineBasicBlock *MBB = MI.getParent();
MachineFunction &MF = *MBB->getParent();
MachineRegisterInfo &MRI = MF.getRegInfo();

Register Reg = MRI.createVirtualRegister(&SystemZ::ADDR64BitRegClass);
BuildMI(*MBB, MI, MI.getDebugLoc(), TII->get(SystemZ::LA), Reg)
    .add(Base)
    .addImm(0)
    .addReg(0);
return Reg;
7087}

7089// The CC operand of MI might be missing a kill marker because there
7090// were multiple uses of CC, and ISel didn't know which to mark.
7091// Figure out whether MI should have had a kill marker.
7092static bool checkCCKill(MachineInstr &MI, MachineBasicBlock *MBB) {
// Scan forward through BB for a use/def of CC.
MachineBasicBlock::iterator miI(std::next(MachineBasicBlock::iterator(MI)));
for (MachineBasicBlock::iterator miE = MBB->end(); miI != miE; ++miI) {
  const MachineInstr& mi = *miI;
  if (mi.readsRegister(SystemZ::CC))
    return false;
  if (mi.definesRegister(SystemZ::CC))
    break; // Should have kill-flag - update below.
}

// If we hit the end of the block, check whether CC is live into a
// successor.
if (miI == MBB->end()) {
  for (auto SI = MBB->succ_begin(), SE = MBB->succ_end(); SI != SE; ++SI)
    if ((*SI)->isLiveIn(SystemZ::CC))
      return false;
}

return true;
7112}

7114// Return true if it is OK for this Select pseudo-opcode to be cascaded
7115// together with other Select pseudo-opcodes into a single basic-block with
7116// a conditional jump around it.
7117static bool isSelectPseudo(MachineInstr &MI) {
switch (MI.getOpcode()) {
case SystemZ::Select32:
case SystemZ::Select64:
case SystemZ::SelectF32:
case SystemZ::SelectF64:
case SystemZ::SelectF128:
case SystemZ::SelectVR32:
case SystemZ::SelectVR64:
case SystemZ::SelectVR128:
  return true;

default:
  return false;
}
7132}

7134// Helper function, which inserts PHI functions into SinkMBB:
7135//   %Result(i) = phi [ %FalseValue(i), FalseMBB ], [ %TrueValue(i), TrueMBB ],
7136// where %FalseValue(i) and %TrueValue(i) are taken from Selects.
7137static void createPHIsForSelects(SmallVector<MachineInstr*, 8> &Selects,
                               MachineBasicBlock *TrueMBB,
                               MachineBasicBlock *FalseMBB,
                               MachineBasicBlock *SinkMBB) {
MachineFunction *MF = TrueMBB->getParent();
const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();

MachineInstr *FirstMI = Selects.front();
unsigned CCValid = FirstMI->getOperand(3).getImm();
unsigned CCMask = FirstMI->getOperand(4).getImm();

MachineBasicBlock::iterator SinkInsertionPoint = SinkMBB->begin();

// As we are creating the PHIs, we have to be careful if there is more than
// one.  Later Selects may reference the results of earlier Selects, but later
// PHIs have to reference the individual true/false inputs from earlier PHIs.
// That also means that PHI construction must work forward from earlier to
// later, and that the code must maintain a mapping from earlier PHI's
// destination registers, and the registers that went into the PHI.
DenseMap<unsigned, std::pair<unsigned, unsigned>> RegRewriteTable;

for (auto MI : Selects) {
  Register DestReg = MI->getOperand(0).getReg();
  Register TrueReg = MI->getOperand(1).getReg();
  Register FalseReg = MI->getOperand(2).getReg();

  // If this Select we are generating is the opposite condition from
  // the jump we generated, then we have to swap the operands for the
  // PHI that is going to be generated.
  if (MI->getOperand(4).getImm() == (CCValid ^ CCMask))
    std::swap(TrueReg, FalseReg);

  if (RegRewriteTable.find(TrueReg) != RegRewriteTable.end())
    TrueReg = RegRewriteTable[TrueReg].first;

  if (RegRewriteTable.find(FalseReg) != RegRewriteTable.end())
    FalseReg = RegRewriteTable[FalseReg].second;

  DebugLoc DL = MI->getDebugLoc();
  BuildMI(*SinkMBB, SinkInsertionPoint, DL, TII->get(SystemZ::PHI), DestReg)
    .addReg(TrueReg).addMBB(TrueMBB)
    .addReg(FalseReg).addMBB(FalseMBB);

  // Add this PHI to the rewrite table.
  RegRewriteTable[DestReg] = std::make_pair(TrueReg, FalseReg);
}

MF->getProperties().reset(MachineFunctionProperties::Property::NoPHIs);
7185}

7187// Implement EmitInstrWithCustomInserter for pseudo Select* instruction MI.
7188MachineBasicBlock *
7189SystemZTargetLowering::emitSelect(MachineInstr &MI,
                                MachineBasicBlock *MBB) const {
assert(isSelectPseudo(MI) && "Bad call to emitSelect()")(static_cast <bool> (isSelectPseudo(MI) && "Bad call to emitSelect()"
) ? void (0) : __assert_fail ("isSelectPseudo(MI) && \"Bad call to emitSelect()\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp"
, 7191, __extension__ __PRETTY_FUNCTION__));
const SystemZInstrInfo *TII =
    static_cast<const SystemZInstrInfo *>(Subtarget.getInstrInfo());

unsigned CCValid = MI.getOperand(3).getImm();
unsigned CCMask = MI.getOperand(4).getImm();

// If we have a sequence of Select* pseudo instructions using the
// same condition code value, we want to expand all of them into
// a single pair of basic blocks using the same condition.
SmallVector<MachineInstr*, 8> Selects;
SmallVector<MachineInstr*, 8> DbgValues;
Selects.push_back(&MI);
unsigned Count = 0;
for (MachineBasicBlock::iterator NextMIIt =
       std::next(MachineBasicBlock::iterator(MI));
     NextMIIt != MBB->end(); ++NextMIIt) {
  if (isSelectPseudo(*NextMIIt)) {
    assert(NextMIIt->getOperand(3).getImm() == CCValid &&(static_cast <bool> (NextMIIt->getOperand(3).getImm(
) == CCValid && "Bad CCValid operands since CC was not redefined."
) ? void (0) : __assert_fail ("NextMIIt->getOperand(3).getImm() == CCValid && \"Bad CCValid operands since CC was not redefined.\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp"
, 7210, __extension__ __PRETTY_FUNCTION__))
           "Bad CCValid operands since CC was not redefined.")(static_cast <bool> (NextMIIt->getOperand(3).getImm(
) == CCValid && "Bad CCValid operands since CC was not redefined."
) ? void (0) : __assert_fail ("NextMIIt->getOperand(3).getImm() == CCValid && \"Bad CCValid operands since CC was not redefined.\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp"
, 7210, __extension__ __PRETTY_FUNCTION__));
    if (NextMIIt->getOperand(4).getImm() == CCMask ||
        NextMIIt->getOperand(4).getImm() == (CCValid ^ CCMask)) {
      Selects.push_back(&*NextMIIt);
      continue;
    }
    break;
  }
  if (NextMIIt->definesRegister(SystemZ::CC) ||
      NextMIIt->usesCustomInsertionHook())
    break;
  bool User = false;
  for (auto SelMI : Selects)
    if (NextMIIt->readsVirtualRegister(SelMI->getOperand(0).getReg())) {
      User = true;
      break;
    }
  if (NextMIIt->isDebugInstr()) {
    if (User) {
      assert(NextMIIt->isDebugValue() && "Unhandled debug opcode.")(static_cast <bool> (NextMIIt->isDebugValue() &&
 "Unhandled debug opcode.") ? void (0) : __assert_fail ("NextMIIt->isDebugValue() && \"Unhandled debug opcode.\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp"
, 7229, __extension__ __PRETTY_FUNCTION__));
      DbgValues.push_back(&*NextMIIt);
    }
  }
  else if (User || ++Count > 20)
    break;
}

MachineInstr *LastMI = Selects.back();
bool CCKilled =
    (LastMI->killsRegister(SystemZ::CC) || checkCCKill(*LastMI, MBB));
MachineBasicBlock *StartMBB = MBB;
MachineBasicBlock *JoinMBB  = SystemZ::splitBlockAfter(LastMI, MBB);
MachineBasicBlock *FalseMBB = SystemZ::emitBlockAfter(StartMBB);

// Unless CC was killed in the last Select instruction, mark it as
// live-in to both FalseMBB and JoinMBB.
if (!CCKilled) {
  FalseMBB->addLiveIn(SystemZ::CC);
  JoinMBB->addLiveIn(SystemZ::CC);
}

//  StartMBB:
//   BRC CCMask, JoinMBB
//   # fallthrough to FalseMBB
MBB = StartMBB;
BuildMI(MBB, MI.getDebugLoc(), TII->get(SystemZ::BRC))
  .addImm(CCValid).addImm(CCMask).addMBB(JoinMBB);
MBB->addSuccessor(JoinMBB);
MBB->addSuccessor(FalseMBB);

//  FalseMBB:
//   # fallthrough to JoinMBB
MBB = FalseMBB;
MBB->addSuccessor(JoinMBB);

//  JoinMBB:
//   %Result = phi [ %FalseReg, FalseMBB ], [ %TrueReg, StartMBB ]
//  ...
MBB = JoinMBB;
createPHIsForSelects(Selects, StartMBB, FalseMBB, MBB);
for (auto SelMI : Selects)
  SelMI->eraseFromParent();

MachineBasicBlock::iterator InsertPos = MBB->getFirstNonPHI();
for (auto DbgMI : DbgValues)
  MBB->splice(InsertPos, StartMBB, DbgMI);

return JoinMBB;
7278}

7280// Implement EmitInstrWithCustomInserter for pseudo CondStore* instruction MI.
7281// StoreOpcode is the store to use and Invert says whether the store should
7282// happen when the condition is false rather than true.  If a STORE ON
7283// CONDITION is available, STOCOpcode is its opcode, otherwise it is 0.
7284MachineBasicBlock *SystemZTargetLowering::emitCondStore(MachineInstr &MI,
                                                      MachineBasicBlock *MBB,
                                                      unsigned StoreOpcode,
                                                      unsigned STOCOpcode,
                                                      bool Invert) const {
const SystemZInstrInfo *TII =
    static_cast<const SystemZInstrInfo *>(Subtarget.getInstrInfo());

Register SrcReg = MI.getOperand(0).getReg();
MachineOperand Base = MI.getOperand(1);
int64_t Disp = MI.getOperand(2).getImm();
Register IndexReg = MI.getOperand(3).getReg();
unsigned CCValid = MI.getOperand(4).getImm();
unsigned CCMask = MI.getOperand(5).getImm();
DebugLoc DL = MI.getDebugLoc();

StoreOpcode = TII->getOpcodeForOffset(StoreOpcode, Disp);

// ISel pattern matching also adds a load memory operand of the same
// address, so take special care to find the storing memory operand.
MachineMemOperand *MMO = nullptr;
for (auto *I : MI.memoperands())
  if (I->isStore()) {
    MMO = I;
    break;
  }

// Use STOCOpcode if possible.  We could use different store patterns in
// order to avoid matching the index register, but the performance trade-offs
// might be more complicated in that case.
if (STOCOpcode && !IndexReg && Subtarget.hasLoadStoreOnCond()) {
  if (Invert)
    CCMask ^= CCValid;

  BuildMI(*MBB, MI, DL, TII->get(STOCOpcode))
    .addReg(SrcReg)
    .add(Base)
    .addImm(Disp)
    .addImm(CCValid)
    .addImm(CCMask)
    .addMemOperand(MMO);

  MI.eraseFromParent();
  return MBB;
}

// Get the condition needed to branch around the store.
if (!Invert)
  CCMask ^= CCValid;

MachineBasicBlock *StartMBB = MBB;
MachineBasicBlock *JoinMBB  = SystemZ::splitBlockBefore(MI, MBB);
MachineBasicBlock *FalseMBB = SystemZ::emitBlockAfter(StartMBB);

// Unless CC was killed in the CondStore instruction, mark it as
// live-in to both FalseMBB and JoinMBB.
if (!MI.killsRegister(SystemZ::CC) && !checkCCKill(MI, JoinMBB)) {
  FalseMBB->addLiveIn(SystemZ::CC);
  JoinMBB->addLiveIn(SystemZ::CC);
}

//  StartMBB:
//   BRC CCMask, JoinMBB
//   # fallthrough to FalseMBB
MBB = StartMBB;
BuildMI(MBB, DL, TII->get(SystemZ::BRC))
  .addImm(CCValid).addImm(CCMask).addMBB(JoinMBB);
MBB->addSuccessor(JoinMBB);
MBB->addSuccessor(FalseMBB);

//  FalseMBB:
//   store %SrcReg, %Disp(%Index,%Base)
//   # fallthrough to JoinMBB
MBB = FalseMBB;
BuildMI(MBB, DL, TII->get(StoreOpcode))
    .addReg(SrcReg)
    .add(Base)
    .addImm(Disp)
    .addReg(IndexReg)
    .addMemOperand(MMO);
MBB->addSuccessor(JoinMBB);

MI.eraseFromParent();
return JoinMBB;
7368}

7370// Implement EmitInstrWithCustomInserter for pseudo ATOMIC_LOAD{,W}_*
7371// or ATOMIC_SWAP{,W} instruction MI.  BinOpcode is the instruction that
7372// performs the binary operation elided by "*", or 0 for ATOMIC_SWAP{,W}.
7373// BitSize is the width of the field in bits, or 0 if this is a partword
7374// ATOMIC_LOADW_* or ATOMIC_SWAPW instruction, in which case the bitsize
7375// is one of the operands.  Invert says whether the field should be
7376// inverted after performing BinOpcode (e.g. for NAND).
7377MachineBasicBlock *SystemZTargetLowering::emitAtomicLoadBinary(
  MachineInstr &MI, MachineBasicBlock *MBB, unsigned BinOpcode,
  unsigned BitSize, bool Invert) const {
MachineFunction &MF = *MBB->getParent();
const SystemZInstrInfo *TII =
    static_cast<const SystemZInstrInfo *>(Subtarget.getInstrInfo());
MachineRegisterInfo &MRI = MF.getRegInfo();
bool IsSubWord = (BitSize < 32);

// Extract the operands.  Base can be a register or a frame index.
// Src2 can be a register or immediate.
Register Dest = MI.getOperand(0).getReg();
MachineOperand Base = earlyUseOperand(MI.getOperand(1));
int64_t Disp = MI.getOperand(2).getImm();
MachineOperand Src2 = earlyUseOperand(MI.getOperand(3));
Register BitShift = IsSubWord ? MI.getOperand(4).getReg() : Register();
Register NegBitShift = IsSubWord ? MI.getOperand(5).getReg() : Register();
DebugLoc DL = MI.getDebugLoc();
if (IsSubWord)
  BitSize = MI.getOperand(6).getImm();

// Subword operations use 32-bit registers.
const TargetRegisterClass *RC = (BitSize <= 32 ?
                                 &SystemZ::GR32BitRegClass :
                                 &SystemZ::GR64BitRegClass);
unsigned LOpcode  = BitSize <= 32 ? SystemZ::L  : SystemZ::LG;
unsigned CSOpcode = BitSize <= 32 ? SystemZ::CS : SystemZ::CSG;

// Get the right opcodes for the displacement.
LOpcode  = TII->getOpcodeForOffset(LOpcode,  Disp);
CSOpcode = TII->getOpcodeForOffset(CSOpcode, Disp);
assert(LOpcode && CSOpcode && "Displacement out of range")(static_cast <bool> (LOpcode && CSOpcode &&
 "Displacement out of range") ? void (0) : __assert_fail ("LOpcode && CSOpcode && \"Displacement out of range\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp"
, 7408, __extension__ __PRETTY_FUNCTION__));

// Create virtual registers for temporary results.
Register OrigVal       = MRI.createVirtualRegister(RC);
Register OldVal        = MRI.createVirtualRegister(RC);
Register NewVal        = (BinOpcode || IsSubWord ?
                          MRI.createVirtualRegister(RC) : Src2.getReg());
Register RotatedOldVal = (IsSubWord ? MRI.createVirtualRegister(RC) : OldVal);
Register RotatedNewVal = (IsSubWord ? MRI.createVirtualRegister(RC) : NewVal);

// Insert a basic block for the main loop.
MachineBasicBlock *StartMBB = MBB;
MachineBasicBlock *DoneMBB  = SystemZ::splitBlockBefore(MI, MBB);
MachineBasicBlock *LoopMBB  = SystemZ::emitBlockAfter(StartMBB);

//  StartMBB:
//   ...
//   %OrigVal = L Disp(%Base)
//   # fall through to LoopMBB
MBB = StartMBB;
BuildMI(MBB, DL, TII->get(LOpcode), OrigVal).add(Base).addImm(Disp).addReg(0);
MBB->addSuccessor(LoopMBB);

//  LoopMBB:
//   %OldVal        = phi [ %OrigVal, StartMBB ], [ %Dest, LoopMBB ]
//   %RotatedOldVal = RLL %OldVal, 0(%BitShift)
//   %RotatedNewVal = OP %RotatedOldVal, %Src2
//   %NewVal        = RLL %RotatedNewVal, 0(%NegBitShift)
//   %Dest          = CS %OldVal, %NewVal, Disp(%Base)
//   JNE LoopMBB
//   # fall through to DoneMBB
MBB = LoopMBB;
BuildMI(MBB, DL, TII->get(SystemZ::PHI), OldVal)
  .addReg(OrigVal).addMBB(StartMBB)
  .addReg(Dest).addMBB(LoopMBB);
if (IsSubWord)
  BuildMI(MBB, DL, TII->get(SystemZ::RLL), RotatedOldVal)
    .addReg(OldVal).addReg(BitShift).addImm(0);
if (Invert) {
  // Perform the operation normally and then invert every bit of the field.
  Register Tmp = MRI.createVirtualRegister(RC);
  BuildMI(MBB, DL, TII->get(BinOpcode), Tmp).addReg(RotatedOldVal).add(Src2);
  if (BitSize <= 32)
    // XILF with the upper BitSize bits set.
    BuildMI(MBB, DL, TII->get(SystemZ::XILF), RotatedNewVal)
      .addReg(Tmp).addImm(-1U << (32 - BitSize));
  else {
    // Use LCGR and add -1 to the result, which is more compact than
    // an XILF, XILH pair.
    Register Tmp2 = MRI.createVirtualRegister(RC);
    BuildMI(MBB, DL, TII->get(SystemZ::LCGR), Tmp2).addReg(Tmp);
    BuildMI(MBB, DL, TII->get(SystemZ::AGHI), RotatedNewVal)
      .addReg(Tmp2).addImm(-1);
  }
} else if (BinOpcode)
  // A simply binary operation.
  BuildMI(MBB, DL, TII->get(BinOpcode), RotatedNewVal)
      .addReg(RotatedOldVal)
      .add(Src2);
else if (IsSubWord)
  // Use RISBG to rotate Src2 into position and use it to replace the
  // field in RotatedOldVal.
  BuildMI(MBB, DL, TII->get(SystemZ::RISBG32), RotatedNewVal)
    .addReg(RotatedOldVal).addReg(Src2.getReg())
    .addImm(32).addImm(31 + BitSize).addImm(32 - BitSize);
if (IsSubWord)
  BuildMI(MBB, DL, TII->get(SystemZ::RLL), NewVal)
    .addReg(RotatedNewVal).addReg(NegBitShift).addImm(0);
BuildMI(MBB, DL, TII->get(CSOpcode), Dest)
    .addReg(OldVal)
    .addReg(NewVal)
    .add(Base)
    .addImm(Disp);
BuildMI(MBB, DL, TII->get(SystemZ::BRC))
  .addImm(SystemZ::CCMASK_CS).addImm(SystemZ::CCMASK_CS_NE).addMBB(LoopMBB);
MBB->addSuccessor(LoopMBB);
MBB->addSuccessor(DoneMBB);

MI.eraseFromParent();
return DoneMBB;
7488}

7490// Implement EmitInstrWithCustomInserter for pseudo
7491// ATOMIC_LOAD{,W}_{,U}{MIN,MAX} instruction MI.  CompareOpcode is the
7492// instruction that should be used to compare the current field with the
7493// minimum or maximum value.  KeepOldMask is the BRC condition-code mask
7494// for when the current field should be kept.  BitSize is the width of
7495// the field in bits, or 0 if this is a partword ATOMIC_LOADW_* instruction.
7496MachineBasicBlock *SystemZTargetLowering::emitAtomicLoadMinMax(
  MachineInstr &MI, MachineBasicBlock *MBB, unsigned CompareOpcode,
  unsigned KeepOldMask, unsigned BitSize) const {
MachineFunction &MF = *MBB->getParent();
const SystemZInstrInfo *TII =
    static_cast<const SystemZInstrInfo *>(Subtarget.getInstrInfo());
MachineRegisterInfo &MRI = MF.getRegInfo();
bool IsSubWord = (BitSize < 32);

// Extract the operands.  Base can be a register or a frame index.
Register Dest = MI.getOperand(0).getReg();
MachineOperand Base = earlyUseOperand(MI.getOperand(1));
int64_t Disp = MI.getOperand(2).getImm();
Register Src2 = MI.getOperand(3).getReg();
Register BitShift = (IsSubWord ? MI.getOperand(4).getReg() : Register());
Register NegBitShift = (IsSubWord ? MI.getOperand(5).getReg() : Register());
DebugLoc DL = MI.getDebugLoc();
if (IsSubWord)
  BitSize = MI.getOperand(6).getImm();

// Subword operations use 32-bit registers.
const TargetRegisterClass *RC = (BitSize <= 32 ?
                                 &SystemZ::GR32BitRegClass :
                                 &SystemZ::GR64BitRegClass);
unsigned LOpcode  = BitSize <= 32 ? SystemZ::L  : SystemZ::LG;
unsigned CSOpcode = BitSize <= 32 ? SystemZ::CS : SystemZ::CSG;

// Get the right opcodes for the displacement.
LOpcode  = TII->getOpcodeForOffset(LOpcode,  Disp);
CSOpcode = TII->getOpcodeForOffset(CSOpcode, Disp);
assert(LOpcode && CSOpcode && "Displacement out of range")(static_cast <bool> (LOpcode && CSOpcode &&
 "Displacement out of range") ? void (0) : __assert_fail ("LOpcode && CSOpcode && \"Displacement out of range\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp"
, 7526, __extension__ __PRETTY_FUNCTION__));

// Create virtual registers for temporary results.
Register OrigVal       = MRI.createVirtualRegister(RC);
Register OldVal        = MRI.createVirtualRegister(RC);
Register NewVal        = MRI.createVirtualRegister(RC);
Register RotatedOldVal = (IsSubWord ? MRI.createVirtualRegister(RC) : OldVal);
Register RotatedAltVal = (IsSubWord ? MRI.createVirtualRegister(RC) : Src2);
Register RotatedNewVal = (IsSubWord ? MRI.createVirtualRegister(RC) : NewVal);

// Insert 3 basic blocks for the loop.
MachineBasicBlock *StartMBB  = MBB;
MachineBasicBlock *DoneMBB   = SystemZ::splitBlockBefore(MI, MBB);
MachineBasicBlock *LoopMBB   = SystemZ::emitBlockAfter(StartMBB);
MachineBasicBlock *UseAltMBB = SystemZ::emitBlockAfter(LoopMBB);
MachineBasicBlock *UpdateMBB = SystemZ::emitBlockAfter(UseAltMBB);

//  StartMBB:
//   ...
//   %OrigVal     = L Disp(%Base)
//   # fall through to LoopMBB
MBB = StartMBB;
BuildMI(MBB, DL, TII->get(LOpcode), OrigVal).add(Base).addImm(Disp).addReg(0);
MBB->addSuccessor(LoopMBB);

//  LoopMBB:
//   %OldVal        = phi [ %OrigVal, StartMBB ], [ %Dest, UpdateMBB ]
//   %RotatedOldVal = RLL %OldVal, 0(%BitShift)
//   CompareOpcode %RotatedOldVal, %Src2
//   BRC KeepOldMask, UpdateMBB
MBB = LoopMBB;
BuildMI(MBB, DL, TII->get(SystemZ::PHI), OldVal)
  .addReg(OrigVal).addMBB(StartMBB)
  .addReg(Dest).addMBB(UpdateMBB);
if (IsSubWord)
  BuildMI(MBB, DL, TII->get(SystemZ::RLL), RotatedOldVal)
    .addReg(OldVal).addReg(BitShift).addImm(0);
BuildMI(MBB, DL, TII->get(CompareOpcode))
  .addReg(RotatedOldVal).addReg(Src2);
BuildMI(MBB, DL, TII->get(SystemZ::BRC))
  .addImm(SystemZ::CCMASK_ICMP).addImm(KeepOldMask).addMBB(UpdateMBB);
MBB->addSuccessor(UpdateMBB);
MBB->addSuccessor(UseAltMBB);

//  UseAltMBB:
//   %RotatedAltVal = RISBG %RotatedOldVal, %Src2, 32, 31 + BitSize, 0
//   # fall through to UpdateMBB
MBB = UseAltMBB;
if (IsSubWord)
  BuildMI(MBB, DL, TII->get(SystemZ::RISBG32), RotatedAltVal)
    .addReg(RotatedOldVal).addReg(Src2)
    .addImm(32).addImm(31 + BitSize).addImm(0);
MBB->addSuccessor(UpdateMBB);

//  UpdateMBB:
//   %RotatedNewVal = PHI [ %RotatedOldVal, LoopMBB ],
//                        [ %RotatedAltVal, UseAltMBB ]
//   %NewVal        = RLL %RotatedNewVal, 0(%NegBitShift)
//   %Dest          = CS %OldVal, %NewVal, Disp(%Base)
//   JNE LoopMBB
//   # fall through to DoneMBB
MBB = UpdateMBB;
BuildMI(MBB, DL, TII->get(SystemZ::PHI), RotatedNewVal)
  .addReg(RotatedOldVal).addMBB(LoopMBB)
  .addReg(RotatedAltVal).addMBB(UseAltMBB);
if (IsSubWord)
  BuildMI(MBB, DL, TII->get(SystemZ::RLL), NewVal)
    .addReg(RotatedNewVal).addReg(NegBitShift).addImm(0);
BuildMI(MBB, DL, TII->get(CSOpcode), Dest)
    .addReg(OldVal)
    .addReg(NewVal)
    .add(Base)
    .addImm(Disp);
BuildMI(MBB, DL, TII->get(SystemZ::BRC))
  .addImm(SystemZ::CCMASK_CS).addImm(SystemZ::CCMASK_CS_NE).addMBB(LoopMBB);
MBB->addSuccessor(LoopMBB);
MBB->addSuccessor(DoneMBB);

MI.eraseFromParent();
return DoneMBB;
7606}

7608// Implement EmitInstrWithCustomInserter for pseudo ATOMIC_CMP_SWAPW
7609// instruction MI.
7610MachineBasicBlock *
7611SystemZTargetLowering::emitAtomicCmpSwapW(MachineInstr &MI,
                                        MachineBasicBlock *MBB) const {
MachineFunction &MF = *MBB->getParent();
const SystemZInstrInfo *TII =
    static_cast<const SystemZInstrInfo *>(Subtarget.getInstrInfo());
MachineRegisterInfo &MRI = MF.getRegInfo();

// Extract the operands.  Base can be a register or a frame index.
Register Dest = MI.getOperand(0).getReg();
MachineOperand Base = earlyUseOperand(MI.getOperand(1));
int64_t Disp = MI.getOperand(2).getImm();
Register CmpVal = MI.getOperand(3).getReg();
Register OrigSwapVal = MI.getOperand(4).getReg();
Register BitShift = MI.getOperand(5).getReg();
Register NegBitShift = MI.getOperand(6).getReg();
int64_t BitSize = MI.getOperand(7).getImm();
DebugLoc DL = MI.getDebugLoc();

const TargetRegisterClass *RC = &SystemZ::GR32BitRegClass;

// Get the right opcodes for the displacement and zero-extension.
unsigned LOpcode  = TII->getOpcodeForOffset(SystemZ::L,  Disp);
unsigned CSOpcode = TII->getOpcodeForOffset(SystemZ::CS, Disp);
unsigned ZExtOpcode  = BitSize == 8 ? SystemZ::LLCR : SystemZ::LLHR;
assert(LOpcode && CSOpcode && "Displacement out of range")(static_cast <bool> (LOpcode && CSOpcode &&
 "Displacement out of range") ? void (0) : __assert_fail ("LOpcode && CSOpcode && \"Displacement out of range\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp"
, 7635, __extension__ __PRETTY_FUNCTION__));

// Create virtual registers for temporary results.
Register OrigOldVal = MRI.createVirtualRegister(RC);
Register OldVal = MRI.createVirtualRegister(RC);
Register SwapVal = MRI.createVirtualRegister(RC);
Register StoreVal = MRI.createVirtualRegister(RC);
Register OldValRot = MRI.createVirtualRegister(RC);
Register RetryOldVal = MRI.createVirtualRegister(RC);
Register RetrySwapVal = MRI.createVirtualRegister(RC);

// Insert 2 basic blocks for the loop.
MachineBasicBlock *StartMBB = MBB;
MachineBasicBlock *DoneMBB  = SystemZ::splitBlockBefore(MI, MBB);
MachineBasicBlock *LoopMBB  = SystemZ::emitBlockAfter(StartMBB);
MachineBasicBlock *SetMBB   = SystemZ::emitBlockAfter(LoopMBB);

//  StartMBB:
//   ...
//   %OrigOldVal     = L Disp(%Base)
//   # fall through to LoopMBB
MBB = StartMBB;
BuildMI(MBB, DL, TII->get(LOpcode), OrigOldVal)
    .add(Base)
    .addImm(Disp)
    .addReg(0);
MBB->addSuccessor(LoopMBB);

//  LoopMBB:
//   %OldVal        = phi [ %OrigOldVal, EntryBB ], [ %RetryOldVal, SetMBB ]
//   %SwapVal       = phi [ %OrigSwapVal, EntryBB ], [ %RetrySwapVal, SetMBB ]
//   %OldValRot     = RLL %OldVal, BitSize(%BitShift)
//                      ^^ The low BitSize bits contain the field
//                         of interest.
//   %RetrySwapVal = RISBG32 %SwapVal, %OldValRot, 32, 63-BitSize, 0
//                      ^^ Replace the upper 32-BitSize bits of the
//                         swap value with those that we loaded and rotated.
//   %Dest = LL[CH] %OldValRot
//   CR %Dest, %CmpVal
//   JNE DoneMBB
//   # Fall through to SetMBB
MBB = LoopMBB;
BuildMI(MBB, DL, TII->get(SystemZ::PHI), OldVal)
  .addReg(OrigOldVal).addMBB(StartMBB)
  .addReg(RetryOldVal).addMBB(SetMBB);
BuildMI(MBB, DL, TII->get(SystemZ::PHI), SwapVal)
  .addReg(OrigSwapVal).addMBB(StartMBB)
  .addReg(RetrySwapVal).addMBB(SetMBB);
BuildMI(MBB, DL, TII->get(SystemZ::RLL), OldValRot)
  .addReg(OldVal).addReg(BitShift).addImm(BitSize);
BuildMI(MBB, DL, TII->get(SystemZ::RISBG32), RetrySwapVal)
  .addReg(SwapVal).addReg(OldValRot).addImm(32).addImm(63 - BitSize).addImm(0);
BuildMI(MBB, DL, TII->get(ZExtOpcode), Dest)
  .addReg(OldValRot);
BuildMI(MBB, DL, TII->get(SystemZ::CR))
  .addReg(Dest).addReg(CmpVal);
BuildMI(MBB, DL, TII->get(SystemZ::BRC))
  .addImm(SystemZ::CCMASK_ICMP)
  .addImm(SystemZ::CCMASK_CMP_NE).addMBB(DoneMBB);
MBB->addSuccessor(DoneMBB);
MBB->addSuccessor(SetMBB);

//  SetMBB:
//   %StoreVal     = RLL %RetrySwapVal, -BitSize(%NegBitShift)
//                      ^^ Rotate the new field to its proper position.
//   %RetryOldVal  = CS %OldVal, %StoreVal, Disp(%Base)
//   JNE LoopMBB
//   # fall through to ExitMBB
MBB = SetMBB;
BuildMI(MBB, DL, TII->get(SystemZ::RLL), StoreVal)
  .addReg(RetrySwapVal).addReg(NegBitShift).addImm(-BitSize);
BuildMI(MBB, DL, TII->get(CSOpcode), RetryOldVal)
    .addReg(OldVal)
    .addReg(StoreVal)
    .add(Base)
    .addImm(Disp);
BuildMI(MBB, DL, TII->get(SystemZ::BRC))
  .addImm(SystemZ::CCMASK_CS).addImm(SystemZ::CCMASK_CS_NE).addMBB(LoopMBB);
MBB->addSuccessor(LoopMBB);
MBB->addSuccessor(DoneMBB);

// If the CC def wasn't dead in the ATOMIC_CMP_SWAPW, mark CC as live-in
// to the block after the loop.  At this point, CC may have been defined
// either by the CR in LoopMBB or by the CS in SetMBB.
if (!MI.registerDefIsDead(SystemZ::CC))
  DoneMBB->addLiveIn(SystemZ::CC);

MI.eraseFromParent();
return DoneMBB;
7724}

7726// Emit a move from two GR64s to a GR128.
7727MachineBasicBlock *
7728SystemZTargetLowering::emitPair128(MachineInstr &MI,
                                 MachineBasicBlock *MBB) const {
MachineFunction &MF = *MBB->getParent();
const SystemZInstrInfo *TII =
    static_cast<const SystemZInstrInfo *>(Subtarget.getInstrInfo());
MachineRegisterInfo &MRI = MF.getRegInfo();
DebugLoc DL = MI.getDebugLoc();

Register Dest = MI.getOperand(0).getReg();
Register Hi = MI.getOperand(1).getReg();
Register Lo = MI.getOperand(2).getReg();
Register Tmp1 = MRI.createVirtualRegister(&SystemZ::GR128BitRegClass);
Register Tmp2 = MRI.createVirtualRegister(&SystemZ::GR128BitRegClass);

BuildMI(*MBB, MI, DL, TII->get(TargetOpcode::IMPLICIT_DEF), Tmp1);
BuildMI(*MBB, MI, DL, TII->get(TargetOpcode::INSERT_SUBREG), Tmp2)
  .addReg(Tmp1).addReg(Hi).addImm(SystemZ::subreg_h64);
BuildMI(*MBB, MI, DL, TII->get(TargetOpcode::INSERT_SUBREG), Dest)
  .addReg(Tmp2).addReg(Lo).addImm(SystemZ::subreg_l64);

MI.eraseFromParent();
return MBB;
7750}

7752// Emit an extension from a GR64 to a GR128.  ClearEven is true
7753// if the high register of the GR128 value must be cleared or false if
7754// it's "don't care".
7755MachineBasicBlock *SystemZTargetLowering::emitExt128(MachineInstr &MI,
                                                   MachineBasicBlock *MBB,
                                                   bool ClearEven) const {
MachineFunction &MF = *MBB->getParent();
const SystemZInstrInfo *TII =
    static_cast<const SystemZInstrInfo *>(Subtarget.getInstrInfo());
MachineRegisterInfo &MRI = MF.getRegInfo();
DebugLoc DL = MI.getDebugLoc();

Register Dest = MI.getOperand(0).getReg();
Register Src = MI.getOperand(1).getReg();
Register In128 = MRI.createVirtualRegister(&SystemZ::GR128BitRegClass);

BuildMI(*MBB, MI, DL, TII->get(TargetOpcode::IMPLICIT_DEF), In128);
if (ClearEven) {
  Register NewIn128 = MRI.createVirtualRegister(&SystemZ::GR128BitRegClass);
  Register Zero64 = MRI.createVirtualRegister(&SystemZ::GR64BitRegClass);

  BuildMI(*MBB, MI, DL, TII->get(SystemZ::LLILL), Zero64)
    .addImm(0);
  BuildMI(*MBB, MI, DL, TII->get(TargetOpcode::INSERT_SUBREG), NewIn128)
    .addReg(In128).addReg(Zero64).addImm(SystemZ::subreg_h64);
  In128 = NewIn128;
}
BuildMI(*MBB, MI, DL, TII->get(TargetOpcode::INSERT_SUBREG), Dest)
  .addReg(In128).addReg(Src).addImm(SystemZ::subreg_l64);

MI.eraseFromParent();
return MBB;
7784}

7786MachineBasicBlock *SystemZTargetLowering::emitMemMemWrapper(
  MachineInstr &MI, MachineBasicBlock *MBB, unsigned Opcode) const {
MachineFunction &MF = *MBB->getParent();
const SystemZInstrInfo *TII =
    static_cast<const SystemZInstrInfo *>(Subtarget.getInstrInfo());
MachineRegisterInfo &MRI = MF.getRegInfo();
DebugLoc DL = MI.getDebugLoc();

MachineOperand DestBase = earlyUseOperand(MI.getOperand(0));
uint64_t DestDisp = MI.getOperand(1).getImm();
MachineOperand SrcBase = earlyUseOperand(MI.getOperand(2));
uint64_t SrcDisp = MI.getOperand(3).getImm();
MachineOperand &LengthMO = MI.getOperand(4);
uint64_t ImmLength = LengthMO.isImm() ? LengthMO.getImm() : 0;
Register LenMinus1Reg =
    LengthMO.isReg() ? LengthMO.getReg() : SystemZ::NoRegister;

// When generating more than one CLC, all but the last will need to
// branch to the end when a difference is found.
MachineBasicBlock *EndMBB = (ImmLength > 256 && Opcode == SystemZ::CLC
                                 ? SystemZ::splitBlockAfter(MI, MBB)
                                 : nullptr);

// Check for the loop form, in which operand 5 is the trip count.
if (MI.getNumExplicitOperands() > 5) {
  Register StartCountReg = MI.getOperand(5).getReg();
  bool HaveSingleBase = DestBase.isIdenticalTo(SrcBase);

  auto loadZeroAddress = [&]() -> MachineOperand {
    Register Reg = MRI.createVirtualRegister(&SystemZ::ADDR64BitRegClass);
    BuildMI(*MBB, MI, DL, TII->get(SystemZ::LGHI), Reg).addImm(0);
    return MachineOperand::CreateReg(Reg, false);
  };
  if (DestBase.isReg() && DestBase.getReg() == SystemZ::NoRegister)
    DestBase = loadZeroAddress();
  if (SrcBase.isReg() && SrcBase.getReg() == SystemZ::NoRegister)
    SrcBase = HaveSingleBase ? DestBase : loadZeroAddress();

  MachineBasicBlock *StartMBB = nullptr;
  MachineBasicBlock *LoopMBB = nullptr;
  MachineBasicBlock *NextMBB = nullptr;
  MachineBasicBlock *DoneMBB = nullptr;
  MachineBasicBlock *AllDoneMBB = nullptr;

  Register StartSrcReg = forceReg(MI, SrcBase, TII);
  Register StartDestReg =
      (HaveSingleBase ? StartSrcReg : forceReg(MI, DestBase, TII));

  const TargetRegisterClass *RC = &SystemZ::ADDR64BitRegClass;
  Register ThisSrcReg  = MRI.createVirtualRegister(RC);
  Register ThisDestReg =
      (HaveSingleBase ? ThisSrcReg : MRI.createVirtualRegister(RC));
  Register NextSrcReg  = MRI.createVirtualRegister(RC);
  Register NextDestReg =
      (HaveSingleBase ? NextSrcReg : MRI.createVirtualRegister(RC));
  RC = &SystemZ::GR64BitRegClass;
  Register ThisCountReg = MRI.createVirtualRegister(RC);
  Register NextCountReg = MRI.createVirtualRegister(RC);

  if (LengthMO.isReg()) {
    AllDoneMBB = SystemZ::splitBlockBefore(MI, MBB);
    StartMBB = SystemZ::emitBlockAfter(MBB);
    LoopMBB = SystemZ::emitBlockAfter(StartMBB);
    NextMBB = LoopMBB;
    DoneMBB = SystemZ::emitBlockAfter(LoopMBB);

    //  MBB:
    //   # Jump to AllDoneMBB if LenMinus1Reg is -1, or fall thru to StartMBB.
    BuildMI(MBB, DL, TII->get(SystemZ::CGHI))
      .addReg(LenMinus1Reg).addImm(-1);
    BuildMI(MBB, DL, TII->get(SystemZ::BRC))
      .addImm(SystemZ::CCMASK_ICMP).addImm(SystemZ::CCMASK_CMP_EQ)
      .addMBB(AllDoneMBB);
    MBB->addSuccessor(AllDoneMBB);
    MBB->addSuccessor(StartMBB);

    // StartMBB:
    // # Jump to DoneMBB if %StartCountReg is zero, or fall through to LoopMBB.
    MBB = StartMBB;
    BuildMI(MBB, DL, TII->get(SystemZ::CGHI))
      .addReg(StartCountReg).addImm(0);
    BuildMI(MBB, DL, TII->get(SystemZ::BRC))
      .addImm(SystemZ::CCMASK_ICMP).addImm(SystemZ::CCMASK_CMP_EQ)
      .addMBB(DoneMBB);
    MBB->addSuccessor(DoneMBB);
    MBB->addSuccessor(LoopMBB);
  }
  else {
    StartMBB = MBB;
    DoneMBB = SystemZ::splitBlockBefore(MI, MBB);
    LoopMBB = SystemZ::emitBlockAfter(StartMBB);
    NextMBB = (EndMBB ? SystemZ::emitBlockAfter(LoopMBB) : LoopMBB);

    //  StartMBB:
    //   # fall through to LoopMBB
    MBB->addSuccessor(LoopMBB);

    DestBase = MachineOperand::CreateReg(NextDestReg, false);
    SrcBase = MachineOperand::CreateReg(NextSrcReg, false);
    ImmLength &= 255;
    if (EndMBB && !ImmLength)
      // If the loop handled the whole CLC range, DoneMBB will be empty with
      // CC live-through into EndMBB, so add it as live-in.
      DoneMBB->addLiveIn(SystemZ::CC);
  }

  //  LoopMBB:
  //   %ThisDestReg = phi [ %StartDestReg, StartMBB ],
  //                      [ %NextDestReg, NextMBB ]
  //   %ThisSrcReg = phi [ %StartSrcReg, StartMBB ],
  //                     [ %NextSrcReg, NextMBB ]
  //   %ThisCountReg = phi [ %StartCountReg, StartMBB ],
  //                       [ %NextCountReg, NextMBB ]
  //   ( PFD 2, 768+DestDisp(%ThisDestReg) )
  //   Opcode DestDisp(256,%ThisDestReg), SrcDisp(%ThisSrcReg)
  //   ( JLH EndMBB )
  //
  // The prefetch is used only for MVC.  The JLH is used only for CLC.
  MBB = LoopMBB;
  BuildMI(MBB, DL, TII->get(SystemZ::PHI), ThisDestReg)
    .addReg(StartDestReg).addMBB(StartMBB)
    .addReg(NextDestReg).addMBB(NextMBB);
  if (!HaveSingleBase)
    BuildMI(MBB, DL, TII->get(SystemZ::PHI), ThisSrcReg)
      .addReg(StartSrcReg).addMBB(StartMBB)
      .addReg(NextSrcReg).addMBB(NextMBB);
  BuildMI(MBB, DL, TII->get(SystemZ::PHI), ThisCountReg)
    .addReg(StartCountReg).addMBB(StartMBB)
    .addReg(NextCountReg).addMBB(NextMBB);
  if (Opcode == SystemZ::MVC)
    BuildMI(MBB, DL, TII->get(SystemZ::PFD))
      .addImm(SystemZ::PFD_WRITE)
      .addReg(ThisDestReg).addImm(DestDisp + 768).addReg(0);
  BuildMI(MBB, DL, TII->get(Opcode))
    .addReg(ThisDestReg).addImm(DestDisp).addImm(256)
    .addReg(ThisSrcReg).addImm(SrcDisp);
  if (EndMBB) {
    BuildMI(MBB, DL, TII->get(SystemZ::BRC))
      .addImm(SystemZ::CCMASK_ICMP).addImm(SystemZ::CCMASK_CMP_NE)
      .addMBB(EndMBB);
    MBB->addSuccessor(EndMBB);
    MBB->addSuccessor(NextMBB);
  }

  // NextMBB:
  //   %NextDestReg = LA 256(%ThisDestReg)
  //   %NextSrcReg = LA 256(%ThisSrcReg)
  //   %NextCountReg = AGHI %ThisCountReg, -1
  //   CGHI %NextCountReg, 0
  //   JLH LoopMBB
  //   # fall through to DoneMBB
  //
  // The AGHI, CGHI and JLH should be converted to BRCTG by later passes.
  MBB = NextMBB;
  BuildMI(MBB, DL, TII->get(SystemZ::LA), NextDestReg)
    .addReg(ThisDestReg).addImm(256).addReg(0);
  if (!HaveSingleBase)
    BuildMI(MBB, DL, TII->get(SystemZ::LA), NextSrcReg)
      .addReg(ThisSrcReg).addImm(256).addReg(0);
  BuildMI(MBB, DL, TII->get(SystemZ::AGHI), NextCountReg)
    .addReg(ThisCountReg).addImm(-1);
  BuildMI(MBB, DL, TII->get(SystemZ::CGHI))
    .addReg(NextCountReg).addImm(0);
  BuildMI(MBB, DL, TII->get(SystemZ::BRC))
    .addImm(SystemZ::CCMASK_ICMP).addImm(SystemZ::CCMASK_CMP_NE)
    .addMBB(LoopMBB);
  MBB->addSuccessor(LoopMBB);
  MBB->addSuccessor(DoneMBB);

  MBB = DoneMBB;
  if (LengthMO.isReg()) {
    // DoneMBB:
    // # Make PHIs for RemDestReg/RemSrcReg as the loop may or may not run.
    // # Use EXecute Relative Long for the remainder of the bytes. The target
    //   instruction of the EXRL will have a length field of 1 since 0 is an
    //   illegal value. The number of bytes processed becomes (%LenMinus1Reg &
    //   0xff) + 1.
    // # Fall through to AllDoneMBB.
    Register RemSrcReg  = MRI.createVirtualRegister(&SystemZ::ADDR64BitRegClass);
    Register RemDestReg = HaveSingleBase ? RemSrcReg
      : MRI.createVirtualRegister(&SystemZ::ADDR64BitRegClass);
    BuildMI(MBB, DL, TII->get(SystemZ::PHI), RemDestReg)
      .addReg(StartDestReg).addMBB(StartMBB)
      .addReg(NextDestReg).addMBB(LoopMBB);
    if (!HaveSingleBase)
      BuildMI(MBB, DL, TII->get(SystemZ::PHI), RemSrcReg)
        .addReg(StartSrcReg).addMBB(StartMBB)
        .addReg(NextSrcReg).addMBB(LoopMBB);
    MRI.constrainRegClass(LenMinus1Reg, &SystemZ::ADDR64BitRegClass);
    BuildMI(MBB, DL, TII->get(SystemZ::EXRL_Pseudo))
      .addImm(Opcode)
      .addReg(LenMinus1Reg)
      .addReg(RemDestReg).addImm(DestDisp)
      .addReg(RemSrcReg).addImm(SrcDisp);
    MBB->addSuccessor(AllDoneMBB);
    MBB = AllDoneMBB;
  }
}

// Handle any remaining bytes with straight-line code.
while (ImmLength > 0) {
  uint64_t ThisLength = std::min(ImmLength, uint64_t(256));
  // The previous iteration might have created out-of-range displacements.
  // Apply them using LAY if so.
  if (!isUInt<12>(DestDisp)) {
    Register Reg = MRI.createVirtualRegister(&SystemZ::ADDR64BitRegClass);
    BuildMI(*MBB, MI, MI.getDebugLoc(), TII->get(SystemZ::LAY), Reg)
        .add(DestBase)
        .addImm(DestDisp)
        .addReg(0);
    DestBase = MachineOperand::CreateReg(Reg, false);
    DestDisp = 0;
  }
  if (!isUInt<12>(SrcDisp)) {
    Register Reg = MRI.createVirtualRegister(&SystemZ::ADDR64BitRegClass);
    BuildMI(*MBB, MI, MI.getDebugLoc(), TII->get(SystemZ::LAY), Reg)
        .add(SrcBase)
        .addImm(SrcDisp)
        .addReg(0);
    SrcBase = MachineOperand::CreateReg(Reg, false);
    SrcDisp = 0;
  }
  BuildMI(*MBB, MI, DL, TII->get(Opcode))
      .add(DestBase)
      .addImm(DestDisp)
      .addImm(ThisLength)
      .add(SrcBase)
      .addImm(SrcDisp)
      .setMemRefs(MI.memoperands());
  DestDisp += ThisLength;
  SrcDisp += ThisLength;
  ImmLength -= ThisLength;
  // If there's another CLC to go, branch to the end if a difference
  // was found.
  if (EndMBB && ImmLength > 0) {
    MachineBasicBlock *NextMBB = SystemZ::splitBlockBefore(MI, MBB);
    BuildMI(MBB, DL, TII->get(SystemZ::BRC))
      .addImm(SystemZ::CCMASK_ICMP).addImm(SystemZ::CCMASK_CMP_NE)
      .addMBB(EndMBB);
    MBB->addSuccessor(EndMBB);
    MBB->addSuccessor(NextMBB);
    MBB = NextMBB;
  }
}
if (EndMBB) {
  MBB->addSuccessor(EndMBB);
  MBB = EndMBB;
  MBB->addLiveIn(SystemZ::CC);
}

MI.eraseFromParent();
return MBB;
8038}

8040// Decompose string pseudo-instruction MI into a loop that continually performs
8041// Opcode until CC != 3.
8042MachineBasicBlock *SystemZTargetLowering::emitStringWrapper(
  MachineInstr &MI, MachineBasicBlock *MBB, unsigned Opcode) const {
MachineFunction &MF = *MBB->getParent();
const SystemZInstrInfo *TII =
    static_cast<const SystemZInstrInfo *>(Subtarget.getInstrInfo());
MachineRegisterInfo &MRI = MF.getRegInfo();
DebugLoc DL = MI.getDebugLoc();

uint64_t End1Reg = MI.getOperand(0).getReg();
uint64_t Start1Reg = MI.getOperand(1).getReg();
uint64_t Start2Reg = MI.getOperand(2).getReg();
uint64_t CharReg = MI.getOperand(3).getReg();

const TargetRegisterClass *RC = &SystemZ::GR64BitRegClass;
uint64_t This1Reg = MRI.createVirtualRegister(RC);
uint64_t This2Reg = MRI.createVirtualRegister(RC);
uint64_t End2Reg  = MRI.createVirtualRegister(RC);

MachineBasicBlock *StartMBB = MBB;
MachineBasicBlock *DoneMBB = SystemZ::splitBlockBefore(MI, MBB);
MachineBasicBlock *LoopMBB = SystemZ::emitBlockAfter(StartMBB);

//  StartMBB:
//   # fall through to LoopMBB
MBB->addSuccessor(LoopMBB);

//  LoopMBB:
//   %This1Reg = phi [ %Start1Reg, StartMBB ], [ %End1Reg, LoopMBB ]
//   %This2Reg = phi [ %Start2Reg, StartMBB ], [ %End2Reg, LoopMBB ]
//   R0L = %CharReg
//   %End1Reg, %End2Reg = CLST %This1Reg, %This2Reg -- uses R0L
//   JO LoopMBB
//   # fall through to DoneMBB
//
// The load of R0L can be hoisted by post-RA LICM.
MBB = LoopMBB;

BuildMI(MBB, DL, TII->get(SystemZ::PHI), This1Reg)
  .addReg(Start1Reg).addMBB(StartMBB)
  .addReg(End1Reg).addMBB(LoopMBB);
BuildMI(MBB, DL, TII->get(SystemZ::PHI), This2Reg)
  .addReg(Start2Reg).addMBB(StartMBB)
  .addReg(End2Reg).addMBB(LoopMBB);
BuildMI(MBB, DL, TII->get(TargetOpcode::COPY), SystemZ::R0L).addReg(CharReg);
BuildMI(MBB, DL, TII->get(Opcode))
  .addReg(End1Reg, RegState::Define).addReg(End2Reg, RegState::Define)
  .addReg(This1Reg).addReg(This2Reg);
BuildMI(MBB, DL, TII->get(SystemZ::BRC))
  .addImm(SystemZ::CCMASK_ANY).addImm(SystemZ::CCMASK_3).addMBB(LoopMBB);
MBB->addSuccessor(LoopMBB);
MBB->addSuccessor(DoneMBB);

DoneMBB->addLiveIn(SystemZ::CC);

MI.eraseFromParent();
return DoneMBB;
8098}

8100// Update TBEGIN instruction with final opcode and register clobbers.
8101MachineBasicBlock *SystemZTargetLowering::emitTransactionBegin(
  MachineInstr &MI, MachineBasicBlock *MBB, unsigned Opcode,
  bool NoFloat) const {
MachineFunction &MF = *MBB->getParent();
const TargetFrameLowering *TFI = Subtarget.getFrameLowering();
const SystemZInstrInfo *TII = Subtarget.getInstrInfo();

// Update opcode.
MI.setDesc(TII->get(Opcode));

// We cannot handle a TBEGIN that clobbers the stack or frame pointer.
// Make sure to add the corresponding GRSM bits if they are missing.
uint64_t Control = MI.getOperand(2).getImm();
static const unsigned GPRControlBit[16] = {
  0x8000, 0x8000, 0x4000, 0x4000, 0x2000, 0x2000, 0x1000, 0x1000,
  0x0800, 0x0800, 0x0400, 0x0400, 0x0200, 0x0200, 0x0100, 0x0100
};
Control |= GPRControlBit[15];
if (TFI->hasFP(MF))
  Control |= GPRControlBit[11];
MI.getOperand(2).setImm(Control);

// Add GPR clobbers.
for (int I = 0; I < 16; I++) {
  if ((Control & GPRControlBit[I]) == 0) {
    unsigned Reg = SystemZMC::GR64Regs[I];
    MI.addOperand(MachineOperand::CreateReg(Reg, true, true));
  }
}

// Add FPR/VR clobbers.
if (!NoFloat && (Control & 4) != 0) {
  if (Subtarget.hasVector()) {
    for (int I = 0; I < 32; I++) {
      unsigned Reg = SystemZMC::VR128Regs[I];
      MI.addOperand(MachineOperand::CreateReg(Reg, true, true));
    }
  } else {
    for (int I = 0; I < 16; I++) {
      unsigned Reg = SystemZMC::FP64Regs[I];
      MI.addOperand(MachineOperand::CreateReg(Reg, true, true));
    }
  }
}

return MBB;
8147}

8149MachineBasicBlock *SystemZTargetLowering::emitLoadAndTestCmp0(
  MachineInstr &MI, MachineBasicBlock *MBB, unsigned Opcode) const {
MachineFunction &MF = *MBB->getParent();
MachineRegisterInfo *MRI = &MF.getRegInfo();
const SystemZInstrInfo *TII =
    static_cast<const SystemZInstrInfo *>(Subtarget.getInstrInfo());
DebugLoc DL = MI.getDebugLoc();

Register SrcReg = MI.getOperand(0).getReg();

// Create new virtual register of the same class as source.
const TargetRegisterClass *RC = MRI->getRegClass(SrcReg);
Register DstReg = MRI->createVirtualRegister(RC);

// Replace pseudo with a normal load-and-test that models the def as
// well.
BuildMI(*MBB, MI, DL, TII->get(Opcode), DstReg)
  .addReg(SrcReg)
  .setMIFlags(MI.getFlags());
MI.eraseFromParent();

return MBB;
8171}

8173MachineBasicBlock *SystemZTargetLowering::emitProbedAlloca(
  MachineInstr &MI, MachineBasicBlock *MBB) const {
MachineFunction &MF = *MBB->getParent();
MachineRegisterInfo *MRI = &MF.getRegInfo();
const SystemZInstrInfo *TII =
    static_cast<const SystemZInstrInfo *>(Subtarget.getInstrInfo());
DebugLoc DL = MI.getDebugLoc();
const unsigned ProbeSize = getStackProbeSize(MF);
Register DstReg = MI.getOperand(0).getReg();
Register SizeReg = MI.getOperand(2).getReg();

MachineBasicBlock *StartMBB = MBB;
MachineBasicBlock *DoneMBB  = SystemZ::splitBlockAfter(MI, MBB);
MachineBasicBlock *LoopTestMBB  = SystemZ::emitBlockAfter(StartMBB);
MachineBasicBlock *LoopBodyMBB = SystemZ::emitBlockAfter(LoopTestMBB);
MachineBasicBlock *TailTestMBB = SystemZ::emitBlockAfter(LoopBodyMBB);
MachineBasicBlock *TailMBB = SystemZ::emitBlockAfter(TailTestMBB);

MachineMemOperand *VolLdMMO = MF.getMachineMemOperand(MachinePointerInfo(),
  MachineMemOperand::MOVolatile | MachineMemOperand::MOLoad, 8, Align(1));

Register PHIReg = MRI->createVirtualRegister(&SystemZ::ADDR64BitRegClass);
Register IncReg = MRI->createVirtualRegister(&SystemZ::ADDR64BitRegClass);

//  LoopTestMBB
//  BRC TailTestMBB
//  # fallthrough to LoopBodyMBB
StartMBB->addSuccessor(LoopTestMBB);
MBB = LoopTestMBB;
BuildMI(MBB, DL, TII->get(SystemZ::PHI), PHIReg)
  .addReg(SizeReg)
  .addMBB(StartMBB)
  .addReg(IncReg)
  .addMBB(LoopBodyMBB);
BuildMI(MBB, DL, TII->get(SystemZ::CLGFI))
  .addReg(PHIReg)
  .addImm(ProbeSize);
BuildMI(MBB, DL, TII->get(SystemZ::BRC))
  .addImm(SystemZ::CCMASK_ICMP).addImm(SystemZ::CCMASK_CMP_LT)
  .addMBB(TailTestMBB);
MBB->addSuccessor(LoopBodyMBB);
MBB->addSuccessor(TailTestMBB);

//  LoopBodyMBB: Allocate and probe by means of a volatile compare.
//  J LoopTestMBB
MBB = LoopBodyMBB;
BuildMI(MBB, DL, TII->get(SystemZ::SLGFI), IncReg)
  .addReg(PHIReg)
  .addImm(ProbeSize);
BuildMI(MBB, DL, TII->get(SystemZ::SLGFI), SystemZ::R15D)
  .addReg(SystemZ::R15D)
  .addImm(ProbeSize);
BuildMI(MBB, DL, TII->get(SystemZ::CG)).addReg(SystemZ::R15D)
  .addReg(SystemZ::R15D).addImm(ProbeSize - 8).addReg(0)
  .setMemRefs(VolLdMMO);
BuildMI(MBB, DL, TII->get(SystemZ::J)).addMBB(LoopTestMBB);
MBB->addSuccessor(LoopTestMBB);

//  TailTestMBB
//  BRC DoneMBB
//  # fallthrough to TailMBB
MBB = TailTestMBB;
BuildMI(MBB, DL, TII->get(SystemZ::CGHI))
  .addReg(PHIReg)
  .addImm(0);
BuildMI(MBB, DL, TII->get(SystemZ::BRC))
  .addImm(SystemZ::CCMASK_ICMP).addImm(SystemZ::CCMASK_CMP_EQ)
  .addMBB(DoneMBB);
MBB->addSuccessor(TailMBB);
MBB->addSuccessor(DoneMBB);

//  TailMBB
//  # fallthrough to DoneMBB
MBB = TailMBB;
BuildMI(MBB, DL, TII->get(SystemZ::SLGR), SystemZ::R15D)
  .addReg(SystemZ::R15D)
  .addReg(PHIReg);
BuildMI(MBB, DL, TII->get(SystemZ::CG)).addReg(SystemZ::R15D)
  .addReg(SystemZ::R15D).addImm(-8).addReg(PHIReg)
  .setMemRefs(VolLdMMO);
MBB->addSuccessor(DoneMBB);

//  DoneMBB
MBB = DoneMBB;
BuildMI(*MBB, MBB->begin(), DL, TII->get(TargetOpcode::COPY), DstReg)
  .addReg(SystemZ::R15D);

MI.eraseFromParent();
return DoneMBB;
8262}

8264SDValue SystemZTargetLowering::
8265getBackchainAddress(SDValue SP, SelectionDAG &DAG) const {
MachineFunction &MF = DAG.getMachineFunction();
auto *TFL =
    static_cast<const SystemZFrameLowering *>(Subtarget.getFrameLowering());
SDLoc DL(SP);
return DAG.getNode(ISD::ADD, DL, MVT::i64, SP,
                   DAG.getIntPtrConstant(TFL->getBackchainOffset(MF), DL));
8272}

8274MachineBasicBlock *SystemZTargetLowering::EmitInstrWithCustomInserter(
  MachineInstr &MI, MachineBasicBlock *MBB) const {
switch (MI.getOpcode()) {
case SystemZ::Select32:
case SystemZ::Select64:
case SystemZ::SelectF32:
case SystemZ::SelectF64:
case SystemZ::SelectF128:
case SystemZ::SelectVR32:
case SystemZ::SelectVR64:
case SystemZ::SelectVR128:
  return emitSelect(MI, MBB);

case SystemZ::CondStore8Mux:
  return emitCondStore(MI, MBB, SystemZ::STCMux, 0, false);
case SystemZ::CondStore8MuxInv:
  return emitCondStore(MI, MBB, SystemZ::STCMux, 0, true);
case SystemZ::CondStore16Mux:
  return emitCondStore(MI, MBB, SystemZ::STHMux, 0, false);
case SystemZ::CondStore16MuxInv:
  return emitCondStore(MI, MBB, SystemZ::STHMux, 0, true);
case SystemZ::CondStore32Mux:
  return emitCondStore(MI, MBB, SystemZ::STMux, SystemZ::STOCMux, false);
case SystemZ::CondStore32MuxInv:
  return emitCondStore(MI, MBB, SystemZ::STMux, SystemZ::STOCMux, true);
case SystemZ::CondStore8:
  return emitCondStore(MI, MBB, SystemZ::STC, 0, false);
case SystemZ::CondStore8Inv:
  return emitCondStore(MI, MBB, SystemZ::STC, 0, true);
case SystemZ::CondStore16:
  return emitCondStore(MI, MBB, SystemZ::STH, 0, false);
case SystemZ::CondStore16Inv:
  return emitCondStore(MI, MBB, SystemZ::STH, 0, true);
case SystemZ::CondStore32:
  return emitCondStore(MI, MBB, SystemZ::ST, SystemZ::STOC, false);
case SystemZ::CondStore32Inv:
  return emitCondStore(MI, MBB, SystemZ::ST, SystemZ::STOC, true);
case SystemZ::CondStore64:
  return emitCondStore(MI, MBB, SystemZ::STG, SystemZ::STOCG, false);
case SystemZ::CondStore64Inv:
  return emitCondStore(MI, MBB, SystemZ::STG, SystemZ::STOCG, true);
case SystemZ::CondStoreF32:
  return emitCondStore(MI, MBB, SystemZ::STE, 0, false);
case SystemZ::CondStoreF32Inv:
  return emitCondStore(MI, MBB, SystemZ::STE, 0, true);
case SystemZ::CondStoreF64:
  return emitCondStore(MI, MBB, SystemZ::STD, 0, false);
case SystemZ::CondStoreF64Inv:
  return emitCondStore(MI, MBB, SystemZ::STD, 0, true);

case SystemZ::PAIR128:
  return emitPair128(MI, MBB);
case SystemZ::AEXT128:
  return emitExt128(MI, MBB, false);
case SystemZ::ZEXT128:
  return emitExt128(MI, MBB, true);

case SystemZ::ATOMIC_SWAPW:
  return emitAtomicLoadBinary(MI, MBB, 0, 0);
case SystemZ::ATOMIC_SWAP_32:
  return emitAtomicLoadBinary(MI, MBB, 0, 32);
case SystemZ::ATOMIC_SWAP_64:
  return emitAtomicLoadBinary(MI, MBB, 0, 64);

case SystemZ::ATOMIC_LOADW_AR:
  return emitAtomicLoadBinary(MI, MBB, SystemZ::AR, 0);
case SystemZ::ATOMIC_LOADW_AFI:
  return emitAtomicLoadBinary(MI, MBB, SystemZ::AFI, 0);
case SystemZ::ATOMIC_LOAD_AR:
  return emitAtomicLoadBinary(MI, MBB, SystemZ::AR, 32);
case SystemZ::ATOMIC_LOAD_AHI:
  return emitAtomicLoadBinary(MI, MBB, SystemZ::AHI, 32);
case SystemZ::ATOMIC_LOAD_AFI:
  return emitAtomicLoadBinary(MI, MBB, SystemZ::AFI, 32);
case SystemZ::ATOMIC_LOAD_AGR:
  return emitAtomicLoadBinary(MI, MBB, SystemZ::AGR, 64);
case SystemZ::ATOMIC_LOAD_AGHI:
  return emitAtomicLoadBinary(MI, MBB, SystemZ::AGHI, 64);
case SystemZ::ATOMIC_LOAD_AGFI:
  return emitAtomicLoadBinary(MI, MBB, SystemZ::AGFI, 64);

case SystemZ::ATOMIC_LOADW_SR:
  return emitAtomicLoadBinary(MI, MBB, SystemZ::SR, 0);
case SystemZ::ATOMIC_LOAD_SR:
  return emitAtomicLoadBinary(MI, MBB, SystemZ::SR, 32);
case SystemZ::ATOMIC_LOAD_SGR:
  return emitAtomicLoadBinary(MI, MBB, SystemZ::SGR, 64);

case SystemZ::ATOMIC_LOADW_NR:
  return emitAtomicLoadBinary(MI, MBB, SystemZ::NR, 0);
case SystemZ::ATOMIC_LOADW_NILH:
  return emitAtomicLoadBinary(MI, MBB, SystemZ::NILH, 0);
case SystemZ::ATOMIC_LOAD_NR:
  return emitAtomicLoadBinary(MI, MBB, SystemZ::NR, 32);
case SystemZ::ATOMIC_LOAD_NILL:
  return emitAtomicLoadBinary(MI, MBB, SystemZ::NILL, 32);
case SystemZ::ATOMIC_LOAD_NILH:
  return emitAtomicLoadBinary(MI, MBB, SystemZ::NILH, 32);
case SystemZ::ATOMIC_LOAD_NILF:
  return emitAtomicLoadBinary(MI, MBB, SystemZ::NILF, 32);
case SystemZ::ATOMIC_LOAD_NGR:
  return emitAtomicLoadBinary(MI, MBB, SystemZ::NGR, 64);
case SystemZ::ATOMIC_LOAD_NILL64:
  return emitAtomicLoadBinary(MI, MBB, SystemZ::NILL64, 64);
case SystemZ::ATOMIC_LOAD_NILH64:
  return emitAtomicLoadBinary(MI, MBB, SystemZ::NILH64, 64);
case SystemZ::ATOMIC_LOAD_NIHL64:
  return emitAtomicLoadBinary(MI, MBB, SystemZ::NIHL64, 64);
case SystemZ::ATOMIC_LOAD_NIHH64:
  return emitAtomicLoadBinary(MI, MBB, SystemZ::NIHH64, 64);
case SystemZ::ATOMIC_LOAD_NILF64:
  return emitAtomicLoadBinary(MI, MBB, SystemZ::NILF64, 64);
case SystemZ::ATOMIC_LOAD_NIHF64:
  return emitAtomicLoadBinary(MI, MBB, SystemZ::NIHF64, 64);

case SystemZ::ATOMIC_LOADW_OR:
  return emitAtomicLoadBinary(MI, MBB, SystemZ::OR, 0);
case SystemZ::ATOMIC_LOADW_OILH:
  return emitAtomicLoadBinary(MI, MBB, SystemZ::OILH, 0);
case SystemZ::ATOMIC_LOAD_OR:
  return emitAtomicLoadBinary(MI, MBB, SystemZ::OR, 32);
case SystemZ::ATOMIC_LOAD_OILL:
  return emitAtomicLoadBinary(MI, MBB, SystemZ::OILL, 32);
case SystemZ::ATOMIC_LOAD_OILH:
  return emitAtomicLoadBinary(MI, MBB, SystemZ::OILH, 32);
case SystemZ::ATOMIC_LOAD_OILF:
  return emitAtomicLoadBinary(MI, MBB, SystemZ::OILF, 32);
case SystemZ::ATOMIC_LOAD_OGR:
  return emitAtomicLoadBinary(MI, MBB, SystemZ::OGR, 64);
case SystemZ::ATOMIC_LOAD_OILL64:
  return emitAtomicLoadBinary(MI, MBB, SystemZ::OILL64, 64);
case SystemZ::ATOMIC_LOAD_OILH64:
  return emitAtomicLoadBinary(MI, MBB, SystemZ::OILH64, 64);
case SystemZ::ATOMIC_LOAD_OIHL64:
  return emitAtomicLoadBinary(MI, MBB, SystemZ::OIHL64, 64);
case SystemZ::ATOMIC_LOAD_OIHH64:
  return emitAtomicLoadBinary(MI, MBB, SystemZ::OIHH64, 64);
case SystemZ::ATOMIC_LOAD_OILF64:
  return emitAtomicLoadBinary(MI, MBB, SystemZ::OILF64, 64);
case SystemZ::ATOMIC_LOAD_OIHF64:
  return emitAtomicLoadBinary(MI, MBB, SystemZ::OIHF64, 64);

case SystemZ::ATOMIC_LOADW_XR:
  return emitAtomicLoadBinary(MI, MBB, SystemZ::XR, 0);
case SystemZ::ATOMIC_LOADW_XILF:
  return emitAtomicLoadBinary(MI, MBB, SystemZ::XILF, 0);
case SystemZ::ATOMIC_LOAD_XR:
  return emitAtomicLoadBinary(MI, MBB, SystemZ::XR, 32);
case SystemZ::ATOMIC_LOAD_XILF:
  return emitAtomicLoadBinary(MI, MBB, SystemZ::XILF, 32);
case SystemZ::ATOMIC_LOAD_XGR:
  return emitAtomicLoadBinary(MI, MBB, SystemZ::XGR, 64);
case SystemZ::ATOMIC_LOAD_XILF64:
  return emitAtomicLoadBinary(MI, MBB, SystemZ::XILF64, 64);
case SystemZ::ATOMIC_LOAD_XIHF64:
  return emitAtomicLoadBinary(MI, MBB, SystemZ::XIHF64, 64);

case SystemZ::ATOMIC_LOADW_NRi:
  return emitAtomicLoadBinary(MI, MBB, SystemZ::NR, 0, true);
case SystemZ::ATOMIC_LOADW_NILHi:
  return emitAtomicLoadBinary(MI, MBB, SystemZ::NILH, 0, true);
case SystemZ::ATOMIC_LOAD_NRi:
  return emitAtomicLoadBinary(MI, MBB, SystemZ::NR, 32, true);
case SystemZ::ATOMIC_LOAD_NILLi:
  return emitAtomicLoadBinary(MI, MBB, SystemZ::NILL, 32, true);
case SystemZ::ATOMIC_LOAD_NILHi:
  return emitAtomicLoadBinary(MI, MBB, SystemZ::NILH, 32, true);
case SystemZ::ATOMIC_LOAD_NILFi:
  return emitAtomicLoadBinary(MI, MBB, SystemZ::NILF, 32, true);
case SystemZ::ATOMIC_LOAD_NGRi:
  return emitAtomicLoadBinary(MI, MBB, SystemZ::NGR, 64, true);
case SystemZ::ATOMIC_LOAD_NILL64i:
  return emitAtomicLoadBinary(MI, MBB, SystemZ::NILL64, 64, true);
case SystemZ::ATOMIC_LOAD_NILH64i:
  return emitAtomicLoadBinary(MI, MBB, SystemZ::NILH64, 64, true);
case SystemZ::ATOMIC_LOAD_NIHL64i:
  return emitAtomicLoadBinary(MI, MBB, SystemZ::NIHL64, 64, true);
case SystemZ::ATOMIC_LOAD_NIHH64i:
  return emitAtomicLoadBinary(MI, MBB, SystemZ::NIHH64, 64, true);
case SystemZ::ATOMIC_LOAD_NILF64i:
  return emitAtomicLoadBinary(MI, MBB, SystemZ::NILF64, 64, true);
case SystemZ::ATOMIC_LOAD_NIHF64i:
  return emitAtomicLoadBinary(MI, MBB, SystemZ::NIHF64, 64, true);

case SystemZ::ATOMIC_LOADW_MIN:
  return emitAtomicLoadMinMax(MI, MBB, SystemZ::CR,
                              SystemZ::CCMASK_CMP_LE, 0);
case SystemZ::ATOMIC_LOAD_MIN_32:
  return emitAtomicLoadMinMax(MI, MBB, SystemZ::CR,
                              SystemZ::CCMASK_CMP_LE, 32);
case SystemZ::ATOMIC_LOAD_MIN_64:
  return emitAtomicLoadMinMax(MI, MBB, SystemZ::CGR,
                              SystemZ::CCMASK_CMP_LE, 64);

case SystemZ::ATOMIC_LOADW_MAX:
  return emitAtomicLoadMinMax(MI, MBB, SystemZ::CR,
                              SystemZ::CCMASK_CMP_GE, 0);
case SystemZ::ATOMIC_LOAD_MAX_32:
  return emitAtomicLoadMinMax(MI, MBB, SystemZ::CR,
                              SystemZ::CCMASK_CMP_GE, 32);
case SystemZ::ATOMIC_LOAD_MAX_64:
  return emitAtomicLoadMinMax(MI, MBB, SystemZ::CGR,
                              SystemZ::CCMASK_CMP_GE, 64);

case SystemZ::ATOMIC_LOADW_UMIN:
  return emitAtomicLoadMinMax(MI, MBB, SystemZ::CLR,
                              SystemZ::CCMASK_CMP_LE, 0);
case SystemZ::ATOMIC_LOAD_UMIN_32:
  return emitAtomicLoadMinMax(MI, MBB, SystemZ::CLR,
                              SystemZ::CCMASK_CMP_LE, 32);
case SystemZ::ATOMIC_LOAD_UMIN_64:
  return emitAtomicLoadMinMax(MI, MBB, SystemZ::CLGR,
                              SystemZ::CCMASK_CMP_LE, 64);

case SystemZ::ATOMIC_LOADW_UMAX:
  return emitAtomicLoadMinMax(MI, MBB, SystemZ::CLR,
                              SystemZ::CCMASK_CMP_GE, 0);
case SystemZ::ATOMIC_LOAD_UMAX_32:
  return emitAtomicLoadMinMax(MI, MBB, SystemZ::CLR,
                              SystemZ::CCMASK_CMP_GE, 32);
case SystemZ::ATOMIC_LOAD_UMAX_64:
  return emitAtomicLoadMinMax(MI, MBB, SystemZ::CLGR,
                              SystemZ::CCMASK_CMP_GE, 64);

case SystemZ::ATOMIC_CMP_SWAPW:
  return emitAtomicCmpSwapW(MI, MBB);
case SystemZ::MVCSequence:
case SystemZ::MVCLoop:
  return emitMemMemWrapper(MI, MBB, SystemZ::MVC);
case SystemZ::NCSequence:
case SystemZ::NCLoop:
  return emitMemMemWrapper(MI, MBB, SystemZ::NC);
case SystemZ::OCSequence:
case SystemZ::OCLoop:
  return emitMemMemWrapper(MI, MBB, SystemZ::OC);
case SystemZ::XCSequence:
case SystemZ::XCLoop:
case SystemZ::XCLoopVarLen:
  return emitMemMemWrapper(MI, MBB, SystemZ::XC);
case SystemZ::CLCSequence:
case SystemZ::CLCLoop:
  return emitMemMemWrapper(MI, MBB, SystemZ::CLC);
case SystemZ::CLSTLoop:
  return emitStringWrapper(MI, MBB, SystemZ::CLST);
case SystemZ::MVSTLoop:
  return emitStringWrapper(MI, MBB, SystemZ::MVST);
case SystemZ::SRSTLoop:
  return emitStringWrapper(MI, MBB, SystemZ::SRST);
case SystemZ::TBEGIN:
  return emitTransactionBegin(MI, MBB, SystemZ::TBEGIN, false);
case SystemZ::TBEGIN_nofloat:
  return emitTransactionBegin(MI, MBB, SystemZ::TBEGIN, true);
case SystemZ::TBEGINC:
  return emitTransactionBegin(MI, MBB, SystemZ::TBEGINC, true);
case SystemZ::LTEBRCompare_VecPseudo:
  return emitLoadAndTestCmp0(MI, MBB, SystemZ::LTEBR);
case SystemZ::LTDBRCompare_VecPseudo:
  return emitLoadAndTestCmp0(MI, MBB, SystemZ::LTDBR);
case SystemZ::LTXBRCompare_VecPseudo:
  return emitLoadAndTestCmp0(MI, MBB, SystemZ::LTXBR);

case SystemZ::PROBED_ALLOCA:
  return emitProbedAlloca(MI, MBB);

case TargetOpcode::STACKMAP:
case TargetOpcode::PATCHPOINT:
  return emitPatchPoint(MI, MBB);

default:
  llvm_unreachable("Unexpected instr type to insert")::llvm::llvm_unreachable_internal("Unexpected instr type to insert"
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp"
, 8543);
}
8545}

8547// This is only used by the isel schedulers, and is needed only to prevent
8548// compiler from crashing when list-ilp is used.
8549const TargetRegisterClass *
8550SystemZTargetLowering::getRepRegClassFor(MVT VT) const {
if (VT == MVT::Untyped)
  return &SystemZ::ADDR128BitRegClass;
return TargetLowering::getRepRegClassFor(VT);
8554}

←

/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/include/llvm/CodeGen/SelectionDAG.h

→

1//===- llvm/CodeGen/SelectionDAG.h - InstSelection DAG ----------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file declares the SelectionDAG class, and transitively defines the
10// SDNode class and subclasses.
11//
12//===----------------------------------------------------------------------===//

14#ifndef LLVM_CODEGEN_SELECTIONDAG_H
15#define LLVM_CODEGEN_SELECTIONDAG_H

17#include "llvm/ADT/APFloat.h"
18#include "llvm/ADT/APInt.h"
19#include "llvm/ADT/ArrayRef.h"
20#include "llvm/ADT/DenseMap.h"
21#include "llvm/ADT/DenseSet.h"
22#include "llvm/ADT/FoldingSet.h"
23#include "llvm/ADT/SetVector.h"
24#include "llvm/ADT/SmallVector.h"
25#include "llvm/ADT/StringMap.h"
26#include "llvm/ADT/ilist.h"
27#include "llvm/ADT/iterator.h"
28#include "llvm/ADT/iterator_range.h"
29#include "llvm/CodeGen/DAGCombine.h"
30#include "llvm/CodeGen/ISDOpcodes.h"
31#include "llvm/CodeGen/MachineFunction.h"
32#include "llvm/CodeGen/MachineMemOperand.h"
33#include "llvm/CodeGen/SelectionDAGNodes.h"
34#include "llvm/CodeGen/ValueTypes.h"
35#include "llvm/IR/DebugLoc.h"
36#include "llvm/IR/Instructions.h"
37#include "llvm/IR/Metadata.h"
38#include "llvm/Support/Allocator.h"
39#include "llvm/Support/ArrayRecycler.h"
40#include "llvm/Support/AtomicOrdering.h"
41#include "llvm/Support/Casting.h"
42#include "llvm/Support/CodeGen.h"
43#include "llvm/Support/ErrorHandling.h"
44#include "llvm/Support/MachineValueType.h"
45#include "llvm/Support/RecyclingAllocator.h"
46#include <algorithm>
47#include <cassert>
48#include <cstdint>
49#include <functional>
50#include <map>
51#include <string>
52#include <tuple>
53#include <utility>
54#include <vector>

56namespace llvm {

58class AAResults;
59class BlockAddress;
60class BlockFrequencyInfo;
61class Constant;
62class ConstantFP;
63class ConstantInt;
64class DataLayout;
65struct fltSemantics;
66class FunctionLoweringInfo;
67class GlobalValue;
68struct KnownBits;
69class LegacyDivergenceAnalysis;
70class LLVMContext;
71class MachineBasicBlock;
72class MachineConstantPoolValue;
73class MCSymbol;
74class OptimizationRemarkEmitter;
75class ProfileSummaryInfo;
76class SDDbgValue;
77class SDDbgOperand;
78class SDDbgLabel;
79class SelectionDAG;
80class SelectionDAGTargetInfo;
81class TargetLibraryInfo;
82class TargetLowering;
83class TargetMachine;
84class TargetSubtargetInfo;
85class Value;

87class SDVTListNode : public FoldingSetNode {
friend struct FoldingSetTrait<SDVTListNode>;

/// A reference to an Interned FoldingSetNodeID for this node.
/// The Allocator in SelectionDAG holds the data.
/// SDVTList contains all types which are frequently accessed in SelectionDAG.
/// The size of this list is not expected to be big so it won't introduce
/// a memory penalty.
FoldingSetNodeIDRef FastID;
const EVT *VTs;
unsigned int NumVTs;
/// The hash value for SDVTList is fixed, so cache it to avoid
/// hash calculation.
unsigned HashValue;

102public:
SDVTListNode(const FoldingSetNodeIDRef ID, const EVT *VT, unsigned int Num) :
    FastID(ID), VTs(VT), NumVTs(Num) {
  HashValue = ID.ComputeHash();
}

SDVTList getSDVTList() {
  SDVTList result = {VTs, NumVTs};
  return result;
}
112};

114/// Specialize FoldingSetTrait for SDVTListNode
115/// to avoid computing temp FoldingSetNodeID and hash value.
116template<> struct FoldingSetTrait<SDVTListNode> : DefaultFoldingSetTrait<SDVTListNode> {
static void Profile(const SDVTListNode &X, FoldingSetNodeID& ID) {
  ID = X.FastID;
}

static bool Equals(const SDVTListNode &X, const FoldingSetNodeID &ID,
                   unsigned IDHash, FoldingSetNodeID &TempID) {
  if (X.HashValue != IDHash)
    return false;
  return ID == X.FastID;
}

static unsigned ComputeHash(const SDVTListNode &X, FoldingSetNodeID &TempID) {
  return X.HashValue;
}
131};

133template <> struct ilist_alloc_traits<SDNode> {
static void deleteNode(SDNode *) {
  llvm_unreachable("ilist_traits<SDNode> shouldn't see a deleteNode call!")::llvm::llvm_unreachable_internal("ilist_traits<SDNode> shouldn't see a deleteNode call!"
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/include/llvm/CodeGen/SelectionDAG.h"
, 135);
}
137};

139/// Keeps track of dbg_value information through SDISel.  We do
140/// not build SDNodes for these so as not to perturb the generated code;
141/// instead the info is kept off to the side in this structure. Each SDNode may
142/// have one or more associated dbg_value entries. This information is kept in
143/// DbgValMap.
144/// Byval parameters are handled separately because they don't use alloca's,
145/// which busts the normal mechanism.  There is good reason for handling all
146/// parameters separately:  they may not have code generated for them, they
147/// should always go at the beginning of the function regardless of other code
148/// motion, and debug info for them is potentially useful even if the parameter
149/// is unused.  Right now only byval parameters are handled separately.
150class SDDbgInfo {
BumpPtrAllocator Alloc;
SmallVector<SDDbgValue*, 32> DbgValues;
SmallVector<SDDbgValue*, 32> ByvalParmDbgValues;
SmallVector<SDDbgLabel*, 4> DbgLabels;
using DbgValMapType = DenseMap<const SDNode *, SmallVector<SDDbgValue *, 2>>;
DbgValMapType DbgValMap;

158public:
SDDbgInfo() = default;
SDDbgInfo(const SDDbgInfo &) = delete;
SDDbgInfo &operator=(const SDDbgInfo &) = delete;

void add(SDDbgValue *V, bool isParameter);

void add(SDDbgLabel *L) { DbgLabels.push_back(L); }

/// Invalidate all DbgValues attached to the node and remove
/// it from the Node-to-DbgValues map.
void erase(const SDNode *Node);

void clear() {
  DbgValMap.clear();
  DbgValues.clear();
  ByvalParmDbgValues.clear();
  DbgLabels.clear();
  Alloc.Reset();
}

BumpPtrAllocator &getAlloc() { return Alloc; }

bool empty() const {
  return DbgValues.empty() && ByvalParmDbgValues.empty() && DbgLabels.empty();
}

ArrayRef<SDDbgValue*> getSDDbgValues(const SDNode *Node) const {
  auto I = DbgValMap.find(Node);
  if (I != DbgValMap.end())
    return I->second;
  return ArrayRef<SDDbgValue*>();
}

using DbgIterator = SmallVectorImpl<SDDbgValue*>::iterator;
using DbgLabelIterator = SmallVectorImpl<SDDbgLabel*>::iterator;

DbgIterator DbgBegin() { return DbgValues.begin(); }
DbgIterator DbgEnd()   { return DbgValues.end(); }
DbgIterator ByvalParmDbgBegin() { return ByvalParmDbgValues.begin(); }
DbgIterator ByvalParmDbgEnd()   { return ByvalParmDbgValues.end(); }
DbgLabelIterator DbgLabelBegin() { return DbgLabels.begin(); }
DbgLabelIterator DbgLabelEnd()   { return DbgLabels.end(); }
201};

203void checkForCycles(const SelectionDAG *DAG, bool force = false);

205/// This is used to represent a portion of an LLVM function in a low-level
206/// Data Dependence DAG representation suitable for instruction selection.
207/// This DAG is constructed as the first step of instruction selection in order
208/// to allow implementation of machine specific optimizations
209/// and code simplifications.
210///
211/// The representation used by the SelectionDAG is a target-independent
212/// representation, which has some similarities to the GCC RTL representation,
213/// but is significantly more simple, powerful, and is a graph form instead of a
214/// linear form.
215///
216class SelectionDAG {
const TargetMachine &TM;
const SelectionDAGTargetInfo *TSI = nullptr;
const TargetLowering *TLI = nullptr;
const TargetLibraryInfo *LibInfo = nullptr;
MachineFunction *MF;
Pass *SDAGISelPass = nullptr;
LLVMContext *Context;
CodeGenOpt::Level OptLevel;

LegacyDivergenceAnalysis * DA = nullptr;
FunctionLoweringInfo * FLI = nullptr;

/// The function-level optimization remark emitter.  Used to emit remarks
/// whenever manipulating the DAG.
OptimizationRemarkEmitter *ORE;

ProfileSummaryInfo *PSI = nullptr;
BlockFrequencyInfo *BFI = nullptr;

/// The starting token.
SDNode EntryNode;

/// The root of the entire DAG.
SDValue Root;

/// A linked list of nodes in the current DAG.
ilist<SDNode> AllNodes;

/// The AllocatorType for allocating SDNodes. We use
/// pool allocation with recycling.
using NodeAllocatorType = RecyclingAllocator<BumpPtrAllocator, SDNode,
                                             sizeof(LargestSDNode),
                                             alignof(MostAlignedSDNode)>;

/// Pool allocation for nodes.
NodeAllocatorType NodeAllocator;

/// This structure is used to memoize nodes, automatically performing
/// CSE with existing nodes when a duplicate is requested.
FoldingSet<SDNode> CSEMap;

/// Pool allocation for machine-opcode SDNode operands.
BumpPtrAllocator OperandAllocator;
ArrayRecycler<SDUse> OperandRecycler;

/// Pool allocation for misc. objects that are created once per SelectionDAG.
BumpPtrAllocator Allocator;

/// Tracks dbg_value and dbg_label information through SDISel.
SDDbgInfo *DbgInfo;

using CallSiteInfo = MachineFunction::CallSiteInfo;
using CallSiteInfoImpl = MachineFunction::CallSiteInfoImpl;

struct CallSiteDbgInfo {
  CallSiteInfo CSInfo;
  MDNode *HeapAllocSite = nullptr;
  bool NoMerge = false;
};

DenseMap<const SDNode *, CallSiteDbgInfo> SDCallSiteDbgInfo;

uint16_t NextPersistentId = 0;

281public:
/// Clients of various APIs that cause global effects on
/// the DAG can optionally implement this interface.  This allows the clients
/// to handle the various sorts of updates that happen.
///
/// A DAGUpdateListener automatically registers itself with DAG when it is
/// constructed, and removes itself when destroyed in RAII fashion.
struct DAGUpdateListener {
  DAGUpdateListener *const Next;
  SelectionDAG &DAG;

  explicit DAGUpdateListener(SelectionDAG &D)
    : Next(D.UpdateListeners), DAG(D) {
    DAG.UpdateListeners = this;
  }

  virtual ~DAGUpdateListener() {
    assert(DAG.UpdateListeners == this &&(static_cast <bool> (DAG.UpdateListeners == this &&
 "DAGUpdateListeners must be destroyed in LIFO order") ? void
 (0) : __assert_fail ("DAG.UpdateListeners == this && \"DAGUpdateListeners must be destroyed in LIFO order\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/include/llvm/CodeGen/SelectionDAG.h"
, 299, __extension__ __PRETTY_FUNCTION__))
           "DAGUpdateListeners must be destroyed in LIFO order")(static_cast <bool> (DAG.UpdateListeners == this &&
 "DAGUpdateListeners must be destroyed in LIFO order") ? void
 (0) : __assert_fail ("DAG.UpdateListeners == this && \"DAGUpdateListeners must be destroyed in LIFO order\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/include/llvm/CodeGen/SelectionDAG.h"
, 299, __extension__ __PRETTY_FUNCTION__));
    DAG.UpdateListeners = Next;
  }

  /// The node N that was deleted and, if E is not null, an
  /// equivalent node E that replaced it.
  virtual void NodeDeleted(SDNode *N, SDNode *E);

  /// The node N that was updated.
  virtual void NodeUpdated(SDNode *N);

  /// The node N that was inserted.
  virtual void NodeInserted(SDNode *N);
};

struct DAGNodeDeletedListener : public DAGUpdateListener {
  std::function<void(SDNode *, SDNode *)> Callback;

  DAGNodeDeletedListener(SelectionDAG &DAG,
                         std::function<void(SDNode *, SDNode *)> Callback)
      : DAGUpdateListener(DAG), Callback(std::move(Callback)) {}

  void NodeDeleted(SDNode *N, SDNode *E) override { Callback(N, E); }

 private:
  virtual void anchor();
};

/// Help to insert SDNodeFlags automatically in transforming. Use
/// RAII to save and resume flags in current scope.
class FlagInserter {
  SelectionDAG &DAG;
  SDNodeFlags Flags;
  FlagInserter *LastInserter;

public:
  FlagInserter(SelectionDAG &SDAG, SDNodeFlags Flags)
      : DAG(SDAG), Flags(Flags),
        LastInserter(SDAG.getFlagInserter()) {
    SDAG.setFlagInserter(this);
  }
  FlagInserter(SelectionDAG &SDAG, SDNode *N)
      : FlagInserter(SDAG, N->getFlags()) {}

  FlagInserter(const FlagInserter &) = delete;
  FlagInserter &operator=(const FlagInserter &) = delete;
  ~FlagInserter() { DAG.setFlagInserter(LastInserter); }

  SDNodeFlags getFlags() const { return Flags; }
};

/// When true, additional steps are taken to
/// ensure that getConstant() and similar functions return DAG nodes that
/// have legal types. This is important after type legalization since
/// any illegally typed nodes generated after this point will not experience
/// type legalization.
bool NewNodesMustHaveLegalTypes = false;

357private:
/// DAGUpdateListener is a friend so it can manipulate the listener stack.
friend struct DAGUpdateListener;

/// Linked list of registered DAGUpdateListener instances.
/// This stack is maintained by DAGUpdateListener RAII.
DAGUpdateListener *UpdateListeners = nullptr;

/// Implementation of setSubgraphColor.
/// Return whether we had to truncate the search.
bool setSubgraphColorHelper(SDNode *N, const char *Color,
                            DenseSet<SDNode *> &visited,
                            int level, bool &printed);

template <typename SDNodeT, typename... ArgTypes>
SDNodeT *newSDNode(ArgTypes &&... Args) {
  return new (NodeAllocator.template Allocate<SDNodeT>())
      SDNodeT(std::forward<ArgTypes>(Args)...);
}

/// Build a synthetic SDNodeT with the given args and extract its subclass
/// data as an integer (e.g. for use in a folding set).
///
/// The args to this function are the same as the args to SDNodeT's
/// constructor, except the second arg (assumed to be a const DebugLoc&) is
/// omitted.
template <typename SDNodeT, typename... ArgTypes>
static uint16_t getSyntheticNodeSubclassData(unsigned IROrder,
                                             ArgTypes &&... Args) {
  // The compiler can reduce this expression to a constant iff we pass an
  // empty DebugLoc.  Thankfully, the debug location doesn't have any bearing
  // on the subclass data.
  return SDNodeT(IROrder, DebugLoc(), std::forward<ArgTypes>(Args)...)
      .getRawSubclassData();
}

template <typename SDNodeTy>
static uint16_t getSyntheticNodeSubclassData(unsigned Opc, unsigned Order,
                                              SDVTList VTs, EVT MemoryVT,
                                              MachineMemOperand *MMO) {
  return SDNodeTy(Opc, Order, DebugLoc(), VTs, MemoryVT, MMO)
       .getRawSubclassData();
}

void createOperands(SDNode *Node, ArrayRef<SDValue> Vals);

void removeOperands(SDNode *Node) {
  if (!Node->OperandList)
    return;
  OperandRecycler.deallocate(
      ArrayRecycler<SDUse>::Capacity::get(Node->NumOperands),
      Node->OperandList);
  Node->NumOperands = 0;
  Node->OperandList = nullptr;
}
void CreateTopologicalOrder(std::vector<SDNode*>& Order);

414public:
// Maximum depth for recursive analysis such as computeKnownBits, etc.
static constexpr unsigned MaxRecursionDepth = 6;

explicit SelectionDAG(const TargetMachine &TM, CodeGenOpt::Level);
SelectionDAG(const SelectionDAG &) = delete;
SelectionDAG &operator=(const SelectionDAG &) = delete;
~SelectionDAG();

/// Prepare this SelectionDAG to process code in the given MachineFunction.
void init(MachineFunction &NewMF, OptimizationRemarkEmitter &NewORE,
          Pass *PassPtr, const TargetLibraryInfo *LibraryInfo,
          LegacyDivergenceAnalysis * Divergence,
          ProfileSummaryInfo *PSIin, BlockFrequencyInfo *BFIin);

void setFunctionLoweringInfo(FunctionLoweringInfo * FuncInfo) {
  FLI = FuncInfo;
}

/// Clear state and free memory necessary to make this
/// SelectionDAG ready to process a new block.
void clear();

MachineFunction &getMachineFunction() const { return *MF; }
const Pass *getPass() const { return SDAGISelPass; }

const DataLayout &getDataLayout() const { return MF->getDataLayout(); }
const TargetMachine &getTarget() const { return TM; }
const TargetSubtargetInfo &getSubtarget() const { return MF->getSubtarget(); }
const TargetLowering &getTargetLoweringInfo() const { return *TLI; }
const TargetLibraryInfo &getLibInfo() const { return *LibInfo; }
const SelectionDAGTargetInfo &getSelectionDAGInfo() const { return *TSI; }
const LegacyDivergenceAnalysis *getDivergenceAnalysis() const { return DA; }
LLVMContext *getContext() const { return Context; }
OptimizationRemarkEmitter &getORE() const { return *ORE; }
ProfileSummaryInfo *getPSI() const { return PSI; }
BlockFrequencyInfo *getBFI() const { return BFI; }

FlagInserter *getFlagInserter() { return Inserter; }
void setFlagInserter(FlagInserter *FI) { Inserter = FI; }

/// Just dump dot graph to a user-provided path and title.
/// This doesn't open the dot viewer program and
/// helps visualization when outside debugging session.
/// FileName expects absolute path. If provided
/// without any path separators then the file
/// will be created in the current directory.
/// Error will be emitted if the path is insane.
462#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
LLVM_DUMP_METHOD__attribute__((noinline)) __attribute__((__used__)) void dumpDotGraph(const Twine &FileName, const Twine &Title);
464#endif

/// Pop up a GraphViz/gv window with the DAG rendered using 'dot'.
void viewGraph(const std::string &Title);
void viewGraph();

470#ifndef NDEBUG
std::map<const SDNode *, std::string> NodeGraphAttrs;
472#endif

/// Clear all previously defined node graph attributes.
/// Intended to be used from a debugging tool (eg. gdb).
void clearGraphAttrs();

/// Set graph attributes for a node. (eg. "color=red".)
void setGraphAttrs(const SDNode *N, const char *Attrs);

/// Get graph attributes for a node. (eg. "color=red".)
/// Used from getNodeAttributes.
std::string getGraphAttrs(const SDNode *N) const;

/// Convenience for setting node color attribute.
void setGraphColor(const SDNode *N, const char *Color);

/// Convenience for setting subgraph color attribute.
void setSubgraphColor(SDNode *N, const char *Color);

using allnodes_const_iterator = ilist<SDNode>::const_iterator;

allnodes_const_iterator allnodes_begin() const { return AllNodes.begin(); }
allnodes_const_iterator allnodes_end() const { return AllNodes.end(); }

using allnodes_iterator = ilist<SDNode>::iterator;

allnodes_iterator allnodes_begin() { return AllNodes.begin(); }
allnodes_iterator allnodes_end() { return AllNodes.end(); }

ilist<SDNode>::size_type allnodes_size() const {
  return AllNodes.size();
}

iterator_range<allnodes_iterator> allnodes() {
  return make_range(allnodes_begin(), allnodes_end());
}
iterator_range<allnodes_const_iterator> allnodes() const {
  return make_range(allnodes_begin(), allnodes_end());
}

/// Return the root tag of the SelectionDAG.
const SDValue &getRoot() const { return Root; }

/// Return the token chain corresponding to the entry of the function.
SDValue getEntryNode() const {
  return SDValue(const_cast<SDNode *>(&EntryNode), 0);
}

/// Set the current root tag of the SelectionDAG.
///
const SDValue &setRoot(SDValue N) {
  assert((!N.getNode() || N.getValueType() == MVT::Other) &&(static_cast <bool> ((!N.getNode() || N.getValueType() ==
 MVT::Other) && "DAG root value is not a chain!") ? void
 (0) : __assert_fail ("(!N.getNode() || N.getValueType() == MVT::Other) && \"DAG root value is not a chain!\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/include/llvm/CodeGen/SelectionDAG.h"
, 524, __extension__ __PRETTY_FUNCTION__))
         "DAG root value is not a chain!")(static_cast <bool> ((!N.getNode() || N.getValueType() ==
 MVT::Other) && "DAG root value is not a chain!") ? void
 (0) : __assert_fail ("(!N.getNode() || N.getValueType() == MVT::Other) && \"DAG root value is not a chain!\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/include/llvm/CodeGen/SelectionDAG.h"
, 524, __extension__ __PRETTY_FUNCTION__));
  if (N.getNode())
    checkForCycles(N.getNode(), this);
  Root = N;
  if (N.getNode())
    checkForCycles(this);
  return Root;
}

533#ifndef NDEBUG
void VerifyDAGDiverence();
535#endif

/// This iterates over the nodes in the SelectionDAG, folding
/// certain types of nodes together, or eliminating superfluous nodes.  The
/// Level argument controls whether Combine is allowed to produce nodes and
/// types that are illegal on the target.
void Combine(CombineLevel Level, AAResults *AA,
             CodeGenOpt::Level OptLevel);

/// This transforms the SelectionDAG into a SelectionDAG that
/// only uses types natively supported by the target.
/// Returns "true" if it made any changes.
///
/// Note that this is an involved process that may invalidate pointers into
/// the graph.
bool LegalizeTypes();

/// This transforms the SelectionDAG into a SelectionDAG that is
/// compatible with the target instruction selector, as indicated by the
/// TargetLowering object.
///
/// Note that this is an involved process that may invalidate pointers into
/// the graph.
void Legalize();

/// Transforms a SelectionDAG node and any operands to it into a node
/// that is compatible with the target instruction selector, as indicated by
/// the TargetLowering object.
///
/// \returns true if \c N is a valid, legal node after calling this.
///
/// This essentially runs a single recursive walk of the \c Legalize process
/// over the given node (and its operands). This can be used to incrementally
/// legalize the DAG. All of the nodes which are directly replaced,
/// potentially including N, are added to the output parameter \c
/// UpdatedNodes so that the delta to the DAG can be understood by the
/// caller.
///
/// When this returns false, N has been legalized in a way that make the
/// pointer passed in no longer valid. It may have even been deleted from the
/// DAG, and so it shouldn't be used further. When this returns true, the
/// N passed in is a legal node, and can be immediately processed as such.
/// This may still have done some work on the DAG, and will still populate
/// UpdatedNodes with any new nodes replacing those originally in the DAG.
bool LegalizeOp(SDNode *N, SmallSetVector<SDNode *, 16> &UpdatedNodes);

/// This transforms the SelectionDAG into a SelectionDAG
/// that only uses vector math operations supported by the target.  This is
/// necessary as a separate step from Legalize because unrolling a vector
/// operation can introduce illegal types, which requires running
/// LegalizeTypes again.
///
/// This returns true if it made any changes; in that case, LegalizeTypes
/// is called again before Legalize.
///
/// Note that this is an involved process that may invalidate pointers into
/// the graph.
bool LegalizeVectors();

/// This method deletes all unreachable nodes in the SelectionDAG.
void RemoveDeadNodes();

/// Remove the specified node from the system.  This node must
/// have no referrers.
void DeleteNode(SDNode *N);

/// Return an SDVTList that represents the list of values specified.
SDVTList getVTList(EVT VT);
SDVTList getVTList(EVT VT1, EVT VT2);
SDVTList getVTList(EVT VT1, EVT VT2, EVT VT3);
SDVTList getVTList(EVT VT1, EVT VT2, EVT VT3, EVT VT4);
SDVTList getVTList(ArrayRef<EVT> VTs);

//===--------------------------------------------------------------------===//
// Node creation methods.

/// Create a ConstantSDNode wrapping a constant value.
/// If VT is a vector type, the constant is splatted into a BUILD_VECTOR.
///
/// If only legal types can be produced, this does the necessary
/// transformations (e.g., if the vector element type is illegal).
/// @{
SDValue getConstant(uint64_t Val, const SDLoc &DL, EVT VT,
                    bool isTarget = false, bool isOpaque = false);
SDValue getConstant(const APInt &Val, const SDLoc &DL, EVT VT,
                    bool isTarget = false, bool isOpaque = false);

SDValue getAllOnesConstant(const SDLoc &DL, EVT VT, bool IsTarget = false,
                           bool IsOpaque = false) {
  return getConstant(APInt::getAllOnesValue(VT.getScalarSizeInBits()), DL,
                     VT, IsTarget, IsOpaque);
}

SDValue getConstant(const ConstantInt &Val, const SDLoc &DL, EVT VT,
                    bool isTarget = false, bool isOpaque = false);
SDValue getIntPtrConstant(uint64_t Val, const SDLoc &DL,
                          bool isTarget = false);
SDValue getShiftAmountConstant(uint64_t Val, EVT VT, const SDLoc &DL,
                               bool LegalTypes = true);
SDValue getVectorIdxConstant(uint64_t Val, const SDLoc &DL,
                             bool isTarget = false);

SDValue getTargetConstant(uint64_t Val, const SDLoc &DL, EVT VT,
                          bool isOpaque = false) {
  return getConstant(Val, DL, VT, true, isOpaque);
}
SDValue getTargetConstant(const APInt &Val, const SDLoc &DL, EVT VT,
                          bool isOpaque = false) {
  return getConstant(Val, DL, VT, true, isOpaque);
}
SDValue getTargetConstant(const ConstantInt &Val, const SDLoc &DL, EVT VT,
                          bool isOpaque = false) {
  return getConstant(Val, DL, VT, true, isOpaque);
}

/// Create a true or false constant of type \p VT using the target's
/// BooleanContent for type \p OpVT.
SDValue getBoolConstant(bool V, const SDLoc &DL, EVT VT, EVT OpVT);
/// @}

/// Create a ConstantFPSDNode wrapping a constant value.
/// If VT is a vector type, the constant is splatted into a BUILD_VECTOR.
///
/// If only legal types can be produced, this does the necessary
/// transformations (e.g., if the vector element type is illegal).
/// The forms that take a double should only be used for simple constants
/// that can be exactly represented in VT.  No checks are made.
/// @{
SDValue getConstantFP(double Val, const SDLoc &DL, EVT VT,
                      bool isTarget = false);
SDValue getConstantFP(const APFloat &Val, const SDLoc &DL, EVT VT,
                      bool isTarget = false);
SDValue getConstantFP(const ConstantFP &V, const SDLoc &DL, EVT VT,
                      bool isTarget = false);
SDValue getTargetConstantFP(double Val, const SDLoc &DL, EVT VT) {
  return getConstantFP(Val, DL, VT, true);
}
SDValue getTargetConstantFP(const APFloat &Val, const SDLoc &DL, EVT VT) {
  return getConstantFP(Val, DL, VT, true);
}
SDValue getTargetConstantFP(const ConstantFP &Val, const SDLoc &DL, EVT VT) {
  return getConstantFP(Val, DL, VT, true);
}
/// @}

SDValue getGlobalAddress(const GlobalValue *GV, const SDLoc &DL, EVT VT,
                         int64_t offset = 0, bool isTargetGA = false,
                         unsigned TargetFlags = 0);
SDValue getTargetGlobalAddress(const GlobalValue *GV, const SDLoc &DL, EVT VT,
                               int64_t offset = 0, unsigned TargetFlags = 0) {
  return getGlobalAddress(GV, DL, VT, offset, true, TargetFlags);
}
SDValue getFrameIndex(int FI, EVT VT, bool isTarget = false);
SDValue getTargetFrameIndex(int FI, EVT VT) {
  return getFrameIndex(FI, VT, true);
}
SDValue getJumpTable(int JTI, EVT VT, bool isTarget = false,
                     unsigned TargetFlags = 0);
SDValue getTargetJumpTable(int JTI, EVT VT, unsigned TargetFlags = 0) {
  return getJumpTable(JTI, VT, true, TargetFlags);
}
SDValue getConstantPool(const Constant *C, EVT VT, MaybeAlign Align = None,
                        int Offs = 0, bool isT = false,
                        unsigned TargetFlags = 0);
SDValue getTargetConstantPool(const Constant *C, EVT VT,
                              MaybeAlign Align = None, int Offset = 0,
                              unsigned TargetFlags = 0) {
  return getConstantPool(C, VT, Align, Offset, true, TargetFlags);
}
SDValue getConstantPool(MachineConstantPoolValue *C, EVT VT,
                        MaybeAlign Align = None, int Offs = 0,
                        bool isT = false, unsigned TargetFlags = 0);
SDValue getTargetConstantPool(MachineConstantPoolValue *C, EVT VT,
                              MaybeAlign Align = None, int Offset = 0,
                              unsigned TargetFlags = 0) {
  return getConstantPool(C, VT, Align, Offset, true, TargetFlags);
}
SDValue getTargetIndex(int Index, EVT VT, int64_t Offset = 0,
                       unsigned TargetFlags = 0);
// When generating a branch to a BB, we don't in general know enough
// to provide debug info for the BB at that time, so keep this one around.
SDValue getBasicBlock(MachineBasicBlock *MBB);
SDValue getExternalSymbol(const char *Sym, EVT VT);
SDValue getTargetExternalSymbol(const char *Sym, EVT VT,
                                unsigned TargetFlags = 0);
SDValue getMCSymbol(MCSymbol *Sym, EVT VT);

SDValue getValueType(EVT);
SDValue getRegister(unsigned Reg, EVT VT);
SDValue getRegisterMask(const uint32_t *RegMask);
SDValue getEHLabel(const SDLoc &dl, SDValue Root, MCSymbol *Label);
SDValue getLabelNode(unsigned Opcode, const SDLoc &dl, SDValue Root,
                     MCSymbol *Label);
SDValue getBlockAddress(const BlockAddress *BA, EVT VT, int64_t Offset = 0,
                        bool isTarget = false, unsigned TargetFlags = 0);
SDValue getTargetBlockAddress(const BlockAddress *BA, EVT VT,
                              int64_t Offset = 0, unsigned TargetFlags = 0) {
  return getBlockAddress(BA, VT, Offset, true, TargetFlags);
}

SDValue getCopyToReg(SDValue Chain, const SDLoc &dl, unsigned Reg,
                     SDValue N) {
  return getNode(ISD::CopyToReg, dl, MVT::Other, Chain,
                 getRegister(Reg, N.getValueType()), N);
}

// This version of the getCopyToReg method takes an extra operand, which
// indicates that there is potentially an incoming glue value (if Glue is not
// null) and that there should be a glue result.
SDValue getCopyToReg(SDValue Chain, const SDLoc &dl, unsigned Reg, SDValue N,
                     SDValue Glue) {
  SDVTList VTs = getVTList(MVT::Other, MVT::Glue);
  SDValue Ops[] = { Chain, getRegister(Reg, N.getValueType()), N, Glue };
14
←
Calling 'SDValue::getValueType'→
  return getNode(ISD::CopyToReg, dl, VTs,
                 makeArrayRef(Ops, Glue.getNode() ? 4 : 3));
}

// Similar to last getCopyToReg() except parameter Reg is a SDValue
SDValue getCopyToReg(SDValue Chain, const SDLoc &dl, SDValue Reg, SDValue N,
                     SDValue Glue) {
  SDVTList VTs = getVTList(MVT::Other, MVT::Glue);
  SDValue Ops[] = { Chain, Reg, N, Glue };
  return getNode(ISD::CopyToReg, dl, VTs,
                 makeArrayRef(Ops, Glue.getNode() ? 4 : 3));
}

SDValue getCopyFromReg(SDValue Chain, const SDLoc &dl, unsigned Reg, EVT VT) {
  SDVTList VTs = getVTList(VT, MVT::Other);
  SDValue Ops[] = { Chain, getRegister(Reg, VT) };
  return getNode(ISD::CopyFromReg, dl, VTs, Ops);
}

// This version of the getCopyFromReg method takes an extra operand, which
// indicates that there is potentially an incoming glue value (if Glue is not
// null) and that there should be a glue result.
SDValue getCopyFromReg(SDValue Chain, const SDLoc &dl, unsigned Reg, EVT VT,
                       SDValue Glue) {
  SDVTList VTs = getVTList(VT, MVT::Other, MVT::Glue);
  SDValue Ops[] = { Chain, getRegister(Reg, VT), Glue };
  return getNode(ISD::CopyFromReg, dl, VTs,
                 makeArrayRef(Ops, Glue.getNode() ? 3 : 2));
}

SDValue getCondCode(ISD::CondCode Cond);

/// Return an ISD::VECTOR_SHUFFLE node. The number of elements in VT,
/// which must be a vector type, must match the number of mask elements
/// NumElts. An integer mask element equal to -1 is treated as undefined.
SDValue getVectorShuffle(EVT VT, const SDLoc &dl, SDValue N1, SDValue N2,
                         ArrayRef<int> Mask);

/// Return an ISD::BUILD_VECTOR node. The number of elements in VT,
/// which must be a vector type, must match the number of operands in Ops.
/// The operands must have the same type as (or, for integers, a type wider
/// than) VT's element type.
SDValue getBuildVector(EVT VT, const SDLoc &DL, ArrayRef<SDValue> Ops) {
  // VerifySDNode (via InsertNode) checks BUILD_VECTOR later.
  return getNode(ISD::BUILD_VECTOR, DL, VT, Ops);
}

/// Return an ISD::BUILD_VECTOR node. The number of elements in VT,
/// which must be a vector type, must match the number of operands in Ops.
/// The operands must have the same type as (or, for integers, a type wider
/// than) VT's element type.
SDValue getBuildVector(EVT VT, const SDLoc &DL, ArrayRef<SDUse> Ops) {
  // VerifySDNode (via InsertNode) checks BUILD_VECTOR later.
  return getNode(ISD::BUILD_VECTOR, DL, VT, Ops);
}

/// Return a splat ISD::BUILD_VECTOR node, consisting of Op splatted to all
/// elements. VT must be a vector type. Op's type must be the same as (or,
/// for integers, a type wider than) VT's element type.
SDValue getSplatBuildVector(EVT VT, const SDLoc &DL, SDValue Op) {
  // VerifySDNode (via InsertNode) checks BUILD_VECTOR later.
  if (Op.getOpcode() == ISD::UNDEF) {
    assert((VT.getVectorElementType() == Op.getValueType() ||(static_cast <bool> ((VT.getVectorElementType() == Op.getValueType
() || (VT.isInteger() && VT.getVectorElementType().bitsLE
(Op.getValueType()))) && "A splatted value must have a width equal or (for integers) "
 "greater than the vector element type!") ? void (0) : __assert_fail
 ("(VT.getVectorElementType() == Op.getValueType() || (VT.isInteger() && VT.getVectorElementType().bitsLE(Op.getValueType()))) && \"A splatted value must have a width equal or (for integers) \" \"greater than the vector element type!\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/include/llvm/CodeGen/SelectionDAG.h"
, 814, __extension__ __PRETTY_FUNCTION__))
            (VT.isInteger() &&(static_cast <bool> ((VT.getVectorElementType() == Op.getValueType
() || (VT.isInteger() && VT.getVectorElementType().bitsLE
(Op.getValueType()))) && "A splatted value must have a width equal or (for integers) "
 "greater than the vector element type!") ? void (0) : __assert_fail
 ("(VT.getVectorElementType() == Op.getValueType() || (VT.isInteger() && VT.getVectorElementType().bitsLE(Op.getValueType()))) && \"A splatted value must have a width equal or (for integers) \" \"greater than the vector element type!\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/include/llvm/CodeGen/SelectionDAG.h"
, 814, __extension__ __PRETTY_FUNCTION__))
             VT.getVectorElementType().bitsLE(Op.getValueType()))) &&(static_cast <bool> ((VT.getVectorElementType() == Op.getValueType
() || (VT.isInteger() && VT.getVectorElementType().bitsLE
(Op.getValueType()))) && "A splatted value must have a width equal or (for integers) "
 "greater than the vector element type!") ? void (0) : __assert_fail
 ("(VT.getVectorElementType() == Op.getValueType() || (VT.isInteger() && VT.getVectorElementType().bitsLE(Op.getValueType()))) && \"A splatted value must have a width equal or (for integers) \" \"greater than the vector element type!\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/include/llvm/CodeGen/SelectionDAG.h"
, 814, __extension__ __PRETTY_FUNCTION__))
           "A splatted value must have a width equal or (for integers) "(static_cast <bool> ((VT.getVectorElementType() == Op.getValueType
() || (VT.isInteger() && VT.getVectorElementType().bitsLE
(Op.getValueType()))) && "A splatted value must have a width equal or (for integers) "
 "greater than the vector element type!") ? void (0) : __assert_fail
 ("(VT.getVectorElementType() == Op.getValueType() || (VT.isInteger() && VT.getVectorElementType().bitsLE(Op.getValueType()))) && \"A splatted value must have a width equal or (for integers) \" \"greater than the vector element type!\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/include/llvm/CodeGen/SelectionDAG.h"
, 814, __extension__ __PRETTY_FUNCTION__))
           "greater than the vector element type!")(static_cast <bool> ((VT.getVectorElementType() == Op.getValueType
() || (VT.isInteger() && VT.getVectorElementType().bitsLE
(Op.getValueType()))) && "A splatted value must have a width equal or (for integers) "
 "greater than the vector element type!") ? void (0) : __assert_fail
 ("(VT.getVectorElementType() == Op.getValueType() || (VT.isInteger() && VT.getVectorElementType().bitsLE(Op.getValueType()))) && \"A splatted value must have a width equal or (for integers) \" \"greater than the vector element type!\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/include/llvm/CodeGen/SelectionDAG.h"
, 814, __extension__ __PRETTY_FUNCTION__));
    return getNode(ISD::UNDEF, SDLoc(), VT);
  }

  SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Op);
  return getNode(ISD::BUILD_VECTOR, DL, VT, Ops);
}

// Return a splat ISD::SPLAT_VECTOR node, consisting of Op splatted to all
// elements.
SDValue getSplatVector(EVT VT, const SDLoc &DL, SDValue Op) {
  if (Op.getOpcode() == ISD::UNDEF) {
    assert((VT.getVectorElementType() == Op.getValueType() ||(static_cast <bool> ((VT.getVectorElementType() == Op.getValueType
() || (VT.isInteger() && VT.getVectorElementType().bitsLE
(Op.getValueType()))) && "A splatted value must have a width equal or (for integers) "
 "greater than the vector element type!") ? void (0) : __assert_fail
 ("(VT.getVectorElementType() == Op.getValueType() || (VT.isInteger() && VT.getVectorElementType().bitsLE(Op.getValueType()))) && \"A splatted value must have a width equal or (for integers) \" \"greater than the vector element type!\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/include/llvm/CodeGen/SelectionDAG.h"
, 830, __extension__ __PRETTY_FUNCTION__))
            (VT.isInteger() &&(static_cast <bool> ((VT.getVectorElementType() == Op.getValueType
() || (VT.isInteger() && VT.getVectorElementType().bitsLE
(Op.getValueType()))) && "A splatted value must have a width equal or (for integers) "
 "greater than the vector element type!") ? void (0) : __assert_fail
 ("(VT.getVectorElementType() == Op.getValueType() || (VT.isInteger() && VT.getVectorElementType().bitsLE(Op.getValueType()))) && \"A splatted value must have a width equal or (for integers) \" \"greater than the vector element type!\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/include/llvm/CodeGen/SelectionDAG.h"
, 830, __extension__ __PRETTY_FUNCTION__))
             VT.getVectorElementType().bitsLE(Op.getValueType()))) &&(static_cast <bool> ((VT.getVectorElementType() == Op.getValueType
() || (VT.isInteger() && VT.getVectorElementType().bitsLE
(Op.getValueType()))) && "A splatted value must have a width equal or (for integers) "
 "greater than the vector element type!") ? void (0) : __assert_fail
 ("(VT.getVectorElementType() == Op.getValueType() || (VT.isInteger() && VT.getVectorElementType().bitsLE(Op.getValueType()))) && \"A splatted value must have a width equal or (for integers) \" \"greater than the vector element type!\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/include/llvm/CodeGen/SelectionDAG.h"
, 830, __extension__ __PRETTY_FUNCTION__))
           "A splatted value must have a width equal or (for integers) "(static_cast <bool> ((VT.getVectorElementType() == Op.getValueType
() || (VT.isInteger() && VT.getVectorElementType().bitsLE
(Op.getValueType()))) && "A splatted value must have a width equal or (for integers) "
 "greater than the vector element type!") ? void (0) : __assert_fail
 ("(VT.getVectorElementType() == Op.getValueType() || (VT.isInteger() && VT.getVectorElementType().bitsLE(Op.getValueType()))) && \"A splatted value must have a width equal or (for integers) \" \"greater than the vector element type!\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/include/llvm/CodeGen/SelectionDAG.h"
, 830, __extension__ __PRETTY_FUNCTION__))
           "greater than the vector element type!")(static_cast <bool> ((VT.getVectorElementType() == Op.getValueType
() || (VT.isInteger() && VT.getVectorElementType().bitsLE
(Op.getValueType()))) && "A splatted value must have a width equal or (for integers) "
 "greater than the vector element type!") ? void (0) : __assert_fail
 ("(VT.getVectorElementType() == Op.getValueType() || (VT.isInteger() && VT.getVectorElementType().bitsLE(Op.getValueType()))) && \"A splatted value must have a width equal or (for integers) \" \"greater than the vector element type!\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/include/llvm/CodeGen/SelectionDAG.h"
, 830, __extension__ __PRETTY_FUNCTION__));
    return getNode(ISD::UNDEF, SDLoc(), VT);
  }
  return getNode(ISD::SPLAT_VECTOR, DL, VT, Op);
}

/// Returns a vector of type ResVT whose elements contain the linear sequence
///   <0, Step, Step * 2, Step * 3, ...>
SDValue getStepVector(const SDLoc &DL, EVT ResVT, APInt StepVal);

/// Returns a vector of type ResVT whose elements contain the linear sequence
///   <0, 1, 2, 3, ...>
SDValue getStepVector(const SDLoc &DL, EVT ResVT);

/// Returns an ISD::VECTOR_SHUFFLE node semantically equivalent to
/// the shuffle node in input but with swapped operands.
///
/// Example: shuffle A, B, <0,5,2,7> -> shuffle B, A, <4,1,6,3>
SDValue getCommutedVectorShuffle(const ShuffleVectorSDNode &SV);

/// Convert Op, which must be of float type, to the
/// float type VT, by either extending or rounding (by truncation).
SDValue getFPExtendOrRound(SDValue Op, const SDLoc &DL, EVT VT);

/// Convert Op, which must be a STRICT operation of float type, to the
/// float type VT, by either extending or rounding (by truncation).
std::pair<SDValue, SDValue>
getStrictFPExtendOrRound(SDValue Op, SDValue Chain, const SDLoc &DL, EVT VT);

/// Convert Op, which must be of integer type, to the
/// integer type VT, by either any-extending or truncating it.
SDValue getAnyExtOrTrunc(SDValue Op, const SDLoc &DL, EVT VT);

/// Convert Op, which must be of integer type, to the
/// integer type VT, by either sign-extending or truncating it.
SDValue getSExtOrTrunc(SDValue Op, const SDLoc &DL, EVT VT);

/// Convert Op, which must be of integer type, to the
/// integer type VT, by either zero-extending or truncating it.
SDValue getZExtOrTrunc(SDValue Op, const SDLoc &DL, EVT VT);

/// Return the expression required to zero extend the Op
/// value assuming it was the smaller SrcTy value.
SDValue getZeroExtendInReg(SDValue Op, const SDLoc &DL, EVT VT);

/// Convert Op, which must be of integer type, to the integer type VT, by
/// either truncating it or performing either zero or sign extension as
/// appropriate extension for the pointer's semantics.
SDValue getPtrExtOrTrunc(SDValue Op, const SDLoc &DL, EVT VT);

/// Return the expression required to extend the Op as a pointer value
/// assuming it was the smaller SrcTy value. This may be either a zero extend
/// or a sign extend.
SDValue getPtrExtendInReg(SDValue Op, const SDLoc &DL, EVT VT);

/// Convert Op, which must be of integer type, to the integer type VT,
/// by using an extension appropriate for the target's
/// BooleanContent for type OpVT or truncating it.
SDValue getBoolExtOrTrunc(SDValue Op, const SDLoc &SL, EVT VT, EVT OpVT);

/// Create a bitwise NOT operation as (XOR Val, -1).
SDValue getNOT(const SDLoc &DL, SDValue Val, EVT VT);

/// Create a logical NOT operation as (XOR Val, BooleanOne).
SDValue getLogicalNOT(const SDLoc &DL, SDValue Val, EVT VT);

/// Returns sum of the base pointer and offset.
/// Unlike getObjectPtrOffset this does not set NoUnsignedWrap by default.
SDValue getMemBasePlusOffset(SDValue Base, TypeSize Offset, const SDLoc &DL,
                             const SDNodeFlags Flags = SDNodeFlags());
SDValue getMemBasePlusOffset(SDValue Base, SDValue Offset, const SDLoc &DL,
                             const SDNodeFlags Flags = SDNodeFlags());

/// Create an add instruction with appropriate flags when used for
/// addressing some offset of an object. i.e. if a load is split into multiple
/// components, create an add nuw from the base pointer to the offset.
SDValue getObjectPtrOffset(const SDLoc &SL, SDValue Ptr, TypeSize Offset) {
  SDNodeFlags Flags;
  Flags.setNoUnsignedWrap(true);
  return getMemBasePlusOffset(Ptr, Offset, SL, Flags);
}

SDValue getObjectPtrOffset(const SDLoc &SL, SDValue Ptr, SDValue Offset) {
  // The object itself can't wrap around the address space, so it shouldn't be
  // possible for the adds of the offsets to the split parts to overflow.
  SDNodeFlags Flags;
  Flags.setNoUnsignedWrap(true);
  return getMemBasePlusOffset(Ptr, Offset, SL, Flags);
}

/// Return a new CALLSEQ_START node, that starts new call frame, in which
/// InSize bytes are set up inside CALLSEQ_START..CALLSEQ_END sequence and
/// OutSize specifies part of the frame set up prior to the sequence.
SDValue getCALLSEQ_START(SDValue Chain, uint64_t InSize, uint64_t OutSize,
                         const SDLoc &DL) {
  SDVTList VTs = getVTList(MVT::Other, MVT::Glue);
  SDValue Ops[] = { Chain,
                    getIntPtrConstant(InSize, DL, true),
                    getIntPtrConstant(OutSize, DL, true) };
  return getNode(ISD::CALLSEQ_START, DL, VTs, Ops);
}

/// Return a new CALLSEQ_END node, which always must have a
/// glue result (to ensure it's not CSE'd).
/// CALLSEQ_END does not have a useful SDLoc.
SDValue getCALLSEQ_END(SDValue Chain, SDValue Op1, SDValue Op2,
                       SDValue InGlue, const SDLoc &DL) {
  SDVTList NodeTys = getVTList(MVT::Other, MVT::Glue);
  SmallVector<SDValue, 4> Ops;
  Ops.push_back(Chain);
  Ops.push_back(Op1);
  Ops.push_back(Op2);
  if (InGlue.getNode())
    Ops.push_back(InGlue);
  return getNode(ISD::CALLSEQ_END, DL, NodeTys, Ops);
}

/// Return true if the result of this operation is always undefined.
bool isUndef(unsigned Opcode, ArrayRef<SDValue> Ops);

/// Return an UNDEF node. UNDEF does not have a useful SDLoc.
SDValue getUNDEF(EVT VT) {
  return getNode(ISD::UNDEF, SDLoc(), VT);
}

/// Return a node that represents the runtime scaling 'MulImm * RuntimeVL'.
SDValue getVScale(const SDLoc &DL, EVT VT, APInt MulImm) {
  assert(MulImm.getMinSignedBits() <= VT.getSizeInBits() &&(static_cast <bool> (MulImm.getMinSignedBits() <= VT
.getSizeInBits() && "Immediate does not fit VT") ? void
 (0) : __assert_fail ("MulImm.getMinSignedBits() <= VT.getSizeInBits() && \"Immediate does not fit VT\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/include/llvm/CodeGen/SelectionDAG.h"
, 958, __extension__ __PRETTY_FUNCTION__))
         "Immediate does not fit VT")(static_cast <bool> (MulImm.getMinSignedBits() <= VT
.getSizeInBits() && "Immediate does not fit VT") ? void
 (0) : __assert_fail ("MulImm.getMinSignedBits() <= VT.getSizeInBits() && \"Immediate does not fit VT\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/include/llvm/CodeGen/SelectionDAG.h"
, 958, __extension__ __PRETTY_FUNCTION__));
  return getNode(ISD::VSCALE, DL, VT,
                 getConstant(MulImm.sextOrTrunc(VT.getSizeInBits()), DL, VT));
}

/// Return a GLOBAL_OFFSET_TABLE node. This does not have a useful SDLoc.
SDValue getGLOBAL_OFFSET_TABLE(EVT VT) {
  return getNode(ISD::GLOBAL_OFFSET_TABLE, SDLoc(), VT);
}

/// Gets or creates the specified node.
///
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
                ArrayRef<SDUse> Ops);
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
                ArrayRef<SDValue> Ops, const SDNodeFlags Flags);
SDValue getNode(unsigned Opcode, const SDLoc &DL, ArrayRef<EVT> ResultTys,
                ArrayRef<SDValue> Ops);
SDValue getNode(unsigned Opcode, const SDLoc &DL, SDVTList VTList,
                ArrayRef<SDValue> Ops, const SDNodeFlags Flags);

// Use flags from current flag inserter.
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
                ArrayRef<SDValue> Ops);
SDValue getNode(unsigned Opcode, const SDLoc &DL, SDVTList VTList,
                ArrayRef<SDValue> Ops);
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, SDValue Operand);
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, SDValue N1,
                SDValue N2);
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, SDValue N1,
                SDValue N2, SDValue N3);

// Specialize based on number of operands.
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT);
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, SDValue Operand,
                const SDNodeFlags Flags);
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, SDValue N1,
                SDValue N2, const SDNodeFlags Flags);
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, SDValue N1,
                SDValue N2, SDValue N3, const SDNodeFlags Flags);
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, SDValue N1,
                SDValue N2, SDValue N3, SDValue N4);
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, SDValue N1,
                SDValue N2, SDValue N3, SDValue N4, SDValue N5);

// Specialize again based on number of operands for nodes with a VTList
// rather than a single VT.
SDValue getNode(unsigned Opcode, const SDLoc &DL, SDVTList VTList);
SDValue getNode(unsigned Opcode, const SDLoc &DL, SDVTList VTList, SDValue N);
SDValue getNode(unsigned Opcode, const SDLoc &DL, SDVTList VTList, SDValue N1,
                SDValue N2);
SDValue getNode(unsigned Opcode, const SDLoc &DL, SDVTList VTList, SDValue N1,
                SDValue N2, SDValue N3);
SDValue getNode(unsigned Opcode, const SDLoc &DL, SDVTList VTList, SDValue N1,
                SDValue N2, SDValue N3, SDValue N4);
SDValue getNode(unsigned Opcode, const SDLoc &DL, SDVTList VTList, SDValue N1,
                SDValue N2, SDValue N3, SDValue N4, SDValue N5);

/// Compute a TokenFactor to force all the incoming stack arguments to be
/// loaded from the stack. This is used in tail call lowering to protect
/// stack arguments from being clobbered.
SDValue getStackArgumentTokenFactor(SDValue Chain);

SDValue getMemcpy(SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src,
                  SDValue Size, Align Alignment, bool isVol,
                  bool AlwaysInline, bool isTailCall,
                  MachinePointerInfo DstPtrInfo,
                  MachinePointerInfo SrcPtrInfo,
                  const AAMDNodes &AAInfo = AAMDNodes());

SDValue getMemmove(SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src,
                   SDValue Size, Align Alignment, bool isVol, bool isTailCall,
                   MachinePointerInfo DstPtrInfo,
                   MachinePointerInfo SrcPtrInfo,
                   const AAMDNodes &AAInfo = AAMDNodes());

SDValue getMemset(SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src,
                  SDValue Size, Align Alignment, bool isVol, bool isTailCall,
                  MachinePointerInfo DstPtrInfo,
                  const AAMDNodes &AAInfo = AAMDNodes());

SDValue getAtomicMemcpy(SDValue Chain, const SDLoc &dl, SDValue Dst,
                        unsigned DstAlign, SDValue Src, unsigned SrcAlign,
                        SDValue Size, Type *SizeTy, unsigned ElemSz,
                        bool isTailCall, MachinePointerInfo DstPtrInfo,
                        MachinePointerInfo SrcPtrInfo);

SDValue getAtomicMemmove(SDValue Chain, const SDLoc &dl, SDValue Dst,
                         unsigned DstAlign, SDValue Src, unsigned SrcAlign,
                         SDValue Size, Type *SizeTy, unsigned ElemSz,
                         bool isTailCall, MachinePointerInfo DstPtrInfo,
                         MachinePointerInfo SrcPtrInfo);

SDValue getAtomicMemset(SDValue Chain, const SDLoc &dl, SDValue Dst,
                        unsigned DstAlign, SDValue Value, SDValue Size,
                        Type *SizeTy, unsigned ElemSz, bool isTailCall,
                        MachinePointerInfo DstPtrInfo);

/// Helper function to make it easier to build SetCC's if you just have an
/// ISD::CondCode instead of an SDValue.
SDValue getSetCC(const SDLoc &DL, EVT VT, SDValue LHS, SDValue RHS,
                 ISD::CondCode Cond, SDValue Chain = SDValue(),
                 bool IsSignaling = false) {
  assert(LHS.getValueType().isVector() == RHS.getValueType().isVector() &&(static_cast <bool> (LHS.getValueType().isVector() == RHS
.getValueType().isVector() && "Cannot compare scalars to vectors"
) ? void (0) : __assert_fail ("LHS.getValueType().isVector() == RHS.getValueType().isVector() && \"Cannot compare scalars to vectors\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/include/llvm/CodeGen/SelectionDAG.h"
, 1062, __extension__ __PRETTY_FUNCTION__))
         "Cannot compare scalars to vectors")(static_cast <bool> (LHS.getValueType().isVector() == RHS
.getValueType().isVector() && "Cannot compare scalars to vectors"
) ? void (0) : __assert_fail ("LHS.getValueType().isVector() == RHS.getValueType().isVector() && \"Cannot compare scalars to vectors\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/include/llvm/CodeGen/SelectionDAG.h"
, 1062, __extension__ __PRETTY_FUNCTION__));
  assert(LHS.getValueType().isVector() == VT.isVector() &&(static_cast <bool> (LHS.getValueType().isVector() == VT
.isVector() && "Cannot compare scalars to vectors") ?
 void (0) : __assert_fail ("LHS.getValueType().isVector() == VT.isVector() && \"Cannot compare scalars to vectors\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/include/llvm/CodeGen/SelectionDAG.h"
, 1064, __extension__ __PRETTY_FUNCTION__))
         "Cannot compare scalars to vectors")(static_cast <bool> (LHS.getValueType().isVector() == VT
.isVector() && "Cannot compare scalars to vectors") ?
 void (0) : __assert_fail ("LHS.getValueType().isVector() == VT.isVector() && \"Cannot compare scalars to vectors\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/include/llvm/CodeGen/SelectionDAG.h"
, 1064, __extension__ __PRETTY_FUNCTION__));
  assert(Cond != ISD::SETCC_INVALID &&(static_cast <bool> (Cond != ISD::SETCC_INVALID &&
 "Cannot create a setCC of an invalid node.") ? void (0) : __assert_fail
 ("Cond != ISD::SETCC_INVALID && \"Cannot create a setCC of an invalid node.\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/include/llvm/CodeGen/SelectionDAG.h"
, 1066, __extension__ __PRETTY_FUNCTION__))
         "Cannot create a setCC of an invalid node.")(static_cast <bool> (Cond != ISD::SETCC_INVALID &&
 "Cannot create a setCC of an invalid node.") ? void (0) : __assert_fail
 ("Cond != ISD::SETCC_INVALID && \"Cannot create a setCC of an invalid node.\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/include/llvm/CodeGen/SelectionDAG.h"
, 1066, __extension__ __PRETTY_FUNCTION__));
  if (Chain)
    return getNode(IsSignaling ? ISD::STRICT_FSETCCS : ISD::STRICT_FSETCC, DL,
                   {VT, MVT::Other}, {Chain, LHS, RHS, getCondCode(Cond)});
  return getNode(ISD::SETCC, DL, VT, LHS, RHS, getCondCode(Cond));
}

/// Helper function to make it easier to build Select's if you just have
/// operands and don't want to check for vector.
SDValue getSelect(const SDLoc &DL, EVT VT, SDValue Cond, SDValue LHS,
                  SDValue RHS) {
  assert(LHS.getValueType() == RHS.getValueType() &&(static_cast <bool> (LHS.getValueType() == RHS.getValueType
() && "Cannot use select on differing types") ? void (
0) : __assert_fail ("LHS.getValueType() == RHS.getValueType() && \"Cannot use select on differing types\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/include/llvm/CodeGen/SelectionDAG.h"
, 1078, __extension__ __PRETTY_FUNCTION__))
         "Cannot use select on differing types")(static_cast <bool> (LHS.getValueType() == RHS.getValueType
() && "Cannot use select on differing types") ? void (
0) : __assert_fail ("LHS.getValueType() == RHS.getValueType() && \"Cannot use select on differing types\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/include/llvm/CodeGen/SelectionDAG.h"
, 1078, __extension__ __PRETTY_FUNCTION__));
  assert(VT.isVector() == LHS.getValueType().isVector() &&(static_cast <bool> (VT.isVector() == LHS.getValueType(
).isVector() && "Cannot mix vectors and scalars") ? void
 (0) : __assert_fail ("VT.isVector() == LHS.getValueType().isVector() && \"Cannot mix vectors and scalars\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/include/llvm/CodeGen/SelectionDAG.h"
, 1080, __extension__ __PRETTY_FUNCTION__))
         "Cannot mix vectors and scalars")(static_cast <bool> (VT.isVector() == LHS.getValueType(
).isVector() && "Cannot mix vectors and scalars") ? void
 (0) : __assert_fail ("VT.isVector() == LHS.getValueType().isVector() && \"Cannot mix vectors and scalars\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/include/llvm/CodeGen/SelectionDAG.h"
, 1080, __extension__ __PRETTY_FUNCTION__));
  auto Opcode = Cond.getValueType().isVector() ? ISD::VSELECT : ISD::SELECT;
  return getNode(Opcode, DL, VT, Cond, LHS, RHS);
}

/// Helper function to make it easier to build SelectCC's if you just have an
/// ISD::CondCode instead of an SDValue.
SDValue getSelectCC(const SDLoc &DL, SDValue LHS, SDValue RHS, SDValue True,
                    SDValue False, ISD::CondCode Cond) {
  return getNode(ISD::SELECT_CC, DL, True.getValueType(), LHS, RHS, True,
                 False, getCondCode(Cond));
}

/// Try to simplify a select/vselect into 1 of its operands or a constant.
SDValue simplifySelect(SDValue Cond, SDValue TVal, SDValue FVal);

/// Try to simplify a shift into 1 of its operands or a constant.
SDValue simplifyShift(SDValue X, SDValue Y);

/// Try to simplify a floating-point binary operation into 1 of its operands
/// or a constant.
SDValue simplifyFPBinop(unsigned Opcode, SDValue X, SDValue Y,
                        SDNodeFlags Flags);

/// VAArg produces a result and token chain, and takes a pointer
/// and a source value as input.
SDValue getVAArg(EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr,
                 SDValue SV, unsigned Align);

/// Gets a node for an atomic cmpxchg op. There are two
/// valid Opcodes. ISD::ATOMIC_CMO_SWAP produces the value loaded and a
/// chain result. ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS produces the value loaded,
/// a success flag (initially i1), and a chain.
SDValue getAtomicCmpSwap(unsigned Opcode, const SDLoc &dl, EVT MemVT,
                         SDVTList VTs, SDValue Chain, SDValue Ptr,
                         SDValue Cmp, SDValue Swp, MachineMemOperand *MMO);

/// Gets a node for an atomic op, produces result (if relevant)
/// and chain and takes 2 operands.
SDValue getAtomic(unsigned Opcode, const SDLoc &dl, EVT MemVT, SDValue Chain,
                  SDValue Ptr, SDValue Val, MachineMemOperand *MMO);

/// Gets a node for an atomic op, produces result and chain and
/// takes 1 operand.
SDValue getAtomic(unsigned Opcode, const SDLoc &dl, EVT MemVT, EVT VT,
                  SDValue Chain, SDValue Ptr, MachineMemOperand *MMO);

/// Gets a node for an atomic op, produces result and chain and takes N
/// operands.
SDValue getAtomic(unsigned Opcode, const SDLoc &dl, EVT MemVT,
                  SDVTList VTList, ArrayRef<SDValue> Ops,
                  MachineMemOperand *MMO);

/// Creates a MemIntrinsicNode that may produce a
/// result and takes a list of operands. Opcode may be INTRINSIC_VOID,
/// INTRINSIC_W_CHAIN, or a target-specific opcode with a value not
/// less than FIRST_TARGET_MEMORY_OPCODE.
SDValue getMemIntrinsicNode(
    unsigned Opcode, const SDLoc &dl, SDVTList VTList, ArrayRef<SDValue> Ops,
    EVT MemVT, MachinePointerInfo PtrInfo, Align Alignment,
    MachineMemOperand::Flags Flags = MachineMemOperand::MOLoad |
                                     MachineMemOperand::MOStore,
    uint64_t Size = 0, const AAMDNodes &AAInfo = AAMDNodes());

inline SDValue getMemIntrinsicNode(
    unsigned Opcode, const SDLoc &dl, SDVTList VTList, ArrayRef<SDValue> Ops,
    EVT MemVT, MachinePointerInfo PtrInfo, MaybeAlign Alignment = None,
    MachineMemOperand::Flags Flags = MachineMemOperand::MOLoad |
                                     MachineMemOperand::MOStore,
    uint64_t Size = 0, const AAMDNodes &AAInfo = AAMDNodes()) {
  // Ensure that codegen never sees alignment 0
  return getMemIntrinsicNode(Opcode, dl, VTList, Ops, MemVT, PtrInfo,
                             Alignment.getValueOr(getEVTAlign(MemVT)), Flags,
                             Size, AAInfo);
}

SDValue getMemIntrinsicNode(unsigned Opcode, const SDLoc &dl, SDVTList VTList,
                            ArrayRef<SDValue> Ops, EVT MemVT,
                            MachineMemOperand *MMO);

/// Creates a LifetimeSDNode that starts (`IsStart==true`) or ends
/// (`IsStart==false`) the lifetime of the portion of `FrameIndex` between
/// offsets `Offset` and `Offset + Size`.
SDValue getLifetimeNode(bool IsStart, const SDLoc &dl, SDValue Chain,
                        int FrameIndex, int64_t Size, int64_t Offset = -1);

/// Creates a PseudoProbeSDNode with function GUID `Guid` and
/// the index of the block `Index` it is probing, as well as the attributes
/// `attr` of the probe.
SDValue getPseudoProbeNode(const SDLoc &Dl, SDValue Chain, uint64_t Guid,
                           uint64_t Index, uint32_t Attr);

/// Create a MERGE_VALUES node from the given operands.
SDValue getMergeValues(ArrayRef<SDValue> Ops, const SDLoc &dl);

/// Loads are not normal binary operators: their result type is not
/// determined by their operands, and they produce a value AND a token chain.
///
/// This function will set the MOLoad flag on MMOFlags, but you can set it if
/// you want.  The MOStore flag must not be set.
SDValue getLoad(EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr,
                MachinePointerInfo PtrInfo,
                MaybeAlign Alignment = MaybeAlign(),
                MachineMemOperand::Flags MMOFlags = MachineMemOperand::MONone,
                const AAMDNodes &AAInfo = AAMDNodes(),
                const MDNode *Ranges = nullptr);
/// FIXME: Remove once transition to Align is over.
inline SDValue
getLoad(EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr,
        MachinePointerInfo PtrInfo, unsigned Alignment,
        MachineMemOperand::Flags MMOFlags = MachineMemOperand::MONone,
        const AAMDNodes &AAInfo = AAMDNodes(),
        const MDNode *Ranges = nullptr) {
  return getLoad(VT, dl, Chain, Ptr, PtrInfo, MaybeAlign(Alignment), MMOFlags,
                 AAInfo, Ranges);
}
SDValue getLoad(EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr,
                MachineMemOperand *MMO);
SDValue
getExtLoad(ISD::LoadExtType ExtType, const SDLoc &dl, EVT VT, SDValue Chain,
           SDValue Ptr, MachinePointerInfo PtrInfo, EVT MemVT,
           MaybeAlign Alignment = MaybeAlign(),
           MachineMemOperand::Flags MMOFlags = MachineMemOperand::MONone,
           const AAMDNodes &AAInfo = AAMDNodes());
/// FIXME: Remove once transition to Align is over.
inline SDValue
getExtLoad(ISD::LoadExtType ExtType, const SDLoc &dl, EVT VT, SDValue Chain,
           SDValue Ptr, MachinePointerInfo PtrInfo, EVT MemVT,
           unsigned Alignment,
           MachineMemOperand::Flags MMOFlags = MachineMemOperand::MONone,
           const AAMDNodes &AAInfo = AAMDNodes()) {
  return getExtLoad(ExtType, dl, VT, Chain, Ptr, PtrInfo, MemVT,
                    MaybeAlign(Alignment), MMOFlags, AAInfo);
}
SDValue getExtLoad(ISD::LoadExtType ExtType, const SDLoc &dl, EVT VT,
                   SDValue Chain, SDValue Ptr, EVT MemVT,
                   MachineMemOperand *MMO);
SDValue getIndexedLoad(SDValue OrigLoad, const SDLoc &dl, SDValue Base,
                       SDValue Offset, ISD::MemIndexedMode AM);
SDValue getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType, EVT VT,
                const SDLoc &dl, SDValue Chain, SDValue Ptr, SDValue Offset,
                MachinePointerInfo PtrInfo, EVT MemVT, Align Alignment,
                MachineMemOperand::Flags MMOFlags = MachineMemOperand::MONone,
                const AAMDNodes &AAInfo = AAMDNodes(),
                const MDNode *Ranges = nullptr);
inline SDValue getLoad(
    ISD::MemIndexedMode AM, ISD::LoadExtType ExtType, EVT VT, const SDLoc &dl,
    SDValue Chain, SDValue Ptr, SDValue Offset, MachinePointerInfo PtrInfo,
    EVT MemVT, MaybeAlign Alignment = MaybeAlign(),
    MachineMemOperand::Flags MMOFlags = MachineMemOperand::MONone,
    const AAMDNodes &AAInfo = AAMDNodes(), const MDNode *Ranges = nullptr) {
  // Ensures that codegen never sees a None Alignment.
  return getLoad(AM, ExtType, VT, dl, Chain, Ptr, Offset, PtrInfo, MemVT,
                 Alignment.getValueOr(getEVTAlign(MemVT)), MMOFlags, AAInfo,
                 Ranges);
}
/// FIXME: Remove once transition to Align is over.
inline SDValue
getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType, EVT VT,
        const SDLoc &dl, SDValue Chain, SDValue Ptr, SDValue Offset,
        MachinePointerInfo PtrInfo, EVT MemVT, unsigned Alignment,
        MachineMemOperand::Flags MMOFlags = MachineMemOperand::MONone,
        const AAMDNodes &AAInfo = AAMDNodes(),
        const MDNode *Ranges = nullptr) {
  return getLoad(AM, ExtType, VT, dl, Chain, Ptr, Offset, PtrInfo, MemVT,
                 MaybeAlign(Alignment), MMOFlags, AAInfo, Ranges);
}
SDValue getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType, EVT VT,
                const SDLoc &dl, SDValue Chain, SDValue Ptr, SDValue Offset,
                EVT MemVT, MachineMemOperand *MMO);

/// Helper function to build ISD::STORE nodes.
///
/// This function will set the MOStore flag on MMOFlags, but you can set it if
/// you want.  The MOLoad and MOInvariant flags must not be set.

SDValue
getStore(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr,
         MachinePointerInfo PtrInfo, Align Alignment,
         MachineMemOperand::Flags MMOFlags = MachineMemOperand::MONone,
         const AAMDNodes &AAInfo = AAMDNodes());
inline SDValue
getStore(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr,
         MachinePointerInfo PtrInfo, MaybeAlign Alignment = MaybeAlign(),
         MachineMemOperand::Flags MMOFlags = MachineMemOperand::MONone,
         const AAMDNodes &AAInfo = AAMDNodes()) {
  return getStore(Chain, dl, Val, Ptr, PtrInfo,
                  Alignment.getValueOr(getEVTAlign(Val.getValueType())),
                  MMOFlags, AAInfo);
}
/// FIXME: Remove once transition to Align is over.
inline SDValue
getStore(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr,
         MachinePointerInfo PtrInfo, unsigned Alignment,
         MachineMemOperand::Flags MMOFlags = MachineMemOperand::MONone,
         const AAMDNodes &AAInfo = AAMDNodes()) {
  return getStore(Chain, dl, Val, Ptr, PtrInfo, MaybeAlign(Alignment),
                  MMOFlags, AAInfo);
}
SDValue getStore(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr,
                 MachineMemOperand *MMO);
SDValue
getTruncStore(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr,
              MachinePointerInfo PtrInfo, EVT SVT, Align Alignment,
              MachineMemOperand::Flags MMOFlags = MachineMemOperand::MONone,
              const AAMDNodes &AAInfo = AAMDNodes());
inline SDValue
getTruncStore(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr,
              MachinePointerInfo PtrInfo, EVT SVT,
              MaybeAlign Alignment = MaybeAlign(),
              MachineMemOperand::Flags MMOFlags = MachineMemOperand::MONone,
              const AAMDNodes &AAInfo = AAMDNodes()) {
  return getTruncStore(Chain, dl, Val, Ptr, PtrInfo, SVT,
                       Alignment.getValueOr(getEVTAlign(SVT)), MMOFlags,
                       AAInfo);
}
/// FIXME: Remove once transition to Align is over.
inline SDValue
getTruncStore(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr,
              MachinePointerInfo PtrInfo, EVT SVT, unsigned Alignment,
              MachineMemOperand::Flags MMOFlags = MachineMemOperand::MONone,
              const AAMDNodes &AAInfo = AAMDNodes()) {
  return getTruncStore(Chain, dl, Val, Ptr, PtrInfo, SVT,
                       MaybeAlign(Alignment), MMOFlags, AAInfo);
}
SDValue getTruncStore(SDValue Chain, const SDLoc &dl, SDValue Val,
                      SDValue Ptr, EVT SVT, MachineMemOperand *MMO);
SDValue getIndexedStore(SDValue OrigStore, const SDLoc &dl, SDValue Base,
                        SDValue Offset, ISD::MemIndexedMode AM);

SDValue getMaskedLoad(EVT VT, const SDLoc &dl, SDValue Chain, SDValue Base,
                      SDValue Offset, SDValue Mask, SDValue Src0, EVT MemVT,
                      MachineMemOperand *MMO, ISD::MemIndexedMode AM,
                      ISD::LoadExtType, bool IsExpanding = false);
SDValue getIndexedMaskedLoad(SDValue OrigLoad, const SDLoc &dl, SDValue Base,
                             SDValue Offset, ISD::MemIndexedMode AM);
SDValue getMaskedStore(SDValue Chain, const SDLoc &dl, SDValue Val,
                       SDValue Base, SDValue Offset, SDValue Mask, EVT MemVT,
                       MachineMemOperand *MMO, ISD::MemIndexedMode AM,
                       bool IsTruncating = false, bool IsCompressing = false);
SDValue getIndexedMaskedStore(SDValue OrigStore, const SDLoc &dl,
                              SDValue Base, SDValue Offset,
                              ISD::MemIndexedMode AM);
SDValue getMaskedGather(SDVTList VTs, EVT MemVT, const SDLoc &dl,
                        ArrayRef<SDValue> Ops, MachineMemOperand *MMO,
                        ISD::MemIndexType IndexType, ISD::LoadExtType ExtTy);
SDValue getMaskedScatter(SDVTList VTs, EVT MemVT, const SDLoc &dl,
                         ArrayRef<SDValue> Ops, MachineMemOperand *MMO,
                         ISD::MemIndexType IndexType,
                         bool IsTruncating = false);

/// Construct a node to track a Value* through the backend.
SDValue getSrcValue(const Value *v);

/// Return an MDNodeSDNode which holds an MDNode.
SDValue getMDNode(const MDNode *MD);

/// Return a bitcast using the SDLoc of the value operand, and casting to the
/// provided type. Use getNode to set a custom SDLoc.
SDValue getBitcast(EVT VT, SDValue V);

/// Return an AddrSpaceCastSDNode.
SDValue getAddrSpaceCast(const SDLoc &dl, EVT VT, SDValue Ptr, unsigned SrcAS,
                         unsigned DestAS);

/// Return a freeze using the SDLoc of the value operand.
SDValue getFreeze(SDValue V);

/// Return an AssertAlignSDNode.
SDValue getAssertAlign(const SDLoc &DL, SDValue V, Align A);

/// Return the specified value casted to
/// the target's desired shift amount type.
SDValue getShiftAmountOperand(EVT LHSTy, SDValue Op);

/// Expand the specified \c ISD::VAARG node as the Legalize pass would.
SDValue expandVAArg(SDNode *Node);

/// Expand the specified \c ISD::VACOPY node as the Legalize pass would.
SDValue expandVACopy(SDNode *Node);

/// Returs an GlobalAddress of the function from the current module with
/// name matching the given ExternalSymbol. Additionally can provide the
/// matched function.
/// Panics the function doesn't exists.
SDValue getSymbolFunctionGlobalAddress(SDValue Op,
                                       Function **TargetFunction = nullptr);

/// *Mutate* the specified node in-place to have the
/// specified operands.  If the resultant node already exists in the DAG,
/// this does not modify the specified node, instead it returns the node that
/// already exists.  If the resultant node does not exist in the DAG, the
/// input node is returned.  As a degenerate case, if you specify the same
/// input operands as the node already has, the input node is returned.
SDNode *UpdateNodeOperands(SDNode *N, SDValue Op);
SDNode *UpdateNodeOperands(SDNode *N, SDValue Op1, SDValue Op2);
SDNode *UpdateNodeOperands(SDNode *N, SDValue Op1, SDValue Op2,
                             SDValue Op3);
SDNode *UpdateNodeOperands(SDNode *N, SDValue Op1, SDValue Op2,
                             SDValue Op3, SDValue Op4);
SDNode *UpdateNodeOperands(SDNode *N, SDValue Op1, SDValue Op2,
                             SDValue Op3, SDValue Op4, SDValue Op5);
SDNode *UpdateNodeOperands(SDNode *N, ArrayRef<SDValue> Ops);

/// Creates a new TokenFactor containing \p Vals. If \p Vals contains 64k
/// values or more, move values into new TokenFactors in 64k-1 blocks, until
/// the final TokenFactor has less than 64k operands.
SDValue getTokenFactor(const SDLoc &DL, SmallVectorImpl<SDValue> &Vals);

/// *Mutate* the specified machine node's memory references to the provided
/// list.
void setNodeMemRefs(MachineSDNode *N,
                    ArrayRef<MachineMemOperand *> NewMemRefs);

// Calculate divergence of node \p N based on its operands.
bool calculateDivergence(SDNode *N);

// Propagates the change in divergence to users
void updateDivergence(SDNode * N);

/// These are used for target selectors to *mutate* the
/// specified node to have the specified return type, Target opcode, and
/// operands.  Note that target opcodes are stored as
/// ~TargetOpcode in the node opcode field.  The resultant node is returned.
SDNode *SelectNodeTo(SDNode *N, unsigned MachineOpc, EVT VT);
SDNode *SelectNodeTo(SDNode *N, unsigned MachineOpc, EVT VT, SDValue Op1);
SDNode *SelectNodeTo(SDNode *N, unsigned MachineOpc, EVT VT,
                     SDValue Op1, SDValue Op2);
SDNode *SelectNodeTo(SDNode *N, unsigned MachineOpc, EVT VT,
                     SDValue Op1, SDValue Op2, SDValue Op3);
SDNode *SelectNodeTo(SDNode *N, unsigned MachineOpc, EVT VT,
                     ArrayRef<SDValue> Ops);
SDNode *SelectNodeTo(SDNode *N, unsigned MachineOpc, EVT VT1, EVT VT2);
SDNode *SelectNodeTo(SDNode *N, unsigned MachineOpc, EVT VT1,
                     EVT VT2, ArrayRef<SDValue> Ops);
SDNode *SelectNodeTo(SDNode *N, unsigned MachineOpc, EVT VT1,
                     EVT VT2, EVT VT3, ArrayRef<SDValue> Ops);
SDNode *SelectNodeTo(SDNode *N, unsigned MachineOpc, EVT VT1,
                     EVT VT2, SDValue Op1, SDValue Op2);
SDNode *SelectNodeTo(SDNode *N, unsigned MachineOpc, SDVTList VTs,
                     ArrayRef<SDValue> Ops);

/// This *mutates* the specified node to have the specified
/// return type, opcode, and operands.
SDNode *MorphNodeTo(SDNode *N, unsigned Opc, SDVTList VTs,
                    ArrayRef<SDValue> Ops);

/// Mutate the specified strict FP node to its non-strict equivalent,
/// unlinking the node from its chain and dropping the metadata arguments.
/// The node must be a strict FP node.
SDNode *mutateStrictFPToFP(SDNode *Node);

/// These are used for target selectors to create a new node
/// with specified return type(s), MachineInstr opcode, and operands.
///
/// Note that getMachineNode returns the resultant node.  If there is already
/// a node of the specified opcode and operands, it returns that node instead
/// of the current one.
MachineSDNode *getMachineNode(unsigned Opcode, const SDLoc &dl, EVT VT);
MachineSDNode *getMachineNode(unsigned Opcode, const SDLoc &dl, EVT VT,
                              SDValue Op1);
MachineSDNode *getMachineNode(unsigned Opcode, const SDLoc &dl, EVT VT,
                              SDValue Op1, SDValue Op2);
MachineSDNode *getMachineNode(unsigned Opcode, const SDLoc &dl, EVT VT,
                              SDValue Op1, SDValue Op2, SDValue Op3);
MachineSDNode *getMachineNode(unsigned Opcode, const SDLoc &dl, EVT VT,
                              ArrayRef<SDValue> Ops);
MachineSDNode *getMachineNode(unsigned Opcode, const SDLoc &dl, EVT VT1,
                              EVT VT2, SDValue Op1, SDValue Op2);
MachineSDNode *getMachineNode(unsigned Opcode, const SDLoc &dl, EVT VT1,
                              EVT VT2, SDValue Op1, SDValue Op2, SDValue Op3);
MachineSDNode *getMachineNode(unsigned Opcode, const SDLoc &dl, EVT VT1,
                              EVT VT2, ArrayRef<SDValue> Ops);
MachineSDNode *getMachineNode(unsigned Opcode, const SDLoc &dl, EVT VT1,
                              EVT VT2, EVT VT3, SDValue Op1, SDValue Op2);
MachineSDNode *getMachineNode(unsigned Opcode, const SDLoc &dl, EVT VT1,
                              EVT VT2, EVT VT3, SDValue Op1, SDValue Op2,
                              SDValue Op3);
MachineSDNode *getMachineNode(unsigned Opcode, const SDLoc &dl, EVT VT1,
                              EVT VT2, EVT VT3, ArrayRef<SDValue> Ops);
MachineSDNode *getMachineNode(unsigned Opcode, const SDLoc &dl,
                              ArrayRef<EVT> ResultTys, ArrayRef<SDValue> Ops);
MachineSDNode *getMachineNode(unsigned Opcode, const SDLoc &dl, SDVTList VTs,
                              ArrayRef<SDValue> Ops);

/// A convenience function for creating TargetInstrInfo::EXTRACT_SUBREG nodes.
SDValue getTargetExtractSubreg(int SRIdx, const SDLoc &DL, EVT VT,
                               SDValue Operand);

/// A convenience function for creating TargetInstrInfo::INSERT_SUBREG nodes.
SDValue getTargetInsertSubreg(int SRIdx, const SDLoc &DL, EVT VT,
                              SDValue Operand, SDValue Subreg);

/// Get the specified node if it's already available, or else return NULL.
SDNode *getNodeIfExists(unsigned Opcode, SDVTList VTList,
                        ArrayRef<SDValue> Ops, const SDNodeFlags Flags);
SDNode *getNodeIfExists(unsigned Opcode, SDVTList VTList,
                        ArrayRef<SDValue> Ops);

/// Check if a node exists without modifying its flags.
bool doesNodeExist(unsigned Opcode, SDVTList VTList, ArrayRef<SDValue> Ops);

/// Creates a SDDbgValue node.
SDDbgValue *getDbgValue(DIVariable *Var, DIExpression *Expr, SDNode *N,
                        unsigned R, bool IsIndirect, const DebugLoc &DL,
                        unsigned O);

/// Creates a constant SDDbgValue node.
SDDbgValue *getConstantDbgValue(DIVariable *Var, DIExpression *Expr,
                                const Value *C, const DebugLoc &DL,
                                unsigned O);

/// Creates a FrameIndex SDDbgValue node.
SDDbgValue *getFrameIndexDbgValue(DIVariable *Var, DIExpression *Expr,
                                  unsigned FI, bool IsIndirect,
                                  const DebugLoc &DL, unsigned O);

/// Creates a FrameIndex SDDbgValue node.
SDDbgValue *getFrameIndexDbgValue(DIVariable *Var, DIExpression *Expr,
                                  unsigned FI,
                                  ArrayRef<SDNode *> Dependencies,
                                  bool IsIndirect, const DebugLoc &DL,
                                  unsigned O);

/// Creates a VReg SDDbgValue node.
SDDbgValue *getVRegDbgValue(DIVariable *Var, DIExpression *Expr,
                            unsigned VReg, bool IsIndirect,
                            const DebugLoc &DL, unsigned O);

/// Creates a SDDbgValue node from a list of locations.
SDDbgValue *getDbgValueList(DIVariable *Var, DIExpression *Expr,
                            ArrayRef<SDDbgOperand> Locs,
                            ArrayRef<SDNode *> Dependencies, bool IsIndirect,
                            const DebugLoc &DL, unsigned O, bool IsVariadic);

/// Creates a SDDbgLabel node.
SDDbgLabel *getDbgLabel(DILabel *Label, const DebugLoc &DL, unsigned O);

/// Transfer debug values from one node to another, while optionally
/// generating fragment expressions for split-up values. If \p InvalidateDbg
/// is set, debug values are invalidated after they are transferred.
void transferDbgValues(SDValue From, SDValue To, unsigned OffsetInBits = 0,
                       unsigned SizeInBits = 0, bool InvalidateDbg = true);

/// Remove the specified node from the system. If any of its
/// operands then becomes dead, remove them as well. Inform UpdateListener
/// for each node deleted.
void RemoveDeadNode(SDNode *N);

/// This method deletes the unreachable nodes in the
/// given list, and any nodes that become unreachable as a result.
void RemoveDeadNodes(SmallVectorImpl<SDNode *> &DeadNodes);

/// Modify anything using 'From' to use 'To' instead.
/// This can cause recursive merging of nodes in the DAG.  Use the first
/// version if 'From' is known to have a single result, use the second
/// if you have two nodes with identical results (or if 'To' has a superset
/// of the results of 'From'), use the third otherwise.
///
/// These methods all take an optional UpdateListener, which (if not null) is
/// informed about nodes that are deleted and modified due to recursive
/// changes in the dag.
///
/// These functions only replace all existing uses. It's possible that as
/// these replacements are being performed, CSE may cause the From node
/// to be given new uses. These new uses of From are left in place, and
/// not automatically transferred to To.
///
void ReplaceAllUsesWith(SDValue From, SDValue To);
void ReplaceAllUsesWith(SDNode *From, SDNode *To);
void ReplaceAllUsesWith(SDNode *From, const SDValue *To);

/// Replace any uses of From with To, leaving
/// uses of other values produced by From.getNode() alone.
void ReplaceAllUsesOfValueWith(SDValue From, SDValue To);

/// Like ReplaceAllUsesOfValueWith, but for multiple values at once.
/// This correctly handles the case where
/// there is an overlap between the From values and the To values.
void ReplaceAllUsesOfValuesWith(const SDValue *From, const SDValue *To,
                                unsigned Num);

/// If an existing load has uses of its chain, create a token factor node with
/// that chain and the new memory node's chain and update users of the old
/// chain to the token factor. This ensures that the new memory node will have
/// the same relative memory dependency position as the old load. Returns the
/// new merged load chain.
SDValue makeEquivalentMemoryOrdering(SDValue OldChain, SDValue NewMemOpChain);

/// If an existing load has uses of its chain, create a token factor node with
/// that chain and the new memory node's chain and update users of the old
/// chain to the token factor. This ensures that the new memory node will have
/// the same relative memory dependency position as the old load. Returns the
/// new merged load chain.
SDValue makeEquivalentMemoryOrdering(LoadSDNode *OldLoad, SDValue NewMemOp);

/// Topological-sort the AllNodes list and a
/// assign a unique node id for each node in the DAG based on their
/// topological order. Returns the number of nodes.
unsigned AssignTopologicalOrder();

/// Move node N in the AllNodes list to be immediately
/// before the given iterator Position. This may be used to update the
/// topological ordering when the list of nodes is modified.
void RepositionNode(allnodes_iterator Position, SDNode *N) {
  AllNodes.insert(Position, AllNodes.remove(N));
}

/// Returns an APFloat semantics tag appropriate for the given type. If VT is
/// a vector type, the element semantics are returned.
static const fltSemantics &EVTToAPFloatSemantics(EVT VT) {
  switch (VT.getScalarType().getSimpleVT().SimpleTy) {
  default: llvm_unreachable("Unknown FP format")::llvm::llvm_unreachable_internal("Unknown FP format", "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/include/llvm/CodeGen/SelectionDAG.h"
, 1592);
  case MVT::f16:     return APFloat::IEEEhalf();
  case MVT::bf16:    return APFloat::BFloat();
  case MVT::f32:     return APFloat::IEEEsingle();
  case MVT::f64:     return APFloat::IEEEdouble();
  case MVT::f80:     return APFloat::x87DoubleExtended();
  case MVT::f128:    return APFloat::IEEEquad();
  case MVT::ppcf128: return APFloat::PPCDoubleDouble();
  }
}

/// Add a dbg_value SDNode. If SD is non-null that means the
/// value is produced by SD.
void AddDbgValue(SDDbgValue *DB, bool isParameter);

/// Add a dbg_label SDNode.
void AddDbgLabel(SDDbgLabel *DB);

/// Get the debug values which reference the given SDNode.
ArrayRef<SDDbgValue*> GetDbgValues(const SDNode* SD) const {
  return DbgInfo->getSDDbgValues(SD);
}

1615public:
/// Return true if there are any SDDbgValue nodes associated
/// with this SelectionDAG.
bool hasDebugValues() const { return !DbgInfo->empty(); }

SDDbgInfo::DbgIterator DbgBegin() const { return DbgInfo->DbgBegin(); }
SDDbgInfo::DbgIterator DbgEnd() const  { return DbgInfo->DbgEnd(); }

SDDbgInfo::DbgIterator ByvalParmDbgBegin() const {
  return DbgInfo->ByvalParmDbgBegin();
}
SDDbgInfo::DbgIterator ByvalParmDbgEnd() const {
  return DbgInfo->ByvalParmDbgEnd();
}

SDDbgInfo::DbgLabelIterator DbgLabelBegin() const {
  return DbgInfo->DbgLabelBegin();
}
SDDbgInfo::DbgLabelIterator DbgLabelEnd() const {
  return DbgInfo->DbgLabelEnd();
}

/// To be invoked on an SDNode that is slated to be erased. This
/// function mirrors \c llvm::salvageDebugInfo.
void salvageDebugInfo(SDNode &N);

void dump() const;

/// In most cases this function returns the ABI alignment for a given type,
/// except for illegal vector types where the alignment exceeds that of the
/// stack. In such cases we attempt to break the vector down to a legal type
/// and return the ABI alignment for that instead.
Align getReducedAlign(EVT VT, bool UseABI);

/// Create a stack temporary based on the size in bytes and the alignment
SDValue CreateStackTemporary(TypeSize Bytes, Align Alignment);

/// Create a stack temporary, suitable for holding the specified value type.
/// If minAlign is specified, the slot size will have at least that alignment.
SDValue CreateStackTemporary(EVT VT, unsigned minAlign = 1);

/// Create a stack temporary suitable for holding either of the specified
/// value types.
SDValue CreateStackTemporary(EVT VT1, EVT VT2);

SDValue FoldSymbolOffset(unsigned Opcode, EVT VT,
                         const GlobalAddressSDNode *GA,
                         const SDNode *N2);

SDValue FoldConstantArithmetic(unsigned Opcode, const SDLoc &DL, EVT VT,
                               ArrayRef<SDValue> Ops);

SDValue FoldConstantVectorArithmetic(unsigned Opcode, const SDLoc &DL, EVT VT,
                                     ArrayRef<SDValue> Ops,
                                     const SDNodeFlags Flags = SDNodeFlags());

/// Fold floating-point operations with 2 operands when both operands are
/// constants and/or undefined.
SDValue foldConstantFPMath(unsigned Opcode, const SDLoc &DL, EVT VT,
                           SDValue N1, SDValue N2);

/// Constant fold a setcc to true or false.
SDValue FoldSetCC(EVT VT, SDValue N1, SDValue N2, ISD::CondCode Cond,
                  const SDLoc &dl);

/// See if the specified operand can be simplified with the knowledge that
/// only the bits specified by DemandedBits are used.  If so, return the
/// simpler operand, otherwise return a null SDValue.
///
/// (This exists alongside SimplifyDemandedBits because GetDemandedBits can
/// simplify nodes with multiple uses more aggressively.)
SDValue GetDemandedBits(SDValue V, const APInt &DemandedBits);

/// See if the specified operand can be simplified with the knowledge that
/// only the bits specified by DemandedBits are used in the elements specified
/// by DemandedElts.  If so, return the simpler operand, otherwise return a
/// null SDValue.
///
/// (This exists alongside SimplifyDemandedBits because GetDemandedBits can
/// simplify nodes with multiple uses more aggressively.)
SDValue GetDemandedBits(SDValue V, const APInt &DemandedBits,
                        const APInt &DemandedElts);

/// Return true if the sign bit of Op is known to be zero.
/// We use this predicate to simplify operations downstream.
bool SignBitIsZero(SDValue Op, unsigned Depth = 0) const;

/// Return true if 'Op & Mask' is known to be zero.  We
/// use this predicate to simplify operations downstream.  Op and Mask are
/// known to be the same type.
bool MaskedValueIsZero(SDValue Op, const APInt &Mask,
                       unsigned Depth = 0) const;

/// Return true if 'Op & Mask' is known to be zero in DemandedElts.  We
/// use this predicate to simplify operations downstream.  Op and Mask are
/// known to be the same type.
bool MaskedValueIsZero(SDValue Op, const APInt &Mask,
                       const APInt &DemandedElts, unsigned Depth = 0) const;

/// Return true if '(Op & Mask) == Mask'.
/// Op and Mask are known to be the same type.
bool MaskedValueIsAllOnes(SDValue Op, const APInt &Mask,
                          unsigned Depth = 0) const;

/// Determine which bits of Op are known to be either zero or one and return
/// them in Known. For vectors, the known bits are those that are shared by
/// every vector element.
/// Targets can implement the computeKnownBitsForTargetNode method in the
/// TargetLowering class to allow target nodes to be understood.
KnownBits computeKnownBits(SDValue Op, unsigned Depth = 0) const;

/// Determine which bits of Op are known to be either zero or one and return
/// them in Known. The DemandedElts argument allows us to only collect the
/// known bits that are shared by the requested vector elements.
/// Targets can implement the computeKnownBitsForTargetNode method in the
/// TargetLowering class to allow target nodes to be understood.
KnownBits computeKnownBits(SDValue Op, const APInt &DemandedElts,
                           unsigned Depth = 0) const;

/// Used to represent the possible overflow behavior of an operation.
/// Never: the operation cannot overflow.
/// Always: the operation will always overflow.
/// Sometime: the operation may or may not overflow.
enum OverflowKind {
  OFK_Never,
  OFK_Sometime,
  OFK_Always,
};

/// Determine if the result of the addition of 2 node can overflow.
OverflowKind computeOverflowKind(SDValue N0, SDValue N1) const;

/// Test if the given value is known to have exactly one bit set. This differs
/// from computeKnownBits in that it doesn't necessarily determine which bit
/// is set.
bool isKnownToBeAPowerOfTwo(SDValue Val) const;

/// Return the number of times the sign bit of the register is replicated into
/// the other bits. We know that at least 1 bit is always equal to the sign
/// bit (itself), but other cases can give us information. For example,
/// immediately after an "SRA X, 2", we know that the top 3 bits are all equal
/// to each other, so we return 3. Targets can implement the
/// ComputeNumSignBitsForTarget method in the TargetLowering class to allow
/// target nodes to be understood.
unsigned ComputeNumSignBits(SDValue Op, unsigned Depth = 0) const;

/// Return the number of times the sign bit of the register is replicated into
/// the other bits. We know that at least 1 bit is always equal to the sign
/// bit (itself), but other cases can give us information. For example,
/// immediately after an "SRA X, 2", we know that the top 3 bits are all equal
/// to each other, so we return 3. The DemandedElts argument allows
/// us to only collect the minimum sign bits of the requested vector elements.
/// Targets can implement the ComputeNumSignBitsForTarget method in the
/// TargetLowering class to allow target nodes to be understood.
unsigned ComputeNumSignBits(SDValue Op, const APInt &DemandedElts,
                            unsigned Depth = 0) const;

/// Return true if this function can prove that \p Op is never poison
/// and, if \p PoisonOnly is false, does not have undef bits.
bool isGuaranteedNotToBeUndefOrPoison(SDValue Op, bool PoisonOnly = false,
                                      unsigned Depth = 0) const;

/// Return true if this function can prove that \p Op is never poison
/// and, if \p PoisonOnly is false, does not have undef bits. The DemandedElts
/// argument limits the check to the requested vector elements.
bool isGuaranteedNotToBeUndefOrPoison(SDValue Op, const APInt &DemandedElts,
                                      bool PoisonOnly = false,
                                      unsigned Depth = 0) const;

/// Return true if this function can prove that \p Op is never poison.
bool isGuaranteedNotToBePoison(SDValue Op, unsigned Depth = 0) const {
  return isGuaranteedNotToBeUndefOrPoison(Op, /*PoisonOnly*/ true, Depth);
}

/// Return true if this function can prove that \p Op is never poison. The
/// DemandedElts argument limits the check to the requested vector elements.
bool isGuaranteedNotToBePoison(SDValue Op, const APInt &DemandedElts,
                               unsigned Depth = 0) const {
  return isGuaranteedNotToBeUndefOrPoison(Op, DemandedElts,
                                          /*PoisonOnly*/ true, Depth);
}

/// Return true if the specified operand is an ISD::ADD with a ConstantSDNode
/// on the right-hand side, or if it is an ISD::OR with a ConstantSDNode that
/// is guaranteed to have the same semantics as an ADD. This handles the
/// equivalence:
///     X|Cst == X+Cst iff X&Cst = 0.
bool isBaseWithConstantOffset(SDValue Op) const;

/// Test whether the given SDValue is known to never be NaN. If \p SNaN is
/// true, returns if \p Op is known to never be a signaling NaN (it may still
/// be a qNaN).
bool isKnownNeverNaN(SDValue Op, bool SNaN = false, unsigned Depth = 0) const;

/// \returns true if \p Op is known to never be a signaling NaN.
bool isKnownNeverSNaN(SDValue Op, unsigned Depth = 0) const {
  return isKnownNeverNaN(Op, true, Depth);
}

/// Test whether the given floating point SDValue is known to never be
/// positive or negative zero.
bool isKnownNeverZeroFloat(SDValue Op) const;

/// Test whether the given SDValue is known to contain non-zero value(s).
bool isKnownNeverZero(SDValue Op) const;

/// Test whether two SDValues are known to compare equal. This
/// is true if they are the same value, or if one is negative zero and the
/// other positive zero.
bool isEqualTo(SDValue A, SDValue B) const;

/// Return true if A and B have no common bits set. As an example, this can
/// allow an 'add' to be transformed into an 'or'.
bool haveNoCommonBitsSet(SDValue A, SDValue B) const;

/// Test whether \p V has a splatted value for all the demanded elements.
///
/// On success \p UndefElts will indicate the elements that have UNDEF
/// values instead of the splat value, this is only guaranteed to be correct
/// for \p DemandedElts.
///
/// NOTE: The function will return true for a demanded splat of UNDEF values.
bool isSplatValue(SDValue V, const APInt &DemandedElts, APInt &UndefElts,
                  unsigned Depth = 0);

/// Test whether \p V has a splatted value.
bool isSplatValue(SDValue V, bool AllowUndefs = false);

/// If V is a splatted value, return the source vector and its splat index.
SDValue getSplatSourceVector(SDValue V, int &SplatIndex);

/// If V is a splat vector, return its scalar source operand by extracting
/// that element from the source vector. If LegalTypes is true, this method
/// may only return a legally-typed splat value. If it cannot legalize the
/// splatted value it will return SDValue().
SDValue getSplatValue(SDValue V, bool LegalTypes = false);

/// If a SHL/SRA/SRL node \p V has a constant or splat constant shift amount
/// that is less than the element bit-width of the shift node, return it.
const APInt *getValidShiftAmountConstant(SDValue V,
                                         const APInt &DemandedElts) const;

/// If a SHL/SRA/SRL node \p V has constant shift amounts that are all less
/// than the element bit-width of the shift node, return the minimum value.
const APInt *
getValidMinimumShiftAmountConstant(SDValue V,
                                   const APInt &DemandedElts) const;

/// If a SHL/SRA/SRL node \p V has constant shift amounts that are all less
/// than the element bit-width of the shift node, return the maximum value.
const APInt *
getValidMaximumShiftAmountConstant(SDValue V,
                                   const APInt &DemandedElts) const;

/// Match a binop + shuffle pyramid that represents a horizontal reduction
/// over the elements of a vector starting from the EXTRACT_VECTOR_ELT node /p
/// Extract. The reduction must use one of the opcodes listed in /p
/// CandidateBinOps and on success /p BinOp will contain the matching opcode.
/// Returns the vector that is being reduced on, or SDValue() if a reduction
/// was not matched. If \p AllowPartials is set then in the case of a
/// reduction pattern that only matches the first few stages, the extracted
/// subvector of the start of the reduction is returned.
SDValue matchBinOpReduction(SDNode *Extract, ISD::NodeType &BinOp,
                            ArrayRef<ISD::NodeType> CandidateBinOps,
                            bool AllowPartials = false);

/// Utility function used by legalize and lowering to
/// "unroll" a vector operation by splitting out the scalars and operating
/// on each element individually.  If the ResNE is 0, fully unroll the vector
/// op. If ResNE is less than the width of the vector op, unroll up to ResNE.
/// If the  ResNE is greater than the width of the vector op, unroll the
/// vector op and fill the end of the resulting vector with UNDEFS.
SDValue UnrollVectorOp(SDNode *N, unsigned ResNE = 0);

/// Like UnrollVectorOp(), but for the [US](ADD|SUB|MUL)O family of opcodes.
/// This is a separate function because those opcodes have two results.
std::pair<SDValue, SDValue> UnrollVectorOverflowOp(SDNode *N,
                                                   unsigned ResNE = 0);

/// Return true if loads are next to each other and can be
/// merged. Check that both are nonvolatile and if LD is loading
/// 'Bytes' bytes from a location that is 'Dist' units away from the
/// location that the 'Base' load is loading from.
bool areNonVolatileConsecutiveLoads(LoadSDNode *LD, LoadSDNode *Base,
                                    unsigned Bytes, int Dist) const;

/// Infer alignment of a load / store address. Return None if it cannot be
/// inferred.
MaybeAlign InferPtrAlign(SDValue Ptr) const;

/// Compute the VTs needed for the low/hi parts of a type
/// which is split (or expanded) into two not necessarily identical pieces.
std::pair<EVT, EVT> GetSplitDestVTs(const EVT &VT) const;

/// Compute the VTs needed for the low/hi parts of a type, dependent on an
/// enveloping VT that has been split into two identical pieces. Sets the
/// HisIsEmpty flag when hi type has zero storage size.
std::pair<EVT, EVT> GetDependentSplitDestVTs(const EVT &VT, const EVT &EnvVT,
                                             bool *HiIsEmpty) const;

/// Split the vector with EXTRACT_SUBVECTOR using the provides
/// VTs and return the low/high part.
std::pair<SDValue, SDValue> SplitVector(const SDValue &N, const SDLoc &DL,
                                        const EVT &LoVT, const EVT &HiVT);

/// Split the vector with EXTRACT_SUBVECTOR and return the low/high part.
std::pair<SDValue, SDValue> SplitVector(const SDValue &N, const SDLoc &DL) {
  EVT LoVT, HiVT;
  std::tie(LoVT, HiVT) = GetSplitDestVTs(N.getValueType());
  return SplitVector(N, DL, LoVT, HiVT);
}

/// Split the node's operand with EXTRACT_SUBVECTOR and
/// return the low/high part.
std::pair<SDValue, SDValue> SplitVectorOperand(const SDNode *N, unsigned OpNo)
{
  return SplitVector(N->getOperand(OpNo), SDLoc(N));
}

/// Widen the vector up to the next power of two using INSERT_SUBVECTOR.
SDValue WidenVector(const SDValue &N, const SDLoc &DL);

/// Append the extracted elements from Start to Count out of the vector Op in
/// Args. If Count is 0, all of the elements will be extracted. The extracted
/// elements will have type EVT if it is provided, and otherwise their type
/// will be Op's element type.
void ExtractVectorElements(SDValue Op, SmallVectorImpl<SDValue> &Args,
                           unsigned Start = 0, unsigned Count = 0,
                           EVT EltVT = EVT());

/// Compute the default alignment value for the given type.
Align getEVTAlign(EVT MemoryVT) const;
/// Compute the default alignment value for the given type.
/// FIXME: Remove once transition to Align is over.
inline unsigned getEVTAlignment(EVT MemoryVT) const {
  return getEVTAlign(MemoryVT).value();
}

/// Test whether the given value is a constant int or similar node.
SDNode *isConstantIntBuildVectorOrConstantInt(SDValue N) const;

/// Test whether the given value is a constant FP or similar node.
SDNode *isConstantFPBuildVectorOrConstantFP(SDValue N) const ;

/// \returns true if \p N is any kind of constant or build_vector of
/// constants, int or float. If a vector, it may not necessarily be a splat.
inline bool isConstantValueOfAnyType(SDValue N) const {
  return isConstantIntBuildVectorOrConstantInt(N) ||
         isConstantFPBuildVectorOrConstantFP(N);
}

void addCallSiteInfo(const SDNode *CallNode, CallSiteInfoImpl &&CallInfo) {
  SDCallSiteDbgInfo[CallNode].CSInfo = std::move(CallInfo);
}

CallSiteInfo getSDCallSiteInfo(const SDNode *CallNode) {
  auto I = SDCallSiteDbgInfo.find(CallNode);
  if (I != SDCallSiteDbgInfo.end())
    return std::move(I->second).CSInfo;
  return CallSiteInfo();
}

void addHeapAllocSite(const SDNode *Node, MDNode *MD) {
  SDCallSiteDbgInfo[Node].HeapAllocSite = MD;
}

/// Return the HeapAllocSite type associated with the SDNode, if it exists.
MDNode *getHeapAllocSite(const SDNode *Node) {
  auto It = SDCallSiteDbgInfo.find(Node);
  if (It == SDCallSiteDbgInfo.end())
    return nullptr;
  return It->second.HeapAllocSite;
}

void addNoMergeSiteInfo(const SDNode *Node, bool NoMerge) {
  if (NoMerge)
    SDCallSiteDbgInfo[Node].NoMerge = NoMerge;
}

bool getNoMergeSiteInfo(const SDNode *Node) {
  auto I = SDCallSiteDbgInfo.find(Node);
  if (I == SDCallSiteDbgInfo.end())
    return false;
  return I->second.NoMerge;
}

/// Return the current function's default denormal handling kind for the given
/// floating point type.
DenormalMode getDenormalMode(EVT VT) const {
  return MF->getDenormalMode(EVTToAPFloatSemantics(VT));
}

bool shouldOptForSize() const;

/// Get the (commutative) neutral element for the given opcode, if it exists.
SDValue getNeutralElement(unsigned Opcode, const SDLoc &DL, EVT VT,
                          SDNodeFlags Flags);

2013private:
void InsertNode(SDNode *N);
bool RemoveNodeFromCSEMaps(SDNode *N);
void AddModifiedNodeToCSEMaps(SDNode *N);
SDNode *FindModifiedNodeSlot(SDNode *N, SDValue Op, void *&InsertPos);
SDNode *FindModifiedNodeSlot(SDNode *N, SDValue Op1, SDValue Op2,
                             void *&InsertPos);
SDNode *FindModifiedNodeSlot(SDNode *N, ArrayRef<SDValue> Ops,
                             void *&InsertPos);
SDNode *UpdateSDLocOnMergeSDNode(SDNode *N, const SDLoc &loc);

void DeleteNodeNotInCSEMaps(SDNode *N);
void DeallocateNode(SDNode *N);

void allnodes_clear();

/// Look up the node specified by ID in CSEMap.  If it exists, return it.  If
/// not, return the insertion token that will make insertion faster.  This
/// overload is for nodes other than Constant or ConstantFP, use the other one
/// for those.
SDNode *FindNodeOrInsertPos(const FoldingSetNodeID &ID, void *&InsertPos);

/// Look up the node specified by ID in CSEMap.  If it exists, return it.  If
/// not, return the insertion token that will make insertion faster.  Performs
/// additional processing for constant nodes.
SDNode *FindNodeOrInsertPos(const FoldingSetNodeID &ID, const SDLoc &DL,
                            void *&InsertPos);

/// List of non-single value types.
FoldingSet<SDVTListNode> VTListMap;

/// Maps to auto-CSE operations.
std::vector<CondCodeSDNode*> CondCodeNodes;

std::vector<SDNode*> ValueTypeNodes;
std::map<EVT, SDNode*, EVT::compareRawBits> ExtendedValueTypeNodes;
StringMap<SDNode*> ExternalSymbols;

std::map<std::pair<std::string, unsigned>, SDNode *> TargetExternalSymbols;
DenseMap<MCSymbol *, SDNode *> MCSymbols;

FlagInserter *Inserter = nullptr;
2055};

2057template <> struct GraphTraits<SelectionDAG*> : public GraphTraits<SDNode*> {
using nodes_iterator = pointer_iterator<SelectionDAG::allnodes_iterator>;

static nodes_iterator nodes_begin(SelectionDAG *G) {
  return nodes_iterator(G->allnodes_begin());
}

static nodes_iterator nodes_end(SelectionDAG *G) {
  return nodes_iterator(G->allnodes_end());
}
2067};

2069} // end namespace llvm

2071#endif // LLVM_CODEGEN_SELECTIONDAG_H

←

/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/include/llvm/CodeGen/SelectionDAGNodes.h

1//===- llvm/CodeGen/SelectionDAGNodes.h - SelectionDAG Nodes ----*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file declares the SDNode class and derived classes, which are used to
10// represent the nodes and operations present in a SelectionDAG.  These nodes
11// and operations are machine code level operations, with some similarities to
12// the GCC RTL representation.
13//
14// Clients should include the SelectionDAG.h file instead of this file directly.
15//
16//===----------------------------------------------------------------------===//

18#ifndef LLVM_CODEGEN_SELECTIONDAGNODES_H
19#define LLVM_CODEGEN_SELECTIONDAGNODES_H

21#include "llvm/ADT/APFloat.h"
22#include "llvm/ADT/ArrayRef.h"
23#include "llvm/ADT/BitVector.h"
24#include "llvm/ADT/FoldingSet.h"
25#include "llvm/ADT/GraphTraits.h"
26#include "llvm/ADT/SmallPtrSet.h"
27#include "llvm/ADT/SmallVector.h"
28#include "llvm/ADT/ilist_node.h"
29#include "llvm/ADT/iterator.h"
30#include "llvm/ADT/iterator_range.h"
31#include "llvm/CodeGen/ISDOpcodes.h"
32#include "llvm/CodeGen/MachineMemOperand.h"
33#include "llvm/CodeGen/Register.h"
34#include "llvm/CodeGen/ValueTypes.h"
35#include "llvm/IR/Constants.h"
36#include "llvm/IR/DebugLoc.h"
37#include "llvm/IR/Instruction.h"
38#include "llvm/IR/Instructions.h"
39#include "llvm/IR/Metadata.h"
40#include "llvm/IR/Operator.h"
41#include "llvm/Support/AlignOf.h"
42#include "llvm/Support/AtomicOrdering.h"
43#include "llvm/Support/Casting.h"
44#include "llvm/Support/ErrorHandling.h"
45#include "llvm/Support/MachineValueType.h"
46#include "llvm/Support/TypeSize.h"
47#include <algorithm>
48#include <cassert>
49#include <climits>
50#include <cstddef>
51#include <cstdint>
52#include <cstring>
53#include <iterator>
54#include <string>
55#include <tuple>

57namespace llvm {

59class APInt;
60class Constant;
61template <typename T> struct DenseMapInfo;
62class GlobalValue;
63class MachineBasicBlock;
64class MachineConstantPoolValue;
65class MCSymbol;
66class raw_ostream;
67class SDNode;
68class SelectionDAG;
69class Type;
70class Value;

72void checkForCycles(const SDNode *N, const SelectionDAG *DAG = nullptr,
                  bool force = false);

75/// This represents a list of ValueType's that has been intern'd by
76/// a SelectionDAG.  Instances of this simple value class are returned by
77/// SelectionDAG::getVTList(...).
78///
79struct SDVTList {
const EVT *VTs;
unsigned int NumVTs;
82};

84namespace ISD {

/// Node predicates

88/// If N is a BUILD_VECTOR or SPLAT_VECTOR node whose elements are all the
89/// same constant or undefined, return true and return the constant value in
90/// \p SplatValue.
91bool isConstantSplatVector(const SDNode *N, APInt &SplatValue);

93/// Return true if the specified node is a BUILD_VECTOR or SPLAT_VECTOR where
94/// all of the elements are ~0 or undef. If \p BuildVectorOnly is set to
95/// true, it only checks BUILD_VECTOR.
96bool isConstantSplatVectorAllOnes(const SDNode *N,
                                bool BuildVectorOnly = false);

99/// Return true if the specified node is a BUILD_VECTOR or SPLAT_VECTOR where
100/// all of the elements are 0 or undef. If \p BuildVectorOnly is set to true, it
101/// only checks BUILD_VECTOR.
102bool isConstantSplatVectorAllZeros(const SDNode *N,
                                 bool BuildVectorOnly = false);

105/// Return true if the specified node is a BUILD_VECTOR where all of the
106/// elements are ~0 or undef.
107bool isBuildVectorAllOnes(const SDNode *N);

109/// Return true if the specified node is a BUILD_VECTOR where all of the
110/// elements are 0 or undef.
111bool isBuildVectorAllZeros(const SDNode *N);

113/// Return true if the specified node is a BUILD_VECTOR node of all
114/// ConstantSDNode or undef.
115bool isBuildVectorOfConstantSDNodes(const SDNode *N);

117/// Return true if the specified node is a BUILD_VECTOR node of all
118/// ConstantFPSDNode or undef.
119bool isBuildVectorOfConstantFPSDNodes(const SDNode *N);

121/// Return true if the node has at least one operand and all operands of the
122/// specified node are ISD::UNDEF.
123bool allOperandsUndef(const SDNode *N);

125} // end namespace ISD

127//===----------------------------------------------------------------------===//
128/// Unlike LLVM values, Selection DAG nodes may return multiple
129/// values as the result of a computation.  Many nodes return multiple values,
130/// from loads (which define a token and a return value) to ADDC (which returns
131/// a result and a carry value), to calls (which may return an arbitrary number
132/// of values).
133///
134/// As such, each use of a SelectionDAG computation must indicate the node that
135/// computes it as well as which return value to use from that node.  This pair
136/// of information is represented with the SDValue value type.
137///
138class SDValue {
friend struct DenseMapInfo<SDValue>;

SDNode *Node = nullptr; // The node defining the value we are using.
unsigned ResNo = 0;     // Which return value of the node we are using.

144public:
SDValue() = default;
SDValue(SDNode *node, unsigned resno);

/// get the index which selects a specific result in the SDNode
unsigned getResNo() const { return ResNo; }

/// get the SDNode which holds the desired result
SDNode *getNode() const { return Node; }

/// set the SDNode
void setNode(SDNode *N) { Node = N; }

inline SDNode *operator->() const { return Node; }

bool operator==(const SDValue &O) const {
  return Node == O.Node && ResNo == O.ResNo;
}
bool operator!=(const SDValue &O) const {
  return !operator==(O);
}
bool operator<(const SDValue &O) const {
  return std::tie(Node, ResNo) < std::tie(O.Node, O.ResNo);
}
explicit operator bool() const {
  return Node != nullptr;
}

SDValue getValue(unsigned R) const {
  return SDValue(Node, R);
}

/// Return true if this node is an operand of N.
bool isOperandOf(const SDNode *N) const;

/// Return the ValueType of the referenced return value.
inline EVT getValueType() const;

/// Return the simple ValueType of the referenced return value.
MVT getSimpleValueType() const {
  return getValueType().getSimpleVT();
}

/// Returns the size of the value in bits.
///
/// If the value type is a scalable vector type, the scalable property will
/// be set and the runtime size will be a positive integer multiple of the
/// base size.
TypeSize getValueSizeInBits() const {
  return getValueType().getSizeInBits();
}

uint64_t getScalarValueSizeInBits() const {
  return getValueType().getScalarType().getFixedSizeInBits();
}

// Forwarding methods - These forward to the corresponding methods in SDNode.
inline unsigned getOpcode() const;
inline unsigned getNumOperands() const;
inline const SDValue &getOperand(unsigned i) const;
inline uint64_t getConstantOperandVal(unsigned i) const;
inline const APInt &getConstantOperandAPInt(unsigned i) const;
inline bool isTargetMemoryOpcode() const;
inline bool isTargetOpcode() const;
inline bool isMachineOpcode() const;
inline bool isUndef() const;
inline unsigned getMachineOpcode() const;
inline const DebugLoc &getDebugLoc() const;
inline void dump() const;
inline void dump(const SelectionDAG *G) const;
inline void dumpr() const;
inline void dumpr(const SelectionDAG *G) const;

/// Return true if this operand (which must be a chain) reaches the
/// specified operand without crossing any side-effecting instructions.
/// In practice, this looks through token factors and non-volatile loads.
/// In order to remain efficient, this only
/// looks a couple of nodes in, it does not do an exhaustive search.
bool reachesChainWithoutSideEffects(SDValue Dest,
                                    unsigned Depth = 2) const;

/// Return true if there are no nodes using value ResNo of Node.
inline bool use_empty() const;

/// Return true if there is exactly one node using value ResNo of Node.
inline bool hasOneUse() const;
230};

232template<> struct DenseMapInfo<SDValue> {
static inline SDValue getEmptyKey() {
  SDValue V;
  V.ResNo = -1U;
  return V;
}

static inline SDValue getTombstoneKey() {
  SDValue V;
  V.ResNo = -2U;
  return V;
}

static unsigned getHashValue(const SDValue &Val) {
  return ((unsigned)((uintptr_t)Val.getNode() >> 4) ^
          (unsigned)((uintptr_t)Val.getNode() >> 9)) + Val.getResNo();
}

static bool isEqual(const SDValue &LHS, const SDValue &RHS) {
  return LHS == RHS;
}
253};

255/// Allow casting operators to work directly on
256/// SDValues as if they were SDNode*'s.
257template<> struct simplify_type<SDValue> {
using SimpleType = SDNode *;

static SimpleType getSimplifiedValue(SDValue &Val) {
  return Val.getNode();
}
263};
264template<> struct simplify_type<const SDValue> {
using SimpleType = /*const*/ SDNode *;

static SimpleType getSimplifiedValue(const SDValue &Val) {
  return Val.getNode();
}
270};

272/// Represents a use of a SDNode. This class holds an SDValue,
273/// which records the SDNode being used and the result number, a
274/// pointer to the SDNode using the value, and Next and Prev pointers,
275/// which link together all the uses of an SDNode.
276///
277class SDUse {
/// Val - The value being used.
SDValue Val;
/// User - The user of this value.
SDNode *User = nullptr;
/// Prev, Next - Pointers to the uses list of the SDNode referred by
/// this operand.
SDUse **Prev = nullptr;
SDUse *Next = nullptr;

287public:
SDUse() = default;
SDUse(const SDUse &U) = delete;
SDUse &operator=(const SDUse &) = delete;

/// Normally SDUse will just implicitly convert to an SDValue that it holds.
operator const SDValue&() const { return Val; }

/// If implicit conversion to SDValue doesn't work, the get() method returns
/// the SDValue.
const SDValue &get() const { return Val; }

/// This returns the SDNode that contains this Use.
SDNode *getUser() { return User; }

/// Get the next SDUse in the use list.
SDUse *getNext() const { return Next; }

/// Convenience function for get().getNode().
SDNode *getNode() const { return Val.getNode(); }
/// Convenience function for get().getResNo().
unsigned getResNo() const { return Val.getResNo(); }
/// Convenience function for get().getValueType().
EVT getValueType() const { return Val.getValueType(); }

/// Convenience function for get().operator==
bool operator==(const SDValue &V) const {
  return Val == V;
}

/// Convenience function for get().operator!=
bool operator!=(const SDValue &V) const {
  return Val != V;
}

/// Convenience function for get().operator<
bool operator<(const SDValue &V) const {
  return Val < V;
}

327private:
friend class SelectionDAG;
friend class SDNode;
// TODO: unfriend HandleSDNode once we fix its operand handling.
friend class HandleSDNode;

void setUser(SDNode *p) { User = p; }

/// Remove this use from its existing use list, assign it the
/// given value, and add it to the new value's node's use list.
inline void set(const SDValue &V);
/// Like set, but only supports initializing a newly-allocated
/// SDUse with a non-null value.
inline void setInitial(const SDValue &V);
/// Like set, but only sets the Node portion of the value,
/// leaving the ResNo portion unmodified.
inline void setNode(SDNode *N);

void addToList(SDUse **List) {
  Next = *List;
  if (Next) Next->Prev = &Next;
  Prev = List;
  *List = this;
}

void removeFromList() {
  *Prev = Next;
  if (Next) Next->Prev = Prev;
}
356};

358/// simplify_type specializations - Allow casting operators to work directly on
359/// SDValues as if they were SDNode*'s.
360template<> struct simplify_type<SDUse> {
using SimpleType = SDNode *;

static SimpleType getSimplifiedValue(SDUse &Val) {
  return Val.getNode();
}
366};

368/// These are IR-level optimization flags that may be propagated to SDNodes.
369/// TODO: This data structure should be shared by the IR optimizer and the
370/// the backend.
371struct SDNodeFlags {
372private:
bool NoUnsignedWrap : 1;
bool NoSignedWrap : 1;
bool Exact : 1;
bool NoNaNs : 1;
bool NoInfs : 1;
bool NoSignedZeros : 1;
bool AllowReciprocal : 1;
bool AllowContract : 1;
bool ApproximateFuncs : 1;
bool AllowReassociation : 1;

// We assume instructions do not raise floating-point exceptions by default,
// and only those marked explicitly may do so.  We could choose to represent
// this via a positive "FPExcept" flags like on the MI level, but having a
// negative "NoFPExcept" flag here (that defaults to true) makes the flag
// intersection logic more straightforward.
bool NoFPExcept : 1;

391public:
/// Default constructor turns off all optimization flags.
SDNodeFlags()
    : NoUnsignedWrap(false), NoSignedWrap(false), Exact(false), NoNaNs(false),
      NoInfs(false), NoSignedZeros(false), AllowReciprocal(false),
      AllowContract(false), ApproximateFuncs(false),
      AllowReassociation(false), NoFPExcept(false) {}

/// Propagate the fast-math-flags from an IR FPMathOperator.
void copyFMF(const FPMathOperator &FPMO) {
  setNoNaNs(FPMO.hasNoNaNs());
  setNoInfs(FPMO.hasNoInfs());
  setNoSignedZeros(FPMO.hasNoSignedZeros());
  setAllowReciprocal(FPMO.hasAllowReciprocal());
  setAllowContract(FPMO.hasAllowContract());
  setApproximateFuncs(FPMO.hasApproxFunc());
  setAllowReassociation(FPMO.hasAllowReassoc());
}

// These are mutators for each flag.
void setNoUnsignedWrap(bool b) { NoUnsignedWrap = b; }
void setNoSignedWrap(bool b) { NoSignedWrap = b; }
void setExact(bool b) { Exact = b; }
void setNoNaNs(bool b) { NoNaNs = b; }
void setNoInfs(bool b) { NoInfs = b; }
void setNoSignedZeros(bool b) { NoSignedZeros = b; }
void setAllowReciprocal(bool b) { AllowReciprocal = b; }
void setAllowContract(bool b) { AllowContract = b; }
void setApproximateFuncs(bool b) { ApproximateFuncs = b; }
void setAllowReassociation(bool b) { AllowReassociation = b; }
void setNoFPExcept(bool b) { NoFPExcept = b; }

// These are accessors for each flag.
bool hasNoUnsignedWrap() const { return NoUnsignedWrap; }
bool hasNoSignedWrap() const { return NoSignedWrap; }
bool hasExact() const { return Exact; }
bool hasNoNaNs() const { return NoNaNs; }
bool hasNoInfs() const { return NoInfs; }
bool hasNoSignedZeros() const { return NoSignedZeros; }
bool hasAllowReciprocal() const { return AllowReciprocal; }
bool hasAllowContract() const { return AllowContract; }
bool hasApproximateFuncs() const { return ApproximateFuncs; }
bool hasAllowReassociation() const { return AllowReassociation; }
bool hasNoFPExcept() const { return NoFPExcept; }

/// Clear any flags in this flag set that aren't also set in Flags. All
/// flags will be cleared if Flags are undefined.
void intersectWith(const SDNodeFlags Flags) {
  NoUnsignedWrap &= Flags.NoUnsignedWrap;
  NoSignedWrap &= Flags.NoSignedWrap;
  Exact &= Flags.Exact;
  NoNaNs &= Flags.NoNaNs;
  NoInfs &= Flags.NoInfs;
  NoSignedZeros &= Flags.NoSignedZeros;
  AllowReciprocal &= Flags.AllowReciprocal;
  AllowContract &= Flags.AllowContract;
  ApproximateFuncs &= Flags.ApproximateFuncs;
  AllowReassociation &= Flags.AllowReassociation;
  NoFPExcept &= Flags.NoFPExcept;
}
451};

453/// Represents one node in the SelectionDAG.
454///
455class SDNode : public FoldingSetNode, public ilist_node<SDNode> {
456private:
/// The operation that this node performs.
int16_t NodeType;

460protected:
// We define a set of mini-helper classes to help us interpret the bits in our
// SubclassData.  These are designed to fit within a uint16_t so they pack
// with NodeType.

465#if defined(_AIX) && (!defined(__GNUC__4) || defined(__clang__1))
466// Except for GCC; by default, AIX compilers store bit-fields in 4-byte words
467// and give the `pack` pragma push semantics.
468#define BEGIN_TWO_BYTE_PACK() _Pragma("pack(2)")pack(2)
469#define END_TWO_BYTE_PACK() _Pragma("pack(pop)")pack(pop)
470#else
471#define BEGIN_TWO_BYTE_PACK()
472#define END_TWO_BYTE_PACK()
473#endif

475BEGIN_TWO_BYTE_PACK()
class SDNodeBitfields {
  friend class SDNode;
  friend class MemIntrinsicSDNode;
  friend class MemSDNode;
  friend class SelectionDAG;

  uint16_t HasDebugValue : 1;
  uint16_t IsMemIntrinsic : 1;
  uint16_t IsDivergent : 1;
};
enum { NumSDNodeBits = 3 };

class ConstantSDNodeBitfields {
  friend class ConstantSDNode;

  uint16_t : NumSDNodeBits;

  uint16_t IsOpaque : 1;
};

class MemSDNodeBitfields {
  friend class MemSDNode;
  friend class MemIntrinsicSDNode;
  friend class AtomicSDNode;

  uint16_t : NumSDNodeBits;

  uint16_t IsVolatile : 1;
  uint16_t IsNonTemporal : 1;
  uint16_t IsDereferenceable : 1;
  uint16_t IsInvariant : 1;
};
enum { NumMemSDNodeBits = NumSDNodeBits + 4 };

class LSBaseSDNodeBitfields {
  friend class LSBaseSDNode;
  friend class MaskedLoadStoreSDNode;
  friend class MaskedGatherScatterSDNode;

  uint16_t : NumMemSDNodeBits;

  // This storage is shared between disparate class hierarchies to hold an
  // enumeration specific to the class hierarchy in use.
  //   LSBaseSDNode => enum ISD::MemIndexedMode
  //   MaskedLoadStoreBaseSDNode => enum ISD::MemIndexedMode
  //   MaskedGatherScatterSDNode => enum ISD::MemIndexType
  uint16_t AddressingMode : 3;
};
enum { NumLSBaseSDNodeBits = NumMemSDNodeBits + 3 };

class LoadSDNodeBitfields {
  friend class LoadSDNode;
  friend class MaskedLoadSDNode;
  friend class MaskedGatherSDNode;

  uint16_t : NumLSBaseSDNodeBits;

  uint16_t ExtTy : 2; // enum ISD::LoadExtType
  uint16_t IsExpanding : 1;
};

class StoreSDNodeBitfields {
  friend class StoreSDNode;
  friend class MaskedStoreSDNode;
  friend class MaskedScatterSDNode;

  uint16_t : NumLSBaseSDNodeBits;

  uint16_t IsTruncating : 1;
  uint16_t IsCompressing : 1;
};

union {
  char RawSDNodeBits[sizeof(uint16_t)];
  SDNodeBitfields SDNodeBits;
  ConstantSDNodeBitfields ConstantSDNodeBits;
  MemSDNodeBitfields MemSDNodeBits;
  LSBaseSDNodeBitfields LSBaseSDNodeBits;
  LoadSDNodeBitfields LoadSDNodeBits;
  StoreSDNodeBitfields StoreSDNodeBits;
};
557END_TWO_BYTE_PACK()
558#undef BEGIN_TWO_BYTE_PACK
559#undef END_TWO_BYTE_PACK

// RawSDNodeBits must cover the entirety of the union.  This means that all of
// the union's members must have size <= RawSDNodeBits.  We write the RHS as
// "2" instead of sizeof(RawSDNodeBits) because MSVC can't handle the latter.
static_assert(sizeof(SDNodeBitfields) <= 2, "field too wide");
static_assert(sizeof(ConstantSDNodeBitfields) <= 2, "field too wide");
static_assert(sizeof(MemSDNodeBitfields) <= 2, "field too wide");
static_assert(sizeof(LSBaseSDNodeBitfields) <= 2, "field too wide");
static_assert(sizeof(LoadSDNodeBitfields) <= 2, "field too wide");
static_assert(sizeof(StoreSDNodeBitfields) <= 2, "field too wide");

571private:
friend class SelectionDAG;
// TODO: unfriend HandleSDNode once we fix its operand handling.
friend class HandleSDNode;

/// Unique id per SDNode in the DAG.
int NodeId = -1;

/// The values that are used by this operation.
SDUse *OperandList = nullptr;

/// The types of the values this node defines.  SDNode's may
/// define multiple values simultaneously.
const EVT *ValueList;

/// List of uses for this SDNode.
SDUse *UseList = nullptr;

/// The number of entries in the Operand/Value list.
unsigned short NumOperands = 0;
unsigned short NumValues;

// The ordering of the SDNodes. It roughly corresponds to the ordering of the
// original LLVM instructions.
// This is used for turning off scheduling, because we'll forgo
// the normal scheduling algorithms and output the instructions according to
// this ordering.
unsigned IROrder;

/// Source line information.
DebugLoc debugLoc;

/// Return a pointer to the specified value type.
static const EVT *getValueTypeList(EVT VT);

SDNodeFlags Flags;

608public:
/// Unique and persistent id per SDNode in the DAG.
/// Used for debug printing.
uint16_t PersistentId;

//===--------------------------------------------------------------------===//
//  Accessors
//

/// Return the SelectionDAG opcode value for this node. For
/// pre-isel nodes (those for which isMachineOpcode returns false), these
/// are the opcode values in the ISD and <target>ISD namespaces. For
/// post-isel opcodes, see getMachineOpcode.
unsigned getOpcode()  const { return (unsigned short)NodeType; }

/// Test if this node has a target-specific opcode (in the
/// \<target\>ISD namespace).
bool isTargetOpcode() const { return NodeType >= ISD::BUILTIN_OP_END; }

/// Test if this node has a target-specific opcode that may raise
/// FP exceptions (in the \<target\>ISD namespace and greater than
/// FIRST_TARGET_STRICTFP_OPCODE).  Note that all target memory
/// opcode are currently automatically considered to possibly raise
/// FP exceptions as well.
bool isTargetStrictFPOpcode() const {
  return NodeType >= ISD::FIRST_TARGET_STRICTFP_OPCODE;
}

/// Test if this node has a target-specific
/// memory-referencing opcode (in the \<target\>ISD namespace and
/// greater than FIRST_TARGET_MEMORY_OPCODE).
bool isTargetMemoryOpcode() const {
  return NodeType >= ISD::FIRST_TARGET_MEMORY_OPCODE;
}

/// Return true if the type of the node type undefined.
bool isUndef() const { return NodeType == ISD::UNDEF; }

/// Test if this node is a memory intrinsic (with valid pointer information).
/// INTRINSIC_W_CHAIN and INTRINSIC_VOID nodes are sometimes created for
/// non-memory intrinsics (with chains) that are not really instances of
/// MemSDNode. For such nodes, we need some extra state to determine the
/// proper classof relationship.
bool isMemIntrinsic() const {
  return (NodeType == ISD::INTRINSIC_W_CHAIN ||
          NodeType == ISD::INTRINSIC_VOID) &&
         SDNodeBits.IsMemIntrinsic;
}

/// Test if this node is a strict floating point pseudo-op.
bool isStrictFPOpcode() {
  switch (NodeType) {
    default:
      return false;
    case ISD::STRICT_FP16_TO_FP:
    case ISD::STRICT_FP_TO_FP16:
664#define DAG_INSTRUCTION(NAME, NARG, ROUND_MODE, INTRINSIC, DAGN)               \
    case ISD::STRICT_##DAGN:
666#include "llvm/IR/ConstrainedOps.def"
      return true;
  }
}

/// Test if this node has a post-isel opcode, directly
/// corresponding to a MachineInstr opcode.
bool isMachineOpcode() const { return NodeType < 0; }

/// This may only be called if isMachineOpcode returns
/// true. It returns the MachineInstr opcode value that the node's opcode
/// corresponds to.
unsigned getMachineOpcode() const {
  assert(isMachineOpcode() && "Not a MachineInstr opcode!")(static_cast <bool> (isMachineOpcode() && "Not a MachineInstr opcode!"
) ? void (0) : __assert_fail ("isMachineOpcode() && \"Not a MachineInstr opcode!\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 679, __extension__ __PRETTY_FUNCTION__));
  return ~NodeType;
}

bool getHasDebugValue() const { return SDNodeBits.HasDebugValue; }
void setHasDebugValue(bool b) { SDNodeBits.HasDebugValue = b; }

bool isDivergent() const { return SDNodeBits.IsDivergent; }

/// Return true if there are no uses of this node.
bool use_empty() const { return UseList == nullptr; }

/// Return true if there is exactly one use of this node.
bool hasOneUse() const { return hasSingleElement(uses()); }

/// Return the number of uses of this node. This method takes
/// time proportional to the number of uses.
size_t use_size() const { return std::distance(use_begin(), use_end()); }

/// Return the unique node id.
int getNodeId() const { return NodeId; }

/// Set unique node id.
void setNodeId(int Id) { NodeId = Id; }

/// Return the node ordering.
unsigned getIROrder() const { return IROrder; }

/// Set the node ordering.
void setIROrder(unsigned Order) { IROrder = Order; }

/// Return the source location info.
const DebugLoc &getDebugLoc() const { return debugLoc; }

/// Set source location info.  Try to avoid this, putting
/// it in the constructor is preferable.
void setDebugLoc(DebugLoc dl) { debugLoc = std::move(dl); }

/// This class provides iterator support for SDUse
/// operands that use a specific SDNode.
class use_iterator {
  friend class SDNode;

  SDUse *Op = nullptr;

  explicit use_iterator(SDUse *op) : Op(op) {}

public:
  using iterator_category = std::forward_iterator_tag;
  using value_type = SDUse;
  using difference_type = std::ptrdiff_t;
  using pointer = value_type *;
  using reference = value_type &;

  use_iterator() = default;
  use_iterator(const use_iterator &I) : Op(I.Op) {}

  bool operator==(const use_iterator &x) const {
    return Op == x.Op;
  }
  bool operator!=(const use_iterator &x) const {
    return !operator==(x);
  }

  /// Return true if this iterator is at the end of uses list.
  bool atEnd() const { return Op == nullptr; }

  // Iterator traversal: forward iteration only.
  use_iterator &operator++() {          // Preincrement
    assert(Op && "Cannot increment end iterator!")(static_cast <bool> (Op && "Cannot increment end iterator!"
) ? void (0) : __assert_fail ("Op && \"Cannot increment end iterator!\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 748, __extension__ __PRETTY_FUNCTION__));
    Op = Op->getNext();
    return *this;
  }

  use_iterator operator++(int) {        // Postincrement
    use_iterator tmp = *this; ++*this; return tmp;
  }

  /// Retrieve a pointer to the current user node.
  SDNode *operator*() const {
    assert(Op && "Cannot dereference end iterator!")(static_cast <bool> (Op && "Cannot dereference end iterator!"
) ? void (0) : __assert_fail ("Op && \"Cannot dereference end iterator!\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 759, __extension__ __PRETTY_FUNCTION__));
    return Op->getUser();
  }

  SDNode *operator->() const { return operator*(); }

  SDUse &getUse() const { return *Op; }

  /// Retrieve the operand # of this use in its user.
  unsigned getOperandNo() const {
    assert(Op && "Cannot dereference end iterator!")(static_cast <bool> (Op && "Cannot dereference end iterator!"
) ? void (0) : __assert_fail ("Op && \"Cannot dereference end iterator!\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 769, __extension__ __PRETTY_FUNCTION__));
    return (unsigned)(Op - Op->getUser()->OperandList);
  }
};

/// Provide iteration support to walk over all uses of an SDNode.
use_iterator use_begin() const {
  return use_iterator(UseList);
}

static use_iterator use_end() { return use_iterator(nullptr); }

inline iterator_range<use_iterator> uses() {
  return make_range(use_begin(), use_end());
}
inline iterator_range<use_iterator> uses() const {
  return make_range(use_begin(), use_end());
}

/// Return true if there are exactly NUSES uses of the indicated value.
/// This method ignores uses of other values defined by this operation.
bool hasNUsesOfValue(unsigned NUses, unsigned Value) const;

/// Return true if there are any use of the indicated value.
/// This method ignores uses of other values defined by this operation.
bool hasAnyUseOfValue(unsigned Value) const;

/// Return true if this node is the only use of N.
bool isOnlyUserOf(const SDNode *N) const;

/// Return true if this node is an operand of N.
bool isOperandOf(const SDNode *N) const;

/// Return true if this node is a predecessor of N.
/// NOTE: Implemented on top of hasPredecessor and every bit as
/// expensive. Use carefully.
bool isPredecessorOf(const SDNode *N) const {
  return N->hasPredecessor(this);
}

/// Return true if N is a predecessor of this node.
/// N is either an operand of this node, or can be reached by recursively
/// traversing up the operands.
/// NOTE: This is an expensive method. Use it carefully.
bool hasPredecessor(const SDNode *N) const;

/// Returns true if N is a predecessor of any node in Worklist. This
/// helper keeps Visited and Worklist sets externally to allow unions
/// searches to be performed in parallel, caching of results across
/// queries and incremental addition to Worklist. Stops early if N is
/// found but will resume. Remember to clear Visited and Worklists
/// if DAG changes. MaxSteps gives a maximum number of nodes to visit before
/// giving up. The TopologicalPrune flag signals that positive NodeIds are
/// topologically ordered (Operands have strictly smaller node id) and search
/// can be pruned leveraging this.
static bool hasPredecessorHelper(const SDNode *N,
                                 SmallPtrSetImpl<const SDNode *> &Visited,
                                 SmallVectorImpl<const SDNode *> &Worklist,
                                 unsigned int MaxSteps = 0,
                                 bool TopologicalPrune = false) {
  SmallVector<const SDNode *, 8> DeferredNodes;
  if (Visited.count(N))
    return true;

  // Node Id's are assigned in three places: As a topological
  // ordering (> 0), during legalization (results in values set to
  // 0), new nodes (set to -1). If N has a topolgical id then we
  // know that all nodes with ids smaller than it cannot be
  // successors and we need not check them. Filter out all node
  // that can't be matches. We add them to the worklist before exit
  // in case of multiple calls. Note that during selection the topological id
  // may be violated if a node's predecessor is selected before it. We mark
  // this at selection negating the id of unselected successors and
  // restricting topological pruning to positive ids.

  int NId = N->getNodeId();
  // If we Invalidated the Id, reconstruct original NId.
  if (NId < -1)
    NId = -(NId + 1);

  bool Found = false;
  while (!Worklist.empty()) {
    const SDNode *M = Worklist.pop_back_val();
    int MId = M->getNodeId();
    if (TopologicalPrune && M->getOpcode() != ISD::TokenFactor && (NId > 0) &&
        (MId > 0) && (MId < NId)) {
      DeferredNodes.push_back(M);
      continue;
    }
    for (const SDValue &OpV : M->op_values()) {
      SDNode *Op = OpV.getNode();
      if (Visited.insert(Op).second)
        Worklist.push_back(Op);
      if (Op == N)
        Found = true;
    }
    if (Found)
      break;
    if (MaxSteps != 0 && Visited.size() >= MaxSteps)
      break;
  }
  // Push deferred nodes back on worklist.
  Worklist.append(DeferredNodes.begin(), DeferredNodes.end());
  // If we bailed early, conservatively return found.
  if (MaxSteps != 0 && Visited.size() >= MaxSteps)
    return true;
  return Found;
}

/// Return true if all the users of N are contained in Nodes.
/// NOTE: Requires at least one match, but doesn't require them all.
static bool areOnlyUsersOf(ArrayRef<const SDNode *> Nodes, const SDNode *N);

/// Return the number of values used by this operation.
unsigned getNumOperands() const { return NumOperands; }

/// Return the maximum number of operands that a SDNode can hold.
static constexpr size_t getMaxNumOperands() {
  return std::numeric_limits<decltype(SDNode::NumOperands)>::max();
}

/// Helper method returns the integer value of a ConstantSDNode operand.
inline uint64_t getConstantOperandVal(unsigned Num) const;

/// Helper method returns the APInt of a ConstantSDNode operand.
inline const APInt &getConstantOperandAPInt(unsigned Num) const;

const SDValue &getOperand(unsigned Num) const {
  assert(Num < NumOperands && "Invalid child # of SDNode!")(static_cast <bool> (Num < NumOperands && "Invalid child # of SDNode!"
) ? void (0) : __assert_fail ("Num < NumOperands && \"Invalid child # of SDNode!\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 897, __extension__ __PRETTY_FUNCTION__));
  return OperandList[Num];
}

using op_iterator = SDUse *;

op_iterator op_begin() const { return OperandList; }
op_iterator op_end() const { return OperandList+NumOperands; }
ArrayRef<SDUse> ops() const { return makeArrayRef(op_begin(), op_end()); }

/// Iterator for directly iterating over the operand SDValue's.
struct value_op_iterator
    : iterator_adaptor_base<value_op_iterator, op_iterator,
                            std::random_access_iterator_tag, SDValue,
                            ptrdiff_t, value_op_iterator *,
                            value_op_iterator *> {
  explicit value_op_iterator(SDUse *U = nullptr)
    : iterator_adaptor_base(U) {}

  const SDValue &operator*() const { return I->get(); }
};

iterator_range<value_op_iterator> op_values() const {
  return make_range(value_op_iterator(op_begin()),
                    value_op_iterator(op_end()));
}

SDVTList getVTList() const {
  SDVTList X = { ValueList, NumValues };
  return X;
}

/// If this node has a glue operand, return the node
/// to which the glue operand points. Otherwise return NULL.
SDNode *getGluedNode() const {
  if (getNumOperands() != 0 &&
      getOperand(getNumOperands()-1).getValueType() == MVT::Glue)
    return getOperand(getNumOperands()-1).getNode();
  return nullptr;
}

/// If this node has a glue value with a user, return
/// the user (there is at most one). Otherwise return NULL.
SDNode *getGluedUser() const {
  for (use_iterator UI = use_begin(), UE = use_end(); UI != UE; ++UI)
    if (UI.getUse().get().getValueType() == MVT::Glue)
      return *UI;
  return nullptr;
}

SDNodeFlags getFlags() const { return Flags; }
void setFlags(SDNodeFlags NewFlags) { Flags = NewFlags; }

/// Clear any flags in this node that aren't also set in Flags.
/// If Flags is not in a defined state then this has no effect.
void intersectFlagsWith(const SDNodeFlags Flags);

/// Return the number of values defined/returned by this operator.
unsigned getNumValues() const { return NumValues; }

/// Return the type of a specified result.
EVT getValueType(unsigned ResNo) const {
  assert(ResNo < NumValues && "Illegal result number!")(static_cast <bool> (ResNo < NumValues && "Illegal result number!"
) ? void (0) : __assert_fail ("ResNo < NumValues && \"Illegal result number!\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 959, __extension__ __PRETTY_FUNCTION__));
  return ValueList[ResNo];
}

/// Return the type of a specified result as a simple type.
MVT getSimpleValueType(unsigned ResNo) const {
  return getValueType(ResNo).getSimpleVT();
}

/// Returns MVT::getSizeInBits(getValueType(ResNo)).
///
/// If the value type is a scalable vector type, the scalable property will
/// be set and the runtime size will be a positive integer multiple of the
/// base size.
TypeSize getValueSizeInBits(unsigned ResNo) const {
  return getValueType(ResNo).getSizeInBits();
}

using value_iterator = const EVT *;

value_iterator value_begin() const { return ValueList; }
value_iterator value_end() const { return ValueList+NumValues; }
iterator_range<value_iterator> values() const {
  return llvm::make_range(value_begin(), value_end());
}

/// Return the opcode of this operation for printing.
std::string getOperationName(const SelectionDAG *G = nullptr) const;
static const char* getIndexedModeName(ISD::MemIndexedMode AM);
void print_types(raw_ostream &OS, const SelectionDAG *G) const;
void print_details(raw_ostream &OS, const SelectionDAG *G) const;
void print(raw_ostream &OS, const SelectionDAG *G = nullptr) const;
void printr(raw_ostream &OS, const SelectionDAG *G = nullptr) const;

/// Print a SelectionDAG node and all children down to
/// the leaves.  The given SelectionDAG allows target-specific nodes
/// to be printed in human-readable form.  Unlike printr, this will
/// print the whole DAG, including children that appear multiple
/// times.
///
void printrFull(raw_ostream &O, const SelectionDAG *G = nullptr) const;

/// Print a SelectionDAG node and children up to
/// depth "depth."  The given SelectionDAG allows target-specific
/// nodes to be printed in human-readable form.  Unlike printr, this
/// will print children that appear multiple times wherever they are
/// used.
///
void printrWithDepth(raw_ostream &O, const SelectionDAG *G = nullptr,
                     unsigned depth = 100) const;

/// Dump this node, for debugging.
void dump() const;

/// Dump (recursively) this node and its use-def subgraph.
void dumpr() const;

/// Dump this node, for debugging.
/// The given SelectionDAG allows target-specific nodes to be printed
/// in human-readable form.
void dump(const SelectionDAG *G) const;

/// Dump (recursively) this node and its use-def subgraph.
/// The given SelectionDAG allows target-specific nodes to be printed
/// in human-readable form.
void dumpr(const SelectionDAG *G) const;

/// printrFull to dbgs().  The given SelectionDAG allows
/// target-specific nodes to be printed in human-readable form.
/// Unlike dumpr, this will print the whole DAG, including children
/// that appear multiple times.
void dumprFull(const SelectionDAG *G = nullptr) const;

/// printrWithDepth to dbgs().  The given
/// SelectionDAG allows target-specific nodes to be printed in
/// human-readable form.  Unlike dumpr, this will print children
/// that appear multiple times wherever they are used.
///
void dumprWithDepth(const SelectionDAG *G = nullptr,
                    unsigned depth = 100) const;

/// Gather unique data for the node.
void Profile(FoldingSetNodeID &ID) const;

/// This method should only be used by the SDUse class.
void addUse(SDUse &U) { U.addToList(&UseList); }

1046protected:
static SDVTList getSDVTList(EVT VT) {
  SDVTList Ret = { getValueTypeList(VT), 1 };
  return Ret;
}

/// Create an SDNode.
///
/// SDNodes are created without any operands, and never own the operand
/// storage. To add operands, see SelectionDAG::createOperands.
SDNode(unsigned Opc, unsigned Order, DebugLoc dl, SDVTList VTs)
    : NodeType(Opc), ValueList(VTs.VTs), NumValues(VTs.NumVTs),
      IROrder(Order), debugLoc(std::move(dl)) {
  memset(&RawSDNodeBits, 0, sizeof(RawSDNodeBits));
  assert(debugLoc.hasTrivialDestructor() && "Expected trivial destructor")(static_cast <bool> (debugLoc.hasTrivialDestructor() &&
 "Expected trivial destructor") ? void (0) : __assert_fail ("debugLoc.hasTrivialDestructor() && \"Expected trivial destructor\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1060, __extension__ __PRETTY_FUNCTION__));
  assert(NumValues == VTs.NumVTs &&(static_cast <bool> (NumValues == VTs.NumVTs &&
 "NumValues wasn't wide enough for its operands!") ? void (0)
 : __assert_fail ("NumValues == VTs.NumVTs && \"NumValues wasn't wide enough for its operands!\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1062, __extension__ __PRETTY_FUNCTION__))
         "NumValues wasn't wide enough for its operands!")(static_cast <bool> (NumValues == VTs.NumVTs &&
 "NumValues wasn't wide enough for its operands!") ? void (0)
 : __assert_fail ("NumValues == VTs.NumVTs && \"NumValues wasn't wide enough for its operands!\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1062, __extension__ __PRETTY_FUNCTION__));
}

/// Release the operands and set this node to have zero operands.
void DropOperands();
1067};

1069/// Wrapper class for IR location info (IR ordering and DebugLoc) to be passed
1070/// into SDNode creation functions.
1071/// When an SDNode is created from the DAGBuilder, the DebugLoc is extracted
1072/// from the original Instruction, and IROrder is the ordinal position of
1073/// the instruction.
1074/// When an SDNode is created after the DAG is being built, both DebugLoc and
1075/// the IROrder are propagated from the original SDNode.
1076/// So SDLoc class provides two constructors besides the default one, one to
1077/// be used by the DAGBuilder, the other to be used by others.
1078class SDLoc {
1079private:
DebugLoc DL;
int IROrder = 0;

1083public:
SDLoc() = default;
SDLoc(const SDNode *N) : DL(N->getDebugLoc()), IROrder(N->getIROrder()) {}
SDLoc(const SDValue V) : SDLoc(V.getNode()) {}
SDLoc(const Instruction *I, int Order) : IROrder(Order) {
  assert(Order >= 0 && "bad IROrder")(static_cast <bool> (Order >= 0 && "bad IROrder"
) ? void (0) : __assert_fail ("Order >= 0 && \"bad IROrder\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1088, __extension__ __PRETTY_FUNCTION__));
  if (I)
    DL = I->getDebugLoc();
}

unsigned getIROrder() const { return IROrder; }
const DebugLoc &getDebugLoc() const { return DL; }
1095};

1097// Define inline functions from the SDValue class.

1099inline SDValue::SDValue(SDNode *node, unsigned resno)
  : Node(node), ResNo(resno) {
// Explicitly check for !ResNo to avoid use-after-free, because there are
// callers that use SDValue(N, 0) with a deleted N to indicate successful
// combines.
assert((!Node || !ResNo || ResNo < Node->getNumValues()) &&(static_cast <bool> ((!Node || !ResNo || ResNo < Node
->getNumValues()) && "Invalid result number for the given node!"
) ? void (0) : __assert_fail ("(!Node || !ResNo || ResNo < Node->getNumValues()) && \"Invalid result number for the given node!\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1105, __extension__ __PRETTY_FUNCTION__))
       "Invalid result number for the given node!")(static_cast <bool> ((!Node || !ResNo || ResNo < Node
->getNumValues()) && "Invalid result number for the given node!"
) ? void (0) : __assert_fail ("(!Node || !ResNo || ResNo < Node->getNumValues()) && \"Invalid result number for the given node!\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1105, __extension__ __PRETTY_FUNCTION__));
assert(ResNo < -2U && "Cannot use result numbers reserved for DenseMaps.")(static_cast <bool> (ResNo < -2U && "Cannot use result numbers reserved for DenseMaps."
) ? void (0) : __assert_fail ("ResNo < -2U && \"Cannot use result numbers reserved for DenseMaps.\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1106, __extension__ __PRETTY_FUNCTION__));
1107}

1109inline unsigned SDValue::getOpcode() const {
return Node->getOpcode();
1111}

1113inline EVT SDValue::getValueType() const {
return Node->getValueType(ResNo);
15
←
Called C++ object pointer is null
1115}

1117inline unsigned SDValue::getNumOperands() const {
return Node->getNumOperands();
1119}

1121inline const SDValue &SDValue::getOperand(unsigned i) const {
return Node->getOperand(i);
1123}

1125inline uint64_t SDValue::getConstantOperandVal(unsigned i) const {
return Node->getConstantOperandVal(i);
1127}

1129inline const APInt &SDValue::getConstantOperandAPInt(unsigned i) const {
return Node->getConstantOperandAPInt(i);
1131}

1133inline bool SDValue::isTargetOpcode() const {
return Node->isTargetOpcode();
1135}

1137inline bool SDValue::isTargetMemoryOpcode() const {
return Node->isTargetMemoryOpcode();
1139}

1141inline bool SDValue::isMachineOpcode() const {
return Node->isMachineOpcode();
1143}

1145inline unsigned SDValue::getMachineOpcode() const {
return Node->getMachineOpcode();
1147}

1149inline bool SDValue::isUndef() const {
return Node->isUndef();
1151}

1153inline bool SDValue::use_empty() const {
return !Node->hasAnyUseOfValue(ResNo);
1155}

1157inline bool SDValue::hasOneUse() const {
return Node->hasNUsesOfValue(1, ResNo);
1159}

1161inline const DebugLoc &SDValue::getDebugLoc() const {
return Node->getDebugLoc();
1163}

1165inline void SDValue::dump() const {
return Node->dump();
1167}

1169inline void SDValue::dump(const SelectionDAG *G) const {
return Node->dump(G);
1171}

1173inline void SDValue::dumpr() const {
return Node->dumpr();
1175}

1177inline void SDValue::dumpr(const SelectionDAG *G) const {
return Node->dumpr(G);
1179}

1181// Define inline functions from the SDUse class.

1183inline void SDUse::set(const SDValue &V) {
if (Val.getNode()) removeFromList();
Val = V;
if (V.getNode()) V.getNode()->addUse(*this);
1187}

1189inline void SDUse::setInitial(const SDValue &V) {
Val = V;
V.getNode()->addUse(*this);
1192}

1194inline void SDUse::setNode(SDNode *N) {
if (Val.getNode()) removeFromList();
Val.setNode(N);
if (N) N->addUse(*this);
1198}

1200/// This class is used to form a handle around another node that
1201/// is persistent and is updated across invocations of replaceAllUsesWith on its
1202/// operand.  This node should be directly created by end-users and not added to
1203/// the AllNodes list.
1204class HandleSDNode : public SDNode {
SDUse Op;

1207public:
explicit HandleSDNode(SDValue X)
  : SDNode(ISD::HANDLENODE, 0, DebugLoc(), getSDVTList(MVT::Other)) {
  // HandleSDNodes are never inserted into the DAG, so they won't be
  // auto-numbered. Use ID 65535 as a sentinel.
  PersistentId = 0xffff;

  // Manually set up the operand list. This node type is special in that it's
  // always stack allocated and SelectionDAG does not manage its operands.
  // TODO: This should either (a) not be in the SDNode hierarchy, or (b) not
  // be so special.
  Op.setUser(this);
  Op.setInitial(X);
  NumOperands = 1;
  OperandList = &Op;
}
~HandleSDNode();

const SDValue &getValue() const { return Op; }
1226};

1228class AddrSpaceCastSDNode : public SDNode {
1229private:
unsigned SrcAddrSpace;
unsigned DestAddrSpace;

1233public:
AddrSpaceCastSDNode(unsigned Order, const DebugLoc &dl, EVT VT,
                    unsigned SrcAS, unsigned DestAS);

unsigned getSrcAddressSpace() const { return SrcAddrSpace; }
unsigned getDestAddressSpace() const { return DestAddrSpace; }

static bool classof(const SDNode *N) {
  return N->getOpcode() == ISD::ADDRSPACECAST;
}
1243};

1245/// This is an abstract virtual class for memory operations.
1246class MemSDNode : public SDNode {
1247private:
// VT of in-memory value.
EVT MemoryVT;

1251protected:
/// Memory reference information.
MachineMemOperand *MMO;

1255public:
MemSDNode(unsigned Opc, unsigned Order, const DebugLoc &dl, SDVTList VTs,
          EVT memvt, MachineMemOperand *MMO);

bool readMem() const { return MMO->isLoad(); }
bool writeMem() const { return MMO->isStore(); }

/// Returns alignment and volatility of the memory access
Align getOriginalAlign() const { return MMO->getBaseAlign(); }
Align getAlign() const { return MMO->getAlign(); }
// FIXME: Remove once transition to getAlign is over.
unsigned getAlignment() const { return MMO->getAlign().value(); }

/// Return the SubclassData value, without HasDebugValue. This contains an
/// encoding of the volatile flag, as well as bits used by subclasses. This
/// function should only be used to compute a FoldingSetNodeID value.
/// The HasDebugValue bit is masked out because CSE map needs to match
/// nodes with debug info with nodes without debug info. Same is about
/// isDivergent bit.
unsigned getRawSubclassData() const {
  uint16_t Data;
  union {
    char RawSDNodeBits[sizeof(uint16_t)];
    SDNodeBitfields SDNodeBits;
  };
  memcpy(&RawSDNodeBits, &this->RawSDNodeBits, sizeof(this->RawSDNodeBits));
  SDNodeBits.HasDebugValue = 0;
  SDNodeBits.IsDivergent = false;
  memcpy(&Data, &RawSDNodeBits, sizeof(RawSDNodeBits));
  return Data;
}

bool isVolatile() const { return MemSDNodeBits.IsVolatile; }
bool isNonTemporal() const { return MemSDNodeBits.IsNonTemporal; }
bool isDereferenceable() const { return MemSDNodeBits.IsDereferenceable; }
bool isInvariant() const { return MemSDNodeBits.IsInvariant; }

// Returns the offset from the location of the access.
int64_t getSrcValueOffset() const { return MMO->getOffset(); }

/// Returns the AA info that describes the dereference.
AAMDNodes getAAInfo() const { return MMO->getAAInfo(); }

/// Returns the Ranges that describes the dereference.
const MDNode *getRanges() const { return MMO->getRanges(); }

/// Returns the synchronization scope ID for this memory operation.
SyncScope::ID getSyncScopeID() const { return MMO->getSyncScopeID(); }

/// Return the atomic ordering requirements for this memory operation. For
/// cmpxchg atomic operations, return the atomic ordering requirements when
/// store occurs.
AtomicOrdering getSuccessOrdering() const {
  return MMO->getSuccessOrdering();
}

/// Return a single atomic ordering that is at least as strong as both the
/// success and failure orderings for an atomic operation.  (For operations
/// other than cmpxchg, this is equivalent to getSuccessOrdering().)
AtomicOrdering getMergedOrdering() const { return MMO->getMergedOrdering(); }

/// Return true if the memory operation ordering is Unordered or higher.
bool isAtomic() const { return MMO->isAtomic(); }

/// Returns true if the memory operation doesn't imply any ordering
/// constraints on surrounding memory operations beyond the normal memory
/// aliasing rules.
bool isUnordered() const { return MMO->isUnordered(); }

/// Returns true if the memory operation is neither atomic or volatile.
bool isSimple() const { return !isAtomic() && !isVolatile(); }

/// Return the type of the in-memory value.
EVT getMemoryVT() const { return MemoryVT; }

/// Return a MachineMemOperand object describing the memory
/// reference performed by operation.
MachineMemOperand *getMemOperand() const { return MMO; }

const MachinePointerInfo &getPointerInfo() const {
  return MMO->getPointerInfo();
}

/// Return the address space for the associated pointer
unsigned getAddressSpace() const {
  return getPointerInfo().getAddrSpace();
}

/// Update this MemSDNode's MachineMemOperand information
/// to reflect the alignment of NewMMO, if it has a greater alignment.
/// This must only be used when the new alignment applies to all users of
/// this MachineMemOperand.
void refineAlignment(const MachineMemOperand *NewMMO) {
  MMO->refineAlignment(NewMMO);
}

const SDValue &getChain() const { return getOperand(0); }

const SDValue &getBasePtr() const {
  switch (getOpcode()) {
  case ISD::STORE:
  case ISD::MSTORE:
    return getOperand(2);
  case ISD::MGATHER:
  case ISD::MSCATTER:
    return getOperand(3);
  default:
    return getOperand(1);
  }
}

// Methods to support isa and dyn_cast
static bool classof(const SDNode *N) {
  // For some targets, we lower some target intrinsics to a MemIntrinsicNode
  // with either an intrinsic or a target opcode.
  switch (N->getOpcode()) {
  case ISD::LOAD:
  case ISD::STORE:
  case ISD::PREFETCH:
  case ISD::ATOMIC_CMP_SWAP:
  case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
  case ISD::ATOMIC_SWAP:
  case ISD::ATOMIC_LOAD_ADD:
  case ISD::ATOMIC_LOAD_SUB:
  case ISD::ATOMIC_LOAD_AND:
  case ISD::ATOMIC_LOAD_CLR:
  case ISD::ATOMIC_LOAD_OR:
  case ISD::ATOMIC_LOAD_XOR:
  case ISD::ATOMIC_LOAD_NAND:
  case ISD::ATOMIC_LOAD_MIN:
  case ISD::ATOMIC_LOAD_MAX:
  case ISD::ATOMIC_LOAD_UMIN:
  case ISD::ATOMIC_LOAD_UMAX:
  case ISD::ATOMIC_LOAD_FADD:
  case ISD::ATOMIC_LOAD_FSUB:
  case ISD::ATOMIC_LOAD:
  case ISD::ATOMIC_STORE:
  case ISD::MLOAD:
  case ISD::MSTORE:
  case ISD::MGATHER:
  case ISD::MSCATTER:
    return true;
  default:
    return N->isMemIntrinsic() || N->isTargetMemoryOpcode();
  }
}
1401};

1403/// This is an SDNode representing atomic operations.
1404class AtomicSDNode : public MemSDNode {
1405public:
AtomicSDNode(unsigned Opc, unsigned Order, const DebugLoc &dl, SDVTList VTL,
             EVT MemVT, MachineMemOperand *MMO)
  : MemSDNode(Opc, Order, dl, VTL, MemVT, MMO) {
  assert(((Opc != ISD::ATOMIC_LOAD && Opc != ISD::ATOMIC_STORE) ||(static_cast <bool> (((Opc != ISD::ATOMIC_LOAD &&
 Opc != ISD::ATOMIC_STORE) || MMO->isAtomic()) && "then why are we using an AtomicSDNode?"
) ? void (0) : __assert_fail ("((Opc != ISD::ATOMIC_LOAD && Opc != ISD::ATOMIC_STORE) || MMO->isAtomic()) && \"then why are we using an AtomicSDNode?\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1410, __extension__ __PRETTY_FUNCTION__))
          MMO->isAtomic()) && "then why are we using an AtomicSDNode?")(static_cast <bool> (((Opc != ISD::ATOMIC_LOAD &&
 Opc != ISD::ATOMIC_STORE) || MMO->isAtomic()) && "then why are we using an AtomicSDNode?"
) ? void (0) : __assert_fail ("((Opc != ISD::ATOMIC_LOAD && Opc != ISD::ATOMIC_STORE) || MMO->isAtomic()) && \"then why are we using an AtomicSDNode?\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1410, __extension__ __PRETTY_FUNCTION__));
}

const SDValue &getBasePtr() const { return getOperand(1); }
const SDValue &getVal() const { return getOperand(2); }

/// Returns true if this SDNode represents cmpxchg atomic operation, false
/// otherwise.
bool isCompareAndSwap() const {
  unsigned Op = getOpcode();
  return Op == ISD::ATOMIC_CMP_SWAP ||
         Op == ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS;
}

/// For cmpxchg atomic operations, return the atomic ordering requirements
/// when store does not occur.
AtomicOrdering getFailureOrdering() const {
  assert(isCompareAndSwap() && "Must be cmpxchg operation")(static_cast <bool> (isCompareAndSwap() && "Must be cmpxchg operation"
) ? void (0) : __assert_fail ("isCompareAndSwap() && \"Must be cmpxchg operation\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1427, __extension__ __PRETTY_FUNCTION__));
  return MMO->getFailureOrdering();
}

// Methods to support isa and dyn_cast
static bool classof(const SDNode *N) {
  return N->getOpcode() == ISD::ATOMIC_CMP_SWAP     ||
         N->getOpcode() == ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS ||
         N->getOpcode() == ISD::ATOMIC_SWAP         ||
         N->getOpcode() == ISD::ATOMIC_LOAD_ADD     ||
         N->getOpcode() == ISD::ATOMIC_LOAD_SUB     ||
         N->getOpcode() == ISD::ATOMIC_LOAD_AND     ||
         N->getOpcode() == ISD::ATOMIC_LOAD_CLR     ||
         N->getOpcode() == ISD::ATOMIC_LOAD_OR      ||
         N->getOpcode() == ISD::ATOMIC_LOAD_XOR     ||
         N->getOpcode() == ISD::ATOMIC_LOAD_NAND    ||
         N->getOpcode() == ISD::ATOMIC_LOAD_MIN     ||
         N->getOpcode() == ISD::ATOMIC_LOAD_MAX     ||
         N->getOpcode() == ISD::ATOMIC_LOAD_UMIN    ||
         N->getOpcode() == ISD::ATOMIC_LOAD_UMAX    ||
         N->getOpcode() == ISD::ATOMIC_LOAD_FADD    ||
         N->getOpcode() == ISD::ATOMIC_LOAD_FSUB    ||
         N->getOpcode() == ISD::ATOMIC_LOAD         ||
         N->getOpcode() == ISD::ATOMIC_STORE;
}
1452};

1454/// This SDNode is used for target intrinsics that touch
1455/// memory and need an associated MachineMemOperand. Its opcode may be
1456/// INTRINSIC_VOID, INTRINSIC_W_CHAIN, PREFETCH, or a target-specific opcode
1457/// with a value not less than FIRST_TARGET_MEMORY_OPCODE.
1458class MemIntrinsicSDNode : public MemSDNode {
1459public:
MemIntrinsicSDNode(unsigned Opc, unsigned Order, const DebugLoc &dl,
                   SDVTList VTs, EVT MemoryVT, MachineMemOperand *MMO)
    : MemSDNode(Opc, Order, dl, VTs, MemoryVT, MMO) {
  SDNodeBits.IsMemIntrinsic = true;
}

// Methods to support isa and dyn_cast
static bool classof(const SDNode *N) {
  // We lower some target intrinsics to their target opcode
  // early a node with a target opcode can be of this class
  return N->isMemIntrinsic()             ||
         N->getOpcode() == ISD::PREFETCH ||
         N->isTargetMemoryOpcode();
}
1474};

1476/// This SDNode is used to implement the code generator
1477/// support for the llvm IR shufflevector instruction.  It combines elements
1478/// from two input vectors into a new input vector, with the selection and
1479/// ordering of elements determined by an array of integers, referred to as
1480/// the shuffle mask.  For input vectors of width N, mask indices of 0..N-1
1481/// refer to elements from the LHS input, and indices from N to 2N-1 the RHS.
1482/// An index of -1 is treated as undef, such that the code generator may put
1483/// any value in the corresponding element of the result.
1484class ShuffleVectorSDNode : public SDNode {
// The memory for Mask is owned by the SelectionDAG's OperandAllocator, and
// is freed when the SelectionDAG object is destroyed.
const int *Mask;

1489protected:
friend class SelectionDAG;

ShuffleVectorSDNode(EVT VT, unsigned Order, const DebugLoc &dl, const int *M)
    : SDNode(ISD::VECTOR_SHUFFLE, Order, dl, getSDVTList(VT)), Mask(M) {}

1495public:
ArrayRef<int> getMask() const {
  EVT VT = getValueType(0);
  return makeArrayRef(Mask, VT.getVectorNumElements());
}

int getMaskElt(unsigned Idx) const {
  assert(Idx < getValueType(0).getVectorNumElements() && "Idx out of range!")(static_cast <bool> (Idx < getValueType(0).getVectorNumElements
() && "Idx out of range!") ? void (0) : __assert_fail
 ("Idx < getValueType(0).getVectorNumElements() && \"Idx out of range!\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1502, __extension__ __PRETTY_FUNCTION__));
  return Mask[Idx];
}

bool isSplat() const { return isSplatMask(Mask, getValueType(0)); }

int getSplatIndex() const {
  assert(isSplat() && "Cannot get splat index for non-splat!")(static_cast <bool> (isSplat() && "Cannot get splat index for non-splat!"
) ? void (0) : __assert_fail ("isSplat() && \"Cannot get splat index for non-splat!\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1509, __extension__ __PRETTY_FUNCTION__));
  EVT VT = getValueType(0);
  for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
    if (Mask[i] >= 0)
      return Mask[i];

  // We can choose any index value here and be correct because all elements
  // are undefined. Return 0 for better potential for callers to simplify.
  return 0;
}

static bool isSplatMask(const int *Mask, EVT VT);

/// Change values in a shuffle permute mask assuming
/// the two vector operands have swapped position.
static void commuteMask(MutableArrayRef<int> Mask) {
  unsigned NumElems = Mask.size();
  for (unsigned i = 0; i != NumElems; ++i) {
    int idx = Mask[i];
    if (idx < 0)
      continue;
    else if (idx < (int)NumElems)
      Mask[i] = idx + NumElems;
    else
      Mask[i] = idx - NumElems;
  }
}

static bool classof(const SDNode *N) {
  return N->getOpcode() == ISD::VECTOR_SHUFFLE;
}
1540};

1542class ConstantSDNode : public SDNode {
friend class SelectionDAG;

const ConstantInt *Value;

ConstantSDNode(bool isTarget, bool isOpaque, const ConstantInt *val, EVT VT)
    : SDNode(isTarget ? ISD::TargetConstant : ISD::Constant, 0, DebugLoc(),
             getSDVTList(VT)),
      Value(val) {
  ConstantSDNodeBits.IsOpaque = isOpaque;
}

1554public:
const ConstantInt *getConstantIntValue() const { return Value; }
const APInt &getAPIntValue() const { return Value->getValue(); }
uint64_t getZExtValue() const { return Value->getZExtValue(); }
int64_t getSExtValue() const { return Value->getSExtValue(); }
uint64_t getLimitedValue(uint64_t Limit = UINT64_MAX(18446744073709551615UL)) {
  return Value->getLimitedValue(Limit);
}
MaybeAlign getMaybeAlignValue() const { return Value->getMaybeAlignValue(); }
Align getAlignValue() const { return Value->getAlignValue(); }

bool isOne() const { return Value->isOne(); }
bool isNullValue() const { return Value->isZero(); }
bool isAllOnesValue() const { return Value->isMinusOne(); }
bool isMaxSignedValue() const { return Value->isMaxValue(true); }
bool isMinSignedValue() const { return Value->isMinValue(true); }

bool isOpaque() const { return ConstantSDNodeBits.IsOpaque; }

static bool classof(const SDNode *N) {
  return N->getOpcode() == ISD::Constant ||
         N->getOpcode() == ISD::TargetConstant;
}
1577};

1579uint64_t SDNode::getConstantOperandVal(unsigned Num) const {
return cast<ConstantSDNode>(getOperand(Num))->getZExtValue();
1581}

1583const APInt &SDNode::getConstantOperandAPInt(unsigned Num) const {
return cast<ConstantSDNode>(getOperand(Num))->getAPIntValue();
1585}

1587class ConstantFPSDNode : public SDNode {
friend class SelectionDAG;

const ConstantFP *Value;

ConstantFPSDNode(bool isTarget, const ConstantFP *val, EVT VT)
    : SDNode(isTarget ? ISD::TargetConstantFP : ISD::ConstantFP, 0,
             DebugLoc(), getSDVTList(VT)),
      Value(val) {}

1597public:
const APFloat& getValueAPF() const { return Value->getValueAPF(); }
const ConstantFP *getConstantFPValue() const { return Value; }

/// Return true if the value is positive or negative zero.
bool isZero() const { return Value->isZero(); }

/// Return true if the value is a NaN.
bool isNaN() const { return Value->isNaN(); }

/// Return true if the value is an infinity
bool isInfinity() const { return Value->isInfinity(); }

/// Return true if the value is negative.
bool isNegative() const { return Value->isNegative(); }

/// We don't rely on operator== working on double values, as
/// it returns true for things that are clearly not equal, like -0.0 and 0.0.
/// As such, this method can be used to do an exact bit-for-bit comparison of
/// two floating point values.

/// We leave the version with the double argument here because it's just so
/// convenient to write "2.0" and the like.  Without this function we'd
/// have to duplicate its logic everywhere it's called.
bool isExactlyValue(double V) const {
  return Value->getValueAPF().isExactlyValue(V);
}
bool isExactlyValue(const APFloat& V) const;

static bool isValueValidForType(EVT VT, const APFloat& Val);

static bool classof(const SDNode *N) {
  return N->getOpcode() == ISD::ConstantFP ||
         N->getOpcode() == ISD::TargetConstantFP;
}
1632};

1634/// Returns true if \p V is a constant integer zero.
1635bool isNullConstant(SDValue V);

1637/// Returns true if \p V is an FP constant with a value of positive zero.
1638bool isNullFPConstant(SDValue V);

1640/// Returns true if \p V is an integer constant with all bits set.
1641bool isAllOnesConstant(SDValue V);

1643/// Returns true if \p V is a constant integer one.
1644bool isOneConstant(SDValue V);

1646/// Return the non-bitcasted source operand of \p V if it exists.
1647/// If \p V is not a bitcasted value, it is returned as-is.
1648SDValue peekThroughBitcasts(SDValue V);

1650/// Return the non-bitcasted and one-use source operand of \p V if it exists.
1651/// If \p V is not a bitcasted one-use value, it is returned as-is.
1652SDValue peekThroughOneUseBitcasts(SDValue V);

1654/// Return the non-extracted vector source operand of \p V if it exists.
1655/// If \p V is not an extracted subvector, it is returned as-is.
1656SDValue peekThroughExtractSubvectors(SDValue V);

1658/// Returns true if \p V is a bitwise not operation. Assumes that an all ones
1659/// constant is canonicalized to be operand 1.
1660bool isBitwiseNot(SDValue V, bool AllowUndefs = false);

1662/// Returns the SDNode if it is a constant splat BuildVector or constant int.
1663ConstantSDNode *isConstOrConstSplat(SDValue N, bool AllowUndefs = false,
                                  bool AllowTruncation = false);

1666/// Returns the SDNode if it is a demanded constant splat BuildVector or
1667/// constant int.
1668ConstantSDNode *isConstOrConstSplat(SDValue N, const APInt &DemandedElts,
                                  bool AllowUndefs = false,
                                  bool AllowTruncation = false);

1672/// Returns the SDNode if it is a constant splat BuildVector or constant float.
1673ConstantFPSDNode *isConstOrConstSplatFP(SDValue N, bool AllowUndefs = false);

1675/// Returns the SDNode if it is a demanded constant splat BuildVector or
1676/// constant float.
1677ConstantFPSDNode *isConstOrConstSplatFP(SDValue N, const APInt &DemandedElts,
                                      bool AllowUndefs = false);

1680/// Return true if the value is a constant 0 integer or a splatted vector of
1681/// a constant 0 integer (with no undefs by default).
1682/// Build vector implicit truncation is not an issue for null values.
1683bool isNullOrNullSplat(SDValue V, bool AllowUndefs = false);

1685/// Return true if the value is a constant 1 integer or a splatted vector of a
1686/// constant 1 integer (with no undefs).
1687/// Does not permit build vector implicit truncation.
1688bool isOneOrOneSplat(SDValue V, bool AllowUndefs = false);

1690/// Return true if the value is a constant -1 integer or a splatted vector of a
1691/// constant -1 integer (with no undefs).
1692/// Does not permit build vector implicit truncation.
1693bool isAllOnesOrAllOnesSplat(SDValue V, bool AllowUndefs = false);

1695/// Return true if \p V is either a integer or FP constant.
1696inline bool isIntOrFPConstant(SDValue V) {
return isa<ConstantSDNode>(V) || isa<ConstantFPSDNode>(V);
1698}

1700class GlobalAddressSDNode : public SDNode {
friend class SelectionDAG;

const GlobalValue *TheGlobal;
int64_t Offset;
unsigned TargetFlags;

GlobalAddressSDNode(unsigned Opc, unsigned Order, const DebugLoc &DL,
                    const GlobalValue *GA, EVT VT, int64_t o,
                    unsigned TF);

1711public:
const GlobalValue *getGlobal() const { return TheGlobal; }
int64_t getOffset() const { return Offset; }
unsigned getTargetFlags() const { return TargetFlags; }
// Return the address space this GlobalAddress belongs to.
unsigned getAddressSpace() const;

static bool classof(const SDNode *N) {
  return N->getOpcode() == ISD::GlobalAddress ||
         N->getOpcode() == ISD::TargetGlobalAddress ||
         N->getOpcode() == ISD::GlobalTLSAddress ||
         N->getOpcode() == ISD::TargetGlobalTLSAddress;
}
1724};

1726class FrameIndexSDNode : public SDNode {
friend class SelectionDAG;

int FI;

FrameIndexSDNode(int fi, EVT VT, bool isTarg)
  : SDNode(isTarg ? ISD::TargetFrameIndex : ISD::FrameIndex,
    0, DebugLoc(), getSDVTList(VT)), FI(fi) {
}

1736public:
int getIndex() const { return FI; }

static bool classof(const SDNode *N) {
  return N->getOpcode() == ISD::FrameIndex ||
         N->getOpcode() == ISD::TargetFrameIndex;
}
1743};

1745/// This SDNode is used for LIFETIME_START/LIFETIME_END values, which indicate
1746/// the offet and size that are started/ended in the underlying FrameIndex.
1747class LifetimeSDNode : public SDNode {
friend class SelectionDAG;
int64_t Size;
int64_t Offset; // -1 if offset is unknown.

LifetimeSDNode(unsigned Opcode, unsigned Order, const DebugLoc &dl,
               SDVTList VTs, int64_t Size, int64_t Offset)
    : SDNode(Opcode, Order, dl, VTs), Size(Size), Offset(Offset) {}
1755public:
int64_t getFrameIndex() const {
  return cast<FrameIndexSDNode>(getOperand(1))->getIndex();
}

bool hasOffset() const { return Offset >= 0; }
int64_t getOffset() const {
  assert(hasOffset() && "offset is unknown")(static_cast <bool> (hasOffset() && "offset is unknown"
) ? void (0) : __assert_fail ("hasOffset() && \"offset is unknown\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1762, __extension__ __PRETTY_FUNCTION__));
  return Offset;
}
int64_t getSize() const {
  assert(hasOffset() && "offset is unknown")(static_cast <bool> (hasOffset() && "offset is unknown"
) ? void (0) : __assert_fail ("hasOffset() && \"offset is unknown\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1766, __extension__ __PRETTY_FUNCTION__));
  return Size;
}

// Methods to support isa and dyn_cast
static bool classof(const SDNode *N) {
  return N->getOpcode() == ISD::LIFETIME_START ||
         N->getOpcode() == ISD::LIFETIME_END;
}
1775};

1777/// This SDNode is used for PSEUDO_PROBE values, which are the function guid and
1778/// the index of the basic block being probed. A pseudo probe serves as a place
1779/// holder and will be removed at the end of compilation. It does not have any
1780/// operand because we do not want the instruction selection to deal with any.
1781class PseudoProbeSDNode : public SDNode {
friend class SelectionDAG;
uint64_t Guid;
uint64_t Index;
uint32_t Attributes;

PseudoProbeSDNode(unsigned Opcode, unsigned Order, const DebugLoc &Dl,
                  SDVTList VTs, uint64_t Guid, uint64_t Index, uint32_t Attr)
    : SDNode(Opcode, Order, Dl, VTs), Guid(Guid), Index(Index),
      Attributes(Attr) {}

1792public:
uint64_t getGuid() const { return Guid; }
uint64_t getIndex() const { return Index; }
uint32_t getAttributes() const { return Attributes; }

// Methods to support isa and dyn_cast
static bool classof(const SDNode *N) {
  return N->getOpcode() == ISD::PSEUDO_PROBE;
}
1801};

1803class JumpTableSDNode : public SDNode {
friend class SelectionDAG;

int JTI;
unsigned TargetFlags;

JumpTableSDNode(int jti, EVT VT, bool isTarg, unsigned TF)
  : SDNode(isTarg ? ISD::TargetJumpTable : ISD::JumpTable,
    0, DebugLoc(), getSDVTList(VT)), JTI(jti), TargetFlags(TF) {
}

1814public:
int getIndex() const { return JTI; }
unsigned getTargetFlags() const { return TargetFlags; }

static bool classof(const SDNode *N) {
  return N->getOpcode() == ISD::JumpTable ||
         N->getOpcode() == ISD::TargetJumpTable;
}
1822};

1824class ConstantPoolSDNode : public SDNode {
friend class SelectionDAG;

union {
  const Constant *ConstVal;
  MachineConstantPoolValue *MachineCPVal;
} Val;
int Offset;  // It's a MachineConstantPoolValue if top bit is set.
Align Alignment; // Minimum alignment requirement of CP.
unsigned TargetFlags;

ConstantPoolSDNode(bool isTarget, const Constant *c, EVT VT, int o,
                   Align Alignment, unsigned TF)
    : SDNode(isTarget ? ISD::TargetConstantPool : ISD::ConstantPool, 0,
             DebugLoc(), getSDVTList(VT)),
      Offset(o), Alignment(Alignment), TargetFlags(TF) {
  assert(Offset >= 0 && "Offset is too large")(static_cast <bool> (Offset >= 0 && "Offset is too large"
) ? void (0) : __assert_fail ("Offset >= 0 && \"Offset is too large\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1840, __extension__ __PRETTY_FUNCTION__));
  Val.ConstVal = c;
}

ConstantPoolSDNode(bool isTarget, MachineConstantPoolValue *v, EVT VT, int o,
                   Align Alignment, unsigned TF)
    : SDNode(isTarget ? ISD::TargetConstantPool : ISD::ConstantPool, 0,
             DebugLoc(), getSDVTList(VT)),
      Offset(o), Alignment(Alignment), TargetFlags(TF) {
  assert(Offset >= 0 && "Offset is too large")(static_cast <bool> (Offset >= 0 && "Offset is too large"
) ? void (0) : __assert_fail ("Offset >= 0 && \"Offset is too large\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1849, __extension__ __PRETTY_FUNCTION__));
  Val.MachineCPVal = v;
  Offset |= 1 << (sizeof(unsigned)*CHAR_BIT8-1);
}

1854public:
bool isMachineConstantPoolEntry() const {
  return Offset < 0;
}

const Constant *getConstVal() const {
  assert(!isMachineConstantPoolEntry() && "Wrong constantpool type")(static_cast <bool> (!isMachineConstantPoolEntry() &&
 "Wrong constantpool type") ? void (0) : __assert_fail ("!isMachineConstantPoolEntry() && \"Wrong constantpool type\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1860, __extension__ __PRETTY_FUNCTION__));
  return Val.ConstVal;
}

MachineConstantPoolValue *getMachineCPVal() const {
  assert(isMachineConstantPoolEntry() && "Wrong constantpool type")(static_cast <bool> (isMachineConstantPoolEntry() &&
 "Wrong constantpool type") ? void (0) : __assert_fail ("isMachineConstantPoolEntry() && \"Wrong constantpool type\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1865, __extension__ __PRETTY_FUNCTION__));
  return Val.MachineCPVal;
}

int getOffset() const {
  return Offset & ~(1 << (sizeof(unsigned)*CHAR_BIT8-1));
}

// Return the alignment of this constant pool object, which is either 0 (for
// default alignment) or the desired value.
Align getAlign() const { return Alignment; }
unsigned getTargetFlags() const { return TargetFlags; }

Type *getType() const;

static bool classof(const SDNode *N) {
  return N->getOpcode() == ISD::ConstantPool ||
         N->getOpcode() == ISD::TargetConstantPool;
}
1884};

1886/// Completely target-dependent object reference.
1887class TargetIndexSDNode : public SDNode {
friend class SelectionDAG;

unsigned TargetFlags;
int Index;
int64_t Offset;

1894public:
TargetIndexSDNode(int Idx, EVT VT, int64_t Ofs, unsigned TF)
    : SDNode(ISD::TargetIndex, 0, DebugLoc(), getSDVTList(VT)),
      TargetFlags(TF), Index(Idx), Offset(Ofs) {}

unsigned getTargetFlags() const { return TargetFlags; }
int getIndex() const { return Index; }
int64_t getOffset() const { return Offset; }

static bool classof(const SDNode *N) {
  return N->getOpcode() == ISD::TargetIndex;
}
1906};

1908class BasicBlockSDNode : public SDNode {
friend class SelectionDAG;

MachineBasicBlock *MBB;

/// Debug info is meaningful and potentially useful here, but we create
/// blocks out of order when they're jumped to, which makes it a bit
/// harder.  Let's see if we need it first.
explicit BasicBlockSDNode(MachineBasicBlock *mbb)
  : SDNode(ISD::BasicBlock, 0, DebugLoc(), getSDVTList(MVT::Other)), MBB(mbb)
{}

1920public:
MachineBasicBlock *getBasicBlock() const { return MBB; }

static bool classof(const SDNode *N) {
  return N->getOpcode() == ISD::BasicBlock;
}
1926};

1928/// A "pseudo-class" with methods for operating on BUILD_VECTORs.
1929class BuildVectorSDNode : public SDNode {
1930public:
// These are constructed as SDNodes and then cast to BuildVectorSDNodes.
explicit BuildVectorSDNode() = delete;

/// Check if this is a constant splat, and if so, find the
/// smallest element size that splats the vector.  If MinSplatBits is
/// nonzero, the element size must be at least that large.  Note that the
/// splat element may be the entire vector (i.e., a one element vector).
/// Returns the splat element value in SplatValue.  Any undefined bits in
/// that value are zero, and the corresponding bits in the SplatUndef mask
/// are set.  The SplatBitSize value is set to the splat element size in
/// bits.  HasAnyUndefs is set to true if any bits in the vector are
/// undefined.  isBigEndian describes the endianness of the target.
bool isConstantSplat(APInt &SplatValue, APInt &SplatUndef,
                     unsigned &SplatBitSize, bool &HasAnyUndefs,
                     unsigned MinSplatBits = 0,
                     bool isBigEndian = false) const;

/// Returns the demanded splatted value or a null value if this is not a
/// splat.
///
/// The DemandedElts mask indicates the elements that must be in the splat.
/// If passed a non-null UndefElements bitvector, it will resize it to match
/// the vector width and set the bits where elements are undef.
SDValue getSplatValue(const APInt &DemandedElts,
                      BitVector *UndefElements = nullptr) const;

/// Returns the splatted value or a null value if this is not a splat.
///
/// If passed a non-null UndefElements bitvector, it will resize it to match
/// the vector width and set the bits where elements are undef.
SDValue getSplatValue(BitVector *UndefElements = nullptr) const;

/// Find the shortest repeating sequence of values in the build vector.
///
/// e.g. { u, X, u, X, u, u, X, u } -> { X }
///      { X, Y, u, Y, u, u, X, u } -> { X, Y }
///
/// Currently this must be a power-of-2 build vector.
/// The DemandedElts mask indicates the elements that must be present,
/// undemanded elements in Sequence may be null (SDValue()). If passed a
/// non-null UndefElements bitvector, it will resize it to match the original
/// vector width and set the bits where elements are undef. If result is
/// false, Sequence will be empty.
bool getRepeatedSequence(const APInt &DemandedElts,
                         SmallVectorImpl<SDValue> &Sequence,
                         BitVector *UndefElements = nullptr) const;

/// Find the shortest repeating sequence of values in the build vector.
///
/// e.g. { u, X, u, X, u, u, X, u } -> { X }
///      { X, Y, u, Y, u, u, X, u } -> { X, Y }
///
/// Currently this must be a power-of-2 build vector.
/// If passed a non-null UndefElements bitvector, it will resize it to match
/// the original vector width and set the bits where elements are undef.
/// If result is false, Sequence will be empty.
bool getRepeatedSequence(SmallVectorImpl<SDValue> &Sequence,
                         BitVector *UndefElements = nullptr) const;

/// Returns the demanded splatted constant or null if this is not a constant
/// splat.
///
/// The DemandedElts mask indicates the elements that must be in the splat.
/// If passed a non-null UndefElements bitvector, it will resize it to match
/// the vector width and set the bits where elements are undef.
ConstantSDNode *
getConstantSplatNode(const APInt &DemandedElts,
                     BitVector *UndefElements = nullptr) const;

/// Returns the splatted constant or null if this is not a constant
/// splat.
///
/// If passed a non-null UndefElements bitvector, it will resize it to match
/// the vector width and set the bits where elements are undef.
ConstantSDNode *
getConstantSplatNode(BitVector *UndefElements = nullptr) const;

/// Returns the demanded splatted constant FP or null if this is not a
/// constant FP splat.
///
/// The DemandedElts mask indicates the elements that must be in the splat.
/// If passed a non-null UndefElements bitvector, it will resize it to match
/// the vector width and set the bits where elements are undef.
ConstantFPSDNode *
getConstantFPSplatNode(const APInt &DemandedElts,
                       BitVector *UndefElements = nullptr) const;

/// Returns the splatted constant FP or null if this is not a constant
/// FP splat.
///
/// If passed a non-null UndefElements bitvector, it will resize it to match
/// the vector width and set the bits where elements are undef.
ConstantFPSDNode *
getConstantFPSplatNode(BitVector *UndefElements = nullptr) const;

/// If this is a constant FP splat and the splatted constant FP is an
/// exact power or 2, return the log base 2 integer value.  Otherwise,
/// return -1.
///
/// The BitWidth specifies the necessary bit precision.
int32_t getConstantFPSplatPow2ToLog2Int(BitVector *UndefElements,
                                        uint32_t BitWidth) const;

bool isConstant() const;

static bool classof(const SDNode *N) {
  return N->getOpcode() == ISD::BUILD_VECTOR;
}
2039};

2041/// An SDNode that holds an arbitrary LLVM IR Value. This is
2042/// used when the SelectionDAG needs to make a simple reference to something
2043/// in the LLVM IR representation.
2044///
2045class SrcValueSDNode : public SDNode {
friend class SelectionDAG;

const Value *V;

/// Create a SrcValue for a general value.
explicit SrcValueSDNode(const Value *v)
  : SDNode(ISD::SRCVALUE, 0, DebugLoc(), getSDVTList(MVT::Other)), V(v) {}

2054public:
/// Return the contained Value.
const Value *getValue() const { return V; }

static bool classof(const SDNode *N) {
  return N->getOpcode() == ISD::SRCVALUE;
}
2061};

2063class MDNodeSDNode : public SDNode {
friend class SelectionDAG;

const MDNode *MD;

explicit MDNodeSDNode(const MDNode *md)
: SDNode(ISD::MDNODE_SDNODE, 0, DebugLoc(), getSDVTList(MVT::Other)), MD(md)
{}

2072public:
const MDNode *getMD() const { return MD; }

static bool classof(const SDNode *N) {
  return N->getOpcode() == ISD::MDNODE_SDNODE;
}
2078};

2080class RegisterSDNode : public SDNode {
friend class SelectionDAG;

Register Reg;

RegisterSDNode(Register reg, EVT VT)
  : SDNode(ISD::Register, 0, DebugLoc(), getSDVTList(VT)), Reg(reg) {}

2088public:
Register getReg() const { return Reg; }

static bool classof(const SDNode *N) {
  return N->getOpcode() == ISD::Register;
}
2094};

2096class RegisterMaskSDNode : public SDNode {
friend class SelectionDAG;

// The memory for RegMask is not owned by the node.
const uint32_t *RegMask;

RegisterMaskSDNode(const uint32_t *mask)
  : SDNode(ISD::RegisterMask, 0, DebugLoc(), getSDVTList(MVT::Untyped)),
    RegMask(mask) {}

2106public:
const uint32_t *getRegMask() const { return RegMask; }

static bool classof(const SDNode *N) {
  return N->getOpcode() == ISD::RegisterMask;
}
2112};

2114class BlockAddressSDNode : public SDNode {
friend class SelectionDAG;

const BlockAddress *BA;
int64_t Offset;
unsigned TargetFlags;

BlockAddressSDNode(unsigned NodeTy, EVT VT, const BlockAddress *ba,
                   int64_t o, unsigned Flags)
  : SDNode(NodeTy, 0, DebugLoc(), getSDVTList(VT)),
           BA(ba), Offset(o), TargetFlags(Flags) {}

2126public:
const BlockAddress *getBlockAddress() const { return BA; }
int64_t getOffset() const { return Offset; }
unsigned getTargetFlags() const { return TargetFlags; }

static bool classof(const SDNode *N) {
  return N->getOpcode() == ISD::BlockAddress ||
         N->getOpcode() == ISD::TargetBlockAddress;
}
2135};

2137class LabelSDNode : public SDNode {
friend class SelectionDAG;

MCSymbol *Label;

LabelSDNode(unsigned Opcode, unsigned Order, const DebugLoc &dl, MCSymbol *L)
    : SDNode(Opcode, Order, dl, getSDVTList(MVT::Other)), Label(L) {
  assert(LabelSDNode::classof(this) && "not a label opcode")(static_cast <bool> (LabelSDNode::classof(this) &&
 "not a label opcode") ? void (0) : __assert_fail ("LabelSDNode::classof(this) && \"not a label opcode\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 2144, __extension__ __PRETTY_FUNCTION__));
}

2147public:
MCSymbol *getLabel() const { return Label; }

static bool classof(const SDNode *N) {
  return N->getOpcode() == ISD::EH_LABEL ||
         N->getOpcode() == ISD::ANNOTATION_LABEL;
}
2154};

2156class ExternalSymbolSDNode : public SDNode {
friend class SelectionDAG;

const char *Symbol;
unsigned TargetFlags;

ExternalSymbolSDNode(bool isTarget, const char *Sym, unsigned TF, EVT VT)
    : SDNode(isTarget ? ISD::TargetExternalSymbol : ISD::ExternalSymbol, 0,
             DebugLoc(), getSDVTList(VT)),
      Symbol(Sym), TargetFlags(TF) {}

2167public:
const char *getSymbol() const { return Symbol; }
unsigned getTargetFlags() const { return TargetFlags; }

static bool classof(const SDNode *N) {
  return N->getOpcode() == ISD::ExternalSymbol ||
         N->getOpcode() == ISD::TargetExternalSymbol;
}
2175};

2177class MCSymbolSDNode : public SDNode {
friend class SelectionDAG;

MCSymbol *Symbol;

MCSymbolSDNode(MCSymbol *Symbol, EVT VT)
    : SDNode(ISD::MCSymbol, 0, DebugLoc(), getSDVTList(VT)), Symbol(Symbol) {}

2185public:
MCSymbol *getMCSymbol() const { return Symbol; }

static bool classof(const SDNode *N) {
  return N->getOpcode() == ISD::MCSymbol;
}
2191};

2193class CondCodeSDNode : public SDNode {
friend class SelectionDAG;

ISD::CondCode Condition;

explicit CondCodeSDNode(ISD::CondCode Cond)
  : SDNode(ISD::CONDCODE, 0, DebugLoc(), getSDVTList(MVT::Other)),
    Condition(Cond) {}

2202public:
ISD::CondCode get() const { return Condition; }

static bool classof(const SDNode *N) {
  return N->getOpcode() == ISD::CONDCODE;
}
2208};

2210/// This class is used to represent EVT's, which are used
2211/// to parameterize some operations.
2212class VTSDNode : public SDNode {
friend class SelectionDAG;

EVT ValueType;

explicit VTSDNode(EVT VT)
  : SDNode(ISD::VALUETYPE, 0, DebugLoc(), getSDVTList(MVT::Other)),
    ValueType(VT) {}

2221public:
EVT getVT() const { return ValueType; }

static bool classof(const SDNode *N) {
  return N->getOpcode() == ISD::VALUETYPE;
}
2227};

2229/// Base class for LoadSDNode and StoreSDNode
2230class LSBaseSDNode : public MemSDNode {
2231public:
LSBaseSDNode(ISD::NodeType NodeTy, unsigned Order, const DebugLoc &dl,
             SDVTList VTs, ISD::MemIndexedMode AM, EVT MemVT,
             MachineMemOperand *MMO)
    : MemSDNode(NodeTy, Order, dl, VTs, MemVT, MMO) {
  LSBaseSDNodeBits.AddressingMode = AM;
  assert(getAddressingMode() == AM && "Value truncated")(static_cast <bool> (getAddressingMode() == AM &&
 "Value truncated") ? void (0) : __assert_fail ("getAddressingMode() == AM && \"Value truncated\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 2237, __extension__ __PRETTY_FUNCTION__));
}

const SDValue &getOffset() const {
  return getOperand(getOpcode() == ISD::LOAD ? 2 : 3);
}

/// Return the addressing mode for this load or store:
/// unindexed, pre-inc, pre-dec, post-inc, or post-dec.
ISD::MemIndexedMode getAddressingMode() const {
  return static_cast<ISD::MemIndexedMode>(LSBaseSDNodeBits.AddressingMode);
}

/// Return true if this is a pre/post inc/dec load/store.
bool isIndexed() const { return getAddressingMode() != ISD::UNINDEXED; }

/// Return true if this is NOT a pre/post inc/dec load/store.
bool isUnindexed() const { return getAddressingMode() == ISD::UNINDEXED; }

static bool classof(const SDNode *N) {
  return N->getOpcode() == ISD::LOAD ||
         N->getOpcode() == ISD::STORE;
}
2260};

2262/// This class is used to represent ISD::LOAD nodes.
2263class LoadSDNode : public LSBaseSDNode {
friend class SelectionDAG;

LoadSDNode(unsigned Order, const DebugLoc &dl, SDVTList VTs,
           ISD::MemIndexedMode AM, ISD::LoadExtType ETy, EVT MemVT,
           MachineMemOperand *MMO)
    : LSBaseSDNode(ISD::LOAD, Order, dl, VTs, AM, MemVT, MMO) {
  LoadSDNodeBits.ExtTy = ETy;
  assert(readMem() && "Load MachineMemOperand is not a load!")(static_cast <bool> (readMem() && "Load MachineMemOperand is not a load!"
) ? void (0) : __assert_fail ("readMem() && \"Load MachineMemOperand is not a load!\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 2271, __extension__ __PRETTY_FUNCTION__));
  assert(!writeMem() && "Load MachineMemOperand is a store!")(static_cast <bool> (!writeMem() && "Load MachineMemOperand is a store!"
) ? void (0) : __assert_fail ("!writeMem() && \"Load MachineMemOperand is a store!\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 2272, __extension__ __PRETTY_FUNCTION__));
}

2275public:
/// Return whether this is a plain node,
/// or one of the varieties of value-extending loads.
ISD::LoadExtType getExtensionType() const {
  return static_cast<ISD::LoadExtType>(LoadSDNodeBits.ExtTy);
}

const SDValue &getBasePtr() const { return getOperand(1); }
const SDValue &getOffset() const { return getOperand(2); }

static bool classof(const SDNode *N) {
  return N->getOpcode() == ISD::LOAD;
}
2288};

2290/// This class is used to represent ISD::STORE nodes.
2291class StoreSDNode : public LSBaseSDNode {
friend class SelectionDAG;

StoreSDNode(unsigned Order, const DebugLoc &dl, SDVTList VTs,
            ISD::MemIndexedMode AM, bool isTrunc, EVT MemVT,
            MachineMemOperand *MMO)
    : LSBaseSDNode(ISD::STORE, Order, dl, VTs, AM, MemVT, MMO) {
  StoreSDNodeBits.IsTruncating = isTrunc;
  assert(!readMem() && "Store MachineMemOperand is a load!")(static_cast <bool> (!readMem() && "Store MachineMemOperand is a load!"
) ? void (0) : __assert_fail ("!readMem() && \"Store MachineMemOperand is a load!\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 2299, __extension__ __PRETTY_FUNCTION__));
  assert(writeMem() && "Store MachineMemOperand is not a store!")(static_cast <bool> (writeMem() && "Store MachineMemOperand is not a store!"
) ? void (0) : __assert_fail ("writeMem() && \"Store MachineMemOperand is not a store!\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 2300, __extension__ __PRETTY_FUNCTION__));
}

2303public:
/// Return true if the op does a truncation before store.
/// For integers this is the same as doing a TRUNCATE and storing the result.
/// For floats, it is the same as doing an FP_ROUND and storing the result.
bool isTruncatingStore() const { return StoreSDNodeBits.IsTruncating; }
void setTruncatingStore(bool Truncating) {
  StoreSDNodeBits.IsTruncating = Truncating;
}

const SDValue &getValue() const { return getOperand(1); }
const SDValue &getBasePtr() const { return getOperand(2); }
const SDValue &getOffset() const { return getOperand(3); }

static bool classof(const SDNode *N) {
  return N->getOpcode() == ISD::STORE;
}
2319};

2321/// This base class is used to represent MLOAD and MSTORE nodes
2322class MaskedLoadStoreSDNode : public MemSDNode {
2323public:
friend class SelectionDAG;

MaskedLoadStoreSDNode(ISD::NodeType NodeTy, unsigned Order,
                      const DebugLoc &dl, SDVTList VTs,
                      ISD::MemIndexedMode AM, EVT MemVT,
                      MachineMemOperand *MMO)
    : MemSDNode(NodeTy, Order, dl, VTs, MemVT, MMO) {
  LSBaseSDNodeBits.AddressingMode = AM;
  assert(getAddressingMode() == AM && "Value truncated")(static_cast <bool> (getAddressingMode() == AM &&
 "Value truncated") ? void (0) : __assert_fail ("getAddressingMode() == AM && \"Value truncated\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 2332, __extension__ __PRETTY_FUNCTION__));
}

// MaskedLoadSDNode (Chain, ptr, offset, mask, passthru)
// MaskedStoreSDNode (Chain, data, ptr, offset, mask)
// Mask is a vector of i1 elements
const SDValue &getOffset() const {
  return getOperand(getOpcode() == ISD::MLOAD ? 2 : 3);
}
const SDValue &getMask() const {
  return getOperand(getOpcode() == ISD::MLOAD ? 3 : 4);
}

/// Return the addressing mode for this load or store:
/// unindexed, pre-inc, pre-dec, post-inc, or post-dec.
ISD::MemIndexedMode getAddressingMode() const {
  return static_cast<ISD::MemIndexedMode>(LSBaseSDNodeBits.AddressingMode);
}

/// Return true if this is a pre/post inc/dec load/store.
bool isIndexed() const { return getAddressingMode() != ISD::UNINDEXED; }

/// Return true if this is NOT a pre/post inc/dec load/store.
bool isUnindexed() const { return getAddressingMode() == ISD::UNINDEXED; }

static bool classof(const SDNode *N) {
  return N->getOpcode() == ISD::MLOAD ||
         N->getOpcode() == ISD::MSTORE;
}
2361};

2363/// This class is used to represent an MLOAD node
2364class MaskedLoadSDNode : public MaskedLoadStoreSDNode {
2365public:
friend class SelectionDAG;

MaskedLoadSDNode(unsigned Order, const DebugLoc &dl, SDVTList VTs,
                 ISD::MemIndexedMode AM, ISD::LoadExtType ETy,
                 bool IsExpanding, EVT MemVT, MachineMemOperand *MMO)
    : MaskedLoadStoreSDNode(ISD::MLOAD, Order, dl, VTs, AM, MemVT, MMO) {
  LoadSDNodeBits.ExtTy = ETy;
  LoadSDNodeBits.IsExpanding = IsExpanding;
}

ISD::LoadExtType getExtensionType() const {
  return static_cast<ISD::LoadExtType>(LoadSDNodeBits.ExtTy);
}

const SDValue &getBasePtr() const { return getOperand(1); }
const SDValue &getOffset() const { return getOperand(2); }
const SDValue &getMask() const { return getOperand(3); }
const SDValue &getPassThru() const { return getOperand(4); }

static bool classof(const SDNode *N) {
  return N->getOpcode() == ISD::MLOAD;
}

bool isExpandingLoad() const { return LoadSDNodeBits.IsExpanding; }
2390};

2392/// This class is used to represent an MSTORE node
2393class MaskedStoreSDNode : public MaskedLoadStoreSDNode {
2394public:
friend class SelectionDAG;

MaskedStoreSDNode(unsigned Order, const DebugLoc &dl, SDVTList VTs,
                  ISD::MemIndexedMode AM, bool isTrunc, bool isCompressing,
                  EVT MemVT, MachineMemOperand *MMO)
    : MaskedLoadStoreSDNode(ISD::MSTORE, Order, dl, VTs, AM, MemVT, MMO) {
  StoreSDNodeBits.IsTruncating = isTrunc;
  StoreSDNodeBits.IsCompressing = isCompressing;
}

/// Return true if the op does a truncation before store.
/// For integers this is the same as doing a TRUNCATE and storing the result.
/// For floats, it is the same as doing an FP_ROUND and storing the result.
bool isTruncatingStore() const { return StoreSDNodeBits.IsTruncating; }

/// Returns true if the op does a compression to the vector before storing.
/// The node contiguously stores the active elements (integers or floats)
/// in src (those with their respective bit set in writemask k) to unaligned
/// memory at base_addr.
bool isCompressingStore() const { return StoreSDNodeBits.IsCompressing; }

const SDValue &getValue() const { return getOperand(1); }
const SDValue &getBasePtr() const { return getOperand(2); }
const SDValue &getOffset() const { return getOperand(3); }
const SDValue &getMask() const { return getOperand(4); }

static bool classof(const SDNode *N) {
  return N->getOpcode() == ISD::MSTORE;
}
2424};

2426/// This is a base class used to represent
2427/// MGATHER and MSCATTER nodes
2428///
2429class MaskedGatherScatterSDNode : public MemSDNode {
2430public:
friend class SelectionDAG;

MaskedGatherScatterSDNode(ISD::NodeType NodeTy, unsigned Order,
                          const DebugLoc &dl, SDVTList VTs, EVT MemVT,
                          MachineMemOperand *MMO, ISD::MemIndexType IndexType)
    : MemSDNode(NodeTy, Order, dl, VTs, MemVT, MMO) {
  LSBaseSDNodeBits.AddressingMode = IndexType;
  assert(getIndexType() == IndexType && "Value truncated")(static_cast <bool> (getIndexType() == IndexType &&
 "Value truncated") ? void (0) : __assert_fail ("getIndexType() == IndexType && \"Value truncated\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 2438, __extension__ __PRETTY_FUNCTION__));
}

/// How is Index applied to BasePtr when computing addresses.
ISD::MemIndexType getIndexType() const {
  return static_cast<ISD::MemIndexType>(LSBaseSDNodeBits.AddressingMode);
}
void setIndexType(ISD::MemIndexType IndexType) {
  LSBaseSDNodeBits.AddressingMode = IndexType;
}
bool isIndexScaled() const {
  return (getIndexType() == ISD::SIGNED_SCALED) ||
         (getIndexType() == ISD::UNSIGNED_SCALED);
}
bool isIndexSigned() const {
  return (getIndexType() == ISD::SIGNED_SCALED) ||
         (getIndexType() == ISD::SIGNED_UNSCALED);
}

// In the both nodes address is Op1, mask is Op2:
// MaskedGatherSDNode  (Chain, passthru, mask, base, index, scale)
// MaskedScatterSDNode (Chain, value, mask, base, index, scale)
// Mask is a vector of i1 elements
const SDValue &getBasePtr() const { return getOperand(3); }
const SDValue &getIndex()   const { return getOperand(4); }
const SDValue &getMask()    const { return getOperand(2); }
const SDValue &getScale()   const { return getOperand(5); }

static bool classof(const SDNode *N) {
  return N->getOpcode() == ISD::MGATHER ||
         N->getOpcode() == ISD::MSCATTER;
}
2470};

2472/// This class is used to represent an MGATHER node
2473///
2474class MaskedGatherSDNode : public MaskedGatherScatterSDNode {
2475public:
friend class SelectionDAG;

MaskedGatherSDNode(unsigned Order, const DebugLoc &dl, SDVTList VTs,
                   EVT MemVT, MachineMemOperand *MMO,
                   ISD::MemIndexType IndexType, ISD::LoadExtType ETy)
    : MaskedGatherScatterSDNode(ISD::MGATHER, Order, dl, VTs, MemVT, MMO,
                                IndexType) {
  LoadSDNodeBits.ExtTy = ETy;
}

const SDValue &getPassThru() const { return getOperand(1); }

ISD::LoadExtType getExtensionType() const {
  return ISD::LoadExtType(LoadSDNodeBits.ExtTy);
}

static bool classof(const SDNode *N) {
  return N->getOpcode() == ISD::MGATHER;
}
2495};

2497/// This class is used to represent an MSCATTER node
2498///
2499class MaskedScatterSDNode : public MaskedGatherScatterSDNode {
2500public:
friend class SelectionDAG;

MaskedScatterSDNode(unsigned Order, const DebugLoc &dl, SDVTList VTs,
                    EVT MemVT, MachineMemOperand *MMO,
                    ISD::MemIndexType IndexType, bool IsTrunc)
    : MaskedGatherScatterSDNode(ISD::MSCATTER, Order, dl, VTs, MemVT, MMO,
                                IndexType) {
  StoreSDNodeBits.IsTruncating = IsTrunc;
}

/// Return true if the op does a truncation before store.
/// For integers this is the same as doing a TRUNCATE and storing the result.
/// For floats, it is the same as doing an FP_ROUND and storing the result.
bool isTruncatingStore() const { return StoreSDNodeBits.IsTruncating; }

const SDValue &getValue() const { return getOperand(1); }

static bool classof(const SDNode *N) {
  return N->getOpcode() == ISD::MSCATTER;
}
2521};

2523/// An SDNode that represents everything that will be needed
2524/// to construct a MachineInstr. These nodes are created during the
2525/// instruction selection proper phase.
2526///
2527/// Note that the only supported way to set the `memoperands` is by calling the
2528/// `SelectionDAG::setNodeMemRefs` function as the memory management happens
2529/// inside the DAG rather than in the node.
2530class MachineSDNode : public SDNode {
2531private:
friend class SelectionDAG;

MachineSDNode(unsigned Opc, unsigned Order, const DebugLoc &DL, SDVTList VTs)
    : SDNode(Opc, Order, DL, VTs) {}

// We use a pointer union between a single `MachineMemOperand` pointer and
// a pointer to an array of `MachineMemOperand` pointers. This is null when
// the number of these is zero, the single pointer variant used when the
// number is one, and the array is used for larger numbers.
//
// The array is allocated via the `SelectionDAG`'s allocator and so will
// always live until the DAG is cleaned up and doesn't require ownership here.
//
// We can't use something simpler like `TinyPtrVector` here because `SDNode`
// subclasses aren't managed in a conforming C++ manner. See the comments on
// `SelectionDAG::MorphNodeTo` which details what all goes on, but the
// constraint here is that these don't manage memory with their constructor or
// destructor and can be initialized to a good state even if they start off
// uninitialized.
PointerUnion<MachineMemOperand *, MachineMemOperand **> MemRefs = {};

// Note that this could be folded into the above `MemRefs` member if doing so
// is advantageous at some point. We don't need to store this in most cases.
// However, at the moment this doesn't appear to make the allocation any
// smaller and makes the code somewhat simpler to read.
int NumMemRefs = 0;

2559public:
using mmo_iterator = ArrayRef<MachineMemOperand *>::const_iterator;

ArrayRef<MachineMemOperand *> memoperands() const {
  // Special case the common cases.
  if (NumMemRefs == 0)
    return {};
  if (NumMemRefs == 1)
    return makeArrayRef(MemRefs.getAddrOfPtr1(), 1);

  // Otherwise we have an actual array.
  return makeArrayRef(MemRefs.get<MachineMemOperand **>(), NumMemRefs);
}
mmo_iterator memoperands_begin() const { return memoperands().begin(); }
mmo_iterator memoperands_end() const { return memoperands().end(); }
bool memoperands_empty() const { return memoperands().empty(); }

/// Clear out the memory reference descriptor list.
void clearMemRefs() {
  MemRefs = nullptr;
  NumMemRefs = 0;
}

static bool classof(const SDNode *N) {
  return N->isMachineOpcode();
}
2585};

2587/// An SDNode that records if a register contains a value that is guaranteed to
2588/// be aligned accordingly.
2589class AssertAlignSDNode : public SDNode {
Align Alignment;

2592public:
AssertAlignSDNode(unsigned Order, const DebugLoc &DL, EVT VT, Align A)
    : SDNode(ISD::AssertAlign, Order, DL, getSDVTList(VT)), Alignment(A) {}

Align getAlign() const { return Alignment; }

static bool classof(const SDNode *N) {
  return N->getOpcode() == ISD::AssertAlign;
}
2601};

2603class SDNodeIterator {
const SDNode *Node;
unsigned Operand;

SDNodeIterator(const SDNode *N, unsigned Op) : Node(N), Operand(Op) {}

2609public:
using iterator_category = std::forward_iterator_tag;
using value_type = SDNode;
using difference_type = std::ptrdiff_t;
using pointer = value_type *;
using reference = value_type &;

bool operator==(const SDNodeIterator& x) const {
  return Operand == x.Operand;
}
bool operator!=(const SDNodeIterator& x) const { return !operator==(x); }

pointer operator*() const {
  return Node->getOperand(Operand).getNode();
}
pointer operator->() const { return operator*(); }

SDNodeIterator& operator++() {                // Preincrement
  ++Operand;
  return *this;
}
SDNodeIterator operator++(int) { // Postincrement
  SDNodeIterator tmp = *this; ++*this; return tmp;
}
size_t operator-(SDNodeIterator Other) const {
  assert(Node == Other.Node &&(static_cast <bool> (Node == Other.Node && "Cannot compare iterators of two different nodes!"
) ? void (0) : __assert_fail ("Node == Other.Node && \"Cannot compare iterators of two different nodes!\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 2635, __extension__ __PRETTY_FUNCTION__))
         "Cannot compare iterators of two different nodes!")(static_cast <bool> (Node == Other.Node && "Cannot compare iterators of two different nodes!"
) ? void (0) : __assert_fail ("Node == Other.Node && \"Cannot compare iterators of two different nodes!\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 2635, __extension__ __PRETTY_FUNCTION__));
  return Operand - Other.Operand;
}

static SDNodeIterator begin(const SDNode *N) { return SDNodeIterator(N, 0); }
static SDNodeIterator end  (const SDNode *N) {
  return SDNodeIterator(N, N->getNumOperands());
}

unsigned getOperand() const { return Operand; }
const SDNode *getNode() const { return Node; }
2646};

2648template <> struct GraphTraits<SDNode*> {
using NodeRef = SDNode *;
using ChildIteratorType = SDNodeIterator;

static NodeRef getEntryNode(SDNode *N) { return N; }

static ChildIteratorType child_begin(NodeRef N) {
  return SDNodeIterator::begin(N);
}

static ChildIteratorType child_end(NodeRef N) {
  return SDNodeIterator::end(N);
}
2661};

2663/// A representation of the largest SDNode, for use in sizeof().
2664///
2665/// This needs to be a union because the largest node differs on 32 bit systems
2666/// with 4 and 8 byte pointer alignment, respectively.
2667using LargestSDNode = AlignedCharArrayUnion<AtomicSDNode, TargetIndexSDNode,
                                          BlockAddressSDNode,
                                          GlobalAddressSDNode,
                                          PseudoProbeSDNode>;

2672/// The SDNode class with the greatest alignment requirement.
2673using MostAlignedSDNode = GlobalAddressSDNode;

2675namespace ISD {

/// Returns true if the specified node is a non-extending and unindexed load.
inline bool isNormalLoad(const SDNode *N) {
  const LoadSDNode *Ld = dyn_cast<LoadSDNode>(N);
  return Ld && Ld->getExtensionType() == ISD::NON_EXTLOAD &&
    Ld->getAddressingMode() == ISD::UNINDEXED;
}

/// Returns true if the specified node is a non-extending load.
inline bool isNON_EXTLoad(const SDNode *N) {
  return isa<LoadSDNode>(N) &&
    cast<LoadSDNode>(N)->getExtensionType() == ISD::NON_EXTLOAD;
}

/// Returns true if the specified node is a EXTLOAD.
inline bool isEXTLoad(const SDNode *N) {
  return isa<LoadSDNode>(N) &&
    cast<LoadSDNode>(N)->getExtensionType() == ISD::EXTLOAD;
}

/// Returns true if the specified node is a SEXTLOAD.
inline bool isSEXTLoad(const SDNode *N) {
  return isa<LoadSDNode>(N) &&
    cast<LoadSDNode>(N)->getExtensionType() == ISD::SEXTLOAD;
}

/// Returns true if the specified node is a ZEXTLOAD.
inline bool isZEXTLoad(const SDNode *N) {
  return isa<LoadSDNode>(N) &&
    cast<LoadSDNode>(N)->getExtensionType() == ISD::ZEXTLOAD;
}

/// Returns true if the specified node is an unindexed load.
inline bool isUNINDEXEDLoad(const SDNode *N) {
  return isa<LoadSDNode>(N) &&
    cast<LoadSDNode>(N)->getAddressingMode() == ISD::UNINDEXED;
}

/// Returns true if the specified node is a non-truncating
/// and unindexed store.
inline bool isNormalStore(const SDNode *N) {
  const StoreSDNode *St = dyn_cast<StoreSDNode>(N);
  return St && !St->isTruncatingStore() &&
    St->getAddressingMode() == ISD::UNINDEXED;
}

/// Returns true if the specified node is an unindexed store.
inline bool isUNINDEXEDStore(const SDNode *N) {
  return isa<StoreSDNode>(N) &&
    cast<StoreSDNode>(N)->getAddressingMode() == ISD::UNINDEXED;
}

/// Attempt to match a unary predicate against a scalar/splat constant or
/// every element of a constant BUILD_VECTOR.
/// If AllowUndef is true, then UNDEF elements will pass nullptr to Match.
bool matchUnaryPredicate(SDValue Op,
                         std::function<bool(ConstantSDNode *)> Match,
                         bool AllowUndefs = false);

/// Attempt to match a binary predicate against a pair of scalar/splat
/// constants or every element of a pair of constant BUILD_VECTORs.
/// If AllowUndef is true, then UNDEF elements will pass nullptr to Match.
/// If AllowTypeMismatch is true then RetType + ArgTypes don't need to match.
bool matchBinaryPredicate(
    SDValue LHS, SDValue RHS,
    std::function<bool(ConstantSDNode *, ConstantSDNode *)> Match,
    bool AllowUndefs = false, bool AllowTypeMismatch = false);

/// Returns true if the specified value is the overflow result from one
/// of the overflow intrinsic nodes.
inline bool isOverflowIntrOpRes(SDValue Op) {
  unsigned Opc = Op.getOpcode();
  return (Op.getResNo() == 1 &&
          (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO ||
           Opc == ISD::USUBO || Opc == ISD::SMULO || Opc == ISD::UMULO));
}

2753} // end namespace ISD

2755} // end namespace llvm

2757#endif // LLVM_CODEGEN_SELECTIONDAGNODES_H