/build/source/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp

Bug Summary

File:	build/source/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
Warning:	line 1721, column 24 The result of the right shift is undefined due to shifting by '4294967295', which is greater or equal to the width of type 'uint64_t'

Annotated Source Code

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clang -cc1 -cc1 -triple x86_64-pc-linux-gnu -analyze -disable-free -clear-ast-before-backend -disable-llvm-verifier -discard-value-names -main-file-name SystemZInstrInfo.cpp -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=cplusplus -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -analyzer-config-compatibility-mode=true -mrelocation-model pic -pic-level 2 -mframe-pointer=none -fmath-errno -ffp-contract=on -fno-rounding-math -mconstructor-aliases -funwind-tables=2 -target-cpu x86-64 -tune-cpu generic -debugger-tuning=gdb -ffunction-sections -fdata-sections -fcoverage-compilation-dir=/build/source/build-llvm/tools/clang/stage2-bins -resource-dir /usr/lib/llvm-16/lib/clang/16 -I lib/Target/SystemZ -I /build/source/llvm/lib/Target/SystemZ -I include -I /build/source/llvm/include -D _DEBUG -D _GNU_SOURCE -D __STDC_CONSTANT_MACROS -D __STDC_FORMAT_MACROS -D __STDC_LIMIT_MACROS -D _FORTIFY_SOURCE=2 -D NDEBUG -U NDEBUG -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/10/../../../../include/c++/10 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/10/../../../../include/x86_64-linux-gnu/c++/10 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/10/../../../../include/c++/10/backward -internal-isystem /usr/lib/llvm-16/lib/clang/16/include -internal-isystem /usr/local/include -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/10/../../../../x86_64-linux-gnu/include -internal-externc-isystem /usr/include/x86_64-linux-gnu -internal-externc-isystem /include -internal-externc-isystem /usr/include -fmacro-prefix-map=/build/source/build-llvm/tools/clang/stage2-bins=build-llvm/tools/clang/stage2-bins -fmacro-prefix-map=/build/source/= -fcoverage-prefix-map=/build/source/build-llvm/tools/clang/stage2-bins=build-llvm/tools/clang/stage2-bins -fcoverage-prefix-map=/build/source/= -source-date-epoch 1673561342 -O2 -Wno-unused-command-line-argument -Wno-unused-parameter -Wwrite-strings -Wno-missing-field-initializers -Wno-long-long -Wno-maybe-uninitialized -Wno-class-memaccess -Wno-redundant-move -Wno-pessimizing-move -Wno-noexcept-type -Wno-comment -Wno-misleading-indentation -std=c++17 -fdeprecated-macro -fdebug-compilation-dir=/build/source/build-llvm/tools/clang/stage2-bins -fdebug-prefix-map=/build/source/build-llvm/tools/clang/stage2-bins=build-llvm/tools/clang/stage2-bins -fdebug-prefix-map=/build/source/= -ferror-limit 19 -fvisibility=hidden -fvisibility-inlines-hidden -stack-protector 2 -fgnuc-version=4.2.1 -fcolor-diagnostics -vectorize-loops -vectorize-slp -analyzer-output=html -analyzer-config stable-report-filename=true -faddrsig -D__GCC_HAVE_DWARF2_CFI_ASM=1 -o /tmp/scan-build-2023-01-13-042150-16221-1 -x c++ /build/source/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp

/build/source/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp

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1//===-- SystemZInstrInfo.cpp - SystemZ instruction information ------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the SystemZ implementation of the TargetInstrInfo class.
10//
11//===----------------------------------------------------------------------===//

13#include "SystemZInstrInfo.h"
14#include "MCTargetDesc/SystemZMCTargetDesc.h"
15#include "SystemZ.h"
16#include "SystemZInstrBuilder.h"
17#include "SystemZSubtarget.h"
18#include "llvm/ADT/Statistic.h"
19#include "llvm/CodeGen/LiveInterval.h"
20#include "llvm/CodeGen/LiveIntervals.h"
21#include "llvm/CodeGen/LivePhysRegs.h"
22#include "llvm/CodeGen/LiveVariables.h"
23#include "llvm/CodeGen/MachineBasicBlock.h"
24#include "llvm/CodeGen/MachineFrameInfo.h"
25#include "llvm/CodeGen/MachineFunction.h"
26#include "llvm/CodeGen/MachineInstr.h"
27#include "llvm/CodeGen/MachineMemOperand.h"
28#include "llvm/CodeGen/MachineOperand.h"
29#include "llvm/CodeGen/MachineRegisterInfo.h"
30#include "llvm/CodeGen/SlotIndexes.h"
31#include "llvm/CodeGen/StackMaps.h"
32#include "llvm/CodeGen/TargetInstrInfo.h"
33#include "llvm/CodeGen/TargetSubtargetInfo.h"
34#include "llvm/CodeGen/VirtRegMap.h"
35#include "llvm/MC/MCInstrDesc.h"
36#include "llvm/MC/MCRegisterInfo.h"
37#include "llvm/Support/BranchProbability.h"
38#include "llvm/Support/ErrorHandling.h"
39#include "llvm/Support/MathExtras.h"
40#include "llvm/Target/TargetMachine.h"
41#include <cassert>
42#include <cstdint>
43#include <iterator>

45using namespace llvm;

47#define GET_INSTRINFO_CTOR_DTOR
48#define GET_INSTRMAP_INFO
49#include "SystemZGenInstrInfo.inc"

51#define DEBUG_TYPE"systemz-II" "systemz-II"

53// Return a mask with Count low bits set.
54static uint64_t allOnes(unsigned int Count) {
return Count == 0 ? 0 : (uint64_t(1) << (Count - 1) << 1) - 1;
56}

58// Pin the vtable to this file.
59void SystemZInstrInfo::anchor() {}

61SystemZInstrInfo::SystemZInstrInfo(SystemZSubtarget &sti)
  : SystemZGenInstrInfo(SystemZ::ADJCALLSTACKDOWN, SystemZ::ADJCALLSTACKUP),
    RI(sti.getSpecialRegisters()->getReturnFunctionAddressRegister()),
    STI(sti) {}

66// MI is a 128-bit load or store.  Split it into two 64-bit loads or stores,
67// each having the opcode given by NewOpcode.
68void SystemZInstrInfo::splitMove(MachineBasicBlock::iterator MI,
                               unsigned NewOpcode) const {
MachineBasicBlock *MBB = MI->getParent();
MachineFunction &MF = *MBB->getParent();

// Get two load or store instructions.  Use the original instruction for one
// of them (arbitrarily the second here) and create a clone for the other.
MachineInstr *EarlierMI = MF.CloneMachineInstr(&*MI);
MBB->insert(MI, EarlierMI);

// Set up the two 64-bit registers and remember super reg and its flags.
MachineOperand &HighRegOp = EarlierMI->getOperand(0);
MachineOperand &LowRegOp = MI->getOperand(0);
Register Reg128 = LowRegOp.getReg();
unsigned Reg128Killed = getKillRegState(LowRegOp.isKill());
unsigned Reg128Undef  = getUndefRegState(LowRegOp.isUndef());
HighRegOp.setReg(RI.getSubReg(HighRegOp.getReg(), SystemZ::subreg_h64));
LowRegOp.setReg(RI.getSubReg(LowRegOp.getReg(), SystemZ::subreg_l64));

if (MI->mayStore()) {
  // Add implicit uses of the super register in case one of the subregs is
  // undefined. We could track liveness and skip storing an undefined
  // subreg, but this is hopefully rare (discovered with llvm-stress).
  // If Reg128 was killed, set kill flag on MI.
  unsigned Reg128UndefImpl = (Reg128Undef | RegState::Implicit);
  MachineInstrBuilder(MF, EarlierMI).addReg(Reg128, Reg128UndefImpl);
  MachineInstrBuilder(MF, MI).addReg(Reg128, (Reg128UndefImpl | Reg128Killed));
}

// The address in the first (high) instruction is already correct.
// Adjust the offset in the second (low) instruction.
MachineOperand &HighOffsetOp = EarlierMI->getOperand(2);
MachineOperand &LowOffsetOp = MI->getOperand(2);
LowOffsetOp.setImm(LowOffsetOp.getImm() + 8);

// Clear the kill flags on the registers in the first instruction.
if (EarlierMI->getOperand(0).isReg() && EarlierMI->getOperand(0).isUse())
  EarlierMI->getOperand(0).setIsKill(false);
EarlierMI->getOperand(1).setIsKill(false);
EarlierMI->getOperand(3).setIsKill(false);

// Set the opcodes.
unsigned HighOpcode = getOpcodeForOffset(NewOpcode, HighOffsetOp.getImm());
unsigned LowOpcode = getOpcodeForOffset(NewOpcode, LowOffsetOp.getImm());
assert(HighOpcode && LowOpcode && "Both offsets should be in range")(static_cast <bool> (HighOpcode && LowOpcode &&
 "Both offsets should be in range") ? void (0) : __assert_fail
 ("HighOpcode && LowOpcode && \"Both offsets should be in range\""
, "llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp", 112, __extension__
 __PRETTY_FUNCTION__));

EarlierMI->setDesc(get(HighOpcode));
MI->setDesc(get(LowOpcode));
116}

118// Split ADJDYNALLOC instruction MI.
119void SystemZInstrInfo::splitAdjDynAlloc(MachineBasicBlock::iterator MI) const {
MachineBasicBlock *MBB = MI->getParent();
MachineFunction &MF = *MBB->getParent();
MachineFrameInfo &MFFrame = MF.getFrameInfo();
MachineOperand &OffsetMO = MI->getOperand(2);
SystemZCallingConventionRegisters *Regs = STI.getSpecialRegisters();

uint64_t Offset = (MFFrame.getMaxCallFrameSize() +
                   Regs->getCallFrameSize() +
                   Regs->getStackPointerBias() +
                   OffsetMO.getImm());
unsigned NewOpcode = getOpcodeForOffset(SystemZ::LA, Offset);
assert(NewOpcode && "No support for huge argument lists yet")(static_cast <bool> (NewOpcode && "No support for huge argument lists yet"
) ? void (0) : __assert_fail ("NewOpcode && \"No support for huge argument lists yet\""
, "llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp", 131, __extension__
 __PRETTY_FUNCTION__));
MI->setDesc(get(NewOpcode));
OffsetMO.setImm(Offset);
134}

136// MI is an RI-style pseudo instruction.  Replace it with LowOpcode
137// if the first operand is a low GR32 and HighOpcode if the first operand
138// is a high GR32.  ConvertHigh is true if LowOpcode takes a signed operand
139// and HighOpcode takes an unsigned 32-bit operand.  In those cases,
140// MI has the same kind of operand as LowOpcode, so needs to be converted
141// if HighOpcode is used.
142void SystemZInstrInfo::expandRIPseudo(MachineInstr &MI, unsigned LowOpcode,
                                    unsigned HighOpcode,
                                    bool ConvertHigh) const {
Register Reg = MI.getOperand(0).getReg();
bool IsHigh = SystemZ::isHighReg(Reg);
MI.setDesc(get(IsHigh ? HighOpcode : LowOpcode));
if (IsHigh && ConvertHigh)
  MI.getOperand(1).setImm(uint32_t(MI.getOperand(1).getImm()));
150}

152// MI is a three-operand RIE-style pseudo instruction.  Replace it with
153// LowOpcodeK if the registers are both low GR32s, otherwise use a move
154// followed by HighOpcode or LowOpcode, depending on whether the target
155// is a high or low GR32.
156void SystemZInstrInfo::expandRIEPseudo(MachineInstr &MI, unsigned LowOpcode,
                                     unsigned LowOpcodeK,
                                     unsigned HighOpcode) const {
Register DestReg = MI.getOperand(0).getReg();
Register SrcReg = MI.getOperand(1).getReg();
bool DestIsHigh = SystemZ::isHighReg(DestReg);
bool SrcIsHigh = SystemZ::isHighReg(SrcReg);
if (!DestIsHigh && !SrcIsHigh)
  MI.setDesc(get(LowOpcodeK));
else {
  if (DestReg != SrcReg) {
    emitGRX32Move(*MI.getParent(), MI, MI.getDebugLoc(), DestReg, SrcReg,
                  SystemZ::LR, 32, MI.getOperand(1).isKill(),
                  MI.getOperand(1).isUndef());
    MI.getOperand(1).setReg(DestReg);
  }
  MI.setDesc(get(DestIsHigh ? HighOpcode : LowOpcode));
  MI.tieOperands(0, 1);
}
175}

177// MI is an RXY-style pseudo instruction.  Replace it with LowOpcode
178// if the first operand is a low GR32 and HighOpcode if the first operand
179// is a high GR32.
180void SystemZInstrInfo::expandRXYPseudo(MachineInstr &MI, unsigned LowOpcode,
                                     unsigned HighOpcode) const {
Register Reg = MI.getOperand(0).getReg();
unsigned Opcode = getOpcodeForOffset(
    SystemZ::isHighReg(Reg) ? HighOpcode : LowOpcode,
    MI.getOperand(2).getImm());
MI.setDesc(get(Opcode));
187}

189// MI is a load-on-condition pseudo instruction with a single register
190// (source or destination) operand.  Replace it with LowOpcode if the
191// register is a low GR32 and HighOpcode if the register is a high GR32.
192void SystemZInstrInfo::expandLOCPseudo(MachineInstr &MI, unsigned LowOpcode,
                                     unsigned HighOpcode) const {
Register Reg = MI.getOperand(0).getReg();
unsigned Opcode = SystemZ::isHighReg(Reg) ? HighOpcode : LowOpcode;
MI.setDesc(get(Opcode));
197}

199// MI is an RR-style pseudo instruction that zero-extends the low Size bits
200// of one GRX32 into another.  Replace it with LowOpcode if both operands
201// are low registers, otherwise use RISB[LH]G.
202void SystemZInstrInfo::expandZExtPseudo(MachineInstr &MI, unsigned LowOpcode,
                                      unsigned Size) const {
MachineInstrBuilder MIB =
  emitGRX32Move(*MI.getParent(), MI, MI.getDebugLoc(),
             MI.getOperand(0).getReg(), MI.getOperand(1).getReg(), LowOpcode,
             Size, MI.getOperand(1).isKill(), MI.getOperand(1).isUndef());

// Keep the remaining operands as-is.
for (const MachineOperand &MO : llvm::drop_begin(MI.operands(), 2))
  MIB.add(MO);

MI.eraseFromParent();
214}

216void SystemZInstrInfo::expandLoadStackGuard(MachineInstr *MI) const {
MachineBasicBlock *MBB = MI->getParent();
MachineFunction &MF = *MBB->getParent();
const Register Reg64 = MI->getOperand(0).getReg();
const Register Reg32 = RI.getSubReg(Reg64, SystemZ::subreg_l32);

// EAR can only load the low subregister so us a shift for %a0 to produce
// the GR containing %a0 and %a1.

// ear <reg>, %a0
BuildMI(*MBB, MI, MI->getDebugLoc(), get(SystemZ::EAR), Reg32)
  .addReg(SystemZ::A0)
  .addReg(Reg64, RegState::ImplicitDefine);

// sllg <reg>, <reg>, 32
BuildMI(*MBB, MI, MI->getDebugLoc(), get(SystemZ::SLLG), Reg64)
  .addReg(Reg64)
  .addReg(0)
  .addImm(32);

// ear <reg>, %a1
BuildMI(*MBB, MI, MI->getDebugLoc(), get(SystemZ::EAR), Reg32)
  .addReg(SystemZ::A1);

// lg <reg>, 40(<reg>)
MI->setDesc(get(SystemZ::LG));
MachineInstrBuilder(MF, MI).addReg(Reg64).addImm(40).addReg(0);
243}

245// Emit a zero-extending move from 32-bit GPR SrcReg to 32-bit GPR
246// DestReg before MBBI in MBB.  Use LowLowOpcode when both DestReg and SrcReg
247// are low registers, otherwise use RISB[LH]G.  Size is the number of bits
248// taken from the low end of SrcReg (8 for LLCR, 16 for LLHR and 32 for LR).
249// KillSrc is true if this move is the last use of SrcReg.
250MachineInstrBuilder
251SystemZInstrInfo::emitGRX32Move(MachineBasicBlock &MBB,
                              MachineBasicBlock::iterator MBBI,
                              const DebugLoc &DL, unsigned DestReg,
                              unsigned SrcReg, unsigned LowLowOpcode,
                              unsigned Size, bool KillSrc,
                              bool UndefSrc) const {
unsigned Opcode;
bool DestIsHigh = SystemZ::isHighReg(DestReg);
bool SrcIsHigh = SystemZ::isHighReg(SrcReg);
if (DestIsHigh && SrcIsHigh)
  Opcode = SystemZ::RISBHH;
else if (DestIsHigh && !SrcIsHigh)
  Opcode = SystemZ::RISBHL;
else if (!DestIsHigh && SrcIsHigh)
  Opcode = SystemZ::RISBLH;
else {
  return BuildMI(MBB, MBBI, DL, get(LowLowOpcode), DestReg)
    .addReg(SrcReg, getKillRegState(KillSrc) | getUndefRegState(UndefSrc));
}
unsigned Rotate = (DestIsHigh != SrcIsHigh ? 32 : 0);
return BuildMI(MBB, MBBI, DL, get(Opcode), DestReg)
  .addReg(DestReg, RegState::Undef)
  .addReg(SrcReg, getKillRegState(KillSrc) | getUndefRegState(UndefSrc))
  .addImm(32 - Size).addImm(128 + 31).addImm(Rotate);
275}

277MachineInstr *SystemZInstrInfo::commuteInstructionImpl(MachineInstr &MI,
                                                     bool NewMI,
                                                     unsigned OpIdx1,
                                                     unsigned OpIdx2) const {
auto cloneIfNew = [NewMI](MachineInstr &MI) -> MachineInstr & {
  if (NewMI)
    return *MI.getParent()->getParent()->CloneMachineInstr(&MI);
  return MI;
};

switch (MI.getOpcode()) {
case SystemZ::SELRMux:
case SystemZ::SELFHR:
case SystemZ::SELR:
case SystemZ::SELGR:
case SystemZ::LOCRMux:
case SystemZ::LOCFHR:
case SystemZ::LOCR:
case SystemZ::LOCGR: {
  auto &WorkingMI = cloneIfNew(MI);
  // Invert condition.
  unsigned CCValid = WorkingMI.getOperand(3).getImm();
  unsigned CCMask = WorkingMI.getOperand(4).getImm();
  WorkingMI.getOperand(4).setImm(CCMask ^ CCValid);
  return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
                                                 OpIdx1, OpIdx2);
}
default:
  return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
}
307}

309// If MI is a simple load or store for a frame object, return the register
310// it loads or stores and set FrameIndex to the index of the frame object.
311// Return 0 otherwise.
312//
313// Flag is SimpleBDXLoad for loads and SimpleBDXStore for stores.
314static int isSimpleMove(const MachineInstr &MI, int &FrameIndex,
                      unsigned Flag) {
const MCInstrDesc &MCID = MI.getDesc();
if ((MCID.TSFlags & Flag) && MI.getOperand(1).isFI() &&
    MI.getOperand(2).getImm() == 0 && MI.getOperand(3).getReg() == 0) {
  FrameIndex = MI.getOperand(1).getIndex();
  return MI.getOperand(0).getReg();
}
return 0;
323}

325unsigned SystemZInstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
                                             int &FrameIndex) const {
return isSimpleMove(MI, FrameIndex, SystemZII::SimpleBDXLoad);
328}

330unsigned SystemZInstrInfo::isStoreToStackSlot(const MachineInstr &MI,
                                            int &FrameIndex) const {
return isSimpleMove(MI, FrameIndex, SystemZII::SimpleBDXStore);
333}

335bool SystemZInstrInfo::isStackSlotCopy(const MachineInstr &MI,
                                     int &DestFrameIndex,
                                     int &SrcFrameIndex) const {
// Check for MVC 0(Length,FI1),0(FI2)
const MachineFrameInfo &MFI = MI.getParent()->getParent()->getFrameInfo();
if (MI.getOpcode() != SystemZ::MVC || !MI.getOperand(0).isFI() ||
    MI.getOperand(1).getImm() != 0 || !MI.getOperand(3).isFI() ||
    MI.getOperand(4).getImm() != 0)
  return false;

// Check that Length covers the full slots.
int64_t Length = MI.getOperand(2).getImm();
unsigned FI1 = MI.getOperand(0).getIndex();
unsigned FI2 = MI.getOperand(3).getIndex();
if (MFI.getObjectSize(FI1) != Length ||
    MFI.getObjectSize(FI2) != Length)
  return false;

DestFrameIndex = FI1;
SrcFrameIndex = FI2;
return true;
356}

358bool SystemZInstrInfo::analyzeBranch(MachineBasicBlock &MBB,
                                   MachineBasicBlock *&TBB,
                                   MachineBasicBlock *&FBB,
                                   SmallVectorImpl<MachineOperand> &Cond,
                                   bool AllowModify) const {
// Most of the code and comments here are boilerplate.

// Start from the bottom of the block and work up, examining the
// terminator instructions.
MachineBasicBlock::iterator I = MBB.end();
while (I != MBB.begin()) {
  --I;
  if (I->isDebugInstr())
    continue;

  // Working from the bottom, when we see a non-terminator instruction, we're
  // done.
  if (!isUnpredicatedTerminator(*I))
    break;

  // A terminator that isn't a branch can't easily be handled by this
  // analysis.
  if (!I->isBranch())
    return true;

  // Can't handle indirect branches.
  SystemZII::Branch Branch(getBranchInfo(*I));
  if (!Branch.hasMBBTarget())
    return true;

  // Punt on compound branches.
  if (Branch.Type != SystemZII::BranchNormal)
    return true;

  if (Branch.CCMask == SystemZ::CCMASK_ANY) {
    // Handle unconditional branches.
    if (!AllowModify) {
      TBB = Branch.getMBBTarget();
      continue;
    }

    // If the block has any instructions after a JMP, delete them.
    MBB.erase(std::next(I), MBB.end());

    Cond.clear();
    FBB = nullptr;

    // Delete the JMP if it's equivalent to a fall-through.
    if (MBB.isLayoutSuccessor(Branch.getMBBTarget())) {
      TBB = nullptr;
      I->eraseFromParent();
      I = MBB.end();
      continue;
    }

    // TBB is used to indicate the unconditinal destination.
    TBB = Branch.getMBBTarget();
    continue;
  }

  // Working from the bottom, handle the first conditional branch.
  if (Cond.empty()) {
    // FIXME: add X86-style branch swap
    FBB = TBB;
    TBB = Branch.getMBBTarget();
    Cond.push_back(MachineOperand::CreateImm(Branch.CCValid));
    Cond.push_back(MachineOperand::CreateImm(Branch.CCMask));
    continue;
  }

  // Handle subsequent conditional branches.
  assert(Cond.size() == 2 && TBB && "Should have seen a conditional branch")(static_cast <bool> (Cond.size() == 2 && TBB &&
 "Should have seen a conditional branch") ? void (0) : __assert_fail
 ("Cond.size() == 2 && TBB && \"Should have seen a conditional branch\""
, "llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp", 429, __extension__
 __PRETTY_FUNCTION__));

  // Only handle the case where all conditional branches branch to the same
  // destination.
  if (TBB != Branch.getMBBTarget())
    return true;

  // If the conditions are the same, we can leave them alone.
  unsigned OldCCValid = Cond[0].getImm();
  unsigned OldCCMask = Cond[1].getImm();
  if (OldCCValid == Branch.CCValid && OldCCMask == Branch.CCMask)
    continue;

  // FIXME: Try combining conditions like X86 does.  Should be easy on Z!
  return false;
}

return false;
447}

449unsigned SystemZInstrInfo::removeBranch(MachineBasicBlock &MBB,
                                      int *BytesRemoved) const {
assert(!BytesRemoved && "code size not handled")(static_cast <bool> (!BytesRemoved && "code size not handled"
) ? void (0) : __assert_fail ("!BytesRemoved && \"code size not handled\""
, "llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp", 451, __extension__
 __PRETTY_FUNCTION__));

// Most of the code and comments here are boilerplate.
MachineBasicBlock::iterator I = MBB.end();
unsigned Count = 0;

while (I != MBB.begin()) {
  --I;
  if (I->isDebugInstr())
    continue;
  if (!I->isBranch())
    break;
  if (!getBranchInfo(*I).hasMBBTarget())
    break;
  // Remove the branch.
  I->eraseFromParent();
  I = MBB.end();
  ++Count;
}

return Count;
472}

474bool SystemZInstrInfo::
475reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
assert(Cond.size() == 2 && "Invalid condition")(static_cast <bool> (Cond.size() == 2 && "Invalid condition"
) ? void (0) : __assert_fail ("Cond.size() == 2 && \"Invalid condition\""
, "llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp", 476, __extension__
 __PRETTY_FUNCTION__));
Cond[1].setImm(Cond[1].getImm() ^ Cond[0].getImm());
return false;
479}

481unsigned SystemZInstrInfo::insertBranch(MachineBasicBlock &MBB,
                                      MachineBasicBlock *TBB,
                                      MachineBasicBlock *FBB,
                                      ArrayRef<MachineOperand> Cond,
                                      const DebugLoc &DL,
                                      int *BytesAdded) const {
// In this function we output 32-bit branches, which should always
// have enough range.  They can be shortened and relaxed by later code
// in the pipeline, if desired.

// Shouldn't be a fall through.
assert(TBB && "insertBranch must not be told to insert a fallthrough")(static_cast <bool> (TBB && "insertBranch must not be told to insert a fallthrough"
) ? void (0) : __assert_fail ("TBB && \"insertBranch must not be told to insert a fallthrough\""
, "llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp", 492, __extension__
 __PRETTY_FUNCTION__));
assert((Cond.size() == 2 || Cond.size() == 0) &&(static_cast <bool> ((Cond.size() == 2 || Cond.size() ==
 0) && "SystemZ branch conditions have one component!"
) ? void (0) : __assert_fail ("(Cond.size() == 2 || Cond.size() == 0) && \"SystemZ branch conditions have one component!\""
, "llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp", 494, __extension__
 __PRETTY_FUNCTION__))
       "SystemZ branch conditions have one component!")(static_cast <bool> ((Cond.size() == 2 || Cond.size() ==
 0) && "SystemZ branch conditions have one component!"
) ? void (0) : __assert_fail ("(Cond.size() == 2 || Cond.size() == 0) && \"SystemZ branch conditions have one component!\""
, "llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp", 494, __extension__
 __PRETTY_FUNCTION__));
assert(!BytesAdded && "code size not handled")(static_cast <bool> (!BytesAdded && "code size not handled"
) ? void (0) : __assert_fail ("!BytesAdded && \"code size not handled\""
, "llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp", 495, __extension__
 __PRETTY_FUNCTION__));

if (Cond.empty()) {
  // Unconditional branch?
  assert(!FBB && "Unconditional branch with multiple successors!")(static_cast <bool> (!FBB && "Unconditional branch with multiple successors!"
) ? void (0) : __assert_fail ("!FBB && \"Unconditional branch with multiple successors!\""
, "llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp", 499, __extension__
 __PRETTY_FUNCTION__));
  BuildMI(&MBB, DL, get(SystemZ::J)).addMBB(TBB);
  return 1;
}

// Conditional branch.
unsigned Count = 0;
unsigned CCValid = Cond[0].getImm();
unsigned CCMask = Cond[1].getImm();
BuildMI(&MBB, DL, get(SystemZ::BRC))
  .addImm(CCValid).addImm(CCMask).addMBB(TBB);
++Count;

if (FBB) {
  // Two-way Conditional branch. Insert the second branch.
  BuildMI(&MBB, DL, get(SystemZ::J)).addMBB(FBB);
  ++Count;
}
return Count;
518}

520bool SystemZInstrInfo::analyzeCompare(const MachineInstr &MI, Register &SrcReg,
                                    Register &SrcReg2, int64_t &Mask,
                                    int64_t &Value) const {
assert(MI.isCompare() && "Caller should have checked for a comparison")(static_cast <bool> (MI.isCompare() && "Caller should have checked for a comparison"
) ? void (0) : __assert_fail ("MI.isCompare() && \"Caller should have checked for a comparison\""
, "llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp", 523, __extension__
 __PRETTY_FUNCTION__));

if (MI.getNumExplicitOperands() == 2 && MI.getOperand(0).isReg() &&
    MI.getOperand(1).isImm()) {
  SrcReg = MI.getOperand(0).getReg();
  SrcReg2 = 0;
  Value = MI.getOperand(1).getImm();
  Mask = ~0;
  return true;
}

return false;
535}

537bool SystemZInstrInfo::canInsertSelect(const MachineBasicBlock &MBB,
                                     ArrayRef<MachineOperand> Pred,
                                     Register DstReg, Register TrueReg,
                                     Register FalseReg, int &CondCycles,
                                     int &TrueCycles,
                                     int &FalseCycles) const {
// Not all subtargets have LOCR instructions.
if (!STI.hasLoadStoreOnCond())
  return false;
if (Pred.size() != 2)
  return false;

// Check register classes.
const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
const TargetRegisterClass *RC =
  RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
if (!RC)
  return false;

// We have LOCR instructions for 32 and 64 bit general purpose registers.
if ((STI.hasLoadStoreOnCond2() &&
     SystemZ::GRX32BitRegClass.hasSubClassEq(RC)) ||
    SystemZ::GR32BitRegClass.hasSubClassEq(RC) ||
    SystemZ::GR64BitRegClass.hasSubClassEq(RC)) {
  CondCycles = 2;
  TrueCycles = 2;
  FalseCycles = 2;
  return true;
}

// Can't do anything else.
return false;
569}

571void SystemZInstrInfo::insertSelect(MachineBasicBlock &MBB,
                                  MachineBasicBlock::iterator I,
                                  const DebugLoc &DL, Register DstReg,
                                  ArrayRef<MachineOperand> Pred,
                                  Register TrueReg,
                                  Register FalseReg) const {
MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
const TargetRegisterClass *RC = MRI.getRegClass(DstReg);

assert(Pred.size() == 2 && "Invalid condition")(static_cast <bool> (Pred.size() == 2 && "Invalid condition"
) ? void (0) : __assert_fail ("Pred.size() == 2 && \"Invalid condition\""
, "llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp", 580, __extension__
 __PRETTY_FUNCTION__));
unsigned CCValid = Pred[0].getImm();
unsigned CCMask = Pred[1].getImm();

unsigned Opc;
if (SystemZ::GRX32BitRegClass.hasSubClassEq(RC)) {
  if (STI.hasMiscellaneousExtensions3())
    Opc = SystemZ::SELRMux;
  else if (STI.hasLoadStoreOnCond2())
    Opc = SystemZ::LOCRMux;
  else {
    Opc = SystemZ::LOCR;
    MRI.constrainRegClass(DstReg, &SystemZ::GR32BitRegClass);
    Register TReg = MRI.createVirtualRegister(&SystemZ::GR32BitRegClass);
    Register FReg = MRI.createVirtualRegister(&SystemZ::GR32BitRegClass);
    BuildMI(MBB, I, DL, get(TargetOpcode::COPY), TReg).addReg(TrueReg);
    BuildMI(MBB, I, DL, get(TargetOpcode::COPY), FReg).addReg(FalseReg);
    TrueReg = TReg;
    FalseReg = FReg;
  }
} else if (SystemZ::GR64BitRegClass.hasSubClassEq(RC)) {
  if (STI.hasMiscellaneousExtensions3())
    Opc = SystemZ::SELGR;
  else
    Opc = SystemZ::LOCGR;
} else
  llvm_unreachable("Invalid register class")::llvm::llvm_unreachable_internal("Invalid register class", "llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp"
, 606);

BuildMI(MBB, I, DL, get(Opc), DstReg)
  .addReg(FalseReg).addReg(TrueReg)
  .addImm(CCValid).addImm(CCMask);
611}

613bool SystemZInstrInfo::FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI,
                                   Register Reg,
                                   MachineRegisterInfo *MRI) const {
unsigned DefOpc = DefMI.getOpcode();
if (DefOpc != SystemZ::LHIMux && DefOpc != SystemZ::LHI &&
    DefOpc != SystemZ::LGHI)
  return false;
if (DefMI.getOperand(0).getReg() != Reg)
  return false;
int32_t ImmVal = (int32_t)DefMI.getOperand(1).getImm();

unsigned UseOpc = UseMI.getOpcode();
unsigned NewUseOpc;
unsigned UseIdx;
int CommuteIdx = -1;
bool TieOps = false;
switch (UseOpc) {
case SystemZ::SELRMux:
  TieOps = true;
  [[fallthrough]];
case SystemZ::LOCRMux:
  if (!STI.hasLoadStoreOnCond2())
    return false;
  NewUseOpc = SystemZ::LOCHIMux;
  if (UseMI.getOperand(2).getReg() == Reg)
    UseIdx = 2;
  else if (UseMI.getOperand(1).getReg() == Reg)
    UseIdx = 2, CommuteIdx = 1;
  else
    return false;
  break;
case SystemZ::SELGR:
  TieOps = true;
  [[fallthrough]];
case SystemZ::LOCGR:
  if (!STI.hasLoadStoreOnCond2())
    return false;
  NewUseOpc = SystemZ::LOCGHI;
  if (UseMI.getOperand(2).getReg() == Reg)
    UseIdx = 2;
  else if (UseMI.getOperand(1).getReg() == Reg)
    UseIdx = 2, CommuteIdx = 1;
  else
    return false;
  break;
default:
  return false;
}

if (CommuteIdx != -1)
  if (!commuteInstruction(UseMI, false, CommuteIdx, UseIdx))
    return false;

bool DeleteDef = MRI->hasOneNonDBGUse(Reg);
UseMI.setDesc(get(NewUseOpc));
if (TieOps)
  UseMI.tieOperands(0, 1);
UseMI.getOperand(UseIdx).ChangeToImmediate(ImmVal);
if (DeleteDef)
  DefMI.eraseFromParent();

return true;
675}

677bool SystemZInstrInfo::isPredicable(const MachineInstr &MI) const {
unsigned Opcode = MI.getOpcode();
if (Opcode == SystemZ::Return ||
    Opcode == SystemZ::Return_XPLINK ||
    Opcode == SystemZ::Trap ||
    Opcode == SystemZ::CallJG ||
    Opcode == SystemZ::CallBR)
  return true;
return false;
686}

688bool SystemZInstrInfo::
689isProfitableToIfCvt(MachineBasicBlock &MBB,
                  unsigned NumCycles, unsigned ExtraPredCycles,
                  BranchProbability Probability) const {
// Avoid using conditional returns at the end of a loop (since then
// we'd need to emit an unconditional branch to the beginning anyway,
// making the loop body longer).  This doesn't apply for low-probability
// loops (eg. compare-and-swap retry), so just decide based on branch
// probability instead of looping structure.
// However, since Compare and Trap instructions cost the same as a regular
// Compare instruction, we should allow the if conversion to convert this
// into a Conditional Compare regardless of the branch probability.
if (MBB.getLastNonDebugInstr()->getOpcode() != SystemZ::Trap &&
    MBB.succ_empty() && Probability < BranchProbability(1, 8))
  return false;
// For now only convert single instructions.
return NumCycles == 1;
705}

707bool SystemZInstrInfo::
708isProfitableToIfCvt(MachineBasicBlock &TMBB,
                  unsigned NumCyclesT, unsigned ExtraPredCyclesT,
                  MachineBasicBlock &FMBB,
                  unsigned NumCyclesF, unsigned ExtraPredCyclesF,
                  BranchProbability Probability) const {
// For now avoid converting mutually-exclusive cases.
return false;
715}

717bool SystemZInstrInfo::
718isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
                        BranchProbability Probability) const {
// For now only duplicate single instructions.
return NumCycles == 1;
722}

724bool SystemZInstrInfo::PredicateInstruction(
  MachineInstr &MI, ArrayRef<MachineOperand> Pred) const {
assert(Pred.size() == 2 && "Invalid condition")(static_cast <bool> (Pred.size() == 2 && "Invalid condition"
) ? void (0) : __assert_fail ("Pred.size() == 2 && \"Invalid condition\""
, "llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp", 726, __extension__
 __PRETTY_FUNCTION__));
unsigned CCValid = Pred[0].getImm();
unsigned CCMask = Pred[1].getImm();
assert(CCMask > 0 && CCMask < 15 && "Invalid predicate")(static_cast <bool> (CCMask > 0 && CCMask <
&& "Invalid predicate") ? void (0) : __assert_fail
 ("CCMask > 0 && CCMask < 15 && \"Invalid predicate\""
, "llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp", 729, __extension__
 __PRETTY_FUNCTION__));
unsigned Opcode = MI.getOpcode();
if (Opcode == SystemZ::Trap) {
  MI.setDesc(get(SystemZ::CondTrap));
  MachineInstrBuilder(*MI.getParent()->getParent(), MI)
    .addImm(CCValid).addImm(CCMask)
    .addReg(SystemZ::CC, RegState::Implicit);
  return true;
}
if (Opcode == SystemZ::Return || Opcode == SystemZ::Return_XPLINK) {
  MI.setDesc(get(Opcode == SystemZ::Return ? SystemZ::CondReturn
                                           : SystemZ::CondReturn_XPLINK));
  MachineInstrBuilder(*MI.getParent()->getParent(), MI)
      .addImm(CCValid)
      .addImm(CCMask)
      .addReg(SystemZ::CC, RegState::Implicit);
  return true;
}
if (Opcode == SystemZ::CallJG) {
  MachineOperand FirstOp = MI.getOperand(0);
  const uint32_t *RegMask = MI.getOperand(1).getRegMask();
  MI.removeOperand(1);
  MI.removeOperand(0);
  MI.setDesc(get(SystemZ::CallBRCL));
  MachineInstrBuilder(*MI.getParent()->getParent(), MI)
      .addImm(CCValid)
      .addImm(CCMask)
      .add(FirstOp)
      .addRegMask(RegMask)
      .addReg(SystemZ::CC, RegState::Implicit);
  return true;
}
if (Opcode == SystemZ::CallBR) {
  MachineOperand Target = MI.getOperand(0);
  const uint32_t *RegMask = MI.getOperand(1).getRegMask();
  MI.removeOperand(1);
  MI.removeOperand(0);
  MI.setDesc(get(SystemZ::CallBCR));
  MachineInstrBuilder(*MI.getParent()->getParent(), MI)
    .addImm(CCValid).addImm(CCMask)
    .add(Target)
    .addRegMask(RegMask)
    .addReg(SystemZ::CC, RegState::Implicit);
  return true;
}
return false;
775}

777void SystemZInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
                                 MachineBasicBlock::iterator MBBI,
                                 const DebugLoc &DL, MCRegister DestReg,
                                 MCRegister SrcReg, bool KillSrc) const {
// Split 128-bit GPR moves into two 64-bit moves. Add implicit uses of the
// super register in case one of the subregs is undefined.
// This handles ADDR128 too.
if (SystemZ::GR128BitRegClass.contains(DestReg, SrcReg)) {
  copyPhysReg(MBB, MBBI, DL, RI.getSubReg(DestReg, SystemZ::subreg_h64),
              RI.getSubReg(SrcReg, SystemZ::subreg_h64), KillSrc);
  MachineInstrBuilder(*MBB.getParent(), std::prev(MBBI))
    .addReg(SrcReg, RegState::Implicit);
  copyPhysReg(MBB, MBBI, DL, RI.getSubReg(DestReg, SystemZ::subreg_l64),
              RI.getSubReg(SrcReg, SystemZ::subreg_l64), KillSrc);
  MachineInstrBuilder(*MBB.getParent(), std::prev(MBBI))
    .addReg(SrcReg, (getKillRegState(KillSrc) | RegState::Implicit));
  return;
}

if (SystemZ::GRX32BitRegClass.contains(DestReg, SrcReg)) {
  emitGRX32Move(MBB, MBBI, DL, DestReg, SrcReg, SystemZ::LR, 32, KillSrc,
                false);
  return;
}

// Move 128-bit floating-point values between VR128 and FP128.
if (SystemZ::VR128BitRegClass.contains(DestReg) &&
    SystemZ::FP128BitRegClass.contains(SrcReg)) {
  MCRegister SrcRegHi =
      RI.getMatchingSuperReg(RI.getSubReg(SrcReg, SystemZ::subreg_h64),
                             SystemZ::subreg_h64, &SystemZ::VR128BitRegClass);
  MCRegister SrcRegLo =
      RI.getMatchingSuperReg(RI.getSubReg(SrcReg, SystemZ::subreg_l64),
                             SystemZ::subreg_h64, &SystemZ::VR128BitRegClass);

  BuildMI(MBB, MBBI, DL, get(SystemZ::VMRHG), DestReg)
    .addReg(SrcRegHi, getKillRegState(KillSrc))
    .addReg(SrcRegLo, getKillRegState(KillSrc));
  return;
}
if (SystemZ::FP128BitRegClass.contains(DestReg) &&
    SystemZ::VR128BitRegClass.contains(SrcReg)) {
  MCRegister DestRegHi =
      RI.getMatchingSuperReg(RI.getSubReg(DestReg, SystemZ::subreg_h64),
                             SystemZ::subreg_h64, &SystemZ::VR128BitRegClass);
  MCRegister DestRegLo =
      RI.getMatchingSuperReg(RI.getSubReg(DestReg, SystemZ::subreg_l64),
                             SystemZ::subreg_h64, &SystemZ::VR128BitRegClass);

  if (DestRegHi != SrcReg)
    copyPhysReg(MBB, MBBI, DL, DestRegHi, SrcReg, false);
  BuildMI(MBB, MBBI, DL, get(SystemZ::VREPG), DestRegLo)
    .addReg(SrcReg, getKillRegState(KillSrc)).addImm(1);
  return;
}

// Move CC value from a GR32.
if (DestReg == SystemZ::CC) {
  unsigned Opcode =
    SystemZ::GR32BitRegClass.contains(SrcReg) ? SystemZ::TMLH : SystemZ::TMHH;
  BuildMI(MBB, MBBI, DL, get(Opcode))
    .addReg(SrcReg, getKillRegState(KillSrc))
    .addImm(3 << (SystemZ::IPM_CC - 16));
  return;
}

// Everything else needs only one instruction.
unsigned Opcode;
if (SystemZ::GR64BitRegClass.contains(DestReg, SrcReg))
  Opcode = SystemZ::LGR;
else if (SystemZ::FP32BitRegClass.contains(DestReg, SrcReg))
  // For z13 we prefer LDR over LER to avoid partial register dependencies.
  Opcode = STI.hasVector() ? SystemZ::LDR32 : SystemZ::LER;
else if (SystemZ::FP64BitRegClass.contains(DestReg, SrcReg))
  Opcode = SystemZ::LDR;
else if (SystemZ::FP128BitRegClass.contains(DestReg, SrcReg))
  Opcode = SystemZ::LXR;
else if (SystemZ::VR32BitRegClass.contains(DestReg, SrcReg))
  Opcode = SystemZ::VLR32;
else if (SystemZ::VR64BitRegClass.contains(DestReg, SrcReg))
  Opcode = SystemZ::VLR64;
else if (SystemZ::VR128BitRegClass.contains(DestReg, SrcReg))
  Opcode = SystemZ::VLR;
else if (SystemZ::AR32BitRegClass.contains(DestReg, SrcReg))
  Opcode = SystemZ::CPYA;
else
  llvm_unreachable("Impossible reg-to-reg copy")::llvm::llvm_unreachable_internal("Impossible reg-to-reg copy"
, "llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp", 863);

BuildMI(MBB, MBBI, DL, get(Opcode), DestReg)
  .addReg(SrcReg, getKillRegState(KillSrc));
867}

869void SystemZInstrInfo::storeRegToStackSlot(
  MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg,
  bool isKill, int FrameIdx, const TargetRegisterClass *RC,
  const TargetRegisterInfo *TRI, Register VReg) const {
DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();

// Callers may expect a single instruction, so keep 128-bit moves
// together for now and lower them after register allocation.
unsigned LoadOpcode, StoreOpcode;
getLoadStoreOpcodes(RC, LoadOpcode, StoreOpcode);
addFrameReference(BuildMI(MBB, MBBI, DL, get(StoreOpcode))
                      .addReg(SrcReg, getKillRegState(isKill)),
                  FrameIdx);
882}

884void SystemZInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
                                          MachineBasicBlock::iterator MBBI,
                                          Register DestReg, int FrameIdx,
                                          const TargetRegisterClass *RC,
                                          const TargetRegisterInfo *TRI,
                                          Register VReg) const {
DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();

// Callers may expect a single instruction, so keep 128-bit moves
// together for now and lower them after register allocation.
unsigned LoadOpcode, StoreOpcode;
getLoadStoreOpcodes(RC, LoadOpcode, StoreOpcode);
addFrameReference(BuildMI(MBB, MBBI, DL, get(LoadOpcode), DestReg),
                  FrameIdx);
898}

900// Return true if MI is a simple load or store with a 12-bit displacement
901// and no index.  Flag is SimpleBDXLoad for loads and SimpleBDXStore for stores.
902static bool isSimpleBD12Move(const MachineInstr *MI, unsigned Flag) {
const MCInstrDesc &MCID = MI->getDesc();
return ((MCID.TSFlags & Flag) &&
        isUInt<12>(MI->getOperand(2).getImm()) &&
        MI->getOperand(3).getReg() == 0);
907}

909namespace {

911struct LogicOp {
LogicOp() = default;
LogicOp(unsigned regSize, unsigned immLSB, unsigned immSize)
  : RegSize(regSize), ImmLSB(immLSB), ImmSize(immSize) {}

explicit operator bool() const { return RegSize; }

unsigned RegSize = 0;
unsigned ImmLSB = 0;
unsigned ImmSize = 0;
921};

923} // end anonymous namespace

925static LogicOp interpretAndImmediate(unsigned Opcode) {
switch (Opcode) {
case SystemZ::NILMux: return LogicOp(32,  0, 16);
case SystemZ::NIHMux: return LogicOp(32, 16, 16);
case SystemZ::NILL64: return LogicOp(64,  0, 16);
case SystemZ::NILH64: return LogicOp(64, 16, 16);
case SystemZ::NIHL64: return LogicOp(64, 32, 16);
case SystemZ::NIHH64: return LogicOp(64, 48, 16);
case SystemZ::NIFMux: return LogicOp(32,  0, 32);
case SystemZ::NILF64: return LogicOp(64,  0, 32);
case SystemZ::NIHF64: return LogicOp(64, 32, 32);
default:              return LogicOp();
}
938}

940static void transferDeadCC(MachineInstr *OldMI, MachineInstr *NewMI) {
if (OldMI->registerDefIsDead(SystemZ::CC)) {
  MachineOperand *CCDef = NewMI->findRegisterDefOperand(SystemZ::CC);
  if (CCDef != nullptr)
    CCDef->setIsDead(true);
}
946}

948static void transferMIFlag(MachineInstr *OldMI, MachineInstr *NewMI,
                         MachineInstr::MIFlag Flag) {
if (OldMI->getFlag(Flag))
  NewMI->setFlag(Flag);
952}

954MachineInstr *
955SystemZInstrInfo::convertToThreeAddress(MachineInstr &MI, LiveVariables *LV,
                                      LiveIntervals *LIS) const {
MachineBasicBlock *MBB = MI.getParent();

// Try to convert an AND into an RISBG-type instruction.
// TODO: It might be beneficial to select RISBG and shorten to AND instead.
if (LogicOp And = interpretAndImmediate(MI.getOpcode())) {
1
Taking true branch→
  uint64_t Imm = MI.getOperand(2).getImm() << And.ImmLSB;
  // AND IMMEDIATE leaves the other bits of the register unchanged.
  Imm |= allOnes(And.RegSize) & ~(allOnes(And.ImmSize) << And.ImmLSB);
  unsigned Start, End;
  if (isRxSBGMask(Imm, And.RegSize, Start, End)) {
2
←
Calling 'SystemZInstrInfo::isRxSBGMask'→
    unsigned NewOpcode;
    if (And.RegSize == 64) {
      NewOpcode = SystemZ::RISBG;
      // Prefer RISBGN if available, since it does not clobber CC.
      if (STI.hasMiscellaneousExtensions())
        NewOpcode = SystemZ::RISBGN;
    } else {
      NewOpcode = SystemZ::RISBMux;
      Start &= 31;
      End &= 31;
    }
    MachineOperand &Dest = MI.getOperand(0);
    MachineOperand &Src = MI.getOperand(1);
    MachineInstrBuilder MIB =
        BuildMI(*MBB, MI, MI.getDebugLoc(), get(NewOpcode))
            .add(Dest)
            .addReg(0)
            .addReg(Src.getReg(), getKillRegState(Src.isKill()),
                    Src.getSubReg())
            .addImm(Start)
            .addImm(End + 128)
            .addImm(0);
    if (LV) {
      unsigned NumOps = MI.getNumOperands();
      for (unsigned I = 1; I < NumOps; ++I) {
        MachineOperand &Op = MI.getOperand(I);
        if (Op.isReg() && Op.isKill())
          LV->replaceKillInstruction(Op.getReg(), MI, *MIB);
      }
    }
    if (LIS)
      LIS->ReplaceMachineInstrInMaps(MI, *MIB);
    transferDeadCC(&MI, MIB);
    return MIB;
  }
}
return nullptr;
1004}

1006MachineInstr *SystemZInstrInfo::foldMemoryOperandImpl(
  MachineFunction &MF, MachineInstr &MI, ArrayRef<unsigned> Ops,
  MachineBasicBlock::iterator InsertPt, int FrameIndex,
  LiveIntervals *LIS, VirtRegMap *VRM) const {
const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
MachineRegisterInfo &MRI = MF.getRegInfo();
const MachineFrameInfo &MFI = MF.getFrameInfo();
unsigned Size = MFI.getObjectSize(FrameIndex);
unsigned Opcode = MI.getOpcode();

// Check CC liveness if new instruction introduces a dead def of CC.
MCRegUnitIterator CCUnit(MCRegister::from(SystemZ::CC), TRI);
SlotIndex MISlot = SlotIndex();
LiveRange *CCLiveRange = nullptr;
bool CCLiveAtMI = true;
if (LIS) {
  MISlot = LIS->getSlotIndexes()->getInstructionIndex(MI).getRegSlot();
  CCLiveRange = &LIS->getRegUnit(*CCUnit);
  CCLiveAtMI = CCLiveRange->liveAt(MISlot);
}
++CCUnit;
assert(!CCUnit.isValid() && "CC only has one reg unit.")(static_cast <bool> (!CCUnit.isValid() && "CC only has one reg unit."
) ? void (0) : __assert_fail ("!CCUnit.isValid() && \"CC only has one reg unit.\""
, "llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp", 1027, __extension__
 __PRETTY_FUNCTION__));

if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
  if (!CCLiveAtMI && (Opcode == SystemZ::LA || Opcode == SystemZ::LAY) &&
      isInt<8>(MI.getOperand(2).getImm()) && !MI.getOperand(3).getReg()) {
    // LA(Y) %reg, CONST(%reg) -> AGSI %mem, CONST
    MachineInstr *BuiltMI = BuildMI(*InsertPt->getParent(), InsertPt,
                                    MI.getDebugLoc(), get(SystemZ::AGSI))
      .addFrameIndex(FrameIndex)
      .addImm(0)
      .addImm(MI.getOperand(2).getImm());
    BuiltMI->findRegisterDefOperand(SystemZ::CC)->setIsDead(true);
    CCLiveRange->createDeadDef(MISlot, LIS->getVNInfoAllocator());
    return BuiltMI;
  }
  return nullptr;
}

// All other cases require a single operand.
if (Ops.size() != 1)
  return nullptr;

unsigned OpNum = Ops[0];
assert(Size * 8 ==(static_cast <bool> (Size * 8 == TRI->getRegSizeInBits
(*MF.getRegInfo() .getRegClass(MI.getOperand(OpNum).getReg())
) && "Invalid size combination") ? void (0) : __assert_fail
 ("Size * 8 == TRI->getRegSizeInBits(*MF.getRegInfo() .getRegClass(MI.getOperand(OpNum).getReg())) && \"Invalid size combination\""
, "llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp", 1053, __extension__
 __PRETTY_FUNCTION__))
         TRI->getRegSizeInBits(*MF.getRegInfo()(static_cast <bool> (Size * 8 == TRI->getRegSizeInBits
(*MF.getRegInfo() .getRegClass(MI.getOperand(OpNum).getReg())
) && "Invalid size combination") ? void (0) : __assert_fail
 ("Size * 8 == TRI->getRegSizeInBits(*MF.getRegInfo() .getRegClass(MI.getOperand(OpNum).getReg())) && \"Invalid size combination\""
, "llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp", 1053, __extension__
 __PRETTY_FUNCTION__))
                             .getRegClass(MI.getOperand(OpNum).getReg())) &&(static_cast <bool> (Size * 8 == TRI->getRegSizeInBits
(*MF.getRegInfo() .getRegClass(MI.getOperand(OpNum).getReg())
) && "Invalid size combination") ? void (0) : __assert_fail
 ("Size * 8 == TRI->getRegSizeInBits(*MF.getRegInfo() .getRegClass(MI.getOperand(OpNum).getReg())) && \"Invalid size combination\""
, "llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp", 1053, __extension__
 __PRETTY_FUNCTION__))
       "Invalid size combination")(static_cast <bool> (Size * 8 == TRI->getRegSizeInBits
(*MF.getRegInfo() .getRegClass(MI.getOperand(OpNum).getReg())
) && "Invalid size combination") ? void (0) : __assert_fail
 ("Size * 8 == TRI->getRegSizeInBits(*MF.getRegInfo() .getRegClass(MI.getOperand(OpNum).getReg())) && \"Invalid size combination\""
, "llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp", 1053, __extension__
 __PRETTY_FUNCTION__));

if ((Opcode == SystemZ::AHI || Opcode == SystemZ::AGHI) && OpNum == 0 &&
    isInt<8>(MI.getOperand(2).getImm())) {
  // A(G)HI %reg, CONST -> A(G)SI %mem, CONST
  Opcode = (Opcode == SystemZ::AHI ? SystemZ::ASI : SystemZ::AGSI);
  MachineInstr *BuiltMI =
      BuildMI(*InsertPt->getParent(), InsertPt, MI.getDebugLoc(), get(Opcode))
          .addFrameIndex(FrameIndex)
          .addImm(0)
          .addImm(MI.getOperand(2).getImm());
  transferDeadCC(&MI, BuiltMI);
  transferMIFlag(&MI, BuiltMI, MachineInstr::NoSWrap);
  return BuiltMI;
}

if ((Opcode == SystemZ::ALFI && OpNum == 0 &&
     isInt<8>((int32_t)MI.getOperand(2).getImm())) ||
    (Opcode == SystemZ::ALGFI && OpNum == 0 &&
     isInt<8>((int64_t)MI.getOperand(2).getImm()))) {
  // AL(G)FI %reg, CONST -> AL(G)SI %mem, CONST
  Opcode = (Opcode == SystemZ::ALFI ? SystemZ::ALSI : SystemZ::ALGSI);
  MachineInstr *BuiltMI =
      BuildMI(*InsertPt->getParent(), InsertPt, MI.getDebugLoc(), get(Opcode))
          .addFrameIndex(FrameIndex)
          .addImm(0)
          .addImm((int8_t)MI.getOperand(2).getImm());
  transferDeadCC(&MI, BuiltMI);
  return BuiltMI;
}

if ((Opcode == SystemZ::SLFI && OpNum == 0 &&
     isInt<8>((int32_t)-MI.getOperand(2).getImm())) ||
    (Opcode == SystemZ::SLGFI && OpNum == 0 &&
     isInt<8>((int64_t)-MI.getOperand(2).getImm()))) {
  // SL(G)FI %reg, CONST -> AL(G)SI %mem, -CONST
  Opcode = (Opcode == SystemZ::SLFI ? SystemZ::ALSI : SystemZ::ALGSI);
  MachineInstr *BuiltMI =
      BuildMI(*InsertPt->getParent(), InsertPt, MI.getDebugLoc(), get(Opcode))
          .addFrameIndex(FrameIndex)
          .addImm(0)
          .addImm((int8_t)-MI.getOperand(2).getImm());
  transferDeadCC(&MI, BuiltMI);
  return BuiltMI;
}

unsigned MemImmOpc = 0;
switch (Opcode) {
case SystemZ::LHIMux:
case SystemZ::LHI:    MemImmOpc = SystemZ::MVHI;  break;
case SystemZ::LGHI:   MemImmOpc = SystemZ::MVGHI; break;
case SystemZ::CHIMux:
case SystemZ::CHI:    MemImmOpc = SystemZ::CHSI;  break;
case SystemZ::CGHI:   MemImmOpc = SystemZ::CGHSI; break;
case SystemZ::CLFIMux:
case SystemZ::CLFI:
  if (isUInt<16>(MI.getOperand(1).getImm()))
    MemImmOpc = SystemZ::CLFHSI;
  break;
case SystemZ::CLGFI:
  if (isUInt<16>(MI.getOperand(1).getImm()))
    MemImmOpc = SystemZ::CLGHSI;
  break;
default: break;
}
if (MemImmOpc)
  return BuildMI(*InsertPt->getParent(), InsertPt, MI.getDebugLoc(),
                 get(MemImmOpc))
             .addFrameIndex(FrameIndex)
             .addImm(0)
             .addImm(MI.getOperand(1).getImm());

if (Opcode == SystemZ::LGDR || Opcode == SystemZ::LDGR) {
  bool Op0IsGPR = (Opcode == SystemZ::LGDR);
  bool Op1IsGPR = (Opcode == SystemZ::LDGR);
  // If we're spilling the destination of an LDGR or LGDR, store the
  // source register instead.
  if (OpNum == 0) {
    unsigned StoreOpcode = Op1IsGPR ? SystemZ::STG : SystemZ::STD;
    return BuildMI(*InsertPt->getParent(), InsertPt, MI.getDebugLoc(),
                   get(StoreOpcode))
        .add(MI.getOperand(1))
        .addFrameIndex(FrameIndex)
        .addImm(0)
        .addReg(0);
  }
  // If we're spilling the source of an LDGR or LGDR, load the
  // destination register instead.
  if (OpNum == 1) {
    unsigned LoadOpcode = Op0IsGPR ? SystemZ::LG : SystemZ::LD;
    return BuildMI(*InsertPt->getParent(), InsertPt, MI.getDebugLoc(),
                   get(LoadOpcode))
      .add(MI.getOperand(0))
      .addFrameIndex(FrameIndex)
      .addImm(0)
      .addReg(0);
  }
}

// Look for cases where the source of a simple store or the destination
// of a simple load is being spilled.  Try to use MVC instead.
//
// Although MVC is in practice a fast choice in these cases, it is still
// logically a bytewise copy.  This means that we cannot use it if the
// load or store is volatile.  We also wouldn't be able to use MVC if
// the two memories partially overlap, but that case cannot occur here,
// because we know that one of the memories is a full frame index.
//
// For performance reasons, we also want to avoid using MVC if the addresses
// might be equal.  We don't worry about that case here, because spill slot
// coloring happens later, and because we have special code to remove
// MVCs that turn out to be redundant.
if (OpNum == 0 && MI.hasOneMemOperand()) {
  MachineMemOperand *MMO = *MI.memoperands_begin();
  if (MMO->getSize() == Size && !MMO->isVolatile() && !MMO->isAtomic()) {
    // Handle conversion of loads.
    if (isSimpleBD12Move(&MI, SystemZII::SimpleBDXLoad)) {
      return BuildMI(*InsertPt->getParent(), InsertPt, MI.getDebugLoc(),
                     get(SystemZ::MVC))
          .addFrameIndex(FrameIndex)
          .addImm(0)
          .addImm(Size)
          .add(MI.getOperand(1))
          .addImm(MI.getOperand(2).getImm())
          .addMemOperand(MMO);
    }
    // Handle conversion of stores.
    if (isSimpleBD12Move(&MI, SystemZII::SimpleBDXStore)) {
      return BuildMI(*InsertPt->getParent(), InsertPt, MI.getDebugLoc(),
                     get(SystemZ::MVC))
          .add(MI.getOperand(1))
          .addImm(MI.getOperand(2).getImm())
          .addImm(Size)
          .addFrameIndex(FrameIndex)
          .addImm(0)
          .addMemOperand(MMO);
    }
  }
}

// If the spilled operand is the final one or the instruction is
// commutable, try to change <INSN>R into <INSN>.  Don't introduce a def of
// CC if it is live and MI does not define it.
unsigned NumOps = MI.getNumExplicitOperands();
int MemOpcode = SystemZ::getMemOpcode(Opcode);
if (MemOpcode == -1 ||
    (CCLiveAtMI && !MI.definesRegister(SystemZ::CC) &&
     get(MemOpcode).hasImplicitDefOfPhysReg(SystemZ::CC)))
  return nullptr;

// Check if all other vregs have a usable allocation in the case of vector
// to FP conversion.
const MCInstrDesc &MCID = MI.getDesc();
for (unsigned I = 0, E = MCID.getNumOperands(); I != E; ++I) {
  const MCOperandInfo &MCOI = MCID.OpInfo[I];
  if (MCOI.OperandType != MCOI::OPERAND_REGISTER || I == OpNum)
    continue;
  const TargetRegisterClass *RC = TRI->getRegClass(MCOI.RegClass);
  if (RC == &SystemZ::VR32BitRegClass || RC == &SystemZ::VR64BitRegClass) {
    Register Reg = MI.getOperand(I).getReg();
    Register PhysReg = Register::isVirtualRegister(Reg)
                           ? (VRM ? Register(VRM->getPhys(Reg)) : Register())
                           : Reg;
    if (!PhysReg ||
        !(SystemZ::FP32BitRegClass.contains(PhysReg) ||
          SystemZ::FP64BitRegClass.contains(PhysReg) ||
          SystemZ::VF128BitRegClass.contains(PhysReg)))
      return nullptr;
  }
}
// Fused multiply and add/sub need to have the same dst and accumulator reg.
bool FusedFPOp = (Opcode == SystemZ::WFMADB || Opcode == SystemZ::WFMASB ||
                  Opcode == SystemZ::WFMSDB || Opcode == SystemZ::WFMSSB);
if (FusedFPOp) {
  Register DstReg = VRM->getPhys(MI.getOperand(0).getReg());
  Register AccReg = VRM->getPhys(MI.getOperand(3).getReg());
  if (OpNum == 0 || OpNum == 3 || DstReg != AccReg)
    return nullptr;
}

// Try to swap compare operands if possible.
bool NeedsCommute = false;
if ((MI.getOpcode() == SystemZ::CR || MI.getOpcode() == SystemZ::CGR ||
     MI.getOpcode() == SystemZ::CLR || MI.getOpcode() == SystemZ::CLGR ||
     MI.getOpcode() == SystemZ::WFCDB || MI.getOpcode() == SystemZ::WFCSB ||
     MI.getOpcode() == SystemZ::WFKDB || MI.getOpcode() == SystemZ::WFKSB) &&
    OpNum == 0 && prepareCompareSwapOperands(MI))
  NeedsCommute = true;

bool CCOperands = false;
if (MI.getOpcode() == SystemZ::LOCRMux || MI.getOpcode() == SystemZ::LOCGR ||
    MI.getOpcode() == SystemZ::SELRMux || MI.getOpcode() == SystemZ::SELGR) {
  assert(MI.getNumOperands() == 6 && NumOps == 5 &&(static_cast <bool> (MI.getNumOperands() == 6 &&
 NumOps == 5 && "LOCR/SELR instruction operands corrupt?"
) ? void (0) : __assert_fail ("MI.getNumOperands() == 6 && NumOps == 5 && \"LOCR/SELR instruction operands corrupt?\""
, "llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp", 1246, __extension__
 __PRETTY_FUNCTION__))
         "LOCR/SELR instruction operands corrupt?")(static_cast <bool> (MI.getNumOperands() == 6 &&
 NumOps == 5 && "LOCR/SELR instruction operands corrupt?"
) ? void (0) : __assert_fail ("MI.getNumOperands() == 6 && NumOps == 5 && \"LOCR/SELR instruction operands corrupt?\""
, "llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp", 1246, __extension__
 __PRETTY_FUNCTION__));
  NumOps -= 2;
  CCOperands = true;
}

// See if this is a 3-address instruction that is convertible to 2-address
// and suitable for folding below.  Only try this with virtual registers
// and a provided VRM (during regalloc).
if (NumOps == 3 && SystemZ::getTargetMemOpcode(MemOpcode) != -1) {
  if (VRM == nullptr)
    return nullptr;
  else {
    Register DstReg = MI.getOperand(0).getReg();
    Register DstPhys =
        (Register::isVirtualRegister(DstReg) ? Register(VRM->getPhys(DstReg))
                                             : DstReg);
    Register SrcReg = (OpNum == 2 ? MI.getOperand(1).getReg()
                                  : ((OpNum == 1 && MI.isCommutable())
                                         ? MI.getOperand(2).getReg()
                                         : Register()));
    if (DstPhys && !SystemZ::GRH32BitRegClass.contains(DstPhys) && SrcReg &&
        Register::isVirtualRegister(SrcReg) &&
        DstPhys == VRM->getPhys(SrcReg))
      NeedsCommute = (OpNum == 1);
    else
      return nullptr;
  }
}

if ((OpNum == NumOps - 1) || NeedsCommute || FusedFPOp) {
  const MCInstrDesc &MemDesc = get(MemOpcode);
  uint64_t AccessBytes = SystemZII::getAccessSize(MemDesc.TSFlags);
  assert(AccessBytes != 0 && "Size of access should be known")(static_cast <bool> (AccessBytes != 0 && "Size of access should be known"
) ? void (0) : __assert_fail ("AccessBytes != 0 && \"Size of access should be known\""
, "llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp", 1278, __extension__
 __PRETTY_FUNCTION__));
  assert(AccessBytes <= Size && "Access outside the frame index")(static_cast <bool> (AccessBytes <= Size && "Access outside the frame index"
) ? void (0) : __assert_fail ("AccessBytes <= Size && \"Access outside the frame index\""
, "llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp", 1279, __extension__
 __PRETTY_FUNCTION__));
  uint64_t Offset = Size - AccessBytes;
  MachineInstrBuilder MIB = BuildMI(*InsertPt->getParent(), InsertPt,
                                    MI.getDebugLoc(), get(MemOpcode));
  if (MI.isCompare()) {
    assert(NumOps == 2 && "Expected 2 register operands for a compare.")(static_cast <bool> (NumOps == 2 && "Expected 2 register operands for a compare."
) ? void (0) : __assert_fail ("NumOps == 2 && \"Expected 2 register operands for a compare.\""
, "llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp", 1284, __extension__
 __PRETTY_FUNCTION__));
    MIB.add(MI.getOperand(NeedsCommute ? 1 : 0));
  }
  else if (FusedFPOp) {
    MIB.add(MI.getOperand(0));
    MIB.add(MI.getOperand(3));
    MIB.add(MI.getOperand(OpNum == 1 ? 2 : 1));
  }
  else {
    MIB.add(MI.getOperand(0));
    if (NeedsCommute)
      MIB.add(MI.getOperand(2));
    else
      for (unsigned I = 1; I < OpNum; ++I)
        MIB.add(MI.getOperand(I));
  }
  MIB.addFrameIndex(FrameIndex).addImm(Offset);
  if (MemDesc.TSFlags & SystemZII::HasIndex)
    MIB.addReg(0);
  if (CCOperands) {
    unsigned CCValid = MI.getOperand(NumOps).getImm();
    unsigned CCMask = MI.getOperand(NumOps + 1).getImm();
    MIB.addImm(CCValid);
    MIB.addImm(NeedsCommute ? CCMask ^ CCValid : CCMask);
  }
  if (MIB->definesRegister(SystemZ::CC) &&
      (!MI.definesRegister(SystemZ::CC) ||
       MI.registerDefIsDead(SystemZ::CC))) {
    MIB->addRegisterDead(SystemZ::CC, TRI);
    if (CCLiveRange)
      CCLiveRange->createDeadDef(MISlot, LIS->getVNInfoAllocator());
  }
  // Constrain the register classes if converted from a vector opcode. The
  // allocated regs are in an FP reg-class per previous check above.
  for (const MachineOperand &MO : MIB->operands())
    if (MO.isReg() && Register::isVirtualRegister(MO.getReg())) {
      Register Reg = MO.getReg();
      if (MRI.getRegClass(Reg) == &SystemZ::VR32BitRegClass)
        MRI.setRegClass(Reg, &SystemZ::FP32BitRegClass);
      else if (MRI.getRegClass(Reg) == &SystemZ::VR64BitRegClass)
        MRI.setRegClass(Reg, &SystemZ::FP64BitRegClass);
      else if (MRI.getRegClass(Reg) == &SystemZ::VR128BitRegClass)
        MRI.setRegClass(Reg, &SystemZ::VF128BitRegClass);
    }

  transferDeadCC(&MI, MIB);
  transferMIFlag(&MI, MIB, MachineInstr::NoSWrap);
  transferMIFlag(&MI, MIB, MachineInstr::NoFPExcept);
  return MIB;
}

return nullptr;
1336}

1338MachineInstr *SystemZInstrInfo::foldMemoryOperandImpl(
  MachineFunction &MF, MachineInstr &MI, ArrayRef<unsigned> Ops,
  MachineBasicBlock::iterator InsertPt, MachineInstr &LoadMI,
  LiveIntervals *LIS) const {
return nullptr;
1343}

1345bool SystemZInstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
switch (MI.getOpcode()) {
case SystemZ::L128:
  splitMove(MI, SystemZ::LG);
  return true;

case SystemZ::ST128:
  splitMove(MI, SystemZ::STG);
  return true;

case SystemZ::LX:
  splitMove(MI, SystemZ::LD);
  return true;

case SystemZ::STX:
  splitMove(MI, SystemZ::STD);
  return true;

case SystemZ::LBMux:
  expandRXYPseudo(MI, SystemZ::LB, SystemZ::LBH);
  return true;

case SystemZ::LHMux:
  expandRXYPseudo(MI, SystemZ::LH, SystemZ::LHH);
  return true;

case SystemZ::LLCRMux:
  expandZExtPseudo(MI, SystemZ::LLCR, 8);
  return true;

case SystemZ::LLHRMux:
  expandZExtPseudo(MI, SystemZ::LLHR, 16);
  return true;

case SystemZ::LLCMux:
  expandRXYPseudo(MI, SystemZ::LLC, SystemZ::LLCH);
  return true;

case SystemZ::LLHMux:
  expandRXYPseudo(MI, SystemZ::LLH, SystemZ::LLHH);
  return true;

case SystemZ::LMux:
  expandRXYPseudo(MI, SystemZ::L, SystemZ::LFH);
  return true;

case SystemZ::LOCMux:
  expandLOCPseudo(MI, SystemZ::LOC, SystemZ::LOCFH);
  return true;

case SystemZ::LOCHIMux:
  expandLOCPseudo(MI, SystemZ::LOCHI, SystemZ::LOCHHI);
  return true;

case SystemZ::STCMux:
  expandRXYPseudo(MI, SystemZ::STC, SystemZ::STCH);
  return true;

case SystemZ::STHMux:
  expandRXYPseudo(MI, SystemZ::STH, SystemZ::STHH);
  return true;

case SystemZ::STMux:
  expandRXYPseudo(MI, SystemZ::ST, SystemZ::STFH);
  return true;

case SystemZ::STOCMux:
  expandLOCPseudo(MI, SystemZ::STOC, SystemZ::STOCFH);
  return true;

case SystemZ::LHIMux:
  expandRIPseudo(MI, SystemZ::LHI, SystemZ::IIHF, true);
  return true;

case SystemZ::IIFMux:
  expandRIPseudo(MI, SystemZ::IILF, SystemZ::IIHF, false);
  return true;

case SystemZ::IILMux:
  expandRIPseudo(MI, SystemZ::IILL, SystemZ::IIHL, false);
  return true;

case SystemZ::IIHMux:
  expandRIPseudo(MI, SystemZ::IILH, SystemZ::IIHH, false);
  return true;

case SystemZ::NIFMux:
  expandRIPseudo(MI, SystemZ::NILF, SystemZ::NIHF, false);
  return true;

case SystemZ::NILMux:
  expandRIPseudo(MI, SystemZ::NILL, SystemZ::NIHL, false);
  return true;

case SystemZ::NIHMux:
  expandRIPseudo(MI, SystemZ::NILH, SystemZ::NIHH, false);
  return true;

case SystemZ::OIFMux:
  expandRIPseudo(MI, SystemZ::OILF, SystemZ::OIHF, false);
  return true;

case SystemZ::OILMux:
  expandRIPseudo(MI, SystemZ::OILL, SystemZ::OIHL, false);
  return true;

case SystemZ::OIHMux:
  expandRIPseudo(MI, SystemZ::OILH, SystemZ::OIHH, false);
  return true;

case SystemZ::XIFMux:
  expandRIPseudo(MI, SystemZ::XILF, SystemZ::XIHF, false);
  return true;

case SystemZ::TMLMux:
  expandRIPseudo(MI, SystemZ::TMLL, SystemZ::TMHL, false);
  return true;

case SystemZ::TMHMux:
  expandRIPseudo(MI, SystemZ::TMLH, SystemZ::TMHH, false);
  return true;

case SystemZ::AHIMux:
  expandRIPseudo(MI, SystemZ::AHI, SystemZ::AIH, false);
  return true;

case SystemZ::AHIMuxK:
  expandRIEPseudo(MI, SystemZ::AHI, SystemZ::AHIK, SystemZ::AIH);
  return true;

case SystemZ::AFIMux:
  expandRIPseudo(MI, SystemZ::AFI, SystemZ::AIH, false);
  return true;

case SystemZ::CHIMux:
  expandRIPseudo(MI, SystemZ::CHI, SystemZ::CIH, false);
  return true;

case SystemZ::CFIMux:
  expandRIPseudo(MI, SystemZ::CFI, SystemZ::CIH, false);
  return true;

case SystemZ::CLFIMux:
  expandRIPseudo(MI, SystemZ::CLFI, SystemZ::CLIH, false);
  return true;

case SystemZ::CMux:
  expandRXYPseudo(MI, SystemZ::C, SystemZ::CHF);
  return true;

case SystemZ::CLMux:
  expandRXYPseudo(MI, SystemZ::CL, SystemZ::CLHF);
  return true;

case SystemZ::RISBMux: {
  bool DestIsHigh = SystemZ::isHighReg(MI.getOperand(0).getReg());
  bool SrcIsHigh = SystemZ::isHighReg(MI.getOperand(2).getReg());
  if (SrcIsHigh == DestIsHigh)
    MI.setDesc(get(DestIsHigh ? SystemZ::RISBHH : SystemZ::RISBLL));
  else {
    MI.setDesc(get(DestIsHigh ? SystemZ::RISBHL : SystemZ::RISBLH));
    MI.getOperand(5).setImm(MI.getOperand(5).getImm() ^ 32);
  }
  return true;
}

case SystemZ::ADJDYNALLOC:
  splitAdjDynAlloc(MI);
  return true;

case TargetOpcode::LOAD_STACK_GUARD:
  expandLoadStackGuard(&MI);
  return true;

default:
  return false;
}
1522}

1524unsigned SystemZInstrInfo::getInstSizeInBytes(const MachineInstr &MI) const {
if (MI.isInlineAsm()) {
  const MachineFunction *MF = MI.getParent()->getParent();
  const char *AsmStr = MI.getOperand(0).getSymbolName();
  return getInlineAsmLength(AsmStr, *MF->getTarget().getMCAsmInfo());
}
else if (MI.getOpcode() == SystemZ::PATCHPOINT)
  return PatchPointOpers(&MI).getNumPatchBytes();
else if (MI.getOpcode() == SystemZ::STACKMAP)
  return MI.getOperand(1).getImm();
else if (MI.getOpcode() == SystemZ::FENTRY_CALL)
  return 6;

return MI.getDesc().getSize();
1538}

1540SystemZII::Branch
1541SystemZInstrInfo::getBranchInfo(const MachineInstr &MI) const {
switch (MI.getOpcode()) {
case SystemZ::BR:
case SystemZ::BI:
case SystemZ::J:
case SystemZ::JG:
  return SystemZII::Branch(SystemZII::BranchNormal, SystemZ::CCMASK_ANY,
                           SystemZ::CCMASK_ANY, &MI.getOperand(0));

case SystemZ::BRC:
case SystemZ::BRCL:
  return SystemZII::Branch(SystemZII::BranchNormal, MI.getOperand(0).getImm(),
                           MI.getOperand(1).getImm(), &MI.getOperand(2));

case SystemZ::BRCT:
case SystemZ::BRCTH:
  return SystemZII::Branch(SystemZII::BranchCT, SystemZ::CCMASK_ICMP,
                           SystemZ::CCMASK_CMP_NE, &MI.getOperand(2));

case SystemZ::BRCTG:
  return SystemZII::Branch(SystemZII::BranchCTG, SystemZ::CCMASK_ICMP,
                           SystemZ::CCMASK_CMP_NE, &MI.getOperand(2));

case SystemZ::CIJ:
case SystemZ::CRJ:
  return SystemZII::Branch(SystemZII::BranchC, SystemZ::CCMASK_ICMP,
                           MI.getOperand(2).getImm(), &MI.getOperand(3));

case SystemZ::CLIJ:
case SystemZ::CLRJ:
  return SystemZII::Branch(SystemZII::BranchCL, SystemZ::CCMASK_ICMP,
                           MI.getOperand(2).getImm(), &MI.getOperand(3));

case SystemZ::CGIJ:
case SystemZ::CGRJ:
  return SystemZII::Branch(SystemZII::BranchCG, SystemZ::CCMASK_ICMP,
                           MI.getOperand(2).getImm(), &MI.getOperand(3));

case SystemZ::CLGIJ:
case SystemZ::CLGRJ:
  return SystemZII::Branch(SystemZII::BranchCLG, SystemZ::CCMASK_ICMP,
                           MI.getOperand(2).getImm(), &MI.getOperand(3));

case SystemZ::INLINEASM_BR:
  // Don't try to analyze asm goto, so pass nullptr as branch target argument.
  return SystemZII::Branch(SystemZII::AsmGoto, 0, 0, nullptr);

default:
  llvm_unreachable("Unrecognized branch opcode")::llvm::llvm_unreachable_internal("Unrecognized branch opcode"
, "llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp", 1589);
}
1591}

1593void SystemZInstrInfo::getLoadStoreOpcodes(const TargetRegisterClass *RC,
                                         unsigned &LoadOpcode,
                                         unsigned &StoreOpcode) const {
if (RC == &SystemZ::GR32BitRegClass || RC == &SystemZ::ADDR32BitRegClass) {
  LoadOpcode = SystemZ::L;
  StoreOpcode = SystemZ::ST;
} else if (RC == &SystemZ::GRH32BitRegClass) {
  LoadOpcode = SystemZ::LFH;
  StoreOpcode = SystemZ::STFH;
} else if (RC == &SystemZ::GRX32BitRegClass) {
  LoadOpcode = SystemZ::LMux;
  StoreOpcode = SystemZ::STMux;
} else if (RC == &SystemZ::GR64BitRegClass ||
           RC == &SystemZ::ADDR64BitRegClass) {
  LoadOpcode = SystemZ::LG;
  StoreOpcode = SystemZ::STG;
} else if (RC == &SystemZ::GR128BitRegClass ||
           RC == &SystemZ::ADDR128BitRegClass) {
  LoadOpcode = SystemZ::L128;
  StoreOpcode = SystemZ::ST128;
} else if (RC == &SystemZ::FP32BitRegClass) {
  LoadOpcode = SystemZ::LE;
  StoreOpcode = SystemZ::STE;
} else if (RC == &SystemZ::FP64BitRegClass) {
  LoadOpcode = SystemZ::LD;
  StoreOpcode = SystemZ::STD;
} else if (RC == &SystemZ::FP128BitRegClass) {
  LoadOpcode = SystemZ::LX;
  StoreOpcode = SystemZ::STX;
} else if (RC == &SystemZ::VR32BitRegClass) {
  LoadOpcode = SystemZ::VL32;
  StoreOpcode = SystemZ::VST32;
} else if (RC == &SystemZ::VR64BitRegClass) {
  LoadOpcode = SystemZ::VL64;
  StoreOpcode = SystemZ::VST64;
} else if (RC == &SystemZ::VF128BitRegClass ||
           RC == &SystemZ::VR128BitRegClass) {
  LoadOpcode = SystemZ::VL;
  StoreOpcode = SystemZ::VST;
} else
  llvm_unreachable("Unsupported regclass to load or store")::llvm::llvm_unreachable_internal("Unsupported regclass to load or store"
, "llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp", 1633);
1634}

1636unsigned SystemZInstrInfo::getOpcodeForOffset(unsigned Opcode,
                                            int64_t Offset,
                                            const MachineInstr *MI) const {
const MCInstrDesc &MCID = get(Opcode);
int64_t Offset2 = (MCID.TSFlags & SystemZII::Is128Bit ? Offset + 8 : Offset);
if (isUInt<12>(Offset) && isUInt<12>(Offset2)) {
  // Get the instruction to use for unsigned 12-bit displacements.
  int Disp12Opcode = SystemZ::getDisp12Opcode(Opcode);
  if (Disp12Opcode >= 0)
    return Disp12Opcode;

  // All address-related instructions can use unsigned 12-bit
  // displacements.
  return Opcode;
}
if (isInt<20>(Offset) && isInt<20>(Offset2)) {
  // Get the instruction to use for signed 20-bit displacements.
  int Disp20Opcode = SystemZ::getDisp20Opcode(Opcode);
  if (Disp20Opcode >= 0)
    return Disp20Opcode;

  // Check whether Opcode allows signed 20-bit displacements.
  if (MCID.TSFlags & SystemZII::Has20BitOffset)
    return Opcode;

  // If a VR32/VR64 reg ended up in an FP register, use the FP opcode.
  if (MI && MI->getOperand(0).isReg()) {
    Register Reg = MI->getOperand(0).getReg();
    if (Reg.isPhysical() && SystemZMC::getFirstReg(Reg) < 16) {
      switch (Opcode) {
      case SystemZ::VL32:
        return SystemZ::LEY;
      case SystemZ::VST32:
        return SystemZ::STEY;
      case SystemZ::VL64:
        return SystemZ::LDY;
      case SystemZ::VST64:
        return SystemZ::STDY;
      default: break;
      }
    }
  }
}
return 0;
1680}

1682bool SystemZInstrInfo::hasDisplacementPairInsn(unsigned Opcode) const {
const MCInstrDesc &MCID = get(Opcode);
if (MCID.TSFlags & SystemZII::Has20BitOffset)
  return SystemZ::getDisp12Opcode(Opcode) >= 0;
return SystemZ::getDisp20Opcode(Opcode) >= 0;
1687}

1689unsigned SystemZInstrInfo::getLoadAndTest(unsigned Opcode) const {
switch (Opcode) {
case SystemZ::L:      return SystemZ::LT;
case SystemZ::LY:     return SystemZ::LT;
case SystemZ::LG:     return SystemZ::LTG;
case SystemZ::LGF:    return SystemZ::LTGF;
case SystemZ::LR:     return SystemZ::LTR;
case SystemZ::LGFR:   return SystemZ::LTGFR;
case SystemZ::LGR:    return SystemZ::LTGR;
case SystemZ::LER:    return SystemZ::LTEBR;
case SystemZ::LDR:    return SystemZ::LTDBR;
case SystemZ::LXR:    return SystemZ::LTXBR;
case SystemZ::LCDFR:  return SystemZ::LCDBR;
case SystemZ::LPDFR:  return SystemZ::LPDBR;
case SystemZ::LNDFR:  return SystemZ::LNDBR;
case SystemZ::LCDFR_32:  return SystemZ::LCEBR;
case SystemZ::LPDFR_32:  return SystemZ::LPEBR;
case SystemZ::LNDFR_32:  return SystemZ::LNEBR;
// On zEC12 we prefer to use RISBGN.  But if there is a chance to
// actually use the condition code, we may turn it back into RISGB.
// Note that RISBG is not really a "load-and-test" instruction,
// but sets the same condition code values, so is OK to use here.
case SystemZ::RISBGN: return SystemZ::RISBG;
default:              return 0;
}
1714}

1716// Return true if Mask matches the regexp 0*1+0*, given that zero masks
1717// have already been filtered out.  Store the first set bit in LSB and
1718// the number of set bits in Length if so.
1719static bool isStringOfOnes(uint64_t Mask, unsigned &LSB, unsigned &Length) {
unsigned First = findFirstSet(Mask);
7
←
Calling 'findFirstSet<unsigned long>'→
14
←
Returning from 'findFirstSet<unsigned long>'→
15
←
'First' initialized to 4294967295→
uint64_t Top = (Mask >> First) + 1;
16
←
The result of the right shift is undefined due to shifting by '4294967295', which is greater or equal to the width of type 'uint64_t'
if ((Top & -Top) == Top) {
  LSB = First;
  Length = findFirstSet(Top);
  return true;
}
return false;
1728}

1730bool SystemZInstrInfo::isRxSBGMask(uint64_t Mask, unsigned BitSize,
                                 unsigned &Start, unsigned &End) const {
// Reject trivial all-zero masks.
Mask &= allOnes(BitSize);
if (Mask == 0)
3
←
Assuming 'Mask' is not equal to 0→
4
←
Taking false branch→
  return false;

// Handle the 1+0+ or 0+1+0* cases.  Start then specifies the index of
// the msb and End specifies the index of the lsb.
unsigned LSB, Length;
if (isStringOfOnes(Mask, LSB, Length)) {
5
←
Taking false branch→
  Start = 63 - (LSB + Length - 1);
  End = 63 - LSB;
  return true;
}

// Handle the wrap-around 1+0+1+ cases.  Start then specifies the msb
// of the low 1s and End specifies the lsb of the high 1s.
if (isStringOfOnes(Mask ^ allOnes(BitSize), LSB, Length)) {
6
←
Calling 'isStringOfOnes'→
  assert(LSB > 0 && "Bottom bit must be set")(static_cast <bool> (LSB > 0 && "Bottom bit must be set"
) ? void (0) : __assert_fail ("LSB > 0 && \"Bottom bit must be set\""
, "llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp", 1749, __extension__
 __PRETTY_FUNCTION__));
  assert(LSB + Length < BitSize && "Top bit must be set")(static_cast <bool> (LSB + Length < BitSize &&
 "Top bit must be set") ? void (0) : __assert_fail ("LSB + Length < BitSize && \"Top bit must be set\""
, "llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp", 1750, __extension__
 __PRETTY_FUNCTION__));
  Start = 63 - (LSB - 1);
  End = 63 - (LSB + Length);
  return true;
}

return false;
1757}

1759unsigned SystemZInstrInfo::getFusedCompare(unsigned Opcode,
                                         SystemZII::FusedCompareType Type,
                                         const MachineInstr *MI) const {
switch (Opcode) {
case SystemZ::CHI:
case SystemZ::CGHI:
  if (!(MI && isInt<8>(MI->getOperand(1).getImm())))
    return 0;
  break;
case SystemZ::CLFI:
case SystemZ::CLGFI:
  if (!(MI && isUInt<8>(MI->getOperand(1).getImm())))
    return 0;
  break;
case SystemZ::CL:
case SystemZ::CLG:
  if (!STI.hasMiscellaneousExtensions())
    return 0;
  if (!(MI && MI->getOperand(3).getReg() == 0))
    return 0;
  break;
}
switch (Type) {
case SystemZII::CompareAndBranch:
  switch (Opcode) {
  case SystemZ::CR:
    return SystemZ::CRJ;
  case SystemZ::CGR:
    return SystemZ::CGRJ;
  case SystemZ::CHI:
    return SystemZ::CIJ;
  case SystemZ::CGHI:
    return SystemZ::CGIJ;
  case SystemZ::CLR:
    return SystemZ::CLRJ;
  case SystemZ::CLGR:
    return SystemZ::CLGRJ;
  case SystemZ::CLFI:
    return SystemZ::CLIJ;
  case SystemZ::CLGFI:
    return SystemZ::CLGIJ;
  default:
    return 0;
  }
case SystemZII::CompareAndReturn:
  switch (Opcode) {
  case SystemZ::CR:
    return SystemZ::CRBReturn;
  case SystemZ::CGR:
    return SystemZ::CGRBReturn;
  case SystemZ::CHI:
    return SystemZ::CIBReturn;
  case SystemZ::CGHI:
    return SystemZ::CGIBReturn;
  case SystemZ::CLR:
    return SystemZ::CLRBReturn;
  case SystemZ::CLGR:
    return SystemZ::CLGRBReturn;
  case SystemZ::CLFI:
    return SystemZ::CLIBReturn;
  case SystemZ::CLGFI:
    return SystemZ::CLGIBReturn;
  default:
    return 0;
  }
case SystemZII::CompareAndSibcall:
  switch (Opcode) {
  case SystemZ::CR:
    return SystemZ::CRBCall;
  case SystemZ::CGR:
    return SystemZ::CGRBCall;
  case SystemZ::CHI:
    return SystemZ::CIBCall;
  case SystemZ::CGHI:
    return SystemZ::CGIBCall;
  case SystemZ::CLR:
    return SystemZ::CLRBCall;
  case SystemZ::CLGR:
    return SystemZ::CLGRBCall;
  case SystemZ::CLFI:
    return SystemZ::CLIBCall;
  case SystemZ::CLGFI:
    return SystemZ::CLGIBCall;
  default:
    return 0;
  }
case SystemZII::CompareAndTrap:
  switch (Opcode) {
  case SystemZ::CR:
    return SystemZ::CRT;
  case SystemZ::CGR:
    return SystemZ::CGRT;
  case SystemZ::CHI:
    return SystemZ::CIT;
  case SystemZ::CGHI:
    return SystemZ::CGIT;
  case SystemZ::CLR:
    return SystemZ::CLRT;
  case SystemZ::CLGR:
    return SystemZ::CLGRT;
  case SystemZ::CLFI:
    return SystemZ::CLFIT;
  case SystemZ::CLGFI:
    return SystemZ::CLGIT;
  case SystemZ::CL:
    return SystemZ::CLT;
  case SystemZ::CLG:
    return SystemZ::CLGT;
  default:
    return 0;
  }
}
return 0;
1872}

1874bool SystemZInstrInfo::
1875prepareCompareSwapOperands(MachineBasicBlock::iterator const MBBI) const {
assert(MBBI->isCompare() && MBBI->getOperand(0).isReg() &&(static_cast <bool> (MBBI->isCompare() && MBBI
->getOperand(0).isReg() && MBBI->getOperand(1).
isReg() && !MBBI->mayLoad() && "Not a compare reg/reg."
) ? void (0) : __assert_fail ("MBBI->isCompare() && MBBI->getOperand(0).isReg() && MBBI->getOperand(1).isReg() && !MBBI->mayLoad() && \"Not a compare reg/reg.\""
, "llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp", 1878, __extension__
 __PRETTY_FUNCTION__))
       MBBI->getOperand(1).isReg() && !MBBI->mayLoad() &&(static_cast <bool> (MBBI->isCompare() && MBBI
->getOperand(0).isReg() && MBBI->getOperand(1).
isReg() && !MBBI->mayLoad() && "Not a compare reg/reg."
) ? void (0) : __assert_fail ("MBBI->isCompare() && MBBI->getOperand(0).isReg() && MBBI->getOperand(1).isReg() && !MBBI->mayLoad() && \"Not a compare reg/reg.\""
, "llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp", 1878, __extension__
 __PRETTY_FUNCTION__))
       "Not a compare reg/reg.")(static_cast <bool> (MBBI->isCompare() && MBBI
->getOperand(0).isReg() && MBBI->getOperand(1).
isReg() && !MBBI->mayLoad() && "Not a compare reg/reg."
) ? void (0) : __assert_fail ("MBBI->isCompare() && MBBI->getOperand(0).isReg() && MBBI->getOperand(1).isReg() && !MBBI->mayLoad() && \"Not a compare reg/reg.\""
, "llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp", 1878, __extension__
 __PRETTY_FUNCTION__));

MachineBasicBlock *MBB = MBBI->getParent();
bool CCLive = true;
SmallVector<MachineInstr *, 4> CCUsers;
for (MachineInstr &MI : llvm::make_range(std::next(MBBI), MBB->end())) {
  if (MI.readsRegister(SystemZ::CC)) {
    unsigned Flags = MI.getDesc().TSFlags;
    if ((Flags & SystemZII::CCMaskFirst) || (Flags & SystemZII::CCMaskLast))
      CCUsers.push_back(&MI);
    else
      return false;
  }
  if (MI.definesRegister(SystemZ::CC)) {
    CCLive = false;
    break;
  }
}
if (CCLive) {
  LivePhysRegs LiveRegs(*MBB->getParent()->getSubtarget().getRegisterInfo());
  LiveRegs.addLiveOuts(*MBB);
  if (LiveRegs.contains(SystemZ::CC))
    return false;
}

// Update all CC users.
for (unsigned Idx = 0; Idx < CCUsers.size(); ++Idx) {
  unsigned Flags = CCUsers[Idx]->getDesc().TSFlags;
  unsigned FirstOpNum = ((Flags & SystemZII::CCMaskFirst) ?
                         0 : CCUsers[Idx]->getNumExplicitOperands() - 2);
  MachineOperand &CCMaskMO = CCUsers[Idx]->getOperand(FirstOpNum + 1);
  unsigned NewCCMask = SystemZ::reverseCCMask(CCMaskMO.getImm());
  CCMaskMO.setImm(NewCCMask);
}

return true;
1914}

1916unsigned SystemZ::reverseCCMask(unsigned CCMask) {
return ((CCMask & SystemZ::CCMASK_CMP_EQ) |
        (CCMask & SystemZ::CCMASK_CMP_GT ? SystemZ::CCMASK_CMP_LT : 0) |
        (CCMask & SystemZ::CCMASK_CMP_LT ? SystemZ::CCMASK_CMP_GT : 0) |
        (CCMask & SystemZ::CCMASK_CMP_UO));
1921}

1923MachineBasicBlock *SystemZ::emitBlockAfter(MachineBasicBlock *MBB) {
MachineFunction &MF = *MBB->getParent();
MachineBasicBlock *NewMBB = MF.CreateMachineBasicBlock(MBB->getBasicBlock());
MF.insert(std::next(MachineFunction::iterator(MBB)), NewMBB);
return NewMBB;
1928}

1930MachineBasicBlock *SystemZ::splitBlockAfter(MachineBasicBlock::iterator MI,
                                          MachineBasicBlock *MBB) {
MachineBasicBlock *NewMBB = emitBlockAfter(MBB);
NewMBB->splice(NewMBB->begin(), MBB,
               std::next(MachineBasicBlock::iterator(MI)), MBB->end());
NewMBB->transferSuccessorsAndUpdatePHIs(MBB);
return NewMBB;
1937}

1939MachineBasicBlock *SystemZ::splitBlockBefore(MachineBasicBlock::iterator MI,
                                           MachineBasicBlock *MBB) {
MachineBasicBlock *NewMBB = emitBlockAfter(MBB);
NewMBB->splice(NewMBB->begin(), MBB, MI, MBB->end());
NewMBB->transferSuccessorsAndUpdatePHIs(MBB);
return NewMBB;
1945}

1947unsigned SystemZInstrInfo::getLoadAndTrap(unsigned Opcode) const {
if (!STI.hasLoadAndTrap())
  return 0;
switch (Opcode) {
case SystemZ::L:
case SystemZ::LY:
  return SystemZ::LAT;
case SystemZ::LG:
  return SystemZ::LGAT;
case SystemZ::LFH:
  return SystemZ::LFHAT;
case SystemZ::LLGF:
  return SystemZ::LLGFAT;
case SystemZ::LLGT:
  return SystemZ::LLGTAT;
}
return 0;
1964}

1966void SystemZInstrInfo::loadImmediate(MachineBasicBlock &MBB,
                                   MachineBasicBlock::iterator MBBI,
                                   unsigned Reg, uint64_t Value) const {
DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
unsigned Opcode = 0;
if (isInt<16>(Value))
  Opcode = SystemZ::LGHI;
else if (SystemZ::isImmLL(Value))
  Opcode = SystemZ::LLILL;
else if (SystemZ::isImmLH(Value)) {
  Opcode = SystemZ::LLILH;
  Value >>= 16;
}
else if (isInt<32>(Value))
  Opcode = SystemZ::LGFI;
if (Opcode) {
  BuildMI(MBB, MBBI, DL, get(Opcode), Reg).addImm(Value);
  return;
}

MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
assert (MRI.isSSA() &&  "Huge values only handled before reg-alloc .")(static_cast <bool> (MRI.isSSA() && "Huge values only handled before reg-alloc ."
) ? void (0) : __assert_fail ("MRI.isSSA() && \"Huge values only handled before reg-alloc .\""
, "llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp", 1987, __extension__
 __PRETTY_FUNCTION__));
Register Reg0 = MRI.createVirtualRegister(&SystemZ::GR64BitRegClass);
Register Reg1 = MRI.createVirtualRegister(&SystemZ::GR64BitRegClass);
BuildMI(MBB, MBBI, DL, get(SystemZ::IMPLICIT_DEF), Reg0);
BuildMI(MBB, MBBI, DL, get(SystemZ::IIHF64), Reg1)
  .addReg(Reg0).addImm(Value >> 32);
BuildMI(MBB, MBBI, DL, get(SystemZ::IILF64), Reg)
  .addReg(Reg1).addImm(Value & ((uint64_t(1) << 32) - 1));
1995}

1997bool SystemZInstrInfo::verifyInstruction(const MachineInstr &MI,
                                       StringRef &ErrInfo) const {
const MCInstrDesc &MCID = MI.getDesc();
for (unsigned I = 0, E = MI.getNumOperands(); I != E; ++I) {
  if (I >= MCID.getNumOperands())
    break;
  const MachineOperand &Op = MI.getOperand(I);
  const MCOperandInfo &MCOI = MCID.OpInfo[I];
  // Addressing modes have register and immediate operands. Op should be a
  // register (or frame index) operand if MCOI.RegClass contains a valid
  // register class, or an immediate otherwise.
  if (MCOI.OperandType == MCOI::OPERAND_MEMORY &&
      ((MCOI.RegClass != -1 && !Op.isReg() && !Op.isFI()) ||
       (MCOI.RegClass == -1 && !Op.isImm()))) {
    ErrInfo = "Addressing mode operands corrupt!";
    return false;
  }
}

return true;
2017}

2019bool SystemZInstrInfo::
2020areMemAccessesTriviallyDisjoint(const MachineInstr &MIa,
                              const MachineInstr &MIb) const {

if (!MIa.hasOneMemOperand() || !MIb.hasOneMemOperand())
  return false;

// If mem-operands show that the same address Value is used by both
// instructions, check for non-overlapping offsets and widths. Not
// sure if a register based analysis would be an improvement...

MachineMemOperand *MMOa = *MIa.memoperands_begin();
MachineMemOperand *MMOb = *MIb.memoperands_begin();
const Value *VALa = MMOa->getValue();
const Value *VALb = MMOb->getValue();
bool SameVal = (VALa && VALb && (VALa == VALb));
if (!SameVal) {
  const PseudoSourceValue *PSVa = MMOa->getPseudoValue();
  const PseudoSourceValue *PSVb = MMOb->getPseudoValue();
  if (PSVa && PSVb && (PSVa == PSVb))
    SameVal = true;
}
if (SameVal) {
  int OffsetA = MMOa->getOffset(), OffsetB = MMOb->getOffset();
  int WidthA = MMOa->getSize(), WidthB = MMOb->getSize();
  int LowOffset = OffsetA < OffsetB ? OffsetA : OffsetB;
  int HighOffset = OffsetA < OffsetB ? OffsetB : OffsetA;
  int LowWidth = (LowOffset == OffsetA) ? WidthA : WidthB;
  if (LowOffset + LowWidth <= HighOffset)
    return true;
}

return false;
2052}

←

/build/source/llvm/include/llvm/Support/MathExtras.h

→

1//===-- llvm/Support/MathExtras.h - Useful math functions -------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains some functions that are useful for math stuff.
10//
11//===----------------------------------------------------------------------===//
12 
13#ifndef LLVM_SUPPORT_MATHEXTRAS_H
14#define LLVM_SUPPORT_MATHEXTRAS_H
15 
16#include "llvm/ADT/bit.h"
17#include "llvm/Support/Compiler.h"
18#include <cassert>
19#include <climits>
20#include <cstdint>
21#include <cstring>
22#include <limits>
23#include <type_traits>
24 
25#ifdef _MSC_VER
26// Declare these intrinsics manually rather including intrin.h. It's very
27// expensive, and MathExtras.h is popular.
28// #include <intrin.h>
29extern "C" {
30unsigned char _BitScanForward(unsigned long *_Index, unsigned long _Mask);
31unsigned char _BitScanForward64(unsigned long *_Index, unsigned __int64 _Mask);
32unsigned char _BitScanReverse(unsigned long *_Index, unsigned long _Mask);
33unsigned char _BitScanReverse64(unsigned long *_Index, unsigned __int64 _Mask);
34}
35#endif
36 
37namespace llvm {
38 
39/// The behavior an operation has on an input of 0.
40enum ZeroBehavior {
41  /// The returned value is undefined.
42  ZB_Undefined,
43  /// The returned value is numeric_limits<T>::max()
44  ZB_Max,
45  /// The returned value is numeric_limits<T>::digits
46  ZB_Width
47};
48 
49/// Mathematical constants.
50namespace numbers {
51// TODO: Track C++20 std::numbers.
52// TODO: Favor using the hexadecimal FP constants (requires C++17).
53constexpr double e          = 2.7182818284590452354, // (0x1.5bf0a8b145749P+1) https://oeis.org/A001113
54                 egamma     = .57721566490153286061, // (0x1.2788cfc6fb619P-1) https://oeis.org/A001620
55                 ln2        = .69314718055994530942, // (0x1.62e42fefa39efP-1) https://oeis.org/A002162
56                 ln10       = 2.3025850929940456840, // (0x1.24bb1bbb55516P+1) https://oeis.org/A002392
57                 log2e      = 1.4426950408889634074, // (0x1.71547652b82feP+0)
58                 log10e     = .43429448190325182765, // (0x1.bcb7b1526e50eP-2)
59                 pi         = 3.1415926535897932385, // (0x1.921fb54442d18P+1) https://oeis.org/A000796
60                 inv_pi     = .31830988618379067154, // (0x1.45f306bc9c883P-2) https://oeis.org/A049541
61                 sqrtpi     = 1.7724538509055160273, // (0x1.c5bf891b4ef6bP+0) https://oeis.org/A002161
62                 inv_sqrtpi = .56418958354775628695, // (0x1.20dd750429b6dP-1) https://oeis.org/A087197
63                 sqrt2      = 1.4142135623730950488, // (0x1.6a09e667f3bcdP+0) https://oeis.org/A00219
64                 inv_sqrt2  = .70710678118654752440, // (0x1.6a09e667f3bcdP-1)
65                 sqrt3      = 1.7320508075688772935, // (0x1.bb67ae8584caaP+0) https://oeis.org/A002194
66                 inv_sqrt3  = .57735026918962576451, // (0x1.279a74590331cP-1)
67                 phi        = 1.6180339887498948482; // (0x1.9e3779b97f4a8P+0) https://oeis.org/A001622
68constexpr float ef          = 2.71828183F, // (0x1.5bf0a8P+1) https://oeis.org/A001113
69                egammaf     = .577215665F, // (0x1.2788d0P-1) https://oeis.org/A001620
70                ln2f        = .693147181F, // (0x1.62e430P-1) https://oeis.org/A002162
71                ln10f       = 2.30258509F, // (0x1.26bb1cP+1) https://oeis.org/A002392
72                log2ef      = 1.44269504F, // (0x1.715476P+0)
73                log10ef     = .434294482F, // (0x1.bcb7b2P-2)
74                pif         = 3.14159265F, // (0x1.921fb6P+1) https://oeis.org/A000796
75                inv_pif     = .318309886F, // (0x1.45f306P-2) https://oeis.org/A049541
76                sqrtpif     = 1.77245385F, // (0x1.c5bf8aP+0) https://oeis.org/A002161
77                inv_sqrtpif = .564189584F, // (0x1.20dd76P-1) https://oeis.org/A087197
78                sqrt2f      = 1.41421356F, // (0x1.6a09e6P+0) https://oeis.org/A002193
79                inv_sqrt2f  = .707106781F, // (0x1.6a09e6P-1)
80                sqrt3f      = 1.73205081F, // (0x1.bb67aeP+0) https://oeis.org/A002194
81                inv_sqrt3f  = .577350269F, // (0x1.279a74P-1)
82                phif        = 1.61803399F; // (0x1.9e377aP+0) https://oeis.org/A001622
83} // namespace numbers
84 
85namespace detail {
86template <typename T, std::size_t SizeOfT> struct TrailingZerosCounter {
87  static unsigned count(T Val, ZeroBehavior) {
88    if (!Val)
89      return std::numeric_limits<T>::digits;
90    if (Val & 0x1)
91      return 0;
92 
93    // Bisection method.
94    unsigned ZeroBits = 0;
95    T Shift = std::numeric_limits<T>::digits >> 1;
96    T Mask = std::numeric_limits<T>::max() >> Shift;
97    while (Shift) {
98      if ((Val & Mask) == 0) {
99        Val >>= Shift;
100        ZeroBits |= Shift;
101      }
102      Shift >>= 1;
103      Mask >>= Shift;
104    }
105    return ZeroBits;
106  }
107};
108 
109#if defined(__GNUC__4) || defined(_MSC_VER)
110template <typename T> struct TrailingZerosCounter<T, 4> {
111  static unsigned count(T Val, ZeroBehavior ZB) {
112    if (ZB != ZB_Undefined && Val == 0)
113      return 32;
114 
115#if __has_builtin(__builtin_ctz)1 || defined(__GNUC__4)
116    return __builtin_ctz(Val);
117#elif defined(_MSC_VER)
118    unsigned long Index;
119    _BitScanForward(&Index, Val);
120    return Index;
121#endif
122  }
123};
124 
125#if !defined(_MSC_VER) || defined(_M_X64)
126template <typename T> struct TrailingZerosCounter<T, 8> {
127  static unsigned count(T Val, ZeroBehavior ZB) {
128    if (ZB != ZB_Undefined && Val == 0)
129      return 64;
130 
131#if __has_builtin(__builtin_ctzll)1 || defined(__GNUC__4)
132    return __builtin_ctzll(Val);
133#elif defined(_MSC_VER)
134    unsigned long Index;
135    _BitScanForward64(&Index, Val);
136    return Index;
137#endif
138  }
139};
140#endif
141#endif
142} // namespace detail
143 
144/// Count number of 0's from the least significant bit to the most
145///   stopping at the first 1.
146///
147/// Only unsigned integral types are allowed.
148///
149/// \param ZB the behavior on an input of 0. Only ZB_Width and ZB_Undefined are
150///   valid arguments.
151template <typename T>
152unsigned countTrailingZeros(T Val, ZeroBehavior ZB = ZB_Width) {
153  static_assert(std::is_unsigned_v<T>,
154                "Only unsigned integral types are allowed.");
155  return llvm::detail::TrailingZerosCounter<T, sizeof(T)>::count(Val, ZB);
156}
157 
158namespace detail {
159template <typename T, std::size_t SizeOfT> struct LeadingZerosCounter {
160  static unsigned count(T Val, ZeroBehavior) {
161    if (!Val)
162      return std::numeric_limits<T>::digits;
163 
164    // Bisection method.
165    unsigned ZeroBits = 0;
166    for (T Shift = std::numeric_limits<T>::digits >> 1; Shift; Shift >>= 1) {
167      T Tmp = Val >> Shift;
168      if (Tmp)
169        Val = Tmp;
170      else
171        ZeroBits |= Shift;
172    }
173    return ZeroBits;
174  }
175};
176 
177#if defined(__GNUC__4) || defined(_MSC_VER)
178template <typename T> struct LeadingZerosCounter<T, 4> {
179  static unsigned count(T Val, ZeroBehavior ZB) {
180    if (ZB != ZB_Undefined && Val == 0)
181      return 32;
182 
183#if __has_builtin(__builtin_clz)1 || defined(__GNUC__4)
184    return __builtin_clz(Val);
185#elif defined(_MSC_VER)
186    unsigned long Index;
187    _BitScanReverse(&Index, Val);
188    return Index ^ 31;
189#endif
190  }
191};
192 
193#if !defined(_MSC_VER) || defined(_M_X64)
194template <typename T> struct LeadingZerosCounter<T, 8> {
195  static unsigned count(T Val, ZeroBehavior ZB) {
196    if (ZB != ZB_Undefined && Val == 0)
197      return 64;
198 
199#if __has_builtin(__builtin_clzll)1 || defined(__GNUC__4)
200    return __builtin_clzll(Val);
201#elif defined(_MSC_VER)
202    unsigned long Index;
203    _BitScanReverse64(&Index, Val);
204    return Index ^ 63;
205#endif
206  }
207};
208#endif
209#endif
210} // namespace detail
211 
212/// Count number of 0's from the most significant bit to the least
213///   stopping at the first 1.
214///
215/// Only unsigned integral types are allowed.
216///
217/// \param ZB the behavior on an input of 0. Only ZB_Width and ZB_Undefined are
218///   valid arguments.
219template <typename T>
220unsigned countLeadingZeros(T Val, ZeroBehavior ZB = ZB_Width) {
221  static_assert(std::is_unsigned_v<T>,
222                "Only unsigned integral types are allowed.");
223  return llvm::detail::LeadingZerosCounter<T, sizeof(T)>::count(Val, ZB);
224}
225 
226/// Get the index of the first set bit starting from the least
227///   significant bit.
228///
229/// Only unsigned integral types are allowed.
230///
231/// \param ZB the behavior on an input of 0. Only ZB_Max and ZB_Undefined are
232///   valid arguments.
233template <typename T> T findFirstSet(T Val, ZeroBehavior ZB = ZB_Max) {
234  if (ZB7.1
'ZB' is equal to ZB_Max
7.1
'ZB' is equal to ZB_Max
7.1
'ZB' is equal to ZB_Max
 == ZB_Max && Val == 0)
8
←
Assuming 'Val' is equal to 0→
9
←
Taking true branch→
235    return std::numeric_limits<T>::max();
10
←
Calling 'numeric_limits::max'→
12
←
Returning from 'numeric_limits::max'→
13
←
Returning the value 18446744073709551615→
236 
237  return countTrailingZeros(Val, ZB_Undefined);
238}
239 
240/// Create a bitmask with the N right-most bits set to 1, and all other
241/// bits set to 0.  Only unsigned types are allowed.
242template <typename T> T maskTrailingOnes(unsigned N) {
243  static_assert(std::is_unsigned<T>::value, "Invalid type!");
244  const unsigned Bits = CHAR_BIT8 * sizeof(T);
245  assert(N <= Bits && "Invalid bit index")(static_cast <bool> (N <= Bits && "Invalid bit index"
) ? void (0) : __assert_fail ("N <= Bits && \"Invalid bit index\""
, "llvm/include/llvm/Support/MathExtras.h", 245, __extension__
 __PRETTY_FUNCTION__));
246  return N == 0 ? 0 : (T(-1) >> (Bits - N));
247}
248 
249/// Create a bitmask with the N left-most bits set to 1, and all other
250/// bits set to 0.  Only unsigned types are allowed.
251template <typename T> T maskLeadingOnes(unsigned N) {
252  return ~maskTrailingOnes<T>(CHAR_BIT8 * sizeof(T) - N);
253}
254 
255/// Create a bitmask with the N right-most bits set to 0, and all other
256/// bits set to 1.  Only unsigned types are allowed.
257template <typename T> T maskTrailingZeros(unsigned N) {
258  return maskLeadingOnes<T>(CHAR_BIT8 * sizeof(T) - N);
259}
260 
261/// Create a bitmask with the N left-most bits set to 0, and all other
262/// bits set to 1.  Only unsigned types are allowed.
263template <typename T> T maskLeadingZeros(unsigned N) {
264  return maskTrailingOnes<T>(CHAR_BIT8 * sizeof(T) - N);
265}
266 
267/// Get the index of the last set bit starting from the least
268///   significant bit.
269///
270/// Only unsigned integral types are allowed.
271///
272/// \param ZB the behavior on an input of 0. Only ZB_Max and ZB_Undefined are
273///   valid arguments.
274template <typename T> T findLastSet(T Val, ZeroBehavior ZB = ZB_Max) {
275  if (ZB == ZB_Max && Val == 0)
276    return std::numeric_limits<T>::max();
277 
278  // Use ^ instead of - because both gcc and llvm can remove the associated ^
279  // in the __builtin_clz intrinsic on x86.
280  return countLeadingZeros(Val, ZB_Undefined) ^
281         (std::numeric_limits<T>::digits - 1);
282}
283 
284/// Macro compressed bit reversal table for 256 bits.
285///
286/// http://graphics.stanford.edu/~seander/bithacks.html#BitReverseTable
287static const unsigned char BitReverseTable256[256] = {
288#define R2(n) n, n + 2 * 64, n + 1 * 64, n + 3 * 64
289#define R4(n) R2(n), R2(n + 2 * 16), R2(n + 1 * 16), R2(n + 3 * 16)
290#define R6(n) R4(n), R4(n + 2 * 4), R4(n + 1 * 4), R4(n + 3 * 4)
291  R6(0), R6(2), R6(1), R6(3)
292#undef R2
293#undef R4
294#undef R6
295};
296 
297/// Reverse the bits in \p Val.
298template <typename T> T reverseBits(T Val) {
299#if __has_builtin(__builtin_bitreverse8)1
300  if constexpr (std::is_same_v<T, uint8_t>)
301    return __builtin_bitreverse8(Val);
302#endif
303#if __has_builtin(__builtin_bitreverse16)1
304  if constexpr (std::is_same_v<T, uint16_t>)
305    return __builtin_bitreverse16(Val);
306#endif
307#if __has_builtin(__builtin_bitreverse32)1
308  if constexpr (std::is_same_v<T, uint32_t>)
309    return __builtin_bitreverse32(Val);
310#endif
311#if __has_builtin(__builtin_bitreverse64)1
312  if constexpr (std::is_same_v<T, uint64_t>)
313    return __builtin_bitreverse64(Val);
314#endif
315 
316  unsigned char in[sizeof(Val)];
317  unsigned char out[sizeof(Val)];
318  std::memcpy(in, &Val, sizeof(Val));
319  for (unsigned i = 0; i < sizeof(Val); ++i)
320    out[(sizeof(Val) - i) - 1] = BitReverseTable256[in[i]];
321  std::memcpy(&Val, out, sizeof(Val));
322  return Val;
323}
324 
325// NOTE: The following support functions use the _32/_64 extensions instead of
326// type overloading so that signed and unsigned integers can be used without
327// ambiguity.
328 
329/// Return the high 32 bits of a 64 bit value.
330constexpr inline uint32_t Hi_32(uint64_t Value) {
331  return static_cast<uint32_t>(Value >> 32);
332}
333 
334/// Return the low 32 bits of a 64 bit value.
335constexpr inline uint32_t Lo_32(uint64_t Value) {
336  return static_cast<uint32_t>(Value);
337}
338 
339/// Make a 64-bit integer from a high / low pair of 32-bit integers.
340constexpr inline uint64_t Make_64(uint32_t High, uint32_t Low) {
341  return ((uint64_t)High << 32) | (uint64_t)Low;
342}
343 
344/// Checks if an integer fits into the given bit width.
345template <unsigned N> constexpr inline bool isInt(int64_t x) {
346  if constexpr (N == 8)
347    return static_cast<int8_t>(x) == x;
348  if constexpr (N == 16)
349    return static_cast<int16_t>(x) == x;
350  if constexpr (N == 32)
351    return static_cast<int32_t>(x) == x;
352  if constexpr (N < 64)
353    return -(INT64_C(1)1L << (N - 1)) <= x && x < (INT64_C(1)1L << (N - 1));
354  (void)x; // MSVC v19.25 warns that x is unused.
355  return true;
356}
357 
358/// Checks if a signed integer is an N bit number shifted left by S.
359template <unsigned N, unsigned S>
360constexpr inline bool isShiftedInt(int64_t x) {
361  static_assert(
362      N > 0, "isShiftedInt<0> doesn't make sense (refers to a 0-bit number.");
363  static_assert(N + S <= 64, "isShiftedInt<N, S> with N + S > 64 is too wide.");
364  return isInt<N + S>(x) && (x % (UINT64_C(1)1UL << S) == 0);
365}
366 
367/// Checks if an unsigned integer fits into the given bit width.
368template <unsigned N> constexpr inline bool isUInt(uint64_t x) {
369  static_assert(N > 0, "isUInt<0> doesn't make sense");
370  if constexpr (N == 8)
371    return static_cast<uint8_t>(x) == x;
372  if constexpr (N == 16)
373    return static_cast<uint16_t>(x) == x;
374  if constexpr (N == 32)
375    return static_cast<uint32_t>(x) == x;
376  if constexpr (N < 64)
377    return x < (UINT64_C(1)1UL << (N));
378  (void)x; // MSVC v19.25 warns that x is unused.
379  return true;
380}
381 
382/// Checks if a unsigned integer is an N bit number shifted left by S.
383template <unsigned N, unsigned S>
384constexpr inline bool isShiftedUInt(uint64_t x) {
385  static_assert(
386      N > 0, "isShiftedUInt<0> doesn't make sense (refers to a 0-bit number)");
387  static_assert(N + S <= 64,
388                "isShiftedUInt<N, S> with N + S > 64 is too wide.");
389  // Per the two static_asserts above, S must be strictly less than 64.  So
390  // 1 << S is not undefined behavior.
391  return isUInt<N + S>(x) && (x % (UINT64_C(1)1UL << S) == 0);
392}
393 
394/// Gets the maximum value for a N-bit unsigned integer.
395inline uint64_t maxUIntN(uint64_t N) {
396  assert(N > 0 && N <= 64 && "integer width out of range")(static_cast <bool> (N > 0 && N <= 64 &&
 "integer width out of range") ? void (0) : __assert_fail ("N > 0 && N <= 64 && \"integer width out of range\""
, "llvm/include/llvm/Support/MathExtras.h", 396, __extension__
 __PRETTY_FUNCTION__));
397 
398  // uint64_t(1) << 64 is undefined behavior, so we can't do
399  //   (uint64_t(1) << N) - 1
400  // without checking first that N != 64.  But this works and doesn't have a
401  // branch.
402  return UINT64_MAX(18446744073709551615UL) >> (64 - N);
403}
404 
405/// Gets the minimum value for a N-bit signed integer.
406inline int64_t minIntN(int64_t N) {
407  assert(N > 0 && N <= 64 && "integer width out of range")(static_cast <bool> (N > 0 && N <= 64 &&
 "integer width out of range") ? void (0) : __assert_fail ("N > 0 && N <= 64 && \"integer width out of range\""
, "llvm/include/llvm/Support/MathExtras.h", 407, __extension__
 __PRETTY_FUNCTION__));
408 
409  return UINT64_C(1)1UL + ~(UINT64_C(1)1UL << (N - 1));
410}
411 
412/// Gets the maximum value for a N-bit signed integer.
413inline int64_t maxIntN(int64_t N) {
414  assert(N > 0 && N <= 64 && "integer width out of range")(static_cast <bool> (N > 0 && N <= 64 &&
 "integer width out of range") ? void (0) : __assert_fail ("N > 0 && N <= 64 && \"integer width out of range\""
, "llvm/include/llvm/Support/MathExtras.h", 414, __extension__
 __PRETTY_FUNCTION__));
415 
416  // This relies on two's complement wraparound when N == 64, so we convert to
417  // int64_t only at the very end to avoid UB.
418  return (UINT64_C(1)1UL << (N - 1)) - 1;
419}
420 
421/// Checks if an unsigned integer fits into the given (dynamic) bit width.
422inline bool isUIntN(unsigned N, uint64_t x) {
423  return N >= 64 || x <= maxUIntN(N);
424}
425 
426/// Checks if an signed integer fits into the given (dynamic) bit width.
427inline bool isIntN(unsigned N, int64_t x) {
428  return N >= 64 || (minIntN(N) <= x && x <= maxIntN(N));
429}
430 
431/// Return true if the argument is a non-empty sequence of ones starting at the
432/// least significant bit with the remainder zero (32 bit version).
433/// Ex. isMask_32(0x0000FFFFU) == true.
434constexpr inline bool isMask_32(uint32_t Value) {
435  return Value && ((Value + 1) & Value) == 0;
436}
437 
438/// Return true if the argument is a non-empty sequence of ones starting at the
439/// least significant bit with the remainder zero (64 bit version).
440constexpr inline bool isMask_64(uint64_t Value) {
441  return Value && ((Value + 1) & Value) == 0;
442}
443 
444/// Return true if the argument contains a non-empty sequence of ones with the
445/// remainder zero (32 bit version.) Ex. isShiftedMask_32(0x0000FF00U) == true.
446constexpr inline bool isShiftedMask_32(uint32_t Value) {
447  return Value && isMask_32((Value - 1) | Value);
448}
449 
450/// Return true if the argument contains a non-empty sequence of ones with the
451/// remainder zero (64 bit version.)
452constexpr inline bool isShiftedMask_64(uint64_t Value) {
453  return Value && isMask_64((Value - 1) | Value);
454}
455 
456/// Return true if the argument is a power of two > 0.
457/// Ex. isPowerOf2_32(0x00100000U) == true (32 bit edition.)
458constexpr inline bool isPowerOf2_32(uint32_t Value) {
459  return llvm::has_single_bit(Value);
460}
461 
462/// Return true if the argument is a power of two > 0 (64 bit edition.)
463constexpr inline bool isPowerOf2_64(uint64_t Value) {
464  return llvm::has_single_bit(Value);
465}
466 
467/// Count the number of ones from the most significant bit to the first
468/// zero bit.
469///
470/// Ex. countLeadingOnes(0xFF0FFF00) == 8.
471/// Only unsigned integral types are allowed.
472///
473/// \param ZB the behavior on an input of all ones. Only ZB_Width and
474/// ZB_Undefined are valid arguments.
475template <typename T>
476unsigned countLeadingOnes(T Value, ZeroBehavior ZB = ZB_Width) {
477  static_assert(std::is_unsigned_v<T>,
478                "Only unsigned integral types are allowed.");
479  return countLeadingZeros<T>(~Value, ZB);
480}
481 
482/// Count the number of ones from the least significant bit to the first
483/// zero bit.
484///
485/// Ex. countTrailingOnes(0x00FF00FF) == 8.
486/// Only unsigned integral types are allowed.
487///
488/// \param ZB the behavior on an input of all ones. Only ZB_Width and
489/// ZB_Undefined are valid arguments.
490template <typename T>
491unsigned countTrailingOnes(T Value, ZeroBehavior ZB = ZB_Width) {
492  static_assert(std::is_unsigned_v<T>,
493                "Only unsigned integral types are allowed.");
494  return countTrailingZeros<T>(~Value, ZB);
495}
496 
497/// Count the number of set bits in a value.
498/// Ex. countPopulation(0xF000F000) = 8
499/// Returns 0 if the word is zero.
500template <typename T>
501inline unsigned countPopulation(T Value) {
502  static_assert(std::is_unsigned_v<T>,
503                "Only unsigned integral types are allowed.");
504  return (unsigned)llvm::popcount(Value);
505}
506 
507/// Return true if the argument contains a non-empty sequence of ones with the
508/// remainder zero (32 bit version.) Ex. isShiftedMask_32(0x0000FF00U) == true.
509/// If true, \p MaskIdx will specify the index of the lowest set bit and \p
510/// MaskLen is updated to specify the length of the mask, else neither are
511/// updated.
512inline bool isShiftedMask_32(uint32_t Value, unsigned &MaskIdx,
513                             unsigned &MaskLen) {
514  if (!isShiftedMask_32(Value))
515    return false;
516  MaskIdx = countTrailingZeros(Value);
517  MaskLen = countPopulation(Value);
518  return true;
519}
520 
521/// Return true if the argument contains a non-empty sequence of ones with the
522/// remainder zero (64 bit version.) If true, \p MaskIdx will specify the index
523/// of the lowest set bit and \p MaskLen is updated to specify the length of the
524/// mask, else neither are updated.
525inline bool isShiftedMask_64(uint64_t Value, unsigned &MaskIdx,
526                             unsigned &MaskLen) {
527  if (!isShiftedMask_64(Value))
528    return false;
529  MaskIdx = countTrailingZeros(Value);
530  MaskLen = countPopulation(Value);
531  return true;
532}
533 
534/// Compile time Log2.
535/// Valid only for positive powers of two.
536template <size_t kValue> constexpr inline size_t CTLog2() {
537  static_assert(kValue > 0 && llvm::isPowerOf2_64(kValue),
538                "Value is not a valid power of 2");
539  return 1 + CTLog2<kValue / 2>();
540}
541 
542template <> constexpr inline size_t CTLog2<1>() { return 0; }
543 
544/// Return the floor log base 2 of the specified value, -1 if the value is zero.
545/// (32 bit edition.)
546/// Ex. Log2_32(32) == 5, Log2_32(1) == 0, Log2_32(0) == -1, Log2_32(6) == 2
547inline unsigned Log2_32(uint32_t Value) {
548  return 31 - countLeadingZeros(Value);
549}
550 
551/// Return the floor log base 2 of the specified value, -1 if the value is zero.
552/// (64 bit edition.)
553inline unsigned Log2_64(uint64_t Value) {
554  return 63 - countLeadingZeros(Value);
555}
556 
557/// Return the ceil log base 2 of the specified value, 32 if the value is zero.
558/// (32 bit edition).
559/// Ex. Log2_32_Ceil(32) == 5, Log2_32_Ceil(1) == 0, Log2_32_Ceil(6) == 3
560inline unsigned Log2_32_Ceil(uint32_t Value) {
561  return 32 - countLeadingZeros(Value - 1);
562}
563 
564/// Return the ceil log base 2 of the specified value, 64 if the value is zero.
565/// (64 bit edition.)
566inline unsigned Log2_64_Ceil(uint64_t Value) {
567  return 64 - countLeadingZeros(Value - 1);
568}
569 
570/// This function takes a 64-bit integer and returns the bit equivalent double.
571inline double BitsToDouble(uint64_t Bits) {
572  static_assert(sizeof(uint64_t) == sizeof(double), "Unexpected type sizes");
573  return llvm::bit_cast<double>(Bits);
574}
575 
576/// This function takes a 32-bit integer and returns the bit equivalent float.
577inline float BitsToFloat(uint32_t Bits) {
578  static_assert(sizeof(uint32_t) == sizeof(float), "Unexpected type sizes");
579  return llvm::bit_cast<float>(Bits);
580}
581 
582/// This function takes a double and returns the bit equivalent 64-bit integer.
583/// Note that copying doubles around changes the bits of NaNs on some hosts,
584/// notably x86, so this routine cannot be used if these bits are needed.
585inline uint64_t DoubleToBits(double Double) {
586  static_assert(sizeof(uint64_t) == sizeof(double), "Unexpected type sizes");
587  return llvm::bit_cast<uint64_t>(Double);
588}
589 
590/// This function takes a float and returns the bit equivalent 32-bit integer.
591/// Note that copying floats around changes the bits of NaNs on some hosts,
592/// notably x86, so this routine cannot be used if these bits are needed.
593inline uint32_t FloatToBits(float Float) {
594  static_assert(sizeof(uint32_t) == sizeof(float), "Unexpected type sizes");
595  return llvm::bit_cast<uint32_t>(Float);
596}
597 
598/// A and B are either alignments or offsets. Return the minimum alignment that
599/// may be assumed after adding the two together.
600constexpr inline uint64_t MinAlign(uint64_t A, uint64_t B) {
601  // The largest power of 2 that divides both A and B.
602  //
603  // Replace "-Value" by "1+~Value" in the following commented code to avoid
604  // MSVC warning C4146
605  //    return (A | B) & -(A | B);
606  return (A | B) & (1 + ~(A | B));
607}
608 
609/// Returns the next power of two (in 64-bits) that is strictly greater than A.
610/// Returns zero on overflow.
611constexpr inline uint64_t NextPowerOf2(uint64_t A) {
612  A |= (A >> 1);
613  A |= (A >> 2);
614  A |= (A >> 4);
615  A |= (A >> 8);
616  A |= (A >> 16);
617  A |= (A >> 32);
618  return A + 1;
619}
620 
621/// Returns the power of two which is less than or equal to the given value.
622/// Essentially, it is a floor operation across the domain of powers of two.
623inline uint64_t PowerOf2Floor(uint64_t A) {
624  if (!A) return 0;
625  return 1ull << (63 - countLeadingZeros(A, ZB_Undefined));
626}
627 
628/// Returns the power of two which is greater than or equal to the given value.
629/// Essentially, it is a ceil operation across the domain of powers of two.
630inline uint64_t PowerOf2Ceil(uint64_t A) {
631  if (!A)
632    return 0;
633  return NextPowerOf2(A - 1);
634}
635 
636/// Returns the next integer (mod 2**64) that is greater than or equal to
637/// \p Value and is a multiple of \p Align. \p Align must be non-zero.
638///
639/// Examples:
640/// \code
641///   alignTo(5, 8) = 8
642///   alignTo(17, 8) = 24
643///   alignTo(~0LL, 8) = 0
644///   alignTo(321, 255) = 510
645/// \endcode
646inline uint64_t alignTo(uint64_t Value, uint64_t Align) {
647  assert(Align != 0u && "Align can't be 0.")(static_cast <bool> (Align != 0u && "Align can't be 0."
) ? void (0) : __assert_fail ("Align != 0u && \"Align can't be 0.\""
, "llvm/include/llvm/Support/MathExtras.h", 647, __extension__
 __PRETTY_FUNCTION__));
648  return (Value + Align - 1) / Align * Align;
649}
650 
651inline uint64_t alignToPowerOf2(uint64_t Value, uint64_t Align) {
652  assert(Align != 0 && (Align & (Align - 1)) == 0 &&(static_cast <bool> (Align != 0 && (Align &
 (Align - 1)) == 0 && "Align must be a power of 2") ?
 void (0) : __assert_fail ("Align != 0 && (Align & (Align - 1)) == 0 && \"Align must be a power of 2\""
, "llvm/include/llvm/Support/MathExtras.h", 653, __extension__
 __PRETTY_FUNCTION__))
653         "Align must be a power of 2")(static_cast <bool> (Align != 0 && (Align &
 (Align - 1)) == 0 && "Align must be a power of 2") ?
 void (0) : __assert_fail ("Align != 0 && (Align & (Align - 1)) == 0 && \"Align must be a power of 2\""
, "llvm/include/llvm/Support/MathExtras.h", 653, __extension__
 __PRETTY_FUNCTION__));
654  return (Value + Align - 1) & -Align;
655}
656 
657/// If non-zero \p Skew is specified, the return value will be a minimal integer
658/// that is greater than or equal to \p Size and equal to \p A * N + \p Skew for
659/// some integer N. If \p Skew is larger than \p A, its value is adjusted to '\p
660/// Skew mod \p A'. \p Align must be non-zero.
661///
662/// Examples:
663/// \code
664///   alignTo(5, 8, 7) = 7
665///   alignTo(17, 8, 1) = 17
666///   alignTo(~0LL, 8, 3) = 3
667///   alignTo(321, 255, 42) = 552
668/// \endcode
669inline uint64_t alignTo(uint64_t Value, uint64_t Align, uint64_t Skew) {
670  assert(Align != 0u && "Align can't be 0.")(static_cast <bool> (Align != 0u && "Align can't be 0."
) ? void (0) : __assert_fail ("Align != 0u && \"Align can't be 0.\""
, "llvm/include/llvm/Support/MathExtras.h", 670, __extension__
 __PRETTY_FUNCTION__));
671  Skew %= Align;
672  return alignTo(Value - Skew, Align) + Skew;
673}
674 
675/// Returns the next integer (mod 2**64) that is greater than or equal to
676/// \p Value and is a multiple of \c Align. \c Align must be non-zero.
677template <uint64_t Align> constexpr inline uint64_t alignTo(uint64_t Value) {
678  static_assert(Align != 0u, "Align must be non-zero");
679  return (Value + Align - 1) / Align * Align;
680}
681 
682/// Returns the integer ceil(Numerator / Denominator).
683inline uint64_t divideCeil(uint64_t Numerator, uint64_t Denominator) {
684  return alignTo(Numerator, Denominator) / Denominator;
685}
686 
687/// Returns the integer nearest(Numerator / Denominator).
688inline uint64_t divideNearest(uint64_t Numerator, uint64_t Denominator) {
689  return (Numerator + (Denominator / 2)) / Denominator;
690}
691 
692/// Returns the largest uint64_t less than or equal to \p Value and is
693/// \p Skew mod \p Align. \p Align must be non-zero
694inline uint64_t alignDown(uint64_t Value, uint64_t Align, uint64_t Skew = 0) {
695  assert(Align != 0u && "Align can't be 0.")(static_cast <bool> (Align != 0u && "Align can't be 0."
) ? void (0) : __assert_fail ("Align != 0u && \"Align can't be 0.\""
, "llvm/include/llvm/Support/MathExtras.h", 695, __extension__
 __PRETTY_FUNCTION__));
696  Skew %= Align;
697  return (Value - Skew) / Align * Align + Skew;
698}
699 
700/// Sign-extend the number in the bottom B bits of X to a 32-bit integer.
701/// Requires 0 < B <= 32.
702template <unsigned B> constexpr inline int32_t SignExtend32(uint32_t X) {
703  static_assert(B > 0, "Bit width can't be 0.");
704  static_assert(B <= 32, "Bit width out of range.");
705  return int32_t(X << (32 - B)) >> (32 - B);
706}
707 
708/// Sign-extend the number in the bottom B bits of X to a 32-bit integer.
709/// Requires 0 < B <= 32.
710inline int32_t SignExtend32(uint32_t X, unsigned B) {
711  assert(B > 0 && "Bit width can't be 0.")(static_cast <bool> (B > 0 && "Bit width can't be 0."
) ? void (0) : __assert_fail ("B > 0 && \"Bit width can't be 0.\""
, "llvm/include/llvm/Support/MathExtras.h", 711, __extension__
 __PRETTY_FUNCTION__));
712  assert(B <= 32 && "Bit width out of range.")(static_cast <bool> (B <= 32 && "Bit width out of range."
) ? void (0) : __assert_fail ("B <= 32 && \"Bit width out of range.\""
, "llvm/include/llvm/Support/MathExtras.h", 712, __extension__
 __PRETTY_FUNCTION__));
713  return int32_t(X << (32 - B)) >> (32 - B);
714}
715 
716/// Sign-extend the number in the bottom B bits of X to a 64-bit integer.
717/// Requires 0 < B <= 64.
718template <unsigned B> constexpr inline int64_t SignExtend64(uint64_t x) {
719  static_assert(B > 0, "Bit width can't be 0.");
720  static_assert(B <= 64, "Bit width out of range.");
721  return int64_t(x << (64 - B)) >> (64 - B);
722}
723 
724/// Sign-extend the number in the bottom B bits of X to a 64-bit integer.
725/// Requires 0 < B <= 64.
726inline int64_t SignExtend64(uint64_t X, unsigned B) {
727  assert(B > 0 && "Bit width can't be 0.")(static_cast <bool> (B > 0 && "Bit width can't be 0."
) ? void (0) : __assert_fail ("B > 0 && \"Bit width can't be 0.\""
, "llvm/include/llvm/Support/MathExtras.h", 727, __extension__
 __PRETTY_FUNCTION__));
728  assert(B <= 64 && "Bit width out of range.")(static_cast <bool> (B <= 64 && "Bit width out of range."
) ? void (0) : __assert_fail ("B <= 64 && \"Bit width out of range.\""
, "llvm/include/llvm/Support/MathExtras.h", 728, __extension__
 __PRETTY_FUNCTION__));
729  return int64_t(X << (64 - B)) >> (64 - B);
730}
731 
732/// Subtract two unsigned integers, X and Y, of type T and return the absolute
733/// value of the result.
734template <typename T>
735std::enable_if_t<std::is_unsigned<T>::value, T> AbsoluteDifference(T X, T Y) {
736  return X > Y ? (X - Y) : (Y - X);
737}
738 
739/// Add two unsigned integers, X and Y, of type T.  Clamp the result to the
740/// maximum representable value of T on overflow.  ResultOverflowed indicates if
741/// the result is larger than the maximum representable value of type T.
742template <typename T>
743std::enable_if_t<std::is_unsigned<T>::value, T>
744SaturatingAdd(T X, T Y, bool *ResultOverflowed = nullptr) {
745  bool Dummy;
746  bool &Overflowed = ResultOverflowed ? *ResultOverflowed : Dummy;
747  // Hacker's Delight, p. 29
748  T Z = X + Y;
749  Overflowed = (Z < X || Z < Y);
750  if (Overflowed)
751    return std::numeric_limits<T>::max();
752  else
753    return Z;
754}
755 
756/// Add multiple unsigned integers of type T.  Clamp the result to the
757/// maximum representable value of T on overflow.
758template <class T, class... Ts>
759std::enable_if_t<std::is_unsigned_v<T>, T> SaturatingAdd(T X, T Y, T Z,
760                                                         Ts... Args) {
761  bool Overflowed = false;
762  T XY = SaturatingAdd(X, Y, &Overflowed);
763  if (Overflowed)
764    return SaturatingAdd(std::numeric_limits<T>::max(), T(1), Args...);
765  return SaturatingAdd(XY, Z, Args...);
766}
767 
768/// Multiply two unsigned integers, X and Y, of type T.  Clamp the result to the
769/// maximum representable value of T on overflow.  ResultOverflowed indicates if
770/// the result is larger than the maximum representable value of type T.
771template <typename T>
772std::enable_if_t<std::is_unsigned<T>::value, T>
773SaturatingMultiply(T X, T Y, bool *ResultOverflowed = nullptr) {
774  bool Dummy;
775  bool &Overflowed = ResultOverflowed ? *ResultOverflowed : Dummy;
776 
777  // Hacker's Delight, p. 30 has a different algorithm, but we don't use that
778  // because it fails for uint16_t (where multiplication can have undefined
779  // behavior due to promotion to int), and requires a division in addition
780  // to the multiplication.
781 
782  Overflowed = false;
783 
784  // Log2(Z) would be either Log2Z or Log2Z + 1.
785  // Special case: if X or Y is 0, Log2_64 gives -1, and Log2Z
786  // will necessarily be less than Log2Max as desired.
787  int Log2Z = Log2_64(X) + Log2_64(Y);
788  const T Max = std::numeric_limits<T>::max();
789  int Log2Max = Log2_64(Max);
790  if (Log2Z < Log2Max) {
791    return X * Y;
792  }
793  if (Log2Z > Log2Max) {
794    Overflowed = true;
795    return Max;
796  }
797 
798  // We're going to use the top bit, and maybe overflow one
799  // bit past it. Multiply all but the bottom bit then add
800  // that on at the end.
801  T Z = (X >> 1) * Y;
802  if (Z & ~(Max >> 1)) {
803    Overflowed = true;
804    return Max;
805  }
806  Z <<= 1;
807  if (X & 1)
808    return SaturatingAdd(Z, Y, ResultOverflowed);
809 
810  return Z;
811}
812 
813/// Multiply two unsigned integers, X and Y, and add the unsigned integer, A to
814/// the product. Clamp the result to the maximum representable value of T on
815/// overflow. ResultOverflowed indicates if the result is larger than the
816/// maximum representable value of type T.
817template <typename T>
818std::enable_if_t<std::is_unsigned<T>::value, T>
819SaturatingMultiplyAdd(T X, T Y, T A, bool *ResultOverflowed = nullptr) {
820  bool Dummy;
821  bool &Overflowed = ResultOverflowed ? *ResultOverflowed : Dummy;
822 
823  T Product = SaturatingMultiply(X, Y, &Overflowed);
824  if (Overflowed)
825    return Product;
826 
827  return SaturatingAdd(A, Product, &Overflowed);
828}
829 
830/// Use this rather than HUGE_VALF; the latter causes warnings on MSVC.
831extern const float huge_valf;
832 
833 
834/// Add two signed integers, computing the two's complement truncated result,
835/// returning true if overflow occurred.
836template <typename T>
837std::enable_if_t<std::is_signed<T>::value, T> AddOverflow(T X, T Y, T &Result) {
838#if __has_builtin(__builtin_add_overflow)1
839  return __builtin_add_overflow(X, Y, &Result);
840#else
841  // Perform the unsigned addition.
842  using U = std::make_unsigned_t<T>;
843  const U UX = static_cast<U>(X);
844  const U UY = static_cast<U>(Y);
845  const U UResult = UX + UY;
846 
847  // Convert to signed.
848  Result = static_cast<T>(UResult);
849 
850  // Adding two positive numbers should result in a positive number.
851  if (X > 0 && Y > 0)
852    return Result <= 0;
853  // Adding two negatives should result in a negative number.
854  if (X < 0 && Y < 0)
855    return Result >= 0;
856  return false;
857#endif
858}
859 
860/// Subtract two signed integers, computing the two's complement truncated
861/// result, returning true if an overflow ocurred.
862template <typename T>
863std::enable_if_t<std::is_signed<T>::value, T> SubOverflow(T X, T Y, T &Result) {
864#if __has_builtin(__builtin_sub_overflow)1
865  return __builtin_sub_overflow(X, Y, &Result);
866#else
867  // Perform the unsigned addition.
868  using U = std::make_unsigned_t<T>;
869  const U UX = static_cast<U>(X);
870  const U UY = static_cast<U>(Y);
871  const U UResult = UX - UY;
872 
873  // Convert to signed.
874  Result = static_cast<T>(UResult);
875 
876  // Subtracting a positive number from a negative results in a negative number.
877  if (X <= 0 && Y > 0)
878    return Result >= 0;
879  // Subtracting a negative number from a positive results in a positive number.
880  if (X >= 0 && Y < 0)
881    return Result <= 0;
882  return false;
883#endif
884}
885 
886/// Multiply two signed integers, computing the two's complement truncated
887/// result, returning true if an overflow ocurred.
888template <typename T>
889std::enable_if_t<std::is_signed<T>::value, T> MulOverflow(T X, T Y, T &Result) {
890  // Perform the unsigned multiplication on absolute values.
891  using U = std::make_unsigned_t<T>;
892  const U UX = X < 0 ? (0 - static_cast<U>(X)) : static_cast<U>(X);
893  const U UY = Y < 0 ? (0 - static_cast<U>(Y)) : static_cast<U>(Y);
894  const U UResult = UX * UY;
895 
896  // Convert to signed.
897  const bool IsNegative = (X < 0) ^ (Y < 0);
898  Result = IsNegative ? (0 - UResult) : UResult;
899 
900  // If any of the args was 0, result is 0 and no overflow occurs.
901  if (UX == 0 || UY == 0)
902    return false;
903 
904  // UX and UY are in [1, 2^n], where n is the number of digits.
905  // Check how the max allowed absolute value (2^n for negative, 2^(n-1) for
906  // positive) divided by an argument compares to the other.
907  if (IsNegative)
908    return UX > (static_cast<U>(std::numeric_limits<T>::max()) + U(1)) / UY;
909  else
910    return UX > (static_cast<U>(std::numeric_limits<T>::max())) / UY;
911}
912 
913} // End llvm namespace
914 
915#endif

←

/usr/lib/gcc/x86_64-linux-gnu/10/../../../../include/c++/10/limits

1// The template and inlines for the numeric_limits classes. -*- C++ -*-

3// Copyright (C) 1999-2020 Free Software Foundation, Inc.
4//
5// This file is part of the GNU ISO C++ Library.  This library is free
6// software; you can redistribute it and/or modify it under the
7// terms of the GNU General Public License as published by the
8// Free Software Foundation; either version 3, or (at your option)
9// any later version.

11// This library is distributed in the hope that it will be useful,
12// but WITHOUT ANY WARRANTY; without even the implied warranty of
13// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14// GNU General Public License for more details.

16// Under Section 7 of GPL version 3, you are granted additional
17// permissions described in the GCC Runtime Library Exception, version
18// 3.1, as published by the Free Software Foundation.

20// You should have received a copy of the GNU General Public License and
21// a copy of the GCC Runtime Library Exception along with this program;
22// see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
23// <http://www.gnu.org/licenses/>.

25/** @file include/limits
*  This is a Standard C++ Library header.
*/

29// Note: this is not a conforming implementation.
30// Written by Gabriel Dos Reis <gdr@codesourcery.com>

32//
33// ISO 14882:1998
34// 18.2.1
35//

37#ifndef _GLIBCXX_NUMERIC_LIMITS1
38#define _GLIBCXX_NUMERIC_LIMITS1 1

40#pragma GCC system_header

42#include <bits/c++config.h>

44//
45// The numeric_limits<> traits document implementation-defined aspects
46// of fundamental arithmetic data types (integers and floating points).
47// From Standard C++ point of view, there are 14 such types:
48//   * integers
49//         bool							(1)
50//         char, signed char, unsigned char, wchar_t            (4)
51//         short, unsigned short				(2)
52//         int, unsigned					(2)
53//         long, unsigned long					(2)
54//
55//   * floating points
56//         float						(1)
57//         double						(1)
58//         long double						(1)
59//
60// GNU C++ understands (where supported by the host C-library)
61//   * integer
62//         long long, unsigned long long			(2)
63//
64// which brings us to 16 fundamental arithmetic data types in GNU C++.
65//
66//
67// Since a numeric_limits<> is a bit tricky to get right, we rely on
68// an interface composed of macros which should be defined in config/os
69// or config/cpu when they differ from the generic (read arbitrary)
70// definitions given here.
71//

73// These values can be overridden in the target configuration file.
74// The default values are appropriate for many 32-bit targets.

76// GCC only intrinsically supports modulo integral types.  The only remaining
77// integral exceptional values is division by zero.  Only targets that do not
78// signal division by zero in some "hard to ignore" way should use false.
79#ifndef __glibcxx_integral_trapstrue
80# define __glibcxx_integral_trapstrue true
81#endif

83// float
84//

86// Default values.  Should be overridden in configuration files if necessary.

88#ifndef __glibcxx_float_has_denorm_loss
89#  define __glibcxx_float_has_denorm_loss false
90#endif
91#ifndef __glibcxx_float_traps
92#  define __glibcxx_float_traps false
93#endif
94#ifndef __glibcxx_float_tinyness_before
95#  define __glibcxx_float_tinyness_before false
96#endif

98// double

100// Default values.  Should be overridden in configuration files if necessary.

102#ifndef __glibcxx_double_has_denorm_loss
103#  define __glibcxx_double_has_denorm_loss false
104#endif
105#ifndef __glibcxx_double_traps
106#  define __glibcxx_double_traps false
107#endif
108#ifndef __glibcxx_double_tinyness_before
109#  define __glibcxx_double_tinyness_before false
110#endif

112// long double

114// Default values.  Should be overridden in configuration files if necessary.

116#ifndef __glibcxx_long_double_has_denorm_loss
117#  define __glibcxx_long_double_has_denorm_loss false
118#endif
119#ifndef __glibcxx_long_double_traps
120#  define __glibcxx_long_double_traps false
121#endif
122#ifndef __glibcxx_long_double_tinyness_before
123#  define __glibcxx_long_double_tinyness_before false
124#endif

126// You should not need to define any macros below this point.

128#define __glibcxx_signed_b(T,B)((T)(-1) < 0)	((T)(-1) < 0)

130#define __glibcxx_min_b(T,B)(((T)(-1) < 0) ? -(((T)(-1) < 0) ? (((((T)1 << ((
B - ((T)(-1) < 0)) - 1)) - 1) << 1) + 1) : ~(T)0) - 1
 : (T)0)					\
(__glibcxx_signed_b (T,B)((T)(-1) < 0) ? -__glibcxx_max_b (T,B)(((T)(-1) < 0) ? (((((T)1 << ((B - ((T)(-1) < 0))
 - 1)) - 1) << 1) + 1) : ~(T)0) - 1 : (T)0)

133#define __glibcxx_max_b(T,B)(((T)(-1) < 0) ? (((((T)1 << ((B - ((T)(-1) < 0))
 - 1)) - 1) << 1) + 1) : ~(T)0)						\
(__glibcxx_signed_b (T,B)((T)(-1) < 0) ?						\
 (((((T)1 << (__glibcxx_digits_b (T,B)(B - ((T)(-1) < 0)) - 1)) - 1) << 1) + 1) : ~(T)0)

137#define __glibcxx_digits_b(T,B)(B - ((T)(-1) < 0))				\
(B - __glibcxx_signed_b (T,B)((T)(-1) < 0))

140// The fraction 643/2136 approximates log10(2) to 7 significant digits.
141#define __glibcxx_digits10_b(T,B)((B - ((T)(-1) < 0)) * 643L / 2136)		\
(__glibcxx_digits_b (T,B)(B - ((T)(-1) < 0)) * 643L / 2136)

144#define __glibcxx_signed(T) \
__glibcxx_signed_b (T, sizeof(T) * __CHAR_BIT__)((T)(-1) < 0)
146#define __glibcxx_min(T) \
__glibcxx_min_b (T, sizeof(T) * __CHAR_BIT__)(((T)(-1) < 0) ? -(((T)(-1) < 0) ? (((((T)1 << ((
sizeof(T) * 8 - ((T)(-1) < 0)) - 1)) - 1) << 1) + 1)
 : ~(T)0) - 1 : (T)0)
148#define __glibcxx_max(T) \
__glibcxx_max_b (T, sizeof(T) * __CHAR_BIT__)(((T)(-1) < 0) ? (((((T)1 << ((sizeof(T) * 8 - ((T)(
-1) < 0)) - 1)) - 1) << 1) + 1) : ~(T)0)
150#define __glibcxx_digits(T) \
__glibcxx_digits_b (T, sizeof(T) * __CHAR_BIT__)(sizeof(T) * 8 - ((T)(-1) < 0))
152#define __glibcxx_digits10(T) \
__glibcxx_digits10_b (T, sizeof(T) * __CHAR_BIT__)((sizeof(T) * 8 - ((T)(-1) < 0)) * 643L / 2136)

155#define __glibcxx_max_digits10(T) \
(2 + (T) * 643L / 2136)

158namespace std _GLIBCXX_VISIBILITY(default)__attribute__ ((__visibility__ ("default")))
159{
160_GLIBCXX_BEGIN_NAMESPACE_VERSION

/**
 *  @brief Describes the rounding style for floating-point types.
 *
 *  This is used in the std::numeric_limits class.
*/
enum float_round_style
{
  round_indeterminate       = -1,    /// Intermediate.
  round_toward_zero         = 0,     /// To zero.
  round_to_nearest          = 1,     /// To the nearest representable value.
  round_toward_infinity     = 2,     /// To infinity.
  round_toward_neg_infinity = 3      /// To negative infinity.
};

/**
 *  @brief Describes the denormalization for floating-point types.
 *
 *  These values represent the presence or absence of a variable number
 *  of exponent bits.  This type is used in the std::numeric_limits class.
*/
enum float_denorm_style
{
  /// Indeterminate at compile time whether denormalized values are allowed.
  denorm_indeterminate = -1,
  /// The type does not allow denormalized values.
  denorm_absent        = 0,
  /// The type allows denormalized values.
  denorm_present       = 1
};

/**
 *  @brief Part of std::numeric_limits.
 *
 *  The @c static @c const members are usable as integral constant
 *  expressions.
 *
 *  @note This is a separate class for purposes of efficiency; you
 *        should only access these members as part of an instantiation
 *        of the std::numeric_limits class.
*/
struct __numeric_limits_base
{
  /** This will be true for all fundamental types (which have
specializations), and false for everything else.  */
  static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_specialized = false;

  /** The number of @c radix digits that be represented without change:  for
integer types, the number of non-sign bits in the mantissa; for
floating types, the number of @c radix digits in the mantissa.  */
  static _GLIBCXX_USE_CONSTEXPRconstexpr int digits = 0;

  /** The number of base 10 digits that can be represented without change. */
  static _GLIBCXX_USE_CONSTEXPRconstexpr int digits10 = 0;

216#if __cplusplus201703L >= 201103L
  /** The number of base 10 digits required to ensure that values which
differ are always differentiated.  */
  static constexpr int max_digits10 = 0;
220#endif

  /** True if the type is signed.  */
  static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_signed = false;

  /** True if the type is integer.  */
  static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_integer = false;

  /** True if the type uses an exact representation. All integer types are
exact, but not all exact types are integer.  For example, rational and
fixed-exponent representations are exact but not integer. */
  static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_exact = false;

  /** For integer types, specifies the base of the representation.  For
floating types, specifies the base of the exponent representation.  */
  static _GLIBCXX_USE_CONSTEXPRconstexpr int radix = 0;

  /** The minimum negative integer such that @c radix raised to the power of
(one less than that integer) is a normalized floating point number.  */
  static _GLIBCXX_USE_CONSTEXPRconstexpr int min_exponent = 0;

  /** The minimum negative integer such that 10 raised to that power is in
the range of normalized floating point numbers.  */
  static _GLIBCXX_USE_CONSTEXPRconstexpr int min_exponent10 = 0;

  /** The maximum positive integer such that @c radix raised to the power of
(one less than that integer) is a representable finite floating point
number.  */
  static _GLIBCXX_USE_CONSTEXPRconstexpr int max_exponent = 0;

  /** The maximum positive integer such that 10 raised to that power is in
the range of representable finite floating point numbers.  */
  static _GLIBCXX_USE_CONSTEXPRconstexpr int max_exponent10 = 0;

  /** True if the type has a representation for positive infinity.  */
  static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_infinity = false;

  /** True if the type has a representation for a quiet (non-signaling)
Not a Number.  */
  static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_quiet_NaN = false;

  /** True if the type has a representation for a signaling
Not a Number.  */
  static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_signaling_NaN = false;

  /** See std::float_denorm_style for more information.  */
  static _GLIBCXX_USE_CONSTEXPRconstexpr float_denorm_style has_denorm = denorm_absent;

  /** True if loss of accuracy is detected as a denormalization loss,
rather than as an inexact result. */
  static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_denorm_loss = false;

  /** True if-and-only-if the type adheres to the IEC 559 standard, also
known as IEEE 754.  (Only makes sense for floating point types.)  */
  static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_iec559 = false;

  /** True if the set of values representable by the type is
finite.  All built-in types are bounded, this member would be
false for arbitrary precision types. */
  static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_bounded = false;

  /** True if the type is @e modulo. A type is modulo if, for any
operation involving +, -, or * on values of that type whose
result would fall outside the range [min(),max()], the value
returned differs from the true value by an integer multiple of
max() - min() + 1. On most machines, this is false for floating
types, true for unsigned integers, and true for signed integers.
See PR22200 about signed integers.  */
  static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_modulo = false;

  /** True if trapping is implemented for this type.  */
  static _GLIBCXX_USE_CONSTEXPRconstexpr bool traps = false;

  /** True if tininess is detected before rounding.  (see IEC 559)  */
  static _GLIBCXX_USE_CONSTEXPRconstexpr bool tinyness_before = false;

  /** See std::float_round_style for more information.  This is only
meaningful for floating types; integer types will all be
round_toward_zero.  */
  static _GLIBCXX_USE_CONSTEXPRconstexpr float_round_style round_style =
				    round_toward_zero;
};

/**
 *  @brief Properties of fundamental types.
 *
 *  This class allows a program to obtain information about the
 *  representation of a fundamental type on a given platform.  For
 *  non-fundamental types, the functions will return 0 and the data
 *  members will all be @c false.
*/
template<typename _Tp>
  struct numeric_limits : public __numeric_limits_base
  {
    /** The minimum finite value, or for floating types with
 denormalization, the minimum positive normalized value.  */
    static _GLIBCXX_CONSTEXPRconstexpr _Tp
    min() _GLIBCXX_USE_NOEXCEPTnoexcept { return _Tp(); }

    /** The maximum finite value.  */
    static _GLIBCXX_CONSTEXPRconstexpr _Tp
    max() _GLIBCXX_USE_NOEXCEPTnoexcept { return _Tp(); }

323#if __cplusplus201703L >= 201103L
    /** A finite value x such that there is no other finite value y
     *  where y < x.  */
    static constexpr _Tp
    lowest() noexcept { return _Tp(); }
328#endif

    /** The @e machine @e epsilon:  the difference between 1 and the least
 value greater than 1 that is representable.  */
    static _GLIBCXX_CONSTEXPRconstexpr _Tp
    epsilon() _GLIBCXX_USE_NOEXCEPTnoexcept { return _Tp(); }

    /** The maximum rounding error measurement (see LIA-1).  */
    static _GLIBCXX_CONSTEXPRconstexpr _Tp
    round_error() _GLIBCXX_USE_NOEXCEPTnoexcept { return _Tp(); }

    /** The representation of positive infinity, if @c has_infinity.  */
    static _GLIBCXX_CONSTEXPRconstexpr _Tp
    infinity() _GLIBCXX_USE_NOEXCEPTnoexcept { return _Tp(); }

    /** The representation of a quiet Not a Number,
 if @c has_quiet_NaN. */
    static _GLIBCXX_CONSTEXPRconstexpr _Tp
    quiet_NaN() _GLIBCXX_USE_NOEXCEPTnoexcept { return _Tp(); }

    /** The representation of a signaling Not a Number, if
 @c has_signaling_NaN. */
    static _GLIBCXX_CONSTEXPRconstexpr _Tp
    signaling_NaN() _GLIBCXX_USE_NOEXCEPTnoexcept { return _Tp(); }

    /** The minimum positive denormalized value.  For types where
 @c has_denorm is false, this is the minimum positive normalized
 value.  */
    static _GLIBCXX_CONSTEXPRconstexpr _Tp
    denorm_min() _GLIBCXX_USE_NOEXCEPTnoexcept { return _Tp(); }
  };

// _GLIBCXX_RESOLVE_LIB_DEFECTS
// 559. numeric_limits<const T>

template<typename _Tp>
  struct numeric_limits<const _Tp>
  : public numeric_limits<_Tp> { };

template<typename _Tp>
  struct numeric_limits<volatile _Tp>
  : public numeric_limits<_Tp> { };

template<typename _Tp>
  struct numeric_limits<const volatile _Tp>
  : public numeric_limits<_Tp> { };

// Now there follow 16 explicit specializations.  Yes, 16.  Make sure
// you get the count right. (18 in C++11 mode, with char16_t and char32_t.)
// (+1 if char8_t is enabled.)

// _GLIBCXX_RESOLVE_LIB_DEFECTS
// 184. numeric_limits<bool> wording problems

/// numeric_limits<bool> specialization.
template<>
  struct numeric_limits<bool>
  {
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_specialized = true;

    static _GLIBCXX_CONSTEXPRconstexpr bool
    min() _GLIBCXX_USE_NOEXCEPTnoexcept { return false; }

    static _GLIBCXX_CONSTEXPRconstexpr bool
    max() _GLIBCXX_USE_NOEXCEPTnoexcept { return true; }

394#if __cplusplus201703L >= 201103L
    static constexpr bool
    lowest() noexcept { return min(); }
397#endif
    static _GLIBCXX_USE_CONSTEXPRconstexpr int digits = 1;
    static _GLIBCXX_USE_CONSTEXPRconstexpr int digits10 = 0;
400#if __cplusplus201703L >= 201103L
    static constexpr int max_digits10 = 0;
402#endif
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_signed = false;
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_integer = true;
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_exact = true;
    static _GLIBCXX_USE_CONSTEXPRconstexpr int radix = 2;

    static _GLIBCXX_CONSTEXPRconstexpr bool
    epsilon() _GLIBCXX_USE_NOEXCEPTnoexcept { return false; }

    static _GLIBCXX_CONSTEXPRconstexpr bool
    round_error() _GLIBCXX_USE_NOEXCEPTnoexcept { return false; }

    static _GLIBCXX_USE_CONSTEXPRconstexpr int min_exponent = 0;
    static _GLIBCXX_USE_CONSTEXPRconstexpr int min_exponent10 = 0;
    static _GLIBCXX_USE_CONSTEXPRconstexpr int max_exponent = 0;
    static _GLIBCXX_USE_CONSTEXPRconstexpr int max_exponent10 = 0;

    static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_infinity = false;
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_quiet_NaN = false;
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_signaling_NaN = false;
    static _GLIBCXX_USE_CONSTEXPRconstexpr float_denorm_style has_denorm
     = denorm_absent;
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_denorm_loss = false;

    static _GLIBCXX_CONSTEXPRconstexpr bool
    infinity() _GLIBCXX_USE_NOEXCEPTnoexcept { return false; }

    static _GLIBCXX_CONSTEXPRconstexpr bool
    quiet_NaN() _GLIBCXX_USE_NOEXCEPTnoexcept { return false; }

    static _GLIBCXX_CONSTEXPRconstexpr bool
    signaling_NaN() _GLIBCXX_USE_NOEXCEPTnoexcept { return false; }

    static _GLIBCXX_CONSTEXPRconstexpr bool
    denorm_min() _GLIBCXX_USE_NOEXCEPTnoexcept { return false; }

    static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_iec559 = false;
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_bounded = true;
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_modulo = false;

    // It is not clear what it means for a boolean type to trap.
    // This is a DR on the LWG issue list.  Here, I use integer
    // promotion semantics.
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool traps = __glibcxx_integral_trapstrue;
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool tinyness_before = false;
    static _GLIBCXX_USE_CONSTEXPRconstexpr float_round_style round_style
     = round_toward_zero;
  };

/// numeric_limits<char> specialization.
template<>
  struct numeric_limits<char>
  {
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_specialized = true;

    static _GLIBCXX_CONSTEXPRconstexpr char
    min() _GLIBCXX_USE_NOEXCEPTnoexcept { return __glibcxx_min(char); }

    static _GLIBCXX_CONSTEXPRconstexpr char
    max() _GLIBCXX_USE_NOEXCEPTnoexcept { return __glibcxx_max(char); }

463#if __cplusplus201703L >= 201103L
    static constexpr char
    lowest() noexcept { return min(); }
466#endif

    static _GLIBCXX_USE_CONSTEXPRconstexpr int digits = __glibcxx_digits (char);
    static _GLIBCXX_USE_CONSTEXPRconstexpr int digits10 = __glibcxx_digits10 (char);
470#if __cplusplus201703L >= 201103L
    static constexpr int max_digits10 = 0;
472#endif
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_signed = __glibcxx_signed (char);
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_integer = true;
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_exact = true;
    static _GLIBCXX_USE_CONSTEXPRconstexpr int radix = 2;

    static _GLIBCXX_CONSTEXPRconstexpr char
    epsilon() _GLIBCXX_USE_NOEXCEPTnoexcept { return 0; }

    static _GLIBCXX_CONSTEXPRconstexpr char
    round_error() _GLIBCXX_USE_NOEXCEPTnoexcept { return 0; }

    static _GLIBCXX_USE_CONSTEXPRconstexpr int min_exponent = 0;
    static _GLIBCXX_USE_CONSTEXPRconstexpr int min_exponent10 = 0;
    static _GLIBCXX_USE_CONSTEXPRconstexpr int max_exponent = 0;
    static _GLIBCXX_USE_CONSTEXPRconstexpr int max_exponent10 = 0;

    static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_infinity = false;
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_quiet_NaN = false;
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_signaling_NaN = false;
    static _GLIBCXX_USE_CONSTEXPRconstexpr float_denorm_style has_denorm
     = denorm_absent;
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_denorm_loss = false;

    static _GLIBCXX_CONSTEXPRconstexpr
    char infinity() _GLIBCXX_USE_NOEXCEPTnoexcept { return char(); }

    static _GLIBCXX_CONSTEXPRconstexpr char
    quiet_NaN() _GLIBCXX_USE_NOEXCEPTnoexcept { return char(); }

    static _GLIBCXX_CONSTEXPRconstexpr char
    signaling_NaN() _GLIBCXX_USE_NOEXCEPTnoexcept { return char(); }

    static _GLIBCXX_CONSTEXPRconstexpr char
    denorm_min() _GLIBCXX_USE_NOEXCEPTnoexcept { return static_cast<char>(0); }

    static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_iec559 = false;
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_bounded = true;
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_modulo = !is_signed;

    static _GLIBCXX_USE_CONSTEXPRconstexpr bool traps = __glibcxx_integral_trapstrue;
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool tinyness_before = false;
    static _GLIBCXX_USE_CONSTEXPRconstexpr float_round_style round_style
     = round_toward_zero;
  };

/// numeric_limits<signed char> specialization.
template<>
  struct numeric_limits<signed char>
  {
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_specialized = true;

    static _GLIBCXX_CONSTEXPRconstexpr signed char
    min() _GLIBCXX_USE_NOEXCEPTnoexcept { return -__SCHAR_MAX__127 - 1; }

    static _GLIBCXX_CONSTEXPRconstexpr signed char
    max() _GLIBCXX_USE_NOEXCEPTnoexcept { return __SCHAR_MAX__127; }

530#if __cplusplus201703L >= 201103L
    static constexpr signed char
    lowest() noexcept { return min(); }
533#endif

    static _GLIBCXX_USE_CONSTEXPRconstexpr int digits = __glibcxx_digits (signed char);
    static _GLIBCXX_USE_CONSTEXPRconstexpr int digits10
     = __glibcxx_digits10 (signed char);
538#if __cplusplus201703L >= 201103L
    static constexpr int max_digits10 = 0;
540#endif
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_signed = true;
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_integer = true;
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_exact = true;
    static _GLIBCXX_USE_CONSTEXPRconstexpr int radix = 2;

    static _GLIBCXX_CONSTEXPRconstexpr signed char
    epsilon() _GLIBCXX_USE_NOEXCEPTnoexcept { return 0; }

    static _GLIBCXX_CONSTEXPRconstexpr signed char
    round_error() _GLIBCXX_USE_NOEXCEPTnoexcept { return 0; }

    static _GLIBCXX_USE_CONSTEXPRconstexpr int min_exponent = 0;
    static _GLIBCXX_USE_CONSTEXPRconstexpr int min_exponent10 = 0;
    static _GLIBCXX_USE_CONSTEXPRconstexpr int max_exponent = 0;
    static _GLIBCXX_USE_CONSTEXPRconstexpr int max_exponent10 = 0;

    static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_infinity = false;
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_quiet_NaN = false;
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_signaling_NaN = false;
    static _GLIBCXX_USE_CONSTEXPRconstexpr float_denorm_style has_denorm
     = denorm_absent;
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_denorm_loss = false;

    static _GLIBCXX_CONSTEXPRconstexpr signed char
    infinity() _GLIBCXX_USE_NOEXCEPTnoexcept { return static_cast<signed char>(0); }

    static _GLIBCXX_CONSTEXPRconstexpr signed char
    quiet_NaN() _GLIBCXX_USE_NOEXCEPTnoexcept { return static_cast<signed char>(0); }

    static _GLIBCXX_CONSTEXPRconstexpr signed char
    signaling_NaN() _GLIBCXX_USE_NOEXCEPTnoexcept
    { return static_cast<signed char>(0); }

    static _GLIBCXX_CONSTEXPRconstexpr signed char
    denorm_min() _GLIBCXX_USE_NOEXCEPTnoexcept
    { return static_cast<signed char>(0); }

    static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_iec559 = false;
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_bounded = true;
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_modulo = false;

    static _GLIBCXX_USE_CONSTEXPRconstexpr bool traps = __glibcxx_integral_trapstrue;
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool tinyness_before = false;
    static _GLIBCXX_USE_CONSTEXPRconstexpr float_round_style round_style
     = round_toward_zero;
  };

/// numeric_limits<unsigned char> specialization.
template<>
  struct numeric_limits<unsigned char>
  {
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_specialized = true;

    static _GLIBCXX_CONSTEXPRconstexpr unsigned char
    min() _GLIBCXX_USE_NOEXCEPTnoexcept { return 0; }

    static _GLIBCXX_CONSTEXPRconstexpr unsigned char
    max() _GLIBCXX_USE_NOEXCEPTnoexcept { return __SCHAR_MAX__127 * 2U + 1; }

600#if __cplusplus201703L >= 201103L
    static constexpr unsigned char
    lowest() noexcept { return min(); }
603#endif

    static _GLIBCXX_USE_CONSTEXPRconstexpr int digits
     = __glibcxx_digits (unsigned char);
    static _GLIBCXX_USE_CONSTEXPRconstexpr int digits10
     = __glibcxx_digits10 (unsigned char);
609#if __cplusplus201703L >= 201103L
    static constexpr int max_digits10 = 0;
611#endif
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_signed = false;
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_integer = true;
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_exact = true;
    static _GLIBCXX_USE_CONSTEXPRconstexpr int radix = 2;

    static _GLIBCXX_CONSTEXPRconstexpr unsigned char
    epsilon() _GLIBCXX_USE_NOEXCEPTnoexcept { return 0; }

    static _GLIBCXX_CONSTEXPRconstexpr unsigned char
    round_error() _GLIBCXX_USE_NOEXCEPTnoexcept { return 0; }

    static _GLIBCXX_USE_CONSTEXPRconstexpr int min_exponent = 0;
    static _GLIBCXX_USE_CONSTEXPRconstexpr int min_exponent10 = 0;
    static _GLIBCXX_USE_CONSTEXPRconstexpr int max_exponent = 0;
    static _GLIBCXX_USE_CONSTEXPRconstexpr int max_exponent10 = 0;

    static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_infinity = false;
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_quiet_NaN = false;
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_signaling_NaN = false;
    static _GLIBCXX_USE_CONSTEXPRconstexpr float_denorm_style has_denorm
     = denorm_absent;
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_denorm_loss = false;

    static _GLIBCXX_CONSTEXPRconstexpr unsigned char
    infinity() _GLIBCXX_USE_NOEXCEPTnoexcept
    { return static_cast<unsigned char>(0); }

    static _GLIBCXX_CONSTEXPRconstexpr unsigned char
    quiet_NaN() _GLIBCXX_USE_NOEXCEPTnoexcept
    { return static_cast<unsigned char>(0); }

    static _GLIBCXX_CONSTEXPRconstexpr unsigned char
    signaling_NaN() _GLIBCXX_USE_NOEXCEPTnoexcept
    { return static_cast<unsigned char>(0); }

    static _GLIBCXX_CONSTEXPRconstexpr unsigned char
    denorm_min() _GLIBCXX_USE_NOEXCEPTnoexcept
    { return static_cast<unsigned char>(0); }

    static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_iec559 = false;
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_bounded = true;
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_modulo = true;

    static _GLIBCXX_USE_CONSTEXPRconstexpr bool traps = __glibcxx_integral_trapstrue;
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool tinyness_before = false;
    static _GLIBCXX_USE_CONSTEXPRconstexpr float_round_style round_style
     = round_toward_zero;
  };

/// numeric_limits<wchar_t> specialization.
template<>
  struct numeric_limits<wchar_t>
  {
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_specialized = true;

    static _GLIBCXX_CONSTEXPRconstexpr wchar_t
    min() _GLIBCXX_USE_NOEXCEPTnoexcept { return __glibcxx_min (wchar_t); }

    static _GLIBCXX_CONSTEXPRconstexpr wchar_t
    max() _GLIBCXX_USE_NOEXCEPTnoexcept { return __glibcxx_max (wchar_t); }

673#if __cplusplus201703L >= 201103L
    static constexpr wchar_t
    lowest() noexcept { return min(); }
676#endif

    static _GLIBCXX_USE_CONSTEXPRconstexpr int digits = __glibcxx_digits (wchar_t);
    static _GLIBCXX_USE_CONSTEXPRconstexpr int digits10
     = __glibcxx_digits10 (wchar_t);
681#if __cplusplus201703L >= 201103L
    static constexpr int max_digits10 = 0;
683#endif
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_signed = __glibcxx_signed (wchar_t);
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_integer = true;
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_exact = true;
    static _GLIBCXX_USE_CONSTEXPRconstexpr int radix = 2;

    static _GLIBCXX_CONSTEXPRconstexpr wchar_t
    epsilon() _GLIBCXX_USE_NOEXCEPTnoexcept { return 0; }

    static _GLIBCXX_CONSTEXPRconstexpr wchar_t
    round_error() _GLIBCXX_USE_NOEXCEPTnoexcept { return 0; }

    static _GLIBCXX_USE_CONSTEXPRconstexpr int min_exponent = 0;
    static _GLIBCXX_USE_CONSTEXPRconstexpr int min_exponent10 = 0;
    static _GLIBCXX_USE_CONSTEXPRconstexpr int max_exponent = 0;
    static _GLIBCXX_USE_CONSTEXPRconstexpr int max_exponent10 = 0;

    static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_infinity = false;
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_quiet_NaN = false;
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_signaling_NaN = false;
    static _GLIBCXX_USE_CONSTEXPRconstexpr float_denorm_style has_denorm
     = denorm_absent;
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_denorm_loss = false;

    static _GLIBCXX_CONSTEXPRconstexpr wchar_t
    infinity() _GLIBCXX_USE_NOEXCEPTnoexcept { return wchar_t(); }

    static _GLIBCXX_CONSTEXPRconstexpr wchar_t
    quiet_NaN() _GLIBCXX_USE_NOEXCEPTnoexcept { return wchar_t(); }

    static _GLIBCXX_CONSTEXPRconstexpr wchar_t
    signaling_NaN() _GLIBCXX_USE_NOEXCEPTnoexcept { return wchar_t(); }

    static _GLIBCXX_CONSTEXPRconstexpr wchar_t
    denorm_min() _GLIBCXX_USE_NOEXCEPTnoexcept { return wchar_t(); }

    static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_iec559 = false;
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_bounded = true;
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_modulo = !is_signed;

    static _GLIBCXX_USE_CONSTEXPRconstexpr bool traps = __glibcxx_integral_trapstrue;
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool tinyness_before = false;
    static _GLIBCXX_USE_CONSTEXPRconstexpr float_round_style round_style
     = round_toward_zero;
  };

729#if _GLIBCXX_USE_CHAR8_T
/// numeric_limits<char8_t> specialization.
template<>
  struct numeric_limits<char8_t>
  {
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_specialized = true;

    static _GLIBCXX_CONSTEXPRconstexpr char8_t
    min() _GLIBCXX_USE_NOEXCEPTnoexcept { return __glibcxx_min (char8_t); }

    static _GLIBCXX_CONSTEXPRconstexpr char8_t
    max() _GLIBCXX_USE_NOEXCEPTnoexcept { return __glibcxx_max (char8_t); }

    static _GLIBCXX_CONSTEXPRconstexpr char8_t
    lowest() _GLIBCXX_USE_NOEXCEPTnoexcept { return min(); }

    static _GLIBCXX_USE_CONSTEXPRconstexpr int digits = __glibcxx_digits (char8_t);
    static _GLIBCXX_USE_CONSTEXPRconstexpr int digits10 = __glibcxx_digits10 (char8_t);
    static _GLIBCXX_USE_CONSTEXPRconstexpr int max_digits10 = 0;
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_signed = __glibcxx_signed (char8_t);
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_integer = true;
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_exact = true;
    static _GLIBCXX_USE_CONSTEXPRconstexpr int radix = 2;

    static _GLIBCXX_CONSTEXPRconstexpr char8_t
    epsilon() _GLIBCXX_USE_NOEXCEPTnoexcept { return 0; }

    static _GLIBCXX_CONSTEXPRconstexpr char8_t
    round_error() _GLIBCXX_USE_NOEXCEPTnoexcept { return 0; }

    static _GLIBCXX_USE_CONSTEXPRconstexpr int min_exponent = 0;
    static _GLIBCXX_USE_CONSTEXPRconstexpr int min_exponent10 = 0;
    static _GLIBCXX_USE_CONSTEXPRconstexpr int max_exponent = 0;
    static _GLIBCXX_USE_CONSTEXPRconstexpr int max_exponent10 = 0;

    static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_infinity = false;
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_quiet_NaN = false;
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_signaling_NaN = false;
    static _GLIBCXX_USE_CONSTEXPRconstexpr float_denorm_style has_denorm
= denorm_absent;
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_denorm_loss = false;

    static _GLIBCXX_CONSTEXPRconstexpr char8_t
    infinity() _GLIBCXX_USE_NOEXCEPTnoexcept { return char8_t(); }

    static _GLIBCXX_CONSTEXPRconstexpr char8_t
    quiet_NaN() _GLIBCXX_USE_NOEXCEPTnoexcept { return char8_t(); }

    static _GLIBCXX_CONSTEXPRconstexpr char8_t
    signaling_NaN() _GLIBCXX_USE_NOEXCEPTnoexcept { return char8_t(); }

    static _GLIBCXX_CONSTEXPRconstexpr char8_t
    denorm_min() _GLIBCXX_USE_NOEXCEPTnoexcept { return char8_t(); }

    static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_iec559 = false;
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_bounded = true;
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_modulo = !is_signed;

    static _GLIBCXX_USE_CONSTEXPRconstexpr bool traps = __glibcxx_integral_trapstrue;
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool tinyness_before = false;
    static _GLIBCXX_USE_CONSTEXPRconstexpr float_round_style round_style
= round_toward_zero;
  };
792#endif

794#if __cplusplus201703L >= 201103L
/// numeric_limits<char16_t> specialization.
template<>
  struct numeric_limits<char16_t>
  {
    static constexpr bool is_specialized = true;

    static constexpr char16_t
    min() noexcept { return __glibcxx_min (char16_t); }

    static constexpr char16_t
    max() noexcept { return __glibcxx_max (char16_t); }

    static constexpr char16_t
    lowest() noexcept { return min(); }

    static constexpr int digits = __glibcxx_digits (char16_t);
    static constexpr int digits10 = __glibcxx_digits10 (char16_t);
    static constexpr int max_digits10 = 0;
    static constexpr bool is_signed = __glibcxx_signed (char16_t);
    static constexpr bool is_integer = true;
    static constexpr bool is_exact = true;
    static constexpr int radix = 2;

    static constexpr char16_t
    epsilon() noexcept { return 0; }

    static constexpr char16_t
    round_error() noexcept { return 0; }

    static constexpr int min_exponent = 0;
    static constexpr int min_exponent10 = 0;
    static constexpr int max_exponent = 0;
    static constexpr int max_exponent10 = 0;

    static constexpr bool has_infinity = false;
    static constexpr bool has_quiet_NaN = false;
    static constexpr bool has_signaling_NaN = false;
    static constexpr float_denorm_style has_denorm = denorm_absent;
    static constexpr bool has_denorm_loss = false;

    static constexpr char16_t
    infinity() noexcept { return char16_t(); }

    static constexpr char16_t
    quiet_NaN() noexcept { return char16_t(); }

    static constexpr char16_t
    signaling_NaN() noexcept { return char16_t(); }

    static constexpr char16_t
    denorm_min() noexcept { return char16_t(); }

    static constexpr bool is_iec559 = false;
    static constexpr bool is_bounded = true;
    static constexpr bool is_modulo = !is_signed;

    static constexpr bool traps = __glibcxx_integral_trapstrue;
    static constexpr bool tinyness_before = false;
    static constexpr float_round_style round_style = round_toward_zero;
  };

/// numeric_limits<char32_t> specialization.
template<>
  struct numeric_limits<char32_t>
  {
    static constexpr bool is_specialized = true;

    static constexpr char32_t
    min() noexcept { return __glibcxx_min (char32_t); }

    static constexpr char32_t
    max() noexcept { return __glibcxx_max (char32_t); }

    static constexpr char32_t
    lowest() noexcept { return min(); }

    static constexpr int digits = __glibcxx_digits (char32_t);
    static constexpr int digits10 = __glibcxx_digits10 (char32_t);
    static constexpr int max_digits10 = 0;
    static constexpr bool is_signed = __glibcxx_signed (char32_t);
    static constexpr bool is_integer = true;
    static constexpr bool is_exact = true;
    static constexpr int radix = 2;

    static constexpr char32_t
    epsilon() noexcept { return 0; }

    static constexpr char32_t
    round_error() noexcept { return 0; }

    static constexpr int min_exponent = 0;
    static constexpr int min_exponent10 = 0;
    static constexpr int max_exponent = 0;
    static constexpr int max_exponent10 = 0;

    static constexpr bool has_infinity = false;
    static constexpr bool has_quiet_NaN = false;
    static constexpr bool has_signaling_NaN = false;
    static constexpr float_denorm_style has_denorm = denorm_absent;
    static constexpr bool has_denorm_loss = false;

    static constexpr char32_t
    infinity() noexcept { return char32_t(); }

    static constexpr char32_t
    quiet_NaN() noexcept { return char32_t(); }

    static constexpr char32_t
    signaling_NaN() noexcept { return char32_t(); }

    static constexpr char32_t
    denorm_min() noexcept { return char32_t(); }

    static constexpr bool is_iec559 = false;
    static constexpr bool is_bounded = true;
    static constexpr bool is_modulo = !is_signed;

    static constexpr bool traps = __glibcxx_integral_trapstrue;
    static constexpr bool tinyness_before = false;
    static constexpr float_round_style round_style = round_toward_zero;
  };
916#endif

/// numeric_limits<short> specialization.
template<>
  struct numeric_limits<short>
  {
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_specialized = true;

    static _GLIBCXX_CONSTEXPRconstexpr short
    min() _GLIBCXX_USE_NOEXCEPTnoexcept { return -__SHRT_MAX__32767 - 1; }

    static _GLIBCXX_CONSTEXPRconstexpr short
    max() _GLIBCXX_USE_NOEXCEPTnoexcept { return __SHRT_MAX__32767; }

930#if __cplusplus201703L >= 201103L
    static constexpr short
    lowest() noexcept { return min(); }
933#endif

    static _GLIBCXX_USE_CONSTEXPRconstexpr int digits = __glibcxx_digits (short);
    static _GLIBCXX_USE_CONSTEXPRconstexpr int digits10 = __glibcxx_digits10 (short);
937#if __cplusplus201703L >= 201103L
    static constexpr int max_digits10 = 0;
939#endif
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_signed = true;
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_integer = true;
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_exact = true;
    static _GLIBCXX_USE_CONSTEXPRconstexpr int radix = 2;

    static _GLIBCXX_CONSTEXPRconstexpr short
    epsilon() _GLIBCXX_USE_NOEXCEPTnoexcept { return 0; }

    static _GLIBCXX_CONSTEXPRconstexpr short
    round_error() _GLIBCXX_USE_NOEXCEPTnoexcept { return 0; }

    static _GLIBCXX_USE_CONSTEXPRconstexpr int min_exponent = 0;
    static _GLIBCXX_USE_CONSTEXPRconstexpr int min_exponent10 = 0;
    static _GLIBCXX_USE_CONSTEXPRconstexpr int max_exponent = 0;
    static _GLIBCXX_USE_CONSTEXPRconstexpr int max_exponent10 = 0;

    static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_infinity = false;
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_quiet_NaN = false;
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_signaling_NaN = false;
    static _GLIBCXX_USE_CONSTEXPRconstexpr float_denorm_style has_denorm
     = denorm_absent;
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_denorm_loss = false;

    static _GLIBCXX_CONSTEXPRconstexpr short
    infinity() _GLIBCXX_USE_NOEXCEPTnoexcept { return short(); }

    static _GLIBCXX_CONSTEXPRconstexpr short
    quiet_NaN() _GLIBCXX_USE_NOEXCEPTnoexcept { return short(); }

    static _GLIBCXX_CONSTEXPRconstexpr short
    signaling_NaN() _GLIBCXX_USE_NOEXCEPTnoexcept { return short(); }

    static _GLIBCXX_CONSTEXPRconstexpr short
    denorm_min() _GLIBCXX_USE_NOEXCEPTnoexcept { return short(); }

    static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_iec559 = false;
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_bounded = true;
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_modulo = false;

    static _GLIBCXX_USE_CONSTEXPRconstexpr bool traps = __glibcxx_integral_trapstrue;
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool tinyness_before = false;
    static _GLIBCXX_USE_CONSTEXPRconstexpr float_round_style round_style
     = round_toward_zero;
  };

/// numeric_limits<unsigned short> specialization.
template<>
  struct numeric_limits<unsigned short>
  {
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_specialized = true;

    static _GLIBCXX_CONSTEXPRconstexpr unsigned short
    min() _GLIBCXX_USE_NOEXCEPTnoexcept { return 0; }

    static _GLIBCXX_CONSTEXPRconstexpr unsigned short
    max() _GLIBCXX_USE_NOEXCEPTnoexcept { return __SHRT_MAX__32767 * 2U + 1; }

997#if __cplusplus201703L >= 201103L
    static constexpr unsigned short
    lowest() noexcept { return min(); }
1000#endif

    static _GLIBCXX_USE_CONSTEXPRconstexpr int digits
     = __glibcxx_digits (unsigned short);
    static _GLIBCXX_USE_CONSTEXPRconstexpr int digits10
     = __glibcxx_digits10 (unsigned short);
1006#if __cplusplus201703L >= 201103L
    static constexpr int max_digits10 = 0;
1008#endif
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_signed = false;
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_integer = true;
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_exact = true;
    static _GLIBCXX_USE_CONSTEXPRconstexpr int radix = 2;

    static _GLIBCXX_CONSTEXPRconstexpr unsigned short
    epsilon() _GLIBCXX_USE_NOEXCEPTnoexcept { return 0; }

    static _GLIBCXX_CONSTEXPRconstexpr unsigned short
    round_error() _GLIBCXX_USE_NOEXCEPTnoexcept { return 0; }

    static _GLIBCXX_USE_CONSTEXPRconstexpr int min_exponent = 0;
    static _GLIBCXX_USE_CONSTEXPRconstexpr int min_exponent10 = 0;
    static _GLIBCXX_USE_CONSTEXPRconstexpr int max_exponent = 0;
    static _GLIBCXX_USE_CONSTEXPRconstexpr int max_exponent10 = 0;

    static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_infinity = false;
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_quiet_NaN = false;
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_signaling_NaN = false;
    static _GLIBCXX_USE_CONSTEXPRconstexpr float_denorm_style has_denorm
     = denorm_absent;
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_denorm_loss = false;

    static _GLIBCXX_CONSTEXPRconstexpr unsigned short
    infinity() _GLIBCXX_USE_NOEXCEPTnoexcept
    { return static_cast<unsigned short>(0); }

    static _GLIBCXX_CONSTEXPRconstexpr unsigned short
    quiet_NaN() _GLIBCXX_USE_NOEXCEPTnoexcept
    { return static_cast<unsigned short>(0); }

    static _GLIBCXX_CONSTEXPRconstexpr unsigned short
    signaling_NaN() _GLIBCXX_USE_NOEXCEPTnoexcept
    { return static_cast<unsigned short>(0); }

    static _GLIBCXX_CONSTEXPRconstexpr unsigned short
    denorm_min() _GLIBCXX_USE_NOEXCEPTnoexcept
    { return static_cast<unsigned short>(0); }

    static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_iec559 = false;
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_bounded = true;
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_modulo = true;

    static _GLIBCXX_USE_CONSTEXPRconstexpr bool traps = __glibcxx_integral_trapstrue;
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool tinyness_before = false;
    static _GLIBCXX_USE_CONSTEXPRconstexpr float_round_style round_style
     = round_toward_zero;
  };

/// numeric_limits<int> specialization.
template<>
  struct numeric_limits<int>
  {
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_specialized = true;

    static _GLIBCXX_CONSTEXPRconstexpr int
    min() _GLIBCXX_USE_NOEXCEPTnoexcept { return -__INT_MAX__2147483647 - 1; }

    static _GLIBCXX_CONSTEXPRconstexpr int
    max() _GLIBCXX_USE_NOEXCEPTnoexcept { return __INT_MAX__2147483647; }

1070#if __cplusplus201703L >= 201103L
    static constexpr int
    lowest() noexcept { return min(); }
1073#endif

    static _GLIBCXX_USE_CONSTEXPRconstexpr int digits = __glibcxx_digits (int);
    static _GLIBCXX_USE_CONSTEXPRconstexpr int digits10 = __glibcxx_digits10 (int);
1077#if __cplusplus201703L >= 201103L
    static constexpr int max_digits10 = 0;
1079#endif
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_signed = true;
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_integer = true;
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_exact = true;
    static _GLIBCXX_USE_CONSTEXPRconstexpr int radix = 2;

    static _GLIBCXX_CONSTEXPRconstexpr int
    epsilon() _GLIBCXX_USE_NOEXCEPTnoexcept { return 0; }

    static _GLIBCXX_CONSTEXPRconstexpr int
    round_error() _GLIBCXX_USE_NOEXCEPTnoexcept { return 0; }

    static _GLIBCXX_USE_CONSTEXPRconstexpr int min_exponent = 0;
    static _GLIBCXX_USE_CONSTEXPRconstexpr int min_exponent10 = 0;
    static _GLIBCXX_USE_CONSTEXPRconstexpr int max_exponent = 0;
    static _GLIBCXX_USE_CONSTEXPRconstexpr int max_exponent10 = 0;

    static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_infinity = false;
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_quiet_NaN = false;
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_signaling_NaN = false;
    static _GLIBCXX_USE_CONSTEXPRconstexpr float_denorm_style has_denorm
     = denorm_absent;
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_denorm_loss = false;

    static _GLIBCXX_CONSTEXPRconstexpr int
    infinity() _GLIBCXX_USE_NOEXCEPTnoexcept { return static_cast<int>(0); }

    static _GLIBCXX_CONSTEXPRconstexpr int
    quiet_NaN() _GLIBCXX_USE_NOEXCEPTnoexcept { return static_cast<int>(0); }

    static _GLIBCXX_CONSTEXPRconstexpr int
    signaling_NaN() _GLIBCXX_USE_NOEXCEPTnoexcept { return static_cast<int>(0); }

    static _GLIBCXX_CONSTEXPRconstexpr int
    denorm_min() _GLIBCXX_USE_NOEXCEPTnoexcept { return static_cast<int>(0); }

    static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_iec559 = false;
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_bounded = true;
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_modulo = false;

    static _GLIBCXX_USE_CONSTEXPRconstexpr bool traps = __glibcxx_integral_trapstrue;
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool tinyness_before = false;
    static _GLIBCXX_USE_CONSTEXPRconstexpr float_round_style round_style
     = round_toward_zero;
  };

/// numeric_limits<unsigned int> specialization.
template<>
  struct numeric_limits<unsigned int>
  {
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_specialized = true;

    static _GLIBCXX_CONSTEXPRconstexpr unsigned int
    min() _GLIBCXX_USE_NOEXCEPTnoexcept { return 0; }

    static _GLIBCXX_CONSTEXPRconstexpr unsigned int
    max() _GLIBCXX_USE_NOEXCEPTnoexcept { return __INT_MAX__2147483647 * 2U + 1; }

1137#if __cplusplus201703L >= 201103L
    static constexpr unsigned int
    lowest() noexcept { return min(); }
1140#endif

    static _GLIBCXX_USE_CONSTEXPRconstexpr int digits
     = __glibcxx_digits (unsigned int);
    static _GLIBCXX_USE_CONSTEXPRconstexpr int digits10
     = __glibcxx_digits10 (unsigned int);
1146#if __cplusplus201703L >= 201103L
    static constexpr int max_digits10 = 0;
1148#endif
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_signed = false;
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_integer = true;
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_exact = true;
    static _GLIBCXX_USE_CONSTEXPRconstexpr int radix = 2;

    static _GLIBCXX_CONSTEXPRconstexpr unsigned int
    epsilon() _GLIBCXX_USE_NOEXCEPTnoexcept { return 0; }

    static _GLIBCXX_CONSTEXPRconstexpr unsigned int
    round_error() _GLIBCXX_USE_NOEXCEPTnoexcept { return 0; }

    static _GLIBCXX_USE_CONSTEXPRconstexpr int min_exponent = 0;
    static _GLIBCXX_USE_CONSTEXPRconstexpr int min_exponent10 = 0;
    static _GLIBCXX_USE_CONSTEXPRconstexpr int max_exponent = 0;
    static _GLIBCXX_USE_CONSTEXPRconstexpr int max_exponent10 = 0;

    static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_infinity = false;
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_quiet_NaN = false;
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_signaling_NaN = false;
    static _GLIBCXX_USE_CONSTEXPRconstexpr float_denorm_style has_denorm
     = denorm_absent;
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_denorm_loss = false;

    static _GLIBCXX_CONSTEXPRconstexpr unsigned int
    infinity() _GLIBCXX_USE_NOEXCEPTnoexcept { return static_cast<unsigned int>(0); }

    static _GLIBCXX_CONSTEXPRconstexpr unsigned int
    quiet_NaN() _GLIBCXX_USE_NOEXCEPTnoexcept
    { return static_cast<unsigned int>(0); }

    static _GLIBCXX_CONSTEXPRconstexpr unsigned int
    signaling_NaN() _GLIBCXX_USE_NOEXCEPTnoexcept
    { return static_cast<unsigned int>(0); }

    static _GLIBCXX_CONSTEXPRconstexpr unsigned int
    denorm_min() _GLIBCXX_USE_NOEXCEPTnoexcept
    { return static_cast<unsigned int>(0); }

    static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_iec559 = false;
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_bounded = true;
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_modulo = true;

    static _GLIBCXX_USE_CONSTEXPRconstexpr bool traps = __glibcxx_integral_trapstrue;
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool tinyness_before = false;
    static _GLIBCXX_USE_CONSTEXPRconstexpr float_round_style round_style
     = round_toward_zero;
  };

/// numeric_limits<long> specialization.
template<>
  struct numeric_limits<long>
  {
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_specialized = true;

    static _GLIBCXX_CONSTEXPRconstexpr long
    min() _GLIBCXX_USE_NOEXCEPTnoexcept { return -__LONG_MAX__9223372036854775807L - 1; }

    static _GLIBCXX_CONSTEXPRconstexpr long
    max() _GLIBCXX_USE_NOEXCEPTnoexcept { return __LONG_MAX__9223372036854775807L; }

1209#if __cplusplus201703L >= 201103L
    static constexpr long
    lowest() noexcept { return min(); }
1212#endif

    static _GLIBCXX_USE_CONSTEXPRconstexpr int digits = __glibcxx_digits (long);
    static _GLIBCXX_USE_CONSTEXPRconstexpr int digits10 = __glibcxx_digits10 (long);
1216#if __cplusplus201703L >= 201103L
    static constexpr int max_digits10 = 0;
1218#endif
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_signed = true;
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_integer = true;
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_exact = true;
    static _GLIBCXX_USE_CONSTEXPRconstexpr int radix = 2;

    static _GLIBCXX_CONSTEXPRconstexpr long
    epsilon() _GLIBCXX_USE_NOEXCEPTnoexcept { return 0; }

    static _GLIBCXX_CONSTEXPRconstexpr long
    round_error() _GLIBCXX_USE_NOEXCEPTnoexcept { return 0; }

    static _GLIBCXX_USE_CONSTEXPRconstexpr int min_exponent = 0;
    static _GLIBCXX_USE_CONSTEXPRconstexpr int min_exponent10 = 0;
    static _GLIBCXX_USE_CONSTEXPRconstexpr int max_exponent = 0;
    static _GLIBCXX_USE_CONSTEXPRconstexpr int max_exponent10 = 0;

    static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_infinity = false;
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_quiet_NaN = false;
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_signaling_NaN = false;
    static _GLIBCXX_USE_CONSTEXPRconstexpr float_denorm_style has_denorm
     = denorm_absent;
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_denorm_loss = false;

    static _GLIBCXX_CONSTEXPRconstexpr long
    infinity() _GLIBCXX_USE_NOEXCEPTnoexcept { return static_cast<long>(0); }

    static _GLIBCXX_CONSTEXPRconstexpr long
    quiet_NaN() _GLIBCXX_USE_NOEXCEPTnoexcept { return static_cast<long>(0); }

    static _GLIBCXX_CONSTEXPRconstexpr long
    signaling_NaN() _GLIBCXX_USE_NOEXCEPTnoexcept { return static_cast<long>(0); }

    static _GLIBCXX_CONSTEXPRconstexpr long
    denorm_min() _GLIBCXX_USE_NOEXCEPTnoexcept { return static_cast<long>(0); }

    static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_iec559 = false;
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_bounded = true;
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_modulo = false;

    static _GLIBCXX_USE_CONSTEXPRconstexpr bool traps = __glibcxx_integral_trapstrue;
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool tinyness_before = false;
    static _GLIBCXX_USE_CONSTEXPRconstexpr float_round_style round_style
     = round_toward_zero;
  };

/// numeric_limits<unsigned long> specialization.
template<>
  struct numeric_limits<unsigned long>
  {
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_specialized = true;

    static _GLIBCXX_CONSTEXPRconstexpr unsigned long
    min() _GLIBCXX_USE_NOEXCEPTnoexcept { return 0; }

    static _GLIBCXX_CONSTEXPRconstexpr unsigned long
    max() _GLIBCXX_USE_NOEXCEPTnoexcept { return __LONG_MAX__9223372036854775807L * 2UL + 1; }
11
←
Returning the value 18446744073709551615→

1276#if __cplusplus201703L >= 201103L
    static constexpr unsigned long
    lowest() noexcept { return min(); }
1279#endif

    static _GLIBCXX_USE_CONSTEXPRconstexpr int digits
     = __glibcxx_digits (unsigned long);
    static _GLIBCXX_USE_CONSTEXPRconstexpr int digits10
     = __glibcxx_digits10 (unsigned long);
1285#if __cplusplus201703L >= 201103L
    static constexpr int max_digits10 = 0;
1287#endif
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_signed = false;
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_integer = true;
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_exact = true;
    static _GLIBCXX_USE_CONSTEXPRconstexpr int radix = 2;

    static _GLIBCXX_CONSTEXPRconstexpr unsigned long
    epsilon() _GLIBCXX_USE_NOEXCEPTnoexcept { return 0; }

    static _GLIBCXX_CONSTEXPRconstexpr unsigned long
    round_error() _GLIBCXX_USE_NOEXCEPTnoexcept { return 0; }

    static _GLIBCXX_USE_CONSTEXPRconstexpr int min_exponent = 0;
    static _GLIBCXX_USE_CONSTEXPRconstexpr int min_exponent10 = 0;
    static _GLIBCXX_USE_CONSTEXPRconstexpr int max_exponent = 0;
    static _GLIBCXX_USE_CONSTEXPRconstexpr int max_exponent10 = 0;

    static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_infinity = false;
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_quiet_NaN = false;
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_signaling_NaN = false;
    static _GLIBCXX_USE_CONSTEXPRconstexpr float_denorm_style has_denorm
     = denorm_absent;
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_denorm_loss = false;

    static _GLIBCXX_CONSTEXPRconstexpr unsigned long
    infinity() _GLIBCXX_USE_NOEXCEPTnoexcept
    { return static_cast<unsigned long>(0); }

    static _GLIBCXX_CONSTEXPRconstexpr unsigned long
    quiet_NaN() _GLIBCXX_USE_NOEXCEPTnoexcept
    { return static_cast<unsigned long>(0); }

    static _GLIBCXX_CONSTEXPRconstexpr unsigned long
    signaling_NaN() _GLIBCXX_USE_NOEXCEPTnoexcept
    { return static_cast<unsigned long>(0); }

    static _GLIBCXX_CONSTEXPRconstexpr unsigned long
    denorm_min() _GLIBCXX_USE_NOEXCEPTnoexcept
    { return static_cast<unsigned long>(0); }

    static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_iec559 = false;
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_bounded = true;
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_modulo = true;

    static _GLIBCXX_USE_CONSTEXPRconstexpr bool traps = __glibcxx_integral_trapstrue;
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool tinyness_before = false;
    static _GLIBCXX_USE_CONSTEXPRconstexpr float_round_style round_style
     = round_toward_zero;
  };

/// numeric_limits<long long> specialization.
template<>
  struct numeric_limits<long long>
  {
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_specialized = true;

    static _GLIBCXX_CONSTEXPRconstexpr long long
    min() _GLIBCXX_USE_NOEXCEPTnoexcept { return -__LONG_LONG_MAX__9223372036854775807LL - 1; }

    static _GLIBCXX_CONSTEXPRconstexpr long long
    max() _GLIBCXX_USE_NOEXCEPTnoexcept { return __LONG_LONG_MAX__9223372036854775807LL; }

1349#if __cplusplus201703L >= 201103L
    static constexpr long long
    lowest() noexcept { return min(); }
1352#endif

    static _GLIBCXX_USE_CONSTEXPRconstexpr int digits
     = __glibcxx_digits (long long);
    static _GLIBCXX_USE_CONSTEXPRconstexpr int digits10
     = __glibcxx_digits10 (long long);
1358#if __cplusplus201703L >= 201103L
    static constexpr int max_digits10 = 0;
1360#endif
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_signed = true;
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_integer = true;
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_exact = true;
    static _GLIBCXX_USE_CONSTEXPRconstexpr int radix = 2;

    static _GLIBCXX_CONSTEXPRconstexpr long long
    epsilon() _GLIBCXX_USE_NOEXCEPTnoexcept { return 0; }

    static _GLIBCXX_CONSTEXPRconstexpr long long
    round_error() _GLIBCXX_USE_NOEXCEPTnoexcept { return 0; }

    static _GLIBCXX_USE_CONSTEXPRconstexpr int min_exponent = 0;
    static _GLIBCXX_USE_CONSTEXPRconstexpr int min_exponent10 = 0;
    static _GLIBCXX_USE_CONSTEXPRconstexpr int max_exponent = 0;
    static _GLIBCXX_USE_CONSTEXPRconstexpr int max_exponent10 = 0;

    static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_infinity = false;
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_quiet_NaN = false;
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_signaling_NaN = false;
    static _GLIBCXX_USE_CONSTEXPRconstexpr float_denorm_style has_denorm
     = denorm_absent;
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_denorm_loss = false;

    static _GLIBCXX_CONSTEXPRconstexpr long long
    infinity() _GLIBCXX_USE_NOEXCEPTnoexcept { return static_cast<long long>(0); }

    static _GLIBCXX_CONSTEXPRconstexpr long long
    quiet_NaN() _GLIBCXX_USE_NOEXCEPTnoexcept { return static_cast<long long>(0); }

    static _GLIBCXX_CONSTEXPRconstexpr long long
    signaling_NaN() _GLIBCXX_USE_NOEXCEPTnoexcept
    { return static_cast<long long>(0); }

    static _GLIBCXX_CONSTEXPRconstexpr long long
    denorm_min() _GLIBCXX_USE_NOEXCEPTnoexcept { return static_cast<long long>(0); }

    static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_iec559 = false;
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_bounded = true;
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_modulo = false;

    static _GLIBCXX_USE_CONSTEXPRconstexpr bool traps = __glibcxx_integral_trapstrue;
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool tinyness_before = false;
    static _GLIBCXX_USE_CONSTEXPRconstexpr float_round_style round_style
     = round_toward_zero;
  };

/// numeric_limits<unsigned long long> specialization.
template<>
  struct numeric_limits<unsigned long long>
  {
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_specialized = true;

    static _GLIBCXX_CONSTEXPRconstexpr unsigned long long
    min() _GLIBCXX_USE_NOEXCEPTnoexcept { return 0; }

    static _GLIBCXX_CONSTEXPRconstexpr unsigned long long
    max() _GLIBCXX_USE_NOEXCEPTnoexcept { return __LONG_LONG_MAX__9223372036854775807LL * 2ULL + 1; }

1419#if __cplusplus201703L >= 201103L
    static constexpr unsigned long long
    lowest() noexcept { return min(); }
1422#endif

    static _GLIBCXX_USE_CONSTEXPRconstexpr int digits
     = __glibcxx_digits (unsigned long long);
    static _GLIBCXX_USE_CONSTEXPRconstexpr int digits10
     = __glibcxx_digits10 (unsigned long long);
1428#if __cplusplus201703L >= 201103L
    static constexpr int max_digits10 = 0;
1430#endif
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_signed = false;
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_integer = true;
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_exact = true;
    static _GLIBCXX_USE_CONSTEXPRconstexpr int radix = 2;

    static _GLIBCXX_CONSTEXPRconstexpr unsigned long long
    epsilon() _GLIBCXX_USE_NOEXCEPTnoexcept { return 0; }

    static _GLIBCXX_CONSTEXPRconstexpr unsigned long long
    round_error() _GLIBCXX_USE_NOEXCEPTnoexcept { return 0; }

    static _GLIBCXX_USE_CONSTEXPRconstexpr int min_exponent = 0;
    static _GLIBCXX_USE_CONSTEXPRconstexpr int min_exponent10 = 0;
    static _GLIBCXX_USE_CONSTEXPRconstexpr int max_exponent = 0;
    static _GLIBCXX_USE_CONSTEXPRconstexpr int max_exponent10 = 0;

    static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_infinity = false;
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_quiet_NaN = false;
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_signaling_NaN = false;
    static _GLIBCXX_USE_CONSTEXPRconstexpr float_denorm_style has_denorm
     = denorm_absent;
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_denorm_loss = false;

    static _GLIBCXX_CONSTEXPRconstexpr unsigned long long
    infinity() _GLIBCXX_USE_NOEXCEPTnoexcept
    { return static_cast<unsigned long long>(0); }

    static _GLIBCXX_CONSTEXPRconstexpr unsigned long long
    quiet_NaN() _GLIBCXX_USE_NOEXCEPTnoexcept
    { return static_cast<unsigned long long>(0); }

    static _GLIBCXX_CONSTEXPRconstexpr unsigned long long
    signaling_NaN() _GLIBCXX_USE_NOEXCEPTnoexcept
    { return static_cast<unsigned long long>(0); }

    static _GLIBCXX_CONSTEXPRconstexpr unsigned long long
    denorm_min() _GLIBCXX_USE_NOEXCEPTnoexcept
    { return static_cast<unsigned long long>(0); }

    static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_iec559 = false;
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_bounded = true;
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_modulo = true;

    static _GLIBCXX_USE_CONSTEXPRconstexpr bool traps = __glibcxx_integral_trapstrue;
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool tinyness_before = false;
    static _GLIBCXX_USE_CONSTEXPRconstexpr float_round_style round_style
     = round_toward_zero;
  };

1480#define __INT_N(TYPE, BITSIZE, EXT, UEXT)			\
template<> 									\
  struct numeric_limits<TYPE> 						\
  { 										\
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_specialized = true; 		\
									\
    static _GLIBCXX_CONSTEXPRconstexpr TYPE 						\
min() _GLIBCXX_USE_NOEXCEPTnoexcept { return __glibcxx_min_b (TYPE, BITSIZE)(((TYPE)(-1) < 0) ? -(((TYPE)(-1) < 0) ? (((((TYPE)1 <<
 ((BITSIZE - ((TYPE)(-1) < 0)) - 1)) - 1) << 1) + 1)
 : ~(TYPE)0) - 1 : (TYPE)0); } \
									\
    static _GLIBCXX_CONSTEXPRconstexpr TYPE 						\
    max() _GLIBCXX_USE_NOEXCEPTnoexcept { return __glibcxx_max_b (TYPE, BITSIZE)(((TYPE)(-1) < 0) ? (((((TYPE)1 << ((BITSIZE - ((TYPE
)(-1) < 0)) - 1)) - 1) << 1) + 1) : ~(TYPE)0); } 	\
									\
    static _GLIBCXX_USE_CONSTEXPRconstexpr int digits 					\
     = BITSIZE - 1; 								\
    static _GLIBCXX_USE_CONSTEXPRconstexpr int digits10 				\
     = (BITSIZE - 1) * 643L / 2136; 						\
    										\
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_signed = true; 			\
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_integer = true; 			\
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_exact = true; 			\
    static _GLIBCXX_USE_CONSTEXPRconstexpr int radix = 2; 				\
									\
    static _GLIBCXX_CONSTEXPRconstexpr TYPE 						\
    epsilon() _GLIBCXX_USE_NOEXCEPTnoexcept { return 0; } 				\
									\
    static _GLIBCXX_CONSTEXPRconstexpr TYPE 						\
    round_error() _GLIBCXX_USE_NOEXCEPTnoexcept { return 0; } 			\
									\
    EXT									\
									\
    static _GLIBCXX_USE_CONSTEXPRconstexpr int min_exponent = 0; 			\
    static _GLIBCXX_USE_CONSTEXPRconstexpr int min_exponent10 = 0; 			\
    static _GLIBCXX_USE_CONSTEXPRconstexpr int max_exponent = 0; 			\
    static _GLIBCXX_USE_CONSTEXPRconstexpr int max_exponent10 = 0; 			\
									\
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_infinity = false; 			\
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_quiet_NaN = false; 		\
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_signaling_NaN = false; 		\
    static _GLIBCXX_USE_CONSTEXPRconstexpr float_denorm_style has_denorm 		\
     = denorm_absent; 							\
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_denorm_loss = false; 		\
									\
    static _GLIBCXX_CONSTEXPRconstexpr TYPE 						\
    infinity() _GLIBCXX_USE_NOEXCEPTnoexcept 						\
    { return static_cast<TYPE>(0); } 						\
									\
    static _GLIBCXX_CONSTEXPRconstexpr TYPE 						\
    quiet_NaN() _GLIBCXX_USE_NOEXCEPTnoexcept 					\
    { return static_cast<TYPE>(0); } 						\
     										\
    static _GLIBCXX_CONSTEXPRconstexpr TYPE 						\
    signaling_NaN() _GLIBCXX_USE_NOEXCEPTnoexcept 					\
    { return static_cast<TYPE>(0); } 						\
     										\
    static _GLIBCXX_CONSTEXPRconstexpr TYPE 						\
    denorm_min() _GLIBCXX_USE_NOEXCEPTnoexcept 					\
    { return static_cast<TYPE>(0); } 						\
									\
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_iec559 = false; 			\
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_bounded = true; 			\
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_modulo = false; 			\
									\
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool traps 					\
     = __glibcxx_integral_trapstrue; 						\
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool tinyness_before = false; 		\
    static _GLIBCXX_USE_CONSTEXPRconstexpr float_round_style round_style 		\
     = round_toward_zero; 							\
  }; 										\
									\
template<> 									\
  struct numeric_limits<unsigned TYPE> 					\
  { 										\
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_specialized = true; 		\
									\
    static _GLIBCXX_CONSTEXPRconstexpr unsigned TYPE 					\
    min() _GLIBCXX_USE_NOEXCEPTnoexcept { return 0; } 				\
									\
    static _GLIBCXX_CONSTEXPRconstexpr unsigned TYPE 					\
    max() _GLIBCXX_USE_NOEXCEPTnoexcept						\
    { return  __glibcxx_max_b (unsigned TYPE, BITSIZE)(((unsigned TYPE)(-1) < 0) ? (((((unsigned TYPE)1 <<
 ((BITSIZE - ((unsigned TYPE)(-1) < 0)) - 1)) - 1) <<
 1) + 1) : ~(unsigned TYPE)0); }			\
									\
    UEXT									\
									\
    static _GLIBCXX_USE_CONSTEXPRconstexpr int digits 					\
     = BITSIZE; 								\
    static _GLIBCXX_USE_CONSTEXPRconstexpr int digits10 				\
     = BITSIZE * 643L / 2136; 						\
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_signed = false; 			\
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_integer = true; 			\
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_exact = true; 			\
    static _GLIBCXX_USE_CONSTEXPRconstexpr int radix = 2; 				\
									\
    static _GLIBCXX_CONSTEXPRconstexpr unsigned TYPE 					\
    epsilon() _GLIBCXX_USE_NOEXCEPTnoexcept { return 0; } 				\
									\
    static _GLIBCXX_CONSTEXPRconstexpr unsigned TYPE 					\
    round_error() _GLIBCXX_USE_NOEXCEPTnoexcept { return 0; } 			\
									\
    static _GLIBCXX_USE_CONSTEXPRconstexpr int min_exponent = 0; 			\
    static _GLIBCXX_USE_CONSTEXPRconstexpr int min_exponent10 = 0; 			\
    static _GLIBCXX_USE_CONSTEXPRconstexpr int max_exponent = 0; 			\
    static _GLIBCXX_USE_CONSTEXPRconstexpr int max_exponent10 = 0; 			\
									\
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_infinity = false; 			\
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_quiet_NaN = false; 		\
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_signaling_NaN = false; 		\
    static _GLIBCXX_USE_CONSTEXPRconstexpr float_denorm_style has_denorm 		\
     = denorm_absent; 							\
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_denorm_loss = false; 		\
									\
    static _GLIBCXX_CONSTEXPRconstexpr unsigned TYPE 					\
    infinity() _GLIBCXX_USE_NOEXCEPTnoexcept 						\
    { return static_cast<unsigned TYPE>(0); } 				\
									\
    static _GLIBCXX_CONSTEXPRconstexpr unsigned TYPE 					\
    quiet_NaN() _GLIBCXX_USE_NOEXCEPTnoexcept 					\
    { return static_cast<unsigned TYPE>(0); } 				\
									\
    static _GLIBCXX_CONSTEXPRconstexpr unsigned TYPE 					\
    signaling_NaN() _GLIBCXX_USE_NOEXCEPTnoexcept 					\
    { return static_cast<unsigned TYPE>(0); } 				\
									\
    static _GLIBCXX_CONSTEXPRconstexpr unsigned TYPE 					\
    denorm_min() _GLIBCXX_USE_NOEXCEPTnoexcept 					\
    { return static_cast<unsigned TYPE>(0); } 				\
									\
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_iec559 = false; 			\
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_bounded = true; 			\
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_modulo = true; 			\
									\
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool traps = __glibcxx_integral_trapstrue; 	\
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool tinyness_before = false; 		\
    static _GLIBCXX_USE_CONSTEXPRconstexpr float_round_style round_style 		\
     = round_toward_zero; 							\
  };

1616#if __cplusplus201703L >= 201103L

1618#define __INT_N_201103(TYPE)							\
    static constexpr TYPE 							\
    lowest() noexcept { return min(); }					\
    static constexpr int max_digits10 = 0;

1623#define __INT_N_U201103(TYPE)							\
    static constexpr unsigned TYPE 						\
    lowest() noexcept { return min(); }					\
    static constexpr int max_digits10 = 0;

1628#else
1629#define __INT_N_201103(TYPE)
1630#define __INT_N_U201103(TYPE)
1631#endif

1633#if !defined(__STRICT_ANSI__1)
1634#ifdef __GLIBCXX_TYPE_INT_N_0
__INT_N(__GLIBCXX_TYPE_INT_N_0, __GLIBCXX_BITSIZE_INT_N_0,
 __INT_N_201103 (__GLIBCXX_TYPE_INT_N_0), __INT_N_U201103 (__GLIBCXX_TYPE_INT_N_0))
1637#endif
1638#ifdef __GLIBCXX_TYPE_INT_N_1
__INT_N (__GLIBCXX_TYPE_INT_N_1, __GLIBCXX_BITSIZE_INT_N_1,
 __INT_N_201103 (__GLIBCXX_TYPE_INT_N_1), __INT_N_U201103 (__GLIBCXX_TYPE_INT_N_1))
1641#endif
1642#ifdef __GLIBCXX_TYPE_INT_N_2
__INT_N (__GLIBCXX_TYPE_INT_N_2, __GLIBCXX_BITSIZE_INT_N_2,
 __INT_N_201103 (__GLIBCXX_TYPE_INT_N_2), __INT_N_U201103 (__GLIBCXX_TYPE_INT_N_2))
1645#endif
1646#ifdef __GLIBCXX_TYPE_INT_N_3
__INT_N (__GLIBCXX_TYPE_INT_N_3, __GLIBCXX_BITSIZE_INT_N_3,
 __INT_N_201103 (__GLIBCXX_TYPE_INT_N_3), __INT_N_U201103 (__GLIBCXX_TYPE_INT_N_3))
1649#endif

1651#elif defined __STRICT_ANSI__1 && defined __SIZEOF_INT128__16
__INT_N(__int128, 128,
 __INT_N_201103 (__int128),
 __INT_N_U201103 (__int128))
1655#endif

1657#undef __INT_N
1658#undef __INT_N_201103
1659#undef __INT_N_U201103


/// numeric_limits<float> specialization.
template<>
  struct numeric_limits<float>
  {
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_specialized = true;

    static _GLIBCXX_CONSTEXPRconstexpr float
    min() _GLIBCXX_USE_NOEXCEPTnoexcept { return __FLT_MIN__1.17549435e-38F; }

    static _GLIBCXX_CONSTEXPRconstexpr float
    max() _GLIBCXX_USE_NOEXCEPTnoexcept { return __FLT_MAX__3.40282347e+38F; }

1674#if __cplusplus201703L >= 201103L
    static constexpr float
    lowest() noexcept { return -__FLT_MAX__3.40282347e+38F; }
1677#endif

    static _GLIBCXX_USE_CONSTEXPRconstexpr int digits = __FLT_MANT_DIG__24;
    static _GLIBCXX_USE_CONSTEXPRconstexpr int digits10 = __FLT_DIG__6;
1681#if __cplusplus201703L >= 201103L
    static constexpr int max_digits10
= __glibcxx_max_digits10 (__FLT_MANT_DIG__24);
1684#endif
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_signed = true;
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_integer = false;
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_exact = false;
    static _GLIBCXX_USE_CONSTEXPRconstexpr int radix = __FLT_RADIX__2;

    static _GLIBCXX_CONSTEXPRconstexpr float
    epsilon() _GLIBCXX_USE_NOEXCEPTnoexcept { return __FLT_EPSILON__1.19209290e-7F; }

    static _GLIBCXX_CONSTEXPRconstexpr float
    round_error() _GLIBCXX_USE_NOEXCEPTnoexcept { return 0.5F; }

    static _GLIBCXX_USE_CONSTEXPRconstexpr int min_exponent = __FLT_MIN_EXP__(-125);
    static _GLIBCXX_USE_CONSTEXPRconstexpr int min_exponent10 = __FLT_MIN_10_EXP__(-37);
    static _GLIBCXX_USE_CONSTEXPRconstexpr int max_exponent = __FLT_MAX_EXP__128;
    static _GLIBCXX_USE_CONSTEXPRconstexpr int max_exponent10 = __FLT_MAX_10_EXP__38;

    static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_infinity = __FLT_HAS_INFINITY__1;
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_quiet_NaN = __FLT_HAS_QUIET_NAN__1;
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_signaling_NaN = has_quiet_NaN;
    static _GLIBCXX_USE_CONSTEXPRconstexpr float_denorm_style has_denorm
= bool(__FLT_HAS_DENORM__1) ? denorm_present : denorm_absent;
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_denorm_loss
     = __glibcxx_float_has_denorm_loss;

    static _GLIBCXX_CONSTEXPRconstexpr float
    infinity() _GLIBCXX_USE_NOEXCEPTnoexcept { return __builtin_huge_valf(); }

    static _GLIBCXX_CONSTEXPRconstexpr float
    quiet_NaN() _GLIBCXX_USE_NOEXCEPTnoexcept { return __builtin_nanf(""); }

    static _GLIBCXX_CONSTEXPRconstexpr float
    signaling_NaN() _GLIBCXX_USE_NOEXCEPTnoexcept { return __builtin_nansf(""); }

    static _GLIBCXX_CONSTEXPRconstexpr float
    denorm_min() _GLIBCXX_USE_NOEXCEPTnoexcept { return __FLT_DENORM_MIN__1.40129846e-45F; }

    static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_iec559
= has_infinity && has_quiet_NaN && has_denorm == denorm_present;
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_bounded = true;
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_modulo = false;

    static _GLIBCXX_USE_CONSTEXPRconstexpr bool traps = __glibcxx_float_traps;
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool tinyness_before
     = __glibcxx_float_tinyness_before;
    static _GLIBCXX_USE_CONSTEXPRconstexpr float_round_style round_style
     = round_to_nearest;
  };

1733#undef __glibcxx_float_has_denorm_loss
1734#undef __glibcxx_float_traps
1735#undef __glibcxx_float_tinyness_before

/// numeric_limits<double> specialization.
template<>
  struct numeric_limits<double>
  {
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_specialized = true;

    static _GLIBCXX_CONSTEXPRconstexpr double
    min() _GLIBCXX_USE_NOEXCEPTnoexcept { return __DBL_MIN__2.2250738585072014e-308; }

    static _GLIBCXX_CONSTEXPRconstexpr double
    max() _GLIBCXX_USE_NOEXCEPTnoexcept { return __DBL_MAX__1.7976931348623157e+308; }

1749#if __cplusplus201703L >= 201103L
    static constexpr double
    lowest() noexcept { return -__DBL_MAX__1.7976931348623157e+308; }
1752#endif

    static _GLIBCXX_USE_CONSTEXPRconstexpr int digits = __DBL_MANT_DIG__53;
    static _GLIBCXX_USE_CONSTEXPRconstexpr int digits10 = __DBL_DIG__15;
1756#if __cplusplus201703L >= 201103L
    static constexpr int max_digits10
= __glibcxx_max_digits10 (__DBL_MANT_DIG__53);
1759#endif
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_signed = true;
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_integer = false;
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_exact = false;
    static _GLIBCXX_USE_CONSTEXPRconstexpr int radix = __FLT_RADIX__2;

    static _GLIBCXX_CONSTEXPRconstexpr double
    epsilon() _GLIBCXX_USE_NOEXCEPTnoexcept { return __DBL_EPSILON__2.2204460492503131e-16; }

    static _GLIBCXX_CONSTEXPRconstexpr double
    round_error() _GLIBCXX_USE_NOEXCEPTnoexcept { return 0.5; }

    static _GLIBCXX_USE_CONSTEXPRconstexpr int min_exponent = __DBL_MIN_EXP__(-1021);
    static _GLIBCXX_USE_CONSTEXPRconstexpr int min_exponent10 = __DBL_MIN_10_EXP__(-307);
    static _GLIBCXX_USE_CONSTEXPRconstexpr int max_exponent = __DBL_MAX_EXP__1024;
    static _GLIBCXX_USE_CONSTEXPRconstexpr int max_exponent10 = __DBL_MAX_10_EXP__308;

    static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_infinity = __DBL_HAS_INFINITY__1;
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_quiet_NaN = __DBL_HAS_QUIET_NAN__1;
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_signaling_NaN = has_quiet_NaN;
    static _GLIBCXX_USE_CONSTEXPRconstexpr float_denorm_style has_denorm
= bool(__DBL_HAS_DENORM__1) ? denorm_present : denorm_absent;
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_denorm_loss
      = __glibcxx_double_has_denorm_loss;

    static _GLIBCXX_CONSTEXPRconstexpr double
    infinity() _GLIBCXX_USE_NOEXCEPTnoexcept { return __builtin_huge_val(); }

    static _GLIBCXX_CONSTEXPRconstexpr double
    quiet_NaN() _GLIBCXX_USE_NOEXCEPTnoexcept { return __builtin_nan(""); }

    static _GLIBCXX_CONSTEXPRconstexpr double
    signaling_NaN() _GLIBCXX_USE_NOEXCEPTnoexcept { return __builtin_nans(""); }

    static _GLIBCXX_CONSTEXPRconstexpr double
    denorm_min() _GLIBCXX_USE_NOEXCEPTnoexcept { return __DBL_DENORM_MIN__4.9406564584124654e-324; }

    static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_iec559
= has_infinity && has_quiet_NaN && has_denorm == denorm_present;
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_bounded = true;
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_modulo = false;

    static _GLIBCXX_USE_CONSTEXPRconstexpr bool traps = __glibcxx_double_traps;
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool tinyness_before
     = __glibcxx_double_tinyness_before;
    static _GLIBCXX_USE_CONSTEXPRconstexpr float_round_style round_style
     = round_to_nearest;
  };

1808#undef __glibcxx_double_has_denorm_loss
1809#undef __glibcxx_double_traps
1810#undef __glibcxx_double_tinyness_before

/// numeric_limits<long double> specialization.
template<>
  struct numeric_limits<long double>
  {
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_specialized = true;

    static _GLIBCXX_CONSTEXPRconstexpr long double
    min() _GLIBCXX_USE_NOEXCEPTnoexcept { return __LDBL_MIN__3.36210314311209350626e-4932L; }

    static _GLIBCXX_CONSTEXPRconstexpr long double
    max() _GLIBCXX_USE_NOEXCEPTnoexcept { return __LDBL_MAX__1.18973149535723176502e+4932L; }

1824#if __cplusplus201703L >= 201103L
    static constexpr long double
    lowest() noexcept { return -__LDBL_MAX__1.18973149535723176502e+4932L; }
1827#endif

    static _GLIBCXX_USE_CONSTEXPRconstexpr int digits = __LDBL_MANT_DIG__64;
    static _GLIBCXX_USE_CONSTEXPRconstexpr int digits10 = __LDBL_DIG__18;
1831#if __cplusplus201703L >= 201103L
    static _GLIBCXX_USE_CONSTEXPRconstexpr int max_digits10
= __glibcxx_max_digits10 (__LDBL_MANT_DIG__64);
1834#endif
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_signed = true;
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_integer = false;
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_exact = false;
    static _GLIBCXX_USE_CONSTEXPRconstexpr int radix = __FLT_RADIX__2;

    static _GLIBCXX_CONSTEXPRconstexpr long double
    epsilon() _GLIBCXX_USE_NOEXCEPTnoexcept { return __LDBL_EPSILON__1.08420217248550443401e-19L; }

    static _GLIBCXX_CONSTEXPRconstexpr long double
    round_error() _GLIBCXX_USE_NOEXCEPTnoexcept { return 0.5L; }

    static _GLIBCXX_USE_CONSTEXPRconstexpr int min_exponent = __LDBL_MIN_EXP__(-16381);
    static _GLIBCXX_USE_CONSTEXPRconstexpr int min_exponent10 = __LDBL_MIN_10_EXP__(-4931);
    static _GLIBCXX_USE_CONSTEXPRconstexpr int max_exponent = __LDBL_MAX_EXP__16384;
    static _GLIBCXX_USE_CONSTEXPRconstexpr int max_exponent10 = __LDBL_MAX_10_EXP__4932;

    static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_infinity = __LDBL_HAS_INFINITY__1;
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_quiet_NaN = __LDBL_HAS_QUIET_NAN__1;
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_signaling_NaN = has_quiet_NaN;
    static _GLIBCXX_USE_CONSTEXPRconstexpr float_denorm_style has_denorm
= bool(__LDBL_HAS_DENORM__1) ? denorm_present : denorm_absent;
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_denorm_loss
= __glibcxx_long_double_has_denorm_loss;

    static _GLIBCXX_CONSTEXPRconstexpr long double
    infinity() _GLIBCXX_USE_NOEXCEPTnoexcept { return __builtin_huge_vall(); }

    static _GLIBCXX_CONSTEXPRconstexpr long double
    quiet_NaN() _GLIBCXX_USE_NOEXCEPTnoexcept { return __builtin_nanl(""); }

    static _GLIBCXX_CONSTEXPRconstexpr long double
    signaling_NaN() _GLIBCXX_USE_NOEXCEPTnoexcept { return __builtin_nansl(""); }

    static _GLIBCXX_CONSTEXPRconstexpr long double
    denorm_min() _GLIBCXX_USE_NOEXCEPTnoexcept { return __LDBL_DENORM_MIN__3.64519953188247460253e-4951L; }

    static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_iec559
= has_infinity && has_quiet_NaN && has_denorm == denorm_present;
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_bounded = true;
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_modulo = false;

    static _GLIBCXX_USE_CONSTEXPRconstexpr bool traps = __glibcxx_long_double_traps;
    static _GLIBCXX_USE_CONSTEXPRconstexpr bool tinyness_before =
			 __glibcxx_long_double_tinyness_before;
    static _GLIBCXX_USE_CONSTEXPRconstexpr float_round_style round_style =
				      round_to_nearest;
  };

1883#undef __glibcxx_long_double_has_denorm_loss
1884#undef __glibcxx_long_double_traps
1885#undef __glibcxx_long_double_tinyness_before

1887_GLIBCXX_END_NAMESPACE_VERSION
1888} // namespace

1890#undef __glibcxx_signed
1891#undef __glibcxx_min
1892#undef __glibcxx_max
1893#undef __glibcxx_digits
1894#undef __glibcxx_digits10
1895#undef __glibcxx_max_digits10

1897#endif // _GLIBCXX_NUMERIC_LIMITS