Bug Summary

File:llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
Warning:line 1676, column 24
The result of the right shift is undefined due to shifting by '4294967295', which is greater or equal to the width of type 'uint64_t'

Annotated Source Code

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clang -cc1 -cc1 -triple x86_64-pc-linux-gnu -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name SystemZInstrInfo.cpp -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=cplusplus -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -analyzer-config-compatibility-mode=true -mrelocation-model pic -pic-level 2 -mframe-pointer=none -fmath-errno -fno-rounding-math -mconstructor-aliases -munwind-tables -target-cpu x86-64 -tune-cpu generic -debugger-tuning=gdb -ffunction-sections -fdata-sections -fcoverage-compilation-dir=/build/llvm-toolchain-snapshot-14~++20210903100615+fd66b44ec19e/build-llvm/lib/Target/SystemZ -resource-dir /usr/lib/llvm-14/lib/clang/14.0.0 -D _GNU_SOURCE -D __STDC_CONSTANT_MACROS -D __STDC_FORMAT_MACROS -D __STDC_LIMIT_MACROS -I /build/llvm-toolchain-snapshot-14~++20210903100615+fd66b44ec19e/build-llvm/lib/Target/SystemZ -I /build/llvm-toolchain-snapshot-14~++20210903100615+fd66b44ec19e/llvm/lib/Target/SystemZ -I /build/llvm-toolchain-snapshot-14~++20210903100615+fd66b44ec19e/build-llvm/include -I /build/llvm-toolchain-snapshot-14~++20210903100615+fd66b44ec19e/llvm/include -D NDEBUG -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/10/../../../../include/c++/10 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/10/../../../../include/x86_64-linux-gnu/c++/10 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/10/../../../../include/c++/10/backward -internal-isystem /usr/lib/llvm-14/lib/clang/14.0.0/include -internal-isystem /usr/local/include -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/10/../../../../x86_64-linux-gnu/include -internal-externc-isystem /usr/include/x86_64-linux-gnu -internal-externc-isystem /include -internal-externc-isystem /usr/include -O2 -Wno-unused-parameter -Wwrite-strings -Wno-missing-field-initializers -Wno-long-long -Wno-maybe-uninitialized -Wno-class-memaccess -Wno-redundant-move -Wno-pessimizing-move -Wno-noexcept-type -Wno-comment -std=c++14 -fdeprecated-macro -fdebug-compilation-dir=/build/llvm-toolchain-snapshot-14~++20210903100615+fd66b44ec19e/build-llvm/lib/Target/SystemZ -fdebug-prefix-map=/build/llvm-toolchain-snapshot-14~++20210903100615+fd66b44ec19e=. -ferror-limit 19 -fvisibility hidden -fvisibility-inlines-hidden -stack-protector 2 -fgnuc-version=4.2.1 -vectorize-loops -vectorize-slp -analyzer-output=html -analyzer-config stable-report-filename=true -faddrsig -D__GCC_HAVE_DWARF2_CFI_ASM=1 -o /tmp/scan-build-2021-09-04-040900-46481-1 -x c++ /build/llvm-toolchain-snapshot-14~++20210903100615+fd66b44ec19e/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp

/build/llvm-toolchain-snapshot-14~++20210903100615+fd66b44ec19e/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp

1//===-- SystemZInstrInfo.cpp - SystemZ instruction information ------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the SystemZ implementation of the TargetInstrInfo class.
10//
11//===----------------------------------------------------------------------===//
12
13#include "SystemZInstrInfo.h"
14#include "MCTargetDesc/SystemZMCTargetDesc.h"
15#include "SystemZ.h"
16#include "SystemZInstrBuilder.h"
17#include "SystemZSubtarget.h"
18#include "llvm/ADT/Statistic.h"
19#include "llvm/CodeGen/LiveInterval.h"
20#include "llvm/CodeGen/LiveIntervals.h"
21#include "llvm/CodeGen/LiveVariables.h"
22#include "llvm/CodeGen/MachineBasicBlock.h"
23#include "llvm/CodeGen/MachineFrameInfo.h"
24#include "llvm/CodeGen/MachineFunction.h"
25#include "llvm/CodeGen/MachineInstr.h"
26#include "llvm/CodeGen/MachineMemOperand.h"
27#include "llvm/CodeGen/MachineOperand.h"
28#include "llvm/CodeGen/MachineRegisterInfo.h"
29#include "llvm/CodeGen/SlotIndexes.h"
30#include "llvm/CodeGen/TargetInstrInfo.h"
31#include "llvm/CodeGen/TargetSubtargetInfo.h"
32#include "llvm/MC/MCInstrDesc.h"
33#include "llvm/MC/MCRegisterInfo.h"
34#include "llvm/Support/BranchProbability.h"
35#include "llvm/Support/ErrorHandling.h"
36#include "llvm/Support/MathExtras.h"
37#include "llvm/Target/TargetMachine.h"
38#include <cassert>
39#include <cstdint>
40#include <iterator>
41
42using namespace llvm;
43
44#define GET_INSTRINFO_CTOR_DTOR
45#define GET_INSTRMAP_INFO
46#include "SystemZGenInstrInfo.inc"
47
48#define DEBUG_TYPE"systemz-II" "systemz-II"
49
50// Return a mask with Count low bits set.
51static uint64_t allOnes(unsigned int Count) {
52 return Count == 0 ? 0 : (uint64_t(1) << (Count - 1) << 1) - 1;
53}
54
55// Pin the vtable to this file.
56void SystemZInstrInfo::anchor() {}
57
58SystemZInstrInfo::SystemZInstrInfo(SystemZSubtarget &sti)
59 : SystemZGenInstrInfo(SystemZ::ADJCALLSTACKDOWN, SystemZ::ADJCALLSTACKUP),
60 RI(sti.getSpecialRegisters()->getReturnFunctionAddressRegister()),
61 STI(sti) {}
62
63// MI is a 128-bit load or store. Split it into two 64-bit loads or stores,
64// each having the opcode given by NewOpcode.
65void SystemZInstrInfo::splitMove(MachineBasicBlock::iterator MI,
66 unsigned NewOpcode) const {
67 MachineBasicBlock *MBB = MI->getParent();
68 MachineFunction &MF = *MBB->getParent();
69
70 // Get two load or store instructions. Use the original instruction for one
71 // of them (arbitrarily the second here) and create a clone for the other.
72 MachineInstr *EarlierMI = MF.CloneMachineInstr(&*MI);
73 MBB->insert(MI, EarlierMI);
74
75 // Set up the two 64-bit registers and remember super reg and its flags.
76 MachineOperand &HighRegOp = EarlierMI->getOperand(0);
77 MachineOperand &LowRegOp = MI->getOperand(0);
78 Register Reg128 = LowRegOp.getReg();
79 unsigned Reg128Killed = getKillRegState(LowRegOp.isKill());
80 unsigned Reg128Undef = getUndefRegState(LowRegOp.isUndef());
81 HighRegOp.setReg(RI.getSubReg(HighRegOp.getReg(), SystemZ::subreg_h64));
82 LowRegOp.setReg(RI.getSubReg(LowRegOp.getReg(), SystemZ::subreg_l64));
83
84 if (MI->mayStore()) {
85 // Add implicit uses of the super register in case one of the subregs is
86 // undefined. We could track liveness and skip storing an undefined
87 // subreg, but this is hopefully rare (discovered with llvm-stress).
88 // If Reg128 was killed, set kill flag on MI.
89 unsigned Reg128UndefImpl = (Reg128Undef | RegState::Implicit);
90 MachineInstrBuilder(MF, EarlierMI).addReg(Reg128, Reg128UndefImpl);
91 MachineInstrBuilder(MF, MI).addReg(Reg128, (Reg128UndefImpl | Reg128Killed));
92 }
93
94 // The address in the first (high) instruction is already correct.
95 // Adjust the offset in the second (low) instruction.
96 MachineOperand &HighOffsetOp = EarlierMI->getOperand(2);
97 MachineOperand &LowOffsetOp = MI->getOperand(2);
98 LowOffsetOp.setImm(LowOffsetOp.getImm() + 8);
99
100 // Clear the kill flags on the registers in the first instruction.
101 if (EarlierMI->getOperand(0).isReg() && EarlierMI->getOperand(0).isUse())
102 EarlierMI->getOperand(0).setIsKill(false);
103 EarlierMI->getOperand(1).setIsKill(false);
104 EarlierMI->getOperand(3).setIsKill(false);
105
106 // Set the opcodes.
107 unsigned HighOpcode = getOpcodeForOffset(NewOpcode, HighOffsetOp.getImm());
108 unsigned LowOpcode = getOpcodeForOffset(NewOpcode, LowOffsetOp.getImm());
109 assert(HighOpcode && LowOpcode && "Both offsets should be in range")(static_cast<void> (0));
110
111 EarlierMI->setDesc(get(HighOpcode));
112 MI->setDesc(get(LowOpcode));
113}
114
115// Split ADJDYNALLOC instruction MI.
116void SystemZInstrInfo::splitAdjDynAlloc(MachineBasicBlock::iterator MI) const {
117 MachineBasicBlock *MBB = MI->getParent();
118 MachineFunction &MF = *MBB->getParent();
119 MachineFrameInfo &MFFrame = MF.getFrameInfo();
120 MachineOperand &OffsetMO = MI->getOperand(2);
121
122 uint64_t Offset = (MFFrame.getMaxCallFrameSize() +
123 SystemZMC::ELFCallFrameSize +
124 OffsetMO.getImm());
125 unsigned NewOpcode = getOpcodeForOffset(SystemZ::LA, Offset);
126 assert(NewOpcode && "No support for huge argument lists yet")(static_cast<void> (0));
127 MI->setDesc(get(NewOpcode));
128 OffsetMO.setImm(Offset);
129}
130
131// MI is an RI-style pseudo instruction. Replace it with LowOpcode
132// if the first operand is a low GR32 and HighOpcode if the first operand
133// is a high GR32. ConvertHigh is true if LowOpcode takes a signed operand
134// and HighOpcode takes an unsigned 32-bit operand. In those cases,
135// MI has the same kind of operand as LowOpcode, so needs to be converted
136// if HighOpcode is used.
137void SystemZInstrInfo::expandRIPseudo(MachineInstr &MI, unsigned LowOpcode,
138 unsigned HighOpcode,
139 bool ConvertHigh) const {
140 Register Reg = MI.getOperand(0).getReg();
141 bool IsHigh = SystemZ::isHighReg(Reg);
142 MI.setDesc(get(IsHigh ? HighOpcode : LowOpcode));
143 if (IsHigh && ConvertHigh)
144 MI.getOperand(1).setImm(uint32_t(MI.getOperand(1).getImm()));
145}
146
147// MI is a three-operand RIE-style pseudo instruction. Replace it with
148// LowOpcodeK if the registers are both low GR32s, otherwise use a move
149// followed by HighOpcode or LowOpcode, depending on whether the target
150// is a high or low GR32.
151void SystemZInstrInfo::expandRIEPseudo(MachineInstr &MI, unsigned LowOpcode,
152 unsigned LowOpcodeK,
153 unsigned HighOpcode) const {
154 Register DestReg = MI.getOperand(0).getReg();
155 Register SrcReg = MI.getOperand(1).getReg();
156 bool DestIsHigh = SystemZ::isHighReg(DestReg);
157 bool SrcIsHigh = SystemZ::isHighReg(SrcReg);
158 if (!DestIsHigh && !SrcIsHigh)
159 MI.setDesc(get(LowOpcodeK));
160 else {
161 if (DestReg != SrcReg) {
162 emitGRX32Move(*MI.getParent(), MI, MI.getDebugLoc(), DestReg, SrcReg,
163 SystemZ::LR, 32, MI.getOperand(1).isKill(),
164 MI.getOperand(1).isUndef());
165 MI.getOperand(1).setReg(DestReg);
166 }
167 MI.setDesc(get(DestIsHigh ? HighOpcode : LowOpcode));
168 MI.tieOperands(0, 1);
169 }
170}
171
172// MI is an RXY-style pseudo instruction. Replace it with LowOpcode
173// if the first operand is a low GR32 and HighOpcode if the first operand
174// is a high GR32.
175void SystemZInstrInfo::expandRXYPseudo(MachineInstr &MI, unsigned LowOpcode,
176 unsigned HighOpcode) const {
177 Register Reg = MI.getOperand(0).getReg();
178 unsigned Opcode = getOpcodeForOffset(
179 SystemZ::isHighReg(Reg) ? HighOpcode : LowOpcode,
180 MI.getOperand(2).getImm());
181 MI.setDesc(get(Opcode));
182}
183
184// MI is a load-on-condition pseudo instruction with a single register
185// (source or destination) operand. Replace it with LowOpcode if the
186// register is a low GR32 and HighOpcode if the register is a high GR32.
187void SystemZInstrInfo::expandLOCPseudo(MachineInstr &MI, unsigned LowOpcode,
188 unsigned HighOpcode) const {
189 Register Reg = MI.getOperand(0).getReg();
190 unsigned Opcode = SystemZ::isHighReg(Reg) ? HighOpcode : LowOpcode;
191 MI.setDesc(get(Opcode));
192}
193
194// MI is an RR-style pseudo instruction that zero-extends the low Size bits
195// of one GRX32 into another. Replace it with LowOpcode if both operands
196// are low registers, otherwise use RISB[LH]G.
197void SystemZInstrInfo::expandZExtPseudo(MachineInstr &MI, unsigned LowOpcode,
198 unsigned Size) const {
199 MachineInstrBuilder MIB =
200 emitGRX32Move(*MI.getParent(), MI, MI.getDebugLoc(),
201 MI.getOperand(0).getReg(), MI.getOperand(1).getReg(), LowOpcode,
202 Size, MI.getOperand(1).isKill(), MI.getOperand(1).isUndef());
203
204 // Keep the remaining operands as-is.
205 for (unsigned I = 2; I < MI.getNumOperands(); ++I)
206 MIB.add(MI.getOperand(I));
207
208 MI.eraseFromParent();
209}
210
211void SystemZInstrInfo::expandLoadStackGuard(MachineInstr *MI) const {
212 MachineBasicBlock *MBB = MI->getParent();
213 MachineFunction &MF = *MBB->getParent();
214 const Register Reg64 = MI->getOperand(0).getReg();
215 const Register Reg32 = RI.getSubReg(Reg64, SystemZ::subreg_l32);
216
217 // EAR can only load the low subregister so us a shift for %a0 to produce
218 // the GR containing %a0 and %a1.
219
220 // ear <reg>, %a0
221 BuildMI(*MBB, MI, MI->getDebugLoc(), get(SystemZ::EAR), Reg32)
222 .addReg(SystemZ::A0)
223 .addReg(Reg64, RegState::ImplicitDefine);
224
225 // sllg <reg>, <reg>, 32
226 BuildMI(*MBB, MI, MI->getDebugLoc(), get(SystemZ::SLLG), Reg64)
227 .addReg(Reg64)
228 .addReg(0)
229 .addImm(32);
230
231 // ear <reg>, %a1
232 BuildMI(*MBB, MI, MI->getDebugLoc(), get(SystemZ::EAR), Reg32)
233 .addReg(SystemZ::A1);
234
235 // lg <reg>, 40(<reg>)
236 MI->setDesc(get(SystemZ::LG));
237 MachineInstrBuilder(MF, MI).addReg(Reg64).addImm(40).addReg(0);
238}
239
240// Emit a zero-extending move from 32-bit GPR SrcReg to 32-bit GPR
241// DestReg before MBBI in MBB. Use LowLowOpcode when both DestReg and SrcReg
242// are low registers, otherwise use RISB[LH]G. Size is the number of bits
243// taken from the low end of SrcReg (8 for LLCR, 16 for LLHR and 32 for LR).
244// KillSrc is true if this move is the last use of SrcReg.
245MachineInstrBuilder
246SystemZInstrInfo::emitGRX32Move(MachineBasicBlock &MBB,
247 MachineBasicBlock::iterator MBBI,
248 const DebugLoc &DL, unsigned DestReg,
249 unsigned SrcReg, unsigned LowLowOpcode,
250 unsigned Size, bool KillSrc,
251 bool UndefSrc) const {
252 unsigned Opcode;
253 bool DestIsHigh = SystemZ::isHighReg(DestReg);
254 bool SrcIsHigh = SystemZ::isHighReg(SrcReg);
255 if (DestIsHigh && SrcIsHigh)
256 Opcode = SystemZ::RISBHH;
257 else if (DestIsHigh && !SrcIsHigh)
258 Opcode = SystemZ::RISBHL;
259 else if (!DestIsHigh && SrcIsHigh)
260 Opcode = SystemZ::RISBLH;
261 else {
262 return BuildMI(MBB, MBBI, DL, get(LowLowOpcode), DestReg)
263 .addReg(SrcReg, getKillRegState(KillSrc) | getUndefRegState(UndefSrc));
264 }
265 unsigned Rotate = (DestIsHigh != SrcIsHigh ? 32 : 0);
266 return BuildMI(MBB, MBBI, DL, get(Opcode), DestReg)
267 .addReg(DestReg, RegState::Undef)
268 .addReg(SrcReg, getKillRegState(KillSrc) | getUndefRegState(UndefSrc))
269 .addImm(32 - Size).addImm(128 + 31).addImm(Rotate);
270}
271
272MachineInstr *SystemZInstrInfo::commuteInstructionImpl(MachineInstr &MI,
273 bool NewMI,
274 unsigned OpIdx1,
275 unsigned OpIdx2) const {
276 auto cloneIfNew = [NewMI](MachineInstr &MI) -> MachineInstr & {
277 if (NewMI)
278 return *MI.getParent()->getParent()->CloneMachineInstr(&MI);
279 return MI;
280 };
281
282 switch (MI.getOpcode()) {
283 case SystemZ::SELRMux:
284 case SystemZ::SELFHR:
285 case SystemZ::SELR:
286 case SystemZ::SELGR:
287 case SystemZ::LOCRMux:
288 case SystemZ::LOCFHR:
289 case SystemZ::LOCR:
290 case SystemZ::LOCGR: {
291 auto &WorkingMI = cloneIfNew(MI);
292 // Invert condition.
293 unsigned CCValid = WorkingMI.getOperand(3).getImm();
294 unsigned CCMask = WorkingMI.getOperand(4).getImm();
295 WorkingMI.getOperand(4).setImm(CCMask ^ CCValid);
296 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
297 OpIdx1, OpIdx2);
298 }
299 default:
300 return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
301 }
302}
303
304// If MI is a simple load or store for a frame object, return the register
305// it loads or stores and set FrameIndex to the index of the frame object.
306// Return 0 otherwise.
307//
308// Flag is SimpleBDXLoad for loads and SimpleBDXStore for stores.
309static int isSimpleMove(const MachineInstr &MI, int &FrameIndex,
310 unsigned Flag) {
311 const MCInstrDesc &MCID = MI.getDesc();
312 if ((MCID.TSFlags & Flag) && MI.getOperand(1).isFI() &&
313 MI.getOperand(2).getImm() == 0 && MI.getOperand(3).getReg() == 0) {
314 FrameIndex = MI.getOperand(1).getIndex();
315 return MI.getOperand(0).getReg();
316 }
317 return 0;
318}
319
320unsigned SystemZInstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
321 int &FrameIndex) const {
322 return isSimpleMove(MI, FrameIndex, SystemZII::SimpleBDXLoad);
323}
324
325unsigned SystemZInstrInfo::isStoreToStackSlot(const MachineInstr &MI,
326 int &FrameIndex) const {
327 return isSimpleMove(MI, FrameIndex, SystemZII::SimpleBDXStore);
328}
329
330bool SystemZInstrInfo::isStackSlotCopy(const MachineInstr &MI,
331 int &DestFrameIndex,
332 int &SrcFrameIndex) const {
333 // Check for MVC 0(Length,FI1),0(FI2)
334 const MachineFrameInfo &MFI = MI.getParent()->getParent()->getFrameInfo();
335 if (MI.getOpcode() != SystemZ::MVC || !MI.getOperand(0).isFI() ||
336 MI.getOperand(1).getImm() != 0 || !MI.getOperand(3).isFI() ||
337 MI.getOperand(4).getImm() != 0)
338 return false;
339
340 // Check that Length covers the full slots.
341 int64_t Length = MI.getOperand(2).getImm();
342 unsigned FI1 = MI.getOperand(0).getIndex();
343 unsigned FI2 = MI.getOperand(3).getIndex();
344 if (MFI.getObjectSize(FI1) != Length ||
345 MFI.getObjectSize(FI2) != Length)
346 return false;
347
348 DestFrameIndex = FI1;
349 SrcFrameIndex = FI2;
350 return true;
351}
352
353bool SystemZInstrInfo::analyzeBranch(MachineBasicBlock &MBB,
354 MachineBasicBlock *&TBB,
355 MachineBasicBlock *&FBB,
356 SmallVectorImpl<MachineOperand> &Cond,
357 bool AllowModify) const {
358 // Most of the code and comments here are boilerplate.
359
360 // Start from the bottom of the block and work up, examining the
361 // terminator instructions.
362 MachineBasicBlock::iterator I = MBB.end();
363 while (I != MBB.begin()) {
364 --I;
365 if (I->isDebugInstr())
366 continue;
367
368 // Working from the bottom, when we see a non-terminator instruction, we're
369 // done.
370 if (!isUnpredicatedTerminator(*I))
371 break;
372
373 // A terminator that isn't a branch can't easily be handled by this
374 // analysis.
375 if (!I->isBranch())
376 return true;
377
378 // Can't handle indirect branches.
379 SystemZII::Branch Branch(getBranchInfo(*I));
380 if (!Branch.hasMBBTarget())
381 return true;
382
383 // Punt on compound branches.
384 if (Branch.Type != SystemZII::BranchNormal)
385 return true;
386
387 if (Branch.CCMask == SystemZ::CCMASK_ANY) {
388 // Handle unconditional branches.
389 if (!AllowModify) {
390 TBB = Branch.getMBBTarget();
391 continue;
392 }
393
394 // If the block has any instructions after a JMP, delete them.
395 while (std::next(I) != MBB.end())
396 std::next(I)->eraseFromParent();
397
398 Cond.clear();
399 FBB = nullptr;
400
401 // Delete the JMP if it's equivalent to a fall-through.
402 if (MBB.isLayoutSuccessor(Branch.getMBBTarget())) {
403 TBB = nullptr;
404 I->eraseFromParent();
405 I = MBB.end();
406 continue;
407 }
408
409 // TBB is used to indicate the unconditinal destination.
410 TBB = Branch.getMBBTarget();
411 continue;
412 }
413
414 // Working from the bottom, handle the first conditional branch.
415 if (Cond.empty()) {
416 // FIXME: add X86-style branch swap
417 FBB = TBB;
418 TBB = Branch.getMBBTarget();
419 Cond.push_back(MachineOperand::CreateImm(Branch.CCValid));
420 Cond.push_back(MachineOperand::CreateImm(Branch.CCMask));
421 continue;
422 }
423
424 // Handle subsequent conditional branches.
425 assert(Cond.size() == 2 && TBB && "Should have seen a conditional branch")(static_cast<void> (0));
426
427 // Only handle the case where all conditional branches branch to the same
428 // destination.
429 if (TBB != Branch.getMBBTarget())
430 return true;
431
432 // If the conditions are the same, we can leave them alone.
433 unsigned OldCCValid = Cond[0].getImm();
434 unsigned OldCCMask = Cond[1].getImm();
435 if (OldCCValid == Branch.CCValid && OldCCMask == Branch.CCMask)
436 continue;
437
438 // FIXME: Try combining conditions like X86 does. Should be easy on Z!
439 return false;
440 }
441
442 return false;
443}
444
445unsigned SystemZInstrInfo::removeBranch(MachineBasicBlock &MBB,
446 int *BytesRemoved) const {
447 assert(!BytesRemoved && "code size not handled")(static_cast<void> (0));
448
449 // Most of the code and comments here are boilerplate.
450 MachineBasicBlock::iterator I = MBB.end();
451 unsigned Count = 0;
452
453 while (I != MBB.begin()) {
454 --I;
455 if (I->isDebugInstr())
456 continue;
457 if (!I->isBranch())
458 break;
459 if (!getBranchInfo(*I).hasMBBTarget())
460 break;
461 // Remove the branch.
462 I->eraseFromParent();
463 I = MBB.end();
464 ++Count;
465 }
466
467 return Count;
468}
469
470bool SystemZInstrInfo::
471reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
472 assert(Cond.size() == 2 && "Invalid condition")(static_cast<void> (0));
473 Cond[1].setImm(Cond[1].getImm() ^ Cond[0].getImm());
474 return false;
475}
476
477unsigned SystemZInstrInfo::insertBranch(MachineBasicBlock &MBB,
478 MachineBasicBlock *TBB,
479 MachineBasicBlock *FBB,
480 ArrayRef<MachineOperand> Cond,
481 const DebugLoc &DL,
482 int *BytesAdded) const {
483 // In this function we output 32-bit branches, which should always
484 // have enough range. They can be shortened and relaxed by later code
485 // in the pipeline, if desired.
486
487 // Shouldn't be a fall through.
488 assert(TBB && "insertBranch must not be told to insert a fallthrough")(static_cast<void> (0));
489 assert((Cond.size() == 2 || Cond.size() == 0) &&(static_cast<void> (0))
490 "SystemZ branch conditions have one component!")(static_cast<void> (0));
491 assert(!BytesAdded && "code size not handled")(static_cast<void> (0));
492
493 if (Cond.empty()) {
494 // Unconditional branch?
495 assert(!FBB && "Unconditional branch with multiple successors!")(static_cast<void> (0));
496 BuildMI(&MBB, DL, get(SystemZ::J)).addMBB(TBB);
497 return 1;
498 }
499
500 // Conditional branch.
501 unsigned Count = 0;
502 unsigned CCValid = Cond[0].getImm();
503 unsigned CCMask = Cond[1].getImm();
504 BuildMI(&MBB, DL, get(SystemZ::BRC))
505 .addImm(CCValid).addImm(CCMask).addMBB(TBB);
506 ++Count;
507
508 if (FBB) {
509 // Two-way Conditional branch. Insert the second branch.
510 BuildMI(&MBB, DL, get(SystemZ::J)).addMBB(FBB);
511 ++Count;
512 }
513 return Count;
514}
515
516bool SystemZInstrInfo::analyzeCompare(const MachineInstr &MI, Register &SrcReg,
517 Register &SrcReg2, int64_t &Mask,
518 int64_t &Value) const {
519 assert(MI.isCompare() && "Caller should have checked for a comparison")(static_cast<void> (0));
520
521 if (MI.getNumExplicitOperands() == 2 && MI.getOperand(0).isReg() &&
522 MI.getOperand(1).isImm()) {
523 SrcReg = MI.getOperand(0).getReg();
524 SrcReg2 = 0;
525 Value = MI.getOperand(1).getImm();
526 Mask = ~0;
527 return true;
528 }
529
530 return false;
531}
532
533bool SystemZInstrInfo::canInsertSelect(const MachineBasicBlock &MBB,
534 ArrayRef<MachineOperand> Pred,
535 Register DstReg, Register TrueReg,
536 Register FalseReg, int &CondCycles,
537 int &TrueCycles,
538 int &FalseCycles) const {
539 // Not all subtargets have LOCR instructions.
540 if (!STI.hasLoadStoreOnCond())
541 return false;
542 if (Pred.size() != 2)
543 return false;
544
545 // Check register classes.
546 const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
547 const TargetRegisterClass *RC =
548 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
549 if (!RC)
550 return false;
551
552 // We have LOCR instructions for 32 and 64 bit general purpose registers.
553 if ((STI.hasLoadStoreOnCond2() &&
554 SystemZ::GRX32BitRegClass.hasSubClassEq(RC)) ||
555 SystemZ::GR32BitRegClass.hasSubClassEq(RC) ||
556 SystemZ::GR64BitRegClass.hasSubClassEq(RC)) {
557 CondCycles = 2;
558 TrueCycles = 2;
559 FalseCycles = 2;
560 return true;
561 }
562
563 // Can't do anything else.
564 return false;
565}
566
567void SystemZInstrInfo::insertSelect(MachineBasicBlock &MBB,
568 MachineBasicBlock::iterator I,
569 const DebugLoc &DL, Register DstReg,
570 ArrayRef<MachineOperand> Pred,
571 Register TrueReg,
572 Register FalseReg) const {
573 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
574 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
575
576 assert(Pred.size() == 2 && "Invalid condition")(static_cast<void> (0));
577 unsigned CCValid = Pred[0].getImm();
578 unsigned CCMask = Pred[1].getImm();
579
580 unsigned Opc;
581 if (SystemZ::GRX32BitRegClass.hasSubClassEq(RC)) {
582 if (STI.hasMiscellaneousExtensions3())
583 Opc = SystemZ::SELRMux;
584 else if (STI.hasLoadStoreOnCond2())
585 Opc = SystemZ::LOCRMux;
586 else {
587 Opc = SystemZ::LOCR;
588 MRI.constrainRegClass(DstReg, &SystemZ::GR32BitRegClass);
589 Register TReg = MRI.createVirtualRegister(&SystemZ::GR32BitRegClass);
590 Register FReg = MRI.createVirtualRegister(&SystemZ::GR32BitRegClass);
591 BuildMI(MBB, I, DL, get(TargetOpcode::COPY), TReg).addReg(TrueReg);
592 BuildMI(MBB, I, DL, get(TargetOpcode::COPY), FReg).addReg(FalseReg);
593 TrueReg = TReg;
594 FalseReg = FReg;
595 }
596 } else if (SystemZ::GR64BitRegClass.hasSubClassEq(RC)) {
597 if (STI.hasMiscellaneousExtensions3())
598 Opc = SystemZ::SELGR;
599 else
600 Opc = SystemZ::LOCGR;
601 } else
602 llvm_unreachable("Invalid register class")__builtin_unreachable();
603
604 BuildMI(MBB, I, DL, get(Opc), DstReg)
605 .addReg(FalseReg).addReg(TrueReg)
606 .addImm(CCValid).addImm(CCMask);
607}
608
609bool SystemZInstrInfo::FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI,
610 Register Reg,
611 MachineRegisterInfo *MRI) const {
612 unsigned DefOpc = DefMI.getOpcode();
613 if (DefOpc != SystemZ::LHIMux && DefOpc != SystemZ::LHI &&
614 DefOpc != SystemZ::LGHI)
615 return false;
616 if (DefMI.getOperand(0).getReg() != Reg)
617 return false;
618 int32_t ImmVal = (int32_t)DefMI.getOperand(1).getImm();
619
620 unsigned UseOpc = UseMI.getOpcode();
621 unsigned NewUseOpc;
622 unsigned UseIdx;
623 int CommuteIdx = -1;
624 bool TieOps = false;
625 switch (UseOpc) {
626 case SystemZ::SELRMux:
627 TieOps = true;
628 LLVM_FALLTHROUGH[[gnu::fallthrough]];
629 case SystemZ::LOCRMux:
630 if (!STI.hasLoadStoreOnCond2())
631 return false;
632 NewUseOpc = SystemZ::LOCHIMux;
633 if (UseMI.getOperand(2).getReg() == Reg)
634 UseIdx = 2;
635 else if (UseMI.getOperand(1).getReg() == Reg)
636 UseIdx = 2, CommuteIdx = 1;
637 else
638 return false;
639 break;
640 case SystemZ::SELGR:
641 TieOps = true;
642 LLVM_FALLTHROUGH[[gnu::fallthrough]];
643 case SystemZ::LOCGR:
644 if (!STI.hasLoadStoreOnCond2())
645 return false;
646 NewUseOpc = SystemZ::LOCGHI;
647 if (UseMI.getOperand(2).getReg() == Reg)
648 UseIdx = 2;
649 else if (UseMI.getOperand(1).getReg() == Reg)
650 UseIdx = 2, CommuteIdx = 1;
651 else
652 return false;
653 break;
654 default:
655 return false;
656 }
657
658 if (CommuteIdx != -1)
659 if (!commuteInstruction(UseMI, false, CommuteIdx, UseIdx))
660 return false;
661
662 bool DeleteDef = MRI->hasOneNonDBGUse(Reg);
663 UseMI.setDesc(get(NewUseOpc));
664 if (TieOps)
665 UseMI.tieOperands(0, 1);
666 UseMI.getOperand(UseIdx).ChangeToImmediate(ImmVal);
667 if (DeleteDef)
668 DefMI.eraseFromParent();
669
670 return true;
671}
672
673bool SystemZInstrInfo::isPredicable(const MachineInstr &MI) const {
674 unsigned Opcode = MI.getOpcode();
675 if (Opcode == SystemZ::Return ||
676 Opcode == SystemZ::Trap ||
677 Opcode == SystemZ::CallJG ||
678 Opcode == SystemZ::CallBR)
679 return true;
680 return false;
681}
682
683bool SystemZInstrInfo::
684isProfitableToIfCvt(MachineBasicBlock &MBB,
685 unsigned NumCycles, unsigned ExtraPredCycles,
686 BranchProbability Probability) const {
687 // Avoid using conditional returns at the end of a loop (since then
688 // we'd need to emit an unconditional branch to the beginning anyway,
689 // making the loop body longer). This doesn't apply for low-probability
690 // loops (eg. compare-and-swap retry), so just decide based on branch
691 // probability instead of looping structure.
692 // However, since Compare and Trap instructions cost the same as a regular
693 // Compare instruction, we should allow the if conversion to convert this
694 // into a Conditional Compare regardless of the branch probability.
695 if (MBB.getLastNonDebugInstr()->getOpcode() != SystemZ::Trap &&
696 MBB.succ_empty() && Probability < BranchProbability(1, 8))
697 return false;
698 // For now only convert single instructions.
699 return NumCycles == 1;
700}
701
702bool SystemZInstrInfo::
703isProfitableToIfCvt(MachineBasicBlock &TMBB,
704 unsigned NumCyclesT, unsigned ExtraPredCyclesT,
705 MachineBasicBlock &FMBB,
706 unsigned NumCyclesF, unsigned ExtraPredCyclesF,
707 BranchProbability Probability) const {
708 // For now avoid converting mutually-exclusive cases.
709 return false;
710}
711
712bool SystemZInstrInfo::
713isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
714 BranchProbability Probability) const {
715 // For now only duplicate single instructions.
716 return NumCycles == 1;
717}
718
719bool SystemZInstrInfo::PredicateInstruction(
720 MachineInstr &MI, ArrayRef<MachineOperand> Pred) const {
721 assert(Pred.size() == 2 && "Invalid condition")(static_cast<void> (0));
722 unsigned CCValid = Pred[0].getImm();
723 unsigned CCMask = Pred[1].getImm();
724 assert(CCMask > 0 && CCMask < 15 && "Invalid predicate")(static_cast<void> (0));
725 unsigned Opcode = MI.getOpcode();
726 if (Opcode == SystemZ::Trap) {
727 MI.setDesc(get(SystemZ::CondTrap));
728 MachineInstrBuilder(*MI.getParent()->getParent(), MI)
729 .addImm(CCValid).addImm(CCMask)
730 .addReg(SystemZ::CC, RegState::Implicit);
731 return true;
732 }
733 if (Opcode == SystemZ::Return) {
734 MI.setDesc(get(SystemZ::CondReturn));
735 MachineInstrBuilder(*MI.getParent()->getParent(), MI)
736 .addImm(CCValid).addImm(CCMask)
737 .addReg(SystemZ::CC, RegState::Implicit);
738 return true;
739 }
740 if (Opcode == SystemZ::CallJG) {
741 MachineOperand FirstOp = MI.getOperand(0);
742 const uint32_t *RegMask = MI.getOperand(1).getRegMask();
743 MI.RemoveOperand(1);
744 MI.RemoveOperand(0);
745 MI.setDesc(get(SystemZ::CallBRCL));
746 MachineInstrBuilder(*MI.getParent()->getParent(), MI)
747 .addImm(CCValid)
748 .addImm(CCMask)
749 .add(FirstOp)
750 .addRegMask(RegMask)
751 .addReg(SystemZ::CC, RegState::Implicit);
752 return true;
753 }
754 if (Opcode == SystemZ::CallBR) {
755 MachineOperand Target = MI.getOperand(0);
756 const uint32_t *RegMask = MI.getOperand(1).getRegMask();
757 MI.RemoveOperand(1);
758 MI.RemoveOperand(0);
759 MI.setDesc(get(SystemZ::CallBCR));
760 MachineInstrBuilder(*MI.getParent()->getParent(), MI)
761 .addImm(CCValid).addImm(CCMask)
762 .add(Target)
763 .addRegMask(RegMask)
764 .addReg(SystemZ::CC, RegState::Implicit);
765 return true;
766 }
767 return false;
768}
769
770void SystemZInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
771 MachineBasicBlock::iterator MBBI,
772 const DebugLoc &DL, MCRegister DestReg,
773 MCRegister SrcReg, bool KillSrc) const {
774 // Split 128-bit GPR moves into two 64-bit moves. Add implicit uses of the
775 // super register in case one of the subregs is undefined.
776 // This handles ADDR128 too.
777 if (SystemZ::GR128BitRegClass.contains(DestReg, SrcReg)) {
778 copyPhysReg(MBB, MBBI, DL, RI.getSubReg(DestReg, SystemZ::subreg_h64),
779 RI.getSubReg(SrcReg, SystemZ::subreg_h64), KillSrc);
780 MachineInstrBuilder(*MBB.getParent(), std::prev(MBBI))
781 .addReg(SrcReg, RegState::Implicit);
782 copyPhysReg(MBB, MBBI, DL, RI.getSubReg(DestReg, SystemZ::subreg_l64),
783 RI.getSubReg(SrcReg, SystemZ::subreg_l64), KillSrc);
784 MachineInstrBuilder(*MBB.getParent(), std::prev(MBBI))
785 .addReg(SrcReg, (getKillRegState(KillSrc) | RegState::Implicit));
786 return;
787 }
788
789 if (SystemZ::GRX32BitRegClass.contains(DestReg, SrcReg)) {
790 emitGRX32Move(MBB, MBBI, DL, DestReg, SrcReg, SystemZ::LR, 32, KillSrc,
791 false);
792 return;
793 }
794
795 // Move 128-bit floating-point values between VR128 and FP128.
796 if (SystemZ::VR128BitRegClass.contains(DestReg) &&
797 SystemZ::FP128BitRegClass.contains(SrcReg)) {
798 MCRegister SrcRegHi =
799 RI.getMatchingSuperReg(RI.getSubReg(SrcReg, SystemZ::subreg_h64),
800 SystemZ::subreg_h64, &SystemZ::VR128BitRegClass);
801 MCRegister SrcRegLo =
802 RI.getMatchingSuperReg(RI.getSubReg(SrcReg, SystemZ::subreg_l64),
803 SystemZ::subreg_h64, &SystemZ::VR128BitRegClass);
804
805 BuildMI(MBB, MBBI, DL, get(SystemZ::VMRHG), DestReg)
806 .addReg(SrcRegHi, getKillRegState(KillSrc))
807 .addReg(SrcRegLo, getKillRegState(KillSrc));
808 return;
809 }
810 if (SystemZ::FP128BitRegClass.contains(DestReg) &&
811 SystemZ::VR128BitRegClass.contains(SrcReg)) {
812 MCRegister DestRegHi =
813 RI.getMatchingSuperReg(RI.getSubReg(DestReg, SystemZ::subreg_h64),
814 SystemZ::subreg_h64, &SystemZ::VR128BitRegClass);
815 MCRegister DestRegLo =
816 RI.getMatchingSuperReg(RI.getSubReg(DestReg, SystemZ::subreg_l64),
817 SystemZ::subreg_h64, &SystemZ::VR128BitRegClass);
818
819 if (DestRegHi != SrcReg)
820 copyPhysReg(MBB, MBBI, DL, DestRegHi, SrcReg, false);
821 BuildMI(MBB, MBBI, DL, get(SystemZ::VREPG), DestRegLo)
822 .addReg(SrcReg, getKillRegState(KillSrc)).addImm(1);
823 return;
824 }
825
826 // Move CC value from a GR32.
827 if (DestReg == SystemZ::CC) {
828 unsigned Opcode =
829 SystemZ::GR32BitRegClass.contains(SrcReg) ? SystemZ::TMLH : SystemZ::TMHH;
830 BuildMI(MBB, MBBI, DL, get(Opcode))
831 .addReg(SrcReg, getKillRegState(KillSrc))
832 .addImm(3 << (SystemZ::IPM_CC - 16));
833 return;
834 }
835
836 // Everything else needs only one instruction.
837 unsigned Opcode;
838 if (SystemZ::GR64BitRegClass.contains(DestReg, SrcReg))
839 Opcode = SystemZ::LGR;
840 else if (SystemZ::FP32BitRegClass.contains(DestReg, SrcReg))
841 // For z13 we prefer LDR over LER to avoid partial register dependencies.
842 Opcode = STI.hasVector() ? SystemZ::LDR32 : SystemZ::LER;
843 else if (SystemZ::FP64BitRegClass.contains(DestReg, SrcReg))
844 Opcode = SystemZ::LDR;
845 else if (SystemZ::FP128BitRegClass.contains(DestReg, SrcReg))
846 Opcode = SystemZ::LXR;
847 else if (SystemZ::VR32BitRegClass.contains(DestReg, SrcReg))
848 Opcode = SystemZ::VLR32;
849 else if (SystemZ::VR64BitRegClass.contains(DestReg, SrcReg))
850 Opcode = SystemZ::VLR64;
851 else if (SystemZ::VR128BitRegClass.contains(DestReg, SrcReg))
852 Opcode = SystemZ::VLR;
853 else if (SystemZ::AR32BitRegClass.contains(DestReg, SrcReg))
854 Opcode = SystemZ::CPYA;
855 else
856 llvm_unreachable("Impossible reg-to-reg copy")__builtin_unreachable();
857
858 BuildMI(MBB, MBBI, DL, get(Opcode), DestReg)
859 .addReg(SrcReg, getKillRegState(KillSrc));
860}
861
862void SystemZInstrInfo::storeRegToStackSlot(
863 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg,
864 bool isKill, int FrameIdx, const TargetRegisterClass *RC,
865 const TargetRegisterInfo *TRI) const {
866 DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
867
868 // Callers may expect a single instruction, so keep 128-bit moves
869 // together for now and lower them after register allocation.
870 unsigned LoadOpcode, StoreOpcode;
871 getLoadStoreOpcodes(RC, LoadOpcode, StoreOpcode);
872 addFrameReference(BuildMI(MBB, MBBI, DL, get(StoreOpcode))
873 .addReg(SrcReg, getKillRegState(isKill)),
874 FrameIdx);
875}
876
877void SystemZInstrInfo::loadRegFromStackSlot(
878 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DestReg,
879 int FrameIdx, const TargetRegisterClass *RC,
880 const TargetRegisterInfo *TRI) const {
881 DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
882
883 // Callers may expect a single instruction, so keep 128-bit moves
884 // together for now and lower them after register allocation.
885 unsigned LoadOpcode, StoreOpcode;
886 getLoadStoreOpcodes(RC, LoadOpcode, StoreOpcode);
887 addFrameReference(BuildMI(MBB, MBBI, DL, get(LoadOpcode), DestReg),
888 FrameIdx);
889}
890
891// Return true if MI is a simple load or store with a 12-bit displacement
892// and no index. Flag is SimpleBDXLoad for loads and SimpleBDXStore for stores.
893static bool isSimpleBD12Move(const MachineInstr *MI, unsigned Flag) {
894 const MCInstrDesc &MCID = MI->getDesc();
895 return ((MCID.TSFlags & Flag) &&
896 isUInt<12>(MI->getOperand(2).getImm()) &&
897 MI->getOperand(3).getReg() == 0);
898}
899
900namespace {
901
902struct LogicOp {
903 LogicOp() = default;
904 LogicOp(unsigned regSize, unsigned immLSB, unsigned immSize)
905 : RegSize(regSize), ImmLSB(immLSB), ImmSize(immSize) {}
906
907 explicit operator bool() const { return RegSize; }
908
909 unsigned RegSize = 0;
910 unsigned ImmLSB = 0;
911 unsigned ImmSize = 0;
912};
913
914} // end anonymous namespace
915
916static LogicOp interpretAndImmediate(unsigned Opcode) {
917 switch (Opcode) {
918 case SystemZ::NILMux: return LogicOp(32, 0, 16);
919 case SystemZ::NIHMux: return LogicOp(32, 16, 16);
920 case SystemZ::NILL64: return LogicOp(64, 0, 16);
921 case SystemZ::NILH64: return LogicOp(64, 16, 16);
922 case SystemZ::NIHL64: return LogicOp(64, 32, 16);
923 case SystemZ::NIHH64: return LogicOp(64, 48, 16);
924 case SystemZ::NIFMux: return LogicOp(32, 0, 32);
925 case SystemZ::NILF64: return LogicOp(64, 0, 32);
926 case SystemZ::NIHF64: return LogicOp(64, 32, 32);
927 default: return LogicOp();
928 }
929}
930
931static void transferDeadCC(MachineInstr *OldMI, MachineInstr *NewMI) {
932 if (OldMI->registerDefIsDead(SystemZ::CC)) {
933 MachineOperand *CCDef = NewMI->findRegisterDefOperand(SystemZ::CC);
934 if (CCDef != nullptr)
935 CCDef->setIsDead(true);
936 }
937}
938
939static void transferMIFlag(MachineInstr *OldMI, MachineInstr *NewMI,
940 MachineInstr::MIFlag Flag) {
941 if (OldMI->getFlag(Flag))
942 NewMI->setFlag(Flag);
943}
944
945MachineInstr *SystemZInstrInfo::convertToThreeAddress(
946 MachineFunction::iterator &MFI, MachineInstr &MI, LiveVariables *LV) const {
947 MachineBasicBlock *MBB = MI.getParent();
948
949 // Try to convert an AND into an RISBG-type instruction.
950 // TODO: It might be beneficial to select RISBG and shorten to AND instead.
951 if (LogicOp And = interpretAndImmediate(MI.getOpcode())) {
1
Taking true branch
952 uint64_t Imm = MI.getOperand(2).getImm() << And.ImmLSB;
953 // AND IMMEDIATE leaves the other bits of the register unchanged.
954 Imm |= allOnes(And.RegSize) & ~(allOnes(And.ImmSize) << And.ImmLSB);
955 unsigned Start, End;
956 if (isRxSBGMask(Imm, And.RegSize, Start, End)) {
2
Calling 'SystemZInstrInfo::isRxSBGMask'
957 unsigned NewOpcode;
958 if (And.RegSize == 64) {
959 NewOpcode = SystemZ::RISBG;
960 // Prefer RISBGN if available, since it does not clobber CC.
961 if (STI.hasMiscellaneousExtensions())
962 NewOpcode = SystemZ::RISBGN;
963 } else {
964 NewOpcode = SystemZ::RISBMux;
965 Start &= 31;
966 End &= 31;
967 }
968 MachineOperand &Dest = MI.getOperand(0);
969 MachineOperand &Src = MI.getOperand(1);
970 MachineInstrBuilder MIB =
971 BuildMI(*MBB, MI, MI.getDebugLoc(), get(NewOpcode))
972 .add(Dest)
973 .addReg(0)
974 .addReg(Src.getReg(), getKillRegState(Src.isKill()),
975 Src.getSubReg())
976 .addImm(Start)
977 .addImm(End + 128)
978 .addImm(0);
979 if (LV) {
980 unsigned NumOps = MI.getNumOperands();
981 for (unsigned I = 1; I < NumOps; ++I) {
982 MachineOperand &Op = MI.getOperand(I);
983 if (Op.isReg() && Op.isKill())
984 LV->replaceKillInstruction(Op.getReg(), MI, *MIB);
985 }
986 }
987 transferDeadCC(&MI, MIB);
988 return MIB;
989 }
990 }
991 return nullptr;
992}
993
994MachineInstr *SystemZInstrInfo::foldMemoryOperandImpl(
995 MachineFunction &MF, MachineInstr &MI, ArrayRef<unsigned> Ops,
996 MachineBasicBlock::iterator InsertPt, int FrameIndex,
997 LiveIntervals *LIS, VirtRegMap *VRM) const {
998 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
999 MachineRegisterInfo &MRI = MF.getRegInfo();
1000 const MachineFrameInfo &MFI = MF.getFrameInfo();
1001 unsigned Size = MFI.getObjectSize(FrameIndex);
1002 unsigned Opcode = MI.getOpcode();
1003
1004 // Check CC liveness if new instruction introduces a dead def of CC.
1005 MCRegUnitIterator CCUnit(MCRegister::from(SystemZ::CC), TRI);
1006 SlotIndex MISlot = SlotIndex();
1007 LiveRange *CCLiveRange = nullptr;
1008 bool CCLiveAtMI = true;
1009 if (LIS) {
1010 MISlot = LIS->getSlotIndexes()->getInstructionIndex(MI).getRegSlot();
1011 CCLiveRange = &LIS->getRegUnit(*CCUnit);
1012 CCLiveAtMI = CCLiveRange->liveAt(MISlot);
1013 }
1014 ++CCUnit;
1015 assert(!CCUnit.isValid() && "CC only has one reg unit.")(static_cast<void> (0));
1016
1017 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
1018 if (!CCLiveAtMI && (Opcode == SystemZ::LA || Opcode == SystemZ::LAY) &&
1019 isInt<8>(MI.getOperand(2).getImm()) && !MI.getOperand(3).getReg()) {
1020 // LA(Y) %reg, CONST(%reg) -> AGSI %mem, CONST
1021 MachineInstr *BuiltMI = BuildMI(*InsertPt->getParent(), InsertPt,
1022 MI.getDebugLoc(), get(SystemZ::AGSI))
1023 .addFrameIndex(FrameIndex)
1024 .addImm(0)
1025 .addImm(MI.getOperand(2).getImm());
1026 BuiltMI->findRegisterDefOperand(SystemZ::CC)->setIsDead(true);
1027 CCLiveRange->createDeadDef(MISlot, LIS->getVNInfoAllocator());
1028 return BuiltMI;
1029 }
1030 return nullptr;
1031 }
1032
1033 // All other cases require a single operand.
1034 if (Ops.size() != 1)
1035 return nullptr;
1036
1037 unsigned OpNum = Ops[0];
1038 assert(Size * 8 ==(static_cast<void> (0))
1039 TRI->getRegSizeInBits(*MF.getRegInfo()(static_cast<void> (0))
1040 .getRegClass(MI.getOperand(OpNum).getReg())) &&(static_cast<void> (0))
1041 "Invalid size combination")(static_cast<void> (0));
1042
1043 if ((Opcode == SystemZ::AHI || Opcode == SystemZ::AGHI) && OpNum == 0 &&
1044 isInt<8>(MI.getOperand(2).getImm())) {
1045 // A(G)HI %reg, CONST -> A(G)SI %mem, CONST
1046 Opcode = (Opcode == SystemZ::AHI ? SystemZ::ASI : SystemZ::AGSI);
1047 MachineInstr *BuiltMI =
1048 BuildMI(*InsertPt->getParent(), InsertPt, MI.getDebugLoc(), get(Opcode))
1049 .addFrameIndex(FrameIndex)
1050 .addImm(0)
1051 .addImm(MI.getOperand(2).getImm());
1052 transferDeadCC(&MI, BuiltMI);
1053 transferMIFlag(&MI, BuiltMI, MachineInstr::NoSWrap);
1054 return BuiltMI;
1055 }
1056
1057 if ((Opcode == SystemZ::ALFI && OpNum == 0 &&
1058 isInt<8>((int32_t)MI.getOperand(2).getImm())) ||
1059 (Opcode == SystemZ::ALGFI && OpNum == 0 &&
1060 isInt<8>((int64_t)MI.getOperand(2).getImm()))) {
1061 // AL(G)FI %reg, CONST -> AL(G)SI %mem, CONST
1062 Opcode = (Opcode == SystemZ::ALFI ? SystemZ::ALSI : SystemZ::ALGSI);
1063 MachineInstr *BuiltMI =
1064 BuildMI(*InsertPt->getParent(), InsertPt, MI.getDebugLoc(), get(Opcode))
1065 .addFrameIndex(FrameIndex)
1066 .addImm(0)
1067 .addImm((int8_t)MI.getOperand(2).getImm());
1068 transferDeadCC(&MI, BuiltMI);
1069 return BuiltMI;
1070 }
1071
1072 if ((Opcode == SystemZ::SLFI && OpNum == 0 &&
1073 isInt<8>((int32_t)-MI.getOperand(2).getImm())) ||
1074 (Opcode == SystemZ::SLGFI && OpNum == 0 &&
1075 isInt<8>((int64_t)-MI.getOperand(2).getImm()))) {
1076 // SL(G)FI %reg, CONST -> AL(G)SI %mem, -CONST
1077 Opcode = (Opcode == SystemZ::SLFI ? SystemZ::ALSI : SystemZ::ALGSI);
1078 MachineInstr *BuiltMI =
1079 BuildMI(*InsertPt->getParent(), InsertPt, MI.getDebugLoc(), get(Opcode))
1080 .addFrameIndex(FrameIndex)
1081 .addImm(0)
1082 .addImm((int8_t)-MI.getOperand(2).getImm());
1083 transferDeadCC(&MI, BuiltMI);
1084 return BuiltMI;
1085 }
1086
1087 unsigned MemImmOpc = 0;
1088 switch (Opcode) {
1089 case SystemZ::LHIMux:
1090 case SystemZ::LHI: MemImmOpc = SystemZ::MVHI; break;
1091 case SystemZ::LGHI: MemImmOpc = SystemZ::MVGHI; break;
1092 case SystemZ::CHIMux:
1093 case SystemZ::CHI: MemImmOpc = SystemZ::CHSI; break;
1094 case SystemZ::CGHI: MemImmOpc = SystemZ::CGHSI; break;
1095 case SystemZ::CLFIMux:
1096 case SystemZ::CLFI:
1097 if (isUInt<16>(MI.getOperand(1).getImm()))
1098 MemImmOpc = SystemZ::CLFHSI;
1099 break;
1100 case SystemZ::CLGFI:
1101 if (isUInt<16>(MI.getOperand(1).getImm()))
1102 MemImmOpc = SystemZ::CLGHSI;
1103 break;
1104 default: break;
1105 }
1106 if (MemImmOpc)
1107 return BuildMI(*InsertPt->getParent(), InsertPt, MI.getDebugLoc(),
1108 get(MemImmOpc))
1109 .addFrameIndex(FrameIndex)
1110 .addImm(0)
1111 .addImm(MI.getOperand(1).getImm());
1112
1113 if (Opcode == SystemZ::LGDR || Opcode == SystemZ::LDGR) {
1114 bool Op0IsGPR = (Opcode == SystemZ::LGDR);
1115 bool Op1IsGPR = (Opcode == SystemZ::LDGR);
1116 // If we're spilling the destination of an LDGR or LGDR, store the
1117 // source register instead.
1118 if (OpNum == 0) {
1119 unsigned StoreOpcode = Op1IsGPR ? SystemZ::STG : SystemZ::STD;
1120 return BuildMI(*InsertPt->getParent(), InsertPt, MI.getDebugLoc(),
1121 get(StoreOpcode))
1122 .add(MI.getOperand(1))
1123 .addFrameIndex(FrameIndex)
1124 .addImm(0)
1125 .addReg(0);
1126 }
1127 // If we're spilling the source of an LDGR or LGDR, load the
1128 // destination register instead.
1129 if (OpNum == 1) {
1130 unsigned LoadOpcode = Op0IsGPR ? SystemZ::LG : SystemZ::LD;
1131 return BuildMI(*InsertPt->getParent(), InsertPt, MI.getDebugLoc(),
1132 get(LoadOpcode))
1133 .add(MI.getOperand(0))
1134 .addFrameIndex(FrameIndex)
1135 .addImm(0)
1136 .addReg(0);
1137 }
1138 }
1139
1140 // Look for cases where the source of a simple store or the destination
1141 // of a simple load is being spilled. Try to use MVC instead.
1142 //
1143 // Although MVC is in practice a fast choice in these cases, it is still
1144 // logically a bytewise copy. This means that we cannot use it if the
1145 // load or store is volatile. We also wouldn't be able to use MVC if
1146 // the two memories partially overlap, but that case cannot occur here,
1147 // because we know that one of the memories is a full frame index.
1148 //
1149 // For performance reasons, we also want to avoid using MVC if the addresses
1150 // might be equal. We don't worry about that case here, because spill slot
1151 // coloring happens later, and because we have special code to remove
1152 // MVCs that turn out to be redundant.
1153 if (OpNum == 0 && MI.hasOneMemOperand()) {
1154 MachineMemOperand *MMO = *MI.memoperands_begin();
1155 if (MMO->getSize() == Size && !MMO->isVolatile() && !MMO->isAtomic()) {
1156 // Handle conversion of loads.
1157 if (isSimpleBD12Move(&MI, SystemZII::SimpleBDXLoad)) {
1158 return BuildMI(*InsertPt->getParent(), InsertPt, MI.getDebugLoc(),
1159 get(SystemZ::MVC))
1160 .addFrameIndex(FrameIndex)
1161 .addImm(0)
1162 .addImm(Size)
1163 .add(MI.getOperand(1))
1164 .addImm(MI.getOperand(2).getImm())
1165 .addMemOperand(MMO);
1166 }
1167 // Handle conversion of stores.
1168 if (isSimpleBD12Move(&MI, SystemZII::SimpleBDXStore)) {
1169 return BuildMI(*InsertPt->getParent(), InsertPt, MI.getDebugLoc(),
1170 get(SystemZ::MVC))
1171 .add(MI.getOperand(1))
1172 .addImm(MI.getOperand(2).getImm())
1173 .addImm(Size)
1174 .addFrameIndex(FrameIndex)
1175 .addImm(0)
1176 .addMemOperand(MMO);
1177 }
1178 }
1179 }
1180
1181 // If the spilled operand is the final one or the instruction is
1182 // commutable, try to change <INSN>R into <INSN>. Don't introduce a def of
1183 // CC if it is live and MI does not define it.
1184 unsigned NumOps = MI.getNumExplicitOperands();
1185 int MemOpcode = SystemZ::getMemOpcode(Opcode);
1186 if (MemOpcode == -1 ||
1187 (CCLiveAtMI && !MI.definesRegister(SystemZ::CC) &&
1188 get(MemOpcode).hasImplicitDefOfPhysReg(SystemZ::CC)))
1189 return nullptr;
1190
1191 // Check if all other vregs have a usable allocation in the case of vector
1192 // to FP conversion.
1193 const MCInstrDesc &MCID = MI.getDesc();
1194 for (unsigned I = 0, E = MCID.getNumOperands(); I != E; ++I) {
1195 const MCOperandInfo &MCOI = MCID.OpInfo[I];
1196 if (MCOI.OperandType != MCOI::OPERAND_REGISTER || I == OpNum)
1197 continue;
1198 const TargetRegisterClass *RC = TRI->getRegClass(MCOI.RegClass);
1199 if (RC == &SystemZ::VR32BitRegClass || RC == &SystemZ::VR64BitRegClass) {
1200 Register Reg = MI.getOperand(I).getReg();
1201 Register PhysReg = Register::isVirtualRegister(Reg)
1202 ? (VRM ? Register(VRM->getPhys(Reg)) : Register())
1203 : Reg;
1204 if (!PhysReg ||
1205 !(SystemZ::FP32BitRegClass.contains(PhysReg) ||
1206 SystemZ::FP64BitRegClass.contains(PhysReg) ||
1207 SystemZ::VF128BitRegClass.contains(PhysReg)))
1208 return nullptr;
1209 }
1210 }
1211 // Fused multiply and add/sub need to have the same dst and accumulator reg.
1212 bool FusedFPOp = (Opcode == SystemZ::WFMADB || Opcode == SystemZ::WFMASB ||
1213 Opcode == SystemZ::WFMSDB || Opcode == SystemZ::WFMSSB);
1214 if (FusedFPOp) {
1215 Register DstReg = VRM->getPhys(MI.getOperand(0).getReg());
1216 Register AccReg = VRM->getPhys(MI.getOperand(3).getReg());
1217 if (OpNum == 0 || OpNum == 3 || DstReg != AccReg)
1218 return nullptr;
1219 }
1220
1221 // Try to swap compare operands if possible.
1222 bool NeedsCommute = false;
1223 if ((MI.getOpcode() == SystemZ::CR || MI.getOpcode() == SystemZ::CGR ||
1224 MI.getOpcode() == SystemZ::CLR || MI.getOpcode() == SystemZ::CLGR ||
1225 MI.getOpcode() == SystemZ::WFCDB || MI.getOpcode() == SystemZ::WFCSB ||
1226 MI.getOpcode() == SystemZ::WFKDB || MI.getOpcode() == SystemZ::WFKSB) &&
1227 OpNum == 0 && prepareCompareSwapOperands(MI))
1228 NeedsCommute = true;
1229
1230 bool CCOperands = false;
1231 if (MI.getOpcode() == SystemZ::LOCRMux || MI.getOpcode() == SystemZ::LOCGR ||
1232 MI.getOpcode() == SystemZ::SELRMux || MI.getOpcode() == SystemZ::SELGR) {
1233 assert(MI.getNumOperands() == 6 && NumOps == 5 &&(static_cast<void> (0))
1234 "LOCR/SELR instruction operands corrupt?")(static_cast<void> (0));
1235 NumOps -= 2;
1236 CCOperands = true;
1237 }
1238
1239 // See if this is a 3-address instruction that is convertible to 2-address
1240 // and suitable for folding below. Only try this with virtual registers
1241 // and a provided VRM (during regalloc).
1242 if (NumOps == 3 && SystemZ::getTargetMemOpcode(MemOpcode) != -1) {
1243 if (VRM == nullptr)
1244 return nullptr;
1245 else {
1246 Register DstReg = MI.getOperand(0).getReg();
1247 Register DstPhys =
1248 (Register::isVirtualRegister(DstReg) ? Register(VRM->getPhys(DstReg))
1249 : DstReg);
1250 Register SrcReg = (OpNum == 2 ? MI.getOperand(1).getReg()
1251 : ((OpNum == 1 && MI.isCommutable())
1252 ? MI.getOperand(2).getReg()
1253 : Register()));
1254 if (DstPhys && !SystemZ::GRH32BitRegClass.contains(DstPhys) && SrcReg &&
1255 Register::isVirtualRegister(SrcReg) &&
1256 DstPhys == VRM->getPhys(SrcReg))
1257 NeedsCommute = (OpNum == 1);
1258 else
1259 return nullptr;
1260 }
1261 }
1262
1263 if ((OpNum == NumOps - 1) || NeedsCommute || FusedFPOp) {
1264 const MCInstrDesc &MemDesc = get(MemOpcode);
1265 uint64_t AccessBytes = SystemZII::getAccessSize(MemDesc.TSFlags);
1266 assert(AccessBytes != 0 && "Size of access should be known")(static_cast<void> (0));
1267 assert(AccessBytes <= Size && "Access outside the frame index")(static_cast<void> (0));
1268 uint64_t Offset = Size - AccessBytes;
1269 MachineInstrBuilder MIB = BuildMI(*InsertPt->getParent(), InsertPt,
1270 MI.getDebugLoc(), get(MemOpcode));
1271 if (MI.isCompare()) {
1272 assert(NumOps == 2 && "Expected 2 register operands for a compare.")(static_cast<void> (0));
1273 MIB.add(MI.getOperand(NeedsCommute ? 1 : 0));
1274 }
1275 else if (FusedFPOp) {
1276 MIB.add(MI.getOperand(0));
1277 MIB.add(MI.getOperand(3));
1278 MIB.add(MI.getOperand(OpNum == 1 ? 2 : 1));
1279 }
1280 else {
1281 MIB.add(MI.getOperand(0));
1282 if (NeedsCommute)
1283 MIB.add(MI.getOperand(2));
1284 else
1285 for (unsigned I = 1; I < OpNum; ++I)
1286 MIB.add(MI.getOperand(I));
1287 }
1288 MIB.addFrameIndex(FrameIndex).addImm(Offset);
1289 if (MemDesc.TSFlags & SystemZII::HasIndex)
1290 MIB.addReg(0);
1291 if (CCOperands) {
1292 unsigned CCValid = MI.getOperand(NumOps).getImm();
1293 unsigned CCMask = MI.getOperand(NumOps + 1).getImm();
1294 MIB.addImm(CCValid);
1295 MIB.addImm(NeedsCommute ? CCMask ^ CCValid : CCMask);
1296 }
1297 if (MIB->definesRegister(SystemZ::CC) &&
1298 (!MI.definesRegister(SystemZ::CC) ||
1299 MI.registerDefIsDead(SystemZ::CC))) {
1300 MIB->addRegisterDead(SystemZ::CC, TRI);
1301 if (CCLiveRange)
1302 CCLiveRange->createDeadDef(MISlot, LIS->getVNInfoAllocator());
1303 }
1304 // Constrain the register classes if converted from a vector opcode. The
1305 // allocated regs are in an FP reg-class per previous check above.
1306 for (const MachineOperand &MO : MIB->operands())
1307 if (MO.isReg() && Register::isVirtualRegister(MO.getReg())) {
1308 unsigned Reg = MO.getReg();
1309 if (MRI.getRegClass(Reg) == &SystemZ::VR32BitRegClass)
1310 MRI.setRegClass(Reg, &SystemZ::FP32BitRegClass);
1311 else if (MRI.getRegClass(Reg) == &SystemZ::VR64BitRegClass)
1312 MRI.setRegClass(Reg, &SystemZ::FP64BitRegClass);
1313 else if (MRI.getRegClass(Reg) == &SystemZ::VR128BitRegClass)
1314 MRI.setRegClass(Reg, &SystemZ::VF128BitRegClass);
1315 }
1316
1317 transferDeadCC(&MI, MIB);
1318 transferMIFlag(&MI, MIB, MachineInstr::NoSWrap);
1319 transferMIFlag(&MI, MIB, MachineInstr::NoFPExcept);
1320 return MIB;
1321 }
1322
1323 return nullptr;
1324}
1325
1326MachineInstr *SystemZInstrInfo::foldMemoryOperandImpl(
1327 MachineFunction &MF, MachineInstr &MI, ArrayRef<unsigned> Ops,
1328 MachineBasicBlock::iterator InsertPt, MachineInstr &LoadMI,
1329 LiveIntervals *LIS) const {
1330 return nullptr;
1331}
1332
1333bool SystemZInstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
1334 switch (MI.getOpcode()) {
1335 case SystemZ::L128:
1336 splitMove(MI, SystemZ::LG);
1337 return true;
1338
1339 case SystemZ::ST128:
1340 splitMove(MI, SystemZ::STG);
1341 return true;
1342
1343 case SystemZ::LX:
1344 splitMove(MI, SystemZ::LD);
1345 return true;
1346
1347 case SystemZ::STX:
1348 splitMove(MI, SystemZ::STD);
1349 return true;
1350
1351 case SystemZ::LBMux:
1352 expandRXYPseudo(MI, SystemZ::LB, SystemZ::LBH);
1353 return true;
1354
1355 case SystemZ::LHMux:
1356 expandRXYPseudo(MI, SystemZ::LH, SystemZ::LHH);
1357 return true;
1358
1359 case SystemZ::LLCRMux:
1360 expandZExtPseudo(MI, SystemZ::LLCR, 8);
1361 return true;
1362
1363 case SystemZ::LLHRMux:
1364 expandZExtPseudo(MI, SystemZ::LLHR, 16);
1365 return true;
1366
1367 case SystemZ::LLCMux:
1368 expandRXYPseudo(MI, SystemZ::LLC, SystemZ::LLCH);
1369 return true;
1370
1371 case SystemZ::LLHMux:
1372 expandRXYPseudo(MI, SystemZ::LLH, SystemZ::LLHH);
1373 return true;
1374
1375 case SystemZ::LMux:
1376 expandRXYPseudo(MI, SystemZ::L, SystemZ::LFH);
1377 return true;
1378
1379 case SystemZ::LOCMux:
1380 expandLOCPseudo(MI, SystemZ::LOC, SystemZ::LOCFH);
1381 return true;
1382
1383 case SystemZ::LOCHIMux:
1384 expandLOCPseudo(MI, SystemZ::LOCHI, SystemZ::LOCHHI);
1385 return true;
1386
1387 case SystemZ::STCMux:
1388 expandRXYPseudo(MI, SystemZ::STC, SystemZ::STCH);
1389 return true;
1390
1391 case SystemZ::STHMux:
1392 expandRXYPseudo(MI, SystemZ::STH, SystemZ::STHH);
1393 return true;
1394
1395 case SystemZ::STMux:
1396 expandRXYPseudo(MI, SystemZ::ST, SystemZ::STFH);
1397 return true;
1398
1399 case SystemZ::STOCMux:
1400 expandLOCPseudo(MI, SystemZ::STOC, SystemZ::STOCFH);
1401 return true;
1402
1403 case SystemZ::LHIMux:
1404 expandRIPseudo(MI, SystemZ::LHI, SystemZ::IIHF, true);
1405 return true;
1406
1407 case SystemZ::IIFMux:
1408 expandRIPseudo(MI, SystemZ::IILF, SystemZ::IIHF, false);
1409 return true;
1410
1411 case SystemZ::IILMux:
1412 expandRIPseudo(MI, SystemZ::IILL, SystemZ::IIHL, false);
1413 return true;
1414
1415 case SystemZ::IIHMux:
1416 expandRIPseudo(MI, SystemZ::IILH, SystemZ::IIHH, false);
1417 return true;
1418
1419 case SystemZ::NIFMux:
1420 expandRIPseudo(MI, SystemZ::NILF, SystemZ::NIHF, false);
1421 return true;
1422
1423 case SystemZ::NILMux:
1424 expandRIPseudo(MI, SystemZ::NILL, SystemZ::NIHL, false);
1425 return true;
1426
1427 case SystemZ::NIHMux:
1428 expandRIPseudo(MI, SystemZ::NILH, SystemZ::NIHH, false);
1429 return true;
1430
1431 case SystemZ::OIFMux:
1432 expandRIPseudo(MI, SystemZ::OILF, SystemZ::OIHF, false);
1433 return true;
1434
1435 case SystemZ::OILMux:
1436 expandRIPseudo(MI, SystemZ::OILL, SystemZ::OIHL, false);
1437 return true;
1438
1439 case SystemZ::OIHMux:
1440 expandRIPseudo(MI, SystemZ::OILH, SystemZ::OIHH, false);
1441 return true;
1442
1443 case SystemZ::XIFMux:
1444 expandRIPseudo(MI, SystemZ::XILF, SystemZ::XIHF, false);
1445 return true;
1446
1447 case SystemZ::TMLMux:
1448 expandRIPseudo(MI, SystemZ::TMLL, SystemZ::TMHL, false);
1449 return true;
1450
1451 case SystemZ::TMHMux:
1452 expandRIPseudo(MI, SystemZ::TMLH, SystemZ::TMHH, false);
1453 return true;
1454
1455 case SystemZ::AHIMux:
1456 expandRIPseudo(MI, SystemZ::AHI, SystemZ::AIH, false);
1457 return true;
1458
1459 case SystemZ::AHIMuxK:
1460 expandRIEPseudo(MI, SystemZ::AHI, SystemZ::AHIK, SystemZ::AIH);
1461 return true;
1462
1463 case SystemZ::AFIMux:
1464 expandRIPseudo(MI, SystemZ::AFI, SystemZ::AIH, false);
1465 return true;
1466
1467 case SystemZ::CHIMux:
1468 expandRIPseudo(MI, SystemZ::CHI, SystemZ::CIH, false);
1469 return true;
1470
1471 case SystemZ::CFIMux:
1472 expandRIPseudo(MI, SystemZ::CFI, SystemZ::CIH, false);
1473 return true;
1474
1475 case SystemZ::CLFIMux:
1476 expandRIPseudo(MI, SystemZ::CLFI, SystemZ::CLIH, false);
1477 return true;
1478
1479 case SystemZ::CMux:
1480 expandRXYPseudo(MI, SystemZ::C, SystemZ::CHF);
1481 return true;
1482
1483 case SystemZ::CLMux:
1484 expandRXYPseudo(MI, SystemZ::CL, SystemZ::CLHF);
1485 return true;
1486
1487 case SystemZ::RISBMux: {
1488 bool DestIsHigh = SystemZ::isHighReg(MI.getOperand(0).getReg());
1489 bool SrcIsHigh = SystemZ::isHighReg(MI.getOperand(2).getReg());
1490 if (SrcIsHigh == DestIsHigh)
1491 MI.setDesc(get(DestIsHigh ? SystemZ::RISBHH : SystemZ::RISBLL));
1492 else {
1493 MI.setDesc(get(DestIsHigh ? SystemZ::RISBHL : SystemZ::RISBLH));
1494 MI.getOperand(5).setImm(MI.getOperand(5).getImm() ^ 32);
1495 }
1496 return true;
1497 }
1498
1499 case SystemZ::ADJDYNALLOC:
1500 splitAdjDynAlloc(MI);
1501 return true;
1502
1503 case TargetOpcode::LOAD_STACK_GUARD:
1504 expandLoadStackGuard(&MI);
1505 return true;
1506
1507 default:
1508 return false;
1509 }
1510}
1511
1512unsigned SystemZInstrInfo::getInstSizeInBytes(const MachineInstr &MI) const {
1513 if (MI.isInlineAsm()) {
1514 const MachineFunction *MF = MI.getParent()->getParent();
1515 const char *AsmStr = MI.getOperand(0).getSymbolName();
1516 return getInlineAsmLength(AsmStr, *MF->getTarget().getMCAsmInfo());
1517 }
1518 return MI.getDesc().getSize();
1519}
1520
1521SystemZII::Branch
1522SystemZInstrInfo::getBranchInfo(const MachineInstr &MI) const {
1523 switch (MI.getOpcode()) {
1524 case SystemZ::BR:
1525 case SystemZ::BI:
1526 case SystemZ::J:
1527 case SystemZ::JG:
1528 return SystemZII::Branch(SystemZII::BranchNormal, SystemZ::CCMASK_ANY,
1529 SystemZ::CCMASK_ANY, &MI.getOperand(0));
1530
1531 case SystemZ::BRC:
1532 case SystemZ::BRCL:
1533 return SystemZII::Branch(SystemZII::BranchNormal, MI.getOperand(0).getImm(),
1534 MI.getOperand(1).getImm(), &MI.getOperand(2));
1535
1536 case SystemZ::BRCT:
1537 case SystemZ::BRCTH:
1538 return SystemZII::Branch(SystemZII::BranchCT, SystemZ::CCMASK_ICMP,
1539 SystemZ::CCMASK_CMP_NE, &MI.getOperand(2));
1540
1541 case SystemZ::BRCTG:
1542 return SystemZII::Branch(SystemZII::BranchCTG, SystemZ::CCMASK_ICMP,
1543 SystemZ::CCMASK_CMP_NE, &MI.getOperand(2));
1544
1545 case SystemZ::CIJ:
1546 case SystemZ::CRJ:
1547 return SystemZII::Branch(SystemZII::BranchC, SystemZ::CCMASK_ICMP,
1548 MI.getOperand(2).getImm(), &MI.getOperand(3));
1549
1550 case SystemZ::CLIJ:
1551 case SystemZ::CLRJ:
1552 return SystemZII::Branch(SystemZII::BranchCL, SystemZ::CCMASK_ICMP,
1553 MI.getOperand(2).getImm(), &MI.getOperand(3));
1554
1555 case SystemZ::CGIJ:
1556 case SystemZ::CGRJ:
1557 return SystemZII::Branch(SystemZII::BranchCG, SystemZ::CCMASK_ICMP,
1558 MI.getOperand(2).getImm(), &MI.getOperand(3));
1559
1560 case SystemZ::CLGIJ:
1561 case SystemZ::CLGRJ:
1562 return SystemZII::Branch(SystemZII::BranchCLG, SystemZ::CCMASK_ICMP,
1563 MI.getOperand(2).getImm(), &MI.getOperand(3));
1564
1565 case SystemZ::INLINEASM_BR:
1566 // Don't try to analyze asm goto, so pass nullptr as branch target argument.
1567 return SystemZII::Branch(SystemZII::AsmGoto, 0, 0, nullptr);
1568
1569 default:
1570 llvm_unreachable("Unrecognized branch opcode")__builtin_unreachable();
1571 }
1572}
1573
1574void SystemZInstrInfo::getLoadStoreOpcodes(const TargetRegisterClass *RC,
1575 unsigned &LoadOpcode,
1576 unsigned &StoreOpcode) const {
1577 if (RC == &SystemZ::GR32BitRegClass || RC == &SystemZ::ADDR32BitRegClass) {
1578 LoadOpcode = SystemZ::L;
1579 StoreOpcode = SystemZ::ST;
1580 } else if (RC == &SystemZ::GRH32BitRegClass) {
1581 LoadOpcode = SystemZ::LFH;
1582 StoreOpcode = SystemZ::STFH;
1583 } else if (RC == &SystemZ::GRX32BitRegClass) {
1584 LoadOpcode = SystemZ::LMux;
1585 StoreOpcode = SystemZ::STMux;
1586 } else if (RC == &SystemZ::GR64BitRegClass ||
1587 RC == &SystemZ::ADDR64BitRegClass) {
1588 LoadOpcode = SystemZ::LG;
1589 StoreOpcode = SystemZ::STG;
1590 } else if (RC == &SystemZ::GR128BitRegClass ||
1591 RC == &SystemZ::ADDR128BitRegClass) {
1592 LoadOpcode = SystemZ::L128;
1593 StoreOpcode = SystemZ::ST128;
1594 } else if (RC == &SystemZ::FP32BitRegClass) {
1595 LoadOpcode = SystemZ::LE;
1596 StoreOpcode = SystemZ::STE;
1597 } else if (RC == &SystemZ::FP64BitRegClass) {
1598 LoadOpcode = SystemZ::LD;
1599 StoreOpcode = SystemZ::STD;
1600 } else if (RC == &SystemZ::FP128BitRegClass) {
1601 LoadOpcode = SystemZ::LX;
1602 StoreOpcode = SystemZ::STX;
1603 } else if (RC == &SystemZ::VR32BitRegClass) {
1604 LoadOpcode = SystemZ::VL32;
1605 StoreOpcode = SystemZ::VST32;
1606 } else if (RC == &SystemZ::VR64BitRegClass) {
1607 LoadOpcode = SystemZ::VL64;
1608 StoreOpcode = SystemZ::VST64;
1609 } else if (RC == &SystemZ::VF128BitRegClass ||
1610 RC == &SystemZ::VR128BitRegClass) {
1611 LoadOpcode = SystemZ::VL;
1612 StoreOpcode = SystemZ::VST;
1613 } else
1614 llvm_unreachable("Unsupported regclass to load or store")__builtin_unreachable();
1615}
1616
1617unsigned SystemZInstrInfo::getOpcodeForOffset(unsigned Opcode,
1618 int64_t Offset) const {
1619 const MCInstrDesc &MCID = get(Opcode);
1620 int64_t Offset2 = (MCID.TSFlags & SystemZII::Is128Bit ? Offset + 8 : Offset);
1621 if (isUInt<12>(Offset) && isUInt<12>(Offset2)) {
1622 // Get the instruction to use for unsigned 12-bit displacements.
1623 int Disp12Opcode = SystemZ::getDisp12Opcode(Opcode);
1624 if (Disp12Opcode >= 0)
1625 return Disp12Opcode;
1626
1627 // All address-related instructions can use unsigned 12-bit
1628 // displacements.
1629 return Opcode;
1630 }
1631 if (isInt<20>(Offset) && isInt<20>(Offset2)) {
1632 // Get the instruction to use for signed 20-bit displacements.
1633 int Disp20Opcode = SystemZ::getDisp20Opcode(Opcode);
1634 if (Disp20Opcode >= 0)
1635 return Disp20Opcode;
1636
1637 // Check whether Opcode allows signed 20-bit displacements.
1638 if (MCID.TSFlags & SystemZII::Has20BitOffset)
1639 return Opcode;
1640 }
1641 return 0;
1642}
1643
1644unsigned SystemZInstrInfo::getLoadAndTest(unsigned Opcode) const {
1645 switch (Opcode) {
1646 case SystemZ::L: return SystemZ::LT;
1647 case SystemZ::LY: return SystemZ::LT;
1648 case SystemZ::LG: return SystemZ::LTG;
1649 case SystemZ::LGF: return SystemZ::LTGF;
1650 case SystemZ::LR: return SystemZ::LTR;
1651 case SystemZ::LGFR: return SystemZ::LTGFR;
1652 case SystemZ::LGR: return SystemZ::LTGR;
1653 case SystemZ::LER: return SystemZ::LTEBR;
1654 case SystemZ::LDR: return SystemZ::LTDBR;
1655 case SystemZ::LXR: return SystemZ::LTXBR;
1656 case SystemZ::LCDFR: return SystemZ::LCDBR;
1657 case SystemZ::LPDFR: return SystemZ::LPDBR;
1658 case SystemZ::LNDFR: return SystemZ::LNDBR;
1659 case SystemZ::LCDFR_32: return SystemZ::LCEBR;
1660 case SystemZ::LPDFR_32: return SystemZ::LPEBR;
1661 case SystemZ::LNDFR_32: return SystemZ::LNEBR;
1662 // On zEC12 we prefer to use RISBGN. But if there is a chance to
1663 // actually use the condition code, we may turn it back into RISGB.
1664 // Note that RISBG is not really a "load-and-test" instruction,
1665 // but sets the same condition code values, so is OK to use here.
1666 case SystemZ::RISBGN: return SystemZ::RISBG;
1667 default: return 0;
1668 }
1669}
1670
1671// Return true if Mask matches the regexp 0*1+0*, given that zero masks
1672// have already been filtered out. Store the first set bit in LSB and
1673// the number of set bits in Length if so.
1674static bool isStringOfOnes(uint64_t Mask, unsigned &LSB, unsigned &Length) {
1675 unsigned First = findFirstSet(Mask);
7
Calling 'findFirstSet<unsigned long>'
14
Returning from 'findFirstSet<unsigned long>'
15
'First' initialized to 4294967295
1676 uint64_t Top = (Mask >> First) + 1;
16
The result of the right shift is undefined due to shifting by '4294967295', which is greater or equal to the width of type 'uint64_t'
1677 if ((Top & -Top) == Top) {
1678 LSB = First;
1679 Length = findFirstSet(Top);
1680 return true;
1681 }
1682 return false;
1683}
1684
1685bool SystemZInstrInfo::isRxSBGMask(uint64_t Mask, unsigned BitSize,
1686 unsigned &Start, unsigned &End) const {
1687 // Reject trivial all-zero masks.
1688 Mask &= allOnes(BitSize);
1689 if (Mask == 0)
3
Assuming 'Mask' is not equal to 0
4
Taking false branch
1690 return false;
1691
1692 // Handle the 1+0+ or 0+1+0* cases. Start then specifies the index of
1693 // the msb and End specifies the index of the lsb.
1694 unsigned LSB, Length;
1695 if (isStringOfOnes(Mask, LSB, Length)) {
5
Taking false branch
1696 Start = 63 - (LSB + Length - 1);
1697 End = 63 - LSB;
1698 return true;
1699 }
1700
1701 // Handle the wrap-around 1+0+1+ cases. Start then specifies the msb
1702 // of the low 1s and End specifies the lsb of the high 1s.
1703 if (isStringOfOnes(Mask ^ allOnes(BitSize), LSB, Length)) {
6
Calling 'isStringOfOnes'
1704 assert(LSB > 0 && "Bottom bit must be set")(static_cast<void> (0));
1705 assert(LSB + Length < BitSize && "Top bit must be set")(static_cast<void> (0));
1706 Start = 63 - (LSB - 1);
1707 End = 63 - (LSB + Length);
1708 return true;
1709 }
1710
1711 return false;
1712}
1713
1714unsigned SystemZInstrInfo::getFusedCompare(unsigned Opcode,
1715 SystemZII::FusedCompareType Type,
1716 const MachineInstr *MI) const {
1717 switch (Opcode) {
1718 case SystemZ::CHI:
1719 case SystemZ::CGHI:
1720 if (!(MI && isInt<8>(MI->getOperand(1).getImm())))
1721 return 0;
1722 break;
1723 case SystemZ::CLFI:
1724 case SystemZ::CLGFI:
1725 if (!(MI && isUInt<8>(MI->getOperand(1).getImm())))
1726 return 0;
1727 break;
1728 case SystemZ::CL:
1729 case SystemZ::CLG:
1730 if (!STI.hasMiscellaneousExtensions())
1731 return 0;
1732 if (!(MI && MI->getOperand(3).getReg() == 0))
1733 return 0;
1734 break;
1735 }
1736 switch (Type) {
1737 case SystemZII::CompareAndBranch:
1738 switch (Opcode) {
1739 case SystemZ::CR:
1740 return SystemZ::CRJ;
1741 case SystemZ::CGR:
1742 return SystemZ::CGRJ;
1743 case SystemZ::CHI:
1744 return SystemZ::CIJ;
1745 case SystemZ::CGHI:
1746 return SystemZ::CGIJ;
1747 case SystemZ::CLR:
1748 return SystemZ::CLRJ;
1749 case SystemZ::CLGR:
1750 return SystemZ::CLGRJ;
1751 case SystemZ::CLFI:
1752 return SystemZ::CLIJ;
1753 case SystemZ::CLGFI:
1754 return SystemZ::CLGIJ;
1755 default:
1756 return 0;
1757 }
1758 case SystemZII::CompareAndReturn:
1759 switch (Opcode) {
1760 case SystemZ::CR:
1761 return SystemZ::CRBReturn;
1762 case SystemZ::CGR:
1763 return SystemZ::CGRBReturn;
1764 case SystemZ::CHI:
1765 return SystemZ::CIBReturn;
1766 case SystemZ::CGHI:
1767 return SystemZ::CGIBReturn;
1768 case SystemZ::CLR:
1769 return SystemZ::CLRBReturn;
1770 case SystemZ::CLGR:
1771 return SystemZ::CLGRBReturn;
1772 case SystemZ::CLFI:
1773 return SystemZ::CLIBReturn;
1774 case SystemZ::CLGFI:
1775 return SystemZ::CLGIBReturn;
1776 default:
1777 return 0;
1778 }
1779 case SystemZII::CompareAndSibcall:
1780 switch (Opcode) {
1781 case SystemZ::CR:
1782 return SystemZ::CRBCall;
1783 case SystemZ::CGR:
1784 return SystemZ::CGRBCall;
1785 case SystemZ::CHI:
1786 return SystemZ::CIBCall;
1787 case SystemZ::CGHI:
1788 return SystemZ::CGIBCall;
1789 case SystemZ::CLR:
1790 return SystemZ::CLRBCall;
1791 case SystemZ::CLGR:
1792 return SystemZ::CLGRBCall;
1793 case SystemZ::CLFI:
1794 return SystemZ::CLIBCall;
1795 case SystemZ::CLGFI:
1796 return SystemZ::CLGIBCall;
1797 default:
1798 return 0;
1799 }
1800 case SystemZII::CompareAndTrap:
1801 switch (Opcode) {
1802 case SystemZ::CR:
1803 return SystemZ::CRT;
1804 case SystemZ::CGR:
1805 return SystemZ::CGRT;
1806 case SystemZ::CHI:
1807 return SystemZ::CIT;
1808 case SystemZ::CGHI:
1809 return SystemZ::CGIT;
1810 case SystemZ::CLR:
1811 return SystemZ::CLRT;
1812 case SystemZ::CLGR:
1813 return SystemZ::CLGRT;
1814 case SystemZ::CLFI:
1815 return SystemZ::CLFIT;
1816 case SystemZ::CLGFI:
1817 return SystemZ::CLGIT;
1818 case SystemZ::CL:
1819 return SystemZ::CLT;
1820 case SystemZ::CLG:
1821 return SystemZ::CLGT;
1822 default:
1823 return 0;
1824 }
1825 }
1826 return 0;
1827}
1828
1829bool SystemZInstrInfo::
1830prepareCompareSwapOperands(MachineBasicBlock::iterator const MBBI) const {
1831 assert(MBBI->isCompare() && MBBI->getOperand(0).isReg() &&(static_cast<void> (0))
1832 MBBI->getOperand(1).isReg() && !MBBI->mayLoad() &&(static_cast<void> (0))
1833 "Not a compare reg/reg.")(static_cast<void> (0));
1834
1835 MachineBasicBlock *MBB = MBBI->getParent();
1836 bool CCLive = true;
1837 SmallVector<MachineInstr *, 4> CCUsers;
1838 for (MachineBasicBlock::iterator Itr = std::next(MBBI);
1839 Itr != MBB->end(); ++Itr) {
1840 if (Itr->readsRegister(SystemZ::CC)) {
1841 unsigned Flags = Itr->getDesc().TSFlags;
1842 if ((Flags & SystemZII::CCMaskFirst) || (Flags & SystemZII::CCMaskLast))
1843 CCUsers.push_back(&*Itr);
1844 else
1845 return false;
1846 }
1847 if (Itr->definesRegister(SystemZ::CC)) {
1848 CCLive = false;
1849 break;
1850 }
1851 }
1852 if (CCLive) {
1853 LivePhysRegs LiveRegs(*MBB->getParent()->getSubtarget().getRegisterInfo());
1854 LiveRegs.addLiveOuts(*MBB);
1855 if (LiveRegs.contains(SystemZ::CC))
1856 return false;
1857 }
1858
1859 // Update all CC users.
1860 for (unsigned Idx = 0; Idx < CCUsers.size(); ++Idx) {
1861 unsigned Flags = CCUsers[Idx]->getDesc().TSFlags;
1862 unsigned FirstOpNum = ((Flags & SystemZII::CCMaskFirst) ?
1863 0 : CCUsers[Idx]->getNumExplicitOperands() - 2);
1864 MachineOperand &CCMaskMO = CCUsers[Idx]->getOperand(FirstOpNum + 1);
1865 unsigned NewCCMask = SystemZ::reverseCCMask(CCMaskMO.getImm());
1866 CCMaskMO.setImm(NewCCMask);
1867 }
1868
1869 return true;
1870}
1871
1872unsigned SystemZ::reverseCCMask(unsigned CCMask) {
1873 return ((CCMask & SystemZ::CCMASK_CMP_EQ) |
1874 (CCMask & SystemZ::CCMASK_CMP_GT ? SystemZ::CCMASK_CMP_LT : 0) |
1875 (CCMask & SystemZ::CCMASK_CMP_LT ? SystemZ::CCMASK_CMP_GT : 0) |
1876 (CCMask & SystemZ::CCMASK_CMP_UO));
1877}
1878
1879MachineBasicBlock *SystemZ::emitBlockAfter(MachineBasicBlock *MBB) {
1880 MachineFunction &MF = *MBB->getParent();
1881 MachineBasicBlock *NewMBB = MF.CreateMachineBasicBlock(MBB->getBasicBlock());
1882 MF.insert(std::next(MachineFunction::iterator(MBB)), NewMBB);
1883 return NewMBB;
1884}
1885
1886MachineBasicBlock *SystemZ::splitBlockAfter(MachineBasicBlock::iterator MI,
1887 MachineBasicBlock *MBB) {
1888 MachineBasicBlock *NewMBB = emitBlockAfter(MBB);
1889 NewMBB->splice(NewMBB->begin(), MBB,
1890 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
1891 NewMBB->transferSuccessorsAndUpdatePHIs(MBB);
1892 return NewMBB;
1893}
1894
1895MachineBasicBlock *SystemZ::splitBlockBefore(MachineBasicBlock::iterator MI,
1896 MachineBasicBlock *MBB) {
1897 MachineBasicBlock *NewMBB = emitBlockAfter(MBB);
1898 NewMBB->splice(NewMBB->begin(), MBB, MI, MBB->end());
1899 NewMBB->transferSuccessorsAndUpdatePHIs(MBB);
1900 return NewMBB;
1901}
1902
1903unsigned SystemZInstrInfo::getLoadAndTrap(unsigned Opcode) const {
1904 if (!STI.hasLoadAndTrap())
1905 return 0;
1906 switch (Opcode) {
1907 case SystemZ::L:
1908 case SystemZ::LY:
1909 return SystemZ::LAT;
1910 case SystemZ::LG:
1911 return SystemZ::LGAT;
1912 case SystemZ::LFH:
1913 return SystemZ::LFHAT;
1914 case SystemZ::LLGF:
1915 return SystemZ::LLGFAT;
1916 case SystemZ::LLGT:
1917 return SystemZ::LLGTAT;
1918 }
1919 return 0;
1920}
1921
1922void SystemZInstrInfo::loadImmediate(MachineBasicBlock &MBB,
1923 MachineBasicBlock::iterator MBBI,
1924 unsigned Reg, uint64_t Value) const {
1925 DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
1926 unsigned Opcode;
1927 if (isInt<16>(Value))
1928 Opcode = SystemZ::LGHI;
1929 else if (SystemZ::isImmLL(Value))
1930 Opcode = SystemZ::LLILL;
1931 else if (SystemZ::isImmLH(Value)) {
1932 Opcode = SystemZ::LLILH;
1933 Value >>= 16;
1934 } else {
1935 assert(isInt<32>(Value) && "Huge values not handled yet")(static_cast<void> (0));
1936 Opcode = SystemZ::LGFI;
1937 }
1938 BuildMI(MBB, MBBI, DL, get(Opcode), Reg).addImm(Value);
1939}
1940
1941bool SystemZInstrInfo::verifyInstruction(const MachineInstr &MI,
1942 StringRef &ErrInfo) const {
1943 const MCInstrDesc &MCID = MI.getDesc();
1944 for (unsigned I = 0, E = MI.getNumOperands(); I != E; ++I) {
1945 if (I >= MCID.getNumOperands())
1946 break;
1947 const MachineOperand &Op = MI.getOperand(I);
1948 const MCOperandInfo &MCOI = MCID.OpInfo[I];
1949 // Addressing modes have register and immediate operands. Op should be a
1950 // register (or frame index) operand if MCOI.RegClass contains a valid
1951 // register class, or an immediate otherwise.
1952 if (MCOI.OperandType == MCOI::OPERAND_MEMORY &&
1953 ((MCOI.RegClass != -1 && !Op.isReg() && !Op.isFI()) ||
1954 (MCOI.RegClass == -1 && !Op.isImm()))) {
1955 ErrInfo = "Addressing mode operands corrupt!";
1956 return false;
1957 }
1958 }
1959
1960 return true;
1961}
1962
1963bool SystemZInstrInfo::
1964areMemAccessesTriviallyDisjoint(const MachineInstr &MIa,
1965 const MachineInstr &MIb) const {
1966
1967 if (!MIa.hasOneMemOperand() || !MIb.hasOneMemOperand())
1968 return false;
1969
1970 // If mem-operands show that the same address Value is used by both
1971 // instructions, check for non-overlapping offsets and widths. Not
1972 // sure if a register based analysis would be an improvement...
1973
1974 MachineMemOperand *MMOa = *MIa.memoperands_begin();
1975 MachineMemOperand *MMOb = *MIb.memoperands_begin();
1976 const Value *VALa = MMOa->getValue();
1977 const Value *VALb = MMOb->getValue();
1978 bool SameVal = (VALa && VALb && (VALa == VALb));
1979 if (!SameVal) {
1980 const PseudoSourceValue *PSVa = MMOa->getPseudoValue();
1981 const PseudoSourceValue *PSVb = MMOb->getPseudoValue();
1982 if (PSVa && PSVb && (PSVa == PSVb))
1983 SameVal = true;
1984 }
1985 if (SameVal) {
1986 int OffsetA = MMOa->getOffset(), OffsetB = MMOb->getOffset();
1987 int WidthA = MMOa->getSize(), WidthB = MMOb->getSize();
1988 int LowOffset = OffsetA < OffsetB ? OffsetA : OffsetB;
1989 int HighOffset = OffsetA < OffsetB ? OffsetB : OffsetA;
1990 int LowWidth = (LowOffset == OffsetA) ? WidthA : WidthB;
1991 if (LowOffset + LowWidth <= HighOffset)
1992 return true;
1993 }
1994
1995 return false;
1996}

/build/llvm-toolchain-snapshot-14~++20210903100615+fd66b44ec19e/llvm/include/llvm/Support/MathExtras.h

1//===-- llvm/Support/MathExtras.h - Useful math functions -------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains some functions that are useful for math stuff.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_SUPPORT_MATHEXTRAS_H
14#define LLVM_SUPPORT_MATHEXTRAS_H
15
16#include "llvm/Support/Compiler.h"
17#include <cassert>
18#include <climits>
19#include <cmath>
20#include <cstdint>
21#include <cstring>
22#include <limits>
23#include <type_traits>
24
25#ifdef __ANDROID_NDK__
26#include <android/api-level.h>
27#endif
28
29#ifdef _MSC_VER
30// Declare these intrinsics manually rather including intrin.h. It's very
31// expensive, and MathExtras.h is popular.
32// #include <intrin.h>
33extern "C" {
34unsigned char _BitScanForward(unsigned long *_Index, unsigned long _Mask);
35unsigned char _BitScanForward64(unsigned long *_Index, unsigned __int64 _Mask);
36unsigned char _BitScanReverse(unsigned long *_Index, unsigned long _Mask);
37unsigned char _BitScanReverse64(unsigned long *_Index, unsigned __int64 _Mask);
38}
39#endif
40
41namespace llvm {
42
43/// The behavior an operation has on an input of 0.
44enum ZeroBehavior {
45 /// The returned value is undefined.
46 ZB_Undefined,
47 /// The returned value is numeric_limits<T>::max()
48 ZB_Max,
49 /// The returned value is numeric_limits<T>::digits
50 ZB_Width
51};
52
53/// Mathematical constants.
54namespace numbers {
55// TODO: Track C++20 std::numbers.
56// TODO: Favor using the hexadecimal FP constants (requires C++17).
57constexpr double e = 2.7182818284590452354, // (0x1.5bf0a8b145749P+1) https://oeis.org/A001113
58 egamma = .57721566490153286061, // (0x1.2788cfc6fb619P-1) https://oeis.org/A001620
59 ln2 = .69314718055994530942, // (0x1.62e42fefa39efP-1) https://oeis.org/A002162
60 ln10 = 2.3025850929940456840, // (0x1.24bb1bbb55516P+1) https://oeis.org/A002392
61 log2e = 1.4426950408889634074, // (0x1.71547652b82feP+0)
62 log10e = .43429448190325182765, // (0x1.bcb7b1526e50eP-2)
63 pi = 3.1415926535897932385, // (0x1.921fb54442d18P+1) https://oeis.org/A000796
64 inv_pi = .31830988618379067154, // (0x1.45f306bc9c883P-2) https://oeis.org/A049541
65 sqrtpi = 1.7724538509055160273, // (0x1.c5bf891b4ef6bP+0) https://oeis.org/A002161
66 inv_sqrtpi = .56418958354775628695, // (0x1.20dd750429b6dP-1) https://oeis.org/A087197
67 sqrt2 = 1.4142135623730950488, // (0x1.6a09e667f3bcdP+0) https://oeis.org/A00219
68 inv_sqrt2 = .70710678118654752440, // (0x1.6a09e667f3bcdP-1)
69 sqrt3 = 1.7320508075688772935, // (0x1.bb67ae8584caaP+0) https://oeis.org/A002194
70 inv_sqrt3 = .57735026918962576451, // (0x1.279a74590331cP-1)
71 phi = 1.6180339887498948482; // (0x1.9e3779b97f4a8P+0) https://oeis.org/A001622
72constexpr float ef = 2.71828183F, // (0x1.5bf0a8P+1) https://oeis.org/A001113
73 egammaf = .577215665F, // (0x1.2788d0P-1) https://oeis.org/A001620
74 ln2f = .693147181F, // (0x1.62e430P-1) https://oeis.org/A002162
75 ln10f = 2.30258509F, // (0x1.26bb1cP+1) https://oeis.org/A002392
76 log2ef = 1.44269504F, // (0x1.715476P+0)
77 log10ef = .434294482F, // (0x1.bcb7b2P-2)
78 pif = 3.14159265F, // (0x1.921fb6P+1) https://oeis.org/A000796
79 inv_pif = .318309886F, // (0x1.45f306P-2) https://oeis.org/A049541
80 sqrtpif = 1.77245385F, // (0x1.c5bf8aP+0) https://oeis.org/A002161
81 inv_sqrtpif = .564189584F, // (0x1.20dd76P-1) https://oeis.org/A087197
82 sqrt2f = 1.41421356F, // (0x1.6a09e6P+0) https://oeis.org/A002193
83 inv_sqrt2f = .707106781F, // (0x1.6a09e6P-1)
84 sqrt3f = 1.73205081F, // (0x1.bb67aeP+0) https://oeis.org/A002194
85 inv_sqrt3f = .577350269F, // (0x1.279a74P-1)
86 phif = 1.61803399F; // (0x1.9e377aP+0) https://oeis.org/A001622
87} // namespace numbers
88
89namespace detail {
90template <typename T, std::size_t SizeOfT> struct TrailingZerosCounter {
91 static unsigned count(T Val, ZeroBehavior) {
92 if (!Val)
93 return std::numeric_limits<T>::digits;
94 if (Val & 0x1)
95 return 0;
96
97 // Bisection method.
98 unsigned ZeroBits = 0;
99 T Shift = std::numeric_limits<T>::digits >> 1;
100 T Mask = std::numeric_limits<T>::max() >> Shift;
101 while (Shift) {
102 if ((Val & Mask) == 0) {
103 Val >>= Shift;
104 ZeroBits |= Shift;
105 }
106 Shift >>= 1;
107 Mask >>= Shift;
108 }
109 return ZeroBits;
110 }
111};
112
113#if defined(__GNUC__4) || defined(_MSC_VER)
114template <typename T> struct TrailingZerosCounter<T, 4> {
115 static unsigned count(T Val, ZeroBehavior ZB) {
116 if (ZB != ZB_Undefined && Val == 0)
117 return 32;
118
119#if __has_builtin(__builtin_ctz)1 || defined(__GNUC__4)
120 return __builtin_ctz(Val);
121#elif defined(_MSC_VER)
122 unsigned long Index;
123 _BitScanForward(&Index, Val);
124 return Index;
125#endif
126 }
127};
128
129#if !defined(_MSC_VER) || defined(_M_X64)
130template <typename T> struct TrailingZerosCounter<T, 8> {
131 static unsigned count(T Val, ZeroBehavior ZB) {
132 if (ZB != ZB_Undefined && Val == 0)
133 return 64;
134
135#if __has_builtin(__builtin_ctzll)1 || defined(__GNUC__4)
136 return __builtin_ctzll(Val);
137#elif defined(_MSC_VER)
138 unsigned long Index;
139 _BitScanForward64(&Index, Val);
140 return Index;
141#endif
142 }
143};
144#endif
145#endif
146} // namespace detail
147
148/// Count number of 0's from the least significant bit to the most
149/// stopping at the first 1.
150///
151/// Only unsigned integral types are allowed.
152///
153/// \param ZB the behavior on an input of 0. Only ZB_Width and ZB_Undefined are
154/// valid arguments.
155template <typename T>
156unsigned countTrailingZeros(T Val, ZeroBehavior ZB = ZB_Width) {
157 static_assert(std::numeric_limits<T>::is_integer &&
158 !std::numeric_limits<T>::is_signed,
159 "Only unsigned integral types are allowed.");
160 return llvm::detail::TrailingZerosCounter<T, sizeof(T)>::count(Val, ZB);
161}
162
163namespace detail {
164template <typename T, std::size_t SizeOfT> struct LeadingZerosCounter {
165 static unsigned count(T Val, ZeroBehavior) {
166 if (!Val)
167 return std::numeric_limits<T>::digits;
168
169 // Bisection method.
170 unsigned ZeroBits = 0;
171 for (T Shift = std::numeric_limits<T>::digits >> 1; Shift; Shift >>= 1) {
172 T Tmp = Val >> Shift;
173 if (Tmp)
174 Val = Tmp;
175 else
176 ZeroBits |= Shift;
177 }
178 return ZeroBits;
179 }
180};
181
182#if defined(__GNUC__4) || defined(_MSC_VER)
183template <typename T> struct LeadingZerosCounter<T, 4> {
184 static unsigned count(T Val, ZeroBehavior ZB) {
185 if (ZB != ZB_Undefined && Val == 0)
186 return 32;
187
188#if __has_builtin(__builtin_clz)1 || defined(__GNUC__4)
189 return __builtin_clz(Val);
190#elif defined(_MSC_VER)
191 unsigned long Index;
192 _BitScanReverse(&Index, Val);
193 return Index ^ 31;
194#endif
195 }
196};
197
198#if !defined(_MSC_VER) || defined(_M_X64)
199template <typename T> struct LeadingZerosCounter<T, 8> {
200 static unsigned count(T Val, ZeroBehavior ZB) {
201 if (ZB != ZB_Undefined && Val == 0)
202 return 64;
203
204#if __has_builtin(__builtin_clzll)1 || defined(__GNUC__4)
205 return __builtin_clzll(Val);
206#elif defined(_MSC_VER)
207 unsigned long Index;
208 _BitScanReverse64(&Index, Val);
209 return Index ^ 63;
210#endif
211 }
212};
213#endif
214#endif
215} // namespace detail
216
217/// Count number of 0's from the most significant bit to the least
218/// stopping at the first 1.
219///
220/// Only unsigned integral types are allowed.
221///
222/// \param ZB the behavior on an input of 0. Only ZB_Width and ZB_Undefined are
223/// valid arguments.
224template <typename T>
225unsigned countLeadingZeros(T Val, ZeroBehavior ZB = ZB_Width) {
226 static_assert(std::numeric_limits<T>::is_integer &&
227 !std::numeric_limits<T>::is_signed,
228 "Only unsigned integral types are allowed.");
229 return llvm::detail::LeadingZerosCounter<T, sizeof(T)>::count(Val, ZB);
230}
231
232/// Get the index of the first set bit starting from the least
233/// significant bit.
234///
235/// Only unsigned integral types are allowed.
236///
237/// \param ZB the behavior on an input of 0. Only ZB_Max and ZB_Undefined are
238/// valid arguments.
239template <typename T> T findFirstSet(T Val, ZeroBehavior ZB = ZB_Max) {
240 if (ZB
7.1
'ZB' is equal to ZB_Max
7.1
'ZB' is equal to ZB_Max
7.1
'ZB' is equal to ZB_Max
== ZB_Max && Val == 0)
8
Assuming 'Val' is equal to 0
9
Taking true branch
241 return std::numeric_limits<T>::max();
10
Calling 'numeric_limits::max'
12
Returning from 'numeric_limits::max'
13
Returning the value 18446744073709551615
242
243 return countTrailingZeros(Val, ZB_Undefined);
244}
245
246/// Create a bitmask with the N right-most bits set to 1, and all other
247/// bits set to 0. Only unsigned types are allowed.
248template <typename T> T maskTrailingOnes(unsigned N) {
249 static_assert(std::is_unsigned<T>::value, "Invalid type!");
250 const unsigned Bits = CHAR_BIT8 * sizeof(T);
251 assert(N <= Bits && "Invalid bit index")(static_cast<void> (0));
252 return N == 0 ? 0 : (T(-1) >> (Bits - N));
253}
254
255/// Create a bitmask with the N left-most bits set to 1, and all other
256/// bits set to 0. Only unsigned types are allowed.
257template <typename T> T maskLeadingOnes(unsigned N) {
258 return ~maskTrailingOnes<T>(CHAR_BIT8 * sizeof(T) - N);
259}
260
261/// Create a bitmask with the N right-most bits set to 0, and all other
262/// bits set to 1. Only unsigned types are allowed.
263template <typename T> T maskTrailingZeros(unsigned N) {
264 return maskLeadingOnes<T>(CHAR_BIT8 * sizeof(T) - N);
265}
266
267/// Create a bitmask with the N left-most bits set to 0, and all other
268/// bits set to 1. Only unsigned types are allowed.
269template <typename T> T maskLeadingZeros(unsigned N) {
270 return maskTrailingOnes<T>(CHAR_BIT8 * sizeof(T) - N);
271}
272
273/// Get the index of the last set bit starting from the least
274/// significant bit.
275///
276/// Only unsigned integral types are allowed.
277///
278/// \param ZB the behavior on an input of 0. Only ZB_Max and ZB_Undefined are
279/// valid arguments.
280template <typename T> T findLastSet(T Val, ZeroBehavior ZB = ZB_Max) {
281 if (ZB == ZB_Max && Val == 0)
282 return std::numeric_limits<T>::max();
283
284 // Use ^ instead of - because both gcc and llvm can remove the associated ^
285 // in the __builtin_clz intrinsic on x86.
286 return countLeadingZeros(Val, ZB_Undefined) ^
287 (std::numeric_limits<T>::digits - 1);
288}
289
290/// Macro compressed bit reversal table for 256 bits.
291///
292/// http://graphics.stanford.edu/~seander/bithacks.html#BitReverseTable
293static const unsigned char BitReverseTable256[256] = {
294#define R2(n) n, n + 2 * 64, n + 1 * 64, n + 3 * 64
295#define R4(n) R2(n), R2(n + 2 * 16), R2(n + 1 * 16), R2(n + 3 * 16)
296#define R6(n) R4(n), R4(n + 2 * 4), R4(n + 1 * 4), R4(n + 3 * 4)
297 R6(0), R6(2), R6(1), R6(3)
298#undef R2
299#undef R4
300#undef R6
301};
302
303/// Reverse the bits in \p Val.
304template <typename T>
305T reverseBits(T Val) {
306 unsigned char in[sizeof(Val)];
307 unsigned char out[sizeof(Val)];
308 std::memcpy(in, &Val, sizeof(Val));
309 for (unsigned i = 0; i < sizeof(Val); ++i)
310 out[(sizeof(Val) - i) - 1] = BitReverseTable256[in[i]];
311 std::memcpy(&Val, out, sizeof(Val));
312 return Val;
313}
314
315#if __has_builtin(__builtin_bitreverse8)1
316template<>
317inline uint8_t reverseBits<uint8_t>(uint8_t Val) {
318 return __builtin_bitreverse8(Val);
319}
320#endif
321
322#if __has_builtin(__builtin_bitreverse16)1
323template<>
324inline uint16_t reverseBits<uint16_t>(uint16_t Val) {
325 return __builtin_bitreverse16(Val);
326}
327#endif
328
329#if __has_builtin(__builtin_bitreverse32)1
330template<>
331inline uint32_t reverseBits<uint32_t>(uint32_t Val) {
332 return __builtin_bitreverse32(Val);
333}
334#endif
335
336#if __has_builtin(__builtin_bitreverse64)1
337template<>
338inline uint64_t reverseBits<uint64_t>(uint64_t Val) {
339 return __builtin_bitreverse64(Val);
340}
341#endif
342
343// NOTE: The following support functions use the _32/_64 extensions instead of
344// type overloading so that signed and unsigned integers can be used without
345// ambiguity.
346
347/// Return the high 32 bits of a 64 bit value.
348constexpr inline uint32_t Hi_32(uint64_t Value) {
349 return static_cast<uint32_t>(Value >> 32);
350}
351
352/// Return the low 32 bits of a 64 bit value.
353constexpr inline uint32_t Lo_32(uint64_t Value) {
354 return static_cast<uint32_t>(Value);
355}
356
357/// Make a 64-bit integer from a high / low pair of 32-bit integers.
358constexpr inline uint64_t Make_64(uint32_t High, uint32_t Low) {
359 return ((uint64_t)High << 32) | (uint64_t)Low;
360}
361
362/// Checks if an integer fits into the given bit width.
363template <unsigned N> constexpr inline bool isInt(int64_t x) {
364 return N >= 64 || (-(INT64_C(1)1L<<(N-1)) <= x && x < (INT64_C(1)1L<<(N-1)));
365}
366// Template specializations to get better code for common cases.
367template <> constexpr inline bool isInt<8>(int64_t x) {
368 return static_cast<int8_t>(x) == x;
369}
370template <> constexpr inline bool isInt<16>(int64_t x) {
371 return static_cast<int16_t>(x) == x;
372}
373template <> constexpr inline bool isInt<32>(int64_t x) {
374 return static_cast<int32_t>(x) == x;
375}
376
377/// Checks if a signed integer is an N bit number shifted left by S.
378template <unsigned N, unsigned S>
379constexpr inline bool isShiftedInt(int64_t x) {
380 static_assert(
381 N > 0, "isShiftedInt<0> doesn't make sense (refers to a 0-bit number.");
382 static_assert(N + S <= 64, "isShiftedInt<N, S> with N + S > 64 is too wide.");
383 return isInt<N + S>(x) && (x % (UINT64_C(1)1UL << S) == 0);
384}
385
386/// Checks if an unsigned integer fits into the given bit width.
387///
388/// This is written as two functions rather than as simply
389///
390/// return N >= 64 || X < (UINT64_C(1) << N);
391///
392/// to keep MSVC from (incorrectly) warning on isUInt<64> that we're shifting
393/// left too many places.
394template <unsigned N>
395constexpr inline std::enable_if_t<(N < 64), bool> isUInt(uint64_t X) {
396 static_assert(N > 0, "isUInt<0> doesn't make sense");
397 return X < (UINT64_C(1)1UL << (N));
398}
399template <unsigned N>
400constexpr inline std::enable_if_t<N >= 64, bool> isUInt(uint64_t) {
401 return true;
402}
403
404// Template specializations to get better code for common cases.
405template <> constexpr inline bool isUInt<8>(uint64_t x) {
406 return static_cast<uint8_t>(x) == x;
407}
408template <> constexpr inline bool isUInt<16>(uint64_t x) {
409 return static_cast<uint16_t>(x) == x;
410}
411template <> constexpr inline bool isUInt<32>(uint64_t x) {
412 return static_cast<uint32_t>(x) == x;
413}
414
415/// Checks if a unsigned integer is an N bit number shifted left by S.
416template <unsigned N, unsigned S>
417constexpr inline bool isShiftedUInt(uint64_t x) {
418 static_assert(
419 N > 0, "isShiftedUInt<0> doesn't make sense (refers to a 0-bit number)");
420 static_assert(N + S <= 64,
421 "isShiftedUInt<N, S> with N + S > 64 is too wide.");
422 // Per the two static_asserts above, S must be strictly less than 64. So
423 // 1 << S is not undefined behavior.
424 return isUInt<N + S>(x) && (x % (UINT64_C(1)1UL << S) == 0);
425}
426
427/// Gets the maximum value for a N-bit unsigned integer.
428inline uint64_t maxUIntN(uint64_t N) {
429 assert(N > 0 && N <= 64 && "integer width out of range")(static_cast<void> (0));
430
431 // uint64_t(1) << 64 is undefined behavior, so we can't do
432 // (uint64_t(1) << N) - 1
433 // without checking first that N != 64. But this works and doesn't have a
434 // branch.
435 return UINT64_MAX(18446744073709551615UL) >> (64 - N);
436}
437
438/// Gets the minimum value for a N-bit signed integer.
439inline int64_t minIntN(int64_t N) {
440 assert(N > 0 && N <= 64 && "integer width out of range")(static_cast<void> (0));
441
442 return UINT64_C(1)1UL + ~(UINT64_C(1)1UL << (N - 1));
443}
444
445/// Gets the maximum value for a N-bit signed integer.
446inline int64_t maxIntN(int64_t N) {
447 assert(N > 0 && N <= 64 && "integer width out of range")(static_cast<void> (0));
448
449 // This relies on two's complement wraparound when N == 64, so we convert to
450 // int64_t only at the very end to avoid UB.
451 return (UINT64_C(1)1UL << (N - 1)) - 1;
452}
453
454/// Checks if an unsigned integer fits into the given (dynamic) bit width.
455inline bool isUIntN(unsigned N, uint64_t x) {
456 return N >= 64 || x <= maxUIntN(N);
457}
458
459/// Checks if an signed integer fits into the given (dynamic) bit width.
460inline bool isIntN(unsigned N, int64_t x) {
461 return N >= 64 || (minIntN(N) <= x && x <= maxIntN(N));
462}
463
464/// Return true if the argument is a non-empty sequence of ones starting at the
465/// least significant bit with the remainder zero (32 bit version).
466/// Ex. isMask_32(0x0000FFFFU) == true.
467constexpr inline bool isMask_32(uint32_t Value) {
468 return Value && ((Value + 1) & Value) == 0;
469}
470
471/// Return true if the argument is a non-empty sequence of ones starting at the
472/// least significant bit with the remainder zero (64 bit version).
473constexpr inline bool isMask_64(uint64_t Value) {
474 return Value && ((Value + 1) & Value) == 0;
475}
476
477/// Return true if the argument contains a non-empty sequence of ones with the
478/// remainder zero (32 bit version.) Ex. isShiftedMask_32(0x0000FF00U) == true.
479constexpr inline bool isShiftedMask_32(uint32_t Value) {
480 return Value && isMask_32((Value - 1) | Value);
481}
482
483/// Return true if the argument contains a non-empty sequence of ones with the
484/// remainder zero (64 bit version.)
485constexpr inline bool isShiftedMask_64(uint64_t Value) {
486 return Value && isMask_64((Value - 1) | Value);
487}
488
489/// Return true if the argument is a power of two > 0.
490/// Ex. isPowerOf2_32(0x00100000U) == true (32 bit edition.)
491constexpr inline bool isPowerOf2_32(uint32_t Value) {
492 return Value && !(Value & (Value - 1));
493}
494
495/// Return true if the argument is a power of two > 0 (64 bit edition.)
496constexpr inline bool isPowerOf2_64(uint64_t Value) {
497 return Value && !(Value & (Value - 1));
498}
499
500/// Count the number of ones from the most significant bit to the first
501/// zero bit.
502///
503/// Ex. countLeadingOnes(0xFF0FFF00) == 8.
504/// Only unsigned integral types are allowed.
505///
506/// \param ZB the behavior on an input of all ones. Only ZB_Width and
507/// ZB_Undefined are valid arguments.
508template <typename T>
509unsigned countLeadingOnes(T Value, ZeroBehavior ZB = ZB_Width) {
510 static_assert(std::numeric_limits<T>::is_integer &&
511 !std::numeric_limits<T>::is_signed,
512 "Only unsigned integral types are allowed.");
513 return countLeadingZeros<T>(~Value, ZB);
514}
515
516/// Count the number of ones from the least significant bit to the first
517/// zero bit.
518///
519/// Ex. countTrailingOnes(0x00FF00FF) == 8.
520/// Only unsigned integral types are allowed.
521///
522/// \param ZB the behavior on an input of all ones. Only ZB_Width and
523/// ZB_Undefined are valid arguments.
524template <typename T>
525unsigned countTrailingOnes(T Value, ZeroBehavior ZB = ZB_Width) {
526 static_assert(std::numeric_limits<T>::is_integer &&
527 !std::numeric_limits<T>::is_signed,
528 "Only unsigned integral types are allowed.");
529 return countTrailingZeros<T>(~Value, ZB);
530}
531
532namespace detail {
533template <typename T, std::size_t SizeOfT> struct PopulationCounter {
534 static unsigned count(T Value) {
535 // Generic version, forward to 32 bits.
536 static_assert(SizeOfT <= 4, "Not implemented!");
537#if defined(__GNUC__4)
538 return __builtin_popcount(Value);
539#else
540 uint32_t v = Value;
541 v = v - ((v >> 1) & 0x55555555);
542 v = (v & 0x33333333) + ((v >> 2) & 0x33333333);
543 return ((v + (v >> 4) & 0xF0F0F0F) * 0x1010101) >> 24;
544#endif
545 }
546};
547
548template <typename T> struct PopulationCounter<T, 8> {
549 static unsigned count(T Value) {
550#if defined(__GNUC__4)
551 return __builtin_popcountll(Value);
552#else
553 uint64_t v = Value;
554 v = v - ((v >> 1) & 0x5555555555555555ULL);
555 v = (v & 0x3333333333333333ULL) + ((v >> 2) & 0x3333333333333333ULL);
556 v = (v + (v >> 4)) & 0x0F0F0F0F0F0F0F0FULL;
557 return unsigned((uint64_t)(v * 0x0101010101010101ULL) >> 56);
558#endif
559 }
560};
561} // namespace detail
562
563/// Count the number of set bits in a value.
564/// Ex. countPopulation(0xF000F000) = 8
565/// Returns 0 if the word is zero.
566template <typename T>
567inline unsigned countPopulation(T Value) {
568 static_assert(std::numeric_limits<T>::is_integer &&
569 !std::numeric_limits<T>::is_signed,
570 "Only unsigned integral types are allowed.");
571 return detail::PopulationCounter<T, sizeof(T)>::count(Value);
572}
573
574/// Compile time Log2.
575/// Valid only for positive powers of two.
576template <size_t kValue> constexpr inline size_t CTLog2() {
577 static_assert(kValue > 0 && llvm::isPowerOf2_64(kValue),
578 "Value is not a valid power of 2");
579 return 1 + CTLog2<kValue / 2>();
580}
581
582template <> constexpr inline size_t CTLog2<1>() { return 0; }
583
584/// Return the log base 2 of the specified value.
585inline double Log2(double Value) {
586#if defined(__ANDROID_API__) && __ANDROID_API__ < 18
587 return __builtin_log(Value) / __builtin_log(2.0);
588#else
589 return log2(Value);
590#endif
591}
592
593/// Return the floor log base 2 of the specified value, -1 if the value is zero.
594/// (32 bit edition.)
595/// Ex. Log2_32(32) == 5, Log2_32(1) == 0, Log2_32(0) == -1, Log2_32(6) == 2
596inline unsigned Log2_32(uint32_t Value) {
597 return 31 - countLeadingZeros(Value);
598}
599
600/// Return the floor log base 2 of the specified value, -1 if the value is zero.
601/// (64 bit edition.)
602inline unsigned Log2_64(uint64_t Value) {
603 return 63 - countLeadingZeros(Value);
604}
605
606/// Return the ceil log base 2 of the specified value, 32 if the value is zero.
607/// (32 bit edition).
608/// Ex. Log2_32_Ceil(32) == 5, Log2_32_Ceil(1) == 0, Log2_32_Ceil(6) == 3
609inline unsigned Log2_32_Ceil(uint32_t Value) {
610 return 32 - countLeadingZeros(Value - 1);
611}
612
613/// Return the ceil log base 2 of the specified value, 64 if the value is zero.
614/// (64 bit edition.)
615inline unsigned Log2_64_Ceil(uint64_t Value) {
616 return 64 - countLeadingZeros(Value - 1);
617}
618
619/// Return the greatest common divisor of the values using Euclid's algorithm.
620template <typename T>
621inline T greatestCommonDivisor(T A, T B) {
622 while (B) {
623 T Tmp = B;
624 B = A % B;
625 A = Tmp;
626 }
627 return A;
628}
629
630inline uint64_t GreatestCommonDivisor64(uint64_t A, uint64_t B) {
631 return greatestCommonDivisor<uint64_t>(A, B);
632}
633
634/// This function takes a 64-bit integer and returns the bit equivalent double.
635inline double BitsToDouble(uint64_t Bits) {
636 double D;
637 static_assert(sizeof(uint64_t) == sizeof(double), "Unexpected type sizes");
638 memcpy(&D, &Bits, sizeof(Bits));
639 return D;
640}
641
642/// This function takes a 32-bit integer and returns the bit equivalent float.
643inline float BitsToFloat(uint32_t Bits) {
644 float F;
645 static_assert(sizeof(uint32_t) == sizeof(float), "Unexpected type sizes");
646 memcpy(&F, &Bits, sizeof(Bits));
647 return F;
648}
649
650/// This function takes a double and returns the bit equivalent 64-bit integer.
651/// Note that copying doubles around changes the bits of NaNs on some hosts,
652/// notably x86, so this routine cannot be used if these bits are needed.
653inline uint64_t DoubleToBits(double Double) {
654 uint64_t Bits;
655 static_assert(sizeof(uint64_t) == sizeof(double), "Unexpected type sizes");
656 memcpy(&Bits, &Double, sizeof(Double));
657 return Bits;
658}
659
660/// This function takes a float and returns the bit equivalent 32-bit integer.
661/// Note that copying floats around changes the bits of NaNs on some hosts,
662/// notably x86, so this routine cannot be used if these bits are needed.
663inline uint32_t FloatToBits(float Float) {
664 uint32_t Bits;
665 static_assert(sizeof(uint32_t) == sizeof(float), "Unexpected type sizes");
666 memcpy(&Bits, &Float, sizeof(Float));
667 return Bits;
668}
669
670/// A and B are either alignments or offsets. Return the minimum alignment that
671/// may be assumed after adding the two together.
672constexpr inline uint64_t MinAlign(uint64_t A, uint64_t B) {
673 // The largest power of 2 that divides both A and B.
674 //
675 // Replace "-Value" by "1+~Value" in the following commented code to avoid
676 // MSVC warning C4146
677 // return (A | B) & -(A | B);
678 return (A | B) & (1 + ~(A | B));
679}
680
681/// Returns the next power of two (in 64-bits) that is strictly greater than A.
682/// Returns zero on overflow.
683inline uint64_t NextPowerOf2(uint64_t A) {
684 A |= (A >> 1);
685 A |= (A >> 2);
686 A |= (A >> 4);
687 A |= (A >> 8);
688 A |= (A >> 16);
689 A |= (A >> 32);
690 return A + 1;
691}
692
693/// Returns the power of two which is less than or equal to the given value.
694/// Essentially, it is a floor operation across the domain of powers of two.
695inline uint64_t PowerOf2Floor(uint64_t A) {
696 if (!A) return 0;
697 return 1ull << (63 - countLeadingZeros(A, ZB_Undefined));
698}
699
700/// Returns the power of two which is greater than or equal to the given value.
701/// Essentially, it is a ceil operation across the domain of powers of two.
702inline uint64_t PowerOf2Ceil(uint64_t A) {
703 if (!A)
704 return 0;
705 return NextPowerOf2(A - 1);
706}
707
708/// Returns the next integer (mod 2**64) that is greater than or equal to
709/// \p Value and is a multiple of \p Align. \p Align must be non-zero.
710///
711/// If non-zero \p Skew is specified, the return value will be a minimal
712/// integer that is greater than or equal to \p Value and equal to
713/// \p Align * N + \p Skew for some integer N. If \p Skew is larger than
714/// \p Align, its value is adjusted to '\p Skew mod \p Align'.
715///
716/// Examples:
717/// \code
718/// alignTo(5, 8) = 8
719/// alignTo(17, 8) = 24
720/// alignTo(~0LL, 8) = 0
721/// alignTo(321, 255) = 510
722///
723/// alignTo(5, 8, 7) = 7
724/// alignTo(17, 8, 1) = 17
725/// alignTo(~0LL, 8, 3) = 3
726/// alignTo(321, 255, 42) = 552
727/// \endcode
728inline uint64_t alignTo(uint64_t Value, uint64_t Align, uint64_t Skew = 0) {
729 assert(Align != 0u && "Align can't be 0.")(static_cast<void> (0));
730 Skew %= Align;
731 return (Value + Align - 1 - Skew) / Align * Align + Skew;
732}
733
734/// Returns the next integer (mod 2**64) that is greater than or equal to
735/// \p Value and is a multiple of \c Align. \c Align must be non-zero.
736template <uint64_t Align> constexpr inline uint64_t alignTo(uint64_t Value) {
737 static_assert(Align != 0u, "Align must be non-zero");
738 return (Value + Align - 1) / Align * Align;
739}
740
741/// Returns the integer ceil(Numerator / Denominator).
742inline uint64_t divideCeil(uint64_t Numerator, uint64_t Denominator) {
743 return alignTo(Numerator, Denominator) / Denominator;
744}
745
746/// Returns the integer nearest(Numerator / Denominator).
747inline uint64_t divideNearest(uint64_t Numerator, uint64_t Denominator) {
748 return (Numerator + (Denominator / 2)) / Denominator;
749}
750
751/// Returns the largest uint64_t less than or equal to \p Value and is
752/// \p Skew mod \p Align. \p Align must be non-zero
753inline uint64_t alignDown(uint64_t Value, uint64_t Align, uint64_t Skew = 0) {
754 assert(Align != 0u && "Align can't be 0.")(static_cast<void> (0));
755 Skew %= Align;
756 return (Value - Skew) / Align * Align + Skew;
757}
758
759/// Sign-extend the number in the bottom B bits of X to a 32-bit integer.
760/// Requires 0 < B <= 32.
761template <unsigned B> constexpr inline int32_t SignExtend32(uint32_t X) {
762 static_assert(B > 0, "Bit width can't be 0.");
763 static_assert(B <= 32, "Bit width out of range.");
764 return int32_t(X << (32 - B)) >> (32 - B);
765}
766
767/// Sign-extend the number in the bottom B bits of X to a 32-bit integer.
768/// Requires 0 < B <= 32.
769inline int32_t SignExtend32(uint32_t X, unsigned B) {
770 assert(B > 0 && "Bit width can't be 0.")(static_cast<void> (0));
771 assert(B <= 32 && "Bit width out of range.")(static_cast<void> (0));
772 return int32_t(X << (32 - B)) >> (32 - B);
773}
774
775/// Sign-extend the number in the bottom B bits of X to a 64-bit integer.
776/// Requires 0 < B <= 64.
777template <unsigned B> constexpr inline int64_t SignExtend64(uint64_t x) {
778 static_assert(B > 0, "Bit width can't be 0.");
779 static_assert(B <= 64, "Bit width out of range.");
780 return int64_t(x << (64 - B)) >> (64 - B);
781}
782
783/// Sign-extend the number in the bottom B bits of X to a 64-bit integer.
784/// Requires 0 < B <= 64.
785inline int64_t SignExtend64(uint64_t X, unsigned B) {
786 assert(B > 0 && "Bit width can't be 0.")(static_cast<void> (0));
787 assert(B <= 64 && "Bit width out of range.")(static_cast<void> (0));
788 return int64_t(X << (64 - B)) >> (64 - B);
789}
790
791/// Subtract two unsigned integers, X and Y, of type T and return the absolute
792/// value of the result.
793template <typename T>
794std::enable_if_t<std::is_unsigned<T>::value, T> AbsoluteDifference(T X, T Y) {
795 return X > Y ? (X - Y) : (Y - X);
796}
797
798/// Add two unsigned integers, X and Y, of type T. Clamp the result to the
799/// maximum representable value of T on overflow. ResultOverflowed indicates if
800/// the result is larger than the maximum representable value of type T.
801template <typename T>
802std::enable_if_t<std::is_unsigned<T>::value, T>
803SaturatingAdd(T X, T Y, bool *ResultOverflowed = nullptr) {
804 bool Dummy;
805 bool &Overflowed = ResultOverflowed ? *ResultOverflowed : Dummy;
806 // Hacker's Delight, p. 29
807 T Z = X + Y;
808 Overflowed = (Z < X || Z < Y);
809 if (Overflowed)
810 return std::numeric_limits<T>::max();
811 else
812 return Z;
813}
814
815/// Multiply two unsigned integers, X and Y, of type T. Clamp the result to the
816/// maximum representable value of T on overflow. ResultOverflowed indicates if
817/// the result is larger than the maximum representable value of type T.
818template <typename T>
819std::enable_if_t<std::is_unsigned<T>::value, T>
820SaturatingMultiply(T X, T Y, bool *ResultOverflowed = nullptr) {
821 bool Dummy;
822 bool &Overflowed = ResultOverflowed ? *ResultOverflowed : Dummy;
823
824 // Hacker's Delight, p. 30 has a different algorithm, but we don't use that
825 // because it fails for uint16_t (where multiplication can have undefined
826 // behavior due to promotion to int), and requires a division in addition
827 // to the multiplication.
828
829 Overflowed = false;
830
831 // Log2(Z) would be either Log2Z or Log2Z + 1.
832 // Special case: if X or Y is 0, Log2_64 gives -1, and Log2Z
833 // will necessarily be less than Log2Max as desired.
834 int Log2Z = Log2_64(X) + Log2_64(Y);
835 const T Max = std::numeric_limits<T>::max();
836 int Log2Max = Log2_64(Max);
837 if (Log2Z < Log2Max) {
838 return X * Y;
839 }
840 if (Log2Z > Log2Max) {
841 Overflowed = true;
842 return Max;
843 }
844
845 // We're going to use the top bit, and maybe overflow one
846 // bit past it. Multiply all but the bottom bit then add
847 // that on at the end.
848 T Z = (X >> 1) * Y;
849 if (Z & ~(Max >> 1)) {
850 Overflowed = true;
851 return Max;
852 }
853 Z <<= 1;
854 if (X & 1)
855 return SaturatingAdd(Z, Y, ResultOverflowed);
856
857 return Z;
858}
859
860/// Multiply two unsigned integers, X and Y, and add the unsigned integer, A to
861/// the product. Clamp the result to the maximum representable value of T on
862/// overflow. ResultOverflowed indicates if the result is larger than the
863/// maximum representable value of type T.
864template <typename T>
865std::enable_if_t<std::is_unsigned<T>::value, T>
866SaturatingMultiplyAdd(T X, T Y, T A, bool *ResultOverflowed = nullptr) {
867 bool Dummy;
868 bool &Overflowed = ResultOverflowed ? *ResultOverflowed : Dummy;
869
870 T Product = SaturatingMultiply(X, Y, &Overflowed);
871 if (Overflowed)
872 return Product;
873
874 return SaturatingAdd(A, Product, &Overflowed);
875}
876
877/// Use this rather than HUGE_VALF; the latter causes warnings on MSVC.
878extern const float huge_valf;
879
880
881/// Add two signed integers, computing the two's complement truncated result,
882/// returning true if overflow occured.
883template <typename T>
884std::enable_if_t<std::is_signed<T>::value, T> AddOverflow(T X, T Y, T &Result) {
885#if __has_builtin(__builtin_add_overflow)1
886 return __builtin_add_overflow(X, Y, &Result);
887#else
888 // Perform the unsigned addition.
889 using U = std::make_unsigned_t<T>;
890 const U UX = static_cast<U>(X);
891 const U UY = static_cast<U>(Y);
892 const U UResult = UX + UY;
893
894 // Convert to signed.
895 Result = static_cast<T>(UResult);
896
897 // Adding two positive numbers should result in a positive number.
898 if (X > 0 && Y > 0)
899 return Result <= 0;
900 // Adding two negatives should result in a negative number.
901 if (X < 0 && Y < 0)
902 return Result >= 0;
903 return false;
904#endif
905}
906
907/// Subtract two signed integers, computing the two's complement truncated
908/// result, returning true if an overflow ocurred.
909template <typename T>
910std::enable_if_t<std::is_signed<T>::value, T> SubOverflow(T X, T Y, T &Result) {
911#if __has_builtin(__builtin_sub_overflow)1
912 return __builtin_sub_overflow(X, Y, &Result);
913#else
914 // Perform the unsigned addition.
915 using U = std::make_unsigned_t<T>;
916 const U UX = static_cast<U>(X);
917 const U UY = static_cast<U>(Y);
918 const U UResult = UX - UY;
919
920 // Convert to signed.
921 Result = static_cast<T>(UResult);
922
923 // Subtracting a positive number from a negative results in a negative number.
924 if (X <= 0 && Y > 0)
925 return Result >= 0;
926 // Subtracting a negative number from a positive results in a positive number.
927 if (X >= 0 && Y < 0)
928 return Result <= 0;
929 return false;
930#endif
931}
932
933/// Multiply two signed integers, computing the two's complement truncated
934/// result, returning true if an overflow ocurred.
935template <typename T>
936std::enable_if_t<std::is_signed<T>::value, T> MulOverflow(T X, T Y, T &Result) {
937 // Perform the unsigned multiplication on absolute values.
938 using U = std::make_unsigned_t<T>;
939 const U UX = X < 0 ? (0 - static_cast<U>(X)) : static_cast<U>(X);
940 const U UY = Y < 0 ? (0 - static_cast<U>(Y)) : static_cast<U>(Y);
941 const U UResult = UX * UY;
942
943 // Convert to signed.
944 const bool IsNegative = (X < 0) ^ (Y < 0);
945 Result = IsNegative ? (0 - UResult) : UResult;
946
947 // If any of the args was 0, result is 0 and no overflow occurs.
948 if (UX == 0 || UY == 0)
949 return false;
950
951 // UX and UY are in [1, 2^n], where n is the number of digits.
952 // Check how the max allowed absolute value (2^n for negative, 2^(n-1) for
953 // positive) divided by an argument compares to the other.
954 if (IsNegative)
955 return UX > (static_cast<U>(std::numeric_limits<T>::max()) + U(1)) / UY;
956 else
957 return UX > (static_cast<U>(std::numeric_limits<T>::max())) / UY;
958}
959
960} // End llvm namespace
961
962#endif

/usr/lib/gcc/x86_64-linux-gnu/10/../../../../include/c++/10/limits

1// The template and inlines for the numeric_limits classes. -*- C++ -*-
2
3// Copyright (C) 1999-2020 Free Software Foundation, Inc.
4//
5// This file is part of the GNU ISO C++ Library. This library is free
6// software; you can redistribute it and/or modify it under the
7// terms of the GNU General Public License as published by the
8// Free Software Foundation; either version 3, or (at your option)
9// any later version.
10
11// This library is distributed in the hope that it will be useful,
12// but WITHOUT ANY WARRANTY; without even the implied warranty of
13// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14// GNU General Public License for more details.
15
16// Under Section 7 of GPL version 3, you are granted additional
17// permissions described in the GCC Runtime Library Exception, version
18// 3.1, as published by the Free Software Foundation.
19
20// You should have received a copy of the GNU General Public License and
21// a copy of the GCC Runtime Library Exception along with this program;
22// see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
23// <http://www.gnu.org/licenses/>.
24
25/** @file include/limits
26 * This is a Standard C++ Library header.
27 */
28
29// Note: this is not a conforming implementation.
30// Written by Gabriel Dos Reis <gdr@codesourcery.com>
31
32//
33// ISO 14882:1998
34// 18.2.1
35//
36
37#ifndef _GLIBCXX_NUMERIC_LIMITS1
38#define _GLIBCXX_NUMERIC_LIMITS1 1
39
40#pragma GCC system_header
41
42#include <bits/c++config.h>
43
44//
45// The numeric_limits<> traits document implementation-defined aspects
46// of fundamental arithmetic data types (integers and floating points).
47// From Standard C++ point of view, there are 14 such types:
48// * integers
49// bool (1)
50// char, signed char, unsigned char, wchar_t (4)
51// short, unsigned short (2)
52// int, unsigned (2)
53// long, unsigned long (2)
54//
55// * floating points
56// float (1)
57// double (1)
58// long double (1)
59//
60// GNU C++ understands (where supported by the host C-library)
61// * integer
62// long long, unsigned long long (2)
63//
64// which brings us to 16 fundamental arithmetic data types in GNU C++.
65//
66//
67// Since a numeric_limits<> is a bit tricky to get right, we rely on
68// an interface composed of macros which should be defined in config/os
69// or config/cpu when they differ from the generic (read arbitrary)
70// definitions given here.
71//
72
73// These values can be overridden in the target configuration file.
74// The default values are appropriate for many 32-bit targets.
75
76// GCC only intrinsically supports modulo integral types. The only remaining
77// integral exceptional values is division by zero. Only targets that do not
78// signal division by zero in some "hard to ignore" way should use false.
79#ifndef __glibcxx_integral_trapstrue
80# define __glibcxx_integral_trapstrue true
81#endif
82
83// float
84//
85
86// Default values. Should be overridden in configuration files if necessary.
87
88#ifndef __glibcxx_float_has_denorm_loss
89# define __glibcxx_float_has_denorm_loss false
90#endif
91#ifndef __glibcxx_float_traps
92# define __glibcxx_float_traps false
93#endif
94#ifndef __glibcxx_float_tinyness_before
95# define __glibcxx_float_tinyness_before false
96#endif
97
98// double
99
100// Default values. Should be overridden in configuration files if necessary.
101
102#ifndef __glibcxx_double_has_denorm_loss
103# define __glibcxx_double_has_denorm_loss false
104#endif
105#ifndef __glibcxx_double_traps
106# define __glibcxx_double_traps false
107#endif
108#ifndef __glibcxx_double_tinyness_before
109# define __glibcxx_double_tinyness_before false
110#endif
111
112// long double
113
114// Default values. Should be overridden in configuration files if necessary.
115
116#ifndef __glibcxx_long_double_has_denorm_loss
117# define __glibcxx_long_double_has_denorm_loss false
118#endif
119#ifndef __glibcxx_long_double_traps
120# define __glibcxx_long_double_traps false
121#endif
122#ifndef __glibcxx_long_double_tinyness_before
123# define __glibcxx_long_double_tinyness_before false
124#endif
125
126// You should not need to define any macros below this point.
127
128#define __glibcxx_signed_b(T,B)((T)(-1) < 0) ((T)(-1) < 0)
129
130#define __glibcxx_min_b(T,B)(((T)(-1) < 0) ? -(((T)(-1) < 0) ? (((((T)1 << ((
B - ((T)(-1) < 0)) - 1)) - 1) << 1) + 1) : ~(T)0) - 1
: (T)0)
\
131 (__glibcxx_signed_b (T,B)((T)(-1) < 0) ? -__glibcxx_max_b (T,B)(((T)(-1) < 0) ? (((((T)1 << ((B - ((T)(-1) < 0))
- 1)) - 1) << 1) + 1) : ~(T)0)
- 1 : (T)0)
132
133#define __glibcxx_max_b(T,B)(((T)(-1) < 0) ? (((((T)1 << ((B - ((T)(-1) < 0))
- 1)) - 1) << 1) + 1) : ~(T)0)
\
134 (__glibcxx_signed_b (T,B)((T)(-1) < 0) ? \
135 (((((T)1 << (__glibcxx_digits_b (T,B)(B - ((T)(-1) < 0)) - 1)) - 1) << 1) + 1) : ~(T)0)
136
137#define __glibcxx_digits_b(T,B)(B - ((T)(-1) < 0)) \
138 (B - __glibcxx_signed_b (T,B)((T)(-1) < 0))
139
140// The fraction 643/2136 approximates log10(2) to 7 significant digits.
141#define __glibcxx_digits10_b(T,B)((B - ((T)(-1) < 0)) * 643L / 2136) \
142 (__glibcxx_digits_b (T,B)(B - ((T)(-1) < 0)) * 643L / 2136)
143
144#define __glibcxx_signed(T) \
145 __glibcxx_signed_b (T, sizeof(T) * __CHAR_BIT__)((T)(-1) < 0)
146#define __glibcxx_min(T) \
147 __glibcxx_min_b (T, sizeof(T) * __CHAR_BIT__)(((T)(-1) < 0) ? -(((T)(-1) < 0) ? (((((T)1 << ((
sizeof(T) * 8 - ((T)(-1) < 0)) - 1)) - 1) << 1) + 1)
: ~(T)0) - 1 : (T)0)
148#define __glibcxx_max(T) \
149 __glibcxx_max_b (T, sizeof(T) * __CHAR_BIT__)(((T)(-1) < 0) ? (((((T)1 << ((sizeof(T) * 8 - ((T)(
-1) < 0)) - 1)) - 1) << 1) + 1) : ~(T)0)
150#define __glibcxx_digits(T) \
151 __glibcxx_digits_b (T, sizeof(T) * __CHAR_BIT__)(sizeof(T) * 8 - ((T)(-1) < 0))
152#define __glibcxx_digits10(T) \
153 __glibcxx_digits10_b (T, sizeof(T) * __CHAR_BIT__)((sizeof(T) * 8 - ((T)(-1) < 0)) * 643L / 2136)
154
155#define __glibcxx_max_digits10(T) \
156 (2 + (T) * 643L / 2136)
157
158namespace std _GLIBCXX_VISIBILITY(default)__attribute__ ((__visibility__ ("default")))
159{
160_GLIBCXX_BEGIN_NAMESPACE_VERSION
161
162 /**
163 * @brief Describes the rounding style for floating-point types.
164 *
165 * This is used in the std::numeric_limits class.
166 */
167 enum float_round_style
168 {
169 round_indeterminate = -1, /// Intermediate.
170 round_toward_zero = 0, /// To zero.
171 round_to_nearest = 1, /// To the nearest representable value.
172 round_toward_infinity = 2, /// To infinity.
173 round_toward_neg_infinity = 3 /// To negative infinity.
174 };
175
176 /**
177 * @brief Describes the denormalization for floating-point types.
178 *
179 * These values represent the presence or absence of a variable number
180 * of exponent bits. This type is used in the std::numeric_limits class.
181 */
182 enum float_denorm_style
183 {
184 /// Indeterminate at compile time whether denormalized values are allowed.
185 denorm_indeterminate = -1,
186 /// The type does not allow denormalized values.
187 denorm_absent = 0,
188 /// The type allows denormalized values.
189 denorm_present = 1
190 };
191
192 /**
193 * @brief Part of std::numeric_limits.
194 *
195 * The @c static @c const members are usable as integral constant
196 * expressions.
197 *
198 * @note This is a separate class for purposes of efficiency; you
199 * should only access these members as part of an instantiation
200 * of the std::numeric_limits class.
201 */
202 struct __numeric_limits_base
203 {
204 /** This will be true for all fundamental types (which have
205 specializations), and false for everything else. */
206 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_specialized = false;
207
208 /** The number of @c radix digits that be represented without change: for
209 integer types, the number of non-sign bits in the mantissa; for
210 floating types, the number of @c radix digits in the mantissa. */
211 static _GLIBCXX_USE_CONSTEXPRconstexpr int digits = 0;
212
213 /** The number of base 10 digits that can be represented without change. */
214 static _GLIBCXX_USE_CONSTEXPRconstexpr int digits10 = 0;
215
216#if __cplusplus201402L >= 201103L
217 /** The number of base 10 digits required to ensure that values which
218 differ are always differentiated. */
219 static constexpr int max_digits10 = 0;
220#endif
221
222 /** True if the type is signed. */
223 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_signed = false;
224
225 /** True if the type is integer. */
226 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_integer = false;
227
228 /** True if the type uses an exact representation. All integer types are
229 exact, but not all exact types are integer. For example, rational and
230 fixed-exponent representations are exact but not integer. */
231 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_exact = false;
232
233 /** For integer types, specifies the base of the representation. For
234 floating types, specifies the base of the exponent representation. */
235 static _GLIBCXX_USE_CONSTEXPRconstexpr int radix = 0;
236
237 /** The minimum negative integer such that @c radix raised to the power of
238 (one less than that integer) is a normalized floating point number. */
239 static _GLIBCXX_USE_CONSTEXPRconstexpr int min_exponent = 0;
240
241 /** The minimum negative integer such that 10 raised to that power is in
242 the range of normalized floating point numbers. */
243 static _GLIBCXX_USE_CONSTEXPRconstexpr int min_exponent10 = 0;
244
245 /** The maximum positive integer such that @c radix raised to the power of
246 (one less than that integer) is a representable finite floating point
247 number. */
248 static _GLIBCXX_USE_CONSTEXPRconstexpr int max_exponent = 0;
249
250 /** The maximum positive integer such that 10 raised to that power is in
251 the range of representable finite floating point numbers. */
252 static _GLIBCXX_USE_CONSTEXPRconstexpr int max_exponent10 = 0;
253
254 /** True if the type has a representation for positive infinity. */
255 static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_infinity = false;
256
257 /** True if the type has a representation for a quiet (non-signaling)
258 Not a Number. */
259 static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_quiet_NaN = false;
260
261 /** True if the type has a representation for a signaling
262 Not a Number. */
263 static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_signaling_NaN = false;
264
265 /** See std::float_denorm_style for more information. */
266 static _GLIBCXX_USE_CONSTEXPRconstexpr float_denorm_style has_denorm = denorm_absent;
267
268 /** True if loss of accuracy is detected as a denormalization loss,
269 rather than as an inexact result. */
270 static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_denorm_loss = false;
271
272 /** True if-and-only-if the type adheres to the IEC 559 standard, also
273 known as IEEE 754. (Only makes sense for floating point types.) */
274 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_iec559 = false;
275
276 /** True if the set of values representable by the type is
277 finite. All built-in types are bounded, this member would be
278 false for arbitrary precision types. */
279 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_bounded = false;
280
281 /** True if the type is @e modulo. A type is modulo if, for any
282 operation involving +, -, or * on values of that type whose
283 result would fall outside the range [min(),max()], the value
284 returned differs from the true value by an integer multiple of
285 max() - min() + 1. On most machines, this is false for floating
286 types, true for unsigned integers, and true for signed integers.
287 See PR22200 about signed integers. */
288 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_modulo = false;
289
290 /** True if trapping is implemented for this type. */
291 static _GLIBCXX_USE_CONSTEXPRconstexpr bool traps = false;
292
293 /** True if tininess is detected before rounding. (see IEC 559) */
294 static _GLIBCXX_USE_CONSTEXPRconstexpr bool tinyness_before = false;
295
296 /** See std::float_round_style for more information. This is only
297 meaningful for floating types; integer types will all be
298 round_toward_zero. */
299 static _GLIBCXX_USE_CONSTEXPRconstexpr float_round_style round_style =
300 round_toward_zero;
301 };
302
303 /**
304 * @brief Properties of fundamental types.
305 *
306 * This class allows a program to obtain information about the
307 * representation of a fundamental type on a given platform. For
308 * non-fundamental types, the functions will return 0 and the data
309 * members will all be @c false.
310 */
311 template<typename _Tp>
312 struct numeric_limits : public __numeric_limits_base
313 {
314 /** The minimum finite value, or for floating types with
315 denormalization, the minimum positive normalized value. */
316 static _GLIBCXX_CONSTEXPRconstexpr _Tp
317 min() _GLIBCXX_USE_NOEXCEPTnoexcept { return _Tp(); }
318
319 /** The maximum finite value. */
320 static _GLIBCXX_CONSTEXPRconstexpr _Tp
321 max() _GLIBCXX_USE_NOEXCEPTnoexcept { return _Tp(); }
322
323#if __cplusplus201402L >= 201103L
324 /** A finite value x such that there is no other finite value y
325 * where y < x. */
326 static constexpr _Tp
327 lowest() noexcept { return _Tp(); }
328#endif
329
330 /** The @e machine @e epsilon: the difference between 1 and the least
331 value greater than 1 that is representable. */
332 static _GLIBCXX_CONSTEXPRconstexpr _Tp
333 epsilon() _GLIBCXX_USE_NOEXCEPTnoexcept { return _Tp(); }
334
335 /** The maximum rounding error measurement (see LIA-1). */
336 static _GLIBCXX_CONSTEXPRconstexpr _Tp
337 round_error() _GLIBCXX_USE_NOEXCEPTnoexcept { return _Tp(); }
338
339 /** The representation of positive infinity, if @c has_infinity. */
340 static _GLIBCXX_CONSTEXPRconstexpr _Tp
341 infinity() _GLIBCXX_USE_NOEXCEPTnoexcept { return _Tp(); }
342
343 /** The representation of a quiet Not a Number,
344 if @c has_quiet_NaN. */
345 static _GLIBCXX_CONSTEXPRconstexpr _Tp
346 quiet_NaN() _GLIBCXX_USE_NOEXCEPTnoexcept { return _Tp(); }
347
348 /** The representation of a signaling Not a Number, if
349 @c has_signaling_NaN. */
350 static _GLIBCXX_CONSTEXPRconstexpr _Tp
351 signaling_NaN() _GLIBCXX_USE_NOEXCEPTnoexcept { return _Tp(); }
352
353 /** The minimum positive denormalized value. For types where
354 @c has_denorm is false, this is the minimum positive normalized
355 value. */
356 static _GLIBCXX_CONSTEXPRconstexpr _Tp
357 denorm_min() _GLIBCXX_USE_NOEXCEPTnoexcept { return _Tp(); }
358 };
359
360 // _GLIBCXX_RESOLVE_LIB_DEFECTS
361 // 559. numeric_limits<const T>
362
363 template<typename _Tp>
364 struct numeric_limits<const _Tp>
365 : public numeric_limits<_Tp> { };
366
367 template<typename _Tp>
368 struct numeric_limits<volatile _Tp>
369 : public numeric_limits<_Tp> { };
370
371 template<typename _Tp>
372 struct numeric_limits<const volatile _Tp>
373 : public numeric_limits<_Tp> { };
374
375 // Now there follow 16 explicit specializations. Yes, 16. Make sure
376 // you get the count right. (18 in C++11 mode, with char16_t and char32_t.)
377 // (+1 if char8_t is enabled.)
378
379 // _GLIBCXX_RESOLVE_LIB_DEFECTS
380 // 184. numeric_limits<bool> wording problems
381
382 /// numeric_limits<bool> specialization.
383 template<>
384 struct numeric_limits<bool>
385 {
386 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_specialized = true;
387
388 static _GLIBCXX_CONSTEXPRconstexpr bool
389 min() _GLIBCXX_USE_NOEXCEPTnoexcept { return false; }
390
391 static _GLIBCXX_CONSTEXPRconstexpr bool
392 max() _GLIBCXX_USE_NOEXCEPTnoexcept { return true; }
393
394#if __cplusplus201402L >= 201103L
395 static constexpr bool
396 lowest() noexcept { return min(); }
397#endif
398 static _GLIBCXX_USE_CONSTEXPRconstexpr int digits = 1;
399 static _GLIBCXX_USE_CONSTEXPRconstexpr int digits10 = 0;
400#if __cplusplus201402L >= 201103L
401 static constexpr int max_digits10 = 0;
402#endif
403 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_signed = false;
404 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_integer = true;
405 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_exact = true;
406 static _GLIBCXX_USE_CONSTEXPRconstexpr int radix = 2;
407
408 static _GLIBCXX_CONSTEXPRconstexpr bool
409 epsilon() _GLIBCXX_USE_NOEXCEPTnoexcept { return false; }
410
411 static _GLIBCXX_CONSTEXPRconstexpr bool
412 round_error() _GLIBCXX_USE_NOEXCEPTnoexcept { return false; }
413
414 static _GLIBCXX_USE_CONSTEXPRconstexpr int min_exponent = 0;
415 static _GLIBCXX_USE_CONSTEXPRconstexpr int min_exponent10 = 0;
416 static _GLIBCXX_USE_CONSTEXPRconstexpr int max_exponent = 0;
417 static _GLIBCXX_USE_CONSTEXPRconstexpr int max_exponent10 = 0;
418
419 static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_infinity = false;
420 static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_quiet_NaN = false;
421 static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_signaling_NaN = false;
422 static _GLIBCXX_USE_CONSTEXPRconstexpr float_denorm_style has_denorm
423 = denorm_absent;
424 static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_denorm_loss = false;
425
426 static _GLIBCXX_CONSTEXPRconstexpr bool
427 infinity() _GLIBCXX_USE_NOEXCEPTnoexcept { return false; }
428
429 static _GLIBCXX_CONSTEXPRconstexpr bool
430 quiet_NaN() _GLIBCXX_USE_NOEXCEPTnoexcept { return false; }
431
432 static _GLIBCXX_CONSTEXPRconstexpr bool
433 signaling_NaN() _GLIBCXX_USE_NOEXCEPTnoexcept { return false; }
434
435 static _GLIBCXX_CONSTEXPRconstexpr bool
436 denorm_min() _GLIBCXX_USE_NOEXCEPTnoexcept { return false; }
437
438 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_iec559 = false;
439 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_bounded = true;
440 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_modulo = false;
441
442 // It is not clear what it means for a boolean type to trap.
443 // This is a DR on the LWG issue list. Here, I use integer
444 // promotion semantics.
445 static _GLIBCXX_USE_CONSTEXPRconstexpr bool traps = __glibcxx_integral_trapstrue;
446 static _GLIBCXX_USE_CONSTEXPRconstexpr bool tinyness_before = false;
447 static _GLIBCXX_USE_CONSTEXPRconstexpr float_round_style round_style
448 = round_toward_zero;
449 };
450
451 /// numeric_limits<char> specialization.
452 template<>
453 struct numeric_limits<char>
454 {
455 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_specialized = true;
456
457 static _GLIBCXX_CONSTEXPRconstexpr char
458 min() _GLIBCXX_USE_NOEXCEPTnoexcept { return __glibcxx_min(char); }
459
460 static _GLIBCXX_CONSTEXPRconstexpr char
461 max() _GLIBCXX_USE_NOEXCEPTnoexcept { return __glibcxx_max(char); }
462
463#if __cplusplus201402L >= 201103L
464 static constexpr char
465 lowest() noexcept { return min(); }
466#endif
467
468 static _GLIBCXX_USE_CONSTEXPRconstexpr int digits = __glibcxx_digits (char);
469 static _GLIBCXX_USE_CONSTEXPRconstexpr int digits10 = __glibcxx_digits10 (char);
470#if __cplusplus201402L >= 201103L
471 static constexpr int max_digits10 = 0;
472#endif
473 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_signed = __glibcxx_signed (char);
474 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_integer = true;
475 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_exact = true;
476 static _GLIBCXX_USE_CONSTEXPRconstexpr int radix = 2;
477
478 static _GLIBCXX_CONSTEXPRconstexpr char
479 epsilon() _GLIBCXX_USE_NOEXCEPTnoexcept { return 0; }
480
481 static _GLIBCXX_CONSTEXPRconstexpr char
482 round_error() _GLIBCXX_USE_NOEXCEPTnoexcept { return 0; }
483
484 static _GLIBCXX_USE_CONSTEXPRconstexpr int min_exponent = 0;
485 static _GLIBCXX_USE_CONSTEXPRconstexpr int min_exponent10 = 0;
486 static _GLIBCXX_USE_CONSTEXPRconstexpr int max_exponent = 0;
487 static _GLIBCXX_USE_CONSTEXPRconstexpr int max_exponent10 = 0;
488
489 static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_infinity = false;
490 static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_quiet_NaN = false;
491 static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_signaling_NaN = false;
492 static _GLIBCXX_USE_CONSTEXPRconstexpr float_denorm_style has_denorm
493 = denorm_absent;
494 static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_denorm_loss = false;
495
496 static _GLIBCXX_CONSTEXPRconstexpr
497 char infinity() _GLIBCXX_USE_NOEXCEPTnoexcept { return char(); }
498
499 static _GLIBCXX_CONSTEXPRconstexpr char
500 quiet_NaN() _GLIBCXX_USE_NOEXCEPTnoexcept { return char(); }
501
502 static _GLIBCXX_CONSTEXPRconstexpr char
503 signaling_NaN() _GLIBCXX_USE_NOEXCEPTnoexcept { return char(); }
504
505 static _GLIBCXX_CONSTEXPRconstexpr char
506 denorm_min() _GLIBCXX_USE_NOEXCEPTnoexcept { return static_cast<char>(0); }
507
508 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_iec559 = false;
509 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_bounded = true;
510 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_modulo = !is_signed;
511
512 static _GLIBCXX_USE_CONSTEXPRconstexpr bool traps = __glibcxx_integral_trapstrue;
513 static _GLIBCXX_USE_CONSTEXPRconstexpr bool tinyness_before = false;
514 static _GLIBCXX_USE_CONSTEXPRconstexpr float_round_style round_style
515 = round_toward_zero;
516 };
517
518 /// numeric_limits<signed char> specialization.
519 template<>
520 struct numeric_limits<signed char>
521 {
522 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_specialized = true;
523
524 static _GLIBCXX_CONSTEXPRconstexpr signed char
525 min() _GLIBCXX_USE_NOEXCEPTnoexcept { return -__SCHAR_MAX__127 - 1; }
526
527 static _GLIBCXX_CONSTEXPRconstexpr signed char
528 max() _GLIBCXX_USE_NOEXCEPTnoexcept { return __SCHAR_MAX__127; }
529
530#if __cplusplus201402L >= 201103L
531 static constexpr signed char
532 lowest() noexcept { return min(); }
533#endif
534
535 static _GLIBCXX_USE_CONSTEXPRconstexpr int digits = __glibcxx_digits (signed char);
536 static _GLIBCXX_USE_CONSTEXPRconstexpr int digits10
537 = __glibcxx_digits10 (signed char);
538#if __cplusplus201402L >= 201103L
539 static constexpr int max_digits10 = 0;
540#endif
541 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_signed = true;
542 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_integer = true;
543 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_exact = true;
544 static _GLIBCXX_USE_CONSTEXPRconstexpr int radix = 2;
545
546 static _GLIBCXX_CONSTEXPRconstexpr signed char
547 epsilon() _GLIBCXX_USE_NOEXCEPTnoexcept { return 0; }
548
549 static _GLIBCXX_CONSTEXPRconstexpr signed char
550 round_error() _GLIBCXX_USE_NOEXCEPTnoexcept { return 0; }
551
552 static _GLIBCXX_USE_CONSTEXPRconstexpr int min_exponent = 0;
553 static _GLIBCXX_USE_CONSTEXPRconstexpr int min_exponent10 = 0;
554 static _GLIBCXX_USE_CONSTEXPRconstexpr int max_exponent = 0;
555 static _GLIBCXX_USE_CONSTEXPRconstexpr int max_exponent10 = 0;
556
557 static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_infinity = false;
558 static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_quiet_NaN = false;
559 static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_signaling_NaN = false;
560 static _GLIBCXX_USE_CONSTEXPRconstexpr float_denorm_style has_denorm
561 = denorm_absent;
562 static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_denorm_loss = false;
563
564 static _GLIBCXX_CONSTEXPRconstexpr signed char
565 infinity() _GLIBCXX_USE_NOEXCEPTnoexcept { return static_cast<signed char>(0); }
566
567 static _GLIBCXX_CONSTEXPRconstexpr signed char
568 quiet_NaN() _GLIBCXX_USE_NOEXCEPTnoexcept { return static_cast<signed char>(0); }
569
570 static _GLIBCXX_CONSTEXPRconstexpr signed char
571 signaling_NaN() _GLIBCXX_USE_NOEXCEPTnoexcept
572 { return static_cast<signed char>(0); }
573
574 static _GLIBCXX_CONSTEXPRconstexpr signed char
575 denorm_min() _GLIBCXX_USE_NOEXCEPTnoexcept
576 { return static_cast<signed char>(0); }
577
578 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_iec559 = false;
579 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_bounded = true;
580 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_modulo = false;
581
582 static _GLIBCXX_USE_CONSTEXPRconstexpr bool traps = __glibcxx_integral_trapstrue;
583 static _GLIBCXX_USE_CONSTEXPRconstexpr bool tinyness_before = false;
584 static _GLIBCXX_USE_CONSTEXPRconstexpr float_round_style round_style
585 = round_toward_zero;
586 };
587
588 /// numeric_limits<unsigned char> specialization.
589 template<>
590 struct numeric_limits<unsigned char>
591 {
592 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_specialized = true;
593
594 static _GLIBCXX_CONSTEXPRconstexpr unsigned char
595 min() _GLIBCXX_USE_NOEXCEPTnoexcept { return 0; }
596
597 static _GLIBCXX_CONSTEXPRconstexpr unsigned char
598 max() _GLIBCXX_USE_NOEXCEPTnoexcept { return __SCHAR_MAX__127 * 2U + 1; }
599
600#if __cplusplus201402L >= 201103L
601 static constexpr unsigned char
602 lowest() noexcept { return min(); }
603#endif
604
605 static _GLIBCXX_USE_CONSTEXPRconstexpr int digits
606 = __glibcxx_digits (unsigned char);
607 static _GLIBCXX_USE_CONSTEXPRconstexpr int digits10
608 = __glibcxx_digits10 (unsigned char);
609#if __cplusplus201402L >= 201103L
610 static constexpr int max_digits10 = 0;
611#endif
612 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_signed = false;
613 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_integer = true;
614 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_exact = true;
615 static _GLIBCXX_USE_CONSTEXPRconstexpr int radix = 2;
616
617 static _GLIBCXX_CONSTEXPRconstexpr unsigned char
618 epsilon() _GLIBCXX_USE_NOEXCEPTnoexcept { return 0; }
619
620 static _GLIBCXX_CONSTEXPRconstexpr unsigned char
621 round_error() _GLIBCXX_USE_NOEXCEPTnoexcept { return 0; }
622
623 static _GLIBCXX_USE_CONSTEXPRconstexpr int min_exponent = 0;
624 static _GLIBCXX_USE_CONSTEXPRconstexpr int min_exponent10 = 0;
625 static _GLIBCXX_USE_CONSTEXPRconstexpr int max_exponent = 0;
626 static _GLIBCXX_USE_CONSTEXPRconstexpr int max_exponent10 = 0;
627
628 static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_infinity = false;
629 static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_quiet_NaN = false;
630 static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_signaling_NaN = false;
631 static _GLIBCXX_USE_CONSTEXPRconstexpr float_denorm_style has_denorm
632 = denorm_absent;
633 static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_denorm_loss = false;
634
635 static _GLIBCXX_CONSTEXPRconstexpr unsigned char
636 infinity() _GLIBCXX_USE_NOEXCEPTnoexcept
637 { return static_cast<unsigned char>(0); }
638
639 static _GLIBCXX_CONSTEXPRconstexpr unsigned char
640 quiet_NaN() _GLIBCXX_USE_NOEXCEPTnoexcept
641 { return static_cast<unsigned char>(0); }
642
643 static _GLIBCXX_CONSTEXPRconstexpr unsigned char
644 signaling_NaN() _GLIBCXX_USE_NOEXCEPTnoexcept
645 { return static_cast<unsigned char>(0); }
646
647 static _GLIBCXX_CONSTEXPRconstexpr unsigned char
648 denorm_min() _GLIBCXX_USE_NOEXCEPTnoexcept
649 { return static_cast<unsigned char>(0); }
650
651 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_iec559 = false;
652 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_bounded = true;
653 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_modulo = true;
654
655 static _GLIBCXX_USE_CONSTEXPRconstexpr bool traps = __glibcxx_integral_trapstrue;
656 static _GLIBCXX_USE_CONSTEXPRconstexpr bool tinyness_before = false;
657 static _GLIBCXX_USE_CONSTEXPRconstexpr float_round_style round_style
658 = round_toward_zero;
659 };
660
661 /// numeric_limits<wchar_t> specialization.
662 template<>
663 struct numeric_limits<wchar_t>
664 {
665 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_specialized = true;
666
667 static _GLIBCXX_CONSTEXPRconstexpr wchar_t
668 min() _GLIBCXX_USE_NOEXCEPTnoexcept { return __glibcxx_min (wchar_t); }
669
670 static _GLIBCXX_CONSTEXPRconstexpr wchar_t
671 max() _GLIBCXX_USE_NOEXCEPTnoexcept { return __glibcxx_max (wchar_t); }
672
673#if __cplusplus201402L >= 201103L
674 static constexpr wchar_t
675 lowest() noexcept { return min(); }
676#endif
677
678 static _GLIBCXX_USE_CONSTEXPRconstexpr int digits = __glibcxx_digits (wchar_t);
679 static _GLIBCXX_USE_CONSTEXPRconstexpr int digits10
680 = __glibcxx_digits10 (wchar_t);
681#if __cplusplus201402L >= 201103L
682 static constexpr int max_digits10 = 0;
683#endif
684 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_signed = __glibcxx_signed (wchar_t);
685 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_integer = true;
686 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_exact = true;
687 static _GLIBCXX_USE_CONSTEXPRconstexpr int radix = 2;
688
689 static _GLIBCXX_CONSTEXPRconstexpr wchar_t
690 epsilon() _GLIBCXX_USE_NOEXCEPTnoexcept { return 0; }
691
692 static _GLIBCXX_CONSTEXPRconstexpr wchar_t
693 round_error() _GLIBCXX_USE_NOEXCEPTnoexcept { return 0; }
694
695 static _GLIBCXX_USE_CONSTEXPRconstexpr int min_exponent = 0;
696 static _GLIBCXX_USE_CONSTEXPRconstexpr int min_exponent10 = 0;
697 static _GLIBCXX_USE_CONSTEXPRconstexpr int max_exponent = 0;
698 static _GLIBCXX_USE_CONSTEXPRconstexpr int max_exponent10 = 0;
699
700 static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_infinity = false;
701 static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_quiet_NaN = false;
702 static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_signaling_NaN = false;
703 static _GLIBCXX_USE_CONSTEXPRconstexpr float_denorm_style has_denorm
704 = denorm_absent;
705 static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_denorm_loss = false;
706
707 static _GLIBCXX_CONSTEXPRconstexpr wchar_t
708 infinity() _GLIBCXX_USE_NOEXCEPTnoexcept { return wchar_t(); }
709
710 static _GLIBCXX_CONSTEXPRconstexpr wchar_t
711 quiet_NaN() _GLIBCXX_USE_NOEXCEPTnoexcept { return wchar_t(); }
712
713 static _GLIBCXX_CONSTEXPRconstexpr wchar_t
714 signaling_NaN() _GLIBCXX_USE_NOEXCEPTnoexcept { return wchar_t(); }
715
716 static _GLIBCXX_CONSTEXPRconstexpr wchar_t
717 denorm_min() _GLIBCXX_USE_NOEXCEPTnoexcept { return wchar_t(); }
718
719 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_iec559 = false;
720 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_bounded = true;
721 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_modulo = !is_signed;
722
723 static _GLIBCXX_USE_CONSTEXPRconstexpr bool traps = __glibcxx_integral_trapstrue;
724 static _GLIBCXX_USE_CONSTEXPRconstexpr bool tinyness_before = false;
725 static _GLIBCXX_USE_CONSTEXPRconstexpr float_round_style round_style
726 = round_toward_zero;
727 };
728
729#if _GLIBCXX_USE_CHAR8_T
730 /// numeric_limits<char8_t> specialization.
731 template<>
732 struct numeric_limits<char8_t>
733 {
734 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_specialized = true;
735
736 static _GLIBCXX_CONSTEXPRconstexpr char8_t
737 min() _GLIBCXX_USE_NOEXCEPTnoexcept { return __glibcxx_min (char8_t); }
738
739 static _GLIBCXX_CONSTEXPRconstexpr char8_t
740 max() _GLIBCXX_USE_NOEXCEPTnoexcept { return __glibcxx_max (char8_t); }
741
742 static _GLIBCXX_CONSTEXPRconstexpr char8_t
743 lowest() _GLIBCXX_USE_NOEXCEPTnoexcept { return min(); }
744
745 static _GLIBCXX_USE_CONSTEXPRconstexpr int digits = __glibcxx_digits (char8_t);
746 static _GLIBCXX_USE_CONSTEXPRconstexpr int digits10 = __glibcxx_digits10 (char8_t);
747 static _GLIBCXX_USE_CONSTEXPRconstexpr int max_digits10 = 0;
748 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_signed = __glibcxx_signed (char8_t);
749 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_integer = true;
750 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_exact = true;
751 static _GLIBCXX_USE_CONSTEXPRconstexpr int radix = 2;
752
753 static _GLIBCXX_CONSTEXPRconstexpr char8_t
754 epsilon() _GLIBCXX_USE_NOEXCEPTnoexcept { return 0; }
755
756 static _GLIBCXX_CONSTEXPRconstexpr char8_t
757 round_error() _GLIBCXX_USE_NOEXCEPTnoexcept { return 0; }
758
759 static _GLIBCXX_USE_CONSTEXPRconstexpr int min_exponent = 0;
760 static _GLIBCXX_USE_CONSTEXPRconstexpr int min_exponent10 = 0;
761 static _GLIBCXX_USE_CONSTEXPRconstexpr int max_exponent = 0;
762 static _GLIBCXX_USE_CONSTEXPRconstexpr int max_exponent10 = 0;
763
764 static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_infinity = false;
765 static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_quiet_NaN = false;
766 static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_signaling_NaN = false;
767 static _GLIBCXX_USE_CONSTEXPRconstexpr float_denorm_style has_denorm
768 = denorm_absent;
769 static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_denorm_loss = false;
770
771 static _GLIBCXX_CONSTEXPRconstexpr char8_t
772 infinity() _GLIBCXX_USE_NOEXCEPTnoexcept { return char8_t(); }
773
774 static _GLIBCXX_CONSTEXPRconstexpr char8_t
775 quiet_NaN() _GLIBCXX_USE_NOEXCEPTnoexcept { return char8_t(); }
776
777 static _GLIBCXX_CONSTEXPRconstexpr char8_t
778 signaling_NaN() _GLIBCXX_USE_NOEXCEPTnoexcept { return char8_t(); }
779
780 static _GLIBCXX_CONSTEXPRconstexpr char8_t
781 denorm_min() _GLIBCXX_USE_NOEXCEPTnoexcept { return char8_t(); }
782
783 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_iec559 = false;
784 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_bounded = true;
785 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_modulo = !is_signed;
786
787 static _GLIBCXX_USE_CONSTEXPRconstexpr bool traps = __glibcxx_integral_trapstrue;
788 static _GLIBCXX_USE_CONSTEXPRconstexpr bool tinyness_before = false;
789 static _GLIBCXX_USE_CONSTEXPRconstexpr float_round_style round_style
790 = round_toward_zero;
791 };
792#endif
793
794#if __cplusplus201402L >= 201103L
795 /// numeric_limits<char16_t> specialization.
796 template<>
797 struct numeric_limits<char16_t>
798 {
799 static constexpr bool is_specialized = true;
800
801 static constexpr char16_t
802 min() noexcept { return __glibcxx_min (char16_t); }
803
804 static constexpr char16_t
805 max() noexcept { return __glibcxx_max (char16_t); }
806
807 static constexpr char16_t
808 lowest() noexcept { return min(); }
809
810 static constexpr int digits = __glibcxx_digits (char16_t);
811 static constexpr int digits10 = __glibcxx_digits10 (char16_t);
812 static constexpr int max_digits10 = 0;
813 static constexpr bool is_signed = __glibcxx_signed (char16_t);
814 static constexpr bool is_integer = true;
815 static constexpr bool is_exact = true;
816 static constexpr int radix = 2;
817
818 static constexpr char16_t
819 epsilon() noexcept { return 0; }
820
821 static constexpr char16_t
822 round_error() noexcept { return 0; }
823
824 static constexpr int min_exponent = 0;
825 static constexpr int min_exponent10 = 0;
826 static constexpr int max_exponent = 0;
827 static constexpr int max_exponent10 = 0;
828
829 static constexpr bool has_infinity = false;
830 static constexpr bool has_quiet_NaN = false;
831 static constexpr bool has_signaling_NaN = false;
832 static constexpr float_denorm_style has_denorm = denorm_absent;
833 static constexpr bool has_denorm_loss = false;
834
835 static constexpr char16_t
836 infinity() noexcept { return char16_t(); }
837
838 static constexpr char16_t
839 quiet_NaN() noexcept { return char16_t(); }
840
841 static constexpr char16_t
842 signaling_NaN() noexcept { return char16_t(); }
843
844 static constexpr char16_t
845 denorm_min() noexcept { return char16_t(); }
846
847 static constexpr bool is_iec559 = false;
848 static constexpr bool is_bounded = true;
849 static constexpr bool is_modulo = !is_signed;
850
851 static constexpr bool traps = __glibcxx_integral_trapstrue;
852 static constexpr bool tinyness_before = false;
853 static constexpr float_round_style round_style = round_toward_zero;
854 };
855
856 /// numeric_limits<char32_t> specialization.
857 template<>
858 struct numeric_limits<char32_t>
859 {
860 static constexpr bool is_specialized = true;
861
862 static constexpr char32_t
863 min() noexcept { return __glibcxx_min (char32_t); }
864
865 static constexpr char32_t
866 max() noexcept { return __glibcxx_max (char32_t); }
867
868 static constexpr char32_t
869 lowest() noexcept { return min(); }
870
871 static constexpr int digits = __glibcxx_digits (char32_t);
872 static constexpr int digits10 = __glibcxx_digits10 (char32_t);
873 static constexpr int max_digits10 = 0;
874 static constexpr bool is_signed = __glibcxx_signed (char32_t);
875 static constexpr bool is_integer = true;
876 static constexpr bool is_exact = true;
877 static constexpr int radix = 2;
878
879 static constexpr char32_t
880 epsilon() noexcept { return 0; }
881
882 static constexpr char32_t
883 round_error() noexcept { return 0; }
884
885 static constexpr int min_exponent = 0;
886 static constexpr int min_exponent10 = 0;
887 static constexpr int max_exponent = 0;
888 static constexpr int max_exponent10 = 0;
889
890 static constexpr bool has_infinity = false;
891 static constexpr bool has_quiet_NaN = false;
892 static constexpr bool has_signaling_NaN = false;
893 static constexpr float_denorm_style has_denorm = denorm_absent;
894 static constexpr bool has_denorm_loss = false;
895
896 static constexpr char32_t
897 infinity() noexcept { return char32_t(); }
898
899 static constexpr char32_t
900 quiet_NaN() noexcept { return char32_t(); }
901
902 static constexpr char32_t
903 signaling_NaN() noexcept { return char32_t(); }
904
905 static constexpr char32_t
906 denorm_min() noexcept { return char32_t(); }
907
908 static constexpr bool is_iec559 = false;
909 static constexpr bool is_bounded = true;
910 static constexpr bool is_modulo = !is_signed;
911
912 static constexpr bool traps = __glibcxx_integral_trapstrue;
913 static constexpr bool tinyness_before = false;
914 static constexpr float_round_style round_style = round_toward_zero;
915 };
916#endif
917
918 /// numeric_limits<short> specialization.
919 template<>
920 struct numeric_limits<short>
921 {
922 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_specialized = true;
923
924 static _GLIBCXX_CONSTEXPRconstexpr short
925 min() _GLIBCXX_USE_NOEXCEPTnoexcept { return -__SHRT_MAX__32767 - 1; }
926
927 static _GLIBCXX_CONSTEXPRconstexpr short
928 max() _GLIBCXX_USE_NOEXCEPTnoexcept { return __SHRT_MAX__32767; }
929
930#if __cplusplus201402L >= 201103L
931 static constexpr short
932 lowest() noexcept { return min(); }
933#endif
934
935 static _GLIBCXX_USE_CONSTEXPRconstexpr int digits = __glibcxx_digits (short);
936 static _GLIBCXX_USE_CONSTEXPRconstexpr int digits10 = __glibcxx_digits10 (short);
937#if __cplusplus201402L >= 201103L
938 static constexpr int max_digits10 = 0;
939#endif
940 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_signed = true;
941 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_integer = true;
942 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_exact = true;
943 static _GLIBCXX_USE_CONSTEXPRconstexpr int radix = 2;
944
945 static _GLIBCXX_CONSTEXPRconstexpr short
946 epsilon() _GLIBCXX_USE_NOEXCEPTnoexcept { return 0; }
947
948 static _GLIBCXX_CONSTEXPRconstexpr short
949 round_error() _GLIBCXX_USE_NOEXCEPTnoexcept { return 0; }
950
951 static _GLIBCXX_USE_CONSTEXPRconstexpr int min_exponent = 0;
952 static _GLIBCXX_USE_CONSTEXPRconstexpr int min_exponent10 = 0;
953 static _GLIBCXX_USE_CONSTEXPRconstexpr int max_exponent = 0;
954 static _GLIBCXX_USE_CONSTEXPRconstexpr int max_exponent10 = 0;
955
956 static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_infinity = false;
957 static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_quiet_NaN = false;
958 static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_signaling_NaN = false;
959 static _GLIBCXX_USE_CONSTEXPRconstexpr float_denorm_style has_denorm
960 = denorm_absent;
961 static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_denorm_loss = false;
962
963 static _GLIBCXX_CONSTEXPRconstexpr short
964 infinity() _GLIBCXX_USE_NOEXCEPTnoexcept { return short(); }
965
966 static _GLIBCXX_CONSTEXPRconstexpr short
967 quiet_NaN() _GLIBCXX_USE_NOEXCEPTnoexcept { return short(); }
968
969 static _GLIBCXX_CONSTEXPRconstexpr short
970 signaling_NaN() _GLIBCXX_USE_NOEXCEPTnoexcept { return short(); }
971
972 static _GLIBCXX_CONSTEXPRconstexpr short
973 denorm_min() _GLIBCXX_USE_NOEXCEPTnoexcept { return short(); }
974
975 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_iec559 = false;
976 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_bounded = true;
977 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_modulo = false;
978
979 static _GLIBCXX_USE_CONSTEXPRconstexpr bool traps = __glibcxx_integral_trapstrue;
980 static _GLIBCXX_USE_CONSTEXPRconstexpr bool tinyness_before = false;
981 static _GLIBCXX_USE_CONSTEXPRconstexpr float_round_style round_style
982 = round_toward_zero;
983 };
984
985 /// numeric_limits<unsigned short> specialization.
986 template<>
987 struct numeric_limits<unsigned short>
988 {
989 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_specialized = true;
990
991 static _GLIBCXX_CONSTEXPRconstexpr unsigned short
992 min() _GLIBCXX_USE_NOEXCEPTnoexcept { return 0; }
993
994 static _GLIBCXX_CONSTEXPRconstexpr unsigned short
995 max() _GLIBCXX_USE_NOEXCEPTnoexcept { return __SHRT_MAX__32767 * 2U + 1; }
996
997#if __cplusplus201402L >= 201103L
998 static constexpr unsigned short
999 lowest() noexcept { return min(); }
1000#endif
1001
1002 static _GLIBCXX_USE_CONSTEXPRconstexpr int digits
1003 = __glibcxx_digits (unsigned short);
1004 static _GLIBCXX_USE_CONSTEXPRconstexpr int digits10
1005 = __glibcxx_digits10 (unsigned short);
1006#if __cplusplus201402L >= 201103L
1007 static constexpr int max_digits10 = 0;
1008#endif
1009 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_signed = false;
1010 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_integer = true;
1011 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_exact = true;
1012 static _GLIBCXX_USE_CONSTEXPRconstexpr int radix = 2;
1013
1014 static _GLIBCXX_CONSTEXPRconstexpr unsigned short
1015 epsilon() _GLIBCXX_USE_NOEXCEPTnoexcept { return 0; }
1016
1017 static _GLIBCXX_CONSTEXPRconstexpr unsigned short
1018 round_error() _GLIBCXX_USE_NOEXCEPTnoexcept { return 0; }
1019
1020 static _GLIBCXX_USE_CONSTEXPRconstexpr int min_exponent = 0;
1021 static _GLIBCXX_USE_CONSTEXPRconstexpr int min_exponent10 = 0;
1022 static _GLIBCXX_USE_CONSTEXPRconstexpr int max_exponent = 0;
1023 static _GLIBCXX_USE_CONSTEXPRconstexpr int max_exponent10 = 0;
1024
1025 static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_infinity = false;
1026 static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_quiet_NaN = false;
1027 static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_signaling_NaN = false;
1028 static _GLIBCXX_USE_CONSTEXPRconstexpr float_denorm_style has_denorm
1029 = denorm_absent;
1030 static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_denorm_loss = false;
1031
1032 static _GLIBCXX_CONSTEXPRconstexpr unsigned short
1033 infinity() _GLIBCXX_USE_NOEXCEPTnoexcept
1034 { return static_cast<unsigned short>(0); }
1035
1036 static _GLIBCXX_CONSTEXPRconstexpr unsigned short
1037 quiet_NaN() _GLIBCXX_USE_NOEXCEPTnoexcept
1038 { return static_cast<unsigned short>(0); }
1039
1040 static _GLIBCXX_CONSTEXPRconstexpr unsigned short
1041 signaling_NaN() _GLIBCXX_USE_NOEXCEPTnoexcept
1042 { return static_cast<unsigned short>(0); }
1043
1044 static _GLIBCXX_CONSTEXPRconstexpr unsigned short
1045 denorm_min() _GLIBCXX_USE_NOEXCEPTnoexcept
1046 { return static_cast<unsigned short>(0); }
1047
1048 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_iec559 = false;
1049 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_bounded = true;
1050 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_modulo = true;
1051
1052 static _GLIBCXX_USE_CONSTEXPRconstexpr bool traps = __glibcxx_integral_trapstrue;
1053 static _GLIBCXX_USE_CONSTEXPRconstexpr bool tinyness_before = false;
1054 static _GLIBCXX_USE_CONSTEXPRconstexpr float_round_style round_style
1055 = round_toward_zero;
1056 };
1057
1058 /// numeric_limits<int> specialization.
1059 template<>
1060 struct numeric_limits<int>
1061 {
1062 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_specialized = true;
1063
1064 static _GLIBCXX_CONSTEXPRconstexpr int
1065 min() _GLIBCXX_USE_NOEXCEPTnoexcept { return -__INT_MAX__2147483647 - 1; }
1066
1067 static _GLIBCXX_CONSTEXPRconstexpr int
1068 max() _GLIBCXX_USE_NOEXCEPTnoexcept { return __INT_MAX__2147483647; }
1069
1070#if __cplusplus201402L >= 201103L
1071 static constexpr int
1072 lowest() noexcept { return min(); }
1073#endif
1074
1075 static _GLIBCXX_USE_CONSTEXPRconstexpr int digits = __glibcxx_digits (int);
1076 static _GLIBCXX_USE_CONSTEXPRconstexpr int digits10 = __glibcxx_digits10 (int);
1077#if __cplusplus201402L >= 201103L
1078 static constexpr int max_digits10 = 0;
1079#endif
1080 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_signed = true;
1081 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_integer = true;
1082 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_exact = true;
1083 static _GLIBCXX_USE_CONSTEXPRconstexpr int radix = 2;
1084
1085 static _GLIBCXX_CONSTEXPRconstexpr int
1086 epsilon() _GLIBCXX_USE_NOEXCEPTnoexcept { return 0; }
1087
1088 static _GLIBCXX_CONSTEXPRconstexpr int
1089 round_error() _GLIBCXX_USE_NOEXCEPTnoexcept { return 0; }
1090
1091 static _GLIBCXX_USE_CONSTEXPRconstexpr int min_exponent = 0;
1092 static _GLIBCXX_USE_CONSTEXPRconstexpr int min_exponent10 = 0;
1093 static _GLIBCXX_USE_CONSTEXPRconstexpr int max_exponent = 0;
1094 static _GLIBCXX_USE_CONSTEXPRconstexpr int max_exponent10 = 0;
1095
1096 static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_infinity = false;
1097 static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_quiet_NaN = false;
1098 static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_signaling_NaN = false;
1099 static _GLIBCXX_USE_CONSTEXPRconstexpr float_denorm_style has_denorm
1100 = denorm_absent;
1101 static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_denorm_loss = false;
1102
1103 static _GLIBCXX_CONSTEXPRconstexpr int
1104 infinity() _GLIBCXX_USE_NOEXCEPTnoexcept { return static_cast<int>(0); }
1105
1106 static _GLIBCXX_CONSTEXPRconstexpr int
1107 quiet_NaN() _GLIBCXX_USE_NOEXCEPTnoexcept { return static_cast<int>(0); }
1108
1109 static _GLIBCXX_CONSTEXPRconstexpr int
1110 signaling_NaN() _GLIBCXX_USE_NOEXCEPTnoexcept { return static_cast<int>(0); }
1111
1112 static _GLIBCXX_CONSTEXPRconstexpr int
1113 denorm_min() _GLIBCXX_USE_NOEXCEPTnoexcept { return static_cast<int>(0); }
1114
1115 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_iec559 = false;
1116 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_bounded = true;
1117 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_modulo = false;
1118
1119 static _GLIBCXX_USE_CONSTEXPRconstexpr bool traps = __glibcxx_integral_trapstrue;
1120 static _GLIBCXX_USE_CONSTEXPRconstexpr bool tinyness_before = false;
1121 static _GLIBCXX_USE_CONSTEXPRconstexpr float_round_style round_style
1122 = round_toward_zero;
1123 };
1124
1125 /// numeric_limits<unsigned int> specialization.
1126 template<>
1127 struct numeric_limits<unsigned int>
1128 {
1129 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_specialized = true;
1130
1131 static _GLIBCXX_CONSTEXPRconstexpr unsigned int
1132 min() _GLIBCXX_USE_NOEXCEPTnoexcept { return 0; }
1133
1134 static _GLIBCXX_CONSTEXPRconstexpr unsigned int
1135 max() _GLIBCXX_USE_NOEXCEPTnoexcept { return __INT_MAX__2147483647 * 2U + 1; }
1136
1137#if __cplusplus201402L >= 201103L
1138 static constexpr unsigned int
1139 lowest() noexcept { return min(); }
1140#endif
1141
1142 static _GLIBCXX_USE_CONSTEXPRconstexpr int digits
1143 = __glibcxx_digits (unsigned int);
1144 static _GLIBCXX_USE_CONSTEXPRconstexpr int digits10
1145 = __glibcxx_digits10 (unsigned int);
1146#if __cplusplus201402L >= 201103L
1147 static constexpr int max_digits10 = 0;
1148#endif
1149 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_signed = false;
1150 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_integer = true;
1151 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_exact = true;
1152 static _GLIBCXX_USE_CONSTEXPRconstexpr int radix = 2;
1153
1154 static _GLIBCXX_CONSTEXPRconstexpr unsigned int
1155 epsilon() _GLIBCXX_USE_NOEXCEPTnoexcept { return 0; }
1156
1157 static _GLIBCXX_CONSTEXPRconstexpr unsigned int
1158 round_error() _GLIBCXX_USE_NOEXCEPTnoexcept { return 0; }
1159
1160 static _GLIBCXX_USE_CONSTEXPRconstexpr int min_exponent = 0;
1161 static _GLIBCXX_USE_CONSTEXPRconstexpr int min_exponent10 = 0;
1162 static _GLIBCXX_USE_CONSTEXPRconstexpr int max_exponent = 0;
1163 static _GLIBCXX_USE_CONSTEXPRconstexpr int max_exponent10 = 0;
1164
1165 static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_infinity = false;
1166 static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_quiet_NaN = false;
1167 static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_signaling_NaN = false;
1168 static _GLIBCXX_USE_CONSTEXPRconstexpr float_denorm_style has_denorm
1169 = denorm_absent;
1170 static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_denorm_loss = false;
1171
1172 static _GLIBCXX_CONSTEXPRconstexpr unsigned int
1173 infinity() _GLIBCXX_USE_NOEXCEPTnoexcept { return static_cast<unsigned int>(0); }
1174
1175 static _GLIBCXX_CONSTEXPRconstexpr unsigned int
1176 quiet_NaN() _GLIBCXX_USE_NOEXCEPTnoexcept
1177 { return static_cast<unsigned int>(0); }
1178
1179 static _GLIBCXX_CONSTEXPRconstexpr unsigned int
1180 signaling_NaN() _GLIBCXX_USE_NOEXCEPTnoexcept
1181 { return static_cast<unsigned int>(0); }
1182
1183 static _GLIBCXX_CONSTEXPRconstexpr unsigned int
1184 denorm_min() _GLIBCXX_USE_NOEXCEPTnoexcept
1185 { return static_cast<unsigned int>(0); }
1186
1187 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_iec559 = false;
1188 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_bounded = true;
1189 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_modulo = true;
1190
1191 static _GLIBCXX_USE_CONSTEXPRconstexpr bool traps = __glibcxx_integral_trapstrue;
1192 static _GLIBCXX_USE_CONSTEXPRconstexpr bool tinyness_before = false;
1193 static _GLIBCXX_USE_CONSTEXPRconstexpr float_round_style round_style
1194 = round_toward_zero;
1195 };
1196
1197 /// numeric_limits<long> specialization.
1198 template<>
1199 struct numeric_limits<long>
1200 {
1201 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_specialized = true;
1202
1203 static _GLIBCXX_CONSTEXPRconstexpr long
1204 min() _GLIBCXX_USE_NOEXCEPTnoexcept { return -__LONG_MAX__9223372036854775807L - 1; }
1205
1206 static _GLIBCXX_CONSTEXPRconstexpr long
1207 max() _GLIBCXX_USE_NOEXCEPTnoexcept { return __LONG_MAX__9223372036854775807L; }
1208
1209#if __cplusplus201402L >= 201103L
1210 static constexpr long
1211 lowest() noexcept { return min(); }
1212#endif
1213
1214 static _GLIBCXX_USE_CONSTEXPRconstexpr int digits = __glibcxx_digits (long);
1215 static _GLIBCXX_USE_CONSTEXPRconstexpr int digits10 = __glibcxx_digits10 (long);
1216#if __cplusplus201402L >= 201103L
1217 static constexpr int max_digits10 = 0;
1218#endif
1219 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_signed = true;
1220 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_integer = true;
1221 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_exact = true;
1222 static _GLIBCXX_USE_CONSTEXPRconstexpr int radix = 2;
1223
1224 static _GLIBCXX_CONSTEXPRconstexpr long
1225 epsilon() _GLIBCXX_USE_NOEXCEPTnoexcept { return 0; }
1226
1227 static _GLIBCXX_CONSTEXPRconstexpr long
1228 round_error() _GLIBCXX_USE_NOEXCEPTnoexcept { return 0; }
1229
1230 static _GLIBCXX_USE_CONSTEXPRconstexpr int min_exponent = 0;
1231 static _GLIBCXX_USE_CONSTEXPRconstexpr int min_exponent10 = 0;
1232 static _GLIBCXX_USE_CONSTEXPRconstexpr int max_exponent = 0;
1233 static _GLIBCXX_USE_CONSTEXPRconstexpr int max_exponent10 = 0;
1234
1235 static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_infinity = false;
1236 static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_quiet_NaN = false;
1237 static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_signaling_NaN = false;
1238 static _GLIBCXX_USE_CONSTEXPRconstexpr float_denorm_style has_denorm
1239 = denorm_absent;
1240 static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_denorm_loss = false;
1241
1242 static _GLIBCXX_CONSTEXPRconstexpr long
1243 infinity() _GLIBCXX_USE_NOEXCEPTnoexcept { return static_cast<long>(0); }
1244
1245 static _GLIBCXX_CONSTEXPRconstexpr long
1246 quiet_NaN() _GLIBCXX_USE_NOEXCEPTnoexcept { return static_cast<long>(0); }
1247
1248 static _GLIBCXX_CONSTEXPRconstexpr long
1249 signaling_NaN() _GLIBCXX_USE_NOEXCEPTnoexcept { return static_cast<long>(0); }
1250
1251 static _GLIBCXX_CONSTEXPRconstexpr long
1252 denorm_min() _GLIBCXX_USE_NOEXCEPTnoexcept { return static_cast<long>(0); }
1253
1254 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_iec559 = false;
1255 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_bounded = true;
1256 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_modulo = false;
1257
1258 static _GLIBCXX_USE_CONSTEXPRconstexpr bool traps = __glibcxx_integral_trapstrue;
1259 static _GLIBCXX_USE_CONSTEXPRconstexpr bool tinyness_before = false;
1260 static _GLIBCXX_USE_CONSTEXPRconstexpr float_round_style round_style
1261 = round_toward_zero;
1262 };
1263
1264 /// numeric_limits<unsigned long> specialization.
1265 template<>
1266 struct numeric_limits<unsigned long>
1267 {
1268 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_specialized = true;
1269
1270 static _GLIBCXX_CONSTEXPRconstexpr unsigned long
1271 min() _GLIBCXX_USE_NOEXCEPTnoexcept { return 0; }
1272
1273 static _GLIBCXX_CONSTEXPRconstexpr unsigned long
1274 max() _GLIBCXX_USE_NOEXCEPTnoexcept { return __LONG_MAX__9223372036854775807L * 2UL + 1; }
11
Returning the value 18446744073709551615
1275
1276#if __cplusplus201402L >= 201103L
1277 static constexpr unsigned long
1278 lowest() noexcept { return min(); }
1279#endif
1280
1281 static _GLIBCXX_USE_CONSTEXPRconstexpr int digits
1282 = __glibcxx_digits (unsigned long);
1283 static _GLIBCXX_USE_CONSTEXPRconstexpr int digits10
1284 = __glibcxx_digits10 (unsigned long);
1285#if __cplusplus201402L >= 201103L
1286 static constexpr int max_digits10 = 0;
1287#endif
1288 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_signed = false;
1289 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_integer = true;
1290 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_exact = true;
1291 static _GLIBCXX_USE_CONSTEXPRconstexpr int radix = 2;
1292
1293 static _GLIBCXX_CONSTEXPRconstexpr unsigned long
1294 epsilon() _GLIBCXX_USE_NOEXCEPTnoexcept { return 0; }
1295
1296 static _GLIBCXX_CONSTEXPRconstexpr unsigned long
1297 round_error() _GLIBCXX_USE_NOEXCEPTnoexcept { return 0; }
1298
1299 static _GLIBCXX_USE_CONSTEXPRconstexpr int min_exponent = 0;
1300 static _GLIBCXX_USE_CONSTEXPRconstexpr int min_exponent10 = 0;
1301 static _GLIBCXX_USE_CONSTEXPRconstexpr int max_exponent = 0;
1302 static _GLIBCXX_USE_CONSTEXPRconstexpr int max_exponent10 = 0;
1303
1304 static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_infinity = false;
1305 static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_quiet_NaN = false;
1306 static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_signaling_NaN = false;
1307 static _GLIBCXX_USE_CONSTEXPRconstexpr float_denorm_style has_denorm
1308 = denorm_absent;
1309 static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_denorm_loss = false;
1310
1311 static _GLIBCXX_CONSTEXPRconstexpr unsigned long
1312 infinity() _GLIBCXX_USE_NOEXCEPTnoexcept
1313 { return static_cast<unsigned long>(0); }
1314
1315 static _GLIBCXX_CONSTEXPRconstexpr unsigned long
1316 quiet_NaN() _GLIBCXX_USE_NOEXCEPTnoexcept
1317 { return static_cast<unsigned long>(0); }
1318
1319 static _GLIBCXX_CONSTEXPRconstexpr unsigned long
1320 signaling_NaN() _GLIBCXX_USE_NOEXCEPTnoexcept
1321 { return static_cast<unsigned long>(0); }
1322
1323 static _GLIBCXX_CONSTEXPRconstexpr unsigned long
1324 denorm_min() _GLIBCXX_USE_NOEXCEPTnoexcept
1325 { return static_cast<unsigned long>(0); }
1326
1327 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_iec559 = false;
1328 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_bounded = true;
1329 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_modulo = true;
1330
1331 static _GLIBCXX_USE_CONSTEXPRconstexpr bool traps = __glibcxx_integral_trapstrue;
1332 static _GLIBCXX_USE_CONSTEXPRconstexpr bool tinyness_before = false;
1333 static _GLIBCXX_USE_CONSTEXPRconstexpr float_round_style round_style
1334 = round_toward_zero;
1335 };
1336
1337 /// numeric_limits<long long> specialization.
1338 template<>
1339 struct numeric_limits<long long>
1340 {
1341 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_specialized = true;
1342
1343 static _GLIBCXX_CONSTEXPRconstexpr long long
1344 min() _GLIBCXX_USE_NOEXCEPTnoexcept { return -__LONG_LONG_MAX__9223372036854775807LL - 1; }
1345
1346 static _GLIBCXX_CONSTEXPRconstexpr long long
1347 max() _GLIBCXX_USE_NOEXCEPTnoexcept { return __LONG_LONG_MAX__9223372036854775807LL; }
1348
1349#if __cplusplus201402L >= 201103L
1350 static constexpr long long
1351 lowest() noexcept { return min(); }
1352#endif
1353
1354 static _GLIBCXX_USE_CONSTEXPRconstexpr int digits
1355 = __glibcxx_digits (long long);
1356 static _GLIBCXX_USE_CONSTEXPRconstexpr int digits10
1357 = __glibcxx_digits10 (long long);
1358#if __cplusplus201402L >= 201103L
1359 static constexpr int max_digits10 = 0;
1360#endif
1361 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_signed = true;
1362 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_integer = true;
1363 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_exact = true;
1364 static _GLIBCXX_USE_CONSTEXPRconstexpr int radix = 2;
1365
1366 static _GLIBCXX_CONSTEXPRconstexpr long long
1367 epsilon() _GLIBCXX_USE_NOEXCEPTnoexcept { return 0; }
1368
1369 static _GLIBCXX_CONSTEXPRconstexpr long long
1370 round_error() _GLIBCXX_USE_NOEXCEPTnoexcept { return 0; }
1371
1372 static _GLIBCXX_USE_CONSTEXPRconstexpr int min_exponent = 0;
1373 static _GLIBCXX_USE_CONSTEXPRconstexpr int min_exponent10 = 0;
1374 static _GLIBCXX_USE_CONSTEXPRconstexpr int max_exponent = 0;
1375 static _GLIBCXX_USE_CONSTEXPRconstexpr int max_exponent10 = 0;
1376
1377 static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_infinity = false;
1378 static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_quiet_NaN = false;
1379 static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_signaling_NaN = false;
1380 static _GLIBCXX_USE_CONSTEXPRconstexpr float_denorm_style has_denorm
1381 = denorm_absent;
1382 static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_denorm_loss = false;
1383
1384 static _GLIBCXX_CONSTEXPRconstexpr long long
1385 infinity() _GLIBCXX_USE_NOEXCEPTnoexcept { return static_cast<long long>(0); }
1386
1387 static _GLIBCXX_CONSTEXPRconstexpr long long
1388 quiet_NaN() _GLIBCXX_USE_NOEXCEPTnoexcept { return static_cast<long long>(0); }
1389
1390 static _GLIBCXX_CONSTEXPRconstexpr long long
1391 signaling_NaN() _GLIBCXX_USE_NOEXCEPTnoexcept
1392 { return static_cast<long long>(0); }
1393
1394 static _GLIBCXX_CONSTEXPRconstexpr long long
1395 denorm_min() _GLIBCXX_USE_NOEXCEPTnoexcept { return static_cast<long long>(0); }
1396
1397 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_iec559 = false;
1398 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_bounded = true;
1399 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_modulo = false;
1400
1401 static _GLIBCXX_USE_CONSTEXPRconstexpr bool traps = __glibcxx_integral_trapstrue;
1402 static _GLIBCXX_USE_CONSTEXPRconstexpr bool tinyness_before = false;
1403 static _GLIBCXX_USE_CONSTEXPRconstexpr float_round_style round_style
1404 = round_toward_zero;
1405 };
1406
1407 /// numeric_limits<unsigned long long> specialization.
1408 template<>
1409 struct numeric_limits<unsigned long long>
1410 {
1411 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_specialized = true;
1412
1413 static _GLIBCXX_CONSTEXPRconstexpr unsigned long long
1414 min() _GLIBCXX_USE_NOEXCEPTnoexcept { return 0; }
1415
1416 static _GLIBCXX_CONSTEXPRconstexpr unsigned long long
1417 max() _GLIBCXX_USE_NOEXCEPTnoexcept { return __LONG_LONG_MAX__9223372036854775807LL * 2ULL + 1; }
1418
1419#if __cplusplus201402L >= 201103L
1420 static constexpr unsigned long long
1421 lowest() noexcept { return min(); }
1422#endif
1423
1424 static _GLIBCXX_USE_CONSTEXPRconstexpr int digits
1425 = __glibcxx_digits (unsigned long long);
1426 static _GLIBCXX_USE_CONSTEXPRconstexpr int digits10
1427 = __glibcxx_digits10 (unsigned long long);
1428#if __cplusplus201402L >= 201103L
1429 static constexpr int max_digits10 = 0;
1430#endif
1431 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_signed = false;
1432 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_integer = true;
1433 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_exact = true;
1434 static _GLIBCXX_USE_CONSTEXPRconstexpr int radix = 2;
1435
1436 static _GLIBCXX_CONSTEXPRconstexpr unsigned long long
1437 epsilon() _GLIBCXX_USE_NOEXCEPTnoexcept { return 0; }
1438
1439 static _GLIBCXX_CONSTEXPRconstexpr unsigned long long
1440 round_error() _GLIBCXX_USE_NOEXCEPTnoexcept { return 0; }
1441
1442 static _GLIBCXX_USE_CONSTEXPRconstexpr int min_exponent = 0;
1443 static _GLIBCXX_USE_CONSTEXPRconstexpr int min_exponent10 = 0;
1444 static _GLIBCXX_USE_CONSTEXPRconstexpr int max_exponent = 0;
1445 static _GLIBCXX_USE_CONSTEXPRconstexpr int max_exponent10 = 0;
1446
1447 static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_infinity = false;
1448 static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_quiet_NaN = false;
1449 static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_signaling_NaN = false;
1450 static _GLIBCXX_USE_CONSTEXPRconstexpr float_denorm_style has_denorm
1451 = denorm_absent;
1452 static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_denorm_loss = false;
1453
1454 static _GLIBCXX_CONSTEXPRconstexpr unsigned long long
1455 infinity() _GLIBCXX_USE_NOEXCEPTnoexcept
1456 { return static_cast<unsigned long long>(0); }
1457
1458 static _GLIBCXX_CONSTEXPRconstexpr unsigned long long
1459 quiet_NaN() _GLIBCXX_USE_NOEXCEPTnoexcept
1460 { return static_cast<unsigned long long>(0); }
1461
1462 static _GLIBCXX_CONSTEXPRconstexpr unsigned long long
1463 signaling_NaN() _GLIBCXX_USE_NOEXCEPTnoexcept
1464 { return static_cast<unsigned long long>(0); }
1465
1466 static _GLIBCXX_CONSTEXPRconstexpr unsigned long long
1467 denorm_min() _GLIBCXX_USE_NOEXCEPTnoexcept
1468 { return static_cast<unsigned long long>(0); }
1469
1470 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_iec559 = false;
1471 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_bounded = true;
1472 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_modulo = true;
1473
1474 static _GLIBCXX_USE_CONSTEXPRconstexpr bool traps = __glibcxx_integral_trapstrue;
1475 static _GLIBCXX_USE_CONSTEXPRconstexpr bool tinyness_before = false;
1476 static _GLIBCXX_USE_CONSTEXPRconstexpr float_round_style round_style
1477 = round_toward_zero;
1478 };
1479
1480#define __INT_N(TYPE, BITSIZE, EXT, UEXT) \
1481 template<> \
1482 struct numeric_limits<TYPE> \
1483 { \
1484 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_specialized = true; \
1485 \
1486 static _GLIBCXX_CONSTEXPRconstexpr TYPE \
1487 min() _GLIBCXX_USE_NOEXCEPTnoexcept { return __glibcxx_min_b (TYPE, BITSIZE)(((TYPE)(-1) < 0) ? -(((TYPE)(-1) < 0) ? (((((TYPE)1 <<
((BITSIZE - ((TYPE)(-1) < 0)) - 1)) - 1) << 1) + 1)
: ~(TYPE)0) - 1 : (TYPE)0)
; } \
1488 \
1489 static _GLIBCXX_CONSTEXPRconstexpr TYPE \
1490 max() _GLIBCXX_USE_NOEXCEPTnoexcept { return __glibcxx_max_b (TYPE, BITSIZE)(((TYPE)(-1) < 0) ? (((((TYPE)1 << ((BITSIZE - ((TYPE
)(-1) < 0)) - 1)) - 1) << 1) + 1) : ~(TYPE)0)
; } \
1491 \
1492 static _GLIBCXX_USE_CONSTEXPRconstexpr int digits \
1493 = BITSIZE - 1; \
1494 static _GLIBCXX_USE_CONSTEXPRconstexpr int digits10 \
1495 = (BITSIZE - 1) * 643L / 2136; \
1496 \
1497 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_signed = true; \
1498 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_integer = true; \
1499 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_exact = true; \
1500 static _GLIBCXX_USE_CONSTEXPRconstexpr int radix = 2; \
1501 \
1502 static _GLIBCXX_CONSTEXPRconstexpr TYPE \
1503 epsilon() _GLIBCXX_USE_NOEXCEPTnoexcept { return 0; } \
1504 \
1505 static _GLIBCXX_CONSTEXPRconstexpr TYPE \
1506 round_error() _GLIBCXX_USE_NOEXCEPTnoexcept { return 0; } \
1507 \
1508 EXT \
1509 \
1510 static _GLIBCXX_USE_CONSTEXPRconstexpr int min_exponent = 0; \
1511 static _GLIBCXX_USE_CONSTEXPRconstexpr int min_exponent10 = 0; \
1512 static _GLIBCXX_USE_CONSTEXPRconstexpr int max_exponent = 0; \
1513 static _GLIBCXX_USE_CONSTEXPRconstexpr int max_exponent10 = 0; \
1514 \
1515 static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_infinity = false; \
1516 static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_quiet_NaN = false; \
1517 static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_signaling_NaN = false; \
1518 static _GLIBCXX_USE_CONSTEXPRconstexpr float_denorm_style has_denorm \
1519 = denorm_absent; \
1520 static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_denorm_loss = false; \
1521 \
1522 static _GLIBCXX_CONSTEXPRconstexpr TYPE \
1523 infinity() _GLIBCXX_USE_NOEXCEPTnoexcept \
1524 { return static_cast<TYPE>(0); } \
1525 \
1526 static _GLIBCXX_CONSTEXPRconstexpr TYPE \
1527 quiet_NaN() _GLIBCXX_USE_NOEXCEPTnoexcept \
1528 { return static_cast<TYPE>(0); } \
1529 \
1530 static _GLIBCXX_CONSTEXPRconstexpr TYPE \
1531 signaling_NaN() _GLIBCXX_USE_NOEXCEPTnoexcept \
1532 { return static_cast<TYPE>(0); } \
1533 \
1534 static _GLIBCXX_CONSTEXPRconstexpr TYPE \
1535 denorm_min() _GLIBCXX_USE_NOEXCEPTnoexcept \
1536 { return static_cast<TYPE>(0); } \
1537 \
1538 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_iec559 = false; \
1539 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_bounded = true; \
1540 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_modulo = false; \
1541 \
1542 static _GLIBCXX_USE_CONSTEXPRconstexpr bool traps \
1543 = __glibcxx_integral_trapstrue; \
1544 static _GLIBCXX_USE_CONSTEXPRconstexpr bool tinyness_before = false; \
1545 static _GLIBCXX_USE_CONSTEXPRconstexpr float_round_style round_style \
1546 = round_toward_zero; \
1547 }; \
1548 \
1549 template<> \
1550 struct numeric_limits<unsigned TYPE> \
1551 { \
1552 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_specialized = true; \
1553 \
1554 static _GLIBCXX_CONSTEXPRconstexpr unsigned TYPE \
1555 min() _GLIBCXX_USE_NOEXCEPTnoexcept { return 0; } \
1556 \
1557 static _GLIBCXX_CONSTEXPRconstexpr unsigned TYPE \
1558 max() _GLIBCXX_USE_NOEXCEPTnoexcept \
1559 { return __glibcxx_max_b (unsigned TYPE, BITSIZE)(((unsigned TYPE)(-1) < 0) ? (((((unsigned TYPE)1 <<
((BITSIZE - ((unsigned TYPE)(-1) < 0)) - 1)) - 1) <<
1) + 1) : ~(unsigned TYPE)0)
; } \
1560 \
1561 UEXT \
1562 \
1563 static _GLIBCXX_USE_CONSTEXPRconstexpr int digits \
1564 = BITSIZE; \
1565 static _GLIBCXX_USE_CONSTEXPRconstexpr int digits10 \
1566 = BITSIZE * 643L / 2136; \
1567 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_signed = false; \
1568 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_integer = true; \
1569 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_exact = true; \
1570 static _GLIBCXX_USE_CONSTEXPRconstexpr int radix = 2; \
1571 \
1572 static _GLIBCXX_CONSTEXPRconstexpr unsigned TYPE \
1573 epsilon() _GLIBCXX_USE_NOEXCEPTnoexcept { return 0; } \
1574 \
1575 static _GLIBCXX_CONSTEXPRconstexpr unsigned TYPE \
1576 round_error() _GLIBCXX_USE_NOEXCEPTnoexcept { return 0; } \
1577 \
1578 static _GLIBCXX_USE_CONSTEXPRconstexpr int min_exponent = 0; \
1579 static _GLIBCXX_USE_CONSTEXPRconstexpr int min_exponent10 = 0; \
1580 static _GLIBCXX_USE_CONSTEXPRconstexpr int max_exponent = 0; \
1581 static _GLIBCXX_USE_CONSTEXPRconstexpr int max_exponent10 = 0; \
1582 \
1583 static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_infinity = false; \
1584 static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_quiet_NaN = false; \
1585 static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_signaling_NaN = false; \
1586 static _GLIBCXX_USE_CONSTEXPRconstexpr float_denorm_style has_denorm \
1587 = denorm_absent; \
1588 static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_denorm_loss = false; \
1589 \
1590 static _GLIBCXX_CONSTEXPRconstexpr unsigned TYPE \
1591 infinity() _GLIBCXX_USE_NOEXCEPTnoexcept \
1592 { return static_cast<unsigned TYPE>(0); } \
1593 \
1594 static _GLIBCXX_CONSTEXPRconstexpr unsigned TYPE \
1595 quiet_NaN() _GLIBCXX_USE_NOEXCEPTnoexcept \
1596 { return static_cast<unsigned TYPE>(0); } \
1597 \
1598 static _GLIBCXX_CONSTEXPRconstexpr unsigned TYPE \
1599 signaling_NaN() _GLIBCXX_USE_NOEXCEPTnoexcept \
1600 { return static_cast<unsigned TYPE>(0); } \
1601 \
1602 static _GLIBCXX_CONSTEXPRconstexpr unsigned TYPE \
1603 denorm_min() _GLIBCXX_USE_NOEXCEPTnoexcept \
1604 { return static_cast<unsigned TYPE>(0); } \
1605 \
1606 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_iec559 = false; \
1607 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_bounded = true; \
1608 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_modulo = true; \
1609 \
1610 static _GLIBCXX_USE_CONSTEXPRconstexpr bool traps = __glibcxx_integral_trapstrue; \
1611 static _GLIBCXX_USE_CONSTEXPRconstexpr bool tinyness_before = false; \
1612 static _GLIBCXX_USE_CONSTEXPRconstexpr float_round_style round_style \
1613 = round_toward_zero; \
1614 };
1615
1616#if __cplusplus201402L >= 201103L
1617
1618#define __INT_N_201103(TYPE) \
1619 static constexpr TYPE \
1620 lowest() noexcept { return min(); } \
1621 static constexpr int max_digits10 = 0;
1622
1623#define __INT_N_U201103(TYPE) \
1624 static constexpr unsigned TYPE \
1625 lowest() noexcept { return min(); } \
1626 static constexpr int max_digits10 = 0;
1627
1628#else
1629#define __INT_N_201103(TYPE)
1630#define __INT_N_U201103(TYPE)
1631#endif
1632
1633#if !defined(__STRICT_ANSI__1)
1634#ifdef __GLIBCXX_TYPE_INT_N_0
1635 __INT_N(__GLIBCXX_TYPE_INT_N_0, __GLIBCXX_BITSIZE_INT_N_0,
1636 __INT_N_201103 (__GLIBCXX_TYPE_INT_N_0), __INT_N_U201103 (__GLIBCXX_TYPE_INT_N_0))
1637#endif
1638#ifdef __GLIBCXX_TYPE_INT_N_1
1639 __INT_N (__GLIBCXX_TYPE_INT_N_1, __GLIBCXX_BITSIZE_INT_N_1,
1640 __INT_N_201103 (__GLIBCXX_TYPE_INT_N_1), __INT_N_U201103 (__GLIBCXX_TYPE_INT_N_1))
1641#endif
1642#ifdef __GLIBCXX_TYPE_INT_N_2
1643 __INT_N (__GLIBCXX_TYPE_INT_N_2, __GLIBCXX_BITSIZE_INT_N_2,
1644 __INT_N_201103 (__GLIBCXX_TYPE_INT_N_2), __INT_N_U201103 (__GLIBCXX_TYPE_INT_N_2))
1645#endif
1646#ifdef __GLIBCXX_TYPE_INT_N_3
1647 __INT_N (__GLIBCXX_TYPE_INT_N_3, __GLIBCXX_BITSIZE_INT_N_3,
1648 __INT_N_201103 (__GLIBCXX_TYPE_INT_N_3), __INT_N_U201103 (__GLIBCXX_TYPE_INT_N_3))
1649#endif
1650
1651#elif defined __STRICT_ANSI__1 && defined __SIZEOF_INT128__16
1652 __INT_N(__int128, 128,
1653 __INT_N_201103 (__int128),
1654 __INT_N_U201103 (__int128))
1655#endif
1656
1657#undef __INT_N
1658#undef __INT_N_201103
1659#undef __INT_N_U201103
1660
1661
1662 /// numeric_limits<float> specialization.
1663 template<>
1664 struct numeric_limits<float>
1665 {
1666 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_specialized = true;
1667
1668 static _GLIBCXX_CONSTEXPRconstexpr float
1669 min() _GLIBCXX_USE_NOEXCEPTnoexcept { return __FLT_MIN__1.17549435e-38F; }
1670
1671 static _GLIBCXX_CONSTEXPRconstexpr float
1672 max() _GLIBCXX_USE_NOEXCEPTnoexcept { return __FLT_MAX__3.40282347e+38F; }
1673
1674#if __cplusplus201402L >= 201103L
1675 static constexpr float
1676 lowest() noexcept { return -__FLT_MAX__3.40282347e+38F; }
1677#endif
1678
1679 static _GLIBCXX_USE_CONSTEXPRconstexpr int digits = __FLT_MANT_DIG__24;
1680 static _GLIBCXX_USE_CONSTEXPRconstexpr int digits10 = __FLT_DIG__6;
1681#if __cplusplus201402L >= 201103L
1682 static constexpr int max_digits10
1683 = __glibcxx_max_digits10 (__FLT_MANT_DIG__24);
1684#endif
1685 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_signed = true;
1686 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_integer = false;
1687 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_exact = false;
1688 static _GLIBCXX_USE_CONSTEXPRconstexpr int radix = __FLT_RADIX__2;
1689
1690 static _GLIBCXX_CONSTEXPRconstexpr float
1691 epsilon() _GLIBCXX_USE_NOEXCEPTnoexcept { return __FLT_EPSILON__1.19209290e-7F; }
1692
1693 static _GLIBCXX_CONSTEXPRconstexpr float
1694 round_error() _GLIBCXX_USE_NOEXCEPTnoexcept { return 0.5F; }
1695
1696 static _GLIBCXX_USE_CONSTEXPRconstexpr int min_exponent = __FLT_MIN_EXP__(-125);
1697 static _GLIBCXX_USE_CONSTEXPRconstexpr int min_exponent10 = __FLT_MIN_10_EXP__(-37);
1698 static _GLIBCXX_USE_CONSTEXPRconstexpr int max_exponent = __FLT_MAX_EXP__128;
1699 static _GLIBCXX_USE_CONSTEXPRconstexpr int max_exponent10 = __FLT_MAX_10_EXP__38;
1700
1701 static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_infinity = __FLT_HAS_INFINITY__1;
1702 static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_quiet_NaN = __FLT_HAS_QUIET_NAN__1;
1703 static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_signaling_NaN = has_quiet_NaN;
1704 static _GLIBCXX_USE_CONSTEXPRconstexpr float_denorm_style has_denorm
1705 = bool(__FLT_HAS_DENORM__1) ? denorm_present : denorm_absent;
1706 static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_denorm_loss
1707 = __glibcxx_float_has_denorm_loss;
1708
1709 static _GLIBCXX_CONSTEXPRconstexpr float
1710 infinity() _GLIBCXX_USE_NOEXCEPTnoexcept { return __builtin_huge_valf(); }
1711
1712 static _GLIBCXX_CONSTEXPRconstexpr float
1713 quiet_NaN() _GLIBCXX_USE_NOEXCEPTnoexcept { return __builtin_nanf(""); }
1714
1715 static _GLIBCXX_CONSTEXPRconstexpr float
1716 signaling_NaN() _GLIBCXX_USE_NOEXCEPTnoexcept { return __builtin_nansf(""); }
1717
1718 static _GLIBCXX_CONSTEXPRconstexpr float
1719 denorm_min() _GLIBCXX_USE_NOEXCEPTnoexcept { return __FLT_DENORM_MIN__1.40129846e-45F; }
1720
1721 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_iec559
1722 = has_infinity && has_quiet_NaN && has_denorm == denorm_present;
1723 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_bounded = true;
1724 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_modulo = false;
1725
1726 static _GLIBCXX_USE_CONSTEXPRconstexpr bool traps = __glibcxx_float_traps;
1727 static _GLIBCXX_USE_CONSTEXPRconstexpr bool tinyness_before
1728 = __glibcxx_float_tinyness_before;
1729 static _GLIBCXX_USE_CONSTEXPRconstexpr float_round_style round_style
1730 = round_to_nearest;
1731 };
1732
1733#undef __glibcxx_float_has_denorm_loss
1734#undef __glibcxx_float_traps
1735#undef __glibcxx_float_tinyness_before
1736
1737 /// numeric_limits<double> specialization.
1738 template<>
1739 struct numeric_limits<double>
1740 {
1741 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_specialized = true;
1742
1743 static _GLIBCXX_CONSTEXPRconstexpr double
1744 min() _GLIBCXX_USE_NOEXCEPTnoexcept { return __DBL_MIN__2.2250738585072014e-308; }
1745
1746 static _GLIBCXX_CONSTEXPRconstexpr double
1747 max() _GLIBCXX_USE_NOEXCEPTnoexcept { return __DBL_MAX__1.7976931348623157e+308; }
1748
1749#if __cplusplus201402L >= 201103L
1750 static constexpr double
1751 lowest() noexcept { return -__DBL_MAX__1.7976931348623157e+308; }
1752#endif
1753
1754 static _GLIBCXX_USE_CONSTEXPRconstexpr int digits = __DBL_MANT_DIG__53;
1755 static _GLIBCXX_USE_CONSTEXPRconstexpr int digits10 = __DBL_DIG__15;
1756#if __cplusplus201402L >= 201103L
1757 static constexpr int max_digits10
1758 = __glibcxx_max_digits10 (__DBL_MANT_DIG__53);
1759#endif
1760 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_signed = true;
1761 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_integer = false;
1762 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_exact = false;
1763 static _GLIBCXX_USE_CONSTEXPRconstexpr int radix = __FLT_RADIX__2;
1764
1765 static _GLIBCXX_CONSTEXPRconstexpr double
1766 epsilon() _GLIBCXX_USE_NOEXCEPTnoexcept { return __DBL_EPSILON__2.2204460492503131e-16; }
1767
1768 static _GLIBCXX_CONSTEXPRconstexpr double
1769 round_error() _GLIBCXX_USE_NOEXCEPTnoexcept { return 0.5; }
1770
1771 static _GLIBCXX_USE_CONSTEXPRconstexpr int min_exponent = __DBL_MIN_EXP__(-1021);
1772 static _GLIBCXX_USE_CONSTEXPRconstexpr int min_exponent10 = __DBL_MIN_10_EXP__(-307);
1773 static _GLIBCXX_USE_CONSTEXPRconstexpr int max_exponent = __DBL_MAX_EXP__1024;
1774 static _GLIBCXX_USE_CONSTEXPRconstexpr int max_exponent10 = __DBL_MAX_10_EXP__308;
1775
1776 static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_infinity = __DBL_HAS_INFINITY__1;
1777 static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_quiet_NaN = __DBL_HAS_QUIET_NAN__1;
1778 static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_signaling_NaN = has_quiet_NaN;
1779 static _GLIBCXX_USE_CONSTEXPRconstexpr float_denorm_style has_denorm
1780 = bool(__DBL_HAS_DENORM__1) ? denorm_present : denorm_absent;
1781 static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_denorm_loss
1782 = __glibcxx_double_has_denorm_loss;
1783
1784 static _GLIBCXX_CONSTEXPRconstexpr double
1785 infinity() _GLIBCXX_USE_NOEXCEPTnoexcept { return __builtin_huge_val(); }
1786
1787 static _GLIBCXX_CONSTEXPRconstexpr double
1788 quiet_NaN() _GLIBCXX_USE_NOEXCEPTnoexcept { return __builtin_nan(""); }
1789
1790 static _GLIBCXX_CONSTEXPRconstexpr double
1791 signaling_NaN() _GLIBCXX_USE_NOEXCEPTnoexcept { return __builtin_nans(""); }
1792
1793 static _GLIBCXX_CONSTEXPRconstexpr double
1794 denorm_min() _GLIBCXX_USE_NOEXCEPTnoexcept { return __DBL_DENORM_MIN__4.9406564584124654e-324; }
1795
1796 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_iec559
1797 = has_infinity && has_quiet_NaN && has_denorm == denorm_present;
1798 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_bounded = true;
1799 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_modulo = false;
1800
1801 static _GLIBCXX_USE_CONSTEXPRconstexpr bool traps = __glibcxx_double_traps;
1802 static _GLIBCXX_USE_CONSTEXPRconstexpr bool tinyness_before
1803 = __glibcxx_double_tinyness_before;
1804 static _GLIBCXX_USE_CONSTEXPRconstexpr float_round_style round_style
1805 = round_to_nearest;
1806 };
1807
1808#undef __glibcxx_double_has_denorm_loss
1809#undef __glibcxx_double_traps
1810#undef __glibcxx_double_tinyness_before
1811
1812 /// numeric_limits<long double> specialization.
1813 template<>
1814 struct numeric_limits<long double>
1815 {
1816 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_specialized = true;
1817
1818 static _GLIBCXX_CONSTEXPRconstexpr long double
1819 min() _GLIBCXX_USE_NOEXCEPTnoexcept { return __LDBL_MIN__3.36210314311209350626e-4932L; }
1820
1821 static _GLIBCXX_CONSTEXPRconstexpr long double
1822 max() _GLIBCXX_USE_NOEXCEPTnoexcept { return __LDBL_MAX__1.18973149535723176502e+4932L; }
1823
1824#if __cplusplus201402L >= 201103L
1825 static constexpr long double
1826 lowest() noexcept { return -__LDBL_MAX__1.18973149535723176502e+4932L; }
1827#endif
1828
1829 static _GLIBCXX_USE_CONSTEXPRconstexpr int digits = __LDBL_MANT_DIG__64;
1830 static _GLIBCXX_USE_CONSTEXPRconstexpr int digits10 = __LDBL_DIG__18;
1831#if __cplusplus201402L >= 201103L
1832 static _GLIBCXX_USE_CONSTEXPRconstexpr int max_digits10
1833 = __glibcxx_max_digits10 (__LDBL_MANT_DIG__64);
1834#endif
1835 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_signed = true;
1836 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_integer = false;
1837 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_exact = false;
1838 static _GLIBCXX_USE_CONSTEXPRconstexpr int radix = __FLT_RADIX__2;
1839
1840 static _GLIBCXX_CONSTEXPRconstexpr long double
1841 epsilon() _GLIBCXX_USE_NOEXCEPTnoexcept { return __LDBL_EPSILON__1.08420217248550443401e-19L; }
1842
1843 static _GLIBCXX_CONSTEXPRconstexpr long double
1844 round_error() _GLIBCXX_USE_NOEXCEPTnoexcept { return 0.5L; }
1845
1846 static _GLIBCXX_USE_CONSTEXPRconstexpr int min_exponent = __LDBL_MIN_EXP__(-16381);
1847 static _GLIBCXX_USE_CONSTEXPRconstexpr int min_exponent10 = __LDBL_MIN_10_EXP__(-4931);
1848 static _GLIBCXX_USE_CONSTEXPRconstexpr int max_exponent = __LDBL_MAX_EXP__16384;
1849 static _GLIBCXX_USE_CONSTEXPRconstexpr int max_exponent10 = __LDBL_MAX_10_EXP__4932;
1850
1851 static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_infinity = __LDBL_HAS_INFINITY__1;
1852 static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_quiet_NaN = __LDBL_HAS_QUIET_NAN__1;
1853 static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_signaling_NaN = has_quiet_NaN;
1854 static _GLIBCXX_USE_CONSTEXPRconstexpr float_denorm_style has_denorm
1855 = bool(__LDBL_HAS_DENORM__1) ? denorm_present : denorm_absent;
1856 static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_denorm_loss
1857 = __glibcxx_long_double_has_denorm_loss;
1858
1859 static _GLIBCXX_CONSTEXPRconstexpr long double
1860 infinity() _GLIBCXX_USE_NOEXCEPTnoexcept { return __builtin_huge_vall(); }
1861
1862 static _GLIBCXX_CONSTEXPRconstexpr long double
1863 quiet_NaN() _GLIBCXX_USE_NOEXCEPTnoexcept { return __builtin_nanl(""); }
1864
1865 static _GLIBCXX_CONSTEXPRconstexpr long double
1866 signaling_NaN() _GLIBCXX_USE_NOEXCEPTnoexcept { return __builtin_nansl(""); }
1867
1868 static _GLIBCXX_CONSTEXPRconstexpr long double
1869 denorm_min() _GLIBCXX_USE_NOEXCEPTnoexcept { return __LDBL_DENORM_MIN__3.64519953188247460253e-4951L; }
1870
1871 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_iec559
1872 = has_infinity && has_quiet_NaN && has_denorm == denorm_present;
1873 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_bounded = true;
1874 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_modulo = false;
1875
1876 static _GLIBCXX_USE_CONSTEXPRconstexpr bool traps = __glibcxx_long_double_traps;
1877 static _GLIBCXX_USE_CONSTEXPRconstexpr bool tinyness_before =
1878 __glibcxx_long_double_tinyness_before;
1879 static _GLIBCXX_USE_CONSTEXPRconstexpr float_round_style round_style =
1880 round_to_nearest;
1881 };
1882
1883#undef __glibcxx_long_double_has_denorm_loss
1884#undef __glibcxx_long_double_traps
1885#undef __glibcxx_long_double_tinyness_before
1886
1887_GLIBCXX_END_NAMESPACE_VERSION
1888} // namespace
1889
1890#undef __glibcxx_signed
1891#undef __glibcxx_min
1892#undef __glibcxx_max
1893#undef __glibcxx_digits
1894#undef __glibcxx_digits10
1895#undef __glibcxx_max_digits10
1896
1897#endif // _GLIBCXX_NUMERIC_LIMITS