Bug Summary

File:build/llvm-toolchain-snapshot-16~++20221003111214+1fa2019828ca/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
Warning:line 1719, column 24
The result of the right shift is undefined due to shifting by '4294967295', which is greater or equal to the width of type 'uint64_t'

Annotated Source Code

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clang -cc1 -cc1 -triple x86_64-pc-linux-gnu -analyze -disable-free -clear-ast-before-backend -disable-llvm-verifier -discard-value-names -main-file-name SystemZInstrInfo.cpp -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=cplusplus -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -analyzer-config-compatibility-mode=true -mrelocation-model pic -pic-level 2 -mframe-pointer=none -fmath-errno -ffp-contract=on -fno-rounding-math -mconstructor-aliases -funwind-tables=2 -target-cpu x86-64 -tune-cpu generic -debugger-tuning=gdb -ffunction-sections -fdata-sections -fcoverage-compilation-dir=/build/llvm-toolchain-snapshot-16~++20221003111214+1fa2019828ca/build-llvm/tools/clang/stage2-bins -resource-dir /usr/lib/llvm-16/lib/clang/16.0.0 -D _DEBUG -D _GNU_SOURCE -D __STDC_CONSTANT_MACROS -D __STDC_FORMAT_MACROS -D __STDC_LIMIT_MACROS -I lib/Target/SystemZ -I /build/llvm-toolchain-snapshot-16~++20221003111214+1fa2019828ca/llvm/lib/Target/SystemZ -I include -I /build/llvm-toolchain-snapshot-16~++20221003111214+1fa2019828ca/llvm/include -D _FORTIFY_SOURCE=2 -D NDEBUG -U NDEBUG -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/10/../../../../include/c++/10 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/10/../../../../include/x86_64-linux-gnu/c++/10 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/10/../../../../include/c++/10/backward -internal-isystem /usr/lib/llvm-16/lib/clang/16.0.0/include -internal-isystem /usr/local/include -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/10/../../../../x86_64-linux-gnu/include -internal-externc-isystem /usr/include/x86_64-linux-gnu -internal-externc-isystem /include -internal-externc-isystem /usr/include -fmacro-prefix-map=/build/llvm-toolchain-snapshot-16~++20221003111214+1fa2019828ca/build-llvm/tools/clang/stage2-bins=build-llvm/tools/clang/stage2-bins -fmacro-prefix-map=/build/llvm-toolchain-snapshot-16~++20221003111214+1fa2019828ca/= -fcoverage-prefix-map=/build/llvm-toolchain-snapshot-16~++20221003111214+1fa2019828ca/build-llvm/tools/clang/stage2-bins=build-llvm/tools/clang/stage2-bins -fcoverage-prefix-map=/build/llvm-toolchain-snapshot-16~++20221003111214+1fa2019828ca/= -O2 -Wno-unused-command-line-argument -Wno-unused-parameter -Wwrite-strings -Wno-missing-field-initializers -Wno-long-long -Wno-maybe-uninitialized -Wno-class-memaccess -Wno-redundant-move -Wno-pessimizing-move -Wno-noexcept-type -Wno-comment -Wno-misleading-indentation -std=c++17 -fdeprecated-macro -fdebug-compilation-dir=/build/llvm-toolchain-snapshot-16~++20221003111214+1fa2019828ca/build-llvm/tools/clang/stage2-bins -fdebug-prefix-map=/build/llvm-toolchain-snapshot-16~++20221003111214+1fa2019828ca/build-llvm/tools/clang/stage2-bins=build-llvm/tools/clang/stage2-bins -fdebug-prefix-map=/build/llvm-toolchain-snapshot-16~++20221003111214+1fa2019828ca/= -ferror-limit 19 -fvisibility=hidden -fvisibility-inlines-hidden -stack-protector 2 -fgnuc-version=4.2.1 -fcolor-diagnostics -vectorize-loops -vectorize-slp -analyzer-output=html -analyzer-config stable-report-filename=true -faddrsig -D__GCC_HAVE_DWARF2_CFI_ASM=1 -o /tmp/scan-build-2022-10-03-140002-15933-1 -x c++ /build/llvm-toolchain-snapshot-16~++20221003111214+1fa2019828ca/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp

/build/llvm-toolchain-snapshot-16~++20221003111214+1fa2019828ca/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp

1//===-- SystemZInstrInfo.cpp - SystemZ instruction information ------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the SystemZ implementation of the TargetInstrInfo class.
10//
11//===----------------------------------------------------------------------===//
12
13#include "SystemZInstrInfo.h"
14#include "MCTargetDesc/SystemZMCTargetDesc.h"
15#include "SystemZ.h"
16#include "SystemZInstrBuilder.h"
17#include "SystemZSubtarget.h"
18#include "llvm/ADT/Statistic.h"
19#include "llvm/CodeGen/LiveInterval.h"
20#include "llvm/CodeGen/LiveIntervals.h"
21#include "llvm/CodeGen/LivePhysRegs.h"
22#include "llvm/CodeGen/LiveVariables.h"
23#include "llvm/CodeGen/MachineBasicBlock.h"
24#include "llvm/CodeGen/MachineFrameInfo.h"
25#include "llvm/CodeGen/MachineFunction.h"
26#include "llvm/CodeGen/MachineInstr.h"
27#include "llvm/CodeGen/MachineMemOperand.h"
28#include "llvm/CodeGen/MachineOperand.h"
29#include "llvm/CodeGen/MachineRegisterInfo.h"
30#include "llvm/CodeGen/SlotIndexes.h"
31#include "llvm/CodeGen/StackMaps.h"
32#include "llvm/CodeGen/TargetInstrInfo.h"
33#include "llvm/CodeGen/TargetSubtargetInfo.h"
34#include "llvm/CodeGen/VirtRegMap.h"
35#include "llvm/MC/MCInstrDesc.h"
36#include "llvm/MC/MCRegisterInfo.h"
37#include "llvm/Support/BranchProbability.h"
38#include "llvm/Support/ErrorHandling.h"
39#include "llvm/Support/MathExtras.h"
40#include "llvm/Target/TargetMachine.h"
41#include <cassert>
42#include <cstdint>
43#include <iterator>
44
45using namespace llvm;
46
47#define GET_INSTRINFO_CTOR_DTOR
48#define GET_INSTRMAP_INFO
49#include "SystemZGenInstrInfo.inc"
50
51#define DEBUG_TYPE"systemz-II" "systemz-II"
52
53// Return a mask with Count low bits set.
54static uint64_t allOnes(unsigned int Count) {
55 return Count == 0 ? 0 : (uint64_t(1) << (Count - 1) << 1) - 1;
56}
57
58// Pin the vtable to this file.
59void SystemZInstrInfo::anchor() {}
60
61SystemZInstrInfo::SystemZInstrInfo(SystemZSubtarget &sti)
62 : SystemZGenInstrInfo(SystemZ::ADJCALLSTACKDOWN, SystemZ::ADJCALLSTACKUP),
63 RI(sti.getSpecialRegisters()->getReturnFunctionAddressRegister()),
64 STI(sti) {}
65
66// MI is a 128-bit load or store. Split it into two 64-bit loads or stores,
67// each having the opcode given by NewOpcode.
68void SystemZInstrInfo::splitMove(MachineBasicBlock::iterator MI,
69 unsigned NewOpcode) const {
70 MachineBasicBlock *MBB = MI->getParent();
71 MachineFunction &MF = *MBB->getParent();
72
73 // Get two load or store instructions. Use the original instruction for one
74 // of them (arbitrarily the second here) and create a clone for the other.
75 MachineInstr *EarlierMI = MF.CloneMachineInstr(&*MI);
76 MBB->insert(MI, EarlierMI);
77
78 // Set up the two 64-bit registers and remember super reg and its flags.
79 MachineOperand &HighRegOp = EarlierMI->getOperand(0);
80 MachineOperand &LowRegOp = MI->getOperand(0);
81 Register Reg128 = LowRegOp.getReg();
82 unsigned Reg128Killed = getKillRegState(LowRegOp.isKill());
83 unsigned Reg128Undef = getUndefRegState(LowRegOp.isUndef());
84 HighRegOp.setReg(RI.getSubReg(HighRegOp.getReg(), SystemZ::subreg_h64));
85 LowRegOp.setReg(RI.getSubReg(LowRegOp.getReg(), SystemZ::subreg_l64));
86
87 if (MI->mayStore()) {
88 // Add implicit uses of the super register in case one of the subregs is
89 // undefined. We could track liveness and skip storing an undefined
90 // subreg, but this is hopefully rare (discovered with llvm-stress).
91 // If Reg128 was killed, set kill flag on MI.
92 unsigned Reg128UndefImpl = (Reg128Undef | RegState::Implicit);
93 MachineInstrBuilder(MF, EarlierMI).addReg(Reg128, Reg128UndefImpl);
94 MachineInstrBuilder(MF, MI).addReg(Reg128, (Reg128UndefImpl | Reg128Killed));
95 }
96
97 // The address in the first (high) instruction is already correct.
98 // Adjust the offset in the second (low) instruction.
99 MachineOperand &HighOffsetOp = EarlierMI->getOperand(2);
100 MachineOperand &LowOffsetOp = MI->getOperand(2);
101 LowOffsetOp.setImm(LowOffsetOp.getImm() + 8);
102
103 // Clear the kill flags on the registers in the first instruction.
104 if (EarlierMI->getOperand(0).isReg() && EarlierMI->getOperand(0).isUse())
105 EarlierMI->getOperand(0).setIsKill(false);
106 EarlierMI->getOperand(1).setIsKill(false);
107 EarlierMI->getOperand(3).setIsKill(false);
108
109 // Set the opcodes.
110 unsigned HighOpcode = getOpcodeForOffset(NewOpcode, HighOffsetOp.getImm());
111 unsigned LowOpcode = getOpcodeForOffset(NewOpcode, LowOffsetOp.getImm());
112 assert(HighOpcode && LowOpcode && "Both offsets should be in range")(static_cast <bool> (HighOpcode && LowOpcode &&
"Both offsets should be in range") ? void (0) : __assert_fail
("HighOpcode && LowOpcode && \"Both offsets should be in range\""
, "llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp", 112, __extension__
__PRETTY_FUNCTION__))
;
113
114 EarlierMI->setDesc(get(HighOpcode));
115 MI->setDesc(get(LowOpcode));
116}
117
118// Split ADJDYNALLOC instruction MI.
119void SystemZInstrInfo::splitAdjDynAlloc(MachineBasicBlock::iterator MI) const {
120 MachineBasicBlock *MBB = MI->getParent();
121 MachineFunction &MF = *MBB->getParent();
122 MachineFrameInfo &MFFrame = MF.getFrameInfo();
123 MachineOperand &OffsetMO = MI->getOperand(2);
124 SystemZCallingConventionRegisters *Regs = STI.getSpecialRegisters();
125
126 uint64_t Offset = (MFFrame.getMaxCallFrameSize() +
127 Regs->getCallFrameSize() +
128 Regs->getStackPointerBias() +
129 OffsetMO.getImm());
130 unsigned NewOpcode = getOpcodeForOffset(SystemZ::LA, Offset);
131 assert(NewOpcode && "No support for huge argument lists yet")(static_cast <bool> (NewOpcode && "No support for huge argument lists yet"
) ? void (0) : __assert_fail ("NewOpcode && \"No support for huge argument lists yet\""
, "llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp", 131, __extension__
__PRETTY_FUNCTION__))
;
132 MI->setDesc(get(NewOpcode));
133 OffsetMO.setImm(Offset);
134}
135
136// MI is an RI-style pseudo instruction. Replace it with LowOpcode
137// if the first operand is a low GR32 and HighOpcode if the first operand
138// is a high GR32. ConvertHigh is true if LowOpcode takes a signed operand
139// and HighOpcode takes an unsigned 32-bit operand. In those cases,
140// MI has the same kind of operand as LowOpcode, so needs to be converted
141// if HighOpcode is used.
142void SystemZInstrInfo::expandRIPseudo(MachineInstr &MI, unsigned LowOpcode,
143 unsigned HighOpcode,
144 bool ConvertHigh) const {
145 Register Reg = MI.getOperand(0).getReg();
146 bool IsHigh = SystemZ::isHighReg(Reg);
147 MI.setDesc(get(IsHigh ? HighOpcode : LowOpcode));
148 if (IsHigh && ConvertHigh)
149 MI.getOperand(1).setImm(uint32_t(MI.getOperand(1).getImm()));
150}
151
152// MI is a three-operand RIE-style pseudo instruction. Replace it with
153// LowOpcodeK if the registers are both low GR32s, otherwise use a move
154// followed by HighOpcode or LowOpcode, depending on whether the target
155// is a high or low GR32.
156void SystemZInstrInfo::expandRIEPseudo(MachineInstr &MI, unsigned LowOpcode,
157 unsigned LowOpcodeK,
158 unsigned HighOpcode) const {
159 Register DestReg = MI.getOperand(0).getReg();
160 Register SrcReg = MI.getOperand(1).getReg();
161 bool DestIsHigh = SystemZ::isHighReg(DestReg);
162 bool SrcIsHigh = SystemZ::isHighReg(SrcReg);
163 if (!DestIsHigh && !SrcIsHigh)
164 MI.setDesc(get(LowOpcodeK));
165 else {
166 if (DestReg != SrcReg) {
167 emitGRX32Move(*MI.getParent(), MI, MI.getDebugLoc(), DestReg, SrcReg,
168 SystemZ::LR, 32, MI.getOperand(1).isKill(),
169 MI.getOperand(1).isUndef());
170 MI.getOperand(1).setReg(DestReg);
171 }
172 MI.setDesc(get(DestIsHigh ? HighOpcode : LowOpcode));
173 MI.tieOperands(0, 1);
174 }
175}
176
177// MI is an RXY-style pseudo instruction. Replace it with LowOpcode
178// if the first operand is a low GR32 and HighOpcode if the first operand
179// is a high GR32.
180void SystemZInstrInfo::expandRXYPseudo(MachineInstr &MI, unsigned LowOpcode,
181 unsigned HighOpcode) const {
182 Register Reg = MI.getOperand(0).getReg();
183 unsigned Opcode = getOpcodeForOffset(
184 SystemZ::isHighReg(Reg) ? HighOpcode : LowOpcode,
185 MI.getOperand(2).getImm());
186 MI.setDesc(get(Opcode));
187}
188
189// MI is a load-on-condition pseudo instruction with a single register
190// (source or destination) operand. Replace it with LowOpcode if the
191// register is a low GR32 and HighOpcode if the register is a high GR32.
192void SystemZInstrInfo::expandLOCPseudo(MachineInstr &MI, unsigned LowOpcode,
193 unsigned HighOpcode) const {
194 Register Reg = MI.getOperand(0).getReg();
195 unsigned Opcode = SystemZ::isHighReg(Reg) ? HighOpcode : LowOpcode;
196 MI.setDesc(get(Opcode));
197}
198
199// MI is an RR-style pseudo instruction that zero-extends the low Size bits
200// of one GRX32 into another. Replace it with LowOpcode if both operands
201// are low registers, otherwise use RISB[LH]G.
202void SystemZInstrInfo::expandZExtPseudo(MachineInstr &MI, unsigned LowOpcode,
203 unsigned Size) const {
204 MachineInstrBuilder MIB =
205 emitGRX32Move(*MI.getParent(), MI, MI.getDebugLoc(),
206 MI.getOperand(0).getReg(), MI.getOperand(1).getReg(), LowOpcode,
207 Size, MI.getOperand(1).isKill(), MI.getOperand(1).isUndef());
208
209 // Keep the remaining operands as-is.
210 for (const MachineOperand &MO : llvm::drop_begin(MI.operands(), 2))
211 MIB.add(MO);
212
213 MI.eraseFromParent();
214}
215
216void SystemZInstrInfo::expandLoadStackGuard(MachineInstr *MI) const {
217 MachineBasicBlock *MBB = MI->getParent();
218 MachineFunction &MF = *MBB->getParent();
219 const Register Reg64 = MI->getOperand(0).getReg();
220 const Register Reg32 = RI.getSubReg(Reg64, SystemZ::subreg_l32);
221
222 // EAR can only load the low subregister so us a shift for %a0 to produce
223 // the GR containing %a0 and %a1.
224
225 // ear <reg>, %a0
226 BuildMI(*MBB, MI, MI->getDebugLoc(), get(SystemZ::EAR), Reg32)
227 .addReg(SystemZ::A0)
228 .addReg(Reg64, RegState::ImplicitDefine);
229
230 // sllg <reg>, <reg>, 32
231 BuildMI(*MBB, MI, MI->getDebugLoc(), get(SystemZ::SLLG), Reg64)
232 .addReg(Reg64)
233 .addReg(0)
234 .addImm(32);
235
236 // ear <reg>, %a1
237 BuildMI(*MBB, MI, MI->getDebugLoc(), get(SystemZ::EAR), Reg32)
238 .addReg(SystemZ::A1);
239
240 // lg <reg>, 40(<reg>)
241 MI->setDesc(get(SystemZ::LG));
242 MachineInstrBuilder(MF, MI).addReg(Reg64).addImm(40).addReg(0);
243}
244
245// Emit a zero-extending move from 32-bit GPR SrcReg to 32-bit GPR
246// DestReg before MBBI in MBB. Use LowLowOpcode when both DestReg and SrcReg
247// are low registers, otherwise use RISB[LH]G. Size is the number of bits
248// taken from the low end of SrcReg (8 for LLCR, 16 for LLHR and 32 for LR).
249// KillSrc is true if this move is the last use of SrcReg.
250MachineInstrBuilder
251SystemZInstrInfo::emitGRX32Move(MachineBasicBlock &MBB,
252 MachineBasicBlock::iterator MBBI,
253 const DebugLoc &DL, unsigned DestReg,
254 unsigned SrcReg, unsigned LowLowOpcode,
255 unsigned Size, bool KillSrc,
256 bool UndefSrc) const {
257 unsigned Opcode;
258 bool DestIsHigh = SystemZ::isHighReg(DestReg);
259 bool SrcIsHigh = SystemZ::isHighReg(SrcReg);
260 if (DestIsHigh && SrcIsHigh)
261 Opcode = SystemZ::RISBHH;
262 else if (DestIsHigh && !SrcIsHigh)
263 Opcode = SystemZ::RISBHL;
264 else if (!DestIsHigh && SrcIsHigh)
265 Opcode = SystemZ::RISBLH;
266 else {
267 return BuildMI(MBB, MBBI, DL, get(LowLowOpcode), DestReg)
268 .addReg(SrcReg, getKillRegState(KillSrc) | getUndefRegState(UndefSrc));
269 }
270 unsigned Rotate = (DestIsHigh != SrcIsHigh ? 32 : 0);
271 return BuildMI(MBB, MBBI, DL, get(Opcode), DestReg)
272 .addReg(DestReg, RegState::Undef)
273 .addReg(SrcReg, getKillRegState(KillSrc) | getUndefRegState(UndefSrc))
274 .addImm(32 - Size).addImm(128 + 31).addImm(Rotate);
275}
276
277MachineInstr *SystemZInstrInfo::commuteInstructionImpl(MachineInstr &MI,
278 bool NewMI,
279 unsigned OpIdx1,
280 unsigned OpIdx2) const {
281 auto cloneIfNew = [NewMI](MachineInstr &MI) -> MachineInstr & {
282 if (NewMI)
283 return *MI.getParent()->getParent()->CloneMachineInstr(&MI);
284 return MI;
285 };
286
287 switch (MI.getOpcode()) {
288 case SystemZ::SELRMux:
289 case SystemZ::SELFHR:
290 case SystemZ::SELR:
291 case SystemZ::SELGR:
292 case SystemZ::LOCRMux:
293 case SystemZ::LOCFHR:
294 case SystemZ::LOCR:
295 case SystemZ::LOCGR: {
296 auto &WorkingMI = cloneIfNew(MI);
297 // Invert condition.
298 unsigned CCValid = WorkingMI.getOperand(3).getImm();
299 unsigned CCMask = WorkingMI.getOperand(4).getImm();
300 WorkingMI.getOperand(4).setImm(CCMask ^ CCValid);
301 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
302 OpIdx1, OpIdx2);
303 }
304 default:
305 return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
306 }
307}
308
309// If MI is a simple load or store for a frame object, return the register
310// it loads or stores and set FrameIndex to the index of the frame object.
311// Return 0 otherwise.
312//
313// Flag is SimpleBDXLoad for loads and SimpleBDXStore for stores.
314static int isSimpleMove(const MachineInstr &MI, int &FrameIndex,
315 unsigned Flag) {
316 const MCInstrDesc &MCID = MI.getDesc();
317 if ((MCID.TSFlags & Flag) && MI.getOperand(1).isFI() &&
318 MI.getOperand(2).getImm() == 0 && MI.getOperand(3).getReg() == 0) {
319 FrameIndex = MI.getOperand(1).getIndex();
320 return MI.getOperand(0).getReg();
321 }
322 return 0;
323}
324
325unsigned SystemZInstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
326 int &FrameIndex) const {
327 return isSimpleMove(MI, FrameIndex, SystemZII::SimpleBDXLoad);
328}
329
330unsigned SystemZInstrInfo::isStoreToStackSlot(const MachineInstr &MI,
331 int &FrameIndex) const {
332 return isSimpleMove(MI, FrameIndex, SystemZII::SimpleBDXStore);
333}
334
335bool SystemZInstrInfo::isStackSlotCopy(const MachineInstr &MI,
336 int &DestFrameIndex,
337 int &SrcFrameIndex) const {
338 // Check for MVC 0(Length,FI1),0(FI2)
339 const MachineFrameInfo &MFI = MI.getParent()->getParent()->getFrameInfo();
340 if (MI.getOpcode() != SystemZ::MVC || !MI.getOperand(0).isFI() ||
341 MI.getOperand(1).getImm() != 0 || !MI.getOperand(3).isFI() ||
342 MI.getOperand(4).getImm() != 0)
343 return false;
344
345 // Check that Length covers the full slots.
346 int64_t Length = MI.getOperand(2).getImm();
347 unsigned FI1 = MI.getOperand(0).getIndex();
348 unsigned FI2 = MI.getOperand(3).getIndex();
349 if (MFI.getObjectSize(FI1) != Length ||
350 MFI.getObjectSize(FI2) != Length)
351 return false;
352
353 DestFrameIndex = FI1;
354 SrcFrameIndex = FI2;
355 return true;
356}
357
358bool SystemZInstrInfo::analyzeBranch(MachineBasicBlock &MBB,
359 MachineBasicBlock *&TBB,
360 MachineBasicBlock *&FBB,
361 SmallVectorImpl<MachineOperand> &Cond,
362 bool AllowModify) const {
363 // Most of the code and comments here are boilerplate.
364
365 // Start from the bottom of the block and work up, examining the
366 // terminator instructions.
367 MachineBasicBlock::iterator I = MBB.end();
368 while (I != MBB.begin()) {
369 --I;
370 if (I->isDebugInstr())
371 continue;
372
373 // Working from the bottom, when we see a non-terminator instruction, we're
374 // done.
375 if (!isUnpredicatedTerminator(*I))
376 break;
377
378 // A terminator that isn't a branch can't easily be handled by this
379 // analysis.
380 if (!I->isBranch())
381 return true;
382
383 // Can't handle indirect branches.
384 SystemZII::Branch Branch(getBranchInfo(*I));
385 if (!Branch.hasMBBTarget())
386 return true;
387
388 // Punt on compound branches.
389 if (Branch.Type != SystemZII::BranchNormal)
390 return true;
391
392 if (Branch.CCMask == SystemZ::CCMASK_ANY) {
393 // Handle unconditional branches.
394 if (!AllowModify) {
395 TBB = Branch.getMBBTarget();
396 continue;
397 }
398
399 // If the block has any instructions after a JMP, delete them.
400 MBB.erase(std::next(I), MBB.end());
401
402 Cond.clear();
403 FBB = nullptr;
404
405 // Delete the JMP if it's equivalent to a fall-through.
406 if (MBB.isLayoutSuccessor(Branch.getMBBTarget())) {
407 TBB = nullptr;
408 I->eraseFromParent();
409 I = MBB.end();
410 continue;
411 }
412
413 // TBB is used to indicate the unconditinal destination.
414 TBB = Branch.getMBBTarget();
415 continue;
416 }
417
418 // Working from the bottom, handle the first conditional branch.
419 if (Cond.empty()) {
420 // FIXME: add X86-style branch swap
421 FBB = TBB;
422 TBB = Branch.getMBBTarget();
423 Cond.push_back(MachineOperand::CreateImm(Branch.CCValid));
424 Cond.push_back(MachineOperand::CreateImm(Branch.CCMask));
425 continue;
426 }
427
428 // Handle subsequent conditional branches.
429 assert(Cond.size() == 2 && TBB && "Should have seen a conditional branch")(static_cast <bool> (Cond.size() == 2 && TBB &&
"Should have seen a conditional branch") ? void (0) : __assert_fail
("Cond.size() == 2 && TBB && \"Should have seen a conditional branch\""
, "llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp", 429, __extension__
__PRETTY_FUNCTION__))
;
430
431 // Only handle the case where all conditional branches branch to the same
432 // destination.
433 if (TBB != Branch.getMBBTarget())
434 return true;
435
436 // If the conditions are the same, we can leave them alone.
437 unsigned OldCCValid = Cond[0].getImm();
438 unsigned OldCCMask = Cond[1].getImm();
439 if (OldCCValid == Branch.CCValid && OldCCMask == Branch.CCMask)
440 continue;
441
442 // FIXME: Try combining conditions like X86 does. Should be easy on Z!
443 return false;
444 }
445
446 return false;
447}
448
449unsigned SystemZInstrInfo::removeBranch(MachineBasicBlock &MBB,
450 int *BytesRemoved) const {
451 assert(!BytesRemoved && "code size not handled")(static_cast <bool> (!BytesRemoved && "code size not handled"
) ? void (0) : __assert_fail ("!BytesRemoved && \"code size not handled\""
, "llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp", 451, __extension__
__PRETTY_FUNCTION__))
;
452
453 // Most of the code and comments here are boilerplate.
454 MachineBasicBlock::iterator I = MBB.end();
455 unsigned Count = 0;
456
457 while (I != MBB.begin()) {
458 --I;
459 if (I->isDebugInstr())
460 continue;
461 if (!I->isBranch())
462 break;
463 if (!getBranchInfo(*I).hasMBBTarget())
464 break;
465 // Remove the branch.
466 I->eraseFromParent();
467 I = MBB.end();
468 ++Count;
469 }
470
471 return Count;
472}
473
474bool SystemZInstrInfo::
475reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
476 assert(Cond.size() == 2 && "Invalid condition")(static_cast <bool> (Cond.size() == 2 && "Invalid condition"
) ? void (0) : __assert_fail ("Cond.size() == 2 && \"Invalid condition\""
, "llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp", 476, __extension__
__PRETTY_FUNCTION__))
;
477 Cond[1].setImm(Cond[1].getImm() ^ Cond[0].getImm());
478 return false;
479}
480
481unsigned SystemZInstrInfo::insertBranch(MachineBasicBlock &MBB,
482 MachineBasicBlock *TBB,
483 MachineBasicBlock *FBB,
484 ArrayRef<MachineOperand> Cond,
485 const DebugLoc &DL,
486 int *BytesAdded) const {
487 // In this function we output 32-bit branches, which should always
488 // have enough range. They can be shortened and relaxed by later code
489 // in the pipeline, if desired.
490
491 // Shouldn't be a fall through.
492 assert(TBB && "insertBranch must not be told to insert a fallthrough")(static_cast <bool> (TBB && "insertBranch must not be told to insert a fallthrough"
) ? void (0) : __assert_fail ("TBB && \"insertBranch must not be told to insert a fallthrough\""
, "llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp", 492, __extension__
__PRETTY_FUNCTION__))
;
493 assert((Cond.size() == 2 || Cond.size() == 0) &&(static_cast <bool> ((Cond.size() == 2 || Cond.size() ==
0) && "SystemZ branch conditions have one component!"
) ? void (0) : __assert_fail ("(Cond.size() == 2 || Cond.size() == 0) && \"SystemZ branch conditions have one component!\""
, "llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp", 494, __extension__
__PRETTY_FUNCTION__))
494 "SystemZ branch conditions have one component!")(static_cast <bool> ((Cond.size() == 2 || Cond.size() ==
0) && "SystemZ branch conditions have one component!"
) ? void (0) : __assert_fail ("(Cond.size() == 2 || Cond.size() == 0) && \"SystemZ branch conditions have one component!\""
, "llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp", 494, __extension__
__PRETTY_FUNCTION__))
;
495 assert(!BytesAdded && "code size not handled")(static_cast <bool> (!BytesAdded && "code size not handled"
) ? void (0) : __assert_fail ("!BytesAdded && \"code size not handled\""
, "llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp", 495, __extension__
__PRETTY_FUNCTION__))
;
496
497 if (Cond.empty()) {
498 // Unconditional branch?
499 assert(!FBB && "Unconditional branch with multiple successors!")(static_cast <bool> (!FBB && "Unconditional branch with multiple successors!"
) ? void (0) : __assert_fail ("!FBB && \"Unconditional branch with multiple successors!\""
, "llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp", 499, __extension__
__PRETTY_FUNCTION__))
;
500 BuildMI(&MBB, DL, get(SystemZ::J)).addMBB(TBB);
501 return 1;
502 }
503
504 // Conditional branch.
505 unsigned Count = 0;
506 unsigned CCValid = Cond[0].getImm();
507 unsigned CCMask = Cond[1].getImm();
508 BuildMI(&MBB, DL, get(SystemZ::BRC))
509 .addImm(CCValid).addImm(CCMask).addMBB(TBB);
510 ++Count;
511
512 if (FBB) {
513 // Two-way Conditional branch. Insert the second branch.
514 BuildMI(&MBB, DL, get(SystemZ::J)).addMBB(FBB);
515 ++Count;
516 }
517 return Count;
518}
519
520bool SystemZInstrInfo::analyzeCompare(const MachineInstr &MI, Register &SrcReg,
521 Register &SrcReg2, int64_t &Mask,
522 int64_t &Value) const {
523 assert(MI.isCompare() && "Caller should have checked for a comparison")(static_cast <bool> (MI.isCompare() && "Caller should have checked for a comparison"
) ? void (0) : __assert_fail ("MI.isCompare() && \"Caller should have checked for a comparison\""
, "llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp", 523, __extension__
__PRETTY_FUNCTION__))
;
524
525 if (MI.getNumExplicitOperands() == 2 && MI.getOperand(0).isReg() &&
526 MI.getOperand(1).isImm()) {
527 SrcReg = MI.getOperand(0).getReg();
528 SrcReg2 = 0;
529 Value = MI.getOperand(1).getImm();
530 Mask = ~0;
531 return true;
532 }
533
534 return false;
535}
536
537bool SystemZInstrInfo::canInsertSelect(const MachineBasicBlock &MBB,
538 ArrayRef<MachineOperand> Pred,
539 Register DstReg, Register TrueReg,
540 Register FalseReg, int &CondCycles,
541 int &TrueCycles,
542 int &FalseCycles) const {
543 // Not all subtargets have LOCR instructions.
544 if (!STI.hasLoadStoreOnCond())
545 return false;
546 if (Pred.size() != 2)
547 return false;
548
549 // Check register classes.
550 const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
551 const TargetRegisterClass *RC =
552 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
553 if (!RC)
554 return false;
555
556 // We have LOCR instructions for 32 and 64 bit general purpose registers.
557 if ((STI.hasLoadStoreOnCond2() &&
558 SystemZ::GRX32BitRegClass.hasSubClassEq(RC)) ||
559 SystemZ::GR32BitRegClass.hasSubClassEq(RC) ||
560 SystemZ::GR64BitRegClass.hasSubClassEq(RC)) {
561 CondCycles = 2;
562 TrueCycles = 2;
563 FalseCycles = 2;
564 return true;
565 }
566
567 // Can't do anything else.
568 return false;
569}
570
571void SystemZInstrInfo::insertSelect(MachineBasicBlock &MBB,
572 MachineBasicBlock::iterator I,
573 const DebugLoc &DL, Register DstReg,
574 ArrayRef<MachineOperand> Pred,
575 Register TrueReg,
576 Register FalseReg) const {
577 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
578 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
579
580 assert(Pred.size() == 2 && "Invalid condition")(static_cast <bool> (Pred.size() == 2 && "Invalid condition"
) ? void (0) : __assert_fail ("Pred.size() == 2 && \"Invalid condition\""
, "llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp", 580, __extension__
__PRETTY_FUNCTION__))
;
581 unsigned CCValid = Pred[0].getImm();
582 unsigned CCMask = Pred[1].getImm();
583
584 unsigned Opc;
585 if (SystemZ::GRX32BitRegClass.hasSubClassEq(RC)) {
586 if (STI.hasMiscellaneousExtensions3())
587 Opc = SystemZ::SELRMux;
588 else if (STI.hasLoadStoreOnCond2())
589 Opc = SystemZ::LOCRMux;
590 else {
591 Opc = SystemZ::LOCR;
592 MRI.constrainRegClass(DstReg, &SystemZ::GR32BitRegClass);
593 Register TReg = MRI.createVirtualRegister(&SystemZ::GR32BitRegClass);
594 Register FReg = MRI.createVirtualRegister(&SystemZ::GR32BitRegClass);
595 BuildMI(MBB, I, DL, get(TargetOpcode::COPY), TReg).addReg(TrueReg);
596 BuildMI(MBB, I, DL, get(TargetOpcode::COPY), FReg).addReg(FalseReg);
597 TrueReg = TReg;
598 FalseReg = FReg;
599 }
600 } else if (SystemZ::GR64BitRegClass.hasSubClassEq(RC)) {
601 if (STI.hasMiscellaneousExtensions3())
602 Opc = SystemZ::SELGR;
603 else
604 Opc = SystemZ::LOCGR;
605 } else
606 llvm_unreachable("Invalid register class")::llvm::llvm_unreachable_internal("Invalid register class", "llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp"
, 606)
;
607
608 BuildMI(MBB, I, DL, get(Opc), DstReg)
609 .addReg(FalseReg).addReg(TrueReg)
610 .addImm(CCValid).addImm(CCMask);
611}
612
613bool SystemZInstrInfo::FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI,
614 Register Reg,
615 MachineRegisterInfo *MRI) const {
616 unsigned DefOpc = DefMI.getOpcode();
617 if (DefOpc != SystemZ::LHIMux && DefOpc != SystemZ::LHI &&
618 DefOpc != SystemZ::LGHI)
619 return false;
620 if (DefMI.getOperand(0).getReg() != Reg)
621 return false;
622 int32_t ImmVal = (int32_t)DefMI.getOperand(1).getImm();
623
624 unsigned UseOpc = UseMI.getOpcode();
625 unsigned NewUseOpc;
626 unsigned UseIdx;
627 int CommuteIdx = -1;
628 bool TieOps = false;
629 switch (UseOpc) {
630 case SystemZ::SELRMux:
631 TieOps = true;
632 [[fallthrough]];
633 case SystemZ::LOCRMux:
634 if (!STI.hasLoadStoreOnCond2())
635 return false;
636 NewUseOpc = SystemZ::LOCHIMux;
637 if (UseMI.getOperand(2).getReg() == Reg)
638 UseIdx = 2;
639 else if (UseMI.getOperand(1).getReg() == Reg)
640 UseIdx = 2, CommuteIdx = 1;
641 else
642 return false;
643 break;
644 case SystemZ::SELGR:
645 TieOps = true;
646 [[fallthrough]];
647 case SystemZ::LOCGR:
648 if (!STI.hasLoadStoreOnCond2())
649 return false;
650 NewUseOpc = SystemZ::LOCGHI;
651 if (UseMI.getOperand(2).getReg() == Reg)
652 UseIdx = 2;
653 else if (UseMI.getOperand(1).getReg() == Reg)
654 UseIdx = 2, CommuteIdx = 1;
655 else
656 return false;
657 break;
658 default:
659 return false;
660 }
661
662 if (CommuteIdx != -1)
663 if (!commuteInstruction(UseMI, false, CommuteIdx, UseIdx))
664 return false;
665
666 bool DeleteDef = MRI->hasOneNonDBGUse(Reg);
667 UseMI.setDesc(get(NewUseOpc));
668 if (TieOps)
669 UseMI.tieOperands(0, 1);
670 UseMI.getOperand(UseIdx).ChangeToImmediate(ImmVal);
671 if (DeleteDef)
672 DefMI.eraseFromParent();
673
674 return true;
675}
676
677bool SystemZInstrInfo::isPredicable(const MachineInstr &MI) const {
678 unsigned Opcode = MI.getOpcode();
679 if (Opcode == SystemZ::Return ||
680 Opcode == SystemZ::Return_XPLINK ||
681 Opcode == SystemZ::Trap ||
682 Opcode == SystemZ::CallJG ||
683 Opcode == SystemZ::CallBR)
684 return true;
685 return false;
686}
687
688bool SystemZInstrInfo::
689isProfitableToIfCvt(MachineBasicBlock &MBB,
690 unsigned NumCycles, unsigned ExtraPredCycles,
691 BranchProbability Probability) const {
692 // Avoid using conditional returns at the end of a loop (since then
693 // we'd need to emit an unconditional branch to the beginning anyway,
694 // making the loop body longer). This doesn't apply for low-probability
695 // loops (eg. compare-and-swap retry), so just decide based on branch
696 // probability instead of looping structure.
697 // However, since Compare and Trap instructions cost the same as a regular
698 // Compare instruction, we should allow the if conversion to convert this
699 // into a Conditional Compare regardless of the branch probability.
700 if (MBB.getLastNonDebugInstr()->getOpcode() != SystemZ::Trap &&
701 MBB.succ_empty() && Probability < BranchProbability(1, 8))
702 return false;
703 // For now only convert single instructions.
704 return NumCycles == 1;
705}
706
707bool SystemZInstrInfo::
708isProfitableToIfCvt(MachineBasicBlock &TMBB,
709 unsigned NumCyclesT, unsigned ExtraPredCyclesT,
710 MachineBasicBlock &FMBB,
711 unsigned NumCyclesF, unsigned ExtraPredCyclesF,
712 BranchProbability Probability) const {
713 // For now avoid converting mutually-exclusive cases.
714 return false;
715}
716
717bool SystemZInstrInfo::
718isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
719 BranchProbability Probability) const {
720 // For now only duplicate single instructions.
721 return NumCycles == 1;
722}
723
724bool SystemZInstrInfo::PredicateInstruction(
725 MachineInstr &MI, ArrayRef<MachineOperand> Pred) const {
726 assert(Pred.size() == 2 && "Invalid condition")(static_cast <bool> (Pred.size() == 2 && "Invalid condition"
) ? void (0) : __assert_fail ("Pred.size() == 2 && \"Invalid condition\""
, "llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp", 726, __extension__
__PRETTY_FUNCTION__))
;
727 unsigned CCValid = Pred[0].getImm();
728 unsigned CCMask = Pred[1].getImm();
729 assert(CCMask > 0 && CCMask < 15 && "Invalid predicate")(static_cast <bool> (CCMask > 0 && CCMask <
15 && "Invalid predicate") ? void (0) : __assert_fail
("CCMask > 0 && CCMask < 15 && \"Invalid predicate\""
, "llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp", 729, __extension__
__PRETTY_FUNCTION__))
;
730 unsigned Opcode = MI.getOpcode();
731 if (Opcode == SystemZ::Trap) {
732 MI.setDesc(get(SystemZ::CondTrap));
733 MachineInstrBuilder(*MI.getParent()->getParent(), MI)
734 .addImm(CCValid).addImm(CCMask)
735 .addReg(SystemZ::CC, RegState::Implicit);
736 return true;
737 }
738 if (Opcode == SystemZ::Return || Opcode == SystemZ::Return_XPLINK) {
739 MI.setDesc(get(Opcode == SystemZ::Return ? SystemZ::CondReturn
740 : SystemZ::CondReturn_XPLINK));
741 MachineInstrBuilder(*MI.getParent()->getParent(), MI)
742 .addImm(CCValid)
743 .addImm(CCMask)
744 .addReg(SystemZ::CC, RegState::Implicit);
745 return true;
746 }
747 if (Opcode == SystemZ::CallJG) {
748 MachineOperand FirstOp = MI.getOperand(0);
749 const uint32_t *RegMask = MI.getOperand(1).getRegMask();
750 MI.removeOperand(1);
751 MI.removeOperand(0);
752 MI.setDesc(get(SystemZ::CallBRCL));
753 MachineInstrBuilder(*MI.getParent()->getParent(), MI)
754 .addImm(CCValid)
755 .addImm(CCMask)
756 .add(FirstOp)
757 .addRegMask(RegMask)
758 .addReg(SystemZ::CC, RegState::Implicit);
759 return true;
760 }
761 if (Opcode == SystemZ::CallBR) {
762 MachineOperand Target = MI.getOperand(0);
763 const uint32_t *RegMask = MI.getOperand(1).getRegMask();
764 MI.removeOperand(1);
765 MI.removeOperand(0);
766 MI.setDesc(get(SystemZ::CallBCR));
767 MachineInstrBuilder(*MI.getParent()->getParent(), MI)
768 .addImm(CCValid).addImm(CCMask)
769 .add(Target)
770 .addRegMask(RegMask)
771 .addReg(SystemZ::CC, RegState::Implicit);
772 return true;
773 }
774 return false;
775}
776
777void SystemZInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
778 MachineBasicBlock::iterator MBBI,
779 const DebugLoc &DL, MCRegister DestReg,
780 MCRegister SrcReg, bool KillSrc) const {
781 // Split 128-bit GPR moves into two 64-bit moves. Add implicit uses of the
782 // super register in case one of the subregs is undefined.
783 // This handles ADDR128 too.
784 if (SystemZ::GR128BitRegClass.contains(DestReg, SrcReg)) {
785 copyPhysReg(MBB, MBBI, DL, RI.getSubReg(DestReg, SystemZ::subreg_h64),
786 RI.getSubReg(SrcReg, SystemZ::subreg_h64), KillSrc);
787 MachineInstrBuilder(*MBB.getParent(), std::prev(MBBI))
788 .addReg(SrcReg, RegState::Implicit);
789 copyPhysReg(MBB, MBBI, DL, RI.getSubReg(DestReg, SystemZ::subreg_l64),
790 RI.getSubReg(SrcReg, SystemZ::subreg_l64), KillSrc);
791 MachineInstrBuilder(*MBB.getParent(), std::prev(MBBI))
792 .addReg(SrcReg, (getKillRegState(KillSrc) | RegState::Implicit));
793 return;
794 }
795
796 if (SystemZ::GRX32BitRegClass.contains(DestReg, SrcReg)) {
797 emitGRX32Move(MBB, MBBI, DL, DestReg, SrcReg, SystemZ::LR, 32, KillSrc,
798 false);
799 return;
800 }
801
802 // Move 128-bit floating-point values between VR128 and FP128.
803 if (SystemZ::VR128BitRegClass.contains(DestReg) &&
804 SystemZ::FP128BitRegClass.contains(SrcReg)) {
805 MCRegister SrcRegHi =
806 RI.getMatchingSuperReg(RI.getSubReg(SrcReg, SystemZ::subreg_h64),
807 SystemZ::subreg_h64, &SystemZ::VR128BitRegClass);
808 MCRegister SrcRegLo =
809 RI.getMatchingSuperReg(RI.getSubReg(SrcReg, SystemZ::subreg_l64),
810 SystemZ::subreg_h64, &SystemZ::VR128BitRegClass);
811
812 BuildMI(MBB, MBBI, DL, get(SystemZ::VMRHG), DestReg)
813 .addReg(SrcRegHi, getKillRegState(KillSrc))
814 .addReg(SrcRegLo, getKillRegState(KillSrc));
815 return;
816 }
817 if (SystemZ::FP128BitRegClass.contains(DestReg) &&
818 SystemZ::VR128BitRegClass.contains(SrcReg)) {
819 MCRegister DestRegHi =
820 RI.getMatchingSuperReg(RI.getSubReg(DestReg, SystemZ::subreg_h64),
821 SystemZ::subreg_h64, &SystemZ::VR128BitRegClass);
822 MCRegister DestRegLo =
823 RI.getMatchingSuperReg(RI.getSubReg(DestReg, SystemZ::subreg_l64),
824 SystemZ::subreg_h64, &SystemZ::VR128BitRegClass);
825
826 if (DestRegHi != SrcReg)
827 copyPhysReg(MBB, MBBI, DL, DestRegHi, SrcReg, false);
828 BuildMI(MBB, MBBI, DL, get(SystemZ::VREPG), DestRegLo)
829 .addReg(SrcReg, getKillRegState(KillSrc)).addImm(1);
830 return;
831 }
832
833 // Move CC value from a GR32.
834 if (DestReg == SystemZ::CC) {
835 unsigned Opcode =
836 SystemZ::GR32BitRegClass.contains(SrcReg) ? SystemZ::TMLH : SystemZ::TMHH;
837 BuildMI(MBB, MBBI, DL, get(Opcode))
838 .addReg(SrcReg, getKillRegState(KillSrc))
839 .addImm(3 << (SystemZ::IPM_CC - 16));
840 return;
841 }
842
843 // Everything else needs only one instruction.
844 unsigned Opcode;
845 if (SystemZ::GR64BitRegClass.contains(DestReg, SrcReg))
846 Opcode = SystemZ::LGR;
847 else if (SystemZ::FP32BitRegClass.contains(DestReg, SrcReg))
848 // For z13 we prefer LDR over LER to avoid partial register dependencies.
849 Opcode = STI.hasVector() ? SystemZ::LDR32 : SystemZ::LER;
850 else if (SystemZ::FP64BitRegClass.contains(DestReg, SrcReg))
851 Opcode = SystemZ::LDR;
852 else if (SystemZ::FP128BitRegClass.contains(DestReg, SrcReg))
853 Opcode = SystemZ::LXR;
854 else if (SystemZ::VR32BitRegClass.contains(DestReg, SrcReg))
855 Opcode = SystemZ::VLR32;
856 else if (SystemZ::VR64BitRegClass.contains(DestReg, SrcReg))
857 Opcode = SystemZ::VLR64;
858 else if (SystemZ::VR128BitRegClass.contains(DestReg, SrcReg))
859 Opcode = SystemZ::VLR;
860 else if (SystemZ::AR32BitRegClass.contains(DestReg, SrcReg))
861 Opcode = SystemZ::CPYA;
862 else
863 llvm_unreachable("Impossible reg-to-reg copy")::llvm::llvm_unreachable_internal("Impossible reg-to-reg copy"
, "llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp", 863)
;
864
865 BuildMI(MBB, MBBI, DL, get(Opcode), DestReg)
866 .addReg(SrcReg, getKillRegState(KillSrc));
867}
868
869void SystemZInstrInfo::storeRegToStackSlot(
870 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg,
871 bool isKill, int FrameIdx, const TargetRegisterClass *RC,
872 const TargetRegisterInfo *TRI) const {
873 DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
874
875 // Callers may expect a single instruction, so keep 128-bit moves
876 // together for now and lower them after register allocation.
877 unsigned LoadOpcode, StoreOpcode;
878 getLoadStoreOpcodes(RC, LoadOpcode, StoreOpcode);
879 addFrameReference(BuildMI(MBB, MBBI, DL, get(StoreOpcode))
880 .addReg(SrcReg, getKillRegState(isKill)),
881 FrameIdx);
882}
883
884void SystemZInstrInfo::loadRegFromStackSlot(
885 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DestReg,
886 int FrameIdx, const TargetRegisterClass *RC,
887 const TargetRegisterInfo *TRI) const {
888 DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
889
890 // Callers may expect a single instruction, so keep 128-bit moves
891 // together for now and lower them after register allocation.
892 unsigned LoadOpcode, StoreOpcode;
893 getLoadStoreOpcodes(RC, LoadOpcode, StoreOpcode);
894 addFrameReference(BuildMI(MBB, MBBI, DL, get(LoadOpcode), DestReg),
895 FrameIdx);
896}
897
898// Return true if MI is a simple load or store with a 12-bit displacement
899// and no index. Flag is SimpleBDXLoad for loads and SimpleBDXStore for stores.
900static bool isSimpleBD12Move(const MachineInstr *MI, unsigned Flag) {
901 const MCInstrDesc &MCID = MI->getDesc();
902 return ((MCID.TSFlags & Flag) &&
903 isUInt<12>(MI->getOperand(2).getImm()) &&
904 MI->getOperand(3).getReg() == 0);
905}
906
907namespace {
908
909struct LogicOp {
910 LogicOp() = default;
911 LogicOp(unsigned regSize, unsigned immLSB, unsigned immSize)
912 : RegSize(regSize), ImmLSB(immLSB), ImmSize(immSize) {}
913
914 explicit operator bool() const { return RegSize; }
915
916 unsigned RegSize = 0;
917 unsigned ImmLSB = 0;
918 unsigned ImmSize = 0;
919};
920
921} // end anonymous namespace
922
923static LogicOp interpretAndImmediate(unsigned Opcode) {
924 switch (Opcode) {
925 case SystemZ::NILMux: return LogicOp(32, 0, 16);
926 case SystemZ::NIHMux: return LogicOp(32, 16, 16);
927 case SystemZ::NILL64: return LogicOp(64, 0, 16);
928 case SystemZ::NILH64: return LogicOp(64, 16, 16);
929 case SystemZ::NIHL64: return LogicOp(64, 32, 16);
930 case SystemZ::NIHH64: return LogicOp(64, 48, 16);
931 case SystemZ::NIFMux: return LogicOp(32, 0, 32);
932 case SystemZ::NILF64: return LogicOp(64, 0, 32);
933 case SystemZ::NIHF64: return LogicOp(64, 32, 32);
934 default: return LogicOp();
935 }
936}
937
938static void transferDeadCC(MachineInstr *OldMI, MachineInstr *NewMI) {
939 if (OldMI->registerDefIsDead(SystemZ::CC)) {
940 MachineOperand *CCDef = NewMI->findRegisterDefOperand(SystemZ::CC);
941 if (CCDef != nullptr)
942 CCDef->setIsDead(true);
943 }
944}
945
946static void transferMIFlag(MachineInstr *OldMI, MachineInstr *NewMI,
947 MachineInstr::MIFlag Flag) {
948 if (OldMI->getFlag(Flag))
949 NewMI->setFlag(Flag);
950}
951
952MachineInstr *
953SystemZInstrInfo::convertToThreeAddress(MachineInstr &MI, LiveVariables *LV,
954 LiveIntervals *LIS) const {
955 MachineBasicBlock *MBB = MI.getParent();
956
957 // Try to convert an AND into an RISBG-type instruction.
958 // TODO: It might be beneficial to select RISBG and shorten to AND instead.
959 if (LogicOp And = interpretAndImmediate(MI.getOpcode())) {
1
Taking true branch
960 uint64_t Imm = MI.getOperand(2).getImm() << And.ImmLSB;
961 // AND IMMEDIATE leaves the other bits of the register unchanged.
962 Imm |= allOnes(And.RegSize) & ~(allOnes(And.ImmSize) << And.ImmLSB);
963 unsigned Start, End;
964 if (isRxSBGMask(Imm, And.RegSize, Start, End)) {
2
Calling 'SystemZInstrInfo::isRxSBGMask'
965 unsigned NewOpcode;
966 if (And.RegSize == 64) {
967 NewOpcode = SystemZ::RISBG;
968 // Prefer RISBGN if available, since it does not clobber CC.
969 if (STI.hasMiscellaneousExtensions())
970 NewOpcode = SystemZ::RISBGN;
971 } else {
972 NewOpcode = SystemZ::RISBMux;
973 Start &= 31;
974 End &= 31;
975 }
976 MachineOperand &Dest = MI.getOperand(0);
977 MachineOperand &Src = MI.getOperand(1);
978 MachineInstrBuilder MIB =
979 BuildMI(*MBB, MI, MI.getDebugLoc(), get(NewOpcode))
980 .add(Dest)
981 .addReg(0)
982 .addReg(Src.getReg(), getKillRegState(Src.isKill()),
983 Src.getSubReg())
984 .addImm(Start)
985 .addImm(End + 128)
986 .addImm(0);
987 if (LV) {
988 unsigned NumOps = MI.getNumOperands();
989 for (unsigned I = 1; I < NumOps; ++I) {
990 MachineOperand &Op = MI.getOperand(I);
991 if (Op.isReg() && Op.isKill())
992 LV->replaceKillInstruction(Op.getReg(), MI, *MIB);
993 }
994 }
995 if (LIS)
996 LIS->ReplaceMachineInstrInMaps(MI, *MIB);
997 transferDeadCC(&MI, MIB);
998 return MIB;
999 }
1000 }
1001 return nullptr;
1002}
1003
1004MachineInstr *SystemZInstrInfo::foldMemoryOperandImpl(
1005 MachineFunction &MF, MachineInstr &MI, ArrayRef<unsigned> Ops,
1006 MachineBasicBlock::iterator InsertPt, int FrameIndex,
1007 LiveIntervals *LIS, VirtRegMap *VRM) const {
1008 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
1009 MachineRegisterInfo &MRI = MF.getRegInfo();
1010 const MachineFrameInfo &MFI = MF.getFrameInfo();
1011 unsigned Size = MFI.getObjectSize(FrameIndex);
1012 unsigned Opcode = MI.getOpcode();
1013
1014 // Check CC liveness if new instruction introduces a dead def of CC.
1015 MCRegUnitIterator CCUnit(MCRegister::from(SystemZ::CC), TRI);
1016 SlotIndex MISlot = SlotIndex();
1017 LiveRange *CCLiveRange = nullptr;
1018 bool CCLiveAtMI = true;
1019 if (LIS) {
1020 MISlot = LIS->getSlotIndexes()->getInstructionIndex(MI).getRegSlot();
1021 CCLiveRange = &LIS->getRegUnit(*CCUnit);
1022 CCLiveAtMI = CCLiveRange->liveAt(MISlot);
1023 }
1024 ++CCUnit;
1025 assert(!CCUnit.isValid() && "CC only has one reg unit.")(static_cast <bool> (!CCUnit.isValid() && "CC only has one reg unit."
) ? void (0) : __assert_fail ("!CCUnit.isValid() && \"CC only has one reg unit.\""
, "llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp", 1025, __extension__
__PRETTY_FUNCTION__))
;
1026
1027 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
1028 if (!CCLiveAtMI && (Opcode == SystemZ::LA || Opcode == SystemZ::LAY) &&
1029 isInt<8>(MI.getOperand(2).getImm()) && !MI.getOperand(3).getReg()) {
1030 // LA(Y) %reg, CONST(%reg) -> AGSI %mem, CONST
1031 MachineInstr *BuiltMI = BuildMI(*InsertPt->getParent(), InsertPt,
1032 MI.getDebugLoc(), get(SystemZ::AGSI))
1033 .addFrameIndex(FrameIndex)
1034 .addImm(0)
1035 .addImm(MI.getOperand(2).getImm());
1036 BuiltMI->findRegisterDefOperand(SystemZ::CC)->setIsDead(true);
1037 CCLiveRange->createDeadDef(MISlot, LIS->getVNInfoAllocator());
1038 return BuiltMI;
1039 }
1040 return nullptr;
1041 }
1042
1043 // All other cases require a single operand.
1044 if (Ops.size() != 1)
1045 return nullptr;
1046
1047 unsigned OpNum = Ops[0];
1048 assert(Size * 8 ==(static_cast <bool> (Size * 8 == TRI->getRegSizeInBits
(*MF.getRegInfo() .getRegClass(MI.getOperand(OpNum).getReg())
) && "Invalid size combination") ? void (0) : __assert_fail
("Size * 8 == TRI->getRegSizeInBits(*MF.getRegInfo() .getRegClass(MI.getOperand(OpNum).getReg())) && \"Invalid size combination\""
, "llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp", 1051, __extension__
__PRETTY_FUNCTION__))
1049 TRI->getRegSizeInBits(*MF.getRegInfo()(static_cast <bool> (Size * 8 == TRI->getRegSizeInBits
(*MF.getRegInfo() .getRegClass(MI.getOperand(OpNum).getReg())
) && "Invalid size combination") ? void (0) : __assert_fail
("Size * 8 == TRI->getRegSizeInBits(*MF.getRegInfo() .getRegClass(MI.getOperand(OpNum).getReg())) && \"Invalid size combination\""
, "llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp", 1051, __extension__
__PRETTY_FUNCTION__))
1050 .getRegClass(MI.getOperand(OpNum).getReg())) &&(static_cast <bool> (Size * 8 == TRI->getRegSizeInBits
(*MF.getRegInfo() .getRegClass(MI.getOperand(OpNum).getReg())
) && "Invalid size combination") ? void (0) : __assert_fail
("Size * 8 == TRI->getRegSizeInBits(*MF.getRegInfo() .getRegClass(MI.getOperand(OpNum).getReg())) && \"Invalid size combination\""
, "llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp", 1051, __extension__
__PRETTY_FUNCTION__))
1051 "Invalid size combination")(static_cast <bool> (Size * 8 == TRI->getRegSizeInBits
(*MF.getRegInfo() .getRegClass(MI.getOperand(OpNum).getReg())
) && "Invalid size combination") ? void (0) : __assert_fail
("Size * 8 == TRI->getRegSizeInBits(*MF.getRegInfo() .getRegClass(MI.getOperand(OpNum).getReg())) && \"Invalid size combination\""
, "llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp", 1051, __extension__
__PRETTY_FUNCTION__))
;
1052
1053 if ((Opcode == SystemZ::AHI || Opcode == SystemZ::AGHI) && OpNum == 0 &&
1054 isInt<8>(MI.getOperand(2).getImm())) {
1055 // A(G)HI %reg, CONST -> A(G)SI %mem, CONST
1056 Opcode = (Opcode == SystemZ::AHI ? SystemZ::ASI : SystemZ::AGSI);
1057 MachineInstr *BuiltMI =
1058 BuildMI(*InsertPt->getParent(), InsertPt, MI.getDebugLoc(), get(Opcode))
1059 .addFrameIndex(FrameIndex)
1060 .addImm(0)
1061 .addImm(MI.getOperand(2).getImm());
1062 transferDeadCC(&MI, BuiltMI);
1063 transferMIFlag(&MI, BuiltMI, MachineInstr::NoSWrap);
1064 return BuiltMI;
1065 }
1066
1067 if ((Opcode == SystemZ::ALFI && OpNum == 0 &&
1068 isInt<8>((int32_t)MI.getOperand(2).getImm())) ||
1069 (Opcode == SystemZ::ALGFI && OpNum == 0 &&
1070 isInt<8>((int64_t)MI.getOperand(2).getImm()))) {
1071 // AL(G)FI %reg, CONST -> AL(G)SI %mem, CONST
1072 Opcode = (Opcode == SystemZ::ALFI ? SystemZ::ALSI : SystemZ::ALGSI);
1073 MachineInstr *BuiltMI =
1074 BuildMI(*InsertPt->getParent(), InsertPt, MI.getDebugLoc(), get(Opcode))
1075 .addFrameIndex(FrameIndex)
1076 .addImm(0)
1077 .addImm((int8_t)MI.getOperand(2).getImm());
1078 transferDeadCC(&MI, BuiltMI);
1079 return BuiltMI;
1080 }
1081
1082 if ((Opcode == SystemZ::SLFI && OpNum == 0 &&
1083 isInt<8>((int32_t)-MI.getOperand(2).getImm())) ||
1084 (Opcode == SystemZ::SLGFI && OpNum == 0 &&
1085 isInt<8>((int64_t)-MI.getOperand(2).getImm()))) {
1086 // SL(G)FI %reg, CONST -> AL(G)SI %mem, -CONST
1087 Opcode = (Opcode == SystemZ::SLFI ? SystemZ::ALSI : SystemZ::ALGSI);
1088 MachineInstr *BuiltMI =
1089 BuildMI(*InsertPt->getParent(), InsertPt, MI.getDebugLoc(), get(Opcode))
1090 .addFrameIndex(FrameIndex)
1091 .addImm(0)
1092 .addImm((int8_t)-MI.getOperand(2).getImm());
1093 transferDeadCC(&MI, BuiltMI);
1094 return BuiltMI;
1095 }
1096
1097 unsigned MemImmOpc = 0;
1098 switch (Opcode) {
1099 case SystemZ::LHIMux:
1100 case SystemZ::LHI: MemImmOpc = SystemZ::MVHI; break;
1101 case SystemZ::LGHI: MemImmOpc = SystemZ::MVGHI; break;
1102 case SystemZ::CHIMux:
1103 case SystemZ::CHI: MemImmOpc = SystemZ::CHSI; break;
1104 case SystemZ::CGHI: MemImmOpc = SystemZ::CGHSI; break;
1105 case SystemZ::CLFIMux:
1106 case SystemZ::CLFI:
1107 if (isUInt<16>(MI.getOperand(1).getImm()))
1108 MemImmOpc = SystemZ::CLFHSI;
1109 break;
1110 case SystemZ::CLGFI:
1111 if (isUInt<16>(MI.getOperand(1).getImm()))
1112 MemImmOpc = SystemZ::CLGHSI;
1113 break;
1114 default: break;
1115 }
1116 if (MemImmOpc)
1117 return BuildMI(*InsertPt->getParent(), InsertPt, MI.getDebugLoc(),
1118 get(MemImmOpc))
1119 .addFrameIndex(FrameIndex)
1120 .addImm(0)
1121 .addImm(MI.getOperand(1).getImm());
1122
1123 if (Opcode == SystemZ::LGDR || Opcode == SystemZ::LDGR) {
1124 bool Op0IsGPR = (Opcode == SystemZ::LGDR);
1125 bool Op1IsGPR = (Opcode == SystemZ::LDGR);
1126 // If we're spilling the destination of an LDGR or LGDR, store the
1127 // source register instead.
1128 if (OpNum == 0) {
1129 unsigned StoreOpcode = Op1IsGPR ? SystemZ::STG : SystemZ::STD;
1130 return BuildMI(*InsertPt->getParent(), InsertPt, MI.getDebugLoc(),
1131 get(StoreOpcode))
1132 .add(MI.getOperand(1))
1133 .addFrameIndex(FrameIndex)
1134 .addImm(0)
1135 .addReg(0);
1136 }
1137 // If we're spilling the source of an LDGR or LGDR, load the
1138 // destination register instead.
1139 if (OpNum == 1) {
1140 unsigned LoadOpcode = Op0IsGPR ? SystemZ::LG : SystemZ::LD;
1141 return BuildMI(*InsertPt->getParent(), InsertPt, MI.getDebugLoc(),
1142 get(LoadOpcode))
1143 .add(MI.getOperand(0))
1144 .addFrameIndex(FrameIndex)
1145 .addImm(0)
1146 .addReg(0);
1147 }
1148 }
1149
1150 // Look for cases where the source of a simple store or the destination
1151 // of a simple load is being spilled. Try to use MVC instead.
1152 //
1153 // Although MVC is in practice a fast choice in these cases, it is still
1154 // logically a bytewise copy. This means that we cannot use it if the
1155 // load or store is volatile. We also wouldn't be able to use MVC if
1156 // the two memories partially overlap, but that case cannot occur here,
1157 // because we know that one of the memories is a full frame index.
1158 //
1159 // For performance reasons, we also want to avoid using MVC if the addresses
1160 // might be equal. We don't worry about that case here, because spill slot
1161 // coloring happens later, and because we have special code to remove
1162 // MVCs that turn out to be redundant.
1163 if (OpNum == 0 && MI.hasOneMemOperand()) {
1164 MachineMemOperand *MMO = *MI.memoperands_begin();
1165 if (MMO->getSize() == Size && !MMO->isVolatile() && !MMO->isAtomic()) {
1166 // Handle conversion of loads.
1167 if (isSimpleBD12Move(&MI, SystemZII::SimpleBDXLoad)) {
1168 return BuildMI(*InsertPt->getParent(), InsertPt, MI.getDebugLoc(),
1169 get(SystemZ::MVC))
1170 .addFrameIndex(FrameIndex)
1171 .addImm(0)
1172 .addImm(Size)
1173 .add(MI.getOperand(1))
1174 .addImm(MI.getOperand(2).getImm())
1175 .addMemOperand(MMO);
1176 }
1177 // Handle conversion of stores.
1178 if (isSimpleBD12Move(&MI, SystemZII::SimpleBDXStore)) {
1179 return BuildMI(*InsertPt->getParent(), InsertPt, MI.getDebugLoc(),
1180 get(SystemZ::MVC))
1181 .add(MI.getOperand(1))
1182 .addImm(MI.getOperand(2).getImm())
1183 .addImm(Size)
1184 .addFrameIndex(FrameIndex)
1185 .addImm(0)
1186 .addMemOperand(MMO);
1187 }
1188 }
1189 }
1190
1191 // If the spilled operand is the final one or the instruction is
1192 // commutable, try to change <INSN>R into <INSN>. Don't introduce a def of
1193 // CC if it is live and MI does not define it.
1194 unsigned NumOps = MI.getNumExplicitOperands();
1195 int MemOpcode = SystemZ::getMemOpcode(Opcode);
1196 if (MemOpcode == -1 ||
1197 (CCLiveAtMI && !MI.definesRegister(SystemZ::CC) &&
1198 get(MemOpcode).hasImplicitDefOfPhysReg(SystemZ::CC)))
1199 return nullptr;
1200
1201 // Check if all other vregs have a usable allocation in the case of vector
1202 // to FP conversion.
1203 const MCInstrDesc &MCID = MI.getDesc();
1204 for (unsigned I = 0, E = MCID.getNumOperands(); I != E; ++I) {
1205 const MCOperandInfo &MCOI = MCID.OpInfo[I];
1206 if (MCOI.OperandType != MCOI::OPERAND_REGISTER || I == OpNum)
1207 continue;
1208 const TargetRegisterClass *RC = TRI->getRegClass(MCOI.RegClass);
1209 if (RC == &SystemZ::VR32BitRegClass || RC == &SystemZ::VR64BitRegClass) {
1210 Register Reg = MI.getOperand(I).getReg();
1211 Register PhysReg = Register::isVirtualRegister(Reg)
1212 ? (VRM ? Register(VRM->getPhys(Reg)) : Register())
1213 : Reg;
1214 if (!PhysReg ||
1215 !(SystemZ::FP32BitRegClass.contains(PhysReg) ||
1216 SystemZ::FP64BitRegClass.contains(PhysReg) ||
1217 SystemZ::VF128BitRegClass.contains(PhysReg)))
1218 return nullptr;
1219 }
1220 }
1221 // Fused multiply and add/sub need to have the same dst and accumulator reg.
1222 bool FusedFPOp = (Opcode == SystemZ::WFMADB || Opcode == SystemZ::WFMASB ||
1223 Opcode == SystemZ::WFMSDB || Opcode == SystemZ::WFMSSB);
1224 if (FusedFPOp) {
1225 Register DstReg = VRM->getPhys(MI.getOperand(0).getReg());
1226 Register AccReg = VRM->getPhys(MI.getOperand(3).getReg());
1227 if (OpNum == 0 || OpNum == 3 || DstReg != AccReg)
1228 return nullptr;
1229 }
1230
1231 // Try to swap compare operands if possible.
1232 bool NeedsCommute = false;
1233 if ((MI.getOpcode() == SystemZ::CR || MI.getOpcode() == SystemZ::CGR ||
1234 MI.getOpcode() == SystemZ::CLR || MI.getOpcode() == SystemZ::CLGR ||
1235 MI.getOpcode() == SystemZ::WFCDB || MI.getOpcode() == SystemZ::WFCSB ||
1236 MI.getOpcode() == SystemZ::WFKDB || MI.getOpcode() == SystemZ::WFKSB) &&
1237 OpNum == 0 && prepareCompareSwapOperands(MI))
1238 NeedsCommute = true;
1239
1240 bool CCOperands = false;
1241 if (MI.getOpcode() == SystemZ::LOCRMux || MI.getOpcode() == SystemZ::LOCGR ||
1242 MI.getOpcode() == SystemZ::SELRMux || MI.getOpcode() == SystemZ::SELGR) {
1243 assert(MI.getNumOperands() == 6 && NumOps == 5 &&(static_cast <bool> (MI.getNumOperands() == 6 &&
NumOps == 5 && "LOCR/SELR instruction operands corrupt?"
) ? void (0) : __assert_fail ("MI.getNumOperands() == 6 && NumOps == 5 && \"LOCR/SELR instruction operands corrupt?\""
, "llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp", 1244, __extension__
__PRETTY_FUNCTION__))
1244 "LOCR/SELR instruction operands corrupt?")(static_cast <bool> (MI.getNumOperands() == 6 &&
NumOps == 5 && "LOCR/SELR instruction operands corrupt?"
) ? void (0) : __assert_fail ("MI.getNumOperands() == 6 && NumOps == 5 && \"LOCR/SELR instruction operands corrupt?\""
, "llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp", 1244, __extension__
__PRETTY_FUNCTION__))
;
1245 NumOps -= 2;
1246 CCOperands = true;
1247 }
1248
1249 // See if this is a 3-address instruction that is convertible to 2-address
1250 // and suitable for folding below. Only try this with virtual registers
1251 // and a provided VRM (during regalloc).
1252 if (NumOps == 3 && SystemZ::getTargetMemOpcode(MemOpcode) != -1) {
1253 if (VRM == nullptr)
1254 return nullptr;
1255 else {
1256 Register DstReg = MI.getOperand(0).getReg();
1257 Register DstPhys =
1258 (Register::isVirtualRegister(DstReg) ? Register(VRM->getPhys(DstReg))
1259 : DstReg);
1260 Register SrcReg = (OpNum == 2 ? MI.getOperand(1).getReg()
1261 : ((OpNum == 1 && MI.isCommutable())
1262 ? MI.getOperand(2).getReg()
1263 : Register()));
1264 if (DstPhys && !SystemZ::GRH32BitRegClass.contains(DstPhys) && SrcReg &&
1265 Register::isVirtualRegister(SrcReg) &&
1266 DstPhys == VRM->getPhys(SrcReg))
1267 NeedsCommute = (OpNum == 1);
1268 else
1269 return nullptr;
1270 }
1271 }
1272
1273 if ((OpNum == NumOps - 1) || NeedsCommute || FusedFPOp) {
1274 const MCInstrDesc &MemDesc = get(MemOpcode);
1275 uint64_t AccessBytes = SystemZII::getAccessSize(MemDesc.TSFlags);
1276 assert(AccessBytes != 0 && "Size of access should be known")(static_cast <bool> (AccessBytes != 0 && "Size of access should be known"
) ? void (0) : __assert_fail ("AccessBytes != 0 && \"Size of access should be known\""
, "llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp", 1276, __extension__
__PRETTY_FUNCTION__))
;
1277 assert(AccessBytes <= Size && "Access outside the frame index")(static_cast <bool> (AccessBytes <= Size && "Access outside the frame index"
) ? void (0) : __assert_fail ("AccessBytes <= Size && \"Access outside the frame index\""
, "llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp", 1277, __extension__
__PRETTY_FUNCTION__))
;
1278 uint64_t Offset = Size - AccessBytes;
1279 MachineInstrBuilder MIB = BuildMI(*InsertPt->getParent(), InsertPt,
1280 MI.getDebugLoc(), get(MemOpcode));
1281 if (MI.isCompare()) {
1282 assert(NumOps == 2 && "Expected 2 register operands for a compare.")(static_cast <bool> (NumOps == 2 && "Expected 2 register operands for a compare."
) ? void (0) : __assert_fail ("NumOps == 2 && \"Expected 2 register operands for a compare.\""
, "llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp", 1282, __extension__
__PRETTY_FUNCTION__))
;
1283 MIB.add(MI.getOperand(NeedsCommute ? 1 : 0));
1284 }
1285 else if (FusedFPOp) {
1286 MIB.add(MI.getOperand(0));
1287 MIB.add(MI.getOperand(3));
1288 MIB.add(MI.getOperand(OpNum == 1 ? 2 : 1));
1289 }
1290 else {
1291 MIB.add(MI.getOperand(0));
1292 if (NeedsCommute)
1293 MIB.add(MI.getOperand(2));
1294 else
1295 for (unsigned I = 1; I < OpNum; ++I)
1296 MIB.add(MI.getOperand(I));
1297 }
1298 MIB.addFrameIndex(FrameIndex).addImm(Offset);
1299 if (MemDesc.TSFlags & SystemZII::HasIndex)
1300 MIB.addReg(0);
1301 if (CCOperands) {
1302 unsigned CCValid = MI.getOperand(NumOps).getImm();
1303 unsigned CCMask = MI.getOperand(NumOps + 1).getImm();
1304 MIB.addImm(CCValid);
1305 MIB.addImm(NeedsCommute ? CCMask ^ CCValid : CCMask);
1306 }
1307 if (MIB->definesRegister(SystemZ::CC) &&
1308 (!MI.definesRegister(SystemZ::CC) ||
1309 MI.registerDefIsDead(SystemZ::CC))) {
1310 MIB->addRegisterDead(SystemZ::CC, TRI);
1311 if (CCLiveRange)
1312 CCLiveRange->createDeadDef(MISlot, LIS->getVNInfoAllocator());
1313 }
1314 // Constrain the register classes if converted from a vector opcode. The
1315 // allocated regs are in an FP reg-class per previous check above.
1316 for (const MachineOperand &MO : MIB->operands())
1317 if (MO.isReg() && Register::isVirtualRegister(MO.getReg())) {
1318 Register Reg = MO.getReg();
1319 if (MRI.getRegClass(Reg) == &SystemZ::VR32BitRegClass)
1320 MRI.setRegClass(Reg, &SystemZ::FP32BitRegClass);
1321 else if (MRI.getRegClass(Reg) == &SystemZ::VR64BitRegClass)
1322 MRI.setRegClass(Reg, &SystemZ::FP64BitRegClass);
1323 else if (MRI.getRegClass(Reg) == &SystemZ::VR128BitRegClass)
1324 MRI.setRegClass(Reg, &SystemZ::VF128BitRegClass);
1325 }
1326
1327 transferDeadCC(&MI, MIB);
1328 transferMIFlag(&MI, MIB, MachineInstr::NoSWrap);
1329 transferMIFlag(&MI, MIB, MachineInstr::NoFPExcept);
1330 return MIB;
1331 }
1332
1333 return nullptr;
1334}
1335
1336MachineInstr *SystemZInstrInfo::foldMemoryOperandImpl(
1337 MachineFunction &MF, MachineInstr &MI, ArrayRef<unsigned> Ops,
1338 MachineBasicBlock::iterator InsertPt, MachineInstr &LoadMI,
1339 LiveIntervals *LIS) const {
1340 return nullptr;
1341}
1342
1343bool SystemZInstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
1344 switch (MI.getOpcode()) {
1345 case SystemZ::L128:
1346 splitMove(MI, SystemZ::LG);
1347 return true;
1348
1349 case SystemZ::ST128:
1350 splitMove(MI, SystemZ::STG);
1351 return true;
1352
1353 case SystemZ::LX:
1354 splitMove(MI, SystemZ::LD);
1355 return true;
1356
1357 case SystemZ::STX:
1358 splitMove(MI, SystemZ::STD);
1359 return true;
1360
1361 case SystemZ::LBMux:
1362 expandRXYPseudo(MI, SystemZ::LB, SystemZ::LBH);
1363 return true;
1364
1365 case SystemZ::LHMux:
1366 expandRXYPseudo(MI, SystemZ::LH, SystemZ::LHH);
1367 return true;
1368
1369 case SystemZ::LLCRMux:
1370 expandZExtPseudo(MI, SystemZ::LLCR, 8);
1371 return true;
1372
1373 case SystemZ::LLHRMux:
1374 expandZExtPseudo(MI, SystemZ::LLHR, 16);
1375 return true;
1376
1377 case SystemZ::LLCMux:
1378 expandRXYPseudo(MI, SystemZ::LLC, SystemZ::LLCH);
1379 return true;
1380
1381 case SystemZ::LLHMux:
1382 expandRXYPseudo(MI, SystemZ::LLH, SystemZ::LLHH);
1383 return true;
1384
1385 case SystemZ::LMux:
1386 expandRXYPseudo(MI, SystemZ::L, SystemZ::LFH);
1387 return true;
1388
1389 case SystemZ::LOCMux:
1390 expandLOCPseudo(MI, SystemZ::LOC, SystemZ::LOCFH);
1391 return true;
1392
1393 case SystemZ::LOCHIMux:
1394 expandLOCPseudo(MI, SystemZ::LOCHI, SystemZ::LOCHHI);
1395 return true;
1396
1397 case SystemZ::STCMux:
1398 expandRXYPseudo(MI, SystemZ::STC, SystemZ::STCH);
1399 return true;
1400
1401 case SystemZ::STHMux:
1402 expandRXYPseudo(MI, SystemZ::STH, SystemZ::STHH);
1403 return true;
1404
1405 case SystemZ::STMux:
1406 expandRXYPseudo(MI, SystemZ::ST, SystemZ::STFH);
1407 return true;
1408
1409 case SystemZ::STOCMux:
1410 expandLOCPseudo(MI, SystemZ::STOC, SystemZ::STOCFH);
1411 return true;
1412
1413 case SystemZ::LHIMux:
1414 expandRIPseudo(MI, SystemZ::LHI, SystemZ::IIHF, true);
1415 return true;
1416
1417 case SystemZ::IIFMux:
1418 expandRIPseudo(MI, SystemZ::IILF, SystemZ::IIHF, false);
1419 return true;
1420
1421 case SystemZ::IILMux:
1422 expandRIPseudo(MI, SystemZ::IILL, SystemZ::IIHL, false);
1423 return true;
1424
1425 case SystemZ::IIHMux:
1426 expandRIPseudo(MI, SystemZ::IILH, SystemZ::IIHH, false);
1427 return true;
1428
1429 case SystemZ::NIFMux:
1430 expandRIPseudo(MI, SystemZ::NILF, SystemZ::NIHF, false);
1431 return true;
1432
1433 case SystemZ::NILMux:
1434 expandRIPseudo(MI, SystemZ::NILL, SystemZ::NIHL, false);
1435 return true;
1436
1437 case SystemZ::NIHMux:
1438 expandRIPseudo(MI, SystemZ::NILH, SystemZ::NIHH, false);
1439 return true;
1440
1441 case SystemZ::OIFMux:
1442 expandRIPseudo(MI, SystemZ::OILF, SystemZ::OIHF, false);
1443 return true;
1444
1445 case SystemZ::OILMux:
1446 expandRIPseudo(MI, SystemZ::OILL, SystemZ::OIHL, false);
1447 return true;
1448
1449 case SystemZ::OIHMux:
1450 expandRIPseudo(MI, SystemZ::OILH, SystemZ::OIHH, false);
1451 return true;
1452
1453 case SystemZ::XIFMux:
1454 expandRIPseudo(MI, SystemZ::XILF, SystemZ::XIHF, false);
1455 return true;
1456
1457 case SystemZ::TMLMux:
1458 expandRIPseudo(MI, SystemZ::TMLL, SystemZ::TMHL, false);
1459 return true;
1460
1461 case SystemZ::TMHMux:
1462 expandRIPseudo(MI, SystemZ::TMLH, SystemZ::TMHH, false);
1463 return true;
1464
1465 case SystemZ::AHIMux:
1466 expandRIPseudo(MI, SystemZ::AHI, SystemZ::AIH, false);
1467 return true;
1468
1469 case SystemZ::AHIMuxK:
1470 expandRIEPseudo(MI, SystemZ::AHI, SystemZ::AHIK, SystemZ::AIH);
1471 return true;
1472
1473 case SystemZ::AFIMux:
1474 expandRIPseudo(MI, SystemZ::AFI, SystemZ::AIH, false);
1475 return true;
1476
1477 case SystemZ::CHIMux:
1478 expandRIPseudo(MI, SystemZ::CHI, SystemZ::CIH, false);
1479 return true;
1480
1481 case SystemZ::CFIMux:
1482 expandRIPseudo(MI, SystemZ::CFI, SystemZ::CIH, false);
1483 return true;
1484
1485 case SystemZ::CLFIMux:
1486 expandRIPseudo(MI, SystemZ::CLFI, SystemZ::CLIH, false);
1487 return true;
1488
1489 case SystemZ::CMux:
1490 expandRXYPseudo(MI, SystemZ::C, SystemZ::CHF);
1491 return true;
1492
1493 case SystemZ::CLMux:
1494 expandRXYPseudo(MI, SystemZ::CL, SystemZ::CLHF);
1495 return true;
1496
1497 case SystemZ::RISBMux: {
1498 bool DestIsHigh = SystemZ::isHighReg(MI.getOperand(0).getReg());
1499 bool SrcIsHigh = SystemZ::isHighReg(MI.getOperand(2).getReg());
1500 if (SrcIsHigh == DestIsHigh)
1501 MI.setDesc(get(DestIsHigh ? SystemZ::RISBHH : SystemZ::RISBLL));
1502 else {
1503 MI.setDesc(get(DestIsHigh ? SystemZ::RISBHL : SystemZ::RISBLH));
1504 MI.getOperand(5).setImm(MI.getOperand(5).getImm() ^ 32);
1505 }
1506 return true;
1507 }
1508
1509 case SystemZ::ADJDYNALLOC:
1510 splitAdjDynAlloc(MI);
1511 return true;
1512
1513 case TargetOpcode::LOAD_STACK_GUARD:
1514 expandLoadStackGuard(&MI);
1515 return true;
1516
1517 default:
1518 return false;
1519 }
1520}
1521
1522unsigned SystemZInstrInfo::getInstSizeInBytes(const MachineInstr &MI) const {
1523 if (MI.isInlineAsm()) {
1524 const MachineFunction *MF = MI.getParent()->getParent();
1525 const char *AsmStr = MI.getOperand(0).getSymbolName();
1526 return getInlineAsmLength(AsmStr, *MF->getTarget().getMCAsmInfo());
1527 }
1528 else if (MI.getOpcode() == SystemZ::PATCHPOINT)
1529 return PatchPointOpers(&MI).getNumPatchBytes();
1530 else if (MI.getOpcode() == SystemZ::STACKMAP)
1531 return MI.getOperand(1).getImm();
1532 else if (MI.getOpcode() == SystemZ::FENTRY_CALL)
1533 return 6;
1534
1535 return MI.getDesc().getSize();
1536}
1537
1538SystemZII::Branch
1539SystemZInstrInfo::getBranchInfo(const MachineInstr &MI) const {
1540 switch (MI.getOpcode()) {
1541 case SystemZ::BR:
1542 case SystemZ::BI:
1543 case SystemZ::J:
1544 case SystemZ::JG:
1545 return SystemZII::Branch(SystemZII::BranchNormal, SystemZ::CCMASK_ANY,
1546 SystemZ::CCMASK_ANY, &MI.getOperand(0));
1547
1548 case SystemZ::BRC:
1549 case SystemZ::BRCL:
1550 return SystemZII::Branch(SystemZII::BranchNormal, MI.getOperand(0).getImm(),
1551 MI.getOperand(1).getImm(), &MI.getOperand(2));
1552
1553 case SystemZ::BRCT:
1554 case SystemZ::BRCTH:
1555 return SystemZII::Branch(SystemZII::BranchCT, SystemZ::CCMASK_ICMP,
1556 SystemZ::CCMASK_CMP_NE, &MI.getOperand(2));
1557
1558 case SystemZ::BRCTG:
1559 return SystemZII::Branch(SystemZII::BranchCTG, SystemZ::CCMASK_ICMP,
1560 SystemZ::CCMASK_CMP_NE, &MI.getOperand(2));
1561
1562 case SystemZ::CIJ:
1563 case SystemZ::CRJ:
1564 return SystemZII::Branch(SystemZII::BranchC, SystemZ::CCMASK_ICMP,
1565 MI.getOperand(2).getImm(), &MI.getOperand(3));
1566
1567 case SystemZ::CLIJ:
1568 case SystemZ::CLRJ:
1569 return SystemZII::Branch(SystemZII::BranchCL, SystemZ::CCMASK_ICMP,
1570 MI.getOperand(2).getImm(), &MI.getOperand(3));
1571
1572 case SystemZ::CGIJ:
1573 case SystemZ::CGRJ:
1574 return SystemZII::Branch(SystemZII::BranchCG, SystemZ::CCMASK_ICMP,
1575 MI.getOperand(2).getImm(), &MI.getOperand(3));
1576
1577 case SystemZ::CLGIJ:
1578 case SystemZ::CLGRJ:
1579 return SystemZII::Branch(SystemZII::BranchCLG, SystemZ::CCMASK_ICMP,
1580 MI.getOperand(2).getImm(), &MI.getOperand(3));
1581
1582 case SystemZ::INLINEASM_BR:
1583 // Don't try to analyze asm goto, so pass nullptr as branch target argument.
1584 return SystemZII::Branch(SystemZII::AsmGoto, 0, 0, nullptr);
1585
1586 default:
1587 llvm_unreachable("Unrecognized branch opcode")::llvm::llvm_unreachable_internal("Unrecognized branch opcode"
, "llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp", 1587)
;
1588 }
1589}
1590
1591void SystemZInstrInfo::getLoadStoreOpcodes(const TargetRegisterClass *RC,
1592 unsigned &LoadOpcode,
1593 unsigned &StoreOpcode) const {
1594 if (RC == &SystemZ::GR32BitRegClass || RC == &SystemZ::ADDR32BitRegClass) {
1595 LoadOpcode = SystemZ::L;
1596 StoreOpcode = SystemZ::ST;
1597 } else if (RC == &SystemZ::GRH32BitRegClass) {
1598 LoadOpcode = SystemZ::LFH;
1599 StoreOpcode = SystemZ::STFH;
1600 } else if (RC == &SystemZ::GRX32BitRegClass) {
1601 LoadOpcode = SystemZ::LMux;
1602 StoreOpcode = SystemZ::STMux;
1603 } else if (RC == &SystemZ::GR64BitRegClass ||
1604 RC == &SystemZ::ADDR64BitRegClass) {
1605 LoadOpcode = SystemZ::LG;
1606 StoreOpcode = SystemZ::STG;
1607 } else if (RC == &SystemZ::GR128BitRegClass ||
1608 RC == &SystemZ::ADDR128BitRegClass) {
1609 LoadOpcode = SystemZ::L128;
1610 StoreOpcode = SystemZ::ST128;
1611 } else if (RC == &SystemZ::FP32BitRegClass) {
1612 LoadOpcode = SystemZ::LE;
1613 StoreOpcode = SystemZ::STE;
1614 } else if (RC == &SystemZ::FP64BitRegClass) {
1615 LoadOpcode = SystemZ::LD;
1616 StoreOpcode = SystemZ::STD;
1617 } else if (RC == &SystemZ::FP128BitRegClass) {
1618 LoadOpcode = SystemZ::LX;
1619 StoreOpcode = SystemZ::STX;
1620 } else if (RC == &SystemZ::VR32BitRegClass) {
1621 LoadOpcode = SystemZ::VL32;
1622 StoreOpcode = SystemZ::VST32;
1623 } else if (RC == &SystemZ::VR64BitRegClass) {
1624 LoadOpcode = SystemZ::VL64;
1625 StoreOpcode = SystemZ::VST64;
1626 } else if (RC == &SystemZ::VF128BitRegClass ||
1627 RC == &SystemZ::VR128BitRegClass) {
1628 LoadOpcode = SystemZ::VL;
1629 StoreOpcode = SystemZ::VST;
1630 } else
1631 llvm_unreachable("Unsupported regclass to load or store")::llvm::llvm_unreachable_internal("Unsupported regclass to load or store"
, "llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp", 1631)
;
1632}
1633
1634unsigned SystemZInstrInfo::getOpcodeForOffset(unsigned Opcode,
1635 int64_t Offset,
1636 const MachineInstr *MI) const {
1637 const MCInstrDesc &MCID = get(Opcode);
1638 int64_t Offset2 = (MCID.TSFlags & SystemZII::Is128Bit ? Offset + 8 : Offset);
1639 if (isUInt<12>(Offset) && isUInt<12>(Offset2)) {
1640 // Get the instruction to use for unsigned 12-bit displacements.
1641 int Disp12Opcode = SystemZ::getDisp12Opcode(Opcode);
1642 if (Disp12Opcode >= 0)
1643 return Disp12Opcode;
1644
1645 // All address-related instructions can use unsigned 12-bit
1646 // displacements.
1647 return Opcode;
1648 }
1649 if (isInt<20>(Offset) && isInt<20>(Offset2)) {
1650 // Get the instruction to use for signed 20-bit displacements.
1651 int Disp20Opcode = SystemZ::getDisp20Opcode(Opcode);
1652 if (Disp20Opcode >= 0)
1653 return Disp20Opcode;
1654
1655 // Check whether Opcode allows signed 20-bit displacements.
1656 if (MCID.TSFlags & SystemZII::Has20BitOffset)
1657 return Opcode;
1658
1659 // If a VR32/VR64 reg ended up in an FP register, use the FP opcode.
1660 if (MI && MI->getOperand(0).isReg()) {
1661 Register Reg = MI->getOperand(0).getReg();
1662 if (Reg.isPhysical() && SystemZMC::getFirstReg(Reg) < 16) {
1663 switch (Opcode) {
1664 case SystemZ::VL32:
1665 return SystemZ::LEY;
1666 case SystemZ::VST32:
1667 return SystemZ::STEY;
1668 case SystemZ::VL64:
1669 return SystemZ::LDY;
1670 case SystemZ::VST64:
1671 return SystemZ::STDY;
1672 default: break;
1673 }
1674 }
1675 }
1676 }
1677 return 0;
1678}
1679
1680bool SystemZInstrInfo::hasDisplacementPairInsn(unsigned Opcode) const {
1681 const MCInstrDesc &MCID = get(Opcode);
1682 if (MCID.TSFlags & SystemZII::Has20BitOffset)
1683 return SystemZ::getDisp12Opcode(Opcode) >= 0;
1684 return SystemZ::getDisp20Opcode(Opcode) >= 0;
1685}
1686
1687unsigned SystemZInstrInfo::getLoadAndTest(unsigned Opcode) const {
1688 switch (Opcode) {
1689 case SystemZ::L: return SystemZ::LT;
1690 case SystemZ::LY: return SystemZ::LT;
1691 case SystemZ::LG: return SystemZ::LTG;
1692 case SystemZ::LGF: return SystemZ::LTGF;
1693 case SystemZ::LR: return SystemZ::LTR;
1694 case SystemZ::LGFR: return SystemZ::LTGFR;
1695 case SystemZ::LGR: return SystemZ::LTGR;
1696 case SystemZ::LER: return SystemZ::LTEBR;
1697 case SystemZ::LDR: return SystemZ::LTDBR;
1698 case SystemZ::LXR: return SystemZ::LTXBR;
1699 case SystemZ::LCDFR: return SystemZ::LCDBR;
1700 case SystemZ::LPDFR: return SystemZ::LPDBR;
1701 case SystemZ::LNDFR: return SystemZ::LNDBR;
1702 case SystemZ::LCDFR_32: return SystemZ::LCEBR;
1703 case SystemZ::LPDFR_32: return SystemZ::LPEBR;
1704 case SystemZ::LNDFR_32: return SystemZ::LNEBR;
1705 // On zEC12 we prefer to use RISBGN. But if there is a chance to
1706 // actually use the condition code, we may turn it back into RISGB.
1707 // Note that RISBG is not really a "load-and-test" instruction,
1708 // but sets the same condition code values, so is OK to use here.
1709 case SystemZ::RISBGN: return SystemZ::RISBG;
1710 default: return 0;
1711 }
1712}
1713
1714// Return true if Mask matches the regexp 0*1+0*, given that zero masks
1715// have already been filtered out. Store the first set bit in LSB and
1716// the number of set bits in Length if so.
1717static bool isStringOfOnes(uint64_t Mask, unsigned &LSB, unsigned &Length) {
1718 unsigned First = findFirstSet(Mask);
7
Calling 'findFirstSet<unsigned long>'
14
Returning from 'findFirstSet<unsigned long>'
15
'First' initialized to 4294967295
1719 uint64_t Top = (Mask >> First) + 1;
16
The result of the right shift is undefined due to shifting by '4294967295', which is greater or equal to the width of type 'uint64_t'
1720 if ((Top & -Top) == Top) {
1721 LSB = First;
1722 Length = findFirstSet(Top);
1723 return true;
1724 }
1725 return false;
1726}
1727
1728bool SystemZInstrInfo::isRxSBGMask(uint64_t Mask, unsigned BitSize,
1729 unsigned &Start, unsigned &End) const {
1730 // Reject trivial all-zero masks.
1731 Mask &= allOnes(BitSize);
1732 if (Mask == 0)
3
Assuming 'Mask' is not equal to 0
4
Taking false branch
1733 return false;
1734
1735 // Handle the 1+0+ or 0+1+0* cases. Start then specifies the index of
1736 // the msb and End specifies the index of the lsb.
1737 unsigned LSB, Length;
1738 if (isStringOfOnes(Mask, LSB, Length)) {
5
Taking false branch
1739 Start = 63 - (LSB + Length - 1);
1740 End = 63 - LSB;
1741 return true;
1742 }
1743
1744 // Handle the wrap-around 1+0+1+ cases. Start then specifies the msb
1745 // of the low 1s and End specifies the lsb of the high 1s.
1746 if (isStringOfOnes(Mask ^ allOnes(BitSize), LSB, Length)) {
6
Calling 'isStringOfOnes'
1747 assert(LSB > 0 && "Bottom bit must be set")(static_cast <bool> (LSB > 0 && "Bottom bit must be set"
) ? void (0) : __assert_fail ("LSB > 0 && \"Bottom bit must be set\""
, "llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp", 1747, __extension__
__PRETTY_FUNCTION__))
;
1748 assert(LSB + Length < BitSize && "Top bit must be set")(static_cast <bool> (LSB + Length < BitSize &&
"Top bit must be set") ? void (0) : __assert_fail ("LSB + Length < BitSize && \"Top bit must be set\""
, "llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp", 1748, __extension__
__PRETTY_FUNCTION__))
;
1749 Start = 63 - (LSB - 1);
1750 End = 63 - (LSB + Length);
1751 return true;
1752 }
1753
1754 return false;
1755}
1756
1757unsigned SystemZInstrInfo::getFusedCompare(unsigned Opcode,
1758 SystemZII::FusedCompareType Type,
1759 const MachineInstr *MI) const {
1760 switch (Opcode) {
1761 case SystemZ::CHI:
1762 case SystemZ::CGHI:
1763 if (!(MI && isInt<8>(MI->getOperand(1).getImm())))
1764 return 0;
1765 break;
1766 case SystemZ::CLFI:
1767 case SystemZ::CLGFI:
1768 if (!(MI && isUInt<8>(MI->getOperand(1).getImm())))
1769 return 0;
1770 break;
1771 case SystemZ::CL:
1772 case SystemZ::CLG:
1773 if (!STI.hasMiscellaneousExtensions())
1774 return 0;
1775 if (!(MI && MI->getOperand(3).getReg() == 0))
1776 return 0;
1777 break;
1778 }
1779 switch (Type) {
1780 case SystemZII::CompareAndBranch:
1781 switch (Opcode) {
1782 case SystemZ::CR:
1783 return SystemZ::CRJ;
1784 case SystemZ::CGR:
1785 return SystemZ::CGRJ;
1786 case SystemZ::CHI:
1787 return SystemZ::CIJ;
1788 case SystemZ::CGHI:
1789 return SystemZ::CGIJ;
1790 case SystemZ::CLR:
1791 return SystemZ::CLRJ;
1792 case SystemZ::CLGR:
1793 return SystemZ::CLGRJ;
1794 case SystemZ::CLFI:
1795 return SystemZ::CLIJ;
1796 case SystemZ::CLGFI:
1797 return SystemZ::CLGIJ;
1798 default:
1799 return 0;
1800 }
1801 case SystemZII::CompareAndReturn:
1802 switch (Opcode) {
1803 case SystemZ::CR:
1804 return SystemZ::CRBReturn;
1805 case SystemZ::CGR:
1806 return SystemZ::CGRBReturn;
1807 case SystemZ::CHI:
1808 return SystemZ::CIBReturn;
1809 case SystemZ::CGHI:
1810 return SystemZ::CGIBReturn;
1811 case SystemZ::CLR:
1812 return SystemZ::CLRBReturn;
1813 case SystemZ::CLGR:
1814 return SystemZ::CLGRBReturn;
1815 case SystemZ::CLFI:
1816 return SystemZ::CLIBReturn;
1817 case SystemZ::CLGFI:
1818 return SystemZ::CLGIBReturn;
1819 default:
1820 return 0;
1821 }
1822 case SystemZII::CompareAndSibcall:
1823 switch (Opcode) {
1824 case SystemZ::CR:
1825 return SystemZ::CRBCall;
1826 case SystemZ::CGR:
1827 return SystemZ::CGRBCall;
1828 case SystemZ::CHI:
1829 return SystemZ::CIBCall;
1830 case SystemZ::CGHI:
1831 return SystemZ::CGIBCall;
1832 case SystemZ::CLR:
1833 return SystemZ::CLRBCall;
1834 case SystemZ::CLGR:
1835 return SystemZ::CLGRBCall;
1836 case SystemZ::CLFI:
1837 return SystemZ::CLIBCall;
1838 case SystemZ::CLGFI:
1839 return SystemZ::CLGIBCall;
1840 default:
1841 return 0;
1842 }
1843 case SystemZII::CompareAndTrap:
1844 switch (Opcode) {
1845 case SystemZ::CR:
1846 return SystemZ::CRT;
1847 case SystemZ::CGR:
1848 return SystemZ::CGRT;
1849 case SystemZ::CHI:
1850 return SystemZ::CIT;
1851 case SystemZ::CGHI:
1852 return SystemZ::CGIT;
1853 case SystemZ::CLR:
1854 return SystemZ::CLRT;
1855 case SystemZ::CLGR:
1856 return SystemZ::CLGRT;
1857 case SystemZ::CLFI:
1858 return SystemZ::CLFIT;
1859 case SystemZ::CLGFI:
1860 return SystemZ::CLGIT;
1861 case SystemZ::CL:
1862 return SystemZ::CLT;
1863 case SystemZ::CLG:
1864 return SystemZ::CLGT;
1865 default:
1866 return 0;
1867 }
1868 }
1869 return 0;
1870}
1871
1872bool SystemZInstrInfo::
1873prepareCompareSwapOperands(MachineBasicBlock::iterator const MBBI) const {
1874 assert(MBBI->isCompare() && MBBI->getOperand(0).isReg() &&(static_cast <bool> (MBBI->isCompare() && MBBI
->getOperand(0).isReg() && MBBI->getOperand(1).
isReg() && !MBBI->mayLoad() && "Not a compare reg/reg."
) ? void (0) : __assert_fail ("MBBI->isCompare() && MBBI->getOperand(0).isReg() && MBBI->getOperand(1).isReg() && !MBBI->mayLoad() && \"Not a compare reg/reg.\""
, "llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp", 1876, __extension__
__PRETTY_FUNCTION__))
1875 MBBI->getOperand(1).isReg() && !MBBI->mayLoad() &&(static_cast <bool> (MBBI->isCompare() && MBBI
->getOperand(0).isReg() && MBBI->getOperand(1).
isReg() && !MBBI->mayLoad() && "Not a compare reg/reg."
) ? void (0) : __assert_fail ("MBBI->isCompare() && MBBI->getOperand(0).isReg() && MBBI->getOperand(1).isReg() && !MBBI->mayLoad() && \"Not a compare reg/reg.\""
, "llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp", 1876, __extension__
__PRETTY_FUNCTION__))
1876 "Not a compare reg/reg.")(static_cast <bool> (MBBI->isCompare() && MBBI
->getOperand(0).isReg() && MBBI->getOperand(1).
isReg() && !MBBI->mayLoad() && "Not a compare reg/reg."
) ? void (0) : __assert_fail ("MBBI->isCompare() && MBBI->getOperand(0).isReg() && MBBI->getOperand(1).isReg() && !MBBI->mayLoad() && \"Not a compare reg/reg.\""
, "llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp", 1876, __extension__
__PRETTY_FUNCTION__))
;
1877
1878 MachineBasicBlock *MBB = MBBI->getParent();
1879 bool CCLive = true;
1880 SmallVector<MachineInstr *, 4> CCUsers;
1881 for (MachineInstr &MI : llvm::make_range(std::next(MBBI), MBB->end())) {
1882 if (MI.readsRegister(SystemZ::CC)) {
1883 unsigned Flags = MI.getDesc().TSFlags;
1884 if ((Flags & SystemZII::CCMaskFirst) || (Flags & SystemZII::CCMaskLast))
1885 CCUsers.push_back(&MI);
1886 else
1887 return false;
1888 }
1889 if (MI.definesRegister(SystemZ::CC)) {
1890 CCLive = false;
1891 break;
1892 }
1893 }
1894 if (CCLive) {
1895 LivePhysRegs LiveRegs(*MBB->getParent()->getSubtarget().getRegisterInfo());
1896 LiveRegs.addLiveOuts(*MBB);
1897 if (LiveRegs.contains(SystemZ::CC))
1898 return false;
1899 }
1900
1901 // Update all CC users.
1902 for (unsigned Idx = 0; Idx < CCUsers.size(); ++Idx) {
1903 unsigned Flags = CCUsers[Idx]->getDesc().TSFlags;
1904 unsigned FirstOpNum = ((Flags & SystemZII::CCMaskFirst) ?
1905 0 : CCUsers[Idx]->getNumExplicitOperands() - 2);
1906 MachineOperand &CCMaskMO = CCUsers[Idx]->getOperand(FirstOpNum + 1);
1907 unsigned NewCCMask = SystemZ::reverseCCMask(CCMaskMO.getImm());
1908 CCMaskMO.setImm(NewCCMask);
1909 }
1910
1911 return true;
1912}
1913
1914unsigned SystemZ::reverseCCMask(unsigned CCMask) {
1915 return ((CCMask & SystemZ::CCMASK_CMP_EQ) |
1916 (CCMask & SystemZ::CCMASK_CMP_GT ? SystemZ::CCMASK_CMP_LT : 0) |
1917 (CCMask & SystemZ::CCMASK_CMP_LT ? SystemZ::CCMASK_CMP_GT : 0) |
1918 (CCMask & SystemZ::CCMASK_CMP_UO));
1919}
1920
1921MachineBasicBlock *SystemZ::emitBlockAfter(MachineBasicBlock *MBB) {
1922 MachineFunction &MF = *MBB->getParent();
1923 MachineBasicBlock *NewMBB = MF.CreateMachineBasicBlock(MBB->getBasicBlock());
1924 MF.insert(std::next(MachineFunction::iterator(MBB)), NewMBB);
1925 return NewMBB;
1926}
1927
1928MachineBasicBlock *SystemZ::splitBlockAfter(MachineBasicBlock::iterator MI,
1929 MachineBasicBlock *MBB) {
1930 MachineBasicBlock *NewMBB = emitBlockAfter(MBB);
1931 NewMBB->splice(NewMBB->begin(), MBB,
1932 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
1933 NewMBB->transferSuccessorsAndUpdatePHIs(MBB);
1934 return NewMBB;
1935}
1936
1937MachineBasicBlock *SystemZ::splitBlockBefore(MachineBasicBlock::iterator MI,
1938 MachineBasicBlock *MBB) {
1939 MachineBasicBlock *NewMBB = emitBlockAfter(MBB);
1940 NewMBB->splice(NewMBB->begin(), MBB, MI, MBB->end());
1941 NewMBB->transferSuccessorsAndUpdatePHIs(MBB);
1942 return NewMBB;
1943}
1944
1945unsigned SystemZInstrInfo::getLoadAndTrap(unsigned Opcode) const {
1946 if (!STI.hasLoadAndTrap())
1947 return 0;
1948 switch (Opcode) {
1949 case SystemZ::L:
1950 case SystemZ::LY:
1951 return SystemZ::LAT;
1952 case SystemZ::LG:
1953 return SystemZ::LGAT;
1954 case SystemZ::LFH:
1955 return SystemZ::LFHAT;
1956 case SystemZ::LLGF:
1957 return SystemZ::LLGFAT;
1958 case SystemZ::LLGT:
1959 return SystemZ::LLGTAT;
1960 }
1961 return 0;
1962}
1963
1964void SystemZInstrInfo::loadImmediate(MachineBasicBlock &MBB,
1965 MachineBasicBlock::iterator MBBI,
1966 unsigned Reg, uint64_t Value) const {
1967 DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
1968 unsigned Opcode = 0;
1969 if (isInt<16>(Value))
1970 Opcode = SystemZ::LGHI;
1971 else if (SystemZ::isImmLL(Value))
1972 Opcode = SystemZ::LLILL;
1973 else if (SystemZ::isImmLH(Value)) {
1974 Opcode = SystemZ::LLILH;
1975 Value >>= 16;
1976 }
1977 else if (isInt<32>(Value))
1978 Opcode = SystemZ::LGFI;
1979 if (Opcode) {
1980 BuildMI(MBB, MBBI, DL, get(Opcode), Reg).addImm(Value);
1981 return;
1982 }
1983
1984 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
1985 assert (MRI.isSSA() && "Huge values only handled before reg-alloc .")(static_cast <bool> (MRI.isSSA() && "Huge values only handled before reg-alloc ."
) ? void (0) : __assert_fail ("MRI.isSSA() && \"Huge values only handled before reg-alloc .\""
, "llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp", 1985, __extension__
__PRETTY_FUNCTION__))
;
1986 Register Reg0 = MRI.createVirtualRegister(&SystemZ::GR64BitRegClass);
1987 Register Reg1 = MRI.createVirtualRegister(&SystemZ::GR64BitRegClass);
1988 BuildMI(MBB, MBBI, DL, get(SystemZ::IMPLICIT_DEF), Reg0);
1989 BuildMI(MBB, MBBI, DL, get(SystemZ::IIHF64), Reg1)
1990 .addReg(Reg0).addImm(Value >> 32);
1991 BuildMI(MBB, MBBI, DL, get(SystemZ::IILF64), Reg)
1992 .addReg(Reg1).addImm(Value & ((uint64_t(1) << 32) - 1));
1993}
1994
1995bool SystemZInstrInfo::verifyInstruction(const MachineInstr &MI,
1996 StringRef &ErrInfo) const {
1997 const MCInstrDesc &MCID = MI.getDesc();
1998 for (unsigned I = 0, E = MI.getNumOperands(); I != E; ++I) {
1999 if (I >= MCID.getNumOperands())
2000 break;
2001 const MachineOperand &Op = MI.getOperand(I);
2002 const MCOperandInfo &MCOI = MCID.OpInfo[I];
2003 // Addressing modes have register and immediate operands. Op should be a
2004 // register (or frame index) operand if MCOI.RegClass contains a valid
2005 // register class, or an immediate otherwise.
2006 if (MCOI.OperandType == MCOI::OPERAND_MEMORY &&
2007 ((MCOI.RegClass != -1 && !Op.isReg() && !Op.isFI()) ||
2008 (MCOI.RegClass == -1 && !Op.isImm()))) {
2009 ErrInfo = "Addressing mode operands corrupt!";
2010 return false;
2011 }
2012 }
2013
2014 return true;
2015}
2016
2017bool SystemZInstrInfo::
2018areMemAccessesTriviallyDisjoint(const MachineInstr &MIa,
2019 const MachineInstr &MIb) const {
2020
2021 if (!MIa.hasOneMemOperand() || !MIb.hasOneMemOperand())
2022 return false;
2023
2024 // If mem-operands show that the same address Value is used by both
2025 // instructions, check for non-overlapping offsets and widths. Not
2026 // sure if a register based analysis would be an improvement...
2027
2028 MachineMemOperand *MMOa = *MIa.memoperands_begin();
2029 MachineMemOperand *MMOb = *MIb.memoperands_begin();
2030 const Value *VALa = MMOa->getValue();
2031 const Value *VALb = MMOb->getValue();
2032 bool SameVal = (VALa && VALb && (VALa == VALb));
2033 if (!SameVal) {
2034 const PseudoSourceValue *PSVa = MMOa->getPseudoValue();
2035 const PseudoSourceValue *PSVb = MMOb->getPseudoValue();
2036 if (PSVa && PSVb && (PSVa == PSVb))
2037 SameVal = true;
2038 }
2039 if (SameVal) {
2040 int OffsetA = MMOa->getOffset(), OffsetB = MMOb->getOffset();
2041 int WidthA = MMOa->getSize(), WidthB = MMOb->getSize();
2042 int LowOffset = OffsetA < OffsetB ? OffsetA : OffsetB;
2043 int HighOffset = OffsetA < OffsetB ? OffsetB : OffsetA;
2044 int LowWidth = (LowOffset == OffsetA) ? WidthA : WidthB;
2045 if (LowOffset + LowWidth <= HighOffset)
2046 return true;
2047 }
2048
2049 return false;
2050}

/build/llvm-toolchain-snapshot-16~++20221003111214+1fa2019828ca/llvm/include/llvm/Support/MathExtras.h

1//===-- llvm/Support/MathExtras.h - Useful math functions -------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains some functions that are useful for math stuff.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_SUPPORT_MATHEXTRAS_H
14#define LLVM_SUPPORT_MATHEXTRAS_H
15
16#include "llvm/ADT/bit.h"
17#include "llvm/Support/Compiler.h"
18#include <cassert>
19#include <climits>
20#include <cstdint>
21#include <cstring>
22#include <limits>
23#include <type_traits>
24
25#ifdef _MSC_VER
26// Declare these intrinsics manually rather including intrin.h. It's very
27// expensive, and MathExtras.h is popular.
28// #include <intrin.h>
29extern "C" {
30unsigned char _BitScanForward(unsigned long *_Index, unsigned long _Mask);
31unsigned char _BitScanForward64(unsigned long *_Index, unsigned __int64 _Mask);
32unsigned char _BitScanReverse(unsigned long *_Index, unsigned long _Mask);
33unsigned char _BitScanReverse64(unsigned long *_Index, unsigned __int64 _Mask);
34}
35#endif
36
37namespace llvm {
38
39/// The behavior an operation has on an input of 0.
40enum ZeroBehavior {
41 /// The returned value is undefined.
42 ZB_Undefined,
43 /// The returned value is numeric_limits<T>::max()
44 ZB_Max,
45 /// The returned value is numeric_limits<T>::digits
46 ZB_Width
47};
48
49/// Mathematical constants.
50namespace numbers {
51// TODO: Track C++20 std::numbers.
52// TODO: Favor using the hexadecimal FP constants (requires C++17).
53constexpr double e = 2.7182818284590452354, // (0x1.5bf0a8b145749P+1) https://oeis.org/A001113
54 egamma = .57721566490153286061, // (0x1.2788cfc6fb619P-1) https://oeis.org/A001620
55 ln2 = .69314718055994530942, // (0x1.62e42fefa39efP-1) https://oeis.org/A002162
56 ln10 = 2.3025850929940456840, // (0x1.24bb1bbb55516P+1) https://oeis.org/A002392
57 log2e = 1.4426950408889634074, // (0x1.71547652b82feP+0)
58 log10e = .43429448190325182765, // (0x1.bcb7b1526e50eP-2)
59 pi = 3.1415926535897932385, // (0x1.921fb54442d18P+1) https://oeis.org/A000796
60 inv_pi = .31830988618379067154, // (0x1.45f306bc9c883P-2) https://oeis.org/A049541
61 sqrtpi = 1.7724538509055160273, // (0x1.c5bf891b4ef6bP+0) https://oeis.org/A002161
62 inv_sqrtpi = .56418958354775628695, // (0x1.20dd750429b6dP-1) https://oeis.org/A087197
63 sqrt2 = 1.4142135623730950488, // (0x1.6a09e667f3bcdP+0) https://oeis.org/A00219
64 inv_sqrt2 = .70710678118654752440, // (0x1.6a09e667f3bcdP-1)
65 sqrt3 = 1.7320508075688772935, // (0x1.bb67ae8584caaP+0) https://oeis.org/A002194
66 inv_sqrt3 = .57735026918962576451, // (0x1.279a74590331cP-1)
67 phi = 1.6180339887498948482; // (0x1.9e3779b97f4a8P+0) https://oeis.org/A001622
68constexpr float ef = 2.71828183F, // (0x1.5bf0a8P+1) https://oeis.org/A001113
69 egammaf = .577215665F, // (0x1.2788d0P-1) https://oeis.org/A001620
70 ln2f = .693147181F, // (0x1.62e430P-1) https://oeis.org/A002162
71 ln10f = 2.30258509F, // (0x1.26bb1cP+1) https://oeis.org/A002392
72 log2ef = 1.44269504F, // (0x1.715476P+0)
73 log10ef = .434294482F, // (0x1.bcb7b2P-2)
74 pif = 3.14159265F, // (0x1.921fb6P+1) https://oeis.org/A000796
75 inv_pif = .318309886F, // (0x1.45f306P-2) https://oeis.org/A049541
76 sqrtpif = 1.77245385F, // (0x1.c5bf8aP+0) https://oeis.org/A002161
77 inv_sqrtpif = .564189584F, // (0x1.20dd76P-1) https://oeis.org/A087197
78 sqrt2f = 1.41421356F, // (0x1.6a09e6P+0) https://oeis.org/A002193
79 inv_sqrt2f = .707106781F, // (0x1.6a09e6P-1)
80 sqrt3f = 1.73205081F, // (0x1.bb67aeP+0) https://oeis.org/A002194
81 inv_sqrt3f = .577350269F, // (0x1.279a74P-1)
82 phif = 1.61803399F; // (0x1.9e377aP+0) https://oeis.org/A001622
83} // namespace numbers
84
85namespace detail {
86template <typename T, std::size_t SizeOfT> struct TrailingZerosCounter {
87 static unsigned count(T Val, ZeroBehavior) {
88 if (!Val)
89 return std::numeric_limits<T>::digits;
90 if (Val & 0x1)
91 return 0;
92
93 // Bisection method.
94 unsigned ZeroBits = 0;
95 T Shift = std::numeric_limits<T>::digits >> 1;
96 T Mask = std::numeric_limits<T>::max() >> Shift;
97 while (Shift) {
98 if ((Val & Mask) == 0) {
99 Val >>= Shift;
100 ZeroBits |= Shift;
101 }
102 Shift >>= 1;
103 Mask >>= Shift;
104 }
105 return ZeroBits;
106 }
107};
108
109#if defined(__GNUC__4) || defined(_MSC_VER)
110template <typename T> struct TrailingZerosCounter<T, 4> {
111 static unsigned count(T Val, ZeroBehavior ZB) {
112 if (ZB != ZB_Undefined && Val == 0)
113 return 32;
114
115#if __has_builtin(__builtin_ctz)1 || defined(__GNUC__4)
116 return __builtin_ctz(Val);
117#elif defined(_MSC_VER)
118 unsigned long Index;
119 _BitScanForward(&Index, Val);
120 return Index;
121#endif
122 }
123};
124
125#if !defined(_MSC_VER) || defined(_M_X64)
126template <typename T> struct TrailingZerosCounter<T, 8> {
127 static unsigned count(T Val, ZeroBehavior ZB) {
128 if (ZB != ZB_Undefined && Val == 0)
129 return 64;
130
131#if __has_builtin(__builtin_ctzll)1 || defined(__GNUC__4)
132 return __builtin_ctzll(Val);
133#elif defined(_MSC_VER)
134 unsigned long Index;
135 _BitScanForward64(&Index, Val);
136 return Index;
137#endif
138 }
139};
140#endif
141#endif
142} // namespace detail
143
144/// Count number of 0's from the least significant bit to the most
145/// stopping at the first 1.
146///
147/// Only unsigned integral types are allowed.
148///
149/// \param ZB the behavior on an input of 0. Only ZB_Width and ZB_Undefined are
150/// valid arguments.
151template <typename T>
152unsigned countTrailingZeros(T Val, ZeroBehavior ZB = ZB_Width) {
153 static_assert(std::is_unsigned_v<T>,
154 "Only unsigned integral types are allowed.");
155 return llvm::detail::TrailingZerosCounter<T, sizeof(T)>::count(Val, ZB);
156}
157
158namespace detail {
159template <typename T, std::size_t SizeOfT> struct LeadingZerosCounter {
160 static unsigned count(T Val, ZeroBehavior) {
161 if (!Val)
162 return std::numeric_limits<T>::digits;
163
164 // Bisection method.
165 unsigned ZeroBits = 0;
166 for (T Shift = std::numeric_limits<T>::digits >> 1; Shift; Shift >>= 1) {
167 T Tmp = Val >> Shift;
168 if (Tmp)
169 Val = Tmp;
170 else
171 ZeroBits |= Shift;
172 }
173 return ZeroBits;
174 }
175};
176
177#if defined(__GNUC__4) || defined(_MSC_VER)
178template <typename T> struct LeadingZerosCounter<T, 4> {
179 static unsigned count(T Val, ZeroBehavior ZB) {
180 if (ZB != ZB_Undefined && Val == 0)
181 return 32;
182
183#if __has_builtin(__builtin_clz)1 || defined(__GNUC__4)
184 return __builtin_clz(Val);
185#elif defined(_MSC_VER)
186 unsigned long Index;
187 _BitScanReverse(&Index, Val);
188 return Index ^ 31;
189#endif
190 }
191};
192
193#if !defined(_MSC_VER) || defined(_M_X64)
194template <typename T> struct LeadingZerosCounter<T, 8> {
195 static unsigned count(T Val, ZeroBehavior ZB) {
196 if (ZB != ZB_Undefined && Val == 0)
197 return 64;
198
199#if __has_builtin(__builtin_clzll)1 || defined(__GNUC__4)
200 return __builtin_clzll(Val);
201#elif defined(_MSC_VER)
202 unsigned long Index;
203 _BitScanReverse64(&Index, Val);
204 return Index ^ 63;
205#endif
206 }
207};
208#endif
209#endif
210} // namespace detail
211
212/// Count number of 0's from the most significant bit to the least
213/// stopping at the first 1.
214///
215/// Only unsigned integral types are allowed.
216///
217/// \param ZB the behavior on an input of 0. Only ZB_Width and ZB_Undefined are
218/// valid arguments.
219template <typename T>
220unsigned countLeadingZeros(T Val, ZeroBehavior ZB = ZB_Width) {
221 static_assert(std::is_unsigned_v<T>,
222 "Only unsigned integral types are allowed.");
223 return llvm::detail::LeadingZerosCounter<T, sizeof(T)>::count(Val, ZB);
224}
225
226/// Get the index of the first set bit starting from the least
227/// significant bit.
228///
229/// Only unsigned integral types are allowed.
230///
231/// \param ZB the behavior on an input of 0. Only ZB_Max and ZB_Undefined are
232/// valid arguments.
233template <typename T> T findFirstSet(T Val, ZeroBehavior ZB = ZB_Max) {
234 if (ZB
7.1
'ZB' is equal to ZB_Max
7.1
'ZB' is equal to ZB_Max
7.1
'ZB' is equal to ZB_Max
== ZB_Max && Val == 0)
8
Assuming 'Val' is equal to 0
9
Taking true branch
235 return std::numeric_limits<T>::max();
10
Calling 'numeric_limits::max'
12
Returning from 'numeric_limits::max'
13
Returning the value 18446744073709551615
236
237 return countTrailingZeros(Val, ZB_Undefined);
238}
239
240/// Create a bitmask with the N right-most bits set to 1, and all other
241/// bits set to 0. Only unsigned types are allowed.
242template <typename T> T maskTrailingOnes(unsigned N) {
243 static_assert(std::is_unsigned<T>::value, "Invalid type!");
244 const unsigned Bits = CHAR_BIT8 * sizeof(T);
245 assert(N <= Bits && "Invalid bit index")(static_cast <bool> (N <= Bits && "Invalid bit index"
) ? void (0) : __assert_fail ("N <= Bits && \"Invalid bit index\""
, "llvm/include/llvm/Support/MathExtras.h", 245, __extension__
__PRETTY_FUNCTION__))
;
246 return N == 0 ? 0 : (T(-1) >> (Bits - N));
247}
248
249/// Create a bitmask with the N left-most bits set to 1, and all other
250/// bits set to 0. Only unsigned types are allowed.
251template <typename T> T maskLeadingOnes(unsigned N) {
252 return ~maskTrailingOnes<T>(CHAR_BIT8 * sizeof(T) - N);
253}
254
255/// Create a bitmask with the N right-most bits set to 0, and all other
256/// bits set to 1. Only unsigned types are allowed.
257template <typename T> T maskTrailingZeros(unsigned N) {
258 return maskLeadingOnes<T>(CHAR_BIT8 * sizeof(T) - N);
259}
260
261/// Create a bitmask with the N left-most bits set to 0, and all other
262/// bits set to 1. Only unsigned types are allowed.
263template <typename T> T maskLeadingZeros(unsigned N) {
264 return maskTrailingOnes<T>(CHAR_BIT8 * sizeof(T) - N);
265}
266
267/// Get the index of the last set bit starting from the least
268/// significant bit.
269///
270/// Only unsigned integral types are allowed.
271///
272/// \param ZB the behavior on an input of 0. Only ZB_Max and ZB_Undefined are
273/// valid arguments.
274template <typename T> T findLastSet(T Val, ZeroBehavior ZB = ZB_Max) {
275 if (ZB == ZB_Max && Val == 0)
276 return std::numeric_limits<T>::max();
277
278 // Use ^ instead of - because both gcc and llvm can remove the associated ^
279 // in the __builtin_clz intrinsic on x86.
280 return countLeadingZeros(Val, ZB_Undefined) ^
281 (std::numeric_limits<T>::digits - 1);
282}
283
284/// Macro compressed bit reversal table for 256 bits.
285///
286/// http://graphics.stanford.edu/~seander/bithacks.html#BitReverseTable
287static const unsigned char BitReverseTable256[256] = {
288#define R2(n) n, n + 2 * 64, n + 1 * 64, n + 3 * 64
289#define R4(n) R2(n), R2(n + 2 * 16), R2(n + 1 * 16), R2(n + 3 * 16)
290#define R6(n) R4(n), R4(n + 2 * 4), R4(n + 1 * 4), R4(n + 3 * 4)
291 R6(0), R6(2), R6(1), R6(3)
292#undef R2
293#undef R4
294#undef R6
295};
296
297/// Reverse the bits in \p Val.
298template <typename T> T reverseBits(T Val) {
299#if __has_builtin(__builtin_bitreverse8)1
300 if constexpr (std::is_same_v<T, uint8_t>)
301 return __builtin_bitreverse8(Val);
302#endif
303#if __has_builtin(__builtin_bitreverse16)1
304 if constexpr (std::is_same_v<T, uint16_t>)
305 return __builtin_bitreverse16(Val);
306#endif
307#if __has_builtin(__builtin_bitreverse32)1
308 if constexpr (std::is_same_v<T, uint32_t>)
309 return __builtin_bitreverse32(Val);
310#endif
311#if __has_builtin(__builtin_bitreverse64)1
312 if constexpr (std::is_same_v<T, uint64_t>)
313 return __builtin_bitreverse64(Val);
314#endif
315
316 unsigned char in[sizeof(Val)];
317 unsigned char out[sizeof(Val)];
318 std::memcpy(in, &Val, sizeof(Val));
319 for (unsigned i = 0; i < sizeof(Val); ++i)
320 out[(sizeof(Val) - i) - 1] = BitReverseTable256[in[i]];
321 std::memcpy(&Val, out, sizeof(Val));
322 return Val;
323}
324
325// NOTE: The following support functions use the _32/_64 extensions instead of
326// type overloading so that signed and unsigned integers can be used without
327// ambiguity.
328
329/// Return the high 32 bits of a 64 bit value.
330constexpr inline uint32_t Hi_32(uint64_t Value) {
331 return static_cast<uint32_t>(Value >> 32);
332}
333
334/// Return the low 32 bits of a 64 bit value.
335constexpr inline uint32_t Lo_32(uint64_t Value) {
336 return static_cast<uint32_t>(Value);
337}
338
339/// Make a 64-bit integer from a high / low pair of 32-bit integers.
340constexpr inline uint64_t Make_64(uint32_t High, uint32_t Low) {
341 return ((uint64_t)High << 32) | (uint64_t)Low;
342}
343
344/// Checks if an integer fits into the given bit width.
345template <unsigned N> constexpr inline bool isInt(int64_t x) {
346 if constexpr (N == 8)
347 return static_cast<int8_t>(x) == x;
348 if constexpr (N == 16)
349 return static_cast<int16_t>(x) == x;
350 if constexpr (N == 32)
351 return static_cast<int32_t>(x) == x;
352 if constexpr (N < 64)
353 return -(INT64_C(1)1L << (N - 1)) <= x && x < (INT64_C(1)1L << (N - 1));
354 (void)x; // MSVC v19.25 warns that x is unused.
355 return true;
356}
357
358/// Checks if a signed integer is an N bit number shifted left by S.
359template <unsigned N, unsigned S>
360constexpr inline bool isShiftedInt(int64_t x) {
361 static_assert(
362 N > 0, "isShiftedInt<0> doesn't make sense (refers to a 0-bit number.");
363 static_assert(N + S <= 64, "isShiftedInt<N, S> with N + S > 64 is too wide.");
364 return isInt<N + S>(x) && (x % (UINT64_C(1)1UL << S) == 0);
365}
366
367/// Checks if an unsigned integer fits into the given bit width.
368template <unsigned N> constexpr inline bool isUInt(uint64_t x) {
369 static_assert(N > 0, "isUInt<0> doesn't make sense");
370 if constexpr (N == 8)
371 return static_cast<uint8_t>(x) == x;
372 if constexpr (N == 16)
373 return static_cast<uint16_t>(x) == x;
374 if constexpr (N == 32)
375 return static_cast<uint32_t>(x) == x;
376 if constexpr (N < 64)
377 return x < (UINT64_C(1)1UL << (N));
378 (void)x; // MSVC v19.25 warns that x is unused.
379 return true;
380}
381
382/// Checks if a unsigned integer is an N bit number shifted left by S.
383template <unsigned N, unsigned S>
384constexpr inline bool isShiftedUInt(uint64_t x) {
385 static_assert(
386 N > 0, "isShiftedUInt<0> doesn't make sense (refers to a 0-bit number)");
387 static_assert(N + S <= 64,
388 "isShiftedUInt<N, S> with N + S > 64 is too wide.");
389 // Per the two static_asserts above, S must be strictly less than 64. So
390 // 1 << S is not undefined behavior.
391 return isUInt<N + S>(x) && (x % (UINT64_C(1)1UL << S) == 0);
392}
393
394/// Gets the maximum value for a N-bit unsigned integer.
395inline uint64_t maxUIntN(uint64_t N) {
396 assert(N > 0 && N <= 64 && "integer width out of range")(static_cast <bool> (N > 0 && N <= 64 &&
"integer width out of range") ? void (0) : __assert_fail ("N > 0 && N <= 64 && \"integer width out of range\""
, "llvm/include/llvm/Support/MathExtras.h", 396, __extension__
__PRETTY_FUNCTION__))
;
397
398 // uint64_t(1) << 64 is undefined behavior, so we can't do
399 // (uint64_t(1) << N) - 1
400 // without checking first that N != 64. But this works and doesn't have a
401 // branch.
402 return UINT64_MAX(18446744073709551615UL) >> (64 - N);
403}
404
405/// Gets the minimum value for a N-bit signed integer.
406inline int64_t minIntN(int64_t N) {
407 assert(N > 0 && N <= 64 && "integer width out of range")(static_cast <bool> (N > 0 && N <= 64 &&
"integer width out of range") ? void (0) : __assert_fail ("N > 0 && N <= 64 && \"integer width out of range\""
, "llvm/include/llvm/Support/MathExtras.h", 407, __extension__
__PRETTY_FUNCTION__))
;
408
409 return UINT64_C(1)1UL + ~(UINT64_C(1)1UL << (N - 1));
410}
411
412/// Gets the maximum value for a N-bit signed integer.
413inline int64_t maxIntN(int64_t N) {
414 assert(N > 0 && N <= 64 && "integer width out of range")(static_cast <bool> (N > 0 && N <= 64 &&
"integer width out of range") ? void (0) : __assert_fail ("N > 0 && N <= 64 && \"integer width out of range\""
, "llvm/include/llvm/Support/MathExtras.h", 414, __extension__
__PRETTY_FUNCTION__))
;
415
416 // This relies on two's complement wraparound when N == 64, so we convert to
417 // int64_t only at the very end to avoid UB.
418 return (UINT64_C(1)1UL << (N - 1)) - 1;
419}
420
421/// Checks if an unsigned integer fits into the given (dynamic) bit width.
422inline bool isUIntN(unsigned N, uint64_t x) {
423 return N >= 64 || x <= maxUIntN(N);
424}
425
426/// Checks if an signed integer fits into the given (dynamic) bit width.
427inline bool isIntN(unsigned N, int64_t x) {
428 return N >= 64 || (minIntN(N) <= x && x <= maxIntN(N));
429}
430
431/// Return true if the argument is a non-empty sequence of ones starting at the
432/// least significant bit with the remainder zero (32 bit version).
433/// Ex. isMask_32(0x0000FFFFU) == true.
434constexpr inline bool isMask_32(uint32_t Value) {
435 return Value && ((Value + 1) & Value) == 0;
436}
437
438/// Return true if the argument is a non-empty sequence of ones starting at the
439/// least significant bit with the remainder zero (64 bit version).
440constexpr inline bool isMask_64(uint64_t Value) {
441 return Value && ((Value + 1) & Value) == 0;
442}
443
444/// Return true if the argument contains a non-empty sequence of ones with the
445/// remainder zero (32 bit version.) Ex. isShiftedMask_32(0x0000FF00U) == true.
446constexpr inline bool isShiftedMask_32(uint32_t Value) {
447 return Value && isMask_32((Value - 1) | Value);
448}
449
450/// Return true if the argument contains a non-empty sequence of ones with the
451/// remainder zero (64 bit version.)
452constexpr inline bool isShiftedMask_64(uint64_t Value) {
453 return Value && isMask_64((Value - 1) | Value);
454}
455
456/// Return true if the argument is a power of two > 0.
457/// Ex. isPowerOf2_32(0x00100000U) == true (32 bit edition.)
458constexpr inline bool isPowerOf2_32(uint32_t Value) {
459 return llvm::has_single_bit(Value);
460}
461
462/// Return true if the argument is a power of two > 0 (64 bit edition.)
463constexpr inline bool isPowerOf2_64(uint64_t Value) {
464 return llvm::has_single_bit(Value);
465}
466
467/// Count the number of ones from the most significant bit to the first
468/// zero bit.
469///
470/// Ex. countLeadingOnes(0xFF0FFF00) == 8.
471/// Only unsigned integral types are allowed.
472///
473/// \param ZB the behavior on an input of all ones. Only ZB_Width and
474/// ZB_Undefined are valid arguments.
475template <typename T>
476unsigned countLeadingOnes(T Value, ZeroBehavior ZB = ZB_Width) {
477 static_assert(std::is_unsigned_v<T>,
478 "Only unsigned integral types are allowed.");
479 return countLeadingZeros<T>(~Value, ZB);
480}
481
482/// Count the number of ones from the least significant bit to the first
483/// zero bit.
484///
485/// Ex. countTrailingOnes(0x00FF00FF) == 8.
486/// Only unsigned integral types are allowed.
487///
488/// \param ZB the behavior on an input of all ones. Only ZB_Width and
489/// ZB_Undefined are valid arguments.
490template <typename T>
491unsigned countTrailingOnes(T Value, ZeroBehavior ZB = ZB_Width) {
492 static_assert(std::is_unsigned_v<T>,
493 "Only unsigned integral types are allowed.");
494 return countTrailingZeros<T>(~Value, ZB);
495}
496
497/// Count the number of set bits in a value.
498/// Ex. countPopulation(0xF000F000) = 8
499/// Returns 0 if the word is zero.
500template <typename T>
501inline unsigned countPopulation(T Value) {
502 static_assert(std::is_unsigned_v<T>,
503 "Only unsigned integral types are allowed.");
504 return (unsigned)llvm::popcount(Value);
505}
506
507/// Return true if the argument contains a non-empty sequence of ones with the
508/// remainder zero (32 bit version.) Ex. isShiftedMask_32(0x0000FF00U) == true.
509/// If true, \p MaskIdx will specify the index of the lowest set bit and \p
510/// MaskLen is updated to specify the length of the mask, else neither are
511/// updated.
512inline bool isShiftedMask_32(uint32_t Value, unsigned &MaskIdx,
513 unsigned &MaskLen) {
514 if (!isShiftedMask_32(Value))
515 return false;
516 MaskIdx = countTrailingZeros(Value);
517 MaskLen = countPopulation(Value);
518 return true;
519}
520
521/// Return true if the argument contains a non-empty sequence of ones with the
522/// remainder zero (64 bit version.) If true, \p MaskIdx will specify the index
523/// of the lowest set bit and \p MaskLen is updated to specify the length of the
524/// mask, else neither are updated.
525inline bool isShiftedMask_64(uint64_t Value, unsigned &MaskIdx,
526 unsigned &MaskLen) {
527 if (!isShiftedMask_64(Value))
528 return false;
529 MaskIdx = countTrailingZeros(Value);
530 MaskLen = countPopulation(Value);
531 return true;
532}
533
534/// Compile time Log2.
535/// Valid only for positive powers of two.
536template <size_t kValue> constexpr inline size_t CTLog2() {
537 static_assert(kValue > 0 && llvm::isPowerOf2_64(kValue),
538 "Value is not a valid power of 2");
539 return 1 + CTLog2<kValue / 2>();
540}
541
542template <> constexpr inline size_t CTLog2<1>() { return 0; }
543
544/// Return the floor log base 2 of the specified value, -1 if the value is zero.
545/// (32 bit edition.)
546/// Ex. Log2_32(32) == 5, Log2_32(1) == 0, Log2_32(0) == -1, Log2_32(6) == 2
547inline unsigned Log2_32(uint32_t Value) {
548 return 31 - countLeadingZeros(Value);
549}
550
551/// Return the floor log base 2 of the specified value, -1 if the value is zero.
552/// (64 bit edition.)
553inline unsigned Log2_64(uint64_t Value) {
554 return 63 - countLeadingZeros(Value);
555}
556
557/// Return the ceil log base 2 of the specified value, 32 if the value is zero.
558/// (32 bit edition).
559/// Ex. Log2_32_Ceil(32) == 5, Log2_32_Ceil(1) == 0, Log2_32_Ceil(6) == 3
560inline unsigned Log2_32_Ceil(uint32_t Value) {
561 return 32 - countLeadingZeros(Value - 1);
562}
563
564/// Return the ceil log base 2 of the specified value, 64 if the value is zero.
565/// (64 bit edition.)
566inline unsigned Log2_64_Ceil(uint64_t Value) {
567 return 64 - countLeadingZeros(Value - 1);
568}
569
570/// This function takes a 64-bit integer and returns the bit equivalent double.
571inline double BitsToDouble(uint64_t Bits) {
572 static_assert(sizeof(uint64_t) == sizeof(double), "Unexpected type sizes");
573 return llvm::bit_cast<double>(Bits);
574}
575
576/// This function takes a 32-bit integer and returns the bit equivalent float.
577inline float BitsToFloat(uint32_t Bits) {
578 static_assert(sizeof(uint32_t) == sizeof(float), "Unexpected type sizes");
579 return llvm::bit_cast<float>(Bits);
580}
581
582/// This function takes a double and returns the bit equivalent 64-bit integer.
583/// Note that copying doubles around changes the bits of NaNs on some hosts,
584/// notably x86, so this routine cannot be used if these bits are needed.
585inline uint64_t DoubleToBits(double Double) {
586 static_assert(sizeof(uint64_t) == sizeof(double), "Unexpected type sizes");
587 return llvm::bit_cast<uint64_t>(Double);
588}
589
590/// This function takes a float and returns the bit equivalent 32-bit integer.
591/// Note that copying floats around changes the bits of NaNs on some hosts,
592/// notably x86, so this routine cannot be used if these bits are needed.
593inline uint32_t FloatToBits(float Float) {
594 static_assert(sizeof(uint32_t) == sizeof(float), "Unexpected type sizes");
595 return llvm::bit_cast<uint32_t>(Float);
596}
597
598/// A and B are either alignments or offsets. Return the minimum alignment that
599/// may be assumed after adding the two together.
600constexpr inline uint64_t MinAlign(uint64_t A, uint64_t B) {
601 // The largest power of 2 that divides both A and B.
602 //
603 // Replace "-Value" by "1+~Value" in the following commented code to avoid
604 // MSVC warning C4146
605 // return (A | B) & -(A | B);
606 return (A | B) & (1 + ~(A | B));
607}
608
609/// Returns the next power of two (in 64-bits) that is strictly greater than A.
610/// Returns zero on overflow.
611constexpr inline uint64_t NextPowerOf2(uint64_t A) {
612 A |= (A >> 1);
613 A |= (A >> 2);
614 A |= (A >> 4);
615 A |= (A >> 8);
616 A |= (A >> 16);
617 A |= (A >> 32);
618 return A + 1;
619}
620
621/// Returns the power of two which is less than or equal to the given value.
622/// Essentially, it is a floor operation across the domain of powers of two.
623inline uint64_t PowerOf2Floor(uint64_t A) {
624 if (!A) return 0;
625 return 1ull << (63 - countLeadingZeros(A, ZB_Undefined));
626}
627
628/// Returns the power of two which is greater than or equal to the given value.
629/// Essentially, it is a ceil operation across the domain of powers of two.
630inline uint64_t PowerOf2Ceil(uint64_t A) {
631 if (!A)
632 return 0;
633 return NextPowerOf2(A - 1);
634}
635
636/// Returns the next integer (mod 2**64) that is greater than or equal to
637/// \p Value and is a multiple of \p Align. \p Align must be non-zero.
638///
639/// Examples:
640/// \code
641/// alignTo(5, 8) = 8
642/// alignTo(17, 8) = 24
643/// alignTo(~0LL, 8) = 0
644/// alignTo(321, 255) = 510
645/// \endcode
646inline uint64_t alignTo(uint64_t Value, uint64_t Align) {
647 assert(Align != 0u && "Align can't be 0.")(static_cast <bool> (Align != 0u && "Align can't be 0."
) ? void (0) : __assert_fail ("Align != 0u && \"Align can't be 0.\""
, "llvm/include/llvm/Support/MathExtras.h", 647, __extension__
__PRETTY_FUNCTION__))
;
648 return (Value + Align - 1) / Align * Align;
649}
650
651inline uint64_t alignToPowerOf2(uint64_t Value, uint64_t Align) {
652 assert(Align != 0 && (Align & (Align - 1)) == 0 &&(static_cast <bool> (Align != 0 && (Align &
(Align - 1)) == 0 && "Align must be a power of 2") ?
void (0) : __assert_fail ("Align != 0 && (Align & (Align - 1)) == 0 && \"Align must be a power of 2\""
, "llvm/include/llvm/Support/MathExtras.h", 653, __extension__
__PRETTY_FUNCTION__))
653 "Align must be a power of 2")(static_cast <bool> (Align != 0 && (Align &
(Align - 1)) == 0 && "Align must be a power of 2") ?
void (0) : __assert_fail ("Align != 0 && (Align & (Align - 1)) == 0 && \"Align must be a power of 2\""
, "llvm/include/llvm/Support/MathExtras.h", 653, __extension__
__PRETTY_FUNCTION__))
;
654 return (Value + Align - 1) & -Align;
655}
656
657/// If non-zero \p Skew is specified, the return value will be a minimal integer
658/// that is greater than or equal to \p Size and equal to \p A * N + \p Skew for
659/// some integer N. If \p Skew is larger than \p A, its value is adjusted to '\p
660/// Skew mod \p A'. \p Align must be non-zero.
661///
662/// Examples:
663/// \code
664/// alignTo(5, 8, 7) = 7
665/// alignTo(17, 8, 1) = 17
666/// alignTo(~0LL, 8, 3) = 3
667/// alignTo(321, 255, 42) = 552
668/// \endcode
669inline uint64_t alignTo(uint64_t Value, uint64_t Align, uint64_t Skew) {
670 assert(Align != 0u && "Align can't be 0.")(static_cast <bool> (Align != 0u && "Align can't be 0."
) ? void (0) : __assert_fail ("Align != 0u && \"Align can't be 0.\""
, "llvm/include/llvm/Support/MathExtras.h", 670, __extension__
__PRETTY_FUNCTION__))
;
671 Skew %= Align;
672 return alignTo(Value - Skew, Align) + Skew;
673}
674
675/// Returns the next integer (mod 2**64) that is greater than or equal to
676/// \p Value and is a multiple of \c Align. \c Align must be non-zero.
677template <uint64_t Align> constexpr inline uint64_t alignTo(uint64_t Value) {
678 static_assert(Align != 0u, "Align must be non-zero");
679 return (Value + Align - 1) / Align * Align;
680}
681
682/// Returns the integer ceil(Numerator / Denominator).
683inline uint64_t divideCeil(uint64_t Numerator, uint64_t Denominator) {
684 return alignTo(Numerator, Denominator) / Denominator;
685}
686
687/// Returns the integer nearest(Numerator / Denominator).
688inline uint64_t divideNearest(uint64_t Numerator, uint64_t Denominator) {
689 return (Numerator + (Denominator / 2)) / Denominator;
690}
691
692/// Returns the largest uint64_t less than or equal to \p Value and is
693/// \p Skew mod \p Align. \p Align must be non-zero
694inline uint64_t alignDown(uint64_t Value, uint64_t Align, uint64_t Skew = 0) {
695 assert(Align != 0u && "Align can't be 0.")(static_cast <bool> (Align != 0u && "Align can't be 0."
) ? void (0) : __assert_fail ("Align != 0u && \"Align can't be 0.\""
, "llvm/include/llvm/Support/MathExtras.h", 695, __extension__
__PRETTY_FUNCTION__))
;
696 Skew %= Align;
697 return (Value - Skew) / Align * Align + Skew;
698}
699
700/// Sign-extend the number in the bottom B bits of X to a 32-bit integer.
701/// Requires 0 < B <= 32.
702template <unsigned B> constexpr inline int32_t SignExtend32(uint32_t X) {
703 static_assert(B > 0, "Bit width can't be 0.");
704 static_assert(B <= 32, "Bit width out of range.");
705 return int32_t(X << (32 - B)) >> (32 - B);
706}
707
708/// Sign-extend the number in the bottom B bits of X to a 32-bit integer.
709/// Requires 0 < B <= 32.
710inline int32_t SignExtend32(uint32_t X, unsigned B) {
711 assert(B > 0 && "Bit width can't be 0.")(static_cast <bool> (B > 0 && "Bit width can't be 0."
) ? void (0) : __assert_fail ("B > 0 && \"Bit width can't be 0.\""
, "llvm/include/llvm/Support/MathExtras.h", 711, __extension__
__PRETTY_FUNCTION__))
;
712 assert(B <= 32 && "Bit width out of range.")(static_cast <bool> (B <= 32 && "Bit width out of range."
) ? void (0) : __assert_fail ("B <= 32 && \"Bit width out of range.\""
, "llvm/include/llvm/Support/MathExtras.h", 712, __extension__
__PRETTY_FUNCTION__))
;
713 return int32_t(X << (32 - B)) >> (32 - B);
714}
715
716/// Sign-extend the number in the bottom B bits of X to a 64-bit integer.
717/// Requires 0 < B <= 64.
718template <unsigned B> constexpr inline int64_t SignExtend64(uint64_t x) {
719 static_assert(B > 0, "Bit width can't be 0.");
720 static_assert(B <= 64, "Bit width out of range.");
721 return int64_t(x << (64 - B)) >> (64 - B);
722}
723
724/// Sign-extend the number in the bottom B bits of X to a 64-bit integer.
725/// Requires 0 < B <= 64.
726inline int64_t SignExtend64(uint64_t X, unsigned B) {
727 assert(B > 0 && "Bit width can't be 0.")(static_cast <bool> (B > 0 && "Bit width can't be 0."
) ? void (0) : __assert_fail ("B > 0 && \"Bit width can't be 0.\""
, "llvm/include/llvm/Support/MathExtras.h", 727, __extension__
__PRETTY_FUNCTION__))
;
728 assert(B <= 64 && "Bit width out of range.")(static_cast <bool> (B <= 64 && "Bit width out of range."
) ? void (0) : __assert_fail ("B <= 64 && \"Bit width out of range.\""
, "llvm/include/llvm/Support/MathExtras.h", 728, __extension__
__PRETTY_FUNCTION__))
;
729 return int64_t(X << (64 - B)) >> (64 - B);
730}
731
732/// Subtract two unsigned integers, X and Y, of type T and return the absolute
733/// value of the result.
734template <typename T>
735std::enable_if_t<std::is_unsigned<T>::value, T> AbsoluteDifference(T X, T Y) {
736 return X > Y ? (X - Y) : (Y - X);
737}
738
739/// Add two unsigned integers, X and Y, of type T. Clamp the result to the
740/// maximum representable value of T on overflow. ResultOverflowed indicates if
741/// the result is larger than the maximum representable value of type T.
742template <typename T>
743std::enable_if_t<std::is_unsigned<T>::value, T>
744SaturatingAdd(T X, T Y, bool *ResultOverflowed = nullptr) {
745 bool Dummy;
746 bool &Overflowed = ResultOverflowed ? *ResultOverflowed : Dummy;
747 // Hacker's Delight, p. 29
748 T Z = X + Y;
749 Overflowed = (Z < X || Z < Y);
750 if (Overflowed)
751 return std::numeric_limits<T>::max();
752 else
753 return Z;
754}
755
756/// Multiply two unsigned integers, X and Y, of type T. Clamp the result to the
757/// maximum representable value of T on overflow. ResultOverflowed indicates if
758/// the result is larger than the maximum representable value of type T.
759template <typename T>
760std::enable_if_t<std::is_unsigned<T>::value, T>
761SaturatingMultiply(T X, T Y, bool *ResultOverflowed = nullptr) {
762 bool Dummy;
763 bool &Overflowed = ResultOverflowed ? *ResultOverflowed : Dummy;
764
765 // Hacker's Delight, p. 30 has a different algorithm, but we don't use that
766 // because it fails for uint16_t (where multiplication can have undefined
767 // behavior due to promotion to int), and requires a division in addition
768 // to the multiplication.
769
770 Overflowed = false;
771
772 // Log2(Z) would be either Log2Z or Log2Z + 1.
773 // Special case: if X or Y is 0, Log2_64 gives -1, and Log2Z
774 // will necessarily be less than Log2Max as desired.
775 int Log2Z = Log2_64(X) + Log2_64(Y);
776 const T Max = std::numeric_limits<T>::max();
777 int Log2Max = Log2_64(Max);
778 if (Log2Z < Log2Max) {
779 return X * Y;
780 }
781 if (Log2Z > Log2Max) {
782 Overflowed = true;
783 return Max;
784 }
785
786 // We're going to use the top bit, and maybe overflow one
787 // bit past it. Multiply all but the bottom bit then add
788 // that on at the end.
789 T Z = (X >> 1) * Y;
790 if (Z & ~(Max >> 1)) {
791 Overflowed = true;
792 return Max;
793 }
794 Z <<= 1;
795 if (X & 1)
796 return SaturatingAdd(Z, Y, ResultOverflowed);
797
798 return Z;
799}
800
801/// Multiply two unsigned integers, X and Y, and add the unsigned integer, A to
802/// the product. Clamp the result to the maximum representable value of T on
803/// overflow. ResultOverflowed indicates if the result is larger than the
804/// maximum representable value of type T.
805template <typename T>
806std::enable_if_t<std::is_unsigned<T>::value, T>
807SaturatingMultiplyAdd(T X, T Y, T A, bool *ResultOverflowed = nullptr) {
808 bool Dummy;
809 bool &Overflowed = ResultOverflowed ? *ResultOverflowed : Dummy;
810
811 T Product = SaturatingMultiply(X, Y, &Overflowed);
812 if (Overflowed)
813 return Product;
814
815 return SaturatingAdd(A, Product, &Overflowed);
816}
817
818/// Use this rather than HUGE_VALF; the latter causes warnings on MSVC.
819extern const float huge_valf;
820
821
822/// Add two signed integers, computing the two's complement truncated result,
823/// returning true if overflow occurred.
824template <typename T>
825std::enable_if_t<std::is_signed<T>::value, T> AddOverflow(T X, T Y, T &Result) {
826#if __has_builtin(__builtin_add_overflow)1
827 return __builtin_add_overflow(X, Y, &Result);
828#else
829 // Perform the unsigned addition.
830 using U = std::make_unsigned_t<T>;
831 const U UX = static_cast<U>(X);
832 const U UY = static_cast<U>(Y);
833 const U UResult = UX + UY;
834
835 // Convert to signed.
836 Result = static_cast<T>(UResult);
837
838 // Adding two positive numbers should result in a positive number.
839 if (X > 0 && Y > 0)
840 return Result <= 0;
841 // Adding two negatives should result in a negative number.
842 if (X < 0 && Y < 0)
843 return Result >= 0;
844 return false;
845#endif
846}
847
848/// Subtract two signed integers, computing the two's complement truncated
849/// result, returning true if an overflow ocurred.
850template <typename T>
851std::enable_if_t<std::is_signed<T>::value, T> SubOverflow(T X, T Y, T &Result) {
852#if __has_builtin(__builtin_sub_overflow)1
853 return __builtin_sub_overflow(X, Y, &Result);
854#else
855 // Perform the unsigned addition.
856 using U = std::make_unsigned_t<T>;
857 const U UX = static_cast<U>(X);
858 const U UY = static_cast<U>(Y);
859 const U UResult = UX - UY;
860
861 // Convert to signed.
862 Result = static_cast<T>(UResult);
863
864 // Subtracting a positive number from a negative results in a negative number.
865 if (X <= 0 && Y > 0)
866 return Result >= 0;
867 // Subtracting a negative number from a positive results in a positive number.
868 if (X >= 0 && Y < 0)
869 return Result <= 0;
870 return false;
871#endif
872}
873
874/// Multiply two signed integers, computing the two's complement truncated
875/// result, returning true if an overflow ocurred.
876template <typename T>
877std::enable_if_t<std::is_signed<T>::value, T> MulOverflow(T X, T Y, T &Result) {
878 // Perform the unsigned multiplication on absolute values.
879 using U = std::make_unsigned_t<T>;
880 const U UX = X < 0 ? (0 - static_cast<U>(X)) : static_cast<U>(X);
881 const U UY = Y < 0 ? (0 - static_cast<U>(Y)) : static_cast<U>(Y);
882 const U UResult = UX * UY;
883
884 // Convert to signed.
885 const bool IsNegative = (X < 0) ^ (Y < 0);
886 Result = IsNegative ? (0 - UResult) : UResult;
887
888 // If any of the args was 0, result is 0 and no overflow occurs.
889 if (UX == 0 || UY == 0)
890 return false;
891
892 // UX and UY are in [1, 2^n], where n is the number of digits.
893 // Check how the max allowed absolute value (2^n for negative, 2^(n-1) for
894 // positive) divided by an argument compares to the other.
895 if (IsNegative)
896 return UX > (static_cast<U>(std::numeric_limits<T>::max()) + U(1)) / UY;
897 else
898 return UX > (static_cast<U>(std::numeric_limits<T>::max())) / UY;
899}
900
901} // End llvm namespace
902
903#endif

/usr/lib/gcc/x86_64-linux-gnu/10/../../../../include/c++/10/limits

1// The template and inlines for the numeric_limits classes. -*- C++ -*-
2
3// Copyright (C) 1999-2020 Free Software Foundation, Inc.
4//
5// This file is part of the GNU ISO C++ Library. This library is free
6// software; you can redistribute it and/or modify it under the
7// terms of the GNU General Public License as published by the
8// Free Software Foundation; either version 3, or (at your option)
9// any later version.
10
11// This library is distributed in the hope that it will be useful,
12// but WITHOUT ANY WARRANTY; without even the implied warranty of
13// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14// GNU General Public License for more details.
15
16// Under Section 7 of GPL version 3, you are granted additional
17// permissions described in the GCC Runtime Library Exception, version
18// 3.1, as published by the Free Software Foundation.
19
20// You should have received a copy of the GNU General Public License and
21// a copy of the GCC Runtime Library Exception along with this program;
22// see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
23// <http://www.gnu.org/licenses/>.
24
25/** @file include/limits
26 * This is a Standard C++ Library header.
27 */
28
29// Note: this is not a conforming implementation.
30// Written by Gabriel Dos Reis <gdr@codesourcery.com>
31
32//
33// ISO 14882:1998
34// 18.2.1
35//
36
37#ifndef _GLIBCXX_NUMERIC_LIMITS1
38#define _GLIBCXX_NUMERIC_LIMITS1 1
39
40#pragma GCC system_header
41
42#include <bits/c++config.h>
43
44//
45// The numeric_limits<> traits document implementation-defined aspects
46// of fundamental arithmetic data types (integers and floating points).
47// From Standard C++ point of view, there are 14 such types:
48// * integers
49// bool (1)
50// char, signed char, unsigned char, wchar_t (4)
51// short, unsigned short (2)
52// int, unsigned (2)
53// long, unsigned long (2)
54//
55// * floating points
56// float (1)
57// double (1)
58// long double (1)
59//
60// GNU C++ understands (where supported by the host C-library)
61// * integer
62// long long, unsigned long long (2)
63//
64// which brings us to 16 fundamental arithmetic data types in GNU C++.
65//
66//
67// Since a numeric_limits<> is a bit tricky to get right, we rely on
68// an interface composed of macros which should be defined in config/os
69// or config/cpu when they differ from the generic (read arbitrary)
70// definitions given here.
71//
72
73// These values can be overridden in the target configuration file.
74// The default values are appropriate for many 32-bit targets.
75
76// GCC only intrinsically supports modulo integral types. The only remaining
77// integral exceptional values is division by zero. Only targets that do not
78// signal division by zero in some "hard to ignore" way should use false.
79#ifndef __glibcxx_integral_trapstrue
80# define __glibcxx_integral_trapstrue true
81#endif
82
83// float
84//
85
86// Default values. Should be overridden in configuration files if necessary.
87
88#ifndef __glibcxx_float_has_denorm_loss
89# define __glibcxx_float_has_denorm_loss false
90#endif
91#ifndef __glibcxx_float_traps
92# define __glibcxx_float_traps false
93#endif
94#ifndef __glibcxx_float_tinyness_before
95# define __glibcxx_float_tinyness_before false
96#endif
97
98// double
99
100// Default values. Should be overridden in configuration files if necessary.
101
102#ifndef __glibcxx_double_has_denorm_loss
103# define __glibcxx_double_has_denorm_loss false
104#endif
105#ifndef __glibcxx_double_traps
106# define __glibcxx_double_traps false
107#endif
108#ifndef __glibcxx_double_tinyness_before
109# define __glibcxx_double_tinyness_before false
110#endif
111
112// long double
113
114// Default values. Should be overridden in configuration files if necessary.
115
116#ifndef __glibcxx_long_double_has_denorm_loss
117# define __glibcxx_long_double_has_denorm_loss false
118#endif
119#ifndef __glibcxx_long_double_traps
120# define __glibcxx_long_double_traps false
121#endif
122#ifndef __glibcxx_long_double_tinyness_before
123# define __glibcxx_long_double_tinyness_before false
124#endif
125
126// You should not need to define any macros below this point.
127
128#define __glibcxx_signed_b(T,B)((T)(-1) < 0) ((T)(-1) < 0)
129
130#define __glibcxx_min_b(T,B)(((T)(-1) < 0) ? -(((T)(-1) < 0) ? (((((T)1 << ((
B - ((T)(-1) < 0)) - 1)) - 1) << 1) + 1) : ~(T)0) - 1
: (T)0)
\
131 (__glibcxx_signed_b (T,B)((T)(-1) < 0) ? -__glibcxx_max_b (T,B)(((T)(-1) < 0) ? (((((T)1 << ((B - ((T)(-1) < 0))
- 1)) - 1) << 1) + 1) : ~(T)0)
- 1 : (T)0)
132
133#define __glibcxx_max_b(T,B)(((T)(-1) < 0) ? (((((T)1 << ((B - ((T)(-1) < 0))
- 1)) - 1) << 1) + 1) : ~(T)0)
\
134 (__glibcxx_signed_b (T,B)((T)(-1) < 0) ? \
135 (((((T)1 << (__glibcxx_digits_b (T,B)(B - ((T)(-1) < 0)) - 1)) - 1) << 1) + 1) : ~(T)0)
136
137#define __glibcxx_digits_b(T,B)(B - ((T)(-1) < 0)) \
138 (B - __glibcxx_signed_b (T,B)((T)(-1) < 0))
139
140// The fraction 643/2136 approximates log10(2) to 7 significant digits.
141#define __glibcxx_digits10_b(T,B)((B - ((T)(-1) < 0)) * 643L / 2136) \
142 (__glibcxx_digits_b (T,B)(B - ((T)(-1) < 0)) * 643L / 2136)
143
144#define __glibcxx_signed(T) \
145 __glibcxx_signed_b (T, sizeof(T) * __CHAR_BIT__)((T)(-1) < 0)
146#define __glibcxx_min(T) \
147 __glibcxx_min_b (T, sizeof(T) * __CHAR_BIT__)(((T)(-1) < 0) ? -(((T)(-1) < 0) ? (((((T)1 << ((
sizeof(T) * 8 - ((T)(-1) < 0)) - 1)) - 1) << 1) + 1)
: ~(T)0) - 1 : (T)0)
148#define __glibcxx_max(T) \
149 __glibcxx_max_b (T, sizeof(T) * __CHAR_BIT__)(((T)(-1) < 0) ? (((((T)1 << ((sizeof(T) * 8 - ((T)(
-1) < 0)) - 1)) - 1) << 1) + 1) : ~(T)0)
150#define __glibcxx_digits(T) \
151 __glibcxx_digits_b (T, sizeof(T) * __CHAR_BIT__)(sizeof(T) * 8 - ((T)(-1) < 0))
152#define __glibcxx_digits10(T) \
153 __glibcxx_digits10_b (T, sizeof(T) * __CHAR_BIT__)((sizeof(T) * 8 - ((T)(-1) < 0)) * 643L / 2136)
154
155#define __glibcxx_max_digits10(T) \
156 (2 + (T) * 643L / 2136)
157
158namespace std _GLIBCXX_VISIBILITY(default)__attribute__ ((__visibility__ ("default")))
159{
160_GLIBCXX_BEGIN_NAMESPACE_VERSION
161
162 /**
163 * @brief Describes the rounding style for floating-point types.
164 *
165 * This is used in the std::numeric_limits class.
166 */
167 enum float_round_style
168 {
169 round_indeterminate = -1, /// Intermediate.
170 round_toward_zero = 0, /// To zero.
171 round_to_nearest = 1, /// To the nearest representable value.
172 round_toward_infinity = 2, /// To infinity.
173 round_toward_neg_infinity = 3 /// To negative infinity.
174 };
175
176 /**
177 * @brief Describes the denormalization for floating-point types.
178 *
179 * These values represent the presence or absence of a variable number
180 * of exponent bits. This type is used in the std::numeric_limits class.
181 */
182 enum float_denorm_style
183 {
184 /// Indeterminate at compile time whether denormalized values are allowed.
185 denorm_indeterminate = -1,
186 /// The type does not allow denormalized values.
187 denorm_absent = 0,
188 /// The type allows denormalized values.
189 denorm_present = 1
190 };
191
192 /**
193 * @brief Part of std::numeric_limits.
194 *
195 * The @c static @c const members are usable as integral constant
196 * expressions.
197 *
198 * @note This is a separate class for purposes of efficiency; you
199 * should only access these members as part of an instantiation
200 * of the std::numeric_limits class.
201 */
202 struct __numeric_limits_base
203 {
204 /** This will be true for all fundamental types (which have
205 specializations), and false for everything else. */
206 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_specialized = false;
207
208 /** The number of @c radix digits that be represented without change: for
209 integer types, the number of non-sign bits in the mantissa; for
210 floating types, the number of @c radix digits in the mantissa. */
211 static _GLIBCXX_USE_CONSTEXPRconstexpr int digits = 0;
212
213 /** The number of base 10 digits that can be represented without change. */
214 static _GLIBCXX_USE_CONSTEXPRconstexpr int digits10 = 0;
215
216#if __cplusplus201703L >= 201103L
217 /** The number of base 10 digits required to ensure that values which
218 differ are always differentiated. */
219 static constexpr int max_digits10 = 0;
220#endif
221
222 /** True if the type is signed. */
223 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_signed = false;
224
225 /** True if the type is integer. */
226 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_integer = false;
227
228 /** True if the type uses an exact representation. All integer types are
229 exact, but not all exact types are integer. For example, rational and
230 fixed-exponent representations are exact but not integer. */
231 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_exact = false;
232
233 /** For integer types, specifies the base of the representation. For
234 floating types, specifies the base of the exponent representation. */
235 static _GLIBCXX_USE_CONSTEXPRconstexpr int radix = 0;
236
237 /** The minimum negative integer such that @c radix raised to the power of
238 (one less than that integer) is a normalized floating point number. */
239 static _GLIBCXX_USE_CONSTEXPRconstexpr int min_exponent = 0;
240
241 /** The minimum negative integer such that 10 raised to that power is in
242 the range of normalized floating point numbers. */
243 static _GLIBCXX_USE_CONSTEXPRconstexpr int min_exponent10 = 0;
244
245 /** The maximum positive integer such that @c radix raised to the power of
246 (one less than that integer) is a representable finite floating point
247 number. */
248 static _GLIBCXX_USE_CONSTEXPRconstexpr int max_exponent = 0;
249
250 /** The maximum positive integer such that 10 raised to that power is in
251 the range of representable finite floating point numbers. */
252 static _GLIBCXX_USE_CONSTEXPRconstexpr int max_exponent10 = 0;
253
254 /** True if the type has a representation for positive infinity. */
255 static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_infinity = false;
256
257 /** True if the type has a representation for a quiet (non-signaling)
258 Not a Number. */
259 static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_quiet_NaN = false;
260
261 /** True if the type has a representation for a signaling
262 Not a Number. */
263 static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_signaling_NaN = false;
264
265 /** See std::float_denorm_style for more information. */
266 static _GLIBCXX_USE_CONSTEXPRconstexpr float_denorm_style has_denorm = denorm_absent;
267
268 /** True if loss of accuracy is detected as a denormalization loss,
269 rather than as an inexact result. */
270 static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_denorm_loss = false;
271
272 /** True if-and-only-if the type adheres to the IEC 559 standard, also
273 known as IEEE 754. (Only makes sense for floating point types.) */
274 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_iec559 = false;
275
276 /** True if the set of values representable by the type is
277 finite. All built-in types are bounded, this member would be
278 false for arbitrary precision types. */
279 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_bounded = false;
280
281 /** True if the type is @e modulo. A type is modulo if, for any
282 operation involving +, -, or * on values of that type whose
283 result would fall outside the range [min(),max()], the value
284 returned differs from the true value by an integer multiple of
285 max() - min() + 1. On most machines, this is false for floating
286 types, true for unsigned integers, and true for signed integers.
287 See PR22200 about signed integers. */
288 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_modulo = false;
289
290 /** True if trapping is implemented for this type. */
291 static _GLIBCXX_USE_CONSTEXPRconstexpr bool traps = false;
292
293 /** True if tininess is detected before rounding. (see IEC 559) */
294 static _GLIBCXX_USE_CONSTEXPRconstexpr bool tinyness_before = false;
295
296 /** See std::float_round_style for more information. This is only
297 meaningful for floating types; integer types will all be
298 round_toward_zero. */
299 static _GLIBCXX_USE_CONSTEXPRconstexpr float_round_style round_style =
300 round_toward_zero;
301 };
302
303 /**
304 * @brief Properties of fundamental types.
305 *
306 * This class allows a program to obtain information about the
307 * representation of a fundamental type on a given platform. For
308 * non-fundamental types, the functions will return 0 and the data
309 * members will all be @c false.
310 */
311 template<typename _Tp>
312 struct numeric_limits : public __numeric_limits_base
313 {
314 /** The minimum finite value, or for floating types with
315 denormalization, the minimum positive normalized value. */
316 static _GLIBCXX_CONSTEXPRconstexpr _Tp
317 min() _GLIBCXX_USE_NOEXCEPTnoexcept { return _Tp(); }
318
319 /** The maximum finite value. */
320 static _GLIBCXX_CONSTEXPRconstexpr _Tp
321 max() _GLIBCXX_USE_NOEXCEPTnoexcept { return _Tp(); }
322
323#if __cplusplus201703L >= 201103L
324 /** A finite value x such that there is no other finite value y
325 * where y < x. */
326 static constexpr _Tp
327 lowest() noexcept { return _Tp(); }
328#endif
329
330 /** The @e machine @e epsilon: the difference between 1 and the least
331 value greater than 1 that is representable. */
332 static _GLIBCXX_CONSTEXPRconstexpr _Tp
333 epsilon() _GLIBCXX_USE_NOEXCEPTnoexcept { return _Tp(); }
334
335 /** The maximum rounding error measurement (see LIA-1). */
336 static _GLIBCXX_CONSTEXPRconstexpr _Tp
337 round_error() _GLIBCXX_USE_NOEXCEPTnoexcept { return _Tp(); }
338
339 /** The representation of positive infinity, if @c has_infinity. */
340 static _GLIBCXX_CONSTEXPRconstexpr _Tp
341 infinity() _GLIBCXX_USE_NOEXCEPTnoexcept { return _Tp(); }
342
343 /** The representation of a quiet Not a Number,
344 if @c has_quiet_NaN. */
345 static _GLIBCXX_CONSTEXPRconstexpr _Tp
346 quiet_NaN() _GLIBCXX_USE_NOEXCEPTnoexcept { return _Tp(); }
347
348 /** The representation of a signaling Not a Number, if
349 @c has_signaling_NaN. */
350 static _GLIBCXX_CONSTEXPRconstexpr _Tp
351 signaling_NaN() _GLIBCXX_USE_NOEXCEPTnoexcept { return _Tp(); }
352
353 /** The minimum positive denormalized value. For types where
354 @c has_denorm is false, this is the minimum positive normalized
355 value. */
356 static _GLIBCXX_CONSTEXPRconstexpr _Tp
357 denorm_min() _GLIBCXX_USE_NOEXCEPTnoexcept { return _Tp(); }
358 };
359
360 // _GLIBCXX_RESOLVE_LIB_DEFECTS
361 // 559. numeric_limits<const T>
362
363 template<typename _Tp>
364 struct numeric_limits<const _Tp>
365 : public numeric_limits<_Tp> { };
366
367 template<typename _Tp>
368 struct numeric_limits<volatile _Tp>
369 : public numeric_limits<_Tp> { };
370
371 template<typename _Tp>
372 struct numeric_limits<const volatile _Tp>
373 : public numeric_limits<_Tp> { };
374
375 // Now there follow 16 explicit specializations. Yes, 16. Make sure
376 // you get the count right. (18 in C++11 mode, with char16_t and char32_t.)
377 // (+1 if char8_t is enabled.)
378
379 // _GLIBCXX_RESOLVE_LIB_DEFECTS
380 // 184. numeric_limits<bool> wording problems
381
382 /// numeric_limits<bool> specialization.
383 template<>
384 struct numeric_limits<bool>
385 {
386 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_specialized = true;
387
388 static _GLIBCXX_CONSTEXPRconstexpr bool
389 min() _GLIBCXX_USE_NOEXCEPTnoexcept { return false; }
390
391 static _GLIBCXX_CONSTEXPRconstexpr bool
392 max() _GLIBCXX_USE_NOEXCEPTnoexcept { return true; }
393
394#if __cplusplus201703L >= 201103L
395 static constexpr bool
396 lowest() noexcept { return min(); }
397#endif
398 static _GLIBCXX_USE_CONSTEXPRconstexpr int digits = 1;
399 static _GLIBCXX_USE_CONSTEXPRconstexpr int digits10 = 0;
400#if __cplusplus201703L >= 201103L
401 static constexpr int max_digits10 = 0;
402#endif
403 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_signed = false;
404 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_integer = true;
405 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_exact = true;
406 static _GLIBCXX_USE_CONSTEXPRconstexpr int radix = 2;
407
408 static _GLIBCXX_CONSTEXPRconstexpr bool
409 epsilon() _GLIBCXX_USE_NOEXCEPTnoexcept { return false; }
410
411 static _GLIBCXX_CONSTEXPRconstexpr bool
412 round_error() _GLIBCXX_USE_NOEXCEPTnoexcept { return false; }
413
414 static _GLIBCXX_USE_CONSTEXPRconstexpr int min_exponent = 0;
415 static _GLIBCXX_USE_CONSTEXPRconstexpr int min_exponent10 = 0;
416 static _GLIBCXX_USE_CONSTEXPRconstexpr int max_exponent = 0;
417 static _GLIBCXX_USE_CONSTEXPRconstexpr int max_exponent10 = 0;
418
419 static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_infinity = false;
420 static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_quiet_NaN = false;
421 static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_signaling_NaN = false;
422 static _GLIBCXX_USE_CONSTEXPRconstexpr float_denorm_style has_denorm
423 = denorm_absent;
424 static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_denorm_loss = false;
425
426 static _GLIBCXX_CONSTEXPRconstexpr bool
427 infinity() _GLIBCXX_USE_NOEXCEPTnoexcept { return false; }
428
429 static _GLIBCXX_CONSTEXPRconstexpr bool
430 quiet_NaN() _GLIBCXX_USE_NOEXCEPTnoexcept { return false; }
431
432 static _GLIBCXX_CONSTEXPRconstexpr bool
433 signaling_NaN() _GLIBCXX_USE_NOEXCEPTnoexcept { return false; }
434
435 static _GLIBCXX_CONSTEXPRconstexpr bool
436 denorm_min() _GLIBCXX_USE_NOEXCEPTnoexcept { return false; }
437
438 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_iec559 = false;
439 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_bounded = true;
440 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_modulo = false;
441
442 // It is not clear what it means for a boolean type to trap.
443 // This is a DR on the LWG issue list. Here, I use integer
444 // promotion semantics.
445 static _GLIBCXX_USE_CONSTEXPRconstexpr bool traps = __glibcxx_integral_trapstrue;
446 static _GLIBCXX_USE_CONSTEXPRconstexpr bool tinyness_before = false;
447 static _GLIBCXX_USE_CONSTEXPRconstexpr float_round_style round_style
448 = round_toward_zero;
449 };
450
451 /// numeric_limits<char> specialization.
452 template<>
453 struct numeric_limits<char>
454 {
455 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_specialized = true;
456
457 static _GLIBCXX_CONSTEXPRconstexpr char
458 min() _GLIBCXX_USE_NOEXCEPTnoexcept { return __glibcxx_min(char); }
459
460 static _GLIBCXX_CONSTEXPRconstexpr char
461 max() _GLIBCXX_USE_NOEXCEPTnoexcept { return __glibcxx_max(char); }
462
463#if __cplusplus201703L >= 201103L
464 static constexpr char
465 lowest() noexcept { return min(); }
466#endif
467
468 static _GLIBCXX_USE_CONSTEXPRconstexpr int digits = __glibcxx_digits (char);
469 static _GLIBCXX_USE_CONSTEXPRconstexpr int digits10 = __glibcxx_digits10 (char);
470#if __cplusplus201703L >= 201103L
471 static constexpr int max_digits10 = 0;
472#endif
473 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_signed = __glibcxx_signed (char);
474 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_integer = true;
475 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_exact = true;
476 static _GLIBCXX_USE_CONSTEXPRconstexpr int radix = 2;
477
478 static _GLIBCXX_CONSTEXPRconstexpr char
479 epsilon() _GLIBCXX_USE_NOEXCEPTnoexcept { return 0; }
480
481 static _GLIBCXX_CONSTEXPRconstexpr char
482 round_error() _GLIBCXX_USE_NOEXCEPTnoexcept { return 0; }
483
484 static _GLIBCXX_USE_CONSTEXPRconstexpr int min_exponent = 0;
485 static _GLIBCXX_USE_CONSTEXPRconstexpr int min_exponent10 = 0;
486 static _GLIBCXX_USE_CONSTEXPRconstexpr int max_exponent = 0;
487 static _GLIBCXX_USE_CONSTEXPRconstexpr int max_exponent10 = 0;
488
489 static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_infinity = false;
490 static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_quiet_NaN = false;
491 static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_signaling_NaN = false;
492 static _GLIBCXX_USE_CONSTEXPRconstexpr float_denorm_style has_denorm
493 = denorm_absent;
494 static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_denorm_loss = false;
495
496 static _GLIBCXX_CONSTEXPRconstexpr
497 char infinity() _GLIBCXX_USE_NOEXCEPTnoexcept { return char(); }
498
499 static _GLIBCXX_CONSTEXPRconstexpr char
500 quiet_NaN() _GLIBCXX_USE_NOEXCEPTnoexcept { return char(); }
501
502 static _GLIBCXX_CONSTEXPRconstexpr char
503 signaling_NaN() _GLIBCXX_USE_NOEXCEPTnoexcept { return char(); }
504
505 static _GLIBCXX_CONSTEXPRconstexpr char
506 denorm_min() _GLIBCXX_USE_NOEXCEPTnoexcept { return static_cast<char>(0); }
507
508 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_iec559 = false;
509 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_bounded = true;
510 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_modulo = !is_signed;
511
512 static _GLIBCXX_USE_CONSTEXPRconstexpr bool traps = __glibcxx_integral_trapstrue;
513 static _GLIBCXX_USE_CONSTEXPRconstexpr bool tinyness_before = false;
514 static _GLIBCXX_USE_CONSTEXPRconstexpr float_round_style round_style
515 = round_toward_zero;
516 };
517
518 /// numeric_limits<signed char> specialization.
519 template<>
520 struct numeric_limits<signed char>
521 {
522 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_specialized = true;
523
524 static _GLIBCXX_CONSTEXPRconstexpr signed char
525 min() _GLIBCXX_USE_NOEXCEPTnoexcept { return -__SCHAR_MAX__127 - 1; }
526
527 static _GLIBCXX_CONSTEXPRconstexpr signed char
528 max() _GLIBCXX_USE_NOEXCEPTnoexcept { return __SCHAR_MAX__127; }
529
530#if __cplusplus201703L >= 201103L
531 static constexpr signed char
532 lowest() noexcept { return min(); }
533#endif
534
535 static _GLIBCXX_USE_CONSTEXPRconstexpr int digits = __glibcxx_digits (signed char);
536 static _GLIBCXX_USE_CONSTEXPRconstexpr int digits10
537 = __glibcxx_digits10 (signed char);
538#if __cplusplus201703L >= 201103L
539 static constexpr int max_digits10 = 0;
540#endif
541 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_signed = true;
542 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_integer = true;
543 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_exact = true;
544 static _GLIBCXX_USE_CONSTEXPRconstexpr int radix = 2;
545
546 static _GLIBCXX_CONSTEXPRconstexpr signed char
547 epsilon() _GLIBCXX_USE_NOEXCEPTnoexcept { return 0; }
548
549 static _GLIBCXX_CONSTEXPRconstexpr signed char
550 round_error() _GLIBCXX_USE_NOEXCEPTnoexcept { return 0; }
551
552 static _GLIBCXX_USE_CONSTEXPRconstexpr int min_exponent = 0;
553 static _GLIBCXX_USE_CONSTEXPRconstexpr int min_exponent10 = 0;
554 static _GLIBCXX_USE_CONSTEXPRconstexpr int max_exponent = 0;
555 static _GLIBCXX_USE_CONSTEXPRconstexpr int max_exponent10 = 0;
556
557 static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_infinity = false;
558 static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_quiet_NaN = false;
559 static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_signaling_NaN = false;
560 static _GLIBCXX_USE_CONSTEXPRconstexpr float_denorm_style has_denorm
561 = denorm_absent;
562 static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_denorm_loss = false;
563
564 static _GLIBCXX_CONSTEXPRconstexpr signed char
565 infinity() _GLIBCXX_USE_NOEXCEPTnoexcept { return static_cast<signed char>(0); }
566
567 static _GLIBCXX_CONSTEXPRconstexpr signed char
568 quiet_NaN() _GLIBCXX_USE_NOEXCEPTnoexcept { return static_cast<signed char>(0); }
569
570 static _GLIBCXX_CONSTEXPRconstexpr signed char
571 signaling_NaN() _GLIBCXX_USE_NOEXCEPTnoexcept
572 { return static_cast<signed char>(0); }
573
574 static _GLIBCXX_CONSTEXPRconstexpr signed char
575 denorm_min() _GLIBCXX_USE_NOEXCEPTnoexcept
576 { return static_cast<signed char>(0); }
577
578 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_iec559 = false;
579 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_bounded = true;
580 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_modulo = false;
581
582 static _GLIBCXX_USE_CONSTEXPRconstexpr bool traps = __glibcxx_integral_trapstrue;
583 static _GLIBCXX_USE_CONSTEXPRconstexpr bool tinyness_before = false;
584 static _GLIBCXX_USE_CONSTEXPRconstexpr float_round_style round_style
585 = round_toward_zero;
586 };
587
588 /// numeric_limits<unsigned char> specialization.
589 template<>
590 struct numeric_limits<unsigned char>
591 {
592 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_specialized = true;
593
594 static _GLIBCXX_CONSTEXPRconstexpr unsigned char
595 min() _GLIBCXX_USE_NOEXCEPTnoexcept { return 0; }
596
597 static _GLIBCXX_CONSTEXPRconstexpr unsigned char
598 max() _GLIBCXX_USE_NOEXCEPTnoexcept { return __SCHAR_MAX__127 * 2U + 1; }
599
600#if __cplusplus201703L >= 201103L
601 static constexpr unsigned char
602 lowest() noexcept { return min(); }
603#endif
604
605 static _GLIBCXX_USE_CONSTEXPRconstexpr int digits
606 = __glibcxx_digits (unsigned char);
607 static _GLIBCXX_USE_CONSTEXPRconstexpr int digits10
608 = __glibcxx_digits10 (unsigned char);
609#if __cplusplus201703L >= 201103L
610 static constexpr int max_digits10 = 0;
611#endif
612 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_signed = false;
613 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_integer = true;
614 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_exact = true;
615 static _GLIBCXX_USE_CONSTEXPRconstexpr int radix = 2;
616
617 static _GLIBCXX_CONSTEXPRconstexpr unsigned char
618 epsilon() _GLIBCXX_USE_NOEXCEPTnoexcept { return 0; }
619
620 static _GLIBCXX_CONSTEXPRconstexpr unsigned char
621 round_error() _GLIBCXX_USE_NOEXCEPTnoexcept { return 0; }
622
623 static _GLIBCXX_USE_CONSTEXPRconstexpr int min_exponent = 0;
624 static _GLIBCXX_USE_CONSTEXPRconstexpr int min_exponent10 = 0;
625 static _GLIBCXX_USE_CONSTEXPRconstexpr int max_exponent = 0;
626 static _GLIBCXX_USE_CONSTEXPRconstexpr int max_exponent10 = 0;
627
628 static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_infinity = false;
629 static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_quiet_NaN = false;
630 static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_signaling_NaN = false;
631 static _GLIBCXX_USE_CONSTEXPRconstexpr float_denorm_style has_denorm
632 = denorm_absent;
633 static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_denorm_loss = false;
634
635 static _GLIBCXX_CONSTEXPRconstexpr unsigned char
636 infinity() _GLIBCXX_USE_NOEXCEPTnoexcept
637 { return static_cast<unsigned char>(0); }
638
639 static _GLIBCXX_CONSTEXPRconstexpr unsigned char
640 quiet_NaN() _GLIBCXX_USE_NOEXCEPTnoexcept
641 { return static_cast<unsigned char>(0); }
642
643 static _GLIBCXX_CONSTEXPRconstexpr unsigned char
644 signaling_NaN() _GLIBCXX_USE_NOEXCEPTnoexcept
645 { return static_cast<unsigned char>(0); }
646
647 static _GLIBCXX_CONSTEXPRconstexpr unsigned char
648 denorm_min() _GLIBCXX_USE_NOEXCEPTnoexcept
649 { return static_cast<unsigned char>(0); }
650
651 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_iec559 = false;
652 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_bounded = true;
653 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_modulo = true;
654
655 static _GLIBCXX_USE_CONSTEXPRconstexpr bool traps = __glibcxx_integral_trapstrue;
656 static _GLIBCXX_USE_CONSTEXPRconstexpr bool tinyness_before = false;
657 static _GLIBCXX_USE_CONSTEXPRconstexpr float_round_style round_style
658 = round_toward_zero;
659 };
660
661 /// numeric_limits<wchar_t> specialization.
662 template<>
663 struct numeric_limits<wchar_t>
664 {
665 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_specialized = true;
666
667 static _GLIBCXX_CONSTEXPRconstexpr wchar_t
668 min() _GLIBCXX_USE_NOEXCEPTnoexcept { return __glibcxx_min (wchar_t); }
669
670 static _GLIBCXX_CONSTEXPRconstexpr wchar_t
671 max() _GLIBCXX_USE_NOEXCEPTnoexcept { return __glibcxx_max (wchar_t); }
672
673#if __cplusplus201703L >= 201103L
674 static constexpr wchar_t
675 lowest() noexcept { return min(); }
676#endif
677
678 static _GLIBCXX_USE_CONSTEXPRconstexpr int digits = __glibcxx_digits (wchar_t);
679 static _GLIBCXX_USE_CONSTEXPRconstexpr int digits10
680 = __glibcxx_digits10 (wchar_t);
681#if __cplusplus201703L >= 201103L
682 static constexpr int max_digits10 = 0;
683#endif
684 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_signed = __glibcxx_signed (wchar_t);
685 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_integer = true;
686 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_exact = true;
687 static _GLIBCXX_USE_CONSTEXPRconstexpr int radix = 2;
688
689 static _GLIBCXX_CONSTEXPRconstexpr wchar_t
690 epsilon() _GLIBCXX_USE_NOEXCEPTnoexcept { return 0; }
691
692 static _GLIBCXX_CONSTEXPRconstexpr wchar_t
693 round_error() _GLIBCXX_USE_NOEXCEPTnoexcept { return 0; }
694
695 static _GLIBCXX_USE_CONSTEXPRconstexpr int min_exponent = 0;
696 static _GLIBCXX_USE_CONSTEXPRconstexpr int min_exponent10 = 0;
697 static _GLIBCXX_USE_CONSTEXPRconstexpr int max_exponent = 0;
698 static _GLIBCXX_USE_CONSTEXPRconstexpr int max_exponent10 = 0;
699
700 static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_infinity = false;
701 static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_quiet_NaN = false;
702 static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_signaling_NaN = false;
703 static _GLIBCXX_USE_CONSTEXPRconstexpr float_denorm_style has_denorm
704 = denorm_absent;
705 static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_denorm_loss = false;
706
707 static _GLIBCXX_CONSTEXPRconstexpr wchar_t
708 infinity() _GLIBCXX_USE_NOEXCEPTnoexcept { return wchar_t(); }
709
710 static _GLIBCXX_CONSTEXPRconstexpr wchar_t
711 quiet_NaN() _GLIBCXX_USE_NOEXCEPTnoexcept { return wchar_t(); }
712
713 static _GLIBCXX_CONSTEXPRconstexpr wchar_t
714 signaling_NaN() _GLIBCXX_USE_NOEXCEPTnoexcept { return wchar_t(); }
715
716 static _GLIBCXX_CONSTEXPRconstexpr wchar_t
717 denorm_min() _GLIBCXX_USE_NOEXCEPTnoexcept { return wchar_t(); }
718
719 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_iec559 = false;
720 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_bounded = true;
721 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_modulo = !is_signed;
722
723 static _GLIBCXX_USE_CONSTEXPRconstexpr bool traps = __glibcxx_integral_trapstrue;
724 static _GLIBCXX_USE_CONSTEXPRconstexpr bool tinyness_before = false;
725 static _GLIBCXX_USE_CONSTEXPRconstexpr float_round_style round_style
726 = round_toward_zero;
727 };
728
729#if _GLIBCXX_USE_CHAR8_T
730 /// numeric_limits<char8_t> specialization.
731 template<>
732 struct numeric_limits<char8_t>
733 {
734 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_specialized = true;
735
736 static _GLIBCXX_CONSTEXPRconstexpr char8_t
737 min() _GLIBCXX_USE_NOEXCEPTnoexcept { return __glibcxx_min (char8_t); }
738
739 static _GLIBCXX_CONSTEXPRconstexpr char8_t
740 max() _GLIBCXX_USE_NOEXCEPTnoexcept { return __glibcxx_max (char8_t); }
741
742 static _GLIBCXX_CONSTEXPRconstexpr char8_t
743 lowest() _GLIBCXX_USE_NOEXCEPTnoexcept { return min(); }
744
745 static _GLIBCXX_USE_CONSTEXPRconstexpr int digits = __glibcxx_digits (char8_t);
746 static _GLIBCXX_USE_CONSTEXPRconstexpr int digits10 = __glibcxx_digits10 (char8_t);
747 static _GLIBCXX_USE_CONSTEXPRconstexpr int max_digits10 = 0;
748 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_signed = __glibcxx_signed (char8_t);
749 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_integer = true;
750 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_exact = true;
751 static _GLIBCXX_USE_CONSTEXPRconstexpr int radix = 2;
752
753 static _GLIBCXX_CONSTEXPRconstexpr char8_t
754 epsilon() _GLIBCXX_USE_NOEXCEPTnoexcept { return 0; }
755
756 static _GLIBCXX_CONSTEXPRconstexpr char8_t
757 round_error() _GLIBCXX_USE_NOEXCEPTnoexcept { return 0; }
758
759 static _GLIBCXX_USE_CONSTEXPRconstexpr int min_exponent = 0;
760 static _GLIBCXX_USE_CONSTEXPRconstexpr int min_exponent10 = 0;
761 static _GLIBCXX_USE_CONSTEXPRconstexpr int max_exponent = 0;
762 static _GLIBCXX_USE_CONSTEXPRconstexpr int max_exponent10 = 0;
763
764 static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_infinity = false;
765 static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_quiet_NaN = false;
766 static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_signaling_NaN = false;
767 static _GLIBCXX_USE_CONSTEXPRconstexpr float_denorm_style has_denorm
768 = denorm_absent;
769 static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_denorm_loss = false;
770
771 static _GLIBCXX_CONSTEXPRconstexpr char8_t
772 infinity() _GLIBCXX_USE_NOEXCEPTnoexcept { return char8_t(); }
773
774 static _GLIBCXX_CONSTEXPRconstexpr char8_t
775 quiet_NaN() _GLIBCXX_USE_NOEXCEPTnoexcept { return char8_t(); }
776
777 static _GLIBCXX_CONSTEXPRconstexpr char8_t
778 signaling_NaN() _GLIBCXX_USE_NOEXCEPTnoexcept { return char8_t(); }
779
780 static _GLIBCXX_CONSTEXPRconstexpr char8_t
781 denorm_min() _GLIBCXX_USE_NOEXCEPTnoexcept { return char8_t(); }
782
783 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_iec559 = false;
784 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_bounded = true;
785 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_modulo = !is_signed;
786
787 static _GLIBCXX_USE_CONSTEXPRconstexpr bool traps = __glibcxx_integral_trapstrue;
788 static _GLIBCXX_USE_CONSTEXPRconstexpr bool tinyness_before = false;
789 static _GLIBCXX_USE_CONSTEXPRconstexpr float_round_style round_style
790 = round_toward_zero;
791 };
792#endif
793
794#if __cplusplus201703L >= 201103L
795 /// numeric_limits<char16_t> specialization.
796 template<>
797 struct numeric_limits<char16_t>
798 {
799 static constexpr bool is_specialized = true;
800
801 static constexpr char16_t
802 min() noexcept { return __glibcxx_min (char16_t); }
803
804 static constexpr char16_t
805 max() noexcept { return __glibcxx_max (char16_t); }
806
807 static constexpr char16_t
808 lowest() noexcept { return min(); }
809
810 static constexpr int digits = __glibcxx_digits (char16_t);
811 static constexpr int digits10 = __glibcxx_digits10 (char16_t);
812 static constexpr int max_digits10 = 0;
813 static constexpr bool is_signed = __glibcxx_signed (char16_t);
814 static constexpr bool is_integer = true;
815 static constexpr bool is_exact = true;
816 static constexpr int radix = 2;
817
818 static constexpr char16_t
819 epsilon() noexcept { return 0; }
820
821 static constexpr char16_t
822 round_error() noexcept { return 0; }
823
824 static constexpr int min_exponent = 0;
825 static constexpr int min_exponent10 = 0;
826 static constexpr int max_exponent = 0;
827 static constexpr int max_exponent10 = 0;
828
829 static constexpr bool has_infinity = false;
830 static constexpr bool has_quiet_NaN = false;
831 static constexpr bool has_signaling_NaN = false;
832 static constexpr float_denorm_style has_denorm = denorm_absent;
833 static constexpr bool has_denorm_loss = false;
834
835 static constexpr char16_t
836 infinity() noexcept { return char16_t(); }
837
838 static constexpr char16_t
839 quiet_NaN() noexcept { return char16_t(); }
840
841 static constexpr char16_t
842 signaling_NaN() noexcept { return char16_t(); }
843
844 static constexpr char16_t
845 denorm_min() noexcept { return char16_t(); }
846
847 static constexpr bool is_iec559 = false;
848 static constexpr bool is_bounded = true;
849 static constexpr bool is_modulo = !is_signed;
850
851 static constexpr bool traps = __glibcxx_integral_trapstrue;
852 static constexpr bool tinyness_before = false;
853 static constexpr float_round_style round_style = round_toward_zero;
854 };
855
856 /// numeric_limits<char32_t> specialization.
857 template<>
858 struct numeric_limits<char32_t>
859 {
860 static constexpr bool is_specialized = true;
861
862 static constexpr char32_t
863 min() noexcept { return __glibcxx_min (char32_t); }
864
865 static constexpr char32_t
866 max() noexcept { return __glibcxx_max (char32_t); }
867
868 static constexpr char32_t
869 lowest() noexcept { return min(); }
870
871 static constexpr int digits = __glibcxx_digits (char32_t);
872 static constexpr int digits10 = __glibcxx_digits10 (char32_t);
873 static constexpr int max_digits10 = 0;
874 static constexpr bool is_signed = __glibcxx_signed (char32_t);
875 static constexpr bool is_integer = true;
876 static constexpr bool is_exact = true;
877 static constexpr int radix = 2;
878
879 static constexpr char32_t
880 epsilon() noexcept { return 0; }
881
882 static constexpr char32_t
883 round_error() noexcept { return 0; }
884
885 static constexpr int min_exponent = 0;
886 static constexpr int min_exponent10 = 0;
887 static constexpr int max_exponent = 0;
888 static constexpr int max_exponent10 = 0;
889
890 static constexpr bool has_infinity = false;
891 static constexpr bool has_quiet_NaN = false;
892 static constexpr bool has_signaling_NaN = false;
893 static constexpr float_denorm_style has_denorm = denorm_absent;
894 static constexpr bool has_denorm_loss = false;
895
896 static constexpr char32_t
897 infinity() noexcept { return char32_t(); }
898
899 static constexpr char32_t
900 quiet_NaN() noexcept { return char32_t(); }
901
902 static constexpr char32_t
903 signaling_NaN() noexcept { return char32_t(); }
904
905 static constexpr char32_t
906 denorm_min() noexcept { return char32_t(); }
907
908 static constexpr bool is_iec559 = false;
909 static constexpr bool is_bounded = true;
910 static constexpr bool is_modulo = !is_signed;
911
912 static constexpr bool traps = __glibcxx_integral_trapstrue;
913 static constexpr bool tinyness_before = false;
914 static constexpr float_round_style round_style = round_toward_zero;
915 };
916#endif
917
918 /// numeric_limits<short> specialization.
919 template<>
920 struct numeric_limits<short>
921 {
922 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_specialized = true;
923
924 static _GLIBCXX_CONSTEXPRconstexpr short
925 min() _GLIBCXX_USE_NOEXCEPTnoexcept { return -__SHRT_MAX__32767 - 1; }
926
927 static _GLIBCXX_CONSTEXPRconstexpr short
928 max() _GLIBCXX_USE_NOEXCEPTnoexcept { return __SHRT_MAX__32767; }
929
930#if __cplusplus201703L >= 201103L
931 static constexpr short
932 lowest() noexcept { return min(); }
933#endif
934
935 static _GLIBCXX_USE_CONSTEXPRconstexpr int digits = __glibcxx_digits (short);
936 static _GLIBCXX_USE_CONSTEXPRconstexpr int digits10 = __glibcxx_digits10 (short);
937#if __cplusplus201703L >= 201103L
938 static constexpr int max_digits10 = 0;
939#endif
940 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_signed = true;
941 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_integer = true;
942 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_exact = true;
943 static _GLIBCXX_USE_CONSTEXPRconstexpr int radix = 2;
944
945 static _GLIBCXX_CONSTEXPRconstexpr short
946 epsilon() _GLIBCXX_USE_NOEXCEPTnoexcept { return 0; }
947
948 static _GLIBCXX_CONSTEXPRconstexpr short
949 round_error() _GLIBCXX_USE_NOEXCEPTnoexcept { return 0; }
950
951 static _GLIBCXX_USE_CONSTEXPRconstexpr int min_exponent = 0;
952 static _GLIBCXX_USE_CONSTEXPRconstexpr int min_exponent10 = 0;
953 static _GLIBCXX_USE_CONSTEXPRconstexpr int max_exponent = 0;
954 static _GLIBCXX_USE_CONSTEXPRconstexpr int max_exponent10 = 0;
955
956 static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_infinity = false;
957 static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_quiet_NaN = false;
958 static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_signaling_NaN = false;
959 static _GLIBCXX_USE_CONSTEXPRconstexpr float_denorm_style has_denorm
960 = denorm_absent;
961 static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_denorm_loss = false;
962
963 static _GLIBCXX_CONSTEXPRconstexpr short
964 infinity() _GLIBCXX_USE_NOEXCEPTnoexcept { return short(); }
965
966 static _GLIBCXX_CONSTEXPRconstexpr short
967 quiet_NaN() _GLIBCXX_USE_NOEXCEPTnoexcept { return short(); }
968
969 static _GLIBCXX_CONSTEXPRconstexpr short
970 signaling_NaN() _GLIBCXX_USE_NOEXCEPTnoexcept { return short(); }
971
972 static _GLIBCXX_CONSTEXPRconstexpr short
973 denorm_min() _GLIBCXX_USE_NOEXCEPTnoexcept { return short(); }
974
975 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_iec559 = false;
976 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_bounded = true;
977 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_modulo = false;
978
979 static _GLIBCXX_USE_CONSTEXPRconstexpr bool traps = __glibcxx_integral_trapstrue;
980 static _GLIBCXX_USE_CONSTEXPRconstexpr bool tinyness_before = false;
981 static _GLIBCXX_USE_CONSTEXPRconstexpr float_round_style round_style
982 = round_toward_zero;
983 };
984
985 /// numeric_limits<unsigned short> specialization.
986 template<>
987 struct numeric_limits<unsigned short>
988 {
989 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_specialized = true;
990
991 static _GLIBCXX_CONSTEXPRconstexpr unsigned short
992 min() _GLIBCXX_USE_NOEXCEPTnoexcept { return 0; }
993
994 static _GLIBCXX_CONSTEXPRconstexpr unsigned short
995 max() _GLIBCXX_USE_NOEXCEPTnoexcept { return __SHRT_MAX__32767 * 2U + 1; }
996
997#if __cplusplus201703L >= 201103L
998 static constexpr unsigned short
999 lowest() noexcept { return min(); }
1000#endif
1001
1002 static _GLIBCXX_USE_CONSTEXPRconstexpr int digits
1003 = __glibcxx_digits (unsigned short);
1004 static _GLIBCXX_USE_CONSTEXPRconstexpr int digits10
1005 = __glibcxx_digits10 (unsigned short);
1006#if __cplusplus201703L >= 201103L
1007 static constexpr int max_digits10 = 0;
1008#endif
1009 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_signed = false;
1010 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_integer = true;
1011 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_exact = true;
1012 static _GLIBCXX_USE_CONSTEXPRconstexpr int radix = 2;
1013
1014 static _GLIBCXX_CONSTEXPRconstexpr unsigned short
1015 epsilon() _GLIBCXX_USE_NOEXCEPTnoexcept { return 0; }
1016
1017 static _GLIBCXX_CONSTEXPRconstexpr unsigned short
1018 round_error() _GLIBCXX_USE_NOEXCEPTnoexcept { return 0; }
1019
1020 static _GLIBCXX_USE_CONSTEXPRconstexpr int min_exponent = 0;
1021 static _GLIBCXX_USE_CONSTEXPRconstexpr int min_exponent10 = 0;
1022 static _GLIBCXX_USE_CONSTEXPRconstexpr int max_exponent = 0;
1023 static _GLIBCXX_USE_CONSTEXPRconstexpr int max_exponent10 = 0;
1024
1025 static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_infinity = false;
1026 static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_quiet_NaN = false;
1027 static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_signaling_NaN = false;
1028 static _GLIBCXX_USE_CONSTEXPRconstexpr float_denorm_style has_denorm
1029 = denorm_absent;
1030 static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_denorm_loss = false;
1031
1032 static _GLIBCXX_CONSTEXPRconstexpr unsigned short
1033 infinity() _GLIBCXX_USE_NOEXCEPTnoexcept
1034 { return static_cast<unsigned short>(0); }
1035
1036 static _GLIBCXX_CONSTEXPRconstexpr unsigned short
1037 quiet_NaN() _GLIBCXX_USE_NOEXCEPTnoexcept
1038 { return static_cast<unsigned short>(0); }
1039
1040 static _GLIBCXX_CONSTEXPRconstexpr unsigned short
1041 signaling_NaN() _GLIBCXX_USE_NOEXCEPTnoexcept
1042 { return static_cast<unsigned short>(0); }
1043
1044 static _GLIBCXX_CONSTEXPRconstexpr unsigned short
1045 denorm_min() _GLIBCXX_USE_NOEXCEPTnoexcept
1046 { return static_cast<unsigned short>(0); }
1047
1048 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_iec559 = false;
1049 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_bounded = true;
1050 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_modulo = true;
1051
1052 static _GLIBCXX_USE_CONSTEXPRconstexpr bool traps = __glibcxx_integral_trapstrue;
1053 static _GLIBCXX_USE_CONSTEXPRconstexpr bool tinyness_before = false;
1054 static _GLIBCXX_USE_CONSTEXPRconstexpr float_round_style round_style
1055 = round_toward_zero;
1056 };
1057
1058 /// numeric_limits<int> specialization.
1059 template<>
1060 struct numeric_limits<int>
1061 {
1062 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_specialized = true;
1063
1064 static _GLIBCXX_CONSTEXPRconstexpr int
1065 min() _GLIBCXX_USE_NOEXCEPTnoexcept { return -__INT_MAX__2147483647 - 1; }
1066
1067 static _GLIBCXX_CONSTEXPRconstexpr int
1068 max() _GLIBCXX_USE_NOEXCEPTnoexcept { return __INT_MAX__2147483647; }
1069
1070#if __cplusplus201703L >= 201103L
1071 static constexpr int
1072 lowest() noexcept { return min(); }
1073#endif
1074
1075 static _GLIBCXX_USE_CONSTEXPRconstexpr int digits = __glibcxx_digits (int);
1076 static _GLIBCXX_USE_CONSTEXPRconstexpr int digits10 = __glibcxx_digits10 (int);
1077#if __cplusplus201703L >= 201103L
1078 static constexpr int max_digits10 = 0;
1079#endif
1080 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_signed = true;
1081 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_integer = true;
1082 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_exact = true;
1083 static _GLIBCXX_USE_CONSTEXPRconstexpr int radix = 2;
1084
1085 static _GLIBCXX_CONSTEXPRconstexpr int
1086 epsilon() _GLIBCXX_USE_NOEXCEPTnoexcept { return 0; }
1087
1088 static _GLIBCXX_CONSTEXPRconstexpr int
1089 round_error() _GLIBCXX_USE_NOEXCEPTnoexcept { return 0; }
1090
1091 static _GLIBCXX_USE_CONSTEXPRconstexpr int min_exponent = 0;
1092 static _GLIBCXX_USE_CONSTEXPRconstexpr int min_exponent10 = 0;
1093 static _GLIBCXX_USE_CONSTEXPRconstexpr int max_exponent = 0;
1094 static _GLIBCXX_USE_CONSTEXPRconstexpr int max_exponent10 = 0;
1095
1096 static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_infinity = false;
1097 static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_quiet_NaN = false;
1098 static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_signaling_NaN = false;
1099 static _GLIBCXX_USE_CONSTEXPRconstexpr float_denorm_style has_denorm
1100 = denorm_absent;
1101 static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_denorm_loss = false;
1102
1103 static _GLIBCXX_CONSTEXPRconstexpr int
1104 infinity() _GLIBCXX_USE_NOEXCEPTnoexcept { return static_cast<int>(0); }
1105
1106 static _GLIBCXX_CONSTEXPRconstexpr int
1107 quiet_NaN() _GLIBCXX_USE_NOEXCEPTnoexcept { return static_cast<int>(0); }
1108
1109 static _GLIBCXX_CONSTEXPRconstexpr int
1110 signaling_NaN() _GLIBCXX_USE_NOEXCEPTnoexcept { return static_cast<int>(0); }
1111
1112 static _GLIBCXX_CONSTEXPRconstexpr int
1113 denorm_min() _GLIBCXX_USE_NOEXCEPTnoexcept { return static_cast<int>(0); }
1114
1115 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_iec559 = false;
1116 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_bounded = true;
1117 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_modulo = false;
1118
1119 static _GLIBCXX_USE_CONSTEXPRconstexpr bool traps = __glibcxx_integral_trapstrue;
1120 static _GLIBCXX_USE_CONSTEXPRconstexpr bool tinyness_before = false;
1121 static _GLIBCXX_USE_CONSTEXPRconstexpr float_round_style round_style
1122 = round_toward_zero;
1123 };
1124
1125 /// numeric_limits<unsigned int> specialization.
1126 template<>
1127 struct numeric_limits<unsigned int>
1128 {
1129 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_specialized = true;
1130
1131 static _GLIBCXX_CONSTEXPRconstexpr unsigned int
1132 min() _GLIBCXX_USE_NOEXCEPTnoexcept { return 0; }
1133
1134 static _GLIBCXX_CONSTEXPRconstexpr unsigned int
1135 max() _GLIBCXX_USE_NOEXCEPTnoexcept { return __INT_MAX__2147483647 * 2U + 1; }
1136
1137#if __cplusplus201703L >= 201103L
1138 static constexpr unsigned int
1139 lowest() noexcept { return min(); }
1140#endif
1141
1142 static _GLIBCXX_USE_CONSTEXPRconstexpr int digits
1143 = __glibcxx_digits (unsigned int);
1144 static _GLIBCXX_USE_CONSTEXPRconstexpr int digits10
1145 = __glibcxx_digits10 (unsigned int);
1146#if __cplusplus201703L >= 201103L
1147 static constexpr int max_digits10 = 0;
1148#endif
1149 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_signed = false;
1150 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_integer = true;
1151 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_exact = true;
1152 static _GLIBCXX_USE_CONSTEXPRconstexpr int radix = 2;
1153
1154 static _GLIBCXX_CONSTEXPRconstexpr unsigned int
1155 epsilon() _GLIBCXX_USE_NOEXCEPTnoexcept { return 0; }
1156
1157 static _GLIBCXX_CONSTEXPRconstexpr unsigned int
1158 round_error() _GLIBCXX_USE_NOEXCEPTnoexcept { return 0; }
1159
1160 static _GLIBCXX_USE_CONSTEXPRconstexpr int min_exponent = 0;
1161 static _GLIBCXX_USE_CONSTEXPRconstexpr int min_exponent10 = 0;
1162 static _GLIBCXX_USE_CONSTEXPRconstexpr int max_exponent = 0;
1163 static _GLIBCXX_USE_CONSTEXPRconstexpr int max_exponent10 = 0;
1164
1165 static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_infinity = false;
1166 static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_quiet_NaN = false;
1167 static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_signaling_NaN = false;
1168 static _GLIBCXX_USE_CONSTEXPRconstexpr float_denorm_style has_denorm
1169 = denorm_absent;
1170 static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_denorm_loss = false;
1171
1172 static _GLIBCXX_CONSTEXPRconstexpr unsigned int
1173 infinity() _GLIBCXX_USE_NOEXCEPTnoexcept { return static_cast<unsigned int>(0); }
1174
1175 static _GLIBCXX_CONSTEXPRconstexpr unsigned int
1176 quiet_NaN() _GLIBCXX_USE_NOEXCEPTnoexcept
1177 { return static_cast<unsigned int>(0); }
1178
1179 static _GLIBCXX_CONSTEXPRconstexpr unsigned int
1180 signaling_NaN() _GLIBCXX_USE_NOEXCEPTnoexcept
1181 { return static_cast<unsigned int>(0); }
1182
1183 static _GLIBCXX_CONSTEXPRconstexpr unsigned int
1184 denorm_min() _GLIBCXX_USE_NOEXCEPTnoexcept
1185 { return static_cast<unsigned int>(0); }
1186
1187 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_iec559 = false;
1188 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_bounded = true;
1189 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_modulo = true;
1190
1191 static _GLIBCXX_USE_CONSTEXPRconstexpr bool traps = __glibcxx_integral_trapstrue;
1192 static _GLIBCXX_USE_CONSTEXPRconstexpr bool tinyness_before = false;
1193 static _GLIBCXX_USE_CONSTEXPRconstexpr float_round_style round_style
1194 = round_toward_zero;
1195 };
1196
1197 /// numeric_limits<long> specialization.
1198 template<>
1199 struct numeric_limits<long>
1200 {
1201 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_specialized = true;
1202
1203 static _GLIBCXX_CONSTEXPRconstexpr long
1204 min() _GLIBCXX_USE_NOEXCEPTnoexcept { return -__LONG_MAX__9223372036854775807L - 1; }
1205
1206 static _GLIBCXX_CONSTEXPRconstexpr long
1207 max() _GLIBCXX_USE_NOEXCEPTnoexcept { return __LONG_MAX__9223372036854775807L; }
1208
1209#if __cplusplus201703L >= 201103L
1210 static constexpr long
1211 lowest() noexcept { return min(); }
1212#endif
1213
1214 static _GLIBCXX_USE_CONSTEXPRconstexpr int digits = __glibcxx_digits (long);
1215 static _GLIBCXX_USE_CONSTEXPRconstexpr int digits10 = __glibcxx_digits10 (long);
1216#if __cplusplus201703L >= 201103L
1217 static constexpr int max_digits10 = 0;
1218#endif
1219 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_signed = true;
1220 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_integer = true;
1221 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_exact = true;
1222 static _GLIBCXX_USE_CONSTEXPRconstexpr int radix = 2;
1223
1224 static _GLIBCXX_CONSTEXPRconstexpr long
1225 epsilon() _GLIBCXX_USE_NOEXCEPTnoexcept { return 0; }
1226
1227 static _GLIBCXX_CONSTEXPRconstexpr long
1228 round_error() _GLIBCXX_USE_NOEXCEPTnoexcept { return 0; }
1229
1230 static _GLIBCXX_USE_CONSTEXPRconstexpr int min_exponent = 0;
1231 static _GLIBCXX_USE_CONSTEXPRconstexpr int min_exponent10 = 0;
1232 static _GLIBCXX_USE_CONSTEXPRconstexpr int max_exponent = 0;
1233 static _GLIBCXX_USE_CONSTEXPRconstexpr int max_exponent10 = 0;
1234
1235 static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_infinity = false;
1236 static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_quiet_NaN = false;
1237 static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_signaling_NaN = false;
1238 static _GLIBCXX_USE_CONSTEXPRconstexpr float_denorm_style has_denorm
1239 = denorm_absent;
1240 static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_denorm_loss = false;
1241
1242 static _GLIBCXX_CONSTEXPRconstexpr long
1243 infinity() _GLIBCXX_USE_NOEXCEPTnoexcept { return static_cast<long>(0); }
1244
1245 static _GLIBCXX_CONSTEXPRconstexpr long
1246 quiet_NaN() _GLIBCXX_USE_NOEXCEPTnoexcept { return static_cast<long>(0); }
1247
1248 static _GLIBCXX_CONSTEXPRconstexpr long
1249 signaling_NaN() _GLIBCXX_USE_NOEXCEPTnoexcept { return static_cast<long>(0); }
1250
1251 static _GLIBCXX_CONSTEXPRconstexpr long
1252 denorm_min() _GLIBCXX_USE_NOEXCEPTnoexcept { return static_cast<long>(0); }
1253
1254 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_iec559 = false;
1255 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_bounded = true;
1256 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_modulo = false;
1257
1258 static _GLIBCXX_USE_CONSTEXPRconstexpr bool traps = __glibcxx_integral_trapstrue;
1259 static _GLIBCXX_USE_CONSTEXPRconstexpr bool tinyness_before = false;
1260 static _GLIBCXX_USE_CONSTEXPRconstexpr float_round_style round_style
1261 = round_toward_zero;
1262 };
1263
1264 /// numeric_limits<unsigned long> specialization.
1265 template<>
1266 struct numeric_limits<unsigned long>
1267 {
1268 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_specialized = true;
1269
1270 static _GLIBCXX_CONSTEXPRconstexpr unsigned long
1271 min() _GLIBCXX_USE_NOEXCEPTnoexcept { return 0; }
1272
1273 static _GLIBCXX_CONSTEXPRconstexpr unsigned long
1274 max() _GLIBCXX_USE_NOEXCEPTnoexcept { return __LONG_MAX__9223372036854775807L * 2UL + 1; }
11
Returning the value 18446744073709551615
1275
1276#if __cplusplus201703L >= 201103L
1277 static constexpr unsigned long
1278 lowest() noexcept { return min(); }
1279#endif
1280
1281 static _GLIBCXX_USE_CONSTEXPRconstexpr int digits
1282 = __glibcxx_digits (unsigned long);
1283 static _GLIBCXX_USE_CONSTEXPRconstexpr int digits10
1284 = __glibcxx_digits10 (unsigned long);
1285#if __cplusplus201703L >= 201103L
1286 static constexpr int max_digits10 = 0;
1287#endif
1288 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_signed = false;
1289 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_integer = true;
1290 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_exact = true;
1291 static _GLIBCXX_USE_CONSTEXPRconstexpr int radix = 2;
1292
1293 static _GLIBCXX_CONSTEXPRconstexpr unsigned long
1294 epsilon() _GLIBCXX_USE_NOEXCEPTnoexcept { return 0; }
1295
1296 static _GLIBCXX_CONSTEXPRconstexpr unsigned long
1297 round_error() _GLIBCXX_USE_NOEXCEPTnoexcept { return 0; }
1298
1299 static _GLIBCXX_USE_CONSTEXPRconstexpr int min_exponent = 0;
1300 static _GLIBCXX_USE_CONSTEXPRconstexpr int min_exponent10 = 0;
1301 static _GLIBCXX_USE_CONSTEXPRconstexpr int max_exponent = 0;
1302 static _GLIBCXX_USE_CONSTEXPRconstexpr int max_exponent10 = 0;
1303
1304 static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_infinity = false;
1305 static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_quiet_NaN = false;
1306 static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_signaling_NaN = false;
1307 static _GLIBCXX_USE_CONSTEXPRconstexpr float_denorm_style has_denorm
1308 = denorm_absent;
1309 static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_denorm_loss = false;
1310
1311 static _GLIBCXX_CONSTEXPRconstexpr unsigned long
1312 infinity() _GLIBCXX_USE_NOEXCEPTnoexcept
1313 { return static_cast<unsigned long>(0); }
1314
1315 static _GLIBCXX_CONSTEXPRconstexpr unsigned long
1316 quiet_NaN() _GLIBCXX_USE_NOEXCEPTnoexcept
1317 { return static_cast<unsigned long>(0); }
1318
1319 static _GLIBCXX_CONSTEXPRconstexpr unsigned long
1320 signaling_NaN() _GLIBCXX_USE_NOEXCEPTnoexcept
1321 { return static_cast<unsigned long>(0); }
1322
1323 static _GLIBCXX_CONSTEXPRconstexpr unsigned long
1324 denorm_min() _GLIBCXX_USE_NOEXCEPTnoexcept
1325 { return static_cast<unsigned long>(0); }
1326
1327 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_iec559 = false;
1328 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_bounded = true;
1329 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_modulo = true;
1330
1331 static _GLIBCXX_USE_CONSTEXPRconstexpr bool traps = __glibcxx_integral_trapstrue;
1332 static _GLIBCXX_USE_CONSTEXPRconstexpr bool tinyness_before = false;
1333 static _GLIBCXX_USE_CONSTEXPRconstexpr float_round_style round_style
1334 = round_toward_zero;
1335 };
1336
1337 /// numeric_limits<long long> specialization.
1338 template<>
1339 struct numeric_limits<long long>
1340 {
1341 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_specialized = true;
1342
1343 static _GLIBCXX_CONSTEXPRconstexpr long long
1344 min() _GLIBCXX_USE_NOEXCEPTnoexcept { return -__LONG_LONG_MAX__9223372036854775807LL - 1; }
1345
1346 static _GLIBCXX_CONSTEXPRconstexpr long long
1347 max() _GLIBCXX_USE_NOEXCEPTnoexcept { return __LONG_LONG_MAX__9223372036854775807LL; }
1348
1349#if __cplusplus201703L >= 201103L
1350 static constexpr long long
1351 lowest() noexcept { return min(); }
1352#endif
1353
1354 static _GLIBCXX_USE_CONSTEXPRconstexpr int digits
1355 = __glibcxx_digits (long long);
1356 static _GLIBCXX_USE_CONSTEXPRconstexpr int digits10
1357 = __glibcxx_digits10 (long long);
1358#if __cplusplus201703L >= 201103L
1359 static constexpr int max_digits10 = 0;
1360#endif
1361 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_signed = true;
1362 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_integer = true;
1363 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_exact = true;
1364 static _GLIBCXX_USE_CONSTEXPRconstexpr int radix = 2;
1365
1366 static _GLIBCXX_CONSTEXPRconstexpr long long
1367 epsilon() _GLIBCXX_USE_NOEXCEPTnoexcept { return 0; }
1368
1369 static _GLIBCXX_CONSTEXPRconstexpr long long
1370 round_error() _GLIBCXX_USE_NOEXCEPTnoexcept { return 0; }
1371
1372 static _GLIBCXX_USE_CONSTEXPRconstexpr int min_exponent = 0;
1373 static _GLIBCXX_USE_CONSTEXPRconstexpr int min_exponent10 = 0;
1374 static _GLIBCXX_USE_CONSTEXPRconstexpr int max_exponent = 0;
1375 static _GLIBCXX_USE_CONSTEXPRconstexpr int max_exponent10 = 0;
1376
1377 static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_infinity = false;
1378 static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_quiet_NaN = false;
1379 static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_signaling_NaN = false;
1380 static _GLIBCXX_USE_CONSTEXPRconstexpr float_denorm_style has_denorm
1381 = denorm_absent;
1382 static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_denorm_loss = false;
1383
1384 static _GLIBCXX_CONSTEXPRconstexpr long long
1385 infinity() _GLIBCXX_USE_NOEXCEPTnoexcept { return static_cast<long long>(0); }
1386
1387 static _GLIBCXX_CONSTEXPRconstexpr long long
1388 quiet_NaN() _GLIBCXX_USE_NOEXCEPTnoexcept { return static_cast<long long>(0); }
1389
1390 static _GLIBCXX_CONSTEXPRconstexpr long long
1391 signaling_NaN() _GLIBCXX_USE_NOEXCEPTnoexcept
1392 { return static_cast<long long>(0); }
1393
1394 static _GLIBCXX_CONSTEXPRconstexpr long long
1395 denorm_min() _GLIBCXX_USE_NOEXCEPTnoexcept { return static_cast<long long>(0); }
1396
1397 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_iec559 = false;
1398 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_bounded = true;
1399 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_modulo = false;
1400
1401 static _GLIBCXX_USE_CONSTEXPRconstexpr bool traps = __glibcxx_integral_trapstrue;
1402 static _GLIBCXX_USE_CONSTEXPRconstexpr bool tinyness_before = false;
1403 static _GLIBCXX_USE_CONSTEXPRconstexpr float_round_style round_style
1404 = round_toward_zero;
1405 };
1406
1407 /// numeric_limits<unsigned long long> specialization.
1408 template<>
1409 struct numeric_limits<unsigned long long>
1410 {
1411 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_specialized = true;
1412
1413 static _GLIBCXX_CONSTEXPRconstexpr unsigned long long
1414 min() _GLIBCXX_USE_NOEXCEPTnoexcept { return 0; }
1415
1416 static _GLIBCXX_CONSTEXPRconstexpr unsigned long long
1417 max() _GLIBCXX_USE_NOEXCEPTnoexcept { return __LONG_LONG_MAX__9223372036854775807LL * 2ULL + 1; }
1418
1419#if __cplusplus201703L >= 201103L
1420 static constexpr unsigned long long
1421 lowest() noexcept { return min(); }
1422#endif
1423
1424 static _GLIBCXX_USE_CONSTEXPRconstexpr int digits
1425 = __glibcxx_digits (unsigned long long);
1426 static _GLIBCXX_USE_CONSTEXPRconstexpr int digits10
1427 = __glibcxx_digits10 (unsigned long long);
1428#if __cplusplus201703L >= 201103L
1429 static constexpr int max_digits10 = 0;
1430#endif
1431 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_signed = false;
1432 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_integer = true;
1433 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_exact = true;
1434 static _GLIBCXX_USE_CONSTEXPRconstexpr int radix = 2;
1435
1436 static _GLIBCXX_CONSTEXPRconstexpr unsigned long long
1437 epsilon() _GLIBCXX_USE_NOEXCEPTnoexcept { return 0; }
1438
1439 static _GLIBCXX_CONSTEXPRconstexpr unsigned long long
1440 round_error() _GLIBCXX_USE_NOEXCEPTnoexcept { return 0; }
1441
1442 static _GLIBCXX_USE_CONSTEXPRconstexpr int min_exponent = 0;
1443 static _GLIBCXX_USE_CONSTEXPRconstexpr int min_exponent10 = 0;
1444 static _GLIBCXX_USE_CONSTEXPRconstexpr int max_exponent = 0;
1445 static _GLIBCXX_USE_CONSTEXPRconstexpr int max_exponent10 = 0;
1446
1447 static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_infinity = false;
1448 static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_quiet_NaN = false;
1449 static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_signaling_NaN = false;
1450 static _GLIBCXX_USE_CONSTEXPRconstexpr float_denorm_style has_denorm
1451 = denorm_absent;
1452 static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_denorm_loss = false;
1453
1454 static _GLIBCXX_CONSTEXPRconstexpr unsigned long long
1455 infinity() _GLIBCXX_USE_NOEXCEPTnoexcept
1456 { return static_cast<unsigned long long>(0); }
1457
1458 static _GLIBCXX_CONSTEXPRconstexpr unsigned long long
1459 quiet_NaN() _GLIBCXX_USE_NOEXCEPTnoexcept
1460 { return static_cast<unsigned long long>(0); }
1461
1462 static _GLIBCXX_CONSTEXPRconstexpr unsigned long long
1463 signaling_NaN() _GLIBCXX_USE_NOEXCEPTnoexcept
1464 { return static_cast<unsigned long long>(0); }
1465
1466 static _GLIBCXX_CONSTEXPRconstexpr unsigned long long
1467 denorm_min() _GLIBCXX_USE_NOEXCEPTnoexcept
1468 { return static_cast<unsigned long long>(0); }
1469
1470 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_iec559 = false;
1471 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_bounded = true;
1472 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_modulo = true;
1473
1474 static _GLIBCXX_USE_CONSTEXPRconstexpr bool traps = __glibcxx_integral_trapstrue;
1475 static _GLIBCXX_USE_CONSTEXPRconstexpr bool tinyness_before = false;
1476 static _GLIBCXX_USE_CONSTEXPRconstexpr float_round_style round_style
1477 = round_toward_zero;
1478 };
1479
1480#define __INT_N(TYPE, BITSIZE, EXT, UEXT) \
1481 template<> \
1482 struct numeric_limits<TYPE> \
1483 { \
1484 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_specialized = true; \
1485 \
1486 static _GLIBCXX_CONSTEXPRconstexpr TYPE \
1487 min() _GLIBCXX_USE_NOEXCEPTnoexcept { return __glibcxx_min_b (TYPE, BITSIZE)(((TYPE)(-1) < 0) ? -(((TYPE)(-1) < 0) ? (((((TYPE)1 <<
((BITSIZE - ((TYPE)(-1) < 0)) - 1)) - 1) << 1) + 1)
: ~(TYPE)0) - 1 : (TYPE)0)
; } \
1488 \
1489 static _GLIBCXX_CONSTEXPRconstexpr TYPE \
1490 max() _GLIBCXX_USE_NOEXCEPTnoexcept { return __glibcxx_max_b (TYPE, BITSIZE)(((TYPE)(-1) < 0) ? (((((TYPE)1 << ((BITSIZE - ((TYPE
)(-1) < 0)) - 1)) - 1) << 1) + 1) : ~(TYPE)0)
; } \
1491 \
1492 static _GLIBCXX_USE_CONSTEXPRconstexpr int digits \
1493 = BITSIZE - 1; \
1494 static _GLIBCXX_USE_CONSTEXPRconstexpr int digits10 \
1495 = (BITSIZE - 1) * 643L / 2136; \
1496 \
1497 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_signed = true; \
1498 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_integer = true; \
1499 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_exact = true; \
1500 static _GLIBCXX_USE_CONSTEXPRconstexpr int radix = 2; \
1501 \
1502 static _GLIBCXX_CONSTEXPRconstexpr TYPE \
1503 epsilon() _GLIBCXX_USE_NOEXCEPTnoexcept { return 0; } \
1504 \
1505 static _GLIBCXX_CONSTEXPRconstexpr TYPE \
1506 round_error() _GLIBCXX_USE_NOEXCEPTnoexcept { return 0; } \
1507 \
1508 EXT \
1509 \
1510 static _GLIBCXX_USE_CONSTEXPRconstexpr int min_exponent = 0; \
1511 static _GLIBCXX_USE_CONSTEXPRconstexpr int min_exponent10 = 0; \
1512 static _GLIBCXX_USE_CONSTEXPRconstexpr int max_exponent = 0; \
1513 static _GLIBCXX_USE_CONSTEXPRconstexpr int max_exponent10 = 0; \
1514 \
1515 static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_infinity = false; \
1516 static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_quiet_NaN = false; \
1517 static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_signaling_NaN = false; \
1518 static _GLIBCXX_USE_CONSTEXPRconstexpr float_denorm_style has_denorm \
1519 = denorm_absent; \
1520 static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_denorm_loss = false; \
1521 \
1522 static _GLIBCXX_CONSTEXPRconstexpr TYPE \
1523 infinity() _GLIBCXX_USE_NOEXCEPTnoexcept \
1524 { return static_cast<TYPE>(0); } \
1525 \
1526 static _GLIBCXX_CONSTEXPRconstexpr TYPE \
1527 quiet_NaN() _GLIBCXX_USE_NOEXCEPTnoexcept \
1528 { return static_cast<TYPE>(0); } \
1529 \
1530 static _GLIBCXX_CONSTEXPRconstexpr TYPE \
1531 signaling_NaN() _GLIBCXX_USE_NOEXCEPTnoexcept \
1532 { return static_cast<TYPE>(0); } \
1533 \
1534 static _GLIBCXX_CONSTEXPRconstexpr TYPE \
1535 denorm_min() _GLIBCXX_USE_NOEXCEPTnoexcept \
1536 { return static_cast<TYPE>(0); } \
1537 \
1538 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_iec559 = false; \
1539 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_bounded = true; \
1540 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_modulo = false; \
1541 \
1542 static _GLIBCXX_USE_CONSTEXPRconstexpr bool traps \
1543 = __glibcxx_integral_trapstrue; \
1544 static _GLIBCXX_USE_CONSTEXPRconstexpr bool tinyness_before = false; \
1545 static _GLIBCXX_USE_CONSTEXPRconstexpr float_round_style round_style \
1546 = round_toward_zero; \
1547 }; \
1548 \
1549 template<> \
1550 struct numeric_limits<unsigned TYPE> \
1551 { \
1552 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_specialized = true; \
1553 \
1554 static _GLIBCXX_CONSTEXPRconstexpr unsigned TYPE \
1555 min() _GLIBCXX_USE_NOEXCEPTnoexcept { return 0; } \
1556 \
1557 static _GLIBCXX_CONSTEXPRconstexpr unsigned TYPE \
1558 max() _GLIBCXX_USE_NOEXCEPTnoexcept \
1559 { return __glibcxx_max_b (unsigned TYPE, BITSIZE)(((unsigned TYPE)(-1) < 0) ? (((((unsigned TYPE)1 <<
((BITSIZE - ((unsigned TYPE)(-1) < 0)) - 1)) - 1) <<
1) + 1) : ~(unsigned TYPE)0)
; } \
1560 \
1561 UEXT \
1562 \
1563 static _GLIBCXX_USE_CONSTEXPRconstexpr int digits \
1564 = BITSIZE; \
1565 static _GLIBCXX_USE_CONSTEXPRconstexpr int digits10 \
1566 = BITSIZE * 643L / 2136; \
1567 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_signed = false; \
1568 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_integer = true; \
1569 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_exact = true; \
1570 static _GLIBCXX_USE_CONSTEXPRconstexpr int radix = 2; \
1571 \
1572 static _GLIBCXX_CONSTEXPRconstexpr unsigned TYPE \
1573 epsilon() _GLIBCXX_USE_NOEXCEPTnoexcept { return 0; } \
1574 \
1575 static _GLIBCXX_CONSTEXPRconstexpr unsigned TYPE \
1576 round_error() _GLIBCXX_USE_NOEXCEPTnoexcept { return 0; } \
1577 \
1578 static _GLIBCXX_USE_CONSTEXPRconstexpr int min_exponent = 0; \
1579 static _GLIBCXX_USE_CONSTEXPRconstexpr int min_exponent10 = 0; \
1580 static _GLIBCXX_USE_CONSTEXPRconstexpr int max_exponent = 0; \
1581 static _GLIBCXX_USE_CONSTEXPRconstexpr int max_exponent10 = 0; \
1582 \
1583 static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_infinity = false; \
1584 static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_quiet_NaN = false; \
1585 static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_signaling_NaN = false; \
1586 static _GLIBCXX_USE_CONSTEXPRconstexpr float_denorm_style has_denorm \
1587 = denorm_absent; \
1588 static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_denorm_loss = false; \
1589 \
1590 static _GLIBCXX_CONSTEXPRconstexpr unsigned TYPE \
1591 infinity() _GLIBCXX_USE_NOEXCEPTnoexcept \
1592 { return static_cast<unsigned TYPE>(0); } \
1593 \
1594 static _GLIBCXX_CONSTEXPRconstexpr unsigned TYPE \
1595 quiet_NaN() _GLIBCXX_USE_NOEXCEPTnoexcept \
1596 { return static_cast<unsigned TYPE>(0); } \
1597 \
1598 static _GLIBCXX_CONSTEXPRconstexpr unsigned TYPE \
1599 signaling_NaN() _GLIBCXX_USE_NOEXCEPTnoexcept \
1600 { return static_cast<unsigned TYPE>(0); } \
1601 \
1602 static _GLIBCXX_CONSTEXPRconstexpr unsigned TYPE \
1603 denorm_min() _GLIBCXX_USE_NOEXCEPTnoexcept \
1604 { return static_cast<unsigned TYPE>(0); } \
1605 \
1606 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_iec559 = false; \
1607 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_bounded = true; \
1608 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_modulo = true; \
1609 \
1610 static _GLIBCXX_USE_CONSTEXPRconstexpr bool traps = __glibcxx_integral_trapstrue; \
1611 static _GLIBCXX_USE_CONSTEXPRconstexpr bool tinyness_before = false; \
1612 static _GLIBCXX_USE_CONSTEXPRconstexpr float_round_style round_style \
1613 = round_toward_zero; \
1614 };
1615
1616#if __cplusplus201703L >= 201103L
1617
1618#define __INT_N_201103(TYPE) \
1619 static constexpr TYPE \
1620 lowest() noexcept { return min(); } \
1621 static constexpr int max_digits10 = 0;
1622
1623#define __INT_N_U201103(TYPE) \
1624 static constexpr unsigned TYPE \
1625 lowest() noexcept { return min(); } \
1626 static constexpr int max_digits10 = 0;
1627
1628#else
1629#define __INT_N_201103(TYPE)
1630#define __INT_N_U201103(TYPE)
1631#endif
1632
1633#if !defined(__STRICT_ANSI__1)
1634#ifdef __GLIBCXX_TYPE_INT_N_0
1635 __INT_N(__GLIBCXX_TYPE_INT_N_0, __GLIBCXX_BITSIZE_INT_N_0,
1636 __INT_N_201103 (__GLIBCXX_TYPE_INT_N_0), __INT_N_U201103 (__GLIBCXX_TYPE_INT_N_0))
1637#endif
1638#ifdef __GLIBCXX_TYPE_INT_N_1
1639 __INT_N (__GLIBCXX_TYPE_INT_N_1, __GLIBCXX_BITSIZE_INT_N_1,
1640 __INT_N_201103 (__GLIBCXX_TYPE_INT_N_1), __INT_N_U201103 (__GLIBCXX_TYPE_INT_N_1))
1641#endif
1642#ifdef __GLIBCXX_TYPE_INT_N_2
1643 __INT_N (__GLIBCXX_TYPE_INT_N_2, __GLIBCXX_BITSIZE_INT_N_2,
1644 __INT_N_201103 (__GLIBCXX_TYPE_INT_N_2), __INT_N_U201103 (__GLIBCXX_TYPE_INT_N_2))
1645#endif
1646#ifdef __GLIBCXX_TYPE_INT_N_3
1647 __INT_N (__GLIBCXX_TYPE_INT_N_3, __GLIBCXX_BITSIZE_INT_N_3,
1648 __INT_N_201103 (__GLIBCXX_TYPE_INT_N_3), __INT_N_U201103 (__GLIBCXX_TYPE_INT_N_3))
1649#endif
1650
1651#elif defined __STRICT_ANSI__1 && defined __SIZEOF_INT128__16
1652 __INT_N(__int128, 128,
1653 __INT_N_201103 (__int128),
1654 __INT_N_U201103 (__int128))
1655#endif
1656
1657#undef __INT_N
1658#undef __INT_N_201103
1659#undef __INT_N_U201103
1660
1661
1662 /// numeric_limits<float> specialization.
1663 template<>
1664 struct numeric_limits<float>
1665 {
1666 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_specialized = true;
1667
1668 static _GLIBCXX_CONSTEXPRconstexpr float
1669 min() _GLIBCXX_USE_NOEXCEPTnoexcept { return __FLT_MIN__1.17549435e-38F; }
1670
1671 static _GLIBCXX_CONSTEXPRconstexpr float
1672 max() _GLIBCXX_USE_NOEXCEPTnoexcept { return __FLT_MAX__3.40282347e+38F; }
1673
1674#if __cplusplus201703L >= 201103L
1675 static constexpr float
1676 lowest() noexcept { return -__FLT_MAX__3.40282347e+38F; }
1677#endif
1678
1679 static _GLIBCXX_USE_CONSTEXPRconstexpr int digits = __FLT_MANT_DIG__24;
1680 static _GLIBCXX_USE_CONSTEXPRconstexpr int digits10 = __FLT_DIG__6;
1681#if __cplusplus201703L >= 201103L
1682 static constexpr int max_digits10
1683 = __glibcxx_max_digits10 (__FLT_MANT_DIG__24);
1684#endif
1685 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_signed = true;
1686 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_integer = false;
1687 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_exact = false;
1688 static _GLIBCXX_USE_CONSTEXPRconstexpr int radix = __FLT_RADIX__2;
1689
1690 static _GLIBCXX_CONSTEXPRconstexpr float
1691 epsilon() _GLIBCXX_USE_NOEXCEPTnoexcept { return __FLT_EPSILON__1.19209290e-7F; }
1692
1693 static _GLIBCXX_CONSTEXPRconstexpr float
1694 round_error() _GLIBCXX_USE_NOEXCEPTnoexcept { return 0.5F; }
1695
1696 static _GLIBCXX_USE_CONSTEXPRconstexpr int min_exponent = __FLT_MIN_EXP__(-125);
1697 static _GLIBCXX_USE_CONSTEXPRconstexpr int min_exponent10 = __FLT_MIN_10_EXP__(-37);
1698 static _GLIBCXX_USE_CONSTEXPRconstexpr int max_exponent = __FLT_MAX_EXP__128;
1699 static _GLIBCXX_USE_CONSTEXPRconstexpr int max_exponent10 = __FLT_MAX_10_EXP__38;
1700
1701 static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_infinity = __FLT_HAS_INFINITY__1;
1702 static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_quiet_NaN = __FLT_HAS_QUIET_NAN__1;
1703 static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_signaling_NaN = has_quiet_NaN;
1704 static _GLIBCXX_USE_CONSTEXPRconstexpr float_denorm_style has_denorm
1705 = bool(__FLT_HAS_DENORM__1) ? denorm_present : denorm_absent;
1706 static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_denorm_loss
1707 = __glibcxx_float_has_denorm_loss;
1708
1709 static _GLIBCXX_CONSTEXPRconstexpr float
1710 infinity() _GLIBCXX_USE_NOEXCEPTnoexcept { return __builtin_huge_valf(); }
1711
1712 static _GLIBCXX_CONSTEXPRconstexpr float
1713 quiet_NaN() _GLIBCXX_USE_NOEXCEPTnoexcept { return __builtin_nanf(""); }
1714
1715 static _GLIBCXX_CONSTEXPRconstexpr float
1716 signaling_NaN() _GLIBCXX_USE_NOEXCEPTnoexcept { return __builtin_nansf(""); }
1717
1718 static _GLIBCXX_CONSTEXPRconstexpr float
1719 denorm_min() _GLIBCXX_USE_NOEXCEPTnoexcept { return __FLT_DENORM_MIN__1.40129846e-45F; }
1720
1721 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_iec559
1722 = has_infinity && has_quiet_NaN && has_denorm == denorm_present;
1723 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_bounded = true;
1724 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_modulo = false;
1725
1726 static _GLIBCXX_USE_CONSTEXPRconstexpr bool traps = __glibcxx_float_traps;
1727 static _GLIBCXX_USE_CONSTEXPRconstexpr bool tinyness_before
1728 = __glibcxx_float_tinyness_before;
1729 static _GLIBCXX_USE_CONSTEXPRconstexpr float_round_style round_style
1730 = round_to_nearest;
1731 };
1732
1733#undef __glibcxx_float_has_denorm_loss
1734#undef __glibcxx_float_traps
1735#undef __glibcxx_float_tinyness_before
1736
1737 /// numeric_limits<double> specialization.
1738 template<>
1739 struct numeric_limits<double>
1740 {
1741 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_specialized = true;
1742
1743 static _GLIBCXX_CONSTEXPRconstexpr double
1744 min() _GLIBCXX_USE_NOEXCEPTnoexcept { return __DBL_MIN__2.2250738585072014e-308; }
1745
1746 static _GLIBCXX_CONSTEXPRconstexpr double
1747 max() _GLIBCXX_USE_NOEXCEPTnoexcept { return __DBL_MAX__1.7976931348623157e+308; }
1748
1749#if __cplusplus201703L >= 201103L
1750 static constexpr double
1751 lowest() noexcept { return -__DBL_MAX__1.7976931348623157e+308; }
1752#endif
1753
1754 static _GLIBCXX_USE_CONSTEXPRconstexpr int digits = __DBL_MANT_DIG__53;
1755 static _GLIBCXX_USE_CONSTEXPRconstexpr int digits10 = __DBL_DIG__15;
1756#if __cplusplus201703L >= 201103L
1757 static constexpr int max_digits10
1758 = __glibcxx_max_digits10 (__DBL_MANT_DIG__53);
1759#endif
1760 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_signed = true;
1761 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_integer = false;
1762 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_exact = false;
1763 static _GLIBCXX_USE_CONSTEXPRconstexpr int radix = __FLT_RADIX__2;
1764
1765 static _GLIBCXX_CONSTEXPRconstexpr double
1766 epsilon() _GLIBCXX_USE_NOEXCEPTnoexcept { return __DBL_EPSILON__2.2204460492503131e-16; }
1767
1768 static _GLIBCXX_CONSTEXPRconstexpr double
1769 round_error() _GLIBCXX_USE_NOEXCEPTnoexcept { return 0.5; }
1770
1771 static _GLIBCXX_USE_CONSTEXPRconstexpr int min_exponent = __DBL_MIN_EXP__(-1021);
1772 static _GLIBCXX_USE_CONSTEXPRconstexpr int min_exponent10 = __DBL_MIN_10_EXP__(-307);
1773 static _GLIBCXX_USE_CONSTEXPRconstexpr int max_exponent = __DBL_MAX_EXP__1024;
1774 static _GLIBCXX_USE_CONSTEXPRconstexpr int max_exponent10 = __DBL_MAX_10_EXP__308;
1775
1776 static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_infinity = __DBL_HAS_INFINITY__1;
1777 static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_quiet_NaN = __DBL_HAS_QUIET_NAN__1;
1778 static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_signaling_NaN = has_quiet_NaN;
1779 static _GLIBCXX_USE_CONSTEXPRconstexpr float_denorm_style has_denorm
1780 = bool(__DBL_HAS_DENORM__1) ? denorm_present : denorm_absent;
1781 static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_denorm_loss
1782 = __glibcxx_double_has_denorm_loss;
1783
1784 static _GLIBCXX_CONSTEXPRconstexpr double
1785 infinity() _GLIBCXX_USE_NOEXCEPTnoexcept { return __builtin_huge_val(); }
1786
1787 static _GLIBCXX_CONSTEXPRconstexpr double
1788 quiet_NaN() _GLIBCXX_USE_NOEXCEPTnoexcept { return __builtin_nan(""); }
1789
1790 static _GLIBCXX_CONSTEXPRconstexpr double
1791 signaling_NaN() _GLIBCXX_USE_NOEXCEPTnoexcept { return __builtin_nans(""); }
1792
1793 static _GLIBCXX_CONSTEXPRconstexpr double
1794 denorm_min() _GLIBCXX_USE_NOEXCEPTnoexcept { return __DBL_DENORM_MIN__4.9406564584124654e-324; }
1795
1796 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_iec559
1797 = has_infinity && has_quiet_NaN && has_denorm == denorm_present;
1798 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_bounded = true;
1799 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_modulo = false;
1800
1801 static _GLIBCXX_USE_CONSTEXPRconstexpr bool traps = __glibcxx_double_traps;
1802 static _GLIBCXX_USE_CONSTEXPRconstexpr bool tinyness_before
1803 = __glibcxx_double_tinyness_before;
1804 static _GLIBCXX_USE_CONSTEXPRconstexpr float_round_style round_style
1805 = round_to_nearest;
1806 };
1807
1808#undef __glibcxx_double_has_denorm_loss
1809#undef __glibcxx_double_traps
1810#undef __glibcxx_double_tinyness_before
1811
1812 /// numeric_limits<long double> specialization.
1813 template<>
1814 struct numeric_limits<long double>
1815 {
1816 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_specialized = true;
1817
1818 static _GLIBCXX_CONSTEXPRconstexpr long double
1819 min() _GLIBCXX_USE_NOEXCEPTnoexcept { return __LDBL_MIN__3.36210314311209350626e-4932L; }
1820
1821 static _GLIBCXX_CONSTEXPRconstexpr long double
1822 max() _GLIBCXX_USE_NOEXCEPTnoexcept { return __LDBL_MAX__1.18973149535723176502e+4932L; }
1823
1824#if __cplusplus201703L >= 201103L
1825 static constexpr long double
1826 lowest() noexcept { return -__LDBL_MAX__1.18973149535723176502e+4932L; }
1827#endif
1828
1829 static _GLIBCXX_USE_CONSTEXPRconstexpr int digits = __LDBL_MANT_DIG__64;
1830 static _GLIBCXX_USE_CONSTEXPRconstexpr int digits10 = __LDBL_DIG__18;
1831#if __cplusplus201703L >= 201103L
1832 static _GLIBCXX_USE_CONSTEXPRconstexpr int max_digits10
1833 = __glibcxx_max_digits10 (__LDBL_MANT_DIG__64);
1834#endif
1835 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_signed = true;
1836 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_integer = false;
1837 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_exact = false;
1838 static _GLIBCXX_USE_CONSTEXPRconstexpr int radix = __FLT_RADIX__2;
1839
1840 static _GLIBCXX_CONSTEXPRconstexpr long double
1841 epsilon() _GLIBCXX_USE_NOEXCEPTnoexcept { return __LDBL_EPSILON__1.08420217248550443401e-19L; }
1842
1843 static _GLIBCXX_CONSTEXPRconstexpr long double
1844 round_error() _GLIBCXX_USE_NOEXCEPTnoexcept { return 0.5L; }
1845
1846 static _GLIBCXX_USE_CONSTEXPRconstexpr int min_exponent = __LDBL_MIN_EXP__(-16381);
1847 static _GLIBCXX_USE_CONSTEXPRconstexpr int min_exponent10 = __LDBL_MIN_10_EXP__(-4931);
1848 static _GLIBCXX_USE_CONSTEXPRconstexpr int max_exponent = __LDBL_MAX_EXP__16384;
1849 static _GLIBCXX_USE_CONSTEXPRconstexpr int max_exponent10 = __LDBL_MAX_10_EXP__4932;
1850
1851 static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_infinity = __LDBL_HAS_INFINITY__1;
1852 static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_quiet_NaN = __LDBL_HAS_QUIET_NAN__1;
1853 static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_signaling_NaN = has_quiet_NaN;
1854 static _GLIBCXX_USE_CONSTEXPRconstexpr float_denorm_style has_denorm
1855 = bool(__LDBL_HAS_DENORM__1) ? denorm_present : denorm_absent;
1856 static _GLIBCXX_USE_CONSTEXPRconstexpr bool has_denorm_loss
1857 = __glibcxx_long_double_has_denorm_loss;
1858
1859 static _GLIBCXX_CONSTEXPRconstexpr long double
1860 infinity() _GLIBCXX_USE_NOEXCEPTnoexcept { return __builtin_huge_vall(); }
1861
1862 static _GLIBCXX_CONSTEXPRconstexpr long double
1863 quiet_NaN() _GLIBCXX_USE_NOEXCEPTnoexcept { return __builtin_nanl(""); }
1864
1865 static _GLIBCXX_CONSTEXPRconstexpr long double
1866 signaling_NaN() _GLIBCXX_USE_NOEXCEPTnoexcept { return __builtin_nansl(""); }
1867
1868 static _GLIBCXX_CONSTEXPRconstexpr long double
1869 denorm_min() _GLIBCXX_USE_NOEXCEPTnoexcept { return __LDBL_DENORM_MIN__3.64519953188247460253e-4951L; }
1870
1871 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_iec559
1872 = has_infinity && has_quiet_NaN && has_denorm == denorm_present;
1873 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_bounded = true;
1874 static _GLIBCXX_USE_CONSTEXPRconstexpr bool is_modulo = false;
1875
1876 static _GLIBCXX_USE_CONSTEXPRconstexpr bool traps = __glibcxx_long_double_traps;
1877 static _GLIBCXX_USE_CONSTEXPRconstexpr bool tinyness_before =
1878 __glibcxx_long_double_tinyness_before;
1879 static _GLIBCXX_USE_CONSTEXPRconstexpr float_round_style round_style =
1880 round_to_nearest;
1881 };
1882
1883#undef __glibcxx_long_double_has_denorm_loss
1884#undef __glibcxx_long_double_traps
1885#undef __glibcxx_long_double_tinyness_before
1886
1887_GLIBCXX_END_NAMESPACE_VERSION
1888} // namespace
1889
1890#undef __glibcxx_signed
1891#undef __glibcxx_min
1892#undef __glibcxx_max
1893#undef __glibcxx_digits
1894#undef __glibcxx_digits10
1895#undef __glibcxx_max_digits10
1896
1897#endif // _GLIBCXX_NUMERIC_LIMITS