File: | llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp |
Warning: | line 698, column 32 The result of the '%' expression is undefined |
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1 | //===-- TargetLowering.cpp - Implement the TargetLowering class -----------===// | ||||||||||
2 | // | ||||||||||
3 | // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. | ||||||||||
4 | // See https://llvm.org/LICENSE.txt for license information. | ||||||||||
5 | // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception | ||||||||||
6 | // | ||||||||||
7 | //===----------------------------------------------------------------------===// | ||||||||||
8 | // | ||||||||||
9 | // This implements the TargetLowering class. | ||||||||||
10 | // | ||||||||||
11 | //===----------------------------------------------------------------------===// | ||||||||||
12 | |||||||||||
13 | #include "llvm/CodeGen/TargetLowering.h" | ||||||||||
14 | #include "llvm/ADT/STLExtras.h" | ||||||||||
15 | #include "llvm/CodeGen/CallingConvLower.h" | ||||||||||
16 | #include "llvm/CodeGen/MachineFrameInfo.h" | ||||||||||
17 | #include "llvm/CodeGen/MachineFunction.h" | ||||||||||
18 | #include "llvm/CodeGen/MachineJumpTableInfo.h" | ||||||||||
19 | #include "llvm/CodeGen/MachineRegisterInfo.h" | ||||||||||
20 | #include "llvm/CodeGen/SelectionDAG.h" | ||||||||||
21 | #include "llvm/CodeGen/TargetRegisterInfo.h" | ||||||||||
22 | #include "llvm/CodeGen/TargetSubtargetInfo.h" | ||||||||||
23 | #include "llvm/IR/DataLayout.h" | ||||||||||
24 | #include "llvm/IR/DerivedTypes.h" | ||||||||||
25 | #include "llvm/IR/GlobalVariable.h" | ||||||||||
26 | #include "llvm/IR/LLVMContext.h" | ||||||||||
27 | #include "llvm/MC/MCAsmInfo.h" | ||||||||||
28 | #include "llvm/MC/MCExpr.h" | ||||||||||
29 | #include "llvm/Support/DivisionByConstantInfo.h" | ||||||||||
30 | #include "llvm/Support/ErrorHandling.h" | ||||||||||
31 | #include "llvm/Support/KnownBits.h" | ||||||||||
32 | #include "llvm/Support/MathExtras.h" | ||||||||||
33 | #include "llvm/Target/TargetLoweringObjectFile.h" | ||||||||||
34 | #include "llvm/Target/TargetMachine.h" | ||||||||||
35 | #include <cctype> | ||||||||||
36 | using namespace llvm; | ||||||||||
37 | |||||||||||
38 | /// NOTE: The TargetMachine owns TLOF. | ||||||||||
39 | TargetLowering::TargetLowering(const TargetMachine &tm) | ||||||||||
40 | : TargetLoweringBase(tm) {} | ||||||||||
41 | |||||||||||
42 | const char *TargetLowering::getTargetNodeName(unsigned Opcode) const { | ||||||||||
43 | return nullptr; | ||||||||||
44 | } | ||||||||||
45 | |||||||||||
46 | bool TargetLowering::isPositionIndependent() const { | ||||||||||
47 | return getTargetMachine().isPositionIndependent(); | ||||||||||
48 | } | ||||||||||
49 | |||||||||||
50 | /// Check whether a given call node is in tail position within its function. If | ||||||||||
51 | /// so, it sets Chain to the input chain of the tail call. | ||||||||||
52 | bool TargetLowering::isInTailCallPosition(SelectionDAG &DAG, SDNode *Node, | ||||||||||
53 | SDValue &Chain) const { | ||||||||||
54 | const Function &F = DAG.getMachineFunction().getFunction(); | ||||||||||
55 | |||||||||||
56 | // First, check if tail calls have been disabled in this function. | ||||||||||
57 | if (F.getFnAttribute("disable-tail-calls").getValueAsBool()) | ||||||||||
58 | return false; | ||||||||||
59 | |||||||||||
60 | // Conservatively require the attributes of the call to match those of | ||||||||||
61 | // the return. Ignore following attributes because they don't affect the | ||||||||||
62 | // call sequence. | ||||||||||
63 | AttrBuilder CallerAttrs(F.getAttributes(), AttributeList::ReturnIndex); | ||||||||||
64 | for (const auto &Attr : {Attribute::Alignment, Attribute::Dereferenceable, | ||||||||||
65 | Attribute::DereferenceableOrNull, Attribute::NoAlias, | ||||||||||
66 | Attribute::NonNull}) | ||||||||||
67 | CallerAttrs.removeAttribute(Attr); | ||||||||||
68 | |||||||||||
69 | if (CallerAttrs.hasAttributes()) | ||||||||||
70 | return false; | ||||||||||
71 | |||||||||||
72 | // It's not safe to eliminate the sign / zero extension of the return value. | ||||||||||
73 | if (CallerAttrs.contains(Attribute::ZExt) || | ||||||||||
74 | CallerAttrs.contains(Attribute::SExt)) | ||||||||||
75 | return false; | ||||||||||
76 | |||||||||||
77 | // Check if the only use is a function return node. | ||||||||||
78 | return isUsedByReturnOnly(Node, Chain); | ||||||||||
79 | } | ||||||||||
80 | |||||||||||
81 | bool TargetLowering::parametersInCSRMatch(const MachineRegisterInfo &MRI, | ||||||||||
82 | const uint32_t *CallerPreservedMask, | ||||||||||
83 | const SmallVectorImpl<CCValAssign> &ArgLocs, | ||||||||||
84 | const SmallVectorImpl<SDValue> &OutVals) const { | ||||||||||
85 | for (unsigned I = 0, E = ArgLocs.size(); I != E; ++I) { | ||||||||||
86 | const CCValAssign &ArgLoc = ArgLocs[I]; | ||||||||||
87 | if (!ArgLoc.isRegLoc()) | ||||||||||
88 | continue; | ||||||||||
89 | MCRegister Reg = ArgLoc.getLocReg(); | ||||||||||
90 | // Only look at callee saved registers. | ||||||||||
91 | if (MachineOperand::clobbersPhysReg(CallerPreservedMask, Reg)) | ||||||||||
92 | continue; | ||||||||||
93 | // Check that we pass the value used for the caller. | ||||||||||
94 | // (We look for a CopyFromReg reading a virtual register that is used | ||||||||||
95 | // for the function live-in value of register Reg) | ||||||||||
96 | SDValue Value = OutVals[I]; | ||||||||||
97 | if (Value->getOpcode() != ISD::CopyFromReg) | ||||||||||
98 | return false; | ||||||||||
99 | Register ArgReg = cast<RegisterSDNode>(Value->getOperand(1))->getReg(); | ||||||||||
100 | if (MRI.getLiveInPhysReg(ArgReg) != Reg) | ||||||||||
101 | return false; | ||||||||||
102 | } | ||||||||||
103 | return true; | ||||||||||
104 | } | ||||||||||
105 | |||||||||||
106 | /// Set CallLoweringInfo attribute flags based on a call instruction | ||||||||||
107 | /// and called function attributes. | ||||||||||
108 | void TargetLoweringBase::ArgListEntry::setAttributes(const CallBase *Call, | ||||||||||
109 | unsigned ArgIdx) { | ||||||||||
110 | IsSExt = Call->paramHasAttr(ArgIdx, Attribute::SExt); | ||||||||||
111 | IsZExt = Call->paramHasAttr(ArgIdx, Attribute::ZExt); | ||||||||||
112 | IsInReg = Call->paramHasAttr(ArgIdx, Attribute::InReg); | ||||||||||
113 | IsSRet = Call->paramHasAttr(ArgIdx, Attribute::StructRet); | ||||||||||
114 | IsNest = Call->paramHasAttr(ArgIdx, Attribute::Nest); | ||||||||||
115 | IsByVal = Call->paramHasAttr(ArgIdx, Attribute::ByVal); | ||||||||||
116 | IsPreallocated = Call->paramHasAttr(ArgIdx, Attribute::Preallocated); | ||||||||||
117 | IsInAlloca = Call->paramHasAttr(ArgIdx, Attribute::InAlloca); | ||||||||||
118 | IsReturned = Call->paramHasAttr(ArgIdx, Attribute::Returned); | ||||||||||
119 | IsSwiftSelf = Call->paramHasAttr(ArgIdx, Attribute::SwiftSelf); | ||||||||||
120 | IsSwiftAsync = Call->paramHasAttr(ArgIdx, Attribute::SwiftAsync); | ||||||||||
121 | IsSwiftError = Call->paramHasAttr(ArgIdx, Attribute::SwiftError); | ||||||||||
122 | Alignment = Call->getParamStackAlign(ArgIdx); | ||||||||||
123 | IndirectType = nullptr; | ||||||||||
124 | assert(IsByVal + IsPreallocated + IsInAlloca <= 1 &&(static_cast <bool> (IsByVal + IsPreallocated + IsInAlloca <= 1 && "multiple ABI attributes?") ? void (0) : __assert_fail ("IsByVal + IsPreallocated + IsInAlloca <= 1 && \"multiple ABI attributes?\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 125, __extension__ __PRETTY_FUNCTION__)) | ||||||||||
125 | "multiple ABI attributes?")(static_cast <bool> (IsByVal + IsPreallocated + IsInAlloca <= 1 && "multiple ABI attributes?") ? void (0) : __assert_fail ("IsByVal + IsPreallocated + IsInAlloca <= 1 && \"multiple ABI attributes?\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 125, __extension__ __PRETTY_FUNCTION__)); | ||||||||||
126 | if (IsByVal) { | ||||||||||
127 | IndirectType = Call->getParamByValType(ArgIdx); | ||||||||||
128 | if (!Alignment) | ||||||||||
129 | Alignment = Call->getParamAlign(ArgIdx); | ||||||||||
130 | } | ||||||||||
131 | if (IsPreallocated) | ||||||||||
132 | IndirectType = Call->getParamPreallocatedType(ArgIdx); | ||||||||||
133 | if (IsInAlloca) | ||||||||||
134 | IndirectType = Call->getParamInAllocaType(ArgIdx); | ||||||||||
135 | } | ||||||||||
136 | |||||||||||
137 | /// Generate a libcall taking the given operands as arguments and returning a | ||||||||||
138 | /// result of type RetVT. | ||||||||||
139 | std::pair<SDValue, SDValue> | ||||||||||
140 | TargetLowering::makeLibCall(SelectionDAG &DAG, RTLIB::Libcall LC, EVT RetVT, | ||||||||||
141 | ArrayRef<SDValue> Ops, | ||||||||||
142 | MakeLibCallOptions CallOptions, | ||||||||||
143 | const SDLoc &dl, | ||||||||||
144 | SDValue InChain) const { | ||||||||||
145 | if (!InChain) | ||||||||||
146 | InChain = DAG.getEntryNode(); | ||||||||||
147 | |||||||||||
148 | TargetLowering::ArgListTy Args; | ||||||||||
149 | Args.reserve(Ops.size()); | ||||||||||
150 | |||||||||||
151 | TargetLowering::ArgListEntry Entry; | ||||||||||
152 | for (unsigned i = 0; i < Ops.size(); ++i) { | ||||||||||
153 | SDValue NewOp = Ops[i]; | ||||||||||
154 | Entry.Node = NewOp; | ||||||||||
155 | Entry.Ty = Entry.Node.getValueType().getTypeForEVT(*DAG.getContext()); | ||||||||||
156 | Entry.IsSExt = shouldSignExtendTypeInLibCall(NewOp.getValueType(), | ||||||||||
157 | CallOptions.IsSExt); | ||||||||||
158 | Entry.IsZExt = !Entry.IsSExt; | ||||||||||
159 | |||||||||||
160 | if (CallOptions.IsSoften && | ||||||||||
161 | !shouldExtendTypeInLibCall(CallOptions.OpsVTBeforeSoften[i])) { | ||||||||||
162 | Entry.IsSExt = Entry.IsZExt = false; | ||||||||||
163 | } | ||||||||||
164 | Args.push_back(Entry); | ||||||||||
165 | } | ||||||||||
166 | |||||||||||
167 | if (LC == RTLIB::UNKNOWN_LIBCALL) | ||||||||||
168 | report_fatal_error("Unsupported library call operation!"); | ||||||||||
169 | SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC), | ||||||||||
170 | getPointerTy(DAG.getDataLayout())); | ||||||||||
171 | |||||||||||
172 | Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext()); | ||||||||||
173 | TargetLowering::CallLoweringInfo CLI(DAG); | ||||||||||
174 | bool signExtend = shouldSignExtendTypeInLibCall(RetVT, CallOptions.IsSExt); | ||||||||||
175 | bool zeroExtend = !signExtend; | ||||||||||
176 | |||||||||||
177 | if (CallOptions.IsSoften && | ||||||||||
178 | !shouldExtendTypeInLibCall(CallOptions.RetVTBeforeSoften)) { | ||||||||||
179 | signExtend = zeroExtend = false; | ||||||||||
180 | } | ||||||||||
181 | |||||||||||
182 | CLI.setDebugLoc(dl) | ||||||||||
183 | .setChain(InChain) | ||||||||||
184 | .setLibCallee(getLibcallCallingConv(LC), RetTy, Callee, std::move(Args)) | ||||||||||
185 | .setNoReturn(CallOptions.DoesNotReturn) | ||||||||||
186 | .setDiscardResult(!CallOptions.IsReturnValueUsed) | ||||||||||
187 | .setIsPostTypeLegalization(CallOptions.IsPostTypeLegalization) | ||||||||||
188 | .setSExtResult(signExtend) | ||||||||||
189 | .setZExtResult(zeroExtend); | ||||||||||
190 | return LowerCallTo(CLI); | ||||||||||
191 | } | ||||||||||
192 | |||||||||||
193 | bool TargetLowering::findOptimalMemOpLowering( | ||||||||||
194 | std::vector<EVT> &MemOps, unsigned Limit, const MemOp &Op, unsigned DstAS, | ||||||||||
195 | unsigned SrcAS, const AttributeList &FuncAttributes) const { | ||||||||||
196 | if (Op.isMemcpyWithFixedDstAlign() && Op.getSrcAlign() < Op.getDstAlign()) | ||||||||||
197 | return false; | ||||||||||
198 | |||||||||||
199 | EVT VT = getOptimalMemOpType(Op, FuncAttributes); | ||||||||||
200 | |||||||||||
201 | if (VT == MVT::Other) { | ||||||||||
202 | // Use the largest integer type whose alignment constraints are satisfied. | ||||||||||
203 | // We only need to check DstAlign here as SrcAlign is always greater or | ||||||||||
204 | // equal to DstAlign (or zero). | ||||||||||
205 | VT = MVT::i64; | ||||||||||
206 | if (Op.isFixedDstAlign()) | ||||||||||
207 | while (Op.getDstAlign() < (VT.getSizeInBits() / 8) && | ||||||||||
208 | !allowsMisalignedMemoryAccesses(VT, DstAS, Op.getDstAlign())) | ||||||||||
209 | VT = (MVT::SimpleValueType)(VT.getSimpleVT().SimpleTy - 1); | ||||||||||
210 | assert(VT.isInteger())(static_cast <bool> (VT.isInteger()) ? void (0) : __assert_fail ("VT.isInteger()", "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 210, __extension__ __PRETTY_FUNCTION__)); | ||||||||||
211 | |||||||||||
212 | // Find the largest legal integer type. | ||||||||||
213 | MVT LVT = MVT::i64; | ||||||||||
214 | while (!isTypeLegal(LVT)) | ||||||||||
215 | LVT = (MVT::SimpleValueType)(LVT.SimpleTy - 1); | ||||||||||
216 | assert(LVT.isInteger())(static_cast <bool> (LVT.isInteger()) ? void (0) : __assert_fail ("LVT.isInteger()", "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 216, __extension__ __PRETTY_FUNCTION__)); | ||||||||||
217 | |||||||||||
218 | // If the type we've chosen is larger than the largest legal integer type | ||||||||||
219 | // then use that instead. | ||||||||||
220 | if (VT.bitsGT(LVT)) | ||||||||||
221 | VT = LVT; | ||||||||||
222 | } | ||||||||||
223 | |||||||||||
224 | unsigned NumMemOps = 0; | ||||||||||
225 | uint64_t Size = Op.size(); | ||||||||||
226 | while (Size) { | ||||||||||
227 | unsigned VTSize = VT.getSizeInBits() / 8; | ||||||||||
228 | while (VTSize > Size) { | ||||||||||
229 | // For now, only use non-vector load / store's for the left-over pieces. | ||||||||||
230 | EVT NewVT = VT; | ||||||||||
231 | unsigned NewVTSize; | ||||||||||
232 | |||||||||||
233 | bool Found = false; | ||||||||||
234 | if (VT.isVector() || VT.isFloatingPoint()) { | ||||||||||
235 | NewVT = (VT.getSizeInBits() > 64) ? MVT::i64 : MVT::i32; | ||||||||||
236 | if (isOperationLegalOrCustom(ISD::STORE, NewVT) && | ||||||||||
237 | isSafeMemOpType(NewVT.getSimpleVT())) | ||||||||||
238 | Found = true; | ||||||||||
239 | else if (NewVT == MVT::i64 && | ||||||||||
240 | isOperationLegalOrCustom(ISD::STORE, MVT::f64) && | ||||||||||
241 | isSafeMemOpType(MVT::f64)) { | ||||||||||
242 | // i64 is usually not legal on 32-bit targets, but f64 may be. | ||||||||||
243 | NewVT = MVT::f64; | ||||||||||
244 | Found = true; | ||||||||||
245 | } | ||||||||||
246 | } | ||||||||||
247 | |||||||||||
248 | if (!Found) { | ||||||||||
249 | do { | ||||||||||
250 | NewVT = (MVT::SimpleValueType)(NewVT.getSimpleVT().SimpleTy - 1); | ||||||||||
251 | if (NewVT == MVT::i8) | ||||||||||
252 | break; | ||||||||||
253 | } while (!isSafeMemOpType(NewVT.getSimpleVT())); | ||||||||||
254 | } | ||||||||||
255 | NewVTSize = NewVT.getSizeInBits() / 8; | ||||||||||
256 | |||||||||||
257 | // If the new VT cannot cover all of the remaining bits, then consider | ||||||||||
258 | // issuing a (or a pair of) unaligned and overlapping load / store. | ||||||||||
259 | bool Fast; | ||||||||||
260 | if (NumMemOps && Op.allowOverlap() && NewVTSize < Size && | ||||||||||
261 | allowsMisalignedMemoryAccesses( | ||||||||||
262 | VT, DstAS, Op.isFixedDstAlign() ? Op.getDstAlign() : Align(1), | ||||||||||
263 | MachineMemOperand::MONone, &Fast) && | ||||||||||
264 | Fast) | ||||||||||
265 | VTSize = Size; | ||||||||||
266 | else { | ||||||||||
267 | VT = NewVT; | ||||||||||
268 | VTSize = NewVTSize; | ||||||||||
269 | } | ||||||||||
270 | } | ||||||||||
271 | |||||||||||
272 | if (++NumMemOps > Limit) | ||||||||||
273 | return false; | ||||||||||
274 | |||||||||||
275 | MemOps.push_back(VT); | ||||||||||
276 | Size -= VTSize; | ||||||||||
277 | } | ||||||||||
278 | |||||||||||
279 | return true; | ||||||||||
280 | } | ||||||||||
281 | |||||||||||
282 | /// Soften the operands of a comparison. This code is shared among BR_CC, | ||||||||||
283 | /// SELECT_CC, and SETCC handlers. | ||||||||||
284 | void TargetLowering::softenSetCCOperands(SelectionDAG &DAG, EVT VT, | ||||||||||
285 | SDValue &NewLHS, SDValue &NewRHS, | ||||||||||
286 | ISD::CondCode &CCCode, | ||||||||||
287 | const SDLoc &dl, const SDValue OldLHS, | ||||||||||
288 | const SDValue OldRHS) const { | ||||||||||
289 | SDValue Chain; | ||||||||||
290 | return softenSetCCOperands(DAG, VT, NewLHS, NewRHS, CCCode, dl, OldLHS, | ||||||||||
291 | OldRHS, Chain); | ||||||||||
292 | } | ||||||||||
293 | |||||||||||
294 | void TargetLowering::softenSetCCOperands(SelectionDAG &DAG, EVT VT, | ||||||||||
295 | SDValue &NewLHS, SDValue &NewRHS, | ||||||||||
296 | ISD::CondCode &CCCode, | ||||||||||
297 | const SDLoc &dl, const SDValue OldLHS, | ||||||||||
298 | const SDValue OldRHS, | ||||||||||
299 | SDValue &Chain, | ||||||||||
300 | bool IsSignaling) const { | ||||||||||
301 | // FIXME: Currently we cannot really respect all IEEE predicates due to libgcc | ||||||||||
302 | // not supporting it. We can update this code when libgcc provides such | ||||||||||
303 | // functions. | ||||||||||
304 | |||||||||||
305 | assert((VT == MVT::f32 || VT == MVT::f64 || VT == MVT::f128 || VT == MVT::ppcf128)(static_cast <bool> ((VT == MVT::f32 || VT == MVT::f64 || VT == MVT::f128 || VT == MVT::ppcf128) && "Unsupported setcc type!" ) ? void (0) : __assert_fail ("(VT == MVT::f32 || VT == MVT::f64 || VT == MVT::f128 || VT == MVT::ppcf128) && \"Unsupported setcc type!\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 306, __extension__ __PRETTY_FUNCTION__)) | ||||||||||
306 | && "Unsupported setcc type!")(static_cast <bool> ((VT == MVT::f32 || VT == MVT::f64 || VT == MVT::f128 || VT == MVT::ppcf128) && "Unsupported setcc type!" ) ? void (0) : __assert_fail ("(VT == MVT::f32 || VT == MVT::f64 || VT == MVT::f128 || VT == MVT::ppcf128) && \"Unsupported setcc type!\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 306, __extension__ __PRETTY_FUNCTION__)); | ||||||||||
307 | |||||||||||
308 | // Expand into one or more soft-fp libcall(s). | ||||||||||
309 | RTLIB::Libcall LC1 = RTLIB::UNKNOWN_LIBCALL, LC2 = RTLIB::UNKNOWN_LIBCALL; | ||||||||||
310 | bool ShouldInvertCC = false; | ||||||||||
311 | switch (CCCode) { | ||||||||||
312 | case ISD::SETEQ: | ||||||||||
313 | case ISD::SETOEQ: | ||||||||||
314 | LC1 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : | ||||||||||
315 | (VT == MVT::f64) ? RTLIB::OEQ_F64 : | ||||||||||
316 | (VT == MVT::f128) ? RTLIB::OEQ_F128 : RTLIB::OEQ_PPCF128; | ||||||||||
317 | break; | ||||||||||
318 | case ISD::SETNE: | ||||||||||
319 | case ISD::SETUNE: | ||||||||||
320 | LC1 = (VT == MVT::f32) ? RTLIB::UNE_F32 : | ||||||||||
321 | (VT == MVT::f64) ? RTLIB::UNE_F64 : | ||||||||||
322 | (VT == MVT::f128) ? RTLIB::UNE_F128 : RTLIB::UNE_PPCF128; | ||||||||||
323 | break; | ||||||||||
324 | case ISD::SETGE: | ||||||||||
325 | case ISD::SETOGE: | ||||||||||
326 | LC1 = (VT == MVT::f32) ? RTLIB::OGE_F32 : | ||||||||||
327 | (VT == MVT::f64) ? RTLIB::OGE_F64 : | ||||||||||
328 | (VT == MVT::f128) ? RTLIB::OGE_F128 : RTLIB::OGE_PPCF128; | ||||||||||
329 | break; | ||||||||||
330 | case ISD::SETLT: | ||||||||||
331 | case ISD::SETOLT: | ||||||||||
332 | LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : | ||||||||||
333 | (VT == MVT::f64) ? RTLIB::OLT_F64 : | ||||||||||
334 | (VT == MVT::f128) ? RTLIB::OLT_F128 : RTLIB::OLT_PPCF128; | ||||||||||
335 | break; | ||||||||||
336 | case ISD::SETLE: | ||||||||||
337 | case ISD::SETOLE: | ||||||||||
338 | LC1 = (VT == MVT::f32) ? RTLIB::OLE_F32 : | ||||||||||
339 | (VT == MVT::f64) ? RTLIB::OLE_F64 : | ||||||||||
340 | (VT == MVT::f128) ? RTLIB::OLE_F128 : RTLIB::OLE_PPCF128; | ||||||||||
341 | break; | ||||||||||
342 | case ISD::SETGT: | ||||||||||
343 | case ISD::SETOGT: | ||||||||||
344 | LC1 = (VT == MVT::f32) ? RTLIB::OGT_F32 : | ||||||||||
345 | (VT == MVT::f64) ? RTLIB::OGT_F64 : | ||||||||||
346 | (VT == MVT::f128) ? RTLIB::OGT_F128 : RTLIB::OGT_PPCF128; | ||||||||||
347 | break; | ||||||||||
348 | case ISD::SETO: | ||||||||||
349 | ShouldInvertCC = true; | ||||||||||
350 | LLVM_FALLTHROUGH[[gnu::fallthrough]]; | ||||||||||
351 | case ISD::SETUO: | ||||||||||
352 | LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : | ||||||||||
353 | (VT == MVT::f64) ? RTLIB::UO_F64 : | ||||||||||
354 | (VT == MVT::f128) ? RTLIB::UO_F128 : RTLIB::UO_PPCF128; | ||||||||||
355 | break; | ||||||||||
356 | case ISD::SETONE: | ||||||||||
357 | // SETONE = O && UNE | ||||||||||
358 | ShouldInvertCC = true; | ||||||||||
359 | LLVM_FALLTHROUGH[[gnu::fallthrough]]; | ||||||||||
360 | case ISD::SETUEQ: | ||||||||||
361 | LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : | ||||||||||
362 | (VT == MVT::f64) ? RTLIB::UO_F64 : | ||||||||||
363 | (VT == MVT::f128) ? RTLIB::UO_F128 : RTLIB::UO_PPCF128; | ||||||||||
364 | LC2 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : | ||||||||||
365 | (VT == MVT::f64) ? RTLIB::OEQ_F64 : | ||||||||||
366 | (VT == MVT::f128) ? RTLIB::OEQ_F128 : RTLIB::OEQ_PPCF128; | ||||||||||
367 | break; | ||||||||||
368 | default: | ||||||||||
369 | // Invert CC for unordered comparisons | ||||||||||
370 | ShouldInvertCC = true; | ||||||||||
371 | switch (CCCode) { | ||||||||||
372 | case ISD::SETULT: | ||||||||||
373 | LC1 = (VT == MVT::f32) ? RTLIB::OGE_F32 : | ||||||||||
374 | (VT == MVT::f64) ? RTLIB::OGE_F64 : | ||||||||||
375 | (VT == MVT::f128) ? RTLIB::OGE_F128 : RTLIB::OGE_PPCF128; | ||||||||||
376 | break; | ||||||||||
377 | case ISD::SETULE: | ||||||||||
378 | LC1 = (VT == MVT::f32) ? RTLIB::OGT_F32 : | ||||||||||
379 | (VT == MVT::f64) ? RTLIB::OGT_F64 : | ||||||||||
380 | (VT == MVT::f128) ? RTLIB::OGT_F128 : RTLIB::OGT_PPCF128; | ||||||||||
381 | break; | ||||||||||
382 | case ISD::SETUGT: | ||||||||||
383 | LC1 = (VT == MVT::f32) ? RTLIB::OLE_F32 : | ||||||||||
384 | (VT == MVT::f64) ? RTLIB::OLE_F64 : | ||||||||||
385 | (VT == MVT::f128) ? RTLIB::OLE_F128 : RTLIB::OLE_PPCF128; | ||||||||||
386 | break; | ||||||||||
387 | case ISD::SETUGE: | ||||||||||
388 | LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : | ||||||||||
389 | (VT == MVT::f64) ? RTLIB::OLT_F64 : | ||||||||||
390 | (VT == MVT::f128) ? RTLIB::OLT_F128 : RTLIB::OLT_PPCF128; | ||||||||||
391 | break; | ||||||||||
392 | default: llvm_unreachable("Do not know how to soften this setcc!")::llvm::llvm_unreachable_internal("Do not know how to soften this setcc!" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 392); | ||||||||||
393 | } | ||||||||||
394 | } | ||||||||||
395 | |||||||||||
396 | // Use the target specific return value for comparions lib calls. | ||||||||||
397 | EVT RetVT = getCmpLibcallReturnType(); | ||||||||||
398 | SDValue Ops[2] = {NewLHS, NewRHS}; | ||||||||||
399 | TargetLowering::MakeLibCallOptions CallOptions; | ||||||||||
400 | EVT OpsVT[2] = { OldLHS.getValueType(), | ||||||||||
401 | OldRHS.getValueType() }; | ||||||||||
402 | CallOptions.setTypeListBeforeSoften(OpsVT, RetVT, true); | ||||||||||
403 | auto Call = makeLibCall(DAG, LC1, RetVT, Ops, CallOptions, dl, Chain); | ||||||||||
404 | NewLHS = Call.first; | ||||||||||
405 | NewRHS = DAG.getConstant(0, dl, RetVT); | ||||||||||
406 | |||||||||||
407 | CCCode = getCmpLibcallCC(LC1); | ||||||||||
408 | if (ShouldInvertCC) { | ||||||||||
409 | assert(RetVT.isInteger())(static_cast <bool> (RetVT.isInteger()) ? void (0) : __assert_fail ("RetVT.isInteger()", "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 409, __extension__ __PRETTY_FUNCTION__)); | ||||||||||
410 | CCCode = getSetCCInverse(CCCode, RetVT); | ||||||||||
411 | } | ||||||||||
412 | |||||||||||
413 | if (LC2 == RTLIB::UNKNOWN_LIBCALL) { | ||||||||||
414 | // Update Chain. | ||||||||||
415 | Chain = Call.second; | ||||||||||
416 | } else { | ||||||||||
417 | EVT SetCCVT = | ||||||||||
418 | getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), RetVT); | ||||||||||
419 | SDValue Tmp = DAG.getSetCC(dl, SetCCVT, NewLHS, NewRHS, CCCode); | ||||||||||
420 | auto Call2 = makeLibCall(DAG, LC2, RetVT, Ops, CallOptions, dl, Chain); | ||||||||||
421 | CCCode = getCmpLibcallCC(LC2); | ||||||||||
422 | if (ShouldInvertCC) | ||||||||||
423 | CCCode = getSetCCInverse(CCCode, RetVT); | ||||||||||
424 | NewLHS = DAG.getSetCC(dl, SetCCVT, Call2.first, NewRHS, CCCode); | ||||||||||
425 | if (Chain) | ||||||||||
426 | Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Call.second, | ||||||||||
427 | Call2.second); | ||||||||||
428 | NewLHS = DAG.getNode(ShouldInvertCC ? ISD::AND : ISD::OR, dl, | ||||||||||
429 | Tmp.getValueType(), Tmp, NewLHS); | ||||||||||
430 | NewRHS = SDValue(); | ||||||||||
431 | } | ||||||||||
432 | } | ||||||||||
433 | |||||||||||
434 | /// Return the entry encoding for a jump table in the current function. The | ||||||||||
435 | /// returned value is a member of the MachineJumpTableInfo::JTEntryKind enum. | ||||||||||
436 | unsigned TargetLowering::getJumpTableEncoding() const { | ||||||||||
437 | // In non-pic modes, just use the address of a block. | ||||||||||
438 | if (!isPositionIndependent()) | ||||||||||
439 | return MachineJumpTableInfo::EK_BlockAddress; | ||||||||||
440 | |||||||||||
441 | // In PIC mode, if the target supports a GPRel32 directive, use it. | ||||||||||
442 | if (getTargetMachine().getMCAsmInfo()->getGPRel32Directive() != nullptr) | ||||||||||
443 | return MachineJumpTableInfo::EK_GPRel32BlockAddress; | ||||||||||
444 | |||||||||||
445 | // Otherwise, use a label difference. | ||||||||||
446 | return MachineJumpTableInfo::EK_LabelDifference32; | ||||||||||
447 | } | ||||||||||
448 | |||||||||||
449 | SDValue TargetLowering::getPICJumpTableRelocBase(SDValue Table, | ||||||||||
450 | SelectionDAG &DAG) const { | ||||||||||
451 | // If our PIC model is GP relative, use the global offset table as the base. | ||||||||||
452 | unsigned JTEncoding = getJumpTableEncoding(); | ||||||||||
453 | |||||||||||
454 | if ((JTEncoding == MachineJumpTableInfo::EK_GPRel64BlockAddress) || | ||||||||||
455 | (JTEncoding == MachineJumpTableInfo::EK_GPRel32BlockAddress)) | ||||||||||
456 | return DAG.getGLOBAL_OFFSET_TABLE(getPointerTy(DAG.getDataLayout())); | ||||||||||
457 | |||||||||||
458 | return Table; | ||||||||||
459 | } | ||||||||||
460 | |||||||||||
461 | /// This returns the relocation base for the given PIC jumptable, the same as | ||||||||||
462 | /// getPICJumpTableRelocBase, but as an MCExpr. | ||||||||||
463 | const MCExpr * | ||||||||||
464 | TargetLowering::getPICJumpTableRelocBaseExpr(const MachineFunction *MF, | ||||||||||
465 | unsigned JTI,MCContext &Ctx) const{ | ||||||||||
466 | // The normal PIC reloc base is the label at the start of the jump table. | ||||||||||
467 | return MCSymbolRefExpr::create(MF->getJTISymbol(JTI, Ctx), Ctx); | ||||||||||
468 | } | ||||||||||
469 | |||||||||||
470 | bool | ||||||||||
471 | TargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const { | ||||||||||
472 | const TargetMachine &TM = getTargetMachine(); | ||||||||||
473 | const GlobalValue *GV = GA->getGlobal(); | ||||||||||
474 | |||||||||||
475 | // If the address is not even local to this DSO we will have to load it from | ||||||||||
476 | // a got and then add the offset. | ||||||||||
477 | if (!TM.shouldAssumeDSOLocal(*GV->getParent(), GV)) | ||||||||||
478 | return false; | ||||||||||
479 | |||||||||||
480 | // If the code is position independent we will have to add a base register. | ||||||||||
481 | if (isPositionIndependent()) | ||||||||||
482 | return false; | ||||||||||
483 | |||||||||||
484 | // Otherwise we can do it. | ||||||||||
485 | return true; | ||||||||||
486 | } | ||||||||||
487 | |||||||||||
488 | //===----------------------------------------------------------------------===// | ||||||||||
489 | // Optimization Methods | ||||||||||
490 | //===----------------------------------------------------------------------===// | ||||||||||
491 | |||||||||||
492 | /// If the specified instruction has a constant integer operand and there are | ||||||||||
493 | /// bits set in that constant that are not demanded, then clear those bits and | ||||||||||
494 | /// return true. | ||||||||||
495 | bool TargetLowering::ShrinkDemandedConstant(SDValue Op, | ||||||||||
496 | const APInt &DemandedBits, | ||||||||||
497 | const APInt &DemandedElts, | ||||||||||
498 | TargetLoweringOpt &TLO) const { | ||||||||||
499 | SDLoc DL(Op); | ||||||||||
500 | unsigned Opcode = Op.getOpcode(); | ||||||||||
501 | |||||||||||
502 | // Do target-specific constant optimization. | ||||||||||
503 | if (targetShrinkDemandedConstant(Op, DemandedBits, DemandedElts, TLO)) | ||||||||||
504 | return TLO.New.getNode(); | ||||||||||
505 | |||||||||||
506 | // FIXME: ISD::SELECT, ISD::SELECT_CC | ||||||||||
507 | switch (Opcode) { | ||||||||||
508 | default: | ||||||||||
509 | break; | ||||||||||
510 | case ISD::XOR: | ||||||||||
511 | case ISD::AND: | ||||||||||
512 | case ISD::OR: { | ||||||||||
513 | auto *Op1C = dyn_cast<ConstantSDNode>(Op.getOperand(1)); | ||||||||||
514 | if (!Op1C || Op1C->isOpaque()) | ||||||||||
515 | return false; | ||||||||||
516 | |||||||||||
517 | // If this is a 'not' op, don't touch it because that's a canonical form. | ||||||||||
518 | const APInt &C = Op1C->getAPIntValue(); | ||||||||||
519 | if (Opcode == ISD::XOR && DemandedBits.isSubsetOf(C)) | ||||||||||
520 | return false; | ||||||||||
521 | |||||||||||
522 | if (!C.isSubsetOf(DemandedBits)) { | ||||||||||
523 | EVT VT = Op.getValueType(); | ||||||||||
524 | SDValue NewC = TLO.DAG.getConstant(DemandedBits & C, DL, VT); | ||||||||||
525 | SDValue NewOp = TLO.DAG.getNode(Opcode, DL, VT, Op.getOperand(0), NewC); | ||||||||||
526 | return TLO.CombineTo(Op, NewOp); | ||||||||||
527 | } | ||||||||||
528 | |||||||||||
529 | break; | ||||||||||
530 | } | ||||||||||
531 | } | ||||||||||
532 | |||||||||||
533 | return false; | ||||||||||
534 | } | ||||||||||
535 | |||||||||||
536 | bool TargetLowering::ShrinkDemandedConstant(SDValue Op, | ||||||||||
537 | const APInt &DemandedBits, | ||||||||||
538 | TargetLoweringOpt &TLO) const { | ||||||||||
539 | EVT VT = Op.getValueType(); | ||||||||||
540 | APInt DemandedElts = VT.isVector() | ||||||||||
541 | ? APInt::getAllOnes(VT.getVectorNumElements()) | ||||||||||
542 | : APInt(1, 1); | ||||||||||
543 | return ShrinkDemandedConstant(Op, DemandedBits, DemandedElts, TLO); | ||||||||||
544 | } | ||||||||||
545 | |||||||||||
546 | /// Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the casts are free. | ||||||||||
547 | /// This uses isZExtFree and ZERO_EXTEND for the widening cast, but it could be | ||||||||||
548 | /// generalized for targets with other types of implicit widening casts. | ||||||||||
549 | bool TargetLowering::ShrinkDemandedOp(SDValue Op, unsigned BitWidth, | ||||||||||
550 | const APInt &Demanded, | ||||||||||
551 | TargetLoweringOpt &TLO) const { | ||||||||||
552 | assert(Op.getNumOperands() == 2 &&(static_cast <bool> (Op.getNumOperands() == 2 && "ShrinkDemandedOp only supports binary operators!") ? void ( 0) : __assert_fail ("Op.getNumOperands() == 2 && \"ShrinkDemandedOp only supports binary operators!\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 553, __extension__ __PRETTY_FUNCTION__)) | ||||||||||
553 | "ShrinkDemandedOp only supports binary operators!")(static_cast <bool> (Op.getNumOperands() == 2 && "ShrinkDemandedOp only supports binary operators!") ? void ( 0) : __assert_fail ("Op.getNumOperands() == 2 && \"ShrinkDemandedOp only supports binary operators!\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 553, __extension__ __PRETTY_FUNCTION__)); | ||||||||||
554 | assert(Op.getNode()->getNumValues() == 1 &&(static_cast <bool> (Op.getNode()->getNumValues() == 1 && "ShrinkDemandedOp only supports nodes with one result!" ) ? void (0) : __assert_fail ("Op.getNode()->getNumValues() == 1 && \"ShrinkDemandedOp only supports nodes with one result!\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 555, __extension__ __PRETTY_FUNCTION__)) | ||||||||||
555 | "ShrinkDemandedOp only supports nodes with one result!")(static_cast <bool> (Op.getNode()->getNumValues() == 1 && "ShrinkDemandedOp only supports nodes with one result!" ) ? void (0) : __assert_fail ("Op.getNode()->getNumValues() == 1 && \"ShrinkDemandedOp only supports nodes with one result!\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 555, __extension__ __PRETTY_FUNCTION__)); | ||||||||||
556 | |||||||||||
557 | SelectionDAG &DAG = TLO.DAG; | ||||||||||
558 | SDLoc dl(Op); | ||||||||||
559 | |||||||||||
560 | // Early return, as this function cannot handle vector types. | ||||||||||
561 | if (Op.getValueType().isVector()) | ||||||||||
562 | return false; | ||||||||||
563 | |||||||||||
564 | // Don't do this if the node has another user, which may require the | ||||||||||
565 | // full value. | ||||||||||
566 | if (!Op.getNode()->hasOneUse()) | ||||||||||
567 | return false; | ||||||||||
568 | |||||||||||
569 | // Search for the smallest integer type with free casts to and from | ||||||||||
570 | // Op's type. For expedience, just check power-of-2 integer types. | ||||||||||
571 | const TargetLowering &TLI = DAG.getTargetLoweringInfo(); | ||||||||||
572 | unsigned DemandedSize = Demanded.getActiveBits(); | ||||||||||
573 | unsigned SmallVTBits = DemandedSize; | ||||||||||
574 | if (!isPowerOf2_32(SmallVTBits)) | ||||||||||
575 | SmallVTBits = NextPowerOf2(SmallVTBits); | ||||||||||
576 | for (; SmallVTBits < BitWidth; SmallVTBits = NextPowerOf2(SmallVTBits)) { | ||||||||||
577 | EVT SmallVT = EVT::getIntegerVT(*DAG.getContext(), SmallVTBits); | ||||||||||
578 | if (TLI.isTruncateFree(Op.getValueType(), SmallVT) && | ||||||||||
579 | TLI.isZExtFree(SmallVT, Op.getValueType())) { | ||||||||||
580 | // We found a type with free casts. | ||||||||||
581 | SDValue X = DAG.getNode( | ||||||||||
582 | Op.getOpcode(), dl, SmallVT, | ||||||||||
583 | DAG.getNode(ISD::TRUNCATE, dl, SmallVT, Op.getOperand(0)), | ||||||||||
584 | DAG.getNode(ISD::TRUNCATE, dl, SmallVT, Op.getOperand(1))); | ||||||||||
585 | assert(DemandedSize <= SmallVTBits && "Narrowed below demanded bits?")(static_cast <bool> (DemandedSize <= SmallVTBits && "Narrowed below demanded bits?") ? void (0) : __assert_fail ( "DemandedSize <= SmallVTBits && \"Narrowed below demanded bits?\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 585, __extension__ __PRETTY_FUNCTION__)); | ||||||||||
586 | SDValue Z = DAG.getNode(ISD::ANY_EXTEND, dl, Op.getValueType(), X); | ||||||||||
587 | return TLO.CombineTo(Op, Z); | ||||||||||
588 | } | ||||||||||
589 | } | ||||||||||
590 | return false; | ||||||||||
591 | } | ||||||||||
592 | |||||||||||
593 | bool TargetLowering::SimplifyDemandedBits(SDValue Op, const APInt &DemandedBits, | ||||||||||
594 | DAGCombinerInfo &DCI) const { | ||||||||||
595 | SelectionDAG &DAG = DCI.DAG; | ||||||||||
596 | TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(), | ||||||||||
597 | !DCI.isBeforeLegalizeOps()); | ||||||||||
598 | KnownBits Known; | ||||||||||
599 | |||||||||||
600 | bool Simplified = SimplifyDemandedBits(Op, DemandedBits, Known, TLO); | ||||||||||
601 | if (Simplified) { | ||||||||||
602 | DCI.AddToWorklist(Op.getNode()); | ||||||||||
603 | DCI.CommitTargetLoweringOpt(TLO); | ||||||||||
604 | } | ||||||||||
605 | return Simplified; | ||||||||||
606 | } | ||||||||||
607 | |||||||||||
608 | bool TargetLowering::SimplifyDemandedBits(SDValue Op, const APInt &DemandedBits, | ||||||||||
609 | KnownBits &Known, | ||||||||||
610 | TargetLoweringOpt &TLO, | ||||||||||
611 | unsigned Depth, | ||||||||||
612 | bool AssumeSingleUse) const { | ||||||||||
613 | EVT VT = Op.getValueType(); | ||||||||||
614 | |||||||||||
615 | // TODO: We can probably do more work on calculating the known bits and | ||||||||||
616 | // simplifying the operations for scalable vectors, but for now we just | ||||||||||
617 | // bail out. | ||||||||||
618 | if (VT.isScalableVector()) { | ||||||||||
619 | // Pretend we don't know anything for now. | ||||||||||
620 | Known = KnownBits(DemandedBits.getBitWidth()); | ||||||||||
621 | return false; | ||||||||||
622 | } | ||||||||||
623 | |||||||||||
624 | APInt DemandedElts = VT.isVector() | ||||||||||
625 | ? APInt::getAllOnes(VT.getVectorNumElements()) | ||||||||||
626 | : APInt(1, 1); | ||||||||||
627 | return SimplifyDemandedBits(Op, DemandedBits, DemandedElts, Known, TLO, Depth, | ||||||||||
628 | AssumeSingleUse); | ||||||||||
629 | } | ||||||||||
630 | |||||||||||
631 | // TODO: Can we merge SelectionDAG::GetDemandedBits into this? | ||||||||||
632 | // TODO: Under what circumstances can we create nodes? Constant folding? | ||||||||||
633 | SDValue TargetLowering::SimplifyMultipleUseDemandedBits( | ||||||||||
634 | SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts, | ||||||||||
635 | SelectionDAG &DAG, unsigned Depth) const { | ||||||||||
636 | // Limit search depth. | ||||||||||
637 | if (Depth >= SelectionDAG::MaxRecursionDepth) | ||||||||||
| |||||||||||
638 | return SDValue(); | ||||||||||
639 | |||||||||||
640 | // Ignore UNDEFs. | ||||||||||
641 | if (Op.isUndef()) | ||||||||||
642 | return SDValue(); | ||||||||||
643 | |||||||||||
644 | // Not demanding any bits/elts from Op. | ||||||||||
645 | if (DemandedBits == 0 || DemandedElts == 0) | ||||||||||
646 | return DAG.getUNDEF(Op.getValueType()); | ||||||||||
647 | |||||||||||
648 | unsigned NumElts = DemandedElts.getBitWidth(); | ||||||||||
649 | unsigned BitWidth = DemandedBits.getBitWidth(); | ||||||||||
650 | KnownBits LHSKnown, RHSKnown; | ||||||||||
651 | switch (Op.getOpcode()) { | ||||||||||
652 | case ISD::BITCAST: { | ||||||||||
653 | SDValue Src = peekThroughBitcasts(Op.getOperand(0)); | ||||||||||
654 | EVT SrcVT = Src.getValueType(); | ||||||||||
655 | EVT DstVT = Op.getValueType(); | ||||||||||
656 | if (SrcVT == DstVT) | ||||||||||
657 | return Src; | ||||||||||
658 | |||||||||||
659 | unsigned NumSrcEltBits = SrcVT.getScalarSizeInBits(); | ||||||||||
660 | unsigned NumDstEltBits = DstVT.getScalarSizeInBits(); | ||||||||||
661 | if (NumSrcEltBits == NumDstEltBits) | ||||||||||
662 | if (SDValue V = SimplifyMultipleUseDemandedBits( | ||||||||||
663 | Src, DemandedBits, DemandedElts, DAG, Depth + 1)) | ||||||||||
664 | return DAG.getBitcast(DstVT, V); | ||||||||||
665 | |||||||||||
666 | // TODO - bigendian once we have test coverage. | ||||||||||
667 | if (SrcVT.isVector() && (NumDstEltBits % NumSrcEltBits) == 0 && | ||||||||||
668 | DAG.getDataLayout().isLittleEndian()) { | ||||||||||
669 | unsigned Scale = NumDstEltBits / NumSrcEltBits; | ||||||||||
670 | unsigned NumSrcElts = SrcVT.getVectorNumElements(); | ||||||||||
671 | APInt DemandedSrcBits = APInt::getZero(NumSrcEltBits); | ||||||||||
672 | APInt DemandedSrcElts = APInt::getZero(NumSrcElts); | ||||||||||
673 | for (unsigned i = 0; i != Scale; ++i) { | ||||||||||
674 | unsigned Offset = i * NumSrcEltBits; | ||||||||||
675 | APInt Sub = DemandedBits.extractBits(NumSrcEltBits, Offset); | ||||||||||
676 | if (!Sub.isZero()) { | ||||||||||
677 | DemandedSrcBits |= Sub; | ||||||||||
678 | for (unsigned j = 0; j != NumElts; ++j) | ||||||||||
679 | if (DemandedElts[j]) | ||||||||||
680 | DemandedSrcElts.setBit((j * Scale) + i); | ||||||||||
681 | } | ||||||||||
682 | } | ||||||||||
683 | |||||||||||
684 | if (SDValue V = SimplifyMultipleUseDemandedBits( | ||||||||||
685 | Src, DemandedSrcBits, DemandedSrcElts, DAG, Depth + 1)) | ||||||||||
686 | return DAG.getBitcast(DstVT, V); | ||||||||||
687 | } | ||||||||||
688 | |||||||||||
689 | // TODO - bigendian once we have test coverage. | ||||||||||
690 | if ((NumSrcEltBits % NumDstEltBits) == 0 && | ||||||||||
691 | DAG.getDataLayout().isLittleEndian()) { | ||||||||||
692 | unsigned Scale = NumSrcEltBits / NumDstEltBits; | ||||||||||
693 | unsigned NumSrcElts = SrcVT.isVector() ? SrcVT.getVectorNumElements() : 1; | ||||||||||
694 | APInt DemandedSrcBits = APInt::getZero(NumSrcEltBits); | ||||||||||
695 | APInt DemandedSrcElts = APInt::getZero(NumSrcElts); | ||||||||||
696 | for (unsigned i = 0; i
| ||||||||||
697 | if (DemandedElts[i]) { | ||||||||||
698 | unsigned Offset = (i % Scale) * NumDstEltBits; | ||||||||||
| |||||||||||
699 | DemandedSrcBits.insertBits(DemandedBits, Offset); | ||||||||||
700 | DemandedSrcElts.setBit(i / Scale); | ||||||||||
701 | } | ||||||||||
702 | |||||||||||
703 | if (SDValue V = SimplifyMultipleUseDemandedBits( | ||||||||||
704 | Src, DemandedSrcBits, DemandedSrcElts, DAG, Depth + 1)) | ||||||||||
705 | return DAG.getBitcast(DstVT, V); | ||||||||||
706 | } | ||||||||||
707 | |||||||||||
708 | break; | ||||||||||
709 | } | ||||||||||
710 | case ISD::AND: { | ||||||||||
711 | LHSKnown = DAG.computeKnownBits(Op.getOperand(0), DemandedElts, Depth + 1); | ||||||||||
712 | RHSKnown = DAG.computeKnownBits(Op.getOperand(1), DemandedElts, Depth + 1); | ||||||||||
713 | |||||||||||
714 | // If all of the demanded bits are known 1 on one side, return the other. | ||||||||||
715 | // These bits cannot contribute to the result of the 'and' in this | ||||||||||
716 | // context. | ||||||||||
717 | if (DemandedBits.isSubsetOf(LHSKnown.Zero | RHSKnown.One)) | ||||||||||
718 | return Op.getOperand(0); | ||||||||||
719 | if (DemandedBits.isSubsetOf(RHSKnown.Zero | LHSKnown.One)) | ||||||||||
720 | return Op.getOperand(1); | ||||||||||
721 | break; | ||||||||||
722 | } | ||||||||||
723 | case ISD::OR: { | ||||||||||
724 | LHSKnown = DAG.computeKnownBits(Op.getOperand(0), DemandedElts, Depth + 1); | ||||||||||
725 | RHSKnown = DAG.computeKnownBits(Op.getOperand(1), DemandedElts, Depth + 1); | ||||||||||
726 | |||||||||||
727 | // If all of the demanded bits are known zero on one side, return the | ||||||||||
728 | // other. These bits cannot contribute to the result of the 'or' in this | ||||||||||
729 | // context. | ||||||||||
730 | if (DemandedBits.isSubsetOf(LHSKnown.One | RHSKnown.Zero)) | ||||||||||
731 | return Op.getOperand(0); | ||||||||||
732 | if (DemandedBits.isSubsetOf(RHSKnown.One | LHSKnown.Zero)) | ||||||||||
733 | return Op.getOperand(1); | ||||||||||
734 | break; | ||||||||||
735 | } | ||||||||||
736 | case ISD::XOR: { | ||||||||||
737 | LHSKnown = DAG.computeKnownBits(Op.getOperand(0), DemandedElts, Depth + 1); | ||||||||||
738 | RHSKnown = DAG.computeKnownBits(Op.getOperand(1), DemandedElts, Depth + 1); | ||||||||||
739 | |||||||||||
740 | // If all of the demanded bits are known zero on one side, return the | ||||||||||
741 | // other. | ||||||||||
742 | if (DemandedBits.isSubsetOf(RHSKnown.Zero)) | ||||||||||
743 | return Op.getOperand(0); | ||||||||||
744 | if (DemandedBits.isSubsetOf(LHSKnown.Zero)) | ||||||||||
745 | return Op.getOperand(1); | ||||||||||
746 | break; | ||||||||||
747 | } | ||||||||||
748 | case ISD::SHL: { | ||||||||||
749 | // If we are only demanding sign bits then we can use the shift source | ||||||||||
750 | // directly. | ||||||||||
751 | if (const APInt *MaxSA = | ||||||||||
752 | DAG.getValidMaximumShiftAmountConstant(Op, DemandedElts)) { | ||||||||||
753 | SDValue Op0 = Op.getOperand(0); | ||||||||||
754 | unsigned ShAmt = MaxSA->getZExtValue(); | ||||||||||
755 | unsigned NumSignBits = | ||||||||||
756 | DAG.ComputeNumSignBits(Op0, DemandedElts, Depth + 1); | ||||||||||
757 | unsigned UpperDemandedBits = BitWidth - DemandedBits.countTrailingZeros(); | ||||||||||
758 | if (NumSignBits > ShAmt && (NumSignBits - ShAmt) >= (UpperDemandedBits)) | ||||||||||
759 | return Op0; | ||||||||||
760 | } | ||||||||||
761 | break; | ||||||||||
762 | } | ||||||||||
763 | case ISD::SETCC: { | ||||||||||
764 | SDValue Op0 = Op.getOperand(0); | ||||||||||
765 | SDValue Op1 = Op.getOperand(1); | ||||||||||
766 | ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); | ||||||||||
767 | // If (1) we only need the sign-bit, (2) the setcc operands are the same | ||||||||||
768 | // width as the setcc result, and (3) the result of a setcc conforms to 0 or | ||||||||||
769 | // -1, we may be able to bypass the setcc. | ||||||||||
770 | if (DemandedBits.isSignMask() && | ||||||||||
771 | Op0.getScalarValueSizeInBits() == BitWidth && | ||||||||||
772 | getBooleanContents(Op0.getValueType()) == | ||||||||||
773 | BooleanContent::ZeroOrNegativeOneBooleanContent) { | ||||||||||
774 | // If we're testing X < 0, then this compare isn't needed - just use X! | ||||||||||
775 | // FIXME: We're limiting to integer types here, but this should also work | ||||||||||
776 | // if we don't care about FP signed-zero. The use of SETLT with FP means | ||||||||||
777 | // that we don't care about NaNs. | ||||||||||
778 | if (CC == ISD::SETLT && Op1.getValueType().isInteger() && | ||||||||||
779 | (isNullConstant(Op1) || ISD::isBuildVectorAllZeros(Op1.getNode()))) | ||||||||||
780 | return Op0; | ||||||||||
781 | } | ||||||||||
782 | break; | ||||||||||
783 | } | ||||||||||
784 | case ISD::SIGN_EXTEND_INREG: { | ||||||||||
785 | // If none of the extended bits are demanded, eliminate the sextinreg. | ||||||||||
786 | SDValue Op0 = Op.getOperand(0); | ||||||||||
787 | EVT ExVT = cast<VTSDNode>(Op.getOperand(1))->getVT(); | ||||||||||
788 | unsigned ExBits = ExVT.getScalarSizeInBits(); | ||||||||||
789 | if (DemandedBits.getActiveBits() <= ExBits) | ||||||||||
790 | return Op0; | ||||||||||
791 | // If the input is already sign extended, just drop the extension. | ||||||||||
792 | unsigned NumSignBits = DAG.ComputeNumSignBits(Op0, DemandedElts, Depth + 1); | ||||||||||
793 | if (NumSignBits >= (BitWidth - ExBits + 1)) | ||||||||||
794 | return Op0; | ||||||||||
795 | break; | ||||||||||
796 | } | ||||||||||
797 | case ISD::ANY_EXTEND_VECTOR_INREG: | ||||||||||
798 | case ISD::SIGN_EXTEND_VECTOR_INREG: | ||||||||||
799 | case ISD::ZERO_EXTEND_VECTOR_INREG: { | ||||||||||
800 | // If we only want the lowest element and none of extended bits, then we can | ||||||||||
801 | // return the bitcasted source vector. | ||||||||||
802 | SDValue Src = Op.getOperand(0); | ||||||||||
803 | EVT SrcVT = Src.getValueType(); | ||||||||||
804 | EVT DstVT = Op.getValueType(); | ||||||||||
805 | if (DemandedElts == 1 && DstVT.getSizeInBits() == SrcVT.getSizeInBits() && | ||||||||||
806 | DAG.getDataLayout().isLittleEndian() && | ||||||||||
807 | DemandedBits.getActiveBits() <= SrcVT.getScalarSizeInBits()) { | ||||||||||
808 | return DAG.getBitcast(DstVT, Src); | ||||||||||
809 | } | ||||||||||
810 | break; | ||||||||||
811 | } | ||||||||||
812 | case ISD::INSERT_VECTOR_ELT: { | ||||||||||
813 | // If we don't demand the inserted element, return the base vector. | ||||||||||
814 | SDValue Vec = Op.getOperand(0); | ||||||||||
815 | auto *CIdx = dyn_cast<ConstantSDNode>(Op.getOperand(2)); | ||||||||||
816 | EVT VecVT = Vec.getValueType(); | ||||||||||
817 | if (CIdx && CIdx->getAPIntValue().ult(VecVT.getVectorNumElements()) && | ||||||||||
818 | !DemandedElts[CIdx->getZExtValue()]) | ||||||||||
819 | return Vec; | ||||||||||
820 | break; | ||||||||||
821 | } | ||||||||||
822 | case ISD::INSERT_SUBVECTOR: { | ||||||||||
823 | SDValue Vec = Op.getOperand(0); | ||||||||||
824 | SDValue Sub = Op.getOperand(1); | ||||||||||
825 | uint64_t Idx = Op.getConstantOperandVal(2); | ||||||||||
826 | unsigned NumSubElts = Sub.getValueType().getVectorNumElements(); | ||||||||||
827 | APInt DemandedSubElts = DemandedElts.extractBits(NumSubElts, Idx); | ||||||||||
828 | // If we don't demand the inserted subvector, return the base vector. | ||||||||||
829 | if (DemandedSubElts == 0) | ||||||||||
830 | return Vec; | ||||||||||
831 | // If this simply widens the lowest subvector, see if we can do it earlier. | ||||||||||
832 | if (Idx == 0 && Vec.isUndef()) { | ||||||||||
833 | if (SDValue NewSub = SimplifyMultipleUseDemandedBits( | ||||||||||
834 | Sub, DemandedBits, DemandedSubElts, DAG, Depth + 1)) | ||||||||||
835 | return DAG.getNode(Op.getOpcode(), SDLoc(Op), Op.getValueType(), | ||||||||||
836 | Op.getOperand(0), NewSub, Op.getOperand(2)); | ||||||||||
837 | } | ||||||||||
838 | break; | ||||||||||
839 | } | ||||||||||
840 | case ISD::VECTOR_SHUFFLE: { | ||||||||||
841 | ArrayRef<int> ShuffleMask = cast<ShuffleVectorSDNode>(Op)->getMask(); | ||||||||||
842 | |||||||||||
843 | // If all the demanded elts are from one operand and are inline, | ||||||||||
844 | // then we can use the operand directly. | ||||||||||
845 | bool AllUndef = true, IdentityLHS = true, IdentityRHS = true; | ||||||||||
846 | for (unsigned i = 0; i != NumElts; ++i) { | ||||||||||
847 | int M = ShuffleMask[i]; | ||||||||||
848 | if (M < 0 || !DemandedElts[i]) | ||||||||||
849 | continue; | ||||||||||
850 | AllUndef = false; | ||||||||||
851 | IdentityLHS &= (M == (int)i); | ||||||||||
852 | IdentityRHS &= ((M - NumElts) == i); | ||||||||||
853 | } | ||||||||||
854 | |||||||||||
855 | if (AllUndef) | ||||||||||
856 | return DAG.getUNDEF(Op.getValueType()); | ||||||||||
857 | if (IdentityLHS) | ||||||||||
858 | return Op.getOperand(0); | ||||||||||
859 | if (IdentityRHS) | ||||||||||
860 | return Op.getOperand(1); | ||||||||||
861 | break; | ||||||||||
862 | } | ||||||||||
863 | default: | ||||||||||
864 | if (Op.getOpcode() >= ISD::BUILTIN_OP_END) | ||||||||||
865 | if (SDValue V = SimplifyMultipleUseDemandedBitsForTargetNode( | ||||||||||
866 | Op, DemandedBits, DemandedElts, DAG, Depth)) | ||||||||||
867 | return V; | ||||||||||
868 | break; | ||||||||||
869 | } | ||||||||||
870 | return SDValue(); | ||||||||||
871 | } | ||||||||||
872 | |||||||||||
873 | SDValue TargetLowering::SimplifyMultipleUseDemandedBits( | ||||||||||
874 | SDValue Op, const APInt &DemandedBits, SelectionDAG &DAG, | ||||||||||
875 | unsigned Depth) const { | ||||||||||
876 | EVT VT = Op.getValueType(); | ||||||||||
877 | APInt DemandedElts = VT.isVector() | ||||||||||
878 | ? APInt::getAllOnes(VT.getVectorNumElements()) | ||||||||||
879 | : APInt(1, 1); | ||||||||||
880 | return SimplifyMultipleUseDemandedBits(Op, DemandedBits, DemandedElts, DAG, | ||||||||||
881 | Depth); | ||||||||||
882 | } | ||||||||||
883 | |||||||||||
884 | SDValue TargetLowering::SimplifyMultipleUseDemandedVectorElts( | ||||||||||
885 | SDValue Op, const APInt &DemandedElts, SelectionDAG &DAG, | ||||||||||
886 | unsigned Depth) const { | ||||||||||
887 | APInt DemandedBits = APInt::getAllOnes(Op.getScalarValueSizeInBits()); | ||||||||||
888 | return SimplifyMultipleUseDemandedBits(Op, DemandedBits, DemandedElts, DAG, | ||||||||||
889 | Depth); | ||||||||||
890 | } | ||||||||||
891 | |||||||||||
892 | /// Look at Op. At this point, we know that only the OriginalDemandedBits of the | ||||||||||
893 | /// result of Op are ever used downstream. If we can use this information to | ||||||||||
894 | /// simplify Op, create a new simplified DAG node and return true, returning the | ||||||||||
895 | /// original and new nodes in Old and New. Otherwise, analyze the expression and | ||||||||||
896 | /// return a mask of Known bits for the expression (used to simplify the | ||||||||||
897 | /// caller). The Known bits may only be accurate for those bits in the | ||||||||||
898 | /// OriginalDemandedBits and OriginalDemandedElts. | ||||||||||
899 | bool TargetLowering::SimplifyDemandedBits( | ||||||||||
900 | SDValue Op, const APInt &OriginalDemandedBits, | ||||||||||
901 | const APInt &OriginalDemandedElts, KnownBits &Known, TargetLoweringOpt &TLO, | ||||||||||
902 | unsigned Depth, bool AssumeSingleUse) const { | ||||||||||
903 | unsigned BitWidth = OriginalDemandedBits.getBitWidth(); | ||||||||||
904 | assert(Op.getScalarValueSizeInBits() == BitWidth &&(static_cast <bool> (Op.getScalarValueSizeInBits() == BitWidth && "Mask size mismatches value type size!") ? void ( 0) : __assert_fail ("Op.getScalarValueSizeInBits() == BitWidth && \"Mask size mismatches value type size!\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 905, __extension__ __PRETTY_FUNCTION__)) | ||||||||||
905 | "Mask size mismatches value type size!")(static_cast <bool> (Op.getScalarValueSizeInBits() == BitWidth && "Mask size mismatches value type size!") ? void ( 0) : __assert_fail ("Op.getScalarValueSizeInBits() == BitWidth && \"Mask size mismatches value type size!\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 905, __extension__ __PRETTY_FUNCTION__)); | ||||||||||
906 | |||||||||||
907 | // Don't know anything. | ||||||||||
908 | Known = KnownBits(BitWidth); | ||||||||||
909 | |||||||||||
910 | // TODO: We can probably do more work on calculating the known bits and | ||||||||||
911 | // simplifying the operations for scalable vectors, but for now we just | ||||||||||
912 | // bail out. | ||||||||||
913 | if (Op.getValueType().isScalableVector()) | ||||||||||
914 | return false; | ||||||||||
915 | |||||||||||
916 | unsigned NumElts = OriginalDemandedElts.getBitWidth(); | ||||||||||
917 | assert((!Op.getValueType().isVector() ||(static_cast <bool> ((!Op.getValueType().isVector() || NumElts == Op.getValueType().getVectorNumElements()) && "Unexpected vector size" ) ? void (0) : __assert_fail ("(!Op.getValueType().isVector() || NumElts == Op.getValueType().getVectorNumElements()) && \"Unexpected vector size\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 919, __extension__ __PRETTY_FUNCTION__)) | ||||||||||
918 | NumElts == Op.getValueType().getVectorNumElements()) &&(static_cast <bool> ((!Op.getValueType().isVector() || NumElts == Op.getValueType().getVectorNumElements()) && "Unexpected vector size" ) ? void (0) : __assert_fail ("(!Op.getValueType().isVector() || NumElts == Op.getValueType().getVectorNumElements()) && \"Unexpected vector size\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 919, __extension__ __PRETTY_FUNCTION__)) | ||||||||||
919 | "Unexpected vector size")(static_cast <bool> ((!Op.getValueType().isVector() || NumElts == Op.getValueType().getVectorNumElements()) && "Unexpected vector size" ) ? void (0) : __assert_fail ("(!Op.getValueType().isVector() || NumElts == Op.getValueType().getVectorNumElements()) && \"Unexpected vector size\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 919, __extension__ __PRETTY_FUNCTION__)); | ||||||||||
920 | |||||||||||
921 | APInt DemandedBits = OriginalDemandedBits; | ||||||||||
922 | APInt DemandedElts = OriginalDemandedElts; | ||||||||||
923 | SDLoc dl(Op); | ||||||||||
924 | auto &DL = TLO.DAG.getDataLayout(); | ||||||||||
925 | |||||||||||
926 | // Undef operand. | ||||||||||
927 | if (Op.isUndef()) | ||||||||||
928 | return false; | ||||||||||
929 | |||||||||||
930 | if (Op.getOpcode() == ISD::Constant) { | ||||||||||
931 | // We know all of the bits for a constant! | ||||||||||
932 | Known = KnownBits::makeConstant(cast<ConstantSDNode>(Op)->getAPIntValue()); | ||||||||||
933 | return false; | ||||||||||
934 | } | ||||||||||
935 | |||||||||||
936 | if (Op.getOpcode() == ISD::ConstantFP) { | ||||||||||
937 | // We know all of the bits for a floating point constant! | ||||||||||
938 | Known = KnownBits::makeConstant( | ||||||||||
939 | cast<ConstantFPSDNode>(Op)->getValueAPF().bitcastToAPInt()); | ||||||||||
940 | return false; | ||||||||||
941 | } | ||||||||||
942 | |||||||||||
943 | // Other users may use these bits. | ||||||||||
944 | EVT VT = Op.getValueType(); | ||||||||||
945 | if (!Op.getNode()->hasOneUse() && !AssumeSingleUse) { | ||||||||||
946 | if (Depth != 0) { | ||||||||||
947 | // If not at the root, Just compute the Known bits to | ||||||||||
948 | // simplify things downstream. | ||||||||||
949 | Known = TLO.DAG.computeKnownBits(Op, DemandedElts, Depth); | ||||||||||
950 | return false; | ||||||||||
951 | } | ||||||||||
952 | // If this is the root being simplified, allow it to have multiple uses, | ||||||||||
953 | // just set the DemandedBits/Elts to all bits. | ||||||||||
954 | DemandedBits = APInt::getAllOnes(BitWidth); | ||||||||||
955 | DemandedElts = APInt::getAllOnes(NumElts); | ||||||||||
956 | } else if (OriginalDemandedBits == 0 || OriginalDemandedElts == 0) { | ||||||||||
957 | // Not demanding any bits/elts from Op. | ||||||||||
958 | return TLO.CombineTo(Op, TLO.DAG.getUNDEF(VT)); | ||||||||||
959 | } else if (Depth >= SelectionDAG::MaxRecursionDepth) { | ||||||||||
960 | // Limit search depth. | ||||||||||
961 | return false; | ||||||||||
962 | } | ||||||||||
963 | |||||||||||
964 | KnownBits Known2; | ||||||||||
965 | switch (Op.getOpcode()) { | ||||||||||
966 | case ISD::TargetConstant: | ||||||||||
967 | llvm_unreachable("Can't simplify this node")::llvm::llvm_unreachable_internal("Can't simplify this node", "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 967); | ||||||||||
968 | case ISD::SCALAR_TO_VECTOR: { | ||||||||||
969 | if (!DemandedElts[0]) | ||||||||||
970 | return TLO.CombineTo(Op, TLO.DAG.getUNDEF(VT)); | ||||||||||
971 | |||||||||||
972 | KnownBits SrcKnown; | ||||||||||
973 | SDValue Src = Op.getOperand(0); | ||||||||||
974 | unsigned SrcBitWidth = Src.getScalarValueSizeInBits(); | ||||||||||
975 | APInt SrcDemandedBits = DemandedBits.zextOrSelf(SrcBitWidth); | ||||||||||
976 | if (SimplifyDemandedBits(Src, SrcDemandedBits, SrcKnown, TLO, Depth + 1)) | ||||||||||
977 | return true; | ||||||||||
978 | |||||||||||
979 | // Upper elements are undef, so only get the knownbits if we just demand | ||||||||||
980 | // the bottom element. | ||||||||||
981 | if (DemandedElts == 1) | ||||||||||
982 | Known = SrcKnown.anyextOrTrunc(BitWidth); | ||||||||||
983 | break; | ||||||||||
984 | } | ||||||||||
985 | case ISD::BUILD_VECTOR: | ||||||||||
986 | // Collect the known bits that are shared by every demanded element. | ||||||||||
987 | // TODO: Call SimplifyDemandedBits for non-constant demanded elements. | ||||||||||
988 | Known = TLO.DAG.computeKnownBits(Op, DemandedElts, Depth); | ||||||||||
989 | return false; // Don't fall through, will infinitely loop. | ||||||||||
990 | case ISD::LOAD: { | ||||||||||
991 | auto *LD = cast<LoadSDNode>(Op); | ||||||||||
992 | if (getTargetConstantFromLoad(LD)) { | ||||||||||
993 | Known = TLO.DAG.computeKnownBits(Op, DemandedElts, Depth); | ||||||||||
994 | return false; // Don't fall through, will infinitely loop. | ||||||||||
995 | } | ||||||||||
996 | if (ISD::isZEXTLoad(Op.getNode()) && Op.getResNo() == 0) { | ||||||||||
997 | // If this is a ZEXTLoad and we are looking at the loaded value. | ||||||||||
998 | EVT MemVT = LD->getMemoryVT(); | ||||||||||
999 | unsigned MemBits = MemVT.getScalarSizeInBits(); | ||||||||||
1000 | Known.Zero.setBitsFrom(MemBits); | ||||||||||
1001 | return false; // Don't fall through, will infinitely loop. | ||||||||||
1002 | } | ||||||||||
1003 | break; | ||||||||||
1004 | } | ||||||||||
1005 | case ISD::INSERT_VECTOR_ELT: { | ||||||||||
1006 | SDValue Vec = Op.getOperand(0); | ||||||||||
1007 | SDValue Scl = Op.getOperand(1); | ||||||||||
1008 | auto *CIdx = dyn_cast<ConstantSDNode>(Op.getOperand(2)); | ||||||||||
1009 | EVT VecVT = Vec.getValueType(); | ||||||||||
1010 | |||||||||||
1011 | // If index isn't constant, assume we need all vector elements AND the | ||||||||||
1012 | // inserted element. | ||||||||||
1013 | APInt DemandedVecElts(DemandedElts); | ||||||||||
1014 | if (CIdx && CIdx->getAPIntValue().ult(VecVT.getVectorNumElements())) { | ||||||||||
1015 | unsigned Idx = CIdx->getZExtValue(); | ||||||||||
1016 | DemandedVecElts.clearBit(Idx); | ||||||||||
1017 | |||||||||||
1018 | // Inserted element is not required. | ||||||||||
1019 | if (!DemandedElts[Idx]) | ||||||||||
1020 | return TLO.CombineTo(Op, Vec); | ||||||||||
1021 | } | ||||||||||
1022 | |||||||||||
1023 | KnownBits KnownScl; | ||||||||||
1024 | unsigned NumSclBits = Scl.getScalarValueSizeInBits(); | ||||||||||
1025 | APInt DemandedSclBits = DemandedBits.zextOrTrunc(NumSclBits); | ||||||||||
1026 | if (SimplifyDemandedBits(Scl, DemandedSclBits, KnownScl, TLO, Depth + 1)) | ||||||||||
1027 | return true; | ||||||||||
1028 | |||||||||||
1029 | Known = KnownScl.anyextOrTrunc(BitWidth); | ||||||||||
1030 | |||||||||||
1031 | KnownBits KnownVec; | ||||||||||
1032 | if (SimplifyDemandedBits(Vec, DemandedBits, DemandedVecElts, KnownVec, TLO, | ||||||||||
1033 | Depth + 1)) | ||||||||||
1034 | return true; | ||||||||||
1035 | |||||||||||
1036 | if (!!DemandedVecElts) | ||||||||||
1037 | Known = KnownBits::commonBits(Known, KnownVec); | ||||||||||
1038 | |||||||||||
1039 | return false; | ||||||||||
1040 | } | ||||||||||
1041 | case ISD::INSERT_SUBVECTOR: { | ||||||||||
1042 | // Demand any elements from the subvector and the remainder from the src its | ||||||||||
1043 | // inserted into. | ||||||||||
1044 | SDValue Src = Op.getOperand(0); | ||||||||||
1045 | SDValue Sub = Op.getOperand(1); | ||||||||||
1046 | uint64_t Idx = Op.getConstantOperandVal(2); | ||||||||||
1047 | unsigned NumSubElts = Sub.getValueType().getVectorNumElements(); | ||||||||||
1048 | APInt DemandedSubElts = DemandedElts.extractBits(NumSubElts, Idx); | ||||||||||
1049 | APInt DemandedSrcElts = DemandedElts; | ||||||||||
1050 | DemandedSrcElts.insertBits(APInt::getZero(NumSubElts), Idx); | ||||||||||
1051 | |||||||||||
1052 | KnownBits KnownSub, KnownSrc; | ||||||||||
1053 | if (SimplifyDemandedBits(Sub, DemandedBits, DemandedSubElts, KnownSub, TLO, | ||||||||||
1054 | Depth + 1)) | ||||||||||
1055 | return true; | ||||||||||
1056 | if (SimplifyDemandedBits(Src, DemandedBits, DemandedSrcElts, KnownSrc, TLO, | ||||||||||
1057 | Depth + 1)) | ||||||||||
1058 | return true; | ||||||||||
1059 | |||||||||||
1060 | Known.Zero.setAllBits(); | ||||||||||
1061 | Known.One.setAllBits(); | ||||||||||
1062 | if (!!DemandedSubElts) | ||||||||||
1063 | Known = KnownBits::commonBits(Known, KnownSub); | ||||||||||
1064 | if (!!DemandedSrcElts) | ||||||||||
1065 | Known = KnownBits::commonBits(Known, KnownSrc); | ||||||||||
1066 | |||||||||||
1067 | // Attempt to avoid multi-use src if we don't need anything from it. | ||||||||||
1068 | if (!DemandedBits.isAllOnes() || !DemandedSubElts.isAllOnes() || | ||||||||||
1069 | !DemandedSrcElts.isAllOnes()) { | ||||||||||
1070 | SDValue NewSub = SimplifyMultipleUseDemandedBits( | ||||||||||
1071 | Sub, DemandedBits, DemandedSubElts, TLO.DAG, Depth + 1); | ||||||||||
1072 | SDValue NewSrc = SimplifyMultipleUseDemandedBits( | ||||||||||
1073 | Src, DemandedBits, DemandedSrcElts, TLO.DAG, Depth + 1); | ||||||||||
1074 | if (NewSub || NewSrc) { | ||||||||||
1075 | NewSub = NewSub ? NewSub : Sub; | ||||||||||
1076 | NewSrc = NewSrc ? NewSrc : Src; | ||||||||||
1077 | SDValue NewOp = TLO.DAG.getNode(Op.getOpcode(), dl, VT, NewSrc, NewSub, | ||||||||||
1078 | Op.getOperand(2)); | ||||||||||
1079 | return TLO.CombineTo(Op, NewOp); | ||||||||||
1080 | } | ||||||||||
1081 | } | ||||||||||
1082 | break; | ||||||||||
1083 | } | ||||||||||
1084 | case ISD::EXTRACT_SUBVECTOR: { | ||||||||||
1085 | // Offset the demanded elts by the subvector index. | ||||||||||
1086 | SDValue Src = Op.getOperand(0); | ||||||||||
1087 | if (Src.getValueType().isScalableVector()) | ||||||||||
1088 | break; | ||||||||||
1089 | uint64_t Idx = Op.getConstantOperandVal(1); | ||||||||||
1090 | unsigned NumSrcElts = Src.getValueType().getVectorNumElements(); | ||||||||||
1091 | APInt DemandedSrcElts = DemandedElts.zextOrSelf(NumSrcElts).shl(Idx); | ||||||||||
1092 | |||||||||||
1093 | if (SimplifyDemandedBits(Src, DemandedBits, DemandedSrcElts, Known, TLO, | ||||||||||
1094 | Depth + 1)) | ||||||||||
1095 | return true; | ||||||||||
1096 | |||||||||||
1097 | // Attempt to avoid multi-use src if we don't need anything from it. | ||||||||||
1098 | if (!DemandedBits.isAllOnes() || !DemandedSrcElts.isAllOnes()) { | ||||||||||
1099 | SDValue DemandedSrc = SimplifyMultipleUseDemandedBits( | ||||||||||
1100 | Src, DemandedBits, DemandedSrcElts, TLO.DAG, Depth + 1); | ||||||||||
1101 | if (DemandedSrc) { | ||||||||||
1102 | SDValue NewOp = TLO.DAG.getNode(Op.getOpcode(), dl, VT, DemandedSrc, | ||||||||||
1103 | Op.getOperand(1)); | ||||||||||
1104 | return TLO.CombineTo(Op, NewOp); | ||||||||||
1105 | } | ||||||||||
1106 | } | ||||||||||
1107 | break; | ||||||||||
1108 | } | ||||||||||
1109 | case ISD::CONCAT_VECTORS: { | ||||||||||
1110 | Known.Zero.setAllBits(); | ||||||||||
1111 | Known.One.setAllBits(); | ||||||||||
1112 | EVT SubVT = Op.getOperand(0).getValueType(); | ||||||||||
1113 | unsigned NumSubVecs = Op.getNumOperands(); | ||||||||||
1114 | unsigned NumSubElts = SubVT.getVectorNumElements(); | ||||||||||
1115 | for (unsigned i = 0; i != NumSubVecs; ++i) { | ||||||||||
1116 | APInt DemandedSubElts = | ||||||||||
1117 | DemandedElts.extractBits(NumSubElts, i * NumSubElts); | ||||||||||
1118 | if (SimplifyDemandedBits(Op.getOperand(i), DemandedBits, DemandedSubElts, | ||||||||||
1119 | Known2, TLO, Depth + 1)) | ||||||||||
1120 | return true; | ||||||||||
1121 | // Known bits are shared by every demanded subvector element. | ||||||||||
1122 | if (!!DemandedSubElts) | ||||||||||
1123 | Known = KnownBits::commonBits(Known, Known2); | ||||||||||
1124 | } | ||||||||||
1125 | break; | ||||||||||
1126 | } | ||||||||||
1127 | case ISD::VECTOR_SHUFFLE: { | ||||||||||
1128 | ArrayRef<int> ShuffleMask = cast<ShuffleVectorSDNode>(Op)->getMask(); | ||||||||||
1129 | |||||||||||
1130 | // Collect demanded elements from shuffle operands.. | ||||||||||
1131 | APInt DemandedLHS(NumElts, 0); | ||||||||||
1132 | APInt DemandedRHS(NumElts, 0); | ||||||||||
1133 | for (unsigned i = 0; i != NumElts; ++i) { | ||||||||||
1134 | if (!DemandedElts[i]) | ||||||||||
1135 | continue; | ||||||||||
1136 | int M = ShuffleMask[i]; | ||||||||||
1137 | if (M < 0) { | ||||||||||
1138 | // For UNDEF elements, we don't know anything about the common state of | ||||||||||
1139 | // the shuffle result. | ||||||||||
1140 | DemandedLHS.clearAllBits(); | ||||||||||
1141 | DemandedRHS.clearAllBits(); | ||||||||||
1142 | break; | ||||||||||
1143 | } | ||||||||||
1144 | assert(0 <= M && M < (int)(2 * NumElts) && "Shuffle index out of range")(static_cast <bool> (0 <= M && M < (int)( 2 * NumElts) && "Shuffle index out of range") ? void ( 0) : __assert_fail ("0 <= M && M < (int)(2 * NumElts) && \"Shuffle index out of range\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 1144, __extension__ __PRETTY_FUNCTION__)); | ||||||||||
1145 | if (M < (int)NumElts) | ||||||||||
1146 | DemandedLHS.setBit(M); | ||||||||||
1147 | else | ||||||||||
1148 | DemandedRHS.setBit(M - NumElts); | ||||||||||
1149 | } | ||||||||||
1150 | |||||||||||
1151 | if (!!DemandedLHS || !!DemandedRHS) { | ||||||||||
1152 | SDValue Op0 = Op.getOperand(0); | ||||||||||
1153 | SDValue Op1 = Op.getOperand(1); | ||||||||||
1154 | |||||||||||
1155 | Known.Zero.setAllBits(); | ||||||||||
1156 | Known.One.setAllBits(); | ||||||||||
1157 | if (!!DemandedLHS) { | ||||||||||
1158 | if (SimplifyDemandedBits(Op0, DemandedBits, DemandedLHS, Known2, TLO, | ||||||||||
1159 | Depth + 1)) | ||||||||||
1160 | return true; | ||||||||||
1161 | Known = KnownBits::commonBits(Known, Known2); | ||||||||||
1162 | } | ||||||||||
1163 | if (!!DemandedRHS) { | ||||||||||
1164 | if (SimplifyDemandedBits(Op1, DemandedBits, DemandedRHS, Known2, TLO, | ||||||||||
1165 | Depth + 1)) | ||||||||||
1166 | return true; | ||||||||||
1167 | Known = KnownBits::commonBits(Known, Known2); | ||||||||||
1168 | } | ||||||||||
1169 | |||||||||||
1170 | // Attempt to avoid multi-use ops if we don't need anything from them. | ||||||||||
1171 | SDValue DemandedOp0 = SimplifyMultipleUseDemandedBits( | ||||||||||
1172 | Op0, DemandedBits, DemandedLHS, TLO.DAG, Depth + 1); | ||||||||||
1173 | SDValue DemandedOp1 = SimplifyMultipleUseDemandedBits( | ||||||||||
1174 | Op1, DemandedBits, DemandedRHS, TLO.DAG, Depth + 1); | ||||||||||
1175 | if (DemandedOp0 || DemandedOp1) { | ||||||||||
1176 | Op0 = DemandedOp0 ? DemandedOp0 : Op0; | ||||||||||
1177 | Op1 = DemandedOp1 ? DemandedOp1 : Op1; | ||||||||||
1178 | SDValue NewOp = TLO.DAG.getVectorShuffle(VT, dl, Op0, Op1, ShuffleMask); | ||||||||||
1179 | return TLO.CombineTo(Op, NewOp); | ||||||||||
1180 | } | ||||||||||
1181 | } | ||||||||||
1182 | break; | ||||||||||
1183 | } | ||||||||||
1184 | case ISD::AND: { | ||||||||||
1185 | SDValue Op0 = Op.getOperand(0); | ||||||||||
1186 | SDValue Op1 = Op.getOperand(1); | ||||||||||
1187 | |||||||||||
1188 | // If the RHS is a constant, check to see if the LHS would be zero without | ||||||||||
1189 | // using the bits from the RHS. Below, we use knowledge about the RHS to | ||||||||||
1190 | // simplify the LHS, here we're using information from the LHS to simplify | ||||||||||
1191 | // the RHS. | ||||||||||
1192 | if (ConstantSDNode *RHSC = isConstOrConstSplat(Op1)) { | ||||||||||
1193 | // Do not increment Depth here; that can cause an infinite loop. | ||||||||||
1194 | KnownBits LHSKnown = TLO.DAG.computeKnownBits(Op0, DemandedElts, Depth); | ||||||||||
1195 | // If the LHS already has zeros where RHSC does, this 'and' is dead. | ||||||||||
1196 | if ((LHSKnown.Zero & DemandedBits) == | ||||||||||
1197 | (~RHSC->getAPIntValue() & DemandedBits)) | ||||||||||
1198 | return TLO.CombineTo(Op, Op0); | ||||||||||
1199 | |||||||||||
1200 | // If any of the set bits in the RHS are known zero on the LHS, shrink | ||||||||||
1201 | // the constant. | ||||||||||
1202 | if (ShrinkDemandedConstant(Op, ~LHSKnown.Zero & DemandedBits, | ||||||||||
1203 | DemandedElts, TLO)) | ||||||||||
1204 | return true; | ||||||||||
1205 | |||||||||||
1206 | // Bitwise-not (xor X, -1) is a special case: we don't usually shrink its | ||||||||||
1207 | // constant, but if this 'and' is only clearing bits that were just set by | ||||||||||
1208 | // the xor, then this 'and' can be eliminated by shrinking the mask of | ||||||||||
1209 | // the xor. For example, for a 32-bit X: | ||||||||||
1210 | // and (xor (srl X, 31), -1), 1 --> xor (srl X, 31), 1 | ||||||||||
1211 | if (isBitwiseNot(Op0) && Op0.hasOneUse() && | ||||||||||
1212 | LHSKnown.One == ~RHSC->getAPIntValue()) { | ||||||||||
1213 | SDValue Xor = TLO.DAG.getNode(ISD::XOR, dl, VT, Op0.getOperand(0), Op1); | ||||||||||
1214 | return TLO.CombineTo(Op, Xor); | ||||||||||
1215 | } | ||||||||||
1216 | } | ||||||||||
1217 | |||||||||||
1218 | if (SimplifyDemandedBits(Op1, DemandedBits, DemandedElts, Known, TLO, | ||||||||||
1219 | Depth + 1)) | ||||||||||
1220 | return true; | ||||||||||
1221 | assert(!Known.hasConflict() && "Bits known to be one AND zero?")(static_cast <bool> (!Known.hasConflict() && "Bits known to be one AND zero?" ) ? void (0) : __assert_fail ("!Known.hasConflict() && \"Bits known to be one AND zero?\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 1221, __extension__ __PRETTY_FUNCTION__)); | ||||||||||
1222 | if (SimplifyDemandedBits(Op0, ~Known.Zero & DemandedBits, DemandedElts, | ||||||||||
1223 | Known2, TLO, Depth + 1)) | ||||||||||
1224 | return true; | ||||||||||
1225 | assert(!Known2.hasConflict() && "Bits known to be one AND zero?")(static_cast <bool> (!Known2.hasConflict() && "Bits known to be one AND zero?" ) ? void (0) : __assert_fail ("!Known2.hasConflict() && \"Bits known to be one AND zero?\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 1225, __extension__ __PRETTY_FUNCTION__)); | ||||||||||
1226 | |||||||||||
1227 | // Attempt to avoid multi-use ops if we don't need anything from them. | ||||||||||
1228 | if (!DemandedBits.isAllOnes() || !DemandedElts.isAllOnes()) { | ||||||||||
1229 | SDValue DemandedOp0 = SimplifyMultipleUseDemandedBits( | ||||||||||
1230 | Op0, DemandedBits, DemandedElts, TLO.DAG, Depth + 1); | ||||||||||
1231 | SDValue DemandedOp1 = SimplifyMultipleUseDemandedBits( | ||||||||||
1232 | Op1, DemandedBits, DemandedElts, TLO.DAG, Depth + 1); | ||||||||||
1233 | if (DemandedOp0 || DemandedOp1) { | ||||||||||
1234 | Op0 = DemandedOp0 ? DemandedOp0 : Op0; | ||||||||||
1235 | Op1 = DemandedOp1 ? DemandedOp1 : Op1; | ||||||||||
1236 | SDValue NewOp = TLO.DAG.getNode(Op.getOpcode(), dl, VT, Op0, Op1); | ||||||||||
1237 | return TLO.CombineTo(Op, NewOp); | ||||||||||
1238 | } | ||||||||||
1239 | } | ||||||||||
1240 | |||||||||||
1241 | // If all of the demanded bits are known one on one side, return the other. | ||||||||||
1242 | // These bits cannot contribute to the result of the 'and'. | ||||||||||
1243 | if (DemandedBits.isSubsetOf(Known2.Zero | Known.One)) | ||||||||||
1244 | return TLO.CombineTo(Op, Op0); | ||||||||||
1245 | if (DemandedBits.isSubsetOf(Known.Zero | Known2.One)) | ||||||||||
1246 | return TLO.CombineTo(Op, Op1); | ||||||||||
1247 | // If all of the demanded bits in the inputs are known zeros, return zero. | ||||||||||
1248 | if (DemandedBits.isSubsetOf(Known.Zero | Known2.Zero)) | ||||||||||
1249 | return TLO.CombineTo(Op, TLO.DAG.getConstant(0, dl, VT)); | ||||||||||
1250 | // If the RHS is a constant, see if we can simplify it. | ||||||||||
1251 | if (ShrinkDemandedConstant(Op, ~Known2.Zero & DemandedBits, DemandedElts, | ||||||||||
1252 | TLO)) | ||||||||||
1253 | return true; | ||||||||||
1254 | // If the operation can be done in a smaller type, do so. | ||||||||||
1255 | if (ShrinkDemandedOp(Op, BitWidth, DemandedBits, TLO)) | ||||||||||
1256 | return true; | ||||||||||
1257 | |||||||||||
1258 | Known &= Known2; | ||||||||||
1259 | break; | ||||||||||
1260 | } | ||||||||||
1261 | case ISD::OR: { | ||||||||||
1262 | SDValue Op0 = Op.getOperand(0); | ||||||||||
1263 | SDValue Op1 = Op.getOperand(1); | ||||||||||
1264 | |||||||||||
1265 | if (SimplifyDemandedBits(Op1, DemandedBits, DemandedElts, Known, TLO, | ||||||||||
1266 | Depth + 1)) | ||||||||||
1267 | return true; | ||||||||||
1268 | assert(!Known.hasConflict() && "Bits known to be one AND zero?")(static_cast <bool> (!Known.hasConflict() && "Bits known to be one AND zero?" ) ? void (0) : __assert_fail ("!Known.hasConflict() && \"Bits known to be one AND zero?\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 1268, __extension__ __PRETTY_FUNCTION__)); | ||||||||||
1269 | if (SimplifyDemandedBits(Op0, ~Known.One & DemandedBits, DemandedElts, | ||||||||||
1270 | Known2, TLO, Depth + 1)) | ||||||||||
1271 | return true; | ||||||||||
1272 | assert(!Known2.hasConflict() && "Bits known to be one AND zero?")(static_cast <bool> (!Known2.hasConflict() && "Bits known to be one AND zero?" ) ? void (0) : __assert_fail ("!Known2.hasConflict() && \"Bits known to be one AND zero?\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 1272, __extension__ __PRETTY_FUNCTION__)); | ||||||||||
1273 | |||||||||||
1274 | // Attempt to avoid multi-use ops if we don't need anything from them. | ||||||||||
1275 | if (!DemandedBits.isAllOnes() || !DemandedElts.isAllOnes()) { | ||||||||||
1276 | SDValue DemandedOp0 = SimplifyMultipleUseDemandedBits( | ||||||||||
1277 | Op0, DemandedBits, DemandedElts, TLO.DAG, Depth + 1); | ||||||||||
1278 | SDValue DemandedOp1 = SimplifyMultipleUseDemandedBits( | ||||||||||
1279 | Op1, DemandedBits, DemandedElts, TLO.DAG, Depth + 1); | ||||||||||
1280 | if (DemandedOp0 || DemandedOp1) { | ||||||||||
1281 | Op0 = DemandedOp0 ? DemandedOp0 : Op0; | ||||||||||
1282 | Op1 = DemandedOp1 ? DemandedOp1 : Op1; | ||||||||||
1283 | SDValue NewOp = TLO.DAG.getNode(Op.getOpcode(), dl, VT, Op0, Op1); | ||||||||||
1284 | return TLO.CombineTo(Op, NewOp); | ||||||||||
1285 | } | ||||||||||
1286 | } | ||||||||||
1287 | |||||||||||
1288 | // If all of the demanded bits are known zero on one side, return the other. | ||||||||||
1289 | // These bits cannot contribute to the result of the 'or'. | ||||||||||
1290 | if (DemandedBits.isSubsetOf(Known2.One | Known.Zero)) | ||||||||||
1291 | return TLO.CombineTo(Op, Op0); | ||||||||||
1292 | if (DemandedBits.isSubsetOf(Known.One | Known2.Zero)) | ||||||||||
1293 | return TLO.CombineTo(Op, Op1); | ||||||||||
1294 | // If the RHS is a constant, see if we can simplify it. | ||||||||||
1295 | if (ShrinkDemandedConstant(Op, DemandedBits, DemandedElts, TLO)) | ||||||||||
1296 | return true; | ||||||||||
1297 | // If the operation can be done in a smaller type, do so. | ||||||||||
1298 | if (ShrinkDemandedOp(Op, BitWidth, DemandedBits, TLO)) | ||||||||||
1299 | return true; | ||||||||||
1300 | |||||||||||
1301 | Known |= Known2; | ||||||||||
1302 | break; | ||||||||||
1303 | } | ||||||||||
1304 | case ISD::XOR: { | ||||||||||
1305 | SDValue Op0 = Op.getOperand(0); | ||||||||||
1306 | SDValue Op1 = Op.getOperand(1); | ||||||||||
1307 | |||||||||||
1308 | if (SimplifyDemandedBits(Op1, DemandedBits, DemandedElts, Known, TLO, | ||||||||||
1309 | Depth + 1)) | ||||||||||
1310 | return true; | ||||||||||
1311 | assert(!Known.hasConflict() && "Bits known to be one AND zero?")(static_cast <bool> (!Known.hasConflict() && "Bits known to be one AND zero?" ) ? void (0) : __assert_fail ("!Known.hasConflict() && \"Bits known to be one AND zero?\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 1311, __extension__ __PRETTY_FUNCTION__)); | ||||||||||
1312 | if (SimplifyDemandedBits(Op0, DemandedBits, DemandedElts, Known2, TLO, | ||||||||||
1313 | Depth + 1)) | ||||||||||
1314 | return true; | ||||||||||
1315 | assert(!Known2.hasConflict() && "Bits known to be one AND zero?")(static_cast <bool> (!Known2.hasConflict() && "Bits known to be one AND zero?" ) ? void (0) : __assert_fail ("!Known2.hasConflict() && \"Bits known to be one AND zero?\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 1315, __extension__ __PRETTY_FUNCTION__)); | ||||||||||
1316 | |||||||||||
1317 | // Attempt to avoid multi-use ops if we don't need anything from them. | ||||||||||
1318 | if (!DemandedBits.isAllOnes() || !DemandedElts.isAllOnes()) { | ||||||||||
1319 | SDValue DemandedOp0 = SimplifyMultipleUseDemandedBits( | ||||||||||
1320 | Op0, DemandedBits, DemandedElts, TLO.DAG, Depth + 1); | ||||||||||
1321 | SDValue DemandedOp1 = SimplifyMultipleUseDemandedBits( | ||||||||||
1322 | Op1, DemandedBits, DemandedElts, TLO.DAG, Depth + 1); | ||||||||||
1323 | if (DemandedOp0 || DemandedOp1) { | ||||||||||
1324 | Op0 = DemandedOp0 ? DemandedOp0 : Op0; | ||||||||||
1325 | Op1 = DemandedOp1 ? DemandedOp1 : Op1; | ||||||||||
1326 | SDValue NewOp = TLO.DAG.getNode(Op.getOpcode(), dl, VT, Op0, Op1); | ||||||||||
1327 | return TLO.CombineTo(Op, NewOp); | ||||||||||
1328 | } | ||||||||||
1329 | } | ||||||||||
1330 | |||||||||||
1331 | // If all of the demanded bits are known zero on one side, return the other. | ||||||||||
1332 | // These bits cannot contribute to the result of the 'xor'. | ||||||||||
1333 | if (DemandedBits.isSubsetOf(Known.Zero)) | ||||||||||
1334 | return TLO.CombineTo(Op, Op0); | ||||||||||
1335 | if (DemandedBits.isSubsetOf(Known2.Zero)) | ||||||||||
1336 | return TLO.CombineTo(Op, Op1); | ||||||||||
1337 | // If the operation can be done in a smaller type, do so. | ||||||||||
1338 | if (ShrinkDemandedOp(Op, BitWidth, DemandedBits, TLO)) | ||||||||||
1339 | return true; | ||||||||||
1340 | |||||||||||
1341 | // If all of the unknown bits are known to be zero on one side or the other | ||||||||||
1342 | // turn this into an *inclusive* or. | ||||||||||
1343 | // e.g. (A & C1)^(B & C2) -> (A & C1)|(B & C2) iff C1&C2 == 0 | ||||||||||
1344 | if (DemandedBits.isSubsetOf(Known.Zero | Known2.Zero)) | ||||||||||
1345 | return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::OR, dl, VT, Op0, Op1)); | ||||||||||
1346 | |||||||||||
1347 | ConstantSDNode* C = isConstOrConstSplat(Op1, DemandedElts); | ||||||||||
1348 | if (C) { | ||||||||||
1349 | // If one side is a constant, and all of the set bits in the constant are | ||||||||||
1350 | // also known set on the other side, turn this into an AND, as we know | ||||||||||
1351 | // the bits will be cleared. | ||||||||||
1352 | // e.g. (X | C1) ^ C2 --> (X | C1) & ~C2 iff (C1&C2) == C2 | ||||||||||
1353 | // NB: it is okay if more bits are known than are requested | ||||||||||
1354 | if (C->getAPIntValue() == Known2.One) { | ||||||||||
1355 | SDValue ANDC = | ||||||||||
1356 | TLO.DAG.getConstant(~C->getAPIntValue() & DemandedBits, dl, VT); | ||||||||||
1357 | return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::AND, dl, VT, Op0, ANDC)); | ||||||||||
1358 | } | ||||||||||
1359 | |||||||||||
1360 | // If the RHS is a constant, see if we can change it. Don't alter a -1 | ||||||||||
1361 | // constant because that's a 'not' op, and that is better for combining | ||||||||||
1362 | // and codegen. | ||||||||||
1363 | if (!C->isAllOnes() && DemandedBits.isSubsetOf(C->getAPIntValue())) { | ||||||||||
1364 | // We're flipping all demanded bits. Flip the undemanded bits too. | ||||||||||
1365 | SDValue New = TLO.DAG.getNOT(dl, Op0, VT); | ||||||||||
1366 | return TLO.CombineTo(Op, New); | ||||||||||
1367 | } | ||||||||||
1368 | } | ||||||||||
1369 | |||||||||||
1370 | // If we can't turn this into a 'not', try to shrink the constant. | ||||||||||
1371 | if (!C || !C->isAllOnes()) | ||||||||||
1372 | if (ShrinkDemandedConstant(Op, DemandedBits, DemandedElts, TLO)) | ||||||||||
1373 | return true; | ||||||||||
1374 | |||||||||||
1375 | Known ^= Known2; | ||||||||||
1376 | break; | ||||||||||
1377 | } | ||||||||||
1378 | case ISD::SELECT: | ||||||||||
1379 | if (SimplifyDemandedBits(Op.getOperand(2), DemandedBits, Known, TLO, | ||||||||||
1380 | Depth + 1)) | ||||||||||
1381 | return true; | ||||||||||
1382 | if (SimplifyDemandedBits(Op.getOperand(1), DemandedBits, Known2, TLO, | ||||||||||
1383 | Depth + 1)) | ||||||||||
1384 | return true; | ||||||||||
1385 | assert(!Known.hasConflict() && "Bits known to be one AND zero?")(static_cast <bool> (!Known.hasConflict() && "Bits known to be one AND zero?" ) ? void (0) : __assert_fail ("!Known.hasConflict() && \"Bits known to be one AND zero?\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 1385, __extension__ __PRETTY_FUNCTION__)); | ||||||||||
1386 | assert(!Known2.hasConflict() && "Bits known to be one AND zero?")(static_cast <bool> (!Known2.hasConflict() && "Bits known to be one AND zero?" ) ? void (0) : __assert_fail ("!Known2.hasConflict() && \"Bits known to be one AND zero?\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 1386, __extension__ __PRETTY_FUNCTION__)); | ||||||||||
1387 | |||||||||||
1388 | // If the operands are constants, see if we can simplify them. | ||||||||||
1389 | if (ShrinkDemandedConstant(Op, DemandedBits, DemandedElts, TLO)) | ||||||||||
1390 | return true; | ||||||||||
1391 | |||||||||||
1392 | // Only known if known in both the LHS and RHS. | ||||||||||
1393 | Known = KnownBits::commonBits(Known, Known2); | ||||||||||
1394 | break; | ||||||||||
1395 | case ISD::SELECT_CC: | ||||||||||
1396 | if (SimplifyDemandedBits(Op.getOperand(3), DemandedBits, Known, TLO, | ||||||||||
1397 | Depth + 1)) | ||||||||||
1398 | return true; | ||||||||||
1399 | if (SimplifyDemandedBits(Op.getOperand(2), DemandedBits, Known2, TLO, | ||||||||||
1400 | Depth + 1)) | ||||||||||
1401 | return true; | ||||||||||
1402 | assert(!Known.hasConflict() && "Bits known to be one AND zero?")(static_cast <bool> (!Known.hasConflict() && "Bits known to be one AND zero?" ) ? void (0) : __assert_fail ("!Known.hasConflict() && \"Bits known to be one AND zero?\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 1402, __extension__ __PRETTY_FUNCTION__)); | ||||||||||
1403 | assert(!Known2.hasConflict() && "Bits known to be one AND zero?")(static_cast <bool> (!Known2.hasConflict() && "Bits known to be one AND zero?" ) ? void (0) : __assert_fail ("!Known2.hasConflict() && \"Bits known to be one AND zero?\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 1403, __extension__ __PRETTY_FUNCTION__)); | ||||||||||
1404 | |||||||||||
1405 | // If the operands are constants, see if we can simplify them. | ||||||||||
1406 | if (ShrinkDemandedConstant(Op, DemandedBits, DemandedElts, TLO)) | ||||||||||
1407 | return true; | ||||||||||
1408 | |||||||||||
1409 | // Only known if known in both the LHS and RHS. | ||||||||||
1410 | Known = KnownBits::commonBits(Known, Known2); | ||||||||||
1411 | break; | ||||||||||
1412 | case ISD::SETCC: { | ||||||||||
1413 | SDValue Op0 = Op.getOperand(0); | ||||||||||
1414 | SDValue Op1 = Op.getOperand(1); | ||||||||||
1415 | ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); | ||||||||||
1416 | // If (1) we only need the sign-bit, (2) the setcc operands are the same | ||||||||||
1417 | // width as the setcc result, and (3) the result of a setcc conforms to 0 or | ||||||||||
1418 | // -1, we may be able to bypass the setcc. | ||||||||||
1419 | if (DemandedBits.isSignMask() && | ||||||||||
1420 | Op0.getScalarValueSizeInBits() == BitWidth && | ||||||||||
1421 | getBooleanContents(Op0.getValueType()) == | ||||||||||
1422 | BooleanContent::ZeroOrNegativeOneBooleanContent) { | ||||||||||
1423 | // If we're testing X < 0, then this compare isn't needed - just use X! | ||||||||||
1424 | // FIXME: We're limiting to integer types here, but this should also work | ||||||||||
1425 | // if we don't care about FP signed-zero. The use of SETLT with FP means | ||||||||||
1426 | // that we don't care about NaNs. | ||||||||||
1427 | if (CC == ISD::SETLT && Op1.getValueType().isInteger() && | ||||||||||
1428 | (isNullConstant(Op1) || ISD::isBuildVectorAllZeros(Op1.getNode()))) | ||||||||||
1429 | return TLO.CombineTo(Op, Op0); | ||||||||||
1430 | |||||||||||
1431 | // TODO: Should we check for other forms of sign-bit comparisons? | ||||||||||
1432 | // Examples: X <= -1, X >= 0 | ||||||||||
1433 | } | ||||||||||
1434 | if (getBooleanContents(Op0.getValueType()) == | ||||||||||
1435 | TargetLowering::ZeroOrOneBooleanContent && | ||||||||||
1436 | BitWidth > 1) | ||||||||||
1437 | Known.Zero.setBitsFrom(1); | ||||||||||
1438 | break; | ||||||||||
1439 | } | ||||||||||
1440 | case ISD::SHL: { | ||||||||||
1441 | SDValue Op0 = Op.getOperand(0); | ||||||||||
1442 | SDValue Op1 = Op.getOperand(1); | ||||||||||
1443 | EVT ShiftVT = Op1.getValueType(); | ||||||||||
1444 | |||||||||||
1445 | if (const APInt *SA = | ||||||||||
1446 | TLO.DAG.getValidShiftAmountConstant(Op, DemandedElts)) { | ||||||||||
1447 | unsigned ShAmt = SA->getZExtValue(); | ||||||||||
1448 | if (ShAmt == 0) | ||||||||||
1449 | return TLO.CombineTo(Op, Op0); | ||||||||||
1450 | |||||||||||
1451 | // If this is ((X >>u C1) << ShAmt), see if we can simplify this into a | ||||||||||
1452 | // single shift. We can do this if the bottom bits (which are shifted | ||||||||||
1453 | // out) are never demanded. | ||||||||||
1454 | // TODO - support non-uniform vector amounts. | ||||||||||
1455 | if (Op0.getOpcode() == ISD::SRL) { | ||||||||||
1456 | if (!DemandedBits.intersects(APInt::getLowBitsSet(BitWidth, ShAmt))) { | ||||||||||
1457 | if (const APInt *SA2 = | ||||||||||
1458 | TLO.DAG.getValidShiftAmountConstant(Op0, DemandedElts)) { | ||||||||||
1459 | unsigned C1 = SA2->getZExtValue(); | ||||||||||
1460 | unsigned Opc = ISD::SHL; | ||||||||||
1461 | int Diff = ShAmt - C1; | ||||||||||
1462 | if (Diff < 0) { | ||||||||||
1463 | Diff = -Diff; | ||||||||||
1464 | Opc = ISD::SRL; | ||||||||||
1465 | } | ||||||||||
1466 | SDValue NewSA = TLO.DAG.getConstant(Diff, dl, ShiftVT); | ||||||||||
1467 | return TLO.CombineTo( | ||||||||||
1468 | Op, TLO.DAG.getNode(Opc, dl, VT, Op0.getOperand(0), NewSA)); | ||||||||||
1469 | } | ||||||||||
1470 | } | ||||||||||
1471 | } | ||||||||||
1472 | |||||||||||
1473 | // Convert (shl (anyext x, c)) to (anyext (shl x, c)) if the high bits | ||||||||||
1474 | // are not demanded. This will likely allow the anyext to be folded away. | ||||||||||
1475 | // TODO - support non-uniform vector amounts. | ||||||||||
1476 | if (Op0.getOpcode() == ISD::ANY_EXTEND) { | ||||||||||
1477 | SDValue InnerOp = Op0.getOperand(0); | ||||||||||
1478 | EVT InnerVT = InnerOp.getValueType(); | ||||||||||
1479 | unsigned InnerBits = InnerVT.getScalarSizeInBits(); | ||||||||||
1480 | if (ShAmt < InnerBits && DemandedBits.getActiveBits() <= InnerBits && | ||||||||||
1481 | isTypeDesirableForOp(ISD::SHL, InnerVT)) { | ||||||||||
1482 | EVT ShTy = getShiftAmountTy(InnerVT, DL); | ||||||||||
1483 | if (!APInt(BitWidth, ShAmt).isIntN(ShTy.getSizeInBits())) | ||||||||||
1484 | ShTy = InnerVT; | ||||||||||
1485 | SDValue NarrowShl = | ||||||||||
1486 | TLO.DAG.getNode(ISD::SHL, dl, InnerVT, InnerOp, | ||||||||||
1487 | TLO.DAG.getConstant(ShAmt, dl, ShTy)); | ||||||||||
1488 | return TLO.CombineTo( | ||||||||||
1489 | Op, TLO.DAG.getNode(ISD::ANY_EXTEND, dl, VT, NarrowShl)); | ||||||||||
1490 | } | ||||||||||
1491 | |||||||||||
1492 | // Repeat the SHL optimization above in cases where an extension | ||||||||||
1493 | // intervenes: (shl (anyext (shr x, c1)), c2) to | ||||||||||
1494 | // (shl (anyext x), c2-c1). This requires that the bottom c1 bits | ||||||||||
1495 | // aren't demanded (as above) and that the shifted upper c1 bits of | ||||||||||
1496 | // x aren't demanded. | ||||||||||
1497 | // TODO - support non-uniform vector amounts. | ||||||||||
1498 | if (Op0.hasOneUse() && InnerOp.getOpcode() == ISD::SRL && | ||||||||||
1499 | InnerOp.hasOneUse()) { | ||||||||||
1500 | if (const APInt *SA2 = | ||||||||||
1501 | TLO.DAG.getValidShiftAmountConstant(InnerOp, DemandedElts)) { | ||||||||||
1502 | unsigned InnerShAmt = SA2->getZExtValue(); | ||||||||||
1503 | if (InnerShAmt < ShAmt && InnerShAmt < InnerBits && | ||||||||||
1504 | DemandedBits.getActiveBits() <= | ||||||||||
1505 | (InnerBits - InnerShAmt + ShAmt) && | ||||||||||
1506 | DemandedBits.countTrailingZeros() >= ShAmt) { | ||||||||||
1507 | SDValue NewSA = | ||||||||||
1508 | TLO.DAG.getConstant(ShAmt - InnerShAmt, dl, ShiftVT); | ||||||||||
1509 | SDValue NewExt = TLO.DAG.getNode(ISD::ANY_EXTEND, dl, VT, | ||||||||||
1510 | InnerOp.getOperand(0)); | ||||||||||
1511 | return TLO.CombineTo( | ||||||||||
1512 | Op, TLO.DAG.getNode(ISD::SHL, dl, VT, NewExt, NewSA)); | ||||||||||
1513 | } | ||||||||||
1514 | } | ||||||||||
1515 | } | ||||||||||
1516 | } | ||||||||||
1517 | |||||||||||
1518 | APInt InDemandedMask = DemandedBits.lshr(ShAmt); | ||||||||||
1519 | if (SimplifyDemandedBits(Op0, InDemandedMask, DemandedElts, Known, TLO, | ||||||||||
1520 | Depth + 1)) | ||||||||||
1521 | return true; | ||||||||||
1522 | assert(!Known.hasConflict() && "Bits known to be one AND zero?")(static_cast <bool> (!Known.hasConflict() && "Bits known to be one AND zero?" ) ? void (0) : __assert_fail ("!Known.hasConflict() && \"Bits known to be one AND zero?\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 1522, __extension__ __PRETTY_FUNCTION__)); | ||||||||||
1523 | Known.Zero <<= ShAmt; | ||||||||||
1524 | Known.One <<= ShAmt; | ||||||||||
1525 | // low bits known zero. | ||||||||||
1526 | Known.Zero.setLowBits(ShAmt); | ||||||||||
1527 | |||||||||||
1528 | // Try shrinking the operation as long as the shift amount will still be | ||||||||||
1529 | // in range. | ||||||||||
1530 | if ((ShAmt < DemandedBits.getActiveBits()) && | ||||||||||
1531 | ShrinkDemandedOp(Op, BitWidth, DemandedBits, TLO)) | ||||||||||
1532 | return true; | ||||||||||
1533 | } | ||||||||||
1534 | |||||||||||
1535 | // If we are only demanding sign bits then we can use the shift source | ||||||||||
1536 | // directly. | ||||||||||
1537 | if (const APInt *MaxSA = | ||||||||||
1538 | TLO.DAG.getValidMaximumShiftAmountConstant(Op, DemandedElts)) { | ||||||||||
1539 | unsigned ShAmt = MaxSA->getZExtValue(); | ||||||||||
1540 | unsigned NumSignBits = | ||||||||||
1541 | TLO.DAG.ComputeNumSignBits(Op0, DemandedElts, Depth + 1); | ||||||||||
1542 | unsigned UpperDemandedBits = BitWidth - DemandedBits.countTrailingZeros(); | ||||||||||
1543 | if (NumSignBits > ShAmt && (NumSignBits - ShAmt) >= (UpperDemandedBits)) | ||||||||||
1544 | return TLO.CombineTo(Op, Op0); | ||||||||||
1545 | } | ||||||||||
1546 | break; | ||||||||||
1547 | } | ||||||||||
1548 | case ISD::SRL: { | ||||||||||
1549 | SDValue Op0 = Op.getOperand(0); | ||||||||||
1550 | SDValue Op1 = Op.getOperand(1); | ||||||||||
1551 | EVT ShiftVT = Op1.getValueType(); | ||||||||||
1552 | |||||||||||
1553 | if (const APInt *SA = | ||||||||||
1554 | TLO.DAG.getValidShiftAmountConstant(Op, DemandedElts)) { | ||||||||||
1555 | unsigned ShAmt = SA->getZExtValue(); | ||||||||||
1556 | if (ShAmt == 0) | ||||||||||
1557 | return TLO.CombineTo(Op, Op0); | ||||||||||
1558 | |||||||||||
1559 | // If this is ((X << C1) >>u ShAmt), see if we can simplify this into a | ||||||||||
1560 | // single shift. We can do this if the top bits (which are shifted out) | ||||||||||
1561 | // are never demanded. | ||||||||||
1562 | // TODO - support non-uniform vector amounts. | ||||||||||
1563 | if (Op0.getOpcode() == ISD::SHL) { | ||||||||||
1564 | if (!DemandedBits.intersects(APInt::getHighBitsSet(BitWidth, ShAmt))) { | ||||||||||
1565 | if (const APInt *SA2 = | ||||||||||
1566 | TLO.DAG.getValidShiftAmountConstant(Op0, DemandedElts)) { | ||||||||||
1567 | unsigned C1 = SA2->getZExtValue(); | ||||||||||
1568 | unsigned Opc = ISD::SRL; | ||||||||||
1569 | int Diff = ShAmt - C1; | ||||||||||
1570 | if (Diff < 0) { | ||||||||||
1571 | Diff = -Diff; | ||||||||||
1572 | Opc = ISD::SHL; | ||||||||||
1573 | } | ||||||||||
1574 | SDValue NewSA = TLO.DAG.getConstant(Diff, dl, ShiftVT); | ||||||||||
1575 | return TLO.CombineTo( | ||||||||||
1576 | Op, TLO.DAG.getNode(Opc, dl, VT, Op0.getOperand(0), NewSA)); | ||||||||||
1577 | } | ||||||||||
1578 | } | ||||||||||
1579 | } | ||||||||||
1580 | |||||||||||
1581 | APInt InDemandedMask = (DemandedBits << ShAmt); | ||||||||||
1582 | |||||||||||
1583 | // If the shift is exact, then it does demand the low bits (and knows that | ||||||||||
1584 | // they are zero). | ||||||||||
1585 | if (Op->getFlags().hasExact()) | ||||||||||
1586 | InDemandedMask.setLowBits(ShAmt); | ||||||||||
1587 | |||||||||||
1588 | // Compute the new bits that are at the top now. | ||||||||||
1589 | if (SimplifyDemandedBits(Op0, InDemandedMask, DemandedElts, Known, TLO, | ||||||||||
1590 | Depth + 1)) | ||||||||||
1591 | return true; | ||||||||||
1592 | assert(!Known.hasConflict() && "Bits known to be one AND zero?")(static_cast <bool> (!Known.hasConflict() && "Bits known to be one AND zero?" ) ? void (0) : __assert_fail ("!Known.hasConflict() && \"Bits known to be one AND zero?\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 1592, __extension__ __PRETTY_FUNCTION__)); | ||||||||||
1593 | Known.Zero.lshrInPlace(ShAmt); | ||||||||||
1594 | Known.One.lshrInPlace(ShAmt); | ||||||||||
1595 | // High bits known zero. | ||||||||||
1596 | Known.Zero.setHighBits(ShAmt); | ||||||||||
1597 | } | ||||||||||
1598 | break; | ||||||||||
1599 | } | ||||||||||
1600 | case ISD::SRA: { | ||||||||||
1601 | SDValue Op0 = Op.getOperand(0); | ||||||||||
1602 | SDValue Op1 = Op.getOperand(1); | ||||||||||
1603 | EVT ShiftVT = Op1.getValueType(); | ||||||||||
1604 | |||||||||||
1605 | // If we only want bits that already match the signbit then we don't need | ||||||||||
1606 | // to shift. | ||||||||||
1607 | unsigned NumHiDemandedBits = BitWidth - DemandedBits.countTrailingZeros(); | ||||||||||
1608 | if (TLO.DAG.ComputeNumSignBits(Op0, DemandedElts, Depth + 1) >= | ||||||||||
1609 | NumHiDemandedBits) | ||||||||||
1610 | return TLO.CombineTo(Op, Op0); | ||||||||||
1611 | |||||||||||
1612 | // If this is an arithmetic shift right and only the low-bit is set, we can | ||||||||||
1613 | // always convert this into a logical shr, even if the shift amount is | ||||||||||
1614 | // variable. The low bit of the shift cannot be an input sign bit unless | ||||||||||
1615 | // the shift amount is >= the size of the datatype, which is undefined. | ||||||||||
1616 | if (DemandedBits.isOne()) | ||||||||||
1617 | return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT, Op0, Op1)); | ||||||||||
1618 | |||||||||||
1619 | if (const APInt *SA = | ||||||||||
1620 | TLO.DAG.getValidShiftAmountConstant(Op, DemandedElts)) { | ||||||||||
1621 | unsigned ShAmt = SA->getZExtValue(); | ||||||||||
1622 | if (ShAmt == 0) | ||||||||||
1623 | return TLO.CombineTo(Op, Op0); | ||||||||||
1624 | |||||||||||
1625 | APInt InDemandedMask = (DemandedBits << ShAmt); | ||||||||||
1626 | |||||||||||
1627 | // If the shift is exact, then it does demand the low bits (and knows that | ||||||||||
1628 | // they are zero). | ||||||||||
1629 | if (Op->getFlags().hasExact()) | ||||||||||
1630 | InDemandedMask.setLowBits(ShAmt); | ||||||||||
1631 | |||||||||||
1632 | // If any of the demanded bits are produced by the sign extension, we also | ||||||||||
1633 | // demand the input sign bit. | ||||||||||
1634 | if (DemandedBits.countLeadingZeros() < ShAmt) | ||||||||||
1635 | InDemandedMask.setSignBit(); | ||||||||||
1636 | |||||||||||
1637 | if (SimplifyDemandedBits(Op0, InDemandedMask, DemandedElts, Known, TLO, | ||||||||||
1638 | Depth + 1)) | ||||||||||
1639 | return true; | ||||||||||
1640 | assert(!Known.hasConflict() && "Bits known to be one AND zero?")(static_cast <bool> (!Known.hasConflict() && "Bits known to be one AND zero?" ) ? void (0) : __assert_fail ("!Known.hasConflict() && \"Bits known to be one AND zero?\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 1640, __extension__ __PRETTY_FUNCTION__)); | ||||||||||
1641 | Known.Zero.lshrInPlace(ShAmt); | ||||||||||
1642 | Known.One.lshrInPlace(ShAmt); | ||||||||||
1643 | |||||||||||
1644 | // If the input sign bit is known to be zero, or if none of the top bits | ||||||||||
1645 | // are demanded, turn this into an unsigned shift right. | ||||||||||
1646 | if (Known.Zero[BitWidth - ShAmt - 1] || | ||||||||||
1647 | DemandedBits.countLeadingZeros() >= ShAmt) { | ||||||||||
1648 | SDNodeFlags Flags; | ||||||||||
1649 | Flags.setExact(Op->getFlags().hasExact()); | ||||||||||
1650 | return TLO.CombineTo( | ||||||||||
1651 | Op, TLO.DAG.getNode(ISD::SRL, dl, VT, Op0, Op1, Flags)); | ||||||||||
1652 | } | ||||||||||
1653 | |||||||||||
1654 | int Log2 = DemandedBits.exactLogBase2(); | ||||||||||
1655 | if (Log2 >= 0) { | ||||||||||
1656 | // The bit must come from the sign. | ||||||||||
1657 | SDValue NewSA = TLO.DAG.getConstant(BitWidth - 1 - Log2, dl, ShiftVT); | ||||||||||
1658 | return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT, Op0, NewSA)); | ||||||||||
1659 | } | ||||||||||
1660 | |||||||||||
1661 | if (Known.One[BitWidth - ShAmt - 1]) | ||||||||||
1662 | // New bits are known one. | ||||||||||
1663 | Known.One.setHighBits(ShAmt); | ||||||||||
1664 | |||||||||||
1665 | // Attempt to avoid multi-use ops if we don't need anything from them. | ||||||||||
1666 | if (!InDemandedMask.isAllOnes() || !DemandedElts.isAllOnes()) { | ||||||||||
1667 | SDValue DemandedOp0 = SimplifyMultipleUseDemandedBits( | ||||||||||
1668 | Op0, InDemandedMask, DemandedElts, TLO.DAG, Depth + 1); | ||||||||||
1669 | if (DemandedOp0) { | ||||||||||
1670 | SDValue NewOp = TLO.DAG.getNode(ISD::SRA, dl, VT, DemandedOp0, Op1); | ||||||||||
1671 | return TLO.CombineTo(Op, NewOp); | ||||||||||
1672 | } | ||||||||||
1673 | } | ||||||||||
1674 | } | ||||||||||
1675 | break; | ||||||||||
1676 | } | ||||||||||
1677 | case ISD::FSHL: | ||||||||||
1678 | case ISD::FSHR: { | ||||||||||
1679 | SDValue Op0 = Op.getOperand(0); | ||||||||||
1680 | SDValue Op1 = Op.getOperand(1); | ||||||||||
1681 | SDValue Op2 = Op.getOperand(2); | ||||||||||
1682 | bool IsFSHL = (Op.getOpcode() == ISD::FSHL); | ||||||||||
1683 | |||||||||||
1684 | if (ConstantSDNode *SA = isConstOrConstSplat(Op2, DemandedElts)) { | ||||||||||
1685 | unsigned Amt = SA->getAPIntValue().urem(BitWidth); | ||||||||||
1686 | |||||||||||
1687 | // For fshl, 0-shift returns the 1st arg. | ||||||||||
1688 | // For fshr, 0-shift returns the 2nd arg. | ||||||||||
1689 | if (Amt == 0) { | ||||||||||
1690 | if (SimplifyDemandedBits(IsFSHL ? Op0 : Op1, DemandedBits, DemandedElts, | ||||||||||
1691 | Known, TLO, Depth + 1)) | ||||||||||
1692 | return true; | ||||||||||
1693 | break; | ||||||||||
1694 | } | ||||||||||
1695 | |||||||||||
1696 | // fshl: (Op0 << Amt) | (Op1 >> (BW - Amt)) | ||||||||||
1697 | // fshr: (Op0 << (BW - Amt)) | (Op1 >> Amt) | ||||||||||
1698 | APInt Demanded0 = DemandedBits.lshr(IsFSHL ? Amt : (BitWidth - Amt)); | ||||||||||
1699 | APInt Demanded1 = DemandedBits << (IsFSHL ? (BitWidth - Amt) : Amt); | ||||||||||
1700 | if (SimplifyDemandedBits(Op0, Demanded0, DemandedElts, Known2, TLO, | ||||||||||
1701 | Depth + 1)) | ||||||||||
1702 | return true; | ||||||||||
1703 | if (SimplifyDemandedBits(Op1, Demanded1, DemandedElts, Known, TLO, | ||||||||||
1704 | Depth + 1)) | ||||||||||
1705 | return true; | ||||||||||
1706 | |||||||||||
1707 | Known2.One <<= (IsFSHL ? Amt : (BitWidth - Amt)); | ||||||||||
1708 | Known2.Zero <<= (IsFSHL ? Amt : (BitWidth - Amt)); | ||||||||||
1709 | Known.One.lshrInPlace(IsFSHL ? (BitWidth - Amt) : Amt); | ||||||||||
1710 | Known.Zero.lshrInPlace(IsFSHL ? (BitWidth - Amt) : Amt); | ||||||||||
1711 | Known.One |= Known2.One; | ||||||||||
1712 | Known.Zero |= Known2.Zero; | ||||||||||
1713 | } | ||||||||||
1714 | |||||||||||
1715 | // For pow-2 bitwidths we only demand the bottom modulo amt bits. | ||||||||||
1716 | if (isPowerOf2_32(BitWidth)) { | ||||||||||
1717 | APInt DemandedAmtBits(Op2.getScalarValueSizeInBits(), BitWidth - 1); | ||||||||||
1718 | if (SimplifyDemandedBits(Op2, DemandedAmtBits, DemandedElts, | ||||||||||
1719 | Known2, TLO, Depth + 1)) | ||||||||||
1720 | return true; | ||||||||||
1721 | } | ||||||||||
1722 | break; | ||||||||||
1723 | } | ||||||||||
1724 | case ISD::ROTL: | ||||||||||
1725 | case ISD::ROTR: { | ||||||||||
1726 | SDValue Op0 = Op.getOperand(0); | ||||||||||
1727 | SDValue Op1 = Op.getOperand(1); | ||||||||||
1728 | |||||||||||
1729 | // If we're rotating an 0/-1 value, then it stays an 0/-1 value. | ||||||||||
1730 | if (BitWidth == TLO.DAG.ComputeNumSignBits(Op0, DemandedElts, Depth + 1)) | ||||||||||
1731 | return TLO.CombineTo(Op, Op0); | ||||||||||
1732 | |||||||||||
1733 | // For pow-2 bitwidths we only demand the bottom modulo amt bits. | ||||||||||
1734 | if (isPowerOf2_32(BitWidth)) { | ||||||||||
1735 | APInt DemandedAmtBits(Op1.getScalarValueSizeInBits(), BitWidth - 1); | ||||||||||
1736 | if (SimplifyDemandedBits(Op1, DemandedAmtBits, DemandedElts, Known2, TLO, | ||||||||||
1737 | Depth + 1)) | ||||||||||
1738 | return true; | ||||||||||
1739 | } | ||||||||||
1740 | break; | ||||||||||
1741 | } | ||||||||||
1742 | case ISD::UMIN: { | ||||||||||
1743 | // Check if one arg is always less than (or equal) to the other arg. | ||||||||||
1744 | SDValue Op0 = Op.getOperand(0); | ||||||||||
1745 | SDValue Op1 = Op.getOperand(1); | ||||||||||
1746 | KnownBits Known0 = TLO.DAG.computeKnownBits(Op0, DemandedElts, Depth + 1); | ||||||||||
1747 | KnownBits Known1 = TLO.DAG.computeKnownBits(Op1, DemandedElts, Depth + 1); | ||||||||||
1748 | Known = KnownBits::umin(Known0, Known1); | ||||||||||
1749 | if (Optional<bool> IsULE = KnownBits::ule(Known0, Known1)) | ||||||||||
1750 | return TLO.CombineTo(Op, IsULE.getValue() ? Op0 : Op1); | ||||||||||
1751 | if (Optional<bool> IsULT = KnownBits::ult(Known0, Known1)) | ||||||||||
1752 | return TLO.CombineTo(Op, IsULT.getValue() ? Op0 : Op1); | ||||||||||
1753 | break; | ||||||||||
1754 | } | ||||||||||
1755 | case ISD::UMAX: { | ||||||||||
1756 | // Check if one arg is always greater than (or equal) to the other arg. | ||||||||||
1757 | SDValue Op0 = Op.getOperand(0); | ||||||||||
1758 | SDValue Op1 = Op.getOperand(1); | ||||||||||
1759 | KnownBits Known0 = TLO.DAG.computeKnownBits(Op0, DemandedElts, Depth + 1); | ||||||||||
1760 | KnownBits Known1 = TLO.DAG.computeKnownBits(Op1, DemandedElts, Depth + 1); | ||||||||||
1761 | Known = KnownBits::umax(Known0, Known1); | ||||||||||
1762 | if (Optional<bool> IsUGE = KnownBits::uge(Known0, Known1)) | ||||||||||
1763 | return TLO.CombineTo(Op, IsUGE.getValue() ? Op0 : Op1); | ||||||||||
1764 | if (Optional<bool> IsUGT = KnownBits::ugt(Known0, Known1)) | ||||||||||
1765 | return TLO.CombineTo(Op, IsUGT.getValue() ? Op0 : Op1); | ||||||||||
1766 | break; | ||||||||||
1767 | } | ||||||||||
1768 | case ISD::BITREVERSE: { | ||||||||||
1769 | SDValue Src = Op.getOperand(0); | ||||||||||
1770 | APInt DemandedSrcBits = DemandedBits.reverseBits(); | ||||||||||
1771 | if (SimplifyDemandedBits(Src, DemandedSrcBits, DemandedElts, Known2, TLO, | ||||||||||
1772 | Depth + 1)) | ||||||||||
1773 | return true; | ||||||||||
1774 | Known.One = Known2.One.reverseBits(); | ||||||||||
1775 | Known.Zero = Known2.Zero.reverseBits(); | ||||||||||
1776 | break; | ||||||||||
1777 | } | ||||||||||
1778 | case ISD::BSWAP: { | ||||||||||
1779 | SDValue Src = Op.getOperand(0); | ||||||||||
1780 | APInt DemandedSrcBits = DemandedBits.byteSwap(); | ||||||||||
1781 | if (SimplifyDemandedBits(Src, DemandedSrcBits, DemandedElts, Known2, TLO, | ||||||||||
1782 | Depth + 1)) | ||||||||||
1783 | return true; | ||||||||||
1784 | Known.One = Known2.One.byteSwap(); | ||||||||||
1785 | Known.Zero = Known2.Zero.byteSwap(); | ||||||||||
1786 | break; | ||||||||||
1787 | } | ||||||||||
1788 | case ISD::CTPOP: { | ||||||||||
1789 | // If only 1 bit is demanded, replace with PARITY as long as we're before | ||||||||||
1790 | // op legalization. | ||||||||||
1791 | // FIXME: Limit to scalars for now. | ||||||||||
1792 | if (DemandedBits.isOne() && !TLO.LegalOps && !VT.isVector()) | ||||||||||
1793 | return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::PARITY, dl, VT, | ||||||||||
1794 | Op.getOperand(0))); | ||||||||||
1795 | |||||||||||
1796 | Known = TLO.DAG.computeKnownBits(Op, DemandedElts, Depth); | ||||||||||
1797 | break; | ||||||||||
1798 | } | ||||||||||
1799 | case ISD::SIGN_EXTEND_INREG: { | ||||||||||
1800 | SDValue Op0 = Op.getOperand(0); | ||||||||||
1801 | EVT ExVT = cast<VTSDNode>(Op.getOperand(1))->getVT(); | ||||||||||
1802 | unsigned ExVTBits = ExVT.getScalarSizeInBits(); | ||||||||||
1803 | |||||||||||
1804 | // If we only care about the highest bit, don't bother shifting right. | ||||||||||
1805 | if (DemandedBits.isSignMask()) { | ||||||||||
1806 | unsigned MinSignedBits = | ||||||||||
1807 | TLO.DAG.ComputeMinSignedBits(Op0, DemandedElts, Depth + 1); | ||||||||||
1808 | bool AlreadySignExtended = ExVTBits >= MinSignedBits; | ||||||||||
1809 | // However if the input is already sign extended we expect the sign | ||||||||||
1810 | // extension to be dropped altogether later and do not simplify. | ||||||||||
1811 | if (!AlreadySignExtended) { | ||||||||||
1812 | // Compute the correct shift amount type, which must be getShiftAmountTy | ||||||||||
1813 | // for scalar types after legalization. | ||||||||||
1814 | EVT ShiftAmtTy = VT; | ||||||||||
1815 | if (TLO.LegalTypes() && !ShiftAmtTy.isVector()) | ||||||||||
1816 | ShiftAmtTy = getShiftAmountTy(ShiftAmtTy, DL); | ||||||||||
1817 | |||||||||||
1818 | SDValue ShiftAmt = | ||||||||||
1819 | TLO.DAG.getConstant(BitWidth - ExVTBits, dl, ShiftAmtTy); | ||||||||||
1820 | return TLO.CombineTo(Op, | ||||||||||
1821 | TLO.DAG.getNode(ISD::SHL, dl, VT, Op0, ShiftAmt)); | ||||||||||
1822 | } | ||||||||||
1823 | } | ||||||||||
1824 | |||||||||||
1825 | // If none of the extended bits are demanded, eliminate the sextinreg. | ||||||||||
1826 | if (DemandedBits.getActiveBits() <= ExVTBits) | ||||||||||
1827 | return TLO.CombineTo(Op, Op0); | ||||||||||
1828 | |||||||||||
1829 | APInt InputDemandedBits = DemandedBits.getLoBits(ExVTBits); | ||||||||||
1830 | |||||||||||
1831 | // Since the sign extended bits are demanded, we know that the sign | ||||||||||
1832 | // bit is demanded. | ||||||||||
1833 | InputDemandedBits.setBit(ExVTBits - 1); | ||||||||||
1834 | |||||||||||
1835 | if (SimplifyDemandedBits(Op0, InputDemandedBits, Known, TLO, Depth + 1)) | ||||||||||
1836 | return true; | ||||||||||
1837 | assert(!Known.hasConflict() && "Bits known to be one AND zero?")(static_cast <bool> (!Known.hasConflict() && "Bits known to be one AND zero?" ) ? void (0) : __assert_fail ("!Known.hasConflict() && \"Bits known to be one AND zero?\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 1837, __extension__ __PRETTY_FUNCTION__)); | ||||||||||
1838 | |||||||||||
1839 | // If the sign bit of the input is known set or clear, then we know the | ||||||||||
1840 | // top bits of the result. | ||||||||||
1841 | |||||||||||
1842 | // If the input sign bit is known zero, convert this into a zero extension. | ||||||||||
1843 | if (Known.Zero[ExVTBits - 1]) | ||||||||||
1844 | return TLO.CombineTo(Op, TLO.DAG.getZeroExtendInReg(Op0, dl, ExVT)); | ||||||||||
1845 | |||||||||||
1846 | APInt Mask = APInt::getLowBitsSet(BitWidth, ExVTBits); | ||||||||||
1847 | if (Known.One[ExVTBits - 1]) { // Input sign bit known set | ||||||||||
1848 | Known.One.setBitsFrom(ExVTBits); | ||||||||||
1849 | Known.Zero &= Mask; | ||||||||||
1850 | } else { // Input sign bit unknown | ||||||||||
1851 | Known.Zero &= Mask; | ||||||||||
1852 | Known.One &= Mask; | ||||||||||
1853 | } | ||||||||||
1854 | break; | ||||||||||
1855 | } | ||||||||||
1856 | case ISD::BUILD_PAIR: { | ||||||||||
1857 | EVT HalfVT = Op.getOperand(0).getValueType(); | ||||||||||
1858 | unsigned HalfBitWidth = HalfVT.getScalarSizeInBits(); | ||||||||||
1859 | |||||||||||
1860 | APInt MaskLo = DemandedBits.getLoBits(HalfBitWidth).trunc(HalfBitWidth); | ||||||||||
1861 | APInt MaskHi = DemandedBits.getHiBits(HalfBitWidth).trunc(HalfBitWidth); | ||||||||||
1862 | |||||||||||
1863 | KnownBits KnownLo, KnownHi; | ||||||||||
1864 | |||||||||||
1865 | if (SimplifyDemandedBits(Op.getOperand(0), MaskLo, KnownLo, TLO, Depth + 1)) | ||||||||||
1866 | return true; | ||||||||||
1867 | |||||||||||
1868 | if (SimplifyDemandedBits(Op.getOperand(1), MaskHi, KnownHi, TLO, Depth + 1)) | ||||||||||
1869 | return true; | ||||||||||
1870 | |||||||||||
1871 | Known.Zero = KnownLo.Zero.zext(BitWidth) | | ||||||||||
1872 | KnownHi.Zero.zext(BitWidth).shl(HalfBitWidth); | ||||||||||
1873 | |||||||||||
1874 | Known.One = KnownLo.One.zext(BitWidth) | | ||||||||||
1875 | KnownHi.One.zext(BitWidth).shl(HalfBitWidth); | ||||||||||
1876 | break; | ||||||||||
1877 | } | ||||||||||
1878 | case ISD::ZERO_EXTEND: | ||||||||||
1879 | case ISD::ZERO_EXTEND_VECTOR_INREG: { | ||||||||||
1880 | SDValue Src = Op.getOperand(0); | ||||||||||
1881 | EVT SrcVT = Src.getValueType(); | ||||||||||
1882 | unsigned InBits = SrcVT.getScalarSizeInBits(); | ||||||||||
1883 | unsigned InElts = SrcVT.isVector() ? SrcVT.getVectorNumElements() : 1; | ||||||||||
1884 | bool IsVecInReg = Op.getOpcode() == ISD::ZERO_EXTEND_VECTOR_INREG; | ||||||||||
1885 | |||||||||||
1886 | // If none of the top bits are demanded, convert this into an any_extend. | ||||||||||
1887 | if (DemandedBits.getActiveBits() <= InBits) { | ||||||||||
1888 | // If we only need the non-extended bits of the bottom element | ||||||||||
1889 | // then we can just bitcast to the result. | ||||||||||
1890 | if (IsVecInReg && DemandedElts == 1 && | ||||||||||
1891 | VT.getSizeInBits() == SrcVT.getSizeInBits() && | ||||||||||
1892 | TLO.DAG.getDataLayout().isLittleEndian()) | ||||||||||
1893 | return TLO.CombineTo(Op, TLO.DAG.getBitcast(VT, Src)); | ||||||||||
1894 | |||||||||||
1895 | unsigned Opc = | ||||||||||
1896 | IsVecInReg ? ISD::ANY_EXTEND_VECTOR_INREG : ISD::ANY_EXTEND; | ||||||||||
1897 | if (!TLO.LegalOperations() || isOperationLegal(Opc, VT)) | ||||||||||
1898 | return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT, Src)); | ||||||||||
1899 | } | ||||||||||
1900 | |||||||||||
1901 | APInt InDemandedBits = DemandedBits.trunc(InBits); | ||||||||||
1902 | APInt InDemandedElts = DemandedElts.zextOrSelf(InElts); | ||||||||||
1903 | if (SimplifyDemandedBits(Src, InDemandedBits, InDemandedElts, Known, TLO, | ||||||||||
1904 | Depth + 1)) | ||||||||||
1905 | return true; | ||||||||||
1906 | assert(!Known.hasConflict() && "Bits known to be one AND zero?")(static_cast <bool> (!Known.hasConflict() && "Bits known to be one AND zero?" ) ? void (0) : __assert_fail ("!Known.hasConflict() && \"Bits known to be one AND zero?\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 1906, __extension__ __PRETTY_FUNCTION__)); | ||||||||||
1907 | assert(Known.getBitWidth() == InBits && "Src width has changed?")(static_cast <bool> (Known.getBitWidth() == InBits && "Src width has changed?") ? void (0) : __assert_fail ("Known.getBitWidth() == InBits && \"Src width has changed?\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 1907, __extension__ __PRETTY_FUNCTION__)); | ||||||||||
1908 | Known = Known.zext(BitWidth); | ||||||||||
1909 | |||||||||||
1910 | // Attempt to avoid multi-use ops if we don't need anything from them. | ||||||||||
1911 | if (SDValue NewSrc = SimplifyMultipleUseDemandedBits( | ||||||||||
1912 | Src, InDemandedBits, InDemandedElts, TLO.DAG, Depth + 1)) | ||||||||||
1913 | return TLO.CombineTo(Op, TLO.DAG.getNode(Op.getOpcode(), dl, VT, NewSrc)); | ||||||||||
1914 | break; | ||||||||||
1915 | } | ||||||||||
1916 | case ISD::SIGN_EXTEND: | ||||||||||
1917 | case ISD::SIGN_EXTEND_VECTOR_INREG: { | ||||||||||
1918 | SDValue Src = Op.getOperand(0); | ||||||||||
1919 | EVT SrcVT = Src.getValueType(); | ||||||||||
1920 | unsigned InBits = SrcVT.getScalarSizeInBits(); | ||||||||||
1921 | unsigned InElts = SrcVT.isVector() ? SrcVT.getVectorNumElements() : 1; | ||||||||||
1922 | bool IsVecInReg = Op.getOpcode() == ISD::SIGN_EXTEND_VECTOR_INREG; | ||||||||||
1923 | |||||||||||
1924 | // If none of the top bits are demanded, convert this into an any_extend. | ||||||||||
1925 | if (DemandedBits.getActiveBits() <= InBits) { | ||||||||||
1926 | // If we only need the non-extended bits of the bottom element | ||||||||||
1927 | // then we can just bitcast to the result. | ||||||||||
1928 | if (IsVecInReg && DemandedElts == 1 && | ||||||||||
1929 | VT.getSizeInBits() == SrcVT.getSizeInBits() && | ||||||||||
1930 | TLO.DAG.getDataLayout().isLittleEndian()) | ||||||||||
1931 | return TLO.CombineTo(Op, TLO.DAG.getBitcast(VT, Src)); | ||||||||||
1932 | |||||||||||
1933 | unsigned Opc = | ||||||||||
1934 | IsVecInReg ? ISD::ANY_EXTEND_VECTOR_INREG : ISD::ANY_EXTEND; | ||||||||||
1935 | if (!TLO.LegalOperations() || isOperationLegal(Opc, VT)) | ||||||||||
1936 | return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT, Src)); | ||||||||||
1937 | } | ||||||||||
1938 | |||||||||||
1939 | APInt InDemandedBits = DemandedBits.trunc(InBits); | ||||||||||
1940 | APInt InDemandedElts = DemandedElts.zextOrSelf(InElts); | ||||||||||
1941 | |||||||||||
1942 | // Since some of the sign extended bits are demanded, we know that the sign | ||||||||||
1943 | // bit is demanded. | ||||||||||
1944 | InDemandedBits.setBit(InBits - 1); | ||||||||||
1945 | |||||||||||
1946 | if (SimplifyDemandedBits(Src, InDemandedBits, InDemandedElts, Known, TLO, | ||||||||||
1947 | Depth + 1)) | ||||||||||
1948 | return true; | ||||||||||
1949 | assert(!Known.hasConflict() && "Bits known to be one AND zero?")(static_cast <bool> (!Known.hasConflict() && "Bits known to be one AND zero?" ) ? void (0) : __assert_fail ("!Known.hasConflict() && \"Bits known to be one AND zero?\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 1949, __extension__ __PRETTY_FUNCTION__)); | ||||||||||
1950 | assert(Known.getBitWidth() == InBits && "Src width has changed?")(static_cast <bool> (Known.getBitWidth() == InBits && "Src width has changed?") ? void (0) : __assert_fail ("Known.getBitWidth() == InBits && \"Src width has changed?\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 1950, __extension__ __PRETTY_FUNCTION__)); | ||||||||||
1951 | |||||||||||
1952 | // If the sign bit is known one, the top bits match. | ||||||||||
1953 | Known = Known.sext(BitWidth); | ||||||||||
1954 | |||||||||||
1955 | // If the sign bit is known zero, convert this to a zero extend. | ||||||||||
1956 | if (Known.isNonNegative()) { | ||||||||||
1957 | unsigned Opc = | ||||||||||
1958 | IsVecInReg ? ISD::ZERO_EXTEND_VECTOR_INREG : ISD::ZERO_EXTEND; | ||||||||||
1959 | if (!TLO.LegalOperations() || isOperationLegal(Opc, VT)) | ||||||||||
1960 | return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT, Src)); | ||||||||||
1961 | } | ||||||||||
1962 | |||||||||||
1963 | // Attempt to avoid multi-use ops if we don't need anything from them. | ||||||||||
1964 | if (SDValue NewSrc = SimplifyMultipleUseDemandedBits( | ||||||||||
1965 | Src, InDemandedBits, InDemandedElts, TLO.DAG, Depth + 1)) | ||||||||||
1966 | return TLO.CombineTo(Op, TLO.DAG.getNode(Op.getOpcode(), dl, VT, NewSrc)); | ||||||||||
1967 | break; | ||||||||||
1968 | } | ||||||||||
1969 | case ISD::ANY_EXTEND: | ||||||||||
1970 | case ISD::ANY_EXTEND_VECTOR_INREG: { | ||||||||||
1971 | SDValue Src = Op.getOperand(0); | ||||||||||
1972 | EVT SrcVT = Src.getValueType(); | ||||||||||
1973 | unsigned InBits = SrcVT.getScalarSizeInBits(); | ||||||||||
1974 | unsigned InElts = SrcVT.isVector() ? SrcVT.getVectorNumElements() : 1; | ||||||||||
1975 | bool IsVecInReg = Op.getOpcode() == ISD::ANY_EXTEND_VECTOR_INREG; | ||||||||||
1976 | |||||||||||
1977 | // If we only need the bottom element then we can just bitcast. | ||||||||||
1978 | // TODO: Handle ANY_EXTEND? | ||||||||||
1979 | if (IsVecInReg && DemandedElts == 1 && | ||||||||||
1980 | VT.getSizeInBits() == SrcVT.getSizeInBits() && | ||||||||||
1981 | TLO.DAG.getDataLayout().isLittleEndian()) | ||||||||||
1982 | return TLO.CombineTo(Op, TLO.DAG.getBitcast(VT, Src)); | ||||||||||
1983 | |||||||||||
1984 | APInt InDemandedBits = DemandedBits.trunc(InBits); | ||||||||||
1985 | APInt InDemandedElts = DemandedElts.zextOrSelf(InElts); | ||||||||||
1986 | if (SimplifyDemandedBits(Src, InDemandedBits, InDemandedElts, Known, TLO, | ||||||||||
1987 | Depth + 1)) | ||||||||||
1988 | return true; | ||||||||||
1989 | assert(!Known.hasConflict() && "Bits known to be one AND zero?")(static_cast <bool> (!Known.hasConflict() && "Bits known to be one AND zero?" ) ? void (0) : __assert_fail ("!Known.hasConflict() && \"Bits known to be one AND zero?\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 1989, __extension__ __PRETTY_FUNCTION__)); | ||||||||||
1990 | assert(Known.getBitWidth() == InBits && "Src width has changed?")(static_cast <bool> (Known.getBitWidth() == InBits && "Src width has changed?") ? void (0) : __assert_fail ("Known.getBitWidth() == InBits && \"Src width has changed?\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 1990, __extension__ __PRETTY_FUNCTION__)); | ||||||||||
1991 | Known = Known.anyext(BitWidth); | ||||||||||
1992 | |||||||||||
1993 | // Attempt to avoid multi-use ops if we don't need anything from them. | ||||||||||
1994 | if (SDValue NewSrc = SimplifyMultipleUseDemandedBits( | ||||||||||
1995 | Src, InDemandedBits, InDemandedElts, TLO.DAG, Depth + 1)) | ||||||||||
1996 | return TLO.CombineTo(Op, TLO.DAG.getNode(Op.getOpcode(), dl, VT, NewSrc)); | ||||||||||
1997 | break; | ||||||||||
1998 | } | ||||||||||
1999 | case ISD::TRUNCATE: { | ||||||||||
2000 | SDValue Src = Op.getOperand(0); | ||||||||||
2001 | |||||||||||
2002 | // Simplify the input, using demanded bit information, and compute the known | ||||||||||
2003 | // zero/one bits live out. | ||||||||||
2004 | unsigned OperandBitWidth = Src.getScalarValueSizeInBits(); | ||||||||||
2005 | APInt TruncMask = DemandedBits.zext(OperandBitWidth); | ||||||||||
2006 | if (SimplifyDemandedBits(Src, TruncMask, DemandedElts, Known, TLO, | ||||||||||
2007 | Depth + 1)) | ||||||||||
2008 | return true; | ||||||||||
2009 | Known = Known.trunc(BitWidth); | ||||||||||
2010 | |||||||||||
2011 | // Attempt to avoid multi-use ops if we don't need anything from them. | ||||||||||
2012 | if (SDValue NewSrc = SimplifyMultipleUseDemandedBits( | ||||||||||
2013 | Src, TruncMask, DemandedElts, TLO.DAG, Depth + 1)) | ||||||||||
2014 | return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::TRUNCATE, dl, VT, NewSrc)); | ||||||||||
2015 | |||||||||||
2016 | // If the input is only used by this truncate, see if we can shrink it based | ||||||||||
2017 | // on the known demanded bits. | ||||||||||
2018 | if (Src.getNode()->hasOneUse()) { | ||||||||||
2019 | switch (Src.getOpcode()) { | ||||||||||
2020 | default: | ||||||||||
2021 | break; | ||||||||||
2022 | case ISD::SRL: | ||||||||||
2023 | // Shrink SRL by a constant if none of the high bits shifted in are | ||||||||||
2024 | // demanded. | ||||||||||
2025 | if (TLO.LegalTypes() && !isTypeDesirableForOp(ISD::SRL, VT)) | ||||||||||
2026 | // Do not turn (vt1 truncate (vt2 srl)) into (vt1 srl) if vt1 is | ||||||||||
2027 | // undesirable. | ||||||||||
2028 | break; | ||||||||||
2029 | |||||||||||
2030 | const APInt *ShAmtC = | ||||||||||
2031 | TLO.DAG.getValidShiftAmountConstant(Src, DemandedElts); | ||||||||||
2032 | if (!ShAmtC || ShAmtC->uge(BitWidth)) | ||||||||||
2033 | break; | ||||||||||
2034 | uint64_t ShVal = ShAmtC->getZExtValue(); | ||||||||||
2035 | |||||||||||
2036 | APInt HighBits = | ||||||||||
2037 | APInt::getHighBitsSet(OperandBitWidth, OperandBitWidth - BitWidth); | ||||||||||
2038 | HighBits.lshrInPlace(ShVal); | ||||||||||
2039 | HighBits = HighBits.trunc(BitWidth); | ||||||||||
2040 | |||||||||||
2041 | if (!(HighBits & DemandedBits)) { | ||||||||||
2042 | // None of the shifted in bits are needed. Add a truncate of the | ||||||||||
2043 | // shift input, then shift it. | ||||||||||
2044 | SDValue NewShAmt = TLO.DAG.getConstant( | ||||||||||
2045 | ShVal, dl, getShiftAmountTy(VT, DL, TLO.LegalTypes())); | ||||||||||
2046 | SDValue NewTrunc = | ||||||||||
2047 | TLO.DAG.getNode(ISD::TRUNCATE, dl, VT, Src.getOperand(0)); | ||||||||||
2048 | return TLO.CombineTo( | ||||||||||
2049 | Op, TLO.DAG.getNode(ISD::SRL, dl, VT, NewTrunc, NewShAmt)); | ||||||||||
2050 | } | ||||||||||
2051 | break; | ||||||||||
2052 | } | ||||||||||
2053 | } | ||||||||||
2054 | |||||||||||
2055 | assert(!Known.hasConflict() && "Bits known to be one AND zero?")(static_cast <bool> (!Known.hasConflict() && "Bits known to be one AND zero?" ) ? void (0) : __assert_fail ("!Known.hasConflict() && \"Bits known to be one AND zero?\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 2055, __extension__ __PRETTY_FUNCTION__)); | ||||||||||
2056 | break; | ||||||||||
2057 | } | ||||||||||
2058 | case ISD::AssertZext: { | ||||||||||
2059 | // AssertZext demands all of the high bits, plus any of the low bits | ||||||||||
2060 | // demanded by its users. | ||||||||||
2061 | EVT ZVT = cast<VTSDNode>(Op.getOperand(1))->getVT(); | ||||||||||
2062 | APInt InMask = APInt::getLowBitsSet(BitWidth, ZVT.getSizeInBits()); | ||||||||||
2063 | if (SimplifyDemandedBits(Op.getOperand(0), ~InMask | DemandedBits, Known, | ||||||||||
2064 | TLO, Depth + 1)) | ||||||||||
2065 | return true; | ||||||||||
2066 | assert(!Known.hasConflict() && "Bits known to be one AND zero?")(static_cast <bool> (!Known.hasConflict() && "Bits known to be one AND zero?" ) ? void (0) : __assert_fail ("!Known.hasConflict() && \"Bits known to be one AND zero?\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 2066, __extension__ __PRETTY_FUNCTION__)); | ||||||||||
2067 | |||||||||||
2068 | Known.Zero |= ~InMask; | ||||||||||
2069 | break; | ||||||||||
2070 | } | ||||||||||
2071 | case ISD::EXTRACT_VECTOR_ELT: { | ||||||||||
2072 | SDValue Src = Op.getOperand(0); | ||||||||||
2073 | SDValue Idx = Op.getOperand(1); | ||||||||||
2074 | ElementCount SrcEltCnt = Src.getValueType().getVectorElementCount(); | ||||||||||
2075 | unsigned EltBitWidth = Src.getScalarValueSizeInBits(); | ||||||||||
2076 | |||||||||||
2077 | if (SrcEltCnt.isScalable()) | ||||||||||
2078 | return false; | ||||||||||
2079 | |||||||||||
2080 | // Demand the bits from every vector element without a constant index. | ||||||||||
2081 | unsigned NumSrcElts = SrcEltCnt.getFixedValue(); | ||||||||||
2082 | APInt DemandedSrcElts = APInt::getAllOnes(NumSrcElts); | ||||||||||
2083 | if (auto *CIdx = dyn_cast<ConstantSDNode>(Idx)) | ||||||||||
2084 | if (CIdx->getAPIntValue().ult(NumSrcElts)) | ||||||||||
2085 | DemandedSrcElts = APInt::getOneBitSet(NumSrcElts, CIdx->getZExtValue()); | ||||||||||
2086 | |||||||||||
2087 | // If BitWidth > EltBitWidth the value is anyext:ed. So we do not know | ||||||||||
2088 | // anything about the extended bits. | ||||||||||
2089 | APInt DemandedSrcBits = DemandedBits; | ||||||||||
2090 | if (BitWidth > EltBitWidth) | ||||||||||
2091 | DemandedSrcBits = DemandedSrcBits.trunc(EltBitWidth); | ||||||||||
2092 | |||||||||||
2093 | if (SimplifyDemandedBits(Src, DemandedSrcBits, DemandedSrcElts, Known2, TLO, | ||||||||||
2094 | Depth + 1)) | ||||||||||
2095 | return true; | ||||||||||
2096 | |||||||||||
2097 | // Attempt to avoid multi-use ops if we don't need anything from them. | ||||||||||
2098 | if (!DemandedSrcBits.isAllOnes() || !DemandedSrcElts.isAllOnes()) { | ||||||||||
2099 | if (SDValue DemandedSrc = SimplifyMultipleUseDemandedBits( | ||||||||||
2100 | Src, DemandedSrcBits, DemandedSrcElts, TLO.DAG, Depth + 1)) { | ||||||||||
2101 | SDValue NewOp = | ||||||||||
2102 | TLO.DAG.getNode(Op.getOpcode(), dl, VT, DemandedSrc, Idx); | ||||||||||
2103 | return TLO.CombineTo(Op, NewOp); | ||||||||||
2104 | } | ||||||||||
2105 | } | ||||||||||
2106 | |||||||||||
2107 | Known = Known2; | ||||||||||
2108 | if (BitWidth > EltBitWidth) | ||||||||||
2109 | Known = Known.anyext(BitWidth); | ||||||||||
2110 | break; | ||||||||||
2111 | } | ||||||||||
2112 | case ISD::BITCAST: { | ||||||||||
2113 | SDValue Src = Op.getOperand(0); | ||||||||||
2114 | EVT SrcVT = Src.getValueType(); | ||||||||||
2115 | unsigned NumSrcEltBits = SrcVT.getScalarSizeInBits(); | ||||||||||
2116 | |||||||||||
2117 | // If this is an FP->Int bitcast and if the sign bit is the only | ||||||||||
2118 | // thing demanded, turn this into a FGETSIGN. | ||||||||||
2119 | if (!TLO.LegalOperations() && !VT.isVector() && !SrcVT.isVector() && | ||||||||||
2120 | DemandedBits == APInt::getSignMask(Op.getValueSizeInBits()) && | ||||||||||
2121 | SrcVT.isFloatingPoint()) { | ||||||||||
2122 | bool OpVTLegal = isOperationLegalOrCustom(ISD::FGETSIGN, VT); | ||||||||||
2123 | bool i32Legal = isOperationLegalOrCustom(ISD::FGETSIGN, MVT::i32); | ||||||||||
2124 | if ((OpVTLegal || i32Legal) && VT.isSimple() && SrcVT != MVT::f16 && | ||||||||||
2125 | SrcVT != MVT::f128) { | ||||||||||
2126 | // Cannot eliminate/lower SHL for f128 yet. | ||||||||||
2127 | EVT Ty = OpVTLegal ? VT : MVT::i32; | ||||||||||
2128 | // Make a FGETSIGN + SHL to move the sign bit into the appropriate | ||||||||||
2129 | // place. We expect the SHL to be eliminated by other optimizations. | ||||||||||
2130 | SDValue Sign = TLO.DAG.getNode(ISD::FGETSIGN, dl, Ty, Src); | ||||||||||
2131 | unsigned OpVTSizeInBits = Op.getValueSizeInBits(); | ||||||||||
2132 | if (!OpVTLegal && OpVTSizeInBits > 32) | ||||||||||
2133 | Sign = TLO.DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Sign); | ||||||||||
2134 | unsigned ShVal = Op.getValueSizeInBits() - 1; | ||||||||||
2135 | SDValue ShAmt = TLO.DAG.getConstant(ShVal, dl, VT); | ||||||||||
2136 | return TLO.CombineTo(Op, | ||||||||||
2137 | TLO.DAG.getNode(ISD::SHL, dl, VT, Sign, ShAmt)); | ||||||||||
2138 | } | ||||||||||
2139 | } | ||||||||||
2140 | |||||||||||
2141 | // Bitcast from a vector using SimplifyDemanded Bits/VectorElts. | ||||||||||
2142 | // Demand the elt/bit if any of the original elts/bits are demanded. | ||||||||||
2143 | // TODO - bigendian once we have test coverage. | ||||||||||
2144 | if (SrcVT.isVector() && (BitWidth % NumSrcEltBits) == 0 && | ||||||||||
2145 | TLO.DAG.getDataLayout().isLittleEndian()) { | ||||||||||
2146 | unsigned Scale = BitWidth / NumSrcEltBits; | ||||||||||
2147 | unsigned NumSrcElts = SrcVT.getVectorNumElements(); | ||||||||||
2148 | APInt DemandedSrcBits = APInt::getZero(NumSrcEltBits); | ||||||||||
2149 | APInt DemandedSrcElts = APInt::getZero(NumSrcElts); | ||||||||||
2150 | for (unsigned i = 0; i != Scale; ++i) { | ||||||||||
2151 | unsigned Offset = i * NumSrcEltBits; | ||||||||||
2152 | APInt Sub = DemandedBits.extractBits(NumSrcEltBits, Offset); | ||||||||||
2153 | if (!Sub.isZero()) { | ||||||||||
2154 | DemandedSrcBits |= Sub; | ||||||||||
2155 | for (unsigned j = 0; j != NumElts; ++j) | ||||||||||
2156 | if (DemandedElts[j]) | ||||||||||
2157 | DemandedSrcElts.setBit((j * Scale) + i); | ||||||||||
2158 | } | ||||||||||
2159 | } | ||||||||||
2160 | |||||||||||
2161 | APInt KnownSrcUndef, KnownSrcZero; | ||||||||||
2162 | if (SimplifyDemandedVectorElts(Src, DemandedSrcElts, KnownSrcUndef, | ||||||||||
2163 | KnownSrcZero, TLO, Depth + 1)) | ||||||||||
2164 | return true; | ||||||||||
2165 | |||||||||||
2166 | KnownBits KnownSrcBits; | ||||||||||
2167 | if (SimplifyDemandedBits(Src, DemandedSrcBits, DemandedSrcElts, | ||||||||||
2168 | KnownSrcBits, TLO, Depth + 1)) | ||||||||||
2169 | return true; | ||||||||||
2170 | } else if ((NumSrcEltBits % BitWidth) == 0 && | ||||||||||
2171 | TLO.DAG.getDataLayout().isLittleEndian()) { | ||||||||||
2172 | unsigned Scale = NumSrcEltBits / BitWidth; | ||||||||||
2173 | unsigned NumSrcElts = SrcVT.isVector() ? SrcVT.getVectorNumElements() : 1; | ||||||||||
2174 | APInt DemandedSrcBits = APInt::getZero(NumSrcEltBits); | ||||||||||
2175 | APInt DemandedSrcElts = APInt::getZero(NumSrcElts); | ||||||||||
2176 | for (unsigned i = 0; i != NumElts; ++i) | ||||||||||
2177 | if (DemandedElts[i]) { | ||||||||||
2178 | unsigned Offset = (i % Scale) * BitWidth; | ||||||||||
2179 | DemandedSrcBits.insertBits(DemandedBits, Offset); | ||||||||||
2180 | DemandedSrcElts.setBit(i / Scale); | ||||||||||
2181 | } | ||||||||||
2182 | |||||||||||
2183 | if (SrcVT.isVector()) { | ||||||||||
2184 | APInt KnownSrcUndef, KnownSrcZero; | ||||||||||
2185 | if (SimplifyDemandedVectorElts(Src, DemandedSrcElts, KnownSrcUndef, | ||||||||||
2186 | KnownSrcZero, TLO, Depth + 1)) | ||||||||||
2187 | return true; | ||||||||||
2188 | } | ||||||||||
2189 | |||||||||||
2190 | KnownBits KnownSrcBits; | ||||||||||
2191 | if (SimplifyDemandedBits(Src, DemandedSrcBits, DemandedSrcElts, | ||||||||||
2192 | KnownSrcBits, TLO, Depth + 1)) | ||||||||||
2193 | return true; | ||||||||||
2194 | } | ||||||||||
2195 | |||||||||||
2196 | // If this is a bitcast, let computeKnownBits handle it. Only do this on a | ||||||||||
2197 | // recursive call where Known may be useful to the caller. | ||||||||||
2198 | if (Depth > 0) { | ||||||||||
2199 | Known = TLO.DAG.computeKnownBits(Op, DemandedElts, Depth); | ||||||||||
2200 | return false; | ||||||||||
2201 | } | ||||||||||
2202 | break; | ||||||||||
2203 | } | ||||||||||
2204 | case ISD::ADD: | ||||||||||
2205 | case ISD::MUL: | ||||||||||
2206 | case ISD::SUB: { | ||||||||||
2207 | // Add, Sub, and Mul don't demand any bits in positions beyond that | ||||||||||
2208 | // of the highest bit demanded of them. | ||||||||||
2209 | SDValue Op0 = Op.getOperand(0), Op1 = Op.getOperand(1); | ||||||||||
2210 | SDNodeFlags Flags = Op.getNode()->getFlags(); | ||||||||||
2211 | unsigned DemandedBitsLZ = DemandedBits.countLeadingZeros(); | ||||||||||
2212 | APInt LoMask = APInt::getLowBitsSet(BitWidth, BitWidth - DemandedBitsLZ); | ||||||||||
2213 | if (SimplifyDemandedBits(Op0, LoMask, DemandedElts, Known2, TLO, | ||||||||||
2214 | Depth + 1) || | ||||||||||
2215 | SimplifyDemandedBits(Op1, LoMask, DemandedElts, Known2, TLO, | ||||||||||
2216 | Depth + 1) || | ||||||||||
2217 | // See if the operation should be performed at a smaller bit width. | ||||||||||
2218 | ShrinkDemandedOp(Op, BitWidth, DemandedBits, TLO)) { | ||||||||||
2219 | if (Flags.hasNoSignedWrap() || Flags.hasNoUnsignedWrap()) { | ||||||||||
2220 | // Disable the nsw and nuw flags. We can no longer guarantee that we | ||||||||||
2221 | // won't wrap after simplification. | ||||||||||
2222 | Flags.setNoSignedWrap(false); | ||||||||||
2223 | Flags.setNoUnsignedWrap(false); | ||||||||||
2224 | SDValue NewOp = | ||||||||||
2225 | TLO.DAG.getNode(Op.getOpcode(), dl, VT, Op0, Op1, Flags); | ||||||||||
2226 | return TLO.CombineTo(Op, NewOp); | ||||||||||
2227 | } | ||||||||||
2228 | return true; | ||||||||||
2229 | } | ||||||||||
2230 | |||||||||||
2231 | // Attempt to avoid multi-use ops if we don't need anything from them. | ||||||||||
2232 | if (!LoMask.isAllOnes() || !DemandedElts.isAllOnes()) { | ||||||||||
2233 | SDValue DemandedOp0 = SimplifyMultipleUseDemandedBits( | ||||||||||
2234 | Op0, LoMask, DemandedElts, TLO.DAG, Depth + 1); | ||||||||||
2235 | SDValue DemandedOp1 = SimplifyMultipleUseDemandedBits( | ||||||||||
2236 | Op1, LoMask, DemandedElts, TLO.DAG, Depth + 1); | ||||||||||
2237 | if (DemandedOp0 || DemandedOp1) { | ||||||||||
2238 | Flags.setNoSignedWrap(false); | ||||||||||
2239 | Flags.setNoUnsignedWrap(false); | ||||||||||
2240 | Op0 = DemandedOp0 ? DemandedOp0 : Op0; | ||||||||||
2241 | Op1 = DemandedOp1 ? DemandedOp1 : Op1; | ||||||||||
2242 | SDValue NewOp = | ||||||||||
2243 | TLO.DAG.getNode(Op.getOpcode(), dl, VT, Op0, Op1, Flags); | ||||||||||
2244 | return TLO.CombineTo(Op, NewOp); | ||||||||||
2245 | } | ||||||||||
2246 | } | ||||||||||
2247 | |||||||||||
2248 | // If we have a constant operand, we may be able to turn it into -1 if we | ||||||||||
2249 | // do not demand the high bits. This can make the constant smaller to | ||||||||||
2250 | // encode, allow more general folding, or match specialized instruction | ||||||||||
2251 | // patterns (eg, 'blsr' on x86). Don't bother changing 1 to -1 because that | ||||||||||
2252 | // is probably not useful (and could be detrimental). | ||||||||||
2253 | ConstantSDNode *C = isConstOrConstSplat(Op1); | ||||||||||
2254 | APInt HighMask = APInt::getHighBitsSet(BitWidth, DemandedBitsLZ); | ||||||||||
2255 | if (C && !C->isAllOnes() && !C->isOne() && | ||||||||||
2256 | (C->getAPIntValue() | HighMask).isAllOnes()) { | ||||||||||
2257 | SDValue Neg1 = TLO.DAG.getAllOnesConstant(dl, VT); | ||||||||||
2258 | // Disable the nsw and nuw flags. We can no longer guarantee that we | ||||||||||
2259 | // won't wrap after simplification. | ||||||||||
2260 | Flags.setNoSignedWrap(false); | ||||||||||
2261 | Flags.setNoUnsignedWrap(false); | ||||||||||
2262 | SDValue NewOp = TLO.DAG.getNode(Op.getOpcode(), dl, VT, Op0, Neg1, Flags); | ||||||||||
2263 | return TLO.CombineTo(Op, NewOp); | ||||||||||
2264 | } | ||||||||||
2265 | |||||||||||
2266 | LLVM_FALLTHROUGH[[gnu::fallthrough]]; | ||||||||||
2267 | } | ||||||||||
2268 | default: | ||||||||||
2269 | if (Op.getOpcode() >= ISD::BUILTIN_OP_END) { | ||||||||||
2270 | if (SimplifyDemandedBitsForTargetNode(Op, DemandedBits, DemandedElts, | ||||||||||
2271 | Known, TLO, Depth)) | ||||||||||
2272 | return true; | ||||||||||
2273 | break; | ||||||||||
2274 | } | ||||||||||
2275 | |||||||||||
2276 | // Just use computeKnownBits to compute output bits. | ||||||||||
2277 | Known = TLO.DAG.computeKnownBits(Op, DemandedElts, Depth); | ||||||||||
2278 | break; | ||||||||||
2279 | } | ||||||||||
2280 | |||||||||||
2281 | // If we know the value of all of the demanded bits, return this as a | ||||||||||
2282 | // constant. | ||||||||||
2283 | if (DemandedBits.isSubsetOf(Known.Zero | Known.One)) { | ||||||||||
2284 | // Avoid folding to a constant if any OpaqueConstant is involved. | ||||||||||
2285 | const SDNode *N = Op.getNode(); | ||||||||||
2286 | for (SDNode *Op : | ||||||||||
2287 | llvm::make_range(SDNodeIterator::begin(N), SDNodeIterator::end(N))) { | ||||||||||
2288 | if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) | ||||||||||
2289 | if (C->isOpaque()) | ||||||||||
2290 | return false; | ||||||||||
2291 | } | ||||||||||
2292 | if (VT.isInteger()) | ||||||||||
2293 | return TLO.CombineTo(Op, TLO.DAG.getConstant(Known.One, dl, VT)); | ||||||||||
2294 | if (VT.isFloatingPoint()) | ||||||||||
2295 | return TLO.CombineTo( | ||||||||||
2296 | Op, | ||||||||||
2297 | TLO.DAG.getConstantFP( | ||||||||||
2298 | APFloat(TLO.DAG.EVTToAPFloatSemantics(VT), Known.One), dl, VT)); | ||||||||||
2299 | } | ||||||||||
2300 | |||||||||||
2301 | return false; | ||||||||||
2302 | } | ||||||||||
2303 | |||||||||||
2304 | bool TargetLowering::SimplifyDemandedVectorElts(SDValue Op, | ||||||||||
2305 | const APInt &DemandedElts, | ||||||||||
2306 | APInt &KnownUndef, | ||||||||||
2307 | APInt &KnownZero, | ||||||||||
2308 | DAGCombinerInfo &DCI) const { | ||||||||||
2309 | SelectionDAG &DAG = DCI.DAG; | ||||||||||
2310 | TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(), | ||||||||||
2311 | !DCI.isBeforeLegalizeOps()); | ||||||||||
2312 | |||||||||||
2313 | bool Simplified = | ||||||||||
2314 | SimplifyDemandedVectorElts(Op, DemandedElts, KnownUndef, KnownZero, TLO); | ||||||||||
2315 | if (Simplified) { | ||||||||||
2316 | DCI.AddToWorklist(Op.getNode()); | ||||||||||
2317 | DCI.CommitTargetLoweringOpt(TLO); | ||||||||||
2318 | } | ||||||||||
2319 | |||||||||||
2320 | return Simplified; | ||||||||||
2321 | } | ||||||||||
2322 | |||||||||||
2323 | /// Given a vector binary operation and known undefined elements for each input | ||||||||||
2324 | /// operand, compute whether each element of the output is undefined. | ||||||||||
2325 | static APInt getKnownUndefForVectorBinop(SDValue BO, SelectionDAG &DAG, | ||||||||||
2326 | const APInt &UndefOp0, | ||||||||||
2327 | const APInt &UndefOp1) { | ||||||||||
2328 | EVT VT = BO.getValueType(); | ||||||||||
2329 | assert(DAG.getTargetLoweringInfo().isBinOp(BO.getOpcode()) && VT.isVector() &&(static_cast <bool> (DAG.getTargetLoweringInfo().isBinOp (BO.getOpcode()) && VT.isVector() && "Vector binop only" ) ? void (0) : __assert_fail ("DAG.getTargetLoweringInfo().isBinOp(BO.getOpcode()) && VT.isVector() && \"Vector binop only\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 2330, __extension__ __PRETTY_FUNCTION__)) | ||||||||||
2330 | "Vector binop only")(static_cast <bool> (DAG.getTargetLoweringInfo().isBinOp (BO.getOpcode()) && VT.isVector() && "Vector binop only" ) ? void (0) : __assert_fail ("DAG.getTargetLoweringInfo().isBinOp(BO.getOpcode()) && VT.isVector() && \"Vector binop only\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 2330, __extension__ __PRETTY_FUNCTION__)); | ||||||||||
2331 | |||||||||||
2332 | EVT EltVT = VT.getVectorElementType(); | ||||||||||
2333 | unsigned NumElts = VT.getVectorNumElements(); | ||||||||||
2334 | assert(UndefOp0.getBitWidth() == NumElts &&(static_cast <bool> (UndefOp0.getBitWidth() == NumElts && UndefOp1.getBitWidth() == NumElts && "Bad type for undef analysis" ) ? void (0) : __assert_fail ("UndefOp0.getBitWidth() == NumElts && UndefOp1.getBitWidth() == NumElts && \"Bad type for undef analysis\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 2335, __extension__ __PRETTY_FUNCTION__)) | ||||||||||
2335 | UndefOp1.getBitWidth() == NumElts && "Bad type for undef analysis")(static_cast <bool> (UndefOp0.getBitWidth() == NumElts && UndefOp1.getBitWidth() == NumElts && "Bad type for undef analysis" ) ? void (0) : __assert_fail ("UndefOp0.getBitWidth() == NumElts && UndefOp1.getBitWidth() == NumElts && \"Bad type for undef analysis\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 2335, __extension__ __PRETTY_FUNCTION__)); | ||||||||||
2336 | |||||||||||
2337 | auto getUndefOrConstantElt = [&](SDValue V, unsigned Index, | ||||||||||
2338 | const APInt &UndefVals) { | ||||||||||
2339 | if (UndefVals[Index]) | ||||||||||
2340 | return DAG.getUNDEF(EltVT); | ||||||||||
2341 | |||||||||||
2342 | if (auto *BV = dyn_cast<BuildVectorSDNode>(V)) { | ||||||||||
2343 | // Try hard to make sure that the getNode() call is not creating temporary | ||||||||||
2344 | // nodes. Ignore opaque integers because they do not constant fold. | ||||||||||
2345 | SDValue Elt = BV->getOperand(Index); | ||||||||||
2346 | auto *C = dyn_cast<ConstantSDNode>(Elt); | ||||||||||
2347 | if (isa<ConstantFPSDNode>(Elt) || Elt.isUndef() || (C && !C->isOpaque())) | ||||||||||
2348 | return Elt; | ||||||||||
2349 | } | ||||||||||
2350 | |||||||||||
2351 | return SDValue(); | ||||||||||
2352 | }; | ||||||||||
2353 | |||||||||||
2354 | APInt KnownUndef = APInt::getZero(NumElts); | ||||||||||
2355 | for (unsigned i = 0; i != NumElts; ++i) { | ||||||||||
2356 | // If both inputs for this element are either constant or undef and match | ||||||||||
2357 | // the element type, compute the constant/undef result for this element of | ||||||||||
2358 | // the vector. | ||||||||||
2359 | // TODO: Ideally we would use FoldConstantArithmetic() here, but that does | ||||||||||
2360 | // not handle FP constants. The code within getNode() should be refactored | ||||||||||
2361 | // to avoid the danger of creating a bogus temporary node here. | ||||||||||
2362 | SDValue C0 = getUndefOrConstantElt(BO.getOperand(0), i, UndefOp0); | ||||||||||
2363 | SDValue C1 = getUndefOrConstantElt(BO.getOperand(1), i, UndefOp1); | ||||||||||
2364 | if (C0 && C1 && C0.getValueType() == EltVT && C1.getValueType() == EltVT) | ||||||||||
2365 | if (DAG.getNode(BO.getOpcode(), SDLoc(BO), EltVT, C0, C1).isUndef()) | ||||||||||
2366 | KnownUndef.setBit(i); | ||||||||||
2367 | } | ||||||||||
2368 | return KnownUndef; | ||||||||||
2369 | } | ||||||||||
2370 | |||||||||||
2371 | bool TargetLowering::SimplifyDemandedVectorElts( | ||||||||||
2372 | SDValue Op, const APInt &OriginalDemandedElts, APInt &KnownUndef, | ||||||||||
2373 | APInt &KnownZero, TargetLoweringOpt &TLO, unsigned Depth, | ||||||||||
2374 | bool AssumeSingleUse) const { | ||||||||||
2375 | EVT VT = Op.getValueType(); | ||||||||||
2376 | unsigned Opcode = Op.getOpcode(); | ||||||||||
2377 | APInt DemandedElts = OriginalDemandedElts; | ||||||||||
2378 | unsigned NumElts = DemandedElts.getBitWidth(); | ||||||||||
2379 | assert(VT.isVector() && "Expected vector op")(static_cast <bool> (VT.isVector() && "Expected vector op" ) ? void (0) : __assert_fail ("VT.isVector() && \"Expected vector op\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 2379, __extension__ __PRETTY_FUNCTION__)); | ||||||||||
2380 | |||||||||||
2381 | KnownUndef = KnownZero = APInt::getZero(NumElts); | ||||||||||
2382 | |||||||||||
2383 | // TODO: For now we assume we know nothing about scalable vectors. | ||||||||||
2384 | if (VT.isScalableVector()) | ||||||||||
2385 | return false; | ||||||||||
2386 | |||||||||||
2387 | assert(VT.getVectorNumElements() == NumElts &&(static_cast <bool> (VT.getVectorNumElements() == NumElts && "Mask size mismatches value type element count!") ? void (0) : __assert_fail ("VT.getVectorNumElements() == NumElts && \"Mask size mismatches value type element count!\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 2388, __extension__ __PRETTY_FUNCTION__)) | ||||||||||
2388 | "Mask size mismatches value type element count!")(static_cast <bool> (VT.getVectorNumElements() == NumElts && "Mask size mismatches value type element count!") ? void (0) : __assert_fail ("VT.getVectorNumElements() == NumElts && \"Mask size mismatches value type element count!\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 2388, __extension__ __PRETTY_FUNCTION__)); | ||||||||||
2389 | |||||||||||
2390 | // Undef operand. | ||||||||||
2391 | if (Op.isUndef()) { | ||||||||||
2392 | KnownUndef.setAllBits(); | ||||||||||
2393 | return false; | ||||||||||
2394 | } | ||||||||||
2395 | |||||||||||
2396 | // If Op has other users, assume that all elements are needed. | ||||||||||
2397 | if (!Op.getNode()->hasOneUse() && !AssumeSingleUse) | ||||||||||
2398 | DemandedElts.setAllBits(); | ||||||||||
2399 | |||||||||||
2400 | // Not demanding any elements from Op. | ||||||||||
2401 | if (DemandedElts == 0) { | ||||||||||
2402 | KnownUndef.setAllBits(); | ||||||||||
2403 | return TLO.CombineTo(Op, TLO.DAG.getUNDEF(VT)); | ||||||||||
2404 | } | ||||||||||
2405 | |||||||||||
2406 | // Limit search depth. | ||||||||||
2407 | if (Depth >= SelectionDAG::MaxRecursionDepth) | ||||||||||
2408 | return false; | ||||||||||
2409 | |||||||||||
2410 | SDLoc DL(Op); | ||||||||||
2411 | unsigned EltSizeInBits = VT.getScalarSizeInBits(); | ||||||||||
2412 | |||||||||||
2413 | // Helper for demanding the specified elements and all the bits of both binary | ||||||||||
2414 | // operands. | ||||||||||
2415 | auto SimplifyDemandedVectorEltsBinOp = [&](SDValue Op0, SDValue Op1) { | ||||||||||
2416 | SDValue NewOp0 = SimplifyMultipleUseDemandedVectorElts(Op0, DemandedElts, | ||||||||||
2417 | TLO.DAG, Depth + 1); | ||||||||||
2418 | SDValue NewOp1 = SimplifyMultipleUseDemandedVectorElts(Op1, DemandedElts, | ||||||||||
2419 | TLO.DAG, Depth + 1); | ||||||||||
2420 | if (NewOp0 || NewOp1) { | ||||||||||
2421 | SDValue NewOp = TLO.DAG.getNode( | ||||||||||
2422 | Opcode, SDLoc(Op), VT, NewOp0 ? NewOp0 : Op0, NewOp1 ? NewOp1 : Op1); | ||||||||||
2423 | return TLO.CombineTo(Op, NewOp); | ||||||||||
2424 | } | ||||||||||
2425 | return false; | ||||||||||
2426 | }; | ||||||||||
2427 | |||||||||||
2428 | switch (Opcode) { | ||||||||||
2429 | case ISD::SCALAR_TO_VECTOR: { | ||||||||||
2430 | if (!DemandedElts[0]) { | ||||||||||
2431 | KnownUndef.setAllBits(); | ||||||||||
2432 | return TLO.CombineTo(Op, TLO.DAG.getUNDEF(VT)); | ||||||||||
2433 | } | ||||||||||
2434 | SDValue ScalarSrc = Op.getOperand(0); | ||||||||||
2435 | if (ScalarSrc.getOpcode() == ISD::EXTRACT_VECTOR_ELT) { | ||||||||||
2436 | SDValue Src = ScalarSrc.getOperand(0); | ||||||||||
2437 | SDValue Idx = ScalarSrc.getOperand(1); | ||||||||||
2438 | EVT SrcVT = Src.getValueType(); | ||||||||||
2439 | |||||||||||
2440 | ElementCount SrcEltCnt = SrcVT.getVectorElementCount(); | ||||||||||
2441 | |||||||||||
2442 | if (SrcEltCnt.isScalable()) | ||||||||||
2443 | return false; | ||||||||||
2444 | |||||||||||
2445 | unsigned NumSrcElts = SrcEltCnt.getFixedValue(); | ||||||||||
2446 | if (isNullConstant(Idx)) { | ||||||||||
2447 | APInt SrcDemandedElts = APInt::getOneBitSet(NumSrcElts, 0); | ||||||||||
2448 | APInt SrcUndef = KnownUndef.zextOrTrunc(NumSrcElts); | ||||||||||
2449 | APInt SrcZero = KnownZero.zextOrTrunc(NumSrcElts); | ||||||||||
2450 | if (SimplifyDemandedVectorElts(Src, SrcDemandedElts, SrcUndef, SrcZero, | ||||||||||
2451 | TLO, Depth + 1)) | ||||||||||
2452 | return true; | ||||||||||
2453 | } | ||||||||||
2454 | } | ||||||||||
2455 | KnownUndef.setHighBits(NumElts - 1); | ||||||||||
2456 | break; | ||||||||||
2457 | } | ||||||||||
2458 | case ISD::BITCAST: { | ||||||||||
2459 | SDValue Src = Op.getOperand(0); | ||||||||||
2460 | EVT SrcVT = Src.getValueType(); | ||||||||||
2461 | |||||||||||
2462 | // We only handle vectors here. | ||||||||||
2463 | // TODO - investigate calling SimplifyDemandedBits/ComputeKnownBits? | ||||||||||
2464 | if (!SrcVT.isVector()) | ||||||||||
2465 | break; | ||||||||||
2466 | |||||||||||
2467 | // Fast handling of 'identity' bitcasts. | ||||||||||
2468 | unsigned NumSrcElts = SrcVT.getVectorNumElements(); | ||||||||||
2469 | if (NumSrcElts == NumElts) | ||||||||||
2470 | return SimplifyDemandedVectorElts(Src, DemandedElts, KnownUndef, | ||||||||||
2471 | KnownZero, TLO, Depth + 1); | ||||||||||
2472 | |||||||||||
2473 | APInt SrcDemandedElts, SrcZero, SrcUndef; | ||||||||||
2474 | |||||||||||
2475 | // Bitcast from 'large element' src vector to 'small element' vector, we | ||||||||||
2476 | // must demand a source element if any DemandedElt maps to it. | ||||||||||
2477 | if ((NumElts % NumSrcElts) == 0) { | ||||||||||
2478 | unsigned Scale = NumElts / NumSrcElts; | ||||||||||
2479 | SrcDemandedElts = APIntOps::ScaleBitMask(DemandedElts, NumSrcElts); | ||||||||||
2480 | if (SimplifyDemandedVectorElts(Src, SrcDemandedElts, SrcUndef, SrcZero, | ||||||||||
2481 | TLO, Depth + 1)) | ||||||||||
2482 | return true; | ||||||||||
2483 | |||||||||||
2484 | // Try calling SimplifyDemandedBits, converting demanded elts to the bits | ||||||||||
2485 | // of the large element. | ||||||||||
2486 | // TODO - bigendian once we have test coverage. | ||||||||||
2487 | if (TLO.DAG.getDataLayout().isLittleEndian()) { | ||||||||||
2488 | unsigned SrcEltSizeInBits = SrcVT.getScalarSizeInBits(); | ||||||||||
2489 | APInt SrcDemandedBits = APInt::getZero(SrcEltSizeInBits); | ||||||||||
2490 | for (unsigned i = 0; i != NumElts; ++i) | ||||||||||
2491 | if (DemandedElts[i]) { | ||||||||||
2492 | unsigned Ofs = (i % Scale) * EltSizeInBits; | ||||||||||
2493 | SrcDemandedBits.setBits(Ofs, Ofs + EltSizeInBits); | ||||||||||
2494 | } | ||||||||||
2495 | |||||||||||
2496 | KnownBits Known; | ||||||||||
2497 | if (SimplifyDemandedBits(Src, SrcDemandedBits, SrcDemandedElts, Known, | ||||||||||
2498 | TLO, Depth + 1)) | ||||||||||
2499 | return true; | ||||||||||
2500 | } | ||||||||||
2501 | |||||||||||
2502 | // If the src element is zero/undef then all the output elements will be - | ||||||||||
2503 | // only demanded elements are guaranteed to be correct. | ||||||||||
2504 | for (unsigned i = 0; i != NumSrcElts; ++i) { | ||||||||||
2505 | if (SrcDemandedElts[i]) { | ||||||||||
2506 | if (SrcZero[i]) | ||||||||||
2507 | KnownZero.setBits(i * Scale, (i + 1) * Scale); | ||||||||||
2508 | if (SrcUndef[i]) | ||||||||||
2509 | KnownUndef.setBits(i * Scale, (i + 1) * Scale); | ||||||||||
2510 | } | ||||||||||
2511 | } | ||||||||||
2512 | } | ||||||||||
2513 | |||||||||||
2514 | // Bitcast from 'small element' src vector to 'large element' vector, we | ||||||||||
2515 | // demand all smaller source elements covered by the larger demanded element | ||||||||||
2516 | // of this vector. | ||||||||||
2517 | if ((NumSrcElts % NumElts) == 0) { | ||||||||||
2518 | unsigned Scale = NumSrcElts / NumElts; | ||||||||||
2519 | SrcDemandedElts = APIntOps::ScaleBitMask(DemandedElts, NumSrcElts); | ||||||||||
2520 | if (SimplifyDemandedVectorElts(Src, SrcDemandedElts, SrcUndef, SrcZero, | ||||||||||
2521 | TLO, Depth + 1)) | ||||||||||
2522 | return true; | ||||||||||
2523 | |||||||||||
2524 | // If all the src elements covering an output element are zero/undef, then | ||||||||||
2525 | // the output element will be as well, assuming it was demanded. | ||||||||||
2526 | for (unsigned i = 0; i != NumElts; ++i) { | ||||||||||
2527 | if (DemandedElts[i]) { | ||||||||||
2528 | if (SrcZero.extractBits(Scale, i * Scale).isAllOnes()) | ||||||||||
2529 | KnownZero.setBit(i); | ||||||||||
2530 | if (SrcUndef.extractBits(Scale, i * Scale).isAllOnes()) | ||||||||||
2531 | KnownUndef.setBit(i); | ||||||||||
2532 | } | ||||||||||
2533 | } | ||||||||||
2534 | } | ||||||||||
2535 | break; | ||||||||||
2536 | } | ||||||||||
2537 | case ISD::BUILD_VECTOR: { | ||||||||||
2538 | // Check all elements and simplify any unused elements with UNDEF. | ||||||||||
2539 | if (!DemandedElts.isAllOnes()) { | ||||||||||
2540 | // Don't simplify BROADCASTS. | ||||||||||
2541 | if (llvm::any_of(Op->op_values(), | ||||||||||
2542 | [&](SDValue Elt) { return Op.getOperand(0) != Elt; })) { | ||||||||||
2543 | SmallVector<SDValue, 32> Ops(Op->op_begin(), Op->op_end()); | ||||||||||
2544 | bool Updated = false; | ||||||||||
2545 | for (unsigned i = 0; i != NumElts; ++i) { | ||||||||||
2546 | if (!DemandedElts[i] && !Ops[i].isUndef()) { | ||||||||||
2547 | Ops[i] = TLO.DAG.getUNDEF(Ops[0].getValueType()); | ||||||||||
2548 | KnownUndef.setBit(i); | ||||||||||
2549 | Updated = true; | ||||||||||
2550 | } | ||||||||||
2551 | } | ||||||||||
2552 | if (Updated) | ||||||||||
2553 | return TLO.CombineTo(Op, TLO.DAG.getBuildVector(VT, DL, Ops)); | ||||||||||
2554 | } | ||||||||||
2555 | } | ||||||||||
2556 | for (unsigned i = 0; i != NumElts; ++i) { | ||||||||||
2557 | SDValue SrcOp = Op.getOperand(i); | ||||||||||
2558 | if (SrcOp.isUndef()) { | ||||||||||
2559 | KnownUndef.setBit(i); | ||||||||||
2560 | } else if (EltSizeInBits == SrcOp.getScalarValueSizeInBits() && | ||||||||||
2561 | (isNullConstant(SrcOp) || isNullFPConstant(SrcOp))) { | ||||||||||
2562 | KnownZero.setBit(i); | ||||||||||
2563 | } | ||||||||||
2564 | } | ||||||||||
2565 | break; | ||||||||||
2566 | } | ||||||||||
2567 | case ISD::CONCAT_VECTORS: { | ||||||||||
2568 | EVT SubVT = Op.getOperand(0).getValueType(); | ||||||||||
2569 | unsigned NumSubVecs = Op.getNumOperands(); | ||||||||||
2570 | unsigned NumSubElts = SubVT.getVectorNumElements(); | ||||||||||
2571 | for (unsigned i = 0; i != NumSubVecs; ++i) { | ||||||||||
2572 | SDValue SubOp = Op.getOperand(i); | ||||||||||
2573 | APInt SubElts = DemandedElts.extractBits(NumSubElts, i * NumSubElts); | ||||||||||
2574 | APInt SubUndef, SubZero; | ||||||||||
2575 | if (SimplifyDemandedVectorElts(SubOp, SubElts, SubUndef, SubZero, TLO, | ||||||||||
2576 | Depth + 1)) | ||||||||||
2577 | return true; | ||||||||||
2578 | KnownUndef.insertBits(SubUndef, i * NumSubElts); | ||||||||||
2579 | KnownZero.insertBits(SubZero, i * NumSubElts); | ||||||||||
2580 | } | ||||||||||
2581 | break; | ||||||||||
2582 | } | ||||||||||
2583 | case ISD::INSERT_SUBVECTOR: { | ||||||||||
2584 | // Demand any elements from the subvector and the remainder from the src its | ||||||||||
2585 | // inserted into. | ||||||||||
2586 | SDValue Src = Op.getOperand(0); | ||||||||||
2587 | SDValue Sub = Op.getOperand(1); | ||||||||||
2588 | uint64_t Idx = Op.getConstantOperandVal(2); | ||||||||||
2589 | unsigned NumSubElts = Sub.getValueType().getVectorNumElements(); | ||||||||||
2590 | APInt DemandedSubElts = DemandedElts.extractBits(NumSubElts, Idx); | ||||||||||
2591 | APInt DemandedSrcElts = DemandedElts; | ||||||||||
2592 | DemandedSrcElts.insertBits(APInt::getZero(NumSubElts), Idx); | ||||||||||
2593 | |||||||||||
2594 | APInt SubUndef, SubZero; | ||||||||||
2595 | if (SimplifyDemandedVectorElts(Sub, DemandedSubElts, SubUndef, SubZero, TLO, | ||||||||||
2596 | Depth + 1)) | ||||||||||
2597 | return true; | ||||||||||
2598 | |||||||||||
2599 | // If none of the src operand elements are demanded, replace it with undef. | ||||||||||
2600 | if (!DemandedSrcElts && !Src.isUndef()) | ||||||||||
2601 | return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::INSERT_SUBVECTOR, DL, VT, | ||||||||||
2602 | TLO.DAG.getUNDEF(VT), Sub, | ||||||||||
2603 | Op.getOperand(2))); | ||||||||||
2604 | |||||||||||
2605 | if (SimplifyDemandedVectorElts(Src, DemandedSrcElts, KnownUndef, KnownZero, | ||||||||||
2606 | TLO, Depth + 1)) | ||||||||||
2607 | return true; | ||||||||||
2608 | KnownUndef.insertBits(SubUndef, Idx); | ||||||||||
2609 | KnownZero.insertBits(SubZero, Idx); | ||||||||||
2610 | |||||||||||
2611 | // Attempt to avoid multi-use ops if we don't need anything from them. | ||||||||||
2612 | if (!DemandedSrcElts.isAllOnes() || !DemandedSubElts.isAllOnes()) { | ||||||||||
2613 | SDValue NewSrc = SimplifyMultipleUseDemandedVectorElts( | ||||||||||
2614 | Src, DemandedSrcElts, TLO.DAG, Depth + 1); | ||||||||||
2615 | SDValue NewSub = SimplifyMultipleUseDemandedVectorElts( | ||||||||||
2616 | Sub, DemandedSubElts, TLO.DAG, Depth + 1); | ||||||||||
2617 | if (NewSrc || NewSub) { | ||||||||||
2618 | NewSrc = NewSrc ? NewSrc : Src; | ||||||||||
2619 | NewSub = NewSub ? NewSub : Sub; | ||||||||||
2620 | SDValue NewOp = TLO.DAG.getNode(Op.getOpcode(), SDLoc(Op), VT, NewSrc, | ||||||||||
2621 | NewSub, Op.getOperand(2)); | ||||||||||
2622 | return TLO.CombineTo(Op, NewOp); | ||||||||||
2623 | } | ||||||||||
2624 | } | ||||||||||
2625 | break; | ||||||||||
2626 | } | ||||||||||
2627 | case ISD::EXTRACT_SUBVECTOR: { | ||||||||||
2628 | // Offset the demanded elts by the subvector index. | ||||||||||
2629 | SDValue Src = Op.getOperand(0); | ||||||||||
2630 | if (Src.getValueType().isScalableVector()) | ||||||||||
2631 | break; | ||||||||||
2632 | uint64_t Idx = Op.getConstantOperandVal(1); | ||||||||||
2633 | unsigned NumSrcElts = Src.getValueType().getVectorNumElements(); | ||||||||||
2634 | APInt DemandedSrcElts = DemandedElts.zextOrSelf(NumSrcElts).shl(Idx); | ||||||||||
2635 | |||||||||||
2636 | APInt SrcUndef, SrcZero; | ||||||||||
2637 | if (SimplifyDemandedVectorElts(Src, DemandedSrcElts, SrcUndef, SrcZero, TLO, | ||||||||||
2638 | Depth + 1)) | ||||||||||
2639 | return true; | ||||||||||
2640 | KnownUndef = SrcUndef.extractBits(NumElts, Idx); | ||||||||||
2641 | KnownZero = SrcZero.extractBits(NumElts, Idx); | ||||||||||
2642 | |||||||||||
2643 | // Attempt to avoid multi-use ops if we don't need anything from them. | ||||||||||
2644 | if (!DemandedElts.isAllOnes()) { | ||||||||||
2645 | SDValue NewSrc = SimplifyMultipleUseDemandedVectorElts( | ||||||||||
2646 | Src, DemandedSrcElts, TLO.DAG, Depth + 1); | ||||||||||
2647 | if (NewSrc) { | ||||||||||
2648 | SDValue NewOp = TLO.DAG.getNode(Op.getOpcode(), SDLoc(Op), VT, NewSrc, | ||||||||||
2649 | Op.getOperand(1)); | ||||||||||
2650 | return TLO.CombineTo(Op, NewOp); | ||||||||||
2651 | } | ||||||||||
2652 | } | ||||||||||
2653 | break; | ||||||||||
2654 | } | ||||||||||
2655 | case ISD::INSERT_VECTOR_ELT: { | ||||||||||
2656 | SDValue Vec = Op.getOperand(0); | ||||||||||
2657 | SDValue Scl = Op.getOperand(1); | ||||||||||
2658 | auto *CIdx = dyn_cast<ConstantSDNode>(Op.getOperand(2)); | ||||||||||
2659 | |||||||||||
2660 | // For a legal, constant insertion index, if we don't need this insertion | ||||||||||
2661 | // then strip it, else remove it from the demanded elts. | ||||||||||
2662 | if (CIdx && CIdx->getAPIntValue().ult(NumElts)) { | ||||||||||
2663 | unsigned Idx = CIdx->getZExtValue(); | ||||||||||
2664 | if (!DemandedElts[Idx]) | ||||||||||
2665 | return TLO.CombineTo(Op, Vec); | ||||||||||
2666 | |||||||||||
2667 | APInt DemandedVecElts(DemandedElts); | ||||||||||
2668 | DemandedVecElts.clearBit(Idx); | ||||||||||
2669 | if (SimplifyDemandedVectorElts(Vec, DemandedVecElts, KnownUndef, | ||||||||||
2670 | KnownZero, TLO, Depth + 1)) | ||||||||||
2671 | return true; | ||||||||||
2672 | |||||||||||
2673 | KnownUndef.setBitVal(Idx, Scl.isUndef()); | ||||||||||
2674 | |||||||||||
2675 | KnownZero.setBitVal(Idx, isNullConstant(Scl) || isNullFPConstant(Scl)); | ||||||||||
2676 | break; | ||||||||||
2677 | } | ||||||||||
2678 | |||||||||||
2679 | APInt VecUndef, VecZero; | ||||||||||
2680 | if (SimplifyDemandedVectorElts(Vec, DemandedElts, VecUndef, VecZero, TLO, | ||||||||||
2681 | Depth + 1)) | ||||||||||
2682 | return true; | ||||||||||
2683 | // Without knowing the insertion index we can't set KnownUndef/KnownZero. | ||||||||||
2684 | break; | ||||||||||
2685 | } | ||||||||||
2686 | case ISD::VSELECT: { | ||||||||||
2687 | // Try to transform the select condition based on the current demanded | ||||||||||
2688 | // elements. | ||||||||||
2689 | // TODO: If a condition element is undef, we can choose from one arm of the | ||||||||||
2690 | // select (and if one arm is undef, then we can propagate that to the | ||||||||||
2691 | // result). | ||||||||||
2692 | // TODO - add support for constant vselect masks (see IR version of this). | ||||||||||
2693 | APInt UnusedUndef, UnusedZero; | ||||||||||
2694 | if (SimplifyDemandedVectorElts(Op.getOperand(0), DemandedElts, UnusedUndef, | ||||||||||
2695 | UnusedZero, TLO, Depth + 1)) | ||||||||||
2696 | return true; | ||||||||||
2697 | |||||||||||
2698 | // See if we can simplify either vselect operand. | ||||||||||
2699 | APInt DemandedLHS(DemandedElts); | ||||||||||
2700 | APInt DemandedRHS(DemandedElts); | ||||||||||
2701 | APInt UndefLHS, ZeroLHS; | ||||||||||
2702 | APInt UndefRHS, ZeroRHS; | ||||||||||
2703 | if (SimplifyDemandedVectorElts(Op.getOperand(1), DemandedLHS, UndefLHS, | ||||||||||
2704 | ZeroLHS, TLO, Depth + 1)) | ||||||||||
2705 | return true; | ||||||||||
2706 | if (SimplifyDemandedVectorElts(Op.getOperand(2), DemandedRHS, UndefRHS, | ||||||||||
2707 | ZeroRHS, TLO, Depth + 1)) | ||||||||||
2708 | return true; | ||||||||||
2709 | |||||||||||
2710 | KnownUndef = UndefLHS & UndefRHS; | ||||||||||
2711 | KnownZero = ZeroLHS & ZeroRHS; | ||||||||||
2712 | break; | ||||||||||
2713 | } | ||||||||||
2714 | case ISD::VECTOR_SHUFFLE: { | ||||||||||
2715 | ArrayRef<int> ShuffleMask = cast<ShuffleVectorSDNode>(Op)->getMask(); | ||||||||||
2716 | |||||||||||
2717 | // Collect demanded elements from shuffle operands.. | ||||||||||
2718 | APInt DemandedLHS(NumElts, 0); | ||||||||||
2719 | APInt DemandedRHS(NumElts, 0); | ||||||||||
2720 | for (unsigned i = 0; i != NumElts; ++i) { | ||||||||||
2721 | int M = ShuffleMask[i]; | ||||||||||
2722 | if (M < 0 || !DemandedElts[i]) | ||||||||||
2723 | continue; | ||||||||||
2724 | assert(0 <= M && M < (int)(2 * NumElts) && "Shuffle index out of range")(static_cast <bool> (0 <= M && M < (int)( 2 * NumElts) && "Shuffle index out of range") ? void ( 0) : __assert_fail ("0 <= M && M < (int)(2 * NumElts) && \"Shuffle index out of range\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 2724, __extension__ __PRETTY_FUNCTION__)); | ||||||||||
2725 | if (M < (int)NumElts) | ||||||||||
2726 | DemandedLHS.setBit(M); | ||||||||||
2727 | else | ||||||||||
2728 | DemandedRHS.setBit(M - NumElts); | ||||||||||
2729 | } | ||||||||||
2730 | |||||||||||
2731 | // See if we can simplify either shuffle operand. | ||||||||||
2732 | APInt UndefLHS, ZeroLHS; | ||||||||||
2733 | APInt UndefRHS, ZeroRHS; | ||||||||||
2734 | if (SimplifyDemandedVectorElts(Op.getOperand(0), DemandedLHS, UndefLHS, | ||||||||||
2735 | ZeroLHS, TLO, Depth + 1)) | ||||||||||
2736 | return true; | ||||||||||
2737 | if (SimplifyDemandedVectorElts(Op.getOperand(1), DemandedRHS, UndefRHS, | ||||||||||
2738 | ZeroRHS, TLO, Depth + 1)) | ||||||||||
2739 | return true; | ||||||||||
2740 | |||||||||||
2741 | // Simplify mask using undef elements from LHS/RHS. | ||||||||||
2742 | bool Updated = false; | ||||||||||
2743 | bool IdentityLHS = true, IdentityRHS = true; | ||||||||||
2744 | SmallVector<int, 32> NewMask(ShuffleMask.begin(), ShuffleMask.end()); | ||||||||||
2745 | for (unsigned i = 0; i != NumElts; ++i) { | ||||||||||
2746 | int &M = NewMask[i]; | ||||||||||
2747 | if (M < 0) | ||||||||||
2748 | continue; | ||||||||||
2749 | if (!DemandedElts[i] || (M < (int)NumElts && UndefLHS[M]) || | ||||||||||
2750 | (M >= (int)NumElts && UndefRHS[M - NumElts])) { | ||||||||||
2751 | Updated = true; | ||||||||||
2752 | M = -1; | ||||||||||
2753 | } | ||||||||||
2754 | IdentityLHS &= (M < 0) || (M == (int)i); | ||||||||||
2755 | IdentityRHS &= (M < 0) || ((M - NumElts) == i); | ||||||||||
2756 | } | ||||||||||
2757 | |||||||||||
2758 | // Update legal shuffle masks based on demanded elements if it won't reduce | ||||||||||
2759 | // to Identity which can cause premature removal of the shuffle mask. | ||||||||||
2760 | if (Updated && !IdentityLHS && !IdentityRHS && !TLO.LegalOps) { | ||||||||||
2761 | SDValue LegalShuffle = | ||||||||||
2762 | buildLegalVectorShuffle(VT, DL, Op.getOperand(0), Op.getOperand(1), | ||||||||||
2763 | NewMask, TLO.DAG); | ||||||||||
2764 | if (LegalShuffle) | ||||||||||
2765 | return TLO.CombineTo(Op, LegalShuffle); | ||||||||||
2766 | } | ||||||||||
2767 | |||||||||||
2768 | // Propagate undef/zero elements from LHS/RHS. | ||||||||||
2769 | for (unsigned i = 0; i != NumElts; ++i) { | ||||||||||
2770 | int M = ShuffleMask[i]; | ||||||||||
2771 | if (M < 0) { | ||||||||||
2772 | KnownUndef.setBit(i); | ||||||||||
2773 | } else if (M < (int)NumElts) { | ||||||||||
2774 | if (UndefLHS[M]) | ||||||||||
2775 | KnownUndef.setBit(i); | ||||||||||
2776 | if (ZeroLHS[M]) | ||||||||||
2777 | KnownZero.setBit(i); | ||||||||||
2778 | } else { | ||||||||||
2779 | if (UndefRHS[M - NumElts]) | ||||||||||
2780 | KnownUndef.setBit(i); | ||||||||||
2781 | if (ZeroRHS[M - NumElts]) | ||||||||||
2782 | KnownZero.setBit(i); | ||||||||||
2783 | } | ||||||||||
2784 | } | ||||||||||
2785 | break; | ||||||||||
2786 | } | ||||||||||
2787 | case ISD::ANY_EXTEND_VECTOR_INREG: | ||||||||||
2788 | case ISD::SIGN_EXTEND_VECTOR_INREG: | ||||||||||
2789 | case ISD::ZERO_EXTEND_VECTOR_INREG: { | ||||||||||
2790 | APInt SrcUndef, SrcZero; | ||||||||||
2791 | SDValue Src = Op.getOperand(0); | ||||||||||
2792 | unsigned NumSrcElts = Src.getValueType().getVectorNumElements(); | ||||||||||
2793 | APInt DemandedSrcElts = DemandedElts.zextOrSelf(NumSrcElts); | ||||||||||
2794 | if (SimplifyDemandedVectorElts(Src, DemandedSrcElts, SrcUndef, SrcZero, TLO, | ||||||||||
2795 | Depth + 1)) | ||||||||||
2796 | return true; | ||||||||||
2797 | KnownZero = SrcZero.zextOrTrunc(NumElts); | ||||||||||
2798 | KnownUndef = SrcUndef.zextOrTrunc(NumElts); | ||||||||||
2799 | |||||||||||
2800 | if (Op.getOpcode() == ISD::ANY_EXTEND_VECTOR_INREG && | ||||||||||
2801 | Op.getValueSizeInBits() == Src.getValueSizeInBits() && | ||||||||||
2802 | DemandedSrcElts == 1 && TLO.DAG.getDataLayout().isLittleEndian()) { | ||||||||||
2803 | // aext - if we just need the bottom element then we can bitcast. | ||||||||||
2804 | return TLO.CombineTo(Op, TLO.DAG.getBitcast(VT, Src)); | ||||||||||
2805 | } | ||||||||||
2806 | |||||||||||
2807 | if (Op.getOpcode() == ISD::ZERO_EXTEND_VECTOR_INREG) { | ||||||||||
2808 | // zext(undef) upper bits are guaranteed to be zero. | ||||||||||
2809 | if (DemandedElts.isSubsetOf(KnownUndef)) | ||||||||||
2810 | return TLO.CombineTo(Op, TLO.DAG.getConstant(0, SDLoc(Op), VT)); | ||||||||||
2811 | KnownUndef.clearAllBits(); | ||||||||||
2812 | } | ||||||||||
2813 | break; | ||||||||||
2814 | } | ||||||||||
2815 | |||||||||||
2816 | // TODO: There are more binop opcodes that could be handled here - MIN, | ||||||||||
2817 | // MAX, saturated math, etc. | ||||||||||
2818 | case ISD::OR: | ||||||||||
2819 | case ISD::XOR: | ||||||||||
2820 | case ISD::ADD: | ||||||||||
2821 | case ISD::SUB: | ||||||||||
2822 | case ISD::FADD: | ||||||||||
2823 | case ISD::FSUB: | ||||||||||
2824 | case ISD::FMUL: | ||||||||||
2825 | case ISD::FDIV: | ||||||||||
2826 | case ISD::FREM: { | ||||||||||
2827 | SDValue Op0 = Op.getOperand(0); | ||||||||||
2828 | SDValue Op1 = Op.getOperand(1); | ||||||||||
2829 | |||||||||||
2830 | APInt UndefRHS, ZeroRHS; | ||||||||||
2831 | if (SimplifyDemandedVectorElts(Op1, DemandedElts, UndefRHS, ZeroRHS, TLO, | ||||||||||
2832 | Depth + 1)) | ||||||||||
2833 | return true; | ||||||||||
2834 | APInt UndefLHS, ZeroLHS; | ||||||||||
2835 | if (SimplifyDemandedVectorElts(Op0, DemandedElts, UndefLHS, ZeroLHS, TLO, | ||||||||||
2836 | Depth + 1)) | ||||||||||
2837 | return true; | ||||||||||
2838 | |||||||||||
2839 | KnownZero = ZeroLHS & ZeroRHS; | ||||||||||
2840 | KnownUndef = getKnownUndefForVectorBinop(Op, TLO.DAG, UndefLHS, UndefRHS); | ||||||||||
2841 | |||||||||||
2842 | // Attempt to avoid multi-use ops if we don't need anything from them. | ||||||||||
2843 | // TODO - use KnownUndef to relax the demandedelts? | ||||||||||
2844 | if (!DemandedElts.isAllOnes()) | ||||||||||
2845 | if (SimplifyDemandedVectorEltsBinOp(Op0, Op1)) | ||||||||||
2846 | return true; | ||||||||||
2847 | break; | ||||||||||
2848 | } | ||||||||||
2849 | case ISD::SHL: | ||||||||||
2850 | case ISD::SRL: | ||||||||||
2851 | case ISD::SRA: | ||||||||||
2852 | case ISD::ROTL: | ||||||||||
2853 | case ISD::ROTR: { | ||||||||||
2854 | SDValue Op0 = Op.getOperand(0); | ||||||||||
2855 | SDValue Op1 = Op.getOperand(1); | ||||||||||
2856 | |||||||||||
2857 | APInt UndefRHS, ZeroRHS; | ||||||||||
2858 | if (SimplifyDemandedVectorElts(Op1, DemandedElts, UndefRHS, ZeroRHS, TLO, | ||||||||||
2859 | Depth + 1)) | ||||||||||
2860 | return true; | ||||||||||
2861 | APInt UndefLHS, ZeroLHS; | ||||||||||
2862 | if (SimplifyDemandedVectorElts(Op0, DemandedElts, UndefLHS, ZeroLHS, TLO, | ||||||||||
2863 | Depth + 1)) | ||||||||||
2864 | return true; | ||||||||||
2865 | |||||||||||
2866 | KnownZero = ZeroLHS; | ||||||||||
2867 | KnownUndef = UndefLHS & UndefRHS; // TODO: use getKnownUndefForVectorBinop? | ||||||||||
2868 | |||||||||||
2869 | // Attempt to avoid multi-use ops if we don't need anything from them. | ||||||||||
2870 | // TODO - use KnownUndef to relax the demandedelts? | ||||||||||
2871 | if (!DemandedElts.isAllOnes()) | ||||||||||
2872 | if (SimplifyDemandedVectorEltsBinOp(Op0, Op1)) | ||||||||||
2873 | return true; | ||||||||||
2874 | break; | ||||||||||
2875 | } | ||||||||||
2876 | case ISD::MUL: | ||||||||||
2877 | case ISD::AND: { | ||||||||||
2878 | SDValue Op0 = Op.getOperand(0); | ||||||||||
2879 | SDValue Op1 = Op.getOperand(1); | ||||||||||
2880 | |||||||||||
2881 | APInt SrcUndef, SrcZero; | ||||||||||
2882 | if (SimplifyDemandedVectorElts(Op1, DemandedElts, SrcUndef, SrcZero, TLO, | ||||||||||
2883 | Depth + 1)) | ||||||||||
2884 | return true; | ||||||||||
2885 | if (SimplifyDemandedVectorElts(Op0, DemandedElts, KnownUndef, KnownZero, | ||||||||||
2886 | TLO, Depth + 1)) | ||||||||||
2887 | return true; | ||||||||||
2888 | |||||||||||
2889 | // If either side has a zero element, then the result element is zero, even | ||||||||||
2890 | // if the other is an UNDEF. | ||||||||||
2891 | // TODO: Extend getKnownUndefForVectorBinop to also deal with known zeros | ||||||||||
2892 | // and then handle 'and' nodes with the rest of the binop opcodes. | ||||||||||
2893 | KnownZero |= SrcZero; | ||||||||||
2894 | KnownUndef &= SrcUndef; | ||||||||||
2895 | KnownUndef &= ~KnownZero; | ||||||||||
2896 | |||||||||||
2897 | // Attempt to avoid multi-use ops if we don't need anything from them. | ||||||||||
2898 | // TODO - use KnownUndef to relax the demandedelts? | ||||||||||
2899 | if (!DemandedElts.isAllOnes()) | ||||||||||
2900 | if (SimplifyDemandedVectorEltsBinOp(Op0, Op1)) | ||||||||||
2901 | return true; | ||||||||||
2902 | break; | ||||||||||
2903 | } | ||||||||||
2904 | case ISD::TRUNCATE: | ||||||||||
2905 | case ISD::SIGN_EXTEND: | ||||||||||
2906 | case ISD::ZERO_EXTEND: | ||||||||||
2907 | if (SimplifyDemandedVectorElts(Op.getOperand(0), DemandedElts, KnownUndef, | ||||||||||
2908 | KnownZero, TLO, Depth + 1)) | ||||||||||
2909 | return true; | ||||||||||
2910 | |||||||||||
2911 | if (Op.getOpcode() == ISD::ZERO_EXTEND) { | ||||||||||
2912 | // zext(undef) upper bits are guaranteed to be zero. | ||||||||||
2913 | if (DemandedElts.isSubsetOf(KnownUndef)) | ||||||||||
2914 | return TLO.CombineTo(Op, TLO.DAG.getConstant(0, SDLoc(Op), VT)); | ||||||||||
2915 | KnownUndef.clearAllBits(); | ||||||||||
2916 | } | ||||||||||
2917 | break; | ||||||||||
2918 | default: { | ||||||||||
2919 | if (Op.getOpcode() >= ISD::BUILTIN_OP_END) { | ||||||||||
2920 | if (SimplifyDemandedVectorEltsForTargetNode(Op, DemandedElts, KnownUndef, | ||||||||||
2921 | KnownZero, TLO, Depth)) | ||||||||||
2922 | return true; | ||||||||||
2923 | } else { | ||||||||||
2924 | KnownBits Known; | ||||||||||
2925 | APInt DemandedBits = APInt::getAllOnes(EltSizeInBits); | ||||||||||
2926 | if (SimplifyDemandedBits(Op, DemandedBits, OriginalDemandedElts, Known, | ||||||||||
2927 | TLO, Depth, AssumeSingleUse)) | ||||||||||
2928 | return true; | ||||||||||
2929 | } | ||||||||||
2930 | break; | ||||||||||
2931 | } | ||||||||||
2932 | } | ||||||||||
2933 | assert((KnownUndef & KnownZero) == 0 && "Elements flagged as undef AND zero")(static_cast <bool> ((KnownUndef & KnownZero) == 0 && "Elements flagged as undef AND zero") ? void (0) : __assert_fail ("(KnownUndef & KnownZero) == 0 && \"Elements flagged as undef AND zero\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 2933, __extension__ __PRETTY_FUNCTION__)); | ||||||||||
2934 | |||||||||||
2935 | // Constant fold all undef cases. | ||||||||||
2936 | // TODO: Handle zero cases as well. | ||||||||||
2937 | if (DemandedElts.isSubsetOf(KnownUndef)) | ||||||||||
2938 | return TLO.CombineTo(Op, TLO.DAG.getUNDEF(VT)); | ||||||||||
2939 | |||||||||||
2940 | return false; | ||||||||||
2941 | } | ||||||||||
2942 | |||||||||||
2943 | /// Determine which of the bits specified in Mask are known to be either zero or | ||||||||||
2944 | /// one and return them in the Known. | ||||||||||
2945 | void TargetLowering::computeKnownBitsForTargetNode(const SDValue Op, | ||||||||||
2946 | KnownBits &Known, | ||||||||||
2947 | const APInt &DemandedElts, | ||||||||||
2948 | const SelectionDAG &DAG, | ||||||||||
2949 | unsigned Depth) const { | ||||||||||
2950 | assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||(static_cast <bool> ((Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode () == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID ) && "Should use MaskedValueIsZero if you don't know whether Op" " is a target node!") ? void (0) : __assert_fail ("(Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && \"Should use MaskedValueIsZero if you don't know whether Op\" \" is a target node!\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 2955, __extension__ __PRETTY_FUNCTION__)) | ||||||||||
2951 | Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||(static_cast <bool> ((Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode () == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID ) && "Should use MaskedValueIsZero if you don't know whether Op" " is a target node!") ? void (0) : __assert_fail ("(Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && \"Should use MaskedValueIsZero if you don't know whether Op\" \" is a target node!\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 2955, __extension__ __PRETTY_FUNCTION__)) | ||||||||||
2952 | Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||(static_cast <bool> ((Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode () == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID ) && "Should use MaskedValueIsZero if you don't know whether Op" " is a target node!") ? void (0) : __assert_fail ("(Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && \"Should use MaskedValueIsZero if you don't know whether Op\" \" is a target node!\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 2955, __extension__ __PRETTY_FUNCTION__)) | ||||||||||
2953 | Op.getOpcode() == ISD::INTRINSIC_VOID) &&(static_cast <bool> ((Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode () == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID ) && "Should use MaskedValueIsZero if you don't know whether Op" " is a target node!") ? void (0) : __assert_fail ("(Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && \"Should use MaskedValueIsZero if you don't know whether Op\" \" is a target node!\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 2955, __extension__ __PRETTY_FUNCTION__)) | ||||||||||
2954 | "Should use MaskedValueIsZero if you don't know whether Op"(static_cast <bool> ((Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode () == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID ) && "Should use MaskedValueIsZero if you don't know whether Op" " is a target node!") ? void (0) : __assert_fail ("(Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && \"Should use MaskedValueIsZero if you don't know whether Op\" \" is a target node!\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 2955, __extension__ __PRETTY_FUNCTION__)) | ||||||||||
2955 | " is a target node!")(static_cast <bool> ((Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode () == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID ) && "Should use MaskedValueIsZero if you don't know whether Op" " is a target node!") ? void (0) : __assert_fail ("(Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && \"Should use MaskedValueIsZero if you don't know whether Op\" \" is a target node!\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 2955, __extension__ __PRETTY_FUNCTION__)); | ||||||||||
2956 | Known.resetAll(); | ||||||||||
2957 | } | ||||||||||
2958 | |||||||||||
2959 | void TargetLowering::computeKnownBitsForTargetInstr( | ||||||||||
2960 | GISelKnownBits &Analysis, Register R, KnownBits &Known, | ||||||||||
2961 | const APInt &DemandedElts, const MachineRegisterInfo &MRI, | ||||||||||
2962 | unsigned Depth) const { | ||||||||||
2963 | Known.resetAll(); | ||||||||||
2964 | } | ||||||||||
2965 | |||||||||||
2966 | void TargetLowering::computeKnownBitsForFrameIndex( | ||||||||||
2967 | const int FrameIdx, KnownBits &Known, const MachineFunction &MF) const { | ||||||||||
2968 | // The low bits are known zero if the pointer is aligned. | ||||||||||
2969 | Known.Zero.setLowBits(Log2(MF.getFrameInfo().getObjectAlign(FrameIdx))); | ||||||||||
2970 | } | ||||||||||
2971 | |||||||||||
2972 | Align TargetLowering::computeKnownAlignForTargetInstr( | ||||||||||
2973 | GISelKnownBits &Analysis, Register R, const MachineRegisterInfo &MRI, | ||||||||||
2974 | unsigned Depth) const { | ||||||||||
2975 | return Align(1); | ||||||||||
2976 | } | ||||||||||
2977 | |||||||||||
2978 | /// This method can be implemented by targets that want to expose additional | ||||||||||
2979 | /// information about sign bits to the DAG Combiner. | ||||||||||
2980 | unsigned TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op, | ||||||||||
2981 | const APInt &, | ||||||||||
2982 | const SelectionDAG &, | ||||||||||
2983 | unsigned Depth) const { | ||||||||||
2984 | assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||(static_cast <bool> ((Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode () == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID ) && "Should use ComputeNumSignBits if you don't know whether Op" " is a target node!") ? void (0) : __assert_fail ("(Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && \"Should use ComputeNumSignBits if you don't know whether Op\" \" is a target node!\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 2989, __extension__ __PRETTY_FUNCTION__)) | ||||||||||
2985 | Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||(static_cast <bool> ((Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode () == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID ) && "Should use ComputeNumSignBits if you don't know whether Op" " is a target node!") ? void (0) : __assert_fail ("(Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && \"Should use ComputeNumSignBits if you don't know whether Op\" \" is a target node!\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 2989, __extension__ __PRETTY_FUNCTION__)) | ||||||||||
2986 | Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||(static_cast <bool> ((Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode () == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID ) && "Should use ComputeNumSignBits if you don't know whether Op" " is a target node!") ? void (0) : __assert_fail ("(Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && \"Should use ComputeNumSignBits if you don't know whether Op\" \" is a target node!\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 2989, __extension__ __PRETTY_FUNCTION__)) | ||||||||||
2987 | Op.getOpcode() == ISD::INTRINSIC_VOID) &&(static_cast <bool> ((Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode () == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID ) && "Should use ComputeNumSignBits if you don't know whether Op" " is a target node!") ? void (0) : __assert_fail ("(Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && \"Should use ComputeNumSignBits if you don't know whether Op\" \" is a target node!\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 2989, __extension__ __PRETTY_FUNCTION__)) | ||||||||||
2988 | "Should use ComputeNumSignBits if you don't know whether Op"(static_cast <bool> ((Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode () == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID ) && "Should use ComputeNumSignBits if you don't know whether Op" " is a target node!") ? void (0) : __assert_fail ("(Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && \"Should use ComputeNumSignBits if you don't know whether Op\" \" is a target node!\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 2989, __extension__ __PRETTY_FUNCTION__)) | ||||||||||
2989 | " is a target node!")(static_cast <bool> ((Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode () == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID ) && "Should use ComputeNumSignBits if you don't know whether Op" " is a target node!") ? void (0) : __assert_fail ("(Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && \"Should use ComputeNumSignBits if you don't know whether Op\" \" is a target node!\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 2989, __extension__ __PRETTY_FUNCTION__)); | ||||||||||
2990 | return 1; | ||||||||||
2991 | } | ||||||||||
2992 | |||||||||||
2993 | unsigned TargetLowering::computeNumSignBitsForTargetInstr( | ||||||||||
2994 | GISelKnownBits &Analysis, Register R, const APInt &DemandedElts, | ||||||||||
2995 | const MachineRegisterInfo &MRI, unsigned Depth) const { | ||||||||||
2996 | return 1; | ||||||||||
2997 | } | ||||||||||
2998 | |||||||||||
2999 | bool TargetLowering::SimplifyDemandedVectorEltsForTargetNode( | ||||||||||
3000 | SDValue Op, const APInt &DemandedElts, APInt &KnownUndef, APInt &KnownZero, | ||||||||||
3001 | TargetLoweringOpt &TLO, unsigned Depth) const { | ||||||||||
3002 | assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||(static_cast <bool> ((Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode () == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID ) && "Should use SimplifyDemandedVectorElts if you don't know whether Op" " is a target node!") ? void (0) : __assert_fail ("(Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && \"Should use SimplifyDemandedVectorElts if you don't know whether Op\" \" is a target node!\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 3007, __extension__ __PRETTY_FUNCTION__)) | ||||||||||
3003 | Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||(static_cast <bool> ((Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode () == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID ) && "Should use SimplifyDemandedVectorElts if you don't know whether Op" " is a target node!") ? void (0) : __assert_fail ("(Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && \"Should use SimplifyDemandedVectorElts if you don't know whether Op\" \" is a target node!\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 3007, __extension__ __PRETTY_FUNCTION__)) | ||||||||||
3004 | Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||(static_cast <bool> ((Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode () == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID ) && "Should use SimplifyDemandedVectorElts if you don't know whether Op" " is a target node!") ? void (0) : __assert_fail ("(Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && \"Should use SimplifyDemandedVectorElts if you don't know whether Op\" \" is a target node!\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 3007, __extension__ __PRETTY_FUNCTION__)) | ||||||||||
3005 | Op.getOpcode() == ISD::INTRINSIC_VOID) &&(static_cast <bool> ((Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode () == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID ) && "Should use SimplifyDemandedVectorElts if you don't know whether Op" " is a target node!") ? void (0) : __assert_fail ("(Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && \"Should use SimplifyDemandedVectorElts if you don't know whether Op\" \" is a target node!\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 3007, __extension__ __PRETTY_FUNCTION__)) | ||||||||||
3006 | "Should use SimplifyDemandedVectorElts if you don't know whether Op"(static_cast <bool> ((Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode () == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID ) && "Should use SimplifyDemandedVectorElts if you don't know whether Op" " is a target node!") ? void (0) : __assert_fail ("(Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && \"Should use SimplifyDemandedVectorElts if you don't know whether Op\" \" is a target node!\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 3007, __extension__ __PRETTY_FUNCTION__)) | ||||||||||
3007 | " is a target node!")(static_cast <bool> ((Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode () == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID ) && "Should use SimplifyDemandedVectorElts if you don't know whether Op" " is a target node!") ? void (0) : __assert_fail ("(Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && \"Should use SimplifyDemandedVectorElts if you don't know whether Op\" \" is a target node!\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 3007, __extension__ __PRETTY_FUNCTION__)); | ||||||||||
3008 | return false; | ||||||||||
3009 | } | ||||||||||
3010 | |||||||||||
3011 | bool TargetLowering::SimplifyDemandedBitsForTargetNode( | ||||||||||
3012 | SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts, | ||||||||||
3013 | KnownBits &Known, TargetLoweringOpt &TLO, unsigned Depth) const { | ||||||||||
3014 | assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||(static_cast <bool> ((Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode () == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID ) && "Should use SimplifyDemandedBits if you don't know whether Op" " is a target node!") ? void (0) : __assert_fail ("(Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && \"Should use SimplifyDemandedBits if you don't know whether Op\" \" is a target node!\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 3019, __extension__ __PRETTY_FUNCTION__)) | ||||||||||
3015 | Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||(static_cast <bool> ((Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode () == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID ) && "Should use SimplifyDemandedBits if you don't know whether Op" " is a target node!") ? void (0) : __assert_fail ("(Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && \"Should use SimplifyDemandedBits if you don't know whether Op\" \" is a target node!\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 3019, __extension__ __PRETTY_FUNCTION__)) | ||||||||||
3016 | Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||(static_cast <bool> ((Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode () == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID ) && "Should use SimplifyDemandedBits if you don't know whether Op" " is a target node!") ? void (0) : __assert_fail ("(Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && \"Should use SimplifyDemandedBits if you don't know whether Op\" \" is a target node!\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 3019, __extension__ __PRETTY_FUNCTION__)) | ||||||||||
3017 | Op.getOpcode() == ISD::INTRINSIC_VOID) &&(static_cast <bool> ((Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode () == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID ) && "Should use SimplifyDemandedBits if you don't know whether Op" " is a target node!") ? void (0) : __assert_fail ("(Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && \"Should use SimplifyDemandedBits if you don't know whether Op\" \" is a target node!\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 3019, __extension__ __PRETTY_FUNCTION__)) | ||||||||||
3018 | "Should use SimplifyDemandedBits if you don't know whether Op"(static_cast <bool> ((Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode () == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID ) && "Should use SimplifyDemandedBits if you don't know whether Op" " is a target node!") ? void (0) : __assert_fail ("(Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && \"Should use SimplifyDemandedBits if you don't know whether Op\" \" is a target node!\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 3019, __extension__ __PRETTY_FUNCTION__)) | ||||||||||
3019 | " is a target node!")(static_cast <bool> ((Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode () == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID ) && "Should use SimplifyDemandedBits if you don't know whether Op" " is a target node!") ? void (0) : __assert_fail ("(Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && \"Should use SimplifyDemandedBits if you don't know whether Op\" \" is a target node!\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 3019, __extension__ __PRETTY_FUNCTION__)); | ||||||||||
3020 | computeKnownBitsForTargetNode(Op, Known, DemandedElts, TLO.DAG, Depth); | ||||||||||
3021 | return false; | ||||||||||
3022 | } | ||||||||||
3023 | |||||||||||
3024 | SDValue TargetLowering::SimplifyMultipleUseDemandedBitsForTargetNode( | ||||||||||
3025 | SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts, | ||||||||||
3026 | SelectionDAG &DAG, unsigned Depth) const { | ||||||||||
3027 | assert((static_cast <bool> ((Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode () == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID ) && "Should use SimplifyMultipleUseDemandedBits if you don't know whether Op" " is a target node!") ? void (0) : __assert_fail ("(Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && \"Should use SimplifyMultipleUseDemandedBits if you don't know whether Op\" \" is a target node!\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 3033, __extension__ __PRETTY_FUNCTION__)) | ||||||||||
3028 | (Op.getOpcode() >= ISD::BUILTIN_OP_END ||(static_cast <bool> ((Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode () == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID ) && "Should use SimplifyMultipleUseDemandedBits if you don't know whether Op" " is a target node!") ? void (0) : __assert_fail ("(Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && \"Should use SimplifyMultipleUseDemandedBits if you don't know whether Op\" \" is a target node!\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 3033, __extension__ __PRETTY_FUNCTION__)) | ||||||||||
3029 | Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||(static_cast <bool> ((Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode () == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID ) && "Should use SimplifyMultipleUseDemandedBits if you don't know whether Op" " is a target node!") ? void (0) : __assert_fail ("(Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && \"Should use SimplifyMultipleUseDemandedBits if you don't know whether Op\" \" is a target node!\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 3033, __extension__ __PRETTY_FUNCTION__)) | ||||||||||
3030 | Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||(static_cast <bool> ((Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode () == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID ) && "Should use SimplifyMultipleUseDemandedBits if you don't know whether Op" " is a target node!") ? void (0) : __assert_fail ("(Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && \"Should use SimplifyMultipleUseDemandedBits if you don't know whether Op\" \" is a target node!\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 3033, __extension__ __PRETTY_FUNCTION__)) | ||||||||||
3031 | Op.getOpcode() == ISD::INTRINSIC_VOID) &&(static_cast <bool> ((Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode () == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID ) && "Should use SimplifyMultipleUseDemandedBits if you don't know whether Op" " is a target node!") ? void (0) : __assert_fail ("(Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && \"Should use SimplifyMultipleUseDemandedBits if you don't know whether Op\" \" is a target node!\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 3033, __extension__ __PRETTY_FUNCTION__)) | ||||||||||
3032 | "Should use SimplifyMultipleUseDemandedBits if you don't know whether Op"(static_cast <bool> ((Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode () == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID ) && "Should use SimplifyMultipleUseDemandedBits if you don't know whether Op" " is a target node!") ? void (0) : __assert_fail ("(Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && \"Should use SimplifyMultipleUseDemandedBits if you don't know whether Op\" \" is a target node!\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 3033, __extension__ __PRETTY_FUNCTION__)) | ||||||||||
3033 | " is a target node!")(static_cast <bool> ((Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode () == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID ) && "Should use SimplifyMultipleUseDemandedBits if you don't know whether Op" " is a target node!") ? void (0) : __assert_fail ("(Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && \"Should use SimplifyMultipleUseDemandedBits if you don't know whether Op\" \" is a target node!\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 3033, __extension__ __PRETTY_FUNCTION__)); | ||||||||||
3034 | return SDValue(); | ||||||||||
3035 | } | ||||||||||
3036 | |||||||||||
3037 | SDValue | ||||||||||
3038 | TargetLowering::buildLegalVectorShuffle(EVT VT, const SDLoc &DL, SDValue N0, | ||||||||||
3039 | SDValue N1, MutableArrayRef<int> Mask, | ||||||||||
3040 | SelectionDAG &DAG) const { | ||||||||||
3041 | bool LegalMask = isShuffleMaskLegal(Mask, VT); | ||||||||||
3042 | if (!LegalMask) { | ||||||||||
3043 | std::swap(N0, N1); | ||||||||||
3044 | ShuffleVectorSDNode::commuteMask(Mask); | ||||||||||
3045 | LegalMask = isShuffleMaskLegal(Mask, VT); | ||||||||||
3046 | } | ||||||||||
3047 | |||||||||||
3048 | if (!LegalMask) | ||||||||||
3049 | return SDValue(); | ||||||||||
3050 | |||||||||||
3051 | return DAG.getVectorShuffle(VT, DL, N0, N1, Mask); | ||||||||||
3052 | } | ||||||||||
3053 | |||||||||||
3054 | const Constant *TargetLowering::getTargetConstantFromLoad(LoadSDNode*) const { | ||||||||||
3055 | return nullptr; | ||||||||||
3056 | } | ||||||||||
3057 | |||||||||||
3058 | bool TargetLowering::isGuaranteedNotToBeUndefOrPoisonForTargetNode( | ||||||||||
3059 | SDValue Op, const APInt &DemandedElts, const SelectionDAG &DAG, | ||||||||||
3060 | bool PoisonOnly, unsigned Depth) const { | ||||||||||
3061 | assert((static_cast <bool> ((Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode () == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID ) && "Should use isGuaranteedNotToBeUndefOrPoison if you don't know whether Op" " is a target node!") ? void (0) : __assert_fail ("(Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && \"Should use isGuaranteedNotToBeUndefOrPoison if you don't know whether Op\" \" is a target node!\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 3067, __extension__ __PRETTY_FUNCTION__)) | ||||||||||
3062 | (Op.getOpcode() >= ISD::BUILTIN_OP_END ||(static_cast <bool> ((Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode () == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID ) && "Should use isGuaranteedNotToBeUndefOrPoison if you don't know whether Op" " is a target node!") ? void (0) : __assert_fail ("(Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && \"Should use isGuaranteedNotToBeUndefOrPoison if you don't know whether Op\" \" is a target node!\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 3067, __extension__ __PRETTY_FUNCTION__)) | ||||||||||
3063 | Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||(static_cast <bool> ((Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode () == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID ) && "Should use isGuaranteedNotToBeUndefOrPoison if you don't know whether Op" " is a target node!") ? void (0) : __assert_fail ("(Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && \"Should use isGuaranteedNotToBeUndefOrPoison if you don't know whether Op\" \" is a target node!\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 3067, __extension__ __PRETTY_FUNCTION__)) | ||||||||||
3064 | Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||(static_cast <bool> ((Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode () == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID ) && "Should use isGuaranteedNotToBeUndefOrPoison if you don't know whether Op" " is a target node!") ? void (0) : __assert_fail ("(Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && \"Should use isGuaranteedNotToBeUndefOrPoison if you don't know whether Op\" \" is a target node!\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 3067, __extension__ __PRETTY_FUNCTION__)) | ||||||||||
3065 | Op.getOpcode() == ISD::INTRINSIC_VOID) &&(static_cast <bool> ((Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode () == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID ) && "Should use isGuaranteedNotToBeUndefOrPoison if you don't know whether Op" " is a target node!") ? void (0) : __assert_fail ("(Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && \"Should use isGuaranteedNotToBeUndefOrPoison if you don't know whether Op\" \" is a target node!\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 3067, __extension__ __PRETTY_FUNCTION__)) | ||||||||||
3066 | "Should use isGuaranteedNotToBeUndefOrPoison if you don't know whether Op"(static_cast <bool> ((Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode () == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID ) && "Should use isGuaranteedNotToBeUndefOrPoison if you don't know whether Op" " is a target node!") ? void (0) : __assert_fail ("(Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && \"Should use isGuaranteedNotToBeUndefOrPoison if you don't know whether Op\" \" is a target node!\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 3067, __extension__ __PRETTY_FUNCTION__)) | ||||||||||
3067 | " is a target node!")(static_cast <bool> ((Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode () == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID ) && "Should use isGuaranteedNotToBeUndefOrPoison if you don't know whether Op" " is a target node!") ? void (0) : __assert_fail ("(Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && \"Should use isGuaranteedNotToBeUndefOrPoison if you don't know whether Op\" \" is a target node!\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 3067, __extension__ __PRETTY_FUNCTION__)); | ||||||||||
3068 | return false; | ||||||||||
3069 | } | ||||||||||
3070 | |||||||||||
3071 | bool TargetLowering::isKnownNeverNaNForTargetNode(SDValue Op, | ||||||||||
3072 | const SelectionDAG &DAG, | ||||||||||
3073 | bool SNaN, | ||||||||||
3074 | unsigned Depth) const { | ||||||||||
3075 | assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||(static_cast <bool> ((Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode () == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID ) && "Should use isKnownNeverNaN if you don't know whether Op" " is a target node!") ? void (0) : __assert_fail ("(Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && \"Should use isKnownNeverNaN if you don't know whether Op\" \" is a target node!\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 3080, __extension__ __PRETTY_FUNCTION__)) | ||||||||||
3076 | Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||(static_cast <bool> ((Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode () == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID ) && "Should use isKnownNeverNaN if you don't know whether Op" " is a target node!") ? void (0) : __assert_fail ("(Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && \"Should use isKnownNeverNaN if you don't know whether Op\" \" is a target node!\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 3080, __extension__ __PRETTY_FUNCTION__)) | ||||||||||
3077 | Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||(static_cast <bool> ((Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode () == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID ) && "Should use isKnownNeverNaN if you don't know whether Op" " is a target node!") ? void (0) : __assert_fail ("(Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && \"Should use isKnownNeverNaN if you don't know whether Op\" \" is a target node!\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 3080, __extension__ __PRETTY_FUNCTION__)) | ||||||||||
3078 | Op.getOpcode() == ISD::INTRINSIC_VOID) &&(static_cast <bool> ((Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode () == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID ) && "Should use isKnownNeverNaN if you don't know whether Op" " is a target node!") ? void (0) : __assert_fail ("(Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && \"Should use isKnownNeverNaN if you don't know whether Op\" \" is a target node!\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 3080, __extension__ __PRETTY_FUNCTION__)) | ||||||||||
3079 | "Should use isKnownNeverNaN if you don't know whether Op"(static_cast <bool> ((Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode () == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID ) && "Should use isKnownNeverNaN if you don't know whether Op" " is a target node!") ? void (0) : __assert_fail ("(Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && \"Should use isKnownNeverNaN if you don't know whether Op\" \" is a target node!\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 3080, __extension__ __PRETTY_FUNCTION__)) | ||||||||||
3080 | " is a target node!")(static_cast <bool> ((Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode () == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID ) && "Should use isKnownNeverNaN if you don't know whether Op" " is a target node!") ? void (0) : __assert_fail ("(Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && \"Should use isKnownNeverNaN if you don't know whether Op\" \" is a target node!\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 3080, __extension__ __PRETTY_FUNCTION__)); | ||||||||||
3081 | return false; | ||||||||||
3082 | } | ||||||||||
3083 | |||||||||||
3084 | // FIXME: Ideally, this would use ISD::isConstantSplatVector(), but that must | ||||||||||
3085 | // work with truncating build vectors and vectors with elements of less than | ||||||||||
3086 | // 8 bits. | ||||||||||
3087 | bool TargetLowering::isConstTrueVal(const SDNode *N) const { | ||||||||||
3088 | if (!N) | ||||||||||
3089 | return false; | ||||||||||
3090 | |||||||||||
3091 | APInt CVal; | ||||||||||
3092 | if (auto *CN = dyn_cast<ConstantSDNode>(N)) { | ||||||||||
3093 | CVal = CN->getAPIntValue(); | ||||||||||
3094 | } else if (auto *BV = dyn_cast<BuildVectorSDNode>(N)) { | ||||||||||
3095 | auto *CN = BV->getConstantSplatNode(); | ||||||||||
3096 | if (!CN) | ||||||||||
3097 | return false; | ||||||||||
3098 | |||||||||||
3099 | // If this is a truncating build vector, truncate the splat value. | ||||||||||
3100 | // Otherwise, we may fail to match the expected values below. | ||||||||||
3101 | unsigned BVEltWidth = BV->getValueType(0).getScalarSizeInBits(); | ||||||||||
3102 | CVal = CN->getAPIntValue(); | ||||||||||
3103 | if (BVEltWidth < CVal.getBitWidth()) | ||||||||||
3104 | CVal = CVal.trunc(BVEltWidth); | ||||||||||
3105 | } else { | ||||||||||
3106 | return false; | ||||||||||
3107 | } | ||||||||||
3108 | |||||||||||
3109 | switch (getBooleanContents(N->getValueType(0))) { | ||||||||||
3110 | case UndefinedBooleanContent: | ||||||||||
3111 | return CVal[0]; | ||||||||||
3112 | case ZeroOrOneBooleanContent: | ||||||||||
3113 | return CVal.isOne(); | ||||||||||
3114 | case ZeroOrNegativeOneBooleanContent: | ||||||||||
3115 | return CVal.isAllOnes(); | ||||||||||
3116 | } | ||||||||||
3117 | |||||||||||
3118 | llvm_unreachable("Invalid boolean contents")::llvm::llvm_unreachable_internal("Invalid boolean contents", "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 3118); | ||||||||||
3119 | } | ||||||||||
3120 | |||||||||||
3121 | bool TargetLowering::isConstFalseVal(const SDNode *N) const { | ||||||||||
3122 | if (!N) | ||||||||||
3123 | return false; | ||||||||||
3124 | |||||||||||
3125 | const ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N); | ||||||||||
3126 | if (!CN) { | ||||||||||
3127 | const BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(N); | ||||||||||
3128 | if (!BV) | ||||||||||
3129 | return false; | ||||||||||
3130 | |||||||||||
3131 | // Only interested in constant splats, we don't care about undef | ||||||||||
3132 | // elements in identifying boolean constants and getConstantSplatNode | ||||||||||
3133 | // returns NULL if all ops are undef; | ||||||||||
3134 | CN = BV->getConstantSplatNode(); | ||||||||||
3135 | if (!CN) | ||||||||||
3136 | return false; | ||||||||||
3137 | } | ||||||||||
3138 | |||||||||||
3139 | if (getBooleanContents(N->getValueType(0)) == UndefinedBooleanContent) | ||||||||||
3140 | return !CN->getAPIntValue()[0]; | ||||||||||
3141 | |||||||||||
3142 | return CN->isZero(); | ||||||||||
3143 | } | ||||||||||
3144 | |||||||||||
3145 | bool TargetLowering::isExtendedTrueVal(const ConstantSDNode *N, EVT VT, | ||||||||||
3146 | bool SExt) const { | ||||||||||
3147 | if (VT == MVT::i1) | ||||||||||
3148 | return N->isOne(); | ||||||||||
3149 | |||||||||||
3150 | TargetLowering::BooleanContent Cnt = getBooleanContents(VT); | ||||||||||
3151 | switch (Cnt) { | ||||||||||
3152 | case TargetLowering::ZeroOrOneBooleanContent: | ||||||||||
3153 | // An extended value of 1 is always true, unless its original type is i1, | ||||||||||
3154 | // in which case it will be sign extended to -1. | ||||||||||
3155 | return (N->isOne() && !SExt) || (SExt && (N->getValueType(0) != MVT::i1)); | ||||||||||
3156 | case TargetLowering::UndefinedBooleanContent: | ||||||||||
3157 | case TargetLowering::ZeroOrNegativeOneBooleanContent: | ||||||||||
3158 | return N->isAllOnes() && SExt; | ||||||||||
3159 | } | ||||||||||
3160 | llvm_unreachable("Unexpected enumeration.")::llvm::llvm_unreachable_internal("Unexpected enumeration.", "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 3160); | ||||||||||
3161 | } | ||||||||||
3162 | |||||||||||
3163 | /// This helper function of SimplifySetCC tries to optimize the comparison when | ||||||||||
3164 | /// either operand of the SetCC node is a bitwise-and instruction. | ||||||||||
3165 | SDValue TargetLowering::foldSetCCWithAnd(EVT VT, SDValue N0, SDValue N1, | ||||||||||
3166 | ISD::CondCode Cond, const SDLoc &DL, | ||||||||||
3167 | DAGCombinerInfo &DCI) const { | ||||||||||
3168 | // Match these patterns in any of their permutations: | ||||||||||
3169 | // (X & Y) == Y | ||||||||||
3170 | // (X & Y) != Y | ||||||||||
3171 | if (N1.getOpcode() == ISD::AND && N0.getOpcode() != ISD::AND) | ||||||||||
3172 | std::swap(N0, N1); | ||||||||||
3173 | |||||||||||
3174 | EVT OpVT = N0.getValueType(); | ||||||||||
3175 | if (N0.getOpcode() != ISD::AND || !OpVT.isInteger() || | ||||||||||
3176 | (Cond != ISD::SETEQ && Cond != ISD::SETNE)) | ||||||||||
3177 | return SDValue(); | ||||||||||
3178 | |||||||||||
3179 | SDValue X, Y; | ||||||||||
3180 | if (N0.getOperand(0) == N1) { | ||||||||||
3181 | X = N0.getOperand(1); | ||||||||||
3182 | Y = N0.getOperand(0); | ||||||||||
3183 | } else if (N0.getOperand(1) == N1) { | ||||||||||
3184 | X = N0.getOperand(0); | ||||||||||
3185 | Y = N0.getOperand(1); | ||||||||||
3186 | } else { | ||||||||||
3187 | return SDValue(); | ||||||||||
3188 | } | ||||||||||
3189 | |||||||||||
3190 | SelectionDAG &DAG = DCI.DAG; | ||||||||||
3191 | SDValue Zero = DAG.getConstant(0, DL, OpVT); | ||||||||||
3192 | if (DAG.isKnownToBeAPowerOfTwo(Y)) { | ||||||||||
3193 | // Simplify X & Y == Y to X & Y != 0 if Y has exactly one bit set. | ||||||||||
3194 | // Note that where Y is variable and is known to have at most one bit set | ||||||||||
3195 | // (for example, if it is Z & 1) we cannot do this; the expressions are not | ||||||||||
3196 | // equivalent when Y == 0. | ||||||||||
3197 | assert(OpVT.isInteger())(static_cast <bool> (OpVT.isInteger()) ? void (0) : __assert_fail ("OpVT.isInteger()", "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 3197, __extension__ __PRETTY_FUNCTION__)); | ||||||||||
3198 | Cond = ISD::getSetCCInverse(Cond, OpVT); | ||||||||||
3199 | if (DCI.isBeforeLegalizeOps() || | ||||||||||
3200 | isCondCodeLegal(Cond, N0.getSimpleValueType())) | ||||||||||
3201 | return DAG.getSetCC(DL, VT, N0, Zero, Cond); | ||||||||||
3202 | } else if (N0.hasOneUse() && hasAndNotCompare(Y)) { | ||||||||||
3203 | // If the target supports an 'and-not' or 'and-complement' logic operation, | ||||||||||
3204 | // try to use that to make a comparison operation more efficient. | ||||||||||
3205 | // But don't do this transform if the mask is a single bit because there are | ||||||||||
3206 | // more efficient ways to deal with that case (for example, 'bt' on x86 or | ||||||||||
3207 | // 'rlwinm' on PPC). | ||||||||||
3208 | |||||||||||
3209 | // Bail out if the compare operand that we want to turn into a zero is | ||||||||||
3210 | // already a zero (otherwise, infinite loop). | ||||||||||
3211 | auto *YConst = dyn_cast<ConstantSDNode>(Y); | ||||||||||
3212 | if (YConst && YConst->isZero()) | ||||||||||
3213 | return SDValue(); | ||||||||||
3214 | |||||||||||
3215 | // Transform this into: ~X & Y == 0. | ||||||||||
3216 | SDValue NotX = DAG.getNOT(SDLoc(X), X, OpVT); | ||||||||||
3217 | SDValue NewAnd = DAG.getNode(ISD::AND, SDLoc(N0), OpVT, NotX, Y); | ||||||||||
3218 | return DAG.getSetCC(DL, VT, NewAnd, Zero, Cond); | ||||||||||
3219 | } | ||||||||||
3220 | |||||||||||
3221 | return SDValue(); | ||||||||||
3222 | } | ||||||||||
3223 | |||||||||||
3224 | /// There are multiple IR patterns that could be checking whether certain | ||||||||||
3225 | /// truncation of a signed number would be lossy or not. The pattern which is | ||||||||||
3226 | /// best at IR level, may not lower optimally. Thus, we want to unfold it. | ||||||||||
3227 | /// We are looking for the following pattern: (KeptBits is a constant) | ||||||||||
3228 | /// (add %x, (1 << (KeptBits-1))) srccond (1 << KeptBits) | ||||||||||
3229 | /// KeptBits won't be bitwidth(x), that will be constant-folded to true/false. | ||||||||||
3230 | /// KeptBits also can't be 1, that would have been folded to %x dstcond 0 | ||||||||||
3231 | /// We will unfold it into the natural trunc+sext pattern: | ||||||||||
3232 | /// ((%x << C) a>> C) dstcond %x | ||||||||||
3233 | /// Where C = bitwidth(x) - KeptBits and C u< bitwidth(x) | ||||||||||
3234 | SDValue TargetLowering::optimizeSetCCOfSignedTruncationCheck( | ||||||||||
3235 | EVT SCCVT, SDValue N0, SDValue N1, ISD::CondCode Cond, DAGCombinerInfo &DCI, | ||||||||||
3236 | const SDLoc &DL) const { | ||||||||||
3237 | // We must be comparing with a constant. | ||||||||||
3238 | ConstantSDNode *C1; | ||||||||||
3239 | if (!(C1 = dyn_cast<ConstantSDNode>(N1))) | ||||||||||
3240 | return SDValue(); | ||||||||||
3241 | |||||||||||
3242 | // N0 should be: add %x, (1 << (KeptBits-1)) | ||||||||||
3243 | if (N0->getOpcode() != ISD::ADD) | ||||||||||
3244 | return SDValue(); | ||||||||||
3245 | |||||||||||
3246 | // And we must be 'add'ing a constant. | ||||||||||
3247 | ConstantSDNode *C01; | ||||||||||
3248 | if (!(C01 = dyn_cast<ConstantSDNode>(N0->getOperand(1)))) | ||||||||||
3249 | return SDValue(); | ||||||||||
3250 | |||||||||||
3251 | SDValue X = N0->getOperand(0); | ||||||||||
3252 | EVT XVT = X.getValueType(); | ||||||||||
3253 | |||||||||||
3254 | // Validate constants ... | ||||||||||
3255 | |||||||||||
3256 | APInt I1 = C1->getAPIntValue(); | ||||||||||
3257 | |||||||||||
3258 | ISD::CondCode NewCond; | ||||||||||
3259 | if (Cond == ISD::CondCode::SETULT) { | ||||||||||
3260 | NewCond = ISD::CondCode::SETEQ; | ||||||||||
3261 | } else if (Cond == ISD::CondCode::SETULE) { | ||||||||||
3262 | NewCond = ISD::CondCode::SETEQ; | ||||||||||
3263 | // But need to 'canonicalize' the constant. | ||||||||||
3264 | I1 += 1; | ||||||||||
3265 | } else if (Cond == ISD::CondCode::SETUGT) { | ||||||||||
3266 | NewCond = ISD::CondCode::SETNE; | ||||||||||
3267 | // But need to 'canonicalize' the constant. | ||||||||||
3268 | I1 += 1; | ||||||||||
3269 | } else if (Cond == ISD::CondCode::SETUGE) { | ||||||||||
3270 | NewCond = ISD::CondCode::SETNE; | ||||||||||
3271 | } else | ||||||||||
3272 | return SDValue(); | ||||||||||
3273 | |||||||||||
3274 | APInt I01 = C01->getAPIntValue(); | ||||||||||
3275 | |||||||||||
3276 | auto checkConstants = [&I1, &I01]() -> bool { | ||||||||||
3277 | // Both of them must be power-of-two, and the constant from setcc is bigger. | ||||||||||
3278 | return I1.ugt(I01) && I1.isPowerOf2() && I01.isPowerOf2(); | ||||||||||
3279 | }; | ||||||||||
3280 | |||||||||||
3281 | if (checkConstants()) { | ||||||||||
3282 | // Great, e.g. got icmp ult i16 (add i16 %x, 128), 256 | ||||||||||
3283 | } else { | ||||||||||
3284 | // What if we invert constants? (and the target predicate) | ||||||||||
3285 | I1.negate(); | ||||||||||
3286 | I01.negate(); | ||||||||||
3287 | assert(XVT.isInteger())(static_cast <bool> (XVT.isInteger()) ? void (0) : __assert_fail ("XVT.isInteger()", "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 3287, __extension__ __PRETTY_FUNCTION__)); | ||||||||||
3288 | NewCond = getSetCCInverse(NewCond, XVT); | ||||||||||
3289 | if (!checkConstants()) | ||||||||||
3290 | return SDValue(); | ||||||||||
3291 | // Great, e.g. got icmp uge i16 (add i16 %x, -128), -256 | ||||||||||
3292 | } | ||||||||||
3293 | |||||||||||
3294 | // They are power-of-two, so which bit is set? | ||||||||||
3295 | const unsigned KeptBits = I1.logBase2(); | ||||||||||
3296 | const unsigned KeptBitsMinusOne = I01.logBase2(); | ||||||||||
3297 | |||||||||||
3298 | // Magic! | ||||||||||
3299 | if (KeptBits != (KeptBitsMinusOne + 1)) | ||||||||||
3300 | return SDValue(); | ||||||||||
3301 | assert(KeptBits > 0 && KeptBits < XVT.getSizeInBits() && "unreachable")(static_cast <bool> (KeptBits > 0 && KeptBits < XVT.getSizeInBits() && "unreachable") ? void (0 ) : __assert_fail ("KeptBits > 0 && KeptBits < XVT.getSizeInBits() && \"unreachable\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 3301, __extension__ __PRETTY_FUNCTION__)); | ||||||||||
3302 | |||||||||||
3303 | // We don't want to do this in every single case. | ||||||||||
3304 | SelectionDAG &DAG = DCI.DAG; | ||||||||||
3305 | if (!DAG.getTargetLoweringInfo().shouldTransformSignedTruncationCheck( | ||||||||||
3306 | XVT, KeptBits)) | ||||||||||
3307 | return SDValue(); | ||||||||||
3308 | |||||||||||
3309 | const unsigned MaskedBits = XVT.getSizeInBits() - KeptBits; | ||||||||||
3310 | assert(MaskedBits > 0 && MaskedBits < XVT.getSizeInBits() && "unreachable")(static_cast <bool> (MaskedBits > 0 && MaskedBits < XVT.getSizeInBits() && "unreachable") ? void (0 ) : __assert_fail ("MaskedBits > 0 && MaskedBits < XVT.getSizeInBits() && \"unreachable\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 3310, __extension__ __PRETTY_FUNCTION__)); | ||||||||||
3311 | |||||||||||
3312 | // Unfold into: ((%x << C) a>> C) cond %x | ||||||||||
3313 | // Where 'cond' will be either 'eq' or 'ne'. | ||||||||||
3314 | SDValue ShiftAmt = DAG.getConstant(MaskedBits, DL, XVT); | ||||||||||
3315 | SDValue T0 = DAG.getNode(ISD::SHL, DL, XVT, X, ShiftAmt); | ||||||||||
3316 | SDValue T1 = DAG.getNode(ISD::SRA, DL, XVT, T0, ShiftAmt); | ||||||||||
3317 | SDValue T2 = DAG.getSetCC(DL, SCCVT, T1, X, NewCond); | ||||||||||
3318 | |||||||||||
3319 | return T2; | ||||||||||
3320 | } | ||||||||||
3321 | |||||||||||
3322 | // (X & (C l>>/<< Y)) ==/!= 0 --> ((X <</l>> Y) & C) ==/!= 0 | ||||||||||
3323 | SDValue TargetLowering::optimizeSetCCByHoistingAndByConstFromLogicalShift( | ||||||||||
3324 | EVT SCCVT, SDValue N0, SDValue N1C, ISD::CondCode Cond, | ||||||||||
3325 | DAGCombinerInfo &DCI, const SDLoc &DL) const { | ||||||||||
3326 | assert(isConstOrConstSplat(N1C) &&(static_cast <bool> (isConstOrConstSplat(N1C) && isConstOrConstSplat(N1C)->getAPIntValue().isZero() && "Should be a comparison with 0.") ? void (0) : __assert_fail ("isConstOrConstSplat(N1C) && isConstOrConstSplat(N1C)->getAPIntValue().isZero() && \"Should be a comparison with 0.\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 3328, __extension__ __PRETTY_FUNCTION__)) | ||||||||||
3327 | isConstOrConstSplat(N1C)->getAPIntValue().isZero() &&(static_cast <bool> (isConstOrConstSplat(N1C) && isConstOrConstSplat(N1C)->getAPIntValue().isZero() && "Should be a comparison with 0.") ? void (0) : __assert_fail ("isConstOrConstSplat(N1C) && isConstOrConstSplat(N1C)->getAPIntValue().isZero() && \"Should be a comparison with 0.\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 3328, __extension__ __PRETTY_FUNCTION__)) | ||||||||||
3328 | "Should be a comparison with 0.")(static_cast <bool> (isConstOrConstSplat(N1C) && isConstOrConstSplat(N1C)->getAPIntValue().isZero() && "Should be a comparison with 0.") ? void (0) : __assert_fail ("isConstOrConstSplat(N1C) && isConstOrConstSplat(N1C)->getAPIntValue().isZero() && \"Should be a comparison with 0.\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 3328, __extension__ __PRETTY_FUNCTION__)); | ||||||||||
3329 | assert((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&(static_cast <bool> ((Cond == ISD::SETEQ || Cond == ISD ::SETNE) && "Valid only for [in]equality comparisons." ) ? void (0) : __assert_fail ("(Cond == ISD::SETEQ || Cond == ISD::SETNE) && \"Valid only for [in]equality comparisons.\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 3330, __extension__ __PRETTY_FUNCTION__)) | ||||||||||
3330 | "Valid only for [in]equality comparisons.")(static_cast <bool> ((Cond == ISD::SETEQ || Cond == ISD ::SETNE) && "Valid only for [in]equality comparisons." ) ? void (0) : __assert_fail ("(Cond == ISD::SETEQ || Cond == ISD::SETNE) && \"Valid only for [in]equality comparisons.\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 3330, __extension__ __PRETTY_FUNCTION__)); | ||||||||||
3331 | |||||||||||
3332 | unsigned NewShiftOpcode; | ||||||||||
3333 | SDValue X, C, Y; | ||||||||||
3334 | |||||||||||
3335 | SelectionDAG &DAG = DCI.DAG; | ||||||||||
3336 | const TargetLowering &TLI = DAG.getTargetLoweringInfo(); | ||||||||||
3337 | |||||||||||
3338 | // Look for '(C l>>/<< Y)'. | ||||||||||
3339 | auto Match = [&NewShiftOpcode, &X, &C, &Y, &TLI, &DAG](SDValue V) { | ||||||||||
3340 | // The shift should be one-use. | ||||||||||
3341 | if (!V.hasOneUse()) | ||||||||||
3342 | return false; | ||||||||||
3343 | unsigned OldShiftOpcode = V.getOpcode(); | ||||||||||
3344 | switch (OldShiftOpcode) { | ||||||||||
3345 | case ISD::SHL: | ||||||||||
3346 | NewShiftOpcode = ISD::SRL; | ||||||||||
3347 | break; | ||||||||||
3348 | case ISD::SRL: | ||||||||||
3349 | NewShiftOpcode = ISD::SHL; | ||||||||||
3350 | break; | ||||||||||
3351 | default: | ||||||||||
3352 | return false; // must be a logical shift. | ||||||||||
3353 | } | ||||||||||
3354 | // We should be shifting a constant. | ||||||||||
3355 | // FIXME: best to use isConstantOrConstantVector(). | ||||||||||
3356 | C = V.getOperand(0); | ||||||||||
3357 | ConstantSDNode *CC = | ||||||||||
3358 | isConstOrConstSplat(C, /*AllowUndefs=*/true, /*AllowTruncation=*/true); | ||||||||||
3359 | if (!CC) | ||||||||||
3360 | return false; | ||||||||||
3361 | Y = V.getOperand(1); | ||||||||||
3362 | |||||||||||
3363 | ConstantSDNode *XC = | ||||||||||
3364 | isConstOrConstSplat(X, /*AllowUndefs=*/true, /*AllowTruncation=*/true); | ||||||||||
3365 | return TLI.shouldProduceAndByConstByHoistingConstFromShiftsLHSOfAnd( | ||||||||||
3366 | X, XC, CC, Y, OldShiftOpcode, NewShiftOpcode, DAG); | ||||||||||
3367 | }; | ||||||||||
3368 | |||||||||||
3369 | // LHS of comparison should be an one-use 'and'. | ||||||||||
3370 | if (N0.getOpcode() != ISD::AND || !N0.hasOneUse()) | ||||||||||
3371 | return SDValue(); | ||||||||||
3372 | |||||||||||
3373 | X = N0.getOperand(0); | ||||||||||
3374 | SDValue Mask = N0.getOperand(1); | ||||||||||
3375 | |||||||||||
3376 | // 'and' is commutative! | ||||||||||
3377 | if (!Match(Mask)) { | ||||||||||
3378 | std::swap(X, Mask); | ||||||||||
3379 | if (!Match(Mask)) | ||||||||||
3380 | return SDValue(); | ||||||||||
3381 | } | ||||||||||
3382 | |||||||||||
3383 | EVT VT = X.getValueType(); | ||||||||||
3384 | |||||||||||
3385 | // Produce: | ||||||||||
3386 | // ((X 'OppositeShiftOpcode' Y) & C) Cond 0 | ||||||||||
3387 | SDValue T0 = DAG.getNode(NewShiftOpcode, DL, VT, X, Y); | ||||||||||
3388 | SDValue T1 = DAG.getNode(ISD::AND, DL, VT, T0, C); | ||||||||||
3389 | SDValue T2 = DAG.getSetCC(DL, SCCVT, T1, N1C, Cond); | ||||||||||
3390 | return T2; | ||||||||||
3391 | } | ||||||||||
3392 | |||||||||||
3393 | /// Try to fold an equality comparison with a {add/sub/xor} binary operation as | ||||||||||
3394 | /// the 1st operand (N0). Callers are expected to swap the N0/N1 parameters to | ||||||||||
3395 | /// handle the commuted versions of these patterns. | ||||||||||
3396 | SDValue TargetLowering::foldSetCCWithBinOp(EVT VT, SDValue N0, SDValue N1, | ||||||||||
3397 | ISD::CondCode Cond, const SDLoc &DL, | ||||||||||
3398 | DAGCombinerInfo &DCI) const { | ||||||||||
3399 | unsigned BOpcode = N0.getOpcode(); | ||||||||||
3400 | assert((BOpcode == ISD::ADD || BOpcode == ISD::SUB || BOpcode == ISD::XOR) &&(static_cast <bool> ((BOpcode == ISD::ADD || BOpcode == ISD::SUB || BOpcode == ISD::XOR) && "Unexpected binop" ) ? void (0) : __assert_fail ("(BOpcode == ISD::ADD || BOpcode == ISD::SUB || BOpcode == ISD::XOR) && \"Unexpected binop\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 3401, __extension__ __PRETTY_FUNCTION__)) | ||||||||||
3401 | "Unexpected binop")(static_cast <bool> ((BOpcode == ISD::ADD || BOpcode == ISD::SUB || BOpcode == ISD::XOR) && "Unexpected binop" ) ? void (0) : __assert_fail ("(BOpcode == ISD::ADD || BOpcode == ISD::SUB || BOpcode == ISD::XOR) && \"Unexpected binop\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 3401, __extension__ __PRETTY_FUNCTION__)); | ||||||||||
3402 | assert((Cond == ISD::SETEQ || Cond == ISD::SETNE) && "Unexpected condcode")(static_cast <bool> ((Cond == ISD::SETEQ || Cond == ISD ::SETNE) && "Unexpected condcode") ? void (0) : __assert_fail ("(Cond == ISD::SETEQ || Cond == ISD::SETNE) && \"Unexpected condcode\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 3402, __extension__ __PRETTY_FUNCTION__)); | ||||||||||
3403 | |||||||||||
3404 | // (X + Y) == X --> Y == 0 | ||||||||||
3405 | // (X - Y) == X --> Y == 0 | ||||||||||
3406 | // (X ^ Y) == X --> Y == 0 | ||||||||||
3407 | SelectionDAG &DAG = DCI.DAG; | ||||||||||
3408 | EVT OpVT = N0.getValueType(); | ||||||||||
3409 | SDValue X = N0.getOperand(0); | ||||||||||
3410 | SDValue Y = N0.getOperand(1); | ||||||||||
3411 | if (X == N1) | ||||||||||
3412 | return DAG.getSetCC(DL, VT, Y, DAG.getConstant(0, DL, OpVT), Cond); | ||||||||||
3413 | |||||||||||
3414 | if (Y != N1) | ||||||||||
3415 | return SDValue(); | ||||||||||
3416 | |||||||||||
3417 | // (X + Y) == Y --> X == 0 | ||||||||||
3418 | // (X ^ Y) == Y --> X == 0 | ||||||||||
3419 | if (BOpcode == ISD::ADD || BOpcode == ISD::XOR) | ||||||||||
3420 | return DAG.getSetCC(DL, VT, X, DAG.getConstant(0, DL, OpVT), Cond); | ||||||||||
3421 | |||||||||||
3422 | // The shift would not be valid if the operands are boolean (i1). | ||||||||||
3423 | if (!N0.hasOneUse() || OpVT.getScalarSizeInBits() == 1) | ||||||||||
3424 | return SDValue(); | ||||||||||
3425 | |||||||||||
3426 | // (X - Y) == Y --> X == Y << 1 | ||||||||||
3427 | EVT ShiftVT = getShiftAmountTy(OpVT, DAG.getDataLayout(), | ||||||||||
3428 | !DCI.isBeforeLegalize()); | ||||||||||
3429 | SDValue One = DAG.getConstant(1, DL, ShiftVT); | ||||||||||
3430 | SDValue YShl1 = DAG.getNode(ISD::SHL, DL, N1.getValueType(), Y, One); | ||||||||||
3431 | if (!DCI.isCalledByLegalizer()) | ||||||||||
3432 | DCI.AddToWorklist(YShl1.getNode()); | ||||||||||
3433 | return DAG.getSetCC(DL, VT, X, YShl1, Cond); | ||||||||||
3434 | } | ||||||||||
3435 | |||||||||||
3436 | static SDValue simplifySetCCWithCTPOP(const TargetLowering &TLI, EVT VT, | ||||||||||
3437 | SDValue N0, const APInt &C1, | ||||||||||
3438 | ISD::CondCode Cond, const SDLoc &dl, | ||||||||||
3439 | SelectionDAG &DAG) { | ||||||||||
3440 | // Look through truncs that don't change the value of a ctpop. | ||||||||||
3441 | // FIXME: Add vector support? Need to be careful with setcc result type below. | ||||||||||
3442 | SDValue CTPOP = N0; | ||||||||||
3443 | if (N0.getOpcode() == ISD::TRUNCATE && N0.hasOneUse() && !VT.isVector() && | ||||||||||
3444 | N0.getScalarValueSizeInBits() > Log2_32(N0.getOperand(0).getScalarValueSizeInBits())) | ||||||||||
3445 | CTPOP = N0.getOperand(0); | ||||||||||
3446 | |||||||||||
3447 | if (CTPOP.getOpcode() != ISD::CTPOP || !CTPOP.hasOneUse()) | ||||||||||
3448 | return SDValue(); | ||||||||||
3449 | |||||||||||
3450 | EVT CTVT = CTPOP.getValueType(); | ||||||||||
3451 | SDValue CTOp = CTPOP.getOperand(0); | ||||||||||
3452 | |||||||||||
3453 | // If this is a vector CTPOP, keep the CTPOP if it is legal. | ||||||||||
3454 | // TODO: Should we check if CTPOP is legal(or custom) for scalars? | ||||||||||
3455 | if (VT.isVector() && TLI.isOperationLegal(ISD::CTPOP, CTVT)) | ||||||||||
3456 | return SDValue(); | ||||||||||
3457 | |||||||||||
3458 | // (ctpop x) u< 2 -> (x & x-1) == 0 | ||||||||||
3459 | // (ctpop x) u> 1 -> (x & x-1) != 0 | ||||||||||
3460 | if (Cond == ISD::SETULT || Cond == ISD::SETUGT) { | ||||||||||
3461 | unsigned CostLimit = TLI.getCustomCtpopCost(CTVT, Cond); | ||||||||||
3462 | if (C1.ugt(CostLimit + (Cond == ISD::SETULT))) | ||||||||||
3463 | return SDValue(); | ||||||||||
3464 | if (C1 == 0 && (Cond == ISD::SETULT)) | ||||||||||
3465 | return SDValue(); // This is handled elsewhere. | ||||||||||
3466 | |||||||||||
3467 | unsigned Passes = C1.getLimitedValue() - (Cond == ISD::SETULT); | ||||||||||
3468 | |||||||||||
3469 | SDValue NegOne = DAG.getAllOnesConstant(dl, CTVT); | ||||||||||
3470 | SDValue Result = CTOp; | ||||||||||
3471 | for (unsigned i = 0; i < Passes; i++) { | ||||||||||
3472 | SDValue Add = DAG.getNode(ISD::ADD, dl, CTVT, Result, NegOne); | ||||||||||
3473 | Result = DAG.getNode(ISD::AND, dl, CTVT, Result, Add); | ||||||||||
3474 | } | ||||||||||
3475 | ISD::CondCode CC = Cond == ISD::SETULT ? ISD::SETEQ : ISD::SETNE; | ||||||||||
3476 | return DAG.getSetCC(dl, VT, Result, DAG.getConstant(0, dl, CTVT), CC); | ||||||||||
3477 | } | ||||||||||
3478 | |||||||||||
3479 | // If ctpop is not supported, expand a power-of-2 comparison based on it. | ||||||||||
3480 | if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && C1 == 1) { | ||||||||||
3481 | // For scalars, keep CTPOP if it is legal or custom. | ||||||||||
3482 | if (!VT.isVector() && TLI.isOperationLegalOrCustom(ISD::CTPOP, CTVT)) | ||||||||||
3483 | return SDValue(); | ||||||||||
3484 | // This is based on X86's custom lowering for CTPOP which produces more | ||||||||||
3485 | // instructions than the expansion here. | ||||||||||
3486 | |||||||||||
3487 | // (ctpop x) == 1 --> (x != 0) && ((x & x-1) == 0) | ||||||||||
3488 | // (ctpop x) != 1 --> (x == 0) || ((x & x-1) != 0) | ||||||||||
3489 | SDValue Zero = DAG.getConstant(0, dl, CTVT); | ||||||||||
3490 | SDValue NegOne = DAG.getAllOnesConstant(dl, CTVT); | ||||||||||
3491 | assert(CTVT.isInteger())(static_cast <bool> (CTVT.isInteger()) ? void (0) : __assert_fail ("CTVT.isInteger()", "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 3491, __extension__ __PRETTY_FUNCTION__)); | ||||||||||
3492 | ISD::CondCode InvCond = ISD::getSetCCInverse(Cond, CTVT); | ||||||||||
3493 | SDValue Add = DAG.getNode(ISD::ADD, dl, CTVT, CTOp, NegOne); | ||||||||||
3494 | SDValue And = DAG.getNode(ISD::AND, dl, CTVT, CTOp, Add); | ||||||||||
3495 | SDValue LHS = DAG.getSetCC(dl, VT, CTOp, Zero, InvCond); | ||||||||||
3496 | SDValue RHS = DAG.getSetCC(dl, VT, And, Zero, Cond); | ||||||||||
3497 | unsigned LogicOpcode = Cond == ISD::SETEQ ? ISD::AND : ISD::OR; | ||||||||||
3498 | return DAG.getNode(LogicOpcode, dl, VT, LHS, RHS); | ||||||||||
3499 | } | ||||||||||
3500 | |||||||||||
3501 | return SDValue(); | ||||||||||
3502 | } | ||||||||||
3503 | |||||||||||
3504 | /// Try to simplify a setcc built with the specified operands and cc. If it is | ||||||||||
3505 | /// unable to simplify it, return a null SDValue. | ||||||||||
3506 | SDValue TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1, | ||||||||||
3507 | ISD::CondCode Cond, bool foldBooleans, | ||||||||||
3508 | DAGCombinerInfo &DCI, | ||||||||||
3509 | const SDLoc &dl) const { | ||||||||||
3510 | SelectionDAG &DAG = DCI.DAG; | ||||||||||
3511 | const DataLayout &Layout = DAG.getDataLayout(); | ||||||||||
3512 | EVT OpVT = N0.getValueType(); | ||||||||||
3513 | |||||||||||
3514 | // Constant fold or commute setcc. | ||||||||||
3515 | if (SDValue Fold = DAG.FoldSetCC(VT, N0, N1, Cond, dl)) | ||||||||||
3516 | return Fold; | ||||||||||
3517 | |||||||||||
3518 | // Ensure that the constant occurs on the RHS and fold constant comparisons. | ||||||||||
3519 | // TODO: Handle non-splat vector constants. All undef causes trouble. | ||||||||||
3520 | // FIXME: We can't yet fold constant scalable vector splats, so avoid an | ||||||||||
3521 | // infinite loop here when we encounter one. | ||||||||||
3522 | ISD::CondCode SwappedCC = ISD::getSetCCSwappedOperands(Cond); | ||||||||||
3523 | if (isConstOrConstSplat(N0) && | ||||||||||
3524 | (!OpVT.isScalableVector() || !isConstOrConstSplat(N1)) && | ||||||||||
3525 | (DCI.isBeforeLegalizeOps() || | ||||||||||
3526 | isCondCodeLegal(SwappedCC, N0.getSimpleValueType()))) | ||||||||||
3527 | return DAG.getSetCC(dl, VT, N1, N0, SwappedCC); | ||||||||||
3528 | |||||||||||
3529 | // If we have a subtract with the same 2 non-constant operands as this setcc | ||||||||||
3530 | // -- but in reverse order -- then try to commute the operands of this setcc | ||||||||||
3531 | // to match. A matching pair of setcc (cmp) and sub may be combined into 1 | ||||||||||
3532 | // instruction on some targets. | ||||||||||
3533 | if (!isConstOrConstSplat(N0) && !isConstOrConstSplat(N1) && | ||||||||||
3534 | (DCI.isBeforeLegalizeOps() || | ||||||||||
3535 | isCondCodeLegal(SwappedCC, N0.getSimpleValueType())) && | ||||||||||
3536 | DAG.doesNodeExist(ISD::SUB, DAG.getVTList(OpVT), {N1, N0}) && | ||||||||||
3537 | !DAG.doesNodeExist(ISD::SUB, DAG.getVTList(OpVT), {N0, N1})) | ||||||||||
3538 | return DAG.getSetCC(dl, VT, N1, N0, SwappedCC); | ||||||||||
3539 | |||||||||||
3540 | if (auto *N1C = isConstOrConstSplat(N1)) { | ||||||||||
3541 | const APInt &C1 = N1C->getAPIntValue(); | ||||||||||
3542 | |||||||||||
3543 | // Optimize some CTPOP cases. | ||||||||||
3544 | if (SDValue V = simplifySetCCWithCTPOP(*this, VT, N0, C1, Cond, dl, DAG)) | ||||||||||
3545 | return V; | ||||||||||
3546 | |||||||||||
3547 | // If the LHS is '(srl (ctlz x), 5)', the RHS is 0/1, and this is an | ||||||||||
3548 | // equality comparison, then we're just comparing whether X itself is | ||||||||||
3549 | // zero. | ||||||||||
3550 | if (N0.getOpcode() == ISD::SRL && (C1.isZero() || C1.isOne()) && | ||||||||||
3551 | N0.getOperand(0).getOpcode() == ISD::CTLZ && | ||||||||||
3552 | isPowerOf2_32(N0.getScalarValueSizeInBits())) { | ||||||||||
3553 | if (ConstantSDNode *ShAmt = isConstOrConstSplat(N0.getOperand(1))) { | ||||||||||
3554 | if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && | ||||||||||
3555 | ShAmt->getAPIntValue() == Log2_32(N0.getScalarValueSizeInBits())) { | ||||||||||
3556 | if ((C1 == 0) == (Cond == ISD::SETEQ)) { | ||||||||||
3557 | // (srl (ctlz x), 5) == 0 -> X != 0 | ||||||||||
3558 | // (srl (ctlz x), 5) != 1 -> X != 0 | ||||||||||
3559 | Cond = ISD::SETNE; | ||||||||||
3560 | } else { | ||||||||||
3561 | // (srl (ctlz x), 5) != 0 -> X == 0 | ||||||||||
3562 | // (srl (ctlz x), 5) == 1 -> X == 0 | ||||||||||
3563 | Cond = ISD::SETEQ; | ||||||||||
3564 | } | ||||||||||
3565 | SDValue Zero = DAG.getConstant(0, dl, N0.getValueType()); | ||||||||||
3566 | return DAG.getSetCC(dl, VT, N0.getOperand(0).getOperand(0), Zero, | ||||||||||
3567 | Cond); | ||||||||||
3568 | } | ||||||||||
3569 | } | ||||||||||
3570 | } | ||||||||||
3571 | } | ||||||||||
3572 | |||||||||||
3573 | // FIXME: Support vectors. | ||||||||||
3574 | if (auto *N1C = dyn_cast<ConstantSDNode>(N1.getNode())) { | ||||||||||
3575 | const APInt &C1 = N1C->getAPIntValue(); | ||||||||||
3576 | |||||||||||
3577 | // (zext x) == C --> x == (trunc C) | ||||||||||
3578 | // (sext x) == C --> x == (trunc C) | ||||||||||
3579 | if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && | ||||||||||
3580 | DCI.isBeforeLegalize() && N0->hasOneUse()) { | ||||||||||
3581 | unsigned MinBits = N0.getValueSizeInBits(); | ||||||||||
3582 | SDValue PreExt; | ||||||||||
3583 | bool Signed = false; | ||||||||||
3584 | if (N0->getOpcode() == ISD::ZERO_EXTEND) { | ||||||||||
3585 | // ZExt | ||||||||||
3586 | MinBits = N0->getOperand(0).getValueSizeInBits(); | ||||||||||
3587 | PreExt = N0->getOperand(0); | ||||||||||
3588 | } else if (N0->getOpcode() == ISD::AND) { | ||||||||||
3589 | // DAGCombine turns costly ZExts into ANDs | ||||||||||
3590 | if (auto *C = dyn_cast<ConstantSDNode>(N0->getOperand(1))) | ||||||||||
3591 | if ((C->getAPIntValue()+1).isPowerOf2()) { | ||||||||||
3592 | MinBits = C->getAPIntValue().countTrailingOnes(); | ||||||||||
3593 | PreExt = N0->getOperand(0); | ||||||||||
3594 | } | ||||||||||
3595 | } else if (N0->getOpcode() == ISD::SIGN_EXTEND) { | ||||||||||
3596 | // SExt | ||||||||||
3597 | MinBits = N0->getOperand(0).getValueSizeInBits(); | ||||||||||
3598 | PreExt = N0->getOperand(0); | ||||||||||
3599 | Signed = true; | ||||||||||
3600 | } else if (auto *LN0 = dyn_cast<LoadSDNode>(N0)) { | ||||||||||
3601 | // ZEXTLOAD / SEXTLOAD | ||||||||||
3602 | if (LN0->getExtensionType() == ISD::ZEXTLOAD) { | ||||||||||
3603 | MinBits = LN0->getMemoryVT().getSizeInBits(); | ||||||||||
3604 | PreExt = N0; | ||||||||||
3605 | } else if (LN0->getExtensionType() == ISD::SEXTLOAD) { | ||||||||||
3606 | Signed = true; | ||||||||||
3607 | MinBits = LN0->getMemoryVT().getSizeInBits(); | ||||||||||
3608 | PreExt = N0; | ||||||||||
3609 | } | ||||||||||
3610 | } | ||||||||||
3611 | |||||||||||
3612 | // Figure out how many bits we need to preserve this constant. | ||||||||||
3613 | unsigned ReqdBits = Signed ? | ||||||||||
3614 | C1.getBitWidth() - C1.getNumSignBits() + 1 : | ||||||||||
3615 | C1.getActiveBits(); | ||||||||||
3616 | |||||||||||
3617 | // Make sure we're not losing bits from the constant. | ||||||||||
3618 | if (MinBits > 0 && | ||||||||||
3619 | MinBits < C1.getBitWidth() && | ||||||||||
3620 | MinBits >= ReqdBits) { | ||||||||||
3621 | EVT MinVT = EVT::getIntegerVT(*DAG.getContext(), MinBits); | ||||||||||
3622 | if (isTypeDesirableForOp(ISD::SETCC, MinVT)) { | ||||||||||
3623 | // Will get folded away. | ||||||||||
3624 | SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, MinVT, PreExt); | ||||||||||
3625 | if (MinBits == 1 && C1 == 1) | ||||||||||
3626 | // Invert the condition. | ||||||||||
3627 | return DAG.getSetCC(dl, VT, Trunc, DAG.getConstant(0, dl, MVT::i1), | ||||||||||
3628 | Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ); | ||||||||||
3629 | SDValue C = DAG.getConstant(C1.trunc(MinBits), dl, MinVT); | ||||||||||
3630 | return DAG.getSetCC(dl, VT, Trunc, C, Cond); | ||||||||||
3631 | } | ||||||||||
3632 | |||||||||||
3633 | // If truncating the setcc operands is not desirable, we can still | ||||||||||
3634 | // simplify the expression in some cases: | ||||||||||
3635 | // setcc ([sz]ext (setcc x, y, cc)), 0, setne) -> setcc (x, y, cc) | ||||||||||
3636 | // setcc ([sz]ext (setcc x, y, cc)), 0, seteq) -> setcc (x, y, inv(cc)) | ||||||||||
3637 | // setcc (zext (setcc x, y, cc)), 1, setne) -> setcc (x, y, inv(cc)) | ||||||||||
3638 | // setcc (zext (setcc x, y, cc)), 1, seteq) -> setcc (x, y, cc) | ||||||||||
3639 | // setcc (sext (setcc x, y, cc)), -1, setne) -> setcc (x, y, inv(cc)) | ||||||||||
3640 | // setcc (sext (setcc x, y, cc)), -1, seteq) -> setcc (x, y, cc) | ||||||||||
3641 | SDValue TopSetCC = N0->getOperand(0); | ||||||||||
3642 | unsigned N0Opc = N0->getOpcode(); | ||||||||||
3643 | bool SExt = (N0Opc == ISD::SIGN_EXTEND); | ||||||||||
3644 | if (TopSetCC.getValueType() == MVT::i1 && VT == MVT::i1 && | ||||||||||
3645 | TopSetCC.getOpcode() == ISD::SETCC && | ||||||||||
3646 | (N0Opc == ISD::ZERO_EXTEND || N0Opc == ISD::SIGN_EXTEND) && | ||||||||||
3647 | (isConstFalseVal(N1C) || | ||||||||||
3648 | isExtendedTrueVal(N1C, N0->getValueType(0), SExt))) { | ||||||||||
3649 | |||||||||||
3650 | bool Inverse = (N1C->isZero() && Cond == ISD::SETEQ) || | ||||||||||
3651 | (!N1C->isZero() && Cond == ISD::SETNE); | ||||||||||
3652 | |||||||||||
3653 | if (!Inverse) | ||||||||||
3654 | return TopSetCC; | ||||||||||
3655 | |||||||||||
3656 | ISD::CondCode InvCond = ISD::getSetCCInverse( | ||||||||||
3657 | cast<CondCodeSDNode>(TopSetCC.getOperand(2))->get(), | ||||||||||
3658 | TopSetCC.getOperand(0).getValueType()); | ||||||||||
3659 | return DAG.getSetCC(dl, VT, TopSetCC.getOperand(0), | ||||||||||
3660 | TopSetCC.getOperand(1), | ||||||||||
3661 | InvCond); | ||||||||||
3662 | } | ||||||||||
3663 | } | ||||||||||
3664 | } | ||||||||||
3665 | |||||||||||
3666 | // If the LHS is '(and load, const)', the RHS is 0, the test is for | ||||||||||
3667 | // equality or unsigned, and all 1 bits of the const are in the same | ||||||||||
3668 | // partial word, see if we can shorten the load. | ||||||||||
3669 | if (DCI.isBeforeLegalize() && | ||||||||||
3670 | !ISD::isSignedIntSetCC(Cond) && | ||||||||||
3671 | N0.getOpcode() == ISD::AND && C1 == 0 && | ||||||||||
3672 | N0.getNode()->hasOneUse() && | ||||||||||
3673 | isa<LoadSDNode>(N0.getOperand(0)) && | ||||||||||
3674 | N0.getOperand(0).getNode()->hasOneUse() && | ||||||||||
3675 | isa<ConstantSDNode>(N0.getOperand(1))) { | ||||||||||
3676 | LoadSDNode *Lod = cast<LoadSDNode>(N0.getOperand(0)); | ||||||||||
3677 | APInt bestMask; | ||||||||||
3678 | unsigned bestWidth = 0, bestOffset = 0; | ||||||||||
3679 | if (Lod->isSimple() && Lod->isUnindexed()) { | ||||||||||
3680 | unsigned origWidth = N0.getValueSizeInBits(); | ||||||||||
3681 | unsigned maskWidth = origWidth; | ||||||||||
3682 | // We can narrow (e.g.) 16-bit extending loads on 32-bit target to | ||||||||||
3683 | // 8 bits, but have to be careful... | ||||||||||
3684 | if (Lod->getExtensionType() != ISD::NON_EXTLOAD) | ||||||||||
3685 | origWidth = Lod->getMemoryVT().getSizeInBits(); | ||||||||||
3686 | const APInt &Mask = N0.getConstantOperandAPInt(1); | ||||||||||
3687 | for (unsigned width = origWidth / 2; width>=8; width /= 2) { | ||||||||||
3688 | APInt newMask = APInt::getLowBitsSet(maskWidth, width); | ||||||||||
3689 | for (unsigned offset=0; offset<origWidth/width; offset++) { | ||||||||||
3690 | if (Mask.isSubsetOf(newMask)) { | ||||||||||
3691 | if (Layout.isLittleEndian()) | ||||||||||
3692 | bestOffset = (uint64_t)offset * (width/8); | ||||||||||
3693 | else | ||||||||||
3694 | bestOffset = (origWidth/width - offset - 1) * (width/8); | ||||||||||
3695 | bestMask = Mask.lshr(offset * (width/8) * 8); | ||||||||||
3696 | bestWidth = width; | ||||||||||
3697 | break; | ||||||||||
3698 | } | ||||||||||
3699 | newMask <<= width; | ||||||||||
3700 | } | ||||||||||
3701 | } | ||||||||||
3702 | } | ||||||||||
3703 | if (bestWidth) { | ||||||||||
3704 | EVT newVT = EVT::getIntegerVT(*DAG.getContext(), bestWidth); | ||||||||||
3705 | if (newVT.isRound() && | ||||||||||
3706 | shouldReduceLoadWidth(Lod, ISD::NON_EXTLOAD, newVT)) { | ||||||||||
3707 | SDValue Ptr = Lod->getBasePtr(); | ||||||||||
3708 | if (bestOffset != 0) | ||||||||||
3709 | Ptr = | ||||||||||
3710 | DAG.getMemBasePlusOffset(Ptr, TypeSize::Fixed(bestOffset), dl); | ||||||||||
3711 | SDValue NewLoad = | ||||||||||
3712 | DAG.getLoad(newVT, dl, Lod->getChain(), Ptr, | ||||||||||
3713 | Lod->getPointerInfo().getWithOffset(bestOffset), | ||||||||||
3714 | Lod->getOriginalAlign()); | ||||||||||
3715 | return DAG.getSetCC(dl, VT, | ||||||||||
3716 | DAG.getNode(ISD::AND, dl, newVT, NewLoad, | ||||||||||
3717 | DAG.getConstant(bestMask.trunc(bestWidth), | ||||||||||
3718 | dl, newVT)), | ||||||||||
3719 | DAG.getConstant(0LL, dl, newVT), Cond); | ||||||||||
3720 | } | ||||||||||
3721 | } | ||||||||||
3722 | } | ||||||||||
3723 | |||||||||||
3724 | // If the LHS is a ZERO_EXTEND, perform the comparison on the input. | ||||||||||
3725 | if (N0.getOpcode() == ISD::ZERO_EXTEND) { | ||||||||||
3726 | unsigned InSize = N0.getOperand(0).getValueSizeInBits(); | ||||||||||
3727 | |||||||||||
3728 | // If the comparison constant has bits in the upper part, the | ||||||||||
3729 | // zero-extended value could never match. | ||||||||||
3730 | if (C1.intersects(APInt::getHighBitsSet(C1.getBitWidth(), | ||||||||||
3731 | C1.getBitWidth() - InSize))) { | ||||||||||
3732 | switch (Cond) { | ||||||||||
3733 | case ISD::SETUGT: | ||||||||||
3734 | case ISD::SETUGE: | ||||||||||
3735 | case ISD::SETEQ: | ||||||||||
3736 | return DAG.getConstant(0, dl, VT); | ||||||||||
3737 | case ISD::SETULT: | ||||||||||
3738 | case ISD::SETULE: | ||||||||||
3739 | case ISD::SETNE: | ||||||||||
3740 | return DAG.getConstant(1, dl, VT); | ||||||||||
3741 | case ISD::SETGT: | ||||||||||
3742 | case ISD::SETGE: | ||||||||||
3743 | // True if the sign bit of C1 is set. | ||||||||||
3744 | return DAG.getConstant(C1.isNegative(), dl, VT); | ||||||||||
3745 | case ISD::SETLT: | ||||||||||
3746 | case ISD::SETLE: | ||||||||||
3747 | // True if the sign bit of C1 isn't set. | ||||||||||
3748 | return DAG.getConstant(C1.isNonNegative(), dl, VT); | ||||||||||
3749 | default: | ||||||||||
3750 | break; | ||||||||||
3751 | } | ||||||||||
3752 | } | ||||||||||
3753 | |||||||||||
3754 | // Otherwise, we can perform the comparison with the low bits. | ||||||||||
3755 | switch (Cond) { | ||||||||||
3756 | case ISD::SETEQ: | ||||||||||
3757 | case ISD::SETNE: | ||||||||||
3758 | case ISD::SETUGT: | ||||||||||
3759 | case ISD::SETUGE: | ||||||||||
3760 | case ISD::SETULT: | ||||||||||
3761 | case ISD::SETULE: { | ||||||||||
3762 | EVT newVT = N0.getOperand(0).getValueType(); | ||||||||||
3763 | if (DCI.isBeforeLegalizeOps() || | ||||||||||
3764 | (isOperationLegal(ISD::SETCC, newVT) && | ||||||||||
3765 | isCondCodeLegal(Cond, newVT.getSimpleVT()))) { | ||||||||||
3766 | EVT NewSetCCVT = getSetCCResultType(Layout, *DAG.getContext(), newVT); | ||||||||||
3767 | SDValue NewConst = DAG.getConstant(C1.trunc(InSize), dl, newVT); | ||||||||||
3768 | |||||||||||
3769 | SDValue NewSetCC = DAG.getSetCC(dl, NewSetCCVT, N0.getOperand(0), | ||||||||||
3770 | NewConst, Cond); | ||||||||||
3771 | return DAG.getBoolExtOrTrunc(NewSetCC, dl, VT, N0.getValueType()); | ||||||||||
3772 | } | ||||||||||
3773 | break; | ||||||||||
3774 | } | ||||||||||
3775 | default: | ||||||||||
3776 | break; // todo, be more careful with signed comparisons | ||||||||||
3777 | } | ||||||||||
3778 | } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && | ||||||||||
3779 | (Cond == ISD::SETEQ || Cond == ISD::SETNE) && | ||||||||||
3780 | !isSExtCheaperThanZExt(cast<VTSDNode>(N0.getOperand(1))->getVT(), | ||||||||||
3781 | OpVT)) { | ||||||||||
3782 | EVT ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT(); | ||||||||||
3783 | unsigned ExtSrcTyBits = ExtSrcTy.getSizeInBits(); | ||||||||||
3784 | EVT ExtDstTy = N0.getValueType(); | ||||||||||
3785 | unsigned ExtDstTyBits = ExtDstTy.getSizeInBits(); | ||||||||||
3786 | |||||||||||
3787 | // If the constant doesn't fit into the number of bits for the source of | ||||||||||
3788 | // the sign extension, it is impossible for both sides to be equal. | ||||||||||
3789 | if (C1.getMinSignedBits() > ExtSrcTyBits) | ||||||||||
3790 | return DAG.getBoolConstant(Cond == ISD::SETNE, dl, VT, OpVT); | ||||||||||
3791 | |||||||||||
3792 | assert(ExtDstTy == N0.getOperand(0).getValueType() &&(static_cast <bool> (ExtDstTy == N0.getOperand(0).getValueType () && ExtDstTy != ExtSrcTy && "Unexpected types!" ) ? void (0) : __assert_fail ("ExtDstTy == N0.getOperand(0).getValueType() && ExtDstTy != ExtSrcTy && \"Unexpected types!\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 3793, __extension__ __PRETTY_FUNCTION__)) | ||||||||||
3793 | ExtDstTy != ExtSrcTy && "Unexpected types!")(static_cast <bool> (ExtDstTy == N0.getOperand(0).getValueType () && ExtDstTy != ExtSrcTy && "Unexpected types!" ) ? void (0) : __assert_fail ("ExtDstTy == N0.getOperand(0).getValueType() && ExtDstTy != ExtSrcTy && \"Unexpected types!\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 3793, __extension__ __PRETTY_FUNCTION__)); | ||||||||||
3794 | APInt Imm = APInt::getLowBitsSet(ExtDstTyBits, ExtSrcTyBits); | ||||||||||
3795 | SDValue ZextOp = DAG.getNode(ISD::AND, dl, ExtDstTy, N0.getOperand(0), | ||||||||||
3796 | DAG.getConstant(Imm, dl, ExtDstTy)); | ||||||||||
3797 | if (!DCI.isCalledByLegalizer()) | ||||||||||
3798 | DCI.AddToWorklist(ZextOp.getNode()); | ||||||||||
3799 | // Otherwise, make this a use of a zext. | ||||||||||
3800 | return DAG.getSetCC(dl, VT, ZextOp, | ||||||||||
3801 | DAG.getConstant(C1 & Imm, dl, ExtDstTy), Cond); | ||||||||||
3802 | } else if ((N1C->isZero() || N1C->isOne()) && | ||||||||||
3803 | (Cond == ISD::SETEQ || Cond == ISD::SETNE)) { | ||||||||||
3804 | // SETCC (SETCC), [0|1], [EQ|NE] -> SETCC | ||||||||||
3805 | if (N0.getOpcode() == ISD::SETCC && | ||||||||||
3806 | isTypeLegal(VT) && VT.bitsLE(N0.getValueType()) && | ||||||||||
3807 | (N0.getValueType() == MVT::i1 || | ||||||||||
3808 | getBooleanContents(N0.getOperand(0).getValueType()) == | ||||||||||
3809 | ZeroOrOneBooleanContent)) { | ||||||||||
3810 | bool TrueWhenTrue = (Cond == ISD::SETEQ) ^ (!N1C->isOne()); | ||||||||||
3811 | if (TrueWhenTrue) | ||||||||||
3812 | return DAG.getNode(ISD::TRUNCATE, dl, VT, N0); | ||||||||||
3813 | // Invert the condition. | ||||||||||
3814 | ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get(); | ||||||||||
3815 | CC = ISD::getSetCCInverse(CC, N0.getOperand(0).getValueType()); | ||||||||||
3816 | if (DCI.isBeforeLegalizeOps() || | ||||||||||
3817 | isCondCodeLegal(CC, N0.getOperand(0).getSimpleValueType())) | ||||||||||
3818 | return DAG.getSetCC(dl, VT, N0.getOperand(0), N0.getOperand(1), CC); | ||||||||||
3819 | } | ||||||||||
3820 | |||||||||||
3821 | if ((N0.getOpcode() == ISD::XOR || | ||||||||||
3822 | (N0.getOpcode() == ISD::AND && | ||||||||||
3823 | N0.getOperand(0).getOpcode() == ISD::XOR && | ||||||||||
3824 | N0.getOperand(1) == N0.getOperand(0).getOperand(1))) && | ||||||||||
3825 | isOneConstant(N0.getOperand(1))) { | ||||||||||
3826 | // If this is (X^1) == 0/1, swap the RHS and eliminate the xor. We | ||||||||||
3827 | // can only do this if the top bits are known zero. | ||||||||||
3828 | unsigned BitWidth = N0.getValueSizeInBits(); | ||||||||||
3829 | if (DAG.MaskedValueIsZero(N0, | ||||||||||
3830 | APInt::getHighBitsSet(BitWidth, | ||||||||||
3831 | BitWidth-1))) { | ||||||||||
3832 | // Okay, get the un-inverted input value. | ||||||||||
3833 | SDValue Val; | ||||||||||
3834 | if (N0.getOpcode() == ISD::XOR) { | ||||||||||
3835 | Val = N0.getOperand(0); | ||||||||||
3836 | } else { | ||||||||||
3837 | assert(N0.getOpcode() == ISD::AND &&(static_cast <bool> (N0.getOpcode() == ISD::AND && N0.getOperand(0).getOpcode() == ISD::XOR) ? void (0) : __assert_fail ("N0.getOpcode() == ISD::AND && N0.getOperand(0).getOpcode() == ISD::XOR" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 3838, __extension__ __PRETTY_FUNCTION__)) | ||||||||||
3838 | N0.getOperand(0).getOpcode() == ISD::XOR)(static_cast <bool> (N0.getOpcode() == ISD::AND && N0.getOperand(0).getOpcode() == ISD::XOR) ? void (0) : __assert_fail ("N0.getOpcode() == ISD::AND && N0.getOperand(0).getOpcode() == ISD::XOR" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 3838, __extension__ __PRETTY_FUNCTION__)); | ||||||||||
3839 | // ((X^1)&1)^1 -> X & 1 | ||||||||||
3840 | Val = DAG.getNode(ISD::AND, dl, N0.getValueType(), | ||||||||||
3841 | N0.getOperand(0).getOperand(0), | ||||||||||
3842 | N0.getOperand(1)); | ||||||||||
3843 | } | ||||||||||
3844 | |||||||||||
3845 | return DAG.getSetCC(dl, VT, Val, N1, | ||||||||||
3846 | Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ); | ||||||||||
3847 | } | ||||||||||
3848 | } else if (N1C->isOne()) { | ||||||||||
3849 | SDValue Op0 = N0; | ||||||||||
3850 | if (Op0.getOpcode() == ISD::TRUNCATE) | ||||||||||
3851 | Op0 = Op0.getOperand(0); | ||||||||||
3852 | |||||||||||
3853 | if ((Op0.getOpcode() == ISD::XOR) && | ||||||||||
3854 | Op0.getOperand(0).getOpcode() == ISD::SETCC && | ||||||||||
3855 | Op0.getOperand(1).getOpcode() == ISD::SETCC) { | ||||||||||
3856 | SDValue XorLHS = Op0.getOperand(0); | ||||||||||
3857 | SDValue XorRHS = Op0.getOperand(1); | ||||||||||
3858 | // Ensure that the input setccs return an i1 type or 0/1 value. | ||||||||||
3859 | if (Op0.getValueType() == MVT::i1 || | ||||||||||
3860 | (getBooleanContents(XorLHS.getOperand(0).getValueType()) == | ||||||||||
3861 | ZeroOrOneBooleanContent && | ||||||||||
3862 | getBooleanContents(XorRHS.getOperand(0).getValueType()) == | ||||||||||
3863 | ZeroOrOneBooleanContent)) { | ||||||||||
3864 | // (xor (setcc), (setcc)) == / != 1 -> (setcc) != / == (setcc) | ||||||||||
3865 | Cond = (Cond == ISD::SETEQ) ? ISD::SETNE : ISD::SETEQ; | ||||||||||
3866 | return DAG.getSetCC(dl, VT, XorLHS, XorRHS, Cond); | ||||||||||
3867 | } | ||||||||||
3868 | } | ||||||||||
3869 | if (Op0.getOpcode() == ISD::AND && isOneConstant(Op0.getOperand(1))) { | ||||||||||
3870 | // If this is (X&1) == / != 1, normalize it to (X&1) != / == 0. | ||||||||||
3871 | if (Op0.getValueType().bitsGT(VT)) | ||||||||||
3872 | Op0 = DAG.getNode(ISD::AND, dl, VT, | ||||||||||
3873 | DAG.getNode(ISD::TRUNCATE, dl, VT, Op0.getOperand(0)), | ||||||||||
3874 | DAG.getConstant(1, dl, VT)); | ||||||||||
3875 | else if (Op0.getValueType().bitsLT(VT)) | ||||||||||
3876 | Op0 = DAG.getNode(ISD::AND, dl, VT, | ||||||||||
3877 | DAG.getNode(ISD::ANY_EXTEND, dl, VT, Op0.getOperand(0)), | ||||||||||
3878 | DAG.getConstant(1, dl, VT)); | ||||||||||
3879 | |||||||||||
3880 | return DAG.getSetCC(dl, VT, Op0, | ||||||||||
3881 | DAG.getConstant(0, dl, Op0.getValueType()), | ||||||||||
3882 | Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ); | ||||||||||
3883 | } | ||||||||||
3884 | if (Op0.getOpcode() == ISD::AssertZext && | ||||||||||
3885 | cast<VTSDNode>(Op0.getOperand(1))->getVT() == MVT::i1) | ||||||||||
3886 | return DAG.getSetCC(dl, VT, Op0, | ||||||||||
3887 | DAG.getConstant(0, dl, Op0.getValueType()), | ||||||||||
3888 | Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ); | ||||||||||
3889 | } | ||||||||||
3890 | } | ||||||||||
3891 | |||||||||||
3892 | // Given: | ||||||||||
3893 | // icmp eq/ne (urem %x, %y), 0 | ||||||||||
3894 | // Iff %x has 0 or 1 bits set, and %y has at least 2 bits set, omit 'urem': | ||||||||||
3895 | // icmp eq/ne %x, 0 | ||||||||||
3896 | if (N0.getOpcode() == ISD::UREM && N1C->isZero() && | ||||||||||
3897 | (Cond == ISD::SETEQ || Cond == ISD::SETNE)) { | ||||||||||
3898 | KnownBits XKnown = DAG.computeKnownBits(N0.getOperand(0)); | ||||||||||
3899 | KnownBits YKnown = DAG.computeKnownBits(N0.getOperand(1)); | ||||||||||
3900 | if (XKnown.countMaxPopulation() == 1 && YKnown.countMinPopulation() >= 2) | ||||||||||
3901 | return DAG.getSetCC(dl, VT, N0.getOperand(0), N1, Cond); | ||||||||||
3902 | } | ||||||||||
3903 | |||||||||||
3904 | // Fold set_cc seteq (ashr X, BW-1), -1 -> set_cc setlt X, 0 | ||||||||||
3905 | // and set_cc setne (ashr X, BW-1), -1 -> set_cc setge X, 0 | ||||||||||
3906 | if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && | ||||||||||
3907 | N0.getOpcode() == ISD::SRA && isa<ConstantSDNode>(N0.getOperand(1)) && | ||||||||||
3908 | N0.getConstantOperandAPInt(1) == OpVT.getScalarSizeInBits() - 1 && | ||||||||||
3909 | N1C && N1C->isAllOnes()) { | ||||||||||
3910 | return DAG.getSetCC(dl, VT, N0.getOperand(0), | ||||||||||
3911 | DAG.getConstant(0, dl, OpVT), | ||||||||||
3912 | Cond == ISD::SETEQ ? ISD::SETLT : ISD::SETGE); | ||||||||||
3913 | } | ||||||||||
3914 | |||||||||||
3915 | if (SDValue V = | ||||||||||
3916 | optimizeSetCCOfSignedTruncationCheck(VT, N0, N1, Cond, DCI, dl)) | ||||||||||
3917 | return V; | ||||||||||
3918 | } | ||||||||||
3919 | |||||||||||
3920 | // These simplifications apply to splat vectors as well. | ||||||||||
3921 | // TODO: Handle more splat vector cases. | ||||||||||
3922 | if (auto *N1C = isConstOrConstSplat(N1)) { | ||||||||||
3923 | const APInt &C1 = N1C->getAPIntValue(); | ||||||||||
3924 | |||||||||||
3925 | APInt MinVal, MaxVal; | ||||||||||
3926 | unsigned OperandBitSize = N1C->getValueType(0).getScalarSizeInBits(); | ||||||||||
3927 | if (ISD::isSignedIntSetCC(Cond)) { | ||||||||||
3928 | MinVal = APInt::getSignedMinValue(OperandBitSize); | ||||||||||
3929 | MaxVal = APInt::getSignedMaxValue(OperandBitSize); | ||||||||||
3930 | } else { | ||||||||||
3931 | MinVal = APInt::getMinValue(OperandBitSize); | ||||||||||
3932 | MaxVal = APInt::getMaxValue(OperandBitSize); | ||||||||||
3933 | } | ||||||||||
3934 | |||||||||||
3935 | // Canonicalize GE/LE comparisons to use GT/LT comparisons. | ||||||||||
3936 | if (Cond == ISD::SETGE || Cond == ISD::SETUGE) { | ||||||||||
3937 | // X >= MIN --> true | ||||||||||
3938 | if (C1 == MinVal) | ||||||||||
3939 | return DAG.getBoolConstant(true, dl, VT, OpVT); | ||||||||||
3940 | |||||||||||
3941 | if (!VT.isVector()) { // TODO: Support this for vectors. | ||||||||||
3942 | // X >= C0 --> X > (C0 - 1) | ||||||||||
3943 | APInt C = C1 - 1; | ||||||||||
3944 | ISD::CondCode NewCC = (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT; | ||||||||||
3945 | if ((DCI.isBeforeLegalizeOps() || | ||||||||||
3946 | isCondCodeLegal(NewCC, VT.getSimpleVT())) && | ||||||||||
3947 | (!N1C->isOpaque() || (C.getBitWidth() <= 64 && | ||||||||||
3948 | isLegalICmpImmediate(C.getSExtValue())))) { | ||||||||||
3949 | return DAG.getSetCC(dl, VT, N0, | ||||||||||
3950 | DAG.getConstant(C, dl, N1.getValueType()), | ||||||||||
3951 | NewCC); | ||||||||||
3952 | } | ||||||||||
3953 | } | ||||||||||
3954 | } | ||||||||||
3955 | |||||||||||
3956 | if (Cond == ISD::SETLE || Cond == ISD::SETULE) { | ||||||||||
3957 | // X <= MAX --> true | ||||||||||
3958 | if (C1 == MaxVal) | ||||||||||
3959 | return DAG.getBoolConstant(true, dl, VT, OpVT); | ||||||||||
3960 | |||||||||||
3961 | // X <= C0 --> X < (C0 + 1) | ||||||||||
3962 | if (!VT.isVector()) { // TODO: Support this for vectors. | ||||||||||
3963 | APInt C = C1 + 1; | ||||||||||
3964 | ISD::CondCode NewCC = (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT; | ||||||||||
3965 | if ((DCI.isBeforeLegalizeOps() || | ||||||||||
3966 | isCondCodeLegal(NewCC, VT.getSimpleVT())) && | ||||||||||
3967 | (!N1C->isOpaque() || (C.getBitWidth() <= 64 && | ||||||||||
3968 | isLegalICmpImmediate(C.getSExtValue())))) { | ||||||||||
3969 | return DAG.getSetCC(dl, VT, N0, | ||||||||||
3970 | DAG.getConstant(C, dl, N1.getValueType()), | ||||||||||
3971 | NewCC); | ||||||||||
3972 | } | ||||||||||
3973 | } | ||||||||||
3974 | } | ||||||||||
3975 | |||||||||||
3976 | if (Cond == ISD::SETLT || Cond == ISD::SETULT) { | ||||||||||
3977 | if (C1 == MinVal) | ||||||||||
3978 | return DAG.getBoolConstant(false, dl, VT, OpVT); // X < MIN --> false | ||||||||||
3979 | |||||||||||
3980 | // TODO: Support this for vectors after legalize ops. | ||||||||||
3981 | if (!VT.isVector() || DCI.isBeforeLegalizeOps()) { | ||||||||||
3982 | // Canonicalize setlt X, Max --> setne X, Max | ||||||||||
3983 | if (C1 == MaxVal) | ||||||||||
3984 | return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE); | ||||||||||
3985 | |||||||||||
3986 | // If we have setult X, 1, turn it into seteq X, 0 | ||||||||||
3987 | if (C1 == MinVal+1) | ||||||||||
3988 | return DAG.getSetCC(dl, VT, N0, | ||||||||||
3989 | DAG.getConstant(MinVal, dl, N0.getValueType()), | ||||||||||
3990 | ISD::SETEQ); | ||||||||||
3991 | } | ||||||||||
3992 | } | ||||||||||
3993 | |||||||||||
3994 | if (Cond == ISD::SETGT || Cond == ISD::SETUGT) { | ||||||||||
3995 | if (C1 == MaxVal) | ||||||||||
3996 | return DAG.getBoolConstant(false, dl, VT, OpVT); // X > MAX --> false | ||||||||||
3997 | |||||||||||
3998 | // TODO: Support this for vectors after legalize ops. | ||||||||||
3999 | if (!VT.isVector() || DCI.isBeforeLegalizeOps()) { | ||||||||||
4000 | // Canonicalize setgt X, Min --> setne X, Min | ||||||||||
4001 | if (C1 == MinVal) | ||||||||||
4002 | return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE); | ||||||||||
4003 | |||||||||||
4004 | // If we have setugt X, Max-1, turn it into seteq X, Max | ||||||||||
4005 | if (C1 == MaxVal-1) | ||||||||||
4006 | return DAG.getSetCC(dl, VT, N0, | ||||||||||
4007 | DAG.getConstant(MaxVal, dl, N0.getValueType()), | ||||||||||
4008 | ISD::SETEQ); | ||||||||||
4009 | } | ||||||||||
4010 | } | ||||||||||
4011 | |||||||||||
4012 | if (Cond == ISD::SETEQ || Cond == ISD::SETNE) { | ||||||||||
4013 | // (X & (C l>>/<< Y)) ==/!= 0 --> ((X <</l>> Y) & C) ==/!= 0 | ||||||||||
4014 | if (C1.isZero()) | ||||||||||
4015 | if (SDValue CC = optimizeSetCCByHoistingAndByConstFromLogicalShift( | ||||||||||
4016 | VT, N0, N1, Cond, DCI, dl)) | ||||||||||
4017 | return CC; | ||||||||||
4018 | |||||||||||
4019 | // For all/any comparisons, replace or(x,shl(y,bw/2)) with and/or(x,y). | ||||||||||
4020 | // For example, when high 32-bits of i64 X are known clear: | ||||||||||
4021 | // all bits clear: (X | (Y<<32)) == 0 --> (X | Y) == 0 | ||||||||||
4022 | // all bits set: (X | (Y<<32)) == -1 --> (X & Y) == -1 | ||||||||||
4023 | bool CmpZero = N1C->getAPIntValue().isZero(); | ||||||||||
4024 | bool CmpNegOne = N1C->getAPIntValue().isAllOnes(); | ||||||||||
4025 | if ((CmpZero || CmpNegOne) && N0.hasOneUse()) { | ||||||||||
4026 | // Match or(lo,shl(hi,bw/2)) pattern. | ||||||||||
4027 | auto IsConcat = [&](SDValue V, SDValue &Lo, SDValue &Hi) { | ||||||||||
4028 | unsigned EltBits = V.getScalarValueSizeInBits(); | ||||||||||
4029 | if (V.getOpcode() != ISD::OR || (EltBits % 2) != 0) | ||||||||||
4030 | return false; | ||||||||||
4031 | SDValue LHS = V.getOperand(0); | ||||||||||
4032 | SDValue RHS = V.getOperand(1); | ||||||||||
4033 | APInt HiBits = APInt::getHighBitsSet(EltBits, EltBits / 2); | ||||||||||
4034 | // Unshifted element must have zero upperbits. | ||||||||||
4035 | if (RHS.getOpcode() == ISD::SHL && | ||||||||||
4036 | isa<ConstantSDNode>(RHS.getOperand(1)) && | ||||||||||
4037 | RHS.getConstantOperandAPInt(1) == (EltBits / 2) && | ||||||||||
4038 | DAG.MaskedValueIsZero(LHS, HiBits)) { | ||||||||||
4039 | Lo = LHS; | ||||||||||
4040 | Hi = RHS.getOperand(0); | ||||||||||
4041 | return true; | ||||||||||
4042 | } | ||||||||||
4043 | if (LHS.getOpcode() == ISD::SHL && | ||||||||||
4044 | isa<ConstantSDNode>(LHS.getOperand(1)) && | ||||||||||
4045 | LHS.getConstantOperandAPInt(1) == (EltBits / 2) && | ||||||||||
4046 | DAG.MaskedValueIsZero(RHS, HiBits)) { | ||||||||||
4047 | Lo = RHS; | ||||||||||
4048 | Hi = LHS.getOperand(0); | ||||||||||
4049 | return true; | ||||||||||
4050 | } | ||||||||||
4051 | return false; | ||||||||||
4052 | }; | ||||||||||
4053 | |||||||||||
4054 | auto MergeConcat = [&](SDValue Lo, SDValue Hi) { | ||||||||||
4055 | unsigned EltBits = N0.getScalarValueSizeInBits(); | ||||||||||
4056 | unsigned HalfBits = EltBits / 2; | ||||||||||
4057 | APInt HiBits = APInt::getHighBitsSet(EltBits, HalfBits); | ||||||||||
4058 | SDValue LoBits = DAG.getConstant(~HiBits, dl, OpVT); | ||||||||||
4059 | SDValue HiMask = DAG.getNode(ISD::AND, dl, OpVT, Hi, LoBits); | ||||||||||
4060 | SDValue NewN0 = | ||||||||||
4061 | DAG.getNode(CmpZero ? ISD::OR : ISD::AND, dl, OpVT, Lo, HiMask); | ||||||||||
4062 | SDValue NewN1 = CmpZero ? DAG.getConstant(0, dl, OpVT) : LoBits; | ||||||||||
4063 | return DAG.getSetCC(dl, VT, NewN0, NewN1, Cond); | ||||||||||
4064 | }; | ||||||||||
4065 | |||||||||||
4066 | SDValue Lo, Hi; | ||||||||||
4067 | if (IsConcat(N0, Lo, Hi)) | ||||||||||
4068 | return MergeConcat(Lo, Hi); | ||||||||||
4069 | |||||||||||
4070 | if (N0.getOpcode() == ISD::AND || N0.getOpcode() == ISD::OR) { | ||||||||||
4071 | SDValue Lo0, Lo1, Hi0, Hi1; | ||||||||||
4072 | if (IsConcat(N0.getOperand(0), Lo0, Hi0) && | ||||||||||
4073 | IsConcat(N0.getOperand(1), Lo1, Hi1)) { | ||||||||||
4074 | return MergeConcat(DAG.getNode(N0.getOpcode(), dl, OpVT, Lo0, Lo1), | ||||||||||
4075 | DAG.getNode(N0.getOpcode(), dl, OpVT, Hi0, Hi1)); | ||||||||||
4076 | } | ||||||||||
4077 | } | ||||||||||
4078 | } | ||||||||||
4079 | } | ||||||||||
4080 | |||||||||||
4081 | // If we have "setcc X, C0", check to see if we can shrink the immediate | ||||||||||
4082 | // by changing cc. | ||||||||||
4083 | // TODO: Support this for vectors after legalize ops. | ||||||||||
4084 | if (!VT.isVector() || DCI.isBeforeLegalizeOps()) { | ||||||||||
4085 | // SETUGT X, SINTMAX -> SETLT X, 0 | ||||||||||
4086 | // SETUGE X, SINTMIN -> SETLT X, 0 | ||||||||||
4087 | if ((Cond == ISD::SETUGT && C1.isMaxSignedValue()) || | ||||||||||
4088 | (Cond == ISD::SETUGE && C1.isMinSignedValue())) | ||||||||||
4089 | return DAG.getSetCC(dl, VT, N0, | ||||||||||
4090 | DAG.getConstant(0, dl, N1.getValueType()), | ||||||||||
4091 | ISD::SETLT); | ||||||||||
4092 | |||||||||||
4093 | // SETULT X, SINTMIN -> SETGT X, -1 | ||||||||||
4094 | // SETULE X, SINTMAX -> SETGT X, -1 | ||||||||||
4095 | if ((Cond == ISD::SETULT && C1.isMinSignedValue()) || | ||||||||||
4096 | (Cond == ISD::SETULE && C1.isMaxSignedValue())) | ||||||||||
4097 | return DAG.getSetCC(dl, VT, N0, | ||||||||||
4098 | DAG.getAllOnesConstant(dl, N1.getValueType()), | ||||||||||
4099 | ISD::SETGT); | ||||||||||
4100 | } | ||||||||||
4101 | } | ||||||||||
4102 | |||||||||||
4103 | // Back to non-vector simplifications. | ||||||||||
4104 | // TODO: Can we do these for vector splats? | ||||||||||
4105 | if (auto *N1C = dyn_cast<ConstantSDNode>(N1.getNode())) { | ||||||||||
4106 | const TargetLowering &TLI = DAG.getTargetLoweringInfo(); | ||||||||||
4107 | const APInt &C1 = N1C->getAPIntValue(); | ||||||||||
4108 | EVT ShValTy = N0.getValueType(); | ||||||||||
4109 | |||||||||||
4110 | // Fold bit comparisons when we can. This will result in an | ||||||||||
4111 | // incorrect value when boolean false is negative one, unless | ||||||||||
4112 | // the bitsize is 1 in which case the false value is the same | ||||||||||
4113 | // in practice regardless of the representation. | ||||||||||
4114 | if ((VT.getSizeInBits() == 1 || | ||||||||||
4115 | getBooleanContents(N0.getValueType()) == ZeroOrOneBooleanContent) && | ||||||||||
4116 | (Cond == ISD::SETEQ || Cond == ISD::SETNE) && | ||||||||||
4117 | (VT == ShValTy || (isTypeLegal(VT) && VT.bitsLE(ShValTy))) && | ||||||||||
4118 | N0.getOpcode() == ISD::AND) { | ||||||||||
4119 | if (auto *AndRHS = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { | ||||||||||
4120 | EVT ShiftTy = | ||||||||||
4121 | getShiftAmountTy(ShValTy, Layout, !DCI.isBeforeLegalize()); | ||||||||||
4122 | if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3 | ||||||||||
4123 | // Perform the xform if the AND RHS is a single bit. | ||||||||||
4124 | unsigned ShCt = AndRHS->getAPIntValue().logBase2(); | ||||||||||
4125 | if (AndRHS->getAPIntValue().isPowerOf2() && | ||||||||||
4126 | !TLI.shouldAvoidTransformToShift(ShValTy, ShCt)) { | ||||||||||
4127 | return DAG.getNode(ISD::TRUNCATE, dl, VT, | ||||||||||
4128 | DAG.getNode(ISD::SRL, dl, ShValTy, N0, | ||||||||||
4129 | DAG.getConstant(ShCt, dl, ShiftTy))); | ||||||||||
4130 | } | ||||||||||
4131 | } else if (Cond == ISD::SETEQ && C1 == AndRHS->getAPIntValue()) { | ||||||||||
4132 | // (X & 8) == 8 --> (X & 8) >> 3 | ||||||||||
4133 | // Perform the xform if C1 is a single bit. | ||||||||||
4134 | unsigned ShCt = C1.logBase2(); | ||||||||||
4135 | if (C1.isPowerOf2() && | ||||||||||
4136 | !TLI.shouldAvoidTransformToShift(ShValTy, ShCt)) { | ||||||||||
4137 | return DAG.getNode(ISD::TRUNCATE, dl, VT, | ||||||||||
4138 | DAG.getNode(ISD::SRL, dl, ShValTy, N0, | ||||||||||
4139 | DAG.getConstant(ShCt, dl, ShiftTy))); | ||||||||||
4140 | } | ||||||||||
4141 | } | ||||||||||
4142 | } | ||||||||||
4143 | } | ||||||||||
4144 | |||||||||||
4145 | if (C1.getMinSignedBits() <= 64 && | ||||||||||
4146 | !isLegalICmpImmediate(C1.getSExtValue())) { | ||||||||||
4147 | EVT ShiftTy = getShiftAmountTy(ShValTy, Layout, !DCI.isBeforeLegalize()); | ||||||||||
4148 | // (X & -256) == 256 -> (X >> 8) == 1 | ||||||||||
4149 | if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && | ||||||||||
4150 | N0.getOpcode() == ISD::AND && N0.hasOneUse()) { | ||||||||||
4151 | if (auto *AndRHS = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { | ||||||||||
4152 | const APInt &AndRHSC = AndRHS->getAPIntValue(); | ||||||||||
4153 | if (AndRHSC.isNegatedPowerOf2() && (AndRHSC & C1) == C1) { | ||||||||||
4154 | unsigned ShiftBits = AndRHSC.countTrailingZeros(); | ||||||||||
4155 | if (!TLI.shouldAvoidTransformToShift(ShValTy, ShiftBits)) { | ||||||||||
4156 | SDValue Shift = | ||||||||||
4157 | DAG.getNode(ISD::SRL, dl, ShValTy, N0.getOperand(0), | ||||||||||
4158 | DAG.getConstant(ShiftBits, dl, ShiftTy)); | ||||||||||
4159 | SDValue CmpRHS = DAG.getConstant(C1.lshr(ShiftBits), dl, ShValTy); | ||||||||||
4160 | return DAG.getSetCC(dl, VT, Shift, CmpRHS, Cond); | ||||||||||
4161 | } | ||||||||||
4162 | } | ||||||||||
4163 | } | ||||||||||
4164 | } else if (Cond == ISD::SETULT || Cond == ISD::SETUGE || | ||||||||||
4165 | Cond == ISD::SETULE || Cond == ISD::SETUGT) { | ||||||||||
4166 | bool AdjOne = (Cond == ISD::SETULE || Cond == ISD::SETUGT); | ||||||||||
4167 | // X < 0x100000000 -> (X >> 32) < 1 | ||||||||||
4168 | // X >= 0x100000000 -> (X >> 32) >= 1 | ||||||||||
4169 | // X <= 0x0ffffffff -> (X >> 32) < 1 | ||||||||||
4170 | // X > 0x0ffffffff -> (X >> 32) >= 1 | ||||||||||
4171 | unsigned ShiftBits; | ||||||||||
4172 | APInt NewC = C1; | ||||||||||
4173 | ISD::CondCode NewCond = Cond; | ||||||||||
4174 | if (AdjOne) { | ||||||||||
4175 | ShiftBits = C1.countTrailingOnes(); | ||||||||||
4176 | NewC = NewC + 1; | ||||||||||
4177 | NewCond = (Cond == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE; | ||||||||||
4178 | } else { | ||||||||||
4179 | ShiftBits = C1.countTrailingZeros(); | ||||||||||
4180 | } | ||||||||||
4181 | NewC.lshrInPlace(ShiftBits); | ||||||||||
4182 | if (ShiftBits && NewC.getMinSignedBits() <= 64 && | ||||||||||
4183 | isLegalICmpImmediate(NewC.getSExtValue()) && | ||||||||||
4184 | !TLI.shouldAvoidTransformToShift(ShValTy, ShiftBits)) { | ||||||||||
4185 | SDValue Shift = DAG.getNode(ISD::SRL, dl, ShValTy, N0, | ||||||||||
4186 | DAG.getConstant(ShiftBits, dl, ShiftTy)); | ||||||||||
4187 | SDValue CmpRHS = DAG.getConstant(NewC, dl, ShValTy); | ||||||||||
4188 | return DAG.getSetCC(dl, VT, Shift, CmpRHS, NewCond); | ||||||||||
4189 | } | ||||||||||
4190 | } | ||||||||||
4191 | } | ||||||||||
4192 | } | ||||||||||
4193 | |||||||||||
4194 | if (!isa<ConstantFPSDNode>(N0) && isa<ConstantFPSDNode>(N1)) { | ||||||||||
4195 | auto *CFP = cast<ConstantFPSDNode>(N1); | ||||||||||
4196 | assert(!CFP->getValueAPF().isNaN() && "Unexpected NaN value")(static_cast <bool> (!CFP->getValueAPF().isNaN() && "Unexpected NaN value") ? void (0) : __assert_fail ("!CFP->getValueAPF().isNaN() && \"Unexpected NaN value\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 4196, __extension__ __PRETTY_FUNCTION__)); | ||||||||||
4197 | |||||||||||
4198 | // Otherwise, we know the RHS is not a NaN. Simplify the node to drop the | ||||||||||
4199 | // constant if knowing that the operand is non-nan is enough. We prefer to | ||||||||||
4200 | // have SETO(x,x) instead of SETO(x, 0.0) because this avoids having to | ||||||||||
4201 | // materialize 0.0. | ||||||||||
4202 | if (Cond == ISD::SETO || Cond == ISD::SETUO) | ||||||||||
4203 | return DAG.getSetCC(dl, VT, N0, N0, Cond); | ||||||||||
4204 | |||||||||||
4205 | // setcc (fneg x), C -> setcc swap(pred) x, -C | ||||||||||
4206 | if (N0.getOpcode() == ISD::FNEG) { | ||||||||||
4207 | ISD::CondCode SwapCond = ISD::getSetCCSwappedOperands(Cond); | ||||||||||
4208 | if (DCI.isBeforeLegalizeOps() || | ||||||||||
4209 | isCondCodeLegal(SwapCond, N0.getSimpleValueType())) { | ||||||||||
4210 | SDValue NegN1 = DAG.getNode(ISD::FNEG, dl, N0.getValueType(), N1); | ||||||||||
4211 | return DAG.getSetCC(dl, VT, N0.getOperand(0), NegN1, SwapCond); | ||||||||||
4212 | } | ||||||||||
4213 | } | ||||||||||
4214 | |||||||||||
4215 | // If the condition is not legal, see if we can find an equivalent one | ||||||||||
4216 | // which is legal. | ||||||||||
4217 | if (!isCondCodeLegal(Cond, N0.getSimpleValueType())) { | ||||||||||
4218 | // If the comparison was an awkward floating-point == or != and one of | ||||||||||
4219 | // the comparison operands is infinity or negative infinity, convert the | ||||||||||
4220 | // condition to a less-awkward <= or >=. | ||||||||||
4221 | if (CFP->getValueAPF().isInfinity()) { | ||||||||||
4222 | bool IsNegInf = CFP->getValueAPF().isNegative(); | ||||||||||
4223 | ISD::CondCode NewCond = ISD::SETCC_INVALID; | ||||||||||
4224 | switch (Cond) { | ||||||||||
4225 | case ISD::SETOEQ: NewCond = IsNegInf ? ISD::SETOLE : ISD::SETOGE; break; | ||||||||||
4226 | case ISD::SETUEQ: NewCond = IsNegInf ? ISD::SETULE : ISD::SETUGE; break; | ||||||||||
4227 | case ISD::SETUNE: NewCond = IsNegInf ? ISD::SETUGT : ISD::SETULT; break; | ||||||||||
4228 | case ISD::SETONE: NewCond = IsNegInf ? ISD::SETOGT : ISD::SETOLT; break; | ||||||||||
4229 | default: break; | ||||||||||
4230 | } | ||||||||||
4231 | if (NewCond != ISD::SETCC_INVALID && | ||||||||||
4232 | isCondCodeLegal(NewCond, N0.getSimpleValueType())) | ||||||||||
4233 | return DAG.getSetCC(dl, VT, N0, N1, NewCond); | ||||||||||
4234 | } | ||||||||||
4235 | } | ||||||||||
4236 | } | ||||||||||
4237 | |||||||||||
4238 | if (N0 == N1) { | ||||||||||
4239 | // The sext(setcc()) => setcc() optimization relies on the appropriate | ||||||||||
4240 | // constant being emitted. | ||||||||||
4241 | assert(!N0.getValueType().isInteger() &&(static_cast <bool> (!N0.getValueType().isInteger() && "Integer types should be handled by FoldSetCC") ? void (0) : __assert_fail ("!N0.getValueType().isInteger() && \"Integer types should be handled by FoldSetCC\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 4242, __extension__ __PRETTY_FUNCTION__)) | ||||||||||
4242 | "Integer types should be handled by FoldSetCC")(static_cast <bool> (!N0.getValueType().isInteger() && "Integer types should be handled by FoldSetCC") ? void (0) : __assert_fail ("!N0.getValueType().isInteger() && \"Integer types should be handled by FoldSetCC\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 4242, __extension__ __PRETTY_FUNCTION__)); | ||||||||||
4243 | |||||||||||
4244 | bool EqTrue = ISD::isTrueWhenEqual(Cond); | ||||||||||
4245 | unsigned UOF = ISD::getUnorderedFlavor(Cond); | ||||||||||
4246 | if (UOF == 2) // FP operators that are undefined on NaNs. | ||||||||||
4247 | return DAG.getBoolConstant(EqTrue, dl, VT, OpVT); | ||||||||||
4248 | if (UOF == unsigned(EqTrue)) | ||||||||||
4249 | return DAG.getBoolConstant(EqTrue, dl, VT, OpVT); | ||||||||||
4250 | // Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO | ||||||||||
4251 | // if it is not already. | ||||||||||
4252 | ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO; | ||||||||||
4253 | if (NewCond != Cond && | ||||||||||
4254 | (DCI.isBeforeLegalizeOps() || | ||||||||||
4255 | isCondCodeLegal(NewCond, N0.getSimpleValueType()))) | ||||||||||
4256 | return DAG.getSetCC(dl, VT, N0, N1, NewCond); | ||||||||||
4257 | } | ||||||||||
4258 | |||||||||||
4259 | if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && | ||||||||||
4260 | N0.getValueType().isInteger()) { | ||||||||||
4261 | if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB || | ||||||||||
4262 | N0.getOpcode() == ISD::XOR) { | ||||||||||
4263 | // Simplify (X+Y) == (X+Z) --> Y == Z | ||||||||||
4264 | if (N0.getOpcode() == N1.getOpcode()) { | ||||||||||
4265 | if (N0.getOperand(0) == N1.getOperand(0)) | ||||||||||
4266 | return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(1), Cond); | ||||||||||
4267 | if (N0.getOperand(1) == N1.getOperand(1)) | ||||||||||
4268 | return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(0), Cond); | ||||||||||
4269 | if (isCommutativeBinOp(N0.getOpcode())) { | ||||||||||
4270 | // If X op Y == Y op X, try other combinations. | ||||||||||
4271 | if (N0.getOperand(0) == N1.getOperand(1)) | ||||||||||
4272 | return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(0), | ||||||||||
4273 | Cond); | ||||||||||
4274 | if (N0.getOperand(1) == N1.getOperand(0)) | ||||||||||
4275 | return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(1), | ||||||||||
4276 | Cond); | ||||||||||
4277 | } | ||||||||||
4278 | } | ||||||||||
4279 | |||||||||||
4280 | // If RHS is a legal immediate value for a compare instruction, we need | ||||||||||
4281 | // to be careful about increasing register pressure needlessly. | ||||||||||
4282 | bool LegalRHSImm = false; | ||||||||||
4283 | |||||||||||
4284 | if (auto *RHSC = dyn_cast<ConstantSDNode>(N1)) { | ||||||||||
4285 | if (auto *LHSR = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { | ||||||||||
4286 | // Turn (X+C1) == C2 --> X == C2-C1 | ||||||||||
4287 | if (N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse()) { | ||||||||||
4288 | return DAG.getSetCC(dl, VT, N0.getOperand(0), | ||||||||||
4289 | DAG.getConstant(RHSC->getAPIntValue()- | ||||||||||
4290 | LHSR->getAPIntValue(), | ||||||||||
4291 | dl, N0.getValueType()), Cond); | ||||||||||
4292 | } | ||||||||||
4293 | |||||||||||
4294 | // Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0. | ||||||||||
4295 | if (N0.getOpcode() == ISD::XOR) | ||||||||||
4296 | // If we know that all of the inverted bits are zero, don't bother | ||||||||||
4297 | // performing the inversion. | ||||||||||
4298 | if (DAG.MaskedValueIsZero(N0.getOperand(0), ~LHSR->getAPIntValue())) | ||||||||||
4299 | return | ||||||||||
4300 | DAG.getSetCC(dl, VT, N0.getOperand(0), | ||||||||||
4301 | DAG.getConstant(LHSR->getAPIntValue() ^ | ||||||||||
4302 | RHSC->getAPIntValue(), | ||||||||||
4303 | dl, N0.getValueType()), | ||||||||||
4304 | Cond); | ||||||||||
4305 | } | ||||||||||
4306 | |||||||||||
4307 | // Turn (C1-X) == C2 --> X == C1-C2 | ||||||||||
4308 | if (auto *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand(0))) { | ||||||||||
4309 | if (N0.getOpcode() == ISD::SUB && N0.getNode()->hasOneUse()) { | ||||||||||
4310 | return | ||||||||||
4311 | DAG.getSetCC(dl, VT, N0.getOperand(1), | ||||||||||
4312 | DAG.getConstant(SUBC->getAPIntValue() - | ||||||||||
4313 | RHSC->getAPIntValue(), | ||||||||||
4314 | dl, N0.getValueType()), | ||||||||||
4315 | Cond); | ||||||||||
4316 | } | ||||||||||
4317 | } | ||||||||||
4318 | |||||||||||
4319 | // Could RHSC fold directly into a compare? | ||||||||||
4320 | if (RHSC->getValueType(0).getSizeInBits() <= 64) | ||||||||||
4321 | LegalRHSImm = isLegalICmpImmediate(RHSC->getSExtValue()); | ||||||||||
4322 | } | ||||||||||
4323 | |||||||||||
4324 | // (X+Y) == X --> Y == 0 and similar folds. | ||||||||||
4325 | // Don't do this if X is an immediate that can fold into a cmp | ||||||||||
4326 | // instruction and X+Y has other uses. It could be an induction variable | ||||||||||
4327 | // chain, and the transform would increase register pressure. | ||||||||||
4328 | if (!LegalRHSImm || N0.hasOneUse()) | ||||||||||
4329 | if (SDValue V = foldSetCCWithBinOp(VT, N0, N1, Cond, dl, DCI)) | ||||||||||
4330 | return V; | ||||||||||
4331 | } | ||||||||||
4332 | |||||||||||
4333 | if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB || | ||||||||||
4334 | N1.getOpcode() == ISD::XOR) | ||||||||||
4335 | if (SDValue V = foldSetCCWithBinOp(VT, N1, N0, Cond, dl, DCI)) | ||||||||||
4336 | return V; | ||||||||||
4337 | |||||||||||
4338 | if (SDValue V = foldSetCCWithAnd(VT, N0, N1, Cond, dl, DCI)) | ||||||||||
4339 | return V; | ||||||||||
4340 | } | ||||||||||
4341 | |||||||||||
4342 | // Fold remainder of division by a constant. | ||||||||||
4343 | if ((N0.getOpcode() == ISD::UREM || N0.getOpcode() == ISD::SREM) && | ||||||||||
4344 | N0.hasOneUse() && (Cond == ISD::SETEQ || Cond == ISD::SETNE)) { | ||||||||||
4345 | AttributeList Attr = DAG.getMachineFunction().getFunction().getAttributes(); | ||||||||||
4346 | |||||||||||
4347 | // When division is cheap or optimizing for minimum size, | ||||||||||
4348 | // fall through to DIVREM creation by skipping this fold. | ||||||||||
4349 | if (!isIntDivCheap(VT, Attr) && !Attr.hasFnAttr(Attribute::MinSize)) { | ||||||||||
4350 | if (N0.getOpcode() == ISD::UREM) { | ||||||||||
4351 | if (SDValue Folded = buildUREMEqFold(VT, N0, N1, Cond, DCI, dl)) | ||||||||||
4352 | return Folded; | ||||||||||
4353 | } else if (N0.getOpcode() == ISD::SREM) { | ||||||||||
4354 | if (SDValue Folded = buildSREMEqFold(VT, N0, N1, Cond, DCI, dl)) | ||||||||||
4355 | return Folded; | ||||||||||
4356 | } | ||||||||||
4357 | } | ||||||||||
4358 | } | ||||||||||
4359 | |||||||||||
4360 | // Fold away ALL boolean setcc's. | ||||||||||
4361 | if (N0.getValueType().getScalarType() == MVT::i1 && foldBooleans) { | ||||||||||
4362 | SDValue Temp; | ||||||||||
4363 | switch (Cond) { | ||||||||||
4364 | default: llvm_unreachable("Unknown integer setcc!")::llvm::llvm_unreachable_internal("Unknown integer setcc!", "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 4364); | ||||||||||
4365 | case ISD::SETEQ: // X == Y -> ~(X^Y) | ||||||||||
4366 | Temp = DAG.getNode(ISD::XOR, dl, OpVT, N0, N1); | ||||||||||
4367 | N0 = DAG.getNOT(dl, Temp, OpVT); | ||||||||||
4368 | if (!DCI.isCalledByLegalizer()) | ||||||||||
4369 | DCI.AddToWorklist(Temp.getNode()); | ||||||||||
4370 | break; | ||||||||||
4371 | case ISD::SETNE: // X != Y --> (X^Y) | ||||||||||
4372 | N0 = DAG.getNode(ISD::XOR, dl, OpVT, N0, N1); | ||||||||||
4373 | break; | ||||||||||
4374 | case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> ~X & Y | ||||||||||
4375 | case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> ~X & Y | ||||||||||
4376 | Temp = DAG.getNOT(dl, N0, OpVT); | ||||||||||
4377 | N0 = DAG.getNode(ISD::AND, dl, OpVT, N1, Temp); | ||||||||||
4378 | if (!DCI.isCalledByLegalizer()) | ||||||||||
4379 | DCI.AddToWorklist(Temp.getNode()); | ||||||||||
4380 | break; | ||||||||||
4381 | case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> ~Y & X | ||||||||||
4382 | case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> ~Y & X | ||||||||||
4383 | Temp = DAG.getNOT(dl, N1, OpVT); | ||||||||||
4384 | N0 = DAG.getNode(ISD::AND, dl, OpVT, N0, Temp); | ||||||||||
4385 | if (!DCI.isCalledByLegalizer()) | ||||||||||
4386 | DCI.AddToWorklist(Temp.getNode()); | ||||||||||
4387 | break; | ||||||||||
4388 | case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> ~X | Y | ||||||||||
4389 | case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> ~X | Y | ||||||||||
4390 | Temp = DAG.getNOT(dl, N0, OpVT); | ||||||||||
4391 | N0 = DAG.getNode(ISD::OR, dl, OpVT, N1, Temp); | ||||||||||
4392 | if (!DCI.isCalledByLegalizer()) | ||||||||||
4393 | DCI.AddToWorklist(Temp.getNode()); | ||||||||||
4394 | break; | ||||||||||
4395 | case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> ~Y | X | ||||||||||
4396 | case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> ~Y | X | ||||||||||
4397 | Temp = DAG.getNOT(dl, N1, OpVT); | ||||||||||
4398 | N0 = DAG.getNode(ISD::OR, dl, OpVT, N0, Temp); | ||||||||||
4399 | break; | ||||||||||
4400 | } | ||||||||||
4401 | if (VT.getScalarType() != MVT::i1) { | ||||||||||
4402 | if (!DCI.isCalledByLegalizer()) | ||||||||||
4403 | DCI.AddToWorklist(N0.getNode()); | ||||||||||
4404 | // FIXME: If running after legalize, we probably can't do this. | ||||||||||
4405 | ISD::NodeType ExtendCode = getExtendForContent(getBooleanContents(OpVT)); | ||||||||||
4406 | N0 = DAG.getNode(ExtendCode, dl, VT, N0); | ||||||||||
4407 | } | ||||||||||
4408 | return N0; | ||||||||||
4409 | } | ||||||||||
4410 | |||||||||||
4411 | // Could not fold it. | ||||||||||
4412 | return SDValue(); | ||||||||||
4413 | } | ||||||||||
4414 | |||||||||||
4415 | /// Returns true (and the GlobalValue and the offset) if the node is a | ||||||||||
4416 | /// GlobalAddress + offset. | ||||||||||
4417 | bool TargetLowering::isGAPlusOffset(SDNode *WN, const GlobalValue *&GA, | ||||||||||
4418 | int64_t &Offset) const { | ||||||||||
4419 | |||||||||||
4420 | SDNode *N = unwrapAddress(SDValue(WN, 0)).getNode(); | ||||||||||
4421 | |||||||||||
4422 | if (auto *GASD = dyn_cast<GlobalAddressSDNode>(N)) { | ||||||||||
4423 | GA = GASD->getGlobal(); | ||||||||||
4424 | Offset += GASD->getOffset(); | ||||||||||
4425 | return true; | ||||||||||
4426 | } | ||||||||||
4427 | |||||||||||
4428 | if (N->getOpcode() == ISD::ADD) { | ||||||||||
4429 | SDValue N1 = N->getOperand(0); | ||||||||||
4430 | SDValue N2 = N->getOperand(1); | ||||||||||
4431 | if (isGAPlusOffset(N1.getNode(), GA, Offset)) { | ||||||||||
4432 | if (auto *V = dyn_cast<ConstantSDNode>(N2)) { | ||||||||||
4433 | Offset += V->getSExtValue(); | ||||||||||
4434 | return true; | ||||||||||
4435 | } | ||||||||||
4436 | } else if (isGAPlusOffset(N2.getNode(), GA, Offset)) { | ||||||||||
4437 | if (auto *V = dyn_cast<ConstantSDNode>(N1)) { | ||||||||||
4438 | Offset += V->getSExtValue(); | ||||||||||
4439 | return true; | ||||||||||
4440 | } | ||||||||||
4441 | } | ||||||||||
4442 | } | ||||||||||
4443 | |||||||||||
4444 | return false; | ||||||||||
4445 | } | ||||||||||
4446 | |||||||||||
4447 | SDValue TargetLowering::PerformDAGCombine(SDNode *N, | ||||||||||
4448 | DAGCombinerInfo &DCI) const { | ||||||||||
4449 | // Default implementation: no optimization. | ||||||||||
4450 | return SDValue(); | ||||||||||
4451 | } | ||||||||||
4452 | |||||||||||
4453 | //===----------------------------------------------------------------------===// | ||||||||||
4454 | // Inline Assembler Implementation Methods | ||||||||||
4455 | //===----------------------------------------------------------------------===// | ||||||||||
4456 | |||||||||||
4457 | TargetLowering::ConstraintType | ||||||||||
4458 | TargetLowering::getConstraintType(StringRef Constraint) const { | ||||||||||
4459 | unsigned S = Constraint.size(); | ||||||||||
4460 | |||||||||||
4461 | if (S == 1) { | ||||||||||
4462 | switch (Constraint[0]) { | ||||||||||
4463 | default: break; | ||||||||||
4464 | case 'r': | ||||||||||
4465 | return C_RegisterClass; | ||||||||||
4466 | case 'm': // memory | ||||||||||
4467 | case 'o': // offsetable | ||||||||||
4468 | case 'V': // not offsetable | ||||||||||
4469 | return C_Memory; | ||||||||||
4470 | case 'n': // Simple Integer | ||||||||||
4471 | case 'E': // Floating Point Constant | ||||||||||
4472 | case 'F': // Floating Point Constant | ||||||||||
4473 | return C_Immediate; | ||||||||||
4474 | case 'i': // Simple Integer or Relocatable Constant | ||||||||||
4475 | case 's': // Relocatable Constant | ||||||||||
4476 | case 'p': // Address. | ||||||||||
4477 | case 'X': // Allow ANY value. | ||||||||||
4478 | case 'I': // Target registers. | ||||||||||
4479 | case 'J': | ||||||||||
4480 | case 'K': | ||||||||||
4481 | case 'L': | ||||||||||
4482 | case 'M': | ||||||||||
4483 | case 'N': | ||||||||||
4484 | case 'O': | ||||||||||
4485 | case 'P': | ||||||||||
4486 | case '<': | ||||||||||
4487 | case '>': | ||||||||||
4488 | return C_Other; | ||||||||||
4489 | } | ||||||||||
4490 | } | ||||||||||
4491 | |||||||||||
4492 | if (S > 1 && Constraint[0] == '{' && Constraint[S - 1] == '}') { | ||||||||||
4493 | if (S == 8 && Constraint.substr(1, 6) == "memory") // "{memory}" | ||||||||||
4494 | return C_Memory; | ||||||||||
4495 | return C_Register; | ||||||||||
4496 | } | ||||||||||
4497 | return C_Unknown; | ||||||||||
4498 | } | ||||||||||
4499 | |||||||||||
4500 | /// Try to replace an X constraint, which matches anything, with another that | ||||||||||
4501 | /// has more specific requirements based on the type of the corresponding | ||||||||||
4502 | /// operand. | ||||||||||
4503 | const char *TargetLowering::LowerXConstraint(EVT ConstraintVT) const { | ||||||||||
4504 | if (ConstraintVT.isInteger()) | ||||||||||
4505 | return "r"; | ||||||||||
4506 | if (ConstraintVT.isFloatingPoint()) | ||||||||||
4507 | return "f"; // works for many targets | ||||||||||
4508 | return nullptr; | ||||||||||
4509 | } | ||||||||||
4510 | |||||||||||
4511 | SDValue TargetLowering::LowerAsmOutputForConstraint( | ||||||||||
4512 | SDValue &Chain, SDValue &Flag, const SDLoc &DL, | ||||||||||
4513 | const AsmOperandInfo &OpInfo, SelectionDAG &DAG) const { | ||||||||||
4514 | return SDValue(); | ||||||||||
4515 | } | ||||||||||
4516 | |||||||||||
4517 | /// Lower the specified operand into the Ops vector. | ||||||||||
4518 | /// If it is invalid, don't add anything to Ops. | ||||||||||
4519 | void TargetLowering::LowerAsmOperandForConstraint(SDValue Op, | ||||||||||
4520 | std::string &Constraint, | ||||||||||
4521 | std::vector<SDValue> &Ops, | ||||||||||
4522 | SelectionDAG &DAG) const { | ||||||||||
4523 | |||||||||||
4524 | if (Constraint.length() > 1) return; | ||||||||||
4525 | |||||||||||
4526 | char ConstraintLetter = Constraint[0]; | ||||||||||
4527 | switch (ConstraintLetter) { | ||||||||||
4528 | default: break; | ||||||||||
4529 | case 'X': // Allows any operand; labels (basic block) use this. | ||||||||||
4530 | if (Op.getOpcode() == ISD::BasicBlock || | ||||||||||
4531 | Op.getOpcode() == ISD::TargetBlockAddress) { | ||||||||||
4532 | Ops.push_back(Op); | ||||||||||
4533 | return; | ||||||||||
4534 | } | ||||||||||
4535 | LLVM_FALLTHROUGH[[gnu::fallthrough]]; | ||||||||||
4536 | case 'i': // Simple Integer or Relocatable Constant | ||||||||||
4537 | case 'n': // Simple Integer | ||||||||||
4538 | case 's': { // Relocatable Constant | ||||||||||
4539 | |||||||||||
4540 | GlobalAddressSDNode *GA; | ||||||||||
4541 | ConstantSDNode *C; | ||||||||||
4542 | BlockAddressSDNode *BA; | ||||||||||
4543 | uint64_t Offset = 0; | ||||||||||
4544 | |||||||||||
4545 | // Match (GA) or (C) or (GA+C) or (GA-C) or ((GA+C)+C) or (((GA+C)+C)+C), | ||||||||||
4546 | // etc., since getelementpointer is variadic. We can't use | ||||||||||
4547 | // SelectionDAG::FoldSymbolOffset because it expects the GA to be accessible | ||||||||||
4548 | // while in this case the GA may be furthest from the root node which is | ||||||||||
4549 | // likely an ISD::ADD. | ||||||||||
4550 | while (1) { | ||||||||||
4551 | if ((GA = dyn_cast<GlobalAddressSDNode>(Op)) && ConstraintLetter != 'n') { | ||||||||||
4552 | Ops.push_back(DAG.getTargetGlobalAddress(GA->getGlobal(), SDLoc(Op), | ||||||||||
4553 | GA->getValueType(0), | ||||||||||
4554 | Offset + GA->getOffset())); | ||||||||||
4555 | return; | ||||||||||
4556 | } | ||||||||||
4557 | if ((C = dyn_cast<ConstantSDNode>(Op)) && ConstraintLetter != 's') { | ||||||||||
4558 | // gcc prints these as sign extended. Sign extend value to 64 bits | ||||||||||
4559 | // now; without this it would get ZExt'd later in | ||||||||||
4560 | // ScheduleDAGSDNodes::EmitNode, which is very generic. | ||||||||||
4561 | bool IsBool = C->getConstantIntValue()->getBitWidth() == 1; | ||||||||||
4562 | BooleanContent BCont = getBooleanContents(MVT::i64); | ||||||||||
4563 | ISD::NodeType ExtOpc = | ||||||||||
4564 | IsBool ? getExtendForContent(BCont) : ISD::SIGN_EXTEND; | ||||||||||
4565 | int64_t ExtVal = | ||||||||||
4566 | ExtOpc == ISD::ZERO_EXTEND ? C->getZExtValue() : C->getSExtValue(); | ||||||||||
4567 | Ops.push_back( | ||||||||||
4568 | DAG.getTargetConstant(Offset + ExtVal, SDLoc(C), MVT::i64)); | ||||||||||
4569 | return; | ||||||||||
4570 | } | ||||||||||
4571 | if ((BA = dyn_cast<BlockAddressSDNode>(Op)) && ConstraintLetter != 'n') { | ||||||||||
4572 | Ops.push_back(DAG.getTargetBlockAddress( | ||||||||||
4573 | BA->getBlockAddress(), BA->getValueType(0), | ||||||||||
4574 | Offset + BA->getOffset(), BA->getTargetFlags())); | ||||||||||
4575 | return; | ||||||||||
4576 | } | ||||||||||
4577 | const unsigned OpCode = Op.getOpcode(); | ||||||||||
4578 | if (OpCode == ISD::ADD || OpCode == ISD::SUB) { | ||||||||||
4579 | if ((C = dyn_cast<ConstantSDNode>(Op.getOperand(0)))) | ||||||||||
4580 | Op = Op.getOperand(1); | ||||||||||
4581 | // Subtraction is not commutative. | ||||||||||
4582 | else if (OpCode == ISD::ADD && | ||||||||||
4583 | (C = dyn_cast<ConstantSDNode>(Op.getOperand(1)))) | ||||||||||
4584 | Op = Op.getOperand(0); | ||||||||||
4585 | else | ||||||||||
4586 | return; | ||||||||||
4587 | Offset += (OpCode == ISD::ADD ? 1 : -1) * C->getSExtValue(); | ||||||||||
4588 | continue; | ||||||||||
4589 | } | ||||||||||
4590 | return; | ||||||||||
4591 | } | ||||||||||
4592 | break; | ||||||||||
4593 | } | ||||||||||
4594 | } | ||||||||||
4595 | } | ||||||||||
4596 | |||||||||||
4597 | std::pair<unsigned, const TargetRegisterClass *> | ||||||||||
4598 | TargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *RI, | ||||||||||
4599 | StringRef Constraint, | ||||||||||
4600 | MVT VT) const { | ||||||||||
4601 | if (Constraint.empty() || Constraint[0] != '{') | ||||||||||
4602 | return std::make_pair(0u, static_cast<TargetRegisterClass *>(nullptr)); | ||||||||||
4603 | assert(*(Constraint.end() - 1) == '}' && "Not a brace enclosed constraint?")(static_cast <bool> (*(Constraint.end() - 1) == '}' && "Not a brace enclosed constraint?") ? void (0) : __assert_fail ("*(Constraint.end() - 1) == '}' && \"Not a brace enclosed constraint?\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 4603, __extension__ __PRETTY_FUNCTION__)); | ||||||||||
4604 | |||||||||||
4605 | // Remove the braces from around the name. | ||||||||||
4606 | StringRef RegName(Constraint.data() + 1, Constraint.size() - 2); | ||||||||||
4607 | |||||||||||
4608 | std::pair<unsigned, const TargetRegisterClass *> R = | ||||||||||
4609 | std::make_pair(0u, static_cast<const TargetRegisterClass *>(nullptr)); | ||||||||||
4610 | |||||||||||
4611 | // Figure out which register class contains this reg. | ||||||||||
4612 | for (const TargetRegisterClass *RC : RI->regclasses()) { | ||||||||||
4613 | // If none of the value types for this register class are valid, we | ||||||||||
4614 | // can't use it. For example, 64-bit reg classes on 32-bit targets. | ||||||||||
4615 | if (!isLegalRC(*RI, *RC)) | ||||||||||
4616 | continue; | ||||||||||
4617 | |||||||||||
4618 | for (const MCPhysReg &PR : *RC) { | ||||||||||
4619 | if (RegName.equals_insensitive(RI->getRegAsmName(PR))) { | ||||||||||
4620 | std::pair<unsigned, const TargetRegisterClass *> S = | ||||||||||
4621 | std::make_pair(PR, RC); | ||||||||||
4622 | |||||||||||
4623 | // If this register class has the requested value type, return it, | ||||||||||
4624 | // otherwise keep searching and return the first class found | ||||||||||
4625 | // if no other is found which explicitly has the requested type. | ||||||||||
4626 | if (RI->isTypeLegalForClass(*RC, VT)) | ||||||||||
4627 | return S; | ||||||||||
4628 | if (!R.second) | ||||||||||
4629 | R = S; | ||||||||||
4630 | } | ||||||||||
4631 | } | ||||||||||
4632 | } | ||||||||||
4633 | |||||||||||
4634 | return R; | ||||||||||
4635 | } | ||||||||||
4636 | |||||||||||
4637 | //===----------------------------------------------------------------------===// | ||||||||||
4638 | // Constraint Selection. | ||||||||||
4639 | |||||||||||
4640 | /// Return true of this is an input operand that is a matching constraint like | ||||||||||
4641 | /// "4". | ||||||||||
4642 | bool TargetLowering::AsmOperandInfo::isMatchingInputConstraint() const { | ||||||||||
4643 | assert(!ConstraintCode.empty() && "No known constraint!")(static_cast <bool> (!ConstraintCode.empty() && "No known constraint!") ? void (0) : __assert_fail ("!ConstraintCode.empty() && \"No known constraint!\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 4643, __extension__ __PRETTY_FUNCTION__)); | ||||||||||
4644 | return isdigit(static_cast<unsigned char>(ConstraintCode[0])); | ||||||||||
4645 | } | ||||||||||
4646 | |||||||||||
4647 | /// If this is an input matching constraint, this method returns the output | ||||||||||
4648 | /// operand it matches. | ||||||||||
4649 | unsigned TargetLowering::AsmOperandInfo::getMatchedOperand() const { | ||||||||||
4650 | assert(!ConstraintCode.empty() && "No known constraint!")(static_cast <bool> (!ConstraintCode.empty() && "No known constraint!") ? void (0) : __assert_fail ("!ConstraintCode.empty() && \"No known constraint!\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 4650, __extension__ __PRETTY_FUNCTION__)); | ||||||||||
4651 | return atoi(ConstraintCode.c_str()); | ||||||||||
4652 | } | ||||||||||
4653 | |||||||||||
4654 | /// Split up the constraint string from the inline assembly value into the | ||||||||||
4655 | /// specific constraints and their prefixes, and also tie in the associated | ||||||||||
4656 | /// operand values. | ||||||||||
4657 | /// If this returns an empty vector, and if the constraint string itself | ||||||||||
4658 | /// isn't empty, there was an error parsing. | ||||||||||
4659 | TargetLowering::AsmOperandInfoVector | ||||||||||
4660 | TargetLowering::ParseConstraints(const DataLayout &DL, | ||||||||||
4661 | const TargetRegisterInfo *TRI, | ||||||||||
4662 | const CallBase &Call) const { | ||||||||||
4663 | /// Information about all of the constraints. | ||||||||||
4664 | AsmOperandInfoVector ConstraintOperands; | ||||||||||
4665 | const InlineAsm *IA = cast<InlineAsm>(Call.getCalledOperand()); | ||||||||||
4666 | unsigned maCount = 0; // Largest number of multiple alternative constraints. | ||||||||||
4667 | |||||||||||
4668 | // Do a prepass over the constraints, canonicalizing them, and building up the | ||||||||||
4669 | // ConstraintOperands list. | ||||||||||
4670 | unsigned ArgNo = 0; // ArgNo - The argument of the CallInst. | ||||||||||
4671 | unsigned ResNo = 0; // ResNo - The result number of the next output. | ||||||||||
4672 | |||||||||||
4673 | for (InlineAsm::ConstraintInfo &CI : IA->ParseConstraints()) { | ||||||||||
4674 | ConstraintOperands.emplace_back(std::move(CI)); | ||||||||||
4675 | AsmOperandInfo &OpInfo = ConstraintOperands.back(); | ||||||||||
4676 | |||||||||||
4677 | // Update multiple alternative constraint count. | ||||||||||
4678 | if (OpInfo.multipleAlternatives.size() > maCount) | ||||||||||
4679 | maCount = OpInfo.multipleAlternatives.size(); | ||||||||||
4680 | |||||||||||
4681 | OpInfo.ConstraintVT = MVT::Other; | ||||||||||
4682 | |||||||||||
4683 | // Compute the value type for each operand. | ||||||||||
4684 | switch (OpInfo.Type) { | ||||||||||
4685 | case InlineAsm::isOutput: | ||||||||||
4686 | // Indirect outputs just consume an argument. | ||||||||||
4687 | if (OpInfo.isIndirect) { | ||||||||||
4688 | OpInfo.CallOperandVal = Call.getArgOperand(ArgNo++); | ||||||||||
4689 | break; | ||||||||||
4690 | } | ||||||||||
4691 | |||||||||||
4692 | // The return value of the call is this value. As such, there is no | ||||||||||
4693 | // corresponding argument. | ||||||||||
4694 | assert(!Call.getType()->isVoidTy() && "Bad inline asm!")(static_cast <bool> (!Call.getType()->isVoidTy() && "Bad inline asm!") ? void (0) : __assert_fail ("!Call.getType()->isVoidTy() && \"Bad inline asm!\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 4694, __extension__ __PRETTY_FUNCTION__)); | ||||||||||
4695 | if (StructType *STy = dyn_cast<StructType>(Call.getType())) { | ||||||||||
4696 | OpInfo.ConstraintVT = | ||||||||||
4697 | getSimpleValueType(DL, STy->getElementType(ResNo)); | ||||||||||
4698 | } else { | ||||||||||
4699 | assert(ResNo == 0 && "Asm only has one result!")(static_cast <bool> (ResNo == 0 && "Asm only has one result!" ) ? void (0) : __assert_fail ("ResNo == 0 && \"Asm only has one result!\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 4699, __extension__ __PRETTY_FUNCTION__)); | ||||||||||
4700 | OpInfo.ConstraintVT = | ||||||||||
4701 | getAsmOperandValueType(DL, Call.getType()).getSimpleVT(); | ||||||||||
4702 | } | ||||||||||
4703 | ++ResNo; | ||||||||||
4704 | break; | ||||||||||
4705 | case InlineAsm::isInput: | ||||||||||
4706 | OpInfo.CallOperandVal = Call.getArgOperand(ArgNo++); | ||||||||||
4707 | break; | ||||||||||
4708 | case InlineAsm::isClobber: | ||||||||||
4709 | // Nothing to do. | ||||||||||
4710 | break; | ||||||||||
4711 | } | ||||||||||
4712 | |||||||||||
4713 | if (OpInfo.CallOperandVal) { | ||||||||||
4714 | llvm::Type *OpTy = OpInfo.CallOperandVal->getType(); | ||||||||||
4715 | if (OpInfo.isIndirect) { | ||||||||||
4716 | llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy); | ||||||||||
4717 | if (!PtrTy) | ||||||||||
4718 | report_fatal_error("Indirect operand for inline asm not a pointer!"); | ||||||||||
4719 | OpTy = PtrTy->getElementType(); | ||||||||||
4720 | } | ||||||||||
4721 | |||||||||||
4722 | // Look for vector wrapped in a struct. e.g. { <16 x i8> }. | ||||||||||
4723 | if (StructType *STy = dyn_cast<StructType>(OpTy)) | ||||||||||
4724 | if (STy->getNumElements() == 1) | ||||||||||
4725 | OpTy = STy->getElementType(0); | ||||||||||
4726 | |||||||||||
4727 | // If OpTy is not a single value, it may be a struct/union that we | ||||||||||
4728 | // can tile with integers. | ||||||||||
4729 | if (!OpTy->isSingleValueType() && OpTy->isSized()) { | ||||||||||
4730 | unsigned BitSize = DL.getTypeSizeInBits(OpTy); | ||||||||||
4731 | switch (BitSize) { | ||||||||||
4732 | default: break; | ||||||||||
4733 | case 1: | ||||||||||
4734 | case 8: | ||||||||||
4735 | case 16: | ||||||||||
4736 | case 32: | ||||||||||
4737 | case 64: | ||||||||||
4738 | case 128: | ||||||||||
4739 | OpInfo.ConstraintVT = | ||||||||||
4740 | MVT::getVT(IntegerType::get(OpTy->getContext(), BitSize), true); | ||||||||||
4741 | break; | ||||||||||
4742 | } | ||||||||||
4743 | } else if (PointerType *PT = dyn_cast<PointerType>(OpTy)) { | ||||||||||
4744 | unsigned PtrSize = DL.getPointerSizeInBits(PT->getAddressSpace()); | ||||||||||
4745 | OpInfo.ConstraintVT = MVT::getIntegerVT(PtrSize); | ||||||||||
4746 | } else { | ||||||||||
4747 | OpInfo.ConstraintVT = MVT::getVT(OpTy, true); | ||||||||||
4748 | } | ||||||||||
4749 | } | ||||||||||
4750 | } | ||||||||||
4751 | |||||||||||
4752 | // If we have multiple alternative constraints, select the best alternative. | ||||||||||
4753 | if (!ConstraintOperands.empty()) { | ||||||||||
4754 | if (maCount) { | ||||||||||
4755 | unsigned bestMAIndex = 0; | ||||||||||
4756 | int bestWeight = -1; | ||||||||||
4757 | // weight: -1 = invalid match, and 0 = so-so match to 5 = good match. | ||||||||||
4758 | int weight = -1; | ||||||||||
4759 | unsigned maIndex; | ||||||||||
4760 | // Compute the sums of the weights for each alternative, keeping track | ||||||||||
4761 | // of the best (highest weight) one so far. | ||||||||||
4762 | for (maIndex = 0; maIndex < maCount; ++maIndex) { | ||||||||||
4763 | int weightSum = 0; | ||||||||||
4764 | for (unsigned cIndex = 0, eIndex = ConstraintOperands.size(); | ||||||||||
4765 | cIndex != eIndex; ++cIndex) { | ||||||||||
4766 | AsmOperandInfo &OpInfo = ConstraintOperands[cIndex]; | ||||||||||
4767 | if (OpInfo.Type == InlineAsm::isClobber) | ||||||||||
4768 | continue; | ||||||||||
4769 | |||||||||||
4770 | // If this is an output operand with a matching input operand, | ||||||||||
4771 | // look up the matching input. If their types mismatch, e.g. one | ||||||||||
4772 | // is an integer, the other is floating point, or their sizes are | ||||||||||
4773 | // different, flag it as an maCantMatch. | ||||||||||
4774 | if (OpInfo.hasMatchingInput()) { | ||||||||||
4775 | AsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput]; | ||||||||||
4776 | if (OpInfo.ConstraintVT != Input.ConstraintVT) { | ||||||||||
4777 | if ((OpInfo.ConstraintVT.isInteger() != | ||||||||||
4778 | Input.ConstraintVT.isInteger()) || | ||||||||||
4779 | (OpInfo.ConstraintVT.getSizeInBits() != | ||||||||||
4780 | Input.ConstraintVT.getSizeInBits())) { | ||||||||||
4781 | weightSum = -1; // Can't match. | ||||||||||
4782 | break; | ||||||||||
4783 | } | ||||||||||
4784 | } | ||||||||||
4785 | } | ||||||||||
4786 | weight = getMultipleConstraintMatchWeight(OpInfo, maIndex); | ||||||||||
4787 | if (weight == -1) { | ||||||||||
4788 | weightSum = -1; | ||||||||||
4789 | break; | ||||||||||
4790 | } | ||||||||||
4791 | weightSum += weight; | ||||||||||
4792 | } | ||||||||||
4793 | // Update best. | ||||||||||
4794 | if (weightSum > bestWeight) { | ||||||||||
4795 | bestWeight = weightSum; | ||||||||||
4796 | bestMAIndex = maIndex; | ||||||||||
4797 | } | ||||||||||
4798 | } | ||||||||||
4799 | |||||||||||
4800 | // Now select chosen alternative in each constraint. | ||||||||||
4801 | for (unsigned cIndex = 0, eIndex = ConstraintOperands.size(); | ||||||||||
4802 | cIndex != eIndex; ++cIndex) { | ||||||||||
4803 | AsmOperandInfo &cInfo = ConstraintOperands[cIndex]; | ||||||||||
4804 | if (cInfo.Type == InlineAsm::isClobber) | ||||||||||
4805 | continue; | ||||||||||
4806 | cInfo.selectAlternative(bestMAIndex); | ||||||||||
4807 | } | ||||||||||
4808 | } | ||||||||||
4809 | } | ||||||||||
4810 | |||||||||||
4811 | // Check and hook up tied operands, choose constraint code to use. | ||||||||||
4812 | for (unsigned cIndex = 0, eIndex = ConstraintOperands.size(); | ||||||||||
4813 | cIndex != eIndex; ++cIndex) { | ||||||||||
4814 | AsmOperandInfo &OpInfo = ConstraintOperands[cIndex]; | ||||||||||
4815 | |||||||||||
4816 | // If this is an output operand with a matching input operand, look up the | ||||||||||
4817 | // matching input. If their types mismatch, e.g. one is an integer, the | ||||||||||
4818 | // other is floating point, or their sizes are different, flag it as an | ||||||||||
4819 | // error. | ||||||||||
4820 | if (OpInfo.hasMatchingInput()) { | ||||||||||
4821 | AsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput]; | ||||||||||
4822 | |||||||||||
4823 | if (OpInfo.ConstraintVT != Input.ConstraintVT) { | ||||||||||
4824 | std::pair<unsigned, const TargetRegisterClass *> MatchRC = | ||||||||||
4825 | getRegForInlineAsmConstraint(TRI, OpInfo.ConstraintCode, | ||||||||||
4826 | OpInfo.ConstraintVT); | ||||||||||
4827 | std::pair<unsigned, const TargetRegisterClass *> InputRC = | ||||||||||
4828 | getRegForInlineAsmConstraint(TRI, Input.ConstraintCode, | ||||||||||
4829 | Input.ConstraintVT); | ||||||||||
4830 | if ((OpInfo.ConstraintVT.isInteger() != | ||||||||||
4831 | Input.ConstraintVT.isInteger()) || | ||||||||||
4832 | (MatchRC.second != InputRC.second)) { | ||||||||||
4833 | report_fatal_error("Unsupported asm: input constraint" | ||||||||||
4834 | " with a matching output constraint of" | ||||||||||
4835 | " incompatible type!"); | ||||||||||
4836 | } | ||||||||||
4837 | } | ||||||||||
4838 | } | ||||||||||
4839 | } | ||||||||||
4840 | |||||||||||
4841 | return ConstraintOperands; | ||||||||||
4842 | } | ||||||||||
4843 | |||||||||||
4844 | /// Return an integer indicating how general CT is. | ||||||||||
4845 | static unsigned getConstraintGenerality(TargetLowering::ConstraintType CT) { | ||||||||||
4846 | switch (CT) { | ||||||||||
4847 | case TargetLowering::C_Immediate: | ||||||||||
4848 | case TargetLowering::C_Other: | ||||||||||
4849 | case TargetLowering::C_Unknown: | ||||||||||
4850 | return 0; | ||||||||||
4851 | case TargetLowering::C_Register: | ||||||||||
4852 | return 1; | ||||||||||
4853 | case TargetLowering::C_RegisterClass: | ||||||||||
4854 | return 2; | ||||||||||
4855 | case TargetLowering::C_Memory: | ||||||||||
4856 | return 3; | ||||||||||
4857 | } | ||||||||||
4858 | llvm_unreachable("Invalid constraint type")::llvm::llvm_unreachable_internal("Invalid constraint type", "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 4858); | ||||||||||
4859 | } | ||||||||||
4860 | |||||||||||
4861 | /// Examine constraint type and operand type and determine a weight value. | ||||||||||
4862 | /// This object must already have been set up with the operand type | ||||||||||
4863 | /// and the current alternative constraint selected. | ||||||||||
4864 | TargetLowering::ConstraintWeight | ||||||||||
4865 | TargetLowering::getMultipleConstraintMatchWeight( | ||||||||||
4866 | AsmOperandInfo &info, int maIndex) const { | ||||||||||
4867 | InlineAsm::ConstraintCodeVector *rCodes; | ||||||||||
4868 | if (maIndex >= (int)info.multipleAlternatives.size()) | ||||||||||
4869 | rCodes = &info.Codes; | ||||||||||
4870 | else | ||||||||||
4871 | rCodes = &info.multipleAlternatives[maIndex].Codes; | ||||||||||
4872 | ConstraintWeight BestWeight = CW_Invalid; | ||||||||||
4873 | |||||||||||
4874 | // Loop over the options, keeping track of the most general one. | ||||||||||
4875 | for (unsigned i = 0, e = rCodes->size(); i != e; ++i) { | ||||||||||
4876 | ConstraintWeight weight = | ||||||||||
4877 | getSingleConstraintMatchWeight(info, (*rCodes)[i].c_str()); | ||||||||||
4878 | if (weight > BestWeight) | ||||||||||
4879 | BestWeight = weight; | ||||||||||
4880 | } | ||||||||||
4881 | |||||||||||
4882 | return BestWeight; | ||||||||||
4883 | } | ||||||||||
4884 | |||||||||||
4885 | /// Examine constraint type and operand type and determine a weight value. | ||||||||||
4886 | /// This object must already have been set up with the operand type | ||||||||||
4887 | /// and the current alternative constraint selected. | ||||||||||
4888 | TargetLowering::ConstraintWeight | ||||||||||
4889 | TargetLowering::getSingleConstraintMatchWeight( | ||||||||||
4890 | AsmOperandInfo &info, const char *constraint) const { | ||||||||||
4891 | ConstraintWeight weight = CW_Invalid; | ||||||||||
4892 | Value *CallOperandVal = info.CallOperandVal; | ||||||||||
4893 | // If we don't have a value, we can't do a match, | ||||||||||
4894 | // but allow it at the lowest weight. | ||||||||||
4895 | if (!CallOperandVal) | ||||||||||
4896 | return CW_Default; | ||||||||||
4897 | // Look at the constraint type. | ||||||||||
4898 | switch (*constraint) { | ||||||||||
4899 | case 'i': // immediate integer. | ||||||||||
4900 | case 'n': // immediate integer with a known value. | ||||||||||
4901 | if (isa<ConstantInt>(CallOperandVal)) | ||||||||||
4902 | weight = CW_Constant; | ||||||||||
4903 | break; | ||||||||||
4904 | case 's': // non-explicit intregal immediate. | ||||||||||
4905 | if (isa<GlobalValue>(CallOperandVal)) | ||||||||||
4906 | weight = CW_Constant; | ||||||||||
4907 | break; | ||||||||||
4908 | case 'E': // immediate float if host format. | ||||||||||
4909 | case 'F': // immediate float. | ||||||||||
4910 | if (isa<ConstantFP>(CallOperandVal)) | ||||||||||
4911 | weight = CW_Constant; | ||||||||||
4912 | break; | ||||||||||
4913 | case '<': // memory operand with autodecrement. | ||||||||||
4914 | case '>': // memory operand with autoincrement. | ||||||||||
4915 | case 'm': // memory operand. | ||||||||||
4916 | case 'o': // offsettable memory operand | ||||||||||
4917 | case 'V': // non-offsettable memory operand | ||||||||||
4918 | weight = CW_Memory; | ||||||||||
4919 | break; | ||||||||||
4920 | case 'r': // general register. | ||||||||||
4921 | case 'g': // general register, memory operand or immediate integer. | ||||||||||
4922 | // note: Clang converts "g" to "imr". | ||||||||||
4923 | if (CallOperandVal->getType()->isIntegerTy()) | ||||||||||
4924 | weight = CW_Register; | ||||||||||
4925 | break; | ||||||||||
4926 | case 'X': // any operand. | ||||||||||
4927 | default: | ||||||||||
4928 | weight = CW_Default; | ||||||||||
4929 | break; | ||||||||||
4930 | } | ||||||||||
4931 | return weight; | ||||||||||
4932 | } | ||||||||||
4933 | |||||||||||
4934 | /// If there are multiple different constraints that we could pick for this | ||||||||||
4935 | /// operand (e.g. "imr") try to pick the 'best' one. | ||||||||||
4936 | /// This is somewhat tricky: constraints fall into four classes: | ||||||||||
4937 | /// Other -> immediates and magic values | ||||||||||
4938 | /// Register -> one specific register | ||||||||||
4939 | /// RegisterClass -> a group of regs | ||||||||||
4940 | /// Memory -> memory | ||||||||||
4941 | /// Ideally, we would pick the most specific constraint possible: if we have | ||||||||||
4942 | /// something that fits into a register, we would pick it. The problem here | ||||||||||
4943 | /// is that if we have something that could either be in a register or in | ||||||||||
4944 | /// memory that use of the register could cause selection of *other* | ||||||||||
4945 | /// operands to fail: they might only succeed if we pick memory. Because of | ||||||||||
4946 | /// this the heuristic we use is: | ||||||||||
4947 | /// | ||||||||||
4948 | /// 1) If there is an 'other' constraint, and if the operand is valid for | ||||||||||
4949 | /// that constraint, use it. This makes us take advantage of 'i' | ||||||||||
4950 | /// constraints when available. | ||||||||||
4951 | /// 2) Otherwise, pick the most general constraint present. This prefers | ||||||||||
4952 | /// 'm' over 'r', for example. | ||||||||||
4953 | /// | ||||||||||
4954 | static void ChooseConstraint(TargetLowering::AsmOperandInfo &OpInfo, | ||||||||||
4955 | const TargetLowering &TLI, | ||||||||||
4956 | SDValue Op, SelectionDAG *DAG) { | ||||||||||
4957 | assert(OpInfo.Codes.size() > 1 && "Doesn't have multiple constraint options")(static_cast <bool> (OpInfo.Codes.size() > 1 && "Doesn't have multiple constraint options") ? void (0) : __assert_fail ("OpInfo.Codes.size() > 1 && \"Doesn't have multiple constraint options\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 4957, __extension__ __PRETTY_FUNCTION__)); | ||||||||||
4958 | unsigned BestIdx = 0; | ||||||||||
4959 | TargetLowering::ConstraintType BestType = TargetLowering::C_Unknown; | ||||||||||
4960 | int BestGenerality = -1; | ||||||||||
4961 | |||||||||||
4962 | // Loop over the options, keeping track of the most general one. | ||||||||||
4963 | for (unsigned i = 0, e = OpInfo.Codes.size(); i != e; ++i) { | ||||||||||
4964 | TargetLowering::ConstraintType CType = | ||||||||||
4965 | TLI.getConstraintType(OpInfo.Codes[i]); | ||||||||||
4966 | |||||||||||
4967 | // Indirect 'other' or 'immediate' constraints are not allowed. | ||||||||||
4968 | if (OpInfo.isIndirect && !(CType == TargetLowering::C_Memory || | ||||||||||
4969 | CType == TargetLowering::C_Register || | ||||||||||
4970 | CType == TargetLowering::C_RegisterClass)) | ||||||||||
4971 | continue; | ||||||||||
4972 | |||||||||||
4973 | // If this is an 'other' or 'immediate' constraint, see if the operand is | ||||||||||
4974 | // valid for it. For example, on X86 we might have an 'rI' constraint. If | ||||||||||
4975 | // the operand is an integer in the range [0..31] we want to use I (saving a | ||||||||||
4976 | // load of a register), otherwise we must use 'r'. | ||||||||||
4977 | if ((CType == TargetLowering::C_Other || | ||||||||||
4978 | CType == TargetLowering::C_Immediate) && Op.getNode()) { | ||||||||||
4979 | assert(OpInfo.Codes[i].size() == 1 &&(static_cast <bool> (OpInfo.Codes[i].size() == 1 && "Unhandled multi-letter 'other' constraint") ? void (0) : __assert_fail ("OpInfo.Codes[i].size() == 1 && \"Unhandled multi-letter 'other' constraint\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 4980, __extension__ __PRETTY_FUNCTION__)) | ||||||||||
4980 | "Unhandled multi-letter 'other' constraint")(static_cast <bool> (OpInfo.Codes[i].size() == 1 && "Unhandled multi-letter 'other' constraint") ? void (0) : __assert_fail ("OpInfo.Codes[i].size() == 1 && \"Unhandled multi-letter 'other' constraint\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 4980, __extension__ __PRETTY_FUNCTION__)); | ||||||||||
4981 | std::vector<SDValue> ResultOps; | ||||||||||
4982 | TLI.LowerAsmOperandForConstraint(Op, OpInfo.Codes[i], | ||||||||||
4983 | ResultOps, *DAG); | ||||||||||
4984 | if (!ResultOps.empty()) { | ||||||||||
4985 | BestType = CType; | ||||||||||
4986 | BestIdx = i; | ||||||||||
4987 | break; | ||||||||||
4988 | } | ||||||||||
4989 | } | ||||||||||
4990 | |||||||||||
4991 | // Things with matching constraints can only be registers, per gcc | ||||||||||
4992 | // documentation. This mainly affects "g" constraints. | ||||||||||
4993 | if (CType == TargetLowering::C_Memory && OpInfo.hasMatchingInput()) | ||||||||||
4994 | continue; | ||||||||||
4995 | |||||||||||
4996 | // This constraint letter is more general than the previous one, use it. | ||||||||||
4997 | int Generality = getConstraintGenerality(CType); | ||||||||||
4998 | if (Generality > BestGenerality) { | ||||||||||
4999 | BestType = CType; | ||||||||||
5000 | BestIdx = i; | ||||||||||
5001 | BestGenerality = Generality; | ||||||||||
5002 | } | ||||||||||
5003 | } | ||||||||||
5004 | |||||||||||
5005 | OpInfo.ConstraintCode = OpInfo.Codes[BestIdx]; | ||||||||||
5006 | OpInfo.ConstraintType = BestType; | ||||||||||
5007 | } | ||||||||||
5008 | |||||||||||
5009 | /// Determines the constraint code and constraint type to use for the specific | ||||||||||
5010 | /// AsmOperandInfo, setting OpInfo.ConstraintCode and OpInfo.ConstraintType. | ||||||||||
5011 | void TargetLowering::ComputeConstraintToUse(AsmOperandInfo &OpInfo, | ||||||||||
5012 | SDValue Op, | ||||||||||
5013 | SelectionDAG *DAG) const { | ||||||||||
5014 | assert(!OpInfo.Codes.empty() && "Must have at least one constraint")(static_cast <bool> (!OpInfo.Codes.empty() && "Must have at least one constraint" ) ? void (0) : __assert_fail ("!OpInfo.Codes.empty() && \"Must have at least one constraint\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 5014, __extension__ __PRETTY_FUNCTION__)); | ||||||||||
5015 | |||||||||||
5016 | // Single-letter constraints ('r') are very common. | ||||||||||
5017 | if (OpInfo.Codes.size() == 1) { | ||||||||||
5018 | OpInfo.ConstraintCode = OpInfo.Codes[0]; | ||||||||||
5019 | OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode); | ||||||||||
5020 | } else { | ||||||||||
5021 | ChooseConstraint(OpInfo, *this, Op, DAG); | ||||||||||
5022 | } | ||||||||||
5023 | |||||||||||
5024 | // 'X' matches anything. | ||||||||||
5025 | if (OpInfo.ConstraintCode == "X" && OpInfo.CallOperandVal) { | ||||||||||
5026 | // Labels and constants are handled elsewhere ('X' is the only thing | ||||||||||
5027 | // that matches labels). For Functions, the type here is the type of | ||||||||||
5028 | // the result, which is not what we want to look at; leave them alone. | ||||||||||
5029 | Value *v = OpInfo.CallOperandVal; | ||||||||||
5030 | if (isa<BasicBlock>(v) || isa<ConstantInt>(v) || isa<Function>(v)) { | ||||||||||
5031 | OpInfo.CallOperandVal = v; | ||||||||||
5032 | return; | ||||||||||
5033 | } | ||||||||||
5034 | |||||||||||
5035 | if (Op.getNode() && Op.getOpcode() == ISD::TargetBlockAddress) | ||||||||||
5036 | return; | ||||||||||
5037 | |||||||||||
5038 | // Otherwise, try to resolve it to something we know about by looking at | ||||||||||
5039 | // the actual operand type. | ||||||||||
5040 | if (const char *Repl = LowerXConstraint(OpInfo.ConstraintVT)) { | ||||||||||
5041 | OpInfo.ConstraintCode = Repl; | ||||||||||
5042 | OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode); | ||||||||||
5043 | } | ||||||||||
5044 | } | ||||||||||
5045 | } | ||||||||||
5046 | |||||||||||
5047 | /// Given an exact SDIV by a constant, create a multiplication | ||||||||||
5048 | /// with the multiplicative inverse of the constant. | ||||||||||
5049 | static SDValue BuildExactSDIV(const TargetLowering &TLI, SDNode *N, | ||||||||||
5050 | const SDLoc &dl, SelectionDAG &DAG, | ||||||||||
5051 | SmallVectorImpl<SDNode *> &Created) { | ||||||||||
5052 | SDValue Op0 = N->getOperand(0); | ||||||||||
5053 | SDValue Op1 = N->getOperand(1); | ||||||||||
5054 | EVT VT = N->getValueType(0); | ||||||||||
5055 | EVT SVT = VT.getScalarType(); | ||||||||||
5056 | EVT ShVT = TLI.getShiftAmountTy(VT, DAG.getDataLayout()); | ||||||||||
5057 | EVT ShSVT = ShVT.getScalarType(); | ||||||||||
5058 | |||||||||||
5059 | bool UseSRA = false; | ||||||||||
5060 | SmallVector<SDValue, 16> Shifts, Factors; | ||||||||||
5061 | |||||||||||
5062 | auto BuildSDIVPattern = [&](ConstantSDNode *C) { | ||||||||||
5063 | if (C->isZero()) | ||||||||||
5064 | return false; | ||||||||||
5065 | APInt Divisor = C->getAPIntValue(); | ||||||||||
5066 | unsigned Shift = Divisor.countTrailingZeros(); | ||||||||||
5067 | if (Shift) { | ||||||||||
5068 | Divisor.ashrInPlace(Shift); | ||||||||||
5069 | UseSRA = true; | ||||||||||
5070 | } | ||||||||||
5071 | // Calculate the multiplicative inverse, using Newton's method. | ||||||||||
5072 | APInt t; | ||||||||||
5073 | APInt Factor = Divisor; | ||||||||||
5074 | while ((t = Divisor * Factor) != 1) | ||||||||||
5075 | Factor *= APInt(Divisor.getBitWidth(), 2) - t; | ||||||||||
5076 | Shifts.push_back(DAG.getConstant(Shift, dl, ShSVT)); | ||||||||||
5077 | Factors.push_back(DAG.getConstant(Factor, dl, SVT)); | ||||||||||
5078 | return true; | ||||||||||
5079 | }; | ||||||||||
5080 | |||||||||||
5081 | // Collect all magic values from the build vector. | ||||||||||
5082 | if (!ISD::matchUnaryPredicate(Op1, BuildSDIVPattern)) | ||||||||||
5083 | return SDValue(); | ||||||||||
5084 | |||||||||||
5085 | SDValue Shift, Factor; | ||||||||||
5086 | if (Op1.getOpcode() == ISD::BUILD_VECTOR) { | ||||||||||
5087 | Shift = DAG.getBuildVector(ShVT, dl, Shifts); | ||||||||||
5088 | Factor = DAG.getBuildVector(VT, dl, Factors); | ||||||||||
5089 | } else if (Op1.getOpcode() == ISD::SPLAT_VECTOR) { | ||||||||||
5090 | assert(Shifts.size() == 1 && Factors.size() == 1 &&(static_cast <bool> (Shifts.size() == 1 && Factors .size() == 1 && "Expected matchUnaryPredicate to return one element for scalable " "vectors") ? void (0) : __assert_fail ("Shifts.size() == 1 && Factors.size() == 1 && \"Expected matchUnaryPredicate to return one element for scalable \" \"vectors\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 5092, __extension__ __PRETTY_FUNCTION__)) | ||||||||||
5091 | "Expected matchUnaryPredicate to return one element for scalable "(static_cast <bool> (Shifts.size() == 1 && Factors .size() == 1 && "Expected matchUnaryPredicate to return one element for scalable " "vectors") ? void (0) : __assert_fail ("Shifts.size() == 1 && Factors.size() == 1 && \"Expected matchUnaryPredicate to return one element for scalable \" \"vectors\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 5092, __extension__ __PRETTY_FUNCTION__)) | ||||||||||
5092 | "vectors")(static_cast <bool> (Shifts.size() == 1 && Factors .size() == 1 && "Expected matchUnaryPredicate to return one element for scalable " "vectors") ? void (0) : __assert_fail ("Shifts.size() == 1 && Factors.size() == 1 && \"Expected matchUnaryPredicate to return one element for scalable \" \"vectors\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 5092, __extension__ __PRETTY_FUNCTION__)); | ||||||||||
5093 | Shift = DAG.getSplatVector(ShVT, dl, Shifts[0]); | ||||||||||
5094 | Factor = DAG.getSplatVector(VT, dl, Factors[0]); | ||||||||||
5095 | } else { | ||||||||||
5096 | assert(isa<ConstantSDNode>(Op1) && "Expected a constant")(static_cast <bool> (isa<ConstantSDNode>(Op1) && "Expected a constant") ? void (0) : __assert_fail ("isa<ConstantSDNode>(Op1) && \"Expected a constant\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 5096, __extension__ __PRETTY_FUNCTION__)); | ||||||||||
5097 | Shift = Shifts[0]; | ||||||||||
5098 | Factor = Factors[0]; | ||||||||||
5099 | } | ||||||||||
5100 | |||||||||||
5101 | SDValue Res = Op0; | ||||||||||
5102 | |||||||||||
5103 | // Shift the value upfront if it is even, so the LSB is one. | ||||||||||
5104 | if (UseSRA) { | ||||||||||
5105 | // TODO: For UDIV use SRL instead of SRA. | ||||||||||
5106 | SDNodeFlags Flags; | ||||||||||
5107 | Flags.setExact(true); | ||||||||||
5108 | Res = DAG.getNode(ISD::SRA, dl, VT, Res, Shift, Flags); | ||||||||||
5109 | Created.push_back(Res.getNode()); | ||||||||||
5110 | } | ||||||||||
5111 | |||||||||||
5112 | return DAG.getNode(ISD::MUL, dl, VT, Res, Factor); | ||||||||||
5113 | } | ||||||||||
5114 | |||||||||||
5115 | SDValue TargetLowering::BuildSDIVPow2(SDNode *N, const APInt &Divisor, | ||||||||||
5116 | SelectionDAG &DAG, | ||||||||||
5117 | SmallVectorImpl<SDNode *> &Created) const { | ||||||||||
5118 | AttributeList Attr = DAG.getMachineFunction().getFunction().getAttributes(); | ||||||||||
5119 | const TargetLowering &TLI = DAG.getTargetLoweringInfo(); | ||||||||||
5120 | if (TLI.isIntDivCheap(N->getValueType(0), Attr)) | ||||||||||
5121 | return SDValue(N, 0); // Lower SDIV as SDIV | ||||||||||
5122 | return SDValue(); | ||||||||||
5123 | } | ||||||||||
5124 | |||||||||||
5125 | /// Given an ISD::SDIV node expressing a divide by constant, | ||||||||||
5126 | /// return a DAG expression to select that will generate the same value by | ||||||||||
5127 | /// multiplying by a magic number. | ||||||||||
5128 | /// Ref: "Hacker's Delight" or "The PowerPC Compiler Writer's Guide". | ||||||||||
5129 | SDValue TargetLowering::BuildSDIV(SDNode *N, SelectionDAG &DAG, | ||||||||||
5130 | bool IsAfterLegalization, | ||||||||||
5131 | SmallVectorImpl<SDNode *> &Created) const { | ||||||||||
5132 | SDLoc dl(N); | ||||||||||
5133 | EVT VT = N->getValueType(0); | ||||||||||
5134 | EVT SVT = VT.getScalarType(); | ||||||||||
5135 | EVT ShVT = getShiftAmountTy(VT, DAG.getDataLayout()); | ||||||||||
5136 | EVT ShSVT = ShVT.getScalarType(); | ||||||||||
5137 | unsigned EltBits = VT.getScalarSizeInBits(); | ||||||||||
5138 | EVT MulVT; | ||||||||||
5139 | |||||||||||
5140 | // Check to see if we can do this. | ||||||||||
5141 | // FIXME: We should be more aggressive here. | ||||||||||
5142 | if (!isTypeLegal(VT)) { | ||||||||||
5143 | // Limit this to simple scalars for now. | ||||||||||
5144 | if (VT.isVector() || !VT.isSimple()) | ||||||||||
5145 | return SDValue(); | ||||||||||
5146 | |||||||||||
5147 | // If this type will be promoted to a large enough type with a legal | ||||||||||
5148 | // multiply operation, we can go ahead and do this transform. | ||||||||||
5149 | if (getTypeAction(VT.getSimpleVT()) != TypePromoteInteger) | ||||||||||
5150 | return SDValue(); | ||||||||||
5151 | |||||||||||
5152 | MulVT = getTypeToTransformTo(*DAG.getContext(), VT); | ||||||||||
5153 | if (MulVT.getSizeInBits() < (2 * EltBits) || | ||||||||||
5154 | !isOperationLegal(ISD::MUL, MulVT)) | ||||||||||
5155 | return SDValue(); | ||||||||||
5156 | } | ||||||||||
5157 | |||||||||||
5158 | // If the sdiv has an 'exact' bit we can use a simpler lowering. | ||||||||||
5159 | if (N->getFlags().hasExact()) | ||||||||||
5160 | return BuildExactSDIV(*this, N, dl, DAG, Created); | ||||||||||
5161 | |||||||||||
5162 | SmallVector<SDValue, 16> MagicFactors, Factors, Shifts, ShiftMasks; | ||||||||||
5163 | |||||||||||
5164 | auto BuildSDIVPattern = [&](ConstantSDNode *C) { | ||||||||||
5165 | if (C->isZero()) | ||||||||||
5166 | return false; | ||||||||||
5167 | |||||||||||
5168 | const APInt &Divisor = C->getAPIntValue(); | ||||||||||
5169 | SignedDivisionByConstantInfo magics = SignedDivisionByConstantInfo::get(Divisor); | ||||||||||
5170 | int NumeratorFactor = 0; | ||||||||||
5171 | int ShiftMask = -1; | ||||||||||
5172 | |||||||||||
5173 | if (Divisor.isOne() || Divisor.isAllOnes()) { | ||||||||||
5174 | // If d is +1/-1, we just multiply the numerator by +1/-1. | ||||||||||
5175 | NumeratorFactor = Divisor.getSExtValue(); | ||||||||||
5176 | magics.Magic = 0; | ||||||||||
5177 | magics.ShiftAmount = 0; | ||||||||||
5178 | ShiftMask = 0; | ||||||||||
5179 | } else if (Divisor.isStrictlyPositive() && magics.Magic.isNegative()) { | ||||||||||
5180 | // If d > 0 and m < 0, add the numerator. | ||||||||||
5181 | NumeratorFactor = 1; | ||||||||||
5182 | } else if (Divisor.isNegative() && magics.Magic.isStrictlyPositive()) { | ||||||||||
5183 | // If d < 0 and m > 0, subtract the numerator. | ||||||||||
5184 | NumeratorFactor = -1; | ||||||||||
5185 | } | ||||||||||
5186 | |||||||||||
5187 | MagicFactors.push_back(DAG.getConstant(magics.Magic, dl, SVT)); | ||||||||||
5188 | Factors.push_back(DAG.getConstant(NumeratorFactor, dl, SVT)); | ||||||||||
5189 | Shifts.push_back(DAG.getConstant(magics.ShiftAmount, dl, ShSVT)); | ||||||||||
5190 | ShiftMasks.push_back(DAG.getConstant(ShiftMask, dl, SVT)); | ||||||||||
5191 | return true; | ||||||||||
5192 | }; | ||||||||||
5193 | |||||||||||
5194 | SDValue N0 = N->getOperand(0); | ||||||||||
5195 | SDValue N1 = N->getOperand(1); | ||||||||||
5196 | |||||||||||
5197 | // Collect the shifts / magic values from each element. | ||||||||||
5198 | if (!ISD::matchUnaryPredicate(N1, BuildSDIVPattern)) | ||||||||||
5199 | return SDValue(); | ||||||||||
5200 | |||||||||||
5201 | SDValue MagicFactor, Factor, Shift, ShiftMask; | ||||||||||
5202 | if (N1.getOpcode() == ISD::BUILD_VECTOR) { | ||||||||||
5203 | MagicFactor = DAG.getBuildVector(VT, dl, MagicFactors); | ||||||||||
5204 | Factor = DAG.getBuildVector(VT, dl, Factors); | ||||||||||
5205 | Shift = DAG.getBuildVector(ShVT, dl, Shifts); | ||||||||||
5206 | ShiftMask = DAG.getBuildVector(VT, dl, ShiftMasks); | ||||||||||
5207 | } else if (N1.getOpcode() == ISD::SPLAT_VECTOR) { | ||||||||||
5208 | assert(MagicFactors.size() == 1 && Factors.size() == 1 &&(static_cast <bool> (MagicFactors.size() == 1 && Factors.size() == 1 && Shifts.size() == 1 && ShiftMasks.size() == 1 && "Expected matchUnaryPredicate to return one element for scalable " "vectors") ? void (0) : __assert_fail ("MagicFactors.size() == 1 && Factors.size() == 1 && Shifts.size() == 1 && ShiftMasks.size() == 1 && \"Expected matchUnaryPredicate to return one element for scalable \" \"vectors\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 5211, __extension__ __PRETTY_FUNCTION__)) | ||||||||||
5209 | Shifts.size() == 1 && ShiftMasks.size() == 1 &&(static_cast <bool> (MagicFactors.size() == 1 && Factors.size() == 1 && Shifts.size() == 1 && ShiftMasks.size() == 1 && "Expected matchUnaryPredicate to return one element for scalable " "vectors") ? void (0) : __assert_fail ("MagicFactors.size() == 1 && Factors.size() == 1 && Shifts.size() == 1 && ShiftMasks.size() == 1 && \"Expected matchUnaryPredicate to return one element for scalable \" \"vectors\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 5211, __extension__ __PRETTY_FUNCTION__)) | ||||||||||
5210 | "Expected matchUnaryPredicate to return one element for scalable "(static_cast <bool> (MagicFactors.size() == 1 && Factors.size() == 1 && Shifts.size() == 1 && ShiftMasks.size() == 1 && "Expected matchUnaryPredicate to return one element for scalable " "vectors") ? void (0) : __assert_fail ("MagicFactors.size() == 1 && Factors.size() == 1 && Shifts.size() == 1 && ShiftMasks.size() == 1 && \"Expected matchUnaryPredicate to return one element for scalable \" \"vectors\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 5211, __extension__ __PRETTY_FUNCTION__)) | ||||||||||
5211 | "vectors")(static_cast <bool> (MagicFactors.size() == 1 && Factors.size() == 1 && Shifts.size() == 1 && ShiftMasks.size() == 1 && "Expected matchUnaryPredicate to return one element for scalable " "vectors") ? void (0) : __assert_fail ("MagicFactors.size() == 1 && Factors.size() == 1 && Shifts.size() == 1 && ShiftMasks.size() == 1 && \"Expected matchUnaryPredicate to return one element for scalable \" \"vectors\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 5211, __extension__ __PRETTY_FUNCTION__)); | ||||||||||
5212 | MagicFactor = DAG.getSplatVector(VT, dl, MagicFactors[0]); | ||||||||||
5213 | Factor = DAG.getSplatVector(VT, dl, Factors[0]); | ||||||||||
5214 | Shift = DAG.getSplatVector(ShVT, dl, Shifts[0]); | ||||||||||
5215 | ShiftMask = DAG.getSplatVector(VT, dl, ShiftMasks[0]); | ||||||||||
5216 | } else { | ||||||||||
5217 | assert(isa<ConstantSDNode>(N1) && "Expected a constant")(static_cast <bool> (isa<ConstantSDNode>(N1) && "Expected a constant") ? void (0) : __assert_fail ("isa<ConstantSDNode>(N1) && \"Expected a constant\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 5217, __extension__ __PRETTY_FUNCTION__)); | ||||||||||
5218 | MagicFactor = MagicFactors[0]; | ||||||||||
5219 | Factor = Factors[0]; | ||||||||||
5220 | Shift = Shifts[0]; | ||||||||||
5221 | ShiftMask = ShiftMasks[0]; | ||||||||||
5222 | } | ||||||||||
5223 | |||||||||||
5224 | // Multiply the numerator (operand 0) by the magic value. | ||||||||||
5225 | // FIXME: We should support doing a MUL in a wider type. | ||||||||||
5226 | auto GetMULHS = [&](SDValue X, SDValue Y) { | ||||||||||
5227 | // If the type isn't legal, use a wider mul of the the type calculated | ||||||||||
5228 | // earlier. | ||||||||||
5229 | if (!isTypeLegal(VT)) { | ||||||||||
5230 | X = DAG.getNode(ISD::SIGN_EXTEND, dl, MulVT, X); | ||||||||||
5231 | Y = DAG.getNode(ISD::SIGN_EXTEND, dl, MulVT, Y); | ||||||||||
5232 | Y = DAG.getNode(ISD::MUL, dl, MulVT, X, Y); | ||||||||||
5233 | Y = DAG.getNode(ISD::SRL, dl, MulVT, Y, | ||||||||||
5234 | DAG.getShiftAmountConstant(EltBits, MulVT, dl)); | ||||||||||
5235 | return DAG.getNode(ISD::TRUNCATE, dl, VT, Y); | ||||||||||
5236 | } | ||||||||||
5237 | |||||||||||
5238 | if (isOperationLegalOrCustom(ISD::MULHS, VT, IsAfterLegalization)) | ||||||||||
5239 | return DAG.getNode(ISD::MULHS, dl, VT, X, Y); | ||||||||||
5240 | if (isOperationLegalOrCustom(ISD::SMUL_LOHI, VT, IsAfterLegalization)) { | ||||||||||
5241 | SDValue LoHi = | ||||||||||
5242 | DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(VT, VT), X, Y); | ||||||||||
5243 | return SDValue(LoHi.getNode(), 1); | ||||||||||
5244 | } | ||||||||||
5245 | return SDValue(); | ||||||||||
5246 | }; | ||||||||||
5247 | |||||||||||
5248 | SDValue Q = GetMULHS(N0, MagicFactor); | ||||||||||
5249 | if (!Q) | ||||||||||
5250 | return SDValue(); | ||||||||||
5251 | |||||||||||
5252 | Created.push_back(Q.getNode()); | ||||||||||
5253 | |||||||||||
5254 | // (Optionally) Add/subtract the numerator using Factor. | ||||||||||
5255 | Factor = DAG.getNode(ISD::MUL, dl, VT, N0, Factor); | ||||||||||
5256 | Created.push_back(Factor.getNode()); | ||||||||||
5257 | Q = DAG.getNode(ISD::ADD, dl, VT, Q, Factor); | ||||||||||
5258 | Created.push_back(Q.getNode()); | ||||||||||
5259 | |||||||||||
5260 | // Shift right algebraic by shift value. | ||||||||||
5261 | Q = DAG.getNode(ISD::SRA, dl, VT, Q, Shift); | ||||||||||
5262 | Created.push_back(Q.getNode()); | ||||||||||
5263 | |||||||||||
5264 | // Extract the sign bit, mask it and add it to the quotient. | ||||||||||
5265 | SDValue SignShift = DAG.getConstant(EltBits - 1, dl, ShVT); | ||||||||||
5266 | SDValue T = DAG.getNode(ISD::SRL, dl, VT, Q, SignShift); | ||||||||||
5267 | Created.push_back(T.getNode()); | ||||||||||
5268 | T = DAG.getNode(ISD::AND, dl, VT, T, ShiftMask); | ||||||||||
5269 | Created.push_back(T.getNode()); | ||||||||||
5270 | return DAG.getNode(ISD::ADD, dl, VT, Q, T); | ||||||||||
5271 | } | ||||||||||
5272 | |||||||||||
5273 | /// Given an ISD::UDIV node expressing a divide by constant, | ||||||||||
5274 | /// return a DAG expression to select that will generate the same value by | ||||||||||
5275 | /// multiplying by a magic number. | ||||||||||
5276 | /// Ref: "Hacker's Delight" or "The PowerPC Compiler Writer's Guide". | ||||||||||
5277 | SDValue TargetLowering::BuildUDIV(SDNode *N, SelectionDAG &DAG, | ||||||||||
5278 | bool IsAfterLegalization, | ||||||||||
5279 | SmallVectorImpl<SDNode *> &Created) const { | ||||||||||
5280 | SDLoc dl(N); | ||||||||||
5281 | EVT VT = N->getValueType(0); | ||||||||||
5282 | EVT SVT = VT.getScalarType(); | ||||||||||
5283 | EVT ShVT = getShiftAmountTy(VT, DAG.getDataLayout()); | ||||||||||
5284 | EVT ShSVT = ShVT.getScalarType(); | ||||||||||
5285 | unsigned EltBits = VT.getScalarSizeInBits(); | ||||||||||
5286 | EVT MulVT; | ||||||||||
5287 | |||||||||||
5288 | // Check to see if we can do this. | ||||||||||
5289 | // FIXME: We should be more aggressive here. | ||||||||||
5290 | if (!isTypeLegal(VT)) { | ||||||||||
5291 | // Limit this to simple scalars for now. | ||||||||||
5292 | if (VT.isVector() || !VT.isSimple()) | ||||||||||
5293 | return SDValue(); | ||||||||||
5294 | |||||||||||
5295 | // If this type will be promoted to a large enough type with a legal | ||||||||||
5296 | // multiply operation, we can go ahead and do this transform. | ||||||||||
5297 | if (getTypeAction(VT.getSimpleVT()) != TypePromoteInteger) | ||||||||||
5298 | return SDValue(); | ||||||||||
5299 | |||||||||||
5300 | MulVT = getTypeToTransformTo(*DAG.getContext(), VT); | ||||||||||
5301 | if (MulVT.getSizeInBits() < (2 * EltBits) || | ||||||||||
5302 | !isOperationLegal(ISD::MUL, MulVT)) | ||||||||||
5303 | return SDValue(); | ||||||||||
5304 | } | ||||||||||
5305 | |||||||||||
5306 | bool UseNPQ = false; | ||||||||||
5307 | SmallVector<SDValue, 16> PreShifts, PostShifts, MagicFactors, NPQFactors; | ||||||||||
5308 | |||||||||||
5309 | auto BuildUDIVPattern = [&](ConstantSDNode *C) { | ||||||||||
5310 | if (C->isZero()) | ||||||||||
5311 | return false; | ||||||||||
5312 | // FIXME: We should use a narrower constant when the upper | ||||||||||
5313 | // bits are known to be zero. | ||||||||||
5314 | const APInt& Divisor = C->getAPIntValue(); | ||||||||||
5315 | UnsignedDivisonByConstantInfo magics = UnsignedDivisonByConstantInfo::get(Divisor); | ||||||||||
5316 | unsigned PreShift = 0, PostShift = 0; | ||||||||||
5317 | |||||||||||
5318 | // If the divisor is even, we can avoid using the expensive fixup by | ||||||||||
5319 | // shifting the divided value upfront. | ||||||||||
5320 | if (magics.IsAdd != 0 && !Divisor[0]) { | ||||||||||
5321 | PreShift = Divisor.countTrailingZeros(); | ||||||||||
5322 | // Get magic number for the shifted divisor. | ||||||||||
5323 | magics = UnsignedDivisonByConstantInfo::get(Divisor.lshr(PreShift), PreShift); | ||||||||||
5324 | assert(magics.IsAdd == 0 && "Should use cheap fixup now")(static_cast <bool> (magics.IsAdd == 0 && "Should use cheap fixup now" ) ? void (0) : __assert_fail ("magics.IsAdd == 0 && \"Should use cheap fixup now\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 5324, __extension__ __PRETTY_FUNCTION__)); | ||||||||||
5325 | } | ||||||||||
5326 | |||||||||||
5327 | APInt Magic = magics.Magic; | ||||||||||
5328 | |||||||||||
5329 | unsigned SelNPQ; | ||||||||||
5330 | if (magics.IsAdd == 0 || Divisor.isOne()) { | ||||||||||
5331 | assert(magics.ShiftAmount < Divisor.getBitWidth() &&(static_cast <bool> (magics.ShiftAmount < Divisor.getBitWidth () && "We shouldn't generate an undefined shift!") ? void (0) : __assert_fail ("magics.ShiftAmount < Divisor.getBitWidth() && \"We shouldn't generate an undefined shift!\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 5332, __extension__ __PRETTY_FUNCTION__)) | ||||||||||
5332 | "We shouldn't generate an undefined shift!")(static_cast <bool> (magics.ShiftAmount < Divisor.getBitWidth () && "We shouldn't generate an undefined shift!") ? void (0) : __assert_fail ("magics.ShiftAmount < Divisor.getBitWidth() && \"We shouldn't generate an undefined shift!\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 5332, __extension__ __PRETTY_FUNCTION__)); | ||||||||||
5333 | PostShift = magics.ShiftAmount; | ||||||||||
5334 | SelNPQ = false; | ||||||||||
5335 | } else { | ||||||||||
5336 | PostShift = magics.ShiftAmount - 1; | ||||||||||
5337 | SelNPQ = true; | ||||||||||
5338 | } | ||||||||||
5339 | |||||||||||
5340 | PreShifts.push_back(DAG.getConstant(PreShift, dl, ShSVT)); | ||||||||||
5341 | MagicFactors.push_back(DAG.getConstant(Magic, dl, SVT)); | ||||||||||
5342 | NPQFactors.push_back( | ||||||||||
5343 | DAG.getConstant(SelNPQ ? APInt::getOneBitSet(EltBits, EltBits - 1) | ||||||||||
5344 | : APInt::getZero(EltBits), | ||||||||||
5345 | dl, SVT)); | ||||||||||
5346 | PostShifts.push_back(DAG.getConstant(PostShift, dl, ShSVT)); | ||||||||||
5347 | UseNPQ |= SelNPQ; | ||||||||||
5348 | return true; | ||||||||||
5349 | }; | ||||||||||
5350 | |||||||||||
5351 | SDValue N0 = N->getOperand(0); | ||||||||||
5352 | SDValue N1 = N->getOperand(1); | ||||||||||
5353 | |||||||||||
5354 | // Collect the shifts/magic values from each element. | ||||||||||
5355 | if (!ISD::matchUnaryPredicate(N1, BuildUDIVPattern)) | ||||||||||
5356 | return SDValue(); | ||||||||||
5357 | |||||||||||
5358 | SDValue PreShift, PostShift, MagicFactor, NPQFactor; | ||||||||||
5359 | if (N1.getOpcode() == ISD::BUILD_VECTOR) { | ||||||||||
5360 | PreShift = DAG.getBuildVector(ShVT, dl, PreShifts); | ||||||||||
5361 | MagicFactor = DAG.getBuildVector(VT, dl, MagicFactors); | ||||||||||
5362 | NPQFactor = DAG.getBuildVector(VT, dl, NPQFactors); | ||||||||||
5363 | PostShift = DAG.getBuildVector(ShVT, dl, PostShifts); | ||||||||||
5364 | } else if (N1.getOpcode() == ISD::SPLAT_VECTOR) { | ||||||||||
5365 | assert(PreShifts.size() == 1 && MagicFactors.size() == 1 &&(static_cast <bool> (PreShifts.size() == 1 && MagicFactors .size() == 1 && NPQFactors.size() == 1 && PostShifts .size() == 1 && "Expected matchUnaryPredicate to return one for scalable vectors" ) ? void (0) : __assert_fail ("PreShifts.size() == 1 && MagicFactors.size() == 1 && NPQFactors.size() == 1 && PostShifts.size() == 1 && \"Expected matchUnaryPredicate to return one for scalable vectors\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 5367, __extension__ __PRETTY_FUNCTION__)) | ||||||||||
5366 | NPQFactors.size() == 1 && PostShifts.size() == 1 &&(static_cast <bool> (PreShifts.size() == 1 && MagicFactors .size() == 1 && NPQFactors.size() == 1 && PostShifts .size() == 1 && "Expected matchUnaryPredicate to return one for scalable vectors" ) ? void (0) : __assert_fail ("PreShifts.size() == 1 && MagicFactors.size() == 1 && NPQFactors.size() == 1 && PostShifts.size() == 1 && \"Expected matchUnaryPredicate to return one for scalable vectors\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 5367, __extension__ __PRETTY_FUNCTION__)) | ||||||||||
5367 | "Expected matchUnaryPredicate to return one for scalable vectors")(static_cast <bool> (PreShifts.size() == 1 && MagicFactors .size() == 1 && NPQFactors.size() == 1 && PostShifts .size() == 1 && "Expected matchUnaryPredicate to return one for scalable vectors" ) ? void (0) : __assert_fail ("PreShifts.size() == 1 && MagicFactors.size() == 1 && NPQFactors.size() == 1 && PostShifts.size() == 1 && \"Expected matchUnaryPredicate to return one for scalable vectors\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 5367, __extension__ __PRETTY_FUNCTION__)); | ||||||||||
5368 | PreShift = DAG.getSplatVector(ShVT, dl, PreShifts[0]); | ||||||||||
5369 | MagicFactor = DAG.getSplatVector(VT, dl, MagicFactors[0]); | ||||||||||
5370 | NPQFactor = DAG.getSplatVector(VT, dl, NPQFactors[0]); | ||||||||||
5371 | PostShift = DAG.getSplatVector(ShVT, dl, PostShifts[0]); | ||||||||||
5372 | } else { | ||||||||||
5373 | assert(isa<ConstantSDNode>(N1) && "Expected a constant")(static_cast <bool> (isa<ConstantSDNode>(N1) && "Expected a constant") ? void (0) : __assert_fail ("isa<ConstantSDNode>(N1) && \"Expected a constant\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 5373, __extension__ __PRETTY_FUNCTION__)); | ||||||||||
5374 | PreShift = PreShifts[0]; | ||||||||||
5375 | MagicFactor = MagicFactors[0]; | ||||||||||
5376 | PostShift = PostShifts[0]; | ||||||||||
5377 | } | ||||||||||
5378 | |||||||||||
5379 | SDValue Q = N0; | ||||||||||
5380 | Q = DAG.getNode(ISD::SRL, dl, VT, Q, PreShift); | ||||||||||
5381 | Created.push_back(Q.getNode()); | ||||||||||
5382 | |||||||||||
5383 | // FIXME: We should support doing a MUL in a wider type. | ||||||||||
5384 | auto GetMULHU = [&](SDValue X, SDValue Y) { | ||||||||||
5385 | // If the type isn't legal, use a wider mul of the the type calculated | ||||||||||
5386 | // earlier. | ||||||||||
5387 | if (!isTypeLegal(VT)) { | ||||||||||
5388 | X = DAG.getNode(ISD::ZERO_EXTEND, dl, MulVT, X); | ||||||||||
5389 | Y = DAG.getNode(ISD::ZERO_EXTEND, dl, MulVT, Y); | ||||||||||
5390 | Y = DAG.getNode(ISD::MUL, dl, MulVT, X, Y); | ||||||||||
5391 | Y = DAG.getNode(ISD::SRL, dl, MulVT, Y, | ||||||||||
5392 | DAG.getShiftAmountConstant(EltBits, MulVT, dl)); | ||||||||||
5393 | return DAG.getNode(ISD::TRUNCATE, dl, VT, Y); | ||||||||||
5394 | } | ||||||||||
5395 | |||||||||||
5396 | if (isOperationLegalOrCustom(ISD::MULHU, VT, IsAfterLegalization)) | ||||||||||
5397 | return DAG.getNode(ISD::MULHU, dl, VT, X, Y); | ||||||||||
5398 | if (isOperationLegalOrCustom(ISD::UMUL_LOHI, VT, IsAfterLegalization)) { | ||||||||||
5399 | SDValue LoHi = | ||||||||||
5400 | DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(VT, VT), X, Y); | ||||||||||
5401 | return SDValue(LoHi.getNode(), 1); | ||||||||||
5402 | } | ||||||||||
5403 | return SDValue(); // No mulhu or equivalent | ||||||||||
5404 | }; | ||||||||||
5405 | |||||||||||
5406 | // Multiply the numerator (operand 0) by the magic value. | ||||||||||
5407 | Q = GetMULHU(Q, MagicFactor); | ||||||||||
5408 | if (!Q) | ||||||||||
5409 | return SDValue(); | ||||||||||
5410 | |||||||||||
5411 | Created.push_back(Q.getNode()); | ||||||||||
5412 | |||||||||||
5413 | if (UseNPQ) { | ||||||||||
5414 | SDValue NPQ = DAG.getNode(ISD::SUB, dl, VT, N0, Q); | ||||||||||
5415 | Created.push_back(NPQ.getNode()); | ||||||||||
5416 | |||||||||||
5417 | // For vectors we might have a mix of non-NPQ/NPQ paths, so use | ||||||||||
5418 | // MULHU to act as a SRL-by-1 for NPQ, else multiply by zero. | ||||||||||
5419 | if (VT.isVector()) | ||||||||||
5420 | NPQ = GetMULHU(NPQ, NPQFactor); | ||||||||||
5421 | else | ||||||||||
5422 | NPQ = DAG.getNode(ISD::SRL, dl, VT, NPQ, DAG.getConstant(1, dl, ShVT)); | ||||||||||
5423 | |||||||||||
5424 | Created.push_back(NPQ.getNode()); | ||||||||||
5425 | |||||||||||
5426 | Q = DAG.getNode(ISD::ADD, dl, VT, NPQ, Q); | ||||||||||
5427 | Created.push_back(Q.getNode()); | ||||||||||
5428 | } | ||||||||||
5429 | |||||||||||
5430 | Q = DAG.getNode(ISD::SRL, dl, VT, Q, PostShift); | ||||||||||
5431 | Created.push_back(Q.getNode()); | ||||||||||
5432 | |||||||||||
5433 | EVT SetCCVT = getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT); | ||||||||||
5434 | |||||||||||
5435 | SDValue One = DAG.getConstant(1, dl, VT); | ||||||||||
5436 | SDValue IsOne = DAG.getSetCC(dl, SetCCVT, N1, One, ISD::SETEQ); | ||||||||||
5437 | return DAG.getSelect(dl, VT, IsOne, N0, Q); | ||||||||||
5438 | } | ||||||||||
5439 | |||||||||||
5440 | /// If all values in Values that *don't* match the predicate are same 'splat' | ||||||||||
5441 | /// value, then replace all values with that splat value. | ||||||||||
5442 | /// Else, if AlternativeReplacement was provided, then replace all values that | ||||||||||
5443 | /// do match predicate with AlternativeReplacement value. | ||||||||||
5444 | static void | ||||||||||
5445 | turnVectorIntoSplatVector(MutableArrayRef<SDValue> Values, | ||||||||||
5446 | std::function<bool(SDValue)> Predicate, | ||||||||||
5447 | SDValue AlternativeReplacement = SDValue()) { | ||||||||||
5448 | SDValue Replacement; | ||||||||||
5449 | // Is there a value for which the Predicate does *NOT* match? What is it? | ||||||||||
5450 | auto SplatValue = llvm::find_if_not(Values, Predicate); | ||||||||||
5451 | if (SplatValue != Values.end()) { | ||||||||||
5452 | // Does Values consist only of SplatValue's and values matching Predicate? | ||||||||||
5453 | if (llvm::all_of(Values, [Predicate, SplatValue](SDValue Value) { | ||||||||||
5454 | return Value == *SplatValue || Predicate(Value); | ||||||||||
5455 | })) // Then we shall replace values matching predicate with SplatValue. | ||||||||||
5456 | Replacement = *SplatValue; | ||||||||||
5457 | } | ||||||||||
5458 | if (!Replacement) { | ||||||||||
5459 | // Oops, we did not find the "baseline" splat value. | ||||||||||
5460 | if (!AlternativeReplacement) | ||||||||||
5461 | return; // Nothing to do. | ||||||||||
5462 | // Let's replace with provided value then. | ||||||||||
5463 | Replacement = AlternativeReplacement; | ||||||||||
5464 | } | ||||||||||
5465 | std::replace_if(Values.begin(), Values.end(), Predicate, Replacement); | ||||||||||
5466 | } | ||||||||||
5467 | |||||||||||
5468 | /// Given an ISD::UREM used only by an ISD::SETEQ or ISD::SETNE | ||||||||||
5469 | /// where the divisor is constant and the comparison target is zero, | ||||||||||
5470 | /// return a DAG expression that will generate the same comparison result | ||||||||||
5471 | /// using only multiplications, additions and shifts/rotations. | ||||||||||
5472 | /// Ref: "Hacker's Delight" 10-17. | ||||||||||
5473 | SDValue TargetLowering::buildUREMEqFold(EVT SETCCVT, SDValue REMNode, | ||||||||||
5474 | SDValue CompTargetNode, | ||||||||||
5475 | ISD::CondCode Cond, | ||||||||||
5476 | DAGCombinerInfo &DCI, | ||||||||||
5477 | const SDLoc &DL) const { | ||||||||||
5478 | SmallVector<SDNode *, 5> Built; | ||||||||||
5479 | if (SDValue Folded = prepareUREMEqFold(SETCCVT, REMNode, CompTargetNode, Cond, | ||||||||||
5480 | DCI, DL, Built)) { | ||||||||||
5481 | for (SDNode *N : Built) | ||||||||||
5482 | DCI.AddToWorklist(N); | ||||||||||
5483 | return Folded; | ||||||||||
5484 | } | ||||||||||
5485 | |||||||||||
5486 | return SDValue(); | ||||||||||
5487 | } | ||||||||||
5488 | |||||||||||
5489 | SDValue | ||||||||||
5490 | TargetLowering::prepareUREMEqFold(EVT SETCCVT, SDValue REMNode, | ||||||||||
5491 | SDValue CompTargetNode, ISD::CondCode Cond, | ||||||||||
5492 | DAGCombinerInfo &DCI, const SDLoc &DL, | ||||||||||
5493 | SmallVectorImpl<SDNode *> &Created) const { | ||||||||||
5494 | // fold (seteq/ne (urem N, D), 0) -> (setule/ugt (rotr (mul N, P), K), Q) | ||||||||||
5495 | // - D must be constant, with D = D0 * 2^K where D0 is odd | ||||||||||
5496 | // - P is the multiplicative inverse of D0 modulo 2^W | ||||||||||
5497 | // - Q = floor(((2^W) - 1) / D) | ||||||||||
5498 | // where W is the width of the common type of N and D. | ||||||||||
5499 | assert((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&(static_cast <bool> ((Cond == ISD::SETEQ || Cond == ISD ::SETNE) && "Only applicable for (in)equality comparisons." ) ? void (0) : __assert_fail ("(Cond == ISD::SETEQ || Cond == ISD::SETNE) && \"Only applicable for (in)equality comparisons.\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 5500, __extension__ __PRETTY_FUNCTION__)) | ||||||||||
5500 | "Only applicable for (in)equality comparisons.")(static_cast <bool> ((Cond == ISD::SETEQ || Cond == ISD ::SETNE) && "Only applicable for (in)equality comparisons." ) ? void (0) : __assert_fail ("(Cond == ISD::SETEQ || Cond == ISD::SETNE) && \"Only applicable for (in)equality comparisons.\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 5500, __extension__ __PRETTY_FUNCTION__)); | ||||||||||
5501 | |||||||||||
5502 | SelectionDAG &DAG = DCI.DAG; | ||||||||||
5503 | |||||||||||
5504 | EVT VT = REMNode.getValueType(); | ||||||||||
5505 | EVT SVT = VT.getScalarType(); | ||||||||||
5506 | EVT ShVT = getShiftAmountTy(VT, DAG.getDataLayout(), !DCI.isBeforeLegalize()); | ||||||||||
5507 | EVT ShSVT = ShVT.getScalarType(); | ||||||||||
5508 | |||||||||||
5509 | // If MUL is unavailable, we cannot proceed in any case. | ||||||||||
5510 | if (!DCI.isBeforeLegalizeOps() && !isOperationLegalOrCustom(ISD::MUL, VT)) | ||||||||||
5511 | return SDValue(); | ||||||||||
5512 | |||||||||||
5513 | bool ComparingWithAllZeros = true; | ||||||||||
5514 | bool AllComparisonsWithNonZerosAreTautological = true; | ||||||||||
5515 | bool HadTautologicalLanes = false; | ||||||||||
5516 | bool AllLanesAreTautological = true; | ||||||||||
5517 | bool HadEvenDivisor = false; | ||||||||||
5518 | bool AllDivisorsArePowerOfTwo = true; | ||||||||||
5519 | bool HadTautologicalInvertedLanes = false; | ||||||||||
5520 | SmallVector<SDValue, 16> PAmts, KAmts, QAmts, IAmts; | ||||||||||
5521 | |||||||||||
5522 | auto BuildUREMPattern = [&](ConstantSDNode *CDiv, ConstantSDNode *CCmp) { | ||||||||||
5523 | // Division by 0 is UB. Leave it to be constant-folded elsewhere. | ||||||||||
5524 | if (CDiv->isZero()) | ||||||||||
5525 | return false; | ||||||||||
5526 | |||||||||||
5527 | const APInt &D = CDiv->getAPIntValue(); | ||||||||||
5528 | const APInt &Cmp = CCmp->getAPIntValue(); | ||||||||||
5529 | |||||||||||
5530 | ComparingWithAllZeros &= Cmp.isZero(); | ||||||||||
5531 | |||||||||||
5532 | // x u% C1` is *always* less than C1. So given `x u% C1 == C2`, | ||||||||||
5533 | // if C2 is not less than C1, the comparison is always false. | ||||||||||
5534 | // But we will only be able to produce the comparison that will give the | ||||||||||
5535 | // opposive tautological answer. So this lane would need to be fixed up. | ||||||||||
5536 | bool TautologicalInvertedLane = D.ule(Cmp); | ||||||||||
5537 | HadTautologicalInvertedLanes |= TautologicalInvertedLane; | ||||||||||
5538 | |||||||||||
5539 | // If all lanes are tautological (either all divisors are ones, or divisor | ||||||||||
5540 | // is not greater than the constant we are comparing with), | ||||||||||
5541 | // we will prefer to avoid the fold. | ||||||||||
5542 | bool TautologicalLane = D.isOne() || TautologicalInvertedLane; | ||||||||||
5543 | HadTautologicalLanes |= TautologicalLane; | ||||||||||
5544 | AllLanesAreTautological &= TautologicalLane; | ||||||||||
5545 | |||||||||||
5546 | // If we are comparing with non-zero, we need'll need to subtract said | ||||||||||
5547 | // comparison value from the LHS. But there is no point in doing that if | ||||||||||
5548 | // every lane where we are comparing with non-zero is tautological.. | ||||||||||
5549 | if (!Cmp.isZero()) | ||||||||||
5550 | AllComparisonsWithNonZerosAreTautological &= TautologicalLane; | ||||||||||
5551 | |||||||||||
5552 | // Decompose D into D0 * 2^K | ||||||||||
5553 | unsigned K = D.countTrailingZeros(); | ||||||||||
5554 | assert((!D.isOne() || (K == 0)) && "For divisor '1' we won't rotate.")(static_cast <bool> ((!D.isOne() || (K == 0)) && "For divisor '1' we won't rotate.") ? void (0) : __assert_fail ("(!D.isOne() || (K == 0)) && \"For divisor '1' we won't rotate.\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 5554, __extension__ __PRETTY_FUNCTION__)); | ||||||||||
5555 | APInt D0 = D.lshr(K); | ||||||||||
5556 | |||||||||||
5557 | // D is even if it has trailing zeros. | ||||||||||
5558 | HadEvenDivisor |= (K != 0); | ||||||||||
5559 | // D is a power-of-two if D0 is one. | ||||||||||
5560 | // If all divisors are power-of-two, we will prefer to avoid the fold. | ||||||||||
5561 | AllDivisorsArePowerOfTwo &= D0.isOne(); | ||||||||||
5562 | |||||||||||
5563 | // P = inv(D0, 2^W) | ||||||||||
5564 | // 2^W requires W + 1 bits, so we have to extend and then truncate. | ||||||||||
5565 | unsigned W = D.getBitWidth(); | ||||||||||
5566 | APInt P = D0.zext(W + 1) | ||||||||||
5567 | .multiplicativeInverse(APInt::getSignedMinValue(W + 1)) | ||||||||||
5568 | .trunc(W); | ||||||||||
5569 | assert(!P.isZero() && "No multiplicative inverse!")(static_cast <bool> (!P.isZero() && "No multiplicative inverse!" ) ? void (0) : __assert_fail ("!P.isZero() && \"No multiplicative inverse!\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 5569, __extension__ __PRETTY_FUNCTION__)); // unreachable | ||||||||||
5570 | assert((D0 * P).isOne() && "Multiplicative inverse sanity check.")(static_cast <bool> ((D0 * P).isOne() && "Multiplicative inverse sanity check." ) ? void (0) : __assert_fail ("(D0 * P).isOne() && \"Multiplicative inverse sanity check.\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 5570, __extension__ __PRETTY_FUNCTION__)); | ||||||||||
5571 | |||||||||||
5572 | // Q = floor((2^W - 1) u/ D) | ||||||||||
5573 | // R = ((2^W - 1) u% D) | ||||||||||
5574 | APInt Q, R; | ||||||||||
5575 | APInt::udivrem(APInt::getAllOnes(W), D, Q, R); | ||||||||||
5576 | |||||||||||
5577 | // If we are comparing with zero, then that comparison constant is okay, | ||||||||||
5578 | // else it may need to be one less than that. | ||||||||||
5579 | if (Cmp.ugt(R)) | ||||||||||
5580 | Q -= 1; | ||||||||||
5581 | |||||||||||
5582 | assert(APInt::getAllOnes(ShSVT.getSizeInBits()).ugt(K) &&(static_cast <bool> (APInt::getAllOnes(ShSVT.getSizeInBits ()).ugt(K) && "We are expecting that K is always less than all-ones for ShSVT" ) ? void (0) : __assert_fail ("APInt::getAllOnes(ShSVT.getSizeInBits()).ugt(K) && \"We are expecting that K is always less than all-ones for ShSVT\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 5583, __extension__ __PRETTY_FUNCTION__)) | ||||||||||
5583 | "We are expecting that K is always less than all-ones for ShSVT")(static_cast <bool> (APInt::getAllOnes(ShSVT.getSizeInBits ()).ugt(K) && "We are expecting that K is always less than all-ones for ShSVT" ) ? void (0) : __assert_fail ("APInt::getAllOnes(ShSVT.getSizeInBits()).ugt(K) && \"We are expecting that K is always less than all-ones for ShSVT\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 5583, __extension__ __PRETTY_FUNCTION__)); | ||||||||||
5584 | |||||||||||
5585 | // If the lane is tautological the result can be constant-folded. | ||||||||||
5586 | if (TautologicalLane) { | ||||||||||
5587 | // Set P and K amount to a bogus values so we can try to splat them. | ||||||||||
5588 | P = 0; | ||||||||||
5589 | K = -1; | ||||||||||
5590 | // And ensure that comparison constant is tautological, | ||||||||||
5591 | // it will always compare true/false. | ||||||||||
5592 | Q = -1; | ||||||||||
5593 | } | ||||||||||
5594 | |||||||||||
5595 | PAmts.push_back(DAG.getConstant(P, DL, SVT)); | ||||||||||
5596 | KAmts.push_back( | ||||||||||
5597 | DAG.getConstant(APInt(ShSVT.getSizeInBits(), K), DL, ShSVT)); | ||||||||||
5598 | QAmts.push_back(DAG.getConstant(Q, DL, SVT)); | ||||||||||
5599 | return true; | ||||||||||
5600 | }; | ||||||||||
5601 | |||||||||||
5602 | SDValue N = REMNode.getOperand(0); | ||||||||||
5603 | SDValue D = REMNode.getOperand(1); | ||||||||||
5604 | |||||||||||
5605 | // Collect the values from each element. | ||||||||||
5606 | if (!ISD::matchBinaryPredicate(D, CompTargetNode, BuildUREMPattern)) | ||||||||||
5607 | return SDValue(); | ||||||||||
5608 | |||||||||||
5609 | // If all lanes are tautological, the result can be constant-folded. | ||||||||||
5610 | if (AllLanesAreTautological) | ||||||||||
5611 | return SDValue(); | ||||||||||
5612 | |||||||||||
5613 | // If this is a urem by a powers-of-two, avoid the fold since it can be | ||||||||||
5614 | // best implemented as a bit test. | ||||||||||
5615 | if (AllDivisorsArePowerOfTwo) | ||||||||||
5616 | return SDValue(); | ||||||||||
5617 | |||||||||||
5618 | SDValue PVal, KVal, QVal; | ||||||||||
5619 | if (D.getOpcode() == ISD::BUILD_VECTOR) { | ||||||||||
5620 | if (HadTautologicalLanes) { | ||||||||||
5621 | // Try to turn PAmts into a splat, since we don't care about the values | ||||||||||
5622 | // that are currently '0'. If we can't, just keep '0'`s. | ||||||||||
5623 | turnVectorIntoSplatVector(PAmts, isNullConstant); | ||||||||||
5624 | // Try to turn KAmts into a splat, since we don't care about the values | ||||||||||
5625 | // that are currently '-1'. If we can't, change them to '0'`s. | ||||||||||
5626 | turnVectorIntoSplatVector(KAmts, isAllOnesConstant, | ||||||||||
5627 | DAG.getConstant(0, DL, ShSVT)); | ||||||||||
5628 | } | ||||||||||
5629 | |||||||||||
5630 | PVal = DAG.getBuildVector(VT, DL, PAmts); | ||||||||||
5631 | KVal = DAG.getBuildVector(ShVT, DL, KAmts); | ||||||||||
5632 | QVal = DAG.getBuildVector(VT, DL, QAmts); | ||||||||||
5633 | } else if (D.getOpcode() == ISD::SPLAT_VECTOR) { | ||||||||||
5634 | assert(PAmts.size() == 1 && KAmts.size() == 1 && QAmts.size() == 1 &&(static_cast <bool> (PAmts.size() == 1 && KAmts .size() == 1 && QAmts.size() == 1 && "Expected matchBinaryPredicate to return one element for " "SPLAT_VECTORs") ? void (0) : __assert_fail ("PAmts.size() == 1 && KAmts.size() == 1 && QAmts.size() == 1 && \"Expected matchBinaryPredicate to return one element for \" \"SPLAT_VECTORs\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 5636, __extension__ __PRETTY_FUNCTION__)) | ||||||||||
5635 | "Expected matchBinaryPredicate to return one element for "(static_cast <bool> (PAmts.size() == 1 && KAmts .size() == 1 && QAmts.size() == 1 && "Expected matchBinaryPredicate to return one element for " "SPLAT_VECTORs") ? void (0) : __assert_fail ("PAmts.size() == 1 && KAmts.size() == 1 && QAmts.size() == 1 && \"Expected matchBinaryPredicate to return one element for \" \"SPLAT_VECTORs\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 5636, __extension__ __PRETTY_FUNCTION__)) | ||||||||||
5636 | "SPLAT_VECTORs")(static_cast <bool> (PAmts.size() == 1 && KAmts .size() == 1 && QAmts.size() == 1 && "Expected matchBinaryPredicate to return one element for " "SPLAT_VECTORs") ? void (0) : __assert_fail ("PAmts.size() == 1 && KAmts.size() == 1 && QAmts.size() == 1 && \"Expected matchBinaryPredicate to return one element for \" \"SPLAT_VECTORs\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 5636, __extension__ __PRETTY_FUNCTION__)); | ||||||||||
5637 | PVal = DAG.getSplatVector(VT, DL, PAmts[0]); | ||||||||||
5638 | KVal = DAG.getSplatVector(ShVT, DL, KAmts[0]); | ||||||||||
5639 | QVal = DAG.getSplatVector(VT, DL, QAmts[0]); | ||||||||||
5640 | } else { | ||||||||||
5641 | PVal = PAmts[0]; | ||||||||||
5642 | KVal = KAmts[0]; | ||||||||||
5643 | QVal = QAmts[0]; | ||||||||||
5644 | } | ||||||||||
5645 | |||||||||||
5646 | if (!ComparingWithAllZeros && !AllComparisonsWithNonZerosAreTautological) { | ||||||||||
5647 | if (!DCI.isBeforeLegalizeOps() && !isOperationLegalOrCustom(ISD::SUB, VT)) | ||||||||||
5648 | return SDValue(); // FIXME: Could/should use `ISD::ADD`? | ||||||||||
5649 | assert(CompTargetNode.getValueType() == N.getValueType() &&(static_cast <bool> (CompTargetNode.getValueType() == N .getValueType() && "Expecting that the types on LHS and RHS of comparisons match." ) ? void (0) : __assert_fail ("CompTargetNode.getValueType() == N.getValueType() && \"Expecting that the types on LHS and RHS of comparisons match.\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 5650, __extension__ __PRETTY_FUNCTION__)) | ||||||||||
5650 | "Expecting that the types on LHS and RHS of comparisons match.")(static_cast <bool> (CompTargetNode.getValueType() == N .getValueType() && "Expecting that the types on LHS and RHS of comparisons match." ) ? void (0) : __assert_fail ("CompTargetNode.getValueType() == N.getValueType() && \"Expecting that the types on LHS and RHS of comparisons match.\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 5650, __extension__ __PRETTY_FUNCTION__)); | ||||||||||
5651 | N = DAG.getNode(ISD::SUB, DL, VT, N, CompTargetNode); | ||||||||||
5652 | } | ||||||||||
5653 | |||||||||||
5654 | // (mul N, P) | ||||||||||
5655 | SDValue Op0 = DAG.getNode(ISD::MUL, DL, VT, N, PVal); | ||||||||||
5656 | Created.push_back(Op0.getNode()); | ||||||||||
5657 | |||||||||||
5658 | // Rotate right only if any divisor was even. We avoid rotates for all-odd | ||||||||||
5659 | // divisors as a performance improvement, since rotating by 0 is a no-op. | ||||||||||
5660 | if (HadEvenDivisor) { | ||||||||||
5661 | // We need ROTR to do this. | ||||||||||
5662 | if (!DCI.isBeforeLegalizeOps() && !isOperationLegalOrCustom(ISD::ROTR, VT)) | ||||||||||
5663 | return SDValue(); | ||||||||||
5664 | // UREM: (rotr (mul N, P), K) | ||||||||||
5665 | Op0 = DAG.getNode(ISD::ROTR, DL, VT, Op0, KVal); | ||||||||||
5666 | Created.push_back(Op0.getNode()); | ||||||||||
5667 | } | ||||||||||
5668 | |||||||||||
5669 | // UREM: (setule/setugt (rotr (mul N, P), K), Q) | ||||||||||
5670 | SDValue NewCC = | ||||||||||
5671 | DAG.getSetCC(DL, SETCCVT, Op0, QVal, | ||||||||||
5672 | ((Cond == ISD::SETEQ) ? ISD::SETULE : ISD::SETUGT)); | ||||||||||
5673 | if (!HadTautologicalInvertedLanes) | ||||||||||
5674 | return NewCC; | ||||||||||
5675 | |||||||||||
5676 | // If any lanes previously compared always-false, the NewCC will give | ||||||||||
5677 | // always-true result for them, so we need to fixup those lanes. | ||||||||||
5678 | // Or the other way around for inequality predicate. | ||||||||||
5679 | assert(VT.isVector() && "Can/should only get here for vectors.")(static_cast <bool> (VT.isVector() && "Can/should only get here for vectors." ) ? void (0) : __assert_fail ("VT.isVector() && \"Can/should only get here for vectors.\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 5679, __extension__ __PRETTY_FUNCTION__)); | ||||||||||
5680 | Created.push_back(NewCC.getNode()); | ||||||||||
5681 | |||||||||||
5682 | // x u% C1` is *always* less than C1. So given `x u% C1 == C2`, | ||||||||||
5683 | // if C2 is not less than C1, the comparison is always false. | ||||||||||
5684 | // But we have produced the comparison that will give the | ||||||||||
5685 | // opposive tautological answer. So these lanes would need to be fixed up. | ||||||||||
5686 | SDValue TautologicalInvertedChannels = | ||||||||||
5687 | DAG.getSetCC(DL, SETCCVT, D, CompTargetNode, ISD::SETULE); | ||||||||||
5688 | Created.push_back(TautologicalInvertedChannels.getNode()); | ||||||||||
5689 | |||||||||||
5690 | // NOTE: we avoid letting illegal types through even if we're before legalize | ||||||||||
5691 | // ops – legalization has a hard time producing good code for this. | ||||||||||
5692 | if (isOperationLegalOrCustom(ISD::VSELECT, SETCCVT)) { | ||||||||||
5693 | // If we have a vector select, let's replace the comparison results in the | ||||||||||
5694 | // affected lanes with the correct tautological result. | ||||||||||
5695 | SDValue Replacement = DAG.getBoolConstant(Cond == ISD::SETEQ ? false : true, | ||||||||||
5696 | DL, SETCCVT, SETCCVT); | ||||||||||
5697 | return DAG.getNode(ISD::VSELECT, DL, SETCCVT, TautologicalInvertedChannels, | ||||||||||
5698 | Replacement, NewCC); | ||||||||||
5699 | } | ||||||||||
5700 | |||||||||||
5701 | // Else, we can just invert the comparison result in the appropriate lanes. | ||||||||||
5702 | // | ||||||||||
5703 | // NOTE: see the note above VSELECT above. | ||||||||||
5704 | if (isOperationLegalOrCustom(ISD::XOR, SETCCVT)) | ||||||||||
5705 | return DAG.getNode(ISD::XOR, DL, SETCCVT, NewCC, | ||||||||||
5706 | TautologicalInvertedChannels); | ||||||||||
5707 | |||||||||||
5708 | return SDValue(); // Don't know how to lower. | ||||||||||
5709 | } | ||||||||||
5710 | |||||||||||
5711 | /// Given an ISD::SREM used only by an ISD::SETEQ or ISD::SETNE | ||||||||||
5712 | /// where the divisor is constant and the comparison target is zero, | ||||||||||
5713 | /// return a DAG expression that will generate the same comparison result | ||||||||||
5714 | /// using only multiplications, additions and shifts/rotations. | ||||||||||
5715 | /// Ref: "Hacker's Delight" 10-17. | ||||||||||
5716 | SDValue TargetLowering::buildSREMEqFold(EVT SETCCVT, SDValue REMNode, | ||||||||||
5717 | SDValue CompTargetNode, | ||||||||||
5718 | ISD::CondCode Cond, | ||||||||||
5719 | DAGCombinerInfo &DCI, | ||||||||||
5720 | const SDLoc &DL) const { | ||||||||||
5721 | SmallVector<SDNode *, 7> Built; | ||||||||||
5722 | if (SDValue Folded = prepareSREMEqFold(SETCCVT, REMNode, CompTargetNode, Cond, | ||||||||||
5723 | DCI, DL, Built)) { | ||||||||||
5724 | assert(Built.size() <= 7 && "Max size prediction failed.")(static_cast <bool> (Built.size() <= 7 && "Max size prediction failed." ) ? void (0) : __assert_fail ("Built.size() <= 7 && \"Max size prediction failed.\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 5724, __extension__ __PRETTY_FUNCTION__)); | ||||||||||
5725 | for (SDNode *N : Built) | ||||||||||
5726 | DCI.AddToWorklist(N); | ||||||||||
5727 | return Folded; | ||||||||||
5728 | } | ||||||||||
5729 | |||||||||||
5730 | return SDValue(); | ||||||||||
5731 | } | ||||||||||
5732 | |||||||||||
5733 | SDValue | ||||||||||
5734 | TargetLowering::prepareSREMEqFold(EVT SETCCVT, SDValue REMNode, | ||||||||||
5735 | SDValue CompTargetNode, ISD::CondCode Cond, | ||||||||||
5736 | DAGCombinerInfo &DCI, const SDLoc &DL, | ||||||||||
5737 | SmallVectorImpl<SDNode *> &Created) const { | ||||||||||
5738 | // Fold: | ||||||||||
5739 | // (seteq/ne (srem N, D), 0) | ||||||||||
5740 | // To: | ||||||||||
5741 | // (setule/ugt (rotr (add (mul N, P), A), K), Q) | ||||||||||
5742 | // | ||||||||||
5743 | // - D must be constant, with D = D0 * 2^K where D0 is odd | ||||||||||
5744 | // - P is the multiplicative inverse of D0 modulo 2^W | ||||||||||
5745 | // - A = bitwiseand(floor((2^(W - 1) - 1) / D0), (-(2^k))) | ||||||||||
5746 | // - Q = floor((2 * A) / (2^K)) | ||||||||||
5747 | // where W is the width of the common type of N and D. | ||||||||||
5748 | assert((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&(static_cast <bool> ((Cond == ISD::SETEQ || Cond == ISD ::SETNE) && "Only applicable for (in)equality comparisons." ) ? void (0) : __assert_fail ("(Cond == ISD::SETEQ || Cond == ISD::SETNE) && \"Only applicable for (in)equality comparisons.\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 5749, __extension__ __PRETTY_FUNCTION__)) | ||||||||||
5749 | "Only applicable for (in)equality comparisons.")(static_cast <bool> ((Cond == ISD::SETEQ || Cond == ISD ::SETNE) && "Only applicable for (in)equality comparisons." ) ? void (0) : __assert_fail ("(Cond == ISD::SETEQ || Cond == ISD::SETNE) && \"Only applicable for (in)equality comparisons.\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 5749, __extension__ __PRETTY_FUNCTION__)); | ||||||||||
5750 | |||||||||||
5751 | SelectionDAG &DAG = DCI.DAG; | ||||||||||
5752 | |||||||||||
5753 | EVT VT = REMNode.getValueType(); | ||||||||||
5754 | EVT SVT = VT.getScalarType(); | ||||||||||
5755 | EVT ShVT = getShiftAmountTy(VT, DAG.getDataLayout(), !DCI.isBeforeLegalize()); | ||||||||||
5756 | EVT ShSVT = ShVT.getScalarType(); | ||||||||||
5757 | |||||||||||
5758 | // If we are after ops legalization, and MUL is unavailable, we can not | ||||||||||
5759 | // proceed. | ||||||||||
5760 | if (!DCI.isBeforeLegalizeOps() && !isOperationLegalOrCustom(ISD::MUL, VT)) | ||||||||||
5761 | return SDValue(); | ||||||||||
5762 | |||||||||||
5763 | // TODO: Could support comparing with non-zero too. | ||||||||||
5764 | ConstantSDNode *CompTarget = isConstOrConstSplat(CompTargetNode); | ||||||||||
5765 | if (!CompTarget || !CompTarget->isZero()) | ||||||||||
5766 | return SDValue(); | ||||||||||
5767 | |||||||||||
5768 | bool HadIntMinDivisor = false; | ||||||||||
5769 | bool HadOneDivisor = false; | ||||||||||
5770 | bool AllDivisorsAreOnes = true; | ||||||||||
5771 | bool HadEvenDivisor = false; | ||||||||||
5772 | bool NeedToApplyOffset = false; | ||||||||||
5773 | bool AllDivisorsArePowerOfTwo = true; | ||||||||||
5774 | SmallVector<SDValue, 16> PAmts, AAmts, KAmts, QAmts; | ||||||||||
5775 | |||||||||||
5776 | auto BuildSREMPattern = [&](ConstantSDNode *C) { | ||||||||||
5777 | // Division by 0 is UB. Leave it to be constant-folded elsewhere. | ||||||||||
5778 | if (C->isZero()) | ||||||||||
5779 | return false; | ||||||||||
5780 | |||||||||||
5781 | // FIXME: we don't fold `rem %X, -C` to `rem %X, C` in DAGCombine. | ||||||||||
5782 | |||||||||||
5783 | // WARNING: this fold is only valid for positive divisors! | ||||||||||
5784 | APInt D = C->getAPIntValue(); | ||||||||||
5785 | if (D.isNegative()) | ||||||||||
5786 | D.negate(); // `rem %X, -C` is equivalent to `rem %X, C` | ||||||||||
5787 | |||||||||||
5788 | HadIntMinDivisor |= D.isMinSignedValue(); | ||||||||||
5789 | |||||||||||
5790 | // If all divisors are ones, we will prefer to avoid the fold. | ||||||||||
5791 | HadOneDivisor |= D.isOne(); | ||||||||||
5792 | AllDivisorsAreOnes &= D.isOne(); | ||||||||||
5793 | |||||||||||
5794 | // Decompose D into D0 * 2^K | ||||||||||
5795 | unsigned K = D.countTrailingZeros(); | ||||||||||
5796 | assert((!D.isOne() || (K == 0)) && "For divisor '1' we won't rotate.")(static_cast <bool> ((!D.isOne() || (K == 0)) && "For divisor '1' we won't rotate.") ? void (0) : __assert_fail ("(!D.isOne() || (K == 0)) && \"For divisor '1' we won't rotate.\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 5796, __extension__ __PRETTY_FUNCTION__)); | ||||||||||
5797 | APInt D0 = D.lshr(K); | ||||||||||
5798 | |||||||||||
5799 | if (!D.isMinSignedValue()) { | ||||||||||
5800 | // D is even if it has trailing zeros; unless it's INT_MIN, in which case | ||||||||||
5801 | // we don't care about this lane in this fold, we'll special-handle it. | ||||||||||
5802 | HadEvenDivisor |= (K != 0); | ||||||||||
5803 | } | ||||||||||
5804 | |||||||||||
5805 | // D is a power-of-two if D0 is one. This includes INT_MIN. | ||||||||||
5806 | // If all divisors are power-of-two, we will prefer to avoid the fold. | ||||||||||
5807 | AllDivisorsArePowerOfTwo &= D0.isOne(); | ||||||||||
5808 | |||||||||||
5809 | // P = inv(D0, 2^W) | ||||||||||
5810 | // 2^W requires W + 1 bits, so we have to extend and then truncate. | ||||||||||
5811 | unsigned W = D.getBitWidth(); | ||||||||||
5812 | APInt P = D0.zext(W + 1) | ||||||||||
5813 | .multiplicativeInverse(APInt::getSignedMinValue(W + 1)) | ||||||||||
5814 | .trunc(W); | ||||||||||
5815 | assert(!P.isZero() && "No multiplicative inverse!")(static_cast <bool> (!P.isZero() && "No multiplicative inverse!" ) ? void (0) : __assert_fail ("!P.isZero() && \"No multiplicative inverse!\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 5815, __extension__ __PRETTY_FUNCTION__)); // unreachable | ||||||||||
5816 | assert((D0 * P).isOne() && "Multiplicative inverse sanity check.")(static_cast <bool> ((D0 * P).isOne() && "Multiplicative inverse sanity check." ) ? void (0) : __assert_fail ("(D0 * P).isOne() && \"Multiplicative inverse sanity check.\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 5816, __extension__ __PRETTY_FUNCTION__)); | ||||||||||
5817 | |||||||||||
5818 | // A = floor((2^(W - 1) - 1) / D0) & -2^K | ||||||||||
5819 | APInt A = APInt::getSignedMaxValue(W).udiv(D0); | ||||||||||
5820 | A.clearLowBits(K); | ||||||||||
5821 | |||||||||||
5822 | if (!D.isMinSignedValue()) { | ||||||||||
5823 | // If divisor INT_MIN, then we don't care about this lane in this fold, | ||||||||||
5824 | // we'll special-handle it. | ||||||||||
5825 | NeedToApplyOffset |= A != 0; | ||||||||||
5826 | } | ||||||||||
5827 | |||||||||||
5828 | // Q = floor((2 * A) / (2^K)) | ||||||||||
5829 | APInt Q = (2 * A).udiv(APInt::getOneBitSet(W, K)); | ||||||||||
5830 | |||||||||||
5831 | assert(APInt::getAllOnes(SVT.getSizeInBits()).ugt(A) &&(static_cast <bool> (APInt::getAllOnes(SVT.getSizeInBits ()).ugt(A) && "We are expecting that A is always less than all-ones for SVT" ) ? void (0) : __assert_fail ("APInt::getAllOnes(SVT.getSizeInBits()).ugt(A) && \"We are expecting that A is always less than all-ones for SVT\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 5832, __extension__ __PRETTY_FUNCTION__)) | ||||||||||
5832 | "We are expecting that A is always less than all-ones for SVT")(static_cast <bool> (APInt::getAllOnes(SVT.getSizeInBits ()).ugt(A) && "We are expecting that A is always less than all-ones for SVT" ) ? void (0) : __assert_fail ("APInt::getAllOnes(SVT.getSizeInBits()).ugt(A) && \"We are expecting that A is always less than all-ones for SVT\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 5832, __extension__ __PRETTY_FUNCTION__)); | ||||||||||
5833 | assert(APInt::getAllOnes(ShSVT.getSizeInBits()).ugt(K) &&(static_cast <bool> (APInt::getAllOnes(ShSVT.getSizeInBits ()).ugt(K) && "We are expecting that K is always less than all-ones for ShSVT" ) ? void (0) : __assert_fail ("APInt::getAllOnes(ShSVT.getSizeInBits()).ugt(K) && \"We are expecting that K is always less than all-ones for ShSVT\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 5834, __extension__ __PRETTY_FUNCTION__)) | ||||||||||
5834 | "We are expecting that K is always less than all-ones for ShSVT")(static_cast <bool> (APInt::getAllOnes(ShSVT.getSizeInBits ()).ugt(K) && "We are expecting that K is always less than all-ones for ShSVT" ) ? void (0) : __assert_fail ("APInt::getAllOnes(ShSVT.getSizeInBits()).ugt(K) && \"We are expecting that K is always less than all-ones for ShSVT\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 5834, __extension__ __PRETTY_FUNCTION__)); | ||||||||||
5835 | |||||||||||
5836 | // If the divisor is 1 the result can be constant-folded. Likewise, we | ||||||||||
5837 | // don't care about INT_MIN lanes, those can be set to undef if appropriate. | ||||||||||
5838 | if (D.isOne()) { | ||||||||||
5839 | // Set P, A and K to a bogus values so we can try to splat them. | ||||||||||
5840 | P = 0; | ||||||||||
5841 | A = -1; | ||||||||||
5842 | K = -1; | ||||||||||
5843 | |||||||||||
5844 | // x ?% 1 == 0 <--> true <--> x u<= -1 | ||||||||||
5845 | Q = -1; | ||||||||||
5846 | } | ||||||||||
5847 | |||||||||||
5848 | PAmts.push_back(DAG.getConstant(P, DL, SVT)); | ||||||||||
5849 | AAmts.push_back(DAG.getConstant(A, DL, SVT)); | ||||||||||
5850 | KAmts.push_back( | ||||||||||
5851 | DAG.getConstant(APInt(ShSVT.getSizeInBits(), K), DL, ShSVT)); | ||||||||||
5852 | QAmts.push_back(DAG.getConstant(Q, DL, SVT)); | ||||||||||
5853 | return true; | ||||||||||
5854 | }; | ||||||||||
5855 | |||||||||||
5856 | SDValue N = REMNode.getOperand(0); | ||||||||||
5857 | SDValue D = REMNode.getOperand(1); | ||||||||||
5858 | |||||||||||
5859 | // Collect the values from each element. | ||||||||||
5860 | if (!ISD::matchUnaryPredicate(D, BuildSREMPattern)) | ||||||||||
5861 | return SDValue(); | ||||||||||
5862 | |||||||||||
5863 | // If this is a srem by a one, avoid the fold since it can be constant-folded. | ||||||||||
5864 | if (AllDivisorsAreOnes) | ||||||||||
5865 | return SDValue(); | ||||||||||
5866 | |||||||||||
5867 | // If this is a srem by a powers-of-two (including INT_MIN), avoid the fold | ||||||||||
5868 | // since it can be best implemented as a bit test. | ||||||||||
5869 | if (AllDivisorsArePowerOfTwo) | ||||||||||
5870 | return SDValue(); | ||||||||||
5871 | |||||||||||
5872 | SDValue PVal, AVal, KVal, QVal; | ||||||||||
5873 | if (D.getOpcode() == ISD::BUILD_VECTOR) { | ||||||||||
5874 | if (HadOneDivisor) { | ||||||||||
5875 | // Try to turn PAmts into a splat, since we don't care about the values | ||||||||||
5876 | // that are currently '0'. If we can't, just keep '0'`s. | ||||||||||
5877 | turnVectorIntoSplatVector(PAmts, isNullConstant); | ||||||||||
5878 | // Try to turn AAmts into a splat, since we don't care about the | ||||||||||
5879 | // values that are currently '-1'. If we can't, change them to '0'`s. | ||||||||||
5880 | turnVectorIntoSplatVector(AAmts, isAllOnesConstant, | ||||||||||
5881 | DAG.getConstant(0, DL, SVT)); | ||||||||||
5882 | // Try to turn KAmts into a splat, since we don't care about the values | ||||||||||
5883 | // that are currently '-1'. If we can't, change them to '0'`s. | ||||||||||
5884 | turnVectorIntoSplatVector(KAmts, isAllOnesConstant, | ||||||||||
5885 | DAG.getConstant(0, DL, ShSVT)); | ||||||||||
5886 | } | ||||||||||
5887 | |||||||||||
5888 | PVal = DAG.getBuildVector(VT, DL, PAmts); | ||||||||||
5889 | AVal = DAG.getBuildVector(VT, DL, AAmts); | ||||||||||
5890 | KVal = DAG.getBuildVector(ShVT, DL, KAmts); | ||||||||||
5891 | QVal = DAG.getBuildVector(VT, DL, QAmts); | ||||||||||
5892 | } else if (D.getOpcode() == ISD::SPLAT_VECTOR) { | ||||||||||
5893 | assert(PAmts.size() == 1 && AAmts.size() == 1 && KAmts.size() == 1 &&(static_cast <bool> (PAmts.size() == 1 && AAmts .size() == 1 && KAmts.size() == 1 && QAmts.size () == 1 && "Expected matchUnaryPredicate to return one element for scalable " "vectors") ? void (0) : __assert_fail ("PAmts.size() == 1 && AAmts.size() == 1 && KAmts.size() == 1 && QAmts.size() == 1 && \"Expected matchUnaryPredicate to return one element for scalable \" \"vectors\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 5896, __extension__ __PRETTY_FUNCTION__)) | ||||||||||
5894 | QAmts.size() == 1 &&(static_cast <bool> (PAmts.size() == 1 && AAmts .size() == 1 && KAmts.size() == 1 && QAmts.size () == 1 && "Expected matchUnaryPredicate to return one element for scalable " "vectors") ? void (0) : __assert_fail ("PAmts.size() == 1 && AAmts.size() == 1 && KAmts.size() == 1 && QAmts.size() == 1 && \"Expected matchUnaryPredicate to return one element for scalable \" \"vectors\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 5896, __extension__ __PRETTY_FUNCTION__)) | ||||||||||
5895 | "Expected matchUnaryPredicate to return one element for scalable "(static_cast <bool> (PAmts.size() == 1 && AAmts .size() == 1 && KAmts.size() == 1 && QAmts.size () == 1 && "Expected matchUnaryPredicate to return one element for scalable " "vectors") ? void (0) : __assert_fail ("PAmts.size() == 1 && AAmts.size() == 1 && KAmts.size() == 1 && QAmts.size() == 1 && \"Expected matchUnaryPredicate to return one element for scalable \" \"vectors\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 5896, __extension__ __PRETTY_FUNCTION__)) | ||||||||||
5896 | "vectors")(static_cast <bool> (PAmts.size() == 1 && AAmts .size() == 1 && KAmts.size() == 1 && QAmts.size () == 1 && "Expected matchUnaryPredicate to return one element for scalable " "vectors") ? void (0) : __assert_fail ("PAmts.size() == 1 && AAmts.size() == 1 && KAmts.size() == 1 && QAmts.size() == 1 && \"Expected matchUnaryPredicate to return one element for scalable \" \"vectors\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 5896, __extension__ __PRETTY_FUNCTION__)); | ||||||||||
5897 | PVal = DAG.getSplatVector(VT, DL, PAmts[0]); | ||||||||||
5898 | AVal = DAG.getSplatVector(VT, DL, AAmts[0]); | ||||||||||
5899 | KVal = DAG.getSplatVector(ShVT, DL, KAmts[0]); | ||||||||||
5900 | QVal = DAG.getSplatVector(VT, DL, QAmts[0]); | ||||||||||
5901 | } else { | ||||||||||
5902 | assert(isa<ConstantSDNode>(D) && "Expected a constant")(static_cast <bool> (isa<ConstantSDNode>(D) && "Expected a constant") ? void (0) : __assert_fail ("isa<ConstantSDNode>(D) && \"Expected a constant\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 5902, __extension__ __PRETTY_FUNCTION__)); | ||||||||||
5903 | PVal = PAmts[0]; | ||||||||||
5904 | AVal = AAmts[0]; | ||||||||||
5905 | KVal = KAmts[0]; | ||||||||||
5906 | QVal = QAmts[0]; | ||||||||||
5907 | } | ||||||||||
5908 | |||||||||||
5909 | // (mul N, P) | ||||||||||
5910 | SDValue Op0 = DAG.getNode(ISD::MUL, DL, VT, N, PVal); | ||||||||||
5911 | Created.push_back(Op0.getNode()); | ||||||||||
5912 | |||||||||||
5913 | if (NeedToApplyOffset) { | ||||||||||
5914 | // We need ADD to do this. | ||||||||||
5915 | if (!DCI.isBeforeLegalizeOps() && !isOperationLegalOrCustom(ISD::ADD, VT)) | ||||||||||
5916 | return SDValue(); | ||||||||||
5917 | |||||||||||
5918 | // (add (mul N, P), A) | ||||||||||
5919 | Op0 = DAG.getNode(ISD::ADD, DL, VT, Op0, AVal); | ||||||||||
5920 | Created.push_back(Op0.getNode()); | ||||||||||
5921 | } | ||||||||||
5922 | |||||||||||
5923 | // Rotate right only if any divisor was even. We avoid rotates for all-odd | ||||||||||
5924 | // divisors as a performance improvement, since rotating by 0 is a no-op. | ||||||||||
5925 | if (HadEvenDivisor) { | ||||||||||
5926 | // We need ROTR to do this. | ||||||||||
5927 | if (!DCI.isBeforeLegalizeOps() && !isOperationLegalOrCustom(ISD::ROTR, VT)) | ||||||||||
5928 | return SDValue(); | ||||||||||
5929 | // SREM: (rotr (add (mul N, P), A), K) | ||||||||||
5930 | Op0 = DAG.getNode(ISD::ROTR, DL, VT, Op0, KVal); | ||||||||||
5931 | Created.push_back(Op0.getNode()); | ||||||||||
5932 | } | ||||||||||
5933 | |||||||||||
5934 | // SREM: (setule/setugt (rotr (add (mul N, P), A), K), Q) | ||||||||||
5935 | SDValue Fold = | ||||||||||
5936 | DAG.getSetCC(DL, SETCCVT, Op0, QVal, | ||||||||||
5937 | ((Cond == ISD::SETEQ) ? ISD::SETULE : ISD::SETUGT)); | ||||||||||
5938 | |||||||||||
5939 | // If we didn't have lanes with INT_MIN divisor, then we're done. | ||||||||||
5940 | if (!HadIntMinDivisor) | ||||||||||
5941 | return Fold; | ||||||||||
5942 | |||||||||||
5943 | // That fold is only valid for positive divisors. Which effectively means, | ||||||||||
5944 | // it is invalid for INT_MIN divisors. So if we have such a lane, | ||||||||||
5945 | // we must fix-up results for said lanes. | ||||||||||
5946 | assert(VT.isVector() && "Can/should only get here for vectors.")(static_cast <bool> (VT.isVector() && "Can/should only get here for vectors." ) ? void (0) : __assert_fail ("VT.isVector() && \"Can/should only get here for vectors.\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 5946, __extension__ __PRETTY_FUNCTION__)); | ||||||||||
5947 | |||||||||||
5948 | // NOTE: we avoid letting illegal types through even if we're before legalize | ||||||||||
5949 | // ops – legalization has a hard time producing good code for the code that | ||||||||||
5950 | // follows. | ||||||||||
5951 | if (!isOperationLegalOrCustom(ISD::SETEQ, VT) || | ||||||||||
5952 | !isOperationLegalOrCustom(ISD::AND, VT) || | ||||||||||
5953 | !isOperationLegalOrCustom(Cond, VT) || | ||||||||||
5954 | !isOperationLegalOrCustom(ISD::VSELECT, SETCCVT)) | ||||||||||
5955 | return SDValue(); | ||||||||||
5956 | |||||||||||
5957 | Created.push_back(Fold.getNode()); | ||||||||||
5958 | |||||||||||
5959 | SDValue IntMin = DAG.getConstant( | ||||||||||
5960 | APInt::getSignedMinValue(SVT.getScalarSizeInBits()), DL, VT); | ||||||||||
5961 | SDValue IntMax = DAG.getConstant( | ||||||||||
5962 | APInt::getSignedMaxValue(SVT.getScalarSizeInBits()), DL, VT); | ||||||||||
5963 | SDValue Zero = | ||||||||||
5964 | DAG.getConstant(APInt::getZero(SVT.getScalarSizeInBits()), DL, VT); | ||||||||||
5965 | |||||||||||
5966 | // Which lanes had INT_MIN divisors? Divisor is constant, so const-folded. | ||||||||||
5967 | SDValue DivisorIsIntMin = DAG.getSetCC(DL, SETCCVT, D, IntMin, ISD::SETEQ); | ||||||||||
5968 | Created.push_back(DivisorIsIntMin.getNode()); | ||||||||||
5969 | |||||||||||
5970 | // (N s% INT_MIN) ==/!= 0 <--> (N & INT_MAX) ==/!= 0 | ||||||||||
5971 | SDValue Masked = DAG.getNode(ISD::AND, DL, VT, N, IntMax); | ||||||||||
5972 | Created.push_back(Masked.getNode()); | ||||||||||
5973 | SDValue MaskedIsZero = DAG.getSetCC(DL, SETCCVT, Masked, Zero, Cond); | ||||||||||
5974 | Created.push_back(MaskedIsZero.getNode()); | ||||||||||
5975 | |||||||||||
5976 | // To produce final result we need to blend 2 vectors: 'SetCC' and | ||||||||||
5977 | // 'MaskedIsZero'. If the divisor for channel was *NOT* INT_MIN, we pick | ||||||||||
5978 | // from 'Fold', else pick from 'MaskedIsZero'. Since 'DivisorIsIntMin' is | ||||||||||
5979 | // constant-folded, select can get lowered to a shuffle with constant mask. | ||||||||||
5980 | SDValue Blended = DAG.getNode(ISD::VSELECT, DL, SETCCVT, DivisorIsIntMin, | ||||||||||
5981 | MaskedIsZero, Fold); | ||||||||||
5982 | |||||||||||
5983 | return Blended; | ||||||||||
5984 | } | ||||||||||
5985 | |||||||||||
5986 | bool TargetLowering:: | ||||||||||
5987 | verifyReturnAddressArgumentIsConstant(SDValue Op, SelectionDAG &DAG) const { | ||||||||||
5988 | if (!isa<ConstantSDNode>(Op.getOperand(0))) { | ||||||||||
5989 | DAG.getContext()->emitError("argument to '__builtin_return_address' must " | ||||||||||
5990 | "be a constant integer"); | ||||||||||
5991 | return true; | ||||||||||
5992 | } | ||||||||||
5993 | |||||||||||
5994 | return false; | ||||||||||
5995 | } | ||||||||||
5996 | |||||||||||
5997 | SDValue TargetLowering::getSqrtInputTest(SDValue Op, SelectionDAG &DAG, | ||||||||||
5998 | const DenormalMode &Mode) const { | ||||||||||
5999 | SDLoc DL(Op); | ||||||||||
6000 | EVT VT = Op.getValueType(); | ||||||||||
6001 | EVT CCVT = getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT); | ||||||||||
6002 | SDValue FPZero = DAG.getConstantFP(0.0, DL, VT); | ||||||||||
6003 | // Testing it with denormal inputs to avoid wrong estimate. | ||||||||||
6004 | if (Mode.Input == DenormalMode::IEEE) { | ||||||||||
6005 | // This is specifically a check for the handling of denormal inputs, | ||||||||||
6006 | // not the result. | ||||||||||
6007 | |||||||||||
6008 | // Test = fabs(X) < SmallestNormal | ||||||||||
6009 | const fltSemantics &FltSem = DAG.EVTToAPFloatSemantics(VT); | ||||||||||
6010 | APFloat SmallestNorm = APFloat::getSmallestNormalized(FltSem); | ||||||||||
6011 | SDValue NormC = DAG.getConstantFP(SmallestNorm, DL, VT); | ||||||||||
6012 | SDValue Fabs = DAG.getNode(ISD::FABS, DL, VT, Op); | ||||||||||
6013 | return DAG.getSetCC(DL, CCVT, Fabs, NormC, ISD::SETLT); | ||||||||||
6014 | } | ||||||||||
6015 | // Test = X == 0.0 | ||||||||||
6016 | return DAG.getSetCC(DL, CCVT, Op, FPZero, ISD::SETEQ); | ||||||||||
6017 | } | ||||||||||
6018 | |||||||||||
6019 | SDValue TargetLowering::getNegatedExpression(SDValue Op, SelectionDAG &DAG, | ||||||||||
6020 | bool LegalOps, bool OptForSize, | ||||||||||
6021 | NegatibleCost &Cost, | ||||||||||
6022 | unsigned Depth) const { | ||||||||||
6023 | // fneg is removable even if it has multiple uses. | ||||||||||
6024 | if (Op.getOpcode() == ISD::FNEG) { | ||||||||||
6025 | Cost = NegatibleCost::Cheaper; | ||||||||||
6026 | return Op.getOperand(0); | ||||||||||
6027 | } | ||||||||||
6028 | |||||||||||
6029 | // Don't recurse exponentially. | ||||||||||
6030 | if (Depth > SelectionDAG::MaxRecursionDepth) | ||||||||||
6031 | return SDValue(); | ||||||||||
6032 | |||||||||||
6033 | // Pre-increment recursion depth for use in recursive calls. | ||||||||||
6034 | ++Depth; | ||||||||||
6035 | const SDNodeFlags Flags = Op->getFlags(); | ||||||||||
6036 | const TargetOptions &Options = DAG.getTarget().Options; | ||||||||||
6037 | EVT VT = Op.getValueType(); | ||||||||||
6038 | unsigned Opcode = Op.getOpcode(); | ||||||||||
6039 | |||||||||||
6040 | // Don't allow anything with multiple uses unless we know it is free. | ||||||||||
6041 | if (!Op.hasOneUse() && Opcode != ISD::ConstantFP) { | ||||||||||
6042 | bool IsFreeExtend = Opcode == ISD::FP_EXTEND && | ||||||||||
6043 | isFPExtFree(VT, Op.getOperand(0).getValueType()); | ||||||||||
6044 | if (!IsFreeExtend) | ||||||||||
6045 | return SDValue(); | ||||||||||
6046 | } | ||||||||||
6047 | |||||||||||
6048 | auto RemoveDeadNode = [&](SDValue N) { | ||||||||||
6049 | if (N && N.getNode()->use_empty()) | ||||||||||
6050 | DAG.RemoveDeadNode(N.getNode()); | ||||||||||
6051 | }; | ||||||||||
6052 | |||||||||||
6053 | SDLoc DL(Op); | ||||||||||
6054 | |||||||||||
6055 | // Because getNegatedExpression can delete nodes we need a handle to keep | ||||||||||
6056 | // temporary nodes alive in case the recursion manages to create an identical | ||||||||||
6057 | // node. | ||||||||||
6058 | std::list<HandleSDNode> Handles; | ||||||||||
6059 | |||||||||||
6060 | switch (Opcode) { | ||||||||||
6061 | case ISD::ConstantFP: { | ||||||||||
6062 | // Don't invert constant FP values after legalization unless the target says | ||||||||||
6063 | // the negated constant is legal. | ||||||||||
6064 | bool IsOpLegal = | ||||||||||
6065 | isOperationLegal(ISD::ConstantFP, VT) || | ||||||||||
6066 | isFPImmLegal(neg(cast<ConstantFPSDNode>(Op)->getValueAPF()), VT, | ||||||||||
6067 | OptForSize); | ||||||||||
6068 | |||||||||||
6069 | if (LegalOps && !IsOpLegal) | ||||||||||
6070 | break; | ||||||||||
6071 | |||||||||||
6072 | APFloat V = cast<ConstantFPSDNode>(Op)->getValueAPF(); | ||||||||||
6073 | V.changeSign(); | ||||||||||
6074 | SDValue CFP = DAG.getConstantFP(V, DL, VT); | ||||||||||
6075 | |||||||||||
6076 | // If we already have the use of the negated floating constant, it is free | ||||||||||
6077 | // to negate it even it has multiple uses. | ||||||||||
6078 | if (!Op.hasOneUse() && CFP.use_empty()) | ||||||||||
6079 | break; | ||||||||||
6080 | Cost = NegatibleCost::Neutral; | ||||||||||
6081 | return CFP; | ||||||||||
6082 | } | ||||||||||
6083 | case ISD::BUILD_VECTOR: { | ||||||||||
6084 | // Only permit BUILD_VECTOR of constants. | ||||||||||
6085 | if (llvm::any_of(Op->op_values(), [&](SDValue N) { | ||||||||||
6086 | return !N.isUndef() && !isa<ConstantFPSDNode>(N); | ||||||||||
6087 | })) | ||||||||||
6088 | break; | ||||||||||
6089 | |||||||||||
6090 | bool IsOpLegal = | ||||||||||
6091 | (isOperationLegal(ISD::ConstantFP, VT) && | ||||||||||
6092 | isOperationLegal(ISD::BUILD_VECTOR, VT)) || | ||||||||||
6093 | llvm::all_of(Op->op_values(), [&](SDValue N) { | ||||||||||
6094 | return N.isUndef() || | ||||||||||
6095 | isFPImmLegal(neg(cast<ConstantFPSDNode>(N)->getValueAPF()), VT, | ||||||||||
6096 | OptForSize); | ||||||||||
6097 | }); | ||||||||||
6098 | |||||||||||
6099 | if (LegalOps && !IsOpLegal) | ||||||||||
6100 | break; | ||||||||||
6101 | |||||||||||
6102 | SmallVector<SDValue, 4> Ops; | ||||||||||
6103 | for (SDValue C : Op->op_values()) { | ||||||||||
6104 | if (C.isUndef()) { | ||||||||||
6105 | Ops.push_back(C); | ||||||||||
6106 | continue; | ||||||||||
6107 | } | ||||||||||
6108 | APFloat V = cast<ConstantFPSDNode>(C)->getValueAPF(); | ||||||||||
6109 | V.changeSign(); | ||||||||||
6110 | Ops.push_back(DAG.getConstantFP(V, DL, C.getValueType())); | ||||||||||
6111 | } | ||||||||||
6112 | Cost = NegatibleCost::Neutral; | ||||||||||
6113 | return DAG.getBuildVector(VT, DL, Ops); | ||||||||||
6114 | } | ||||||||||
6115 | case ISD::FADD: { | ||||||||||
6116 | if (!Options.NoSignedZerosFPMath && !Flags.hasNoSignedZeros()) | ||||||||||
6117 | break; | ||||||||||
6118 | |||||||||||
6119 | // After operation legalization, it might not be legal to create new FSUBs. | ||||||||||
6120 | if (LegalOps && !isOperationLegalOrCustom(ISD::FSUB, VT)) | ||||||||||
6121 | break; | ||||||||||
6122 | SDValue X = Op.getOperand(0), Y = Op.getOperand(1); | ||||||||||
6123 | |||||||||||
6124 | // fold (fneg (fadd X, Y)) -> (fsub (fneg X), Y) | ||||||||||
6125 | NegatibleCost CostX = NegatibleCost::Expensive; | ||||||||||
6126 | SDValue NegX = | ||||||||||
6127 | getNegatedExpression(X, DAG, LegalOps, OptForSize, CostX, Depth); | ||||||||||
6128 | // Prevent this node from being deleted by the next call. | ||||||||||
6129 | if (NegX) | ||||||||||
6130 | Handles.emplace_back(NegX); | ||||||||||
6131 | |||||||||||
6132 | // fold (fneg (fadd X, Y)) -> (fsub (fneg Y), X) | ||||||||||
6133 | NegatibleCost CostY = NegatibleCost::Expensive; | ||||||||||
6134 | SDValue NegY = | ||||||||||
6135 | getNegatedExpression(Y, DAG, LegalOps, OptForSize, CostY, Depth); | ||||||||||
6136 | |||||||||||
6137 | // We're done with the handles. | ||||||||||
6138 | Handles.clear(); | ||||||||||
6139 | |||||||||||
6140 | // Negate the X if its cost is less or equal than Y. | ||||||||||
6141 | if (NegX && (CostX <= CostY)) { | ||||||||||
6142 | Cost = CostX; | ||||||||||
6143 | SDValue N = DAG.getNode(ISD::FSUB, DL, VT, NegX, Y, Flags); | ||||||||||
6144 | if (NegY != N) | ||||||||||
6145 | RemoveDeadNode(NegY); | ||||||||||
6146 | return N; | ||||||||||
6147 | } | ||||||||||
6148 | |||||||||||
6149 | // Negate the Y if it is not expensive. | ||||||||||
6150 | if (NegY) { | ||||||||||
6151 | Cost = CostY; | ||||||||||
6152 | SDValue N = DAG.getNode(ISD::FSUB, DL, VT, NegY, X, Flags); | ||||||||||
6153 | if (NegX != N) | ||||||||||
6154 | RemoveDeadNode(NegX); | ||||||||||
6155 | return N; | ||||||||||
6156 | } | ||||||||||
6157 | break; | ||||||||||
6158 | } | ||||||||||
6159 | case ISD::FSUB: { | ||||||||||
6160 | // We can't turn -(A-B) into B-A when we honor signed zeros. | ||||||||||
6161 | if (!Options.NoSignedZerosFPMath && !Flags.hasNoSignedZeros()) | ||||||||||
6162 | break; | ||||||||||
6163 | |||||||||||
6164 | SDValue X = Op.getOperand(0), Y = Op.getOperand(1); | ||||||||||
6165 | // fold (fneg (fsub 0, Y)) -> Y | ||||||||||
6166 | if (ConstantFPSDNode *C = isConstOrConstSplatFP(X, /*AllowUndefs*/ true)) | ||||||||||
6167 | if (C->isZero()) { | ||||||||||
6168 | Cost = NegatibleCost::Cheaper; | ||||||||||
6169 | return Y; | ||||||||||
6170 | } | ||||||||||
6171 | |||||||||||
6172 | // fold (fneg (fsub X, Y)) -> (fsub Y, X) | ||||||||||
6173 | Cost = NegatibleCost::Neutral; | ||||||||||
6174 | return DAG.getNode(ISD::FSUB, DL, VT, Y, X, Flags); | ||||||||||
6175 | } | ||||||||||
6176 | case ISD::FMUL: | ||||||||||
6177 | case ISD::FDIV: { | ||||||||||
6178 | SDValue X = Op.getOperand(0), Y = Op.getOperand(1); | ||||||||||
6179 | |||||||||||
6180 | // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y) | ||||||||||
6181 | NegatibleCost CostX = NegatibleCost::Expensive; | ||||||||||
6182 | SDValue NegX = | ||||||||||
6183 | getNegatedExpression(X, DAG, LegalOps, OptForSize, CostX, Depth); | ||||||||||
6184 | // Prevent this node from being deleted by the next call. | ||||||||||
6185 | if (NegX) | ||||||||||
6186 | Handles.emplace_back(NegX); | ||||||||||
6187 | |||||||||||
6188 | // fold (fneg (fmul X, Y)) -> (fmul X, (fneg Y)) | ||||||||||
6189 | NegatibleCost CostY = NegatibleCost::Expensive; | ||||||||||
6190 | SDValue NegY = | ||||||||||
6191 | getNegatedExpression(Y, DAG, LegalOps, OptForSize, CostY, Depth); | ||||||||||
6192 | |||||||||||
6193 | // We're done with the handles. | ||||||||||
6194 | Handles.clear(); | ||||||||||
6195 | |||||||||||
6196 | // Negate the X if its cost is less or equal than Y. | ||||||||||
6197 | if (NegX && (CostX <= CostY)) { | ||||||||||
6198 | Cost = CostX; | ||||||||||
6199 | SDValue N = DAG.getNode(Opcode, DL, VT, NegX, Y, Flags); | ||||||||||
6200 | if (NegY != N) | ||||||||||
6201 | RemoveDeadNode(NegY); | ||||||||||
6202 | return N; | ||||||||||
6203 | } | ||||||||||
6204 | |||||||||||
6205 | // Ignore X * 2.0 because that is expected to be canonicalized to X + X. | ||||||||||
6206 | if (auto *C = isConstOrConstSplatFP(Op.getOperand(1))) | ||||||||||
6207 | if (C->isExactlyValue(2.0) && Op.getOpcode() == ISD::FMUL) | ||||||||||
6208 | break; | ||||||||||
6209 | |||||||||||
6210 | // Negate the Y if it is not expensive. | ||||||||||
6211 | if (NegY) { | ||||||||||
6212 | Cost = CostY; | ||||||||||
6213 | SDValue N = DAG.getNode(Opcode, DL, VT, X, NegY, Flags); | ||||||||||
6214 | if (NegX != N) | ||||||||||
6215 | RemoveDeadNode(NegX); | ||||||||||
6216 | return N; | ||||||||||
6217 | } | ||||||||||
6218 | break; | ||||||||||
6219 | } | ||||||||||
6220 | case ISD::FMA: | ||||||||||
6221 | case ISD::FMAD: { | ||||||||||
6222 | if (!Options.NoSignedZerosFPMath && !Flags.hasNoSignedZeros()) | ||||||||||
6223 | break; | ||||||||||
6224 | |||||||||||
6225 | SDValue X = Op.getOperand(0), Y = Op.getOperand(1), Z = Op.getOperand(2); | ||||||||||
6226 | NegatibleCost CostZ = NegatibleCost::Expensive; | ||||||||||
6227 | SDValue NegZ = | ||||||||||
6228 | getNegatedExpression(Z, DAG, LegalOps, OptForSize, CostZ, Depth); | ||||||||||
6229 | // Give up if fail to negate the Z. | ||||||||||
6230 | if (!NegZ) | ||||||||||
6231 | break; | ||||||||||
6232 | |||||||||||
6233 | // Prevent this node from being deleted by the next two calls. | ||||||||||
6234 | Handles.emplace_back(NegZ); | ||||||||||
6235 | |||||||||||
6236 | // fold (fneg (fma X, Y, Z)) -> (fma (fneg X), Y, (fneg Z)) | ||||||||||
6237 | NegatibleCost CostX = NegatibleCost::Expensive; | ||||||||||
6238 | SDValue NegX = | ||||||||||
6239 | getNegatedExpression(X, DAG, LegalOps, OptForSize, CostX, Depth); | ||||||||||
6240 | // Prevent this node from being deleted by the next call. | ||||||||||
6241 | if (NegX) | ||||||||||
6242 | Handles.emplace_back(NegX); | ||||||||||
6243 | |||||||||||
6244 | // fold (fneg (fma X, Y, Z)) -> (fma X, (fneg Y), (fneg Z)) | ||||||||||
6245 | NegatibleCost CostY = NegatibleCost::Expensive; | ||||||||||
6246 | SDValue NegY = | ||||||||||
6247 | getNegatedExpression(Y, DAG, LegalOps, OptForSize, CostY, Depth); | ||||||||||
6248 | |||||||||||
6249 | // We're done with the handles. | ||||||||||
6250 | Handles.clear(); | ||||||||||
6251 | |||||||||||
6252 | // Negate the X if its cost is less or equal than Y. | ||||||||||
6253 | if (NegX && (CostX <= CostY)) { | ||||||||||
6254 | Cost = std::min(CostX, CostZ); | ||||||||||
6255 | SDValue N = DAG.getNode(Opcode, DL, VT, NegX, Y, NegZ, Flags); | ||||||||||
6256 | if (NegY != N) | ||||||||||
6257 | RemoveDeadNode(NegY); | ||||||||||
6258 | return N; | ||||||||||
6259 | } | ||||||||||
6260 | |||||||||||
6261 | // Negate the Y if it is not expensive. | ||||||||||
6262 | if (NegY) { | ||||||||||
6263 | Cost = std::min(CostY, CostZ); | ||||||||||
6264 | SDValue N = DAG.getNode(Opcode, DL, VT, X, NegY, NegZ, Flags); | ||||||||||
6265 | if (NegX != N) | ||||||||||
6266 | RemoveDeadNode(NegX); | ||||||||||
6267 | return N; | ||||||||||
6268 | } | ||||||||||
6269 | break; | ||||||||||
6270 | } | ||||||||||
6271 | |||||||||||
6272 | case ISD::FP_EXTEND: | ||||||||||
6273 | case ISD::FSIN: | ||||||||||
6274 | if (SDValue NegV = getNegatedExpression(Op.getOperand(0), DAG, LegalOps, | ||||||||||
6275 | OptForSize, Cost, Depth)) | ||||||||||
6276 | return DAG.getNode(Opcode, DL, VT, NegV); | ||||||||||
6277 | break; | ||||||||||
6278 | case ISD::FP_ROUND: | ||||||||||
6279 | if (SDValue NegV = getNegatedExpression(Op.getOperand(0), DAG, LegalOps, | ||||||||||
6280 | OptForSize, Cost, Depth)) | ||||||||||
6281 | return DAG.getNode(ISD::FP_ROUND, DL, VT, NegV, Op.getOperand(1)); | ||||||||||
6282 | break; | ||||||||||
6283 | } | ||||||||||
6284 | |||||||||||
6285 | return SDValue(); | ||||||||||
6286 | } | ||||||||||
6287 | |||||||||||
6288 | //===----------------------------------------------------------------------===// | ||||||||||
6289 | // Legalization Utilities | ||||||||||
6290 | //===----------------------------------------------------------------------===// | ||||||||||
6291 | |||||||||||
6292 | bool TargetLowering::expandMUL_LOHI(unsigned Opcode, EVT VT, const SDLoc &dl, | ||||||||||
6293 | SDValue LHS, SDValue RHS, | ||||||||||
6294 | SmallVectorImpl<SDValue> &Result, | ||||||||||
6295 | EVT HiLoVT, SelectionDAG &DAG, | ||||||||||
6296 | MulExpansionKind Kind, SDValue LL, | ||||||||||
6297 | SDValue LH, SDValue RL, SDValue RH) const { | ||||||||||
6298 | assert(Opcode == ISD::MUL || Opcode == ISD::UMUL_LOHI ||(static_cast <bool> (Opcode == ISD::MUL || Opcode == ISD ::UMUL_LOHI || Opcode == ISD::SMUL_LOHI) ? void (0) : __assert_fail ("Opcode == ISD::MUL || Opcode == ISD::UMUL_LOHI || Opcode == ISD::SMUL_LOHI" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 6299, __extension__ __PRETTY_FUNCTION__)) | ||||||||||
6299 | Opcode == ISD::SMUL_LOHI)(static_cast <bool> (Opcode == ISD::MUL || Opcode == ISD ::UMUL_LOHI || Opcode == ISD::SMUL_LOHI) ? void (0) : __assert_fail ("Opcode == ISD::MUL || Opcode == ISD::UMUL_LOHI || Opcode == ISD::SMUL_LOHI" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 6299, __extension__ __PRETTY_FUNCTION__)); | ||||||||||
6300 | |||||||||||
6301 | bool HasMULHS = (Kind == MulExpansionKind::Always) || | ||||||||||
6302 | isOperationLegalOrCustom(ISD::MULHS, HiLoVT); | ||||||||||
6303 | bool HasMULHU = (Kind == MulExpansionKind::Always) || | ||||||||||
6304 | isOperationLegalOrCustom(ISD::MULHU, HiLoVT); | ||||||||||
6305 | bool HasSMUL_LOHI = (Kind == MulExpansionKind::Always) || | ||||||||||
6306 | isOperationLegalOrCustom(ISD::SMUL_LOHI, HiLoVT); | ||||||||||
6307 | bool HasUMUL_LOHI = (Kind == MulExpansionKind::Always) || | ||||||||||
6308 | isOperationLegalOrCustom(ISD::UMUL_LOHI, HiLoVT); | ||||||||||
6309 | |||||||||||
6310 | if (!HasMULHU && !HasMULHS && !HasUMUL_LOHI && !HasSMUL_LOHI) | ||||||||||
6311 | return false; | ||||||||||
6312 | |||||||||||
6313 | unsigned OuterBitSize = VT.getScalarSizeInBits(); | ||||||||||
6314 | unsigned InnerBitSize = HiLoVT.getScalarSizeInBits(); | ||||||||||
6315 | |||||||||||
6316 | // LL, LH, RL, and RH must be either all NULL or all set to a value. | ||||||||||
6317 | assert((LL.getNode() && LH.getNode() && RL.getNode() && RH.getNode()) ||(static_cast <bool> ((LL.getNode() && LH.getNode () && RL.getNode() && RH.getNode()) || (!LL.getNode () && !LH.getNode() && !RL.getNode() && !RH.getNode())) ? void (0) : __assert_fail ("(LL.getNode() && LH.getNode() && RL.getNode() && RH.getNode()) || (!LL.getNode() && !LH.getNode() && !RL.getNode() && !RH.getNode())" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 6318, __extension__ __PRETTY_FUNCTION__)) | ||||||||||
6318 | (!LL.getNode() && !LH.getNode() && !RL.getNode() && !RH.getNode()))(static_cast <bool> ((LL.getNode() && LH.getNode () && RL.getNode() && RH.getNode()) || (!LL.getNode () && !LH.getNode() && !RL.getNode() && !RH.getNode())) ? void (0) : __assert_fail ("(LL.getNode() && LH.getNode() && RL.getNode() && RH.getNode()) || (!LL.getNode() && !LH.getNode() && !RL.getNode() && !RH.getNode())" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 6318, __extension__ __PRETTY_FUNCTION__)); | ||||||||||
6319 | |||||||||||
6320 | SDVTList VTs = DAG.getVTList(HiLoVT, HiLoVT); | ||||||||||
6321 | auto MakeMUL_LOHI = [&](SDValue L, SDValue R, SDValue &Lo, SDValue &Hi, | ||||||||||
6322 | bool Signed) -> bool { | ||||||||||
6323 | if ((Signed && HasSMUL_LOHI) || (!Signed && HasUMUL_LOHI)) { | ||||||||||
6324 | Lo = DAG.getNode(Signed ? ISD::SMUL_LOHI : ISD::UMUL_LOHI, dl, VTs, L, R); | ||||||||||
6325 | Hi = SDValue(Lo.getNode(), 1); | ||||||||||
6326 | return true; | ||||||||||
6327 | } | ||||||||||
6328 | if ((Signed && HasMULHS) || (!Signed && HasMULHU)) { | ||||||||||
6329 | Lo = DAG.getNode(ISD::MUL, dl, HiLoVT, L, R); | ||||||||||
6330 | Hi = DAG.getNode(Signed ? ISD::MULHS : ISD::MULHU, dl, HiLoVT, L, R); | ||||||||||
6331 | return true; | ||||||||||
6332 | } | ||||||||||
6333 | return false; | ||||||||||
6334 | }; | ||||||||||
6335 | |||||||||||
6336 | SDValue Lo, Hi; | ||||||||||
6337 | |||||||||||
6338 | if (!LL.getNode() && !RL.getNode() && | ||||||||||
6339 | isOperationLegalOrCustom(ISD::TRUNCATE, HiLoVT)) { | ||||||||||
6340 | LL = DAG.getNode(ISD::TRUNCATE, dl, HiLoVT, LHS); | ||||||||||
6341 | RL = DAG.getNode(ISD::TRUNCATE, dl, HiLoVT, RHS); | ||||||||||
6342 | } | ||||||||||
6343 | |||||||||||
6344 | if (!LL.getNode()) | ||||||||||
6345 | return false; | ||||||||||
6346 | |||||||||||
6347 | APInt HighMask = APInt::getHighBitsSet(OuterBitSize, InnerBitSize); | ||||||||||
6348 | if (DAG.MaskedValueIsZero(LHS, HighMask) && | ||||||||||
6349 | DAG.MaskedValueIsZero(RHS, HighMask)) { | ||||||||||
6350 | // The inputs are both zero-extended. | ||||||||||
6351 | if (MakeMUL_LOHI(LL, RL, Lo, Hi, false)) { | ||||||||||
6352 | Result.push_back(Lo); | ||||||||||
6353 | Result.push_back(Hi); | ||||||||||
6354 | if (Opcode != ISD::MUL) { | ||||||||||
6355 | SDValue Zero = DAG.getConstant(0, dl, HiLoVT); | ||||||||||
6356 | Result.push_back(Zero); | ||||||||||
6357 | Result.push_back(Zero); | ||||||||||
6358 | } | ||||||||||
6359 | return true; | ||||||||||
6360 | } | ||||||||||
6361 | } | ||||||||||
6362 | |||||||||||
6363 | if (!VT.isVector() && Opcode == ISD::MUL && | ||||||||||
6364 | DAG.ComputeNumSignBits(LHS) > InnerBitSize && | ||||||||||
6365 | DAG.ComputeNumSignBits(RHS) > InnerBitSize) { | ||||||||||
6366 | // The input values are both sign-extended. | ||||||||||
6367 | // TODO non-MUL case? | ||||||||||
6368 | if (MakeMUL_LOHI(LL, RL, Lo, Hi, true)) { | ||||||||||
6369 | Result.push_back(Lo); | ||||||||||
6370 | Result.push_back(Hi); | ||||||||||
6371 | return true; | ||||||||||
6372 | } | ||||||||||
6373 | } | ||||||||||
6374 | |||||||||||
6375 | unsigned ShiftAmount = OuterBitSize - InnerBitSize; | ||||||||||
6376 | EVT ShiftAmountTy = getShiftAmountTy(VT, DAG.getDataLayout()); | ||||||||||
6377 | if (APInt::getMaxValue(ShiftAmountTy.getSizeInBits()).ult(ShiftAmount)) { | ||||||||||
6378 | // FIXME getShiftAmountTy does not always return a sensible result when VT | ||||||||||
6379 | // is an illegal type, and so the type may be too small to fit the shift | ||||||||||
6380 | // amount. Override it with i32. The shift will have to be legalized. | ||||||||||
6381 | ShiftAmountTy = MVT::i32; | ||||||||||
6382 | } | ||||||||||
6383 | SDValue Shift = DAG.getConstant(ShiftAmount, dl, ShiftAmountTy); | ||||||||||
6384 | |||||||||||
6385 | if (!LH.getNode() && !RH.getNode() && | ||||||||||
6386 | isOperationLegalOrCustom(ISD::SRL, VT) && | ||||||||||
6387 | isOperationLegalOrCustom(ISD::TRUNCATE, HiLoVT)) { | ||||||||||
6388 | LH = DAG.getNode(ISD::SRL, dl, VT, LHS, Shift); | ||||||||||
6389 | LH = DAG.getNode(ISD::TRUNCATE, dl, HiLoVT, LH); | ||||||||||
6390 | RH = DAG.getNode(ISD::SRL, dl, VT, RHS, Shift); | ||||||||||
6391 | RH = DAG.getNode(ISD::TRUNCATE, dl, HiLoVT, RH); | ||||||||||
6392 | } | ||||||||||
6393 | |||||||||||
6394 | if (!LH.getNode()) | ||||||||||
6395 | return false; | ||||||||||
6396 | |||||||||||
6397 | if (!MakeMUL_LOHI(LL, RL, Lo, Hi, false)) | ||||||||||
6398 | return false; | ||||||||||
6399 | |||||||||||
6400 | Result.push_back(Lo); | ||||||||||
6401 | |||||||||||
6402 | if (Opcode == ISD::MUL) { | ||||||||||
6403 | RH = DAG.getNode(ISD::MUL, dl, HiLoVT, LL, RH); | ||||||||||
6404 | LH = DAG.getNode(ISD::MUL, dl, HiLoVT, LH, RL); | ||||||||||
6405 | Hi = DAG.getNode(ISD::ADD, dl, HiLoVT, Hi, RH); | ||||||||||
6406 | Hi = DAG.getNode(ISD::ADD, dl, HiLoVT, Hi, LH); | ||||||||||
6407 | Result.push_back(Hi); | ||||||||||
6408 | return true; | ||||||||||
6409 | } | ||||||||||
6410 | |||||||||||
6411 | // Compute the full width result. | ||||||||||
6412 | auto Merge = [&](SDValue Lo, SDValue Hi) -> SDValue { | ||||||||||
6413 | Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Lo); | ||||||||||
6414 | Hi = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Hi); | ||||||||||
6415 | Hi = DAG.getNode(ISD::SHL, dl, VT, Hi, Shift); | ||||||||||
6416 | return DAG.getNode(ISD::OR, dl, VT, Lo, Hi); | ||||||||||
6417 | }; | ||||||||||
6418 | |||||||||||
6419 | SDValue Next = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Hi); | ||||||||||
6420 | if (!MakeMUL_LOHI(LL, RH, Lo, Hi, false)) | ||||||||||
6421 | return false; | ||||||||||
6422 | |||||||||||
6423 | // This is effectively the add part of a multiply-add of half-sized operands, | ||||||||||
6424 | // so it cannot overflow. | ||||||||||
6425 | Next = DAG.getNode(ISD::ADD, dl, VT, Next, Merge(Lo, Hi)); | ||||||||||
6426 | |||||||||||
6427 | if (!MakeMUL_LOHI(LH, RL, Lo, Hi, false)) | ||||||||||
6428 | return false; | ||||||||||
6429 | |||||||||||
6430 | SDValue Zero = DAG.getConstant(0, dl, HiLoVT); | ||||||||||
6431 | EVT BoolType = getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT); | ||||||||||
6432 | |||||||||||
6433 | bool UseGlue = (isOperationLegalOrCustom(ISD::ADDC, VT) && | ||||||||||
6434 | isOperationLegalOrCustom(ISD::ADDE, VT)); | ||||||||||
6435 | if (UseGlue) | ||||||||||
6436 | Next = DAG.getNode(ISD::ADDC, dl, DAG.getVTList(VT, MVT::Glue), Next, | ||||||||||
6437 | Merge(Lo, Hi)); | ||||||||||
6438 | else | ||||||||||
6439 | Next = DAG.getNode(ISD::ADDCARRY, dl, DAG.getVTList(VT, BoolType), Next, | ||||||||||
6440 | Merge(Lo, Hi), DAG.getConstant(0, dl, BoolType)); | ||||||||||
6441 | |||||||||||
6442 | SDValue Carry = Next.getValue(1); | ||||||||||
6443 | Result.push_back(DAG.getNode(ISD::TRUNCATE, dl, HiLoVT, Next)); | ||||||||||
6444 | Next = DAG.getNode(ISD::SRL, dl, VT, Next, Shift); | ||||||||||
6445 | |||||||||||
6446 | if (!MakeMUL_LOHI(LH, RH, Lo, Hi, Opcode == ISD::SMUL_LOHI)) | ||||||||||
6447 | return false; | ||||||||||
6448 | |||||||||||
6449 | if (UseGlue) | ||||||||||
6450 | Hi = DAG.getNode(ISD::ADDE, dl, DAG.getVTList(HiLoVT, MVT::Glue), Hi, Zero, | ||||||||||
6451 | Carry); | ||||||||||
6452 | else | ||||||||||
6453 | Hi = DAG.getNode(ISD::ADDCARRY, dl, DAG.getVTList(HiLoVT, BoolType), Hi, | ||||||||||
6454 | Zero, Carry); | ||||||||||
6455 | |||||||||||
6456 | Next = DAG.getNode(ISD::ADD, dl, VT, Next, Merge(Lo, Hi)); | ||||||||||
6457 | |||||||||||
6458 | if (Opcode == ISD::SMUL_LOHI) { | ||||||||||
6459 | SDValue NextSub = DAG.getNode(ISD::SUB, dl, VT, Next, | ||||||||||
6460 | DAG.getNode(ISD::ZERO_EXTEND, dl, VT, RL)); | ||||||||||
6461 | Next = DAG.getSelectCC(dl, LH, Zero, NextSub, Next, ISD::SETLT); | ||||||||||
6462 | |||||||||||
6463 | NextSub = DAG.getNode(ISD::SUB, dl, VT, Next, | ||||||||||
6464 | DAG.getNode(ISD::ZERO_EXTEND, dl, VT, LL)); | ||||||||||
6465 | Next = DAG.getSelectCC(dl, RH, Zero, NextSub, Next, ISD::SETLT); | ||||||||||
6466 | } | ||||||||||
6467 | |||||||||||
6468 | Result.push_back(DAG.getNode(ISD::TRUNCATE, dl, HiLoVT, Next)); | ||||||||||
6469 | Next = DAG.getNode(ISD::SRL, dl, VT, Next, Shift); | ||||||||||
6470 | Result.push_back(DAG.getNode(ISD::TRUNCATE, dl, HiLoVT, Next)); | ||||||||||
6471 | return true; | ||||||||||
6472 | } | ||||||||||
6473 | |||||||||||
6474 | bool TargetLowering::expandMUL(SDNode *N, SDValue &Lo, SDValue &Hi, EVT HiLoVT, | ||||||||||
6475 | SelectionDAG &DAG, MulExpansionKind Kind, | ||||||||||
6476 | SDValue LL, SDValue LH, SDValue RL, | ||||||||||
6477 | SDValue RH) const { | ||||||||||
6478 | SmallVector<SDValue, 2> Result; | ||||||||||
6479 | bool Ok = expandMUL_LOHI(N->getOpcode(), N->getValueType(0), SDLoc(N), | ||||||||||
6480 | N->getOperand(0), N->getOperand(1), Result, HiLoVT, | ||||||||||
6481 | DAG, Kind, LL, LH, RL, RH); | ||||||||||
6482 | if (Ok) { | ||||||||||
6483 | assert(Result.size() == 2)(static_cast <bool> (Result.size() == 2) ? void (0) : __assert_fail ("Result.size() == 2", "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 6483, __extension__ __PRETTY_FUNCTION__)); | ||||||||||
6484 | Lo = Result[0]; | ||||||||||
6485 | Hi = Result[1]; | ||||||||||
6486 | } | ||||||||||
6487 | return Ok; | ||||||||||
6488 | } | ||||||||||
6489 | |||||||||||
6490 | // Check that (every element of) Z is undef or not an exact multiple of BW. | ||||||||||
6491 | static bool isNonZeroModBitWidthOrUndef(SDValue Z, unsigned BW) { | ||||||||||
6492 | return ISD::matchUnaryPredicate( | ||||||||||
6493 | Z, | ||||||||||
6494 | [=](ConstantSDNode *C) { return !C || C->getAPIntValue().urem(BW) != 0; }, | ||||||||||
6495 | true); | ||||||||||
6496 | } | ||||||||||
6497 | |||||||||||
6498 | bool TargetLowering::expandFunnelShift(SDNode *Node, SDValue &Result, | ||||||||||
6499 | SelectionDAG &DAG) const { | ||||||||||
6500 | EVT VT = Node->getValueType(0); | ||||||||||
6501 | |||||||||||
6502 | if (VT.isVector() && (!isOperationLegalOrCustom(ISD::SHL, VT) || | ||||||||||
6503 | !isOperationLegalOrCustom(ISD::SRL, VT) || | ||||||||||
6504 | !isOperationLegalOrCustom(ISD::SUB, VT) || | ||||||||||
6505 | !isOperationLegalOrCustomOrPromote(ISD::OR, VT))) | ||||||||||
6506 | return false; | ||||||||||
6507 | |||||||||||
6508 | SDValue X = Node->getOperand(0); | ||||||||||
6509 | SDValue Y = Node->getOperand(1); | ||||||||||
6510 | SDValue Z = Node->getOperand(2); | ||||||||||
6511 | |||||||||||
6512 | unsigned BW = VT.getScalarSizeInBits(); | ||||||||||
6513 | bool IsFSHL = Node->getOpcode() == ISD::FSHL; | ||||||||||
6514 | SDLoc DL(SDValue(Node, 0)); | ||||||||||
6515 | |||||||||||
6516 | EVT ShVT = Z.getValueType(); | ||||||||||
6517 | |||||||||||
6518 | // If a funnel shift in the other direction is more supported, use it. | ||||||||||
6519 | unsigned RevOpcode = IsFSHL ? ISD::FSHR : ISD::FSHL; | ||||||||||
6520 | if (!isOperationLegalOrCustom(Node->getOpcode(), VT) && | ||||||||||
6521 | isOperationLegalOrCustom(RevOpcode, VT) && isPowerOf2_32(BW)) { | ||||||||||
6522 | if (isNonZeroModBitWidthOrUndef(Z, BW)) { | ||||||||||
6523 | // fshl X, Y, Z -> fshr X, Y, -Z | ||||||||||
6524 | // fshr X, Y, Z -> fshl X, Y, -Z | ||||||||||
6525 | SDValue Zero = DAG.getConstant(0, DL, ShVT); | ||||||||||
6526 | Z = DAG.getNode(ISD::SUB, DL, VT, Zero, Z); | ||||||||||
6527 | } else { | ||||||||||
6528 | // fshl X, Y, Z -> fshr (srl X, 1), (fshr X, Y, 1), ~Z | ||||||||||
6529 | // fshr X, Y, Z -> fshl (fshl X, Y, 1), (shl Y, 1), ~Z | ||||||||||
6530 | SDValue One = DAG.getConstant(1, DL, ShVT); | ||||||||||
6531 | if (IsFSHL) { | ||||||||||
6532 | Y = DAG.getNode(RevOpcode, DL, VT, X, Y, One); | ||||||||||
6533 | X = DAG.getNode(ISD::SRL, DL, VT, X, One); | ||||||||||
6534 | } else { | ||||||||||
6535 | X = DAG.getNode(RevOpcode, DL, VT, X, Y, One); | ||||||||||
6536 | Y = DAG.getNode(ISD::SHL, DL, VT, Y, One); | ||||||||||
6537 | } | ||||||||||
6538 | Z = DAG.getNOT(DL, Z, ShVT); | ||||||||||
6539 | } | ||||||||||
6540 | Result = DAG.getNode(RevOpcode, DL, VT, X, Y, Z); | ||||||||||
6541 | return true; | ||||||||||
6542 | } | ||||||||||
6543 | |||||||||||
6544 | SDValue ShX, ShY; | ||||||||||
6545 | SDValue ShAmt, InvShAmt; | ||||||||||
6546 | if (isNonZeroModBitWidthOrUndef(Z, BW)) { | ||||||||||
6547 | // fshl: X << C | Y >> (BW - C) | ||||||||||
6548 | // fshr: X << (BW - C) | Y >> C | ||||||||||
6549 | // where C = Z % BW is not zero | ||||||||||
6550 | SDValue BitWidthC = DAG.getConstant(BW, DL, ShVT); | ||||||||||
6551 | ShAmt = DAG.getNode(ISD::UREM, DL, ShVT, Z, BitWidthC); | ||||||||||
6552 | InvShAmt = DAG.getNode(ISD::SUB, DL, ShVT, BitWidthC, ShAmt); | ||||||||||
6553 | ShX = DAG.getNode(ISD::SHL, DL, VT, X, IsFSHL ? ShAmt : InvShAmt); | ||||||||||
6554 | ShY = DAG.getNode(ISD::SRL, DL, VT, Y, IsFSHL ? InvShAmt : ShAmt); | ||||||||||
6555 | } else { | ||||||||||
6556 | // fshl: X << (Z % BW) | Y >> 1 >> (BW - 1 - (Z % BW)) | ||||||||||
6557 | // fshr: X << 1 << (BW - 1 - (Z % BW)) | Y >> (Z % BW) | ||||||||||
6558 | SDValue Mask = DAG.getConstant(BW - 1, DL, ShVT); | ||||||||||
6559 | if (isPowerOf2_32(BW)) { | ||||||||||
6560 | // Z % BW -> Z & (BW - 1) | ||||||||||
6561 | ShAmt = DAG.getNode(ISD::AND, DL, ShVT, Z, Mask); | ||||||||||
6562 | // (BW - 1) - (Z % BW) -> ~Z & (BW - 1) | ||||||||||
6563 | InvShAmt = DAG.getNode(ISD::AND, DL, ShVT, DAG.getNOT(DL, Z, ShVT), Mask); | ||||||||||
6564 | } else { | ||||||||||
6565 | SDValue BitWidthC = DAG.getConstant(BW, DL, ShVT); | ||||||||||
6566 | ShAmt = DAG.getNode(ISD::UREM, DL, ShVT, Z, BitWidthC); | ||||||||||
6567 | InvShAmt = DAG.getNode(ISD::SUB, DL, ShVT, Mask, ShAmt); | ||||||||||
6568 | } | ||||||||||
6569 | |||||||||||
6570 | SDValue One = DAG.getConstant(1, DL, ShVT); | ||||||||||
6571 | if (IsFSHL) { | ||||||||||
6572 | ShX = DAG.getNode(ISD::SHL, DL, VT, X, ShAmt); | ||||||||||
6573 | SDValue ShY1 = DAG.getNode(ISD::SRL, DL, VT, Y, One); | ||||||||||
6574 | ShY = DAG.getNode(ISD::SRL, DL, VT, ShY1, InvShAmt); | ||||||||||
6575 | } else { | ||||||||||
6576 | SDValue ShX1 = DAG.getNode(ISD::SHL, DL, VT, X, One); | ||||||||||
6577 | ShX = DAG.getNode(ISD::SHL, DL, VT, ShX1, InvShAmt); | ||||||||||
6578 | ShY = DAG.getNode(ISD::SRL, DL, VT, Y, ShAmt); | ||||||||||
6579 | } | ||||||||||
6580 | } | ||||||||||
6581 | Result = DAG.getNode(ISD::OR, DL, VT, ShX, ShY); | ||||||||||
6582 | return true; | ||||||||||
6583 | } | ||||||||||
6584 | |||||||||||
6585 | // TODO: Merge with expandFunnelShift. | ||||||||||
6586 | bool TargetLowering::expandROT(SDNode *Node, bool AllowVectorOps, | ||||||||||
6587 | SDValue &Result, SelectionDAG &DAG) const { | ||||||||||
6588 | EVT VT = Node->getValueType(0); | ||||||||||
6589 | unsigned EltSizeInBits = VT.getScalarSizeInBits(); | ||||||||||
6590 | bool IsLeft = Node->getOpcode() == ISD::ROTL; | ||||||||||
6591 | SDValue Op0 = Node->getOperand(0); | ||||||||||
6592 | SDValue Op1 = Node->getOperand(1); | ||||||||||
6593 | SDLoc DL(SDValue(Node, 0)); | ||||||||||
6594 | |||||||||||
6595 | EVT ShVT = Op1.getValueType(); | ||||||||||
6596 | SDValue Zero = DAG.getConstant(0, DL, ShVT); | ||||||||||
6597 | |||||||||||
6598 | // If a rotate in the other direction is supported, use it. | ||||||||||
6599 | unsigned RevRot = IsLeft ? ISD::ROTR : ISD::ROTL; | ||||||||||
6600 | if (isOperationLegalOrCustom(RevRot, VT) && isPowerOf2_32(EltSizeInBits)) { | ||||||||||
6601 | SDValue Sub = DAG.getNode(ISD::SUB, DL, ShVT, Zero, Op1); | ||||||||||
6602 | Result = DAG.getNode(RevRot, DL, VT, Op0, Sub); | ||||||||||
6603 | return true; | ||||||||||
6604 | } | ||||||||||
6605 | |||||||||||
6606 | if (!AllowVectorOps && VT.isVector() && | ||||||||||
6607 | (!isOperationLegalOrCustom(ISD::SHL, VT) || | ||||||||||
6608 | !isOperationLegalOrCustom(ISD::SRL, VT) || | ||||||||||
6609 | !isOperationLegalOrCustom(ISD::SUB, VT) || | ||||||||||
6610 | !isOperationLegalOrCustomOrPromote(ISD::OR, VT) || | ||||||||||
6611 | !isOperationLegalOrCustomOrPromote(ISD::AND, VT))) | ||||||||||
6612 | return false; | ||||||||||
6613 | |||||||||||
6614 | unsigned ShOpc = IsLeft ? ISD::SHL : ISD::SRL; | ||||||||||
6615 | unsigned HsOpc = IsLeft ? ISD::SRL : ISD::SHL; | ||||||||||
6616 | SDValue BitWidthMinusOneC = DAG.getConstant(EltSizeInBits - 1, DL, ShVT); | ||||||||||
6617 | SDValue ShVal; | ||||||||||
6618 | SDValue HsVal; | ||||||||||
6619 | if (isPowerOf2_32(EltSizeInBits)) { | ||||||||||
6620 | // (rotl x, c) -> x << (c & (w - 1)) | x >> (-c & (w - 1)) | ||||||||||
6621 | // (rotr x, c) -> x >> (c & (w - 1)) | x << (-c & (w - 1)) | ||||||||||
6622 | SDValue NegOp1 = DAG.getNode(ISD::SUB, DL, ShVT, Zero, Op1); | ||||||||||
6623 | SDValue ShAmt = DAG.getNode(ISD::AND, DL, ShVT, Op1, BitWidthMinusOneC); | ||||||||||
6624 | ShVal = DAG.getNode(ShOpc, DL, VT, Op0, ShAmt); | ||||||||||
6625 | SDValue HsAmt = DAG.getNode(ISD::AND, DL, ShVT, NegOp1, BitWidthMinusOneC); | ||||||||||
6626 | HsVal = DAG.getNode(HsOpc, DL, VT, Op0, HsAmt); | ||||||||||
6627 | } else { | ||||||||||
6628 | // (rotl x, c) -> x << (c % w) | x >> 1 >> (w - 1 - (c % w)) | ||||||||||
6629 | // (rotr x, c) -> x >> (c % w) | x << 1 << (w - 1 - (c % w)) | ||||||||||
6630 | SDValue BitWidthC = DAG.getConstant(EltSizeInBits, DL, ShVT); | ||||||||||
6631 | SDValue ShAmt = DAG.getNode(ISD::UREM, DL, ShVT, Op1, BitWidthC); | ||||||||||
6632 | ShVal = DAG.getNode(ShOpc, DL, VT, Op0, ShAmt); | ||||||||||
6633 | SDValue HsAmt = DAG.getNode(ISD::SUB, DL, ShVT, BitWidthMinusOneC, ShAmt); | ||||||||||
6634 | SDValue One = DAG.getConstant(1, DL, ShVT); | ||||||||||
6635 | HsVal = | ||||||||||
6636 | DAG.getNode(HsOpc, DL, VT, DAG.getNode(HsOpc, DL, VT, Op0, One), HsAmt); | ||||||||||
6637 | } | ||||||||||
6638 | Result = DAG.getNode(ISD::OR, DL, VT, ShVal, HsVal); | ||||||||||
6639 | return true; | ||||||||||
6640 | } | ||||||||||
6641 | |||||||||||
6642 | void TargetLowering::expandShiftParts(SDNode *Node, SDValue &Lo, SDValue &Hi, | ||||||||||
6643 | SelectionDAG &DAG) const { | ||||||||||
6644 | assert(Node->getNumOperands() == 3 && "Not a double-shift!")(static_cast <bool> (Node->getNumOperands() == 3 && "Not a double-shift!") ? void (0) : __assert_fail ("Node->getNumOperands() == 3 && \"Not a double-shift!\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 6644, __extension__ __PRETTY_FUNCTION__)); | ||||||||||
6645 | EVT VT = Node->getValueType(0); | ||||||||||
6646 | unsigned VTBits = VT.getScalarSizeInBits(); | ||||||||||
6647 | assert(isPowerOf2_32(VTBits) && "Power-of-two integer type expected")(static_cast <bool> (isPowerOf2_32(VTBits) && "Power-of-two integer type expected" ) ? void (0) : __assert_fail ("isPowerOf2_32(VTBits) && \"Power-of-two integer type expected\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 6647, __extension__ __PRETTY_FUNCTION__)); | ||||||||||
6648 | |||||||||||
6649 | bool IsSHL = Node->getOpcode() == ISD::SHL_PARTS; | ||||||||||
6650 | bool IsSRA = Node->getOpcode() == ISD::SRA_PARTS; | ||||||||||
6651 | SDValue ShOpLo = Node->getOperand(0); | ||||||||||
6652 | SDValue ShOpHi = Node->getOperand(1); | ||||||||||
6653 | SDValue ShAmt = Node->getOperand(2); | ||||||||||
6654 | EVT ShAmtVT = ShAmt.getValueType(); | ||||||||||
6655 | EVT ShAmtCCVT = | ||||||||||
6656 | getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), ShAmtVT); | ||||||||||
6657 | SDLoc dl(Node); | ||||||||||
6658 | |||||||||||
6659 | // ISD::FSHL and ISD::FSHR have defined overflow behavior but ISD::SHL and | ||||||||||
6660 | // ISD::SRA/L nodes haven't. Insert an AND to be safe, it's usually optimized | ||||||||||
6661 | // away during isel. | ||||||||||
6662 | SDValue SafeShAmt = DAG.getNode(ISD::AND, dl, ShAmtVT, ShAmt, | ||||||||||
6663 | DAG.getConstant(VTBits - 1, dl, ShAmtVT)); | ||||||||||
6664 | SDValue Tmp1 = IsSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi, | ||||||||||
6665 | DAG.getConstant(VTBits - 1, dl, ShAmtVT)) | ||||||||||
6666 | : DAG.getConstant(0, dl, VT); | ||||||||||
6667 | |||||||||||
6668 | SDValue Tmp2, Tmp3; | ||||||||||
6669 | if (IsSHL) { | ||||||||||
6670 | Tmp2 = DAG.getNode(ISD::FSHL, dl, VT, ShOpHi, ShOpLo, ShAmt); | ||||||||||
6671 | Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, SafeShAmt); | ||||||||||
6672 | } else { | ||||||||||
6673 | Tmp2 = DAG.getNode(ISD::FSHR, dl, VT, ShOpHi, ShOpLo, ShAmt); | ||||||||||
6674 | Tmp3 = DAG.getNode(IsSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, SafeShAmt); | ||||||||||
6675 | } | ||||||||||
6676 | |||||||||||
6677 | // If the shift amount is larger or equal than the width of a part we don't | ||||||||||
6678 | // use the result from the FSHL/FSHR. Insert a test and select the appropriate | ||||||||||
6679 | // values for large shift amounts. | ||||||||||
6680 | SDValue AndNode = DAG.getNode(ISD::AND, dl, ShAmtVT, ShAmt, | ||||||||||
6681 | DAG.getConstant(VTBits, dl, ShAmtVT)); | ||||||||||
6682 | SDValue Cond = DAG.getSetCC(dl, ShAmtCCVT, AndNode, | ||||||||||
6683 | DAG.getConstant(0, dl, ShAmtVT), ISD::SETNE); | ||||||||||
6684 | |||||||||||
6685 | if (IsSHL) { | ||||||||||
6686 | Hi = DAG.getNode(ISD::SELECT, dl, VT, Cond, Tmp3, Tmp2); | ||||||||||
6687 | Lo = DAG.getNode(ISD::SELECT, dl, VT, Cond, Tmp1, Tmp3); | ||||||||||
6688 | } else { | ||||||||||
6689 | Lo = DAG.getNode(ISD::SELECT, dl, VT, Cond, Tmp3, Tmp2); | ||||||||||
6690 | Hi = DAG.getNode(ISD::SELECT, dl, VT, Cond, Tmp1, Tmp3); | ||||||||||
6691 | } | ||||||||||
6692 | } | ||||||||||
6693 | |||||||||||
6694 | bool TargetLowering::expandFP_TO_SINT(SDNode *Node, SDValue &Result, | ||||||||||
6695 | SelectionDAG &DAG) const { | ||||||||||
6696 | unsigned OpNo = Node->isStrictFPOpcode() ? 1 : 0; | ||||||||||
6697 | SDValue Src = Node->getOperand(OpNo); | ||||||||||
6698 | EVT SrcVT = Src.getValueType(); | ||||||||||
6699 | EVT DstVT = Node->getValueType(0); | ||||||||||
6700 | SDLoc dl(SDValue(Node, 0)); | ||||||||||
6701 | |||||||||||
6702 | // FIXME: Only f32 to i64 conversions are supported. | ||||||||||
6703 | if (SrcVT != MVT::f32 || DstVT != MVT::i64) | ||||||||||
6704 | return false; | ||||||||||
6705 | |||||||||||
6706 | if (Node->isStrictFPOpcode()) | ||||||||||
6707 | // When a NaN is converted to an integer a trap is allowed. We can't | ||||||||||
6708 | // use this expansion here because it would eliminate that trap. Other | ||||||||||
6709 | // traps are also allowed and cannot be eliminated. See | ||||||||||
6710 | // IEEE 754-2008 sec 5.8. | ||||||||||
6711 | return false; | ||||||||||
6712 | |||||||||||
6713 | // Expand f32 -> i64 conversion | ||||||||||
6714 | // This algorithm comes from compiler-rt's implementation of fixsfdi: | ||||||||||
6715 | // https://github.com/llvm/llvm-project/blob/main/compiler-rt/lib/builtins/fixsfdi.c | ||||||||||
6716 | unsigned SrcEltBits = SrcVT.getScalarSizeInBits(); | ||||||||||
6717 | EVT IntVT = SrcVT.changeTypeToInteger(); | ||||||||||
6718 | EVT IntShVT = getShiftAmountTy(IntVT, DAG.getDataLayout()); | ||||||||||
6719 | |||||||||||
6720 | SDValue ExponentMask = DAG.getConstant(0x7F800000, dl, IntVT); | ||||||||||
6721 | SDValue ExponentLoBit = DAG.getConstant(23, dl, IntVT); | ||||||||||
6722 | SDValue Bias = DAG.getConstant(127, dl, IntVT); | ||||||||||
6723 | SDValue SignMask = DAG.getConstant(APInt::getSignMask(SrcEltBits), dl, IntVT); | ||||||||||
6724 | SDValue SignLowBit = DAG.getConstant(SrcEltBits - 1, dl, IntVT); | ||||||||||
6725 | SDValue MantissaMask = DAG.getConstant(0x007FFFFF, dl, IntVT); | ||||||||||
6726 | |||||||||||
6727 | SDValue Bits = DAG.getNode(ISD::BITCAST, dl, IntVT, Src); | ||||||||||
6728 | |||||||||||
6729 | SDValue ExponentBits = DAG.getNode( | ||||||||||
6730 | ISD::SRL, dl, IntVT, DAG.getNode(ISD::AND, dl, IntVT, Bits, ExponentMask), | ||||||||||
6731 | DAG.getZExtOrTrunc(ExponentLoBit, dl, IntShVT)); | ||||||||||
6732 | SDValue Exponent = DAG.getNode(ISD::SUB, dl, IntVT, ExponentBits, Bias); | ||||||||||
6733 | |||||||||||
6734 | SDValue Sign = DAG.getNode(ISD::SRA, dl, IntVT, | ||||||||||
6735 | DAG.getNode(ISD::AND, dl, IntVT, Bits, SignMask), | ||||||||||
6736 | DAG.getZExtOrTrunc(SignLowBit, dl, IntShVT)); | ||||||||||
6737 | Sign = DAG.getSExtOrTrunc(Sign, dl, DstVT); | ||||||||||
6738 | |||||||||||
6739 | SDValue R = DAG.getNode(ISD::OR, dl, IntVT, | ||||||||||
6740 | DAG.getNode(ISD::AND, dl, IntVT, Bits, MantissaMask), | ||||||||||
6741 | DAG.getConstant(0x00800000, dl, IntVT)); | ||||||||||
6742 | |||||||||||
6743 | R = DAG.getZExtOrTrunc(R, dl, DstVT); | ||||||||||
6744 | |||||||||||
6745 | R = DAG.getSelectCC( | ||||||||||
6746 | dl, Exponent, ExponentLoBit, | ||||||||||
6747 | DAG.getNode(ISD::SHL, dl, DstVT, R, | ||||||||||
6748 | DAG.getZExtOrTrunc( | ||||||||||
6749 | DAG.getNode(ISD::SUB, dl, IntVT, Exponent, ExponentLoBit), | ||||||||||
6750 | dl, IntShVT)), | ||||||||||
6751 | DAG.getNode(ISD::SRL, dl, DstVT, R, | ||||||||||
6752 | DAG.getZExtOrTrunc( | ||||||||||
6753 | DAG.getNode(ISD::SUB, dl, IntVT, ExponentLoBit, Exponent), | ||||||||||
6754 | dl, IntShVT)), | ||||||||||
6755 | ISD::SETGT); | ||||||||||
6756 | |||||||||||
6757 | SDValue Ret = DAG.getNode(ISD::SUB, dl, DstVT, | ||||||||||
6758 | DAG.getNode(ISD::XOR, dl, DstVT, R, Sign), Sign); | ||||||||||
6759 | |||||||||||
6760 | Result = DAG.getSelectCC(dl, Exponent, DAG.getConstant(0, dl, IntVT), | ||||||||||
6761 | DAG.getConstant(0, dl, DstVT), Ret, ISD::SETLT); | ||||||||||
6762 | return true; | ||||||||||
6763 | } | ||||||||||
6764 | |||||||||||
6765 | bool TargetLowering::expandFP_TO_UINT(SDNode *Node, SDValue &Result, | ||||||||||
6766 | SDValue &Chain, | ||||||||||
6767 | SelectionDAG &DAG) const { | ||||||||||
6768 | SDLoc dl(SDValue(Node, 0)); | ||||||||||
6769 | unsigned OpNo = Node->isStrictFPOpcode() ? 1 : 0; | ||||||||||
6770 | SDValue Src = Node->getOperand(OpNo); | ||||||||||
6771 | |||||||||||
6772 | EVT SrcVT = Src.getValueType(); | ||||||||||
6773 | EVT DstVT = Node->getValueType(0); | ||||||||||
6774 | EVT SetCCVT = | ||||||||||
6775 | getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), SrcVT); | ||||||||||
6776 | EVT DstSetCCVT = | ||||||||||
6777 | getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), DstVT); | ||||||||||
6778 | |||||||||||
6779 | // Only expand vector types if we have the appropriate vector bit operations. | ||||||||||
6780 | unsigned SIntOpcode = Node->isStrictFPOpcode() ? ISD::STRICT_FP_TO_SINT : | ||||||||||
6781 | ISD::FP_TO_SINT; | ||||||||||
6782 | if (DstVT.isVector() && (!isOperationLegalOrCustom(SIntOpcode, DstVT) || | ||||||||||
6783 | !isOperationLegalOrCustomOrPromote(ISD::XOR, SrcVT))) | ||||||||||
6784 | return false; | ||||||||||
6785 | |||||||||||
6786 | // If the maximum float value is smaller then the signed integer range, | ||||||||||
6787 | // the destination signmask can't be represented by the float, so we can | ||||||||||
6788 | // just use FP_TO_SINT directly. | ||||||||||
6789 | const fltSemantics &APFSem = DAG.EVTToAPFloatSemantics(SrcVT); | ||||||||||
6790 | APFloat APF(APFSem, APInt::getZero(SrcVT.getScalarSizeInBits())); | ||||||||||
6791 | APInt SignMask = APInt::getSignMask(DstVT.getScalarSizeInBits()); | ||||||||||
6792 | if (APFloat::opOverflow & | ||||||||||
6793 | APF.convertFromAPInt(SignMask, false, APFloat::rmNearestTiesToEven)) { | ||||||||||
6794 | if (Node->isStrictFPOpcode()) { | ||||||||||
6795 | Result = DAG.getNode(ISD::STRICT_FP_TO_SINT, dl, { DstVT, MVT::Other }, | ||||||||||
6796 | { Node->getOperand(0), Src }); | ||||||||||
6797 | Chain = Result.getValue(1); | ||||||||||
6798 | } else | ||||||||||
6799 | Result = DAG.getNode(ISD::FP_TO_SINT, dl, DstVT, Src); | ||||||||||
6800 | return true; | ||||||||||
6801 | } | ||||||||||
6802 | |||||||||||
6803 | // Don't expand it if there isn't cheap fsub instruction. | ||||||||||
6804 | if (!isOperationLegalOrCustom( | ||||||||||
6805 | Node->isStrictFPOpcode() ? ISD::STRICT_FSUB : ISD::FSUB, SrcVT)) | ||||||||||
6806 | return false; | ||||||||||
6807 | |||||||||||
6808 | SDValue Cst = DAG.getConstantFP(APF, dl, SrcVT); | ||||||||||
6809 | SDValue Sel; | ||||||||||
6810 | |||||||||||
6811 | if (Node->isStrictFPOpcode()) { | ||||||||||
6812 | Sel = DAG.getSetCC(dl, SetCCVT, Src, Cst, ISD::SETLT, | ||||||||||
6813 | Node->getOperand(0), /*IsSignaling*/ true); | ||||||||||
6814 | Chain = Sel.getValue(1); | ||||||||||
6815 | } else { | ||||||||||
6816 | Sel = DAG.getSetCC(dl, SetCCVT, Src, Cst, ISD::SETLT); | ||||||||||
6817 | } | ||||||||||
6818 | |||||||||||
6819 | bool Strict = Node->isStrictFPOpcode() || | ||||||||||
6820 | shouldUseStrictFP_TO_INT(SrcVT, DstVT, /*IsSigned*/ false); | ||||||||||
6821 | |||||||||||
6822 | if (Strict) { | ||||||||||
6823 | // Expand based on maximum range of FP_TO_SINT, if the value exceeds the | ||||||||||
6824 | // signmask then offset (the result of which should be fully representable). | ||||||||||
6825 | // Sel = Src < 0x8000000000000000 | ||||||||||
6826 | // FltOfs = select Sel, 0, 0x8000000000000000 | ||||||||||
6827 | // IntOfs = select Sel, 0, 0x8000000000000000 | ||||||||||
6828 | // Result = fp_to_sint(Src - FltOfs) ^ IntOfs | ||||||||||
6829 | |||||||||||
6830 | // TODO: Should any fast-math-flags be set for the FSUB? | ||||||||||
6831 | SDValue FltOfs = DAG.getSelect(dl, SrcVT, Sel, | ||||||||||
6832 | DAG.getConstantFP(0.0, dl, SrcVT), Cst); | ||||||||||
6833 | Sel = DAG.getBoolExtOrTrunc(Sel, dl, DstSetCCVT, DstVT); | ||||||||||
6834 | SDValue IntOfs = DAG.getSelect(dl, DstVT, Sel, | ||||||||||
6835 | DAG.getConstant(0, dl, DstVT), | ||||||||||
6836 | DAG.getConstant(SignMask, dl, DstVT)); | ||||||||||
6837 | SDValue SInt; | ||||||||||
6838 | if (Node->isStrictFPOpcode()) { | ||||||||||
6839 | SDValue Val = DAG.getNode(ISD::STRICT_FSUB, dl, { SrcVT, MVT::Other }, | ||||||||||
6840 | { Chain, Src, FltOfs }); | ||||||||||
6841 | SInt = DAG.getNode(ISD::STRICT_FP_TO_SINT, dl, { DstVT, MVT::Other }, | ||||||||||
6842 | { Val.getValue(1), Val }); | ||||||||||
6843 | Chain = SInt.getValue(1); | ||||||||||
6844 | } else { | ||||||||||
6845 | SDValue Val = DAG.getNode(ISD::FSUB, dl, SrcVT, Src, FltOfs); | ||||||||||
6846 | SInt = DAG.getNode(ISD::FP_TO_SINT, dl, DstVT, Val); | ||||||||||
6847 | } | ||||||||||
6848 | Result = DAG.getNode(ISD::XOR, dl, DstVT, SInt, IntOfs); | ||||||||||
6849 | } else { | ||||||||||
6850 | // Expand based on maximum range of FP_TO_SINT: | ||||||||||
6851 | // True = fp_to_sint(Src) | ||||||||||
6852 | // False = 0x8000000000000000 + fp_to_sint(Src - 0x8000000000000000) | ||||||||||
6853 | // Result = select (Src < 0x8000000000000000), True, False | ||||||||||
6854 | |||||||||||
6855 | SDValue True = DAG.getNode(ISD::FP_TO_SINT, dl, DstVT, Src); | ||||||||||
6856 | // TODO: Should any fast-math-flags be set for the FSUB? | ||||||||||
6857 | SDValue False = DAG.getNode(ISD::FP_TO_SINT, dl, DstVT, | ||||||||||
6858 | DAG.getNode(ISD::FSUB, dl, SrcVT, Src, Cst)); | ||||||||||
6859 | False = DAG.getNode(ISD::XOR, dl, DstVT, False, | ||||||||||
6860 | DAG.getConstant(SignMask, dl, DstVT)); | ||||||||||
6861 | Sel = DAG.getBoolExtOrTrunc(Sel, dl, DstSetCCVT, DstVT); | ||||||||||
6862 | Result = DAG.getSelect(dl, DstVT, Sel, True, False); | ||||||||||
6863 | } | ||||||||||
6864 | return true; | ||||||||||
6865 | } | ||||||||||
6866 | |||||||||||
6867 | bool TargetLowering::expandUINT_TO_FP(SDNode *Node, SDValue &Result, | ||||||||||
6868 | SDValue &Chain, | ||||||||||
6869 | SelectionDAG &DAG) const { | ||||||||||
6870 | // This transform is not correct for converting 0 when rounding mode is set | ||||||||||
6871 | // to round toward negative infinity which will produce -0.0. So disable under | ||||||||||
6872 | // strictfp. | ||||||||||
6873 | if (Node->isStrictFPOpcode()) | ||||||||||
6874 | return false; | ||||||||||
6875 | |||||||||||
6876 | SDValue Src = Node->getOperand(0); | ||||||||||
6877 | EVT SrcVT = Src.getValueType(); | ||||||||||
6878 | EVT DstVT = Node->getValueType(0); | ||||||||||
6879 | |||||||||||
6880 | if (SrcVT.getScalarType() != MVT::i64 || DstVT.getScalarType() != MVT::f64) | ||||||||||
6881 | return false; | ||||||||||
6882 | |||||||||||
6883 | // Only expand vector types if we have the appropriate vector bit operations. | ||||||||||
6884 | if (SrcVT.isVector() && (!isOperationLegalOrCustom(ISD::SRL, SrcVT) || | ||||||||||
6885 | !isOperationLegalOrCustom(ISD::FADD, DstVT) || | ||||||||||
6886 | !isOperationLegalOrCustom(ISD::FSUB, DstVT) || | ||||||||||
6887 | !isOperationLegalOrCustomOrPromote(ISD::OR, SrcVT) || | ||||||||||
6888 | !isOperationLegalOrCustomOrPromote(ISD::AND, SrcVT))) | ||||||||||
6889 | return false; | ||||||||||
6890 | |||||||||||
6891 | SDLoc dl(SDValue(Node, 0)); | ||||||||||
6892 | EVT ShiftVT = getShiftAmountTy(SrcVT, DAG.getDataLayout()); | ||||||||||
6893 | |||||||||||
6894 | // Implementation of unsigned i64 to f64 following the algorithm in | ||||||||||
6895 | // __floatundidf in compiler_rt. This implementation performs rounding | ||||||||||
6896 | // correctly in all rounding modes with the exception of converting 0 | ||||||||||
6897 | // when rounding toward negative infinity. In that case the fsub will produce | ||||||||||
6898 | // -0.0. This will be added to +0.0 and produce -0.0 which is incorrect. | ||||||||||
6899 | SDValue TwoP52 = DAG.getConstant(UINT64_C(0x4330000000000000)0x4330000000000000UL, dl, SrcVT); | ||||||||||
6900 | SDValue TwoP84PlusTwoP52 = DAG.getConstantFP( | ||||||||||
6901 | BitsToDouble(UINT64_C(0x4530000000100000)0x4530000000100000UL), dl, DstVT); | ||||||||||
6902 | SDValue TwoP84 = DAG.getConstant(UINT64_C(0x4530000000000000)0x4530000000000000UL, dl, SrcVT); | ||||||||||
6903 | SDValue LoMask = DAG.getConstant(UINT64_C(0x00000000FFFFFFFF)0x00000000FFFFFFFFUL, dl, SrcVT); | ||||||||||
6904 | SDValue HiShift = DAG.getConstant(32, dl, ShiftVT); | ||||||||||
6905 | |||||||||||
6906 | SDValue Lo = DAG.getNode(ISD::AND, dl, SrcVT, Src, LoMask); | ||||||||||
6907 | SDValue Hi = DAG.getNode(ISD::SRL, dl, SrcVT, Src, HiShift); | ||||||||||
6908 | SDValue LoOr = DAG.getNode(ISD::OR, dl, SrcVT, Lo, TwoP52); | ||||||||||
6909 | SDValue HiOr = DAG.getNode(ISD::OR, dl, SrcVT, Hi, TwoP84); | ||||||||||
6910 | SDValue LoFlt = DAG.getBitcast(DstVT, LoOr); | ||||||||||
6911 | SDValue HiFlt = DAG.getBitcast(DstVT, HiOr); | ||||||||||
6912 | SDValue HiSub = | ||||||||||
6913 | DAG.getNode(ISD::FSUB, dl, DstVT, HiFlt, TwoP84PlusTwoP52); | ||||||||||
6914 | Result = DAG.getNode(ISD::FADD, dl, DstVT, LoFlt, HiSub); | ||||||||||
6915 | return true; | ||||||||||
6916 | } | ||||||||||
6917 | |||||||||||
6918 | SDValue TargetLowering::expandFMINNUM_FMAXNUM(SDNode *Node, | ||||||||||
6919 | SelectionDAG &DAG) const { | ||||||||||
6920 | SDLoc dl(Node); | ||||||||||
6921 | unsigned NewOp = Node->getOpcode() == ISD::FMINNUM ? | ||||||||||
6922 | ISD::FMINNUM_IEEE : ISD::FMAXNUM_IEEE; | ||||||||||
6923 | EVT VT = Node->getValueType(0); | ||||||||||
6924 | |||||||||||
6925 | if (VT.isScalableVector()) | ||||||||||
6926 | report_fatal_error( | ||||||||||
6927 | "Expanding fminnum/fmaxnum for scalable vectors is undefined."); | ||||||||||
6928 | |||||||||||
6929 | if (isOperationLegalOrCustom(NewOp, VT)) { | ||||||||||
6930 | SDValue Quiet0 = Node->getOperand(0); | ||||||||||
6931 | SDValue Quiet1 = Node->getOperand(1); | ||||||||||
6932 | |||||||||||
6933 | if (!Node->getFlags().hasNoNaNs()) { | ||||||||||
6934 | // Insert canonicalizes if it's possible we need to quiet to get correct | ||||||||||
6935 | // sNaN behavior. | ||||||||||
6936 | if (!DAG.isKnownNeverSNaN(Quiet0)) { | ||||||||||
6937 | Quiet0 = DAG.getNode(ISD::FCANONICALIZE, dl, VT, Quiet0, | ||||||||||
6938 | Node->getFlags()); | ||||||||||
6939 | } | ||||||||||
6940 | if (!DAG.isKnownNeverSNaN(Quiet1)) { | ||||||||||
6941 | Quiet1 = DAG.getNode(ISD::FCANONICALIZE, dl, VT, Quiet1, | ||||||||||
6942 | Node->getFlags()); | ||||||||||
6943 | } | ||||||||||
6944 | } | ||||||||||
6945 | |||||||||||
6946 | return DAG.getNode(NewOp, dl, VT, Quiet0, Quiet1, Node->getFlags()); | ||||||||||
6947 | } | ||||||||||
6948 | |||||||||||
6949 | // If the target has FMINIMUM/FMAXIMUM but not FMINNUM/FMAXNUM use that | ||||||||||
6950 | // instead if there are no NaNs. | ||||||||||
6951 | if (Node->getFlags().hasNoNaNs()) { | ||||||||||
6952 | unsigned IEEE2018Op = | ||||||||||
6953 | Node->getOpcode() == ISD::FMINNUM ? ISD::FMINIMUM : ISD::FMAXIMUM; | ||||||||||
6954 | if (isOperationLegalOrCustom(IEEE2018Op, VT)) { | ||||||||||
6955 | return DAG.getNode(IEEE2018Op, dl, VT, Node->getOperand(0), | ||||||||||
6956 | Node->getOperand(1), Node->getFlags()); | ||||||||||
6957 | } | ||||||||||
6958 | } | ||||||||||
6959 | |||||||||||
6960 | // If none of the above worked, but there are no NaNs, then expand to | ||||||||||
6961 | // a compare/select sequence. This is required for correctness since | ||||||||||
6962 | // InstCombine might have canonicalized a fcmp+select sequence to a | ||||||||||
6963 | // FMINNUM/FMAXNUM node. If we were to fall through to the default | ||||||||||
6964 | // expansion to libcall, we might introduce a link-time dependency | ||||||||||
6965 | // on libm into a file that originally did not have one. | ||||||||||
6966 | if (Node->getFlags().hasNoNaNs()) { | ||||||||||
6967 | ISD::CondCode Pred = | ||||||||||
6968 | Node->getOpcode() == ISD::FMINNUM ? ISD::SETLT : ISD::SETGT; | ||||||||||
6969 | SDValue Op1 = Node->getOperand(0); | ||||||||||
6970 | SDValue Op2 = Node->getOperand(1); | ||||||||||
6971 | SDValue SelCC = DAG.getSelectCC(dl, Op1, Op2, Op1, Op2, Pred); | ||||||||||
6972 | // Copy FMF flags, but always set the no-signed-zeros flag | ||||||||||
6973 | // as this is implied by the FMINNUM/FMAXNUM semantics. | ||||||||||
6974 | SDNodeFlags Flags = Node->getFlags(); | ||||||||||
6975 | Flags.setNoSignedZeros(true); | ||||||||||
6976 | SelCC->setFlags(Flags); | ||||||||||
6977 | return SelCC; | ||||||||||
6978 | } | ||||||||||
6979 | |||||||||||
6980 | return SDValue(); | ||||||||||
6981 | } | ||||||||||
6982 | |||||||||||
6983 | // Only expand vector types if we have the appropriate vector bit operations. | ||||||||||
6984 | static bool canExpandVectorCTPOP(const TargetLowering &TLI, EVT VT) { | ||||||||||
6985 | assert(VT.isVector() && "Expected vector type")(static_cast <bool> (VT.isVector() && "Expected vector type" ) ? void (0) : __assert_fail ("VT.isVector() && \"Expected vector type\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 6985, __extension__ __PRETTY_FUNCTION__)); | ||||||||||
6986 | unsigned Len = VT.getScalarSizeInBits(); | ||||||||||
6987 | return TLI.isOperationLegalOrCustom(ISD::ADD, VT) && | ||||||||||
6988 | TLI.isOperationLegalOrCustom(ISD::SUB, VT) && | ||||||||||
6989 | TLI.isOperationLegalOrCustom(ISD::SRL, VT) && | ||||||||||
6990 | (Len == 8 || TLI.isOperationLegalOrCustom(ISD::MUL, VT)) && | ||||||||||
6991 | TLI.isOperationLegalOrCustomOrPromote(ISD::AND, VT); | ||||||||||
6992 | } | ||||||||||
6993 | |||||||||||
6994 | SDValue TargetLowering::expandCTPOP(SDNode *Node, SelectionDAG &DAG) const { | ||||||||||
6995 | SDLoc dl(Node); | ||||||||||
6996 | EVT VT = Node->getValueType(0); | ||||||||||
6997 | EVT ShVT = getShiftAmountTy(VT, DAG.getDataLayout()); | ||||||||||
6998 | SDValue Op = Node->getOperand(0); | ||||||||||
6999 | unsigned Len = VT.getScalarSizeInBits(); | ||||||||||
7000 | assert(VT.isInteger() && "CTPOP not implemented for this type.")(static_cast <bool> (VT.isInteger() && "CTPOP not implemented for this type." ) ? void (0) : __assert_fail ("VT.isInteger() && \"CTPOP not implemented for this type.\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 7000, __extension__ __PRETTY_FUNCTION__)); | ||||||||||
7001 | |||||||||||
7002 | // TODO: Add support for irregular type lengths. | ||||||||||
7003 | if (!(Len <= 128 && Len % 8 == 0)) | ||||||||||
7004 | return SDValue(); | ||||||||||
7005 | |||||||||||
7006 | // Only expand vector types if we have the appropriate vector bit operations. | ||||||||||
7007 | if (VT.isVector() && !canExpandVectorCTPOP(*this, VT)) | ||||||||||
7008 | return SDValue(); | ||||||||||
7009 | |||||||||||
7010 | // This is the "best" algorithm from | ||||||||||
7011 | // http://graphics.stanford.edu/~seander/bithacks.html#CountBitsSetParallel | ||||||||||
7012 | SDValue Mask55 = | ||||||||||
7013 | DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x55)), dl, VT); | ||||||||||
7014 | SDValue Mask33 = | ||||||||||
7015 | DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x33)), dl, VT); | ||||||||||
7016 | SDValue Mask0F = | ||||||||||
7017 | DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x0F)), dl, VT); | ||||||||||
7018 | SDValue Mask01 = | ||||||||||
7019 | DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x01)), dl, VT); | ||||||||||
7020 | |||||||||||
7021 | // v = v - ((v >> 1) & 0x55555555...) | ||||||||||
7022 | Op = DAG.getNode(ISD::SUB, dl, VT, Op, | ||||||||||
7023 | DAG.getNode(ISD::AND, dl, VT, | ||||||||||
7024 | DAG.getNode(ISD::SRL, dl, VT, Op, | ||||||||||
7025 | DAG.getConstant(1, dl, ShVT)), | ||||||||||
7026 | Mask55)); | ||||||||||
7027 | // v = (v & 0x33333333...) + ((v >> 2) & 0x33333333...) | ||||||||||
7028 | Op = DAG.getNode(ISD::ADD, dl, VT, DAG.getNode(ISD::AND, dl, VT, Op, Mask33), | ||||||||||
7029 | DAG.getNode(ISD::AND, dl, VT, | ||||||||||
7030 | DAG.getNode(ISD::SRL, dl, VT, Op, | ||||||||||
7031 | DAG.getConstant(2, dl, ShVT)), | ||||||||||
7032 | Mask33)); | ||||||||||
7033 | // v = (v + (v >> 4)) & 0x0F0F0F0F... | ||||||||||
7034 | Op = DAG.getNode(ISD::AND, dl, VT, | ||||||||||
7035 | DAG.getNode(ISD::ADD, dl, VT, Op, | ||||||||||
7036 | DAG.getNode(ISD::SRL, dl, VT, Op, | ||||||||||
7037 | DAG.getConstant(4, dl, ShVT))), | ||||||||||
7038 | Mask0F); | ||||||||||
7039 | // v = (v * 0x01010101...) >> (Len - 8) | ||||||||||
7040 | if (Len > 8) | ||||||||||
7041 | Op = | ||||||||||
7042 | DAG.getNode(ISD::SRL, dl, VT, DAG.getNode(ISD::MUL, dl, VT, Op, Mask01), | ||||||||||
7043 | DAG.getConstant(Len - 8, dl, ShVT)); | ||||||||||
7044 | |||||||||||
7045 | return Op; | ||||||||||
7046 | } | ||||||||||
7047 | |||||||||||
7048 | SDValue TargetLowering::expandCTLZ(SDNode *Node, SelectionDAG &DAG) const { | ||||||||||
7049 | SDLoc dl(Node); | ||||||||||
7050 | EVT VT = Node->getValueType(0); | ||||||||||
7051 | EVT ShVT = getShiftAmountTy(VT, DAG.getDataLayout()); | ||||||||||
7052 | SDValue Op = Node->getOperand(0); | ||||||||||
7053 | unsigned NumBitsPerElt = VT.getScalarSizeInBits(); | ||||||||||
7054 | |||||||||||
7055 | // If the non-ZERO_UNDEF version is supported we can use that instead. | ||||||||||
7056 | if (Node->getOpcode() == ISD::CTLZ_ZERO_UNDEF && | ||||||||||
7057 | isOperationLegalOrCustom(ISD::CTLZ, VT)) | ||||||||||
7058 | return DAG.getNode(ISD::CTLZ, dl, VT, Op); | ||||||||||
7059 | |||||||||||
7060 | // If the ZERO_UNDEF version is supported use that and handle the zero case. | ||||||||||
7061 | if (isOperationLegalOrCustom(ISD::CTLZ_ZERO_UNDEF, VT)) { | ||||||||||
7062 | EVT SetCCVT = | ||||||||||
7063 | getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT); | ||||||||||
7064 | SDValue CTLZ = DAG.getNode(ISD::CTLZ_ZERO_UNDEF, dl, VT, Op); | ||||||||||
7065 | SDValue Zero = DAG.getConstant(0, dl, VT); | ||||||||||
7066 | SDValue SrcIsZero = DAG.getSetCC(dl, SetCCVT, Op, Zero, ISD::SETEQ); | ||||||||||
7067 | return DAG.getNode(ISD::SELECT, dl, VT, SrcIsZero, | ||||||||||
7068 | DAG.getConstant(NumBitsPerElt, dl, VT), CTLZ); | ||||||||||
7069 | } | ||||||||||
7070 | |||||||||||
7071 | // Only expand vector types if we have the appropriate vector bit operations. | ||||||||||
7072 | // This includes the operations needed to expand CTPOP if it isn't supported. | ||||||||||
7073 | if (VT.isVector() && (!isPowerOf2_32(NumBitsPerElt) || | ||||||||||
7074 | (!isOperationLegalOrCustom(ISD::CTPOP, VT) && | ||||||||||
7075 | !canExpandVectorCTPOP(*this, VT)) || | ||||||||||
7076 | !isOperationLegalOrCustom(ISD::SRL, VT) || | ||||||||||
7077 | !isOperationLegalOrCustomOrPromote(ISD::OR, VT))) | ||||||||||
7078 | return SDValue(); | ||||||||||
7079 | |||||||||||
7080 | // for now, we do this: | ||||||||||
7081 | // x = x | (x >> 1); | ||||||||||
7082 | // x = x | (x >> 2); | ||||||||||
7083 | // ... | ||||||||||
7084 | // x = x | (x >>16); | ||||||||||
7085 | // x = x | (x >>32); // for 64-bit input | ||||||||||
7086 | // return popcount(~x); | ||||||||||
7087 | // | ||||||||||
7088 | // Ref: "Hacker's Delight" by Henry Warren | ||||||||||
7089 | for (unsigned i = 0; (1U << i) <= (NumBitsPerElt / 2); ++i) { | ||||||||||
7090 | SDValue Tmp = DAG.getConstant(1ULL << i, dl, ShVT); | ||||||||||
7091 | Op = DAG.getNode(ISD::OR, dl, VT, Op, | ||||||||||
7092 | DAG.getNode(ISD::SRL, dl, VT, Op, Tmp)); | ||||||||||
7093 | } | ||||||||||
7094 | Op = DAG.getNOT(dl, Op, VT); | ||||||||||
7095 | return DAG.getNode(ISD::CTPOP, dl, VT, Op); | ||||||||||
7096 | } | ||||||||||
7097 | |||||||||||
7098 | SDValue TargetLowering::expandCTTZ(SDNode *Node, SelectionDAG &DAG) const { | ||||||||||
7099 | SDLoc dl(Node); | ||||||||||
7100 | EVT VT = Node->getValueType(0); | ||||||||||
7101 | SDValue Op = Node->getOperand(0); | ||||||||||
7102 | unsigned NumBitsPerElt = VT.getScalarSizeInBits(); | ||||||||||
7103 | |||||||||||
7104 | // If the non-ZERO_UNDEF version is supported we can use that instead. | ||||||||||
7105 | if (Node->getOpcode() == ISD::CTTZ_ZERO_UNDEF && | ||||||||||
7106 | isOperationLegalOrCustom(ISD::CTTZ, VT)) | ||||||||||
7107 | return DAG.getNode(ISD::CTTZ, dl, VT, Op); | ||||||||||
7108 | |||||||||||
7109 | // If the ZERO_UNDEF version is supported use that and handle the zero case. | ||||||||||
7110 | if (isOperationLegalOrCustom(ISD::CTTZ_ZERO_UNDEF, VT)) { | ||||||||||
7111 | EVT SetCCVT = | ||||||||||
7112 | getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT); | ||||||||||
7113 | SDValue CTTZ = DAG.getNode(ISD::CTTZ_ZERO_UNDEF, dl, VT, Op); | ||||||||||
7114 | SDValue Zero = DAG.getConstant(0, dl, VT); | ||||||||||
7115 | SDValue SrcIsZero = DAG.getSetCC(dl, SetCCVT, Op, Zero, ISD::SETEQ); | ||||||||||
7116 | return DAG.getNode(ISD::SELECT, dl, VT, SrcIsZero, | ||||||||||
7117 | DAG.getConstant(NumBitsPerElt, dl, VT), CTTZ); | ||||||||||
7118 | } | ||||||||||
7119 | |||||||||||
7120 | // Only expand vector types if we have the appropriate vector bit operations. | ||||||||||
7121 | // This includes the operations needed to expand CTPOP if it isn't supported. | ||||||||||
7122 | if (VT.isVector() && (!isPowerOf2_32(NumBitsPerElt) || | ||||||||||
7123 | (!isOperationLegalOrCustom(ISD::CTPOP, VT) && | ||||||||||
7124 | !isOperationLegalOrCustom(ISD::CTLZ, VT) && | ||||||||||
7125 | !canExpandVectorCTPOP(*this, VT)) || | ||||||||||
7126 | !isOperationLegalOrCustom(ISD::SUB, VT) || | ||||||||||
7127 | !isOperationLegalOrCustomOrPromote(ISD::AND, VT) || | ||||||||||
7128 | !isOperationLegalOrCustomOrPromote(ISD::XOR, VT))) | ||||||||||
7129 | return SDValue(); | ||||||||||
7130 | |||||||||||
7131 | // for now, we use: { return popcount(~x & (x - 1)); } | ||||||||||
7132 | // unless the target has ctlz but not ctpop, in which case we use: | ||||||||||
7133 | // { return 32 - nlz(~x & (x-1)); } | ||||||||||
7134 | // Ref: "Hacker's Delight" by Henry Warren | ||||||||||
7135 | SDValue Tmp = DAG.getNode( | ||||||||||
7136 | ISD::AND, dl, VT, DAG.getNOT(dl, Op, VT), | ||||||||||
7137 | DAG.getNode(ISD::SUB, dl, VT, Op, DAG.getConstant(1, dl, VT))); | ||||||||||
7138 | |||||||||||
7139 | // If ISD::CTLZ is legal and CTPOP isn't, then do that instead. | ||||||||||
7140 | if (isOperationLegal(ISD::CTLZ, VT) && !isOperationLegal(ISD::CTPOP, VT)) { | ||||||||||
7141 | return DAG.getNode(ISD::SUB, dl, VT, DAG.getConstant(NumBitsPerElt, dl, VT), | ||||||||||
7142 | DAG.getNode(ISD::CTLZ, dl, VT, Tmp)); | ||||||||||
7143 | } | ||||||||||
7144 | |||||||||||
7145 | return DAG.getNode(ISD::CTPOP, dl, VT, Tmp); | ||||||||||
7146 | } | ||||||||||
7147 | |||||||||||
7148 | SDValue TargetLowering::expandABS(SDNode *N, SelectionDAG &DAG, | ||||||||||
7149 | bool IsNegative) const { | ||||||||||
7150 | SDLoc dl(N); | ||||||||||
7151 | EVT VT = N->getValueType(0); | ||||||||||
7152 | EVT ShVT = getShiftAmountTy(VT, DAG.getDataLayout()); | ||||||||||
7153 | SDValue Op = N->getOperand(0); | ||||||||||
7154 | |||||||||||
7155 | // abs(x) -> smax(x,sub(0,x)) | ||||||||||
7156 | if (!IsNegative && isOperationLegal(ISD::SUB, VT) && | ||||||||||
7157 | isOperationLegal(ISD::SMAX, VT)) { | ||||||||||
7158 | SDValue Zero = DAG.getConstant(0, dl, VT); | ||||||||||
7159 | return DAG.getNode(ISD::SMAX, dl, VT, Op, | ||||||||||
7160 | DAG.getNode(ISD::SUB, dl, VT, Zero, Op)); | ||||||||||
7161 | } | ||||||||||
7162 | |||||||||||
7163 | // abs(x) -> umin(x,sub(0,x)) | ||||||||||
7164 | if (!IsNegative && isOperationLegal(ISD::SUB, VT) && | ||||||||||
7165 | isOperationLegal(ISD::UMIN, VT)) { | ||||||||||
7166 | SDValue Zero = DAG.getConstant(0, dl, VT); | ||||||||||
7167 | return DAG.getNode(ISD::UMIN, dl, VT, Op, | ||||||||||
7168 | DAG.getNode(ISD::SUB, dl, VT, Zero, Op)); | ||||||||||
7169 | } | ||||||||||
7170 | |||||||||||
7171 | // 0 - abs(x) -> smin(x, sub(0,x)) | ||||||||||
7172 | if (IsNegative && isOperationLegal(ISD::SUB, VT) && | ||||||||||
7173 | isOperationLegal(ISD::SMIN, VT)) { | ||||||||||
7174 | SDValue Zero = DAG.getConstant(0, dl, VT); | ||||||||||
7175 | return DAG.getNode(ISD::SMIN, dl, VT, Op, | ||||||||||
7176 | DAG.getNode(ISD::SUB, dl, VT, Zero, Op)); | ||||||||||
7177 | } | ||||||||||
7178 | |||||||||||
7179 | // Only expand vector types if we have the appropriate vector operations. | ||||||||||
7180 | if (VT.isVector() && | ||||||||||
7181 | (!isOperationLegalOrCustom(ISD::SRA, VT) || | ||||||||||
7182 | (!IsNegative && !isOperationLegalOrCustom(ISD::ADD, VT)) || | ||||||||||
7183 | (IsNegative && !isOperationLegalOrCustom(ISD::SUB, VT)) || | ||||||||||
7184 | !isOperationLegalOrCustomOrPromote(ISD::XOR, VT))) | ||||||||||
7185 | return SDValue(); | ||||||||||
7186 | |||||||||||
7187 | SDValue Shift = | ||||||||||
7188 | DAG.getNode(ISD::SRA, dl, VT, Op, | ||||||||||
7189 | DAG.getConstant(VT.getScalarSizeInBits() - 1, dl, ShVT)); | ||||||||||
7190 | if (!IsNegative) { | ||||||||||
7191 | SDValue Add = DAG.getNode(ISD::ADD, dl, VT, Op, Shift); | ||||||||||
7192 | return DAG.getNode(ISD::XOR, dl, VT, Add, Shift); | ||||||||||
7193 | } | ||||||||||
7194 | |||||||||||
7195 | // 0 - abs(x) -> Y = sra (X, size(X)-1); sub (Y, xor (X, Y)) | ||||||||||
7196 | SDValue Xor = DAG.getNode(ISD::XOR, dl, VT, Op, Shift); | ||||||||||
7197 | return DAG.getNode(ISD::SUB, dl, VT, Shift, Xor); | ||||||||||
7198 | } | ||||||||||
7199 | |||||||||||
7200 | SDValue TargetLowering::expandBSWAP(SDNode *N, SelectionDAG &DAG) const { | ||||||||||
7201 | SDLoc dl(N); | ||||||||||
7202 | EVT VT = N->getValueType(0); | ||||||||||
7203 | SDValue Op = N->getOperand(0); | ||||||||||
7204 | |||||||||||
7205 | if (!VT.isSimple()) | ||||||||||
7206 | return SDValue(); | ||||||||||
7207 | |||||||||||
7208 | EVT SHVT = getShiftAmountTy(VT, DAG.getDataLayout()); | ||||||||||
7209 | SDValue Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8; | ||||||||||
7210 | switch (VT.getSimpleVT().getScalarType().SimpleTy) { | ||||||||||
7211 | default: | ||||||||||
7212 | return SDValue(); | ||||||||||
7213 | case MVT::i16: | ||||||||||
7214 | // Use a rotate by 8. This can be further expanded if necessary. | ||||||||||
7215 | return DAG.getNode(ISD::ROTL, dl, VT, Op, DAG.getConstant(8, dl, SHVT)); | ||||||||||
7216 | case MVT::i32: | ||||||||||
7217 | Tmp4 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, dl, SHVT)); | ||||||||||
7218 | Tmp3 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, dl, SHVT)); | ||||||||||
7219 | Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, dl, SHVT)); | ||||||||||
7220 | Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, dl, SHVT)); | ||||||||||
7221 | Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3, | ||||||||||
7222 | DAG.getConstant(0xFF0000, dl, VT)); | ||||||||||
7223 | Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(0xFF00, dl, VT)); | ||||||||||
7224 | Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3); | ||||||||||
7225 | Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1); | ||||||||||
7226 | return DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2); | ||||||||||
7227 | case MVT::i64: | ||||||||||
7228 | Tmp8 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(56, dl, SHVT)); | ||||||||||
7229 | Tmp7 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(40, dl, SHVT)); | ||||||||||
7230 | Tmp6 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, dl, SHVT)); | ||||||||||
7231 | Tmp5 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, dl, SHVT)); | ||||||||||
7232 | Tmp4 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, dl, SHVT)); | ||||||||||
7233 | Tmp3 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, dl, SHVT)); | ||||||||||
7234 | Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(40, dl, SHVT)); | ||||||||||
7235 | Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(56, dl, SHVT)); | ||||||||||
7236 | Tmp7 = DAG.getNode(ISD::AND, dl, VT, Tmp7, | ||||||||||
7237 | DAG.getConstant(255ULL<<48, dl, VT)); | ||||||||||
7238 | Tmp6 = DAG.getNode(ISD::AND, dl, VT, Tmp6, | ||||||||||
7239 | DAG.getConstant(255ULL<<40, dl, VT)); | ||||||||||
7240 | Tmp5 = DAG.getNode(ISD::AND, dl, VT, Tmp5, | ||||||||||
7241 | DAG.getConstant(255ULL<<32, dl, VT)); | ||||||||||
7242 | Tmp4 = DAG.getNode(ISD::AND, dl, VT, Tmp4, | ||||||||||
7243 | DAG.getConstant(255ULL<<24, dl, VT)); | ||||||||||
7244 | Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3, | ||||||||||
7245 | DAG.getConstant(255ULL<<16, dl, VT)); | ||||||||||
7246 | Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, | ||||||||||
7247 | DAG.getConstant(255ULL<<8 , dl, VT)); | ||||||||||
7248 | Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp7); | ||||||||||
7249 | Tmp6 = DAG.getNode(ISD::OR, dl, VT, Tmp6, Tmp5); | ||||||||||
7250 | Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3); | ||||||||||
7251 | Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1); | ||||||||||
7252 | Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp6); | ||||||||||
7253 | Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2); | ||||||||||
7254 | return DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp4); | ||||||||||
7255 | } | ||||||||||
7256 | } | ||||||||||
7257 | |||||||||||
7258 | SDValue TargetLowering::expandBITREVERSE(SDNode *N, SelectionDAG &DAG) const { | ||||||||||
7259 | SDLoc dl(N); | ||||||||||
7260 | EVT VT = N->getValueType(0); | ||||||||||
7261 | SDValue Op = N->getOperand(0); | ||||||||||
7262 | EVT SHVT = getShiftAmountTy(VT, DAG.getDataLayout()); | ||||||||||
7263 | unsigned Sz = VT.getScalarSizeInBits(); | ||||||||||
7264 | |||||||||||
7265 | SDValue Tmp, Tmp2, Tmp3; | ||||||||||
7266 | |||||||||||
7267 | // If we can, perform BSWAP first and then the mask+swap the i4, then i2 | ||||||||||
7268 | // and finally the i1 pairs. | ||||||||||
7269 | // TODO: We can easily support i4/i2 legal types if any target ever does. | ||||||||||
7270 | if (Sz >= 8 && isPowerOf2_32(Sz)) { | ||||||||||
7271 | // Create the masks - repeating the pattern every byte. | ||||||||||
7272 | APInt Mask4 = APInt::getSplat(Sz, APInt(8, 0x0F)); | ||||||||||
7273 | APInt Mask2 = APInt::getSplat(Sz, APInt(8, 0x33)); | ||||||||||
7274 | APInt Mask1 = APInt::getSplat(Sz, APInt(8, 0x55)); | ||||||||||
7275 | |||||||||||
7276 | // BSWAP if the type is wider than a single byte. | ||||||||||
7277 | Tmp = (Sz > 8 ? DAG.getNode(ISD::BSWAP, dl, VT, Op) : Op); | ||||||||||
7278 | |||||||||||
7279 | // swap i4: ((V >> 4) & 0x0F) | ((V & 0x0F) << 4) | ||||||||||
7280 | Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Tmp, DAG.getConstant(4, dl, SHVT)); | ||||||||||
7281 | Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(Mask4, dl, VT)); | ||||||||||
7282 | Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp, DAG.getConstant(Mask4, dl, VT)); | ||||||||||
7283 | Tmp3 = DAG.getNode(ISD::SHL, dl, VT, Tmp3, DAG.getConstant(4, dl, SHVT)); | ||||||||||
7284 | Tmp = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3); | ||||||||||
7285 | |||||||||||
7286 | // swap i2: ((V >> 2) & 0x33) | ((V & 0x33) << 2) | ||||||||||
7287 | Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Tmp, DAG.getConstant(2, dl, SHVT)); | ||||||||||
7288 | Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(Mask2, dl, VT)); | ||||||||||
7289 | Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp, DAG.getConstant(Mask2, dl, VT)); | ||||||||||
7290 | Tmp3 = DAG.getNode(ISD::SHL, dl, VT, Tmp3, DAG.getConstant(2, dl, SHVT)); | ||||||||||
7291 | Tmp = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3); | ||||||||||
7292 | |||||||||||
7293 | // swap i1: ((V >> 1) & 0x55) | ((V & 0x55) << 1) | ||||||||||
7294 | Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Tmp, DAG.getConstant(1, dl, SHVT)); | ||||||||||
7295 | Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(Mask1, dl, VT)); | ||||||||||
7296 | Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp, DAG.getConstant(Mask1, dl, VT)); | ||||||||||
7297 | Tmp3 = DAG.getNode(ISD::SHL, dl, VT, Tmp3, DAG.getConstant(1, dl, SHVT)); | ||||||||||
7298 | Tmp = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3); | ||||||||||
7299 | return Tmp; | ||||||||||
7300 | } | ||||||||||
7301 | |||||||||||
7302 | Tmp = DAG.getConstant(0, dl, VT); | ||||||||||
7303 | for (unsigned I = 0, J = Sz-1; I < Sz; ++I, --J) { | ||||||||||
7304 | if (I < J) | ||||||||||
7305 | Tmp2 = | ||||||||||
7306 | DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(J - I, dl, SHVT)); | ||||||||||
7307 | else | ||||||||||
7308 | Tmp2 = | ||||||||||
7309 | DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(I - J, dl, SHVT)); | ||||||||||
7310 | |||||||||||
7311 | APInt Shift(Sz, 1); | ||||||||||
7312 | Shift <<= J; | ||||||||||
7313 | Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(Shift, dl, VT)); | ||||||||||
7314 | Tmp = DAG.getNode(ISD::OR, dl, VT, Tmp, Tmp2); | ||||||||||
7315 | } | ||||||||||
7316 | |||||||||||
7317 | return Tmp; | ||||||||||
7318 | } | ||||||||||
7319 | |||||||||||
7320 | std::pair<SDValue, SDValue> | ||||||||||
7321 | TargetLowering::scalarizeVectorLoad(LoadSDNode *LD, | ||||||||||
7322 | SelectionDAG &DAG) const { | ||||||||||
7323 | SDLoc SL(LD); | ||||||||||
7324 | SDValue Chain = LD->getChain(); | ||||||||||
7325 | SDValue BasePTR = LD->getBasePtr(); | ||||||||||
7326 | EVT SrcVT = LD->getMemoryVT(); | ||||||||||
7327 | EVT DstVT = LD->getValueType(0); | ||||||||||
7328 | ISD::LoadExtType ExtType = LD->getExtensionType(); | ||||||||||
7329 | |||||||||||
7330 | if (SrcVT.isScalableVector()) | ||||||||||
7331 | report_fatal_error("Cannot scalarize scalable vector loads"); | ||||||||||
7332 | |||||||||||
7333 | unsigned NumElem = SrcVT.getVectorNumElements(); | ||||||||||
7334 | |||||||||||
7335 | EVT SrcEltVT = SrcVT.getScalarType(); | ||||||||||
7336 | EVT DstEltVT = DstVT.getScalarType(); | ||||||||||
7337 | |||||||||||
7338 | // A vector must always be stored in memory as-is, i.e. without any padding | ||||||||||
7339 | // between the elements, since various code depend on it, e.g. in the | ||||||||||
7340 | // handling of a bitcast of a vector type to int, which may be done with a | ||||||||||
7341 | // vector store followed by an integer load. A vector that does not have | ||||||||||
7342 | // elements that are byte-sized must therefore be stored as an integer | ||||||||||
7343 | // built out of the extracted vector elements. | ||||||||||
7344 | if (!SrcEltVT.isByteSized()) { | ||||||||||
7345 | unsigned NumLoadBits = SrcVT.getStoreSizeInBits(); | ||||||||||
7346 | EVT LoadVT = EVT::getIntegerVT(*DAG.getContext(), NumLoadBits); | ||||||||||
7347 | |||||||||||
7348 | unsigned NumSrcBits = SrcVT.getSizeInBits(); | ||||||||||
7349 | EVT SrcIntVT = EVT::getIntegerVT(*DAG.getContext(), NumSrcBits); | ||||||||||
7350 | |||||||||||
7351 | unsigned SrcEltBits = SrcEltVT.getSizeInBits(); | ||||||||||
7352 | SDValue SrcEltBitMask = DAG.getConstant( | ||||||||||
7353 | APInt::getLowBitsSet(NumLoadBits, SrcEltBits), SL, LoadVT); | ||||||||||
7354 | |||||||||||
7355 | // Load the whole vector and avoid masking off the top bits as it makes | ||||||||||
7356 | // the codegen worse. | ||||||||||
7357 | SDValue Load = | ||||||||||
7358 | DAG.getExtLoad(ISD::EXTLOAD, SL, LoadVT, Chain, BasePTR, | ||||||||||
7359 | LD->getPointerInfo(), SrcIntVT, LD->getOriginalAlign(), | ||||||||||
7360 | LD->getMemOperand()->getFlags(), LD->getAAInfo()); | ||||||||||
7361 | |||||||||||
7362 | SmallVector<SDValue, 8> Vals; | ||||||||||
7363 | for (unsigned Idx = 0; Idx < NumElem; ++Idx) { | ||||||||||
7364 | unsigned ShiftIntoIdx = | ||||||||||
7365 | (DAG.getDataLayout().isBigEndian() ? (NumElem - 1) - Idx : Idx); | ||||||||||
7366 | SDValue ShiftAmount = | ||||||||||
7367 | DAG.getShiftAmountConstant(ShiftIntoIdx * SrcEltVT.getSizeInBits(), | ||||||||||
7368 | LoadVT, SL, /*LegalTypes=*/false); | ||||||||||
7369 | SDValue ShiftedElt = DAG.getNode(ISD::SRL, SL, LoadVT, Load, ShiftAmount); | ||||||||||
7370 | SDValue Elt = | ||||||||||
7371 | DAG.getNode(ISD::AND, SL, LoadVT, ShiftedElt, SrcEltBitMask); | ||||||||||
7372 | SDValue Scalar = DAG.getNode(ISD::TRUNCATE, SL, SrcEltVT, Elt); | ||||||||||
7373 | |||||||||||
7374 | if (ExtType != ISD::NON_EXTLOAD) { | ||||||||||
7375 | unsigned ExtendOp = ISD::getExtForLoadExtType(false, ExtType); | ||||||||||
7376 | Scalar = DAG.getNode(ExtendOp, SL, DstEltVT, Scalar); | ||||||||||
7377 | } | ||||||||||
7378 | |||||||||||
7379 | Vals.push_back(Scalar); | ||||||||||
7380 | } | ||||||||||
7381 | |||||||||||
7382 | SDValue Value = DAG.getBuildVector(DstVT, SL, Vals); | ||||||||||
7383 | return std::make_pair(Value, Load.getValue(1)); | ||||||||||
7384 | } | ||||||||||
7385 | |||||||||||
7386 | unsigned Stride = SrcEltVT.getSizeInBits() / 8; | ||||||||||
7387 | assert(SrcEltVT.isByteSized())(static_cast <bool> (SrcEltVT.isByteSized()) ? void (0) : __assert_fail ("SrcEltVT.isByteSized()", "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 7387, __extension__ __PRETTY_FUNCTION__)); | ||||||||||
7388 | |||||||||||
7389 | SmallVector<SDValue, 8> Vals; | ||||||||||
7390 | SmallVector<SDValue, 8> LoadChains; | ||||||||||
7391 | |||||||||||
7392 | for (unsigned Idx = 0; Idx < NumElem; ++Idx) { | ||||||||||
7393 | SDValue ScalarLoad = | ||||||||||
7394 | DAG.getExtLoad(ExtType, SL, DstEltVT, Chain, BasePTR, | ||||||||||
7395 | LD->getPointerInfo().getWithOffset(Idx * Stride), | ||||||||||
7396 | SrcEltVT, LD->getOriginalAlign(), | ||||||||||
7397 | LD->getMemOperand()->getFlags(), LD->getAAInfo()); | ||||||||||
7398 | |||||||||||
7399 | BasePTR = DAG.getObjectPtrOffset(SL, BasePTR, TypeSize::Fixed(Stride)); | ||||||||||
7400 | |||||||||||
7401 | Vals.push_back(ScalarLoad.getValue(0)); | ||||||||||
7402 | LoadChains.push_back(ScalarLoad.getValue(1)); | ||||||||||
7403 | } | ||||||||||
7404 | |||||||||||
7405 | SDValue NewChain = DAG.getNode(ISD::TokenFactor, SL, MVT::Other, LoadChains); | ||||||||||
7406 | SDValue Value = DAG.getBuildVector(DstVT, SL, Vals); | ||||||||||
7407 | |||||||||||
7408 | return std::make_pair(Value, NewChain); | ||||||||||
7409 | } | ||||||||||
7410 | |||||||||||
7411 | SDValue TargetLowering::scalarizeVectorStore(StoreSDNode *ST, | ||||||||||
7412 | SelectionDAG &DAG) const { | ||||||||||
7413 | SDLoc SL(ST); | ||||||||||
7414 | |||||||||||
7415 | SDValue Chain = ST->getChain(); | ||||||||||
7416 | SDValue BasePtr = ST->getBasePtr(); | ||||||||||
7417 | SDValue Value = ST->getValue(); | ||||||||||
7418 | EVT StVT = ST->getMemoryVT(); | ||||||||||
7419 | |||||||||||
7420 | if (StVT.isScalableVector()) | ||||||||||
7421 | report_fatal_error("Cannot scalarize scalable vector stores"); | ||||||||||
7422 | |||||||||||
7423 | // The type of the data we want to save | ||||||||||
7424 | EVT RegVT = Value.getValueType(); | ||||||||||
7425 | EVT RegSclVT = RegVT.getScalarType(); | ||||||||||
7426 | |||||||||||
7427 | // The type of data as saved in memory. | ||||||||||
7428 | EVT MemSclVT = StVT.getScalarType(); | ||||||||||
7429 | |||||||||||
7430 | unsigned NumElem = StVT.getVectorNumElements(); | ||||||||||
7431 | |||||||||||
7432 | // A vector must always be stored in memory as-is, i.e. without any padding | ||||||||||
7433 | // between the elements, since various code depend on it, e.g. in the | ||||||||||
7434 | // handling of a bitcast of a vector type to int, which may be done with a | ||||||||||
7435 | // vector store followed by an integer load. A vector that does not have | ||||||||||
7436 | // elements that are byte-sized must therefore be stored as an integer | ||||||||||
7437 | // built out of the extracted vector elements. | ||||||||||
7438 | if (!MemSclVT.isByteSized()) { | ||||||||||
7439 | unsigned NumBits = StVT.getSizeInBits(); | ||||||||||
7440 | EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), NumBits); | ||||||||||
7441 | |||||||||||
7442 | SDValue CurrVal = DAG.getConstant(0, SL, IntVT); | ||||||||||
7443 | |||||||||||
7444 | for (unsigned Idx = 0; Idx < NumElem; ++Idx) { | ||||||||||
7445 | SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, RegSclVT, Value, | ||||||||||
7446 | DAG.getVectorIdxConstant(Idx, SL)); | ||||||||||
7447 | SDValue Trunc = DAG.getNode(ISD::TRUNCATE, SL, MemSclVT, Elt); | ||||||||||
7448 | SDValue ExtElt = DAG.getNode(ISD::ZERO_EXTEND, SL, IntVT, Trunc); | ||||||||||
7449 | unsigned ShiftIntoIdx = | ||||||||||
7450 | (DAG.getDataLayout().isBigEndian() ? (NumElem - 1) - Idx : Idx); | ||||||||||
7451 | SDValue ShiftAmount = | ||||||||||
7452 | DAG.getConstant(ShiftIntoIdx * MemSclVT.getSizeInBits(), SL, IntVT); | ||||||||||
7453 | SDValue ShiftedElt = | ||||||||||
7454 | DAG.getNode(ISD::SHL, SL, IntVT, ExtElt, ShiftAmount); | ||||||||||
7455 | CurrVal = DAG.getNode(ISD::OR, SL, IntVT, CurrVal, ShiftedElt); | ||||||||||
7456 | } | ||||||||||
7457 | |||||||||||
7458 | return DAG.getStore(Chain, SL, CurrVal, BasePtr, ST->getPointerInfo(), | ||||||||||
7459 | ST->getOriginalAlign(), ST->getMemOperand()->getFlags(), | ||||||||||
7460 | ST->getAAInfo()); | ||||||||||
7461 | } | ||||||||||
7462 | |||||||||||
7463 | // Store Stride in bytes | ||||||||||
7464 | unsigned Stride = MemSclVT.getSizeInBits() / 8; | ||||||||||
7465 | assert(Stride && "Zero stride!")(static_cast <bool> (Stride && "Zero stride!") ? void (0) : __assert_fail ("Stride && \"Zero stride!\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 7465, __extension__ __PRETTY_FUNCTION__)); | ||||||||||
7466 | // Extract each of the elements from the original vector and save them into | ||||||||||
7467 | // memory individually. | ||||||||||
7468 | SmallVector<SDValue, 8> Stores; | ||||||||||
7469 | for (unsigned Idx = 0; Idx < NumElem; ++Idx) { | ||||||||||
7470 | SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, RegSclVT, Value, | ||||||||||
7471 | DAG.getVectorIdxConstant(Idx, SL)); | ||||||||||
7472 | |||||||||||
7473 | SDValue Ptr = | ||||||||||
7474 | DAG.getObjectPtrOffset(SL, BasePtr, TypeSize::Fixed(Idx * Stride)); | ||||||||||
7475 | |||||||||||
7476 | // This scalar TruncStore may be illegal, but we legalize it later. | ||||||||||
7477 | SDValue Store = DAG.getTruncStore( | ||||||||||
7478 | Chain, SL, Elt, Ptr, ST->getPointerInfo().getWithOffset(Idx * Stride), | ||||||||||
7479 | MemSclVT, ST->getOriginalAlign(), ST->getMemOperand()->getFlags(), | ||||||||||
7480 | ST->getAAInfo()); | ||||||||||
7481 | |||||||||||
7482 | Stores.push_back(Store); | ||||||||||
7483 | } | ||||||||||
7484 | |||||||||||
7485 | return DAG.getNode(ISD::TokenFactor, SL, MVT::Other, Stores); | ||||||||||
7486 | } | ||||||||||
7487 | |||||||||||
7488 | std::pair<SDValue, SDValue> | ||||||||||
7489 | TargetLowering::expandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG) const { | ||||||||||
7490 | assert(LD->getAddressingMode() == ISD::UNINDEXED &&(static_cast <bool> (LD->getAddressingMode() == ISD:: UNINDEXED && "unaligned indexed loads not implemented!" ) ? void (0) : __assert_fail ("LD->getAddressingMode() == ISD::UNINDEXED && \"unaligned indexed loads not implemented!\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 7491, __extension__ __PRETTY_FUNCTION__)) | ||||||||||
7491 | "unaligned indexed loads not implemented!")(static_cast <bool> (LD->getAddressingMode() == ISD:: UNINDEXED && "unaligned indexed loads not implemented!" ) ? void (0) : __assert_fail ("LD->getAddressingMode() == ISD::UNINDEXED && \"unaligned indexed loads not implemented!\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 7491, __extension__ __PRETTY_FUNCTION__)); | ||||||||||
7492 | SDValue Chain = LD->getChain(); | ||||||||||
7493 | SDValue Ptr = LD->getBasePtr(); | ||||||||||
7494 | EVT VT = LD->getValueType(0); | ||||||||||
7495 | EVT LoadedVT = LD->getMemoryVT(); | ||||||||||
7496 | SDLoc dl(LD); | ||||||||||
7497 | auto &MF = DAG.getMachineFunction(); | ||||||||||
7498 | |||||||||||
7499 | if (VT.isFloatingPoint() || VT.isVector()) { | ||||||||||
7500 | EVT intVT = EVT::getIntegerVT(*DAG.getContext(), LoadedVT.getSizeInBits()); | ||||||||||
7501 | if (isTypeLegal(intVT) && isTypeLegal(LoadedVT)) { | ||||||||||
7502 | if (!isOperationLegalOrCustom(ISD::LOAD, intVT) && | ||||||||||
7503 | LoadedVT.isVector()) { | ||||||||||
7504 | // Scalarize the load and let the individual components be handled. | ||||||||||
7505 | return scalarizeVectorLoad(LD, DAG); | ||||||||||
7506 | } | ||||||||||
7507 | |||||||||||
7508 | // Expand to a (misaligned) integer load of the same size, | ||||||||||
7509 | // then bitconvert to floating point or vector. | ||||||||||
7510 | SDValue newLoad = DAG.getLoad(intVT, dl, Chain, Ptr, | ||||||||||
7511 | LD->getMemOperand()); | ||||||||||
7512 | SDValue Result = DAG.getNode(ISD::BITCAST, dl, LoadedVT, newLoad); | ||||||||||
7513 | if (LoadedVT != VT) | ||||||||||
7514 | Result = DAG.getNode(VT.isFloatingPoint() ? ISD::FP_EXTEND : | ||||||||||
7515 | ISD::ANY_EXTEND, dl, VT, Result); | ||||||||||
7516 | |||||||||||
7517 | return std::make_pair(Result, newLoad.getValue(1)); | ||||||||||
7518 | } | ||||||||||
7519 | |||||||||||
7520 | // Copy the value to a (aligned) stack slot using (unaligned) integer | ||||||||||
7521 | // loads and stores, then do a (aligned) load from the stack slot. | ||||||||||
7522 | MVT RegVT = getRegisterType(*DAG.getContext(), intVT); | ||||||||||
7523 | unsigned LoadedBytes = LoadedVT.getStoreSize(); | ||||||||||
7524 | unsigned RegBytes = RegVT.getSizeInBits() / 8; | ||||||||||
7525 | unsigned NumRegs = (LoadedBytes + RegBytes - 1) / RegBytes; | ||||||||||
7526 | |||||||||||
7527 | // Make sure the stack slot is also aligned for the register type. | ||||||||||
7528 | SDValue StackBase = DAG.CreateStackTemporary(LoadedVT, RegVT); | ||||||||||
7529 | auto FrameIndex = cast<FrameIndexSDNode>(StackBase.getNode())->getIndex(); | ||||||||||
7530 | SmallVector<SDValue, 8> Stores; | ||||||||||
7531 | SDValue StackPtr = StackBase; | ||||||||||
7532 | unsigned Offset = 0; | ||||||||||
7533 | |||||||||||
7534 | EVT PtrVT = Ptr.getValueType(); | ||||||||||
7535 | EVT StackPtrVT = StackPtr.getValueType(); | ||||||||||
7536 | |||||||||||
7537 | SDValue PtrIncrement = DAG.getConstant(RegBytes, dl, PtrVT); | ||||||||||
7538 | SDValue StackPtrIncrement = DAG.getConstant(RegBytes, dl, StackPtrVT); | ||||||||||
7539 | |||||||||||
7540 | // Do all but one copies using the full register width. | ||||||||||
7541 | for (unsigned i = 1; i < NumRegs; i++) { | ||||||||||
7542 | // Load one integer register's worth from the original location. | ||||||||||
7543 | SDValue Load = DAG.getLoad( | ||||||||||
7544 | RegVT, dl, Chain, Ptr, LD->getPointerInfo().getWithOffset(Offset), | ||||||||||
7545 | LD->getOriginalAlign(), LD->getMemOperand()->getFlags(), | ||||||||||
7546 | LD->getAAInfo()); | ||||||||||
7547 | // Follow the load with a store to the stack slot. Remember the store. | ||||||||||
7548 | Stores.push_back(DAG.getStore( | ||||||||||
7549 | Load.getValue(1), dl, Load, StackPtr, | ||||||||||
7550 | MachinePointerInfo::getFixedStack(MF, FrameIndex, Offset))); | ||||||||||
7551 | // Increment the pointers. | ||||||||||
7552 | Offset += RegBytes; | ||||||||||
7553 | |||||||||||
7554 | Ptr = DAG.getObjectPtrOffset(dl, Ptr, PtrIncrement); | ||||||||||
7555 | StackPtr = DAG.getObjectPtrOffset(dl, StackPtr, StackPtrIncrement); | ||||||||||
7556 | } | ||||||||||
7557 | |||||||||||
7558 | // The last copy may be partial. Do an extending load. | ||||||||||
7559 | EVT MemVT = EVT::getIntegerVT(*DAG.getContext(), | ||||||||||
7560 | 8 * (LoadedBytes - Offset)); | ||||||||||
7561 | SDValue Load = | ||||||||||
7562 | DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Chain, Ptr, | ||||||||||
7563 | LD->getPointerInfo().getWithOffset(Offset), MemVT, | ||||||||||
7564 | LD->getOriginalAlign(), LD->getMemOperand()->getFlags(), | ||||||||||
7565 | LD->getAAInfo()); | ||||||||||
7566 | // Follow the load with a store to the stack slot. Remember the store. | ||||||||||
7567 | // On big-endian machines this requires a truncating store to ensure | ||||||||||
7568 | // that the bits end up in the right place. | ||||||||||
7569 | Stores.push_back(DAG.getTruncStore( | ||||||||||
7570 | Load.getValue(1), dl, Load, StackPtr, | ||||||||||
7571 | MachinePointerInfo::getFixedStack(MF, FrameIndex, Offset), MemVT)); | ||||||||||
7572 | |||||||||||
7573 | // The order of the stores doesn't matter - say it with a TokenFactor. | ||||||||||
7574 | SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Stores); | ||||||||||
7575 | |||||||||||
7576 | // Finally, perform the original load only redirected to the stack slot. | ||||||||||
7577 | Load = DAG.getExtLoad(LD->getExtensionType(), dl, VT, TF, StackBase, | ||||||||||
7578 | MachinePointerInfo::getFixedStack(MF, FrameIndex, 0), | ||||||||||
7579 | LoadedVT); | ||||||||||
7580 | |||||||||||
7581 | // Callers expect a MERGE_VALUES node. | ||||||||||
7582 | return std::make_pair(Load, TF); | ||||||||||
7583 | } | ||||||||||
7584 | |||||||||||
7585 | assert(LoadedVT.isInteger() && !LoadedVT.isVector() &&(static_cast <bool> (LoadedVT.isInteger() && !LoadedVT .isVector() && "Unaligned load of unsupported type.") ? void (0) : __assert_fail ("LoadedVT.isInteger() && !LoadedVT.isVector() && \"Unaligned load of unsupported type.\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 7586, __extension__ __PRETTY_FUNCTION__)) | ||||||||||
7586 | "Unaligned load of unsupported type.")(static_cast <bool> (LoadedVT.isInteger() && !LoadedVT .isVector() && "Unaligned load of unsupported type.") ? void (0) : __assert_fail ("LoadedVT.isInteger() && !LoadedVT.isVector() && \"Unaligned load of unsupported type.\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 7586, __extension__ __PRETTY_FUNCTION__)); | ||||||||||
7587 | |||||||||||
7588 | // Compute the new VT that is half the size of the old one. This is an | ||||||||||
7589 | // integer MVT. | ||||||||||
7590 | unsigned NumBits = LoadedVT.getSizeInBits(); | ||||||||||
7591 | EVT NewLoadedVT; | ||||||||||
7592 | NewLoadedVT = EVT::getIntegerVT(*DAG.getContext(), NumBits/2); | ||||||||||
7593 | NumBits >>= 1; | ||||||||||
7594 | |||||||||||
7595 | Align Alignment = LD->getOriginalAlign(); | ||||||||||
7596 | unsigned IncrementSize = NumBits / 8; | ||||||||||
7597 | ISD::LoadExtType HiExtType = LD->getExtensionType(); | ||||||||||
7598 | |||||||||||
7599 | // If the original load is NON_EXTLOAD, the hi part load must be ZEXTLOAD. | ||||||||||
7600 | if (HiExtType == ISD::NON_EXTLOAD) | ||||||||||
7601 | HiExtType = ISD::ZEXTLOAD; | ||||||||||
7602 | |||||||||||
7603 | // Load the value in two parts | ||||||||||
7604 | SDValue Lo, Hi; | ||||||||||
7605 | if (DAG.getDataLayout().isLittleEndian()) { | ||||||||||
7606 | Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr, LD->getPointerInfo(), | ||||||||||
7607 | NewLoadedVT, Alignment, LD->getMemOperand()->getFlags(), | ||||||||||
7608 | LD->getAAInfo()); | ||||||||||
7609 | |||||||||||
7610 | Ptr = DAG.getObjectPtrOffset(dl, Ptr, TypeSize::Fixed(IncrementSize)); | ||||||||||
7611 | Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr, | ||||||||||
7612 | LD->getPointerInfo().getWithOffset(IncrementSize), | ||||||||||
7613 | NewLoadedVT, Alignment, LD->getMemOperand()->getFlags(), | ||||||||||
7614 | LD->getAAInfo()); | ||||||||||
7615 | } else { | ||||||||||
7616 | Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr, LD->getPointerInfo(), | ||||||||||
7617 | NewLoadedVT, Alignment, LD->getMemOperand()->getFlags(), | ||||||||||
7618 | LD->getAAInfo()); | ||||||||||
7619 | |||||||||||
7620 | Ptr = DAG.getObjectPtrOffset(dl, Ptr, TypeSize::Fixed(IncrementSize)); | ||||||||||
7621 | Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr, | ||||||||||
7622 | LD->getPointerInfo().getWithOffset(IncrementSize), | ||||||||||
7623 | NewLoadedVT, Alignment, LD->getMemOperand()->getFlags(), | ||||||||||
7624 | LD->getAAInfo()); | ||||||||||
7625 | } | ||||||||||
7626 | |||||||||||
7627 | // aggregate the two parts | ||||||||||
7628 | SDValue ShiftAmount = | ||||||||||
7629 | DAG.getConstant(NumBits, dl, getShiftAmountTy(Hi.getValueType(), | ||||||||||
7630 | DAG.getDataLayout())); | ||||||||||
7631 | SDValue Result = DAG.getNode(ISD::SHL, dl, VT, Hi, ShiftAmount); | ||||||||||
7632 | Result = DAG.getNode(ISD::OR, dl, VT, Result, Lo); | ||||||||||
7633 | |||||||||||
7634 | SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1), | ||||||||||
7635 | Hi.getValue(1)); | ||||||||||
7636 | |||||||||||
7637 | return std::make_pair(Result, TF); | ||||||||||
7638 | } | ||||||||||
7639 | |||||||||||
7640 | SDValue TargetLowering::expandUnalignedStore(StoreSDNode *ST, | ||||||||||
7641 | SelectionDAG &DAG) const { | ||||||||||
7642 | assert(ST->getAddressingMode() == ISD::UNINDEXED &&(static_cast <bool> (ST->getAddressingMode() == ISD:: UNINDEXED && "unaligned indexed stores not implemented!" ) ? void (0) : __assert_fail ("ST->getAddressingMode() == ISD::UNINDEXED && \"unaligned indexed stores not implemented!\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 7643, __extension__ __PRETTY_FUNCTION__)) | ||||||||||
7643 | "unaligned indexed stores not implemented!")(static_cast <bool> (ST->getAddressingMode() == ISD:: UNINDEXED && "unaligned indexed stores not implemented!" ) ? void (0) : __assert_fail ("ST->getAddressingMode() == ISD::UNINDEXED && \"unaligned indexed stores not implemented!\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 7643, __extension__ __PRETTY_FUNCTION__)); | ||||||||||
7644 | SDValue Chain = ST->getChain(); | ||||||||||
7645 | SDValue Ptr = ST->getBasePtr(); | ||||||||||
7646 | SDValue Val = ST->getValue(); | ||||||||||
7647 | EVT VT = Val.getValueType(); | ||||||||||
7648 | Align Alignment = ST->getOriginalAlign(); | ||||||||||
7649 | auto &MF = DAG.getMachineFunction(); | ||||||||||
7650 | EVT StoreMemVT = ST->getMemoryVT(); | ||||||||||
7651 | |||||||||||
7652 | SDLoc dl(ST); | ||||||||||
7653 | if (StoreMemVT.isFloatingPoint() || StoreMemVT.isVector()) { | ||||||||||
7654 | EVT intVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits()); | ||||||||||
7655 | if (isTypeLegal(intVT)) { | ||||||||||
7656 | if (!isOperationLegalOrCustom(ISD::STORE, intVT) && | ||||||||||
7657 | StoreMemVT.isVector()) { | ||||||||||
7658 | // Scalarize the store and let the individual components be handled. | ||||||||||
7659 | SDValue Result = scalarizeVectorStore(ST, DAG); | ||||||||||
7660 | return Result; | ||||||||||
7661 | } | ||||||||||
7662 | // Expand to a bitconvert of the value to the integer type of the | ||||||||||
7663 | // same size, then a (misaligned) int store. | ||||||||||
7664 | // FIXME: Does not handle truncating floating point stores! | ||||||||||
7665 | SDValue Result = DAG.getNode(ISD::BITCAST, dl, intVT, Val); | ||||||||||
7666 | Result = DAG.getStore(Chain, dl, Result, Ptr, ST->getPointerInfo(), | ||||||||||
7667 | Alignment, ST->getMemOperand()->getFlags()); | ||||||||||
7668 | return Result; | ||||||||||
7669 | } | ||||||||||
7670 | // Do a (aligned) store to a stack slot, then copy from the stack slot | ||||||||||
7671 | // to the final destination using (unaligned) integer loads and stores. | ||||||||||
7672 | MVT RegVT = getRegisterType( | ||||||||||
7673 | *DAG.getContext(), | ||||||||||
7674 | EVT::getIntegerVT(*DAG.getContext(), StoreMemVT.getSizeInBits())); | ||||||||||
7675 | EVT PtrVT = Ptr.getValueType(); | ||||||||||
7676 | unsigned StoredBytes = StoreMemVT.getStoreSize(); | ||||||||||
7677 | unsigned RegBytes = RegVT.getSizeInBits() / 8; | ||||||||||
7678 | unsigned NumRegs = (StoredBytes + RegBytes - 1) / RegBytes; | ||||||||||
7679 | |||||||||||
7680 | // Make sure the stack slot is also aligned for the register type. | ||||||||||
7681 | SDValue StackPtr = DAG.CreateStackTemporary(StoreMemVT, RegVT); | ||||||||||
7682 | auto FrameIndex = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex(); | ||||||||||
7683 | |||||||||||
7684 | // Perform the original store, only redirected to the stack slot. | ||||||||||
7685 | SDValue Store = DAG.getTruncStore( | ||||||||||
7686 | Chain, dl, Val, StackPtr, | ||||||||||
7687 | MachinePointerInfo::getFixedStack(MF, FrameIndex, 0), StoreMemVT); | ||||||||||
7688 | |||||||||||
7689 | EVT StackPtrVT = StackPtr.getValueType(); | ||||||||||
7690 | |||||||||||
7691 | SDValue PtrIncrement = DAG.getConstant(RegBytes, dl, PtrVT); | ||||||||||
7692 | SDValue StackPtrIncrement = DAG.getConstant(RegBytes, dl, StackPtrVT); | ||||||||||
7693 | SmallVector<SDValue, 8> Stores; | ||||||||||
7694 | unsigned Offset = 0; | ||||||||||
7695 | |||||||||||
7696 | // Do all but one copies using the full register width. | ||||||||||
7697 | for (unsigned i = 1; i < NumRegs; i++) { | ||||||||||
7698 | // Load one integer register's worth from the stack slot. | ||||||||||
7699 | SDValue Load = DAG.getLoad( | ||||||||||
7700 | RegVT, dl, Store, StackPtr, | ||||||||||
7701 | MachinePointerInfo::getFixedStack(MF, FrameIndex, Offset)); | ||||||||||
7702 | // Store it to the final location. Remember the store. | ||||||||||
7703 | Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, Ptr, | ||||||||||
7704 | ST->getPointerInfo().getWithOffset(Offset), | ||||||||||
7705 | ST->getOriginalAlign(), | ||||||||||
7706 | ST->getMemOperand()->getFlags())); | ||||||||||
7707 | // Increment the pointers. | ||||||||||
7708 | Offset += RegBytes; | ||||||||||
7709 | StackPtr = DAG.getObjectPtrOffset(dl, StackPtr, StackPtrIncrement); | ||||||||||
7710 | Ptr = DAG.getObjectPtrOffset(dl, Ptr, PtrIncrement); | ||||||||||
7711 | } | ||||||||||
7712 | |||||||||||
7713 | // The last store may be partial. Do a truncating store. On big-endian | ||||||||||
7714 | // machines this requires an extending load from the stack slot to ensure | ||||||||||
7715 | // that the bits are in the right place. | ||||||||||
7716 | EVT LoadMemVT = | ||||||||||
7717 | EVT::getIntegerVT(*DAG.getContext(), 8 * (StoredBytes - Offset)); | ||||||||||
7718 | |||||||||||
7719 | // Load from the stack slot. | ||||||||||
7720 | SDValue Load = DAG.getExtLoad( | ||||||||||
7721 | ISD::EXTLOAD, dl, RegVT, Store, StackPtr, | ||||||||||
7722 | MachinePointerInfo::getFixedStack(MF, FrameIndex, Offset), LoadMemVT); | ||||||||||
7723 | |||||||||||
7724 | Stores.push_back( | ||||||||||
7725 | DAG.getTruncStore(Load.getValue(1), dl, Load, Ptr, | ||||||||||
7726 | ST->getPointerInfo().getWithOffset(Offset), LoadMemVT, | ||||||||||
7727 | ST->getOriginalAlign(), | ||||||||||
7728 | ST->getMemOperand()->getFlags(), ST->getAAInfo())); | ||||||||||
7729 | // The order of the stores doesn't matter - say it with a TokenFactor. | ||||||||||
7730 | SDValue Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Stores); | ||||||||||
7731 | return Result; | ||||||||||
7732 | } | ||||||||||
7733 | |||||||||||
7734 | assert(StoreMemVT.isInteger() && !StoreMemVT.isVector() &&(static_cast <bool> (StoreMemVT.isInteger() && ! StoreMemVT.isVector() && "Unaligned store of unknown type." ) ? void (0) : __assert_fail ("StoreMemVT.isInteger() && !StoreMemVT.isVector() && \"Unaligned store of unknown type.\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 7735, __extension__ __PRETTY_FUNCTION__)) | ||||||||||
7735 | "Unaligned store of unknown type.")(static_cast <bool> (StoreMemVT.isInteger() && ! StoreMemVT.isVector() && "Unaligned store of unknown type." ) ? void (0) : __assert_fail ("StoreMemVT.isInteger() && !StoreMemVT.isVector() && \"Unaligned store of unknown type.\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 7735, __extension__ __PRETTY_FUNCTION__)); | ||||||||||
7736 | // Get the half-size VT | ||||||||||
7737 | EVT NewStoredVT = StoreMemVT.getHalfSizedIntegerVT(*DAG.getContext()); | ||||||||||
7738 | unsigned NumBits = NewStoredVT.getFixedSizeInBits(); | ||||||||||
7739 | unsigned IncrementSize = NumBits / 8; | ||||||||||
7740 | |||||||||||
7741 | // Divide the stored value in two parts. | ||||||||||
7742 | SDValue ShiftAmount = DAG.getConstant( | ||||||||||
7743 | NumBits, dl, getShiftAmountTy(Val.getValueType(), DAG.getDataLayout())); | ||||||||||
7744 | SDValue Lo = Val; | ||||||||||
7745 | SDValue Hi = DAG.getNode(ISD::SRL, dl, VT, Val, ShiftAmount); | ||||||||||
7746 | |||||||||||
7747 | // Store the two parts | ||||||||||
7748 | SDValue Store1, Store2; | ||||||||||
7749 | Store1 = DAG.getTruncStore(Chain, dl, | ||||||||||
7750 | DAG.getDataLayout().isLittleEndian() ? Lo : Hi, | ||||||||||
7751 | Ptr, ST->getPointerInfo(), NewStoredVT, Alignment, | ||||||||||
7752 | ST->getMemOperand()->getFlags()); | ||||||||||
7753 | |||||||||||
7754 | Ptr = DAG.getObjectPtrOffset(dl, Ptr, TypeSize::Fixed(IncrementSize)); | ||||||||||
7755 | Store2 = DAG.getTruncStore( | ||||||||||
7756 | Chain, dl, DAG.getDataLayout().isLittleEndian() ? Hi : Lo, Ptr, | ||||||||||
7757 | ST->getPointerInfo().getWithOffset(IncrementSize), NewStoredVT, Alignment, | ||||||||||
7758 | ST->getMemOperand()->getFlags(), ST->getAAInfo()); | ||||||||||
7759 | |||||||||||
7760 | SDValue Result = | ||||||||||
7761 | DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Store1, Store2); | ||||||||||
7762 | return Result; | ||||||||||
7763 | } | ||||||||||
7764 | |||||||||||
7765 | SDValue | ||||||||||
7766 | TargetLowering::IncrementMemoryAddress(SDValue Addr, SDValue Mask, | ||||||||||
7767 | const SDLoc &DL, EVT DataVT, | ||||||||||
7768 | SelectionDAG &DAG, | ||||||||||
7769 | bool IsCompressedMemory) const { | ||||||||||
7770 | SDValue Increment; | ||||||||||
7771 | EVT AddrVT = Addr.getValueType(); | ||||||||||
7772 | EVT MaskVT = Mask.getValueType(); | ||||||||||
7773 | assert(DataVT.getVectorElementCount() == MaskVT.getVectorElementCount() &&(static_cast <bool> (DataVT.getVectorElementCount() == MaskVT .getVectorElementCount() && "Incompatible types of Data and Mask" ) ? void (0) : __assert_fail ("DataVT.getVectorElementCount() == MaskVT.getVectorElementCount() && \"Incompatible types of Data and Mask\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 7774, __extension__ __PRETTY_FUNCTION__)) | ||||||||||
7774 | "Incompatible types of Data and Mask")(static_cast <bool> (DataVT.getVectorElementCount() == MaskVT .getVectorElementCount() && "Incompatible types of Data and Mask" ) ? void (0) : __assert_fail ("DataVT.getVectorElementCount() == MaskVT.getVectorElementCount() && \"Incompatible types of Data and Mask\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 7774, __extension__ __PRETTY_FUNCTION__)); | ||||||||||
7775 | if (IsCompressedMemory) { | ||||||||||
7776 | if (DataVT.isScalableVector()) | ||||||||||
7777 | report_fatal_error( | ||||||||||
7778 | "Cannot currently handle compressed memory with scalable vectors"); | ||||||||||
7779 | // Incrementing the pointer according to number of '1's in the mask. | ||||||||||
7780 | EVT MaskIntVT = EVT::getIntegerVT(*DAG.getContext(), MaskVT.getSizeInBits()); | ||||||||||
7781 | SDValue MaskInIntReg = DAG.getBitcast(MaskIntVT, Mask); | ||||||||||
7782 | if (MaskIntVT.getSizeInBits() < 32) { | ||||||||||
7783 | MaskInIntReg = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, MaskInIntReg); | ||||||||||
7784 | MaskIntVT = MVT::i32; | ||||||||||
7785 | } | ||||||||||
7786 | |||||||||||
7787 | // Count '1's with POPCNT. | ||||||||||
7788 | Increment = DAG.getNode(ISD::CTPOP, DL, MaskIntVT, MaskInIntReg); | ||||||||||
7789 | Increment = DAG.getZExtOrTrunc(Increment, DL, AddrVT); | ||||||||||
7790 | // Scale is an element size in bytes. | ||||||||||
7791 | SDValue Scale = DAG.getConstant(DataVT.getScalarSizeInBits() / 8, DL, | ||||||||||
7792 | AddrVT); | ||||||||||
7793 | Increment = DAG.getNode(ISD::MUL, DL, AddrVT, Increment, Scale); | ||||||||||
7794 | } else if (DataVT.isScalableVector()) { | ||||||||||
7795 | Increment = DAG.getVScale(DL, AddrVT, | ||||||||||
7796 | APInt(AddrVT.getFixedSizeInBits(), | ||||||||||
7797 | DataVT.getStoreSize().getKnownMinSize())); | ||||||||||
7798 | } else | ||||||||||
7799 | Increment = DAG.getConstant(DataVT.getStoreSize(), DL, AddrVT); | ||||||||||
7800 | |||||||||||
7801 | return DAG.getNode(ISD::ADD, DL, AddrVT, Addr, Increment); | ||||||||||
7802 | } | ||||||||||
7803 | |||||||||||
7804 | static SDValue clampDynamicVectorIndex(SelectionDAG &DAG, SDValue Idx, | ||||||||||
7805 | EVT VecVT, const SDLoc &dl, | ||||||||||
7806 | ElementCount SubEC) { | ||||||||||
7807 | assert(!(SubEC.isScalable() && VecVT.isFixedLengthVector()) &&(static_cast <bool> (!(SubEC.isScalable() && VecVT .isFixedLengthVector()) && "Cannot index a scalable vector within a fixed-width vector" ) ? void (0) : __assert_fail ("!(SubEC.isScalable() && VecVT.isFixedLengthVector()) && \"Cannot index a scalable vector within a fixed-width vector\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 7808, __extension__ __PRETTY_FUNCTION__)) | ||||||||||
7808 | "Cannot index a scalable vector within a fixed-width vector")(static_cast <bool> (!(SubEC.isScalable() && VecVT .isFixedLengthVector()) && "Cannot index a scalable vector within a fixed-width vector" ) ? void (0) : __assert_fail ("!(SubEC.isScalable() && VecVT.isFixedLengthVector()) && \"Cannot index a scalable vector within a fixed-width vector\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 7808, __extension__ __PRETTY_FUNCTION__)); | ||||||||||
7809 | |||||||||||
7810 | unsigned NElts = VecVT.getVectorMinNumElements(); | ||||||||||
7811 | unsigned NumSubElts = SubEC.getKnownMinValue(); | ||||||||||
7812 | EVT IdxVT = Idx.getValueType(); | ||||||||||
7813 | |||||||||||
7814 | if (VecVT.isScalableVector() && !SubEC.isScalable()) { | ||||||||||
7815 | // If this is a constant index and we know the value plus the number of the | ||||||||||
7816 | // elements in the subvector minus one is less than the minimum number of | ||||||||||
7817 | // elements then it's safe to return Idx. | ||||||||||
7818 | if (auto *IdxCst = dyn_cast<ConstantSDNode>(Idx)) | ||||||||||
7819 | if (IdxCst->getZExtValue() + (NumSubElts - 1) < NElts) | ||||||||||
7820 | return Idx; | ||||||||||
7821 | SDValue VS = | ||||||||||
7822 | DAG.getVScale(dl, IdxVT, APInt(IdxVT.getFixedSizeInBits(), NElts)); | ||||||||||
7823 | unsigned SubOpcode = NumSubElts <= NElts ? ISD::SUB : ISD::USUBSAT; | ||||||||||
7824 | SDValue Sub = DAG.getNode(SubOpcode, dl, IdxVT, VS, | ||||||||||
7825 | DAG.getConstant(NumSubElts, dl, IdxVT)); | ||||||||||
7826 | return DAG.getNode(ISD::UMIN, dl, IdxVT, Idx, Sub); | ||||||||||
7827 | } | ||||||||||
7828 | if (isPowerOf2_32(NElts) && NumSubElts == 1) { | ||||||||||
7829 | APInt Imm = APInt::getLowBitsSet(IdxVT.getSizeInBits(), Log2_32(NElts)); | ||||||||||
7830 | return DAG.getNode(ISD::AND, dl, IdxVT, Idx, | ||||||||||
7831 | DAG.getConstant(Imm, dl, IdxVT)); | ||||||||||
7832 | } | ||||||||||
7833 | unsigned MaxIndex = NumSubElts < NElts ? NElts - NumSubElts : 0; | ||||||||||
7834 | return DAG.getNode(ISD::UMIN, dl, IdxVT, Idx, | ||||||||||
7835 | DAG.getConstant(MaxIndex, dl, IdxVT)); | ||||||||||
7836 | } | ||||||||||
7837 | |||||||||||
7838 | SDValue TargetLowering::getVectorElementPointer(SelectionDAG &DAG, | ||||||||||
7839 | SDValue VecPtr, EVT VecVT, | ||||||||||
7840 | SDValue Index) const { | ||||||||||
7841 | return getVectorSubVecPointer( | ||||||||||
7842 | DAG, VecPtr, VecVT, | ||||||||||
7843 | EVT::getVectorVT(*DAG.getContext(), VecVT.getVectorElementType(), 1), | ||||||||||
7844 | Index); | ||||||||||
7845 | } | ||||||||||
7846 | |||||||||||
7847 | SDValue TargetLowering::getVectorSubVecPointer(SelectionDAG &DAG, | ||||||||||
7848 | SDValue VecPtr, EVT VecVT, | ||||||||||
7849 | EVT SubVecVT, | ||||||||||
7850 | SDValue Index) const { | ||||||||||
7851 | SDLoc dl(Index); | ||||||||||
7852 | // Make sure the index type is big enough to compute in. | ||||||||||
7853 | Index = DAG.getZExtOrTrunc(Index, dl, VecPtr.getValueType()); | ||||||||||
7854 | |||||||||||
7855 | EVT EltVT = VecVT.getVectorElementType(); | ||||||||||
7856 | |||||||||||
7857 | // Calculate the element offset and add it to the pointer. | ||||||||||
7858 | unsigned EltSize = EltVT.getFixedSizeInBits() / 8; // FIXME: should be ABI size. | ||||||||||
7859 | assert(EltSize * 8 == EltVT.getFixedSizeInBits() &&(static_cast <bool> (EltSize * 8 == EltVT.getFixedSizeInBits () && "Converting bits to bytes lost precision") ? void (0) : __assert_fail ("EltSize * 8 == EltVT.getFixedSizeInBits() && \"Converting bits to bytes lost precision\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 7860, __extension__ __PRETTY_FUNCTION__)) | ||||||||||
7860 | "Converting bits to bytes lost precision")(static_cast <bool> (EltSize * 8 == EltVT.getFixedSizeInBits () && "Converting bits to bytes lost precision") ? void (0) : __assert_fail ("EltSize * 8 == EltVT.getFixedSizeInBits() && \"Converting bits to bytes lost precision\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 7860, __extension__ __PRETTY_FUNCTION__)); | ||||||||||
7861 | assert(SubVecVT.getVectorElementType() == EltVT &&(static_cast <bool> (SubVecVT.getVectorElementType() == EltVT && "Sub-vector must be a vector with matching element type" ) ? void (0) : __assert_fail ("SubVecVT.getVectorElementType() == EltVT && \"Sub-vector must be a vector with matching element type\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 7862, __extension__ __PRETTY_FUNCTION__)) | ||||||||||
7862 | "Sub-vector must be a vector with matching element type")(static_cast <bool> (SubVecVT.getVectorElementType() == EltVT && "Sub-vector must be a vector with matching element type" ) ? void (0) : __assert_fail ("SubVecVT.getVectorElementType() == EltVT && \"Sub-vector must be a vector with matching element type\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 7862, __extension__ __PRETTY_FUNCTION__)); | ||||||||||
7863 | Index = clampDynamicVectorIndex(DAG, Index, VecVT, dl, | ||||||||||
7864 | SubVecVT.getVectorElementCount()); | ||||||||||
7865 | |||||||||||
7866 | EVT IdxVT = Index.getValueType(); | ||||||||||
7867 | if (SubVecVT.isScalableVector()) | ||||||||||
7868 | Index = | ||||||||||
7869 | DAG.getNode(ISD::MUL, dl, IdxVT, Index, | ||||||||||
7870 | DAG.getVScale(dl, IdxVT, APInt(IdxVT.getSizeInBits(), 1))); | ||||||||||
7871 | |||||||||||
7872 | Index = DAG.getNode(ISD::MUL, dl, IdxVT, Index, | ||||||||||
7873 | DAG.getConstant(EltSize, dl, IdxVT)); | ||||||||||
7874 | return DAG.getMemBasePlusOffset(VecPtr, Index, dl); | ||||||||||
7875 | } | ||||||||||
7876 | |||||||||||
7877 | //===----------------------------------------------------------------------===// | ||||||||||
7878 | // Implementation of Emulated TLS Model | ||||||||||
7879 | //===----------------------------------------------------------------------===// | ||||||||||
7880 | |||||||||||
7881 | SDValue TargetLowering::LowerToTLSEmulatedModel(const GlobalAddressSDNode *GA, | ||||||||||
7882 | SelectionDAG &DAG) const { | ||||||||||
7883 | // Access to address of TLS varialbe xyz is lowered to a function call: | ||||||||||
7884 | // __emutls_get_address( address of global variable named "__emutls_v.xyz" ) | ||||||||||
7885 | EVT PtrVT = getPointerTy(DAG.getDataLayout()); | ||||||||||
7886 | PointerType *VoidPtrType = Type::getInt8PtrTy(*DAG.getContext()); | ||||||||||
7887 | SDLoc dl(GA); | ||||||||||
7888 | |||||||||||
7889 | ArgListTy Args; | ||||||||||
7890 | ArgListEntry Entry; | ||||||||||
7891 | std::string NameString = ("__emutls_v." + GA->getGlobal()->getName()).str(); | ||||||||||
7892 | Module *VariableModule = const_cast<Module*>(GA->getGlobal()->getParent()); | ||||||||||
7893 | StringRef EmuTlsVarName(NameString); | ||||||||||
7894 | GlobalVariable *EmuTlsVar = VariableModule->getNamedGlobal(EmuTlsVarName); | ||||||||||
7895 | assert(EmuTlsVar && "Cannot find EmuTlsVar ")(static_cast <bool> (EmuTlsVar && "Cannot find EmuTlsVar " ) ? void (0) : __assert_fail ("EmuTlsVar && \"Cannot find EmuTlsVar \"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 7895, __extension__ __PRETTY_FUNCTION__)); | ||||||||||
7896 | Entry.Node = DAG.getGlobalAddress(EmuTlsVar, dl, PtrVT); | ||||||||||
7897 | Entry.Ty = VoidPtrType; | ||||||||||
7898 | Args.push_back(Entry); | ||||||||||
7899 | |||||||||||
7900 | SDValue EmuTlsGetAddr = DAG.getExternalSymbol("__emutls_get_address", PtrVT); | ||||||||||
7901 | |||||||||||
7902 | TargetLowering::CallLoweringInfo CLI(DAG); | ||||||||||
7903 | CLI.setDebugLoc(dl).setChain(DAG.getEntryNode()); | ||||||||||
7904 | CLI.setLibCallee(CallingConv::C, VoidPtrType, EmuTlsGetAddr, std::move(Args)); | ||||||||||
7905 | std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI); | ||||||||||
7906 | |||||||||||
7907 | // TLSADDR will be codegen'ed as call. Inform MFI that function has calls. | ||||||||||
7908 | // At last for X86 targets, maybe good for other targets too? | ||||||||||
7909 | MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo(); | ||||||||||
7910 | MFI.setAdjustsStack(true); // Is this only for X86 target? | ||||||||||
7911 | MFI.setHasCalls(true); | ||||||||||
7912 | |||||||||||
7913 | assert((GA->getOffset() == 0) &&(static_cast <bool> ((GA->getOffset() == 0) && "Emulated TLS must have zero offset in GlobalAddressSDNode") ? void (0) : __assert_fail ("(GA->getOffset() == 0) && \"Emulated TLS must have zero offset in GlobalAddressSDNode\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 7914, __extension__ __PRETTY_FUNCTION__)) | ||||||||||
7914 | "Emulated TLS must have zero offset in GlobalAddressSDNode")(static_cast <bool> ((GA->getOffset() == 0) && "Emulated TLS must have zero offset in GlobalAddressSDNode") ? void (0) : __assert_fail ("(GA->getOffset() == 0) && \"Emulated TLS must have zero offset in GlobalAddressSDNode\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 7914, __extension__ __PRETTY_FUNCTION__)); | ||||||||||
7915 | return CallResult.first; | ||||||||||
7916 | } | ||||||||||
7917 | |||||||||||
7918 | SDValue TargetLowering::lowerCmpEqZeroToCtlzSrl(SDValue Op, | ||||||||||
7919 | SelectionDAG &DAG) const { | ||||||||||
7920 | assert((Op->getOpcode() == ISD::SETCC) && "Input has to be a SETCC node.")(static_cast <bool> ((Op->getOpcode() == ISD::SETCC) && "Input has to be a SETCC node.") ? void (0) : __assert_fail ("(Op->getOpcode() == ISD::SETCC) && \"Input has to be a SETCC node.\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 7920, __extension__ __PRETTY_FUNCTION__)); | ||||||||||
7921 | if (!isCtlzFast()) | ||||||||||
7922 | return SDValue(); | ||||||||||
7923 | ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); | ||||||||||
7924 | SDLoc dl(Op); | ||||||||||
7925 | if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { | ||||||||||
7926 | if (C->isZero() && CC == ISD::SETEQ) { | ||||||||||
7927 | EVT VT = Op.getOperand(0).getValueType(); | ||||||||||
7928 | SDValue Zext = Op.getOperand(0); | ||||||||||
7929 | if (VT.bitsLT(MVT::i32)) { | ||||||||||
7930 | VT = MVT::i32; | ||||||||||
7931 | Zext = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Op.getOperand(0)); | ||||||||||
7932 | } | ||||||||||
7933 | unsigned Log2b = Log2_32(VT.getSizeInBits()); | ||||||||||
7934 | SDValue Clz = DAG.getNode(ISD::CTLZ, dl, VT, Zext); | ||||||||||
7935 | SDValue Scc = DAG.getNode(ISD::SRL, dl, VT, Clz, | ||||||||||
7936 | DAG.getConstant(Log2b, dl, MVT::i32)); | ||||||||||
7937 | return DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Scc); | ||||||||||
7938 | } | ||||||||||
7939 | } | ||||||||||
7940 | return SDValue(); | ||||||||||
7941 | } | ||||||||||
7942 | |||||||||||
7943 | // Convert redundant addressing modes (e.g. scaling is redundant | ||||||||||
7944 | // when accessing bytes). | ||||||||||
7945 | ISD::MemIndexType | ||||||||||
7946 | TargetLowering::getCanonicalIndexType(ISD::MemIndexType IndexType, EVT MemVT, | ||||||||||
7947 | SDValue Offsets) const { | ||||||||||
7948 | bool IsScaledIndex = | ||||||||||
7949 | (IndexType == ISD::SIGNED_SCALED) || (IndexType == ISD::UNSIGNED_SCALED); | ||||||||||
7950 | bool IsSignedIndex = | ||||||||||
7951 | (IndexType == ISD::SIGNED_SCALED) || (IndexType == ISD::SIGNED_UNSCALED); | ||||||||||
7952 | |||||||||||
7953 | // Scaling is unimportant for bytes, canonicalize to unscaled. | ||||||||||
7954 | if (IsScaledIndex && MemVT.getScalarType() == MVT::i8) | ||||||||||
7955 | return IsSignedIndex ? ISD::SIGNED_UNSCALED : ISD::UNSIGNED_UNSCALED; | ||||||||||
7956 | |||||||||||
7957 | return IndexType; | ||||||||||
7958 | } | ||||||||||
7959 | |||||||||||
7960 | SDValue TargetLowering::expandIntMINMAX(SDNode *Node, SelectionDAG &DAG) const { | ||||||||||
7961 | SDValue Op0 = Node->getOperand(0); | ||||||||||
7962 | SDValue Op1 = Node->getOperand(1); | ||||||||||
7963 | EVT VT = Op0.getValueType(); | ||||||||||
7964 | unsigned Opcode = Node->getOpcode(); | ||||||||||
7965 | SDLoc DL(Node); | ||||||||||
7966 | |||||||||||
7967 | // umin(x,y) -> sub(x,usubsat(x,y)) | ||||||||||
7968 | if (Opcode == ISD::UMIN && isOperationLegal(ISD::SUB, VT) && | ||||||||||
7969 | isOperationLegal(ISD::USUBSAT, VT)) { | ||||||||||
7970 | return DAG.getNode(ISD::SUB, DL, VT, Op0, | ||||||||||
7971 | DAG.getNode(ISD::USUBSAT, DL, VT, Op0, Op1)); | ||||||||||
7972 | } | ||||||||||
7973 | |||||||||||
7974 | // umax(x,y) -> add(x,usubsat(y,x)) | ||||||||||
7975 | if (Opcode == ISD::UMAX && isOperationLegal(ISD::ADD, VT) && | ||||||||||
7976 | isOperationLegal(ISD::USUBSAT, VT)) { | ||||||||||
7977 | return DAG.getNode(ISD::ADD, DL, VT, Op0, | ||||||||||
7978 | DAG.getNode(ISD::USUBSAT, DL, VT, Op1, Op0)); | ||||||||||
7979 | } | ||||||||||
7980 | |||||||||||
7981 | // Expand Y = MAX(A, B) -> Y = (A > B) ? A : B | ||||||||||
7982 | ISD::CondCode CC; | ||||||||||
7983 | switch (Opcode) { | ||||||||||
7984 | default: llvm_unreachable("How did we get here?")::llvm::llvm_unreachable_internal("How did we get here?", "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 7984); | ||||||||||
7985 | case ISD::SMAX: CC = ISD::SETGT; break; | ||||||||||
7986 | case ISD::SMIN: CC = ISD::SETLT; break; | ||||||||||
7987 | case ISD::UMAX: CC = ISD::SETUGT; break; | ||||||||||
7988 | case ISD::UMIN: CC = ISD::SETULT; break; | ||||||||||
7989 | } | ||||||||||
7990 | |||||||||||
7991 | // FIXME: Should really try to split the vector in case it's legal on a | ||||||||||
7992 | // subvector. | ||||||||||
7993 | if (VT.isVector() && !isOperationLegalOrCustom(ISD::VSELECT, VT)) | ||||||||||
7994 | return DAG.UnrollVectorOp(Node); | ||||||||||
7995 | |||||||||||
7996 | SDValue Cond = DAG.getSetCC(DL, VT, Op0, Op1, CC); | ||||||||||
7997 | return DAG.getSelect(DL, VT, Cond, Op0, Op1); | ||||||||||
7998 | } | ||||||||||
7999 | |||||||||||
8000 | SDValue TargetLowering::expandAddSubSat(SDNode *Node, SelectionDAG &DAG) const { | ||||||||||
8001 | unsigned Opcode = Node->getOpcode(); | ||||||||||
8002 | SDValue LHS = Node->getOperand(0); | ||||||||||
8003 | SDValue RHS = Node->getOperand(1); | ||||||||||
8004 | EVT VT = LHS.getValueType(); | ||||||||||
8005 | SDLoc dl(Node); | ||||||||||
8006 | |||||||||||
8007 | assert(VT == RHS.getValueType() && "Expected operands to be the same type")(static_cast <bool> (VT == RHS.getValueType() && "Expected operands to be the same type") ? void (0) : __assert_fail ("VT == RHS.getValueType() && \"Expected operands to be the same type\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 8007, __extension__ __PRETTY_FUNCTION__)); | ||||||||||
8008 | assert(VT.isInteger() && "Expected operands to be integers")(static_cast <bool> (VT.isInteger() && "Expected operands to be integers" ) ? void (0) : __assert_fail ("VT.isInteger() && \"Expected operands to be integers\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 8008, __extension__ __PRETTY_FUNCTION__)); | ||||||||||
8009 | |||||||||||
8010 | // usub.sat(a, b) -> umax(a, b) - b | ||||||||||
8011 | if (Opcode == ISD::USUBSAT && isOperationLegal(ISD::UMAX, VT)) { | ||||||||||
8012 | SDValue Max = DAG.getNode(ISD::UMAX, dl, VT, LHS, RHS); | ||||||||||
8013 | return DAG.getNode(ISD::SUB, dl, VT, Max, RHS); | ||||||||||
8014 | } | ||||||||||
8015 | |||||||||||
8016 | // uadd.sat(a, b) -> umin(a, ~b) + b | ||||||||||
8017 | if (Opcode == ISD::UADDSAT && isOperationLegal(ISD::UMIN, VT)) { | ||||||||||
8018 | SDValue InvRHS = DAG.getNOT(dl, RHS, VT); | ||||||||||
8019 | SDValue Min = DAG.getNode(ISD::UMIN, dl, VT, LHS, InvRHS); | ||||||||||
8020 | return DAG.getNode(ISD::ADD, dl, VT, Min, RHS); | ||||||||||
8021 | } | ||||||||||
8022 | |||||||||||
8023 | unsigned OverflowOp; | ||||||||||
8024 | switch (Opcode) { | ||||||||||
8025 | case ISD::SADDSAT: | ||||||||||
8026 | OverflowOp = ISD::SADDO; | ||||||||||
8027 | break; | ||||||||||
8028 | case ISD::UADDSAT: | ||||||||||
8029 | OverflowOp = ISD::UADDO; | ||||||||||
8030 | break; | ||||||||||
8031 | case ISD::SSUBSAT: | ||||||||||
8032 | OverflowOp = ISD::SSUBO; | ||||||||||
8033 | break; | ||||||||||
8034 | case ISD::USUBSAT: | ||||||||||
8035 | OverflowOp = ISD::USUBO; | ||||||||||
8036 | break; | ||||||||||
8037 | default: | ||||||||||
8038 | llvm_unreachable("Expected method to receive signed or unsigned saturation "::llvm::llvm_unreachable_internal("Expected method to receive signed or unsigned saturation " "addition or subtraction node.", "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 8039) | ||||||||||
8039 | "addition or subtraction node.")::llvm::llvm_unreachable_internal("Expected method to receive signed or unsigned saturation " "addition or subtraction node.", "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 8039); | ||||||||||
8040 | } | ||||||||||
8041 | |||||||||||
8042 | // FIXME: Should really try to split the vector in case it's legal on a | ||||||||||
8043 | // subvector. | ||||||||||
8044 | if (VT.isVector() && !isOperationLegalOrCustom(ISD::VSELECT, VT)) | ||||||||||
8045 | return DAG.UnrollVectorOp(Node); | ||||||||||
8046 | |||||||||||
8047 | unsigned BitWidth = LHS.getScalarValueSizeInBits(); | ||||||||||
8048 | EVT BoolVT = getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT); | ||||||||||
8049 | SDValue Result = DAG.getNode(OverflowOp, dl, DAG.getVTList(VT, BoolVT), LHS, RHS); | ||||||||||
8050 | SDValue SumDiff = Result.getValue(0); | ||||||||||
8051 | SDValue Overflow = Result.getValue(1); | ||||||||||
8052 | SDValue Zero = DAG.getConstant(0, dl, VT); | ||||||||||
8053 | SDValue AllOnes = DAG.getAllOnesConstant(dl, VT); | ||||||||||
8054 | |||||||||||
8055 | if (Opcode == ISD::UADDSAT) { | ||||||||||
8056 | if (getBooleanContents(VT) == ZeroOrNegativeOneBooleanContent) { | ||||||||||
8057 | // (LHS + RHS) | OverflowMask | ||||||||||
8058 | SDValue OverflowMask = DAG.getSExtOrTrunc(Overflow, dl, VT); | ||||||||||
8059 | return DAG.getNode(ISD::OR, dl, VT, SumDiff, OverflowMask); | ||||||||||
8060 | } | ||||||||||
8061 | // Overflow ? 0xffff.... : (LHS + RHS) | ||||||||||
8062 | return DAG.getSelect(dl, VT, Overflow, AllOnes, SumDiff); | ||||||||||
8063 | } | ||||||||||
8064 | |||||||||||
8065 | if (Opcode == ISD::USUBSAT) { | ||||||||||
8066 | if (getBooleanContents(VT) == ZeroOrNegativeOneBooleanContent) { | ||||||||||
8067 | // (LHS - RHS) & ~OverflowMask | ||||||||||
8068 | SDValue OverflowMask = DAG.getSExtOrTrunc(Overflow, dl, VT); | ||||||||||
8069 | SDValue Not = DAG.getNOT(dl, OverflowMask, VT); | ||||||||||
8070 | return DAG.getNode(ISD::AND, dl, VT, SumDiff, Not); | ||||||||||
8071 | } | ||||||||||
8072 | // Overflow ? 0 : (LHS - RHS) | ||||||||||
8073 | return DAG.getSelect(dl, VT, Overflow, Zero, SumDiff); | ||||||||||
8074 | } | ||||||||||
8075 | |||||||||||
8076 | // Overflow ? (SumDiff >> BW) ^ MinVal : SumDiff | ||||||||||
8077 | APInt MinVal = APInt::getSignedMinValue(BitWidth); | ||||||||||
8078 | SDValue SatMin = DAG.getConstant(MinVal, dl, VT); | ||||||||||
8079 | SDValue Shift = DAG.getNode(ISD::SRA, dl, VT, SumDiff, | ||||||||||
8080 | DAG.getConstant(BitWidth - 1, dl, VT)); | ||||||||||
8081 | Result = DAG.getNode(ISD::XOR, dl, VT, Shift, SatMin); | ||||||||||
8082 | return DAG.getSelect(dl, VT, Overflow, Result, SumDiff); | ||||||||||
8083 | } | ||||||||||
8084 | |||||||||||
8085 | SDValue TargetLowering::expandShlSat(SDNode *Node, SelectionDAG &DAG) const { | ||||||||||
8086 | unsigned Opcode = Node->getOpcode(); | ||||||||||
8087 | bool IsSigned = Opcode == ISD::SSHLSAT; | ||||||||||
8088 | SDValue LHS = Node->getOperand(0); | ||||||||||
8089 | SDValue RHS = Node->getOperand(1); | ||||||||||
8090 | EVT VT = LHS.getValueType(); | ||||||||||
8091 | SDLoc dl(Node); | ||||||||||
8092 | |||||||||||
8093 | assert((Node->getOpcode() == ISD::SSHLSAT ||(static_cast <bool> ((Node->getOpcode() == ISD::SSHLSAT || Node->getOpcode() == ISD::USHLSAT) && "Expected a SHLSAT opcode" ) ? void (0) : __assert_fail ("(Node->getOpcode() == ISD::SSHLSAT || Node->getOpcode() == ISD::USHLSAT) && \"Expected a SHLSAT opcode\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 8095, __extension__ __PRETTY_FUNCTION__)) | ||||||||||
8094 | Node->getOpcode() == ISD::USHLSAT) &&(static_cast <bool> ((Node->getOpcode() == ISD::SSHLSAT || Node->getOpcode() == ISD::USHLSAT) && "Expected a SHLSAT opcode" ) ? void (0) : __assert_fail ("(Node->getOpcode() == ISD::SSHLSAT || Node->getOpcode() == ISD::USHLSAT) && \"Expected a SHLSAT opcode\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 8095, __extension__ __PRETTY_FUNCTION__)) | ||||||||||
8095 | "Expected a SHLSAT opcode")(static_cast <bool> ((Node->getOpcode() == ISD::SSHLSAT || Node->getOpcode() == ISD::USHLSAT) && "Expected a SHLSAT opcode" ) ? void (0) : __assert_fail ("(Node->getOpcode() == ISD::SSHLSAT || Node->getOpcode() == ISD::USHLSAT) && \"Expected a SHLSAT opcode\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 8095, __extension__ __PRETTY_FUNCTION__)); | ||||||||||
8096 | assert(VT == RHS.getValueType() && "Expected operands to be the same type")(static_cast <bool> (VT == RHS.getValueType() && "Expected operands to be the same type") ? void (0) : __assert_fail ("VT == RHS.getValueType() && \"Expected operands to be the same type\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 8096, __extension__ __PRETTY_FUNCTION__)); | ||||||||||
8097 | assert(VT.isInteger() && "Expected operands to be integers")(static_cast <bool> (VT.isInteger() && "Expected operands to be integers" ) ? void (0) : __assert_fail ("VT.isInteger() && \"Expected operands to be integers\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 8097, __extension__ __PRETTY_FUNCTION__)); | ||||||||||
8098 | |||||||||||
8099 | // If LHS != (LHS << RHS) >> RHS, we have overflow and must saturate. | ||||||||||
8100 | |||||||||||
8101 | unsigned BW = VT.getScalarSizeInBits(); | ||||||||||
8102 | SDValue Result = DAG.getNode(ISD::SHL, dl, VT, LHS, RHS); | ||||||||||
8103 | SDValue Orig = | ||||||||||
8104 | DAG.getNode(IsSigned ? ISD::SRA : ISD::SRL, dl, VT, Result, RHS); | ||||||||||
8105 | |||||||||||
8106 | SDValue SatVal; | ||||||||||
8107 | if (IsSigned) { | ||||||||||
8108 | SDValue SatMin = DAG.getConstant(APInt::getSignedMinValue(BW), dl, VT); | ||||||||||
8109 | SDValue SatMax = DAG.getConstant(APInt::getSignedMaxValue(BW), dl, VT); | ||||||||||
8110 | SatVal = DAG.getSelectCC(dl, LHS, DAG.getConstant(0, dl, VT), | ||||||||||
8111 | SatMin, SatMax, ISD::SETLT); | ||||||||||
8112 | } else { | ||||||||||
8113 | SatVal = DAG.getConstant(APInt::getMaxValue(BW), dl, VT); | ||||||||||
8114 | } | ||||||||||
8115 | Result = DAG.getSelectCC(dl, LHS, Orig, SatVal, Result, ISD::SETNE); | ||||||||||
8116 | |||||||||||
8117 | return Result; | ||||||||||
8118 | } | ||||||||||
8119 | |||||||||||
8120 | SDValue | ||||||||||
8121 | TargetLowering::expandFixedPointMul(SDNode *Node, SelectionDAG &DAG) const { | ||||||||||
8122 | assert((Node->getOpcode() == ISD::SMULFIX ||(static_cast <bool> ((Node->getOpcode() == ISD::SMULFIX || Node->getOpcode() == ISD::UMULFIX || Node->getOpcode () == ISD::SMULFIXSAT || Node->getOpcode() == ISD::UMULFIXSAT ) && "Expected a fixed point multiplication opcode") ? void (0) : __assert_fail ("(Node->getOpcode() == ISD::SMULFIX || Node->getOpcode() == ISD::UMULFIX || Node->getOpcode() == ISD::SMULFIXSAT || Node->getOpcode() == ISD::UMULFIXSAT) && \"Expected a fixed point multiplication opcode\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 8126, __extension__ __PRETTY_FUNCTION__)) | ||||||||||
8123 | Node->getOpcode() == ISD::UMULFIX ||(static_cast <bool> ((Node->getOpcode() == ISD::SMULFIX || Node->getOpcode() == ISD::UMULFIX || Node->getOpcode () == ISD::SMULFIXSAT || Node->getOpcode() == ISD::UMULFIXSAT ) && "Expected a fixed point multiplication opcode") ? void (0) : __assert_fail ("(Node->getOpcode() == ISD::SMULFIX || Node->getOpcode() == ISD::UMULFIX || Node->getOpcode() == ISD::SMULFIXSAT || Node->getOpcode() == ISD::UMULFIXSAT) && \"Expected a fixed point multiplication opcode\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 8126, __extension__ __PRETTY_FUNCTION__)) | ||||||||||
8124 | Node->getOpcode() == ISD::SMULFIXSAT ||(static_cast <bool> ((Node->getOpcode() == ISD::SMULFIX || Node->getOpcode() == ISD::UMULFIX || Node->getOpcode () == ISD::SMULFIXSAT || Node->getOpcode() == ISD::UMULFIXSAT ) && "Expected a fixed point multiplication opcode") ? void (0) : __assert_fail ("(Node->getOpcode() == ISD::SMULFIX || Node->getOpcode() == ISD::UMULFIX || Node->getOpcode() == ISD::SMULFIXSAT || Node->getOpcode() == ISD::UMULFIXSAT) && \"Expected a fixed point multiplication opcode\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 8126, __extension__ __PRETTY_FUNCTION__)) | ||||||||||
8125 | Node->getOpcode() == ISD::UMULFIXSAT) &&(static_cast <bool> ((Node->getOpcode() == ISD::SMULFIX || Node->getOpcode() == ISD::UMULFIX || Node->getOpcode () == ISD::SMULFIXSAT || Node->getOpcode() == ISD::UMULFIXSAT ) && "Expected a fixed point multiplication opcode") ? void (0) : __assert_fail ("(Node->getOpcode() == ISD::SMULFIX || Node->getOpcode() == ISD::UMULFIX || Node->getOpcode() == ISD::SMULFIXSAT || Node->getOpcode() == ISD::UMULFIXSAT) && \"Expected a fixed point multiplication opcode\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 8126, __extension__ __PRETTY_FUNCTION__)) | ||||||||||
8126 | "Expected a fixed point multiplication opcode")(static_cast <bool> ((Node->getOpcode() == ISD::SMULFIX || Node->getOpcode() == ISD::UMULFIX || Node->getOpcode () == ISD::SMULFIXSAT || Node->getOpcode() == ISD::UMULFIXSAT ) && "Expected a fixed point multiplication opcode") ? void (0) : __assert_fail ("(Node->getOpcode() == ISD::SMULFIX || Node->getOpcode() == ISD::UMULFIX || Node->getOpcode() == ISD::SMULFIXSAT || Node->getOpcode() == ISD::UMULFIXSAT) && \"Expected a fixed point multiplication opcode\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 8126, __extension__ __PRETTY_FUNCTION__)); | ||||||||||
8127 | |||||||||||
8128 | SDLoc dl(Node); | ||||||||||
8129 | SDValue LHS = Node->getOperand(0); | ||||||||||
8130 | SDValue RHS = Node->getOperand(1); | ||||||||||
8131 | EVT VT = LHS.getValueType(); | ||||||||||
8132 | unsigned Scale = Node->getConstantOperandVal(2); | ||||||||||
8133 | bool Saturating = (Node->getOpcode() == ISD::SMULFIXSAT || | ||||||||||
8134 | Node->getOpcode() == ISD::UMULFIXSAT); | ||||||||||
8135 | bool Signed = (Node->getOpcode() == ISD::SMULFIX || | ||||||||||
8136 | Node->getOpcode() == ISD::SMULFIXSAT); | ||||||||||
8137 | EVT BoolVT = getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT); | ||||||||||
8138 | unsigned VTSize = VT.getScalarSizeInBits(); | ||||||||||
8139 | |||||||||||
8140 | if (!Scale) { | ||||||||||
8141 | // [us]mul.fix(a, b, 0) -> mul(a, b) | ||||||||||
8142 | if (!Saturating) { | ||||||||||
8143 | if (isOperationLegalOrCustom(ISD::MUL, VT)) | ||||||||||
8144 | return DAG.getNode(ISD::MUL, dl, VT, LHS, RHS); | ||||||||||
8145 | } else if (Signed && isOperationLegalOrCustom(ISD::SMULO, VT)) { | ||||||||||
8146 | SDValue Result = | ||||||||||
8147 | DAG.getNode(ISD::SMULO, dl, DAG.getVTList(VT, BoolVT), LHS, RHS); | ||||||||||
8148 | SDValue Product = Result.getValue(0); | ||||||||||
8149 | SDValue Overflow = Result.getValue(1); | ||||||||||
8150 | SDValue Zero = DAG.getConstant(0, dl, VT); | ||||||||||
8151 | |||||||||||
8152 | APInt MinVal = APInt::getSignedMinValue(VTSize); | ||||||||||
8153 | APInt MaxVal = APInt::getSignedMaxValue(VTSize); | ||||||||||
8154 | SDValue SatMin = DAG.getConstant(MinVal, dl, VT); | ||||||||||
8155 | SDValue SatMax = DAG.getConstant(MaxVal, dl, VT); | ||||||||||
8156 | // Xor the inputs, if resulting sign bit is 0 the product will be | ||||||||||
8157 | // positive, else negative. | ||||||||||
8158 | SDValue Xor = DAG.getNode(ISD::XOR, dl, VT, LHS, RHS); | ||||||||||
8159 | SDValue ProdNeg = DAG.getSetCC(dl, BoolVT, Xor, Zero, ISD::SETLT); | ||||||||||
8160 | Result = DAG.getSelect(dl, VT, ProdNeg, SatMin, SatMax); | ||||||||||
8161 | return DAG.getSelect(dl, VT, Overflow, Result, Product); | ||||||||||
8162 | } else if (!Signed && isOperationLegalOrCustom(ISD::UMULO, VT)) { | ||||||||||
8163 | SDValue Result = | ||||||||||
8164 | DAG.getNode(ISD::UMULO, dl, DAG.getVTList(VT, BoolVT), LHS, RHS); | ||||||||||
8165 | SDValue Product = Result.getValue(0); | ||||||||||
8166 | SDValue Overflow = Result.getValue(1); | ||||||||||
8167 | |||||||||||
8168 | APInt MaxVal = APInt::getMaxValue(VTSize); | ||||||||||
8169 | SDValue SatMax = DAG.getConstant(MaxVal, dl, VT); | ||||||||||
8170 | return DAG.getSelect(dl, VT, Overflow, SatMax, Product); | ||||||||||
8171 | } | ||||||||||
8172 | } | ||||||||||
8173 | |||||||||||
8174 | assert(((Signed && Scale < VTSize) || (!Signed && Scale <= VTSize)) &&(static_cast <bool> (((Signed && Scale < VTSize ) || (!Signed && Scale <= VTSize)) && "Expected scale to be less than the number of bits if signed or at " "most the number of bits if unsigned.") ? void (0) : __assert_fail ("((Signed && Scale < VTSize) || (!Signed && Scale <= VTSize)) && \"Expected scale to be less than the number of bits if signed or at \" \"most the number of bits if unsigned.\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 8176, __extension__ __PRETTY_FUNCTION__)) | ||||||||||
8175 | "Expected scale to be less than the number of bits if signed or at "(static_cast <bool> (((Signed && Scale < VTSize ) || (!Signed && Scale <= VTSize)) && "Expected scale to be less than the number of bits if signed or at " "most the number of bits if unsigned.") ? void (0) : __assert_fail ("((Signed && Scale < VTSize) || (!Signed && Scale <= VTSize)) && \"Expected scale to be less than the number of bits if signed or at \" \"most the number of bits if unsigned.\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 8176, __extension__ __PRETTY_FUNCTION__)) | ||||||||||
8176 | "most the number of bits if unsigned.")(static_cast <bool> (((Signed && Scale < VTSize ) || (!Signed && Scale <= VTSize)) && "Expected scale to be less than the number of bits if signed or at " "most the number of bits if unsigned.") ? void (0) : __assert_fail ("((Signed && Scale < VTSize) || (!Signed && Scale <= VTSize)) && \"Expected scale to be less than the number of bits if signed or at \" \"most the number of bits if unsigned.\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 8176, __extension__ __PRETTY_FUNCTION__)); | ||||||||||
8177 | assert(LHS.getValueType() == RHS.getValueType() &&(static_cast <bool> (LHS.getValueType() == RHS.getValueType () && "Expected both operands to be the same type") ? void (0) : __assert_fail ("LHS.getValueType() == RHS.getValueType() && \"Expected both operands to be the same type\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 8178, __extension__ __PRETTY_FUNCTION__)) | ||||||||||
8178 | "Expected both operands to be the same type")(static_cast <bool> (LHS.getValueType() == RHS.getValueType () && "Expected both operands to be the same type") ? void (0) : __assert_fail ("LHS.getValueType() == RHS.getValueType() && \"Expected both operands to be the same type\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 8178, __extension__ __PRETTY_FUNCTION__)); | ||||||||||
8179 | |||||||||||
8180 | // Get the upper and lower bits of the result. | ||||||||||
8181 | SDValue Lo, Hi; | ||||||||||
8182 | unsigned LoHiOp = Signed ? ISD::SMUL_LOHI : ISD::UMUL_LOHI; | ||||||||||
8183 | unsigned HiOp = Signed ? ISD::MULHS : ISD::MULHU; | ||||||||||
8184 | if (isOperationLegalOrCustom(LoHiOp, VT)) { | ||||||||||
8185 | SDValue Result = DAG.getNode(LoHiOp, dl, DAG.getVTList(VT, VT), LHS, RHS); | ||||||||||
8186 | Lo = Result.getValue(0); | ||||||||||
8187 | Hi = Result.getValue(1); | ||||||||||
8188 | } else if (isOperationLegalOrCustom(HiOp, VT)) { | ||||||||||
8189 | Lo = DAG.getNode(ISD::MUL, dl, VT, LHS, RHS); | ||||||||||
8190 | Hi = DAG.getNode(HiOp, dl, VT, LHS, RHS); | ||||||||||
8191 | } else if (VT.isVector()) { | ||||||||||
8192 | return SDValue(); | ||||||||||
8193 | } else { | ||||||||||
8194 | report_fatal_error("Unable to expand fixed point multiplication."); | ||||||||||
8195 | } | ||||||||||
8196 | |||||||||||
8197 | if (Scale == VTSize) | ||||||||||
8198 | // Result is just the top half since we'd be shifting by the width of the | ||||||||||
8199 | // operand. Overflow impossible so this works for both UMULFIX and | ||||||||||
8200 | // UMULFIXSAT. | ||||||||||
8201 | return Hi; | ||||||||||
8202 | |||||||||||
8203 | // The result will need to be shifted right by the scale since both operands | ||||||||||
8204 | // are scaled. The result is given to us in 2 halves, so we only want part of | ||||||||||
8205 | // both in the result. | ||||||||||
8206 | EVT ShiftTy = getShiftAmountTy(VT, DAG.getDataLayout()); | ||||||||||
8207 | SDValue Result = DAG.getNode(ISD::FSHR, dl, VT, Hi, Lo, | ||||||||||
8208 | DAG.getConstant(Scale, dl, ShiftTy)); | ||||||||||
8209 | if (!Saturating) | ||||||||||
8210 | return Result; | ||||||||||
8211 | |||||||||||
8212 | if (!Signed) { | ||||||||||
8213 | // Unsigned overflow happened if the upper (VTSize - Scale) bits (of the | ||||||||||
8214 | // widened multiplication) aren't all zeroes. | ||||||||||
8215 | |||||||||||
8216 | // Saturate to max if ((Hi >> Scale) != 0), | ||||||||||
8217 | // which is the same as if (Hi > ((1 << Scale) - 1)) | ||||||||||
8218 | APInt MaxVal = APInt::getMaxValue(VTSize); | ||||||||||
8219 | SDValue LowMask = DAG.getConstant(APInt::getLowBitsSet(VTSize, Scale), | ||||||||||
8220 | dl, VT); | ||||||||||
8221 | Result = DAG.getSelectCC(dl, Hi, LowMask, | ||||||||||
8222 | DAG.getConstant(MaxVal, dl, VT), Result, | ||||||||||
8223 | ISD::SETUGT); | ||||||||||
8224 | |||||||||||
8225 | return Result; | ||||||||||
8226 | } | ||||||||||
8227 | |||||||||||
8228 | // Signed overflow happened if the upper (VTSize - Scale + 1) bits (of the | ||||||||||
8229 | // widened multiplication) aren't all ones or all zeroes. | ||||||||||
8230 | |||||||||||
8231 | SDValue SatMin = DAG.getConstant(APInt::getSignedMinValue(VTSize), dl, VT); | ||||||||||
8232 | SDValue SatMax = DAG.getConstant(APInt::getSignedMaxValue(VTSize), dl, VT); | ||||||||||
8233 | |||||||||||
8234 | if (Scale == 0) { | ||||||||||
8235 | SDValue Sign = DAG.getNode(ISD::SRA, dl, VT, Lo, | ||||||||||
8236 | DAG.getConstant(VTSize - 1, dl, ShiftTy)); | ||||||||||
8237 | SDValue Overflow = DAG.getSetCC(dl, BoolVT, Hi, Sign, ISD::SETNE); | ||||||||||
8238 | // Saturated to SatMin if wide product is negative, and SatMax if wide | ||||||||||
8239 | // product is positive ... | ||||||||||
8240 | SDValue Zero = DAG.getConstant(0, dl, VT); | ||||||||||
8241 | SDValue ResultIfOverflow = DAG.getSelectCC(dl, Hi, Zero, SatMin, SatMax, | ||||||||||
8242 | ISD::SETLT); | ||||||||||
8243 | // ... but only if we overflowed. | ||||||||||
8244 | return DAG.getSelect(dl, VT, Overflow, ResultIfOverflow, Result); | ||||||||||
8245 | } | ||||||||||
8246 | |||||||||||
8247 | // We handled Scale==0 above so all the bits to examine is in Hi. | ||||||||||
8248 | |||||||||||
8249 | // Saturate to max if ((Hi >> (Scale - 1)) > 0), | ||||||||||
8250 | // which is the same as if (Hi > (1 << (Scale - 1)) - 1) | ||||||||||
8251 | SDValue LowMask = DAG.getConstant(APInt::getLowBitsSet(VTSize, Scale - 1), | ||||||||||
8252 | dl, VT); | ||||||||||
8253 | Result = DAG.getSelectCC(dl, Hi, LowMask, SatMax, Result, ISD::SETGT); | ||||||||||
8254 | // Saturate to min if (Hi >> (Scale - 1)) < -1), | ||||||||||
8255 | // which is the same as if (HI < (-1 << (Scale - 1)) | ||||||||||
8256 | SDValue HighMask = | ||||||||||
8257 | DAG.getConstant(APInt::getHighBitsSet(VTSize, VTSize - Scale + 1), | ||||||||||
8258 | dl, VT); | ||||||||||
8259 | Result = DAG.getSelectCC(dl, Hi, HighMask, SatMin, Result, ISD::SETLT); | ||||||||||
8260 | return Result; | ||||||||||
8261 | } | ||||||||||
8262 | |||||||||||
8263 | SDValue | ||||||||||
8264 | TargetLowering::expandFixedPointDiv(unsigned Opcode, const SDLoc &dl, | ||||||||||
8265 | SDValue LHS, SDValue RHS, | ||||||||||
8266 | unsigned Scale, SelectionDAG &DAG) const { | ||||||||||
8267 | assert((Opcode == ISD::SDIVFIX || Opcode == ISD::SDIVFIXSAT ||(static_cast <bool> ((Opcode == ISD::SDIVFIX || Opcode == ISD::SDIVFIXSAT || Opcode == ISD::UDIVFIX || Opcode == ISD:: UDIVFIXSAT) && "Expected a fixed point division opcode" ) ? void (0) : __assert_fail ("(Opcode == ISD::SDIVFIX || Opcode == ISD::SDIVFIXSAT || Opcode == ISD::UDIVFIX || Opcode == ISD::UDIVFIXSAT) && \"Expected a fixed point division opcode\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 8269, __extension__ __PRETTY_FUNCTION__)) | ||||||||||
8268 | Opcode == ISD::UDIVFIX || Opcode == ISD::UDIVFIXSAT) &&(static_cast <bool> ((Opcode == ISD::SDIVFIX || Opcode == ISD::SDIVFIXSAT || Opcode == ISD::UDIVFIX || Opcode == ISD:: UDIVFIXSAT) && "Expected a fixed point division opcode" ) ? void (0) : __assert_fail ("(Opcode == ISD::SDIVFIX || Opcode == ISD::SDIVFIXSAT || Opcode == ISD::UDIVFIX || Opcode == ISD::UDIVFIXSAT) && \"Expected a fixed point division opcode\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 8269, __extension__ __PRETTY_FUNCTION__)) | ||||||||||
8269 | "Expected a fixed point division opcode")(static_cast <bool> ((Opcode == ISD::SDIVFIX || Opcode == ISD::SDIVFIXSAT || Opcode == ISD::UDIVFIX || Opcode == ISD:: UDIVFIXSAT) && "Expected a fixed point division opcode" ) ? void (0) : __assert_fail ("(Opcode == ISD::SDIVFIX || Opcode == ISD::SDIVFIXSAT || Opcode == ISD::UDIVFIX || Opcode == ISD::UDIVFIXSAT) && \"Expected a fixed point division opcode\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 8269, __extension__ __PRETTY_FUNCTION__)); | ||||||||||
8270 | |||||||||||
8271 | EVT VT = LHS.getValueType(); | ||||||||||
8272 | bool Signed = Opcode == ISD::SDIVFIX || Opcode == ISD::SDIVFIXSAT; | ||||||||||
8273 | bool Saturating = Opcode == ISD::SDIVFIXSAT || Opcode == ISD::UDIVFIXSAT; | ||||||||||
8274 | EVT BoolVT = getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT); | ||||||||||
8275 | |||||||||||
8276 | // If there is enough room in the type to upscale the LHS or downscale the | ||||||||||
8277 | // RHS before the division, we can perform it in this type without having to | ||||||||||
8278 | // resize. For signed operations, the LHS headroom is the number of | ||||||||||
8279 | // redundant sign bits, and for unsigned ones it is the number of zeroes. | ||||||||||
8280 | // The headroom for the RHS is the number of trailing zeroes. | ||||||||||
8281 | unsigned LHSLead = Signed ? DAG.ComputeNumSignBits(LHS) - 1 | ||||||||||
8282 | : DAG.computeKnownBits(LHS).countMinLeadingZeros(); | ||||||||||
8283 | unsigned RHSTrail = DAG.computeKnownBits(RHS).countMinTrailingZeros(); | ||||||||||
8284 | |||||||||||
8285 | // For signed saturating operations, we need to be able to detect true integer | ||||||||||
8286 | // division overflow; that is, when you have MIN / -EPS. However, this | ||||||||||
8287 | // is undefined behavior and if we emit divisions that could take such | ||||||||||
8288 | // values it may cause undesired behavior (arithmetic exceptions on x86, for | ||||||||||
8289 | // example). | ||||||||||
8290 | // Avoid this by requiring an extra bit so that we never get this case. | ||||||||||
8291 | // FIXME: This is a bit unfortunate as it means that for an 8-bit 7-scale | ||||||||||
8292 | // signed saturating division, we need to emit a whopping 32-bit division. | ||||||||||
8293 | if (LHSLead + RHSTrail < Scale + (unsigned)(Saturating && Signed)) | ||||||||||
8294 | return SDValue(); | ||||||||||
8295 | |||||||||||
8296 | unsigned LHSShift = std::min(LHSLead, Scale); | ||||||||||
8297 | unsigned RHSShift = Scale - LHSShift; | ||||||||||
8298 | |||||||||||
8299 | // At this point, we know that if we shift the LHS up by LHSShift and the | ||||||||||
8300 | // RHS down by RHSShift, we can emit a regular division with a final scaling | ||||||||||
8301 | // factor of Scale. | ||||||||||
8302 | |||||||||||
8303 | EVT ShiftTy = getShiftAmountTy(VT, DAG.getDataLayout()); | ||||||||||
8304 | if (LHSShift) | ||||||||||
8305 | LHS = DAG.getNode(ISD::SHL, dl, VT, LHS, | ||||||||||
8306 | DAG.getConstant(LHSShift, dl, ShiftTy)); | ||||||||||
8307 | if (RHSShift) | ||||||||||
8308 | RHS = DAG.getNode(Signed ? ISD::SRA : ISD::SRL, dl, VT, RHS, | ||||||||||
8309 | DAG.getConstant(RHSShift, dl, ShiftTy)); | ||||||||||
8310 | |||||||||||
8311 | SDValue Quot; | ||||||||||
8312 | if (Signed) { | ||||||||||
8313 | // For signed operations, if the resulting quotient is negative and the | ||||||||||
8314 | // remainder is nonzero, subtract 1 from the quotient to round towards | ||||||||||
8315 | // negative infinity. | ||||||||||
8316 | SDValue Rem; | ||||||||||
8317 | // FIXME: Ideally we would always produce an SDIVREM here, but if the | ||||||||||
8318 | // type isn't legal, SDIVREM cannot be expanded. There is no reason why | ||||||||||
8319 | // we couldn't just form a libcall, but the type legalizer doesn't do it. | ||||||||||
8320 | if (isTypeLegal(VT) && | ||||||||||
8321 | isOperationLegalOrCustom(ISD::SDIVREM, VT)) { | ||||||||||
8322 | Quot = DAG.getNode(ISD::SDIVREM, dl, | ||||||||||
8323 | DAG.getVTList(VT, VT), | ||||||||||
8324 | LHS, RHS); | ||||||||||
8325 | Rem = Quot.getValue(1); | ||||||||||
8326 | Quot = Quot.getValue(0); | ||||||||||
8327 | } else { | ||||||||||
8328 | Quot = DAG.getNode(ISD::SDIV, dl, VT, | ||||||||||
8329 | LHS, RHS); | ||||||||||
8330 | Rem = DAG.getNode(ISD::SREM, dl, VT, | ||||||||||
8331 | LHS, RHS); | ||||||||||
8332 | } | ||||||||||
8333 | SDValue Zero = DAG.getConstant(0, dl, VT); | ||||||||||
8334 | SDValue RemNonZero = DAG.getSetCC(dl, BoolVT, Rem, Zero, ISD::SETNE); | ||||||||||
8335 | SDValue LHSNeg = DAG.getSetCC(dl, BoolVT, LHS, Zero, ISD::SETLT); | ||||||||||
8336 | SDValue RHSNeg = DAG.getSetCC(dl, BoolVT, RHS, Zero, ISD::SETLT); | ||||||||||
8337 | SDValue QuotNeg = DAG.getNode(ISD::XOR, dl, BoolVT, LHSNeg, RHSNeg); | ||||||||||
8338 | SDValue Sub1 = DAG.getNode(ISD::SUB, dl, VT, Quot, | ||||||||||
8339 | DAG.getConstant(1, dl, VT)); | ||||||||||
8340 | Quot = DAG.getSelect(dl, VT, | ||||||||||
8341 | DAG.getNode(ISD::AND, dl, BoolVT, RemNonZero, QuotNeg), | ||||||||||
8342 | Sub1, Quot); | ||||||||||
8343 | } else | ||||||||||
8344 | Quot = DAG.getNode(ISD::UDIV, dl, VT, | ||||||||||
8345 | LHS, RHS); | ||||||||||
8346 | |||||||||||
8347 | return Quot; | ||||||||||
8348 | } | ||||||||||
8349 | |||||||||||
8350 | void TargetLowering::expandUADDSUBO( | ||||||||||
8351 | SDNode *Node, SDValue &Result, SDValue &Overflow, SelectionDAG &DAG) const { | ||||||||||
8352 | SDLoc dl(Node); | ||||||||||
8353 | SDValue LHS = Node->getOperand(0); | ||||||||||
8354 | SDValue RHS = Node->getOperand(1); | ||||||||||
8355 | bool IsAdd = Node->getOpcode() == ISD::UADDO; | ||||||||||
8356 | |||||||||||
8357 | // If ADD/SUBCARRY is legal, use that instead. | ||||||||||
8358 | unsigned OpcCarry = IsAdd ? ISD::ADDCARRY : ISD::SUBCARRY; | ||||||||||
8359 | if (isOperationLegalOrCustom(OpcCarry, Node->getValueType(0))) { | ||||||||||
8360 | SDValue CarryIn = DAG.getConstant(0, dl, Node->getValueType(1)); | ||||||||||
8361 | SDValue NodeCarry = DAG.getNode(OpcCarry, dl, Node->getVTList(), | ||||||||||
8362 | { LHS, RHS, CarryIn }); | ||||||||||
8363 | Result = SDValue(NodeCarry.getNode(), 0); | ||||||||||
8364 | Overflow = SDValue(NodeCarry.getNode(), 1); | ||||||||||
8365 | return; | ||||||||||
8366 | } | ||||||||||
8367 | |||||||||||
8368 | Result = DAG.getNode(IsAdd ? ISD::ADD : ISD::SUB, dl, | ||||||||||
8369 | LHS.getValueType(), LHS, RHS); | ||||||||||
8370 | |||||||||||
8371 | EVT ResultType = Node->getValueType(1); | ||||||||||
8372 | EVT SetCCType = getSetCCResultType( | ||||||||||
8373 | DAG.getDataLayout(), *DAG.getContext(), Node->getValueType(0)); | ||||||||||
8374 | ISD::CondCode CC = IsAdd ? ISD::SETULT : ISD::SETUGT; | ||||||||||
8375 | SDValue SetCC = DAG.getSetCC(dl, SetCCType, Result, LHS, CC); | ||||||||||
8376 | Overflow = DAG.getBoolExtOrTrunc(SetCC, dl, ResultType, ResultType); | ||||||||||
8377 | } | ||||||||||
8378 | |||||||||||
8379 | void TargetLowering::expandSADDSUBO( | ||||||||||
8380 | SDNode *Node, SDValue &Result, SDValue &Overflow, SelectionDAG &DAG) const { | ||||||||||
8381 | SDLoc dl(Node); | ||||||||||
8382 | SDValue LHS = Node->getOperand(0); | ||||||||||
8383 | SDValue RHS = Node->getOperand(1); | ||||||||||
8384 | bool IsAdd = Node->getOpcode() == ISD::SADDO; | ||||||||||
8385 | |||||||||||
8386 | Result = DAG.getNode(IsAdd ? ISD::ADD : ISD::SUB, dl, | ||||||||||
8387 | LHS.getValueType(), LHS, RHS); | ||||||||||
8388 | |||||||||||
8389 | EVT ResultType = Node->getValueType(1); | ||||||||||
8390 | EVT OType = getSetCCResultType( | ||||||||||
8391 | DAG.getDataLayout(), *DAG.getContext(), Node->getValueType(0)); | ||||||||||
8392 | |||||||||||
8393 | // If SADDSAT/SSUBSAT is legal, compare results to detect overflow. | ||||||||||
8394 | unsigned OpcSat = IsAdd ? ISD::SADDSAT : ISD::SSUBSAT; | ||||||||||
8395 | if (isOperationLegal(OpcSat, LHS.getValueType())) { | ||||||||||
8396 | SDValue Sat = DAG.getNode(OpcSat, dl, LHS.getValueType(), LHS, RHS); | ||||||||||
8397 | SDValue SetCC = DAG.getSetCC(dl, OType, Result, Sat, ISD::SETNE); | ||||||||||
8398 | Overflow = DAG.getBoolExtOrTrunc(SetCC, dl, ResultType, ResultType); | ||||||||||
8399 | return; | ||||||||||
8400 | } | ||||||||||
8401 | |||||||||||
8402 | SDValue Zero = DAG.getConstant(0, dl, LHS.getValueType()); | ||||||||||
8403 | |||||||||||
8404 | // For an addition, the result should be less than one of the operands (LHS) | ||||||||||
8405 | // if and only if the other operand (RHS) is negative, otherwise there will | ||||||||||
8406 | // be overflow. | ||||||||||
8407 | // For a subtraction, the result should be less than one of the operands | ||||||||||
8408 | // (LHS) if and only if the other operand (RHS) is (non-zero) positive, | ||||||||||
8409 | // otherwise there will be overflow. | ||||||||||
8410 | SDValue ResultLowerThanLHS = DAG.getSetCC(dl, OType, Result, LHS, ISD::SETLT); | ||||||||||
8411 | SDValue ConditionRHS = | ||||||||||
8412 | DAG.getSetCC(dl, OType, RHS, Zero, IsAdd ? ISD::SETLT : ISD::SETGT); | ||||||||||
8413 | |||||||||||
8414 | Overflow = DAG.getBoolExtOrTrunc( | ||||||||||
8415 | DAG.getNode(ISD::XOR, dl, OType, ConditionRHS, ResultLowerThanLHS), dl, | ||||||||||
8416 | ResultType, ResultType); | ||||||||||
8417 | } | ||||||||||
8418 | |||||||||||
8419 | bool TargetLowering::expandMULO(SDNode *Node, SDValue &Result, | ||||||||||
8420 | SDValue &Overflow, SelectionDAG &DAG) const { | ||||||||||
8421 | SDLoc dl(Node); | ||||||||||
8422 | EVT VT = Node->getValueType(0); | ||||||||||
8423 | EVT SetCCVT = getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT); | ||||||||||
8424 | SDValue LHS = Node->getOperand(0); | ||||||||||
8425 | SDValue RHS = Node->getOperand(1); | ||||||||||
8426 | bool isSigned = Node->getOpcode() == ISD::SMULO; | ||||||||||
8427 | |||||||||||
8428 | // For power-of-two multiplications we can use a simpler shift expansion. | ||||||||||
8429 | if (ConstantSDNode *RHSC = isConstOrConstSplat(RHS)) { | ||||||||||
8430 | const APInt &C = RHSC->getAPIntValue(); | ||||||||||
8431 | // mulo(X, 1 << S) -> { X << S, (X << S) >> S != X } | ||||||||||
8432 | if (C.isPowerOf2()) { | ||||||||||
8433 | // smulo(x, signed_min) is same as umulo(x, signed_min). | ||||||||||
8434 | bool UseArithShift = isSigned && !C.isMinSignedValue(); | ||||||||||
8435 | EVT ShiftAmtTy = getShiftAmountTy(VT, DAG.getDataLayout()); | ||||||||||
8436 | SDValue ShiftAmt = DAG.getConstant(C.logBase2(), dl, ShiftAmtTy); | ||||||||||
8437 | Result = DAG.getNode(ISD::SHL, dl, VT, LHS, ShiftAmt); | ||||||||||
8438 | Overflow = DAG.getSetCC(dl, SetCCVT, | ||||||||||
8439 | DAG.getNode(UseArithShift ? ISD::SRA : ISD::SRL, | ||||||||||
8440 | dl, VT, Result, ShiftAmt), | ||||||||||
8441 | LHS, ISD::SETNE); | ||||||||||
8442 | return true; | ||||||||||
8443 | } | ||||||||||
8444 | } | ||||||||||
8445 | |||||||||||
8446 | EVT WideVT = EVT::getIntegerVT(*DAG.getContext(), VT.getScalarSizeInBits() * 2); | ||||||||||
8447 | if (VT.isVector()) | ||||||||||
8448 | WideVT = EVT::getVectorVT(*DAG.getContext(), WideVT, | ||||||||||
8449 | VT.getVectorNumElements()); | ||||||||||
8450 | |||||||||||
8451 | SDValue BottomHalf; | ||||||||||
8452 | SDValue TopHalf; | ||||||||||
8453 | static const unsigned Ops[2][3] = | ||||||||||
8454 | { { ISD::MULHU, ISD::UMUL_LOHI, ISD::ZERO_EXTEND }, | ||||||||||
8455 | { ISD::MULHS, ISD::SMUL_LOHI, ISD::SIGN_EXTEND }}; | ||||||||||
8456 | if (isOperationLegalOrCustom(Ops[isSigned][0], VT)) { | ||||||||||
8457 | BottomHalf = DAG.getNode(ISD::MUL, dl, VT, LHS, RHS); | ||||||||||
8458 | TopHalf = DAG.getNode(Ops[isSigned][0], dl, VT, LHS, RHS); | ||||||||||
8459 | } else if (isOperationLegalOrCustom(Ops[isSigned][1], VT)) { | ||||||||||
8460 | BottomHalf = DAG.getNode(Ops[isSigned][1], dl, DAG.getVTList(VT, VT), LHS, | ||||||||||
8461 | RHS); | ||||||||||
8462 | TopHalf = BottomHalf.getValue(1); | ||||||||||
8463 | } else if (isTypeLegal(WideVT)) { | ||||||||||
8464 | LHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, LHS); | ||||||||||
8465 | RHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, RHS); | ||||||||||
8466 | SDValue Mul = DAG.getNode(ISD::MUL, dl, WideVT, LHS, RHS); | ||||||||||
8467 | BottomHalf = DAG.getNode(ISD::TRUNCATE, dl, VT, Mul); | ||||||||||
8468 | SDValue ShiftAmt = DAG.getConstant(VT.getScalarSizeInBits(), dl, | ||||||||||
8469 | getShiftAmountTy(WideVT, DAG.getDataLayout())); | ||||||||||
8470 | TopHalf = DAG.getNode(ISD::TRUNCATE, dl, VT, | ||||||||||
8471 | DAG.getNode(ISD::SRL, dl, WideVT, Mul, ShiftAmt)); | ||||||||||
8472 | } else { | ||||||||||
8473 | if (VT.isVector()) | ||||||||||
8474 | return false; | ||||||||||
8475 | |||||||||||
8476 | // We can fall back to a libcall with an illegal type for the MUL if we | ||||||||||
8477 | // have a libcall big enough. | ||||||||||
8478 | // Also, we can fall back to a division in some cases, but that's a big | ||||||||||
8479 | // performance hit in the general case. | ||||||||||
8480 | RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; | ||||||||||
8481 | if (WideVT == MVT::i16) | ||||||||||
8482 | LC = RTLIB::MUL_I16; | ||||||||||
8483 | else if (WideVT == MVT::i32) | ||||||||||
8484 | LC = RTLIB::MUL_I32; | ||||||||||
8485 | else if (WideVT == MVT::i64) | ||||||||||
8486 | LC = RTLIB::MUL_I64; | ||||||||||
8487 | else if (WideVT == MVT::i128) | ||||||||||
8488 | LC = RTLIB::MUL_I128; | ||||||||||
8489 | assert(LC != RTLIB::UNKNOWN_LIBCALL && "Cannot expand this operation!")(static_cast <bool> (LC != RTLIB::UNKNOWN_LIBCALL && "Cannot expand this operation!") ? void (0) : __assert_fail ( "LC != RTLIB::UNKNOWN_LIBCALL && \"Cannot expand this operation!\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 8489, __extension__ __PRETTY_FUNCTION__)); | ||||||||||
8490 | |||||||||||
8491 | SDValue HiLHS; | ||||||||||
8492 | SDValue HiRHS; | ||||||||||
8493 | if (isSigned) { | ||||||||||
8494 | // The high part is obtained by SRA'ing all but one of the bits of low | ||||||||||
8495 | // part. | ||||||||||
8496 | unsigned LoSize = VT.getFixedSizeInBits(); | ||||||||||
8497 | HiLHS = | ||||||||||
8498 | DAG.getNode(ISD::SRA, dl, VT, LHS, | ||||||||||
8499 | DAG.getConstant(LoSize - 1, dl, | ||||||||||
8500 | getPointerTy(DAG.getDataLayout()))); | ||||||||||
8501 | HiRHS = | ||||||||||
8502 | DAG.getNode(ISD::SRA, dl, VT, RHS, | ||||||||||
8503 | DAG.getConstant(LoSize - 1, dl, | ||||||||||
8504 | getPointerTy(DAG.getDataLayout()))); | ||||||||||
8505 | } else { | ||||||||||
8506 | HiLHS = DAG.getConstant(0, dl, VT); | ||||||||||
8507 | HiRHS = DAG.getConstant(0, dl, VT); | ||||||||||
8508 | } | ||||||||||
8509 | |||||||||||
8510 | // Here we're passing the 2 arguments explicitly as 4 arguments that are | ||||||||||
8511 | // pre-lowered to the correct types. This all depends upon WideVT not | ||||||||||
8512 | // being a legal type for the architecture and thus has to be split to | ||||||||||
8513 | // two arguments. | ||||||||||
8514 | SDValue Ret; | ||||||||||
8515 | TargetLowering::MakeLibCallOptions CallOptions; | ||||||||||
8516 | CallOptions.setSExt(isSigned); | ||||||||||
8517 | CallOptions.setIsPostTypeLegalization(true); | ||||||||||
8518 | if (shouldSplitFunctionArgumentsAsLittleEndian(DAG.getDataLayout())) { | ||||||||||
8519 | // Halves of WideVT are packed into registers in different order | ||||||||||
8520 | // depending on platform endianness. This is usually handled by | ||||||||||
8521 | // the C calling convention, but we can't defer to it in | ||||||||||
8522 | // the legalizer. | ||||||||||
8523 | SDValue Args[] = { LHS, HiLHS, RHS, HiRHS }; | ||||||||||
8524 | Ret = makeLibCall(DAG, LC, WideVT, Args, CallOptions, dl).first; | ||||||||||
8525 | } else { | ||||||||||
8526 | SDValue Args[] = { HiLHS, LHS, HiRHS, RHS }; | ||||||||||
8527 | Ret = makeLibCall(DAG, LC, WideVT, Args, CallOptions, dl).first; | ||||||||||
8528 | } | ||||||||||
8529 | assert(Ret.getOpcode() == ISD::MERGE_VALUES &&(static_cast <bool> (Ret.getOpcode() == ISD::MERGE_VALUES && "Ret value is a collection of constituent nodes holding result." ) ? void (0) : __assert_fail ("Ret.getOpcode() == ISD::MERGE_VALUES && \"Ret value is a collection of constituent nodes holding result.\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 8530, __extension__ __PRETTY_FUNCTION__)) | ||||||||||
8530 | "Ret value is a collection of constituent nodes holding result.")(static_cast <bool> (Ret.getOpcode() == ISD::MERGE_VALUES && "Ret value is a collection of constituent nodes holding result." ) ? void (0) : __assert_fail ("Ret.getOpcode() == ISD::MERGE_VALUES && \"Ret value is a collection of constituent nodes holding result.\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 8530, __extension__ __PRETTY_FUNCTION__)); | ||||||||||
8531 | if (DAG.getDataLayout().isLittleEndian()) { | ||||||||||
8532 | // Same as above. | ||||||||||
8533 | BottomHalf = Ret.getOperand(0); | ||||||||||
8534 | TopHalf = Ret.getOperand(1); | ||||||||||
8535 | } else { | ||||||||||
8536 | BottomHalf = Ret.getOperand(1); | ||||||||||
8537 | TopHalf = Ret.getOperand(0); | ||||||||||
8538 | } | ||||||||||
8539 | } | ||||||||||
8540 | |||||||||||
8541 | Result = BottomHalf; | ||||||||||
8542 | if (isSigned) { | ||||||||||
8543 | SDValue ShiftAmt = DAG.getConstant( | ||||||||||
8544 | VT.getScalarSizeInBits() - 1, dl, | ||||||||||
8545 | getShiftAmountTy(BottomHalf.getValueType(), DAG.getDataLayout())); | ||||||||||
8546 | SDValue Sign = DAG.getNode(ISD::SRA, dl, VT, BottomHalf, ShiftAmt); | ||||||||||
8547 | Overflow = DAG.getSetCC(dl, SetCCVT, TopHalf, Sign, ISD::SETNE); | ||||||||||
8548 | } else { | ||||||||||
8549 | Overflow = DAG.getSetCC(dl, SetCCVT, TopHalf, | ||||||||||
8550 | DAG.getConstant(0, dl, VT), ISD::SETNE); | ||||||||||
8551 | } | ||||||||||
8552 | |||||||||||
8553 | // Truncate the result if SetCC returns a larger type than needed. | ||||||||||
8554 | EVT RType = Node->getValueType(1); | ||||||||||
8555 | if (RType.bitsLT(Overflow.getValueType())) | ||||||||||
8556 | Overflow = DAG.getNode(ISD::TRUNCATE, dl, RType, Overflow); | ||||||||||
8557 | |||||||||||
8558 | assert(RType.getSizeInBits() == Overflow.getValueSizeInBits() &&(static_cast <bool> (RType.getSizeInBits() == Overflow. getValueSizeInBits() && "Unexpected result type for S/UMULO legalization" ) ? void (0) : __assert_fail ("RType.getSizeInBits() == Overflow.getValueSizeInBits() && \"Unexpected result type for S/UMULO legalization\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 8559, __extension__ __PRETTY_FUNCTION__)) | ||||||||||
8559 | "Unexpected result type for S/UMULO legalization")(static_cast <bool> (RType.getSizeInBits() == Overflow. getValueSizeInBits() && "Unexpected result type for S/UMULO legalization" ) ? void (0) : __assert_fail ("RType.getSizeInBits() == Overflow.getValueSizeInBits() && \"Unexpected result type for S/UMULO legalization\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 8559, __extension__ __PRETTY_FUNCTION__)); | ||||||||||
8560 | return true; | ||||||||||
8561 | } | ||||||||||
8562 | |||||||||||
8563 | SDValue TargetLowering::expandVecReduce(SDNode *Node, SelectionDAG &DAG) const { | ||||||||||
8564 | SDLoc dl(Node); | ||||||||||
8565 | unsigned BaseOpcode = ISD::getVecReduceBaseOpcode(Node->getOpcode()); | ||||||||||
8566 | SDValue Op = Node->getOperand(0); | ||||||||||
8567 | EVT VT = Op.getValueType(); | ||||||||||
8568 | |||||||||||
8569 | if (VT.isScalableVector()) | ||||||||||
8570 | report_fatal_error( | ||||||||||
8571 | "Expanding reductions for scalable vectors is undefined."); | ||||||||||
8572 | |||||||||||
8573 | // Try to use a shuffle reduction for power of two vectors. | ||||||||||
8574 | if (VT.isPow2VectorType()) { | ||||||||||
8575 | while (VT.getVectorNumElements() > 1) { | ||||||||||
8576 | EVT HalfVT = VT.getHalfNumVectorElementsVT(*DAG.getContext()); | ||||||||||
8577 | if (!isOperationLegalOrCustom(BaseOpcode, HalfVT)) | ||||||||||
8578 | break; | ||||||||||
8579 | |||||||||||
8580 | SDValue Lo, Hi; | ||||||||||
8581 | std::tie(Lo, Hi) = DAG.SplitVector(Op, dl); | ||||||||||
8582 | Op = DAG.getNode(BaseOpcode, dl, HalfVT, Lo, Hi); | ||||||||||
8583 | VT = HalfVT; | ||||||||||
8584 | } | ||||||||||
8585 | } | ||||||||||
8586 | |||||||||||
8587 | EVT EltVT = VT.getVectorElementType(); | ||||||||||
8588 | unsigned NumElts = VT.getVectorNumElements(); | ||||||||||
8589 | |||||||||||
8590 | SmallVector<SDValue, 8> Ops; | ||||||||||
8591 | DAG.ExtractVectorElements(Op, Ops, 0, NumElts); | ||||||||||
8592 | |||||||||||
8593 | SDValue Res = Ops[0]; | ||||||||||
8594 | for (unsigned i = 1; i < NumElts; i++) | ||||||||||
8595 | Res = DAG.getNode(BaseOpcode, dl, EltVT, Res, Ops[i], Node->getFlags()); | ||||||||||
8596 | |||||||||||
8597 | // Result type may be wider than element type. | ||||||||||
8598 | if (EltVT != Node->getValueType(0)) | ||||||||||
8599 | Res = DAG.getNode(ISD::ANY_EXTEND, dl, Node->getValueType(0), Res); | ||||||||||
8600 | return Res; | ||||||||||
8601 | } | ||||||||||
8602 | |||||||||||
8603 | SDValue TargetLowering::expandVecReduceSeq(SDNode *Node, SelectionDAG &DAG) const { | ||||||||||
8604 | SDLoc dl(Node); | ||||||||||
8605 | SDValue AccOp = Node->getOperand(0); | ||||||||||
8606 | SDValue VecOp = Node->getOperand(1); | ||||||||||
8607 | SDNodeFlags Flags = Node->getFlags(); | ||||||||||
8608 | |||||||||||
8609 | EVT VT = VecOp.getValueType(); | ||||||||||
8610 | EVT EltVT = VT.getVectorElementType(); | ||||||||||
8611 | |||||||||||
8612 | if (VT.isScalableVector()) | ||||||||||
8613 | report_fatal_error( | ||||||||||
8614 | "Expanding reductions for scalable vectors is undefined."); | ||||||||||
8615 | |||||||||||
8616 | unsigned NumElts = VT.getVectorNumElements(); | ||||||||||
8617 | |||||||||||
8618 | SmallVector<SDValue, 8> Ops; | ||||||||||
8619 | DAG.ExtractVectorElements(VecOp, Ops, 0, NumElts); | ||||||||||
8620 | |||||||||||
8621 | unsigned BaseOpcode = ISD::getVecReduceBaseOpcode(Node->getOpcode()); | ||||||||||
8622 | |||||||||||
8623 | SDValue Res = AccOp; | ||||||||||
8624 | for (unsigned i = 0; i < NumElts; i++) | ||||||||||
8625 | Res = DAG.getNode(BaseOpcode, dl, EltVT, Res, Ops[i], Flags); | ||||||||||
8626 | |||||||||||
8627 | return Res; | ||||||||||
8628 | } | ||||||||||
8629 | |||||||||||
8630 | bool TargetLowering::expandREM(SDNode *Node, SDValue &Result, | ||||||||||
8631 | SelectionDAG &DAG) const { | ||||||||||
8632 | EVT VT = Node->getValueType(0); | ||||||||||
8633 | SDLoc dl(Node); | ||||||||||
8634 | bool isSigned = Node->getOpcode() == ISD::SREM; | ||||||||||
8635 | unsigned DivOpc = isSigned ? ISD::SDIV : ISD::UDIV; | ||||||||||
8636 | unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM; | ||||||||||
8637 | SDValue Dividend = Node->getOperand(0); | ||||||||||
8638 | SDValue Divisor = Node->getOperand(1); | ||||||||||
8639 | if (isOperationLegalOrCustom(DivRemOpc, VT)) { | ||||||||||
8640 | SDVTList VTs = DAG.getVTList(VT, VT); | ||||||||||
8641 | Result = DAG.getNode(DivRemOpc, dl, VTs, Dividend, Divisor).getValue(1); | ||||||||||
8642 | return true; | ||||||||||
8643 | } | ||||||||||
8644 | if (isOperationLegalOrCustom(DivOpc, VT)) { | ||||||||||
8645 | // X % Y -> X-X/Y*Y | ||||||||||
8646 | SDValue Divide = DAG.getNode(DivOpc, dl, VT, Dividend, Divisor); | ||||||||||
8647 | SDValue Mul = DAG.getNode(ISD::MUL, dl, VT, Divide, Divisor); | ||||||||||
8648 | Result = DAG.getNode(ISD::SUB, dl, VT, Dividend, Mul); | ||||||||||
8649 | return true; | ||||||||||
8650 | } | ||||||||||
8651 | return false; | ||||||||||
8652 | } | ||||||||||
8653 | |||||||||||
8654 | SDValue TargetLowering::expandFP_TO_INT_SAT(SDNode *Node, | ||||||||||
8655 | SelectionDAG &DAG) const { | ||||||||||
8656 | bool IsSigned = Node->getOpcode() == ISD::FP_TO_SINT_SAT; | ||||||||||
8657 | SDLoc dl(SDValue(Node, 0)); | ||||||||||
8658 | SDValue Src = Node->getOperand(0); | ||||||||||
8659 | |||||||||||
8660 | // DstVT is the result type, while SatVT is the size to which we saturate | ||||||||||
8661 | EVT SrcVT = Src.getValueType(); | ||||||||||
8662 | EVT DstVT = Node->getValueType(0); | ||||||||||
8663 | |||||||||||
8664 | EVT SatVT = cast<VTSDNode>(Node->getOperand(1))->getVT(); | ||||||||||
8665 | unsigned SatWidth = SatVT.getScalarSizeInBits(); | ||||||||||
8666 | unsigned DstWidth = DstVT.getScalarSizeInBits(); | ||||||||||
8667 | assert(SatWidth <= DstWidth &&(static_cast <bool> (SatWidth <= DstWidth && "Expected saturation width smaller than result width") ? void (0) : __assert_fail ("SatWidth <= DstWidth && \"Expected saturation width smaller than result width\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 8668, __extension__ __PRETTY_FUNCTION__)) | ||||||||||
8668 | "Expected saturation width smaller than result width")(static_cast <bool> (SatWidth <= DstWidth && "Expected saturation width smaller than result width") ? void (0) : __assert_fail ("SatWidth <= DstWidth && \"Expected saturation width smaller than result width\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 8668, __extension__ __PRETTY_FUNCTION__)); | ||||||||||
8669 | |||||||||||
8670 | // Determine minimum and maximum integer values and their corresponding | ||||||||||
8671 | // floating-point values. | ||||||||||
8672 | APInt MinInt, MaxInt; | ||||||||||
8673 | if (IsSigned) { | ||||||||||
8674 | MinInt = APInt::getSignedMinValue(SatWidth).sextOrSelf(DstWidth); | ||||||||||
8675 | MaxInt = APInt::getSignedMaxValue(SatWidth).sextOrSelf(DstWidth); | ||||||||||
8676 | } else { | ||||||||||
8677 | MinInt = APInt::getMinValue(SatWidth).zextOrSelf(DstWidth); | ||||||||||
8678 | MaxInt = APInt::getMaxValue(SatWidth).zextOrSelf(DstWidth); | ||||||||||
8679 | } | ||||||||||
8680 | |||||||||||
8681 | // We cannot risk emitting FP_TO_XINT nodes with a source VT of f16, as | ||||||||||
8682 | // libcall emission cannot handle this. Large result types will fail. | ||||||||||
8683 | if (SrcVT == MVT::f16) { | ||||||||||
8684 | Src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f32, Src); | ||||||||||
8685 | SrcVT = Src.getValueType(); | ||||||||||
8686 | } | ||||||||||
8687 | |||||||||||
8688 | APFloat MinFloat(DAG.EVTToAPFloatSemantics(SrcVT)); | ||||||||||
8689 | APFloat MaxFloat(DAG.EVTToAPFloatSemantics(SrcVT)); | ||||||||||
8690 | |||||||||||
8691 | APFloat::opStatus MinStatus = | ||||||||||
8692 | MinFloat.convertFromAPInt(MinInt, IsSigned, APFloat::rmTowardZero); | ||||||||||
8693 | APFloat::opStatus MaxStatus = | ||||||||||
8694 | MaxFloat.convertFromAPInt(MaxInt, IsSigned, APFloat::rmTowardZero); | ||||||||||
8695 | bool AreExactFloatBounds = !(MinStatus & APFloat::opStatus::opInexact) && | ||||||||||
8696 | !(MaxStatus & APFloat::opStatus::opInexact); | ||||||||||
8697 | |||||||||||
8698 | SDValue MinFloatNode = DAG.getConstantFP(MinFloat, dl, SrcVT); | ||||||||||
8699 | SDValue MaxFloatNode = DAG.getConstantFP(MaxFloat, dl, SrcVT); | ||||||||||
8700 | |||||||||||
8701 | // If the integer bounds are exactly representable as floats and min/max are | ||||||||||
8702 | // legal, emit a min+max+fptoi sequence. Otherwise we have to use a sequence | ||||||||||
8703 | // of comparisons and selects. | ||||||||||
8704 | bool MinMaxLegal = isOperationLegal(ISD::FMINNUM, SrcVT) && | ||||||||||
8705 | isOperationLegal(ISD::FMAXNUM, SrcVT); | ||||||||||
8706 | if (AreExactFloatBounds && MinMaxLegal) { | ||||||||||
8707 | SDValue Clamped = Src; | ||||||||||
8708 | |||||||||||
8709 | // Clamp Src by MinFloat from below. If Src is NaN the result is MinFloat. | ||||||||||
8710 | Clamped = DAG.getNode(ISD::FMAXNUM, dl, SrcVT, Clamped, MinFloatNode); | ||||||||||
8711 | // Clamp by MaxFloat from above. NaN cannot occur. | ||||||||||
8712 | Clamped = DAG.getNode(ISD::FMINNUM, dl, SrcVT, Clamped, MaxFloatNode); | ||||||||||
8713 | // Convert clamped value to integer. | ||||||||||
8714 | SDValue FpToInt = DAG.getNode(IsSigned ? ISD::FP_TO_SINT : ISD::FP_TO_UINT, | ||||||||||
8715 | dl, DstVT, Clamped); | ||||||||||
8716 | |||||||||||
8717 | // In the unsigned case we're done, because we mapped NaN to MinFloat, | ||||||||||
8718 | // which will cast to zero. | ||||||||||
8719 | if (!IsSigned) | ||||||||||
8720 | return FpToInt; | ||||||||||
8721 | |||||||||||
8722 | // Otherwise, select 0 if Src is NaN. | ||||||||||
8723 | SDValue ZeroInt = DAG.getConstant(0, dl, DstVT); | ||||||||||
8724 | return DAG.getSelectCC(dl, Src, Src, ZeroInt, FpToInt, | ||||||||||
8725 | ISD::CondCode::SETUO); | ||||||||||
8726 | } | ||||||||||
8727 | |||||||||||
8728 | SDValue MinIntNode = DAG.getConstant(MinInt, dl, DstVT); | ||||||||||
8729 | SDValue MaxIntNode = DAG.getConstant(MaxInt, dl, DstVT); | ||||||||||
8730 | |||||||||||
8731 | // Result of direct conversion. The assumption here is that the operation is | ||||||||||
8732 | // non-trapping and it's fine to apply it to an out-of-range value if we | ||||||||||
8733 | // select it away later. | ||||||||||
8734 | SDValue FpToInt = | ||||||||||
8735 | DAG.getNode(IsSigned ? ISD::FP_TO_SINT : ISD::FP_TO_UINT, dl, DstVT, Src); | ||||||||||
8736 | |||||||||||
8737 | SDValue Select = FpToInt; | ||||||||||
8738 | |||||||||||
8739 | // If Src ULT MinFloat, select MinInt. In particular, this also selects | ||||||||||
8740 | // MinInt if Src is NaN. | ||||||||||
8741 | Select = DAG.getSelectCC(dl, Src, MinFloatNode, MinIntNode, Select, | ||||||||||
8742 | ISD::CondCode::SETULT); | ||||||||||
8743 | // If Src OGT MaxFloat, select MaxInt. | ||||||||||
8744 | Select = DAG.getSelectCC(dl, Src, MaxFloatNode, MaxIntNode, Select, | ||||||||||
8745 | ISD::CondCode::SETOGT); | ||||||||||
8746 | |||||||||||
8747 | // In the unsigned case we are done, because we mapped NaN to MinInt, which | ||||||||||
8748 | // is already zero. | ||||||||||
8749 | if (!IsSigned) | ||||||||||
8750 | return Select; | ||||||||||
8751 | |||||||||||
8752 | // Otherwise, select 0 if Src is NaN. | ||||||||||
8753 | SDValue ZeroInt = DAG.getConstant(0, dl, DstVT); | ||||||||||
8754 | return DAG.getSelectCC(dl, Src, Src, ZeroInt, Select, ISD::CondCode::SETUO); | ||||||||||
8755 | } | ||||||||||
8756 | |||||||||||
8757 | SDValue TargetLowering::expandVectorSplice(SDNode *Node, | ||||||||||
8758 | SelectionDAG &DAG) const { | ||||||||||
8759 | assert(Node->getOpcode() == ISD::VECTOR_SPLICE && "Unexpected opcode!")(static_cast <bool> (Node->getOpcode() == ISD::VECTOR_SPLICE && "Unexpected opcode!") ? void (0) : __assert_fail ( "Node->getOpcode() == ISD::VECTOR_SPLICE && \"Unexpected opcode!\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 8759, __extension__ __PRETTY_FUNCTION__)); | ||||||||||
8760 | assert(Node->getValueType(0).isScalableVector() &&(static_cast <bool> (Node->getValueType(0).isScalableVector () && "Fixed length vector types expected to use SHUFFLE_VECTOR!" ) ? void (0) : __assert_fail ("Node->getValueType(0).isScalableVector() && \"Fixed length vector types expected to use SHUFFLE_VECTOR!\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 8761, __extension__ __PRETTY_FUNCTION__)) | ||||||||||
8761 | "Fixed length vector types expected to use SHUFFLE_VECTOR!")(static_cast <bool> (Node->getValueType(0).isScalableVector () && "Fixed length vector types expected to use SHUFFLE_VECTOR!" ) ? void (0) : __assert_fail ("Node->getValueType(0).isScalableVector() && \"Fixed length vector types expected to use SHUFFLE_VECTOR!\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 8761, __extension__ __PRETTY_FUNCTION__)); | ||||||||||
8762 | |||||||||||
8763 | EVT VT = Node->getValueType(0); | ||||||||||
8764 | SDValue V1 = Node->getOperand(0); | ||||||||||
8765 | SDValue V2 = Node->getOperand(1); | ||||||||||
8766 | int64_t Imm = cast<ConstantSDNode>(Node->getOperand(2))->getSExtValue(); | ||||||||||
8767 | SDLoc DL(Node); | ||||||||||
8768 | |||||||||||
8769 | // Expand through memory thusly: | ||||||||||
8770 | // Alloca CONCAT_VECTORS_TYPES(V1, V2) Ptr | ||||||||||
8771 | // Store V1, Ptr | ||||||||||
8772 | // Store V2, Ptr + sizeof(V1) | ||||||||||
8773 | // If (Imm < 0) | ||||||||||
8774 | // TrailingElts = -Imm | ||||||||||
8775 | // Ptr = Ptr + sizeof(V1) - (TrailingElts * sizeof(VT.Elt)) | ||||||||||
8776 | // else | ||||||||||
8777 | // Ptr = Ptr + (Imm * sizeof(VT.Elt)) | ||||||||||
8778 | // Res = Load Ptr | ||||||||||
8779 | |||||||||||
8780 | Align Alignment = DAG.getReducedAlign(VT, /*UseABI=*/false); | ||||||||||
8781 | |||||||||||
8782 | EVT MemVT = EVT::getVectorVT(*DAG.getContext(), VT.getVectorElementType(), | ||||||||||
8783 | VT.getVectorElementCount() * 2); | ||||||||||
8784 | SDValue StackPtr = DAG.CreateStackTemporary(MemVT.getStoreSize(), Alignment); | ||||||||||
8785 | EVT PtrVT = StackPtr.getValueType(); | ||||||||||
8786 | auto &MF = DAG.getMachineFunction(); | ||||||||||
8787 | auto FrameIndex = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex(); | ||||||||||
8788 | auto PtrInfo = MachinePointerInfo::getFixedStack(MF, FrameIndex); | ||||||||||
8789 | |||||||||||
8790 | // Store the lo part of CONCAT_VECTORS(V1, V2) | ||||||||||
8791 | SDValue StoreV1 = DAG.getStore(DAG.getEntryNode(), DL, V1, StackPtr, PtrInfo); | ||||||||||
8792 | // Store the hi part of CONCAT_VECTORS(V1, V2) | ||||||||||
8793 | SDValue OffsetToV2 = DAG.getVScale( | ||||||||||
8794 | DL, PtrVT, | ||||||||||
8795 | APInt(PtrVT.getFixedSizeInBits(), VT.getStoreSize().getKnownMinSize())); | ||||||||||
8796 | SDValue StackPtr2 = DAG.getNode(ISD::ADD, DL, PtrVT, StackPtr, OffsetToV2); | ||||||||||
8797 | SDValue StoreV2 = DAG.getStore(StoreV1, DL, V2, StackPtr2, PtrInfo); | ||||||||||
8798 | |||||||||||
8799 | if (Imm >= 0) { | ||||||||||
8800 | // Load back the required element. getVectorElementPointer takes care of | ||||||||||
8801 | // clamping the index if it's out-of-bounds. | ||||||||||
8802 | StackPtr = getVectorElementPointer(DAG, StackPtr, VT, Node->getOperand(2)); | ||||||||||
8803 | // Load the spliced result | ||||||||||
8804 | return DAG.getLoad(VT, DL, StoreV2, StackPtr, | ||||||||||
8805 | MachinePointerInfo::getUnknownStack(MF)); | ||||||||||
8806 | } | ||||||||||
8807 | |||||||||||
8808 | uint64_t TrailingElts = -Imm; | ||||||||||
8809 | |||||||||||
8810 | // NOTE: TrailingElts must be clamped so as not to read outside of V1:V2. | ||||||||||
8811 | TypeSize EltByteSize = VT.getVectorElementType().getStoreSize(); | ||||||||||
8812 | SDValue TrailingBytes = | ||||||||||
8813 | DAG.getConstant(TrailingElts * EltByteSize, DL, PtrVT); | ||||||||||
8814 | |||||||||||
8815 | if (TrailingElts > VT.getVectorMinNumElements()) { | ||||||||||
8816 | SDValue VLBytes = DAG.getVScale( | ||||||||||
8817 | DL, PtrVT, | ||||||||||
8818 | APInt(PtrVT.getFixedSizeInBits(), VT.getStoreSize().getKnownMinSize())); | ||||||||||
8819 | TrailingBytes = DAG.getNode(ISD::UMIN, DL, PtrVT, TrailingBytes, VLBytes); | ||||||||||
8820 | } | ||||||||||
8821 | |||||||||||
8822 | // Calculate the start address of the spliced result. | ||||||||||
8823 | StackPtr2 = DAG.getNode(ISD::SUB, DL, PtrVT, StackPtr2, TrailingBytes); | ||||||||||
8824 | |||||||||||
8825 | // Load the spliced result | ||||||||||
8826 | return DAG.getLoad(VT, DL, StoreV2, StackPtr2, | ||||||||||
8827 | MachinePointerInfo::getUnknownStack(MF)); | ||||||||||
8828 | } | ||||||||||
8829 | |||||||||||
8830 | bool TargetLowering::LegalizeSetCCCondCode(SelectionDAG &DAG, EVT VT, | ||||||||||
8831 | SDValue &LHS, SDValue &RHS, | ||||||||||
8832 | SDValue &CC, bool &NeedInvert, | ||||||||||
8833 | const SDLoc &dl, SDValue &Chain, | ||||||||||
8834 | bool IsSignaling) const { | ||||||||||
8835 | const TargetLowering &TLI = DAG.getTargetLoweringInfo(); | ||||||||||
8836 | MVT OpVT = LHS.getSimpleValueType(); | ||||||||||
8837 | ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get(); | ||||||||||
8838 | NeedInvert = false; | ||||||||||
8839 | switch (TLI.getCondCodeAction(CCCode, OpVT)) { | ||||||||||
8840 | default: | ||||||||||
8841 | llvm_unreachable("Unknown condition code action!")::llvm::llvm_unreachable_internal("Unknown condition code action!" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 8841); | ||||||||||
8842 | case TargetLowering::Legal: | ||||||||||
8843 | // Nothing to do. | ||||||||||
8844 | break; | ||||||||||
8845 | case TargetLowering::Expand: { | ||||||||||
8846 | ISD::CondCode InvCC = ISD::getSetCCSwappedOperands(CCCode); | ||||||||||
8847 | if (TLI.isCondCodeLegalOrCustom(InvCC, OpVT)) { | ||||||||||
8848 | std::swap(LHS, RHS); | ||||||||||
8849 | CC = DAG.getCondCode(InvCC); | ||||||||||
8850 | return true; | ||||||||||
8851 | } | ||||||||||
8852 | // Swapping operands didn't work. Try inverting the condition. | ||||||||||
8853 | bool NeedSwap = false; | ||||||||||
8854 | InvCC = getSetCCInverse(CCCode, OpVT); | ||||||||||
8855 | if (!TLI.isCondCodeLegalOrCustom(InvCC, OpVT)) { | ||||||||||
8856 | // If inverting the condition is not enough, try swapping operands | ||||||||||
8857 | // on top of it. | ||||||||||
8858 | InvCC = ISD::getSetCCSwappedOperands(InvCC); | ||||||||||
8859 | NeedSwap = true; | ||||||||||
8860 | } | ||||||||||
8861 | if (TLI.isCondCodeLegalOrCustom(InvCC, OpVT)) { | ||||||||||
8862 | CC = DAG.getCondCode(InvCC); | ||||||||||
8863 | NeedInvert = true; | ||||||||||
8864 | if (NeedSwap) | ||||||||||
8865 | std::swap(LHS, RHS); | ||||||||||
8866 | return true; | ||||||||||
8867 | } | ||||||||||
8868 | |||||||||||
8869 | ISD::CondCode CC1 = ISD::SETCC_INVALID, CC2 = ISD::SETCC_INVALID; | ||||||||||
8870 | unsigned Opc = 0; | ||||||||||
8871 | switch (CCCode) { | ||||||||||
8872 | default: | ||||||||||
8873 | llvm_unreachable("Don't know how to expand this condition!")::llvm::llvm_unreachable_internal("Don't know how to expand this condition!" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 8873); | ||||||||||
8874 | case ISD::SETUO: | ||||||||||
8875 | if (TLI.isCondCodeLegal(ISD::SETUNE, OpVT)) { | ||||||||||
8876 | CC1 = ISD::SETUNE; | ||||||||||
8877 | CC2 = ISD::SETUNE; | ||||||||||
8878 | Opc = ISD::OR; | ||||||||||
8879 | break; | ||||||||||
8880 | } | ||||||||||
8881 | assert(TLI.isCondCodeLegal(ISD::SETOEQ, OpVT) &&(static_cast <bool> (TLI.isCondCodeLegal(ISD::SETOEQ, OpVT ) && "If SETUE is expanded, SETOEQ or SETUNE must be legal!" ) ? void (0) : __assert_fail ("TLI.isCondCodeLegal(ISD::SETOEQ, OpVT) && \"If SETUE is expanded, SETOEQ or SETUNE must be legal!\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 8882, __extension__ __PRETTY_FUNCTION__)) | ||||||||||
8882 | "If SETUE is expanded, SETOEQ or SETUNE must be legal!")(static_cast <bool> (TLI.isCondCodeLegal(ISD::SETOEQ, OpVT ) && "If SETUE is expanded, SETOEQ or SETUNE must be legal!" ) ? void (0) : __assert_fail ("TLI.isCondCodeLegal(ISD::SETOEQ, OpVT) && \"If SETUE is expanded, SETOEQ or SETUNE must be legal!\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 8882, __extension__ __PRETTY_FUNCTION__)); | ||||||||||
8883 | NeedInvert = true; | ||||||||||
8884 | LLVM_FALLTHROUGH[[gnu::fallthrough]]; | ||||||||||
8885 | case ISD::SETO: | ||||||||||
8886 | assert(TLI.isCondCodeLegal(ISD::SETOEQ, OpVT) &&(static_cast <bool> (TLI.isCondCodeLegal(ISD::SETOEQ, OpVT ) && "If SETO is expanded, SETOEQ must be legal!") ? void (0) : __assert_fail ("TLI.isCondCodeLegal(ISD::SETOEQ, OpVT) && \"If SETO is expanded, SETOEQ must be legal!\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 8887, __extension__ __PRETTY_FUNCTION__)) | ||||||||||
8887 | "If SETO is expanded, SETOEQ must be legal!")(static_cast <bool> (TLI.isCondCodeLegal(ISD::SETOEQ, OpVT ) && "If SETO is expanded, SETOEQ must be legal!") ? void (0) : __assert_fail ("TLI.isCondCodeLegal(ISD::SETOEQ, OpVT) && \"If SETO is expanded, SETOEQ must be legal!\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 8887, __extension__ __PRETTY_FUNCTION__)); | ||||||||||
8888 | CC1 = ISD::SETOEQ; | ||||||||||
8889 | CC2 = ISD::SETOEQ; | ||||||||||
8890 | Opc = ISD::AND; | ||||||||||
8891 | break; | ||||||||||
8892 | case ISD::SETONE: | ||||||||||
8893 | case ISD::SETUEQ: | ||||||||||
8894 | // If the SETUO or SETO CC isn't legal, we might be able to use | ||||||||||
8895 | // SETOGT || SETOLT, inverting the result for SETUEQ. We only need one | ||||||||||
8896 | // of SETOGT/SETOLT to be legal, the other can be emulated by swapping | ||||||||||
8897 | // the operands. | ||||||||||
8898 | CC2 = ((unsigned)CCCode & 0x8U) ? ISD::SETUO : ISD::SETO; | ||||||||||
8899 | if (!TLI.isCondCodeLegal(CC2, OpVT) && | ||||||||||
8900 | (TLI.isCondCodeLegal(ISD::SETOGT, OpVT) || | ||||||||||
8901 | TLI.isCondCodeLegal(ISD::SETOLT, OpVT))) { | ||||||||||
8902 | CC1 = ISD::SETOGT; | ||||||||||
8903 | CC2 = ISD::SETOLT; | ||||||||||
8904 | Opc = ISD::OR; | ||||||||||
8905 | NeedInvert = ((unsigned)CCCode & 0x8U); | ||||||||||
8906 | break; | ||||||||||
8907 | } | ||||||||||
8908 | LLVM_FALLTHROUGH[[gnu::fallthrough]]; | ||||||||||
8909 | case ISD::SETOEQ: | ||||||||||
8910 | case ISD::SETOGT: | ||||||||||
8911 | case ISD::SETOGE: | ||||||||||
8912 | case ISD::SETOLT: | ||||||||||
8913 | case ISD::SETOLE: | ||||||||||
8914 | case ISD::SETUNE: | ||||||||||
8915 | case ISD::SETUGT: | ||||||||||
8916 | case ISD::SETUGE: | ||||||||||
8917 | case ISD::SETULT: | ||||||||||
8918 | case ISD::SETULE: | ||||||||||
8919 | // If we are floating point, assign and break, otherwise fall through. | ||||||||||
8920 | if (!OpVT.isInteger()) { | ||||||||||
8921 | // We can use the 4th bit to tell if we are the unordered | ||||||||||
8922 | // or ordered version of the opcode. | ||||||||||
8923 | CC2 = ((unsigned)CCCode & 0x8U) ? ISD::SETUO : ISD::SETO; | ||||||||||
8924 | Opc = ((unsigned)CCCode & 0x8U) ? ISD::OR : ISD::AND; | ||||||||||
8925 | CC1 = (ISD::CondCode)(((int)CCCode & 0x7) | 0x10); | ||||||||||
8926 | break; | ||||||||||
8927 | } | ||||||||||
8928 | // Fallthrough if we are unsigned integer. | ||||||||||
8929 | LLVM_FALLTHROUGH[[gnu::fallthrough]]; | ||||||||||
8930 | case ISD::SETLE: | ||||||||||
8931 | case ISD::SETGT: | ||||||||||
8932 | case ISD::SETGE: | ||||||||||
8933 | case ISD::SETLT: | ||||||||||
8934 | case ISD::SETNE: | ||||||||||
8935 | case ISD::SETEQ: | ||||||||||
8936 | // If all combinations of inverting the condition and swapping operands | ||||||||||
8937 | // didn't work then we have no means to expand the condition. | ||||||||||
8938 | llvm_unreachable("Don't know how to expand this condition!")::llvm::llvm_unreachable_internal("Don't know how to expand this condition!" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 8938); | ||||||||||
8939 | } | ||||||||||
8940 | |||||||||||
8941 | SDValue SetCC1, SetCC2; | ||||||||||
8942 | if (CCCode != ISD::SETO && CCCode != ISD::SETUO) { | ||||||||||
8943 | // If we aren't the ordered or unorder operation, | ||||||||||
8944 | // then the pattern is (LHS CC1 RHS) Opc (LHS CC2 RHS). | ||||||||||
8945 | SetCC1 = DAG.getSetCC(dl, VT, LHS, RHS, CC1, Chain, IsSignaling); | ||||||||||
8946 | SetCC2 = DAG.getSetCC(dl, VT, LHS, RHS, CC2, Chain, IsSignaling); | ||||||||||
8947 | } else { | ||||||||||
8948 | // Otherwise, the pattern is (LHS CC1 LHS) Opc (RHS CC2 RHS) | ||||||||||
8949 | SetCC1 = DAG.getSetCC(dl, VT, LHS, LHS, CC1, Chain, IsSignaling); | ||||||||||
8950 | SetCC2 = DAG.getSetCC(dl, VT, RHS, RHS, CC2, Chain, IsSignaling); | ||||||||||
8951 | } | ||||||||||
8952 | if (Chain) | ||||||||||
8953 | Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, SetCC1.getValue(1), | ||||||||||
8954 | SetCC2.getValue(1)); | ||||||||||
8955 | LHS = DAG.getNode(Opc, dl, VT, SetCC1, SetCC2); | ||||||||||
8956 | RHS = SDValue(); | ||||||||||
8957 | CC = SDValue(); | ||||||||||
8958 | return true; | ||||||||||
8959 | } | ||||||||||
8960 | } | ||||||||||
8961 | return false; | ||||||||||
8962 | } |
1 | //===- llvm/CodeGen/SelectionDAGNodes.h - SelectionDAG Nodes ----*- C++ -*-===// |
2 | // |
3 | // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. |
4 | // See https://llvm.org/LICENSE.txt for license information. |
5 | // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception |
6 | // |
7 | //===----------------------------------------------------------------------===// |
8 | // |
9 | // This file declares the SDNode class and derived classes, which are used to |
10 | // represent the nodes and operations present in a SelectionDAG. These nodes |
11 | // and operations are machine code level operations, with some similarities to |
12 | // the GCC RTL representation. |
13 | // |
14 | // Clients should include the SelectionDAG.h file instead of this file directly. |
15 | // |
16 | //===----------------------------------------------------------------------===// |
17 | |
18 | #ifndef LLVM_CODEGEN_SELECTIONDAGNODES_H |
19 | #define LLVM_CODEGEN_SELECTIONDAGNODES_H |
20 | |
21 | #include "llvm/ADT/APFloat.h" |
22 | #include "llvm/ADT/ArrayRef.h" |
23 | #include "llvm/ADT/BitVector.h" |
24 | #include "llvm/ADT/FoldingSet.h" |
25 | #include "llvm/ADT/GraphTraits.h" |
26 | #include "llvm/ADT/SmallPtrSet.h" |
27 | #include "llvm/ADT/SmallVector.h" |
28 | #include "llvm/ADT/ilist_node.h" |
29 | #include "llvm/ADT/iterator.h" |
30 | #include "llvm/ADT/iterator_range.h" |
31 | #include "llvm/CodeGen/ISDOpcodes.h" |
32 | #include "llvm/CodeGen/MachineMemOperand.h" |
33 | #include "llvm/CodeGen/Register.h" |
34 | #include "llvm/CodeGen/ValueTypes.h" |
35 | #include "llvm/IR/Constants.h" |
36 | #include "llvm/IR/DebugLoc.h" |
37 | #include "llvm/IR/Instruction.h" |
38 | #include "llvm/IR/Instructions.h" |
39 | #include "llvm/IR/Metadata.h" |
40 | #include "llvm/IR/Operator.h" |
41 | #include "llvm/Support/AlignOf.h" |
42 | #include "llvm/Support/AtomicOrdering.h" |
43 | #include "llvm/Support/Casting.h" |
44 | #include "llvm/Support/ErrorHandling.h" |
45 | #include "llvm/Support/MachineValueType.h" |
46 | #include "llvm/Support/TypeSize.h" |
47 | #include <algorithm> |
48 | #include <cassert> |
49 | #include <climits> |
50 | #include <cstddef> |
51 | #include <cstdint> |
52 | #include <cstring> |
53 | #include <iterator> |
54 | #include <string> |
55 | #include <tuple> |
56 | |
57 | namespace llvm { |
58 | |
59 | class APInt; |
60 | class Constant; |
61 | template <typename T> struct DenseMapInfo; |
62 | class GlobalValue; |
63 | class MachineBasicBlock; |
64 | class MachineConstantPoolValue; |
65 | class MCSymbol; |
66 | class raw_ostream; |
67 | class SDNode; |
68 | class SelectionDAG; |
69 | class Type; |
70 | class Value; |
71 | |
72 | void checkForCycles(const SDNode *N, const SelectionDAG *DAG = nullptr, |
73 | bool force = false); |
74 | |
75 | /// This represents a list of ValueType's that has been intern'd by |
76 | /// a SelectionDAG. Instances of this simple value class are returned by |
77 | /// SelectionDAG::getVTList(...). |
78 | /// |
79 | struct SDVTList { |
80 | const EVT *VTs; |
81 | unsigned int NumVTs; |
82 | }; |
83 | |
84 | namespace ISD { |
85 | |
86 | /// Node predicates |
87 | |
88 | /// If N is a BUILD_VECTOR or SPLAT_VECTOR node whose elements are all the |
89 | /// same constant or undefined, return true and return the constant value in |
90 | /// \p SplatValue. |
91 | bool isConstantSplatVector(const SDNode *N, APInt &SplatValue); |
92 | |
93 | /// Return true if the specified node is a BUILD_VECTOR or SPLAT_VECTOR where |
94 | /// all of the elements are ~0 or undef. If \p BuildVectorOnly is set to |
95 | /// true, it only checks BUILD_VECTOR. |
96 | bool isConstantSplatVectorAllOnes(const SDNode *N, |
97 | bool BuildVectorOnly = false); |
98 | |
99 | /// Return true if the specified node is a BUILD_VECTOR or SPLAT_VECTOR where |
100 | /// all of the elements are 0 or undef. If \p BuildVectorOnly is set to true, it |
101 | /// only checks BUILD_VECTOR. |
102 | bool isConstantSplatVectorAllZeros(const SDNode *N, |
103 | bool BuildVectorOnly = false); |
104 | |
105 | /// Return true if the specified node is a BUILD_VECTOR where all of the |
106 | /// elements are ~0 or undef. |
107 | bool isBuildVectorAllOnes(const SDNode *N); |
108 | |
109 | /// Return true if the specified node is a BUILD_VECTOR where all of the |
110 | /// elements are 0 or undef. |
111 | bool isBuildVectorAllZeros(const SDNode *N); |
112 | |
113 | /// Return true if the specified node is a BUILD_VECTOR node of all |
114 | /// ConstantSDNode or undef. |
115 | bool isBuildVectorOfConstantSDNodes(const SDNode *N); |
116 | |
117 | /// Return true if the specified node is a BUILD_VECTOR node of all |
118 | /// ConstantFPSDNode or undef. |
119 | bool isBuildVectorOfConstantFPSDNodes(const SDNode *N); |
120 | |
121 | /// Return true if the node has at least one operand and all operands of the |
122 | /// specified node are ISD::UNDEF. |
123 | bool allOperandsUndef(const SDNode *N); |
124 | |
125 | } // end namespace ISD |
126 | |
127 | //===----------------------------------------------------------------------===// |
128 | /// Unlike LLVM values, Selection DAG nodes may return multiple |
129 | /// values as the result of a computation. Many nodes return multiple values, |
130 | /// from loads (which define a token and a return value) to ADDC (which returns |
131 | /// a result and a carry value), to calls (which may return an arbitrary number |
132 | /// of values). |
133 | /// |
134 | /// As such, each use of a SelectionDAG computation must indicate the node that |
135 | /// computes it as well as which return value to use from that node. This pair |
136 | /// of information is represented with the SDValue value type. |
137 | /// |
138 | class SDValue { |
139 | friend struct DenseMapInfo<SDValue>; |
140 | |
141 | SDNode *Node = nullptr; // The node defining the value we are using. |
142 | unsigned ResNo = 0; // Which return value of the node we are using. |
143 | |
144 | public: |
145 | SDValue() = default; |
146 | SDValue(SDNode *node, unsigned resno); |
147 | |
148 | /// get the index which selects a specific result in the SDNode |
149 | unsigned getResNo() const { return ResNo; } |
150 | |
151 | /// get the SDNode which holds the desired result |
152 | SDNode *getNode() const { return Node; } |
153 | |
154 | /// set the SDNode |
155 | void setNode(SDNode *N) { Node = N; } |
156 | |
157 | inline SDNode *operator->() const { return Node; } |
158 | |
159 | bool operator==(const SDValue &O) const { |
160 | return Node == O.Node && ResNo == O.ResNo; |
161 | } |
162 | bool operator!=(const SDValue &O) const { |
163 | return !operator==(O); |
164 | } |
165 | bool operator<(const SDValue &O) const { |
166 | return std::tie(Node, ResNo) < std::tie(O.Node, O.ResNo); |
167 | } |
168 | explicit operator bool() const { |
169 | return Node != nullptr; |
170 | } |
171 | |
172 | SDValue getValue(unsigned R) const { |
173 | return SDValue(Node, R); |
174 | } |
175 | |
176 | /// Return true if this node is an operand of N. |
177 | bool isOperandOf(const SDNode *N) const; |
178 | |
179 | /// Return the ValueType of the referenced return value. |
180 | inline EVT getValueType() const; |
181 | |
182 | /// Return the simple ValueType of the referenced return value. |
183 | MVT getSimpleValueType() const { |
184 | return getValueType().getSimpleVT(); |
185 | } |
186 | |
187 | /// Returns the size of the value in bits. |
188 | /// |
189 | /// If the value type is a scalable vector type, the scalable property will |
190 | /// be set and the runtime size will be a positive integer multiple of the |
191 | /// base size. |
192 | TypeSize getValueSizeInBits() const { |
193 | return getValueType().getSizeInBits(); |
194 | } |
195 | |
196 | uint64_t getScalarValueSizeInBits() const { |
197 | return getValueType().getScalarType().getFixedSizeInBits(); |
198 | } |
199 | |
200 | // Forwarding methods - These forward to the corresponding methods in SDNode. |
201 | inline unsigned getOpcode() const; |
202 | inline unsigned getNumOperands() const; |
203 | inline const SDValue &getOperand(unsigned i) const; |
204 | inline uint64_t getConstantOperandVal(unsigned i) const; |
205 | inline const APInt &getConstantOperandAPInt(unsigned i) const; |
206 | inline bool isTargetMemoryOpcode() const; |
207 | inline bool isTargetOpcode() const; |
208 | inline bool isMachineOpcode() const; |
209 | inline bool isUndef() const; |
210 | inline unsigned getMachineOpcode() const; |
211 | inline const DebugLoc &getDebugLoc() const; |
212 | inline void dump() const; |
213 | inline void dump(const SelectionDAG *G) const; |
214 | inline void dumpr() const; |
215 | inline void dumpr(const SelectionDAG *G) const; |
216 | |
217 | /// Return true if this operand (which must be a chain) reaches the |
218 | /// specified operand without crossing any side-effecting instructions. |
219 | /// In practice, this looks through token factors and non-volatile loads. |
220 | /// In order to remain efficient, this only |
221 | /// looks a couple of nodes in, it does not do an exhaustive search. |
222 | bool reachesChainWithoutSideEffects(SDValue Dest, |
223 | unsigned Depth = 2) const; |
224 | |
225 | /// Return true if there are no nodes using value ResNo of Node. |
226 | inline bool use_empty() const; |
227 | |
228 | /// Return true if there is exactly one node using value ResNo of Node. |
229 | inline bool hasOneUse() const; |
230 | }; |
231 | |
232 | template<> struct DenseMapInfo<SDValue> { |
233 | static inline SDValue getEmptyKey() { |
234 | SDValue V; |
235 | V.ResNo = -1U; |
236 | return V; |
237 | } |
238 | |
239 | static inline SDValue getTombstoneKey() { |
240 | SDValue V; |
241 | V.ResNo = -2U; |
242 | return V; |
243 | } |
244 | |
245 | static unsigned getHashValue(const SDValue &Val) { |
246 | return ((unsigned)((uintptr_t)Val.getNode() >> 4) ^ |
247 | (unsigned)((uintptr_t)Val.getNode() >> 9)) + Val.getResNo(); |
248 | } |
249 | |
250 | static bool isEqual(const SDValue &LHS, const SDValue &RHS) { |
251 | return LHS == RHS; |
252 | } |
253 | }; |
254 | |
255 | /// Allow casting operators to work directly on |
256 | /// SDValues as if they were SDNode*'s. |
257 | template<> struct simplify_type<SDValue> { |
258 | using SimpleType = SDNode *; |
259 | |
260 | static SimpleType getSimplifiedValue(SDValue &Val) { |
261 | return Val.getNode(); |
262 | } |
263 | }; |
264 | template<> struct simplify_type<const SDValue> { |
265 | using SimpleType = /*const*/ SDNode *; |
266 | |
267 | static SimpleType getSimplifiedValue(const SDValue &Val) { |
268 | return Val.getNode(); |
269 | } |
270 | }; |
271 | |
272 | /// Represents a use of a SDNode. This class holds an SDValue, |
273 | /// which records the SDNode being used and the result number, a |
274 | /// pointer to the SDNode using the value, and Next and Prev pointers, |
275 | /// which link together all the uses of an SDNode. |
276 | /// |
277 | class SDUse { |
278 | /// Val - The value being used. |
279 | SDValue Val; |
280 | /// User - The user of this value. |
281 | SDNode *User = nullptr; |
282 | /// Prev, Next - Pointers to the uses list of the SDNode referred by |
283 | /// this operand. |
284 | SDUse **Prev = nullptr; |
285 | SDUse *Next = nullptr; |
286 | |
287 | public: |
288 | SDUse() = default; |
289 | SDUse(const SDUse &U) = delete; |
290 | SDUse &operator=(const SDUse &) = delete; |
291 | |
292 | /// Normally SDUse will just implicitly convert to an SDValue that it holds. |
293 | operator const SDValue&() const { return Val; } |
294 | |
295 | /// If implicit conversion to SDValue doesn't work, the get() method returns |
296 | /// the SDValue. |
297 | const SDValue &get() const { return Val; } |
298 | |
299 | /// This returns the SDNode that contains this Use. |
300 | SDNode *getUser() { return User; } |
301 | |
302 | /// Get the next SDUse in the use list. |
303 | SDUse *getNext() const { return Next; } |
304 | |
305 | /// Convenience function for get().getNode(). |
306 | SDNode *getNode() const { return Val.getNode(); } |
307 | /// Convenience function for get().getResNo(). |
308 | unsigned getResNo() const { return Val.getResNo(); } |
309 | /// Convenience function for get().getValueType(). |
310 | EVT getValueType() const { return Val.getValueType(); } |
311 | |
312 | /// Convenience function for get().operator== |
313 | bool operator==(const SDValue &V) const { |
314 | return Val == V; |
315 | } |
316 | |
317 | /// Convenience function for get().operator!= |
318 | bool operator!=(const SDValue &V) const { |
319 | return Val != V; |
320 | } |
321 | |
322 | /// Convenience function for get().operator< |
323 | bool operator<(const SDValue &V) const { |
324 | return Val < V; |
325 | } |
326 | |
327 | private: |
328 | friend class SelectionDAG; |
329 | friend class SDNode; |
330 | // TODO: unfriend HandleSDNode once we fix its operand handling. |
331 | friend class HandleSDNode; |
332 | |
333 | void setUser(SDNode *p) { User = p; } |
334 | |
335 | /// Remove this use from its existing use list, assign it the |
336 | /// given value, and add it to the new value's node's use list. |
337 | inline void set(const SDValue &V); |
338 | /// Like set, but only supports initializing a newly-allocated |
339 | /// SDUse with a non-null value. |
340 | inline void setInitial(const SDValue &V); |
341 | /// Like set, but only sets the Node portion of the value, |
342 | /// leaving the ResNo portion unmodified. |
343 | inline void setNode(SDNode *N); |
344 | |
345 | void addToList(SDUse **List) { |
346 | Next = *List; |
347 | if (Next) Next->Prev = &Next; |
348 | Prev = List; |
349 | *List = this; |
350 | } |
351 | |
352 | void removeFromList() { |
353 | *Prev = Next; |
354 | if (Next) Next->Prev = Prev; |
355 | } |
356 | }; |
357 | |
358 | /// simplify_type specializations - Allow casting operators to work directly on |
359 | /// SDValues as if they were SDNode*'s. |
360 | template<> struct simplify_type<SDUse> { |
361 | using SimpleType = SDNode *; |
362 | |
363 | static SimpleType getSimplifiedValue(SDUse &Val) { |
364 | return Val.getNode(); |
365 | } |
366 | }; |
367 | |
368 | /// These are IR-level optimization flags that may be propagated to SDNodes. |
369 | /// TODO: This data structure should be shared by the IR optimizer and the |
370 | /// the backend. |
371 | struct SDNodeFlags { |
372 | private: |
373 | bool NoUnsignedWrap : 1; |
374 | bool NoSignedWrap : 1; |
375 | bool Exact : 1; |
376 | bool NoNaNs : 1; |
377 | bool NoInfs : 1; |
378 | bool NoSignedZeros : 1; |
379 | bool AllowReciprocal : 1; |
380 | bool AllowContract : 1; |
381 | bool ApproximateFuncs : 1; |
382 | bool AllowReassociation : 1; |
383 | |
384 | // We assume instructions do not raise floating-point exceptions by default, |
385 | // and only those marked explicitly may do so. We could choose to represent |
386 | // this via a positive "FPExcept" flags like on the MI level, but having a |
387 | // negative "NoFPExcept" flag here (that defaults to true) makes the flag |
388 | // intersection logic more straightforward. |
389 | bool NoFPExcept : 1; |
390 | |
391 | public: |
392 | /// Default constructor turns off all optimization flags. |
393 | SDNodeFlags() |
394 | : NoUnsignedWrap(false), NoSignedWrap(false), Exact(false), NoNaNs(false), |
395 | NoInfs(false), NoSignedZeros(false), AllowReciprocal(false), |
396 | AllowContract(false), ApproximateFuncs(false), |
397 | AllowReassociation(false), NoFPExcept(false) {} |
398 | |
399 | /// Propagate the fast-math-flags from an IR FPMathOperator. |
400 | void copyFMF(const FPMathOperator &FPMO) { |
401 | setNoNaNs(FPMO.hasNoNaNs()); |
402 | setNoInfs(FPMO.hasNoInfs()); |
403 | setNoSignedZeros(FPMO.hasNoSignedZeros()); |
404 | setAllowReciprocal(FPMO.hasAllowReciprocal()); |
405 | setAllowContract(FPMO.hasAllowContract()); |
406 | setApproximateFuncs(FPMO.hasApproxFunc()); |
407 | setAllowReassociation(FPMO.hasAllowReassoc()); |
408 | } |
409 | |
410 | // These are mutators for each flag. |
411 | void setNoUnsignedWrap(bool b) { NoUnsignedWrap = b; } |
412 | void setNoSignedWrap(bool b) { NoSignedWrap = b; } |
413 | void setExact(bool b) { Exact = b; } |
414 | void setNoNaNs(bool b) { NoNaNs = b; } |
415 | void setNoInfs(bool b) { NoInfs = b; } |
416 | void setNoSignedZeros(bool b) { NoSignedZeros = b; } |
417 | void setAllowReciprocal(bool b) { AllowReciprocal = b; } |
418 | void setAllowContract(bool b) { AllowContract = b; } |
419 | void setApproximateFuncs(bool b) { ApproximateFuncs = b; } |
420 | void setAllowReassociation(bool b) { AllowReassociation = b; } |
421 | void setNoFPExcept(bool b) { NoFPExcept = b; } |
422 | |
423 | // These are accessors for each flag. |
424 | bool hasNoUnsignedWrap() const { return NoUnsignedWrap; } |
425 | bool hasNoSignedWrap() const { return NoSignedWrap; } |
426 | bool hasExact() const { return Exact; } |
427 | bool hasNoNaNs() const { return NoNaNs; } |
428 | bool hasNoInfs() const { return NoInfs; } |
429 | bool hasNoSignedZeros() const { return NoSignedZeros; } |
430 | bool hasAllowReciprocal() const { return AllowReciprocal; } |
431 | bool hasAllowContract() const { return AllowContract; } |
432 | bool hasApproximateFuncs() const { return ApproximateFuncs; } |
433 | bool hasAllowReassociation() const { return AllowReassociation; } |
434 | bool hasNoFPExcept() const { return NoFPExcept; } |
435 | |
436 | /// Clear any flags in this flag set that aren't also set in Flags. All |
437 | /// flags will be cleared if Flags are undefined. |
438 | void intersectWith(const SDNodeFlags Flags) { |
439 | NoUnsignedWrap &= Flags.NoUnsignedWrap; |
440 | NoSignedWrap &= Flags.NoSignedWrap; |
441 | Exact &= Flags.Exact; |
442 | NoNaNs &= Flags.NoNaNs; |
443 | NoInfs &= Flags.NoInfs; |
444 | NoSignedZeros &= Flags.NoSignedZeros; |
445 | AllowReciprocal &= Flags.AllowReciprocal; |
446 | AllowContract &= Flags.AllowContract; |
447 | ApproximateFuncs &= Flags.ApproximateFuncs; |
448 | AllowReassociation &= Flags.AllowReassociation; |
449 | NoFPExcept &= Flags.NoFPExcept; |
450 | } |
451 | }; |
452 | |
453 | /// Represents one node in the SelectionDAG. |
454 | /// |
455 | class SDNode : public FoldingSetNode, public ilist_node<SDNode> { |
456 | private: |
457 | /// The operation that this node performs. |
458 | int16_t NodeType; |
459 | |
460 | protected: |
461 | // We define a set of mini-helper classes to help us interpret the bits in our |
462 | // SubclassData. These are designed to fit within a uint16_t so they pack |
463 | // with NodeType. |
464 | |
465 | #if defined(_AIX) && (!defined(__GNUC__4) || defined(__clang__1)) |
466 | // Except for GCC; by default, AIX compilers store bit-fields in 4-byte words |
467 | // and give the `pack` pragma push semantics. |
468 | #define BEGIN_TWO_BYTE_PACK() _Pragma("pack(2)")pack(2) |
469 | #define END_TWO_BYTE_PACK() _Pragma("pack(pop)")pack(pop) |
470 | #else |
471 | #define BEGIN_TWO_BYTE_PACK() |
472 | #define END_TWO_BYTE_PACK() |
473 | #endif |
474 | |
475 | BEGIN_TWO_BYTE_PACK() |
476 | class SDNodeBitfields { |
477 | friend class SDNode; |
478 | friend class MemIntrinsicSDNode; |
479 | friend class MemSDNode; |
480 | friend class SelectionDAG; |
481 | |
482 | uint16_t HasDebugValue : 1; |
483 | uint16_t IsMemIntrinsic : 1; |
484 | uint16_t IsDivergent : 1; |
485 | }; |
486 | enum { NumSDNodeBits = 3 }; |
487 | |
488 | class ConstantSDNodeBitfields { |
489 | friend class ConstantSDNode; |
490 | |
491 | uint16_t : NumSDNodeBits; |
492 | |
493 | uint16_t IsOpaque : 1; |
494 | }; |
495 | |
496 | class MemSDNodeBitfields { |
497 | friend class MemSDNode; |
498 | friend class MemIntrinsicSDNode; |
499 | friend class AtomicSDNode; |
500 | |
501 | uint16_t : NumSDNodeBits; |
502 | |
503 | uint16_t IsVolatile : 1; |
504 | uint16_t IsNonTemporal : 1; |
505 | uint16_t IsDereferenceable : 1; |
506 | uint16_t IsInvariant : 1; |
507 | }; |
508 | enum { NumMemSDNodeBits = NumSDNodeBits + 4 }; |
509 | |
510 | class LSBaseSDNodeBitfields { |
511 | friend class LSBaseSDNode; |
512 | friend class VPLoadStoreSDNode; |
513 | friend class MaskedLoadStoreSDNode; |
514 | friend class MaskedGatherScatterSDNode; |
515 | friend class VPGatherScatterSDNode; |
516 | |
517 | uint16_t : NumMemSDNodeBits; |
518 | |
519 | // This storage is shared between disparate class hierarchies to hold an |
520 | // enumeration specific to the class hierarchy in use. |
521 | // LSBaseSDNode => enum ISD::MemIndexedMode |
522 | // VPLoadStoreBaseSDNode => enum ISD::MemIndexedMode |
523 | // MaskedLoadStoreBaseSDNode => enum ISD::MemIndexedMode |
524 | // VPGatherScatterSDNode => enum ISD::MemIndexType |
525 | // MaskedGatherScatterSDNode => enum ISD::MemIndexType |
526 | uint16_t AddressingMode : 3; |
527 | }; |
528 | enum { NumLSBaseSDNodeBits = NumMemSDNodeBits + 3 }; |
529 | |
530 | class LoadSDNodeBitfields { |
531 | friend class LoadSDNode; |
532 | friend class VPLoadSDNode; |
533 | friend class MaskedLoadSDNode; |
534 | friend class MaskedGatherSDNode; |
535 | friend class VPGatherSDNode; |
536 | |
537 | uint16_t : NumLSBaseSDNodeBits; |
538 | |
539 | uint16_t ExtTy : 2; // enum ISD::LoadExtType |
540 | uint16_t IsExpanding : 1; |
541 | }; |
542 | |
543 | class StoreSDNodeBitfields { |
544 | friend class StoreSDNode; |
545 | friend class VPStoreSDNode; |
546 | friend class MaskedStoreSDNode; |
547 | friend class MaskedScatterSDNode; |
548 | friend class VPScatterSDNode; |
549 | |
550 | uint16_t : NumLSBaseSDNodeBits; |
551 | |
552 | uint16_t IsTruncating : 1; |
553 | uint16_t IsCompressing : 1; |
554 | }; |
555 | |
556 | union { |
557 | char RawSDNodeBits[sizeof(uint16_t)]; |
558 | SDNodeBitfields SDNodeBits; |
559 | ConstantSDNodeBitfields ConstantSDNodeBits; |
560 | MemSDNodeBitfields MemSDNodeBits; |
561 | LSBaseSDNodeBitfields LSBaseSDNodeBits; |
562 | LoadSDNodeBitfields LoadSDNodeBits; |
563 | StoreSDNodeBitfields StoreSDNodeBits; |
564 | }; |
565 | END_TWO_BYTE_PACK() |
566 | #undef BEGIN_TWO_BYTE_PACK |
567 | #undef END_TWO_BYTE_PACK |
568 | |
569 | // RawSDNodeBits must cover the entirety of the union. This means that all of |
570 | // the union's members must have size <= RawSDNodeBits. We write the RHS as |
571 | // "2" instead of sizeof(RawSDNodeBits) because MSVC can't handle the latter. |
572 | static_assert(sizeof(SDNodeBitfields) <= 2, "field too wide"); |
573 | static_assert(sizeof(ConstantSDNodeBitfields) <= 2, "field too wide"); |
574 | static_assert(sizeof(MemSDNodeBitfields) <= 2, "field too wide"); |
575 | static_assert(sizeof(LSBaseSDNodeBitfields) <= 2, "field too wide"); |
576 | static_assert(sizeof(LoadSDNodeBitfields) <= 2, "field too wide"); |
577 | static_assert(sizeof(StoreSDNodeBitfields) <= 2, "field too wide"); |
578 | |
579 | private: |
580 | friend class SelectionDAG; |
581 | // TODO: unfriend HandleSDNode once we fix its operand handling. |
582 | friend class HandleSDNode; |
583 | |
584 | /// Unique id per SDNode in the DAG. |
585 | int NodeId = -1; |
586 | |
587 | /// The values that are used by this operation. |
588 | SDUse *OperandList = nullptr; |
589 | |
590 | /// The types of the values this node defines. SDNode's may |
591 | /// define multiple values simultaneously. |
592 | const EVT *ValueList; |
593 | |
594 | /// List of uses for this SDNode. |
595 | SDUse *UseList = nullptr; |
596 | |
597 | /// The number of entries in the Operand/Value list. |
598 | unsigned short NumOperands = 0; |
599 | unsigned short NumValues; |
600 | |
601 | // The ordering of the SDNodes. It roughly corresponds to the ordering of the |
602 | // original LLVM instructions. |
603 | // This is used for turning off scheduling, because we'll forgo |
604 | // the normal scheduling algorithms and output the instructions according to |
605 | // this ordering. |
606 | unsigned IROrder; |
607 | |
608 | /// Source line information. |
609 | DebugLoc debugLoc; |
610 | |
611 | /// Return a pointer to the specified value type. |
612 | static const EVT *getValueTypeList(EVT VT); |
613 | |
614 | SDNodeFlags Flags; |
615 | |
616 | public: |
617 | /// Unique and persistent id per SDNode in the DAG. |
618 | /// Used for debug printing. |
619 | uint16_t PersistentId; |
620 | |
621 | //===--------------------------------------------------------------------===// |
622 | // Accessors |
623 | // |
624 | |
625 | /// Return the SelectionDAG opcode value for this node. For |
626 | /// pre-isel nodes (those for which isMachineOpcode returns false), these |
627 | /// are the opcode values in the ISD and <target>ISD namespaces. For |
628 | /// post-isel opcodes, see getMachineOpcode. |
629 | unsigned getOpcode() const { return (unsigned short)NodeType; } |
630 | |
631 | /// Test if this node has a target-specific opcode (in the |
632 | /// \<target\>ISD namespace). |
633 | bool isTargetOpcode() const { return NodeType >= ISD::BUILTIN_OP_END; } |
634 | |
635 | /// Test if this node has a target-specific opcode that may raise |
636 | /// FP exceptions (in the \<target\>ISD namespace and greater than |
637 | /// FIRST_TARGET_STRICTFP_OPCODE). Note that all target memory |
638 | /// opcode are currently automatically considered to possibly raise |
639 | /// FP exceptions as well. |
640 | bool isTargetStrictFPOpcode() const { |
641 | return NodeType >= ISD::FIRST_TARGET_STRICTFP_OPCODE; |
642 | } |
643 | |
644 | /// Test if this node has a target-specific |
645 | /// memory-referencing opcode (in the \<target\>ISD namespace and |
646 | /// greater than FIRST_TARGET_MEMORY_OPCODE). |
647 | bool isTargetMemoryOpcode() const { |
648 | return NodeType >= ISD::FIRST_TARGET_MEMORY_OPCODE; |
649 | } |
650 | |
651 | /// Return true if the type of the node type undefined. |
652 | bool isUndef() const { return NodeType == ISD::UNDEF; } |
653 | |
654 | /// Test if this node is a memory intrinsic (with valid pointer information). |
655 | /// INTRINSIC_W_CHAIN and INTRINSIC_VOID nodes are sometimes created for |
656 | /// non-memory intrinsics (with chains) that are not really instances of |
657 | /// MemSDNode. For such nodes, we need some extra state to determine the |
658 | /// proper classof relationship. |
659 | bool isMemIntrinsic() const { |
660 | return (NodeType == ISD::INTRINSIC_W_CHAIN || |
661 | NodeType == ISD::INTRINSIC_VOID) && |
662 | SDNodeBits.IsMemIntrinsic; |
663 | } |
664 | |
665 | /// Test if this node is a strict floating point pseudo-op. |
666 | bool isStrictFPOpcode() { |
667 | switch (NodeType) { |
668 | default: |
669 | return false; |
670 | case ISD::STRICT_FP16_TO_FP: |
671 | case ISD::STRICT_FP_TO_FP16: |
672 | #define DAG_INSTRUCTION(NAME, NARG, ROUND_MODE, INTRINSIC, DAGN) \ |
673 | case ISD::STRICT_##DAGN: |
674 | #include "llvm/IR/ConstrainedOps.def" |
675 | return true; |
676 | } |
677 | } |
678 | |
679 | /// Test if this node has a post-isel opcode, directly |
680 | /// corresponding to a MachineInstr opcode. |
681 | bool isMachineOpcode() const { return NodeType < 0; } |
682 | |
683 | /// This may only be called if isMachineOpcode returns |
684 | /// true. It returns the MachineInstr opcode value that the node's opcode |
685 | /// corresponds to. |
686 | unsigned getMachineOpcode() const { |
687 | assert(isMachineOpcode() && "Not a MachineInstr opcode!")(static_cast <bool> (isMachineOpcode() && "Not a MachineInstr opcode!" ) ? void (0) : __assert_fail ("isMachineOpcode() && \"Not a MachineInstr opcode!\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/include/llvm/CodeGen/SelectionDAGNodes.h" , 687, __extension__ __PRETTY_FUNCTION__)); |
688 | return ~NodeType; |
689 | } |
690 | |
691 | bool getHasDebugValue() const { return SDNodeBits.HasDebugValue; } |
692 | void setHasDebugValue(bool b) { SDNodeBits.HasDebugValue = b; } |
693 | |
694 | bool isDivergent() const { return SDNodeBits.IsDivergent; } |
695 | |
696 | /// Return true if there are no uses of this node. |
697 | bool use_empty() const { return UseList == nullptr; } |
698 | |
699 | /// Return true if there is exactly one use of this node. |
700 | bool hasOneUse() const { return hasSingleElement(uses()); } |
701 | |
702 | /// Return the number of uses of this node. This method takes |
703 | /// time proportional to the number of uses. |
704 | size_t use_size() const { return std::distance(use_begin(), use_end()); } |
705 | |
706 | /// Return the unique node id. |
707 | int getNodeId() const { return NodeId; } |
708 | |
709 | /// Set unique node id. |
710 | void setNodeId(int Id) { NodeId = Id; } |
711 | |
712 | /// Return the node ordering. |
713 | unsigned getIROrder() const { return IROrder; } |
714 | |
715 | /// Set the node ordering. |
716 | void setIROrder(unsigned Order) { IROrder = Order; } |
717 | |
718 | /// Return the source location info. |
719 | const DebugLoc &getDebugLoc() const { return debugLoc; } |
720 | |
721 | /// Set source location info. Try to avoid this, putting |
722 | /// it in the constructor is preferable. |
723 | void setDebugLoc(DebugLoc dl) { debugLoc = std::move(dl); } |
724 | |
725 | /// This class provides iterator support for SDUse |
726 | /// operands that use a specific SDNode. |
727 | class use_iterator { |
728 | friend class SDNode; |
729 | |
730 | SDUse *Op = nullptr; |
731 | |
732 | explicit use_iterator(SDUse *op) : Op(op) {} |
733 | |
734 | public: |
735 | using iterator_category = std::forward_iterator_tag; |
736 | using value_type = SDUse; |
737 | using difference_type = std::ptrdiff_t; |
738 | using pointer = value_type *; |
739 | using reference = value_type &; |
740 | |
741 | use_iterator() = default; |
742 | use_iterator(const use_iterator &I) : Op(I.Op) {} |
743 | |
744 | bool operator==(const use_iterator &x) const { |
745 | return Op == x.Op; |
746 | } |
747 | bool operator!=(const use_iterator &x) const { |
748 | return !operator==(x); |
749 | } |
750 | |
751 | /// Return true if this iterator is at the end of uses list. |
752 | bool atEnd() const { return Op == nullptr; } |
753 | |
754 | // Iterator traversal: forward iteration only. |
755 | use_iterator &operator++() { // Preincrement |
756 | assert(Op && "Cannot increment end iterator!")(static_cast <bool> (Op && "Cannot increment end iterator!" ) ? void (0) : __assert_fail ("Op && \"Cannot increment end iterator!\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/include/llvm/CodeGen/SelectionDAGNodes.h" , 756, __extension__ __PRETTY_FUNCTION__)); |
757 | Op = Op->getNext(); |
758 | return *this; |
759 | } |
760 | |
761 | use_iterator operator++(int) { // Postincrement |
762 | use_iterator tmp = *this; ++*this; return tmp; |
763 | } |
764 | |
765 | /// Retrieve a pointer to the current user node. |
766 | SDNode *operator*() const { |
767 | assert(Op && "Cannot dereference end iterator!")(static_cast <bool> (Op && "Cannot dereference end iterator!" ) ? void (0) : __assert_fail ("Op && \"Cannot dereference end iterator!\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/include/llvm/CodeGen/SelectionDAGNodes.h" , 767, __extension__ __PRETTY_FUNCTION__)); |
768 | return Op->getUser(); |
769 | } |
770 | |
771 | SDNode *operator->() const { return operator*(); } |
772 | |
773 | SDUse &getUse() const { return *Op; } |
774 | |
775 | /// Retrieve the operand # of this use in its user. |
776 | unsigned getOperandNo() const { |
777 | assert(Op && "Cannot dereference end iterator!")(static_cast <bool> (Op && "Cannot dereference end iterator!" ) ? void (0) : __assert_fail ("Op && \"Cannot dereference end iterator!\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/include/llvm/CodeGen/SelectionDAGNodes.h" , 777, __extension__ __PRETTY_FUNCTION__)); |
778 | return (unsigned)(Op - Op->getUser()->OperandList); |
779 | } |
780 | }; |
781 | |
782 | /// Provide iteration support to walk over all uses of an SDNode. |
783 | use_iterator use_begin() const { |
784 | return use_iterator(UseList); |
785 | } |
786 | |
787 | static use_iterator use_end() { return use_iterator(nullptr); } |
788 | |
789 | inline iterator_range<use_iterator> uses() { |
790 | return make_range(use_begin(), use_end()); |
791 | } |
792 | inline iterator_range<use_iterator> uses() const { |
793 | return make_range(use_begin(), use_end()); |
794 | } |
795 | |
796 | /// Return true if there are exactly NUSES uses of the indicated value. |
797 | /// This method ignores uses of other values defined by this operation. |
798 | bool hasNUsesOfValue(unsigned NUses, unsigned Value) const; |
799 | |
800 | /// Return true if there are any use of the indicated value. |
801 | /// This method ignores uses of other values defined by this operation. |
802 | bool hasAnyUseOfValue(unsigned Value) const; |
803 | |
804 | /// Return true if this node is the only use of N. |
805 | bool isOnlyUserOf(const SDNode *N) const; |
806 | |
807 | /// Return true if this node is an operand of N. |
808 | bool isOperandOf(const SDNode *N) const; |
809 | |
810 | /// Return true if this node is a predecessor of N. |
811 | /// NOTE: Implemented on top of hasPredecessor and every bit as |
812 | /// expensive. Use carefully. |
813 | bool isPredecessorOf(const SDNode *N) const { |
814 | return N->hasPredecessor(this); |
815 | } |
816 | |
817 | /// Return true if N is a predecessor of this node. |
818 | /// N is either an operand of this node, or can be reached by recursively |
819 | /// traversing up the operands. |
820 | /// NOTE: This is an expensive method. Use it carefully. |
821 | bool hasPredecessor(const SDNode *N) const; |
822 | |
823 | /// Returns true if N is a predecessor of any node in Worklist. This |
824 | /// helper keeps Visited and Worklist sets externally to allow unions |
825 | /// searches to be performed in parallel, caching of results across |
826 | /// queries and incremental addition to Worklist. Stops early if N is |
827 | /// found but will resume. Remember to clear Visited and Worklists |
828 | /// if DAG changes. MaxSteps gives a maximum number of nodes to visit before |
829 | /// giving up. The TopologicalPrune flag signals that positive NodeIds are |
830 | /// topologically ordered (Operands have strictly smaller node id) and search |
831 | /// can be pruned leveraging this. |
832 | static bool hasPredecessorHelper(const SDNode *N, |
833 | SmallPtrSetImpl<const SDNode *> &Visited, |
834 | SmallVectorImpl<const SDNode *> &Worklist, |
835 | unsigned int MaxSteps = 0, |
836 | bool TopologicalPrune = false) { |
837 | SmallVector<const SDNode *, 8> DeferredNodes; |
838 | if (Visited.count(N)) |
839 | return true; |
840 | |
841 | // Node Id's are assigned in three places: As a topological |
842 | // ordering (> 0), during legalization (results in values set to |
843 | // 0), new nodes (set to -1). If N has a topolgical id then we |
844 | // know that all nodes with ids smaller than it cannot be |
845 | // successors and we need not check them. Filter out all node |
846 | // that can't be matches. We add them to the worklist before exit |
847 | // in case of multiple calls. Note that during selection the topological id |
848 | // may be violated if a node's predecessor is selected before it. We mark |
849 | // this at selection negating the id of unselected successors and |
850 | // restricting topological pruning to positive ids. |
851 | |
852 | int NId = N->getNodeId(); |
853 | // If we Invalidated the Id, reconstruct original NId. |
854 | if (NId < -1) |
855 | NId = -(NId + 1); |
856 | |
857 | bool Found = false; |
858 | while (!Worklist.empty()) { |
859 | const SDNode *M = Worklist.pop_back_val(); |
860 | int MId = M->getNodeId(); |
861 | if (TopologicalPrune && M->getOpcode() != ISD::TokenFactor && (NId > 0) && |
862 | (MId > 0) && (MId < NId)) { |
863 | DeferredNodes.push_back(M); |
864 | continue; |
865 | } |
866 | for (const SDValue &OpV : M->op_values()) { |
867 | SDNode *Op = OpV.getNode(); |
868 | if (Visited.insert(Op).second) |
869 | Worklist.push_back(Op); |
870 | if (Op == N) |
871 | Found = true; |
872 | } |
873 | if (Found) |
874 | break; |
875 | if (MaxSteps != 0 && Visited.size() >= MaxSteps) |
876 | break; |
877 | } |
878 | // Push deferred nodes back on worklist. |
879 | Worklist.append(DeferredNodes.begin(), DeferredNodes.end()); |
880 | // If we bailed early, conservatively return found. |
881 | if (MaxSteps != 0 && Visited.size() >= MaxSteps) |
882 | return true; |
883 | return Found; |
884 | } |
885 | |
886 | /// Return true if all the users of N are contained in Nodes. |
887 | /// NOTE: Requires at least one match, but doesn't require them all. |
888 | static bool areOnlyUsersOf(ArrayRef<const SDNode *> Nodes, const SDNode *N); |
889 | |
890 | /// Return the number of values used by this operation. |
891 | unsigned getNumOperands() const { return NumOperands; } |
892 | |
893 | /// Return the maximum number of operands that a SDNode can hold. |
894 | static constexpr size_t getMaxNumOperands() { |
895 | return std::numeric_limits<decltype(SDNode::NumOperands)>::max(); |
896 | } |
897 | |
898 | /// Helper method returns the integer value of a ConstantSDNode operand. |
899 | inline uint64_t getConstantOperandVal(unsigned Num) const; |
900 | |
901 | /// Helper method returns the APInt of a ConstantSDNode operand. |
902 | inline const APInt &getConstantOperandAPInt(unsigned Num) const; |
903 | |
904 | const SDValue &getOperand(unsigned Num) const { |
905 | assert(Num < NumOperands && "Invalid child # of SDNode!")(static_cast <bool> (Num < NumOperands && "Invalid child # of SDNode!" ) ? void (0) : __assert_fail ("Num < NumOperands && \"Invalid child # of SDNode!\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/include/llvm/CodeGen/SelectionDAGNodes.h" , 905, __extension__ __PRETTY_FUNCTION__)); |
906 | return OperandList[Num]; |
907 | } |
908 | |
909 | using op_iterator = SDUse *; |
910 | |
911 | op_iterator op_begin() const { return OperandList; } |
912 | op_iterator op_end() const { return OperandList+NumOperands; } |
913 | ArrayRef<SDUse> ops() const { return makeArrayRef(op_begin(), op_end()); } |
914 | |
915 | /// Iterator for directly iterating over the operand SDValue's. |
916 | struct value_op_iterator |
917 | : iterator_adaptor_base<value_op_iterator, op_iterator, |
918 | std::random_access_iterator_tag, SDValue, |
919 | ptrdiff_t, value_op_iterator *, |
920 | value_op_iterator *> { |
921 | explicit value_op_iterator(SDUse *U = nullptr) |
922 | : iterator_adaptor_base(U) {} |
923 | |
924 | const SDValue &operator*() const { return I->get(); } |
925 | }; |
926 | |
927 | iterator_range<value_op_iterator> op_values() const { |
928 | return make_range(value_op_iterator(op_begin()), |
929 | value_op_iterator(op_end())); |
930 | } |
931 | |
932 | SDVTList getVTList() const { |
933 | SDVTList X = { ValueList, NumValues }; |
934 | return X; |
935 | } |
936 | |
937 | /// If this node has a glue operand, return the node |
938 | /// to which the glue operand points. Otherwise return NULL. |
939 | SDNode *getGluedNode() const { |
940 | if (getNumOperands() != 0 && |
941 | getOperand(getNumOperands()-1).getValueType() == MVT::Glue) |
942 | return getOperand(getNumOperands()-1).getNode(); |
943 | return nullptr; |
944 | } |
945 | |
946 | /// If this node has a glue value with a user, return |
947 | /// the user (there is at most one). Otherwise return NULL. |
948 | SDNode *getGluedUser() const { |
949 | for (use_iterator UI = use_begin(), UE = use_end(); UI != UE; ++UI) |
950 | if (UI.getUse().get().getValueType() == MVT::Glue) |
951 | return *UI; |
952 | return nullptr; |
953 | } |
954 | |
955 | SDNodeFlags getFlags() const { return Flags; } |
956 | void setFlags(SDNodeFlags NewFlags) { Flags = NewFlags; } |
957 | |
958 | /// Clear any flags in this node that aren't also set in Flags. |
959 | /// If Flags is not in a defined state then this has no effect. |
960 | void intersectFlagsWith(const SDNodeFlags Flags); |
961 | |
962 | /// Return the number of values defined/returned by this operator. |
963 | unsigned getNumValues() const { return NumValues; } |
964 | |
965 | /// Return the type of a specified result. |
966 | EVT getValueType(unsigned ResNo) const { |
967 | assert(ResNo < NumValues && "Illegal result number!")(static_cast <bool> (ResNo < NumValues && "Illegal result number!" ) ? void (0) : __assert_fail ("ResNo < NumValues && \"Illegal result number!\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/include/llvm/CodeGen/SelectionDAGNodes.h" , 967, __extension__ __PRETTY_FUNCTION__)); |
968 | return ValueList[ResNo]; |
969 | } |
970 | |
971 | /// Return the type of a specified result as a simple type. |
972 | MVT getSimpleValueType(unsigned ResNo) const { |
973 | return getValueType(ResNo).getSimpleVT(); |
974 | } |
975 | |
976 | /// Returns MVT::getSizeInBits(getValueType(ResNo)). |
977 | /// |
978 | /// If the value type is a scalable vector type, the scalable property will |
979 | /// be set and the runtime size will be a positive integer multiple of the |
980 | /// base size. |
981 | TypeSize getValueSizeInBits(unsigned ResNo) const { |
982 | return getValueType(ResNo).getSizeInBits(); |
983 | } |
984 | |
985 | using value_iterator = const EVT *; |
986 | |
987 | value_iterator value_begin() const { return ValueList; } |
988 | value_iterator value_end() const { return ValueList+NumValues; } |
989 | iterator_range<value_iterator> values() const { |
990 | return llvm::make_range(value_begin(), value_end()); |
991 | } |
992 | |
993 | /// Return the opcode of this operation for printing. |
994 | std::string getOperationName(const SelectionDAG *G = nullptr) const; |
995 | static const char* getIndexedModeName(ISD::MemIndexedMode AM); |
996 | void print_types(raw_ostream &OS, const SelectionDAG *G) const; |
997 | void print_details(raw_ostream &OS, const SelectionDAG *G) const; |
998 | void print(raw_ostream &OS, const SelectionDAG *G = nullptr) const; |
999 | void printr(raw_ostream &OS, const SelectionDAG *G = nullptr) const; |
1000 | |
1001 | /// Print a SelectionDAG node and all children down to |
1002 | /// the leaves. The given SelectionDAG allows target-specific nodes |
1003 | /// to be printed in human-readable form. Unlike printr, this will |
1004 | /// print the whole DAG, including children that appear multiple |
1005 | /// times. |
1006 | /// |
1007 | void printrFull(raw_ostream &O, const SelectionDAG *G = nullptr) const; |
1008 | |
1009 | /// Print a SelectionDAG node and children up to |
1010 | /// depth "depth." The given SelectionDAG allows target-specific |
1011 | /// nodes to be printed in human-readable form. Unlike printr, this |
1012 | /// will print children that appear multiple times wherever they are |
1013 | /// used. |
1014 | /// |
1015 | void printrWithDepth(raw_ostream &O, const SelectionDAG *G = nullptr, |
1016 | unsigned depth = 100) const; |
1017 | |
1018 | /// Dump this node, for debugging. |
1019 | void dump() const; |
1020 | |
1021 | /// Dump (recursively) this node and its use-def subgraph. |
1022 | void dumpr() const; |
1023 | |
1024 | /// Dump this node, for debugging. |
1025 | /// The given SelectionDAG allows target-specific nodes to be printed |
1026 | /// in human-readable form. |
1027 | void dump(const SelectionDAG *G) const; |
1028 | |
1029 | /// Dump (recursively) this node and its use-def subgraph. |
1030 | /// The given SelectionDAG allows target-specific nodes to be printed |
1031 | /// in human-readable form. |
1032 | void dumpr(const SelectionDAG *G) const; |
1033 | |
1034 | /// printrFull to dbgs(). The given SelectionDAG allows |
1035 | /// target-specific nodes to be printed in human-readable form. |
1036 | /// Unlike dumpr, this will print the whole DAG, including children |
1037 | /// that appear multiple times. |
1038 | void dumprFull(const SelectionDAG *G = nullptr) const; |
1039 | |
1040 | /// printrWithDepth to dbgs(). The given |
1041 | /// SelectionDAG allows target-specific nodes to be printed in |
1042 | /// human-readable form. Unlike dumpr, this will print children |
1043 | /// that appear multiple times wherever they are used. |
1044 | /// |
1045 | void dumprWithDepth(const SelectionDAG *G = nullptr, |
1046 | unsigned depth = 100) const; |
1047 | |
1048 | /// Gather unique data for the node. |
1049 | void Profile(FoldingSetNodeID &ID) const; |
1050 | |
1051 | /// This method should only be used by the SDUse class. |
1052 | void addUse(SDUse &U) { U.addToList(&UseList); } |
1053 | |
1054 | protected: |
1055 | static SDVTList getSDVTList(EVT VT) { |
1056 | SDVTList Ret = { getValueTypeList(VT), 1 }; |
1057 | return Ret; |
1058 | } |
1059 | |
1060 | /// Create an SDNode. |
1061 | /// |
1062 | /// SDNodes are created without any operands, and never own the operand |
1063 | /// storage. To add operands, see SelectionDAG::createOperands. |
1064 | SDNode(unsigned Opc, unsigned Order, DebugLoc dl, SDVTList VTs) |
1065 | : NodeType(Opc), ValueList(VTs.VTs), NumValues(VTs.NumVTs), |
1066 | IROrder(Order), debugLoc(std::move(dl)) { |
1067 | memset(&RawSDNodeBits, 0, sizeof(RawSDNodeBits)); |
1068 | assert(debugLoc.hasTrivialDestructor() && "Expected trivial destructor")(static_cast <bool> (debugLoc.hasTrivialDestructor() && "Expected trivial destructor") ? void (0) : __assert_fail ("debugLoc.hasTrivialDestructor() && \"Expected trivial destructor\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/include/llvm/CodeGen/SelectionDAGNodes.h" , 1068, __extension__ __PRETTY_FUNCTION__)); |
1069 | assert(NumValues == VTs.NumVTs &&(static_cast <bool> (NumValues == VTs.NumVTs && "NumValues wasn't wide enough for its operands!") ? void (0) : __assert_fail ("NumValues == VTs.NumVTs && \"NumValues wasn't wide enough for its operands!\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/include/llvm/CodeGen/SelectionDAGNodes.h" , 1070, __extension__ __PRETTY_FUNCTION__)) |
1070 | "NumValues wasn't wide enough for its operands!")(static_cast <bool> (NumValues == VTs.NumVTs && "NumValues wasn't wide enough for its operands!") ? void (0) : __assert_fail ("NumValues == VTs.NumVTs && \"NumValues wasn't wide enough for its operands!\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/include/llvm/CodeGen/SelectionDAGNodes.h" , 1070, __extension__ __PRETTY_FUNCTION__)); |
1071 | } |
1072 | |
1073 | /// Release the operands and set this node to have zero operands. |
1074 | void DropOperands(); |
1075 | }; |
1076 | |
1077 | /// Wrapper class for IR location info (IR ordering and DebugLoc) to be passed |
1078 | /// into SDNode creation functions. |
1079 | /// When an SDNode is created from the DAGBuilder, the DebugLoc is extracted |
1080 | /// from the original Instruction, and IROrder is the ordinal position of |
1081 | /// the instruction. |
1082 | /// When an SDNode is created after the DAG is being built, both DebugLoc and |
1083 | /// the IROrder are propagated from the original SDNode. |
1084 | /// So SDLoc class provides two constructors besides the default one, one to |
1085 | /// be used by the DAGBuilder, the other to be used by others. |
1086 | class SDLoc { |
1087 | private: |
1088 | DebugLoc DL; |
1089 | int IROrder = 0; |
1090 | |
1091 | public: |
1092 | SDLoc() = default; |
1093 | SDLoc(const SDNode *N) : DL(N->getDebugLoc()), IROrder(N->getIROrder()) {} |
1094 | SDLoc(const SDValue V) : SDLoc(V.getNode()) {} |
1095 | SDLoc(const Instruction *I, int Order) : IROrder(Order) { |
1096 | assert(Order >= 0 && "bad IROrder")(static_cast <bool> (Order >= 0 && "bad IROrder" ) ? void (0) : __assert_fail ("Order >= 0 && \"bad IROrder\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/include/llvm/CodeGen/SelectionDAGNodes.h" , 1096, __extension__ __PRETTY_FUNCTION__)); |
1097 | if (I) |
1098 | DL = I->getDebugLoc(); |
1099 | } |
1100 | |
1101 | unsigned getIROrder() const { return IROrder; } |
1102 | const DebugLoc &getDebugLoc() const { return DL; } |
1103 | }; |
1104 | |
1105 | // Define inline functions from the SDValue class. |
1106 | |
1107 | inline SDValue::SDValue(SDNode *node, unsigned resno) |
1108 | : Node(node), ResNo(resno) { |
1109 | // Explicitly check for !ResNo to avoid use-after-free, because there are |
1110 | // callers that use SDValue(N, 0) with a deleted N to indicate successful |
1111 | // combines. |
1112 | assert((!Node || !ResNo || ResNo < Node->getNumValues()) &&(static_cast <bool> ((!Node || !ResNo || ResNo < Node ->getNumValues()) && "Invalid result number for the given node!" ) ? void (0) : __assert_fail ("(!Node || !ResNo || ResNo < Node->getNumValues()) && \"Invalid result number for the given node!\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/include/llvm/CodeGen/SelectionDAGNodes.h" , 1113, __extension__ __PRETTY_FUNCTION__)) |
1113 | "Invalid result number for the given node!")(static_cast <bool> ((!Node || !ResNo || ResNo < Node ->getNumValues()) && "Invalid result number for the given node!" ) ? void (0) : __assert_fail ("(!Node || !ResNo || ResNo < Node->getNumValues()) && \"Invalid result number for the given node!\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/include/llvm/CodeGen/SelectionDAGNodes.h" , 1113, __extension__ __PRETTY_FUNCTION__)); |
1114 | assert(ResNo < -2U && "Cannot use result numbers reserved for DenseMaps.")(static_cast <bool> (ResNo < -2U && "Cannot use result numbers reserved for DenseMaps." ) ? void (0) : __assert_fail ("ResNo < -2U && \"Cannot use result numbers reserved for DenseMaps.\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/include/llvm/CodeGen/SelectionDAGNodes.h" , 1114, __extension__ __PRETTY_FUNCTION__)); |
1115 | } |
1116 | |
1117 | inline unsigned SDValue::getOpcode() const { |
1118 | return Node->getOpcode(); |
1119 | } |
1120 | |
1121 | inline EVT SDValue::getValueType() const { |
1122 | return Node->getValueType(ResNo); |
1123 | } |
1124 | |
1125 | inline unsigned SDValue::getNumOperands() const { |
1126 | return Node->getNumOperands(); |
1127 | } |
1128 | |
1129 | inline const SDValue &SDValue::getOperand(unsigned i) const { |
1130 | return Node->getOperand(i); |
1131 | } |
1132 | |
1133 | inline uint64_t SDValue::getConstantOperandVal(unsigned i) const { |
1134 | return Node->getConstantOperandVal(i); |
1135 | } |
1136 | |
1137 | inline const APInt &SDValue::getConstantOperandAPInt(unsigned i) const { |
1138 | return Node->getConstantOperandAPInt(i); |
1139 | } |
1140 | |
1141 | inline bool SDValue::isTargetOpcode() const { |
1142 | return Node->isTargetOpcode(); |
1143 | } |
1144 | |
1145 | inline bool SDValue::isTargetMemoryOpcode() const { |
1146 | return Node->isTargetMemoryOpcode(); |
1147 | } |
1148 | |
1149 | inline bool SDValue::isMachineOpcode() const { |
1150 | return Node->isMachineOpcode(); |
1151 | } |
1152 | |
1153 | inline unsigned SDValue::getMachineOpcode() const { |
1154 | return Node->getMachineOpcode(); |
1155 | } |
1156 | |
1157 | inline bool SDValue::isUndef() const { |
1158 | return Node->isUndef(); |
1159 | } |
1160 | |
1161 | inline bool SDValue::use_empty() const { |
1162 | return !Node->hasAnyUseOfValue(ResNo); |
1163 | } |
1164 | |
1165 | inline bool SDValue::hasOneUse() const { |
1166 | return Node->hasNUsesOfValue(1, ResNo); |
1167 | } |
1168 | |
1169 | inline const DebugLoc &SDValue::getDebugLoc() const { |
1170 | return Node->getDebugLoc(); |
1171 | } |
1172 | |
1173 | inline void SDValue::dump() const { |
1174 | return Node->dump(); |
1175 | } |
1176 | |
1177 | inline void SDValue::dump(const SelectionDAG *G) const { |
1178 | return Node->dump(G); |
1179 | } |
1180 | |
1181 | inline void SDValue::dumpr() const { |
1182 | return Node->dumpr(); |
1183 | } |
1184 | |
1185 | inline void SDValue::dumpr(const SelectionDAG *G) const { |
1186 | return Node->dumpr(G); |
1187 | } |
1188 | |
1189 | // Define inline functions from the SDUse class. |
1190 | |
1191 | inline void SDUse::set(const SDValue &V) { |
1192 | if (Val.getNode()) removeFromList(); |
1193 | Val = V; |
1194 | if (V.getNode()) V.getNode()->addUse(*this); |
1195 | } |
1196 | |
1197 | inline void SDUse::setInitial(const SDValue &V) { |
1198 | Val = V; |
1199 | V.getNode()->addUse(*this); |
1200 | } |
1201 | |
1202 | inline void SDUse::setNode(SDNode *N) { |
1203 | if (Val.getNode()) removeFromList(); |
1204 | Val.setNode(N); |
1205 | if (N) N->addUse(*this); |
1206 | } |
1207 | |
1208 | /// This class is used to form a handle around another node that |
1209 | /// is persistent and is updated across invocations of replaceAllUsesWith on its |
1210 | /// operand. This node should be directly created by end-users and not added to |
1211 | /// the AllNodes list. |
1212 | class HandleSDNode : public SDNode { |
1213 | SDUse Op; |
1214 | |
1215 | public: |
1216 | explicit HandleSDNode(SDValue X) |
1217 | : SDNode(ISD::HANDLENODE, 0, DebugLoc(), getSDVTList(MVT::Other)) { |
1218 | // HandleSDNodes are never inserted into the DAG, so they won't be |
1219 | // auto-numbered. Use ID 65535 as a sentinel. |
1220 | PersistentId = 0xffff; |
1221 | |
1222 | // Manually set up the operand list. This node type is special in that it's |
1223 | // always stack allocated and SelectionDAG does not manage its operands. |
1224 | // TODO: This should either (a) not be in the SDNode hierarchy, or (b) not |
1225 | // be so special. |
1226 | Op.setUser(this); |
1227 | Op.setInitial(X); |
1228 | NumOperands = 1; |
1229 | OperandList = &Op; |
1230 | } |
1231 | ~HandleSDNode(); |
1232 | |
1233 | const SDValue &getValue() const { return Op; } |
1234 | }; |
1235 | |
1236 | class AddrSpaceCastSDNode : public SDNode { |
1237 | private: |
1238 | unsigned SrcAddrSpace; |
1239 | unsigned DestAddrSpace; |
1240 | |
1241 | public: |
1242 | AddrSpaceCastSDNode(unsigned Order, const DebugLoc &dl, EVT VT, |
1243 | unsigned SrcAS, unsigned DestAS); |
1244 | |
1245 | unsigned getSrcAddressSpace() const { return SrcAddrSpace; } |
1246 | unsigned getDestAddressSpace() const { return DestAddrSpace; } |
1247 | |
1248 | static bool classof(const SDNode *N) { |
1249 | return N->getOpcode() == ISD::ADDRSPACECAST; |
1250 | } |
1251 | }; |
1252 | |
1253 | /// This is an abstract virtual class for memory operations. |
1254 | class MemSDNode : public SDNode { |
1255 | private: |
1256 | // VT of in-memory value. |
1257 | EVT MemoryVT; |
1258 | |
1259 | protected: |
1260 | /// Memory reference information. |
1261 | MachineMemOperand *MMO; |
1262 | |
1263 | public: |
1264 | MemSDNode(unsigned Opc, unsigned Order, const DebugLoc &dl, SDVTList VTs, |
1265 | EVT memvt, MachineMemOperand *MMO); |
1266 | |
1267 | bool readMem() const { return MMO->isLoad(); } |
1268 | bool writeMem() const { return MMO->isStore(); } |
1269 | |
1270 | /// Returns alignment and volatility of the memory access |
1271 | Align getOriginalAlign() const { return MMO->getBaseAlign(); } |
1272 | Align getAlign() const { return MMO->getAlign(); } |
1273 | // FIXME: Remove once transition to getAlign is over. |
1274 | unsigned getAlignment() const { return MMO->getAlign().value(); } |
1275 | |
1276 | /// Return the SubclassData value, without HasDebugValue. This contains an |
1277 | /// encoding of the volatile flag, as well as bits used by subclasses. This |
1278 | /// function should only be used to compute a FoldingSetNodeID value. |
1279 | /// The HasDebugValue bit is masked out because CSE map needs to match |
1280 | /// nodes with debug info with nodes without debug info. Same is about |
1281 | /// isDivergent bit. |
1282 | unsigned getRawSubclassData() const { |
1283 | uint16_t Data; |
1284 | union { |
1285 | char RawSDNodeBits[sizeof(uint16_t)]; |
1286 | SDNodeBitfields SDNodeBits; |
1287 | }; |
1288 | memcpy(&RawSDNodeBits, &this->RawSDNodeBits, sizeof(this->RawSDNodeBits)); |
1289 | SDNodeBits.HasDebugValue = 0; |
1290 | SDNodeBits.IsDivergent = false; |
1291 | memcpy(&Data, &RawSDNodeBits, sizeof(RawSDNodeBits)); |
1292 | return Data; |
1293 | } |
1294 | |
1295 | bool isVolatile() const { return MemSDNodeBits.IsVolatile; } |
1296 | bool isNonTemporal() const { return MemSDNodeBits.IsNonTemporal; } |
1297 | bool isDereferenceable() const { return MemSDNodeBits.IsDereferenceable; } |
1298 | bool isInvariant() const { return MemSDNodeBits.IsInvariant; } |
1299 | |
1300 | // Returns the offset from the location of the access. |
1301 | int64_t getSrcValueOffset() const { return MMO->getOffset(); } |
1302 | |
1303 | /// Returns the AA info that describes the dereference. |
1304 | AAMDNodes getAAInfo() const { return MMO->getAAInfo(); } |
1305 | |
1306 | /// Returns the Ranges that describes the dereference. |
1307 | const MDNode *getRanges() const { return MMO->getRanges(); } |
1308 | |
1309 | /// Returns the synchronization scope ID for this memory operation. |
1310 | SyncScope::ID getSyncScopeID() const { return MMO->getSyncScopeID(); } |
1311 | |
1312 | /// Return the atomic ordering requirements for this memory operation. For |
1313 | /// cmpxchg atomic operations, return the atomic ordering requirements when |
1314 | /// store occurs. |
1315 | AtomicOrdering getSuccessOrdering() const { |
1316 | return MMO->getSuccessOrdering(); |
1317 | } |
1318 | |
1319 | /// Return a single atomic ordering that is at least as strong as both the |
1320 | /// success and failure orderings for an atomic operation. (For operations |
1321 | /// other than cmpxchg, this is equivalent to getSuccessOrdering().) |
1322 | AtomicOrdering getMergedOrdering() const { return MMO->getMergedOrdering(); } |
1323 | |
1324 | /// Return true if the memory operation ordering is Unordered or higher. |
1325 | bool isAtomic() const { return MMO->isAtomic(); } |
1326 | |
1327 | /// Returns true if the memory operation doesn't imply any ordering |
1328 | /// constraints on surrounding memory operations beyond the normal memory |
1329 | /// aliasing rules. |
1330 | bool isUnordered() const { return MMO->isUnordered(); } |
1331 | |
1332 | /// Returns true if the memory operation is neither atomic or volatile. |
1333 | bool isSimple() const { return !isAtomic() && !isVolatile(); } |
1334 | |
1335 | /// Return the type of the in-memory value. |
1336 | EVT getMemoryVT() const { return MemoryVT; } |
1337 | |
1338 | /// Return a MachineMemOperand object describing the memory |
1339 | /// reference performed by operation. |
1340 | MachineMemOperand *getMemOperand() const { return MMO; } |
1341 | |
1342 | const MachinePointerInfo &getPointerInfo() const { |
1343 | return MMO->getPointerInfo(); |
1344 | } |
1345 | |
1346 | /// Return the address space for the associated pointer |
1347 | unsigned getAddressSpace() const { |
1348 | return getPointerInfo().getAddrSpace(); |
1349 | } |
1350 | |
1351 | /// Update this MemSDNode's MachineMemOperand information |
1352 | /// to reflect the alignment of NewMMO, if it has a greater alignment. |
1353 | /// This must only be used when the new alignment applies to all users of |
1354 | /// this MachineMemOperand. |
1355 | void refineAlignment(const MachineMemOperand *NewMMO) { |
1356 | MMO->refineAlignment(NewMMO); |
1357 | } |
1358 | |
1359 | const SDValue &getChain() const { return getOperand(0); } |
1360 | |
1361 | const SDValue &getBasePtr() const { |
1362 | switch (getOpcode()) { |
1363 | case ISD::STORE: |
1364 | case ISD::VP_STORE: |
1365 | case ISD::MSTORE: |
1366 | case ISD::VP_SCATTER: |
1367 | return getOperand(2); |
1368 | case ISD::MGATHER: |
1369 | case ISD::MSCATTER: |
1370 | return getOperand(3); |
1371 | default: |
1372 | return getOperand(1); |
1373 | } |
1374 | } |
1375 | |
1376 | // Methods to support isa and dyn_cast |
1377 | static bool classof(const SDNode *N) { |
1378 | // For some targets, we lower some target intrinsics to a MemIntrinsicNode |
1379 | // with either an intrinsic or a target opcode. |
1380 | switch (N->getOpcode()) { |
1381 | case ISD::LOAD: |
1382 | case ISD::STORE: |
1383 | case ISD::PREFETCH: |
1384 | case ISD::ATOMIC_CMP_SWAP: |
1385 | case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: |
1386 | case ISD::ATOMIC_SWAP: |
1387 | case ISD::ATOMIC_LOAD_ADD: |
1388 | case ISD::ATOMIC_LOAD_SUB: |
1389 | case ISD::ATOMIC_LOAD_AND: |
1390 | case ISD::ATOMIC_LOAD_CLR: |
1391 | case ISD::ATOMIC_LOAD_OR: |
1392 | case ISD::ATOMIC_LOAD_XOR: |
1393 | case ISD::ATOMIC_LOAD_NAND: |
1394 | case ISD::ATOMIC_LOAD_MIN: |
1395 | case ISD::ATOMIC_LOAD_MAX: |
1396 | case ISD::ATOMIC_LOAD_UMIN: |
1397 | case ISD::ATOMIC_LOAD_UMAX: |
1398 | case ISD::ATOMIC_LOAD_FADD: |
1399 | case ISD::ATOMIC_LOAD_FSUB: |
1400 | case ISD::ATOMIC_LOAD: |
1401 | case ISD::ATOMIC_STORE: |
1402 | case ISD::MLOAD: |
1403 | case ISD::MSTORE: |
1404 | case ISD::MGATHER: |
1405 | case ISD::MSCATTER: |
1406 | case ISD::VP_LOAD: |
1407 | case ISD::VP_STORE: |
1408 | case ISD::VP_GATHER: |
1409 | case ISD::VP_SCATTER: |
1410 | return true; |
1411 | default: |
1412 | return N->isMemIntrinsic() || N->isTargetMemoryOpcode(); |
1413 | } |
1414 | } |
1415 | }; |
1416 | |
1417 | /// This is an SDNode representing atomic operations. |
1418 | class AtomicSDNode : public MemSDNode { |
1419 | public: |
1420 | AtomicSDNode(unsigned Opc, unsigned Order, const DebugLoc &dl, SDVTList VTL, |
1421 | EVT MemVT, MachineMemOperand *MMO) |
1422 | : MemSDNode(Opc, Order, dl, VTL, MemVT, MMO) { |
1423 | assert(((Opc != ISD::ATOMIC_LOAD && Opc != ISD::ATOMIC_STORE) ||(static_cast <bool> (((Opc != ISD::ATOMIC_LOAD && Opc != ISD::ATOMIC_STORE) || MMO->isAtomic()) && "then why are we using an AtomicSDNode?" ) ? void (0) : __assert_fail ("((Opc != ISD::ATOMIC_LOAD && Opc != ISD::ATOMIC_STORE) || MMO->isAtomic()) && \"then why are we using an AtomicSDNode?\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/include/llvm/CodeGen/SelectionDAGNodes.h" , 1424, __extension__ __PRETTY_FUNCTION__)) |
1424 | MMO->isAtomic()) && "then why are we using an AtomicSDNode?")(static_cast <bool> (((Opc != ISD::ATOMIC_LOAD && Opc != ISD::ATOMIC_STORE) || MMO->isAtomic()) && "then why are we using an AtomicSDNode?" ) ? void (0) : __assert_fail ("((Opc != ISD::ATOMIC_LOAD && Opc != ISD::ATOMIC_STORE) || MMO->isAtomic()) && \"then why are we using an AtomicSDNode?\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/include/llvm/CodeGen/SelectionDAGNodes.h" , 1424, __extension__ __PRETTY_FUNCTION__)); |
1425 | } |
1426 | |
1427 | const SDValue &getBasePtr() const { return getOperand(1); } |
1428 | const SDValue &getVal() const { return getOperand(2); } |
1429 | |
1430 | /// Returns true if this SDNode represents cmpxchg atomic operation, false |
1431 | /// otherwise. |
1432 | bool isCompareAndSwap() const { |
1433 | unsigned Op = getOpcode(); |
1434 | return Op == ISD::ATOMIC_CMP_SWAP || |
1435 | Op == ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS; |
1436 | } |
1437 | |
1438 | /// For cmpxchg atomic operations, return the atomic ordering requirements |
1439 | /// when store does not occur. |
1440 | AtomicOrdering getFailureOrdering() const { |
1441 | assert(isCompareAndSwap() && "Must be cmpxchg operation")(static_cast <bool> (isCompareAndSwap() && "Must be cmpxchg operation" ) ? void (0) : __assert_fail ("isCompareAndSwap() && \"Must be cmpxchg operation\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/include/llvm/CodeGen/SelectionDAGNodes.h" , 1441, __extension__ __PRETTY_FUNCTION__)); |
1442 | return MMO->getFailureOrdering(); |
1443 | } |
1444 | |
1445 | // Methods to support isa and dyn_cast |
1446 | static bool classof(const SDNode *N) { |
1447 | return N->getOpcode() == ISD::ATOMIC_CMP_SWAP || |
1448 | N->getOpcode() == ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS || |
1449 | N->getOpcode() == ISD::ATOMIC_SWAP || |
1450 | N->getOpcode() == ISD::ATOMIC_LOAD_ADD || |
1451 | N->getOpcode() == ISD::ATOMIC_LOAD_SUB || |
1452 | N->getOpcode() == ISD::ATOMIC_LOAD_AND || |
1453 | N->getOpcode() == ISD::ATOMIC_LOAD_CLR || |
1454 | N->getOpcode() == ISD::ATOMIC_LOAD_OR || |
1455 | N->getOpcode() == ISD::ATOMIC_LOAD_XOR || |
1456 | N->getOpcode() == ISD::ATOMIC_LOAD_NAND || |
1457 | N->getOpcode() == ISD::ATOMIC_LOAD_MIN || |
1458 | N->getOpcode() == ISD::ATOMIC_LOAD_MAX || |
1459 | N->getOpcode() == ISD::ATOMIC_LOAD_UMIN || |
1460 | N->getOpcode() == ISD::ATOMIC_LOAD_UMAX || |
1461 | N->getOpcode() == ISD::ATOMIC_LOAD_FADD || |
1462 | N->getOpcode() == ISD::ATOMIC_LOAD_FSUB || |
1463 | N->getOpcode() == ISD::ATOMIC_LOAD || |
1464 | N->getOpcode() == ISD::ATOMIC_STORE; |
1465 | } |
1466 | }; |
1467 | |
1468 | /// This SDNode is used for target intrinsics that touch |
1469 | /// memory and need an associated MachineMemOperand. Its opcode may be |
1470 | /// INTRINSIC_VOID, INTRINSIC_W_CHAIN, PREFETCH, or a target-specific opcode |
1471 | /// with a value not less than FIRST_TARGET_MEMORY_OPCODE. |
1472 | class MemIntrinsicSDNode : public MemSDNode { |
1473 | public: |
1474 | MemIntrinsicSDNode(unsigned Opc, unsigned Order, const DebugLoc &dl, |
1475 | SDVTList VTs, EVT MemoryVT, MachineMemOperand *MMO) |
1476 | : MemSDNode(Opc, Order, dl, VTs, MemoryVT, MMO) { |
1477 | SDNodeBits.IsMemIntrinsic = true; |
1478 | } |
1479 | |
1480 | // Methods to support isa and dyn_cast |
1481 | static bool classof(const SDNode *N) { |
1482 | // We lower some target intrinsics to their target opcode |
1483 | // early a node with a target opcode can be of this class |
1484 | return N->isMemIntrinsic() || |
1485 | N->getOpcode() == ISD::PREFETCH || |
1486 | N->isTargetMemoryOpcode(); |
1487 | } |
1488 | }; |
1489 | |
1490 | /// This SDNode is used to implement the code generator |
1491 | /// support for the llvm IR shufflevector instruction. It combines elements |
1492 | /// from two input vectors into a new input vector, with the selection and |
1493 | /// ordering of elements determined by an array of integers, referred to as |
1494 | /// the shuffle mask. For input vectors of width N, mask indices of 0..N-1 |
1495 | /// refer to elements from the LHS input, and indices from N to 2N-1 the RHS. |
1496 | /// An index of -1 is treated as undef, such that the code generator may put |
1497 | /// any value in the corresponding element of the result. |
1498 | class ShuffleVectorSDNode : public SDNode { |
1499 | // The memory for Mask is owned by the SelectionDAG's OperandAllocator, and |
1500 | // is freed when the SelectionDAG object is destroyed. |
1501 | const int *Mask; |
1502 | |
1503 | protected: |
1504 | friend class SelectionDAG; |
1505 | |
1506 | ShuffleVectorSDNode(EVT VT, unsigned Order, const DebugLoc &dl, const int *M) |
1507 | : SDNode(ISD::VECTOR_SHUFFLE, Order, dl, getSDVTList(VT)), Mask(M) {} |
1508 | |
1509 | public: |
1510 | ArrayRef<int> getMask() const { |
1511 | EVT VT = getValueType(0); |
1512 | return makeArrayRef(Mask, VT.getVectorNumElements()); |
1513 | } |
1514 | |
1515 | int getMaskElt(unsigned Idx) const { |
1516 | assert(Idx < getValueType(0).getVectorNumElements() && "Idx out of range!")(static_cast <bool> (Idx < getValueType(0).getVectorNumElements () && "Idx out of range!") ? void (0) : __assert_fail ("Idx < getValueType(0).getVectorNumElements() && \"Idx out of range!\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/include/llvm/CodeGen/SelectionDAGNodes.h" , 1516, __extension__ __PRETTY_FUNCTION__)); |
1517 | return Mask[Idx]; |
1518 | } |
1519 | |
1520 | bool isSplat() const { return isSplatMask(Mask, getValueType(0)); } |
1521 | |
1522 | int getSplatIndex() const { |
1523 | assert(isSplat() && "Cannot get splat index for non-splat!")(static_cast <bool> (isSplat() && "Cannot get splat index for non-splat!" ) ? void (0) : __assert_fail ("isSplat() && \"Cannot get splat index for non-splat!\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/include/llvm/CodeGen/SelectionDAGNodes.h" , 1523, __extension__ __PRETTY_FUNCTION__)); |
1524 | EVT VT = getValueType(0); |
1525 | for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i) |
1526 | if (Mask[i] >= 0) |
1527 | return Mask[i]; |
1528 | |
1529 | // We can choose any index value here and be correct because all elements |
1530 | // are undefined. Return 0 for better potential for callers to simplify. |
1531 | return 0; |
1532 | } |
1533 | |
1534 | static bool isSplatMask(const int *Mask, EVT VT); |
1535 | |
1536 | /// Change values in a shuffle permute mask assuming |
1537 | /// the two vector operands have swapped position. |
1538 | static void commuteMask(MutableArrayRef<int> Mask) { |
1539 | unsigned NumElems = Mask.size(); |
1540 | for (unsigned i = 0; i != NumElems; ++i) { |
1541 | int idx = Mask[i]; |
1542 | if (idx < 0) |
1543 | continue; |
1544 | else if (idx < (int)NumElems) |
1545 | Mask[i] = idx + NumElems; |
1546 | else |
1547 | Mask[i] = idx - NumElems; |
1548 | } |
1549 | } |
1550 | |
1551 | static bool classof(const SDNode *N) { |
1552 | return N->getOpcode() == ISD::VECTOR_SHUFFLE; |
1553 | } |
1554 | }; |
1555 | |
1556 | class ConstantSDNode : public SDNode { |
1557 | friend class SelectionDAG; |
1558 | |
1559 | const ConstantInt *Value; |
1560 | |
1561 | ConstantSDNode(bool isTarget, bool isOpaque, const ConstantInt *val, EVT VT) |
1562 | : SDNode(isTarget ? ISD::TargetConstant : ISD::Constant, 0, DebugLoc(), |
1563 | getSDVTList(VT)), |
1564 | Value(val) { |
1565 | ConstantSDNodeBits.IsOpaque = isOpaque; |
1566 | } |
1567 | |
1568 | public: |
1569 | const ConstantInt *getConstantIntValue() const { return Value; } |
1570 | const APInt &getAPIntValue() const { return Value->getValue(); } |
1571 | uint64_t getZExtValue() const { return Value->getZExtValue(); } |
1572 | int64_t getSExtValue() const { return Value->getSExtValue(); } |
1573 | uint64_t getLimitedValue(uint64_t Limit = UINT64_MAX(18446744073709551615UL)) { |
1574 | return Value->getLimitedValue(Limit); |
1575 | } |
1576 | MaybeAlign getMaybeAlignValue() const { return Value->getMaybeAlignValue(); } |
1577 | Align getAlignValue() const { return Value->getAlignValue(); } |
1578 | |
1579 | bool isOne() const { return Value->isOne(); } |
1580 | bool isZero() const { return Value->isZero(); } |
1581 | // NOTE: This is soft-deprecated. Please use `isZero()` instead. |
1582 | bool isNullValue() const { return isZero(); } |
1583 | bool isAllOnes() const { return Value->isMinusOne(); } |
1584 | // NOTE: This is soft-deprecated. Please use `isAllOnes()` instead. |
1585 | bool isAllOnesValue() const { return isAllOnes(); } |
1586 | bool isMaxSignedValue() const { return Value->isMaxValue(true); } |
1587 | bool isMinSignedValue() const { return Value->isMinValue(true); } |
1588 | |
1589 | bool isOpaque() const { return ConstantSDNodeBits.IsOpaque; } |
1590 | |
1591 | static bool classof(const SDNode *N) { |
1592 | return N->getOpcode() == ISD::Constant || |
1593 | N->getOpcode() == ISD::TargetConstant; |
1594 | } |
1595 | }; |
1596 | |
1597 | uint64_t SDNode::getConstantOperandVal(unsigned Num) const { |
1598 | return cast<ConstantSDNode>(getOperand(Num))->getZExtValue(); |
1599 | } |
1600 | |
1601 | const APInt &SDNode::getConstantOperandAPInt(unsigned Num) const { |
1602 | return cast<ConstantSDNode>(getOperand(Num))->getAPIntValue(); |
1603 | } |
1604 | |
1605 | class ConstantFPSDNode : public SDNode { |
1606 | friend class SelectionDAG; |
1607 | |
1608 | const ConstantFP *Value; |
1609 | |
1610 | ConstantFPSDNode(bool isTarget, const ConstantFP *val, EVT VT) |
1611 | : SDNode(isTarget ? ISD::TargetConstantFP : ISD::ConstantFP, 0, |
1612 | DebugLoc(), getSDVTList(VT)), |
1613 | Value(val) {} |
1614 | |
1615 | public: |
1616 | const APFloat& getValueAPF() const { return Value->getValueAPF(); } |
1617 | const ConstantFP *getConstantFPValue() const { return Value; } |
1618 | |
1619 | /// Return true if the value is positive or negative zero. |
1620 | bool isZero() const { return Value->isZero(); } |
1621 | |
1622 | /// Return true if the value is a NaN. |
1623 | bool isNaN() const { return Value->isNaN(); } |
1624 | |
1625 | /// Return true if the value is an infinity |
1626 | bool isInfinity() const { return Value->isInfinity(); } |
1627 | |
1628 | /// Return true if the value is negative. |
1629 | bool isNegative() const { return Value->isNegative(); } |
1630 | |
1631 | /// We don't rely on operator== working on double values, as |
1632 | /// it returns true for things that are clearly not equal, like -0.0 and 0.0. |
1633 | /// As such, this method can be used to do an exact bit-for-bit comparison of |
1634 | /// two floating point values. |
1635 | |
1636 | /// We leave the version with the double argument here because it's just so |
1637 | /// convenient to write "2.0" and the like. Without this function we'd |
1638 | /// have to duplicate its logic everywhere it's called. |
1639 | bool isExactlyValue(double V) const { |
1640 | return Value->getValueAPF().isExactlyValue(V); |
1641 | } |
1642 | bool isExactlyValue(const APFloat& V) const; |
1643 | |
1644 | static bool isValueValidForType(EVT VT, const APFloat& Val); |
1645 | |
1646 | static bool classof(const SDNode *N) { |
1647 | return N->getOpcode() == ISD::ConstantFP || |
1648 | N->getOpcode() == ISD::TargetConstantFP; |
1649 | } |
1650 | }; |
1651 | |
1652 | /// Returns true if \p V is a constant integer zero. |
1653 | bool isNullConstant(SDValue V); |
1654 | |
1655 | /// Returns true if \p V is an FP constant with a value of positive zero. |
1656 | bool isNullFPConstant(SDValue V); |
1657 | |
1658 | /// Returns true if \p V is an integer constant with all bits set. |
1659 | bool isAllOnesConstant(SDValue V); |
1660 | |
1661 | /// Returns true if \p V is a constant integer one. |
1662 | bool isOneConstant(SDValue V); |
1663 | |
1664 | /// Return the non-bitcasted source operand of \p V if it exists. |
1665 | /// If \p V is not a bitcasted value, it is returned as-is. |
1666 | SDValue peekThroughBitcasts(SDValue V); |
1667 | |
1668 | /// Return the non-bitcasted and one-use source operand of \p V if it exists. |
1669 | /// If \p V is not a bitcasted one-use value, it is returned as-is. |
1670 | SDValue peekThroughOneUseBitcasts(SDValue V); |
1671 | |
1672 | /// Return the non-extracted vector source operand of \p V if it exists. |
1673 | /// If \p V is not an extracted subvector, it is returned as-is. |
1674 | SDValue peekThroughExtractSubvectors(SDValue V); |
1675 | |
1676 | /// Returns true if \p V is a bitwise not operation. Assumes that an all ones |
1677 | /// constant is canonicalized to be operand 1. |
1678 | bool isBitwiseNot(SDValue V, bool AllowUndefs = false); |
1679 | |
1680 | /// Returns the SDNode if it is a constant splat BuildVector or constant int. |
1681 | ConstantSDNode *isConstOrConstSplat(SDValue N, bool AllowUndefs = false, |
1682 | bool AllowTruncation = false); |
1683 | |
1684 | /// Returns the SDNode if it is a demanded constant splat BuildVector or |
1685 | /// constant int. |
1686 | ConstantSDNode *isConstOrConstSplat(SDValue N, const APInt &DemandedElts, |
1687 | bool AllowUndefs = false, |
1688 | bool AllowTruncation = false); |
1689 | |
1690 | /// Returns the SDNode if it is a constant splat BuildVector or constant float. |
1691 | ConstantFPSDNode *isConstOrConstSplatFP(SDValue N, bool AllowUndefs = false); |
1692 | |
1693 | /// Returns the SDNode if it is a demanded constant splat BuildVector or |
1694 | /// constant float. |
1695 | ConstantFPSDNode *isConstOrConstSplatFP(SDValue N, const APInt &DemandedElts, |
1696 | bool AllowUndefs = false); |
1697 | |
1698 | /// Return true if the value is a constant 0 integer or a splatted vector of |
1699 | /// a constant 0 integer (with no undefs by default). |
1700 | /// Build vector implicit truncation is not an issue for null values. |
1701 | bool isNullOrNullSplat(SDValue V, bool AllowUndefs = false); |
1702 | |
1703 | /// Return true if the value is a constant 1 integer or a splatted vector of a |
1704 | /// constant 1 integer (with no undefs). |
1705 | /// Does not permit build vector implicit truncation. |
1706 | bool isOneOrOneSplat(SDValue V, bool AllowUndefs = false); |
1707 | |
1708 | /// Return true if the value is a constant -1 integer or a splatted vector of a |
1709 | /// constant -1 integer (with no undefs). |
1710 | /// Does not permit build vector implicit truncation. |
1711 | bool isAllOnesOrAllOnesSplat(SDValue V, bool AllowUndefs = false); |
1712 | |
1713 | /// Return true if \p V is either a integer or FP constant. |
1714 | inline bool isIntOrFPConstant(SDValue V) { |
1715 | return isa<ConstantSDNode>(V) || isa<ConstantFPSDNode>(V); |
1716 | } |
1717 | |
1718 | class GlobalAddressSDNode : public SDNode { |
1719 | friend class SelectionDAG; |
1720 | |
1721 | const GlobalValue *TheGlobal; |
1722 | int64_t Offset; |
1723 | unsigned TargetFlags; |
1724 | |
1725 | GlobalAddressSDNode(unsigned Opc, unsigned Order, const DebugLoc &DL, |
1726 | const GlobalValue *GA, EVT VT, int64_t o, |
1727 | unsigned TF); |
1728 | |
1729 | public: |
1730 | const GlobalValue *getGlobal() const { return TheGlobal; } |
1731 | int64_t getOffset() const { return Offset; } |
1732 | unsigned getTargetFlags() const { return TargetFlags; } |
1733 | // Return the address space this GlobalAddress belongs to. |
1734 | unsigned getAddressSpace() const; |
1735 | |
1736 | static bool classof(const SDNode *N) { |
1737 | return N->getOpcode() == ISD::GlobalAddress || |
1738 | N->getOpcode() == ISD::TargetGlobalAddress || |
1739 | N->getOpcode() == ISD::GlobalTLSAddress || |
1740 | N->getOpcode() == ISD::TargetGlobalTLSAddress; |
1741 | } |
1742 | }; |
1743 | |
1744 | class FrameIndexSDNode : public SDNode { |
1745 | friend class SelectionDAG; |
1746 | |
1747 | int FI; |
1748 | |
1749 | FrameIndexSDNode(int fi, EVT VT, bool isTarg) |
1750 | : SDNode(isTarg ? ISD::TargetFrameIndex : ISD::FrameIndex, |
1751 | 0, DebugLoc(), getSDVTList(VT)), FI(fi) { |
1752 | } |
1753 | |
1754 | public: |
1755 | int getIndex() const { return FI; } |
1756 | |
1757 | static bool classof(const SDNode *N) { |
1758 | return N->getOpcode() == ISD::FrameIndex || |
1759 | N->getOpcode() == ISD::TargetFrameIndex; |
1760 | } |
1761 | }; |
1762 | |
1763 | /// This SDNode is used for LIFETIME_START/LIFETIME_END values, which indicate |
1764 | /// the offet and size that are started/ended in the underlying FrameIndex. |
1765 | class LifetimeSDNode : public SDNode { |
1766 | friend class SelectionDAG; |
1767 | int64_t Size; |
1768 | int64_t Offset; // -1 if offset is unknown. |
1769 | |
1770 | LifetimeSDNode(unsigned Opcode, unsigned Order, const DebugLoc &dl, |
1771 | SDVTList VTs, int64_t Size, int64_t Offset) |
1772 | : SDNode(Opcode, Order, dl, VTs), Size(Size), Offset(Offset) {} |
1773 | public: |
1774 | int64_t getFrameIndex() const { |
1775 | return cast<FrameIndexSDNode>(getOperand(1))->getIndex(); |
1776 | } |
1777 | |
1778 | bool hasOffset() const { return Offset >= 0; } |
1779 | int64_t getOffset() const { |
1780 | assert(hasOffset() && "offset is unknown")(static_cast <bool> (hasOffset() && "offset is unknown" ) ? void (0) : __assert_fail ("hasOffset() && \"offset is unknown\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/include/llvm/CodeGen/SelectionDAGNodes.h" , 1780, __extension__ __PRETTY_FUNCTION__)); |
1781 | return Offset; |
1782 | } |
1783 | int64_t getSize() const { |
1784 | assert(hasOffset() && "offset is unknown")(static_cast <bool> (hasOffset() && "offset is unknown" ) ? void (0) : __assert_fail ("hasOffset() && \"offset is unknown\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/include/llvm/CodeGen/SelectionDAGNodes.h" , 1784, __extension__ __PRETTY_FUNCTION__)); |
1785 | return Size; |
1786 | } |
1787 | |
1788 | // Methods to support isa and dyn_cast |
1789 | static bool classof(const SDNode *N) { |
1790 | return N->getOpcode() == ISD::LIFETIME_START || |
1791 | N->getOpcode() == ISD::LIFETIME_END; |
1792 | } |
1793 | }; |
1794 | |
1795 | /// This SDNode is used for PSEUDO_PROBE values, which are the function guid and |
1796 | /// the index of the basic block being probed. A pseudo probe serves as a place |
1797 | /// holder and will be removed at the end of compilation. It does not have any |
1798 | /// operand because we do not want the instruction selection to deal with any. |
1799 | class PseudoProbeSDNode : public SDNode { |
1800 | friend class SelectionDAG; |
1801 | uint64_t Guid; |
1802 | uint64_t Index; |
1803 | uint32_t Attributes; |
1804 | |
1805 | PseudoProbeSDNode(unsigned Opcode, unsigned Order, const DebugLoc &Dl, |
1806 | SDVTList VTs, uint64_t Guid, uint64_t Index, uint32_t Attr) |
1807 | : SDNode(Opcode, Order, Dl, VTs), Guid(Guid), Index(Index), |
1808 | Attributes(Attr) {} |
1809 | |
1810 | public: |
1811 | uint64_t getGuid() const { return Guid; } |
1812 | uint64_t getIndex() const { return Index; } |
1813 | uint32_t getAttributes() const { return Attributes; } |
1814 | |
1815 | // Methods to support isa and dyn_cast |
1816 | static bool classof(const SDNode *N) { |
1817 | return N->getOpcode() == ISD::PSEUDO_PROBE; |
1818 | } |
1819 | }; |
1820 | |
1821 | class JumpTableSDNode : public SDNode { |
1822 | friend class SelectionDAG; |
1823 | |
1824 | int JTI; |
1825 | unsigned TargetFlags; |
1826 | |
1827 | JumpTableSDNode(int jti, EVT VT, bool isTarg, unsigned TF) |
1828 | : SDNode(isTarg ? ISD::TargetJumpTable : ISD::JumpTable, |
1829 | 0, DebugLoc(), getSDVTList(VT)), JTI(jti), TargetFlags(TF) { |
1830 | } |
1831 | |
1832 | public: |
1833 | int getIndex() const { return JTI; } |
1834 | unsigned getTargetFlags() const { return TargetFlags; } |
1835 | |
1836 | static bool classof(const SDNode *N) { |
1837 | return N->getOpcode() == ISD::JumpTable || |
1838 | N->getOpcode() == ISD::TargetJumpTable; |
1839 | } |
1840 | }; |
1841 | |
1842 | class ConstantPoolSDNode : public SDNode { |
1843 | friend class SelectionDAG; |
1844 | |
1845 | union { |
1846 | const Constant *ConstVal; |
1847 | MachineConstantPoolValue *MachineCPVal; |
1848 | } Val; |
1849 | int Offset; // It's a MachineConstantPoolValue if top bit is set. |
1850 | Align Alignment; // Minimum alignment requirement of CP. |
1851 | unsigned TargetFlags; |
1852 | |
1853 | ConstantPoolSDNode(bool isTarget, const Constant *c, EVT VT, int o, |
1854 | Align Alignment, unsigned TF) |
1855 | : SDNode(isTarget ? ISD::TargetConstantPool : ISD::ConstantPool, 0, |
1856 | DebugLoc(), getSDVTList(VT)), |
1857 | Offset(o), Alignment(Alignment), TargetFlags(TF) { |
1858 | assert(Offset >= 0 && "Offset is too large")(static_cast <bool> (Offset >= 0 && "Offset is too large" ) ? void (0) : __assert_fail ("Offset >= 0 && \"Offset is too large\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/include/llvm/CodeGen/SelectionDAGNodes.h" , 1858, __extension__ __PRETTY_FUNCTION__)); |
1859 | Val.ConstVal = c; |
1860 | } |
1861 | |
1862 | ConstantPoolSDNode(bool isTarget, MachineConstantPoolValue *v, EVT VT, int o, |
1863 | Align Alignment, unsigned TF) |
1864 | : SDNode(isTarget ? ISD::TargetConstantPool : ISD::ConstantPool, 0, |
1865 | DebugLoc(), getSDVTList(VT)), |
1866 | Offset(o), Alignment(Alignment), TargetFlags(TF) { |
1867 | assert(Offset >= 0 && "Offset is too large")(static_cast <bool> (Offset >= 0 && "Offset is too large" ) ? void (0) : __assert_fail ("Offset >= 0 && \"Offset is too large\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/include/llvm/CodeGen/SelectionDAGNodes.h" , 1867, __extension__ __PRETTY_FUNCTION__)); |
1868 | Val.MachineCPVal = v; |
1869 | Offset |= 1 << (sizeof(unsigned)*CHAR_BIT8-1); |
1870 | } |
1871 | |
1872 | public: |
1873 | bool isMachineConstantPoolEntry() const { |
1874 | return Offset < 0; |
1875 | } |
1876 | |
1877 | const Constant *getConstVal() const { |
1878 | assert(!isMachineConstantPoolEntry() && "Wrong constantpool type")(static_cast <bool> (!isMachineConstantPoolEntry() && "Wrong constantpool type") ? void (0) : __assert_fail ("!isMachineConstantPoolEntry() && \"Wrong constantpool type\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/include/llvm/CodeGen/SelectionDAGNodes.h" , 1878, __extension__ __PRETTY_FUNCTION__)); |
1879 | return Val.ConstVal; |
1880 | } |
1881 | |
1882 | MachineConstantPoolValue *getMachineCPVal() const { |
1883 | assert(isMachineConstantPoolEntry() && "Wrong constantpool type")(static_cast <bool> (isMachineConstantPoolEntry() && "Wrong constantpool type") ? void (0) : __assert_fail ("isMachineConstantPoolEntry() && \"Wrong constantpool type\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/include/llvm/CodeGen/SelectionDAGNodes.h" , 1883, __extension__ __PRETTY_FUNCTION__)); |
1884 | return Val.MachineCPVal; |
1885 | } |
1886 | |
1887 | int getOffset() const { |
1888 | return Offset & ~(1 << (sizeof(unsigned)*CHAR_BIT8-1)); |
1889 | } |
1890 | |
1891 | // Return the alignment of this constant pool object, which is either 0 (for |
1892 | // default alignment) or the desired value. |
1893 | Align getAlign() const { return Alignment; } |
1894 | unsigned getTargetFlags() const { return TargetFlags; } |
1895 | |
1896 | Type *getType() const; |
1897 | |
1898 | static bool classof(const SDNode *N) { |
1899 | return N->getOpcode() == ISD::ConstantPool || |
1900 | N->getOpcode() == ISD::TargetConstantPool; |
1901 | } |
1902 | }; |
1903 | |
1904 | /// Completely target-dependent object reference. |
1905 | class TargetIndexSDNode : public SDNode { |
1906 | friend class SelectionDAG; |
1907 | |
1908 | unsigned TargetFlags; |
1909 | int Index; |
1910 | int64_t Offset; |
1911 | |
1912 | public: |
1913 | TargetIndexSDNode(int Idx, EVT VT, int64_t Ofs, unsigned TF) |
1914 | : SDNode(ISD::TargetIndex, 0, DebugLoc(), getSDVTList(VT)), |
1915 | TargetFlags(TF), Index(Idx), Offset(Ofs) {} |
1916 | |
1917 | unsigned getTargetFlags() const { return TargetFlags; } |
1918 | int getIndex() const { return Index; } |
1919 | int64_t getOffset() const { return Offset; } |
1920 | |
1921 | static bool classof(const SDNode *N) { |
1922 | return N->getOpcode() == ISD::TargetIndex; |
1923 | } |
1924 | }; |
1925 | |
1926 | class BasicBlockSDNode : public SDNode { |
1927 | friend class SelectionDAG; |
1928 | |
1929 | MachineBasicBlock *MBB; |
1930 | |
1931 | /// Debug info is meaningful and potentially useful here, but we create |
1932 | /// blocks out of order when they're jumped to, which makes it a bit |
1933 | /// harder. Let's see if we need it first. |
1934 | explicit BasicBlockSDNode(MachineBasicBlock *mbb) |
1935 | : SDNode(ISD::BasicBlock, 0, DebugLoc(), getSDVTList(MVT::Other)), MBB(mbb) |
1936 | {} |
1937 | |
1938 | public: |
1939 | MachineBasicBlock *getBasicBlock() const { return MBB; } |
1940 | |
1941 | static bool classof(const SDNode *N) { |
1942 | return N->getOpcode() == ISD::BasicBlock; |
1943 | } |
1944 | }; |
1945 | |
1946 | /// A "pseudo-class" with methods for operating on BUILD_VECTORs. |
1947 | class BuildVectorSDNode : public SDNode { |
1948 | public: |
1949 | // These are constructed as SDNodes and then cast to BuildVectorSDNodes. |
1950 | explicit BuildVectorSDNode() = delete; |
1951 | |
1952 | /// Check if this is a constant splat, and if so, find the |
1953 | /// smallest element size that splats the vector. If MinSplatBits is |
1954 | /// nonzero, the element size must be at least that large. Note that the |
1955 | /// splat element may be the entire vector (i.e., a one element vector). |
1956 | /// Returns the splat element value in SplatValue. Any undefined bits in |
1957 | /// that value are zero, and the corresponding bits in the SplatUndef mask |
1958 | /// are set. The SplatBitSize value is set to the splat element size in |
1959 | /// bits. HasAnyUndefs is set to true if any bits in the vector are |
1960 | /// undefined. isBigEndian describes the endianness of the target. |
1961 | bool isConstantSplat(APInt &SplatValue, APInt &SplatUndef, |
1962 | unsigned &SplatBitSize, bool &HasAnyUndefs, |
1963 | unsigned MinSplatBits = 0, |
1964 | bool isBigEndian = false) const; |
1965 | |
1966 | /// Returns the demanded splatted value or a null value if this is not a |
1967 | /// splat. |
1968 | /// |
1969 | /// The DemandedElts mask indicates the elements that must be in the splat. |
1970 | /// If passed a non-null UndefElements bitvector, it will resize it to match |
1971 | /// the vector width and set the bits where elements are undef. |
1972 | SDValue getSplatValue(const APInt &DemandedElts, |
1973 | BitVector *UndefElements = nullptr) const; |
1974 | |
1975 | /// Returns the splatted value or a null value if this is not a splat. |
1976 | /// |
1977 | /// If passed a non-null UndefElements bitvector, it will resize it to match |
1978 | /// the vector width and set the bits where elements are undef. |
1979 | SDValue getSplatValue(BitVector *UndefElements = nullptr) const; |
1980 | |
1981 | /// Find the shortest repeating sequence of values in the build vector. |
1982 | /// |
1983 | /// e.g. { u, X, u, X, u, u, X, u } -> { X } |
1984 | /// { X, Y, u, Y, u, u, X, u } -> { X, Y } |
1985 | /// |
1986 | /// Currently this must be a power-of-2 build vector. |
1987 | /// The DemandedElts mask indicates the elements that must be present, |
1988 | /// undemanded elements in Sequence may be null (SDValue()). If passed a |
1989 | /// non-null UndefElements bitvector, it will resize it to match the original |
1990 | /// vector width and set the bits where elements are undef. If result is |
1991 | /// false, Sequence will be empty. |
1992 | bool getRepeatedSequence(const APInt &DemandedElts, |
1993 | SmallVectorImpl<SDValue> &Sequence, |
1994 | BitVector *UndefElements = nullptr) const; |
1995 | |
1996 | /// Find the shortest repeating sequence of values in the build vector. |
1997 | /// |
1998 | /// e.g. { u, X, u, X, u, u, X, u } -> { X } |
1999 | /// { X, Y, u, Y, u, u, X, u } -> { X, Y } |
2000 | /// |
2001 | /// Currently this must be a power-of-2 build vector. |
2002 | /// If passed a non-null UndefElements bitvector, it will resize it to match |
2003 | /// the original vector width and set the bits where elements are undef. |
2004 | /// If result is false, Sequence will be empty. |
2005 | bool getRepeatedSequence(SmallVectorImpl<SDValue> &Sequence, |
2006 | BitVector *UndefElements = nullptr) const; |
2007 | |
2008 | /// Returns the demanded splatted constant or null if this is not a constant |
2009 | /// splat. |
2010 | /// |
2011 | /// The DemandedElts mask indicates the elements that must be in the splat. |
2012 | /// If passed a non-null UndefElements bitvector, it will resize it to match |
2013 | /// the vector width and set the bits where elements are undef. |
2014 | ConstantSDNode * |
2015 | getConstantSplatNode(const APInt &DemandedElts, |
2016 | BitVector *UndefElements = nullptr) const; |
2017 | |
2018 | /// Returns the splatted constant or null if this is not a constant |
2019 | /// splat. |
2020 | /// |
2021 | /// If passed a non-null UndefElements bitvector, it will resize it to match |
2022 | /// the vector width and set the bits where elements are undef. |
2023 | ConstantSDNode * |
2024 | getConstantSplatNode(BitVector *UndefElements = nullptr) const; |
2025 | |
2026 | /// Returns the demanded splatted constant FP or null if this is not a |
2027 | /// constant FP splat. |
2028 | /// |
2029 | /// The DemandedElts mask indicates the elements that must be in the splat. |
2030 | /// If passed a non-null UndefElements bitvector, it will resize it to match |
2031 | /// the vector width and set the bits where elements are undef. |
2032 | ConstantFPSDNode * |
2033 | getConstantFPSplatNode(const APInt &DemandedElts, |
2034 | BitVector *UndefElements = nullptr) const; |
2035 | |
2036 | /// Returns the splatted constant FP or null if this is not a constant |
2037 | /// FP splat. |
2038 | /// |
2039 | /// If passed a non-null UndefElements bitvector, it will resize it to match |
2040 | /// the vector width and set the bits where elements are undef. |
2041 | ConstantFPSDNode * |
2042 | getConstantFPSplatNode(BitVector *UndefElements = nullptr) const; |
2043 | |
2044 | /// If this is a constant FP splat and the splatted constant FP is an |
2045 | /// exact power or 2, return the log base 2 integer value. Otherwise, |
2046 | /// return -1. |
2047 | /// |
2048 | /// The BitWidth specifies the necessary bit precision. |
2049 | int32_t getConstantFPSplatPow2ToLog2Int(BitVector *UndefElements, |
2050 | uint32_t BitWidth) const; |
2051 | |
2052 | /// Extract the raw bit data from a build vector of Undef, Constant or |
2053 | /// ConstantFP node elements. Each raw bit element will be \p |
2054 | /// DstEltSizeInBits wide, undef elements are treated as zero, and entirely |
2055 | /// undefined elements are flagged in \p UndefElements. |
2056 | bool getConstantRawBits(bool IsLittleEndian, unsigned DstEltSizeInBits, |
2057 | SmallVectorImpl<APInt> &RawBitElements, |
2058 | BitVector &UndefElements) const; |
2059 | |
2060 | bool isConstant() const; |
2061 | |
2062 | static bool classof(const SDNode *N) { |
2063 | return N->getOpcode() == ISD::BUILD_VECTOR; |
2064 | } |
2065 | }; |
2066 | |
2067 | /// An SDNode that holds an arbitrary LLVM IR Value. This is |
2068 | /// used when the SelectionDAG needs to make a simple reference to something |
2069 | /// in the LLVM IR representation. |
2070 | /// |
2071 | class SrcValueSDNode : public SDNode { |
2072 | friend class SelectionDAG; |
2073 | |
2074 | const Value *V; |
2075 | |
2076 | /// Create a SrcValue for a general value. |
2077 | explicit SrcValueSDNode(const Value *v) |
2078 | : SDNode(ISD::SRCVALUE, 0, DebugLoc(), getSDVTList(MVT::Other)), V(v) {} |
2079 | |
2080 | public: |
2081 | /// Return the contained Value. |
2082 | const Value *getValue() const { return V; } |
2083 | |
2084 | static bool classof(const SDNode *N) { |
2085 | return N->getOpcode() == ISD::SRCVALUE; |
2086 | } |
2087 | }; |
2088 | |
2089 | class MDNodeSDNode : public SDNode { |
2090 | friend class SelectionDAG; |
2091 | |
2092 | const MDNode *MD; |
2093 | |
2094 | explicit MDNodeSDNode(const MDNode *md) |
2095 | : SDNode(ISD::MDNODE_SDNODE, 0, DebugLoc(), getSDVTList(MVT::Other)), MD(md) |
2096 | {} |
2097 | |
2098 | public: |
2099 | const MDNode *getMD() const { return MD; } |
2100 | |
2101 | static bool classof(const SDNode *N) { |
2102 | return N->getOpcode() == ISD::MDNODE_SDNODE; |
2103 | } |
2104 | }; |
2105 | |
2106 | class RegisterSDNode : public SDNode { |
2107 | friend class SelectionDAG; |
2108 | |
2109 | Register Reg; |
2110 | |
2111 | RegisterSDNode(Register reg, EVT VT) |
2112 | : SDNode(ISD::Register, 0, DebugLoc(), getSDVTList(VT)), Reg(reg) {} |
2113 | |
2114 | public: |
2115 | Register getReg() const { return Reg; } |
2116 | |
2117 | static bool classof(const SDNode *N) { |
2118 | return N->getOpcode() == ISD::Register; |
2119 | } |
2120 | }; |
2121 | |
2122 | class RegisterMaskSDNode : public SDNode { |
2123 | friend class SelectionDAG; |
2124 | |
2125 | // The memory for RegMask is not owned by the node. |
2126 | const uint32_t *RegMask; |
2127 | |
2128 | RegisterMaskSDNode(const uint32_t *mask) |
2129 | : SDNode(ISD::RegisterMask, 0, DebugLoc(), getSDVTList(MVT::Untyped)), |
2130 | RegMask(mask) {} |
2131 | |
2132 | public: |
2133 | const uint32_t *getRegMask() const { return RegMask; } |
2134 | |
2135 | static bool classof(const SDNode *N) { |
2136 | return N->getOpcode() == ISD::RegisterMask; |
2137 | } |
2138 | }; |
2139 | |
2140 | class BlockAddressSDNode : public SDNode { |
2141 | friend class SelectionDAG; |
2142 | |
2143 | const BlockAddress *BA; |
2144 | int64_t Offset; |
2145 | unsigned TargetFlags; |
2146 | |
2147 | BlockAddressSDNode(unsigned NodeTy, EVT VT, const BlockAddress *ba, |
2148 | int64_t o, unsigned Flags) |
2149 | : SDNode(NodeTy, 0, DebugLoc(), getSDVTList(VT)), |
2150 | BA(ba), Offset(o), TargetFlags(Flags) {} |
2151 | |
2152 | public: |
2153 | const BlockAddress *getBlockAddress() const { return BA; } |
2154 | int64_t getOffset() const { return Offset; } |
2155 | unsigned getTargetFlags() const { return TargetFlags; } |
2156 | |
2157 | static bool classof(const SDNode *N) { |
2158 | return N->getOpcode() == ISD::BlockAddress || |
2159 | N->getOpcode() == ISD::TargetBlockAddress; |
2160 | } |
2161 | }; |
2162 | |
2163 | class LabelSDNode : public SDNode { |
2164 | friend class SelectionDAG; |
2165 | |
2166 | MCSymbol *Label; |
2167 | |
2168 | LabelSDNode(unsigned Opcode, unsigned Order, const DebugLoc &dl, MCSymbol *L) |
2169 | : SDNode(Opcode, Order, dl, getSDVTList(MVT::Other)), Label(L) { |
2170 | assert(LabelSDNode::classof(this) && "not a label opcode")(static_cast <bool> (LabelSDNode::classof(this) && "not a label opcode") ? void (0) : __assert_fail ("LabelSDNode::classof(this) && \"not a label opcode\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/include/llvm/CodeGen/SelectionDAGNodes.h" , 2170, __extension__ __PRETTY_FUNCTION__)); |
2171 | } |
2172 | |
2173 | public: |
2174 | MCSymbol *getLabel() const { return Label; } |
2175 | |
2176 | static bool classof(const SDNode *N) { |
2177 | return N->getOpcode() == ISD::EH_LABEL || |
2178 | N->getOpcode() == ISD::ANNOTATION_LABEL; |
2179 | } |
2180 | }; |
2181 | |
2182 | class ExternalSymbolSDNode : public SDNode { |
2183 | friend class SelectionDAG; |
2184 | |
2185 | const char *Symbol; |
2186 | unsigned TargetFlags; |
2187 | |
2188 | ExternalSymbolSDNode(bool isTarget, const char *Sym, unsigned TF, EVT VT) |
2189 | : SDNode(isTarget ? ISD::TargetExternalSymbol : ISD::ExternalSymbol, 0, |
2190 | DebugLoc(), getSDVTList(VT)), |
2191 | Symbol(Sym), TargetFlags(TF) {} |
2192 | |
2193 | public: |
2194 | const char *getSymbol() const { return Symbol; } |
2195 | unsigned getTargetFlags() const { return TargetFlags; } |
2196 | |
2197 | static bool classof(const SDNode *N) { |
2198 | return N->getOpcode() == ISD::ExternalSymbol || |
2199 | N->getOpcode() == ISD::TargetExternalSymbol; |
2200 | } |
2201 | }; |
2202 | |
2203 | class MCSymbolSDNode : public SDNode { |
2204 | friend class SelectionDAG; |
2205 | |
2206 | MCSymbol *Symbol; |
2207 | |
2208 | MCSymbolSDNode(MCSymbol *Symbol, EVT VT) |
2209 | : SDNode(ISD::MCSymbol, 0, DebugLoc(), getSDVTList(VT)), Symbol(Symbol) {} |
2210 | |
2211 | public: |
2212 | MCSymbol *getMCSymbol() const { return Symbol; } |
2213 | |
2214 | static bool classof(const SDNode *N) { |
2215 | return N->getOpcode() == ISD::MCSymbol; |
2216 | } |
2217 | }; |
2218 | |
2219 | class CondCodeSDNode : public SDNode { |
2220 | friend class SelectionDAG; |
2221 | |
2222 | ISD::CondCode Condition; |
2223 | |
2224 | explicit CondCodeSDNode(ISD::CondCode Cond) |
2225 | : SDNode(ISD::CONDCODE, 0, DebugLoc(), getSDVTList(MVT::Other)), |
2226 | Condition(Cond) {} |
2227 | |
2228 | public: |
2229 | ISD::CondCode get() const { return Condition; } |
2230 | |
2231 | static bool classof(const SDNode *N) { |
2232 | return N->getOpcode() == ISD::CONDCODE; |
2233 | } |
2234 | }; |
2235 | |
2236 | /// This class is used to represent EVT's, which are used |
2237 | /// to parameterize some operations. |
2238 | class VTSDNode : public SDNode { |
2239 | friend class SelectionDAG; |
2240 | |
2241 | EVT ValueType; |
2242 | |
2243 | explicit VTSDNode(EVT VT) |
2244 | : SDNode(ISD::VALUETYPE, 0, DebugLoc(), getSDVTList(MVT::Other)), |
2245 | ValueType(VT) {} |
2246 | |
2247 | public: |
2248 | EVT getVT() const { return ValueType; } |
2249 | |
2250 | static bool classof(const SDNode *N) { |
2251 | return N->getOpcode() == ISD::VALUETYPE; |
2252 | } |
2253 | }; |
2254 | |
2255 | /// Base class for LoadSDNode and StoreSDNode |
2256 | class LSBaseSDNode : public MemSDNode { |
2257 | public: |
2258 | LSBaseSDNode(ISD::NodeType NodeTy, unsigned Order, const DebugLoc &dl, |
2259 | SDVTList VTs, ISD::MemIndexedMode AM, EVT MemVT, |
2260 | MachineMemOperand *MMO) |
2261 | : MemSDNode(NodeTy, Order, dl, VTs, MemVT, MMO) { |
2262 | LSBaseSDNodeBits.AddressingMode = AM; |
2263 | assert(getAddressingMode() == AM && "Value truncated")(static_cast <bool> (getAddressingMode() == AM && "Value truncated") ? void (0) : __assert_fail ("getAddressingMode() == AM && \"Value truncated\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/include/llvm/CodeGen/SelectionDAGNodes.h" , 2263, __extension__ __PRETTY_FUNCTION__)); |
2264 | } |
2265 | |
2266 | const SDValue &getOffset() const { |
2267 | return getOperand(getOpcode() == ISD::LOAD ? 2 : 3); |
2268 | } |
2269 | |
2270 | /// Return the addressing mode for this load or store: |
2271 | /// unindexed, pre-inc, pre-dec, post-inc, or post-dec. |
2272 | ISD::MemIndexedMode getAddressingMode() const { |
2273 | return static_cast<ISD::MemIndexedMode>(LSBaseSDNodeBits.AddressingMode); |
2274 | } |
2275 | |
2276 | /// Return true if this is a pre/post inc/dec load/store. |
2277 | bool isIndexed() const { return getAddressingMode() != ISD::UNINDEXED; } |
2278 | |
2279 | /// Return true if this is NOT a pre/post inc/dec load/store. |
2280 | bool isUnindexed() const { return getAddressingMode() == ISD::UNINDEXED; } |
2281 | |
2282 | static bool classof(const SDNode *N) { |
2283 | return N->getOpcode() == ISD::LOAD || |
2284 | N->getOpcode() == ISD::STORE; |
2285 | } |
2286 | }; |
2287 | |
2288 | /// This class is used to represent ISD::LOAD nodes. |
2289 | class LoadSDNode : public LSBaseSDNode { |
2290 | friend class SelectionDAG; |
2291 | |
2292 | LoadSDNode(unsigned Order, const DebugLoc &dl, SDVTList VTs, |
2293 | ISD::MemIndexedMode AM, ISD::LoadExtType ETy, EVT MemVT, |
2294 | MachineMemOperand *MMO) |
2295 | : LSBaseSDNode(ISD::LOAD, Order, dl, VTs, AM, MemVT, MMO) { |
2296 | LoadSDNodeBits.ExtTy = ETy; |
2297 | assert(readMem() && "Load MachineMemOperand is not a load!")(static_cast <bool> (readMem() && "Load MachineMemOperand is not a load!" ) ? void (0) : __assert_fail ("readMem() && \"Load MachineMemOperand is not a load!\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/include/llvm/CodeGen/SelectionDAGNodes.h" , 2297, __extension__ __PRETTY_FUNCTION__)); |
2298 | assert(!writeMem() && "Load MachineMemOperand is a store!")(static_cast <bool> (!writeMem() && "Load MachineMemOperand is a store!" ) ? void (0) : __assert_fail ("!writeMem() && \"Load MachineMemOperand is a store!\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/include/llvm/CodeGen/SelectionDAGNodes.h" , 2298, __extension__ __PRETTY_FUNCTION__)); |
2299 | } |
2300 | |
2301 | public: |
2302 | /// Return whether this is a plain node, |
2303 | /// or one of the varieties of value-extending loads. |
2304 | ISD::LoadExtType getExtensionType() const { |
2305 | return static_cast<ISD::LoadExtType>(LoadSDNodeBits.ExtTy); |
2306 | } |
2307 | |
2308 | const SDValue &getBasePtr() const { return getOperand(1); } |
2309 | const SDValue &getOffset() const { return getOperand(2); } |
2310 | |
2311 | static bool classof(const SDNode *N) { |
2312 | return N->getOpcode() == ISD::LOAD; |
2313 | } |
2314 | }; |
2315 | |
2316 | /// This class is used to represent ISD::STORE nodes. |
2317 | class StoreSDNode : public LSBaseSDNode { |
2318 | friend class SelectionDAG; |
2319 | |
2320 | StoreSDNode(unsigned Order, const DebugLoc &dl, SDVTList VTs, |
2321 | ISD::MemIndexedMode AM, bool isTrunc, EVT MemVT, |
2322 | MachineMemOperand *MMO) |
2323 | : LSBaseSDNode(ISD::STORE, Order, dl, VTs, AM, MemVT, MMO) { |
2324 | StoreSDNodeBits.IsTruncating = isTrunc; |
2325 | assert(!readMem() && "Store MachineMemOperand is a load!")(static_cast <bool> (!readMem() && "Store MachineMemOperand is a load!" ) ? void (0) : __assert_fail ("!readMem() && \"Store MachineMemOperand is a load!\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/include/llvm/CodeGen/SelectionDAGNodes.h" , 2325, __extension__ __PRETTY_FUNCTION__)); |
2326 | assert(writeMem() && "Store MachineMemOperand is not a store!")(static_cast <bool> (writeMem() && "Store MachineMemOperand is not a store!" ) ? void (0) : __assert_fail ("writeMem() && \"Store MachineMemOperand is not a store!\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/include/llvm/CodeGen/SelectionDAGNodes.h" , 2326, __extension__ __PRETTY_FUNCTION__)); |
2327 | } |
2328 | |
2329 | public: |
2330 | /// Return true if the op does a truncation before store. |
2331 | /// For integers this is the same as doing a TRUNCATE and storing the result. |
2332 | /// For floats, it is the same as doing an FP_ROUND and storing the result. |
2333 | bool isTruncatingStore() const { return StoreSDNodeBits.IsTruncating; } |
2334 | void setTruncatingStore(bool Truncating) { |
2335 | StoreSDNodeBits.IsTruncating = Truncating; |
2336 | } |
2337 | |
2338 | const SDValue &getValue() const { return getOperand(1); } |
2339 | const SDValue &getBasePtr() const { return getOperand(2); } |
2340 | const SDValue &getOffset() const { return getOperand(3); } |
2341 | |
2342 | static bool classof(const SDNode *N) { |
2343 | return N->getOpcode() == ISD::STORE; |
2344 | } |
2345 | }; |
2346 | |
2347 | /// This base class is used to represent VP_LOAD and VP_STORE nodes |
2348 | class VPLoadStoreSDNode : public MemSDNode { |
2349 | public: |
2350 | friend class SelectionDAG; |
2351 | |
2352 | VPLoadStoreSDNode(ISD::NodeType NodeTy, unsigned Order, const DebugLoc &dl, |
2353 | SDVTList VTs, ISD::MemIndexedMode AM, EVT MemVT, |
2354 | MachineMemOperand *MMO) |
2355 | : MemSDNode(NodeTy, Order, dl, VTs, MemVT, MMO) { |
2356 | LSBaseSDNodeBits.AddressingMode = AM; |
2357 | assert(getAddressingMode() == AM && "Value truncated")(static_cast <bool> (getAddressingMode() == AM && "Value truncated") ? void (0) : __assert_fail ("getAddressingMode() == AM && \"Value truncated\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/include/llvm/CodeGen/SelectionDAGNodes.h" , 2357, __extension__ __PRETTY_FUNCTION__)); |
2358 | } |
2359 | |
2360 | // VPLoadSDNode (Chain, Ptr, Offset, Mask, EVL) |
2361 | // VPStoreSDNode (Chain, Data, Ptr, Offset, Mask, EVL) |
2362 | // Mask is a vector of i1 elements; |
2363 | // the type of EVL is TLI.getVPExplicitVectorLengthTy(). |
2364 | const SDValue &getOffset() const { |
2365 | return getOperand(getOpcode() == ISD::VP_LOAD ? 2 : 3); |
2366 | } |
2367 | const SDValue &getBasePtr() const { |
2368 | return getOperand(getOpcode() == ISD::VP_LOAD ? 1 : 2); |
2369 | } |
2370 | const SDValue &getMask() const { |
2371 | return getOperand(getOpcode() == ISD::VP_LOAD ? 3 : 4); |
2372 | } |
2373 | const SDValue &getVectorLength() const { |
2374 | return getOperand(getOpcode() == ISD::VP_LOAD ? 4 : 5); |
2375 | } |
2376 | |
2377 | /// Return the addressing mode for this load or store: |
2378 | /// unindexed, pre-inc, pre-dec, post-inc, or post-dec. |
2379 | ISD::MemIndexedMode getAddressingMode() const { |
2380 | return static_cast<ISD::MemIndexedMode>(LSBaseSDNodeBits.AddressingMode); |
2381 | } |
2382 | |
2383 | /// Return true if this is a pre/post inc/dec load/store. |
2384 | bool isIndexed() const { return getAddressingMode() != ISD::UNINDEXED; } |
2385 | |
2386 | /// Return true if this is NOT a pre/post inc/dec load/store. |
2387 | bool isUnindexed() const { return getAddressingMode() == ISD::UNINDEXED; } |
2388 | |
2389 | static bool classof(const SDNode *N) { |
2390 | return N->getOpcode() == ISD::VP_LOAD || N->getOpcode() == ISD::VP_STORE; |
2391 | } |
2392 | }; |
2393 | |
2394 | /// This class is used to represent a VP_LOAD node |
2395 | class VPLoadSDNode : public VPLoadStoreSDNode { |
2396 | public: |
2397 | friend class SelectionDAG; |
2398 | |
2399 | VPLoadSDNode(unsigned Order, const DebugLoc &dl, SDVTList VTs, |
2400 | ISD::MemIndexedMode AM, ISD::LoadExtType ETy, bool isExpanding, |
2401 | EVT MemVT, MachineMemOperand *MMO) |
2402 | : VPLoadStoreSDNode(ISD::VP_LOAD, Order, dl, VTs, AM, MemVT, MMO) { |
2403 | LoadSDNodeBits.ExtTy = ETy; |
2404 | LoadSDNodeBits.IsExpanding = isExpanding; |
2405 | } |
2406 | |
2407 | ISD::LoadExtType getExtensionType() const { |
2408 | return static_cast<ISD::LoadExtType>(LoadSDNodeBits.ExtTy); |
2409 | } |
2410 | |
2411 | const SDValue &getBasePtr() const { return getOperand(1); } |
2412 | const SDValue &getOffset() const { return getOperand(2); } |
2413 | const SDValue &getMask() const { return getOperand(3); } |
2414 | const SDValue &getVectorLength() const { return getOperand(4); } |
2415 | |
2416 | static bool classof(const SDNode *N) { |
2417 | return N->getOpcode() == ISD::VP_LOAD; |
2418 | } |
2419 | bool isExpandingLoad() const { return LoadSDNodeBits.IsExpanding; } |
2420 | }; |
2421 | |
2422 | /// This class is used to represent a VP_STORE node |
2423 | class VPStoreSDNode : public VPLoadStoreSDNode { |
2424 | public: |
2425 | friend class SelectionDAG; |
2426 | |
2427 | VPStoreSDNode(unsigned Order, const DebugLoc &dl, SDVTList VTs, |
2428 | ISD::MemIndexedMode AM, bool isTrunc, bool isCompressing, |
2429 | EVT MemVT, MachineMemOperand *MMO) |
2430 | : VPLoadStoreSDNode(ISD::VP_STORE, Order, dl, VTs, AM, MemVT, MMO) { |
2431 | StoreSDNodeBits.IsTruncating = isTrunc; |
2432 | StoreSDNodeBits.IsCompressing = isCompressing; |
2433 | } |
2434 | |
2435 | /// Return true if this is a truncating store. |
2436 | /// For integers this is the same as doing a TRUNCATE and storing the result. |
2437 | /// For floats, it is the same as doing an FP_ROUND and storing the result. |
2438 | bool isTruncatingStore() const { return StoreSDNodeBits.IsTruncating; } |
2439 | |
2440 | /// Returns true if the op does a compression to the vector before storing. |
2441 | /// The node contiguously stores the active elements (integers or floats) |
2442 | /// in src (those with their respective bit set in writemask k) to unaligned |
2443 | /// memory at base_addr. |
2444 | bool isCompressingStore() const { return StoreSDNodeBits.IsCompressing; } |
2445 | |
2446 | const SDValue &getValue() const { return getOperand(1); } |
2447 | const SDValue &getBasePtr() const { return getOperand(2); } |
2448 | const SDValue &getOffset() const { return getOperand(3); } |
2449 | const SDValue &getMask() const { return getOperand(4); } |
2450 | const SDValue &getVectorLength() const { return getOperand(5); } |
2451 | |
2452 | static bool classof(const SDNode *N) { |
2453 | return N->getOpcode() == ISD::VP_STORE; |
2454 | } |
2455 | }; |
2456 | |
2457 | /// This base class is used to represent MLOAD and MSTORE nodes |
2458 | class MaskedLoadStoreSDNode : public MemSDNode { |
2459 | public: |
2460 | friend class SelectionDAG; |
2461 | |
2462 | MaskedLoadStoreSDNode(ISD::NodeType NodeTy, unsigned Order, |
2463 | const DebugLoc &dl, SDVTList VTs, |
2464 | ISD::MemIndexedMode AM, EVT MemVT, |
2465 | MachineMemOperand *MMO) |
2466 | : MemSDNode(NodeTy, Order, dl, VTs, MemVT, MMO) { |
2467 | LSBaseSDNodeBits.AddressingMode = AM; |
2468 | assert(getAddressingMode() == AM && "Value truncated")(static_cast <bool> (getAddressingMode() == AM && "Value truncated") ? void (0) : __assert_fail ("getAddressingMode() == AM && \"Value truncated\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/include/llvm/CodeGen/SelectionDAGNodes.h" , 2468, __extension__ __PRETTY_FUNCTION__)); |
2469 | } |
2470 | |
2471 | // MaskedLoadSDNode (Chain, ptr, offset, mask, passthru) |
2472 | // MaskedStoreSDNode (Chain, data, ptr, offset, mask) |
2473 | // Mask is a vector of i1 elements |
2474 | const SDValue &getOffset() const { |
2475 | return getOperand(getOpcode() == ISD::MLOAD ? 2 : 3); |
2476 | } |
2477 | const SDValue &getMask() const { |
2478 | return getOperand(getOpcode() == ISD::MLOAD ? 3 : 4); |
2479 | } |
2480 | |
2481 | /// Return the addressing mode for this load or store: |
2482 | /// unindexed, pre-inc, pre-dec, post-inc, or post-dec. |
2483 | ISD::MemIndexedMode getAddressingMode() const { |
2484 | return static_cast<ISD::MemIndexedMode>(LSBaseSDNodeBits.AddressingMode); |
2485 | } |
2486 | |
2487 | /// Return true if this is a pre/post inc/dec load/store. |
2488 | bool isIndexed() const { return getAddressingMode() != ISD::UNINDEXED; } |
2489 | |
2490 | /// Return true if this is NOT a pre/post inc/dec load/store. |
2491 | bool isUnindexed() const { return getAddressingMode() == ISD::UNINDEXED; } |
2492 | |
2493 | static bool classof(const SDNode *N) { |
2494 | return N->getOpcode() == ISD::MLOAD || |
2495 | N->getOpcode() == ISD::MSTORE; |
2496 | } |
2497 | }; |
2498 | |
2499 | /// This class is used to represent an MLOAD node |
2500 | class MaskedLoadSDNode : public MaskedLoadStoreSDNode { |
2501 | public: |
2502 | friend class SelectionDAG; |
2503 | |
2504 | MaskedLoadSDNode(unsigned Order, const DebugLoc &dl, SDVTList VTs, |
2505 | ISD::MemIndexedMode AM, ISD::LoadExtType ETy, |
2506 | bool IsExpanding, EVT MemVT, MachineMemOperand *MMO) |
2507 | : MaskedLoadStoreSDNode(ISD::MLOAD, Order, dl, VTs, AM, MemVT, MMO) { |
2508 | LoadSDNodeBits.ExtTy = ETy; |
2509 | LoadSDNodeBits.IsExpanding = IsExpanding; |
2510 | } |
2511 | |
2512 | ISD::LoadExtType getExtensionType() const { |
2513 | return static_cast<ISD::LoadExtType>(LoadSDNodeBits.ExtTy); |
2514 | } |
2515 | |
2516 | const SDValue &getBasePtr() const { return getOperand(1); } |
2517 | const SDValue &getOffset() const { return getOperand(2); } |
2518 | const SDValue &getMask() const { return getOperand(3); } |
2519 | const SDValue &getPassThru() const { return getOperand(4); } |
2520 | |
2521 | static bool classof(const SDNode *N) { |
2522 | return N->getOpcode() == ISD::MLOAD; |
2523 | } |
2524 | |
2525 | bool isExpandingLoad() const { return LoadSDNodeBits.IsExpanding; } |
2526 | }; |
2527 | |
2528 | /// This class is used to represent an MSTORE node |
2529 | class MaskedStoreSDNode : public MaskedLoadStoreSDNode { |
2530 | public: |
2531 | friend class SelectionDAG; |
2532 | |
2533 | MaskedStoreSDNode(unsigned Order, const DebugLoc &dl, SDVTList VTs, |
2534 | ISD::MemIndexedMode AM, bool isTrunc, bool isCompressing, |
2535 | EVT MemVT, MachineMemOperand *MMO) |
2536 | : MaskedLoadStoreSDNode(ISD::MSTORE, Order, dl, VTs, AM, MemVT, MMO) { |
2537 | StoreSDNodeBits.IsTruncating = isTrunc; |
2538 | StoreSDNodeBits.IsCompressing = isCompressing; |
2539 | } |
2540 | |
2541 | /// Return true if the op does a truncation before store. |
2542 | /// For integers this is the same as doing a TRUNCATE and storing the result. |
2543 | /// For floats, it is the same as doing an FP_ROUND and storing the result. |
2544 | bool isTruncatingStore() const { return StoreSDNodeBits.IsTruncating; } |
2545 | |
2546 | /// Returns true if the op does a compression to the vector before storing. |
2547 | /// The node contiguously stores the active elements (integers or floats) |
2548 | /// in src (those with their respective bit set in writemask k) to unaligned |
2549 | /// memory at base_addr. |
2550 | bool isCompressingStore() const { return StoreSDNodeBits.IsCompressing; } |
2551 | |
2552 | const SDValue &getValue() const { return getOperand(1); } |
2553 | const SDValue &getBasePtr() const { return getOperand(2); } |
2554 | const SDValue &getOffset() const { return getOperand(3); } |
2555 | const SDValue &getMask() const { return getOperand(4); } |
2556 | |
2557 | static bool classof(const SDNode *N) { |
2558 | return N->getOpcode() == ISD::MSTORE; |
2559 | } |
2560 | }; |
2561 | |
2562 | /// This is a base class used to represent |
2563 | /// VP_GATHER and VP_SCATTER nodes |
2564 | /// |
2565 | class VPGatherScatterSDNode : public MemSDNode { |
2566 | public: |
2567 | friend class SelectionDAG; |
2568 | |
2569 | VPGatherScatterSDNode(ISD::NodeType NodeTy, unsigned Order, |
2570 | const DebugLoc &dl, SDVTList VTs, EVT MemVT, |
2571 | MachineMemOperand *MMO, ISD::MemIndexType IndexType) |
2572 | : MemSDNode(NodeTy, Order, dl, VTs, MemVT, MMO) { |
2573 | LSBaseSDNodeBits.AddressingMode = IndexType; |
2574 | assert(getIndexType() == IndexType && "Value truncated")(static_cast <bool> (getIndexType() == IndexType && "Value truncated") ? void (0) : __assert_fail ("getIndexType() == IndexType && \"Value truncated\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/include/llvm/CodeGen/SelectionDAGNodes.h" , 2574, __extension__ __PRETTY_FUNCTION__)); |
2575 | } |
2576 | |
2577 | /// How is Index applied to BasePtr when computing addresses. |
2578 | ISD::MemIndexType getIndexType() const { |
2579 | return static_cast<ISD::MemIndexType>(LSBaseSDNodeBits.AddressingMode); |
2580 | } |
2581 | bool isIndexScaled() const { |
2582 | return (getIndexType() == ISD::SIGNED_SCALED) || |
2583 | (getIndexType() == ISD::UNSIGNED_SCALED); |
2584 | } |
2585 | bool isIndexSigned() const { |
2586 | return (getIndexType() == ISD::SIGNED_SCALED) || |
2587 | (getIndexType() == ISD::SIGNED_UNSCALED); |
2588 | } |
2589 | |
2590 | // In the both nodes address is Op1, mask is Op2: |
2591 | // VPGatherSDNode (Chain, base, index, scale, mask, vlen) |
2592 | // VPScatterSDNode (Chain, value, base, index, scale, mask, vlen) |
2593 | // Mask is a vector of i1 elements |
2594 | const SDValue &getBasePtr() const { |
2595 | return getOperand((getOpcode() == ISD::VP_GATHER) ? 1 : 2); |
2596 | } |
2597 | const SDValue &getIndex() const { |
2598 | return getOperand((getOpcode() == ISD::VP_GATHER) ? 2 : 3); |
2599 | } |
2600 | const SDValue &getScale() const { |
2601 | return getOperand((getOpcode() == ISD::VP_GATHER) ? 3 : 4); |
2602 | } |
2603 | const SDValue &getMask() const { |
2604 | return getOperand((getOpcode() == ISD::VP_GATHER) ? 4 : 5); |
2605 | } |
2606 | const SDValue &getVectorLength() const { |
2607 | return getOperand((getOpcode() == ISD::VP_GATHER) ? 5 : 6); |
2608 | } |
2609 | |
2610 | static bool classof(const SDNode *N) { |
2611 | return N->getOpcode() == ISD::VP_GATHER || |
2612 | N->getOpcode() == ISD::VP_SCATTER; |
2613 | } |
2614 | }; |
2615 | |
2616 | /// This class is used to represent an VP_GATHER node |
2617 | /// |
2618 | class VPGatherSDNode : public VPGatherScatterSDNode { |
2619 | public: |
2620 | friend class SelectionDAG; |
2621 | |
2622 | VPGatherSDNode(unsigned Order, const DebugLoc &dl, SDVTList VTs, EVT MemVT, |
2623 | MachineMemOperand *MMO, ISD::MemIndexType IndexType) |
2624 | : VPGatherScatterSDNode(ISD::VP_GATHER, Order, dl, VTs, MemVT, MMO, |
2625 | IndexType) {} |
2626 | |
2627 | static bool classof(const SDNode *N) { |
2628 | return N->getOpcode() == ISD::VP_GATHER; |
2629 | } |
2630 | }; |
2631 | |
2632 | /// This class is used to represent an VP_SCATTER node |
2633 | /// |
2634 | class VPScatterSDNode : public VPGatherScatterSDNode { |
2635 | public: |
2636 | friend class SelectionDAG; |
2637 | |
2638 | VPScatterSDNode(unsigned Order, const DebugLoc &dl, SDVTList VTs, EVT MemVT, |
2639 | MachineMemOperand *MMO, ISD::MemIndexType IndexType) |
2640 | : VPGatherScatterSDNode(ISD::VP_SCATTER, Order, dl, VTs, MemVT, MMO, |
2641 | IndexType) {} |
2642 | |
2643 | const SDValue &getValue() const { return getOperand(1); } |
2644 | |
2645 | static bool classof(const SDNode *N) { |
2646 | return N->getOpcode() == ISD::VP_SCATTER; |
2647 | } |
2648 | }; |
2649 | |
2650 | /// This is a base class used to represent |
2651 | /// MGATHER and MSCATTER nodes |
2652 | /// |
2653 | class MaskedGatherScatterSDNode : public MemSDNode { |
2654 | public: |
2655 | friend class SelectionDAG; |
2656 | |
2657 | MaskedGatherScatterSDNode(ISD::NodeType NodeTy, unsigned Order, |
2658 | const DebugLoc &dl, SDVTList VTs, EVT MemVT, |
2659 | MachineMemOperand *MMO, ISD::MemIndexType IndexType) |
2660 | : MemSDNode(NodeTy, Order, dl, VTs, MemVT, MMO) { |
2661 | LSBaseSDNodeBits.AddressingMode = IndexType; |
2662 | assert(getIndexType() == IndexType && "Value truncated")(static_cast <bool> (getIndexType() == IndexType && "Value truncated") ? void (0) : __assert_fail ("getIndexType() == IndexType && \"Value truncated\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/include/llvm/CodeGen/SelectionDAGNodes.h" , 2662, __extension__ __PRETTY_FUNCTION__)); |
2663 | } |
2664 | |
2665 | /// How is Index applied to BasePtr when computing addresses. |
2666 | ISD::MemIndexType getIndexType() const { |
2667 | return static_cast<ISD::MemIndexType>(LSBaseSDNodeBits.AddressingMode); |
2668 | } |
2669 | void setIndexType(ISD::MemIndexType IndexType) { |
2670 | LSBaseSDNodeBits.AddressingMode = IndexType; |
2671 | } |
2672 | bool isIndexScaled() const { |
2673 | return (getIndexType() == ISD::SIGNED_SCALED) || |
2674 | (getIndexType() == ISD::UNSIGNED_SCALED); |
2675 | } |
2676 | bool isIndexSigned() const { |
2677 | return (getIndexType() == ISD::SIGNED_SCALED) || |
2678 | (getIndexType() == ISD::SIGNED_UNSCALED); |
2679 | } |
2680 | |
2681 | // In the both nodes address is Op1, mask is Op2: |
2682 | // MaskedGatherSDNode (Chain, passthru, mask, base, index, scale) |
2683 | // MaskedScatterSDNode (Chain, value, mask, base, index, scale) |
2684 | // Mask is a vector of i1 elements |
2685 | const SDValue &getBasePtr() const { return getOperand(3); } |
2686 | const SDValue &getIndex() const { return getOperand(4); } |
2687 | const SDValue &getMask() const { return getOperand(2); } |
2688 | const SDValue &getScale() const { return getOperand(5); } |
2689 | |
2690 | static bool classof(const SDNode *N) { |
2691 | return N->getOpcode() == ISD::MGATHER || |
2692 | N->getOpcode() == ISD::MSCATTER; |
2693 | } |
2694 | }; |
2695 | |
2696 | /// This class is used to represent an MGATHER node |
2697 | /// |
2698 | class MaskedGatherSDNode : public MaskedGatherScatterSDNode { |
2699 | public: |
2700 | friend class SelectionDAG; |
2701 | |
2702 | MaskedGatherSDNode(unsigned Order, const DebugLoc &dl, SDVTList VTs, |
2703 | EVT MemVT, MachineMemOperand *MMO, |
2704 | ISD::MemIndexType IndexType, ISD::LoadExtType ETy) |
2705 | : MaskedGatherScatterSDNode(ISD::MGATHER, Order, dl, VTs, MemVT, MMO, |
2706 | IndexType) { |
2707 | LoadSDNodeBits.ExtTy = ETy; |
2708 | } |
2709 | |
2710 | const SDValue &getPassThru() const { return getOperand(1); } |
2711 | |
2712 | ISD::LoadExtType getExtensionType() const { |
2713 | return ISD::LoadExtType(LoadSDNodeBits.ExtTy); |
2714 | } |
2715 | |
2716 | static bool classof(const SDNode *N) { |
2717 | return N->getOpcode() == ISD::MGATHER; |
2718 | } |
2719 | }; |
2720 | |
2721 | /// This class is used to represent an MSCATTER node |
2722 | /// |
2723 | class MaskedScatterSDNode : public MaskedGatherScatterSDNode { |
2724 | public: |
2725 | friend class SelectionDAG; |
2726 | |
2727 | MaskedScatterSDNode(unsigned Order, const DebugLoc &dl, SDVTList VTs, |
2728 | EVT MemVT, MachineMemOperand *MMO, |
2729 | ISD::MemIndexType IndexType, bool IsTrunc) |
2730 | : MaskedGatherScatterSDNode(ISD::MSCATTER, Order, dl, VTs, MemVT, MMO, |
2731 | IndexType) { |
2732 | StoreSDNodeBits.IsTruncating = IsTrunc; |
2733 | } |
2734 | |
2735 | /// Return true if the op does a truncation before store. |
2736 | /// For integers this is the same as doing a TRUNCATE and storing the result. |
2737 | /// For floats, it is the same as doing an FP_ROUND and storing the result. |
2738 | bool isTruncatingStore() const { return StoreSDNodeBits.IsTruncating; } |
2739 | |
2740 | const SDValue &getValue() const { return getOperand(1); } |
2741 | |
2742 | static bool classof(const SDNode *N) { |
2743 | return N->getOpcode() == ISD::MSCATTER; |
2744 | } |
2745 | }; |
2746 | |
2747 | /// An SDNode that represents everything that will be needed |
2748 | /// to construct a MachineInstr. These nodes are created during the |
2749 | /// instruction selection proper phase. |
2750 | /// |
2751 | /// Note that the only supported way to set the `memoperands` is by calling the |
2752 | /// `SelectionDAG::setNodeMemRefs` function as the memory management happens |
2753 | /// inside the DAG rather than in the node. |
2754 | class MachineSDNode : public SDNode { |
2755 | private: |
2756 | friend class SelectionDAG; |
2757 | |
2758 | MachineSDNode(unsigned Opc, unsigned Order, const DebugLoc &DL, SDVTList VTs) |
2759 | : SDNode(Opc, Order, DL, VTs) {} |
2760 | |
2761 | // We use a pointer union between a single `MachineMemOperand` pointer and |
2762 | // a pointer to an array of `MachineMemOperand` pointers. This is null when |
2763 | // the number of these is zero, the single pointer variant used when the |
2764 | // number is one, and the array is used for larger numbers. |
2765 | // |
2766 | // The array is allocated via the `SelectionDAG`'s allocator and so will |
2767 | // always live until the DAG is cleaned up and doesn't require ownership here. |
2768 | // |
2769 | // We can't use something simpler like `TinyPtrVector` here because `SDNode` |
2770 | // subclasses aren't managed in a conforming C++ manner. See the comments on |
2771 | // `SelectionDAG::MorphNodeTo` which details what all goes on, but the |
2772 | // constraint here is that these don't manage memory with their constructor or |
2773 | // destructor and can be initialized to a good state even if they start off |
2774 | // uninitialized. |
2775 | PointerUnion<MachineMemOperand *, MachineMemOperand **> MemRefs = {}; |
2776 | |
2777 | // Note that this could be folded into the above `MemRefs` member if doing so |
2778 | // is advantageous at some point. We don't need to store this in most cases. |
2779 | // However, at the moment this doesn't appear to make the allocation any |
2780 | // smaller and makes the code somewhat simpler to read. |
2781 | int NumMemRefs = 0; |
2782 | |
2783 | public: |
2784 | using mmo_iterator = ArrayRef<MachineMemOperand *>::const_iterator; |
2785 | |
2786 | ArrayRef<MachineMemOperand *> memoperands() const { |
2787 | // Special case the common cases. |
2788 | if (NumMemRefs == 0) |
2789 | return {}; |
2790 | if (NumMemRefs == 1) |
2791 | return makeArrayRef(MemRefs.getAddrOfPtr1(), 1); |
2792 | |
2793 | // Otherwise we have an actual array. |
2794 | return makeArrayRef(MemRefs.get<MachineMemOperand **>(), NumMemRefs); |
2795 | } |
2796 | mmo_iterator memoperands_begin() const { return memoperands().begin(); } |
2797 | mmo_iterator memoperands_end() const { return memoperands().end(); } |
2798 | bool memoperands_empty() const { return memoperands().empty(); } |
2799 | |
2800 | /// Clear out the memory reference descriptor list. |
2801 | void clearMemRefs() { |
2802 | MemRefs = nullptr; |
2803 | NumMemRefs = 0; |
2804 | } |
2805 | |
2806 | static bool classof(const SDNode *N) { |
2807 | return N->isMachineOpcode(); |
2808 | } |
2809 | }; |
2810 | |
2811 | /// An SDNode that records if a register contains a value that is guaranteed to |
2812 | /// be aligned accordingly. |
2813 | class AssertAlignSDNode : public SDNode { |
2814 | Align Alignment; |
2815 | |
2816 | public: |
2817 | AssertAlignSDNode(unsigned Order, const DebugLoc &DL, EVT VT, Align A) |
2818 | : SDNode(ISD::AssertAlign, Order, DL, getSDVTList(VT)), Alignment(A) {} |
2819 | |
2820 | Align getAlign() const { return Alignment; } |
2821 | |
2822 | static bool classof(const SDNode *N) { |
2823 | return N->getOpcode() == ISD::AssertAlign; |
2824 | } |
2825 | }; |
2826 | |
2827 | class SDNodeIterator { |
2828 | const SDNode *Node; |
2829 | unsigned Operand; |
2830 | |
2831 | SDNodeIterator(const SDNode *N, unsigned Op) : Node(N), Operand(Op) {} |
2832 | |
2833 | public: |
2834 | using iterator_category = std::forward_iterator_tag; |
2835 | using value_type = SDNode; |
2836 | using difference_type = std::ptrdiff_t; |
2837 | using pointer = value_type *; |
2838 | using reference = value_type &; |
2839 | |
2840 | bool operator==(const SDNodeIterator& x) const { |
2841 | return Operand == x.Operand; |
2842 | } |
2843 | bool operator!=(const SDNodeIterator& x) const { return !operator==(x); } |
2844 | |
2845 | pointer operator*() const { |
2846 | return Node->getOperand(Operand).getNode(); |
2847 | } |
2848 | pointer operator->() const { return operator*(); } |
2849 | |
2850 | SDNodeIterator& operator++() { // Preincrement |
2851 | ++Operand; |
2852 | return *this; |
2853 | } |
2854 | SDNodeIterator operator++(int) { // Postincrement |
2855 | SDNodeIterator tmp = *this; ++*this; return tmp; |
2856 | } |
2857 | size_t operator-(SDNodeIterator Other) const { |
2858 | assert(Node == Other.Node &&(static_cast <bool> (Node == Other.Node && "Cannot compare iterators of two different nodes!" ) ? void (0) : __assert_fail ("Node == Other.Node && \"Cannot compare iterators of two different nodes!\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/include/llvm/CodeGen/SelectionDAGNodes.h" , 2859, __extension__ __PRETTY_FUNCTION__)) |
2859 | "Cannot compare iterators of two different nodes!")(static_cast <bool> (Node == Other.Node && "Cannot compare iterators of two different nodes!" ) ? void (0) : __assert_fail ("Node == Other.Node && \"Cannot compare iterators of two different nodes!\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/include/llvm/CodeGen/SelectionDAGNodes.h" , 2859, __extension__ __PRETTY_FUNCTION__)); |
2860 | return Operand - Other.Operand; |
2861 | } |
2862 | |
2863 | static SDNodeIterator begin(const SDNode *N) { return SDNodeIterator(N, 0); } |
2864 | static SDNodeIterator end (const SDNode *N) { |
2865 | return SDNodeIterator(N, N->getNumOperands()); |
2866 | } |
2867 | |
2868 | unsigned getOperand() const { return Operand; } |
2869 | const SDNode *getNode() const { return Node; } |
2870 | }; |
2871 | |
2872 | template <> struct GraphTraits<SDNode*> { |
2873 | using NodeRef = SDNode *; |
2874 | using ChildIteratorType = SDNodeIterator; |
2875 | |
2876 | static NodeRef getEntryNode(SDNode *N) { return N; } |
2877 | |
2878 | static ChildIteratorType child_begin(NodeRef N) { |
2879 | return SDNodeIterator::begin(N); |
2880 | } |
2881 | |
2882 | static ChildIteratorType child_end(NodeRef N) { |
2883 | return SDNodeIterator::end(N); |
2884 | } |
2885 | }; |
2886 | |
2887 | /// A representation of the largest SDNode, for use in sizeof(). |
2888 | /// |
2889 | /// This needs to be a union because the largest node differs on 32 bit systems |
2890 | /// with 4 and 8 byte pointer alignment, respectively. |
2891 | using LargestSDNode = AlignedCharArrayUnion<AtomicSDNode, TargetIndexSDNode, |
2892 | BlockAddressSDNode, |
2893 | GlobalAddressSDNode, |
2894 | PseudoProbeSDNode>; |
2895 | |
2896 | /// The SDNode class with the greatest alignment requirement. |
2897 | using MostAlignedSDNode = GlobalAddressSDNode; |
2898 | |
2899 | namespace ISD { |
2900 | |
2901 | /// Returns true if the specified node is a non-extending and unindexed load. |
2902 | inline bool isNormalLoad(const SDNode *N) { |
2903 | const LoadSDNode *Ld = dyn_cast<LoadSDNode>(N); |
2904 | return Ld && Ld->getExtensionType() == ISD::NON_EXTLOAD && |
2905 | Ld->getAddressingMode() == ISD::UNINDEXED; |
2906 | } |
2907 | |
2908 | /// Returns true if the specified node is a non-extending load. |
2909 | inline bool isNON_EXTLoad(const SDNode *N) { |
2910 | return isa<LoadSDNode>(N) && |
2911 | cast<LoadSDNode>(N)->getExtensionType() == ISD::NON_EXTLOAD; |
2912 | } |
2913 | |
2914 | /// Returns true if the specified node is a EXTLOAD. |
2915 | inline bool isEXTLoad(const SDNode *N) { |
2916 | return isa<LoadSDNode>(N) && |
2917 | cast<LoadSDNode>(N)->getExtensionType() == ISD::EXTLOAD; |
2918 | } |
2919 | |
2920 | /// Returns true if the specified node is a SEXTLOAD. |
2921 | inline bool isSEXTLoad(const SDNode *N) { |
2922 | return isa<LoadSDNode>(N) && |
2923 | cast<LoadSDNode>(N)->getExtensionType() == ISD::SEXTLOAD; |
2924 | } |
2925 | |
2926 | /// Returns true if the specified node is a ZEXTLOAD. |
2927 | inline bool isZEXTLoad(const SDNode *N) { |
2928 | return isa<LoadSDNode>(N) && |
2929 | cast<LoadSDNode>(N)->getExtensionType() == ISD::ZEXTLOAD; |
2930 | } |
2931 | |
2932 | /// Returns true if the specified node is an unindexed load. |
2933 | inline bool isUNINDEXEDLoad(const SDNode *N) { |
2934 | return isa<LoadSDNode>(N) && |
2935 | cast<LoadSDNode>(N)->getAddressingMode() == ISD::UNINDEXED; |
2936 | } |
2937 | |
2938 | /// Returns true if the specified node is a non-truncating |
2939 | /// and unindexed store. |
2940 | inline bool isNormalStore(const SDNode *N) { |
2941 | const StoreSDNode *St = dyn_cast<StoreSDNode>(N); |
2942 | return St && !St->isTruncatingStore() && |
2943 | St->getAddressingMode() == ISD::UNINDEXED; |
2944 | } |
2945 | |
2946 | /// Returns true if the specified node is an unindexed store. |
2947 | inline bool isUNINDEXEDStore(const SDNode *N) { |
2948 | return isa<StoreSDNode>(N) && |
2949 | cast<StoreSDNode>(N)->getAddressingMode() == ISD::UNINDEXED; |
2950 | } |
2951 | |
2952 | /// Attempt to match a unary predicate against a scalar/splat constant or |
2953 | /// every element of a constant BUILD_VECTOR. |
2954 | /// If AllowUndef is true, then UNDEF elements will pass nullptr to Match. |
2955 | bool matchUnaryPredicate(SDValue Op, |
2956 | std::function<bool(ConstantSDNode *)> Match, |
2957 | bool AllowUndefs = false); |
2958 | |
2959 | /// Attempt to match a binary predicate against a pair of scalar/splat |
2960 | /// constants or every element of a pair of constant BUILD_VECTORs. |
2961 | /// If AllowUndef is true, then UNDEF elements will pass nullptr to Match. |
2962 | /// If AllowTypeMismatch is true then RetType + ArgTypes don't need to match. |
2963 | bool matchBinaryPredicate( |
2964 | SDValue LHS, SDValue RHS, |
2965 | std::function<bool(ConstantSDNode *, ConstantSDNode *)> Match, |
2966 | bool AllowUndefs = false, bool AllowTypeMismatch = false); |
2967 | |
2968 | /// Returns true if the specified value is the overflow result from one |
2969 | /// of the overflow intrinsic nodes. |
2970 | inline bool isOverflowIntrOpRes(SDValue Op) { |
2971 | unsigned Opc = Op.getOpcode(); |
2972 | return (Op.getResNo() == 1 && |
2973 | (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO || |
2974 | Opc == ISD::USUBO || Opc == ISD::SMULO || Opc == ISD::UMULO)); |
2975 | } |
2976 | |
2977 | } // end namespace ISD |
2978 | |
2979 | } // end namespace llvm |
2980 | |
2981 | #endif // LLVM_CODEGEN_SELECTIONDAGNODES_H |
1 | //===-- llvm/ADT/APInt.h - For Arbitrary Precision Integer -----*- C++ -*--===// |
2 | // |
3 | // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. |
4 | // See https://llvm.org/LICENSE.txt for license information. |
5 | // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception |
6 | // |
7 | //===----------------------------------------------------------------------===// |
8 | /// |
9 | /// \file |
10 | /// This file implements a class to represent arbitrary precision |
11 | /// integral constant values and operations on them. |
12 | /// |
13 | //===----------------------------------------------------------------------===// |
14 | |
15 | #ifndef LLVM_ADT_APINT_H |
16 | #define LLVM_ADT_APINT_H |
17 | |
18 | #include "llvm/Support/Compiler.h" |
19 | #include "llvm/Support/MathExtras.h" |
20 | #include <cassert> |
21 | #include <climits> |
22 | #include <cstring> |
23 | #include <utility> |
24 | |
25 | namespace llvm { |
26 | class FoldingSetNodeID; |
27 | class StringRef; |
28 | class hash_code; |
29 | class raw_ostream; |
30 | |
31 | template <typename T> class SmallVectorImpl; |
32 | template <typename T> class ArrayRef; |
33 | template <typename T> class Optional; |
34 | template <typename T> struct DenseMapInfo; |
35 | |
36 | class APInt; |
37 | |
38 | inline APInt operator-(APInt); |
39 | |
40 | //===----------------------------------------------------------------------===// |
41 | // APInt Class |
42 | //===----------------------------------------------------------------------===// |
43 | |
44 | /// Class for arbitrary precision integers. |
45 | /// |
46 | /// APInt is a functional replacement for common case unsigned integer type like |
47 | /// "unsigned", "unsigned long" or "uint64_t", but also allows non-byte-width |
48 | /// integer sizes and large integer value types such as 3-bits, 15-bits, or more |
49 | /// than 64-bits of precision. APInt provides a variety of arithmetic operators |
50 | /// and methods to manipulate integer values of any bit-width. It supports both |
51 | /// the typical integer arithmetic and comparison operations as well as bitwise |
52 | /// manipulation. |
53 | /// |
54 | /// The class has several invariants worth noting: |
55 | /// * All bit, byte, and word positions are zero-based. |
56 | /// * Once the bit width is set, it doesn't change except by the Truncate, |
57 | /// SignExtend, or ZeroExtend operations. |
58 | /// * All binary operators must be on APInt instances of the same bit width. |
59 | /// Attempting to use these operators on instances with different bit |
60 | /// widths will yield an assertion. |
61 | /// * The value is stored canonically as an unsigned value. For operations |
62 | /// where it makes a difference, there are both signed and unsigned variants |
63 | /// of the operation. For example, sdiv and udiv. However, because the bit |
64 | /// widths must be the same, operations such as Mul and Add produce the same |
65 | /// results regardless of whether the values are interpreted as signed or |
66 | /// not. |
67 | /// * In general, the class tries to follow the style of computation that LLVM |
68 | /// uses in its IR. This simplifies its use for LLVM. |
69 | /// * APInt supports zero-bit-width values, but operations that require bits |
70 | /// are not defined on it (e.g. you cannot ask for the sign of a zero-bit |
71 | /// integer). This means that operations like zero extension and logical |
72 | /// shifts are defined, but sign extension and ashr is not. Zero bit values |
73 | /// compare and hash equal to themselves, and countLeadingZeros returns 0. |
74 | /// |
75 | class LLVM_NODISCARD[[clang::warn_unused_result]] APInt { |
76 | public: |
77 | typedef uint64_t WordType; |
78 | |
79 | /// This enum is used to hold the constants we needed for APInt. |
80 | enum : unsigned { |
81 | /// Byte size of a word. |
82 | APINT_WORD_SIZE = sizeof(WordType), |
83 | /// Bits in a word. |
84 | APINT_BITS_PER_WORD = APINT_WORD_SIZE * CHAR_BIT8 |
85 | }; |
86 | |
87 | enum class Rounding { |
88 | DOWN, |
89 | TOWARD_ZERO, |
90 | UP, |
91 | }; |
92 | |
93 | static constexpr WordType WORDTYPE_MAX = ~WordType(0); |
94 | |
95 | /// \name Constructors |
96 | /// @{ |
97 | |
98 | /// Create a new APInt of numBits width, initialized as val. |
99 | /// |
100 | /// If isSigned is true then val is treated as if it were a signed value |
101 | /// (i.e. as an int64_t) and the appropriate sign extension to the bit width |
102 | /// will be done. Otherwise, no sign extension occurs (high order bits beyond |
103 | /// the range of val are zero filled). |
104 | /// |
105 | /// \param numBits the bit width of the constructed APInt |
106 | /// \param val the initial value of the APInt |
107 | /// \param isSigned how to treat signedness of val |
108 | APInt(unsigned numBits, uint64_t val, bool isSigned = false) |
109 | : BitWidth(numBits) { |
110 | if (isSingleWord()) { |
111 | U.VAL = val; |
112 | clearUnusedBits(); |
113 | } else { |
114 | initSlowCase(val, isSigned); |
115 | } |
116 | } |
117 | |
118 | /// Construct an APInt of numBits width, initialized as bigVal[]. |
119 | /// |
120 | /// Note that bigVal.size() can be smaller or larger than the corresponding |
121 | /// bit width but any extraneous bits will be dropped. |
122 | /// |
123 | /// \param numBits the bit width of the constructed APInt |
124 | /// \param bigVal a sequence of words to form the initial value of the APInt |
125 | APInt(unsigned numBits, ArrayRef<uint64_t> bigVal); |
126 | |
127 | /// Equivalent to APInt(numBits, ArrayRef<uint64_t>(bigVal, numWords)), but |
128 | /// deprecated because this constructor is prone to ambiguity with the |
129 | /// APInt(unsigned, uint64_t, bool) constructor. |
130 | /// |
131 | /// If this overload is ever deleted, care should be taken to prevent calls |
132 | /// from being incorrectly captured by the APInt(unsigned, uint64_t, bool) |
133 | /// constructor. |
134 | APInt(unsigned numBits, unsigned numWords, const uint64_t bigVal[]); |
135 | |
136 | /// Construct an APInt from a string representation. |
137 | /// |
138 | /// This constructor interprets the string \p str in the given radix. The |
139 | /// interpretation stops when the first character that is not suitable for the |
140 | /// radix is encountered, or the end of the string. Acceptable radix values |
141 | /// are 2, 8, 10, 16, and 36. It is an error for the value implied by the |
142 | /// string to require more bits than numBits. |
143 | /// |
144 | /// \param numBits the bit width of the constructed APInt |
145 | /// \param str the string to be interpreted |
146 | /// \param radix the radix to use for the conversion |
147 | APInt(unsigned numBits, StringRef str, uint8_t radix); |
148 | |
149 | /// Default constructor that creates an APInt with a 1-bit zero value. |
150 | explicit APInt() : BitWidth(1) { U.VAL = 0; } |
151 | |
152 | /// Copy Constructor. |
153 | APInt(const APInt &that) : BitWidth(that.BitWidth) { |
154 | if (isSingleWord()) |
155 | U.VAL = that.U.VAL; |
156 | else |
157 | initSlowCase(that); |
158 | } |
159 | |
160 | /// Move Constructor. |
161 | APInt(APInt &&that) : BitWidth(that.BitWidth) { |
162 | memcpy(&U, &that.U, sizeof(U)); |
163 | that.BitWidth = 0; |
164 | } |
165 | |
166 | /// Destructor. |
167 | ~APInt() { |
168 | if (needsCleanup()) |
169 | delete[] U.pVal; |
170 | } |
171 | |
172 | /// @} |
173 | /// \name Value Generators |
174 | /// @{ |
175 | |
176 | /// Get the '0' value for the specified bit-width. |
177 | static APInt getZero(unsigned numBits) { return APInt(numBits, 0); } |
178 | |
179 | /// NOTE: This is soft-deprecated. Please use `getZero()` instead. |
180 | static APInt getNullValue(unsigned numBits) { return getZero(numBits); } |
181 | |
182 | /// Return an APInt zero bits wide. |
183 | static APInt getZeroWidth() { return getZero(0); } |
184 | |
185 | /// Gets maximum unsigned value of APInt for specific bit width. |
186 | static APInt getMaxValue(unsigned numBits) { return getAllOnes(numBits); } |
187 | |
188 | /// Gets maximum signed value of APInt for a specific bit width. |
189 | static APInt getSignedMaxValue(unsigned numBits) { |
190 | APInt API = getAllOnes(numBits); |
191 | API.clearBit(numBits - 1); |
192 | return API; |
193 | } |
194 | |
195 | /// Gets minimum unsigned value of APInt for a specific bit width. |
196 | static APInt getMinValue(unsigned numBits) { return APInt(numBits, 0); } |
197 | |
198 | /// Gets minimum signed value of APInt for a specific bit width. |
199 | static APInt getSignedMinValue(unsigned numBits) { |
200 | APInt API(numBits, 0); |
201 | API.setBit(numBits - 1); |
202 | return API; |
203 | } |
204 | |
205 | /// Get the SignMask for a specific bit width. |
206 | /// |
207 | /// This is just a wrapper function of getSignedMinValue(), and it helps code |
208 | /// readability when we want to get a SignMask. |
209 | static APInt getSignMask(unsigned BitWidth) { |
210 | return getSignedMinValue(BitWidth); |
211 | } |
212 | |
213 | /// Return an APInt of a specified width with all bits set. |
214 | static APInt getAllOnes(unsigned numBits) { |
215 | return APInt(numBits, WORDTYPE_MAX, true); |
216 | } |
217 | |
218 | /// NOTE: This is soft-deprecated. Please use `getAllOnes()` instead. |
219 | static APInt getAllOnesValue(unsigned numBits) { return getAllOnes(numBits); } |
220 | |
221 | /// Return an APInt with exactly one bit set in the result. |
222 | static APInt getOneBitSet(unsigned numBits, unsigned BitNo) { |
223 | APInt Res(numBits, 0); |
224 | Res.setBit(BitNo); |
225 | return Res; |
226 | } |
227 | |
228 | /// Get a value with a block of bits set. |
229 | /// |
230 | /// Constructs an APInt value that has a contiguous range of bits set. The |
231 | /// bits from loBit (inclusive) to hiBit (exclusive) will be set. All other |
232 | /// bits will be zero. For example, with parameters(32, 0, 16) you would get |
233 | /// 0x0000FFFF. Please call getBitsSetWithWrap if \p loBit may be greater than |
234 | /// \p hiBit. |
235 | /// |
236 | /// \param numBits the intended bit width of the result |
237 | /// \param loBit the index of the lowest bit set. |
238 | /// \param hiBit the index of the highest bit set. |
239 | /// |
240 | /// \returns An APInt value with the requested bits set. |
241 | static APInt getBitsSet(unsigned numBits, unsigned loBit, unsigned hiBit) { |
242 | APInt Res(numBits, 0); |
243 | Res.setBits(loBit, hiBit); |
244 | return Res; |
245 | } |
246 | |
247 | /// Wrap version of getBitsSet. |
248 | /// If \p hiBit is bigger than \p loBit, this is same with getBitsSet. |
249 | /// If \p hiBit is not bigger than \p loBit, the set bits "wrap". For example, |
250 | /// with parameters (32, 28, 4), you would get 0xF000000F. |
251 | /// If \p hiBit is equal to \p loBit, you would get a result with all bits |
252 | /// set. |
253 | static APInt getBitsSetWithWrap(unsigned numBits, unsigned loBit, |
254 | unsigned hiBit) { |
255 | APInt Res(numBits, 0); |
256 | Res.setBitsWithWrap(loBit, hiBit); |
257 | return Res; |
258 | } |
259 | |
260 | /// Constructs an APInt value that has a contiguous range of bits set. The |
261 | /// bits from loBit (inclusive) to numBits (exclusive) will be set. All other |
262 | /// bits will be zero. For example, with parameters(32, 12) you would get |
263 | /// 0xFFFFF000. |
264 | /// |
265 | /// \param numBits the intended bit width of the result |
266 | /// \param loBit the index of the lowest bit to set. |
267 | /// |
268 | /// \returns An APInt value with the requested bits set. |
269 | static APInt getBitsSetFrom(unsigned numBits, unsigned loBit) { |
270 | APInt Res(numBits, 0); |
271 | Res.setBitsFrom(loBit); |
272 | return Res; |
273 | } |
274 | |
275 | /// Constructs an APInt value that has the top hiBitsSet bits set. |
276 | /// |
277 | /// \param numBits the bitwidth of the result |
278 | /// \param hiBitsSet the number of high-order bits set in the result. |
279 | static APInt getHighBitsSet(unsigned numBits, unsigned hiBitsSet) { |
280 | APInt Res(numBits, 0); |
281 | Res.setHighBits(hiBitsSet); |
282 | return Res; |
283 | } |
284 | |
285 | /// Constructs an APInt value that has the bottom loBitsSet bits set. |
286 | /// |
287 | /// \param numBits the bitwidth of the result |
288 | /// \param loBitsSet the number of low-order bits set in the result. |
289 | static APInt getLowBitsSet(unsigned numBits, unsigned loBitsSet) { |
290 | APInt Res(numBits, 0); |
291 | Res.setLowBits(loBitsSet); |
292 | return Res; |
293 | } |
294 | |
295 | /// Return a value containing V broadcasted over NewLen bits. |
296 | static APInt getSplat(unsigned NewLen, const APInt &V); |
297 | |
298 | /// @} |
299 | /// \name Value Tests |
300 | /// @{ |
301 | |
302 | /// Determine if this APInt just has one word to store value. |
303 | /// |
304 | /// \returns true if the number of bits <= 64, false otherwise. |
305 | bool isSingleWord() const { return BitWidth <= APINT_BITS_PER_WORD; } |
306 | |
307 | /// Determine sign of this APInt. |
308 | /// |
309 | /// This tests the high bit of this APInt to determine if it is set. |
310 | /// |
311 | /// \returns true if this APInt is negative, false otherwise |
312 | bool isNegative() const { return (*this)[BitWidth - 1]; } |
313 | |
314 | /// Determine if this APInt Value is non-negative (>= 0) |
315 | /// |
316 | /// This tests the high bit of the APInt to determine if it is unset. |
317 | bool isNonNegative() const { return !isNegative(); } |
318 | |
319 | /// Determine if sign bit of this APInt is set. |
320 | /// |
321 | /// This tests the high bit of this APInt to determine if it is set. |
322 | /// |
323 | /// \returns true if this APInt has its sign bit set, false otherwise. |
324 | bool isSignBitSet() const { return (*this)[BitWidth - 1]; } |
325 | |
326 | /// Determine if sign bit of this APInt is clear. |
327 | /// |
328 | /// This tests the high bit of this APInt to determine if it is clear. |
329 | /// |
330 | /// \returns true if this APInt has its sign bit clear, false otherwise. |
331 | bool isSignBitClear() const { return !isSignBitSet(); } |
332 | |
333 | /// Determine if this APInt Value is positive. |
334 | /// |
335 | /// This tests if the value of this APInt is positive (> 0). Note |
336 | /// that 0 is not a positive value. |
337 | /// |
338 | /// \returns true if this APInt is positive. |
339 | bool isStrictlyPositive() const { return isNonNegative() && !isZero(); } |
340 | |
341 | /// Determine if this APInt Value is non-positive (<= 0). |
342 | /// |
343 | /// \returns true if this APInt is non-positive. |
344 | bool isNonPositive() const { return !isStrictlyPositive(); } |
345 | |
346 | /// Determine if all bits are set. This is true for zero-width values. |
347 | bool isAllOnes() const { |
348 | if (BitWidth == 0) |
349 | return true; |
350 | if (isSingleWord()) |
351 | return U.VAL == WORDTYPE_MAX >> (APINT_BITS_PER_WORD - BitWidth); |
352 | return countTrailingOnesSlowCase() == BitWidth; |
353 | } |
354 | |
355 | /// NOTE: This is soft-deprecated. Please use `isAllOnes()` instead. |
356 | bool isAllOnesValue() const { return isAllOnes(); } |
357 | |
358 | /// Determine if this value is zero, i.e. all bits are clear. |
359 | bool isZero() const { |
360 | if (isSingleWord()) |
361 | return U.VAL == 0; |
362 | return countLeadingZerosSlowCase() == BitWidth; |
363 | } |
364 | |
365 | /// NOTE: This is soft-deprecated. Please use `isZero()` instead. |
366 | bool isNullValue() const { return isZero(); } |
367 | |
368 | /// Determine if this is a value of 1. |
369 | /// |
370 | /// This checks to see if the value of this APInt is one. |
371 | bool isOne() const { |
372 | if (isSingleWord()) |
373 | return U.VAL == 1; |
374 | return countLeadingZerosSlowCase() == BitWidth - 1; |
375 | } |
376 | |
377 | /// NOTE: This is soft-deprecated. Please use `isOne()` instead. |
378 | bool isOneValue() const { return isOne(); } |
379 | |
380 | /// Determine if this is the largest unsigned value. |
381 | /// |
382 | /// This checks to see if the value of this APInt is the maximum unsigned |
383 | /// value for the APInt's bit width. |
384 | bool isMaxValue() const { return isAllOnes(); } |
385 | |
386 | /// Determine if this is the largest signed value. |
387 | /// |
388 | /// This checks to see if the value of this APInt is the maximum signed |
389 | /// value for the APInt's bit width. |
390 | bool isMaxSignedValue() const { |
391 | if (isSingleWord()) { |
392 | assert(BitWidth && "zero width values not allowed")(static_cast <bool> (BitWidth && "zero width values not allowed" ) ? void (0) : __assert_fail ("BitWidth && \"zero width values not allowed\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/include/llvm/ADT/APInt.h" , 392, __extension__ __PRETTY_FUNCTION__)); |
393 | return U.VAL == ((WordType(1) << (BitWidth - 1)) - 1); |
394 | } |
395 | return !isNegative() && countTrailingOnesSlowCase() == BitWidth - 1; |
396 | } |
397 | |
398 | /// Determine if this is the smallest unsigned value. |
399 | /// |
400 | /// This checks to see if the value of this APInt is the minimum unsigned |
401 | /// value for the APInt's bit width. |
402 | bool isMinValue() const { return isZero(); } |
403 | |
404 | /// Determine if this is the smallest signed value. |
405 | /// |
406 | /// This checks to see if the value of this APInt is the minimum signed |
407 | /// value for the APInt's bit width. |
408 | bool isMinSignedValue() const { |
409 | if (isSingleWord()) { |
410 | assert(BitWidth && "zero width values not allowed")(static_cast <bool> (BitWidth && "zero width values not allowed" ) ? void (0) : __assert_fail ("BitWidth && \"zero width values not allowed\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/include/llvm/ADT/APInt.h" , 410, __extension__ __PRETTY_FUNCTION__)); |
411 | return U.VAL == (WordType(1) << (BitWidth - 1)); |
412 | } |
413 | return isNegative() && countTrailingZerosSlowCase() == BitWidth - 1; |
414 | } |
415 | |
416 | /// Check if this APInt has an N-bits unsigned integer value. |
417 | bool isIntN(unsigned N) const { return getActiveBits() <= N; } |
418 | |
419 | /// Check if this APInt has an N-bits signed integer value. |
420 | bool isSignedIntN(unsigned N) const { return getMinSignedBits() <= N; } |
421 | |
422 | /// Check if this APInt's value is a power of two greater than zero. |
423 | /// |
424 | /// \returns true if the argument APInt value is a power of two > 0. |
425 | bool isPowerOf2() const { |
426 | if (isSingleWord()) { |
427 | assert(BitWidth && "zero width values not allowed")(static_cast <bool> (BitWidth && "zero width values not allowed" ) ? void (0) : __assert_fail ("BitWidth && \"zero width values not allowed\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/include/llvm/ADT/APInt.h" , 427, __extension__ __PRETTY_FUNCTION__)); |
428 | return isPowerOf2_64(U.VAL); |
429 | } |
430 | return countPopulationSlowCase() == 1; |
431 | } |
432 | |
433 | /// Check if this APInt's negated value is a power of two greater than zero. |
434 | bool isNegatedPowerOf2() const { |
435 | assert(BitWidth && "zero width values not allowed")(static_cast <bool> (BitWidth && "zero width values not allowed" ) ? void (0) : __assert_fail ("BitWidth && \"zero width values not allowed\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/include/llvm/ADT/APInt.h" , 435, __extension__ __PRETTY_FUNCTION__)); |
436 | if (isNonNegative()) |
437 | return false; |
438 | // NegatedPowerOf2 - shifted mask in the top bits. |
439 | unsigned LO = countLeadingOnes(); |
440 | unsigned TZ = countTrailingZeros(); |
441 | return (LO + TZ) == BitWidth; |
442 | } |
443 | |
444 | /// Check if the APInt's value is returned by getSignMask. |
445 | /// |
446 | /// \returns true if this is the value returned by getSignMask. |
447 | bool isSignMask() const { return isMinSignedValue(); } |
448 | |
449 | /// Convert APInt to a boolean value. |
450 | /// |
451 | /// This converts the APInt to a boolean value as a test against zero. |
452 | bool getBoolValue() const { return !isZero(); } |
453 | |
454 | /// If this value is smaller than the specified limit, return it, otherwise |
455 | /// return the limit value. This causes the value to saturate to the limit. |
456 | uint64_t getLimitedValue(uint64_t Limit = UINT64_MAX(18446744073709551615UL)) const { |
457 | return ugt(Limit) ? Limit : getZExtValue(); |
458 | } |
459 | |
460 | /// Check if the APInt consists of a repeated bit pattern. |
461 | /// |
462 | /// e.g. 0x01010101 satisfies isSplat(8). |
463 | /// \param SplatSizeInBits The size of the pattern in bits. Must divide bit |
464 | /// width without remainder. |
465 | bool isSplat(unsigned SplatSizeInBits) const; |
466 | |
467 | /// \returns true if this APInt value is a sequence of \param numBits ones |
468 | /// starting at the least significant bit with the remainder zero. |
469 | bool isMask(unsigned numBits) const { |
470 | assert(numBits != 0 && "numBits must be non-zero")(static_cast <bool> (numBits != 0 && "numBits must be non-zero" ) ? void (0) : __assert_fail ("numBits != 0 && \"numBits must be non-zero\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/include/llvm/ADT/APInt.h" , 470, __extension__ __PRETTY_FUNCTION__)); |
471 | assert(numBits <= BitWidth && "numBits out of range")(static_cast <bool> (numBits <= BitWidth && "numBits out of range" ) ? void (0) : __assert_fail ("numBits <= BitWidth && \"numBits out of range\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/include/llvm/ADT/APInt.h" , 471, __extension__ __PRETTY_FUNCTION__)); |
472 | if (isSingleWord()) |
473 | return U.VAL == (WORDTYPE_MAX >> (APINT_BITS_PER_WORD - numBits)); |
474 | unsigned Ones = countTrailingOnesSlowCase(); |
475 | return (numBits == Ones) && |
476 | ((Ones + countLeadingZerosSlowCase()) == BitWidth); |
477 | } |
478 | |
479 | /// \returns true if this APInt is a non-empty sequence of ones starting at |
480 | /// the least significant bit with the remainder zero. |
481 | /// Ex. isMask(0x0000FFFFU) == true. |
482 | bool isMask() const { |
483 | if (isSingleWord()) |
484 | return isMask_64(U.VAL); |
485 | unsigned Ones = countTrailingOnesSlowCase(); |
486 | return (Ones > 0) && ((Ones + countLeadingZerosSlowCase()) == BitWidth); |
487 | } |
488 | |
489 | /// Return true if this APInt value contains a sequence of ones with |
490 | /// the remainder zero. |
491 | bool isShiftedMask() const { |
492 | if (isSingleWord()) |
493 | return isShiftedMask_64(U.VAL); |
494 | unsigned Ones = countPopulationSlowCase(); |
495 | unsigned LeadZ = countLeadingZerosSlowCase(); |
496 | return (Ones + LeadZ + countTrailingZeros()) == BitWidth; |
497 | } |
498 | |
499 | /// Compute an APInt containing numBits highbits from this APInt. |
500 | /// |
501 | /// Get an APInt with the same BitWidth as this APInt, just zero mask the low |
502 | /// bits and right shift to the least significant bit. |
503 | /// |
504 | /// \returns the high "numBits" bits of this APInt. |
505 | APInt getHiBits(unsigned numBits) const; |
506 | |
507 | /// Compute an APInt containing numBits lowbits from this APInt. |
508 | /// |
509 | /// Get an APInt with the same BitWidth as this APInt, just zero mask the high |
510 | /// bits. |
511 | /// |
512 | /// \returns the low "numBits" bits of this APInt. |
513 | APInt getLoBits(unsigned numBits) const; |
514 | |
515 | /// Determine if two APInts have the same value, after zero-extending |
516 | /// one of them (if needed!) to ensure that the bit-widths match. |
517 | static bool isSameValue(const APInt &I1, const APInt &I2) { |
518 | if (I1.getBitWidth() == I2.getBitWidth()) |
519 | return I1 == I2; |
520 | |
521 | if (I1.getBitWidth() > I2.getBitWidth()) |
522 | return I1 == I2.zext(I1.getBitWidth()); |
523 | |
524 | return I1.zext(I2.getBitWidth()) == I2; |
525 | } |
526 | |
527 | /// Overload to compute a hash_code for an APInt value. |
528 | friend hash_code hash_value(const APInt &Arg); |
529 | |
530 | /// This function returns a pointer to the internal storage of the APInt. |
531 | /// This is useful for writing out the APInt in binary form without any |
532 | /// conversions. |
533 | const uint64_t *getRawData() const { |
534 | if (isSingleWord()) |
535 | return &U.VAL; |
536 | return &U.pVal[0]; |
537 | } |
538 | |
539 | /// @} |
540 | /// \name Unary Operators |
541 | /// @{ |
542 | |
543 | /// Postfix increment operator. Increment *this by 1. |
544 | /// |
545 | /// \returns a new APInt value representing the original value of *this. |
546 | APInt operator++(int) { |
547 | APInt API(*this); |
548 | ++(*this); |
549 | return API; |
550 | } |
551 | |
552 | /// Prefix increment operator. |
553 | /// |
554 | /// \returns *this incremented by one |
555 | APInt &operator++(); |
556 | |
557 | /// Postfix decrement operator. Decrement *this by 1. |
558 | /// |
559 | /// \returns a new APInt value representing the original value of *this. |
560 | APInt operator--(int) { |
561 | APInt API(*this); |
562 | --(*this); |
563 | return API; |
564 | } |
565 | |
566 | /// Prefix decrement operator. |
567 | /// |
568 | /// \returns *this decremented by one. |
569 | APInt &operator--(); |
570 | |
571 | /// Logical negation operation on this APInt returns true if zero, like normal |
572 | /// integers. |
573 | bool operator!() const { return isZero(); } |
574 | |
575 | /// @} |
576 | /// \name Assignment Operators |
577 | /// @{ |
578 | |
579 | /// Copy assignment operator. |
580 | /// |
581 | /// \returns *this after assignment of RHS. |
582 | APInt &operator=(const APInt &RHS) { |
583 | // The common case (both source or dest being inline) doesn't require |
584 | // allocation or deallocation. |
585 | if (isSingleWord() && RHS.isSingleWord()) { |
586 | U.VAL = RHS.U.VAL; |
587 | BitWidth = RHS.BitWidth; |
588 | return *this; |
589 | } |
590 | |
591 | assignSlowCase(RHS); |
592 | return *this; |
593 | } |
594 | |
595 | /// Move assignment operator. |
596 | APInt &operator=(APInt &&that) { |
597 | #ifdef EXPENSIVE_CHECKS |
598 | // Some std::shuffle implementations still do self-assignment. |
599 | if (this == &that) |
600 | return *this; |
601 | #endif |
602 | assert(this != &that && "Self-move not supported")(static_cast <bool> (this != &that && "Self-move not supported" ) ? void (0) : __assert_fail ("this != &that && \"Self-move not supported\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/include/llvm/ADT/APInt.h" , 602, __extension__ __PRETTY_FUNCTION__)); |
603 | if (!isSingleWord()) |
604 | delete[] U.pVal; |
605 | |
606 | // Use memcpy so that type based alias analysis sees both VAL and pVal |
607 | // as modified. |
608 | memcpy(&U, &that.U, sizeof(U)); |
609 | |
610 | BitWidth = that.BitWidth; |
611 | that.BitWidth = 0; |
612 | return *this; |
613 | } |
614 | |
615 | /// Assignment operator. |
616 | /// |
617 | /// The RHS value is assigned to *this. If the significant bits in RHS exceed |
618 | /// the bit width, the excess bits are truncated. If the bit width is larger |
619 | /// than 64, the value is zero filled in the unspecified high order bits. |
620 | /// |
621 | /// \returns *this after assignment of RHS value. |
622 | APInt &operator=(uint64_t RHS) { |
623 | if (isSingleWord()) { |
624 | U.VAL = RHS; |
625 | return clearUnusedBits(); |
626 | } |
627 | U.pVal[0] = RHS; |
628 | memset(U.pVal + 1, 0, (getNumWords() - 1) * APINT_WORD_SIZE); |
629 | return *this; |
630 | } |
631 | |
632 | /// Bitwise AND assignment operator. |
633 | /// |
634 | /// Performs a bitwise AND operation on this APInt and RHS. The result is |
635 | /// assigned to *this. |
636 | /// |
637 | /// \returns *this after ANDing with RHS. |
638 | APInt &operator&=(const APInt &RHS) { |
639 | assert(BitWidth == RHS.BitWidth && "Bit widths must be the same")(static_cast <bool> (BitWidth == RHS.BitWidth && "Bit widths must be the same") ? void (0) : __assert_fail ("BitWidth == RHS.BitWidth && \"Bit widths must be the same\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/include/llvm/ADT/APInt.h" , 639, __extension__ __PRETTY_FUNCTION__)); |
640 | if (isSingleWord()) |
641 | U.VAL &= RHS.U.VAL; |
642 | else |
643 | andAssignSlowCase(RHS); |
644 | return *this; |
645 | } |
646 | |
647 | /// Bitwise AND assignment operator. |
648 | /// |
649 | /// Performs a bitwise AND operation on this APInt and RHS. RHS is |
650 | /// logically zero-extended or truncated to match the bit-width of |
651 | /// the LHS. |
652 | APInt &operator&=(uint64_t RHS) { |
653 | if (isSingleWord()) { |
654 | U.VAL &= RHS; |
655 | return *this; |
656 | } |
657 | U.pVal[0] &= RHS; |
658 | memset(U.pVal + 1, 0, (getNumWords() - 1) * APINT_WORD_SIZE); |
659 | return *this; |
660 | } |
661 | |
662 | /// Bitwise OR assignment operator. |
663 | /// |
664 | /// Performs a bitwise OR operation on this APInt and RHS. The result is |
665 | /// assigned *this; |
666 | /// |
667 | /// \returns *this after ORing with RHS. |
668 | APInt &operator|=(const APInt &RHS) { |
669 | assert(BitWidth == RHS.BitWidth && "Bit widths must be the same")(static_cast <bool> (BitWidth == RHS.BitWidth && "Bit widths must be the same") ? void (0) : __assert_fail ("BitWidth == RHS.BitWidth && \"Bit widths must be the same\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/include/llvm/ADT/APInt.h" , 669, __extension__ __PRETTY_FUNCTION__)); |
670 | if (isSingleWord()) |
671 | U.VAL |= RHS.U.VAL; |
672 | else |
673 | orAssignSlowCase(RHS); |
674 | return *this; |
675 | } |
676 | |
677 | /// Bitwise OR assignment operator. |
678 | /// |
679 | /// Performs a bitwise OR operation on this APInt and RHS. RHS is |
680 | /// logically zero-extended or truncated to match the bit-width of |
681 | /// the LHS. |
682 | APInt &operator|=(uint64_t RHS) { |
683 | if (isSingleWord()) { |
684 | U.VAL |= RHS; |
685 | return clearUnusedBits(); |
686 | } |
687 | U.pVal[0] |= RHS; |
688 | return *this; |
689 | } |
690 | |
691 | /// Bitwise XOR assignment operator. |
692 | /// |
693 | /// Performs a bitwise XOR operation on this APInt and RHS. The result is |
694 | /// assigned to *this. |
695 | /// |
696 | /// \returns *this after XORing with RHS. |
697 | APInt &operator^=(const APInt &RHS) { |
698 | assert(BitWidth == RHS.BitWidth && "Bit widths must be the same")(static_cast <bool> (BitWidth == RHS.BitWidth && "Bit widths must be the same") ? void (0) : __assert_fail ("BitWidth == RHS.BitWidth && \"Bit widths must be the same\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/include/llvm/ADT/APInt.h" , 698, __extension__ __PRETTY_FUNCTION__)); |
699 | if (isSingleWord()) |
700 | U.VAL ^= RHS.U.VAL; |
701 | else |
702 | xorAssignSlowCase(RHS); |
703 | return *this; |
704 | } |
705 | |
706 | /// Bitwise XOR assignment operator. |
707 | /// |
708 | /// Performs a bitwise XOR operation on this APInt and RHS. RHS is |
709 | /// logically zero-extended or truncated to match the bit-width of |
710 | /// the LHS. |
711 | APInt &operator^=(uint64_t RHS) { |
712 | if (isSingleWord()) { |
713 | U.VAL ^= RHS; |
714 | return clearUnusedBits(); |
715 | } |
716 | U.pVal[0] ^= RHS; |
717 | return *this; |
718 | } |
719 | |
720 | /// Multiplication assignment operator. |
721 | /// |
722 | /// Multiplies this APInt by RHS and assigns the result to *this. |
723 | /// |
724 | /// \returns *this |
725 | APInt &operator*=(const APInt &RHS); |
726 | APInt &operator*=(uint64_t RHS); |
727 | |
728 | /// Addition assignment operator. |
729 | /// |
730 | /// Adds RHS to *this and assigns the result to *this. |
731 | /// |
732 | /// \returns *this |
733 | APInt &operator+=(const APInt &RHS); |
734 | APInt &operator+=(uint64_t RHS); |
735 | |
736 | /// Subtraction assignment operator. |
737 | /// |
738 | /// Subtracts RHS from *this and assigns the result to *this. |
739 | /// |
740 | /// \returns *this |
741 | APInt &operator-=(const APInt &RHS); |
742 | APInt &operator-=(uint64_t RHS); |
743 | |
744 | /// Left-shift assignment function. |
745 | /// |
746 | /// Shifts *this left by shiftAmt and assigns the result to *this. |
747 | /// |
748 | /// \returns *this after shifting left by ShiftAmt |
749 | APInt &operator<<=(unsigned ShiftAmt) { |
750 | assert(ShiftAmt <= BitWidth && "Invalid shift amount")(static_cast <bool> (ShiftAmt <= BitWidth && "Invalid shift amount") ? void (0) : __assert_fail ("ShiftAmt <= BitWidth && \"Invalid shift amount\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/include/llvm/ADT/APInt.h" , 750, __extension__ __PRETTY_FUNCTION__)); |
751 | if (isSingleWord()) { |
752 | if (ShiftAmt == BitWidth) |
753 | U.VAL = 0; |
754 | else |
755 | U.VAL <<= ShiftAmt; |
756 | return clearUnusedBits(); |
757 | } |
758 | shlSlowCase(ShiftAmt); |
759 | return *this; |
760 | } |
761 | |
762 | /// Left-shift assignment function. |
763 | /// |
764 | /// Shifts *this left by shiftAmt and assigns the result to *this. |
765 | /// |
766 | /// \returns *this after shifting left by ShiftAmt |
767 | APInt &operator<<=(const APInt &ShiftAmt); |
768 | |
769 | /// @} |
770 | /// \name Binary Operators |
771 | /// @{ |
772 | |
773 | /// Multiplication operator. |
774 | /// |
775 | /// Multiplies this APInt by RHS and returns the result. |
776 | APInt operator*(const APInt &RHS) const; |
777 | |
778 | /// Left logical shift operator. |
779 | /// |
780 | /// Shifts this APInt left by \p Bits and returns the result. |
781 | APInt operator<<(unsigned Bits) const { return shl(Bits); } |
782 | |
783 | /// Left logical shift operator. |
784 | /// |
785 | /// Shifts this APInt left by \p Bits and returns the result. |
786 | APInt operator<<(const APInt &Bits) const { return shl(Bits); } |
787 | |
788 | /// Arithmetic right-shift function. |
789 | /// |
790 | /// Arithmetic right-shift this APInt by shiftAmt. |
791 | APInt ashr(unsigned ShiftAmt) const { |
792 | APInt R(*this); |
793 | R.ashrInPlace(ShiftAmt); |
794 | return R; |
795 | } |
796 | |
797 | /// Arithmetic right-shift this APInt by ShiftAmt in place. |
798 | void ashrInPlace(unsigned ShiftAmt) { |
799 | assert(ShiftAmt <= BitWidth && "Invalid shift amount")(static_cast <bool> (ShiftAmt <= BitWidth && "Invalid shift amount") ? void (0) : __assert_fail ("ShiftAmt <= BitWidth && \"Invalid shift amount\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/include/llvm/ADT/APInt.h" , 799, __extension__ __PRETTY_FUNCTION__)); |
800 | if (isSingleWord()) { |
801 | int64_t SExtVAL = SignExtend64(U.VAL, BitWidth); |
802 | if (ShiftAmt == BitWidth) |
803 | U.VAL = SExtVAL >> (APINT_BITS_PER_WORD - 1); // Fill with sign bit. |
804 | else |
805 | U.VAL = SExtVAL >> ShiftAmt; |
806 | clearUnusedBits(); |
807 | return; |
808 | } |
809 | ashrSlowCase(ShiftAmt); |
810 | } |
811 | |
812 | /// Logical right-shift function. |
813 | /// |
814 | /// Logical right-shift this APInt by shiftAmt. |
815 | APInt lshr(unsigned shiftAmt) const { |
816 | APInt R(*this); |
817 | R.lshrInPlace(shiftAmt); |
818 | return R; |
819 | } |
820 | |
821 | /// Logical right-shift this APInt by ShiftAmt in place. |
822 | void lshrInPlace(unsigned ShiftAmt) { |
823 | assert(ShiftAmt <= BitWidth && "Invalid shift amount")(static_cast <bool> (ShiftAmt <= BitWidth && "Invalid shift amount") ? void (0) : __assert_fail ("ShiftAmt <= BitWidth && \"Invalid shift amount\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/include/llvm/ADT/APInt.h" , 823, __extension__ __PRETTY_FUNCTION__)); |
824 | if (isSingleWord()) { |
825 | if (ShiftAmt == BitWidth) |
826 | U.VAL = 0; |
827 | else |
828 | U.VAL >>= ShiftAmt; |
829 | return; |
830 | } |
831 | lshrSlowCase(ShiftAmt); |
832 | } |
833 | |
834 | /// Left-shift function. |
835 | /// |
836 | /// Left-shift this APInt by shiftAmt. |
837 | APInt shl(unsigned shiftAmt) const { |
838 | APInt R(*this); |
839 | R <<= shiftAmt; |
840 | return R; |
841 | } |
842 | |
843 | /// Rotate left by rotateAmt. |
844 | APInt rotl(unsigned rotateAmt) const; |
845 | |
846 | /// Rotate right by rotateAmt. |
847 | APInt rotr(unsigned rotateAmt) const; |
848 | |
849 | /// Arithmetic right-shift function. |
850 | /// |
851 | /// Arithmetic right-shift this APInt by shiftAmt. |
852 | APInt ashr(const APInt &ShiftAmt) const { |
853 | APInt R(*this); |
854 | R.ashrInPlace(ShiftAmt); |
855 | return R; |
856 | } |
857 | |
858 | /// Arithmetic right-shift this APInt by shiftAmt in place. |
859 | void ashrInPlace(const APInt &shiftAmt); |
860 | |
861 | /// Logical right-shift function. |
862 | /// |
863 | /// Logical right-shift this APInt by shiftAmt. |
864 | APInt lshr(const APInt &ShiftAmt) const { |
865 | APInt R(*this); |
866 | R.lshrInPlace(ShiftAmt); |
867 | return R; |
868 | } |
869 | |
870 | /// Logical right-shift this APInt by ShiftAmt in place. |
871 | void lshrInPlace(const APInt &ShiftAmt); |
872 | |
873 | /// Left-shift function. |
874 | /// |
875 | /// Left-shift this APInt by shiftAmt. |
876 | APInt shl(const APInt &ShiftAmt) const { |
877 | APInt R(*this); |
878 | R <<= ShiftAmt; |
879 | return R; |
880 | } |
881 | |
882 | /// Rotate left by rotateAmt. |
883 | APInt rotl(const APInt &rotateAmt) const; |
884 | |
885 | /// Rotate right by rotateAmt. |
886 | APInt rotr(const APInt &rotateAmt) const; |
887 | |
888 | /// Concatenate the bits from "NewLSB" onto the bottom of *this. This is |
889 | /// equivalent to: |
890 | /// (this->zext(NewWidth) << NewLSB.getBitWidth()) | NewLSB.zext(NewWidth) |
891 | APInt concat(const APInt &NewLSB) const { |
892 | /// If the result will be small, then both the merged values are small. |
893 | unsigned NewWidth = getBitWidth() + NewLSB.getBitWidth(); |
894 | if (NewWidth <= APINT_BITS_PER_WORD) |
895 | return APInt(NewWidth, (U.VAL << NewLSB.getBitWidth()) | NewLSB.U.VAL); |
896 | return concatSlowCase(NewLSB); |
897 | } |
898 | |
899 | /// Unsigned division operation. |
900 | /// |
901 | /// Perform an unsigned divide operation on this APInt by RHS. Both this and |
902 | /// RHS are treated as unsigned quantities for purposes of this division. |
903 | /// |
904 | /// \returns a new APInt value containing the division result, rounded towards |
905 | /// zero. |
906 | APInt udiv(const APInt &RHS) const; |
907 | APInt udiv(uint64_t RHS) const; |
908 | |
909 | /// Signed division function for APInt. |
910 | /// |
911 | /// Signed divide this APInt by APInt RHS. |
912 | /// |
913 | /// The result is rounded towards zero. |
914 | APInt sdiv(const APInt &RHS) const; |
915 | APInt sdiv(int64_t RHS) const; |
916 | |
917 | /// Unsigned remainder operation. |
918 | /// |
919 | /// Perform an unsigned remainder operation on this APInt with RHS being the |
920 | /// divisor. Both this and RHS are treated as unsigned quantities for purposes |
921 | /// of this operation. Note that this is a true remainder operation and not a |
922 | /// modulo operation because the sign follows the sign of the dividend which |
923 | /// is *this. |
924 | /// |
925 | /// \returns a new APInt value containing the remainder result |
926 | APInt urem(const APInt &RHS) const; |
927 | uint64_t urem(uint64_t RHS) const; |
928 | |
929 | /// Function for signed remainder operation. |
930 | /// |
931 | /// Signed remainder operation on APInt. |
932 | APInt srem(const APInt &RHS) const; |
933 | int64_t srem(int64_t RHS) const; |
934 | |
935 | /// Dual division/remainder interface. |
936 | /// |
937 | /// Sometimes it is convenient to divide two APInt values and obtain both the |
938 | /// quotient and remainder. This function does both operations in the same |
939 | /// computation making it a little more efficient. The pair of input arguments |
940 | /// may overlap with the pair of output arguments. It is safe to call |
941 | /// udivrem(X, Y, X, Y), for example. |
942 | static void udivrem(const APInt &LHS, const APInt &RHS, APInt &Quotient, |
943 | APInt &Remainder); |
944 | static void udivrem(const APInt &LHS, uint64_t RHS, APInt &Quotient, |
945 | uint64_t &Remainder); |
946 | |
947 | static void sdivrem(const APInt &LHS, const APInt &RHS, APInt &Quotient, |
948 | APInt &Remainder); |
949 | static void sdivrem(const APInt &LHS, int64_t RHS, APInt &Quotient, |
950 | int64_t &Remainder); |
951 | |
952 | // Operations that return overflow indicators. |
953 | APInt sadd_ov(const APInt &RHS, bool &Overflow) const; |
954 | APInt uadd_ov(const APInt &RHS, bool &Overflow) const; |
955 | APInt ssub_ov(const APInt &RHS, bool &Overflow) const; |
956 | APInt usub_ov(const APInt &RHS, bool &Overflow) const; |
957 | APInt sdiv_ov(const APInt &RHS, bool &Overflow) const; |
958 | APInt smul_ov(const APInt &RHS, bool &Overflow) const; |
959 | APInt umul_ov(const APInt &RHS, bool &Overflow) const; |
960 | APInt sshl_ov(const APInt &Amt, bool &Overflow) const; |
961 | APInt ushl_ov(const APInt &Amt, bool &Overflow) const; |
962 | |
963 | // Operations that saturate |
964 | APInt sadd_sat(const APInt &RHS) const; |
965 | APInt uadd_sat(const APInt &RHS) const; |
966 | APInt ssub_sat(const APInt &RHS) const; |
967 | APInt usub_sat(const APInt &RHS) const; |
968 | APInt smul_sat(const APInt &RHS) const; |
969 | APInt umul_sat(const APInt &RHS) const; |
970 | APInt sshl_sat(const APInt &RHS) const; |
971 | APInt ushl_sat(const APInt &RHS) const; |
972 | |
973 | /// Array-indexing support. |
974 | /// |
975 | /// \returns the bit value at bitPosition |
976 | bool operator[](unsigned bitPosition) const { |
977 | assert(bitPosition < getBitWidth() && "Bit position out of bounds!")(static_cast <bool> (bitPosition < getBitWidth() && "Bit position out of bounds!") ? void (0) : __assert_fail ("bitPosition < getBitWidth() && \"Bit position out of bounds!\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/include/llvm/ADT/APInt.h" , 977, __extension__ __PRETTY_FUNCTION__)); |
978 | return (maskBit(bitPosition) & getWord(bitPosition)) != 0; |
979 | } |
980 | |
981 | /// @} |
982 | /// \name Comparison Operators |
983 | /// @{ |
984 | |
985 | /// Equality operator. |
986 | /// |
987 | /// Compares this APInt with RHS for the validity of the equality |
988 | /// relationship. |
989 | bool operator==(const APInt &RHS) const { |
990 | assert(BitWidth == RHS.BitWidth && "Comparison requires equal bit widths")(static_cast <bool> (BitWidth == RHS.BitWidth && "Comparison requires equal bit widths") ? void (0) : __assert_fail ("BitWidth == RHS.BitWidth && \"Comparison requires equal bit widths\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/include/llvm/ADT/APInt.h" , 990, __extension__ __PRETTY_FUNCTION__)); |
991 | if (isSingleWord()) |
992 | return U.VAL == RHS.U.VAL; |
993 | return equalSlowCase(RHS); |
994 | } |
995 | |
996 | /// Equality operator. |
997 | /// |
998 | /// Compares this APInt with a uint64_t for the validity of the equality |
999 | /// relationship. |
1000 | /// |
1001 | /// \returns true if *this == Val |
1002 | bool operator==(uint64_t Val) const { |
1003 | return (isSingleWord() || getActiveBits() <= 64) && getZExtValue() == Val; |
1004 | } |
1005 | |
1006 | /// Equality comparison. |
1007 | /// |
1008 | /// Compares this APInt with RHS for the validity of the equality |
1009 | /// relationship. |
1010 | /// |
1011 | /// \returns true if *this == Val |
1012 | bool eq(const APInt &RHS) const { return (*this) == RHS; } |
1013 | |
1014 | /// Inequality operator. |
1015 | /// |
1016 | /// Compares this APInt with RHS for the validity of the inequality |
1017 | /// relationship. |
1018 | /// |
1019 | /// \returns true if *this != Val |
1020 | bool operator!=(const APInt &RHS) const { return !((*this) == RHS); } |
1021 | |
1022 | /// Inequality operator. |
1023 | /// |
1024 | /// Compares this APInt with a uint64_t for the validity of the inequality |
1025 | /// relationship. |
1026 | /// |
1027 | /// \returns true if *this != Val |
1028 | bool operator!=(uint64_t Val) const { return !((*this) == Val); } |
1029 | |
1030 | /// Inequality comparison |
1031 | /// |
1032 | /// Compares this APInt with RHS for the validity of the inequality |
1033 | /// relationship. |
1034 | /// |
1035 | /// \returns true if *this != Val |
1036 | bool ne(const APInt &RHS) const { return !((*this) == RHS); } |
1037 | |
1038 | /// Unsigned less than comparison |
1039 | /// |
1040 | /// Regards both *this and RHS as unsigned quantities and compares them for |
1041 | /// the validity of the less-than relationship. |
1042 | /// |
1043 | /// \returns true if *this < RHS when both are considered unsigned. |
1044 | bool ult(const APInt &RHS) const { return compare(RHS) < 0; } |
1045 | |
1046 | /// Unsigned less than comparison |
1047 | /// |
1048 | /// Regards both *this as an unsigned quantity and compares it with RHS for |
1049 | /// the validity of the less-than relationship. |
1050 | /// |
1051 | /// \returns true if *this < RHS when considered unsigned. |
1052 | bool ult(uint64_t RHS) const { |
1053 | // Only need to check active bits if not a single word. |
1054 | return (isSingleWord() || getActiveBits() <= 64) && getZExtValue() < RHS; |
1055 | } |
1056 | |
1057 | /// Signed less than comparison |
1058 | /// |
1059 | /// Regards both *this and RHS as signed quantities and compares them for |
1060 | /// validity of the less-than relationship. |
1061 | /// |
1062 | /// \returns true if *this < RHS when both are considered signed. |
1063 | bool slt(const APInt &RHS) const { return compareSigned(RHS) < 0; } |
1064 | |
1065 | /// Signed less than comparison |
1066 | /// |
1067 | /// Regards both *this as a signed quantity and compares it with RHS for |
1068 | /// the validity of the less-than relationship. |
1069 | /// |
1070 | /// \returns true if *this < RHS when considered signed. |
1071 | bool slt(int64_t RHS) const { |
1072 | return (!isSingleWord() && getMinSignedBits() > 64) ? isNegative() |
1073 | : getSExtValue() < RHS; |
1074 | } |
1075 | |
1076 | /// Unsigned less or equal comparison |
1077 | /// |
1078 | /// Regards both *this and RHS as unsigned quantities and compares them for |
1079 | /// validity of the less-or-equal relationship. |
1080 | /// |
1081 | /// \returns true if *this <= RHS when both are considered unsigned. |
1082 | bool ule(const APInt &RHS) const { return compare(RHS) <= 0; } |
1083 | |
1084 | /// Unsigned less or equal comparison |
1085 | /// |
1086 | /// Regards both *this as an unsigned quantity and compares it with RHS for |
1087 | /// the validity of the less-or-equal relationship. |
1088 | /// |
1089 | /// \returns true if *this <= RHS when considered unsigned. |
1090 | bool ule(uint64_t RHS) const { return !ugt(RHS); } |
1091 | |
1092 | /// Signed less or equal comparison |
1093 | /// |
1094 | /// Regards both *this and RHS as signed quantities and compares them for |
1095 | /// validity of the less-or-equal relationship. |
1096 | /// |
1097 | /// \returns true if *this <= RHS when both are considered signed. |
1098 | bool sle(const APInt &RHS) const { return compareSigned(RHS) <= 0; } |
1099 | |
1100 | /// Signed less or equal comparison |
1101 | /// |
1102 | /// Regards both *this as a signed quantity and compares it with RHS for the |
1103 | /// validity of the less-or-equal relationship. |
1104 | /// |
1105 | /// \returns true if *this <= RHS when considered signed. |
1106 | bool sle(uint64_t RHS) const { return !sgt(RHS); } |
1107 | |
1108 | /// Unsigned greater than comparison |
1109 | /// |
1110 | /// Regards both *this and RHS as unsigned quantities and compares them for |
1111 | /// the validity of the greater-than relationship. |
1112 | /// |
1113 | /// \returns true if *this > RHS when both are considered unsigned. |
1114 | bool ugt(const APInt &RHS) const { return !ule(RHS); } |
1115 | |
1116 | /// Unsigned greater than comparison |
1117 | /// |
1118 | /// Regards both *this as an unsigned quantity and compares it with RHS for |
1119 | /// the validity of the greater-than relationship. |
1120 | /// |
1121 | /// \returns true if *this > RHS when considered unsigned. |
1122 | bool ugt(uint64_t RHS) const { |
1123 | // Only need to check active bits if not a single word. |
1124 | return (!isSingleWord() && getActiveBits() > 64) || getZExtValue() > RHS; |
1125 | } |
1126 | |
1127 | /// Signed greater than comparison |
1128 | /// |
1129 | /// Regards both *this and RHS as signed quantities and compares them for the |
1130 | /// validity of the greater-than relationship. |
1131 | /// |
1132 | /// \returns true if *this > RHS when both are considered signed. |
1133 | bool sgt(const APInt &RHS) const { return !sle(RHS); } |
1134 | |
1135 | /// Signed greater than comparison |
1136 | /// |
1137 | /// Regards both *this as a signed quantity and compares it with RHS for |
1138 | /// the validity of the greater-than relationship. |
1139 | /// |
1140 | /// \returns true if *this > RHS when considered signed. |
1141 | bool sgt(int64_t RHS) const { |
1142 | return (!isSingleWord() && getMinSignedBits() > 64) ? !isNegative() |
1143 | : getSExtValue() > RHS; |
1144 | } |
1145 | |
1146 | /// Unsigned greater or equal comparison |
1147 | /// |
1148 | /// Regards both *this and RHS as unsigned quantities and compares them for |
1149 | /// validity of the greater-or-equal relationship. |
1150 | /// |
1151 | /// \returns true if *this >= RHS when both are considered unsigned. |
1152 | bool uge(const APInt &RHS) const { return !ult(RHS); } |
1153 | |
1154 | /// Unsigned greater or equal comparison |
1155 | /// |
1156 | /// Regards both *this as an unsigned quantity and compares it with RHS for |
1157 | /// the validity of the greater-or-equal relationship. |
1158 | /// |
1159 | /// \returns true if *this >= RHS when considered unsigned. |
1160 | bool uge(uint64_t RHS) const { return !ult(RHS); } |
1161 | |
1162 | /// Signed greater or equal comparison |
1163 | /// |
1164 | /// Regards both *this and RHS as signed quantities and compares them for |
1165 | /// validity of the greater-or-equal relationship. |
1166 | /// |
1167 | /// \returns true if *this >= RHS when both are considered signed. |
1168 | bool sge(const APInt &RHS) const { return !slt(RHS); } |
1169 | |
1170 | /// Signed greater or equal comparison |
1171 | /// |
1172 | /// Regards both *this as a signed quantity and compares it with RHS for |
1173 | /// the validity of the greater-or-equal relationship. |
1174 | /// |
1175 | /// \returns true if *this >= RHS when considered signed. |
1176 | bool sge(int64_t RHS) const { return !slt(RHS); } |
1177 | |
1178 | /// This operation tests if there are any pairs of corresponding bits |
1179 | /// between this APInt and RHS that are both set. |
1180 | bool intersects(const APInt &RHS) const { |
1181 | assert(BitWidth == RHS.BitWidth && "Bit widths must be the same")(static_cast <bool> (BitWidth == RHS.BitWidth && "Bit widths must be the same") ? void (0) : __assert_fail ("BitWidth == RHS.BitWidth && \"Bit widths must be the same\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/include/llvm/ADT/APInt.h" , 1181, __extension__ __PRETTY_FUNCTION__)); |
1182 | if (isSingleWord()) |
1183 | return (U.VAL & RHS.U.VAL) != 0; |
1184 | return intersectsSlowCase(RHS); |
1185 | } |
1186 | |
1187 | /// This operation checks that all bits set in this APInt are also set in RHS. |
1188 | bool isSubsetOf(const APInt &RHS) const { |
1189 | assert(BitWidth == RHS.BitWidth && "Bit widths must be the same")(static_cast <bool> (BitWidth == RHS.BitWidth && "Bit widths must be the same") ? void (0) : __assert_fail ("BitWidth == RHS.BitWidth && \"Bit widths must be the same\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/include/llvm/ADT/APInt.h" , 1189, __extension__ __PRETTY_FUNCTION__)); |
1190 | if (isSingleWord()) |
1191 | return (U.VAL & ~RHS.U.VAL) == 0; |
1192 | return isSubsetOfSlowCase(RHS); |
1193 | } |
1194 | |
1195 | /// @} |
1196 | /// \name Resizing Operators |
1197 | /// @{ |
1198 | |
1199 | /// Truncate to new width. |
1200 | /// |
1201 | /// Truncate the APInt to a specified width. It is an error to specify a width |
1202 | /// that is greater than or equal to the current width. |
1203 | APInt trunc(unsigned width) const; |
1204 | |
1205 | /// Truncate to new width with unsigned saturation. |
1206 | /// |
1207 | /// If the APInt, treated as unsigned integer, can be losslessly truncated to |
1208 | /// the new bitwidth, then return truncated APInt. Else, return max value. |
1209 | APInt truncUSat(unsigned width) const; |
1210 | |
1211 | /// Truncate to new width with signed saturation. |
1212 | /// |
1213 | /// If this APInt, treated as signed integer, can be losslessly truncated to |
1214 | /// the new bitwidth, then return truncated APInt. Else, return either |
1215 | /// signed min value if the APInt was negative, or signed max value. |
1216 | APInt truncSSat(unsigned width) const; |
1217 | |
1218 | /// Sign extend to a new width. |
1219 | /// |
1220 | /// This operation sign extends the APInt to a new width. If the high order |
1221 | /// bit is set, the fill on the left will be done with 1 bits, otherwise zero. |
1222 | /// It is an error to specify a width that is less than or equal to the |
1223 | /// current width. |
1224 | APInt sext(unsigned width) const; |
1225 | |
1226 | /// Zero extend to a new width. |
1227 | /// |
1228 | /// This operation zero extends the APInt to a new width. The high order bits |
1229 | /// are filled with 0 bits. It is an error to specify a width that is less |
1230 | /// than or equal to the current width. |
1231 | APInt zext(unsigned width) const; |
1232 | |
1233 | /// Sign extend or truncate to width |
1234 | /// |
1235 | /// Make this APInt have the bit width given by \p width. The value is sign |
1236 | /// extended, truncated, or left alone to make it that width. |
1237 | APInt sextOrTrunc(unsigned width) const; |
1238 | |
1239 | /// Zero extend or truncate to width |
1240 | /// |
1241 | /// Make this APInt have the bit width given by \p width. The value is zero |
1242 | /// extended, truncated, or left alone to make it that width. |
1243 | APInt zextOrTrunc(unsigned width) const; |
1244 | |
1245 | /// Truncate to width |
1246 | /// |
1247 | /// Make this APInt have the bit width given by \p width. The value is |
1248 | /// truncated or left alone to make it that width. |
1249 | APInt truncOrSelf(unsigned width) const; |
1250 | |
1251 | /// Sign extend or truncate to width |
1252 | /// |
1253 | /// Make this APInt have the bit width given by \p width. The value is sign |
1254 | /// extended, or left alone to make it that width. |
1255 | APInt sextOrSelf(unsigned width) const; |
1256 | |
1257 | /// Zero extend or truncate to width |
1258 | /// |
1259 | /// Make this APInt have the bit width given by \p width. The value is zero |
1260 | /// extended, or left alone to make it that width. |
1261 | APInt zextOrSelf(unsigned width) const; |
1262 | |
1263 | /// @} |
1264 | /// \name Bit Manipulation Operators |
1265 | /// @{ |
1266 | |
1267 | /// Set every bit to 1. |
1268 | void setAllBits() { |
1269 | if (isSingleWord()) |
1270 | U.VAL = WORDTYPE_MAX; |
1271 | else |
1272 | // Set all the bits in all the words. |
1273 | memset(U.pVal, -1, getNumWords() * APINT_WORD_SIZE); |
1274 | // Clear the unused ones |
1275 | clearUnusedBits(); |
1276 | } |
1277 | |
1278 | /// Set the given bit to 1 whose position is given as "bitPosition". |
1279 | void setBit(unsigned BitPosition) { |
1280 | assert(BitPosition < BitWidth && "BitPosition out of range")(static_cast <bool> (BitPosition < BitWidth && "BitPosition out of range") ? void (0) : __assert_fail ("BitPosition < BitWidth && \"BitPosition out of range\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/include/llvm/ADT/APInt.h" , 1280, __extension__ __PRETTY_FUNCTION__)); |
1281 | WordType Mask = maskBit(BitPosition); |
1282 | if (isSingleWord()) |
1283 | U.VAL |= Mask; |
1284 | else |
1285 | U.pVal[whichWord(BitPosition)] |= Mask; |
1286 | } |
1287 | |
1288 | /// Set the sign bit to 1. |
1289 | void setSignBit() { setBit(BitWidth - 1); } |
1290 | |
1291 | /// Set a given bit to a given value. |
1292 | void setBitVal(unsigned BitPosition, bool BitValue) { |
1293 | if (BitValue) |
1294 | setBit(BitPosition); |
1295 | else |
1296 | clearBit(BitPosition); |
1297 | } |
1298 | |
1299 | /// Set the bits from loBit (inclusive) to hiBit (exclusive) to 1. |
1300 | /// This function handles "wrap" case when \p loBit >= \p hiBit, and calls |
1301 | /// setBits when \p loBit < \p hiBit. |
1302 | /// For \p loBit == \p hiBit wrap case, set every bit to 1. |
1303 | void setBitsWithWrap(unsigned loBit, unsigned hiBit) { |
1304 | assert(hiBit <= BitWidth && "hiBit out of range")(static_cast <bool> (hiBit <= BitWidth && "hiBit out of range" ) ? void (0) : __assert_fail ("hiBit <= BitWidth && \"hiBit out of range\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/include/llvm/ADT/APInt.h" , 1304, __extension__ __PRETTY_FUNCTION__)); |
1305 | assert(loBit <= BitWidth && "loBit out of range")(static_cast <bool> (loBit <= BitWidth && "loBit out of range" ) ? void (0) : __assert_fail ("loBit <= BitWidth && \"loBit out of range\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/include/llvm/ADT/APInt.h" , 1305, __extension__ __PRETTY_FUNCTION__)); |
1306 | if (loBit < hiBit) { |
1307 | setBits(loBit, hiBit); |
1308 | return; |
1309 | } |
1310 | setLowBits(hiBit); |
1311 | setHighBits(BitWidth - loBit); |
1312 | } |
1313 | |
1314 | /// Set the bits from loBit (inclusive) to hiBit (exclusive) to 1. |
1315 | /// This function handles case when \p loBit <= \p hiBit. |
1316 | void setBits(unsigned loBit, unsigned hiBit) { |
1317 | assert(hiBit <= BitWidth && "hiBit out of range")(static_cast <bool> (hiBit <= BitWidth && "hiBit out of range" ) ? void (0) : __assert_fail ("hiBit <= BitWidth && \"hiBit out of range\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/include/llvm/ADT/APInt.h" , 1317, __extension__ __PRETTY_FUNCTION__)); |
1318 | assert(loBit <= BitWidth && "loBit out of range")(static_cast <bool> (loBit <= BitWidth && "loBit out of range" ) ? void (0) : __assert_fail ("loBit <= BitWidth && \"loBit out of range\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/include/llvm/ADT/APInt.h" , 1318, __extension__ __PRETTY_FUNCTION__)); |
1319 | assert(loBit <= hiBit && "loBit greater than hiBit")(static_cast <bool> (loBit <= hiBit && "loBit greater than hiBit" ) ? void (0) : __assert_fail ("loBit <= hiBit && \"loBit greater than hiBit\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/include/llvm/ADT/APInt.h" , 1319, __extension__ __PRETTY_FUNCTION__)); |
1320 | if (loBit == hiBit) |
1321 | return; |
1322 | if (loBit < APINT_BITS_PER_WORD && hiBit <= APINT_BITS_PER_WORD) { |
1323 | uint64_t mask = WORDTYPE_MAX >> (APINT_BITS_PER_WORD - (hiBit - loBit)); |
1324 | mask <<= loBit; |
1325 | if (isSingleWord()) |
1326 | U.VAL |= mask; |
1327 | else |
1328 | U.pVal[0] |= mask; |
1329 | } else { |
1330 | setBitsSlowCase(loBit, hiBit); |
1331 | } |
1332 | } |
1333 | |
1334 | /// Set the top bits starting from loBit. |
1335 | void setBitsFrom(unsigned loBit) { return setBits(loBit, BitWidth); } |
1336 | |
1337 | /// Set the bottom loBits bits. |
1338 | void setLowBits(unsigned loBits) { return setBits(0, loBits); } |
1339 | |
1340 | /// Set the top hiBits bits. |
1341 | void setHighBits(unsigned hiBits) { |
1342 | return setBits(BitWidth - hiBits, BitWidth); |
1343 | } |
1344 | |
1345 | /// Set every bit to 0. |
1346 | void clearAllBits() { |
1347 | if (isSingleWord()) |
1348 | U.VAL = 0; |
1349 | else |
1350 | memset(U.pVal, 0, getNumWords() * APINT_WORD_SIZE); |
1351 | } |
1352 | |
1353 | /// Set a given bit to 0. |
1354 | /// |
1355 | /// Set the given bit to 0 whose position is given as "bitPosition". |
1356 | void clearBit(unsigned BitPosition) { |
1357 | assert(BitPosition < BitWidth && "BitPosition out of range")(static_cast <bool> (BitPosition < BitWidth && "BitPosition out of range") ? void (0) : __assert_fail ("BitPosition < BitWidth && \"BitPosition out of range\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/include/llvm/ADT/APInt.h" , 1357, __extension__ __PRETTY_FUNCTION__)); |
1358 | WordType Mask = ~maskBit(BitPosition); |
1359 | if (isSingleWord()) |
1360 | U.VAL &= Mask; |
1361 | else |
1362 | U.pVal[whichWord(BitPosition)] &= Mask; |
1363 | } |
1364 | |
1365 | /// Set bottom loBits bits to 0. |
1366 | void clearLowBits(unsigned loBits) { |
1367 | assert(loBits <= BitWidth && "More bits than bitwidth")(static_cast <bool> (loBits <= BitWidth && "More bits than bitwidth" ) ? void (0) : __assert_fail ("loBits <= BitWidth && \"More bits than bitwidth\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/include/llvm/ADT/APInt.h" , 1367, __extension__ __PRETTY_FUNCTION__)); |
1368 | APInt Keep = getHighBitsSet(BitWidth, BitWidth - loBits); |
1369 | *this &= Keep; |
1370 | } |
1371 | |
1372 | /// Set the sign bit to 0. |
1373 | void clearSignBit() { clearBit(BitWidth - 1); } |
1374 | |
1375 | /// Toggle every bit to its opposite value. |
1376 | void flipAllBits() { |
1377 | if (isSingleWord()) { |
1378 | U.VAL ^= WORDTYPE_MAX; |
1379 | clearUnusedBits(); |
1380 | } else { |
1381 | flipAllBitsSlowCase(); |
1382 | } |
1383 | } |
1384 | |
1385 | /// Toggles a given bit to its opposite value. |
1386 | /// |
1387 | /// Toggle a given bit to its opposite value whose position is given |
1388 | /// as "bitPosition". |
1389 | void flipBit(unsigned bitPosition); |
1390 | |
1391 | /// Negate this APInt in place. |
1392 | void negate() { |
1393 | flipAllBits(); |
1394 | ++(*this); |
1395 | } |
1396 | |
1397 | /// Insert the bits from a smaller APInt starting at bitPosition. |
1398 | void insertBits(const APInt &SubBits, unsigned bitPosition); |
1399 | void insertBits(uint64_t SubBits, unsigned bitPosition, unsigned numBits); |
1400 | |
1401 | /// Return an APInt with the extracted bits [bitPosition,bitPosition+numBits). |
1402 | APInt extractBits(unsigned numBits, unsigned bitPosition) const; |
1403 | uint64_t extractBitsAsZExtValue(unsigned numBits, unsigned bitPosition) const; |
1404 | |
1405 | /// @} |
1406 | /// \name Value Characterization Functions |
1407 | /// @{ |
1408 | |
1409 | /// Return the number of bits in the APInt. |
1410 | unsigned getBitWidth() const { return BitWidth; } |
1411 | |
1412 | /// Get the number of words. |
1413 | /// |
1414 | /// Here one word's bitwidth equals to that of uint64_t. |
1415 | /// |
1416 | /// \returns the number of words to hold the integer value of this APInt. |
1417 | unsigned getNumWords() const { return getNumWords(BitWidth); } |
1418 | |
1419 | /// Get the number of words. |
1420 | /// |
1421 | /// *NOTE* Here one word's bitwidth equals to that of uint64_t. |
1422 | /// |
1423 | /// \returns the number of words to hold the integer value with a given bit |
1424 | /// width. |
1425 | static unsigned getNumWords(unsigned BitWidth) { |
1426 | return ((uint64_t)BitWidth + APINT_BITS_PER_WORD - 1) / APINT_BITS_PER_WORD; |
1427 | } |
1428 | |
1429 | /// Compute the number of active bits in the value |
1430 | /// |
1431 | /// This function returns the number of active bits which is defined as the |
1432 | /// bit width minus the number of leading zeros. This is used in several |
1433 | /// computations to see how "wide" the value is. |
1434 | unsigned getActiveBits() const { return BitWidth - countLeadingZeros(); } |
1435 | |
1436 | /// Compute the number of active words in the value of this APInt. |
1437 | /// |
1438 | /// This is used in conjunction with getActiveData to extract the raw value of |
1439 | /// the APInt. |
1440 | unsigned getActiveWords() const { |
1441 | unsigned numActiveBits = getActiveBits(); |
1442 | return numActiveBits ? whichWord(numActiveBits - 1) + 1 : 1; |
1443 | } |
1444 | |
1445 | /// Get the minimum bit size for this signed APInt |
1446 | /// |
1447 | /// Computes the minimum bit width for this APInt while considering it to be a |
1448 | /// signed (and probably negative) value. If the value is not negative, this |
1449 | /// function returns the same value as getActiveBits()+1. Otherwise, it |
1450 | /// returns the smallest bit width that will retain the negative value. For |
1451 | /// example, -1 can be written as 0b1 or 0xFFFFFFFFFF. 0b1 is shorter and so |
1452 | /// for -1, this function will always return 1. |
1453 | unsigned getMinSignedBits() const { return BitWidth - getNumSignBits() + 1; } |
1454 | |
1455 | /// Get zero extended value |
1456 | /// |
1457 | /// This method attempts to return the value of this APInt as a zero extended |
1458 | /// uint64_t. The bitwidth must be <= 64 or the value must fit within a |
1459 | /// uint64_t. Otherwise an assertion will result. |
1460 | uint64_t getZExtValue() const { |
1461 | if (isSingleWord()) { |
1462 | assert(BitWidth && "zero width values not allowed")(static_cast <bool> (BitWidth && "zero width values not allowed" ) ? void (0) : __assert_fail ("BitWidth && \"zero width values not allowed\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/include/llvm/ADT/APInt.h" , 1462, __extension__ __PRETTY_FUNCTION__)); |
1463 | return U.VAL; |
1464 | } |
1465 | assert(getActiveBits() <= 64 && "Too many bits for uint64_t")(static_cast <bool> (getActiveBits() <= 64 && "Too many bits for uint64_t") ? void (0) : __assert_fail ("getActiveBits() <= 64 && \"Too many bits for uint64_t\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/include/llvm/ADT/APInt.h" , 1465, __extension__ __PRETTY_FUNCTION__)); |
1466 | return U.pVal[0]; |
1467 | } |
1468 | |
1469 | /// Get sign extended value |
1470 | /// |
1471 | /// This method attempts to return the value of this APInt as a sign extended |
1472 | /// int64_t. The bit width must be <= 64 or the value must fit within an |
1473 | /// int64_t. Otherwise an assertion will result. |
1474 | int64_t getSExtValue() const { |
1475 | if (isSingleWord()) |
1476 | return SignExtend64(U.VAL, BitWidth); |
1477 | assert(getMinSignedBits() <= 64 && "Too many bits for int64_t")(static_cast <bool> (getMinSignedBits() <= 64 && "Too many bits for int64_t") ? void (0) : __assert_fail ("getMinSignedBits() <= 64 && \"Too many bits for int64_t\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/include/llvm/ADT/APInt.h" , 1477, __extension__ __PRETTY_FUNCTION__)); |
1478 | return int64_t(U.pVal[0]); |
1479 | } |
1480 | |
1481 | /// Get bits required for string value. |
1482 | /// |
1483 | /// This method determines how many bits are required to hold the APInt |
1484 | /// equivalent of the string given by \p str. |
1485 | static unsigned getBitsNeeded(StringRef str, uint8_t radix); |
1486 | |
1487 | /// The APInt version of the countLeadingZeros functions in |
1488 | /// MathExtras.h. |
1489 | /// |
1490 | /// It counts the number of zeros from the most significant bit to the first |
1491 | /// one bit. |
1492 | /// |
1493 | /// \returns BitWidth if the value is zero, otherwise returns the number of |
1494 | /// zeros from the most significant bit to the first one bits. |
1495 | unsigned countLeadingZeros() const { |
1496 | if (isSingleWord()) { |
1497 | unsigned unusedBits = APINT_BITS_PER_WORD - BitWidth; |
1498 | return llvm::countLeadingZeros(U.VAL) - unusedBits; |
1499 | } |
1500 | return countLeadingZerosSlowCase(); |
1501 | } |
1502 | |
1503 | /// Count the number of leading one bits. |
1504 | /// |
1505 | /// This function is an APInt version of the countLeadingOnes |
1506 | /// functions in MathExtras.h. It counts the number of ones from the most |
1507 | /// significant bit to the first zero bit. |
1508 | /// |
1509 | /// \returns 0 if the high order bit is not set, otherwise returns the number |
1510 | /// of 1 bits from the most significant to the least |
1511 | unsigned countLeadingOnes() const { |
1512 | if (isSingleWord()) { |
1513 | if (LLVM_UNLIKELY(BitWidth == 0)__builtin_expect((bool)(BitWidth == 0), false)) |
1514 | return 0; |
1515 | return llvm::countLeadingOnes(U.VAL << (APINT_BITS_PER_WORD - BitWidth)); |
1516 | } |
1517 | return countLeadingOnesSlowCase(); |
1518 | } |
1519 | |
1520 | /// Computes the number of leading bits of this APInt that are equal to its |
1521 | /// sign bit. |
1522 | unsigned getNumSignBits() const { |
1523 | return isNegative() ? countLeadingOnes() : countLeadingZeros(); |
1524 | } |
1525 | |
1526 | /// Count the number of trailing zero bits. |
1527 | /// |
1528 | /// This function is an APInt version of the countTrailingZeros |
1529 | /// functions in MathExtras.h. It counts the number of zeros from the least |
1530 | /// significant bit to the first set bit. |
1531 | /// |
1532 | /// \returns BitWidth if the value is zero, otherwise returns the number of |
1533 | /// zeros from the least significant bit to the first one bit. |
1534 | unsigned countTrailingZeros() const { |
1535 | if (isSingleWord()) { |
1536 | unsigned TrailingZeros = llvm::countTrailingZeros(U.VAL); |
1537 | return (TrailingZeros > BitWidth ? BitWidth : TrailingZeros); |
1538 | } |
1539 | return countTrailingZerosSlowCase(); |
1540 | } |
1541 | |
1542 | /// Count the number of trailing one bits. |
1543 | /// |
1544 | /// This function is an APInt version of the countTrailingOnes |
1545 | /// functions in MathExtras.h. It counts the number of ones from the least |
1546 | /// significant bit to the first zero bit. |
1547 | /// |
1548 | /// \returns BitWidth if the value is all ones, otherwise returns the number |
1549 | /// of ones from the least significant bit to the first zero bit. |
1550 | unsigned countTrailingOnes() const { |
1551 | if (isSingleWord()) |
1552 | return llvm::countTrailingOnes(U.VAL); |
1553 | return countTrailingOnesSlowCase(); |
1554 | } |
1555 | |
1556 | /// Count the number of bits set. |
1557 | /// |
1558 | /// This function is an APInt version of the countPopulation functions |
1559 | /// in MathExtras.h. It counts the number of 1 bits in the APInt value. |
1560 | /// |
1561 | /// \returns 0 if the value is zero, otherwise returns the number of set bits. |
1562 | unsigned countPopulation() const { |
1563 | if (isSingleWord()) |
1564 | return llvm::countPopulation(U.VAL); |
1565 | return countPopulationSlowCase(); |
1566 | } |
1567 | |
1568 | /// @} |
1569 | /// \name Conversion Functions |
1570 | /// @{ |
1571 | void print(raw_ostream &OS, bool isSigned) const; |
1572 | |
1573 | /// Converts an APInt to a string and append it to Str. Str is commonly a |
1574 | /// SmallString. |
1575 | void toString(SmallVectorImpl<char> &Str, unsigned Radix, bool Signed, |
1576 | bool formatAsCLiteral = false) const; |
1577 | |
1578 | /// Considers the APInt to be unsigned and converts it into a string in the |
1579 | /// radix given. The radix can be 2, 8, 10 16, or 36. |
1580 | void toStringUnsigned(SmallVectorImpl<char> &Str, unsigned Radix = 10) const { |
1581 | toString(Str, Radix, false, false); |
1582 | } |
1583 | |
1584 | /// Considers the APInt to be signed and converts it into a string in the |
1585 | /// radix given. The radix can be 2, 8, 10, 16, or 36. |
1586 | void toStringSigned(SmallVectorImpl<char> &Str, unsigned Radix = 10) const { |
1587 | toString(Str, Radix, true, false); |
1588 | } |
1589 | |
1590 | /// \returns a byte-swapped representation of this APInt Value. |
1591 | APInt byteSwap() const; |
1592 | |
1593 | /// \returns the value with the bit representation reversed of this APInt |
1594 | /// Value. |
1595 | APInt reverseBits() const; |
1596 | |
1597 | /// Converts this APInt to a double value. |
1598 | double roundToDouble(bool isSigned) const; |
1599 | |
1600 | /// Converts this unsigned APInt to a double value. |
1601 | double roundToDouble() const { return roundToDouble(false); } |
1602 | |
1603 | /// Converts this signed APInt to a double value. |
1604 | double signedRoundToDouble() const { return roundToDouble(true); } |
1605 | |
1606 | /// Converts APInt bits to a double |
1607 | /// |
1608 | /// The conversion does not do a translation from integer to double, it just |
1609 | /// re-interprets the bits as a double. Note that it is valid to do this on |
1610 | /// any bit width. Exactly 64 bits will be translated. |
1611 | double bitsToDouble() const { return BitsToDouble(getWord(0)); } |
1612 | |
1613 | /// Converts APInt bits to a float |
1614 | /// |
1615 | /// The conversion does not do a translation from integer to float, it just |
1616 | /// re-interprets the bits as a float. Note that it is valid to do this on |
1617 | /// any bit width. Exactly 32 bits will be translated. |
1618 | float bitsToFloat() const { |
1619 | return BitsToFloat(static_cast<uint32_t>(getWord(0))); |
1620 | } |
1621 | |
1622 | /// Converts a double to APInt bits. |
1623 | /// |
1624 | /// The conversion does not do a translation from double to integer, it just |
1625 | /// re-interprets the bits of the double. |
1626 | static APInt doubleToBits(double V) { |
1627 | return APInt(sizeof(double) * CHAR_BIT8, DoubleToBits(V)); |
1628 | } |
1629 | |
1630 | /// Converts a float to APInt bits. |
1631 | /// |
1632 | /// The conversion does not do a translation from float to integer, it just |
1633 | /// re-interprets the bits of the float. |
1634 | static APInt floatToBits(float V) { |
1635 | return APInt(sizeof(float) * CHAR_BIT8, FloatToBits(V)); |
1636 | } |
1637 | |
1638 | /// @} |
1639 | /// \name Mathematics Operations |
1640 | /// @{ |
1641 | |
1642 | /// \returns the floor log base 2 of this APInt. |
1643 | unsigned logBase2() const { return getActiveBits() - 1; } |
1644 | |
1645 | /// \returns the ceil log base 2 of this APInt. |
1646 | unsigned ceilLogBase2() const { |
1647 | APInt temp(*this); |
1648 | --temp; |
1649 | return temp.getActiveBits(); |
1650 | } |
1651 | |
1652 | /// \returns the nearest log base 2 of this APInt. Ties round up. |
1653 | /// |
1654 | /// NOTE: When we have a BitWidth of 1, we define: |
1655 | /// |
1656 | /// log2(0) = UINT32_MAX |
1657 | /// log2(1) = 0 |
1658 | /// |
1659 | /// to get around any mathematical concerns resulting from |
1660 | /// referencing 2 in a space where 2 does no exist. |
1661 | unsigned nearestLogBase2() const; |
1662 | |
1663 | /// \returns the log base 2 of this APInt if its an exact power of two, -1 |
1664 | /// otherwise |
1665 | int32_t exactLogBase2() const { |
1666 | if (!isPowerOf2()) |
1667 | return -1; |
1668 | return logBase2(); |
1669 | } |
1670 | |
1671 | /// Compute the square root. |
1672 | APInt sqrt() const; |
1673 | |
1674 | /// Get the absolute value. If *this is < 0 then return -(*this), otherwise |
1675 | /// *this. Note that the "most negative" signed number (e.g. -128 for 8 bit |
1676 | /// wide APInt) is unchanged due to how negation works. |
1677 | APInt abs() const { |
1678 | if (isNegative()) |
1679 | return -(*this); |
1680 | return *this; |
1681 | } |
1682 | |
1683 | /// \returns the multiplicative inverse for a given modulo. |
1684 | APInt multiplicativeInverse(const APInt &modulo) const; |
1685 | |
1686 | /// @} |
1687 | /// \name Building-block Operations for APInt and APFloat |
1688 | /// @{ |
1689 | |
1690 | // These building block operations operate on a representation of arbitrary |
1691 | // precision, two's-complement, bignum integer values. They should be |
1692 | // sufficient to implement APInt and APFloat bignum requirements. Inputs are |
1693 | // generally a pointer to the base of an array of integer parts, representing |
1694 | // an unsigned bignum, and a count of how many parts there are. |
1695 | |
1696 | /// Sets the least significant part of a bignum to the input value, and zeroes |
1697 | /// out higher parts. |
1698 | static void tcSet(WordType *, WordType, unsigned); |
1699 | |
1700 | /// Assign one bignum to another. |
1701 | static void tcAssign(WordType *, const WordType *, unsigned); |
1702 | |
1703 | /// Returns true if a bignum is zero, false otherwise. |
1704 | static bool tcIsZero(const WordType *, unsigned); |
1705 | |
1706 | /// Extract the given bit of a bignum; returns 0 or 1. Zero-based. |
1707 | static int tcExtractBit(const WordType *, unsigned bit); |
1708 | |
1709 | /// Copy the bit vector of width srcBITS from SRC, starting at bit srcLSB, to |
1710 | /// DST, of dstCOUNT parts, such that the bit srcLSB becomes the least |
1711 | /// significant bit of DST. All high bits above srcBITS in DST are |
1712 | /// zero-filled. |
1713 | static void tcExtract(WordType *, unsigned dstCount, const WordType *, |
1714 | unsigned srcBits, unsigned srcLSB); |
1715 | |
1716 | /// Set the given bit of a bignum. Zero-based. |
1717 | static void tcSetBit(WordType *, unsigned bit); |
1718 | |
1719 | /// Clear the given bit of a bignum. Zero-based. |
1720 | static void tcClearBit(WordType *, unsigned bit); |
1721 | |
1722 | /// Returns the bit number of the least or most significant set bit of a |
1723 | /// number. If the input number has no bits set -1U is returned. |
1724 | static unsigned tcLSB(const WordType *, unsigned n); |
1725 | static unsigned tcMSB(const WordType *parts, unsigned n); |
1726 | |
1727 | /// Negate a bignum in-place. |
1728 | static void tcNegate(WordType *, unsigned); |
1729 | |
1730 | /// DST += RHS + CARRY where CARRY is zero or one. Returns the carry flag. |
1731 | static WordType tcAdd(WordType *, const WordType *, WordType carry, unsigned); |
1732 | /// DST += RHS. Returns the carry flag. |
1733 | static WordType tcAddPart(WordType *, WordType, unsigned); |
1734 | |
1735 | /// DST -= RHS + CARRY where CARRY is zero or one. Returns the carry flag. |
1736 | static WordType tcSubtract(WordType *, const WordType *, WordType carry, |
1737 | unsigned); |
1738 | /// DST -= RHS. Returns the carry flag. |
1739 | static WordType tcSubtractPart(WordType *, WordType, unsigned); |
1740 | |
1741 | /// DST += SRC * MULTIPLIER + PART if add is true |
1742 | /// DST = SRC * MULTIPLIER + PART if add is false |
1743 | /// |
1744 | /// Requires 0 <= DSTPARTS <= SRCPARTS + 1. If DST overlaps SRC they must |
1745 | /// start at the same point, i.e. DST == SRC. |
1746 | /// |
1747 | /// If DSTPARTS == SRC_PARTS + 1 no overflow occurs and zero is returned. |
1748 | /// Otherwise DST is filled with the least significant DSTPARTS parts of the |
1749 | /// result, and if all of the omitted higher parts were zero return zero, |
1750 | /// otherwise overflow occurred and return one. |
1751 | static int tcMultiplyPart(WordType *dst, const WordType *src, |
1752 | WordType multiplier, WordType carry, |
1753 | unsigned srcParts, unsigned dstParts, bool add); |
1754 | |
1755 | /// DST = LHS * RHS, where DST has the same width as the operands and is |
1756 | /// filled with the least significant parts of the result. Returns one if |
1757 | /// overflow occurred, otherwise zero. DST must be disjoint from both |
1758 | /// operands. |
1759 | static int tcMultiply(WordType *, const WordType *, const WordType *, |
1760 | unsigned); |
1761 | |
1762 | /// DST = LHS * RHS, where DST has width the sum of the widths of the |
1763 | /// operands. No overflow occurs. DST must be disjoint from both operands. |
1764 | static void tcFullMultiply(WordType *, const WordType *, const WordType *, |
1765 | unsigned, unsigned); |
1766 | |
1767 | /// If RHS is zero LHS and REMAINDER are left unchanged, return one. |
1768 | /// Otherwise set LHS to LHS / RHS with the fractional part discarded, set |
1769 | /// REMAINDER to the remainder, return zero. i.e. |
1770 | /// |
1771 | /// OLD_LHS = RHS * LHS + REMAINDER |
1772 | /// |
1773 | /// SCRATCH is a bignum of the same size as the operands and result for use by |
1774 | /// the routine; its contents need not be initialized and are destroyed. LHS, |
1775 | /// REMAINDER and SCRATCH must be distinct. |
1776 | static int tcDivide(WordType *lhs, const WordType *rhs, WordType *remainder, |
1777 | WordType *scratch, unsigned parts); |
1778 | |
1779 | /// Shift a bignum left Count bits. Shifted in bits are zero. There are no |
1780 | /// restrictions on Count. |
1781 | static void tcShiftLeft(WordType *, unsigned Words, unsigned Count); |
1782 | |
1783 | /// Shift a bignum right Count bits. Shifted in bits are zero. There are no |
1784 | /// restrictions on Count. |
1785 | static void tcShiftRight(WordType *, unsigned Words, unsigned Count); |
1786 | |
1787 | /// Comparison (unsigned) of two bignums. |
1788 | static int tcCompare(const WordType *, const WordType *, unsigned); |
1789 | |
1790 | /// Increment a bignum in-place. Return the carry flag. |
1791 | static WordType tcIncrement(WordType *dst, unsigned parts) { |
1792 | return tcAddPart(dst, 1, parts); |
1793 | } |
1794 | |
1795 | /// Decrement a bignum in-place. Return the borrow flag. |
1796 | static WordType tcDecrement(WordType *dst, unsigned parts) { |
1797 | return tcSubtractPart(dst, 1, parts); |
1798 | } |
1799 | |
1800 | /// Used to insert APInt objects, or objects that contain APInt objects, into |
1801 | /// FoldingSets. |
1802 | void Profile(FoldingSetNodeID &id) const; |
1803 | |
1804 | /// debug method |
1805 | void dump() const; |
1806 | |
1807 | /// Returns whether this instance allocated memory. |
1808 | bool needsCleanup() const { return !isSingleWord(); } |
1809 | |
1810 | private: |
1811 | /// This union is used to store the integer value. When the |
1812 | /// integer bit-width <= 64, it uses VAL, otherwise it uses pVal. |
1813 | union { |
1814 | uint64_t VAL; ///< Used to store the <= 64 bits integer value. |
1815 | uint64_t *pVal; ///< Used to store the >64 bits integer value. |
1816 | } U; |
1817 | |
1818 | unsigned BitWidth; ///< The number of bits in this APInt. |
1819 | |
1820 | friend struct DenseMapInfo<APInt>; |
1821 | friend class APSInt; |
1822 | |
1823 | /// This constructor is used only internally for speed of construction of |
1824 | /// temporaries. It is unsafe since it takes ownership of the pointer, so it |
1825 | /// is not public. |
1826 | APInt(uint64_t *val, unsigned bits) : BitWidth(bits) { U.pVal = val; } |
1827 | |
1828 | /// Determine which word a bit is in. |
1829 | /// |
1830 | /// \returns the word position for the specified bit position. |
1831 | static unsigned whichWord(unsigned bitPosition) { |
1832 | return bitPosition / APINT_BITS_PER_WORD; |
1833 | } |
1834 | |
1835 | /// Determine which bit in a word the specified bit position is in. |
1836 | static unsigned whichBit(unsigned bitPosition) { |
1837 | return bitPosition % APINT_BITS_PER_WORD; |
1838 | } |
1839 | |
1840 | /// Get a single bit mask. |
1841 | /// |
1842 | /// \returns a uint64_t with only bit at "whichBit(bitPosition)" set |
1843 | /// This method generates and returns a uint64_t (word) mask for a single |
1844 | /// bit at a specific bit position. This is used to mask the bit in the |
1845 | /// corresponding word. |
1846 | static uint64_t maskBit(unsigned bitPosition) { |
1847 | return 1ULL << whichBit(bitPosition); |
1848 | } |
1849 | |
1850 | /// Clear unused high order bits |
1851 | /// |
1852 | /// This method is used internally to clear the top "N" bits in the high order |
1853 | /// word that are not used by the APInt. This is needed after the most |
1854 | /// significant word is assigned a value to ensure that those bits are |
1855 | /// zero'd out. |
1856 | APInt &clearUnusedBits() { |
1857 | // Compute how many bits are used in the final word. |
1858 | unsigned WordBits = ((BitWidth - 1) % APINT_BITS_PER_WORD) + 1; |
1859 | |
1860 | // Mask out the high bits. |
1861 | uint64_t mask = WORDTYPE_MAX >> (APINT_BITS_PER_WORD - WordBits); |
1862 | if (LLVM_UNLIKELY(BitWidth == 0)__builtin_expect((bool)(BitWidth == 0), false)) |
1863 | mask = 0; |
1864 | |
1865 | if (isSingleWord()) |
1866 | U.VAL &= mask; |
1867 | else |
1868 | U.pVal[getNumWords() - 1] &= mask; |
1869 | return *this; |
1870 | } |
1871 | |
1872 | /// Get the word corresponding to a bit position |
1873 | /// \returns the corresponding word for the specified bit position. |
1874 | uint64_t getWord(unsigned bitPosition) const { |
1875 | return isSingleWord() ? U.VAL : U.pVal[whichWord(bitPosition)]; |
1876 | } |
1877 | |
1878 | /// Utility method to change the bit width of this APInt to new bit width, |
1879 | /// allocating and/or deallocating as necessary. There is no guarantee on the |
1880 | /// value of any bits upon return. Caller should populate the bits after. |
1881 | void reallocate(unsigned NewBitWidth); |
1882 | |
1883 | /// Convert a char array into an APInt |
1884 | /// |
1885 | /// \param radix 2, 8, 10, 16, or 36 |
1886 | /// Converts a string into a number. The string must be non-empty |
1887 | /// and well-formed as a number of the given base. The bit-width |
1888 | /// must be sufficient to hold the result. |
1889 | /// |
1890 | /// This is used by the constructors that take string arguments. |
1891 | /// |
1892 | /// StringRef::getAsInteger is superficially similar but (1) does |
1893 | /// not assume that the string is well-formed and (2) grows the |
1894 | /// result to hold the input. |
1895 | void fromString(unsigned numBits, StringRef str, uint8_t radix); |
1896 | |
1897 | /// An internal division function for dividing APInts. |
1898 | /// |
1899 | /// This is used by the toString method to divide by the radix. It simply |
1900 | /// provides a more convenient form of divide for internal use since KnuthDiv |
1901 | /// has specific constraints on its inputs. If those constraints are not met |
1902 | /// then it provides a simpler form of divide. |
1903 | static void divide(const WordType *LHS, unsigned lhsWords, |
1904 | const WordType *RHS, unsigned rhsWords, WordType *Quotient, |
1905 | WordType *Remainder); |
1906 | |
1907 | /// out-of-line slow case for inline constructor |
1908 | void initSlowCase(uint64_t val, bool isSigned); |
1909 | |
1910 | /// shared code between two array constructors |
1911 | void initFromArray(ArrayRef<uint64_t> array); |
1912 | |
1913 | /// out-of-line slow case for inline copy constructor |
1914 | void initSlowCase(const APInt &that); |
1915 | |
1916 | /// out-of-line slow case for shl |
1917 | void shlSlowCase(unsigned ShiftAmt); |
1918 | |
1919 | /// out-of-line slow case for lshr. |
1920 | void lshrSlowCase(unsigned ShiftAmt); |
1921 | |
1922 | /// out-of-line slow case for ashr. |
1923 | void ashrSlowCase(unsigned ShiftAmt); |
1924 | |
1925 | /// out-of-line slow case for operator= |
1926 | void assignSlowCase(const APInt &RHS); |
1927 | |
1928 | /// out-of-line slow case for operator== |
1929 | bool equalSlowCase(const APInt &RHS) const LLVM_READONLY__attribute__((__pure__)); |
1930 | |
1931 | /// out-of-line slow case for countLeadingZeros |
1932 | unsigned countLeadingZerosSlowCase() const LLVM_READONLY__attribute__((__pure__)); |
1933 | |
1934 | /// out-of-line slow case for countLeadingOnes. |
1935 | unsigned countLeadingOnesSlowCase() const LLVM_READONLY__attribute__((__pure__)); |
1936 | |
1937 | /// out-of-line slow case for countTrailingZeros. |
1938 | unsigned countTrailingZerosSlowCase() const LLVM_READONLY__attribute__((__pure__)); |
1939 | |
1940 | /// out-of-line slow case for countTrailingOnes |
1941 | unsigned countTrailingOnesSlowCase() const LLVM_READONLY__attribute__((__pure__)); |
1942 | |
1943 | /// out-of-line slow case for countPopulation |
1944 | unsigned countPopulationSlowCase() const LLVM_READONLY__attribute__((__pure__)); |
1945 | |
1946 | /// out-of-line slow case for intersects. |
1947 | bool intersectsSlowCase(const APInt &RHS) const LLVM_READONLY__attribute__((__pure__)); |
1948 | |
1949 | /// out-of-line slow case for isSubsetOf. |
1950 | bool isSubsetOfSlowCase(const APInt &RHS) const LLVM_READONLY__attribute__((__pure__)); |
1951 | |
1952 | /// out-of-line slow case for setBits. |
1953 | void setBitsSlowCase(unsigned loBit, unsigned hiBit); |
1954 | |
1955 | /// out-of-line slow case for flipAllBits. |
1956 | void flipAllBitsSlowCase(); |
1957 | |
1958 | /// out-of-line slow case for concat. |
1959 | APInt concatSlowCase(const APInt &NewLSB) const; |
1960 | |
1961 | /// out-of-line slow case for operator&=. |
1962 | void andAssignSlowCase(const APInt &RHS); |
1963 | |
1964 | /// out-of-line slow case for operator|=. |
1965 | void orAssignSlowCase(const APInt &RHS); |
1966 | |
1967 | /// out-of-line slow case for operator^=. |
1968 | void xorAssignSlowCase(const APInt &RHS); |
1969 | |
1970 | /// Unsigned comparison. Returns -1, 0, or 1 if this APInt is less than, equal |
1971 | /// to, or greater than RHS. |
1972 | int compare(const APInt &RHS) const LLVM_READONLY__attribute__((__pure__)); |
1973 | |
1974 | /// Signed comparison. Returns -1, 0, or 1 if this APInt is less than, equal |
1975 | /// to, or greater than RHS. |
1976 | int compareSigned(const APInt &RHS) const LLVM_READONLY__attribute__((__pure__)); |
1977 | |
1978 | /// @} |
1979 | }; |
1980 | |
1981 | inline bool operator==(uint64_t V1, const APInt &V2) { return V2 == V1; } |
1982 | |
1983 | inline bool operator!=(uint64_t V1, const APInt &V2) { return V2 != V1; } |
1984 | |
1985 | /// Unary bitwise complement operator. |
1986 | /// |
1987 | /// \returns an APInt that is the bitwise complement of \p v. |
1988 | inline APInt operator~(APInt v) { |
1989 | v.flipAllBits(); |
1990 | return v; |
1991 | } |
1992 | |
1993 | inline APInt operator&(APInt a, const APInt &b) { |
1994 | a &= b; |
1995 | return a; |
1996 | } |
1997 | |
1998 | inline APInt operator&(const APInt &a, APInt &&b) { |
1999 | b &= a; |
2000 | return std::move(b); |
2001 | } |
2002 | |
2003 | inline APInt operator&(APInt a, uint64_t RHS) { |
2004 | a &= RHS; |
2005 | return a; |
2006 | } |
2007 | |
2008 | inline APInt operator&(uint64_t LHS, APInt b) { |
2009 | b &= LHS; |
2010 | return b; |
2011 | } |
2012 | |
2013 | inline APInt operator|(APInt a, const APInt &b) { |
2014 | a |= b; |
2015 | return a; |
2016 | } |
2017 | |
2018 | inline APInt operator|(const APInt &a, APInt &&b) { |
2019 | b |= a; |
2020 | return std::move(b); |
2021 | } |
2022 | |
2023 | inline APInt operator|(APInt a, uint64_t RHS) { |
2024 | a |= RHS; |
2025 | return a; |
2026 | } |
2027 | |
2028 | inline APInt operator|(uint64_t LHS, APInt b) { |
2029 | b |= LHS; |
2030 | return b; |
2031 | } |
2032 | |
2033 | inline APInt operator^(APInt a, const APInt &b) { |
2034 | a ^= b; |
2035 | return a; |
2036 | } |
2037 | |
2038 | inline APInt operator^(const APInt &a, APInt &&b) { |
2039 | b ^= a; |
2040 | return std::move(b); |
2041 | } |
2042 | |
2043 | inline APInt operator^(APInt a, uint64_t RHS) { |
2044 | a ^= RHS; |
2045 | return a; |
2046 | } |
2047 | |
2048 | inline APInt operator^(uint64_t LHS, APInt b) { |
2049 | b ^= LHS; |
2050 | return b; |
2051 | } |
2052 | |
2053 | inline raw_ostream &operator<<(raw_ostream &OS, const APInt &I) { |
2054 | I.print(OS, true); |
2055 | return OS; |
2056 | } |
2057 | |
2058 | inline APInt operator-(APInt v) { |
2059 | v.negate(); |
2060 | return v; |
2061 | } |
2062 | |
2063 | inline APInt operator+(APInt a, const APInt &b) { |
2064 | a += b; |
2065 | return a; |
2066 | } |
2067 | |
2068 | inline APInt operator+(const APInt &a, APInt &&b) { |
2069 | b += a; |
2070 | return std::move(b); |
2071 | } |
2072 | |
2073 | inline APInt operator+(APInt a, uint64_t RHS) { |
2074 | a += RHS; |
2075 | return a; |
2076 | } |
2077 | |
2078 | inline APInt operator+(uint64_t LHS, APInt b) { |
2079 | b += LHS; |
2080 | return b; |
2081 | } |
2082 | |
2083 | inline APInt operator-(APInt a, const APInt &b) { |
2084 | a -= b; |
2085 | return a; |
2086 | } |
2087 | |
2088 | inline APInt operator-(const APInt &a, APInt &&b) { |
2089 | b.negate(); |
2090 | b += a; |
2091 | return std::move(b); |
2092 | } |
2093 | |
2094 | inline APInt operator-(APInt a, uint64_t RHS) { |
2095 | a -= RHS; |
2096 | return a; |
2097 | } |
2098 | |
2099 | inline APInt operator-(uint64_t LHS, APInt b) { |
2100 | b.negate(); |
2101 | b += LHS; |
2102 | return b; |
2103 | } |
2104 | |
2105 | inline APInt operator*(APInt a, uint64_t RHS) { |
2106 | a *= RHS; |
2107 | return a; |
2108 | } |
2109 | |
2110 | inline APInt operator*(uint64_t LHS, APInt b) { |
2111 | b *= LHS; |
2112 | return b; |
2113 | } |
2114 | |
2115 | namespace APIntOps { |
2116 | |
2117 | /// Determine the smaller of two APInts considered to be signed. |
2118 | inline const APInt &smin(const APInt &A, const APInt &B) { |
2119 | return A.slt(B) ? A : B; |
2120 | } |
2121 | |
2122 | /// Determine the larger of two APInts considered to be signed. |
2123 | inline const APInt &smax(const APInt &A, const APInt &B) { |
2124 | return A.sgt(B) ? A : B; |
2125 | } |
2126 | |
2127 | /// Determine the smaller of two APInts considered to be unsigned. |
2128 | inline const APInt &umin(const APInt &A, const APInt &B) { |
2129 | return A.ult(B) ? A : B; |
2130 | } |
2131 | |
2132 | /// Determine the larger of two APInts considered to be unsigned. |
2133 | inline const APInt &umax(const APInt &A, const APInt &B) { |
2134 | return A.ugt(B) ? A : B; |
2135 | } |
2136 | |
2137 | /// Compute GCD of two unsigned APInt values. |
2138 | /// |
2139 | /// This function returns the greatest common divisor of the two APInt values |
2140 | /// using Stein's algorithm. |
2141 | /// |
2142 | /// \returns the greatest common divisor of A and B. |
2143 | APInt GreatestCommonDivisor(APInt A, APInt B); |
2144 | |
2145 | /// Converts the given APInt to a double value. |
2146 | /// |
2147 | /// Treats the APInt as an unsigned value for conversion purposes. |
2148 | inline double RoundAPIntToDouble(const APInt &APIVal) { |
2149 | return APIVal.roundToDouble(); |
2150 | } |
2151 | |
2152 | /// Converts the given APInt to a double value. |
2153 | /// |
2154 | /// Treats the APInt as a signed value for conversion purposes. |
2155 | inline double RoundSignedAPIntToDouble(const APInt &APIVal) { |
2156 | return APIVal.signedRoundToDouble(); |
2157 | } |
2158 | |
2159 | /// Converts the given APInt to a float value. |
2160 | inline float RoundAPIntToFloat(const APInt &APIVal) { |
2161 | return float(RoundAPIntToDouble(APIVal)); |
2162 | } |
2163 | |
2164 | /// Converts the given APInt to a float value. |
2165 | /// |
2166 | /// Treats the APInt as a signed value for conversion purposes. |
2167 | inline float RoundSignedAPIntToFloat(const APInt &APIVal) { |
2168 | return float(APIVal.signedRoundToDouble()); |
2169 | } |
2170 | |
2171 | /// Converts the given double value into a APInt. |
2172 | /// |
2173 | /// This function convert a double value to an APInt value. |
2174 | APInt RoundDoubleToAPInt(double Double, unsigned width); |
2175 | |
2176 | /// Converts a float value into a APInt. |
2177 | /// |
2178 | /// Converts a float value into an APInt value. |
2179 | inline APInt RoundFloatToAPInt(float Float, unsigned width) { |
2180 | return RoundDoubleToAPInt(double(Float), width); |
2181 | } |
2182 | |
2183 | /// Return A unsign-divided by B, rounded by the given rounding mode. |
2184 | APInt RoundingUDiv(const APInt &A, const APInt &B, APInt::Rounding RM); |
2185 | |
2186 | /// Return A sign-divided by B, rounded by the given rounding mode. |
2187 | APInt RoundingSDiv(const APInt &A, const APInt &B, APInt::Rounding RM); |
2188 | |
2189 | /// Let q(n) = An^2 + Bn + C, and BW = bit width of the value range |
2190 | /// (e.g. 32 for i32). |
2191 | /// This function finds the smallest number n, such that |
2192 | /// (a) n >= 0 and q(n) = 0, or |
2193 | /// (b) n >= 1 and q(n-1) and q(n), when evaluated in the set of all |
2194 | /// integers, belong to two different intervals [Rk, Rk+R), |
2195 | /// where R = 2^BW, and k is an integer. |
2196 | /// The idea here is to find when q(n) "overflows" 2^BW, while at the |
2197 | /// same time "allowing" subtraction. In unsigned modulo arithmetic a |
2198 | /// subtraction (treated as addition of negated numbers) would always |
2199 | /// count as an overflow, but here we want to allow values to decrease |
2200 | /// and increase as long as they are within the same interval. |
2201 | /// Specifically, adding of two negative numbers should not cause an |
2202 | /// overflow (as long as the magnitude does not exceed the bit width). |
2203 | /// On the other hand, given a positive number, adding a negative |
2204 | /// number to it can give a negative result, which would cause the |
2205 | /// value to go from [-2^BW, 0) to [0, 2^BW). In that sense, zero is |
2206 | /// treated as a special case of an overflow. |
2207 | /// |
2208 | /// This function returns None if after finding k that minimizes the |
2209 | /// positive solution to q(n) = kR, both solutions are contained between |
2210 | /// two consecutive integers. |
2211 | /// |
2212 | /// There are cases where q(n) > T, and q(n+1) < T (assuming evaluation |
2213 | /// in arithmetic modulo 2^BW, and treating the values as signed) by the |
2214 | /// virtue of *signed* overflow. This function will *not* find such an n, |
2215 | /// however it may find a value of n satisfying the inequalities due to |
2216 | /// an *unsigned* overflow (if the values are treated as unsigned). |
2217 | /// To find a solution for a signed overflow, treat it as a problem of |
2218 | /// finding an unsigned overflow with a range with of BW-1. |
2219 | /// |
2220 | /// The returned value may have a different bit width from the input |
2221 | /// coefficients. |
2222 | Optional<APInt> SolveQuadraticEquationWrap(APInt A, APInt B, APInt C, |
2223 | unsigned RangeWidth); |
2224 | |
2225 | /// Compare two values, and if they are different, return the position of the |
2226 | /// most significant bit that is different in the values. |
2227 | Optional<unsigned> GetMostSignificantDifferentBit(const APInt &A, |
2228 | const APInt &B); |
2229 | |
2230 | /// Splat/Merge neighboring bits to widen/narrow the bitmask represented |
2231 | /// by \param A to \param NewBitWidth bits. |
2232 | /// |
2233 | /// e.g. ScaleBitMask(0b0101, 8) -> 0b00110011 |
2234 | /// e.g. ScaleBitMask(0b00011011, 4) -> 0b0111 |
2235 | /// A.getBitwidth() or NewBitWidth must be a whole multiples of the other. |
2236 | /// |
2237 | /// TODO: Do we need a mode where all bits must be set when merging down? |
2238 | APInt ScaleBitMask(const APInt &A, unsigned NewBitWidth); |
2239 | } // namespace APIntOps |
2240 | |
2241 | // See friend declaration above. This additional declaration is required in |
2242 | // order to compile LLVM with IBM xlC compiler. |
2243 | hash_code hash_value(const APInt &Arg); |
2244 | |
2245 | /// StoreIntToMemory - Fills the StoreBytes bytes of memory starting from Dst |
2246 | /// with the integer held in IntVal. |
2247 | void StoreIntToMemory(const APInt &IntVal, uint8_t *Dst, unsigned StoreBytes); |
2248 | |
2249 | /// LoadIntFromMemory - Loads the integer stored in the LoadBytes bytes starting |
2250 | /// from Src into IntVal, which is assumed to be wide enough and to hold zero. |
2251 | void LoadIntFromMemory(APInt &IntVal, const uint8_t *Src, unsigned LoadBytes); |
2252 | |
2253 | /// Provide DenseMapInfo for APInt. |
2254 | template <> struct DenseMapInfo<APInt> { |
2255 | static inline APInt getEmptyKey() { |
2256 | APInt V(nullptr, 0); |
2257 | V.U.VAL = 0; |
2258 | return V; |
2259 | } |
2260 | |
2261 | static inline APInt getTombstoneKey() { |
2262 | APInt V(nullptr, 0); |
2263 | V.U.VAL = 1; |
2264 | return V; |
2265 | } |
2266 | |
2267 | static unsigned getHashValue(const APInt &Key); |
2268 | |
2269 | static bool isEqual(const APInt &LHS, const APInt &RHS) { |
2270 | return LHS.getBitWidth() == RHS.getBitWidth() && LHS == RHS; |
2271 | } |
2272 | }; |
2273 | |
2274 | } // namespace llvm |
2275 | |
2276 | #endif |
1 | //===- CodeGen/ValueTypes.h - Low-Level Target independ. types --*- C++ -*-===// |
2 | // |
3 | // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. |
4 | // See https://llvm.org/LICENSE.txt for license information. |
5 | // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception |
6 | // |
7 | //===----------------------------------------------------------------------===// |
8 | // |
9 | // This file defines the set of low-level target independent types which various |
10 | // values in the code generator are. This allows the target specific behavior |
11 | // of instructions to be described to target independent passes. |
12 | // |
13 | //===----------------------------------------------------------------------===// |
14 | |
15 | #ifndef LLVM_CODEGEN_VALUETYPES_H |
16 | #define LLVM_CODEGEN_VALUETYPES_H |
17 | |
18 | #include "llvm/Support/Compiler.h" |
19 | #include "llvm/Support/MachineValueType.h" |
20 | #include "llvm/Support/MathExtras.h" |
21 | #include "llvm/Support/TypeSize.h" |
22 | #include "llvm/Support/WithColor.h" |
23 | #include <cassert> |
24 | #include <cstdint> |
25 | #include <string> |
26 | |
27 | namespace llvm { |
28 | |
29 | class LLVMContext; |
30 | class Type; |
31 | |
32 | /// Extended Value Type. Capable of holding value types which are not native |
33 | /// for any processor (such as the i12345 type), as well as the types an MVT |
34 | /// can represent. |
35 | struct EVT { |
36 | private: |
37 | MVT V = MVT::INVALID_SIMPLE_VALUE_TYPE; |
38 | Type *LLVMTy = nullptr; |
39 | |
40 | public: |
41 | constexpr EVT() = default; |
42 | constexpr EVT(MVT::SimpleValueType SVT) : V(SVT) {} |
43 | constexpr EVT(MVT S) : V(S) {} |
44 | |
45 | bool operator==(EVT VT) const { |
46 | return !(*this != VT); |
47 | } |
48 | bool operator!=(EVT VT) const { |
49 | if (V.SimpleTy != VT.V.SimpleTy) |
50 | return true; |
51 | if (V.SimpleTy == MVT::INVALID_SIMPLE_VALUE_TYPE) |
52 | return LLVMTy != VT.LLVMTy; |
53 | return false; |
54 | } |
55 | |
56 | /// Returns the EVT that represents a floating-point type with the given |
57 | /// number of bits. There are two floating-point types with 128 bits - this |
58 | /// returns f128 rather than ppcf128. |
59 | static EVT getFloatingPointVT(unsigned BitWidth) { |
60 | return MVT::getFloatingPointVT(BitWidth); |
61 | } |
62 | |
63 | /// Returns the EVT that represents an integer with the given number of |
64 | /// bits. |
65 | static EVT getIntegerVT(LLVMContext &Context, unsigned BitWidth) { |
66 | MVT M = MVT::getIntegerVT(BitWidth); |
67 | if (M.SimpleTy != MVT::INVALID_SIMPLE_VALUE_TYPE) |
68 | return M; |
69 | return getExtendedIntegerVT(Context, BitWidth); |
70 | } |
71 | |
72 | /// Returns the EVT that represents a vector NumElements in length, where |
73 | /// each element is of type VT. |
74 | static EVT getVectorVT(LLVMContext &Context, EVT VT, unsigned NumElements, |
75 | bool IsScalable = false) { |
76 | MVT M = MVT::getVectorVT(VT.V, NumElements, IsScalable); |
77 | if (M.SimpleTy != MVT::INVALID_SIMPLE_VALUE_TYPE) |
78 | return M; |
79 | return getExtendedVectorVT(Context, VT, NumElements, IsScalable); |
80 | } |
81 | |
82 | /// Returns the EVT that represents a vector EC.Min elements in length, |
83 | /// where each element is of type VT. |
84 | static EVT getVectorVT(LLVMContext &Context, EVT VT, ElementCount EC) { |
85 | MVT M = MVT::getVectorVT(VT.V, EC); |
86 | if (M.SimpleTy != MVT::INVALID_SIMPLE_VALUE_TYPE) |
87 | return M; |
88 | return getExtendedVectorVT(Context, VT, EC); |
89 | } |
90 | |
91 | /// Return a vector with the same number of elements as this vector, but |
92 | /// with the element type converted to an integer type with the same |
93 | /// bitwidth. |
94 | EVT changeVectorElementTypeToInteger() const { |
95 | if (isSimple()) |
96 | return getSimpleVT().changeVectorElementTypeToInteger(); |
97 | return changeExtendedVectorElementTypeToInteger(); |
98 | } |
99 | |
100 | /// Return a VT for a vector type whose attributes match ourselves |
101 | /// with the exception of the element type that is chosen by the caller. |
102 | EVT changeVectorElementType(EVT EltVT) const { |
103 | if (isSimple()) { |
104 | assert(EltVT.isSimple() &&(static_cast <bool> (EltVT.isSimple() && "Can't change simple vector VT to have extended element VT" ) ? void (0) : __assert_fail ("EltVT.isSimple() && \"Can't change simple vector VT to have extended element VT\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/include/llvm/CodeGen/ValueTypes.h" , 105, __extension__ __PRETTY_FUNCTION__)) |
105 | "Can't change simple vector VT to have extended element VT")(static_cast <bool> (EltVT.isSimple() && "Can't change simple vector VT to have extended element VT" ) ? void (0) : __assert_fail ("EltVT.isSimple() && \"Can't change simple vector VT to have extended element VT\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/include/llvm/CodeGen/ValueTypes.h" , 105, __extension__ __PRETTY_FUNCTION__)); |
106 | return getSimpleVT().changeVectorElementType(EltVT.getSimpleVT()); |
107 | } |
108 | return changeExtendedVectorElementType(EltVT); |
109 | } |
110 | |
111 | /// Return the type converted to an equivalently sized integer or vector |
112 | /// with integer element type. Similar to changeVectorElementTypeToInteger, |
113 | /// but also handles scalars. |
114 | EVT changeTypeToInteger() { |
115 | if (isVector()) |
116 | return changeVectorElementTypeToInteger(); |
117 | |
118 | if (isSimple()) |
119 | return getSimpleVT().changeTypeToInteger(); |
120 | return changeExtendedTypeToInteger(); |
121 | } |
122 | |
123 | /// Test if the given EVT has zero size, this will fail if called on a |
124 | /// scalable type |
125 | bool isZeroSized() const { |
126 | return !isScalableVector() && getSizeInBits() == 0; |
127 | } |
128 | |
129 | /// Test if the given EVT is simple (as opposed to being extended). |
130 | bool isSimple() const { |
131 | return V.SimpleTy != MVT::INVALID_SIMPLE_VALUE_TYPE; |
132 | } |
133 | |
134 | /// Test if the given EVT is extended (as opposed to being simple). |
135 | bool isExtended() const { |
136 | return !isSimple(); |
137 | } |
138 | |
139 | /// Return true if this is a FP or a vector FP type. |
140 | bool isFloatingPoint() const { |
141 | return isSimple() ? V.isFloatingPoint() : isExtendedFloatingPoint(); |
142 | } |
143 | |
144 | /// Return true if this is an integer or a vector integer type. |
145 | bool isInteger() const { |
146 | return isSimple() ? V.isInteger() : isExtendedInteger(); |
147 | } |
148 | |
149 | /// Return true if this is an integer, but not a vector. |
150 | bool isScalarInteger() const { |
151 | return isSimple() ? V.isScalarInteger() : isExtendedScalarInteger(); |
152 | } |
153 | |
154 | /// Return true if this is a vector value type. |
155 | bool isVector() const { |
156 | return isSimple() ? V.isVector() : isExtendedVector(); |
157 | } |
158 | |
159 | /// Return true if this is a vector type where the runtime |
160 | /// length is machine dependent |
161 | bool isScalableVector() const { |
162 | return isSimple() ? V.isScalableVector() : isExtendedScalableVector(); |
163 | } |
164 | |
165 | bool isFixedLengthVector() const { |
166 | return isSimple() ? V.isFixedLengthVector() |
167 | : isExtendedFixedLengthVector(); |
168 | } |
169 | |
170 | /// Return true if this is a 16-bit vector type. |
171 | bool is16BitVector() const { |
172 | return isSimple() ? V.is16BitVector() : isExtended16BitVector(); |
173 | } |
174 | |
175 | /// Return true if this is a 32-bit vector type. |
176 | bool is32BitVector() const { |
177 | return isSimple() ? V.is32BitVector() : isExtended32BitVector(); |
178 | } |
179 | |
180 | /// Return true if this is a 64-bit vector type. |
181 | bool is64BitVector() const { |
182 | return isSimple() ? V.is64BitVector() : isExtended64BitVector(); |
183 | } |
184 | |
185 | /// Return true if this is a 128-bit vector type. |
186 | bool is128BitVector() const { |
187 | return isSimple() ? V.is128BitVector() : isExtended128BitVector(); |
188 | } |
189 | |
190 | /// Return true if this is a 256-bit vector type. |
191 | bool is256BitVector() const { |
192 | return isSimple() ? V.is256BitVector() : isExtended256BitVector(); |
193 | } |
194 | |
195 | /// Return true if this is a 512-bit vector type. |
196 | bool is512BitVector() const { |
197 | return isSimple() ? V.is512BitVector() : isExtended512BitVector(); |
198 | } |
199 | |
200 | /// Return true if this is a 1024-bit vector type. |
201 | bool is1024BitVector() const { |
202 | return isSimple() ? V.is1024BitVector() : isExtended1024BitVector(); |
203 | } |
204 | |
205 | /// Return true if this is a 2048-bit vector type. |
206 | bool is2048BitVector() const { |
207 | return isSimple() ? V.is2048BitVector() : isExtended2048BitVector(); |
208 | } |
209 | |
210 | /// Return true if this is an overloaded type for TableGen. |
211 | bool isOverloaded() const { |
212 | return (V==MVT::iAny || V==MVT::fAny || V==MVT::vAny || V==MVT::iPTRAny); |
213 | } |
214 | |
215 | /// Return true if the bit size is a multiple of 8. |
216 | bool isByteSized() const { |
217 | return !isZeroSized() && getSizeInBits().isKnownMultipleOf(8); |
218 | } |
219 | |
220 | /// Return true if the size is a power-of-two number of bytes. |
221 | bool isRound() const { |
222 | if (isScalableVector()) |
223 | return false; |
224 | unsigned BitSize = getSizeInBits(); |
225 | return BitSize >= 8 && !(BitSize & (BitSize - 1)); |
226 | } |
227 | |
228 | /// Return true if this has the same number of bits as VT. |
229 | bool bitsEq(EVT VT) const { |
230 | if (EVT::operator==(VT)) return true; |
231 | return getSizeInBits() == VT.getSizeInBits(); |
232 | } |
233 | |
234 | /// Return true if we know at compile time this has more bits than VT. |
235 | bool knownBitsGT(EVT VT) const { |
236 | return TypeSize::isKnownGT(getSizeInBits(), VT.getSizeInBits()); |
237 | } |
238 | |
239 | /// Return true if we know at compile time this has more than or the same |
240 | /// bits as VT. |
241 | bool knownBitsGE(EVT VT) const { |
242 | return TypeSize::isKnownGE(getSizeInBits(), VT.getSizeInBits()); |
243 | } |
244 | |
245 | /// Return true if we know at compile time this has fewer bits than VT. |
246 | bool knownBitsLT(EVT VT) const { |
247 | return TypeSize::isKnownLT(getSizeInBits(), VT.getSizeInBits()); |
248 | } |
249 | |
250 | /// Return true if we know at compile time this has fewer than or the same |
251 | /// bits as VT. |
252 | bool knownBitsLE(EVT VT) const { |
253 | return TypeSize::isKnownLE(getSizeInBits(), VT.getSizeInBits()); |
254 | } |
255 | |
256 | /// Return true if this has more bits than VT. |
257 | bool bitsGT(EVT VT) const { |
258 | if (EVT::operator==(VT)) return false; |
259 | assert(isScalableVector() == VT.isScalableVector() &&(static_cast <bool> (isScalableVector() == VT.isScalableVector () && "Comparison between scalable and fixed types") ? void (0) : __assert_fail ("isScalableVector() == VT.isScalableVector() && \"Comparison between scalable and fixed types\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/include/llvm/CodeGen/ValueTypes.h" , 260, __extension__ __PRETTY_FUNCTION__)) |
260 | "Comparison between scalable and fixed types")(static_cast <bool> (isScalableVector() == VT.isScalableVector () && "Comparison between scalable and fixed types") ? void (0) : __assert_fail ("isScalableVector() == VT.isScalableVector() && \"Comparison between scalable and fixed types\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/include/llvm/CodeGen/ValueTypes.h" , 260, __extension__ __PRETTY_FUNCTION__)); |
261 | return knownBitsGT(VT); |
262 | } |
263 | |
264 | /// Return true if this has no less bits than VT. |
265 | bool bitsGE(EVT VT) const { |
266 | if (EVT::operator==(VT)) return true; |
267 | assert(isScalableVector() == VT.isScalableVector() &&(static_cast <bool> (isScalableVector() == VT.isScalableVector () && "Comparison between scalable and fixed types") ? void (0) : __assert_fail ("isScalableVector() == VT.isScalableVector() && \"Comparison between scalable and fixed types\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/include/llvm/CodeGen/ValueTypes.h" , 268, __extension__ __PRETTY_FUNCTION__)) |
268 | "Comparison between scalable and fixed types")(static_cast <bool> (isScalableVector() == VT.isScalableVector () && "Comparison between scalable and fixed types") ? void (0) : __assert_fail ("isScalableVector() == VT.isScalableVector() && \"Comparison between scalable and fixed types\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/include/llvm/CodeGen/ValueTypes.h" , 268, __extension__ __PRETTY_FUNCTION__)); |
269 | return knownBitsGE(VT); |
270 | } |
271 | |
272 | /// Return true if this has less bits than VT. |
273 | bool bitsLT(EVT VT) const { |
274 | if (EVT::operator==(VT)) return false; |
275 | assert(isScalableVector() == VT.isScalableVector() &&(static_cast <bool> (isScalableVector() == VT.isScalableVector () && "Comparison between scalable and fixed types") ? void (0) : __assert_fail ("isScalableVector() == VT.isScalableVector() && \"Comparison between scalable and fixed types\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/include/llvm/CodeGen/ValueTypes.h" , 276, __extension__ __PRETTY_FUNCTION__)) |
276 | "Comparison between scalable and fixed types")(static_cast <bool> (isScalableVector() == VT.isScalableVector () && "Comparison between scalable and fixed types") ? void (0) : __assert_fail ("isScalableVector() == VT.isScalableVector() && \"Comparison between scalable and fixed types\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/include/llvm/CodeGen/ValueTypes.h" , 276, __extension__ __PRETTY_FUNCTION__)); |
277 | return knownBitsLT(VT); |
278 | } |
279 | |
280 | /// Return true if this has no more bits than VT. |
281 | bool bitsLE(EVT VT) const { |
282 | if (EVT::operator==(VT)) return true; |
283 | assert(isScalableVector() == VT.isScalableVector() &&(static_cast <bool> (isScalableVector() == VT.isScalableVector () && "Comparison between scalable and fixed types") ? void (0) : __assert_fail ("isScalableVector() == VT.isScalableVector() && \"Comparison between scalable and fixed types\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/include/llvm/CodeGen/ValueTypes.h" , 284, __extension__ __PRETTY_FUNCTION__)) |
284 | "Comparison between scalable and fixed types")(static_cast <bool> (isScalableVector() == VT.isScalableVector () && "Comparison between scalable and fixed types") ? void (0) : __assert_fail ("isScalableVector() == VT.isScalableVector() && \"Comparison between scalable and fixed types\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/include/llvm/CodeGen/ValueTypes.h" , 284, __extension__ __PRETTY_FUNCTION__)); |
285 | return knownBitsLE(VT); |
286 | } |
287 | |
288 | /// Return the SimpleValueType held in the specified simple EVT. |
289 | MVT getSimpleVT() const { |
290 | assert(isSimple() && "Expected a SimpleValueType!")(static_cast <bool> (isSimple() && "Expected a SimpleValueType!" ) ? void (0) : __assert_fail ("isSimple() && \"Expected a SimpleValueType!\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/include/llvm/CodeGen/ValueTypes.h" , 290, __extension__ __PRETTY_FUNCTION__)); |
291 | return V; |
292 | } |
293 | |
294 | /// If this is a vector type, return the element type, otherwise return |
295 | /// this. |
296 | EVT getScalarType() const { |
297 | return isVector() ? getVectorElementType() : *this; |
298 | } |
299 | |
300 | /// Given a vector type, return the type of each element. |
301 | EVT getVectorElementType() const { |
302 | assert(isVector() && "Invalid vector type!")(static_cast <bool> (isVector() && "Invalid vector type!" ) ? void (0) : __assert_fail ("isVector() && \"Invalid vector type!\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/include/llvm/CodeGen/ValueTypes.h" , 302, __extension__ __PRETTY_FUNCTION__)); |
303 | if (isSimple()) |
304 | return V.getVectorElementType(); |
305 | return getExtendedVectorElementType(); |
306 | } |
307 | |
308 | /// Given a vector type, return the number of elements it contains. |
309 | unsigned getVectorNumElements() const { |
310 | assert(isVector() && "Invalid vector type!")(static_cast <bool> (isVector() && "Invalid vector type!" ) ? void (0) : __assert_fail ("isVector() && \"Invalid vector type!\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/include/llvm/CodeGen/ValueTypes.h" , 310, __extension__ __PRETTY_FUNCTION__)); |
311 | |
312 | if (isScalableVector()) |
313 | llvm::reportInvalidSizeRequest( |
314 | "Possible incorrect use of EVT::getVectorNumElements() for " |
315 | "scalable vector. Scalable flag may be dropped, use " |
316 | "EVT::getVectorElementCount() instead"); |
317 | |
318 | return isSimple() ? V.getVectorNumElements() |
319 | : getExtendedVectorNumElements(); |
320 | } |
321 | |
322 | // Given a (possibly scalable) vector type, return the ElementCount |
323 | ElementCount getVectorElementCount() const { |
324 | assert((isVector()) && "Invalid vector type!")(static_cast <bool> ((isVector()) && "Invalid vector type!" ) ? void (0) : __assert_fail ("(isVector()) && \"Invalid vector type!\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/include/llvm/CodeGen/ValueTypes.h" , 324, __extension__ __PRETTY_FUNCTION__)); |
325 | if (isSimple()) |
326 | return V.getVectorElementCount(); |
327 | |
328 | return getExtendedVectorElementCount(); |
329 | } |
330 | |
331 | /// Given a vector type, return the minimum number of elements it contains. |
332 | unsigned getVectorMinNumElements() const { |
333 | return getVectorElementCount().getKnownMinValue(); |
334 | } |
335 | |
336 | /// Return the size of the specified value type in bits. |
337 | /// |
338 | /// If the value type is a scalable vector type, the scalable property will |
339 | /// be set and the runtime size will be a positive integer multiple of the |
340 | /// base size. |
341 | TypeSize getSizeInBits() const { |
342 | if (isSimple()) |
343 | return V.getSizeInBits(); |
344 | return getExtendedSizeInBits(); |
345 | } |
346 | |
347 | /// Return the size of the specified fixed width value type in bits. The |
348 | /// function will assert if the type is scalable. |
349 | uint64_t getFixedSizeInBits() const { |
350 | return getSizeInBits().getFixedSize(); |
351 | } |
352 | |
353 | uint64_t getScalarSizeInBits() const { |
354 | return getScalarType().getSizeInBits().getFixedSize(); |
355 | } |
356 | |
357 | /// Return the number of bytes overwritten by a store of the specified value |
358 | /// type. |
359 | /// |
360 | /// If the value type is a scalable vector type, the scalable property will |
361 | /// be set and the runtime size will be a positive integer multiple of the |
362 | /// base size. |
363 | TypeSize getStoreSize() const { |
364 | TypeSize BaseSize = getSizeInBits(); |
365 | return {(BaseSize.getKnownMinSize() + 7) / 8, BaseSize.isScalable()}; |
366 | } |
367 | |
368 | /// Return the number of bits overwritten by a store of the specified value |
369 | /// type. |
370 | /// |
371 | /// If the value type is a scalable vector type, the scalable property will |
372 | /// be set and the runtime size will be a positive integer multiple of the |
373 | /// base size. |
374 | TypeSize getStoreSizeInBits() const { |
375 | return getStoreSize() * 8; |
376 | } |
377 | |
378 | /// Rounds the bit-width of the given integer EVT up to the nearest power of |
379 | /// two (and at least to eight), and returns the integer EVT with that |
380 | /// number of bits. |
381 | EVT getRoundIntegerType(LLVMContext &Context) const { |
382 | assert(isInteger() && !isVector() && "Invalid integer type!")(static_cast <bool> (isInteger() && !isVector() && "Invalid integer type!") ? void (0) : __assert_fail ("isInteger() && !isVector() && \"Invalid integer type!\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/include/llvm/CodeGen/ValueTypes.h" , 382, __extension__ __PRETTY_FUNCTION__)); |
383 | unsigned BitWidth = getSizeInBits(); |
384 | if (BitWidth <= 8) |
385 | return EVT(MVT::i8); |
386 | return getIntegerVT(Context, 1 << Log2_32_Ceil(BitWidth)); |
387 | } |
388 | |
389 | /// Finds the smallest simple value type that is greater than or equal to |
390 | /// half the width of this EVT. If no simple value type can be found, an |
391 | /// extended integer value type of half the size (rounded up) is returned. |
392 | EVT getHalfSizedIntegerVT(LLVMContext &Context) const { |
393 | assert(isInteger() && !isVector() && "Invalid integer type!")(static_cast <bool> (isInteger() && !isVector() && "Invalid integer type!") ? void (0) : __assert_fail ("isInteger() && !isVector() && \"Invalid integer type!\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/include/llvm/CodeGen/ValueTypes.h" , 393, __extension__ __PRETTY_FUNCTION__)); |
394 | unsigned EVTSize = getSizeInBits(); |
395 | for (unsigned IntVT = MVT::FIRST_INTEGER_VALUETYPE; |
396 | IntVT <= MVT::LAST_INTEGER_VALUETYPE; ++IntVT) { |
397 | EVT HalfVT = EVT((MVT::SimpleValueType)IntVT); |
398 | if (HalfVT.getSizeInBits() * 2 >= EVTSize) |
399 | return HalfVT; |
400 | } |
401 | return getIntegerVT(Context, (EVTSize + 1) / 2); |
402 | } |
403 | |
404 | /// Return a VT for an integer vector type with the size of the |
405 | /// elements doubled. The typed returned may be an extended type. |
406 | EVT widenIntegerVectorElementType(LLVMContext &Context) const { |
407 | EVT EltVT = getVectorElementType(); |
408 | EltVT = EVT::getIntegerVT(Context, 2 * EltVT.getSizeInBits()); |
409 | return EVT::getVectorVT(Context, EltVT, getVectorElementCount()); |
410 | } |
411 | |
412 | // Return a VT for a vector type with the same element type but |
413 | // half the number of elements. The type returned may be an |
414 | // extended type. |
415 | EVT getHalfNumVectorElementsVT(LLVMContext &Context) const { |
416 | EVT EltVT = getVectorElementType(); |
417 | auto EltCnt = getVectorElementCount(); |
418 | assert(EltCnt.isKnownEven() && "Splitting vector, but not in half!")(static_cast <bool> (EltCnt.isKnownEven() && "Splitting vector, but not in half!" ) ? void (0) : __assert_fail ("EltCnt.isKnownEven() && \"Splitting vector, but not in half!\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/include/llvm/CodeGen/ValueTypes.h" , 418, __extension__ __PRETTY_FUNCTION__)); |
419 | return EVT::getVectorVT(Context, EltVT, EltCnt.divideCoefficientBy(2)); |
420 | } |
421 | |
422 | // Return a VT for a vector type with the same element type but |
423 | // double the number of elements. The type returned may be an |
424 | // extended type. |
425 | EVT getDoubleNumVectorElementsVT(LLVMContext &Context) const { |
426 | EVT EltVT = getVectorElementType(); |
427 | auto EltCnt = getVectorElementCount(); |
428 | return EVT::getVectorVT(Context, EltVT, EltCnt * 2); |
429 | } |
430 | |
431 | /// Returns true if the given vector is a power of 2. |
432 | bool isPow2VectorType() const { |
433 | unsigned NElts = getVectorMinNumElements(); |
434 | return !(NElts & (NElts - 1)); |
435 | } |
436 | |
437 | /// Widens the length of the given vector EVT up to the nearest power of 2 |
438 | /// and returns that type. |
439 | EVT getPow2VectorType(LLVMContext &Context) const { |
440 | if (!isPow2VectorType()) { |
441 | ElementCount NElts = getVectorElementCount(); |
442 | unsigned NewMinCount = 1 << Log2_32_Ceil(NElts.getKnownMinValue()); |
443 | NElts = ElementCount::get(NewMinCount, NElts.isScalable()); |
444 | return EVT::getVectorVT(Context, getVectorElementType(), NElts); |
445 | } |
446 | else { |
447 | return *this; |
448 | } |
449 | } |
450 | |
451 | /// This function returns value type as a string, e.g. "i32". |
452 | std::string getEVTString() const; |
453 | |
454 | /// This method returns an LLVM type corresponding to the specified EVT. |
455 | /// For integer types, this returns an unsigned type. Note that this will |
456 | /// abort for types that cannot be represented. |
457 | Type *getTypeForEVT(LLVMContext &Context) const; |
458 | |
459 | /// Return the value type corresponding to the specified type. |
460 | /// This returns all pointers as iPTR. If HandleUnknown is true, unknown |
461 | /// types are returned as Other, otherwise they are invalid. |
462 | static EVT getEVT(Type *Ty, bool HandleUnknown = false); |
463 | |
464 | intptr_t getRawBits() const { |
465 | if (isSimple()) |
466 | return V.SimpleTy; |
467 | else |
468 | return (intptr_t)(LLVMTy); |
469 | } |
470 | |
471 | /// A meaningless but well-behaved order, useful for constructing |
472 | /// containers. |
473 | struct compareRawBits { |
474 | bool operator()(EVT L, EVT R) const { |
475 | if (L.V.SimpleTy == R.V.SimpleTy) |
476 | return L.LLVMTy < R.LLVMTy; |
477 | else |
478 | return L.V.SimpleTy < R.V.SimpleTy; |
479 | } |
480 | }; |
481 | |
482 | private: |
483 | // Methods for handling the Extended-type case in functions above. |
484 | // These are all out-of-line to prevent users of this header file |
485 | // from having a dependency on Type.h. |
486 | EVT changeExtendedTypeToInteger() const; |
487 | EVT changeExtendedVectorElementType(EVT EltVT) const; |
488 | EVT changeExtendedVectorElementTypeToInteger() const; |
489 | static EVT getExtendedIntegerVT(LLVMContext &C, unsigned BitWidth); |
490 | static EVT getExtendedVectorVT(LLVMContext &C, EVT VT, unsigned NumElements, |
491 | bool IsScalable); |
492 | static EVT getExtendedVectorVT(LLVMContext &Context, EVT VT, |
493 | ElementCount EC); |
494 | bool isExtendedFloatingPoint() const LLVM_READONLY__attribute__((__pure__)); |
495 | bool isExtendedInteger() const LLVM_READONLY__attribute__((__pure__)); |
496 | bool isExtendedScalarInteger() const LLVM_READONLY__attribute__((__pure__)); |
497 | bool isExtendedVector() const LLVM_READONLY__attribute__((__pure__)); |
498 | bool isExtended16BitVector() const LLVM_READONLY__attribute__((__pure__)); |
499 | bool isExtended32BitVector() const LLVM_READONLY__attribute__((__pure__)); |
500 | bool isExtended64BitVector() const LLVM_READONLY__attribute__((__pure__)); |
501 | bool isExtended128BitVector() const LLVM_READONLY__attribute__((__pure__)); |
502 | bool isExtended256BitVector() const LLVM_READONLY__attribute__((__pure__)); |
503 | bool isExtended512BitVector() const LLVM_READONLY__attribute__((__pure__)); |
504 | bool isExtended1024BitVector() const LLVM_READONLY__attribute__((__pure__)); |
505 | bool isExtended2048BitVector() const LLVM_READONLY__attribute__((__pure__)); |
506 | bool isExtendedFixedLengthVector() const LLVM_READONLY__attribute__((__pure__)); |
507 | bool isExtendedScalableVector() const LLVM_READONLY__attribute__((__pure__)); |
508 | EVT getExtendedVectorElementType() const; |
509 | unsigned getExtendedVectorNumElements() const LLVM_READONLY__attribute__((__pure__)); |
510 | ElementCount getExtendedVectorElementCount() const LLVM_READONLY__attribute__((__pure__)); |
511 | TypeSize getExtendedSizeInBits() const LLVM_READONLY__attribute__((__pure__)); |
512 | }; |
513 | |
514 | } // end namespace llvm |
515 | |
516 | #endif // LLVM_CODEGEN_VALUETYPES_H |
1 | //===- llvm/DataLayout.h - Data size & alignment info -----------*- C++ -*-===// |
2 | // |
3 | // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. |
4 | // See https://llvm.org/LICENSE.txt for license information. |
5 | // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception |
6 | // |
7 | //===----------------------------------------------------------------------===// |
8 | // |
9 | // This file defines layout properties related to datatype size/offset/alignment |
10 | // information. It uses lazy annotations to cache information about how |
11 | // structure types are laid out and used. |
12 | // |
13 | // This structure should be created once, filled in if the defaults are not |
14 | // correct and then passed around by const&. None of the members functions |
15 | // require modification to the object. |
16 | // |
17 | //===----------------------------------------------------------------------===// |
18 | |
19 | #ifndef LLVM_IR_DATALAYOUT_H |
20 | #define LLVM_IR_DATALAYOUT_H |
21 | |
22 | #include "llvm/ADT/APInt.h" |
23 | #include "llvm/ADT/ArrayRef.h" |
24 | #include "llvm/ADT/STLExtras.h" |
25 | #include "llvm/ADT/SmallVector.h" |
26 | #include "llvm/ADT/StringRef.h" |
27 | #include "llvm/IR/DerivedTypes.h" |
28 | #include "llvm/IR/Type.h" |
29 | #include "llvm/Support/Casting.h" |
30 | #include "llvm/Support/ErrorHandling.h" |
31 | #include "llvm/Support/MathExtras.h" |
32 | #include "llvm/Support/Alignment.h" |
33 | #include "llvm/Support/TrailingObjects.h" |
34 | #include "llvm/Support/TypeSize.h" |
35 | #include <cassert> |
36 | #include <cstdint> |
37 | #include <string> |
38 | |
39 | // This needs to be outside of the namespace, to avoid conflict with llvm-c |
40 | // decl. |
41 | using LLVMTargetDataRef = struct LLVMOpaqueTargetData *; |
42 | |
43 | namespace llvm { |
44 | |
45 | class GlobalVariable; |
46 | class LLVMContext; |
47 | class Module; |
48 | class StructLayout; |
49 | class Triple; |
50 | class Value; |
51 | |
52 | /// Enum used to categorize the alignment types stored by LayoutAlignElem |
53 | enum AlignTypeEnum { |
54 | INVALID_ALIGN = 0, |
55 | INTEGER_ALIGN = 'i', |
56 | VECTOR_ALIGN = 'v', |
57 | FLOAT_ALIGN = 'f', |
58 | AGGREGATE_ALIGN = 'a' |
59 | }; |
60 | |
61 | // FIXME: Currently the DataLayout string carries a "preferred alignment" |
62 | // for types. As the DataLayout is module/global, this should likely be |
63 | // sunk down to an FTTI element that is queried rather than a global |
64 | // preference. |
65 | |
66 | /// Layout alignment element. |
67 | /// |
68 | /// Stores the alignment data associated with a given alignment type (integer, |
69 | /// vector, float) and type bit width. |
70 | /// |
71 | /// \note The unusual order of elements in the structure attempts to reduce |
72 | /// padding and make the structure slightly more cache friendly. |
73 | struct LayoutAlignElem { |
74 | /// Alignment type from \c AlignTypeEnum |
75 | unsigned AlignType : 8; |
76 | unsigned TypeBitWidth : 24; |
77 | Align ABIAlign; |
78 | Align PrefAlign; |
79 | |
80 | static LayoutAlignElem get(AlignTypeEnum align_type, Align abi_align, |
81 | Align pref_align, uint32_t bit_width); |
82 | |
83 | bool operator==(const LayoutAlignElem &rhs) const; |
84 | }; |
85 | |
86 | /// Layout pointer alignment element. |
87 | /// |
88 | /// Stores the alignment data associated with a given pointer and address space. |
89 | /// |
90 | /// \note The unusual order of elements in the structure attempts to reduce |
91 | /// padding and make the structure slightly more cache friendly. |
92 | struct PointerAlignElem { |
93 | Align ABIAlign; |
94 | Align PrefAlign; |
95 | uint32_t TypeByteWidth; |
96 | uint32_t AddressSpace; |
97 | uint32_t IndexWidth; |
98 | |
99 | /// Initializer |
100 | static PointerAlignElem get(uint32_t AddressSpace, Align ABIAlign, |
101 | Align PrefAlign, uint32_t TypeByteWidth, |
102 | uint32_t IndexWidth); |
103 | |
104 | bool operator==(const PointerAlignElem &rhs) const; |
105 | }; |
106 | |
107 | /// A parsed version of the target data layout string in and methods for |
108 | /// querying it. |
109 | /// |
110 | /// The target data layout string is specified *by the target* - a frontend |
111 | /// generating LLVM IR is required to generate the right target data for the |
112 | /// target being codegen'd to. |
113 | class DataLayout { |
114 | public: |
115 | enum class FunctionPtrAlignType { |
116 | /// The function pointer alignment is independent of the function alignment. |
117 | Independent, |
118 | /// The function pointer alignment is a multiple of the function alignment. |
119 | MultipleOfFunctionAlign, |
120 | }; |
121 | private: |
122 | /// Defaults to false. |
123 | bool BigEndian; |
124 | |
125 | unsigned AllocaAddrSpace; |
126 | MaybeAlign StackNaturalAlign; |
127 | unsigned ProgramAddrSpace; |
128 | unsigned DefaultGlobalsAddrSpace; |
129 | |
130 | MaybeAlign FunctionPtrAlign; |
131 | FunctionPtrAlignType TheFunctionPtrAlignType; |
132 | |
133 | enum ManglingModeT { |
134 | MM_None, |
135 | MM_ELF, |
136 | MM_MachO, |
137 | MM_WinCOFF, |
138 | MM_WinCOFFX86, |
139 | MM_GOFF, |
140 | MM_Mips, |
141 | MM_XCOFF |
142 | }; |
143 | ManglingModeT ManglingMode; |
144 | |
145 | SmallVector<unsigned char, 8> LegalIntWidths; |
146 | |
147 | /// Primitive type alignment data. This is sorted by type and bit |
148 | /// width during construction. |
149 | using AlignmentsTy = SmallVector<LayoutAlignElem, 16>; |
150 | AlignmentsTy Alignments; |
151 | |
152 | AlignmentsTy::const_iterator |
153 | findAlignmentLowerBound(AlignTypeEnum AlignType, uint32_t BitWidth) const { |
154 | return const_cast<DataLayout *>(this)->findAlignmentLowerBound(AlignType, |
155 | BitWidth); |
156 | } |
157 | |
158 | AlignmentsTy::iterator |
159 | findAlignmentLowerBound(AlignTypeEnum AlignType, uint32_t BitWidth); |
160 | |
161 | /// The string representation used to create this DataLayout |
162 | std::string StringRepresentation; |
163 | |
164 | using PointersTy = SmallVector<PointerAlignElem, 8>; |
165 | PointersTy Pointers; |
166 | |
167 | const PointerAlignElem &getPointerAlignElem(uint32_t AddressSpace) const; |
168 | |
169 | // The StructType -> StructLayout map. |
170 | mutable void *LayoutMap = nullptr; |
171 | |
172 | /// Pointers in these address spaces are non-integral, and don't have a |
173 | /// well-defined bitwise representation. |
174 | SmallVector<unsigned, 8> NonIntegralAddressSpaces; |
175 | |
176 | /// Attempts to set the alignment of the given type. Returns an error |
177 | /// description on failure. |
178 | Error setAlignment(AlignTypeEnum align_type, Align abi_align, |
179 | Align pref_align, uint32_t bit_width); |
180 | |
181 | /// Attempts to set the alignment of a pointer in the given address space. |
182 | /// Returns an error description on failure. |
183 | Error setPointerAlignment(uint32_t AddrSpace, Align ABIAlign, Align PrefAlign, |
184 | uint32_t TypeByteWidth, uint32_t IndexWidth); |
185 | |
186 | /// Internal helper to get alignment for integer of given bitwidth. |
187 | Align getIntegerAlignment(uint32_t BitWidth, bool abi_or_pref) const; |
188 | |
189 | /// Internal helper method that returns requested alignment for type. |
190 | Align getAlignment(Type *Ty, bool abi_or_pref) const; |
191 | |
192 | /// Attempts to parse a target data specification string and reports an error |
193 | /// if the string is malformed. |
194 | Error parseSpecifier(StringRef Desc); |
195 | |
196 | // Free all internal data structures. |
197 | void clear(); |
198 | |
199 | public: |
200 | /// Constructs a DataLayout from a specification string. See reset(). |
201 | explicit DataLayout(StringRef LayoutDescription) { |
202 | reset(LayoutDescription); |
203 | } |
204 | |
205 | /// Initialize target data from properties stored in the module. |
206 | explicit DataLayout(const Module *M); |
207 | |
208 | DataLayout(const DataLayout &DL) { *this = DL; } |
209 | |
210 | ~DataLayout(); // Not virtual, do not subclass this class |
211 | |
212 | DataLayout &operator=(const DataLayout &DL) { |
213 | clear(); |
214 | StringRepresentation = DL.StringRepresentation; |
215 | BigEndian = DL.isBigEndian(); |
216 | AllocaAddrSpace = DL.AllocaAddrSpace; |
217 | StackNaturalAlign = DL.StackNaturalAlign; |
218 | FunctionPtrAlign = DL.FunctionPtrAlign; |
219 | TheFunctionPtrAlignType = DL.TheFunctionPtrAlignType; |
220 | ProgramAddrSpace = DL.ProgramAddrSpace; |
221 | DefaultGlobalsAddrSpace = DL.DefaultGlobalsAddrSpace; |
222 | ManglingMode = DL.ManglingMode; |
223 | LegalIntWidths = DL.LegalIntWidths; |
224 | Alignments = DL.Alignments; |
225 | Pointers = DL.Pointers; |
226 | NonIntegralAddressSpaces = DL.NonIntegralAddressSpaces; |
227 | return *this; |
228 | } |
229 | |
230 | bool operator==(const DataLayout &Other) const; |
231 | bool operator!=(const DataLayout &Other) const { return !(*this == Other); } |
232 | |
233 | void init(const Module *M); |
234 | |
235 | /// Parse a data layout string (with fallback to default values). |
236 | void reset(StringRef LayoutDescription); |
237 | |
238 | /// Parse a data layout string and return the layout. Return an error |
239 | /// description on failure. |
240 | static Expected<DataLayout> parse(StringRef LayoutDescription); |
241 | |
242 | /// Layout endianness... |
243 | bool isLittleEndian() const { return !BigEndian; } |
244 | bool isBigEndian() const { return BigEndian; } |
245 | |
246 | /// Returns the string representation of the DataLayout. |
247 | /// |
248 | /// This representation is in the same format accepted by the string |
249 | /// constructor above. This should not be used to compare two DataLayout as |
250 | /// different string can represent the same layout. |
251 | const std::string &getStringRepresentation() const { |
252 | return StringRepresentation; |
253 | } |
254 | |
255 | /// Test if the DataLayout was constructed from an empty string. |
256 | bool isDefault() const { return StringRepresentation.empty(); } |
257 | |
258 | /// Returns true if the specified type is known to be a native integer |
259 | /// type supported by the CPU. |
260 | /// |
261 | /// For example, i64 is not native on most 32-bit CPUs and i37 is not native |
262 | /// on any known one. This returns false if the integer width is not legal. |
263 | /// |
264 | /// The width is specified in bits. |
265 | bool isLegalInteger(uint64_t Width) const { |
266 | return llvm::is_contained(LegalIntWidths, Width); |
267 | } |
268 | |
269 | bool isIllegalInteger(uint64_t Width) const { return !isLegalInteger(Width); } |
270 | |
271 | /// Returns true if the given alignment exceeds the natural stack alignment. |
272 | bool exceedsNaturalStackAlignment(Align Alignment) const { |
273 | return StackNaturalAlign && (Alignment > *StackNaturalAlign); |
274 | } |
275 | |
276 | Align getStackAlignment() const { |
277 | assert(StackNaturalAlign && "StackNaturalAlign must be defined")(static_cast <bool> (StackNaturalAlign && "StackNaturalAlign must be defined" ) ? void (0) : __assert_fail ("StackNaturalAlign && \"StackNaturalAlign must be defined\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/include/llvm/IR/DataLayout.h" , 277, __extension__ __PRETTY_FUNCTION__)); |
278 | return *StackNaturalAlign; |
279 | } |
280 | |
281 | unsigned getAllocaAddrSpace() const { return AllocaAddrSpace; } |
282 | |
283 | /// Returns the alignment of function pointers, which may or may not be |
284 | /// related to the alignment of functions. |
285 | /// \see getFunctionPtrAlignType |
286 | MaybeAlign getFunctionPtrAlign() const { return FunctionPtrAlign; } |
287 | |
288 | /// Return the type of function pointer alignment. |
289 | /// \see getFunctionPtrAlign |
290 | FunctionPtrAlignType getFunctionPtrAlignType() const { |
291 | return TheFunctionPtrAlignType; |
292 | } |
293 | |
294 | unsigned getProgramAddressSpace() const { return ProgramAddrSpace; } |
295 | unsigned getDefaultGlobalsAddressSpace() const { |
296 | return DefaultGlobalsAddrSpace; |
297 | } |
298 | |
299 | bool hasMicrosoftFastStdCallMangling() const { |
300 | return ManglingMode == MM_WinCOFFX86; |
301 | } |
302 | |
303 | /// Returns true if symbols with leading question marks should not receive IR |
304 | /// mangling. True for Windows mangling modes. |
305 | bool doNotMangleLeadingQuestionMark() const { |
306 | return ManglingMode == MM_WinCOFF || ManglingMode == MM_WinCOFFX86; |
307 | } |
308 | |
309 | bool hasLinkerPrivateGlobalPrefix() const { return ManglingMode == MM_MachO; } |
310 | |
311 | StringRef getLinkerPrivateGlobalPrefix() const { |
312 | if (ManglingMode == MM_MachO) |
313 | return "l"; |
314 | return ""; |
315 | } |
316 | |
317 | char getGlobalPrefix() const { |
318 | switch (ManglingMode) { |
319 | case MM_None: |
320 | case MM_ELF: |
321 | case MM_GOFF: |
322 | case MM_Mips: |
323 | case MM_WinCOFF: |
324 | case MM_XCOFF: |
325 | return '\0'; |
326 | case MM_MachO: |
327 | case MM_WinCOFFX86: |
328 | return '_'; |
329 | } |
330 | llvm_unreachable("invalid mangling mode")::llvm::llvm_unreachable_internal("invalid mangling mode", "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/include/llvm/IR/DataLayout.h" , 330); |
331 | } |
332 | |
333 | StringRef getPrivateGlobalPrefix() const { |
334 | switch (ManglingMode) { |
335 | case MM_None: |
336 | return ""; |
337 | case MM_ELF: |
338 | case MM_WinCOFF: |
339 | return ".L"; |
340 | case MM_GOFF: |
341 | return "@"; |
342 | case MM_Mips: |
343 | return "$"; |
344 | case MM_MachO: |
345 | case MM_WinCOFFX86: |
346 | return "L"; |
347 | case MM_XCOFF: |
348 | return "L.."; |
349 | } |
350 | llvm_unreachable("invalid mangling mode")::llvm::llvm_unreachable_internal("invalid mangling mode", "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/include/llvm/IR/DataLayout.h" , 350); |
351 | } |
352 | |
353 | static const char *getManglingComponent(const Triple &T); |
354 | |
355 | /// Returns true if the specified type fits in a native integer type |
356 | /// supported by the CPU. |
357 | /// |
358 | /// For example, if the CPU only supports i32 as a native integer type, then |
359 | /// i27 fits in a legal integer type but i45 does not. |
360 | bool fitsInLegalInteger(unsigned Width) const { |
361 | for (unsigned LegalIntWidth : LegalIntWidths) |
362 | if (Width <= LegalIntWidth) |
363 | return true; |
364 | return false; |
365 | } |
366 | |
367 | /// Layout pointer alignment |
368 | Align getPointerABIAlignment(unsigned AS) const; |
369 | |
370 | /// Return target's alignment for stack-based pointers |
371 | /// FIXME: The defaults need to be removed once all of |
372 | /// the backends/clients are updated. |
373 | Align getPointerPrefAlignment(unsigned AS = 0) const; |
374 | |
375 | /// Layout pointer size |
376 | /// FIXME: The defaults need to be removed once all of |
377 | /// the backends/clients are updated. |
378 | unsigned getPointerSize(unsigned AS = 0) const; |
379 | |
380 | /// Returns the maximum index size over all address spaces. |
381 | unsigned getMaxIndexSize() const; |
382 | |
383 | // Index size used for address calculation. |
384 | unsigned getIndexSize(unsigned AS) const; |
385 | |
386 | /// Return the address spaces containing non-integral pointers. Pointers in |
387 | /// this address space don't have a well-defined bitwise representation. |
388 | ArrayRef<unsigned> getNonIntegralAddressSpaces() const { |
389 | return NonIntegralAddressSpaces; |
390 | } |
391 | |
392 | bool isNonIntegralAddressSpace(unsigned AddrSpace) const { |
393 | ArrayRef<unsigned> NonIntegralSpaces = getNonIntegralAddressSpaces(); |
394 | return is_contained(NonIntegralSpaces, AddrSpace); |
395 | } |
396 | |
397 | bool isNonIntegralPointerType(PointerType *PT) const { |
398 | return isNonIntegralAddressSpace(PT->getAddressSpace()); |
399 | } |
400 | |
401 | bool isNonIntegralPointerType(Type *Ty) const { |
402 | auto *PTy = dyn_cast<PointerType>(Ty); |
403 | return PTy && isNonIntegralPointerType(PTy); |
404 | } |
405 | |
406 | /// Layout pointer size, in bits |
407 | /// FIXME: The defaults need to be removed once all of |
408 | /// the backends/clients are updated. |
409 | unsigned getPointerSizeInBits(unsigned AS = 0) const { |
410 | return getPointerSize(AS) * 8; |
411 | } |
412 | |
413 | /// Returns the maximum index size over all address spaces. |
414 | unsigned getMaxIndexSizeInBits() const { |
415 | return getMaxIndexSize() * 8; |
416 | } |
417 | |
418 | /// Size in bits of index used for address calculation in getelementptr. |
419 | unsigned getIndexSizeInBits(unsigned AS) const { |
420 | return getIndexSize(AS) * 8; |
421 | } |
422 | |
423 | /// Layout pointer size, in bits, based on the type. If this function is |
424 | /// called with a pointer type, then the type size of the pointer is returned. |
425 | /// If this function is called with a vector of pointers, then the type size |
426 | /// of the pointer is returned. This should only be called with a pointer or |
427 | /// vector of pointers. |
428 | unsigned getPointerTypeSizeInBits(Type *) const; |
429 | |
430 | /// Layout size of the index used in GEP calculation. |
431 | /// The function should be called with pointer or vector of pointers type. |
432 | unsigned getIndexTypeSizeInBits(Type *Ty) const; |
433 | |
434 | unsigned getPointerTypeSize(Type *Ty) const { |
435 | return getPointerTypeSizeInBits(Ty) / 8; |
436 | } |
437 | |
438 | /// Size examples: |
439 | /// |
440 | /// Type SizeInBits StoreSizeInBits AllocSizeInBits[*] |
441 | /// ---- ---------- --------------- --------------- |
442 | /// i1 1 8 8 |
443 | /// i8 8 8 8 |
444 | /// i19 19 24 32 |
445 | /// i32 32 32 32 |
446 | /// i100 100 104 128 |
447 | /// i128 128 128 128 |
448 | /// Float 32 32 32 |
449 | /// Double 64 64 64 |
450 | /// X86_FP80 80 80 96 |
451 | /// |
452 | /// [*] The alloc size depends on the alignment, and thus on the target. |
453 | /// These values are for x86-32 linux. |
454 | |
455 | /// Returns the number of bits necessary to hold the specified type. |
456 | /// |
457 | /// If Ty is a scalable vector type, the scalable property will be set and |
458 | /// the runtime size will be a positive integer multiple of the base size. |
459 | /// |
460 | /// For example, returns 36 for i36 and 80 for x86_fp80. The type passed must |
461 | /// have a size (Type::isSized() must return true). |
462 | TypeSize getTypeSizeInBits(Type *Ty) const; |
463 | |
464 | /// Returns the maximum number of bytes that may be overwritten by |
465 | /// storing the specified type. |
466 | /// |
467 | /// If Ty is a scalable vector type, the scalable property will be set and |
468 | /// the runtime size will be a positive integer multiple of the base size. |
469 | /// |
470 | /// For example, returns 5 for i36 and 10 for x86_fp80. |
471 | TypeSize getTypeStoreSize(Type *Ty) const { |
472 | TypeSize BaseSize = getTypeSizeInBits(Ty); |
473 | return { (BaseSize.getKnownMinSize() + 7) / 8, BaseSize.isScalable() }; |
474 | } |
475 | |
476 | /// Returns the maximum number of bits that may be overwritten by |
477 | /// storing the specified type; always a multiple of 8. |
478 | /// |
479 | /// If Ty is a scalable vector type, the scalable property will be set and |
480 | /// the runtime size will be a positive integer multiple of the base size. |
481 | /// |
482 | /// For example, returns 40 for i36 and 80 for x86_fp80. |
483 | TypeSize getTypeStoreSizeInBits(Type *Ty) const { |
484 | return 8 * getTypeStoreSize(Ty); |
485 | } |
486 | |
487 | /// Returns true if no extra padding bits are needed when storing the |
488 | /// specified type. |
489 | /// |
490 | /// For example, returns false for i19 that has a 24-bit store size. |
491 | bool typeSizeEqualsStoreSize(Type *Ty) const { |
492 | return getTypeSizeInBits(Ty) == getTypeStoreSizeInBits(Ty); |
493 | } |
494 | |
495 | /// Returns the offset in bytes between successive objects of the |
496 | /// specified type, including alignment padding. |
497 | /// |
498 | /// If Ty is a scalable vector type, the scalable property will be set and |
499 | /// the runtime size will be a positive integer multiple of the base size. |
500 | /// |
501 | /// This is the amount that alloca reserves for this type. For example, |
502 | /// returns 12 or 16 for x86_fp80, depending on alignment. |
503 | TypeSize getTypeAllocSize(Type *Ty) const { |
504 | // Round up to the next alignment boundary. |
505 | return alignTo(getTypeStoreSize(Ty), getABITypeAlignment(Ty)); |
506 | } |
507 | |
508 | /// Returns the offset in bits between successive objects of the |
509 | /// specified type, including alignment padding; always a multiple of 8. |
510 | /// |
511 | /// If Ty is a scalable vector type, the scalable property will be set and |
512 | /// the runtime size will be a positive integer multiple of the base size. |
513 | /// |
514 | /// This is the amount that alloca reserves for this type. For example, |
515 | /// returns 96 or 128 for x86_fp80, depending on alignment. |
516 | TypeSize getTypeAllocSizeInBits(Type *Ty) const { |
517 | return 8 * getTypeAllocSize(Ty); |
518 | } |
519 | |
520 | /// Returns the minimum ABI-required alignment for the specified type. |
521 | /// FIXME: Deprecate this function once migration to Align is over. |
522 | uint64_t getABITypeAlignment(Type *Ty) const; |
523 | |
524 | /// Returns the minimum ABI-required alignment for the specified type. |
525 | Align getABITypeAlign(Type *Ty) const; |
526 | |
527 | /// Helper function to return `Alignment` if it's set or the result of |
528 | /// `getABITypeAlignment(Ty)`, in any case the result is a valid alignment. |
529 | inline Align getValueOrABITypeAlignment(MaybeAlign Alignment, |
530 | Type *Ty) const { |
531 | return Alignment ? *Alignment : getABITypeAlign(Ty); |
532 | } |
533 | |
534 | /// Returns the minimum ABI-required alignment for an integer type of |
535 | /// the specified bitwidth. |
536 | Align getABIIntegerTypeAlignment(unsigned BitWidth) const { |
537 | return getIntegerAlignment(BitWidth, /* abi_or_pref */ true); |
538 | } |
539 | |
540 | /// Returns the preferred stack/global alignment for the specified |
541 | /// type. |
542 | /// |
543 | /// This is always at least as good as the ABI alignment. |
544 | /// FIXME: Deprecate this function once migration to Align is over. |
545 | uint64_t getPrefTypeAlignment(Type *Ty) const; |
546 | |
547 | /// Returns the preferred stack/global alignment for the specified |
548 | /// type. |
549 | /// |
550 | /// This is always at least as good as the ABI alignment. |
551 | Align getPrefTypeAlign(Type *Ty) const; |
552 | |
553 | /// Returns an integer type with size at least as big as that of a |
554 | /// pointer in the given address space. |
555 | IntegerType *getIntPtrType(LLVMContext &C, unsigned AddressSpace = 0) const; |
556 | |
557 | /// Returns an integer (vector of integer) type with size at least as |
558 | /// big as that of a pointer of the given pointer (vector of pointer) type. |
559 | Type *getIntPtrType(Type *) const; |
560 | |
561 | /// Returns the smallest integer type with size at least as big as |
562 | /// Width bits. |
563 | Type *getSmallestLegalIntType(LLVMContext &C, unsigned Width = 0) const; |
564 | |
565 | /// Returns the largest legal integer type, or null if none are set. |
566 | Type *getLargestLegalIntType(LLVMContext &C) const { |
567 | unsigned LargestSize = getLargestLegalIntTypeSizeInBits(); |
568 | return (LargestSize == 0) ? nullptr : Type::getIntNTy(C, LargestSize); |
569 | } |
570 | |
571 | /// Returns the size of largest legal integer type size, or 0 if none |
572 | /// are set. |
573 | unsigned getLargestLegalIntTypeSizeInBits() const; |
574 | |
575 | /// Returns the type of a GEP index. |
576 | /// If it was not specified explicitly, it will be the integer type of the |
577 | /// pointer width - IntPtrType. |
578 | Type *getIndexType(Type *PtrTy) const; |
579 | |
580 | /// Returns the offset from the beginning of the type for the specified |
581 | /// indices. |
582 | /// |
583 | /// Note that this takes the element type, not the pointer type. |
584 | /// This is used to implement getelementptr. |
585 | int64_t getIndexedOffsetInType(Type *ElemTy, ArrayRef<Value *> Indices) const; |
586 | |
587 | /// Get GEP indices to access Offset inside ElemTy. ElemTy is updated to be |
588 | /// the result element type and Offset to be the residual offset. |
589 | SmallVector<APInt> getGEPIndicesForOffset(Type *&ElemTy, APInt &Offset) const; |
590 | |
591 | /// Returns a StructLayout object, indicating the alignment of the |
592 | /// struct, its size, and the offsets of its fields. |
593 | /// |
594 | /// Note that this information is lazily cached. |
595 | const StructLayout *getStructLayout(StructType *Ty) const; |
596 | |
597 | /// Returns the preferred alignment of the specified global. |
598 | /// |
599 | /// This includes an explicitly requested alignment (if the global has one). |
600 | Align getPreferredAlign(const GlobalVariable *GV) const; |
601 | }; |
602 | |
603 | inline DataLayout *unwrap(LLVMTargetDataRef P) { |
604 | return reinterpret_cast<DataLayout *>(P); |
605 | } |
606 | |
607 | inline LLVMTargetDataRef wrap(const DataLayout *P) { |
608 | return reinterpret_cast<LLVMTargetDataRef>(const_cast<DataLayout *>(P)); |
609 | } |
610 | |
611 | /// Used to lazily calculate structure layout information for a target machine, |
612 | /// based on the DataLayout structure. |
613 | class StructLayout final : public TrailingObjects<StructLayout, uint64_t> { |
614 | uint64_t StructSize; |
615 | Align StructAlignment; |
616 | unsigned IsPadded : 1; |
617 | unsigned NumElements : 31; |
618 | |
619 | public: |
620 | uint64_t getSizeInBytes() const { return StructSize; } |
621 | |
622 | uint64_t getSizeInBits() const { return 8 * StructSize; } |
623 | |
624 | Align getAlignment() const { return StructAlignment; } |
625 | |
626 | /// Returns whether the struct has padding or not between its fields. |
627 | /// NB: Padding in nested element is not taken into account. |
628 | bool hasPadding() const { return IsPadded; } |
629 | |
630 | /// Given a valid byte offset into the structure, returns the structure |
631 | /// index that contains it. |
632 | unsigned getElementContainingOffset(uint64_t Offset) const; |
633 | |
634 | MutableArrayRef<uint64_t> getMemberOffsets() { |
635 | return llvm::makeMutableArrayRef(getTrailingObjects<uint64_t>(), |
636 | NumElements); |
637 | } |
638 | |
639 | ArrayRef<uint64_t> getMemberOffsets() const { |
640 | return llvm::makeArrayRef(getTrailingObjects<uint64_t>(), NumElements); |
641 | } |
642 | |
643 | uint64_t getElementOffset(unsigned Idx) const { |
644 | assert(Idx < NumElements && "Invalid element idx!")(static_cast <bool> (Idx < NumElements && "Invalid element idx!" ) ? void (0) : __assert_fail ("Idx < NumElements && \"Invalid element idx!\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/include/llvm/IR/DataLayout.h" , 644, __extension__ __PRETTY_FUNCTION__)); |
645 | return getMemberOffsets()[Idx]; |
646 | } |
647 | |
648 | uint64_t getElementOffsetInBits(unsigned Idx) const { |
649 | return getElementOffset(Idx) * 8; |
650 | } |
651 | |
652 | private: |
653 | friend class DataLayout; // Only DataLayout can create this class |
654 | |
655 | StructLayout(StructType *ST, const DataLayout &DL); |
656 | |
657 | size_t numTrailingObjects(OverloadToken<uint64_t>) const { |
658 | return NumElements; |
659 | } |
660 | }; |
661 | |
662 | // The implementation of this method is provided inline as it is particularly |
663 | // well suited to constant folding when called on a specific Type subclass. |
664 | inline TypeSize DataLayout::getTypeSizeInBits(Type *Ty) const { |
665 | assert(Ty->isSized() && "Cannot getTypeInfo() on a type that is unsized!")(static_cast <bool> (Ty->isSized() && "Cannot getTypeInfo() on a type that is unsized!" ) ? void (0) : __assert_fail ("Ty->isSized() && \"Cannot getTypeInfo() on a type that is unsized!\"" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/include/llvm/IR/DataLayout.h" , 665, __extension__ __PRETTY_FUNCTION__)); |
666 | switch (Ty->getTypeID()) { |
667 | case Type::LabelTyID: |
668 | return TypeSize::Fixed(getPointerSizeInBits(0)); |
669 | case Type::PointerTyID: |
670 | return TypeSize::Fixed(getPointerSizeInBits(Ty->getPointerAddressSpace())); |
671 | case Type::ArrayTyID: { |
672 | ArrayType *ATy = cast<ArrayType>(Ty); |
673 | return ATy->getNumElements() * |
674 | getTypeAllocSizeInBits(ATy->getElementType()); |
675 | } |
676 | case Type::StructTyID: |
677 | // Get the layout annotation... which is lazily created on demand. |
678 | return TypeSize::Fixed( |
679 | getStructLayout(cast<StructType>(Ty))->getSizeInBits()); |
680 | case Type::IntegerTyID: |
681 | return TypeSize::Fixed(Ty->getIntegerBitWidth()); |
682 | case Type::HalfTyID: |
683 | case Type::BFloatTyID: |
684 | return TypeSize::Fixed(16); |
685 | case Type::FloatTyID: |
686 | return TypeSize::Fixed(32); |
687 | case Type::DoubleTyID: |
688 | case Type::X86_MMXTyID: |
689 | return TypeSize::Fixed(64); |
690 | case Type::PPC_FP128TyID: |
691 | case Type::FP128TyID: |
692 | return TypeSize::Fixed(128); |
693 | case Type::X86_AMXTyID: |
694 | return TypeSize::Fixed(8192); |
695 | // In memory objects this is always aligned to a higher boundary, but |
696 | // only 80 bits contain information. |
697 | case Type::X86_FP80TyID: |
698 | return TypeSize::Fixed(80); |
699 | case Type::FixedVectorTyID: |
700 | case Type::ScalableVectorTyID: { |
701 | VectorType *VTy = cast<VectorType>(Ty); |
702 | auto EltCnt = VTy->getElementCount(); |
703 | uint64_t MinBits = EltCnt.getKnownMinValue() * |
704 | getTypeSizeInBits(VTy->getElementType()).getFixedSize(); |
705 | return TypeSize(MinBits, EltCnt.isScalable()); |
706 | } |
707 | default: |
708 | llvm_unreachable("DataLayout::getTypeSizeInBits(): Unsupported type")::llvm::llvm_unreachable_internal("DataLayout::getTypeSizeInBits(): Unsupported type" , "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/include/llvm/IR/DataLayout.h" , 708); |
709 | } |
710 | } |
711 | |
712 | } // end namespace llvm |
713 | |
714 | #endif // LLVM_IR_DATALAYOUT_H |