Bug Summary

File:include/llvm/ADT/APInt.h
Warning:line 444, column 36
The result of the left shift is undefined due to shifting by '4294967295', which is greater or equal to the width of type 'llvm::APInt::WordType'

Annotated Source Code

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clang -cc1 -triple x86_64-pc-linux-gnu -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name TargetLowering.cpp -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=cplusplus -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -analyzer-config-compatibility-mode=true -mrelocation-model pic -pic-level 2 -mthread-model posix -mframe-pointer=none -fmath-errno -masm-verbose -mconstructor-aliases -munwind-tables -fuse-init-array -target-cpu x86-64 -dwarf-column-info -debugger-tuning=gdb -ffunction-sections -fdata-sections -resource-dir /usr/lib/llvm-10/lib/clang/10.0.0 -D _DEBUG -D _GNU_SOURCE -D __STDC_CONSTANT_MACROS -D __STDC_FORMAT_MACROS -D __STDC_LIMIT_MACROS -I /build/llvm-toolchain-snapshot-10~svn374877/build-llvm/lib/CodeGen/SelectionDAG -I /build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/SelectionDAG -I /build/llvm-toolchain-snapshot-10~svn374877/build-llvm/include -I /build/llvm-toolchain-snapshot-10~svn374877/include -U NDEBUG -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/x86_64-linux-gnu/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/x86_64-linux-gnu/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/c++/6.3.0/backward -internal-isystem /usr/local/include -internal-isystem /usr/lib/llvm-10/lib/clang/10.0.0/include -internal-externc-isystem /usr/include/x86_64-linux-gnu -internal-externc-isystem /include -internal-externc-isystem /usr/include -O2 -Wno-unused-parameter -Wwrite-strings -Wno-missing-field-initializers -Wno-long-long -Wno-maybe-uninitialized -Wno-comment -std=c++14 -fdeprecated-macro -fdebug-compilation-dir /build/llvm-toolchain-snapshot-10~svn374877/build-llvm/lib/CodeGen/SelectionDAG -fdebug-prefix-map=/build/llvm-toolchain-snapshot-10~svn374877=. -ferror-limit 19 -fmessage-length 0 -fvisibility-inlines-hidden -stack-protector 2 -fgnuc-version=4.2.1 -fobjc-runtime=gcc -fdiagnostics-show-option -vectorize-loops -vectorize-slp -analyzer-output=html -analyzer-config stable-report-filename=true -faddrsig -o /tmp/scan-build-2019-10-15-233810-7101-1 -x c++ /build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/SelectionDAG/TargetLowering.cpp

/build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/SelectionDAG/TargetLowering.cpp

1//===-- TargetLowering.cpp - Implement the TargetLowering class -----------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This implements the TargetLowering class.
10//
11//===----------------------------------------------------------------------===//
12
13#include "llvm/CodeGen/TargetLowering.h"
14#include "llvm/ADT/STLExtras.h"
15#include "llvm/CodeGen/CallingConvLower.h"
16#include "llvm/CodeGen/MachineFrameInfo.h"
17#include "llvm/CodeGen/MachineFunction.h"
18#include "llvm/CodeGen/MachineJumpTableInfo.h"
19#include "llvm/CodeGen/MachineRegisterInfo.h"
20#include "llvm/CodeGen/SelectionDAG.h"
21#include "llvm/CodeGen/TargetRegisterInfo.h"
22#include "llvm/CodeGen/TargetSubtargetInfo.h"
23#include "llvm/IR/DataLayout.h"
24#include "llvm/IR/DerivedTypes.h"
25#include "llvm/IR/GlobalVariable.h"
26#include "llvm/IR/LLVMContext.h"
27#include "llvm/MC/MCAsmInfo.h"
28#include "llvm/MC/MCExpr.h"
29#include "llvm/Support/ErrorHandling.h"
30#include "llvm/Support/KnownBits.h"
31#include "llvm/Support/MathExtras.h"
32#include "llvm/Target/TargetLoweringObjectFile.h"
33#include "llvm/Target/TargetMachine.h"
34#include <cctype>
35using namespace llvm;
36
37/// NOTE: The TargetMachine owns TLOF.
38TargetLowering::TargetLowering(const TargetMachine &tm)
39 : TargetLoweringBase(tm) {}
40
41const char *TargetLowering::getTargetNodeName(unsigned Opcode) const {
42 return nullptr;
43}
44
45bool TargetLowering::isPositionIndependent() const {
46 return getTargetMachine().isPositionIndependent();
47}
48
49/// Check whether a given call node is in tail position within its function. If
50/// so, it sets Chain to the input chain of the tail call.
51bool TargetLowering::isInTailCallPosition(SelectionDAG &DAG, SDNode *Node,
52 SDValue &Chain) const {
53 const Function &F = DAG.getMachineFunction().getFunction();
54
55 // Conservatively require the attributes of the call to match those of
56 // the return. Ignore NoAlias and NonNull because they don't affect the
57 // call sequence.
58 AttributeList CallerAttrs = F.getAttributes();
59 if (AttrBuilder(CallerAttrs, AttributeList::ReturnIndex)
60 .removeAttribute(Attribute::NoAlias)
61 .removeAttribute(Attribute::NonNull)
62 .hasAttributes())
63 return false;
64
65 // It's not safe to eliminate the sign / zero extension of the return value.
66 if (CallerAttrs.hasAttribute(AttributeList::ReturnIndex, Attribute::ZExt) ||
67 CallerAttrs.hasAttribute(AttributeList::ReturnIndex, Attribute::SExt))
68 return false;
69
70 // Check if the only use is a function return node.
71 return isUsedByReturnOnly(Node, Chain);
72}
73
74bool TargetLowering::parametersInCSRMatch(const MachineRegisterInfo &MRI,
75 const uint32_t *CallerPreservedMask,
76 const SmallVectorImpl<CCValAssign> &ArgLocs,
77 const SmallVectorImpl<SDValue> &OutVals) const {
78 for (unsigned I = 0, E = ArgLocs.size(); I != E; ++I) {
79 const CCValAssign &ArgLoc = ArgLocs[I];
80 if (!ArgLoc.isRegLoc())
81 continue;
82 Register Reg = ArgLoc.getLocReg();
83 // Only look at callee saved registers.
84 if (MachineOperand::clobbersPhysReg(CallerPreservedMask, Reg))
85 continue;
86 // Check that we pass the value used for the caller.
87 // (We look for a CopyFromReg reading a virtual register that is used
88 // for the function live-in value of register Reg)
89 SDValue Value = OutVals[I];
90 if (Value->getOpcode() != ISD::CopyFromReg)
91 return false;
92 unsigned ArgReg = cast<RegisterSDNode>(Value->getOperand(1))->getReg();
93 if (MRI.getLiveInPhysReg(ArgReg) != Reg)
94 return false;
95 }
96 return true;
97}
98
99/// Set CallLoweringInfo attribute flags based on a call instruction
100/// and called function attributes.
101void TargetLoweringBase::ArgListEntry::setAttributes(const CallBase *Call,
102 unsigned ArgIdx) {
103 IsSExt = Call->paramHasAttr(ArgIdx, Attribute::SExt);
104 IsZExt = Call->paramHasAttr(ArgIdx, Attribute::ZExt);
105 IsInReg = Call->paramHasAttr(ArgIdx, Attribute::InReg);
106 IsSRet = Call->paramHasAttr(ArgIdx, Attribute::StructRet);
107 IsNest = Call->paramHasAttr(ArgIdx, Attribute::Nest);
108 IsByVal = Call->paramHasAttr(ArgIdx, Attribute::ByVal);
109 IsInAlloca = Call->paramHasAttr(ArgIdx, Attribute::InAlloca);
110 IsReturned = Call->paramHasAttr(ArgIdx, Attribute::Returned);
111 IsSwiftSelf = Call->paramHasAttr(ArgIdx, Attribute::SwiftSelf);
112 IsSwiftError = Call->paramHasAttr(ArgIdx, Attribute::SwiftError);
113 Alignment = Call->getParamAlignment(ArgIdx);
114 ByValType = nullptr;
115 if (Call->paramHasAttr(ArgIdx, Attribute::ByVal))
116 ByValType = Call->getParamByValType(ArgIdx);
117}
118
119/// Generate a libcall taking the given operands as arguments and returning a
120/// result of type RetVT.
121std::pair<SDValue, SDValue>
122TargetLowering::makeLibCall(SelectionDAG &DAG, RTLIB::Libcall LC, EVT RetVT,
123 ArrayRef<SDValue> Ops,
124 MakeLibCallOptions CallOptions,
125 const SDLoc &dl) const {
126 TargetLowering::ArgListTy Args;
127 Args.reserve(Ops.size());
128
129 TargetLowering::ArgListEntry Entry;
130 for (unsigned i = 0; i < Ops.size(); ++i) {
131 SDValue NewOp = Ops[i];
132 Entry.Node = NewOp;
133 Entry.Ty = Entry.Node.getValueType().getTypeForEVT(*DAG.getContext());
134 Entry.IsSExt = shouldSignExtendTypeInLibCall(NewOp.getValueType(),
135 CallOptions.IsSExt);
136 Entry.IsZExt = !Entry.IsSExt;
137
138 if (CallOptions.IsSoften &&
139 !shouldExtendTypeInLibCall(CallOptions.OpsVTBeforeSoften[i])) {
140 Entry.IsSExt = Entry.IsZExt = false;
141 }
142 Args.push_back(Entry);
143 }
144
145 if (LC == RTLIB::UNKNOWN_LIBCALL)
146 report_fatal_error("Unsupported library call operation!");
147 SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC),
148 getPointerTy(DAG.getDataLayout()));
149
150 Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext());
151 TargetLowering::CallLoweringInfo CLI(DAG);
152 bool signExtend = shouldSignExtendTypeInLibCall(RetVT, CallOptions.IsSExt);
153 bool zeroExtend = !signExtend;
154
155 if (CallOptions.IsSoften &&
156 !shouldExtendTypeInLibCall(CallOptions.RetVTBeforeSoften)) {
157 signExtend = zeroExtend = false;
158 }
159
160 CLI.setDebugLoc(dl)
161 .setChain(DAG.getEntryNode())
162 .setLibCallee(getLibcallCallingConv(LC), RetTy, Callee, std::move(Args))
163 .setNoReturn(CallOptions.DoesNotReturn)
164 .setDiscardResult(!CallOptions.IsReturnValueUsed)
165 .setIsPostTypeLegalization(CallOptions.IsPostTypeLegalization)
166 .setSExtResult(signExtend)
167 .setZExtResult(zeroExtend);
168 return LowerCallTo(CLI);
169}
170
171bool
172TargetLowering::findOptimalMemOpLowering(std::vector<EVT> &MemOps,
173 unsigned Limit, uint64_t Size,
174 unsigned DstAlign, unsigned SrcAlign,
175 bool IsMemset,
176 bool ZeroMemset,
177 bool MemcpyStrSrc,
178 bool AllowOverlap,
179 unsigned DstAS, unsigned SrcAS,
180 const AttributeList &FuncAttributes) const {
181 // If 'SrcAlign' is zero, that means the memory operation does not need to
182 // load the value, i.e. memset or memcpy from constant string. Otherwise,
183 // it's the inferred alignment of the source. 'DstAlign', on the other hand,
184 // is the specified alignment of the memory operation. If it is zero, that
185 // means it's possible to change the alignment of the destination.
186 // 'MemcpyStrSrc' indicates whether the memcpy source is constant so it does
187 // not need to be loaded.
188 if (!(SrcAlign == 0 || SrcAlign >= DstAlign))
189 return false;
190
191 EVT VT = getOptimalMemOpType(Size, DstAlign, SrcAlign,
192 IsMemset, ZeroMemset, MemcpyStrSrc,
193 FuncAttributes);
194
195 if (VT == MVT::Other) {
196 // Use the largest integer type whose alignment constraints are satisfied.
197 // We only need to check DstAlign here as SrcAlign is always greater or
198 // equal to DstAlign (or zero).
199 VT = MVT::i64;
200 while (DstAlign && DstAlign < VT.getSizeInBits() / 8 &&
201 !allowsMisalignedMemoryAccesses(VT, DstAS, DstAlign))
202 VT = (MVT::SimpleValueType)(VT.getSimpleVT().SimpleTy - 1);
203 assert(VT.isInteger())((VT.isInteger()) ? static_cast<void> (0) : __assert_fail
("VT.isInteger()", "/build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/SelectionDAG/TargetLowering.cpp"
, 203, __PRETTY_FUNCTION__))
;
204
205 // Find the largest legal integer type.
206 MVT LVT = MVT::i64;
207 while (!isTypeLegal(LVT))
208 LVT = (MVT::SimpleValueType)(LVT.SimpleTy - 1);
209 assert(LVT.isInteger())((LVT.isInteger()) ? static_cast<void> (0) : __assert_fail
("LVT.isInteger()", "/build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/SelectionDAG/TargetLowering.cpp"
, 209, __PRETTY_FUNCTION__))
;
210
211 // If the type we've chosen is larger than the largest legal integer type
212 // then use that instead.
213 if (VT.bitsGT(LVT))
214 VT = LVT;
215 }
216
217 unsigned NumMemOps = 0;
218 while (Size != 0) {
219 unsigned VTSize = VT.getSizeInBits() / 8;
220 while (VTSize > Size) {
221 // For now, only use non-vector load / store's for the left-over pieces.
222 EVT NewVT = VT;
223 unsigned NewVTSize;
224
225 bool Found = false;
226 if (VT.isVector() || VT.isFloatingPoint()) {
227 NewVT = (VT.getSizeInBits() > 64) ? MVT::i64 : MVT::i32;
228 if (isOperationLegalOrCustom(ISD::STORE, NewVT) &&
229 isSafeMemOpType(NewVT.getSimpleVT()))
230 Found = true;
231 else if (NewVT == MVT::i64 &&
232 isOperationLegalOrCustom(ISD::STORE, MVT::f64) &&
233 isSafeMemOpType(MVT::f64)) {
234 // i64 is usually not legal on 32-bit targets, but f64 may be.
235 NewVT = MVT::f64;
236 Found = true;
237 }
238 }
239
240 if (!Found) {
241 do {
242 NewVT = (MVT::SimpleValueType)(NewVT.getSimpleVT().SimpleTy - 1);
243 if (NewVT == MVT::i8)
244 break;
245 } while (!isSafeMemOpType(NewVT.getSimpleVT()));
246 }
247 NewVTSize = NewVT.getSizeInBits() / 8;
248
249 // If the new VT cannot cover all of the remaining bits, then consider
250 // issuing a (or a pair of) unaligned and overlapping load / store.
251 bool Fast;
252 if (NumMemOps && AllowOverlap && NewVTSize < Size &&
253 allowsMisalignedMemoryAccesses(VT, DstAS, DstAlign,
254 MachineMemOperand::MONone, &Fast) &&
255 Fast)
256 VTSize = Size;
257 else {
258 VT = NewVT;
259 VTSize = NewVTSize;
260 }
261 }
262
263 if (++NumMemOps > Limit)
264 return false;
265
266 MemOps.push_back(VT);
267 Size -= VTSize;
268 }
269
270 return true;
271}
272
273/// Soften the operands of a comparison. This code is shared among BR_CC,
274/// SELECT_CC, and SETCC handlers.
275void TargetLowering::softenSetCCOperands(SelectionDAG &DAG, EVT VT,
276 SDValue &NewLHS, SDValue &NewRHS,
277 ISD::CondCode &CCCode,
278 const SDLoc &dl, const SDValue OldLHS,
279 const SDValue OldRHS) const {
280 assert((VT == MVT::f32 || VT == MVT::f64 || VT == MVT::f128 || VT == MVT::ppcf128)(((VT == MVT::f32 || VT == MVT::f64 || VT == MVT::f128 || VT ==
MVT::ppcf128) && "Unsupported setcc type!") ? static_cast
<void> (0) : __assert_fail ("(VT == MVT::f32 || VT == MVT::f64 || VT == MVT::f128 || VT == MVT::ppcf128) && \"Unsupported setcc type!\""
, "/build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/SelectionDAG/TargetLowering.cpp"
, 281, __PRETTY_FUNCTION__))
281 && "Unsupported setcc type!")(((VT == MVT::f32 || VT == MVT::f64 || VT == MVT::f128 || VT ==
MVT::ppcf128) && "Unsupported setcc type!") ? static_cast
<void> (0) : __assert_fail ("(VT == MVT::f32 || VT == MVT::f64 || VT == MVT::f128 || VT == MVT::ppcf128) && \"Unsupported setcc type!\""
, "/build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/SelectionDAG/TargetLowering.cpp"
, 281, __PRETTY_FUNCTION__))
;
282
283 // Expand into one or more soft-fp libcall(s).
284 RTLIB::Libcall LC1 = RTLIB::UNKNOWN_LIBCALL, LC2 = RTLIB::UNKNOWN_LIBCALL;
285 bool ShouldInvertCC = false;
286 switch (CCCode) {
287 case ISD::SETEQ:
288 case ISD::SETOEQ:
289 LC1 = (VT == MVT::f32) ? RTLIB::OEQ_F32 :
290 (VT == MVT::f64) ? RTLIB::OEQ_F64 :
291 (VT == MVT::f128) ? RTLIB::OEQ_F128 : RTLIB::OEQ_PPCF128;
292 break;
293 case ISD::SETNE:
294 case ISD::SETUNE:
295 LC1 = (VT == MVT::f32) ? RTLIB::UNE_F32 :
296 (VT == MVT::f64) ? RTLIB::UNE_F64 :
297 (VT == MVT::f128) ? RTLIB::UNE_F128 : RTLIB::UNE_PPCF128;
298 break;
299 case ISD::SETGE:
300 case ISD::SETOGE:
301 LC1 = (VT == MVT::f32) ? RTLIB::OGE_F32 :
302 (VT == MVT::f64) ? RTLIB::OGE_F64 :
303 (VT == MVT::f128) ? RTLIB::OGE_F128 : RTLIB::OGE_PPCF128;
304 break;
305 case ISD::SETLT:
306 case ISD::SETOLT:
307 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 :
308 (VT == MVT::f64) ? RTLIB::OLT_F64 :
309 (VT == MVT::f128) ? RTLIB::OLT_F128 : RTLIB::OLT_PPCF128;
310 break;
311 case ISD::SETLE:
312 case ISD::SETOLE:
313 LC1 = (VT == MVT::f32) ? RTLIB::OLE_F32 :
314 (VT == MVT::f64) ? RTLIB::OLE_F64 :
315 (VT == MVT::f128) ? RTLIB::OLE_F128 : RTLIB::OLE_PPCF128;
316 break;
317 case ISD::SETGT:
318 case ISD::SETOGT:
319 LC1 = (VT == MVT::f32) ? RTLIB::OGT_F32 :
320 (VT == MVT::f64) ? RTLIB::OGT_F64 :
321 (VT == MVT::f128) ? RTLIB::OGT_F128 : RTLIB::OGT_PPCF128;
322 break;
323 case ISD::SETUO:
324 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 :
325 (VT == MVT::f64) ? RTLIB::UO_F64 :
326 (VT == MVT::f128) ? RTLIB::UO_F128 : RTLIB::UO_PPCF128;
327 break;
328 case ISD::SETO:
329 LC1 = (VT == MVT::f32) ? RTLIB::O_F32 :
330 (VT == MVT::f64) ? RTLIB::O_F64 :
331 (VT == MVT::f128) ? RTLIB::O_F128 : RTLIB::O_PPCF128;
332 break;
333 case ISD::SETONE:
334 // SETONE = SETOLT | SETOGT
335 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 :
336 (VT == MVT::f64) ? RTLIB::OLT_F64 :
337 (VT == MVT::f128) ? RTLIB::OLT_F128 : RTLIB::OLT_PPCF128;
338 LC2 = (VT == MVT::f32) ? RTLIB::OGT_F32 :
339 (VT == MVT::f64) ? RTLIB::OGT_F64 :
340 (VT == MVT::f128) ? RTLIB::OGT_F128 : RTLIB::OGT_PPCF128;
341 break;
342 case ISD::SETUEQ:
343 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 :
344 (VT == MVT::f64) ? RTLIB::UO_F64 :
345 (VT == MVT::f128) ? RTLIB::UO_F128 : RTLIB::UO_PPCF128;
346 LC2 = (VT == MVT::f32) ? RTLIB::OEQ_F32 :
347 (VT == MVT::f64) ? RTLIB::OEQ_F64 :
348 (VT == MVT::f128) ? RTLIB::OEQ_F128 : RTLIB::OEQ_PPCF128;
349 break;
350 default:
351 // Invert CC for unordered comparisons
352 ShouldInvertCC = true;
353 switch (CCCode) {
354 case ISD::SETULT:
355 LC1 = (VT == MVT::f32) ? RTLIB::OGE_F32 :
356 (VT == MVT::f64) ? RTLIB::OGE_F64 :
357 (VT == MVT::f128) ? RTLIB::OGE_F128 : RTLIB::OGE_PPCF128;
358 break;
359 case ISD::SETULE:
360 LC1 = (VT == MVT::f32) ? RTLIB::OGT_F32 :
361 (VT == MVT::f64) ? RTLIB::OGT_F64 :
362 (VT == MVT::f128) ? RTLIB::OGT_F128 : RTLIB::OGT_PPCF128;
363 break;
364 case ISD::SETUGT:
365 LC1 = (VT == MVT::f32) ? RTLIB::OLE_F32 :
366 (VT == MVT::f64) ? RTLIB::OLE_F64 :
367 (VT == MVT::f128) ? RTLIB::OLE_F128 : RTLIB::OLE_PPCF128;
368 break;
369 case ISD::SETUGE:
370 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 :
371 (VT == MVT::f64) ? RTLIB::OLT_F64 :
372 (VT == MVT::f128) ? RTLIB::OLT_F128 : RTLIB::OLT_PPCF128;
373 break;
374 default: llvm_unreachable("Do not know how to soften this setcc!")::llvm::llvm_unreachable_internal("Do not know how to soften this setcc!"
, "/build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/SelectionDAG/TargetLowering.cpp"
, 374)
;
375 }
376 }
377
378 // Use the target specific return value for comparions lib calls.
379 EVT RetVT = getCmpLibcallReturnType();
380 SDValue Ops[2] = {NewLHS, NewRHS};
381 TargetLowering::MakeLibCallOptions CallOptions;
382 EVT OpsVT[2] = { OldLHS.getValueType(),
383 OldRHS.getValueType() };
384 CallOptions.setTypeListBeforeSoften(OpsVT, RetVT, true);
385 NewLHS = makeLibCall(DAG, LC1, RetVT, Ops, CallOptions, dl).first;
386 NewRHS = DAG.getConstant(0, dl, RetVT);
387
388 CCCode = getCmpLibcallCC(LC1);
389 if (ShouldInvertCC)
390 CCCode = getSetCCInverse(CCCode, /*isInteger=*/true);
391
392 if (LC2 != RTLIB::UNKNOWN_LIBCALL) {
393 SDValue Tmp = DAG.getNode(
394 ISD::SETCC, dl,
395 getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), RetVT),
396 NewLHS, NewRHS, DAG.getCondCode(CCCode));
397 NewLHS = makeLibCall(DAG, LC2, RetVT, Ops, CallOptions, dl).first;
398 NewLHS = DAG.getNode(
399 ISD::SETCC, dl,
400 getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), RetVT),
401 NewLHS, NewRHS, DAG.getCondCode(getCmpLibcallCC(LC2)));
402 NewLHS = DAG.getNode(ISD::OR, dl, Tmp.getValueType(), Tmp, NewLHS);
403 NewRHS = SDValue();
404 }
405}
406
407/// Return the entry encoding for a jump table in the current function. The
408/// returned value is a member of the MachineJumpTableInfo::JTEntryKind enum.
409unsigned TargetLowering::getJumpTableEncoding() const {
410 // In non-pic modes, just use the address of a block.
411 if (!isPositionIndependent())
412 return MachineJumpTableInfo::EK_BlockAddress;
413
414 // In PIC mode, if the target supports a GPRel32 directive, use it.
415 if (getTargetMachine().getMCAsmInfo()->getGPRel32Directive() != nullptr)
416 return MachineJumpTableInfo::EK_GPRel32BlockAddress;
417
418 // Otherwise, use a label difference.
419 return MachineJumpTableInfo::EK_LabelDifference32;
420}
421
422SDValue TargetLowering::getPICJumpTableRelocBase(SDValue Table,
423 SelectionDAG &DAG) const {
424 // If our PIC model is GP relative, use the global offset table as the base.
425 unsigned JTEncoding = getJumpTableEncoding();
426
427 if ((JTEncoding == MachineJumpTableInfo::EK_GPRel64BlockAddress) ||
428 (JTEncoding == MachineJumpTableInfo::EK_GPRel32BlockAddress))
429 return DAG.getGLOBAL_OFFSET_TABLE(getPointerTy(DAG.getDataLayout()));
430
431 return Table;
432}
433
434/// This returns the relocation base for the given PIC jumptable, the same as
435/// getPICJumpTableRelocBase, but as an MCExpr.
436const MCExpr *
437TargetLowering::getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
438 unsigned JTI,MCContext &Ctx) const{
439 // The normal PIC reloc base is the label at the start of the jump table.
440 return MCSymbolRefExpr::create(MF->getJTISymbol(JTI, Ctx), Ctx);
441}
442
443bool
444TargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
445 const TargetMachine &TM = getTargetMachine();
446 const GlobalValue *GV = GA->getGlobal();
447
448 // If the address is not even local to this DSO we will have to load it from
449 // a got and then add the offset.
450 if (!TM.shouldAssumeDSOLocal(*GV->getParent(), GV))
451 return false;
452
453 // If the code is position independent we will have to add a base register.
454 if (isPositionIndependent())
455 return false;
456
457 // Otherwise we can do it.
458 return true;
459}
460
461//===----------------------------------------------------------------------===//
462// Optimization Methods
463//===----------------------------------------------------------------------===//
464
465/// If the specified instruction has a constant integer operand and there are
466/// bits set in that constant that are not demanded, then clear those bits and
467/// return true.
468bool TargetLowering::ShrinkDemandedConstant(SDValue Op, const APInt &Demanded,
469 TargetLoweringOpt &TLO) const {
470 SDLoc DL(Op);
471 unsigned Opcode = Op.getOpcode();
472
473 // Do target-specific constant optimization.
474 if (targetShrinkDemandedConstant(Op, Demanded, TLO))
475 return TLO.New.getNode();
476
477 // FIXME: ISD::SELECT, ISD::SELECT_CC
478 switch (Opcode) {
479 default:
480 break;
481 case ISD::XOR:
482 case ISD::AND:
483 case ISD::OR: {
484 auto *Op1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
485 if (!Op1C)
486 return false;
487
488 // If this is a 'not' op, don't touch it because that's a canonical form.
489 const APInt &C = Op1C->getAPIntValue();
490 if (Opcode == ISD::XOR && Demanded.isSubsetOf(C))
491 return false;
492
493 if (!C.isSubsetOf(Demanded)) {
494 EVT VT = Op.getValueType();
495 SDValue NewC = TLO.DAG.getConstant(Demanded & C, DL, VT);
496 SDValue NewOp = TLO.DAG.getNode(Opcode, DL, VT, Op.getOperand(0), NewC);
497 return TLO.CombineTo(Op, NewOp);
498 }
499
500 break;
501 }
502 }
503
504 return false;
505}
506
507/// Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the casts are free.
508/// This uses isZExtFree and ZERO_EXTEND for the widening cast, but it could be
509/// generalized for targets with other types of implicit widening casts.
510bool TargetLowering::ShrinkDemandedOp(SDValue Op, unsigned BitWidth,
511 const APInt &Demanded,
512 TargetLoweringOpt &TLO) const {
513 assert(Op.getNumOperands() == 2 &&((Op.getNumOperands() == 2 && "ShrinkDemandedOp only supports binary operators!"
) ? static_cast<void> (0) : __assert_fail ("Op.getNumOperands() == 2 && \"ShrinkDemandedOp only supports binary operators!\""
, "/build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/SelectionDAG/TargetLowering.cpp"
, 514, __PRETTY_FUNCTION__))
514 "ShrinkDemandedOp only supports binary operators!")((Op.getNumOperands() == 2 && "ShrinkDemandedOp only supports binary operators!"
) ? static_cast<void> (0) : __assert_fail ("Op.getNumOperands() == 2 && \"ShrinkDemandedOp only supports binary operators!\""
, "/build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/SelectionDAG/TargetLowering.cpp"
, 514, __PRETTY_FUNCTION__))
;
515 assert(Op.getNode()->getNumValues() == 1 &&((Op.getNode()->getNumValues() == 1 && "ShrinkDemandedOp only supports nodes with one result!"
) ? static_cast<void> (0) : __assert_fail ("Op.getNode()->getNumValues() == 1 && \"ShrinkDemandedOp only supports nodes with one result!\""
, "/build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/SelectionDAG/TargetLowering.cpp"
, 516, __PRETTY_FUNCTION__))
516 "ShrinkDemandedOp only supports nodes with one result!")((Op.getNode()->getNumValues() == 1 && "ShrinkDemandedOp only supports nodes with one result!"
) ? static_cast<void> (0) : __assert_fail ("Op.getNode()->getNumValues() == 1 && \"ShrinkDemandedOp only supports nodes with one result!\""
, "/build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/SelectionDAG/TargetLowering.cpp"
, 516, __PRETTY_FUNCTION__))
;
517
518 SelectionDAG &DAG = TLO.DAG;
519 SDLoc dl(Op);
520
521 // Early return, as this function cannot handle vector types.
522 if (Op.getValueType().isVector())
523 return false;
524
525 // Don't do this if the node has another user, which may require the
526 // full value.
527 if (!Op.getNode()->hasOneUse())
528 return false;
529
530 // Search for the smallest integer type with free casts to and from
531 // Op's type. For expedience, just check power-of-2 integer types.
532 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
533 unsigned DemandedSize = Demanded.getActiveBits();
534 unsigned SmallVTBits = DemandedSize;
535 if (!isPowerOf2_32(SmallVTBits))
536 SmallVTBits = NextPowerOf2(SmallVTBits);
537 for (; SmallVTBits < BitWidth; SmallVTBits = NextPowerOf2(SmallVTBits)) {
538 EVT SmallVT = EVT::getIntegerVT(*DAG.getContext(), SmallVTBits);
539 if (TLI.isTruncateFree(Op.getValueType(), SmallVT) &&
540 TLI.isZExtFree(SmallVT, Op.getValueType())) {
541 // We found a type with free casts.
542 SDValue X = DAG.getNode(
543 Op.getOpcode(), dl, SmallVT,
544 DAG.getNode(ISD::TRUNCATE, dl, SmallVT, Op.getOperand(0)),
545 DAG.getNode(ISD::TRUNCATE, dl, SmallVT, Op.getOperand(1)));
546 assert(DemandedSize <= SmallVTBits && "Narrowed below demanded bits?")((DemandedSize <= SmallVTBits && "Narrowed below demanded bits?"
) ? static_cast<void> (0) : __assert_fail ("DemandedSize <= SmallVTBits && \"Narrowed below demanded bits?\""
, "/build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/SelectionDAG/TargetLowering.cpp"
, 546, __PRETTY_FUNCTION__))
;
547 SDValue Z = DAG.getNode(ISD::ANY_EXTEND, dl, Op.getValueType(), X);
548 return TLO.CombineTo(Op, Z);
549 }
550 }
551 return false;
552}
553
554bool TargetLowering::SimplifyDemandedBits(SDValue Op, const APInt &DemandedBits,
555 DAGCombinerInfo &DCI) const {
556 SelectionDAG &DAG = DCI.DAG;
557 TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
558 !DCI.isBeforeLegalizeOps());
559 KnownBits Known;
560
561 bool Simplified = SimplifyDemandedBits(Op, DemandedBits, Known, TLO);
562 if (Simplified) {
563 DCI.AddToWorklist(Op.getNode());
564 DCI.CommitTargetLoweringOpt(TLO);
565 }
566 return Simplified;
567}
568
569bool TargetLowering::SimplifyDemandedBits(SDValue Op, const APInt &DemandedBits,
570 KnownBits &Known,
571 TargetLoweringOpt &TLO,
572 unsigned Depth,
573 bool AssumeSingleUse) const {
574 EVT VT = Op.getValueType();
575 APInt DemandedElts = VT.isVector()
576 ? APInt::getAllOnesValue(VT.getVectorNumElements())
577 : APInt(1, 1);
578 return SimplifyDemandedBits(Op, DemandedBits, DemandedElts, Known, TLO, Depth,
579 AssumeSingleUse);
580}
581
582// TODO: Can we merge SelectionDAG::GetDemandedBits into this?
583// TODO: Under what circumstances can we create nodes? Constant folding?
584SDValue TargetLowering::SimplifyMultipleUseDemandedBits(
585 SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts,
586 SelectionDAG &DAG, unsigned Depth) const {
587 // Limit search depth.
588 if (Depth >= SelectionDAG::MaxRecursionDepth)
589 return SDValue();
590
591 // Ignore UNDEFs.
592 if (Op.isUndef())
593 return SDValue();
594
595 // Not demanding any bits/elts from Op.
596 if (DemandedBits == 0 || DemandedElts == 0)
597 return DAG.getUNDEF(Op.getValueType());
598
599 unsigned NumElts = DemandedElts.getBitWidth();
600 KnownBits LHSKnown, RHSKnown;
601 switch (Op.getOpcode()) {
602 case ISD::BITCAST: {
603 SDValue Src = peekThroughBitcasts(Op.getOperand(0));
604 EVT SrcVT = Src.getValueType();
605 EVT DstVT = Op.getValueType();
606 unsigned NumSrcEltBits = SrcVT.getScalarSizeInBits();
607 unsigned NumDstEltBits = DstVT.getScalarSizeInBits();
608
609 if (NumSrcEltBits == NumDstEltBits)
610 if (SDValue V = SimplifyMultipleUseDemandedBits(
611 Src, DemandedBits, DemandedElts, DAG, Depth + 1))
612 return DAG.getBitcast(DstVT, V);
613
614 // TODO - bigendian once we have test coverage.
615 if (SrcVT.isVector() && (NumDstEltBits % NumSrcEltBits) == 0 &&
616 DAG.getDataLayout().isLittleEndian()) {
617 unsigned Scale = NumDstEltBits / NumSrcEltBits;
618 unsigned NumSrcElts = SrcVT.getVectorNumElements();
619 APInt DemandedSrcBits = APInt::getNullValue(NumSrcEltBits);
620 APInt DemandedSrcElts = APInt::getNullValue(NumSrcElts);
621 for (unsigned i = 0; i != Scale; ++i) {
622 unsigned Offset = i * NumSrcEltBits;
623 APInt Sub = DemandedBits.extractBits(NumSrcEltBits, Offset);
624 if (!Sub.isNullValue()) {
625 DemandedSrcBits |= Sub;
626 for (unsigned j = 0; j != NumElts; ++j)
627 if (DemandedElts[j])
628 DemandedSrcElts.setBit((j * Scale) + i);
629 }
630 }
631
632 if (SDValue V = SimplifyMultipleUseDemandedBits(
633 Src, DemandedSrcBits, DemandedSrcElts, DAG, Depth + 1))
634 return DAG.getBitcast(DstVT, V);
635 }
636
637 // TODO - bigendian once we have test coverage.
638 if ((NumSrcEltBits % NumDstEltBits) == 0 &&
639 DAG.getDataLayout().isLittleEndian()) {
640 unsigned Scale = NumSrcEltBits / NumDstEltBits;
641 unsigned NumSrcElts = SrcVT.isVector() ? SrcVT.getVectorNumElements() : 1;
642 APInt DemandedSrcBits = APInt::getNullValue(NumSrcEltBits);
643 APInt DemandedSrcElts = APInt::getNullValue(NumSrcElts);
644 for (unsigned i = 0; i != NumElts; ++i)
645 if (DemandedElts[i]) {
646 unsigned Offset = (i % Scale) * NumDstEltBits;
647 DemandedSrcBits.insertBits(DemandedBits, Offset);
648 DemandedSrcElts.setBit(i / Scale);
649 }
650
651 if (SDValue V = SimplifyMultipleUseDemandedBits(
652 Src, DemandedSrcBits, DemandedSrcElts, DAG, Depth + 1))
653 return DAG.getBitcast(DstVT, V);
654 }
655
656 break;
657 }
658 case ISD::AND: {
659 LHSKnown = DAG.computeKnownBits(Op.getOperand(0), DemandedElts, Depth + 1);
660 RHSKnown = DAG.computeKnownBits(Op.getOperand(1), DemandedElts, Depth + 1);
661
662 // If all of the demanded bits are known 1 on one side, return the other.
663 // These bits cannot contribute to the result of the 'and' in this
664 // context.
665 if (DemandedBits.isSubsetOf(LHSKnown.Zero | RHSKnown.One))
666 return Op.getOperand(0);
667 if (DemandedBits.isSubsetOf(RHSKnown.Zero | LHSKnown.One))
668 return Op.getOperand(1);
669 break;
670 }
671 case ISD::OR: {
672 LHSKnown = DAG.computeKnownBits(Op.getOperand(0), DemandedElts, Depth + 1);
673 RHSKnown = DAG.computeKnownBits(Op.getOperand(1), DemandedElts, Depth + 1);
674
675 // If all of the demanded bits are known zero on one side, return the
676 // other. These bits cannot contribute to the result of the 'or' in this
677 // context.
678 if (DemandedBits.isSubsetOf(LHSKnown.One | RHSKnown.Zero))
679 return Op.getOperand(0);
680 if (DemandedBits.isSubsetOf(RHSKnown.One | LHSKnown.Zero))
681 return Op.getOperand(1);
682 break;
683 }
684 case ISD::XOR: {
685 LHSKnown = DAG.computeKnownBits(Op.getOperand(0), DemandedElts, Depth + 1);
686 RHSKnown = DAG.computeKnownBits(Op.getOperand(1), DemandedElts, Depth + 1);
687
688 // If all of the demanded bits are known zero on one side, return the
689 // other.
690 if (DemandedBits.isSubsetOf(RHSKnown.Zero))
691 return Op.getOperand(0);
692 if (DemandedBits.isSubsetOf(LHSKnown.Zero))
693 return Op.getOperand(1);
694 break;
695 }
696 case ISD::SIGN_EXTEND_INREG: {
697 // If none of the extended bits are demanded, eliminate the sextinreg.
698 EVT ExVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
699 if (DemandedBits.getActiveBits() <= ExVT.getScalarSizeInBits())
700 return Op.getOperand(0);
701 break;
702 }
703 case ISD::INSERT_VECTOR_ELT: {
704 // If we don't demand the inserted element, return the base vector.
705 SDValue Vec = Op.getOperand(0);
706 auto *CIdx = dyn_cast<ConstantSDNode>(Op.getOperand(2));
707 EVT VecVT = Vec.getValueType();
708 if (CIdx && CIdx->getAPIntValue().ult(VecVT.getVectorNumElements()) &&
709 !DemandedElts[CIdx->getZExtValue()])
710 return Vec;
711 break;
712 }
713 case ISD::VECTOR_SHUFFLE: {
714 ArrayRef<int> ShuffleMask = cast<ShuffleVectorSDNode>(Op)->getMask();
715
716 // If all the demanded elts are from one operand and are inline,
717 // then we can use the operand directly.
718 bool AllUndef = true, IdentityLHS = true, IdentityRHS = true;
719 for (unsigned i = 0; i != NumElts; ++i) {
720 int M = ShuffleMask[i];
721 if (M < 0 || !DemandedElts[i])
722 continue;
723 AllUndef = false;
724 IdentityLHS &= (M == (int)i);
725 IdentityRHS &= ((M - NumElts) == i);
726 }
727
728 if (AllUndef)
729 return DAG.getUNDEF(Op.getValueType());
730 if (IdentityLHS)
731 return Op.getOperand(0);
732 if (IdentityRHS)
733 return Op.getOperand(1);
734 break;
735 }
736 default:
737 if (Op.getOpcode() >= ISD::BUILTIN_OP_END)
738 if (SDValue V = SimplifyMultipleUseDemandedBitsForTargetNode(
739 Op, DemandedBits, DemandedElts, DAG, Depth))
740 return V;
741 break;
742 }
743 return SDValue();
744}
745
746/// Look at Op. At this point, we know that only the OriginalDemandedBits of the
747/// result of Op are ever used downstream. If we can use this information to
748/// simplify Op, create a new simplified DAG node and return true, returning the
749/// original and new nodes in Old and New. Otherwise, analyze the expression and
750/// return a mask of Known bits for the expression (used to simplify the
751/// caller). The Known bits may only be accurate for those bits in the
752/// OriginalDemandedBits and OriginalDemandedElts.
753bool TargetLowering::SimplifyDemandedBits(
754 SDValue Op, const APInt &OriginalDemandedBits,
755 const APInt &OriginalDemandedElts, KnownBits &Known, TargetLoweringOpt &TLO,
756 unsigned Depth, bool AssumeSingleUse) const {
757 unsigned BitWidth = OriginalDemandedBits.getBitWidth();
758 assert(Op.getScalarValueSizeInBits() == BitWidth &&((Op.getScalarValueSizeInBits() == BitWidth && "Mask size mismatches value type size!"
) ? static_cast<void> (0) : __assert_fail ("Op.getScalarValueSizeInBits() == BitWidth && \"Mask size mismatches value type size!\""
, "/build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/SelectionDAG/TargetLowering.cpp"
, 759, __PRETTY_FUNCTION__))
759 "Mask size mismatches value type size!")((Op.getScalarValueSizeInBits() == BitWidth && "Mask size mismatches value type size!"
) ? static_cast<void> (0) : __assert_fail ("Op.getScalarValueSizeInBits() == BitWidth && \"Mask size mismatches value type size!\""
, "/build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/SelectionDAG/TargetLowering.cpp"
, 759, __PRETTY_FUNCTION__))
;
760
761 unsigned NumElts = OriginalDemandedElts.getBitWidth();
762 assert((!Op.getValueType().isVector() ||(((!Op.getValueType().isVector() || NumElts == Op.getValueType
().getVectorNumElements()) && "Unexpected vector size"
) ? static_cast<void> (0) : __assert_fail ("(!Op.getValueType().isVector() || NumElts == Op.getValueType().getVectorNumElements()) && \"Unexpected vector size\""
, "/build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/SelectionDAG/TargetLowering.cpp"
, 764, __PRETTY_FUNCTION__))
763 NumElts == Op.getValueType().getVectorNumElements()) &&(((!Op.getValueType().isVector() || NumElts == Op.getValueType
().getVectorNumElements()) && "Unexpected vector size"
) ? static_cast<void> (0) : __assert_fail ("(!Op.getValueType().isVector() || NumElts == Op.getValueType().getVectorNumElements()) && \"Unexpected vector size\""
, "/build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/SelectionDAG/TargetLowering.cpp"
, 764, __PRETTY_FUNCTION__))
764 "Unexpected vector size")(((!Op.getValueType().isVector() || NumElts == Op.getValueType
().getVectorNumElements()) && "Unexpected vector size"
) ? static_cast<void> (0) : __assert_fail ("(!Op.getValueType().isVector() || NumElts == Op.getValueType().getVectorNumElements()) && \"Unexpected vector size\""
, "/build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/SelectionDAG/TargetLowering.cpp"
, 764, __PRETTY_FUNCTION__))
;
765
766 APInt DemandedBits = OriginalDemandedBits;
767 APInt DemandedElts = OriginalDemandedElts;
768 SDLoc dl(Op);
769 auto &DL = TLO.DAG.getDataLayout();
770
771 // Don't know anything.
772 Known = KnownBits(BitWidth);
773
774 // Undef operand.
775 if (Op.isUndef())
776 return false;
777
778 if (Op.getOpcode() == ISD::Constant) {
779 // We know all of the bits for a constant!
780 Known.One = cast<ConstantSDNode>(Op)->getAPIntValue();
781 Known.Zero = ~Known.One;
782 return false;
783 }
784
785 // Other users may use these bits.
786 EVT VT = Op.getValueType();
787 if (!Op.getNode()->hasOneUse() && !AssumeSingleUse) {
788 if (Depth != 0) {
789 // If not at the root, Just compute the Known bits to
790 // simplify things downstream.
791 Known = TLO.DAG.computeKnownBits(Op, DemandedElts, Depth);
792 return false;
793 }
794 // If this is the root being simplified, allow it to have multiple uses,
795 // just set the DemandedBits/Elts to all bits.
796 DemandedBits = APInt::getAllOnesValue(BitWidth);
797 DemandedElts = APInt::getAllOnesValue(NumElts);
798 } else if (OriginalDemandedBits == 0 || OriginalDemandedElts == 0) {
799 // Not demanding any bits/elts from Op.
800 return TLO.CombineTo(Op, TLO.DAG.getUNDEF(VT));
801 } else if (Depth >= SelectionDAG::MaxRecursionDepth) {
802 // Limit search depth.
803 return false;
804 }
805
806 KnownBits Known2, KnownOut;
807 switch (Op.getOpcode()) {
808 case ISD::TargetConstant:
809 llvm_unreachable("Can't simplify this node")::llvm::llvm_unreachable_internal("Can't simplify this node",
"/build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/SelectionDAG/TargetLowering.cpp"
, 809)
;
810 case ISD::SCALAR_TO_VECTOR: {
811 if (!DemandedElts[0])
812 return TLO.CombineTo(Op, TLO.DAG.getUNDEF(VT));
813
814 KnownBits SrcKnown;
815 SDValue Src = Op.getOperand(0);
816 unsigned SrcBitWidth = Src.getScalarValueSizeInBits();
817 APInt SrcDemandedBits = DemandedBits.zextOrSelf(SrcBitWidth);
818 if (SimplifyDemandedBits(Src, SrcDemandedBits, SrcKnown, TLO, Depth + 1))
819 return true;
820 Known = SrcKnown.zextOrTrunc(BitWidth, false);
821 break;
822 }
823 case ISD::BUILD_VECTOR:
824 // Collect the known bits that are shared by every demanded element.
825 // TODO: Call SimplifyDemandedBits for non-constant demanded elements.
826 Known = TLO.DAG.computeKnownBits(Op, DemandedElts, Depth);
827 return false; // Don't fall through, will infinitely loop.
828 case ISD::LOAD: {
829 LoadSDNode *LD = cast<LoadSDNode>(Op);
830 if (getTargetConstantFromLoad(LD)) {
831 Known = TLO.DAG.computeKnownBits(Op, DemandedElts, Depth);
832 return false; // Don't fall through, will infinitely loop.
833 }
834 break;
835 }
836 case ISD::INSERT_VECTOR_ELT: {
837 SDValue Vec = Op.getOperand(0);
838 SDValue Scl = Op.getOperand(1);
839 auto *CIdx = dyn_cast<ConstantSDNode>(Op.getOperand(2));
840 EVT VecVT = Vec.getValueType();
841
842 // If index isn't constant, assume we need all vector elements AND the
843 // inserted element.
844 APInt DemandedVecElts(DemandedElts);
845 if (CIdx && CIdx->getAPIntValue().ult(VecVT.getVectorNumElements())) {
846 unsigned Idx = CIdx->getZExtValue();
847 DemandedVecElts.clearBit(Idx);
848
849 // Inserted element is not required.
850 if (!DemandedElts[Idx])
851 return TLO.CombineTo(Op, Vec);
852 }
853
854 KnownBits KnownScl;
855 unsigned NumSclBits = Scl.getScalarValueSizeInBits();
856 APInt DemandedSclBits = DemandedBits.zextOrTrunc(NumSclBits);
857 if (SimplifyDemandedBits(Scl, DemandedSclBits, KnownScl, TLO, Depth + 1))
858 return true;
859
860 Known = KnownScl.zextOrTrunc(BitWidth, false);
861
862 KnownBits KnownVec;
863 if (SimplifyDemandedBits(Vec, DemandedBits, DemandedVecElts, KnownVec, TLO,
864 Depth + 1))
865 return true;
866
867 if (!!DemandedVecElts) {
868 Known.One &= KnownVec.One;
869 Known.Zero &= KnownVec.Zero;
870 }
871
872 return false;
873 }
874 case ISD::INSERT_SUBVECTOR: {
875 SDValue Base = Op.getOperand(0);
876 SDValue Sub = Op.getOperand(1);
877 EVT SubVT = Sub.getValueType();
878 unsigned NumSubElts = SubVT.getVectorNumElements();
879
880 // If index isn't constant, assume we need the original demanded base
881 // elements and ALL the inserted subvector elements.
882 APInt BaseElts = DemandedElts;
883 APInt SubElts = APInt::getAllOnesValue(NumSubElts);
884 if (isa<ConstantSDNode>(Op.getOperand(2))) {
885 const APInt &Idx = Op.getConstantOperandAPInt(2);
886 if (Idx.ule(NumElts - NumSubElts)) {
887 unsigned SubIdx = Idx.getZExtValue();
888 SubElts = DemandedElts.extractBits(NumSubElts, SubIdx);
889 BaseElts.insertBits(APInt::getNullValue(NumSubElts), SubIdx);
890 }
891 }
892
893 KnownBits KnownSub, KnownBase;
894 if (SimplifyDemandedBits(Sub, DemandedBits, SubElts, KnownSub, TLO,
895 Depth + 1))
896 return true;
897 if (SimplifyDemandedBits(Base, DemandedBits, BaseElts, KnownBase, TLO,
898 Depth + 1))
899 return true;
900
901 Known.Zero.setAllBits();
902 Known.One.setAllBits();
903 if (!!SubElts) {
904 Known.One &= KnownSub.One;
905 Known.Zero &= KnownSub.Zero;
906 }
907 if (!!BaseElts) {
908 Known.One &= KnownBase.One;
909 Known.Zero &= KnownBase.Zero;
910 }
911 break;
912 }
913 case ISD::EXTRACT_SUBVECTOR: {
914 // If index isn't constant, assume we need all the source vector elements.
915 SDValue Src = Op.getOperand(0);
916 ConstantSDNode *SubIdx = dyn_cast<ConstantSDNode>(Op.getOperand(1));
917 unsigned NumSrcElts = Src.getValueType().getVectorNumElements();
918 APInt SrcElts = APInt::getAllOnesValue(NumSrcElts);
919 if (SubIdx && SubIdx->getAPIntValue().ule(NumSrcElts - NumElts)) {
920 // Offset the demanded elts by the subvector index.
921 uint64_t Idx = SubIdx->getZExtValue();
922 SrcElts = DemandedElts.zextOrSelf(NumSrcElts).shl(Idx);
923 }
924 if (SimplifyDemandedBits(Src, DemandedBits, SrcElts, Known, TLO, Depth + 1))
925 return true;
926 break;
927 }
928 case ISD::CONCAT_VECTORS: {
929 Known.Zero.setAllBits();
930 Known.One.setAllBits();
931 EVT SubVT = Op.getOperand(0).getValueType();
932 unsigned NumSubVecs = Op.getNumOperands();
933 unsigned NumSubElts = SubVT.getVectorNumElements();
934 for (unsigned i = 0; i != NumSubVecs; ++i) {
935 APInt DemandedSubElts =
936 DemandedElts.extractBits(NumSubElts, i * NumSubElts);
937 if (SimplifyDemandedBits(Op.getOperand(i), DemandedBits, DemandedSubElts,
938 Known2, TLO, Depth + 1))
939 return true;
940 // Known bits are shared by every demanded subvector element.
941 if (!!DemandedSubElts) {
942 Known.One &= Known2.One;
943 Known.Zero &= Known2.Zero;
944 }
945 }
946 break;
947 }
948 case ISD::VECTOR_SHUFFLE: {
949 ArrayRef<int> ShuffleMask = cast<ShuffleVectorSDNode>(Op)->getMask();
950
951 // Collect demanded elements from shuffle operands..
952 APInt DemandedLHS(NumElts, 0);
953 APInt DemandedRHS(NumElts, 0);
954 for (unsigned i = 0; i != NumElts; ++i) {
955 if (!DemandedElts[i])
956 continue;
957 int M = ShuffleMask[i];
958 if (M < 0) {
959 // For UNDEF elements, we don't know anything about the common state of
960 // the shuffle result.
961 DemandedLHS.clearAllBits();
962 DemandedRHS.clearAllBits();
963 break;
964 }
965 assert(0 <= M && M < (int)(2 * NumElts) && "Shuffle index out of range")((0 <= M && M < (int)(2 * NumElts) && "Shuffle index out of range"
) ? static_cast<void> (0) : __assert_fail ("0 <= M && M < (int)(2 * NumElts) && \"Shuffle index out of range\""
, "/build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/SelectionDAG/TargetLowering.cpp"
, 965, __PRETTY_FUNCTION__))
;
966 if (M < (int)NumElts)
967 DemandedLHS.setBit(M);
968 else
969 DemandedRHS.setBit(M - NumElts);
970 }
971
972 if (!!DemandedLHS || !!DemandedRHS) {
973 SDValue Op0 = Op.getOperand(0);
974 SDValue Op1 = Op.getOperand(1);
975
976 Known.Zero.setAllBits();
977 Known.One.setAllBits();
978 if (!!DemandedLHS) {
979 if (SimplifyDemandedBits(Op0, DemandedBits, DemandedLHS, Known2, TLO,
980 Depth + 1))
981 return true;
982 Known.One &= Known2.One;
983 Known.Zero &= Known2.Zero;
984 }
985 if (!!DemandedRHS) {
986 if (SimplifyDemandedBits(Op1, DemandedBits, DemandedRHS, Known2, TLO,
987 Depth + 1))
988 return true;
989 Known.One &= Known2.One;
990 Known.Zero &= Known2.Zero;
991 }
992
993 // Attempt to avoid multi-use ops if we don't need anything from them.
994 SDValue DemandedOp0 = SimplifyMultipleUseDemandedBits(
995 Op0, DemandedBits, DemandedLHS, TLO.DAG, Depth + 1);
996 SDValue DemandedOp1 = SimplifyMultipleUseDemandedBits(
997 Op1, DemandedBits, DemandedRHS, TLO.DAG, Depth + 1);
998 if (DemandedOp0 || DemandedOp1) {
999 Op0 = DemandedOp0 ? DemandedOp0 : Op0;
1000 Op1 = DemandedOp1 ? DemandedOp1 : Op1;
1001 SDValue NewOp = TLO.DAG.getVectorShuffle(VT, dl, Op0, Op1, ShuffleMask);
1002 return TLO.CombineTo(Op, NewOp);
1003 }
1004 }
1005 break;
1006 }
1007 case ISD::AND: {
1008 SDValue Op0 = Op.getOperand(0);
1009 SDValue Op1 = Op.getOperand(1);
1010
1011 // If the RHS is a constant, check to see if the LHS would be zero without
1012 // using the bits from the RHS. Below, we use knowledge about the RHS to
1013 // simplify the LHS, here we're using information from the LHS to simplify
1014 // the RHS.
1015 if (ConstantSDNode *RHSC = isConstOrConstSplat(Op1)) {
1016 // Do not increment Depth here; that can cause an infinite loop.
1017 KnownBits LHSKnown = TLO.DAG.computeKnownBits(Op0, DemandedElts, Depth);
1018 // If the LHS already has zeros where RHSC does, this 'and' is dead.
1019 if ((LHSKnown.Zero & DemandedBits) ==
1020 (~RHSC->getAPIntValue() & DemandedBits))
1021 return TLO.CombineTo(Op, Op0);
1022
1023 // If any of the set bits in the RHS are known zero on the LHS, shrink
1024 // the constant.
1025 if (ShrinkDemandedConstant(Op, ~LHSKnown.Zero & DemandedBits, TLO))
1026 return true;
1027
1028 // Bitwise-not (xor X, -1) is a special case: we don't usually shrink its
1029 // constant, but if this 'and' is only clearing bits that were just set by
1030 // the xor, then this 'and' can be eliminated by shrinking the mask of
1031 // the xor. For example, for a 32-bit X:
1032 // and (xor (srl X, 31), -1), 1 --> xor (srl X, 31), 1
1033 if (isBitwiseNot(Op0) && Op0.hasOneUse() &&
1034 LHSKnown.One == ~RHSC->getAPIntValue()) {
1035 SDValue Xor = TLO.DAG.getNode(ISD::XOR, dl, VT, Op0.getOperand(0), Op1);
1036 return TLO.CombineTo(Op, Xor);
1037 }
1038 }
1039
1040 if (SimplifyDemandedBits(Op1, DemandedBits, DemandedElts, Known, TLO,
1041 Depth + 1))
1042 return true;
1043 assert(!Known.hasConflict() && "Bits known to be one AND zero?")((!Known.hasConflict() && "Bits known to be one AND zero?"
) ? static_cast<void> (0) : __assert_fail ("!Known.hasConflict() && \"Bits known to be one AND zero?\""
, "/build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/SelectionDAG/TargetLowering.cpp"
, 1043, __PRETTY_FUNCTION__))
;
1044 if (SimplifyDemandedBits(Op0, ~Known.Zero & DemandedBits, DemandedElts,
1045 Known2, TLO, Depth + 1))
1046 return true;
1047 assert(!Known2.hasConflict() && "Bits known to be one AND zero?")((!Known2.hasConflict() && "Bits known to be one AND zero?"
) ? static_cast<void> (0) : __assert_fail ("!Known2.hasConflict() && \"Bits known to be one AND zero?\""
, "/build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/SelectionDAG/TargetLowering.cpp"
, 1047, __PRETTY_FUNCTION__))
;
1048
1049 // Attempt to avoid multi-use ops if we don't need anything from them.
1050 if (!DemandedBits.isAllOnesValue() || !DemandedElts.isAllOnesValue()) {
1051 SDValue DemandedOp0 = SimplifyMultipleUseDemandedBits(
1052 Op0, DemandedBits, DemandedElts, TLO.DAG, Depth + 1);
1053 SDValue DemandedOp1 = SimplifyMultipleUseDemandedBits(
1054 Op1, DemandedBits, DemandedElts, TLO.DAG, Depth + 1);
1055 if (DemandedOp0 || DemandedOp1) {
1056 Op0 = DemandedOp0 ? DemandedOp0 : Op0;
1057 Op1 = DemandedOp1 ? DemandedOp1 : Op1;
1058 SDValue NewOp = TLO.DAG.getNode(Op.getOpcode(), dl, VT, Op0, Op1);
1059 return TLO.CombineTo(Op, NewOp);
1060 }
1061 }
1062
1063 // If all of the demanded bits are known one on one side, return the other.
1064 // These bits cannot contribute to the result of the 'and'.
1065 if (DemandedBits.isSubsetOf(Known2.Zero | Known.One))
1066 return TLO.CombineTo(Op, Op0);
1067 if (DemandedBits.isSubsetOf(Known.Zero | Known2.One))
1068 return TLO.CombineTo(Op, Op1);
1069 // If all of the demanded bits in the inputs are known zeros, return zero.
1070 if (DemandedBits.isSubsetOf(Known.Zero | Known2.Zero))
1071 return TLO.CombineTo(Op, TLO.DAG.getConstant(0, dl, VT));
1072 // If the RHS is a constant, see if we can simplify it.
1073 if (ShrinkDemandedConstant(Op, ~Known2.Zero & DemandedBits, TLO))
1074 return true;
1075 // If the operation can be done in a smaller type, do so.
1076 if (ShrinkDemandedOp(Op, BitWidth, DemandedBits, TLO))
1077 return true;
1078
1079 // Output known-1 bits are only known if set in both the LHS & RHS.
1080 Known.One &= Known2.One;
1081 // Output known-0 are known to be clear if zero in either the LHS | RHS.
1082 Known.Zero |= Known2.Zero;
1083 break;
1084 }
1085 case ISD::OR: {
1086 SDValue Op0 = Op.getOperand(0);
1087 SDValue Op1 = Op.getOperand(1);
1088
1089 if (SimplifyDemandedBits(Op1, DemandedBits, DemandedElts, Known, TLO,
1090 Depth + 1))
1091 return true;
1092 assert(!Known.hasConflict() && "Bits known to be one AND zero?")((!Known.hasConflict() && "Bits known to be one AND zero?"
) ? static_cast<void> (0) : __assert_fail ("!Known.hasConflict() && \"Bits known to be one AND zero?\""
, "/build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/SelectionDAG/TargetLowering.cpp"
, 1092, __PRETTY_FUNCTION__))
;
1093 if (SimplifyDemandedBits(Op0, ~Known.One & DemandedBits, DemandedElts,
1094 Known2, TLO, Depth + 1))
1095 return true;
1096 assert(!Known2.hasConflict() && "Bits known to be one AND zero?")((!Known2.hasConflict() && "Bits known to be one AND zero?"
) ? static_cast<void> (0) : __assert_fail ("!Known2.hasConflict() && \"Bits known to be one AND zero?\""
, "/build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/SelectionDAG/TargetLowering.cpp"
, 1096, __PRETTY_FUNCTION__))
;
1097
1098 // Attempt to avoid multi-use ops if we don't need anything from them.
1099 if (!DemandedBits.isAllOnesValue() || !DemandedElts.isAllOnesValue()) {
1100 SDValue DemandedOp0 = SimplifyMultipleUseDemandedBits(
1101 Op0, DemandedBits, DemandedElts, TLO.DAG, Depth + 1);
1102 SDValue DemandedOp1 = SimplifyMultipleUseDemandedBits(
1103 Op1, DemandedBits, DemandedElts, TLO.DAG, Depth + 1);
1104 if (DemandedOp0 || DemandedOp1) {
1105 Op0 = DemandedOp0 ? DemandedOp0 : Op0;
1106 Op1 = DemandedOp1 ? DemandedOp1 : Op1;
1107 SDValue NewOp = TLO.DAG.getNode(Op.getOpcode(), dl, VT, Op0, Op1);
1108 return TLO.CombineTo(Op, NewOp);
1109 }
1110 }
1111
1112 // If all of the demanded bits are known zero on one side, return the other.
1113 // These bits cannot contribute to the result of the 'or'.
1114 if (DemandedBits.isSubsetOf(Known2.One | Known.Zero))
1115 return TLO.CombineTo(Op, Op0);
1116 if (DemandedBits.isSubsetOf(Known.One | Known2.Zero))
1117 return TLO.CombineTo(Op, Op1);
1118 // If the RHS is a constant, see if we can simplify it.
1119 if (ShrinkDemandedConstant(Op, DemandedBits, TLO))
1120 return true;
1121 // If the operation can be done in a smaller type, do so.
1122 if (ShrinkDemandedOp(Op, BitWidth, DemandedBits, TLO))
1123 return true;
1124
1125 // Output known-0 bits are only known if clear in both the LHS & RHS.
1126 Known.Zero &= Known2.Zero;
1127 // Output known-1 are known to be set if set in either the LHS | RHS.
1128 Known.One |= Known2.One;
1129 break;
1130 }
1131 case ISD::XOR: {
1132 SDValue Op0 = Op.getOperand(0);
1133 SDValue Op1 = Op.getOperand(1);
1134
1135 if (SimplifyDemandedBits(Op1, DemandedBits, DemandedElts, Known, TLO,
1136 Depth + 1))
1137 return true;
1138 assert(!Known.hasConflict() && "Bits known to be one AND zero?")((!Known.hasConflict() && "Bits known to be one AND zero?"
) ? static_cast<void> (0) : __assert_fail ("!Known.hasConflict() && \"Bits known to be one AND zero?\""
, "/build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/SelectionDAG/TargetLowering.cpp"
, 1138, __PRETTY_FUNCTION__))
;
1139 if (SimplifyDemandedBits(Op0, DemandedBits, DemandedElts, Known2, TLO,
1140 Depth + 1))
1141 return true;
1142 assert(!Known2.hasConflict() && "Bits known to be one AND zero?")((!Known2.hasConflict() && "Bits known to be one AND zero?"
) ? static_cast<void> (0) : __assert_fail ("!Known2.hasConflict() && \"Bits known to be one AND zero?\""
, "/build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/SelectionDAG/TargetLowering.cpp"
, 1142, __PRETTY_FUNCTION__))
;
1143
1144 // Attempt to avoid multi-use ops if we don't need anything from them.
1145 if (!DemandedBits.isAllOnesValue() || !DemandedElts.isAllOnesValue()) {
1146 SDValue DemandedOp0 = SimplifyMultipleUseDemandedBits(
1147 Op0, DemandedBits, DemandedElts, TLO.DAG, Depth + 1);
1148 SDValue DemandedOp1 = SimplifyMultipleUseDemandedBits(
1149 Op1, DemandedBits, DemandedElts, TLO.DAG, Depth + 1);
1150 if (DemandedOp0 || DemandedOp1) {
1151 Op0 = DemandedOp0 ? DemandedOp0 : Op0;
1152 Op1 = DemandedOp1 ? DemandedOp1 : Op1;
1153 SDValue NewOp = TLO.DAG.getNode(Op.getOpcode(), dl, VT, Op0, Op1);
1154 return TLO.CombineTo(Op, NewOp);
1155 }
1156 }
1157
1158 // If all of the demanded bits are known zero on one side, return the other.
1159 // These bits cannot contribute to the result of the 'xor'.
1160 if (DemandedBits.isSubsetOf(Known.Zero))
1161 return TLO.CombineTo(Op, Op0);
1162 if (DemandedBits.isSubsetOf(Known2.Zero))
1163 return TLO.CombineTo(Op, Op1);
1164 // If the operation can be done in a smaller type, do so.
1165 if (ShrinkDemandedOp(Op, BitWidth, DemandedBits, TLO))
1166 return true;
1167
1168 // If all of the unknown bits are known to be zero on one side or the other
1169 // (but not both) turn this into an *inclusive* or.
1170 // e.g. (A & C1)^(B & C2) -> (A & C1)|(B & C2) iff C1&C2 == 0
1171 if (DemandedBits.isSubsetOf(Known.Zero | Known2.Zero))
1172 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::OR, dl, VT, Op0, Op1));
1173
1174 // Output known-0 bits are known if clear or set in both the LHS & RHS.
1175 KnownOut.Zero = (Known.Zero & Known2.Zero) | (Known.One & Known2.One);
1176 // Output known-1 are known to be set if set in only one of the LHS, RHS.
1177 KnownOut.One = (Known.Zero & Known2.One) | (Known.One & Known2.Zero);
1178
1179 if (ConstantSDNode *C = isConstOrConstSplat(Op1)) {
1180 // If one side is a constant, and all of the known set bits on the other
1181 // side are also set in the constant, turn this into an AND, as we know
1182 // the bits will be cleared.
1183 // e.g. (X | C1) ^ C2 --> (X | C1) & ~C2 iff (C1&C2) == C2
1184 // NB: it is okay if more bits are known than are requested
1185 if (C->getAPIntValue() == Known2.One) {
1186 SDValue ANDC =
1187 TLO.DAG.getConstant(~C->getAPIntValue() & DemandedBits, dl, VT);
1188 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::AND, dl, VT, Op0, ANDC));
1189 }
1190
1191 // If the RHS is a constant, see if we can change it. Don't alter a -1
1192 // constant because that's a 'not' op, and that is better for combining
1193 // and codegen.
1194 if (!C->isAllOnesValue()) {
1195 if (DemandedBits.isSubsetOf(C->getAPIntValue())) {
1196 // We're flipping all demanded bits. Flip the undemanded bits too.
1197 SDValue New = TLO.DAG.getNOT(dl, Op0, VT);
1198 return TLO.CombineTo(Op, New);
1199 }
1200 // If we can't turn this into a 'not', try to shrink the constant.
1201 if (ShrinkDemandedConstant(Op, DemandedBits, TLO))
1202 return true;
1203 }
1204 }
1205
1206 Known = std::move(KnownOut);
1207 break;
1208 }
1209 case ISD::SELECT:
1210 if (SimplifyDemandedBits(Op.getOperand(2), DemandedBits, Known, TLO,
1211 Depth + 1))
1212 return true;
1213 if (SimplifyDemandedBits(Op.getOperand(1), DemandedBits, Known2, TLO,
1214 Depth + 1))
1215 return true;
1216 assert(!Known.hasConflict() && "Bits known to be one AND zero?")((!Known.hasConflict() && "Bits known to be one AND zero?"
) ? static_cast<void> (0) : __assert_fail ("!Known.hasConflict() && \"Bits known to be one AND zero?\""
, "/build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/SelectionDAG/TargetLowering.cpp"
, 1216, __PRETTY_FUNCTION__))
;
1217 assert(!Known2.hasConflict() && "Bits known to be one AND zero?")((!Known2.hasConflict() && "Bits known to be one AND zero?"
) ? static_cast<void> (0) : __assert_fail ("!Known2.hasConflict() && \"Bits known to be one AND zero?\""
, "/build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/SelectionDAG/TargetLowering.cpp"
, 1217, __PRETTY_FUNCTION__))
;
1218
1219 // If the operands are constants, see if we can simplify them.
1220 if (ShrinkDemandedConstant(Op, DemandedBits, TLO))
1221 return true;
1222
1223 // Only known if known in both the LHS and RHS.
1224 Known.One &= Known2.One;
1225 Known.Zero &= Known2.Zero;
1226 break;
1227 case ISD::SELECT_CC:
1228 if (SimplifyDemandedBits(Op.getOperand(3), DemandedBits, Known, TLO,
1229 Depth + 1))
1230 return true;
1231 if (SimplifyDemandedBits(Op.getOperand(2), DemandedBits, Known2, TLO,
1232 Depth + 1))
1233 return true;
1234 assert(!Known.hasConflict() && "Bits known to be one AND zero?")((!Known.hasConflict() && "Bits known to be one AND zero?"
) ? static_cast<void> (0) : __assert_fail ("!Known.hasConflict() && \"Bits known to be one AND zero?\""
, "/build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/SelectionDAG/TargetLowering.cpp"
, 1234, __PRETTY_FUNCTION__))
;
1235 assert(!Known2.hasConflict() && "Bits known to be one AND zero?")((!Known2.hasConflict() && "Bits known to be one AND zero?"
) ? static_cast<void> (0) : __assert_fail ("!Known2.hasConflict() && \"Bits known to be one AND zero?\""
, "/build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/SelectionDAG/TargetLowering.cpp"
, 1235, __PRETTY_FUNCTION__))
;
1236
1237 // If the operands are constants, see if we can simplify them.
1238 if (ShrinkDemandedConstant(Op, DemandedBits, TLO))
1239 return true;
1240
1241 // Only known if known in both the LHS and RHS.
1242 Known.One &= Known2.One;
1243 Known.Zero &= Known2.Zero;
1244 break;
1245 case ISD::SETCC: {
1246 SDValue Op0 = Op.getOperand(0);
1247 SDValue Op1 = Op.getOperand(1);
1248 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
1249 // If (1) we only need the sign-bit, (2) the setcc operands are the same
1250 // width as the setcc result, and (3) the result of a setcc conforms to 0 or
1251 // -1, we may be able to bypass the setcc.
1252 if (DemandedBits.isSignMask() &&
1253 Op0.getScalarValueSizeInBits() == BitWidth &&
1254 getBooleanContents(VT) ==
1255 BooleanContent::ZeroOrNegativeOneBooleanContent) {
1256 // If we're testing X < 0, then this compare isn't needed - just use X!
1257 // FIXME: We're limiting to integer types here, but this should also work
1258 // if we don't care about FP signed-zero. The use of SETLT with FP means
1259 // that we don't care about NaNs.
1260 if (CC == ISD::SETLT && Op1.getValueType().isInteger() &&
1261 (isNullConstant(Op1) || ISD::isBuildVectorAllZeros(Op1.getNode())))
1262 return TLO.CombineTo(Op, Op0);
1263
1264 // TODO: Should we check for other forms of sign-bit comparisons?
1265 // Examples: X <= -1, X >= 0
1266 }
1267 if (getBooleanContents(Op0.getValueType()) ==
1268 TargetLowering::ZeroOrOneBooleanContent &&
1269 BitWidth > 1)
1270 Known.Zero.setBitsFrom(1);
1271 break;
1272 }
1273 case ISD::SHL: {
1274 SDValue Op0 = Op.getOperand(0);
1275 SDValue Op1 = Op.getOperand(1);
1276
1277 if (ConstantSDNode *SA = isConstOrConstSplat(Op1, DemandedElts)) {
1278 // If the shift count is an invalid immediate, don't do anything.
1279 if (SA->getAPIntValue().uge(BitWidth))
1280 break;
1281
1282 unsigned ShAmt = SA->getZExtValue();
1283 if (ShAmt == 0)
1284 return TLO.CombineTo(Op, Op0);
1285
1286 // If this is ((X >>u C1) << ShAmt), see if we can simplify this into a
1287 // single shift. We can do this if the bottom bits (which are shifted
1288 // out) are never demanded.
1289 // TODO - support non-uniform vector amounts.
1290 if (Op0.getOpcode() == ISD::SRL) {
1291 if (!DemandedBits.intersects(APInt::getLowBitsSet(BitWidth, ShAmt))) {
1292 if (ConstantSDNode *SA2 =
1293 isConstOrConstSplat(Op0.getOperand(1), DemandedElts)) {
1294 if (SA2->getAPIntValue().ult(BitWidth)) {
1295 unsigned C1 = SA2->getZExtValue();
1296 unsigned Opc = ISD::SHL;
1297 int Diff = ShAmt - C1;
1298 if (Diff < 0) {
1299 Diff = -Diff;
1300 Opc = ISD::SRL;
1301 }
1302
1303 SDValue NewSA = TLO.DAG.getConstant(Diff, dl, Op1.getValueType());
1304 return TLO.CombineTo(
1305 Op, TLO.DAG.getNode(Opc, dl, VT, Op0.getOperand(0), NewSA));
1306 }
1307 }
1308 }
1309 }
1310
1311 if (SimplifyDemandedBits(Op0, DemandedBits.lshr(ShAmt), DemandedElts,
1312 Known, TLO, Depth + 1))
1313 return true;
1314
1315 // Try shrinking the operation as long as the shift amount will still be
1316 // in range.
1317 if ((ShAmt < DemandedBits.getActiveBits()) &&
1318 ShrinkDemandedOp(Op, BitWidth, DemandedBits, TLO))
1319 return true;
1320
1321 // Convert (shl (anyext x, c)) to (anyext (shl x, c)) if the high bits
1322 // are not demanded. This will likely allow the anyext to be folded away.
1323 if (Op0.getOpcode() == ISD::ANY_EXTEND) {
1324 SDValue InnerOp = Op0.getOperand(0);
1325 EVT InnerVT = InnerOp.getValueType();
1326 unsigned InnerBits = InnerVT.getScalarSizeInBits();
1327 if (ShAmt < InnerBits && DemandedBits.getActiveBits() <= InnerBits &&
1328 isTypeDesirableForOp(ISD::SHL, InnerVT)) {
1329 EVT ShTy = getShiftAmountTy(InnerVT, DL);
1330 if (!APInt(BitWidth, ShAmt).isIntN(ShTy.getSizeInBits()))
1331 ShTy = InnerVT;
1332 SDValue NarrowShl =
1333 TLO.DAG.getNode(ISD::SHL, dl, InnerVT, InnerOp,
1334 TLO.DAG.getConstant(ShAmt, dl, ShTy));
1335 return TLO.CombineTo(
1336 Op, TLO.DAG.getNode(ISD::ANY_EXTEND, dl, VT, NarrowShl));
1337 }
1338 // Repeat the SHL optimization above in cases where an extension
1339 // intervenes: (shl (anyext (shr x, c1)), c2) to
1340 // (shl (anyext x), c2-c1). This requires that the bottom c1 bits
1341 // aren't demanded (as above) and that the shifted upper c1 bits of
1342 // x aren't demanded.
1343 if (Op0.hasOneUse() && InnerOp.getOpcode() == ISD::SRL &&
1344 InnerOp.hasOneUse()) {
1345 if (ConstantSDNode *SA2 =
1346 isConstOrConstSplat(InnerOp.getOperand(1))) {
1347 unsigned InnerShAmt = SA2->getLimitedValue(InnerBits);
1348 if (InnerShAmt < ShAmt && InnerShAmt < InnerBits &&
1349 DemandedBits.getActiveBits() <=
1350 (InnerBits - InnerShAmt + ShAmt) &&
1351 DemandedBits.countTrailingZeros() >= ShAmt) {
1352 SDValue NewSA = TLO.DAG.getConstant(ShAmt - InnerShAmt, dl,
1353 Op1.getValueType());
1354 SDValue NewExt = TLO.DAG.getNode(ISD::ANY_EXTEND, dl, VT,
1355 InnerOp.getOperand(0));
1356 return TLO.CombineTo(
1357 Op, TLO.DAG.getNode(ISD::SHL, dl, VT, NewExt, NewSA));
1358 }
1359 }
1360 }
1361 }
1362
1363 Known.Zero <<= ShAmt;
1364 Known.One <<= ShAmt;
1365 // low bits known zero.
1366 Known.Zero.setLowBits(ShAmt);
1367 }
1368 break;
1369 }
1370 case ISD::SRL: {
1371 SDValue Op0 = Op.getOperand(0);
1372 SDValue Op1 = Op.getOperand(1);
1373
1374 if (ConstantSDNode *SA = isConstOrConstSplat(Op1, DemandedElts)) {
1375 // If the shift count is an invalid immediate, don't do anything.
1376 if (SA->getAPIntValue().uge(BitWidth))
1377 break;
1378
1379 unsigned ShAmt = SA->getZExtValue();
1380 if (ShAmt == 0)
1381 return TLO.CombineTo(Op, Op0);
1382
1383 EVT ShiftVT = Op1.getValueType();
1384 APInt InDemandedMask = (DemandedBits << ShAmt);
1385
1386 // If the shift is exact, then it does demand the low bits (and knows that
1387 // they are zero).
1388 if (Op->getFlags().hasExact())
1389 InDemandedMask.setLowBits(ShAmt);
1390
1391 // If this is ((X << C1) >>u ShAmt), see if we can simplify this into a
1392 // single shift. We can do this if the top bits (which are shifted out)
1393 // are never demanded.
1394 // TODO - support non-uniform vector amounts.
1395 if (Op0.getOpcode() == ISD::SHL) {
1396 if (ConstantSDNode *SA2 =
1397 isConstOrConstSplat(Op0.getOperand(1), DemandedElts)) {
1398 if (!DemandedBits.intersects(
1399 APInt::getHighBitsSet(BitWidth, ShAmt))) {
1400 if (SA2->getAPIntValue().ult(BitWidth)) {
1401 unsigned C1 = SA2->getZExtValue();
1402 unsigned Opc = ISD::SRL;
1403 int Diff = ShAmt - C1;
1404 if (Diff < 0) {
1405 Diff = -Diff;
1406 Opc = ISD::SHL;
1407 }
1408
1409 SDValue NewSA = TLO.DAG.getConstant(Diff, dl, ShiftVT);
1410 return TLO.CombineTo(
1411 Op, TLO.DAG.getNode(Opc, dl, VT, Op0.getOperand(0), NewSA));
1412 }
1413 }
1414 }
1415 }
1416
1417 // Compute the new bits that are at the top now.
1418 if (SimplifyDemandedBits(Op0, InDemandedMask, DemandedElts, Known, TLO,
1419 Depth + 1))
1420 return true;
1421 assert(!Known.hasConflict() && "Bits known to be one AND zero?")((!Known.hasConflict() && "Bits known to be one AND zero?"
) ? static_cast<void> (0) : __assert_fail ("!Known.hasConflict() && \"Bits known to be one AND zero?\""
, "/build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/SelectionDAG/TargetLowering.cpp"
, 1421, __PRETTY_FUNCTION__))
;
1422 Known.Zero.lshrInPlace(ShAmt);
1423 Known.One.lshrInPlace(ShAmt);
1424
1425 Known.Zero.setHighBits(ShAmt); // High bits known zero.
1426 }
1427 break;
1428 }
1429 case ISD::SRA: {
1430 SDValue Op0 = Op.getOperand(0);
1431 SDValue Op1 = Op.getOperand(1);
1432
1433 // If this is an arithmetic shift right and only the low-bit is set, we can
1434 // always convert this into a logical shr, even if the shift amount is
1435 // variable. The low bit of the shift cannot be an input sign bit unless
1436 // the shift amount is >= the size of the datatype, which is undefined.
1437 if (DemandedBits.isOneValue())
1438 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT, Op0, Op1));
1439
1440 if (ConstantSDNode *SA = isConstOrConstSplat(Op1, DemandedElts)) {
1441 // If the shift count is an invalid immediate, don't do anything.
1442 if (SA->getAPIntValue().uge(BitWidth))
1443 break;
1444
1445 unsigned ShAmt = SA->getZExtValue();
1446 if (ShAmt == 0)
1447 return TLO.CombineTo(Op, Op0);
1448
1449 APInt InDemandedMask = (DemandedBits << ShAmt);
1450
1451 // If the shift is exact, then it does demand the low bits (and knows that
1452 // they are zero).
1453 if (Op->getFlags().hasExact())
1454 InDemandedMask.setLowBits(ShAmt);
1455
1456 // If any of the demanded bits are produced by the sign extension, we also
1457 // demand the input sign bit.
1458 if (DemandedBits.countLeadingZeros() < ShAmt)
1459 InDemandedMask.setSignBit();
1460
1461 if (SimplifyDemandedBits(Op0, InDemandedMask, DemandedElts, Known, TLO,
1462 Depth + 1))
1463 return true;
1464 assert(!Known.hasConflict() && "Bits known to be one AND zero?")((!Known.hasConflict() && "Bits known to be one AND zero?"
) ? static_cast<void> (0) : __assert_fail ("!Known.hasConflict() && \"Bits known to be one AND zero?\""
, "/build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/SelectionDAG/TargetLowering.cpp"
, 1464, __PRETTY_FUNCTION__))
;
1465 Known.Zero.lshrInPlace(ShAmt);
1466 Known.One.lshrInPlace(ShAmt);
1467
1468 // If the input sign bit is known to be zero, or if none of the top bits
1469 // are demanded, turn this into an unsigned shift right.
1470 if (Known.Zero[BitWidth - ShAmt - 1] ||
1471 DemandedBits.countLeadingZeros() >= ShAmt) {
1472 SDNodeFlags Flags;
1473 Flags.setExact(Op->getFlags().hasExact());
1474 return TLO.CombineTo(
1475 Op, TLO.DAG.getNode(ISD::SRL, dl, VT, Op0, Op1, Flags));
1476 }
1477
1478 int Log2 = DemandedBits.exactLogBase2();
1479 if (Log2 >= 0) {
1480 // The bit must come from the sign.
1481 SDValue NewSA =
1482 TLO.DAG.getConstant(BitWidth - 1 - Log2, dl, Op1.getValueType());
1483 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT, Op0, NewSA));
1484 }
1485
1486 if (Known.One[BitWidth - ShAmt - 1])
1487 // New bits are known one.
1488 Known.One.setHighBits(ShAmt);
1489 }
1490 break;
1491 }
1492 case ISD::FSHL:
1493 case ISD::FSHR: {
1494 SDValue Op0 = Op.getOperand(0);
1495 SDValue Op1 = Op.getOperand(1);
1496 SDValue Op2 = Op.getOperand(2);
1497 bool IsFSHL = (Op.getOpcode() == ISD::FSHL);
1498
1499 if (ConstantSDNode *SA = isConstOrConstSplat(Op2, DemandedElts)) {
1500 unsigned Amt = SA->getAPIntValue().urem(BitWidth);
1501
1502 // For fshl, 0-shift returns the 1st arg.
1503 // For fshr, 0-shift returns the 2nd arg.
1504 if (Amt == 0) {
1505 if (SimplifyDemandedBits(IsFSHL ? Op0 : Op1, DemandedBits, DemandedElts,
1506 Known, TLO, Depth + 1))
1507 return true;
1508 break;
1509 }
1510
1511 // fshl: (Op0 << Amt) | (Op1 >> (BW - Amt))
1512 // fshr: (Op0 << (BW - Amt)) | (Op1 >> Amt)
1513 APInt Demanded0 = DemandedBits.lshr(IsFSHL ? Amt : (BitWidth - Amt));
1514 APInt Demanded1 = DemandedBits << (IsFSHL ? (BitWidth - Amt) : Amt);
1515 if (SimplifyDemandedBits(Op0, Demanded0, DemandedElts, Known2, TLO,
1516 Depth + 1))
1517 return true;
1518 if (SimplifyDemandedBits(Op1, Demanded1, DemandedElts, Known, TLO,
1519 Depth + 1))
1520 return true;
1521
1522 Known2.One <<= (IsFSHL ? Amt : (BitWidth - Amt));
1523 Known2.Zero <<= (IsFSHL ? Amt : (BitWidth - Amt));
1524 Known.One.lshrInPlace(IsFSHL ? (BitWidth - Amt) : Amt);
1525 Known.Zero.lshrInPlace(IsFSHL ? (BitWidth - Amt) : Amt);
1526 Known.One |= Known2.One;
1527 Known.Zero |= Known2.Zero;
1528 }
1529 break;
1530 }
1531 case ISD::BITREVERSE: {
1532 SDValue Src = Op.getOperand(0);
1533 APInt DemandedSrcBits = DemandedBits.reverseBits();
1534 if (SimplifyDemandedBits(Src, DemandedSrcBits, DemandedElts, Known2, TLO,
1535 Depth + 1))
1536 return true;
1537 Known.One = Known2.One.reverseBits();
1538 Known.Zero = Known2.Zero.reverseBits();
1539 break;
1540 }
1541 case ISD::SIGN_EXTEND_INREG: {
1542 SDValue Op0 = Op.getOperand(0);
1543 EVT ExVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
1544 unsigned ExVTBits = ExVT.getScalarSizeInBits();
1545
1546 // If we only care about the highest bit, don't bother shifting right.
1547 if (DemandedBits.isSignMask()) {
1548 unsigned NumSignBits = TLO.DAG.ComputeNumSignBits(Op0);
1549 bool AlreadySignExtended = NumSignBits >= BitWidth - ExVTBits + 1;
1550 // However if the input is already sign extended we expect the sign
1551 // extension to be dropped altogether later and do not simplify.
1552 if (!AlreadySignExtended) {
1553 // Compute the correct shift amount type, which must be getShiftAmountTy
1554 // for scalar types after legalization.
1555 EVT ShiftAmtTy = VT;
1556 if (TLO.LegalTypes() && !ShiftAmtTy.isVector())
1557 ShiftAmtTy = getShiftAmountTy(ShiftAmtTy, DL);
1558
1559 SDValue ShiftAmt =
1560 TLO.DAG.getConstant(BitWidth - ExVTBits, dl, ShiftAmtTy);
1561 return TLO.CombineTo(Op,
1562 TLO.DAG.getNode(ISD::SHL, dl, VT, Op0, ShiftAmt));
1563 }
1564 }
1565
1566 // If none of the extended bits are demanded, eliminate the sextinreg.
1567 if (DemandedBits.getActiveBits() <= ExVTBits)
1568 return TLO.CombineTo(Op, Op0);
1569
1570 APInt InputDemandedBits = DemandedBits.getLoBits(ExVTBits);
1571
1572 // Since the sign extended bits are demanded, we know that the sign
1573 // bit is demanded.
1574 InputDemandedBits.setBit(ExVTBits - 1);
1575
1576 if (SimplifyDemandedBits(Op0, InputDemandedBits, Known, TLO, Depth + 1))
1577 return true;
1578 assert(!Known.hasConflict() && "Bits known to be one AND zero?")((!Known.hasConflict() && "Bits known to be one AND zero?"
) ? static_cast<void> (0) : __assert_fail ("!Known.hasConflict() && \"Bits known to be one AND zero?\""
, "/build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/SelectionDAG/TargetLowering.cpp"
, 1578, __PRETTY_FUNCTION__))
;
1579
1580 // If the sign bit of the input is known set or clear, then we know the
1581 // top bits of the result.
1582
1583 // If the input sign bit is known zero, convert this into a zero extension.
1584 if (Known.Zero[ExVTBits - 1])
1585 return TLO.CombineTo(
1586 Op, TLO.DAG.getZeroExtendInReg(Op0, dl, ExVT.getScalarType()));
1587
1588 APInt Mask = APInt::getLowBitsSet(BitWidth, ExVTBits);
1589 if (Known.One[ExVTBits - 1]) { // Input sign bit known set
1590 Known.One.setBitsFrom(ExVTBits);
1591 Known.Zero &= Mask;
1592 } else { // Input sign bit unknown
1593 Known.Zero &= Mask;
1594 Known.One &= Mask;
1595 }
1596 break;
1597 }
1598 case ISD::BUILD_PAIR: {
1599 EVT HalfVT = Op.getOperand(0).getValueType();
1600 unsigned HalfBitWidth = HalfVT.getScalarSizeInBits();
1601
1602 APInt MaskLo = DemandedBits.getLoBits(HalfBitWidth).trunc(HalfBitWidth);
1603 APInt MaskHi = DemandedBits.getHiBits(HalfBitWidth).trunc(HalfBitWidth);
1604
1605 KnownBits KnownLo, KnownHi;
1606
1607 if (SimplifyDemandedBits(Op.getOperand(0), MaskLo, KnownLo, TLO, Depth + 1))
1608 return true;
1609
1610 if (SimplifyDemandedBits(Op.getOperand(1), MaskHi, KnownHi, TLO, Depth + 1))
1611 return true;
1612
1613 Known.Zero = KnownLo.Zero.zext(BitWidth) |
1614 KnownHi.Zero.zext(BitWidth).shl(HalfBitWidth);
1615
1616 Known.One = KnownLo.One.zext(BitWidth) |
1617 KnownHi.One.zext(BitWidth).shl(HalfBitWidth);
1618 break;
1619 }
1620 case ISD::ZERO_EXTEND:
1621 case ISD::ZERO_EXTEND_VECTOR_INREG: {
1622 SDValue Src = Op.getOperand(0);
1623 EVT SrcVT = Src.getValueType();
1624 unsigned InBits = SrcVT.getScalarSizeInBits();
1625 unsigned InElts = SrcVT.isVector() ? SrcVT.getVectorNumElements() : 1;
1626 bool IsVecInReg = Op.getOpcode() == ISD::ZERO_EXTEND_VECTOR_INREG;
1627
1628 // If none of the top bits are demanded, convert this into an any_extend.
1629 if (DemandedBits.getActiveBits() <= InBits) {
1630 // If we only need the non-extended bits of the bottom element
1631 // then we can just bitcast to the result.
1632 if (IsVecInReg && DemandedElts == 1 &&
1633 VT.getSizeInBits() == SrcVT.getSizeInBits() &&
1634 TLO.DAG.getDataLayout().isLittleEndian())
1635 return TLO.CombineTo(Op, TLO.DAG.getBitcast(VT, Src));
1636
1637 unsigned Opc =
1638 IsVecInReg ? ISD::ANY_EXTEND_VECTOR_INREG : ISD::ANY_EXTEND;
1639 if (!TLO.LegalOperations() || isOperationLegal(Opc, VT))
1640 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT, Src));
1641 }
1642
1643 APInt InDemandedBits = DemandedBits.trunc(InBits);
1644 APInt InDemandedElts = DemandedElts.zextOrSelf(InElts);
1645 if (SimplifyDemandedBits(Src, InDemandedBits, InDemandedElts, Known, TLO,
1646 Depth + 1))
1647 return true;
1648 assert(!Known.hasConflict() && "Bits known to be one AND zero?")((!Known.hasConflict() && "Bits known to be one AND zero?"
) ? static_cast<void> (0) : __assert_fail ("!Known.hasConflict() && \"Bits known to be one AND zero?\""
, "/build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/SelectionDAG/TargetLowering.cpp"
, 1648, __PRETTY_FUNCTION__))
;
1649 assert(Known.getBitWidth() == InBits && "Src width has changed?")((Known.getBitWidth() == InBits && "Src width has changed?"
) ? static_cast<void> (0) : __assert_fail ("Known.getBitWidth() == InBits && \"Src width has changed?\""
, "/build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/SelectionDAG/TargetLowering.cpp"
, 1649, __PRETTY_FUNCTION__))
;
1650 Known = Known.zext(BitWidth, true /* ExtendedBitsAreKnownZero */);
1651 break;
1652 }
1653 case ISD::SIGN_EXTEND:
1654 case ISD::SIGN_EXTEND_VECTOR_INREG: {
1655 SDValue Src = Op.getOperand(0);
1656 EVT SrcVT = Src.getValueType();
1657 unsigned InBits = SrcVT.getScalarSizeInBits();
1658 unsigned InElts = SrcVT.isVector() ? SrcVT.getVectorNumElements() : 1;
1659 bool IsVecInReg = Op.getOpcode() == ISD::SIGN_EXTEND_VECTOR_INREG;
1660
1661 // If none of the top bits are demanded, convert this into an any_extend.
1662 if (DemandedBits.getActiveBits() <= InBits) {
1663 // If we only need the non-extended bits of the bottom element
1664 // then we can just bitcast to the result.
1665 if (IsVecInReg && DemandedElts == 1 &&
1666 VT.getSizeInBits() == SrcVT.getSizeInBits() &&
1667 TLO.DAG.getDataLayout().isLittleEndian())
1668 return TLO.CombineTo(Op, TLO.DAG.getBitcast(VT, Src));
1669
1670 unsigned Opc =
1671 IsVecInReg ? ISD::ANY_EXTEND_VECTOR_INREG : ISD::ANY_EXTEND;
1672 if (!TLO.LegalOperations() || isOperationLegal(Opc, VT))
1673 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT, Src));
1674 }
1675
1676 APInt InDemandedBits = DemandedBits.trunc(InBits);
1677 APInt InDemandedElts = DemandedElts.zextOrSelf(InElts);
1678
1679 // Since some of the sign extended bits are demanded, we know that the sign
1680 // bit is demanded.
1681 InDemandedBits.setBit(InBits - 1);
1682
1683 if (SimplifyDemandedBits(Src, InDemandedBits, InDemandedElts, Known, TLO,
1684 Depth + 1))
1685 return true;
1686 assert(!Known.hasConflict() && "Bits known to be one AND zero?")((!Known.hasConflict() && "Bits known to be one AND zero?"
) ? static_cast<void> (0) : __assert_fail ("!Known.hasConflict() && \"Bits known to be one AND zero?\""
, "/build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/SelectionDAG/TargetLowering.cpp"
, 1686, __PRETTY_FUNCTION__))
;
1687 assert(Known.getBitWidth() == InBits && "Src width has changed?")((Known.getBitWidth() == InBits && "Src width has changed?"
) ? static_cast<void> (0) : __assert_fail ("Known.getBitWidth() == InBits && \"Src width has changed?\""
, "/build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/SelectionDAG/TargetLowering.cpp"
, 1687, __PRETTY_FUNCTION__))
;
1688
1689 // If the sign bit is known one, the top bits match.
1690 Known = Known.sext(BitWidth);
1691
1692 // If the sign bit is known zero, convert this to a zero extend.
1693 if (Known.isNonNegative()) {
1694 unsigned Opc =
1695 IsVecInReg ? ISD::ZERO_EXTEND_VECTOR_INREG : ISD::ZERO_EXTEND;
1696 if (!TLO.LegalOperations() || isOperationLegal(Opc, VT))
1697 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT, Src));
1698 }
1699 break;
1700 }
1701 case ISD::ANY_EXTEND:
1702 case ISD::ANY_EXTEND_VECTOR_INREG: {
1703 SDValue Src = Op.getOperand(0);
1704 EVT SrcVT = Src.getValueType();
1705 unsigned InBits = SrcVT.getScalarSizeInBits();
1706 unsigned InElts = SrcVT.isVector() ? SrcVT.getVectorNumElements() : 1;
1707 bool IsVecInReg = Op.getOpcode() == ISD::ANY_EXTEND_VECTOR_INREG;
1708
1709 // If we only need the bottom element then we can just bitcast.
1710 // TODO: Handle ANY_EXTEND?
1711 if (IsVecInReg && DemandedElts == 1 &&
1712 VT.getSizeInBits() == SrcVT.getSizeInBits() &&
1713 TLO.DAG.getDataLayout().isLittleEndian())
1714 return TLO.CombineTo(Op, TLO.DAG.getBitcast(VT, Src));
1715
1716 APInt InDemandedBits = DemandedBits.trunc(InBits);
1717 APInt InDemandedElts = DemandedElts.zextOrSelf(InElts);
1718 if (SimplifyDemandedBits(Src, InDemandedBits, InDemandedElts, Known, TLO,
1719 Depth + 1))
1720 return true;
1721 assert(!Known.hasConflict() && "Bits known to be one AND zero?")((!Known.hasConflict() && "Bits known to be one AND zero?"
) ? static_cast<void> (0) : __assert_fail ("!Known.hasConflict() && \"Bits known to be one AND zero?\""
, "/build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/SelectionDAG/TargetLowering.cpp"
, 1721, __PRETTY_FUNCTION__))
;
1722 assert(Known.getBitWidth() == InBits && "Src width has changed?")((Known.getBitWidth() == InBits && "Src width has changed?"
) ? static_cast<void> (0) : __assert_fail ("Known.getBitWidth() == InBits && \"Src width has changed?\""
, "/build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/SelectionDAG/TargetLowering.cpp"
, 1722, __PRETTY_FUNCTION__))
;
1723 Known = Known.zext(BitWidth, false /* => any extend */);
1724 break;
1725 }
1726 case ISD::TRUNCATE: {
1727 SDValue Src = Op.getOperand(0);
1728
1729 // Simplify the input, using demanded bit information, and compute the known
1730 // zero/one bits live out.
1731 unsigned OperandBitWidth = Src.getScalarValueSizeInBits();
1732 APInt TruncMask = DemandedBits.zext(OperandBitWidth);
1733 if (SimplifyDemandedBits(Src, TruncMask, Known, TLO, Depth + 1))
1734 return true;
1735 Known = Known.trunc(BitWidth);
1736
1737 // Attempt to avoid multi-use ops if we don't need anything from them.
1738 if (SDValue NewSrc = SimplifyMultipleUseDemandedBits(
1739 Src, TruncMask, DemandedElts, TLO.DAG, Depth + 1))
1740 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::TRUNCATE, dl, VT, NewSrc));
1741
1742 // If the input is only used by this truncate, see if we can shrink it based
1743 // on the known demanded bits.
1744 if (Src.getNode()->hasOneUse()) {
1745 switch (Src.getOpcode()) {
1746 default:
1747 break;
1748 case ISD::SRL:
1749 // Shrink SRL by a constant if none of the high bits shifted in are
1750 // demanded.
1751 if (TLO.LegalTypes() && !isTypeDesirableForOp(ISD::SRL, VT))
1752 // Do not turn (vt1 truncate (vt2 srl)) into (vt1 srl) if vt1 is
1753 // undesirable.
1754 break;
1755
1756 auto *ShAmt = dyn_cast<ConstantSDNode>(Src.getOperand(1));
1757 if (!ShAmt || ShAmt->getAPIntValue().uge(BitWidth))
1758 break;
1759
1760 SDValue Shift = Src.getOperand(1);
1761 uint64_t ShVal = ShAmt->getZExtValue();
1762
1763 if (TLO.LegalTypes())
1764 Shift = TLO.DAG.getConstant(ShVal, dl, getShiftAmountTy(VT, DL));
1765
1766 APInt HighBits =
1767 APInt::getHighBitsSet(OperandBitWidth, OperandBitWidth - BitWidth);
1768 HighBits.lshrInPlace(ShVal);
1769 HighBits = HighBits.trunc(BitWidth);
1770
1771 if (!(HighBits & DemandedBits)) {
1772 // None of the shifted in bits are needed. Add a truncate of the
1773 // shift input, then shift it.
1774 SDValue NewTrunc =
1775 TLO.DAG.getNode(ISD::TRUNCATE, dl, VT, Src.getOperand(0));
1776 return TLO.CombineTo(
1777 Op, TLO.DAG.getNode(ISD::SRL, dl, VT, NewTrunc, Shift));
1778 }
1779 break;
1780 }
1781 }
1782
1783 assert(!Known.hasConflict() && "Bits known to be one AND zero?")((!Known.hasConflict() && "Bits known to be one AND zero?"
) ? static_cast<void> (0) : __assert_fail ("!Known.hasConflict() && \"Bits known to be one AND zero?\""
, "/build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/SelectionDAG/TargetLowering.cpp"
, 1783, __PRETTY_FUNCTION__))
;
1784 break;
1785 }
1786 case ISD::AssertZext: {
1787 // AssertZext demands all of the high bits, plus any of the low bits
1788 // demanded by its users.
1789 EVT ZVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
1790 APInt InMask = APInt::getLowBitsSet(BitWidth, ZVT.getSizeInBits());
1791 if (SimplifyDemandedBits(Op.getOperand(0), ~InMask | DemandedBits, Known,
1792 TLO, Depth + 1))
1793 return true;
1794 assert(!Known.hasConflict() && "Bits known to be one AND zero?")((!Known.hasConflict() && "Bits known to be one AND zero?"
) ? static_cast<void> (0) : __assert_fail ("!Known.hasConflict() && \"Bits known to be one AND zero?\""
, "/build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/SelectionDAG/TargetLowering.cpp"
, 1794, __PRETTY_FUNCTION__))
;
1795
1796 Known.Zero |= ~InMask;
1797 break;
1798 }
1799 case ISD::EXTRACT_VECTOR_ELT: {
1800 SDValue Src = Op.getOperand(0);
1801 SDValue Idx = Op.getOperand(1);
1802 unsigned NumSrcElts = Src.getValueType().getVectorNumElements();
1803 unsigned EltBitWidth = Src.getScalarValueSizeInBits();
1804
1805 // Demand the bits from every vector element without a constant index.
1806 APInt DemandedSrcElts = APInt::getAllOnesValue(NumSrcElts);
1807 if (auto *CIdx = dyn_cast<ConstantSDNode>(Idx))
1808 if (CIdx->getAPIntValue().ult(NumSrcElts))
1809 DemandedSrcElts = APInt::getOneBitSet(NumSrcElts, CIdx->getZExtValue());
1810
1811 // If BitWidth > EltBitWidth the value is anyext:ed. So we do not know
1812 // anything about the extended bits.
1813 APInt DemandedSrcBits = DemandedBits;
1814 if (BitWidth > EltBitWidth)
1815 DemandedSrcBits = DemandedSrcBits.trunc(EltBitWidth);
1816
1817 if (SimplifyDemandedBits(Src, DemandedSrcBits, DemandedSrcElts, Known2, TLO,
1818 Depth + 1))
1819 return true;
1820
1821 Known = Known2;
1822 if (BitWidth > EltBitWidth)
1823 Known = Known.zext(BitWidth, false /* => any extend */);
1824 break;
1825 }
1826 case ISD::BITCAST: {
1827 SDValue Src = Op.getOperand(0);
1828 EVT SrcVT = Src.getValueType();
1829 unsigned NumSrcEltBits = SrcVT.getScalarSizeInBits();
1830
1831 // If this is an FP->Int bitcast and if the sign bit is the only
1832 // thing demanded, turn this into a FGETSIGN.
1833 if (!TLO.LegalOperations() && !VT.isVector() && !SrcVT.isVector() &&
1834 DemandedBits == APInt::getSignMask(Op.getValueSizeInBits()) &&
1835 SrcVT.isFloatingPoint()) {
1836 bool OpVTLegal = isOperationLegalOrCustom(ISD::FGETSIGN, VT);
1837 bool i32Legal = isOperationLegalOrCustom(ISD::FGETSIGN, MVT::i32);
1838 if ((OpVTLegal || i32Legal) && VT.isSimple() && SrcVT != MVT::f16 &&
1839 SrcVT != MVT::f128) {
1840 // Cannot eliminate/lower SHL for f128 yet.
1841 EVT Ty = OpVTLegal ? VT : MVT::i32;
1842 // Make a FGETSIGN + SHL to move the sign bit into the appropriate
1843 // place. We expect the SHL to be eliminated by other optimizations.
1844 SDValue Sign = TLO.DAG.getNode(ISD::FGETSIGN, dl, Ty, Src);
1845 unsigned OpVTSizeInBits = Op.getValueSizeInBits();
1846 if (!OpVTLegal && OpVTSizeInBits > 32)
1847 Sign = TLO.DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Sign);
1848 unsigned ShVal = Op.getValueSizeInBits() - 1;
1849 SDValue ShAmt = TLO.DAG.getConstant(ShVal, dl, VT);
1850 return TLO.CombineTo(Op,
1851 TLO.DAG.getNode(ISD::SHL, dl, VT, Sign, ShAmt));
1852 }
1853 }
1854
1855 // Bitcast from a vector using SimplifyDemanded Bits/VectorElts.
1856 // Demand the elt/bit if any of the original elts/bits are demanded.
1857 // TODO - bigendian once we have test coverage.
1858 if (SrcVT.isVector() && (BitWidth % NumSrcEltBits) == 0 &&
1859 TLO.DAG.getDataLayout().isLittleEndian()) {
1860 unsigned Scale = BitWidth / NumSrcEltBits;
1861 unsigned NumSrcElts = SrcVT.getVectorNumElements();
1862 APInt DemandedSrcBits = APInt::getNullValue(NumSrcEltBits);
1863 APInt DemandedSrcElts = APInt::getNullValue(NumSrcElts);
1864 for (unsigned i = 0; i != Scale; ++i) {
1865 unsigned Offset = i * NumSrcEltBits;
1866 APInt Sub = DemandedBits.extractBits(NumSrcEltBits, Offset);
1867 if (!Sub.isNullValue()) {
1868 DemandedSrcBits |= Sub;
1869 for (unsigned j = 0; j != NumElts; ++j)
1870 if (DemandedElts[j])
1871 DemandedSrcElts.setBit((j * Scale) + i);
1872 }
1873 }
1874
1875 APInt KnownSrcUndef, KnownSrcZero;
1876 if (SimplifyDemandedVectorElts(Src, DemandedSrcElts, KnownSrcUndef,
1877 KnownSrcZero, TLO, Depth + 1))
1878 return true;
1879
1880 KnownBits KnownSrcBits;
1881 if (SimplifyDemandedBits(Src, DemandedSrcBits, DemandedSrcElts,
1882 KnownSrcBits, TLO, Depth + 1))
1883 return true;
1884 } else if ((NumSrcEltBits % BitWidth) == 0 &&
1885 TLO.DAG.getDataLayout().isLittleEndian()) {
1886 unsigned Scale = NumSrcEltBits / BitWidth;
1887 unsigned NumSrcElts = SrcVT.isVector() ? SrcVT.getVectorNumElements() : 1;
1888 APInt DemandedSrcBits = APInt::getNullValue(NumSrcEltBits);
1889 APInt DemandedSrcElts = APInt::getNullValue(NumSrcElts);
1890 for (unsigned i = 0; i != NumElts; ++i)
1891 if (DemandedElts[i]) {
1892 unsigned Offset = (i % Scale) * BitWidth;
1893 DemandedSrcBits.insertBits(DemandedBits, Offset);
1894 DemandedSrcElts.setBit(i / Scale);
1895 }
1896
1897 if (SrcVT.isVector()) {
1898 APInt KnownSrcUndef, KnownSrcZero;
1899 if (SimplifyDemandedVectorElts(Src, DemandedSrcElts, KnownSrcUndef,
1900 KnownSrcZero, TLO, Depth + 1))
1901 return true;
1902 }
1903
1904 KnownBits KnownSrcBits;
1905 if (SimplifyDemandedBits(Src, DemandedSrcBits, DemandedSrcElts,
1906 KnownSrcBits, TLO, Depth + 1))
1907 return true;
1908 }
1909
1910 // If this is a bitcast, let computeKnownBits handle it. Only do this on a
1911 // recursive call where Known may be useful to the caller.
1912 if (Depth > 0) {
1913 Known = TLO.DAG.computeKnownBits(Op, DemandedElts, Depth);
1914 return false;
1915 }
1916 break;
1917 }
1918 case ISD::ADD:
1919 case ISD::MUL:
1920 case ISD::SUB: {
1921 // Add, Sub, and Mul don't demand any bits in positions beyond that
1922 // of the highest bit demanded of them.
1923 SDValue Op0 = Op.getOperand(0), Op1 = Op.getOperand(1);
1924 SDNodeFlags Flags = Op.getNode()->getFlags();
1925 unsigned DemandedBitsLZ = DemandedBits.countLeadingZeros();
1926 APInt LoMask = APInt::getLowBitsSet(BitWidth, BitWidth - DemandedBitsLZ);
1927 if (SimplifyDemandedBits(Op0, LoMask, DemandedElts, Known2, TLO,
1928 Depth + 1) ||
1929 SimplifyDemandedBits(Op1, LoMask, DemandedElts, Known2, TLO,
1930 Depth + 1) ||
1931 // See if the operation should be performed at a smaller bit width.
1932 ShrinkDemandedOp(Op, BitWidth, DemandedBits, TLO)) {
1933 if (Flags.hasNoSignedWrap() || Flags.hasNoUnsignedWrap()) {
1934 // Disable the nsw and nuw flags. We can no longer guarantee that we
1935 // won't wrap after simplification.
1936 Flags.setNoSignedWrap(false);
1937 Flags.setNoUnsignedWrap(false);
1938 SDValue NewOp =
1939 TLO.DAG.getNode(Op.getOpcode(), dl, VT, Op0, Op1, Flags);
1940 return TLO.CombineTo(Op, NewOp);
1941 }
1942 return true;
1943 }
1944
1945 // Attempt to avoid multi-use ops if we don't need anything from them.
1946 if (!LoMask.isAllOnesValue() || !DemandedElts.isAllOnesValue()) {
1947 SDValue DemandedOp0 = SimplifyMultipleUseDemandedBits(
1948 Op0, LoMask, DemandedElts, TLO.DAG, Depth + 1);
1949 SDValue DemandedOp1 = SimplifyMultipleUseDemandedBits(
1950 Op1, LoMask, DemandedElts, TLO.DAG, Depth + 1);
1951 if (DemandedOp0 || DemandedOp1) {
1952 Flags.setNoSignedWrap(false);
1953 Flags.setNoUnsignedWrap(false);
1954 Op0 = DemandedOp0 ? DemandedOp0 : Op0;
1955 Op1 = DemandedOp1 ? DemandedOp1 : Op1;
1956 SDValue NewOp =
1957 TLO.DAG.getNode(Op.getOpcode(), dl, VT, Op0, Op1, Flags);
1958 return TLO.CombineTo(Op, NewOp);
1959 }
1960 }
1961
1962 // If we have a constant operand, we may be able to turn it into -1 if we
1963 // do not demand the high bits. This can make the constant smaller to
1964 // encode, allow more general folding, or match specialized instruction
1965 // patterns (eg, 'blsr' on x86). Don't bother changing 1 to -1 because that
1966 // is probably not useful (and could be detrimental).
1967 ConstantSDNode *C = isConstOrConstSplat(Op1);
1968 APInt HighMask = APInt::getHighBitsSet(BitWidth, DemandedBitsLZ);
1969 if (C && !C->isAllOnesValue() && !C->isOne() &&
1970 (C->getAPIntValue() | HighMask).isAllOnesValue()) {
1971 SDValue Neg1 = TLO.DAG.getAllOnesConstant(dl, VT);
1972 // Disable the nsw and nuw flags. We can no longer guarantee that we
1973 // won't wrap after simplification.
1974 Flags.setNoSignedWrap(false);
1975 Flags.setNoUnsignedWrap(false);
1976 SDValue NewOp = TLO.DAG.getNode(Op.getOpcode(), dl, VT, Op0, Neg1, Flags);
1977 return TLO.CombineTo(Op, NewOp);
1978 }
1979
1980 LLVM_FALLTHROUGH[[gnu::fallthrough]];
1981 }
1982 default:
1983 if (Op.getOpcode() >= ISD::BUILTIN_OP_END) {
1984 if (SimplifyDemandedBitsForTargetNode(Op, DemandedBits, DemandedElts,
1985 Known, TLO, Depth))
1986 return true;
1987 break;
1988 }
1989
1990 // Just use computeKnownBits to compute output bits.
1991 Known = TLO.DAG.computeKnownBits(Op, DemandedElts, Depth);
1992 break;
1993 }
1994
1995 // If we know the value of all of the demanded bits, return this as a
1996 // constant.
1997 if (DemandedBits.isSubsetOf(Known.Zero | Known.One)) {
1998 // Avoid folding to a constant if any OpaqueConstant is involved.
1999 const SDNode *N = Op.getNode();
2000 for (SDNodeIterator I = SDNodeIterator::begin(N),
2001 E = SDNodeIterator::end(N);
2002 I != E; ++I) {
2003 SDNode *Op = *I;
2004 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op))
2005 if (C->isOpaque())
2006 return false;
2007 }
2008 // TODO: Handle float bits as well.
2009 if (VT.isInteger())
2010 return TLO.CombineTo(Op, TLO.DAG.getConstant(Known.One, dl, VT));
2011 }
2012
2013 return false;
2014}
2015
2016bool TargetLowering::SimplifyDemandedVectorElts(SDValue Op,
2017 const APInt &DemandedElts,
2018 APInt &KnownUndef,
2019 APInt &KnownZero,
2020 DAGCombinerInfo &DCI) const {
2021 SelectionDAG &DAG = DCI.DAG;
2022 TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
2023 !DCI.isBeforeLegalizeOps());
2024
2025 bool Simplified =
2026 SimplifyDemandedVectorElts(Op, DemandedElts, KnownUndef, KnownZero, TLO);
2027 if (Simplified) {
2028 DCI.AddToWorklist(Op.getNode());
2029 DCI.CommitTargetLoweringOpt(TLO);
2030 }
2031
2032 return Simplified;
2033}
2034
2035/// Given a vector binary operation and known undefined elements for each input
2036/// operand, compute whether each element of the output is undefined.
2037static APInt getKnownUndefForVectorBinop(SDValue BO, SelectionDAG &DAG,
2038 const APInt &UndefOp0,
2039 const APInt &UndefOp1) {
2040 EVT VT = BO.getValueType();
2041 assert(DAG.getTargetLoweringInfo().isBinOp(BO.getOpcode()) && VT.isVector() &&((DAG.getTargetLoweringInfo().isBinOp(BO.getOpcode()) &&
VT.isVector() && "Vector binop only") ? static_cast<
void> (0) : __assert_fail ("DAG.getTargetLoweringInfo().isBinOp(BO.getOpcode()) && VT.isVector() && \"Vector binop only\""
, "/build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/SelectionDAG/TargetLowering.cpp"
, 2042, __PRETTY_FUNCTION__))
2042 "Vector binop only")((DAG.getTargetLoweringInfo().isBinOp(BO.getOpcode()) &&
VT.isVector() && "Vector binop only") ? static_cast<
void> (0) : __assert_fail ("DAG.getTargetLoweringInfo().isBinOp(BO.getOpcode()) && VT.isVector() && \"Vector binop only\""
, "/build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/SelectionDAG/TargetLowering.cpp"
, 2042, __PRETTY_FUNCTION__))
;
2043
2044 EVT EltVT = VT.getVectorElementType();
2045 unsigned NumElts = VT.getVectorNumElements();
2046 assert(UndefOp0.getBitWidth() == NumElts &&((UndefOp0.getBitWidth() == NumElts && UndefOp1.getBitWidth
() == NumElts && "Bad type for undef analysis") ? static_cast
<void> (0) : __assert_fail ("UndefOp0.getBitWidth() == NumElts && UndefOp1.getBitWidth() == NumElts && \"Bad type for undef analysis\""
, "/build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/SelectionDAG/TargetLowering.cpp"
, 2047, __PRETTY_FUNCTION__))
2047 UndefOp1.getBitWidth() == NumElts && "Bad type for undef analysis")((UndefOp0.getBitWidth() == NumElts && UndefOp1.getBitWidth
() == NumElts && "Bad type for undef analysis") ? static_cast
<void> (0) : __assert_fail ("UndefOp0.getBitWidth() == NumElts && UndefOp1.getBitWidth() == NumElts && \"Bad type for undef analysis\""
, "/build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/SelectionDAG/TargetLowering.cpp"
, 2047, __PRETTY_FUNCTION__))
;
2048
2049 auto getUndefOrConstantElt = [&](SDValue V, unsigned Index,
2050 const APInt &UndefVals) {
2051 if (UndefVals[Index])
2052 return DAG.getUNDEF(EltVT);
2053
2054 if (auto *BV = dyn_cast<BuildVectorSDNode>(V)) {
2055 // Try hard to make sure that the getNode() call is not creating temporary
2056 // nodes. Ignore opaque integers because they do not constant fold.
2057 SDValue Elt = BV->getOperand(Index);
2058 auto *C = dyn_cast<ConstantSDNode>(Elt);
2059 if (isa<ConstantFPSDNode>(Elt) || Elt.isUndef() || (C && !C->isOpaque()))
2060 return Elt;
2061 }
2062
2063 return SDValue();
2064 };
2065
2066 APInt KnownUndef = APInt::getNullValue(NumElts);
2067 for (unsigned i = 0; i != NumElts; ++i) {
2068 // If both inputs for this element are either constant or undef and match
2069 // the element type, compute the constant/undef result for this element of
2070 // the vector.
2071 // TODO: Ideally we would use FoldConstantArithmetic() here, but that does
2072 // not handle FP constants. The code within getNode() should be refactored
2073 // to avoid the danger of creating a bogus temporary node here.
2074 SDValue C0 = getUndefOrConstantElt(BO.getOperand(0), i, UndefOp0);
2075 SDValue C1 = getUndefOrConstantElt(BO.getOperand(1), i, UndefOp1);
2076 if (C0 && C1 && C0.getValueType() == EltVT && C1.getValueType() == EltVT)
2077 if (DAG.getNode(BO.getOpcode(), SDLoc(BO), EltVT, C0, C1).isUndef())
2078 KnownUndef.setBit(i);
2079 }
2080 return KnownUndef;
2081}
2082
2083bool TargetLowering::SimplifyDemandedVectorElts(
2084 SDValue Op, const APInt &OriginalDemandedElts, APInt &KnownUndef,
2085 APInt &KnownZero, TargetLoweringOpt &TLO, unsigned Depth,
2086 bool AssumeSingleUse) const {
2087 EVT VT = Op.getValueType();
2088 APInt DemandedElts = OriginalDemandedElts;
2089 unsigned NumElts = DemandedElts.getBitWidth();
2090 assert(VT.isVector() && "Expected vector op")((VT.isVector() && "Expected vector op") ? static_cast
<void> (0) : __assert_fail ("VT.isVector() && \"Expected vector op\""
, "/build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/SelectionDAG/TargetLowering.cpp"
, 2090, __PRETTY_FUNCTION__))
;
2091 assert(VT.getVectorNumElements() == NumElts &&((VT.getVectorNumElements() == NumElts && "Mask size mismatches value type element count!"
) ? static_cast<void> (0) : __assert_fail ("VT.getVectorNumElements() == NumElts && \"Mask size mismatches value type element count!\""
, "/build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/SelectionDAG/TargetLowering.cpp"
, 2092, __PRETTY_FUNCTION__))
2092 "Mask size mismatches value type element count!")((VT.getVectorNumElements() == NumElts && "Mask size mismatches value type element count!"
) ? static_cast<void> (0) : __assert_fail ("VT.getVectorNumElements() == NumElts && \"Mask size mismatches value type element count!\""
, "/build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/SelectionDAG/TargetLowering.cpp"
, 2092, __PRETTY_FUNCTION__))
;
2093
2094 KnownUndef = KnownZero = APInt::getNullValue(NumElts);
2095
2096 // Undef operand.
2097 if (Op.isUndef()) {
2098 KnownUndef.setAllBits();
2099 return false;
2100 }
2101
2102 // If Op has other users, assume that all elements are needed.
2103 if (!Op.getNode()->hasOneUse() && !AssumeSingleUse)
2104 DemandedElts.setAllBits();
2105
2106 // Not demanding any elements from Op.
2107 if (DemandedElts == 0) {
2108 KnownUndef.setAllBits();
2109 return TLO.CombineTo(Op, TLO.DAG.getUNDEF(VT));
2110 }
2111
2112 // Limit search depth.
2113 if (Depth >= SelectionDAG::MaxRecursionDepth)
2114 return false;
2115
2116 SDLoc DL(Op);
2117 unsigned EltSizeInBits = VT.getScalarSizeInBits();
2118
2119 switch (Op.getOpcode()) {
2120 case ISD::SCALAR_TO_VECTOR: {
2121 if (!DemandedElts[0]) {
2122 KnownUndef.setAllBits();
2123 return TLO.CombineTo(Op, TLO.DAG.getUNDEF(VT));
2124 }
2125 KnownUndef.setHighBits(NumElts - 1);
2126 break;
2127 }
2128 case ISD::BITCAST: {
2129 SDValue Src = Op.getOperand(0);
2130 EVT SrcVT = Src.getValueType();
2131
2132 // We only handle vectors here.
2133 // TODO - investigate calling SimplifyDemandedBits/ComputeKnownBits?
2134 if (!SrcVT.isVector())
2135 break;
2136
2137 // Fast handling of 'identity' bitcasts.
2138 unsigned NumSrcElts = SrcVT.getVectorNumElements();
2139 if (NumSrcElts == NumElts)
2140 return SimplifyDemandedVectorElts(Src, DemandedElts, KnownUndef,
2141 KnownZero, TLO, Depth + 1);
2142
2143 APInt SrcZero, SrcUndef;
2144 APInt SrcDemandedElts = APInt::getNullValue(NumSrcElts);
2145
2146 // Bitcast from 'large element' src vector to 'small element' vector, we
2147 // must demand a source element if any DemandedElt maps to it.
2148 if ((NumElts % NumSrcElts) == 0) {
2149 unsigned Scale = NumElts / NumSrcElts;
2150 for (unsigned i = 0; i != NumElts; ++i)
2151 if (DemandedElts[i])
2152 SrcDemandedElts.setBit(i / Scale);
2153
2154 if (SimplifyDemandedVectorElts(Src, SrcDemandedElts, SrcUndef, SrcZero,
2155 TLO, Depth + 1))
2156 return true;
2157
2158 // Try calling SimplifyDemandedBits, converting demanded elts to the bits
2159 // of the large element.
2160 // TODO - bigendian once we have test coverage.
2161 if (TLO.DAG.getDataLayout().isLittleEndian()) {
2162 unsigned SrcEltSizeInBits = SrcVT.getScalarSizeInBits();
2163 APInt SrcDemandedBits = APInt::getNullValue(SrcEltSizeInBits);
2164 for (unsigned i = 0; i != NumElts; ++i)
2165 if (DemandedElts[i]) {
2166 unsigned Ofs = (i % Scale) * EltSizeInBits;
2167 SrcDemandedBits.setBits(Ofs, Ofs + EltSizeInBits);
2168 }
2169
2170 KnownBits Known;
2171 if (SimplifyDemandedBits(Src, SrcDemandedBits, Known, TLO, Depth + 1))
2172 return true;
2173 }
2174
2175 // If the src element is zero/undef then all the output elements will be -
2176 // only demanded elements are guaranteed to be correct.
2177 for (unsigned i = 0; i != NumSrcElts; ++i) {
2178 if (SrcDemandedElts[i]) {
2179 if (SrcZero[i])
2180 KnownZero.setBits(i * Scale, (i + 1) * Scale);
2181 if (SrcUndef[i])
2182 KnownUndef.setBits(i * Scale, (i + 1) * Scale);
2183 }
2184 }
2185 }
2186
2187 // Bitcast from 'small element' src vector to 'large element' vector, we
2188 // demand all smaller source elements covered by the larger demanded element
2189 // of this vector.
2190 if ((NumSrcElts % NumElts) == 0) {
2191 unsigned Scale = NumSrcElts / NumElts;
2192 for (unsigned i = 0; i != NumElts; ++i)
2193 if (DemandedElts[i])
2194 SrcDemandedElts.setBits(i * Scale, (i + 1) * Scale);
2195
2196 if (SimplifyDemandedVectorElts(Src, SrcDemandedElts, SrcUndef, SrcZero,
2197 TLO, Depth + 1))
2198 return true;
2199
2200 // If all the src elements covering an output element are zero/undef, then
2201 // the output element will be as well, assuming it was demanded.
2202 for (unsigned i = 0; i != NumElts; ++i) {
2203 if (DemandedElts[i]) {
2204 if (SrcZero.extractBits(Scale, i * Scale).isAllOnesValue())
2205 KnownZero.setBit(i);
2206 if (SrcUndef.extractBits(Scale, i * Scale).isAllOnesValue())
2207 KnownUndef.setBit(i);
2208 }
2209 }
2210 }
2211 break;
2212 }
2213 case ISD::BUILD_VECTOR: {
2214 // Check all elements and simplify any unused elements with UNDEF.
2215 if (!DemandedElts.isAllOnesValue()) {
2216 // Don't simplify BROADCASTS.
2217 if (llvm::any_of(Op->op_values(),
2218 [&](SDValue Elt) { return Op.getOperand(0) != Elt; })) {
2219 SmallVector<SDValue, 32> Ops(Op->op_begin(), Op->op_end());
2220 bool Updated = false;
2221 for (unsigned i = 0; i != NumElts; ++i) {
2222 if (!DemandedElts[i] && !Ops[i].isUndef()) {
2223 Ops[i] = TLO.DAG.getUNDEF(Ops[0].getValueType());
2224 KnownUndef.setBit(i);
2225 Updated = true;
2226 }
2227 }
2228 if (Updated)
2229 return TLO.CombineTo(Op, TLO.DAG.getBuildVector(VT, DL, Ops));
2230 }
2231 }
2232 for (unsigned i = 0; i != NumElts; ++i) {
2233 SDValue SrcOp = Op.getOperand(i);
2234 if (SrcOp.isUndef()) {
2235 KnownUndef.setBit(i);
2236 } else if (EltSizeInBits == SrcOp.getScalarValueSizeInBits() &&
2237 (isNullConstant(SrcOp) || isNullFPConstant(SrcOp))) {
2238 KnownZero.setBit(i);
2239 }
2240 }
2241 break;
2242 }
2243 case ISD::CONCAT_VECTORS: {
2244 EVT SubVT = Op.getOperand(0).getValueType();
2245 unsigned NumSubVecs = Op.getNumOperands();
2246 unsigned NumSubElts = SubVT.getVectorNumElements();
2247 for (unsigned i = 0; i != NumSubVecs; ++i) {
2248 SDValue SubOp = Op.getOperand(i);
2249 APInt SubElts = DemandedElts.extractBits(NumSubElts, i * NumSubElts);
2250 APInt SubUndef, SubZero;
2251 if (SimplifyDemandedVectorElts(SubOp, SubElts, SubUndef, SubZero, TLO,
2252 Depth + 1))
2253 return true;
2254 KnownUndef.insertBits(SubUndef, i * NumSubElts);
2255 KnownZero.insertBits(SubZero, i * NumSubElts);
2256 }
2257 break;
2258 }
2259 case ISD::INSERT_SUBVECTOR: {
2260 if (!isa<ConstantSDNode>(Op.getOperand(2)))
2261 break;
2262 SDValue Base = Op.getOperand(0);
2263 SDValue Sub = Op.getOperand(1);
2264 EVT SubVT = Sub.getValueType();
2265 unsigned NumSubElts = SubVT.getVectorNumElements();
2266 const APInt &Idx = Op.getConstantOperandAPInt(2);
2267 if (Idx.ugt(NumElts - NumSubElts))
2268 break;
2269 unsigned SubIdx = Idx.getZExtValue();
2270 APInt SubElts = DemandedElts.extractBits(NumSubElts, SubIdx);
2271 APInt SubUndef, SubZero;
2272 if (SimplifyDemandedVectorElts(Sub, SubElts, SubUndef, SubZero, TLO,
2273 Depth + 1))
2274 return true;
2275 APInt BaseElts = DemandedElts;
2276 BaseElts.insertBits(APInt::getNullValue(NumSubElts), SubIdx);
2277
2278 // If none of the base operand elements are demanded, replace it with undef.
2279 if (!BaseElts && !Base.isUndef())
2280 return TLO.CombineTo(Op,
2281 TLO.DAG.getNode(ISD::INSERT_SUBVECTOR, DL, VT,
2282 TLO.DAG.getUNDEF(VT),
2283 Op.getOperand(1),
2284 Op.getOperand(2)));
2285
2286 if (SimplifyDemandedVectorElts(Base, BaseElts, KnownUndef, KnownZero, TLO,
2287 Depth + 1))
2288 return true;
2289 KnownUndef.insertBits(SubUndef, SubIdx);
2290 KnownZero.insertBits(SubZero, SubIdx);
2291 break;
2292 }
2293 case ISD::EXTRACT_SUBVECTOR: {
2294 SDValue Src = Op.getOperand(0);
2295 ConstantSDNode *SubIdx = dyn_cast<ConstantSDNode>(Op.getOperand(1));
2296 unsigned NumSrcElts = Src.getValueType().getVectorNumElements();
2297 if (SubIdx && SubIdx->getAPIntValue().ule(NumSrcElts - NumElts)) {
2298 // Offset the demanded elts by the subvector index.
2299 uint64_t Idx = SubIdx->getZExtValue();
2300 APInt SrcElts = DemandedElts.zextOrSelf(NumSrcElts).shl(Idx);
2301 APInt SrcUndef, SrcZero;
2302 if (SimplifyDemandedVectorElts(Src, SrcElts, SrcUndef, SrcZero, TLO,
2303 Depth + 1))
2304 return true;
2305 KnownUndef = SrcUndef.extractBits(NumElts, Idx);
2306 KnownZero = SrcZero.extractBits(NumElts, Idx);
2307 }
2308 break;
2309 }
2310 case ISD::INSERT_VECTOR_ELT: {
2311 SDValue Vec = Op.getOperand(0);
2312 SDValue Scl = Op.getOperand(1);
2313 auto *CIdx = dyn_cast<ConstantSDNode>(Op.getOperand(2));
2314
2315 // For a legal, constant insertion index, if we don't need this insertion
2316 // then strip it, else remove it from the demanded elts.
2317 if (CIdx && CIdx->getAPIntValue().ult(NumElts)) {
2318 unsigned Idx = CIdx->getZExtValue();
2319 if (!DemandedElts[Idx])
2320 return TLO.CombineTo(Op, Vec);
2321
2322 APInt DemandedVecElts(DemandedElts);
2323 DemandedVecElts.clearBit(Idx);
2324 if (SimplifyDemandedVectorElts(Vec, DemandedVecElts, KnownUndef,
2325 KnownZero, TLO, Depth + 1))
2326 return true;
2327
2328 KnownUndef.clearBit(Idx);
2329 if (Scl.isUndef())
2330 KnownUndef.setBit(Idx);
2331
2332 KnownZero.clearBit(Idx);
2333 if (isNullConstant(Scl) || isNullFPConstant(Scl))
2334 KnownZero.setBit(Idx);
2335 break;
2336 }
2337
2338 APInt VecUndef, VecZero;
2339 if (SimplifyDemandedVectorElts(Vec, DemandedElts, VecUndef, VecZero, TLO,
2340 Depth + 1))
2341 return true;
2342 // Without knowing the insertion index we can't set KnownUndef/KnownZero.
2343 break;
2344 }
2345 case ISD::VSELECT: {
2346 // Try to transform the select condition based on the current demanded
2347 // elements.
2348 // TODO: If a condition element is undef, we can choose from one arm of the
2349 // select (and if one arm is undef, then we can propagate that to the
2350 // result).
2351 // TODO - add support for constant vselect masks (see IR version of this).
2352 APInt UnusedUndef, UnusedZero;
2353 if (SimplifyDemandedVectorElts(Op.getOperand(0), DemandedElts, UnusedUndef,
2354 UnusedZero, TLO, Depth + 1))
2355 return true;
2356
2357 // See if we can simplify either vselect operand.
2358 APInt DemandedLHS(DemandedElts);
2359 APInt DemandedRHS(DemandedElts);
2360 APInt UndefLHS, ZeroLHS;
2361 APInt UndefRHS, ZeroRHS;
2362 if (SimplifyDemandedVectorElts(Op.getOperand(1), DemandedLHS, UndefLHS,
2363 ZeroLHS, TLO, Depth + 1))
2364 return true;
2365 if (SimplifyDemandedVectorElts(Op.getOperand(2), DemandedRHS, UndefRHS,
2366 ZeroRHS, TLO, Depth + 1))
2367 return true;
2368
2369 KnownUndef = UndefLHS & UndefRHS;
2370 KnownZero = ZeroLHS & ZeroRHS;
2371 break;
2372 }
2373 case ISD::VECTOR_SHUFFLE: {
2374 ArrayRef<int> ShuffleMask = cast<ShuffleVectorSDNode>(Op)->getMask();
2375
2376 // Collect demanded elements from shuffle operands..
2377 APInt DemandedLHS(NumElts, 0);
2378 APInt DemandedRHS(NumElts, 0);
2379 for (unsigned i = 0; i != NumElts; ++i) {
2380 int M = ShuffleMask[i];
2381 if (M < 0 || !DemandedElts[i])
2382 continue;
2383 assert(0 <= M && M < (int)(2 * NumElts) && "Shuffle index out of range")((0 <= M && M < (int)(2 * NumElts) && "Shuffle index out of range"
) ? static_cast<void> (0) : __assert_fail ("0 <= M && M < (int)(2 * NumElts) && \"Shuffle index out of range\""
, "/build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/SelectionDAG/TargetLowering.cpp"
, 2383, __PRETTY_FUNCTION__))
;
2384 if (M < (int)NumElts)
2385 DemandedLHS.setBit(M);
2386 else
2387 DemandedRHS.setBit(M - NumElts);
2388 }
2389
2390 // See if we can simplify either shuffle operand.
2391 APInt UndefLHS, ZeroLHS;
2392 APInt UndefRHS, ZeroRHS;
2393 if (SimplifyDemandedVectorElts(Op.getOperand(0), DemandedLHS, UndefLHS,
2394 ZeroLHS, TLO, Depth + 1))
2395 return true;
2396 if (SimplifyDemandedVectorElts(Op.getOperand(1), DemandedRHS, UndefRHS,
2397 ZeroRHS, TLO, Depth + 1))
2398 return true;
2399
2400 // Simplify mask using undef elements from LHS/RHS.
2401 bool Updated = false;
2402 bool IdentityLHS = true, IdentityRHS = true;
2403 SmallVector<int, 32> NewMask(ShuffleMask.begin(), ShuffleMask.end());
2404 for (unsigned i = 0; i != NumElts; ++i) {
2405 int &M = NewMask[i];
2406 if (M < 0)
2407 continue;
2408 if (!DemandedElts[i] || (M < (int)NumElts && UndefLHS[M]) ||
2409 (M >= (int)NumElts && UndefRHS[M - NumElts])) {
2410 Updated = true;
2411 M = -1;
2412 }
2413 IdentityLHS &= (M < 0) || (M == (int)i);
2414 IdentityRHS &= (M < 0) || ((M - NumElts) == i);
2415 }
2416
2417 // Update legal shuffle masks based on demanded elements if it won't reduce
2418 // to Identity which can cause premature removal of the shuffle mask.
2419 if (Updated && !IdentityLHS && !IdentityRHS && !TLO.LegalOps) {
2420 SDValue LegalShuffle =
2421 buildLegalVectorShuffle(VT, DL, Op.getOperand(0), Op.getOperand(1),
2422 NewMask, TLO.DAG);
2423 if (LegalShuffle)
2424 return TLO.CombineTo(Op, LegalShuffle);
2425 }
2426
2427 // Propagate undef/zero elements from LHS/RHS.
2428 for (unsigned i = 0; i != NumElts; ++i) {
2429 int M = ShuffleMask[i];
2430 if (M < 0) {
2431 KnownUndef.setBit(i);
2432 } else if (M < (int)NumElts) {
2433 if (UndefLHS[M])
2434 KnownUndef.setBit(i);
2435 if (ZeroLHS[M])
2436 KnownZero.setBit(i);
2437 } else {
2438 if (UndefRHS[M - NumElts])
2439 KnownUndef.setBit(i);
2440 if (ZeroRHS[M - NumElts])
2441 KnownZero.setBit(i);
2442 }
2443 }
2444 break;
2445 }
2446 case ISD::ANY_EXTEND_VECTOR_INREG:
2447 case ISD::SIGN_EXTEND_VECTOR_INREG:
2448 case ISD::ZERO_EXTEND_VECTOR_INREG: {
2449 APInt SrcUndef, SrcZero;
2450 SDValue Src = Op.getOperand(0);
2451 unsigned NumSrcElts = Src.getValueType().getVectorNumElements();
2452 APInt DemandedSrcElts = DemandedElts.zextOrSelf(NumSrcElts);
2453 if (SimplifyDemandedVectorElts(Src, DemandedSrcElts, SrcUndef, SrcZero, TLO,
2454 Depth + 1))
2455 return true;
2456 KnownZero = SrcZero.zextOrTrunc(NumElts);
2457 KnownUndef = SrcUndef.zextOrTrunc(NumElts);
2458
2459 if (Op.getOpcode() == ISD::ANY_EXTEND_VECTOR_INREG &&
2460 Op.getValueSizeInBits() == Src.getValueSizeInBits() &&
2461 DemandedSrcElts == 1 && TLO.DAG.getDataLayout().isLittleEndian()) {
2462 // aext - if we just need the bottom element then we can bitcast.
2463 return TLO.CombineTo(Op, TLO.DAG.getBitcast(VT, Src));
2464 }
2465
2466 if (Op.getOpcode() == ISD::ZERO_EXTEND_VECTOR_INREG) {
2467 // zext(undef) upper bits are guaranteed to be zero.
2468 if (DemandedElts.isSubsetOf(KnownUndef))
2469 return TLO.CombineTo(Op, TLO.DAG.getConstant(0, SDLoc(Op), VT));
2470 KnownUndef.clearAllBits();
2471 }
2472 break;
2473 }
2474
2475 // TODO: There are more binop opcodes that could be handled here - MUL, MIN,
2476 // MAX, saturated math, etc.
2477 case ISD::OR:
2478 case ISD::XOR:
2479 case ISD::ADD:
2480 case ISD::SUB:
2481 case ISD::FADD:
2482 case ISD::FSUB:
2483 case ISD::FMUL:
2484 case ISD::FDIV:
2485 case ISD::FREM: {
2486 APInt UndefRHS, ZeroRHS;
2487 if (SimplifyDemandedVectorElts(Op.getOperand(1), DemandedElts, UndefRHS,
2488 ZeroRHS, TLO, Depth + 1))
2489 return true;
2490 APInt UndefLHS, ZeroLHS;
2491 if (SimplifyDemandedVectorElts(Op.getOperand(0), DemandedElts, UndefLHS,
2492 ZeroLHS, TLO, Depth + 1))
2493 return true;
2494
2495 KnownZero = ZeroLHS & ZeroRHS;
2496 KnownUndef = getKnownUndefForVectorBinop(Op, TLO.DAG, UndefLHS, UndefRHS);
2497 break;
2498 }
2499 case ISD::SHL:
2500 case ISD::SRL:
2501 case ISD::SRA:
2502 case ISD::ROTL:
2503 case ISD::ROTR: {
2504 APInt UndefRHS, ZeroRHS;
2505 if (SimplifyDemandedVectorElts(Op.getOperand(1), DemandedElts, UndefRHS,
2506 ZeroRHS, TLO, Depth + 1))
2507 return true;
2508 APInt UndefLHS, ZeroLHS;
2509 if (SimplifyDemandedVectorElts(Op.getOperand(0), DemandedElts, UndefLHS,
2510 ZeroLHS, TLO, Depth + 1))
2511 return true;
2512
2513 KnownZero = ZeroLHS;
2514 KnownUndef = UndefLHS & UndefRHS; // TODO: use getKnownUndefForVectorBinop?
2515 break;
2516 }
2517 case ISD::MUL:
2518 case ISD::AND: {
2519 APInt SrcUndef, SrcZero;
2520 if (SimplifyDemandedVectorElts(Op.getOperand(1), DemandedElts, SrcUndef,
2521 SrcZero, TLO, Depth + 1))
2522 return true;
2523 if (SimplifyDemandedVectorElts(Op.getOperand(0), DemandedElts, KnownUndef,
2524 KnownZero, TLO, Depth + 1))
2525 return true;
2526
2527 // If either side has a zero element, then the result element is zero, even
2528 // if the other is an UNDEF.
2529 // TODO: Extend getKnownUndefForVectorBinop to also deal with known zeros
2530 // and then handle 'and' nodes with the rest of the binop opcodes.
2531 KnownZero |= SrcZero;
2532 KnownUndef &= SrcUndef;
2533 KnownUndef &= ~KnownZero;
2534 break;
2535 }
2536 case ISD::TRUNCATE:
2537 case ISD::SIGN_EXTEND:
2538 case ISD::ZERO_EXTEND:
2539 if (SimplifyDemandedVectorElts(Op.getOperand(0), DemandedElts, KnownUndef,
2540 KnownZero, TLO, Depth + 1))
2541 return true;
2542
2543 if (Op.getOpcode() == ISD::ZERO_EXTEND) {
2544 // zext(undef) upper bits are guaranteed to be zero.
2545 if (DemandedElts.isSubsetOf(KnownUndef))
2546 return TLO.CombineTo(Op, TLO.DAG.getConstant(0, SDLoc(Op), VT));
2547 KnownUndef.clearAllBits();
2548 }
2549 break;
2550 default: {
2551 if (Op.getOpcode() >= ISD::BUILTIN_OP_END) {
2552 if (SimplifyDemandedVectorEltsForTargetNode(Op, DemandedElts, KnownUndef,
2553 KnownZero, TLO, Depth))
2554 return true;
2555 } else {
2556 KnownBits Known;
2557 APInt DemandedBits = APInt::getAllOnesValue(EltSizeInBits);
2558 if (SimplifyDemandedBits(Op, DemandedBits, OriginalDemandedElts, Known,
2559 TLO, Depth, AssumeSingleUse))
2560 return true;
2561 }
2562 break;
2563 }
2564 }
2565 assert((KnownUndef & KnownZero) == 0 && "Elements flagged as undef AND zero")(((KnownUndef & KnownZero) == 0 && "Elements flagged as undef AND zero"
) ? static_cast<void> (0) : __assert_fail ("(KnownUndef & KnownZero) == 0 && \"Elements flagged as undef AND zero\""
, "/build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/SelectionDAG/TargetLowering.cpp"
, 2565, __PRETTY_FUNCTION__))
;
2566
2567 // Constant fold all undef cases.
2568 // TODO: Handle zero cases as well.
2569 if (DemandedElts.isSubsetOf(KnownUndef))
2570 return TLO.CombineTo(Op, TLO.DAG.getUNDEF(VT));
2571
2572 return false;
2573}
2574
2575/// Determine which of the bits specified in Mask are known to be either zero or
2576/// one and return them in the Known.
2577void TargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
2578 KnownBits &Known,
2579 const APInt &DemandedElts,
2580 const SelectionDAG &DAG,
2581 unsigned Depth) const {
2582 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||(((Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode()
== ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN
|| Op.getOpcode() == ISD::INTRINSIC_VOID) && "Should use MaskedValueIsZero if you don't know whether Op"
" is a target node!") ? static_cast<void> (0) : __assert_fail
("(Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && \"Should use MaskedValueIsZero if you don't know whether Op\" \" is a target node!\""
, "/build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/SelectionDAG/TargetLowering.cpp"
, 2587, __PRETTY_FUNCTION__))
2583 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||(((Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode()
== ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN
|| Op.getOpcode() == ISD::INTRINSIC_VOID) && "Should use MaskedValueIsZero if you don't know whether Op"
" is a target node!") ? static_cast<void> (0) : __assert_fail
("(Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && \"Should use MaskedValueIsZero if you don't know whether Op\" \" is a target node!\""
, "/build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/SelectionDAG/TargetLowering.cpp"
, 2587, __PRETTY_FUNCTION__))
2584 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||(((Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode()
== ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN
|| Op.getOpcode() == ISD::INTRINSIC_VOID) && "Should use MaskedValueIsZero if you don't know whether Op"
" is a target node!") ? static_cast<void> (0) : __assert_fail
("(Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && \"Should use MaskedValueIsZero if you don't know whether Op\" \" is a target node!\""
, "/build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/SelectionDAG/TargetLowering.cpp"
, 2587, __PRETTY_FUNCTION__))
2585 Op.getOpcode() == ISD::INTRINSIC_VOID) &&(((Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode()
== ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN
|| Op.getOpcode() == ISD::INTRINSIC_VOID) && "Should use MaskedValueIsZero if you don't know whether Op"
" is a target node!") ? static_cast<void> (0) : __assert_fail
("(Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && \"Should use MaskedValueIsZero if you don't know whether Op\" \" is a target node!\""
, "/build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/SelectionDAG/TargetLowering.cpp"
, 2587, __PRETTY_FUNCTION__))
2586 "Should use MaskedValueIsZero if you don't know whether Op"(((Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode()
== ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN
|| Op.getOpcode() == ISD::INTRINSIC_VOID) && "Should use MaskedValueIsZero if you don't know whether Op"
" is a target node!") ? static_cast<void> (0) : __assert_fail
("(Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && \"Should use MaskedValueIsZero if you don't know whether Op\" \" is a target node!\""
, "/build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/SelectionDAG/TargetLowering.cpp"
, 2587, __PRETTY_FUNCTION__))
2587 " is a target node!")(((Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode()
== ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN
|| Op.getOpcode() == ISD::INTRINSIC_VOID) && "Should use MaskedValueIsZero if you don't know whether Op"
" is a target node!") ? static_cast<void> (0) : __assert_fail
("(Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && \"Should use MaskedValueIsZero if you don't know whether Op\" \" is a target node!\""
, "/build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/SelectionDAG/TargetLowering.cpp"
, 2587, __PRETTY_FUNCTION__))
;
2588 Known.resetAll();
2589}
2590
2591void TargetLowering::computeKnownBitsForTargetInstr(
2592 GISelKnownBits &Analysis, Register R, KnownBits &Known,
2593 const APInt &DemandedElts, const MachineRegisterInfo &MRI,
2594 unsigned Depth) const {
2595 Known.resetAll();
2596}
2597
2598void TargetLowering::computeKnownBitsForFrameIndex(const SDValue Op,
2599 KnownBits &Known,
2600 const APInt &DemandedElts,
2601 const SelectionDAG &DAG,
2602 unsigned Depth) const {
2603 assert(isa<FrameIndexSDNode>(Op) && "expected FrameIndex")((isa<FrameIndexSDNode>(Op) && "expected FrameIndex"
) ? static_cast<void> (0) : __assert_fail ("isa<FrameIndexSDNode>(Op) && \"expected FrameIndex\""
, "/build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/SelectionDAG/TargetLowering.cpp"
, 2603, __PRETTY_FUNCTION__))
;
2604
2605 if (unsigned Align = DAG.InferPtrAlignment(Op)) {
2606 // The low bits are known zero if the pointer is aligned.
2607 Known.Zero.setLowBits(Log2_32(Align));
2608 }
2609}
2610
2611/// This method can be implemented by targets that want to expose additional
2612/// information about sign bits to the DAG Combiner.
2613unsigned TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op,
2614 const APInt &,
2615 const SelectionDAG &,
2616 unsigned Depth) const {
2617 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||(((Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode()
== ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN
|| Op.getOpcode() == ISD::INTRINSIC_VOID) && "Should use ComputeNumSignBits if you don't know whether Op"
" is a target node!") ? static_cast<void> (0) : __assert_fail
("(Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && \"Should use ComputeNumSignBits if you don't know whether Op\" \" is a target node!\""
, "/build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/SelectionDAG/TargetLowering.cpp"
, 2622, __PRETTY_FUNCTION__))
2618 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||(((Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode()
== ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN
|| Op.getOpcode() == ISD::INTRINSIC_VOID) && "Should use ComputeNumSignBits if you don't know whether Op"
" is a target node!") ? static_cast<void> (0) : __assert_fail
("(Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && \"Should use ComputeNumSignBits if you don't know whether Op\" \" is a target node!\""
, "/build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/SelectionDAG/TargetLowering.cpp"
, 2622, __PRETTY_FUNCTION__))
2619 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||(((Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode()
== ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN
|| Op.getOpcode() == ISD::INTRINSIC_VOID) && "Should use ComputeNumSignBits if you don't know whether Op"
" is a target node!") ? static_cast<void> (0) : __assert_fail
("(Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && \"Should use ComputeNumSignBits if you don't know whether Op\" \" is a target node!\""
, "/build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/SelectionDAG/TargetLowering.cpp"
, 2622, __PRETTY_FUNCTION__))
2620 Op.getOpcode() == ISD::INTRINSIC_VOID) &&(((Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode()
== ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN
|| Op.getOpcode() == ISD::INTRINSIC_VOID) && "Should use ComputeNumSignBits if you don't know whether Op"
" is a target node!") ? static_cast<void> (0) : __assert_fail
("(Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && \"Should use ComputeNumSignBits if you don't know whether Op\" \" is a target node!\""
, "/build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/SelectionDAG/TargetLowering.cpp"
, 2622, __PRETTY_FUNCTION__))
2621 "Should use ComputeNumSignBits if you don't know whether Op"(((Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode()
== ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN
|| Op.getOpcode() == ISD::INTRINSIC_VOID) && "Should use ComputeNumSignBits if you don't know whether Op"
" is a target node!") ? static_cast<void> (0) : __assert_fail
("(Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && \"Should use ComputeNumSignBits if you don't know whether Op\" \" is a target node!\""
, "/build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/SelectionDAG/TargetLowering.cpp"
, 2622, __PRETTY_FUNCTION__))
2622 " is a target node!")(((Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode()
== ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN
|| Op.getOpcode() == ISD::INTRINSIC_VOID) && "Should use ComputeNumSignBits if you don't know whether Op"
" is a target node!") ? static_cast<void> (0) : __assert_fail
("(Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && \"Should use ComputeNumSignBits if you don't know whether Op\" \" is a target node!\""
, "/build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/SelectionDAG/TargetLowering.cpp"
, 2622, __PRETTY_FUNCTION__))
;
2623 return 1;
2624}
2625
2626bool TargetLowering::SimplifyDemandedVectorEltsForTargetNode(
2627 SDValue Op, const APInt &DemandedElts, APInt &KnownUndef, APInt &KnownZero,
2628 TargetLoweringOpt &TLO, unsigned Depth) const {
2629 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||(((Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode()
== ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN
|| Op.getOpcode() == ISD::INTRINSIC_VOID) && "Should use SimplifyDemandedVectorElts if you don't know whether Op"
" is a target node!") ? static_cast<void> (0) : __assert_fail
("(Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && \"Should use SimplifyDemandedVectorElts if you don't know whether Op\" \" is a target node!\""
, "/build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/SelectionDAG/TargetLowering.cpp"
, 2634, __PRETTY_FUNCTION__))
2630 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||(((Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode()
== ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN
|| Op.getOpcode() == ISD::INTRINSIC_VOID) && "Should use SimplifyDemandedVectorElts if you don't know whether Op"
" is a target node!") ? static_cast<void> (0) : __assert_fail
("(Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && \"Should use SimplifyDemandedVectorElts if you don't know whether Op\" \" is a target node!\""
, "/build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/SelectionDAG/TargetLowering.cpp"
, 2634, __PRETTY_FUNCTION__))
2631 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||(((Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode()
== ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN
|| Op.getOpcode() == ISD::INTRINSIC_VOID) && "Should use SimplifyDemandedVectorElts if you don't know whether Op"
" is a target node!") ? static_cast<void> (0) : __assert_fail
("(Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && \"Should use SimplifyDemandedVectorElts if you don't know whether Op\" \" is a target node!\""
, "/build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/SelectionDAG/TargetLowering.cpp"
, 2634, __PRETTY_FUNCTION__))
2632 Op.getOpcode() == ISD::INTRINSIC_VOID) &&(((Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode()
== ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN
|| Op.getOpcode() == ISD::INTRINSIC_VOID) && "Should use SimplifyDemandedVectorElts if you don't know whether Op"
" is a target node!") ? static_cast<void> (0) : __assert_fail
("(Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && \"Should use SimplifyDemandedVectorElts if you don't know whether Op\" \" is a target node!\""
, "/build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/SelectionDAG/TargetLowering.cpp"
, 2634, __PRETTY_FUNCTION__))
2633 "Should use SimplifyDemandedVectorElts if you don't know whether Op"(((Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode()
== ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN
|| Op.getOpcode() == ISD::INTRINSIC_VOID) && "Should use SimplifyDemandedVectorElts if you don't know whether Op"
" is a target node!") ? static_cast<void> (0) : __assert_fail
("(Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && \"Should use SimplifyDemandedVectorElts if you don't know whether Op\" \" is a target node!\""
, "/build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/SelectionDAG/TargetLowering.cpp"
, 2634, __PRETTY_FUNCTION__))
2634 " is a target node!")(((Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode()
== ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN
|| Op.getOpcode() == ISD::INTRINSIC_VOID) && "Should use SimplifyDemandedVectorElts if you don't know whether Op"
" is a target node!") ? static_cast<void> (0) : __assert_fail
("(Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && \"Should use SimplifyDemandedVectorElts if you don't know whether Op\" \" is a target node!\""
, "/build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/SelectionDAG/TargetLowering.cpp"
, 2634, __PRETTY_FUNCTION__))
;
2635 return false;
2636}
2637
2638bool TargetLowering::SimplifyDemandedBitsForTargetNode(
2639 SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts,
2640 KnownBits &Known, TargetLoweringOpt &TLO, unsigned Depth) const {
2641 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||(((Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode()
== ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN
|| Op.getOpcode() == ISD::INTRINSIC_VOID) && "Should use SimplifyDemandedBits if you don't know whether Op"
" is a target node!") ? static_cast<void> (0) : __assert_fail
("(Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && \"Should use SimplifyDemandedBits if you don't know whether Op\" \" is a target node!\""
, "/build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/SelectionDAG/TargetLowering.cpp"
, 2646, __PRETTY_FUNCTION__))
2642 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||(((Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode()
== ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN
|| Op.getOpcode() == ISD::INTRINSIC_VOID) && "Should use SimplifyDemandedBits if you don't know whether Op"
" is a target node!") ? static_cast<void> (0) : __assert_fail
("(Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && \"Should use SimplifyDemandedBits if you don't know whether Op\" \" is a target node!\""
, "/build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/SelectionDAG/TargetLowering.cpp"
, 2646, __PRETTY_FUNCTION__))
2643 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||(((Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode()
== ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN
|| Op.getOpcode() == ISD::INTRINSIC_VOID) && "Should use SimplifyDemandedBits if you don't know whether Op"
" is a target node!") ? static_cast<void> (0) : __assert_fail
("(Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && \"Should use SimplifyDemandedBits if you don't know whether Op\" \" is a target node!\""
, "/build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/SelectionDAG/TargetLowering.cpp"
, 2646, __PRETTY_FUNCTION__))
2644 Op.getOpcode() == ISD::INTRINSIC_VOID) &&(((Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode()
== ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN
|| Op.getOpcode() == ISD::INTRINSIC_VOID) && "Should use SimplifyDemandedBits if you don't know whether Op"
" is a target node!") ? static_cast<void> (0) : __assert_fail
("(Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && \"Should use SimplifyDemandedBits if you don't know whether Op\" \" is a target node!\""
, "/build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/SelectionDAG/TargetLowering.cpp"
, 2646, __PRETTY_FUNCTION__))
2645 "Should use SimplifyDemandedBits if you don't know whether Op"(((Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode()
== ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN
|| Op.getOpcode() == ISD::INTRINSIC_VOID) && "Should use SimplifyDemandedBits if you don't know whether Op"
" is a target node!") ? static_cast<void> (0) : __assert_fail
("(Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && \"Should use SimplifyDemandedBits if you don't know whether Op\" \" is a target node!\""
, "/build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/SelectionDAG/TargetLowering.cpp"
, 2646, __PRETTY_FUNCTION__))
2646 " is a target node!")(((Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode()
== ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN
|| Op.getOpcode() == ISD::INTRINSIC_VOID) && "Should use SimplifyDemandedBits if you don't know whether Op"
" is a target node!") ? static_cast<void> (0) : __assert_fail
("(Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && \"Should use SimplifyDemandedBits if you don't know whether Op\" \" is a target node!\""
, "/build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/SelectionDAG/TargetLowering.cpp"
, 2646, __PRETTY_FUNCTION__))
;
2647 computeKnownBitsForTargetNode(Op, Known, DemandedElts, TLO.DAG, Depth);
2648 return false;
2649}
2650
2651SDValue TargetLowering::SimplifyMultipleUseDemandedBitsForTargetNode(
2652 SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts,
2653 SelectionDAG &DAG, unsigned Depth) const {
2654 assert((((Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode()
== ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN
|| Op.getOpcode() == ISD::INTRINSIC_VOID) && "Should use SimplifyMultipleUseDemandedBits if you don't know whether Op"
" is a target node!") ? static_cast<void> (0) : __assert_fail
("(Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && \"Should use SimplifyMultipleUseDemandedBits if you don't know whether Op\" \" is a target node!\""
, "/build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/SelectionDAG/TargetLowering.cpp"
, 2660, __PRETTY_FUNCTION__))
2655 (Op.getOpcode() >= ISD::BUILTIN_OP_END ||(((Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode()
== ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN
|| Op.getOpcode() == ISD::INTRINSIC_VOID) && "Should use SimplifyMultipleUseDemandedBits if you don't know whether Op"
" is a target node!") ? static_cast<void> (0) : __assert_fail
("(Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && \"Should use SimplifyMultipleUseDemandedBits if you don't know whether Op\" \" is a target node!\""
, "/build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/SelectionDAG/TargetLowering.cpp"
, 2660, __PRETTY_FUNCTION__))
2656 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||(((Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode()
== ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN
|| Op.getOpcode() == ISD::INTRINSIC_VOID) && "Should use SimplifyMultipleUseDemandedBits if you don't know whether Op"
" is a target node!") ? static_cast<void> (0) : __assert_fail
("(Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && \"Should use SimplifyMultipleUseDemandedBits if you don't know whether Op\" \" is a target node!\""
, "/build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/SelectionDAG/TargetLowering.cpp"
, 2660, __PRETTY_FUNCTION__))
2657 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||(((Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode()
== ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN
|| Op.getOpcode() == ISD::INTRINSIC_VOID) && "Should use SimplifyMultipleUseDemandedBits if you don't know whether Op"
" is a target node!") ? static_cast<void> (0) : __assert_fail
("(Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && \"Should use SimplifyMultipleUseDemandedBits if you don't know whether Op\" \" is a target node!\""
, "/build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/SelectionDAG/TargetLowering.cpp"
, 2660, __PRETTY_FUNCTION__))
2658 Op.getOpcode() == ISD::INTRINSIC_VOID) &&(((Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode()
== ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN
|| Op.getOpcode() == ISD::INTRINSIC_VOID) && "Should use SimplifyMultipleUseDemandedBits if you don't know whether Op"
" is a target node!") ? static_cast<void> (0) : __assert_fail
("(Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && \"Should use SimplifyMultipleUseDemandedBits if you don't know whether Op\" \" is a target node!\""
, "/build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/SelectionDAG/TargetLowering.cpp"
, 2660, __PRETTY_FUNCTION__))
2659 "Should use SimplifyMultipleUseDemandedBits if you don't know whether Op"(((Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode()
== ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN
|| Op.getOpcode() == ISD::INTRINSIC_VOID) && "Should use SimplifyMultipleUseDemandedBits if you don't know whether Op"
" is a target node!") ? static_cast<void> (0) : __assert_fail
("(Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && \"Should use SimplifyMultipleUseDemandedBits if you don't know whether Op\" \" is a target node!\""
, "/build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/SelectionDAG/TargetLowering.cpp"
, 2660, __PRETTY_FUNCTION__))
2660 " is a target node!")(((Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode()
== ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN
|| Op.getOpcode() == ISD::INTRINSIC_VOID) && "Should use SimplifyMultipleUseDemandedBits if you don't know whether Op"
" is a target node!") ? static_cast<void> (0) : __assert_fail
("(Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && \"Should use SimplifyMultipleUseDemandedBits if you don't know whether Op\" \" is a target node!\""
, "/build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/SelectionDAG/TargetLowering.cpp"
, 2660, __PRETTY_FUNCTION__))
;
2661 return SDValue();
2662}
2663
2664SDValue
2665TargetLowering::buildLegalVectorShuffle(EVT VT, const SDLoc &DL, SDValue N0,
2666 SDValue N1, MutableArrayRef<int> Mask,
2667 SelectionDAG &DAG) const {
2668 bool LegalMask = isShuffleMaskLegal(Mask, VT);
2669 if (!LegalMask) {
2670 std::swap(N0, N1);
2671 ShuffleVectorSDNode::commuteMask(Mask);
2672 LegalMask = isShuffleMaskLegal(Mask, VT);
2673 }
2674
2675 if (!LegalMask)
2676 return SDValue();
2677
2678 return DAG.getVectorShuffle(VT, DL, N0, N1, Mask);
2679}
2680
2681const Constant *TargetLowering::getTargetConstantFromLoad(LoadSDNode*) const {
2682 return nullptr;
2683}
2684
2685bool TargetLowering::isKnownNeverNaNForTargetNode(SDValue Op,
2686 const SelectionDAG &DAG,
2687 bool SNaN,
2688 unsigned Depth) const {
2689 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||(((Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode()
== ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN
|| Op.getOpcode() == ISD::INTRINSIC_VOID) && "Should use isKnownNeverNaN if you don't know whether Op"
" is a target node!") ? static_cast<void> (0) : __assert_fail
("(Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && \"Should use isKnownNeverNaN if you don't know whether Op\" \" is a target node!\""
, "/build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/SelectionDAG/TargetLowering.cpp"
, 2694, __PRETTY_FUNCTION__))
2690 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||(((Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode()
== ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN
|| Op.getOpcode() == ISD::INTRINSIC_VOID) && "Should use isKnownNeverNaN if you don't know whether Op"
" is a target node!") ? static_cast<void> (0) : __assert_fail
("(Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && \"Should use isKnownNeverNaN if you don't know whether Op\" \" is a target node!\""
, "/build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/SelectionDAG/TargetLowering.cpp"
, 2694, __PRETTY_FUNCTION__))
2691 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||(((Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode()
== ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN
|| Op.getOpcode() == ISD::INTRINSIC_VOID) && "Should use isKnownNeverNaN if you don't know whether Op"
" is a target node!") ? static_cast<void> (0) : __assert_fail
("(Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && \"Should use isKnownNeverNaN if you don't know whether Op\" \" is a target node!\""
, "/build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/SelectionDAG/TargetLowering.cpp"
, 2694, __PRETTY_FUNCTION__))
2692 Op.getOpcode() == ISD::INTRINSIC_VOID) &&(((Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode()
== ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN
|| Op.getOpcode() == ISD::INTRINSIC_VOID) && "Should use isKnownNeverNaN if you don't know whether Op"
" is a target node!") ? static_cast<void> (0) : __assert_fail
("(Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && \"Should use isKnownNeverNaN if you don't know whether Op\" \" is a target node!\""
, "/build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/SelectionDAG/TargetLowering.cpp"
, 2694, __PRETTY_FUNCTION__))
2693 "Should use isKnownNeverNaN if you don't know whether Op"(((Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode()
== ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN
|| Op.getOpcode() == ISD::INTRINSIC_VOID) && "Should use isKnownNeverNaN if you don't know whether Op"
" is a target node!") ? static_cast<void> (0) : __assert_fail
("(Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && \"Should use isKnownNeverNaN if you don't know whether Op\" \" is a target node!\""
, "/build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/SelectionDAG/TargetLowering.cpp"
, 2694, __PRETTY_FUNCTION__))
2694 " is a target node!")(((Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode()
== ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN
|| Op.getOpcode() == ISD::INTRINSIC_VOID) && "Should use isKnownNeverNaN if you don't know whether Op"
" is a target node!") ? static_cast<void> (0) : __assert_fail
("(Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && \"Should use isKnownNeverNaN if you don't know whether Op\" \" is a target node!\""
, "/build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/SelectionDAG/TargetLowering.cpp"
, 2694, __PRETTY_FUNCTION__))
;
2695 return false;
2696}
2697
2698// FIXME: Ideally, this would use ISD::isConstantSplatVector(), but that must
2699// work with truncating build vectors and vectors with elements of less than
2700// 8 bits.
2701bool TargetLowering::isConstTrueVal(const SDNode *N) const {
2702 if (!N)
2703 return false;
2704
2705 APInt CVal;
2706 if (auto *CN = dyn_cast<ConstantSDNode>(N)) {
2707 CVal = CN->getAPIntValue();
2708 } else if (auto *BV = dyn_cast<BuildVectorSDNode>(N)) {
2709 auto *CN = BV->getConstantSplatNode();
2710 if (!CN)
2711 return false;
2712
2713 // If this is a truncating build vector, truncate the splat value.
2714 // Otherwise, we may fail to match the expected values below.
2715 unsigned BVEltWidth = BV->getValueType(0).getScalarSizeInBits();
2716 CVal = CN->getAPIntValue();
2717 if (BVEltWidth < CVal.getBitWidth())
2718 CVal = CVal.trunc(BVEltWidth);
2719 } else {
2720 return false;
2721 }
2722
2723 switch (getBooleanContents(N->getValueType(0))) {
2724 case UndefinedBooleanContent:
2725 return CVal[0];
2726 case ZeroOrOneBooleanContent:
2727 return CVal.isOneValue();
2728 case ZeroOrNegativeOneBooleanContent:
2729 return CVal.isAllOnesValue();
2730 }
2731
2732 llvm_unreachable("Invalid boolean contents")::llvm::llvm_unreachable_internal("Invalid boolean contents",
"/build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/SelectionDAG/TargetLowering.cpp"
, 2732)
;
2733}
2734
2735bool TargetLowering::isConstFalseVal(const SDNode *N) const {
2736 if (!N)
2737 return false;
2738
2739 const ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N);
2740 if (!CN) {
2741 const BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(N);
2742 if (!BV)
2743 return false;
2744
2745 // Only interested in constant splats, we don't care about undef
2746 // elements in identifying boolean constants and getConstantSplatNode
2747 // returns NULL if all ops are undef;
2748 CN = BV->getConstantSplatNode();
2749 if (!CN)
2750 return false;
2751 }
2752
2753 if (getBooleanContents(N->getValueType(0)) == UndefinedBooleanContent)
2754 return !CN->getAPIntValue()[0];
2755
2756 return CN->isNullValue();
2757}
2758
2759bool TargetLowering::isExtendedTrueVal(const ConstantSDNode *N, EVT VT,
2760 bool SExt) const {
2761 if (VT == MVT::i1)
2762 return N->isOne();
2763
2764 TargetLowering::BooleanContent Cnt = getBooleanContents(VT);
2765 switch (Cnt) {
2766 case TargetLowering::ZeroOrOneBooleanContent:
2767 // An extended value of 1 is always true, unless its original type is i1,
2768 // in which case it will be sign extended to -1.
2769 return (N->isOne() && !SExt) || (SExt && (N->getValueType(0) != MVT::i1));
2770 case TargetLowering::UndefinedBooleanContent:
2771 case TargetLowering::ZeroOrNegativeOneBooleanContent:
2772 return N->isAllOnesValue() && SExt;
2773 }
2774 llvm_unreachable("Unexpected enumeration.")::llvm::llvm_unreachable_internal("Unexpected enumeration.", "/build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/SelectionDAG/TargetLowering.cpp"
, 2774)
;
2775}
2776
2777/// This helper function of SimplifySetCC tries to optimize the comparison when
2778/// either operand of the SetCC node is a bitwise-and instruction.
2779SDValue TargetLowering::foldSetCCWithAnd(EVT VT, SDValue N0, SDValue N1,
2780 ISD::CondCode Cond, const SDLoc &DL,
2781 DAGCombinerInfo &DCI) const {
2782 // Match these patterns in any of their permutations:
2783 // (X & Y) == Y
2784 // (X & Y) != Y
2785 if (N1.getOpcode() == ISD::AND && N0.getOpcode() != ISD::AND)
2786 std::swap(N0, N1);
2787
2788 EVT OpVT = N0.getValueType();
2789 if (N0.getOpcode() != ISD::AND || !OpVT.isInteger() ||
2790 (Cond != ISD::SETEQ && Cond != ISD::SETNE))
2791 return SDValue();
2792
2793 SDValue X, Y;
2794 if (N0.getOperand(0) == N1) {
2795 X = N0.getOperand(1);
2796 Y = N0.getOperand(0);
2797 } else if (N0.getOperand(1) == N1) {
2798 X = N0.getOperand(0);
2799 Y = N0.getOperand(1);
2800 } else {
2801 return SDValue();
2802 }
2803
2804 SelectionDAG &DAG = DCI.DAG;
2805 SDValue Zero = DAG.getConstant(0, DL, OpVT);
2806 if (DAG.isKnownToBeAPowerOfTwo(Y)) {
2807 // Simplify X & Y == Y to X & Y != 0 if Y has exactly one bit set.
2808 // Note that where Y is variable and is known to have at most one bit set
2809 // (for example, if it is Z & 1) we cannot do this; the expressions are not
2810 // equivalent when Y == 0.
2811 Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true);
2812 if (DCI.isBeforeLegalizeOps() ||
2813 isCondCodeLegal(Cond, N0.getSimpleValueType()))
2814 return DAG.getSetCC(DL, VT, N0, Zero, Cond);
2815 } else if (N0.hasOneUse() && hasAndNotCompare(Y)) {
2816 // If the target supports an 'and-not' or 'and-complement' logic operation,
2817 // try to use that to make a comparison operation more efficient.
2818 // But don't do this transform if the mask is a single bit because there are
2819 // more efficient ways to deal with that case (for example, 'bt' on x86 or
2820 // 'rlwinm' on PPC).
2821
2822 // Bail out if the compare operand that we want to turn into a zero is
2823 // already a zero (otherwise, infinite loop).
2824 auto *YConst = dyn_cast<ConstantSDNode>(Y);
2825 if (YConst && YConst->isNullValue())
2826 return SDValue();
2827
2828 // Transform this into: ~X & Y == 0.
2829 SDValue NotX = DAG.getNOT(SDLoc(X), X, OpVT);
2830 SDValue NewAnd = DAG.getNode(ISD::AND, SDLoc(N0), OpVT, NotX, Y);
2831 return DAG.getSetCC(DL, VT, NewAnd, Zero, Cond);
2832 }
2833
2834 return SDValue();
2835}
2836
2837/// There are multiple IR patterns that could be checking whether certain
2838/// truncation of a signed number would be lossy or not. The pattern which is
2839/// best at IR level, may not lower optimally. Thus, we want to unfold it.
2840/// We are looking for the following pattern: (KeptBits is a constant)
2841/// (add %x, (1 << (KeptBits-1))) srccond (1 << KeptBits)
2842/// KeptBits won't be bitwidth(x), that will be constant-folded to true/false.
2843/// KeptBits also can't be 1, that would have been folded to %x dstcond 0
2844/// We will unfold it into the natural trunc+sext pattern:
2845/// ((%x << C) a>> C) dstcond %x
2846/// Where C = bitwidth(x) - KeptBits and C u< bitwidth(x)
2847SDValue TargetLowering::optimizeSetCCOfSignedTruncationCheck(
2848 EVT SCCVT, SDValue N0, SDValue N1, ISD::CondCode Cond, DAGCombinerInfo &DCI,
2849 const SDLoc &DL) const {
2850 // We must be comparing with a constant.
2851 ConstantSDNode *C1;
2852 if (!(C1 = dyn_cast<ConstantSDNode>(N1)))
2853 return SDValue();
2854
2855 // N0 should be: add %x, (1 << (KeptBits-1))
2856 if (N0->getOpcode() != ISD::ADD)
2857 return SDValue();
2858
2859 // And we must be 'add'ing a constant.
2860 ConstantSDNode *C01;
2861 if (!(C01 = dyn_cast<ConstantSDNode>(N0->getOperand(1))))
2862 return SDValue();
2863
2864 SDValue X = N0->getOperand(0);
2865 EVT XVT = X.getValueType();
2866
2867 // Validate constants ...
2868
2869 APInt I1 = C1->getAPIntValue();
2870
2871 ISD::CondCode NewCond;
2872 if (Cond == ISD::CondCode::SETULT) {
2873 NewCond = ISD::CondCode::SETEQ;
2874 } else if (Cond == ISD::CondCode::SETULE) {
2875 NewCond = ISD::CondCode::SETEQ;
2876 // But need to 'canonicalize' the constant.
2877 I1 += 1;
2878 } else if (Cond == ISD::CondCode::SETUGT) {
2879 NewCond = ISD::CondCode::SETNE;
2880 // But need to 'canonicalize' the constant.
2881 I1 += 1;
2882 } else if (Cond == ISD::CondCode::SETUGE) {
2883 NewCond = ISD::CondCode::SETNE;
2884 } else
2885 return SDValue();
2886
2887 APInt I01 = C01->getAPIntValue();
2888
2889 auto checkConstants = [&I1, &I01]() -> bool {
2890 // Both of them must be power-of-two, and the constant from setcc is bigger.
2891 return I1.ugt(I01) && I1.isPowerOf2() && I01.isPowerOf2();
2892 };
2893
2894 if (checkConstants()) {
2895 // Great, e.g. got icmp ult i16 (add i16 %x, 128), 256
2896 } else {
2897 // What if we invert constants? (and the target predicate)
2898 I1.negate();
2899 I01.negate();
2900 NewCond = getSetCCInverse(NewCond, /*isInteger=*/true);
2901 if (!checkConstants())
2902 return SDValue();
2903 // Great, e.g. got icmp uge i16 (add i16 %x, -128), -256
2904 }
2905
2906 // They are power-of-two, so which bit is set?
2907 const unsigned KeptBits = I1.logBase2();
2908 const unsigned KeptBitsMinusOne = I01.logBase2();
2909
2910 // Magic!
2911 if (KeptBits != (KeptBitsMinusOne + 1))
2912 return SDValue();
2913 assert(KeptBits > 0 && KeptBits < XVT.getSizeInBits() && "unreachable")((KeptBits > 0 && KeptBits < XVT.getSizeInBits(
) && "unreachable") ? static_cast<void> (0) : __assert_fail
("KeptBits > 0 && KeptBits < XVT.getSizeInBits() && \"unreachable\""
, "/build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/SelectionDAG/TargetLowering.cpp"
, 2913, __PRETTY_FUNCTION__))
;
2914
2915 // We don't want to do this in every single case.
2916 SelectionDAG &DAG = DCI.DAG;
2917 if (!DAG.getTargetLoweringInfo().shouldTransformSignedTruncationCheck(
2918 XVT, KeptBits))
2919 return SDValue();
2920
2921 const unsigned MaskedBits = XVT.getSizeInBits() - KeptBits;
2922 assert(MaskedBits > 0 && MaskedBits < XVT.getSizeInBits() && "unreachable")((MaskedBits > 0 && MaskedBits < XVT.getSizeInBits
() && "unreachable") ? static_cast<void> (0) : __assert_fail
("MaskedBits > 0 && MaskedBits < XVT.getSizeInBits() && \"unreachable\""
, "/build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/SelectionDAG/TargetLowering.cpp"
, 2922, __PRETTY_FUNCTION__))
;
2923
2924 // Unfold into: ((%x << C) a>> C) cond %x
2925 // Where 'cond' will be either 'eq' or 'ne'.
2926 SDValue ShiftAmt = DAG.getConstant(MaskedBits, DL, XVT);
2927 SDValue T0 = DAG.getNode(ISD::SHL, DL, XVT, X, ShiftAmt);
2928 SDValue T1 = DAG.getNode(ISD::SRA, DL, XVT, T0, ShiftAmt);
2929 SDValue T2 = DAG.getSetCC(DL, SCCVT, T1, X, NewCond);
2930
2931 return T2;
2932}
2933
2934// (X & (C l>>/<< Y)) ==/!= 0 --> ((X <</l>> Y) & C) ==/!= 0
2935SDValue TargetLowering::optimizeSetCCByHoistingAndByConstFromLogicalShift(
2936 EVT SCCVT, SDValue N0, SDValue N1C, ISD::CondCode Cond,
2937 DAGCombinerInfo &DCI, const SDLoc &DL) const {
2938 assert(isConstOrConstSplat(N1C) &&((isConstOrConstSplat(N1C) && isConstOrConstSplat(N1C
)->getAPIntValue().isNullValue() && "Should be a comparison with 0."
) ? static_cast<void> (0) : __assert_fail ("isConstOrConstSplat(N1C) && isConstOrConstSplat(N1C)->getAPIntValue().isNullValue() && \"Should be a comparison with 0.\""
, "/build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/SelectionDAG/TargetLowering.cpp"
, 2940, __PRETTY_FUNCTION__))
2939 isConstOrConstSplat(N1C)->getAPIntValue().isNullValue() &&((isConstOrConstSplat(N1C) && isConstOrConstSplat(N1C
)->getAPIntValue().isNullValue() && "Should be a comparison with 0."
) ? static_cast<void> (0) : __assert_fail ("isConstOrConstSplat(N1C) && isConstOrConstSplat(N1C)->getAPIntValue().isNullValue() && \"Should be a comparison with 0.\""
, "/build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/SelectionDAG/TargetLowering.cpp"
, 2940, __PRETTY_FUNCTION__))
2940 "Should be a comparison with 0.")((isConstOrConstSplat(N1C) && isConstOrConstSplat(N1C
)->getAPIntValue().isNullValue() && "Should be a comparison with 0."
) ? static_cast<void> (0) : __assert_fail ("isConstOrConstSplat(N1C) && isConstOrConstSplat(N1C)->getAPIntValue().isNullValue() && \"Should be a comparison with 0.\""
, "/build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/SelectionDAG/TargetLowering.cpp"
, 2940, __PRETTY_FUNCTION__))
;
2941 assert((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&(((Cond == ISD::SETEQ || Cond == ISD::SETNE) && "Valid only for [in]equality comparisons."
) ? static_cast<void> (0) : __assert_fail ("(Cond == ISD::SETEQ || Cond == ISD::SETNE) && \"Valid only for [in]equality comparisons.\""
, "/build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/SelectionDAG/TargetLowering.cpp"
, 2942, __PRETTY_FUNCTION__))
2942 "Valid only for [in]equality comparisons.")(((Cond == ISD::SETEQ || Cond == ISD::SETNE) && "Valid only for [in]equality comparisons."
) ? static_cast<void> (0) : __assert_fail ("(Cond == ISD::SETEQ || Cond == ISD::SETNE) && \"Valid only for [in]equality comparisons.\""
, "/build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/SelectionDAG/TargetLowering.cpp"
, 2942, __PRETTY_FUNCTION__))
;
2943
2944 unsigned NewShiftOpcode;
2945 SDValue X, C, Y;
2946
2947 SelectionDAG &DAG = DCI.DAG;
2948 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2949
2950 // Look for '(C l>>/<< Y)'.
2951 auto Match = [&NewShiftOpcode, &X, &C, &Y, &TLI, &DAG](SDValue V) {
2952 // The shift should be one-use.
2953 if (!V.hasOneUse())
2954 return false;
2955 unsigned OldShiftOpcode = V.getOpcode();
2956 switch (OldShiftOpcode) {
2957 case ISD::SHL:
2958 NewShiftOpcode = ISD::SRL;
2959 break;
2960 case ISD::SRL:
2961 NewShiftOpcode = ISD::SHL;
2962 break;
2963 default:
2964 return false; // must be a logical shift.
2965 }
2966 // We should be shifting a constant.
2967 // FIXME: best to use isConstantOrConstantVector().
2968 C = V.getOperand(0);
2969 ConstantSDNode *CC =
2970 isConstOrConstSplat(C, /*AllowUndefs=*/true, /*AllowTruncation=*/true);
2971 if (!CC)
2972 return false;
2973 Y = V.getOperand(1);
2974
2975 ConstantSDNode *XC =
2976 isConstOrConstSplat(X, /*AllowUndefs=*/true, /*AllowTruncation=*/true);
2977 return TLI.shouldProduceAndByConstByHoistingConstFromShiftsLHSOfAnd(
2978 X, XC, CC, Y, OldShiftOpcode, NewShiftOpcode, DAG);
2979 };
2980
2981 // LHS of comparison should be an one-use 'and'.
2982 if (N0.getOpcode() != ISD::AND || !N0.hasOneUse())
2983 return SDValue();
2984
2985 X = N0.getOperand(0);
2986 SDValue Mask = N0.getOperand(1);
2987
2988 // 'and' is commutative!
2989 if (!Match(Mask)) {
2990 std::swap(X, Mask);
2991 if (!Match(Mask))
2992 return SDValue();
2993 }
2994
2995 EVT VT = X.getValueType();
2996
2997 // Produce:
2998 // ((X 'OppositeShiftOpcode' Y) & C) Cond 0
2999 SDValue T0 = DAG.getNode(NewShiftOpcode, DL, VT, X, Y);
3000 SDValue T1 = DAG.getNode(ISD::AND, DL, VT, T0, C);
3001 SDValue T2 = DAG.getSetCC(DL, SCCVT, T1, N1C, Cond);
3002 return T2;
3003}
3004
3005/// Try to fold an equality comparison with a {add/sub/xor} binary operation as
3006/// the 1st operand (N0). Callers are expected to swap the N0/N1 parameters to
3007/// handle the commuted versions of these patterns.
3008SDValue TargetLowering::foldSetCCWithBinOp(EVT VT, SDValue N0, SDValue N1,
3009 ISD::CondCode Cond, const SDLoc &DL,
3010 DAGCombinerInfo &DCI) const {
3011 unsigned BOpcode = N0.getOpcode();
3012 assert((BOpcode == ISD::ADD || BOpcode == ISD::SUB || BOpcode == ISD::XOR) &&(((BOpcode == ISD::ADD || BOpcode == ISD::SUB || BOpcode == ISD
::XOR) && "Unexpected binop") ? static_cast<void>
(0) : __assert_fail ("(BOpcode == ISD::ADD || BOpcode == ISD::SUB || BOpcode == ISD::XOR) && \"Unexpected binop\""
, "/build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/SelectionDAG/TargetLowering.cpp"
, 3013, __PRETTY_FUNCTION__))
3013 "Unexpected binop")(((BOpcode == ISD::ADD || BOpcode == ISD::SUB || BOpcode == ISD
::XOR) && "Unexpected binop") ? static_cast<void>
(0) : __assert_fail ("(BOpcode == ISD::ADD || BOpcode == ISD::SUB || BOpcode == ISD::XOR) && \"Unexpected binop\""
, "/build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/SelectionDAG/TargetLowering.cpp"
, 3013, __PRETTY_FUNCTION__))
;
3014 assert((Cond == ISD::SETEQ || Cond == ISD::SETNE) && "Unexpected condcode")(((Cond == ISD::SETEQ || Cond == ISD::SETNE) && "Unexpected condcode"
) ? static_cast<void> (0) : __assert_fail ("(Cond == ISD::SETEQ || Cond == ISD::SETNE) && \"Unexpected condcode\""
, "/build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/SelectionDAG/TargetLowering.cpp"
, 3014, __PRETTY_FUNCTION__))
;
3015
3016 // (X + Y) == X --> Y == 0
3017 // (X - Y) == X --> Y == 0
3018 // (X ^ Y) == X --> Y == 0
3019 SelectionDAG &DAG = DCI.DAG;
3020 EVT OpVT = N0.getValueType();
3021 SDValue X = N0.getOperand(0);
3022 SDValue Y = N0.getOperand(1);
3023 if (X == N1)
3024 return DAG.getSetCC(DL, VT, Y, DAG.getConstant(0, DL, OpVT), Cond);
3025
3026 if (Y != N1)
3027 return SDValue();
3028
3029 // (X + Y) == Y --> X == 0
3030 // (X ^ Y) == Y --> X == 0
3031 if (BOpcode == ISD::ADD || BOpcode == ISD::XOR)
3032 return DAG.getSetCC(DL, VT, X, DAG.getConstant(0, DL, OpVT), Cond);
3033
3034 // The shift would not be valid if the operands are boolean (i1).
3035 if (!N0.hasOneUse() || OpVT.getScalarSizeInBits() == 1)
3036 return SDValue();
3037
3038 // (X - Y) == Y --> X == Y << 1
3039 EVT ShiftVT = getShiftAmountTy(OpVT, DAG.getDataLayout(),
3040 !DCI.isBeforeLegalize());
3041 SDValue One = DAG.getConstant(1, DL, ShiftVT);
3042 SDValue YShl1 = DAG.getNode(ISD::SHL, DL, N1.getValueType(), Y, One);
3043 if (!DCI.isCalledByLegalizer())
3044 DCI.AddToWorklist(YShl1.getNode());
3045 return DAG.getSetCC(DL, VT, X, YShl1, Cond);
3046}
3047
3048/// Try to simplify a setcc built with the specified operands and cc. If it is
3049/// unable to simplify it, return a null SDValue.
3050SDValue TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
3051 ISD::CondCode Cond, bool foldBooleans,
3052 DAGCombinerInfo &DCI,
3053 const SDLoc &dl) const {
3054 SelectionDAG &DAG = DCI.DAG;
3055 EVT OpVT = N0.getValueType();
3056
3057 // Constant fold or commute setcc.
3058 if (SDValue Fold = DAG.FoldSetCC(VT, N0, N1, Cond, dl))
3059 return Fold;
3060
3061 // Ensure that the constant occurs on the RHS and fold constant comparisons.
3062 // TODO: Handle non-splat vector constants. All undef causes trouble.
3063 ISD::CondCode SwappedCC = ISD::getSetCCSwappedOperands(Cond);
3064 if (isConstOrConstSplat(N0) &&
3065 (DCI.isBeforeLegalizeOps() ||
3066 isCondCodeLegal(SwappedCC, N0.getSimpleValueType())))
3067 return DAG.getSetCC(dl, VT, N1, N0, SwappedCC);
3068
3069 // If we have a subtract with the same 2 non-constant operands as this setcc
3070 // -- but in reverse order -- then try to commute the operands of this setcc
3071 // to match. A matching pair of setcc (cmp) and sub may be combined into 1
3072 // instruction on some targets.
3073 if (!isConstOrConstSplat(N0) && !isConstOrConstSplat(N1) &&
3074 (DCI.isBeforeLegalizeOps() ||
3075 isCondCodeLegal(SwappedCC, N0.getSimpleValueType())) &&
3076 DAG.getNodeIfExists(ISD::SUB, DAG.getVTList(OpVT), { N1, N0 } ) &&
3077 !DAG.getNodeIfExists(ISD::SUB, DAG.getVTList(OpVT), { N0, N1 } ))
3078 return DAG.getSetCC(dl, VT, N1, N0, SwappedCC);
3079
3080 if (auto *N1C = dyn_cast<ConstantSDNode>(N1.getNode())) {
3081 const APInt &C1 = N1C->getAPIntValue();
3082
3083 // If the LHS is '(srl (ctlz x), 5)', the RHS is 0/1, and this is an
3084 // equality comparison, then we're just comparing whether X itself is
3085 // zero.
3086 if (N0.getOpcode() == ISD::SRL && (C1.isNullValue() || C1.isOneValue()) &&
3087 N0.getOperand(0).getOpcode() == ISD::CTLZ &&
3088 N0.getOperand(1).getOpcode() == ISD::Constant) {
3089 const APInt &ShAmt = N0.getConstantOperandAPInt(1);
3090 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
3091 ShAmt == Log2_32(N0.getValueSizeInBits())) {
3092 if ((C1 == 0) == (Cond == ISD::SETEQ)) {
3093 // (srl (ctlz x), 5) == 0 -> X != 0
3094 // (srl (ctlz x), 5) != 1 -> X != 0
3095 Cond = ISD::SETNE;
3096 } else {
3097 // (srl (ctlz x), 5) != 0 -> X == 0
3098 // (srl (ctlz x), 5) == 1 -> X == 0
3099 Cond = ISD::SETEQ;
3100 }
3101 SDValue Zero = DAG.getConstant(0, dl, N0.getValueType());
3102 return DAG.getSetCC(dl, VT, N0.getOperand(0).getOperand(0),
3103 Zero, Cond);
3104 }
3105 }
3106
3107 SDValue CTPOP = N0;
3108 // Look through truncs that don't change the value of a ctpop.
3109 if (N0.hasOneUse() && N0.getOpcode() == ISD::TRUNCATE)
3110 CTPOP = N0.getOperand(0);
3111
3112 if (CTPOP.hasOneUse() && CTPOP.getOpcode() == ISD::CTPOP &&
3113 (N0 == CTPOP ||
3114 N0.getValueSizeInBits() > Log2_32_Ceil(CTPOP.getValueSizeInBits()))) {
3115 EVT CTVT = CTPOP.getValueType();
3116 SDValue CTOp = CTPOP.getOperand(0);
3117
3118 // (ctpop x) u< 2 -> (x & x-1) == 0
3119 // (ctpop x) u> 1 -> (x & x-1) != 0
3120 if ((Cond == ISD::SETULT && C1 == 2) || (Cond == ISD::SETUGT && C1 == 1)){
3121 SDValue NegOne = DAG.getAllOnesConstant(dl, CTVT);
3122 SDValue Add = DAG.getNode(ISD::ADD, dl, CTVT, CTOp, NegOne);
3123 SDValue And = DAG.getNode(ISD::AND, dl, CTVT, CTOp, Add);
3124 ISD::CondCode CC = Cond == ISD::SETULT ? ISD::SETEQ : ISD::SETNE;
3125 return DAG.getSetCC(dl, VT, And, DAG.getConstant(0, dl, CTVT), CC);
3126 }
3127
3128 // If ctpop is not supported, expand a power-of-2 comparison based on it.
3129 if (C1 == 1 && !isOperationLegalOrCustom(ISD::CTPOP, CTVT) &&
3130 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
3131 // (ctpop x) == 1 --> (x != 0) && ((x & x-1) == 0)
3132 // (ctpop x) != 1 --> (x == 0) || ((x & x-1) != 0)
3133 SDValue Zero = DAG.getConstant(0, dl, CTVT);
3134 SDValue NegOne = DAG.getAllOnesConstant(dl, CTVT);
3135 ISD::CondCode InvCond = ISD::getSetCCInverse(Cond, true);
3136 SDValue Add = DAG.getNode(ISD::ADD, dl, CTVT, CTOp, NegOne);
3137 SDValue And = DAG.getNode(ISD::AND, dl, CTVT, CTOp, Add);
3138 SDValue LHS = DAG.getSetCC(dl, VT, CTOp, Zero, InvCond);
3139 SDValue RHS = DAG.getSetCC(dl, VT, And, Zero, Cond);
3140 unsigned LogicOpcode = Cond == ISD::SETEQ ? ISD::AND : ISD::OR;
3141 return DAG.getNode(LogicOpcode, dl, VT, LHS, RHS);
3142 }
3143 }
3144
3145 // (zext x) == C --> x == (trunc C)
3146 // (sext x) == C --> x == (trunc C)
3147 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
3148 DCI.isBeforeLegalize() && N0->hasOneUse()) {
3149 unsigned MinBits = N0.getValueSizeInBits();
3150 SDValue PreExt;
3151 bool Signed = false;
3152 if (N0->getOpcode() == ISD::ZERO_EXTEND) {
3153 // ZExt
3154 MinBits = N0->getOperand(0).getValueSizeInBits();
3155 PreExt = N0->getOperand(0);
3156 } else if (N0->getOpcode() == ISD::AND) {
3157 // DAGCombine turns costly ZExts into ANDs
3158 if (auto *C = dyn_cast<ConstantSDNode>(N0->getOperand(1)))
3159 if ((C->getAPIntValue()+1).isPowerOf2()) {
3160 MinBits = C->getAPIntValue().countTrailingOnes();
3161 PreExt = N0->getOperand(0);
3162 }
3163 } else if (N0->getOpcode() == ISD::SIGN_EXTEND) {
3164 // SExt
3165 MinBits = N0->getOperand(0).getValueSizeInBits();
3166 PreExt = N0->getOperand(0);
3167 Signed = true;
3168 } else if (auto *LN0 = dyn_cast<LoadSDNode>(N0)) {
3169 // ZEXTLOAD / SEXTLOAD
3170 if (LN0->getExtensionType() == ISD::ZEXTLOAD) {
3171 MinBits = LN0->getMemoryVT().getSizeInBits();
3172 PreExt = N0;
3173 } else if (LN0->getExtensionType() == ISD::SEXTLOAD) {
3174 Signed = true;
3175 MinBits = LN0->getMemoryVT().getSizeInBits();
3176 PreExt = N0;
3177 }
3178 }
3179
3180 // Figure out how many bits we need to preserve this constant.
3181 unsigned ReqdBits = Signed ?
3182 C1.getBitWidth() - C1.getNumSignBits() + 1 :
3183 C1.getActiveBits();
3184
3185 // Make sure we're not losing bits from the constant.
3186 if (MinBits > 0 &&
3187 MinBits < C1.getBitWidth() &&
3188 MinBits >= ReqdBits) {
3189 EVT MinVT = EVT::getIntegerVT(*DAG.getContext(), MinBits);
3190 if (isTypeDesirableForOp(ISD::SETCC, MinVT)) {
3191 // Will get folded away.
3192 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, MinVT, PreExt);
3193 if (MinBits == 1 && C1 == 1)
3194 // Invert the condition.
3195 return DAG.getSetCC(dl, VT, Trunc, DAG.getConstant(0, dl, MVT::i1),
3196 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
3197 SDValue C = DAG.getConstant(C1.trunc(MinBits), dl, MinVT);
3198 return DAG.getSetCC(dl, VT, Trunc, C, Cond);
3199 }
3200
3201 // If truncating the setcc operands is not desirable, we can still
3202 // simplify the expression in some cases:
3203 // setcc ([sz]ext (setcc x, y, cc)), 0, setne) -> setcc (x, y, cc)
3204 // setcc ([sz]ext (setcc x, y, cc)), 0, seteq) -> setcc (x, y, inv(cc))
3205 // setcc (zext (setcc x, y, cc)), 1, setne) -> setcc (x, y, inv(cc))
3206 // setcc (zext (setcc x, y, cc)), 1, seteq) -> setcc (x, y, cc)
3207 // setcc (sext (setcc x, y, cc)), -1, setne) -> setcc (x, y, inv(cc))
3208 // setcc (sext (setcc x, y, cc)), -1, seteq) -> setcc (x, y, cc)
3209 SDValue TopSetCC = N0->getOperand(0);
3210 unsigned N0Opc = N0->getOpcode();
3211 bool SExt = (N0Opc == ISD::SIGN_EXTEND);
3212 if (TopSetCC.getValueType() == MVT::i1 && VT == MVT::i1 &&
3213 TopSetCC.getOpcode() == ISD::SETCC &&
3214 (N0Opc == ISD::ZERO_EXTEND || N0Opc == ISD::SIGN_EXTEND) &&
3215 (isConstFalseVal(N1C) ||
3216 isExtendedTrueVal(N1C, N0->getValueType(0), SExt))) {
3217
3218 bool Inverse = (N1C->isNullValue() && Cond == ISD::SETEQ) ||
3219 (!N1C->isNullValue() && Cond == ISD::SETNE);
3220
3221 if (!Inverse)
3222 return TopSetCC;
3223
3224 ISD::CondCode InvCond = ISD::getSetCCInverse(
3225 cast<CondCodeSDNode>(TopSetCC.getOperand(2))->get(),
3226 TopSetCC.getOperand(0).getValueType().isInteger());
3227 return DAG.getSetCC(dl, VT, TopSetCC.getOperand(0),
3228 TopSetCC.getOperand(1),
3229 InvCond);
3230 }
3231 }
3232 }
3233
3234 // If the LHS is '(and load, const)', the RHS is 0, the test is for
3235 // equality or unsigned, and all 1 bits of the const are in the same
3236 // partial word, see if we can shorten the load.
3237 if (DCI.isBeforeLegalize() &&
3238 !ISD::isSignedIntSetCC(Cond) &&
3239 N0.getOpcode() == ISD::AND && C1 == 0 &&
3240 N0.getNode()->hasOneUse() &&
3241 isa<LoadSDNode>(N0.getOperand(0)) &&
3242 N0.getOperand(0).getNode()->hasOneUse() &&
3243 isa<ConstantSDNode>(N0.getOperand(1))) {
3244 LoadSDNode *Lod = cast<LoadSDNode>(N0.getOperand(0));
3245 APInt bestMask;
3246 unsigned bestWidth = 0, bestOffset = 0;
3247 if (Lod->isSimple() && Lod->isUnindexed()) {
3248 unsigned origWidth = N0.getValueSizeInBits();
3249 unsigned maskWidth = origWidth;
3250 // We can narrow (e.g.) 16-bit extending loads on 32-bit target to
3251 // 8 bits, but have to be careful...
3252 if (Lod->getExtensionType() != ISD::NON_EXTLOAD)
3253 origWidth = Lod->getMemoryVT().getSizeInBits();
3254 const APInt &Mask = N0.getConstantOperandAPInt(1);
3255 for (unsigned width = origWidth / 2; width>=8; width /= 2) {
3256 APInt newMask = APInt::getLowBitsSet(maskWidth, width);
3257 for (unsigned offset=0; offset<origWidth/width; offset++) {
3258 if (Mask.isSubsetOf(newMask)) {
3259 if (DAG.getDataLayout().isLittleEndian())
3260 bestOffset = (uint64_t)offset * (width/8);
3261 else
3262 bestOffset = (origWidth/width - offset - 1) * (width/8);
3263 bestMask = Mask.lshr(offset * (width/8) * 8);
3264 bestWidth = width;
3265 break;
3266 }
3267 newMask <<= width;
3268 }
3269 }
3270 }
3271 if (bestWidth) {
3272 EVT newVT = EVT::getIntegerVT(*DAG.getContext(), bestWidth);
3273 if (newVT.isRound() &&
3274 shouldReduceLoadWidth(Lod, ISD::NON_EXTLOAD, newVT)) {
3275 EVT PtrType = Lod->getOperand(1).getValueType();
3276 SDValue Ptr = Lod->getBasePtr();
3277 if (bestOffset != 0)
3278 Ptr = DAG.getNode(ISD::ADD, dl, PtrType, Lod->getBasePtr(),
3279 DAG.getConstant(bestOffset, dl, PtrType));
3280 unsigned NewAlign = MinAlign(Lod->getAlignment(), bestOffset);
3281 SDValue NewLoad = DAG.getLoad(
3282 newVT, dl, Lod->getChain(), Ptr,
3283 Lod->getPointerInfo().getWithOffset(bestOffset), NewAlign);
3284 return DAG.getSetCC(dl, VT,
3285 DAG.getNode(ISD::AND, dl, newVT, NewLoad,
3286 DAG.getConstant(bestMask.trunc(bestWidth),
3287 dl, newVT)),
3288 DAG.getConstant(0LL, dl, newVT), Cond);
3289 }
3290 }
3291 }
3292
3293 // If the LHS is a ZERO_EXTEND, perform the comparison on the input.
3294 if (N0.getOpcode() == ISD::ZERO_EXTEND) {
3295 unsigned InSize = N0.getOperand(0).getValueSizeInBits();
3296
3297 // If the comparison constant has bits in the upper part, the
3298 // zero-extended value could never match.
3299 if (C1.intersects(APInt::getHighBitsSet(C1.getBitWidth(),
3300 C1.getBitWidth() - InSize))) {
3301 switch (Cond) {
3302 case ISD::SETUGT:
3303 case ISD::SETUGE:
3304 case ISD::SETEQ:
3305 return DAG.getConstant(0, dl, VT);
3306 case ISD::SETULT:
3307 case ISD::SETULE:
3308 case ISD::SETNE:
3309 return DAG.getConstant(1, dl, VT);
3310 case ISD::SETGT:
3311 case ISD::SETGE:
3312 // True if the sign bit of C1 is set.
3313 return DAG.getConstant(C1.isNegative(), dl, VT);
3314 case ISD::SETLT:
3315 case ISD::SETLE:
3316 // True if the sign bit of C1 isn't set.
3317 return DAG.getConstant(C1.isNonNegative(), dl, VT);
3318 default:
3319 break;
3320 }
3321 }
3322
3323 // Otherwise, we can perform the comparison with the low bits.
3324 switch (Cond) {
3325 case ISD::SETEQ:
3326 case ISD::SETNE:
3327 case ISD::SETUGT:
3328 case ISD::SETUGE:
3329 case ISD::SETULT:
3330 case ISD::SETULE: {
3331 EVT newVT = N0.getOperand(0).getValueType();
3332 if (DCI.isBeforeLegalizeOps() ||
3333 (isOperationLegal(ISD::SETCC, newVT) &&
3334 isCondCodeLegal(Cond, newVT.getSimpleVT()))) {
3335 EVT NewSetCCVT =
3336 getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), newVT);
3337 SDValue NewConst = DAG.getConstant(C1.trunc(InSize), dl, newVT);
3338
3339 SDValue NewSetCC = DAG.getSetCC(dl, NewSetCCVT, N0.getOperand(0),
3340 NewConst, Cond);
3341 return DAG.getBoolExtOrTrunc(NewSetCC, dl, VT, N0.getValueType());
3342 }
3343 break;
3344 }
3345 default:
3346 break; // todo, be more careful with signed comparisons
3347 }
3348 } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
3349 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
3350 EVT ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT();
3351 unsigned ExtSrcTyBits = ExtSrcTy.getSizeInBits();
3352 EVT ExtDstTy = N0.getValueType();
3353 unsigned ExtDstTyBits = ExtDstTy.getSizeInBits();
3354
3355 // If the constant doesn't fit into the number of bits for the source of
3356 // the sign extension, it is impossible for both sides to be equal.
3357 if (C1.getMinSignedBits() > ExtSrcTyBits)
3358 return DAG.getConstant(Cond == ISD::SETNE, dl, VT);
3359
3360 SDValue ZextOp;
3361 EVT Op0Ty = N0.getOperand(0).getValueType();
3362 if (Op0Ty == ExtSrcTy) {
3363 ZextOp = N0.getOperand(0);
3364 } else {
3365 APInt Imm = APInt::getLowBitsSet(ExtDstTyBits, ExtSrcTyBits);
3366 ZextOp = DAG.getNode(ISD::AND, dl, Op0Ty, N0.getOperand(0),
3367 DAG.getConstant(Imm, dl, Op0Ty));
3368 }
3369 if (!DCI.isCalledByLegalizer())
3370 DCI.AddToWorklist(ZextOp.getNode());
3371 // Otherwise, make this a use of a zext.
3372 return DAG.getSetCC(dl, VT, ZextOp,
3373 DAG.getConstant(C1 & APInt::getLowBitsSet(
3374 ExtDstTyBits,
3375 ExtSrcTyBits),
3376 dl, ExtDstTy),
3377 Cond);
3378 } else if ((N1C->isNullValue() || N1C->isOne()) &&
3379 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
3380 // SETCC (SETCC), [0|1], [EQ|NE] -> SETCC
3381 if (N0.getOpcode() == ISD::SETCC &&
3382 isTypeLegal(VT) && VT.bitsLE(N0.getValueType())) {
3383 bool TrueWhenTrue = (Cond == ISD::SETEQ) ^ (!N1C->isOne());
3384 if (TrueWhenTrue)
3385 return DAG.getNode(ISD::TRUNCATE, dl, VT, N0);
3386 // Invert the condition.
3387 ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get();
3388 CC = ISD::getSetCCInverse(CC,
3389 N0.getOperand(0).getValueType().isInteger());
3390 if (DCI.isBeforeLegalizeOps() ||
3391 isCondCodeLegal(CC, N0.getOperand(0).getSimpleValueType()))
3392 return DAG.getSetCC(dl, VT, N0.getOperand(0), N0.getOperand(1), CC);
3393 }
3394
3395 if ((N0.getOpcode() == ISD::XOR ||
3396 (N0.getOpcode() == ISD::AND &&
3397 N0.getOperand(0).getOpcode() == ISD::XOR &&
3398 N0.getOperand(1) == N0.getOperand(0).getOperand(1))) &&
3399 isa<ConstantSDNode>(N0.getOperand(1)) &&
3400 cast<ConstantSDNode>(N0.getOperand(1))->isOne()) {
3401 // If this is (X^1) == 0/1, swap the RHS and eliminate the xor. We
3402 // can only do this if the top bits are known zero.
3403 unsigned BitWidth = N0.getValueSizeInBits();
3404 if (DAG.MaskedValueIsZero(N0,
3405 APInt::getHighBitsSet(BitWidth,
3406 BitWidth-1))) {
3407 // Okay, get the un-inverted input value.
3408 SDValue Val;
3409 if (N0.getOpcode() == ISD::XOR) {
3410 Val = N0.getOperand(0);
3411 } else {
3412 assert(N0.getOpcode() == ISD::AND &&((N0.getOpcode() == ISD::AND && N0.getOperand(0).getOpcode
() == ISD::XOR) ? static_cast<void> (0) : __assert_fail
("N0.getOpcode() == ISD::AND && N0.getOperand(0).getOpcode() == ISD::XOR"
, "/build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/SelectionDAG/TargetLowering.cpp"
, 3413, __PRETTY_FUNCTION__))
3413 N0.getOperand(0).getOpcode() == ISD::XOR)((N0.getOpcode() == ISD::AND && N0.getOperand(0).getOpcode
() == ISD::XOR) ? static_cast<void> (0) : __assert_fail
("N0.getOpcode() == ISD::AND && N0.getOperand(0).getOpcode() == ISD::XOR"
, "/build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/SelectionDAG/TargetLowering.cpp"
, 3413, __PRETTY_FUNCTION__))
;
3414 // ((X^1)&1)^1 -> X & 1
3415 Val = DAG.getNode(ISD::AND, dl, N0.getValueType(),
3416 N0.getOperand(0).getOperand(0),
3417 N0.getOperand(1));
3418 }
3419
3420 return DAG.getSetCC(dl, VT, Val, N1,
3421 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
3422 }
3423 } else if (N1C->isOne() &&
3424 (VT == MVT::i1 ||
3425 getBooleanContents(N0->getValueType(0)) ==
3426 ZeroOrOneBooleanContent)) {
3427 SDValue Op0 = N0;
3428 if (Op0.getOpcode() == ISD::TRUNCATE)
3429 Op0 = Op0.getOperand(0);
3430
3431 if ((Op0.getOpcode() == ISD::XOR) &&
3432 Op0.getOperand(0).getOpcode() == ISD::SETCC &&
3433 Op0.getOperand(1).getOpcode() == ISD::SETCC) {
3434 // (xor (setcc), (setcc)) == / != 1 -> (setcc) != / == (setcc)
3435 Cond = (Cond == ISD::SETEQ) ? ISD::SETNE : ISD::SETEQ;
3436 return DAG.getSetCC(dl, VT, Op0.getOperand(0), Op0.getOperand(1),
3437 Cond);
3438 }
3439 if (Op0.getOpcode() == ISD::AND &&
3440 isa<ConstantSDNode>(Op0.getOperand(1)) &&
3441 cast<ConstantSDNode>(Op0.getOperand(1))->isOne()) {
3442 // If this is (X&1) == / != 1, normalize it to (X&1) != / == 0.
3443 if (Op0.getValueType().bitsGT(VT))
3444 Op0 = DAG.getNode(ISD::AND, dl, VT,
3445 DAG.getNode(ISD::TRUNCATE, dl, VT, Op0.getOperand(0)),
3446 DAG.getConstant(1, dl, VT));
3447 else if (Op0.getValueType().bitsLT(VT))
3448 Op0 = DAG.getNode(ISD::AND, dl, VT,
3449 DAG.getNode(ISD::ANY_EXTEND, dl, VT, Op0.getOperand(0)),
3450 DAG.getConstant(1, dl, VT));
3451
3452 return DAG.getSetCC(dl, VT, Op0,
3453 DAG.getConstant(0, dl, Op0.getValueType()),
3454 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
3455 }
3456 if (Op0.getOpcode() == ISD::AssertZext &&
3457 cast<VTSDNode>(Op0.getOperand(1))->getVT() == MVT::i1)
3458 return DAG.getSetCC(dl, VT, Op0,
3459 DAG.getConstant(0, dl, Op0.getValueType()),
3460 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
3461 }
3462 }
3463
3464 // Given:
3465 // icmp eq/ne (urem %x, %y), 0
3466 // Iff %x has 0 or 1 bits set, and %y has at least 2 bits set, omit 'urem':
3467 // icmp eq/ne %x, 0
3468 if (N0.getOpcode() == ISD::UREM && N1C->isNullValue() &&
3469 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
3470 KnownBits XKnown = DAG.computeKnownBits(N0.getOperand(0));
3471 KnownBits YKnown = DAG.computeKnownBits(N0.getOperand(1));
3472 if (XKnown.countMaxPopulation() == 1 && YKnown.countMinPopulation() >= 2)
3473 return DAG.getSetCC(dl, VT, N0.getOperand(0), N1, Cond);
3474 }
3475
3476 if (SDValue V =
3477 optimizeSetCCOfSignedTruncationCheck(VT, N0, N1, Cond, DCI, dl))
3478 return V;
3479 }
3480
3481 // These simplifications apply to splat vectors as well.
3482 // TODO: Handle more splat vector cases.
3483 if (auto *N1C = isConstOrConstSplat(N1)) {
3484 const APInt &C1 = N1C->getAPIntValue();
3485
3486 APInt MinVal, MaxVal;
3487 unsigned OperandBitSize = N1C->getValueType(0).getScalarSizeInBits();
3488 if (ISD::isSignedIntSetCC(Cond)) {
3489 MinVal = APInt::getSignedMinValue(OperandBitSize);
3490 MaxVal = APInt::getSignedMaxValue(OperandBitSize);
3491 } else {
3492 MinVal = APInt::getMinValue(OperandBitSize);
3493 MaxVal = APInt::getMaxValue(OperandBitSize);
3494 }
3495
3496 // Canonicalize GE/LE comparisons to use GT/LT comparisons.
3497 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) {
3498 // X >= MIN --> true
3499 if (C1 == MinVal)
3500 return DAG.getBoolConstant(true, dl, VT, OpVT);
3501
3502 if (!VT.isVector()) { // TODO: Support this for vectors.
3503 // X >= C0 --> X > (C0 - 1)
3504 APInt C = C1 - 1;
3505 ISD::CondCode NewCC = (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT;
3506 if ((DCI.isBeforeLegalizeOps() ||
3507 isCondCodeLegal(NewCC, VT.getSimpleVT())) &&
3508 (!N1C->isOpaque() || (C.getBitWidth() <= 64 &&
3509 isLegalICmpImmediate(C.getSExtValue())))) {
3510 return DAG.getSetCC(dl, VT, N0,
3511 DAG.getConstant(C, dl, N1.getValueType()),
3512 NewCC);
3513 }
3514 }
3515 }
3516
3517 if (Cond == ISD::SETLE || Cond == ISD::SETULE) {
3518 // X <= MAX --> true
3519 if (C1 == MaxVal)
3520 return DAG.getBoolConstant(true, dl, VT, OpVT);
3521
3522 // X <= C0 --> X < (C0 + 1)
3523 if (!VT.isVector()) { // TODO: Support this for vectors.
3524 APInt C = C1 + 1;
3525 ISD::CondCode NewCC = (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT;
3526 if ((DCI.isBeforeLegalizeOps() ||
3527 isCondCodeLegal(NewCC, VT.getSimpleVT())) &&
3528 (!N1C->isOpaque() || (C.getBitWidth() <= 64 &&
3529 isLegalICmpImmediate(C.getSExtValue())))) {
3530 return DAG.getSetCC(dl, VT, N0,
3531 DAG.getConstant(C, dl, N1.getValueType()),
3532 NewCC);
3533 }
3534 }
3535 }
3536
3537 if (Cond == ISD::SETLT || Cond == ISD::SETULT) {
3538 if (C1 == MinVal)
3539 return DAG.getBoolConstant(false, dl, VT, OpVT); // X < MIN --> false
3540
3541 // TODO: Support this for vectors after legalize ops.
3542 if (!VT.isVector() || DCI.isBeforeLegalizeOps()) {
3543 // Canonicalize setlt X, Max --> setne X, Max
3544 if (C1 == MaxVal)
3545 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE);
3546
3547 // If we have setult X, 1, turn it into seteq X, 0
3548 if (C1 == MinVal+1)
3549 return DAG.getSetCC(dl, VT, N0,
3550 DAG.getConstant(MinVal, dl, N0.getValueType()),
3551 ISD::SETEQ);
3552 }
3553 }
3554
3555 if (Cond == ISD::SETGT || Cond == ISD::SETUGT) {
3556 if (C1 == MaxVal)
3557 return DAG.getBoolConstant(false, dl, VT, OpVT); // X > MAX --> false
3558
3559 // TODO: Support this for vectors after legalize ops.
3560 if (!VT.isVector() || DCI.isBeforeLegalizeOps()) {
3561 // Canonicalize setgt X, Min --> setne X, Min
3562 if (C1 == MinVal)
3563 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE);
3564
3565 // If we have setugt X, Max-1, turn it into seteq X, Max
3566 if (C1 == MaxVal-1)
3567 return DAG.getSetCC(dl, VT, N0,
3568 DAG.getConstant(MaxVal, dl, N0.getValueType()),
3569 ISD::SETEQ);
3570 }
3571 }
3572
3573 if (Cond == ISD::SETEQ || Cond == ISD::SETNE) {
3574 // (X & (C l>>/<< Y)) ==/!= 0 --> ((X <</l>> Y) & C) ==/!= 0
3575 if (C1.isNullValue())
3576 if (SDValue CC = optimizeSetCCByHoistingAndByConstFromLogicalShift(
3577 VT, N0, N1, Cond, DCI, dl))
3578 return CC;
3579 }
3580
3581 // If we have "setcc X, C0", check to see if we can shrink the immediate
3582 // by changing cc.
3583 // TODO: Support this for vectors after legalize ops.
3584 if (!VT.isVector() || DCI.isBeforeLegalizeOps()) {
3585 // SETUGT X, SINTMAX -> SETLT X, 0
3586 if (Cond == ISD::SETUGT &&
3587 C1 == APInt::getSignedMaxValue(OperandBitSize))
3588 return DAG.getSetCC(dl, VT, N0,
3589 DAG.getConstant(0, dl, N1.getValueType()),
3590 ISD::SETLT);
3591
3592 // SETULT X, SINTMIN -> SETGT X, -1
3593 if (Cond == ISD::SETULT &&
3594 C1 == APInt::getSignedMinValue(OperandBitSize)) {
3595 SDValue ConstMinusOne =
3596 DAG.getConstant(APInt::getAllOnesValue(OperandBitSize), dl,
3597 N1.getValueType());
3598 return DAG.getSetCC(dl, VT, N0, ConstMinusOne, ISD::SETGT);
3599 }
3600 }
3601 }
3602
3603 // Back to non-vector simplifications.
3604 // TODO: Can we do these for vector splats?
3605 if (auto *N1C = dyn_cast<ConstantSDNode>(N1.getNode())) {
3606 const APInt &C1 = N1C->getAPIntValue();
3607
3608 // Fold bit comparisons when we can.
3609 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
3610 (VT == N0.getValueType() ||
3611 (isTypeLegal(VT) && VT.bitsLE(N0.getValueType()))) &&
3612 N0.getOpcode() == ISD::AND) {
3613 auto &DL = DAG.getDataLayout();
3614 if (auto *AndRHS = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
3615 EVT ShiftTy = getShiftAmountTy(N0.getValueType(), DL,
3616 !DCI.isBeforeLegalize());
3617 if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3
3618 // Perform the xform if the AND RHS is a single bit.
3619 if (AndRHS->getAPIntValue().isPowerOf2()) {
3620 return DAG.getNode(ISD::TRUNCATE, dl, VT,
3621 DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0,
3622 DAG.getConstant(AndRHS->getAPIntValue().logBase2(), dl,
3623 ShiftTy)));
3624 }
3625 } else if (Cond == ISD::SETEQ && C1 == AndRHS->getAPIntValue()) {
3626 // (X & 8) == 8 --> (X & 8) >> 3
3627 // Perform the xform if C1 is a single bit.
3628 if (C1.isPowerOf2()) {
3629 return DAG.getNode(ISD::TRUNCATE, dl, VT,
3630 DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0,
3631 DAG.getConstant(C1.logBase2(), dl,
3632 ShiftTy)));
3633 }
3634 }
3635 }
3636 }
3637
3638 if (C1.getMinSignedBits() <= 64 &&
3639 !isLegalICmpImmediate(C1.getSExtValue())) {
3640 // (X & -256) == 256 -> (X >> 8) == 1
3641 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
3642 N0.getOpcode() == ISD::AND && N0.hasOneUse()) {
3643 if (auto *AndRHS = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
3644 const APInt &AndRHSC = AndRHS->getAPIntValue();
3645 if ((-AndRHSC).isPowerOf2() && (AndRHSC & C1) == C1) {
3646 unsigned ShiftBits = AndRHSC.countTrailingZeros();
3647 auto &DL = DAG.getDataLayout();
3648 EVT ShiftTy = getShiftAmountTy(N0.getValueType(), DL,
3649 !DCI.isBeforeLegalize());
3650 EVT CmpTy = N0.getValueType();
3651 SDValue Shift = DAG.getNode(ISD::SRL, dl, CmpTy, N0.getOperand(0),
3652 DAG.getConstant(ShiftBits, dl,
3653 ShiftTy));
3654 SDValue CmpRHS = DAG.getConstant(C1.lshr(ShiftBits), dl, CmpTy);
3655 return DAG.getSetCC(dl, VT, Shift, CmpRHS, Cond);
3656 }
3657 }
3658 } else if (Cond == ISD::SETULT || Cond == ISD::SETUGE ||
3659 Cond == ISD::SETULE || Cond == ISD::SETUGT) {
3660 bool AdjOne = (Cond == ISD::SETULE || Cond == ISD::SETUGT);
3661 // X < 0x100000000 -> (X >> 32) < 1
3662 // X >= 0x100000000 -> (X >> 32) >= 1
3663 // X <= 0x0ffffffff -> (X >> 32) < 1
3664 // X > 0x0ffffffff -> (X >> 32) >= 1
3665 unsigned ShiftBits;
3666 APInt NewC = C1;
3667 ISD::CondCode NewCond = Cond;
3668 if (AdjOne) {
3669 ShiftBits = C1.countTrailingOnes();
3670 NewC = NewC + 1;
3671 NewCond = (Cond == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
3672 } else {
3673 ShiftBits = C1.countTrailingZeros();
3674 }
3675 NewC.lshrInPlace(ShiftBits);
3676 if (ShiftBits && NewC.getMinSignedBits() <= 64 &&
3677 isLegalICmpImmediate(NewC.getSExtValue())) {
3678 auto &DL = DAG.getDataLayout();
3679 EVT ShiftTy = getShiftAmountTy(N0.getValueType(), DL,
3680 !DCI.isBeforeLegalize());
3681 EVT CmpTy = N0.getValueType();
3682 SDValue Shift = DAG.getNode(ISD::SRL, dl, CmpTy, N0,
3683 DAG.getConstant(ShiftBits, dl, ShiftTy));
3684 SDValue CmpRHS = DAG.getConstant(NewC, dl, CmpTy);
3685 return DAG.getSetCC(dl, VT, Shift, CmpRHS, NewCond);
3686 }
3687 }
3688 }
3689 }
3690
3691 if (!isa<ConstantFPSDNode>(N0) && isa<ConstantFPSDNode>(N1)) {
3692 auto *CFP = cast<ConstantFPSDNode>(N1);
3693 assert(!CFP->getValueAPF().isNaN() && "Unexpected NaN value")((!CFP->getValueAPF().isNaN() && "Unexpected NaN value"
) ? static_cast<void> (0) : __assert_fail ("!CFP->getValueAPF().isNaN() && \"Unexpected NaN value\""
, "/build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/SelectionDAG/TargetLowering.cpp"
, 3693, __PRETTY_FUNCTION__))
;
3694
3695 // Otherwise, we know the RHS is not a NaN. Simplify the node to drop the
3696 // constant if knowing that the operand is non-nan is enough. We prefer to
3697 // have SETO(x,x) instead of SETO(x, 0.0) because this avoids having to
3698 // materialize 0.0.
3699 if (Cond == ISD::SETO || Cond == ISD::SETUO)
3700 return DAG.getSetCC(dl, VT, N0, N0, Cond);
3701
3702 // setcc (fneg x), C -> setcc swap(pred) x, -C
3703 if (N0.getOpcode() == ISD::FNEG) {
3704 ISD::CondCode SwapCond = ISD::getSetCCSwappedOperands(Cond);
3705 if (DCI.isBeforeLegalizeOps() ||
3706 isCondCodeLegal(SwapCond, N0.getSimpleValueType())) {
3707 SDValue NegN1 = DAG.getNode(ISD::FNEG, dl, N0.getValueType(), N1);
3708 return DAG.getSetCC(dl, VT, N0.getOperand(0), NegN1, SwapCond);
3709 }
3710 }
3711
3712 // If the condition is not legal, see if we can find an equivalent one
3713 // which is legal.
3714 if (!isCondCodeLegal(Cond, N0.getSimpleValueType())) {
3715 // If the comparison was an awkward floating-point == or != and one of
3716 // the comparison operands is infinity or negative infinity, convert the
3717 // condition to a less-awkward <= or >=.
3718 if (CFP->getValueAPF().isInfinity()) {
3719 if (CFP->getValueAPF().isNegative()) {
3720 if (Cond == ISD::SETOEQ &&
3721 isCondCodeLegal(ISD::SETOLE, N0.getSimpleValueType()))
3722 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLE);
3723 if (Cond == ISD::SETUEQ &&
3724 isCondCodeLegal(ISD::SETOLE, N0.getSimpleValueType()))
3725 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULE);
3726 if (Cond == ISD::SETUNE &&
3727 isCondCodeLegal(ISD::SETUGT, N0.getSimpleValueType()))
3728 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGT);
3729 if (Cond == ISD::SETONE &&
3730 isCondCodeLegal(ISD::SETUGT, N0.getSimpleValueType()))
3731 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGT);
3732 } else {
3733 if (Cond == ISD::SETOEQ &&
3734 isCondCodeLegal(ISD::SETOGE, N0.getSimpleValueType()))
3735 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGE);
3736 if (Cond == ISD::SETUEQ &&
3737 isCondCodeLegal(ISD::SETOGE, N0.getSimpleValueType()))
3738 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGE);
3739 if (Cond == ISD::SETUNE &&
3740 isCondCodeLegal(ISD::SETULT, N0.getSimpleValueType()))
3741 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULT);
3742 if (Cond == ISD::SETONE &&
3743 isCondCodeLegal(ISD::SETULT, N0.getSimpleValueType()))
3744 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLT);
3745 }
3746 }
3747 }
3748 }
3749
3750 if (N0 == N1) {
3751 // The sext(setcc()) => setcc() optimization relies on the appropriate
3752 // constant being emitted.
3753 assert(!N0.getValueType().isInteger() &&((!N0.getValueType().isInteger() && "Integer types should be handled by FoldSetCC"
) ? static_cast<void> (0) : __assert_fail ("!N0.getValueType().isInteger() && \"Integer types should be handled by FoldSetCC\""
, "/build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/SelectionDAG/TargetLowering.cpp"
, 3754, __PRETTY_FUNCTION__))
3754 "Integer types should be handled by FoldSetCC")((!N0.getValueType().isInteger() && "Integer types should be handled by FoldSetCC"
) ? static_cast<void> (0) : __assert_fail ("!N0.getValueType().isInteger() && \"Integer types should be handled by FoldSetCC\""
, "/build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/SelectionDAG/TargetLowering.cpp"
, 3754, __PRETTY_FUNCTION__))
;
3755
3756 bool EqTrue = ISD::isTrueWhenEqual(Cond);
3757 unsigned UOF = ISD::getUnorderedFlavor(Cond);
3758 if (UOF == 2) // FP operators that are undefined on NaNs.
3759 return DAG.getBoolConstant(EqTrue, dl, VT, OpVT);
3760 if (UOF == unsigned(EqTrue))
3761 return DAG.getBoolConstant(EqTrue, dl, VT, OpVT);
3762 // Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO
3763 // if it is not already.
3764 ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO;
3765 if (NewCond != Cond &&
3766 (DCI.isBeforeLegalizeOps() ||
3767 isCondCodeLegal(NewCond, N0.getSimpleValueType())))
3768 return DAG.getSetCC(dl, VT, N0, N1, NewCond);
3769 }
3770
3771 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
3772 N0.getValueType().isInteger()) {
3773 if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB ||
3774 N0.getOpcode() == ISD::XOR) {
3775 // Simplify (X+Y) == (X+Z) --> Y == Z
3776 if (N0.getOpcode() == N1.getOpcode()) {
3777 if (N0.getOperand(0) == N1.getOperand(0))
3778 return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(1), Cond);
3779 if (N0.getOperand(1) == N1.getOperand(1))
3780 return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(0), Cond);
3781 if (isCommutativeBinOp(N0.getOpcode())) {
3782 // If X op Y == Y op X, try other combinations.
3783 if (N0.getOperand(0) == N1.getOperand(1))
3784 return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(0),
3785 Cond);
3786 if (N0.getOperand(1) == N1.getOperand(0))
3787 return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(1),
3788 Cond);
3789 }
3790 }
3791
3792 // If RHS is a legal immediate value for a compare instruction, we need
3793 // to be careful about increasing register pressure needlessly.
3794 bool LegalRHSImm = false;
3795
3796 if (auto *RHSC = dyn_cast<ConstantSDNode>(N1)) {
3797 if (auto *LHSR = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
3798 // Turn (X+C1) == C2 --> X == C2-C1
3799 if (N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse()) {
3800 return DAG.getSetCC(dl, VT, N0.getOperand(0),
3801 DAG.getConstant(RHSC->getAPIntValue()-
3802 LHSR->getAPIntValue(),
3803 dl, N0.getValueType()), Cond);
3804 }
3805
3806 // Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0.
3807 if (N0.getOpcode() == ISD::XOR)
3808 // If we know that all of the inverted bits are zero, don't bother
3809 // performing the inversion.
3810 if (DAG.MaskedValueIsZero(N0.getOperand(0), ~LHSR->getAPIntValue()))
3811 return
3812 DAG.getSetCC(dl, VT, N0.getOperand(0),
3813 DAG.getConstant(LHSR->getAPIntValue() ^
3814 RHSC->getAPIntValue(),
3815 dl, N0.getValueType()),
3816 Cond);
3817 }
3818
3819 // Turn (C1-X) == C2 --> X == C1-C2
3820 if (auto *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand(0))) {
3821 if (N0.getOpcode() == ISD::SUB && N0.getNode()->hasOneUse()) {
3822 return
3823 DAG.getSetCC(dl, VT, N0.getOperand(1),
3824 DAG.getConstant(SUBC->getAPIntValue() -
3825 RHSC->getAPIntValue(),
3826 dl, N0.getValueType()),
3827 Cond);
3828 }
3829 }
3830
3831 // Could RHSC fold directly into a compare?
3832 if (RHSC->getValueType(0).getSizeInBits() <= 64)
3833 LegalRHSImm = isLegalICmpImmediate(RHSC->getSExtValue());
3834 }
3835
3836 // (X+Y) == X --> Y == 0 and similar folds.
3837 // Don't do this if X is an immediate that can fold into a cmp
3838 // instruction and X+Y has other uses. It could be an induction variable
3839 // chain, and the transform would increase register pressure.
3840 if (!LegalRHSImm || N0.hasOneUse())
3841 if (SDValue V = foldSetCCWithBinOp(VT, N0, N1, Cond, dl, DCI))
3842 return V;
3843 }
3844
3845 if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB ||
3846 N1.getOpcode() == ISD::XOR)
3847 if (SDValue V = foldSetCCWithBinOp(VT, N1, N0, Cond, dl, DCI))
3848 return V;
3849
3850 if (SDValue V = foldSetCCWithAnd(VT, N0, N1, Cond, dl, DCI))
3851 return V;
3852 }
3853
3854 // Fold remainder of division by a constant.
3855 if ((N0.getOpcode() == ISD::UREM || N0.getOpcode() == ISD::SREM) &&
3856 N0.hasOneUse() && (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
3857 AttributeList Attr = DAG.getMachineFunction().getFunction().getAttributes();
3858
3859 // When division is cheap or optimizing for minimum size,
3860 // fall through to DIVREM creation by skipping this fold.
3861 if (!isIntDivCheap(VT, Attr) && !Attr.hasFnAttribute(Attribute::MinSize)) {
3862 if (N0.getOpcode() == ISD::UREM) {
3863 if (SDValue Folded = buildUREMEqFold(VT, N0, N1, Cond, DCI, dl))
3864 return Folded;
3865 } else if (N0.getOpcode() == ISD::SREM) {
3866 if (SDValue Folded = buildSREMEqFold(VT, N0, N1, Cond, DCI, dl))
3867 return Folded;
3868 }
3869 }
3870 }
3871
3872 // Fold away ALL boolean setcc's.
3873 if (N0.getValueType().getScalarType() == MVT::i1 && foldBooleans) {
3874 SDValue Temp;
3875 switch (Cond) {
3876 default: llvm_unreachable("Unknown integer setcc!")::llvm::llvm_unreachable_internal("Unknown integer setcc!", "/build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/SelectionDAG/TargetLowering.cpp"
, 3876)
;
3877 case ISD::SETEQ: // X == Y -> ~(X^Y)
3878 Temp = DAG.getNode(ISD::XOR, dl, OpVT, N0, N1);
3879 N0 = DAG.getNOT(dl, Temp, OpVT);
3880 if (!DCI.isCalledByLegalizer())
3881 DCI.AddToWorklist(Temp.getNode());
3882 break;
3883 case ISD::SETNE: // X != Y --> (X^Y)
3884 N0 = DAG.getNode(ISD::XOR, dl, OpVT, N0, N1);
3885 break;
3886 case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> ~X & Y
3887 case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> ~X & Y
3888 Temp = DAG.getNOT(dl, N0, OpVT);
3889 N0 = DAG.getNode(ISD::AND, dl, OpVT, N1, Temp);
3890 if (!DCI.isCalledByLegalizer())
3891 DCI.AddToWorklist(Temp.getNode());
3892 break;
3893 case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> ~Y & X
3894 case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> ~Y & X
3895 Temp = DAG.getNOT(dl, N1, OpVT);
3896 N0 = DAG.getNode(ISD::AND, dl, OpVT, N0, Temp);
3897 if (!DCI.isCalledByLegalizer())
3898 DCI.AddToWorklist(Temp.getNode());
3899 break;
3900 case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> ~X | Y
3901 case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> ~X | Y
3902 Temp = DAG.getNOT(dl, N0, OpVT);
3903 N0 = DAG.getNode(ISD::OR, dl, OpVT, N1, Temp);
3904 if (!DCI.isCalledByLegalizer())
3905 DCI.AddToWorklist(Temp.getNode());
3906 break;
3907 case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> ~Y | X
3908 case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> ~Y | X
3909 Temp = DAG.getNOT(dl, N1, OpVT);
3910 N0 = DAG.getNode(ISD::OR, dl, OpVT, N0, Temp);
3911 break;
3912 }
3913 if (VT.getScalarType() != MVT::i1) {
3914 if (!DCI.isCalledByLegalizer())
3915 DCI.AddToWorklist(N0.getNode());
3916 // FIXME: If running after legalize, we probably can't do this.
3917 ISD::NodeType ExtendCode = getExtendForContent(getBooleanContents(OpVT));
3918 N0 = DAG.getNode(ExtendCode, dl, VT, N0);
3919 }
3920 return N0;
3921 }
3922
3923 // Could not fold it.
3924 return SDValue();
3925}
3926
3927/// Returns true (and the GlobalValue and the offset) if the node is a
3928/// GlobalAddress + offset.
3929bool TargetLowering::isGAPlusOffset(SDNode *WN, const GlobalValue *&GA,
3930 int64_t &Offset) const {
3931
3932 SDNode *N = unwrapAddress(SDValue(WN, 0)).getNode();
3933
3934 if (auto *GASD = dyn_cast<GlobalAddressSDNode>(N)) {
3935 GA = GASD->getGlobal();
3936 Offset += GASD->getOffset();
3937 return true;
3938 }
3939
3940 if (N->getOpcode() == ISD::ADD) {
3941 SDValue N1 = N->getOperand(0);
3942 SDValue N2 = N->getOperand(1);
3943 if (isGAPlusOffset(N1.getNode(), GA, Offset)) {
3944 if (auto *V = dyn_cast<ConstantSDNode>(N2)) {
3945 Offset += V->getSExtValue();
3946 return true;
3947 }
3948 } else if (isGAPlusOffset(N2.getNode(), GA, Offset)) {
3949 if (auto *V = dyn_cast<ConstantSDNode>(N1)) {
3950 Offset += V->getSExtValue();
3951 return true;
3952 }
3953 }
3954 }
3955
3956 return false;
3957}
3958
3959SDValue TargetLowering::PerformDAGCombine(SDNode *N,
3960 DAGCombinerInfo &DCI) const {
3961 // Default implementation: no optimization.
3962 return SDValue();
3963}
3964
3965//===----------------------------------------------------------------------===//
3966// Inline Assembler Implementation Methods
3967//===----------------------------------------------------------------------===//
3968
3969TargetLowering::ConstraintType
3970TargetLowering::getConstraintType(StringRef Constraint) const {
3971 unsigned S = Constraint.size();
3972
3973 if (S == 1) {
3974 switch (Constraint[0]) {
3975 default: break;
3976 case 'r':
3977 return C_RegisterClass;
3978 case 'm': // memory
3979 case 'o': // offsetable
3980 case 'V': // not offsetable
3981 return C_Memory;
3982 case 'n': // Simple Integer
3983 case 'E': // Floating Point Constant
3984 case 'F': // Floating Point Constant
3985 return C_Immediate;
3986 case 'i': // Simple Integer or Relocatable Constant
3987 case 's': // Relocatable Constant
3988 case 'p': // Address.
3989 case 'X': // Allow ANY value.
3990 case 'I': // Target registers.
3991 case 'J':
3992 case 'K':
3993 case 'L':
3994 case 'M':
3995 case 'N':
3996 case 'O':
3997 case 'P':
3998 case '<':
3999 case '>':
4000 return C_Other;
4001 }
4002 }
4003
4004 if (S > 1 && Constraint[0] == '{' && Constraint[S - 1] == '}') {
4005 if (S == 8 && Constraint.substr(1, 6) == "memory") // "{memory}"
4006 return C_Memory;
4007 return C_Register;
4008 }
4009 return C_Unknown;
4010}
4011
4012/// Try to replace an X constraint, which matches anything, with another that
4013/// has more specific requirements based on the type of the corresponding
4014/// operand.
4015const char *TargetLowering::LowerXConstraint(EVT ConstraintVT) const {
4016 if (ConstraintVT.isInteger())
4017 return "r";
4018 if (ConstraintVT.isFloatingPoint())
4019 return "f"; // works for many targets
4020 return nullptr;
4021}
4022
4023SDValue TargetLowering::LowerAsmOutputForConstraint(
4024 SDValue &Chain, SDValue &Flag, SDLoc DL, const AsmOperandInfo &OpInfo,
4025 SelectionDAG &DAG) const {
4026 return SDValue();
4027}
4028
4029/// Lower the specified operand into the Ops vector.
4030/// If it is invalid, don't add anything to Ops.
4031void TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
4032 std::string &Constraint,
4033 std::vector<SDValue> &Ops,
4034 SelectionDAG &DAG) const {
4035
4036 if (Constraint.length() > 1) return;
4037
4038 char ConstraintLetter = Constraint[0];
4039 switch (ConstraintLetter) {
4040 default: break;
4041 case 'X': // Allows any operand; labels (basic block) use this.
4042 if (Op.getOpcode() == ISD::BasicBlock ||
4043 Op.getOpcode() == ISD::TargetBlockAddress) {
4044 Ops.push_back(Op);
4045 return;
4046 }
4047 LLVM_FALLTHROUGH[[gnu::fallthrough]];
4048 case 'i': // Simple Integer or Relocatable Constant
4049 case 'n': // Simple Integer
4050 case 's': { // Relocatable Constant
4051
4052 GlobalAddressSDNode *GA;
4053 ConstantSDNode *C;
4054 BlockAddressSDNode *BA;
4055 uint64_t Offset = 0;
4056
4057 // Match (GA) or (C) or (GA+C) or (GA-C) or ((GA+C)+C) or (((GA+C)+C)+C),
4058 // etc., since getelementpointer is variadic. We can't use
4059 // SelectionDAG::FoldSymbolOffset because it expects the GA to be accessible
4060 // while in this case the GA may be furthest from the root node which is
4061 // likely an ISD::ADD.
4062 while (1) {
4063 if ((GA = dyn_cast<GlobalAddressSDNode>(Op)) && ConstraintLetter != 'n') {
4064 Ops.push_back(DAG.getTargetGlobalAddress(GA->getGlobal(), SDLoc(Op),
4065 GA->getValueType(0),
4066 Offset + GA->getOffset()));
4067 return;
4068 } else if ((C = dyn_cast<ConstantSDNode>(Op)) &&
4069 ConstraintLetter != 's') {
4070 // gcc prints these as sign extended. Sign extend value to 64 bits
4071 // now; without this it would get ZExt'd later in
4072 // ScheduleDAGSDNodes::EmitNode, which is very generic.
4073 bool IsBool = C->getConstantIntValue()->getBitWidth() == 1;
4074 BooleanContent BCont = getBooleanContents(MVT::i64);
4075 ISD::NodeType ExtOpc = IsBool ? getExtendForContent(BCont)
4076 : ISD::SIGN_EXTEND;
4077 int64_t ExtVal = ExtOpc == ISD::ZERO_EXTEND ? C->getZExtValue()
4078 : C->getSExtValue();
4079 Ops.push_back(DAG.getTargetConstant(Offset + ExtVal,
4080 SDLoc(C), MVT::i64));
4081 return;
4082 } else if ((BA = dyn_cast<BlockAddressSDNode>(Op)) &&
4083 ConstraintLetter != 'n') {
4084 Ops.push_back(DAG.getTargetBlockAddress(
4085 BA->getBlockAddress(), BA->getValueType(0),
4086 Offset + BA->getOffset(), BA->getTargetFlags()));
4087 return;
4088 } else {
4089 const unsigned OpCode = Op.getOpcode();
4090 if (OpCode == ISD::ADD || OpCode == ISD::SUB) {
4091 if ((C = dyn_cast<ConstantSDNode>(Op.getOperand(0))))
4092 Op = Op.getOperand(1);
4093 // Subtraction is not commutative.
4094 else if (OpCode == ISD::ADD &&
4095 (C = dyn_cast<ConstantSDNode>(Op.getOperand(1))))
4096 Op = Op.getOperand(0);
4097 else
4098 return;
4099 Offset += (OpCode == ISD::ADD ? 1 : -1) * C->getSExtValue();
4100 continue;
4101 }
4102 }
4103 return;
4104 }
4105 break;
4106 }
4107 }
4108}
4109
4110std::pair<unsigned, const TargetRegisterClass *>
4111TargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *RI,
4112 StringRef Constraint,
4113 MVT VT) const {
4114 if (Constraint.empty() || Constraint[0] != '{')
4115 return std::make_pair(0u, static_cast<TargetRegisterClass *>(nullptr));
4116 assert(*(Constraint.end() - 1) == '}' && "Not a brace enclosed constraint?")((*(Constraint.end() - 1) == '}' && "Not a brace enclosed constraint?"
) ? static_cast<void> (0) : __assert_fail ("*(Constraint.end() - 1) == '}' && \"Not a brace enclosed constraint?\""
, "/build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/SelectionDAG/TargetLowering.cpp"
, 4116, __PRETTY_FUNCTION__))
;
4117
4118 // Remove the braces from around the name.
4119 StringRef RegName(Constraint.data() + 1, Constraint.size() - 2);
4120
4121 std::pair<unsigned, const TargetRegisterClass *> R =
4122 std::make_pair(0u, static_cast<const TargetRegisterClass *>(nullptr));
4123
4124 // Figure out which register class contains this reg.
4125 for (const TargetRegisterClass *RC : RI->regclasses()) {
4126 // If none of the value types for this register class are valid, we
4127 // can't use it. For example, 64-bit reg classes on 32-bit targets.
4128 if (!isLegalRC(*RI, *RC))
4129 continue;
4130
4131 for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end();
4132 I != E; ++I) {
4133 if (RegName.equals_lower(RI->getRegAsmName(*I))) {
4134 std::pair<unsigned, const TargetRegisterClass *> S =
4135 std::make_pair(*I, RC);
4136
4137 // If this register class has the requested value type, return it,
4138 // otherwise keep searching and return the first class found
4139 // if no other is found which explicitly has the requested type.
4140 if (RI->isTypeLegalForClass(*RC, VT))
4141 return S;
4142 if (!R.second)
4143 R = S;
4144 }
4145 }
4146 }
4147
4148 return R;
4149}
4150
4151//===----------------------------------------------------------------------===//
4152// Constraint Selection.
4153
4154/// Return true of this is an input operand that is a matching constraint like
4155/// "4".
4156bool TargetLowering::AsmOperandInfo::isMatchingInputConstraint() const {
4157 assert(!ConstraintCode.empty() && "No known constraint!")((!ConstraintCode.empty() && "No known constraint!") ?
static_cast<void> (0) : __assert_fail ("!ConstraintCode.empty() && \"No known constraint!\""
, "/build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/SelectionDAG/TargetLowering.cpp"
, 4157, __PRETTY_FUNCTION__))
;
4158 return isdigit(static_cast<unsigned char>(ConstraintCode[0]));
4159}
4160
4161/// If this is an input matching constraint, this method returns the output
4162/// operand it matches.
4163unsigned TargetLowering::AsmOperandInfo::getMatchedOperand() const {
4164 assert(!ConstraintCode.empty() && "No known constraint!")((!ConstraintCode.empty() && "No known constraint!") ?
static_cast<void> (0) : __assert_fail ("!ConstraintCode.empty() && \"No known constraint!\""
, "/build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/SelectionDAG/TargetLowering.cpp"
, 4164, __PRETTY_FUNCTION__))
;
4165 return atoi(ConstraintCode.c_str());
4166}
4167
4168/// Split up the constraint string from the inline assembly value into the
4169/// specific constraints and their prefixes, and also tie in the associated
4170/// operand values.
4171/// If this returns an empty vector, and if the constraint string itself
4172/// isn't empty, there was an error parsing.
4173TargetLowering::AsmOperandInfoVector
4174TargetLowering::ParseConstraints(const DataLayout &DL,
4175 const TargetRegisterInfo *TRI,
4176 ImmutableCallSite CS) const {
4177 /// Information about all of the constraints.
4178 AsmOperandInfoVector ConstraintOperands;
4179 const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
4180 unsigned maCount = 0; // Largest number of multiple alternative constraints.
4181
4182 // Do a prepass over the constraints, canonicalizing them, and building up the
4183 // ConstraintOperands list.
4184 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
4185 unsigned ResNo = 0; // ResNo - The result number of the next output.
4186
4187 for (InlineAsm::ConstraintInfo &CI : IA->ParseConstraints()) {
4188 ConstraintOperands.emplace_back(std::move(CI));
4189 AsmOperandInfo &OpInfo = ConstraintOperands.back();
4190
4191 // Update multiple alternative constraint count.
4192 if (OpInfo.multipleAlternatives.size() > maCount)
4193 maCount = OpInfo.multipleAlternatives.size();
4194
4195 OpInfo.ConstraintVT = MVT::Other;
4196
4197 // Compute the value type for each operand.
4198 switch (OpInfo.Type) {
4199 case InlineAsm::isOutput:
4200 // Indirect outputs just consume an argument.
4201 if (OpInfo.isIndirect) {
4202 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
4203 break;
4204 }
4205
4206 // The return value of the call is this value. As such, there is no
4207 // corresponding argument.
4208 assert(!CS.getType()->isVoidTy() &&((!CS.getType()->isVoidTy() && "Bad inline asm!") ?
static_cast<void> (0) : __assert_fail ("!CS.getType()->isVoidTy() && \"Bad inline asm!\""
, "/build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/SelectionDAG/TargetLowering.cpp"
, 4209, __PRETTY_FUNCTION__))
4209 "Bad inline asm!")((!CS.getType()->isVoidTy() && "Bad inline asm!") ?
static_cast<void> (0) : __assert_fail ("!CS.getType()->isVoidTy() && \"Bad inline asm!\""
, "/build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/SelectionDAG/TargetLowering.cpp"
, 4209, __PRETTY_FUNCTION__))
;
4210 if (StructType *STy = dyn_cast<StructType>(CS.getType())) {
4211 OpInfo.ConstraintVT =
4212 getSimpleValueType(DL, STy->getElementType(ResNo));
4213 } else {
4214 assert(ResNo == 0 && "Asm only has one result!")((ResNo == 0 && "Asm only has one result!") ? static_cast
<void> (0) : __assert_fail ("ResNo == 0 && \"Asm only has one result!\""
, "/build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/SelectionDAG/TargetLowering.cpp"
, 4214, __PRETTY_FUNCTION__))
;
4215 OpInfo.ConstraintVT = getSimpleValueType(DL, CS.getType());
4216 }
4217 ++ResNo;
4218 break;
4219 case InlineAsm::isInput:
4220 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
4221 break;
4222 case InlineAsm::isClobber:
4223 // Nothing to do.
4224 break;
4225 }
4226
4227 if (OpInfo.CallOperandVal) {
4228 llvm::Type *OpTy = OpInfo.CallOperandVal->getType();
4229 if (OpInfo.isIndirect) {
4230 llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy);
4231 if (!PtrTy)
4232 report_fatal_error("Indirect operand for inline asm not a pointer!");
4233 OpTy = PtrTy->getElementType();
4234 }
4235
4236 // Look for vector wrapped in a struct. e.g. { <16 x i8> }.
4237 if (StructType *STy = dyn_cast<StructType>(OpTy))
4238 if (STy->getNumElements() == 1)
4239 OpTy = STy->getElementType(0);
4240
4241 // If OpTy is not a single value, it may be a struct/union that we
4242 // can tile with integers.
4243 if (!OpTy->isSingleValueType() && OpTy->isSized()) {
4244 unsigned BitSize = DL.getTypeSizeInBits(OpTy);
4245 switch (BitSize) {
4246 default: break;
4247 case 1:
4248 case 8:
4249 case 16:
4250 case 32:
4251 case 64:
4252 case 128:
4253 OpInfo.ConstraintVT =
4254 MVT::getVT(IntegerType::get(OpTy->getContext(), BitSize), true);
4255 break;
4256 }
4257 } else if (PointerType *PT = dyn_cast<PointerType>(OpTy)) {
4258 unsigned PtrSize = DL.getPointerSizeInBits(PT->getAddressSpace());
4259 OpInfo.ConstraintVT = MVT::getIntegerVT(PtrSize);
4260 } else {
4261 OpInfo.ConstraintVT = MVT::getVT(OpTy, true);
4262 }
4263 }
4264 }
4265
4266 // If we have multiple alternative constraints, select the best alternative.
4267 if (!ConstraintOperands.empty()) {
4268 if (maCount) {
4269 unsigned bestMAIndex = 0;
4270 int bestWeight = -1;
4271 // weight: -1 = invalid match, and 0 = so-so match to 5 = good match.
4272 int weight = -1;
4273 unsigned maIndex;
4274 // Compute the sums of the weights for each alternative, keeping track
4275 // of the best (highest weight) one so far.
4276 for (maIndex = 0; maIndex < maCount; ++maIndex) {
4277 int weightSum = 0;
4278 for (unsigned cIndex = 0, eIndex = ConstraintOperands.size();
4279 cIndex != eIndex; ++cIndex) {
4280 AsmOperandInfo &OpInfo = ConstraintOperands[cIndex];
4281 if (OpInfo.Type == InlineAsm::isClobber)
4282 continue;
4283
4284 // If this is an output operand with a matching input operand,
4285 // look up the matching input. If their types mismatch, e.g. one
4286 // is an integer, the other is floating point, or their sizes are
4287 // different, flag it as an maCantMatch.
4288 if (OpInfo.hasMatchingInput()) {
4289 AsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
4290 if (OpInfo.ConstraintVT != Input.ConstraintVT) {
4291 if ((OpInfo.ConstraintVT.isInteger() !=
4292 Input.ConstraintVT.isInteger()) ||
4293 (OpInfo.ConstraintVT.getSizeInBits() !=
4294 Input.ConstraintVT.getSizeInBits())) {
4295 weightSum = -1; // Can't match.
4296 break;
4297 }
4298 }
4299 }
4300 weight = getMultipleConstraintMatchWeight(OpInfo, maIndex);
4301 if (weight == -1) {
4302 weightSum = -1;
4303 break;
4304 }
4305 weightSum += weight;
4306 }
4307 // Update best.
4308 if (weightSum > bestWeight) {
4309 bestWeight = weightSum;
4310 bestMAIndex = maIndex;
4311 }
4312 }
4313
4314 // Now select chosen alternative in each constraint.
4315 for (unsigned cIndex = 0, eIndex = ConstraintOperands.size();
4316 cIndex != eIndex; ++cIndex) {
4317 AsmOperandInfo &cInfo = ConstraintOperands[cIndex];
4318 if (cInfo.Type == InlineAsm::isClobber)
4319 continue;
4320 cInfo.selectAlternative(bestMAIndex);
4321 }
4322 }
4323 }
4324
4325 // Check and hook up tied operands, choose constraint code to use.
4326 for (unsigned cIndex = 0, eIndex = ConstraintOperands.size();
4327 cIndex != eIndex; ++cIndex) {
4328 AsmOperandInfo &OpInfo = ConstraintOperands[cIndex];
4329
4330 // If this is an output operand with a matching input operand, look up the
4331 // matching input. If their types mismatch, e.g. one is an integer, the
4332 // other is floating point, or their sizes are different, flag it as an
4333 // error.
4334 if (OpInfo.hasMatchingInput()) {
4335 AsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
4336
4337 if (OpInfo.ConstraintVT != Input.ConstraintVT) {
4338 std::pair<unsigned, const TargetRegisterClass *> MatchRC =
4339 getRegForInlineAsmConstraint(TRI, OpInfo.ConstraintCode,
4340 OpInfo.ConstraintVT);
4341 std::pair<unsigned, const TargetRegisterClass *> InputRC =
4342 getRegForInlineAsmConstraint(TRI, Input.ConstraintCode,
4343 Input.ConstraintVT);
4344 if ((OpInfo.ConstraintVT.isInteger() !=
4345 Input.ConstraintVT.isInteger()) ||
4346 (MatchRC.second != InputRC.second)) {
4347 report_fatal_error("Unsupported asm: input constraint"
4348 " with a matching output constraint of"
4349 " incompatible type!");
4350 }
4351 }
4352 }
4353 }
4354
4355 return ConstraintOperands;
4356}
4357
4358/// Return an integer indicating how general CT is.
4359static unsigned getConstraintGenerality(TargetLowering::ConstraintType CT) {
4360 switch (CT) {
4361 case TargetLowering::C_Immediate:
4362 case TargetLowering::C_Other:
4363 case TargetLowering::C_Unknown:
4364 return 0;
4365 case TargetLowering::C_Register:
4366 return 1;
4367 case TargetLowering::C_RegisterClass:
4368 return 2;
4369 case TargetLowering::C_Memory:
4370 return 3;
4371 }
4372 llvm_unreachable("Invalid constraint type")::llvm::llvm_unreachable_internal("Invalid constraint type", "/build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/SelectionDAG/TargetLowering.cpp"
, 4372)
;
4373}
4374
4375/// Examine constraint type and operand type and determine a weight value.
4376/// This object must already have been set up with the operand type
4377/// and the current alternative constraint selected.
4378TargetLowering::ConstraintWeight
4379 TargetLowering::getMultipleConstraintMatchWeight(
4380 AsmOperandInfo &info, int maIndex) const {
4381 InlineAsm::ConstraintCodeVector *rCodes;
4382 if (maIndex >= (int)info.multipleAlternatives.size())
4383 rCodes = &info.Codes;
4384 else
4385 rCodes = &info.multipleAlternatives[maIndex].Codes;
4386 ConstraintWeight BestWeight = CW_Invalid;
4387
4388 // Loop over the options, keeping track of the most general one.
4389 for (unsigned i = 0, e = rCodes->size(); i != e; ++i) {
4390 ConstraintWeight weight =
4391 getSingleConstraintMatchWeight(info, (*rCodes)[i].c_str());
4392 if (weight > BestWeight)
4393 BestWeight = weight;
4394 }
4395
4396 return BestWeight;
4397}
4398
4399/// Examine constraint type and operand type and determine a weight value.
4400/// This object must already have been set up with the operand type
4401/// and the current alternative constraint selected.
4402TargetLowering::ConstraintWeight
4403 TargetLowering::getSingleConstraintMatchWeight(
4404 AsmOperandInfo &info, const char *constraint) const {
4405 ConstraintWeight weight = CW_Invalid;
4406 Value *CallOperandVal = info.CallOperandVal;
4407 // If we don't have a value, we can't do a match,
4408 // but allow it at the lowest weight.
4409 if (!CallOperandVal)
4410 return CW_Default;
4411 // Look at the constraint type.
4412 switch (*constraint) {
4413 case 'i': // immediate integer.
4414 case 'n': // immediate integer with a known value.
4415 if (isa<ConstantInt>(CallOperandVal))
4416 weight = CW_Constant;
4417 break;
4418 case 's': // non-explicit intregal immediate.
4419 if (isa<GlobalValue>(CallOperandVal))
4420 weight = CW_Constant;
4421 break;
4422 case 'E': // immediate float if host format.
4423 case 'F': // immediate float.
4424 if (isa<ConstantFP>(CallOperandVal))
4425 weight = CW_Constant;
4426 break;
4427 case '<': // memory operand with autodecrement.
4428 case '>': // memory operand with autoincrement.
4429 case 'm': // memory operand.
4430 case 'o': // offsettable memory operand
4431 case 'V': // non-offsettable memory operand
4432 weight = CW_Memory;
4433 break;
4434 case 'r': // general register.
4435 case 'g': // general register, memory operand or immediate integer.
4436 // note: Clang converts "g" to "imr".
4437 if (CallOperandVal->getType()->isIntegerTy())
4438 weight = CW_Register;
4439 break;
4440 case 'X': // any operand.
4441 default:
4442 weight = CW_Default;
4443 break;
4444 }
4445 return weight;
4446}
4447
4448/// If there are multiple different constraints that we could pick for this
4449/// operand (e.g. "imr") try to pick the 'best' one.
4450/// This is somewhat tricky: constraints fall into four classes:
4451/// Other -> immediates and magic values
4452/// Register -> one specific register
4453/// RegisterClass -> a group of regs
4454/// Memory -> memory
4455/// Ideally, we would pick the most specific constraint possible: if we have
4456/// something that fits into a register, we would pick it. The problem here
4457/// is that if we have something that could either be in a register or in
4458/// memory that use of the register could cause selection of *other*
4459/// operands to fail: they might only succeed if we pick memory. Because of
4460/// this the heuristic we use is:
4461///
4462/// 1) If there is an 'other' constraint, and if the operand is valid for
4463/// that constraint, use it. This makes us take advantage of 'i'
4464/// constraints when available.
4465/// 2) Otherwise, pick the most general constraint present. This prefers
4466/// 'm' over 'r', for example.
4467///
4468static void ChooseConstraint(TargetLowering::AsmOperandInfo &OpInfo,
4469 const TargetLowering &TLI,
4470 SDValue Op, SelectionDAG *DAG) {
4471 assert(OpInfo.Codes.size() > 1 && "Doesn't have multiple constraint options")((OpInfo.Codes.size() > 1 && "Doesn't have multiple constraint options"
) ? static_cast<void> (0) : __assert_fail ("OpInfo.Codes.size() > 1 && \"Doesn't have multiple constraint options\""
, "/build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/SelectionDAG/TargetLowering.cpp"
, 4471, __PRETTY_FUNCTION__))
;
4472 unsigned BestIdx = 0;
4473 TargetLowering::ConstraintType BestType = TargetLowering::C_Unknown;
4474 int BestGenerality = -1;
4475
4476 // Loop over the options, keeping track of the most general one.
4477 for (unsigned i = 0, e = OpInfo.Codes.size(); i != e; ++i) {
4478 TargetLowering::ConstraintType CType =
4479 TLI.getConstraintType(OpInfo.Codes[i]);
4480
4481 // If this is an 'other' or 'immediate' constraint, see if the operand is
4482 // valid for it. For example, on X86 we might have an 'rI' constraint. If
4483 // the operand is an integer in the range [0..31] we want to use I (saving a
4484 // load of a register), otherwise we must use 'r'.
4485 if ((CType == TargetLowering::C_Other ||
4486 CType == TargetLowering::C_Immediate) && Op.getNode()) {
4487 assert(OpInfo.Codes[i].size() == 1 &&((OpInfo.Codes[i].size() == 1 && "Unhandled multi-letter 'other' constraint"
) ? static_cast<void> (0) : __assert_fail ("OpInfo.Codes[i].size() == 1 && \"Unhandled multi-letter 'other' constraint\""
, "/build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/SelectionDAG/TargetLowering.cpp"
, 4488, __PRETTY_FUNCTION__))
4488 "Unhandled multi-letter 'other' constraint")((OpInfo.Codes[i].size() == 1 && "Unhandled multi-letter 'other' constraint"
) ? static_cast<void> (0) : __assert_fail ("OpInfo.Codes[i].size() == 1 && \"Unhandled multi-letter 'other' constraint\""
, "/build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/SelectionDAG/TargetLowering.cpp"
, 4488, __PRETTY_FUNCTION__))
;
4489 std::vector<SDValue> ResultOps;
4490 TLI.LowerAsmOperandForConstraint(Op, OpInfo.Codes[i],
4491 ResultOps, *DAG);
4492 if (!ResultOps.empty()) {
4493 BestType = CType;
4494 BestIdx = i;
4495 break;
4496 }
4497 }
4498
4499 // Things with matching constraints can only be registers, per gcc
4500 // documentation. This mainly affects "g" constraints.
4501 if (CType == TargetLowering::C_Memory && OpInfo.hasMatchingInput())
4502 continue;
4503
4504 // This constraint letter is more general than the previous one, use it.
4505 int Generality = getConstraintGenerality(CType);
4506 if (Generality > BestGenerality) {
4507 BestType = CType;
4508 BestIdx = i;
4509 BestGenerality = Generality;
4510 }
4511 }
4512
4513 OpInfo.ConstraintCode = OpInfo.Codes[BestIdx];
4514 OpInfo.ConstraintType = BestType;
4515}
4516
4517/// Determines the constraint code and constraint type to use for the specific
4518/// AsmOperandInfo, setting OpInfo.ConstraintCode and OpInfo.ConstraintType.
4519void TargetLowering::ComputeConstraintToUse(AsmOperandInfo &OpInfo,
4520 SDValue Op,
4521 SelectionDAG *DAG) const {
4522 assert(!OpInfo.Codes.empty() && "Must have at least one constraint")((!OpInfo.Codes.empty() && "Must have at least one constraint"
) ? static_cast<void> (0) : __assert_fail ("!OpInfo.Codes.empty() && \"Must have at least one constraint\""
, "/build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/SelectionDAG/TargetLowering.cpp"
, 4522, __PRETTY_FUNCTION__))
;
4523
4524 // Single-letter constraints ('r') are very common.
4525 if (OpInfo.Codes.size() == 1) {
4526 OpInfo.ConstraintCode = OpInfo.Codes[0];
4527 OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode);
4528 } else {
4529 ChooseConstraint(OpInfo, *this, Op, DAG);
4530 }
4531
4532 // 'X' matches anything.
4533 if (OpInfo.ConstraintCode == "X" && OpInfo.CallOperandVal) {
4534 // Labels and constants are handled elsewhere ('X' is the only thing
4535 // that matches labels). For Functions, the type here is the type of
4536 // the result, which is not what we want to look at; leave them alone.
4537 Value *v = OpInfo.CallOperandVal;
4538 if (isa<BasicBlock>(v) || isa<ConstantInt>(v) || isa<Function>(v)) {
4539 OpInfo.CallOperandVal = v;
4540 return;
4541 }
4542
4543 if (Op.getNode() && Op.getOpcode() == ISD::TargetBlockAddress)
4544 return;
4545
4546 // Otherwise, try to resolve it to something we know about by looking at
4547 // the actual operand type.
4548 if (const char *Repl = LowerXConstraint(OpInfo.ConstraintVT)) {
4549 OpInfo.ConstraintCode = Repl;
4550 OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode);
4551 }
4552 }
4553}
4554
4555/// Given an exact SDIV by a constant, create a multiplication
4556/// with the multiplicative inverse of the constant.
4557static SDValue BuildExactSDIV(const TargetLowering &TLI, SDNode *N,
4558 const SDLoc &dl, SelectionDAG &DAG,
4559 SmallVectorImpl<SDNode *> &Created) {
4560 SDValue Op0 = N->getOperand(0);
4561 SDValue Op1 = N->getOperand(1);
4562 EVT VT = N->getValueType(0);
4563 EVT SVT = VT.getScalarType();
4564 EVT ShVT = TLI.getShiftAmountTy(VT, DAG.getDataLayout());
4565 EVT ShSVT = ShVT.getScalarType();
4566
4567 bool UseSRA = false;
4568 SmallVector<SDValue, 16> Shifts, Factors;
4569
4570 auto BuildSDIVPattern = [&](ConstantSDNode *C) {
4571 if (C->isNullValue())
4572 return false;
4573 APInt Divisor = C->getAPIntValue();
4574 unsigned Shift = Divisor.countTrailingZeros();
4575 if (Shift) {
4576 Divisor.ashrInPlace(Shift);
4577 UseSRA = true;
4578 }
4579 // Calculate the multiplicative inverse, using Newton's method.
4580 APInt t;
4581 APInt Factor = Divisor;
4582 while ((t = Divisor * Factor) != 1)
4583 Factor *= APInt(Divisor.getBitWidth(), 2) - t;
4584 Shifts.push_back(DAG.getConstant(Shift, dl, ShSVT));
4585 Factors.push_back(DAG.getConstant(Factor, dl, SVT));
4586 return true;
4587 };
4588
4589 // Collect all magic values from the build vector.
4590 if (!ISD::matchUnaryPredicate(Op1, BuildSDIVPattern))
4591 return SDValue();
4592
4593 SDValue Shift, Factor;
4594 if (VT.isVector()) {
4595 Shift = DAG.getBuildVector(ShVT, dl, Shifts);
4596 Factor = DAG.getBuildVector(VT, dl, Factors);
4597 } else {
4598 Shift = Shifts[0];
4599 Factor = Factors[0];
4600 }
4601
4602 SDValue Res = Op0;
4603
4604 // Shift the value upfront if it is even, so the LSB is one.
4605 if (UseSRA) {
4606 // TODO: For UDIV use SRL instead of SRA.
4607 SDNodeFlags Flags;
4608 Flags.setExact(true);
4609 Res = DAG.getNode(ISD::SRA, dl, VT, Res, Shift, Flags);
4610 Created.push_back(Res.getNode());
4611 }
4612
4613 return DAG.getNode(ISD::MUL, dl, VT, Res, Factor);
4614}
4615
4616SDValue TargetLowering::BuildSDIVPow2(SDNode *N, const APInt &Divisor,
4617 SelectionDAG &DAG,
4618 SmallVectorImpl<SDNode *> &Created) const {
4619 AttributeList Attr = DAG.getMachineFunction().getFunction().getAttributes();
4620 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4621 if (TLI.isIntDivCheap(N->getValueType(0), Attr))
4622 return SDValue(N, 0); // Lower SDIV as SDIV
4623 return SDValue();
4624}
4625
4626/// Given an ISD::SDIV node expressing a divide by constant,
4627/// return a DAG expression to select that will generate the same value by
4628/// multiplying by a magic number.
4629/// Ref: "Hacker's Delight" or "The PowerPC Compiler Writer's Guide".
4630SDValue TargetLowering::BuildSDIV(SDNode *N, SelectionDAG &DAG,
4631 bool IsAfterLegalization,
4632 SmallVectorImpl<SDNode *> &Created) const {
4633 SDLoc dl(N);
4634 EVT VT = N->getValueType(0);
4635 EVT SVT = VT.getScalarType();
4636 EVT ShVT = getShiftAmountTy(VT, DAG.getDataLayout());
4637 EVT ShSVT = ShVT.getScalarType();
4638 unsigned EltBits = VT.getScalarSizeInBits();
4639
4640 // Check to see if we can do this.
4641 // FIXME: We should be more aggressive here.
4642 if (!isTypeLegal(VT))
4643 return SDValue();
4644
4645 // If the sdiv has an 'exact' bit we can use a simpler lowering.
4646 if (N->getFlags().hasExact())
4647 return BuildExactSDIV(*this, N, dl, DAG, Created);
4648
4649 SmallVector<SDValue, 16> MagicFactors, Factors, Shifts, ShiftMasks;
4650
4651 auto BuildSDIVPattern = [&](ConstantSDNode *C) {
4652 if (C->isNullValue())
4653 return false;
4654
4655 const APInt &Divisor = C->getAPIntValue();
4656 APInt::ms magics = Divisor.magic();
4657 int NumeratorFactor = 0;
4658 int ShiftMask = -1;
4659
4660 if (Divisor.isOneValue() || Divisor.isAllOnesValue()) {
4661 // If d is +1/-1, we just multiply the numerator by +1/-1.
4662 NumeratorFactor = Divisor.getSExtValue();
4663 magics.m = 0;
4664 magics.s = 0;
4665 ShiftMask = 0;
4666 } else if (Divisor.isStrictlyPositive() && magics.m.isNegative()) {
4667 // If d > 0 and m < 0, add the numerator.
4668 NumeratorFactor = 1;
4669 } else if (Divisor.isNegative() && magics.m.isStrictlyPositive()) {
4670 // If d < 0 and m > 0, subtract the numerator.
4671 NumeratorFactor = -1;
4672 }
4673
4674 MagicFactors.push_back(DAG.getConstant(magics.m, dl, SVT));
4675 Factors.push_back(DAG.getConstant(NumeratorFactor, dl, SVT));
4676 Shifts.push_back(DAG.getConstant(magics.s, dl, ShSVT));
4677 ShiftMasks.push_back(DAG.getConstant(ShiftMask, dl, SVT));
4678 return true;
4679 };
4680
4681 SDValue N0 = N->getOperand(0);
4682 SDValue N1 = N->getOperand(1);
4683
4684 // Collect the shifts / magic values from each element.
4685 if (!ISD::matchUnaryPredicate(N1, BuildSDIVPattern))
4686 return SDValue();
4687
4688 SDValue MagicFactor, Factor, Shift, ShiftMask;
4689 if (VT.isVector()) {
4690 MagicFactor = DAG.getBuildVector(VT, dl, MagicFactors);
4691 Factor = DAG.getBuildVector(VT, dl, Factors);
4692 Shift = DAG.getBuildVector(ShVT, dl, Shifts);
4693 ShiftMask = DAG.getBuildVector(VT, dl, ShiftMasks);
4694 } else {
4695 MagicFactor = MagicFactors[0];
4696 Factor = Factors[0];
4697 Shift = Shifts[0];
4698 ShiftMask = ShiftMasks[0];
4699 }
4700
4701 // Multiply the numerator (operand 0) by the magic value.
4702 // FIXME: We should support doing a MUL in a wider type.
4703 SDValue Q;
4704 if (IsAfterLegalization ? isOperationLegal(ISD::MULHS, VT)
4705 : isOperationLegalOrCustom(ISD::MULHS, VT))
4706 Q = DAG.getNode(ISD::MULHS, dl, VT, N0, MagicFactor);
4707 else if (IsAfterLegalization ? isOperationLegal(ISD::SMUL_LOHI, VT)
4708 : isOperationLegalOrCustom(ISD::SMUL_LOHI, VT)) {
4709 SDValue LoHi =
4710 DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(VT, VT), N0, MagicFactor);
4711 Q = SDValue(LoHi.getNode(), 1);
4712 } else
4713 return SDValue(); // No mulhs or equivalent.
4714 Created.push_back(Q.getNode());
4715
4716 // (Optionally) Add/subtract the numerator using Factor.
4717 Factor = DAG.getNode(ISD::MUL, dl, VT, N0, Factor);
4718 Created.push_back(Factor.getNode());
4719 Q = DAG.getNode(ISD::ADD, dl, VT, Q, Factor);
4720 Created.push_back(Q.getNode());
4721
4722 // Shift right algebraic by shift value.
4723 Q = DAG.getNode(ISD::SRA, dl, VT, Q, Shift);
4724 Created.push_back(Q.getNode());
4725
4726 // Extract the sign bit, mask it and add it to the quotient.
4727 SDValue SignShift = DAG.getConstant(EltBits - 1, dl, ShVT);
4728 SDValue T = DAG.getNode(ISD::SRL, dl, VT, Q, SignShift);
4729 Created.push_back(T.getNode());
4730 T = DAG.getNode(ISD::AND, dl, VT, T, ShiftMask);
4731 Created.push_back(T.getNode());
4732 return DAG.getNode(ISD::ADD, dl, VT, Q, T);
4733}
4734
4735/// Given an ISD::UDIV node expressing a divide by constant,
4736/// return a DAG expression to select that will generate the same value by
4737/// multiplying by a magic number.
4738/// Ref: "Hacker's Delight" or "The PowerPC Compiler Writer's Guide".
4739SDValue TargetLowering::BuildUDIV(SDNode *N, SelectionDAG &DAG,
4740 bool IsAfterLegalization,
4741 SmallVectorImpl<SDNode *> &Created) const {
4742 SDLoc dl(N);
4743 EVT VT = N->getValueType(0);
4744 EVT SVT = VT.getScalarType();
4745 EVT ShVT = getShiftAmountTy(VT, DAG.getDataLayout());
4746 EVT ShSVT = ShVT.getScalarType();
4747 unsigned EltBits = VT.getScalarSizeInBits();
4748
4749 // Check to see if we can do this.
4750 // FIXME: We should be more aggressive here.
4751 if (!isTypeLegal(VT))
4752 return SDValue();
4753
4754 bool UseNPQ = false;
4755 SmallVector<SDValue, 16> PreShifts, PostShifts, MagicFactors, NPQFactors;
4756
4757 auto BuildUDIVPattern = [&](ConstantSDNode *C) {
4758 if (C->isNullValue())
4759 return false;
4760 // FIXME: We should use a narrower constant when the upper
4761 // bits are known to be zero.
4762 APInt Divisor = C->getAPIntValue();
4763 APInt::mu magics = Divisor.magicu();
4764 unsigned PreShift = 0, PostShift = 0;
4765
4766 // If the divisor is even, we can avoid using the expensive fixup by
4767 // shifting the divided value upfront.
4768 if (magics.a != 0 && !Divisor[0]) {
4769 PreShift = Divisor.countTrailingZeros();
4770 // Get magic number for the shifted divisor.
4771 magics = Divisor.lshr(PreShift).magicu(PreShift);
4772 assert(magics.a == 0 && "Should use cheap fixup now")((magics.a == 0 && "Should use cheap fixup now") ? static_cast
<void> (0) : __assert_fail ("magics.a == 0 && \"Should use cheap fixup now\""
, "/build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/SelectionDAG/TargetLowering.cpp"
, 4772, __PRETTY_FUNCTION__))
;
4773 }
4774
4775 APInt Magic = magics.m;
4776
4777 unsigned SelNPQ;
4778 if (magics.a == 0 || Divisor.isOneValue()) {
4779 assert(magics.s < Divisor.getBitWidth() &&((magics.s < Divisor.getBitWidth() && "We shouldn't generate an undefined shift!"
) ? static_cast<void> (0) : __assert_fail ("magics.s < Divisor.getBitWidth() && \"We shouldn't generate an undefined shift!\""
, "/build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/SelectionDAG/TargetLowering.cpp"
, 4780, __PRETTY_FUNCTION__))
4780 "We shouldn't generate an undefined shift!")((magics.s < Divisor.getBitWidth() && "We shouldn't generate an undefined shift!"
) ? static_cast<void> (0) : __assert_fail ("magics.s < Divisor.getBitWidth() && \"We shouldn't generate an undefined shift!\""
, "/build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/SelectionDAG/TargetLowering.cpp"
, 4780, __PRETTY_FUNCTION__))
;
4781 PostShift = magics.s;
4782 SelNPQ = false;
4783 } else {
4784 PostShift = magics.s - 1;
4785 SelNPQ = true;
4786 }
4787
4788 PreShifts.push_back(DAG.getConstant(PreShift, dl, ShSVT));
4789 MagicFactors.push_back(DAG.getConstant(Magic, dl, SVT));
4790 NPQFactors.push_back(
4791 DAG.getConstant(SelNPQ ? APInt::getOneBitSet(EltBits, EltBits - 1)
4792 : APInt::getNullValue(EltBits),
4793 dl, SVT));
4794 PostShifts.push_back(DAG.getConstant(PostShift, dl, ShSVT));
4795 UseNPQ |= SelNPQ;
4796 return true;
4797 };
4798
4799 SDValue N0 = N->getOperand(0);
4800 SDValue N1 = N->getOperand(1);
4801
4802 // Collect the shifts/magic values from each element.
4803 if (!ISD::matchUnaryPredicate(N1, BuildUDIVPattern))
4804 return SDValue();
4805
4806 SDValue PreShift, PostShift, MagicFactor, NPQFactor;
4807 if (VT.isVector()) {
4808 PreShift = DAG.getBuildVector(ShVT, dl, PreShifts);
4809 MagicFactor = DAG.getBuildVector(VT, dl, MagicFactors);
4810 NPQFactor = DAG.getBuildVector(VT, dl, NPQFactors);
4811 PostShift = DAG.getBuildVector(ShVT, dl, PostShifts);
4812 } else {
4813 PreShift = PreShifts[0];
4814 MagicFactor = MagicFactors[0];
4815 PostShift = PostShifts[0];
4816 }
4817
4818 SDValue Q = N0;
4819 Q = DAG.getNode(ISD::SRL, dl, VT, Q, PreShift);
4820 Created.push_back(Q.getNode());
4821
4822 // FIXME: We should support doing a MUL in a wider type.
4823 auto GetMULHU = [&](SDValue X, SDValue Y) {
4824 if (IsAfterLegalization ? isOperationLegal(ISD::MULHU, VT)
4825 : isOperationLegalOrCustom(ISD::MULHU, VT))
4826 return DAG.getNode(ISD::MULHU, dl, VT, X, Y);
4827 if (IsAfterLegalization ? isOperationLegal(ISD::UMUL_LOHI, VT)
4828 : isOperationLegalOrCustom(ISD::UMUL_LOHI, VT)) {
4829 SDValue LoHi =
4830 DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(VT, VT), X, Y);
4831 return SDValue(LoHi.getNode(), 1);
4832 }
4833 return SDValue(); // No mulhu or equivalent
4834 };
4835
4836 // Multiply the numerator (operand 0) by the magic value.
4837 Q = GetMULHU(Q, MagicFactor);
4838 if (!Q)
4839 return SDValue();
4840
4841 Created.push_back(Q.getNode());
4842
4843 if (UseNPQ) {
4844 SDValue NPQ = DAG.getNode(ISD::SUB, dl, VT, N0, Q);
4845 Created.push_back(NPQ.getNode());
4846
4847 // For vectors we might have a mix of non-NPQ/NPQ paths, so use
4848 // MULHU to act as a SRL-by-1 for NPQ, else multiply by zero.
4849 if (VT.isVector())
4850 NPQ = GetMULHU(NPQ, NPQFactor);
4851 else
4852 NPQ = DAG.getNode(ISD::SRL, dl, VT, NPQ, DAG.getConstant(1, dl, ShVT));
4853
4854 Created.push_back(NPQ.getNode());
4855
4856 Q = DAG.getNode(ISD::ADD, dl, VT, NPQ, Q);
4857 Created.push_back(Q.getNode());
4858 }
4859
4860 Q = DAG.getNode(ISD::SRL, dl, VT, Q, PostShift);
4861 Created.push_back(Q.getNode());
4862
4863 SDValue One = DAG.getConstant(1, dl, VT);
4864 SDValue IsOne = DAG.getSetCC(dl, VT, N1, One, ISD::SETEQ);
4865 return DAG.getSelect(dl, VT, IsOne, N0, Q);
4866}
4867
4868/// If all values in Values that *don't* match the predicate are same 'splat'
4869/// value, then replace all values with that splat value.
4870/// Else, if AlternativeReplacement was provided, then replace all values that
4871/// do match predicate with AlternativeReplacement value.
4872static void
4873turnVectorIntoSplatVector(MutableArrayRef<SDValue> Values,
4874 std::function<bool(SDValue)> Predicate,
4875 SDValue AlternativeReplacement = SDValue()) {
4876 SDValue Replacement;
4877 // Is there a value for which the Predicate does *NOT* match? What is it?
4878 auto SplatValue = llvm::find_if_not(Values, Predicate);
4879 if (SplatValue != Values.end()) {
4880 // Does Values consist only of SplatValue's and values matching Predicate?
4881 if (llvm::all_of(Values, [Predicate, SplatValue](SDValue Value) {
4882 return Value == *SplatValue || Predicate(Value);
4883 })) // Then we shall replace values matching predicate with SplatValue.
4884 Replacement = *SplatValue;
4885 }
4886 if (!Replacement) {
4887 // Oops, we did not find the "baseline" splat value.
4888 if (!AlternativeReplacement)
4889 return; // Nothing to do.
4890 // Let's replace with provided value then.
4891 Replacement = AlternativeReplacement;
4892 }
4893 std::replace_if(Values.begin(), Values.end(), Predicate, Replacement);
4894}
4895
4896/// Given an ISD::UREM used only by an ISD::SETEQ or ISD::SETNE
4897/// where the divisor is constant and the comparison target is zero,
4898/// return a DAG expression that will generate the same comparison result
4899/// using only multiplications, additions and shifts/rotations.
4900/// Ref: "Hacker's Delight" 10-17.
4901SDValue TargetLowering::buildUREMEqFold(EVT SETCCVT, SDValue REMNode,
4902 SDValue CompTargetNode,
4903 ISD::CondCode Cond,
4904 DAGCombinerInfo &DCI,
4905 const SDLoc &DL) const {
4906 SmallVector<SDNode *, 2> Built;
4907 if (SDValue Folded = prepareUREMEqFold(SETCCVT, REMNode, CompTargetNode, Cond,
4908 DCI, DL, Built)) {
4909 for (SDNode *N : Built)
4910 DCI.AddToWorklist(N);
4911 return Folded;
4912 }
4913
4914 return SDValue();
4915}
4916
4917SDValue
4918TargetLowering::prepareUREMEqFold(EVT SETCCVT, SDValue REMNode,
4919 SDValue CompTargetNode, ISD::CondCode Cond,
4920 DAGCombinerInfo &DCI, const SDLoc &DL,
4921 SmallVectorImpl<SDNode *> &Created) const {
4922 // fold (seteq/ne (urem N, D), 0) -> (setule/ugt (rotr (mul N, P), K), Q)
4923 // - D must be constant, with D = D0 * 2^K where D0 is odd
4924 // - P is the multiplicative inverse of D0 modulo 2^W
4925 // - Q = floor(((2^W) - 1) / D)
4926 // where W is the width of the common type of N and D.
4927 assert((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&(((Cond == ISD::SETEQ || Cond == ISD::SETNE) && "Only applicable for (in)equality comparisons."
) ? static_cast<void> (0) : __assert_fail ("(Cond == ISD::SETEQ || Cond == ISD::SETNE) && \"Only applicable for (in)equality comparisons.\""
, "/build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/SelectionDAG/TargetLowering.cpp"
, 4928, __PRETTY_FUNCTION__))
4928 "Only applicable for (in)equality comparisons.")(((Cond == ISD::SETEQ || Cond == ISD::SETNE) && "Only applicable for (in)equality comparisons."
) ? static_cast<void> (0) : __assert_fail ("(Cond == ISD::SETEQ || Cond == ISD::SETNE) && \"Only applicable for (in)equality comparisons.\""
, "/build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/SelectionDAG/TargetLowering.cpp"
, 4928, __PRETTY_FUNCTION__))
;
4929
4930 SelectionDAG &DAG = DCI.DAG;
4931
4932 EVT VT = REMNode.getValueType();
4933 EVT SVT = VT.getScalarType();
4934 EVT ShVT = getShiftAmountTy(VT, DAG.getDataLayout());
4935 EVT ShSVT = ShVT.getScalarType();
4936
4937 // If MUL is unavailable, we cannot proceed in any case.
4938 if (!isOperationLegalOrCustom(ISD::MUL, VT))
4939 return SDValue();
4940
4941 // TODO: Could support comparing with non-zero too.
4942 ConstantSDNode *CompTarget = isConstOrConstSplat(CompTargetNode);
4943 if (!CompTarget || !CompTarget->isNullValue())
4944 return SDValue();
4945
4946 bool HadOneDivisor = false;
4947 bool AllDivisorsAreOnes = true;
4948 bool HadEvenDivisor = false;
4949 bool AllDivisorsArePowerOfTwo = true;
4950 SmallVector<SDValue, 16> PAmts, KAmts, QAmts;
4951
4952 auto BuildUREMPattern = [&](ConstantSDNode *C) {
4953 // Division by 0 is UB. Leave it to be constant-folded elsewhere.
4954 if (C->isNullValue())
4955 return false;
4956
4957 const APInt &D = C->getAPIntValue();
4958 // If all divisors are ones, we will prefer to avoid the fold.
4959 HadOneDivisor |= D.isOneValue();
4960 AllDivisorsAreOnes &= D.isOneValue();
4961
4962 // Decompose D into D0 * 2^K
4963 unsigned K = D.countTrailingZeros();
4964 assert((!D.isOneValue() || (K == 0)) && "For divisor '1' we won't rotate.")(((!D.isOneValue() || (K == 0)) && "For divisor '1' we won't rotate."
) ? static_cast<void> (0) : __assert_fail ("(!D.isOneValue() || (K == 0)) && \"For divisor '1' we won't rotate.\""
, "/build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/SelectionDAG/TargetLowering.cpp"
, 4964, __PRETTY_FUNCTION__))
;
4965 APInt D0 = D.lshr(K);
4966
4967 // D is even if it has trailing zeros.
4968 HadEvenDivisor |= (K != 0);
4969 // D is a power-of-two if D0 is one.
4970 // If all divisors are power-of-two, we will prefer to avoid the fold.
4971 AllDivisorsArePowerOfTwo &= D0.isOneValue();
4972
4973 // P = inv(D0, 2^W)
4974 // 2^W requires W + 1 bits, so we have to extend and then truncate.
4975 unsigned W = D.getBitWidth();
4976 APInt P = D0.zext(W + 1)
4977 .multiplicativeInverse(APInt::getSignedMinValue(W + 1))
4978 .trunc(W);
4979 assert(!P.isNullValue() && "No multiplicative inverse!")((!P.isNullValue() && "No multiplicative inverse!") ?
static_cast<void> (0) : __assert_fail ("!P.isNullValue() && \"No multiplicative inverse!\""
, "/build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/SelectionDAG/TargetLowering.cpp"
, 4979, __PRETTY_FUNCTION__))
; // unreachable
4980 assert((D0 * P).isOneValue() && "Multiplicative inverse sanity check.")(((D0 * P).isOneValue() && "Multiplicative inverse sanity check."
) ? static_cast<void> (0) : __assert_fail ("(D0 * P).isOneValue() && \"Multiplicative inverse sanity check.\""
, "/build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/SelectionDAG/TargetLowering.cpp"
, 4980, __PRETTY_FUNCTION__))
;
4981
4982 // Q = floor((2^W - 1) / D)
4983 APInt Q = APInt::getAllOnesValue(W).udiv(D);
4984
4985 assert(APInt::getAllOnesValue(ShSVT.getSizeInBits()).ugt(K) &&((APInt::getAllOnesValue(ShSVT.getSizeInBits()).ugt(K) &&
"We are expecting that K is always less than all-ones for ShSVT"
) ? static_cast<void> (0) : __assert_fail ("APInt::getAllOnesValue(ShSVT.getSizeInBits()).ugt(K) && \"We are expecting that K is always less than all-ones for ShSVT\""
, "/build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/SelectionDAG/TargetLowering.cpp"
, 4986, __PRETTY_FUNCTION__))
4986 "We are expecting that K is always less than all-ones for ShSVT")((APInt::getAllOnesValue(ShSVT.getSizeInBits()).ugt(K) &&
"We are expecting that K is always less than all-ones for ShSVT"
) ? static_cast<void> (0) : __assert_fail ("APInt::getAllOnesValue(ShSVT.getSizeInBits()).ugt(K) && \"We are expecting that K is always less than all-ones for ShSVT\""
, "/build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/SelectionDAG/TargetLowering.cpp"
, 4986, __PRETTY_FUNCTION__))
;
4987
4988 // If the divisor is 1 the result can be constant-folded.
4989 if (D.isOneValue()) {
4990 // Set P and K amount to a bogus values so we can try to splat them.
4991 P = 0;
4992 K = -1;
4993 assert(Q.isAllOnesValue() &&((Q.isAllOnesValue() && "Expecting all-ones comparison for one divisor"
) ? static_cast<void> (0) : __assert_fail ("Q.isAllOnesValue() && \"Expecting all-ones comparison for one divisor\""
, "/build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/SelectionDAG/TargetLowering.cpp"
, 4994, __PRETTY_FUNCTION__))
4994 "Expecting all-ones comparison for one divisor")((Q.isAllOnesValue() && "Expecting all-ones comparison for one divisor"
) ? static_cast<void> (0) : __assert_fail ("Q.isAllOnesValue() && \"Expecting all-ones comparison for one divisor\""
, "/build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/SelectionDAG/TargetLowering.cpp"
, 4994, __PRETTY_FUNCTION__))
;
4995 }
4996
4997 PAmts.push_back(DAG.getConstant(P, DL, SVT));
4998 KAmts.push_back(
4999 DAG.getConstant(APInt(ShSVT.getSizeInBits(), K), DL, ShSVT));
5000 QAmts.push_back(DAG.getConstant(Q, DL, SVT));
5001 return true;
5002 };
5003
5004 SDValue N = REMNode.getOperand(0);
5005 SDValue D = REMNode.getOperand(1);
5006
5007 // Collect the values from each element.
5008 if (!ISD::matchUnaryPredicate(D, BuildUREMPattern))
5009 return SDValue();
5010
5011 // If this is a urem by a one, avoid the fold since it can be constant-folded.
5012 if (AllDivisorsAreOnes)
5013 return SDValue();
5014
5015 // If this is a urem by a powers-of-two, avoid the fold since it can be
5016 // best implemented as a bit test.
5017 if (AllDivisorsArePowerOfTwo)
5018 return SDValue();
5019
5020 SDValue PVal, KVal, QVal;
5021 if (VT.isVector()) {
5022 if (HadOneDivisor) {
5023 // Try to turn PAmts into a splat, since we don't care about the values
5024 // that are currently '0'. If we can't, just keep '0'`s.
5025 turnVectorIntoSplatVector(PAmts, isNullConstant);
5026 // Try to turn KAmts into a splat, since we don't care about the values
5027 // that are currently '-1'. If we can't, change them to '0'`s.
5028 turnVectorIntoSplatVector(KAmts, isAllOnesConstant,
5029 DAG.getConstant(0, DL, ShSVT));
5030 }
5031
5032 PVal = DAG.getBuildVector(VT, DL, PAmts);
5033 KVal = DAG.getBuildVector(ShVT, DL, KAmts);
5034 QVal = DAG.getBuildVector(VT, DL, QAmts);
5035 } else {
5036 PVal = PAmts[0];
5037 KVal = KAmts[0];
5038 QVal = QAmts[0];
5039 }
5040
5041 // (mul N, P)
5042 SDValue Op0 = DAG.getNode(ISD::MUL, DL, VT, N, PVal);
5043 Created.push_back(Op0.getNode());
5044
5045 // Rotate right only if any divisor was even. We avoid rotates for all-odd
5046 // divisors as a performance improvement, since rotating by 0 is a no-op.
5047 if (HadEvenDivisor) {
5048 // We need ROTR to do this.
5049 if (!isOperationLegalOrCustom(ISD::ROTR, VT))
5050 return SDValue();
5051 SDNodeFlags Flags;
5052 Flags.setExact(true);
5053 // UREM: (rotr (mul N, P), K)
5054 Op0 = DAG.getNode(ISD::ROTR, DL, VT, Op0, KVal, Flags);
5055 Created.push_back(Op0.getNode());
5056 }
5057
5058 // UREM: (setule/setugt (rotr (mul N, P), K), Q)
5059 return DAG.getSetCC(DL, SETCCVT, Op0, QVal,
5060 ((Cond == ISD::SETEQ) ? ISD::SETULE : ISD::SETUGT));
5061}
5062
5063/// Given an ISD::SREM used only by an ISD::SETEQ or ISD::SETNE
5064/// where the divisor is constant and the comparison target is zero,
5065/// return a DAG expression that will generate the same comparison result
5066/// using only multiplications, additions and shifts/rotations.
5067/// Ref: "Hacker's Delight" 10-17.
5068SDValue TargetLowering::buildSREMEqFold(EVT SETCCVT, SDValue REMNode,
5069 SDValue CompTargetNode,
5070 ISD::CondCode Cond,
5071 DAGCombinerInfo &DCI,
5072 const SDLoc &DL) const {
5073 SmallVector<SDNode *, 7> Built;
5074 if (SDValue Folded = prepareSREMEqFold(SETCCVT, REMNode, CompTargetNode, Cond,
5075 DCI, DL, Built)) {
5076 assert(Built.size() <= 7 && "Max size prediction failed.")((Built.size() <= 7 && "Max size prediction failed."
) ? static_cast<void> (0) : __assert_fail ("Built.size() <= 7 && \"Max size prediction failed.\""
, "/build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/SelectionDAG/TargetLowering.cpp"
, 5076, __PRETTY_FUNCTION__))
;
5077 for (SDNode *N : Built)
5078 DCI.AddToWorklist(N);
5079 return Folded;
5080 }
5081
5082 return SDValue();
5083}
5084
5085SDValue
5086TargetLowering::prepareSREMEqFold(EVT SETCCVT, SDValue REMNode,
5087 SDValue CompTargetNode, ISD::CondCode Cond,
5088 DAGCombinerInfo &DCI, const SDLoc &DL,
5089 SmallVectorImpl<SDNode *> &Created) const {
5090 // Fold:
5091 // (seteq/ne (srem N, D), 0)
5092 // To:
5093 // (setule/ugt (rotr (add (mul N, P), A), K), Q)
5094 //
5095 // - D must be constant, with D = D0 * 2^K where D0 is odd
5096 // - P is the multiplicative inverse of D0 modulo 2^W
5097 // - A = bitwiseand(floor((2^(W - 1) - 1) / D0), (-(2^k)))
5098 // - Q = floor((2 * A) / (2^K))
5099 // where W is the width of the common type of N and D.
5100 assert((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&(((Cond == ISD::SETEQ || Cond == ISD::SETNE) && "Only applicable for (in)equality comparisons."
) ? static_cast<void> (0) : __assert_fail ("(Cond == ISD::SETEQ || Cond == ISD::SETNE) && \"Only applicable for (in)equality comparisons.\""
, "/build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/SelectionDAG/TargetLowering.cpp"
, 5101, __PRETTY_FUNCTION__))
5101 "Only applicable for (in)equality comparisons.")(((Cond == ISD::SETEQ || Cond == ISD::SETNE) && "Only applicable for (in)equality comparisons."
) ? static_cast<void> (0) : __assert_fail ("(Cond == ISD::SETEQ || Cond == ISD::SETNE) && \"Only applicable for (in)equality comparisons.\""
, "/build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/SelectionDAG/TargetLowering.cpp"
, 5101, __PRETTY_FUNCTION__))
;
5102
5103 SelectionDAG &DAG = DCI.DAG;
5104
5105 EVT VT = REMNode.getValueType();
5106 EVT SVT = VT.getScalarType();
5107 EVT ShVT = getShiftAmountTy(VT, DAG.getDataLayout());
5108 EVT ShSVT = ShVT.getScalarType();
5109
5110 // If MUL is unavailable, we cannot proceed in any case.
5111 if (!isOperationLegalOrCustom(ISD::MUL, VT))
5112 return SDValue();
5113
5114 // TODO: Could support comparing with non-zero too.
5115 ConstantSDNode *CompTarget = isConstOrConstSplat(CompTargetNode);
5116 if (!CompTarget || !CompTarget->isNullValue())
5117 return SDValue();
5118
5119 bool HadIntMinDivisor = false;
5120 bool HadOneDivisor = false;
5121 bool AllDivisorsAreOnes = true;
5122 bool HadEvenDivisor = false;
5123 bool NeedToApplyOffset = false;
5124 bool AllDivisorsArePowerOfTwo = true;
5125 SmallVector<SDValue, 16> PAmts, AAmts, KAmts, QAmts;
5126
5127 auto BuildSREMPattern = [&](ConstantSDNode *C) {
5128 // Division by 0 is UB. Leave it to be constant-folded elsewhere.
5129 if (C->isNullValue())
1
Taking false branch
5130 return false;
5131
5132 // FIXME: we don't fold `rem %X, -C` to `rem %X, C` in DAGCombine.
5133
5134 // WARNING: this fold is only valid for positive divisors!
5135 APInt D = C->getAPIntValue();
5136 if (D.isNegative())
2
Taking false branch
5137 D.negate(); // `rem %X, -C` is equivalent to `rem %X, C`
5138
5139 HadIntMinDivisor |= D.isMinSignedValue();
5140
5141 // If all divisors are ones, we will prefer to avoid the fold.
5142 HadOneDivisor |= D.isOneValue();
5143 AllDivisorsAreOnes &= D.isOneValue();
5144
5145 // Decompose D into D0 * 2^K
5146 unsigned K = D.countTrailingZeros();
5147 assert((!D.isOneValue() || (K == 0)) && "For divisor '1' we won't rotate.")(((!D.isOneValue() || (K == 0)) && "For divisor '1' we won't rotate."
) ? static_cast<void> (0) : __assert_fail ("(!D.isOneValue() || (K == 0)) && \"For divisor '1' we won't rotate.\""
, "/build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/SelectionDAG/TargetLowering.cpp"
, 5147, __PRETTY_FUNCTION__))
;
3
Assuming 'K' is equal to 0
4
'?' condition is true
5148 APInt D0 = D.lshr(K);
5149
5150 if (!D.isMinSignedValue()) {
5
Calling 'APInt::isMinSignedValue'
5151 // D is even if it has trailing zeros; unless it's INT_MIN, in which case
5152 // we don't care about this lane in this fold, we'll special-handle it.
5153 HadEvenDivisor |= (K != 0);
5154 }
5155
5156 // D is a power-of-two if D0 is one. This includes INT_MIN.
5157 // If all divisors are power-of-two, we will prefer to avoid the fold.
5158 AllDivisorsArePowerOfTwo &= D0.isOneValue();
5159
5160 // P = inv(D0, 2^W)
5161 // 2^W requires W + 1 bits, so we have to extend and then truncate.
5162 unsigned W = D.getBitWidth();
5163 APInt P = D0.zext(W + 1)
5164 .multiplicativeInverse(APInt::getSignedMinValue(W + 1))
5165 .trunc(W);
5166 assert(!P.isNullValue() && "No multiplicative inverse!")((!P.isNullValue() && "No multiplicative inverse!") ?
static_cast<void> (0) : __assert_fail ("!P.isNullValue() && \"No multiplicative inverse!\""
, "/build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/SelectionDAG/TargetLowering.cpp"
, 5166, __PRETTY_FUNCTION__))
; // unreachable
5167 assert((D0 * P).isOneValue() && "Multiplicative inverse sanity check.")(((D0 * P).isOneValue() && "Multiplicative inverse sanity check."
) ? static_cast<void> (0) : __assert_fail ("(D0 * P).isOneValue() && \"Multiplicative inverse sanity check.\""
, "/build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/SelectionDAG/TargetLowering.cpp"
, 5167, __PRETTY_FUNCTION__))
;
5168
5169 // A = floor((2^(W - 1) - 1) / D0) & -2^K
5170 APInt A = APInt::getSignedMaxValue(W).udiv(D0);
5171 A.clearLowBits(K);
5172
5173 if (!D.isMinSignedValue()) {
5174 // If divisor INT_MIN, then we don't care about this lane in this fold,
5175 // we'll special-handle it.
5176 NeedToApplyOffset |= A != 0;
5177 }
5178
5179 // Q = floor((2 * A) / (2^K))
5180 APInt Q = (2 * A).udiv(APInt::getOneBitSet(W, K));
5181
5182 assert(APInt::getAllOnesValue(SVT.getSizeInBits()).ugt(A) &&((APInt::getAllOnesValue(SVT.getSizeInBits()).ugt(A) &&
"We are expecting that A is always less than all-ones for SVT"
) ? static_cast<void> (0) : __assert_fail ("APInt::getAllOnesValue(SVT.getSizeInBits()).ugt(A) && \"We are expecting that A is always less than all-ones for SVT\""
, "/build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/SelectionDAG/TargetLowering.cpp"
, 5183, __PRETTY_FUNCTION__))
5183 "We are expecting that A is always less than all-ones for SVT")((APInt::getAllOnesValue(SVT.getSizeInBits()).ugt(A) &&
"We are expecting that A is always less than all-ones for SVT"
) ? static_cast<void> (0) : __assert_fail ("APInt::getAllOnesValue(SVT.getSizeInBits()).ugt(A) && \"We are expecting that A is always less than all-ones for SVT\""
, "/build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/SelectionDAG/TargetLowering.cpp"
, 5183, __PRETTY_FUNCTION__))
;
5184 assert(APInt::getAllOnesValue(ShSVT.getSizeInBits()).ugt(K) &&((APInt::getAllOnesValue(ShSVT.getSizeInBits()).ugt(K) &&
"We are expecting that K is always less than all-ones for ShSVT"
) ? static_cast<void> (0) : __assert_fail ("APInt::getAllOnesValue(ShSVT.getSizeInBits()).ugt(K) && \"We are expecting that K is always less than all-ones for ShSVT\""
, "/build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/SelectionDAG/TargetLowering.cpp"
, 5185, __PRETTY_FUNCTION__))
5185 "We are expecting that K is always less than all-ones for ShSVT")((APInt::getAllOnesValue(ShSVT.getSizeInBits()).ugt(K) &&
"We are expecting that K is always less than all-ones for ShSVT"
) ? static_cast<void> (0) : __assert_fail ("APInt::getAllOnesValue(ShSVT.getSizeInBits()).ugt(K) && \"We are expecting that K is always less than all-ones for ShSVT\""
, "/build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/SelectionDAG/TargetLowering.cpp"
, 5185, __PRETTY_FUNCTION__))
;
5186
5187 // If the divisor is 1 the result can be constant-folded. Likewise, we
5188 // don't care about INT_MIN lanes, those can be set to undef if appropriate.
5189 if (D.isOneValue()) {
5190 // Set P, A and K to a bogus values so we can try to splat them.
5191 P = 0;
5192 A = -1;
5193 K = -1;
5194
5195 // x ?% 1 == 0 <--> true <--> x u<= -1
5196 Q = -1;
5197 }
5198
5199 PAmts.push_back(DAG.getConstant(P, DL, SVT));
5200 AAmts.push_back(DAG.getConstant(A, DL, SVT));
5201 KAmts.push_back(
5202 DAG.getConstant(APInt(ShSVT.getSizeInBits(), K), DL, ShSVT));
5203 QAmts.push_back(DAG.getConstant(Q, DL, SVT));
5204 return true;
5205 };
5206
5207 SDValue N = REMNode.getOperand(0);
5208 SDValue D = REMNode.getOperand(1);
5209
5210 // Collect the values from each element.
5211 if (!ISD::matchUnaryPredicate(D, BuildSREMPattern))
5212 return SDValue();
5213
5214 // If this is a srem by a one, avoid the fold since it can be constant-folded.
5215 if (AllDivisorsAreOnes)
5216 return SDValue();
5217
5218 // If this is a srem by a powers-of-two (including INT_MIN), avoid the fold
5219 // since it can be best implemented as a bit test.
5220 if (AllDivisorsArePowerOfTwo)
5221 return SDValue();
5222
5223 SDValue PVal, AVal, KVal, QVal;
5224 if (VT.isVector()) {
5225 if (HadOneDivisor) {
5226 // Try to turn PAmts into a splat, since we don't care about the values
5227 // that are currently '0'. If we can't, just keep '0'`s.
5228 turnVectorIntoSplatVector(PAmts, isNullConstant);
5229 // Try to turn AAmts into a splat, since we don't care about the
5230 // values that are currently '-1'. If we can't, change them to '0'`s.
5231 turnVectorIntoSplatVector(AAmts, isAllOnesConstant,
5232 DAG.getConstant(0, DL, SVT));
5233 // Try to turn KAmts into a splat, since we don't care about the values
5234 // that are currently '-1'. If we can't, change them to '0'`s.
5235 turnVectorIntoSplatVector(KAmts, isAllOnesConstant,
5236 DAG.getConstant(0, DL, ShSVT));
5237 }
5238
5239 PVal = DAG.getBuildVector(VT, DL, PAmts);
5240 AVal = DAG.getBuildVector(VT, DL, AAmts);
5241 KVal = DAG.getBuildVector(ShVT, DL, KAmts);
5242 QVal = DAG.getBuildVector(VT, DL, QAmts);
5243 } else {
5244 PVal = PAmts[0];
5245 AVal = AAmts[0];
5246 KVal = KAmts[0];
5247 QVal = QAmts[0];
5248 }
5249
5250 // (mul N, P)
5251 SDValue Op0 = DAG.getNode(ISD::MUL, DL, VT, N, PVal);
5252 Created.push_back(Op0.getNode());
5253
5254 if (NeedToApplyOffset) {
5255 // We need ADD to do this.
5256 if (!isOperationLegalOrCustom(ISD::ADD, VT))
5257 return SDValue();
5258
5259 // (add (mul N, P), A)
5260 Op0 = DAG.getNode(ISD::ADD, DL, VT, Op0, AVal);
5261 Created.push_back(Op0.getNode());
5262 }
5263
5264 // Rotate right only if any divisor was even. We avoid rotates for all-odd
5265 // divisors as a performance improvement, since rotating by 0 is a no-op.
5266 if (HadEvenDivisor) {
5267 // We need ROTR to do this.
5268 if (!isOperationLegalOrCustom(ISD::ROTR, VT))
5269 return SDValue();
5270 SDNodeFlags Flags;
5271 Flags.setExact(true);
5272 // SREM: (rotr (add (mul N, P), A), K)
5273 Op0 = DAG.getNode(ISD::ROTR, DL, VT, Op0, KVal, Flags);
5274 Created.push_back(Op0.getNode());
5275 }
5276
5277 // SREM: (setule/setugt (rotr (add (mul N, P), A), K), Q)
5278 SDValue Fold =
5279 DAG.getSetCC(DL, SETCCVT, Op0, QVal,
5280 ((Cond == ISD::SETEQ) ? ISD::SETULE : ISD::SETUGT));
5281
5282 // If we didn't have lanes with INT_MIN divisor, then we're done.
5283 if (!HadIntMinDivisor)
5284 return Fold;
5285
5286 // That fold is only valid for positive divisors. Which effectively means,
5287 // it is invalid for INT_MIN divisors. So if we have such a lane,
5288 // we must fix-up results for said lanes.
5289 assert(VT.isVector() && "Can/should only get here for vectors.")((VT.isVector() && "Can/should only get here for vectors."
) ? static_cast<void> (0) : __assert_fail ("VT.isVector() && \"Can/should only get here for vectors.\""
, "/build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/SelectionDAG/TargetLowering.cpp"
, 5289, __PRETTY_FUNCTION__))
;
5290
5291 if (!isOperationLegalOrCustom(ISD::SETEQ, VT) ||
5292 !isOperationLegalOrCustom(ISD::AND, VT) ||
5293 !isOperationLegalOrCustom(Cond, VT) ||
5294 !isOperationLegalOrCustom(ISD::VSELECT, VT))
5295 return SDValue();
5296
5297 Created.push_back(Fold.getNode());
5298
5299 SDValue IntMin = DAG.getConstant(
5300 APInt::getSignedMinValue(SVT.getScalarSizeInBits()), DL, VT);
5301 SDValue IntMax = DAG.getConstant(
5302 APInt::getSignedMaxValue(SVT.getScalarSizeInBits()), DL, VT);
5303 SDValue Zero =
5304 DAG.getConstant(APInt::getNullValue(SVT.getScalarSizeInBits()), DL, VT);
5305
5306 // Which lanes had INT_MIN divisors? Divisor is constant, so const-folded.
5307 SDValue DivisorIsIntMin = DAG.getSetCC(DL, SETCCVT, D, IntMin, ISD::SETEQ);
5308 Created.push_back(DivisorIsIntMin.getNode());
5309
5310 // (N s% INT_MIN) ==/!= 0 <--> (N & INT_MAX) ==/!= 0
5311 SDValue Masked = DAG.getNode(ISD::AND, DL, VT, N, IntMax);
5312 Created.push_back(Masked.getNode());
5313 SDValue MaskedIsZero = DAG.getSetCC(DL, SETCCVT, Masked, Zero, Cond);
5314 Created.push_back(MaskedIsZero.getNode());
5315
5316 // To produce final result we need to blend 2 vectors: 'SetCC' and
5317 // 'MaskedIsZero'. If the divisor for channel was *NOT* INT_MIN, we pick
5318 // from 'Fold', else pick from 'MaskedIsZero'. Since 'DivisorIsIntMin' is
5319 // constant-folded, select can get lowered to a shuffle with constant mask.
5320 SDValue Blended =
5321 DAG.getNode(ISD::VSELECT, DL, VT, DivisorIsIntMin, MaskedIsZero, Fold);
5322
5323 return Blended;
5324}
5325
5326bool TargetLowering::
5327verifyReturnAddressArgumentIsConstant(SDValue Op, SelectionDAG &DAG) const {
5328 if (!isa<ConstantSDNode>(Op.getOperand(0))) {
5329 DAG.getContext()->emitError("argument to '__builtin_return_address' must "
5330 "be a constant integer");
5331 return true;
5332 }
5333
5334 return false;
5335}
5336
5337char TargetLowering::isNegatibleForFree(SDValue Op, SelectionDAG &DAG,
5338 bool LegalOperations, bool ForCodeSize,
5339 unsigned Depth) const {
5340 // fneg is removable even if it has multiple uses.
5341 if (Op.getOpcode() == ISD::FNEG)
5342 return 2;
5343
5344 // Don't allow anything with multiple uses unless we know it is free.
5345 EVT VT = Op.getValueType();
5346 const SDNodeFlags Flags = Op->getFlags();
5347 const TargetOptions &Options = DAG.getTarget().Options;
5348 if (!Op.hasOneUse() && !(Op.getOpcode() == ISD::FP_EXTEND &&
5349 isFPExtFree(VT, Op.getOperand(0).getValueType())))
5350 return 0;
5351
5352 // Don't recurse exponentially.
5353 if (Depth > SelectionDAG::MaxRecursionDepth)
5354 return 0;
5355
5356 switch (Op.getOpcode()) {
5357 case ISD::ConstantFP: {
5358 if (!LegalOperations)
5359 return 1;
5360
5361 // Don't invert constant FP values after legalization unless the target says
5362 // the negated constant is legal.
5363 return isOperationLegal(ISD::ConstantFP, VT) ||
5364 isFPImmLegal(neg(cast<ConstantFPSDNode>(Op)->getValueAPF()), VT,
5365 ForCodeSize);
5366 }
5367 case ISD::BUILD_VECTOR: {
5368 // Only permit BUILD_VECTOR of constants.
5369 if (llvm::any_of(Op->op_values(), [&](SDValue N) {
5370 return !N.isUndef() && !isa<ConstantFPSDNode>(N);
5371 }))
5372 return 0;
5373 if (!LegalOperations)
5374 return 1;
5375 if (isOperationLegal(ISD::ConstantFP, VT) &&
5376 isOperationLegal(ISD::BUILD_VECTOR, VT))
5377 return 1;
5378 return llvm::all_of(Op->op_values(), [&](SDValue N) {
5379 return N.isUndef() ||
5380 isFPImmLegal(neg(cast<ConstantFPSDNode>(N)->getValueAPF()), VT,
5381 ForCodeSize);
5382 });
5383 }
5384 case ISD::FADD:
5385 if (!Options.NoSignedZerosFPMath && !Flags.hasNoSignedZeros())
5386 return 0;
5387
5388 // After operation legalization, it might not be legal to create new FSUBs.
5389 if (LegalOperations && !isOperationLegalOrCustom(ISD::FSUB, VT))
5390 return 0;
5391
5392 // fold (fneg (fadd A, B)) -> (fsub (fneg A), B)
5393 if (char V = isNegatibleForFree(Op.getOperand(0), DAG, LegalOperations,
5394 ForCodeSize, Depth + 1))
5395 return V;
5396 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A)
5397 return isNegatibleForFree(Op.getOperand(1), DAG, LegalOperations,
5398 ForCodeSize, Depth + 1);
5399 case ISD::FSUB:
5400 // We can't turn -(A-B) into B-A when we honor signed zeros.
5401 if (!Options.NoSignedZerosFPMath && !Flags.hasNoSignedZeros())
5402 return 0;
5403
5404 // fold (fneg (fsub A, B)) -> (fsub B, A)
5405 return 1;
5406
5407 case ISD::FMUL:
5408 case ISD::FDIV:
5409 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y) or (fmul X, (fneg Y))
5410 if (char V = isNegatibleForFree(Op.getOperand(0), DAG, LegalOperations,
5411 ForCodeSize, Depth + 1))
5412 return V;
5413
5414 // Ignore X * 2.0 because that is expected to be canonicalized to X + X.
5415 if (auto *C = isConstOrConstSplatFP(Op.getOperand(1)))
5416 if (C->isExactlyValue(2.0) && Op.getOpcode() == ISD::FMUL)
5417 return 0;
5418
5419 return isNegatibleForFree(Op.getOperand(1), DAG, LegalOperations,
5420 ForCodeSize, Depth + 1);
5421
5422 case ISD::FMA:
5423 case ISD::FMAD: {
5424 if (!Options.NoSignedZerosFPMath && !Flags.hasNoSignedZeros())
5425 return 0;
5426
5427 // fold (fneg (fma X, Y, Z)) -> (fma (fneg X), Y, (fneg Z))
5428 // fold (fneg (fma X, Y, Z)) -> (fma X, (fneg Y), (fneg Z))
5429 char V2 = isNegatibleForFree(Op.getOperand(2), DAG, LegalOperations,
5430 ForCodeSize, Depth + 1);
5431 if (!V2)
5432 return 0;
5433
5434 // One of Op0/Op1 must be cheaply negatible, then select the cheapest.
5435 char V0 = isNegatibleForFree(Op.getOperand(0), DAG, LegalOperations,
5436 ForCodeSize, Depth + 1);
5437 char V1 = isNegatibleForFree(Op.getOperand(1), DAG, LegalOperations,
5438 ForCodeSize, Depth + 1);
5439 char V01 = std::max(V0, V1);
5440 return V01 ? std::max(V01, V2) : 0;
5441 }
5442
5443 case ISD::FP_EXTEND:
5444 case ISD::FP_ROUND:
5445 case ISD::FSIN:
5446 return isNegatibleForFree(Op.getOperand(0), DAG, LegalOperations,
5447 ForCodeSize, Depth + 1);
5448 }
5449
5450 return 0;
5451}
5452
5453SDValue TargetLowering::getNegatedExpression(SDValue Op, SelectionDAG &DAG,
5454 bool LegalOperations,
5455 bool ForCodeSize,
5456 unsigned Depth) const {
5457 // fneg is removable even if it has multiple uses.
5458 if (Op.getOpcode() == ISD::FNEG)
5459 return Op.getOperand(0);
5460
5461 assert(Depth <= SelectionDAG::MaxRecursionDepth &&((Depth <= SelectionDAG::MaxRecursionDepth && "getNegatedExpression doesn't match isNegatibleForFree"
) ? static_cast<void> (0) : __assert_fail ("Depth <= SelectionDAG::MaxRecursionDepth && \"getNegatedExpression doesn't match isNegatibleForFree\""
, "/build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/SelectionDAG/TargetLowering.cpp"
, 5462, __PRETTY_FUNCTION__))
5462 "getNegatedExpression doesn't match isNegatibleForFree")((Depth <= SelectionDAG::MaxRecursionDepth && "getNegatedExpression doesn't match isNegatibleForFree"
) ? static_cast<void> (0) : __assert_fail ("Depth <= SelectionDAG::MaxRecursionDepth && \"getNegatedExpression doesn't match isNegatibleForFree\""
, "/build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/SelectionDAG/TargetLowering.cpp"
, 5462, __PRETTY_FUNCTION__))
;
5463 const SDNodeFlags Flags = Op->getFlags();
5464
5465 switch (Op.getOpcode()) {
5466 case ISD::ConstantFP: {
5467 APFloat V = cast<ConstantFPSDNode>(Op)->getValueAPF();
5468 V.changeSign();
5469 return DAG.getConstantFP(V, SDLoc(Op), Op.getValueType());
5470 }
5471 case ISD::BUILD_VECTOR: {
5472 SmallVector<SDValue, 4> Ops;
5473 for (SDValue C : Op->op_values()) {
5474 if (C.isUndef()) {
5475 Ops.push_back(C);
5476 continue;
5477 }
5478 APFloat V = cast<ConstantFPSDNode>(C)->getValueAPF();
5479 V.changeSign();
5480 Ops.push_back(DAG.getConstantFP(V, SDLoc(Op), C.getValueType()));
5481 }
5482 return DAG.getBuildVector(Op.getValueType(), SDLoc(Op), Ops);
5483 }
5484 case ISD::FADD:
5485 assert((DAG.getTarget().Options.NoSignedZerosFPMath ||(((DAG.getTarget().Options.NoSignedZerosFPMath || Flags.hasNoSignedZeros
()) && "Expected NSZ fp-flag") ? static_cast<void>
(0) : __assert_fail ("(DAG.getTarget().Options.NoSignedZerosFPMath || Flags.hasNoSignedZeros()) && \"Expected NSZ fp-flag\""
, "/build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/SelectionDAG/TargetLowering.cpp"
, 5487, __PRETTY_FUNCTION__))
5486 Flags.hasNoSignedZeros()) &&(((DAG.getTarget().Options.NoSignedZerosFPMath || Flags.hasNoSignedZeros
()) && "Expected NSZ fp-flag") ? static_cast<void>
(0) : __assert_fail ("(DAG.getTarget().Options.NoSignedZerosFPMath || Flags.hasNoSignedZeros()) && \"Expected NSZ fp-flag\""
, "/build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/SelectionDAG/TargetLowering.cpp"
, 5487, __PRETTY_FUNCTION__))
5487 "Expected NSZ fp-flag")(((DAG.getTarget().Options.NoSignedZerosFPMath || Flags.hasNoSignedZeros
()) && "Expected NSZ fp-flag") ? static_cast<void>
(0) : __assert_fail ("(DAG.getTarget().Options.NoSignedZerosFPMath || Flags.hasNoSignedZeros()) && \"Expected NSZ fp-flag\""
, "/build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/SelectionDAG/TargetLowering.cpp"
, 5487, __PRETTY_FUNCTION__))
;
5488
5489 // fold (fneg (fadd A, B)) -> (fsub (fneg A), B)
5490 if (isNegatibleForFree(Op.getOperand(0), DAG, LegalOperations, ForCodeSize,
5491 Depth + 1))
5492 return DAG.getNode(ISD::FSUB, SDLoc(Op), Op.getValueType(),
5493 getNegatedExpression(Op.getOperand(0), DAG,
5494 LegalOperations, ForCodeSize,
5495 Depth + 1),
5496 Op.getOperand(1), Flags);
5497 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A)
5498 return DAG.getNode(ISD::FSUB, SDLoc(Op), Op.getValueType(),
5499 getNegatedExpression(Op.getOperand(1), DAG,
5500 LegalOperations, ForCodeSize,
5501 Depth + 1),
5502 Op.getOperand(0), Flags);
5503 case ISD::FSUB:
5504 // fold (fneg (fsub 0, B)) -> B
5505 if (ConstantFPSDNode *N0CFP =
5506 isConstOrConstSplatFP(Op.getOperand(0), /*AllowUndefs*/ true))
5507 if (N0CFP->isZero())
5508 return Op.getOperand(1);
5509
5510 // fold (fneg (fsub A, B)) -> (fsub B, A)
5511 return DAG.getNode(ISD::FSUB, SDLoc(Op), Op.getValueType(),
5512 Op.getOperand(1), Op.getOperand(0), Flags);
5513
5514 case ISD::FMUL:
5515 case ISD::FDIV:
5516 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y)
5517 if (isNegatibleForFree(Op.getOperand(0), DAG, LegalOperations, ForCodeSize,
5518 Depth + 1))
5519 return DAG.getNode(Op.getOpcode(), SDLoc(Op), Op.getValueType(),
5520 getNegatedExpression(Op.getOperand(0), DAG,
5521 LegalOperations, ForCodeSize,
5522 Depth + 1),
5523 Op.getOperand(1), Flags);
5524
5525 // fold (fneg (fmul X, Y)) -> (fmul X, (fneg Y))
5526 return DAG.getNode(
5527 Op.getOpcode(), SDLoc(Op), Op.getValueType(), Op.getOperand(0),
5528 getNegatedExpression(Op.getOperand(1), DAG, LegalOperations,
5529 ForCodeSize, Depth + 1),
5530 Flags);
5531
5532 case ISD::FMA:
5533 case ISD::FMAD: {
5534 assert((DAG.getTarget().Options.NoSignedZerosFPMath ||(((DAG.getTarget().Options.NoSignedZerosFPMath || Flags.hasNoSignedZeros
()) && "Expected NSZ fp-flag") ? static_cast<void>
(0) : __assert_fail ("(DAG.getTarget().Options.NoSignedZerosFPMath || Flags.hasNoSignedZeros()) && \"Expected NSZ fp-flag\""
, "/build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/SelectionDAG/TargetLowering.cpp"
, 5536, __PRETTY_FUNCTION__))
5535 Flags.hasNoSignedZeros()) &&(((DAG.getTarget().Options.NoSignedZerosFPMath || Flags.hasNoSignedZeros
()) && "Expected NSZ fp-flag") ? static_cast<void>
(0) : __assert_fail ("(DAG.getTarget().Options.NoSignedZerosFPMath || Flags.hasNoSignedZeros()) && \"Expected NSZ fp-flag\""
, "/build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/SelectionDAG/TargetLowering.cpp"
, 5536, __PRETTY_FUNCTION__))
5536 "Expected NSZ fp-flag")(((DAG.getTarget().Options.NoSignedZerosFPMath || Flags.hasNoSignedZeros
()) && "Expected NSZ fp-flag") ? static_cast<void>
(0) : __assert_fail ("(DAG.getTarget().Options.NoSignedZerosFPMath || Flags.hasNoSignedZeros()) && \"Expected NSZ fp-flag\""
, "/build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/SelectionDAG/TargetLowering.cpp"
, 5536, __PRETTY_FUNCTION__))
;
5537
5538 SDValue Neg2 = getNegatedExpression(Op.getOperand(2), DAG, LegalOperations,
5539 ForCodeSize, Depth + 1);
5540
5541 char V0 = isNegatibleForFree(Op.getOperand(0), DAG, LegalOperations,
5542 ForCodeSize, Depth + 1);
5543 char V1 = isNegatibleForFree(Op.getOperand(1), DAG, LegalOperations,
5544 ForCodeSize, Depth + 1);
5545 if (V0 >= V1) {
5546 // fold (fneg (fma X, Y, Z)) -> (fma (fneg X), Y, (fneg Z))
5547 SDValue Neg0 = getNegatedExpression(
5548 Op.getOperand(0), DAG, LegalOperations, ForCodeSize, Depth + 1);
5549 return DAG.getNode(Op.getOpcode(), SDLoc(Op), Op.getValueType(), Neg0,
5550 Op.getOperand(1), Neg2, Flags);
5551 }
5552
5553 // fold (fneg (fma X, Y, Z)) -> (fma X, (fneg Y), (fneg Z))
5554 SDValue Neg1 = getNegatedExpression(Op.getOperand(1), DAG, LegalOperations,
5555 ForCodeSize, Depth + 1);
5556 return DAG.getNode(Op.getOpcode(), SDLoc(Op), Op.getValueType(),
5557 Op.getOperand(0), Neg1, Neg2, Flags);
5558 }
5559
5560 case ISD::FP_EXTEND:
5561 case ISD::FSIN:
5562 return DAG.getNode(Op.getOpcode(), SDLoc(Op), Op.getValueType(),
5563 getNegatedExpression(Op.getOperand(0), DAG,
5564 LegalOperations, ForCodeSize,
5565 Depth + 1));
5566 case ISD::FP_ROUND:
5567 return DAG.getNode(ISD::FP_ROUND, SDLoc(Op), Op.getValueType(),
5568 getNegatedExpression(Op.getOperand(0), DAG,
5569 LegalOperations, ForCodeSize,
5570 Depth + 1),
5571 Op.getOperand(1));
5572 }
5573
5574 llvm_unreachable("Unknown code")::llvm::llvm_unreachable_internal("Unknown code", "/build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/SelectionDAG/TargetLowering.cpp"
, 5574)
;
5575}
5576
5577//===----------------------------------------------------------------------===//
5578// Legalization Utilities
5579//===----------------------------------------------------------------------===//
5580
5581bool TargetLowering::expandMUL_LOHI(unsigned Opcode, EVT VT, SDLoc dl,
5582 SDValue LHS, SDValue RHS,
5583 SmallVectorImpl<SDValue> &Result,
5584 EVT HiLoVT, SelectionDAG &DAG,
5585 MulExpansionKind Kind, SDValue LL,
5586 SDValue LH, SDValue RL, SDValue RH) const {
5587 assert(Opcode == ISD::MUL || Opcode == ISD::UMUL_LOHI ||((Opcode == ISD::MUL || Opcode == ISD::UMUL_LOHI || Opcode ==
ISD::SMUL_LOHI) ? static_cast<void> (0) : __assert_fail
("Opcode == ISD::MUL || Opcode == ISD::UMUL_LOHI || Opcode == ISD::SMUL_LOHI"
, "/build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/SelectionDAG/TargetLowering.cpp"
, 5588, __PRETTY_FUNCTION__))
5588 Opcode == ISD::SMUL_LOHI)((Opcode == ISD::MUL || Opcode == ISD::UMUL_LOHI || Opcode ==
ISD::SMUL_LOHI) ? static_cast<void> (0) : __assert_fail
("Opcode == ISD::MUL || Opcode == ISD::UMUL_LOHI || Opcode == ISD::SMUL_LOHI"
, "/build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/SelectionDAG/TargetLowering.cpp"
, 5588, __PRETTY_FUNCTION__))
;
5589
5590 bool HasMULHS = (Kind == MulExpansionKind::Always) ||
5591 isOperationLegalOrCustom(ISD::MULHS, HiLoVT);
5592 bool HasMULHU = (Kind == MulExpansionKind::Always) ||
5593 isOperationLegalOrCustom(ISD::MULHU, HiLoVT);
5594 bool HasSMUL_LOHI = (Kind == MulExpansionKind::Always) ||
5595 isOperationLegalOrCustom(ISD::SMUL_LOHI, HiLoVT);
5596 bool HasUMUL_LOHI = (Kind == MulExpansionKind::Always) ||
5597 isOperationLegalOrCustom(ISD::UMUL_LOHI, HiLoVT);
5598
5599 if (!HasMULHU && !HasMULHS && !HasUMUL_LOHI && !HasSMUL_LOHI)
5600 return false;
5601
5602 unsigned OuterBitSize = VT.getScalarSizeInBits();
5603 unsigned InnerBitSize = HiLoVT.getScalarSizeInBits();
5604 unsigned LHSSB = DAG.ComputeNumSignBits(LHS);
5605 unsigned RHSSB = DAG.ComputeNumSignBits(RHS);
5606
5607 // LL, LH, RL, and RH must be either all NULL or all set to a value.
5608 assert((LL.getNode() && LH.getNode() && RL.getNode() && RH.getNode()) ||(((LL.getNode() && LH.getNode() && RL.getNode
() && RH.getNode()) || (!LL.getNode() && !LH.
getNode() && !RL.getNode() && !RH.getNode()))
? static_cast<void> (0) : __assert_fail ("(LL.getNode() && LH.getNode() && RL.getNode() && RH.getNode()) || (!LL.getNode() && !LH.getNode() && !RL.getNode() && !RH.getNode())"
, "/build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/SelectionDAG/TargetLowering.cpp"
, 5609, __PRETTY_FUNCTION__))
5609 (!LL.getNode() && !LH.getNode() && !RL.getNode() && !RH.getNode()))(((LL.getNode() && LH.getNode() && RL.getNode
() && RH.getNode()) || (!LL.getNode() && !LH.
getNode() && !RL.getNode() && !RH.getNode()))
? static_cast<void> (0) : __assert_fail ("(LL.getNode() && LH.getNode() && RL.getNode() && RH.getNode()) || (!LL.getNode() && !LH.getNode() && !RL.getNode() && !RH.getNode())"
, "/build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/SelectionDAG/TargetLowering.cpp"
, 5609, __PRETTY_FUNCTION__))
;
5610
5611 SDVTList VTs = DAG.getVTList(HiLoVT, HiLoVT);
5612 auto MakeMUL_LOHI = [&](SDValue L, SDValue R, SDValue &Lo, SDValue &Hi,
5613 bool Signed) -> bool {
5614 if ((Signed && HasSMUL_LOHI) || (!Signed && HasUMUL_LOHI)) {
5615 Lo = DAG.getNode(Signed ? ISD::SMUL_LOHI : ISD::UMUL_LOHI, dl, VTs, L, R);
5616 Hi = SDValue(Lo.getNode(), 1);
5617 return true;
5618 }
5619 if ((Signed && HasMULHS) || (!Signed && HasMULHU)) {
5620 Lo = DAG.getNode(ISD::MUL, dl, HiLoVT, L, R);
5621 Hi = DAG.getNode(Signed ? ISD::MULHS : ISD::MULHU, dl, HiLoVT, L, R);
5622 return true;
5623 }
5624 return false;
5625 };
5626
5627 SDValue Lo, Hi;
5628
5629 if (!LL.getNode() && !RL.getNode() &&
5630 isOperationLegalOrCustom(ISD::TRUNCATE, HiLoVT)) {
5631 LL = DAG.getNode(ISD::TRUNCATE, dl, HiLoVT, LHS);
5632 RL = DAG.getNode(ISD::TRUNCATE, dl, HiLoVT, RHS);
5633 }
5634
5635 if (!LL.getNode())
5636 return false;
5637
5638 APInt HighMask = APInt::getHighBitsSet(OuterBitSize, InnerBitSize);
5639 if (DAG.MaskedValueIsZero(LHS, HighMask) &&
5640 DAG.MaskedValueIsZero(RHS, HighMask)) {
5641 // The inputs are both zero-extended.
5642 if (MakeMUL_LOHI(LL, RL, Lo, Hi, false)) {
5643 Result.push_back(Lo);
5644 Result.push_back(Hi);
5645 if (Opcode != ISD::MUL) {
5646 SDValue Zero = DAG.getConstant(0, dl, HiLoVT);
5647 Result.push_back(Zero);
5648 Result.push_back(Zero);
5649 }
5650 return true;
5651 }
5652 }
5653
5654 if (!VT.isVector() && Opcode == ISD::MUL && LHSSB > InnerBitSize &&
5655 RHSSB > InnerBitSize) {
5656 // The input values are both sign-extended.
5657 // TODO non-MUL case?
5658 if (MakeMUL_LOHI(LL, RL, Lo, Hi, true)) {
5659 Result.push_back(Lo);
5660 Result.push_back(Hi);
5661 return true;
5662 }
5663 }
5664
5665 unsigned ShiftAmount = OuterBitSize - InnerBitSize;
5666 EVT ShiftAmountTy = getShiftAmountTy(VT, DAG.getDataLayout());
5667 if (APInt::getMaxValue(ShiftAmountTy.getSizeInBits()).ult(ShiftAmount)) {
5668 // FIXME getShiftAmountTy does not always return a sensible result when VT
5669 // is an illegal type, and so the type may be too small to fit the shift
5670 // amount. Override it with i32. The shift will have to be legalized.
5671 ShiftAmountTy = MVT::i32;
5672 }
5673 SDValue Shift = DAG.getConstant(ShiftAmount, dl, ShiftAmountTy);
5674
5675 if (!LH.getNode() && !RH.getNode() &&
5676 isOperationLegalOrCustom(ISD::SRL, VT) &&
5677 isOperationLegalOrCustom(ISD::TRUNCATE, HiLoVT)) {
5678 LH = DAG.getNode(ISD::SRL, dl, VT, LHS, Shift);
5679 LH = DAG.getNode(ISD::TRUNCATE, dl, HiLoVT, LH);
5680 RH = DAG.getNode(ISD::SRL, dl, VT, RHS, Shift);
5681 RH = DAG.getNode(ISD::TRUNCATE, dl, HiLoVT, RH);
5682 }
5683
5684 if (!LH.getNode())
5685 return false;
5686
5687 if (!MakeMUL_LOHI(LL, RL, Lo, Hi, false))
5688 return false;
5689
5690 Result.push_back(Lo);
5691
5692 if (Opcode == ISD::MUL) {
5693 RH = DAG.getNode(ISD::MUL, dl, HiLoVT, LL, RH);
5694 LH = DAG.getNode(ISD::MUL, dl, HiLoVT, LH, RL);
5695 Hi = DAG.getNode(ISD::ADD, dl, HiLoVT, Hi, RH);
5696 Hi = DAG.getNode(ISD::ADD, dl, HiLoVT, Hi, LH);
5697 Result.push_back(Hi);
5698 return true;
5699 }
5700
5701 // Compute the full width result.
5702 auto Merge = [&](SDValue Lo, SDValue Hi) -> SDValue {
5703 Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Lo);
5704 Hi = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Hi);
5705 Hi = DAG.getNode(ISD::SHL, dl, VT, Hi, Shift);
5706 return DAG.getNode(ISD::OR, dl, VT, Lo, Hi);
5707 };
5708
5709 SDValue Next = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Hi);
5710 if (!MakeMUL_LOHI(LL, RH, Lo, Hi, false))
5711 return false;
5712
5713 // This is effectively the add part of a multiply-add of half-sized operands,
5714 // so it cannot overflow.
5715 Next = DAG.getNode(ISD::ADD, dl, VT, Next, Merge(Lo, Hi));
5716
5717 if (!MakeMUL_LOHI(LH, RL, Lo, Hi, false))
5718 return false;
5719
5720 SDValue Zero = DAG.getConstant(0, dl, HiLoVT);
5721 EVT BoolType = getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT);
5722
5723 bool UseGlue = (isOperationLegalOrCustom(ISD::ADDC, VT) &&
5724 isOperationLegalOrCustom(ISD::ADDE, VT));
5725 if (UseGlue)
5726 Next = DAG.getNode(ISD::ADDC, dl, DAG.getVTList(VT, MVT::Glue), Next,
5727 Merge(Lo, Hi));
5728 else
5729 Next = DAG.getNode(ISD::ADDCARRY, dl, DAG.getVTList(VT, BoolType), Next,
5730 Merge(Lo, Hi), DAG.getConstant(0, dl, BoolType));
5731
5732 SDValue Carry = Next.getValue(1);
5733 Result.push_back(DAG.getNode(ISD::TRUNCATE, dl, HiLoVT, Next));
5734 Next = DAG.getNode(ISD::SRL, dl, VT, Next, Shift);
5735
5736 if (!MakeMUL_LOHI(LH, RH, Lo, Hi, Opcode == ISD::SMUL_LOHI))
5737 return false;
5738
5739 if (UseGlue)
5740 Hi = DAG.getNode(ISD::ADDE, dl, DAG.getVTList(HiLoVT, MVT::Glue), Hi, Zero,
5741 Carry);
5742 else
5743 Hi = DAG.getNode(ISD::ADDCARRY, dl, DAG.getVTList(HiLoVT, BoolType), Hi,
5744 Zero, Carry);
5745
5746 Next = DAG.getNode(ISD::ADD, dl, VT, Next, Merge(Lo, Hi));
5747
5748 if (Opcode == ISD::SMUL_LOHI) {
5749 SDValue NextSub = DAG.getNode(ISD::SUB, dl, VT, Next,
5750 DAG.getNode(ISD::ZERO_EXTEND, dl, VT, RL));
5751 Next = DAG.getSelectCC(dl, LH, Zero, NextSub, Next, ISD::SETLT);
5752
5753 NextSub = DAG.getNode(ISD::SUB, dl, VT, Next,
5754 DAG.getNode(ISD::ZERO_EXTEND, dl, VT, LL));
5755 Next = DAG.getSelectCC(dl, RH, Zero, NextSub, Next, ISD::SETLT);
5756 }
5757
5758 Result.push_back(DAG.getNode(ISD::TRUNCATE, dl, HiLoVT, Next));
5759 Next = DAG.getNode(ISD::SRL, dl, VT, Next, Shift);
5760 Result.push_back(DAG.getNode(ISD::TRUNCATE, dl, HiLoVT, Next));
5761 return true;
5762}
5763
5764bool TargetLowering::expandMUL(SDNode *N, SDValue &Lo, SDValue &Hi, EVT HiLoVT,
5765 SelectionDAG &DAG, MulExpansionKind Kind,
5766 SDValue LL, SDValue LH, SDValue RL,
5767 SDValue RH) const {
5768 SmallVector<SDValue, 2> Result;
5769 bool Ok = expandMUL_LOHI(N->getOpcode(), N->getValueType(0), N,
5770 N->getOperand(0), N->getOperand(1), Result, HiLoVT,
5771 DAG, Kind, LL, LH, RL, RH);
5772 if (Ok) {
5773 assert(Result.size() == 2)((Result.size() == 2) ? static_cast<void> (0) : __assert_fail
("Result.size() == 2", "/build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/SelectionDAG/TargetLowering.cpp"
, 5773, __PRETTY_FUNCTION__))
;
5774 Lo = Result[0];
5775 Hi = Result[1];
5776 }
5777 return Ok;
5778}
5779
5780bool TargetLowering::expandFunnelShift(SDNode *Node, SDValue &Result,