File: | llvm/include/llvm/ADT/APInt.h |
Warning: | line 444, column 36 The result of the left shift is undefined due to shifting by '4294967295', which is greater or equal to the width of type 'llvm::APInt::WordType' |
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1 | //===-- TargetLowering.cpp - Implement the TargetLowering class -----------===// | |||
2 | // | |||
3 | // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. | |||
4 | // See https://llvm.org/LICENSE.txt for license information. | |||
5 | // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception | |||
6 | // | |||
7 | //===----------------------------------------------------------------------===// | |||
8 | // | |||
9 | // This implements the TargetLowering class. | |||
10 | // | |||
11 | //===----------------------------------------------------------------------===// | |||
12 | ||||
13 | #include "llvm/CodeGen/TargetLowering.h" | |||
14 | #include "llvm/ADT/STLExtras.h" | |||
15 | #include "llvm/CodeGen/CallingConvLower.h" | |||
16 | #include "llvm/CodeGen/MachineFrameInfo.h" | |||
17 | #include "llvm/CodeGen/MachineFunction.h" | |||
18 | #include "llvm/CodeGen/MachineJumpTableInfo.h" | |||
19 | #include "llvm/CodeGen/MachineRegisterInfo.h" | |||
20 | #include "llvm/CodeGen/SelectionDAG.h" | |||
21 | #include "llvm/CodeGen/TargetRegisterInfo.h" | |||
22 | #include "llvm/CodeGen/TargetSubtargetInfo.h" | |||
23 | #include "llvm/IR/DataLayout.h" | |||
24 | #include "llvm/IR/DerivedTypes.h" | |||
25 | #include "llvm/IR/GlobalVariable.h" | |||
26 | #include "llvm/IR/LLVMContext.h" | |||
27 | #include "llvm/MC/MCAsmInfo.h" | |||
28 | #include "llvm/MC/MCExpr.h" | |||
29 | #include "llvm/Support/ErrorHandling.h" | |||
30 | #include "llvm/Support/KnownBits.h" | |||
31 | #include "llvm/Support/MathExtras.h" | |||
32 | #include "llvm/Target/TargetLoweringObjectFile.h" | |||
33 | #include "llvm/Target/TargetMachine.h" | |||
34 | #include <cctype> | |||
35 | using namespace llvm; | |||
36 | ||||
37 | /// NOTE: The TargetMachine owns TLOF. | |||
38 | TargetLowering::TargetLowering(const TargetMachine &tm) | |||
39 | : TargetLoweringBase(tm) {} | |||
40 | ||||
41 | const char *TargetLowering::getTargetNodeName(unsigned Opcode) const { | |||
42 | return nullptr; | |||
43 | } | |||
44 | ||||
45 | bool TargetLowering::isPositionIndependent() const { | |||
46 | return getTargetMachine().isPositionIndependent(); | |||
47 | } | |||
48 | ||||
49 | /// Check whether a given call node is in tail position within its function. If | |||
50 | /// so, it sets Chain to the input chain of the tail call. | |||
51 | bool TargetLowering::isInTailCallPosition(SelectionDAG &DAG, SDNode *Node, | |||
52 | SDValue &Chain) const { | |||
53 | const Function &F = DAG.getMachineFunction().getFunction(); | |||
54 | ||||
55 | // Conservatively require the attributes of the call to match those of | |||
56 | // the return. Ignore NoAlias and NonNull because they don't affect the | |||
57 | // call sequence. | |||
58 | AttributeList CallerAttrs = F.getAttributes(); | |||
59 | if (AttrBuilder(CallerAttrs, AttributeList::ReturnIndex) | |||
60 | .removeAttribute(Attribute::NoAlias) | |||
61 | .removeAttribute(Attribute::NonNull) | |||
62 | .hasAttributes()) | |||
63 | return false; | |||
64 | ||||
65 | // It's not safe to eliminate the sign / zero extension of the return value. | |||
66 | if (CallerAttrs.hasAttribute(AttributeList::ReturnIndex, Attribute::ZExt) || | |||
67 | CallerAttrs.hasAttribute(AttributeList::ReturnIndex, Attribute::SExt)) | |||
68 | return false; | |||
69 | ||||
70 | // Check if the only use is a function return node. | |||
71 | return isUsedByReturnOnly(Node, Chain); | |||
72 | } | |||
73 | ||||
74 | bool TargetLowering::parametersInCSRMatch(const MachineRegisterInfo &MRI, | |||
75 | const uint32_t *CallerPreservedMask, | |||
76 | const SmallVectorImpl<CCValAssign> &ArgLocs, | |||
77 | const SmallVectorImpl<SDValue> &OutVals) const { | |||
78 | for (unsigned I = 0, E = ArgLocs.size(); I != E; ++I) { | |||
79 | const CCValAssign &ArgLoc = ArgLocs[I]; | |||
80 | if (!ArgLoc.isRegLoc()) | |||
81 | continue; | |||
82 | Register Reg = ArgLoc.getLocReg(); | |||
83 | // Only look at callee saved registers. | |||
84 | if (MachineOperand::clobbersPhysReg(CallerPreservedMask, Reg)) | |||
85 | continue; | |||
86 | // Check that we pass the value used for the caller. | |||
87 | // (We look for a CopyFromReg reading a virtual register that is used | |||
88 | // for the function live-in value of register Reg) | |||
89 | SDValue Value = OutVals[I]; | |||
90 | if (Value->getOpcode() != ISD::CopyFromReg) | |||
91 | return false; | |||
92 | unsigned ArgReg = cast<RegisterSDNode>(Value->getOperand(1))->getReg(); | |||
93 | if (MRI.getLiveInPhysReg(ArgReg) != Reg) | |||
94 | return false; | |||
95 | } | |||
96 | return true; | |||
97 | } | |||
98 | ||||
99 | /// Set CallLoweringInfo attribute flags based on a call instruction | |||
100 | /// and called function attributes. | |||
101 | void TargetLoweringBase::ArgListEntry::setAttributes(const CallBase *Call, | |||
102 | unsigned ArgIdx) { | |||
103 | IsSExt = Call->paramHasAttr(ArgIdx, Attribute::SExt); | |||
104 | IsZExt = Call->paramHasAttr(ArgIdx, Attribute::ZExt); | |||
105 | IsInReg = Call->paramHasAttr(ArgIdx, Attribute::InReg); | |||
106 | IsSRet = Call->paramHasAttr(ArgIdx, Attribute::StructRet); | |||
107 | IsNest = Call->paramHasAttr(ArgIdx, Attribute::Nest); | |||
108 | IsByVal = Call->paramHasAttr(ArgIdx, Attribute::ByVal); | |||
109 | IsInAlloca = Call->paramHasAttr(ArgIdx, Attribute::InAlloca); | |||
110 | IsReturned = Call->paramHasAttr(ArgIdx, Attribute::Returned); | |||
111 | IsSwiftSelf = Call->paramHasAttr(ArgIdx, Attribute::SwiftSelf); | |||
112 | IsSwiftError = Call->paramHasAttr(ArgIdx, Attribute::SwiftError); | |||
113 | Alignment = Call->getParamAlignment(ArgIdx); | |||
114 | ByValType = nullptr; | |||
115 | if (Call->paramHasAttr(ArgIdx, Attribute::ByVal)) | |||
116 | ByValType = Call->getParamByValType(ArgIdx); | |||
117 | } | |||
118 | ||||
119 | /// Generate a libcall taking the given operands as arguments and returning a | |||
120 | /// result of type RetVT. | |||
121 | std::pair<SDValue, SDValue> | |||
122 | TargetLowering::makeLibCall(SelectionDAG &DAG, RTLIB::Libcall LC, EVT RetVT, | |||
123 | ArrayRef<SDValue> Ops, | |||
124 | MakeLibCallOptions CallOptions, | |||
125 | const SDLoc &dl) const { | |||
126 | TargetLowering::ArgListTy Args; | |||
127 | Args.reserve(Ops.size()); | |||
128 | ||||
129 | TargetLowering::ArgListEntry Entry; | |||
130 | for (unsigned i = 0; i < Ops.size(); ++i) { | |||
131 | SDValue NewOp = Ops[i]; | |||
132 | Entry.Node = NewOp; | |||
133 | Entry.Ty = Entry.Node.getValueType().getTypeForEVT(*DAG.getContext()); | |||
134 | Entry.IsSExt = shouldSignExtendTypeInLibCall(NewOp.getValueType(), | |||
135 | CallOptions.IsSExt); | |||
136 | Entry.IsZExt = !Entry.IsSExt; | |||
137 | ||||
138 | if (CallOptions.IsSoften && | |||
139 | !shouldExtendTypeInLibCall(CallOptions.OpsVTBeforeSoften[i])) { | |||
140 | Entry.IsSExt = Entry.IsZExt = false; | |||
141 | } | |||
142 | Args.push_back(Entry); | |||
143 | } | |||
144 | ||||
145 | if (LC == RTLIB::UNKNOWN_LIBCALL) | |||
146 | report_fatal_error("Unsupported library call operation!"); | |||
147 | SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC), | |||
148 | getPointerTy(DAG.getDataLayout())); | |||
149 | ||||
150 | Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext()); | |||
151 | TargetLowering::CallLoweringInfo CLI(DAG); | |||
152 | bool signExtend = shouldSignExtendTypeInLibCall(RetVT, CallOptions.IsSExt); | |||
153 | bool zeroExtend = !signExtend; | |||
154 | ||||
155 | if (CallOptions.IsSoften && | |||
156 | !shouldExtendTypeInLibCall(CallOptions.RetVTBeforeSoften)) { | |||
157 | signExtend = zeroExtend = false; | |||
158 | } | |||
159 | ||||
160 | CLI.setDebugLoc(dl) | |||
161 | .setChain(DAG.getEntryNode()) | |||
162 | .setLibCallee(getLibcallCallingConv(LC), RetTy, Callee, std::move(Args)) | |||
163 | .setNoReturn(CallOptions.DoesNotReturn) | |||
164 | .setDiscardResult(!CallOptions.IsReturnValueUsed) | |||
165 | .setIsPostTypeLegalization(CallOptions.IsPostTypeLegalization) | |||
166 | .setSExtResult(signExtend) | |||
167 | .setZExtResult(zeroExtend); | |||
168 | return LowerCallTo(CLI); | |||
169 | } | |||
170 | ||||
171 | bool | |||
172 | TargetLowering::findOptimalMemOpLowering(std::vector<EVT> &MemOps, | |||
173 | unsigned Limit, uint64_t Size, | |||
174 | unsigned DstAlign, unsigned SrcAlign, | |||
175 | bool IsMemset, | |||
176 | bool ZeroMemset, | |||
177 | bool MemcpyStrSrc, | |||
178 | bool AllowOverlap, | |||
179 | unsigned DstAS, unsigned SrcAS, | |||
180 | const AttributeList &FuncAttributes) const { | |||
181 | // If 'SrcAlign' is zero, that means the memory operation does not need to | |||
182 | // load the value, i.e. memset or memcpy from constant string. Otherwise, | |||
183 | // it's the inferred alignment of the source. 'DstAlign', on the other hand, | |||
184 | // is the specified alignment of the memory operation. If it is zero, that | |||
185 | // means it's possible to change the alignment of the destination. | |||
186 | // 'MemcpyStrSrc' indicates whether the memcpy source is constant so it does | |||
187 | // not need to be loaded. | |||
188 | if (!(SrcAlign == 0 || SrcAlign >= DstAlign)) | |||
189 | return false; | |||
190 | ||||
191 | EVT VT = getOptimalMemOpType(Size, DstAlign, SrcAlign, | |||
192 | IsMemset, ZeroMemset, MemcpyStrSrc, | |||
193 | FuncAttributes); | |||
194 | ||||
195 | if (VT == MVT::Other) { | |||
196 | // Use the largest integer type whose alignment constraints are satisfied. | |||
197 | // We only need to check DstAlign here as SrcAlign is always greater or | |||
198 | // equal to DstAlign (or zero). | |||
199 | VT = MVT::i64; | |||
200 | while (DstAlign && DstAlign < VT.getSizeInBits() / 8 && | |||
201 | !allowsMisalignedMemoryAccesses(VT, DstAS, DstAlign)) | |||
202 | VT = (MVT::SimpleValueType)(VT.getSimpleVT().SimpleTy - 1); | |||
203 | assert(VT.isInteger())((VT.isInteger()) ? static_cast<void> (0) : __assert_fail ("VT.isInteger()", "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 203, __PRETTY_FUNCTION__)); | |||
204 | ||||
205 | // Find the largest legal integer type. | |||
206 | MVT LVT = MVT::i64; | |||
207 | while (!isTypeLegal(LVT)) | |||
208 | LVT = (MVT::SimpleValueType)(LVT.SimpleTy - 1); | |||
209 | assert(LVT.isInteger())((LVT.isInteger()) ? static_cast<void> (0) : __assert_fail ("LVT.isInteger()", "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 209, __PRETTY_FUNCTION__)); | |||
210 | ||||
211 | // If the type we've chosen is larger than the largest legal integer type | |||
212 | // then use that instead. | |||
213 | if (VT.bitsGT(LVT)) | |||
214 | VT = LVT; | |||
215 | } | |||
216 | ||||
217 | unsigned NumMemOps = 0; | |||
218 | while (Size != 0) { | |||
219 | unsigned VTSize = VT.getSizeInBits() / 8; | |||
220 | while (VTSize > Size) { | |||
221 | // For now, only use non-vector load / store's for the left-over pieces. | |||
222 | EVT NewVT = VT; | |||
223 | unsigned NewVTSize; | |||
224 | ||||
225 | bool Found = false; | |||
226 | if (VT.isVector() || VT.isFloatingPoint()) { | |||
227 | NewVT = (VT.getSizeInBits() > 64) ? MVT::i64 : MVT::i32; | |||
228 | if (isOperationLegalOrCustom(ISD::STORE, NewVT) && | |||
229 | isSafeMemOpType(NewVT.getSimpleVT())) | |||
230 | Found = true; | |||
231 | else if (NewVT == MVT::i64 && | |||
232 | isOperationLegalOrCustom(ISD::STORE, MVT::f64) && | |||
233 | isSafeMemOpType(MVT::f64)) { | |||
234 | // i64 is usually not legal on 32-bit targets, but f64 may be. | |||
235 | NewVT = MVT::f64; | |||
236 | Found = true; | |||
237 | } | |||
238 | } | |||
239 | ||||
240 | if (!Found) { | |||
241 | do { | |||
242 | NewVT = (MVT::SimpleValueType)(NewVT.getSimpleVT().SimpleTy - 1); | |||
243 | if (NewVT == MVT::i8) | |||
244 | break; | |||
245 | } while (!isSafeMemOpType(NewVT.getSimpleVT())); | |||
246 | } | |||
247 | NewVTSize = NewVT.getSizeInBits() / 8; | |||
248 | ||||
249 | // If the new VT cannot cover all of the remaining bits, then consider | |||
250 | // issuing a (or a pair of) unaligned and overlapping load / store. | |||
251 | bool Fast; | |||
252 | if (NumMemOps && AllowOverlap && NewVTSize < Size && | |||
253 | allowsMisalignedMemoryAccesses(VT, DstAS, DstAlign, | |||
254 | MachineMemOperand::MONone, &Fast) && | |||
255 | Fast) | |||
256 | VTSize = Size; | |||
257 | else { | |||
258 | VT = NewVT; | |||
259 | VTSize = NewVTSize; | |||
260 | } | |||
261 | } | |||
262 | ||||
263 | if (++NumMemOps > Limit) | |||
264 | return false; | |||
265 | ||||
266 | MemOps.push_back(VT); | |||
267 | Size -= VTSize; | |||
268 | } | |||
269 | ||||
270 | return true; | |||
271 | } | |||
272 | ||||
273 | /// Soften the operands of a comparison. This code is shared among BR_CC, | |||
274 | /// SELECT_CC, and SETCC handlers. | |||
275 | void TargetLowering::softenSetCCOperands(SelectionDAG &DAG, EVT VT, | |||
276 | SDValue &NewLHS, SDValue &NewRHS, | |||
277 | ISD::CondCode &CCCode, | |||
278 | const SDLoc &dl, const SDValue OldLHS, | |||
279 | const SDValue OldRHS) const { | |||
280 | assert((VT == MVT::f32 || VT == MVT::f64 || VT == MVT::f128 || VT == MVT::ppcf128)(((VT == MVT::f32 || VT == MVT::f64 || VT == MVT::f128 || VT == MVT::ppcf128) && "Unsupported setcc type!") ? static_cast <void> (0) : __assert_fail ("(VT == MVT::f32 || VT == MVT::f64 || VT == MVT::f128 || VT == MVT::ppcf128) && \"Unsupported setcc type!\"" , "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 281, __PRETTY_FUNCTION__)) | |||
281 | && "Unsupported setcc type!")(((VT == MVT::f32 || VT == MVT::f64 || VT == MVT::f128 || VT == MVT::ppcf128) && "Unsupported setcc type!") ? static_cast <void> (0) : __assert_fail ("(VT == MVT::f32 || VT == MVT::f64 || VT == MVT::f128 || VT == MVT::ppcf128) && \"Unsupported setcc type!\"" , "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 281, __PRETTY_FUNCTION__)); | |||
282 | ||||
283 | // Expand into one or more soft-fp libcall(s). | |||
284 | RTLIB::Libcall LC1 = RTLIB::UNKNOWN_LIBCALL, LC2 = RTLIB::UNKNOWN_LIBCALL; | |||
285 | bool ShouldInvertCC = false; | |||
286 | switch (CCCode) { | |||
287 | case ISD::SETEQ: | |||
288 | case ISD::SETOEQ: | |||
289 | LC1 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : | |||
290 | (VT == MVT::f64) ? RTLIB::OEQ_F64 : | |||
291 | (VT == MVT::f128) ? RTLIB::OEQ_F128 : RTLIB::OEQ_PPCF128; | |||
292 | break; | |||
293 | case ISD::SETNE: | |||
294 | case ISD::SETUNE: | |||
295 | LC1 = (VT == MVT::f32) ? RTLIB::UNE_F32 : | |||
296 | (VT == MVT::f64) ? RTLIB::UNE_F64 : | |||
297 | (VT == MVT::f128) ? RTLIB::UNE_F128 : RTLIB::UNE_PPCF128; | |||
298 | break; | |||
299 | case ISD::SETGE: | |||
300 | case ISD::SETOGE: | |||
301 | LC1 = (VT == MVT::f32) ? RTLIB::OGE_F32 : | |||
302 | (VT == MVT::f64) ? RTLIB::OGE_F64 : | |||
303 | (VT == MVT::f128) ? RTLIB::OGE_F128 : RTLIB::OGE_PPCF128; | |||
304 | break; | |||
305 | case ISD::SETLT: | |||
306 | case ISD::SETOLT: | |||
307 | LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : | |||
308 | (VT == MVT::f64) ? RTLIB::OLT_F64 : | |||
309 | (VT == MVT::f128) ? RTLIB::OLT_F128 : RTLIB::OLT_PPCF128; | |||
310 | break; | |||
311 | case ISD::SETLE: | |||
312 | case ISD::SETOLE: | |||
313 | LC1 = (VT == MVT::f32) ? RTLIB::OLE_F32 : | |||
314 | (VT == MVT::f64) ? RTLIB::OLE_F64 : | |||
315 | (VT == MVT::f128) ? RTLIB::OLE_F128 : RTLIB::OLE_PPCF128; | |||
316 | break; | |||
317 | case ISD::SETGT: | |||
318 | case ISD::SETOGT: | |||
319 | LC1 = (VT == MVT::f32) ? RTLIB::OGT_F32 : | |||
320 | (VT == MVT::f64) ? RTLIB::OGT_F64 : | |||
321 | (VT == MVT::f128) ? RTLIB::OGT_F128 : RTLIB::OGT_PPCF128; | |||
322 | break; | |||
323 | case ISD::SETUO: | |||
324 | LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : | |||
325 | (VT == MVT::f64) ? RTLIB::UO_F64 : | |||
326 | (VT == MVT::f128) ? RTLIB::UO_F128 : RTLIB::UO_PPCF128; | |||
327 | break; | |||
328 | case ISD::SETO: | |||
329 | LC1 = (VT == MVT::f32) ? RTLIB::O_F32 : | |||
330 | (VT == MVT::f64) ? RTLIB::O_F64 : | |||
331 | (VT == MVT::f128) ? RTLIB::O_F128 : RTLIB::O_PPCF128; | |||
332 | break; | |||
333 | case ISD::SETONE: | |||
334 | // SETONE = SETOLT | SETOGT | |||
335 | LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : | |||
336 | (VT == MVT::f64) ? RTLIB::OLT_F64 : | |||
337 | (VT == MVT::f128) ? RTLIB::OLT_F128 : RTLIB::OLT_PPCF128; | |||
338 | LC2 = (VT == MVT::f32) ? RTLIB::OGT_F32 : | |||
339 | (VT == MVT::f64) ? RTLIB::OGT_F64 : | |||
340 | (VT == MVT::f128) ? RTLIB::OGT_F128 : RTLIB::OGT_PPCF128; | |||
341 | break; | |||
342 | case ISD::SETUEQ: | |||
343 | LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : | |||
344 | (VT == MVT::f64) ? RTLIB::UO_F64 : | |||
345 | (VT == MVT::f128) ? RTLIB::UO_F128 : RTLIB::UO_PPCF128; | |||
346 | LC2 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : | |||
347 | (VT == MVT::f64) ? RTLIB::OEQ_F64 : | |||
348 | (VT == MVT::f128) ? RTLIB::OEQ_F128 : RTLIB::OEQ_PPCF128; | |||
349 | break; | |||
350 | default: | |||
351 | // Invert CC for unordered comparisons | |||
352 | ShouldInvertCC = true; | |||
353 | switch (CCCode) { | |||
354 | case ISD::SETULT: | |||
355 | LC1 = (VT == MVT::f32) ? RTLIB::OGE_F32 : | |||
356 | (VT == MVT::f64) ? RTLIB::OGE_F64 : | |||
357 | (VT == MVT::f128) ? RTLIB::OGE_F128 : RTLIB::OGE_PPCF128; | |||
358 | break; | |||
359 | case ISD::SETULE: | |||
360 | LC1 = (VT == MVT::f32) ? RTLIB::OGT_F32 : | |||
361 | (VT == MVT::f64) ? RTLIB::OGT_F64 : | |||
362 | (VT == MVT::f128) ? RTLIB::OGT_F128 : RTLIB::OGT_PPCF128; | |||
363 | break; | |||
364 | case ISD::SETUGT: | |||
365 | LC1 = (VT == MVT::f32) ? RTLIB::OLE_F32 : | |||
366 | (VT == MVT::f64) ? RTLIB::OLE_F64 : | |||
367 | (VT == MVT::f128) ? RTLIB::OLE_F128 : RTLIB::OLE_PPCF128; | |||
368 | break; | |||
369 | case ISD::SETUGE: | |||
370 | LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : | |||
371 | (VT == MVT::f64) ? RTLIB::OLT_F64 : | |||
372 | (VT == MVT::f128) ? RTLIB::OLT_F128 : RTLIB::OLT_PPCF128; | |||
373 | break; | |||
374 | default: llvm_unreachable("Do not know how to soften this setcc!")::llvm::llvm_unreachable_internal("Do not know how to soften this setcc!" , "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 374); | |||
375 | } | |||
376 | } | |||
377 | ||||
378 | // Use the target specific return value for comparions lib calls. | |||
379 | EVT RetVT = getCmpLibcallReturnType(); | |||
380 | SDValue Ops[2] = {NewLHS, NewRHS}; | |||
381 | TargetLowering::MakeLibCallOptions CallOptions; | |||
382 | EVT OpsVT[2] = { OldLHS.getValueType(), | |||
383 | OldRHS.getValueType() }; | |||
384 | CallOptions.setTypeListBeforeSoften(OpsVT, RetVT, true); | |||
385 | NewLHS = makeLibCall(DAG, LC1, RetVT, Ops, CallOptions, dl).first; | |||
386 | NewRHS = DAG.getConstant(0, dl, RetVT); | |||
387 | ||||
388 | CCCode = getCmpLibcallCC(LC1); | |||
389 | if (ShouldInvertCC) | |||
390 | CCCode = getSetCCInverse(CCCode, /*isInteger=*/true); | |||
391 | ||||
392 | if (LC2 != RTLIB::UNKNOWN_LIBCALL) { | |||
393 | SDValue Tmp = DAG.getNode( | |||
394 | ISD::SETCC, dl, | |||
395 | getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), RetVT), | |||
396 | NewLHS, NewRHS, DAG.getCondCode(CCCode)); | |||
397 | NewLHS = makeLibCall(DAG, LC2, RetVT, Ops, CallOptions, dl).first; | |||
398 | NewLHS = DAG.getNode( | |||
399 | ISD::SETCC, dl, | |||
400 | getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), RetVT), | |||
401 | NewLHS, NewRHS, DAG.getCondCode(getCmpLibcallCC(LC2))); | |||
402 | NewLHS = DAG.getNode(ISD::OR, dl, Tmp.getValueType(), Tmp, NewLHS); | |||
403 | NewRHS = SDValue(); | |||
404 | } | |||
405 | } | |||
406 | ||||
407 | /// Return the entry encoding for a jump table in the current function. The | |||
408 | /// returned value is a member of the MachineJumpTableInfo::JTEntryKind enum. | |||
409 | unsigned TargetLowering::getJumpTableEncoding() const { | |||
410 | // In non-pic modes, just use the address of a block. | |||
411 | if (!isPositionIndependent()) | |||
412 | return MachineJumpTableInfo::EK_BlockAddress; | |||
413 | ||||
414 | // In PIC mode, if the target supports a GPRel32 directive, use it. | |||
415 | if (getTargetMachine().getMCAsmInfo()->getGPRel32Directive() != nullptr) | |||
416 | return MachineJumpTableInfo::EK_GPRel32BlockAddress; | |||
417 | ||||
418 | // Otherwise, use a label difference. | |||
419 | return MachineJumpTableInfo::EK_LabelDifference32; | |||
420 | } | |||
421 | ||||
422 | SDValue TargetLowering::getPICJumpTableRelocBase(SDValue Table, | |||
423 | SelectionDAG &DAG) const { | |||
424 | // If our PIC model is GP relative, use the global offset table as the base. | |||
425 | unsigned JTEncoding = getJumpTableEncoding(); | |||
426 | ||||
427 | if ((JTEncoding == MachineJumpTableInfo::EK_GPRel64BlockAddress) || | |||
428 | (JTEncoding == MachineJumpTableInfo::EK_GPRel32BlockAddress)) | |||
429 | return DAG.getGLOBAL_OFFSET_TABLE(getPointerTy(DAG.getDataLayout())); | |||
430 | ||||
431 | return Table; | |||
432 | } | |||
433 | ||||
434 | /// This returns the relocation base for the given PIC jumptable, the same as | |||
435 | /// getPICJumpTableRelocBase, but as an MCExpr. | |||
436 | const MCExpr * | |||
437 | TargetLowering::getPICJumpTableRelocBaseExpr(const MachineFunction *MF, | |||
438 | unsigned JTI,MCContext &Ctx) const{ | |||
439 | // The normal PIC reloc base is the label at the start of the jump table. | |||
440 | return MCSymbolRefExpr::create(MF->getJTISymbol(JTI, Ctx), Ctx); | |||
441 | } | |||
442 | ||||
443 | bool | |||
444 | TargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const { | |||
445 | const TargetMachine &TM = getTargetMachine(); | |||
446 | const GlobalValue *GV = GA->getGlobal(); | |||
447 | ||||
448 | // If the address is not even local to this DSO we will have to load it from | |||
449 | // a got and then add the offset. | |||
450 | if (!TM.shouldAssumeDSOLocal(*GV->getParent(), GV)) | |||
451 | return false; | |||
452 | ||||
453 | // If the code is position independent we will have to add a base register. | |||
454 | if (isPositionIndependent()) | |||
455 | return false; | |||
456 | ||||
457 | // Otherwise we can do it. | |||
458 | return true; | |||
459 | } | |||
460 | ||||
461 | //===----------------------------------------------------------------------===// | |||
462 | // Optimization Methods | |||
463 | //===----------------------------------------------------------------------===// | |||
464 | ||||
465 | /// If the specified instruction has a constant integer operand and there are | |||
466 | /// bits set in that constant that are not demanded, then clear those bits and | |||
467 | /// return true. | |||
468 | bool TargetLowering::ShrinkDemandedConstant(SDValue Op, const APInt &Demanded, | |||
469 | TargetLoweringOpt &TLO) const { | |||
470 | SDLoc DL(Op); | |||
471 | unsigned Opcode = Op.getOpcode(); | |||
472 | ||||
473 | // Do target-specific constant optimization. | |||
474 | if (targetShrinkDemandedConstant(Op, Demanded, TLO)) | |||
475 | return TLO.New.getNode(); | |||
476 | ||||
477 | // FIXME: ISD::SELECT, ISD::SELECT_CC | |||
478 | switch (Opcode) { | |||
479 | default: | |||
480 | break; | |||
481 | case ISD::XOR: | |||
482 | case ISD::AND: | |||
483 | case ISD::OR: { | |||
484 | auto *Op1C = dyn_cast<ConstantSDNode>(Op.getOperand(1)); | |||
485 | if (!Op1C) | |||
486 | return false; | |||
487 | ||||
488 | // If this is a 'not' op, don't touch it because that's a canonical form. | |||
489 | const APInt &C = Op1C->getAPIntValue(); | |||
490 | if (Opcode == ISD::XOR && Demanded.isSubsetOf(C)) | |||
491 | return false; | |||
492 | ||||
493 | if (!C.isSubsetOf(Demanded)) { | |||
494 | EVT VT = Op.getValueType(); | |||
495 | SDValue NewC = TLO.DAG.getConstant(Demanded & C, DL, VT); | |||
496 | SDValue NewOp = TLO.DAG.getNode(Opcode, DL, VT, Op.getOperand(0), NewC); | |||
497 | return TLO.CombineTo(Op, NewOp); | |||
498 | } | |||
499 | ||||
500 | break; | |||
501 | } | |||
502 | } | |||
503 | ||||
504 | return false; | |||
505 | } | |||
506 | ||||
507 | /// Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the casts are free. | |||
508 | /// This uses isZExtFree and ZERO_EXTEND for the widening cast, but it could be | |||
509 | /// generalized for targets with other types of implicit widening casts. | |||
510 | bool TargetLowering::ShrinkDemandedOp(SDValue Op, unsigned BitWidth, | |||
511 | const APInt &Demanded, | |||
512 | TargetLoweringOpt &TLO) const { | |||
513 | assert(Op.getNumOperands() == 2 &&((Op.getNumOperands() == 2 && "ShrinkDemandedOp only supports binary operators!" ) ? static_cast<void> (0) : __assert_fail ("Op.getNumOperands() == 2 && \"ShrinkDemandedOp only supports binary operators!\"" , "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 514, __PRETTY_FUNCTION__)) | |||
514 | "ShrinkDemandedOp only supports binary operators!")((Op.getNumOperands() == 2 && "ShrinkDemandedOp only supports binary operators!" ) ? static_cast<void> (0) : __assert_fail ("Op.getNumOperands() == 2 && \"ShrinkDemandedOp only supports binary operators!\"" , "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 514, __PRETTY_FUNCTION__)); | |||
515 | assert(Op.getNode()->getNumValues() == 1 &&((Op.getNode()->getNumValues() == 1 && "ShrinkDemandedOp only supports nodes with one result!" ) ? static_cast<void> (0) : __assert_fail ("Op.getNode()->getNumValues() == 1 && \"ShrinkDemandedOp only supports nodes with one result!\"" , "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 516, __PRETTY_FUNCTION__)) | |||
516 | "ShrinkDemandedOp only supports nodes with one result!")((Op.getNode()->getNumValues() == 1 && "ShrinkDemandedOp only supports nodes with one result!" ) ? static_cast<void> (0) : __assert_fail ("Op.getNode()->getNumValues() == 1 && \"ShrinkDemandedOp only supports nodes with one result!\"" , "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 516, __PRETTY_FUNCTION__)); | |||
517 | ||||
518 | SelectionDAG &DAG = TLO.DAG; | |||
519 | SDLoc dl(Op); | |||
520 | ||||
521 | // Early return, as this function cannot handle vector types. | |||
522 | if (Op.getValueType().isVector()) | |||
523 | return false; | |||
524 | ||||
525 | // Don't do this if the node has another user, which may require the | |||
526 | // full value. | |||
527 | if (!Op.getNode()->hasOneUse()) | |||
528 | return false; | |||
529 | ||||
530 | // Search for the smallest integer type with free casts to and from | |||
531 | // Op's type. For expedience, just check power-of-2 integer types. | |||
532 | const TargetLowering &TLI = DAG.getTargetLoweringInfo(); | |||
533 | unsigned DemandedSize = Demanded.getActiveBits(); | |||
534 | unsigned SmallVTBits = DemandedSize; | |||
535 | if (!isPowerOf2_32(SmallVTBits)) | |||
536 | SmallVTBits = NextPowerOf2(SmallVTBits); | |||
537 | for (; SmallVTBits < BitWidth; SmallVTBits = NextPowerOf2(SmallVTBits)) { | |||
538 | EVT SmallVT = EVT::getIntegerVT(*DAG.getContext(), SmallVTBits); | |||
539 | if (TLI.isTruncateFree(Op.getValueType(), SmallVT) && | |||
540 | TLI.isZExtFree(SmallVT, Op.getValueType())) { | |||
541 | // We found a type with free casts. | |||
542 | SDValue X = DAG.getNode( | |||
543 | Op.getOpcode(), dl, SmallVT, | |||
544 | DAG.getNode(ISD::TRUNCATE, dl, SmallVT, Op.getOperand(0)), | |||
545 | DAG.getNode(ISD::TRUNCATE, dl, SmallVT, Op.getOperand(1))); | |||
546 | assert(DemandedSize <= SmallVTBits && "Narrowed below demanded bits?")((DemandedSize <= SmallVTBits && "Narrowed below demanded bits?" ) ? static_cast<void> (0) : __assert_fail ("DemandedSize <= SmallVTBits && \"Narrowed below demanded bits?\"" , "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 546, __PRETTY_FUNCTION__)); | |||
547 | SDValue Z = DAG.getNode(ISD::ANY_EXTEND, dl, Op.getValueType(), X); | |||
548 | return TLO.CombineTo(Op, Z); | |||
549 | } | |||
550 | } | |||
551 | return false; | |||
552 | } | |||
553 | ||||
554 | bool TargetLowering::SimplifyDemandedBits(SDValue Op, const APInt &DemandedBits, | |||
555 | DAGCombinerInfo &DCI) const { | |||
556 | SelectionDAG &DAG = DCI.DAG; | |||
557 | TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(), | |||
558 | !DCI.isBeforeLegalizeOps()); | |||
559 | KnownBits Known; | |||
560 | ||||
561 | bool Simplified = SimplifyDemandedBits(Op, DemandedBits, Known, TLO); | |||
562 | if (Simplified) { | |||
563 | DCI.AddToWorklist(Op.getNode()); | |||
564 | DCI.CommitTargetLoweringOpt(TLO); | |||
565 | } | |||
566 | return Simplified; | |||
567 | } | |||
568 | ||||
569 | bool TargetLowering::SimplifyDemandedBits(SDValue Op, const APInt &DemandedBits, | |||
570 | KnownBits &Known, | |||
571 | TargetLoweringOpt &TLO, | |||
572 | unsigned Depth, | |||
573 | bool AssumeSingleUse) const { | |||
574 | EVT VT = Op.getValueType(); | |||
575 | APInt DemandedElts = VT.isVector() | |||
576 | ? APInt::getAllOnesValue(VT.getVectorNumElements()) | |||
577 | : APInt(1, 1); | |||
578 | return SimplifyDemandedBits(Op, DemandedBits, DemandedElts, Known, TLO, Depth, | |||
579 | AssumeSingleUse); | |||
580 | } | |||
581 | ||||
582 | // TODO: Can we merge SelectionDAG::GetDemandedBits into this? | |||
583 | // TODO: Under what circumstances can we create nodes? Constant folding? | |||
584 | SDValue TargetLowering::SimplifyMultipleUseDemandedBits( | |||
585 | SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts, | |||
586 | SelectionDAG &DAG, unsigned Depth) const { | |||
587 | // Limit search depth. | |||
588 | if (Depth >= SelectionDAG::MaxRecursionDepth) | |||
589 | return SDValue(); | |||
590 | ||||
591 | // Ignore UNDEFs. | |||
592 | if (Op.isUndef()) | |||
593 | return SDValue(); | |||
594 | ||||
595 | // Not demanding any bits/elts from Op. | |||
596 | if (DemandedBits == 0 || DemandedElts == 0) | |||
597 | return DAG.getUNDEF(Op.getValueType()); | |||
598 | ||||
599 | unsigned NumElts = DemandedElts.getBitWidth(); | |||
600 | KnownBits LHSKnown, RHSKnown; | |||
601 | switch (Op.getOpcode()) { | |||
602 | case ISD::BITCAST: { | |||
603 | SDValue Src = peekThroughBitcasts(Op.getOperand(0)); | |||
604 | EVT SrcVT = Src.getValueType(); | |||
605 | EVT DstVT = Op.getValueType(); | |||
606 | unsigned NumSrcEltBits = SrcVT.getScalarSizeInBits(); | |||
607 | unsigned NumDstEltBits = DstVT.getScalarSizeInBits(); | |||
608 | ||||
609 | if (NumSrcEltBits == NumDstEltBits) | |||
610 | if (SDValue V = SimplifyMultipleUseDemandedBits( | |||
611 | Src, DemandedBits, DemandedElts, DAG, Depth + 1)) | |||
612 | return DAG.getBitcast(DstVT, V); | |||
613 | ||||
614 | // TODO - bigendian once we have test coverage. | |||
615 | if (SrcVT.isVector() && (NumDstEltBits % NumSrcEltBits) == 0 && | |||
616 | DAG.getDataLayout().isLittleEndian()) { | |||
617 | unsigned Scale = NumDstEltBits / NumSrcEltBits; | |||
618 | unsigned NumSrcElts = SrcVT.getVectorNumElements(); | |||
619 | APInt DemandedSrcBits = APInt::getNullValue(NumSrcEltBits); | |||
620 | APInt DemandedSrcElts = APInt::getNullValue(NumSrcElts); | |||
621 | for (unsigned i = 0; i != Scale; ++i) { | |||
622 | unsigned Offset = i * NumSrcEltBits; | |||
623 | APInt Sub = DemandedBits.extractBits(NumSrcEltBits, Offset); | |||
624 | if (!Sub.isNullValue()) { | |||
625 | DemandedSrcBits |= Sub; | |||
626 | for (unsigned j = 0; j != NumElts; ++j) | |||
627 | if (DemandedElts[j]) | |||
628 | DemandedSrcElts.setBit((j * Scale) + i); | |||
629 | } | |||
630 | } | |||
631 | ||||
632 | if (SDValue V = SimplifyMultipleUseDemandedBits( | |||
633 | Src, DemandedSrcBits, DemandedSrcElts, DAG, Depth + 1)) | |||
634 | return DAG.getBitcast(DstVT, V); | |||
635 | } | |||
636 | ||||
637 | // TODO - bigendian once we have test coverage. | |||
638 | if ((NumSrcEltBits % NumDstEltBits) == 0 && | |||
639 | DAG.getDataLayout().isLittleEndian()) { | |||
640 | unsigned Scale = NumSrcEltBits / NumDstEltBits; | |||
641 | unsigned NumSrcElts = SrcVT.isVector() ? SrcVT.getVectorNumElements() : 1; | |||
642 | APInt DemandedSrcBits = APInt::getNullValue(NumSrcEltBits); | |||
643 | APInt DemandedSrcElts = APInt::getNullValue(NumSrcElts); | |||
644 | for (unsigned i = 0; i != NumElts; ++i) | |||
645 | if (DemandedElts[i]) { | |||
646 | unsigned Offset = (i % Scale) * NumDstEltBits; | |||
647 | DemandedSrcBits.insertBits(DemandedBits, Offset); | |||
648 | DemandedSrcElts.setBit(i / Scale); | |||
649 | } | |||
650 | ||||
651 | if (SDValue V = SimplifyMultipleUseDemandedBits( | |||
652 | Src, DemandedSrcBits, DemandedSrcElts, DAG, Depth + 1)) | |||
653 | return DAG.getBitcast(DstVT, V); | |||
654 | } | |||
655 | ||||
656 | break; | |||
657 | } | |||
658 | case ISD::AND: { | |||
659 | LHSKnown = DAG.computeKnownBits(Op.getOperand(0), DemandedElts, Depth + 1); | |||
660 | RHSKnown = DAG.computeKnownBits(Op.getOperand(1), DemandedElts, Depth + 1); | |||
661 | ||||
662 | // If all of the demanded bits are known 1 on one side, return the other. | |||
663 | // These bits cannot contribute to the result of the 'and' in this | |||
664 | // context. | |||
665 | if (DemandedBits.isSubsetOf(LHSKnown.Zero | RHSKnown.One)) | |||
666 | return Op.getOperand(0); | |||
667 | if (DemandedBits.isSubsetOf(RHSKnown.Zero | LHSKnown.One)) | |||
668 | return Op.getOperand(1); | |||
669 | break; | |||
670 | } | |||
671 | case ISD::OR: { | |||
672 | LHSKnown = DAG.computeKnownBits(Op.getOperand(0), DemandedElts, Depth + 1); | |||
673 | RHSKnown = DAG.computeKnownBits(Op.getOperand(1), DemandedElts, Depth + 1); | |||
674 | ||||
675 | // If all of the demanded bits are known zero on one side, return the | |||
676 | // other. These bits cannot contribute to the result of the 'or' in this | |||
677 | // context. | |||
678 | if (DemandedBits.isSubsetOf(LHSKnown.One | RHSKnown.Zero)) | |||
679 | return Op.getOperand(0); | |||
680 | if (DemandedBits.isSubsetOf(RHSKnown.One | LHSKnown.Zero)) | |||
681 | return Op.getOperand(1); | |||
682 | break; | |||
683 | } | |||
684 | case ISD::XOR: { | |||
685 | LHSKnown = DAG.computeKnownBits(Op.getOperand(0), DemandedElts, Depth + 1); | |||
686 | RHSKnown = DAG.computeKnownBits(Op.getOperand(1), DemandedElts, Depth + 1); | |||
687 | ||||
688 | // If all of the demanded bits are known zero on one side, return the | |||
689 | // other. | |||
690 | if (DemandedBits.isSubsetOf(RHSKnown.Zero)) | |||
691 | return Op.getOperand(0); | |||
692 | if (DemandedBits.isSubsetOf(LHSKnown.Zero)) | |||
693 | return Op.getOperand(1); | |||
694 | break; | |||
695 | } | |||
696 | case ISD::SIGN_EXTEND_INREG: { | |||
697 | // If none of the extended bits are demanded, eliminate the sextinreg. | |||
698 | EVT ExVT = cast<VTSDNode>(Op.getOperand(1))->getVT(); | |||
699 | if (DemandedBits.getActiveBits() <= ExVT.getScalarSizeInBits()) | |||
700 | return Op.getOperand(0); | |||
701 | break; | |||
702 | } | |||
703 | case ISD::INSERT_VECTOR_ELT: { | |||
704 | // If we don't demand the inserted element, return the base vector. | |||
705 | SDValue Vec = Op.getOperand(0); | |||
706 | auto *CIdx = dyn_cast<ConstantSDNode>(Op.getOperand(2)); | |||
707 | EVT VecVT = Vec.getValueType(); | |||
708 | if (CIdx && CIdx->getAPIntValue().ult(VecVT.getVectorNumElements()) && | |||
709 | !DemandedElts[CIdx->getZExtValue()]) | |||
710 | return Vec; | |||
711 | break; | |||
712 | } | |||
713 | case ISD::VECTOR_SHUFFLE: { | |||
714 | ArrayRef<int> ShuffleMask = cast<ShuffleVectorSDNode>(Op)->getMask(); | |||
715 | ||||
716 | // If all the demanded elts are from one operand and are inline, | |||
717 | // then we can use the operand directly. | |||
718 | bool AllUndef = true, IdentityLHS = true, IdentityRHS = true; | |||
719 | for (unsigned i = 0; i != NumElts; ++i) { | |||
720 | int M = ShuffleMask[i]; | |||
721 | if (M < 0 || !DemandedElts[i]) | |||
722 | continue; | |||
723 | AllUndef = false; | |||
724 | IdentityLHS &= (M == (int)i); | |||
725 | IdentityRHS &= ((M - NumElts) == i); | |||
726 | } | |||
727 | ||||
728 | if (AllUndef) | |||
729 | return DAG.getUNDEF(Op.getValueType()); | |||
730 | if (IdentityLHS) | |||
731 | return Op.getOperand(0); | |||
732 | if (IdentityRHS) | |||
733 | return Op.getOperand(1); | |||
734 | break; | |||
735 | } | |||
736 | default: | |||
737 | if (Op.getOpcode() >= ISD::BUILTIN_OP_END) | |||
738 | if (SDValue V = SimplifyMultipleUseDemandedBitsForTargetNode( | |||
739 | Op, DemandedBits, DemandedElts, DAG, Depth)) | |||
740 | return V; | |||
741 | break; | |||
742 | } | |||
743 | return SDValue(); | |||
744 | } | |||
745 | ||||
746 | /// Look at Op. At this point, we know that only the OriginalDemandedBits of the | |||
747 | /// result of Op are ever used downstream. If we can use this information to | |||
748 | /// simplify Op, create a new simplified DAG node and return true, returning the | |||
749 | /// original and new nodes in Old and New. Otherwise, analyze the expression and | |||
750 | /// return a mask of Known bits for the expression (used to simplify the | |||
751 | /// caller). The Known bits may only be accurate for those bits in the | |||
752 | /// OriginalDemandedBits and OriginalDemandedElts. | |||
753 | bool TargetLowering::SimplifyDemandedBits( | |||
754 | SDValue Op, const APInt &OriginalDemandedBits, | |||
755 | const APInt &OriginalDemandedElts, KnownBits &Known, TargetLoweringOpt &TLO, | |||
756 | unsigned Depth, bool AssumeSingleUse) const { | |||
757 | unsigned BitWidth = OriginalDemandedBits.getBitWidth(); | |||
758 | assert(Op.getScalarValueSizeInBits() == BitWidth &&((Op.getScalarValueSizeInBits() == BitWidth && "Mask size mismatches value type size!" ) ? static_cast<void> (0) : __assert_fail ("Op.getScalarValueSizeInBits() == BitWidth && \"Mask size mismatches value type size!\"" , "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 759, __PRETTY_FUNCTION__)) | |||
759 | "Mask size mismatches value type size!")((Op.getScalarValueSizeInBits() == BitWidth && "Mask size mismatches value type size!" ) ? static_cast<void> (0) : __assert_fail ("Op.getScalarValueSizeInBits() == BitWidth && \"Mask size mismatches value type size!\"" , "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 759, __PRETTY_FUNCTION__)); | |||
760 | ||||
761 | unsigned NumElts = OriginalDemandedElts.getBitWidth(); | |||
762 | assert((!Op.getValueType().isVector() ||(((!Op.getValueType().isVector() || NumElts == Op.getValueType ().getVectorNumElements()) && "Unexpected vector size" ) ? static_cast<void> (0) : __assert_fail ("(!Op.getValueType().isVector() || NumElts == Op.getValueType().getVectorNumElements()) && \"Unexpected vector size\"" , "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 764, __PRETTY_FUNCTION__)) | |||
763 | NumElts == Op.getValueType().getVectorNumElements()) &&(((!Op.getValueType().isVector() || NumElts == Op.getValueType ().getVectorNumElements()) && "Unexpected vector size" ) ? static_cast<void> (0) : __assert_fail ("(!Op.getValueType().isVector() || NumElts == Op.getValueType().getVectorNumElements()) && \"Unexpected vector size\"" , "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 764, __PRETTY_FUNCTION__)) | |||
764 | "Unexpected vector size")(((!Op.getValueType().isVector() || NumElts == Op.getValueType ().getVectorNumElements()) && "Unexpected vector size" ) ? static_cast<void> (0) : __assert_fail ("(!Op.getValueType().isVector() || NumElts == Op.getValueType().getVectorNumElements()) && \"Unexpected vector size\"" , "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 764, __PRETTY_FUNCTION__)); | |||
765 | ||||
766 | APInt DemandedBits = OriginalDemandedBits; | |||
767 | APInt DemandedElts = OriginalDemandedElts; | |||
768 | SDLoc dl(Op); | |||
769 | auto &DL = TLO.DAG.getDataLayout(); | |||
770 | ||||
771 | // Don't know anything. | |||
772 | Known = KnownBits(BitWidth); | |||
773 | ||||
774 | // Undef operand. | |||
775 | if (Op.isUndef()) | |||
776 | return false; | |||
777 | ||||
778 | if (Op.getOpcode() == ISD::Constant) { | |||
779 | // We know all of the bits for a constant! | |||
780 | Known.One = cast<ConstantSDNode>(Op)->getAPIntValue(); | |||
781 | Known.Zero = ~Known.One; | |||
782 | return false; | |||
783 | } | |||
784 | ||||
785 | // Other users may use these bits. | |||
786 | EVT VT = Op.getValueType(); | |||
787 | if (!Op.getNode()->hasOneUse() && !AssumeSingleUse) { | |||
788 | if (Depth != 0) { | |||
789 | // If not at the root, Just compute the Known bits to | |||
790 | // simplify things downstream. | |||
791 | Known = TLO.DAG.computeKnownBits(Op, DemandedElts, Depth); | |||
792 | return false; | |||
793 | } | |||
794 | // If this is the root being simplified, allow it to have multiple uses, | |||
795 | // just set the DemandedBits/Elts to all bits. | |||
796 | DemandedBits = APInt::getAllOnesValue(BitWidth); | |||
797 | DemandedElts = APInt::getAllOnesValue(NumElts); | |||
798 | } else if (OriginalDemandedBits == 0 || OriginalDemandedElts == 0) { | |||
799 | // Not demanding any bits/elts from Op. | |||
800 | return TLO.CombineTo(Op, TLO.DAG.getUNDEF(VT)); | |||
801 | } else if (Depth >= SelectionDAG::MaxRecursionDepth) { | |||
802 | // Limit search depth. | |||
803 | return false; | |||
804 | } | |||
805 | ||||
806 | KnownBits Known2, KnownOut; | |||
807 | switch (Op.getOpcode()) { | |||
808 | case ISD::TargetConstant: | |||
809 | llvm_unreachable("Can't simplify this node")::llvm::llvm_unreachable_internal("Can't simplify this node", "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 809); | |||
810 | case ISD::SCALAR_TO_VECTOR: { | |||
811 | if (!DemandedElts[0]) | |||
812 | return TLO.CombineTo(Op, TLO.DAG.getUNDEF(VT)); | |||
813 | ||||
814 | KnownBits SrcKnown; | |||
815 | SDValue Src = Op.getOperand(0); | |||
816 | unsigned SrcBitWidth = Src.getScalarValueSizeInBits(); | |||
817 | APInt SrcDemandedBits = DemandedBits.zextOrSelf(SrcBitWidth); | |||
818 | if (SimplifyDemandedBits(Src, SrcDemandedBits, SrcKnown, TLO, Depth + 1)) | |||
819 | return true; | |||
820 | Known = SrcKnown.zextOrTrunc(BitWidth, false); | |||
821 | break; | |||
822 | } | |||
823 | case ISD::BUILD_VECTOR: | |||
824 | // Collect the known bits that are shared by every demanded element. | |||
825 | // TODO: Call SimplifyDemandedBits for non-constant demanded elements. | |||
826 | Known = TLO.DAG.computeKnownBits(Op, DemandedElts, Depth); | |||
827 | return false; // Don't fall through, will infinitely loop. | |||
828 | case ISD::LOAD: { | |||
829 | LoadSDNode *LD = cast<LoadSDNode>(Op); | |||
830 | if (getTargetConstantFromLoad(LD)) { | |||
831 | Known = TLO.DAG.computeKnownBits(Op, DemandedElts, Depth); | |||
832 | return false; // Don't fall through, will infinitely loop. | |||
833 | } | |||
834 | break; | |||
835 | } | |||
836 | case ISD::INSERT_VECTOR_ELT: { | |||
837 | SDValue Vec = Op.getOperand(0); | |||
838 | SDValue Scl = Op.getOperand(1); | |||
839 | auto *CIdx = dyn_cast<ConstantSDNode>(Op.getOperand(2)); | |||
840 | EVT VecVT = Vec.getValueType(); | |||
841 | ||||
842 | // If index isn't constant, assume we need all vector elements AND the | |||
843 | // inserted element. | |||
844 | APInt DemandedVecElts(DemandedElts); | |||
845 | if (CIdx && CIdx->getAPIntValue().ult(VecVT.getVectorNumElements())) { | |||
846 | unsigned Idx = CIdx->getZExtValue(); | |||
847 | DemandedVecElts.clearBit(Idx); | |||
848 | ||||
849 | // Inserted element is not required. | |||
850 | if (!DemandedElts[Idx]) | |||
851 | return TLO.CombineTo(Op, Vec); | |||
852 | } | |||
853 | ||||
854 | KnownBits KnownScl; | |||
855 | unsigned NumSclBits = Scl.getScalarValueSizeInBits(); | |||
856 | APInt DemandedSclBits = DemandedBits.zextOrTrunc(NumSclBits); | |||
857 | if (SimplifyDemandedBits(Scl, DemandedSclBits, KnownScl, TLO, Depth + 1)) | |||
858 | return true; | |||
859 | ||||
860 | Known = KnownScl.zextOrTrunc(BitWidth, false); | |||
861 | ||||
862 | KnownBits KnownVec; | |||
863 | if (SimplifyDemandedBits(Vec, DemandedBits, DemandedVecElts, KnownVec, TLO, | |||
864 | Depth + 1)) | |||
865 | return true; | |||
866 | ||||
867 | if (!!DemandedVecElts) { | |||
868 | Known.One &= KnownVec.One; | |||
869 | Known.Zero &= KnownVec.Zero; | |||
870 | } | |||
871 | ||||
872 | return false; | |||
873 | } | |||
874 | case ISD::INSERT_SUBVECTOR: { | |||
875 | SDValue Base = Op.getOperand(0); | |||
876 | SDValue Sub = Op.getOperand(1); | |||
877 | EVT SubVT = Sub.getValueType(); | |||
878 | unsigned NumSubElts = SubVT.getVectorNumElements(); | |||
879 | ||||
880 | // If index isn't constant, assume we need the original demanded base | |||
881 | // elements and ALL the inserted subvector elements. | |||
882 | APInt BaseElts = DemandedElts; | |||
883 | APInt SubElts = APInt::getAllOnesValue(NumSubElts); | |||
884 | if (isa<ConstantSDNode>(Op.getOperand(2))) { | |||
885 | const APInt &Idx = Op.getConstantOperandAPInt(2); | |||
886 | if (Idx.ule(NumElts - NumSubElts)) { | |||
887 | unsigned SubIdx = Idx.getZExtValue(); | |||
888 | SubElts = DemandedElts.extractBits(NumSubElts, SubIdx); | |||
889 | BaseElts.insertBits(APInt::getNullValue(NumSubElts), SubIdx); | |||
890 | } | |||
891 | } | |||
892 | ||||
893 | KnownBits KnownSub, KnownBase; | |||
894 | if (SimplifyDemandedBits(Sub, DemandedBits, SubElts, KnownSub, TLO, | |||
895 | Depth + 1)) | |||
896 | return true; | |||
897 | if (SimplifyDemandedBits(Base, DemandedBits, BaseElts, KnownBase, TLO, | |||
898 | Depth + 1)) | |||
899 | return true; | |||
900 | ||||
901 | Known.Zero.setAllBits(); | |||
902 | Known.One.setAllBits(); | |||
903 | if (!!SubElts) { | |||
904 | Known.One &= KnownSub.One; | |||
905 | Known.Zero &= KnownSub.Zero; | |||
906 | } | |||
907 | if (!!BaseElts) { | |||
908 | Known.One &= KnownBase.One; | |||
909 | Known.Zero &= KnownBase.Zero; | |||
910 | } | |||
911 | break; | |||
912 | } | |||
913 | case ISD::EXTRACT_SUBVECTOR: { | |||
914 | // If index isn't constant, assume we need all the source vector elements. | |||
915 | SDValue Src = Op.getOperand(0); | |||
916 | ConstantSDNode *SubIdx = dyn_cast<ConstantSDNode>(Op.getOperand(1)); | |||
917 | unsigned NumSrcElts = Src.getValueType().getVectorNumElements(); | |||
918 | APInt SrcElts = APInt::getAllOnesValue(NumSrcElts); | |||
919 | if (SubIdx && SubIdx->getAPIntValue().ule(NumSrcElts - NumElts)) { | |||
920 | // Offset the demanded elts by the subvector index. | |||
921 | uint64_t Idx = SubIdx->getZExtValue(); | |||
922 | SrcElts = DemandedElts.zextOrSelf(NumSrcElts).shl(Idx); | |||
923 | } | |||
924 | if (SimplifyDemandedBits(Src, DemandedBits, SrcElts, Known, TLO, Depth + 1)) | |||
925 | return true; | |||
926 | break; | |||
927 | } | |||
928 | case ISD::CONCAT_VECTORS: { | |||
929 | Known.Zero.setAllBits(); | |||
930 | Known.One.setAllBits(); | |||
931 | EVT SubVT = Op.getOperand(0).getValueType(); | |||
932 | unsigned NumSubVecs = Op.getNumOperands(); | |||
933 | unsigned NumSubElts = SubVT.getVectorNumElements(); | |||
934 | for (unsigned i = 0; i != NumSubVecs; ++i) { | |||
935 | APInt DemandedSubElts = | |||
936 | DemandedElts.extractBits(NumSubElts, i * NumSubElts); | |||
937 | if (SimplifyDemandedBits(Op.getOperand(i), DemandedBits, DemandedSubElts, | |||
938 | Known2, TLO, Depth + 1)) | |||
939 | return true; | |||
940 | // Known bits are shared by every demanded subvector element. | |||
941 | if (!!DemandedSubElts) { | |||
942 | Known.One &= Known2.One; | |||
943 | Known.Zero &= Known2.Zero; | |||
944 | } | |||
945 | } | |||
946 | break; | |||
947 | } | |||
948 | case ISD::VECTOR_SHUFFLE: { | |||
949 | ArrayRef<int> ShuffleMask = cast<ShuffleVectorSDNode>(Op)->getMask(); | |||
950 | ||||
951 | // Collect demanded elements from shuffle operands.. | |||
952 | APInt DemandedLHS(NumElts, 0); | |||
953 | APInt DemandedRHS(NumElts, 0); | |||
954 | for (unsigned i = 0; i != NumElts; ++i) { | |||
955 | if (!DemandedElts[i]) | |||
956 | continue; | |||
957 | int M = ShuffleMask[i]; | |||
958 | if (M < 0) { | |||
959 | // For UNDEF elements, we don't know anything about the common state of | |||
960 | // the shuffle result. | |||
961 | DemandedLHS.clearAllBits(); | |||
962 | DemandedRHS.clearAllBits(); | |||
963 | break; | |||
964 | } | |||
965 | assert(0 <= M && M < (int)(2 * NumElts) && "Shuffle index out of range")((0 <= M && M < (int)(2 * NumElts) && "Shuffle index out of range" ) ? static_cast<void> (0) : __assert_fail ("0 <= M && M < (int)(2 * NumElts) && \"Shuffle index out of range\"" , "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 965, __PRETTY_FUNCTION__)); | |||
966 | if (M < (int)NumElts) | |||
967 | DemandedLHS.setBit(M); | |||
968 | else | |||
969 | DemandedRHS.setBit(M - NumElts); | |||
970 | } | |||
971 | ||||
972 | if (!!DemandedLHS || !!DemandedRHS) { | |||
973 | SDValue Op0 = Op.getOperand(0); | |||
974 | SDValue Op1 = Op.getOperand(1); | |||
975 | ||||
976 | Known.Zero.setAllBits(); | |||
977 | Known.One.setAllBits(); | |||
978 | if (!!DemandedLHS) { | |||
979 | if (SimplifyDemandedBits(Op0, DemandedBits, DemandedLHS, Known2, TLO, | |||
980 | Depth + 1)) | |||
981 | return true; | |||
982 | Known.One &= Known2.One; | |||
983 | Known.Zero &= Known2.Zero; | |||
984 | } | |||
985 | if (!!DemandedRHS) { | |||
986 | if (SimplifyDemandedBits(Op1, DemandedBits, DemandedRHS, Known2, TLO, | |||
987 | Depth + 1)) | |||
988 | return true; | |||
989 | Known.One &= Known2.One; | |||
990 | Known.Zero &= Known2.Zero; | |||
991 | } | |||
992 | ||||
993 | // Attempt to avoid multi-use ops if we don't need anything from them. | |||
994 | SDValue DemandedOp0 = SimplifyMultipleUseDemandedBits( | |||
995 | Op0, DemandedBits, DemandedLHS, TLO.DAG, Depth + 1); | |||
996 | SDValue DemandedOp1 = SimplifyMultipleUseDemandedBits( | |||
997 | Op1, DemandedBits, DemandedRHS, TLO.DAG, Depth + 1); | |||
998 | if (DemandedOp0 || DemandedOp1) { | |||
999 | Op0 = DemandedOp0 ? DemandedOp0 : Op0; | |||
1000 | Op1 = DemandedOp1 ? DemandedOp1 : Op1; | |||
1001 | SDValue NewOp = TLO.DAG.getVectorShuffle(VT, dl, Op0, Op1, ShuffleMask); | |||
1002 | return TLO.CombineTo(Op, NewOp); | |||
1003 | } | |||
1004 | } | |||
1005 | break; | |||
1006 | } | |||
1007 | case ISD::AND: { | |||
1008 | SDValue Op0 = Op.getOperand(0); | |||
1009 | SDValue Op1 = Op.getOperand(1); | |||
1010 | ||||
1011 | // If the RHS is a constant, check to see if the LHS would be zero without | |||
1012 | // using the bits from the RHS. Below, we use knowledge about the RHS to | |||
1013 | // simplify the LHS, here we're using information from the LHS to simplify | |||
1014 | // the RHS. | |||
1015 | if (ConstantSDNode *RHSC = isConstOrConstSplat(Op1)) { | |||
1016 | // Do not increment Depth here; that can cause an infinite loop. | |||
1017 | KnownBits LHSKnown = TLO.DAG.computeKnownBits(Op0, DemandedElts, Depth); | |||
1018 | // If the LHS already has zeros where RHSC does, this 'and' is dead. | |||
1019 | if ((LHSKnown.Zero & DemandedBits) == | |||
1020 | (~RHSC->getAPIntValue() & DemandedBits)) | |||
1021 | return TLO.CombineTo(Op, Op0); | |||
1022 | ||||
1023 | // If any of the set bits in the RHS are known zero on the LHS, shrink | |||
1024 | // the constant. | |||
1025 | if (ShrinkDemandedConstant(Op, ~LHSKnown.Zero & DemandedBits, TLO)) | |||
1026 | return true; | |||
1027 | ||||
1028 | // Bitwise-not (xor X, -1) is a special case: we don't usually shrink its | |||
1029 | // constant, but if this 'and' is only clearing bits that were just set by | |||
1030 | // the xor, then this 'and' can be eliminated by shrinking the mask of | |||
1031 | // the xor. For example, for a 32-bit X: | |||
1032 | // and (xor (srl X, 31), -1), 1 --> xor (srl X, 31), 1 | |||
1033 | if (isBitwiseNot(Op0) && Op0.hasOneUse() && | |||
1034 | LHSKnown.One == ~RHSC->getAPIntValue()) { | |||
1035 | SDValue Xor = TLO.DAG.getNode(ISD::XOR, dl, VT, Op0.getOperand(0), Op1); | |||
1036 | return TLO.CombineTo(Op, Xor); | |||
1037 | } | |||
1038 | } | |||
1039 | ||||
1040 | if (SimplifyDemandedBits(Op1, DemandedBits, DemandedElts, Known, TLO, | |||
1041 | Depth + 1)) | |||
1042 | return true; | |||
1043 | assert(!Known.hasConflict() && "Bits known to be one AND zero?")((!Known.hasConflict() && "Bits known to be one AND zero?" ) ? static_cast<void> (0) : __assert_fail ("!Known.hasConflict() && \"Bits known to be one AND zero?\"" , "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 1043, __PRETTY_FUNCTION__)); | |||
1044 | if (SimplifyDemandedBits(Op0, ~Known.Zero & DemandedBits, DemandedElts, | |||
1045 | Known2, TLO, Depth + 1)) | |||
1046 | return true; | |||
1047 | assert(!Known2.hasConflict() && "Bits known to be one AND zero?")((!Known2.hasConflict() && "Bits known to be one AND zero?" ) ? static_cast<void> (0) : __assert_fail ("!Known2.hasConflict() && \"Bits known to be one AND zero?\"" , "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 1047, __PRETTY_FUNCTION__)); | |||
1048 | ||||
1049 | // Attempt to avoid multi-use ops if we don't need anything from them. | |||
1050 | if (!DemandedBits.isAllOnesValue() || !DemandedElts.isAllOnesValue()) { | |||
1051 | SDValue DemandedOp0 = SimplifyMultipleUseDemandedBits( | |||
1052 | Op0, DemandedBits, DemandedElts, TLO.DAG, Depth + 1); | |||
1053 | SDValue DemandedOp1 = SimplifyMultipleUseDemandedBits( | |||
1054 | Op1, DemandedBits, DemandedElts, TLO.DAG, Depth + 1); | |||
1055 | if (DemandedOp0 || DemandedOp1) { | |||
1056 | Op0 = DemandedOp0 ? DemandedOp0 : Op0; | |||
1057 | Op1 = DemandedOp1 ? DemandedOp1 : Op1; | |||
1058 | SDValue NewOp = TLO.DAG.getNode(Op.getOpcode(), dl, VT, Op0, Op1); | |||
1059 | return TLO.CombineTo(Op, NewOp); | |||
1060 | } | |||
1061 | } | |||
1062 | ||||
1063 | // If all of the demanded bits are known one on one side, return the other. | |||
1064 | // These bits cannot contribute to the result of the 'and'. | |||
1065 | if (DemandedBits.isSubsetOf(Known2.Zero | Known.One)) | |||
1066 | return TLO.CombineTo(Op, Op0); | |||
1067 | if (DemandedBits.isSubsetOf(Known.Zero | Known2.One)) | |||
1068 | return TLO.CombineTo(Op, Op1); | |||
1069 | // If all of the demanded bits in the inputs are known zeros, return zero. | |||
1070 | if (DemandedBits.isSubsetOf(Known.Zero | Known2.Zero)) | |||
1071 | return TLO.CombineTo(Op, TLO.DAG.getConstant(0, dl, VT)); | |||
1072 | // If the RHS is a constant, see if we can simplify it. | |||
1073 | if (ShrinkDemandedConstant(Op, ~Known2.Zero & DemandedBits, TLO)) | |||
1074 | return true; | |||
1075 | // If the operation can be done in a smaller type, do so. | |||
1076 | if (ShrinkDemandedOp(Op, BitWidth, DemandedBits, TLO)) | |||
1077 | return true; | |||
1078 | ||||
1079 | // Output known-1 bits are only known if set in both the LHS & RHS. | |||
1080 | Known.One &= Known2.One; | |||
1081 | // Output known-0 are known to be clear if zero in either the LHS | RHS. | |||
1082 | Known.Zero |= Known2.Zero; | |||
1083 | break; | |||
1084 | } | |||
1085 | case ISD::OR: { | |||
1086 | SDValue Op0 = Op.getOperand(0); | |||
1087 | SDValue Op1 = Op.getOperand(1); | |||
1088 | ||||
1089 | if (SimplifyDemandedBits(Op1, DemandedBits, DemandedElts, Known, TLO, | |||
1090 | Depth + 1)) | |||
1091 | return true; | |||
1092 | assert(!Known.hasConflict() && "Bits known to be one AND zero?")((!Known.hasConflict() && "Bits known to be one AND zero?" ) ? static_cast<void> (0) : __assert_fail ("!Known.hasConflict() && \"Bits known to be one AND zero?\"" , "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 1092, __PRETTY_FUNCTION__)); | |||
1093 | if (SimplifyDemandedBits(Op0, ~Known.One & DemandedBits, DemandedElts, | |||
1094 | Known2, TLO, Depth + 1)) | |||
1095 | return true; | |||
1096 | assert(!Known2.hasConflict() && "Bits known to be one AND zero?")((!Known2.hasConflict() && "Bits known to be one AND zero?" ) ? static_cast<void> (0) : __assert_fail ("!Known2.hasConflict() && \"Bits known to be one AND zero?\"" , "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 1096, __PRETTY_FUNCTION__)); | |||
1097 | ||||
1098 | // Attempt to avoid multi-use ops if we don't need anything from them. | |||
1099 | if (!DemandedBits.isAllOnesValue() || !DemandedElts.isAllOnesValue()) { | |||
1100 | SDValue DemandedOp0 = SimplifyMultipleUseDemandedBits( | |||
1101 | Op0, DemandedBits, DemandedElts, TLO.DAG, Depth + 1); | |||
1102 | SDValue DemandedOp1 = SimplifyMultipleUseDemandedBits( | |||
1103 | Op1, DemandedBits, DemandedElts, TLO.DAG, Depth + 1); | |||
1104 | if (DemandedOp0 || DemandedOp1) { | |||
1105 | Op0 = DemandedOp0 ? DemandedOp0 : Op0; | |||
1106 | Op1 = DemandedOp1 ? DemandedOp1 : Op1; | |||
1107 | SDValue NewOp = TLO.DAG.getNode(Op.getOpcode(), dl, VT, Op0, Op1); | |||
1108 | return TLO.CombineTo(Op, NewOp); | |||
1109 | } | |||
1110 | } | |||
1111 | ||||
1112 | // If all of the demanded bits are known zero on one side, return the other. | |||
1113 | // These bits cannot contribute to the result of the 'or'. | |||
1114 | if (DemandedBits.isSubsetOf(Known2.One | Known.Zero)) | |||
1115 | return TLO.CombineTo(Op, Op0); | |||
1116 | if (DemandedBits.isSubsetOf(Known.One | Known2.Zero)) | |||
1117 | return TLO.CombineTo(Op, Op1); | |||
1118 | // If the RHS is a constant, see if we can simplify it. | |||
1119 | if (ShrinkDemandedConstant(Op, DemandedBits, TLO)) | |||
1120 | return true; | |||
1121 | // If the operation can be done in a smaller type, do so. | |||
1122 | if (ShrinkDemandedOp(Op, BitWidth, DemandedBits, TLO)) | |||
1123 | return true; | |||
1124 | ||||
1125 | // Output known-0 bits are only known if clear in both the LHS & RHS. | |||
1126 | Known.Zero &= Known2.Zero; | |||
1127 | // Output known-1 are known to be set if set in either the LHS | RHS. | |||
1128 | Known.One |= Known2.One; | |||
1129 | break; | |||
1130 | } | |||
1131 | case ISD::XOR: { | |||
1132 | SDValue Op0 = Op.getOperand(0); | |||
1133 | SDValue Op1 = Op.getOperand(1); | |||
1134 | ||||
1135 | if (SimplifyDemandedBits(Op1, DemandedBits, DemandedElts, Known, TLO, | |||
1136 | Depth + 1)) | |||
1137 | return true; | |||
1138 | assert(!Known.hasConflict() && "Bits known to be one AND zero?")((!Known.hasConflict() && "Bits known to be one AND zero?" ) ? static_cast<void> (0) : __assert_fail ("!Known.hasConflict() && \"Bits known to be one AND zero?\"" , "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 1138, __PRETTY_FUNCTION__)); | |||
1139 | if (SimplifyDemandedBits(Op0, DemandedBits, DemandedElts, Known2, TLO, | |||
1140 | Depth + 1)) | |||
1141 | return true; | |||
1142 | assert(!Known2.hasConflict() && "Bits known to be one AND zero?")((!Known2.hasConflict() && "Bits known to be one AND zero?" ) ? static_cast<void> (0) : __assert_fail ("!Known2.hasConflict() && \"Bits known to be one AND zero?\"" , "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 1142, __PRETTY_FUNCTION__)); | |||
1143 | ||||
1144 | // Attempt to avoid multi-use ops if we don't need anything from them. | |||
1145 | if (!DemandedBits.isAllOnesValue() || !DemandedElts.isAllOnesValue()) { | |||
1146 | SDValue DemandedOp0 = SimplifyMultipleUseDemandedBits( | |||
1147 | Op0, DemandedBits, DemandedElts, TLO.DAG, Depth + 1); | |||
1148 | SDValue DemandedOp1 = SimplifyMultipleUseDemandedBits( | |||
1149 | Op1, DemandedBits, DemandedElts, TLO.DAG, Depth + 1); | |||
1150 | if (DemandedOp0 || DemandedOp1) { | |||
1151 | Op0 = DemandedOp0 ? DemandedOp0 : Op0; | |||
1152 | Op1 = DemandedOp1 ? DemandedOp1 : Op1; | |||
1153 | SDValue NewOp = TLO.DAG.getNode(Op.getOpcode(), dl, VT, Op0, Op1); | |||
1154 | return TLO.CombineTo(Op, NewOp); | |||
1155 | } | |||
1156 | } | |||
1157 | ||||
1158 | // If all of the demanded bits are known zero on one side, return the other. | |||
1159 | // These bits cannot contribute to the result of the 'xor'. | |||
1160 | if (DemandedBits.isSubsetOf(Known.Zero)) | |||
1161 | return TLO.CombineTo(Op, Op0); | |||
1162 | if (DemandedBits.isSubsetOf(Known2.Zero)) | |||
1163 | return TLO.CombineTo(Op, Op1); | |||
1164 | // If the operation can be done in a smaller type, do so. | |||
1165 | if (ShrinkDemandedOp(Op, BitWidth, DemandedBits, TLO)) | |||
1166 | return true; | |||
1167 | ||||
1168 | // If all of the unknown bits are known to be zero on one side or the other | |||
1169 | // (but not both) turn this into an *inclusive* or. | |||
1170 | // e.g. (A & C1)^(B & C2) -> (A & C1)|(B & C2) iff C1&C2 == 0 | |||
1171 | if (DemandedBits.isSubsetOf(Known.Zero | Known2.Zero)) | |||
1172 | return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::OR, dl, VT, Op0, Op1)); | |||
1173 | ||||
1174 | // Output known-0 bits are known if clear or set in both the LHS & RHS. | |||
1175 | KnownOut.Zero = (Known.Zero & Known2.Zero) | (Known.One & Known2.One); | |||
1176 | // Output known-1 are known to be set if set in only one of the LHS, RHS. | |||
1177 | KnownOut.One = (Known.Zero & Known2.One) | (Known.One & Known2.Zero); | |||
1178 | ||||
1179 | if (ConstantSDNode *C = isConstOrConstSplat(Op1)) { | |||
1180 | // If one side is a constant, and all of the known set bits on the other | |||
1181 | // side are also set in the constant, turn this into an AND, as we know | |||
1182 | // the bits will be cleared. | |||
1183 | // e.g. (X | C1) ^ C2 --> (X | C1) & ~C2 iff (C1&C2) == C2 | |||
1184 | // NB: it is okay if more bits are known than are requested | |||
1185 | if (C->getAPIntValue() == Known2.One) { | |||
1186 | SDValue ANDC = | |||
1187 | TLO.DAG.getConstant(~C->getAPIntValue() & DemandedBits, dl, VT); | |||
1188 | return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::AND, dl, VT, Op0, ANDC)); | |||
1189 | } | |||
1190 | ||||
1191 | // If the RHS is a constant, see if we can change it. Don't alter a -1 | |||
1192 | // constant because that's a 'not' op, and that is better for combining | |||
1193 | // and codegen. | |||
1194 | if (!C->isAllOnesValue()) { | |||
1195 | if (DemandedBits.isSubsetOf(C->getAPIntValue())) { | |||
1196 | // We're flipping all demanded bits. Flip the undemanded bits too. | |||
1197 | SDValue New = TLO.DAG.getNOT(dl, Op0, VT); | |||
1198 | return TLO.CombineTo(Op, New); | |||
1199 | } | |||
1200 | // If we can't turn this into a 'not', try to shrink the constant. | |||
1201 | if (ShrinkDemandedConstant(Op, DemandedBits, TLO)) | |||
1202 | return true; | |||
1203 | } | |||
1204 | } | |||
1205 | ||||
1206 | Known = std::move(KnownOut); | |||
1207 | break; | |||
1208 | } | |||
1209 | case ISD::SELECT: | |||
1210 | if (SimplifyDemandedBits(Op.getOperand(2), DemandedBits, Known, TLO, | |||
1211 | Depth + 1)) | |||
1212 | return true; | |||
1213 | if (SimplifyDemandedBits(Op.getOperand(1), DemandedBits, Known2, TLO, | |||
1214 | Depth + 1)) | |||
1215 | return true; | |||
1216 | assert(!Known.hasConflict() && "Bits known to be one AND zero?")((!Known.hasConflict() && "Bits known to be one AND zero?" ) ? static_cast<void> (0) : __assert_fail ("!Known.hasConflict() && \"Bits known to be one AND zero?\"" , "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 1216, __PRETTY_FUNCTION__)); | |||
1217 | assert(!Known2.hasConflict() && "Bits known to be one AND zero?")((!Known2.hasConflict() && "Bits known to be one AND zero?" ) ? static_cast<void> (0) : __assert_fail ("!Known2.hasConflict() && \"Bits known to be one AND zero?\"" , "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 1217, __PRETTY_FUNCTION__)); | |||
1218 | ||||
1219 | // If the operands are constants, see if we can simplify them. | |||
1220 | if (ShrinkDemandedConstant(Op, DemandedBits, TLO)) | |||
1221 | return true; | |||
1222 | ||||
1223 | // Only known if known in both the LHS and RHS. | |||
1224 | Known.One &= Known2.One; | |||
1225 | Known.Zero &= Known2.Zero; | |||
1226 | break; | |||
1227 | case ISD::SELECT_CC: | |||
1228 | if (SimplifyDemandedBits(Op.getOperand(3), DemandedBits, Known, TLO, | |||
1229 | Depth + 1)) | |||
1230 | return true; | |||
1231 | if (SimplifyDemandedBits(Op.getOperand(2), DemandedBits, Known2, TLO, | |||
1232 | Depth + 1)) | |||
1233 | return true; | |||
1234 | assert(!Known.hasConflict() && "Bits known to be one AND zero?")((!Known.hasConflict() && "Bits known to be one AND zero?" ) ? static_cast<void> (0) : __assert_fail ("!Known.hasConflict() && \"Bits known to be one AND zero?\"" , "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 1234, __PRETTY_FUNCTION__)); | |||
1235 | assert(!Known2.hasConflict() && "Bits known to be one AND zero?")((!Known2.hasConflict() && "Bits known to be one AND zero?" ) ? static_cast<void> (0) : __assert_fail ("!Known2.hasConflict() && \"Bits known to be one AND zero?\"" , "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 1235, __PRETTY_FUNCTION__)); | |||
1236 | ||||
1237 | // If the operands are constants, see if we can simplify them. | |||
1238 | if (ShrinkDemandedConstant(Op, DemandedBits, TLO)) | |||
1239 | return true; | |||
1240 | ||||
1241 | // Only known if known in both the LHS and RHS. | |||
1242 | Known.One &= Known2.One; | |||
1243 | Known.Zero &= Known2.Zero; | |||
1244 | break; | |||
1245 | case ISD::SETCC: { | |||
1246 | SDValue Op0 = Op.getOperand(0); | |||
1247 | SDValue Op1 = Op.getOperand(1); | |||
1248 | ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); | |||
1249 | // If (1) we only need the sign-bit, (2) the setcc operands are the same | |||
1250 | // width as the setcc result, and (3) the result of a setcc conforms to 0 or | |||
1251 | // -1, we may be able to bypass the setcc. | |||
1252 | if (DemandedBits.isSignMask() && | |||
1253 | Op0.getScalarValueSizeInBits() == BitWidth && | |||
1254 | getBooleanContents(VT) == | |||
1255 | BooleanContent::ZeroOrNegativeOneBooleanContent) { | |||
1256 | // If we're testing X < 0, then this compare isn't needed - just use X! | |||
1257 | // FIXME: We're limiting to integer types here, but this should also work | |||
1258 | // if we don't care about FP signed-zero. The use of SETLT with FP means | |||
1259 | // that we don't care about NaNs. | |||
1260 | if (CC == ISD::SETLT && Op1.getValueType().isInteger() && | |||
1261 | (isNullConstant(Op1) || ISD::isBuildVectorAllZeros(Op1.getNode()))) | |||
1262 | return TLO.CombineTo(Op, Op0); | |||
1263 | ||||
1264 | // TODO: Should we check for other forms of sign-bit comparisons? | |||
1265 | // Examples: X <= -1, X >= 0 | |||
1266 | } | |||
1267 | if (getBooleanContents(Op0.getValueType()) == | |||
1268 | TargetLowering::ZeroOrOneBooleanContent && | |||
1269 | BitWidth > 1) | |||
1270 | Known.Zero.setBitsFrom(1); | |||
1271 | break; | |||
1272 | } | |||
1273 | case ISD::SHL: { | |||
1274 | SDValue Op0 = Op.getOperand(0); | |||
1275 | SDValue Op1 = Op.getOperand(1); | |||
1276 | ||||
1277 | if (ConstantSDNode *SA = isConstOrConstSplat(Op1, DemandedElts)) { | |||
1278 | // If the shift count is an invalid immediate, don't do anything. | |||
1279 | if (SA->getAPIntValue().uge(BitWidth)) | |||
1280 | break; | |||
1281 | ||||
1282 | unsigned ShAmt = SA->getZExtValue(); | |||
1283 | if (ShAmt == 0) | |||
1284 | return TLO.CombineTo(Op, Op0); | |||
1285 | ||||
1286 | // If this is ((X >>u C1) << ShAmt), see if we can simplify this into a | |||
1287 | // single shift. We can do this if the bottom bits (which are shifted | |||
1288 | // out) are never demanded. | |||
1289 | // TODO - support non-uniform vector amounts. | |||
1290 | if (Op0.getOpcode() == ISD::SRL) { | |||
1291 | if (!DemandedBits.intersects(APInt::getLowBitsSet(BitWidth, ShAmt))) { | |||
1292 | if (ConstantSDNode *SA2 = | |||
1293 | isConstOrConstSplat(Op0.getOperand(1), DemandedElts)) { | |||
1294 | if (SA2->getAPIntValue().ult(BitWidth)) { | |||
1295 | unsigned C1 = SA2->getZExtValue(); | |||
1296 | unsigned Opc = ISD::SHL; | |||
1297 | int Diff = ShAmt - C1; | |||
1298 | if (Diff < 0) { | |||
1299 | Diff = -Diff; | |||
1300 | Opc = ISD::SRL; | |||
1301 | } | |||
1302 | ||||
1303 | SDValue NewSA = TLO.DAG.getConstant(Diff, dl, Op1.getValueType()); | |||
1304 | return TLO.CombineTo( | |||
1305 | Op, TLO.DAG.getNode(Opc, dl, VT, Op0.getOperand(0), NewSA)); | |||
1306 | } | |||
1307 | } | |||
1308 | } | |||
1309 | } | |||
1310 | ||||
1311 | if (SimplifyDemandedBits(Op0, DemandedBits.lshr(ShAmt), DemandedElts, | |||
1312 | Known, TLO, Depth + 1)) | |||
1313 | return true; | |||
1314 | ||||
1315 | // Try shrinking the operation as long as the shift amount will still be | |||
1316 | // in range. | |||
1317 | if ((ShAmt < DemandedBits.getActiveBits()) && | |||
1318 | ShrinkDemandedOp(Op, BitWidth, DemandedBits, TLO)) | |||
1319 | return true; | |||
1320 | ||||
1321 | // Convert (shl (anyext x, c)) to (anyext (shl x, c)) if the high bits | |||
1322 | // are not demanded. This will likely allow the anyext to be folded away. | |||
1323 | if (Op0.getOpcode() == ISD::ANY_EXTEND) { | |||
1324 | SDValue InnerOp = Op0.getOperand(0); | |||
1325 | EVT InnerVT = InnerOp.getValueType(); | |||
1326 | unsigned InnerBits = InnerVT.getScalarSizeInBits(); | |||
1327 | if (ShAmt < InnerBits && DemandedBits.getActiveBits() <= InnerBits && | |||
1328 | isTypeDesirableForOp(ISD::SHL, InnerVT)) { | |||
1329 | EVT ShTy = getShiftAmountTy(InnerVT, DL); | |||
1330 | if (!APInt(BitWidth, ShAmt).isIntN(ShTy.getSizeInBits())) | |||
1331 | ShTy = InnerVT; | |||
1332 | SDValue NarrowShl = | |||
1333 | TLO.DAG.getNode(ISD::SHL, dl, InnerVT, InnerOp, | |||
1334 | TLO.DAG.getConstant(ShAmt, dl, ShTy)); | |||
1335 | return TLO.CombineTo( | |||
1336 | Op, TLO.DAG.getNode(ISD::ANY_EXTEND, dl, VT, NarrowShl)); | |||
1337 | } | |||
1338 | // Repeat the SHL optimization above in cases where an extension | |||
1339 | // intervenes: (shl (anyext (shr x, c1)), c2) to | |||
1340 | // (shl (anyext x), c2-c1). This requires that the bottom c1 bits | |||
1341 | // aren't demanded (as above) and that the shifted upper c1 bits of | |||
1342 | // x aren't demanded. | |||
1343 | if (Op0.hasOneUse() && InnerOp.getOpcode() == ISD::SRL && | |||
1344 | InnerOp.hasOneUse()) { | |||
1345 | if (ConstantSDNode *SA2 = | |||
1346 | isConstOrConstSplat(InnerOp.getOperand(1))) { | |||
1347 | unsigned InnerShAmt = SA2->getLimitedValue(InnerBits); | |||
1348 | if (InnerShAmt < ShAmt && InnerShAmt < InnerBits && | |||
1349 | DemandedBits.getActiveBits() <= | |||
1350 | (InnerBits - InnerShAmt + ShAmt) && | |||
1351 | DemandedBits.countTrailingZeros() >= ShAmt) { | |||
1352 | SDValue NewSA = TLO.DAG.getConstant(ShAmt - InnerShAmt, dl, | |||
1353 | Op1.getValueType()); | |||
1354 | SDValue NewExt = TLO.DAG.getNode(ISD::ANY_EXTEND, dl, VT, | |||
1355 | InnerOp.getOperand(0)); | |||
1356 | return TLO.CombineTo( | |||
1357 | Op, TLO.DAG.getNode(ISD::SHL, dl, VT, NewExt, NewSA)); | |||
1358 | } | |||
1359 | } | |||
1360 | } | |||
1361 | } | |||
1362 | ||||
1363 | Known.Zero <<= ShAmt; | |||
1364 | Known.One <<= ShAmt; | |||
1365 | // low bits known zero. | |||
1366 | Known.Zero.setLowBits(ShAmt); | |||
1367 | } | |||
1368 | break; | |||
1369 | } | |||
1370 | case ISD::SRL: { | |||
1371 | SDValue Op0 = Op.getOperand(0); | |||
1372 | SDValue Op1 = Op.getOperand(1); | |||
1373 | ||||
1374 | if (ConstantSDNode *SA = isConstOrConstSplat(Op1, DemandedElts)) { | |||
1375 | // If the shift count is an invalid immediate, don't do anything. | |||
1376 | if (SA->getAPIntValue().uge(BitWidth)) | |||
1377 | break; | |||
1378 | ||||
1379 | unsigned ShAmt = SA->getZExtValue(); | |||
1380 | if (ShAmt == 0) | |||
1381 | return TLO.CombineTo(Op, Op0); | |||
1382 | ||||
1383 | EVT ShiftVT = Op1.getValueType(); | |||
1384 | APInt InDemandedMask = (DemandedBits << ShAmt); | |||
1385 | ||||
1386 | // If the shift is exact, then it does demand the low bits (and knows that | |||
1387 | // they are zero). | |||
1388 | if (Op->getFlags().hasExact()) | |||
1389 | InDemandedMask.setLowBits(ShAmt); | |||
1390 | ||||
1391 | // If this is ((X << C1) >>u ShAmt), see if we can simplify this into a | |||
1392 | // single shift. We can do this if the top bits (which are shifted out) | |||
1393 | // are never demanded. | |||
1394 | // TODO - support non-uniform vector amounts. | |||
1395 | if (Op0.getOpcode() == ISD::SHL) { | |||
1396 | if (ConstantSDNode *SA2 = | |||
1397 | isConstOrConstSplat(Op0.getOperand(1), DemandedElts)) { | |||
1398 | if (!DemandedBits.intersects( | |||
1399 | APInt::getHighBitsSet(BitWidth, ShAmt))) { | |||
1400 | if (SA2->getAPIntValue().ult(BitWidth)) { | |||
1401 | unsigned C1 = SA2->getZExtValue(); | |||
1402 | unsigned Opc = ISD::SRL; | |||
1403 | int Diff = ShAmt - C1; | |||
1404 | if (Diff < 0) { | |||
1405 | Diff = -Diff; | |||
1406 | Opc = ISD::SHL; | |||
1407 | } | |||
1408 | ||||
1409 | SDValue NewSA = TLO.DAG.getConstant(Diff, dl, ShiftVT); | |||
1410 | return TLO.CombineTo( | |||
1411 | Op, TLO.DAG.getNode(Opc, dl, VT, Op0.getOperand(0), NewSA)); | |||
1412 | } | |||
1413 | } | |||
1414 | } | |||
1415 | } | |||
1416 | ||||
1417 | // Compute the new bits that are at the top now. | |||
1418 | if (SimplifyDemandedBits(Op0, InDemandedMask, DemandedElts, Known, TLO, | |||
1419 | Depth + 1)) | |||
1420 | return true; | |||
1421 | assert(!Known.hasConflict() && "Bits known to be one AND zero?")((!Known.hasConflict() && "Bits known to be one AND zero?" ) ? static_cast<void> (0) : __assert_fail ("!Known.hasConflict() && \"Bits known to be one AND zero?\"" , "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 1421, __PRETTY_FUNCTION__)); | |||
1422 | Known.Zero.lshrInPlace(ShAmt); | |||
1423 | Known.One.lshrInPlace(ShAmt); | |||
1424 | ||||
1425 | Known.Zero.setHighBits(ShAmt); // High bits known zero. | |||
1426 | } | |||
1427 | break; | |||
1428 | } | |||
1429 | case ISD::SRA: { | |||
1430 | SDValue Op0 = Op.getOperand(0); | |||
1431 | SDValue Op1 = Op.getOperand(1); | |||
1432 | ||||
1433 | // If this is an arithmetic shift right and only the low-bit is set, we can | |||
1434 | // always convert this into a logical shr, even if the shift amount is | |||
1435 | // variable. The low bit of the shift cannot be an input sign bit unless | |||
1436 | // the shift amount is >= the size of the datatype, which is undefined. | |||
1437 | if (DemandedBits.isOneValue()) | |||
1438 | return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT, Op0, Op1)); | |||
1439 | ||||
1440 | if (ConstantSDNode *SA = isConstOrConstSplat(Op1, DemandedElts)) { | |||
1441 | // If the shift count is an invalid immediate, don't do anything. | |||
1442 | if (SA->getAPIntValue().uge(BitWidth)) | |||
1443 | break; | |||
1444 | ||||
1445 | unsigned ShAmt = SA->getZExtValue(); | |||
1446 | if (ShAmt == 0) | |||
1447 | return TLO.CombineTo(Op, Op0); | |||
1448 | ||||
1449 | APInt InDemandedMask = (DemandedBits << ShAmt); | |||
1450 | ||||
1451 | // If the shift is exact, then it does demand the low bits (and knows that | |||
1452 | // they are zero). | |||
1453 | if (Op->getFlags().hasExact()) | |||
1454 | InDemandedMask.setLowBits(ShAmt); | |||
1455 | ||||
1456 | // If any of the demanded bits are produced by the sign extension, we also | |||
1457 | // demand the input sign bit. | |||
1458 | if (DemandedBits.countLeadingZeros() < ShAmt) | |||
1459 | InDemandedMask.setSignBit(); | |||
1460 | ||||
1461 | if (SimplifyDemandedBits(Op0, InDemandedMask, DemandedElts, Known, TLO, | |||
1462 | Depth + 1)) | |||
1463 | return true; | |||
1464 | assert(!Known.hasConflict() && "Bits known to be one AND zero?")((!Known.hasConflict() && "Bits known to be one AND zero?" ) ? static_cast<void> (0) : __assert_fail ("!Known.hasConflict() && \"Bits known to be one AND zero?\"" , "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 1464, __PRETTY_FUNCTION__)); | |||
1465 | Known.Zero.lshrInPlace(ShAmt); | |||
1466 | Known.One.lshrInPlace(ShAmt); | |||
1467 | ||||
1468 | // If the input sign bit is known to be zero, or if none of the top bits | |||
1469 | // are demanded, turn this into an unsigned shift right. | |||
1470 | if (Known.Zero[BitWidth - ShAmt - 1] || | |||
1471 | DemandedBits.countLeadingZeros() >= ShAmt) { | |||
1472 | SDNodeFlags Flags; | |||
1473 | Flags.setExact(Op->getFlags().hasExact()); | |||
1474 | return TLO.CombineTo( | |||
1475 | Op, TLO.DAG.getNode(ISD::SRL, dl, VT, Op0, Op1, Flags)); | |||
1476 | } | |||
1477 | ||||
1478 | int Log2 = DemandedBits.exactLogBase2(); | |||
1479 | if (Log2 >= 0) { | |||
1480 | // The bit must come from the sign. | |||
1481 | SDValue NewSA = | |||
1482 | TLO.DAG.getConstant(BitWidth - 1 - Log2, dl, Op1.getValueType()); | |||
1483 | return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT, Op0, NewSA)); | |||
1484 | } | |||
1485 | ||||
1486 | if (Known.One[BitWidth - ShAmt - 1]) | |||
1487 | // New bits are known one. | |||
1488 | Known.One.setHighBits(ShAmt); | |||
1489 | } | |||
1490 | break; | |||
1491 | } | |||
1492 | case ISD::FSHL: | |||
1493 | case ISD::FSHR: { | |||
1494 | SDValue Op0 = Op.getOperand(0); | |||
1495 | SDValue Op1 = Op.getOperand(1); | |||
1496 | SDValue Op2 = Op.getOperand(2); | |||
1497 | bool IsFSHL = (Op.getOpcode() == ISD::FSHL); | |||
1498 | ||||
1499 | if (ConstantSDNode *SA = isConstOrConstSplat(Op2, DemandedElts)) { | |||
1500 | unsigned Amt = SA->getAPIntValue().urem(BitWidth); | |||
1501 | ||||
1502 | // For fshl, 0-shift returns the 1st arg. | |||
1503 | // For fshr, 0-shift returns the 2nd arg. | |||
1504 | if (Amt == 0) { | |||
1505 | if (SimplifyDemandedBits(IsFSHL ? Op0 : Op1, DemandedBits, DemandedElts, | |||
1506 | Known, TLO, Depth + 1)) | |||
1507 | return true; | |||
1508 | break; | |||
1509 | } | |||
1510 | ||||
1511 | // fshl: (Op0 << Amt) | (Op1 >> (BW - Amt)) | |||
1512 | // fshr: (Op0 << (BW - Amt)) | (Op1 >> Amt) | |||
1513 | APInt Demanded0 = DemandedBits.lshr(IsFSHL ? Amt : (BitWidth - Amt)); | |||
1514 | APInt Demanded1 = DemandedBits << (IsFSHL ? (BitWidth - Amt) : Amt); | |||
1515 | if (SimplifyDemandedBits(Op0, Demanded0, DemandedElts, Known2, TLO, | |||
1516 | Depth + 1)) | |||
1517 | return true; | |||
1518 | if (SimplifyDemandedBits(Op1, Demanded1, DemandedElts, Known, TLO, | |||
1519 | Depth + 1)) | |||
1520 | return true; | |||
1521 | ||||
1522 | Known2.One <<= (IsFSHL ? Amt : (BitWidth - Amt)); | |||
1523 | Known2.Zero <<= (IsFSHL ? Amt : (BitWidth - Amt)); | |||
1524 | Known.One.lshrInPlace(IsFSHL ? (BitWidth - Amt) : Amt); | |||
1525 | Known.Zero.lshrInPlace(IsFSHL ? (BitWidth - Amt) : Amt); | |||
1526 | Known.One |= Known2.One; | |||
1527 | Known.Zero |= Known2.Zero; | |||
1528 | } | |||
1529 | break; | |||
1530 | } | |||
1531 | case ISD::BITREVERSE: { | |||
1532 | SDValue Src = Op.getOperand(0); | |||
1533 | APInt DemandedSrcBits = DemandedBits.reverseBits(); | |||
1534 | if (SimplifyDemandedBits(Src, DemandedSrcBits, DemandedElts, Known2, TLO, | |||
1535 | Depth + 1)) | |||
1536 | return true; | |||
1537 | Known.One = Known2.One.reverseBits(); | |||
1538 | Known.Zero = Known2.Zero.reverseBits(); | |||
1539 | break; | |||
1540 | } | |||
1541 | case ISD::SIGN_EXTEND_INREG: { | |||
1542 | SDValue Op0 = Op.getOperand(0); | |||
1543 | EVT ExVT = cast<VTSDNode>(Op.getOperand(1))->getVT(); | |||
1544 | unsigned ExVTBits = ExVT.getScalarSizeInBits(); | |||
1545 | ||||
1546 | // If we only care about the highest bit, don't bother shifting right. | |||
1547 | if (DemandedBits.isSignMask()) { | |||
1548 | unsigned NumSignBits = TLO.DAG.ComputeNumSignBits(Op0); | |||
1549 | bool AlreadySignExtended = NumSignBits >= BitWidth - ExVTBits + 1; | |||
1550 | // However if the input is already sign extended we expect the sign | |||
1551 | // extension to be dropped altogether later and do not simplify. | |||
1552 | if (!AlreadySignExtended) { | |||
1553 | // Compute the correct shift amount type, which must be getShiftAmountTy | |||
1554 | // for scalar types after legalization. | |||
1555 | EVT ShiftAmtTy = VT; | |||
1556 | if (TLO.LegalTypes() && !ShiftAmtTy.isVector()) | |||
1557 | ShiftAmtTy = getShiftAmountTy(ShiftAmtTy, DL); | |||
1558 | ||||
1559 | SDValue ShiftAmt = | |||
1560 | TLO.DAG.getConstant(BitWidth - ExVTBits, dl, ShiftAmtTy); | |||
1561 | return TLO.CombineTo(Op, | |||
1562 | TLO.DAG.getNode(ISD::SHL, dl, VT, Op0, ShiftAmt)); | |||
1563 | } | |||
1564 | } | |||
1565 | ||||
1566 | // If none of the extended bits are demanded, eliminate the sextinreg. | |||
1567 | if (DemandedBits.getActiveBits() <= ExVTBits) | |||
1568 | return TLO.CombineTo(Op, Op0); | |||
1569 | ||||
1570 | APInt InputDemandedBits = DemandedBits.getLoBits(ExVTBits); | |||
1571 | ||||
1572 | // Since the sign extended bits are demanded, we know that the sign | |||
1573 | // bit is demanded. | |||
1574 | InputDemandedBits.setBit(ExVTBits - 1); | |||
1575 | ||||
1576 | if (SimplifyDemandedBits(Op0, InputDemandedBits, Known, TLO, Depth + 1)) | |||
1577 | return true; | |||
1578 | assert(!Known.hasConflict() && "Bits known to be one AND zero?")((!Known.hasConflict() && "Bits known to be one AND zero?" ) ? static_cast<void> (0) : __assert_fail ("!Known.hasConflict() && \"Bits known to be one AND zero?\"" , "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 1578, __PRETTY_FUNCTION__)); | |||
1579 | ||||
1580 | // If the sign bit of the input is known set or clear, then we know the | |||
1581 | // top bits of the result. | |||
1582 | ||||
1583 | // If the input sign bit is known zero, convert this into a zero extension. | |||
1584 | if (Known.Zero[ExVTBits - 1]) | |||
1585 | return TLO.CombineTo( | |||
1586 | Op, TLO.DAG.getZeroExtendInReg(Op0, dl, ExVT.getScalarType())); | |||
1587 | ||||
1588 | APInt Mask = APInt::getLowBitsSet(BitWidth, ExVTBits); | |||
1589 | if (Known.One[ExVTBits - 1]) { // Input sign bit known set | |||
1590 | Known.One.setBitsFrom(ExVTBits); | |||
1591 | Known.Zero &= Mask; | |||
1592 | } else { // Input sign bit unknown | |||
1593 | Known.Zero &= Mask; | |||
1594 | Known.One &= Mask; | |||
1595 | } | |||
1596 | break; | |||
1597 | } | |||
1598 | case ISD::BUILD_PAIR: { | |||
1599 | EVT HalfVT = Op.getOperand(0).getValueType(); | |||
1600 | unsigned HalfBitWidth = HalfVT.getScalarSizeInBits(); | |||
1601 | ||||
1602 | APInt MaskLo = DemandedBits.getLoBits(HalfBitWidth).trunc(HalfBitWidth); | |||
1603 | APInt MaskHi = DemandedBits.getHiBits(HalfBitWidth).trunc(HalfBitWidth); | |||
1604 | ||||
1605 | KnownBits KnownLo, KnownHi; | |||
1606 | ||||
1607 | if (SimplifyDemandedBits(Op.getOperand(0), MaskLo, KnownLo, TLO, Depth + 1)) | |||
1608 | return true; | |||
1609 | ||||
1610 | if (SimplifyDemandedBits(Op.getOperand(1), MaskHi, KnownHi, TLO, Depth + 1)) | |||
1611 | return true; | |||
1612 | ||||
1613 | Known.Zero = KnownLo.Zero.zext(BitWidth) | | |||
1614 | KnownHi.Zero.zext(BitWidth).shl(HalfBitWidth); | |||
1615 | ||||
1616 | Known.One = KnownLo.One.zext(BitWidth) | | |||
1617 | KnownHi.One.zext(BitWidth).shl(HalfBitWidth); | |||
1618 | break; | |||
1619 | } | |||
1620 | case ISD::ZERO_EXTEND: | |||
1621 | case ISD::ZERO_EXTEND_VECTOR_INREG: { | |||
1622 | SDValue Src = Op.getOperand(0); | |||
1623 | EVT SrcVT = Src.getValueType(); | |||
1624 | unsigned InBits = SrcVT.getScalarSizeInBits(); | |||
1625 | unsigned InElts = SrcVT.isVector() ? SrcVT.getVectorNumElements() : 1; | |||
1626 | bool IsVecInReg = Op.getOpcode() == ISD::ZERO_EXTEND_VECTOR_INREG; | |||
1627 | ||||
1628 | // If none of the top bits are demanded, convert this into an any_extend. | |||
1629 | if (DemandedBits.getActiveBits() <= InBits) { | |||
1630 | // If we only need the non-extended bits of the bottom element | |||
1631 | // then we can just bitcast to the result. | |||
1632 | if (IsVecInReg && DemandedElts == 1 && | |||
1633 | VT.getSizeInBits() == SrcVT.getSizeInBits() && | |||
1634 | TLO.DAG.getDataLayout().isLittleEndian()) | |||
1635 | return TLO.CombineTo(Op, TLO.DAG.getBitcast(VT, Src)); | |||
1636 | ||||
1637 | unsigned Opc = | |||
1638 | IsVecInReg ? ISD::ANY_EXTEND_VECTOR_INREG : ISD::ANY_EXTEND; | |||
1639 | if (!TLO.LegalOperations() || isOperationLegal(Opc, VT)) | |||
1640 | return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT, Src)); | |||
1641 | } | |||
1642 | ||||
1643 | APInt InDemandedBits = DemandedBits.trunc(InBits); | |||
1644 | APInt InDemandedElts = DemandedElts.zextOrSelf(InElts); | |||
1645 | if (SimplifyDemandedBits(Src, InDemandedBits, InDemandedElts, Known, TLO, | |||
1646 | Depth + 1)) | |||
1647 | return true; | |||
1648 | assert(!Known.hasConflict() && "Bits known to be one AND zero?")((!Known.hasConflict() && "Bits known to be one AND zero?" ) ? static_cast<void> (0) : __assert_fail ("!Known.hasConflict() && \"Bits known to be one AND zero?\"" , "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 1648, __PRETTY_FUNCTION__)); | |||
1649 | assert(Known.getBitWidth() == InBits && "Src width has changed?")((Known.getBitWidth() == InBits && "Src width has changed?" ) ? static_cast<void> (0) : __assert_fail ("Known.getBitWidth() == InBits && \"Src width has changed?\"" , "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 1649, __PRETTY_FUNCTION__)); | |||
1650 | Known = Known.zext(BitWidth, true /* ExtendedBitsAreKnownZero */); | |||
1651 | break; | |||
1652 | } | |||
1653 | case ISD::SIGN_EXTEND: | |||
1654 | case ISD::SIGN_EXTEND_VECTOR_INREG: { | |||
1655 | SDValue Src = Op.getOperand(0); | |||
1656 | EVT SrcVT = Src.getValueType(); | |||
1657 | unsigned InBits = SrcVT.getScalarSizeInBits(); | |||
1658 | unsigned InElts = SrcVT.isVector() ? SrcVT.getVectorNumElements() : 1; | |||
1659 | bool IsVecInReg = Op.getOpcode() == ISD::SIGN_EXTEND_VECTOR_INREG; | |||
1660 | ||||
1661 | // If none of the top bits are demanded, convert this into an any_extend. | |||
1662 | if (DemandedBits.getActiveBits() <= InBits) { | |||
1663 | // If we only need the non-extended bits of the bottom element | |||
1664 | // then we can just bitcast to the result. | |||
1665 | if (IsVecInReg && DemandedElts == 1 && | |||
1666 | VT.getSizeInBits() == SrcVT.getSizeInBits() && | |||
1667 | TLO.DAG.getDataLayout().isLittleEndian()) | |||
1668 | return TLO.CombineTo(Op, TLO.DAG.getBitcast(VT, Src)); | |||
1669 | ||||
1670 | unsigned Opc = | |||
1671 | IsVecInReg ? ISD::ANY_EXTEND_VECTOR_INREG : ISD::ANY_EXTEND; | |||
1672 | if (!TLO.LegalOperations() || isOperationLegal(Opc, VT)) | |||
1673 | return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT, Src)); | |||
1674 | } | |||
1675 | ||||
1676 | APInt InDemandedBits = DemandedBits.trunc(InBits); | |||
1677 | APInt InDemandedElts = DemandedElts.zextOrSelf(InElts); | |||
1678 | ||||
1679 | // Since some of the sign extended bits are demanded, we know that the sign | |||
1680 | // bit is demanded. | |||
1681 | InDemandedBits.setBit(InBits - 1); | |||
1682 | ||||
1683 | if (SimplifyDemandedBits(Src, InDemandedBits, InDemandedElts, Known, TLO, | |||
1684 | Depth + 1)) | |||
1685 | return true; | |||
1686 | assert(!Known.hasConflict() && "Bits known to be one AND zero?")((!Known.hasConflict() && "Bits known to be one AND zero?" ) ? static_cast<void> (0) : __assert_fail ("!Known.hasConflict() && \"Bits known to be one AND zero?\"" , "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 1686, __PRETTY_FUNCTION__)); | |||
1687 | assert(Known.getBitWidth() == InBits && "Src width has changed?")((Known.getBitWidth() == InBits && "Src width has changed?" ) ? static_cast<void> (0) : __assert_fail ("Known.getBitWidth() == InBits && \"Src width has changed?\"" , "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 1687, __PRETTY_FUNCTION__)); | |||
1688 | ||||
1689 | // If the sign bit is known one, the top bits match. | |||
1690 | Known = Known.sext(BitWidth); | |||
1691 | ||||
1692 | // If the sign bit is known zero, convert this to a zero extend. | |||
1693 | if (Known.isNonNegative()) { | |||
1694 | unsigned Opc = | |||
1695 | IsVecInReg ? ISD::ZERO_EXTEND_VECTOR_INREG : ISD::ZERO_EXTEND; | |||
1696 | if (!TLO.LegalOperations() || isOperationLegal(Opc, VT)) | |||
1697 | return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT, Src)); | |||
1698 | } | |||
1699 | break; | |||
1700 | } | |||
1701 | case ISD::ANY_EXTEND: | |||
1702 | case ISD::ANY_EXTEND_VECTOR_INREG: { | |||
1703 | SDValue Src = Op.getOperand(0); | |||
1704 | EVT SrcVT = Src.getValueType(); | |||
1705 | unsigned InBits = SrcVT.getScalarSizeInBits(); | |||
1706 | unsigned InElts = SrcVT.isVector() ? SrcVT.getVectorNumElements() : 1; | |||
1707 | bool IsVecInReg = Op.getOpcode() == ISD::ANY_EXTEND_VECTOR_INREG; | |||
1708 | ||||
1709 | // If we only need the bottom element then we can just bitcast. | |||
1710 | // TODO: Handle ANY_EXTEND? | |||
1711 | if (IsVecInReg && DemandedElts == 1 && | |||
1712 | VT.getSizeInBits() == SrcVT.getSizeInBits() && | |||
1713 | TLO.DAG.getDataLayout().isLittleEndian()) | |||
1714 | return TLO.CombineTo(Op, TLO.DAG.getBitcast(VT, Src)); | |||
1715 | ||||
1716 | APInt InDemandedBits = DemandedBits.trunc(InBits); | |||
1717 | APInt InDemandedElts = DemandedElts.zextOrSelf(InElts); | |||
1718 | if (SimplifyDemandedBits(Src, InDemandedBits, InDemandedElts, Known, TLO, | |||
1719 | Depth + 1)) | |||
1720 | return true; | |||
1721 | assert(!Known.hasConflict() && "Bits known to be one AND zero?")((!Known.hasConflict() && "Bits known to be one AND zero?" ) ? static_cast<void> (0) : __assert_fail ("!Known.hasConflict() && \"Bits known to be one AND zero?\"" , "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 1721, __PRETTY_FUNCTION__)); | |||
1722 | assert(Known.getBitWidth() == InBits && "Src width has changed?")((Known.getBitWidth() == InBits && "Src width has changed?" ) ? static_cast<void> (0) : __assert_fail ("Known.getBitWidth() == InBits && \"Src width has changed?\"" , "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 1722, __PRETTY_FUNCTION__)); | |||
1723 | Known = Known.zext(BitWidth, false /* => any extend */); | |||
1724 | break; | |||
1725 | } | |||
1726 | case ISD::TRUNCATE: { | |||
1727 | SDValue Src = Op.getOperand(0); | |||
1728 | ||||
1729 | // Simplify the input, using demanded bit information, and compute the known | |||
1730 | // zero/one bits live out. | |||
1731 | unsigned OperandBitWidth = Src.getScalarValueSizeInBits(); | |||
1732 | APInt TruncMask = DemandedBits.zext(OperandBitWidth); | |||
1733 | if (SimplifyDemandedBits(Src, TruncMask, Known, TLO, Depth + 1)) | |||
1734 | return true; | |||
1735 | Known = Known.trunc(BitWidth); | |||
1736 | ||||
1737 | // Attempt to avoid multi-use ops if we don't need anything from them. | |||
1738 | if (SDValue NewSrc = SimplifyMultipleUseDemandedBits( | |||
1739 | Src, TruncMask, DemandedElts, TLO.DAG, Depth + 1)) | |||
1740 | return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::TRUNCATE, dl, VT, NewSrc)); | |||
1741 | ||||
1742 | // If the input is only used by this truncate, see if we can shrink it based | |||
1743 | // on the known demanded bits. | |||
1744 | if (Src.getNode()->hasOneUse()) { | |||
1745 | switch (Src.getOpcode()) { | |||
1746 | default: | |||
1747 | break; | |||
1748 | case ISD::SRL: | |||
1749 | // Shrink SRL by a constant if none of the high bits shifted in are | |||
1750 | // demanded. | |||
1751 | if (TLO.LegalTypes() && !isTypeDesirableForOp(ISD::SRL, VT)) | |||
1752 | // Do not turn (vt1 truncate (vt2 srl)) into (vt1 srl) if vt1 is | |||
1753 | // undesirable. | |||
1754 | break; | |||
1755 | ||||
1756 | auto *ShAmt = dyn_cast<ConstantSDNode>(Src.getOperand(1)); | |||
1757 | if (!ShAmt || ShAmt->getAPIntValue().uge(BitWidth)) | |||
1758 | break; | |||
1759 | ||||
1760 | SDValue Shift = Src.getOperand(1); | |||
1761 | uint64_t ShVal = ShAmt->getZExtValue(); | |||
1762 | ||||
1763 | if (TLO.LegalTypes()) | |||
1764 | Shift = TLO.DAG.getConstant(ShVal, dl, getShiftAmountTy(VT, DL)); | |||
1765 | ||||
1766 | APInt HighBits = | |||
1767 | APInt::getHighBitsSet(OperandBitWidth, OperandBitWidth - BitWidth); | |||
1768 | HighBits.lshrInPlace(ShVal); | |||
1769 | HighBits = HighBits.trunc(BitWidth); | |||
1770 | ||||
1771 | if (!(HighBits & DemandedBits)) { | |||
1772 | // None of the shifted in bits are needed. Add a truncate of the | |||
1773 | // shift input, then shift it. | |||
1774 | SDValue NewTrunc = | |||
1775 | TLO.DAG.getNode(ISD::TRUNCATE, dl, VT, Src.getOperand(0)); | |||
1776 | return TLO.CombineTo( | |||
1777 | Op, TLO.DAG.getNode(ISD::SRL, dl, VT, NewTrunc, Shift)); | |||
1778 | } | |||
1779 | break; | |||
1780 | } | |||
1781 | } | |||
1782 | ||||
1783 | assert(!Known.hasConflict() && "Bits known to be one AND zero?")((!Known.hasConflict() && "Bits known to be one AND zero?" ) ? static_cast<void> (0) : __assert_fail ("!Known.hasConflict() && \"Bits known to be one AND zero?\"" , "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 1783, __PRETTY_FUNCTION__)); | |||
1784 | break; | |||
1785 | } | |||
1786 | case ISD::AssertZext: { | |||
1787 | // AssertZext demands all of the high bits, plus any of the low bits | |||
1788 | // demanded by its users. | |||
1789 | EVT ZVT = cast<VTSDNode>(Op.getOperand(1))->getVT(); | |||
1790 | APInt InMask = APInt::getLowBitsSet(BitWidth, ZVT.getSizeInBits()); | |||
1791 | if (SimplifyDemandedBits(Op.getOperand(0), ~InMask | DemandedBits, Known, | |||
1792 | TLO, Depth + 1)) | |||
1793 | return true; | |||
1794 | assert(!Known.hasConflict() && "Bits known to be one AND zero?")((!Known.hasConflict() && "Bits known to be one AND zero?" ) ? static_cast<void> (0) : __assert_fail ("!Known.hasConflict() && \"Bits known to be one AND zero?\"" , "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 1794, __PRETTY_FUNCTION__)); | |||
1795 | ||||
1796 | Known.Zero |= ~InMask; | |||
1797 | break; | |||
1798 | } | |||
1799 | case ISD::EXTRACT_VECTOR_ELT: { | |||
1800 | SDValue Src = Op.getOperand(0); | |||
1801 | SDValue Idx = Op.getOperand(1); | |||
1802 | unsigned NumSrcElts = Src.getValueType().getVectorNumElements(); | |||
1803 | unsigned EltBitWidth = Src.getScalarValueSizeInBits(); | |||
1804 | ||||
1805 | // Demand the bits from every vector element without a constant index. | |||
1806 | APInt DemandedSrcElts = APInt::getAllOnesValue(NumSrcElts); | |||
1807 | if (auto *CIdx = dyn_cast<ConstantSDNode>(Idx)) | |||
1808 | if (CIdx->getAPIntValue().ult(NumSrcElts)) | |||
1809 | DemandedSrcElts = APInt::getOneBitSet(NumSrcElts, CIdx->getZExtValue()); | |||
1810 | ||||
1811 | // If BitWidth > EltBitWidth the value is anyext:ed. So we do not know | |||
1812 | // anything about the extended bits. | |||
1813 | APInt DemandedSrcBits = DemandedBits; | |||
1814 | if (BitWidth > EltBitWidth) | |||
1815 | DemandedSrcBits = DemandedSrcBits.trunc(EltBitWidth); | |||
1816 | ||||
1817 | if (SimplifyDemandedBits(Src, DemandedSrcBits, DemandedSrcElts, Known2, TLO, | |||
1818 | Depth + 1)) | |||
1819 | return true; | |||
1820 | ||||
1821 | Known = Known2; | |||
1822 | if (BitWidth > EltBitWidth) | |||
1823 | Known = Known.zext(BitWidth, false /* => any extend */); | |||
1824 | break; | |||
1825 | } | |||
1826 | case ISD::BITCAST: { | |||
1827 | SDValue Src = Op.getOperand(0); | |||
1828 | EVT SrcVT = Src.getValueType(); | |||
1829 | unsigned NumSrcEltBits = SrcVT.getScalarSizeInBits(); | |||
1830 | ||||
1831 | // If this is an FP->Int bitcast and if the sign bit is the only | |||
1832 | // thing demanded, turn this into a FGETSIGN. | |||
1833 | if (!TLO.LegalOperations() && !VT.isVector() && !SrcVT.isVector() && | |||
1834 | DemandedBits == APInt::getSignMask(Op.getValueSizeInBits()) && | |||
1835 | SrcVT.isFloatingPoint()) { | |||
1836 | bool OpVTLegal = isOperationLegalOrCustom(ISD::FGETSIGN, VT); | |||
1837 | bool i32Legal = isOperationLegalOrCustom(ISD::FGETSIGN, MVT::i32); | |||
1838 | if ((OpVTLegal || i32Legal) && VT.isSimple() && SrcVT != MVT::f16 && | |||
1839 | SrcVT != MVT::f128) { | |||
1840 | // Cannot eliminate/lower SHL for f128 yet. | |||
1841 | EVT Ty = OpVTLegal ? VT : MVT::i32; | |||
1842 | // Make a FGETSIGN + SHL to move the sign bit into the appropriate | |||
1843 | // place. We expect the SHL to be eliminated by other optimizations. | |||
1844 | SDValue Sign = TLO.DAG.getNode(ISD::FGETSIGN, dl, Ty, Src); | |||
1845 | unsigned OpVTSizeInBits = Op.getValueSizeInBits(); | |||
1846 | if (!OpVTLegal && OpVTSizeInBits > 32) | |||
1847 | Sign = TLO.DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Sign); | |||
1848 | unsigned ShVal = Op.getValueSizeInBits() - 1; | |||
1849 | SDValue ShAmt = TLO.DAG.getConstant(ShVal, dl, VT); | |||
1850 | return TLO.CombineTo(Op, | |||
1851 | TLO.DAG.getNode(ISD::SHL, dl, VT, Sign, ShAmt)); | |||
1852 | } | |||
1853 | } | |||
1854 | ||||
1855 | // Bitcast from a vector using SimplifyDemanded Bits/VectorElts. | |||
1856 | // Demand the elt/bit if any of the original elts/bits are demanded. | |||
1857 | // TODO - bigendian once we have test coverage. | |||
1858 | if (SrcVT.isVector() && (BitWidth % NumSrcEltBits) == 0 && | |||
1859 | TLO.DAG.getDataLayout().isLittleEndian()) { | |||
1860 | unsigned Scale = BitWidth / NumSrcEltBits; | |||
1861 | unsigned NumSrcElts = SrcVT.getVectorNumElements(); | |||
1862 | APInt DemandedSrcBits = APInt::getNullValue(NumSrcEltBits); | |||
1863 | APInt DemandedSrcElts = APInt::getNullValue(NumSrcElts); | |||
1864 | for (unsigned i = 0; i != Scale; ++i) { | |||
1865 | unsigned Offset = i * NumSrcEltBits; | |||
1866 | APInt Sub = DemandedBits.extractBits(NumSrcEltBits, Offset); | |||
1867 | if (!Sub.isNullValue()) { | |||
1868 | DemandedSrcBits |= Sub; | |||
1869 | for (unsigned j = 0; j != NumElts; ++j) | |||
1870 | if (DemandedElts[j]) | |||
1871 | DemandedSrcElts.setBit((j * Scale) + i); | |||
1872 | } | |||
1873 | } | |||
1874 | ||||
1875 | APInt KnownSrcUndef, KnownSrcZero; | |||
1876 | if (SimplifyDemandedVectorElts(Src, DemandedSrcElts, KnownSrcUndef, | |||
1877 | KnownSrcZero, TLO, Depth + 1)) | |||
1878 | return true; | |||
1879 | ||||
1880 | KnownBits KnownSrcBits; | |||
1881 | if (SimplifyDemandedBits(Src, DemandedSrcBits, DemandedSrcElts, | |||
1882 | KnownSrcBits, TLO, Depth + 1)) | |||
1883 | return true; | |||
1884 | } else if ((NumSrcEltBits % BitWidth) == 0 && | |||
1885 | TLO.DAG.getDataLayout().isLittleEndian()) { | |||
1886 | unsigned Scale = NumSrcEltBits / BitWidth; | |||
1887 | unsigned NumSrcElts = SrcVT.isVector() ? SrcVT.getVectorNumElements() : 1; | |||
1888 | APInt DemandedSrcBits = APInt::getNullValue(NumSrcEltBits); | |||
1889 | APInt DemandedSrcElts = APInt::getNullValue(NumSrcElts); | |||
1890 | for (unsigned i = 0; i != NumElts; ++i) | |||
1891 | if (DemandedElts[i]) { | |||
1892 | unsigned Offset = (i % Scale) * BitWidth; | |||
1893 | DemandedSrcBits.insertBits(DemandedBits, Offset); | |||
1894 | DemandedSrcElts.setBit(i / Scale); | |||
1895 | } | |||
1896 | ||||
1897 | if (SrcVT.isVector()) { | |||
1898 | APInt KnownSrcUndef, KnownSrcZero; | |||
1899 | if (SimplifyDemandedVectorElts(Src, DemandedSrcElts, KnownSrcUndef, | |||
1900 | KnownSrcZero, TLO, Depth + 1)) | |||
1901 | return true; | |||
1902 | } | |||
1903 | ||||
1904 | KnownBits KnownSrcBits; | |||
1905 | if (SimplifyDemandedBits(Src, DemandedSrcBits, DemandedSrcElts, | |||
1906 | KnownSrcBits, TLO, Depth + 1)) | |||
1907 | return true; | |||
1908 | } | |||
1909 | ||||
1910 | // If this is a bitcast, let computeKnownBits handle it. Only do this on a | |||
1911 | // recursive call where Known may be useful to the caller. | |||
1912 | if (Depth > 0) { | |||
1913 | Known = TLO.DAG.computeKnownBits(Op, DemandedElts, Depth); | |||
1914 | return false; | |||
1915 | } | |||
1916 | break; | |||
1917 | } | |||
1918 | case ISD::ADD: | |||
1919 | case ISD::MUL: | |||
1920 | case ISD::SUB: { | |||
1921 | // Add, Sub, and Mul don't demand any bits in positions beyond that | |||
1922 | // of the highest bit demanded of them. | |||
1923 | SDValue Op0 = Op.getOperand(0), Op1 = Op.getOperand(1); | |||
1924 | SDNodeFlags Flags = Op.getNode()->getFlags(); | |||
1925 | unsigned DemandedBitsLZ = DemandedBits.countLeadingZeros(); | |||
1926 | APInt LoMask = APInt::getLowBitsSet(BitWidth, BitWidth - DemandedBitsLZ); | |||
1927 | if (SimplifyDemandedBits(Op0, LoMask, DemandedElts, Known2, TLO, | |||
1928 | Depth + 1) || | |||
1929 | SimplifyDemandedBits(Op1, LoMask, DemandedElts, Known2, TLO, | |||
1930 | Depth + 1) || | |||
1931 | // See if the operation should be performed at a smaller bit width. | |||
1932 | ShrinkDemandedOp(Op, BitWidth, DemandedBits, TLO)) { | |||
1933 | if (Flags.hasNoSignedWrap() || Flags.hasNoUnsignedWrap()) { | |||
1934 | // Disable the nsw and nuw flags. We can no longer guarantee that we | |||
1935 | // won't wrap after simplification. | |||
1936 | Flags.setNoSignedWrap(false); | |||
1937 | Flags.setNoUnsignedWrap(false); | |||
1938 | SDValue NewOp = | |||
1939 | TLO.DAG.getNode(Op.getOpcode(), dl, VT, Op0, Op1, Flags); | |||
1940 | return TLO.CombineTo(Op, NewOp); | |||
1941 | } | |||
1942 | return true; | |||
1943 | } | |||
1944 | ||||
1945 | // Attempt to avoid multi-use ops if we don't need anything from them. | |||
1946 | if (!LoMask.isAllOnesValue() || !DemandedElts.isAllOnesValue()) { | |||
1947 | SDValue DemandedOp0 = SimplifyMultipleUseDemandedBits( | |||
1948 | Op0, LoMask, DemandedElts, TLO.DAG, Depth + 1); | |||
1949 | SDValue DemandedOp1 = SimplifyMultipleUseDemandedBits( | |||
1950 | Op1, LoMask, DemandedElts, TLO.DAG, Depth + 1); | |||
1951 | if (DemandedOp0 || DemandedOp1) { | |||
1952 | Flags.setNoSignedWrap(false); | |||
1953 | Flags.setNoUnsignedWrap(false); | |||
1954 | Op0 = DemandedOp0 ? DemandedOp0 : Op0; | |||
1955 | Op1 = DemandedOp1 ? DemandedOp1 : Op1; | |||
1956 | SDValue NewOp = | |||
1957 | TLO.DAG.getNode(Op.getOpcode(), dl, VT, Op0, Op1, Flags); | |||
1958 | return TLO.CombineTo(Op, NewOp); | |||
1959 | } | |||
1960 | } | |||
1961 | ||||
1962 | // If we have a constant operand, we may be able to turn it into -1 if we | |||
1963 | // do not demand the high bits. This can make the constant smaller to | |||
1964 | // encode, allow more general folding, or match specialized instruction | |||
1965 | // patterns (eg, 'blsr' on x86). Don't bother changing 1 to -1 because that | |||
1966 | // is probably not useful (and could be detrimental). | |||
1967 | ConstantSDNode *C = isConstOrConstSplat(Op1); | |||
1968 | APInt HighMask = APInt::getHighBitsSet(BitWidth, DemandedBitsLZ); | |||
1969 | if (C && !C->isAllOnesValue() && !C->isOne() && | |||
1970 | (C->getAPIntValue() | HighMask).isAllOnesValue()) { | |||
1971 | SDValue Neg1 = TLO.DAG.getAllOnesConstant(dl, VT); | |||
1972 | // Disable the nsw and nuw flags. We can no longer guarantee that we | |||
1973 | // won't wrap after simplification. | |||
1974 | Flags.setNoSignedWrap(false); | |||
1975 | Flags.setNoUnsignedWrap(false); | |||
1976 | SDValue NewOp = TLO.DAG.getNode(Op.getOpcode(), dl, VT, Op0, Neg1, Flags); | |||
1977 | return TLO.CombineTo(Op, NewOp); | |||
1978 | } | |||
1979 | ||||
1980 | LLVM_FALLTHROUGH[[gnu::fallthrough]]; | |||
1981 | } | |||
1982 | default: | |||
1983 | if (Op.getOpcode() >= ISD::BUILTIN_OP_END) { | |||
1984 | if (SimplifyDemandedBitsForTargetNode(Op, DemandedBits, DemandedElts, | |||
1985 | Known, TLO, Depth)) | |||
1986 | return true; | |||
1987 | break; | |||
1988 | } | |||
1989 | ||||
1990 | // Just use computeKnownBits to compute output bits. | |||
1991 | Known = TLO.DAG.computeKnownBits(Op, DemandedElts, Depth); | |||
1992 | break; | |||
1993 | } | |||
1994 | ||||
1995 | // If we know the value of all of the demanded bits, return this as a | |||
1996 | // constant. | |||
1997 | if (DemandedBits.isSubsetOf(Known.Zero | Known.One)) { | |||
1998 | // Avoid folding to a constant if any OpaqueConstant is involved. | |||
1999 | const SDNode *N = Op.getNode(); | |||
2000 | for (SDNodeIterator I = SDNodeIterator::begin(N), | |||
2001 | E = SDNodeIterator::end(N); | |||
2002 | I != E; ++I) { | |||
2003 | SDNode *Op = *I; | |||
2004 | if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) | |||
2005 | if (C->isOpaque()) | |||
2006 | return false; | |||
2007 | } | |||
2008 | // TODO: Handle float bits as well. | |||
2009 | if (VT.isInteger()) | |||
2010 | return TLO.CombineTo(Op, TLO.DAG.getConstant(Known.One, dl, VT)); | |||
2011 | } | |||
2012 | ||||
2013 | return false; | |||
2014 | } | |||
2015 | ||||
2016 | bool TargetLowering::SimplifyDemandedVectorElts(SDValue Op, | |||
2017 | const APInt &DemandedElts, | |||
2018 | APInt &KnownUndef, | |||
2019 | APInt &KnownZero, | |||
2020 | DAGCombinerInfo &DCI) const { | |||
2021 | SelectionDAG &DAG = DCI.DAG; | |||
2022 | TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(), | |||
2023 | !DCI.isBeforeLegalizeOps()); | |||
2024 | ||||
2025 | bool Simplified = | |||
2026 | SimplifyDemandedVectorElts(Op, DemandedElts, KnownUndef, KnownZero, TLO); | |||
2027 | if (Simplified) { | |||
2028 | DCI.AddToWorklist(Op.getNode()); | |||
2029 | DCI.CommitTargetLoweringOpt(TLO); | |||
2030 | } | |||
2031 | ||||
2032 | return Simplified; | |||
2033 | } | |||
2034 | ||||
2035 | /// Given a vector binary operation and known undefined elements for each input | |||
2036 | /// operand, compute whether each element of the output is undefined. | |||
2037 | static APInt getKnownUndefForVectorBinop(SDValue BO, SelectionDAG &DAG, | |||
2038 | const APInt &UndefOp0, | |||
2039 | const APInt &UndefOp1) { | |||
2040 | EVT VT = BO.getValueType(); | |||
2041 | assert(DAG.getTargetLoweringInfo().isBinOp(BO.getOpcode()) && VT.isVector() &&((DAG.getTargetLoweringInfo().isBinOp(BO.getOpcode()) && VT.isVector() && "Vector binop only") ? static_cast< void> (0) : __assert_fail ("DAG.getTargetLoweringInfo().isBinOp(BO.getOpcode()) && VT.isVector() && \"Vector binop only\"" , "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 2042, __PRETTY_FUNCTION__)) | |||
2042 | "Vector binop only")((DAG.getTargetLoweringInfo().isBinOp(BO.getOpcode()) && VT.isVector() && "Vector binop only") ? static_cast< void> (0) : __assert_fail ("DAG.getTargetLoweringInfo().isBinOp(BO.getOpcode()) && VT.isVector() && \"Vector binop only\"" , "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 2042, __PRETTY_FUNCTION__)); | |||
2043 | ||||
2044 | EVT EltVT = VT.getVectorElementType(); | |||
2045 | unsigned NumElts = VT.getVectorNumElements(); | |||
2046 | assert(UndefOp0.getBitWidth() == NumElts &&((UndefOp0.getBitWidth() == NumElts && UndefOp1.getBitWidth () == NumElts && "Bad type for undef analysis") ? static_cast <void> (0) : __assert_fail ("UndefOp0.getBitWidth() == NumElts && UndefOp1.getBitWidth() == NumElts && \"Bad type for undef analysis\"" , "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 2047, __PRETTY_FUNCTION__)) | |||
2047 | UndefOp1.getBitWidth() == NumElts && "Bad type for undef analysis")((UndefOp0.getBitWidth() == NumElts && UndefOp1.getBitWidth () == NumElts && "Bad type for undef analysis") ? static_cast <void> (0) : __assert_fail ("UndefOp0.getBitWidth() == NumElts && UndefOp1.getBitWidth() == NumElts && \"Bad type for undef analysis\"" , "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 2047, __PRETTY_FUNCTION__)); | |||
2048 | ||||
2049 | auto getUndefOrConstantElt = [&](SDValue V, unsigned Index, | |||
2050 | const APInt &UndefVals) { | |||
2051 | if (UndefVals[Index]) | |||
2052 | return DAG.getUNDEF(EltVT); | |||
2053 | ||||
2054 | if (auto *BV = dyn_cast<BuildVectorSDNode>(V)) { | |||
2055 | // Try hard to make sure that the getNode() call is not creating temporary | |||
2056 | // nodes. Ignore opaque integers because they do not constant fold. | |||
2057 | SDValue Elt = BV->getOperand(Index); | |||
2058 | auto *C = dyn_cast<ConstantSDNode>(Elt); | |||
2059 | if (isa<ConstantFPSDNode>(Elt) || Elt.isUndef() || (C && !C->isOpaque())) | |||
2060 | return Elt; | |||
2061 | } | |||
2062 | ||||
2063 | return SDValue(); | |||
2064 | }; | |||
2065 | ||||
2066 | APInt KnownUndef = APInt::getNullValue(NumElts); | |||
2067 | for (unsigned i = 0; i != NumElts; ++i) { | |||
2068 | // If both inputs for this element are either constant or undef and match | |||
2069 | // the element type, compute the constant/undef result for this element of | |||
2070 | // the vector. | |||
2071 | // TODO: Ideally we would use FoldConstantArithmetic() here, but that does | |||
2072 | // not handle FP constants. The code within getNode() should be refactored | |||
2073 | // to avoid the danger of creating a bogus temporary node here. | |||
2074 | SDValue C0 = getUndefOrConstantElt(BO.getOperand(0), i, UndefOp0); | |||
2075 | SDValue C1 = getUndefOrConstantElt(BO.getOperand(1), i, UndefOp1); | |||
2076 | if (C0 && C1 && C0.getValueType() == EltVT && C1.getValueType() == EltVT) | |||
2077 | if (DAG.getNode(BO.getOpcode(), SDLoc(BO), EltVT, C0, C1).isUndef()) | |||
2078 | KnownUndef.setBit(i); | |||
2079 | } | |||
2080 | return KnownUndef; | |||
2081 | } | |||
2082 | ||||
2083 | bool TargetLowering::SimplifyDemandedVectorElts( | |||
2084 | SDValue Op, const APInt &OriginalDemandedElts, APInt &KnownUndef, | |||
2085 | APInt &KnownZero, TargetLoweringOpt &TLO, unsigned Depth, | |||
2086 | bool AssumeSingleUse) const { | |||
2087 | EVT VT = Op.getValueType(); | |||
2088 | APInt DemandedElts = OriginalDemandedElts; | |||
2089 | unsigned NumElts = DemandedElts.getBitWidth(); | |||
2090 | assert(VT.isVector() && "Expected vector op")((VT.isVector() && "Expected vector op") ? static_cast <void> (0) : __assert_fail ("VT.isVector() && \"Expected vector op\"" , "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 2090, __PRETTY_FUNCTION__)); | |||
2091 | assert(VT.getVectorNumElements() == NumElts &&((VT.getVectorNumElements() == NumElts && "Mask size mismatches value type element count!" ) ? static_cast<void> (0) : __assert_fail ("VT.getVectorNumElements() == NumElts && \"Mask size mismatches value type element count!\"" , "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 2092, __PRETTY_FUNCTION__)) | |||
2092 | "Mask size mismatches value type element count!")((VT.getVectorNumElements() == NumElts && "Mask size mismatches value type element count!" ) ? static_cast<void> (0) : __assert_fail ("VT.getVectorNumElements() == NumElts && \"Mask size mismatches value type element count!\"" , "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 2092, __PRETTY_FUNCTION__)); | |||
2093 | ||||
2094 | KnownUndef = KnownZero = APInt::getNullValue(NumElts); | |||
2095 | ||||
2096 | // Undef operand. | |||
2097 | if (Op.isUndef()) { | |||
2098 | KnownUndef.setAllBits(); | |||
2099 | return false; | |||
2100 | } | |||
2101 | ||||
2102 | // If Op has other users, assume that all elements are needed. | |||
2103 | if (!Op.getNode()->hasOneUse() && !AssumeSingleUse) | |||
2104 | DemandedElts.setAllBits(); | |||
2105 | ||||
2106 | // Not demanding any elements from Op. | |||
2107 | if (DemandedElts == 0) { | |||
2108 | KnownUndef.setAllBits(); | |||
2109 | return TLO.CombineTo(Op, TLO.DAG.getUNDEF(VT)); | |||
2110 | } | |||
2111 | ||||
2112 | // Limit search depth. | |||
2113 | if (Depth >= SelectionDAG::MaxRecursionDepth) | |||
2114 | return false; | |||
2115 | ||||
2116 | SDLoc DL(Op); | |||
2117 | unsigned EltSizeInBits = VT.getScalarSizeInBits(); | |||
2118 | ||||
2119 | switch (Op.getOpcode()) { | |||
2120 | case ISD::SCALAR_TO_VECTOR: { | |||
2121 | if (!DemandedElts[0]) { | |||
2122 | KnownUndef.setAllBits(); | |||
2123 | return TLO.CombineTo(Op, TLO.DAG.getUNDEF(VT)); | |||
2124 | } | |||
2125 | KnownUndef.setHighBits(NumElts - 1); | |||
2126 | break; | |||
2127 | } | |||
2128 | case ISD::BITCAST: { | |||
2129 | SDValue Src = Op.getOperand(0); | |||
2130 | EVT SrcVT = Src.getValueType(); | |||
2131 | ||||
2132 | // We only handle vectors here. | |||
2133 | // TODO - investigate calling SimplifyDemandedBits/ComputeKnownBits? | |||
2134 | if (!SrcVT.isVector()) | |||
2135 | break; | |||
2136 | ||||
2137 | // Fast handling of 'identity' bitcasts. | |||
2138 | unsigned NumSrcElts = SrcVT.getVectorNumElements(); | |||
2139 | if (NumSrcElts == NumElts) | |||
2140 | return SimplifyDemandedVectorElts(Src, DemandedElts, KnownUndef, | |||
2141 | KnownZero, TLO, Depth + 1); | |||
2142 | ||||
2143 | APInt SrcZero, SrcUndef; | |||
2144 | APInt SrcDemandedElts = APInt::getNullValue(NumSrcElts); | |||
2145 | ||||
2146 | // Bitcast from 'large element' src vector to 'small element' vector, we | |||
2147 | // must demand a source element if any DemandedElt maps to it. | |||
2148 | if ((NumElts % NumSrcElts) == 0) { | |||
2149 | unsigned Scale = NumElts / NumSrcElts; | |||
2150 | for (unsigned i = 0; i != NumElts; ++i) | |||
2151 | if (DemandedElts[i]) | |||
2152 | SrcDemandedElts.setBit(i / Scale); | |||
2153 | ||||
2154 | if (SimplifyDemandedVectorElts(Src, SrcDemandedElts, SrcUndef, SrcZero, | |||
2155 | TLO, Depth + 1)) | |||
2156 | return true; | |||
2157 | ||||
2158 | // Try calling SimplifyDemandedBits, converting demanded elts to the bits | |||
2159 | // of the large element. | |||
2160 | // TODO - bigendian once we have test coverage. | |||
2161 | if (TLO.DAG.getDataLayout().isLittleEndian()) { | |||
2162 | unsigned SrcEltSizeInBits = SrcVT.getScalarSizeInBits(); | |||
2163 | APInt SrcDemandedBits = APInt::getNullValue(SrcEltSizeInBits); | |||
2164 | for (unsigned i = 0; i != NumElts; ++i) | |||
2165 | if (DemandedElts[i]) { | |||
2166 | unsigned Ofs = (i % Scale) * EltSizeInBits; | |||
2167 | SrcDemandedBits.setBits(Ofs, Ofs + EltSizeInBits); | |||
2168 | } | |||
2169 | ||||
2170 | KnownBits Known; | |||
2171 | if (SimplifyDemandedBits(Src, SrcDemandedBits, Known, TLO, Depth + 1)) | |||
2172 | return true; | |||
2173 | } | |||
2174 | ||||
2175 | // If the src element is zero/undef then all the output elements will be - | |||
2176 | // only demanded elements are guaranteed to be correct. | |||
2177 | for (unsigned i = 0; i != NumSrcElts; ++i) { | |||
2178 | if (SrcDemandedElts[i]) { | |||
2179 | if (SrcZero[i]) | |||
2180 | KnownZero.setBits(i * Scale, (i + 1) * Scale); | |||
2181 | if (SrcUndef[i]) | |||
2182 | KnownUndef.setBits(i * Scale, (i + 1) * Scale); | |||
2183 | } | |||
2184 | } | |||
2185 | } | |||
2186 | ||||
2187 | // Bitcast from 'small element' src vector to 'large element' vector, we | |||
2188 | // demand all smaller source elements covered by the larger demanded element | |||
2189 | // of this vector. | |||
2190 | if ((NumSrcElts % NumElts) == 0) { | |||
2191 | unsigned Scale = NumSrcElts / NumElts; | |||
2192 | for (unsigned i = 0; i != NumElts; ++i) | |||
2193 | if (DemandedElts[i]) | |||
2194 | SrcDemandedElts.setBits(i * Scale, (i + 1) * Scale); | |||
2195 | ||||
2196 | if (SimplifyDemandedVectorElts(Src, SrcDemandedElts, SrcUndef, SrcZero, | |||
2197 | TLO, Depth + 1)) | |||
2198 | return true; | |||
2199 | ||||
2200 | // If all the src elements covering an output element are zero/undef, then | |||
2201 | // the output element will be as well, assuming it was demanded. | |||
2202 | for (unsigned i = 0; i != NumElts; ++i) { | |||
2203 | if (DemandedElts[i]) { | |||
2204 | if (SrcZero.extractBits(Scale, i * Scale).isAllOnesValue()) | |||
2205 | KnownZero.setBit(i); | |||
2206 | if (SrcUndef.extractBits(Scale, i * Scale).isAllOnesValue()) | |||
2207 | KnownUndef.setBit(i); | |||
2208 | } | |||
2209 | } | |||
2210 | } | |||
2211 | break; | |||
2212 | } | |||
2213 | case ISD::BUILD_VECTOR: { | |||
2214 | // Check all elements and simplify any unused elements with UNDEF. | |||
2215 | if (!DemandedElts.isAllOnesValue()) { | |||
2216 | // Don't simplify BROADCASTS. | |||
2217 | if (llvm::any_of(Op->op_values(), | |||
2218 | [&](SDValue Elt) { return Op.getOperand(0) != Elt; })) { | |||
2219 | SmallVector<SDValue, 32> Ops(Op->op_begin(), Op->op_end()); | |||
2220 | bool Updated = false; | |||
2221 | for (unsigned i = 0; i != NumElts; ++i) { | |||
2222 | if (!DemandedElts[i] && !Ops[i].isUndef()) { | |||
2223 | Ops[i] = TLO.DAG.getUNDEF(Ops[0].getValueType()); | |||
2224 | KnownUndef.setBit(i); | |||
2225 | Updated = true; | |||
2226 | } | |||
2227 | } | |||
2228 | if (Updated) | |||
2229 | return TLO.CombineTo(Op, TLO.DAG.getBuildVector(VT, DL, Ops)); | |||
2230 | } | |||
2231 | } | |||
2232 | for (unsigned i = 0; i != NumElts; ++i) { | |||
2233 | SDValue SrcOp = Op.getOperand(i); | |||
2234 | if (SrcOp.isUndef()) { | |||
2235 | KnownUndef.setBit(i); | |||
2236 | } else if (EltSizeInBits == SrcOp.getScalarValueSizeInBits() && | |||
2237 | (isNullConstant(SrcOp) || isNullFPConstant(SrcOp))) { | |||
2238 | KnownZero.setBit(i); | |||
2239 | } | |||
2240 | } | |||
2241 | break; | |||
2242 | } | |||
2243 | case ISD::CONCAT_VECTORS: { | |||
2244 | EVT SubVT = Op.getOperand(0).getValueType(); | |||
2245 | unsigned NumSubVecs = Op.getNumOperands(); | |||
2246 | unsigned NumSubElts = SubVT.getVectorNumElements(); | |||
2247 | for (unsigned i = 0; i != NumSubVecs; ++i) { | |||
2248 | SDValue SubOp = Op.getOperand(i); | |||
2249 | APInt SubElts = DemandedElts.extractBits(NumSubElts, i * NumSubElts); | |||
2250 | APInt SubUndef, SubZero; | |||
2251 | if (SimplifyDemandedVectorElts(SubOp, SubElts, SubUndef, SubZero, TLO, | |||
2252 | Depth + 1)) | |||
2253 | return true; | |||
2254 | KnownUndef.insertBits(SubUndef, i * NumSubElts); | |||
2255 | KnownZero.insertBits(SubZero, i * NumSubElts); | |||
2256 | } | |||
2257 | break; | |||
2258 | } | |||
2259 | case ISD::INSERT_SUBVECTOR: { | |||
2260 | if (!isa<ConstantSDNode>(Op.getOperand(2))) | |||
2261 | break; | |||
2262 | SDValue Base = Op.getOperand(0); | |||
2263 | SDValue Sub = Op.getOperand(1); | |||
2264 | EVT SubVT = Sub.getValueType(); | |||
2265 | unsigned NumSubElts = SubVT.getVectorNumElements(); | |||
2266 | const APInt &Idx = Op.getConstantOperandAPInt(2); | |||
2267 | if (Idx.ugt(NumElts - NumSubElts)) | |||
2268 | break; | |||
2269 | unsigned SubIdx = Idx.getZExtValue(); | |||
2270 | APInt SubElts = DemandedElts.extractBits(NumSubElts, SubIdx); | |||
2271 | APInt SubUndef, SubZero; | |||
2272 | if (SimplifyDemandedVectorElts(Sub, SubElts, SubUndef, SubZero, TLO, | |||
2273 | Depth + 1)) | |||
2274 | return true; | |||
2275 | APInt BaseElts = DemandedElts; | |||
2276 | BaseElts.insertBits(APInt::getNullValue(NumSubElts), SubIdx); | |||
2277 | ||||
2278 | // If none of the base operand elements are demanded, replace it with undef. | |||
2279 | if (!BaseElts && !Base.isUndef()) | |||
2280 | return TLO.CombineTo(Op, | |||
2281 | TLO.DAG.getNode(ISD::INSERT_SUBVECTOR, DL, VT, | |||
2282 | TLO.DAG.getUNDEF(VT), | |||
2283 | Op.getOperand(1), | |||
2284 | Op.getOperand(2))); | |||
2285 | ||||
2286 | if (SimplifyDemandedVectorElts(Base, BaseElts, KnownUndef, KnownZero, TLO, | |||
2287 | Depth + 1)) | |||
2288 | return true; | |||
2289 | KnownUndef.insertBits(SubUndef, SubIdx); | |||
2290 | KnownZero.insertBits(SubZero, SubIdx); | |||
2291 | break; | |||
2292 | } | |||
2293 | case ISD::EXTRACT_SUBVECTOR: { | |||
2294 | SDValue Src = Op.getOperand(0); | |||
2295 | ConstantSDNode *SubIdx = dyn_cast<ConstantSDNode>(Op.getOperand(1)); | |||
2296 | unsigned NumSrcElts = Src.getValueType().getVectorNumElements(); | |||
2297 | if (SubIdx && SubIdx->getAPIntValue().ule(NumSrcElts - NumElts)) { | |||
2298 | // Offset the demanded elts by the subvector index. | |||
2299 | uint64_t Idx = SubIdx->getZExtValue(); | |||
2300 | APInt SrcElts = DemandedElts.zextOrSelf(NumSrcElts).shl(Idx); | |||
2301 | APInt SrcUndef, SrcZero; | |||
2302 | if (SimplifyDemandedVectorElts(Src, SrcElts, SrcUndef, SrcZero, TLO, | |||
2303 | Depth + 1)) | |||
2304 | return true; | |||
2305 | KnownUndef = SrcUndef.extractBits(NumElts, Idx); | |||
2306 | KnownZero = SrcZero.extractBits(NumElts, Idx); | |||
2307 | } | |||
2308 | break; | |||
2309 | } | |||
2310 | case ISD::INSERT_VECTOR_ELT: { | |||
2311 | SDValue Vec = Op.getOperand(0); | |||
2312 | SDValue Scl = Op.getOperand(1); | |||
2313 | auto *CIdx = dyn_cast<ConstantSDNode>(Op.getOperand(2)); | |||
2314 | ||||
2315 | // For a legal, constant insertion index, if we don't need this insertion | |||
2316 | // then strip it, else remove it from the demanded elts. | |||
2317 | if (CIdx && CIdx->getAPIntValue().ult(NumElts)) { | |||
2318 | unsigned Idx = CIdx->getZExtValue(); | |||
2319 | if (!DemandedElts[Idx]) | |||
2320 | return TLO.CombineTo(Op, Vec); | |||
2321 | ||||
2322 | APInt DemandedVecElts(DemandedElts); | |||
2323 | DemandedVecElts.clearBit(Idx); | |||
2324 | if (SimplifyDemandedVectorElts(Vec, DemandedVecElts, KnownUndef, | |||
2325 | KnownZero, TLO, Depth + 1)) | |||
2326 | return true; | |||
2327 | ||||
2328 | KnownUndef.clearBit(Idx); | |||
2329 | if (Scl.isUndef()) | |||
2330 | KnownUndef.setBit(Idx); | |||
2331 | ||||
2332 | KnownZero.clearBit(Idx); | |||
2333 | if (isNullConstant(Scl) || isNullFPConstant(Scl)) | |||
2334 | KnownZero.setBit(Idx); | |||
2335 | break; | |||
2336 | } | |||
2337 | ||||
2338 | APInt VecUndef, VecZero; | |||
2339 | if (SimplifyDemandedVectorElts(Vec, DemandedElts, VecUndef, VecZero, TLO, | |||
2340 | Depth + 1)) | |||
2341 | return true; | |||
2342 | // Without knowing the insertion index we can't set KnownUndef/KnownZero. | |||
2343 | break; | |||
2344 | } | |||
2345 | case ISD::VSELECT: { | |||
2346 | // Try to transform the select condition based on the current demanded | |||
2347 | // elements. | |||
2348 | // TODO: If a condition element is undef, we can choose from one arm of the | |||
2349 | // select (and if one arm is undef, then we can propagate that to the | |||
2350 | // result). | |||
2351 | // TODO - add support for constant vselect masks (see IR version of this). | |||
2352 | APInt UnusedUndef, UnusedZero; | |||
2353 | if (SimplifyDemandedVectorElts(Op.getOperand(0), DemandedElts, UnusedUndef, | |||
2354 | UnusedZero, TLO, Depth + 1)) | |||
2355 | return true; | |||
2356 | ||||
2357 | // See if we can simplify either vselect operand. | |||
2358 | APInt DemandedLHS(DemandedElts); | |||
2359 | APInt DemandedRHS(DemandedElts); | |||
2360 | APInt UndefLHS, ZeroLHS; | |||
2361 | APInt UndefRHS, ZeroRHS; | |||
2362 | if (SimplifyDemandedVectorElts(Op.getOperand(1), DemandedLHS, UndefLHS, | |||
2363 | ZeroLHS, TLO, Depth + 1)) | |||
2364 | return true; | |||
2365 | if (SimplifyDemandedVectorElts(Op.getOperand(2), DemandedRHS, UndefRHS, | |||
2366 | ZeroRHS, TLO, Depth + 1)) | |||
2367 | return true; | |||
2368 | ||||
2369 | KnownUndef = UndefLHS & UndefRHS; | |||
2370 | KnownZero = ZeroLHS & ZeroRHS; | |||
2371 | break; | |||
2372 | } | |||
2373 | case ISD::VECTOR_SHUFFLE: { | |||
2374 | ArrayRef<int> ShuffleMask = cast<ShuffleVectorSDNode>(Op)->getMask(); | |||
2375 | ||||
2376 | // Collect demanded elements from shuffle operands.. | |||
2377 | APInt DemandedLHS(NumElts, 0); | |||
2378 | APInt DemandedRHS(NumElts, 0); | |||
2379 | for (unsigned i = 0; i != NumElts; ++i) { | |||
2380 | int M = ShuffleMask[i]; | |||
2381 | if (M < 0 || !DemandedElts[i]) | |||
2382 | continue; | |||
2383 | assert(0 <= M && M < (int)(2 * NumElts) && "Shuffle index out of range")((0 <= M && M < (int)(2 * NumElts) && "Shuffle index out of range" ) ? static_cast<void> (0) : __assert_fail ("0 <= M && M < (int)(2 * NumElts) && \"Shuffle index out of range\"" , "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 2383, __PRETTY_FUNCTION__)); | |||
2384 | if (M < (int)NumElts) | |||
2385 | DemandedLHS.setBit(M); | |||
2386 | else | |||
2387 | DemandedRHS.setBit(M - NumElts); | |||
2388 | } | |||
2389 | ||||
2390 | // See if we can simplify either shuffle operand. | |||
2391 | APInt UndefLHS, ZeroLHS; | |||
2392 | APInt UndefRHS, ZeroRHS; | |||
2393 | if (SimplifyDemandedVectorElts(Op.getOperand(0), DemandedLHS, UndefLHS, | |||
2394 | ZeroLHS, TLO, Depth + 1)) | |||
2395 | return true; | |||
2396 | if (SimplifyDemandedVectorElts(Op.getOperand(1), DemandedRHS, UndefRHS, | |||
2397 | ZeroRHS, TLO, Depth + 1)) | |||
2398 | return true; | |||
2399 | ||||
2400 | // Simplify mask using undef elements from LHS/RHS. | |||
2401 | bool Updated = false; | |||
2402 | bool IdentityLHS = true, IdentityRHS = true; | |||
2403 | SmallVector<int, 32> NewMask(ShuffleMask.begin(), ShuffleMask.end()); | |||
2404 | for (unsigned i = 0; i != NumElts; ++i) { | |||
2405 | int &M = NewMask[i]; | |||
2406 | if (M < 0) | |||
2407 | continue; | |||
2408 | if (!DemandedElts[i] || (M < (int)NumElts && UndefLHS[M]) || | |||
2409 | (M >= (int)NumElts && UndefRHS[M - NumElts])) { | |||
2410 | Updated = true; | |||
2411 | M = -1; | |||
2412 | } | |||
2413 | IdentityLHS &= (M < 0) || (M == (int)i); | |||
2414 | IdentityRHS &= (M < 0) || ((M - NumElts) == i); | |||
2415 | } | |||
2416 | ||||
2417 | // Update legal shuffle masks based on demanded elements if it won't reduce | |||
2418 | // to Identity which can cause premature removal of the shuffle mask. | |||
2419 | if (Updated && !IdentityLHS && !IdentityRHS && !TLO.LegalOps) { | |||
2420 | SDValue LegalShuffle = | |||
2421 | buildLegalVectorShuffle(VT, DL, Op.getOperand(0), Op.getOperand(1), | |||
2422 | NewMask, TLO.DAG); | |||
2423 | if (LegalShuffle) | |||
2424 | return TLO.CombineTo(Op, LegalShuffle); | |||
2425 | } | |||
2426 | ||||
2427 | // Propagate undef/zero elements from LHS/RHS. | |||
2428 | for (unsigned i = 0; i != NumElts; ++i) { | |||
2429 | int M = ShuffleMask[i]; | |||
2430 | if (M < 0) { | |||
2431 | KnownUndef.setBit(i); | |||
2432 | } else if (M < (int)NumElts) { | |||
2433 | if (UndefLHS[M]) | |||
2434 | KnownUndef.setBit(i); | |||
2435 | if (ZeroLHS[M]) | |||
2436 | KnownZero.setBit(i); | |||
2437 | } else { | |||
2438 | if (UndefRHS[M - NumElts]) | |||
2439 | KnownUndef.setBit(i); | |||
2440 | if (ZeroRHS[M - NumElts]) | |||
2441 | KnownZero.setBit(i); | |||
2442 | } | |||
2443 | } | |||
2444 | break; | |||
2445 | } | |||
2446 | case ISD::ANY_EXTEND_VECTOR_INREG: | |||
2447 | case ISD::SIGN_EXTEND_VECTOR_INREG: | |||
2448 | case ISD::ZERO_EXTEND_VECTOR_INREG: { | |||
2449 | APInt SrcUndef, SrcZero; | |||
2450 | SDValue Src = Op.getOperand(0); | |||
2451 | unsigned NumSrcElts = Src.getValueType().getVectorNumElements(); | |||
2452 | APInt DemandedSrcElts = DemandedElts.zextOrSelf(NumSrcElts); | |||
2453 | if (SimplifyDemandedVectorElts(Src, DemandedSrcElts, SrcUndef, SrcZero, TLO, | |||
2454 | Depth + 1)) | |||
2455 | return true; | |||
2456 | KnownZero = SrcZero.zextOrTrunc(NumElts); | |||
2457 | KnownUndef = SrcUndef.zextOrTrunc(NumElts); | |||
2458 | ||||
2459 | if (Op.getOpcode() == ISD::ANY_EXTEND_VECTOR_INREG && | |||
2460 | Op.getValueSizeInBits() == Src.getValueSizeInBits() && | |||
2461 | DemandedSrcElts == 1 && TLO.DAG.getDataLayout().isLittleEndian()) { | |||
2462 | // aext - if we just need the bottom element then we can bitcast. | |||
2463 | return TLO.CombineTo(Op, TLO.DAG.getBitcast(VT, Src)); | |||
2464 | } | |||
2465 | ||||
2466 | if (Op.getOpcode() == ISD::ZERO_EXTEND_VECTOR_INREG) { | |||
2467 | // zext(undef) upper bits are guaranteed to be zero. | |||
2468 | if (DemandedElts.isSubsetOf(KnownUndef)) | |||
2469 | return TLO.CombineTo(Op, TLO.DAG.getConstant(0, SDLoc(Op), VT)); | |||
2470 | KnownUndef.clearAllBits(); | |||
2471 | } | |||
2472 | break; | |||
2473 | } | |||
2474 | ||||
2475 | // TODO: There are more binop opcodes that could be handled here - MUL, MIN, | |||
2476 | // MAX, saturated math, etc. | |||
2477 | case ISD::OR: | |||
2478 | case ISD::XOR: | |||
2479 | case ISD::ADD: | |||
2480 | case ISD::SUB: | |||
2481 | case ISD::FADD: | |||
2482 | case ISD::FSUB: | |||
2483 | case ISD::FMUL: | |||
2484 | case ISD::FDIV: | |||
2485 | case ISD::FREM: { | |||
2486 | APInt UndefRHS, ZeroRHS; | |||
2487 | if (SimplifyDemandedVectorElts(Op.getOperand(1), DemandedElts, UndefRHS, | |||
2488 | ZeroRHS, TLO, Depth + 1)) | |||
2489 | return true; | |||
2490 | APInt UndefLHS, ZeroLHS; | |||
2491 | if (SimplifyDemandedVectorElts(Op.getOperand(0), DemandedElts, UndefLHS, | |||
2492 | ZeroLHS, TLO, Depth + 1)) | |||
2493 | return true; | |||
2494 | ||||
2495 | KnownZero = ZeroLHS & ZeroRHS; | |||
2496 | KnownUndef = getKnownUndefForVectorBinop(Op, TLO.DAG, UndefLHS, UndefRHS); | |||
2497 | break; | |||
2498 | } | |||
2499 | case ISD::SHL: | |||
2500 | case ISD::SRL: | |||
2501 | case ISD::SRA: | |||
2502 | case ISD::ROTL: | |||
2503 | case ISD::ROTR: { | |||
2504 | APInt UndefRHS, ZeroRHS; | |||
2505 | if (SimplifyDemandedVectorElts(Op.getOperand(1), DemandedElts, UndefRHS, | |||
2506 | ZeroRHS, TLO, Depth + 1)) | |||
2507 | return true; | |||
2508 | APInt UndefLHS, ZeroLHS; | |||
2509 | if (SimplifyDemandedVectorElts(Op.getOperand(0), DemandedElts, UndefLHS, | |||
2510 | ZeroLHS, TLO, Depth + 1)) | |||
2511 | return true; | |||
2512 | ||||
2513 | KnownZero = ZeroLHS; | |||
2514 | KnownUndef = UndefLHS & UndefRHS; // TODO: use getKnownUndefForVectorBinop? | |||
2515 | break; | |||
2516 | } | |||
2517 | case ISD::MUL: | |||
2518 | case ISD::AND: { | |||
2519 | APInt SrcUndef, SrcZero; | |||
2520 | if (SimplifyDemandedVectorElts(Op.getOperand(1), DemandedElts, SrcUndef, | |||
2521 | SrcZero, TLO, Depth + 1)) | |||
2522 | return true; | |||
2523 | if (SimplifyDemandedVectorElts(Op.getOperand(0), DemandedElts, KnownUndef, | |||
2524 | KnownZero, TLO, Depth + 1)) | |||
2525 | return true; | |||
2526 | ||||
2527 | // If either side has a zero element, then the result element is zero, even | |||
2528 | // if the other is an UNDEF. | |||
2529 | // TODO: Extend getKnownUndefForVectorBinop to also deal with known zeros | |||
2530 | // and then handle 'and' nodes with the rest of the binop opcodes. | |||
2531 | KnownZero |= SrcZero; | |||
2532 | KnownUndef &= SrcUndef; | |||
2533 | KnownUndef &= ~KnownZero; | |||
2534 | break; | |||
2535 | } | |||
2536 | case ISD::TRUNCATE: | |||
2537 | case ISD::SIGN_EXTEND: | |||
2538 | case ISD::ZERO_EXTEND: | |||
2539 | if (SimplifyDemandedVectorElts(Op.getOperand(0), DemandedElts, KnownUndef, | |||
2540 | KnownZero, TLO, Depth + 1)) | |||
2541 | return true; | |||
2542 | ||||
2543 | if (Op.getOpcode() == ISD::ZERO_EXTEND) { | |||
2544 | // zext(undef) upper bits are guaranteed to be zero. | |||
2545 | if (DemandedElts.isSubsetOf(KnownUndef)) | |||
2546 | return TLO.CombineTo(Op, TLO.DAG.getConstant(0, SDLoc(Op), VT)); | |||
2547 | KnownUndef.clearAllBits(); | |||
2548 | } | |||
2549 | break; | |||
2550 | default: { | |||
2551 | if (Op.getOpcode() >= ISD::BUILTIN_OP_END) { | |||
2552 | if (SimplifyDemandedVectorEltsForTargetNode(Op, DemandedElts, KnownUndef, | |||
2553 | KnownZero, TLO, Depth)) | |||
2554 | return true; | |||
2555 | } else { | |||
2556 | KnownBits Known; | |||
2557 | APInt DemandedBits = APInt::getAllOnesValue(EltSizeInBits); | |||
2558 | if (SimplifyDemandedBits(Op, DemandedBits, OriginalDemandedElts, Known, | |||
2559 | TLO, Depth, AssumeSingleUse)) | |||
2560 | return true; | |||
2561 | } | |||
2562 | break; | |||
2563 | } | |||
2564 | } | |||
2565 | assert((KnownUndef & KnownZero) == 0 && "Elements flagged as undef AND zero")(((KnownUndef & KnownZero) == 0 && "Elements flagged as undef AND zero" ) ? static_cast<void> (0) : __assert_fail ("(KnownUndef & KnownZero) == 0 && \"Elements flagged as undef AND zero\"" , "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 2565, __PRETTY_FUNCTION__)); | |||
2566 | ||||
2567 | // Constant fold all undef cases. | |||
2568 | // TODO: Handle zero cases as well. | |||
2569 | if (DemandedElts.isSubsetOf(KnownUndef)) | |||
2570 | return TLO.CombineTo(Op, TLO.DAG.getUNDEF(VT)); | |||
2571 | ||||
2572 | return false; | |||
2573 | } | |||
2574 | ||||
2575 | /// Determine which of the bits specified in Mask are known to be either zero or | |||
2576 | /// one and return them in the Known. | |||
2577 | void TargetLowering::computeKnownBitsForTargetNode(const SDValue Op, | |||
2578 | KnownBits &Known, | |||
2579 | const APInt &DemandedElts, | |||
2580 | const SelectionDAG &DAG, | |||
2581 | unsigned Depth) const { | |||
2582 | assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||(((Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && "Should use MaskedValueIsZero if you don't know whether Op" " is a target node!") ? static_cast<void> (0) : __assert_fail ("(Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && \"Should use MaskedValueIsZero if you don't know whether Op\" \" is a target node!\"" , "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 2587, __PRETTY_FUNCTION__)) | |||
2583 | Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||(((Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && "Should use MaskedValueIsZero if you don't know whether Op" " is a target node!") ? static_cast<void> (0) : __assert_fail ("(Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && \"Should use MaskedValueIsZero if you don't know whether Op\" \" is a target node!\"" , "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 2587, __PRETTY_FUNCTION__)) | |||
2584 | Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||(((Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && "Should use MaskedValueIsZero if you don't know whether Op" " is a target node!") ? static_cast<void> (0) : __assert_fail ("(Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && \"Should use MaskedValueIsZero if you don't know whether Op\" \" is a target node!\"" , "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 2587, __PRETTY_FUNCTION__)) | |||
2585 | Op.getOpcode() == ISD::INTRINSIC_VOID) &&(((Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && "Should use MaskedValueIsZero if you don't know whether Op" " is a target node!") ? static_cast<void> (0) : __assert_fail ("(Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && \"Should use MaskedValueIsZero if you don't know whether Op\" \" is a target node!\"" , "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 2587, __PRETTY_FUNCTION__)) | |||
2586 | "Should use MaskedValueIsZero if you don't know whether Op"(((Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && "Should use MaskedValueIsZero if you don't know whether Op" " is a target node!") ? static_cast<void> (0) : __assert_fail ("(Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && \"Should use MaskedValueIsZero if you don't know whether Op\" \" is a target node!\"" , "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 2587, __PRETTY_FUNCTION__)) | |||
2587 | " is a target node!")(((Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && "Should use MaskedValueIsZero if you don't know whether Op" " is a target node!") ? static_cast<void> (0) : __assert_fail ("(Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && \"Should use MaskedValueIsZero if you don't know whether Op\" \" is a target node!\"" , "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 2587, __PRETTY_FUNCTION__)); | |||
2588 | Known.resetAll(); | |||
2589 | } | |||
2590 | ||||
2591 | void TargetLowering::computeKnownBitsForTargetInstr( | |||
2592 | GISelKnownBits &Analysis, Register R, KnownBits &Known, | |||
2593 | const APInt &DemandedElts, const MachineRegisterInfo &MRI, | |||
2594 | unsigned Depth) const { | |||
2595 | Known.resetAll(); | |||
2596 | } | |||
2597 | ||||
2598 | void TargetLowering::computeKnownBitsForFrameIndex(const SDValue Op, | |||
2599 | KnownBits &Known, | |||
2600 | const APInt &DemandedElts, | |||
2601 | const SelectionDAG &DAG, | |||
2602 | unsigned Depth) const { | |||
2603 | assert(isa<FrameIndexSDNode>(Op) && "expected FrameIndex")((isa<FrameIndexSDNode>(Op) && "expected FrameIndex" ) ? static_cast<void> (0) : __assert_fail ("isa<FrameIndexSDNode>(Op) && \"expected FrameIndex\"" , "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 2603, __PRETTY_FUNCTION__)); | |||
2604 | ||||
2605 | if (unsigned Align = DAG.InferPtrAlignment(Op)) { | |||
2606 | // The low bits are known zero if the pointer is aligned. | |||
2607 | Known.Zero.setLowBits(Log2_32(Align)); | |||
2608 | } | |||
2609 | } | |||
2610 | ||||
2611 | /// This method can be implemented by targets that want to expose additional | |||
2612 | /// information about sign bits to the DAG Combiner. | |||
2613 | unsigned TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op, | |||
2614 | const APInt &, | |||
2615 | const SelectionDAG &, | |||
2616 | unsigned Depth) const { | |||
2617 | assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||(((Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && "Should use ComputeNumSignBits if you don't know whether Op" " is a target node!") ? static_cast<void> (0) : __assert_fail ("(Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && \"Should use ComputeNumSignBits if you don't know whether Op\" \" is a target node!\"" , "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 2622, __PRETTY_FUNCTION__)) | |||
2618 | Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||(((Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && "Should use ComputeNumSignBits if you don't know whether Op" " is a target node!") ? static_cast<void> (0) : __assert_fail ("(Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && \"Should use ComputeNumSignBits if you don't know whether Op\" \" is a target node!\"" , "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 2622, __PRETTY_FUNCTION__)) | |||
2619 | Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||(((Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && "Should use ComputeNumSignBits if you don't know whether Op" " is a target node!") ? static_cast<void> (0) : __assert_fail ("(Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && \"Should use ComputeNumSignBits if you don't know whether Op\" \" is a target node!\"" , "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 2622, __PRETTY_FUNCTION__)) | |||
2620 | Op.getOpcode() == ISD::INTRINSIC_VOID) &&(((Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && "Should use ComputeNumSignBits if you don't know whether Op" " is a target node!") ? static_cast<void> (0) : __assert_fail ("(Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && \"Should use ComputeNumSignBits if you don't know whether Op\" \" is a target node!\"" , "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 2622, __PRETTY_FUNCTION__)) | |||
2621 | "Should use ComputeNumSignBits if you don't know whether Op"(((Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && "Should use ComputeNumSignBits if you don't know whether Op" " is a target node!") ? static_cast<void> (0) : __assert_fail ("(Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && \"Should use ComputeNumSignBits if you don't know whether Op\" \" is a target node!\"" , "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 2622, __PRETTY_FUNCTION__)) | |||
2622 | " is a target node!")(((Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && "Should use ComputeNumSignBits if you don't know whether Op" " is a target node!") ? static_cast<void> (0) : __assert_fail ("(Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && \"Should use ComputeNumSignBits if you don't know whether Op\" \" is a target node!\"" , "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 2622, __PRETTY_FUNCTION__)); | |||
2623 | return 1; | |||
2624 | } | |||
2625 | ||||
2626 | bool TargetLowering::SimplifyDemandedVectorEltsForTargetNode( | |||
2627 | SDValue Op, const APInt &DemandedElts, APInt &KnownUndef, APInt &KnownZero, | |||
2628 | TargetLoweringOpt &TLO, unsigned Depth) const { | |||
2629 | assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||(((Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && "Should use SimplifyDemandedVectorElts if you don't know whether Op" " is a target node!") ? static_cast<void> (0) : __assert_fail ("(Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && \"Should use SimplifyDemandedVectorElts if you don't know whether Op\" \" is a target node!\"" , "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 2634, __PRETTY_FUNCTION__)) | |||
2630 | Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||(((Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && "Should use SimplifyDemandedVectorElts if you don't know whether Op" " is a target node!") ? static_cast<void> (0) : __assert_fail ("(Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && \"Should use SimplifyDemandedVectorElts if you don't know whether Op\" \" is a target node!\"" , "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 2634, __PRETTY_FUNCTION__)) | |||
2631 | Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||(((Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && "Should use SimplifyDemandedVectorElts if you don't know whether Op" " is a target node!") ? static_cast<void> (0) : __assert_fail ("(Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && \"Should use SimplifyDemandedVectorElts if you don't know whether Op\" \" is a target node!\"" , "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 2634, __PRETTY_FUNCTION__)) | |||
2632 | Op.getOpcode() == ISD::INTRINSIC_VOID) &&(((Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && "Should use SimplifyDemandedVectorElts if you don't know whether Op" " is a target node!") ? static_cast<void> (0) : __assert_fail ("(Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && \"Should use SimplifyDemandedVectorElts if you don't know whether Op\" \" is a target node!\"" , "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 2634, __PRETTY_FUNCTION__)) | |||
2633 | "Should use SimplifyDemandedVectorElts if you don't know whether Op"(((Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && "Should use SimplifyDemandedVectorElts if you don't know whether Op" " is a target node!") ? static_cast<void> (0) : __assert_fail ("(Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && \"Should use SimplifyDemandedVectorElts if you don't know whether Op\" \" is a target node!\"" , "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 2634, __PRETTY_FUNCTION__)) | |||
2634 | " is a target node!")(((Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && "Should use SimplifyDemandedVectorElts if you don't know whether Op" " is a target node!") ? static_cast<void> (0) : __assert_fail ("(Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && \"Should use SimplifyDemandedVectorElts if you don't know whether Op\" \" is a target node!\"" , "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 2634, __PRETTY_FUNCTION__)); | |||
2635 | return false; | |||
2636 | } | |||
2637 | ||||
2638 | bool TargetLowering::SimplifyDemandedBitsForTargetNode( | |||
2639 | SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts, | |||
2640 | KnownBits &Known, TargetLoweringOpt &TLO, unsigned Depth) const { | |||
2641 | assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||(((Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && "Should use SimplifyDemandedBits if you don't know whether Op" " is a target node!") ? static_cast<void> (0) : __assert_fail ("(Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && \"Should use SimplifyDemandedBits if you don't know whether Op\" \" is a target node!\"" , "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 2646, __PRETTY_FUNCTION__)) | |||
2642 | Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||(((Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && "Should use SimplifyDemandedBits if you don't know whether Op" " is a target node!") ? static_cast<void> (0) : __assert_fail ("(Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && \"Should use SimplifyDemandedBits if you don't know whether Op\" \" is a target node!\"" , "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 2646, __PRETTY_FUNCTION__)) | |||
2643 | Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||(((Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && "Should use SimplifyDemandedBits if you don't know whether Op" " is a target node!") ? static_cast<void> (0) : __assert_fail ("(Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && \"Should use SimplifyDemandedBits if you don't know whether Op\" \" is a target node!\"" , "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 2646, __PRETTY_FUNCTION__)) | |||
2644 | Op.getOpcode() == ISD::INTRINSIC_VOID) &&(((Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && "Should use SimplifyDemandedBits if you don't know whether Op" " is a target node!") ? static_cast<void> (0) : __assert_fail ("(Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && \"Should use SimplifyDemandedBits if you don't know whether Op\" \" is a target node!\"" , "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 2646, __PRETTY_FUNCTION__)) | |||
2645 | "Should use SimplifyDemandedBits if you don't know whether Op"(((Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && "Should use SimplifyDemandedBits if you don't know whether Op" " is a target node!") ? static_cast<void> (0) : __assert_fail ("(Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && \"Should use SimplifyDemandedBits if you don't know whether Op\" \" is a target node!\"" , "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 2646, __PRETTY_FUNCTION__)) | |||
2646 | " is a target node!")(((Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && "Should use SimplifyDemandedBits if you don't know whether Op" " is a target node!") ? static_cast<void> (0) : __assert_fail ("(Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && \"Should use SimplifyDemandedBits if you don't know whether Op\" \" is a target node!\"" , "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 2646, __PRETTY_FUNCTION__)); | |||
2647 | computeKnownBitsForTargetNode(Op, Known, DemandedElts, TLO.DAG, Depth); | |||
2648 | return false; | |||
2649 | } | |||
2650 | ||||
2651 | SDValue TargetLowering::SimplifyMultipleUseDemandedBitsForTargetNode( | |||
2652 | SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts, | |||
2653 | SelectionDAG &DAG, unsigned Depth) const { | |||
2654 | assert((((Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && "Should use SimplifyMultipleUseDemandedBits if you don't know whether Op" " is a target node!") ? static_cast<void> (0) : __assert_fail ("(Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && \"Should use SimplifyMultipleUseDemandedBits if you don't know whether Op\" \" is a target node!\"" , "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 2660, __PRETTY_FUNCTION__)) | |||
2655 | (Op.getOpcode() >= ISD::BUILTIN_OP_END ||(((Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && "Should use SimplifyMultipleUseDemandedBits if you don't know whether Op" " is a target node!") ? static_cast<void> (0) : __assert_fail ("(Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && \"Should use SimplifyMultipleUseDemandedBits if you don't know whether Op\" \" is a target node!\"" , "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 2660, __PRETTY_FUNCTION__)) | |||
2656 | Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||(((Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && "Should use SimplifyMultipleUseDemandedBits if you don't know whether Op" " is a target node!") ? static_cast<void> (0) : __assert_fail ("(Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && \"Should use SimplifyMultipleUseDemandedBits if you don't know whether Op\" \" is a target node!\"" , "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 2660, __PRETTY_FUNCTION__)) | |||
2657 | Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||(((Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && "Should use SimplifyMultipleUseDemandedBits if you don't know whether Op" " is a target node!") ? static_cast<void> (0) : __assert_fail ("(Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && \"Should use SimplifyMultipleUseDemandedBits if you don't know whether Op\" \" is a target node!\"" , "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 2660, __PRETTY_FUNCTION__)) | |||
2658 | Op.getOpcode() == ISD::INTRINSIC_VOID) &&(((Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && "Should use SimplifyMultipleUseDemandedBits if you don't know whether Op" " is a target node!") ? static_cast<void> (0) : __assert_fail ("(Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && \"Should use SimplifyMultipleUseDemandedBits if you don't know whether Op\" \" is a target node!\"" , "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 2660, __PRETTY_FUNCTION__)) | |||
2659 | "Should use SimplifyMultipleUseDemandedBits if you don't know whether Op"(((Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && "Should use SimplifyMultipleUseDemandedBits if you don't know whether Op" " is a target node!") ? static_cast<void> (0) : __assert_fail ("(Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && \"Should use SimplifyMultipleUseDemandedBits if you don't know whether Op\" \" is a target node!\"" , "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 2660, __PRETTY_FUNCTION__)) | |||
2660 | " is a target node!")(((Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && "Should use SimplifyMultipleUseDemandedBits if you don't know whether Op" " is a target node!") ? static_cast<void> (0) : __assert_fail ("(Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && \"Should use SimplifyMultipleUseDemandedBits if you don't know whether Op\" \" is a target node!\"" , "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 2660, __PRETTY_FUNCTION__)); | |||
2661 | return SDValue(); | |||
2662 | } | |||
2663 | ||||
2664 | SDValue | |||
2665 | TargetLowering::buildLegalVectorShuffle(EVT VT, const SDLoc &DL, SDValue N0, | |||
2666 | SDValue N1, MutableArrayRef<int> Mask, | |||
2667 | SelectionDAG &DAG) const { | |||
2668 | bool LegalMask = isShuffleMaskLegal(Mask, VT); | |||
2669 | if (!LegalMask) { | |||
2670 | std::swap(N0, N1); | |||
2671 | ShuffleVectorSDNode::commuteMask(Mask); | |||
2672 | LegalMask = isShuffleMaskLegal(Mask, VT); | |||
2673 | } | |||
2674 | ||||
2675 | if (!LegalMask) | |||
2676 | return SDValue(); | |||
2677 | ||||
2678 | return DAG.getVectorShuffle(VT, DL, N0, N1, Mask); | |||
2679 | } | |||
2680 | ||||
2681 | const Constant *TargetLowering::getTargetConstantFromLoad(LoadSDNode*) const { | |||
2682 | return nullptr; | |||
2683 | } | |||
2684 | ||||
2685 | bool TargetLowering::isKnownNeverNaNForTargetNode(SDValue Op, | |||
2686 | const SelectionDAG &DAG, | |||
2687 | bool SNaN, | |||
2688 | unsigned Depth) const { | |||
2689 | assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||(((Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && "Should use isKnownNeverNaN if you don't know whether Op" " is a target node!") ? static_cast<void> (0) : __assert_fail ("(Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && \"Should use isKnownNeverNaN if you don't know whether Op\" \" is a target node!\"" , "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 2694, __PRETTY_FUNCTION__)) | |||
2690 | Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||(((Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && "Should use isKnownNeverNaN if you don't know whether Op" " is a target node!") ? static_cast<void> (0) : __assert_fail ("(Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && \"Should use isKnownNeverNaN if you don't know whether Op\" \" is a target node!\"" , "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 2694, __PRETTY_FUNCTION__)) | |||
2691 | Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||(((Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && "Should use isKnownNeverNaN if you don't know whether Op" " is a target node!") ? static_cast<void> (0) : __assert_fail ("(Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && \"Should use isKnownNeverNaN if you don't know whether Op\" \" is a target node!\"" , "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 2694, __PRETTY_FUNCTION__)) | |||
2692 | Op.getOpcode() == ISD::INTRINSIC_VOID) &&(((Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && "Should use isKnownNeverNaN if you don't know whether Op" " is a target node!") ? static_cast<void> (0) : __assert_fail ("(Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && \"Should use isKnownNeverNaN if you don't know whether Op\" \" is a target node!\"" , "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 2694, __PRETTY_FUNCTION__)) | |||
2693 | "Should use isKnownNeverNaN if you don't know whether Op"(((Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && "Should use isKnownNeverNaN if you don't know whether Op" " is a target node!") ? static_cast<void> (0) : __assert_fail ("(Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && \"Should use isKnownNeverNaN if you don't know whether Op\" \" is a target node!\"" , "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 2694, __PRETTY_FUNCTION__)) | |||
2694 | " is a target node!")(((Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && "Should use isKnownNeverNaN if you don't know whether Op" " is a target node!") ? static_cast<void> (0) : __assert_fail ("(Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || Op.getOpcode() == ISD::INTRINSIC_VOID) && \"Should use isKnownNeverNaN if you don't know whether Op\" \" is a target node!\"" , "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 2694, __PRETTY_FUNCTION__)); | |||
2695 | return false; | |||
2696 | } | |||
2697 | ||||
2698 | // FIXME: Ideally, this would use ISD::isConstantSplatVector(), but that must | |||
2699 | // work with truncating build vectors and vectors with elements of less than | |||
2700 | // 8 bits. | |||
2701 | bool TargetLowering::isConstTrueVal(const SDNode *N) const { | |||
2702 | if (!N) | |||
2703 | return false; | |||
2704 | ||||
2705 | APInt CVal; | |||
2706 | if (auto *CN = dyn_cast<ConstantSDNode>(N)) { | |||
2707 | CVal = CN->getAPIntValue(); | |||
2708 | } else if (auto *BV = dyn_cast<BuildVectorSDNode>(N)) { | |||
2709 | auto *CN = BV->getConstantSplatNode(); | |||
2710 | if (!CN) | |||
2711 | return false; | |||
2712 | ||||
2713 | // If this is a truncating build vector, truncate the splat value. | |||
2714 | // Otherwise, we may fail to match the expected values below. | |||
2715 | unsigned BVEltWidth = BV->getValueType(0).getScalarSizeInBits(); | |||
2716 | CVal = CN->getAPIntValue(); | |||
2717 | if (BVEltWidth < CVal.getBitWidth()) | |||
2718 | CVal = CVal.trunc(BVEltWidth); | |||
2719 | } else { | |||
2720 | return false; | |||
2721 | } | |||
2722 | ||||
2723 | switch (getBooleanContents(N->getValueType(0))) { | |||
2724 | case UndefinedBooleanContent: | |||
2725 | return CVal[0]; | |||
2726 | case ZeroOrOneBooleanContent: | |||
2727 | return CVal.isOneValue(); | |||
2728 | case ZeroOrNegativeOneBooleanContent: | |||
2729 | return CVal.isAllOnesValue(); | |||
2730 | } | |||
2731 | ||||
2732 | llvm_unreachable("Invalid boolean contents")::llvm::llvm_unreachable_internal("Invalid boolean contents", "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 2732); | |||
2733 | } | |||
2734 | ||||
2735 | bool TargetLowering::isConstFalseVal(const SDNode *N) const { | |||
2736 | if (!N) | |||
2737 | return false; | |||
2738 | ||||
2739 | const ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N); | |||
2740 | if (!CN) { | |||
2741 | const BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(N); | |||
2742 | if (!BV) | |||
2743 | return false; | |||
2744 | ||||
2745 | // Only interested in constant splats, we don't care about undef | |||
2746 | // elements in identifying boolean constants and getConstantSplatNode | |||
2747 | // returns NULL if all ops are undef; | |||
2748 | CN = BV->getConstantSplatNode(); | |||
2749 | if (!CN) | |||
2750 | return false; | |||
2751 | } | |||
2752 | ||||
2753 | if (getBooleanContents(N->getValueType(0)) == UndefinedBooleanContent) | |||
2754 | return !CN->getAPIntValue()[0]; | |||
2755 | ||||
2756 | return CN->isNullValue(); | |||
2757 | } | |||
2758 | ||||
2759 | bool TargetLowering::isExtendedTrueVal(const ConstantSDNode *N, EVT VT, | |||
2760 | bool SExt) const { | |||
2761 | if (VT == MVT::i1) | |||
2762 | return N->isOne(); | |||
2763 | ||||
2764 | TargetLowering::BooleanContent Cnt = getBooleanContents(VT); | |||
2765 | switch (Cnt) { | |||
2766 | case TargetLowering::ZeroOrOneBooleanContent: | |||
2767 | // An extended value of 1 is always true, unless its original type is i1, | |||
2768 | // in which case it will be sign extended to -1. | |||
2769 | return (N->isOne() && !SExt) || (SExt && (N->getValueType(0) != MVT::i1)); | |||
2770 | case TargetLowering::UndefinedBooleanContent: | |||
2771 | case TargetLowering::ZeroOrNegativeOneBooleanContent: | |||
2772 | return N->isAllOnesValue() && SExt; | |||
2773 | } | |||
2774 | llvm_unreachable("Unexpected enumeration.")::llvm::llvm_unreachable_internal("Unexpected enumeration.", "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 2774); | |||
2775 | } | |||
2776 | ||||
2777 | /// This helper function of SimplifySetCC tries to optimize the comparison when | |||
2778 | /// either operand of the SetCC node is a bitwise-and instruction. | |||
2779 | SDValue TargetLowering::foldSetCCWithAnd(EVT VT, SDValue N0, SDValue N1, | |||
2780 | ISD::CondCode Cond, const SDLoc &DL, | |||
2781 | DAGCombinerInfo &DCI) const { | |||
2782 | // Match these patterns in any of their permutations: | |||
2783 | // (X & Y) == Y | |||
2784 | // (X & Y) != Y | |||
2785 | if (N1.getOpcode() == ISD::AND && N0.getOpcode() != ISD::AND) | |||
2786 | std::swap(N0, N1); | |||
2787 | ||||
2788 | EVT OpVT = N0.getValueType(); | |||
2789 | if (N0.getOpcode() != ISD::AND || !OpVT.isInteger() || | |||
2790 | (Cond != ISD::SETEQ && Cond != ISD::SETNE)) | |||
2791 | return SDValue(); | |||
2792 | ||||
2793 | SDValue X, Y; | |||
2794 | if (N0.getOperand(0) == N1) { | |||
2795 | X = N0.getOperand(1); | |||
2796 | Y = N0.getOperand(0); | |||
2797 | } else if (N0.getOperand(1) == N1) { | |||
2798 | X = N0.getOperand(0); | |||
2799 | Y = N0.getOperand(1); | |||
2800 | } else { | |||
2801 | return SDValue(); | |||
2802 | } | |||
2803 | ||||
2804 | SelectionDAG &DAG = DCI.DAG; | |||
2805 | SDValue Zero = DAG.getConstant(0, DL, OpVT); | |||
2806 | if (DAG.isKnownToBeAPowerOfTwo(Y)) { | |||
2807 | // Simplify X & Y == Y to X & Y != 0 if Y has exactly one bit set. | |||
2808 | // Note that where Y is variable and is known to have at most one bit set | |||
2809 | // (for example, if it is Z & 1) we cannot do this; the expressions are not | |||
2810 | // equivalent when Y == 0. | |||
2811 | Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true); | |||
2812 | if (DCI.isBeforeLegalizeOps() || | |||
2813 | isCondCodeLegal(Cond, N0.getSimpleValueType())) | |||
2814 | return DAG.getSetCC(DL, VT, N0, Zero, Cond); | |||
2815 | } else if (N0.hasOneUse() && hasAndNotCompare(Y)) { | |||
2816 | // If the target supports an 'and-not' or 'and-complement' logic operation, | |||
2817 | // try to use that to make a comparison operation more efficient. | |||
2818 | // But don't do this transform if the mask is a single bit because there are | |||
2819 | // more efficient ways to deal with that case (for example, 'bt' on x86 or | |||
2820 | // 'rlwinm' on PPC). | |||
2821 | ||||
2822 | // Bail out if the compare operand that we want to turn into a zero is | |||
2823 | // already a zero (otherwise, infinite loop). | |||
2824 | auto *YConst = dyn_cast<ConstantSDNode>(Y); | |||
2825 | if (YConst && YConst->isNullValue()) | |||
2826 | return SDValue(); | |||
2827 | ||||
2828 | // Transform this into: ~X & Y == 0. | |||
2829 | SDValue NotX = DAG.getNOT(SDLoc(X), X, OpVT); | |||
2830 | SDValue NewAnd = DAG.getNode(ISD::AND, SDLoc(N0), OpVT, NotX, Y); | |||
2831 | return DAG.getSetCC(DL, VT, NewAnd, Zero, Cond); | |||
2832 | } | |||
2833 | ||||
2834 | return SDValue(); | |||
2835 | } | |||
2836 | ||||
2837 | /// There are multiple IR patterns that could be checking whether certain | |||
2838 | /// truncation of a signed number would be lossy or not. The pattern which is | |||
2839 | /// best at IR level, may not lower optimally. Thus, we want to unfold it. | |||
2840 | /// We are looking for the following pattern: (KeptBits is a constant) | |||
2841 | /// (add %x, (1 << (KeptBits-1))) srccond (1 << KeptBits) | |||
2842 | /// KeptBits won't be bitwidth(x), that will be constant-folded to true/false. | |||
2843 | /// KeptBits also can't be 1, that would have been folded to %x dstcond 0 | |||
2844 | /// We will unfold it into the natural trunc+sext pattern: | |||
2845 | /// ((%x << C) a>> C) dstcond %x | |||
2846 | /// Where C = bitwidth(x) - KeptBits and C u< bitwidth(x) | |||
2847 | SDValue TargetLowering::optimizeSetCCOfSignedTruncationCheck( | |||
2848 | EVT SCCVT, SDValue N0, SDValue N1, ISD::CondCode Cond, DAGCombinerInfo &DCI, | |||
2849 | const SDLoc &DL) const { | |||
2850 | // We must be comparing with a constant. | |||
2851 | ConstantSDNode *C1; | |||
2852 | if (!(C1 = dyn_cast<ConstantSDNode>(N1))) | |||
2853 | return SDValue(); | |||
2854 | ||||
2855 | // N0 should be: add %x, (1 << (KeptBits-1)) | |||
2856 | if (N0->getOpcode() != ISD::ADD) | |||
2857 | return SDValue(); | |||
2858 | ||||
2859 | // And we must be 'add'ing a constant. | |||
2860 | ConstantSDNode *C01; | |||
2861 | if (!(C01 = dyn_cast<ConstantSDNode>(N0->getOperand(1)))) | |||
2862 | return SDValue(); | |||
2863 | ||||
2864 | SDValue X = N0->getOperand(0); | |||
2865 | EVT XVT = X.getValueType(); | |||
2866 | ||||
2867 | // Validate constants ... | |||
2868 | ||||
2869 | APInt I1 = C1->getAPIntValue(); | |||
2870 | ||||
2871 | ISD::CondCode NewCond; | |||
2872 | if (Cond == ISD::CondCode::SETULT) { | |||
2873 | NewCond = ISD::CondCode::SETEQ; | |||
2874 | } else if (Cond == ISD::CondCode::SETULE) { | |||
2875 | NewCond = ISD::CondCode::SETEQ; | |||
2876 | // But need to 'canonicalize' the constant. | |||
2877 | I1 += 1; | |||
2878 | } else if (Cond == ISD::CondCode::SETUGT) { | |||
2879 | NewCond = ISD::CondCode::SETNE; | |||
2880 | // But need to 'canonicalize' the constant. | |||
2881 | I1 += 1; | |||
2882 | } else if (Cond == ISD::CondCode::SETUGE) { | |||
2883 | NewCond = ISD::CondCode::SETNE; | |||
2884 | } else | |||
2885 | return SDValue(); | |||
2886 | ||||
2887 | APInt I01 = C01->getAPIntValue(); | |||
2888 | ||||
2889 | auto checkConstants = [&I1, &I01]() -> bool { | |||
2890 | // Both of them must be power-of-two, and the constant from setcc is bigger. | |||
2891 | return I1.ugt(I01) && I1.isPowerOf2() && I01.isPowerOf2(); | |||
2892 | }; | |||
2893 | ||||
2894 | if (checkConstants()) { | |||
2895 | // Great, e.g. got icmp ult i16 (add i16 %x, 128), 256 | |||
2896 | } else { | |||
2897 | // What if we invert constants? (and the target predicate) | |||
2898 | I1.negate(); | |||
2899 | I01.negate(); | |||
2900 | NewCond = getSetCCInverse(NewCond, /*isInteger=*/true); | |||
2901 | if (!checkConstants()) | |||
2902 | return SDValue(); | |||
2903 | // Great, e.g. got icmp uge i16 (add i16 %x, -128), -256 | |||
2904 | } | |||
2905 | ||||
2906 | // They are power-of-two, so which bit is set? | |||
2907 | const unsigned KeptBits = I1.logBase2(); | |||
2908 | const unsigned KeptBitsMinusOne = I01.logBase2(); | |||
2909 | ||||
2910 | // Magic! | |||
2911 | if (KeptBits != (KeptBitsMinusOne + 1)) | |||
2912 | return SDValue(); | |||
2913 | assert(KeptBits > 0 && KeptBits < XVT.getSizeInBits() && "unreachable")((KeptBits > 0 && KeptBits < XVT.getSizeInBits( ) && "unreachable") ? static_cast<void> (0) : __assert_fail ("KeptBits > 0 && KeptBits < XVT.getSizeInBits() && \"unreachable\"" , "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 2913, __PRETTY_FUNCTION__)); | |||
2914 | ||||
2915 | // We don't want to do this in every single case. | |||
2916 | SelectionDAG &DAG = DCI.DAG; | |||
2917 | if (!DAG.getTargetLoweringInfo().shouldTransformSignedTruncationCheck( | |||
2918 | XVT, KeptBits)) | |||
2919 | return SDValue(); | |||
2920 | ||||
2921 | const unsigned MaskedBits = XVT.getSizeInBits() - KeptBits; | |||
2922 | assert(MaskedBits > 0 && MaskedBits < XVT.getSizeInBits() && "unreachable")((MaskedBits > 0 && MaskedBits < XVT.getSizeInBits () && "unreachable") ? static_cast<void> (0) : __assert_fail ("MaskedBits > 0 && MaskedBits < XVT.getSizeInBits() && \"unreachable\"" , "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 2922, __PRETTY_FUNCTION__)); | |||
2923 | ||||
2924 | // Unfold into: ((%x << C) a>> C) cond %x | |||
2925 | // Where 'cond' will be either 'eq' or 'ne'. | |||
2926 | SDValue ShiftAmt = DAG.getConstant(MaskedBits, DL, XVT); | |||
2927 | SDValue T0 = DAG.getNode(ISD::SHL, DL, XVT, X, ShiftAmt); | |||
2928 | SDValue T1 = DAG.getNode(ISD::SRA, DL, XVT, T0, ShiftAmt); | |||
2929 | SDValue T2 = DAG.getSetCC(DL, SCCVT, T1, X, NewCond); | |||
2930 | ||||
2931 | return T2; | |||
2932 | } | |||
2933 | ||||
2934 | // (X & (C l>>/<< Y)) ==/!= 0 --> ((X <</l>> Y) & C) ==/!= 0 | |||
2935 | SDValue TargetLowering::optimizeSetCCByHoistingAndByConstFromLogicalShift( | |||
2936 | EVT SCCVT, SDValue N0, SDValue N1C, ISD::CondCode Cond, | |||
2937 | DAGCombinerInfo &DCI, const SDLoc &DL) const { | |||
2938 | assert(isConstOrConstSplat(N1C) &&((isConstOrConstSplat(N1C) && isConstOrConstSplat(N1C )->getAPIntValue().isNullValue() && "Should be a comparison with 0." ) ? static_cast<void> (0) : __assert_fail ("isConstOrConstSplat(N1C) && isConstOrConstSplat(N1C)->getAPIntValue().isNullValue() && \"Should be a comparison with 0.\"" , "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 2940, __PRETTY_FUNCTION__)) | |||
2939 | isConstOrConstSplat(N1C)->getAPIntValue().isNullValue() &&((isConstOrConstSplat(N1C) && isConstOrConstSplat(N1C )->getAPIntValue().isNullValue() && "Should be a comparison with 0." ) ? static_cast<void> (0) : __assert_fail ("isConstOrConstSplat(N1C) && isConstOrConstSplat(N1C)->getAPIntValue().isNullValue() && \"Should be a comparison with 0.\"" , "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 2940, __PRETTY_FUNCTION__)) | |||
2940 | "Should be a comparison with 0.")((isConstOrConstSplat(N1C) && isConstOrConstSplat(N1C )->getAPIntValue().isNullValue() && "Should be a comparison with 0." ) ? static_cast<void> (0) : __assert_fail ("isConstOrConstSplat(N1C) && isConstOrConstSplat(N1C)->getAPIntValue().isNullValue() && \"Should be a comparison with 0.\"" , "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 2940, __PRETTY_FUNCTION__)); | |||
2941 | assert((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&(((Cond == ISD::SETEQ || Cond == ISD::SETNE) && "Valid only for [in]equality comparisons." ) ? static_cast<void> (0) : __assert_fail ("(Cond == ISD::SETEQ || Cond == ISD::SETNE) && \"Valid only for [in]equality comparisons.\"" , "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 2942, __PRETTY_FUNCTION__)) | |||
2942 | "Valid only for [in]equality comparisons.")(((Cond == ISD::SETEQ || Cond == ISD::SETNE) && "Valid only for [in]equality comparisons." ) ? static_cast<void> (0) : __assert_fail ("(Cond == ISD::SETEQ || Cond == ISD::SETNE) && \"Valid only for [in]equality comparisons.\"" , "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 2942, __PRETTY_FUNCTION__)); | |||
2943 | ||||
2944 | unsigned NewShiftOpcode; | |||
2945 | SDValue X, C, Y; | |||
2946 | ||||
2947 | SelectionDAG &DAG = DCI.DAG; | |||
2948 | const TargetLowering &TLI = DAG.getTargetLoweringInfo(); | |||
2949 | ||||
2950 | // Look for '(C l>>/<< Y)'. | |||
2951 | auto Match = [&NewShiftOpcode, &X, &C, &Y, &TLI, &DAG](SDValue V) { | |||
2952 | // The shift should be one-use. | |||
2953 | if (!V.hasOneUse()) | |||
2954 | return false; | |||
2955 | unsigned OldShiftOpcode = V.getOpcode(); | |||
2956 | switch (OldShiftOpcode) { | |||
2957 | case ISD::SHL: | |||
2958 | NewShiftOpcode = ISD::SRL; | |||
2959 | break; | |||
2960 | case ISD::SRL: | |||
2961 | NewShiftOpcode = ISD::SHL; | |||
2962 | break; | |||
2963 | default: | |||
2964 | return false; // must be a logical shift. | |||
2965 | } | |||
2966 | // We should be shifting a constant. | |||
2967 | // FIXME: best to use isConstantOrConstantVector(). | |||
2968 | C = V.getOperand(0); | |||
2969 | ConstantSDNode *CC = | |||
2970 | isConstOrConstSplat(C, /*AllowUndefs=*/true, /*AllowTruncation=*/true); | |||
2971 | if (!CC) | |||
2972 | return false; | |||
2973 | Y = V.getOperand(1); | |||
2974 | ||||
2975 | ConstantSDNode *XC = | |||
2976 | isConstOrConstSplat(X, /*AllowUndefs=*/true, /*AllowTruncation=*/true); | |||
2977 | return TLI.shouldProduceAndByConstByHoistingConstFromShiftsLHSOfAnd( | |||
2978 | X, XC, CC, Y, OldShiftOpcode, NewShiftOpcode, DAG); | |||
2979 | }; | |||
2980 | ||||
2981 | // LHS of comparison should be an one-use 'and'. | |||
2982 | if (N0.getOpcode() != ISD::AND || !N0.hasOneUse()) | |||
2983 | return SDValue(); | |||
2984 | ||||
2985 | X = N0.getOperand(0); | |||
2986 | SDValue Mask = N0.getOperand(1); | |||
2987 | ||||
2988 | // 'and' is commutative! | |||
2989 | if (!Match(Mask)) { | |||
2990 | std::swap(X, Mask); | |||
2991 | if (!Match(Mask)) | |||
2992 | return SDValue(); | |||
2993 | } | |||
2994 | ||||
2995 | EVT VT = X.getValueType(); | |||
2996 | ||||
2997 | // Produce: | |||
2998 | // ((X 'OppositeShiftOpcode' Y) & C) Cond 0 | |||
2999 | SDValue T0 = DAG.getNode(NewShiftOpcode, DL, VT, X, Y); | |||
3000 | SDValue T1 = DAG.getNode(ISD::AND, DL, VT, T0, C); | |||
3001 | SDValue T2 = DAG.getSetCC(DL, SCCVT, T1, N1C, Cond); | |||
3002 | return T2; | |||
3003 | } | |||
3004 | ||||
3005 | /// Try to fold an equality comparison with a {add/sub/xor} binary operation as | |||
3006 | /// the 1st operand (N0). Callers are expected to swap the N0/N1 parameters to | |||
3007 | /// handle the commuted versions of these patterns. | |||
3008 | SDValue TargetLowering::foldSetCCWithBinOp(EVT VT, SDValue N0, SDValue N1, | |||
3009 | ISD::CondCode Cond, const SDLoc &DL, | |||
3010 | DAGCombinerInfo &DCI) const { | |||
3011 | unsigned BOpcode = N0.getOpcode(); | |||
3012 | assert((BOpcode == ISD::ADD || BOpcode == ISD::SUB || BOpcode == ISD::XOR) &&(((BOpcode == ISD::ADD || BOpcode == ISD::SUB || BOpcode == ISD ::XOR) && "Unexpected binop") ? static_cast<void> (0) : __assert_fail ("(BOpcode == ISD::ADD || BOpcode == ISD::SUB || BOpcode == ISD::XOR) && \"Unexpected binop\"" , "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 3013, __PRETTY_FUNCTION__)) | |||
3013 | "Unexpected binop")(((BOpcode == ISD::ADD || BOpcode == ISD::SUB || BOpcode == ISD ::XOR) && "Unexpected binop") ? static_cast<void> (0) : __assert_fail ("(BOpcode == ISD::ADD || BOpcode == ISD::SUB || BOpcode == ISD::XOR) && \"Unexpected binop\"" , "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 3013, __PRETTY_FUNCTION__)); | |||
3014 | assert((Cond == ISD::SETEQ || Cond == ISD::SETNE) && "Unexpected condcode")(((Cond == ISD::SETEQ || Cond == ISD::SETNE) && "Unexpected condcode" ) ? static_cast<void> (0) : __assert_fail ("(Cond == ISD::SETEQ || Cond == ISD::SETNE) && \"Unexpected condcode\"" , "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 3014, __PRETTY_FUNCTION__)); | |||
3015 | ||||
3016 | // (X + Y) == X --> Y == 0 | |||
3017 | // (X - Y) == X --> Y == 0 | |||
3018 | // (X ^ Y) == X --> Y == 0 | |||
3019 | SelectionDAG &DAG = DCI.DAG; | |||
3020 | EVT OpVT = N0.getValueType(); | |||
3021 | SDValue X = N0.getOperand(0); | |||
3022 | SDValue Y = N0.getOperand(1); | |||
3023 | if (X == N1) | |||
3024 | return DAG.getSetCC(DL, VT, Y, DAG.getConstant(0, DL, OpVT), Cond); | |||
3025 | ||||
3026 | if (Y != N1) | |||
3027 | return SDValue(); | |||
3028 | ||||
3029 | // (X + Y) == Y --> X == 0 | |||
3030 | // (X ^ Y) == Y --> X == 0 | |||
3031 | if (BOpcode == ISD::ADD || BOpcode == ISD::XOR) | |||
3032 | return DAG.getSetCC(DL, VT, X, DAG.getConstant(0, DL, OpVT), Cond); | |||
3033 | ||||
3034 | // The shift would not be valid if the operands are boolean (i1). | |||
3035 | if (!N0.hasOneUse() || OpVT.getScalarSizeInBits() == 1) | |||
3036 | return SDValue(); | |||
3037 | ||||
3038 | // (X - Y) == Y --> X == Y << 1 | |||
3039 | EVT ShiftVT = getShiftAmountTy(OpVT, DAG.getDataLayout(), | |||
3040 | !DCI.isBeforeLegalize()); | |||
3041 | SDValue One = DAG.getConstant(1, DL, ShiftVT); | |||
3042 | SDValue YShl1 = DAG.getNode(ISD::SHL, DL, N1.getValueType(), Y, One); | |||
3043 | if (!DCI.isCalledByLegalizer()) | |||
3044 | DCI.AddToWorklist(YShl1.getNode()); | |||
3045 | return DAG.getSetCC(DL, VT, X, YShl1, Cond); | |||
3046 | } | |||
3047 | ||||
3048 | /// Try to simplify a setcc built with the specified operands and cc. If it is | |||
3049 | /// unable to simplify it, return a null SDValue. | |||
3050 | SDValue TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1, | |||
3051 | ISD::CondCode Cond, bool foldBooleans, | |||
3052 | DAGCombinerInfo &DCI, | |||
3053 | const SDLoc &dl) const { | |||
3054 | SelectionDAG &DAG = DCI.DAG; | |||
3055 | const DataLayout &Layout = DAG.getDataLayout(); | |||
3056 | EVT OpVT = N0.getValueType(); | |||
3057 | ||||
3058 | // Constant fold or commute setcc. | |||
3059 | if (SDValue Fold = DAG.FoldSetCC(VT, N0, N1, Cond, dl)) | |||
3060 | return Fold; | |||
3061 | ||||
3062 | // Ensure that the constant occurs on the RHS and fold constant comparisons. | |||
3063 | // TODO: Handle non-splat vector constants. All undef causes trouble. | |||
3064 | ISD::CondCode SwappedCC = ISD::getSetCCSwappedOperands(Cond); | |||
3065 | if (isConstOrConstSplat(N0) && | |||
3066 | (DCI.isBeforeLegalizeOps() || | |||
3067 | isCondCodeLegal(SwappedCC, N0.getSimpleValueType()))) | |||
3068 | return DAG.getSetCC(dl, VT, N1, N0, SwappedCC); | |||
3069 | ||||
3070 | // If we have a subtract with the same 2 non-constant operands as this setcc | |||
3071 | // -- but in reverse order -- then try to commute the operands of this setcc | |||
3072 | // to match. A matching pair of setcc (cmp) and sub may be combined into 1 | |||
3073 | // instruction on some targets. | |||
3074 | if (!isConstOrConstSplat(N0) && !isConstOrConstSplat(N1) && | |||
3075 | (DCI.isBeforeLegalizeOps() || | |||
3076 | isCondCodeLegal(SwappedCC, N0.getSimpleValueType())) && | |||
3077 | DAG.getNodeIfExists(ISD::SUB, DAG.getVTList(OpVT), { N1, N0 } ) && | |||
3078 | !DAG.getNodeIfExists(ISD::SUB, DAG.getVTList(OpVT), { N0, N1 } )) | |||
3079 | return DAG.getSetCC(dl, VT, N1, N0, SwappedCC); | |||
3080 | ||||
3081 | if (auto *N1C = dyn_cast<ConstantSDNode>(N1.getNode())) { | |||
3082 | const APInt &C1 = N1C->getAPIntValue(); | |||
3083 | ||||
3084 | // If the LHS is '(srl (ctlz x), 5)', the RHS is 0/1, and this is an | |||
3085 | // equality comparison, then we're just comparing whether X itself is | |||
3086 | // zero. | |||
3087 | if (N0.getOpcode() == ISD::SRL && (C1.isNullValue() || C1.isOneValue()) && | |||
3088 | N0.getOperand(0).getOpcode() == ISD::CTLZ && | |||
3089 | N0.getOperand(1).getOpcode() == ISD::Constant) { | |||
3090 | const APInt &ShAmt = N0.getConstantOperandAPInt(1); | |||
3091 | if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && | |||
3092 | ShAmt == Log2_32(N0.getValueSizeInBits())) { | |||
3093 | if ((C1 == 0) == (Cond == ISD::SETEQ)) { | |||
3094 | // (srl (ctlz x), 5) == 0 -> X != 0 | |||
3095 | // (srl (ctlz x), 5) != 1 -> X != 0 | |||
3096 | Cond = ISD::SETNE; | |||
3097 | } else { | |||
3098 | // (srl (ctlz x), 5) != 0 -> X == 0 | |||
3099 | // (srl (ctlz x), 5) == 1 -> X == 0 | |||
3100 | Cond = ISD::SETEQ; | |||
3101 | } | |||
3102 | SDValue Zero = DAG.getConstant(0, dl, N0.getValueType()); | |||
3103 | return DAG.getSetCC(dl, VT, N0.getOperand(0).getOperand(0), | |||
3104 | Zero, Cond); | |||
3105 | } | |||
3106 | } | |||
3107 | ||||
3108 | SDValue CTPOP = N0; | |||
3109 | // Look through truncs that don't change the value of a ctpop. | |||
3110 | if (N0.hasOneUse() && N0.getOpcode() == ISD::TRUNCATE) | |||
3111 | CTPOP = N0.getOperand(0); | |||
3112 | ||||
3113 | if (CTPOP.hasOneUse() && CTPOP.getOpcode() == ISD::CTPOP && | |||
3114 | (N0 == CTPOP || | |||
3115 | N0.getValueSizeInBits() > Log2_32_Ceil(CTPOP.getValueSizeInBits()))) { | |||
3116 | EVT CTVT = CTPOP.getValueType(); | |||
3117 | SDValue CTOp = CTPOP.getOperand(0); | |||
3118 | ||||
3119 | // (ctpop x) u< 2 -> (x & x-1) == 0 | |||
3120 | // (ctpop x) u> 1 -> (x & x-1) != 0 | |||
3121 | if ((Cond == ISD::SETULT && C1 == 2) || (Cond == ISD::SETUGT && C1 == 1)){ | |||
3122 | SDValue NegOne = DAG.getAllOnesConstant(dl, CTVT); | |||
3123 | SDValue Add = DAG.getNode(ISD::ADD, dl, CTVT, CTOp, NegOne); | |||
3124 | SDValue And = DAG.getNode(ISD::AND, dl, CTVT, CTOp, Add); | |||
3125 | ISD::CondCode CC = Cond == ISD::SETULT ? ISD::SETEQ : ISD::SETNE; | |||
3126 | return DAG.getSetCC(dl, VT, And, DAG.getConstant(0, dl, CTVT), CC); | |||
3127 | } | |||
3128 | ||||
3129 | // If ctpop is not supported, expand a power-of-2 comparison based on it. | |||
3130 | if (C1 == 1 && !isOperationLegalOrCustom(ISD::CTPOP, CTVT) && | |||
3131 | (Cond == ISD::SETEQ || Cond == ISD::SETNE)) { | |||
3132 | // (ctpop x) == 1 --> (x != 0) && ((x & x-1) == 0) | |||
3133 | // (ctpop x) != 1 --> (x == 0) || ((x & x-1) != 0) | |||
3134 | SDValue Zero = DAG.getConstant(0, dl, CTVT); | |||
3135 | SDValue NegOne = DAG.getAllOnesConstant(dl, CTVT); | |||
3136 | ISD::CondCode InvCond = ISD::getSetCCInverse(Cond, true); | |||
3137 | SDValue Add = DAG.getNode(ISD::ADD, dl, CTVT, CTOp, NegOne); | |||
3138 | SDValue And = DAG.getNode(ISD::AND, dl, CTVT, CTOp, Add); | |||
3139 | SDValue LHS = DAG.getSetCC(dl, VT, CTOp, Zero, InvCond); | |||
3140 | SDValue RHS = DAG.getSetCC(dl, VT, And, Zero, Cond); | |||
3141 | unsigned LogicOpcode = Cond == ISD::SETEQ ? ISD::AND : ISD::OR; | |||
3142 | return DAG.getNode(LogicOpcode, dl, VT, LHS, RHS); | |||
3143 | } | |||
3144 | } | |||
3145 | ||||
3146 | // (zext x) == C --> x == (trunc C) | |||
3147 | // (sext x) == C --> x == (trunc C) | |||
3148 | if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && | |||
3149 | DCI.isBeforeLegalize() && N0->hasOneUse()) { | |||
3150 | unsigned MinBits = N0.getValueSizeInBits(); | |||
3151 | SDValue PreExt; | |||
3152 | bool Signed = false; | |||
3153 | if (N0->getOpcode() == ISD::ZERO_EXTEND) { | |||
3154 | // ZExt | |||
3155 | MinBits = N0->getOperand(0).getValueSizeInBits(); | |||
3156 | PreExt = N0->getOperand(0); | |||
3157 | } else if (N0->getOpcode() == ISD::AND) { | |||
3158 | // DAGCombine turns costly ZExts into ANDs | |||
3159 | if (auto *C = dyn_cast<ConstantSDNode>(N0->getOperand(1))) | |||
3160 | if ((C->getAPIntValue()+1).isPowerOf2()) { | |||
3161 | MinBits = C->getAPIntValue().countTrailingOnes(); | |||
3162 | PreExt = N0->getOperand(0); | |||
3163 | } | |||
3164 | } else if (N0->getOpcode() == ISD::SIGN_EXTEND) { | |||
3165 | // SExt | |||
3166 | MinBits = N0->getOperand(0).getValueSizeInBits(); | |||
3167 | PreExt = N0->getOperand(0); | |||
3168 | Signed = true; | |||
3169 | } else if (auto *LN0 = dyn_cast<LoadSDNode>(N0)) { | |||
3170 | // ZEXTLOAD / SEXTLOAD | |||
3171 | if (LN0->getExtensionType() == ISD::ZEXTLOAD) { | |||
3172 | MinBits = LN0->getMemoryVT().getSizeInBits(); | |||
3173 | PreExt = N0; | |||
3174 | } else if (LN0->getExtensionType() == ISD::SEXTLOAD) { | |||
3175 | Signed = true; | |||
3176 | MinBits = LN0->getMemoryVT().getSizeInBits(); | |||
3177 | PreExt = N0; | |||
3178 | } | |||
3179 | } | |||
3180 | ||||
3181 | // Figure out how many bits we need to preserve this constant. | |||
3182 | unsigned ReqdBits = Signed ? | |||
3183 | C1.getBitWidth() - C1.getNumSignBits() + 1 : | |||
3184 | C1.getActiveBits(); | |||
3185 | ||||
3186 | // Make sure we're not losing bits from the constant. | |||
3187 | if (MinBits > 0 && | |||
3188 | MinBits < C1.getBitWidth() && | |||
3189 | MinBits >= ReqdBits) { | |||
3190 | EVT MinVT = EVT::getIntegerVT(*DAG.getContext(), MinBits); | |||
3191 | if (isTypeDesirableForOp(ISD::SETCC, MinVT)) { | |||
3192 | // Will get folded away. | |||
3193 | SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, MinVT, PreExt); | |||
3194 | if (MinBits == 1 && C1 == 1) | |||
3195 | // Invert the condition. | |||
3196 | return DAG.getSetCC(dl, VT, Trunc, DAG.getConstant(0, dl, MVT::i1), | |||
3197 | Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ); | |||
3198 | SDValue C = DAG.getConstant(C1.trunc(MinBits), dl, MinVT); | |||
3199 | return DAG.getSetCC(dl, VT, Trunc, C, Cond); | |||
3200 | } | |||
3201 | ||||
3202 | // If truncating the setcc operands is not desirable, we can still | |||
3203 | // simplify the expression in some cases: | |||
3204 | // setcc ([sz]ext (setcc x, y, cc)), 0, setne) -> setcc (x, y, cc) | |||
3205 | // setcc ([sz]ext (setcc x, y, cc)), 0, seteq) -> setcc (x, y, inv(cc)) | |||
3206 | // setcc (zext (setcc x, y, cc)), 1, setne) -> setcc (x, y, inv(cc)) | |||
3207 | // setcc (zext (setcc x, y, cc)), 1, seteq) -> setcc (x, y, cc) | |||
3208 | // setcc (sext (setcc x, y, cc)), -1, setne) -> setcc (x, y, inv(cc)) | |||
3209 | // setcc (sext (setcc x, y, cc)), -1, seteq) -> setcc (x, y, cc) | |||
3210 | SDValue TopSetCC = N0->getOperand(0); | |||
3211 | unsigned N0Opc = N0->getOpcode(); | |||
3212 | bool SExt = (N0Opc == ISD::SIGN_EXTEND); | |||
3213 | if (TopSetCC.getValueType() == MVT::i1 && VT == MVT::i1 && | |||
3214 | TopSetCC.getOpcode() == ISD::SETCC && | |||
3215 | (N0Opc == ISD::ZERO_EXTEND || N0Opc == ISD::SIGN_EXTEND) && | |||
3216 | (isConstFalseVal(N1C) || | |||
3217 | isExtendedTrueVal(N1C, N0->getValueType(0), SExt))) { | |||
3218 | ||||
3219 | bool Inverse = (N1C->isNullValue() && Cond == ISD::SETEQ) || | |||
3220 | (!N1C->isNullValue() && Cond == ISD::SETNE); | |||
3221 | ||||
3222 | if (!Inverse) | |||
3223 | return TopSetCC; | |||
3224 | ||||
3225 | ISD::CondCode InvCond = ISD::getSetCCInverse( | |||
3226 | cast<CondCodeSDNode>(TopSetCC.getOperand(2))->get(), | |||
3227 | TopSetCC.getOperand(0).getValueType().isInteger()); | |||
3228 | return DAG.getSetCC(dl, VT, TopSetCC.getOperand(0), | |||
3229 | TopSetCC.getOperand(1), | |||
3230 | InvCond); | |||
3231 | } | |||
3232 | } | |||
3233 | } | |||
3234 | ||||
3235 | // If the LHS is '(and load, const)', the RHS is 0, the test is for | |||
3236 | // equality or unsigned, and all 1 bits of the const are in the same | |||
3237 | // partial word, see if we can shorten the load. | |||
3238 | if (DCI.isBeforeLegalize() && | |||
3239 | !ISD::isSignedIntSetCC(Cond) && | |||
3240 | N0.getOpcode() == ISD::AND && C1 == 0 && | |||
3241 | N0.getNode()->hasOneUse() && | |||
3242 | isa<LoadSDNode>(N0.getOperand(0)) && | |||
3243 | N0.getOperand(0).getNode()->hasOneUse() && | |||
3244 | isa<ConstantSDNode>(N0.getOperand(1))) { | |||
3245 | LoadSDNode *Lod = cast<LoadSDNode>(N0.getOperand(0)); | |||
3246 | APInt bestMask; | |||
3247 | unsigned bestWidth = 0, bestOffset = 0; | |||
3248 | if (Lod->isSimple() && Lod->isUnindexed()) { | |||
3249 | unsigned origWidth = N0.getValueSizeInBits(); | |||
3250 | unsigned maskWidth = origWidth; | |||
3251 | // We can narrow (e.g.) 16-bit extending loads on 32-bit target to | |||
3252 | // 8 bits, but have to be careful... | |||
3253 | if (Lod->getExtensionType() != ISD::NON_EXTLOAD) | |||
3254 | origWidth = Lod->getMemoryVT().getSizeInBits(); | |||
3255 | const APInt &Mask = N0.getConstantOperandAPInt(1); | |||
3256 | for (unsigned width = origWidth / 2; width>=8; width /= 2) { | |||
3257 | APInt newMask = APInt::getLowBitsSet(maskWidth, width); | |||
3258 | for (unsigned offset=0; offset<origWidth/width; offset++) { | |||
3259 | if (Mask.isSubsetOf(newMask)) { | |||
3260 | if (Layout.isLittleEndian()) | |||
3261 | bestOffset = (uint64_t)offset * (width/8); | |||
3262 | else | |||
3263 | bestOffset = (origWidth/width - offset - 1) * (width/8); | |||
3264 | bestMask = Mask.lshr(offset * (width/8) * 8); | |||
3265 | bestWidth = width; | |||
3266 | break; | |||
3267 | } | |||
3268 | newMask <<= width; | |||
3269 | } | |||
3270 | } | |||
3271 | } | |||
3272 | if (bestWidth) { | |||
3273 | EVT newVT = EVT::getIntegerVT(*DAG.getContext(), bestWidth); | |||
3274 | if (newVT.isRound() && | |||
3275 | shouldReduceLoadWidth(Lod, ISD::NON_EXTLOAD, newVT)) { | |||
3276 | EVT PtrType = Lod->getOperand(1).getValueType(); | |||
3277 | SDValue Ptr = Lod->getBasePtr(); | |||
3278 | if (bestOffset != 0) | |||
3279 | Ptr = DAG.getNode(ISD::ADD, dl, PtrType, Lod->getBasePtr(), | |||
3280 | DAG.getConstant(bestOffset, dl, PtrType)); | |||
3281 | unsigned NewAlign = MinAlign(Lod->getAlignment(), bestOffset); | |||
3282 | SDValue NewLoad = DAG.getLoad( | |||
3283 | newVT, dl, Lod->getChain(), Ptr, | |||
3284 | Lod->getPointerInfo().getWithOffset(bestOffset), NewAlign); | |||
3285 | return DAG.getSetCC(dl, VT, | |||
3286 | DAG.getNode(ISD::AND, dl, newVT, NewLoad, | |||
3287 | DAG.getConstant(bestMask.trunc(bestWidth), | |||
3288 | dl, newVT)), | |||
3289 | DAG.getConstant(0LL, dl, newVT), Cond); | |||
3290 | } | |||
3291 | } | |||
3292 | } | |||
3293 | ||||
3294 | // If the LHS is a ZERO_EXTEND, perform the comparison on the input. | |||
3295 | if (N0.getOpcode() == ISD::ZERO_EXTEND) { | |||
3296 | unsigned InSize = N0.getOperand(0).getValueSizeInBits(); | |||
3297 | ||||
3298 | // If the comparison constant has bits in the upper part, the | |||
3299 | // zero-extended value could never match. | |||
3300 | if (C1.intersects(APInt::getHighBitsSet(C1.getBitWidth(), | |||
3301 | C1.getBitWidth() - InSize))) { | |||
3302 | switch (Cond) { | |||
3303 | case ISD::SETUGT: | |||
3304 | case ISD::SETUGE: | |||
3305 | case ISD::SETEQ: | |||
3306 | return DAG.getConstant(0, dl, VT); | |||
3307 | case ISD::SETULT: | |||
3308 | case ISD::SETULE: | |||
3309 | case ISD::SETNE: | |||
3310 | return DAG.getConstant(1, dl, VT); | |||
3311 | case ISD::SETGT: | |||
3312 | case ISD::SETGE: | |||
3313 | // True if the sign bit of C1 is set. | |||
3314 | return DAG.getConstant(C1.isNegative(), dl, VT); | |||
3315 | case ISD::SETLT: | |||
3316 | case ISD::SETLE: | |||
3317 | // True if the sign bit of C1 isn't set. | |||
3318 | return DAG.getConstant(C1.isNonNegative(), dl, VT); | |||
3319 | default: | |||
3320 | break; | |||
3321 | } | |||
3322 | } | |||
3323 | ||||
3324 | // Otherwise, we can perform the comparison with the low bits. | |||
3325 | switch (Cond) { | |||
3326 | case ISD::SETEQ: | |||
3327 | case ISD::SETNE: | |||
3328 | case ISD::SETUGT: | |||
3329 | case ISD::SETUGE: | |||
3330 | case ISD::SETULT: | |||
3331 | case ISD::SETULE: { | |||
3332 | EVT newVT = N0.getOperand(0).getValueType(); | |||
3333 | if (DCI.isBeforeLegalizeOps() || | |||
3334 | (isOperationLegal(ISD::SETCC, newVT) && | |||
3335 | isCondCodeLegal(Cond, newVT.getSimpleVT()))) { | |||
3336 | EVT NewSetCCVT = getSetCCResultType(Layout, *DAG.getContext(), newVT); | |||
3337 | SDValue NewConst = DAG.getConstant(C1.trunc(InSize), dl, newVT); | |||
3338 | ||||
3339 | SDValue NewSetCC = DAG.getSetCC(dl, NewSetCCVT, N0.getOperand(0), | |||
3340 | NewConst, Cond); | |||
3341 | return DAG.getBoolExtOrTrunc(NewSetCC, dl, VT, N0.getValueType()); | |||
3342 | } | |||
3343 | break; | |||
3344 | } | |||
3345 | default: | |||
3346 | break; // todo, be more careful with signed comparisons | |||
3347 | } | |||
3348 | } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && | |||
3349 | (Cond == ISD::SETEQ || Cond == ISD::SETNE)) { | |||
3350 | EVT ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT(); | |||
3351 | unsigned ExtSrcTyBits = ExtSrcTy.getSizeInBits(); | |||
3352 | EVT ExtDstTy = N0.getValueType(); | |||
3353 | unsigned ExtDstTyBits = ExtDstTy.getSizeInBits(); | |||
3354 | ||||
3355 | // If the constant doesn't fit into the number of bits for the source of | |||
3356 | // the sign extension, it is impossible for both sides to be equal. | |||
3357 | if (C1.getMinSignedBits() > ExtSrcTyBits) | |||
3358 | return DAG.getConstant(Cond == ISD::SETNE, dl, VT); | |||
3359 | ||||
3360 | SDValue ZextOp; | |||
3361 | EVT Op0Ty = N0.getOperand(0).getValueType(); | |||
3362 | if (Op0Ty == ExtSrcTy) { | |||
3363 | ZextOp = N0.getOperand(0); | |||
3364 | } else { | |||
3365 | APInt Imm = APInt::getLowBitsSet(ExtDstTyBits, ExtSrcTyBits); | |||
3366 | ZextOp = DAG.getNode(ISD::AND, dl, Op0Ty, N0.getOperand(0), | |||
3367 | DAG.getConstant(Imm, dl, Op0Ty)); | |||
3368 | } | |||
3369 | if (!DCI.isCalledByLegalizer()) | |||
3370 | DCI.AddToWorklist(ZextOp.getNode()); | |||
3371 | // Otherwise, make this a use of a zext. | |||
3372 | return DAG.getSetCC(dl, VT, ZextOp, | |||
3373 | DAG.getConstant(C1 & APInt::getLowBitsSet( | |||
3374 | ExtDstTyBits, | |||
3375 | ExtSrcTyBits), | |||
3376 | dl, ExtDstTy), | |||
3377 | Cond); | |||
3378 | } else if ((N1C->isNullValue() || N1C->isOne()) && | |||
3379 | (Cond == ISD::SETEQ || Cond == ISD::SETNE)) { | |||
3380 | // SETCC (SETCC), [0|1], [EQ|NE] -> SETCC | |||
3381 | if (N0.getOpcode() == ISD::SETCC && | |||
3382 | isTypeLegal(VT) && VT.bitsLE(N0.getValueType()) && | |||
3383 | (N0.getValueType() == MVT::i1 || | |||
3384 | getBooleanContents(N0.getOperand(0).getValueType()) == | |||
3385 | ZeroOrOneBooleanContent)) { | |||
3386 | bool TrueWhenTrue = (Cond == ISD::SETEQ) ^ (!N1C->isOne()); | |||
3387 | if (TrueWhenTrue) | |||
3388 | return DAG.getNode(ISD::TRUNCATE, dl, VT, N0); | |||
3389 | // Invert the condition. | |||
3390 | ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get(); | |||
3391 | CC = ISD::getSetCCInverse(CC, | |||
3392 | N0.getOperand(0).getValueType().isInteger()); | |||
3393 | if (DCI.isBeforeLegalizeOps() || | |||
3394 | isCondCodeLegal(CC, N0.getOperand(0).getSimpleValueType())) | |||
3395 | return DAG.getSetCC(dl, VT, N0.getOperand(0), N0.getOperand(1), CC); | |||
3396 | } | |||
3397 | ||||
3398 | if ((N0.getOpcode() == ISD::XOR || | |||
3399 | (N0.getOpcode() == ISD::AND && | |||
3400 | N0.getOperand(0).getOpcode() == ISD::XOR && | |||
3401 | N0.getOperand(1) == N0.getOperand(0).getOperand(1))) && | |||
3402 | isa<ConstantSDNode>(N0.getOperand(1)) && | |||
3403 | cast<ConstantSDNode>(N0.getOperand(1))->isOne()) { | |||
3404 | // If this is (X^1) == 0/1, swap the RHS and eliminate the xor. We | |||
3405 | // can only do this if the top bits are known zero. | |||
3406 | unsigned BitWidth = N0.getValueSizeInBits(); | |||
3407 | if (DAG.MaskedValueIsZero(N0, | |||
3408 | APInt::getHighBitsSet(BitWidth, | |||
3409 | BitWidth-1))) { | |||
3410 | // Okay, get the un-inverted input value. | |||
3411 | SDValue Val; | |||
3412 | if (N0.getOpcode() == ISD::XOR) { | |||
3413 | Val = N0.getOperand(0); | |||
3414 | } else { | |||
3415 | assert(N0.getOpcode() == ISD::AND &&((N0.getOpcode() == ISD::AND && N0.getOperand(0).getOpcode () == ISD::XOR) ? static_cast<void> (0) : __assert_fail ("N0.getOpcode() == ISD::AND && N0.getOperand(0).getOpcode() == ISD::XOR" , "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 3416, __PRETTY_FUNCTION__)) | |||
3416 | N0.getOperand(0).getOpcode() == ISD::XOR)((N0.getOpcode() == ISD::AND && N0.getOperand(0).getOpcode () == ISD::XOR) ? static_cast<void> (0) : __assert_fail ("N0.getOpcode() == ISD::AND && N0.getOperand(0).getOpcode() == ISD::XOR" , "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 3416, __PRETTY_FUNCTION__)); | |||
3417 | // ((X^1)&1)^1 -> X & 1 | |||
3418 | Val = DAG.getNode(ISD::AND, dl, N0.getValueType(), | |||
3419 | N0.getOperand(0).getOperand(0), | |||
3420 | N0.getOperand(1)); | |||
3421 | } | |||
3422 | ||||
3423 | return DAG.getSetCC(dl, VT, Val, N1, | |||
3424 | Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ); | |||
3425 | } | |||
3426 | } else if (N1C->isOne()) { | |||
3427 | SDValue Op0 = N0; | |||
3428 | if (Op0.getOpcode() == ISD::TRUNCATE) | |||
3429 | Op0 = Op0.getOperand(0); | |||
3430 | ||||
3431 | if ((Op0.getOpcode() == ISD::XOR) && | |||
3432 | Op0.getOperand(0).getOpcode() == ISD::SETCC && | |||
3433 | Op0.getOperand(1).getOpcode() == ISD::SETCC) { | |||
3434 | SDValue XorLHS = Op0.getOperand(0); | |||
3435 | SDValue XorRHS = Op0.getOperand(1); | |||
3436 | // Ensure that the input setccs return an i1 type or 0/1 value. | |||
3437 | if (Op0.getValueType() == MVT::i1 || | |||
3438 | (getBooleanContents(XorLHS.getOperand(0).getValueType()) == | |||
3439 | ZeroOrOneBooleanContent && | |||
3440 | getBooleanContents(XorRHS.getOperand(0).getValueType()) == | |||
3441 | ZeroOrOneBooleanContent)) { | |||
3442 | // (xor (setcc), (setcc)) == / != 1 -> (setcc) != / == (setcc) | |||
3443 | Cond = (Cond == ISD::SETEQ) ? ISD::SETNE : ISD::SETEQ; | |||
3444 | return DAG.getSetCC(dl, VT, XorLHS, XorRHS, Cond); | |||
3445 | } | |||
3446 | } | |||
3447 | if (Op0.getOpcode() == ISD::AND && | |||
3448 | isa<ConstantSDNode>(Op0.getOperand(1)) && | |||
3449 | cast<ConstantSDNode>(Op0.getOperand(1))->isOne()) { | |||
3450 | // If this is (X&1) == / != 1, normalize it to (X&1) != / == 0. | |||
3451 | if (Op0.getValueType().bitsGT(VT)) | |||
3452 | Op0 = DAG.getNode(ISD::AND, dl, VT, | |||
3453 | DAG.getNode(ISD::TRUNCATE, dl, VT, Op0.getOperand(0)), | |||
3454 | DAG.getConstant(1, dl, VT)); | |||
3455 | else if (Op0.getValueType().bitsLT(VT)) | |||
3456 | Op0 = DAG.getNode(ISD::AND, dl, VT, | |||
3457 | DAG.getNode(ISD::ANY_EXTEND, dl, VT, Op0.getOperand(0)), | |||
3458 | DAG.getConstant(1, dl, VT)); | |||
3459 | ||||
3460 | return DAG.getSetCC(dl, VT, Op0, | |||
3461 | DAG.getConstant(0, dl, Op0.getValueType()), | |||
3462 | Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ); | |||
3463 | } | |||
3464 | if (Op0.getOpcode() == ISD::AssertZext && | |||
3465 | cast<VTSDNode>(Op0.getOperand(1))->getVT() == MVT::i1) | |||
3466 | return DAG.getSetCC(dl, VT, Op0, | |||
3467 | DAG.getConstant(0, dl, Op0.getValueType()), | |||
3468 | Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ); | |||
3469 | } | |||
3470 | } | |||
3471 | ||||
3472 | // Given: | |||
3473 | // icmp eq/ne (urem %x, %y), 0 | |||
3474 | // Iff %x has 0 or 1 bits set, and %y has at least 2 bits set, omit 'urem': | |||
3475 | // icmp eq/ne %x, 0 | |||
3476 | if (N0.getOpcode() == ISD::UREM && N1C->isNullValue() && | |||
3477 | (Cond == ISD::SETEQ || Cond == ISD::SETNE)) { | |||
3478 | KnownBits XKnown = DAG.computeKnownBits(N0.getOperand(0)); | |||
3479 | KnownBits YKnown = DAG.computeKnownBits(N0.getOperand(1)); | |||
3480 | if (XKnown.countMaxPopulation() == 1 && YKnown.countMinPopulation() >= 2) | |||
3481 | return DAG.getSetCC(dl, VT, N0.getOperand(0), N1, Cond); | |||
3482 | } | |||
3483 | ||||
3484 | if (SDValue V = | |||
3485 | optimizeSetCCOfSignedTruncationCheck(VT, N0, N1, Cond, DCI, dl)) | |||
3486 | return V; | |||
3487 | } | |||
3488 | ||||
3489 | // These simplifications apply to splat vectors as well. | |||
3490 | // TODO: Handle more splat vector cases. | |||
3491 | if (auto *N1C = isConstOrConstSplat(N1)) { | |||
3492 | const APInt &C1 = N1C->getAPIntValue(); | |||
3493 | ||||
3494 | APInt MinVal, MaxVal; | |||
3495 | unsigned OperandBitSize = N1C->getValueType(0).getScalarSizeInBits(); | |||
3496 | if (ISD::isSignedIntSetCC(Cond)) { | |||
3497 | MinVal = APInt::getSignedMinValue(OperandBitSize); | |||
3498 | MaxVal = APInt::getSignedMaxValue(OperandBitSize); | |||
3499 | } else { | |||
3500 | MinVal = APInt::getMinValue(OperandBitSize); | |||
3501 | MaxVal = APInt::getMaxValue(OperandBitSize); | |||
3502 | } | |||
3503 | ||||
3504 | // Canonicalize GE/LE comparisons to use GT/LT comparisons. | |||
3505 | if (Cond == ISD::SETGE || Cond == ISD::SETUGE) { | |||
3506 | // X >= MIN --> true | |||
3507 | if (C1 == MinVal) | |||
3508 | return DAG.getBoolConstant(true, dl, VT, OpVT); | |||
3509 | ||||
3510 | if (!VT.isVector()) { // TODO: Support this for vectors. | |||
3511 | // X >= C0 --> X > (C0 - 1) | |||
3512 | APInt C = C1 - 1; | |||
3513 | ISD::CondCode NewCC = (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT; | |||
3514 | if ((DCI.isBeforeLegalizeOps() || | |||
3515 | isCondCodeLegal(NewCC, VT.getSimpleVT())) && | |||
3516 | (!N1C->isOpaque() || (C.getBitWidth() <= 64 && | |||
3517 | isLegalICmpImmediate(C.getSExtValue())))) { | |||
3518 | return DAG.getSetCC(dl, VT, N0, | |||
3519 | DAG.getConstant(C, dl, N1.getValueType()), | |||
3520 | NewCC); | |||
3521 | } | |||
3522 | } | |||
3523 | } | |||
3524 | ||||
3525 | if (Cond == ISD::SETLE || Cond == ISD::SETULE) { | |||
3526 | // X <= MAX --> true | |||
3527 | if (C1 == MaxVal) | |||
3528 | return DAG.getBoolConstant(true, dl, VT, OpVT); | |||
3529 | ||||
3530 | // X <= C0 --> X < (C0 + 1) | |||
3531 | if (!VT.isVector()) { // TODO: Support this for vectors. | |||
3532 | APInt C = C1 + 1; | |||
3533 | ISD::CondCode NewCC = (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT; | |||
3534 | if ((DCI.isBeforeLegalizeOps() || | |||
3535 | isCondCodeLegal(NewCC, VT.getSimpleVT())) && | |||
3536 | (!N1C->isOpaque() || (C.getBitWidth() <= 64 && | |||
3537 | isLegalICmpImmediate(C.getSExtValue())))) { | |||
3538 | return DAG.getSetCC(dl, VT, N0, | |||
3539 | DAG.getConstant(C, dl, N1.getValueType()), | |||
3540 | NewCC); | |||
3541 | } | |||
3542 | } | |||
3543 | } | |||
3544 | ||||
3545 | if (Cond == ISD::SETLT || Cond == ISD::SETULT) { | |||
3546 | if (C1 == MinVal) | |||
3547 | return DAG.getBoolConstant(false, dl, VT, OpVT); // X < MIN --> false | |||
3548 | ||||
3549 | // TODO: Support this for vectors after legalize ops. | |||
3550 | if (!VT.isVector() || DCI.isBeforeLegalizeOps()) { | |||
3551 | // Canonicalize setlt X, Max --> setne X, Max | |||
3552 | if (C1 == MaxVal) | |||
3553 | return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE); | |||
3554 | ||||
3555 | // If we have setult X, 1, turn it into seteq X, 0 | |||
3556 | if (C1 == MinVal+1) | |||
3557 | return DAG.getSetCC(dl, VT, N0, | |||
3558 | DAG.getConstant(MinVal, dl, N0.getValueType()), | |||
3559 | ISD::SETEQ); | |||
3560 | } | |||
3561 | } | |||
3562 | ||||
3563 | if (Cond == ISD::SETGT || Cond == ISD::SETUGT) { | |||
3564 | if (C1 == MaxVal) | |||
3565 | return DAG.getBoolConstant(false, dl, VT, OpVT); // X > MAX --> false | |||
3566 | ||||
3567 | // TODO: Support this for vectors after legalize ops. | |||
3568 | if (!VT.isVector() || DCI.isBeforeLegalizeOps()) { | |||
3569 | // Canonicalize setgt X, Min --> setne X, Min | |||
3570 | if (C1 == MinVal) | |||
3571 | return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE); | |||
3572 | ||||
3573 | // If we have setugt X, Max-1, turn it into seteq X, Max | |||
3574 | if (C1 == MaxVal-1) | |||
3575 | return DAG.getSetCC(dl, VT, N0, | |||
3576 | DAG.getConstant(MaxVal, dl, N0.getValueType()), | |||
3577 | ISD::SETEQ); | |||
3578 | } | |||
3579 | } | |||
3580 | ||||
3581 | if (Cond == ISD::SETEQ || Cond == ISD::SETNE) { | |||
3582 | // (X & (C l>>/<< Y)) ==/!= 0 --> ((X <</l>> Y) & C) ==/!= 0 | |||
3583 | if (C1.isNullValue()) | |||
3584 | if (SDValue CC = optimizeSetCCByHoistingAndByConstFromLogicalShift( | |||
3585 | VT, N0, N1, Cond, DCI, dl)) | |||
3586 | return CC; | |||
3587 | } | |||
3588 | ||||
3589 | // If we have "setcc X, C0", check to see if we can shrink the immediate | |||
3590 | // by changing cc. | |||
3591 | // TODO: Support this for vectors after legalize ops. | |||
3592 | if (!VT.isVector() || DCI.isBeforeLegalizeOps()) { | |||
3593 | // SETUGT X, SINTMAX -> SETLT X, 0 | |||
3594 | if (Cond == ISD::SETUGT && | |||
3595 | C1 == APInt::getSignedMaxValue(OperandBitSize)) | |||
3596 | return DAG.getSetCC(dl, VT, N0, | |||
3597 | DAG.getConstant(0, dl, N1.getValueType()), | |||
3598 | ISD::SETLT); | |||
3599 | ||||
3600 | // SETULT X, SINTMIN -> SETGT X, -1 | |||
3601 | if (Cond == ISD::SETULT && | |||
3602 | C1 == APInt::getSignedMinValue(OperandBitSize)) { | |||
3603 | SDValue ConstMinusOne = | |||
3604 | DAG.getConstant(APInt::getAllOnesValue(OperandBitSize), dl, | |||
3605 | N1.getValueType()); | |||
3606 | return DAG.getSetCC(dl, VT, N0, ConstMinusOne, ISD::SETGT); | |||
3607 | } | |||
3608 | } | |||
3609 | } | |||
3610 | ||||
3611 | // Back to non-vector simplifications. | |||
3612 | // TODO: Can we do these for vector splats? | |||
3613 | if (auto *N1C = dyn_cast<ConstantSDNode>(N1.getNode())) { | |||
3614 | const TargetLowering &TLI = DAG.getTargetLoweringInfo(); | |||
3615 | const APInt &C1 = N1C->getAPIntValue(); | |||
3616 | EVT ShValTy = N0.getValueType(); | |||
3617 | ||||
3618 | // Fold bit comparisons when we can. | |||
3619 | if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && | |||
3620 | (VT == ShValTy || (isTypeLegal(VT) && VT.bitsLE(ShValTy))) && | |||
3621 | N0.getOpcode() == ISD::AND) { | |||
3622 | if (auto *AndRHS = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { | |||
3623 | EVT ShiftTy = | |||
3624 | getShiftAmountTy(ShValTy, Layout, !DCI.isBeforeLegalize()); | |||
3625 | if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3 | |||
3626 | // Perform the xform if the AND RHS is a single bit. | |||
3627 | unsigned ShCt = AndRHS->getAPIntValue().logBase2(); | |||
3628 | if (AndRHS->getAPIntValue().isPowerOf2() && | |||
3629 | ShCt <= TLI.getShiftAmountThreshold(ShValTy)) { | |||
3630 | return DAG.getNode(ISD::TRUNCATE, dl, VT, | |||
3631 | DAG.getNode(ISD::SRL, dl, ShValTy, N0, | |||
3632 | DAG.getConstant(ShCt, dl, ShiftTy))); | |||
3633 | } | |||
3634 | } else if (Cond == ISD::SETEQ && C1 == AndRHS->getAPIntValue()) { | |||
3635 | // (X & 8) == 8 --> (X & 8) >> 3 | |||
3636 | // Perform the xform if C1 is a single bit. | |||
3637 | unsigned ShCt = C1.logBase2(); | |||
3638 | if (C1.isPowerOf2() && | |||
3639 | ShCt <= TLI.getShiftAmountThreshold(ShValTy)) { | |||
3640 | return DAG.getNode(ISD::TRUNCATE, dl, VT, | |||
3641 | DAG.getNode(ISD::SRL, dl, ShValTy, N0, | |||
3642 | DAG.getConstant(ShCt, dl, ShiftTy))); | |||
3643 | } | |||
3644 | } | |||
3645 | } | |||
3646 | } | |||
3647 | ||||
3648 | if (C1.getMinSignedBits() <= 64 && | |||
3649 | !isLegalICmpImmediate(C1.getSExtValue())) { | |||
3650 | EVT ShiftTy = getShiftAmountTy(ShValTy, Layout, !DCI.isBeforeLegalize()); | |||
3651 | // (X & -256) == 256 -> (X >> 8) == 1 | |||
3652 | if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && | |||
3653 | N0.getOpcode() == ISD::AND && N0.hasOneUse()) { | |||
3654 | if (auto *AndRHS = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { | |||
3655 | const APInt &AndRHSC = AndRHS->getAPIntValue(); | |||
3656 | if ((-AndRHSC).isPowerOf2() && (AndRHSC & C1) == C1) { | |||
3657 | unsigned ShiftBits = AndRHSC.countTrailingZeros(); | |||
3658 | if (ShiftBits <= TLI.getShiftAmountThreshold(ShValTy)) { | |||
3659 | SDValue Shift = | |||
3660 | DAG.getNode(ISD::SRL, dl, ShValTy, N0.getOperand(0), | |||
3661 | DAG.getConstant(ShiftBits, dl, ShiftTy)); | |||
3662 | SDValue CmpRHS = DAG.getConstant(C1.lshr(ShiftBits), dl, ShValTy); | |||
3663 | return DAG.getSetCC(dl, VT, Shift, CmpRHS, Cond); | |||
3664 | } | |||
3665 | } | |||
3666 | } | |||
3667 | } else if (Cond == ISD::SETULT || Cond == ISD::SETUGE || | |||
3668 | Cond == ISD::SETULE || Cond == ISD::SETUGT) { | |||
3669 | bool AdjOne = (Cond == ISD::SETULE || Cond == ISD::SETUGT); | |||
3670 | // X < 0x100000000 -> (X >> 32) < 1 | |||
3671 | // X >= 0x100000000 -> (X >> 32) >= 1 | |||
3672 | // X <= 0x0ffffffff -> (X >> 32) < 1 | |||
3673 | // X > 0x0ffffffff -> (X >> 32) >= 1 | |||
3674 | unsigned ShiftBits; | |||
3675 | APInt NewC = C1; | |||
3676 | ISD::CondCode NewCond = Cond; | |||
3677 | if (AdjOne) { | |||
3678 | ShiftBits = C1.countTrailingOnes(); | |||
3679 | NewC = NewC + 1; | |||
3680 | NewCond = (Cond == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE; | |||
3681 | } else { | |||
3682 | ShiftBits = C1.countTrailingZeros(); | |||
3683 | } | |||
3684 | NewC.lshrInPlace(ShiftBits); | |||
3685 | if (ShiftBits && NewC.getMinSignedBits() <= 64 && | |||
3686 | isLegalICmpImmediate(NewC.getSExtValue()) && | |||
3687 | ShiftBits <= TLI.getShiftAmountThreshold(ShValTy)) { | |||
3688 | SDValue Shift = DAG.getNode(ISD::SRL, dl, ShValTy, N0, | |||
3689 | DAG.getConstant(ShiftBits, dl, ShiftTy)); | |||
3690 | SDValue CmpRHS = DAG.getConstant(NewC, dl, ShValTy); | |||
3691 | return DAG.getSetCC(dl, VT, Shift, CmpRHS, NewCond); | |||
3692 | } | |||
3693 | } | |||
3694 | } | |||
3695 | } | |||
3696 | ||||
3697 | if (!isa<ConstantFPSDNode>(N0) && isa<ConstantFPSDNode>(N1)) { | |||
3698 | auto *CFP = cast<ConstantFPSDNode>(N1); | |||
3699 | assert(!CFP->getValueAPF().isNaN() && "Unexpected NaN value")((!CFP->getValueAPF().isNaN() && "Unexpected NaN value" ) ? static_cast<void> (0) : __assert_fail ("!CFP->getValueAPF().isNaN() && \"Unexpected NaN value\"" , "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 3699, __PRETTY_FUNCTION__)); | |||
3700 | ||||
3701 | // Otherwise, we know the RHS is not a NaN. Simplify the node to drop the | |||
3702 | // constant if knowing that the operand is non-nan is enough. We prefer to | |||
3703 | // have SETO(x,x) instead of SETO(x, 0.0) because this avoids having to | |||
3704 | // materialize 0.0. | |||
3705 | if (Cond == ISD::SETO || Cond == ISD::SETUO) | |||
3706 | return DAG.getSetCC(dl, VT, N0, N0, Cond); | |||
3707 | ||||
3708 | // setcc (fneg x), C -> setcc swap(pred) x, -C | |||
3709 | if (N0.getOpcode() == ISD::FNEG) { | |||
3710 | ISD::CondCode SwapCond = ISD::getSetCCSwappedOperands(Cond); | |||
3711 | if (DCI.isBeforeLegalizeOps() || | |||
3712 | isCondCodeLegal(SwapCond, N0.getSimpleValueType())) { | |||
3713 | SDValue NegN1 = DAG.getNode(ISD::FNEG, dl, N0.getValueType(), N1); | |||
3714 | return DAG.getSetCC(dl, VT, N0.getOperand(0), NegN1, SwapCond); | |||
3715 | } | |||
3716 | } | |||
3717 | ||||
3718 | // If the condition is not legal, see if we can find an equivalent one | |||
3719 | // which is legal. | |||
3720 | if (!isCondCodeLegal(Cond, N0.getSimpleValueType())) { | |||
3721 | // If the comparison was an awkward floating-point == or != and one of | |||
3722 | // the comparison operands is infinity or negative infinity, convert the | |||
3723 | // condition to a less-awkward <= or >=. | |||
3724 | if (CFP->getValueAPF().isInfinity()) { | |||
3725 | if (CFP->getValueAPF().isNegative()) { | |||
3726 | if (Cond == ISD::SETOEQ && | |||
3727 | isCondCodeLegal(ISD::SETOLE, N0.getSimpleValueType())) | |||
3728 | return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLE); | |||
3729 | if (Cond == ISD::SETUEQ && | |||
3730 | isCondCodeLegal(ISD::SETOLE, N0.getSimpleValueType())) | |||
3731 | return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULE); | |||
3732 | if (Cond == ISD::SETUNE && | |||
3733 | isCondCodeLegal(ISD::SETUGT, N0.getSimpleValueType())) | |||
3734 | return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGT); | |||
3735 | if (Cond == ISD::SETONE && | |||
3736 | isCondCodeLegal(ISD::SETUGT, N0.getSimpleValueType())) | |||
3737 | return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGT); | |||
3738 | } else { | |||
3739 | if (Cond == ISD::SETOEQ && | |||
3740 | isCondCodeLegal(ISD::SETOGE, N0.getSimpleValueType())) | |||
3741 | return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGE); | |||
3742 | if (Cond == ISD::SETUEQ && | |||
3743 | isCondCodeLegal(ISD::SETOGE, N0.getSimpleValueType())) | |||
3744 | return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGE); | |||
3745 | if (Cond == ISD::SETUNE && | |||
3746 | isCondCodeLegal(ISD::SETULT, N0.getSimpleValueType())) | |||
3747 | return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULT); | |||
3748 | if (Cond == ISD::SETONE && | |||
3749 | isCondCodeLegal(ISD::SETULT, N0.getSimpleValueType())) | |||
3750 | return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLT); | |||
3751 | } | |||
3752 | } | |||
3753 | } | |||
3754 | } | |||
3755 | ||||
3756 | if (N0 == N1) { | |||
3757 | // The sext(setcc()) => setcc() optimization relies on the appropriate | |||
3758 | // constant being emitted. | |||
3759 | assert(!N0.getValueType().isInteger() &&((!N0.getValueType().isInteger() && "Integer types should be handled by FoldSetCC" ) ? static_cast<void> (0) : __assert_fail ("!N0.getValueType().isInteger() && \"Integer types should be handled by FoldSetCC\"" , "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 3760, __PRETTY_FUNCTION__)) | |||
3760 | "Integer types should be handled by FoldSetCC")((!N0.getValueType().isInteger() && "Integer types should be handled by FoldSetCC" ) ? static_cast<void> (0) : __assert_fail ("!N0.getValueType().isInteger() && \"Integer types should be handled by FoldSetCC\"" , "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 3760, __PRETTY_FUNCTION__)); | |||
3761 | ||||
3762 | bool EqTrue = ISD::isTrueWhenEqual(Cond); | |||
3763 | unsigned UOF = ISD::getUnorderedFlavor(Cond); | |||
3764 | if (UOF == 2) // FP operators that are undefined on NaNs. | |||
3765 | return DAG.getBoolConstant(EqTrue, dl, VT, OpVT); | |||
3766 | if (UOF == unsigned(EqTrue)) | |||
3767 | return DAG.getBoolConstant(EqTrue, dl, VT, OpVT); | |||
3768 | // Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO | |||
3769 | // if it is not already. | |||
3770 | ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO; | |||
3771 | if (NewCond != Cond && | |||
3772 | (DCI.isBeforeLegalizeOps() || | |||
3773 | isCondCodeLegal(NewCond, N0.getSimpleValueType()))) | |||
3774 | return DAG.getSetCC(dl, VT, N0, N1, NewCond); | |||
3775 | } | |||
3776 | ||||
3777 | if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && | |||
3778 | N0.getValueType().isInteger()) { | |||
3779 | if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB || | |||
3780 | N0.getOpcode() == ISD::XOR) { | |||
3781 | // Simplify (X+Y) == (X+Z) --> Y == Z | |||
3782 | if (N0.getOpcode() == N1.getOpcode()) { | |||
3783 | if (N0.getOperand(0) == N1.getOperand(0)) | |||
3784 | return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(1), Cond); | |||
3785 | if (N0.getOperand(1) == N1.getOperand(1)) | |||
3786 | return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(0), Cond); | |||
3787 | if (isCommutativeBinOp(N0.getOpcode())) { | |||
3788 | // If X op Y == Y op X, try other combinations. | |||
3789 | if (N0.getOperand(0) == N1.getOperand(1)) | |||
3790 | return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(0), | |||
3791 | Cond); | |||
3792 | if (N0.getOperand(1) == N1.getOperand(0)) | |||
3793 | return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(1), | |||
3794 | Cond); | |||
3795 | } | |||
3796 | } | |||
3797 | ||||
3798 | // If RHS is a legal immediate value for a compare instruction, we need | |||
3799 | // to be careful about increasing register pressure needlessly. | |||
3800 | bool LegalRHSImm = false; | |||
3801 | ||||
3802 | if (auto *RHSC = dyn_cast<ConstantSDNode>(N1)) { | |||
3803 | if (auto *LHSR = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { | |||
3804 | // Turn (X+C1) == C2 --> X == C2-C1 | |||
3805 | if (N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse()) { | |||
3806 | return DAG.getSetCC(dl, VT, N0.getOperand(0), | |||
3807 | DAG.getConstant(RHSC->getAPIntValue()- | |||
3808 | LHSR->getAPIntValue(), | |||
3809 | dl, N0.getValueType()), Cond); | |||
3810 | } | |||
3811 | ||||
3812 | // Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0. | |||
3813 | if (N0.getOpcode() == ISD::XOR) | |||
3814 | // If we know that all of the inverted bits are zero, don't bother | |||
3815 | // performing the inversion. | |||
3816 | if (DAG.MaskedValueIsZero(N0.getOperand(0), ~LHSR->getAPIntValue())) | |||
3817 | return | |||
3818 | DAG.getSetCC(dl, VT, N0.getOperand(0), | |||
3819 | DAG.getConstant(LHSR->getAPIntValue() ^ | |||
3820 | RHSC->getAPIntValue(), | |||
3821 | dl, N0.getValueType()), | |||
3822 | Cond); | |||
3823 | } | |||
3824 | ||||
3825 | // Turn (C1-X) == C2 --> X == C1-C2 | |||
3826 | if (auto *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand(0))) { | |||
3827 | if (N0.getOpcode() == ISD::SUB && N0.getNode()->hasOneUse()) { | |||
3828 | return | |||
3829 | DAG.getSetCC(dl, VT, N0.getOperand(1), | |||
3830 | DAG.getConstant(SUBC->getAPIntValue() - | |||
3831 | RHSC->getAPIntValue(), | |||
3832 | dl, N0.getValueType()), | |||
3833 | Cond); | |||
3834 | } | |||
3835 | } | |||
3836 | ||||
3837 | // Could RHSC fold directly into a compare? | |||
3838 | if (RHSC->getValueType(0).getSizeInBits() <= 64) | |||
3839 | LegalRHSImm = isLegalICmpImmediate(RHSC->getSExtValue()); | |||
3840 | } | |||
3841 | ||||
3842 | // (X+Y) == X --> Y == 0 and similar folds. | |||
3843 | // Don't do this if X is an immediate that can fold into a cmp | |||
3844 | // instruction and X+Y has other uses. It could be an induction variable | |||
3845 | // chain, and the transform would increase register pressure. | |||
3846 | if (!LegalRHSImm || N0.hasOneUse()) | |||
3847 | if (SDValue V = foldSetCCWithBinOp(VT, N0, N1, Cond, dl, DCI)) | |||
3848 | return V; | |||
3849 | } | |||
3850 | ||||
3851 | if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB || | |||
3852 | N1.getOpcode() == ISD::XOR) | |||
3853 | if (SDValue V = foldSetCCWithBinOp(VT, N1, N0, Cond, dl, DCI)) | |||
3854 | return V; | |||
3855 | ||||
3856 | if (SDValue V = foldSetCCWithAnd(VT, N0, N1, Cond, dl, DCI)) | |||
3857 | return V; | |||
3858 | } | |||
3859 | ||||
3860 | // Fold remainder of division by a constant. | |||
3861 | if ((N0.getOpcode() == ISD::UREM || N0.getOpcode() == ISD::SREM) && | |||
3862 | N0.hasOneUse() && (Cond == ISD::SETEQ || Cond == ISD::SETNE)) { | |||
3863 | AttributeList Attr = DAG.getMachineFunction().getFunction().getAttributes(); | |||
3864 | ||||
3865 | // When division is cheap or optimizing for minimum size, | |||
3866 | // fall through to DIVREM creation by skipping this fold. | |||
3867 | if (!isIntDivCheap(VT, Attr) && !Attr.hasFnAttribute(Attribute::MinSize)) { | |||
3868 | if (N0.getOpcode() == ISD::UREM) { | |||
3869 | if (SDValue Folded = buildUREMEqFold(VT, N0, N1, Cond, DCI, dl)) | |||
3870 | return Folded; | |||
3871 | } else if (N0.getOpcode() == ISD::SREM) { | |||
3872 | if (SDValue Folded = buildSREMEqFold(VT, N0, N1, Cond, DCI, dl)) | |||
3873 | return Folded; | |||
3874 | } | |||
3875 | } | |||
3876 | } | |||
3877 | ||||
3878 | // Fold away ALL boolean setcc's. | |||
3879 | if (N0.getValueType().getScalarType() == MVT::i1 && foldBooleans) { | |||
3880 | SDValue Temp; | |||
3881 | switch (Cond) { | |||
3882 | default: llvm_unreachable("Unknown integer setcc!")::llvm::llvm_unreachable_internal("Unknown integer setcc!", "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 3882); | |||
3883 | case ISD::SETEQ: // X == Y -> ~(X^Y) | |||
3884 | Temp = DAG.getNode(ISD::XOR, dl, OpVT, N0, N1); | |||
3885 | N0 = DAG.getNOT(dl, Temp, OpVT); | |||
3886 | if (!DCI.isCalledByLegalizer()) | |||
3887 | DCI.AddToWorklist(Temp.getNode()); | |||
3888 | break; | |||
3889 | case ISD::SETNE: // X != Y --> (X^Y) | |||
3890 | N0 = DAG.getNode(ISD::XOR, dl, OpVT, N0, N1); | |||
3891 | break; | |||
3892 | case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> ~X & Y | |||
3893 | case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> ~X & Y | |||
3894 | Temp = DAG.getNOT(dl, N0, OpVT); | |||
3895 | N0 = DAG.getNode(ISD::AND, dl, OpVT, N1, Temp); | |||
3896 | if (!DCI.isCalledByLegalizer()) | |||
3897 | DCI.AddToWorklist(Temp.getNode()); | |||
3898 | break; | |||
3899 | case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> ~Y & X | |||
3900 | case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> ~Y & X | |||
3901 | Temp = DAG.getNOT(dl, N1, OpVT); | |||
3902 | N0 = DAG.getNode(ISD::AND, dl, OpVT, N0, Temp); | |||
3903 | if (!DCI.isCalledByLegalizer()) | |||
3904 | DCI.AddToWorklist(Temp.getNode()); | |||
3905 | break; | |||
3906 | case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> ~X | Y | |||
3907 | case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> ~X | Y | |||
3908 | Temp = DAG.getNOT(dl, N0, OpVT); | |||
3909 | N0 = DAG.getNode(ISD::OR, dl, OpVT, N1, Temp); | |||
3910 | if (!DCI.isCalledByLegalizer()) | |||
3911 | DCI.AddToWorklist(Temp.getNode()); | |||
3912 | break; | |||
3913 | case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> ~Y | X | |||
3914 | case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> ~Y | X | |||
3915 | Temp = DAG.getNOT(dl, N1, OpVT); | |||
3916 | N0 = DAG.getNode(ISD::OR, dl, OpVT, N0, Temp); | |||
3917 | break; | |||
3918 | } | |||
3919 | if (VT.getScalarType() != MVT::i1) { | |||
3920 | if (!DCI.isCalledByLegalizer()) | |||
3921 | DCI.AddToWorklist(N0.getNode()); | |||
3922 | // FIXME: If running after legalize, we probably can't do this. | |||
3923 | ISD::NodeType ExtendCode = getExtendForContent(getBooleanContents(OpVT)); | |||
3924 | N0 = DAG.getNode(ExtendCode, dl, VT, N0); | |||
3925 | } | |||
3926 | return N0; | |||
3927 | } | |||
3928 | ||||
3929 | // Could not fold it. | |||
3930 | return SDValue(); | |||
3931 | } | |||
3932 | ||||
3933 | /// Returns true (and the GlobalValue and the offset) if the node is a | |||
3934 | /// GlobalAddress + offset. | |||
3935 | bool TargetLowering::isGAPlusOffset(SDNode *WN, const GlobalValue *&GA, | |||
3936 | int64_t &Offset) const { | |||
3937 | ||||
3938 | SDNode *N = unwrapAddress(SDValue(WN, 0)).getNode(); | |||
3939 | ||||
3940 | if (auto *GASD = dyn_cast<GlobalAddressSDNode>(N)) { | |||
3941 | GA = GASD->getGlobal(); | |||
3942 | Offset += GASD->getOffset(); | |||
3943 | return true; | |||
3944 | } | |||
3945 | ||||
3946 | if (N->getOpcode() == ISD::ADD) { | |||
3947 | SDValue N1 = N->getOperand(0); | |||
3948 | SDValue N2 = N->getOperand(1); | |||
3949 | if (isGAPlusOffset(N1.getNode(), GA, Offset)) { | |||
3950 | if (auto *V = dyn_cast<ConstantSDNode>(N2)) { | |||
3951 | Offset += V->getSExtValue(); | |||
3952 | return true; | |||
3953 | } | |||
3954 | } else if (isGAPlusOffset(N2.getNode(), GA, Offset)) { | |||
3955 | if (auto *V = dyn_cast<ConstantSDNode>(N1)) { | |||
3956 | Offset += V->getSExtValue(); | |||
3957 | return true; | |||
3958 | } | |||
3959 | } | |||
3960 | } | |||
3961 | ||||
3962 | return false; | |||
3963 | } | |||
3964 | ||||
3965 | SDValue TargetLowering::PerformDAGCombine(SDNode *N, | |||
3966 | DAGCombinerInfo &DCI) const { | |||
3967 | // Default implementation: no optimization. | |||
3968 | return SDValue(); | |||
3969 | } | |||
3970 | ||||
3971 | //===----------------------------------------------------------------------===// | |||
3972 | // Inline Assembler Implementation Methods | |||
3973 | //===----------------------------------------------------------------------===// | |||
3974 | ||||
3975 | TargetLowering::ConstraintType | |||
3976 | TargetLowering::getConstraintType(StringRef Constraint) const { | |||
3977 | unsigned S = Constraint.size(); | |||
3978 | ||||
3979 | if (S == 1) { | |||
3980 | switch (Constraint[0]) { | |||
3981 | default: break; | |||
3982 | case 'r': | |||
3983 | return C_RegisterClass; | |||
3984 | case 'm': // memory | |||
3985 | case 'o': // offsetable | |||
3986 | case 'V': // not offsetable | |||
3987 | return C_Memory; | |||
3988 | case 'n': // Simple Integer | |||
3989 | case 'E': // Floating Point Constant | |||
3990 | case 'F': // Floating Point Constant | |||
3991 | return C_Immediate; | |||
3992 | case 'i': // Simple Integer or Relocatable Constant | |||
3993 | case 's': // Relocatable Constant | |||
3994 | case 'p': // Address. | |||
3995 | case 'X': // Allow ANY value. | |||
3996 | case 'I': // Target registers. | |||
3997 | case 'J': | |||
3998 | case 'K': | |||
3999 | case 'L': | |||
4000 | case 'M': | |||
4001 | case 'N': | |||
4002 | case 'O': | |||
4003 | case 'P': | |||
4004 | case '<': | |||
4005 | case '>': | |||
4006 | return C_Other; | |||
4007 | } | |||
4008 | } | |||
4009 | ||||
4010 | if (S > 1 && Constraint[0] == '{' && Constraint[S - 1] == '}') { | |||
4011 | if (S == 8 && Constraint.substr(1, 6) == "memory") // "{memory}" | |||
4012 | return C_Memory; | |||
4013 | return C_Register; | |||
4014 | } | |||
4015 | return C_Unknown; | |||
4016 | } | |||
4017 | ||||
4018 | /// Try to replace an X constraint, which matches anything, with another that | |||
4019 | /// has more specific requirements based on the type of the corresponding | |||
4020 | /// operand. | |||
4021 | const char *TargetLowering::LowerXConstraint(EVT ConstraintVT) const { | |||
4022 | if (ConstraintVT.isInteger()) | |||
4023 | return "r"; | |||
4024 | if (ConstraintVT.isFloatingPoint()) | |||
4025 | return "f"; // works for many targets | |||
4026 | return nullptr; | |||
4027 | } | |||
4028 | ||||
4029 | SDValue TargetLowering::LowerAsmOutputForConstraint( | |||
4030 | SDValue &Chain, SDValue &Flag, SDLoc DL, const AsmOperandInfo &OpInfo, | |||
4031 | SelectionDAG &DAG) const { | |||
4032 | return SDValue(); | |||
4033 | } | |||
4034 | ||||
4035 | /// Lower the specified operand into the Ops vector. | |||
4036 | /// If it is invalid, don't add anything to Ops. | |||
4037 | void TargetLowering::LowerAsmOperandForConstraint(SDValue Op, | |||
4038 | std::string &Constraint, | |||
4039 | std::vector<SDValue> &Ops, | |||
4040 | SelectionDAG &DAG) const { | |||
4041 | ||||
4042 | if (Constraint.length() > 1) return; | |||
4043 | ||||
4044 | char ConstraintLetter = Constraint[0]; | |||
4045 | switch (ConstraintLetter) { | |||
4046 | default: break; | |||
4047 | case 'X': // Allows any operand; labels (basic block) use this. | |||
4048 | if (Op.getOpcode() == ISD::BasicBlock || | |||
4049 | Op.getOpcode() == ISD::TargetBlockAddress) { | |||
4050 | Ops.push_back(Op); | |||
4051 | return; | |||
4052 | } | |||
4053 | LLVM_FALLTHROUGH[[gnu::fallthrough]]; | |||
4054 | case 'i': // Simple Integer or Relocatable Constant | |||
4055 | case 'n': // Simple Integer | |||
4056 | case 's': { // Relocatable Constant | |||
4057 | ||||
4058 | GlobalAddressSDNode *GA; | |||
4059 | ConstantSDNode *C; | |||
4060 | BlockAddressSDNode *BA; | |||
4061 | uint64_t Offset = 0; | |||
4062 | ||||
4063 | // Match (GA) or (C) or (GA+C) or (GA-C) or ((GA+C)+C) or (((GA+C)+C)+C), | |||
4064 | // etc., since getelementpointer is variadic. We can't use | |||
4065 | // SelectionDAG::FoldSymbolOffset because it expects the GA to be accessible | |||
4066 | // while in this case the GA may be furthest from the root node which is | |||
4067 | // likely an ISD::ADD. | |||
4068 | while (1) { | |||
4069 | if ((GA = dyn_cast<GlobalAddressSDNode>(Op)) && ConstraintLetter != 'n') { | |||
4070 | Ops.push_back(DAG.getTargetGlobalAddress(GA->getGlobal(), SDLoc(Op), | |||
4071 | GA->getValueType(0), | |||
4072 | Offset + GA->getOffset())); | |||
4073 | return; | |||
4074 | } else if ((C = dyn_cast<ConstantSDNode>(Op)) && | |||
4075 | ConstraintLetter != 's') { | |||
4076 | // gcc prints these as sign extended. Sign extend value to 64 bits | |||
4077 | // now; without this it would get ZExt'd later in | |||
4078 | // ScheduleDAGSDNodes::EmitNode, which is very generic. | |||
4079 | bool IsBool = C->getConstantIntValue()->getBitWidth() == 1; | |||
4080 | BooleanContent BCont = getBooleanContents(MVT::i64); | |||
4081 | ISD::NodeType ExtOpc = IsBool ? getExtendForContent(BCont) | |||
4082 | : ISD::SIGN_EXTEND; | |||
4083 | int64_t ExtVal = ExtOpc == ISD::ZERO_EXTEND ? C->getZExtValue() | |||
4084 | : C->getSExtValue(); | |||
4085 | Ops.push_back(DAG.getTargetConstant(Offset + ExtVal, | |||
4086 | SDLoc(C), MVT::i64)); | |||
4087 | return; | |||
4088 | } else if ((BA = dyn_cast<BlockAddressSDNode>(Op)) && | |||
4089 | ConstraintLetter != 'n') { | |||
4090 | Ops.push_back(DAG.getTargetBlockAddress( | |||
4091 | BA->getBlockAddress(), BA->getValueType(0), | |||
4092 | Offset + BA->getOffset(), BA->getTargetFlags())); | |||
4093 | return; | |||
4094 | } else { | |||
4095 | const unsigned OpCode = Op.getOpcode(); | |||
4096 | if (OpCode == ISD::ADD || OpCode == ISD::SUB) { | |||
4097 | if ((C = dyn_cast<ConstantSDNode>(Op.getOperand(0)))) | |||
4098 | Op = Op.getOperand(1); | |||
4099 | // Subtraction is not commutative. | |||
4100 | else if (OpCode == ISD::ADD && | |||
4101 | (C = dyn_cast<ConstantSDNode>(Op.getOperand(1)))) | |||
4102 | Op = Op.getOperand(0); | |||
4103 | else | |||
4104 | return; | |||
4105 | Offset += (OpCode == ISD::ADD ? 1 : -1) * C->getSExtValue(); | |||
4106 | continue; | |||
4107 | } | |||
4108 | } | |||
4109 | return; | |||
4110 | } | |||
4111 | break; | |||
4112 | } | |||
4113 | } | |||
4114 | } | |||
4115 | ||||
4116 | std::pair<unsigned, const TargetRegisterClass *> | |||
4117 | TargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *RI, | |||
4118 | StringRef Constraint, | |||
4119 | MVT VT) const { | |||
4120 | if (Constraint.empty() || Constraint[0] != '{') | |||
4121 | return std::make_pair(0u, static_cast<TargetRegisterClass *>(nullptr)); | |||
4122 | assert(*(Constraint.end() - 1) == '}' && "Not a brace enclosed constraint?")((*(Constraint.end() - 1) == '}' && "Not a brace enclosed constraint?" ) ? static_cast<void> (0) : __assert_fail ("*(Constraint.end() - 1) == '}' && \"Not a brace enclosed constraint?\"" , "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 4122, __PRETTY_FUNCTION__)); | |||
4123 | ||||
4124 | // Remove the braces from around the name. | |||
4125 | StringRef RegName(Constraint.data() + 1, Constraint.size() - 2); | |||
4126 | ||||
4127 | std::pair<unsigned, const TargetRegisterClass *> R = | |||
4128 | std::make_pair(0u, static_cast<const TargetRegisterClass *>(nullptr)); | |||
4129 | ||||
4130 | // Figure out which register class contains this reg. | |||
4131 | for (const TargetRegisterClass *RC : RI->regclasses()) { | |||
4132 | // If none of the value types for this register class are valid, we | |||
4133 | // can't use it. For example, 64-bit reg classes on 32-bit targets. | |||
4134 | if (!isLegalRC(*RI, *RC)) | |||
4135 | continue; | |||
4136 | ||||
4137 | for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end(); | |||
4138 | I != E; ++I) { | |||
4139 | if (RegName.equals_lower(RI->getRegAsmName(*I))) { | |||
4140 | std::pair<unsigned, const TargetRegisterClass *> S = | |||
4141 | std::make_pair(*I, RC); | |||
4142 | ||||
4143 | // If this register class has the requested value type, return it, | |||
4144 | // otherwise keep searching and return the first class found | |||
4145 | // if no other is found which explicitly has the requested type. | |||
4146 | if (RI->isTypeLegalForClass(*RC, VT)) | |||
4147 | return S; | |||
4148 | if (!R.second) | |||
4149 | R = S; | |||
4150 | } | |||
4151 | } | |||
4152 | } | |||
4153 | ||||
4154 | return R; | |||
4155 | } | |||
4156 | ||||
4157 | //===----------------------------------------------------------------------===// | |||
4158 | // Constraint Selection. | |||
4159 | ||||
4160 | /// Return true of this is an input operand that is a matching constraint like | |||
4161 | /// "4". | |||
4162 | bool TargetLowering::AsmOperandInfo::isMatchingInputConstraint() const { | |||
4163 | assert(!ConstraintCode.empty() && "No known constraint!")((!ConstraintCode.empty() && "No known constraint!") ? static_cast<void> (0) : __assert_fail ("!ConstraintCode.empty() && \"No known constraint!\"" , "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 4163, __PRETTY_FUNCTION__)); | |||
4164 | return isdigit(static_cast<unsigned char>(ConstraintCode[0])); | |||
4165 | } | |||
4166 | ||||
4167 | /// If this is an input matching constraint, this method returns the output | |||
4168 | /// operand it matches. | |||
4169 | unsigned TargetLowering::AsmOperandInfo::getMatchedOperand() const { | |||
4170 | assert(!ConstraintCode.empty() && "No known constraint!")((!ConstraintCode.empty() && "No known constraint!") ? static_cast<void> (0) : __assert_fail ("!ConstraintCode.empty() && \"No known constraint!\"" , "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 4170, __PRETTY_FUNCTION__)); | |||
4171 | return atoi(ConstraintCode.c_str()); | |||
4172 | } | |||
4173 | ||||
4174 | /// Split up the constraint string from the inline assembly value into the | |||
4175 | /// specific constraints and their prefixes, and also tie in the associated | |||
4176 | /// operand values. | |||
4177 | /// If this returns an empty vector, and if the constraint string itself | |||
4178 | /// isn't empty, there was an error parsing. | |||
4179 | TargetLowering::AsmOperandInfoVector | |||
4180 | TargetLowering::ParseConstraints(const DataLayout &DL, | |||
4181 | const TargetRegisterInfo *TRI, | |||
4182 | ImmutableCallSite CS) const { | |||
4183 | /// Information about all of the constraints. | |||
4184 | AsmOperandInfoVector ConstraintOperands; | |||
4185 | const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue()); | |||
4186 | unsigned maCount = 0; // Largest number of multiple alternative constraints. | |||
4187 | ||||
4188 | // Do a prepass over the constraints, canonicalizing them, and building up the | |||
4189 | // ConstraintOperands list. | |||
4190 | unsigned ArgNo = 0; // ArgNo - The argument of the CallInst. | |||
4191 | unsigned ResNo = 0; // ResNo - The result number of the next output. | |||
4192 | ||||
4193 | for (InlineAsm::ConstraintInfo &CI : IA->ParseConstraints()) { | |||
4194 | ConstraintOperands.emplace_back(std::move(CI)); | |||
4195 | AsmOperandInfo &OpInfo = ConstraintOperands.back(); | |||
4196 | ||||
4197 | // Update multiple alternative constraint count. | |||
4198 | if (OpInfo.multipleAlternatives.size() > maCount) | |||
4199 | maCount = OpInfo.multipleAlternatives.size(); | |||
4200 | ||||
4201 | OpInfo.ConstraintVT = MVT::Other; | |||
4202 | ||||
4203 | // Compute the value type for each operand. | |||
4204 | switch (OpInfo.Type) { | |||
4205 | case InlineAsm::isOutput: | |||
4206 | // Indirect outputs just consume an argument. | |||
4207 | if (OpInfo.isIndirect) { | |||
4208 | OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++)); | |||
4209 | break; | |||
4210 | } | |||
4211 | ||||
4212 | // The return value of the call is this value. As such, there is no | |||
4213 | // corresponding argument. | |||
4214 | assert(!CS.getType()->isVoidTy() &&((!CS.getType()->isVoidTy() && "Bad inline asm!") ? static_cast<void> (0) : __assert_fail ("!CS.getType()->isVoidTy() && \"Bad inline asm!\"" , "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 4215, __PRETTY_FUNCTION__)) | |||
4215 | "Bad inline asm!")((!CS.getType()->isVoidTy() && "Bad inline asm!") ? static_cast<void> (0) : __assert_fail ("!CS.getType()->isVoidTy() && \"Bad inline asm!\"" , "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 4215, __PRETTY_FUNCTION__)); | |||
4216 | if (StructType *STy = dyn_cast<StructType>(CS.getType())) { | |||
4217 | OpInfo.ConstraintVT = | |||
4218 | getSimpleValueType(DL, STy->getElementType(ResNo)); | |||
4219 | } else { | |||
4220 | assert(ResNo == 0 && "Asm only has one result!")((ResNo == 0 && "Asm only has one result!") ? static_cast <void> (0) : __assert_fail ("ResNo == 0 && \"Asm only has one result!\"" , "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 4220, __PRETTY_FUNCTION__)); | |||
4221 | OpInfo.ConstraintVT = getSimpleValueType(DL, CS.getType()); | |||
4222 | } | |||
4223 | ++ResNo; | |||
4224 | break; | |||
4225 | case InlineAsm::isInput: | |||
4226 | OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++)); | |||
4227 | break; | |||
4228 | case InlineAsm::isClobber: | |||
4229 | // Nothing to do. | |||
4230 | break; | |||
4231 | } | |||
4232 | ||||
4233 | if (OpInfo.CallOperandVal) { | |||
4234 | llvm::Type *OpTy = OpInfo.CallOperandVal->getType(); | |||
4235 | if (OpInfo.isIndirect) { | |||
4236 | llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy); | |||
4237 | if (!PtrTy) | |||
4238 | report_fatal_error("Indirect operand for inline asm not a pointer!"); | |||
4239 | OpTy = PtrTy->getElementType(); | |||
4240 | } | |||
4241 | ||||
4242 | // Look for vector wrapped in a struct. e.g. { <16 x i8> }. | |||
4243 | if (StructType *STy = dyn_cast<StructType>(OpTy)) | |||
4244 | if (STy->getNumElements() == 1) | |||
4245 | OpTy = STy->getElementType(0); | |||
4246 | ||||
4247 | // If OpTy is not a single value, it may be a struct/union that we | |||
4248 | // can tile with integers. | |||
4249 | if (!OpTy->isSingleValueType() && OpTy->isSized()) { | |||
4250 | unsigned BitSize = DL.getTypeSizeInBits(OpTy); | |||
4251 | switch (BitSize) { | |||
4252 | default: break; | |||
4253 | case 1: | |||
4254 | case 8: | |||
4255 | case 16: | |||
4256 | case 32: | |||
4257 | case 64: | |||
4258 | case 128: | |||
4259 | OpInfo.ConstraintVT = | |||
4260 | MVT::getVT(IntegerType::get(OpTy->getContext(), BitSize), true); | |||
4261 | break; | |||
4262 | } | |||
4263 | } else if (PointerType *PT = dyn_cast<PointerType>(OpTy)) { | |||
4264 | unsigned PtrSize = DL.getPointerSizeInBits(PT->getAddressSpace()); | |||
4265 | OpInfo.ConstraintVT = MVT::getIntegerVT(PtrSize); | |||
4266 | } else { | |||
4267 | OpInfo.ConstraintVT = MVT::getVT(OpTy, true); | |||
4268 | } | |||
4269 | } | |||
4270 | } | |||
4271 | ||||
4272 | // If we have multiple alternative constraints, select the best alternative. | |||
4273 | if (!ConstraintOperands.empty()) { | |||
4274 | if (maCount) { | |||
4275 | unsigned bestMAIndex = 0; | |||
4276 | int bestWeight = -1; | |||
4277 | // weight: -1 = invalid match, and 0 = so-so match to 5 = good match. | |||
4278 | int weight = -1; | |||
4279 | unsigned maIndex; | |||
4280 | // Compute the sums of the weights for each alternative, keeping track | |||
4281 | // of the best (highest weight) one so far. | |||
4282 | for (maIndex = 0; maIndex < maCount; ++maIndex) { | |||
4283 | int weightSum = 0; | |||
4284 | for (unsigned cIndex = 0, eIndex = ConstraintOperands.size(); | |||
4285 | cIndex != eIndex; ++cIndex) { | |||
4286 | AsmOperandInfo &OpInfo = ConstraintOperands[cIndex]; | |||
4287 | if (OpInfo.Type == InlineAsm::isClobber) | |||
4288 | continue; | |||
4289 | ||||
4290 | // If this is an output operand with a matching input operand, | |||
4291 | // look up the matching input. If their types mismatch, e.g. one | |||
4292 | // is an integer, the other is floating point, or their sizes are | |||
4293 | // different, flag it as an maCantMatch. | |||
4294 | if (OpInfo.hasMatchingInput()) { | |||
4295 | AsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput]; | |||
4296 | if (OpInfo.ConstraintVT != Input.ConstraintVT) { | |||
4297 | if ((OpInfo.ConstraintVT.isInteger() != | |||
4298 | Input.ConstraintVT.isInteger()) || | |||
4299 | (OpInfo.ConstraintVT.getSizeInBits() != | |||
4300 | Input.ConstraintVT.getSizeInBits())) { | |||
4301 | weightSum = -1; // Can't match. | |||
4302 | break; | |||
4303 | } | |||
4304 | } | |||
4305 | } | |||
4306 | weight = getMultipleConstraintMatchWeight(OpInfo, maIndex); | |||
4307 | if (weight == -1) { | |||
4308 | weightSum = -1; | |||
4309 | break; | |||
4310 | } | |||
4311 | weightSum += weight; | |||
4312 | } | |||
4313 | // Update best. | |||
4314 | if (weightSum > bestWeight) { | |||
4315 | bestWeight = weightSum; | |||
4316 | bestMAIndex = maIndex; | |||
4317 | } | |||
4318 | } | |||
4319 | ||||
4320 | // Now select chosen alternative in each constraint. | |||
4321 | for (unsigned cIndex = 0, eIndex = ConstraintOperands.size(); | |||
4322 | cIndex != eIndex; ++cIndex) { | |||
4323 | AsmOperandInfo &cInfo = ConstraintOperands[cIndex]; | |||
4324 | if (cInfo.Type == InlineAsm::isClobber) | |||
4325 | continue; | |||
4326 | cInfo.selectAlternative(bestMAIndex); | |||
4327 | } | |||
4328 | } | |||
4329 | } | |||
4330 | ||||
4331 | // Check and hook up tied operands, choose constraint code to use. | |||
4332 | for (unsigned cIndex = 0, eIndex = ConstraintOperands.size(); | |||
4333 | cIndex != eIndex; ++cIndex) { | |||
4334 | AsmOperandInfo &OpInfo = ConstraintOperands[cIndex]; | |||
4335 | ||||
4336 | // If this is an output operand with a matching input operand, look up the | |||
4337 | // matching input. If their types mismatch, e.g. one is an integer, the | |||
4338 | // other is floating point, or their sizes are different, flag it as an | |||
4339 | // error. | |||
4340 | if (OpInfo.hasMatchingInput()) { | |||
4341 | AsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput]; | |||
4342 | ||||
4343 | if (OpInfo.ConstraintVT != Input.ConstraintVT) { | |||
4344 | std::pair<unsigned, const TargetRegisterClass *> MatchRC = | |||
4345 | getRegForInlineAsmConstraint(TRI, OpInfo.ConstraintCode, | |||
4346 | OpInfo.ConstraintVT); | |||
4347 | std::pair<unsigned, const TargetRegisterClass *> InputRC = | |||
4348 | getRegForInlineAsmConstraint(TRI, Input.ConstraintCode, | |||
4349 | Input.ConstraintVT); | |||
4350 | if ((OpInfo.ConstraintVT.isInteger() != | |||
4351 | Input.ConstraintVT.isInteger()) || | |||
4352 | (MatchRC.second != InputRC.second)) { | |||
4353 | report_fatal_error("Unsupported asm: input constraint" | |||
4354 | " with a matching output constraint of" | |||
4355 | " incompatible type!"); | |||
4356 | } | |||
4357 | } | |||
4358 | } | |||
4359 | } | |||
4360 | ||||
4361 | return ConstraintOperands; | |||
4362 | } | |||
4363 | ||||
4364 | /// Return an integer indicating how general CT is. | |||
4365 | static unsigned getConstraintGenerality(TargetLowering::ConstraintType CT) { | |||
4366 | switch (CT) { | |||
4367 | case TargetLowering::C_Immediate: | |||
4368 | case TargetLowering::C_Other: | |||
4369 | case TargetLowering::C_Unknown: | |||
4370 | return 0; | |||
4371 | case TargetLowering::C_Register: | |||
4372 | return 1; | |||
4373 | case TargetLowering::C_RegisterClass: | |||
4374 | return 2; | |||
4375 | case TargetLowering::C_Memory: | |||
4376 | return 3; | |||
4377 | } | |||
4378 | llvm_unreachable("Invalid constraint type")::llvm::llvm_unreachable_internal("Invalid constraint type", "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 4378); | |||
4379 | } | |||
4380 | ||||
4381 | /// Examine constraint type and operand type and determine a weight value. | |||
4382 | /// This object must already have been set up with the operand type | |||
4383 | /// and the current alternative constraint selected. | |||
4384 | TargetLowering::ConstraintWeight | |||
4385 | TargetLowering::getMultipleConstraintMatchWeight( | |||
4386 | AsmOperandInfo &info, int maIndex) const { | |||
4387 | InlineAsm::ConstraintCodeVector *rCodes; | |||
4388 | if (maIndex >= (int)info.multipleAlternatives.size()) | |||
4389 | rCodes = &info.Codes; | |||
4390 | else | |||
4391 | rCodes = &info.multipleAlternatives[maIndex].Codes; | |||
4392 | ConstraintWeight BestWeight = CW_Invalid; | |||
4393 | ||||
4394 | // Loop over the options, keeping track of the most general one. | |||
4395 | for (unsigned i = 0, e = rCodes->size(); i != e; ++i) { | |||
4396 | ConstraintWeight weight = | |||
4397 | getSingleConstraintMatchWeight(info, (*rCodes)[i].c_str()); | |||
4398 | if (weight > BestWeight) | |||
4399 | BestWeight = weight; | |||
4400 | } | |||
4401 | ||||
4402 | return BestWeight; | |||
4403 | } | |||
4404 | ||||
4405 | /// Examine constraint type and operand type and determine a weight value. | |||
4406 | /// This object must already have been set up with the operand type | |||
4407 | /// and the current alternative constraint selected. | |||
4408 | TargetLowering::ConstraintWeight | |||
4409 | TargetLowering::getSingleConstraintMatchWeight( | |||
4410 | AsmOperandInfo &info, const char *constraint) const { | |||
4411 | ConstraintWeight weight = CW_Invalid; | |||
4412 | Value *CallOperandVal = info.CallOperandVal; | |||
4413 | // If we don't have a value, we can't do a match, | |||
4414 | // but allow it at the lowest weight. | |||
4415 | if (!CallOperandVal) | |||
4416 | return CW_Default; | |||
4417 | // Look at the constraint type. | |||
4418 | switch (*constraint) { | |||
4419 | case 'i': // immediate integer. | |||
4420 | case 'n': // immediate integer with a known value. | |||
4421 | if (isa<ConstantInt>(CallOperandVal)) | |||
4422 | weight = CW_Constant; | |||
4423 | break; | |||
4424 | case 's': // non-explicit intregal immediate. | |||
4425 | if (isa<GlobalValue>(CallOperandVal)) | |||
4426 | weight = CW_Constant; | |||
4427 | break; | |||
4428 | case 'E': // immediate float if host format. | |||
4429 | case 'F': // immediate float. | |||
4430 | if (isa<ConstantFP>(CallOperandVal)) | |||
4431 | weight = CW_Constant; | |||
4432 | break; | |||
4433 | case '<': // memory operand with autodecrement. | |||
4434 | case '>': // memory operand with autoincrement. | |||
4435 | case 'm': // memory operand. | |||
4436 | case 'o': // offsettable memory operand | |||
4437 | case 'V': // non-offsettable memory operand | |||
4438 | weight = CW_Memory; | |||
4439 | break; | |||
4440 | case 'r': // general register. | |||
4441 | case 'g': // general register, memory operand or immediate integer. | |||
4442 | // note: Clang converts "g" to "imr". | |||
4443 | if (CallOperandVal->getType()->isIntegerTy()) | |||
4444 | weight = CW_Register; | |||
4445 | break; | |||
4446 | case 'X': // any operand. | |||
4447 | default: | |||
4448 | weight = CW_Default; | |||
4449 | break; | |||
4450 | } | |||
4451 | return weight; | |||
4452 | } | |||
4453 | ||||
4454 | /// If there are multiple different constraints that we could pick for this | |||
4455 | /// operand (e.g. "imr") try to pick the 'best' one. | |||
4456 | /// This is somewhat tricky: constraints fall into four classes: | |||
4457 | /// Other -> immediates and magic values | |||
4458 | /// Register -> one specific register | |||
4459 | /// RegisterClass -> a group of regs | |||
4460 | /// Memory -> memory | |||
4461 | /// Ideally, we would pick the most specific constraint possible: if we have | |||
4462 | /// something that fits into a register, we would pick it. The problem here | |||
4463 | /// is that if we have something that could either be in a register or in | |||
4464 | /// memory that use of the register could cause selection of *other* | |||
4465 | /// operands to fail: they might only succeed if we pick memory. Because of | |||
4466 | /// this the heuristic we use is: | |||
4467 | /// | |||
4468 | /// 1) If there is an 'other' constraint, and if the operand is valid for | |||
4469 | /// that constraint, use it. This makes us take advantage of 'i' | |||
4470 | /// constraints when available. | |||
4471 | /// 2) Otherwise, pick the most general constraint present. This prefers | |||
4472 | /// 'm' over 'r', for example. | |||
4473 | /// | |||
4474 | static void ChooseConstraint(TargetLowering::AsmOperandInfo &OpInfo, | |||
4475 | const TargetLowering &TLI, | |||
4476 | SDValue Op, SelectionDAG *DAG) { | |||
4477 | assert(OpInfo.Codes.size() > 1 && "Doesn't have multiple constraint options")((OpInfo.Codes.size() > 1 && "Doesn't have multiple constraint options" ) ? static_cast<void> (0) : __assert_fail ("OpInfo.Codes.size() > 1 && \"Doesn't have multiple constraint options\"" , "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 4477, __PRETTY_FUNCTION__)); | |||
4478 | unsigned BestIdx = 0; | |||
4479 | TargetLowering::ConstraintType BestType = TargetLowering::C_Unknown; | |||
4480 | int BestGenerality = -1; | |||
4481 | ||||
4482 | // Loop over the options, keeping track of the most general one. | |||
4483 | for (unsigned i = 0, e = OpInfo.Codes.size(); i != e; ++i) { | |||
4484 | TargetLowering::ConstraintType CType = | |||
4485 | TLI.getConstraintType(OpInfo.Codes[i]); | |||
4486 | ||||
4487 | // If this is an 'other' or 'immediate' constraint, see if the operand is | |||
4488 | // valid for it. For example, on X86 we might have an 'rI' constraint. If | |||
4489 | // the operand is an integer in the range [0..31] we want to use I (saving a | |||
4490 | // load of a register), otherwise we must use 'r'. | |||
4491 | if ((CType == TargetLowering::C_Other || | |||
4492 | CType == TargetLowering::C_Immediate) && Op.getNode()) { | |||
4493 | assert(OpInfo.Codes[i].size() == 1 &&((OpInfo.Codes[i].size() == 1 && "Unhandled multi-letter 'other' constraint" ) ? static_cast<void> (0) : __assert_fail ("OpInfo.Codes[i].size() == 1 && \"Unhandled multi-letter 'other' constraint\"" , "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 4494, __PRETTY_FUNCTION__)) | |||
4494 | "Unhandled multi-letter 'other' constraint")((OpInfo.Codes[i].size() == 1 && "Unhandled multi-letter 'other' constraint" ) ? static_cast<void> (0) : __assert_fail ("OpInfo.Codes[i].size() == 1 && \"Unhandled multi-letter 'other' constraint\"" , "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 4494, __PRETTY_FUNCTION__)); | |||
4495 | std::vector<SDValue> ResultOps; | |||
4496 | TLI.LowerAsmOperandForConstraint(Op, OpInfo.Codes[i], | |||
4497 | ResultOps, *DAG); | |||
4498 | if (!ResultOps.empty()) { | |||
4499 | BestType = CType; | |||
4500 | BestIdx = i; | |||
4501 | break; | |||
4502 | } | |||
4503 | } | |||
4504 | ||||
4505 | // Things with matching constraints can only be registers, per gcc | |||
4506 | // documentation. This mainly affects "g" constraints. | |||
4507 | if (CType == TargetLowering::C_Memory && OpInfo.hasMatchingInput()) | |||
4508 | continue; | |||
4509 | ||||
4510 | // This constraint letter is more general than the previous one, use it. | |||
4511 | int Generality = getConstraintGenerality(CType); | |||
4512 | if (Generality > BestGenerality) { | |||
4513 | BestType = CType; | |||
4514 | BestIdx = i; | |||
4515 | BestGenerality = Generality; | |||
4516 | } | |||
4517 | } | |||
4518 | ||||
4519 | OpInfo.ConstraintCode = OpInfo.Codes[BestIdx]; | |||
4520 | OpInfo.ConstraintType = BestType; | |||
4521 | } | |||
4522 | ||||
4523 | /// Determines the constraint code and constraint type to use for the specific | |||
4524 | /// AsmOperandInfo, setting OpInfo.ConstraintCode and OpInfo.ConstraintType. | |||
4525 | void TargetLowering::ComputeConstraintToUse(AsmOperandInfo &OpInfo, | |||
4526 | SDValue Op, | |||
4527 | SelectionDAG *DAG) const { | |||
4528 | assert(!OpInfo.Codes.empty() && "Must have at least one constraint")((!OpInfo.Codes.empty() && "Must have at least one constraint" ) ? static_cast<void> (0) : __assert_fail ("!OpInfo.Codes.empty() && \"Must have at least one constraint\"" , "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 4528, __PRETTY_FUNCTION__)); | |||
4529 | ||||
4530 | // Single-letter constraints ('r') are very common. | |||
4531 | if (OpInfo.Codes.size() == 1) { | |||
4532 | OpInfo.ConstraintCode = OpInfo.Codes[0]; | |||
4533 | OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode); | |||
4534 | } else { | |||
4535 | ChooseConstraint(OpInfo, *this, Op, DAG); | |||
4536 | } | |||
4537 | ||||
4538 | // 'X' matches anything. | |||
4539 | if (OpInfo.ConstraintCode == "X" && OpInfo.CallOperandVal) { | |||
4540 | // Labels and constants are handled elsewhere ('X' is the only thing | |||
4541 | // that matches labels). For Functions, the type here is the type of | |||
4542 | // the result, which is not what we want to look at; leave them alone. | |||
4543 | Value *v = OpInfo.CallOperandVal; | |||
4544 | if (isa<BasicBlock>(v) || isa<ConstantInt>(v) || isa<Function>(v)) { | |||
4545 | OpInfo.CallOperandVal = v; | |||
4546 | return; | |||
4547 | } | |||
4548 | ||||
4549 | if (Op.getNode() && Op.getOpcode() == ISD::TargetBlockAddress) | |||
4550 | return; | |||
4551 | ||||
4552 | // Otherwise, try to resolve it to something we know about by looking at | |||
4553 | // the actual operand type. | |||
4554 | if (const char *Repl = LowerXConstraint(OpInfo.ConstraintVT)) { | |||
4555 | OpInfo.ConstraintCode = Repl; | |||
4556 | OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode); | |||
4557 | } | |||
4558 | } | |||
4559 | } | |||
4560 | ||||
4561 | /// Given an exact SDIV by a constant, create a multiplication | |||
4562 | /// with the multiplicative inverse of the constant. | |||
4563 | static SDValue BuildExactSDIV(const TargetLowering &TLI, SDNode *N, | |||
4564 | const SDLoc &dl, SelectionDAG &DAG, | |||
4565 | SmallVectorImpl<SDNode *> &Created) { | |||
4566 | SDValue Op0 = N->getOperand(0); | |||
4567 | SDValue Op1 = N->getOperand(1); | |||
4568 | EVT VT = N->getValueType(0); | |||
4569 | EVT SVT = VT.getScalarType(); | |||
4570 | EVT ShVT = TLI.getShiftAmountTy(VT, DAG.getDataLayout()); | |||
4571 | EVT ShSVT = ShVT.getScalarType(); | |||
4572 | ||||
4573 | bool UseSRA = false; | |||
4574 | SmallVector<SDValue, 16> Shifts, Factors; | |||
4575 | ||||
4576 | auto BuildSDIVPattern = [&](ConstantSDNode *C) { | |||
4577 | if (C->isNullValue()) | |||
4578 | return false; | |||
4579 | APInt Divisor = C->getAPIntValue(); | |||
4580 | unsigned Shift = Divisor.countTrailingZeros(); | |||
4581 | if (Shift) { | |||
4582 | Divisor.ashrInPlace(Shift); | |||
4583 | UseSRA = true; | |||
4584 | } | |||
4585 | // Calculate the multiplicative inverse, using Newton's method. | |||
4586 | APInt t; | |||
4587 | APInt Factor = Divisor; | |||
4588 | while ((t = Divisor * Factor) != 1) | |||
4589 | Factor *= APInt(Divisor.getBitWidth(), 2) - t; | |||
4590 | Shifts.push_back(DAG.getConstant(Shift, dl, ShSVT)); | |||
4591 | Factors.push_back(DAG.getConstant(Factor, dl, SVT)); | |||
4592 | return true; | |||
4593 | }; | |||
4594 | ||||
4595 | // Collect all magic values from the build vector. | |||
4596 | if (!ISD::matchUnaryPredicate(Op1, BuildSDIVPattern)) | |||
4597 | return SDValue(); | |||
4598 | ||||
4599 | SDValue Shift, Factor; | |||
4600 | if (VT.isVector()) { | |||
4601 | Shift = DAG.getBuildVector(ShVT, dl, Shifts); | |||
4602 | Factor = DAG.getBuildVector(VT, dl, Factors); | |||
4603 | } else { | |||
4604 | Shift = Shifts[0]; | |||
4605 | Factor = Factors[0]; | |||
4606 | } | |||
4607 | ||||
4608 | SDValue Res = Op0; | |||
4609 | ||||
4610 | // Shift the value upfront if it is even, so the LSB is one. | |||
4611 | if (UseSRA) { | |||
4612 | // TODO: For UDIV use SRL instead of SRA. | |||
4613 | SDNodeFlags Flags; | |||
4614 | Flags.setExact(true); | |||
4615 | Res = DAG.getNode(ISD::SRA, dl, VT, Res, Shift, Flags); | |||
4616 | Created.push_back(Res.getNode()); | |||
4617 | } | |||
4618 | ||||
4619 | return DAG.getNode(ISD::MUL, dl, VT, Res, Factor); | |||
4620 | } | |||
4621 | ||||
4622 | SDValue TargetLowering::BuildSDIVPow2(SDNode *N, const APInt &Divisor, | |||
4623 | SelectionDAG &DAG, | |||
4624 | SmallVectorImpl<SDNode *> &Created) const { | |||
4625 | AttributeList Attr = DAG.getMachineFunction().getFunction().getAttributes(); | |||
4626 | const TargetLowering &TLI = DAG.getTargetLoweringInfo(); | |||
4627 | if (TLI.isIntDivCheap(N->getValueType(0), Attr)) | |||
4628 | return SDValue(N, 0); // Lower SDIV as SDIV | |||
4629 | return SDValue(); | |||
4630 | } | |||
4631 | ||||
4632 | /// Given an ISD::SDIV node expressing a divide by constant, | |||
4633 | /// return a DAG expression to select that will generate the same value by | |||
4634 | /// multiplying by a magic number. | |||
4635 | /// Ref: "Hacker's Delight" or "The PowerPC Compiler Writer's Guide". | |||
4636 | SDValue TargetLowering::BuildSDIV(SDNode *N, SelectionDAG &DAG, | |||
4637 | bool IsAfterLegalization, | |||
4638 | SmallVectorImpl<SDNode *> &Created) const { | |||
4639 | SDLoc dl(N); | |||
4640 | EVT VT = N->getValueType(0); | |||
4641 | EVT SVT = VT.getScalarType(); | |||
4642 | EVT ShVT = getShiftAmountTy(VT, DAG.getDataLayout()); | |||
4643 | EVT ShSVT = ShVT.getScalarType(); | |||
4644 | unsigned EltBits = VT.getScalarSizeInBits(); | |||
4645 | ||||
4646 | // Check to see if we can do this. | |||
4647 | // FIXME: We should be more aggressive here. | |||
4648 | if (!isTypeLegal(VT)) | |||
4649 | return SDValue(); | |||
4650 | ||||
4651 | // If the sdiv has an 'exact' bit we can use a simpler lowering. | |||
4652 | if (N->getFlags().hasExact()) | |||
4653 | return BuildExactSDIV(*this, N, dl, DAG, Created); | |||
4654 | ||||
4655 | SmallVector<SDValue, 16> MagicFactors, Factors, Shifts, ShiftMasks; | |||
4656 | ||||
4657 | auto BuildSDIVPattern = [&](ConstantSDNode *C) { | |||
4658 | if (C->isNullValue()) | |||
4659 | return false; | |||
4660 | ||||
4661 | const APInt &Divisor = C->getAPIntValue(); | |||
4662 | APInt::ms magics = Divisor.magic(); | |||
4663 | int NumeratorFactor = 0; | |||
4664 | int ShiftMask = -1; | |||
4665 | ||||
4666 | if (Divisor.isOneValue() || Divisor.isAllOnesValue()) { | |||
4667 | // If d is +1/-1, we just multiply the numerator by +1/-1. | |||
4668 | NumeratorFactor = Divisor.getSExtValue(); | |||
4669 | magics.m = 0; | |||
4670 | magics.s = 0; | |||
4671 | ShiftMask = 0; | |||
4672 | } else if (Divisor.isStrictlyPositive() && magics.m.isNegative()) { | |||
4673 | // If d > 0 and m < 0, add the numerator. | |||
4674 | NumeratorFactor = 1; | |||
4675 | } else if (Divisor.isNegative() && magics.m.isStrictlyPositive()) { | |||
4676 | // If d < 0 and m > 0, subtract the numerator. | |||
4677 | NumeratorFactor = -1; | |||
4678 | } | |||
4679 | ||||
4680 | MagicFactors.push_back(DAG.getConstant(magics.m, dl, SVT)); | |||
4681 | Factors.push_back(DAG.getConstant(NumeratorFactor, dl, SVT)); | |||
4682 | Shifts.push_back(DAG.getConstant(magics.s, dl, ShSVT)); | |||
4683 | ShiftMasks.push_back(DAG.getConstant(ShiftMask, dl, SVT)); | |||
4684 | return true; | |||
4685 | }; | |||
4686 | ||||
4687 | SDValue N0 = N->getOperand(0); | |||
4688 | SDValue N1 = N->getOperand(1); | |||
4689 | ||||
4690 | // Collect the shifts / magic values from each element. | |||
4691 | if (!ISD::matchUnaryPredicate(N1, BuildSDIVPattern)) | |||
4692 | return SDValue(); | |||
4693 | ||||
4694 | SDValue MagicFactor, Factor, Shift, ShiftMask; | |||
4695 | if (VT.isVector()) { | |||
4696 | MagicFactor = DAG.getBuildVector(VT, dl, MagicFactors); | |||
4697 | Factor = DAG.getBuildVector(VT, dl, Factors); | |||
4698 | Shift = DAG.getBuildVector(ShVT, dl, Shifts); | |||
4699 | ShiftMask = DAG.getBuildVector(VT, dl, ShiftMasks); | |||
4700 | } else { | |||
4701 | MagicFactor = MagicFactors[0]; | |||
4702 | Factor = Factors[0]; | |||
4703 | Shift = Shifts[0]; | |||
4704 | ShiftMask = ShiftMasks[0]; | |||
4705 | } | |||
4706 | ||||
4707 | // Multiply the numerator (operand 0) by the magic value. | |||
4708 | // FIXME: We should support doing a MUL in a wider type. | |||
4709 | SDValue Q; | |||
4710 | if (IsAfterLegalization ? isOperationLegal(ISD::MULHS, VT) | |||
4711 | : isOperationLegalOrCustom(ISD::MULHS, VT)) | |||
4712 | Q = DAG.getNode(ISD::MULHS, dl, VT, N0, MagicFactor); | |||
4713 | else if (IsAfterLegalization ? isOperationLegal(ISD::SMUL_LOHI, VT) | |||
4714 | : isOperationLegalOrCustom(ISD::SMUL_LOHI, VT)) { | |||
4715 | SDValue LoHi = | |||
4716 | DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(VT, VT), N0, MagicFactor); | |||
4717 | Q = SDValue(LoHi.getNode(), 1); | |||
4718 | } else | |||
4719 | return SDValue(); // No mulhs or equivalent. | |||
4720 | Created.push_back(Q.getNode()); | |||
4721 | ||||
4722 | // (Optionally) Add/subtract the numerator using Factor. | |||
4723 | Factor = DAG.getNode(ISD::MUL, dl, VT, N0, Factor); | |||
4724 | Created.push_back(Factor.getNode()); | |||
4725 | Q = DAG.getNode(ISD::ADD, dl, VT, Q, Factor); | |||
4726 | Created.push_back(Q.getNode()); | |||
4727 | ||||
4728 | // Shift right algebraic by shift value. | |||
4729 | Q = DAG.getNode(ISD::SRA, dl, VT, Q, Shift); | |||
4730 | Created.push_back(Q.getNode()); | |||
4731 | ||||
4732 | // Extract the sign bit, mask it and add it to the quotient. | |||
4733 | SDValue SignShift = DAG.getConstant(EltBits - 1, dl, ShVT); | |||
4734 | SDValue T = DAG.getNode(ISD::SRL, dl, VT, Q, SignShift); | |||
4735 | Created.push_back(T.getNode()); | |||
4736 | T = DAG.getNode(ISD::AND, dl, VT, T, ShiftMask); | |||
4737 | Created.push_back(T.getNode()); | |||
4738 | return DAG.getNode(ISD::ADD, dl, VT, Q, T); | |||
4739 | } | |||
4740 | ||||
4741 | /// Given an ISD::UDIV node expressing a divide by constant, | |||
4742 | /// return a DAG expression to select that will generate the same value by | |||
4743 | /// multiplying by a magic number. | |||
4744 | /// Ref: "Hacker's Delight" or "The PowerPC Compiler Writer's Guide". | |||
4745 | SDValue TargetLowering::BuildUDIV(SDNode *N, SelectionDAG &DAG, | |||
4746 | bool IsAfterLegalization, | |||
4747 | SmallVectorImpl<SDNode *> &Created) const { | |||
4748 | SDLoc dl(N); | |||
4749 | EVT VT = N->getValueType(0); | |||
4750 | EVT SVT = VT.getScalarType(); | |||
4751 | EVT ShVT = getShiftAmountTy(VT, DAG.getDataLayout()); | |||
4752 | EVT ShSVT = ShVT.getScalarType(); | |||
4753 | unsigned EltBits = VT.getScalarSizeInBits(); | |||
4754 | ||||
4755 | // Check to see if we can do this. | |||
4756 | // FIXME: We should be more aggressive here. | |||
4757 | if (!isTypeLegal(VT)) | |||
4758 | return SDValue(); | |||
4759 | ||||
4760 | bool UseNPQ = false; | |||
4761 | SmallVector<SDValue, 16> PreShifts, PostShifts, MagicFactors, NPQFactors; | |||
4762 | ||||
4763 | auto BuildUDIVPattern = [&](ConstantSDNode *C) { | |||
4764 | if (C->isNullValue()) | |||
4765 | return false; | |||
4766 | // FIXME: We should use a narrower constant when the upper | |||
4767 | // bits are known to be zero. | |||
4768 | APInt Divisor = C->getAPIntValue(); | |||
4769 | APInt::mu magics = Divisor.magicu(); | |||
4770 | unsigned PreShift = 0, PostShift = 0; | |||
4771 | ||||
4772 | // If the divisor is even, we can avoid using the expensive fixup by | |||
4773 | // shifting the divided value upfront. | |||
4774 | if (magics.a != 0 && !Divisor[0]) { | |||
4775 | PreShift = Divisor.countTrailingZeros(); | |||
4776 | // Get magic number for the shifted divisor. | |||
4777 | magics = Divisor.lshr(PreShift).magicu(PreShift); | |||
4778 | assert(magics.a == 0 && "Should use cheap fixup now")((magics.a == 0 && "Should use cheap fixup now") ? static_cast <void> (0) : __assert_fail ("magics.a == 0 && \"Should use cheap fixup now\"" , "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 4778, __PRETTY_FUNCTION__)); | |||
4779 | } | |||
4780 | ||||
4781 | APInt Magic = magics.m; | |||
4782 | ||||
4783 | unsigned SelNPQ; | |||
4784 | if (magics.a == 0 || Divisor.isOneValue()) { | |||
4785 | assert(magics.s < Divisor.getBitWidth() &&((magics.s < Divisor.getBitWidth() && "We shouldn't generate an undefined shift!" ) ? static_cast<void> (0) : __assert_fail ("magics.s < Divisor.getBitWidth() && \"We shouldn't generate an undefined shift!\"" , "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 4786, __PRETTY_FUNCTION__)) | |||
4786 | "We shouldn't generate an undefined shift!")((magics.s < Divisor.getBitWidth() && "We shouldn't generate an undefined shift!" ) ? static_cast<void> (0) : __assert_fail ("magics.s < Divisor.getBitWidth() && \"We shouldn't generate an undefined shift!\"" , "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 4786, __PRETTY_FUNCTION__)); | |||
4787 | PostShift = magics.s; | |||
4788 | SelNPQ = false; | |||
4789 | } else { | |||
4790 | PostShift = magics.s - 1; | |||
4791 | SelNPQ = true; | |||
4792 | } | |||
4793 | ||||
4794 | PreShifts.push_back(DAG.getConstant(PreShift, dl, ShSVT)); | |||
4795 | MagicFactors.push_back(DAG.getConstant(Magic, dl, SVT)); | |||
4796 | NPQFactors.push_back( | |||
4797 | DAG.getConstant(SelNPQ ? APInt::getOneBitSet(EltBits, EltBits - 1) | |||
4798 | : APInt::getNullValue(EltBits), | |||
4799 | dl, SVT)); | |||
4800 | PostShifts.push_back(DAG.getConstant(PostShift, dl, ShSVT)); | |||
4801 | UseNPQ |= SelNPQ; | |||
4802 | return true; | |||
4803 | }; | |||
4804 | ||||
4805 | SDValue N0 = N->getOperand(0); | |||
4806 | SDValue N1 = N->getOperand(1); | |||
4807 | ||||
4808 | // Collect the shifts/magic values from each element. | |||
4809 | if (!ISD::matchUnaryPredicate(N1, BuildUDIVPattern)) | |||
4810 | return SDValue(); | |||
4811 | ||||
4812 | SDValue PreShift, PostShift, MagicFactor, NPQFactor; | |||
4813 | if (VT.isVector()) { | |||
4814 | PreShift = DAG.getBuildVector(ShVT, dl, PreShifts); | |||
4815 | MagicFactor = DAG.getBuildVector(VT, dl, MagicFactors); | |||
4816 | NPQFactor = DAG.getBuildVector(VT, dl, NPQFactors); | |||
4817 | PostShift = DAG.getBuildVector(ShVT, dl, PostShifts); | |||
4818 | } else { | |||
4819 | PreShift = PreShifts[0]; | |||
4820 | MagicFactor = MagicFactors[0]; | |||
4821 | PostShift = PostShifts[0]; | |||
4822 | } | |||
4823 | ||||
4824 | SDValue Q = N0; | |||
4825 | Q = DAG.getNode(ISD::SRL, dl, VT, Q, PreShift); | |||
4826 | Created.push_back(Q.getNode()); | |||
4827 | ||||
4828 | // FIXME: We should support doing a MUL in a wider type. | |||
4829 | auto GetMULHU = [&](SDValue X, SDValue Y) { | |||
4830 | if (IsAfterLegalization ? isOperationLegal(ISD::MULHU, VT) | |||
4831 | : isOperationLegalOrCustom(ISD::MULHU, VT)) | |||
4832 | return DAG.getNode(ISD::MULHU, dl, VT, X, Y); | |||
4833 | if (IsAfterLegalization ? isOperationLegal(ISD::UMUL_LOHI, VT) | |||
4834 | : isOperationLegalOrCustom(ISD::UMUL_LOHI, VT)) { | |||
4835 | SDValue LoHi = | |||
4836 | DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(VT, VT), X, Y); | |||
4837 | return SDValue(LoHi.getNode(), 1); | |||
4838 | } | |||
4839 | return SDValue(); // No mulhu or equivalent | |||
4840 | }; | |||
4841 | ||||
4842 | // Multiply the numerator (operand 0) by the magic value. | |||
4843 | Q = GetMULHU(Q, MagicFactor); | |||
4844 | if (!Q) | |||
4845 | return SDValue(); | |||
4846 | ||||
4847 | Created.push_back(Q.getNode()); | |||
4848 | ||||
4849 | if (UseNPQ) { | |||
4850 | SDValue NPQ = DAG.getNode(ISD::SUB, dl, VT, N0, Q); | |||
4851 | Created.push_back(NPQ.getNode()); | |||
4852 | ||||
4853 | // For vectors we might have a mix of non-NPQ/NPQ paths, so use | |||
4854 | // MULHU to act as a SRL-by-1 for NPQ, else multiply by zero. | |||
4855 | if (VT.isVector()) | |||
4856 | NPQ = GetMULHU(NPQ, NPQFactor); | |||
4857 | else | |||
4858 | NPQ = DAG.getNode(ISD::SRL, dl, VT, NPQ, DAG.getConstant(1, dl, ShVT)); | |||
4859 | ||||
4860 | Created.push_back(NPQ.getNode()); | |||
4861 | ||||
4862 | Q = DAG.getNode(ISD::ADD, dl, VT, NPQ, Q); | |||
4863 | Created.push_back(Q.getNode()); | |||
4864 | } | |||
4865 | ||||
4866 | Q = DAG.getNode(ISD::SRL, dl, VT, Q, PostShift); | |||
4867 | Created.push_back(Q.getNode()); | |||
4868 | ||||
4869 | SDValue One = DAG.getConstant(1, dl, VT); | |||
4870 | SDValue IsOne = DAG.getSetCC(dl, VT, N1, One, ISD::SETEQ); | |||
4871 | return DAG.getSelect(dl, VT, IsOne, N0, Q); | |||
4872 | } | |||
4873 | ||||
4874 | /// If all values in Values that *don't* match the predicate are same 'splat' | |||
4875 | /// value, then replace all values with that splat value. | |||
4876 | /// Else, if AlternativeReplacement was provided, then replace all values that | |||
4877 | /// do match predicate with AlternativeReplacement value. | |||
4878 | static void | |||
4879 | turnVectorIntoSplatVector(MutableArrayRef<SDValue> Values, | |||
4880 | std::function<bool(SDValue)> Predicate, | |||
4881 | SDValue AlternativeReplacement = SDValue()) { | |||
4882 | SDValue Replacement; | |||
4883 | // Is there a value for which the Predicate does *NOT* match? What is it? | |||
4884 | auto SplatValue = llvm::find_if_not(Values, Predicate); | |||
4885 | if (SplatValue != Values.end()) { | |||
4886 | // Does Values consist only of SplatValue's and values matching Predicate? | |||
4887 | if (llvm::all_of(Values, [Predicate, SplatValue](SDValue Value) { | |||
4888 | return Value == *SplatValue || Predicate(Value); | |||
4889 | })) // Then we shall replace values matching predicate with SplatValue. | |||
4890 | Replacement = *SplatValue; | |||
4891 | } | |||
4892 | if (!Replacement) { | |||
4893 | // Oops, we did not find the "baseline" splat value. | |||
4894 | if (!AlternativeReplacement) | |||
4895 | return; // Nothing to do. | |||
4896 | // Let's replace with provided value then. | |||
4897 | Replacement = AlternativeReplacement; | |||
4898 | } | |||
4899 | std::replace_if(Values.begin(), Values.end(), Predicate, Replacement); | |||
4900 | } | |||
4901 | ||||
4902 | /// Given an ISD::UREM used only by an ISD::SETEQ or ISD::SETNE | |||
4903 | /// where the divisor is constant and the comparison target is zero, | |||
4904 | /// return a DAG expression that will generate the same comparison result | |||
4905 | /// using only multiplications, additions and shifts/rotations. | |||
4906 | /// Ref: "Hacker's Delight" 10-17. | |||
4907 | SDValue TargetLowering::buildUREMEqFold(EVT SETCCVT, SDValue REMNode, | |||
4908 | SDValue CompTargetNode, | |||
4909 | ISD::CondCode Cond, | |||
4910 | DAGCombinerInfo &DCI, | |||
4911 | const SDLoc &DL) const { | |||
4912 | SmallVector<SDNode *, 2> Built; | |||
4913 | if (SDValue Folded = prepareUREMEqFold(SETCCVT, REMNode, CompTargetNode, Cond, | |||
4914 | DCI, DL, Built)) { | |||
4915 | for (SDNode *N : Built) | |||
4916 | DCI.AddToWorklist(N); | |||
4917 | return Folded; | |||
4918 | } | |||
4919 | ||||
4920 | return SDValue(); | |||
4921 | } | |||
4922 | ||||
4923 | SDValue | |||
4924 | TargetLowering::prepareUREMEqFold(EVT SETCCVT, SDValue REMNode, | |||
4925 | SDValue CompTargetNode, ISD::CondCode Cond, | |||
4926 | DAGCombinerInfo &DCI, const SDLoc &DL, | |||
4927 | SmallVectorImpl<SDNode *> &Created) const { | |||
4928 | // fold (seteq/ne (urem N, D), 0) -> (setule/ugt (rotr (mul N, P), K), Q) | |||
4929 | // - D must be constant, with D = D0 * 2^K where D0 is odd | |||
4930 | // - P is the multiplicative inverse of D0 modulo 2^W | |||
4931 | // - Q = floor(((2^W) - 1) / D) | |||
4932 | // where W is the width of the common type of N and D. | |||
4933 | assert((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&(((Cond == ISD::SETEQ || Cond == ISD::SETNE) && "Only applicable for (in)equality comparisons." ) ? static_cast<void> (0) : __assert_fail ("(Cond == ISD::SETEQ || Cond == ISD::SETNE) && \"Only applicable for (in)equality comparisons.\"" , "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 4934, __PRETTY_FUNCTION__)) | |||
4934 | "Only applicable for (in)equality comparisons.")(((Cond == ISD::SETEQ || Cond == ISD::SETNE) && "Only applicable for (in)equality comparisons." ) ? static_cast<void> (0) : __assert_fail ("(Cond == ISD::SETEQ || Cond == ISD::SETNE) && \"Only applicable for (in)equality comparisons.\"" , "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 4934, __PRETTY_FUNCTION__)); | |||
4935 | ||||
4936 | SelectionDAG &DAG = DCI.DAG; | |||
4937 | ||||
4938 | EVT VT = REMNode.getValueType(); | |||
4939 | EVT SVT = VT.getScalarType(); | |||
4940 | EVT ShVT = getShiftAmountTy(VT, DAG.getDataLayout()); | |||
4941 | EVT ShSVT = ShVT.getScalarType(); | |||
4942 | ||||
4943 | // If MUL is unavailable, we cannot proceed in any case. | |||
4944 | if (!isOperationLegalOrCustom(ISD::MUL, VT)) | |||
4945 | return SDValue(); | |||
4946 | ||||
4947 | // TODO: Could support comparing with non-zero too. | |||
4948 | ConstantSDNode *CompTarget = isConstOrConstSplat(CompTargetNode); | |||
4949 | if (!CompTarget || !CompTarget->isNullValue()) | |||
4950 | return SDValue(); | |||
4951 | ||||
4952 | bool HadOneDivisor = false; | |||
4953 | bool AllDivisorsAreOnes = true; | |||
4954 | bool HadEvenDivisor = false; | |||
4955 | bool AllDivisorsArePowerOfTwo = true; | |||
4956 | SmallVector<SDValue, 16> PAmts, KAmts, QAmts; | |||
4957 | ||||
4958 | auto BuildUREMPattern = [&](ConstantSDNode *C) { | |||
4959 | // Division by 0 is UB. Leave it to be constant-folded elsewhere. | |||
4960 | if (C->isNullValue()) | |||
4961 | return false; | |||
4962 | ||||
4963 | const APInt &D = C->getAPIntValue(); | |||
4964 | // If all divisors are ones, we will prefer to avoid the fold. | |||
4965 | HadOneDivisor |= D.isOneValue(); | |||
4966 | AllDivisorsAreOnes &= D.isOneValue(); | |||
4967 | ||||
4968 | // Decompose D into D0 * 2^K | |||
4969 | unsigned K = D.countTrailingZeros(); | |||
4970 | assert((!D.isOneValue() || (K == 0)) && "For divisor '1' we won't rotate.")(((!D.isOneValue() || (K == 0)) && "For divisor '1' we won't rotate." ) ? static_cast<void> (0) : __assert_fail ("(!D.isOneValue() || (K == 0)) && \"For divisor '1' we won't rotate.\"" , "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 4970, __PRETTY_FUNCTION__)); | |||
4971 | APInt D0 = D.lshr(K); | |||
4972 | ||||
4973 | // D is even if it has trailing zeros. | |||
4974 | HadEvenDivisor |= (K != 0); | |||
4975 | // D is a power-of-two if D0 is one. | |||
4976 | // If all divisors are power-of-two, we will prefer to avoid the fold. | |||
4977 | AllDivisorsArePowerOfTwo &= D0.isOneValue(); | |||
4978 | ||||
4979 | // P = inv(D0, 2^W) | |||
4980 | // 2^W requires W + 1 bits, so we have to extend and then truncate. | |||
4981 | unsigned W = D.getBitWidth(); | |||
4982 | APInt P = D0.zext(W + 1) | |||
4983 | .multiplicativeInverse(APInt::getSignedMinValue(W + 1)) | |||
4984 | .trunc(W); | |||
4985 | assert(!P.isNullValue() && "No multiplicative inverse!")((!P.isNullValue() && "No multiplicative inverse!") ? static_cast<void> (0) : __assert_fail ("!P.isNullValue() && \"No multiplicative inverse!\"" , "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 4985, __PRETTY_FUNCTION__)); // unreachable | |||
4986 | assert((D0 * P).isOneValue() && "Multiplicative inverse sanity check.")(((D0 * P).isOneValue() && "Multiplicative inverse sanity check." ) ? static_cast<void> (0) : __assert_fail ("(D0 * P).isOneValue() && \"Multiplicative inverse sanity check.\"" , "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 4986, __PRETTY_FUNCTION__)); | |||
4987 | ||||
4988 | // Q = floor((2^W - 1) / D) | |||
4989 | APInt Q = APInt::getAllOnesValue(W).udiv(D); | |||
4990 | ||||
4991 | assert(APInt::getAllOnesValue(ShSVT.getSizeInBits()).ugt(K) &&((APInt::getAllOnesValue(ShSVT.getSizeInBits()).ugt(K) && "We are expecting that K is always less than all-ones for ShSVT" ) ? static_cast<void> (0) : __assert_fail ("APInt::getAllOnesValue(ShSVT.getSizeInBits()).ugt(K) && \"We are expecting that K is always less than all-ones for ShSVT\"" , "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 4992, __PRETTY_FUNCTION__)) | |||
4992 | "We are expecting that K is always less than all-ones for ShSVT")((APInt::getAllOnesValue(ShSVT.getSizeInBits()).ugt(K) && "We are expecting that K is always less than all-ones for ShSVT" ) ? static_cast<void> (0) : __assert_fail ("APInt::getAllOnesValue(ShSVT.getSizeInBits()).ugt(K) && \"We are expecting that K is always less than all-ones for ShSVT\"" , "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 4992, __PRETTY_FUNCTION__)); | |||
4993 | ||||
4994 | // If the divisor is 1 the result can be constant-folded. | |||
4995 | if (D.isOneValue()) { | |||
4996 | // Set P and K amount to a bogus values so we can try to splat them. | |||
4997 | P = 0; | |||
4998 | K = -1; | |||
4999 | assert(Q.isAllOnesValue() &&((Q.isAllOnesValue() && "Expecting all-ones comparison for one divisor" ) ? static_cast<void> (0) : __assert_fail ("Q.isAllOnesValue() && \"Expecting all-ones comparison for one divisor\"" , "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 5000, __PRETTY_FUNCTION__)) | |||
5000 | "Expecting all-ones comparison for one divisor")((Q.isAllOnesValue() && "Expecting all-ones comparison for one divisor" ) ? static_cast<void> (0) : __assert_fail ("Q.isAllOnesValue() && \"Expecting all-ones comparison for one divisor\"" , "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 5000, __PRETTY_FUNCTION__)); | |||
5001 | } | |||
5002 | ||||
5003 | PAmts.push_back(DAG.getConstant(P, DL, SVT)); | |||
5004 | KAmts.push_back( | |||
5005 | DAG.getConstant(APInt(ShSVT.getSizeInBits(), K), DL, ShSVT)); | |||
5006 | QAmts.push_back(DAG.getConstant(Q, DL, SVT)); | |||
5007 | return true; | |||
5008 | }; | |||
5009 | ||||
5010 | SDValue N = REMNode.getOperand(0); | |||
5011 | SDValue D = REMNode.getOperand(1); | |||
5012 | ||||
5013 | // Collect the values from each element. | |||
5014 | if (!ISD::matchUnaryPredicate(D, BuildUREMPattern)) | |||
5015 | return SDValue(); | |||
5016 | ||||
5017 | // If this is a urem by a one, avoid the fold since it can be constant-folded. | |||
5018 | if (AllDivisorsAreOnes) | |||
5019 | return SDValue(); | |||
5020 | ||||
5021 | // If this is a urem by a powers-of-two, avoid the fold since it can be | |||
5022 | // best implemented as a bit test. | |||
5023 | if (AllDivisorsArePowerOfTwo) | |||
5024 | return SDValue(); | |||
5025 | ||||
5026 | SDValue PVal, KVal, QVal; | |||
5027 | if (VT.isVector()) { | |||
5028 | if (HadOneDivisor) { | |||
5029 | // Try to turn PAmts into a splat, since we don't care about the values | |||
5030 | // that are currently '0'. If we can't, just keep '0'`s. | |||
5031 | turnVectorIntoSplatVector(PAmts, isNullConstant); | |||
5032 | // Try to turn KAmts into a splat, since we don't care about the values | |||
5033 | // that are currently '-1'. If we can't, change them to '0'`s. | |||
5034 | turnVectorIntoSplatVector(KAmts, isAllOnesConstant, | |||
5035 | DAG.getConstant(0, DL, ShSVT)); | |||
5036 | } | |||
5037 | ||||
5038 | PVal = DAG.getBuildVector(VT, DL, PAmts); | |||
5039 | KVal = DAG.getBuildVector(ShVT, DL, KAmts); | |||
5040 | QVal = DAG.getBuildVector(VT, DL, QAmts); | |||
5041 | } else { | |||
5042 | PVal = PAmts[0]; | |||
5043 | KVal = KAmts[0]; | |||
5044 | QVal = QAmts[0]; | |||
5045 | } | |||
5046 | ||||
5047 | // (mul N, P) | |||
5048 | SDValue Op0 = DAG.getNode(ISD::MUL, DL, VT, N, PVal); | |||
5049 | Created.push_back(Op0.getNode()); | |||
5050 | ||||
5051 | // Rotate right only if any divisor was even. We avoid rotates for all-odd | |||
5052 | // divisors as a performance improvement, since rotating by 0 is a no-op. | |||
5053 | if (HadEvenDivisor) { | |||
5054 | // We need ROTR to do this. | |||
5055 | if (!isOperationLegalOrCustom(ISD::ROTR, VT)) | |||
5056 | return SDValue(); | |||
5057 | SDNodeFlags Flags; | |||
5058 | Flags.setExact(true); | |||
5059 | // UREM: (rotr (mul N, P), K) | |||
5060 | Op0 = DAG.getNode(ISD::ROTR, DL, VT, Op0, KVal, Flags); | |||
5061 | Created.push_back(Op0.getNode()); | |||
5062 | } | |||
5063 | ||||
5064 | // UREM: (setule/setugt (rotr (mul N, P), K), Q) | |||
5065 | return DAG.getSetCC(DL, SETCCVT, Op0, QVal, | |||
5066 | ((Cond == ISD::SETEQ) ? ISD::SETULE : ISD::SETUGT)); | |||
5067 | } | |||
5068 | ||||
5069 | /// Given an ISD::SREM used only by an ISD::SETEQ or ISD::SETNE | |||
5070 | /// where the divisor is constant and the comparison target is zero, | |||
5071 | /// return a DAG expression that will generate the same comparison result | |||
5072 | /// using only multiplications, additions and shifts/rotations. | |||
5073 | /// Ref: "Hacker's Delight" 10-17. | |||
5074 | SDValue TargetLowering::buildSREMEqFold(EVT SETCCVT, SDValue REMNode, | |||
5075 | SDValue CompTargetNode, | |||
5076 | ISD::CondCode Cond, | |||
5077 | DAGCombinerInfo &DCI, | |||
5078 | const SDLoc &DL) const { | |||
5079 | SmallVector<SDNode *, 7> Built; | |||
5080 | if (SDValue Folded = prepareSREMEqFold(SETCCVT, REMNode, CompTargetNode, Cond, | |||
5081 | DCI, DL, Built)) { | |||
5082 | assert(Built.size() <= 7 && "Max size prediction failed.")((Built.size() <= 7 && "Max size prediction failed." ) ? static_cast<void> (0) : __assert_fail ("Built.size() <= 7 && \"Max size prediction failed.\"" , "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 5082, __PRETTY_FUNCTION__)); | |||
5083 | for (SDNode *N : Built) | |||
5084 | DCI.AddToWorklist(N); | |||
5085 | return Folded; | |||
5086 | } | |||
5087 | ||||
5088 | return SDValue(); | |||
5089 | } | |||
5090 | ||||
5091 | SDValue | |||
5092 | TargetLowering::prepareSREMEqFold(EVT SETCCVT, SDValue REMNode, | |||
5093 | SDValue CompTargetNode, ISD::CondCode Cond, | |||
5094 | DAGCombinerInfo &DCI, const SDLoc &DL, | |||
5095 | SmallVectorImpl<SDNode *> &Created) const { | |||
5096 | // Fold: | |||
5097 | // (seteq/ne (srem N, D), 0) | |||
5098 | // To: | |||
5099 | // (setule/ugt (rotr (add (mul N, P), A), K), Q) | |||
5100 | // | |||
5101 | // - D must be constant, with D = D0 * 2^K where D0 is odd | |||
5102 | // - P is the multiplicative inverse of D0 modulo 2^W | |||
5103 | // - A = bitwiseand(floor((2^(W - 1) - 1) / D0), (-(2^k))) | |||
5104 | // - Q = floor((2 * A) / (2^K)) | |||
5105 | // where W is the width of the common type of N and D. | |||
5106 | assert((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&(((Cond == ISD::SETEQ || Cond == ISD::SETNE) && "Only applicable for (in)equality comparisons." ) ? static_cast<void> (0) : __assert_fail ("(Cond == ISD::SETEQ || Cond == ISD::SETNE) && \"Only applicable for (in)equality comparisons.\"" , "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 5107, __PRETTY_FUNCTION__)) | |||
5107 | "Only applicable for (in)equality comparisons.")(((Cond == ISD::SETEQ || Cond == ISD::SETNE) && "Only applicable for (in)equality comparisons." ) ? static_cast<void> (0) : __assert_fail ("(Cond == ISD::SETEQ || Cond == ISD::SETNE) && \"Only applicable for (in)equality comparisons.\"" , "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 5107, __PRETTY_FUNCTION__)); | |||
5108 | ||||
5109 | SelectionDAG &DAG = DCI.DAG; | |||
5110 | ||||
5111 | EVT VT = REMNode.getValueType(); | |||
5112 | EVT SVT = VT.getScalarType(); | |||
5113 | EVT ShVT = getShiftAmountTy(VT, DAG.getDataLayout()); | |||
5114 | EVT ShSVT = ShVT.getScalarType(); | |||
5115 | ||||
5116 | // If MUL is unavailable, we cannot proceed in any case. | |||
5117 | if (!isOperationLegalOrCustom(ISD::MUL, VT)) | |||
5118 | return SDValue(); | |||
5119 | ||||
5120 | // TODO: Could support comparing with non-zero too. | |||
5121 | ConstantSDNode *CompTarget = isConstOrConstSplat(CompTargetNode); | |||
5122 | if (!CompTarget || !CompTarget->isNullValue()) | |||
5123 | return SDValue(); | |||
5124 | ||||
5125 | bool HadIntMinDivisor = false; | |||
5126 | bool HadOneDivisor = false; | |||
5127 | bool AllDivisorsAreOnes = true; | |||
5128 | bool HadEvenDivisor = false; | |||
5129 | bool NeedToApplyOffset = false; | |||
5130 | bool AllDivisorsArePowerOfTwo = true; | |||
5131 | SmallVector<SDValue, 16> PAmts, AAmts, KAmts, QAmts; | |||
5132 | ||||
5133 | auto BuildSREMPattern = [&](ConstantSDNode *C) { | |||
5134 | // Division by 0 is UB. Leave it to be constant-folded elsewhere. | |||
5135 | if (C->isNullValue()) | |||
| ||||
5136 | return false; | |||
5137 | ||||
5138 | // FIXME: we don't fold `rem %X, -C` to `rem %X, C` in DAGCombine. | |||
5139 | ||||
5140 | // WARNING: this fold is only valid for positive divisors! | |||
5141 | APInt D = C->getAPIntValue(); | |||
5142 | if (D.isNegative()) | |||
5143 | D.negate(); // `rem %X, -C` is equivalent to `rem %X, C` | |||
5144 | ||||
5145 | HadIntMinDivisor |= D.isMinSignedValue(); | |||
5146 | ||||
5147 | // If all divisors are ones, we will prefer to avoid the fold. | |||
5148 | HadOneDivisor |= D.isOneValue(); | |||
5149 | AllDivisorsAreOnes &= D.isOneValue(); | |||
5150 | ||||
5151 | // Decompose D into D0 * 2^K | |||
5152 | unsigned K = D.countTrailingZeros(); | |||
5153 | assert((!D.isOneValue() || (K == 0)) && "For divisor '1' we won't rotate.")(((!D.isOneValue() || (K == 0)) && "For divisor '1' we won't rotate." ) ? static_cast<void> (0) : __assert_fail ("(!D.isOneValue() || (K == 0)) && \"For divisor '1' we won't rotate.\"" , "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 5153, __PRETTY_FUNCTION__)); | |||
5154 | APInt D0 = D.lshr(K); | |||
5155 | ||||
5156 | if (!D.isMinSignedValue()) { | |||
5157 | // D is even if it has trailing zeros; unless it's INT_MIN, in which case | |||
5158 | // we don't care about this lane in this fold, we'll special-handle it. | |||
5159 | HadEvenDivisor |= (K != 0); | |||
5160 | } | |||
5161 | ||||
5162 | // D is a power-of-two if D0 is one. This includes INT_MIN. | |||
5163 | // If all divisors are power-of-two, we will prefer to avoid the fold. | |||
5164 | AllDivisorsArePowerOfTwo &= D0.isOneValue(); | |||
5165 | ||||
5166 | // P = inv(D0, 2^W) | |||
5167 | // 2^W requires W + 1 bits, so we have to extend and then truncate. | |||
5168 | unsigned W = D.getBitWidth(); | |||
5169 | APInt P = D0.zext(W + 1) | |||
5170 | .multiplicativeInverse(APInt::getSignedMinValue(W + 1)) | |||
5171 | .trunc(W); | |||
5172 | assert(!P.isNullValue() && "No multiplicative inverse!")((!P.isNullValue() && "No multiplicative inverse!") ? static_cast<void> (0) : __assert_fail ("!P.isNullValue() && \"No multiplicative inverse!\"" , "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 5172, __PRETTY_FUNCTION__)); // unreachable | |||
5173 | assert((D0 * P).isOneValue() && "Multiplicative inverse sanity check.")(((D0 * P).isOneValue() && "Multiplicative inverse sanity check." ) ? static_cast<void> (0) : __assert_fail ("(D0 * P).isOneValue() && \"Multiplicative inverse sanity check.\"" , "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 5173, __PRETTY_FUNCTION__)); | |||
5174 | ||||
5175 | // A = floor((2^(W - 1) - 1) / D0) & -2^K | |||
5176 | APInt A = APInt::getSignedMaxValue(W).udiv(D0); | |||
5177 | A.clearLowBits(K); | |||
5178 | ||||
5179 | if (!D.isMinSignedValue()) { | |||
5180 | // If divisor INT_MIN, then we don't care about this lane in this fold, | |||
5181 | // we'll special-handle it. | |||
5182 | NeedToApplyOffset |= A != 0; | |||
5183 | } | |||
5184 | ||||
5185 | // Q = floor((2 * A) / (2^K)) | |||
5186 | APInt Q = (2 * A).udiv(APInt::getOneBitSet(W, K)); | |||
5187 | ||||
5188 | assert(APInt::getAllOnesValue(SVT.getSizeInBits()).ugt(A) &&((APInt::getAllOnesValue(SVT.getSizeInBits()).ugt(A) && "We are expecting that A is always less than all-ones for SVT" ) ? static_cast<void> (0) : __assert_fail ("APInt::getAllOnesValue(SVT.getSizeInBits()).ugt(A) && \"We are expecting that A is always less than all-ones for SVT\"" , "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 5189, __PRETTY_FUNCTION__)) | |||
5189 | "We are expecting that A is always less than all-ones for SVT")((APInt::getAllOnesValue(SVT.getSizeInBits()).ugt(A) && "We are expecting that A is always less than all-ones for SVT" ) ? static_cast<void> (0) : __assert_fail ("APInt::getAllOnesValue(SVT.getSizeInBits()).ugt(A) && \"We are expecting that A is always less than all-ones for SVT\"" , "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 5189, __PRETTY_FUNCTION__)); | |||
5190 | assert(APInt::getAllOnesValue(ShSVT.getSizeInBits()).ugt(K) &&((APInt::getAllOnesValue(ShSVT.getSizeInBits()).ugt(K) && "We are expecting that K is always less than all-ones for ShSVT" ) ? static_cast<void> (0) : __assert_fail ("APInt::getAllOnesValue(ShSVT.getSizeInBits()).ugt(K) && \"We are expecting that K is always less than all-ones for ShSVT\"" , "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 5191, __PRETTY_FUNCTION__)) | |||
5191 | "We are expecting that K is always less than all-ones for ShSVT")((APInt::getAllOnesValue(ShSVT.getSizeInBits()).ugt(K) && "We are expecting that K is always less than all-ones for ShSVT" ) ? static_cast<void> (0) : __assert_fail ("APInt::getAllOnesValue(ShSVT.getSizeInBits()).ugt(K) && \"We are expecting that K is always less than all-ones for ShSVT\"" , "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 5191, __PRETTY_FUNCTION__)); | |||
5192 | ||||
5193 | // If the divisor is 1 the result can be constant-folded. Likewise, we | |||
5194 | // don't care about INT_MIN lanes, those can be set to undef if appropriate. | |||
5195 | if (D.isOneValue()) { | |||
5196 | // Set P, A and K to a bogus values so we can try to splat them. | |||
5197 | P = 0; | |||
5198 | A = -1; | |||
5199 | K = -1; | |||
5200 | ||||
5201 | // x ?% 1 == 0 <--> true <--> x u<= -1 | |||
5202 | Q = -1; | |||
5203 | } | |||
5204 | ||||
5205 | PAmts.push_back(DAG.getConstant(P, DL, SVT)); | |||
5206 | AAmts.push_back(DAG.getConstant(A, DL, SVT)); | |||
5207 | KAmts.push_back( | |||
5208 | DAG.getConstant(APInt(ShSVT.getSizeInBits(), K), DL, ShSVT)); | |||
5209 | QAmts.push_back(DAG.getConstant(Q, DL, SVT)); | |||
5210 | return true; | |||
5211 | }; | |||
5212 | ||||
5213 | SDValue N = REMNode.getOperand(0); | |||
5214 | SDValue D = REMNode.getOperand(1); | |||
5215 | ||||
5216 | // Collect the values from each element. | |||
5217 | if (!ISD::matchUnaryPredicate(D, BuildSREMPattern)) | |||
5218 | return SDValue(); | |||
5219 | ||||
5220 | // If this is a srem by a one, avoid the fold since it can be constant-folded. | |||
5221 | if (AllDivisorsAreOnes) | |||
5222 | return SDValue(); | |||
5223 | ||||
5224 | // If this is a srem by a powers-of-two (including INT_MIN), avoid the fold | |||
5225 | // since it can be best implemented as a bit test. | |||
5226 | if (AllDivisorsArePowerOfTwo) | |||
5227 | return SDValue(); | |||
5228 | ||||
5229 | SDValue PVal, AVal, KVal, QVal; | |||
5230 | if (VT.isVector()) { | |||
5231 | if (HadOneDivisor) { | |||
5232 | // Try to turn PAmts into a splat, since we don't care about the values | |||
5233 | // that are currently '0'. If we can't, just keep '0'`s. | |||
5234 | turnVectorIntoSplatVector(PAmts, isNullConstant); | |||
5235 | // Try to turn AAmts into a splat, since we don't care about the | |||
5236 | // values that are currently '-1'. If we can't, change them to '0'`s. | |||
5237 | turnVectorIntoSplatVector(AAmts, isAllOnesConstant, | |||
5238 | DAG.getConstant(0, DL, SVT)); | |||
5239 | // Try to turn KAmts into a splat, since we don't care about the values | |||
5240 | // that are currently '-1'. If we can't, change them to '0'`s. | |||
5241 | turnVectorIntoSplatVector(KAmts, isAllOnesConstant, | |||
5242 | DAG.getConstant(0, DL, ShSVT)); | |||
5243 | } | |||
5244 | ||||
5245 | PVal = DAG.getBuildVector(VT, DL, PAmts); | |||
5246 | AVal = DAG.getBuildVector(VT, DL, AAmts); | |||
5247 | KVal = DAG.getBuildVector(ShVT, DL, KAmts); | |||
5248 | QVal = DAG.getBuildVector(VT, DL, QAmts); | |||
5249 | } else { | |||
5250 | PVal = PAmts[0]; | |||
5251 | AVal = AAmts[0]; | |||
5252 | KVal = KAmts[0]; | |||
5253 | QVal = QAmts[0]; | |||
5254 | } | |||
5255 | ||||
5256 | // (mul N, P) | |||
5257 | SDValue Op0 = DAG.getNode(ISD::MUL, DL, VT, N, PVal); | |||
5258 | Created.push_back(Op0.getNode()); | |||
5259 | ||||
5260 | if (NeedToApplyOffset) { | |||
5261 | // We need ADD to do this. | |||
5262 | if (!isOperationLegalOrCustom(ISD::ADD, VT)) | |||
5263 | return SDValue(); | |||
5264 | ||||
5265 | // (add (mul N, P), A) | |||
5266 | Op0 = DAG.getNode(ISD::ADD, DL, VT, Op0, AVal); | |||
5267 | Created.push_back(Op0.getNode()); | |||
5268 | } | |||
5269 | ||||
5270 | // Rotate right only if any divisor was even. We avoid rotates for all-odd | |||
5271 | // divisors as a performance improvement, since rotating by 0 is a no-op. | |||
5272 | if (HadEvenDivisor) { | |||
5273 | // We need ROTR to do this. | |||
5274 | if (!isOperationLegalOrCustom(ISD::ROTR, VT)) | |||
5275 | return SDValue(); | |||
5276 | SDNodeFlags Flags; | |||
5277 | Flags.setExact(true); | |||
5278 | // SREM: (rotr (add (mul N, P), A), K) | |||
5279 | Op0 = DAG.getNode(ISD::ROTR, DL, VT, Op0, KVal, Flags); | |||
5280 | Created.push_back(Op0.getNode()); | |||
5281 | } | |||
5282 | ||||
5283 | // SREM: (setule/setugt (rotr (add (mul N, P), A), K), Q) | |||
5284 | SDValue Fold = | |||
5285 | DAG.getSetCC(DL, SETCCVT, Op0, QVal, | |||
5286 | ((Cond == ISD::SETEQ) ? ISD::SETULE : ISD::SETUGT)); | |||
5287 | ||||
5288 | // If we didn't have lanes with INT_MIN divisor, then we're done. | |||
5289 | if (!HadIntMinDivisor) | |||
5290 | return Fold; | |||
5291 | ||||
5292 | // That fold is only valid for positive divisors. Which effectively means, | |||
5293 | // it is invalid for INT_MIN divisors. So if we have such a lane, | |||
5294 | // we must fix-up results for said lanes. | |||
5295 | assert(VT.isVector() && "Can/should only get here for vectors.")((VT.isVector() && "Can/should only get here for vectors." ) ? static_cast<void> (0) : __assert_fail ("VT.isVector() && \"Can/should only get here for vectors.\"" , "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 5295, __PRETTY_FUNCTION__)); | |||
5296 | ||||
5297 | if (!isOperationLegalOrCustom(ISD::SETEQ, VT) || | |||
5298 | !isOperationLegalOrCustom(ISD::AND, VT) || | |||
5299 | !isOperationLegalOrCustom(Cond, VT) || | |||
5300 | !isOperationLegalOrCustom(ISD::VSELECT, VT)) | |||
5301 | return SDValue(); | |||
5302 | ||||
5303 | Created.push_back(Fold.getNode()); | |||
5304 | ||||
5305 | SDValue IntMin = DAG.getConstant( | |||
5306 | APInt::getSignedMinValue(SVT.getScalarSizeInBits()), DL, VT); | |||
5307 | SDValue IntMax = DAG.getConstant( | |||
5308 | APInt::getSignedMaxValue(SVT.getScalarSizeInBits()), DL, VT); | |||
5309 | SDValue Zero = | |||
5310 | DAG.getConstant(APInt::getNullValue(SVT.getScalarSizeInBits()), DL, VT); | |||
5311 | ||||
5312 | // Which lanes had INT_MIN divisors? Divisor is constant, so const-folded. | |||
5313 | SDValue DivisorIsIntMin = DAG.getSetCC(DL, SETCCVT, D, IntMin, ISD::SETEQ); | |||
5314 | Created.push_back(DivisorIsIntMin.getNode()); | |||
5315 | ||||
5316 | // (N s% INT_MIN) ==/!= 0 <--> (N & INT_MAX) ==/!= 0 | |||
5317 | SDValue Masked = DAG.getNode(ISD::AND, DL, VT, N, IntMax); | |||
5318 | Created.push_back(Masked.getNode()); | |||
5319 | SDValue MaskedIsZero = DAG.getSetCC(DL, SETCCVT, Masked, Zero, Cond); | |||
5320 | Created.push_back(MaskedIsZero.getNode()); | |||
5321 | ||||
5322 | // To produce final result we need to blend 2 vectors: 'SetCC' and | |||
5323 | // 'MaskedIsZero'. If the divisor for channel was *NOT* INT_MIN, we pick | |||
5324 | // from 'Fold', else pick from 'MaskedIsZero'. Since 'DivisorIsIntMin' is | |||
5325 | // constant-folded, select can get lowered to a shuffle with constant mask. | |||
5326 | SDValue Blended = | |||
5327 | DAG.getNode(ISD::VSELECT, DL, VT, DivisorIsIntMin, MaskedIsZero, Fold); | |||
5328 | ||||
5329 | return Blended; | |||
5330 | } | |||
5331 | ||||
5332 | bool TargetLowering:: | |||
5333 | verifyReturnAddressArgumentIsConstant(SDValue Op, SelectionDAG &DAG) const { | |||
5334 | if (!isa<ConstantSDNode>(Op.getOperand(0))) { | |||
5335 | DAG.getContext()->emitError("argument to '__builtin_return_address' must " | |||
5336 | "be a constant integer"); | |||
5337 | return true; | |||
5338 | } | |||
5339 | ||||
5340 | return false; | |||
5341 | } | |||
5342 | ||||
5343 | char TargetLowering::isNegatibleForFree(SDValue Op, SelectionDAG &DAG, | |||
5344 | bool LegalOperations, bool ForCodeSize, | |||
5345 | unsigned Depth) const { | |||
5346 | // fneg is removable even if it has multiple uses. | |||
5347 | if (Op.getOpcode() == ISD::FNEG) | |||
5348 | return 2; | |||
5349 | ||||
5350 | // Don't allow anything with multiple uses unless we know it is free. | |||
5351 | EVT VT = Op.getValueType(); | |||
5352 | const SDNodeFlags Flags = Op->getFlags(); | |||
5353 | const TargetOptions &Options = DAG.getTarget().Options; | |||
5354 | if (!Op.hasOneUse() && !(Op.getOpcode() == ISD::FP_EXTEND && | |||
5355 | isFPExtFree(VT, Op.getOperand(0).getValueType()))) | |||
5356 | return 0; | |||
5357 | ||||
5358 | // Don't recurse exponentially. | |||
5359 | if (Depth > SelectionDAG::MaxRecursionDepth) | |||
5360 | return 0; | |||
5361 | ||||
5362 | switch (Op.getOpcode()) { | |||
5363 | case ISD::ConstantFP: { | |||
5364 | if (!LegalOperations) | |||
5365 | return 1; | |||
5366 | ||||
5367 | // Don't invert constant FP values after legalization unless the target says | |||
5368 | // the negated constant is legal. | |||
5369 | return isOperationLegal(ISD::ConstantFP, VT) || | |||
5370 | isFPImmLegal(neg(cast<ConstantFPSDNode>(Op)->getValueAPF()), VT, | |||
5371 | ForCodeSize); | |||
5372 | } | |||
5373 | case ISD::BUILD_VECTOR: { | |||
5374 | // Only permit BUILD_VECTOR of constants. | |||
5375 | if (llvm::any_of(Op->op_values(), [&](SDValue N) { | |||
5376 | return !N.isUndef() && !isa<ConstantFPSDNode>(N); | |||
5377 | })) | |||
5378 | return 0; | |||
5379 | if (!LegalOperations) | |||
5380 | return 1; | |||
5381 | if (isOperationLegal(ISD::ConstantFP, VT) && | |||
5382 | isOperationLegal(ISD::BUILD_VECTOR, VT)) | |||
5383 | return 1; | |||
5384 | return llvm::all_of(Op->op_values(), [&](SDValue N) { | |||
5385 | return N.isUndef() || | |||
5386 | isFPImmLegal(neg(cast<ConstantFPSDNode>(N)->getValueAPF()), VT, | |||
5387 | ForCodeSize); | |||
5388 | }); | |||
5389 | } | |||
5390 | case ISD::FADD: | |||
5391 | if (!Options.NoSignedZerosFPMath && !Flags.hasNoSignedZeros()) | |||
5392 | return 0; | |||
5393 | ||||
5394 | // After operation legalization, it might not be legal to create new FSUBs. | |||
5395 | if (LegalOperations && !isOperationLegalOrCustom(ISD::FSUB, VT)) | |||
5396 | return 0; | |||
5397 | ||||
5398 | // fold (fneg (fadd A, B)) -> (fsub (fneg A), B) | |||
5399 | if (char V = isNegatibleForFree(Op.getOperand(0), DAG, LegalOperations, | |||
5400 | ForCodeSize, Depth + 1)) | |||
5401 | return V; | |||
5402 | // fold (fneg (fadd A, B)) -> (fsub (fneg B), A) | |||
5403 | return isNegatibleForFree(Op.getOperand(1), DAG, LegalOperations, | |||
5404 | ForCodeSize, Depth + 1); | |||
5405 | case ISD::FSUB: | |||
5406 | // We can't turn -(A-B) into B-A when we honor signed zeros. | |||
5407 | if (!Options.NoSignedZerosFPMath && !Flags.hasNoSignedZeros()) | |||
5408 | return 0; | |||
5409 | ||||
5410 | // fold (fneg (fsub A, B)) -> (fsub B, A) | |||
5411 | return 1; | |||
5412 | ||||
5413 | case ISD::FMUL: | |||
5414 | case ISD::FDIV: | |||
5415 | // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y) or (fmul X, (fneg Y)) | |||
5416 | if (char V = isNegatibleForFree(Op.getOperand(0), DAG, LegalOperations, | |||
5417 | ForCodeSize, Depth + 1)) | |||
5418 | return V; | |||
5419 | ||||
5420 | // Ignore X * 2.0 because that is expected to be canonicalized to X + X. | |||
5421 | if (auto *C = isConstOrConstSplatFP(Op.getOperand(1))) | |||
5422 | if (C->isExactlyValue(2.0) && Op.getOpcode() == ISD::FMUL) | |||
5423 | return 0; | |||
5424 | ||||
5425 | return isNegatibleForFree(Op.getOperand(1), DAG, LegalOperations, | |||
5426 | ForCodeSize, Depth + 1); | |||
5427 | ||||
5428 | case ISD::FMA: | |||
5429 | case ISD::FMAD: { | |||
5430 | if (!Options.NoSignedZerosFPMath && !Flags.hasNoSignedZeros()) | |||
5431 | return 0; | |||
5432 | ||||
5433 | // fold (fneg (fma X, Y, Z)) -> (fma (fneg X), Y, (fneg Z)) | |||
5434 | // fold (fneg (fma X, Y, Z)) -> (fma X, (fneg Y), (fneg Z)) | |||
5435 | char V2 = isNegatibleForFree(Op.getOperand(2), DAG, LegalOperations, | |||
5436 | ForCodeSize, Depth + 1); | |||
5437 | if (!V2) | |||
5438 | return 0; | |||
5439 | ||||
5440 | // One of Op0/Op1 must be cheaply negatible, then select the cheapest. | |||
5441 | char V0 = isNegatibleForFree(Op.getOperand(0), DAG, LegalOperations, | |||
5442 | ForCodeSize, Depth + 1); | |||
5443 | char V1 = isNegatibleForFree(Op.getOperand(1), DAG, LegalOperations, | |||
5444 | ForCodeSize, Depth + 1); | |||
5445 | char V01 = std::max(V0, V1); | |||
5446 | return V01 ? std::max(V01, V2) : 0; | |||
5447 | } | |||
5448 | ||||
5449 | case ISD::FP_EXTEND: | |||
5450 | case ISD::FP_ROUND: | |||
5451 | case ISD::FSIN: | |||
5452 | return isNegatibleForFree(Op.getOperand(0), DAG, LegalOperations, | |||
5453 | ForCodeSize, Depth + 1); | |||
5454 | } | |||
5455 | ||||
5456 | return 0; | |||
5457 | } | |||
5458 | ||||
5459 | SDValue TargetLowering::getNegatedExpression(SDValue Op, SelectionDAG &DAG, | |||
5460 | bool LegalOperations, | |||
5461 | bool ForCodeSize, | |||
5462 | unsigned Depth) const { | |||
5463 | // fneg is removable even if it has multiple uses. | |||
5464 | if (Op.getOpcode() == ISD::FNEG) | |||
5465 | return Op.getOperand(0); | |||
5466 | ||||
5467 | assert(Depth <= SelectionDAG::MaxRecursionDepth &&((Depth <= SelectionDAG::MaxRecursionDepth && "getNegatedExpression doesn't match isNegatibleForFree" ) ? static_cast<void> (0) : __assert_fail ("Depth <= SelectionDAG::MaxRecursionDepth && \"getNegatedExpression doesn't match isNegatibleForFree\"" , "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 5468, __PRETTY_FUNCTION__)) | |||
5468 | "getNegatedExpression doesn't match isNegatibleForFree")((Depth <= SelectionDAG::MaxRecursionDepth && "getNegatedExpression doesn't match isNegatibleForFree" ) ? static_cast<void> (0) : __assert_fail ("Depth <= SelectionDAG::MaxRecursionDepth && \"getNegatedExpression doesn't match isNegatibleForFree\"" , "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 5468, __PRETTY_FUNCTION__)); | |||
5469 | const SDNodeFlags Flags = Op->getFlags(); | |||
5470 | ||||
5471 | switch (Op.getOpcode()) { | |||
5472 | case ISD::ConstantFP: { | |||
5473 | APFloat V = cast<ConstantFPSDNode>(Op)->getValueAPF(); | |||
5474 | V.changeSign(); | |||
5475 | return DAG.getConstantFP(V, SDLoc(Op), Op.getValueType()); | |||
5476 | } | |||
5477 | case ISD::BUILD_VECTOR: { | |||
5478 | SmallVector<SDValue, 4> Ops; | |||
5479 | for (SDValue C : Op->op_values()) { | |||
5480 | if (C.isUndef()) { | |||
5481 | Ops.push_back(C); | |||
5482 | continue; | |||
5483 | } | |||
5484 | APFloat V = cast<ConstantFPSDNode>(C)->getValueAPF(); | |||
5485 | V.changeSign(); | |||
5486 | Ops.push_back(DAG.getConstantFP(V, SDLoc(Op), C.getValueType())); | |||
5487 | } | |||
5488 | return DAG.getBuildVector(Op.getValueType(), SDLoc(Op), Ops); | |||
5489 | } | |||
5490 | case ISD::FADD: | |||
5491 | assert((DAG.getTarget().Options.NoSignedZerosFPMath ||(((DAG.getTarget().Options.NoSignedZerosFPMath || Flags.hasNoSignedZeros ()) && "Expected NSZ fp-flag") ? static_cast<void> (0) : __assert_fail ("(DAG.getTarget().Options.NoSignedZerosFPMath || Flags.hasNoSignedZeros()) && \"Expected NSZ fp-flag\"" , "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 5493, __PRETTY_FUNCTION__)) | |||
5492 | Flags.hasNoSignedZeros()) &&(((DAG.getTarget().Options.NoSignedZerosFPMath || Flags.hasNoSignedZeros ()) && "Expected NSZ fp-flag") ? static_cast<void> (0) : __assert_fail ("(DAG.getTarget().Options.NoSignedZerosFPMath || Flags.hasNoSignedZeros()) && \"Expected NSZ fp-flag\"" , "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 5493, __PRETTY_FUNCTION__)) | |||
5493 | "Expected NSZ fp-flag")(((DAG.getTarget().Options.NoSignedZerosFPMath || Flags.hasNoSignedZeros ()) && "Expected NSZ fp-flag") ? static_cast<void> (0) : __assert_fail ("(DAG.getTarget().Options.NoSignedZerosFPMath || Flags.hasNoSignedZeros()) && \"Expected NSZ fp-flag\"" , "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 5493, __PRETTY_FUNCTION__)); | |||
5494 | ||||
5495 | // fold (fneg (fadd A, B)) -> (fsub (fneg A), B) | |||
5496 | if (isNegatibleForFree(Op.getOperand(0), DAG, LegalOperations, ForCodeSize, | |||
5497 | Depth + 1)) | |||
5498 | return DAG.getNode(ISD::FSUB, SDLoc(Op), Op.getValueType(), | |||
5499 | getNegatedExpression(Op.getOperand(0), DAG, | |||
5500 | LegalOperations, ForCodeSize, | |||
5501 | Depth + 1), | |||
5502 | Op.getOperand(1), Flags); | |||
5503 | // fold (fneg (fadd A, B)) -> (fsub (fneg B), A) | |||
5504 | return DAG.getNode(ISD::FSUB, SDLoc(Op), Op.getValueType(), | |||
5505 | getNegatedExpression(Op.getOperand(1), DAG, | |||
5506 | LegalOperations, ForCodeSize, | |||
5507 | Depth + 1), | |||
5508 | Op.getOperand(0), Flags); | |||
5509 | case ISD::FSUB: | |||
5510 | // fold (fneg (fsub 0, B)) -> B | |||
5511 | if (ConstantFPSDNode *N0CFP = | |||
5512 | isConstOrConstSplatFP(Op.getOperand(0), /*AllowUndefs*/ true)) | |||
5513 | if (N0CFP->isZero()) | |||
5514 | return Op.getOperand(1); | |||
5515 | ||||
5516 | // fold (fneg (fsub A, B)) -> (fsub B, A) | |||
5517 | return DAG.getNode(ISD::FSUB, SDLoc(Op), Op.getValueType(), | |||
5518 | Op.getOperand(1), Op.getOperand(0), Flags); | |||
5519 | ||||
5520 | case ISD::FMUL: | |||
5521 | case ISD::FDIV: | |||
5522 | // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y) | |||
5523 | if (isNegatibleForFree(Op.getOperand(0), DAG, LegalOperations, ForCodeSize, | |||
5524 | Depth + 1)) | |||
5525 | return DAG.getNode(Op.getOpcode(), SDLoc(Op), Op.getValueType(), | |||
5526 | getNegatedExpression(Op.getOperand(0), DAG, | |||
5527 | LegalOperations, ForCodeSize, | |||
5528 | Depth + 1), | |||
5529 | Op.getOperand(1), Flags); | |||
5530 | ||||
5531 | // fold (fneg (fmul X, Y)) -> (fmul X, (fneg Y)) | |||
5532 | return DAG.getNode( | |||
5533 | Op.getOpcode(), SDLoc(Op), Op.getValueType(), Op.getOperand(0), | |||
5534 | getNegatedExpression(Op.getOperand(1), DAG, LegalOperations, | |||
5535 | ForCodeSize, Depth + 1), | |||
5536 | Flags); | |||
5537 | ||||
5538 | case ISD::FMA: | |||
5539 | case ISD::FMAD: { | |||
5540 | assert((DAG.getTarget().Options.NoSignedZerosFPMath ||(((DAG.getTarget().Options.NoSignedZerosFPMath || Flags.hasNoSignedZeros ()) && "Expected NSZ fp-flag") ? static_cast<void> (0) : __assert_fail ("(DAG.getTarget().Options.NoSignedZerosFPMath || Flags.hasNoSignedZeros()) && \"Expected NSZ fp-flag\"" , "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 5542, __PRETTY_FUNCTION__)) | |||
5541 | Flags.hasNoSignedZeros()) &&(((DAG.getTarget().Options.NoSignedZerosFPMath || Flags.hasNoSignedZeros ()) && "Expected NSZ fp-flag") ? static_cast<void> (0) : __assert_fail ("(DAG.getTarget().Options.NoSignedZerosFPMath || Flags.hasNoSignedZeros()) && \"Expected NSZ fp-flag\"" , "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 5542, __PRETTY_FUNCTION__)) | |||
5542 | "Expected NSZ fp-flag")(((DAG.getTarget().Options.NoSignedZerosFPMath || Flags.hasNoSignedZeros ()) && "Expected NSZ fp-flag") ? static_cast<void> (0) : __assert_fail ("(DAG.getTarget().Options.NoSignedZerosFPMath || Flags.hasNoSignedZeros()) && \"Expected NSZ fp-flag\"" , "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 5542, __PRETTY_FUNCTION__)); | |||
5543 | ||||
5544 | SDValue Neg2 = getNegatedExpression(Op.getOperand(2), DAG, LegalOperations, | |||
5545 | ForCodeSize, Depth + 1); | |||
5546 | ||||
5547 | char V0 = isNegatibleForFree(Op.getOperand(0), DAG, LegalOperations, | |||
5548 | ForCodeSize, Depth + 1); | |||
5549 | char V1 = isNegatibleForFree(Op.getOperand(1), DAG, LegalOperations, | |||
5550 | ForCodeSize, Depth + 1); | |||
5551 | if (V0 >= V1) { | |||
5552 | // fold (fneg (fma X, Y, Z)) -> (fma (fneg X), Y, (fneg Z)) | |||
5553 | SDValue Neg0 = getNegatedExpression( | |||
5554 | Op.getOperand(0), DAG, LegalOperations, ForCodeSize, Depth + 1); | |||
5555 | return DAG.getNode(Op.getOpcode(), SDLoc(Op), Op.getValueType(), Neg0, | |||
5556 | Op.getOperand(1), Neg2, Flags); | |||
5557 | } | |||
5558 | ||||
5559 | // fold (fneg (fma X, Y, Z)) -> (fma X, (fneg Y), (fneg Z)) | |||
5560 | SDValue Neg1 = getNegatedExpression(Op.getOperand(1), DAG, LegalOperations, | |||
5561 | ForCodeSize, Depth + 1); | |||
5562 | return DAG.getNode(Op.getOpcode(), SDLoc(Op), Op.getValueType(), | |||
5563 | Op.getOperand(0), Neg1, Neg2, Flags); | |||
5564 | } | |||
5565 | ||||
5566 | case ISD::FP_EXTEND: | |||
5567 | case ISD::FSIN: | |||
5568 | return DAG.getNode(Op.getOpcode(), SDLoc(Op), Op.getValueType(), | |||
5569 | getNegatedExpression(Op.getOperand(0), DAG, | |||
5570 | LegalOperations, ForCodeSize, | |||
5571 | Depth + 1)); | |||
5572 | case ISD::FP_ROUND: | |||
5573 | return DAG.getNode(ISD::FP_ROUND, SDLoc(Op), Op.getValueType(), | |||
5574 | getNegatedExpression(Op.getOperand(0), DAG, | |||
5575 | LegalOperations, ForCodeSize, | |||
5576 | Depth + 1), | |||
5577 | Op.getOperand(1)); | |||
5578 | } | |||
5579 | ||||
5580 | llvm_unreachable("Unknown code")::llvm::llvm_unreachable_internal("Unknown code", "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 5580); | |||
5581 | } | |||
5582 | ||||
5583 | //===----------------------------------------------------------------------===// | |||
5584 | // Legalization Utilities | |||
5585 | //===----------------------------------------------------------------------===// | |||
5586 | ||||
5587 | bool TargetLowering::expandMUL_LOHI(unsigned Opcode, EVT VT, SDLoc dl, | |||
5588 | SDValue LHS, SDValue RHS, | |||
5589 | SmallVectorImpl<SDValue> &Result, | |||
5590 | EVT HiLoVT, SelectionDAG &DAG, | |||
5591 | MulExpansionKind Kind, SDValue LL, | |||
5592 | SDValue LH, SDValue RL, SDValue RH) const { | |||
5593 | assert(Opcode == ISD::MUL || Opcode == ISD::UMUL_LOHI ||((Opcode == ISD::MUL || Opcode == ISD::UMUL_LOHI || Opcode == ISD::SMUL_LOHI) ? static_cast<void> (0) : __assert_fail ("Opcode == ISD::MUL || Opcode == ISD::UMUL_LOHI || Opcode == ISD::SMUL_LOHI" , "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 5594, __PRETTY_FUNCTION__)) | |||
5594 | Opcode == ISD::SMUL_LOHI)((Opcode == ISD::MUL || Opcode == ISD::UMUL_LOHI || Opcode == ISD::SMUL_LOHI) ? static_cast<void> (0) : __assert_fail ("Opcode == ISD::MUL || Opcode == ISD::UMUL_LOHI || Opcode == ISD::SMUL_LOHI" , "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 5594, __PRETTY_FUNCTION__)); | |||
5595 | ||||
5596 | bool HasMULHS = (Kind == MulExpansionKind::Always) || | |||
5597 | isOperationLegalOrCustom(ISD::MULHS, HiLoVT); | |||
5598 | bool HasMULHU = (Kind == MulExpansionKind::Always) || | |||
5599 | isOperationLegalOrCustom(ISD::MULHU, HiLoVT); | |||
5600 | bool HasSMUL_LOHI = (Kind == MulExpansionKind::Always) || | |||
5601 | isOperationLegalOrCustom(ISD::SMUL_LOHI, HiLoVT); | |||
5602 | bool HasUMUL_LOHI = (Kind == MulExpansionKind::Always) || | |||
5603 | isOperationLegalOrCustom(ISD::UMUL_LOHI, HiLoVT); | |||
5604 | ||||
5605 | if (!HasMULHU && !HasMULHS && !HasUMUL_LOHI && !HasSMUL_LOHI) | |||
5606 | return false; | |||
5607 | ||||
5608 | unsigned OuterBitSize = VT.getScalarSizeInBits(); | |||
5609 | unsigned InnerBitSize = HiLoVT.getScalarSizeInBits(); | |||
5610 | unsigned LHSSB = DAG.ComputeNumSignBits(LHS); | |||
5611 | unsigned RHSSB = DAG.ComputeNumSignBits(RHS); | |||
5612 | ||||
5613 | // LL, LH, RL, and RH must be either all NULL or all set to a value. | |||
5614 | assert((LL.getNode() && LH.getNode() && RL.getNode() && RH.getNode()) ||(((LL.getNode() && LH.getNode() && RL.getNode () && RH.getNode()) || (!LL.getNode() && !LH. getNode() && !RL.getNode() && !RH.getNode())) ? static_cast<void> (0) : __assert_fail ("(LL.getNode() && LH.getNode() && RL.getNode() && RH.getNode()) || (!LL.getNode() && !LH.getNode() && !RL.getNode() && !RH.getNode())" , "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 5615, __PRETTY_FUNCTION__)) | |||
5615 | (!LL.getNode() && !LH.getNode() && !RL.getNode() && !RH.getNode()))(((LL.getNode() && LH.getNode() && RL.getNode () && RH.getNode()) || (!LL.getNode() && !LH. getNode() && !RL.getNode() && !RH.getNode())) ? static_cast<void> (0) : __assert_fail ("(LL.getNode() && LH.getNode() && RL.getNode() && RH.getNode()) || (!LL.getNode() && !LH.getNode() && !RL.getNode() && !RH.getNode())" , "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp" , 5615, __PRETTY_FUNCTION__)); | |||
5616 | ||||
5617 | SDVTList VTs = DAG.getVTList(HiLoVT, HiLoVT); | |||
5618 | auto MakeMUL_LOHI = [&](SDValue L, SDValue R, SDValue &Lo, SDValue &Hi, | |||
5619 | bool Signed) -> bool { | |||
5620 | if ((Signed && HasSMUL_LOHI) || (!Signed && HasUMUL_LOHI)) { | |||
5621 | Lo = DAG.getNode(Signed ? ISD::SMUL_LOHI : ISD::UMUL_LOHI, dl, VTs, L, R); | |||
5622 | Hi = SDValue(Lo.getNode(), 1); | |||
5623 | return true; | |||
5624 | } | |||
5625 | if ((Signed && HasMULHS) || (!Signed && HasMULHU)) { | |||
5626 | Lo = DAG.getNode(ISD::MUL, dl, HiLoVT, L, R); | |||
5627 | Hi = DAG.getNode(Signed ? ISD::MULHS : ISD::MULHU, dl, HiLoVT, L, R); | |||
5628 | return true; | |||
5629 | } | |||
5630 | return false; | |||
5631 | }; | |||
5632 | ||||
5633 | SDValue Lo, Hi; | |||
5634 | ||||
5635 | if (!LL.getNode() && !RL.getNode() && | |||
5636 | isOperationLegalOrCustom(ISD::TRUNCATE, HiLoVT)) { | |||
5637 | LL = DAG.getNode(ISD::TRUNCATE, dl, HiLoVT, LHS); | |||
5638 | RL = DAG.getNode(ISD::TRUNCATE, dl, HiLoVT, RHS); | |||
5639 | } | |||
5640 | ||||
5641 | if (!LL.getNode()) | |||
5642 | return false; | |||
5643 | ||||
5644 | APInt HighMask = APInt::getHighBitsSet(OuterBitSize, InnerBitSize); | |||
5645 | if (DAG.MaskedValueIsZero(LHS, HighMask) && | |||
5646 | DAG.MaskedValueIsZero(RHS, HighMask)) { | |||
5647 | // The inputs are both zero-extended. | |||
5648 | if (MakeMUL_LOHI(LL, RL, Lo, Hi, false)) { | |||
5649 | Result.push_back(Lo); | |||
5650 | Result.push_back(Hi); | |||
5651 | if (Opcode != ISD::MUL) { | |||
5652 | SDValue Zero = DAG.getConstant(0, dl, HiLoVT); | |||
5653 | Result.push_back(Zero); | |||
5654 | Result.push_back(Zero); | |||
5655 | } | |||
5656 | return true; | |||
5657 | } | |||
5658 | } | |||
5659 | ||||
5660 | if (!VT.isVector() && Opcode == ISD::MUL && LHSSB > InnerBitSize && | |||
5661 | RHSSB > InnerBitSize) { | |||
5662 | // The input values are both sign-extended. | |||
5663 | // TODO non-MUL case? | |||
5664 | if (MakeMUL_LOHI(LL, RL, Lo, Hi, true)) { | |||
5665 | Result.push_back(Lo); | |||
5666 | Result.push_back(Hi); | |||
5667 | return true; | |||
5668 | } | |||
5669 | } | |||
5670 | ||||
5671 | unsigned ShiftAmount = OuterBitSize - InnerBitSize; | |||
5672 | EVT ShiftAmountTy = getShiftAmountTy(VT, DAG.getDataLayout()); | |||
5673 | if (APInt::getMaxValue(ShiftAmountTy.getSizeInBits()).ult(ShiftAmount)) { | |||
5674 | // FIXME getShiftAmountTy does not always return a sensible result when VT | |||
5675 | // is an illegal type, and so the type may be too small to fit the shift | |||
5676 | // amount. Override it with i32. The shift will have to be legalized. | |||
5677 | ShiftAmountTy = MVT::i32; | |||
5678 | } | |||
5679 | SDValue Shift = DAG.getConstant(ShiftAmount, dl, ShiftAmountTy); | |||
5680 | ||||
5681 | if (!LH.getNode() && !RH.getNode() && | |||
5682 | isOperationLegalOrCustom(ISD::SRL, VT) && | |||
5683 | isOperationLegalOrCustom(ISD::TRUNCATE, HiLoVT)) { | |||
5684 | LH = DAG.getNode(ISD::SRL, dl, VT, LHS, Shift); | |||
5685 | LH = DAG.getNode(ISD::TRUNCATE, dl, HiLoVT, LH); | |||
5686 | RH = DAG.getNode(ISD::SRL, dl, VT, RHS, Shift); | |||
5687 | RH = DAG.getNode(ISD::TRUNCATE, dl, HiLoVT, RH); | |||
5688 | } | |||
5689 | ||||
5690 | if (!LH.getNode()) | |||
5691 | return false; | |||
5692 | ||||
5693 | if (!MakeMUL_LOHI(LL, RL, Lo, Hi, false)) | |||
5694 | return false; | |||
5695 | ||||
5696 | Result.push_back(Lo); | |||
5697 | ||||
5698 | if (Opcode == ISD::MUL) { | |||
5699 | RH = DAG.getNode(ISD::MUL, dl, HiLoVT, LL, RH); | |||
5700 | LH = DAG.getNode(ISD::MUL, dl, HiLoVT, LH, RL); | |||
5701 | Hi = DAG.getNode(ISD::ADD, dl, HiLoVT, Hi, RH); | |||
5702 | Hi = DAG.getNode(ISD::ADD, dl, HiLoVT, Hi, LH); | |||
5703 | Result.push_back(Hi); | |||
5704 | return true; | |||
5705 | } | |||
5706 | ||||
5707 | // Compute the full width result. | |||
5708 | auto Merge = [&](SDValue Lo, SDValue Hi) -> SDValue { | |||
5709 | Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Lo); | |||
5710 | Hi = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Hi); | |||
5711 | Hi = DAG.getNode(ISD::SHL, dl, VT, Hi, Shift); | |||
5712 | return DAG.getNode(ISD::OR, dl, VT, Lo, Hi); | |||
5713 | }; | |||
5714 | ||||
5715 | SDValue Next = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Hi); | |||
5716 | if (!MakeMUL_LOHI(LL, RH, Lo, Hi, false)) | |||
5717 | return false; | |||
5718 | ||||
5719 | // This is effectively the add part of a multiply-add of half-sized operands, | |||
5720 | // so it cannot overflow. | |||
5721 | Next = DAG.getNode(ISD::ADD, dl, VT, Next, Merge(Lo, Hi)); | |||
5722 | ||||
5723 | if (!MakeMUL_LOHI(LH, RL, Lo, Hi, false)) | |||
5724 | return false; | |||
5725 | ||||
5726 | SDValue Zero = DAG.getConstant(0, dl, HiLoVT); | |||
5727 | EVT BoolType = getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT); | |||
5728 | ||||
5729 | bool UseGlue = (isOperationLegalOrCustom(ISD::ADDC, VT) && | |||
5730 | isOperationLegalOrCustom(ISD::ADDE, VT)); | |||
5731 | if (UseGlue) | |||
5732 | Next = DAG.getNode(ISD::ADDC, dl, DAG.getVTList(VT, MVT::Glue), Next, | |||
5733 | Merge(Lo, Hi)); | |||
5734 | else | |||
5735 | Next = DAG.getNode(ISD::ADDCARRY, dl, DAG.getVTList(VT, BoolType), Next, | |||
5736 | Merge(Lo, Hi), DAG.getConstant(0, dl, BoolType)); | |||
5737 | ||||
5738 | SDValue Carry = Next.getValue(1); | |||
5739 | Result.push_back(DAG.getNode(ISD::TRUNCATE, dl, HiLoVT, Next)); | |||
5740 | Next = DAG.getNode(ISD::SRL, dl, VT, Next, Shift); | |||
5741 | ||||
5742 | if (!MakeMUL_LOHI(LH, RH, Lo, Hi, Opcode == ISD::SMUL_LOHI)) | |||
5743 | return false; | |||
5744 | ||||
5745 | if (UseGlue) | |||
5746 | Hi = DAG.getNode(ISD::ADDE, dl, DAG.getVTList(HiLoVT, MVT::Glue), Hi, Zero, | |||
5747 | Carry); | |||
5748 | else | |||
5749 | Hi = DAG.getNode(ISD::ADDCARRY, dl, DAG.getVTList(HiLoVT, BoolType), Hi, | |||
5750 | Zero, Carry); | |||
5751 | ||||
5752 | Next = DAG.getNode(ISD::ADD, dl, VT, Next, Merge(Lo, Hi)); | |||
5753 | ||||
5754 | if (Opcode == ISD::SMUL_LO |