Bug Summary

File:lib/CodeGen/TargetPassConfig.cpp
Warning:line 1048, column 5
Value stored to 'Ctor' is never read

Annotated Source Code

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clang -cc1 -triple x86_64-pc-linux-gnu -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name TargetPassConfig.cpp -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=cplusplus -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -analyzer-config-compatibility-mode=true -mrelocation-model pic -pic-level 2 -mthread-model posix -fmath-errno -masm-verbose -mconstructor-aliases -munwind-tables -fuse-init-array -target-cpu x86-64 -dwarf-column-info -debugger-tuning=gdb -momit-leaf-frame-pointer -ffunction-sections -fdata-sections -resource-dir /usr/lib/llvm-8/lib/clang/8.0.0 -D _DEBUG -D _GNU_SOURCE -D __STDC_CONSTANT_MACROS -D __STDC_FORMAT_MACROS -D __STDC_LIMIT_MACROS -I /build/llvm-toolchain-snapshot-8~svn350071/build-llvm/lib/CodeGen -I /build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen -I /build/llvm-toolchain-snapshot-8~svn350071/build-llvm/include -I /build/llvm-toolchain-snapshot-8~svn350071/include -U NDEBUG -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/x86_64-linux-gnu/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/x86_64-linux-gnu/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/c++/6.3.0/backward -internal-isystem /usr/include/clang/8.0.0/include/ -internal-isystem /usr/local/include -internal-isystem /usr/lib/llvm-8/lib/clang/8.0.0/include -internal-externc-isystem /usr/include/x86_64-linux-gnu -internal-externc-isystem /include -internal-externc-isystem /usr/include -O2 -Wno-unused-parameter -Wwrite-strings -Wno-missing-field-initializers -Wno-long-long -Wno-maybe-uninitialized -Wno-comment -std=c++11 -fdeprecated-macro -fdebug-compilation-dir /build/llvm-toolchain-snapshot-8~svn350071/build-llvm/lib/CodeGen -fdebug-prefix-map=/build/llvm-toolchain-snapshot-8~svn350071=. -ferror-limit 19 -fmessage-length 0 -fvisibility-inlines-hidden -stack-protector 2 -fobjc-runtime=gcc -fdiagnostics-show-option -vectorize-loops -vectorize-slp -analyzer-output=html -analyzer-config stable-report-filename=true -o /tmp/scan-build-2018-12-27-042839-1215-1 -x c++ /build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/TargetPassConfig.cpp -faddrsig
1//===- TargetPassConfig.cpp - Target independent code generation passes ---===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines interfaces to access the target independent code
11// generation passes provided by the LLVM backend.
12//
13//===---------------------------------------------------------------------===//
14
15#include "llvm/CodeGen/TargetPassConfig.h"
16#include "llvm/ADT/DenseMap.h"
17#include "llvm/ADT/SmallVector.h"
18#include "llvm/ADT/StringRef.h"
19#include "llvm/Analysis/BasicAliasAnalysis.h"
20#include "llvm/Analysis/CFLAndersAliasAnalysis.h"
21#include "llvm/Analysis/CFLSteensAliasAnalysis.h"
22#include "llvm/Analysis/CallGraphSCCPass.h"
23#include "llvm/Analysis/ScopedNoAliasAA.h"
24#include "llvm/Analysis/TargetTransformInfo.h"
25#include "llvm/Analysis/TypeBasedAliasAnalysis.h"
26#include "llvm/CodeGen/MachineFunctionPass.h"
27#include "llvm/CodeGen/MachinePassRegistry.h"
28#include "llvm/CodeGen/Passes.h"
29#include "llvm/CodeGen/RegAllocRegistry.h"
30#include "llvm/IR/IRPrintingPasses.h"
31#include "llvm/IR/LegacyPassManager.h"
32#include "llvm/IR/Verifier.h"
33#include "llvm/MC/MCAsmInfo.h"
34#include "llvm/MC/MCTargetOptions.h"
35#include "llvm/Pass.h"
36#include "llvm/Support/CodeGen.h"
37#include "llvm/Support/CommandLine.h"
38#include "llvm/Support/Compiler.h"
39#include "llvm/Support/Debug.h"
40#include "llvm/Support/ErrorHandling.h"
41#include "llvm/Support/Threading.h"
42#include "llvm/Support/SaveAndRestore.h"
43#include "llvm/Target/TargetMachine.h"
44#include "llvm/Transforms/Scalar.h"
45#include "llvm/Transforms/Utils.h"
46#include "llvm/Transforms/Utils/SymbolRewriter.h"
47#include <cassert>
48#include <string>
49
50using namespace llvm;
51
52cl::opt<bool> EnableIPRA("enable-ipra", cl::init(false), cl::Hidden,
53 cl::desc("Enable interprocedural register allocation "
54 "to reduce load/store at procedure calls."));
55static cl::opt<bool> DisablePostRASched("disable-post-ra", cl::Hidden,
56 cl::desc("Disable Post Regalloc Scheduler"));
57static cl::opt<bool> DisableBranchFold("disable-branch-fold", cl::Hidden,
58 cl::desc("Disable branch folding"));
59static cl::opt<bool> DisableTailDuplicate("disable-tail-duplicate", cl::Hidden,
60 cl::desc("Disable tail duplication"));
61static cl::opt<bool> DisableEarlyTailDup("disable-early-taildup", cl::Hidden,
62 cl::desc("Disable pre-register allocation tail duplication"));
63static cl::opt<bool> DisableBlockPlacement("disable-block-placement",
64 cl::Hidden, cl::desc("Disable probability-driven block placement"));
65static cl::opt<bool> EnableBlockPlacementStats("enable-block-placement-stats",
66 cl::Hidden, cl::desc("Collect probability-driven block placement stats"));
67static cl::opt<bool> DisableSSC("disable-ssc", cl::Hidden,
68 cl::desc("Disable Stack Slot Coloring"));
69static cl::opt<bool> DisableMachineDCE("disable-machine-dce", cl::Hidden,
70 cl::desc("Disable Machine Dead Code Elimination"));
71static cl::opt<bool> DisableEarlyIfConversion("disable-early-ifcvt", cl::Hidden,
72 cl::desc("Disable Early If-conversion"));
73static cl::opt<bool> DisableMachineLICM("disable-machine-licm", cl::Hidden,
74 cl::desc("Disable Machine LICM"));
75static cl::opt<bool> DisableMachineCSE("disable-machine-cse", cl::Hidden,
76 cl::desc("Disable Machine Common Subexpression Elimination"));
77static cl::opt<cl::boolOrDefault> OptimizeRegAlloc(
78 "optimize-regalloc", cl::Hidden,
79 cl::desc("Enable optimized register allocation compilation path."));
80static cl::opt<bool> DisablePostRAMachineLICM("disable-postra-machine-licm",
81 cl::Hidden,
82 cl::desc("Disable Machine LICM"));
83static cl::opt<bool> DisableMachineSink("disable-machine-sink", cl::Hidden,
84 cl::desc("Disable Machine Sinking"));
85static cl::opt<bool> DisablePostRAMachineSink("disable-postra-machine-sink",
86 cl::Hidden,
87 cl::desc("Disable PostRA Machine Sinking"));
88static cl::opt<bool> DisableLSR("disable-lsr", cl::Hidden,
89 cl::desc("Disable Loop Strength Reduction Pass"));
90static cl::opt<bool> DisableConstantHoisting("disable-constant-hoisting",
91 cl::Hidden, cl::desc("Disable ConstantHoisting"));
92static cl::opt<bool> DisableCGP("disable-cgp", cl::Hidden,
93 cl::desc("Disable Codegen Prepare"));
94static cl::opt<bool> DisableCopyProp("disable-copyprop", cl::Hidden,
95 cl::desc("Disable Copy Propagation pass"));
96static cl::opt<bool> DisablePartialLibcallInlining("disable-partial-libcall-inlining",
97 cl::Hidden, cl::desc("Disable Partial Libcall Inlining"));
98static cl::opt<bool> EnableImplicitNullChecks(
99 "enable-implicit-null-checks",
100 cl::desc("Fold null checks into faulting memory operations"),
101 cl::init(false), cl::Hidden);
102static cl::opt<bool> DisableMergeICmps("disable-mergeicmps",
103 cl::desc("Disable MergeICmps Pass"),
104 cl::init(false), cl::Hidden);
105static cl::opt<bool> PrintLSR("print-lsr-output", cl::Hidden,
106 cl::desc("Print LLVM IR produced by the loop-reduce pass"));
107static cl::opt<bool> PrintISelInput("print-isel-input", cl::Hidden,
108 cl::desc("Print LLVM IR input to isel pass"));
109static cl::opt<bool> PrintGCInfo("print-gc", cl::Hidden,
110 cl::desc("Dump garbage collector data"));
111static cl::opt<cl::boolOrDefault>
112 VerifyMachineCode("verify-machineinstrs", cl::Hidden,
113 cl::desc("Verify generated machine code"),
114 cl::ZeroOrMore);
115enum RunOutliner { AlwaysOutline, NeverOutline, TargetDefault };
116// Enable or disable the MachineOutliner.
117static cl::opt<RunOutliner> EnableMachineOutliner(
118 "enable-machine-outliner", cl::desc("Enable the machine outliner"),
119 cl::Hidden, cl::ValueOptional, cl::init(TargetDefault),
120 cl::values(clEnumValN(AlwaysOutline, "always",llvm::cl::OptionEnumValue { "always", int(AlwaysOutline), "Run on all functions guaranteed to be beneficial"
}
121 "Run on all functions guaranteed to be beneficial")llvm::cl::OptionEnumValue { "always", int(AlwaysOutline), "Run on all functions guaranteed to be beneficial"
}
,
122 clEnumValN(NeverOutline, "never", "Disable all outlining")llvm::cl::OptionEnumValue { "never", int(NeverOutline), "Disable all outlining"
}
,
123 // Sentinel value for unspecified option.
124 clEnumValN(AlwaysOutline, "", "")llvm::cl::OptionEnumValue { "", int(AlwaysOutline), "" }));
125// Enable or disable FastISel. Both options are needed, because
126// FastISel is enabled by default with -fast, and we wish to be
127// able to enable or disable fast-isel independently from -O0.
128static cl::opt<cl::boolOrDefault>
129EnableFastISelOption("fast-isel", cl::Hidden,
130 cl::desc("Enable the \"fast\" instruction selector"));
131
132static cl::opt<cl::boolOrDefault> EnableGlobalISelOption(
133 "global-isel", cl::Hidden,
134 cl::desc("Enable the \"global\" instruction selector"));
135
136static cl::opt<std::string> PrintMachineInstrs(
137 "print-machineinstrs", cl::ValueOptional, cl::desc("Print machine instrs"),
138 cl::value_desc("pass-name"), cl::init("option-unspecified"), cl::Hidden);
139
140static cl::opt<GlobalISelAbortMode> EnableGlobalISelAbort(
141 "global-isel-abort", cl::Hidden,
142 cl::desc("Enable abort calls when \"global\" instruction selection "
143 "fails to lower/select an instruction"),
144 cl::values(
145 clEnumValN(GlobalISelAbortMode::Disable, "0", "Disable the abort")llvm::cl::OptionEnumValue { "0", int(GlobalISelAbortMode::Disable
), "Disable the abort" }
,
146 clEnumValN(GlobalISelAbortMode::Enable, "1", "Enable the abort")llvm::cl::OptionEnumValue { "1", int(GlobalISelAbortMode::Enable
), "Enable the abort" }
,
147 clEnumValN(GlobalISelAbortMode::DisableWithDiag, "2",llvm::cl::OptionEnumValue { "2", int(GlobalISelAbortMode::DisableWithDiag
), "Disable the abort but emit a diagnostic on failure" }
148 "Disable the abort but emit a diagnostic on failure")llvm::cl::OptionEnumValue { "2", int(GlobalISelAbortMode::DisableWithDiag
), "Disable the abort but emit a diagnostic on failure" }
));
149
150// Temporary option to allow experimenting with MachineScheduler as a post-RA
151// scheduler. Targets can "properly" enable this with
152// substitutePass(&PostRASchedulerID, &PostMachineSchedulerID).
153// Targets can return true in targetSchedulesPostRAScheduling() and
154// insert a PostRA scheduling pass wherever it wants.
155cl::opt<bool> MISchedPostRA("misched-postra", cl::Hidden,
156 cl::desc("Run MachineScheduler post regalloc (independent of preRA sched)"));
157
158// Experimental option to run live interval analysis early.
159static cl::opt<bool> EarlyLiveIntervals("early-live-intervals", cl::Hidden,
160 cl::desc("Run live interval analysis earlier in the pipeline"));
161
162// Experimental option to use CFL-AA in codegen
163enum class CFLAAType { None, Steensgaard, Andersen, Both };
164static cl::opt<CFLAAType> UseCFLAA(
165 "use-cfl-aa-in-codegen", cl::init(CFLAAType::None), cl::Hidden,
166 cl::desc("Enable the new, experimental CFL alias analysis in CodeGen"),
167 cl::values(clEnumValN(CFLAAType::None, "none", "Disable CFL-AA")llvm::cl::OptionEnumValue { "none", int(CFLAAType::None), "Disable CFL-AA"
}
,
168 clEnumValN(CFLAAType::Steensgaard, "steens",llvm::cl::OptionEnumValue { "steens", int(CFLAAType::Steensgaard
), "Enable unification-based CFL-AA" }
169 "Enable unification-based CFL-AA")llvm::cl::OptionEnumValue { "steens", int(CFLAAType::Steensgaard
), "Enable unification-based CFL-AA" }
,
170 clEnumValN(CFLAAType::Andersen, "anders",llvm::cl::OptionEnumValue { "anders", int(CFLAAType::Andersen
), "Enable inclusion-based CFL-AA" }
171 "Enable inclusion-based CFL-AA")llvm::cl::OptionEnumValue { "anders", int(CFLAAType::Andersen
), "Enable inclusion-based CFL-AA" }
,
172 clEnumValN(CFLAAType::Both, "both",llvm::cl::OptionEnumValue { "both", int(CFLAAType::Both), "Enable both variants of CFL-AA"
}
173 "Enable both variants of CFL-AA")llvm::cl::OptionEnumValue { "both", int(CFLAAType::Both), "Enable both variants of CFL-AA"
}
));
174
175/// Option names for limiting the codegen pipeline.
176/// Those are used in error reporting and we didn't want
177/// to duplicate their names all over the place.
178const char *StartAfterOptName = "start-after";
179const char *StartBeforeOptName = "start-before";
180const char *StopAfterOptName = "stop-after";
181const char *StopBeforeOptName = "stop-before";
182
183static cl::opt<std::string>
184 StartAfterOpt(StringRef(StartAfterOptName),
185 cl::desc("Resume compilation after a specific pass"),
186 cl::value_desc("pass-name"), cl::init(""), cl::Hidden);
187
188static cl::opt<std::string>
189 StartBeforeOpt(StringRef(StartBeforeOptName),
190 cl::desc("Resume compilation before a specific pass"),
191 cl::value_desc("pass-name"), cl::init(""), cl::Hidden);
192
193static cl::opt<std::string>
194 StopAfterOpt(StringRef(StopAfterOptName),
195 cl::desc("Stop compilation after a specific pass"),
196 cl::value_desc("pass-name"), cl::init(""), cl::Hidden);
197
198static cl::opt<std::string>
199 StopBeforeOpt(StringRef(StopBeforeOptName),
200 cl::desc("Stop compilation before a specific pass"),
201 cl::value_desc("pass-name"), cl::init(""), cl::Hidden);
202
203/// Allow standard passes to be disabled by command line options. This supports
204/// simple binary flags that either suppress the pass or do nothing.
205/// i.e. -disable-mypass=false has no effect.
206/// These should be converted to boolOrDefault in order to use applyOverride.
207static IdentifyingPassPtr applyDisable(IdentifyingPassPtr PassID,
208 bool Override) {
209 if (Override)
210 return IdentifyingPassPtr();
211 return PassID;
212}
213
214/// Allow standard passes to be disabled by the command line, regardless of who
215/// is adding the pass.
216///
217/// StandardID is the pass identified in the standard pass pipeline and provided
218/// to addPass(). It may be a target-specific ID in the case that the target
219/// directly adds its own pass, but in that case we harmlessly fall through.
220///
221/// TargetID is the pass that the target has configured to override StandardID.
222///
223/// StandardID may be a pseudo ID. In that case TargetID is the name of the real
224/// pass to run. This allows multiple options to control a single pass depending
225/// on where in the pipeline that pass is added.
226static IdentifyingPassPtr overridePass(AnalysisID StandardID,
227 IdentifyingPassPtr TargetID) {
228 if (StandardID == &PostRASchedulerID)
229 return applyDisable(TargetID, DisablePostRASched);
230
231 if (StandardID == &BranchFolderPassID)
232 return applyDisable(TargetID, DisableBranchFold);
233
234 if (StandardID == &TailDuplicateID)
235 return applyDisable(TargetID, DisableTailDuplicate);
236
237 if (StandardID == &EarlyTailDuplicateID)
238 return applyDisable(TargetID, DisableEarlyTailDup);
239
240 if (StandardID == &MachineBlockPlacementID)
241 return applyDisable(TargetID, DisableBlockPlacement);
242
243 if (StandardID == &StackSlotColoringID)
244 return applyDisable(TargetID, DisableSSC);
245
246 if (StandardID == &DeadMachineInstructionElimID)
247 return applyDisable(TargetID, DisableMachineDCE);
248
249 if (StandardID == &EarlyIfConverterID)
250 return applyDisable(TargetID, DisableEarlyIfConversion);
251
252 if (StandardID == &EarlyMachineLICMID)
253 return applyDisable(TargetID, DisableMachineLICM);
254
255 if (StandardID == &MachineCSEID)
256 return applyDisable(TargetID, DisableMachineCSE);
257
258 if (StandardID == &MachineLICMID)
259 return applyDisable(TargetID, DisablePostRAMachineLICM);
260
261 if (StandardID == &MachineSinkingID)
262 return applyDisable(TargetID, DisableMachineSink);
263
264 if (StandardID == &PostRAMachineSinkingID)
265 return applyDisable(TargetID, DisablePostRAMachineSink);
266
267 if (StandardID == &MachineCopyPropagationID)
268 return applyDisable(TargetID, DisableCopyProp);
269
270 return TargetID;
271}
272
273//===---------------------------------------------------------------------===//
274/// TargetPassConfig
275//===---------------------------------------------------------------------===//
276
277INITIALIZE_PASS(TargetPassConfig, "targetpassconfig",static void *initializeTargetPassConfigPassOnce(PassRegistry &
Registry) { PassInfo *PI = new PassInfo( "Target Pass Configuration"
, "targetpassconfig", &TargetPassConfig::ID, PassInfo::NormalCtor_t
(callDefaultCtor<TargetPassConfig>), false, false); Registry
.registerPass(*PI, true); return PI; } static llvm::once_flag
InitializeTargetPassConfigPassFlag; void llvm::initializeTargetPassConfigPass
(PassRegistry &Registry) { llvm::call_once(InitializeTargetPassConfigPassFlag
, initializeTargetPassConfigPassOnce, std::ref(Registry)); }
278 "Target Pass Configuration", false, false)static void *initializeTargetPassConfigPassOnce(PassRegistry &
Registry) { PassInfo *PI = new PassInfo( "Target Pass Configuration"
, "targetpassconfig", &TargetPassConfig::ID, PassInfo::NormalCtor_t
(callDefaultCtor<TargetPassConfig>), false, false); Registry
.registerPass(*PI, true); return PI; } static llvm::once_flag
InitializeTargetPassConfigPassFlag; void llvm::initializeTargetPassConfigPass
(PassRegistry &Registry) { llvm::call_once(InitializeTargetPassConfigPassFlag
, initializeTargetPassConfigPassOnce, std::ref(Registry)); }
279char TargetPassConfig::ID = 0;
280
281namespace {
282
283struct InsertedPass {
284 AnalysisID TargetPassID;
285 IdentifyingPassPtr InsertedPassID;
286 bool VerifyAfter;
287 bool PrintAfter;
288
289 InsertedPass(AnalysisID TargetPassID, IdentifyingPassPtr InsertedPassID,
290 bool VerifyAfter, bool PrintAfter)
291 : TargetPassID(TargetPassID), InsertedPassID(InsertedPassID),
292 VerifyAfter(VerifyAfter), PrintAfter(PrintAfter) {}
293
294 Pass *getInsertedPass() const {
295 assert(InsertedPassID.isValid() && "Illegal Pass ID!")((InsertedPassID.isValid() && "Illegal Pass ID!") ? static_cast
<void> (0) : __assert_fail ("InsertedPassID.isValid() && \"Illegal Pass ID!\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/TargetPassConfig.cpp"
, 295, __PRETTY_FUNCTION__))
;
296 if (InsertedPassID.isInstance())
297 return InsertedPassID.getInstance();
298 Pass *NP = Pass::createPass(InsertedPassID.getID());
299 assert(NP && "Pass ID not registered")((NP && "Pass ID not registered") ? static_cast<void
> (0) : __assert_fail ("NP && \"Pass ID not registered\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/TargetPassConfig.cpp"
, 299, __PRETTY_FUNCTION__))
;
300 return NP;
301 }
302};
303
304} // end anonymous namespace
305
306namespace llvm {
307
308class PassConfigImpl {
309public:
310 // List of passes explicitly substituted by this target. Normally this is
311 // empty, but it is a convenient way to suppress or replace specific passes
312 // that are part of a standard pass pipeline without overridding the entire
313 // pipeline. This mechanism allows target options to inherit a standard pass's
314 // user interface. For example, a target may disable a standard pass by
315 // default by substituting a pass ID of zero, and the user may still enable
316 // that standard pass with an explicit command line option.
317 DenseMap<AnalysisID,IdentifyingPassPtr> TargetPasses;
318
319 /// Store the pairs of <AnalysisID, AnalysisID> of which the second pass
320 /// is inserted after each instance of the first one.
321 SmallVector<InsertedPass, 4> InsertedPasses;
322};
323
324} // end namespace llvm
325
326// Out of line virtual method.
327TargetPassConfig::~TargetPassConfig() {
328 delete Impl;
329}
330
331static const PassInfo *getPassInfo(StringRef PassName) {
332 if (PassName.empty())
333 return nullptr;
334
335 const PassRegistry &PR = *PassRegistry::getPassRegistry();
336 const PassInfo *PI = PR.getPassInfo(PassName);
337 if (!PI)
338 report_fatal_error(Twine('\"') + Twine(PassName) +
339 Twine("\" pass is not registered."));
340 return PI;
341}
342
343static AnalysisID getPassIDFromName(StringRef PassName) {
344 const PassInfo *PI = getPassInfo(PassName);
345 return PI ? PI->getTypeInfo() : nullptr;
346}
347
348static std::pair<StringRef, unsigned>
349getPassNameAndInstanceNum(StringRef PassName) {
350 StringRef Name, InstanceNumStr;
351 std::tie(Name, InstanceNumStr) = PassName.split(',');
352
353 unsigned InstanceNum = 0;
354 if (!InstanceNumStr.empty() && InstanceNumStr.getAsInteger(10, InstanceNum))
355 report_fatal_error("invalid pass instance specifier " + PassName);
356
357 return std::make_pair(Name, InstanceNum);
358}
359
360void TargetPassConfig::setStartStopPasses() {
361 StringRef StartBeforeName;
362 std::tie(StartBeforeName, StartBeforeInstanceNum) =
363 getPassNameAndInstanceNum(StartBeforeOpt);
364
365 StringRef StartAfterName;
366 std::tie(StartAfterName, StartAfterInstanceNum) =
367 getPassNameAndInstanceNum(StartAfterOpt);
368
369 StringRef StopBeforeName;
370 std::tie(StopBeforeName, StopBeforeInstanceNum)
371 = getPassNameAndInstanceNum(StopBeforeOpt);
372
373 StringRef StopAfterName;
374 std::tie(StopAfterName, StopAfterInstanceNum)
375 = getPassNameAndInstanceNum(StopAfterOpt);
376
377 StartBefore = getPassIDFromName(StartBeforeName);
378 StartAfter = getPassIDFromName(StartAfterName);
379 StopBefore = getPassIDFromName(StopBeforeName);
380 StopAfter = getPassIDFromName(StopAfterName);
381 if (StartBefore && StartAfter)
382 report_fatal_error(Twine(StartBeforeOptName) + Twine(" and ") +
383 Twine(StartAfterOptName) + Twine(" specified!"));
384 if (StopBefore && StopAfter)
385 report_fatal_error(Twine(StopBeforeOptName) + Twine(" and ") +
386 Twine(StopAfterOptName) + Twine(" specified!"));
387 Started = (StartAfter == nullptr) && (StartBefore == nullptr);
388}
389
390// Out of line constructor provides default values for pass options and
391// registers all common codegen passes.
392TargetPassConfig::TargetPassConfig(LLVMTargetMachine &TM, PassManagerBase &pm)
393 : ImmutablePass(ID), PM(&pm), TM(&TM) {
394 Impl = new PassConfigImpl();
395
396 // Register all target independent codegen passes to activate their PassIDs,
397 // including this pass itself.
398 initializeCodeGen(*PassRegistry::getPassRegistry());
399
400 // Also register alias analysis passes required by codegen passes.
401 initializeBasicAAWrapperPassPass(*PassRegistry::getPassRegistry());
402 initializeAAResultsWrapperPassPass(*PassRegistry::getPassRegistry());
403
404 if (StringRef(PrintMachineInstrs.getValue()).equals(""))
405 TM.Options.PrintMachineCode = true;
406
407 if (EnableIPRA.getNumOccurrences())
408 TM.Options.EnableIPRA = EnableIPRA;
409 else {
410 // If not explicitly specified, use target default.
411 TM.Options.EnableIPRA = TM.useIPRA();
412 }
413
414 if (TM.Options.EnableIPRA)
415 setRequiresCodeGenSCCOrder();
416
417 if (EnableGlobalISelAbort.getNumOccurrences())
418 TM.Options.GlobalISelAbort = EnableGlobalISelAbort;
419
420 setStartStopPasses();
421}
422
423CodeGenOpt::Level TargetPassConfig::getOptLevel() const {
424 return TM->getOptLevel();
425}
426
427/// Insert InsertedPassID pass after TargetPassID.
428void TargetPassConfig::insertPass(AnalysisID TargetPassID,
429 IdentifyingPassPtr InsertedPassID,
430 bool VerifyAfter, bool PrintAfter) {
431 assert(((!InsertedPassID.isInstance() &&((((!InsertedPassID.isInstance() && TargetPassID != InsertedPassID
.getID()) || (InsertedPassID.isInstance() && TargetPassID
!= InsertedPassID.getInstance()->getPassID())) &&
"Insert a pass after itself!") ? static_cast<void> (0)
: __assert_fail ("((!InsertedPassID.isInstance() && TargetPassID != InsertedPassID.getID()) || (InsertedPassID.isInstance() && TargetPassID != InsertedPassID.getInstance()->getPassID())) && \"Insert a pass after itself!\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/TargetPassConfig.cpp"
, 435, __PRETTY_FUNCTION__))
432 TargetPassID != InsertedPassID.getID()) ||((((!InsertedPassID.isInstance() && TargetPassID != InsertedPassID
.getID()) || (InsertedPassID.isInstance() && TargetPassID
!= InsertedPassID.getInstance()->getPassID())) &&
"Insert a pass after itself!") ? static_cast<void> (0)
: __assert_fail ("((!InsertedPassID.isInstance() && TargetPassID != InsertedPassID.getID()) || (InsertedPassID.isInstance() && TargetPassID != InsertedPassID.getInstance()->getPassID())) && \"Insert a pass after itself!\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/TargetPassConfig.cpp"
, 435, __PRETTY_FUNCTION__))
433 (InsertedPassID.isInstance() &&((((!InsertedPassID.isInstance() && TargetPassID != InsertedPassID
.getID()) || (InsertedPassID.isInstance() && TargetPassID
!= InsertedPassID.getInstance()->getPassID())) &&
"Insert a pass after itself!") ? static_cast<void> (0)
: __assert_fail ("((!InsertedPassID.isInstance() && TargetPassID != InsertedPassID.getID()) || (InsertedPassID.isInstance() && TargetPassID != InsertedPassID.getInstance()->getPassID())) && \"Insert a pass after itself!\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/TargetPassConfig.cpp"
, 435, __PRETTY_FUNCTION__))
434 TargetPassID != InsertedPassID.getInstance()->getPassID())) &&((((!InsertedPassID.isInstance() && TargetPassID != InsertedPassID
.getID()) || (InsertedPassID.isInstance() && TargetPassID
!= InsertedPassID.getInstance()->getPassID())) &&
"Insert a pass after itself!") ? static_cast<void> (0)
: __assert_fail ("((!InsertedPassID.isInstance() && TargetPassID != InsertedPassID.getID()) || (InsertedPassID.isInstance() && TargetPassID != InsertedPassID.getInstance()->getPassID())) && \"Insert a pass after itself!\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/TargetPassConfig.cpp"
, 435, __PRETTY_FUNCTION__))
435 "Insert a pass after itself!")((((!InsertedPassID.isInstance() && TargetPassID != InsertedPassID
.getID()) || (InsertedPassID.isInstance() && TargetPassID
!= InsertedPassID.getInstance()->getPassID())) &&
"Insert a pass after itself!") ? static_cast<void> (0)
: __assert_fail ("((!InsertedPassID.isInstance() && TargetPassID != InsertedPassID.getID()) || (InsertedPassID.isInstance() && TargetPassID != InsertedPassID.getInstance()->getPassID())) && \"Insert a pass after itself!\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/TargetPassConfig.cpp"
, 435, __PRETTY_FUNCTION__))
;
436 Impl->InsertedPasses.emplace_back(TargetPassID, InsertedPassID, VerifyAfter,
437 PrintAfter);
438}
439
440/// createPassConfig - Create a pass configuration object to be used by
441/// addPassToEmitX methods for generating a pipeline of CodeGen passes.
442///
443/// Targets may override this to extend TargetPassConfig.
444TargetPassConfig *LLVMTargetMachine::createPassConfig(PassManagerBase &PM) {
445 return new TargetPassConfig(*this, PM);
446}
447
448TargetPassConfig::TargetPassConfig()
449 : ImmutablePass(ID) {
450 report_fatal_error("Trying to construct TargetPassConfig without a target "
451 "machine. Scheduling a CodeGen pass without a target "
452 "triple set?");
453}
454
455bool TargetPassConfig::willCompleteCodeGenPipeline() {
456 return StopBeforeOpt.empty() && StopAfterOpt.empty();
457}
458
459bool TargetPassConfig::hasLimitedCodeGenPipeline() {
460 return !StartBeforeOpt.empty() || !StartAfterOpt.empty() ||
461 !willCompleteCodeGenPipeline();
462}
463
464std::string
465TargetPassConfig::getLimitedCodeGenPipelineReason(const char *Separator) const {
466 if (!hasLimitedCodeGenPipeline())
467 return std::string();
468 std::string Res;
469 static cl::opt<std::string> *PassNames[] = {&StartAfterOpt, &StartBeforeOpt,
470 &StopAfterOpt, &StopBeforeOpt};
471 static const char *OptNames[] = {StartAfterOptName, StartBeforeOptName,
472 StopAfterOptName, StopBeforeOptName};
473 bool IsFirst = true;
474 for (int Idx = 0; Idx < 4; ++Idx)
475 if (!PassNames[Idx]->empty()) {
476 if (!IsFirst)
477 Res += Separator;
478 IsFirst = false;
479 Res += OptNames[Idx];
480 }
481 return Res;
482}
483
484// Helper to verify the analysis is really immutable.
485void TargetPassConfig::setOpt(bool &Opt, bool Val) {
486 assert(!Initialized && "PassConfig is immutable")((!Initialized && "PassConfig is immutable") ? static_cast
<void> (0) : __assert_fail ("!Initialized && \"PassConfig is immutable\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/TargetPassConfig.cpp"
, 486, __PRETTY_FUNCTION__))
;
487 Opt = Val;
488}
489
490void TargetPassConfig::substitutePass(AnalysisID StandardID,
491 IdentifyingPassPtr TargetID) {
492 Impl->TargetPasses[StandardID] = TargetID;
493}
494
495IdentifyingPassPtr TargetPassConfig::getPassSubstitution(AnalysisID ID) const {
496 DenseMap<AnalysisID, IdentifyingPassPtr>::const_iterator
497 I = Impl->TargetPasses.find(ID);
498 if (I == Impl->TargetPasses.end())
499 return ID;
500 return I->second;
501}
502
503bool TargetPassConfig::isPassSubstitutedOrOverridden(AnalysisID ID) const {
504 IdentifyingPassPtr TargetID = getPassSubstitution(ID);
505 IdentifyingPassPtr FinalPtr = overridePass(ID, TargetID);
506 return !FinalPtr.isValid() || FinalPtr.isInstance() ||
507 FinalPtr.getID() != ID;
508}
509
510/// Add a pass to the PassManager if that pass is supposed to be run. If the
511/// Started/Stopped flags indicate either that the compilation should start at
512/// a later pass or that it should stop after an earlier pass, then do not add
513/// the pass. Finally, compare the current pass against the StartAfter
514/// and StopAfter options and change the Started/Stopped flags accordingly.
515void TargetPassConfig::addPass(Pass *P, bool verifyAfter, bool printAfter) {
516 assert(!Initialized && "PassConfig is immutable")((!Initialized && "PassConfig is immutable") ? static_cast
<void> (0) : __assert_fail ("!Initialized && \"PassConfig is immutable\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/TargetPassConfig.cpp"
, 516, __PRETTY_FUNCTION__))
;
517
518 // Cache the Pass ID here in case the pass manager finds this pass is
519 // redundant with ones already scheduled / available, and deletes it.
520 // Fundamentally, once we add the pass to the manager, we no longer own it
521 // and shouldn't reference it.
522 AnalysisID PassID = P->getPassID();
523
524 if (StartBefore == PassID && StartBeforeCount++ == StartBeforeInstanceNum)
525 Started = true;
526 if (StopBefore == PassID && StopBeforeCount++ == StopBeforeInstanceNum)
527 Stopped = true;
528 if (Started && !Stopped) {
529 std::string Banner;
530 // Construct banner message before PM->add() as that may delete the pass.
531 if (AddingMachinePasses && (printAfter || verifyAfter))
532 Banner = std::string("After ") + std::string(P->getPassName());
533 PM->add(P);
534 if (AddingMachinePasses) {
535 if (printAfter)
536 addPrintPass(Banner);
537 if (verifyAfter)
538 addVerifyPass(Banner);
539 }
540
541 // Add the passes after the pass P if there is any.
542 for (auto IP : Impl->InsertedPasses) {
543 if (IP.TargetPassID == PassID)
544 addPass(IP.getInsertedPass(), IP.VerifyAfter, IP.PrintAfter);
545 }
546 } else {
547 delete P;
548 }
549
550 if (StopAfter == PassID && StopAfterCount++ == StopAfterInstanceNum)
551 Stopped = true;
552
553 if (StartAfter == PassID && StartAfterCount++ == StartAfterInstanceNum)
554 Started = true;
555 if (Stopped && !Started)
556 report_fatal_error("Cannot stop compilation after pass that is not run");
557}
558
559/// Add a CodeGen pass at this point in the pipeline after checking for target
560/// and command line overrides.
561///
562/// addPass cannot return a pointer to the pass instance because is internal the
563/// PassManager and the instance we create here may already be freed.
564AnalysisID TargetPassConfig::addPass(AnalysisID PassID, bool verifyAfter,
565 bool printAfter) {
566 IdentifyingPassPtr TargetID = getPassSubstitution(PassID);
567 IdentifyingPassPtr FinalPtr = overridePass(PassID, TargetID);
568 if (!FinalPtr.isValid())
569 return nullptr;
570
571 Pass *P;
572 if (FinalPtr.isInstance())
573 P = FinalPtr.getInstance();
574 else {
575 P = Pass::createPass(FinalPtr.getID());
576 if (!P)
577 llvm_unreachable("Pass ID not registered")::llvm::llvm_unreachable_internal("Pass ID not registered", "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/TargetPassConfig.cpp"
, 577)
;
578 }
579 AnalysisID FinalID = P->getPassID();
580 addPass(P, verifyAfter, printAfter); // Ends the lifetime of P.
581
582 return FinalID;
583}
584
585void TargetPassConfig::printAndVerify(const std::string &Banner) {
586 addPrintPass(Banner);
587 addVerifyPass(Banner);
588}
589
590void TargetPassConfig::addPrintPass(const std::string &Banner) {
591 if (TM->shouldPrintMachineCode())
592 PM->add(createMachineFunctionPrinterPass(dbgs(), Banner));
593}
594
595void TargetPassConfig::addVerifyPass(const std::string &Banner) {
596 bool Verify = VerifyMachineCode == cl::BOU_TRUE;
597#ifdef EXPENSIVE_CHECKS
598 if (VerifyMachineCode == cl::BOU_UNSET)
599 Verify = TM->isMachineVerifierClean();
600#endif
601 if (Verify)
602 PM->add(createMachineVerifierPass(Banner));
603}
604
605/// Add common target configurable passes that perform LLVM IR to IR transforms
606/// following machine independent optimization.
607void TargetPassConfig::addIRPasses() {
608 switch (UseCFLAA) {
609 case CFLAAType::Steensgaard:
610 addPass(createCFLSteensAAWrapperPass());
611 break;
612 case CFLAAType::Andersen:
613 addPass(createCFLAndersAAWrapperPass());
614 break;
615 case CFLAAType::Both:
616 addPass(createCFLAndersAAWrapperPass());
617 addPass(createCFLSteensAAWrapperPass());
618 break;
619 default:
620 break;
621 }
622
623 // Basic AliasAnalysis support.
624 // Add TypeBasedAliasAnalysis before BasicAliasAnalysis so that
625 // BasicAliasAnalysis wins if they disagree. This is intended to help
626 // support "obvious" type-punning idioms.
627 addPass(createTypeBasedAAWrapperPass());
628 addPass(createScopedNoAliasAAWrapperPass());
629 addPass(createBasicAAWrapperPass());
630
631 // Before running any passes, run the verifier to determine if the input
632 // coming from the front-end and/or optimizer is valid.
633 if (!DisableVerify)
634 addPass(createVerifierPass());
635
636 // Run loop strength reduction before anything else.
637 if (getOptLevel() != CodeGenOpt::None && !DisableLSR) {
638 addPass(createLoopStrengthReducePass());
639 if (PrintLSR)
640 addPass(createPrintFunctionPass(dbgs(), "\n\n*** Code after LSR ***\n"));
641 }
642
643 if (getOptLevel() != CodeGenOpt::None) {
644 // The MergeICmpsPass tries to create memcmp calls by grouping sequences of
645 // loads and compares. ExpandMemCmpPass then tries to expand those calls
646 // into optimally-sized loads and compares. The transforms are enabled by a
647 // target lowering hook.
648 if (!DisableMergeICmps)
649 addPass(createMergeICmpsPass());
650 addPass(createExpandMemCmpPass());
651 }
652
653 // Run GC lowering passes for builtin collectors
654 // TODO: add a pass insertion point here
655 addPass(createGCLoweringPass());
656 addPass(createShadowStackGCLoweringPass());
657
658 // Make sure that no unreachable blocks are instruction selected.
659 addPass(createUnreachableBlockEliminationPass());
660
661 // Prepare expensive constants for SelectionDAG.
662 if (getOptLevel() != CodeGenOpt::None && !DisableConstantHoisting)
663 addPass(createConstantHoistingPass());
664
665 if (getOptLevel() != CodeGenOpt::None && !DisablePartialLibcallInlining)
666 addPass(createPartiallyInlineLibCallsPass());
667
668 // Instrument function entry and exit, e.g. with calls to mcount().
669 addPass(createPostInlineEntryExitInstrumenterPass());
670
671 // Add scalarization of target's unsupported masked memory intrinsics pass.
672 // the unsupported intrinsic will be replaced with a chain of basic blocks,
673 // that stores/loads element one-by-one if the appropriate mask bit is set.
674 addPass(createScalarizeMaskedMemIntrinPass());
675
676 // Expand reduction intrinsics into shuffle sequences if the target wants to.
677 addPass(createExpandReductionsPass());
678}
679
680/// Turn exception handling constructs into something the code generators can
681/// handle.
682void TargetPassConfig::addPassesToHandleExceptions() {
683 const MCAsmInfo *MCAI = TM->getMCAsmInfo();
684 assert(MCAI && "No MCAsmInfo")((MCAI && "No MCAsmInfo") ? static_cast<void> (
0) : __assert_fail ("MCAI && \"No MCAsmInfo\"", "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/TargetPassConfig.cpp"
, 684, __PRETTY_FUNCTION__))
;
685 switch (MCAI->getExceptionHandlingType()) {
686 case ExceptionHandling::SjLj:
687 // SjLj piggy-backs on dwarf for this bit. The cleanups done apply to both
688 // Dwarf EH prepare needs to be run after SjLj prepare. Otherwise,
689 // catch info can get misplaced when a selector ends up more than one block
690 // removed from the parent invoke(s). This could happen when a landing
691 // pad is shared by multiple invokes and is also a target of a normal
692 // edge from elsewhere.
693 addPass(createSjLjEHPreparePass());
694 LLVM_FALLTHROUGH[[clang::fallthrough]];
695 case ExceptionHandling::DwarfCFI:
696 case ExceptionHandling::ARM:
697 addPass(createDwarfEHPass());
698 break;
699 case ExceptionHandling::WinEH:
700 // We support using both GCC-style and MSVC-style exceptions on Windows, so
701 // add both preparation passes. Each pass will only actually run if it
702 // recognizes the personality function.
703 addPass(createWinEHPass());
704 addPass(createDwarfEHPass());
705 break;
706 case ExceptionHandling::Wasm:
707 // Wasm EH uses Windows EH instructions, but it does not need to demote PHIs
708 // on catchpads and cleanuppads because it does not outline them into
709 // funclets. Catchswitch blocks are not lowered in SelectionDAG, so we
710 // should remove PHIs there.
711 addPass(createWinEHPass(/*DemoteCatchSwitchPHIOnly=*/false));
712 addPass(createWasmEHPass());
713 break;
714 case ExceptionHandling::None:
715 addPass(createLowerInvokePass());
716
717 // The lower invoke pass may create unreachable code. Remove it.
718 addPass(createUnreachableBlockEliminationPass());
719 break;
720 }
721}
722
723/// Add pass to prepare the LLVM IR for code generation. This should be done
724/// before exception handling preparation passes.
725void TargetPassConfig::addCodeGenPrepare() {
726 if (getOptLevel() != CodeGenOpt::None && !DisableCGP)
727 addPass(createCodeGenPreparePass());
728 addPass(createRewriteSymbolsPass());
729}
730
731/// Add common passes that perform LLVM IR to IR transforms in preparation for
732/// instruction selection.
733void TargetPassConfig::addISelPrepare() {
734 addPreISel();
735
736 // Force codegen to run according to the callgraph.
737 if (requiresCodeGenSCCOrder())
738 addPass(new DummyCGSCCPass);
739
740 // Add both the safe stack and the stack protection passes: each of them will
741 // only protect functions that have corresponding attributes.
742 addPass(createSafeStackPass());
743 addPass(createStackProtectorPass());
744
745 if (PrintISelInput)
746 addPass(createPrintFunctionPass(
747 dbgs(), "\n\n*** Final LLVM Code input to ISel ***\n"));
748
749 // All passes which modify the LLVM IR are now complete; run the verifier
750 // to ensure that the IR is valid.
751 if (!DisableVerify)
752 addPass(createVerifierPass());
753}
754
755bool TargetPassConfig::addCoreISelPasses() {
756 // Enable FastISel with -fast-isel, but allow that to be overridden.
757 TM->setO0WantsFastISel(EnableFastISelOption != cl::BOU_FALSE);
758 if (EnableFastISelOption == cl::BOU_TRUE ||
759 (TM->getOptLevel() == CodeGenOpt::None && TM->getO0WantsFastISel() &&
760 !TM->Options.EnableGlobalISel)) {
761 TM->setFastISel(true);
762 TM->setGlobalISel(false);
763 }
764
765 // Ask the target for an instruction selector.
766 // Explicitly enabling fast-isel should override implicitly enabled
767 // global-isel.
768 if (EnableGlobalISelOption == cl::BOU_TRUE ||
769 (EnableGlobalISelOption == cl::BOU_UNSET &&
770 TM->Options.EnableGlobalISel && EnableFastISelOption != cl::BOU_TRUE)) {
771 TM->setGlobalISel(true);
772 TM->setFastISel(false);
773
774 SaveAndRestore<bool> SavedAddingMachinePasses(AddingMachinePasses, true);
775 if (addIRTranslator())
776 return true;
777
778 addPreLegalizeMachineIR();
779
780 if (addLegalizeMachineIR())
781 return true;
782
783 // Before running the register bank selector, ask the target if it
784 // wants to run some passes.
785 addPreRegBankSelect();
786
787 if (addRegBankSelect())
788 return true;
789
790 addPreGlobalInstructionSelect();
791
792 if (addGlobalInstructionSelect())
793 return true;
794
795 // Pass to reset the MachineFunction if the ISel failed.
796 addPass(createResetMachineFunctionPass(
797 reportDiagnosticWhenGlobalISelFallback(), isGlobalISelAbortEnabled()));
798
799 // Provide a fallback path when we do not want to abort on
800 // not-yet-supported input.
801 if (!isGlobalISelAbortEnabled() && addInstSelector())
802 return true;
803
804 } else if (addInstSelector())
805 return true;
806
807 return false;
808}
809
810bool TargetPassConfig::addISelPasses() {
811 if (TM->useEmulatedTLS())
812 addPass(createLowerEmuTLSPass());
813
814 addPass(createPreISelIntrinsicLoweringPass());
815 addPass(createTargetTransformInfoWrapperPass(TM->getTargetIRAnalysis()));
816 addIRPasses();
817 addCodeGenPrepare();
818 addPassesToHandleExceptions();
819 addISelPrepare();
820
821 return addCoreISelPasses();
822}
823
824/// -regalloc=... command line option.
825static FunctionPass *useDefaultRegisterAllocator() { return nullptr; }
826static cl::opt<RegisterRegAlloc::FunctionPassCtor, false,
827 RegisterPassParser<RegisterRegAlloc>>
828 RegAlloc("regalloc", cl::Hidden, cl::init(&useDefaultRegisterAllocator),
829 cl::desc("Register allocator to use"));
830
831/// Add the complete set of target-independent postISel code generator passes.
832///
833/// This can be read as the standard order of major LLVM CodeGen stages. Stages
834/// with nontrivial configuration or multiple passes are broken out below in
835/// add%Stage routines.
836///
837/// Any TargetPassConfig::addXX routine may be overriden by the Target. The
838/// addPre/Post methods with empty header implementations allow injecting
839/// target-specific fixups just before or after major stages. Additionally,
840/// targets have the flexibility to change pass order within a stage by
841/// overriding default implementation of add%Stage routines below. Each
842/// technique has maintainability tradeoffs because alternate pass orders are
843/// not well supported. addPre/Post works better if the target pass is easily
844/// tied to a common pass. But if it has subtle dependencies on multiple passes,
845/// the target should override the stage instead.
846///
847/// TODO: We could use a single addPre/Post(ID) hook to allow pass injection
848/// before/after any target-independent pass. But it's currently overkill.
849void TargetPassConfig::addMachinePasses() {
850 AddingMachinePasses = true;
851
852 // Insert a machine instr printer pass after the specified pass.
853 StringRef PrintMachineInstrsPassName = PrintMachineInstrs.getValue();
854 if (!PrintMachineInstrsPassName.equals("") &&
855 !PrintMachineInstrsPassName.equals("option-unspecified")) {
856 if (const PassInfo *TPI = getPassInfo(PrintMachineInstrsPassName)) {
857 const PassRegistry *PR = PassRegistry::getPassRegistry();
858 const PassInfo *IPI = PR->getPassInfo(StringRef("machineinstr-printer"));
859 assert(IPI && "failed to get \"machineinstr-printer\" PassInfo!")((IPI && "failed to get \"machineinstr-printer\" PassInfo!"
) ? static_cast<void> (0) : __assert_fail ("IPI && \"failed to get \\\"machineinstr-printer\\\" PassInfo!\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/TargetPassConfig.cpp"
, 859, __PRETTY_FUNCTION__))
;
860 const char *TID = (const char *)(TPI->getTypeInfo());
861 const char *IID = (const char *)(IPI->getTypeInfo());
862 insertPass(TID, IID);
863 }
864 }
865
866 // Print the instruction selected machine code...
867 printAndVerify("After Instruction Selection");
868
869 // Expand pseudo-instructions emitted by ISel.
870 addPass(&ExpandISelPseudosID);
871
872 // Add passes that optimize machine instructions in SSA form.
873 if (getOptLevel() != CodeGenOpt::None) {
874 addMachineSSAOptimization();
875 } else {
876 // If the target requests it, assign local variables to stack slots relative
877 // to one another and simplify frame index references where possible.
878 addPass(&LocalStackSlotAllocationID, false);
879 }
880
881 if (TM->Options.EnableIPRA)
882 addPass(createRegUsageInfoPropPass());
883
884 // Run pre-ra passes.
885 addPreRegAlloc();
886
887 // Run register allocation and passes that are tightly coupled with it,
888 // including phi elimination and scheduling.
889 if (getOptimizeRegAlloc())
890 addOptimizedRegAlloc(createRegAllocPass(true));
891 else {
892 if (RegAlloc != &useDefaultRegisterAllocator &&
893 RegAlloc != &createFastRegisterAllocator)
894 report_fatal_error("Must use fast (default) register allocator for unoptimized regalloc.");
895 addFastRegAlloc(createRegAllocPass(false));
896 }
897
898 // Run post-ra passes.
899 addPostRegAlloc();
900
901 // Insert prolog/epilog code. Eliminate abstract frame index references...
902 if (getOptLevel() != CodeGenOpt::None) {
903 addPass(&PostRAMachineSinkingID);
904 addPass(&ShrinkWrapID);
905 }
906
907 // Prolog/Epilog inserter needs a TargetMachine to instantiate. But only
908 // do so if it hasn't been disabled, substituted, or overridden.
909 if (!isPassSubstitutedOrOverridden(&PrologEpilogCodeInserterID))
910 addPass(createPrologEpilogInserterPass());
911
912 /// Add passes that optimize machine instructions after register allocation.
913 if (getOptLevel() != CodeGenOpt::None)
914 addMachineLateOptimization();
915
916 // Expand pseudo instructions before second scheduling pass.
917 addPass(&ExpandPostRAPseudosID);
918
919 // Run pre-sched2 passes.
920 addPreSched2();
921
922 if (EnableImplicitNullChecks)
923 addPass(&ImplicitNullChecksID);
924
925 // Second pass scheduler.
926 // Let Target optionally insert this pass by itself at some other
927 // point.
928 if (getOptLevel() != CodeGenOpt::None &&
929 !TM->targetSchedulesPostRAScheduling()) {
930 if (MISchedPostRA)
931 addPass(&PostMachineSchedulerID);
932 else
933 addPass(&PostRASchedulerID);
934 }
935
936 // GC
937 if (addGCPasses()) {
938 if (PrintGCInfo)
939 addPass(createGCInfoPrinter(dbgs()), false, false);
940 }
941
942 // Basic block placement.
943 if (getOptLevel() != CodeGenOpt::None)
944 addBlockPlacement();
945
946 addPreEmitPass();
947
948 if (TM->Options.EnableIPRA)
949 // Collect register usage information and produce a register mask of
950 // clobbered registers, to be used to optimize call sites.
951 addPass(createRegUsageInfoCollector());
952
953 addPass(&FuncletLayoutID, false);
954
955 addPass(&StackMapLivenessID, false);
956 addPass(&LiveDebugValuesID, false);
957
958 // Insert before XRay Instrumentation.
959 addPass(&FEntryInserterID, false);
960
961 addPass(&XRayInstrumentationID, false);
962 addPass(&PatchableFunctionID, false);
963
964 if (TM->Options.EnableMachineOutliner && getOptLevel() != CodeGenOpt::None &&
965 EnableMachineOutliner != NeverOutline) {
966 bool RunOnAllFunctions = (EnableMachineOutliner == AlwaysOutline);
967 bool AddOutliner = RunOnAllFunctions ||
968 TM->Options.SupportsDefaultOutlining;
969 if (AddOutliner)
970 addPass(createMachineOutlinerPass(RunOnAllFunctions));
971 }
972
973 // Add passes that directly emit MI after all other MI passes.
974 addPreEmitPass2();
975
976 AddingMachinePasses = false;
977}
978
979/// Add passes that optimize machine instructions in SSA form.
980void TargetPassConfig::addMachineSSAOptimization() {
981 // Pre-ra tail duplication.
982 addPass(&EarlyTailDuplicateID);
983
984 // Optimize PHIs before DCE: removing dead PHI cycles may make more
985 // instructions dead.
986 addPass(&OptimizePHIsID, false);
987
988 // This pass merges large allocas. StackSlotColoring is a different pass
989 // which merges spill slots.
990 addPass(&StackColoringID, false);
991
992 // If the target requests it, assign local variables to stack slots relative
993 // to one another and simplify frame index references where possible.
994 addPass(&LocalStackSlotAllocationID, false);
995
996 // With optimization, dead code should already be eliminated. However
997 // there is one known exception: lowered code for arguments that are only
998 // used by tail calls, where the tail calls reuse the incoming stack
999 // arguments directly (see t11 in test/CodeGen/X86/sibcall.ll).
1000 addPass(&DeadMachineInstructionElimID);
1001
1002 // Allow targets to insert passes that improve instruction level parallelism,
1003 // like if-conversion. Such passes will typically need dominator trees and
1004 // loop info, just like LICM and CSE below.
1005 addILPOpts();
1006
1007 addPass(&EarlyMachineLICMID, false);
1008 addPass(&MachineCSEID, false);
1009
1010 addPass(&MachineSinkingID);
1011
1012 addPass(&PeepholeOptimizerID);
1013 // Clean-up the dead code that may have been generated by peephole
1014 // rewriting.
1015 addPass(&DeadMachineInstructionElimID);
1016}
1017
1018//===---------------------------------------------------------------------===//
1019/// Register Allocation Pass Configuration
1020//===---------------------------------------------------------------------===//
1021
1022bool TargetPassConfig::getOptimizeRegAlloc() const {
1023 switch (OptimizeRegAlloc) {
1024 case cl::BOU_UNSET: return getOptLevel() != CodeGenOpt::None;
1025 case cl::BOU_TRUE: return true;
1026 case cl::BOU_FALSE: return false;
1027 }
1028 llvm_unreachable("Invalid optimize-regalloc state")::llvm::llvm_unreachable_internal("Invalid optimize-regalloc state"
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/TargetPassConfig.cpp"
, 1028)
;
1029}
1030
1031/// RegisterRegAlloc's global Registry tracks allocator registration.
1032MachinePassRegistry<RegisterRegAlloc::FunctionPassCtor>
1033 RegisterRegAlloc::Registry;
1034
1035/// A dummy default pass factory indicates whether the register allocator is
1036/// overridden on the command line.
1037static llvm::once_flag InitializeDefaultRegisterAllocatorFlag;
1038
1039static RegisterRegAlloc
1040defaultRegAlloc("default",
1041 "pick register allocator based on -O option",
1042 useDefaultRegisterAllocator);
1043
1044static void initializeDefaultRegisterAllocatorOnce() {
1045 RegisterRegAlloc::FunctionPassCtor Ctor = RegisterRegAlloc::getDefault();
1046
1047 if (!Ctor) {
1048 Ctor = RegAlloc;
Value stored to 'Ctor' is never read
1049 RegisterRegAlloc::setDefault(RegAlloc);
1050 }
1051}
1052
1053/// Instantiate the default register allocator pass for this target for either
1054/// the optimized or unoptimized allocation path. This will be added to the pass
1055/// manager by addFastRegAlloc in the unoptimized case or addOptimizedRegAlloc
1056/// in the optimized case.
1057///
1058/// A target that uses the standard regalloc pass order for fast or optimized
1059/// allocation may still override this for per-target regalloc
1060/// selection. But -regalloc=... always takes precedence.
1061FunctionPass *TargetPassConfig::createTargetRegisterAllocator(bool Optimized) {
1062 if (Optimized)
1063 return createGreedyRegisterAllocator();
1064 else
1065 return createFastRegisterAllocator();
1066}
1067
1068/// Find and instantiate the register allocation pass requested by this target
1069/// at the current optimization level. Different register allocators are
1070/// defined as separate passes because they may require different analysis.
1071///
1072/// This helper ensures that the regalloc= option is always available,
1073/// even for targets that override the default allocator.
1074///
1075/// FIXME: When MachinePassRegistry register pass IDs instead of function ptrs,
1076/// this can be folded into addPass.
1077FunctionPass *TargetPassConfig::createRegAllocPass(bool Optimized) {
1078 // Initialize the global default.
1079 llvm::call_once(InitializeDefaultRegisterAllocatorFlag,
1080 initializeDefaultRegisterAllocatorOnce);
1081
1082 RegisterRegAlloc::FunctionPassCtor Ctor = RegisterRegAlloc::getDefault();
1083 if (Ctor != useDefaultRegisterAllocator)
1084 return Ctor();
1085
1086 // With no -regalloc= override, ask the target for a regalloc pass.
1087 return createTargetRegisterAllocator(Optimized);
1088}
1089
1090/// Return true if the default global register allocator is in use and
1091/// has not be overriden on the command line with '-regalloc=...'
1092bool TargetPassConfig::usingDefaultRegAlloc() const {
1093 return RegAlloc.getNumOccurrences() == 0;
1094}
1095
1096/// Add the minimum set of target-independent passes that are required for
1097/// register allocation. No coalescing or scheduling.
1098void TargetPassConfig::addFastRegAlloc(FunctionPass *RegAllocPass) {
1099 addPass(&PHIEliminationID, false);
1100 addPass(&TwoAddressInstructionPassID, false);
1101
1102 if (RegAllocPass)
1103 addPass(RegAllocPass);
1104}
1105
1106/// Add standard target-independent passes that are tightly coupled with
1107/// optimized register allocation, including coalescing, machine instruction
1108/// scheduling, and register allocation itself.
1109void TargetPassConfig::addOptimizedRegAlloc(FunctionPass *RegAllocPass) {
1110 addPass(&DetectDeadLanesID, false);
1111
1112 addPass(&ProcessImplicitDefsID, false);
1113
1114 // LiveVariables currently requires pure SSA form.
1115 //
1116 // FIXME: Once TwoAddressInstruction pass no longer uses kill flags,
1117 // LiveVariables can be removed completely, and LiveIntervals can be directly
1118 // computed. (We still either need to regenerate kill flags after regalloc, or
1119 // preferably fix the scavenger to not depend on them).
1120 addPass(&LiveVariablesID, false);
1121
1122 // Edge splitting is smarter with machine loop info.
1123 addPass(&MachineLoopInfoID, false);
1124 addPass(&PHIEliminationID, false);
1125
1126 // Eventually, we want to run LiveIntervals before PHI elimination.
1127 if (EarlyLiveIntervals)
1128 addPass(&LiveIntervalsID, false);
1129
1130 addPass(&TwoAddressInstructionPassID, false);
1131 addPass(&RegisterCoalescerID);
1132
1133 // The machine scheduler may accidentally create disconnected components
1134 // when moving subregister definitions around, avoid this by splitting them to
1135 // separate vregs before. Splitting can also improve reg. allocation quality.
1136 addPass(&RenameIndependentSubregsID);
1137
1138 // PreRA instruction scheduling.
1139 addPass(&MachineSchedulerID);
1140
1141 if (RegAllocPass) {
1142 // Add the selected register allocation pass.
1143 addPass(RegAllocPass);
1144
1145 // Allow targets to change the register assignments before rewriting.
1146 addPreRewrite();
1147
1148 // Finally rewrite virtual registers.
1149 addPass(&VirtRegRewriterID);
1150
1151 // Perform stack slot coloring and post-ra machine LICM.
1152 //
1153 // FIXME: Re-enable coloring with register when it's capable of adding
1154 // kill markers.
1155 addPass(&StackSlotColoringID);
1156
1157 // Copy propagate to forward register uses and try to eliminate COPYs that
1158 // were not coalesced.
1159 addPass(&MachineCopyPropagationID);
1160
1161 // Run post-ra machine LICM to hoist reloads / remats.
1162 //
1163 // FIXME: can this move into MachineLateOptimization?
1164 addPass(&MachineLICMID);
1165 }
1166}
1167
1168//===---------------------------------------------------------------------===//
1169/// Post RegAlloc Pass Configuration
1170//===---------------------------------------------------------------------===//
1171
1172/// Add passes that optimize machine instructions after register allocation.
1173void TargetPassConfig::addMachineLateOptimization() {
1174 // Branch folding must be run after regalloc and prolog/epilog insertion.
1175 addPass(&BranchFolderPassID);
1176
1177 // Tail duplication.
1178 // Note that duplicating tail just increases code size and degrades
1179 // performance for targets that require Structured Control Flow.
1180 // In addition it can also make CFG irreducible. Thus we disable it.
1181 if (!TM->requiresStructuredCFG())
1182 addPass(&TailDuplicateID);
1183
1184 // Copy propagation.
1185 addPass(&MachineCopyPropagationID);
1186}
1187
1188/// Add standard GC passes.
1189bool TargetPassConfig::addGCPasses() {
1190 addPass(&GCMachineCodeAnalysisID, false);
1191 return true;
1192}
1193
1194/// Add standard basic block placement passes.
1195void TargetPassConfig::addBlockPlacement() {
1196 if (addPass(&MachineBlockPlacementID)) {
1197 // Run a separate pass to collect block placement statistics.
1198 if (EnableBlockPlacementStats)
1199 addPass(&MachineBlockPlacementStatsID);
1200 }
1201}
1202
1203//===---------------------------------------------------------------------===//
1204/// GlobalISel Configuration
1205//===---------------------------------------------------------------------===//
1206bool TargetPassConfig::isGlobalISelAbortEnabled() const {
1207 return TM->Options.GlobalISelAbort == GlobalISelAbortMode::Enable;
1208}
1209
1210bool TargetPassConfig::reportDiagnosticWhenGlobalISelFallback() const {
1211 return TM->Options.GlobalISelAbort == GlobalISelAbortMode::DisableWithDiag;
1212}