Bug Summary

File:llvm/include/llvm/ADT/APInt.h
Warning:line 403, column 36
The result of the right shift is undefined due to shifting by '64', which is greater or equal to the width of type 'llvm::APInt::WordType'

Annotated Source Code

Press '?' to see keyboard shortcuts

clang -cc1 -cc1 -triple x86_64-pc-linux-gnu -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name X86ISelLowering.cpp -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=cplusplus -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -analyzer-config-compatibility-mode=true -mrelocation-model pic -pic-level 2 -fhalf-no-semantic-interposition -mframe-pointer=none -fmath-errno -fno-rounding-math -mconstructor-aliases -munwind-tables -target-cpu x86-64 -tune-cpu generic -debugger-tuning=gdb -ffunction-sections -fdata-sections -fcoverage-compilation-dir=/build/llvm-toolchain-snapshot-13~++20210405022414+5f57793c4fe4/build-llvm/lib/Target/X86 -resource-dir /usr/lib/llvm-13/lib/clang/13.0.0 -D _DEBUG -D _GNU_SOURCE -D __STDC_CONSTANT_MACROS -D __STDC_FORMAT_MACROS -D __STDC_LIMIT_MACROS -I /build/llvm-toolchain-snapshot-13~++20210405022414+5f57793c4fe4/build-llvm/lib/Target/X86 -I /build/llvm-toolchain-snapshot-13~++20210405022414+5f57793c4fe4/llvm/lib/Target/X86 -I /build/llvm-toolchain-snapshot-13~++20210405022414+5f57793c4fe4/build-llvm/include -I /build/llvm-toolchain-snapshot-13~++20210405022414+5f57793c4fe4/llvm/include -U NDEBUG -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/x86_64-linux-gnu/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/c++/6.3.0/backward -internal-isystem /usr/local/include -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../x86_64-linux-gnu/include -internal-isystem /usr/lib/llvm-13/lib/clang/13.0.0/include -internal-externc-isystem /usr/include/x86_64-linux-gnu -internal-externc-isystem /include -internal-externc-isystem /usr/include -O2 -Wno-unused-parameter -Wwrite-strings -Wno-missing-field-initializers -Wno-long-long -Wno-maybe-uninitialized -Wno-comment -std=c++14 -fdeprecated-macro -fdebug-compilation-dir=/build/llvm-toolchain-snapshot-13~++20210405022414+5f57793c4fe4/build-llvm/lib/Target/X86 -fdebug-prefix-map=/build/llvm-toolchain-snapshot-13~++20210405022414+5f57793c4fe4=. -ferror-limit 19 -fvisibility hidden -fvisibility-inlines-hidden -stack-protector 2 -fgnuc-version=4.2.1 -vectorize-loops -vectorize-slp -analyzer-output=html -analyzer-config stable-report-filename=true -faddrsig -D__GCC_HAVE_DWARF2_CFI_ASM=1 -o /tmp/scan-build-2021-04-05-202135-9119-1 -x c++ /build/llvm-toolchain-snapshot-13~++20210405022414+5f57793c4fe4/llvm/lib/Target/X86/X86ISelLowering.cpp

/build/llvm-toolchain-snapshot-13~++20210405022414+5f57793c4fe4/llvm/lib/Target/X86/X86ISelLowering.cpp

1//===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines the interfaces that X86 uses to lower LLVM code into a
10// selection DAG.
11//
12//===----------------------------------------------------------------------===//
13
14#include "X86ISelLowering.h"
15#include "MCTargetDesc/X86ShuffleDecode.h"
16#include "X86.h"
17#include "X86CallingConv.h"
18#include "X86FrameLowering.h"
19#include "X86InstrBuilder.h"
20#include "X86IntrinsicsInfo.h"
21#include "X86MachineFunctionInfo.h"
22#include "X86TargetMachine.h"
23#include "X86TargetObjectFile.h"
24#include "llvm/ADT/SmallBitVector.h"
25#include "llvm/ADT/SmallSet.h"
26#include "llvm/ADT/Statistic.h"
27#include "llvm/ADT/StringExtras.h"
28#include "llvm/ADT/StringSwitch.h"
29#include "llvm/Analysis/BlockFrequencyInfo.h"
30#include "llvm/Analysis/EHPersonalities.h"
31#include "llvm/Analysis/ProfileSummaryInfo.h"
32#include "llvm/Analysis/VectorUtils.h"
33#include "llvm/CodeGen/IntrinsicLowering.h"
34#include "llvm/CodeGen/MachineFrameInfo.h"
35#include "llvm/CodeGen/MachineFunction.h"
36#include "llvm/CodeGen/MachineInstrBuilder.h"
37#include "llvm/CodeGen/MachineJumpTableInfo.h"
38#include "llvm/CodeGen/MachineLoopInfo.h"
39#include "llvm/CodeGen/MachineModuleInfo.h"
40#include "llvm/CodeGen/MachineRegisterInfo.h"
41#include "llvm/CodeGen/TargetLowering.h"
42#include "llvm/CodeGen/WinEHFuncInfo.h"
43#include "llvm/IR/CallingConv.h"
44#include "llvm/IR/Constants.h"
45#include "llvm/IR/DerivedTypes.h"
46#include "llvm/IR/DiagnosticInfo.h"
47#include "llvm/IR/Function.h"
48#include "llvm/IR/GlobalAlias.h"
49#include "llvm/IR/GlobalVariable.h"
50#include "llvm/IR/Instructions.h"
51#include "llvm/IR/Intrinsics.h"
52#include "llvm/MC/MCAsmInfo.h"
53#include "llvm/MC/MCContext.h"
54#include "llvm/MC/MCExpr.h"
55#include "llvm/MC/MCSymbol.h"
56#include "llvm/Support/CommandLine.h"
57#include "llvm/Support/Debug.h"
58#include "llvm/Support/ErrorHandling.h"
59#include "llvm/Support/KnownBits.h"
60#include "llvm/Support/MathExtras.h"
61#include "llvm/Target/TargetOptions.h"
62#include <algorithm>
63#include <bitset>
64#include <cctype>
65#include <numeric>
66using namespace llvm;
67
68#define DEBUG_TYPE"x86-isel" "x86-isel"
69
70STATISTIC(NumTailCalls, "Number of tail calls")static llvm::Statistic NumTailCalls = {"x86-isel", "NumTailCalls"
, "Number of tail calls"}
;
71
72static cl::opt<int> ExperimentalPrefLoopAlignment(
73 "x86-experimental-pref-loop-alignment", cl::init(4),
74 cl::desc(
75 "Sets the preferable loop alignment for experiments (as log2 bytes)"
76 "(the last x86-experimental-pref-loop-alignment bits"
77 " of the loop header PC will be 0)."),
78 cl::Hidden);
79
80static cl::opt<int> ExperimentalPrefInnermostLoopAlignment(
81 "x86-experimental-pref-innermost-loop-alignment", cl::init(4),
82 cl::desc(
83 "Sets the preferable loop alignment for experiments (as log2 bytes) "
84 "for innermost loops only. If specified, this option overrides "
85 "alignment set by x86-experimental-pref-loop-alignment."),
86 cl::Hidden);
87
88static cl::opt<bool> MulConstantOptimization(
89 "mul-constant-optimization", cl::init(true),
90 cl::desc("Replace 'mul x, Const' with more effective instructions like "
91 "SHIFT, LEA, etc."),
92 cl::Hidden);
93
94static cl::opt<bool> ExperimentalUnorderedISEL(
95 "x86-experimental-unordered-atomic-isel", cl::init(false),
96 cl::desc("Use LoadSDNode and StoreSDNode instead of "
97 "AtomicSDNode for unordered atomic loads and "
98 "stores respectively."),
99 cl::Hidden);
100
101/// Call this when the user attempts to do something unsupported, like
102/// returning a double without SSE2 enabled on x86_64. This is not fatal, unlike
103/// report_fatal_error, so calling code should attempt to recover without
104/// crashing.
105static void errorUnsupported(SelectionDAG &DAG, const SDLoc &dl,
106 const char *Msg) {
107 MachineFunction &MF = DAG.getMachineFunction();
108 DAG.getContext()->diagnose(
109 DiagnosticInfoUnsupported(MF.getFunction(), Msg, dl.getDebugLoc()));
110}
111
112X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
113 const X86Subtarget &STI)
114 : TargetLowering(TM), Subtarget(STI) {
115 bool UseX87 = !Subtarget.useSoftFloat() && Subtarget.hasX87();
116 X86ScalarSSEf64 = Subtarget.hasSSE2();
117 X86ScalarSSEf32 = Subtarget.hasSSE1();
118 MVT PtrVT = MVT::getIntegerVT(TM.getPointerSizeInBits(0));
119
120 // Set up the TargetLowering object.
121
122 // X86 is weird. It always uses i8 for shift amounts and setcc results.
123 setBooleanContents(ZeroOrOneBooleanContent);
124 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
125 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
126
127 // For 64-bit, since we have so many registers, use the ILP scheduler.
128 // For 32-bit, use the register pressure specific scheduling.
129 // For Atom, always use ILP scheduling.
130 if (Subtarget.isAtom())
131 setSchedulingPreference(Sched::ILP);
132 else if (Subtarget.is64Bit())
133 setSchedulingPreference(Sched::ILP);
134 else
135 setSchedulingPreference(Sched::RegPressure);
136 const X86RegisterInfo *RegInfo = Subtarget.getRegisterInfo();
137 setStackPointerRegisterToSaveRestore(RegInfo->getStackRegister());
138
139 // Bypass expensive divides and use cheaper ones.
140 if (TM.getOptLevel() >= CodeGenOpt::Default) {
141 if (Subtarget.hasSlowDivide32())
142 addBypassSlowDiv(32, 8);
143 if (Subtarget.hasSlowDivide64() && Subtarget.is64Bit())
144 addBypassSlowDiv(64, 32);
145 }
146
147 // Setup Windows compiler runtime calls.
148 if (Subtarget.isTargetWindowsMSVC() || Subtarget.isTargetWindowsItanium()) {
149 static const struct {
150 const RTLIB::Libcall Op;
151 const char * const Name;
152 const CallingConv::ID CC;
153 } LibraryCalls[] = {
154 { RTLIB::SDIV_I64, "_alldiv", CallingConv::X86_StdCall },
155 { RTLIB::UDIV_I64, "_aulldiv", CallingConv::X86_StdCall },
156 { RTLIB::SREM_I64, "_allrem", CallingConv::X86_StdCall },
157 { RTLIB::UREM_I64, "_aullrem", CallingConv::X86_StdCall },
158 { RTLIB::MUL_I64, "_allmul", CallingConv::X86_StdCall },
159 };
160
161 for (const auto &LC : LibraryCalls) {
162 setLibcallName(LC.Op, LC.Name);
163 setLibcallCallingConv(LC.Op, LC.CC);
164 }
165 }
166
167 if (Subtarget.getTargetTriple().isOSMSVCRT()) {
168 // MSVCRT doesn't have powi; fall back to pow
169 setLibcallName(RTLIB::POWI_F32, nullptr);
170 setLibcallName(RTLIB::POWI_F64, nullptr);
171 }
172
173 // If we don't have cmpxchg8b(meaing this is a 386/486), limit atomic size to
174 // 32 bits so the AtomicExpandPass will expand it so we don't need cmpxchg8b.
175 // FIXME: Should we be limiting the atomic size on other configs? Default is
176 // 1024.
177 if (!Subtarget.hasCmpxchg8b())
178 setMaxAtomicSizeInBitsSupported(32);
179
180 // Set up the register classes.
181 addRegisterClass(MVT::i8, &X86::GR8RegClass);
182 addRegisterClass(MVT::i16, &X86::GR16RegClass);
183 addRegisterClass(MVT::i32, &X86::GR32RegClass);
184 if (Subtarget.is64Bit())
185 addRegisterClass(MVT::i64, &X86::GR64RegClass);
186
187 for (MVT VT : MVT::integer_valuetypes())
188 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
189
190 // We don't accept any truncstore of integer registers.
191 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
192 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
193 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
194 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
195 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
196 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
197
198 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
199
200 // SETOEQ and SETUNE require checking two conditions.
201 for (auto VT : {MVT::f32, MVT::f64, MVT::f80}) {
202 setCondCodeAction(ISD::SETOEQ, VT, Expand);
203 setCondCodeAction(ISD::SETUNE, VT, Expand);
204 }
205
206 // Integer absolute.
207 if (Subtarget.hasCMov()) {
208 setOperationAction(ISD::ABS , MVT::i16 , Custom);
209 setOperationAction(ISD::ABS , MVT::i32 , Custom);
210 if (Subtarget.is64Bit())
211 setOperationAction(ISD::ABS , MVT::i64 , Custom);
212 }
213
214 // Funnel shifts.
215 for (auto ShiftOp : {ISD::FSHL, ISD::FSHR}) {
216 // For slow shld targets we only lower for code size.
217 LegalizeAction ShiftDoubleAction = Subtarget.isSHLDSlow() ? Custom : Legal;
218
219 setOperationAction(ShiftOp , MVT::i8 , Custom);
220 setOperationAction(ShiftOp , MVT::i16 , Custom);
221 setOperationAction(ShiftOp , MVT::i32 , ShiftDoubleAction);
222 if (Subtarget.is64Bit())
223 setOperationAction(ShiftOp , MVT::i64 , ShiftDoubleAction);
224 }
225
226 if (!Subtarget.useSoftFloat()) {
227 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
228 // operation.
229 setOperationAction(ISD::UINT_TO_FP, MVT::i8, Promote);
230 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::i8, Promote);
231 setOperationAction(ISD::UINT_TO_FP, MVT::i16, Promote);
232 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::i16, Promote);
233 // We have an algorithm for SSE2, and we turn this into a 64-bit
234 // FILD or VCVTUSI2SS/SD for other targets.
235 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
236 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::i32, Custom);
237 // We have an algorithm for SSE2->double, and we turn this into a
238 // 64-bit FILD followed by conditional FADD for other targets.
239 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
240 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::i64, Custom);
241
242 // Promote i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
243 // this operation.
244 setOperationAction(ISD::SINT_TO_FP, MVT::i8, Promote);
245 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::i8, Promote);
246 // SSE has no i16 to fp conversion, only i32. We promote in the handler
247 // to allow f80 to use i16 and f64 to use i16 with sse1 only
248 setOperationAction(ISD::SINT_TO_FP, MVT::i16, Custom);
249 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::i16, Custom);
250 // f32 and f64 cases are Legal with SSE1/SSE2, f80 case is not
251 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
252 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::i32, Custom);
253 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
254 // are Legal, f80 is custom lowered.
255 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
256 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::i64, Custom);
257
258 // Promote i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
259 // this operation.
260 setOperationAction(ISD::FP_TO_SINT, MVT::i8, Promote);
261 // FIXME: This doesn't generate invalid exception when it should. PR44019.
262 setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::i8, Promote);
263 setOperationAction(ISD::FP_TO_SINT, MVT::i16, Custom);
264 setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::i16, Custom);
265 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
266 setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::i32, Custom);
267 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
268 // are Legal, f80 is custom lowered.
269 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
270 setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::i64, Custom);
271
272 // Handle FP_TO_UINT by promoting the destination to a larger signed
273 // conversion.
274 setOperationAction(ISD::FP_TO_UINT, MVT::i8, Promote);
275 // FIXME: This doesn't generate invalid exception when it should. PR44019.
276 setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::i8, Promote);
277 setOperationAction(ISD::FP_TO_UINT, MVT::i16, Promote);
278 // FIXME: This doesn't generate invalid exception when it should. PR44019.
279 setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::i16, Promote);
280 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
281 setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::i32, Custom);
282 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
283 setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::i64, Custom);
284
285 setOperationAction(ISD::LRINT, MVT::f32, Custom);
286 setOperationAction(ISD::LRINT, MVT::f64, Custom);
287 setOperationAction(ISD::LLRINT, MVT::f32, Custom);
288 setOperationAction(ISD::LLRINT, MVT::f64, Custom);
289
290 if (!Subtarget.is64Bit()) {
291 setOperationAction(ISD::LRINT, MVT::i64, Custom);
292 setOperationAction(ISD::LLRINT, MVT::i64, Custom);
293 }
294 }
295
296 if (Subtarget.hasSSE2()) {
297 // Custom lowering for saturating float to int conversions.
298 // We handle promotion to larger result types manually.
299 for (MVT VT : { MVT::i8, MVT::i16, MVT::i32 }) {
300 setOperationAction(ISD::FP_TO_UINT_SAT, VT, Custom);
301 setOperationAction(ISD::FP_TO_SINT_SAT, VT, Custom);
302 }
303 if (Subtarget.is64Bit()) {
304 setOperationAction(ISD::FP_TO_UINT_SAT, MVT::i64, Custom);
305 setOperationAction(ISD::FP_TO_SINT_SAT, MVT::i64, Custom);
306 }
307 }
308
309 // Handle address space casts between mixed sized pointers.
310 setOperationAction(ISD::ADDRSPACECAST, MVT::i32, Custom);
311 setOperationAction(ISD::ADDRSPACECAST, MVT::i64, Custom);
312
313 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
314 if (!X86ScalarSSEf64) {
315 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
316 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
317 if (Subtarget.is64Bit()) {
318 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
319 // Without SSE, i64->f64 goes through memory.
320 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
321 }
322 } else if (!Subtarget.is64Bit())
323 setOperationAction(ISD::BITCAST , MVT::i64 , Custom);
324
325 // Scalar integer divide and remainder are lowered to use operations that
326 // produce two results, to match the available instructions. This exposes
327 // the two-result form to trivial CSE, which is able to combine x/y and x%y
328 // into a single instruction.
329 //
330 // Scalar integer multiply-high is also lowered to use two-result
331 // operations, to match the available instructions. However, plain multiply
332 // (low) operations are left as Legal, as there are single-result
333 // instructions for this in x86. Using the two-result multiply instructions
334 // when both high and low results are needed must be arranged by dagcombine.
335 for (auto VT : { MVT::i8, MVT::i16, MVT::i32, MVT::i64 }) {
336 setOperationAction(ISD::MULHS, VT, Expand);
337 setOperationAction(ISD::MULHU, VT, Expand);
338 setOperationAction(ISD::SDIV, VT, Expand);
339 setOperationAction(ISD::UDIV, VT, Expand);
340 setOperationAction(ISD::SREM, VT, Expand);
341 setOperationAction(ISD::UREM, VT, Expand);
342 }
343
344 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
345 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
346 for (auto VT : { MVT::f32, MVT::f64, MVT::f80, MVT::f128,
347 MVT::i8, MVT::i16, MVT::i32, MVT::i64 }) {
348 setOperationAction(ISD::BR_CC, VT, Expand);
349 setOperationAction(ISD::SELECT_CC, VT, Expand);
350 }
351 if (Subtarget.is64Bit())
352 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
353 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
354 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
355 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
356
357 setOperationAction(ISD::FREM , MVT::f32 , Expand);
358 setOperationAction(ISD::FREM , MVT::f64 , Expand);
359 setOperationAction(ISD::FREM , MVT::f80 , Expand);
360 setOperationAction(ISD::FREM , MVT::f128 , Expand);
361 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
362
363 // Promote the i8 variants and force them on up to i32 which has a shorter
364 // encoding.
365 setOperationPromotedToType(ISD::CTTZ , MVT::i8 , MVT::i32);
366 setOperationPromotedToType(ISD::CTTZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
367 if (!Subtarget.hasBMI()) {
368 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
369 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
370 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Legal);
371 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Legal);
372 if (Subtarget.is64Bit()) {
373 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
374 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Legal);
375 }
376 }
377
378 if (Subtarget.hasLZCNT()) {
379 // When promoting the i8 variants, force them to i32 for a shorter
380 // encoding.
381 setOperationPromotedToType(ISD::CTLZ , MVT::i8 , MVT::i32);
382 setOperationPromotedToType(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
383 } else {
384 for (auto VT : {MVT::i8, MVT::i16, MVT::i32, MVT::i64}) {
385 if (VT == MVT::i64 && !Subtarget.is64Bit())
386 continue;
387 setOperationAction(ISD::CTLZ , VT, Custom);
388 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Custom);
389 }
390 }
391
392 for (auto Op : {ISD::FP16_TO_FP, ISD::STRICT_FP16_TO_FP, ISD::FP_TO_FP16,
393 ISD::STRICT_FP_TO_FP16}) {
394 // Special handling for half-precision floating point conversions.
395 // If we don't have F16C support, then lower half float conversions
396 // into library calls.
397 setOperationAction(
398 Op, MVT::f32,
399 (!Subtarget.useSoftFloat() && Subtarget.hasF16C()) ? Custom : Expand);
400 // There's never any support for operations beyond MVT::f32.
401 setOperationAction(Op, MVT::f64, Expand);
402 setOperationAction(Op, MVT::f80, Expand);
403 setOperationAction(Op, MVT::f128, Expand);
404 }
405
406 setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Expand);
407 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Expand);
408 setLoadExtAction(ISD::EXTLOAD, MVT::f80, MVT::f16, Expand);
409 setLoadExtAction(ISD::EXTLOAD, MVT::f128, MVT::f16, Expand);
410 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
411 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
412 setTruncStoreAction(MVT::f80, MVT::f16, Expand);
413 setTruncStoreAction(MVT::f128, MVT::f16, Expand);
414
415 setOperationAction(ISD::PARITY, MVT::i8, Custom);
416 if (Subtarget.hasPOPCNT()) {
417 setOperationPromotedToType(ISD::CTPOP, MVT::i8, MVT::i32);
418 } else {
419 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
420 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
421 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
422 if (Subtarget.is64Bit())
423 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
424 else
425 setOperationAction(ISD::CTPOP , MVT::i64 , Custom);
426
427 setOperationAction(ISD::PARITY, MVT::i16, Custom);
428 setOperationAction(ISD::PARITY, MVT::i32, Custom);
429 if (Subtarget.is64Bit())
430 setOperationAction(ISD::PARITY, MVT::i64, Custom);
431 }
432
433 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
434
435 if (!Subtarget.hasMOVBE())
436 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
437
438 // X86 wants to expand cmov itself.
439 for (auto VT : { MVT::f32, MVT::f64, MVT::f80, MVT::f128 }) {
440 setOperationAction(ISD::SELECT, VT, Custom);
441 setOperationAction(ISD::SETCC, VT, Custom);
442 setOperationAction(ISD::STRICT_FSETCC, VT, Custom);
443 setOperationAction(ISD::STRICT_FSETCCS, VT, Custom);
444 }
445 for (auto VT : { MVT::i8, MVT::i16, MVT::i32, MVT::i64 }) {
446 if (VT == MVT::i64 && !Subtarget.is64Bit())
447 continue;
448 setOperationAction(ISD::SELECT, VT, Custom);
449 setOperationAction(ISD::SETCC, VT, Custom);
450 }
451
452 // Custom action for SELECT MMX and expand action for SELECT_CC MMX
453 setOperationAction(ISD::SELECT, MVT::x86mmx, Custom);
454 setOperationAction(ISD::SELECT_CC, MVT::x86mmx, Expand);
455
456 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
457 // NOTE: EH_SJLJ_SETJMP/_LONGJMP are not recommended, since
458 // LLVM/Clang supports zero-cost DWARF and SEH exception handling.
459 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
460 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
461 setOperationAction(ISD::EH_SJLJ_SETUP_DISPATCH, MVT::Other, Custom);
462 if (TM.Options.ExceptionModel == ExceptionHandling::SjLj)
463 setLibcallName(RTLIB::UNWIND_RESUME, "_Unwind_SjLj_Resume");
464
465 // Darwin ABI issue.
466 for (auto VT : { MVT::i32, MVT::i64 }) {
467 if (VT == MVT::i64 && !Subtarget.is64Bit())
468 continue;
469 setOperationAction(ISD::ConstantPool , VT, Custom);
470 setOperationAction(ISD::JumpTable , VT, Custom);
471 setOperationAction(ISD::GlobalAddress , VT, Custom);
472 setOperationAction(ISD::GlobalTLSAddress, VT, Custom);
473 setOperationAction(ISD::ExternalSymbol , VT, Custom);
474 setOperationAction(ISD::BlockAddress , VT, Custom);
475 }
476
477 // 64-bit shl, sra, srl (iff 32-bit x86)
478 for (auto VT : { MVT::i32, MVT::i64 }) {
479 if (VT == MVT::i64 && !Subtarget.is64Bit())
480 continue;
481 setOperationAction(ISD::SHL_PARTS, VT, Custom);
482 setOperationAction(ISD::SRA_PARTS, VT, Custom);
483 setOperationAction(ISD::SRL_PARTS, VT, Custom);
484 }
485
486 if (Subtarget.hasSSEPrefetch() || Subtarget.has3DNow())
487 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
488
489 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
490
491 // Expand certain atomics
492 for (auto VT : { MVT::i8, MVT::i16, MVT::i32, MVT::i64 }) {
493 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Custom);
494 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
495 setOperationAction(ISD::ATOMIC_LOAD_ADD, VT, Custom);
496 setOperationAction(ISD::ATOMIC_LOAD_OR, VT, Custom);
497 setOperationAction(ISD::ATOMIC_LOAD_XOR, VT, Custom);
498 setOperationAction(ISD::ATOMIC_LOAD_AND, VT, Custom);
499 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
500 }
501
502 if (!Subtarget.is64Bit())
503 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Custom);
504
505 if (Subtarget.hasCmpxchg16b()) {
506 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, MVT::i128, Custom);
507 }
508
509 // FIXME - use subtarget debug flags
510 if (!Subtarget.isTargetDarwin() && !Subtarget.isTargetELF() &&
511 !Subtarget.isTargetCygMing() && !Subtarget.isTargetWin64() &&
512 TM.Options.ExceptionModel != ExceptionHandling::SjLj) {
513 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
514 }
515
516 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
517 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
518
519 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
520 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
521
522 setOperationAction(ISD::TRAP, MVT::Other, Legal);
523 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
524 setOperationAction(ISD::UBSANTRAP, MVT::Other, Legal);
525
526 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
527 setOperationAction(ISD::VASTART , MVT::Other, Custom);
528 setOperationAction(ISD::VAEND , MVT::Other, Expand);
529 bool Is64Bit = Subtarget.is64Bit();
530 setOperationAction(ISD::VAARG, MVT::Other, Is64Bit ? Custom : Expand);
531 setOperationAction(ISD::VACOPY, MVT::Other, Is64Bit ? Custom : Expand);
532
533 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
534 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
535
536 setOperationAction(ISD::DYNAMIC_STACKALLOC, PtrVT, Custom);
537
538 // GC_TRANSITION_START and GC_TRANSITION_END need custom lowering.
539 setOperationAction(ISD::GC_TRANSITION_START, MVT::Other, Custom);
540 setOperationAction(ISD::GC_TRANSITION_END, MVT::Other, Custom);
541
542 if (!Subtarget.useSoftFloat() && X86ScalarSSEf64) {
543 // f32 and f64 use SSE.
544 // Set up the FP register classes.
545 addRegisterClass(MVT::f32, Subtarget.hasAVX512() ? &X86::FR32XRegClass
546 : &X86::FR32RegClass);
547 addRegisterClass(MVT::f64, Subtarget.hasAVX512() ? &X86::FR64XRegClass
548 : &X86::FR64RegClass);
549
550 // Disable f32->f64 extload as we can only generate this in one instruction
551 // under optsize. So its easier to pattern match (fpext (load)) for that
552 // case instead of needing to emit 2 instructions for extload in the
553 // non-optsize case.
554 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f32, Expand);
555
556 for (auto VT : { MVT::f32, MVT::f64 }) {
557 // Use ANDPD to simulate FABS.
558 setOperationAction(ISD::FABS, VT, Custom);
559
560 // Use XORP to simulate FNEG.
561 setOperationAction(ISD::FNEG, VT, Custom);
562
563 // Use ANDPD and ORPD to simulate FCOPYSIGN.
564 setOperationAction(ISD::FCOPYSIGN, VT, Custom);
565
566 // These might be better off as horizontal vector ops.
567 setOperationAction(ISD::FADD, VT, Custom);
568 setOperationAction(ISD::FSUB, VT, Custom);
569
570 // We don't support sin/cos/fmod
571 setOperationAction(ISD::FSIN , VT, Expand);
572 setOperationAction(ISD::FCOS , VT, Expand);
573 setOperationAction(ISD::FSINCOS, VT, Expand);
574 }
575
576 // Lower this to MOVMSK plus an AND.
577 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
578 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
579
580 } else if (!Subtarget.useSoftFloat() && X86ScalarSSEf32 &&
581 (UseX87 || Is64Bit)) {
582 // Use SSE for f32, x87 for f64.
583 // Set up the FP register classes.
584 addRegisterClass(MVT::f32, &X86::FR32RegClass);
585 if (UseX87)
586 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
587
588 // Use ANDPS to simulate FABS.
589 setOperationAction(ISD::FABS , MVT::f32, Custom);
590
591 // Use XORP to simulate FNEG.
592 setOperationAction(ISD::FNEG , MVT::f32, Custom);
593
594 if (UseX87)
595 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
596
597 // Use ANDPS and ORPS to simulate FCOPYSIGN.
598 if (UseX87)
599 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
600 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
601
602 // We don't support sin/cos/fmod
603 setOperationAction(ISD::FSIN , MVT::f32, Expand);
604 setOperationAction(ISD::FCOS , MVT::f32, Expand);
605 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
606
607 if (UseX87) {
608 // Always expand sin/cos functions even though x87 has an instruction.
609 setOperationAction(ISD::FSIN, MVT::f64, Expand);
610 setOperationAction(ISD::FCOS, MVT::f64, Expand);
611 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
612 }
613 } else if (UseX87) {
614 // f32 and f64 in x87.
615 // Set up the FP register classes.
616 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
617 addRegisterClass(MVT::f32, &X86::RFP32RegClass);
618
619 for (auto VT : { MVT::f32, MVT::f64 }) {
620 setOperationAction(ISD::UNDEF, VT, Expand);
621 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
622
623 // Always expand sin/cos functions even though x87 has an instruction.
624 setOperationAction(ISD::FSIN , VT, Expand);
625 setOperationAction(ISD::FCOS , VT, Expand);
626 setOperationAction(ISD::FSINCOS, VT, Expand);
627 }
628 }
629
630 // Expand FP32 immediates into loads from the stack, save special cases.
631 if (isTypeLegal(MVT::f32)) {
632 if (UseX87 && (getRegClassFor(MVT::f32) == &X86::RFP32RegClass)) {
633 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
634 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
635 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
636 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
637 } else // SSE immediates.
638 addLegalFPImmediate(APFloat(+0.0f)); // xorps
639 }
640 // Expand FP64 immediates into loads from the stack, save special cases.
641 if (isTypeLegal(MVT::f64)) {
642 if (UseX87 && getRegClassFor(MVT::f64) == &X86::RFP64RegClass) {
643 addLegalFPImmediate(APFloat(+0.0)); // FLD0
644 addLegalFPImmediate(APFloat(+1.0)); // FLD1
645 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
646 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
647 } else // SSE immediates.
648 addLegalFPImmediate(APFloat(+0.0)); // xorpd
649 }
650 // Handle constrained floating-point operations of scalar.
651 setOperationAction(ISD::STRICT_FADD, MVT::f32, Legal);
652 setOperationAction(ISD::STRICT_FADD, MVT::f64, Legal);
653 setOperationAction(ISD::STRICT_FSUB, MVT::f32, Legal);
654 setOperationAction(ISD::STRICT_FSUB, MVT::f64, Legal);
655 setOperationAction(ISD::STRICT_FMUL, MVT::f32, Legal);
656 setOperationAction(ISD::STRICT_FMUL, MVT::f64, Legal);
657 setOperationAction(ISD::STRICT_FDIV, MVT::f32, Legal);
658 setOperationAction(ISD::STRICT_FDIV, MVT::f64, Legal);
659 setOperationAction(ISD::STRICT_FP_EXTEND, MVT::f64, Legal);
660 setOperationAction(ISD::STRICT_FP_ROUND, MVT::f32, Legal);
661 setOperationAction(ISD::STRICT_FP_ROUND, MVT::f64, Legal);
662 setOperationAction(ISD::STRICT_FSQRT, MVT::f32, Legal);
663 setOperationAction(ISD::STRICT_FSQRT, MVT::f64, Legal);
664
665 // We don't support FMA.
666 setOperationAction(ISD::FMA, MVT::f64, Expand);
667 setOperationAction(ISD::FMA, MVT::f32, Expand);
668
669 // f80 always uses X87.
670 if (UseX87) {
671 addRegisterClass(MVT::f80, &X86::RFP80RegClass);
672 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
673 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
674 {
675 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended());
676 addLegalFPImmediate(TmpFlt); // FLD0
677 TmpFlt.changeSign();
678 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
679
680 bool ignored;
681 APFloat TmpFlt2(+1.0);
682 TmpFlt2.convert(APFloat::x87DoubleExtended(), APFloat::rmNearestTiesToEven,
683 &ignored);
684 addLegalFPImmediate(TmpFlt2); // FLD1
685 TmpFlt2.changeSign();
686 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
687 }
688
689 // Always expand sin/cos functions even though x87 has an instruction.
690 setOperationAction(ISD::FSIN , MVT::f80, Expand);
691 setOperationAction(ISD::FCOS , MVT::f80, Expand);
692 setOperationAction(ISD::FSINCOS, MVT::f80, Expand);
693
694 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
695 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
696 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
697 setOperationAction(ISD::FRINT, MVT::f80, Expand);
698 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
699 setOperationAction(ISD::FMA, MVT::f80, Expand);
700 setOperationAction(ISD::LROUND, MVT::f80, Expand);
701 setOperationAction(ISD::LLROUND, MVT::f80, Expand);
702 setOperationAction(ISD::LRINT, MVT::f80, Custom);
703 setOperationAction(ISD::LLRINT, MVT::f80, Custom);
704
705 // Handle constrained floating-point operations of scalar.
706 setOperationAction(ISD::STRICT_FADD , MVT::f80, Legal);
707 setOperationAction(ISD::STRICT_FSUB , MVT::f80, Legal);
708 setOperationAction(ISD::STRICT_FMUL , MVT::f80, Legal);
709 setOperationAction(ISD::STRICT_FDIV , MVT::f80, Legal);
710 setOperationAction(ISD::STRICT_FSQRT , MVT::f80, Legal);
711 setOperationAction(ISD::STRICT_FP_EXTEND, MVT::f80, Legal);
712 // FIXME: When the target is 64-bit, STRICT_FP_ROUND will be overwritten
713 // as Custom.
714 setOperationAction(ISD::STRICT_FP_ROUND, MVT::f80, Legal);
715 }
716
717 // f128 uses xmm registers, but most operations require libcalls.
718 if (!Subtarget.useSoftFloat() && Subtarget.is64Bit() && Subtarget.hasSSE1()) {
719 addRegisterClass(MVT::f128, Subtarget.hasVLX() ? &X86::VR128XRegClass
720 : &X86::VR128RegClass);
721
722 addLegalFPImmediate(APFloat::getZero(APFloat::IEEEquad())); // xorps
723
724 setOperationAction(ISD::FADD, MVT::f128, LibCall);
725 setOperationAction(ISD::STRICT_FADD, MVT::f128, LibCall);
726 setOperationAction(ISD::FSUB, MVT::f128, LibCall);
727 setOperationAction(ISD::STRICT_FSUB, MVT::f128, LibCall);
728 setOperationAction(ISD::FDIV, MVT::f128, LibCall);
729 setOperationAction(ISD::STRICT_FDIV, MVT::f128, LibCall);
730 setOperationAction(ISD::FMUL, MVT::f128, LibCall);
731 setOperationAction(ISD::STRICT_FMUL, MVT::f128, LibCall);
732 setOperationAction(ISD::FMA, MVT::f128, LibCall);
733 setOperationAction(ISD::STRICT_FMA, MVT::f128, LibCall);
734
735 setOperationAction(ISD::FABS, MVT::f128, Custom);
736 setOperationAction(ISD::FNEG, MVT::f128, Custom);
737 setOperationAction(ISD::FCOPYSIGN, MVT::f128, Custom);
738
739 setOperationAction(ISD::FSIN, MVT::f128, LibCall);
740 setOperationAction(ISD::STRICT_FSIN, MVT::f128, LibCall);
741 setOperationAction(ISD::FCOS, MVT::f128, LibCall);
742 setOperationAction(ISD::STRICT_FCOS, MVT::f128, LibCall);
743 setOperationAction(ISD::FSINCOS, MVT::f128, LibCall);
744 // No STRICT_FSINCOS
745 setOperationAction(ISD::FSQRT, MVT::f128, LibCall);
746 setOperationAction(ISD::STRICT_FSQRT, MVT::f128, LibCall);
747
748 setOperationAction(ISD::FP_EXTEND, MVT::f128, Custom);
749 setOperationAction(ISD::STRICT_FP_EXTEND, MVT::f128, Custom);
750 // We need to custom handle any FP_ROUND with an f128 input, but
751 // LegalizeDAG uses the result type to know when to run a custom handler.
752 // So we have to list all legal floating point result types here.
753 if (isTypeLegal(MVT::f32)) {
754 setOperationAction(ISD::FP_ROUND, MVT::f32, Custom);
755 setOperationAction(ISD::STRICT_FP_ROUND, MVT::f32, Custom);
756 }
757 if (isTypeLegal(MVT::f64)) {
758 setOperationAction(ISD::FP_ROUND, MVT::f64, Custom);
759 setOperationAction(ISD::STRICT_FP_ROUND, MVT::f64, Custom);
760 }
761 if (isTypeLegal(MVT::f80)) {
762 setOperationAction(ISD::FP_ROUND, MVT::f80, Custom);
763 setOperationAction(ISD::STRICT_FP_ROUND, MVT::f80, Custom);
764 }
765
766 setOperationAction(ISD::SETCC, MVT::f128, Custom);
767
768 setLoadExtAction(ISD::EXTLOAD, MVT::f128, MVT::f32, Expand);
769 setLoadExtAction(ISD::EXTLOAD, MVT::f128, MVT::f64, Expand);
770 setLoadExtAction(ISD::EXTLOAD, MVT::f128, MVT::f80, Expand);
771 setTruncStoreAction(MVT::f128, MVT::f32, Expand);
772 setTruncStoreAction(MVT::f128, MVT::f64, Expand);
773 setTruncStoreAction(MVT::f128, MVT::f80, Expand);
774 }
775
776 // Always use a library call for pow.
777 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
778 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
779 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
780 setOperationAction(ISD::FPOW , MVT::f128 , Expand);
781
782 setOperationAction(ISD::FLOG, MVT::f80, Expand);
783 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
784 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
785 setOperationAction(ISD::FEXP, MVT::f80, Expand);
786 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
787 setOperationAction(ISD::FMINNUM, MVT::f80, Expand);
788 setOperationAction(ISD::FMAXNUM, MVT::f80, Expand);
789
790 // Some FP actions are always expanded for vector types.
791 for (auto VT : { MVT::v4f32, MVT::v8f32, MVT::v16f32,
792 MVT::v2f64, MVT::v4f64, MVT::v8f64 }) {
793 setOperationAction(ISD::FSIN, VT, Expand);
794 setOperationAction(ISD::FSINCOS, VT, Expand);
795 setOperationAction(ISD::FCOS, VT, Expand);
796 setOperationAction(ISD::FREM, VT, Expand);
797 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
798 setOperationAction(ISD::FPOW, VT, Expand);
799 setOperationAction(ISD::FLOG, VT, Expand);
800 setOperationAction(ISD::FLOG2, VT, Expand);
801 setOperationAction(ISD::FLOG10, VT, Expand);
802 setOperationAction(ISD::FEXP, VT, Expand);
803 setOperationAction(ISD::FEXP2, VT, Expand);
804 }
805
806 // First set operation action for all vector types to either promote
807 // (for widening) or expand (for scalarization). Then we will selectively
808 // turn on ones that can be effectively codegen'd.
809 for (MVT VT : MVT::fixedlen_vector_valuetypes()) {
810 setOperationAction(ISD::SDIV, VT, Expand);
811 setOperationAction(ISD::UDIV, VT, Expand);
812 setOperationAction(ISD::SREM, VT, Expand);
813 setOperationAction(ISD::UREM, VT, Expand);
814 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT,Expand);
815 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
816 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT,Expand);
817 setOperationAction(ISD::INSERT_SUBVECTOR, VT,Expand);
818 setOperationAction(ISD::FMA, VT, Expand);
819 setOperationAction(ISD::FFLOOR, VT, Expand);
820 setOperationAction(ISD::FCEIL, VT, Expand);
821 setOperationAction(ISD::FTRUNC, VT, Expand);
822 setOperationAction(ISD::FRINT, VT, Expand);
823 setOperationAction(ISD::FNEARBYINT, VT, Expand);
824 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
825 setOperationAction(ISD::MULHS, VT, Expand);
826 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
827 setOperationAction(ISD::MULHU, VT, Expand);
828 setOperationAction(ISD::SDIVREM, VT, Expand);
829 setOperationAction(ISD::UDIVREM, VT, Expand);
830 setOperationAction(ISD::CTPOP, VT, Expand);
831 setOperationAction(ISD::CTTZ, VT, Expand);
832 setOperationAction(ISD::CTLZ, VT, Expand);
833 setOperationAction(ISD::ROTL, VT, Expand);
834 setOperationAction(ISD::ROTR, VT, Expand);
835 setOperationAction(ISD::BSWAP, VT, Expand);
836 setOperationAction(ISD::SETCC, VT, Expand);
837 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
838 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
839 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
840 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
841 setOperationAction(ISD::SIGN_EXTEND_INREG, VT,Expand);
842 setOperationAction(ISD::TRUNCATE, VT, Expand);
843 setOperationAction(ISD::SIGN_EXTEND, VT, Expand);
844 setOperationAction(ISD::ZERO_EXTEND, VT, Expand);
845 setOperationAction(ISD::ANY_EXTEND, VT, Expand);
846 setOperationAction(ISD::SELECT_CC, VT, Expand);
847 for (MVT InnerVT : MVT::fixedlen_vector_valuetypes()) {
848 setTruncStoreAction(InnerVT, VT, Expand);
849
850 setLoadExtAction(ISD::SEXTLOAD, InnerVT, VT, Expand);
851 setLoadExtAction(ISD::ZEXTLOAD, InnerVT, VT, Expand);
852
853 // N.b. ISD::EXTLOAD legality is basically ignored except for i1-like
854 // types, we have to deal with them whether we ask for Expansion or not.
855 // Setting Expand causes its own optimisation problems though, so leave
856 // them legal.
857 if (VT.getVectorElementType() == MVT::i1)
858 setLoadExtAction(ISD::EXTLOAD, InnerVT, VT, Expand);
859
860 // EXTLOAD for MVT::f16 vectors is not legal because f16 vectors are
861 // split/scalarized right now.
862 if (VT.getVectorElementType() == MVT::f16)
863 setLoadExtAction(ISD::EXTLOAD, InnerVT, VT, Expand);
864 }
865 }
866
867 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
868 // with -msoft-float, disable use of MMX as well.
869 if (!Subtarget.useSoftFloat() && Subtarget.hasMMX()) {
870 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
871 // No operations on x86mmx supported, everything uses intrinsics.
872 }
873
874 if (!Subtarget.useSoftFloat() && Subtarget.hasSSE1()) {
875 addRegisterClass(MVT::v4f32, Subtarget.hasVLX() ? &X86::VR128XRegClass
876 : &X86::VR128RegClass);
877
878 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
879 setOperationAction(ISD::FABS, MVT::v4f32, Custom);
880 setOperationAction(ISD::FCOPYSIGN, MVT::v4f32, Custom);
881 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
882 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
883 setOperationAction(ISD::VSELECT, MVT::v4f32, Custom);
884 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
885 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
886
887 setOperationAction(ISD::LOAD, MVT::v2f32, Custom);
888 setOperationAction(ISD::STORE, MVT::v2f32, Custom);
889
890 setOperationAction(ISD::STRICT_FADD, MVT::v4f32, Legal);
891 setOperationAction(ISD::STRICT_FSUB, MVT::v4f32, Legal);
892 setOperationAction(ISD::STRICT_FMUL, MVT::v4f32, Legal);
893 setOperationAction(ISD::STRICT_FDIV, MVT::v4f32, Legal);
894 setOperationAction(ISD::STRICT_FSQRT, MVT::v4f32, Legal);
895 }
896
897 if (!Subtarget.useSoftFloat() && Subtarget.hasSSE2()) {
898 addRegisterClass(MVT::v2f64, Subtarget.hasVLX() ? &X86::VR128XRegClass
899 : &X86::VR128RegClass);
900
901 // FIXME: Unfortunately, -soft-float and -no-implicit-float mean XMM
902 // registers cannot be used even for integer operations.
903 addRegisterClass(MVT::v16i8, Subtarget.hasVLX() ? &X86::VR128XRegClass
904 : &X86::VR128RegClass);
905 addRegisterClass(MVT::v8i16, Subtarget.hasVLX() ? &X86::VR128XRegClass
906 : &X86::VR128RegClass);
907 addRegisterClass(MVT::v4i32, Subtarget.hasVLX() ? &X86::VR128XRegClass
908 : &X86::VR128RegClass);
909 addRegisterClass(MVT::v2i64, Subtarget.hasVLX() ? &X86::VR128XRegClass
910 : &X86::VR128RegClass);
911
912 for (auto VT : { MVT::v2i8, MVT::v4i8, MVT::v8i8,
913 MVT::v2i16, MVT::v4i16, MVT::v2i32 }) {
914 setOperationAction(ISD::SDIV, VT, Custom);
915 setOperationAction(ISD::SREM, VT, Custom);
916 setOperationAction(ISD::UDIV, VT, Custom);
917 setOperationAction(ISD::UREM, VT, Custom);
918 }
919
920 setOperationAction(ISD::MUL, MVT::v2i8, Custom);
921 setOperationAction(ISD::MUL, MVT::v4i8, Custom);
922 setOperationAction(ISD::MUL, MVT::v8i8, Custom);
923
924 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
925 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
926 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
927 setOperationAction(ISD::MULHU, MVT::v4i32, Custom);
928 setOperationAction(ISD::MULHS, MVT::v4i32, Custom);
929 setOperationAction(ISD::MULHU, MVT::v16i8, Custom);
930 setOperationAction(ISD::MULHS, MVT::v16i8, Custom);
931 setOperationAction(ISD::MULHU, MVT::v8i16, Legal);
932 setOperationAction(ISD::MULHS, MVT::v8i16, Legal);
933 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
934
935 setOperationAction(ISD::SMULO, MVT::v16i8, Custom);
936 setOperationAction(ISD::UMULO, MVT::v16i8, Custom);
937
938 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
939 setOperationAction(ISD::FABS, MVT::v2f64, Custom);
940 setOperationAction(ISD::FCOPYSIGN, MVT::v2f64, Custom);
941
942 for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64 }) {
943 setOperationAction(ISD::SMAX, VT, VT == MVT::v8i16 ? Legal : Custom);
944 setOperationAction(ISD::SMIN, VT, VT == MVT::v8i16 ? Legal : Custom);
945 setOperationAction(ISD::UMAX, VT, VT == MVT::v16i8 ? Legal : Custom);
946 setOperationAction(ISD::UMIN, VT, VT == MVT::v16i8 ? Legal : Custom);
947 }
948
949 setOperationAction(ISD::UADDSAT, MVT::v16i8, Legal);
950 setOperationAction(ISD::SADDSAT, MVT::v16i8, Legal);
951 setOperationAction(ISD::USUBSAT, MVT::v16i8, Legal);
952 setOperationAction(ISD::SSUBSAT, MVT::v16i8, Legal);
953 setOperationAction(ISD::UADDSAT, MVT::v8i16, Legal);
954 setOperationAction(ISD::SADDSAT, MVT::v8i16, Legal);
955 setOperationAction(ISD::USUBSAT, MVT::v8i16, Legal);
956 setOperationAction(ISD::SSUBSAT, MVT::v8i16, Legal);
957 setOperationAction(ISD::USUBSAT, MVT::v4i32, Custom);
958 setOperationAction(ISD::USUBSAT, MVT::v2i64, Custom);
959
960 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
961 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
962 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
963
964 for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64 }) {
965 setOperationAction(ISD::SETCC, VT, Custom);
966 setOperationAction(ISD::STRICT_FSETCC, VT, Custom);
967 setOperationAction(ISD::STRICT_FSETCCS, VT, Custom);
968 setOperationAction(ISD::CTPOP, VT, Custom);
969 setOperationAction(ISD::ABS, VT, Custom);
970
971 // The condition codes aren't legal in SSE/AVX and under AVX512 we use
972 // setcc all the way to isel and prefer SETGT in some isel patterns.
973 setCondCodeAction(ISD::SETLT, VT, Custom);
974 setCondCodeAction(ISD::SETLE, VT, Custom);
975 }
976
977 for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32 }) {
978 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
979 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
980 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
981 setOperationAction(ISD::VSELECT, VT, Custom);
982 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
983 }
984
985 for (auto VT : { MVT::v2f64, MVT::v2i64 }) {
986 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
987 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
988 setOperationAction(ISD::VSELECT, VT, Custom);
989
990 if (VT == MVT::v2i64 && !Subtarget.is64Bit())
991 continue;
992
993 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
994 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
995 }
996
997 // Custom lower v2i64 and v2f64 selects.
998 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
999 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
1000 setOperationAction(ISD::SELECT, MVT::v4i32, Custom);
1001 setOperationAction(ISD::SELECT, MVT::v8i16, Custom);
1002 setOperationAction(ISD::SELECT, MVT::v16i8, Custom);
1003
1004 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
1005 setOperationAction(ISD::FP_TO_SINT, MVT::v2i32, Custom);
1006 setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::v4i32, Legal);
1007 setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::v2i32, Custom);
1008
1009 // Custom legalize these to avoid over promotion or custom promotion.
1010 for (auto VT : {MVT::v2i8, MVT::v4i8, MVT::v8i8, MVT::v2i16, MVT::v4i16}) {
1011 setOperationAction(ISD::FP_TO_SINT, VT, Custom);
1012 setOperationAction(ISD::FP_TO_UINT, VT, Custom);
1013 setOperationAction(ISD::STRICT_FP_TO_SINT, VT, Custom);
1014 setOperationAction(ISD::STRICT_FP_TO_UINT, VT, Custom);
1015 }
1016
1017 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
1018 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::v4i32, Legal);
1019 setOperationAction(ISD::SINT_TO_FP, MVT::v2i32, Custom);
1020 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::v2i32, Custom);
1021
1022 setOperationAction(ISD::UINT_TO_FP, MVT::v2i32, Custom);
1023 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::v2i32, Custom);
1024
1025 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Custom);
1026 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::v4i32, Custom);
1027
1028 // Fast v2f32 UINT_TO_FP( v2i32 ) custom conversion.
1029 setOperationAction(ISD::SINT_TO_FP, MVT::v2f32, Custom);
1030 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::v2f32, Custom);
1031 setOperationAction(ISD::UINT_TO_FP, MVT::v2f32, Custom);
1032 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::v2f32, Custom);
1033
1034 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
1035 setOperationAction(ISD::STRICT_FP_EXTEND, MVT::v2f32, Custom);
1036 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Custom);
1037 setOperationAction(ISD::STRICT_FP_ROUND, MVT::v2f32, Custom);
1038
1039 // We want to legalize this to an f64 load rather than an i64 load on
1040 // 64-bit targets and two 32-bit loads on a 32-bit target. Similar for
1041 // store.
1042 setOperationAction(ISD::LOAD, MVT::v2i32, Custom);
1043 setOperationAction(ISD::LOAD, MVT::v4i16, Custom);
1044 setOperationAction(ISD::LOAD, MVT::v8i8, Custom);
1045 setOperationAction(ISD::STORE, MVT::v2i32, Custom);
1046 setOperationAction(ISD::STORE, MVT::v4i16, Custom);
1047 setOperationAction(ISD::STORE, MVT::v8i8, Custom);
1048
1049 setOperationAction(ISD::BITCAST, MVT::v2i32, Custom);
1050 setOperationAction(ISD::BITCAST, MVT::v4i16, Custom);
1051 setOperationAction(ISD::BITCAST, MVT::v8i8, Custom);
1052 if (!Subtarget.hasAVX512())
1053 setOperationAction(ISD::BITCAST, MVT::v16i1, Custom);
1054
1055 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v2i64, Custom);
1056 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v4i32, Custom);
1057 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v8i16, Custom);
1058
1059 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i64, Custom);
1060
1061 setOperationAction(ISD::TRUNCATE, MVT::v2i8, Custom);
1062 setOperationAction(ISD::TRUNCATE, MVT::v2i16, Custom);
1063 setOperationAction(ISD::TRUNCATE, MVT::v2i32, Custom);
1064 setOperationAction(ISD::TRUNCATE, MVT::v4i8, Custom);
1065 setOperationAction(ISD::TRUNCATE, MVT::v4i16, Custom);
1066 setOperationAction(ISD::TRUNCATE, MVT::v8i8, Custom);
1067
1068 // In the customized shift lowering, the legal v4i32/v2i64 cases
1069 // in AVX2 will be recognized.
1070 for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64 }) {
1071 setOperationAction(ISD::SRL, VT, Custom);
1072 setOperationAction(ISD::SHL, VT, Custom);
1073 setOperationAction(ISD::SRA, VT, Custom);
1074 }
1075
1076 setOperationAction(ISD::ROTL, MVT::v4i32, Custom);
1077 setOperationAction(ISD::ROTL, MVT::v8i16, Custom);
1078
1079 // With 512-bit registers or AVX512VL+BW, expanding (and promoting the
1080 // shifts) is better.
1081 if (!Subtarget.useAVX512Regs() &&
1082 !(Subtarget.hasBWI() && Subtarget.hasVLX()))
1083 setOperationAction(ISD::ROTL, MVT::v16i8, Custom);
1084
1085 setOperationAction(ISD::STRICT_FSQRT, MVT::v2f64, Legal);
1086 setOperationAction(ISD::STRICT_FADD, MVT::v2f64, Legal);
1087 setOperationAction(ISD::STRICT_FSUB, MVT::v2f64, Legal);
1088 setOperationAction(ISD::STRICT_FMUL, MVT::v2f64, Legal);
1089 setOperationAction(ISD::STRICT_FDIV, MVT::v2f64, Legal);
1090 }
1091
1092 if (!Subtarget.useSoftFloat() && Subtarget.hasSSSE3()) {
1093 setOperationAction(ISD::ABS, MVT::v16i8, Legal);
1094 setOperationAction(ISD::ABS, MVT::v8i16, Legal);
1095 setOperationAction(ISD::ABS, MVT::v4i32, Legal);
1096 setOperationAction(ISD::BITREVERSE, MVT::v16i8, Custom);
1097 setOperationAction(ISD::CTLZ, MVT::v16i8, Custom);
1098 setOperationAction(ISD::CTLZ, MVT::v8i16, Custom);
1099 setOperationAction(ISD::CTLZ, MVT::v4i32, Custom);
1100 setOperationAction(ISD::CTLZ, MVT::v2i64, Custom);
1101
1102 // These might be better off as horizontal vector ops.
1103 setOperationAction(ISD::ADD, MVT::i16, Custom);
1104 setOperationAction(ISD::ADD, MVT::i32, Custom);
1105 setOperationAction(ISD::SUB, MVT::i16, Custom);
1106 setOperationAction(ISD::SUB, MVT::i32, Custom);
1107 }
1108
1109 if (!Subtarget.useSoftFloat() && Subtarget.hasSSE41()) {
1110 for (MVT RoundedTy : {MVT::f32, MVT::f64, MVT::v4f32, MVT::v2f64}) {
1111 setOperationAction(ISD::FFLOOR, RoundedTy, Legal);
1112 setOperationAction(ISD::STRICT_FFLOOR, RoundedTy, Legal);
1113 setOperationAction(ISD::FCEIL, RoundedTy, Legal);
1114 setOperationAction(ISD::STRICT_FCEIL, RoundedTy, Legal);
1115 setOperationAction(ISD::FTRUNC, RoundedTy, Legal);
1116 setOperationAction(ISD::STRICT_FTRUNC, RoundedTy, Legal);
1117 setOperationAction(ISD::FRINT, RoundedTy, Legal);
1118 setOperationAction(ISD::STRICT_FRINT, RoundedTy, Legal);
1119 setOperationAction(ISD::FNEARBYINT, RoundedTy, Legal);
1120 setOperationAction(ISD::STRICT_FNEARBYINT, RoundedTy, Legal);
1121 setOperationAction(ISD::FROUNDEVEN, RoundedTy, Legal);
1122 setOperationAction(ISD::STRICT_FROUNDEVEN, RoundedTy, Legal);
1123
1124 setOperationAction(ISD::FROUND, RoundedTy, Custom);
1125 }
1126
1127 setOperationAction(ISD::SMAX, MVT::v16i8, Legal);
1128 setOperationAction(ISD::SMAX, MVT::v4i32, Legal);
1129 setOperationAction(ISD::UMAX, MVT::v8i16, Legal);
1130 setOperationAction(ISD::UMAX, MVT::v4i32, Legal);
1131 setOperationAction(ISD::SMIN, MVT::v16i8, Legal);
1132 setOperationAction(ISD::SMIN, MVT::v4i32, Legal);
1133 setOperationAction(ISD::UMIN, MVT::v8i16, Legal);
1134 setOperationAction(ISD::UMIN, MVT::v4i32, Legal);
1135
1136 setOperationAction(ISD::UADDSAT, MVT::v4i32, Custom);
1137
1138 // FIXME: Do we need to handle scalar-to-vector here?
1139 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
1140
1141 // We directly match byte blends in the backend as they match the VSELECT
1142 // condition form.
1143 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
1144
1145 // SSE41 brings specific instructions for doing vector sign extend even in
1146 // cases where we don't have SRA.
1147 for (auto VT : { MVT::v8i16, MVT::v4i32, MVT::v2i64 }) {
1148 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, VT, Legal);
1149 setOperationAction(ISD::ZERO_EXTEND_VECTOR_INREG, VT, Legal);
1150 }
1151
1152 // SSE41 also has vector sign/zero extending loads, PMOV[SZ]X
1153 for (auto LoadExtOp : { ISD::SEXTLOAD, ISD::ZEXTLOAD }) {
1154 setLoadExtAction(LoadExtOp, MVT::v8i16, MVT::v8i8, Legal);
1155 setLoadExtAction(LoadExtOp, MVT::v4i32, MVT::v4i8, Legal);
1156 setLoadExtAction(LoadExtOp, MVT::v2i64, MVT::v2i8, Legal);
1157 setLoadExtAction(LoadExtOp, MVT::v4i32, MVT::v4i16, Legal);
1158 setLoadExtAction(LoadExtOp, MVT::v2i64, MVT::v2i16, Legal);
1159 setLoadExtAction(LoadExtOp, MVT::v2i64, MVT::v2i32, Legal);
1160 }
1161
1162 // i8 vectors are custom because the source register and source
1163 // source memory operand types are not the same width.
1164 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
1165
1166 if (Subtarget.is64Bit() && !Subtarget.hasAVX512()) {
1167 // We need to scalarize v4i64->v432 uint_to_fp using cvtsi2ss, but we can
1168 // do the pre and post work in the vector domain.
1169 setOperationAction(ISD::UINT_TO_FP, MVT::v4i64, Custom);
1170 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::v4i64, Custom);
1171 // We need to mark SINT_TO_FP as Custom even though we want to expand it
1172 // so that DAG combine doesn't try to turn it into uint_to_fp.
1173 setOperationAction(ISD::SINT_TO_FP, MVT::v4i64, Custom);
1174 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::v4i64, Custom);
1175 }
1176 }
1177
1178 if (!Subtarget.useSoftFloat() && Subtarget.hasSSE42()) {
1179 setOperationAction(ISD::UADDSAT, MVT::v2i64, Custom);
1180 }
1181
1182 if (!Subtarget.useSoftFloat() && Subtarget.hasXOP()) {
1183 for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64,
1184 MVT::v32i8, MVT::v16i16, MVT::v8i32, MVT::v4i64 })
1185 setOperationAction(ISD::ROTL, VT, Custom);
1186
1187 // XOP can efficiently perform BITREVERSE with VPPERM.
1188 for (auto VT : { MVT::i8, MVT::i16, MVT::i32, MVT::i64 })
1189 setOperationAction(ISD::BITREVERSE, VT, Custom);
1190
1191 for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64,
1192 MVT::v32i8, MVT::v16i16, MVT::v8i32, MVT::v4i64 })
1193 setOperationAction(ISD::BITREVERSE, VT, Custom);
1194 }
1195
1196 if (!Subtarget.useSoftFloat() && Subtarget.hasAVX()) {
1197 bool HasInt256 = Subtarget.hasInt256();
1198
1199 addRegisterClass(MVT::v32i8, Subtarget.hasVLX() ? &X86::VR256XRegClass
1200 : &X86::VR256RegClass);
1201 addRegisterClass(MVT::v16i16, Subtarget.hasVLX() ? &X86::VR256XRegClass
1202 : &X86::VR256RegClass);
1203 addRegisterClass(MVT::v8i32, Subtarget.hasVLX() ? &X86::VR256XRegClass
1204 : &X86::VR256RegClass);
1205 addRegisterClass(MVT::v8f32, Subtarget.hasVLX() ? &X86::VR256XRegClass
1206 : &X86::VR256RegClass);
1207 addRegisterClass(MVT::v4i64, Subtarget.hasVLX() ? &X86::VR256XRegClass
1208 : &X86::VR256RegClass);
1209 addRegisterClass(MVT::v4f64, Subtarget.hasVLX() ? &X86::VR256XRegClass
1210 : &X86::VR256RegClass);
1211
1212 for (auto VT : { MVT::v8f32, MVT::v4f64 }) {
1213 setOperationAction(ISD::FFLOOR, VT, Legal);
1214 setOperationAction(ISD::STRICT_FFLOOR, VT, Legal);
1215 setOperationAction(ISD::FCEIL, VT, Legal);
1216 setOperationAction(ISD::STRICT_FCEIL, VT, Legal);
1217 setOperationAction(ISD::FTRUNC, VT, Legal);
1218 setOperationAction(ISD::STRICT_FTRUNC, VT, Legal);
1219 setOperationAction(ISD::FRINT, VT, Legal);
1220 setOperationAction(ISD::STRICT_FRINT, VT, Legal);
1221 setOperationAction(ISD::FNEARBYINT, VT, Legal);
1222 setOperationAction(ISD::STRICT_FNEARBYINT, VT, Legal);
1223 setOperationAction(ISD::FROUNDEVEN, VT, Legal);
1224 setOperationAction(ISD::STRICT_FROUNDEVEN, VT, Legal);
1225
1226 setOperationAction(ISD::FROUND, VT, Custom);
1227
1228 setOperationAction(ISD::FNEG, VT, Custom);
1229 setOperationAction(ISD::FABS, VT, Custom);
1230 setOperationAction(ISD::FCOPYSIGN, VT, Custom);
1231 }
1232
1233 // (fp_to_int:v8i16 (v8f32 ..)) requires the result type to be promoted
1234 // even though v8i16 is a legal type.
1235 setOperationPromotedToType(ISD::FP_TO_SINT, MVT::v8i16, MVT::v8i32);
1236 setOperationPromotedToType(ISD::FP_TO_UINT, MVT::v8i16, MVT::v8i32);
1237 setOperationPromotedToType(ISD::STRICT_FP_TO_SINT, MVT::v8i16, MVT::v8i32);
1238 setOperationPromotedToType(ISD::STRICT_FP_TO_UINT, MVT::v8i16, MVT::v8i32);
1239 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1240 setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::v8i32, Legal);
1241
1242 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1243 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::v8i32, Legal);
1244
1245 setOperationAction(ISD::STRICT_FP_ROUND, MVT::v4f32, Legal);
1246 setOperationAction(ISD::STRICT_FADD, MVT::v8f32, Legal);
1247 setOperationAction(ISD::STRICT_FADD, MVT::v4f64, Legal);
1248 setOperationAction(ISD::STRICT_FSUB, MVT::v8f32, Legal);
1249 setOperationAction(ISD::STRICT_FSUB, MVT::v4f64, Legal);
1250 setOperationAction(ISD::STRICT_FMUL, MVT::v8f32, Legal);
1251 setOperationAction(ISD::STRICT_FMUL, MVT::v4f64, Legal);
1252 setOperationAction(ISD::STRICT_FDIV, MVT::v8f32, Legal);
1253 setOperationAction(ISD::STRICT_FDIV, MVT::v4f64, Legal);
1254 setOperationAction(ISD::STRICT_FP_EXTEND, MVT::v4f64, Legal);
1255 setOperationAction(ISD::STRICT_FSQRT, MVT::v8f32, Legal);
1256 setOperationAction(ISD::STRICT_FSQRT, MVT::v4f64, Legal);
1257
1258 if (!Subtarget.hasAVX512())
1259 setOperationAction(ISD::BITCAST, MVT::v32i1, Custom);
1260
1261 // In the customized shift lowering, the legal v8i32/v4i64 cases
1262 // in AVX2 will be recognized.
1263 for (auto VT : { MVT::v32i8, MVT::v16i16, MVT::v8i32, MVT::v4i64 }) {
1264 setOperationAction(ISD::SRL, VT, Custom);
1265 setOperationAction(ISD::SHL, VT, Custom);
1266 setOperationAction(ISD::SRA, VT, Custom);
1267 }
1268
1269 // These types need custom splitting if their input is a 128-bit vector.
1270 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i64, Custom);
1271 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom);
1272 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i64, Custom);
1273 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i32, Custom);
1274
1275 setOperationAction(ISD::ROTL, MVT::v8i32, Custom);
1276 setOperationAction(ISD::ROTL, MVT::v16i16, Custom);
1277
1278 // With BWI, expanding (and promoting the shifts) is the better.
1279 if (!Subtarget.useBWIRegs())
1280 setOperationAction(ISD::ROTL, MVT::v32i8, Custom);
1281
1282 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1283 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1284 setOperationAction(ISD::SELECT, MVT::v8i32, Custom);
1285 setOperationAction(ISD::SELECT, MVT::v16i16, Custom);
1286 setOperationAction(ISD::SELECT, MVT::v32i8, Custom);
1287 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1288
1289 for (auto VT : { MVT::v16i16, MVT::v8i32, MVT::v4i64 }) {
1290 setOperationAction(ISD::SIGN_EXTEND, VT, Custom);
1291 setOperationAction(ISD::ZERO_EXTEND, VT, Custom);
1292 setOperationAction(ISD::ANY_EXTEND, VT, Custom);
1293 }
1294
1295 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1296 setOperationAction(ISD::TRUNCATE, MVT::v8i16, Custom);
1297 setOperationAction(ISD::TRUNCATE, MVT::v4i32, Custom);
1298 setOperationAction(ISD::BITREVERSE, MVT::v32i8, Custom);
1299
1300 for (auto VT : { MVT::v32i8, MVT::v16i16, MVT::v8i32, MVT::v4i64 }) {
1301 setOperationAction(ISD::SETCC, VT, Custom);
1302 setOperationAction(ISD::STRICT_FSETCC, VT, Custom);
1303 setOperationAction(ISD::STRICT_FSETCCS, VT, Custom);
1304 setOperationAction(ISD::CTPOP, VT, Custom);
1305 setOperationAction(ISD::CTLZ, VT, Custom);
1306
1307 // The condition codes aren't legal in SSE/AVX and under AVX512 we use
1308 // setcc all the way to isel and prefer SETGT in some isel patterns.
1309 setCondCodeAction(ISD::SETLT, VT, Custom);
1310 setCondCodeAction(ISD::SETLE, VT, Custom);
1311 }
1312
1313 if (Subtarget.hasAnyFMA()) {
1314 for (auto VT : { MVT::f32, MVT::f64, MVT::v4f32, MVT::v8f32,
1315 MVT::v2f64, MVT::v4f64 }) {
1316 setOperationAction(ISD::FMA, VT, Legal);
1317 setOperationAction(ISD::STRICT_FMA, VT, Legal);
1318 }
1319 }
1320
1321 for (auto VT : { MVT::v32i8, MVT::v16i16, MVT::v8i32, MVT::v4i64 }) {
1322 setOperationAction(ISD::ADD, VT, HasInt256 ? Legal : Custom);
1323 setOperationAction(ISD::SUB, VT, HasInt256 ? Legal : Custom);
1324 }
1325
1326 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1327 setOperationAction(ISD::MUL, MVT::v8i32, HasInt256 ? Legal : Custom);
1328 setOperationAction(ISD::MUL, MVT::v16i16, HasInt256 ? Legal : Custom);
1329 setOperationAction(ISD::MUL, MVT::v32i8, Custom);
1330
1331 setOperationAction(ISD::MULHU, MVT::v8i32, Custom);
1332 setOperationAction(ISD::MULHS, MVT::v8i32, Custom);
1333 setOperationAction(ISD::MULHU, MVT::v16i16, HasInt256 ? Legal : Custom);
1334 setOperationAction(ISD::MULHS, MVT::v16i16, HasInt256 ? Legal : Custom);
1335 setOperationAction(ISD::MULHU, MVT::v32i8, Custom);
1336 setOperationAction(ISD::MULHS, MVT::v32i8, Custom);
1337
1338 setOperationAction(ISD::SMULO, MVT::v32i8, Custom);
1339 setOperationAction(ISD::UMULO, MVT::v32i8, Custom);
1340
1341 setOperationAction(ISD::ABS, MVT::v4i64, Custom);
1342 setOperationAction(ISD::SMAX, MVT::v4i64, Custom);
1343 setOperationAction(ISD::UMAX, MVT::v4i64, Custom);
1344 setOperationAction(ISD::SMIN, MVT::v4i64, Custom);
1345 setOperationAction(ISD::UMIN, MVT::v4i64, Custom);
1346
1347 setOperationAction(ISD::UADDSAT, MVT::v32i8, HasInt256 ? Legal : Custom);
1348 setOperationAction(ISD::SADDSAT, MVT::v32i8, HasInt256 ? Legal : Custom);
1349 setOperationAction(ISD::USUBSAT, MVT::v32i8, HasInt256 ? Legal : Custom);
1350 setOperationAction(ISD::SSUBSAT, MVT::v32i8, HasInt256 ? Legal : Custom);
1351 setOperationAction(ISD::UADDSAT, MVT::v16i16, HasInt256 ? Legal : Custom);
1352 setOperationAction(ISD::SADDSAT, MVT::v16i16, HasInt256 ? Legal : Custom);
1353 setOperationAction(ISD::USUBSAT, MVT::v16i16, HasInt256 ? Legal : Custom);
1354 setOperationAction(ISD::SSUBSAT, MVT::v16i16, HasInt256 ? Legal : Custom);
1355 setOperationAction(ISD::UADDSAT, MVT::v8i32, Custom);
1356 setOperationAction(ISD::USUBSAT, MVT::v8i32, Custom);
1357 setOperationAction(ISD::UADDSAT, MVT::v4i64, Custom);
1358 setOperationAction(ISD::USUBSAT, MVT::v4i64, Custom);
1359
1360 for (auto VT : { MVT::v32i8, MVT::v16i16, MVT::v8i32 }) {
1361 setOperationAction(ISD::ABS, VT, HasInt256 ? Legal : Custom);
1362 setOperationAction(ISD::SMAX, VT, HasInt256 ? Legal : Custom);
1363 setOperationAction(ISD::UMAX, VT, HasInt256 ? Legal : Custom);
1364 setOperationAction(ISD::SMIN, VT, HasInt256 ? Legal : Custom);
1365 setOperationAction(ISD::UMIN, VT, HasInt256 ? Legal : Custom);
1366 }
1367
1368 for (auto VT : {MVT::v16i16, MVT::v8i32, MVT::v4i64}) {
1369 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, VT, Custom);
1370 setOperationAction(ISD::ZERO_EXTEND_VECTOR_INREG, VT, Custom);
1371 }
1372
1373 if (HasInt256) {
1374 // The custom lowering for UINT_TO_FP for v8i32 becomes interesting
1375 // when we have a 256bit-wide blend with immediate.
1376 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Custom);
1377 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::v8i32, Custom);
1378
1379 // AVX2 also has wider vector sign/zero extending loads, VPMOV[SZ]X
1380 for (auto LoadExtOp : { ISD::SEXTLOAD, ISD::ZEXTLOAD }) {
1381 setLoadExtAction(LoadExtOp, MVT::v16i16, MVT::v16i8, Legal);
1382 setLoadExtAction(LoadExtOp, MVT::v8i32, MVT::v8i8, Legal);
1383 setLoadExtAction(LoadExtOp, MVT::v4i64, MVT::v4i8, Legal);
1384 setLoadExtAction(LoadExtOp, MVT::v8i32, MVT::v8i16, Legal);
1385 setLoadExtAction(LoadExtOp, MVT::v4i64, MVT::v4i16, Legal);
1386 setLoadExtAction(LoadExtOp, MVT::v4i64, MVT::v4i32, Legal);
1387 }
1388 }
1389
1390 for (auto VT : { MVT::v4i32, MVT::v8i32, MVT::v2i64, MVT::v4i64,
1391 MVT::v4f32, MVT::v8f32, MVT::v2f64, MVT::v4f64 }) {
1392 setOperationAction(ISD::MLOAD, VT, Subtarget.hasVLX() ? Legal : Custom);
1393 setOperationAction(ISD::MSTORE, VT, Legal);
1394 }
1395
1396 // Extract subvector is special because the value type
1397 // (result) is 128-bit but the source is 256-bit wide.
1398 for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64,
1399 MVT::v4f32, MVT::v2f64 }) {
1400 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
1401 }
1402
1403 // Custom lower several nodes for 256-bit types.
1404 for (MVT VT : { MVT::v32i8, MVT::v16i16, MVT::v8i32, MVT::v4i64,
1405 MVT::v8f32, MVT::v4f64 }) {
1406 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1407 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1408 setOperationAction(ISD::VSELECT, VT, Custom);
1409 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1410 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1411 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1412 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Legal);
1413 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1414 setOperationAction(ISD::STORE, VT, Custom);
1415 }
1416
1417 if (HasInt256) {
1418 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1419
1420 // Custom legalize 2x32 to get a little better code.
1421 setOperationAction(ISD::MGATHER, MVT::v2f32, Custom);
1422 setOperationAction(ISD::MGATHER, MVT::v2i32, Custom);
1423
1424 for (auto VT : { MVT::v4i32, MVT::v8i32, MVT::v2i64, MVT::v4i64,
1425 MVT::v4f32, MVT::v8f32, MVT::v2f64, MVT::v4f64 })
1426 setOperationAction(ISD::MGATHER, VT, Custom);
1427 }
1428 }
1429
1430 // This block controls legalization of the mask vector sizes that are
1431 // available with AVX512. 512-bit vectors are in a separate block controlled
1432 // by useAVX512Regs.
1433 if (!Subtarget.useSoftFloat() && Subtarget.hasAVX512()) {
1434 addRegisterClass(MVT::v1i1, &X86::VK1RegClass);
1435 addRegisterClass(MVT::v2i1, &X86::VK2RegClass);
1436 addRegisterClass(MVT::v4i1, &X86::VK4RegClass);
1437 addRegisterClass(MVT::v8i1, &X86::VK8RegClass);
1438 addRegisterClass(MVT::v16i1, &X86::VK16RegClass);
1439
1440 setOperationAction(ISD::SELECT, MVT::v1i1, Custom);
1441 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v1i1, Custom);
1442 setOperationAction(ISD::BUILD_VECTOR, MVT::v1i1, Custom);
1443
1444 setOperationPromotedToType(ISD::FP_TO_SINT, MVT::v8i1, MVT::v8i32);
1445 setOperationPromotedToType(ISD::FP_TO_UINT, MVT::v8i1, MVT::v8i32);
1446 setOperationPromotedToType(ISD::FP_TO_SINT, MVT::v4i1, MVT::v4i32);
1447 setOperationPromotedToType(ISD::FP_TO_UINT, MVT::v4i1, MVT::v4i32);
1448 setOperationPromotedToType(ISD::STRICT_FP_TO_SINT, MVT::v8i1, MVT::v8i32);
1449 setOperationPromotedToType(ISD::STRICT_FP_TO_UINT, MVT::v8i1, MVT::v8i32);
1450 setOperationPromotedToType(ISD::STRICT_FP_TO_SINT, MVT::v4i1, MVT::v4i32);
1451 setOperationPromotedToType(ISD::STRICT_FP_TO_UINT, MVT::v4i1, MVT::v4i32);
1452 setOperationAction(ISD::FP_TO_SINT, MVT::v2i1, Custom);
1453 setOperationAction(ISD::FP_TO_UINT, MVT::v2i1, Custom);
1454 setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::v2i1, Custom);
1455 setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::v2i1, Custom);
1456
1457 // There is no byte sized k-register load or store without AVX512DQ.
1458 if (!Subtarget.hasDQI()) {
1459 setOperationAction(ISD::LOAD, MVT::v1i1, Custom);
1460 setOperationAction(ISD::LOAD, MVT::v2i1, Custom);
1461 setOperationAction(ISD::LOAD, MVT::v4i1, Custom);
1462 setOperationAction(ISD::LOAD, MVT::v8i1, Custom);
1463
1464 setOperationAction(ISD::STORE, MVT::v1i1, Custom);
1465 setOperationAction(ISD::STORE, MVT::v2i1, Custom);
1466 setOperationAction(ISD::STORE, MVT::v4i1, Custom);
1467 setOperationAction(ISD::STORE, MVT::v8i1, Custom);
1468 }
1469
1470 // Extends of v16i1/v8i1/v4i1/v2i1 to 128-bit vectors.
1471 for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64 }) {
1472 setOperationAction(ISD::SIGN_EXTEND, VT, Custom);
1473 setOperationAction(ISD::ZERO_EXTEND, VT, Custom);
1474 setOperationAction(ISD::ANY_EXTEND, VT, Custom);
1475 }
1476
1477 for (auto VT : { MVT::v1i1, MVT::v2i1, MVT::v4i1, MVT::v8i1, MVT::v16i1 })
1478 setOperationAction(ISD::VSELECT, VT, Expand);
1479
1480 for (auto VT : { MVT::v2i1, MVT::v4i1, MVT::v8i1, MVT::v16i1 }) {
1481 setOperationAction(ISD::SETCC, VT, Custom);
1482 setOperationAction(ISD::STRICT_FSETCC, VT, Custom);
1483 setOperationAction(ISD::STRICT_FSETCCS, VT, Custom);
1484 setOperationAction(ISD::SELECT, VT, Custom);
1485 setOperationAction(ISD::TRUNCATE, VT, Custom);
1486
1487 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1488 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1489 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1490 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1491 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1492 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1493 }
1494
1495 for (auto VT : { MVT::v1i1, MVT::v2i1, MVT::v4i1, MVT::v8i1 })
1496 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1497 }
1498
1499 // This block controls legalization for 512-bit operations with 32/64 bit
1500 // elements. 512-bits can be disabled based on prefer-vector-width and
1501 // required-vector-width function attributes.
1502 if (!Subtarget.useSoftFloat() && Subtarget.useAVX512Regs()) {
1503 bool HasBWI = Subtarget.hasBWI();
1504
1505 addRegisterClass(MVT::v16i32, &X86::VR512RegClass);
1506 addRegisterClass(MVT::v16f32, &X86::VR512RegClass);
1507 addRegisterClass(MVT::v8i64, &X86::VR512RegClass);
1508 addRegisterClass(MVT::v8f64, &X86::VR512RegClass);
1509 addRegisterClass(MVT::v32i16, &X86::VR512RegClass);
1510 addRegisterClass(MVT::v64i8, &X86::VR512RegClass);
1511
1512 for (auto ExtType : {ISD::ZEXTLOAD, ISD::SEXTLOAD}) {
1513 setLoadExtAction(ExtType, MVT::v16i32, MVT::v16i8, Legal);
1514 setLoadExtAction(ExtType, MVT::v16i32, MVT::v16i16, Legal);
1515 setLoadExtAction(ExtType, MVT::v8i64, MVT::v8i8, Legal);
1516 setLoadExtAction(ExtType, MVT::v8i64, MVT::v8i16, Legal);
1517 setLoadExtAction(ExtType, MVT::v8i64, MVT::v8i32, Legal);
1518 if (HasBWI)
1519 setLoadExtAction(ExtType, MVT::v32i16, MVT::v32i8, Legal);
1520 }
1521
1522 for (MVT VT : { MVT::v16f32, MVT::v8f64 }) {
1523 setOperationAction(ISD::FNEG, VT, Custom);
1524 setOperationAction(ISD::FABS, VT, Custom);
1525 setOperationAction(ISD::FMA, VT, Legal);
1526 setOperationAction(ISD::STRICT_FMA, VT, Legal);
1527 setOperationAction(ISD::FCOPYSIGN, VT, Custom);
1528 }
1529
1530 for (MVT VT : { MVT::v16i1, MVT::v16i8, MVT::v16i16 }) {
1531 setOperationPromotedToType(ISD::FP_TO_SINT , VT, MVT::v16i32);
1532 setOperationPromotedToType(ISD::FP_TO_UINT , VT, MVT::v16i32);
1533 setOperationPromotedToType(ISD::STRICT_FP_TO_SINT, VT, MVT::v16i32);
1534 setOperationPromotedToType(ISD::STRICT_FP_TO_UINT, VT, MVT::v16i32);
1535 }
1536 setOperationAction(ISD::FP_TO_SINT, MVT::v16i32, Legal);
1537 setOperationAction(ISD::FP_TO_UINT, MVT::v16i32, Legal);
1538 setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::v16i32, Legal);
1539 setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::v16i32, Legal);
1540 setOperationAction(ISD::SINT_TO_FP, MVT::v16i32, Legal);
1541 setOperationAction(ISD::UINT_TO_FP, MVT::v16i32, Legal);
1542 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::v16i32, Legal);
1543 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::v16i32, Legal);
1544
1545 setOperationAction(ISD::STRICT_FADD, MVT::v16f32, Legal);
1546 setOperationAction(ISD::STRICT_FADD, MVT::v8f64, Legal);
1547 setOperationAction(ISD::STRICT_FSUB, MVT::v16f32, Legal);
1548 setOperationAction(ISD::STRICT_FSUB, MVT::v8f64, Legal);
1549 setOperationAction(ISD::STRICT_FMUL, MVT::v16f32, Legal);
1550 setOperationAction(ISD::STRICT_FMUL, MVT::v8f64, Legal);
1551 setOperationAction(ISD::STRICT_FDIV, MVT::v16f32, Legal);
1552 setOperationAction(ISD::STRICT_FDIV, MVT::v8f64, Legal);
1553 setOperationAction(ISD::STRICT_FSQRT, MVT::v16f32, Legal);
1554 setOperationAction(ISD::STRICT_FSQRT, MVT::v8f64, Legal);
1555 setOperationAction(ISD::STRICT_FP_EXTEND, MVT::v8f64, Legal);
1556 setOperationAction(ISD::STRICT_FP_ROUND, MVT::v8f32, Legal);
1557
1558 setTruncStoreAction(MVT::v8i64, MVT::v8i8, Legal);
1559 setTruncStoreAction(MVT::v8i64, MVT::v8i16, Legal);
1560 setTruncStoreAction(MVT::v8i64, MVT::v8i32, Legal);
1561 setTruncStoreAction(MVT::v16i32, MVT::v16i8, Legal);
1562 setTruncStoreAction(MVT::v16i32, MVT::v16i16, Legal);
1563 if (HasBWI)
1564 setTruncStoreAction(MVT::v32i16, MVT::v32i8, Legal);
1565
1566 // With 512-bit vectors and no VLX, we prefer to widen MLOAD/MSTORE
1567 // to 512-bit rather than use the AVX2 instructions so that we can use
1568 // k-masks.
1569 if (!Subtarget.hasVLX()) {
1570 for (auto VT : {MVT::v4i32, MVT::v8i32, MVT::v2i64, MVT::v4i64,
1571 MVT::v4f32, MVT::v8f32, MVT::v2f64, MVT::v4f64}) {
1572 setOperationAction(ISD::MLOAD, VT, Custom);
1573 setOperationAction(ISD::MSTORE, VT, Custom);
1574 }
1575 }
1576
1577 setOperationAction(ISD::TRUNCATE, MVT::v8i32, Legal);
1578 setOperationAction(ISD::TRUNCATE, MVT::v16i16, Legal);
1579 setOperationAction(ISD::TRUNCATE, MVT::v32i8, HasBWI ? Legal : Custom);
1580 setOperationAction(ISD::TRUNCATE, MVT::v16i64, Custom);
1581 setOperationAction(ISD::ZERO_EXTEND, MVT::v32i16, Custom);
1582 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i32, Custom);
1583 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i64, Custom);
1584 setOperationAction(ISD::ANY_EXTEND, MVT::v32i16, Custom);
1585 setOperationAction(ISD::ANY_EXTEND, MVT::v16i32, Custom);
1586 setOperationAction(ISD::ANY_EXTEND, MVT::v8i64, Custom);
1587 setOperationAction(ISD::SIGN_EXTEND, MVT::v32i16, Custom);
1588 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom);
1589 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i64, Custom);
1590
1591 if (HasBWI) {
1592 // Extends from v64i1 masks to 512-bit vectors.
1593 setOperationAction(ISD::SIGN_EXTEND, MVT::v64i8, Custom);
1594 setOperationAction(ISD::ZERO_EXTEND, MVT::v64i8, Custom);
1595 setOperationAction(ISD::ANY_EXTEND, MVT::v64i8, Custom);
1596 }
1597
1598 for (auto VT : { MVT::v16f32, MVT::v8f64 }) {
1599 setOperationAction(ISD::FFLOOR, VT, Legal);
1600 setOperationAction(ISD::STRICT_FFLOOR, VT, Legal);
1601 setOperationAction(ISD::FCEIL, VT, Legal);
1602 setOperationAction(ISD::STRICT_FCEIL, VT, Legal);
1603 setOperationAction(ISD::FTRUNC, VT, Legal);
1604 setOperationAction(ISD::STRICT_FTRUNC, VT, Legal);
1605 setOperationAction(ISD::FRINT, VT, Legal);
1606 setOperationAction(ISD::STRICT_FRINT, VT, Legal);
1607 setOperationAction(ISD::FNEARBYINT, VT, Legal);
1608 setOperationAction(ISD::STRICT_FNEARBYINT, VT, Legal);
1609 setOperationAction(ISD::FROUNDEVEN, VT, Legal);
1610 setOperationAction(ISD::STRICT_FROUNDEVEN, VT, Legal);
1611
1612 setOperationAction(ISD::FROUND, VT, Custom);
1613 }
1614
1615 for (auto VT : {MVT::v32i16, MVT::v16i32, MVT::v8i64}) {
1616 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, VT, Custom);
1617 setOperationAction(ISD::ZERO_EXTEND_VECTOR_INREG, VT, Custom);
1618 }
1619
1620 setOperationAction(ISD::ADD, MVT::v32i16, HasBWI ? Legal : Custom);
1621 setOperationAction(ISD::SUB, MVT::v32i16, HasBWI ? Legal : Custom);
1622 setOperationAction(ISD::ADD, MVT::v64i8, HasBWI ? Legal : Custom);
1623 setOperationAction(ISD::SUB, MVT::v64i8, HasBWI ? Legal : Custom);
1624
1625 setOperationAction(ISD::MUL, MVT::v8i64, Custom);
1626 setOperationAction(ISD::MUL, MVT::v16i32, Legal);
1627 setOperationAction(ISD::MUL, MVT::v32i16, HasBWI ? Legal : Custom);
1628 setOperationAction(ISD::MUL, MVT::v64i8, Custom);
1629
1630 setOperationAction(ISD::MULHU, MVT::v16i32, Custom);
1631 setOperationAction(ISD::MULHS, MVT::v16i32, Custom);
1632 setOperationAction(ISD::MULHS, MVT::v32i16, HasBWI ? Legal : Custom);
1633 setOperationAction(ISD::MULHU, MVT::v32i16, HasBWI ? Legal : Custom);
1634 setOperationAction(ISD::MULHS, MVT::v64i8, Custom);
1635 setOperationAction(ISD::MULHU, MVT::v64i8, Custom);
1636
1637 setOperationAction(ISD::SMULO, MVT::v64i8, Custom);
1638 setOperationAction(ISD::UMULO, MVT::v64i8, Custom);
1639
1640 setOperationAction(ISD::BITREVERSE, MVT::v64i8, Custom);
1641
1642 for (auto VT : { MVT::v64i8, MVT::v32i16, MVT::v16i32, MVT::v8i64 }) {
1643 setOperationAction(ISD::SRL, VT, Custom);
1644 setOperationAction(ISD::SHL, VT, Custom);
1645 setOperationAction(ISD::SRA, VT, Custom);
1646 setOperationAction(ISD::SETCC, VT, Custom);
1647
1648 // The condition codes aren't legal in SSE/AVX and under AVX512 we use
1649 // setcc all the way to isel and prefer SETGT in some isel patterns.
1650 setCondCodeAction(ISD::SETLT, VT, Custom);
1651 setCondCodeAction(ISD::SETLE, VT, Custom);
1652 }
1653 for (auto VT : { MVT::v16i32, MVT::v8i64 }) {
1654 setOperationAction(ISD::SMAX, VT, Legal);
1655 setOperationAction(ISD::UMAX, VT, Legal);
1656 setOperationAction(ISD::SMIN, VT, Legal);
1657 setOperationAction(ISD::UMIN, VT, Legal);
1658 setOperationAction(ISD::ABS, VT, Legal);
1659 setOperationAction(ISD::CTPOP, VT, Custom);
1660 setOperationAction(ISD::ROTL, VT, Custom);
1661 setOperationAction(ISD::ROTR, VT, Custom);
1662 setOperationAction(ISD::STRICT_FSETCC, VT, Custom);
1663 setOperationAction(ISD::STRICT_FSETCCS, VT, Custom);
1664 }
1665
1666 for (auto VT : { MVT::v64i8, MVT::v32i16 }) {
1667 setOperationAction(ISD::ABS, VT, HasBWI ? Legal : Custom);
1668 setOperationAction(ISD::CTPOP, VT, Subtarget.hasBITALG() ? Legal : Custom);
1669 setOperationAction(ISD::CTLZ, VT, Custom);
1670 setOperationAction(ISD::SMAX, VT, HasBWI ? Legal : Custom);
1671 setOperationAction(ISD::UMAX, VT, HasBWI ? Legal : Custom);
1672 setOperationAction(ISD::SMIN, VT, HasBWI ? Legal : Custom);
1673 setOperationAction(ISD::UMIN, VT, HasBWI ? Legal : Custom);
1674 setOperationAction(ISD::UADDSAT, VT, HasBWI ? Legal : Custom);
1675 setOperationAction(ISD::SADDSAT, VT, HasBWI ? Legal : Custom);
1676 setOperationAction(ISD::USUBSAT, VT, HasBWI ? Legal : Custom);
1677 setOperationAction(ISD::SSUBSAT, VT, HasBWI ? Legal : Custom);
1678 }
1679
1680 if (Subtarget.hasDQI()) {
1681 setOperationAction(ISD::SINT_TO_FP, MVT::v8i64, Legal);
1682 setOperationAction(ISD::UINT_TO_FP, MVT::v8i64, Legal);
1683 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::v8i64, Legal);
1684 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::v8i64, Legal);
1685 setOperationAction(ISD::FP_TO_SINT, MVT::v8i64, Legal);
1686 setOperationAction(ISD::FP_TO_UINT, MVT::v8i64, Legal);
1687 setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::v8i64, Legal);
1688 setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::v8i64, Legal);
1689
1690 setOperationAction(ISD::MUL, MVT::v8i64, Legal);
1691 }
1692
1693 if (Subtarget.hasCDI()) {
1694 // NonVLX sub-targets extend 128/256 vectors to use the 512 version.
1695 for (auto VT : { MVT::v16i32, MVT::v8i64} ) {
1696 setOperationAction(ISD::CTLZ, VT, Legal);
1697 }
1698 } // Subtarget.hasCDI()
1699
1700 if (Subtarget.hasVPOPCNTDQ()) {
1701 for (auto VT : { MVT::v16i32, MVT::v8i64 })
1702 setOperationAction(ISD::CTPOP, VT, Legal);
1703 }
1704
1705 // Extract subvector is special because the value type
1706 // (result) is 256-bit but the source is 512-bit wide.
1707 // 128-bit was made Legal under AVX1.
1708 for (auto VT : { MVT::v32i8, MVT::v16i16, MVT::v8i32, MVT::v4i64,
1709 MVT::v8f32, MVT::v4f64 })
1710 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
1711
1712 for (auto VT : { MVT::v64i8, MVT::v32i16, MVT::v16i32, MVT::v8i64,
1713 MVT::v16f32, MVT::v8f64 }) {
1714 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1715 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Legal);
1716 setOperationAction(ISD::SELECT, VT, Custom);
1717 setOperationAction(ISD::VSELECT, VT, Custom);
1718 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1719 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1720 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1721 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1722 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1723 }
1724
1725 for (auto VT : { MVT::v16i32, MVT::v8i64, MVT::v16f32, MVT::v8f64 }) {
1726 setOperationAction(ISD::MLOAD, VT, Legal);
1727 setOperationAction(ISD::MSTORE, VT, Legal);
1728 setOperationAction(ISD::MGATHER, VT, Custom);
1729 setOperationAction(ISD::MSCATTER, VT, Custom);
1730 }
1731 if (HasBWI) {
1732 for (auto VT : { MVT::v64i8, MVT::v32i16 }) {
1733 setOperationAction(ISD::MLOAD, VT, Legal);
1734 setOperationAction(ISD::MSTORE, VT, Legal);
1735 }
1736 } else {
1737 setOperationAction(ISD::STORE, MVT::v32i16, Custom);
1738 setOperationAction(ISD::STORE, MVT::v64i8, Custom);
1739 }
1740
1741 if (Subtarget.hasVBMI2()) {
1742 for (auto VT : { MVT::v8i16, MVT::v4i32, MVT::v2i64,
1743 MVT::v16i16, MVT::v8i32, MVT::v4i64,
1744 MVT::v32i16, MVT::v16i32, MVT::v8i64 }) {
1745 setOperationAction(ISD::FSHL, VT, Custom);
1746 setOperationAction(ISD::FSHR, VT, Custom);
1747 }
1748
1749 setOperationAction(ISD::ROTL, MVT::v32i16, Custom);
1750 setOperationAction(ISD::ROTR, MVT::v8i16, Custom);
1751 setOperationAction(ISD::ROTR, MVT::v16i16, Custom);
1752 setOperationAction(ISD::ROTR, MVT::v32i16, Custom);
1753 }
1754 }// useAVX512Regs
1755
1756 // This block controls legalization for operations that don't have
1757 // pre-AVX512 equivalents. Without VLX we use 512-bit operations for
1758 // narrower widths.
1759 if (!Subtarget.useSoftFloat() && Subtarget.hasAVX512()) {
1760 // These operations are handled on non-VLX by artificially widening in
1761 // isel patterns.
1762
1763 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32,
1764 Subtarget.hasVLX() ? Legal : Custom);
1765 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32,
1766 Subtarget.hasVLX() ? Legal : Custom);
1767 setOperationAction(ISD::FP_TO_UINT, MVT::v2i32, Custom);
1768 setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::v8i32,
1769 Subtarget.hasVLX() ? Legal : Custom);
1770 setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::v4i32,
1771 Subtarget.hasVLX() ? Legal : Custom);
1772 setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::v2i32, Custom);
1773 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32,
1774 Subtarget.hasVLX() ? Legal : Custom);
1775 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32,
1776 Subtarget.hasVLX() ? Legal : Custom);
1777 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::v8i32,
1778 Subtarget.hasVLX() ? Legal : Custom);
1779 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::v4i32,
1780 Subtarget.hasVLX() ? Legal : Custom);
1781
1782 if (Subtarget.hasDQI()) {
1783 // Fast v2f32 SINT_TO_FP( v2i64 ) custom conversion.
1784 // v2f32 UINT_TO_FP is already custom under SSE2.
1785 assert(isOperationCustom(ISD::UINT_TO_FP, MVT::v2f32) &&((isOperationCustom(ISD::UINT_TO_FP, MVT::v2f32) && isOperationCustom
(ISD::STRICT_UINT_TO_FP, MVT::v2f32) && "Unexpected operation action!"
) ? static_cast<void> (0) : __assert_fail ("isOperationCustom(ISD::UINT_TO_FP, MVT::v2f32) && isOperationCustom(ISD::STRICT_UINT_TO_FP, MVT::v2f32) && \"Unexpected operation action!\""
, "/build/llvm-toolchain-snapshot-13~++20210405022414+5f57793c4fe4/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 1787, __PRETTY_FUNCTION__))
1786 isOperationCustom(ISD::STRICT_UINT_TO_FP, MVT::v2f32) &&((isOperationCustom(ISD::UINT_TO_FP, MVT::v2f32) && isOperationCustom
(ISD::STRICT_UINT_TO_FP, MVT::v2f32) && "Unexpected operation action!"
) ? static_cast<void> (0) : __assert_fail ("isOperationCustom(ISD::UINT_TO_FP, MVT::v2f32) && isOperationCustom(ISD::STRICT_UINT_TO_FP, MVT::v2f32) && \"Unexpected operation action!\""
, "/build/llvm-toolchain-snapshot-13~++20210405022414+5f57793c4fe4/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 1787, __PRETTY_FUNCTION__))
1787 "Unexpected operation action!")((isOperationCustom(ISD::UINT_TO_FP, MVT::v2f32) && isOperationCustom
(ISD::STRICT_UINT_TO_FP, MVT::v2f32) && "Unexpected operation action!"
) ? static_cast<void> (0) : __assert_fail ("isOperationCustom(ISD::UINT_TO_FP, MVT::v2f32) && isOperationCustom(ISD::STRICT_UINT_TO_FP, MVT::v2f32) && \"Unexpected operation action!\""
, "/build/llvm-toolchain-snapshot-13~++20210405022414+5f57793c4fe4/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 1787, __PRETTY_FUNCTION__))
;
1788 // v2i64 FP_TO_S/UINT(v2f32) custom conversion.
1789 setOperationAction(ISD::FP_TO_SINT, MVT::v2f32, Custom);
1790 setOperationAction(ISD::FP_TO_UINT, MVT::v2f32, Custom);
1791 setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::v2f32, Custom);
1792 setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::v2f32, Custom);
1793 }
1794
1795 for (auto VT : { MVT::v2i64, MVT::v4i64 }) {
1796 setOperationAction(ISD::SMAX, VT, Legal);
1797 setOperationAction(ISD::UMAX, VT, Legal);
1798 setOperationAction(ISD::SMIN, VT, Legal);
1799 setOperationAction(ISD::UMIN, VT, Legal);
1800 setOperationAction(ISD::ABS, VT, Legal);
1801 }
1802
1803 for (auto VT : { MVT::v4i32, MVT::v8i32, MVT::v2i64, MVT::v4i64 }) {
1804 setOperationAction(ISD::ROTL, VT, Custom);
1805 setOperationAction(ISD::ROTR, VT, Custom);
1806 }
1807
1808 // Custom legalize 2x32 to get a little better code.
1809 setOperationAction(ISD::MSCATTER, MVT::v2f32, Custom);
1810 setOperationAction(ISD::MSCATTER, MVT::v2i32, Custom);
1811
1812 for (auto VT : { MVT::v4i32, MVT::v8i32, MVT::v2i64, MVT::v4i64,
1813 MVT::v4f32, MVT::v8f32, MVT::v2f64, MVT::v4f64 })
1814 setOperationAction(ISD::MSCATTER, VT, Custom);
1815
1816 if (Subtarget.hasDQI()) {
1817 for (auto VT : { MVT::v2i64, MVT::v4i64 }) {
1818 setOperationAction(ISD::SINT_TO_FP, VT,
1819 Subtarget.hasVLX() ? Legal : Custom);
1820 setOperationAction(ISD::UINT_TO_FP, VT,
1821 Subtarget.hasVLX() ? Legal : Custom);
1822 setOperationAction(ISD::STRICT_SINT_TO_FP, VT,
1823 Subtarget.hasVLX() ? Legal : Custom);
1824 setOperationAction(ISD::STRICT_UINT_TO_FP, VT,
1825 Subtarget.hasVLX() ? Legal : Custom);
1826 setOperationAction(ISD::FP_TO_SINT, VT,
1827 Subtarget.hasVLX() ? Legal : Custom);
1828 setOperationAction(ISD::FP_TO_UINT, VT,
1829 Subtarget.hasVLX() ? Legal : Custom);
1830 setOperationAction(ISD::STRICT_FP_TO_SINT, VT,
1831 Subtarget.hasVLX() ? Legal : Custom);
1832 setOperationAction(ISD::STRICT_FP_TO_UINT, VT,
1833 Subtarget.hasVLX() ? Legal : Custom);
1834 setOperationAction(ISD::MUL, VT, Legal);
1835 }
1836 }
1837
1838 if (Subtarget.hasCDI()) {
1839 for (auto VT : { MVT::v4i32, MVT::v8i32, MVT::v2i64, MVT::v4i64 }) {
1840 setOperationAction(ISD::CTLZ, VT, Legal);
1841 }
1842 } // Subtarget.hasCDI()
1843
1844 if (Subtarget.hasVPOPCNTDQ()) {
1845 for (auto VT : { MVT::v4i32, MVT::v8i32, MVT::v2i64, MVT::v4i64 })
1846 setOperationAction(ISD::CTPOP, VT, Legal);
1847 }
1848 }
1849
1850 // This block control legalization of v32i1/v64i1 which are available with
1851 // AVX512BW. 512-bit v32i16 and v64i8 vector legalization is controlled with
1852 // useBWIRegs.
1853 if (!Subtarget.useSoftFloat() && Subtarget.hasBWI()) {
1854 addRegisterClass(MVT::v32i1, &X86::VK32RegClass);
1855 addRegisterClass(MVT::v64i1, &X86::VK64RegClass);
1856
1857 for (auto VT : { MVT::v32i1, MVT::v64i1 }) {
1858 setOperationAction(ISD::VSELECT, VT, Expand);
1859 setOperationAction(ISD::TRUNCATE, VT, Custom);
1860 setOperationAction(ISD::SETCC, VT, Custom);
1861 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1862 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1863 setOperationAction(ISD::SELECT, VT, Custom);
1864 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1865 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1866 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1867 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1868 }
1869
1870 for (auto VT : { MVT::v16i1, MVT::v32i1 })
1871 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1872
1873 // Extends from v32i1 masks to 256-bit vectors.
1874 setOperationAction(ISD::SIGN_EXTEND, MVT::v32i8, Custom);
1875 setOperationAction(ISD::ZERO_EXTEND, MVT::v32i8, Custom);
1876 setOperationAction(ISD::ANY_EXTEND, MVT::v32i8, Custom);
1877
1878 for (auto VT : { MVT::v32i8, MVT::v16i8, MVT::v16i16, MVT::v8i16 }) {
1879 setOperationAction(ISD::MLOAD, VT, Subtarget.hasVLX() ? Legal : Custom);
1880 setOperationAction(ISD::MSTORE, VT, Subtarget.hasVLX() ? Legal : Custom);
1881 }
1882
1883 // These operations are handled on non-VLX by artificially widening in
1884 // isel patterns.
1885 // TODO: Custom widen in lowering on non-VLX and drop the isel patterns?
1886
1887 if (Subtarget.hasBITALG()) {
1888 for (auto VT : { MVT::v16i8, MVT::v32i8, MVT::v8i16, MVT::v16i16 })
1889 setOperationAction(ISD::CTPOP, VT, Legal);
1890 }
1891 }
1892
1893 if (!Subtarget.useSoftFloat() && Subtarget.hasVLX()) {
1894 setTruncStoreAction(MVT::v4i64, MVT::v4i8, Legal);
1895 setTruncStoreAction(MVT::v4i64, MVT::v4i16, Legal);
1896 setTruncStoreAction(MVT::v4i64, MVT::v4i32, Legal);
1897 setTruncStoreAction(MVT::v8i32, MVT::v8i8, Legal);
1898 setTruncStoreAction(MVT::v8i32, MVT::v8i16, Legal);
1899
1900 setTruncStoreAction(MVT::v2i64, MVT::v2i8, Legal);
1901 setTruncStoreAction(MVT::v2i64, MVT::v2i16, Legal);
1902 setTruncStoreAction(MVT::v2i64, MVT::v2i32, Legal);
1903 setTruncStoreAction(MVT::v4i32, MVT::v4i8, Legal);
1904 setTruncStoreAction(MVT::v4i32, MVT::v4i16, Legal);
1905
1906 if (Subtarget.hasBWI()) {
1907 setTruncStoreAction(MVT::v16i16, MVT::v16i8, Legal);
1908 setTruncStoreAction(MVT::v8i16, MVT::v8i8, Legal);
1909 }
1910
1911 setOperationAction(ISD::TRUNCATE, MVT::v16i32, Custom);
1912 setOperationAction(ISD::TRUNCATE, MVT::v8i64, Custom);
1913 setOperationAction(ISD::TRUNCATE, MVT::v16i64, Custom);
1914 }
1915
1916 if (Subtarget.hasAMXTILE()) {
1917 addRegisterClass(MVT::x86amx, &X86::TILERegClass);
1918 }
1919
1920 // We want to custom lower some of our intrinsics.
1921 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1922 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
1923 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
1924 if (!Subtarget.is64Bit()) {
1925 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom);
1926 }
1927
1928 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1929 // handle type legalization for these operations here.
1930 //
1931 // FIXME: We really should do custom legalization for addition and
1932 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1933 // than generic legalization for 64-bit multiplication-with-overflow, though.
1934 for (auto VT : { MVT::i8, MVT::i16, MVT::i32, MVT::i64 }) {
1935 if (VT == MVT::i64 && !Subtarget.is64Bit())
1936 continue;
1937 // Add/Sub/Mul with overflow operations are custom lowered.
1938 setOperationAction(ISD::SADDO, VT, Custom);
1939 setOperationAction(ISD::UADDO, VT, Custom);
1940 setOperationAction(ISD::SSUBO, VT, Custom);
1941 setOperationAction(ISD::USUBO, VT, Custom);
1942 setOperationAction(ISD::SMULO, VT, Custom);
1943 setOperationAction(ISD::UMULO, VT, Custom);
1944
1945 // Support carry in as value rather than glue.
1946 setOperationAction(ISD::ADDCARRY, VT, Custom);
1947 setOperationAction(ISD::SUBCARRY, VT, Custom);
1948 setOperationAction(ISD::SETCCCARRY, VT, Custom);
1949 setOperationAction(ISD::SADDO_CARRY, VT, Custom);
1950 setOperationAction(ISD::SSUBO_CARRY, VT, Custom);
1951 }
1952
1953 if (!Subtarget.is64Bit()) {
1954 // These libcalls are not available in 32-bit.
1955 setLibcallName(RTLIB::SHL_I128, nullptr);
1956 setLibcallName(RTLIB::SRL_I128, nullptr);
1957 setLibcallName(RTLIB::SRA_I128, nullptr);
1958 setLibcallName(RTLIB::MUL_I128, nullptr);
1959 }
1960
1961 // Combine sin / cos into _sincos_stret if it is available.
1962 if (getLibcallName(RTLIB::SINCOS_STRET_F32) != nullptr &&
1963 getLibcallName(RTLIB::SINCOS_STRET_F64) != nullptr) {
1964 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
1965 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
1966 }
1967
1968 if (Subtarget.isTargetWin64()) {
1969 setOperationAction(ISD::SDIV, MVT::i128, Custom);
1970 setOperationAction(ISD::UDIV, MVT::i128, Custom);
1971 setOperationAction(ISD::SREM, MVT::i128, Custom);
1972 setOperationAction(ISD::UREM, MVT::i128, Custom);
1973 }
1974
1975 // On 32 bit MSVC, `fmodf(f32)` is not defined - only `fmod(f64)`
1976 // is. We should promote the value to 64-bits to solve this.
1977 // This is what the CRT headers do - `fmodf` is an inline header
1978 // function casting to f64 and calling `fmod`.
1979 if (Subtarget.is32Bit() &&
1980 (Subtarget.isTargetWindowsMSVC() || Subtarget.isTargetWindowsItanium()))
1981 for (ISD::NodeType Op :
1982 {ISD::FCEIL, ISD::STRICT_FCEIL,
1983 ISD::FCOS, ISD::STRICT_FCOS,
1984 ISD::FEXP, ISD::STRICT_FEXP,
1985 ISD::FFLOOR, ISD::STRICT_FFLOOR,
1986 ISD::FREM, ISD::STRICT_FREM,
1987 ISD::FLOG, ISD::STRICT_FLOG,
1988 ISD::FLOG10, ISD::STRICT_FLOG10,
1989 ISD::FPOW, ISD::STRICT_FPOW,
1990 ISD::FSIN, ISD::STRICT_FSIN})
1991 if (isOperationExpand(Op, MVT::f32))
1992 setOperationAction(Op, MVT::f32, Promote);
1993
1994 // We have target-specific dag combine patterns for the following nodes:
1995 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1996 setTargetDAGCombine(ISD::SCALAR_TO_VECTOR);
1997 setTargetDAGCombine(ISD::INSERT_VECTOR_ELT);
1998 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1999 setTargetDAGCombine(ISD::CONCAT_VECTORS);
2000 setTargetDAGCombine(ISD::INSERT_SUBVECTOR);
2001 setTargetDAGCombine(ISD::EXTRACT_SUBVECTOR);
2002 setTargetDAGCombine(ISD::BITCAST);
2003 setTargetDAGCombine(ISD::VSELECT);
2004 setTargetDAGCombine(ISD::SELECT);
2005 setTargetDAGCombine(ISD::SHL);
2006 setTargetDAGCombine(ISD::SRA);
2007 setTargetDAGCombine(ISD::SRL);
2008 setTargetDAGCombine(ISD::OR);
2009 setTargetDAGCombine(ISD::AND);
2010 setTargetDAGCombine(ISD::ADD);
2011 setTargetDAGCombine(ISD::FADD);
2012 setTargetDAGCombine(ISD::FSUB);
2013 setTargetDAGCombine(ISD::FNEG);
2014 setTargetDAGCombine(ISD::FMA);
2015 setTargetDAGCombine(ISD::STRICT_FMA);
2016 setTargetDAGCombine(ISD::FMINNUM);
2017 setTargetDAGCombine(ISD::FMAXNUM);
2018 setTargetDAGCombine(ISD::SUB);
2019 setTargetDAGCombine(ISD::LOAD);
2020 setTargetDAGCombine(ISD::MLOAD);
2021 setTargetDAGCombine(ISD::STORE);
2022 setTargetDAGCombine(ISD::MSTORE);
2023 setTargetDAGCombine(ISD::TRUNCATE);
2024 setTargetDAGCombine(ISD::ZERO_EXTEND);
2025 setTargetDAGCombine(ISD::ANY_EXTEND);
2026 setTargetDAGCombine(ISD::SIGN_EXTEND);
2027 setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
2028 setTargetDAGCombine(ISD::ANY_EXTEND_VECTOR_INREG);
2029 setTargetDAGCombine(ISD::SIGN_EXTEND_VECTOR_INREG);
2030 setTargetDAGCombine(ISD::ZERO_EXTEND_VECTOR_INREG);
2031 setTargetDAGCombine(ISD::SINT_TO_FP);
2032 setTargetDAGCombine(ISD::UINT_TO_FP);
2033 setTargetDAGCombine(ISD::STRICT_SINT_TO_FP);
2034 setTargetDAGCombine(ISD::STRICT_UINT_TO_FP);
2035 setTargetDAGCombine(ISD::SETCC);
2036 setTargetDAGCombine(ISD::MUL);
2037 setTargetDAGCombine(ISD::XOR);
2038 setTargetDAGCombine(ISD::MSCATTER);
2039 setTargetDAGCombine(ISD::MGATHER);
2040 setTargetDAGCombine(ISD::FP16_TO_FP);
2041 setTargetDAGCombine(ISD::FP_EXTEND);
2042 setTargetDAGCombine(ISD::STRICT_FP_EXTEND);
2043 setTargetDAGCombine(ISD::FP_ROUND);
2044
2045 computeRegisterProperties(Subtarget.getRegisterInfo());
2046
2047 MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
2048 MaxStoresPerMemsetOptSize = 8;
2049 MaxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
2050 MaxStoresPerMemcpyOptSize = 4;
2051 MaxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
2052 MaxStoresPerMemmoveOptSize = 4;
2053
2054 // TODO: These control memcmp expansion in CGP and could be raised higher, but
2055 // that needs to benchmarked and balanced with the potential use of vector
2056 // load/store types (PR33329, PR33914).
2057 MaxLoadsPerMemcmp = 2;
2058 MaxLoadsPerMemcmpOptSize = 2;
2059
2060 // Set loop alignment to 2^ExperimentalPrefLoopAlignment bytes (default: 2^4).
2061 setPrefLoopAlignment(Align(1ULL << ExperimentalPrefLoopAlignment));
2062
2063 // An out-of-order CPU can speculatively execute past a predictable branch,
2064 // but a conditional move could be stalled by an expensive earlier operation.
2065 PredictableSelectIsExpensive = Subtarget.getSchedModel().isOutOfOrder();
2066 EnableExtLdPromotion = true;
2067 setPrefFunctionAlignment(Align(16));
2068
2069 verifyIntrinsicTables();
2070
2071 // Default to having -disable-strictnode-mutation on
2072 IsStrictFPEnabled = true;
2073}
2074
2075// This has so far only been implemented for 64-bit MachO.
2076bool X86TargetLowering::useLoadStackGuardNode() const {
2077 return Subtarget.isTargetMachO() && Subtarget.is64Bit();
2078}
2079
2080bool X86TargetLowering::useStackGuardXorFP() const {
2081 // Currently only MSVC CRTs XOR the frame pointer into the stack guard value.
2082 return Subtarget.getTargetTriple().isOSMSVCRT() && !Subtarget.isTargetMachO();
2083}
2084
2085SDValue X86TargetLowering::emitStackGuardXorFP(SelectionDAG &DAG, SDValue Val,
2086 const SDLoc &DL) const {
2087 EVT PtrTy = getPointerTy(DAG.getDataLayout());
2088 unsigned XorOp = Subtarget.is64Bit() ? X86::XOR64_FP : X86::XOR32_FP;
2089 MachineSDNode *Node = DAG.getMachineNode(XorOp, DL, PtrTy, Val);
2090 return SDValue(Node, 0);
2091}
2092
2093TargetLoweringBase::LegalizeTypeAction
2094X86TargetLowering::getPreferredVectorAction(MVT VT) const {
2095 if ((VT == MVT::v32i1 || VT == MVT::v64i1) && Subtarget.hasAVX512() &&
2096 !Subtarget.hasBWI())
2097 return TypeSplitVector;
2098
2099 if (VT.getVectorNumElements() != 1 &&
2100 VT.getVectorElementType() != MVT::i1)
2101 return TypeWidenVector;
2102
2103 return TargetLoweringBase::getPreferredVectorAction(VT);
2104}
2105
2106static std::pair<MVT, unsigned>
2107handleMaskRegisterForCallingConv(unsigned NumElts, CallingConv::ID CC,
2108 const X86Subtarget &Subtarget) {
2109 // v2i1/v4i1/v8i1/v16i1 all pass in xmm registers unless the calling
2110 // convention is one that uses k registers.
2111 if (NumElts == 2)
2112 return {MVT::v2i64, 1};
2113 if (NumElts == 4)
2114 return {MVT::v4i32, 1};
2115 if (NumElts == 8 && CC != CallingConv::X86_RegCall &&
2116 CC != CallingConv::Intel_OCL_BI)
2117 return {MVT::v8i16, 1};
2118 if (NumElts == 16 && CC != CallingConv::X86_RegCall &&
2119 CC != CallingConv::Intel_OCL_BI)
2120 return {MVT::v16i8, 1};
2121 // v32i1 passes in ymm unless we have BWI and the calling convention is
2122 // regcall.
2123 if (NumElts == 32 && (!Subtarget.hasBWI() || CC != CallingConv::X86_RegCall))
2124 return {MVT::v32i8, 1};
2125 // Split v64i1 vectors if we don't have v64i8 available.
2126 if (NumElts == 64 && Subtarget.hasBWI() && CC != CallingConv::X86_RegCall) {
2127 if (Subtarget.useAVX512Regs())
2128 return {MVT::v64i8, 1};
2129 return {MVT::v32i8, 2};
2130 }
2131
2132 // Break wide or odd vXi1 vectors into scalars to match avx2 behavior.
2133 if (!isPowerOf2_32(NumElts) || (NumElts == 64 && !Subtarget.hasBWI()) ||
2134 NumElts > 64)
2135 return {MVT::i8, NumElts};
2136
2137 return {MVT::INVALID_SIMPLE_VALUE_TYPE, 0};
2138}
2139
2140MVT X86TargetLowering::getRegisterTypeForCallingConv(LLVMContext &Context,
2141 CallingConv::ID CC,
2142 EVT VT) const {
2143 if (VT.isVector() && VT.getVectorElementType() == MVT::i1 &&
2144 Subtarget.hasAVX512()) {
2145 unsigned NumElts = VT.getVectorNumElements();
2146
2147 MVT RegisterVT;
2148 unsigned NumRegisters;
2149 std::tie(RegisterVT, NumRegisters) =
2150 handleMaskRegisterForCallingConv(NumElts, CC, Subtarget);
2151 if (RegisterVT != MVT::INVALID_SIMPLE_VALUE_TYPE)
2152 return RegisterVT;
2153 }
2154
2155 return TargetLowering::getRegisterTypeForCallingConv(Context, CC, VT);
2156}
2157
2158unsigned X86TargetLowering::getNumRegistersForCallingConv(LLVMContext &Context,
2159 CallingConv::ID CC,
2160 EVT VT) const {
2161 if (VT.isVector() && VT.getVectorElementType() == MVT::i1 &&
2162 Subtarget.hasAVX512()) {
2163 unsigned NumElts = VT.getVectorNumElements();
2164
2165 MVT RegisterVT;
2166 unsigned NumRegisters;
2167 std::tie(RegisterVT, NumRegisters) =
2168 handleMaskRegisterForCallingConv(NumElts, CC, Subtarget);
2169 if (RegisterVT != MVT::INVALID_SIMPLE_VALUE_TYPE)
2170 return NumRegisters;
2171 }
2172
2173 return TargetLowering::getNumRegistersForCallingConv(Context, CC, VT);
2174}
2175
2176unsigned X86TargetLowering::getVectorTypeBreakdownForCallingConv(
2177 LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT,
2178 unsigned &NumIntermediates, MVT &RegisterVT) const {
2179 // Break wide or odd vXi1 vectors into scalars to match avx2 behavior.
2180 if (VT.isVector() && VT.getVectorElementType() == MVT::i1 &&
2181 Subtarget.hasAVX512() &&
2182 (!isPowerOf2_32(VT.getVectorNumElements()) ||
2183 (VT.getVectorNumElements() == 64 && !Subtarget.hasBWI()) ||
2184 VT.getVectorNumElements() > 64)) {
2185 RegisterVT = MVT::i8;
2186 IntermediateVT = MVT::i1;
2187 NumIntermediates = VT.getVectorNumElements();
2188 return NumIntermediates;
2189 }
2190
2191 // Split v64i1 vectors if we don't have v64i8 available.
2192 if (VT == MVT::v64i1 && Subtarget.hasBWI() && !Subtarget.useAVX512Regs() &&
2193 CC != CallingConv::X86_RegCall) {
2194 RegisterVT = MVT::v32i8;
2195 IntermediateVT = MVT::v32i1;
2196 NumIntermediates = 2;
2197 return 2;
2198 }
2199
2200 return TargetLowering::getVectorTypeBreakdownForCallingConv(Context, CC, VT, IntermediateVT,
2201 NumIntermediates, RegisterVT);
2202}
2203
2204EVT X86TargetLowering::getSetCCResultType(const DataLayout &DL,
2205 LLVMContext& Context,
2206 EVT VT) const {
2207 if (!VT.isVector())
2208 return MVT::i8;
2209
2210 if (Subtarget.hasAVX512()) {
2211 // Figure out what this type will be legalized to.
2212 EVT LegalVT = VT;
2213 while (getTypeAction(Context, LegalVT) != TypeLegal)
2214 LegalVT = getTypeToTransformTo(Context, LegalVT);
2215
2216 // If we got a 512-bit vector then we'll definitely have a vXi1 compare.
2217 if (LegalVT.getSimpleVT().is512BitVector())
2218 return EVT::getVectorVT(Context, MVT::i1, VT.getVectorElementCount());
2219
2220 if (LegalVT.getSimpleVT().isVector() && Subtarget.hasVLX()) {
2221 // If we legalized to less than a 512-bit vector, then we will use a vXi1
2222 // compare for vXi32/vXi64 for sure. If we have BWI we will also support
2223 // vXi16/vXi8.
2224 MVT EltVT = LegalVT.getSimpleVT().getVectorElementType();
2225 if (Subtarget.hasBWI() || EltVT.getSizeInBits() >= 32)
2226 return EVT::getVectorVT(Context, MVT::i1, VT.getVectorElementCount());
2227 }
2228 }
2229
2230 return VT.changeVectorElementTypeToInteger();
2231}
2232
2233/// Helper for getByValTypeAlignment to determine
2234/// the desired ByVal argument alignment.
2235static void getMaxByValAlign(Type *Ty, Align &MaxAlign) {
2236 if (MaxAlign == 16)
2237 return;
2238 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
2239 if (VTy->getPrimitiveSizeInBits().getFixedSize() == 128)
2240 MaxAlign = Align(16);
2241 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
2242 Align EltAlign;
2243 getMaxByValAlign(ATy->getElementType(), EltAlign);
2244 if (EltAlign > MaxAlign)
2245 MaxAlign = EltAlign;
2246 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
2247 for (auto *EltTy : STy->elements()) {
2248 Align EltAlign;
2249 getMaxByValAlign(EltTy, EltAlign);
2250 if (EltAlign > MaxAlign)
2251 MaxAlign = EltAlign;
2252 if (MaxAlign == 16)
2253 break;
2254 }
2255 }
2256}
2257
2258/// Return the desired alignment for ByVal aggregate
2259/// function arguments in the caller parameter area. For X86, aggregates
2260/// that contain SSE vectors are placed at 16-byte boundaries while the rest
2261/// are at 4-byte boundaries.
2262unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty,
2263 const DataLayout &DL) const {
2264 if (Subtarget.is64Bit()) {
2265 // Max of 8 and alignment of type.
2266 Align TyAlign = DL.getABITypeAlign(Ty);
2267 if (TyAlign > 8)
2268 return TyAlign.value();
2269 return 8;
2270 }
2271
2272 Align Alignment(4);
2273 if (Subtarget.hasSSE1())
2274 getMaxByValAlign(Ty, Alignment);
2275 return Alignment.value();
2276}
2277
2278/// It returns EVT::Other if the type should be determined using generic
2279/// target-independent logic.
2280/// For vector ops we check that the overall size isn't larger than our
2281/// preferred vector width.
2282EVT X86TargetLowering::getOptimalMemOpType(
2283 const MemOp &Op, const AttributeList &FuncAttributes) const {
2284 if (!FuncAttributes.hasFnAttribute(Attribute::NoImplicitFloat)) {
2285 if (Op.size() >= 16 &&
2286 (!Subtarget.isUnalignedMem16Slow() || Op.isAligned(Align(16)))) {
2287 // FIXME: Check if unaligned 64-byte accesses are slow.
2288 if (Op.size() >= 64 && Subtarget.hasAVX512() &&
2289 (Subtarget.getPreferVectorWidth() >= 512)) {
2290 return Subtarget.hasBWI() ? MVT::v64i8 : MVT::v16i32;
2291 }
2292 // FIXME: Check if unaligned 32-byte accesses are slow.
2293 if (Op.size() >= 32 && Subtarget.hasAVX() &&
2294 (Subtarget.getPreferVectorWidth() >= 256)) {
2295 // Although this isn't a well-supported type for AVX1, we'll let
2296 // legalization and shuffle lowering produce the optimal codegen. If we
2297 // choose an optimal type with a vector element larger than a byte,
2298 // getMemsetStores() may create an intermediate splat (using an integer
2299 // multiply) before we splat as a vector.
2300 return MVT::v32i8;
2301 }
2302 if (Subtarget.hasSSE2() && (Subtarget.getPreferVectorWidth() >= 128))
2303 return MVT::v16i8;
2304 // TODO: Can SSE1 handle a byte vector?
2305 // If we have SSE1 registers we should be able to use them.
2306 if (Subtarget.hasSSE1() && (Subtarget.is64Bit() || Subtarget.hasX87()) &&
2307 (Subtarget.getPreferVectorWidth() >= 128))
2308 return MVT::v4f32;
2309 } else if (((Op.isMemcpy() && !Op.isMemcpyStrSrc()) || Op.isZeroMemset()) &&
2310 Op.size() >= 8 && !Subtarget.is64Bit() && Subtarget.hasSSE2()) {
2311 // Do not use f64 to lower memcpy if source is string constant. It's
2312 // better to use i32 to avoid the loads.
2313 // Also, do not use f64 to lower memset unless this is a memset of zeros.
2314 // The gymnastics of splatting a byte value into an XMM register and then
2315 // only using 8-byte stores (because this is a CPU with slow unaligned
2316 // 16-byte accesses) makes that a loser.
2317 return MVT::f64;
2318 }
2319 }
2320 // This is a compromise. If we reach here, unaligned accesses may be slow on
2321 // this target. However, creating smaller, aligned accesses could be even
2322 // slower and would certainly be a lot more code.
2323 if (Subtarget.is64Bit() && Op.size() >= 8)
2324 return MVT::i64;
2325 return MVT::i32;
2326}
2327
2328bool X86TargetLowering::isSafeMemOpType(MVT VT) const {
2329 if (VT == MVT::f32)
2330 return X86ScalarSSEf32;
2331 if (VT == MVT::f64)
2332 return X86ScalarSSEf64;
2333 return true;
2334}
2335
2336bool X86TargetLowering::allowsMisalignedMemoryAccesses(
2337 EVT VT, unsigned, Align Alignment, MachineMemOperand::Flags Flags,
2338 bool *Fast) const {
2339 if (Fast) {
2340 switch (VT.getSizeInBits()) {
2341 default:
2342 // 8-byte and under are always assumed to be fast.
2343 *Fast = true;
2344 break;
2345 case 128:
2346 *Fast = !Subtarget.isUnalignedMem16Slow();
2347 break;
2348 case 256:
2349 *Fast = !Subtarget.isUnalignedMem32Slow();
2350 break;
2351 // TODO: What about AVX-512 (512-bit) accesses?
2352 }
2353 }
2354 // NonTemporal vector memory ops must be aligned.
2355 if (!!(Flags & MachineMemOperand::MONonTemporal) && VT.isVector()) {
2356 // NT loads can only be vector aligned, so if its less aligned than the
2357 // minimum vector size (which we can split the vector down to), we might as
2358 // well use a regular unaligned vector load.
2359 // We don't have any NT loads pre-SSE41.
2360 if (!!(Flags & MachineMemOperand::MOLoad))
2361 return (Alignment < 16 || !Subtarget.hasSSE41());
2362 return false;
2363 }
2364 // Misaligned accesses of any size are always allowed.
2365 return true;
2366}
2367
2368/// Return the entry encoding for a jump table in the
2369/// current function. The returned value is a member of the
2370/// MachineJumpTableInfo::JTEntryKind enum.
2371unsigned X86TargetLowering::getJumpTableEncoding() const {
2372 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
2373 // symbol.
2374 if (isPositionIndependent() && Subtarget.isPICStyleGOT())
2375 return MachineJumpTableInfo::EK_Custom32;
2376
2377 // Otherwise, use the normal jump table encoding heuristics.
2378 return TargetLowering::getJumpTableEncoding();
2379}
2380
2381bool X86TargetLowering::useSoftFloat() const {
2382 return Subtarget.useSoftFloat();
2383}
2384
2385void X86TargetLowering::markLibCallAttributes(MachineFunction *MF, unsigned CC,
2386 ArgListTy &Args) const {
2387
2388 // Only relabel X86-32 for C / Stdcall CCs.
2389 if (Subtarget.is64Bit())
2390 return;
2391 if (CC != CallingConv::C && CC != CallingConv::X86_StdCall)
2392 return;
2393 unsigned ParamRegs = 0;
2394 if (auto *M = MF->getFunction().getParent())
2395 ParamRegs = M->getNumberRegisterParameters();
2396
2397 // Mark the first N int arguments as having reg
2398 for (auto &Arg : Args) {
2399 Type *T = Arg.Ty;
2400 if (T->isIntOrPtrTy())
2401 if (MF->getDataLayout().getTypeAllocSize(T) <= 8) {
2402 unsigned numRegs = 1;
2403 if (MF->getDataLayout().getTypeAllocSize(T) > 4)
2404 numRegs = 2;
2405 if (ParamRegs < numRegs)
2406 return;
2407 ParamRegs -= numRegs;
2408 Arg.IsInReg = true;
2409 }
2410 }
2411}
2412
2413const MCExpr *
2414X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
2415 const MachineBasicBlock *MBB,
2416 unsigned uid,MCContext &Ctx) const{
2417 assert(isPositionIndependent() && Subtarget.isPICStyleGOT())((isPositionIndependent() && Subtarget.isPICStyleGOT(
)) ? static_cast<void> (0) : __assert_fail ("isPositionIndependent() && Subtarget.isPICStyleGOT()"
, "/build/llvm-toolchain-snapshot-13~++20210405022414+5f57793c4fe4/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 2417, __PRETTY_FUNCTION__))
;
2418 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
2419 // entries.
2420 return MCSymbolRefExpr::create(MBB->getSymbol(),
2421 MCSymbolRefExpr::VK_GOTOFF, Ctx);
2422}
2423
2424/// Returns relocation base for the given PIC jumptable.
2425SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
2426 SelectionDAG &DAG) const {
2427 if (!Subtarget.is64Bit())
2428 // This doesn't have SDLoc associated with it, but is not really the
2429 // same as a Register.
2430 return DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(),
2431 getPointerTy(DAG.getDataLayout()));
2432 return Table;
2433}
2434
2435/// This returns the relocation base for the given PIC jumptable,
2436/// the same as getPICJumpTableRelocBase, but as an MCExpr.
2437const MCExpr *X86TargetLowering::
2438getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
2439 MCContext &Ctx) const {
2440 // X86-64 uses RIP relative addressing based on the jump table label.
2441 if (Subtarget.isPICStyleRIPRel())
2442 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
2443
2444 // Otherwise, the reference is relative to the PIC base.
2445 return MCSymbolRefExpr::create(MF->getPICBaseSymbol(), Ctx);
2446}
2447
2448std::pair<const TargetRegisterClass *, uint8_t>
2449X86TargetLowering::findRepresentativeClass(const TargetRegisterInfo *TRI,
2450 MVT VT) const {
2451 const TargetRegisterClass *RRC = nullptr;
2452 uint8_t Cost = 1;
2453 switch (VT.SimpleTy) {
2454 default:
2455 return TargetLowering::findRepresentativeClass(TRI, VT);
2456 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
2457 RRC = Subtarget.is64Bit() ? &X86::GR64RegClass : &X86::GR32RegClass;
2458 break;
2459 case MVT::x86mmx:
2460 RRC = &X86::VR64RegClass;
2461 break;
2462 case MVT::f32: case MVT::f64:
2463 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
2464 case MVT::v4f32: case MVT::v2f64:
2465 case MVT::v32i8: case MVT::v16i16: case MVT::v8i32: case MVT::v4i64:
2466 case MVT::v8f32: case MVT::v4f64:
2467 case MVT::v64i8: case MVT::v32i16: case MVT::v16i32: case MVT::v8i64:
2468 case MVT::v16f32: case MVT::v8f64:
2469 RRC = &X86::VR128XRegClass;
2470 break;
2471 }
2472 return std::make_pair(RRC, Cost);
2473}
2474
2475unsigned X86TargetLowering::getAddressSpace() const {
2476 if (Subtarget.is64Bit())
2477 return (getTargetMachine().getCodeModel() == CodeModel::Kernel) ? 256 : 257;
2478 return 256;
2479}
2480
2481static bool hasStackGuardSlotTLS(const Triple &TargetTriple) {
2482 return TargetTriple.isOSGlibc() || TargetTriple.isOSFuchsia() ||
2483 (TargetTriple.isAndroid() && !TargetTriple.isAndroidVersionLT(17));
2484}
2485
2486static Constant* SegmentOffset(IRBuilder<> &IRB,
2487 unsigned Offset, unsigned AddressSpace) {
2488 return ConstantExpr::getIntToPtr(
2489 ConstantInt::get(Type::getInt32Ty(IRB.getContext()), Offset),
2490 Type::getInt8PtrTy(IRB.getContext())->getPointerTo(AddressSpace));
2491}
2492
2493Value *X86TargetLowering::getIRStackGuard(IRBuilder<> &IRB) const {
2494 // glibc, bionic, and Fuchsia have a special slot for the stack guard in
2495 // tcbhead_t; use it instead of the usual global variable (see
2496 // sysdeps/{i386,x86_64}/nptl/tls.h)
2497 if (hasStackGuardSlotTLS(Subtarget.getTargetTriple())) {
2498 if (Subtarget.isTargetFuchsia()) {
2499 // <zircon/tls.h> defines ZX_TLS_STACK_GUARD_OFFSET with this value.
2500 return SegmentOffset(IRB, 0x10, getAddressSpace());
2501 } else {
2502 unsigned AddressSpace = getAddressSpace();
2503 // Specially, some users may customize the base reg and offset.
2504 unsigned Offset = getTargetMachine().Options.StackProtectorGuardOffset;
2505 // If we don't set -stack-protector-guard-offset value:
2506 // %fs:0x28, unless we're using a Kernel code model, in which case
2507 // it's %gs:0x28. gs:0x14 on i386.
2508 if (Offset == (unsigned)-1)
2509 Offset = (Subtarget.is64Bit()) ? 0x28 : 0x14;
2510
2511 const auto &GuardReg = getTargetMachine().Options.StackProtectorGuardReg;
2512 if (GuardReg == "fs")
2513 AddressSpace = X86AS::FS;
2514 else if (GuardReg == "gs")
2515 AddressSpace = X86AS::GS;
2516 return SegmentOffset(IRB, Offset, AddressSpace);
2517 }
2518 }
2519 return TargetLowering::getIRStackGuard(IRB);
2520}
2521
2522void X86TargetLowering::insertSSPDeclarations(Module &M) const {
2523 // MSVC CRT provides functionalities for stack protection.
2524 if (Subtarget.getTargetTriple().isWindowsMSVCEnvironment() ||
2525 Subtarget.getTargetTriple().isWindowsItaniumEnvironment()) {
2526 // MSVC CRT has a global variable holding security cookie.
2527 M.getOrInsertGlobal("__security_cookie",
2528 Type::getInt8PtrTy(M.getContext()));
2529
2530 // MSVC CRT has a function to validate security cookie.
2531 FunctionCallee SecurityCheckCookie = M.getOrInsertFunction(
2532 "__security_check_cookie", Type::getVoidTy(M.getContext()),
2533 Type::getInt8PtrTy(M.getContext()));
2534 if (Function *F = dyn_cast<Function>(SecurityCheckCookie.getCallee())) {
2535 F->setCallingConv(CallingConv::X86_FastCall);
2536 F->addAttribute(1, Attribute::AttrKind::InReg);
2537 }
2538 return;
2539 }
2540
2541 auto GuardMode = getTargetMachine().Options.StackProtectorGuard;
2542
2543 // glibc, bionic, and Fuchsia have a special slot for the stack guard.
2544 if ((GuardMode == llvm::StackProtectorGuards::TLS ||
2545 GuardMode == llvm::StackProtectorGuards::None)
2546 && hasStackGuardSlotTLS(Subtarget.getTargetTriple()))
2547 return;
2548 TargetLowering::insertSSPDeclarations(M);
2549}
2550
2551Value *X86TargetLowering::getSDagStackGuard(const Module &M) const {
2552 // MSVC CRT has a global variable holding security cookie.
2553 if (Subtarget.getTargetTriple().isWindowsMSVCEnvironment() ||
2554 Subtarget.getTargetTriple().isWindowsItaniumEnvironment()) {
2555 return M.getGlobalVariable("__security_cookie");
2556 }
2557 return TargetLowering::getSDagStackGuard(M);
2558}
2559
2560Function *X86TargetLowering::getSSPStackGuardCheck(const Module &M) const {
2561 // MSVC CRT has a function to validate security cookie.
2562 if (Subtarget.getTargetTriple().isWindowsMSVCEnvironment() ||
2563 Subtarget.getTargetTriple().isWindowsItaniumEnvironment()) {
2564 return M.getFunction("__security_check_cookie");
2565 }
2566 return TargetLowering::getSSPStackGuardCheck(M);
2567}
2568
2569Value *X86TargetLowering::getSafeStackPointerLocation(IRBuilder<> &IRB) const {
2570 if (Subtarget.getTargetTriple().isOSContiki())
2571 return getDefaultSafeStackPointerLocation(IRB, false);
2572
2573 // Android provides a fixed TLS slot for the SafeStack pointer. See the
2574 // definition of TLS_SLOT_SAFESTACK in
2575 // https://android.googlesource.com/platform/bionic/+/master/libc/private/bionic_tls.h
2576 if (Subtarget.isTargetAndroid()) {
2577 // %fs:0x48, unless we're using a Kernel code model, in which case it's %gs:
2578 // %gs:0x24 on i386
2579 unsigned Offset = (Subtarget.is64Bit()) ? 0x48 : 0x24;
2580 return SegmentOffset(IRB, Offset, getAddressSpace());
2581 }
2582
2583 // Fuchsia is similar.
2584 if (Subtarget.isTargetFuchsia()) {
2585 // <zircon/tls.h> defines ZX_TLS_UNSAFE_SP_OFFSET with this value.
2586 return SegmentOffset(IRB, 0x18, getAddressSpace());
2587 }
2588
2589 return TargetLowering::getSafeStackPointerLocation(IRB);
2590}
2591
2592//===----------------------------------------------------------------------===//
2593// Return Value Calling Convention Implementation
2594//===----------------------------------------------------------------------===//
2595
2596bool X86TargetLowering::CanLowerReturn(
2597 CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg,
2598 const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const {
2599 SmallVector<CCValAssign, 16> RVLocs;
2600 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
2601 return CCInfo.CheckReturn(Outs, RetCC_X86);
2602}
2603
2604const MCPhysReg *X86TargetLowering::getScratchRegisters(CallingConv::ID) const {
2605 static const MCPhysReg ScratchRegs[] = { X86::R11, 0 };
2606 return ScratchRegs;
2607}
2608
2609/// Lowers masks values (v*i1) to the local register values
2610/// \returns DAG node after lowering to register type
2611static SDValue lowerMasksToReg(const SDValue &ValArg, const EVT &ValLoc,
2612 const SDLoc &Dl, SelectionDAG &DAG) {
2613 EVT ValVT = ValArg.getValueType();
2614
2615 if (ValVT == MVT::v1i1)
2616 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, Dl, ValLoc, ValArg,
2617 DAG.getIntPtrConstant(0, Dl));
2618
2619 if ((ValVT == MVT::v8i1 && (ValLoc == MVT::i8 || ValLoc == MVT::i32)) ||
2620 (ValVT == MVT::v16i1 && (ValLoc == MVT::i16 || ValLoc == MVT::i32))) {
2621 // Two stage lowering might be required
2622 // bitcast: v8i1 -> i8 / v16i1 -> i16
2623 // anyextend: i8 -> i32 / i16 -> i32
2624 EVT TempValLoc = ValVT == MVT::v8i1 ? MVT::i8 : MVT::i16;
2625 SDValue ValToCopy = DAG.getBitcast(TempValLoc, ValArg);
2626 if (ValLoc == MVT::i32)
2627 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, Dl, ValLoc, ValToCopy);
2628 return ValToCopy;
2629 }
2630
2631 if ((ValVT == MVT::v32i1 && ValLoc == MVT::i32) ||
2632 (ValVT == MVT::v64i1 && ValLoc == MVT::i64)) {
2633 // One stage lowering is required
2634 // bitcast: v32i1 -> i32 / v64i1 -> i64
2635 return DAG.getBitcast(ValLoc, ValArg);
2636 }
2637
2638 return DAG.getNode(ISD::ANY_EXTEND, Dl, ValLoc, ValArg);
2639}
2640
2641/// Breaks v64i1 value into two registers and adds the new node to the DAG
2642static void Passv64i1ArgInRegs(
2643 const SDLoc &Dl, SelectionDAG &DAG, SDValue &Arg,
2644 SmallVectorImpl<std::pair<Register, SDValue>> &RegsToPass, CCValAssign &VA,
2645 CCValAssign &NextVA, const X86Subtarget &Subtarget) {
2646 assert(Subtarget.hasBWI() && "Expected AVX512BW target!")((Subtarget.hasBWI() && "Expected AVX512BW target!") ?
static_cast<void> (0) : __assert_fail ("Subtarget.hasBWI() && \"Expected AVX512BW target!\""
, "/build/llvm-toolchain-snapshot-13~++20210405022414+5f57793c4fe4/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 2646, __PRETTY_FUNCTION__))
;
2647 assert(Subtarget.is32Bit() && "Expecting 32 bit target")((Subtarget.is32Bit() && "Expecting 32 bit target") ?
static_cast<void> (0) : __assert_fail ("Subtarget.is32Bit() && \"Expecting 32 bit target\""
, "/build/llvm-toolchain-snapshot-13~++20210405022414+5f57793c4fe4/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 2647, __PRETTY_FUNCTION__))
;
2648 assert(Arg.getValueType() == MVT::i64 && "Expecting 64 bit value")((Arg.getValueType() == MVT::i64 && "Expecting 64 bit value"
) ? static_cast<void> (0) : __assert_fail ("Arg.getValueType() == MVT::i64 && \"Expecting 64 bit value\""
, "/build/llvm-toolchain-snapshot-13~++20210405022414+5f57793c4fe4/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 2648, __PRETTY_FUNCTION__))
;
2649 assert(VA.isRegLoc() && NextVA.isRegLoc() &&((VA.isRegLoc() && NextVA.isRegLoc() && "The value should reside in two registers"
) ? static_cast<void> (0) : __assert_fail ("VA.isRegLoc() && NextVA.isRegLoc() && \"The value should reside in two registers\""
, "/build/llvm-toolchain-snapshot-13~++20210405022414+5f57793c4fe4/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 2650, __PRETTY_FUNCTION__))
2650 "The value should reside in two registers")((VA.isRegLoc() && NextVA.isRegLoc() && "The value should reside in two registers"
) ? static_cast<void> (0) : __assert_fail ("VA.isRegLoc() && NextVA.isRegLoc() && \"The value should reside in two registers\""
, "/build/llvm-toolchain-snapshot-13~++20210405022414+5f57793c4fe4/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 2650, __PRETTY_FUNCTION__))
;
2651
2652 // Before splitting the value we cast it to i64
2653 Arg = DAG.getBitcast(MVT::i64, Arg);
2654
2655 // Splitting the value into two i32 types
2656 SDValue Lo, Hi;
2657 Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, Dl, MVT::i32, Arg,
2658 DAG.getConstant(0, Dl, MVT::i32));
2659 Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, Dl, MVT::i32, Arg,
2660 DAG.getConstant(1, Dl, MVT::i32));
2661
2662 // Attach the two i32 types into corresponding registers
2663 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Lo));
2664 RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), Hi));
2665}
2666
2667SDValue
2668X86TargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
2669 bool isVarArg,
2670 const SmallVectorImpl<ISD::OutputArg> &Outs,
2671 const SmallVectorImpl<SDValue> &OutVals,
2672 const SDLoc &dl, SelectionDAG &DAG) const {
2673 MachineFunction &MF = DAG.getMachineFunction();
2674 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2675
2676 // In some cases we need to disable registers from the default CSR list.
2677 // For example, when they are used for argument passing.
2678 bool ShouldDisableCalleeSavedRegister =
2679 CallConv == CallingConv::X86_RegCall ||
2680 MF.getFunction().hasFnAttribute("no_caller_saved_registers");
2681
2682 if (CallConv == CallingConv::X86_INTR && !Outs.empty())
2683 report_fatal_error("X86 interrupts may not return any value");
2684
2685 SmallVector<CCValAssign, 16> RVLocs;
2686 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, *DAG.getContext());
2687 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
2688
2689 SmallVector<std::pair<Register, SDValue>, 4> RetVals;
2690 for (unsigned I = 0, OutsIndex = 0, E = RVLocs.size(); I != E;
2691 ++I, ++OutsIndex) {
2692 CCValAssign &VA = RVLocs[I];
2693 assert(VA.isRegLoc() && "Can only return in registers!")((VA.isRegLoc() && "Can only return in registers!") ?
static_cast<void> (0) : __assert_fail ("VA.isRegLoc() && \"Can only return in registers!\""
, "/build/llvm-toolchain-snapshot-13~++20210405022414+5f57793c4fe4/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 2693, __PRETTY_FUNCTION__))
;
2694
2695 // Add the register to the CalleeSaveDisableRegs list.
2696 if (ShouldDisableCalleeSavedRegister)
2697 MF.getRegInfo().disableCalleeSavedRegister(VA.getLocReg());
2698
2699 SDValue ValToCopy = OutVals[OutsIndex];
2700 EVT ValVT = ValToCopy.getValueType();
2701
2702 // Promote values to the appropriate types.
2703 if (VA.getLocInfo() == CCValAssign::SExt)
2704 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
2705 else if (VA.getLocInfo() == CCValAssign::ZExt)
2706 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy);
2707 else if (VA.getLocInfo() == CCValAssign::AExt) {
2708 if (ValVT.isVector() && ValVT.getVectorElementType() == MVT::i1)
2709 ValToCopy = lowerMasksToReg(ValToCopy, VA.getLocVT(), dl, DAG);
2710 else
2711 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy);
2712 }
2713 else if (VA.getLocInfo() == CCValAssign::BCvt)
2714 ValToCopy = DAG.getBitcast(VA.getLocVT(), ValToCopy);
2715
2716 assert(VA.getLocInfo() != CCValAssign::FPExt &&((VA.getLocInfo() != CCValAssign::FPExt && "Unexpected FP-extend for return value."
) ? static_cast<void> (0) : __assert_fail ("VA.getLocInfo() != CCValAssign::FPExt && \"Unexpected FP-extend for return value.\""
, "/build/llvm-toolchain-snapshot-13~++20210405022414+5f57793c4fe4/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 2717, __PRETTY_FUNCTION__))
2717 "Unexpected FP-extend for return value.")((VA.getLocInfo() != CCValAssign::FPExt && "Unexpected FP-extend for return value."
) ? static_cast<void> (0) : __assert_fail ("VA.getLocInfo() != CCValAssign::FPExt && \"Unexpected FP-extend for return value.\""
, "/build/llvm-toolchain-snapshot-13~++20210405022414+5f57793c4fe4/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 2717, __PRETTY_FUNCTION__))
;
2718
2719 // Report an error if we have attempted to return a value via an XMM
2720 // register and SSE was disabled.
2721 if (!Subtarget.hasSSE1() && X86::FR32XRegClass.contains(VA.getLocReg())) {
2722 errorUnsupported(DAG, dl, "SSE register return with SSE disabled");
2723 VA.convertToReg(X86::FP0); // Set reg to FP0, avoid hitting asserts.
2724 } else if (!Subtarget.hasSSE2() &&
2725 X86::FR64XRegClass.contains(VA.getLocReg()) &&
2726 ValVT == MVT::f64) {
2727 // When returning a double via an XMM register, report an error if SSE2 is
2728 // not enabled.
2729 errorUnsupported(DAG, dl, "SSE2 register return with SSE2 disabled");
2730 VA.convertToReg(X86::FP0); // Set reg to FP0, avoid hitting asserts.
2731 }
2732
2733 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
2734 // the RET instruction and handled by the FP Stackifier.
2735 if (VA.getLocReg() == X86::FP0 ||
2736 VA.getLocReg() == X86::FP1) {
2737 // If this is a copy from an xmm register to ST(0), use an FPExtend to
2738 // change the value to the FP stack register class.
2739 if (isScalarFPTypeInSSEReg(VA.getValVT()))
2740 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
2741 RetVals.push_back(std::make_pair(VA.getLocReg(), ValToCopy));
2742 // Don't emit a copytoreg.
2743 continue;
2744 }
2745
2746 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
2747 // which is returned in RAX / RDX.
2748 if (Subtarget.is64Bit()) {
2749 if (ValVT == MVT::x86mmx) {
2750 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
2751 ValToCopy = DAG.getBitcast(MVT::i64, ValToCopy);
2752 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
2753 ValToCopy);
2754 // If we don't have SSE2 available, convert to v4f32 so the generated
2755 // register is legal.
2756 if (!Subtarget.hasSSE2())
2757 ValToCopy = DAG.getBitcast(MVT::v4f32, ValToCopy);
2758 }
2759 }
2760 }
2761
2762 if (VA.needsCustom()) {
2763 assert(VA.getValVT() == MVT::v64i1 &&((VA.getValVT() == MVT::v64i1 && "Currently the only custom case is when we split v64i1 to 2 regs"
) ? static_cast<void> (0) : __assert_fail ("VA.getValVT() == MVT::v64i1 && \"Currently the only custom case is when we split v64i1 to 2 regs\""
, "/build/llvm-toolchain-snapshot-13~++20210405022414+5f57793c4fe4/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 2764, __PRETTY_FUNCTION__))
2764 "Currently the only custom case is when we split v64i1 to 2 regs")((VA.getValVT() == MVT::v64i1 && "Currently the only custom case is when we split v64i1 to 2 regs"
) ? static_cast<void> (0) : __assert_fail ("VA.getValVT() == MVT::v64i1 && \"Currently the only custom case is when we split v64i1 to 2 regs\""
, "/build/llvm-toolchain-snapshot-13~++20210405022414+5f57793c4fe4/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 2764, __PRETTY_FUNCTION__))
;
2765
2766 Passv64i1ArgInRegs(dl, DAG, ValToCopy, RetVals, VA, RVLocs[++I],
2767 Subtarget);
2768
2769 // Add the second register to the CalleeSaveDisableRegs list.
2770 if (ShouldDisableCalleeSavedRegister)
2771 MF.getRegInfo().disableCalleeSavedRegister(RVLocs[I].getLocReg());
2772 } else {
2773 RetVals.push_back(std::make_pair(VA.getLocReg(), ValToCopy));
2774 }
2775 }
2776
2777 SDValue Flag;
2778 SmallVector<SDValue, 6> RetOps;
2779 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
2780 // Operand #1 = Bytes To Pop
2781 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(), dl,
2782 MVT::i32));
2783
2784 // Copy the result values into the output registers.
2785 for (auto &RetVal : RetVals) {
2786 if (RetVal.first == X86::FP0 || RetVal.first == X86::FP1) {
2787 RetOps.push_back(RetVal.second);
2788 continue; // Don't emit a copytoreg.
2789 }
2790
2791 Chain = DAG.getCopyToReg(Chain, dl, RetVal.first, RetVal.second, Flag);
2792 Flag = Chain.getValue(1);
2793 RetOps.push_back(
2794 DAG.getRegister(RetVal.first, RetVal.second.getValueType()));
2795 }
2796
2797 // Swift calling convention does not require we copy the sret argument
2798 // into %rax/%eax for the return, and SRetReturnReg is not set for Swift.
2799
2800 // All x86 ABIs require that for returning structs by value we copy
2801 // the sret argument into %rax/%eax (depending on ABI) for the return.
2802 // We saved the argument into a virtual register in the entry block,
2803 // so now we copy the value out and into %rax/%eax.
2804 //
2805 // Checking Function.hasStructRetAttr() here is insufficient because the IR
2806 // may not have an explicit sret argument. If FuncInfo.CanLowerReturn is
2807 // false, then an sret argument may be implicitly inserted in the SelDAG. In
2808 // either case FuncInfo->setSRetReturnReg() will have been called.
2809 if (Register SRetReg = FuncInfo->getSRetReturnReg()) {
2810 // When we have both sret and another return value, we should use the
2811 // original Chain stored in RetOps[0], instead of the current Chain updated
2812 // in the above loop. If we only have sret, RetOps[0] equals to Chain.
2813
2814 // For the case of sret and another return value, we have
2815 // Chain_0 at the function entry
2816 // Chain_1 = getCopyToReg(Chain_0) in the above loop
2817 // If we use Chain_1 in getCopyFromReg, we will have
2818 // Val = getCopyFromReg(Chain_1)
2819 // Chain_2 = getCopyToReg(Chain_1, Val) from below
2820
2821 // getCopyToReg(Chain_0) will be glued together with
2822 // getCopyToReg(Chain_1, Val) into Unit A, getCopyFromReg(Chain_1) will be
2823 // in Unit B, and we will have cyclic dependency between Unit A and Unit B:
2824 // Data dependency from Unit B to Unit A due to usage of Val in
2825 // getCopyToReg(Chain_1, Val)
2826 // Chain dependency from Unit A to Unit B
2827
2828 // So here, we use RetOps[0] (i.e Chain_0) for getCopyFromReg.
2829 SDValue Val = DAG.getCopyFromReg(RetOps[0], dl, SRetReg,
2830 getPointerTy(MF.getDataLayout()));
2831
2832 Register RetValReg
2833 = (Subtarget.is64Bit() && !Subtarget.isTarget64BitILP32()) ?
2834 X86::RAX : X86::EAX;
2835 Chain = DAG.getCopyToReg(Chain, dl, RetValReg, Val, Flag);
2836 Flag = Chain.getValue(1);
2837
2838 // RAX/EAX now acts like a return value.
2839 RetOps.push_back(
2840 DAG.getRegister(RetValReg, getPointerTy(DAG.getDataLayout())));
2841
2842 // Add the returned register to the CalleeSaveDisableRegs list.
2843 if (ShouldDisableCalleeSavedRegister)
2844 MF.getRegInfo().disableCalleeSavedRegister(RetValReg);
2845 }
2846
2847 const X86RegisterInfo *TRI = Subtarget.getRegisterInfo();
2848 const MCPhysReg *I =
2849 TRI->getCalleeSavedRegsViaCopy(&DAG.getMachineFunction());
2850 if (I) {
2851 for (; *I; ++I) {
2852 if (X86::GR64RegClass.contains(*I))
2853 RetOps.push_back(DAG.getRegister(*I, MVT::i64));
2854 else
2855 llvm_unreachable("Unexpected register class in CSRsViaCopy!")::llvm::llvm_unreachable_internal("Unexpected register class in CSRsViaCopy!"
, "/build/llvm-toolchain-snapshot-13~++20210405022414+5f57793c4fe4/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 2855)
;
2856 }
2857 }
2858
2859 RetOps[0] = Chain; // Update chain.
2860
2861 // Add the flag if we have it.
2862 if (Flag.getNode())
2863 RetOps.push_back(Flag);
2864
2865 X86ISD::NodeType opcode = X86ISD::RET_FLAG;
2866 if (CallConv == CallingConv::X86_INTR)
2867 opcode = X86ISD::IRET;
2868 return DAG.getNode(opcode, dl, MVT::Other, RetOps);
2869}
2870
2871bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
2872 if (N->getNumValues() != 1 || !N->hasNUsesOfValue(1, 0))
2873 return false;
2874
2875 SDValue TCChain = Chain;
2876 SDNode *Copy = *N->use_begin();
2877 if (Copy->getOpcode() == ISD::CopyToReg) {
2878 // If the copy has a glue operand, we conservatively assume it isn't safe to
2879 // perform a tail call.
2880 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
2881 return false;
2882 TCChain = Copy->getOperand(0);
2883 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
2884 return false;
2885
2886 bool HasRet = false;
2887 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
2888 UI != UE; ++UI) {
2889 if (UI->getOpcode() != X86ISD::RET_FLAG)
2890 return false;
2891 // If we are returning more than one value, we can definitely
2892 // not make a tail call see PR19530
2893 if (UI->getNumOperands() > 4)
2894 return false;
2895 if (UI->getNumOperands() == 4 &&
2896 UI->getOperand(UI->getNumOperands()-1).getValueType() != MVT::Glue)
2897 return false;
2898 HasRet = true;
2899 }
2900
2901 if (!HasRet)
2902 return false;
2903
2904 Chain = TCChain;
2905 return true;
2906}
2907
2908EVT X86TargetLowering::getTypeForExtReturn(LLVMContext &Context, EVT VT,
2909 ISD::NodeType ExtendKind) const {
2910 MVT ReturnMVT = MVT::i32;
2911
2912 bool Darwin = Subtarget.getTargetTriple().isOSDarwin();
2913 if (VT == MVT::i1 || (!Darwin && (VT == MVT::i8 || VT == MVT::i16))) {
2914 // The ABI does not require i1, i8 or i16 to be extended.
2915 //
2916 // On Darwin, there is code in the wild relying on Clang's old behaviour of
2917 // always extending i8/i16 return values, so keep doing that for now.
2918 // (PR26665).
2919 ReturnMVT = MVT::i8;
2920 }
2921
2922 EVT MinVT = getRegisterType(Context, ReturnMVT);
2923 return VT.bitsLT(MinVT) ? MinVT : VT;
2924}
2925
2926/// Reads two 32 bit registers and creates a 64 bit mask value.
2927/// \param VA The current 32 bit value that need to be assigned.
2928/// \param NextVA The next 32 bit value that need to be assigned.
2929/// \param Root The parent DAG node.
2930/// \param [in,out] InFlag Represents SDvalue in the parent DAG node for
2931/// glue purposes. In the case the DAG is already using
2932/// physical register instead of virtual, we should glue
2933/// our new SDValue to InFlag SDvalue.
2934/// \return a new SDvalue of size 64bit.
2935static SDValue getv64i1Argument(CCValAssign &VA, CCValAssign &NextVA,
2936 SDValue &Root, SelectionDAG &DAG,
2937 const SDLoc &Dl, const X86Subtarget &Subtarget,
2938 SDValue *InFlag = nullptr) {
2939 assert((Subtarget.hasBWI()) && "Expected AVX512BW target!")(((Subtarget.hasBWI()) && "Expected AVX512BW target!"
) ? static_cast<void> (0) : __assert_fail ("(Subtarget.hasBWI()) && \"Expected AVX512BW target!\""
, "/build/llvm-toolchain-snapshot-13~++20210405022414+5f57793c4fe4/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 2939, __PRETTY_FUNCTION__))
;
2940 assert(Subtarget.is32Bit() && "Expecting 32 bit target")((Subtarget.is32Bit() && "Expecting 32 bit target") ?
static_cast<void> (0) : __assert_fail ("Subtarget.is32Bit() && \"Expecting 32 bit target\""
, "/build/llvm-toolchain-snapshot-13~++20210405022414+5f57793c4fe4/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 2940, __PRETTY_FUNCTION__))
;
2941 assert(VA.getValVT() == MVT::v64i1 &&((VA.getValVT() == MVT::v64i1 && "Expecting first location of 64 bit width type"
) ? static_cast<void> (0) : __assert_fail ("VA.getValVT() == MVT::v64i1 && \"Expecting first location of 64 bit width type\""
, "/build/llvm-toolchain-snapshot-13~++20210405022414+5f57793c4fe4/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 2942, __PRETTY_FUNCTION__))
2942 "Expecting first location of 64 bit width type")((VA.getValVT() == MVT::v64i1 && "Expecting first location of 64 bit width type"
) ? static_cast<void> (0) : __assert_fail ("VA.getValVT() == MVT::v64i1 && \"Expecting first location of 64 bit width type\""
, "/build/llvm-toolchain-snapshot-13~++20210405022414+5f57793c4fe4/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 2942, __PRETTY_FUNCTION__))
;
2943 assert(NextVA.getValVT() == VA.getValVT() &&((NextVA.getValVT() == VA.getValVT() && "The locations should have the same type"
) ? static_cast<void> (0) : __assert_fail ("NextVA.getValVT() == VA.getValVT() && \"The locations should have the same type\""
, "/build/llvm-toolchain-snapshot-13~++20210405022414+5f57793c4fe4/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 2944, __PRETTY_FUNCTION__))
2944 "The locations should have the same type")((NextVA.getValVT() == VA.getValVT() && "The locations should have the same type"
) ? static_cast<void> (0) : __assert_fail ("NextVA.getValVT() == VA.getValVT() && \"The locations should have the same type\""
, "/build/llvm-toolchain-snapshot-13~++20210405022414+5f57793c4fe4/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 2944, __PRETTY_FUNCTION__))
;
2945 assert(VA.isRegLoc() && NextVA.isRegLoc() &&((VA.isRegLoc() && NextVA.isRegLoc() && "The values should reside in two registers"
) ? static_cast<void> (0) : __assert_fail ("VA.isRegLoc() && NextVA.isRegLoc() && \"The values should reside in two registers\""
, "/build/llvm-toolchain-snapshot-13~++20210405022414+5f57793c4fe4/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 2946, __PRETTY_FUNCTION__))
2946 "The values should reside in two registers")((VA.isRegLoc() && NextVA.isRegLoc() && "The values should reside in two registers"
) ? static_cast<void> (0) : __assert_fail ("VA.isRegLoc() && NextVA.isRegLoc() && \"The values should reside in two registers\""
, "/build/llvm-toolchain-snapshot-13~++20210405022414+5f57793c4fe4/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 2946, __PRETTY_FUNCTION__))
;
2947
2948 SDValue Lo, Hi;
2949 SDValue ArgValueLo, ArgValueHi;
2950
2951 MachineFunction &MF = DAG.getMachineFunction();
2952 const TargetRegisterClass *RC = &X86::GR32RegClass;
2953
2954 // Read a 32 bit value from the registers.
2955 if (nullptr == InFlag) {
2956 // When no physical register is present,
2957 // create an intermediate virtual register.
2958 Register Reg = MF.addLiveIn(VA.getLocReg(), RC);
2959 ArgValueLo = DAG.getCopyFromReg(Root, Dl, Reg, MVT::i32);
2960 Reg = MF.addLiveIn(NextVA.getLocReg(), RC);
2961 ArgValueHi = DAG.getCopyFromReg(Root, Dl, Reg, MVT::i32);
2962 } else {
2963 // When a physical register is available read the value from it and glue
2964 // the reads together.
2965 ArgValueLo =
2966 DAG.getCopyFromReg(Root, Dl, VA.getLocReg(), MVT::i32, *InFlag);
2967 *InFlag = ArgValueLo.getValue(2);
2968 ArgValueHi =
2969 DAG.getCopyFromReg(Root, Dl, NextVA.getLocReg(), MVT::i32, *InFlag);
2970 *InFlag = ArgValueHi.getValue(2);
2971 }
2972
2973 // Convert the i32 type into v32i1 type.
2974 Lo = DAG.getBitcast(MVT::v32i1, ArgValueLo);
2975
2976 // Convert the i32 type into v32i1 type.
2977 Hi = DAG.getBitcast(MVT::v32i1, ArgValueHi);
2978
2979 // Concatenate the two values together.
2980 return DAG.getNode(ISD::CONCAT_VECTORS, Dl, MVT::v64i1, Lo, Hi);
2981}
2982
2983/// The function will lower a register of various sizes (8/16/32/64)
2984/// to a mask value of the expected size (v8i1/v16i1/v32i1/v64i1)
2985/// \returns a DAG node contains the operand after lowering to mask type.
2986static SDValue lowerRegToMasks(const SDValue &ValArg, const EVT &ValVT,
2987 const EVT &ValLoc, const SDLoc &Dl,
2988 SelectionDAG &DAG) {
2989 SDValue ValReturned = ValArg;
2990
2991 if (ValVT == MVT::v1i1)
2992 return DAG.getNode(ISD::SCALAR_TO_VECTOR, Dl, MVT::v1i1, ValReturned);
2993
2994 if (ValVT == MVT::v64i1) {
2995 // In 32 bit machine, this case is handled by getv64i1Argument
2996 assert(ValLoc == MVT::i64 && "Expecting only i64 locations")((ValLoc == MVT::i64 && "Expecting only i64 locations"
) ? static_cast<void> (0) : __assert_fail ("ValLoc == MVT::i64 && \"Expecting only i64 locations\""
, "/build/llvm-toolchain-snapshot-13~++20210405022414+5f57793c4fe4/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 2996, __PRETTY_FUNCTION__))
;
2997 // In 64 bit machine, There is no need to truncate the value only bitcast
2998 } else {
2999 MVT maskLen;
3000 switch (ValVT.getSimpleVT().SimpleTy) {
3001 case MVT::v8i1:
3002 maskLen = MVT::i8;
3003 break;
3004 case MVT::v16i1:
3005 maskLen = MVT::i16;
3006 break;
3007 case MVT::v32i1:
3008 maskLen = MVT::i32;
3009 break;
3010 default:
3011 llvm_unreachable("Expecting a vector of i1 types")::llvm::llvm_unreachable_internal("Expecting a vector of i1 types"
, "/build/llvm-toolchain-snapshot-13~++20210405022414+5f57793c4fe4/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 3011)
;
3012 }
3013
3014 ValReturned = DAG.getNode(ISD::TRUNCATE, Dl, maskLen, ValReturned);
3015 }
3016 return DAG.getBitcast(ValVT, ValReturned);
3017}
3018
3019/// Lower the result values of a call into the
3020/// appropriate copies out of appropriate physical registers.
3021///
3022SDValue X86TargetLowering::LowerCallResult(
3023 SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg,
3024 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
3025 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals,
3026 uint32_t *RegMask) const {
3027
3028 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
3029 // Assign locations to each value returned by this call.
3030 SmallVector<CCValAssign, 16> RVLocs;
3031 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
3032 *DAG.getContext());
3033 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
3034
3035 // Copy all of the result registers out of their specified physreg.
3036 for (unsigned I = 0, InsIndex = 0, E = RVLocs.size(); I != E;
3037 ++I, ++InsIndex) {
3038 CCValAssign &VA = RVLocs[I];
3039 EVT CopyVT = VA.getLocVT();
3040
3041 // In some calling conventions we need to remove the used registers
3042 // from the register mask.
3043 if (RegMask) {
3044 for (MCSubRegIterator SubRegs(VA.getLocReg(), TRI, /*IncludeSelf=*/true);
3045 SubRegs.isValid(); ++SubRegs)
3046 RegMask[*SubRegs / 32] &= ~(1u << (*SubRegs % 32));
3047 }
3048
3049 // Report an error if there was an attempt to return FP values via XMM
3050 // registers.
3051 if (!Subtarget.hasSSE1() && X86::FR32XRegClass.contains(VA.getLocReg())) {
3052 errorUnsupported(DAG, dl, "SSE register return with SSE disabled");
3053 if (VA.getLocReg() == X86::XMM1)
3054 VA.convertToReg(X86::FP1); // Set reg to FP1, avoid hitting asserts.
3055 else
3056 VA.convertToReg(X86::FP0); // Set reg to FP0, avoid hitting asserts.
3057 } else if (!Subtarget.hasSSE2() &&
3058 X86::FR64XRegClass.contains(VA.getLocReg()) &&
3059 CopyVT == MVT::f64) {
3060 errorUnsupported(DAG, dl, "SSE2 register return with SSE2 disabled");
3061 if (VA.getLocReg() == X86::XMM1)
3062 VA.convertToReg(X86::FP1); // Set reg to FP1, avoid hitting asserts.
3063 else
3064 VA.convertToReg(X86::FP0); // Set reg to FP0, avoid hitting asserts.
3065 }
3066
3067 // If we prefer to use the value in xmm registers, copy it out as f80 and
3068 // use a truncate to move it from fp stack reg to xmm reg.
3069 bool RoundAfterCopy = false;
3070 if ((VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1) &&
3071 isScalarFPTypeInSSEReg(VA.getValVT())) {
3072 if (!Subtarget.hasX87())
3073 report_fatal_error("X87 register return with X87 disabled");
3074 CopyVT = MVT::f80;
3075 RoundAfterCopy = (CopyVT != VA.getLocVT());
3076 }
3077
3078 SDValue Val;
3079 if (VA.needsCustom()) {
3080 assert(VA.getValVT() == MVT::v64i1 &&((VA.getValVT() == MVT::v64i1 && "Currently the only custom case is when we split v64i1 to 2 regs"
) ? static_cast<void> (0) : __assert_fail ("VA.getValVT() == MVT::v64i1 && \"Currently the only custom case is when we split v64i1 to 2 regs\""
, "/build/llvm-toolchain-snapshot-13~++20210405022414+5f57793c4fe4/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 3081, __PRETTY_FUNCTION__))
3081 "Currently the only custom case is when we split v64i1 to 2 regs")((VA.getValVT() == MVT::v64i1 && "Currently the only custom case is when we split v64i1 to 2 regs"
) ? static_cast<void> (0) : __assert_fail ("VA.getValVT() == MVT::v64i1 && \"Currently the only custom case is when we split v64i1 to 2 regs\""
, "/build/llvm-toolchain-snapshot-13~++20210405022414+5f57793c4fe4/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 3081, __PRETTY_FUNCTION__))
;
3082 Val =
3083 getv64i1Argument(VA, RVLocs[++I], Chain, DAG, dl, Subtarget, &InFlag);
3084 } else {
3085 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), CopyVT, InFlag)
3086 .getValue(1);
3087 Val = Chain.getValue(0);
3088 InFlag = Chain.getValue(2);
3089 }
3090
3091 if (RoundAfterCopy)
3092 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
3093 // This truncation won't change the value.
3094 DAG.getIntPtrConstant(1, dl));
3095
3096 if (VA.isExtInLoc()) {
3097 if (VA.getValVT().isVector() &&
3098 VA.getValVT().getScalarType() == MVT::i1 &&
3099 ((VA.getLocVT() == MVT::i64) || (VA.getLocVT() == MVT::i32) ||
3100 (VA.getLocVT() == MVT::i16) || (VA.getLocVT() == MVT::i8))) {
3101 // promoting a mask type (v*i1) into a register of type i64/i32/i16/i8
3102 Val = lowerRegToMasks(Val, VA.getValVT(), VA.getLocVT(), dl, DAG);
3103 } else
3104 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
3105 }
3106
3107 if (VA.getLocInfo() == CCValAssign::BCvt)
3108 Val = DAG.getBitcast(VA.getValVT(), Val);
3109
3110 InVals.push_back(Val);
3111 }
3112
3113 return Chain;
3114}
3115
3116//===----------------------------------------------------------------------===//
3117// C & StdCall & Fast Calling Convention implementation
3118//===----------------------------------------------------------------------===//
3119// StdCall calling convention seems to be standard for many Windows' API
3120// routines and around. It differs from C calling convention just a little:
3121// callee should clean up the stack, not caller. Symbols should be also
3122// decorated in some fancy way :) It doesn't support any vector arguments.
3123// For info on fast calling convention see Fast Calling Convention (tail call)
3124// implementation LowerX86_32FastCCCallTo.
3125
3126/// CallIsStructReturn - Determines whether a call uses struct return
3127/// semantics.
3128enum StructReturnType {
3129 NotStructReturn,
3130 RegStructReturn,
3131 StackStructReturn
3132};
3133static StructReturnType
3134callIsStructReturn(ArrayRef<ISD::OutputArg> Outs, bool IsMCU) {
3135 if (Outs.empty())
3136 return NotStructReturn;
3137
3138 const ISD::ArgFlagsTy &Flags = Outs[0].Flags;
3139 if (!Flags.isSRet())
3140 return NotStructReturn;
3141 if (Flags.isInReg() || IsMCU)
3142 return RegStructReturn;
3143 return StackStructReturn;
3144}
3145
3146/// Determines whether a function uses struct return semantics.
3147static StructReturnType
3148argsAreStructReturn(ArrayRef<ISD::InputArg> Ins, bool IsMCU) {
3149 if (Ins.empty())
3150 return NotStructReturn;
3151
3152 const ISD::ArgFlagsTy &Flags = Ins[0].Flags;
3153 if (!Flags.isSRet())
3154 return NotStructReturn;
3155 if (Flags.isInReg() || IsMCU)
3156 return RegStructReturn;
3157 return StackStructReturn;
3158}
3159
3160/// Make a copy of an aggregate at address specified by "Src" to address
3161/// "Dst" with size and alignment information specified by the specific
3162/// parameter attribute. The copy will be passed as a byval function parameter.
3163static SDValue CreateCopyOfByValArgument(SDValue Src, SDValue Dst,
3164 SDValue Chain, ISD::ArgFlagsTy Flags,
3165 SelectionDAG &DAG, const SDLoc &dl) {
3166 SDValue SizeNode = DAG.getIntPtrConstant(Flags.getByValSize(), dl);
3167
3168 return DAG.getMemcpy(
3169 Chain, dl, Dst, Src, SizeNode, Flags.getNonZeroByValAlign(),
3170 /*isVolatile*/ false, /*AlwaysInline=*/true,
3171 /*isTailCall*/ false, MachinePointerInfo(), MachinePointerInfo());
3172}
3173
3174/// Return true if the calling convention is one that we can guarantee TCO for.
3175static bool canGuaranteeTCO(CallingConv::ID CC) {
3176 return (CC == CallingConv::Fast || CC == CallingConv::GHC ||
3177 CC == CallingConv::X86_RegCall || CC == CallingConv::HiPE ||
3178 CC == CallingConv::HHVM || CC == CallingConv::Tail);
3179}
3180
3181/// Return true if we might ever do TCO for calls with this calling convention.
3182static bool mayTailCallThisCC(CallingConv::ID CC) {
3183 switch (CC) {
3184 // C calling conventions:
3185 case CallingConv::C:
3186 case CallingConv::Win64:
3187 case CallingConv::X86_64_SysV:
3188 // Callee pop conventions:
3189 case CallingConv::X86_ThisCall:
3190 case CallingConv::X86_StdCall:
3191 case CallingConv::X86_VectorCall:
3192 case CallingConv::X86_FastCall:
3193 // Swift:
3194 case CallingConv::Swift:
3195 return true;
3196 default:
3197 return canGuaranteeTCO(CC);
3198 }
3199}
3200
3201/// Return true if the function is being made into a tailcall target by
3202/// changing its ABI.
3203static bool shouldGuaranteeTCO(CallingConv::ID CC, bool GuaranteedTailCallOpt) {
3204 return (GuaranteedTailCallOpt && canGuaranteeTCO(CC)) || CC == CallingConv::Tail;
3205}
3206
3207bool X86TargetLowering::mayBeEmittedAsTailCall(const CallInst *CI) const {
3208 if (!CI->isTailCall())
3209 return false;
3210
3211 CallingConv::ID CalleeCC = CI->getCallingConv();
3212 if (!mayTailCallThisCC(CalleeCC))
3213 return false;
3214
3215 return true;
3216}
3217
3218SDValue
3219X86TargetLowering::LowerMemArgument(SDValue Chain, CallingConv::ID CallConv,
3220 const SmallVectorImpl<ISD::InputArg> &Ins,
3221 const SDLoc &dl, SelectionDAG &DAG,
3222 const CCValAssign &VA,
3223 MachineFrameInfo &MFI, unsigned i) const {
3224 // Create the nodes corresponding to a load from this parameter slot.
3225 ISD::ArgFlagsTy Flags = Ins[i].Flags;
3226 bool AlwaysUseMutable = shouldGuaranteeTCO(
3227 CallConv, DAG.getTarget().Options.GuaranteedTailCallOpt);
3228 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
3229 EVT ValVT;
3230 MVT PtrVT = getPointerTy(DAG.getDataLayout());
3231
3232 // If value is passed by pointer we have address passed instead of the value
3233 // itself. No need to extend if the mask value and location share the same
3234 // absolute size.
3235 bool ExtendedInMem =
3236 VA.isExtInLoc() && VA.getValVT().getScalarType() == MVT::i1 &&
3237 VA.getValVT().getSizeInBits() != VA.getLocVT().getSizeInBits();
3238
3239 if (VA.getLocInfo() == CCValAssign::Indirect || ExtendedInMem)
3240 ValVT = VA.getLocVT();
3241 else
3242 ValVT = VA.getValVT();
3243
3244 // FIXME: For now, all byval parameter objects are marked mutable. This can be
3245 // changed with more analysis.
3246 // In case of tail call optimization mark all arguments mutable. Since they
3247 // could be overwritten by lowering of arguments in case of a tail call.
3248 if (Flags.isByVal()) {
3249 unsigned Bytes = Flags.getByValSize();
3250 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
3251
3252 // FIXME: For now, all byval parameter objects are marked as aliasing. This
3253 // can be improved with deeper analysis.
3254 int FI = MFI.CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable,
3255 /*isAliased=*/true);
3256 return DAG.getFrameIndex(FI, PtrVT);
3257 }
3258
3259 EVT ArgVT = Ins[i].ArgVT;
3260
3261 // If this is a vector that has been split into multiple parts, and the
3262 // scalar size of the parts don't match the vector element size, then we can't
3263 // elide the copy. The parts will have padding between them instead of being
3264 // packed like a vector.
3265 bool ScalarizedAndExtendedVector =
3266 ArgVT.isVector() && !VA.getLocVT().isVector() &&
3267 VA.getLocVT().getSizeInBits() != ArgVT.getScalarSizeInBits();
3268
3269 // This is an argument in memory. We might be able to perform copy elision.
3270 // If the argument is passed directly in memory without any extension, then we
3271 // can perform copy elision. Large vector types, for example, may be passed
3272 // indirectly by pointer.
3273 if (Flags.isCopyElisionCandidate() &&
3274 VA.getLocInfo() != CCValAssign::Indirect && !ExtendedInMem &&
3275 !ScalarizedAndExtendedVector) {
3276 SDValue PartAddr;
3277 if (Ins[i].PartOffset == 0) {
3278 // If this is a one-part value or the first part of a multi-part value,
3279 // create a stack object for the entire argument value type and return a
3280 // load from our portion of it. This assumes that if the first part of an
3281 // argument is in memory, the rest will also be in memory.
3282 int FI = MFI.CreateFixedObject(ArgVT.getStoreSize(), VA.getLocMemOffset(),
3283 /*IsImmutable=*/false);
3284 PartAddr = DAG.getFrameIndex(FI, PtrVT);
3285 return DAG.getLoad(
3286 ValVT, dl, Chain, PartAddr,
3287 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI));
3288 } else {
3289 // This is not the first piece of an argument in memory. See if there is
3290 // already a fixed stack object including this offset. If so, assume it
3291 // was created by the PartOffset == 0 branch above and create a load from
3292 // the appropriate offset into it.
3293 int64_t PartBegin = VA.getLocMemOffset();
3294 int64_t PartEnd = PartBegin + ValVT.getSizeInBits() / 8;
3295 int FI = MFI.getObjectIndexBegin();
3296 for (; MFI.isFixedObjectIndex(FI); ++FI) {
3297 int64_t ObjBegin = MFI.getObjectOffset(FI);
3298 int64_t ObjEnd = ObjBegin + MFI.getObjectSize(FI);
3299 if (ObjBegin <= PartBegin && PartEnd <= ObjEnd)
3300 break;
3301 }
3302 if (MFI.isFixedObjectIndex(FI)) {
3303 SDValue Addr =
3304 DAG.getNode(ISD::ADD, dl, PtrVT, DAG.getFrameIndex(FI, PtrVT),
3305 DAG.getIntPtrConstant(Ins[i].PartOffset, dl));
3306 return DAG.getLoad(
3307 ValVT, dl, Chain, Addr,
3308 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI,
3309 Ins[i].PartOffset));
3310 }
3311 }
3312 }
3313
3314 int FI = MFI.CreateFixedObject(ValVT.getSizeInBits() / 8,
3315 VA.getLocMemOffset(), isImmutable);
3316
3317 // Set SExt or ZExt flag.
3318 if (VA.getLocInfo() == CCValAssign::ZExt) {
3319 MFI.setObjectZExt(FI, true);
3320 } else if (VA.getLocInfo() == CCValAssign::SExt) {
3321 MFI.setObjectSExt(FI, true);
3322 }
3323
3324 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3325 SDValue Val = DAG.getLoad(
3326 ValVT, dl, Chain, FIN,
3327 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI));
3328 return ExtendedInMem
3329 ? (VA.getValVT().isVector()
3330 ? DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VA.getValVT(), Val)
3331 : DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val))
3332 : Val;
3333}
3334
3335// FIXME: Get this from tablegen.
3336static ArrayRef<MCPhysReg> get64BitArgumentGPRs(CallingConv::ID CallConv,
3337 const X86Subtarget &Subtarget) {
3338 assert(Subtarget.is64Bit())((Subtarget.is64Bit()) ? static_cast<void> (0) : __assert_fail
("Subtarget.is64Bit()", "/build/llvm-toolchain-snapshot-13~++20210405022414+5f57793c4fe4/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 3338, __PRETTY_FUNCTION__))
;
3339
3340 if (Subtarget.isCallingConvWin64(CallConv)) {
3341 static const MCPhysReg GPR64ArgRegsWin64[] = {
3342 X86::RCX, X86::RDX, X86::R8, X86::R9
3343 };
3344 return makeArrayRef(std::begin(GPR64ArgRegsWin64), std::end(GPR64ArgRegsWin64));
3345 }
3346
3347 static const MCPhysReg GPR64ArgRegs64Bit[] = {
3348 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
3349 };
3350 return makeArrayRef(std::begin(GPR64ArgRegs64Bit), std::end(GPR64ArgRegs64Bit));
3351}
3352
3353// FIXME: Get this from tablegen.
3354static ArrayRef<MCPhysReg> get64BitArgumentXMMs(MachineFunction &MF,
3355 CallingConv::ID CallConv,
3356 const X86Subtarget &Subtarget) {
3357 assert(Subtarget.is64Bit())((Subtarget.is64Bit()) ? static_cast<void> (0) : __assert_fail
("Subtarget.is64Bit()", "/build/llvm-toolchain-snapshot-13~++20210405022414+5f57793c4fe4/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 3357, __PRETTY_FUNCTION__))
;
3358 if (Subtarget.isCallingConvWin64(CallConv)) {
3359 // The XMM registers which might contain var arg parameters are shadowed
3360 // in their paired GPR. So we only need to save the GPR to their home
3361 // slots.
3362 // TODO: __vectorcall will change this.
3363 return None;
3364 }
3365
3366 const Function &F = MF.getFunction();
3367 bool NoImplicitFloatOps = F.hasFnAttribute(Attribute::NoImplicitFloat);
3368 bool isSoftFloat = Subtarget.useSoftFloat();
3369 assert(!(isSoftFloat && NoImplicitFloatOps) &&((!(isSoftFloat && NoImplicitFloatOps) && "SSE register cannot be used when SSE is disabled!"
) ? static_cast<void> (0) : __assert_fail ("!(isSoftFloat && NoImplicitFloatOps) && \"SSE register cannot be used when SSE is disabled!\""
, "/build/llvm-toolchain-snapshot-13~++20210405022414+5f57793c4fe4/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 3370, __PRETTY_FUNCTION__))
3370 "SSE register cannot be used when SSE is disabled!")((!(isSoftFloat && NoImplicitFloatOps) && "SSE register cannot be used when SSE is disabled!"
) ? static_cast<void> (0) : __assert_fail ("!(isSoftFloat && NoImplicitFloatOps) && \"SSE register cannot be used when SSE is disabled!\""
, "/build/llvm-toolchain-snapshot-13~++20210405022414+5f57793c4fe4/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 3370, __PRETTY_FUNCTION__))
;
3371 if (isSoftFloat || NoImplicitFloatOps || !Subtarget.hasSSE1())
3372 // Kernel mode asks for SSE to be disabled, so there are no XMM argument
3373 // registers.
3374 return None;
3375
3376 static const MCPhysReg XMMArgRegs64Bit[] = {
3377 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
3378 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
3379 };
3380 return makeArrayRef(std::begin(XMMArgRegs64Bit), std::end(XMMArgRegs64Bit));
3381}
3382
3383#ifndef NDEBUG
3384static bool isSortedByValueNo(ArrayRef<CCValAssign> ArgLocs) {
3385 return llvm::is_sorted(
3386 ArgLocs, [](const CCValAssign &A, const CCValAssign &B) -> bool {
3387 return A.getValNo() < B.getValNo();
3388 });
3389}
3390#endif
3391
3392namespace {
3393/// This is a helper class for lowering variable arguments parameters.
3394class VarArgsLoweringHelper {
3395public:
3396 VarArgsLoweringHelper(X86MachineFunctionInfo *FuncInfo, const SDLoc &Loc,
3397 SelectionDAG &DAG, const X86Subtarget &Subtarget,
3398 CallingConv::ID CallConv, CCState &CCInfo)
3399 : FuncInfo(FuncInfo), DL(Loc), DAG(DAG), Subtarget(Subtarget),
3400 TheMachineFunction(DAG.getMachineFunction()),
3401 TheFunction(TheMachineFunction.getFunction()),
3402 FrameInfo(TheMachineFunction.getFrameInfo()),
3403 FrameLowering(*Subtarget.getFrameLowering()),
3404 TargLowering(DAG.getTargetLoweringInfo()), CallConv(CallConv),
3405 CCInfo(CCInfo) {}
3406
3407 // Lower variable arguments parameters.
3408 void lowerVarArgsParameters(SDValue &Chain, unsigned StackSize);
3409
3410private:
3411 void createVarArgAreaAndStoreRegisters(SDValue &Chain, unsigned StackSize);
3412
3413 void forwardMustTailParameters(SDValue &Chain);
3414
3415 bool is64Bit() const { return Subtarget.is64Bit(); }
3416 bool isWin64() const { return Subtarget.isCallingConvWin64(CallConv); }
3417
3418 X86MachineFunctionInfo *FuncInfo;
3419 const SDLoc &DL;
3420 SelectionDAG &DAG;
3421 const X86Subtarget &Subtarget;
3422 MachineFunction &TheMachineFunction;
3423 const Function &TheFunction;
3424 MachineFrameInfo &FrameInfo;
3425 const TargetFrameLowering &FrameLowering;
3426 const TargetLowering &TargLowering;
3427 CallingConv::ID CallConv;
3428 CCState &CCInfo;
3429};
3430} // namespace
3431
3432void VarArgsLoweringHelper::createVarArgAreaAndStoreRegisters(
3433 SDValue &Chain, unsigned StackSize) {
3434 // If the function takes variable number of arguments, make a frame index for
3435 // the start of the first vararg value... for expansion of llvm.va_start. We
3436 // can skip this if there are no va_start calls.
3437 if (is64Bit() || (CallConv != CallingConv::X86_FastCall &&
3438 CallConv != CallingConv::X86_ThisCall)) {
3439 FuncInfo->setVarArgsFrameIndex(
3440 FrameInfo.CreateFixedObject(1, StackSize, true));
3441 }
3442
3443 // Figure out if XMM registers are in use.
3444 assert(!(Subtarget.useSoftFloat() &&((!(Subtarget.useSoftFloat() && TheFunction.hasFnAttribute
(Attribute::NoImplicitFloat)) && "SSE register cannot be used when SSE is disabled!"
) ? static_cast<void> (0) : __assert_fail ("!(Subtarget.useSoftFloat() && TheFunction.hasFnAttribute(Attribute::NoImplicitFloat)) && \"SSE register cannot be used when SSE is disabled!\""
, "/build/llvm-toolchain-snapshot-13~++20210405022414+5f57793c4fe4/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 3446, __PRETTY_FUNCTION__))
3445 TheFunction.hasFnAttribute(Attribute::NoImplicitFloat)) &&((!(Subtarget.useSoftFloat() && TheFunction.hasFnAttribute
(Attribute::NoImplicitFloat)) && "SSE register cannot be used when SSE is disabled!"
) ? static_cast<void> (0) : __assert_fail ("!(Subtarget.useSoftFloat() && TheFunction.hasFnAttribute(Attribute::NoImplicitFloat)) && \"SSE register cannot be used when SSE is disabled!\""
, "/build/llvm-toolchain-snapshot-13~++20210405022414+5f57793c4fe4/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 3446, __PRETTY_FUNCTION__))
3446 "SSE register cannot be used when SSE is disabled!")((!(Subtarget.useSoftFloat() && TheFunction.hasFnAttribute
(Attribute::NoImplicitFloat)) && "SSE register cannot be used when SSE is disabled!"
) ? static_cast<void> (0) : __assert_fail ("!(Subtarget.useSoftFloat() && TheFunction.hasFnAttribute(Attribute::NoImplicitFloat)) && \"SSE register cannot be used when SSE is disabled!\""
, "/build/llvm-toolchain-snapshot-13~++20210405022414+5f57793c4fe4/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 3446, __PRETTY_FUNCTION__))
;
3447
3448 // 64-bit calling conventions support varargs and register parameters, so we
3449 // have to do extra work to spill them in the prologue.
3450 if (is64Bit()) {
3451 // Find the first unallocated argument registers.
3452 ArrayRef<MCPhysReg> ArgGPRs = get64BitArgumentGPRs(CallConv, Subtarget);
3453 ArrayRef<MCPhysReg> ArgXMMs =
3454 get64BitArgumentXMMs(TheMachineFunction, CallConv, Subtarget);
3455 unsigned NumIntRegs = CCInfo.getFirstUnallocated(ArgGPRs);
3456 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(ArgXMMs);
3457
3458 assert(!(NumXMMRegs && !Subtarget.hasSSE1()) &&((!(NumXMMRegs && !Subtarget.hasSSE1()) && "SSE register cannot be used when SSE is disabled!"
) ? static_cast<void> (0) : __assert_fail ("!(NumXMMRegs && !Subtarget.hasSSE1()) && \"SSE register cannot be used when SSE is disabled!\""
, "/build/llvm-toolchain-snapshot-13~++20210405022414+5f57793c4fe4/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 3459, __PRETTY_FUNCTION__))
3459 "SSE register cannot be used when SSE is disabled!")((!(NumXMMRegs && !Subtarget.hasSSE1()) && "SSE register cannot be used when SSE is disabled!"
) ? static_cast<void> (0) : __assert_fail ("!(NumXMMRegs && !Subtarget.hasSSE1()) && \"SSE register cannot be used when SSE is disabled!\""
, "/build/llvm-toolchain-snapshot-13~++20210405022414+5f57793c4fe4/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 3459, __PRETTY_FUNCTION__))
;
3460
3461 if (isWin64()) {
3462 // Get to the caller-allocated home save location. Add 8 to account
3463 // for the return address.
3464 int HomeOffset = FrameLowering.getOffsetOfLocalArea() + 8;
3465 FuncInfo->setRegSaveFrameIndex(
3466 FrameInfo.CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
3467 // Fixup to set vararg frame on shadow area (4 x i64).
3468 if (NumIntRegs < 4)
3469 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
3470 } else {
3471 // For X86-64, if there are vararg parameters that are passed via
3472 // registers, then we must store them to their spots on the stack so
3473 // they may be loaded by dereferencing the result of va_next.
3474 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
3475 FuncInfo->setVarArgsFPOffset(ArgGPRs.size() * 8 + NumXMMRegs * 16);
3476 FuncInfo->setRegSaveFrameIndex(FrameInfo.CreateStackObject(
3477 ArgGPRs.size() * 8 + ArgXMMs.size() * 16, Align(16), false));
3478 }
3479
3480 SmallVector<SDValue, 6>
3481 LiveGPRs; // list of SDValue for GPR registers keeping live input value
3482 SmallVector<SDValue, 8> LiveXMMRegs; // list of SDValue for XMM registers
3483 // keeping live input value
3484 SDValue ALVal; // if applicable keeps SDValue for %al register
3485
3486 // Gather all the live in physical registers.
3487 for (MCPhysReg Reg : ArgGPRs.slice(NumIntRegs)) {
3488 Register GPR = TheMachineFunction.addLiveIn(Reg, &X86::GR64RegClass);
3489 LiveGPRs.push_back(DAG.getCopyFromReg(Chain, DL, GPR, MVT::i64));
3490 }
3491 const auto &AvailableXmms = ArgXMMs.slice(NumXMMRegs);
3492 if (!AvailableXmms.empty()) {
3493 Register AL = TheMachineFunction.addLiveIn(X86::AL, &X86::GR8RegClass);
3494 ALVal = DAG.getCopyFromReg(Chain, DL, AL, MVT::i8);
3495 for (MCPhysReg Reg : AvailableXmms) {
3496 // FastRegisterAllocator spills virtual registers at basic
3497 // block boundary. That leads to usages of xmm registers
3498 // outside of check for %al. Pass physical registers to
3499 // VASTART_SAVE_XMM_REGS to avoid unneccessary spilling.
3500 TheMachineFunction.getRegInfo().addLiveIn(Reg);
3501 LiveXMMRegs.push_back(DAG.getRegister(Reg, MVT::v4f32));
3502 }
3503 }
3504
3505 // Store the integer parameter registers.
3506 SmallVector<SDValue, 8> MemOps;
3507 SDValue RSFIN =
3508 DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
3509 TargLowering.getPointerTy(DAG.getDataLayout()));
3510 unsigned Offset = FuncInfo->getVarArgsGPOffset();
3511 for (SDValue Val : LiveGPRs) {
3512 SDValue FIN = DAG.getNode(ISD::ADD, DL,
3513 TargLowering.getPointerTy(DAG.getDataLayout()),
3514 RSFIN, DAG.getIntPtrConstant(Offset, DL));
3515 SDValue Store =
3516 DAG.getStore(Val.getValue(1), DL, Val, FIN,
3517 MachinePointerInfo::getFixedStack(
3518 DAG.getMachineFunction(),
3519 FuncInfo->getRegSaveFrameIndex(), Offset));
3520 MemOps.push_back(Store);
3521 Offset += 8;
3522 }
3523
3524 // Now store the XMM (fp + vector) parameter registers.
3525 if (!LiveXMMRegs.empty()) {
3526 SmallVector<SDValue, 12> SaveXMMOps;
3527 SaveXMMOps.push_back(Chain);
3528 SaveXMMOps.push_back(ALVal);
3529 SaveXMMOps.push_back(
3530 DAG.getTargetConstant(FuncInfo->getRegSaveFrameIndex(), DL, MVT::i32));
3531 SaveXMMOps.push_back(
3532 DAG.getTargetConstant(FuncInfo->getVarArgsFPOffset(), DL, MVT::i32));
3533 llvm::append_range(SaveXMMOps, LiveXMMRegs);
3534 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, DL,
3535 MVT::Other, SaveXMMOps));
3536 }
3537
3538 if (!MemOps.empty())
3539 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
3540 }
3541}
3542
3543void VarArgsLoweringHelper::forwardMustTailParameters(SDValue &Chain) {
3544 // Find the largest legal vector type.
3545 MVT VecVT = MVT::Other;
3546 // FIXME: Only some x86_32 calling conventions support AVX512.
3547 if (Subtarget.useAVX512Regs() &&
3548 (is64Bit() || (CallConv == CallingConv::X86_VectorCall ||
3549 CallConv == CallingConv::Intel_OCL_BI)))
3550 VecVT = MVT::v16f32;
3551 else if (Subtarget.hasAVX())
3552 VecVT = MVT::v8f32;
3553 else if (Subtarget.hasSSE2())
3554 VecVT = MVT::v4f32;
3555
3556 // We forward some GPRs and some vector types.
3557 SmallVector<MVT, 2> RegParmTypes;
3558 MVT IntVT = is64Bit() ? MVT::i64 : MVT::i32;
3559 RegParmTypes.push_back(IntVT);
3560 if (VecVT != MVT::Other)
3561 RegParmTypes.push_back(VecVT);
3562
3563 // Compute the set of forwarded registers. The rest are scratch.
3564 SmallVectorImpl<ForwardedRegister> &Forwards =
3565 FuncInfo->getForwardedMustTailRegParms();
3566 CCInfo.analyzeMustTailForwardedRegisters(Forwards, RegParmTypes, CC_X86);
3567
3568 // Forward AL for SysV x86_64 targets, since it is used for varargs.
3569 if (is64Bit() && !isWin64() && !CCInfo.isAllocated(X86::AL)) {
3570 Register ALVReg = TheMachineFunction.addLiveIn(X86::AL, &X86::GR8RegClass);
3571 Forwards.push_back(ForwardedRegister(ALVReg, X86::AL, MVT::i8));
3572 }
3573
3574 // Copy all forwards from physical to virtual registers.
3575 for (ForwardedRegister &FR : Forwards) {
3576 // FIXME: Can we use a less constrained schedule?
3577 SDValue RegVal = DAG.getCopyFromReg(Chain, DL, FR.VReg, FR.VT);
3578 FR.VReg = TheMachineFunction.getRegInfo().createVirtualRegister(
3579 TargLowering.getRegClassFor(FR.VT));
3580 Chain = DAG.getCopyToReg(Chain, DL, FR.VReg, RegVal);
3581 }
3582}
3583
3584void VarArgsLoweringHelper::lowerVarArgsParameters(SDValue &Chain,
3585 unsigned StackSize) {
3586 // Set FrameIndex to the 0xAAAAAAA value to mark unset state.
3587 // If necessary, it would be set into the correct value later.
3588 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
3589 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
3590
3591 if (FrameInfo.hasVAStart())
3592 createVarArgAreaAndStoreRegisters(Chain, StackSize);
3593
3594 if (FrameInfo.hasMustTailInVarArgFunc())
3595 forwardMustTailParameters(Chain);
3596}
3597
3598SDValue X86TargetLowering::LowerFormalArguments(
3599 SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
3600 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
3601 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
3602 MachineFunction &MF = DAG.getMachineFunction();
3603 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
3604
3605 const Function &F = MF.getFunction();
3606 if (F.hasExternalLinkage() && Subtarget.isTargetCygMing() &&
3607 F.getName() == "main")
3608 FuncInfo->setForceFramePointer(true);
3609
3610 MachineFrameInfo &MFI = MF.getFrameInfo();
3611 bool Is64Bit = Subtarget.is64Bit();
3612 bool IsWin64 = Subtarget.isCallingConvWin64(CallConv);
3613
3614 assert(((!(IsVarArg && canGuaranteeTCO(CallConv)) &&
"Var args not supported with calling conv' regcall, fastcc, ghc or hipe"
) ? static_cast<void> (0) : __assert_fail ("!(IsVarArg && canGuaranteeTCO(CallConv)) && \"Var args not supported with calling conv' regcall, fastcc, ghc or hipe\""
, "/build/llvm-toolchain-snapshot-13~++20210405022414+5f57793c4fe4/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 3616, __PRETTY_FUNCTION__))
3615 !(IsVarArg && canGuaranteeTCO(CallConv)) &&((!(IsVarArg && canGuaranteeTCO(CallConv)) &&
"Var args not supported with calling conv' regcall, fastcc, ghc or hipe"
) ? static_cast<void> (0) : __assert_fail ("!(IsVarArg && canGuaranteeTCO(CallConv)) && \"Var args not supported with calling conv' regcall, fastcc, ghc or hipe\""
, "/build/llvm-toolchain-snapshot-13~++20210405022414+5f57793c4fe4/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 3616, __PRETTY_FUNCTION__))
3616 "Var args not supported with calling conv' regcall, fastcc, ghc or hipe")((!(IsVarArg && canGuaranteeTCO(CallConv)) &&
"Var args not supported with calling conv' regcall, fastcc, ghc or hipe"
) ? static_cast<void> (0) : __assert_fail ("!(IsVarArg && canGuaranteeTCO(CallConv)) && \"Var args not supported with calling conv' regcall, fastcc, ghc or hipe\""
, "/build/llvm-toolchain-snapshot-13~++20210405022414+5f57793c4fe4/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 3616, __PRETTY_FUNCTION__))
;
3617
3618 // Assign locations to all of the incoming arguments.
3619 SmallVector<CCValAssign, 16> ArgLocs;
3620 CCState CCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext());
3621
3622 // Allocate shadow area for Win64.
3623 if (IsWin64)
3624 CCInfo.AllocateStack(32, Align(8));
3625
3626 CCInfo.AnalyzeArguments(Ins, CC_X86);
3627
3628 // In vectorcall calling convention a second pass is required for the HVA
3629 // types.
3630 if (CallingConv::X86_VectorCall == CallConv) {
3631 CCInfo.AnalyzeArgumentsSecondPass(Ins, CC_X86);
3632 }
3633
3634 // The next loop assumes that the locations are in the same order of the
3635 // input arguments.
3636 assert(isSortedByValueNo(ArgLocs) &&((isSortedByValueNo(ArgLocs) && "Argument Location list must be sorted before lowering"
) ? static_cast<void> (0) : __assert_fail ("isSortedByValueNo(ArgLocs) && \"Argument Location list must be sorted before lowering\""
, "/build/llvm-toolchain-snapshot-13~++20210405022414+5f57793c4fe4/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 3637, __PRETTY_FUNCTION__))
3637 "Argument Location list must be sorted before lowering")((isSortedByValueNo(ArgLocs) && "Argument Location list must be sorted before lowering"
) ? static_cast<void> (0) : __assert_fail ("isSortedByValueNo(ArgLocs) && \"Argument Location list must be sorted before lowering\""
, "/build/llvm-toolchain-snapshot-13~++20210405022414+5f57793c4fe4/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 3637, __PRETTY_FUNCTION__))
;
3638
3639 SDValue ArgValue;
3640 for (unsigned I = 0, InsIndex = 0, E = ArgLocs.size(); I != E;
3641 ++I, ++InsIndex) {
3642 assert(InsIndex < Ins.size() && "Invalid Ins index")((InsIndex < Ins.size() && "Invalid Ins index") ? static_cast
<void> (0) : __assert_fail ("InsIndex < Ins.size() && \"Invalid Ins index\""
, "/build/llvm-toolchain-snapshot-13~++20210405022414+5f57793c4fe4/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 3642, __PRETTY_FUNCTION__))
;
3643 CCValAssign &VA = ArgLocs[I];
3644
3645 if (VA.isRegLoc()) {
3646 EVT RegVT = VA.getLocVT();
3647 if (VA.needsCustom()) {
3648 assert(((VA.getValVT() == MVT::v64i1 && "Currently the only custom case is when we split v64i1 to 2 regs"
) ? static_cast<void> (0) : __assert_fail ("VA.getValVT() == MVT::v64i1 && \"Currently the only custom case is when we split v64i1 to 2 regs\""
, "/build/llvm-toolchain-snapshot-13~++20210405022414+5f57793c4fe4/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 3650, __PRETTY_FUNCTION__))
3649 VA.getValVT() == MVT::v64i1 &&((VA.getValVT() == MVT::v64i1 && "Currently the only custom case is when we split v64i1 to 2 regs"
) ? static_cast<void> (0) : __assert_fail ("VA.getValVT() == MVT::v64i1 && \"Currently the only custom case is when we split v64i1 to 2 regs\""
, "/build/llvm-toolchain-snapshot-13~++20210405022414+5f57793c4fe4/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 3650, __PRETTY_FUNCTION__))
3650 "Currently the only custom case is when we split v64i1 to 2 regs")((VA.getValVT() == MVT::v64i1 && "Currently the only custom case is when we split v64i1 to 2 regs"
) ? static_cast<void> (0) : __assert_fail ("VA.getValVT() == MVT::v64i1 && \"Currently the only custom case is when we split v64i1 to 2 regs\""
, "/build/llvm-toolchain-snapshot-13~++20210405022414+5f57793c4fe4/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 3650, __PRETTY_FUNCTION__))
;
3651
3652 // v64i1 values, in regcall calling convention, that are
3653 // compiled to 32 bit arch, are split up into two registers.
3654 ArgValue =
3655 getv64i1Argument(VA, ArgLocs[++I], Chain, DAG, dl, Subtarget);
3656 } else {
3657 const TargetRegisterClass *RC;
3658 if (RegVT == MVT::i8)
3659 RC = &X86::GR8RegClass;
3660 else if (RegVT == MVT::i16)
3661 RC = &X86::GR16RegClass;
3662 else if (RegVT == MVT::i32)
3663 RC = &X86::GR32RegClass;
3664 else if (Is64Bit && RegVT == MVT::i64)
3665 RC = &X86::GR64RegClass;
3666 else if (RegVT == MVT::f32)
3667 RC = Subtarget.hasAVX512() ? &X86::FR32XRegClass : &X86::FR32RegClass;
3668 else if (RegVT == MVT::f64)
3669 RC = Subtarget.hasAVX512() ? &X86::FR64XRegClass : &X86::FR64RegClass;
3670 else if (RegVT == MVT::f80)
3671 RC = &X86::RFP80RegClass;
3672 else if (RegVT == MVT::f128)
3673 RC = &X86::VR128RegClass;
3674 else if (RegVT.is512BitVector())
3675 RC = &X86::VR512RegClass;
3676 else if (RegVT.is256BitVector())
3677 RC = Subtarget.hasVLX() ? &X86::VR256XRegClass : &X86::VR256RegClass;
3678 else if (RegVT.is128BitVector())
3679 RC = Subtarget.hasVLX() ? &X86::VR128XRegClass : &X86::VR128RegClass;
3680 else if (RegVT == MVT::x86mmx)
3681 RC = &X86::VR64RegClass;
3682 else if (RegVT == MVT::v1i1)
3683 RC = &X86::VK1RegClass;
3684 else if (RegVT == MVT::v8i1)
3685 RC = &X86::VK8RegClass;
3686 else if (RegVT == MVT::v16i1)
3687 RC = &X86::VK16RegClass;
3688 else if (RegVT == MVT::v32i1)
3689 RC = &X86::VK32RegClass;
3690 else if (RegVT == MVT::v64i1)
3691 RC = &X86::VK64RegClass;
3692 else
3693 llvm_unreachable("Unknown argument type!")::llvm::llvm_unreachable_internal("Unknown argument type!", "/build/llvm-toolchain-snapshot-13~++20210405022414+5f57793c4fe4/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 3693)
;
3694
3695 Register Reg = MF.addLiveIn(VA.getLocReg(), RC);
3696 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
3697 }
3698
3699 // If this is an 8 or 16-bit value, it is really passed promoted to 32
3700 // bits. Insert an assert[sz]ext to capture this, then truncate to the
3701 // right size.
3702 if (VA.getLocInfo() == CCValAssign::SExt)
3703 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
3704 DAG.getValueType(VA.getValVT()));
3705 else if (VA.getLocInfo() == CCValAssign::ZExt)
3706 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
3707 DAG.getValueType(VA.getValVT()));
3708 else if (VA.getLocInfo() == CCValAssign::BCvt)
3709 ArgValue = DAG.getBitcast(VA.getValVT(), ArgValue);
3710
3711 if (VA.isExtInLoc()) {
3712 // Handle MMX values passed in XMM regs.
3713 if (RegVT.isVector() && VA.getValVT().getScalarType() != MVT::i1)
3714 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), ArgValue);
3715 else if (VA.getValVT().isVector() &&
3716 VA.getValVT().getScalarType() == MVT::i1 &&
3717 ((VA.getLocVT() == MVT::i64) || (VA.getLocVT() == MVT::i32) ||
3718 (VA.getLocVT() == MVT::i16) || (VA.getLocVT() == MVT::i8))) {
3719 // Promoting a mask type (v*i1) into a register of type i64/i32/i16/i8
3720 ArgValue = lowerRegToMasks(ArgValue, VA.getValVT(), RegVT, dl, DAG);
3721 } else
3722 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
3723 }
3724 } else {
3725 assert(VA.isMemLoc())((VA.isMemLoc()) ? static_cast<void> (0) : __assert_fail
("VA.isMemLoc()", "/build/llvm-toolchain-snapshot-13~++20210405022414+5f57793c4fe4/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 3725, __PRETTY_FUNCTION__))
;
3726 ArgValue =
3727 LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, InsIndex);
3728 }
3729
3730 // If value is passed via pointer - do a load.
3731 if (VA.getLocInfo() == CCValAssign::Indirect && !Ins[I].Flags.isByVal())
3732 ArgValue =
3733 DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue, MachinePointerInfo());
3734
3735 InVals.push_back(ArgValue);
3736 }
3737
3738 for (unsigned I = 0, E = Ins.size(); I != E; ++I) {
3739 // Swift calling convention does not require we copy the sret argument
3740 // into %rax/%eax for the return. We don't set SRetReturnReg for Swift.
3741 if (CallConv == CallingConv::Swift)
3742 continue;
3743
3744 // All x86 ABIs require that for returning structs by value we copy the
3745 // sret argument into %rax/%eax (depending on ABI) for the return. Save
3746 // the argument into a virtual register so that we can access it from the
3747 // return points.
3748 if (Ins[I].Flags.isSRet()) {
3749 Register Reg = FuncInfo->getSRetReturnReg();
3750 if (!Reg) {
3751 MVT PtrTy = getPointerTy(DAG.getDataLayout());
3752 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy));
3753 FuncInfo->setSRetReturnReg(Reg);
3754 }
3755 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[I]);
3756 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
3757 break;
3758 }
3759 }
3760
3761 unsigned StackSize = CCInfo.getNextStackOffset();
3762 // Align stack specially for tail calls.
3763 if (shouldGuaranteeTCO(CallConv,
3764 MF.getTarget().Options.GuaranteedTailCallOpt))
3765 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
3766
3767 if (IsVarArg)
3768 VarArgsLoweringHelper(FuncInfo, dl, DAG, Subtarget, CallConv, CCInfo)
3769 .lowerVarArgsParameters(Chain, StackSize);
3770
3771 // Some CCs need callee pop.
3772 if (X86::isCalleePop(CallConv, Is64Bit, IsVarArg,
3773 MF.getTarget().Options.GuaranteedTailCallOpt)) {
3774 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
3775 } else if (CallConv == CallingConv::X86_INTR && Ins.size() == 2) {
3776 // X86 interrupts must pop the error code (and the alignment padding) if
3777 // present.
3778 FuncInfo->setBytesToPopOnReturn(Is64Bit ? 16 : 4);
3779 } else {
3780 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
3781 // If this is an sret function, the return should pop the hidden pointer.
3782 if (!Is64Bit && !canGuaranteeTCO(CallConv) &&
3783 !Subtarget.getTargetTriple().isOSMSVCRT() &&
3784 argsAreStructReturn(Ins, Subtarget.isTargetMCU()) == StackStructReturn)
3785 FuncInfo->setBytesToPopOnReturn(4);
3786 }
3787
3788 if (!Is64Bit) {
3789 // RegSaveFrameIndex is X86-64 only.
3790 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
3791 }
3792
3793 FuncInfo->setArgumentStackSize(StackSize);
3794
3795 if (WinEHFuncInfo *EHInfo = MF.getWinEHFuncInfo()) {
3796 EHPersonality Personality = classifyEHPersonality(F.getPersonalityFn());
3797 if (Personality == EHPersonality::CoreCLR) {
3798 assert(Is64Bit)((Is64Bit) ? static_cast<void> (0) : __assert_fail ("Is64Bit"
, "/build/llvm-toolchain-snapshot-13~++20210405022414+5f57793c4fe4/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 3798, __PRETTY_FUNCTION__))
;
3799 // TODO: Add a mechanism to frame lowering that will allow us to indicate
3800 // that we'd prefer this slot be allocated towards the bottom of the frame
3801 // (i.e. near the stack pointer after allocating the frame). Every
3802 // funclet needs a copy of this slot in its (mostly empty) frame, and the
3803 // offset from the bottom of this and each funclet's frame must be the
3804 // same, so the size of funclets' (mostly empty) frames is dictated by
3805 // how far this slot is from the bottom (since they allocate just enough
3806 // space to accommodate holding this slot at the correct offset).
3807 int PSPSymFI = MFI.CreateStackObject(8, Align(8), /*isSpillSlot=*/false);
3808 EHInfo->PSPSymFrameIdx = PSPSymFI;
3809 }
3810 }
3811
3812 if (CallConv == CallingConv::X86_RegCall ||
3813 F.hasFnAttribute("no_caller_saved_registers")) {
3814 MachineRegisterInfo &MRI = MF.getRegInfo();
3815 for (std::pair<Register, Register> Pair : MRI.liveins())
3816 MRI.disableCalleeSavedRegister(Pair.first);
3817 }
3818
3819 return Chain;
3820}
3821
3822SDValue X86TargetLowering::LowerMemOpCallTo(SDValue Chain, SDValue StackPtr,
3823 SDValue Arg, const SDLoc &dl,
3824 SelectionDAG &DAG,
3825 const CCValAssign &VA,
3826 ISD::ArgFlagsTy Flags,
3827 bool isByVal) const {
3828 unsigned LocMemOffset = VA.getLocMemOffset();
3829 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset, dl);
3830 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(DAG.getDataLayout()),
3831 StackPtr, PtrOff);
3832 if (isByVal)
3833 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
3834
3835 return DAG.getStore(
3836 Chain, dl, Arg, PtrOff,
3837 MachinePointerInfo::getStack(DAG.getMachineFunction(), LocMemOffset));
3838}
3839
3840/// Emit a load of return address if tail call
3841/// optimization is performed and it is required.
3842SDValue X86TargetLowering::EmitTailCallLoadRetAddr(
3843 SelectionDAG &DAG, SDValue &OutRetAddr, SDValue Chain, bool IsTailCall,
3844 bool Is64Bit, int FPDiff, const SDLoc &dl) const {
3845 // Adjust the Return address stack slot.
3846 EVT VT = getPointerTy(DAG.getDataLayout());
3847 OutRetAddr = getReturnAddressFrameIndex(DAG);
3848
3849 // Load the "old" Return address.
3850 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo());
3851 return SDValue(OutRetAddr.getNode(), 1);
3852}
3853
3854/// Emit a store of the return address if tail call
3855/// optimization is performed and it is required (FPDiff!=0).
3856static SDValue EmitTailCallStoreRetAddr(SelectionDAG &DAG, MachineFunction &MF,
3857 SDValue Chain, SDValue RetAddrFrIdx,
3858 EVT PtrVT, unsigned SlotSize,
3859 int FPDiff, const SDLoc &dl) {
3860 // Store the return address to the appropriate stack slot.
3861 if (!FPDiff) return Chain;
3862 // Calculate the new stack slot for the return address.
3863 int NewReturnAddrFI =
3864 MF.getFrameInfo().CreateFixedObject(SlotSize, (int64_t)FPDiff - SlotSize,
3865 false);
3866 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, PtrVT);
3867 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
3868 MachinePointerInfo::getFixedStack(
3869 DAG.getMachineFunction(), NewReturnAddrFI));
3870 return Chain;
3871}
3872
3873/// Returns a vector_shuffle mask for an movs{s|d}, movd
3874/// operation of specified width.
3875static SDValue getMOVL(SelectionDAG &DAG, const SDLoc &dl, MVT VT, SDValue V1,
3876 SDValue V2) {
3877 unsigned NumElems = VT.getVectorNumElements();
3878 SmallVector<int, 8> Mask;
3879 Mask.push_back(NumElems);
3880 for (unsigned i = 1; i != NumElems; ++i)
3881 Mask.push_back(i);
3882 return DAG.getVectorShuffle(VT, dl, V1, V2, Mask);
3883}
3884
3885SDValue
3886X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
3887 SmallVectorImpl<SDValue> &InVals) const {
3888 SelectionDAG &DAG = CLI.DAG;
3889 SDLoc &dl = CLI.DL;
3890 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
3891 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
3892 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
3893 SDValue Chain = CLI.Chain;
3894 SDValue Callee = CLI.Callee;
3895 CallingConv::ID CallConv = CLI.CallConv;
3896 bool &isTailCall = CLI.IsTailCall;
3897 bool isVarArg = CLI.IsVarArg;
3898 const auto *CB = CLI.CB;
3899
3900 MachineFunction &MF = DAG.getMachineFunction();
3901 bool Is64Bit = Subtarget.is64Bit();
3902 bool IsWin64 = Subtarget.isCallingConvWin64(CallConv);
3903 StructReturnType SR = callIsStructReturn(Outs, Subtarget.isTargetMCU());
3904 bool IsSibcall = false;
3905 bool IsGuaranteeTCO = MF.getTarget().Options.GuaranteedTailCallOpt ||
3906 CallConv == CallingConv::Tail;
3907 X86MachineFunctionInfo *X86Info = MF.getInfo<X86MachineFunctionInfo>();
3908 bool HasNCSR = (CB && isa<CallInst>(CB) &&
3909 CB->hasFnAttr("no_caller_saved_registers"));
3910 bool HasNoCfCheck = (CB && CB->doesNoCfCheck());
3911 bool IsIndirectCall = (CB && isa<CallInst>(CB) && CB->isIndirectCall());
3912 const Module *M = MF.getMMI().getModule();
3913 Metadata *IsCFProtectionSupported = M->getModuleFlag("cf-protection-branch");
3914
3915 MachineFunction::CallSiteInfo CSInfo;
3916 if (CallConv == CallingConv::X86_INTR)
3917 report_fatal_error("X86 interrupts may not be called directly");
3918
3919 if (Subtarget.isPICStyleGOT() && !IsGuaranteeTCO) {
3920 // If we are using a GOT, disable tail calls to external symbols with
3921 // default visibility. Tail calling such a symbol requires using a GOT
3922 // relocation, which forces early binding of the symbol. This breaks code
3923 // that require lazy function symbol resolution. Using musttail or
3924 // GuaranteedTailCallOpt will override this.
3925 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
3926 if (!G || (!G->getGlobal()->hasLocalLinkage() &&
3927 G->getGlobal()->hasDefaultVisibility()))
3928 isTailCall = false;
3929 }
3930
3931 bool IsMustTail = CLI.CB && CLI.CB->isMustTailCall();
3932 if (IsMustTail) {
3933 // Force this to be a tail call. The verifier rules are enough to ensure
3934 // that we can lower this successfully without moving the return address
3935 // around.
3936 isTailCall = true;
3937 } else if (isTailCall) {
3938 // Check if it's really possible to do a tail call.
3939 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
3940 isVarArg, SR != NotStructReturn,
3941 MF.getFunction().hasStructRetAttr(), CLI.RetTy,
3942 Outs, OutVals, Ins, DAG);
3943
3944 // Sibcalls are automatically detected tailcalls which do not require
3945 // ABI changes.
3946 if (!IsGuaranteeTCO && isTailCall)
3947 IsSibcall = true;
3948
3949 if (isTailCall)
3950 ++NumTailCalls;
3951 }
3952
3953 assert(!(isVarArg && canGuaranteeTCO(CallConv)) &&((!(isVarArg && canGuaranteeTCO(CallConv)) &&
"Var args not supported with calling convention fastcc, ghc or hipe"
) ? static_cast<void> (0) : __assert_fail ("!(isVarArg && canGuaranteeTCO(CallConv)) && \"Var args not supported with calling convention fastcc, ghc or hipe\""
, "/build/llvm-toolchain-snapshot-13~++20210405022414+5f57793c4fe4/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 3954, __PRETTY_FUNCTION__))
3954 "Var args not supported with calling convention fastcc, ghc or hipe")((!(isVarArg && canGuaranteeTCO(CallConv)) &&
"Var args not supported with calling convention fastcc, ghc or hipe"
) ? static_cast<void> (0) : __assert_fail ("!(isVarArg && canGuaranteeTCO(CallConv)) && \"Var args not supported with calling convention fastcc, ghc or hipe\""
, "/build/llvm-toolchain-snapshot-13~++20210405022414+5f57793c4fe4/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 3954, __PRETTY_FUNCTION__))
;
3955
3956 // Analyze operands of the call, assigning locations to each operand.
3957 SmallVector<CCValAssign, 16> ArgLocs;
3958 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
3959
3960 // Allocate shadow area for Win64.
3961 if (IsWin64)
3962 CCInfo.AllocateStack(32, Align(8));
3963
3964 CCInfo.AnalyzeArguments(Outs, CC_X86);
3965
3966 // In vectorcall calling convention a second pass is required for the HVA
3967 // types.
3968 if (CallingConv::X86_VectorCall == CallConv) {
3969 CCInfo.AnalyzeArgumentsSecondPass(Outs, CC_X86);
3970 }
3971
3972 // Get a count of how many bytes are to be pushed on the stack.
3973 unsigned NumBytes = CCInfo.getAlignedCallFrameSize();
3974 if (IsSibcall)
3975 // This is a sibcall. The memory operands are available in caller's
3976 // own caller's stack.
3977 NumBytes = 0;
3978 else if (IsGuaranteeTCO && canGuaranteeTCO(CallConv))
3979 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
3980
3981 int FPDiff = 0;
3982 if (isTailCall && !IsSibcall && !IsMustTail) {
3983 // Lower arguments at fp - stackoffset + fpdiff.
3984 unsigned NumBytesCallerPushed = X86Info->getBytesToPopOnReturn();
3985
3986 FPDiff = NumBytesCallerPushed - NumBytes;
3987
3988 // Set the delta of movement of the returnaddr stackslot.
3989 // But only set if delta is greater than previous delta.
3990 if (FPDiff < X86Info->getTCReturnAddrDelta())
3991 X86Info->setTCReturnAddrDelta(FPDiff);
3992 }
3993
3994 unsigned NumBytesToPush = NumBytes;
3995 unsigned NumBytesToPop = NumBytes;
3996
3997 // If we have an inalloca argument, all stack space has already been allocated
3998 // for us and be right at the top of the stack. We don't support multiple
3999 // arguments passed in memory when using inalloca.
4000 if (!Outs.empty() && Outs.back().Flags.isInAlloca()) {
4001 NumBytesToPush = 0;
4002 if (!ArgLocs.back().isMemLoc())
4003 report_fatal_error("cannot use inalloca attribute on a register "
4004 "parameter");
4005 if (ArgLocs.back().getLocMemOffset() != 0)
4006 report_fatal_error("any parameter with the inalloca attribute must be "
4007 "the only memory argument");
4008 } else if (CLI.IsPreallocated) {
4009 assert(ArgLocs.back().isMemLoc() &&((ArgLocs.back().isMemLoc() && "cannot use preallocated attribute on a register "
"parameter") ? static_cast<void> (0) : __assert_fail (
"ArgLocs.back().isMemLoc() && \"cannot use preallocated attribute on a register \" \"parameter\""
, "/build/llvm-toolchain-snapshot-13~++20210405022414+5f57793c4fe4/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 4011, __PRETTY_FUNCTION__))
4010 "cannot use preallocated attribute on a register "((ArgLocs.back().isMemLoc() && "cannot use preallocated attribute on a register "
"parameter") ? static_cast<void> (0) : __assert_fail (
"ArgLocs.back().isMemLoc() && \"cannot use preallocated attribute on a register \" \"parameter\""
, "/build/llvm-toolchain-snapshot-13~++20210405022414+5f57793c4fe4/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 4011, __PRETTY_FUNCTION__))
4011 "parameter")((ArgLocs.back().isMemLoc() && "cannot use preallocated attribute on a register "
"parameter") ? static_cast<void> (0) : __assert_fail (
"ArgLocs.back().isMemLoc() && \"cannot use preallocated attribute on a register \" \"parameter\""
, "/build/llvm-toolchain-snapshot-13~++20210405022414+5f57793c4fe4/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 4011, __PRETTY_FUNCTION__))
;
4012 SmallVector<size_t, 4> PreallocatedOffsets;
4013 for (size_t i = 0; i < CLI.OutVals.size(); ++i) {
4014 if (CLI.CB->paramHasAttr(i, Attribute::Preallocated)) {
4015 PreallocatedOffsets.push_back(ArgLocs[i].getLocMemOffset());
4016 }
4017 }
4018 auto *MFI = DAG.getMachineFunction().getInfo<X86MachineFunctionInfo>();
4019 size_t PreallocatedId = MFI->getPreallocatedIdForCallSite(CLI.CB);
4020 MFI->setPreallocatedStackSize(PreallocatedId, NumBytes);
4021 MFI->setPreallocatedArgOffsets(PreallocatedId, PreallocatedOffsets);
4022 NumBytesToPush = 0;
4023 }
4024
4025 if (!IsSibcall && !IsMustTail)
4026 Chain = DAG.getCALLSEQ_START(Chain, NumBytesToPush,
4027 NumBytes - NumBytesToPush, dl);
4028
4029 SDValue RetAddrFrIdx;
4030 // Load return address for tail calls.
4031 if (isTailCall && FPDiff)
4032 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
4033 Is64Bit, FPDiff, dl);
4034
4035 SmallVector<std::pair<Register, SDValue>, 8> RegsToPass;
4036 SmallVector<SDValue, 8> MemOpChains;
4037 SDValue StackPtr;
4038
4039 // The next loop assumes that the locations are in the same order of the
4040 // input arguments.
4041 assert(isSortedByValueNo(ArgLocs) &&((isSortedByValueNo(ArgLocs) && "Argument Location list must be sorted before lowering"
) ? static_cast<void> (0) : __assert_fail ("isSortedByValueNo(ArgLocs) && \"Argument Location list must be sorted before lowering\""
, "/build/llvm-toolchain-snapshot-13~++20210405022414+5f57793c4fe4/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 4042, __PRETTY_FUNCTION__))
4042 "Argument Location list must be sorted before lowering")((isSortedByValueNo(ArgLocs) && "Argument Location list must be sorted before lowering"
) ? static_cast<void> (0) : __assert_fail ("isSortedByValueNo(ArgLocs) && \"Argument Location list must be sorted before lowering\""
, "/build/llvm-toolchain-snapshot-13~++20210405022414+5f57793c4fe4/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 4042, __PRETTY_FUNCTION__))
;
4043
4044 // Walk the register/memloc assignments, inserting copies/loads. In the case
4045 // of tail call optimization arguments are handle later.
4046 const X86RegisterInfo *RegInfo = Subtarget.getRegisterInfo();
4047 for (unsigned I = 0, OutIndex = 0, E = ArgLocs.size(); I != E;
4048 ++I, ++OutIndex) {
4049 assert(OutIndex < Outs.size() && "Invalid Out index")((OutIndex < Outs.size() && "Invalid Out index") ?
static_cast<void> (0) : __assert_fail ("OutIndex < Outs.size() && \"Invalid Out index\""
, "/build/llvm-toolchain-snapshot-13~++20210405022414+5f57793c4fe4/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 4049, __PRETTY_FUNCTION__))
;
4050 // Skip inalloca/preallocated arguments, they have already been written.
4051 ISD::ArgFlagsTy Flags = Outs[OutIndex].Flags;
4052 if (Flags.isInAlloca() || Flags.isPreallocated())
4053 continue;
4054
4055 CCValAssign &VA = ArgLocs[I];
4056 EVT RegVT = VA.getLocVT();
4057 SDValue Arg = OutVals[OutIndex];
4058 bool isByVal = Flags.isByVal();
4059
4060 // Promote the value if needed.
4061 switch (VA.getLocInfo()) {
4062 default: llvm_unreachable("Unknown loc info!")::llvm::llvm_unreachable_internal("Unknown loc info!", "/build/llvm-toolchain-snapshot-13~++20210405022414+5f57793c4fe4/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 4062)
;
4063 case CCValAssign::Full: break;
4064 case CCValAssign::SExt:
4065 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
4066 break;
4067 case CCValAssign::ZExt:
4068 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
4069 break;
4070 case CCValAssign::AExt:
4071 if (Arg.getValueType().isVector() &&
4072 Arg.getValueType().getVectorElementType() == MVT::i1)
4073 Arg = lowerMasksToReg(Arg, RegVT, dl, DAG);
4074 else if (RegVT.is128BitVector()) {
4075 // Special case: passing MMX values in XMM registers.
4076 Arg = DAG.getBitcast(MVT::i64, Arg);
4077 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
4078 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
4079 } else
4080 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
4081 break;
4082 case CCValAssign::BCvt:
4083 Arg = DAG.getBitcast(RegVT, Arg);
4084 break;
4085 case CCValAssign::Indirect: {
4086 if (isByVal) {
4087 // Memcpy the argument to a temporary stack slot to prevent
4088 // the caller from seeing any modifications the callee may make
4089 // as guaranteed by the `byval` attribute.
4090 int FrameIdx = MF.getFrameInfo().CreateStackObject(
4091 Flags.getByValSize(),
4092 std::max(Align(16), Flags.getNonZeroByValAlign()), false);
4093 SDValue StackSlot =
4094 DAG.getFrameIndex(FrameIdx, getPointerTy(DAG.getDataLayout()));
4095 Chain =
4096 CreateCopyOfByValArgument(Arg, StackSlot, Chain, Flags, DAG, dl);
4097 // From now on treat this as a regular pointer
4098 Arg = StackSlot;
4099 isByVal = false;
4100 } else {
4101 // Store the argument.
4102 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
4103 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
4104 Chain = DAG.getStore(
4105 Chain, dl, Arg, SpillSlot,
4106 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI));
4107 Arg = SpillSlot;
4108 }
4109 break;
4110 }
4111 }
4112
4113 if (VA.needsCustom()) {
4114 assert(VA.getValVT() == MVT::v64i1 &&((VA.getValVT() == MVT::v64i1 && "Currently the only custom case is when we split v64i1 to 2 regs"
) ? static_cast<void> (0) : __assert_fail ("VA.getValVT() == MVT::v64i1 && \"Currently the only custom case is when we split v64i1 to 2 regs\""
, "/build/llvm-toolchain-snapshot-13~++20210405022414+5f57793c4fe4/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 4115, __PRETTY_FUNCTION__))
4115 "Currently the only custom case is when we split v64i1 to 2 regs")((VA.getValVT() == MVT::v64i1 && "Currently the only custom case is when we split v64i1 to 2 regs"
) ? static_cast<void> (0) : __assert_fail ("VA.getValVT() == MVT::v64i1 && \"Currently the only custom case is when we split v64i1 to 2 regs\""
, "/build/llvm-toolchain-snapshot-13~++20210405022414+5f57793c4fe4/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 4115, __PRETTY_FUNCTION__))
;
4116 // Split v64i1 value into two registers
4117 Passv64i1ArgInRegs(dl, DAG, Arg, RegsToPass, VA, ArgLocs[++I], Subtarget);
4118 } else if (VA.isRegLoc()) {
4119 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
4120 const TargetOptions &Options = DAG.getTarget().Options;
4121 if (Options.EmitCallSiteInfo)
4122 CSInfo.emplace_back(VA.getLocReg(), I);
4123 if (isVarArg && IsWin64) {
4124 // Win64 ABI requires argument XMM reg to be copied to the corresponding
4125 // shadow reg if callee is a varargs function.
4126 Register ShadowReg;
4127 switch (VA.getLocReg()) {
4128 case X86::XMM0: ShadowReg = X86::RCX; break;
4129 case X86::XMM1: ShadowReg = X86::RDX; break;
4130 case X86::XMM2: ShadowReg = X86::R8; break;
4131 case X86::XMM3: ShadowReg = X86::R9; break;
4132 }
4133 if (ShadowReg)
4134 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
4135 }
4136 } else if (!IsSibcall && (!isTailCall || isByVal)) {
4137 assert(VA.isMemLoc())((VA.isMemLoc()) ? static_cast<void> (0) : __assert_fail
("VA.isMemLoc()", "/build/llvm-toolchain-snapshot-13~++20210405022414+5f57793c4fe4/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 4137, __PRETTY_FUNCTION__))
;
4138 if (!StackPtr.getNode())
4139 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
4140 getPointerTy(DAG.getDataLayout()));
4141 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
4142 dl, DAG, VA, Flags, isByVal));
4143 }
4144 }
4145
4146 if (!MemOpChains.empty())
4147 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
4148
4149 if (Subtarget.isPICStyleGOT()) {
4150 // ELF / PIC requires GOT in the EBX register before function calls via PLT
4151 // GOT pointer (except regcall).
4152 if (!isTailCall) {
4153 // Indirect call with RegCall calling convertion may use up all the
4154 // general registers, so it is not suitable to bind EBX reister for
4155 // GOT address, just let register allocator handle it.
4156 if (CallConv != CallingConv::X86_RegCall)
4157 RegsToPass.push_back(std::make_pair(
4158 Register(X86::EBX), DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(),
4159 getPointerTy(DAG.getDataLayout()))));
4160 } else {
4161 // If we are tail calling and generating PIC/GOT style code load the
4162 // address of the callee into ECX. The value in ecx is used as target of
4163 // the tail jump. This is done to circumvent the ebx/callee-saved problem
4164 // for tail calls on PIC/GOT architectures. Normally we would just put the
4165 // address of GOT into ebx and then call target@PLT. But for tail calls
4166 // ebx would be restored (since ebx is callee saved) before jumping to the
4167 // target@PLT.
4168
4169 // Note: The actual moving to ECX is done further down.
4170 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
4171 if (G && !G->getGlobal()->hasLocalLinkage() &&
4172 G->getGlobal()->hasDefaultVisibility())
4173 Callee = LowerGlobalAddress(Callee, DAG);
4174 else if (isa<ExternalSymbolSDNode>(Callee))
4175 Callee = LowerExternalSymbol(Callee, DAG);
4176 }
4177 }
4178
4179 if (Is64Bit && isVarArg && !IsWin64 && !IsMustTail) {
4180 // From AMD64 ABI document:
4181 // For calls that may call functions that use varargs or stdargs
4182 // (prototype-less calls or calls to functions containing ellipsis (...) in
4183 // the declaration) %al is used as hidden argument to specify the number
4184 // of SSE registers used. The contents of %al do not need to match exactly
4185 // the number of registers, but must be an ubound on the number of SSE
4186 // registers used and is in the range 0 - 8 inclusive.
4187
4188 // Count the number of XMM registers allocated.
4189 static const MCPhysReg XMMArgRegs[] = {
4190 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
4191 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
4192 };
4193 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs);
4194 assert((Subtarget.hasSSE1() || !NumXMMRegs)(((Subtarget.hasSSE1() || !NumXMMRegs) && "SSE registers cannot be used when SSE is disabled"
) ? static_cast<void> (0) : __assert_fail ("(Subtarget.hasSSE1() || !NumXMMRegs) && \"SSE registers cannot be used when SSE is disabled\""
, "/build/llvm-toolchain-snapshot-13~++20210405022414+5f57793c4fe4/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 4195, __PRETTY_FUNCTION__))
4195 && "SSE registers cannot be used when SSE is disabled")(((Subtarget.hasSSE1() || !NumXMMRegs) && "SSE registers cannot be used when SSE is disabled"
) ? static_cast<void> (0) : __assert_fail ("(Subtarget.hasSSE1() || !NumXMMRegs) && \"SSE registers cannot be used when SSE is disabled\""
, "/build/llvm-toolchain-snapshot-13~++20210405022414+5f57793c4fe4/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 4195, __PRETTY_FUNCTION__))
;
4196 RegsToPass.push_back(std::make_pair(Register(X86::AL),
4197 DAG.getConstant(NumXMMRegs, dl,
4198 MVT::i8)));
4199 }
4200
4201 if (isVarArg && IsMustTail) {
4202 const auto &Forwards = X86Info->getForwardedMustTailRegParms();
4203 for (const auto &F : Forwards) {
4204 SDValue Val = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
4205 RegsToPass.push_back(std::make_pair(F.PReg, Val));
4206 }
4207 }
4208
4209 // For tail calls lower the arguments to the 'real' stack slots. Sibcalls
4210 // don't need this because the eligibility check rejects calls that require
4211 // shuffling arguments passed in memory.
4212 if (!IsSibcall && isTailCall) {
4213 // Force all the incoming stack arguments to be loaded from the stack
4214 // before any new outgoing arguments are stored to the stack, because the
4215 // outgoing stack slots may alias the incoming argument stack slots, and
4216 // the alias isn't otherwise explicit. This is slightly more conservative
4217 // than necessary, because it means that each store effectively depends
4218 // on every argument instead of just those arguments it would clobber.
4219 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
4220
4221 SmallVector<SDValue, 8> MemOpChains2;
4222 SDValue FIN;
4223 int FI = 0;
4224 for (unsigned I = 0, OutsIndex = 0, E = ArgLocs.size(); I != E;
4225 ++I, ++OutsIndex) {
4226 CCValAssign &VA = ArgLocs[I];
4227
4228 if (VA.isRegLoc()) {
4229 if (VA.needsCustom()) {
4230 assert((CallConv == CallingConv::X86_RegCall) &&(((CallConv == CallingConv::X86_RegCall) && "Expecting custom case only in regcall calling convention"
) ? static_cast<void> (0) : __assert_fail ("(CallConv == CallingConv::X86_RegCall) && \"Expecting custom case only in regcall calling convention\""
, "/build/llvm-toolchain-snapshot-13~++20210405022414+5f57793c4fe4/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 4231, __PRETTY_FUNCTION__))
4231 "Expecting custom case only in regcall calling convention")(((CallConv == CallingConv::X86_RegCall) && "Expecting custom case only in regcall calling convention"
) ? static_cast<void> (0) : __assert_fail ("(CallConv == CallingConv::X86_RegCall) && \"Expecting custom case only in regcall calling convention\""
, "/build/llvm-toolchain-snapshot-13~++20210405022414+5f57793c4fe4/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 4231, __PRETTY_FUNCTION__))
;
4232 // This means that we are in special case where one argument was
4233 // passed through two register locations - Skip the next location
4234 ++I;
4235 }
4236
4237 continue;
4238 }
4239
4240 assert(VA.isMemLoc())((VA.isMemLoc()) ? static_cast<void> (0) : __assert_fail
("VA.isMemLoc()", "/build/llvm-toolchain-snapshot-13~++20210405022414+5f57793c4fe4/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 4240, __PRETTY_FUNCTION__))
;
4241 SDValue Arg = OutVals[OutsIndex];
4242 ISD::ArgFlagsTy Flags = Outs[OutsIndex].Flags;
4243 // Skip inalloca/preallocated arguments. They don't require any work.
4244 if (Flags.isInAlloca() || Flags.isPreallocated())
4245 continue;
4246 // Create frame index.
4247 int32_t Offset = VA.getLocMemOffset()+FPDiff;
4248 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
4249 FI = MF.getFrameInfo().CreateFixedObject(OpSize, Offset, true);
4250 FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
4251
4252 if (Flags.isByVal()) {
4253 // Copy relative to framepointer.
4254 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset(), dl);
4255 if (!StackPtr.getNode())
4256 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
4257 getPointerTy(DAG.getDataLayout()));
4258 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(DAG.getDataLayout()),
4259 StackPtr, Source);
4260
4261 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
4262 ArgChain,
4263 Flags, DAG, dl));
4264 } else {
4265 // Store relative to framepointer.
4266 MemOpChains2.push_back(DAG.getStore(
4267 ArgChain, dl, Arg, FIN,
4268 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI)));
4269 }
4270 }
4271
4272 if (!MemOpChains2.empty())
4273 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
4274
4275 // Store the return address to the appropriate stack slot.
4276 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx,
4277 getPointerTy(DAG.getDataLayout()),
4278 RegInfo->getSlotSize(), FPDiff, dl);
4279 }
4280
4281 // Build a sequence of copy-to-reg nodes chained together with token chain
4282 // and flag operands which copy the outgoing args into registers.
4283 SDValue InFlag;
4284 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
4285 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
4286 RegsToPass[i].second, InFlag);
4287 InFlag = Chain.getValue(1);
4288 }
4289
4290 if (DAG.getTarget().getCodeModel() == CodeModel::Large) {
4291 assert(Is64Bit && "Large code model is only legal in 64-bit mode.")((Is64Bit && "Large code model is only legal in 64-bit mode."
) ? static_cast<void> (0) : __assert_fail ("Is64Bit && \"Large code model is only legal in 64-bit mode.\""
, "/build/llvm-toolchain-snapshot-13~++20210405022414+5f57793c4fe4/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 4291, __PRETTY_FUNCTION__))
;
4292 // In the 64-bit large code model, we have to make all calls
4293 // through a register, since the call instruction's 32-bit
4294 // pc-relative offset may not be large enough to hold the whole
4295 // address.
4296 } else if (Callee->getOpcode() == ISD::GlobalAddress ||
4297 Callee->getOpcode() == ISD::ExternalSymbol) {
4298 // Lower direct calls to global addresses and external symbols. Setting
4299 // ForCall to true here has the effect of removing WrapperRIP when possible
4300 // to allow direct calls to be selected without first materializing the
4301 // address into a register.
4302 Callee = LowerGlobalOrExternal(Callee, DAG, /*ForCall=*/true);
4303 } else if (Subtarget.isTarget64BitILP32() &&
4304 Callee->getValueType(0) == MVT::i32) {
4305 // Zero-extend the 32-bit Callee address into a 64-bit according to x32 ABI
4306 Callee = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Callee);
4307 }
4308
4309 // Returns a chain & a flag for retval copy to use.
4310 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
4311 SmallVector<SDValue, 8> Ops;
4312
4313 if (!IsSibcall && isTailCall && !IsMustTail) {
4314 Chain = DAG.getCALLSEQ_END(Chain,
4315 DAG.getIntPtrConstant(NumBytesToPop, dl, true),
4316 DAG.getIntPtrConstant(0, dl, true), InFlag, dl);
4317 InFlag = Chain.getValue(1);
4318 }
4319
4320 Ops.push_back(Chain);
4321 Ops.push_back(Callee);
4322
4323 if (isTailCall)
4324 Ops.push_back(DAG.getTargetConstant(FPDiff, dl, MVT::i32));
4325
4326 // Add argument registers to the end of the list so that they are known live
4327 // into the call.
4328 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
4329 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
4330 RegsToPass[i].second.getValueType()));
4331
4332 // Add a register mask operand representing the call-preserved registers.
4333 const uint32_t *Mask = [&]() {
4334 auto AdaptedCC = CallConv;
4335 // If HasNCSR is asserted (attribute NoCallerSavedRegisters exists),
4336 // use X86_INTR calling convention because it has the same CSR mask
4337 // (same preserved registers).
4338 if (HasNCSR)
4339 AdaptedCC = (CallingConv::ID)CallingConv::X86_INTR;
4340 // If NoCalleeSavedRegisters is requested, than use GHC since it happens
4341 // to use the CSR_NoRegs_RegMask.
4342 if (CB && CB->hasFnAttr("no_callee_saved_registers"))
4343 AdaptedCC = (CallingConv::ID)CallingConv::GHC;
4344 return RegInfo->getCallPreservedMask(MF, AdaptedCC);
4345 }();
4346 assert(Mask && "Missing call preserved mask for calling convention")((Mask && "Missing call preserved mask for calling convention"
) ? static_cast<void> (0) : __assert_fail ("Mask && \"Missing call preserved mask for calling convention\""
, "/build/llvm-toolchain-snapshot-13~++20210405022414+5f57793c4fe4/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 4346, __PRETTY_FUNCTION__))
;
4347
4348 // If this is an invoke in a 32-bit function using a funclet-based
4349 // personality, assume the function clobbers all registers. If an exception
4350 // is thrown, the runtime will not restore CSRs.
4351 // FIXME: Model this more precisely so that we can register allocate across
4352 // the normal edge and spill and fill across the exceptional edge.
4353 if (!Is64Bit && CLI.CB && isa<InvokeInst>(CLI.CB)) {
4354 const Function &CallerFn = MF.getFunction();
4355 EHPersonality Pers =
4356 CallerFn.hasPersonalityFn()
4357 ? classifyEHPersonality(CallerFn.getPersonalityFn())
4358 : EHPersonality::Unknown;
4359 if (isFuncletEHPersonality(Pers))
4360 Mask = RegInfo->getNoPreservedMask();
4361 }
4362
4363 // Define a new register mask from the existing mask.
4364 uint32_t *RegMask = nullptr;
4365
4366 // In some calling conventions we need to remove the used physical registers
4367 // from the reg mask.
4368 if (CallConv == CallingConv::X86_RegCall || HasNCSR) {
4369 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
4370
4371 // Allocate a new Reg Mask and copy Mask.
4372 RegMask = MF.allocateRegMask();
4373 unsigned RegMaskSize = MachineOperand::getRegMaskSize(TRI->getNumRegs());
4374 memcpy(RegMask, Mask, sizeof(RegMask[0]) * RegMaskSize);
4375
4376 // Make sure all sub registers of the argument registers are reset
4377 // in the RegMask.
4378 for (auto const &RegPair : RegsToPass)
4379 for (MCSubRegIterator SubRegs(RegPair.first, TRI, /*IncludeSelf=*/true);
4380 SubRegs.isValid(); ++SubRegs)
4381 RegMask[*SubRegs / 32] &= ~(1u << (*SubRegs % 32));
4382
4383 // Create the RegMask Operand according to our updated mask.
4384 Ops.push_back(DAG.getRegisterMask(RegMask));
4385 } else {
4386 // Create the RegMask Operand according to the static mask.
4387 Ops.push_back(DAG.getRegisterMask(Mask));
4388 }
4389
4390 if (InFlag.getNode())
4391 Ops.push_back(InFlag);
4392
4393 if (isTailCall) {
4394 // We used to do:
4395 //// If this is the first return lowered for this function, add the regs
4396 //// to the liveout set for the function.
4397 // This isn't right, although it's probably harmless on x86; liveouts
4398 // should be computed from returns not tail calls. Consider a void
4399 // function making a tail call to a function returning int.
4400 MF.getFrameInfo().setHasTailCall();
4401 SDValue Ret = DAG.getNode(X86ISD::TC_RETURN, dl, NodeTys, Ops);
4402 DAG.addCallSiteInfo(Ret.getNode(), std::move(CSInfo));
4403 return Ret;
4404 }
4405
4406 if (HasNoCfCheck && IsCFProtectionSupported && IsIndirectCall) {
4407 Chain = DAG.getNode(X86ISD::NT_CALL, dl, NodeTys, Ops);
4408 } else {
4409 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, Ops);
4410 }
4411 InFlag = Chain.getValue(1);
4412 DAG.addNoMergeSiteInfo(Chain.getNode(), CLI.NoMerge);
4413 DAG.addCallSiteInfo(Chain.getNode(), std::move(CSInfo));
4414
4415 // Save heapallocsite metadata.
4416 if (CLI.CB)
4417 if (MDNode *HeapAlloc = CLI.CB->getMetadata("heapallocsite"))
4418 DAG.addHeapAllocSite(Chain.getNode(), HeapAlloc);
4419
4420 // Create the CALLSEQ_END node.
4421 unsigned NumBytesForCalleeToPop;
4422 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
4423 DAG.getTarget().Options.GuaranteedTailCallOpt))
4424 NumBytesForCalleeToPop = NumBytes; // Callee pops everything
4425 else if (!Is64Bit && !canGuaranteeTCO(CallConv) &&
4426 !Subtarget.getTargetTriple().isOSMSVCRT() &&
4427 SR == StackStructReturn)
4428 // If this is a call to a struct-return function, the callee
4429 // pops the hidden struct pointer, so we have to push it back.
4430 // This is common for Darwin/X86, Linux & Mingw32 targets.
4431 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
4432 NumBytesForCalleeToPop = 4;
4433 else
4434 NumBytesForCalleeToPop = 0; // Callee pops nothing.
4435
4436 // Returns a flag for retval copy to use.
4437 if (!IsSibcall) {
4438 Chain = DAG.getCALLSEQ_END(Chain,
4439 DAG.getIntPtrConstant(NumBytesToPop, dl, true),
4440 DAG.getIntPtrConstant(NumBytesForCalleeToPop, dl,
4441 true),
4442 InFlag, dl);
4443 InFlag = Chain.getValue(1);
4444 }
4445
4446 // Handle result values, copying them out of physregs into vregs that we
4447 // return.
4448 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins, dl, DAG,
4449 InVals, RegMask);
4450}
4451
4452//===----------------------------------------------------------------------===//
4453// Fast Calling Convention (tail call) implementation
4454//===----------------------------------------------------------------------===//
4455
4456// Like std call, callee cleans arguments, convention except that ECX is
4457// reserved for storing the tail called function address. Only 2 registers are
4458// free for argument passing (inreg). Tail call optimization is performed
4459// provided:
4460// * tailcallopt is enabled
4461// * caller/callee are fastcc
4462// On X86_64 architecture with GOT-style position independent code only local
4463// (within module) calls are supported at the moment.
4464// To keep the stack aligned according to platform abi the function
4465// GetAlignedArgumentStackSize ensures that argument delta is always multiples
4466// of stack alignment. (Dynamic linkers need this - Darwin's dyld for example)
4467// If a tail called function callee has more arguments than the caller the
4468// caller needs to make sure that there is room to move the RETADDR to. This is
4469// achieved by reserving an area the size of the argument delta right after the
4470// original RETADDR, but before the saved framepointer or the spilled registers
4471// e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
4472// stack layout:
4473// arg1
4474// arg2
4475// RETADDR
4476// [ new RETADDR
4477// move area ]
4478// (possible EBP)
4479// ESI
4480// EDI
4481// local1 ..
4482
4483/// Make the stack size align e.g 16n + 12 aligned for a 16-byte align
4484/// requirement.
4485unsigned
4486X86TargetLowering::GetAlignedArgumentStackSize(const unsigned StackSize,
4487 SelectionDAG &DAG) const {
4488 const Align StackAlignment = Subtarget.getFrameLowering()->getStackAlign();
4489 const uint64_t SlotSize = Subtarget.getRegisterInfo()->getSlotSize();
4490 assert(StackSize % SlotSize == 0 &&((StackSize % SlotSize == 0 && "StackSize must be a multiple of SlotSize"
) ? static_cast<void> (0) : __assert_fail ("StackSize % SlotSize == 0 && \"StackSize must be a multiple of SlotSize\""
, "/build/llvm-toolchain-snapshot-13~++20210405022414+5f57793c4fe4/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 4491, __PRETTY_FUNCTION__))
4491 "StackSize must be a multiple of SlotSize")((StackSize % SlotSize == 0 && "StackSize must be a multiple of SlotSize"
) ? static_cast<void> (0) : __assert_fail ("StackSize % SlotSize == 0 && \"StackSize must be a multiple of SlotSize\""
, "/build/llvm-toolchain-snapshot-13~++20210405022414+5f57793c4fe4/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 4491, __PRETTY_FUNCTION__))
;
4492 return alignTo(StackSize + SlotSize, StackAlignment) - SlotSize;
4493}
4494
4495/// Return true if the given stack call argument is already available in the
4496/// same position (relatively) of the caller's incoming argument stack.
4497static
4498bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
4499 MachineFrameInfo &MFI, const MachineRegisterInfo *MRI,
4500 const X86InstrInfo *TII, const CCValAssign &VA) {
4501 unsigned Bytes = Arg.getValueSizeInBits() / 8;
4502
4503 for (;;) {
4504 // Look through nodes that don't alter the bits of the incoming value.
4505 unsigned Op = Arg.getOpcode();
4506 if (Op == ISD::ZERO_EXTEND || Op == ISD::ANY_EXTEND || Op == ISD::BITCAST) {
4507 Arg = Arg.getOperand(0);
4508 continue;
4509 }
4510 if (Op == ISD::TRUNCATE) {
4511 const SDValue &TruncInput = Arg.getOperand(0);
4512 if (TruncInput.getOpcode() == ISD::AssertZext &&
4513 cast<VTSDNode>(TruncInput.getOperand(1))->getVT() ==
4514 Arg.getValueType()) {
4515 Arg = TruncInput.getOperand(0);
4516 continue;
4517 }
4518 }
4519 break;
4520 }
4521
4522 int FI = INT_MAX2147483647;
4523 if (Arg.getOpcode() == ISD::CopyFromReg) {
4524 Register VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
4525 if (!VR.isVirtual())
4526 return false;
4527 MachineInstr *Def = MRI->getVRegDef(VR);
4528 if (!Def)
4529 return false;
4530 if (!Flags.isByVal()) {
4531 if (!TII->isLoadFromStackSlot(*Def, FI))
4532 return false;
4533 } else {
4534 unsigned Opcode = Def->getOpcode();
4535 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r ||
4536 Opcode == X86::LEA64_32r) &&
4537 Def->getOperand(1).isFI()) {
4538 FI = Def->getOperand(1).getIndex();
4539 Bytes = Flags.getByValSize();
4540 } else
4541 return false;
4542 }
4543 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
4544 if (Flags.isByVal())
4545 // ByVal argument is passed in as a pointer but it's now being
4546 // dereferenced. e.g.
4547 // define @foo(%struct.X* %A) {
4548 // tail call @bar(%struct.X* byval %A)
4549 // }
4550 return false;
4551 SDValue Ptr = Ld->getBasePtr();
4552 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
4553 if (!FINode)
4554 return false;
4555 FI = FINode->getIndex();
4556 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
4557 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
4558 FI = FINode->getIndex();
4559 Bytes = Flags.getByValSize();
4560 } else
4561 return false;
4562
4563 assert(FI != INT_MAX)((FI != 2147483647) ? static_cast<void> (0) : __assert_fail
("FI != INT_MAX", "/build/llvm-toolchain-snapshot-13~++20210405022414+5f57793c4fe4/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 4563, __PRETTY_FUNCTION__))
;
4564 if (!MFI.isFixedObjectIndex(FI))
4565 return false;
4566
4567 if (Offset != MFI.getObjectOffset(FI))
4568 return false;
4569
4570 // If this is not byval, check that the argument stack object is immutable.
4571 // inalloca and argument copy elision can create mutable argument stack
4572 // objects. Byval objects can be mutated, but a byval call intends to pass the
4573 // mutated memory.
4574 if (!Flags.isByVal() && !MFI.isImmutableObjectIndex(FI))
4575 return false;
4576
4577 if (VA.getLocVT().getFixedSizeInBits() >
4578 Arg.getValueSizeInBits().getFixedSize()) {
4579 // If the argument location is wider than the argument type, check that any
4580 // extension flags match.
4581 if (Flags.isZExt() != MFI.isObjectZExt(FI) ||
4582 Flags.isSExt() != MFI.isObjectSExt(FI)) {
4583 return false;
4584 }
4585 }
4586
4587 return Bytes == MFI.getObjectSize(FI);
4588}
4589
4590/// Check whether the call is eligible for tail call optimization. Targets
4591/// that want to do tail call optimization should implement this function.
4592bool X86TargetLowering::IsEligibleForTailCallOptimization(
4593 SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg,
4594 bool isCalleeStructRet, bool isCallerStructRet, Type *RetTy,
4595 const SmallVectorImpl<ISD::OutputArg> &Outs,
4596 const SmallVectorImpl<SDValue> &OutVals,
4597 const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG) const {
4598 if (!mayTailCallThisCC(CalleeCC))
4599 return false;
4600
4601 // If -tailcallopt is specified, make fastcc functions tail-callable.
4602 MachineFunction &MF = DAG.getMachineFunction();
4603 const Function &CallerF = MF.getFunction();
4604
4605 // If the function return type is x86_fp80 and the callee return type is not,
4606 // then the FP_EXTEND of the call result is not a nop. It's not safe to
4607 // perform a tailcall optimization here.
4608 if (CallerF.getReturnType()->isX86_FP80Ty() && !RetTy->isX86_FP80Ty())
4609 return false;
4610
4611 CallingConv::ID CallerCC = CallerF.getCallingConv();
4612 bool CCMatch = CallerCC == CalleeCC;
4613 bool IsCalleeWin64 = Subtarget.isCallingConvWin64(CalleeCC);
4614 bool IsCallerWin64 = Subtarget.isCallingConvWin64(CallerCC);
4615 bool IsGuaranteeTCO = DAG.getTarget().Options.GuaranteedTailCallOpt ||
4616 CalleeCC == CallingConv::Tail;
4617
4618 // Win64 functions have extra shadow space for argument homing. Don't do the
4619 // sibcall if the caller and callee have mismatched expectations for this
4620 // space.
4621 if (IsCalleeWin64 != IsCallerWin64)
4622 return false;
4623
4624 if (IsGuaranteeTCO) {
4625 if (canGuaranteeTCO(CalleeCC) && CCMatch)
4626 return true;
4627 return false;
4628 }
4629
4630 // Look for obvious safe cases to perform tail call optimization that do not
4631 // require ABI changes. This is what gcc calls sibcall.
4632
4633 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
4634 // emit a special epilogue.
4635 const X86RegisterInfo *RegInfo = Subtarget.getRegisterInfo();
4636 if (RegInfo->hasStackRealignment(MF))
4637 return false;
4638
4639 // Also avoid sibcall optimization if either caller or callee uses struct
4640 // return semantics.
4641 if (isCalleeStructRet || isCallerStructRet)
4642 return false;
4643
4644 // Do not sibcall optimize vararg calls unless all arguments are passed via
4645 // registers.
4646 LLVMContext &C = *DAG.getContext();
4647 if (isVarArg && !Outs.empty()) {
4648 // Optimizing for varargs on Win64 is unlikely to be safe without
4649 // additional testing.
4650 if (IsCalleeWin64 || IsCallerWin64)
4651 return false;
4652
4653 SmallVector<CCValAssign, 16> ArgLocs;
4654 CCState CCInfo(CalleeCC, isVarArg, MF, ArgLocs, C);
4655
4656 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
4657 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
4658 if (!ArgLocs[i].isRegLoc())
4659 return false;
4660 }
4661
4662 // If the call result is in ST0 / ST1, it needs to be popped off the x87
4663 // stack. Therefore, if it's not used by the call it is not safe to optimize
4664 // this into a sibcall.
4665 bool Unused = false;
4666 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
4667 if (!Ins[i].Used) {
4668 Unused = true;
4669 break;
4670 }
4671 }
4672 if (Unused) {
4673 SmallVector<CCValAssign, 16> RVLocs;
4674 CCState CCInfo(CalleeCC, false, MF, RVLocs, C);
4675 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
4676 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
4677 CCValAssign &VA = RVLocs[i];
4678 if (VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1)
4679 return false;
4680 }
4681 }
4682
4683 // Check that the call results are passed in the same way.
4684 if (!CCState::resultsCompatible(CalleeCC, CallerCC, MF, C, Ins,
4685 RetCC_X86, RetCC_X86))
4686 return false;
4687 // The callee has to preserve all registers the caller needs to preserve.
4688 const X86RegisterInfo *TRI = Subtarget.getRegisterInfo();
4689 const uint32_t *CallerPreserved = TRI->getCallPreservedMask(MF, CallerCC);
4690 if (!CCMatch) {
4691 const uint32_t *CalleePreserved = TRI->getCallPreservedMask(MF, CalleeCC);
4692 if (!TRI->regmaskSubsetEqual(CallerPreserved, CalleePreserved))
4693 return false;
4694 }
4695
4696 unsigned StackArgsSize = 0;
4697
4698 // If the callee takes no arguments then go on to check the results of the
4699 // call.
4700 if (!Outs.empty()) {
4701 // Check if stack adjustment is needed. For now, do not do this if any
4702 // argument is passed on the stack.
4703 SmallVector<CCValAssign, 16> ArgLocs;
4704 CCState CCInfo(CalleeCC, isVarArg, MF, ArgLocs, C);
4705
4706 // Allocate shadow area for Win64
4707 if (IsCalleeWin64)
4708 CCInfo.AllocateStack(32, Align(8));
4709
4710 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
4711 StackArgsSize = CCInfo.getNextStackOffset();
4712
4713 if (CCInfo.getNextStackOffset()) {
4714 // Check if the arguments are already laid out in the right way as
4715 // the caller's fixed stack objects.
4716 MachineFrameInfo &MFI = MF.getFrameInfo();
4717 const MachineRegisterInfo *MRI = &MF.getRegInfo();
4718 const X86InstrInfo *TII = Subtarget.getInstrInfo();
4719 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
4720 CCValAssign &VA = ArgLocs[i];
4721 SDValue Arg = OutVals[i];
4722 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4723 if (VA.getLocInfo() == CCValAssign::Indirect)
4724 return false;
4725 if (!VA.isRegLoc()) {
4726 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
4727 MFI, MRI, TII, VA))
4728 return false;
4729 }
4730 }
4731 }
4732
4733 bool PositionIndependent = isPositionIndependent();
4734 // If the tailcall address may be in a register, then make sure it's
4735 // possible to register allocate for it. In 32-bit, the call address can
4736 // only target EAX, EDX, or ECX since the tail call must be scheduled after
4737 // callee-saved registers are restored. These happen to be the same
4738 // registers used to pass 'inreg' arguments so watch out for those.
4739 if (!Subtarget.is64Bit() && ((!isa<GlobalAddressSDNode>(Callee) &&
4740 !isa<ExternalSymbolSDNode>(Callee)) ||
4741 PositionIndependent)) {
4742 unsigned NumInRegs = 0;
4743 // In PIC we need an extra register to formulate the address computation
4744 // for the callee.
4745 unsigned MaxInRegs = PositionIndependent ? 2 : 3;
4746
4747 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
4748 CCValAssign &VA = ArgLocs[i];
4749 if (!VA.isRegLoc())
4750 continue;
4751 Register Reg = VA.getLocReg();
4752 switch (Reg) {
4753 default: break;
4754 case X86::EAX: case X86::EDX: case X86::ECX:
4755 if (++NumInRegs == MaxInRegs)
4756 return false;
4757 break;
4758 }
4759 }
4760 }
4761
4762 const MachineRegisterInfo &MRI = MF.getRegInfo();
4763 if (!parametersInCSRMatch(MRI, CallerPreserved, ArgLocs, OutVals))
4764 return false;
4765 }
4766
4767 bool CalleeWillPop =
4768 X86::isCalleePop(CalleeCC, Subtarget.is64Bit(), isVarArg,
4769 MF.getTarget().Options.GuaranteedTailCallOpt);
4770
4771 if (unsigned BytesToPop =
4772 MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn()) {
4773 // If we have bytes to pop, the callee must pop them.
4774 bool CalleePopMatches = CalleeWillPop && BytesToPop == StackArgsSize;
4775 if (!CalleePopMatches)
4776 return false;
4777 } else if (CalleeWillPop && StackArgsSize > 0) {
4778 // If we don't have bytes to pop, make sure the callee doesn't pop any.
4779 return false;
4780 }
4781
4782 return true;
4783}
4784
4785FastISel *
4786X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
4787 const TargetLibraryInfo *libInfo) const {
4788 return X86::createFastISel(funcInfo, libInfo);
4789}
4790
4791//===----------------------------------------------------------------------===//
4792// Other Lowering Hooks
4793//===----------------------------------------------------------------------===//
4794
4795static bool MayFoldLoad(SDValue Op) {
4796 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
4797}
4798
4799static bool MayFoldIntoStore(SDValue Op) {
4800 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
4801}
4802
4803static bool MayFoldIntoZeroExtend(SDValue Op) {
4804 if (Op.hasOneUse()) {
4805 unsigned Opcode = Op.getNode()->use_begin()->getOpcode();
4806 return (ISD::ZERO_EXTEND == Opcode);
4807 }
4808 return false;
4809}
4810
4811static bool isTargetShuffle(unsigned Opcode) {
4812 switch(Opcode) {
4813 default: return false;
4814 case X86ISD::BLENDI:
4815 case X86ISD::PSHUFB:
4816 case X86ISD::PSHUFD:
4817 case X86ISD::PSHUFHW:
4818 case X86ISD::PSHUFLW:
4819 case X86ISD::SHUFP:
4820 case X86ISD::INSERTPS:
4821 case X86ISD::EXTRQI:
4822 case X86ISD::INSERTQI:
4823 case X86ISD::VALIGN:
4824 case X86ISD::PALIGNR:
4825 case X86ISD::VSHLDQ:
4826 case X86ISD::VSRLDQ:
4827 case X86ISD::MOVLHPS:
4828 case X86ISD::MOVHLPS:
4829 case X86ISD::MOVSHDUP:
4830 case X86ISD::MOVSLDUP:
4831 case X86ISD::MOVDDUP:
4832 case X86ISD::MOVSS:
4833 case X86ISD::MOVSD:
4834 case X86ISD::UNPCKL:
4835 case X86ISD::UNPCKH:
4836 case X86ISD::VBROADCAST:
4837 case X86ISD::VPERMILPI:
4838 case X86ISD::VPERMILPV:
4839 case X86ISD::VPERM2X128:
4840 case X86ISD::SHUF128:
4841 case X86ISD::VPERMIL2:
4842 case X86ISD::VPERMI:
4843 case X86ISD::VPPERM:
4844 case X86ISD::VPERMV:
4845 case X86ISD::VPERMV3:
4846 case X86ISD::VZEXT_MOVL:
4847 return true;
4848 }
4849}
4850
4851static bool isTargetShuffleVariableMask(unsigned Opcode) {
4852 switch (Opcode) {
4853 default: return false;
4854 // Target Shuffles.
4855 case X86ISD::PSHUFB:
4856 case X86ISD::VPERMILPV:
4857 case X86ISD::VPERMIL2:
4858 case X86ISD::VPPERM:
4859 case X86ISD::VPERMV:
4860 case X86ISD::VPERMV3:
4861 return true;
4862 // 'Faux' Target Shuffles.
4863 case ISD::OR:
4864 case ISD::AND:
4865 case X86ISD::ANDNP:
4866 return true;
4867 }
4868}
4869
4870static bool isTargetShuffleSplat(SDValue Op) {
4871 unsigned Opcode = Op.getOpcode();
4872 if (Opcode == ISD::EXTRACT_SUBVECTOR)
4873 return isTargetShuffleSplat(Op.getOperand(0));
4874 return Opcode == X86ISD::VBROADCAST || Opcode == X86ISD::VBROADCAST_LOAD;
4875}
4876
4877SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
4878 MachineFunction &MF = DAG.getMachineFunction();
4879 const X86RegisterInfo *RegInfo = Subtarget.getRegisterInfo();
4880 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
4881 int ReturnAddrIndex = FuncInfo->getRAIndex();
4882
4883 if (ReturnAddrIndex == 0) {
4884 // Set up a frame object for the return address.
4885 unsigned SlotSize = RegInfo->getSlotSize();
4886 ReturnAddrIndex = MF.getFrameInfo().CreateFixedObject(SlotSize,
4887 -(int64_t)SlotSize,
4888 false);
4889 FuncInfo->setRAIndex(ReturnAddrIndex);
4890 }
4891
4892 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy(DAG.getDataLayout()));
4893}
4894
4895bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
4896 bool hasSymbolicDisplacement) {
4897 // Offset should fit into 32 bit immediate field.
4898 if (!isInt<32>(Offset))
4899 return false;
4900
4901 // If we don't have a symbolic displacement - we don't have any extra
4902 // restrictions.
4903 if (!hasSymbolicDisplacement)
4904 return true;
4905
4906 // FIXME: Some tweaks might be needed for medium code model.
4907 if (M != CodeModel::Small && M != CodeModel::Kernel)
4908 return false;
4909
4910 // For small code model we assume that latest object is 16MB before end of 31
4911 // bits boundary. We may also accept pretty large negative constants knowing
4912 // that all objects are in the positive half of address space.
4913 if (M == CodeModel::Small && Offset < 16*1024*1024)
4914 return true;
4915
4916 // For kernel code model we know that all object resist in the negative half
4917 // of 32bits address space. We may not accept negative offsets, since they may
4918 // be just off and we may accept pretty large positive ones.
4919 if (M == CodeModel::Kernel && Offset >= 0)
4920 return true;
4921
4922 return false;
4923}
4924
4925/// Determines whether the callee is required to pop its own arguments.
4926/// Callee pop is necessary to support tail calls.
4927bool X86::isCalleePop(CallingConv::ID CallingConv,
4928 bool is64Bit, bool IsVarArg, bool GuaranteeTCO) {
4929 // If GuaranteeTCO is true, we force some calls to be callee pop so that we
4930 // can guarantee TCO.
4931 if (!IsVarArg && shouldGuaranteeTCO(CallingConv, GuaranteeTCO))
4932 return true;
4933
4934 switch (CallingConv) {
4935 default:
4936 return false;
4937 case CallingConv::X86_StdCall:
4938 case CallingConv::X86_FastCall:
4939 case CallingConv::X86_ThisCall:
4940 case CallingConv::X86_VectorCall:
4941 return !is64Bit;
4942 }
4943}
4944
4945/// Return true if the condition is an signed comparison operation.
4946static bool isX86CCSigned(unsigned X86CC) {
4947 switch (X86CC) {
4948 default:
4949 llvm_unreachable("Invalid integer condition!")::llvm::llvm_unreachable_internal("Invalid integer condition!"
, "/build/llvm-toolchain-snapshot-13~++20210405022414+5f57793c4fe4/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 4949)
;
4950 case X86::COND_E:
4951 case X86::COND_NE:
4952 case X86::COND_B:
4953 case X86::COND_A:
4954 case X86::COND_BE:
4955 case X86::COND_AE:
4956 return false;
4957 case X86::COND_G:
4958 case X86::COND_GE:
4959 case X86::COND_L:
4960 case X86::COND_LE:
4961 return true;
4962 }
4963}
4964
4965static X86::CondCode TranslateIntegerX86CC(ISD::CondCode SetCCOpcode) {
4966 switch (SetCCOpcode) {
4967 default: llvm_unreachable("Invalid integer condition!")::llvm::llvm_unreachable_internal("Invalid integer condition!"
, "/build/llvm-toolchain-snapshot-13~++20210405022414+5f57793c4fe4/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 4967)
;
4968 case ISD::SETEQ: return X86::COND_E;
4969 case ISD::SETGT: return X86::COND_G;
4970 case ISD::SETGE: return X86::COND_GE;
4971 case ISD::SETLT: return X86::COND_L;
4972 case ISD::SETLE: return X86::COND_LE;
4973 case ISD::SETNE: return X86::COND_NE;
4974 case ISD::SETULT: return X86::COND_B;
4975 case ISD::SETUGT: return X86::COND_A;
4976 case ISD::SETULE: return X86::COND_BE;
4977 case ISD::SETUGE: return X86::COND_AE;
4978 }
4979}
4980
4981/// Do a one-to-one translation of a ISD::CondCode to the X86-specific
4982/// condition code, returning the condition code and the LHS/RHS of the
4983/// comparison to make.
4984static X86::CondCode TranslateX86CC(ISD::CondCode SetCCOpcode, const SDLoc &DL,
4985 bool isFP, SDValue &LHS, SDValue &RHS,
4986 SelectionDAG &DAG) {
4987 if (!isFP) {
4988 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
4989 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
4990 // X > -1 -> X == 0, jump !sign.
4991 RHS = DAG.getConstant(0, DL, RHS.getValueType());
4992 return X86::COND_NS;
4993 }
4994 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
4995 // X < 0 -> X == 0, jump on sign.
4996 return X86::COND_S;
4997 }
4998 if (SetCCOpcode == ISD::SETGE && RHSC->isNullValue()) {
4999 // X >= 0 -> X == 0, jump on !sign.
5000 return X86::COND_NS;
5001 }
5002 if (SetCCOpcode == ISD::SETLT && RHSC->isOne()) {
5003 // X < 1 -> X <= 0
5004 RHS = DAG.getConstant(0, DL, RHS.getValueType());
5005 return X86::COND_LE;
5006 }
5007 }
5008
5009 return TranslateIntegerX86CC(SetCCOpcode);
5010 }
5011
5012 // First determine if it is required or is profitable to flip the operands.
5013
5014 // If LHS is a foldable load, but RHS is not, flip the condition.
5015 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
5016 !ISD::isNON_EXTLoad(RHS.getNode())) {
5017 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
5018 std::swap(LHS, RHS);
5019 }
5020
5021 switch (SetCCOpcode) {
5022 default: break;
5023 case ISD::SETOLT:
5024 case ISD::SETOLE:
5025 case ISD::SETUGT:
5026 case ISD::SETUGE:
5027 std::swap(LHS, RHS);
5028 break;
5029 }
5030
5031 // On a floating point condition, the flags are set as follows:
5032 // ZF PF CF op
5033 // 0 | 0 | 0 | X > Y
5034 // 0 | 0 | 1 | X < Y
5035 // 1 | 0 | 0 | X == Y
5036 // 1 | 1 | 1 | unordered
5037 switch (SetCCOpcode) {
5038 default: llvm_unreachable("Condcode should be pre-legalized away")::llvm::llvm_unreachable_internal("Condcode should be pre-legalized away"
, "/build/llvm-toolchain-snapshot-13~++20210405022414+5f57793c4fe4/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 5038)
;
5039 case ISD::SETUEQ:
5040 case ISD::SETEQ: return X86::COND_E;
5041 case ISD::SETOLT: // flipped
5042 case ISD::SETOGT:
5043 case ISD::SETGT: return X86::COND_A;
5044 case ISD::SETOLE: // flipped
5045 case ISD::SETOGE:
5046 case ISD::SETGE: return X86::COND_AE;
5047 case ISD::SETUGT: // flipped
5048 case ISD::SETULT:
5049 case ISD::SETLT: return X86::COND_B;
5050 case ISD::SETUGE: // flipped
5051 case ISD::SETULE:
5052 case ISD::SETLE: return X86::COND_BE;
5053 case ISD::SETONE:
5054 case ISD::SETNE: return X86::COND_NE;
5055 case ISD::SETUO: return X86::COND_P;
5056 case ISD::SETO: return X86::COND_NP;
5057 case ISD::SETOEQ:
5058 case ISD::SETUNE: return X86::COND_INVALID;
5059 }
5060}
5061
5062/// Is there a floating point cmov for the specific X86 condition code?
5063/// Current x86 isa includes the following FP cmov instructions:
5064/// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
5065static bool hasFPCMov(unsigned X86CC) {
5066 switch (X86CC) {
5067 default:
5068 return false;
5069 case X86::COND_B:
5070 case X86::COND_BE:
5071 case X86::COND_E:
5072 case X86::COND_P:
5073 case X86::COND_A:
5074 case X86::COND_AE:
5075 case X86::COND_NE:
5076 case X86::COND_NP:
5077 return true;
5078 }
5079}
5080
5081
5082bool X86TargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
5083 const CallInst &I,
5084 MachineFunction &MF,
5085 unsigned Intrinsic) const {
5086 Info.flags = MachineMemOperand::MONone;
5087 Info.offset = 0;
5088
5089 const IntrinsicData* IntrData = getIntrinsicWithChain(Intrinsic);
5090 if (!IntrData) {
5091 switch (Intrinsic) {
5092 case Intrinsic::x86_aesenc128kl:
5093 case Intrinsic::x86_aesdec128kl:
5094 Info.opc = ISD::INTRINSIC_W_CHAIN;
5095 Info.ptrVal = I.getArgOperand(1);
5096 Info.memVT = EVT::getIntegerVT(I.getType()->getContext(), 48);
5097 Info.align = Align(1);
5098 Info.flags |= MachineMemOperand::MOLoad;
5099 return true;
5100 case Intrinsic::x86_aesenc256kl:
5101 case Intrinsic::x86_aesdec256kl:
5102 Info.opc = ISD::INTRINSIC_W_CHAIN;
5103 Info.ptrVal = I.getArgOperand(1);
5104 Info.memVT = EVT::getIntegerVT(I.getType()->getContext(), 64);
5105 Info.align = Align(1);
5106 Info.flags |= MachineMemOperand::MOLoad;
5107 return true;
5108 case Intrinsic::x86_aesencwide128kl:
5109 case Intrinsic::x86_aesdecwide128kl:
5110 Info.opc = ISD::INTRINSIC_W_CHAIN;
5111 Info.ptrVal = I.getArgOperand(0);
5112 Info.memVT = EVT::getIntegerVT(I.getType()->getContext(), 48);
5113 Info.align = Align(1);
5114 Info.flags |= MachineMemOperand::MOLoad;
5115 return true;
5116 case Intrinsic::x86_aesencwide256kl:
5117 case Intrinsic::x86_aesdecwide256kl:
5118 Info.opc = ISD::INTRINSIC_W_CHAIN;
5119 Info.ptrVal = I.getArgOperand(0);
5120 Info.memVT = EVT::getIntegerVT(I.getType()->getContext(), 64);
5121 Info.align = Align(1);
5122 Info.flags |= MachineMemOperand::MOLoad;
5123 return true;
5124 }
5125 return false;
5126 }
5127
5128 switch (IntrData->Type) {
5129 case TRUNCATE_TO_MEM_VI8:
5130 case TRUNCATE_TO_MEM_VI16:
5131 case TRUNCATE_TO_MEM_VI32: {
5132 Info.opc = ISD::INTRINSIC_VOID;
5133 Info.ptrVal = I.getArgOperand(0);
5134 MVT VT = MVT::getVT(I.getArgOperand(1)->getType());
5135 MVT ScalarVT = MVT::INVALID_SIMPLE_VALUE_TYPE;
5136 if (IntrData->Type == TRUNCATE_TO_MEM_VI8)
5137 ScalarVT = MVT::i8;
5138 else if (IntrData->Type == TRUNCATE_TO_MEM_VI16)
5139 ScalarVT = MVT::i16;
5140 else if (IntrData->Type == TRUNCATE_TO_MEM_VI32)
5141 ScalarVT = MVT::i32;
5142
5143 Info.memVT = MVT::getVectorVT(ScalarVT, VT.getVectorNumElements());
5144 Info.align = Align(1);
5145 Info.flags |= MachineMemOperand::MOStore;
5146 break;
5147 }
5148 case GATHER:
5149 case GATHER_AVX2: {
5150 Info.opc = ISD::INTRINSIC_W_CHAIN;
5151 Info.ptrVal = nullptr;
5152 MVT DataVT = MVT::getVT(I.getType());
5153 MVT IndexVT = MVT::getVT(I.getArgOperand(2)->getType());
5154 unsigned NumElts = std::min(DataVT.getVectorNumElements(),
5155 IndexVT.getVectorNumElements());
5156 Info.memVT = MVT::getVectorVT(DataVT.getVectorElementType(), NumElts);
5157 Info.align = Align(1);
5158 Info.flags |= MachineMemOperand::MOLoad;
5159 break;
5160 }
5161 case SCATTER: {
5162 Info.opc = ISD::INTRINSIC_VOID;
5163 Info.ptrVal = nullptr;
5164 MVT DataVT = MVT::getVT(I.getArgOperand(3)->getType());
5165 MVT IndexVT = MVT::getVT(I.getArgOperand(2)->getType());
5166 unsigned NumElts = std::min(DataVT.getVectorNumElements(),
5167 IndexVT.getVectorNumElements());
5168 Info.memVT = MVT::getVectorVT(DataVT.getVectorElementType(), NumElts);
5169 Info.align = Align(1);
5170 Info.flags |= MachineMemOperand::MOStore;
5171 break;
5172 }
5173 default:
5174 return false;
5175 }
5176
5177 return true;
5178}
5179
5180/// Returns true if the target can instruction select the
5181/// specified FP immediate natively. If false, the legalizer will
5182/// materialize the FP immediate as a load from a constant pool.
5183bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT,
5184 bool ForCodeSize) const {
5185 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
5186 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
5187 return true;
5188 }
5189 return false;
5190}
5191
5192bool X86TargetLowering::shouldReduceLoadWidth(SDNode *Load,
5193 ISD::LoadExtType ExtTy,
5194 EVT NewVT) const {
5195 assert(cast<LoadSDNode>(Load)->isSimple() && "illegal to narrow")((cast<LoadSDNode>(Load)->isSimple() && "illegal to narrow"
) ? static_cast<void> (0) : __assert_fail ("cast<LoadSDNode>(Load)->isSimple() && \"illegal to narrow\""
, "/build/llvm-toolchain-snapshot-13~++20210405022414+5f57793c4fe4/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 5195, __PRETTY_FUNCTION__))
;
5196
5197 // "ELF Handling for Thread-Local Storage" specifies that R_X86_64_GOTTPOFF
5198 // relocation target a movq or addq instruction: don't let the load shrink.
5199 SDValue BasePtr = cast<LoadSDNode>(Load)->getBasePtr();
5200 if (BasePtr.getOpcode() == X86ISD::WrapperRIP)
5201 if (const auto *GA = dyn_cast<GlobalAddressSDNode>(BasePtr.getOperand(0)))
5202 return GA->getTargetFlags() != X86II::MO_GOTTPOFF;
5203
5204 // If this is an (1) AVX vector load with (2) multiple uses and (3) all of
5205 // those uses are extracted directly into a store, then the extract + store
5206 // can be store-folded. Therefore, it's probably not worth splitting the load.
5207 EVT VT = Load->getValueType(0);
5208 if ((VT.is256BitVector() || VT.is512BitVector()) && !Load->hasOneUse()) {
5209 for (auto UI = Load->use_begin(), UE = Load->use_end(); UI != UE; ++UI) {
5210 // Skip uses of the chain value. Result 0 of the node is the load value.
5211 if (UI.getUse().getResNo() != 0)
5212 continue;
5213
5214 // If this use is not an extract + store, it's probably worth splitting.
5215 if (UI->getOpcode() != ISD::EXTRACT_SUBVECTOR || !UI->hasOneUse() ||
5216 UI->use_begin()->getOpcode() != ISD::STORE)
5217 return true;
5218 }
5219 // All non-chain uses are extract + store.
5220 return false;
5221 }
5222
5223 return true;
5224}
5225
5226/// Returns true if it is beneficial to convert a load of a constant
5227/// to just the constant itself.
5228bool X86TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
5229 Type *Ty) const {
5230 assert(Ty->isIntegerTy())((Ty->isIntegerTy()) ? static_cast<void> (0) : __assert_fail
("Ty->isIntegerTy()", "/build/llvm-toolchain-snapshot-13~++20210405022414+5f57793c4fe4/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 5230, __PRETTY_FUNCTION__))
;
5231
5232 unsigned BitSize = Ty->getPrimitiveSizeInBits();
5233 if (BitSize == 0 || BitSize > 64)
5234 return false;
5235 return true;
5236}
5237
5238bool X86TargetLowering::reduceSelectOfFPConstantLoads(EVT CmpOpVT) const {
5239 // If we are using XMM registers in the ABI and the condition of the select is
5240 // a floating-point compare and we have blendv or conditional move, then it is
5241 // cheaper to select instead of doing a cross-register move and creating a
5242 // load that depends on the compare result.
5243 bool IsFPSetCC = CmpOpVT.isFloatingPoint() && CmpOpVT != MVT::f128;
5244 return !IsFPSetCC || !Subtarget.isTarget64BitLP64() || !Subtarget.hasAVX();
5245}
5246
5247bool X86TargetLowering::convertSelectOfConstantsToMath(EVT VT) const {
5248 // TODO: It might be a win to ease or lift this restriction, but the generic
5249 // folds in DAGCombiner conflict with vector folds for an AVX512 target.
5250 if (VT.isVector() && Subtarget.hasAVX512())
5251 return false;
5252
5253 return true;
5254}
5255
5256bool X86TargetLowering::decomposeMulByConstant(LLVMContext &Context, EVT VT,
5257 SDValue C) const {
5258 // TODO: We handle scalars using custom code, but generic combining could make
5259 // that unnecessary.
5260 APInt MulC;
5261 if (!ISD::isConstantSplatVector(C.getNode(), MulC))
5262 return false;
5263
5264 // Find the type this will be legalized too. Otherwise we might prematurely
5265 // convert this to shl+add/sub and then still have to type legalize those ops.
5266 // Another choice would be to defer the decision for illegal types until
5267 // after type legalization. But constant splat vectors of i64 can't make it
5268 // through type legalization on 32-bit targets so we would need to special
5269 // case vXi64.
5270 while (getTypeAction(Context, VT) != TypeLegal)
5271 VT = getTypeToTransformTo(Context, VT);
5272
5273 // If vector multiply is legal, assume that's faster than shl + add/sub.
5274 // TODO: Multiply is a complex op with higher latency and lower throughput in
5275 // most implementations, so this check could be loosened based on type
5276 // and/or a CPU attribute.
5277 if (isOperationLegal(ISD::MUL, VT))
5278 return false;
5279
5280 // shl+add, shl+sub, shl+add+neg
5281 return (MulC + 1).isPowerOf2() || (MulC - 1).isPowerOf2() ||
5282 (1 - MulC).isPowerOf2() || (-(MulC + 1)).isPowerOf2();
5283}
5284
5285bool X86TargetLowering::isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
5286 unsigned Index) const {
5287 if (!isOperationLegalOrCustom(ISD::EXTRACT_SUBVECTOR, ResVT))
5288 return false;
5289
5290 // Mask vectors support all subregister combinations and operations that
5291 // extract half of vector.
5292 if (ResVT.getVectorElementType() == MVT::i1)
5293 return Index == 0 || ((ResVT.getSizeInBits() == SrcVT.getSizeInBits()*2) &&
5294 (Index == ResVT.getVectorNumElements()));
5295
5296 return (Index % ResVT.getVectorNumElements()) == 0;
5297}
5298
5299bool X86TargetLowering::shouldScalarizeBinop(SDValue VecOp) const {
5300 unsigned Opc = VecOp.getOpcode();
5301
5302 // Assume target opcodes can't be scalarized.
5303 // TODO - do we have any exceptions?
5304 if (Opc >= ISD::BUILTIN_OP_END)
5305 return false;
5306
5307 // If the vector op is not supported, try to convert to scalar.
5308 EVT VecVT = VecOp.getValueType();
5309 if (!isOperationLegalOrCustomOrPromote(Opc, VecVT))
5310 return true;
5311
5312 // If the vector op is supported, but the scalar op is not, the transform may
5313 // not be worthwhile.
5314 EVT ScalarVT = VecVT.getScalarType();
5315 return isOperationLegalOrCustomOrPromote(Opc, ScalarVT);
5316}
5317
5318bool X86TargetLowering::shouldFormOverflowOp(unsigned Opcode, EVT VT,
5319 bool) const {
5320 // TODO: Allow vectors?
5321 if (VT.isVector())
5322 return false;
5323 return VT.isSimple() || !isOperationExpand(Opcode, VT);
5324}
5325
5326bool X86TargetLowering::isCheapToSpeculateCttz() const {
5327 // Speculate cttz only if we can directly use TZCNT.
5328 return Subtarget.hasBMI();
5329}
5330
5331bool X86TargetLowering::isCheapToSpeculateCtlz() const {
5332 // Speculate ctlz only if we can directly use LZCNT.
5333 return Subtarget.hasLZCNT();
5334}
5335
5336bool X86TargetLowering::isLoadBitCastBeneficial(EVT LoadVT, EVT BitcastVT,
5337 const SelectionDAG &DAG,
5338 const MachineMemOperand &MMO) const {
5339 if (!Subtarget.hasAVX512() && !LoadVT.isVector() && BitcastVT.isVector() &&
5340 BitcastVT.getVectorElementType() == MVT::i1)
5341 return false;
5342
5343 if (!Subtarget.hasDQI() && BitcastVT == MVT::v8i1 && LoadVT == MVT::i8)
5344 return false;
5345
5346 // If both types are legal vectors, it's always ok to convert them.
5347 if (LoadVT.isVector() && BitcastVT.isVector() &&
5348 isTypeLegal(LoadVT) && isTypeLegal(BitcastVT))
5349 return true;
5350
5351 return TargetLowering::isLoadBitCastBeneficial(LoadVT, BitcastVT, DAG, MMO);
5352}
5353
5354bool X86TargetLowering::canMergeStoresTo(unsigned AddressSpace, EVT MemVT,
5355 const SelectionDAG &DAG) const {
5356 // Do not merge to float value size (128 bytes) if no implicit
5357 // float attribute is set.
5358 bool NoFloat = DAG.getMachineFunction().getFunction().hasFnAttribute(
5359 Attribute::NoImplicitFloat);
5360
5361 if (NoFloat) {
5362 unsigned MaxIntSize = Subtarget.is64Bit() ? 64 : 32;
5363 return (MemVT.getSizeInBits() <= MaxIntSize);
5364 }
5365 // Make sure we don't merge greater than our preferred vector
5366 // width.
5367 if (MemVT.getSizeInBits() > Subtarget.getPreferVectorWidth())
5368 return false;
5369
5370 return true;
5371}
5372
5373bool X86TargetLowering::isCtlzFast() const {
5374 return Subtarget.hasFastLZCNT();
5375}
5376
5377bool X86TargetLowering::isMaskAndCmp0FoldingBeneficial(
5378 const Instruction &AndI) const {
5379 return true;
5380}
5381
5382bool X86TargetLowering::hasAndNotCompare(SDValue Y) const {
5383 EVT VT = Y.getValueType();
5384
5385 if (VT.isVector())
5386 return false;
5387
5388 if (!Subtarget.hasBMI())
5389 return false;
5390
5391 // There are only 32-bit and 64-bit forms for 'andn'.
5392 if (VT != MVT::i32 && VT != MVT::i64)
5393 return false;
5394
5395 return !isa<ConstantSDNode>(Y);
5396}
5397
5398bool X86TargetLowering::hasAndNot(SDValue Y) const {
5399 EVT VT = Y.getValueType();
5400
5401 if (!VT.isVector())
5402 return hasAndNotCompare(Y);
5403
5404 // Vector.
5405
5406 if (!Subtarget.hasSSE1() || VT.getSizeInBits() < 128)
5407 return false;
5408
5409 if (VT == MVT::v4i32)
5410 return true;
5411
5412 return Subtarget.hasSSE2();
5413}
5414
5415bool X86TargetLowering::hasBitTest(SDValue X, SDValue Y) const {
5416 return X.getValueType().isScalarInteger(); // 'bt'
5417}
5418
5419bool X86TargetLowering::
5420 shouldProduceAndByConstByHoistingConstFromShiftsLHSOfAnd(
5421 SDValue X, ConstantSDNode *XC, ConstantSDNode *CC, SDValue Y,
5422 unsigned OldShiftOpcode, unsigned NewShiftOpcode,
5423 SelectionDAG &DAG) const {
5424 // Does baseline recommend not to perform the fold by default?
5425 if (!TargetLowering::shouldProduceAndByConstByHoistingConstFromShiftsLHSOfAnd(
5426 X, XC, CC, Y, OldShiftOpcode, NewShiftOpcode, DAG))
5427 return false;
5428 // For scalars this transform is always beneficial.
5429 if (X.getValueType().isScalarInteger())
5430 return true;
5431 // If all the shift amounts are identical, then transform is beneficial even
5432 // with rudimentary SSE2 shifts.
5433 if (DAG.isSplatValue(Y, /*AllowUndefs=*/true))
5434 return true;
5435 // If we have AVX2 with it's powerful shift operations, then it's also good.
5436 if (Subtarget.hasAVX2())
5437 return true;
5438 // Pre-AVX2 vector codegen for this pattern is best for variant with 'shl'.
5439 return NewShiftOpcode == ISD::SHL;
5440}
5441
5442bool X86TargetLowering::shouldFoldConstantShiftPairToMask(
5443 const SDNode *N, CombineLevel Level) const {
5444 assert(((N->getOpcode() == ISD::SHL &&((((N->getOpcode() == ISD::SHL && N->getOperand
(0).getOpcode() == ISD::SRL) || (N->getOpcode() == ISD::SRL
&& N->getOperand(0).getOpcode() == ISD::SHL)) &&
"Expected shift-shift mask") ? static_cast<void> (0) :
__assert_fail ("((N->getOpcode() == ISD::SHL && N->getOperand(0).getOpcode() == ISD::SRL) || (N->getOpcode() == ISD::SRL && N->getOperand(0).getOpcode() == ISD::SHL)) && \"Expected shift-shift mask\""
, "/build/llvm-toolchain-snapshot-13~++20210405022414+5f57793c4fe4/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 5448, __PRETTY_FUNCTION__))
5445 N->getOperand(0).getOpcode() == ISD::SRL) ||((((N->getOpcode() == ISD::SHL && N->getOperand
(0).getOpcode() == ISD::SRL) || (N->getOpcode() == ISD::SRL
&& N->getOperand(0).getOpcode() == ISD::SHL)) &&
"Expected shift-shift mask") ? static_cast<void> (0) :
__assert_fail ("((N->getOpcode() == ISD::SHL && N->getOperand(0).getOpcode() == ISD::SRL) || (N->getOpcode() == ISD::SRL && N->getOperand(0).getOpcode() == ISD::SHL)) && \"Expected shift-shift mask\""
, "/build/llvm-toolchain-snapshot-13~++20210405022414+5f57793c4fe4/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 5448, __PRETTY_FUNCTION__))
5446 (N->getOpcode() == ISD::SRL &&((((N->getOpcode() == ISD::SHL && N->getOperand
(0).getOpcode() == ISD::SRL) || (N->getOpcode() == ISD::SRL
&& N->getOperand(0).getOpcode() == ISD::SHL)) &&
"Expected shift-shift mask") ? static_cast<void> (0) :
__assert_fail ("((N->getOpcode() == ISD::SHL && N->getOperand(0).getOpcode() == ISD::SRL) || (N->getOpcode() == ISD::SRL && N->getOperand(0).getOpcode() == ISD::SHL)) && \"Expected shift-shift mask\""
, "/build/llvm-toolchain-snapshot-13~++20210405022414+5f57793c4fe4/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 5448, __PRETTY_FUNCTION__))
5447 N->getOperand(0).getOpcode() == ISD::SHL)) &&((((N->getOpcode() == ISD::SHL && N->getOperand
(0).getOpcode() == ISD::SRL) || (N->getOpcode() == ISD::SRL
&& N->getOperand(0).getOpcode() == ISD::SHL)) &&
"Expected shift-shift mask") ? static_cast<void> (0) :
__assert_fail ("((N->getOpcode() == ISD::SHL && N->getOperand(0).getOpcode() == ISD::SRL) || (N->getOpcode() == ISD::SRL && N->getOperand(0).getOpcode() == ISD::SHL)) && \"Expected shift-shift mask\""
, "/build/llvm-toolchain-snapshot-13~++20210405022414+5f57793c4fe4/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 5448, __PRETTY_FUNCTION__))
5448 "Expected shift-shift mask")((((N->getOpcode() == ISD::SHL && N->getOperand
(0).getOpcode() == ISD::SRL) || (N->getOpcode() == ISD::SRL
&& N->getOperand(0).getOpcode() == ISD::SHL)) &&
"Expected shift-shift mask") ? static_cast<void> (0) :
__assert_fail ("((N->getOpcode() == ISD::SHL && N->getOperand(0).getOpcode() == ISD::SRL) || (N->getOpcode() == ISD::SRL && N->getOperand(0).getOpcode() == ISD::SHL)) && \"Expected shift-shift mask\""
, "/build/llvm-toolchain-snapshot-13~++20210405022414+5f57793c4fe4/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 5448, __PRETTY_FUNCTION__))
;
5449 EVT VT = N->getValueType(0);
5450 if ((Subtarget.hasFastVectorShiftMasks() && VT.isVector()) ||
5451 (Subtarget.hasFastScalarShiftMasks() && !VT.isVector())) {
5452 // Only fold if the shift values are equal - so it folds to AND.
5453 // TODO - we should fold if either is a non-uniform vector but we don't do
5454 // the fold for non-splats yet.
5455 return N->getOperand(1) == N->getOperand(0).getOperand(1);
5456 }
5457 return TargetLoweringBase::shouldFoldConstantShiftPairToMask(N, Level);
5458}
5459
5460bool X86TargetLowering::shouldFoldMaskToVariableShiftPair(SDValue Y) const {
5461 EVT VT = Y.getValueType();
5462
5463 // For vectors, we don't have a preference, but we probably want a mask.
5464 if (VT.isVector())
5465 return false;
5466
5467 // 64-bit shifts on 32-bit targets produce really bad bloated code.
5468 if (VT == MVT::i64 && !Subtarget.is64Bit())
5469 return false;
5470
5471 return true;
5472}
5473
5474bool X86TargetLowering::shouldExpandShift(SelectionDAG &DAG,
5475 SDNode *N) const {
5476 if (DAG.getMachineFunction().getFunction().hasMinSize() &&
5477 !Subtarget.isOSWindows())
5478 return false;
5479 return true;
5480}
5481
5482bool X86TargetLowering::shouldSplatInsEltVarIndex(EVT VT) const {
5483 // Any legal vector type can be splatted more efficiently than
5484 // loading/spilling from memory.
5485 return isTypeLegal(VT);
5486}
5487
5488MVT X86TargetLowering::hasFastEqualityCompare(unsigned NumBits) const {
5489 MVT VT = MVT::getIntegerVT(NumBits);
5490 if (isTypeLegal(VT))
5491 return VT;
5492
5493 // PMOVMSKB can handle this.
5494 if (NumBits == 128 && isTypeLegal(MVT::v16i8))
5495 return MVT::v16i8;
5496
5497 // VPMOVMSKB can handle this.
5498 if (NumBits == 256 && isTypeLegal(MVT::v32i8))
5499 return MVT::v32i8;
5500
5501 // TODO: Allow 64-bit type for 32-bit target.
5502 // TODO: 512-bit types should be allowed, but make sure that those
5503 // cases are handled in combineVectorSizedSetCCEquality().
5504
5505 return MVT::INVALID_SIMPLE_VALUE_TYPE;
5506}
5507
5508/// Val is the undef sentinel value or equal to the specified value.
5509static bool isUndefOrEqual(int Val, int CmpVal) {
5510 return ((Val == SM_SentinelUndef) || (Val == CmpVal));
5511}
5512
5513/// Return true if every element in Mask is the undef sentinel value or equal to
5514/// the specified value..
5515static bool isUndefOrEqual(ArrayRef<int> Mask, int CmpVal) {
5516 return llvm::all_of(Mask, [CmpVal](int M) {
5517 return (M == SM_SentinelUndef) || (M == CmpVal);
5518 });
5519}
5520
5521/// Val is either the undef or zero sentinel value.
5522static bool isUndefOrZero(int Val) {
5523 return ((Val == SM_SentinelUndef) || (Val == SM_SentinelZero));
5524}
5525
5526/// Return true if every element in Mask, beginning from position Pos and ending
5527/// in Pos+Size is the undef sentinel value.
5528static bool isUndefInRange(ArrayRef<int> Mask, unsigned Pos, unsigned Size) {
5529 return llvm::all_of(Mask.slice(Pos, Size),
5530 [](int M) { return M == SM_SentinelUndef; });
5531}
5532
5533/// Return true if the mask creates a vector whose lower half is undefined.
5534static bool isUndefLowerHalf(ArrayRef<int> Mask) {
5535 unsigned NumElts = Mask.size();
5536 return isUndefInRange(Mask, 0, NumElts / 2);
5537}
5538
5539/// Return true if the mask creates a vector whose upper half is undefined.
5540static bool isUndefUpperHalf(ArrayRef<int> Mask) {
5541 unsigned NumElts = Mask.size();
5542 return isUndefInRange(Mask, NumElts / 2, NumElts / 2);
5543}
5544
5545/// Return true if Val falls within the specified range (L, H].
5546static bool isInRange(int Val, int Low, int Hi) {
5547 return (Val >= Low && Val < Hi);
5548}
5549
5550/// Return true if the value of any element in Mask falls within the specified
5551/// range (L, H].
5552static bool isAnyInRange(ArrayRef<int> Mask, int Low, int Hi) {
5553 return llvm::any_of(Mask, [Low, Hi](int M) { return isInRange(M, Low, Hi); });
5554}
5555
5556/// Return true if the value of any element in Mask is the zero sentinel value.
5557static bool isAnyZero(ArrayRef<int> Mask) {
5558 return llvm::any_of(Mask, [](int M) { return M == SM_SentinelZero; });
5559}
5560
5561/// Return true if the value of any element in Mask is the zero or undef
5562/// sentinel values.
5563static bool isAnyZeroOrUndef(ArrayRef<int> Mask) {
5564 return llvm::any_of(Mask, [](int M) {
5565 return M == SM_SentinelZero || M == SM_SentinelUndef;
5566 });
5567}
5568
5569/// Return true if Val is undef or if its value falls within the
5570/// specified range (L, H].
5571static bool isUndefOrInRange(int Val, int Low, int Hi) {
5572 return (Val == SM_SentinelUndef) || isInRange(Val, Low, Hi);
5573}
5574
5575/// Return true if every element in Mask is undef or if its value
5576/// falls within the specified range (L, H].
5577static bool isUndefOrInRange(ArrayRef<int> Mask, int Low, int Hi) {
5578 return llvm::all_of(
5579 Mask, [Low, Hi](int M) { return isUndefOrInRange(M, Low, Hi); });
5580}
5581
5582/// Return true if Val is undef, zero or if its value falls within the
5583/// specified range (L, H].
5584static bool isUndefOrZeroOrInRange(int Val, int Low, int Hi) {
5585 return isUndefOrZero(Val) || isInRange(Val, Low, Hi);
5586}
5587
5588/// Return true if every element in Mask is undef, zero or if its value
5589/// falls within the specified range (L, H].
5590static bool isUndefOrZeroOrInRange(ArrayRef<int> Mask, int Low, int Hi) {
5591 return llvm::all_of(
5592 Mask, [Low, Hi](int M) { return isUndefOrZeroOrInRange(M, Low, Hi); });
5593}
5594
5595/// Return true if every element in Mask, beginning
5596/// from position Pos and ending in Pos + Size, falls within the specified
5597/// sequence (Low, Low + Step, ..., Low + (Size - 1) * Step) or is undef.
5598static bool isSequentialOrUndefInRange(ArrayRef<int> Mask, unsigned Pos,
5599 unsigned Size, int Low, int Step = 1) {
5600 for (unsigned i = Pos, e = Pos + Size; i != e; ++i, Low += Step)
5601 if (!isUndefOrEqual(Mask[i], Low))
5602 return false;
5603 return true;
5604}
5605
5606/// Return true if every element in Mask, beginning
5607/// from position Pos and ending in Pos+Size, falls within the specified
5608/// sequential range (Low, Low+Size], or is undef or is zero.
5609static bool isSequentialOrUndefOrZeroInRange(ArrayRef<int> Mask, unsigned Pos,
5610 unsigned Size, int Low,
5611 int Step = 1) {
5612 for (unsigned i = Pos, e = Pos + Size; i != e; ++i, Low += Step)
5613 if (!isUndefOrZero(Mask[i]) && Mask[i] != Low)
5614 return false;
5615 return true;
5616}
5617
5618/// Return true if every element in Mask, beginning
5619/// from position Pos and ending in Pos+Size is undef or is zero.
5620static bool isUndefOrZeroInRange(ArrayRef<int> Mask, unsigned Pos,
5621 unsigned Size) {
5622 return llvm::all_of(Mask.slice(Pos, Size),
5623 [](int M) { return isUndefOrZero(M); });
5624}
5625
5626/// Helper function to test whether a shuffle mask could be
5627/// simplified by widening the elements being shuffled.
5628///
5629/// Appends the mask for wider elements in WidenedMask if valid. Otherwise
5630/// leaves it in an unspecified state.
5631///
5632/// NOTE: This must handle normal vector shuffle masks and *target* vector
5633/// shuffle masks. The latter have the special property of a '-2' representing
5634/// a zero-ed lane of a vector.
5635static bool canWidenShuffleElements(ArrayRef<int> Mask,
5636 SmallVectorImpl<int> &WidenedMask) {
5637 WidenedMask.assign(Mask.size() / 2, 0);
5638 for (int i = 0, Size = Mask.size(); i < Size; i += 2) {
5639 int M0 = Mask[i];
5640 int M1 = Mask[i + 1];
5641
5642 // If both elements are undef, its trivial.
5643 if (M0 == SM_SentinelUndef && M1 == SM_SentinelUndef) {
5644 WidenedMask[i / 2] = SM_SentinelUndef;
5645 continue;
5646 }
5647
5648 // Check for an undef mask and a mask value properly aligned to fit with
5649 // a pair of values. If we find such a case, use the non-undef mask's value.
5650 if (M0 == SM_SentinelUndef && M1 >= 0 && (M1 % 2) == 1) {
5651 WidenedMask[i / 2] = M1 / 2;
5652 continue;
5653 }
5654 if (M1 == SM_SentinelUndef && M0 >= 0 && (M0 % 2) == 0) {
5655 WidenedMask[i / 2] = M0 / 2;
5656 continue;
5657 }
5658
5659 // When zeroing, we need to spread the zeroing across both lanes to widen.
5660 if (M0 == SM_SentinelZero || M1 == SM_SentinelZero) {
5661 if ((M0 == SM_SentinelZero || M0 == SM_SentinelUndef) &&
5662 (M1 == SM_SentinelZero || M1 == SM_SentinelUndef)) {
5663 WidenedMask[i / 2] = SM_SentinelZero;
5664 continue;
5665 }
5666 return false;
5667 }
5668
5669 // Finally check if the two mask values are adjacent and aligned with
5670 // a pair.
5671 if (M0 != SM_SentinelUndef && (M0 % 2) == 0 && (M0 + 1) == M1) {
5672 WidenedMask[i / 2] = M0 / 2;
5673 continue;
5674 }
5675
5676 // Otherwise we can't safely widen the elements used in this shuffle.
5677 return false;
5678 }
5679 assert(WidenedMask.size() == Mask.size() / 2 &&((WidenedMask.size() == Mask.size() / 2 && "Incorrect size of mask after widening the elements!"
) ? static_cast<void> (0) : __assert_fail ("WidenedMask.size() == Mask.size() / 2 && \"Incorrect size of mask after widening the elements!\""
, "/build/llvm-toolchain-snapshot-13~++20210405022414+5f57793c4fe4/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 5680, __PRETTY_FUNCTION__))
5680 "Incorrect size of mask after widening the elements!")((WidenedMask.size() == Mask.size() / 2 && "Incorrect size of mask after widening the elements!"
) ? static_cast<void> (0) : __assert_fail ("WidenedMask.size() == Mask.size() / 2 && \"Incorrect size of mask after widening the elements!\""
, "/build/llvm-toolchain-snapshot-13~++20210405022414+5f57793c4fe4/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 5680, __PRETTY_FUNCTION__))
;
5681
5682 return true;
5683}
5684
5685static bool canWidenShuffleElements(ArrayRef<int> Mask,
5686 const APInt &Zeroable,
5687 bool V2IsZero,
5688 SmallVectorImpl<int> &WidenedMask) {
5689 // Create an alternative mask with info about zeroable elements.
5690 // Here we do not set undef elements as zeroable.
5691 SmallVector<int, 64> ZeroableMask(Mask.begin(), Mask.end());
5692 if (V2IsZero) {
5693 assert(!Zeroable.isNullValue() && "V2's non-undef elements are used?!")((!Zeroable.isNullValue() && "V2's non-undef elements are used?!"
) ? static_cast<void> (0) : __assert_fail ("!Zeroable.isNullValue() && \"V2's non-undef elements are used?!\""
, "/build/llvm-toolchain-snapshot-13~++20210405022414+5f57793c4fe4/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 5693, __PRETTY_FUNCTION__))
;
5694 for (int i = 0, Size = Mask.size(); i != Size; ++i)
5695 if (Mask[i] != SM_SentinelUndef && Zeroable[i])
5696 ZeroableMask[i] = SM_SentinelZero;
5697 }
5698 return canWidenShuffleElements(ZeroableMask, WidenedMask);
5699}
5700
5701static bool canWidenShuffleElements(ArrayRef<int> Mask) {
5702 SmallVector<int, 32> WidenedMask;
5703 return canWidenShuffleElements(Mask, WidenedMask);
5704}
5705
5706// Attempt to narrow/widen shuffle mask until it matches the target number of
5707// elements.
5708static bool scaleShuffleElements(ArrayRef<int> Mask, unsigned NumDstElts,
5709 SmallVectorImpl<int> &ScaledMask) {
5710 unsigned NumSrcElts = Mask.size();
5711 assert(((NumSrcElts % NumDstElts) == 0 || (NumDstElts % NumSrcElts) == 0) &&((((NumSrcElts % NumDstElts) == 0 || (NumDstElts % NumSrcElts
) == 0) && "Illegal shuffle scale factor") ? static_cast
<void> (0) : __assert_fail ("((NumSrcElts % NumDstElts) == 0 || (NumDstElts % NumSrcElts) == 0) && \"Illegal shuffle scale factor\""
, "/build/llvm-toolchain-snapshot-13~++20210405022414+5f57793c4fe4/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 5712, __PRETTY_FUNCTION__))
5712 "Illegal shuffle scale factor")((((NumSrcElts % NumDstElts) == 0 || (NumDstElts % NumSrcElts
) == 0) && "Illegal shuffle scale factor") ? static_cast
<void> (0) : __assert_fail ("((NumSrcElts % NumDstElts) == 0 || (NumDstElts % NumSrcElts) == 0) && \"Illegal shuffle scale factor\""
, "/build/llvm-toolchain-snapshot-13~++20210405022414+5f57793c4fe4/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 5712, __PRETTY_FUNCTION__))
;
5713
5714 // Narrowing is guaranteed to work.
5715 if (NumDstElts >= NumSrcElts) {
5716 int Scale = NumDstElts / NumSrcElts;
5717 llvm::narrowShuffleMaskElts(Scale, Mask, ScaledMask);
5718 return true;
5719 }
5720
5721 // We have to repeat the widening until we reach the target size, but we can
5722 // split out the first widening as it sets up ScaledMask for us.
5723 if (canWidenShuffleElements(Mask, ScaledMask)) {
5724 while (ScaledMask.size() > NumDstElts) {
5725 SmallVector<int, 16> WidenedMask;
5726 if (!canWidenShuffleElements(ScaledMask, WidenedMask))
5727 return false;
5728 ScaledMask = std::move(WidenedMask);
5729 }
5730 return true;
5731 }
5732
5733 return false;
5734}
5735
5736/// Returns true if Elt is a constant zero or a floating point constant +0.0.
5737bool X86::isZeroNode(SDValue Elt) {
5738 return isNullConstant(Elt) || isNullFPConstant(Elt);
5739}
5740
5741// Build a vector of constants.
5742// Use an UNDEF node if MaskElt == -1.
5743// Split 64-bit constants in the 32-bit mode.
5744static SDValue getConstVector(ArrayRef<int> Values, MVT VT, SelectionDAG &DAG,
5745 const SDLoc &dl, bool IsMask = false) {
5746
5747 SmallVector<SDValue, 32> Ops;
5748 bool Split = false;
5749
5750 MVT ConstVecVT = VT;
5751 unsigned NumElts = VT.getVectorNumElements();
5752 bool In64BitMode = DAG.getTargetLoweringInfo().isTypeLegal(MVT::i64);
5753 if (!In64BitMode && VT.getVectorElementType() == MVT::i64) {
5754 ConstVecVT = MVT::getVectorVT(MVT::i32, NumElts * 2);
5755 Split = true;
5756 }
5757
5758 MVT EltVT = ConstVecVT.getVectorElementType();
5759 for (unsigned i = 0; i < NumElts; ++i) {
5760 bool IsUndef = Values[i] < 0 && IsMask;
5761 SDValue OpNode = IsUndef ? DAG.getUNDEF(EltVT) :
5762 DAG.getConstant(Values[i], dl, EltVT);
5763 Ops.push_back(OpNode);
5764 if (Split)
5765 Ops.push_back(IsUndef ? DAG.getUNDEF(EltVT) :
5766 DAG.getConstant(0, dl, EltVT));
5767 }
5768 SDValue ConstsNode = DAG.getBuildVector(ConstVecVT, dl, Ops);
5769 if (Split)
5770 ConstsNode = DAG.getBitcast(VT, ConstsNode);
5771 return ConstsNode;
5772}
5773
5774static SDValue getConstVector(ArrayRef<APInt> Bits, APInt &Undefs,
5775 MVT VT, SelectionDAG &DAG, const SDLoc &dl) {
5776 assert(Bits.size() == Undefs.getBitWidth() &&((Bits.size() == Undefs.getBitWidth() && "Unequal constant and undef arrays"
) ? static_cast<void> (0) : __assert_fail ("Bits.size() == Undefs.getBitWidth() && \"Unequal constant and undef arrays\""
, "/build/llvm-toolchain-snapshot-13~++20210405022414+5f57793c4fe4/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 5777, __PRETTY_FUNCTION__))
5777 "Unequal constant and undef arrays")((Bits.size() == Undefs.getBitWidth() && "Unequal constant and undef arrays"
) ? static_cast<void> (0) : __assert_fail ("Bits.size() == Undefs.getBitWidth() && \"Unequal constant and undef arrays\""
, "/build/llvm-toolchain-snapshot-13~++20210405022414+5f57793c4fe4/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 5777, __PRETTY_FUNCTION__))
;
5778 SmallVector<SDValue, 32> Ops;
5779 bool Split = false;
5780
5781 MVT ConstVecVT = VT;
5782 unsigned NumElts = VT.getVectorNumElements();
5783 bool In64BitMode = DAG.getTargetLoweringInfo().isTypeLegal(MVT::i64);
5784 if (!In64BitMode && VT.getVectorElementType() == MVT::i64) {
5785 ConstVecVT = MVT::getVectorVT(MVT::i32, NumElts * 2);
5786 Split = true;
5787 }
5788
5789 MVT EltVT = ConstVecVT.getVectorElementType();
5790 for (unsigned i = 0, e = Bits.size(); i != e; ++i) {
5791 if (Undefs[i]) {
5792 Ops.append(Split ? 2 : 1, DAG.getUNDEF(EltVT));
5793 continue;
5794 }
5795 const APInt &V = Bits[i];
5796 assert(V.getBitWidth() == VT.getScalarSizeInBits() && "Unexpected sizes")((V.getBitWidth() == VT.getScalarSizeInBits() && "Unexpected sizes"
) ? static_cast<void> (0) : __assert_fail ("V.getBitWidth() == VT.getScalarSizeInBits() && \"Unexpected sizes\""
, "/build/llvm-toolchain-snapshot-13~++20210405022414+5f57793c4fe4/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 5796, __PRETTY_FUNCTION__))
;
5797 if (Split) {
5798 Ops.push_back(DAG.getConstant(V.trunc(32), dl, EltVT));
5799 Ops.push_back(DAG.getConstant(V.lshr(32).trunc(32), dl, EltVT));
5800 } else if (EltVT == MVT::f32) {
5801 APFloat FV(APFloat::IEEEsingle(), V);
5802 Ops.push_back(DAG.getConstantFP(FV, dl, EltVT));
5803 } else if (EltVT == MVT::f64) {
5804 APFloat FV(APFloat::IEEEdouble(), V);
5805 Ops.push_back(DAG.getConstantFP(FV, dl, EltVT));
5806 } else {
5807 Ops.push_back(DAG.getConstant(V, dl, EltVT));
5808 }
5809 }
5810
5811 SDValue ConstsNode = DAG.getBuildVector(ConstVecVT, dl, Ops);
5812 return DAG.getBitcast(VT, ConstsNode);
5813}
5814
5815/// Returns a vector of specified type with all zero elements.
5816static SDValue getZeroVector(MVT VT, const X86Subtarget &Subtarget,
5817 SelectionDAG &DAG, const SDLoc &dl) {
5818 assert((VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector() ||(((VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector
() || VT.getVectorElementType() == MVT::i1) && "Unexpected vector type"
) ? static_cast<void> (0) : __assert_fail ("(VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector() || VT.getVectorElementType() == MVT::i1) && \"Unexpected vector type\""
, "/build/llvm-toolchain-snapshot-13~++20210405022414+5f57793c4fe4/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 5820, __PRETTY_FUNCTION__))
5819 VT.getVectorElementType() == MVT::i1) &&(((VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector
() || VT.getVectorElementType() == MVT::i1) && "Unexpected vector type"
) ? static_cast<void> (0) : __assert_fail ("(VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector() || VT.getVectorElementType() == MVT::i1) && \"Unexpected vector type\""
, "/build/llvm-toolchain-snapshot-13~++20210405022414+5f57793c4fe4/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 5820, __PRETTY_FUNCTION__))
5820 "Unexpected vector type")(((VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector
() || VT.getVectorElementType() == MVT::i1) && "Unexpected vector type"
) ? static_cast<void> (0) : __assert_fail ("(VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector() || VT.getVectorElementType() == MVT::i1) && \"Unexpected vector type\""
, "/build/llvm-toolchain-snapshot-13~++20210405022414+5f57793c4fe4/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 5820, __PRETTY_FUNCTION__))
;
5821
5822 // Try to build SSE/AVX zero vectors as <N x i32> bitcasted to their dest
5823 // type. This ensures they get CSE'd. But if the integer type is not
5824 // available, use a floating-point +0.0 instead.
5825 SDValue Vec;
5826 if (!Subtarget.hasSSE2() && VT.is128BitVector()) {
5827 Vec = DAG.getConstantFP(+0.0, dl, MVT::v4f32);
5828 } else if (VT.isFloatingPoint()) {
5829 Vec = DAG.getConstantFP(+0.0, dl, VT);
5830 } else if (VT.getVectorElementType() == MVT::i1) {
5831 assert((Subtarget.hasBWI() || VT.getVectorNumElements() <= 16) &&(((Subtarget.hasBWI() || VT.getVectorNumElements() <= 16) &&
"Unexpected vector type") ? static_cast<void> (0) : __assert_fail
("(Subtarget.hasBWI() || VT.getVectorNumElements() <= 16) && \"Unexpected vector type\""
, "/build/llvm-toolchain-snapshot-13~++20210405022414+5f57793c4fe4/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 5832, __PRETTY_FUNCTION__))
5832 "Unexpected vector type")(((Subtarget.hasBWI() || VT.getVectorNumElements() <= 16) &&
"Unexpected vector type") ? static_cast<void> (0) : __assert_fail
("(Subtarget.hasBWI() || VT.getVectorNumElements() <= 16) && \"Unexpected vector type\""
, "/build/llvm-toolchain-snapshot-13~++20210405022414+5f57793c4fe4/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 5832, __PRETTY_FUNCTION__))
;
5833 Vec = DAG.getConstant(0, dl, VT);
5834 } else {
5835 unsigned Num32BitElts = VT.getSizeInBits() / 32;
5836 Vec = DAG.getConstant(0, dl, MVT::getVectorVT(MVT::i32, Num32BitElts));
5837 }
5838 return DAG.getBitcast(VT, Vec);
5839}
5840
5841static SDValue extractSubVector(SDValue Vec, unsigned IdxVal, SelectionDAG &DAG,
5842 const SDLoc &dl, unsigned vectorWidth) {
5843 EVT VT = Vec.getValueType();
5844 EVT ElVT = VT.getVectorElementType();
5845 unsigned Factor = VT.getSizeInBits() / vectorWidth;
5846 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
5847 VT.getVectorNumElements() / Factor);
5848
5849 // Extract the relevant vectorWidth bits. Generate an EXTRACT_SUBVECTOR
5850 unsigned ElemsPerChunk = vectorWidth / ElVT.getSizeInBits();
5851 assert(isPowerOf2_32(ElemsPerChunk) && "Elements per chunk not power of 2")((isPowerOf2_32(ElemsPerChunk) && "Elements per chunk not power of 2"
) ? static_cast<void> (0) : __assert_fail ("isPowerOf2_32(ElemsPerChunk) && \"Elements per chunk not power of 2\""
, "/build/llvm-toolchain-snapshot-13~++20210405022414+5f57793c4fe4/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 5851, __PRETTY_FUNCTION__))
;
5852
5853 // This is the index of the first element of the vectorWidth-bit chunk
5854 // we want. Since ElemsPerChunk is a power of 2 just need to clear bits.
5855 IdxVal &= ~(ElemsPerChunk - 1);
5856
5857 // If the input is a buildvector just emit a smaller one.
5858 if (Vec.getOpcode() == ISD::BUILD_VECTOR)
5859 return DAG.getBuildVector(ResultVT, dl,
5860 Vec->ops().slice(IdxVal, ElemsPerChunk));
5861
5862 SDValue VecIdx = DAG.getIntPtrConstant(IdxVal, dl);
5863 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec, VecIdx);
5864}
5865
5866/// Generate a DAG to grab 128-bits from a vector > 128 bits. This
5867/// sets things up to match to an AVX VEXTRACTF128 / VEXTRACTI128
5868/// or AVX-512 VEXTRACTF32x4 / VEXTRACTI32x4
5869/// instructions or a simple subregister reference. Idx is an index in the
5870/// 128 bits we want. It need not be aligned to a 128-bit boundary. That makes
5871/// lowering EXTRACT_VECTOR_ELT operations easier.
5872static SDValue extract128BitVector(SDValue Vec, unsigned IdxVal,
5873 SelectionDAG &DAG, const SDLoc &dl) {
5874 assert((Vec.getValueType().is256BitVector() ||(((Vec.getValueType().is256BitVector() || Vec.getValueType().
is512BitVector()) && "Unexpected vector size!") ? static_cast
<void> (0) : __assert_fail ("(Vec.getValueType().is256BitVector() || Vec.getValueType().is512BitVector()) && \"Unexpected vector size!\""
, "/build/llvm-toolchain-snapshot-13~++20210405022414+5f57793c4fe4/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 5875, __PRETTY_FUNCTION__))
5875 Vec.getValueType().is512BitVector()) && "Unexpected vector size!")(((Vec.getValueType().is256BitVector() || Vec.getValueType().
is512BitVector()) && "Unexpected vector size!") ? static_cast
<void> (0) : __assert_fail ("(Vec.getValueType().is256BitVector() || Vec.getValueType().is512BitVector()) && \"Unexpected vector size!\""
, "/build/llvm-toolchain-snapshot-13~++20210405022414+5f57793c4fe4/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 5875, __PRETTY_FUNCTION__))
;
5876 return extractSubVector(Vec, IdxVal, DAG, dl, 128);
5877}
5878
5879/// Generate a DAG to grab 256-bits from a 512-bit vector.
5880static SDValue extract256BitVector(SDValue Vec, unsigned IdxVal,
5881 SelectionDAG &DAG, const SDLoc &dl) {
5882 assert(Vec.getValueType().is512BitVector() && "Unexpected vector size!")((Vec.getValueType().is512BitVector() && "Unexpected vector size!"
) ? static_cast<void> (0) : __assert_fail ("Vec.getValueType().is512BitVector() && \"Unexpected vector size!\""
, "/build/llvm-toolchain-snapshot-13~++20210405022414+5f57793c4fe4/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 5882, __PRETTY_FUNCTION__))
;
5883 return extractSubVector(Vec, IdxVal, DAG, dl, 256);
5884}
5885
5886static SDValue insertSubVector(SDValue Result, SDValue Vec, unsigned IdxVal,
5887 SelectionDAG &DAG, const SDLoc &dl,
5888 unsigned vectorWidth) {
5889 assert((vectorWidth == 128 || vectorWidth == 256) &&(((vectorWidth == 128 || vectorWidth == 256) && "Unsupported vector width"
) ? static_cast<void> (0) : __assert_fail ("(vectorWidth == 128 || vectorWidth == 256) && \"Unsupported vector width\""
, "/build/llvm-toolchain-snapshot-13~++20210405022414+5f57793c4fe4/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 5890, __PRETTY_FUNCTION__))
5890 "Unsupported vector width")(((vectorWidth == 128 || vectorWidth == 256) && "Unsupported vector width"
) ? static_cast<void> (0) : __assert_fail ("(vectorWidth == 128 || vectorWidth == 256) && \"Unsupported vector width\""
, "/build/llvm-toolchain-snapshot-13~++20210405022414+5f57793c4fe4/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 5890, __PRETTY_FUNCTION__))
;
5891 // Inserting UNDEF is Result
5892 if (Vec.isUndef())
5893 return Result;
5894 EVT VT = Vec.getValueType();
5895 EVT ElVT = VT.getVectorElementType();
5896 EVT ResultVT = Result.getValueType();
5897
5898 // Insert the relevant vectorWidth bits.
5899 unsigned ElemsPerChunk = vectorWidth/ElVT.getSizeInBits();
5900 assert(isPowerOf2_32(ElemsPerChunk) && "Elements per chunk not power of 2")((isPowerOf2_32(ElemsPerChunk) && "Elements per chunk not power of 2"
) ? static_cast<void> (0) : __assert_fail ("isPowerOf2_32(ElemsPerChunk) && \"Elements per chunk not power of 2\""
, "/build/llvm-toolchain-snapshot-13~++20210405022414+5f57793c4fe4/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 5900, __PRETTY_FUNCTION__))
;
5901
5902 // This is the index of the first element of the vectorWidth-bit chunk
5903 // we want. Since ElemsPerChunk is a power of 2 just need to clear bits.
5904 IdxVal &= ~(ElemsPerChunk - 1);
5905
5906 SDValue VecIdx = DAG.getIntPtrConstant(IdxVal, dl);
5907 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec, VecIdx);
5908}
5909
5910/// Generate a DAG to put 128-bits into a vector > 128 bits. This
5911/// sets things up to match to an AVX VINSERTF128/VINSERTI128 or
5912/// AVX-512 VINSERTF32x4/VINSERTI32x4 instructions or a
5913/// simple superregister reference. Idx is an index in the 128 bits
5914/// we want. It need not be aligned to a 128-bit boundary. That makes
5915/// lowering INSERT_VECTOR_ELT operations easier.
5916static SDValue insert128BitVector(SDValue Result, SDValue Vec, unsigned IdxVal,
5917 SelectionDAG &DAG, const SDLoc &dl) {
5918 assert(Vec.getValueType().is128BitVector() && "Unexpected vector size!")((Vec.getValueType().is128BitVector() && "Unexpected vector size!"
) ? static_cast<void> (0) : __assert_fail ("Vec.getValueType().is128BitVector() && \"Unexpected vector size!\""
, "/build/llvm-toolchain-snapshot-13~++20210405022414+5f57793c4fe4/llvm/lib/Target/X86/X86ISelL