Bug Summary

File:llvm/lib/Target/X86/X86ISelLowering.cpp
Warning:line 16874, column 31
Division by zero

Annotated Source Code

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clang -cc1 -cc1 -triple x86_64-pc-linux-gnu -analyze -disable-free -clear-ast-before-backend -disable-llvm-verifier -discard-value-names -main-file-name X86ISelLowering.cpp -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=cplusplus -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -analyzer-config-compatibility-mode=true -mrelocation-model pic -pic-level 2 -mframe-pointer=none -fmath-errno -ffp-contract=on -fno-rounding-math -mconstructor-aliases -funwind-tables=2 -target-cpu x86-64 -tune-cpu generic -debugger-tuning=gdb -ffunction-sections -fdata-sections -fcoverage-compilation-dir=/build/llvm-toolchain-snapshot-14~++20220116100644+5f782d25a742/build-llvm -resource-dir /usr/lib/llvm-14/lib/clang/14.0.0 -D _DEBUG -D _GNU_SOURCE -D __STDC_CONSTANT_MACROS -D __STDC_FORMAT_MACROS -D __STDC_LIMIT_MACROS -I lib/Target/X86 -I /build/llvm-toolchain-snapshot-14~++20220116100644+5f782d25a742/llvm/lib/Target/X86 -I include -I /build/llvm-toolchain-snapshot-14~++20220116100644+5f782d25a742/llvm/include -D _FORTIFY_SOURCE=2 -D NDEBUG -U NDEBUG -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/10/../../../../include/c++/10 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/10/../../../../include/x86_64-linux-gnu/c++/10 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/10/../../../../include/c++/10/backward -internal-isystem /usr/lib/llvm-14/lib/clang/14.0.0/include -internal-isystem /usr/local/include -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/10/../../../../x86_64-linux-gnu/include -internal-externc-isystem /usr/include/x86_64-linux-gnu -internal-externc-isystem /include -internal-externc-isystem /usr/include -fmacro-prefix-map=/build/llvm-toolchain-snapshot-14~++20220116100644+5f782d25a742/build-llvm=build-llvm -fmacro-prefix-map=/build/llvm-toolchain-snapshot-14~++20220116100644+5f782d25a742/= -fcoverage-prefix-map=/build/llvm-toolchain-snapshot-14~++20220116100644+5f782d25a742/build-llvm=build-llvm -fcoverage-prefix-map=/build/llvm-toolchain-snapshot-14~++20220116100644+5f782d25a742/= -O3 -Wno-unused-command-line-argument -Wno-unused-parameter -Wwrite-strings -Wno-missing-field-initializers -Wno-long-long -Wno-maybe-uninitialized -Wno-class-memaccess -Wno-redundant-move -Wno-pessimizing-move -Wno-noexcept-type -Wno-comment -std=c++14 -fdeprecated-macro -fdebug-compilation-dir=/build/llvm-toolchain-snapshot-14~++20220116100644+5f782d25a742/build-llvm -fdebug-prefix-map=/build/llvm-toolchain-snapshot-14~++20220116100644+5f782d25a742/build-llvm=build-llvm -fdebug-prefix-map=/build/llvm-toolchain-snapshot-14~++20220116100644+5f782d25a742/= -ferror-limit 19 -fvisibility hidden -fvisibility-inlines-hidden -stack-protector 2 -fgnuc-version=4.2.1 -fcolor-diagnostics -vectorize-loops -vectorize-slp -analyzer-output=html -analyzer-config stable-report-filename=true -faddrsig -D__GCC_HAVE_DWARF2_CFI_ASM=1 -o /tmp/scan-build-2022-01-16-232930-107970-1 -x c++ /build/llvm-toolchain-snapshot-14~++20220116100644+5f782d25a742/llvm/lib/Target/X86/X86ISelLowering.cpp
1//===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines the interfaces that X86 uses to lower LLVM code into a
10// selection DAG.
11//
12//===----------------------------------------------------------------------===//
13
14#include "X86ISelLowering.h"
15#include "MCTargetDesc/X86ShuffleDecode.h"
16#include "X86.h"
17#include "X86CallingConv.h"
18#include "X86FrameLowering.h"
19#include "X86InstrBuilder.h"
20#include "X86IntrinsicsInfo.h"
21#include "X86MachineFunctionInfo.h"
22#include "X86TargetMachine.h"
23#include "X86TargetObjectFile.h"
24#include "llvm/ADT/SmallBitVector.h"
25#include "llvm/ADT/SmallSet.h"
26#include "llvm/ADT/Statistic.h"
27#include "llvm/ADT/StringExtras.h"
28#include "llvm/ADT/StringSwitch.h"
29#include "llvm/Analysis/BlockFrequencyInfo.h"
30#include "llvm/Analysis/EHPersonalities.h"
31#include "llvm/Analysis/ObjCARCUtil.h"
32#include "llvm/Analysis/ProfileSummaryInfo.h"
33#include "llvm/Analysis/VectorUtils.h"
34#include "llvm/CodeGen/IntrinsicLowering.h"
35#include "llvm/CodeGen/MachineFrameInfo.h"
36#include "llvm/CodeGen/MachineFunction.h"
37#include "llvm/CodeGen/MachineInstrBuilder.h"
38#include "llvm/CodeGen/MachineJumpTableInfo.h"
39#include "llvm/CodeGen/MachineLoopInfo.h"
40#include "llvm/CodeGen/MachineModuleInfo.h"
41#include "llvm/CodeGen/MachineRegisterInfo.h"
42#include "llvm/CodeGen/TargetLowering.h"
43#include "llvm/CodeGen/WinEHFuncInfo.h"
44#include "llvm/IR/CallingConv.h"
45#include "llvm/IR/Constants.h"
46#include "llvm/IR/DerivedTypes.h"
47#include "llvm/IR/DiagnosticInfo.h"
48#include "llvm/IR/Function.h"
49#include "llvm/IR/GlobalAlias.h"
50#include "llvm/IR/GlobalVariable.h"
51#include "llvm/IR/IRBuilder.h"
52#include "llvm/IR/Instructions.h"
53#include "llvm/IR/Intrinsics.h"
54#include "llvm/IR/PatternMatch.h"
55#include "llvm/MC/MCAsmInfo.h"
56#include "llvm/MC/MCContext.h"
57#include "llvm/MC/MCExpr.h"
58#include "llvm/MC/MCSymbol.h"
59#include "llvm/Support/CommandLine.h"
60#include "llvm/Support/Debug.h"
61#include "llvm/Support/ErrorHandling.h"
62#include "llvm/Support/KnownBits.h"
63#include "llvm/Support/MathExtras.h"
64#include "llvm/Target/TargetOptions.h"
65#include <algorithm>
66#include <bitset>
67#include <cctype>
68#include <numeric>
69using namespace llvm;
70
71#define DEBUG_TYPE"x86-isel" "x86-isel"
72
73STATISTIC(NumTailCalls, "Number of tail calls")static llvm::Statistic NumTailCalls = {"x86-isel", "NumTailCalls"
, "Number of tail calls"}
;
74
75static cl::opt<int> ExperimentalPrefInnermostLoopAlignment(
76 "x86-experimental-pref-innermost-loop-alignment", cl::init(4),
77 cl::desc(
78 "Sets the preferable loop alignment for experiments (as log2 bytes) "
79 "for innermost loops only. If specified, this option overrides "
80 "alignment set by x86-experimental-pref-loop-alignment."),
81 cl::Hidden);
82
83static cl::opt<bool> MulConstantOptimization(
84 "mul-constant-optimization", cl::init(true),
85 cl::desc("Replace 'mul x, Const' with more effective instructions like "
86 "SHIFT, LEA, etc."),
87 cl::Hidden);
88
89static cl::opt<bool> ExperimentalUnorderedISEL(
90 "x86-experimental-unordered-atomic-isel", cl::init(false),
91 cl::desc("Use LoadSDNode and StoreSDNode instead of "
92 "AtomicSDNode for unordered atomic loads and "
93 "stores respectively."),
94 cl::Hidden);
95
96/// Call this when the user attempts to do something unsupported, like
97/// returning a double without SSE2 enabled on x86_64. This is not fatal, unlike
98/// report_fatal_error, so calling code should attempt to recover without
99/// crashing.
100static void errorUnsupported(SelectionDAG &DAG, const SDLoc &dl,
101 const char *Msg) {
102 MachineFunction &MF = DAG.getMachineFunction();
103 DAG.getContext()->diagnose(
104 DiagnosticInfoUnsupported(MF.getFunction(), Msg, dl.getDebugLoc()));
105}
106
107X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
108 const X86Subtarget &STI)
109 : TargetLowering(TM), Subtarget(STI) {
110 bool UseX87 = !Subtarget.useSoftFloat() && Subtarget.hasX87();
111 X86ScalarSSEf64 = Subtarget.hasSSE2();
112 X86ScalarSSEf32 = Subtarget.hasSSE1();
113 X86ScalarSSEf16 = Subtarget.hasFP16();
114 MVT PtrVT = MVT::getIntegerVT(TM.getPointerSizeInBits(0));
115
116 // Set up the TargetLowering object.
117
118 // X86 is weird. It always uses i8 for shift amounts and setcc results.
119 setBooleanContents(ZeroOrOneBooleanContent);
120 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
121 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
122
123 // For 64-bit, since we have so many registers, use the ILP scheduler.
124 // For 32-bit, use the register pressure specific scheduling.
125 // For Atom, always use ILP scheduling.
126 if (Subtarget.isAtom())
127 setSchedulingPreference(Sched::ILP);
128 else if (Subtarget.is64Bit())
129 setSchedulingPreference(Sched::ILP);
130 else
131 setSchedulingPreference(Sched::RegPressure);
132 const X86RegisterInfo *RegInfo = Subtarget.getRegisterInfo();
133 setStackPointerRegisterToSaveRestore(RegInfo->getStackRegister());
134
135 // Bypass expensive divides and use cheaper ones.
136 if (TM.getOptLevel() >= CodeGenOpt::Default) {
137 if (Subtarget.hasSlowDivide32())
138 addBypassSlowDiv(32, 8);
139 if (Subtarget.hasSlowDivide64() && Subtarget.is64Bit())
140 addBypassSlowDiv(64, 32);
141 }
142
143 // Setup Windows compiler runtime calls.
144 if (Subtarget.isTargetWindowsMSVC() || Subtarget.isTargetWindowsItanium()) {
145 static const struct {
146 const RTLIB::Libcall Op;
147 const char * const Name;
148 const CallingConv::ID CC;
149 } LibraryCalls[] = {
150 { RTLIB::SDIV_I64, "_alldiv", CallingConv::X86_StdCall },
151 { RTLIB::UDIV_I64, "_aulldiv", CallingConv::X86_StdCall },
152 { RTLIB::SREM_I64, "_allrem", CallingConv::X86_StdCall },
153 { RTLIB::UREM_I64, "_aullrem", CallingConv::X86_StdCall },
154 { RTLIB::MUL_I64, "_allmul", CallingConv::X86_StdCall },
155 };
156
157 for (const auto &LC : LibraryCalls) {
158 setLibcallName(LC.Op, LC.Name);
159 setLibcallCallingConv(LC.Op, LC.CC);
160 }
161 }
162
163 if (Subtarget.getTargetTriple().isOSMSVCRT()) {
164 // MSVCRT doesn't have powi; fall back to pow
165 setLibcallName(RTLIB::POWI_F32, nullptr);
166 setLibcallName(RTLIB::POWI_F64, nullptr);
167 }
168
169 // If we don't have cmpxchg8b(meaing this is a 386/486), limit atomic size to
170 // 32 bits so the AtomicExpandPass will expand it so we don't need cmpxchg8b.
171 // FIXME: Should we be limiting the atomic size on other configs? Default is
172 // 1024.
173 if (!Subtarget.hasCmpxchg8b())
174 setMaxAtomicSizeInBitsSupported(32);
175
176 // Set up the register classes.
177 addRegisterClass(MVT::i8, &X86::GR8RegClass);
178 addRegisterClass(MVT::i16, &X86::GR16RegClass);
179 addRegisterClass(MVT::i32, &X86::GR32RegClass);
180 if (Subtarget.is64Bit())
181 addRegisterClass(MVT::i64, &X86::GR64RegClass);
182
183 for (MVT VT : MVT::integer_valuetypes())
184 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
185
186 // We don't accept any truncstore of integer registers.
187 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
188 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
189 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
190 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
191 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
192 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
193
194 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
195
196 // SETOEQ and SETUNE require checking two conditions.
197 for (auto VT : {MVT::f32, MVT::f64, MVT::f80}) {
198 setCondCodeAction(ISD::SETOEQ, VT, Expand);
199 setCondCodeAction(ISD::SETUNE, VT, Expand);
200 }
201
202 // Integer absolute.
203 if (Subtarget.hasCMov()) {
204 setOperationAction(ISD::ABS , MVT::i16 , Custom);
205 setOperationAction(ISD::ABS , MVT::i32 , Custom);
206 if (Subtarget.is64Bit())
207 setOperationAction(ISD::ABS , MVT::i64 , Custom);
208 }
209
210 // Signed saturation subtraction.
211 setOperationAction(ISD::SSUBSAT , MVT::i8 , Custom);
212 setOperationAction(ISD::SSUBSAT , MVT::i16 , Custom);
213 setOperationAction(ISD::SSUBSAT , MVT::i32 , Custom);
214 if (Subtarget.is64Bit())
215 setOperationAction(ISD::SSUBSAT , MVT::i64 , Custom);
216
217 // Funnel shifts.
218 for (auto ShiftOp : {ISD::FSHL, ISD::FSHR}) {
219 // For slow shld targets we only lower for code size.
220 LegalizeAction ShiftDoubleAction = Subtarget.isSHLDSlow() ? Custom : Legal;
221
222 setOperationAction(ShiftOp , MVT::i8 , Custom);
223 setOperationAction(ShiftOp , MVT::i16 , Custom);
224 setOperationAction(ShiftOp , MVT::i32 , ShiftDoubleAction);
225 if (Subtarget.is64Bit())
226 setOperationAction(ShiftOp , MVT::i64 , ShiftDoubleAction);
227 }
228
229 if (!Subtarget.useSoftFloat()) {
230 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
231 // operation.
232 setOperationAction(ISD::UINT_TO_FP, MVT::i8, Promote);
233 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::i8, Promote);
234 setOperationAction(ISD::UINT_TO_FP, MVT::i16, Promote);
235 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::i16, Promote);
236 // We have an algorithm for SSE2, and we turn this into a 64-bit
237 // FILD or VCVTUSI2SS/SD for other targets.
238 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
239 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::i32, Custom);
240 // We have an algorithm for SSE2->double, and we turn this into a
241 // 64-bit FILD followed by conditional FADD for other targets.
242 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
243 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::i64, Custom);
244
245 // Promote i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
246 // this operation.
247 setOperationAction(ISD::SINT_TO_FP, MVT::i8, Promote);
248 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::i8, Promote);
249 // SSE has no i16 to fp conversion, only i32. We promote in the handler
250 // to allow f80 to use i16 and f64 to use i16 with sse1 only
251 setOperationAction(ISD::SINT_TO_FP, MVT::i16, Custom);
252 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::i16, Custom);
253 // f32 and f64 cases are Legal with SSE1/SSE2, f80 case is not
254 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
255 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::i32, Custom);
256 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
257 // are Legal, f80 is custom lowered.
258 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
259 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::i64, Custom);
260
261 // Promote i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
262 // this operation.
263 setOperationAction(ISD::FP_TO_SINT, MVT::i8, Promote);
264 // FIXME: This doesn't generate invalid exception when it should. PR44019.
265 setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::i8, Promote);
266 setOperationAction(ISD::FP_TO_SINT, MVT::i16, Custom);
267 setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::i16, Custom);
268 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
269 setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::i32, Custom);
270 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
271 // are Legal, f80 is custom lowered.
272 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
273 setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::i64, Custom);
274
275 // Handle FP_TO_UINT by promoting the destination to a larger signed
276 // conversion.
277 setOperationAction(ISD::FP_TO_UINT, MVT::i8, Promote);
278 // FIXME: This doesn't generate invalid exception when it should. PR44019.
279 setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::i8, Promote);
280 setOperationAction(ISD::FP_TO_UINT, MVT::i16, Promote);
281 // FIXME: This doesn't generate invalid exception when it should. PR44019.
282 setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::i16, Promote);
283 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
284 setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::i32, Custom);
285 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
286 setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::i64, Custom);
287
288 setOperationAction(ISD::LRINT, MVT::f32, Custom);
289 setOperationAction(ISD::LRINT, MVT::f64, Custom);
290 setOperationAction(ISD::LLRINT, MVT::f32, Custom);
291 setOperationAction(ISD::LLRINT, MVT::f64, Custom);
292
293 if (!Subtarget.is64Bit()) {
294 setOperationAction(ISD::LRINT, MVT::i64, Custom);
295 setOperationAction(ISD::LLRINT, MVT::i64, Custom);
296 }
297 }
298
299 if (Subtarget.hasSSE2()) {
300 // Custom lowering for saturating float to int conversions.
301 // We handle promotion to larger result types manually.
302 for (MVT VT : { MVT::i8, MVT::i16, MVT::i32 }) {
303 setOperationAction(ISD::FP_TO_UINT_SAT, VT, Custom);
304 setOperationAction(ISD::FP_TO_SINT_SAT, VT, Custom);
305 }
306 if (Subtarget.is64Bit()) {
307 setOperationAction(ISD::FP_TO_UINT_SAT, MVT::i64, Custom);
308 setOperationAction(ISD::FP_TO_SINT_SAT, MVT::i64, Custom);
309 }
310 }
311
312 // Handle address space casts between mixed sized pointers.
313 setOperationAction(ISD::ADDRSPACECAST, MVT::i32, Custom);
314 setOperationAction(ISD::ADDRSPACECAST, MVT::i64, Custom);
315
316 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
317 if (!X86ScalarSSEf64) {
318 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
319 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
320 if (Subtarget.is64Bit()) {
321 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
322 // Without SSE, i64->f64 goes through memory.
323 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
324 }
325 } else if (!Subtarget.is64Bit())
326 setOperationAction(ISD::BITCAST , MVT::i64 , Custom);
327
328 // Scalar integer divide and remainder are lowered to use operations that
329 // produce two results, to match the available instructions. This exposes
330 // the two-result form to trivial CSE, which is able to combine x/y and x%y
331 // into a single instruction.
332 //
333 // Scalar integer multiply-high is also lowered to use two-result
334 // operations, to match the available instructions. However, plain multiply
335 // (low) operations are left as Legal, as there are single-result
336 // instructions for this in x86. Using the two-result multiply instructions
337 // when both high and low results are needed must be arranged by dagcombine.
338 for (auto VT : { MVT::i8, MVT::i16, MVT::i32, MVT::i64 }) {
339 setOperationAction(ISD::MULHS, VT, Expand);
340 setOperationAction(ISD::MULHU, VT, Expand);
341 setOperationAction(ISD::SDIV, VT, Expand);
342 setOperationAction(ISD::UDIV, VT, Expand);
343 setOperationAction(ISD::SREM, VT, Expand);
344 setOperationAction(ISD::UREM, VT, Expand);
345 }
346
347 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
348 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
349 for (auto VT : { MVT::f32, MVT::f64, MVT::f80, MVT::f128,
350 MVT::i8, MVT::i16, MVT::i32, MVT::i64 }) {
351 setOperationAction(ISD::BR_CC, VT, Expand);
352 setOperationAction(ISD::SELECT_CC, VT, Expand);
353 }
354 if (Subtarget.is64Bit())
355 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
356 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
357 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
358 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
359
360 setOperationAction(ISD::FREM , MVT::f32 , Expand);
361 setOperationAction(ISD::FREM , MVT::f64 , Expand);
362 setOperationAction(ISD::FREM , MVT::f80 , Expand);
363 setOperationAction(ISD::FREM , MVT::f128 , Expand);
364
365 if (!Subtarget.useSoftFloat() && Subtarget.hasX87()) {
366 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
367 setOperationAction(ISD::SET_ROUNDING , MVT::Other, Custom);
368 }
369
370 // Promote the i8 variants and force them on up to i32 which has a shorter
371 // encoding.
372 setOperationPromotedToType(ISD::CTTZ , MVT::i8 , MVT::i32);
373 setOperationPromotedToType(ISD::CTTZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
374
375 if (Subtarget.hasBMI()) {
376 // Promote the i16 zero undef variant and force it on up to i32 when tzcnt
377 // is enabled.
378 setOperationPromotedToType(ISD::CTTZ_ZERO_UNDEF, MVT::i16, MVT::i32);
379 } else {
380 setOperationAction(ISD::CTTZ, MVT::i16, Custom);
381 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
382 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Legal);
383 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Legal);
384 if (Subtarget.is64Bit()) {
385 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
386 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Legal);
387 }
388 }
389
390 if (Subtarget.hasLZCNT()) {
391 // When promoting the i8 variants, force them to i32 for a shorter
392 // encoding.
393 setOperationPromotedToType(ISD::CTLZ , MVT::i8 , MVT::i32);
394 setOperationPromotedToType(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
395 } else {
396 for (auto VT : {MVT::i8, MVT::i16, MVT::i32, MVT::i64}) {
397 if (VT == MVT::i64 && !Subtarget.is64Bit())
398 continue;
399 setOperationAction(ISD::CTLZ , VT, Custom);
400 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Custom);
401 }
402 }
403
404 for (auto Op : {ISD::FP16_TO_FP, ISD::STRICT_FP16_TO_FP, ISD::FP_TO_FP16,
405 ISD::STRICT_FP_TO_FP16}) {
406 // Special handling for half-precision floating point conversions.
407 // If we don't have F16C support, then lower half float conversions
408 // into library calls.
409 setOperationAction(
410 Op, MVT::f32,
411 (!Subtarget.useSoftFloat() && Subtarget.hasF16C()) ? Custom : Expand);
412 // There's never any support for operations beyond MVT::f32.
413 setOperationAction(Op, MVT::f64, Expand);
414 setOperationAction(Op, MVT::f80, Expand);
415 setOperationAction(Op, MVT::f128, Expand);
416 }
417
418 setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Expand);
419 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Expand);
420 setLoadExtAction(ISD::EXTLOAD, MVT::f80, MVT::f16, Expand);
421 setLoadExtAction(ISD::EXTLOAD, MVT::f128, MVT::f16, Expand);
422 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
423 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
424 setTruncStoreAction(MVT::f80, MVT::f16, Expand);
425 setTruncStoreAction(MVT::f128, MVT::f16, Expand);
426
427 setOperationAction(ISD::PARITY, MVT::i8, Custom);
428 setOperationAction(ISD::PARITY, MVT::i16, Custom);
429 setOperationAction(ISD::PARITY, MVT::i32, Custom);
430 if (Subtarget.is64Bit())
431 setOperationAction(ISD::PARITY, MVT::i64, Custom);
432 if (Subtarget.hasPOPCNT()) {
433 setOperationPromotedToType(ISD::CTPOP, MVT::i8, MVT::i32);
434 // popcntw is longer to encode than popcntl and also has a false dependency
435 // on the dest that popcntl hasn't had since Cannon Lake.
436 setOperationPromotedToType(ISD::CTPOP, MVT::i16, MVT::i32);
437 } else {
438 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
439 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
440 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
441 if (Subtarget.is64Bit())
442 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
443 else
444 setOperationAction(ISD::CTPOP , MVT::i64 , Custom);
445 }
446
447 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
448
449 if (!Subtarget.hasMOVBE())
450 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
451
452 // X86 wants to expand cmov itself.
453 for (auto VT : { MVT::f32, MVT::f64, MVT::f80, MVT::f128 }) {
454 setOperationAction(ISD::SELECT, VT, Custom);
455 setOperationAction(ISD::SETCC, VT, Custom);
456 setOperationAction(ISD::STRICT_FSETCC, VT, Custom);
457 setOperationAction(ISD::STRICT_FSETCCS, VT, Custom);
458 }
459 for (auto VT : { MVT::i8, MVT::i16, MVT::i32, MVT::i64 }) {
460 if (VT == MVT::i64 && !Subtarget.is64Bit())
461 continue;
462 setOperationAction(ISD::SELECT, VT, Custom);
463 setOperationAction(ISD::SETCC, VT, Custom);
464 }
465
466 // Custom action for SELECT MMX and expand action for SELECT_CC MMX
467 setOperationAction(ISD::SELECT, MVT::x86mmx, Custom);
468 setOperationAction(ISD::SELECT_CC, MVT::x86mmx, Expand);
469
470 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
471 // NOTE: EH_SJLJ_SETJMP/_LONGJMP are not recommended, since
472 // LLVM/Clang supports zero-cost DWARF and SEH exception handling.
473 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
474 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
475 setOperationAction(ISD::EH_SJLJ_SETUP_DISPATCH, MVT::Other, Custom);
476 if (TM.Options.ExceptionModel == ExceptionHandling::SjLj)
477 setLibcallName(RTLIB::UNWIND_RESUME, "_Unwind_SjLj_Resume");
478
479 // Darwin ABI issue.
480 for (auto VT : { MVT::i32, MVT::i64 }) {
481 if (VT == MVT::i64 && !Subtarget.is64Bit())
482 continue;
483 setOperationAction(ISD::ConstantPool , VT, Custom);
484 setOperationAction(ISD::JumpTable , VT, Custom);
485 setOperationAction(ISD::GlobalAddress , VT, Custom);
486 setOperationAction(ISD::GlobalTLSAddress, VT, Custom);
487 setOperationAction(ISD::ExternalSymbol , VT, Custom);
488 setOperationAction(ISD::BlockAddress , VT, Custom);
489 }
490
491 // 64-bit shl, sra, srl (iff 32-bit x86)
492 for (auto VT : { MVT::i32, MVT::i64 }) {
493 if (VT == MVT::i64 && !Subtarget.is64Bit())
494 continue;
495 setOperationAction(ISD::SHL_PARTS, VT, Custom);
496 setOperationAction(ISD::SRA_PARTS, VT, Custom);
497 setOperationAction(ISD::SRL_PARTS, VT, Custom);
498 }
499
500 if (Subtarget.hasSSEPrefetch() || Subtarget.has3DNow())
501 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
502
503 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
504
505 // Expand certain atomics
506 for (auto VT : { MVT::i8, MVT::i16, MVT::i32, MVT::i64 }) {
507 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Custom);
508 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
509 setOperationAction(ISD::ATOMIC_LOAD_ADD, VT, Custom);
510 setOperationAction(ISD::ATOMIC_LOAD_OR, VT, Custom);
511 setOperationAction(ISD::ATOMIC_LOAD_XOR, VT, Custom);
512 setOperationAction(ISD::ATOMIC_LOAD_AND, VT, Custom);
513 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
514 }
515
516 if (!Subtarget.is64Bit())
517 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Custom);
518
519 if (Subtarget.hasCmpxchg16b()) {
520 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, MVT::i128, Custom);
521 }
522
523 // FIXME - use subtarget debug flags
524 if (!Subtarget.isTargetDarwin() && !Subtarget.isTargetELF() &&
525 !Subtarget.isTargetCygMing() && !Subtarget.isTargetWin64() &&
526 TM.Options.ExceptionModel != ExceptionHandling::SjLj) {
527 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
528 }
529
530 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
531 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
532
533 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
534 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
535
536 setOperationAction(ISD::TRAP, MVT::Other, Legal);
537 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
538 if (Subtarget.getTargetTriple().isPS4CPU())
539 setOperationAction(ISD::UBSANTRAP, MVT::Other, Expand);
540 else
541 setOperationAction(ISD::UBSANTRAP, MVT::Other, Legal);
542
543 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
544 setOperationAction(ISD::VASTART , MVT::Other, Custom);
545 setOperationAction(ISD::VAEND , MVT::Other, Expand);
546 bool Is64Bit = Subtarget.is64Bit();
547 setOperationAction(ISD::VAARG, MVT::Other, Is64Bit ? Custom : Expand);
548 setOperationAction(ISD::VACOPY, MVT::Other, Is64Bit ? Custom : Expand);
549
550 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
551 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
552
553 setOperationAction(ISD::DYNAMIC_STACKALLOC, PtrVT, Custom);
554
555 // GC_TRANSITION_START and GC_TRANSITION_END need custom lowering.
556 setOperationAction(ISD::GC_TRANSITION_START, MVT::Other, Custom);
557 setOperationAction(ISD::GC_TRANSITION_END, MVT::Other, Custom);
558
559 if (!Subtarget.useSoftFloat() && X86ScalarSSEf64) {
560 // f32 and f64 use SSE.
561 // Set up the FP register classes.
562 addRegisterClass(MVT::f32, Subtarget.hasAVX512() ? &X86::FR32XRegClass
563 : &X86::FR32RegClass);
564 addRegisterClass(MVT::f64, Subtarget.hasAVX512() ? &X86::FR64XRegClass
565 : &X86::FR64RegClass);
566
567 // Disable f32->f64 extload as we can only generate this in one instruction
568 // under optsize. So its easier to pattern match (fpext (load)) for that
569 // case instead of needing to emit 2 instructions for extload in the
570 // non-optsize case.
571 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f32, Expand);
572
573 for (auto VT : { MVT::f32, MVT::f64 }) {
574 // Use ANDPD to simulate FABS.
575 setOperationAction(ISD::FABS, VT, Custom);
576
577 // Use XORP to simulate FNEG.
578 setOperationAction(ISD::FNEG, VT, Custom);
579
580 // Use ANDPD and ORPD to simulate FCOPYSIGN.
581 setOperationAction(ISD::FCOPYSIGN, VT, Custom);
582
583 // These might be better off as horizontal vector ops.
584 setOperationAction(ISD::FADD, VT, Custom);
585 setOperationAction(ISD::FSUB, VT, Custom);
586
587 // We don't support sin/cos/fmod
588 setOperationAction(ISD::FSIN , VT, Expand);
589 setOperationAction(ISD::FCOS , VT, Expand);
590 setOperationAction(ISD::FSINCOS, VT, Expand);
591 }
592
593 // Lower this to MOVMSK plus an AND.
594 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
595 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
596
597 } else if (!Subtarget.useSoftFloat() && X86ScalarSSEf32 &&
598 (UseX87 || Is64Bit)) {
599 // Use SSE for f32, x87 for f64.
600 // Set up the FP register classes.
601 addRegisterClass(MVT::f32, &X86::FR32RegClass);
602 if (UseX87)
603 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
604
605 // Use ANDPS to simulate FABS.
606 setOperationAction(ISD::FABS , MVT::f32, Custom);
607
608 // Use XORP to simulate FNEG.
609 setOperationAction(ISD::FNEG , MVT::f32, Custom);
610
611 if (UseX87)
612 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
613
614 // Use ANDPS and ORPS to simulate FCOPYSIGN.
615 if (UseX87)
616 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
617 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
618
619 // We don't support sin/cos/fmod
620 setOperationAction(ISD::FSIN , MVT::f32, Expand);
621 setOperationAction(ISD::FCOS , MVT::f32, Expand);
622 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
623
624 if (UseX87) {
625 // Always expand sin/cos functions even though x87 has an instruction.
626 setOperationAction(ISD::FSIN, MVT::f64, Expand);
627 setOperationAction(ISD::FCOS, MVT::f64, Expand);
628 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
629 }
630 } else if (UseX87) {
631 // f32 and f64 in x87.
632 // Set up the FP register classes.
633 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
634 addRegisterClass(MVT::f32, &X86::RFP32RegClass);
635
636 for (auto VT : { MVT::f32, MVT::f64 }) {
637 setOperationAction(ISD::UNDEF, VT, Expand);
638 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
639
640 // Always expand sin/cos functions even though x87 has an instruction.
641 setOperationAction(ISD::FSIN , VT, Expand);
642 setOperationAction(ISD::FCOS , VT, Expand);
643 setOperationAction(ISD::FSINCOS, VT, Expand);
644 }
645 }
646
647 // Expand FP32 immediates into loads from the stack, save special cases.
648 if (isTypeLegal(MVT::f32)) {
649 if (UseX87 && (getRegClassFor(MVT::f32) == &X86::RFP32RegClass)) {
650 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
651 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
652 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
653 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
654 } else // SSE immediates.
655 addLegalFPImmediate(APFloat(+0.0f)); // xorps
656 }
657 // Expand FP64 immediates into loads from the stack, save special cases.
658 if (isTypeLegal(MVT::f64)) {
659 if (UseX87 && getRegClassFor(MVT::f64) == &X86::RFP64RegClass) {
660 addLegalFPImmediate(APFloat(+0.0)); // FLD0
661 addLegalFPImmediate(APFloat(+1.0)); // FLD1
662 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
663 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
664 } else // SSE immediates.
665 addLegalFPImmediate(APFloat(+0.0)); // xorpd
666 }
667 // Handle constrained floating-point operations of scalar.
668 setOperationAction(ISD::STRICT_FADD, MVT::f32, Legal);
669 setOperationAction(ISD::STRICT_FADD, MVT::f64, Legal);
670 setOperationAction(ISD::STRICT_FSUB, MVT::f32, Legal);
671 setOperationAction(ISD::STRICT_FSUB, MVT::f64, Legal);
672 setOperationAction(ISD::STRICT_FMUL, MVT::f32, Legal);
673 setOperationAction(ISD::STRICT_FMUL, MVT::f64, Legal);
674 setOperationAction(ISD::STRICT_FDIV, MVT::f32, Legal);
675 setOperationAction(ISD::STRICT_FDIV, MVT::f64, Legal);
676 setOperationAction(ISD::STRICT_FP_EXTEND, MVT::f64, Legal);
677 setOperationAction(ISD::STRICT_FP_ROUND, MVT::f32, Legal);
678 setOperationAction(ISD::STRICT_FP_ROUND, MVT::f64, Legal);
679 setOperationAction(ISD::STRICT_FSQRT, MVT::f32, Legal);
680 setOperationAction(ISD::STRICT_FSQRT, MVT::f64, Legal);
681
682 // We don't support FMA.
683 setOperationAction(ISD::FMA, MVT::f64, Expand);
684 setOperationAction(ISD::FMA, MVT::f32, Expand);
685
686 // f80 always uses X87.
687 if (UseX87) {
688 addRegisterClass(MVT::f80, &X86::RFP80RegClass);
689 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
690 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
691 {
692 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended());
693 addLegalFPImmediate(TmpFlt); // FLD0
694 TmpFlt.changeSign();
695 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
696
697 bool ignored;
698 APFloat TmpFlt2(+1.0);
699 TmpFlt2.convert(APFloat::x87DoubleExtended(), APFloat::rmNearestTiesToEven,
700 &ignored);
701 addLegalFPImmediate(TmpFlt2); // FLD1
702 TmpFlt2.changeSign();
703 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
704 }
705
706 // Always expand sin/cos functions even though x87 has an instruction.
707 setOperationAction(ISD::FSIN , MVT::f80, Expand);
708 setOperationAction(ISD::FCOS , MVT::f80, Expand);
709 setOperationAction(ISD::FSINCOS, MVT::f80, Expand);
710
711 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
712 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
713 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
714 setOperationAction(ISD::FRINT, MVT::f80, Expand);
715 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
716 setOperationAction(ISD::FMA, MVT::f80, Expand);
717 setOperationAction(ISD::LROUND, MVT::f80, Expand);
718 setOperationAction(ISD::LLROUND, MVT::f80, Expand);
719 setOperationAction(ISD::LRINT, MVT::f80, Custom);
720 setOperationAction(ISD::LLRINT, MVT::f80, Custom);
721
722 // Handle constrained floating-point operations of scalar.
723 setOperationAction(ISD::STRICT_FADD , MVT::f80, Legal);
724 setOperationAction(ISD::STRICT_FSUB , MVT::f80, Legal);
725 setOperationAction(ISD::STRICT_FMUL , MVT::f80, Legal);
726 setOperationAction(ISD::STRICT_FDIV , MVT::f80, Legal);
727 setOperationAction(ISD::STRICT_FSQRT , MVT::f80, Legal);
728 setOperationAction(ISD::STRICT_FP_EXTEND, MVT::f80, Legal);
729 // FIXME: When the target is 64-bit, STRICT_FP_ROUND will be overwritten
730 // as Custom.
731 setOperationAction(ISD::STRICT_FP_ROUND, MVT::f80, Legal);
732 }
733
734 // f128 uses xmm registers, but most operations require libcalls.
735 if (!Subtarget.useSoftFloat() && Subtarget.is64Bit() && Subtarget.hasSSE1()) {
736 addRegisterClass(MVT::f128, Subtarget.hasVLX() ? &X86::VR128XRegClass
737 : &X86::VR128RegClass);
738
739 addLegalFPImmediate(APFloat::getZero(APFloat::IEEEquad())); // xorps
740
741 setOperationAction(ISD::FADD, MVT::f128, LibCall);
742 setOperationAction(ISD::STRICT_FADD, MVT::f128, LibCall);
743 setOperationAction(ISD::FSUB, MVT::f128, LibCall);
744 setOperationAction(ISD::STRICT_FSUB, MVT::f128, LibCall);
745 setOperationAction(ISD::FDIV, MVT::f128, LibCall);
746 setOperationAction(ISD::STRICT_FDIV, MVT::f128, LibCall);
747 setOperationAction(ISD::FMUL, MVT::f128, LibCall);
748 setOperationAction(ISD::STRICT_FMUL, MVT::f128, LibCall);
749 setOperationAction(ISD::FMA, MVT::f128, LibCall);
750 setOperationAction(ISD::STRICT_FMA, MVT::f128, LibCall);
751
752 setOperationAction(ISD::FABS, MVT::f128, Custom);
753 setOperationAction(ISD::FNEG, MVT::f128, Custom);
754 setOperationAction(ISD::FCOPYSIGN, MVT::f128, Custom);
755
756 setOperationAction(ISD::FSIN, MVT::f128, LibCall);
757 setOperationAction(ISD::STRICT_FSIN, MVT::f128, LibCall);
758 setOperationAction(ISD::FCOS, MVT::f128, LibCall);
759 setOperationAction(ISD::STRICT_FCOS, MVT::f128, LibCall);
760 setOperationAction(ISD::FSINCOS, MVT::f128, LibCall);
761 // No STRICT_FSINCOS
762 setOperationAction(ISD::FSQRT, MVT::f128, LibCall);
763 setOperationAction(ISD::STRICT_FSQRT, MVT::f128, LibCall);
764
765 setOperationAction(ISD::FP_EXTEND, MVT::f128, Custom);
766 setOperationAction(ISD::STRICT_FP_EXTEND, MVT::f128, Custom);
767 // We need to custom handle any FP_ROUND with an f128 input, but
768 // LegalizeDAG uses the result type to know when to run a custom handler.
769 // So we have to list all legal floating point result types here.
770 if (isTypeLegal(MVT::f32)) {
771 setOperationAction(ISD::FP_ROUND, MVT::f32, Custom);
772 setOperationAction(ISD::STRICT_FP_ROUND, MVT::f32, Custom);
773 }
774 if (isTypeLegal(MVT::f64)) {
775 setOperationAction(ISD::FP_ROUND, MVT::f64, Custom);
776 setOperationAction(ISD::STRICT_FP_ROUND, MVT::f64, Custom);
777 }
778 if (isTypeLegal(MVT::f80)) {
779 setOperationAction(ISD::FP_ROUND, MVT::f80, Custom);
780 setOperationAction(ISD::STRICT_FP_ROUND, MVT::f80, Custom);
781 }
782
783 setOperationAction(ISD::SETCC, MVT::f128, Custom);
784
785 setLoadExtAction(ISD::EXTLOAD, MVT::f128, MVT::f32, Expand);
786 setLoadExtAction(ISD::EXTLOAD, MVT::f128, MVT::f64, Expand);
787 setLoadExtAction(ISD::EXTLOAD, MVT::f128, MVT::f80, Expand);
788 setTruncStoreAction(MVT::f128, MVT::f32, Expand);
789 setTruncStoreAction(MVT::f128, MVT::f64, Expand);
790 setTruncStoreAction(MVT::f128, MVT::f80, Expand);
791 }
792
793 // Always use a library call for pow.
794 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
795 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
796 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
797 setOperationAction(ISD::FPOW , MVT::f128 , Expand);
798
799 setOperationAction(ISD::FLOG, MVT::f80, Expand);
800 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
801 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
802 setOperationAction(ISD::FEXP, MVT::f80, Expand);
803 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
804 setOperationAction(ISD::FMINNUM, MVT::f80, Expand);
805 setOperationAction(ISD::FMAXNUM, MVT::f80, Expand);
806
807 // Some FP actions are always expanded for vector types.
808 for (auto VT : { MVT::v4f32, MVT::v8f32, MVT::v16f32,
809 MVT::v2f64, MVT::v4f64, MVT::v8f64 }) {
810 setOperationAction(ISD::FSIN, VT, Expand);
811 setOperationAction(ISD::FSINCOS, VT, Expand);
812 setOperationAction(ISD::FCOS, VT, Expand);
813 setOperationAction(ISD::FREM, VT, Expand);
814 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
815 setOperationAction(ISD::FPOW, VT, Expand);
816 setOperationAction(ISD::FLOG, VT, Expand);
817 setOperationAction(ISD::FLOG2, VT, Expand);
818 setOperationAction(ISD::FLOG10, VT, Expand);
819 setOperationAction(ISD::FEXP, VT, Expand);
820 setOperationAction(ISD::FEXP2, VT, Expand);
821 }
822
823 // First set operation action for all vector types to either promote
824 // (for widening) or expand (for scalarization). Then we will selectively
825 // turn on ones that can be effectively codegen'd.
826 for (MVT VT : MVT::fixedlen_vector_valuetypes()) {
827 setOperationAction(ISD::SDIV, VT, Expand);
828 setOperationAction(ISD::UDIV, VT, Expand);
829 setOperationAction(ISD::SREM, VT, Expand);
830 setOperationAction(ISD::UREM, VT, Expand);
831 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT,Expand);
832 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
833 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT,Expand);
834 setOperationAction(ISD::INSERT_SUBVECTOR, VT,Expand);
835 setOperationAction(ISD::FMA, VT, Expand);
836 setOperationAction(ISD::FFLOOR, VT, Expand);
837 setOperationAction(ISD::FCEIL, VT, Expand);
838 setOperationAction(ISD::FTRUNC, VT, Expand);
839 setOperationAction(ISD::FRINT, VT, Expand);
840 setOperationAction(ISD::FNEARBYINT, VT, Expand);
841 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
842 setOperationAction(ISD::MULHS, VT, Expand);
843 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
844 setOperationAction(ISD::MULHU, VT, Expand);
845 setOperationAction(ISD::SDIVREM, VT, Expand);
846 setOperationAction(ISD::UDIVREM, VT, Expand);
847 setOperationAction(ISD::CTPOP, VT, Expand);
848 setOperationAction(ISD::CTTZ, VT, Expand);
849 setOperationAction(ISD::CTLZ, VT, Expand);
850 setOperationAction(ISD::ROTL, VT, Expand);
851 setOperationAction(ISD::ROTR, VT, Expand);
852 setOperationAction(ISD::BSWAP, VT, Expand);
853 setOperationAction(ISD::SETCC, VT, Expand);
854 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
855 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
856 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
857 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
858 setOperationAction(ISD::SIGN_EXTEND_INREG, VT,Expand);
859 setOperationAction(ISD::TRUNCATE, VT, Expand);
860 setOperationAction(ISD::SIGN_EXTEND, VT, Expand);
861 setOperationAction(ISD::ZERO_EXTEND, VT, Expand);
862 setOperationAction(ISD::ANY_EXTEND, VT, Expand);
863 setOperationAction(ISD::SELECT_CC, VT, Expand);
864 for (MVT InnerVT : MVT::fixedlen_vector_valuetypes()) {
865 setTruncStoreAction(InnerVT, VT, Expand);
866
867 setLoadExtAction(ISD::SEXTLOAD, InnerVT, VT, Expand);
868 setLoadExtAction(ISD::ZEXTLOAD, InnerVT, VT, Expand);
869
870 // N.b. ISD::EXTLOAD legality is basically ignored except for i1-like
871 // types, we have to deal with them whether we ask for Expansion or not.
872 // Setting Expand causes its own optimisation problems though, so leave
873 // them legal.
874 if (VT.getVectorElementType() == MVT::i1)
875 setLoadExtAction(ISD::EXTLOAD, InnerVT, VT, Expand);
876
877 // EXTLOAD for MVT::f16 vectors is not legal because f16 vectors are
878 // split/scalarized right now.
879 if (VT.getVectorElementType() == MVT::f16)
880 setLoadExtAction(ISD::EXTLOAD, InnerVT, VT, Expand);
881 }
882 }
883
884 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
885 // with -msoft-float, disable use of MMX as well.
886 if (!Subtarget.useSoftFloat() && Subtarget.hasMMX()) {
887 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
888 // No operations on x86mmx supported, everything uses intrinsics.
889 }
890
891 if (!Subtarget.useSoftFloat() && Subtarget.hasSSE1()) {
892 addRegisterClass(MVT::v4f32, Subtarget.hasVLX() ? &X86::VR128XRegClass
893 : &X86::VR128RegClass);
894
895 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
896 setOperationAction(ISD::FABS, MVT::v4f32, Custom);
897 setOperationAction(ISD::FCOPYSIGN, MVT::v4f32, Custom);
898 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
899 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
900 setOperationAction(ISD::VSELECT, MVT::v4f32, Custom);
901 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
902 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
903
904 setOperationAction(ISD::LOAD, MVT::v2f32, Custom);
905 setOperationAction(ISD::STORE, MVT::v2f32, Custom);
906
907 setOperationAction(ISD::STRICT_FADD, MVT::v4f32, Legal);
908 setOperationAction(ISD::STRICT_FSUB, MVT::v4f32, Legal);
909 setOperationAction(ISD::STRICT_FMUL, MVT::v4f32, Legal);
910 setOperationAction(ISD::STRICT_FDIV, MVT::v4f32, Legal);
911 setOperationAction(ISD::STRICT_FSQRT, MVT::v4f32, Legal);
912 }
913
914 if (!Subtarget.useSoftFloat() && Subtarget.hasSSE2()) {
915 addRegisterClass(MVT::v2f64, Subtarget.hasVLX() ? &X86::VR128XRegClass
916 : &X86::VR128RegClass);
917
918 // FIXME: Unfortunately, -soft-float and -no-implicit-float mean XMM
919 // registers cannot be used even for integer operations.
920 addRegisterClass(MVT::v16i8, Subtarget.hasVLX() ? &X86::VR128XRegClass
921 : &X86::VR128RegClass);
922 addRegisterClass(MVT::v8i16, Subtarget.hasVLX() ? &X86::VR128XRegClass
923 : &X86::VR128RegClass);
924 addRegisterClass(MVT::v4i32, Subtarget.hasVLX() ? &X86::VR128XRegClass
925 : &X86::VR128RegClass);
926 addRegisterClass(MVT::v2i64, Subtarget.hasVLX() ? &X86::VR128XRegClass
927 : &X86::VR128RegClass);
928
929 for (auto VT : { MVT::v2i8, MVT::v4i8, MVT::v8i8,
930 MVT::v2i16, MVT::v4i16, MVT::v2i32 }) {
931 setOperationAction(ISD::SDIV, VT, Custom);
932 setOperationAction(ISD::SREM, VT, Custom);
933 setOperationAction(ISD::UDIV, VT, Custom);
934 setOperationAction(ISD::UREM, VT, Custom);
935 }
936
937 setOperationAction(ISD::MUL, MVT::v2i8, Custom);
938 setOperationAction(ISD::MUL, MVT::v4i8, Custom);
939 setOperationAction(ISD::MUL, MVT::v8i8, Custom);
940
941 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
942 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
943 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
944 setOperationAction(ISD::MULHU, MVT::v4i32, Custom);
945 setOperationAction(ISD::MULHS, MVT::v4i32, Custom);
946 setOperationAction(ISD::MULHU, MVT::v16i8, Custom);
947 setOperationAction(ISD::MULHS, MVT::v16i8, Custom);
948 setOperationAction(ISD::MULHU, MVT::v8i16, Legal);
949 setOperationAction(ISD::MULHS, MVT::v8i16, Legal);
950 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
951
952 setOperationAction(ISD::SMULO, MVT::v16i8, Custom);
953 setOperationAction(ISD::UMULO, MVT::v16i8, Custom);
954
955 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
956 setOperationAction(ISD::FABS, MVT::v2f64, Custom);
957 setOperationAction(ISD::FCOPYSIGN, MVT::v2f64, Custom);
958
959 for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64 }) {
960 setOperationAction(ISD::SMAX, VT, VT == MVT::v8i16 ? Legal : Custom);
961 setOperationAction(ISD::SMIN, VT, VT == MVT::v8i16 ? Legal : Custom);
962 setOperationAction(ISD::UMAX, VT, VT == MVT::v16i8 ? Legal : Custom);
963 setOperationAction(ISD::UMIN, VT, VT == MVT::v16i8 ? Legal : Custom);
964 }
965
966 setOperationAction(ISD::UADDSAT, MVT::v16i8, Legal);
967 setOperationAction(ISD::SADDSAT, MVT::v16i8, Legal);
968 setOperationAction(ISD::USUBSAT, MVT::v16i8, Legal);
969 setOperationAction(ISD::SSUBSAT, MVT::v16i8, Legal);
970 setOperationAction(ISD::UADDSAT, MVT::v8i16, Legal);
971 setOperationAction(ISD::SADDSAT, MVT::v8i16, Legal);
972 setOperationAction(ISD::USUBSAT, MVT::v8i16, Legal);
973 setOperationAction(ISD::SSUBSAT, MVT::v8i16, Legal);
974 setOperationAction(ISD::USUBSAT, MVT::v4i32, Custom);
975 setOperationAction(ISD::USUBSAT, MVT::v2i64, Custom);
976
977 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
978 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
979 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
980 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
981
982 for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64 }) {
983 setOperationAction(ISD::SETCC, VT, Custom);
984 setOperationAction(ISD::STRICT_FSETCC, VT, Custom);
985 setOperationAction(ISD::STRICT_FSETCCS, VT, Custom);
986 setOperationAction(ISD::CTPOP, VT, Custom);
987 setOperationAction(ISD::ABS, VT, Custom);
988
989 // The condition codes aren't legal in SSE/AVX and under AVX512 we use
990 // setcc all the way to isel and prefer SETGT in some isel patterns.
991 setCondCodeAction(ISD::SETLT, VT, Custom);
992 setCondCodeAction(ISD::SETLE, VT, Custom);
993 }
994
995 for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32 }) {
996 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
997 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
998 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
999 setOperationAction(ISD::VSELECT, VT, Custom);
1000 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1001 }
1002
1003 for (auto VT : { MVT::v2f64, MVT::v2i64 }) {
1004 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1005 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1006 setOperationAction(ISD::VSELECT, VT, Custom);
1007
1008 if (VT == MVT::v2i64 && !Subtarget.is64Bit())
1009 continue;
1010
1011 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1012 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1013 }
1014
1015 // Custom lower v2i64 and v2f64 selects.
1016 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
1017 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
1018 setOperationAction(ISD::SELECT, MVT::v4i32, Custom);
1019 setOperationAction(ISD::SELECT, MVT::v8i16, Custom);
1020 setOperationAction(ISD::SELECT, MVT::v16i8, Custom);
1021
1022 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
1023 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Custom);
1024 setOperationAction(ISD::FP_TO_SINT, MVT::v2i32, Custom);
1025 setOperationAction(ISD::FP_TO_UINT, MVT::v2i32, Custom);
1026 setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::v4i32, Legal);
1027 setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::v2i32, Custom);
1028
1029 // Custom legalize these to avoid over promotion or custom promotion.
1030 for (auto VT : {MVT::v2i8, MVT::v4i8, MVT::v8i8, MVT::v2i16, MVT::v4i16}) {
1031 setOperationAction(ISD::FP_TO_SINT, VT, Custom);
1032 setOperationAction(ISD::FP_TO_UINT, VT, Custom);
1033 setOperationAction(ISD::STRICT_FP_TO_SINT, VT, Custom);
1034 setOperationAction(ISD::STRICT_FP_TO_UINT, VT, Custom);
1035 }
1036
1037 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
1038 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::v4i32, Legal);
1039 setOperationAction(ISD::SINT_TO_FP, MVT::v2i32, Custom);
1040 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::v2i32, Custom);
1041
1042 setOperationAction(ISD::UINT_TO_FP, MVT::v2i32, Custom);
1043 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::v2i32, Custom);
1044
1045 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Custom);
1046 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::v4i32, Custom);
1047
1048 // Fast v2f32 UINT_TO_FP( v2i32 ) custom conversion.
1049 setOperationAction(ISD::SINT_TO_FP, MVT::v2f32, Custom);
1050 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::v2f32, Custom);
1051 setOperationAction(ISD::UINT_TO_FP, MVT::v2f32, Custom);
1052 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::v2f32, Custom);
1053
1054 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
1055 setOperationAction(ISD::STRICT_FP_EXTEND, MVT::v2f32, Custom);
1056 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Custom);
1057 setOperationAction(ISD::STRICT_FP_ROUND, MVT::v2f32, Custom);
1058
1059 // We want to legalize this to an f64 load rather than an i64 load on
1060 // 64-bit targets and two 32-bit loads on a 32-bit target. Similar for
1061 // store.
1062 setOperationAction(ISD::LOAD, MVT::v2i32, Custom);
1063 setOperationAction(ISD::LOAD, MVT::v4i16, Custom);
1064 setOperationAction(ISD::LOAD, MVT::v8i8, Custom);
1065 setOperationAction(ISD::STORE, MVT::v2i32, Custom);
1066 setOperationAction(ISD::STORE, MVT::v4i16, Custom);
1067 setOperationAction(ISD::STORE, MVT::v8i8, Custom);
1068
1069 setOperationAction(ISD::BITCAST, MVT::v2i32, Custom);
1070 setOperationAction(ISD::BITCAST, MVT::v4i16, Custom);
1071 setOperationAction(ISD::BITCAST, MVT::v8i8, Custom);
1072 if (!Subtarget.hasAVX512())
1073 setOperationAction(ISD::BITCAST, MVT::v16i1, Custom);
1074
1075 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v2i64, Custom);
1076 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v4i32, Custom);
1077 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v8i16, Custom);
1078
1079 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i64, Custom);
1080
1081 setOperationAction(ISD::TRUNCATE, MVT::v2i8, Custom);
1082 setOperationAction(ISD::TRUNCATE, MVT::v2i16, Custom);
1083 setOperationAction(ISD::TRUNCATE, MVT::v2i32, Custom);
1084 setOperationAction(ISD::TRUNCATE, MVT::v4i8, Custom);
1085 setOperationAction(ISD::TRUNCATE, MVT::v4i16, Custom);
1086 setOperationAction(ISD::TRUNCATE, MVT::v8i8, Custom);
1087
1088 // In the customized shift lowering, the legal v4i32/v2i64 cases
1089 // in AVX2 will be recognized.
1090 for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64 }) {
1091 setOperationAction(ISD::SRL, VT, Custom);
1092 setOperationAction(ISD::SHL, VT, Custom);
1093 setOperationAction(ISD::SRA, VT, Custom);
1094 if (VT == MVT::v2i64) continue;
1095 setOperationAction(ISD::ROTL, VT, Custom);
1096 setOperationAction(ISD::ROTR, VT, Custom);
1097 }
1098
1099 setOperationAction(ISD::FSHL, MVT::v16i8, Custom);
1100 setOperationAction(ISD::FSHR, MVT::v16i8, Custom);
1101 setOperationAction(ISD::FSHL, MVT::v4i32, Custom);
1102 setOperationAction(ISD::FSHR, MVT::v4i32, Custom);
1103
1104 setOperationAction(ISD::STRICT_FSQRT, MVT::v2f64, Legal);
1105 setOperationAction(ISD::STRICT_FADD, MVT::v2f64, Legal);
1106 setOperationAction(ISD::STRICT_FSUB, MVT::v2f64, Legal);
1107 setOperationAction(ISD::STRICT_FMUL, MVT::v2f64, Legal);
1108 setOperationAction(ISD::STRICT_FDIV, MVT::v2f64, Legal);
1109 }
1110
1111 if (!Subtarget.useSoftFloat() && Subtarget.hasSSSE3()) {
1112 setOperationAction(ISD::ABS, MVT::v16i8, Legal);
1113 setOperationAction(ISD::ABS, MVT::v8i16, Legal);
1114 setOperationAction(ISD::ABS, MVT::v4i32, Legal);
1115 setOperationAction(ISD::BITREVERSE, MVT::v16i8, Custom);
1116 setOperationAction(ISD::CTLZ, MVT::v16i8, Custom);
1117 setOperationAction(ISD::CTLZ, MVT::v8i16, Custom);
1118 setOperationAction(ISD::CTLZ, MVT::v4i32, Custom);
1119 setOperationAction(ISD::CTLZ, MVT::v2i64, Custom);
1120
1121 // These might be better off as horizontal vector ops.
1122 setOperationAction(ISD::ADD, MVT::i16, Custom);
1123 setOperationAction(ISD::ADD, MVT::i32, Custom);
1124 setOperationAction(ISD::SUB, MVT::i16, Custom);
1125 setOperationAction(ISD::SUB, MVT::i32, Custom);
1126 }
1127
1128 if (!Subtarget.useSoftFloat() && Subtarget.hasSSE41()) {
1129 for (MVT RoundedTy : {MVT::f32, MVT::f64, MVT::v4f32, MVT::v2f64}) {
1130 setOperationAction(ISD::FFLOOR, RoundedTy, Legal);
1131 setOperationAction(ISD::STRICT_FFLOOR, RoundedTy, Legal);
1132 setOperationAction(ISD::FCEIL, RoundedTy, Legal);
1133 setOperationAction(ISD::STRICT_FCEIL, RoundedTy, Legal);
1134 setOperationAction(ISD::FTRUNC, RoundedTy, Legal);
1135 setOperationAction(ISD::STRICT_FTRUNC, RoundedTy, Legal);
1136 setOperationAction(ISD::FRINT, RoundedTy, Legal);
1137 setOperationAction(ISD::STRICT_FRINT, RoundedTy, Legal);
1138 setOperationAction(ISD::FNEARBYINT, RoundedTy, Legal);
1139 setOperationAction(ISD::STRICT_FNEARBYINT, RoundedTy, Legal);
1140 setOperationAction(ISD::FROUNDEVEN, RoundedTy, Legal);
1141 setOperationAction(ISD::STRICT_FROUNDEVEN, RoundedTy, Legal);
1142
1143 setOperationAction(ISD::FROUND, RoundedTy, Custom);
1144 }
1145
1146 setOperationAction(ISD::SMAX, MVT::v16i8, Legal);
1147 setOperationAction(ISD::SMAX, MVT::v4i32, Legal);
1148 setOperationAction(ISD::UMAX, MVT::v8i16, Legal);
1149 setOperationAction(ISD::UMAX, MVT::v4i32, Legal);
1150 setOperationAction(ISD::SMIN, MVT::v16i8, Legal);
1151 setOperationAction(ISD::SMIN, MVT::v4i32, Legal);
1152 setOperationAction(ISD::UMIN, MVT::v8i16, Legal);
1153 setOperationAction(ISD::UMIN, MVT::v4i32, Legal);
1154
1155 setOperationAction(ISD::UADDSAT, MVT::v4i32, Custom);
1156 setOperationAction(ISD::SADDSAT, MVT::v2i64, Custom);
1157 setOperationAction(ISD::SSUBSAT, MVT::v2i64, Custom);
1158
1159 // FIXME: Do we need to handle scalar-to-vector here?
1160 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
1161
1162 // We directly match byte blends in the backend as they match the VSELECT
1163 // condition form.
1164 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
1165
1166 // SSE41 brings specific instructions for doing vector sign extend even in
1167 // cases where we don't have SRA.
1168 for (auto VT : { MVT::v8i16, MVT::v4i32, MVT::v2i64 }) {
1169 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, VT, Legal);
1170 setOperationAction(ISD::ZERO_EXTEND_VECTOR_INREG, VT, Legal);
1171 }
1172
1173 // SSE41 also has vector sign/zero extending loads, PMOV[SZ]X
1174 for (auto LoadExtOp : { ISD::SEXTLOAD, ISD::ZEXTLOAD }) {
1175 setLoadExtAction(LoadExtOp, MVT::v8i16, MVT::v8i8, Legal);
1176 setLoadExtAction(LoadExtOp, MVT::v4i32, MVT::v4i8, Legal);
1177 setLoadExtAction(LoadExtOp, MVT::v2i64, MVT::v2i8, Legal);
1178 setLoadExtAction(LoadExtOp, MVT::v4i32, MVT::v4i16, Legal);
1179 setLoadExtAction(LoadExtOp, MVT::v2i64, MVT::v2i16, Legal);
1180 setLoadExtAction(LoadExtOp, MVT::v2i64, MVT::v2i32, Legal);
1181 }
1182
1183 if (Subtarget.is64Bit() && !Subtarget.hasAVX512()) {
1184 // We need to scalarize v4i64->v432 uint_to_fp using cvtsi2ss, but we can
1185 // do the pre and post work in the vector domain.
1186 setOperationAction(ISD::UINT_TO_FP, MVT::v4i64, Custom);
1187 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::v4i64, Custom);
1188 // We need to mark SINT_TO_FP as Custom even though we want to expand it
1189 // so that DAG combine doesn't try to turn it into uint_to_fp.
1190 setOperationAction(ISD::SINT_TO_FP, MVT::v4i64, Custom);
1191 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::v4i64, Custom);
1192 }
1193 }
1194
1195 if (!Subtarget.useSoftFloat() && Subtarget.hasSSE42()) {
1196 setOperationAction(ISD::UADDSAT, MVT::v2i64, Custom);
1197 }
1198
1199 if (!Subtarget.useSoftFloat() && Subtarget.hasXOP()) {
1200 for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64,
1201 MVT::v32i8, MVT::v16i16, MVT::v8i32, MVT::v4i64 }) {
1202 setOperationAction(ISD::ROTL, VT, Custom);
1203 setOperationAction(ISD::ROTR, VT, Custom);
1204 }
1205
1206 // XOP can efficiently perform BITREVERSE with VPPERM.
1207 for (auto VT : { MVT::i8, MVT::i16, MVT::i32, MVT::i64 })
1208 setOperationAction(ISD::BITREVERSE, VT, Custom);
1209
1210 for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64,
1211 MVT::v32i8, MVT::v16i16, MVT::v8i32, MVT::v4i64 })
1212 setOperationAction(ISD::BITREVERSE, VT, Custom);
1213 }
1214
1215 if (!Subtarget.useSoftFloat() && Subtarget.hasAVX()) {
1216 bool HasInt256 = Subtarget.hasInt256();
1217
1218 addRegisterClass(MVT::v32i8, Subtarget.hasVLX() ? &X86::VR256XRegClass
1219 : &X86::VR256RegClass);
1220 addRegisterClass(MVT::v16i16, Subtarget.hasVLX() ? &X86::VR256XRegClass
1221 : &X86::VR256RegClass);
1222 addRegisterClass(MVT::v8i32, Subtarget.hasVLX() ? &X86::VR256XRegClass
1223 : &X86::VR256RegClass);
1224 addRegisterClass(MVT::v8f32, Subtarget.hasVLX() ? &X86::VR256XRegClass
1225 : &X86::VR256RegClass);
1226 addRegisterClass(MVT::v4i64, Subtarget.hasVLX() ? &X86::VR256XRegClass
1227 : &X86::VR256RegClass);
1228 addRegisterClass(MVT::v4f64, Subtarget.hasVLX() ? &X86::VR256XRegClass
1229 : &X86::VR256RegClass);
1230
1231 for (auto VT : { MVT::v8f32, MVT::v4f64 }) {
1232 setOperationAction(ISD::FFLOOR, VT, Legal);
1233 setOperationAction(ISD::STRICT_FFLOOR, VT, Legal);
1234 setOperationAction(ISD::FCEIL, VT, Legal);
1235 setOperationAction(ISD::STRICT_FCEIL, VT, Legal);
1236 setOperationAction(ISD::FTRUNC, VT, Legal);
1237 setOperationAction(ISD::STRICT_FTRUNC, VT, Legal);
1238 setOperationAction(ISD::FRINT, VT, Legal);
1239 setOperationAction(ISD::STRICT_FRINT, VT, Legal);
1240 setOperationAction(ISD::FNEARBYINT, VT, Legal);
1241 setOperationAction(ISD::STRICT_FNEARBYINT, VT, Legal);
1242 setOperationAction(ISD::FROUNDEVEN, VT, Legal);
1243 setOperationAction(ISD::STRICT_FROUNDEVEN, VT, Legal);
1244
1245 setOperationAction(ISD::FROUND, VT, Custom);
1246
1247 setOperationAction(ISD::FNEG, VT, Custom);
1248 setOperationAction(ISD::FABS, VT, Custom);
1249 setOperationAction(ISD::FCOPYSIGN, VT, Custom);
1250 }
1251
1252 // (fp_to_int:v8i16 (v8f32 ..)) requires the result type to be promoted
1253 // even though v8i16 is a legal type.
1254 setOperationPromotedToType(ISD::FP_TO_SINT, MVT::v8i16, MVT::v8i32);
1255 setOperationPromotedToType(ISD::FP_TO_UINT, MVT::v8i16, MVT::v8i32);
1256 setOperationPromotedToType(ISD::STRICT_FP_TO_SINT, MVT::v8i16, MVT::v8i32);
1257 setOperationPromotedToType(ISD::STRICT_FP_TO_UINT, MVT::v8i16, MVT::v8i32);
1258 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1259 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Custom);
1260 setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::v8i32, Legal);
1261
1262 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1263 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::v8i32, Legal);
1264
1265 setOperationAction(ISD::STRICT_FP_ROUND, MVT::v4f32, Legal);
1266 setOperationAction(ISD::STRICT_FADD, MVT::v8f32, Legal);
1267 setOperationAction(ISD::STRICT_FADD, MVT::v4f64, Legal);
1268 setOperationAction(ISD::STRICT_FSUB, MVT::v8f32, Legal);
1269 setOperationAction(ISD::STRICT_FSUB, MVT::v4f64, Legal);
1270 setOperationAction(ISD::STRICT_FMUL, MVT::v8f32, Legal);
1271 setOperationAction(ISD::STRICT_FMUL, MVT::v4f64, Legal);
1272 setOperationAction(ISD::STRICT_FDIV, MVT::v8f32, Legal);
1273 setOperationAction(ISD::STRICT_FDIV, MVT::v4f64, Legal);
1274 setOperationAction(ISD::STRICT_FP_EXTEND, MVT::v4f64, Legal);
1275 setOperationAction(ISD::STRICT_FSQRT, MVT::v8f32, Legal);
1276 setOperationAction(ISD::STRICT_FSQRT, MVT::v4f64, Legal);
1277
1278 if (!Subtarget.hasAVX512())
1279 setOperationAction(ISD::BITCAST, MVT::v32i1, Custom);
1280
1281 // In the customized shift lowering, the legal v8i32/v4i64 cases
1282 // in AVX2 will be recognized.
1283 for (auto VT : { MVT::v32i8, MVT::v16i16, MVT::v8i32, MVT::v4i64 }) {
1284 setOperationAction(ISD::SRL, VT, Custom);
1285 setOperationAction(ISD::SHL, VT, Custom);
1286 setOperationAction(ISD::SRA, VT, Custom);
1287 if (VT == MVT::v4i64) continue;
1288 setOperationAction(ISD::ROTL, VT, Custom);
1289 setOperationAction(ISD::ROTR, VT, Custom);
1290 }
1291
1292 setOperationAction(ISD::FSHL, MVT::v32i8, Custom);
1293 setOperationAction(ISD::FSHR, MVT::v32i8, Custom);
1294 setOperationAction(ISD::FSHL, MVT::v8i32, Custom);
1295 setOperationAction(ISD::FSHR, MVT::v8i32, Custom);
1296
1297 // These types need custom splitting if their input is a 128-bit vector.
1298 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i64, Custom);
1299 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom);
1300 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i64, Custom);
1301 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i32, Custom);
1302
1303 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1304 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1305 setOperationAction(ISD::SELECT, MVT::v8i32, Custom);
1306 setOperationAction(ISD::SELECT, MVT::v16i16, Custom);
1307 setOperationAction(ISD::SELECT, MVT::v32i8, Custom);
1308 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1309
1310 for (auto VT : { MVT::v16i16, MVT::v8i32, MVT::v4i64 }) {
1311 setOperationAction(ISD::SIGN_EXTEND, VT, Custom);
1312 setOperationAction(ISD::ZERO_EXTEND, VT, Custom);
1313 setOperationAction(ISD::ANY_EXTEND, VT, Custom);
1314 }
1315
1316 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1317 setOperationAction(ISD::TRUNCATE, MVT::v8i16, Custom);
1318 setOperationAction(ISD::TRUNCATE, MVT::v4i32, Custom);
1319 setOperationAction(ISD::BITREVERSE, MVT::v32i8, Custom);
1320
1321 for (auto VT : { MVT::v32i8, MVT::v16i16, MVT::v8i32, MVT::v4i64 }) {
1322 setOperationAction(ISD::SETCC, VT, Custom);
1323 setOperationAction(ISD::STRICT_FSETCC, VT, Custom);
1324 setOperationAction(ISD::STRICT_FSETCCS, VT, Custom);
1325 setOperationAction(ISD::CTPOP, VT, Custom);
1326 setOperationAction(ISD::CTLZ, VT, Custom);
1327
1328 // The condition codes aren't legal in SSE/AVX and under AVX512 we use
1329 // setcc all the way to isel and prefer SETGT in some isel patterns.
1330 setCondCodeAction(ISD::SETLT, VT, Custom);
1331 setCondCodeAction(ISD::SETLE, VT, Custom);
1332 }
1333
1334 if (Subtarget.hasAnyFMA()) {
1335 for (auto VT : { MVT::f32, MVT::f64, MVT::v4f32, MVT::v8f32,
1336 MVT::v2f64, MVT::v4f64 }) {
1337 setOperationAction(ISD::FMA, VT, Legal);
1338 setOperationAction(ISD::STRICT_FMA, VT, Legal);
1339 }
1340 }
1341
1342 for (auto VT : { MVT::v32i8, MVT::v16i16, MVT::v8i32, MVT::v4i64 }) {
1343 setOperationAction(ISD::ADD, VT, HasInt256 ? Legal : Custom);
1344 setOperationAction(ISD::SUB, VT, HasInt256 ? Legal : Custom);
1345 }
1346
1347 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1348 setOperationAction(ISD::MUL, MVT::v8i32, HasInt256 ? Legal : Custom);
1349 setOperationAction(ISD::MUL, MVT::v16i16, HasInt256 ? Legal : Custom);
1350 setOperationAction(ISD::MUL, MVT::v32i8, Custom);
1351
1352 setOperationAction(ISD::MULHU, MVT::v8i32, Custom);
1353 setOperationAction(ISD::MULHS, MVT::v8i32, Custom);
1354 setOperationAction(ISD::MULHU, MVT::v16i16, HasInt256 ? Legal : Custom);
1355 setOperationAction(ISD::MULHS, MVT::v16i16, HasInt256 ? Legal : Custom);
1356 setOperationAction(ISD::MULHU, MVT::v32i8, Custom);
1357 setOperationAction(ISD::MULHS, MVT::v32i8, Custom);
1358
1359 setOperationAction(ISD::SMULO, MVT::v32i8, Custom);
1360 setOperationAction(ISD::UMULO, MVT::v32i8, Custom);
1361
1362 setOperationAction(ISD::ABS, MVT::v4i64, Custom);
1363 setOperationAction(ISD::SMAX, MVT::v4i64, Custom);
1364 setOperationAction(ISD::UMAX, MVT::v4i64, Custom);
1365 setOperationAction(ISD::SMIN, MVT::v4i64, Custom);
1366 setOperationAction(ISD::UMIN, MVT::v4i64, Custom);
1367
1368 setOperationAction(ISD::UADDSAT, MVT::v32i8, HasInt256 ? Legal : Custom);
1369 setOperationAction(ISD::SADDSAT, MVT::v32i8, HasInt256 ? Legal : Custom);
1370 setOperationAction(ISD::USUBSAT, MVT::v32i8, HasInt256 ? Legal : Custom);
1371 setOperationAction(ISD::SSUBSAT, MVT::v32i8, HasInt256 ? Legal : Custom);
1372 setOperationAction(ISD::UADDSAT, MVT::v16i16, HasInt256 ? Legal : Custom);
1373 setOperationAction(ISD::SADDSAT, MVT::v16i16, HasInt256 ? Legal : Custom);
1374 setOperationAction(ISD::USUBSAT, MVT::v16i16, HasInt256 ? Legal : Custom);
1375 setOperationAction(ISD::SSUBSAT, MVT::v16i16, HasInt256 ? Legal : Custom);
1376 setOperationAction(ISD::UADDSAT, MVT::v8i32, Custom);
1377 setOperationAction(ISD::USUBSAT, MVT::v8i32, Custom);
1378 setOperationAction(ISD::UADDSAT, MVT::v4i64, Custom);
1379 setOperationAction(ISD::USUBSAT, MVT::v4i64, Custom);
1380
1381 for (auto VT : { MVT::v32i8, MVT::v16i16, MVT::v8i32 }) {
1382 setOperationAction(ISD::ABS, VT, HasInt256 ? Legal : Custom);
1383 setOperationAction(ISD::SMAX, VT, HasInt256 ? Legal : Custom);
1384 setOperationAction(ISD::UMAX, VT, HasInt256 ? Legal : Custom);
1385 setOperationAction(ISD::SMIN, VT, HasInt256 ? Legal : Custom);
1386 setOperationAction(ISD::UMIN, VT, HasInt256 ? Legal : Custom);
1387 }
1388
1389 for (auto VT : {MVT::v16i16, MVT::v8i32, MVT::v4i64}) {
1390 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, VT, Custom);
1391 setOperationAction(ISD::ZERO_EXTEND_VECTOR_INREG, VT, Custom);
1392 }
1393
1394 if (HasInt256) {
1395 // The custom lowering for UINT_TO_FP for v8i32 becomes interesting
1396 // when we have a 256bit-wide blend with immediate.
1397 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Custom);
1398 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::v8i32, Custom);
1399
1400 // AVX2 also has wider vector sign/zero extending loads, VPMOV[SZ]X
1401 for (auto LoadExtOp : { ISD::SEXTLOAD, ISD::ZEXTLOAD }) {
1402 setLoadExtAction(LoadExtOp, MVT::v16i16, MVT::v16i8, Legal);
1403 setLoadExtAction(LoadExtOp, MVT::v8i32, MVT::v8i8, Legal);
1404 setLoadExtAction(LoadExtOp, MVT::v4i64, MVT::v4i8, Legal);
1405 setLoadExtAction(LoadExtOp, MVT::v8i32, MVT::v8i16, Legal);
1406 setLoadExtAction(LoadExtOp, MVT::v4i64, MVT::v4i16, Legal);
1407 setLoadExtAction(LoadExtOp, MVT::v4i64, MVT::v4i32, Legal);
1408 }
1409 }
1410
1411 for (auto VT : { MVT::v4i32, MVT::v8i32, MVT::v2i64, MVT::v4i64,
1412 MVT::v4f32, MVT::v8f32, MVT::v2f64, MVT::v4f64 }) {
1413 setOperationAction(ISD::MLOAD, VT, Subtarget.hasVLX() ? Legal : Custom);
1414 setOperationAction(ISD::MSTORE, VT, Legal);
1415 }
1416
1417 // Extract subvector is special because the value type
1418 // (result) is 128-bit but the source is 256-bit wide.
1419 for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64,
1420 MVT::v4f32, MVT::v2f64 }) {
1421 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
1422 }
1423
1424 // Custom lower several nodes for 256-bit types.
1425 for (MVT VT : { MVT::v32i8, MVT::v16i16, MVT::v8i32, MVT::v4i64,
1426 MVT::v8f32, MVT::v4f64 }) {
1427 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1428 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1429 setOperationAction(ISD::VSELECT, VT, Custom);
1430 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1431 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1432 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1433 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Legal);
1434 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1435 setOperationAction(ISD::STORE, VT, Custom);
1436 }
1437
1438 if (HasInt256) {
1439 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1440
1441 // Custom legalize 2x32 to get a little better code.
1442 setOperationAction(ISD::MGATHER, MVT::v2f32, Custom);
1443 setOperationAction(ISD::MGATHER, MVT::v2i32, Custom);
1444
1445 for (auto VT : { MVT::v4i32, MVT::v8i32, MVT::v2i64, MVT::v4i64,
1446 MVT::v4f32, MVT::v8f32, MVT::v2f64, MVT::v4f64 })
1447 setOperationAction(ISD::MGATHER, VT, Custom);
1448 }
1449 }
1450
1451 // This block controls legalization of the mask vector sizes that are
1452 // available with AVX512. 512-bit vectors are in a separate block controlled
1453 // by useAVX512Regs.
1454 if (!Subtarget.useSoftFloat() && Subtarget.hasAVX512()) {
1455 addRegisterClass(MVT::v1i1, &X86::VK1RegClass);
1456 addRegisterClass(MVT::v2i1, &X86::VK2RegClass);
1457 addRegisterClass(MVT::v4i1, &X86::VK4RegClass);
1458 addRegisterClass(MVT::v8i1, &X86::VK8RegClass);
1459 addRegisterClass(MVT::v16i1, &X86::VK16RegClass);
1460
1461 setOperationAction(ISD::SELECT, MVT::v1i1, Custom);
1462 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v1i1, Custom);
1463 setOperationAction(ISD::BUILD_VECTOR, MVT::v1i1, Custom);
1464
1465 setOperationPromotedToType(ISD::FP_TO_SINT, MVT::v8i1, MVT::v8i32);
1466 setOperationPromotedToType(ISD::FP_TO_UINT, MVT::v8i1, MVT::v8i32);
1467 setOperationPromotedToType(ISD::FP_TO_SINT, MVT::v4i1, MVT::v4i32);
1468 setOperationPromotedToType(ISD::FP_TO_UINT, MVT::v4i1, MVT::v4i32);
1469 setOperationPromotedToType(ISD::STRICT_FP_TO_SINT, MVT::v8i1, MVT::v8i32);
1470 setOperationPromotedToType(ISD::STRICT_FP_TO_UINT, MVT::v8i1, MVT::v8i32);
1471 setOperationPromotedToType(ISD::STRICT_FP_TO_SINT, MVT::v4i1, MVT::v4i32);
1472 setOperationPromotedToType(ISD::STRICT_FP_TO_UINT, MVT::v4i1, MVT::v4i32);
1473 setOperationAction(ISD::FP_TO_SINT, MVT::v2i1, Custom);
1474 setOperationAction(ISD::FP_TO_UINT, MVT::v2i1, Custom);
1475 setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::v2i1, Custom);
1476 setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::v2i1, Custom);
1477
1478 // There is no byte sized k-register load or store without AVX512DQ.
1479 if (!Subtarget.hasDQI()) {
1480 setOperationAction(ISD::LOAD, MVT::v1i1, Custom);
1481 setOperationAction(ISD::LOAD, MVT::v2i1, Custom);
1482 setOperationAction(ISD::LOAD, MVT::v4i1, Custom);
1483 setOperationAction(ISD::LOAD, MVT::v8i1, Custom);
1484
1485 setOperationAction(ISD::STORE, MVT::v1i1, Custom);
1486 setOperationAction(ISD::STORE, MVT::v2i1, Custom);
1487 setOperationAction(ISD::STORE, MVT::v4i1, Custom);
1488 setOperationAction(ISD::STORE, MVT::v8i1, Custom);
1489 }
1490
1491 // Extends of v16i1/v8i1/v4i1/v2i1 to 128-bit vectors.
1492 for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64 }) {
1493 setOperationAction(ISD::SIGN_EXTEND, VT, Custom);
1494 setOperationAction(ISD::ZERO_EXTEND, VT, Custom);
1495 setOperationAction(ISD::ANY_EXTEND, VT, Custom);
1496 }
1497
1498 for (auto VT : { MVT::v1i1, MVT::v2i1, MVT::v4i1, MVT::v8i1, MVT::v16i1 })
1499 setOperationAction(ISD::VSELECT, VT, Expand);
1500
1501 for (auto VT : { MVT::v2i1, MVT::v4i1, MVT::v8i1, MVT::v16i1 }) {
1502 setOperationAction(ISD::SETCC, VT, Custom);
1503 setOperationAction(ISD::STRICT_FSETCC, VT, Custom);
1504 setOperationAction(ISD::STRICT_FSETCCS, VT, Custom);
1505 setOperationAction(ISD::SELECT, VT, Custom);
1506 setOperationAction(ISD::TRUNCATE, VT, Custom);
1507
1508 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1509 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1510 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1511 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1512 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1513 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1514 }
1515
1516 for (auto VT : { MVT::v1i1, MVT::v2i1, MVT::v4i1, MVT::v8i1 })
1517 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1518 }
1519
1520 // This block controls legalization for 512-bit operations with 32/64 bit
1521 // elements. 512-bits can be disabled based on prefer-vector-width and
1522 // required-vector-width function attributes.
1523 if (!Subtarget.useSoftFloat() && Subtarget.useAVX512Regs()) {
1524 bool HasBWI = Subtarget.hasBWI();
1525
1526 addRegisterClass(MVT::v16i32, &X86::VR512RegClass);
1527 addRegisterClass(MVT::v16f32, &X86::VR512RegClass);
1528 addRegisterClass(MVT::v8i64, &X86::VR512RegClass);
1529 addRegisterClass(MVT::v8f64, &X86::VR512RegClass);
1530 addRegisterClass(MVT::v32i16, &X86::VR512RegClass);
1531 addRegisterClass(MVT::v64i8, &X86::VR512RegClass);
1532
1533 for (auto ExtType : {ISD::ZEXTLOAD, ISD::SEXTLOAD}) {
1534 setLoadExtAction(ExtType, MVT::v16i32, MVT::v16i8, Legal);
1535 setLoadExtAction(ExtType, MVT::v16i32, MVT::v16i16, Legal);
1536 setLoadExtAction(ExtType, MVT::v8i64, MVT::v8i8, Legal);
1537 setLoadExtAction(ExtType, MVT::v8i64, MVT::v8i16, Legal);
1538 setLoadExtAction(ExtType, MVT::v8i64, MVT::v8i32, Legal);
1539 if (HasBWI)
1540 setLoadExtAction(ExtType, MVT::v32i16, MVT::v32i8, Legal);
1541 }
1542
1543 for (MVT VT : { MVT::v16f32, MVT::v8f64 }) {
1544 setOperationAction(ISD::FNEG, VT, Custom);
1545 setOperationAction(ISD::FABS, VT, Custom);
1546 setOperationAction(ISD::FMA, VT, Legal);
1547 setOperationAction(ISD::STRICT_FMA, VT, Legal);
1548 setOperationAction(ISD::FCOPYSIGN, VT, Custom);
1549 }
1550
1551 for (MVT VT : { MVT::v16i1, MVT::v16i8, MVT::v16i16 }) {
1552 setOperationPromotedToType(ISD::FP_TO_SINT , VT, MVT::v16i32);
1553 setOperationPromotedToType(ISD::FP_TO_UINT , VT, MVT::v16i32);
1554 setOperationPromotedToType(ISD::STRICT_FP_TO_SINT, VT, MVT::v16i32);
1555 setOperationPromotedToType(ISD::STRICT_FP_TO_UINT, VT, MVT::v16i32);
1556 }
1557 setOperationAction(ISD::FP_TO_SINT, MVT::v16i32, Legal);
1558 setOperationAction(ISD::FP_TO_UINT, MVT::v16i32, Legal);
1559 setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::v16i32, Legal);
1560 setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::v16i32, Legal);
1561 setOperationAction(ISD::SINT_TO_FP, MVT::v16i32, Legal);
1562 setOperationAction(ISD::UINT_TO_FP, MVT::v16i32, Legal);
1563 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::v16i32, Legal);
1564 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::v16i32, Legal);
1565
1566 setOperationAction(ISD::STRICT_FADD, MVT::v16f32, Legal);
1567 setOperationAction(ISD::STRICT_FADD, MVT::v8f64, Legal);
1568 setOperationAction(ISD::STRICT_FSUB, MVT::v16f32, Legal);
1569 setOperationAction(ISD::STRICT_FSUB, MVT::v8f64, Legal);
1570 setOperationAction(ISD::STRICT_FMUL, MVT::v16f32, Legal);
1571 setOperationAction(ISD::STRICT_FMUL, MVT::v8f64, Legal);
1572 setOperationAction(ISD::STRICT_FDIV, MVT::v16f32, Legal);
1573 setOperationAction(ISD::STRICT_FDIV, MVT::v8f64, Legal);
1574 setOperationAction(ISD::STRICT_FSQRT, MVT::v16f32, Legal);
1575 setOperationAction(ISD::STRICT_FSQRT, MVT::v8f64, Legal);
1576 setOperationAction(ISD::STRICT_FP_EXTEND, MVT::v8f64, Legal);
1577 setOperationAction(ISD::STRICT_FP_ROUND, MVT::v8f32, Legal);
1578
1579 setTruncStoreAction(MVT::v8i64, MVT::v8i8, Legal);
1580 setTruncStoreAction(MVT::v8i64, MVT::v8i16, Legal);
1581 setTruncStoreAction(MVT::v8i64, MVT::v8i32, Legal);
1582 setTruncStoreAction(MVT::v16i32, MVT::v16i8, Legal);
1583 setTruncStoreAction(MVT::v16i32, MVT::v16i16, Legal);
1584 if (HasBWI)
1585 setTruncStoreAction(MVT::v32i16, MVT::v32i8, Legal);
1586
1587 // With 512-bit vectors and no VLX, we prefer to widen MLOAD/MSTORE
1588 // to 512-bit rather than use the AVX2 instructions so that we can use
1589 // k-masks.
1590 if (!Subtarget.hasVLX()) {
1591 for (auto VT : {MVT::v4i32, MVT::v8i32, MVT::v2i64, MVT::v4i64,
1592 MVT::v4f32, MVT::v8f32, MVT::v2f64, MVT::v4f64}) {
1593 setOperationAction(ISD::MLOAD, VT, Custom);
1594 setOperationAction(ISD::MSTORE, VT, Custom);
1595 }
1596 }
1597
1598 setOperationAction(ISD::TRUNCATE, MVT::v8i32, Legal);
1599 setOperationAction(ISD::TRUNCATE, MVT::v16i16, Legal);
1600 setOperationAction(ISD::TRUNCATE, MVT::v32i8, HasBWI ? Legal : Custom);
1601 setOperationAction(ISD::TRUNCATE, MVT::v16i64, Custom);
1602 setOperationAction(ISD::ZERO_EXTEND, MVT::v32i16, Custom);
1603 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i32, Custom);
1604 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i64, Custom);
1605 setOperationAction(ISD::ANY_EXTEND, MVT::v32i16, Custom);
1606 setOperationAction(ISD::ANY_EXTEND, MVT::v16i32, Custom);
1607 setOperationAction(ISD::ANY_EXTEND, MVT::v8i64, Custom);
1608 setOperationAction(ISD::SIGN_EXTEND, MVT::v32i16, Custom);
1609 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom);
1610 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i64, Custom);
1611
1612 if (HasBWI) {
1613 // Extends from v64i1 masks to 512-bit vectors.
1614 setOperationAction(ISD::SIGN_EXTEND, MVT::v64i8, Custom);
1615 setOperationAction(ISD::ZERO_EXTEND, MVT::v64i8, Custom);
1616 setOperationAction(ISD::ANY_EXTEND, MVT::v64i8, Custom);
1617 }
1618
1619 for (auto VT : { MVT::v16f32, MVT::v8f64 }) {
1620 setOperationAction(ISD::FFLOOR, VT, Legal);
1621 setOperationAction(ISD::STRICT_FFLOOR, VT, Legal);
1622 setOperationAction(ISD::FCEIL, VT, Legal);
1623 setOperationAction(ISD::STRICT_FCEIL, VT, Legal);
1624 setOperationAction(ISD::FTRUNC, VT, Legal);
1625 setOperationAction(ISD::STRICT_FTRUNC, VT, Legal);
1626 setOperationAction(ISD::FRINT, VT, Legal);
1627 setOperationAction(ISD::STRICT_FRINT, VT, Legal);
1628 setOperationAction(ISD::FNEARBYINT, VT, Legal);
1629 setOperationAction(ISD::STRICT_FNEARBYINT, VT, Legal);
1630 setOperationAction(ISD::FROUNDEVEN, VT, Legal);
1631 setOperationAction(ISD::STRICT_FROUNDEVEN, VT, Legal);
1632
1633 setOperationAction(ISD::FROUND, VT, Custom);
1634 }
1635
1636 for (auto VT : {MVT::v32i16, MVT::v16i32, MVT::v8i64}) {
1637 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, VT, Custom);
1638 setOperationAction(ISD::ZERO_EXTEND_VECTOR_INREG, VT, Custom);
1639 }
1640
1641 setOperationAction(ISD::ADD, MVT::v32i16, HasBWI ? Legal : Custom);
1642 setOperationAction(ISD::SUB, MVT::v32i16, HasBWI ? Legal : Custom);
1643 setOperationAction(ISD::ADD, MVT::v64i8, HasBWI ? Legal : Custom);
1644 setOperationAction(ISD::SUB, MVT::v64i8, HasBWI ? Legal : Custom);
1645
1646 setOperationAction(ISD::MUL, MVT::v8i64, Custom);
1647 setOperationAction(ISD::MUL, MVT::v16i32, Legal);
1648 setOperationAction(ISD::MUL, MVT::v32i16, HasBWI ? Legal : Custom);
1649 setOperationAction(ISD::MUL, MVT::v64i8, Custom);
1650
1651 setOperationAction(ISD::MULHU, MVT::v16i32, Custom);
1652 setOperationAction(ISD::MULHS, MVT::v16i32, Custom);
1653 setOperationAction(ISD::MULHS, MVT::v32i16, HasBWI ? Legal : Custom);
1654 setOperationAction(ISD::MULHU, MVT::v32i16, HasBWI ? Legal : Custom);
1655 setOperationAction(ISD::MULHS, MVT::v64i8, Custom);
1656 setOperationAction(ISD::MULHU, MVT::v64i8, Custom);
1657
1658 setOperationAction(ISD::SMULO, MVT::v64i8, Custom);
1659 setOperationAction(ISD::UMULO, MVT::v64i8, Custom);
1660
1661 setOperationAction(ISD::BITREVERSE, MVT::v64i8, Custom);
1662
1663 for (auto VT : { MVT::v64i8, MVT::v32i16, MVT::v16i32, MVT::v8i64 }) {
1664 setOperationAction(ISD::SRL, VT, Custom);
1665 setOperationAction(ISD::SHL, VT, Custom);
1666 setOperationAction(ISD::SRA, VT, Custom);
1667 setOperationAction(ISD::ROTL, VT, Custom);
1668 setOperationAction(ISD::ROTR, VT, Custom);
1669 setOperationAction(ISD::SETCC, VT, Custom);
1670
1671 // The condition codes aren't legal in SSE/AVX and under AVX512 we use
1672 // setcc all the way to isel and prefer SETGT in some isel patterns.
1673 setCondCodeAction(ISD::SETLT, VT, Custom);
1674 setCondCodeAction(ISD::SETLE, VT, Custom);
1675 }
1676 for (auto VT : { MVT::v16i32, MVT::v8i64 }) {
1677 setOperationAction(ISD::SMAX, VT, Legal);
1678 setOperationAction(ISD::UMAX, VT, Legal);
1679 setOperationAction(ISD::SMIN, VT, Legal);
1680 setOperationAction(ISD::UMIN, VT, Legal);
1681 setOperationAction(ISD::ABS, VT, Legal);
1682 setOperationAction(ISD::CTPOP, VT, Custom);
1683 setOperationAction(ISD::STRICT_FSETCC, VT, Custom);
1684 setOperationAction(ISD::STRICT_FSETCCS, VT, Custom);
1685 }
1686
1687 for (auto VT : { MVT::v64i8, MVT::v32i16 }) {
1688 setOperationAction(ISD::ABS, VT, HasBWI ? Legal : Custom);
1689 setOperationAction(ISD::CTPOP, VT, Subtarget.hasBITALG() ? Legal : Custom);
1690 setOperationAction(ISD::CTLZ, VT, Custom);
1691 setOperationAction(ISD::SMAX, VT, HasBWI ? Legal : Custom);
1692 setOperationAction(ISD::UMAX, VT, HasBWI ? Legal : Custom);
1693 setOperationAction(ISD::SMIN, VT, HasBWI ? Legal : Custom);
1694 setOperationAction(ISD::UMIN, VT, HasBWI ? Legal : Custom);
1695 setOperationAction(ISD::UADDSAT, VT, HasBWI ? Legal : Custom);
1696 setOperationAction(ISD::SADDSAT, VT, HasBWI ? Legal : Custom);
1697 setOperationAction(ISD::USUBSAT, VT, HasBWI ? Legal : Custom);
1698 setOperationAction(ISD::SSUBSAT, VT, HasBWI ? Legal : Custom);
1699 }
1700
1701 setOperationAction(ISD::FSHL, MVT::v64i8, Custom);
1702 setOperationAction(ISD::FSHR, MVT::v64i8, Custom);
1703 setOperationAction(ISD::FSHL, MVT::v16i32, Custom);
1704 setOperationAction(ISD::FSHR, MVT::v16i32, Custom);
1705
1706 if (Subtarget.hasDQI()) {
1707 setOperationAction(ISD::SINT_TO_FP, MVT::v8i64, Legal);
1708 setOperationAction(ISD::UINT_TO_FP, MVT::v8i64, Legal);
1709 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::v8i64, Legal);
1710 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::v8i64, Legal);
1711 setOperationAction(ISD::FP_TO_SINT, MVT::v8i64, Legal);
1712 setOperationAction(ISD::FP_TO_UINT, MVT::v8i64, Legal);
1713 setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::v8i64, Legal);
1714 setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::v8i64, Legal);
1715
1716 setOperationAction(ISD::MUL, MVT::v8i64, Legal);
1717 }
1718
1719 if (Subtarget.hasCDI()) {
1720 // NonVLX sub-targets extend 128/256 vectors to use the 512 version.
1721 for (auto VT : { MVT::v16i32, MVT::v8i64} ) {
1722 setOperationAction(ISD::CTLZ, VT, Legal);
1723 }
1724 } // Subtarget.hasCDI()
1725
1726 if (Subtarget.hasVPOPCNTDQ()) {
1727 for (auto VT : { MVT::v16i32, MVT::v8i64 })
1728 setOperationAction(ISD::CTPOP, VT, Legal);
1729 }
1730
1731 // Extract subvector is special because the value type
1732 // (result) is 256-bit but the source is 512-bit wide.
1733 // 128-bit was made Legal under AVX1.
1734 for (auto VT : { MVT::v32i8, MVT::v16i16, MVT::v8i32, MVT::v4i64,
1735 MVT::v8f32, MVT::v4f64 })
1736 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
1737
1738 for (auto VT : { MVT::v64i8, MVT::v32i16, MVT::v16i32, MVT::v8i64,
1739 MVT::v16f32, MVT::v8f64 }) {
1740 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1741 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Legal);
1742 setOperationAction(ISD::SELECT, VT, Custom);
1743 setOperationAction(ISD::VSELECT, VT, Custom);
1744 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1745 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1746 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1747 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1748 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1749 }
1750
1751 for (auto VT : { MVT::v16i32, MVT::v8i64, MVT::v16f32, MVT::v8f64 }) {
1752 setOperationAction(ISD::MLOAD, VT, Legal);
1753 setOperationAction(ISD::MSTORE, VT, Legal);
1754 setOperationAction(ISD::MGATHER, VT, Custom);
1755 setOperationAction(ISD::MSCATTER, VT, Custom);
1756 }
1757 if (HasBWI) {
1758 for (auto VT : { MVT::v64i8, MVT::v32i16 }) {
1759 setOperationAction(ISD::MLOAD, VT, Legal);
1760 setOperationAction(ISD::MSTORE, VT, Legal);
1761 }
1762 } else {
1763 setOperationAction(ISD::STORE, MVT::v32i16, Custom);
1764 setOperationAction(ISD::STORE, MVT::v64i8, Custom);
1765 }
1766
1767 if (Subtarget.hasVBMI2()) {
1768 for (auto VT : { MVT::v8i16, MVT::v4i32, MVT::v2i64,
1769 MVT::v16i16, MVT::v8i32, MVT::v4i64,
1770 MVT::v32i16, MVT::v16i32, MVT::v8i64 }) {
1771 setOperationAction(ISD::FSHL, VT, Custom);
1772 setOperationAction(ISD::FSHR, VT, Custom);
1773 }
1774
1775 setOperationAction(ISD::ROTL, MVT::v32i16, Custom);
1776 setOperationAction(ISD::ROTR, MVT::v8i16, Custom);
1777 setOperationAction(ISD::ROTR, MVT::v16i16, Custom);
1778 setOperationAction(ISD::ROTR, MVT::v32i16, Custom);
1779 }
1780 }// useAVX512Regs
1781
1782 // This block controls legalization for operations that don't have
1783 // pre-AVX512 equivalents. Without VLX we use 512-bit operations for
1784 // narrower widths.
1785 if (!Subtarget.useSoftFloat() && Subtarget.hasAVX512()) {
1786 // These operations are handled on non-VLX by artificially widening in
1787 // isel patterns.
1788
1789 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32,
1790 Subtarget.hasVLX() ? Legal : Custom);
1791 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32,
1792 Subtarget.hasVLX() ? Legal : Custom);
1793 setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::v8i32,
1794 Subtarget.hasVLX() ? Legal : Custom);
1795 setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::v4i32,
1796 Subtarget.hasVLX() ? Legal : Custom);
1797 setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::v2i32, Custom);
1798 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32,
1799 Subtarget.hasVLX() ? Legal : Custom);
1800 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32,
1801 Subtarget.hasVLX() ? Legal : Custom);
1802 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::v8i32,
1803 Subtarget.hasVLX() ? Legal : Custom);
1804 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::v4i32,
1805 Subtarget.hasVLX() ? Legal : Custom);
1806
1807 if (Subtarget.hasDQI()) {
1808 // Fast v2f32 SINT_TO_FP( v2i64 ) custom conversion.
1809 // v2f32 UINT_TO_FP is already custom under SSE2.
1810 assert(isOperationCustom(ISD::UINT_TO_FP, MVT::v2f32) &&(static_cast <bool> (isOperationCustom(ISD::UINT_TO_FP,
MVT::v2f32) && isOperationCustom(ISD::STRICT_UINT_TO_FP
, MVT::v2f32) && "Unexpected operation action!") ? void
(0) : __assert_fail ("isOperationCustom(ISD::UINT_TO_FP, MVT::v2f32) && isOperationCustom(ISD::STRICT_UINT_TO_FP, MVT::v2f32) && \"Unexpected operation action!\""
, "llvm/lib/Target/X86/X86ISelLowering.cpp", 1812, __extension__
__PRETTY_FUNCTION__))
1811 isOperationCustom(ISD::STRICT_UINT_TO_FP, MVT::v2f32) &&(static_cast <bool> (isOperationCustom(ISD::UINT_TO_FP,
MVT::v2f32) && isOperationCustom(ISD::STRICT_UINT_TO_FP
, MVT::v2f32) && "Unexpected operation action!") ? void
(0) : __assert_fail ("isOperationCustom(ISD::UINT_TO_FP, MVT::v2f32) && isOperationCustom(ISD::STRICT_UINT_TO_FP, MVT::v2f32) && \"Unexpected operation action!\""
, "llvm/lib/Target/X86/X86ISelLowering.cpp", 1812, __extension__
__PRETTY_FUNCTION__))
1812 "Unexpected operation action!")(static_cast <bool> (isOperationCustom(ISD::UINT_TO_FP,
MVT::v2f32) && isOperationCustom(ISD::STRICT_UINT_TO_FP
, MVT::v2f32) && "Unexpected operation action!") ? void
(0) : __assert_fail ("isOperationCustom(ISD::UINT_TO_FP, MVT::v2f32) && isOperationCustom(ISD::STRICT_UINT_TO_FP, MVT::v2f32) && \"Unexpected operation action!\""
, "llvm/lib/Target/X86/X86ISelLowering.cpp", 1812, __extension__
__PRETTY_FUNCTION__))
;
1813 // v2i64 FP_TO_S/UINT(v2f32) custom conversion.
1814 setOperationAction(ISD::FP_TO_SINT, MVT::v2f32, Custom);
1815 setOperationAction(ISD::FP_TO_UINT, MVT::v2f32, Custom);
1816 setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::v2f32, Custom);
1817 setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::v2f32, Custom);
1818 }
1819
1820 for (auto VT : { MVT::v2i64, MVT::v4i64 }) {
1821 setOperationAction(ISD::SMAX, VT, Legal);
1822 setOperationAction(ISD::UMAX, VT, Legal);
1823 setOperationAction(ISD::SMIN, VT, Legal);
1824 setOperationAction(ISD::UMIN, VT, Legal);
1825 setOperationAction(ISD::ABS, VT, Legal);
1826 }
1827
1828 for (auto VT : { MVT::v4i32, MVT::v8i32, MVT::v2i64, MVT::v4i64 }) {
1829 setOperationAction(ISD::ROTL, VT, Custom);
1830 setOperationAction(ISD::ROTR, VT, Custom);
1831 }
1832
1833 // Custom legalize 2x32 to get a little better code.
1834 setOperationAction(ISD::MSCATTER, MVT::v2f32, Custom);
1835 setOperationAction(ISD::MSCATTER, MVT::v2i32, Custom);
1836
1837 for (auto VT : { MVT::v4i32, MVT::v8i32, MVT::v2i64, MVT::v4i64,
1838 MVT::v4f32, MVT::v8f32, MVT::v2f64, MVT::v4f64 })
1839 setOperationAction(ISD::MSCATTER, VT, Custom);
1840
1841 if (Subtarget.hasDQI()) {
1842 for (auto VT : { MVT::v2i64, MVT::v4i64 }) {
1843 setOperationAction(ISD::SINT_TO_FP, VT,
1844 Subtarget.hasVLX() ? Legal : Custom);
1845 setOperationAction(ISD::UINT_TO_FP, VT,
1846 Subtarget.hasVLX() ? Legal : Custom);
1847 setOperationAction(ISD::STRICT_SINT_TO_FP, VT,
1848 Subtarget.hasVLX() ? Legal : Custom);
1849 setOperationAction(ISD::STRICT_UINT_TO_FP, VT,
1850 Subtarget.hasVLX() ? Legal : Custom);
1851 setOperationAction(ISD::FP_TO_SINT, VT,
1852 Subtarget.hasVLX() ? Legal : Custom);
1853 setOperationAction(ISD::FP_TO_UINT, VT,
1854 Subtarget.hasVLX() ? Legal : Custom);
1855 setOperationAction(ISD::STRICT_FP_TO_SINT, VT,
1856 Subtarget.hasVLX() ? Legal : Custom);
1857 setOperationAction(ISD::STRICT_FP_TO_UINT, VT,
1858 Subtarget.hasVLX() ? Legal : Custom);
1859 setOperationAction(ISD::MUL, VT, Legal);
1860 }
1861 }
1862
1863 if (Subtarget.hasCDI()) {
1864 for (auto VT : { MVT::v4i32, MVT::v8i32, MVT::v2i64, MVT::v4i64 }) {
1865 setOperationAction(ISD::CTLZ, VT, Legal);
1866 }
1867 } // Subtarget.hasCDI()
1868
1869 if (Subtarget.hasVPOPCNTDQ()) {
1870 for (auto VT : { MVT::v4i32, MVT::v8i32, MVT::v2i64, MVT::v4i64 })
1871 setOperationAction(ISD::CTPOP, VT, Legal);
1872 }
1873 }
1874
1875 // This block control legalization of v32i1/v64i1 which are available with
1876 // AVX512BW. 512-bit v32i16 and v64i8 vector legalization is controlled with
1877 // useBWIRegs.
1878 if (!Subtarget.useSoftFloat() && Subtarget.hasBWI()) {
1879 addRegisterClass(MVT::v32i1, &X86::VK32RegClass);
1880 addRegisterClass(MVT::v64i1, &X86::VK64RegClass);
1881
1882 for (auto VT : { MVT::v32i1, MVT::v64i1 }) {
1883 setOperationAction(ISD::VSELECT, VT, Expand);
1884 setOperationAction(ISD::TRUNCATE, VT, Custom);
1885 setOperationAction(ISD::SETCC, VT, Custom);
1886 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1887 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1888 setOperationAction(ISD::SELECT, VT, Custom);
1889 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1890 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1891 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1892 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1893 }
1894
1895 for (auto VT : { MVT::v16i1, MVT::v32i1 })
1896 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1897
1898 // Extends from v32i1 masks to 256-bit vectors.
1899 setOperationAction(ISD::SIGN_EXTEND, MVT::v32i8, Custom);
1900 setOperationAction(ISD::ZERO_EXTEND, MVT::v32i8, Custom);
1901 setOperationAction(ISD::ANY_EXTEND, MVT::v32i8, Custom);
1902
1903 for (auto VT : { MVT::v32i8, MVT::v16i8, MVT::v16i16, MVT::v8i16 }) {
1904 setOperationAction(ISD::MLOAD, VT, Subtarget.hasVLX() ? Legal : Custom);
1905 setOperationAction(ISD::MSTORE, VT, Subtarget.hasVLX() ? Legal : Custom);
1906 }
1907
1908 // These operations are handled on non-VLX by artificially widening in
1909 // isel patterns.
1910 // TODO: Custom widen in lowering on non-VLX and drop the isel patterns?
1911
1912 if (Subtarget.hasBITALG()) {
1913 for (auto VT : { MVT::v16i8, MVT::v32i8, MVT::v8i16, MVT::v16i16 })
1914 setOperationAction(ISD::CTPOP, VT, Legal);
1915 }
1916 }
1917
1918 if (!Subtarget.useSoftFloat() && Subtarget.hasFP16()) {
1919 auto setGroup = [&] (MVT VT) {
1920 setOperationAction(ISD::FADD, VT, Legal);
1921 setOperationAction(ISD::STRICT_FADD, VT, Legal);
1922 setOperationAction(ISD::FSUB, VT, Legal);
1923 setOperationAction(ISD::STRICT_FSUB, VT, Legal);
1924 setOperationAction(ISD::FMUL, VT, Legal);
1925 setOperationAction(ISD::STRICT_FMUL, VT, Legal);
1926 setOperationAction(ISD::FDIV, VT, Legal);
1927 setOperationAction(ISD::STRICT_FDIV, VT, Legal);
1928 setOperationAction(ISD::FSQRT, VT, Legal);
1929 setOperationAction(ISD::STRICT_FSQRT, VT, Legal);
1930
1931 setOperationAction(ISD::FFLOOR, VT, Legal);
1932 setOperationAction(ISD::STRICT_FFLOOR, VT, Legal);
1933 setOperationAction(ISD::FCEIL, VT, Legal);
1934 setOperationAction(ISD::STRICT_FCEIL, VT, Legal);
1935 setOperationAction(ISD::FTRUNC, VT, Legal);
1936 setOperationAction(ISD::STRICT_FTRUNC, VT, Legal);
1937 setOperationAction(ISD::FRINT, VT, Legal);
1938 setOperationAction(ISD::STRICT_FRINT, VT, Legal);
1939 setOperationAction(ISD::FNEARBYINT, VT, Legal);
1940 setOperationAction(ISD::STRICT_FNEARBYINT, VT, Legal);
1941
1942 setOperationAction(ISD::LOAD, VT, Legal);
1943 setOperationAction(ISD::STORE, VT, Legal);
1944
1945 setOperationAction(ISD::FMA, VT, Legal);
1946 setOperationAction(ISD::STRICT_FMA, VT, Legal);
1947 setOperationAction(ISD::VSELECT, VT, Legal);
1948 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1949 setOperationAction(ISD::SELECT, VT, Custom);
1950
1951 setOperationAction(ISD::FNEG, VT, Custom);
1952 setOperationAction(ISD::FABS, VT, Custom);
1953 setOperationAction(ISD::FCOPYSIGN, VT, Custom);
1954 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1955 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1956 };
1957
1958 // AVX512_FP16 scalar operations
1959 setGroup(MVT::f16);
1960 addRegisterClass(MVT::f16, &X86::FR16XRegClass);
1961 setOperationAction(ISD::SELECT_CC, MVT::f16, Expand);
1962 setOperationAction(ISD::BR_CC, MVT::f16, Expand);
1963 setOperationAction(ISD::SETCC, MVT::f16, Custom);
1964 setOperationAction(ISD::STRICT_FSETCC, MVT::f16, Custom);
1965 setOperationAction(ISD::STRICT_FSETCCS, MVT::f16, Custom);
1966 setOperationAction(ISD::FROUND, MVT::f16, Custom);
1967 setOperationAction(ISD::STRICT_FROUND, MVT::f16, Promote);
1968 setOperationAction(ISD::FROUNDEVEN, MVT::f16, Legal);
1969 setOperationAction(ISD::STRICT_FROUNDEVEN, MVT::f16, Legal);
1970 setOperationAction(ISD::FP_ROUND, MVT::f16, Custom);
1971 setOperationAction(ISD::STRICT_FP_ROUND, MVT::f16, Custom);
1972 setOperationAction(ISD::STRICT_FP_EXTEND, MVT::f32, Legal);
1973 if (isTypeLegal(MVT::f80)) {
1974 setOperationAction(ISD::FP_EXTEND, MVT::f80, Custom);
1975 setOperationAction(ISD::STRICT_FP_EXTEND, MVT::f80, Custom);
1976 }
1977
1978 setCondCodeAction(ISD::SETOEQ, MVT::f16, Expand);
1979 setCondCodeAction(ISD::SETUNE, MVT::f16, Expand);
1980
1981 if (Subtarget.useAVX512Regs()) {
1982 setGroup(MVT::v32f16);
1983 addRegisterClass(MVT::v32f16, &X86::VR512RegClass);
1984 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v32f16, Custom);
1985 setOperationAction(ISD::SINT_TO_FP, MVT::v32i16, Legal);
1986 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::v32i16, Legal);
1987 setOperationAction(ISD::UINT_TO_FP, MVT::v32i16, Legal);
1988 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::v32i16, Legal);
1989 setOperationAction(ISD::STRICT_FP_ROUND, MVT::v16f16, Legal);
1990 setOperationAction(ISD::STRICT_FP_EXTEND, MVT::v16f32, Legal);
1991 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v32f16, Custom);
1992
1993 setOperationAction(ISD::FP_TO_SINT, MVT::v32i16, Custom);
1994 setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::v32i16, Custom);
1995 setOperationAction(ISD::FP_TO_UINT, MVT::v32i16, Custom);
1996 setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::v32i16, Custom);
1997 setOperationPromotedToType(ISD::FP_TO_SINT, MVT::v32i8, MVT::v32i16);
1998 setOperationPromotedToType(ISD::STRICT_FP_TO_SINT, MVT::v32i8,
1999 MVT::v32i16);
2000 setOperationPromotedToType(ISD::FP_TO_UINT, MVT::v32i8, MVT::v32i16);
2001 setOperationPromotedToType(ISD::STRICT_FP_TO_UINT, MVT::v32i8,
2002 MVT::v32i16);
2003 setOperationPromotedToType(ISD::FP_TO_SINT, MVT::v32i1, MVT::v32i16);
2004 setOperationPromotedToType(ISD::STRICT_FP_TO_SINT, MVT::v32i1,
2005 MVT::v32i16);
2006 setOperationPromotedToType(ISD::FP_TO_UINT, MVT::v32i1, MVT::v32i16);
2007 setOperationPromotedToType(ISD::STRICT_FP_TO_UINT, MVT::v32i1,
2008 MVT::v32i16);
2009
2010 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v16f16, Legal);
2011 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v32f16, Legal);
2012 setOperationAction(ISD::CONCAT_VECTORS, MVT::v32f16, Custom);
2013
2014 setLoadExtAction(ISD::EXTLOAD, MVT::v8f64, MVT::v8f16, Legal);
2015 setLoadExtAction(ISD::EXTLOAD, MVT::v16f32, MVT::v16f16, Legal);
2016
2017 setOperationAction(ISD::STRICT_FSETCC, MVT::v32i1, Custom);
2018 setOperationAction(ISD::STRICT_FSETCCS, MVT::v32i1, Custom);
2019 }
2020
2021 if (Subtarget.hasVLX()) {
2022 addRegisterClass(MVT::v8f16, &X86::VR128XRegClass);
2023 addRegisterClass(MVT::v16f16, &X86::VR256XRegClass);
2024 setGroup(MVT::v8f16);
2025 setGroup(MVT::v16f16);
2026
2027 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8f16, Legal);
2028 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16f16, Custom);
2029 setOperationAction(ISD::SINT_TO_FP, MVT::v16i16, Legal);
2030 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::v16i16, Legal);
2031 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Legal);
2032 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::v8i16, Legal);
2033 setOperationAction(ISD::UINT_TO_FP, MVT::v16i16, Legal);
2034 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::v16i16, Legal);
2035 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Legal);
2036 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::v8i16, Legal);
2037
2038 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Custom);
2039 setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::v8i16, Custom);
2040 setOperationAction(ISD::FP_TO_UINT, MVT::v8i16, Custom);
2041 setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::v8i16, Custom);
2042 setOperationAction(ISD::STRICT_FP_ROUND, MVT::v8f16, Legal);
2043 setOperationAction(ISD::STRICT_FP_EXTEND, MVT::v8f32, Legal);
2044
2045 // INSERT_VECTOR_ELT v8f16 extended to VECTOR_SHUFFLE
2046 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8f16, Custom);
2047 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16f16, Custom);
2048
2049 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v8f16, Legal);
2050 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v16f16, Legal);
2051 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16f16, Custom);
2052
2053 setLoadExtAction(ISD::EXTLOAD, MVT::v4f64, MVT::v4f16, Legal);
2054 setLoadExtAction(ISD::EXTLOAD, MVT::v2f64, MVT::v2f16, Legal);
2055 setLoadExtAction(ISD::EXTLOAD, MVT::v8f32, MVT::v8f16, Legal);
2056 setLoadExtAction(ISD::EXTLOAD, MVT::v4f32, MVT::v4f16, Legal);
2057
2058 // Need to custom widen these to prevent scalarization.
2059 setOperationAction(ISD::LOAD, MVT::v4f16, Custom);
2060 setOperationAction(ISD::STORE, MVT::v4f16, Custom);
2061 }
2062
2063 // Support fp16 0 immediate
2064 addLegalFPImmediate(APFloat::getZero(APFloat::IEEEhalf()));
2065 }
2066
2067 if (!Subtarget.useSoftFloat() && Subtarget.hasVLX()) {
2068 setTruncStoreAction(MVT::v4i64, MVT::v4i8, Legal);
2069 setTruncStoreAction(MVT::v4i64, MVT::v4i16, Legal);
2070 setTruncStoreAction(MVT::v4i64, MVT::v4i32, Legal);
2071 setTruncStoreAction(MVT::v8i32, MVT::v8i8, Legal);
2072 setTruncStoreAction(MVT::v8i32, MVT::v8i16, Legal);
2073
2074 setTruncStoreAction(MVT::v2i64, MVT::v2i8, Legal);
2075 setTruncStoreAction(MVT::v2i64, MVT::v2i16, Legal);
2076 setTruncStoreAction(MVT::v2i64, MVT::v2i32, Legal);
2077 setTruncStoreAction(MVT::v4i32, MVT::v4i8, Legal);
2078 setTruncStoreAction(MVT::v4i32, MVT::v4i16, Legal);
2079
2080 if (Subtarget.hasBWI()) {
2081 setTruncStoreAction(MVT::v16i16, MVT::v16i8, Legal);
2082 setTruncStoreAction(MVT::v8i16, MVT::v8i8, Legal);
2083 }
2084
2085 if (Subtarget.hasFP16()) {
2086 // vcvttph2[u]dq v4f16 -> v4i32/64, v2f16 -> v2i32/64
2087 setOperationAction(ISD::FP_TO_SINT, MVT::v2f16, Custom);
2088 setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::v2f16, Custom);
2089 setOperationAction(ISD::FP_TO_UINT, MVT::v2f16, Custom);
2090 setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::v2f16, Custom);
2091 setOperationAction(ISD::FP_TO_SINT, MVT::v4f16, Custom);
2092 setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::v4f16, Custom);
2093 setOperationAction(ISD::FP_TO_UINT, MVT::v4f16, Custom);
2094 setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::v4f16, Custom);
2095 // vcvt[u]dq2ph v4i32/64 -> v4f16, v2i32/64 -> v2f16
2096 setOperationAction(ISD::SINT_TO_FP, MVT::v2f16, Custom);
2097 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::v2f16, Custom);
2098 setOperationAction(ISD::UINT_TO_FP, MVT::v2f16, Custom);
2099 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::v2f16, Custom);
2100 setOperationAction(ISD::SINT_TO_FP, MVT::v4f16, Custom);
2101 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::v4f16, Custom);
2102 setOperationAction(ISD::UINT_TO_FP, MVT::v4f16, Custom);
2103 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::v4f16, Custom);
2104 // vcvtps2phx v4f32 -> v4f16, v2f32 -> v2f16
2105 setOperationAction(ISD::FP_ROUND, MVT::v2f16, Custom);
2106 setOperationAction(ISD::STRICT_FP_ROUND, MVT::v2f16, Custom);
2107 setOperationAction(ISD::FP_ROUND, MVT::v4f16, Custom);
2108 setOperationAction(ISD::STRICT_FP_ROUND, MVT::v4f16, Custom);
2109 // vcvtph2psx v4f16 -> v4f32, v2f16 -> v2f32
2110 setOperationAction(ISD::FP_EXTEND, MVT::v2f16, Custom);
2111 setOperationAction(ISD::STRICT_FP_EXTEND, MVT::v2f16, Custom);
2112 setOperationAction(ISD::FP_EXTEND, MVT::v4f16, Custom);
2113 setOperationAction(ISD::STRICT_FP_EXTEND, MVT::v4f16, Custom);
2114 }
2115
2116 setOperationAction(ISD::TRUNCATE, MVT::v16i32, Custom);
2117 setOperationAction(ISD::TRUNCATE, MVT::v8i64, Custom);
2118 setOperationAction(ISD::TRUNCATE, MVT::v16i64, Custom);
2119 }
2120
2121 if (Subtarget.hasAMXTILE()) {
2122 addRegisterClass(MVT::x86amx, &X86::TILERegClass);
2123 }
2124
2125 // We want to custom lower some of our intrinsics.
2126 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
2127 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
2128 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
2129 if (!Subtarget.is64Bit()) {
2130 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom);
2131 }
2132
2133 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
2134 // handle type legalization for these operations here.
2135 //
2136 // FIXME: We really should do custom legalization for addition and
2137 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
2138 // than generic legalization for 64-bit multiplication-with-overflow, though.
2139 for (auto VT : { MVT::i8, MVT::i16, MVT::i32, MVT::i64 }) {
2140 if (VT == MVT::i64 && !Subtarget.is64Bit())
2141 continue;
2142 // Add/Sub/Mul with overflow operations are custom lowered.
2143 setOperationAction(ISD::SADDO, VT, Custom);
2144 setOperationAction(ISD::UADDO, VT, Custom);
2145 setOperationAction(ISD::SSUBO, VT, Custom);
2146 setOperationAction(ISD::USUBO, VT, Custom);
2147 setOperationAction(ISD::SMULO, VT, Custom);
2148 setOperationAction(ISD::UMULO, VT, Custom);
2149
2150 // Support carry in as value rather than glue.
2151 setOperationAction(ISD::ADDCARRY, VT, Custom);
2152 setOperationAction(ISD::SUBCARRY, VT, Custom);
2153 setOperationAction(ISD::SETCCCARRY, VT, Custom);
2154 setOperationAction(ISD::SADDO_CARRY, VT, Custom);
2155 setOperationAction(ISD::SSUBO_CARRY, VT, Custom);
2156 }
2157
2158 if (!Subtarget.is64Bit()) {
2159 // These libcalls are not available in 32-bit.
2160 setLibcallName(RTLIB::SHL_I128, nullptr);
2161 setLibcallName(RTLIB::SRL_I128, nullptr);
2162 setLibcallName(RTLIB::SRA_I128, nullptr);
2163 setLibcallName(RTLIB::MUL_I128, nullptr);
2164 // The MULO libcall is not part of libgcc, only compiler-rt.
2165 setLibcallName(RTLIB::MULO_I64, nullptr);
2166 }
2167 // The MULO libcall is not part of libgcc, only compiler-rt.
2168 setLibcallName(RTLIB::MULO_I128, nullptr);
2169
2170 // Combine sin / cos into _sincos_stret if it is available.
2171 if (getLibcallName(RTLIB::SINCOS_STRET_F32) != nullptr &&
2172 getLibcallName(RTLIB::SINCOS_STRET_F64) != nullptr) {
2173 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
2174 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
2175 }
2176
2177 if (Subtarget.isTargetWin64()) {
2178 setOperationAction(ISD::SDIV, MVT::i128, Custom);
2179 setOperationAction(ISD::UDIV, MVT::i128, Custom);
2180 setOperationAction(ISD::SREM, MVT::i128, Custom);
2181 setOperationAction(ISD::UREM, MVT::i128, Custom);
2182 setOperationAction(ISD::FP_TO_SINT, MVT::i128, Custom);
2183 setOperationAction(ISD::FP_TO_UINT, MVT::i128, Custom);
2184 setOperationAction(ISD::SINT_TO_FP, MVT::i128, Custom);
2185 setOperationAction(ISD::UINT_TO_FP, MVT::i128, Custom);
2186 setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::i128, Custom);
2187 setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::i128, Custom);
2188 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::i128, Custom);
2189 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::i128, Custom);
2190 }
2191
2192 // On 32 bit MSVC, `fmodf(f32)` is not defined - only `fmod(f64)`
2193 // is. We should promote the value to 64-bits to solve this.
2194 // This is what the CRT headers do - `fmodf` is an inline header
2195 // function casting to f64 and calling `fmod`.
2196 if (Subtarget.is32Bit() &&
2197 (Subtarget.isTargetWindowsMSVC() || Subtarget.isTargetWindowsItanium()))
2198 for (ISD::NodeType Op :
2199 {ISD::FCEIL, ISD::STRICT_FCEIL,
2200 ISD::FCOS, ISD::STRICT_FCOS,
2201 ISD::FEXP, ISD::STRICT_FEXP,
2202 ISD::FFLOOR, ISD::STRICT_FFLOOR,
2203 ISD::FREM, ISD::STRICT_FREM,
2204 ISD::FLOG, ISD::STRICT_FLOG,
2205 ISD::FLOG10, ISD::STRICT_FLOG10,
2206 ISD::FPOW, ISD::STRICT_FPOW,
2207 ISD::FSIN, ISD::STRICT_FSIN})
2208 if (isOperationExpand(Op, MVT::f32))
2209 setOperationAction(Op, MVT::f32, Promote);
2210
2211 // We have target-specific dag combine patterns for the following nodes:
2212 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
2213 setTargetDAGCombine(ISD::SCALAR_TO_VECTOR);
2214 setTargetDAGCombine(ISD::INSERT_VECTOR_ELT);
2215 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
2216 setTargetDAGCombine(ISD::CONCAT_VECTORS);
2217 setTargetDAGCombine(ISD::INSERT_SUBVECTOR);
2218 setTargetDAGCombine(ISD::EXTRACT_SUBVECTOR);
2219 setTargetDAGCombine(ISD::BITCAST);
2220 setTargetDAGCombine(ISD::VSELECT);
2221 setTargetDAGCombine(ISD::SELECT);
2222 setTargetDAGCombine(ISD::SHL);
2223 setTargetDAGCombine(ISD::SRA);
2224 setTargetDAGCombine(ISD::SRL);
2225 setTargetDAGCombine(ISD::OR);
2226 setTargetDAGCombine(ISD::AND);
2227 setTargetDAGCombine(ISD::ADD);
2228 setTargetDAGCombine(ISD::FADD);
2229 setTargetDAGCombine(ISD::FSUB);
2230 setTargetDAGCombine(ISD::FNEG);
2231 setTargetDAGCombine(ISD::FMA);
2232 setTargetDAGCombine(ISD::STRICT_FMA);
2233 setTargetDAGCombine(ISD::FMINNUM);
2234 setTargetDAGCombine(ISD::FMAXNUM);
2235 setTargetDAGCombine(ISD::SUB);
2236 setTargetDAGCombine(ISD::LOAD);
2237 setTargetDAGCombine(ISD::MLOAD);
2238 setTargetDAGCombine(ISD::STORE);
2239 setTargetDAGCombine(ISD::MSTORE);
2240 setTargetDAGCombine(ISD::TRUNCATE);
2241 setTargetDAGCombine(ISD::ZERO_EXTEND);
2242 setTargetDAGCombine(ISD::ANY_EXTEND);
2243 setTargetDAGCombine(ISD::SIGN_EXTEND);
2244 setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
2245 setTargetDAGCombine(ISD::ANY_EXTEND_VECTOR_INREG);
2246 setTargetDAGCombine(ISD::SIGN_EXTEND_VECTOR_INREG);
2247 setTargetDAGCombine(ISD::ZERO_EXTEND_VECTOR_INREG);
2248 setTargetDAGCombine(ISD::SINT_TO_FP);
2249 setTargetDAGCombine(ISD::UINT_TO_FP);
2250 setTargetDAGCombine(ISD::STRICT_SINT_TO_FP);
2251 setTargetDAGCombine(ISD::STRICT_UINT_TO_FP);
2252 setTargetDAGCombine(ISD::SETCC);
2253 setTargetDAGCombine(ISD::MUL);
2254 setTargetDAGCombine(ISD::XOR);
2255 setTargetDAGCombine(ISD::MSCATTER);
2256 setTargetDAGCombine(ISD::MGATHER);
2257 setTargetDAGCombine(ISD::FP16_TO_FP);
2258 setTargetDAGCombine(ISD::FP_EXTEND);
2259 setTargetDAGCombine(ISD::STRICT_FP_EXTEND);
2260 setTargetDAGCombine(ISD::FP_ROUND);
2261
2262 computeRegisterProperties(Subtarget.getRegisterInfo());
2263
2264 MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
2265 MaxStoresPerMemsetOptSize = 8;
2266 MaxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
2267 MaxStoresPerMemcpyOptSize = 4;
2268 MaxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
2269 MaxStoresPerMemmoveOptSize = 4;
2270
2271 // TODO: These control memcmp expansion in CGP and could be raised higher, but
2272 // that needs to benchmarked and balanced with the potential use of vector
2273 // load/store types (PR33329, PR33914).
2274 MaxLoadsPerMemcmp = 2;
2275 MaxLoadsPerMemcmpOptSize = 2;
2276
2277 // Default loop alignment, which can be overridden by -align-loops.
2278 setPrefLoopAlignment(Align(16));
2279
2280 // An out-of-order CPU can speculatively execute past a predictable branch,
2281 // but a conditional move could be stalled by an expensive earlier operation.
2282 PredictableSelectIsExpensive = Subtarget.getSchedModel().isOutOfOrder();
2283 EnableExtLdPromotion = true;
2284 setPrefFunctionAlignment(Align(16));
2285
2286 verifyIntrinsicTables();
2287
2288 // Default to having -disable-strictnode-mutation on
2289 IsStrictFPEnabled = true;
2290}
2291
2292// This has so far only been implemented for 64-bit MachO.
2293bool X86TargetLowering::useLoadStackGuardNode() const {
2294 return Subtarget.isTargetMachO() && Subtarget.is64Bit();
2295}
2296
2297bool X86TargetLowering::useStackGuardXorFP() const {
2298 // Currently only MSVC CRTs XOR the frame pointer into the stack guard value.
2299 return Subtarget.getTargetTriple().isOSMSVCRT() && !Subtarget.isTargetMachO();
2300}
2301
2302SDValue X86TargetLowering::emitStackGuardXorFP(SelectionDAG &DAG, SDValue Val,
2303 const SDLoc &DL) const {
2304 EVT PtrTy = getPointerTy(DAG.getDataLayout());
2305 unsigned XorOp = Subtarget.is64Bit() ? X86::XOR64_FP : X86::XOR32_FP;
2306 MachineSDNode *Node = DAG.getMachineNode(XorOp, DL, PtrTy, Val);
2307 return SDValue(Node, 0);
2308}
2309
2310TargetLoweringBase::LegalizeTypeAction
2311X86TargetLowering::getPreferredVectorAction(MVT VT) const {
2312 if ((VT == MVT::v32i1 || VT == MVT::v64i1) && Subtarget.hasAVX512() &&
2313 !Subtarget.hasBWI())
2314 return TypeSplitVector;
2315
2316 if (!VT.isScalableVector() && VT.getVectorNumElements() != 1 &&
2317 VT.getVectorElementType() != MVT::i1)
2318 return TypeWidenVector;
2319
2320 return TargetLoweringBase::getPreferredVectorAction(VT);
2321}
2322
2323static std::pair<MVT, unsigned>
2324handleMaskRegisterForCallingConv(unsigned NumElts, CallingConv::ID CC,
2325 const X86Subtarget &Subtarget) {
2326 // v2i1/v4i1/v8i1/v16i1 all pass in xmm registers unless the calling
2327 // convention is one that uses k registers.
2328 if (NumElts == 2)
2329 return {MVT::v2i64, 1};
2330 if (NumElts == 4)
2331 return {MVT::v4i32, 1};
2332 if (NumElts == 8 && CC != CallingConv::X86_RegCall &&
2333 CC != CallingConv::Intel_OCL_BI)
2334 return {MVT::v8i16, 1};
2335 if (NumElts == 16 && CC != CallingConv::X86_RegCall &&
2336 CC != CallingConv::Intel_OCL_BI)
2337 return {MVT::v16i8, 1};
2338 // v32i1 passes in ymm unless we have BWI and the calling convention is
2339 // regcall.
2340 if (NumElts == 32 && (!Subtarget.hasBWI() || CC != CallingConv::X86_RegCall))
2341 return {MVT::v32i8, 1};
2342 // Split v64i1 vectors if we don't have v64i8 available.
2343 if (NumElts == 64 && Subtarget.hasBWI() && CC != CallingConv::X86_RegCall) {
2344 if (Subtarget.useAVX512Regs())
2345 return {MVT::v64i8, 1};
2346 return {MVT::v32i8, 2};
2347 }
2348
2349 // Break wide or odd vXi1 vectors into scalars to match avx2 behavior.
2350 if (!isPowerOf2_32(NumElts) || (NumElts == 64 && !Subtarget.hasBWI()) ||
2351 NumElts > 64)
2352 return {MVT::i8, NumElts};
2353
2354 return {MVT::INVALID_SIMPLE_VALUE_TYPE, 0};
2355}
2356
2357MVT X86TargetLowering::getRegisterTypeForCallingConv(LLVMContext &Context,
2358 CallingConv::ID CC,
2359 EVT VT) const {
2360 if (VT.isVector() && VT.getVectorElementType() == MVT::i1 &&
2361 Subtarget.hasAVX512()) {
2362 unsigned NumElts = VT.getVectorNumElements();
2363
2364 MVT RegisterVT;
2365 unsigned NumRegisters;
2366 std::tie(RegisterVT, NumRegisters) =
2367 handleMaskRegisterForCallingConv(NumElts, CC, Subtarget);
2368 if (RegisterVT != MVT::INVALID_SIMPLE_VALUE_TYPE)
2369 return RegisterVT;
2370 }
2371
2372 // v3f16 will be widen to v4f16. But we don't assign register class for v4f16.
2373 // So its default register type is f16. We override the type to v8f16 here.
2374 if (VT == MVT::v3f16 && Subtarget.hasFP16())
2375 return MVT::v8f16;
2376
2377 // We will use more GPRs for f64 and f80 on 32 bits when x87 is disabled.
2378 if ((VT == MVT::f64 || VT == MVT::f80) && !Subtarget.is64Bit() &&
2379 !Subtarget.hasX87())
2380 return MVT::i32;
2381
2382 return TargetLowering::getRegisterTypeForCallingConv(Context, CC, VT);
2383}
2384
2385unsigned X86TargetLowering::getNumRegistersForCallingConv(LLVMContext &Context,
2386 CallingConv::ID CC,
2387 EVT VT) const {
2388 if (VT.isVector() && VT.getVectorElementType() == MVT::i1 &&
2389 Subtarget.hasAVX512()) {
2390 unsigned NumElts = VT.getVectorNumElements();
2391
2392 MVT RegisterVT;
2393 unsigned NumRegisters;
2394 std::tie(RegisterVT, NumRegisters) =
2395 handleMaskRegisterForCallingConv(NumElts, CC, Subtarget);
2396 if (RegisterVT != MVT::INVALID_SIMPLE_VALUE_TYPE)
2397 return NumRegisters;
2398 }
2399
2400 // v3f16 will be widen to v4f16. But we don't assign register class for v4f16.
2401 // So its default register number is 3. We override the number to 1 here.
2402 if (VT == MVT::v3f16 && Subtarget.hasFP16())
2403 return 1;
2404
2405 // We have to split f64 to 2 registers and f80 to 3 registers on 32 bits if
2406 // x87 is disabled.
2407 if (!Subtarget.is64Bit() && !Subtarget.hasX87()) {
2408 if (VT == MVT::f64)
2409 return 2;
2410 if (VT == MVT::f80)
2411 return 3;
2412 }
2413
2414 return TargetLowering::getNumRegistersForCallingConv(Context, CC, VT);
2415}
2416
2417unsigned X86TargetLowering::getVectorTypeBreakdownForCallingConv(
2418 LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT,
2419 unsigned &NumIntermediates, MVT &RegisterVT) const {
2420 // Break wide or odd vXi1 vectors into scalars to match avx2 behavior.
2421 if (VT.isVector() && VT.getVectorElementType() == MVT::i1 &&
2422 Subtarget.hasAVX512() &&
2423 (!isPowerOf2_32(VT.getVectorNumElements()) ||
2424 (VT.getVectorNumElements() == 64 && !Subtarget.hasBWI()) ||
2425 VT.getVectorNumElements() > 64)) {
2426 RegisterVT = MVT::i8;
2427 IntermediateVT = MVT::i1;
2428 NumIntermediates = VT.getVectorNumElements();
2429 return NumIntermediates;
2430 }
2431
2432 // Split v64i1 vectors if we don't have v64i8 available.
2433 if (VT == MVT::v64i1 && Subtarget.hasBWI() && !Subtarget.useAVX512Regs() &&
2434 CC != CallingConv::X86_RegCall) {
2435 RegisterVT = MVT::v32i8;
2436 IntermediateVT = MVT::v32i1;
2437 NumIntermediates = 2;
2438 return 2;
2439 }
2440
2441 return TargetLowering::getVectorTypeBreakdownForCallingConv(Context, CC, VT, IntermediateVT,
2442 NumIntermediates, RegisterVT);
2443}
2444
2445EVT X86TargetLowering::getSetCCResultType(const DataLayout &DL,
2446 LLVMContext& Context,
2447 EVT VT) const {
2448 if (!VT.isVector())
2449 return MVT::i8;
2450
2451 if (Subtarget.hasAVX512()) {
2452 // Figure out what this type will be legalized to.
2453 EVT LegalVT = VT;
2454 while (getTypeAction(Context, LegalVT) != TypeLegal)
2455 LegalVT = getTypeToTransformTo(Context, LegalVT);
2456
2457 // If we got a 512-bit vector then we'll definitely have a vXi1 compare.
2458 if (LegalVT.getSimpleVT().is512BitVector())
2459 return EVT::getVectorVT(Context, MVT::i1, VT.getVectorElementCount());
2460
2461 if (LegalVT.getSimpleVT().isVector() && Subtarget.hasVLX()) {
2462 // If we legalized to less than a 512-bit vector, then we will use a vXi1
2463 // compare for vXi32/vXi64 for sure. If we have BWI we will also support
2464 // vXi16/vXi8.
2465 MVT EltVT = LegalVT.getSimpleVT().getVectorElementType();
2466 if (Subtarget.hasBWI() || EltVT.getSizeInBits() >= 32)
2467 return EVT::getVectorVT(Context, MVT::i1, VT.getVectorElementCount());
2468 }
2469 }
2470
2471 return VT.changeVectorElementTypeToInteger();
2472}
2473
2474/// Helper for getByValTypeAlignment to determine
2475/// the desired ByVal argument alignment.
2476static void getMaxByValAlign(Type *Ty, Align &MaxAlign) {
2477 if (MaxAlign == 16)
2478 return;
2479 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
2480 if (VTy->getPrimitiveSizeInBits().getFixedSize() == 128)
2481 MaxAlign = Align(16);
2482 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
2483 Align EltAlign;
2484 getMaxByValAlign(ATy->getElementType(), EltAlign);
2485 if (EltAlign > MaxAlign)
2486 MaxAlign = EltAlign;
2487 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
2488 for (auto *EltTy : STy->elements()) {
2489 Align EltAlign;
2490 getMaxByValAlign(EltTy, EltAlign);
2491 if (EltAlign > MaxAlign)
2492 MaxAlign = EltAlign;
2493 if (MaxAlign == 16)
2494 break;
2495 }
2496 }
2497}
2498
2499/// Return the desired alignment for ByVal aggregate
2500/// function arguments in the caller parameter area. For X86, aggregates
2501/// that contain SSE vectors are placed at 16-byte boundaries while the rest
2502/// are at 4-byte boundaries.
2503uint64_t X86TargetLowering::getByValTypeAlignment(Type *Ty,
2504 const DataLayout &DL) const {
2505 if (Subtarget.is64Bit()) {
2506 // Max of 8 and alignment of type.
2507 Align TyAlign = DL.getABITypeAlign(Ty);
2508 if (TyAlign > 8)
2509 return TyAlign.value();
2510 return 8;
2511 }
2512
2513 Align Alignment(4);
2514 if (Subtarget.hasSSE1())
2515 getMaxByValAlign(Ty, Alignment);
2516 return Alignment.value();
2517}
2518
2519/// It returns EVT::Other if the type should be determined using generic
2520/// target-independent logic.
2521/// For vector ops we check that the overall size isn't larger than our
2522/// preferred vector width.
2523EVT X86TargetLowering::getOptimalMemOpType(
2524 const MemOp &Op, const AttributeList &FuncAttributes) const {
2525 if (!FuncAttributes.hasFnAttr(Attribute::NoImplicitFloat)) {
2526 if (Op.size() >= 16 &&
2527 (!Subtarget.isUnalignedMem16Slow() || Op.isAligned(Align(16)))) {
2528 // FIXME: Check if unaligned 64-byte accesses are slow.
2529 if (Op.size() >= 64 && Subtarget.hasAVX512() &&
2530 (Subtarget.getPreferVectorWidth() >= 512)) {
2531 return Subtarget.hasBWI() ? MVT::v64i8 : MVT::v16i32;
2532 }
2533 // FIXME: Check if unaligned 32-byte accesses are slow.
2534 if (Op.size() >= 32 && Subtarget.hasAVX() &&
2535 (Subtarget.getPreferVectorWidth() >= 256)) {
2536 // Although this isn't a well-supported type for AVX1, we'll let
2537 // legalization and shuffle lowering produce the optimal codegen. If we
2538 // choose an optimal type with a vector element larger than a byte,
2539 // getMemsetStores() may create an intermediate splat (using an integer
2540 // multiply) before we splat as a vector.
2541 return MVT::v32i8;
2542 }
2543 if (Subtarget.hasSSE2() && (Subtarget.getPreferVectorWidth() >= 128))
2544 return MVT::v16i8;
2545 // TODO: Can SSE1 handle a byte vector?
2546 // If we have SSE1 registers we should be able to use them.
2547 if (Subtarget.hasSSE1() && (Subtarget.is64Bit() || Subtarget.hasX87()) &&
2548 (Subtarget.getPreferVectorWidth() >= 128))
2549 return MVT::v4f32;
2550 } else if (((Op.isMemcpy() && !Op.isMemcpyStrSrc()) || Op.isZeroMemset()) &&
2551 Op.size() >= 8 && !Subtarget.is64Bit() && Subtarget.hasSSE2()) {
2552 // Do not use f64 to lower memcpy if source is string constant. It's
2553 // better to use i32 to avoid the loads.
2554 // Also, do not use f64 to lower memset unless this is a memset of zeros.
2555 // The gymnastics of splatting a byte value into an XMM register and then
2556 // only using 8-byte stores (because this is a CPU with slow unaligned
2557 // 16-byte accesses) makes that a loser.
2558 return MVT::f64;
2559 }
2560 }
2561 // This is a compromise. If we reach here, unaligned accesses may be slow on
2562 // this target. However, creating smaller, aligned accesses could be even
2563 // slower and would certainly be a lot more code.
2564 if (Subtarget.is64Bit() && Op.size() >= 8)
2565 return MVT::i64;
2566 return MVT::i32;
2567}
2568
2569bool X86TargetLowering::isSafeMemOpType(MVT VT) const {
2570 if (VT == MVT::f32)
2571 return X86ScalarSSEf32;
2572 if (VT == MVT::f64)
2573 return X86ScalarSSEf64;
2574 return true;
2575}
2576
2577bool X86TargetLowering::allowsMisalignedMemoryAccesses(
2578 EVT VT, unsigned, Align Alignment, MachineMemOperand::Flags Flags,
2579 bool *Fast) const {
2580 if (Fast) {
2581 switch (VT.getSizeInBits()) {
2582 default:
2583 // 8-byte and under are always assumed to be fast.
2584 *Fast = true;
2585 break;
2586 case 128:
2587 *Fast = !Subtarget.isUnalignedMem16Slow();
2588 break;
2589 case 256:
2590 *Fast = !Subtarget.isUnalignedMem32Slow();
2591 break;
2592 // TODO: What about AVX-512 (512-bit) accesses?
2593 }
2594 }
2595 // NonTemporal vector memory ops must be aligned.
2596 if (!!(Flags & MachineMemOperand::MONonTemporal) && VT.isVector()) {
2597 // NT loads can only be vector aligned, so if its less aligned than the
2598 // minimum vector size (which we can split the vector down to), we might as
2599 // well use a regular unaligned vector load.
2600 // We don't have any NT loads pre-SSE41.
2601 if (!!(Flags & MachineMemOperand::MOLoad))
2602 return (Alignment < 16 || !Subtarget.hasSSE41());
2603 return false;
2604 }
2605 // Misaligned accesses of any size are always allowed.
2606 return true;
2607}
2608
2609/// Return the entry encoding for a jump table in the
2610/// current function. The returned value is a member of the
2611/// MachineJumpTableInfo::JTEntryKind enum.
2612unsigned X86TargetLowering::getJumpTableEncoding() const {
2613 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
2614 // symbol.
2615 if (isPositionIndependent() && Subtarget.isPICStyleGOT())
2616 return MachineJumpTableInfo::EK_Custom32;
2617
2618 // Otherwise, use the normal jump table encoding heuristics.
2619 return TargetLowering::getJumpTableEncoding();
2620}
2621
2622bool X86TargetLowering::useSoftFloat() const {
2623 return Subtarget.useSoftFloat();
2624}
2625
2626void X86TargetLowering::markLibCallAttributes(MachineFunction *MF, unsigned CC,
2627 ArgListTy &Args) const {
2628
2629 // Only relabel X86-32 for C / Stdcall CCs.
2630 if (Subtarget.is64Bit())
2631 return;
2632 if (CC != CallingConv::C && CC != CallingConv::X86_StdCall)
2633 return;
2634 unsigned ParamRegs = 0;
2635 if (auto *M = MF->getFunction().getParent())
2636 ParamRegs = M->getNumberRegisterParameters();
2637
2638 // Mark the first N int arguments as having reg
2639 for (auto &Arg : Args) {
2640 Type *T = Arg.Ty;
2641 if (T->isIntOrPtrTy())
2642 if (MF->getDataLayout().getTypeAllocSize(T) <= 8) {
2643 unsigned numRegs = 1;
2644 if (MF->getDataLayout().getTypeAllocSize(T) > 4)
2645 numRegs = 2;
2646 if (ParamRegs < numRegs)
2647 return;
2648 ParamRegs -= numRegs;
2649 Arg.IsInReg = true;
2650 }
2651 }
2652}
2653
2654const MCExpr *
2655X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
2656 const MachineBasicBlock *MBB,
2657 unsigned uid,MCContext &Ctx) const{
2658 assert(isPositionIndependent() && Subtarget.isPICStyleGOT())(static_cast <bool> (isPositionIndependent() &&
Subtarget.isPICStyleGOT()) ? void (0) : __assert_fail ("isPositionIndependent() && Subtarget.isPICStyleGOT()"
, "llvm/lib/Target/X86/X86ISelLowering.cpp", 2658, __extension__
__PRETTY_FUNCTION__))
;
2659 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
2660 // entries.
2661 return MCSymbolRefExpr::create(MBB->getSymbol(),
2662 MCSymbolRefExpr::VK_GOTOFF, Ctx);
2663}
2664
2665/// Returns relocation base for the given PIC jumptable.
2666SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
2667 SelectionDAG &DAG) const {
2668 if (!Subtarget.is64Bit())
2669 // This doesn't have SDLoc associated with it, but is not really the
2670 // same as a Register.
2671 return DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(),
2672 getPointerTy(DAG.getDataLayout()));
2673 return Table;
2674}
2675
2676/// This returns the relocation base for the given PIC jumptable,
2677/// the same as getPICJumpTableRelocBase, but as an MCExpr.
2678const MCExpr *X86TargetLowering::
2679getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
2680 MCContext &Ctx) const {
2681 // X86-64 uses RIP relative addressing based on the jump table label.
2682 if (Subtarget.isPICStyleRIPRel())
2683 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
2684
2685 // Otherwise, the reference is relative to the PIC base.
2686 return MCSymbolRefExpr::create(MF->getPICBaseSymbol(), Ctx);
2687}
2688
2689std::pair<const TargetRegisterClass *, uint8_t>
2690X86TargetLowering::findRepresentativeClass(const TargetRegisterInfo *TRI,
2691 MVT VT) const {
2692 const TargetRegisterClass *RRC = nullptr;
2693 uint8_t Cost = 1;
2694 switch (VT.SimpleTy) {
2695 default:
2696 return TargetLowering::findRepresentativeClass(TRI, VT);
2697 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
2698 RRC = Subtarget.is64Bit() ? &X86::GR64RegClass : &X86::GR32RegClass;
2699 break;
2700 case MVT::x86mmx:
2701 RRC = &X86::VR64RegClass;
2702 break;
2703 case MVT::f32: case MVT::f64:
2704 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
2705 case MVT::v4f32: case MVT::v2f64:
2706 case MVT::v32i8: case MVT::v16i16: case MVT::v8i32: case MVT::v4i64:
2707 case MVT::v8f32: case MVT::v4f64:
2708 case MVT::v64i8: case MVT::v32i16: case MVT::v16i32: case MVT::v8i64:
2709 case MVT::v16f32: case MVT::v8f64:
2710 RRC = &X86::VR128XRegClass;
2711 break;
2712 }
2713 return std::make_pair(RRC, Cost);
2714}
2715
2716unsigned X86TargetLowering::getAddressSpace() const {
2717 if (Subtarget.is64Bit())
2718 return (getTargetMachine().getCodeModel() == CodeModel::Kernel) ? 256 : 257;
2719 return 256;
2720}
2721
2722static bool hasStackGuardSlotTLS(const Triple &TargetTriple) {
2723 return TargetTriple.isOSGlibc() || TargetTriple.isOSFuchsia() ||
2724 (TargetTriple.isAndroid() && !TargetTriple.isAndroidVersionLT(17));
2725}
2726
2727static Constant* SegmentOffset(IRBuilderBase &IRB,
2728 int Offset, unsigned AddressSpace) {
2729 return ConstantExpr::getIntToPtr(
2730 ConstantInt::get(Type::getInt32Ty(IRB.getContext()), Offset),
2731 Type::getInt8PtrTy(IRB.getContext())->getPointerTo(AddressSpace));
2732}
2733
2734Value *X86TargetLowering::getIRStackGuard(IRBuilderBase &IRB) const {
2735 // glibc, bionic, and Fuchsia have a special slot for the stack guard in
2736 // tcbhead_t; use it instead of the usual global variable (see
2737 // sysdeps/{i386,x86_64}/nptl/tls.h)
2738 if (hasStackGuardSlotTLS(Subtarget.getTargetTriple())) {
2739 if (Subtarget.isTargetFuchsia()) {
2740 // <zircon/tls.h> defines ZX_TLS_STACK_GUARD_OFFSET with this value.
2741 return SegmentOffset(IRB, 0x10, getAddressSpace());
2742 } else {
2743 unsigned AddressSpace = getAddressSpace();
2744 Module *M = IRB.GetInsertBlock()->getParent()->getParent();
2745 // Specially, some users may customize the base reg and offset.
2746 int Offset = M->getStackProtectorGuardOffset();
2747 // If we don't set -stack-protector-guard-offset value:
2748 // %fs:0x28, unless we're using a Kernel code model, in which case
2749 // it's %gs:0x28. gs:0x14 on i386.
2750 if (Offset == INT_MAX2147483647)
2751 Offset = (Subtarget.is64Bit()) ? 0x28 : 0x14;
2752
2753 StringRef GuardReg = M->getStackProtectorGuardReg();
2754 if (GuardReg == "fs")
2755 AddressSpace = X86AS::FS;
2756 else if (GuardReg == "gs")
2757 AddressSpace = X86AS::GS;
2758 return SegmentOffset(IRB, Offset, AddressSpace);
2759 }
2760 }
2761 return TargetLowering::getIRStackGuard(IRB);
2762}
2763
2764void X86TargetLowering::insertSSPDeclarations(Module &M) const {
2765 // MSVC CRT provides functionalities for stack protection.
2766 if (Subtarget.getTargetTriple().isWindowsMSVCEnvironment() ||
2767 Subtarget.getTargetTriple().isWindowsItaniumEnvironment()) {
2768 // MSVC CRT has a global variable holding security cookie.
2769 M.getOrInsertGlobal("__security_cookie",
2770 Type::getInt8PtrTy(M.getContext()));
2771
2772 // MSVC CRT has a function to validate security cookie.
2773 FunctionCallee SecurityCheckCookie = M.getOrInsertFunction(
2774 "__security_check_cookie", Type::getVoidTy(M.getContext()),
2775 Type::getInt8PtrTy(M.getContext()));
2776 if (Function *F = dyn_cast<Function>(SecurityCheckCookie.getCallee())) {
2777 F->setCallingConv(CallingConv::X86_FastCall);
2778 F->addParamAttr(0, Attribute::AttrKind::InReg);
2779 }
2780 return;
2781 }
2782
2783 StringRef GuardMode = M.getStackProtectorGuard();
2784
2785 // glibc, bionic, and Fuchsia have a special slot for the stack guard.
2786 if ((GuardMode == "tls" || GuardMode.empty()) &&
2787 hasStackGuardSlotTLS(Subtarget.getTargetTriple()))
2788 return;
2789 TargetLowering::insertSSPDeclarations(M);
2790}
2791
2792Value *X86TargetLowering::getSDagStackGuard(const Module &M) const {
2793 // MSVC CRT has a global variable holding security cookie.
2794 if (Subtarget.getTargetTriple().isWindowsMSVCEnvironment() ||
2795 Subtarget.getTargetTriple().isWindowsItaniumEnvironment()) {
2796 return M.getGlobalVariable("__security_cookie");
2797 }
2798 return TargetLowering::getSDagStackGuard(M);
2799}
2800
2801Function *X86TargetLowering::getSSPStackGuardCheck(const Module &M) const {
2802 // MSVC CRT has a function to validate security cookie.
2803 if (Subtarget.getTargetTriple().isWindowsMSVCEnvironment() ||
2804 Subtarget.getTargetTriple().isWindowsItaniumEnvironment()) {
2805 return M.getFunction("__security_check_cookie");
2806 }
2807 return TargetLowering::getSSPStackGuardCheck(M);
2808}
2809
2810Value *
2811X86TargetLowering::getSafeStackPointerLocation(IRBuilderBase &IRB) const {
2812 if (Subtarget.getTargetTriple().isOSContiki())
2813 return getDefaultSafeStackPointerLocation(IRB, false);
2814
2815 // Android provides a fixed TLS slot for the SafeStack pointer. See the
2816 // definition of TLS_SLOT_SAFESTACK in
2817 // https://android.googlesource.com/platform/bionic/+/master/libc/private/bionic_tls.h
2818 if (Subtarget.isTargetAndroid()) {
2819 // %fs:0x48, unless we're using a Kernel code model, in which case it's %gs:
2820 // %gs:0x24 on i386
2821 int Offset = (Subtarget.is64Bit()) ? 0x48 : 0x24;
2822 return SegmentOffset(IRB, Offset, getAddressSpace());
2823 }
2824
2825 // Fuchsia is similar.
2826 if (Subtarget.isTargetFuchsia()) {
2827 // <zircon/tls.h> defines ZX_TLS_UNSAFE_SP_OFFSET with this value.
2828 return SegmentOffset(IRB, 0x18, getAddressSpace());
2829 }
2830
2831 return TargetLowering::getSafeStackPointerLocation(IRB);
2832}
2833
2834//===----------------------------------------------------------------------===//
2835// Return Value Calling Convention Implementation
2836//===----------------------------------------------------------------------===//
2837
2838bool X86TargetLowering::CanLowerReturn(
2839 CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg,
2840 const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const {
2841 SmallVector<CCValAssign, 16> RVLocs;
2842 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
2843 return CCInfo.CheckReturn(Outs, RetCC_X86);
2844}
2845
2846const MCPhysReg *X86TargetLowering::getScratchRegisters(CallingConv::ID) const {
2847 static const MCPhysReg ScratchRegs[] = { X86::R11, 0 };
2848 return ScratchRegs;
2849}
2850
2851/// Lowers masks values (v*i1) to the local register values
2852/// \returns DAG node after lowering to register type
2853static SDValue lowerMasksToReg(const SDValue &ValArg, const EVT &ValLoc,
2854 const SDLoc &Dl, SelectionDAG &DAG) {
2855 EVT ValVT = ValArg.getValueType();
2856
2857 if (ValVT == MVT::v1i1)
2858 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, Dl, ValLoc, ValArg,
2859 DAG.getIntPtrConstant(0, Dl));
2860
2861 if ((ValVT == MVT::v8i1 && (ValLoc == MVT::i8 || ValLoc == MVT::i32)) ||
2862 (ValVT == MVT::v16i1 && (ValLoc == MVT::i16 || ValLoc == MVT::i32))) {
2863 // Two stage lowering might be required
2864 // bitcast: v8i1 -> i8 / v16i1 -> i16
2865 // anyextend: i8 -> i32 / i16 -> i32
2866 EVT TempValLoc = ValVT == MVT::v8i1 ? MVT::i8 : MVT::i16;
2867 SDValue ValToCopy = DAG.getBitcast(TempValLoc, ValArg);
2868 if (ValLoc == MVT::i32)
2869 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, Dl, ValLoc, ValToCopy);
2870 return ValToCopy;
2871 }
2872
2873 if ((ValVT == MVT::v32i1 && ValLoc == MVT::i32) ||
2874 (ValVT == MVT::v64i1 && ValLoc == MVT::i64)) {
2875 // One stage lowering is required
2876 // bitcast: v32i1 -> i32 / v64i1 -> i64
2877 return DAG.getBitcast(ValLoc, ValArg);
2878 }
2879
2880 return DAG.getNode(ISD::ANY_EXTEND, Dl, ValLoc, ValArg);
2881}
2882
2883/// Breaks v64i1 value into two registers and adds the new node to the DAG
2884static void Passv64i1ArgInRegs(
2885 const SDLoc &Dl, SelectionDAG &DAG, SDValue &Arg,
2886 SmallVectorImpl<std::pair<Register, SDValue>> &RegsToPass, CCValAssign &VA,
2887 CCValAssign &NextVA, const X86Subtarget &Subtarget) {
2888 assert(Subtarget.hasBWI() && "Expected AVX512BW target!")(static_cast <bool> (Subtarget.hasBWI() && "Expected AVX512BW target!"
) ? void (0) : __assert_fail ("Subtarget.hasBWI() && \"Expected AVX512BW target!\""
, "llvm/lib/Target/X86/X86ISelLowering.cpp", 2888, __extension__
__PRETTY_FUNCTION__))
;
2889 assert(Subtarget.is32Bit() && "Expecting 32 bit target")(static_cast <bool> (Subtarget.is32Bit() && "Expecting 32 bit target"
) ? void (0) : __assert_fail ("Subtarget.is32Bit() && \"Expecting 32 bit target\""
, "llvm/lib/Target/X86/X86ISelLowering.cpp", 2889, __extension__
__PRETTY_FUNCTION__))
;
2890 assert(Arg.getValueType() == MVT::i64 && "Expecting 64 bit value")(static_cast <bool> (Arg.getValueType() == MVT::i64 &&
"Expecting 64 bit value") ? void (0) : __assert_fail ("Arg.getValueType() == MVT::i64 && \"Expecting 64 bit value\""
, "llvm/lib/Target/X86/X86ISelLowering.cpp", 2890, __extension__
__PRETTY_FUNCTION__))
;
2891 assert(VA.isRegLoc() && NextVA.isRegLoc() &&(static_cast <bool> (VA.isRegLoc() && NextVA.isRegLoc
() && "The value should reside in two registers") ? void
(0) : __assert_fail ("VA.isRegLoc() && NextVA.isRegLoc() && \"The value should reside in two registers\""
, "llvm/lib/Target/X86/X86ISelLowering.cpp", 2892, __extension__
__PRETTY_FUNCTION__))
2892 "The value should reside in two registers")(static_cast <bool> (VA.isRegLoc() && NextVA.isRegLoc
() && "The value should reside in two registers") ? void
(0) : __assert_fail ("VA.isRegLoc() && NextVA.isRegLoc() && \"The value should reside in two registers\""
, "llvm/lib/Target/X86/X86ISelLowering.cpp", 2892, __extension__
__PRETTY_FUNCTION__))
;
2893
2894 // Before splitting the value we cast it to i64
2895 Arg = DAG.getBitcast(MVT::i64, Arg);
2896
2897 // Splitting the value into two i32 types
2898 SDValue Lo, Hi;
2899 Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, Dl, MVT::i32, Arg,
2900 DAG.getConstant(0, Dl, MVT::i32));
2901 Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, Dl, MVT::i32, Arg,
2902 DAG.getConstant(1, Dl, MVT::i32));
2903
2904 // Attach the two i32 types into corresponding registers
2905 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Lo));
2906 RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), Hi));
2907}
2908
2909SDValue
2910X86TargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
2911 bool isVarArg,
2912 const SmallVectorImpl<ISD::OutputArg> &Outs,
2913 const SmallVectorImpl<SDValue> &OutVals,
2914 const SDLoc &dl, SelectionDAG &DAG) const {
2915 MachineFunction &MF = DAG.getMachineFunction();
2916 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2917
2918 // In some cases we need to disable registers from the default CSR list.
2919 // For example, when they are used for argument passing.
2920 bool ShouldDisableCalleeSavedRegister =
2921 CallConv == CallingConv::X86_RegCall ||
2922 MF.getFunction().hasFnAttribute("no_caller_saved_registers");
2923
2924 if (CallConv == CallingConv::X86_INTR && !Outs.empty())
2925 report_fatal_error("X86 interrupts may not return any value");
2926
2927 SmallVector<CCValAssign, 16> RVLocs;
2928 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, *DAG.getContext());
2929 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
2930
2931 SmallVector<std::pair<Register, SDValue>, 4> RetVals;
2932 for (unsigned I = 0, OutsIndex = 0, E = RVLocs.size(); I != E;
2933 ++I, ++OutsIndex) {
2934 CCValAssign &VA = RVLocs[I];
2935 assert(VA.isRegLoc() && "Can only return in registers!")(static_cast <bool> (VA.isRegLoc() && "Can only return in registers!"
) ? void (0) : __assert_fail ("VA.isRegLoc() && \"Can only return in registers!\""
, "llvm/lib/Target/X86/X86ISelLowering.cpp", 2935, __extension__
__PRETTY_FUNCTION__))
;
2936
2937 // Add the register to the CalleeSaveDisableRegs list.
2938 if (ShouldDisableCalleeSavedRegister)
2939 MF.getRegInfo().disableCalleeSavedRegister(VA.getLocReg());
2940
2941 SDValue ValToCopy = OutVals[OutsIndex];
2942 EVT ValVT = ValToCopy.getValueType();
2943
2944 // Promote values to the appropriate types.
2945 if (VA.getLocInfo() == CCValAssign::SExt)
2946 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
2947 else if (VA.getLocInfo() == CCValAssign::ZExt)
2948 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy);
2949 else if (VA.getLocInfo() == CCValAssign::AExt) {
2950 if (ValVT.isVector() && ValVT.getVectorElementType() == MVT::i1)
2951 ValToCopy = lowerMasksToReg(ValToCopy, VA.getLocVT(), dl, DAG);
2952 else
2953 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy);
2954 }
2955 else if (VA.getLocInfo() == CCValAssign::BCvt)
2956 ValToCopy = DAG.getBitcast(VA.getLocVT(), ValToCopy);
2957
2958 assert(VA.getLocInfo() != CCValAssign::FPExt &&(static_cast <bool> (VA.getLocInfo() != CCValAssign::FPExt
&& "Unexpected FP-extend for return value.") ? void (
0) : __assert_fail ("VA.getLocInfo() != CCValAssign::FPExt && \"Unexpected FP-extend for return value.\""
, "llvm/lib/Target/X86/X86ISelLowering.cpp", 2959, __extension__
__PRETTY_FUNCTION__))
2959 "Unexpected FP-extend for return value.")(static_cast <bool> (VA.getLocInfo() != CCValAssign::FPExt
&& "Unexpected FP-extend for return value.") ? void (
0) : __assert_fail ("VA.getLocInfo() != CCValAssign::FPExt && \"Unexpected FP-extend for return value.\""
, "llvm/lib/Target/X86/X86ISelLowering.cpp", 2959, __extension__
__PRETTY_FUNCTION__))
;
2960
2961 // Report an error if we have attempted to return a value via an XMM
2962 // register and SSE was disabled.
2963 if (!Subtarget.hasSSE1() && X86::FR32XRegClass.contains(VA.getLocReg())) {
2964 errorUnsupported(DAG, dl, "SSE register return with SSE disabled");
2965 VA.convertToReg(X86::FP0); // Set reg to FP0, avoid hitting asserts.
2966 } else if (!Subtarget.hasSSE2() &&
2967 X86::FR64XRegClass.contains(VA.getLocReg()) &&
2968 ValVT == MVT::f64) {
2969 // When returning a double via an XMM register, report an error if SSE2 is
2970 // not enabled.
2971 errorUnsupported(DAG, dl, "SSE2 register return with SSE2 disabled");
2972 VA.convertToReg(X86::FP0); // Set reg to FP0, avoid hitting asserts.
2973 }
2974
2975 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
2976 // the RET instruction and handled by the FP Stackifier.
2977 if (VA.getLocReg() == X86::FP0 ||
2978 VA.getLocReg() == X86::FP1) {
2979 // If this is a copy from an xmm register to ST(0), use an FPExtend to
2980 // change the value to the FP stack register class.
2981 if (isScalarFPTypeInSSEReg(VA.getValVT()))
2982 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
2983 RetVals.push_back(std::make_pair(VA.getLocReg(), ValToCopy));
2984 // Don't emit a copytoreg.
2985 continue;
2986 }
2987
2988 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
2989 // which is returned in RAX / RDX.
2990 if (Subtarget.is64Bit()) {
2991 if (ValVT == MVT::x86mmx) {
2992 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
2993 ValToCopy = DAG.getBitcast(MVT::i64, ValToCopy);
2994 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
2995 ValToCopy);
2996 // If we don't have SSE2 available, convert to v4f32 so the generated
2997 // register is legal.
2998 if (!Subtarget.hasSSE2())
2999 ValToCopy = DAG.getBitcast(MVT::v4f32, ValToCopy);
3000 }
3001 }
3002 }
3003
3004 if (VA.needsCustom()) {
3005 assert(VA.getValVT() == MVT::v64i1 &&(static_cast <bool> (VA.getValVT() == MVT::v64i1 &&
"Currently the only custom case is when we split v64i1 to 2 regs"
) ? void (0) : __assert_fail ("VA.getValVT() == MVT::v64i1 && \"Currently the only custom case is when we split v64i1 to 2 regs\""
, "llvm/lib/Target/X86/X86ISelLowering.cpp", 3006, __extension__
__PRETTY_FUNCTION__))
3006 "Currently the only custom case is when we split v64i1 to 2 regs")(static_cast <bool> (VA.getValVT() == MVT::v64i1 &&
"Currently the only custom case is when we split v64i1 to 2 regs"
) ? void (0) : __assert_fail ("VA.getValVT() == MVT::v64i1 && \"Currently the only custom case is when we split v64i1 to 2 regs\""
, "llvm/lib/Target/X86/X86ISelLowering.cpp", 3006, __extension__
__PRETTY_FUNCTION__))
;
3007
3008 Passv64i1ArgInRegs(dl, DAG, ValToCopy, RetVals, VA, RVLocs[++I],
3009 Subtarget);
3010
3011 // Add the second register to the CalleeSaveDisableRegs list.
3012 if (ShouldDisableCalleeSavedRegister)
3013 MF.getRegInfo().disableCalleeSavedRegister(RVLocs[I].getLocReg());
3014 } else {
3015 RetVals.push_back(std::make_pair(VA.getLocReg(), ValToCopy));
3016 }
3017 }
3018
3019 SDValue Flag;
3020 SmallVector<SDValue, 6> RetOps;
3021 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
3022 // Operand #1 = Bytes To Pop
3023 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(), dl,
3024 MVT::i32));
3025
3026 // Copy the result values into the output registers.
3027 for (auto &RetVal : RetVals) {
3028 if (RetVal.first == X86::FP0 || RetVal.first == X86::FP1) {
3029 RetOps.push_back(RetVal.second);
3030 continue; // Don't emit a copytoreg.
3031 }
3032
3033 Chain = DAG.getCopyToReg(Chain, dl, RetVal.first, RetVal.second, Flag);
3034 Flag = Chain.getValue(1);
3035 RetOps.push_back(
3036 DAG.getRegister(RetVal.first, RetVal.second.getValueType()));
3037 }
3038
3039 // Swift calling convention does not require we copy the sret argument
3040 // into %rax/%eax for the return, and SRetReturnReg is not set for Swift.
3041
3042 // All x86 ABIs require that for returning structs by value we copy
3043 // the sret argument into %rax/%eax (depending on ABI) for the return.
3044 // We saved the argument into a virtual register in the entry block,
3045 // so now we copy the value out and into %rax/%eax.
3046 //
3047 // Checking Function.hasStructRetAttr() here is insufficient because the IR
3048 // may not have an explicit sret argument. If FuncInfo.CanLowerReturn is
3049 // false, then an sret argument may be implicitly inserted in the SelDAG. In
3050 // either case FuncInfo->setSRetReturnReg() will have been called.
3051 if (Register SRetReg = FuncInfo->getSRetReturnReg()) {
3052 // When we have both sret and another return value, we should use the
3053 // original Chain stored in RetOps[0], instead of the current Chain updated
3054 // in the above loop. If we only have sret, RetOps[0] equals to Chain.
3055
3056 // For the case of sret and another return value, we have
3057 // Chain_0 at the function entry
3058 // Chain_1 = getCopyToReg(Chain_0) in the above loop
3059 // If we use Chain_1 in getCopyFromReg, we will have
3060 // Val = getCopyFromReg(Chain_1)
3061 // Chain_2 = getCopyToReg(Chain_1, Val) from below
3062
3063 // getCopyToReg(Chain_0) will be glued together with
3064 // getCopyToReg(Chain_1, Val) into Unit A, getCopyFromReg(Chain_1) will be
3065 // in Unit B, and we will have cyclic dependency between Unit A and Unit B:
3066 // Data dependency from Unit B to Unit A due to usage of Val in
3067 // getCopyToReg(Chain_1, Val)
3068 // Chain dependency from Unit A to Unit B
3069
3070 // So here, we use RetOps[0] (i.e Chain_0) for getCopyFromReg.
3071 SDValue Val = DAG.getCopyFromReg(RetOps[0], dl, SRetReg,
3072 getPointerTy(MF.getDataLayout()));
3073
3074 Register RetValReg
3075 = (Subtarget.is64Bit() && !Subtarget.isTarget64BitILP32()) ?
3076 X86::RAX : X86::EAX;
3077 Chain = DAG.getCopyToReg(Chain, dl, RetValReg, Val, Flag);
3078 Flag = Chain.getValue(1);
3079
3080 // RAX/EAX now acts like a return value.
3081 RetOps.push_back(
3082 DAG.getRegister(RetValReg, getPointerTy(DAG.getDataLayout())));
3083
3084 // Add the returned register to the CalleeSaveDisableRegs list.
3085 if (ShouldDisableCalleeSavedRegister)
3086 MF.getRegInfo().disableCalleeSavedRegister(RetValReg);
3087 }
3088
3089 const X86RegisterInfo *TRI = Subtarget.getRegisterInfo();
3090 const MCPhysReg *I =
3091 TRI->getCalleeSavedRegsViaCopy(&DAG.getMachineFunction());
3092 if (I) {
3093 for (; *I; ++I) {
3094 if (X86::GR64RegClass.contains(*I))
3095 RetOps.push_back(DAG.getRegister(*I, MVT::i64));
3096 else
3097 llvm_unreachable("Unexpected register class in CSRsViaCopy!")::llvm::llvm_unreachable_internal("Unexpected register class in CSRsViaCopy!"
, "llvm/lib/Target/X86/X86ISelLowering.cpp", 3097)
;
3098 }
3099 }
3100
3101 RetOps[0] = Chain; // Update chain.
3102
3103 // Add the flag if we have it.
3104 if (Flag.getNode())
3105 RetOps.push_back(Flag);
3106
3107 X86ISD::NodeType opcode = X86ISD::RET_FLAG;
3108 if (CallConv == CallingConv::X86_INTR)
3109 opcode = X86ISD::IRET;
3110 return DAG.getNode(opcode, dl, MVT::Other, RetOps);
3111}
3112
3113bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
3114 if (N->getNumValues() != 1 || !N->hasNUsesOfValue(1, 0))
3115 return false;
3116
3117 SDValue TCChain = Chain;
3118 SDNode *Copy = *N->use_begin();
3119 if (Copy->getOpcode() == ISD::CopyToReg) {
3120 // If the copy has a glue operand, we conservatively assume it isn't safe to
3121 // perform a tail call.
3122 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
3123 return false;
3124 TCChain = Copy->getOperand(0);
3125 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
3126 return false;
3127
3128 bool HasRet = false;
3129 for (const SDNode *U : Copy->uses()) {
3130 if (U->getOpcode() != X86ISD::RET_FLAG)
3131 return false;
3132 // If we are returning more than one value, we can definitely
3133 // not make a tail call see PR19530
3134 if (U->getNumOperands() > 4)
3135 return false;
3136 if (U->getNumOperands() == 4 &&
3137 U->getOperand(U->getNumOperands() - 1).getValueType() != MVT::Glue)
3138 return false;
3139 HasRet = true;
3140 }
3141
3142 if (!HasRet)
3143 return false;
3144
3145 Chain = TCChain;
3146 return true;
3147}
3148
3149EVT X86TargetLowering::getTypeForExtReturn(LLVMContext &Context, EVT VT,
3150 ISD::NodeType ExtendKind) const {
3151 MVT ReturnMVT = MVT::i32;
3152
3153 bool Darwin = Subtarget.getTargetTriple().isOSDarwin();
3154 if (VT == MVT::i1 || (!Darwin && (VT == MVT::i8 || VT == MVT::i16))) {
3155 // The ABI does not require i1, i8 or i16 to be extended.
3156 //
3157 // On Darwin, there is code in the wild relying on Clang's old behaviour of
3158 // always extending i8/i16 return values, so keep doing that for now.
3159 // (PR26665).
3160 ReturnMVT = MVT::i8;
3161 }
3162
3163 EVT MinVT = getRegisterType(Context, ReturnMVT);
3164 return VT.bitsLT(MinVT) ? MinVT : VT;
3165}
3166
3167/// Reads two 32 bit registers and creates a 64 bit mask value.
3168/// \param VA The current 32 bit value that need to be assigned.
3169/// \param NextVA The next 32 bit value that need to be assigned.
3170/// \param Root The parent DAG node.
3171/// \param [in,out] InFlag Represents SDvalue in the parent DAG node for
3172/// glue purposes. In the case the DAG is already using
3173/// physical register instead of virtual, we should glue
3174/// our new SDValue to InFlag SDvalue.
3175/// \return a new SDvalue of size 64bit.
3176static SDValue getv64i1Argument(CCValAssign &VA, CCValAssign &NextVA,
3177 SDValue &Root, SelectionDAG &DAG,
3178 const SDLoc &Dl, const X86Subtarget &Subtarget,
3179 SDValue *InFlag = nullptr) {
3180 assert((Subtarget.hasBWI()) && "Expected AVX512BW target!")(static_cast <bool> ((Subtarget.hasBWI()) && "Expected AVX512BW target!"
) ? void (0) : __assert_fail ("(Subtarget.hasBWI()) && \"Expected AVX512BW target!\""
, "llvm/lib/Target/X86/X86ISelLowering.cpp", 3180, __extension__
__PRETTY_FUNCTION__))
;
3181 assert(Subtarget.is32Bit() && "Expecting 32 bit target")(static_cast <bool> (Subtarget.is32Bit() && "Expecting 32 bit target"
) ? void (0) : __assert_fail ("Subtarget.is32Bit() && \"Expecting 32 bit target\""
, "llvm/lib/Target/X86/X86ISelLowering.cpp", 3181, __extension__
__PRETTY_FUNCTION__))
;
3182 assert(VA.getValVT() == MVT::v64i1 &&(static_cast <bool> (VA.getValVT() == MVT::v64i1 &&
"Expecting first location of 64 bit width type") ? void (0) :
__assert_fail ("VA.getValVT() == MVT::v64i1 && \"Expecting first location of 64 bit width type\""
, "llvm/lib/Target/X86/X86ISelLowering.cpp", 3183, __extension__
__PRETTY_FUNCTION__))
3183 "Expecting first location of 64 bit width type")(static_cast <bool> (VA.getValVT() == MVT::v64i1 &&
"Expecting first location of 64 bit width type") ? void (0) :
__assert_fail ("VA.getValVT() == MVT::v64i1 && \"Expecting first location of 64 bit width type\""
, "llvm/lib/Target/X86/X86ISelLowering.cpp", 3183, __extension__
__PRETTY_FUNCTION__))
;
3184 assert(NextVA.getValVT() == VA.getValVT() &&(static_cast <bool> (NextVA.getValVT() == VA.getValVT()
&& "The locations should have the same type") ? void
(0) : __assert_fail ("NextVA.getValVT() == VA.getValVT() && \"The locations should have the same type\""
, "llvm/lib/Target/X86/X86ISelLowering.cpp", 3185, __extension__
__PRETTY_FUNCTION__))
3185 "The locations should have the same type")(static_cast <bool> (NextVA.getValVT() == VA.getValVT()
&& "The locations should have the same type") ? void
(0) : __assert_fail ("NextVA.getValVT() == VA.getValVT() && \"The locations should have the same type\""
, "llvm/lib/Target/X86/X86ISelLowering.cpp", 3185, __extension__
__PRETTY_FUNCTION__))
;
3186 assert(VA.isRegLoc() && NextVA.isRegLoc() &&(static_cast <bool> (VA.isRegLoc() && NextVA.isRegLoc
() && "The values should reside in two registers") ? void
(0) : __assert_fail ("VA.isRegLoc() && NextVA.isRegLoc() && \"The values should reside in two registers\""
, "llvm/lib/Target/X86/X86ISelLowering.cpp", 3187, __extension__
__PRETTY_FUNCTION__))
3187 "The values should reside in two registers")(static_cast <bool> (VA.isRegLoc() && NextVA.isRegLoc
() && "The values should reside in two registers") ? void
(0) : __assert_fail ("VA.isRegLoc() && NextVA.isRegLoc() && \"The values should reside in two registers\""
, "llvm/lib/Target/X86/X86ISelLowering.cpp", 3187, __extension__
__PRETTY_FUNCTION__))
;
3188
3189 SDValue Lo, Hi;
3190 SDValue ArgValueLo, ArgValueHi;
3191
3192 MachineFunction &MF = DAG.getMachineFunction();
3193 const TargetRegisterClass *RC = &X86::GR32RegClass;
3194
3195 // Read a 32 bit value from the registers.
3196 if (nullptr == InFlag) {
3197 // When no physical register is present,
3198 // create an intermediate virtual register.
3199 Register Reg = MF.addLiveIn(VA.getLocReg(), RC);
3200 ArgValueLo = DAG.getCopyFromReg(Root, Dl, Reg, MVT::i32);
3201 Reg = MF.addLiveIn(NextVA.getLocReg(), RC);
3202 ArgValueHi = DAG.getCopyFromReg(Root, Dl, Reg, MVT::i32);
3203 } else {
3204 // When a physical register is available read the value from it and glue
3205 // the reads together.
3206 ArgValueLo =
3207 DAG.getCopyFromReg(Root, Dl, VA.getLocReg(), MVT::i32, *InFlag);
3208 *InFlag = ArgValueLo.getValue(2);
3209 ArgValueHi =
3210 DAG.getCopyFromReg(Root, Dl, NextVA.getLocReg(), MVT::i32, *InFlag);
3211 *InFlag = ArgValueHi.getValue(2);
3212 }
3213
3214 // Convert the i32 type into v32i1 type.
3215 Lo = DAG.getBitcast(MVT::v32i1, ArgValueLo);
3216
3217 // Convert the i32 type into v32i1 type.
3218 Hi = DAG.getBitcast(MVT::v32i1, ArgValueHi);
3219
3220 // Concatenate the two values together.
3221 return DAG.getNode(ISD::CONCAT_VECTORS, Dl, MVT::v64i1, Lo, Hi);
3222}
3223
3224/// The function will lower a register of various sizes (8/16/32/64)
3225/// to a mask value of the expected size (v8i1/v16i1/v32i1/v64i1)
3226/// \returns a DAG node contains the operand after lowering to mask type.
3227static SDValue lowerRegToMasks(const SDValue &ValArg, const EVT &ValVT,
3228 const EVT &ValLoc, const SDLoc &Dl,
3229 SelectionDAG &DAG) {
3230 SDValue ValReturned = ValArg;
3231
3232 if (ValVT == MVT::v1i1)
3233 return DAG.getNode(ISD::SCALAR_TO_VECTOR, Dl, MVT::v1i1, ValReturned);
3234
3235 if (ValVT == MVT::v64i1) {
3236 // In 32 bit machine, this case is handled by getv64i1Argument
3237 assert(ValLoc == MVT::i64 && "Expecting only i64 locations")(static_cast <bool> (ValLoc == MVT::i64 && "Expecting only i64 locations"
) ? void (0) : __assert_fail ("ValLoc == MVT::i64 && \"Expecting only i64 locations\""
, "llvm/lib/Target/X86/X86ISelLowering.cpp", 3237, __extension__
__PRETTY_FUNCTION__))
;
3238 // In 64 bit machine, There is no need to truncate the value only bitcast
3239 } else {
3240 MVT maskLen;
3241 switch (ValVT.getSimpleVT().SimpleTy) {
3242 case MVT::v8i1:
3243 maskLen = MVT::i8;
3244 break;
3245 case MVT::v16i1:
3246 maskLen = MVT::i16;
3247 break;
3248 case MVT::v32i1:
3249 maskLen = MVT::i32;
3250 break;
3251 default:
3252 llvm_unreachable("Expecting a vector of i1 types")::llvm::llvm_unreachable_internal("Expecting a vector of i1 types"
, "llvm/lib/Target/X86/X86ISelLowering.cpp", 3252)
;
3253 }
3254
3255 ValReturned = DAG.getNode(ISD::TRUNCATE, Dl, maskLen, ValReturned);
3256 }
3257 return DAG.getBitcast(ValVT, ValReturned);
3258}
3259
3260/// Lower the result values of a call into the
3261/// appropriate copies out of appropriate physical registers.
3262///
3263SDValue X86TargetLowering::LowerCallResult(
3264 SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg,
3265 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
3266 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals,
3267 uint32_t *RegMask) const {
3268
3269 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
3270 // Assign locations to each value returned by this call.
3271 SmallVector<CCValAssign, 16> RVLocs;
3272 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
3273 *DAG.getContext());
3274 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
3275
3276 // Copy all of the result registers out of their specified physreg.
3277 for (unsigned I = 0, InsIndex = 0, E = RVLocs.size(); I != E;
3278 ++I, ++InsIndex) {
3279 CCValAssign &VA = RVLocs[I];
3280 EVT CopyVT = VA.getLocVT();
3281
3282 // In some calling conventions we need to remove the used registers
3283 // from the register mask.
3284 if (RegMask) {
3285 for (MCSubRegIterator SubRegs(VA.getLocReg(), TRI, /*IncludeSelf=*/true);
3286 SubRegs.isValid(); ++SubRegs)
3287 RegMask[*SubRegs / 32] &= ~(1u << (*SubRegs % 32));
3288 }
3289
3290 // Report an error if there was an attempt to return FP values via XMM
3291 // registers.
3292 if (!Subtarget.hasSSE1() && X86::FR32XRegClass.contains(VA.getLocReg())) {
3293 errorUnsupported(DAG, dl, "SSE register return with SSE disabled");
3294 if (VA.getLocReg() == X86::XMM1)
3295 VA.convertToReg(X86::FP1); // Set reg to FP1, avoid hitting asserts.
3296 else
3297 VA.convertToReg(X86::FP0); // Set reg to FP0, avoid hitting asserts.
3298 } else if (!Subtarget.hasSSE2() &&
3299 X86::FR64XRegClass.contains(VA.getLocReg()) &&
3300 CopyVT == MVT::f64) {
3301 errorUnsupported(DAG, dl, "SSE2 register return with SSE2 disabled");
3302 if (VA.getLocReg() == X86::XMM1)
3303 VA.convertToReg(X86::FP1); // Set reg to FP1, avoid hitting asserts.
3304 else
3305 VA.convertToReg(X86::FP0); // Set reg to FP0, avoid hitting asserts.
3306 }
3307
3308 // If we prefer to use the value in xmm registers, copy it out as f80 and
3309 // use a truncate to move it from fp stack reg to xmm reg.
3310 bool RoundAfterCopy = false;
3311 if ((VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1) &&
3312 isScalarFPTypeInSSEReg(VA.getValVT())) {
3313 if (!Subtarget.hasX87())
3314 report_fatal_error("X87 register return with X87 disabled");
3315 CopyVT = MVT::f80;
3316 RoundAfterCopy = (CopyVT != VA.getLocVT());
3317 }
3318
3319 SDValue Val;
3320 if (VA.needsCustom()) {
3321 assert(VA.getValVT() == MVT::v64i1 &&(static_cast <bool> (VA.getValVT() == MVT::v64i1 &&
"Currently the only custom case is when we split v64i1 to 2 regs"
) ? void (0) : __assert_fail ("VA.getValVT() == MVT::v64i1 && \"Currently the only custom case is when we split v64i1 to 2 regs\""
, "llvm/lib/Target/X86/X86ISelLowering.cpp", 3322, __extension__
__PRETTY_FUNCTION__))
3322 "Currently the only custom case is when we split v64i1 to 2 regs")(static_cast <bool> (VA.getValVT() == MVT::v64i1 &&
"Currently the only custom case is when we split v64i1 to 2 regs"
) ? void (0) : __assert_fail ("VA.getValVT() == MVT::v64i1 && \"Currently the only custom case is when we split v64i1 to 2 regs\""
, "llvm/lib/Target/X86/X86ISelLowering.cpp", 3322, __extension__
__PRETTY_FUNCTION__))
;
3323 Val =
3324 getv64i1Argument(VA, RVLocs[++I], Chain, DAG, dl, Subtarget, &InFlag);
3325 } else {
3326 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), CopyVT, InFlag)
3327 .getValue(1);
3328 Val = Chain.getValue(0);
3329 InFlag = Chain.getValue(2);
3330 }
3331
3332 if (RoundAfterCopy)
3333 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
3334 // This truncation won't change the value.
3335 DAG.getIntPtrConstant(1, dl));
3336
3337 if (VA.isExtInLoc()) {
3338 if (VA.getValVT().isVector() &&
3339 VA.getValVT().getScalarType() == MVT::i1 &&
3340 ((VA.getLocVT() == MVT::i64) || (VA.getLocVT() == MVT::i32) ||
3341 (VA.getLocVT() == MVT::i16) || (VA.getLocVT() == MVT::i8))) {
3342 // promoting a mask type (v*i1) into a register of type i64/i32/i16/i8
3343 Val = lowerRegToMasks(Val, VA.getValVT(), VA.getLocVT(), dl, DAG);
3344 } else
3345 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
3346 }
3347
3348 if (VA.getLocInfo() == CCValAssign::BCvt)
3349 Val = DAG.getBitcast(VA.getValVT(), Val);
3350
3351 InVals.push_back(Val);
3352 }
3353
3354 return Chain;
3355}
3356
3357//===----------------------------------------------------------------------===//
3358// C & StdCall & Fast Calling Convention implementation
3359//===----------------------------------------------------------------------===//
3360// StdCall calling convention seems to be standard for many Windows' API
3361// routines and around. It differs from C calling convention just a little:
3362// callee should clean up the stack, not caller. Symbols should be also
3363// decorated in some fancy way :) It doesn't support any vector arguments.
3364// For info on fast calling convention see Fast Calling Convention (tail call)
3365// implementation LowerX86_32FastCCCallTo.
3366
3367/// Determines whether Args, either a set of outgoing arguments to a call, or a
3368/// set of incoming args of a call, contains an sret pointer that the callee
3369/// pops
3370template <typename T>
3371static bool hasCalleePopSRet(const SmallVectorImpl<T> &Args,
3372 const X86Subtarget &Subtarget) {
3373 // Not C++20 (yet), so no concepts available.
3374 static_assert(std::is_same<T, ISD::OutputArg>::value ||
3375 std::is_same<T, ISD::InputArg>::value,
3376 "requires ISD::OutputArg or ISD::InputArg");
3377
3378 // Only 32-bit pops the sret. It's a 64-bit world these days, so early-out
3379 // for most compilations.
3380 if (!Subtarget.is32Bit())
3381 return false;
3382
3383 if (Args.empty())
3384 return false;
3385
3386 // Most calls do not have an sret argument, check the arg next.
3387 const ISD::ArgFlagsTy &Flags = Args[0].Flags;
3388 if (!Flags.isSRet() || Flags.isInReg())
3389 return false;
3390
3391 // The MSVCabi does not pop the sret.
3392 if (Subtarget.getTargetTriple().isOSMSVCRT())
3393 return false;
3394
3395 // MCUs don't pop the sret
3396 if (Subtarget.isTargetMCU())
3397 return false;
3398
3399 // Callee pops argument
3400 return true;
3401}
3402
3403/// Make a copy of an aggregate at address specified by "Src" to address
3404/// "Dst" with size and alignment information specified by the specific
3405/// parameter attribute. The copy will be passed as a byval function parameter.
3406static SDValue CreateCopyOfByValArgument(SDValue Src, SDValue Dst,
3407 SDValue Chain, ISD::ArgFlagsTy Flags,
3408 SelectionDAG &DAG, const SDLoc &dl) {
3409 SDValue SizeNode = DAG.getIntPtrConstant(Flags.getByValSize(), dl);
3410
3411 return DAG.getMemcpy(
3412 Chain, dl, Dst, Src, SizeNode, Flags.getNonZeroByValAlign(),
3413 /*isVolatile*/ false, /*AlwaysInline=*/true,
3414 /*isTailCall*/ false, MachinePointerInfo(), MachinePointerInfo());
3415}
3416
3417/// Return true if the calling convention is one that we can guarantee TCO for.
3418static bool canGuaranteeTCO(CallingConv::ID CC) {
3419 return (CC == CallingConv::Fast || CC == CallingConv::GHC ||
3420 CC == CallingConv::X86_RegCall || CC == CallingConv::HiPE ||
3421 CC == CallingConv::HHVM || CC == CallingConv::Tail ||
3422 CC == CallingConv::SwiftTail);
3423}
3424
3425/// Return true if we might ever do TCO for calls with this calling convention.
3426static bool mayTailCallThisCC(CallingConv::ID CC) {
3427 switch (CC) {
3428 // C calling conventions:
3429 case CallingConv::C:
3430 case CallingConv::Win64:
3431 case CallingConv::X86_64_SysV:
3432 // Callee pop conventions:
3433 case CallingConv::X86_ThisCall:
3434 case CallingConv::X86_StdCall:
3435 case CallingConv::X86_VectorCall:
3436 case CallingConv::X86_FastCall:
3437 // Swift:
3438 case CallingConv::Swift:
3439 return true;
3440 default:
3441 return canGuaranteeTCO(CC);
3442 }
3443}
3444
3445/// Return true if the function is being made into a tailcall target by
3446/// changing its ABI.
3447static bool shouldGuaranteeTCO(CallingConv::ID CC, bool GuaranteedTailCallOpt) {
3448 return (GuaranteedTailCallOpt && canGuaranteeTCO(CC)) ||
3449 CC == CallingConv::Tail || CC == CallingConv::SwiftTail;
3450}
3451
3452bool X86TargetLowering::mayBeEmittedAsTailCall(const CallInst *CI) const {
3453 if (!CI->isTailCall())
3454 return false;
3455
3456 CallingConv::ID CalleeCC = CI->getCallingConv();
3457 if (!mayTailCallThisCC(CalleeCC))
3458 return false;
3459
3460 return true;
3461}
3462
3463SDValue
3464X86TargetLowering::LowerMemArgument(SDValue Chain, CallingConv::ID CallConv,
3465 const SmallVectorImpl<ISD::InputArg> &Ins,
3466 const SDLoc &dl, SelectionDAG &DAG,
3467 const CCValAssign &VA,
3468 MachineFrameInfo &MFI, unsigned i) const {
3469 // Create the nodes corresponding to a load from this parameter slot.
3470 ISD::ArgFlagsTy Flags = Ins[i].Flags;
3471 bool AlwaysUseMutable = shouldGuaranteeTCO(
3472 CallConv, DAG.getTarget().Options.GuaranteedTailCallOpt);
3473 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
3474 EVT ValVT;
3475 MVT PtrVT = getPointerTy(DAG.getDataLayout());
3476
3477 // If value is passed by pointer we have address passed instead of the value
3478 // itself. No need to extend if the mask value and location share the same
3479 // absolute size.
3480 bool ExtendedInMem =
3481 VA.isExtInLoc() && VA.getValVT().getScalarType() == MVT::i1 &&
3482 VA.getValVT().getSizeInBits() != VA.getLocVT().getSizeInBits();
3483
3484 if (VA.getLocInfo() == CCValAssign::Indirect || ExtendedInMem)
3485 ValVT = VA.getLocVT();
3486 else
3487 ValVT = VA.getValVT();
3488
3489 // FIXME: For now, all byval parameter objects are marked mutable. This can be
3490 // changed with more analysis.
3491 // In case of tail call optimization mark all arguments mutable. Since they
3492 // could be overwritten by lowering of arguments in case of a tail call.
3493 if (Flags.isByVal()) {
3494 unsigned Bytes = Flags.getByValSize();
3495 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
3496
3497 // FIXME: For now, all byval parameter objects are marked as aliasing. This
3498 // can be improved with deeper analysis.
3499 int FI = MFI.CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable,
3500 /*isAliased=*/true);
3501 return DAG.getFrameIndex(FI, PtrVT);
3502 }
3503
3504 EVT ArgVT = Ins[i].ArgVT;
3505
3506 // If this is a vector that has been split into multiple parts, and the
3507 // scalar size of the parts don't match the vector element size, then we can't
3508 // elide the copy. The parts will have padding between them instead of being
3509 // packed like a vector.
3510 bool ScalarizedAndExtendedVector =
3511 ArgVT.isVector() && !VA.getLocVT().isVector() &&
3512 VA.getLocVT().getSizeInBits() != ArgVT.getScalarSizeInBits();
3513
3514 // This is an argument in memory. We might be able to perform copy elision.
3515 // If the argument is passed directly in memory without any extension, then we
3516 // can perform copy elision. Large vector types, for example, may be passed
3517 // indirectly by pointer.
3518 if (Flags.isCopyElisionCandidate() &&
3519 VA.getLocInfo() != CCValAssign::Indirect && !ExtendedInMem &&
3520 !ScalarizedAndExtendedVector) {
3521 SDValue PartAddr;
3522 if (Ins[i].PartOffset == 0) {
3523 // If this is a one-part value or the first part of a multi-part value,
3524 // create a stack object for the entire argument value type and return a
3525 // load from our portion of it. This assumes that if the first part of an
3526 // argument is in memory, the rest will also be in memory.
3527 int FI = MFI.CreateFixedObject(ArgVT.getStoreSize(), VA.getLocMemOffset(),
3528 /*IsImmutable=*/false);
3529 PartAddr = DAG.getFrameIndex(FI, PtrVT);
3530 return DAG.getLoad(
3531 ValVT, dl, Chain, PartAddr,
3532 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI));
3533 } else {
3534 // This is not the first piece of an argument in memory. See if there is
3535 // already a fixed stack object including this offset. If so, assume it
3536 // was created by the PartOffset == 0 branch above and create a load from
3537 // the appropriate offset into it.
3538 int64_t PartBegin = VA.getLocMemOffset();
3539 int64_t PartEnd = PartBegin + ValVT.getSizeInBits() / 8;
3540 int FI = MFI.getObjectIndexBegin();
3541 for (; MFI.isFixedObjectIndex(FI); ++FI) {
3542 int64_t ObjBegin = MFI.getObjectOffset(FI);
3543 int64_t ObjEnd = ObjBegin + MFI.getObjectSize(FI);
3544 if (ObjBegin <= PartBegin && PartEnd <= ObjEnd)
3545 break;
3546 }
3547 if (MFI.isFixedObjectIndex(FI)) {
3548 SDValue Addr =
3549 DAG.getNode(ISD::ADD, dl, PtrVT, DAG.getFrameIndex(FI, PtrVT),
3550 DAG.getIntPtrConstant(Ins[i].PartOffset, dl));
3551 return DAG.getLoad(
3552 ValVT, dl, Chain, Addr,
3553 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI,
3554 Ins[i].PartOffset));
3555 }
3556 }
3557 }
3558
3559 int FI = MFI.CreateFixedObject(ValVT.getSizeInBits() / 8,
3560 VA.getLocMemOffset(), isImmutable);
3561
3562 // Set SExt or ZExt flag.
3563 if (VA.getLocInfo() == CCValAssign::ZExt) {
3564 MFI.setObjectZExt(FI, true);
3565 } else if (VA.getLocInfo() == CCValAssign::SExt) {
3566 MFI.setObjectSExt(FI, true);
3567 }
3568
3569 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3570 SDValue Val = DAG.getLoad(
3571 ValVT, dl, Chain, FIN,
3572 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI));
3573 return ExtendedInMem
3574 ? (VA.getValVT().isVector()
3575 ? DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VA.getValVT(), Val)
3576 : DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val))
3577 : Val;
3578}
3579
3580// FIXME: Get this from tablegen.
3581static ArrayRef<MCPhysReg> get64BitArgumentGPRs(CallingConv::ID CallConv,
3582 const X86Subtarget &Subtarget) {
3583 assert(Subtarget.is64Bit())(static_cast <bool> (Subtarget.is64Bit()) ? void (0) : __assert_fail
("Subtarget.is64Bit()", "llvm/lib/Target/X86/X86ISelLowering.cpp"
, 3583, __extension__ __PRETTY_FUNCTION__))
;
3584
3585 if (Subtarget.isCallingConvWin64(CallConv)) {
3586 static const MCPhysReg GPR64ArgRegsWin64[] = {
3587 X86::RCX, X86::RDX, X86::R8, X86::R9
3588 };
3589 return makeArrayRef(std::begin(GPR64ArgRegsWin64), std::end(GPR64ArgRegsWin64));
3590 }
3591
3592 static const MCPhysReg GPR64ArgRegs64Bit[] = {
3593 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
3594 };
3595 return makeArrayRef(std::begin(GPR64ArgRegs64Bit), std::end(GPR64ArgRegs64Bit));
3596}
3597
3598// FIXME: Get this from tablegen.
3599static ArrayRef<MCPhysReg> get64BitArgumentXMMs(MachineFunction &MF,
3600 CallingConv::ID CallConv,
3601 const X86Subtarget &Subtarget) {
3602 assert(Subtarget.is64Bit())(static_cast <bool> (Subtarget.is64Bit()) ? void (0) : __assert_fail
("Subtarget.is64Bit()", "llvm/lib/Target/X86/X86ISelLowering.cpp"
, 3602, __extension__ __PRETTY_FUNCTION__))
;
3603 if (Subtarget.isCallingConvWin64(CallConv)) {
3604 // The XMM registers which might contain var arg parameters are shadowed
3605 // in their paired GPR. So we only need to save the GPR to their home
3606 // slots.
3607 // TODO: __vectorcall will change this.
3608 return None;
3609 }
3610
3611 bool isSoftFloat = Subtarget.useSoftFloat();
3612 if (isSoftFloat || !Subtarget.hasSSE1())
3613 // Kernel mode asks for SSE to be disabled, so there are no XMM argument
3614 // registers.
3615 return None;
3616
3617 static const MCPhysReg XMMArgRegs64Bit[] = {
3618 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
3619 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
3620 };
3621 return makeArrayRef(std::begin(XMMArgRegs64Bit), std::end(XMMArgRegs64Bit));
3622}
3623
3624#ifndef NDEBUG
3625static bool isSortedByValueNo(ArrayRef<CCValAssign> ArgLocs) {
3626 return llvm::is_sorted(
3627 ArgLocs, [](const CCValAssign &A, const CCValAssign &B) -> bool {
3628 return A.getValNo() < B.getValNo();
3629 });
3630}
3631#endif
3632
3633namespace {
3634/// This is a helper class for lowering variable arguments parameters.
3635class VarArgsLoweringHelper {
3636public:
3637 VarArgsLoweringHelper(X86MachineFunctionInfo *FuncInfo, const SDLoc &Loc,
3638 SelectionDAG &DAG, const X86Subtarget &Subtarget,
3639 CallingConv::ID CallConv, CCState &CCInfo)
3640 : FuncInfo(FuncInfo), DL(Loc), DAG(DAG), Subtarget(Subtarget),
3641 TheMachineFunction(DAG.getMachineFunction()),
3642 TheFunction(TheMachineFunction.getFunction()),
3643 FrameInfo(TheMachineFunction.getFrameInfo()),
3644 FrameLowering(*Subtarget.getFrameLowering()),
3645 TargLowering(DAG.getTargetLoweringInfo()), CallConv(CallConv),
3646 CCInfo(CCInfo) {}
3647
3648 // Lower variable arguments parameters.
3649 void lowerVarArgsParameters(SDValue &Chain, unsigned StackSize);
3650
3651private:
3652 void createVarArgAreaAndStoreRegisters(SDValue &Chain, unsigned StackSize);
3653
3654 void forwardMustTailParameters(SDValue &Chain);
3655
3656 bool is64Bit() const { return Subtarget.is64Bit(); }
3657 bool isWin64() const { return Subtarget.isCallingConvWin64(CallConv); }
3658
3659 X86MachineFunctionInfo *FuncInfo;
3660 const SDLoc &DL;
3661 SelectionDAG &DAG;
3662 const X86Subtarget &Subtarget;
3663 MachineFunction &TheMachineFunction;
3664 const Function &TheFunction;
3665 MachineFrameInfo &FrameInfo;
3666 const TargetFrameLowering &FrameLowering;
3667 const TargetLowering &TargLowering;
3668 CallingConv::ID CallConv;
3669 CCState &CCInfo;
3670};
3671} // namespace
3672
3673void VarArgsLoweringHelper::createVarArgAreaAndStoreRegisters(
3674 SDValue &Chain, unsigned StackSize) {
3675 // If the function takes variable number of arguments, make a frame index for
3676 // the start of the first vararg value... for expansion of llvm.va_start. We
3677 // can skip this if there are no va_start calls.
3678 if (is64Bit() || (CallConv != CallingConv::X86_FastCall &&
3679 CallConv != CallingConv::X86_ThisCall)) {
3680 FuncInfo->setVarArgsFrameIndex(
3681 FrameInfo.CreateFixedObject(1, StackSize, true));
3682 }
3683
3684 // 64-bit calling conventions support varargs and register parameters, so we
3685 // have to do extra work to spill them in the prologue.
3686 if (is64Bit()) {
3687 // Find the first unallocated argument registers.
3688 ArrayRef<MCPhysReg> ArgGPRs = get64BitArgumentGPRs(CallConv, Subtarget);
3689 ArrayRef<MCPhysReg> ArgXMMs =
3690 get64BitArgumentXMMs(TheMachineFunction, CallConv, Subtarget);
3691 unsigned NumIntRegs = CCInfo.getFirstUnallocated(ArgGPRs);
3692 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(ArgXMMs);
3693
3694 assert(!(NumXMMRegs && !Subtarget.hasSSE1()) &&(static_cast <bool> (!(NumXMMRegs && !Subtarget
.hasSSE1()) && "SSE register cannot be used when SSE is disabled!"
) ? void (0) : __assert_fail ("!(NumXMMRegs && !Subtarget.hasSSE1()) && \"SSE register cannot be used when SSE is disabled!\""
, "llvm/lib/Target/X86/X86ISelLowering.cpp", 3695, __extension__
__PRETTY_FUNCTION__))
3695 "SSE register cannot be used when SSE is disabled!")(static_cast <bool> (!(NumXMMRegs && !Subtarget
.hasSSE1()) && "SSE register cannot be used when SSE is disabled!"
) ? void (0) : __assert_fail ("!(NumXMMRegs && !Subtarget.hasSSE1()) && \"SSE register cannot be used when SSE is disabled!\""
, "llvm/lib/Target/X86/X86ISelLowering.cpp", 3695, __extension__
__PRETTY_FUNCTION__))
;
3696
3697 if (isWin64()) {
3698 // Get to the caller-allocated home save location. Add 8 to account
3699 // for the return address.
3700 int HomeOffset = FrameLowering.getOffsetOfLocalArea() + 8;
3701 FuncInfo->setRegSaveFrameIndex(
3702 FrameInfo.CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
3703 // Fixup to set vararg frame on shadow area (4 x i64).
3704 if (NumIntRegs < 4)
3705 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
3706 } else {
3707 // For X86-64, if there are vararg parameters that are passed via
3708 // registers, then we must store them to their spots on the stack so
3709 // they may be loaded by dereferencing the result of va_next.
3710 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
3711 FuncInfo->setVarArgsFPOffset(ArgGPRs.size() * 8 + NumXMMRegs * 16);
3712 FuncInfo->setRegSaveFrameIndex(FrameInfo.CreateStackObject(
3713 ArgGPRs.size() * 8 + ArgXMMs.size() * 16, Align(16), false));
3714 }
3715
3716 SmallVector<SDValue, 6>
3717 LiveGPRs; // list of SDValue for GPR registers keeping live input value
3718 SmallVector<SDValue, 8> LiveXMMRegs; // list of SDValue for XMM registers
3719 // keeping live input value
3720 SDValue ALVal; // if applicable keeps SDValue for %al register
3721
3722 // Gather all the live in physical registers.
3723 for (MCPhysReg Reg : ArgGPRs.slice(NumIntRegs)) {
3724 Register GPR = TheMachineFunction.addLiveIn(Reg, &X86::GR64RegClass);
3725 LiveGPRs.push_back(DAG.getCopyFromReg(Chain, DL, GPR, MVT::i64));
3726 }
3727 const auto &AvailableXmms = ArgXMMs.slice(NumXMMRegs);
3728 if (!AvailableXmms.empty()) {
3729 Register AL = TheMachineFunction.addLiveIn(X86::AL, &X86::GR8RegClass);
3730 ALVal = DAG.getCopyFromReg(Chain, DL, AL, MVT::i8);
3731 for (MCPhysReg Reg : AvailableXmms) {
3732 // FastRegisterAllocator spills virtual registers at basic
3733 // block boundary. That leads to usages of xmm registers
3734 // outside of check for %al. Pass physical registers to
3735 // VASTART_SAVE_XMM_REGS to avoid unneccessary spilling.
3736 TheMachineFunction.getRegInfo().addLiveIn(Reg);
3737 LiveXMMRegs.push_back(DAG.getRegister(Reg, MVT::v4f32));
3738 }
3739 }
3740
3741 // Store the integer parameter registers.
3742 SmallVector<SDValue, 8> MemOps;
3743 SDValue RSFIN =
3744 DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
3745 TargLowering.getPointerTy(DAG.getDataLayout()));
3746 unsigned Offset = FuncInfo->getVarArgsGPOffset();
3747 for (SDValue Val : LiveGPRs) {
3748 SDValue FIN = DAG.getNode(ISD::ADD, DL,
3749 TargLowering.getPointerTy(DAG.getDataLayout()),
3750 RSFIN, DAG.getIntPtrConstant(Offset, DL));
3751 SDValue Store =
3752 DAG.getStore(Val.getValue(1), DL, Val, FIN,
3753 MachinePointerInfo::getFixedStack(
3754 DAG.getMachineFunction(),
3755 FuncInfo->getRegSaveFrameIndex(), Offset));
3756 MemOps.push_back(Store);
3757 Offset += 8;
3758 }
3759
3760 // Now store the XMM (fp + vector) parameter registers.
3761 if (!LiveXMMRegs.empty()) {
3762 SmallVector<SDValue, 12> SaveXMMOps;
3763 SaveXMMOps.push_back(Chain);
3764 SaveXMMOps.push_back(ALVal);
3765 SaveXMMOps.push_back(RSFIN);
3766 SaveXMMOps.push_back(
3767 DAG.getTargetConstant(FuncInfo->getVarArgsFPOffset(), DL, MVT::i32));
3768 llvm::append_range(SaveXMMOps, LiveXMMRegs);
3769 MachineMemOperand *StoreMMO =
3770 DAG.getMachineFunction().getMachineMemOperand(
3771 MachinePointerInfo::getFixedStack(
3772 DAG.getMachineFunction(), FuncInfo->getRegSaveFrameIndex(),
3773 Offset),
3774 MachineMemOperand::MOStore, 128, Align(16));
3775 MemOps.push_back(DAG.getMemIntrinsicNode(X86ISD::VASTART_SAVE_XMM_REGS,
3776 DL, DAG.getVTList(MVT::Other),
3777 SaveXMMOps, MVT::i8, StoreMMO));
3778 }
3779
3780 if (!MemOps.empty())
3781 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
3782 }
3783}
3784
3785void VarArgsLoweringHelper::forwardMustTailParameters(SDValue &Chain) {
3786 // Find the largest legal vector type.
3787 MVT VecVT = MVT::Other;
3788 // FIXME: Only some x86_32 calling conventions support AVX512.
3789 if (Subtarget.useAVX512Regs() &&
3790 (is64Bit() || (CallConv == CallingConv::X86_VectorCall ||
3791 CallConv == CallingConv::Intel_OCL_BI)))
3792 VecVT = MVT::v16f32;
3793 else if (Subtarget.hasAVX())
3794 VecVT = MVT::v8f32;
3795 else if (Subtarget.hasSSE2())
3796 VecVT = MVT::v4f32;
3797
3798 // We forward some GPRs and some vector types.
3799 SmallVector<MVT, 2> RegParmTypes;
3800 MVT IntVT = is64Bit() ? MVT::i64 : MVT::i32;
3801 RegParmTypes.push_back(IntVT);
3802 if (VecVT != MVT::Other)
3803 RegParmTypes.push_back(VecVT);
3804
3805 // Compute the set of forwarded registers. The rest are scratch.
3806 SmallVectorImpl<ForwardedRegister> &Forwards =
3807 FuncInfo->getForwardedMustTailRegParms();
3808 CCInfo.analyzeMustTailForwardedRegisters(Forwards, RegParmTypes, CC_X86);
3809
3810 // Forward AL for SysV x86_64 targets, since it is used for varargs.
3811 if (is64Bit() && !isWin64() && !CCInfo.isAllocated(X86::AL)) {
3812 Register ALVReg = TheMachineFunction.addLiveIn(X86::AL, &X86::GR8RegClass);
3813 Forwards.push_back(ForwardedRegister(ALVReg, X86::AL, MVT::i8));
3814 }
3815
3816 // Copy all forwards from physical to virtual registers.
3817 for (ForwardedRegister &FR : Forwards) {
3818 // FIXME: Can we use a less constrained schedule?
3819 SDValue RegVal = DAG.getCopyFromReg(Chain, DL, FR.VReg, FR.VT);
3820 FR.VReg = TheMachineFunction.getRegInfo().createVirtualRegister(
3821 TargLowering.getRegClassFor(FR.VT));
3822 Chain = DAG.getCopyToReg(Chain, DL, FR.VReg, RegVal);
3823 }
3824}
3825
3826void VarArgsLoweringHelper::lowerVarArgsParameters(SDValue &Chain,
3827 unsigned StackSize) {
3828 // Set FrameIndex to the 0xAAAAAAA value to mark unset state.
3829 // If necessary, it would be set into the correct value later.
3830 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
3831 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
3832
3833 if (FrameInfo.hasVAStart())
3834 createVarArgAreaAndStoreRegisters(Chain, StackSize);
3835
3836 if (FrameInfo.hasMustTailInVarArgFunc())
3837 forwardMustTailParameters(Chain);
3838}
3839
3840SDValue X86TargetLowering::LowerFormalArguments(
3841 SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
3842 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
3843 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
3844 MachineFunction &MF = DAG.getMachineFunction();
3845 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
3846
3847 const Function &F = MF.getFunction();
3848 if (F.hasExternalLinkage() && Subtarget.isTargetCygMing() &&
3849 F.getName() == "main")
3850 FuncInfo->setForceFramePointer(true);
3851
3852 MachineFrameInfo &MFI = MF.getFrameInfo();
3853 bool Is64Bit = Subtarget.is64Bit();
3854 bool IsWin64 = Subtarget.isCallingConvWin64(CallConv);
3855
3856 assert((static_cast <bool> (!(IsVarArg && canGuaranteeTCO
(CallConv)) && "Var args not supported with calling conv' regcall, fastcc, ghc or hipe"
) ? void (0) : __assert_fail ("!(IsVarArg && canGuaranteeTCO(CallConv)) && \"Var args not supported with calling conv' regcall, fastcc, ghc or hipe\""
, "llvm/lib/Target/X86/X86ISelLowering.cpp", 3858, __extension__
__PRETTY_FUNCTION__))
3857 !(IsVarArg && canGuaranteeTCO(CallConv)) &&(static_cast <bool> (!(IsVarArg && canGuaranteeTCO
(CallConv)) && "Var args not supported with calling conv' regcall, fastcc, ghc or hipe"
) ? void (0) : __assert_fail ("!(IsVarArg && canGuaranteeTCO(CallConv)) && \"Var args not supported with calling conv' regcall, fastcc, ghc or hipe\""
, "llvm/lib/Target/X86/X86ISelLowering.cpp", 3858, __extension__
__PRETTY_FUNCTION__))
3858 "Var args not supported with calling conv' regcall, fastcc, ghc or hipe")(static_cast <bool> (!(IsVarArg && canGuaranteeTCO
(CallConv)) && "Var args not supported with calling conv' regcall, fastcc, ghc or hipe"
) ? void (0) : __assert_fail ("!(IsVarArg && canGuaranteeTCO(CallConv)) && \"Var args not supported with calling conv' regcall, fastcc, ghc or hipe\""
, "llvm/lib/Target/X86/X86ISelLowering.cpp", 3858, __extension__
__PRETTY_FUNCTION__))
;
3859
3860 // Assign locations to all of the incoming arguments.
3861 SmallVector<CCValAssign, 16> ArgLocs;
3862 CCState CCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext());
3863
3864 // Allocate shadow area for Win64.
3865 if (IsWin64)
3866 CCInfo.AllocateStack(32, Align(8));
3867
3868 CCInfo.AnalyzeArguments(Ins, CC_X86);
3869
3870 // In vectorcall calling convention a second pass is required for the HVA
3871 // types.
3872 if (CallingConv::X86_VectorCall == CallConv) {
3873 CCInfo.AnalyzeArgumentsSecondPass(Ins, CC_X86);
3874 }
3875
3876 // The next loop assumes that the locations are in the same order of the
3877 // input arguments.
3878 assert(isSortedByValueNo(ArgLocs) &&(static_cast <bool> (isSortedByValueNo(ArgLocs) &&
"Argument Location list must be sorted before lowering") ? void
(0) : __assert_fail ("isSortedByValueNo(ArgLocs) && \"Argument Location list must be sorted before lowering\""
, "llvm/lib/Target/X86/X86ISelLowering.cpp", 3879, __extension__
__PRETTY_FUNCTION__))
3879 "Argument Location list must be sorted before lowering")(static_cast <bool> (isSortedByValueNo(ArgLocs) &&
"Argument Location list must be sorted before lowering") ? void
(0) : __assert_fail ("isSortedByValueNo(ArgLocs) && \"Argument Location list must be sorted before lowering\""
, "llvm/lib/Target/X86/X86ISelLowering.cpp", 3879, __extension__
__PRETTY_FUNCTION__))
;
3880
3881 SDValue ArgValue;
3882 for (unsigned I = 0, InsIndex = 0, E = ArgLocs.size(); I != E;
3883 ++I, ++InsIndex) {
3884 assert(InsIndex < Ins.size() && "Invalid Ins index")(static_cast <bool> (InsIndex < Ins.size() &&
"Invalid Ins index") ? void (0) : __assert_fail ("InsIndex < Ins.size() && \"Invalid Ins index\""
, "llvm/lib/Target/X86/X86ISelLowering.cpp", 3884, __extension__
__PRETTY_FUNCTION__))
;
3885 CCValAssign &VA = ArgLocs[I];
3886
3887 if (VA.isRegLoc()) {
3888 EVT RegVT = VA.getLocVT();
3889 if (VA.needsCustom()) {
3890 assert((static_cast <bool> (VA.getValVT() == MVT::v64i1 &&
"Currently the only custom case is when we split v64i1 to 2 regs"
) ? void (0) : __assert_fail ("VA.getValVT() == MVT::v64i1 && \"Currently the only custom case is when we split v64i1 to 2 regs\""
, "llvm/lib/Target/X86/X86ISelLowering.cpp", 3892, __extension__
__PRETTY_FUNCTION__))
3891 VA.getValVT() == MVT::v64i1 &&(static_cast <bool> (VA.getValVT() == MVT::v64i1 &&
"Currently the only custom case is when we split v64i1 to 2 regs"
) ? void (0) : __assert_fail ("VA.getValVT() == MVT::v64i1 && \"Currently the only custom case is when we split v64i1 to 2 regs\""
, "llvm/lib/Target/X86/X86ISelLowering.cpp", 3892, __extension__
__PRETTY_FUNCTION__))
3892 "Currently the only custom case is when we split v64i1 to 2 regs")(static_cast <bool> (VA.getValVT() == MVT::v64i1 &&
"Currently the only custom case is when we split v64i1 to 2 regs"
) ? void (0) : __assert_fail ("VA.getValVT() == MVT::v64i1 && \"Currently the only custom case is when we split v64i1 to 2 regs\""
, "llvm/lib/Target/X86/X86ISelLowering.cpp", 3892, __extension__
__PRETTY_FUNCTION__))
;
3893
3894 // v64i1 values, in regcall calling convention, that are
3895 // compiled to 32 bit arch, are split up into two registers.
3896 ArgValue =
3897 getv64i1Argument(VA, ArgLocs[++I], Chain, DAG, dl, Subtarget);
3898 } else {
3899 const TargetRegisterClass *RC;
3900 if (RegVT == MVT::i8)
3901 RC = &X86::GR8RegClass;
3902 else if (RegVT == MVT::i16)
3903 RC = &X86::GR16RegClass;
3904 else if (RegVT == MVT::i32)
3905 RC = &X86::GR32RegClass;
3906 else if (Is64Bit && RegVT == MVT::i64)
3907 RC = &X86::GR64RegClass;
3908 else if (RegVT == MVT::f16)
3909 RC = &X86::FR16XRegClass;
3910 else if (RegVT == MVT::f32)
3911 RC = Subtarget.hasAVX512() ? &X86::FR32XRegClass : &X86::FR32RegClass;
3912 else if (RegVT == MVT::f64)
3913 RC = Subtarget.hasAVX512() ? &X86::FR64XRegClass : &X86::FR64RegClass;
3914 else if (RegVT == MVT::f80)
3915 RC = &X86::RFP80RegClass;
3916 else if (RegVT == MVT::f128)
3917 RC = &X86::VR128RegClass;
3918 else if (RegVT.is512BitVector())
3919 RC = &X86::VR512RegClass;
3920 else if (RegVT.is256BitVector())
3921 RC = Subtarget.hasVLX() ? &X86::VR256XRegClass : &X86::VR256RegClass;
3922 else if (RegVT.is128BitVector())
3923 RC = Subtarget.hasVLX() ? &X86::VR128XRegClass : &X86::VR128RegClass;
3924 else if (RegVT == MVT::x86mmx)
3925 RC = &X86::VR64RegClass;
3926 else if (RegVT == MVT::v1i1)
3927 RC = &X86::VK1RegClass;
3928 else if (RegVT == MVT::v8i1)
3929 RC = &X86::VK8RegClass;
3930 else if (RegVT == MVT::v16i1)
3931 RC = &X86::VK16RegClass;
3932 else if (RegVT == MVT::v32i1)
3933 RC = &X86::VK32RegClass;
3934 else if (RegVT == MVT::v64i1)
3935 RC = &X86::VK64RegClass;
3936 else
3937 llvm_unreachable("Unknown argument type!")::llvm::llvm_unreachable_internal("Unknown argument type!", "llvm/lib/Target/X86/X86ISelLowering.cpp"
, 3937)
;
3938
3939 Register Reg = MF.addLiveIn(VA.getLocReg(), RC);
3940 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
3941 }
3942
3943 // If this is an 8 or 16-bit value, it is really passed promoted to 32
3944 // bits. Insert an assert[sz]ext to capture this, then truncate to the
3945 // right size.
3946 if (VA.getLocInfo() == CCValAssign::SExt)
3947 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
3948 DAG.getValueType(VA.getValVT()));
3949 else if (VA.getLocInfo() == CCValAssign::ZExt)
3950 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
3951 DAG.getValueType(VA.getValVT()));
3952 else if (VA.getLocInfo() == CCValAssign::BCvt)
3953 ArgValue = DAG.getBitcast(VA.getValVT(), ArgValue);
3954
3955 if (VA.isExtInLoc()) {
3956 // Handle MMX values passed in XMM regs.
3957 if (RegVT.isVector() && VA.getValVT().getScalarType() != MVT::i1)
3958 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), ArgValue);
3959 else if (VA.getValVT().isVector() &&
3960 VA.getValVT().getScalarType() == MVT::i1 &&
3961 ((VA.getLocVT() == MVT::i64) || (VA.getLocVT() == MVT::i32) ||
3962 (VA.getLocVT() == MVT::i16) || (VA.getLocVT() == MVT::i8))) {
3963 // Promoting a mask type (v*i1) into a register of type i64/i32/i16/i8
3964 ArgValue = lowerRegToMasks(ArgValue, VA.getValVT(), RegVT, dl, DAG);
3965 } else
3966 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
3967 }
3968 } else {
3969 assert(VA.isMemLoc())(static_cast <bool> (VA.isMemLoc()) ? void (0) : __assert_fail
("VA.isMemLoc()", "llvm/lib/Target/X86/X86ISelLowering.cpp",
3969, __extension__ __PRETTY_FUNCTION__))
;
3970 ArgValue =
3971 LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, InsIndex);
3972 }
3973
3974 // If value is passed via pointer - do a load.
3975 if (VA.getLocInfo() == CCValAssign::Indirect && !Ins[I].Flags.isByVal())
3976 ArgValue =
3977 DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue, MachinePointerInfo());
3978
3979 InVals.push_back(ArgValue);
3980 }
3981
3982 for (unsigned I = 0, E = Ins.size(); I != E; ++I) {
3983 if (Ins[I].Flags.isSwiftAsync()) {
3984 auto X86FI = MF.getInfo<X86MachineFunctionInfo>();
3985 if (Subtarget.is64Bit())
3986 X86FI->setHasSwiftAsyncContext(true);
3987 else {
3988 int FI = MF.getFrameInfo().CreateStackObject(4, Align(4), false);
3989 X86FI->setSwiftAsyncContextFrameIdx(FI);
3990 SDValue St = DAG.getStore(DAG.getEntryNode(), dl, InVals[I],
3991 DAG.getFrameIndex(FI, MVT::i32),
3992 MachinePointerInfo::getFixedStack(MF, FI));
3993 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, St, Chain);
3994 }
3995 }
3996
3997 // Swift calling convention does not require we copy the sret argument
3998 // into %rax/%eax for the return. We don't set SRetReturnReg for Swift.
3999 if (CallConv == CallingConv::Swift || CallConv == CallingConv::SwiftTail)
4000 continue;
4001
4002 // All x86 ABIs require that for returning structs by value we copy the
4003 // sret argument into %rax/%eax (depending on ABI) for the return. Save
4004 // the argument into a virtual register so that we can access it from the
4005 // return points.
4006 if (Ins[I].Flags.isSRet()) {
4007 assert(!FuncInfo->getSRetReturnReg() &&(static_cast <bool> (!FuncInfo->getSRetReturnReg() &&
"SRet return has already been set") ? void (0) : __assert_fail
("!FuncInfo->getSRetReturnReg() && \"SRet return has already been set\""
, "llvm/lib/Target/X86/X86ISelLowering.cpp", 4008, __extension__
__PRETTY_FUNCTION__))
4008 "SRet return has already been set")(static_cast <bool> (!FuncInfo->getSRetReturnReg() &&
"SRet return has already been set") ? void (0) : __assert_fail
("!FuncInfo->getSRetReturnReg() && \"SRet return has already been set\""
, "llvm/lib/Target/X86/X86ISelLowering.cpp", 4008, __extension__
__PRETTY_FUNCTION__))
;
4009 MVT PtrTy = getPointerTy(DAG.getDataLayout());
4010 Register Reg =
4011 MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy));
4012 FuncInfo->setSRetReturnReg(Reg);
4013 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[I]);
4014 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
4015 break;
4016 }
4017 }
4018
4019 unsigned StackSize = CCInfo.getNextStackOffset();
4020 // Align stack specially for tail calls.
4021 if (shouldGuaranteeTCO(CallConv,
4022 MF.getTarget().Options.GuaranteedTailCallOpt))
4023 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
4024
4025 if (IsVarArg)
4026 VarArgsLoweringHelper(FuncInfo, dl, DAG, Subtarget, CallConv, CCInfo)
4027 .lowerVarArgsParameters(Chain, StackSize);
4028
4029 // Some CCs need callee pop.
4030 if (X86::isCalleePop(CallConv, Is64Bit, IsVarArg,
4031 MF.getTarget().Options.GuaranteedTailCallOpt)) {
4032 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
4033 } else if (CallConv == CallingConv::X86_INTR && Ins.size() == 2) {
4034 // X86 interrupts must pop the error code (and the alignment padding) if
4035 // present.
4036 FuncInfo->setBytesToPopOnReturn(Is64Bit ? 16 : 4);
4037 } else {
4038 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
4039 // If this is an sret function, the return should pop the hidden pointer.
4040 if (!canGuaranteeTCO(CallConv) && hasCalleePopSRet(Ins, Subtarget))
4041 FuncInfo->setBytesToPopOnReturn(4);
4042 }
4043
4044 if (!Is64Bit) {
4045 // RegSaveFrameIndex is X86-64 only.
4046 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
4047 }
4048
4049 FuncInfo->setArgumentStackSize(StackSize);
4050
4051 if (WinEHFuncInfo *EHInfo = MF.getWinEHFuncInfo()) {
4052 EHPersonality Personality = classifyEHPersonality(F.getPersonalityFn());
4053 if (Personality == EHPersonality::CoreCLR) {
4054 assert(Is64Bit)(static_cast <bool> (Is64Bit) ? void (0) : __assert_fail
("Is64Bit", "llvm/lib/Target/X86/X86ISelLowering.cpp", 4054,
__extension__ __PRETTY_FUNCTION__))
;
4055 // TODO: Add a mechanism to frame lowering that will allow us to indicate
4056 // that we'd prefer this slot be allocated towards the bottom of the frame
4057 // (i.e. near the stack pointer after allocating the frame). Every
4058 // funclet needs a copy of this slot in its (mostly empty) frame, and the
4059 // offset from the bottom of this and each funclet's frame must be the
4060 // same, so the size of funclets' (mostly empty) frames is dictated by
4061 // how far this slot is from the bottom (since they allocate just enough
4062 // space to accommodate holding this slot at the correct offset).
4063 int PSPSymFI = MFI.CreateStackObject(8, Align(8), /*isSpillSlot=*/false);
4064 EHInfo->PSPSymFrameIdx = PSPSymFI;
4065 }
4066 }
4067
4068 if (CallConv == CallingConv::X86_RegCall ||
4069 F.hasFnAttribute("no_caller_saved_registers")) {
4070 MachineRegisterInfo &MRI = MF.getRegInfo();
4071 for (std::pair<Register, Register> Pair : MRI.liveins())
4072 MRI.disableCalleeSavedRegister(Pair.first);
4073 }
4074
4075 return Chain;
4076}
4077
4078SDValue X86TargetLowering::LowerMemOpCallTo(SDValue Chain, SDValue StackPtr,
4079 SDValue Arg, const SDLoc &dl,
4080 SelectionDAG &DAG,
4081 const CCValAssign &VA,
4082 ISD::ArgFlagsTy Flags,
4083 bool isByVal) const {
4084 unsigned LocMemOffset = VA.getLocMemOffset();
4085 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset, dl);
4086 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(DAG.getDataLayout()),
4087 StackPtr, PtrOff);
4088 if (isByVal)
4089 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
4090
4091 return DAG.getStore(
4092 Chain, dl, Arg, PtrOff,
4093 MachinePointerInfo::getStack(DAG.getMachineFunction(), LocMemOffset));
4094}
4095
4096/// Emit a load of return address if tail call
4097/// optimization is performed and it is required.
4098SDValue X86TargetLowering::EmitTailCallLoadRetAddr(
4099 SelectionDAG &DAG, SDValue &OutRetAddr, SDValue Chain, bool IsTailCall,
4100 bool Is64Bit, int FPDiff, const SDLoc &dl) const {
4101 // Adjust the Return address stack slot.
4102 EVT VT = getPointerTy(DAG.getDataLayout());
4103 OutRetAddr = getReturnAddressFrameIndex(DAG);
4104
4105 // Load the "old" Return address.
4106 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo());
4107 return SDValue(OutRetAddr.getNode(), 1);
4108}
4109
4110/// Emit a store of the return address if tail call
4111/// optimization is performed and it is required (FPDiff!=0).
4112static SDValue EmitTailCallStoreRetAddr(SelectionDAG &DAG, MachineFunction &MF,
4113 SDValue Chain, SDValue RetAddrFrIdx,
4114 EVT PtrVT, unsigned SlotSize,
4115 int FPDiff, const SDLoc &dl) {
4116 // Store the return address to the appropriate stack slot.
4117 if (!FPDiff) return Chain;
4118 // Calculate the new stack slot for the return address.
4119 int NewReturnAddrFI =
4120 MF.getFrameInfo().CreateFixedObject(SlotSize, (int64_t)FPDiff - SlotSize,
4121 false);
4122 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, PtrVT);
4123 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
4124 MachinePointerInfo::getFixedStack(
4125 DAG.getMachineFunction(), NewReturnAddrFI));
4126 return Chain;
4127}
4128
4129/// Returns a vector_shuffle mask for an movs{s|d}, movd
4130/// operation of specified width.
4131static SDValue getMOVL(SelectionDAG &DAG, const SDLoc &dl, MVT VT, SDValue V1,
4132 SDValue V2) {
4133 unsigned NumElems = VT.getVectorNumElements();
4134 SmallVector<int, 8> Mask;
4135 Mask.push_back(NumElems);
4136 for (unsigned i = 1; i != NumElems; ++i)
4137 Mask.push_back(i);
4138 return DAG.getVectorShuffle(VT, dl, V1, V2, Mask);
4139}
4140
4141SDValue
4142X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
4143 SmallVectorImpl<SDValue> &InVals) const {
4144 SelectionDAG &DAG = CLI.DAG;
4145 SDLoc &dl = CLI.DL;
4146 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
4147 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
4148 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
4149 SDValue Chain = CLI.Chain;
4150 SDValue Callee = CLI.Callee;
4151 CallingConv::ID CallConv = CLI.CallConv;
4152 bool &isTailCall = CLI.IsTailCall;
4153 bool isVarArg = CLI.IsVarArg;
4154 const auto *CB = CLI.CB;
4155
4156 MachineFunction &MF = DAG.getMachineFunction();
4157 bool Is64Bit = Subtarget.is64Bit();
4158 bool IsWin64 = Subtarget.isCallingConvWin64(CallConv);
4159 bool IsSibcall = false;
4160 bool IsGuaranteeTCO = MF.getTarget().Options.GuaranteedTailCallOpt ||
4161 CallConv == CallingConv::Tail || CallConv == CallingConv::SwiftTail;
4162 bool IsCalleePopSRet = !IsGuaranteeTCO && hasCalleePopSRet(Outs, Subtarget);
4163 X86MachineFunctionInfo *X86Info = MF.getInfo<X86MachineFunctionInfo>();
4164 bool HasNCSR = (CB && isa<CallInst>(CB) &&
4165 CB->hasFnAttr("no_caller_saved_registers"));
4166 bool HasNoCfCheck = (CB && CB->doesNoCfCheck());
4167 bool IsIndirectCall = (CB && isa<CallInst>(CB) && CB->isIndirectCall());
4168 const Module *M = MF.getMMI().getModule();
4169 Metadata *IsCFProtectionSupported = M->getModuleFlag("cf-protection-branch");
4170
4171 MachineFunction::CallSiteInfo CSInfo;
4172 if (CallConv == CallingConv::X86_INTR)
4173 report_fatal_error("X86 interrupts may not be called directly");
4174
4175 bool IsMustTail = CLI.CB && CLI.CB->isMustTailCall();
4176 if (Subtarget.isPICStyleGOT() && !IsGuaranteeTCO && !IsMustTail) {
4177 // If we are using a GOT, disable tail calls to external symbols with
4178 // default visibility. Tail calling such a symbol requires using a GOT
4179 // relocation, which forces early binding of the symbol. This breaks code
4180 // that require lazy function symbol resolution. Using musttail or
4181 // GuaranteedTailCallOpt will override this.
4182 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
4183 if (!G || (!G->getGlobal()->hasLocalLinkage() &&
4184 G->getGlobal()->hasDefaultVisibility()))
4185 isTailCall = false;
4186 }
4187
4188 if (isTailCall && !IsMustTail) {
4189 // Check if it's really possible to do a tail call.
4190 isTailCall = IsEligibleForTailCallOptimization(
4191 Callee, CallConv, IsCalleePopSRet, isVarArg, CLI.RetTy, Outs, OutVals,
4192 Ins, DAG);
4193
4194 // Sibcalls are automatically detected tailcalls which do not require
4195 // ABI changes.
4196 if (!IsGuaranteeTCO && isTailCall)
4197 IsSibcall = true;
4198
4199 if (isTailCall)
4200 ++NumTailCalls;
4201 }
4202
4203 if (IsMustTail && !isTailCall)
4204 report_fatal_error("failed to perform tail call elimination on a call "
4205 "site marked musttail");
4206
4207 assert(!(isVarArg && canGuaranteeTCO(CallConv)) &&(static_cast <bool> (!(isVarArg && canGuaranteeTCO
(CallConv)) && "Var args not supported with calling convention fastcc, ghc or hipe"
) ? void (0) : __assert_fail ("!(isVarArg && canGuaranteeTCO(CallConv)) && \"Var args not supported with calling convention fastcc, ghc or hipe\""
, "llvm/lib/Target/X86/X86ISelLowering.cpp", 4208, __extension__
__PRETTY_FUNCTION__))
4208 "Var args not supported with calling convention fastcc, ghc or hipe")(static_cast <bool> (!(isVarArg && canGuaranteeTCO
(CallConv)) && "Var args not supported with calling convention fastcc, ghc or hipe"
) ? void (0) : __assert_fail ("!(isVarArg && canGuaranteeTCO(CallConv)) && \"Var args not supported with calling convention fastcc, ghc or hipe\""
, "llvm/lib/Target/X86/X86ISelLowering.cpp", 4208, __extension__
__PRETTY_FUNCTION__))
;
4209
4210 // Analyze operands of the call, assigning locations to each operand.
4211 SmallVector<CCValAssign, 16> ArgLocs;
4212 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
4213
4214 // Allocate shadow area for Win64.
4215 if (IsWin64)
4216 CCInfo.AllocateStack(32, Align(8));
4217
4218 CCInfo.AnalyzeArguments(Outs, CC_X86);
4219
4220 // In vectorcall calling convention a second pass is required for the HVA
4221 // types.
4222 if (CallingConv::X86_VectorCall == CallConv) {
4223 CCInfo.AnalyzeArgumentsSecondPass(Outs, CC_X86);
4224 }
4225
4226 // Get a count of how many bytes are to be pushed on the stack.
4227 unsigned NumBytes = CCInfo.getAlignedCallFrameSize();
4228 if (IsSibcall)
4229 // This is a sibcall. The memory operands are available in caller's
4230 // own caller's stack.
4231 NumBytes = 0;
4232 else if (IsGuaranteeTCO && canGuaranteeTCO(CallConv))
4233 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
4234
4235 int FPDiff = 0;
4236 if (isTailCall &&
4237 shouldGuaranteeTCO(CallConv,
4238 MF.getTarget().Options.GuaranteedTailCallOpt)) {
4239 // Lower arguments at fp - stackoffset + fpdiff.
4240 unsigned NumBytesCallerPushed = X86Info->getBytesToPopOnReturn();
4241
4242 FPDiff = NumBytesCallerPushed - NumBytes;
4243
4244 // Set the delta of movement of the returnaddr stackslot.
4245 // But only set if delta is greater than previous delta.
4246 if (FPDiff < X86Info->getTCReturnAddrDelta())
4247 X86Info->setTCReturnAddrDelta(FPDiff);
4248 }
4249
4250 unsigned NumBytesToPush = NumBytes;
4251 unsigned NumBytesToPop = NumBytes;
4252
4253 // If we have an inalloca argument, all stack space has already been allocated
4254 // for us and be right at the top of the stack. We don't support multiple
4255 // arguments passed in memory when using inalloca.
4256 if (!Outs.empty() && Outs.back().Flags.isInAlloca()) {
4257 NumBytesToPush = 0;
4258 if (!ArgLocs.back().isMemLoc())
4259 report_fatal_error("cannot use inalloca attribute on a register "
4260 "parameter");
4261 if (ArgLocs.back().getLocMemOffset() != 0)
4262 report_fatal_error("any parameter with the inalloca attribute must be "
4263 "the only memory argument");
4264 } else if (CLI.IsPreallocated) {
4265 assert(ArgLocs.back().isMemLoc() &&(static_cast <bool> (ArgLocs.back().isMemLoc() &&
"cannot use preallocated attribute on a register " "parameter"
) ? void (0) : __assert_fail ("ArgLocs.back().isMemLoc() && \"cannot use preallocated attribute on a register \" \"parameter\""
, "llvm/lib/Target/X86/X86ISelLowering.cpp", 4267, __extension__
__PRETTY_FUNCTION__))
4266 "cannot use preallocated attribute on a register "(static_cast <bool> (ArgLocs.back().isMemLoc() &&
"cannot use preallocated attribute on a register " "parameter"
) ? void (0) : __assert_fail ("ArgLocs.back().isMemLoc() && \"cannot use preallocated attribute on a register \" \"parameter\""
, "llvm/lib/Target/X86/X86ISelLowering.cpp", 4267, __extension__
__PRETTY_FUNCTION__))
4267 "parameter")(static_cast <bool> (ArgLocs.back().isMemLoc() &&
"cannot use preallocated attribute on a register " "parameter"
) ? void (0) : __assert_fail ("ArgLocs.back().isMemLoc() && \"cannot use preallocated attribute on a register \" \"parameter\""
, "llvm/lib/Target/X86/X86ISelLowering.cpp", 4267, __extension__
__PRETTY_FUNCTION__))
;
4268 SmallVector<size_t, 4> PreallocatedOffsets;
4269 for (size_t i = 0; i < CLI.OutVals.size(); ++i) {
4270 if (CLI.CB->paramHasAttr(i, Attribute::Preallocated)) {
4271 PreallocatedOffsets.push_back(ArgLocs[i].getLocMemOffset());
4272 }
4273 }
4274 auto *MFI = DAG.getMachineFunction().getInfo<X86MachineFunctionInfo>();
4275 size_t PreallocatedId = MFI->getPreallocatedIdForCallSite(CLI.CB);
4276 MFI->setPreallocatedStackSize(PreallocatedId, NumBytes);
4277 MFI->setPreallocatedArgOffsets(PreallocatedId, PreallocatedOffsets);
4278 NumBytesToPush = 0;
4279 }
4280
4281 if (!IsSibcall && !IsMustTail)
4282 Chain = DAG.getCALLSEQ_START(Chain, NumBytesToPush,
4283 NumBytes - NumBytesToPush, dl);
4284
4285 SDValue RetAddrFrIdx;
4286 // Load return address for tail calls.
4287 if (isTailCall && FPDiff)
4288 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
4289 Is64Bit, FPDiff, dl);
4290
4291 SmallVector<std::pair<Register, SDValue>, 8> RegsToPass;
4292 SmallVector<SDValue, 8> MemOpChains;
4293 SDValue StackPtr;
4294
4295 // The next loop assumes that the locations are in the same order of the
4296 // input arguments.
4297 assert(isSortedByValueNo(ArgLocs) &&(static_cast <bool> (isSortedByValueNo(ArgLocs) &&
"Argument Location list must be sorted before lowering") ? void
(0) : __assert_fail ("isSortedByValueNo(ArgLocs) && \"Argument Location list must be sorted before lowering\""
, "llvm/lib/Target/X86/X86ISelLowering.cpp", 4298, __extension__
__PRETTY_FUNCTION__))
4298 "Argument Location list must be sorted before lowering")(static_cast <bool> (isSortedByValueNo(ArgLocs) &&
"Argument Location list must be sorted before lowering") ? void
(0) : __assert_fail ("isSortedByValueNo(ArgLocs) && \"Argument Location list must be sorted before lowering\""
, "llvm/lib/Target/X86/X86ISelLowering.cpp", 4298, __extension__
__PRETTY_FUNCTION__))
;
4299
4300 // Walk the register/memloc assignments, inserting copies/loads. In the case
4301 // of tail call optimization arguments are handle later.
4302 const X86RegisterInfo *RegInfo = Subtarget.getRegisterInfo();
4303 for (unsigned I = 0, OutIndex = 0, E = ArgLocs.size(); I != E;
4304 ++I, ++OutIndex) {
4305 assert(OutIndex < Outs.size() && "Invalid Out index")(static_cast <bool> (OutIndex < Outs.size() &&
"Invalid Out index") ? void (0) : __assert_fail ("OutIndex < Outs.size() && \"Invalid Out index\""
, "llvm/lib/Target/X86/X86ISelLowering.cpp", 4305, __extension__
__PRETTY_FUNCTION__))
;
4306 // Skip inalloca/preallocated arguments, they have already been written.
4307 ISD::ArgFlagsTy Flags = Outs[OutIndex].Flags;
4308 if (Flags.isInAlloca() || Flags.isPreallocated())
4309 continue;
4310
4311 CCValAssign &VA = ArgLocs[I];
4312 EVT RegVT = VA.getLocVT();
4313 SDValue Arg = OutVals[OutIndex];
4314 bool isByVal = Flags.isByVal();
4315
4316 // Promote the value if needed.
4317 switch (VA.getLocInfo()) {
4318 default: llvm_unreachable("Unknown loc info!")::llvm::llvm_unreachable_internal("Unknown loc info!", "llvm/lib/Target/X86/X86ISelLowering.cpp"
, 4318)
;
4319 case CCValAssign::Full: break;
4320 case CCValAssign::SExt:
4321 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
4322 break;
4323 case CCValAssign::ZExt:
4324 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
4325 break;
4326 case CCValAssign::AExt:
4327 if (Arg.getValueType().isVector() &&
4328 Arg.getValueType().getVectorElementType() == MVT::i1)
4329 Arg = lowerMasksToReg(Arg, RegVT, dl, DAG);
4330 else if (RegVT.is128BitVector()) {
4331 // Special case: passing MMX values in XMM registers.
4332 Arg = DAG.getBitcast(MVT::i64, Arg);
4333 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
4334 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
4335 } else
4336 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
4337 break;
4338 case CCValAssign::BCvt:
4339 Arg = DAG.getBitcast(RegVT, Arg);
4340 break;
4341 case CCValAssign::Indirect: {
4342 if (isByVal) {
4343 // Memcpy the argument to a temporary stack slot to prevent
4344 // the caller from seeing any modifications the callee may make
4345 // as guaranteed by the `byval` attribute.
4346 int FrameIdx = MF.getFrameInfo().CreateStackObject(
4347 Flags.getByValSize(),
4348 std::max(Align(16), Flags.getNonZeroByValAlign()), false);
4349 SDValue StackSlot =
4350 DAG.getFrameIndex(FrameIdx, getPointerTy(DAG.getDataLayout()));
4351 Chain =
4352 CreateCopyOfByValArgument(Arg, StackSlot, Chain, Flags, DAG, dl);
4353 // From now on treat this as a regular pointer
4354 Arg = StackSlot;
4355 isByVal = false;
4356 } else {
4357 // Store the argument.
4358 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
4359 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
4360 Chain = DAG.getStore(
4361 Chain, dl, Arg, SpillSlot,
4362 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI));
4363 Arg = SpillSlot;
4364 }
4365 break;
4366 }
4367 }
4368
4369 if (VA.needsCustom()) {
4370 assert(VA.getValVT() == MVT::v64i1 &&(static_cast <bool> (VA.getValVT() == MVT::v64i1 &&
"Currently the only custom case is when we split v64i1 to 2 regs"
) ? void (0) : __assert_fail ("VA.getValVT() == MVT::v64i1 && \"Currently the only custom case is when we split v64i1 to 2 regs\""
, "llvm/lib/Target/X86/X86ISelLowering.cpp", 4371, __extension__
__PRETTY_FUNCTION__))
4371 "Currently the only custom case is when we split v64i1 to 2 regs")(static_cast <bool> (VA.getValVT() == MVT::v64i1 &&
"Currently the only custom case is when we split v64i1 to 2 regs"
) ? void (0) : __assert_fail ("VA.getValVT() == MVT::v64i1 && \"Currently the only custom case is when we split v64i1 to 2 regs\""
, "llvm/lib/Target/X86/X86ISelLowering.cpp", 4371, __extension__
__PRETTY_FUNCTION__))
;
4372 // Split v64i1 value into two registers
4373 Passv64i1ArgInRegs(dl, DAG, Arg, RegsToPass, VA, ArgLocs[++I], Subtarget);
4374 } else if (VA.isRegLoc()) {
4375 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
4376 const TargetOptions &Options = DAG.getTarget().Options;
4377 if (Options.EmitCallSiteInfo)
4378 CSInfo.emplace_back(VA.getLocReg(), I);
4379 if (isVarArg && IsWin64) {
4380 // Win64 ABI requires argument XMM reg to be copied to the corresponding
4381 // shadow reg if callee is a varargs function.
4382 Register ShadowReg;
4383 switch (VA.getLocReg()) {
4384 case X86::XMM0: ShadowReg = X86::RCX; break;
4385 case X86::XMM1: ShadowReg = X86::RDX; break;
4386 case X86::XMM2: ShadowReg = X86::R8; break;
4387 case X86::XMM3: ShadowReg = X86::R9; break;
4388 }
4389 if (ShadowReg)
4390 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
4391 }
4392 } else if (!IsSibcall && (!isTailCall || isByVal)) {
4393 assert(VA.isMemLoc())(static_cast <bool> (VA.isMemLoc()) ? void (0) : __assert_fail
("VA.isMemLoc()", "llvm/lib/Target/X86/X86ISelLowering.cpp",
4393, __extension__ __PRETTY_FUNCTION__))
;
4394 if (!StackPtr.getNode())
4395 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
4396 getPointerTy(DAG.getDataLayout()));
4397 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
4398 dl, DAG, VA, Flags, isByVal));
4399 }
4400 }
4401
4402 if (!MemOpChains.empty())
4403 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
4404
4405 if (Subtarget.isPICStyleGOT()) {
4406 // ELF / PIC requires GOT in the EBX register before function calls via PLT
4407 // GOT pointer (except regcall).
4408 if (!isTailCall) {
4409 // Indirect call with RegCall calling convertion may use up all the
4410 // general registers, so it is not suitable to bind EBX reister for
4411 // GOT address, just let register allocator handle it.
4412 if (CallConv != CallingConv::X86_RegCall)
4413 RegsToPass.push_back(std::make_pair(
4414 Register(X86::EBX), DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(),
4415 getPointerTy(DAG.getDataLayout()))));
4416 } else {
4417 // If we are tail calling and generating PIC/GOT style code load the
4418 // address of the callee into ECX. The value in ecx is used as target of
4419 // the tail jump. This is done to circumvent the ebx/callee-saved problem
4420 // for tail calls on PIC/GOT architectures. Normally we would just put the
4421 // address of GOT into ebx and then call target@PLT. But for tail calls
4422 // ebx would be restored (since ebx is callee saved) before jumping to the
4423 // target@PLT.
4424
4425 // Note: The actual moving to ECX is done further down.
4426 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
4427 if (G && !G->getGlobal()->hasLocalLinkage() &&
4428 G->getGlobal()->hasDefaultVisibility())
4429 Callee = LowerGlobalAddress(Callee, DAG);
4430 else if (isa<ExternalSymbolSDNode>(Callee))
4431 Callee = LowerExternalSymbol(Callee, DAG);
4432 }
4433 }
4434
4435 if (Is64Bit && isVarArg && !IsWin64 && !IsMustTail &&
4436 (Subtarget.hasSSE1() || !M->getModuleFlag("SkipRaxSetup"))) {
4437 // From AMD64 ABI document:
4438 // For calls that may call functions that use varargs or stdargs
4439 // (prototype-less calls or calls to functions containing ellipsis (...) in
4440 // the declaration) %al is used as hidden argument to specify the number
4441 // of SSE registers used. The contents of %al do not need to match exactly
4442 // the number of registers, but must be an ubound on the number of SSE
4443 // registers used and is in the range 0 - 8 inclusive.
4444
4445 // Count the number of XMM registers allocated.
4446 static const MCPhysReg XMMArgRegs[] = {
4447 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
4448 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
4449 };
4450 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs);
4451 assert((Subtarget.hasSSE1() || !NumXMMRegs)(static_cast <bool> ((Subtarget.hasSSE1() || !NumXMMRegs
) && "SSE registers cannot be used when SSE is disabled"
) ? void (0) : __assert_fail ("(Subtarget.hasSSE1() || !NumXMMRegs) && \"SSE registers cannot be used when SSE is disabled\""
, "llvm/lib/Target/X86/X86ISelLowering.cpp", 4452, __extension__
__PRETTY_FUNCTION__))
4452 && "SSE registers cannot be used when SSE is disabled")(static_cast <bool> ((Subtarget.hasSSE1() || !NumXMMRegs
) && "SSE registers cannot be used when SSE is disabled"
) ? void (0) : __assert_fail ("(Subtarget.hasSSE1() || !NumXMMRegs) && \"SSE registers cannot be used when SSE is disabled\""
, "llvm/lib/Target/X86/X86ISelLowering.cpp", 4452, __extension__
__PRETTY_FUNCTION__))
;
4453 RegsToPass.push_back(std::make_pair(Register(X86::AL),
4454 DAG.getConstant(NumXMMRegs, dl,
4455 MVT::i8)));
4456 }
4457
4458 if (isVarArg && IsMustTail) {
4459 const auto &Forwards = X86Info->getForwardedMustTailRegParms();
4460 for (const auto &F : Forwards) {
4461 SDValue Val = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
4462 RegsToPass.push_back(std::make_pair(F.PReg, Val));
4463 }
4464 }
4465
4466 // For tail calls lower the arguments to the 'real' stack slots. Sibcalls
4467 // don't need this because the eligibility check rejects calls that require
4468 // shuffling arguments passed in memory.
4469 if (!IsSibcall && isTailCall) {
4470 // Force all the incoming stack arguments to be loaded from the stack
4471 // before any new outgoing arguments are stored to the stack, because the
4472 // outgoing stack slots may alias the incoming argument stack slots, and
4473 // the alias isn't otherwise explicit. This is slightly more conservative
4474 // than necessary, because it means that each store effectively depends
4475 // on every argument instead of just those arguments it would clobber.
4476 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
4477
4478 SmallVector<SDValue, 8> MemOpChains2;
4479 SDValue FIN;
4480 int FI = 0;
4481 for (unsigned I = 0, OutsIndex = 0, E = ArgLocs.size(); I != E;
4482 ++I, ++OutsIndex) {
4483 CCValAssign &VA = ArgLocs[I];
4484
4485 if (VA.isRegLoc()) {
4486 if (VA.needsCustom()) {
4487 assert((CallConv == CallingConv::X86_RegCall) &&(static_cast <bool> ((CallConv == CallingConv::X86_RegCall
) && "Expecting custom case only in regcall calling convention"
) ? void (0) : __assert_fail ("(CallConv == CallingConv::X86_RegCall) && \"Expecting custom case only in regcall calling convention\""
, "llvm/lib/Target/X86/X86ISelLowering.cpp", 4488, __extension__
__PRETTY_FUNCTION__))
4488 "Expecting custom case only in regcall calling convention")(static_cast <bool> ((CallConv == CallingConv::X86_RegCall
) && "Expecting custom case only in regcall calling convention"
) ? void (0) : __assert_fail ("(CallConv == CallingConv::X86_RegCall) && \"Expecting custom case only in regcall calling convention\""
, "llvm/lib/Target/X86/X86ISelLowering.cpp", 4488, __extension__
__PRETTY_FUNCTION__))
;
4489 // This means that we are in special case where one argument was
4490 // passed through two register locations - Skip the next location
4491 ++I;
4492 }
4493
4494 continue;
4495 }
4496
4497 assert(VA.isMemLoc())(static_cast <bool> (VA.isMemLoc()) ? void (0) : __assert_fail
("VA.isMemLoc()", "llvm/lib/Target/X86/X86ISelLowering.cpp",
4497, __extension__ __PRETTY_FUNCTION__))
;
4498 SDValue Arg = OutVals[OutsIndex];
4499 ISD::ArgFlagsTy Flags = Outs[OutsIndex].Flags;
4500 // Skip inalloca/preallocated arguments. They don't require any work.
4501 if (Flags.isInAlloca() || Flags.isPreallocated())
4502 continue;
4503 // Create frame index.
4504 int32_t Offset = VA.getLocMemOffset()+FPDiff;
4505 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
4506 FI = MF.getFrameInfo().CreateFixedObject(OpSize, Offset, true);
4507 FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
4508
4509 if (Flags.isByVal()) {
4510 // Copy relative to framepointer.
4511 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset(), dl);
4512 if (!StackPtr.getNode())
4513 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
4514 getPointerTy(DAG.getDataLayout()));
4515 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(DAG.getDataLayout()),
4516 StackPtr, Source);
4517
4518 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
4519 ArgChain,
4520 Flags, DAG, dl));
4521 } else {
4522 // Store relative to framepointer.
4523 MemOpChains2.push_back(DAG.getStore(
4524 ArgChain, dl, Arg, FIN,
4525 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI)));
4526 }
4527 }
4528
4529 if (!MemOpChains2.empty())
4530 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
4531
4532 // Store the return address to the appropriate stack slot.
4533 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx,
4534 getPointerTy(DAG.getDataLayout()),
4535 RegInfo->getSlotSize(), FPDiff, dl);
4536 }
4537
4538 // Build a sequence of copy-to-reg nodes chained together with token chain
4539 // and flag operands which copy the outgoing args into registers.
4540 SDValue InFlag;
4541 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
4542 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
4543 RegsToPass[i].second, InFlag);
4544 InFlag = Chain.getValue(1);
4545 }
4546
4547 if (DAG.getTarget().getCodeModel() == CodeModel::Large) {
4548 assert(Is64Bit && "Large code model is only legal in 64-bit mode.")(static_cast <bool> (Is64Bit && "Large code model is only legal in 64-bit mode."
) ? void (0) : __assert_fail ("Is64Bit && \"Large code model is only legal in 64-bit mode.\""
, "llvm/lib/Target/X86/X86ISelLowering.cpp", 4548, __extension__
__PRETTY_FUNCTION__))
;
4549 // In the 64-bit large code model, we have to make all calls
4550 // through a register, since the call instruction's 32-bit
4551 // pc-relative offset may not be large enough to hold the whole
4552 // address.
4553 } else if (Callee->getOpcode() == ISD::GlobalAddress ||
4554 Callee->getOpcode() == ISD::ExternalSymbol) {
4555 // Lower direct calls to global addresses and external symbols. Setting
4556 // ForCall to true here has the effect of removing WrapperRIP when possible
4557 // to allow direct calls to be selected without first materializing the
4558 // address into a register.
4559 Callee = LowerGlobalOrExternal(Callee, DAG, /*ForCall=*/true);
4560 } else if (Subtarget.isTarget64BitILP32() &&
4561 Callee.getValueType() == MVT::i32) {
4562 // Zero-extend the 32-bit Callee address into a 64-bit according to x32 ABI
4563 Callee = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Callee);
4564 }
4565
4566 // Returns a chain & a flag for retval copy to use.
4567 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
4568 SmallVector<SDValue, 8> Ops;
4569
4570 if (!IsSibcall && isTailCall && !IsMustTail) {
4571 Chain = DAG.getCALLSEQ_END(Chain,
4572 DAG.getIntPtrConstant(NumBytesToPop, dl, true),
4573 DAG.getIntPtrConstant(0, dl, true), InFlag, dl);
4574 InFlag = Chain.getValue(1);
4575 }
4576
4577 Ops.push_back(Chain);
4578 Ops.push_back(Callee);
4579
4580 if (isTailCall)
4581 Ops.push_back(DAG.getTargetConstant(FPDiff, dl, MVT::i32));
4582
4583 // Add argument registers to the end of the list so that they are known live
4584 // into the call.
4585 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
4586 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
4587 RegsToPass[i].second.getValueType()));
4588
4589 // Add a register mask operand representing the call-preserved registers.
4590 const uint32_t *Mask = [&]() {
4591 auto AdaptedCC = CallConv;
4592 // If HasNCSR is asserted (attribute NoCallerSavedRegisters exists),
4593 // use X86_INTR calling convention because it has the same CSR mask
4594 // (same preserved registers).
4595 if (HasNCSR)
4596 AdaptedCC = (CallingConv::ID)CallingConv::X86_INTR;
4597 // If NoCalleeSavedRegisters is requested, than use GHC since it happens
4598 // to use the CSR_NoRegs_RegMask.
4599 if (CB && CB->hasFnAttr("no_callee_saved_registers"))
4600 AdaptedCC = (CallingConv::ID)CallingConv::GHC;
4601 return RegInfo->getCallPreservedMask(MF, AdaptedCC);
4602 }();
4603 assert(Mask && "Missing call preserved mask for calling convention")(static_cast <bool> (Mask && "Missing call preserved mask for calling convention"
) ? void (0) : __assert_fail ("Mask && \"Missing call preserved mask for calling convention\""
, "llvm/lib/Target/X86/X86ISelLowering.cpp", 4603, __extension__
__PRETTY_FUNCTION__))
;
4604
4605 // If this is an invoke in a 32-bit function using a funclet-based
4606 // personality, assume the function clobbers all registers. If an exception
4607 // is thrown, the runtime will not restore CSRs.
4608 // FIXME: Model this more precisely so that we can register allocate across
4609 // the normal edge and spill and fill across the exceptional edge.
4610 if (!Is64Bit && CLI.CB && isa<InvokeInst>(CLI.CB)) {
4611 const Function &CallerFn = MF.getFunction();
4612 EHPersonality Pers =
4613 CallerFn.hasPersonalityFn()
4614 ? classifyEHPersonality(CallerFn.getPersonalityFn())
4615 : EHPersonality::Unknown;
4616 if (isFuncletEHPersonality(Pers))
4617 Mask = RegInfo->getNoPreservedMask();
4618 }
4619
4620 // Define a new register mask from the existing mask.
4621 uint32_t *RegMask = nullptr;
4622
4623 // In some calling conventions we need to remove the used physical registers
4624 // from the reg mask.
4625 if (CallConv == CallingConv::X86_RegCall || HasNCSR) {
4626 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
4627
4628 // Allocate a new Reg Mask and copy Mask.
4629 RegMask = MF.allocateRegMask();
4630 unsigned RegMaskSize = MachineOperand::getRegMaskSize(TRI->getNumRegs());
4631 memcpy(RegMask, Mask, sizeof(RegMask[0]) * RegMaskSize);
4632
4633 // Make sure all sub registers of the argument registers are reset
4634 // in the RegMask.
4635 for (auto const &RegPair : RegsToPass)
4636 for (MCSubRegIterator SubRegs(RegPair.first, TRI, /*IncludeSelf=*/true);
4637 SubRegs.isValid(); ++SubRegs)
4638 RegMask[*SubRegs / 32] &= ~(1u << (*SubRegs % 32));
4639
4640 // Create the RegMask Operand according to our updated mask.
4641 Ops.push_back(DAG.getRegisterMask(RegMask));
4642 } else {
4643 // Create the RegMask Operand according to the static mask.
4644 Ops.push_back(DAG.getRegisterMask(Mask));
4645 }
4646
4647 if (InFlag.getNode())
4648 Ops.push_back(InFlag);
4649
4650 if (isTailCall) {
4651 // We used to do:
4652 //// If this is the first return lowered for this function, add the regs
4653 //// to the liveout set for the function.
4654 // This isn't right, although it's probably harmless on x86; liveouts
4655 // should be computed from returns not tail calls. Consider a void
4656 // function making a tail call to a function returning int.
4657 MF.getFrameInfo().setHasTailCall();
4658 SDValue Ret = DAG.getNode(X86ISD::TC_RETURN, dl, NodeTys, Ops);
4659 DAG.addCallSiteInfo(Ret.getNode(), std::move(CSInfo));
4660 return Ret;
4661 }
4662
4663 if (HasNoCfCheck && IsCFProtectionSupported && IsIndirectCall) {
4664 Chain = DAG.getNode(X86ISD::NT_CALL, dl, NodeTys, Ops);
4665 } else if (CLI.CB && objcarc::hasAttachedCallOpBundle(CLI.CB)) {
4666 // Calls with a "clang.arc.attachedcall" bundle are special. They should be
4667 // expanded to the call, directly followed by a special marker sequence and
4668 // a call to a ObjC library function. Use the CALL_RVMARKER to do that.
4669 assert(!isTailCall &&(static_cast <bool> (!isTailCall && "tail calls cannot be marked with clang.arc.attachedcall"
) ? void (0) : __assert_fail ("!isTailCall && \"tail calls cannot be marked with clang.arc.attachedcall\""
, "llvm/lib/Target/X86/X86ISelLowering.cpp", 4670, __extension__
__PRETTY_FUNCTION__))
4670 "tail calls cannot be marked with clang.arc.attachedcall")(static_cast <bool> (!isTailCall && "tail calls cannot be marked with clang.arc.attachedcall"
) ? void (0) : __assert_fail ("!isTailCall && \"tail calls cannot be marked with clang.arc.attachedcall\""
, "llvm/lib/Target/X86/X86ISelLowering.cpp", 4670, __extension__
__PRETTY_FUNCTION__))
;
4671 assert(Is64Bit && "clang.arc.attachedcall is only supported in 64bit mode")(static_cast <bool> (Is64Bit && "clang.arc.attachedcall is only supported in 64bit mode"
) ? void (0) : __assert_fail ("Is64Bit && \"clang.arc.attachedcall is only supported in 64bit mode\""
, "llvm/lib/Target/X86/X86ISelLowering.cpp", 4671, __extension__
__PRETTY_FUNCTION__))
;
4672
4673 // Add a target global address for the retainRV/claimRV runtime function
4674 // just before the call target.
4675 Function *ARCFn = *objcarc::getAttachedARCFunction(CLI.CB);
4676 auto PtrVT = getPointerTy(DAG.getDataLayout());
4677 auto GA = DAG.getTargetGlobalAddress(ARCFn, dl, PtrVT);
4678 Ops.insert(Ops.begin() + 1, GA);
4679 Chain = DAG.getNode(X86ISD::CALL_RVMARKER, dl, NodeTys, Ops);
4680 } else {
4681 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, Ops);
4682 }
4683
4684 InFlag = Chain.getValue(1);
4685 DAG.addNoMergeSiteInfo(Chain.getNode(), CLI.NoMerge);
4686 DAG.addCallSiteInfo(Chain.getNode(), std::move(CSInfo));
4687
4688 // Save heapallocsite metadata.
4689 if (CLI.CB)
4690 if (MDNode *HeapAlloc = CLI.CB->getMetadata("heapallocsite"))
4691 DAG.addHeapAllocSite(Chain.getNode(), HeapAlloc);
4692
4693 // Create the CALLSEQ_END node.
4694 unsigned NumBytesForCalleeToPop = 0; // Callee pops nothing.
4695 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
4696 DAG.getTarget().Options.GuaranteedTailCallOpt))
4697 NumBytesForCalleeToPop = NumBytes; // Callee pops everything
4698 else if (!canGuaranteeTCO(CallConv) && IsCalleePopSRet)
4699 // If this call passes a struct-return pointer, the callee
4700 // pops that struct pointer.
4701 NumBytesForCalleeToPop = 4;
4702
4703 // Returns a flag for retval copy to use.
4704 if (!IsSibcall) {
4705 Chain = DAG.getCALLSEQ_END(Chain,
4706 DAG.getIntPtrConstant(NumBytesToPop, dl, true),
4707 DAG.getIntPtrConstant(NumBytesForCalleeToPop, dl,
4708 true),
4709 InFlag, dl);
4710 InFlag = Chain.getValue(1);
4711 }
4712
4713 // Handle result values, copying them out of physregs into vregs that we
4714 // return.
4715 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins, dl, DAG,
4716 InVals, RegMask);
4717}
4718
4719//===----------------------------------------------------------------------===//
4720// Fast Calling Convention (tail call) implementation
4721//===----------------------------------------------------------------------===//
4722
4723// Like std call, callee cleans arguments, convention except that ECX is
4724// reserved for storing the tail called function address. Only 2 registers are
4725// free for argument passing (inreg). Tail call optimization is performed
4726// provided:
4727// * tailcallopt is enabled
4728// * caller/callee are fastcc
4729// On X86_64 architecture with GOT-style position independent code only local
4730// (within module) calls are supported at the moment.
4731// To keep the stack aligned according to platform abi the function
4732// GetAlignedArgumentStackSize ensures that argument delta is always multiples
4733// of stack alignment. (Dynamic linkers need this - Darwin's dyld for example)
4734// If a tail called function callee has more arguments than the caller the
4735// caller needs to make sure that there is room to move the RETADDR to. This is
4736// achieved by reserving an area the size of the argument delta right after the
4737// original RETADDR, but before the saved framepointer or the spilled registers
4738// e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
4739// stack layout:
4740// arg1
4741// arg2
4742// RETADDR
4743// [ new RETADDR
4744// move area ]
4745// (possible EBP)
4746// ESI
4747// EDI
4748// local1 ..
4749
4750/// Make the stack size align e.g 16n + 12 aligned for a 16-byte align
4751/// requirement.
4752unsigned
4753X86TargetLowering::GetAlignedArgumentStackSize(const unsigned StackSize,
4754 SelectionDAG &DAG) const {
4755 const Align StackAlignment = Subtarget.getFrameLowering()->getStackAlign();
4756 const uint64_t SlotSize = Subtarget.getRegisterInfo()->getSlotSize();
4757 assert(StackSize % SlotSize == 0 &&(static_cast <bool> (StackSize % SlotSize == 0 &&
"StackSize must be a multiple of SlotSize") ? void (0) : __assert_fail
("StackSize % SlotSize == 0 && \"StackSize must be a multiple of SlotSize\""
, "llvm/lib/Target/X86/X86ISelLowering.cpp", 4758, __extension__
__PRETTY_FUNCTION__))
4758 "StackSize must be a multiple of SlotSize")(static_cast <bool> (StackSize % SlotSize == 0 &&
"StackSize must be a multiple of SlotSize") ? void (0) : __assert_fail
("StackSize % SlotSize == 0 && \"StackSize must be a multiple of SlotSize\""
, "llvm/lib/Target/X86/X86ISelLowering.cpp", 4758, __extension__
__PRETTY_FUNCTION__))
;
4759 return alignTo(StackSize + SlotSize, StackAlignment) - SlotSize;
4760}
4761
4762/// Return true if the given stack call argument is already available in the
4763/// same position (relatively) of the caller's incoming argument stack.
4764static
4765bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
4766 MachineFrameInfo &MFI, const MachineRegisterInfo *MRI,
4767 const X86InstrInfo *TII, const CCValAssign &VA) {
4768 unsigned Bytes = Arg.getValueSizeInBits() / 8;
4769
4770 for (;;) {
4771 // Look through nodes that don't alter the bits of the incoming value.
4772 unsigned Op = Arg.getOpcode();
4773 if (Op == ISD::ZERO_EXTEND || Op == ISD::ANY_EXTEND || Op == ISD::BITCAST) {
4774 Arg = Arg.getOperand(0);
4775 continue;
4776 }
4777 if (Op == ISD::TRUNCATE) {
4778 const SDValue &TruncInput = Arg.getOperand(0);
4779 if (TruncInput.getOpcode() == ISD::AssertZext &&
4780 cast<VTSDNode>(TruncInput.getOperand(1))->getVT() ==
4781 Arg.getValueType()) {
4782 Arg = TruncInput.getOperand(0);
4783 continue;
4784 }
4785 }
4786 break;
4787 }
4788
4789 int FI = INT_MAX2147483647;
4790 if (Arg.getOpcode() == ISD::CopyFromReg) {
4791 Register VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
4792 if (!VR.isVirtual())
4793 return false;
4794 MachineInstr *Def = MRI->getVRegDef(VR);
4795 if (!Def)
4796 return false;
4797 if (!Flags.isByVal()) {
4798 if (!TII->isLoadFromStackSlot(*Def, FI))
4799 return false;
4800 } else {
4801 unsigned Opcode = Def->getOpcode();
4802 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r ||
4803 Opcode == X86::LEA64_32r) &&
4804 Def->getOperand(1).isFI()) {
4805 FI = Def->getOperand(1).getIndex();
4806 Bytes = Flags.getByValSize();
4807 } else
4808 return false;
4809 }
4810 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
4811 if (Flags.isByVal())
4812 // ByVal argument is passed in as a pointer but it's now being
4813 // dereferenced. e.g.
4814 // define @foo(%struct.X* %A) {
4815 // tail call @bar(%struct.X* byval %A)
4816 // }
4817 return false;
4818 SDValue Ptr = Ld->getBasePtr();
4819 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
4820 if (!FINode)
4821 return false;
4822 FI = FINode->getIndex();
4823 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
4824 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
4825 FI = FINode->getIndex();
4826 Bytes = Flags.getByValSize();
4827 } else
4828 return false;
4829
4830 assert(FI != INT_MAX)(static_cast <bool> (FI != 2147483647) ? void (0) : __assert_fail
("FI != INT_MAX", "llvm/lib/Target/X86/X86ISelLowering.cpp",
4830, __extension__ __PRETTY_FUNCTION__))
;
4831 if (!MFI.isFixedObjectIndex(FI))
4832 return false;
4833
4834 if (Offset != MFI.getObjectOffset(FI))
4835 return false;
4836
4837 // If this is not byval, check that the argument stack object is immutable.
4838 // inalloca and argument copy elision can create mutable argument stack
4839 // objects. Byval objects can be mutated, but a byval call intends to pass the
4840 // mutated memory.
4841 if (!Flags.isByVal() && !MFI.isImmutableObjectIndex(FI))
4842 return false;
4843
4844 if (VA.getLocVT().getFixedSizeInBits() >
4845 Arg.getValueSizeInBits().getFixedSize()) {
4846 // If the argument location is wider than the argument type, check that any
4847 // extension flags match.
4848 if (Flags.isZExt() != MFI.isObjectZExt(FI) ||
4849 Flags.isSExt() != MFI.isObjectSExt(FI)) {
4850 return false;
4851 }
4852 }
4853
4854 return Bytes == MFI.getObjectSize(FI);
4855}
4856
4857/// Check whether the call is eligible for tail call optimization. Targets
4858/// that want to do tail call optimization should implement this function.
4859bool X86TargetLowering::IsEligibleForTailCallOptimization(
4860 SDValue Callee, CallingConv::ID CalleeCC, bool IsCalleePopSRet,
4861 bool isVarArg, Type *RetTy, const SmallVectorImpl<ISD::OutputArg> &Outs,
4862 const SmallVectorImpl<SDValue> &OutVals,
4863 const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG) const {
4864 if (!mayTailCallThisCC(CalleeCC))
4865 return false;
4866
4867 // If -tailcallopt is specified, make fastcc functions tail-callable.
4868 MachineFunction &MF = DAG.getMachineFunction();
4869 const Function &CallerF = MF.getFunction();
4870
4871 // If the function return type is x86_fp80 and the callee return type is not,
4872 // then the FP_EXTEND of the call result is not a nop. It's not safe to
4873 // perform a tailcall optimization here.
4874 if (CallerF.getReturnType()->isX86_FP80Ty() && !RetTy->isX86_FP80Ty())
4875 return false;
4876
4877 CallingConv::ID CallerCC = CallerF.getCallingConv();
4878 bool CCMatch = CallerCC == CalleeCC;
4879 bool IsCalleeWin64 = Subtarget.isCallingConvWin64(CalleeCC);
4880 bool IsCallerWin64 = Subtarget.isCallingConvWin64(CallerCC);
4881 bool IsGuaranteeTCO = DAG.getTarget().Options.GuaranteedTailCallOpt ||
4882 CalleeCC == CallingConv::Tail || CalleeCC == CallingConv::SwiftTail;
4883
4884 // Win64 functions have extra shadow space for argument homing. Don't do the
4885 // sibcall if the caller and callee have mismatched expectations for this
4886 // space.
4887 if (IsCalleeWin64 != IsCallerWin64)
4888 return false;
4889
4890 if (IsGuaranteeTCO) {
4891 if (canGuaranteeTCO(CalleeCC) && CCMatch)
4892 return true;
4893 return false;
4894 }
4895
4896 // Look for obvious safe cases to perform tail call optimization that do not
4897 // require ABI changes. This is what gcc calls sibcall.
4898
4899 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
4900 // emit a special epilogue.
4901 const X86RegisterInfo *RegInfo = Subtarget.getRegisterInfo();
4902 if (RegInfo->hasStackRealignment(MF))
4903 return false;
4904
4905 // Also avoid sibcall optimization if we're an sret return fn and the callee
4906 // is incompatible. See comment in LowerReturn about why hasStructRetAttr is
4907 // insufficient.
4908 if (MF.getInfo<X86MachineFunctionInfo>()->getSRetReturnReg()) {
4909 // For a compatible tail call the callee must return our sret pointer. So it
4910 // needs to be (a) an sret function itself and (b) we pass our sret as its
4911 // sret. Condition #b is harder to determine.
4912 return false;
4913 } else if (IsCalleePopSRet)
4914 // The callee pops an sret, so we cannot tail-call, as our caller doesn't
4915 // expect that.
4916 return false;
4917
4918 // Do not sibcall optimize vararg calls unless all arguments are passed via
4919 // registers.
4920 LLVMContext &C = *DAG.getContext();
4921 if (isVarArg && !Outs.empty()) {
4922 // Optimizing for varargs on Win64 is unlikely to be safe without
4923 // additional testing.
4924 if (IsCalleeWin64 || IsCallerWin64)
4925 return false;
4926
4927 SmallVector<CCValAssign, 16> ArgLocs;
4928 CCState CCInfo(CalleeCC, isVarArg, MF, ArgLocs, C);
4929
4930 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
4931 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
4932 if (!ArgLocs[i].isRegLoc())
4933 return false;
4934 }
4935
4936 // If the call result is in ST0 / ST1, it needs to be popped off the x87
4937 // stack. Therefore, if it's not used by the call it is not safe to optimize
4938 // this into a sibcall.
4939 bool Unused = false;
4940 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
4941 if (!Ins[i].Used) {
4942 Unused = true;
4943 break;
4944 }
4945 }
4946 if (Unused) {
4947 SmallVector<CCValAssign, 16> RVLocs;
4948 CCState CCInfo(CalleeCC, false, MF, RVLocs, C);
4949 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
4950 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
4951 CCValAssign &VA = RVLocs[i];
4952 if (VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1)
4953 return false;
4954 }
4955 }
4956
4957 // Check that the call results are passed in the same way.
4958 if (!CCState::resultsCompatible(CalleeCC, CallerCC, MF, C, Ins,
4959 RetCC_X86, RetCC_X86))
4960 return false;
4961 // The callee has to preserve all registers the caller needs to preserve.
4962 const X86RegisterInfo *TRI = Subtarget.getRegisterInfo();
4963 const uint32_t *CallerPreserved = TRI->getCallPreservedMask(MF, CallerCC);
4964 if (!CCMatch) {
4965 const uint32_t *CalleePreserved = TRI->getCallPreservedMask(MF, CalleeCC);
4966 if (!TRI->regmaskSubsetEqual(CallerPreserved, CalleePreserved))
4967 return false;
4968 }
4969
4970 unsigned StackArgsSize = 0;
4971
4972 // If the callee takes no arguments then go on to check the results of the
4973 // call.
4974 if (!Outs.empty()) {
4975 // Check if stack adjustment is needed. For now, do not do this if any
4976 // argument is passed on the stack.
4977 SmallVector<CCValAssign, 16> ArgLocs;
4978 CCState CCInfo(CalleeCC, isVarArg, MF, ArgLocs, C);
4979
4980 // Allocate shadow area for Win64
4981 if (IsCalleeWin64)
4982 CCInfo.AllocateStack(32, Align(8));
4983
4984 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
4985 StackArgsSize = CCInfo.getNextStackOffset();
4986
4987 if (CCInfo.getNextStackOffset()) {
4988 // Check if the arguments are already laid out in the right way as
4989 // the caller's fixed stack objects.
4990 MachineFrameInfo &MFI = MF.getFrameInfo();
4991 const MachineRegisterInfo *MRI = &MF.getRegInfo();
4992 const X86InstrInfo *TII = Subtarget.getInstrInfo();
4993 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
4994 CCValAssign &VA = ArgLocs[i];
4995 SDValue Arg = OutVals[i];
4996 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4997 if (VA.getLocInfo() == CCValAssign::Indirect)
4998 return false;
4999 if (!VA.isRegLoc()) {
5000 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
5001 MFI, MRI, TII, VA))
5002 return false;
5003 }
5004 }
5005 }
5006
5007 bool PositionIndependent = isPositionIndependent();
5008 // If the tailcall address may be in a register, then make sure it's
5009 // possible to register allocate for it. In 32-bit, the call address can
5010 // only target EAX, EDX, or ECX since the tail call must be scheduled after
5011 // callee-saved registers are restored. These happen to be the same
5012 // registers used to pass 'inreg' arguments so watch out for those.
5013 if (!Subtarget.is64Bit() && ((!isa<GlobalAddressSDNode>(Callee) &&
5014 !isa<ExternalSymbolSDNode>(Callee)) ||
5015 PositionIndependent)) {
5016 unsigned NumInRegs = 0;
5017 // In PIC we need an extra register to formulate the address computation
5018 // for the callee.
5019 unsigned MaxInRegs = PositionIndependent ? 2 : 3;
5020
5021 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
5022 CCValAssign &VA = ArgLocs[i];
5023 if (!VA.isRegLoc())
5024 continue;
5025 Register Reg = VA.getLocReg();
5026 switch (Reg) {
5027 default: break;
5028 case X86::EAX: case X86::EDX: case X86::ECX:
5029 if (++NumInRegs == MaxInRegs)
5030 return false;
5031 break;
5032 }
5033 }
5034 }
5035
5036 const MachineRegisterInfo &MRI = MF.getRegInfo();
5037 if (!parametersInCSRMatch(MRI, CallerPreserved, ArgLocs, OutVals))
5038 return false;
5039 }
5040
5041 bool CalleeWillPop =
5042 X86::isCalleePop(CalleeCC, Subtarget.is64Bit(), isVarArg,
5043 MF.getTarget().Options.GuaranteedTailCallOpt);
5044
5045 if (unsigned BytesToPop =
5046 MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn()) {
5047 // If we have bytes to pop, the callee must pop them.
5048 bool CalleePopMatches = CalleeWillPop && BytesToPop == StackArgsSize;
5049 if (!CalleePopMatches)
5050 return false;
5051 } else if (CalleeWillPop && StackArgsSize > 0) {
5052 // If we don't have bytes to pop, make sure the callee doesn't pop any.
5053 return false;
5054 }
5055
5056 return true;
5057}
5058
5059FastISel *
5060X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
5061 const TargetLibraryInfo *libInfo) const {
5062 return X86::createFastISel(funcInfo, libInfo);
5063}
5064
5065//===----------------------------------------------------------------------===//
5066// Other Lowering Hooks
5067//===----------------------------------------------------------------------===//
5068
5069bool X86::mayFoldLoad(SDValue Op, const X86Subtarget &Subtarget,
5070 bool AssumeSingleUse) {
5071 if (!AssumeSingleUse && !Op.hasOneUse())
5072 return false;
5073 if (!ISD::isNormalLoad(Op.getNode()))
5074 return false;
5075
5076 // If this is an unaligned vector, make sure the target supports folding it.
5077 auto *Ld = cast<LoadSDNode>(Op.getNode());
5078 if (!Subtarget.hasAVX() && !Subtarget.hasSSEUnalignedMem() &&
5079 Ld->getValueSizeInBits(0) == 128 && Ld->getAlignment() < 16)
5080 return false;
5081
5082 // TODO: If this is a non-temporal load and the target has an instruction
5083 // for it, it should not be folded. See "useNonTemporalLoad()".
5084
5085 return true;
5086}
5087
5088bool X86::mayFoldLoadIntoBroadcastFromMem(SDValue Op, MVT EltVT,
5089 const X86Subtarget &Subtarget,
5090 bool AssumeSingleUse) {
5091 assert(Subtarget.hasAVX() && "Expected AVX for broadcast from memory")(static_cast <bool> (Subtarget.hasAVX() && "Expected AVX for broadcast from memory"
) ? void (0) : __assert_fail ("Subtarget.hasAVX() && \"Expected AVX for broadcast from memory\""
, "llvm/lib/Target/X86/X86ISelLowering.cpp", 5091, __extension__
__PRETTY_FUNCTION__))
;
5092 if (!X86::mayFoldLoad(Op, Subtarget, AssumeSingleUse))
5093 return false;
5094
5095 // We can not replace a wide volatile load with a broadcast-from-memory,
5096 // because that would narrow the load, which isn't legal for volatiles.
5097 auto *Ld = cast<LoadSDNode>(Op.getNode());
5098 return !Ld->isVolatile() ||
5099 Ld->getValueSizeInBits(0) == EltVT.getScalarSizeInBits();
5100}
5101
5102bool X86::mayFoldIntoStore(SDValue Op) {
5103 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
5104}
5105
5106bool X86::mayFoldIntoZeroExtend(SDValue Op) {
5107 if (Op.hasOneUse()) {
5108 unsigned Opcode = Op.getNode()->use_begin()->getOpcode();
5109 return (ISD::ZERO_EXTEND == Opcode);
5110 }
5111 return false;
5112}
5113
5114static bool isTargetShuffle(unsigned Opcode) {
5115 switch(Opcode) {
5116 default: return false;
5117 case X86ISD::BLENDI:
5118 case X86ISD::PSHUFB:
5119 case X86ISD::PSHUFD:
5120 case X86ISD::PSHUFHW:
5121 case X86ISD::PSHUFLW:
5122 case X86ISD::SHUFP:
5123 case X86ISD::INSERTPS:
5124 case X86ISD::EXTRQI:
5125 case X86ISD::INSERTQI:
5126 case X86ISD::VALIGN:
5127 case X86ISD::PALIGNR:
5128 case X86ISD::VSHLDQ:
5129 case X86ISD::VSRLDQ:
5130 case X86ISD::MOVLHPS:
5131 case X86ISD::MOVHLPS:
5132 case X86ISD::MOVSHDUP:
5133 case X86ISD::MOVSLDUP:
5134 case X86ISD::MOVDDUP:
5135 case X86ISD::MOVSS:
5136 case X86ISD::MOVSD:
5137 case X86ISD::MOVSH:
5138 case X86ISD::UNPCKL:
5139 case X86ISD::UNPCKH:
5140 case X86ISD::VBROADCAST:
5141 case X86ISD::VPERMILPI:
5142 case X86ISD::VPERMILPV:
5143 case X86ISD::VPERM2X128:
5144 case X86ISD::SHUF128:
5145 case X86ISD::VPERMIL2:
5146 case X86ISD::VPERMI:
5147 case X86ISD::VPPERM:
5148 case X86ISD::VPERMV:
5149 case X86ISD::VPERMV3:
5150 case X86ISD::VZEXT_MOVL:
5151 return true;
5152 }
5153}
5154
5155static bool isTargetShuffleVariableMask(unsigned Opcode) {
5156 switch (Opcode) {
5157 default: return false;
5158 // Target Shuffles.
5159 case X86ISD::PSHUFB:
5160 case X86ISD::VPERMILPV:
5161 case X86ISD::VPERMIL2:
5162 case X86ISD::VPPERM:
5163 case X86ISD::VPERMV:
5164 case X86ISD::VPERMV3:
5165 return true;
5166 // 'Faux' Target Shuffles.
5167 case ISD::OR:
5168 case ISD::AND:
5169 case X86ISD::ANDNP:
5170 return true;
5171 }
5172}
5173
5174static bool isTargetShuffleSplat(SDValue Op) {
5175 unsigned Opcode = Op.getOpcode();
5176 if (Opcode == ISD::EXTRACT_SUBVECTOR)
5177 return isTargetShuffleSplat(Op.getOperand(0));
5178 return Opcode == X86ISD::VBROADCAST || Opcode == X86ISD::VBROADCAST_LOAD;
5179}
5180
5181SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
5182 MachineFunction &MF = DAG.getMachineFunction();
5183 const X86RegisterInfo *RegInfo = Subtarget.getRegisterInfo();
5184 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
5185 int ReturnAddrIndex = FuncInfo->getRAIndex();
5186
5187 if (ReturnAddrIndex == 0) {
5188 // Set up a frame object for the return address.
5189 unsigned SlotSize = RegInfo->getSlotSize();
5190 ReturnAddrIndex = MF.getFrameInfo().CreateFixedObject(SlotSize,
5191 -(int64_t)SlotSize,
5192 false);
5193 FuncInfo->setRAIndex(ReturnAddrIndex);
5194 }
5195
5196 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy(DAG.getDataLayout()));
5197}
5198
5199bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
5200 bool hasSymbolicDisplacement) {
5201 // Offset should fit into 32 bit immediate field.
5202 if (!isInt<32>(Offset))
5203 return false;
5204
5205 // If we don't have a symbolic displacement - we don't have any extra
5206 // restrictions.
5207 if (!hasSymbolicDisplacement)
5208 return true;
5209
5210 // FIXME: Some tweaks might be needed for medium code model.
5211 if (M != CodeModel::Small && M != CodeModel::Kernel)
5212 return false;
5213
5214 // For small code model we assume that latest object is 16MB before end of 31
5215 // bits boundary. We may also accept pretty large negative constants knowing
5216 // that all objects are in the positive half of address space.
5217 if (M == CodeModel::Small && Offset < 16*1024*1024)
5218 return true;
5219
5220 // For kernel code model we know that all object resist in the negative half
5221 // of 32bits address space. We may not accept negative offsets, since they may
5222 // be just off and we may accept pretty large positive ones.
5223 if (M == CodeModel::Kernel && Offset >= 0)
5224 return true;
5225
5226 return false;
5227}
5228
5229/// Determines whether the callee is required to pop its own arguments.
5230/// Callee pop is necessary to support tail calls.
5231bool X86::isCalleePop(CallingConv::ID CallingConv,
5232 bool is64Bit, bool IsVarArg, bool GuaranteeTCO) {
5233 // If GuaranteeTCO is true, we force some calls to be callee pop so that we
5234 // can guarantee TCO.
5235 if (!IsVarArg && shouldGuaranteeTCO(CallingConv, GuaranteeTCO))
5236 return true;
5237
5238 switch (CallingConv) {
5239 default:
5240 return false;
5241 case CallingConv::X86_StdCall:
5242 case CallingConv::X86_FastCall:
5243 case CallingConv::X86_ThisCall:
5244 case CallingConv::X86_VectorCall:
5245 return !is64Bit;
5246 }
5247}
5248
5249/// Return true if the condition is an signed comparison operation.
5250static bool isX86CCSigned(unsigned X86CC) {
5251 switch (X86CC) {
5252 default:
5253 llvm_unreachable("Invalid integer condition!")::llvm::llvm_unreachable_internal("Invalid integer condition!"
, "llvm/lib/Target/X86/X86ISelLowering.cpp", 5253)
;
5254 case X86::COND_E:
5255 case X86::COND_NE:
5256 case X86::COND_B:
5257 case X86::COND_A:
5258 case X86::COND_BE:
5259 case X86::COND_AE:
5260 return false;
5261 case X86::COND_G:
5262 case X86::COND_GE:
5263 case X86::COND_L:
5264 case X86::COND_LE:
5265 return true;
5266 }
5267}
5268
5269static X86::CondCode TranslateIntegerX86CC(ISD::CondCode SetCCOpcode) {
5270 switch (SetCCOpcode) {
5271 default: llvm_unreachable("Invalid integer condition!")::llvm::llvm_unreachable_internal("Invalid integer condition!"
, "llvm/lib/Target/X86/X86ISelLowering.cpp", 5271)
;
5272 case ISD::SETEQ: return X86::COND_E;
5273 case ISD::SETGT: return X86::COND_G;
5274 case ISD::SETGE: return X86::COND_GE;
5275 case ISD::SETLT: return X86::COND_L;
5276 case ISD::SETLE: return X86::COND_LE;
5277 case ISD::SETNE: return X86::COND_NE;
5278 case ISD::SETULT: return X86::COND_B;
5279 case ISD::SETUGT: return X86::COND_A;
5280 case ISD::SETULE: return X86::COND_BE;
5281 case ISD::SETUGE: return X86::COND_AE;
5282 }
5283}
5284
5285/// Do a one-to-one translation of a ISD::CondCode to the X86-specific
5286/// condition code, returning the condition code and the LHS/RHS of the
5287/// comparison to make.
5288static X86::CondCode TranslateX86CC(ISD::CondCode SetCCOpcode, const SDLoc &DL,
5289 bool isFP, SDValue &LHS, SDValue &RHS,
5290 SelectionDAG &DAG) {
5291 if (!isFP) {
5292 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
5293 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnes()) {
5294 // X > -1 -> X == 0, jump !sign.
5295 RHS = DAG.getConstant(0, DL, RHS.getValueType());
5296 return X86::COND_NS;
5297 }
5298 if (SetCCOpcode == ISD::SETLT && RHSC->isZero()) {
5299 // X < 0 -> X == 0, jump on sign.
5300 return X86::COND_S;
5301 }
5302 if (SetCCOpcode == ISD::SETGE && RHSC->isZero()) {
5303 // X >= 0 -> X == 0, jump on !sign.
5304 return X86::COND_NS;
5305 }
5306 if (SetCCOpcode == ISD::SETLT && RHSC->isOne()) {
5307 // X < 1 -> X <= 0
5308 RHS = DAG.getConstant(0, DL, RHS.getValueType());
5309 return X86::COND_LE;
5310 }
5311 }
5312
5313 return TranslateIntegerX86CC(SetCCOpcode);
5314 }
5315
5316 // First determine if it is required or is profitable to flip the operands.
5317
5318 // If LHS is a foldable load, but RHS is not, flip the condition.
5319 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
5320 !ISD::isNON_EXTLoad(RHS.getNode())) {
5321 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
5322 std::swap(LHS, RHS);
5323 }
5324
5325 switch (SetCCOpcode) {
5326 default: break;
5327 case ISD::SETOLT:
5328 case ISD::SETOLE:
5329 case ISD::SETUGT:
5330 case ISD::SETUGE:
5331 std::swap(LHS, RHS);
5332 break;
5333 }
5334
5335 // On a floating point condition, the flags are set as follows:
5336 // ZF PF CF op
5337 // 0 | 0 | 0 | X > Y
5338 // 0 | 0 | 1 | X < Y
5339 // 1 | 0 | 0 | X == Y
5340 // 1 | 1 | 1 | unordered
5341 switch (SetCCOpcode) {
5342 default: llvm_unreachable("Condcode should be pre-legalized away")::llvm::llvm_unreachable_internal("Condcode should be pre-legalized away"
, "llvm/lib/Target/X86/X86ISelLowering.cpp", 5342)
;
5343 case ISD::SETUEQ:
5344 case ISD::SETEQ: return X86::COND_E;
5345 case ISD::SETOLT: // flipped
5346 case ISD::SETOGT:
5347 case ISD::SETGT: return X86::COND_A;
5348 case ISD::SETOLE: // flipped
5349 case ISD::SETOGE:
5350 case ISD::SETGE: return X86::COND_AE;
5351 case ISD::SETUGT: // flipped
5352 case ISD::SETULT:
5353 case ISD::SETLT: return X86::COND_B;
5354 case ISD::SETUGE: // flipped
5355 case ISD::SETULE:
5356 case ISD::SETLE: return X86::COND_BE;
5357 case ISD::SETONE:
5358 case ISD::SETNE: return X86::COND_NE;
5359 case ISD::SETUO: return X86::COND_P;
5360 case ISD::SETO: return X86::COND_NP;
5361 case ISD::SETOEQ:
5362 case ISD::SETUNE: return X86::COND_INVALID;
5363 }
5364}
5365
5366/// Is there a floating point cmov for the specific X86 condition code?
5367/// Current x86 isa includes the following FP cmov instructions:
5368/// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
5369static bool hasFPCMov(unsigned X86CC) {
5370 switch (X86CC) {
5371 default:
5372 return false;
5373 case X86::COND_B:
5374 case X86::COND_BE:
5375 case X86::COND_E:
5376 case X86::COND_P:
5377 case X86::COND_A:
5378 case X86::COND_AE:
5379 case X86::COND_NE:
5380 case X86::COND_NP:
5381 return true;
5382 }
5383}
5384
5385static bool useVPTERNLOG(const X86Subtarget &Subtarget, MVT VT) {
5386 return Subtarget.hasVLX() || Subtarget.canExtendTo512DQ() ||
5387 VT.is512BitVector();
5388}
5389
5390bool X86TargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
5391 const CallInst &I,
5392 MachineFunction &MF,
5393 unsigned Intrinsic) const {
5394 Info.flags = MachineMemOperand::MONone;
5395 Info.offset = 0;
5396
5397 const IntrinsicData* IntrData = getIntrinsicWithChain(Intrinsic);
5398 if (!IntrData) {
5399 switch (Intrinsic) {
5400 case Intrinsic::x86_aesenc128kl:
5401 case Intrinsic::x86_aesdec128kl:
5402 Info.opc = ISD::INTRINSIC_W_CHAIN;
5403 Info.ptrVal = I.getArgOperand(1);
5404 Info.memVT = EVT::getIntegerVT(I.getType()->getContext(), 48);
5405 Info.align = Align(1);
5406 Info.flags |= MachineMemOperand::MOLoad;
5407 return true;
5408 case Intrinsic::x86_aesenc256kl:
5409 case Intrinsic::x86_aesdec256kl:
5410 Info.opc = ISD::INTRINSIC_W_CHAIN;
5411 Info.ptrVal = I.getArgOperand(1);
5412 Info.memVT = EVT::getIntegerVT(I.getType()->getContext(), 64);
5413 Info.align = Align(1);
5414 Info.flags |= MachineMemOperand::MOLoad;
5415 return true;
5416 case Intrinsic::x86_aesencwide128kl:
5417 case Intrinsic::x86_aesdecwide128kl:
5418 Info.opc = ISD::INTRINSIC_W_CHAIN;
5419 Info.ptrVal = I.getArgOperand(0);
5420 Info.memVT = EVT::getIntegerVT(I.getType()->getContext(), 48);
5421 Info.align = Align(1);
5422 Info.flags |= MachineMemOperand::MOLoad;
5423 return true;
5424 case Intrinsic::x86_aesencwide256kl:
5425 case Intrinsic::x86_aesdecwide256kl:
5426 Info.opc = ISD::INTRINSIC_W_CHAIN;
5427 Info.ptrVal = I.getArgOperand(0);
5428 Info.memVT = EVT::getIntegerVT(I.getType()->getContext(), 64);
5429 Info.align = Align(1);
5430 Info.flags |= MachineMemOperand::MOLoad;
5431 return true;
5432 }
5433 return false;
5434 }
5435
5436 switch (IntrData->Type) {
5437 case TRUNCATE_TO_MEM_VI8:
5438 case TRUNCATE_TO_MEM_VI16:
5439 case TRUNCATE_TO_MEM_VI32: {
5440 Info.opc = ISD::INTRINSIC_VOID;
5441 Info.ptrVal = I.getArgOperand(0);
5442 MVT VT = MVT::getVT(I.getArgOperand(1)->getType());
5443 MVT ScalarVT = MVT::INVALID_SIMPLE_VALUE_TYPE;
5444 if (IntrData->Type == TRUNCATE_TO_MEM_VI8)
5445 ScalarVT = MVT::i8;
5446 else if (IntrData->Type == TRUNCATE_TO_MEM_VI16)
5447 ScalarVT = MVT::i16;
5448 else if (IntrData->Type == TRUNCATE_TO_MEM_VI32)
5449 ScalarVT = MVT::i32;
5450
5451 Info.memVT = MVT::getVectorVT(ScalarVT, VT.getVectorNumElements());
5452 Info.align = Align(1);
5453 Info.flags |= MachineMemOperand::MOStore;
5454 break;
5455 }
5456 case GATHER:
5457 case GATHER_AVX2: {
5458 Info.opc = ISD::INTRINSIC_W_CHAIN;
5459 Info.ptrVal = nullptr;
5460 MVT DataVT = MVT::getVT(I.getType());
5461 MVT IndexVT = MVT::getVT(I.getArgOperand(2)->getType());
5462 unsigned NumElts = std::min(DataVT.getVectorNumElements(),
5463 IndexVT.getVectorNumElements());
5464 Info.memVT = MVT::getVectorVT(DataVT.getVectorElementType(), NumElts);
5465 Info.align = Align(1);
5466 Info.flags |= MachineMemOperand::MOLoad;
5467 break;
5468 }
5469 case SCATTER: {
5470 Info.opc = ISD::INTRINSIC_VOID;
5471 Info.ptrVal = nullptr;
5472 MVT DataVT = MVT::getVT(I.getArgOperand(3)->getType());
5473 MVT IndexVT = MVT::getVT(I.getArgOperand(2)->getType());
5474 unsigned NumElts = std::min(DataVT.getVectorNumElements(),
5475 IndexVT.getVectorNumElements());
5476 Info.memVT = MVT::getVectorVT(DataVT.getVectorElementType(), NumElts);
5477 Info.align = Align(1);
5478 Info.flags |= MachineMemOperand::MOStore;
5479 break;
5480 }
5481 default:
5482 return false;
5483 }
5484
5485 return true;
5486}
5487
5488/// Returns true if the target can instruction select the
5489/// specified FP immediate natively. If false, the legalizer will
5490/// materialize the FP immediate as a load from a constant pool.
5491bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT,
5492 bool ForCodeSize) const {
5493 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
5494 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
5495 return true;
5496 }
5497 return false;
5498}
5499
5500bool X86TargetLowering::shouldReduceLoadWidth(SDNode *Load,
5501 ISD::LoadExtType ExtTy,
5502 EVT NewVT) const {
5503 assert(cast<LoadSDNode>(Load)->isSimple() && "illegal to narrow")(static_cast <bool> (cast<LoadSDNode>(Load)->isSimple
() && "illegal to narrow") ? void (0) : __assert_fail
("cast<LoadSDNode>(Load)->isSimple() && \"illegal to narrow\""
, "llvm/lib/Target/X86/X86ISelLowering.cpp", 5503, __extension__
__PRETTY_FUNCTION__))
;
5504
5505 // "ELF Handling for Thread-Local Storage" specifies that R_X86_64_GOTTPOFF
5506 // relocation target a movq or addq instruction: don't let the load shrink.
5507 SDValue BasePtr = cast<LoadSDNode>(Load)->getBasePtr();
5508 if (BasePtr.getOpcode() == X86ISD::WrapperRIP)
5509 if (const auto *GA = dyn_cast<GlobalAddressSDNode>(BasePtr.getOperand(0)))
5510 return GA->getTargetFlags() != X86II::MO_GOTTPOFF;
5511
5512 // If this is an (1) AVX vector load with (2) multiple uses and (3) all of
5513 // those uses are extracted directly into a store, then the extract + store
5514 // can be store-folded. Therefore, it's probably not worth splitting the load.
5515 EVT VT = Load->getValueType(0);
5516 if ((VT.is256BitVector() || VT.is512BitVector()) && !Load->hasOneUse()) {
5517 for (auto UI = Load->use_begin(), UE = Load->use_end(); UI != UE; ++UI) {
5518 // Skip uses of the chain value. Result 0 of the node is the load value.
5519 if (UI.getUse().getResNo() != 0)
5520 continue;
5521
5522 // If this use is not an extract + store, it's probably worth splitting.
5523 if (UI->getOpcode() != ISD::EXTRACT_SUBVECTOR || !UI->hasOneUse() ||
5524 UI->use_begin()->getOpcode() != ISD::STORE)
5525 return true;
5526 }
5527 // All non-chain uses are extract + store.
5528 return false;
5529 }
5530
5531 return true;
5532}
5533
5534/// Returns true if it is beneficial to convert a load of a constant
5535/// to just the constant itself.
5536bool X86TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
5537 Type *Ty) const {
5538 assert(Ty->isIntegerTy())(static_cast <bool> (Ty->isIntegerTy()) ? void (0) :
__assert_fail ("Ty->isIntegerTy()", "llvm/lib/Target/X86/X86ISelLowering.cpp"
, 5538, __extension__ __PRETTY_FUNCTION__))
;
5539
5540 unsigned BitSize = Ty->getPrimitiveSizeInBits();
5541 if (BitSize == 0 || BitSize > 64)
5542 return false;
5543 return true;
5544}
5545
5546bool X86TargetLowering::reduceSelectOfFPConstantLoads(EVT CmpOpVT) const {
5547 // If we are using XMM registers in the ABI and the condition of the select is
5548 // a floating-point compare and we have blendv or conditional move, then it is
5549 // cheaper to select instead of doing a cross-register move and creating a
5550 // load that depends on the compare result.
5551 bool IsFPSetCC = CmpOpVT.isFloatingPoint() && CmpOpVT != MVT::f128;
5552 return !IsFPSetCC || !Subtarget.isTarget64BitLP64() || !Subtarget.hasAVX();
5553}
5554
5555bool X86TargetLowering::convertSelectOfConstantsToMath(EVT VT) const {
5556 // TODO: It might be a win to ease or lift this restriction, but the generic
5557 // folds in DAGCombiner conflict with vector folds for an AVX512 target.
5558 if (VT.isVector() && Subtarget.hasAVX512())
5559 return false;
5560
5561 return true;
5562}
5563
5564bool X86TargetLowering::decomposeMulByConstant(LLVMContext &Context, EVT VT,
5565 SDValue C) const {
5566 // TODO: We handle scalars using custom code, but generic combining could make
5567 // that unnecessary.
5568 APInt MulC;
5569 if (!ISD::isConstantSplatVector(C.getNode(), MulC))
5570 return false;
5571
5572 // Find the type this will be legalized too. Otherwise we might prematurely
5573 // convert this to shl+add/sub and then still have to type legalize those ops.
5574 // Another choice would be to defer the decision for illegal types until
5575 // after type legalization. But constant splat vectors of i64 can't make it
5576 // through type legalization on 32-bit targets so we would need to special
5577 // case vXi64.
5578 while (getTypeAction(Context, VT) != TypeLegal)
5579 VT = getTypeToTransformTo(Context, VT);
5580
5581 // If vector multiply is legal, assume that's faster than shl + add/sub.
5582 // Multiply is a complex op with higher latency and lower throughput in
5583 // most implementations, sub-vXi32 vector multiplies are always fast,
5584 // vXi32 mustn't have a SlowMULLD implementation, and anything larger (vXi64)
5585 // is always going to be slow.
5586 unsigned EltSizeInBits = VT.getScalarSizeInBits();
5587 if (isOperationLegal(ISD::MUL, VT) && EltSizeInBits <= 32 &&
5588 (EltSizeInBits != 32 || !Subtarget.isPMULLDSlow()))
5589 return false;
5590
5591 // shl+add, shl+sub, shl+add+neg
5592 return (MulC + 1).isPowerOf2() || (MulC - 1).isPowerOf2() ||
5593 (1 - MulC).isPowerOf2() || (-(MulC + 1)).isPowerOf2();
5594}
5595
5596bool X86TargetLowering::isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
5597 unsigned Index) const {
5598 if (!isOperationLegalOrCustom(ISD::EXTRACT_SUBVECTOR, ResVT))
5599 return false;
5600
5601 // Mask vectors support all subregister combinations and operations that
5602 // extract half of vector.
5603 if (ResVT.getVectorElementType() == MVT::i1)
5604 return Index == 0 || ((ResVT.getSizeInBits() == SrcVT.getSizeInBits()*2) &&
5605 (Index == ResVT.getVectorNumElements()));
5606
5607 return (Index % ResVT.getVectorNumElements()) == 0;
5608}
5609
5610bool X86TargetLowering::shouldScalarizeBinop(SDValue VecOp) const {
5611 unsigned Opc = VecOp.getOpcode();
5612
5613 // Assume target opcodes can't be scalarized.
5614 // TODO - do we have any exceptions?
5615 if (Opc >= ISD::BUILTIN_OP_END)
5616 return false;
5617
5618 // If the vector op is not supported, try to convert to scalar.
5619 EVT VecVT = VecOp.getValueType();
5620 if (!isOperationLegalOrCustomOrPromote(Opc, VecVT))
5621 return true;
5622
5623 // If the vector op is supported, but the scalar op is not, the transform may
5624 // not be worthwhile.
5625 EVT ScalarVT = VecVT.getScalarType();
5626 return isOperationLegalOrCustomOrPromote(Opc, ScalarVT);
5627}
5628
5629bool X86TargetLowering::shouldFormOverflowOp(unsigned Opcode, EVT VT,
5630 bool) const {
5631 // TODO: Allow vectors?
5632 if (VT.isVector())
5633 return false;
5634 return VT.isSimple() || !isOperationExpand(Opcode, VT);
5635}
5636
5637bool X86TargetLowering::isCheapToSpeculateCttz() const {
5638 // Speculate cttz only if we can directly use TZCNT.
5639 return Subtarget.hasBMI();
5640}
5641
5642bool X86TargetLowering::isCheapToSpeculateCtlz() const {
5643 // Speculate ctlz only if we can directly use LZCNT.
5644 return Subtarget.hasLZCNT();
5645}
5646
5647bool X86TargetLowering::isLoadBitCastBeneficial(EVT LoadVT, EVT BitcastVT,
5648 const SelectionDAG &DAG,
5649 const MachineMemOperand &MMO) const {
5650 if (!Subtarget.hasAVX512() && !LoadVT.isVector() && BitcastVT.isVector() &&
5651 BitcastVT.getVectorElementType() == MVT::i1)
5652 return false;
5653
5654 if (!Subtarget.hasDQI() && BitcastVT == MVT::v8i1 && LoadVT == MVT::i8)
5655 return false;
5656
5657 // If both types are legal vectors, it's always ok to convert them.
5658 if (LoadVT.isVector() && BitcastVT.isVector() &&
5659 isTypeLegal(LoadVT) && isTypeLegal(BitcastVT))
5660 return true;
5661
5662 return TargetLowering::isLoadBitCastBeneficial(LoadVT, BitcastVT, DAG, MMO);
5663}
5664
5665bool X86TargetLowering::canMergeStoresTo(unsigned AddressSpace, EVT MemVT,
5666 const MachineFunction &MF) const {
5667 // Do not merge to float value size (128 bytes) if no implicit
5668 // float attribute is set.
5669 bool NoFloat = MF.getFunction().hasFnAttribute(Attribute::NoImplicitFloat);
5670
5671 if (NoFloat) {
5672 unsigned MaxIntSize = Subtarget.is64Bit() ? 64 : 32;
5673 return (MemVT.getSizeInBits() <= MaxIntSize);
5674 }
5675 // Make sure we don't merge greater than our preferred vector
5676 // width.
5677 if (MemVT.getSizeInBits() > Subtarget.getPreferVectorWidth())
5678 return false;
5679
5680 return true;
5681}
5682
5683bool X86TargetLowering::isCtlzFast() const {
5684 return Subtarget.hasFastLZCNT();
5685}
5686
5687bool X86TargetLowering::isMaskAndCmp0FoldingBeneficial(
5688 const Instruction &AndI) const {
5689 return true;
5690}
5691
5692bool X86TargetLowering::hasAndNotCompare(SDValue Y) const {
5693 EVT VT = Y.getValueType();
5694
5695 if (VT.isVector())
5696 return false;
5697
5698 if (!Subtarget.hasBMI())
5699 return false;
5700
5701 // There are only 32-bit and 64-bit forms for 'andn'.
5702 if (VT != MVT::i32 && VT != MVT::i64)
5703 return false;
5704
5705 return !isa<ConstantSDNode>(Y);
5706}
5707
5708bool X86TargetLowering::hasAndNot(SDValue Y) const {
5709 EVT VT = Y.getValueType();
5710
5711 if (!VT.isVector())
5712 return hasAndNotCompare(Y);
5713
5714 // Vector.
5715
5716 if (!Subtarget.hasSSE1() || VT.getSizeInBits() < 128)
5717 return false;
5718
5719 if (VT == MVT::v4i32)
5720 return true;
5721
5722 return Subtarget.hasSSE2();
5723}
5724
5725bool X86TargetLowering::hasBitTest(SDValue X, SDValue Y) const {
5726 return X.getValueType().isScalarInteger(); // 'bt'
5727}
5728
5729bool X86TargetLowering::
5730 shouldProduceAndByConstByHoistingConstFromShiftsLHSOfAnd(
5731 SDValue X, ConstantSDNode *XC, ConstantSDNode *CC, SDValue Y,
5732 unsigned OldShiftOpcode, unsigned NewShiftOpcode,
5733 SelectionDAG &DAG) const {
5734 // Does baseline recommend not to perform the fold by default?
5735 if (!TargetLowering::shouldProduceAndByConstByHoistingConstFromShiftsLHSOfAnd(
5736 X, XC, CC, Y, OldShiftOpcode, NewShiftOpcode, DAG))
5737 return false;
5738 // For scalars this transform is always beneficial.
5739 if (X.getValueType().isScalarInteger())
5740 return true;
5741 // If all the shift amounts are identical, then transform is beneficial even
5742 // with rudimentary SSE2 shifts.
5743 if (DAG.isSplatValue(Y, /*AllowUndefs=*/true))
5744 return true;
5745 // If we have AVX2 with it's powerful shift operations, then it's also good.
5746 if (Subtarget.hasAVX2())
5747 return true;
5748 // Pre-AVX2 vector codegen for this pattern is best for variant with 'shl'.
5749 return NewShiftOpcode == ISD::SHL;
5750}
5751
5752bool X86TargetLowering::shouldFoldConstantShiftPairToMask(
5753 const SDNode *N, CombineLevel Level) const {
5754 assert(((N->getOpcode() == ISD::SHL &&(static_cast <bool> (((N->getOpcode() == ISD::SHL &&
N->getOperand(0).getOpcode() == ISD::SRL) || (N->getOpcode
() == ISD::SRL && N->getOperand(0).getOpcode() == ISD
::SHL)) && "Expected shift-shift mask") ? void (0) : __assert_fail
("((N->getOpcode() == ISD::SHL && N->getOperand(0).getOpcode() == ISD::SRL) || (N->getOpcode() == ISD::SRL && N->getOperand(0).getOpcode() == ISD::SHL)) && \"Expected shift-shift mask\""
, "llvm/lib/Target/X86/X86ISelLowering.cpp", 5758, __extension__
__PRETTY_FUNCTION__))
5755 N->getOperand(0).getOpcode() == ISD::SRL) ||(static_cast <bool> (((N->getOpcode() == ISD::SHL &&
N->getOperand(0).getOpcode() == ISD::SRL) || (N->getOpcode
() == ISD::SRL && N->getOperand(0).getOpcode() == ISD
::SHL)) && "Expected shift-shift mask") ? void (0) : __assert_fail
("((N->getOpcode() == ISD::SHL && N->getOperand(0).getOpcode() == ISD::SRL) || (N->getOpcode() == ISD::SRL && N->getOperand(0).getOpcode() == ISD::SHL)) && \"Expected shift-shift mask\""
, "llvm/lib/Target/X86/X86ISelLowering.cpp", 5758, __extension__
__PRETTY_FUNCTION__))
5756 (N->getOpcode() == ISD::SRL &&(static_cast <bool> (((N->getOpcode() == ISD::SHL &&
N->getOperand(0).getOpcode() == ISD::SRL) || (N->getOpcode
() == ISD::SRL && N->getOperand(0).getOpcode() == ISD
::SHL)) && "Expected shift-shift mask") ? void (0) : __assert_fail
("((N->getOpcode() == ISD::SHL && N->getOperand(0).getOpcode() == ISD::SRL) || (N->getOpcode() == ISD::SRL && N->getOperand(0).getOpcode() == ISD::SHL)) && \"Expected shift-shift mask\""
, "llvm/lib/Target/X86/X86ISelLowering.cpp", 5758, __extension__
__PRETTY_FUNCTION__))
5757 N->getOperand(0).getOpcode() == ISD::SHL)) &&(static_cast <bool> (((N->getOpcode() == ISD::SHL &&
N->getOperand(0).getOpcode() == ISD::SRL) || (N->getOpcode
() == ISD::SRL && N->getOperand(0).getOpcode() == ISD
::SHL)) && "Expected shift-shift mask") ? void (0) : __assert_fail
("((N->getOpcode() == ISD::SHL && N->getOperand(0).getOpcode() == ISD::SRL) || (N->getOpcode() == ISD::SRL && N->getOperand(0).getOpcode() == ISD::SHL)) && \"Expected shift-shift mask\""
, "llvm/lib/Target/X86/X86ISelLowering.cpp", 5758, __extension__
__PRETTY_FUNCTION__))
5758 "Expected shift-shift mask")(static_cast <bool> (((N->getOpcode() == ISD::SHL &&
N->getOperand(0).getOpcode() == ISD::SRL) || (N->getOpcode
() == ISD::SRL && N->getOperand(0).getOpcode() == ISD
::SHL)) && "Expected shift-shift mask") ? void (0) : __assert_fail
("((N->getOpcode() == ISD::SHL && N->getOperand(0).getOpcode() == ISD::SRL) || (N->getOpcode() == ISD::SRL && N->getOperand(0).getOpcode() == ISD::SHL)) && \"Expected shift-shift mask\""
, "llvm/lib/Target/X86/X86ISelLowering.cpp", 5758, __extension__
__PRETTY_FUNCTION__))
;
5759 EVT VT = N->getValueType(0);
5760 if ((Subtarget.hasFastVectorShiftMasks() && VT.isVector()) ||
5761 (Subtarget.hasFastScalarShiftMasks() && !VT.isVector())) {
5762 // Only fold if the shift values are equal - so it folds to AND.
5763 // TODO - we should fold if either is a non-uniform vector but we don't do
5764 // the fold for non-splats yet.
5765 return N->getOperand(1) == N->getOperand(0).getOperand(1);
5766 }
5767 return TargetLoweringBase::shouldFoldConstantShiftPairToMask(N, Level);
5768}
5769
5770bool X86TargetLowering::shouldFoldMaskToVariableShiftPair(SDValue Y) const {
5771 EVT VT = Y.getValueType();
5772
5773 // For vectors, we don't have a preference, but we probably want a mask.
5774 if (VT.isVector())
5775 return false;
5776
5777 // 64-bit shifts on 32-bit targets produce really bad bloated code.
5778 if (VT == MVT::i64 && !Subtarget.is64Bit())
5779 return false;
5780
5781 return true;
5782}
5783
5784bool X86TargetLowering::shouldExpandShift(SelectionDAG &DAG,
5785 SDNode *N) const {
5786 if (DAG.getMachineFunction().getFunction().hasMinSize() &&
5787 !Subtarget.isOSWindows())
5788 return false;
5789 return true;
5790}
5791
5792bool X86TargetLowering::shouldSplatInsEltVarIndex(EVT VT) const {
5793 // Any legal vector type can be splatted more efficiently than
5794 // loading/spilling from memory.
5795 return isTypeLegal(VT);
5796}
5797
5798MVT X86TargetLowering::hasFastEqualityCompare(unsigned NumBits) const {
5799 MVT VT = MVT::getIntegerVT(NumBits);
5800 if (isTypeLegal(VT))
5801 return VT;
5802
5803 // PMOVMSKB can handle this.
5804 if (NumBits == 128 && isTypeLegal(MVT::v16i8))
5805 return MVT::v16i8;
5806
5807 // VPMOVMSKB can handle this.
5808 if (NumBits == 256 && isTypeLegal(MVT::v32i8))
5809 return MVT::v32i8;
5810
5811 // TODO: Allow 64-bit type for 32-bit target.
5812 // TODO: 512-bit types should be allowed, but make sure that those
5813 // cases are handled in combineVectorSizedSetCCEquality().
5814
5815 return MVT::INVALID_SIMPLE_VALUE_TYPE;
5816}
5817
5818/// Val is the undef sentinel value or equal to the specified value.
5819static bool isUndefOrEqual(int Val, int CmpVal) {
5820 return ((Val == SM_SentinelUndef) || (Val == CmpVal));
5821}
5822
5823/// Return true if every element in Mask is the undef sentinel value or equal to
5824/// the specified value..
5825static bool isUndefOrEqual(ArrayRef<int> Mask, int CmpVal) {
5826 return llvm::all_of(Mask, [CmpVal](int M) {
5827 return (M == SM_SentinelUndef) || (M == CmpVal);
5828 });
5829}
5830
5831/// Val is either the undef or zero sentinel value.
5832static bool isUndefOrZero(int Val) {
5833 return ((Val == SM_SentinelUndef) || (Val == SM_SentinelZero));
5834}
5835
5836/// Return true if every element in Mask, beginning from position Pos and ending
5837/// in Pos+Size is the undef sentinel value.
5838static bool isUndefInRange(ArrayRef<int> Mask, unsigned Pos, unsigned Size) {
5839 return llvm::all_of(Mask.slice(Pos, Size),
5840 [](int M) { return M == SM_SentinelUndef; });
5841}
5842
5843/// Return true if the mask creates a vector whose lower half is undefined.
5844static bool isUndefLowerHalf(ArrayRef<int> Mask) {
5845 unsigned NumElts = Mask.size();
5846 return isUndefInRange(Mask, 0, NumElts / 2);
5847}
5848
5849/// Return true if the mask creates a vector whose upper half is undefined.
5850static bool isUndefUpperHalf(ArrayRef<int> Mask) {
5851 unsigned NumElts = Mask.size();
5852 return isUndefInRange(Mask, NumElts / 2, NumElts / 2);
5853}
5854
5855/// Return true if Val falls within the specified range (L, H].
5856static bool isInRange(int Val, int Low, int Hi) {
5857 return (Val >= Low && Val < Hi);
5858}
5859
5860/// Return true if the value of any element in Mask falls within the specified
5861/// range (L, H].
5862static bool isAnyInRange(ArrayRef<int> Mask, int Low, int Hi) {
5863 return llvm::any_of(Mask, [Low, Hi](int M) { return isInRange(M, Low, Hi); });
5864}
5865
5866/// Return true if the value of any element in Mask is the zero sentinel value.
5867static bool isAnyZero(ArrayRef<int> Mask) {
5868 return llvm::any_of(Mask, [](int M) { return M == SM_SentinelZero; });
5869}
5870
5871/// Return true if the value of any element in Mask is the zero or undef
5872/// sentinel values.
5873static bool isAnyZeroOrUndef(ArrayRef<int> Mask) {
5874 return llvm::any_of(Mask, [](int M) {
5875 return M == SM_SentinelZero || M == SM_SentinelUndef;
5876 });
5877}
5878
5879/// Return true if Val is undef or if its value falls within the
5880/// specified range (L, H].
5881static bool isUndefOrInRange(int Val, int Low, int Hi) {
5882 return (Val == SM_SentinelUndef) || isInRange(Val, Low, Hi);
5883}
5884
5885/// Return true if every element in Mask is undef or if its value
5886/// falls within the specified range (L, H].
5887static bool isUndefOrInRange(ArrayRef<int> Mask, int Low, int Hi) {
5888 return llvm::all_of(
5889 Mask, [Low, Hi](int M) { return isUndefOrInRange(M, Low, Hi); });
5890}
5891
5892/// Return true if Val is undef, zero or if its value falls within the
5893/// specified range (L, H].
5894static bool isUndefOrZeroOrInRange(int Val, int Low, int Hi) {
5895 return isUndefOrZero(Val) || isInRange(Val, Low, Hi);
5896}
5897
5898/// Return true if every element in Mask is undef, zero or if its value
5899/// falls within the specified range (L, H].
5900static bool isUndefOrZeroOrInRange(ArrayRef<int> Mask, int Low, int Hi) {
5901 return llvm::all_of(
5902 Mask, [Low, Hi](int M) { return isUndefOrZeroOrInRange(M, Low, Hi); });
5903}
5904
5905/// Return true if every element in Mask, beginning
5906/// from position Pos and ending in Pos + Size, falls within the specified
5907/// sequence (Low, Low + Step, ..., Low + (Size - 1) * Step) or is undef.
5908static bool isSequentialOrUndefInRange(ArrayRef<int> Mask, unsigned Pos,
5909 unsigned Size, int Low, int Step = 1) {
5910 for (unsigned i = Pos, e = Pos + Size; i != e; ++i, Low += Step)
5911 if (!isUndefOrEqual(Mask[i], Low))
5912 return false;
5913