Bug Summary

File:llvm/lib/Target/X86/X86ISelLowering.cpp
Warning:line 16685, column 31
Division by zero

Annotated Source Code

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clang -cc1 -cc1 -triple x86_64-pc-linux-gnu -analyze -disable-free -clear-ast-before-backend -disable-llvm-verifier -discard-value-names -main-file-name X86ISelLowering.cpp -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=cplusplus -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -analyzer-config-compatibility-mode=true -mrelocation-model pic -pic-level 2 -mframe-pointer=none -fmath-errno -fno-rounding-math -mconstructor-aliases -funwind-tables=2 -target-cpu x86-64 -tune-cpu generic -debugger-tuning=gdb -ffunction-sections -fdata-sections -fcoverage-compilation-dir=/build/llvm-toolchain-snapshot-14~++20211016100712+8e1d532707fd/build-llvm -resource-dir /usr/lib/llvm-14/lib/clang/14.0.0 -D _DEBUG -D _GNU_SOURCE -D __STDC_CONSTANT_MACROS -D __STDC_FORMAT_MACROS -D __STDC_LIMIT_MACROS -I lib/Target/X86 -I /build/llvm-toolchain-snapshot-14~++20211016100712+8e1d532707fd/llvm/lib/Target/X86 -I include -I /build/llvm-toolchain-snapshot-14~++20211016100712+8e1d532707fd/llvm/include -D NDEBUG -U NDEBUG -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/10/../../../../include/c++/10 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/10/../../../../include/x86_64-linux-gnu/c++/10 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/10/../../../../include/c++/10/backward -internal-isystem /usr/lib/llvm-14/lib/clang/14.0.0/include -internal-isystem /usr/local/include -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/10/../../../../x86_64-linux-gnu/include -internal-externc-isystem /usr/include/x86_64-linux-gnu -internal-externc-isystem /include -internal-externc-isystem /usr/include -O2 -Wno-unused-command-line-argument -Wno-unknown-warning-option -Wno-unused-parameter -Wwrite-strings -Wno-missing-field-initializers -Wno-long-long -Wno-maybe-uninitialized -Wno-class-memaccess -Wno-redundant-move -Wno-pessimizing-move -Wno-noexcept-type -Wno-comment -std=c++14 -fdeprecated-macro -fdebug-compilation-dir=/build/llvm-toolchain-snapshot-14~++20211016100712+8e1d532707fd/build-llvm -ferror-limit 19 -fvisibility hidden -fvisibility-inlines-hidden -fgnuc-version=4.2.1 -fcolor-diagnostics -vectorize-loops -vectorize-slp -analyzer-output=html -analyzer-config stable-report-filename=true -faddrsig -D__GCC_HAVE_DWARF2_CFI_ASM=1 -o /tmp/scan-build-2021-10-17-004846-21170-1 -x c++ /build/llvm-toolchain-snapshot-14~++20211016100712+8e1d532707fd/llvm/lib/Target/X86/X86ISelLowering.cpp
1//===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines the interfaces that X86 uses to lower LLVM code into a
10// selection DAG.
11//
12//===----------------------------------------------------------------------===//
13
14#include "X86ISelLowering.h"
15#include "MCTargetDesc/X86ShuffleDecode.h"
16#include "X86.h"
17#include "X86CallingConv.h"
18#include "X86FrameLowering.h"
19#include "X86InstrBuilder.h"
20#include "X86IntrinsicsInfo.h"
21#include "X86MachineFunctionInfo.h"
22#include "X86TargetMachine.h"
23#include "X86TargetObjectFile.h"
24#include "llvm/ADT/SmallBitVector.h"
25#include "llvm/ADT/SmallSet.h"
26#include "llvm/ADT/Statistic.h"
27#include "llvm/ADT/StringExtras.h"
28#include "llvm/ADT/StringSwitch.h"
29#include "llvm/Analysis/BlockFrequencyInfo.h"
30#include "llvm/Analysis/EHPersonalities.h"
31#include "llvm/Analysis/ObjCARCUtil.h"
32#include "llvm/Analysis/ProfileSummaryInfo.h"
33#include "llvm/Analysis/VectorUtils.h"
34#include "llvm/CodeGen/IntrinsicLowering.h"
35#include "llvm/CodeGen/MachineFrameInfo.h"
36#include "llvm/CodeGen/MachineFunction.h"
37#include "llvm/CodeGen/MachineInstrBuilder.h"
38#include "llvm/CodeGen/MachineJumpTableInfo.h"
39#include "llvm/CodeGen/MachineLoopInfo.h"
40#include "llvm/CodeGen/MachineModuleInfo.h"
41#include "llvm/CodeGen/MachineRegisterInfo.h"
42#include "llvm/CodeGen/TargetLowering.h"
43#include "llvm/CodeGen/WinEHFuncInfo.h"
44#include "llvm/IR/CallingConv.h"
45#include "llvm/IR/Constants.h"
46#include "llvm/IR/DerivedTypes.h"
47#include "llvm/IR/DiagnosticInfo.h"
48#include "llvm/IR/Function.h"
49#include "llvm/IR/GlobalAlias.h"
50#include "llvm/IR/GlobalVariable.h"
51#include "llvm/IR/IRBuilder.h"
52#include "llvm/IR/Instructions.h"
53#include "llvm/IR/Intrinsics.h"
54#include "llvm/IR/PatternMatch.h"
55#include "llvm/MC/MCAsmInfo.h"
56#include "llvm/MC/MCContext.h"
57#include "llvm/MC/MCExpr.h"
58#include "llvm/MC/MCSymbol.h"
59#include "llvm/Support/CommandLine.h"
60#include "llvm/Support/Debug.h"
61#include "llvm/Support/ErrorHandling.h"
62#include "llvm/Support/KnownBits.h"
63#include "llvm/Support/MathExtras.h"
64#include "llvm/Target/TargetOptions.h"
65#include <algorithm>
66#include <bitset>
67#include <cctype>
68#include <numeric>
69using namespace llvm;
70
71#define DEBUG_TYPE"x86-isel" "x86-isel"
72
73STATISTIC(NumTailCalls, "Number of tail calls")static llvm::Statistic NumTailCalls = {"x86-isel", "NumTailCalls"
, "Number of tail calls"}
;
74
75static cl::opt<int> ExperimentalPrefInnermostLoopAlignment(
76 "x86-experimental-pref-innermost-loop-alignment", cl::init(4),
77 cl::desc(
78 "Sets the preferable loop alignment for experiments (as log2 bytes) "
79 "for innermost loops only. If specified, this option overrides "
80 "alignment set by x86-experimental-pref-loop-alignment."),
81 cl::Hidden);
82
83static cl::opt<bool> MulConstantOptimization(
84 "mul-constant-optimization", cl::init(true),
85 cl::desc("Replace 'mul x, Const' with more effective instructions like "
86 "SHIFT, LEA, etc."),
87 cl::Hidden);
88
89static cl::opt<bool> ExperimentalUnorderedISEL(
90 "x86-experimental-unordered-atomic-isel", cl::init(false),
91 cl::desc("Use LoadSDNode and StoreSDNode instead of "
92 "AtomicSDNode for unordered atomic loads and "
93 "stores respectively."),
94 cl::Hidden);
95
96/// Call this when the user attempts to do something unsupported, like
97/// returning a double without SSE2 enabled on x86_64. This is not fatal, unlike
98/// report_fatal_error, so calling code should attempt to recover without
99/// crashing.
100static void errorUnsupported(SelectionDAG &DAG, const SDLoc &dl,
101 const char *Msg) {
102 MachineFunction &MF = DAG.getMachineFunction();
103 DAG.getContext()->diagnose(
104 DiagnosticInfoUnsupported(MF.getFunction(), Msg, dl.getDebugLoc()));
105}
106
107X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
108 const X86Subtarget &STI)
109 : TargetLowering(TM), Subtarget(STI) {
110 bool UseX87 = !Subtarget.useSoftFloat() && Subtarget.hasX87();
111 X86ScalarSSEf64 = Subtarget.hasSSE2();
112 X86ScalarSSEf32 = Subtarget.hasSSE1();
113 X86ScalarSSEf16 = Subtarget.hasFP16();
114 MVT PtrVT = MVT::getIntegerVT(TM.getPointerSizeInBits(0));
115
116 // Set up the TargetLowering object.
117
118 // X86 is weird. It always uses i8 for shift amounts and setcc results.
119 setBooleanContents(ZeroOrOneBooleanContent);
120 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
121 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
122
123 // For 64-bit, since we have so many registers, use the ILP scheduler.
124 // For 32-bit, use the register pressure specific scheduling.
125 // For Atom, always use ILP scheduling.
126 if (Subtarget.isAtom())
127 setSchedulingPreference(Sched::ILP);
128 else if (Subtarget.is64Bit())
129 setSchedulingPreference(Sched::ILP);
130 else
131 setSchedulingPreference(Sched::RegPressure);
132 const X86RegisterInfo *RegInfo = Subtarget.getRegisterInfo();
133 setStackPointerRegisterToSaveRestore(RegInfo->getStackRegister());
134
135 // Bypass expensive divides and use cheaper ones.
136 if (TM.getOptLevel() >= CodeGenOpt::Default) {
137 if (Subtarget.hasSlowDivide32())
138 addBypassSlowDiv(32, 8);
139 if (Subtarget.hasSlowDivide64() && Subtarget.is64Bit())
140 addBypassSlowDiv(64, 32);
141 }
142
143 // Setup Windows compiler runtime calls.
144 if (Subtarget.isTargetWindowsMSVC() || Subtarget.isTargetWindowsItanium()) {
145 static const struct {
146 const RTLIB::Libcall Op;
147 const char * const Name;
148 const CallingConv::ID CC;
149 } LibraryCalls[] = {
150 { RTLIB::SDIV_I64, "_alldiv", CallingConv::X86_StdCall },
151 { RTLIB::UDIV_I64, "_aulldiv", CallingConv::X86_StdCall },
152 { RTLIB::SREM_I64, "_allrem", CallingConv::X86_StdCall },
153 { RTLIB::UREM_I64, "_aullrem", CallingConv::X86_StdCall },
154 { RTLIB::MUL_I64, "_allmul", CallingConv::X86_StdCall },
155 };
156
157 for (const auto &LC : LibraryCalls) {
158 setLibcallName(LC.Op, LC.Name);
159 setLibcallCallingConv(LC.Op, LC.CC);
160 }
161 }
162
163 if (Subtarget.getTargetTriple().isOSMSVCRT()) {
164 // MSVCRT doesn't have powi; fall back to pow
165 setLibcallName(RTLIB::POWI_F32, nullptr);
166 setLibcallName(RTLIB::POWI_F64, nullptr);
167 }
168
169 // If we don't have cmpxchg8b(meaing this is a 386/486), limit atomic size to
170 // 32 bits so the AtomicExpandPass will expand it so we don't need cmpxchg8b.
171 // FIXME: Should we be limiting the atomic size on other configs? Default is
172 // 1024.
173 if (!Subtarget.hasCmpxchg8b())
174 setMaxAtomicSizeInBitsSupported(32);
175
176 // Set up the register classes.
177 addRegisterClass(MVT::i8, &X86::GR8RegClass);
178 addRegisterClass(MVT::i16, &X86::GR16RegClass);
179 addRegisterClass(MVT::i32, &X86::GR32RegClass);
180 if (Subtarget.is64Bit())
181 addRegisterClass(MVT::i64, &X86::GR64RegClass);
182
183 for (MVT VT : MVT::integer_valuetypes())
184 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
185
186 // We don't accept any truncstore of integer registers.
187 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
188 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
189 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
190 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
191 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
192 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
193
194 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
195
196 // SETOEQ and SETUNE require checking two conditions.
197 for (auto VT : {MVT::f32, MVT::f64, MVT::f80}) {
198 setCondCodeAction(ISD::SETOEQ, VT, Expand);
199 setCondCodeAction(ISD::SETUNE, VT, Expand);
200 }
201
202 // Integer absolute.
203 if (Subtarget.hasCMov()) {
204 setOperationAction(ISD::ABS , MVT::i16 , Custom);
205 setOperationAction(ISD::ABS , MVT::i32 , Custom);
206 if (Subtarget.is64Bit())
207 setOperationAction(ISD::ABS , MVT::i64 , Custom);
208 }
209
210 // Signed saturation subtraction.
211 setOperationAction(ISD::SSUBSAT , MVT::i8 , Custom);
212 setOperationAction(ISD::SSUBSAT , MVT::i16 , Custom);
213 setOperationAction(ISD::SSUBSAT , MVT::i32 , Custom);
214 if (Subtarget.is64Bit())
215 setOperationAction(ISD::SSUBSAT , MVT::i64 , Custom);
216
217 // Funnel shifts.
218 for (auto ShiftOp : {ISD::FSHL, ISD::FSHR}) {
219 // For slow shld targets we only lower for code size.
220 LegalizeAction ShiftDoubleAction = Subtarget.isSHLDSlow() ? Custom : Legal;
221
222 setOperationAction(ShiftOp , MVT::i8 , Custom);
223 setOperationAction(ShiftOp , MVT::i16 , Custom);
224 setOperationAction(ShiftOp , MVT::i32 , ShiftDoubleAction);
225 if (Subtarget.is64Bit())
226 setOperationAction(ShiftOp , MVT::i64 , ShiftDoubleAction);
227 }
228
229 if (!Subtarget.useSoftFloat()) {
230 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
231 // operation.
232 setOperationAction(ISD::UINT_TO_FP, MVT::i8, Promote);
233 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::i8, Promote);
234 setOperationAction(ISD::UINT_TO_FP, MVT::i16, Promote);
235 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::i16, Promote);
236 // We have an algorithm for SSE2, and we turn this into a 64-bit
237 // FILD or VCVTUSI2SS/SD for other targets.
238 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
239 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::i32, Custom);
240 // We have an algorithm for SSE2->double, and we turn this into a
241 // 64-bit FILD followed by conditional FADD for other targets.
242 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
243 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::i64, Custom);
244
245 // Promote i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
246 // this operation.
247 setOperationAction(ISD::SINT_TO_FP, MVT::i8, Promote);
248 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::i8, Promote);
249 // SSE has no i16 to fp conversion, only i32. We promote in the handler
250 // to allow f80 to use i16 and f64 to use i16 with sse1 only
251 setOperationAction(ISD::SINT_TO_FP, MVT::i16, Custom);
252 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::i16, Custom);
253 // f32 and f64 cases are Legal with SSE1/SSE2, f80 case is not
254 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
255 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::i32, Custom);
256 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
257 // are Legal, f80 is custom lowered.
258 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
259 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::i64, Custom);
260
261 // Promote i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
262 // this operation.
263 setOperationAction(ISD::FP_TO_SINT, MVT::i8, Promote);
264 // FIXME: This doesn't generate invalid exception when it should. PR44019.
265 setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::i8, Promote);
266 setOperationAction(ISD::FP_TO_SINT, MVT::i16, Custom);
267 setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::i16, Custom);
268 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
269 setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::i32, Custom);
270 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
271 // are Legal, f80 is custom lowered.
272 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
273 setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::i64, Custom);
274
275 // Handle FP_TO_UINT by promoting the destination to a larger signed
276 // conversion.
277 setOperationAction(ISD::FP_TO_UINT, MVT::i8, Promote);
278 // FIXME: This doesn't generate invalid exception when it should. PR44019.
279 setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::i8, Promote);
280 setOperationAction(ISD::FP_TO_UINT, MVT::i16, Promote);
281 // FIXME: This doesn't generate invalid exception when it should. PR44019.
282 setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::i16, Promote);
283 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
284 setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::i32, Custom);
285 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
286 setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::i64, Custom);
287
288 setOperationAction(ISD::LRINT, MVT::f32, Custom);
289 setOperationAction(ISD::LRINT, MVT::f64, Custom);
290 setOperationAction(ISD::LLRINT, MVT::f32, Custom);
291 setOperationAction(ISD::LLRINT, MVT::f64, Custom);
292
293 if (!Subtarget.is64Bit()) {
294 setOperationAction(ISD::LRINT, MVT::i64, Custom);
295 setOperationAction(ISD::LLRINT, MVT::i64, Custom);
296 }
297 }
298
299 if (Subtarget.hasSSE2()) {
300 // Custom lowering for saturating float to int conversions.
301 // We handle promotion to larger result types manually.
302 for (MVT VT : { MVT::i8, MVT::i16, MVT::i32 }) {
303 setOperationAction(ISD::FP_TO_UINT_SAT, VT, Custom);
304 setOperationAction(ISD::FP_TO_SINT_SAT, VT, Custom);
305 }
306 if (Subtarget.is64Bit()) {
307 setOperationAction(ISD::FP_TO_UINT_SAT, MVT::i64, Custom);
308 setOperationAction(ISD::FP_TO_SINT_SAT, MVT::i64, Custom);
309 }
310 }
311
312 // Handle address space casts between mixed sized pointers.
313 setOperationAction(ISD::ADDRSPACECAST, MVT::i32, Custom);
314 setOperationAction(ISD::ADDRSPACECAST, MVT::i64, Custom);
315
316 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
317 if (!X86ScalarSSEf64) {
318 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
319 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
320 if (Subtarget.is64Bit()) {
321 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
322 // Without SSE, i64->f64 goes through memory.
323 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
324 }
325 } else if (!Subtarget.is64Bit())
326 setOperationAction(ISD::BITCAST , MVT::i64 , Custom);
327
328 // Scalar integer divide and remainder are lowered to use operations that
329 // produce two results, to match the available instructions. This exposes
330 // the two-result form to trivial CSE, which is able to combine x/y and x%y
331 // into a single instruction.
332 //
333 // Scalar integer multiply-high is also lowered to use two-result
334 // operations, to match the available instructions. However, plain multiply
335 // (low) operations are left as Legal, as there are single-result
336 // instructions for this in x86. Using the two-result multiply instructions
337 // when both high and low results are needed must be arranged by dagcombine.
338 for (auto VT : { MVT::i8, MVT::i16, MVT::i32, MVT::i64 }) {
339 setOperationAction(ISD::MULHS, VT, Expand);
340 setOperationAction(ISD::MULHU, VT, Expand);
341 setOperationAction(ISD::SDIV, VT, Expand);
342 setOperationAction(ISD::UDIV, VT, Expand);
343 setOperationAction(ISD::SREM, VT, Expand);
344 setOperationAction(ISD::UREM, VT, Expand);
345 }
346
347 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
348 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
349 for (auto VT : { MVT::f32, MVT::f64, MVT::f80, MVT::f128,
350 MVT::i8, MVT::i16, MVT::i32, MVT::i64 }) {
351 setOperationAction(ISD::BR_CC, VT, Expand);
352 setOperationAction(ISD::SELECT_CC, VT, Expand);
353 }
354 if (Subtarget.is64Bit())
355 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
356 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
357 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
358 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
359
360 setOperationAction(ISD::FREM , MVT::f32 , Expand);
361 setOperationAction(ISD::FREM , MVT::f64 , Expand);
362 setOperationAction(ISD::FREM , MVT::f80 , Expand);
363 setOperationAction(ISD::FREM , MVT::f128 , Expand);
364
365 if (!Subtarget.useSoftFloat() && Subtarget.hasX87()) {
366 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
367 setOperationAction(ISD::SET_ROUNDING , MVT::Other, Custom);
368 }
369
370 // Promote the i8 variants and force them on up to i32 which has a shorter
371 // encoding.
372 setOperationPromotedToType(ISD::CTTZ , MVT::i8 , MVT::i32);
373 setOperationPromotedToType(ISD::CTTZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
374
375 if (Subtarget.hasBMI()) {
376 // Promote the i16 zero undef variant and force it on up to i32 when tzcnt
377 // is enabled.
378 setOperationPromotedToType(ISD::CTTZ_ZERO_UNDEF, MVT::i16, MVT::i32);
379 } else {
380 setOperationAction(ISD::CTTZ, MVT::i16, Custom);
381 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
382 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Legal);
383 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Legal);
384 if (Subtarget.is64Bit()) {
385 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
386 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Legal);
387 }
388 }
389
390 if (Subtarget.hasLZCNT()) {
391 // When promoting the i8 variants, force them to i32 for a shorter
392 // encoding.
393 setOperationPromotedToType(ISD::CTLZ , MVT::i8 , MVT::i32);
394 setOperationPromotedToType(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
395 } else {
396 for (auto VT : {MVT::i8, MVT::i16, MVT::i32, MVT::i64}) {
397 if (VT == MVT::i64 && !Subtarget.is64Bit())
398 continue;
399 setOperationAction(ISD::CTLZ , VT, Custom);
400 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Custom);
401 }
402 }
403
404 for (auto Op : {ISD::FP16_TO_FP, ISD::STRICT_FP16_TO_FP, ISD::FP_TO_FP16,
405 ISD::STRICT_FP_TO_FP16}) {
406 // Special handling for half-precision floating point conversions.
407 // If we don't have F16C support, then lower half float conversions
408 // into library calls.
409 setOperationAction(
410 Op, MVT::f32,
411 (!Subtarget.useSoftFloat() && Subtarget.hasF16C()) ? Custom : Expand);
412 // There's never any support for operations beyond MVT::f32.
413 setOperationAction(Op, MVT::f64, Expand);
414 setOperationAction(Op, MVT::f80, Expand);
415 setOperationAction(Op, MVT::f128, Expand);
416 }
417
418 setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Expand);
419 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Expand);
420 setLoadExtAction(ISD::EXTLOAD, MVT::f80, MVT::f16, Expand);
421 setLoadExtAction(ISD::EXTLOAD, MVT::f128, MVT::f16, Expand);
422 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
423 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
424 setTruncStoreAction(MVT::f80, MVT::f16, Expand);
425 setTruncStoreAction(MVT::f128, MVT::f16, Expand);
426
427 setOperationAction(ISD::PARITY, MVT::i8, Custom);
428 setOperationAction(ISD::PARITY, MVT::i16, Custom);
429 setOperationAction(ISD::PARITY, MVT::i32, Custom);
430 if (Subtarget.is64Bit())
431 setOperationAction(ISD::PARITY, MVT::i64, Custom);
432 if (Subtarget.hasPOPCNT()) {
433 setOperationPromotedToType(ISD::CTPOP, MVT::i8, MVT::i32);
434 // popcntw is longer to encode than popcntl and also has a false dependency
435 // on the dest that popcntl hasn't had since Cannon Lake.
436 setOperationPromotedToType(ISD::CTPOP, MVT::i16, MVT::i32);
437 } else {
438 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
439 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
440 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
441 if (Subtarget.is64Bit())
442 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
443 else
444 setOperationAction(ISD::CTPOP , MVT::i64 , Custom);
445 }
446
447 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
448
449 if (!Subtarget.hasMOVBE())
450 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
451
452 // X86 wants to expand cmov itself.
453 for (auto VT : { MVT::f32, MVT::f64, MVT::f80, MVT::f128 }) {
454 setOperationAction(ISD::SELECT, VT, Custom);
455 setOperationAction(ISD::SETCC, VT, Custom);
456 setOperationAction(ISD::STRICT_FSETCC, VT, Custom);
457 setOperationAction(ISD::STRICT_FSETCCS, VT, Custom);
458 }
459 for (auto VT : { MVT::i8, MVT::i16, MVT::i32, MVT::i64 }) {
460 if (VT == MVT::i64 && !Subtarget.is64Bit())
461 continue;
462 setOperationAction(ISD::SELECT, VT, Custom);
463 setOperationAction(ISD::SETCC, VT, Custom);
464 }
465
466 // Custom action for SELECT MMX and expand action for SELECT_CC MMX
467 setOperationAction(ISD::SELECT, MVT::x86mmx, Custom);
468 setOperationAction(ISD::SELECT_CC, MVT::x86mmx, Expand);
469
470 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
471 // NOTE: EH_SJLJ_SETJMP/_LONGJMP are not recommended, since
472 // LLVM/Clang supports zero-cost DWARF and SEH exception handling.
473 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
474 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
475 setOperationAction(ISD::EH_SJLJ_SETUP_DISPATCH, MVT::Other, Custom);
476 if (TM.Options.ExceptionModel == ExceptionHandling::SjLj)
477 setLibcallName(RTLIB::UNWIND_RESUME, "_Unwind_SjLj_Resume");
478
479 // Darwin ABI issue.
480 for (auto VT : { MVT::i32, MVT::i64 }) {
481 if (VT == MVT::i64 && !Subtarget.is64Bit())
482 continue;
483 setOperationAction(ISD::ConstantPool , VT, Custom);
484 setOperationAction(ISD::JumpTable , VT, Custom);
485 setOperationAction(ISD::GlobalAddress , VT, Custom);
486 setOperationAction(ISD::GlobalTLSAddress, VT, Custom);
487 setOperationAction(ISD::ExternalSymbol , VT, Custom);
488 setOperationAction(ISD::BlockAddress , VT, Custom);
489 }
490
491 // 64-bit shl, sra, srl (iff 32-bit x86)
492 for (auto VT : { MVT::i32, MVT::i64 }) {
493 if (VT == MVT::i64 && !Subtarget.is64Bit())
494 continue;
495 setOperationAction(ISD::SHL_PARTS, VT, Custom);
496 setOperationAction(ISD::SRA_PARTS, VT, Custom);
497 setOperationAction(ISD::SRL_PARTS, VT, Custom);
498 }
499
500 if (Subtarget.hasSSEPrefetch() || Subtarget.has3DNow())
501 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
502
503 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
504
505 // Expand certain atomics
506 for (auto VT : { MVT::i8, MVT::i16, MVT::i32, MVT::i64 }) {
507 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Custom);
508 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
509 setOperationAction(ISD::ATOMIC_LOAD_ADD, VT, Custom);
510 setOperationAction(ISD::ATOMIC_LOAD_OR, VT, Custom);
511 setOperationAction(ISD::ATOMIC_LOAD_XOR, VT, Custom);
512 setOperationAction(ISD::ATOMIC_LOAD_AND, VT, Custom);
513 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
514 }
515
516 if (!Subtarget.is64Bit())
517 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Custom);
518
519 if (Subtarget.hasCmpxchg16b()) {
520 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, MVT::i128, Custom);
521 }
522
523 // FIXME - use subtarget debug flags
524 if (!Subtarget.isTargetDarwin() && !Subtarget.isTargetELF() &&
525 !Subtarget.isTargetCygMing() && !Subtarget.isTargetWin64() &&
526 TM.Options.ExceptionModel != ExceptionHandling::SjLj) {
527 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
528 }
529
530 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
531 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
532
533 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
534 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
535
536 setOperationAction(ISD::TRAP, MVT::Other, Legal);
537 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
538 if (Subtarget.getTargetTriple().isPS4CPU())
539 setOperationAction(ISD::UBSANTRAP, MVT::Other, Expand);
540 else
541 setOperationAction(ISD::UBSANTRAP, MVT::Other, Legal);
542
543 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
544 setOperationAction(ISD::VASTART , MVT::Other, Custom);
545 setOperationAction(ISD::VAEND , MVT::Other, Expand);
546 bool Is64Bit = Subtarget.is64Bit();
547 setOperationAction(ISD::VAARG, MVT::Other, Is64Bit ? Custom : Expand);
548 setOperationAction(ISD::VACOPY, MVT::Other, Is64Bit ? Custom : Expand);
549
550 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
551 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
552
553 setOperationAction(ISD::DYNAMIC_STACKALLOC, PtrVT, Custom);
554
555 // GC_TRANSITION_START and GC_TRANSITION_END need custom lowering.
556 setOperationAction(ISD::GC_TRANSITION_START, MVT::Other, Custom);
557 setOperationAction(ISD::GC_TRANSITION_END, MVT::Other, Custom);
558
559 if (!Subtarget.useSoftFloat() && X86ScalarSSEf64) {
560 // f32 and f64 use SSE.
561 // Set up the FP register classes.
562 addRegisterClass(MVT::f32, Subtarget.hasAVX512() ? &X86::FR32XRegClass
563 : &X86::FR32RegClass);
564 addRegisterClass(MVT::f64, Subtarget.hasAVX512() ? &X86::FR64XRegClass
565 : &X86::FR64RegClass);
566
567 // Disable f32->f64 extload as we can only generate this in one instruction
568 // under optsize. So its easier to pattern match (fpext (load)) for that
569 // case instead of needing to emit 2 instructions for extload in the
570 // non-optsize case.
571 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f32, Expand);
572
573 for (auto VT : { MVT::f32, MVT::f64 }) {
574 // Use ANDPD to simulate FABS.
575 setOperationAction(ISD::FABS, VT, Custom);
576
577 // Use XORP to simulate FNEG.
578 setOperationAction(ISD::FNEG, VT, Custom);
579
580 // Use ANDPD and ORPD to simulate FCOPYSIGN.
581 setOperationAction(ISD::FCOPYSIGN, VT, Custom);
582
583 // These might be better off as horizontal vector ops.
584 setOperationAction(ISD::FADD, VT, Custom);
585 setOperationAction(ISD::FSUB, VT, Custom);
586
587 // We don't support sin/cos/fmod
588 setOperationAction(ISD::FSIN , VT, Expand);
589 setOperationAction(ISD::FCOS , VT, Expand);
590 setOperationAction(ISD::FSINCOS, VT, Expand);
591 }
592
593 // Lower this to MOVMSK plus an AND.
594 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
595 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
596
597 } else if (!Subtarget.useSoftFloat() && X86ScalarSSEf32 &&
598 (UseX87 || Is64Bit)) {
599 // Use SSE for f32, x87 for f64.
600 // Set up the FP register classes.
601 addRegisterClass(MVT::f32, &X86::FR32RegClass);
602 if (UseX87)
603 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
604
605 // Use ANDPS to simulate FABS.
606 setOperationAction(ISD::FABS , MVT::f32, Custom);
607
608 // Use XORP to simulate FNEG.
609 setOperationAction(ISD::FNEG , MVT::f32, Custom);
610
611 if (UseX87)
612 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
613
614 // Use ANDPS and ORPS to simulate FCOPYSIGN.
615 if (UseX87)
616 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
617 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
618
619 // We don't support sin/cos/fmod
620 setOperationAction(ISD::FSIN , MVT::f32, Expand);
621 setOperationAction(ISD::FCOS , MVT::f32, Expand);
622 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
623
624 if (UseX87) {
625 // Always expand sin/cos functions even though x87 has an instruction.
626 setOperationAction(ISD::FSIN, MVT::f64, Expand);
627 setOperationAction(ISD::FCOS, MVT::f64, Expand);
628 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
629 }
630 } else if (UseX87) {
631 // f32 and f64 in x87.
632 // Set up the FP register classes.
633 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
634 addRegisterClass(MVT::f32, &X86::RFP32RegClass);
635
636 for (auto VT : { MVT::f32, MVT::f64 }) {
637 setOperationAction(ISD::UNDEF, VT, Expand);
638 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
639
640 // Always expand sin/cos functions even though x87 has an instruction.
641 setOperationAction(ISD::FSIN , VT, Expand);
642 setOperationAction(ISD::FCOS , VT, Expand);
643 setOperationAction(ISD::FSINCOS, VT, Expand);
644 }
645 }
646
647 // Expand FP32 immediates into loads from the stack, save special cases.
648 if (isTypeLegal(MVT::f32)) {
649 if (UseX87 && (getRegClassFor(MVT::f32) == &X86::RFP32RegClass)) {
650 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
651 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
652 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
653 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
654 } else // SSE immediates.
655 addLegalFPImmediate(APFloat(+0.0f)); // xorps
656 }
657 // Expand FP64 immediates into loads from the stack, save special cases.
658 if (isTypeLegal(MVT::f64)) {
659 if (UseX87 && getRegClassFor(MVT::f64) == &X86::RFP64RegClass) {
660 addLegalFPImmediate(APFloat(+0.0)); // FLD0
661 addLegalFPImmediate(APFloat(+1.0)); // FLD1
662 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
663 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
664 } else // SSE immediates.
665 addLegalFPImmediate(APFloat(+0.0)); // xorpd
666 }
667 // Handle constrained floating-point operations of scalar.
668 setOperationAction(ISD::STRICT_FADD, MVT::f32, Legal);
669 setOperationAction(ISD::STRICT_FADD, MVT::f64, Legal);
670 setOperationAction(ISD::STRICT_FSUB, MVT::f32, Legal);
671 setOperationAction(ISD::STRICT_FSUB, MVT::f64, Legal);
672 setOperationAction(ISD::STRICT_FMUL, MVT::f32, Legal);
673 setOperationAction(ISD::STRICT_FMUL, MVT::f64, Legal);
674 setOperationAction(ISD::STRICT_FDIV, MVT::f32, Legal);
675 setOperationAction(ISD::STRICT_FDIV, MVT::f64, Legal);
676 setOperationAction(ISD::STRICT_FP_EXTEND, MVT::f64, Legal);
677 setOperationAction(ISD::STRICT_FP_ROUND, MVT::f32, Legal);
678 setOperationAction(ISD::STRICT_FP_ROUND, MVT::f64, Legal);
679 setOperationAction(ISD::STRICT_FSQRT, MVT::f32, Legal);
680 setOperationAction(ISD::STRICT_FSQRT, MVT::f64, Legal);
681
682 // We don't support FMA.
683 setOperationAction(ISD::FMA, MVT::f64, Expand);
684 setOperationAction(ISD::FMA, MVT::f32, Expand);
685
686 // f80 always uses X87.
687 if (UseX87) {
688 addRegisterClass(MVT::f80, &X86::RFP80RegClass);
689 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
690 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
691 {
692 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended());
693 addLegalFPImmediate(TmpFlt); // FLD0
694 TmpFlt.changeSign();
695 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
696
697 bool ignored;
698 APFloat TmpFlt2(+1.0);
699 TmpFlt2.convert(APFloat::x87DoubleExtended(), APFloat::rmNearestTiesToEven,
700 &ignored);
701 addLegalFPImmediate(TmpFlt2); // FLD1
702 TmpFlt2.changeSign();
703 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
704 }
705
706 // Always expand sin/cos functions even though x87 has an instruction.
707 setOperationAction(ISD::FSIN , MVT::f80, Expand);
708 setOperationAction(ISD::FCOS , MVT::f80, Expand);
709 setOperationAction(ISD::FSINCOS, MVT::f80, Expand);
710
711 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
712 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
713 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
714 setOperationAction(ISD::FRINT, MVT::f80, Expand);
715 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
716 setOperationAction(ISD::FMA, MVT::f80, Expand);
717 setOperationAction(ISD::LROUND, MVT::f80, Expand);
718 setOperationAction(ISD::LLROUND, MVT::f80, Expand);
719 setOperationAction(ISD::LRINT, MVT::f80, Custom);
720 setOperationAction(ISD::LLRINT, MVT::f80, Custom);
721
722 // Handle constrained floating-point operations of scalar.
723 setOperationAction(ISD::STRICT_FADD , MVT::f80, Legal);
724 setOperationAction(ISD::STRICT_FSUB , MVT::f80, Legal);
725 setOperationAction(ISD::STRICT_FMUL , MVT::f80, Legal);
726 setOperationAction(ISD::STRICT_FDIV , MVT::f80, Legal);
727 setOperationAction(ISD::STRICT_FSQRT , MVT::f80, Legal);
728 setOperationAction(ISD::STRICT_FP_EXTEND, MVT::f80, Legal);
729 // FIXME: When the target is 64-bit, STRICT_FP_ROUND will be overwritten
730 // as Custom.
731 setOperationAction(ISD::STRICT_FP_ROUND, MVT::f80, Legal);
732 }
733
734 // f128 uses xmm registers, but most operations require libcalls.
735 if (!Subtarget.useSoftFloat() && Subtarget.is64Bit() && Subtarget.hasSSE1()) {
736 addRegisterClass(MVT::f128, Subtarget.hasVLX() ? &X86::VR128XRegClass
737 : &X86::VR128RegClass);
738
739 addLegalFPImmediate(APFloat::getZero(APFloat::IEEEquad())); // xorps
740
741 setOperationAction(ISD::FADD, MVT::f128, LibCall);
742 setOperationAction(ISD::STRICT_FADD, MVT::f128, LibCall);
743 setOperationAction(ISD::FSUB, MVT::f128, LibCall);
744 setOperationAction(ISD::STRICT_FSUB, MVT::f128, LibCall);
745 setOperationAction(ISD::FDIV, MVT::f128, LibCall);
746 setOperationAction(ISD::STRICT_FDIV, MVT::f128, LibCall);
747 setOperationAction(ISD::FMUL, MVT::f128, LibCall);
748 setOperationAction(ISD::STRICT_FMUL, MVT::f128, LibCall);
749 setOperationAction(ISD::FMA, MVT::f128, LibCall);
750 setOperationAction(ISD::STRICT_FMA, MVT::f128, LibCall);
751
752 setOperationAction(ISD::FABS, MVT::f128, Custom);
753 setOperationAction(ISD::FNEG, MVT::f128, Custom);
754 setOperationAction(ISD::FCOPYSIGN, MVT::f128, Custom);
755
756 setOperationAction(ISD::FSIN, MVT::f128, LibCall);
757 setOperationAction(ISD::STRICT_FSIN, MVT::f128, LibCall);
758 setOperationAction(ISD::FCOS, MVT::f128, LibCall);
759 setOperationAction(ISD::STRICT_FCOS, MVT::f128, LibCall);
760 setOperationAction(ISD::FSINCOS, MVT::f128, LibCall);
761 // No STRICT_FSINCOS
762 setOperationAction(ISD::FSQRT, MVT::f128, LibCall);
763 setOperationAction(ISD::STRICT_FSQRT, MVT::f128, LibCall);
764
765 setOperationAction(ISD::FP_EXTEND, MVT::f128, Custom);
766 setOperationAction(ISD::STRICT_FP_EXTEND, MVT::f128, Custom);
767 // We need to custom handle any FP_ROUND with an f128 input, but
768 // LegalizeDAG uses the result type to know when to run a custom handler.
769 // So we have to list all legal floating point result types here.
770 if (isTypeLegal(MVT::f32)) {
771 setOperationAction(ISD::FP_ROUND, MVT::f32, Custom);
772 setOperationAction(ISD::STRICT_FP_ROUND, MVT::f32, Custom);
773 }
774 if (isTypeLegal(MVT::f64)) {
775 setOperationAction(ISD::FP_ROUND, MVT::f64, Custom);
776 setOperationAction(ISD::STRICT_FP_ROUND, MVT::f64, Custom);
777 }
778 if (isTypeLegal(MVT::f80)) {
779 setOperationAction(ISD::FP_ROUND, MVT::f80, Custom);
780 setOperationAction(ISD::STRICT_FP_ROUND, MVT::f80, Custom);
781 }
782
783 setOperationAction(ISD::SETCC, MVT::f128, Custom);
784
785 setLoadExtAction(ISD::EXTLOAD, MVT::f128, MVT::f32, Expand);
786 setLoadExtAction(ISD::EXTLOAD, MVT::f128, MVT::f64, Expand);
787 setLoadExtAction(ISD::EXTLOAD, MVT::f128, MVT::f80, Expand);
788 setTruncStoreAction(MVT::f128, MVT::f32, Expand);
789 setTruncStoreAction(MVT::f128, MVT::f64, Expand);
790 setTruncStoreAction(MVT::f128, MVT::f80, Expand);
791 }
792
793 // Always use a library call for pow.
794 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
795 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
796 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
797 setOperationAction(ISD::FPOW , MVT::f128 , Expand);
798
799 setOperationAction(ISD::FLOG, MVT::f80, Expand);
800 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
801 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
802 setOperationAction(ISD::FEXP, MVT::f80, Expand);
803 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
804 setOperationAction(ISD::FMINNUM, MVT::f80, Expand);
805 setOperationAction(ISD::FMAXNUM, MVT::f80, Expand);
806
807 // Some FP actions are always expanded for vector types.
808 for (auto VT : { MVT::v4f32, MVT::v8f32, MVT::v16f32,
809 MVT::v2f64, MVT::v4f64, MVT::v8f64 }) {
810 setOperationAction(ISD::FSIN, VT, Expand);
811 setOperationAction(ISD::FSINCOS, VT, Expand);
812 setOperationAction(ISD::FCOS, VT, Expand);
813 setOperationAction(ISD::FREM, VT, Expand);
814 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
815 setOperationAction(ISD::FPOW, VT, Expand);
816 setOperationAction(ISD::FLOG, VT, Expand);
817 setOperationAction(ISD::FLOG2, VT, Expand);
818 setOperationAction(ISD::FLOG10, VT, Expand);
819 setOperationAction(ISD::FEXP, VT, Expand);
820 setOperationAction(ISD::FEXP2, VT, Expand);
821 }
822
823 // First set operation action for all vector types to either promote
824 // (for widening) or expand (for scalarization). Then we will selectively
825 // turn on ones that can be effectively codegen'd.
826 for (MVT VT : MVT::fixedlen_vector_valuetypes()) {
827 setOperationAction(ISD::SDIV, VT, Expand);
828 setOperationAction(ISD::UDIV, VT, Expand);
829 setOperationAction(ISD::SREM, VT, Expand);
830 setOperationAction(ISD::UREM, VT, Expand);
831 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT,Expand);
832 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
833 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT,Expand);
834 setOperationAction(ISD::INSERT_SUBVECTOR, VT,Expand);
835 setOperationAction(ISD::FMA, VT, Expand);
836 setOperationAction(ISD::FFLOOR, VT, Expand);
837 setOperationAction(ISD::FCEIL, VT, Expand);
838 setOperationAction(ISD::FTRUNC, VT, Expand);
839 setOperationAction(ISD::FRINT, VT, Expand);
840 setOperationAction(ISD::FNEARBYINT, VT, Expand);
841 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
842 setOperationAction(ISD::MULHS, VT, Expand);
843 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
844 setOperationAction(ISD::MULHU, VT, Expand);
845 setOperationAction(ISD::SDIVREM, VT, Expand);
846 setOperationAction(ISD::UDIVREM, VT, Expand);
847 setOperationAction(ISD::CTPOP, VT, Expand);
848 setOperationAction(ISD::CTTZ, VT, Expand);
849 setOperationAction(ISD::CTLZ, VT, Expand);
850 setOperationAction(ISD::ROTL, VT, Expand);
851 setOperationAction(ISD::ROTR, VT, Expand);
852 setOperationAction(ISD::BSWAP, VT, Expand);
853 setOperationAction(ISD::SETCC, VT, Expand);
854 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
855 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
856 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
857 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
858 setOperationAction(ISD::SIGN_EXTEND_INREG, VT,Expand);
859 setOperationAction(ISD::TRUNCATE, VT, Expand);
860 setOperationAction(ISD::SIGN_EXTEND, VT, Expand);
861 setOperationAction(ISD::ZERO_EXTEND, VT, Expand);
862 setOperationAction(ISD::ANY_EXTEND, VT, Expand);
863 setOperationAction(ISD::SELECT_CC, VT, Expand);
864 for (MVT InnerVT : MVT::fixedlen_vector_valuetypes()) {
865 setTruncStoreAction(InnerVT, VT, Expand);
866
867 setLoadExtAction(ISD::SEXTLOAD, InnerVT, VT, Expand);
868 setLoadExtAction(ISD::ZEXTLOAD, InnerVT, VT, Expand);
869
870 // N.b. ISD::EXTLOAD legality is basically ignored except for i1-like
871 // types, we have to deal with them whether we ask for Expansion or not.
872 // Setting Expand causes its own optimisation problems though, so leave
873 // them legal.
874 if (VT.getVectorElementType() == MVT::i1)
875 setLoadExtAction(ISD::EXTLOAD, InnerVT, VT, Expand);
876
877 // EXTLOAD for MVT::f16 vectors is not legal because f16 vectors are
878 // split/scalarized right now.
879 if (VT.getVectorElementType() == MVT::f16)
880 setLoadExtAction(ISD::EXTLOAD, InnerVT, VT, Expand);
881 }
882 }
883
884 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
885 // with -msoft-float, disable use of MMX as well.
886 if (!Subtarget.useSoftFloat() && Subtarget.hasMMX()) {
887 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
888 // No operations on x86mmx supported, everything uses intrinsics.
889 }
890
891 if (!Subtarget.useSoftFloat() && Subtarget.hasSSE1()) {
892 addRegisterClass(MVT::v4f32, Subtarget.hasVLX() ? &X86::VR128XRegClass
893 : &X86::VR128RegClass);
894
895 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
896 setOperationAction(ISD::FABS, MVT::v4f32, Custom);
897 setOperationAction(ISD::FCOPYSIGN, MVT::v4f32, Custom);
898 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
899 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
900 setOperationAction(ISD::VSELECT, MVT::v4f32, Custom);
901 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
902 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
903
904 setOperationAction(ISD::LOAD, MVT::v2f32, Custom);
905 setOperationAction(ISD::STORE, MVT::v2f32, Custom);
906
907 setOperationAction(ISD::STRICT_FADD, MVT::v4f32, Legal);
908 setOperationAction(ISD::STRICT_FSUB, MVT::v4f32, Legal);
909 setOperationAction(ISD::STRICT_FMUL, MVT::v4f32, Legal);
910 setOperationAction(ISD::STRICT_FDIV, MVT::v4f32, Legal);
911 setOperationAction(ISD::STRICT_FSQRT, MVT::v4f32, Legal);
912 }
913
914 if (!Subtarget.useSoftFloat() && Subtarget.hasSSE2()) {
915 addRegisterClass(MVT::v2f64, Subtarget.hasVLX() ? &X86::VR128XRegClass
916 : &X86::VR128RegClass);
917
918 // FIXME: Unfortunately, -soft-float and -no-implicit-float mean XMM
919 // registers cannot be used even for integer operations.
920 addRegisterClass(MVT::v16i8, Subtarget.hasVLX() ? &X86::VR128XRegClass
921 : &X86::VR128RegClass);
922 addRegisterClass(MVT::v8i16, Subtarget.hasVLX() ? &X86::VR128XRegClass
923 : &X86::VR128RegClass);
924 addRegisterClass(MVT::v4i32, Subtarget.hasVLX() ? &X86::VR128XRegClass
925 : &X86::VR128RegClass);
926 addRegisterClass(MVT::v2i64, Subtarget.hasVLX() ? &X86::VR128XRegClass
927 : &X86::VR128RegClass);
928
929 for (auto VT : { MVT::v2i8, MVT::v4i8, MVT::v8i8,
930 MVT::v2i16, MVT::v4i16, MVT::v2i32 }) {
931 setOperationAction(ISD::SDIV, VT, Custom);
932 setOperationAction(ISD::SREM, VT, Custom);
933 setOperationAction(ISD::UDIV, VT, Custom);
934 setOperationAction(ISD::UREM, VT, Custom);
935 }
936
937 setOperationAction(ISD::MUL, MVT::v2i8, Custom);
938 setOperationAction(ISD::MUL, MVT::v4i8, Custom);
939 setOperationAction(ISD::MUL, MVT::v8i8, Custom);
940
941 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
942 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
943 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
944 setOperationAction(ISD::MULHU, MVT::v4i32, Custom);
945 setOperationAction(ISD::MULHS, MVT::v4i32, Custom);
946 setOperationAction(ISD::MULHU, MVT::v16i8, Custom);
947 setOperationAction(ISD::MULHS, MVT::v16i8, Custom);
948 setOperationAction(ISD::MULHU, MVT::v8i16, Legal);
949 setOperationAction(ISD::MULHS, MVT::v8i16, Legal);
950 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
951
952 setOperationAction(ISD::SMULO, MVT::v16i8, Custom);
953 setOperationAction(ISD::UMULO, MVT::v16i8, Custom);
954
955 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
956 setOperationAction(ISD::FABS, MVT::v2f64, Custom);
957 setOperationAction(ISD::FCOPYSIGN, MVT::v2f64, Custom);
958
959 for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64 }) {
960 setOperationAction(ISD::SMAX, VT, VT == MVT::v8i16 ? Legal : Custom);
961 setOperationAction(ISD::SMIN, VT, VT == MVT::v8i16 ? Legal : Custom);
962 setOperationAction(ISD::UMAX, VT, VT == MVT::v16i8 ? Legal : Custom);
963 setOperationAction(ISD::UMIN, VT, VT == MVT::v16i8 ? Legal : Custom);
964 }
965
966 setOperationAction(ISD::UADDSAT, MVT::v16i8, Legal);
967 setOperationAction(ISD::SADDSAT, MVT::v16i8, Legal);
968 setOperationAction(ISD::USUBSAT, MVT::v16i8, Legal);
969 setOperationAction(ISD::SSUBSAT, MVT::v16i8, Legal);
970 setOperationAction(ISD::UADDSAT, MVT::v8i16, Legal);
971 setOperationAction(ISD::SADDSAT, MVT::v8i16, Legal);
972 setOperationAction(ISD::USUBSAT, MVT::v8i16, Legal);
973 setOperationAction(ISD::SSUBSAT, MVT::v8i16, Legal);
974 setOperationAction(ISD::USUBSAT, MVT::v4i32, Custom);
975 setOperationAction(ISD::USUBSAT, MVT::v2i64, Custom);
976
977 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
978 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
979 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
980 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
981
982 for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64 }) {
983 setOperationAction(ISD::SETCC, VT, Custom);
984 setOperationAction(ISD::STRICT_FSETCC, VT, Custom);
985 setOperationAction(ISD::STRICT_FSETCCS, VT, Custom);
986 setOperationAction(ISD::CTPOP, VT, Custom);
987 setOperationAction(ISD::ABS, VT, Custom);
988
989 // The condition codes aren't legal in SSE/AVX and under AVX512 we use
990 // setcc all the way to isel and prefer SETGT in some isel patterns.
991 setCondCodeAction(ISD::SETLT, VT, Custom);
992 setCondCodeAction(ISD::SETLE, VT, Custom);
993 }
994
995 for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32 }) {
996 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
997 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
998 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
999 setOperationAction(ISD::VSELECT, VT, Custom);
1000 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1001 }
1002
1003 for (auto VT : { MVT::v2f64, MVT::v2i64 }) {
1004 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1005 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1006 setOperationAction(ISD::VSELECT, VT, Custom);
1007
1008 if (VT == MVT::v2i64 && !Subtarget.is64Bit())
1009 continue;
1010
1011 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1012 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1013 }
1014
1015 // Custom lower v2i64 and v2f64 selects.
1016 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
1017 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
1018 setOperationAction(ISD::SELECT, MVT::v4i32, Custom);
1019 setOperationAction(ISD::SELECT, MVT::v8i16, Custom);
1020 setOperationAction(ISD::SELECT, MVT::v16i8, Custom);
1021
1022 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
1023 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Custom);
1024 setOperationAction(ISD::FP_TO_SINT, MVT::v2i32, Custom);
1025 setOperationAction(ISD::FP_TO_UINT, MVT::v2i32, Custom);
1026 setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::v4i32, Legal);
1027 setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::v2i32, Custom);
1028
1029 // Custom legalize these to avoid over promotion or custom promotion.
1030 for (auto VT : {MVT::v2i8, MVT::v4i8, MVT::v8i8, MVT::v2i16, MVT::v4i16}) {
1031 setOperationAction(ISD::FP_TO_SINT, VT, Custom);
1032 setOperationAction(ISD::FP_TO_UINT, VT, Custom);
1033 setOperationAction(ISD::STRICT_FP_TO_SINT, VT, Custom);
1034 setOperationAction(ISD::STRICT_FP_TO_UINT, VT, Custom);
1035 }
1036
1037 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
1038 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::v4i32, Legal);
1039 setOperationAction(ISD::SINT_TO_FP, MVT::v2i32, Custom);
1040 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::v2i32, Custom);
1041
1042 setOperationAction(ISD::UINT_TO_FP, MVT::v2i32, Custom);
1043 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::v2i32, Custom);
1044
1045 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Custom);
1046 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::v4i32, Custom);
1047
1048 // Fast v2f32 UINT_TO_FP( v2i32 ) custom conversion.
1049 setOperationAction(ISD::SINT_TO_FP, MVT::v2f32, Custom);
1050 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::v2f32, Custom);
1051 setOperationAction(ISD::UINT_TO_FP, MVT::v2f32, Custom);
1052 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::v2f32, Custom);
1053
1054 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
1055 setOperationAction(ISD::STRICT_FP_EXTEND, MVT::v2f32, Custom);
1056 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Custom);
1057 setOperationAction(ISD::STRICT_FP_ROUND, MVT::v2f32, Custom);
1058
1059 // We want to legalize this to an f64 load rather than an i64 load on
1060 // 64-bit targets and two 32-bit loads on a 32-bit target. Similar for
1061 // store.
1062 setOperationAction(ISD::LOAD, MVT::v2i32, Custom);
1063 setOperationAction(ISD::LOAD, MVT::v4i16, Custom);
1064 setOperationAction(ISD::LOAD, MVT::v8i8, Custom);
1065 setOperationAction(ISD::STORE, MVT::v2i32, Custom);
1066 setOperationAction(ISD::STORE, MVT::v4i16, Custom);
1067 setOperationAction(ISD::STORE, MVT::v8i8, Custom);
1068
1069 setOperationAction(ISD::BITCAST, MVT::v2i32, Custom);
1070 setOperationAction(ISD::BITCAST, MVT::v4i16, Custom);
1071 setOperationAction(ISD::BITCAST, MVT::v8i8, Custom);
1072 if (!Subtarget.hasAVX512())
1073 setOperationAction(ISD::BITCAST, MVT::v16i1, Custom);
1074
1075 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v2i64, Custom);
1076 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v4i32, Custom);
1077 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v8i16, Custom);
1078
1079 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i64, Custom);
1080
1081 setOperationAction(ISD::TRUNCATE, MVT::v2i8, Custom);
1082 setOperationAction(ISD::TRUNCATE, MVT::v2i16, Custom);
1083 setOperationAction(ISD::TRUNCATE, MVT::v2i32, Custom);
1084 setOperationAction(ISD::TRUNCATE, MVT::v4i8, Custom);
1085 setOperationAction(ISD::TRUNCATE, MVT::v4i16, Custom);
1086 setOperationAction(ISD::TRUNCATE, MVT::v8i8, Custom);
1087
1088 // In the customized shift lowering, the legal v4i32/v2i64 cases
1089 // in AVX2 will be recognized.
1090 for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64 }) {
1091 setOperationAction(ISD::SRL, VT, Custom);
1092 setOperationAction(ISD::SHL, VT, Custom);
1093 setOperationAction(ISD::SRA, VT, Custom);
1094 }
1095
1096 setOperationAction(ISD::ROTL, MVT::v4i32, Custom);
1097 setOperationAction(ISD::ROTL, MVT::v8i16, Custom);
1098
1099 // With 512-bit registers or AVX512VL+BW, expanding (and promoting the
1100 // shifts) is better.
1101 if (!Subtarget.useAVX512Regs() &&
1102 !(Subtarget.hasBWI() && Subtarget.hasVLX()))
1103 setOperationAction(ISD::ROTL, MVT::v16i8, Custom);
1104
1105 setOperationAction(ISD::STRICT_FSQRT, MVT::v2f64, Legal);
1106 setOperationAction(ISD::STRICT_FADD, MVT::v2f64, Legal);
1107 setOperationAction(ISD::STRICT_FSUB, MVT::v2f64, Legal);
1108 setOperationAction(ISD::STRICT_FMUL, MVT::v2f64, Legal);
1109 setOperationAction(ISD::STRICT_FDIV, MVT::v2f64, Legal);
1110 }
1111
1112 if (!Subtarget.useSoftFloat() && Subtarget.hasSSSE3()) {
1113 setOperationAction(ISD::ABS, MVT::v16i8, Legal);
1114 setOperationAction(ISD::ABS, MVT::v8i16, Legal);
1115 setOperationAction(ISD::ABS, MVT::v4i32, Legal);
1116 setOperationAction(ISD::BITREVERSE, MVT::v16i8, Custom);
1117 setOperationAction(ISD::CTLZ, MVT::v16i8, Custom);
1118 setOperationAction(ISD::CTLZ, MVT::v8i16, Custom);
1119 setOperationAction(ISD::CTLZ, MVT::v4i32, Custom);
1120 setOperationAction(ISD::CTLZ, MVT::v2i64, Custom);
1121
1122 // These might be better off as horizontal vector ops.
1123 setOperationAction(ISD::ADD, MVT::i16, Custom);
1124 setOperationAction(ISD::ADD, MVT::i32, Custom);
1125 setOperationAction(ISD::SUB, MVT::i16, Custom);
1126 setOperationAction(ISD::SUB, MVT::i32, Custom);
1127 }
1128
1129 if (!Subtarget.useSoftFloat() && Subtarget.hasSSE41()) {
1130 for (MVT RoundedTy : {MVT::f32, MVT::f64, MVT::v4f32, MVT::v2f64}) {
1131 setOperationAction(ISD::FFLOOR, RoundedTy, Legal);
1132 setOperationAction(ISD::STRICT_FFLOOR, RoundedTy, Legal);
1133 setOperationAction(ISD::FCEIL, RoundedTy, Legal);
1134 setOperationAction(ISD::STRICT_FCEIL, RoundedTy, Legal);
1135 setOperationAction(ISD::FTRUNC, RoundedTy, Legal);
1136 setOperationAction(ISD::STRICT_FTRUNC, RoundedTy, Legal);
1137 setOperationAction(ISD::FRINT, RoundedTy, Legal);
1138 setOperationAction(ISD::STRICT_FRINT, RoundedTy, Legal);
1139 setOperationAction(ISD::FNEARBYINT, RoundedTy, Legal);
1140 setOperationAction(ISD::STRICT_FNEARBYINT, RoundedTy, Legal);
1141 setOperationAction(ISD::FROUNDEVEN, RoundedTy, Legal);
1142 setOperationAction(ISD::STRICT_FROUNDEVEN, RoundedTy, Legal);
1143
1144 setOperationAction(ISD::FROUND, RoundedTy, Custom);
1145 }
1146
1147 setOperationAction(ISD::SMAX, MVT::v16i8, Legal);
1148 setOperationAction(ISD::SMAX, MVT::v4i32, Legal);
1149 setOperationAction(ISD::UMAX, MVT::v8i16, Legal);
1150 setOperationAction(ISD::UMAX, MVT::v4i32, Legal);
1151 setOperationAction(ISD::SMIN, MVT::v16i8, Legal);
1152 setOperationAction(ISD::SMIN, MVT::v4i32, Legal);
1153 setOperationAction(ISD::UMIN, MVT::v8i16, Legal);
1154 setOperationAction(ISD::UMIN, MVT::v4i32, Legal);
1155
1156 setOperationAction(ISD::UADDSAT, MVT::v4i32, Custom);
1157 setOperationAction(ISD::SADDSAT, MVT::v2i64, Custom);
1158 setOperationAction(ISD::SSUBSAT, MVT::v2i64, Custom);
1159
1160 // FIXME: Do we need to handle scalar-to-vector here?
1161 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
1162
1163 // We directly match byte blends in the backend as they match the VSELECT
1164 // condition form.
1165 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
1166
1167 // SSE41 brings specific instructions for doing vector sign extend even in
1168 // cases where we don't have SRA.
1169 for (auto VT : { MVT::v8i16, MVT::v4i32, MVT::v2i64 }) {
1170 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, VT, Legal);
1171 setOperationAction(ISD::ZERO_EXTEND_VECTOR_INREG, VT, Legal);
1172 }
1173
1174 // SSE41 also has vector sign/zero extending loads, PMOV[SZ]X
1175 for (auto LoadExtOp : { ISD::SEXTLOAD, ISD::ZEXTLOAD }) {
1176 setLoadExtAction(LoadExtOp, MVT::v8i16, MVT::v8i8, Legal);
1177 setLoadExtAction(LoadExtOp, MVT::v4i32, MVT::v4i8, Legal);
1178 setLoadExtAction(LoadExtOp, MVT::v2i64, MVT::v2i8, Legal);
1179 setLoadExtAction(LoadExtOp, MVT::v4i32, MVT::v4i16, Legal);
1180 setLoadExtAction(LoadExtOp, MVT::v2i64, MVT::v2i16, Legal);
1181 setLoadExtAction(LoadExtOp, MVT::v2i64, MVT::v2i32, Legal);
1182 }
1183
1184 if (Subtarget.is64Bit() && !Subtarget.hasAVX512()) {
1185 // We need to scalarize v4i64->v432 uint_to_fp using cvtsi2ss, but we can
1186 // do the pre and post work in the vector domain.
1187 setOperationAction(ISD::UINT_TO_FP, MVT::v4i64, Custom);
1188 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::v4i64, Custom);
1189 // We need to mark SINT_TO_FP as Custom even though we want to expand it
1190 // so that DAG combine doesn't try to turn it into uint_to_fp.
1191 setOperationAction(ISD::SINT_TO_FP, MVT::v4i64, Custom);
1192 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::v4i64, Custom);
1193 }
1194 }
1195
1196 if (!Subtarget.useSoftFloat() && Subtarget.hasSSE42()) {
1197 setOperationAction(ISD::UADDSAT, MVT::v2i64, Custom);
1198 }
1199
1200 if (!Subtarget.useSoftFloat() && Subtarget.hasXOP()) {
1201 for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64,
1202 MVT::v32i8, MVT::v16i16, MVT::v8i32, MVT::v4i64 })
1203 setOperationAction(ISD::ROTL, VT, Custom);
1204
1205 // XOP can efficiently perform BITREVERSE with VPPERM.
1206 for (auto VT : { MVT::i8, MVT::i16, MVT::i32, MVT::i64 })
1207 setOperationAction(ISD::BITREVERSE, VT, Custom);
1208
1209 for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64,
1210 MVT::v32i8, MVT::v16i16, MVT::v8i32, MVT::v4i64 })
1211 setOperationAction(ISD::BITREVERSE, VT, Custom);
1212 }
1213
1214 if (!Subtarget.useSoftFloat() && Subtarget.hasAVX()) {
1215 bool HasInt256 = Subtarget.hasInt256();
1216
1217 addRegisterClass(MVT::v32i8, Subtarget.hasVLX() ? &X86::VR256XRegClass
1218 : &X86::VR256RegClass);
1219 addRegisterClass(MVT::v16i16, Subtarget.hasVLX() ? &X86::VR256XRegClass
1220 : &X86::VR256RegClass);
1221 addRegisterClass(MVT::v8i32, Subtarget.hasVLX() ? &X86::VR256XRegClass
1222 : &X86::VR256RegClass);
1223 addRegisterClass(MVT::v8f32, Subtarget.hasVLX() ? &X86::VR256XRegClass
1224 : &X86::VR256RegClass);
1225 addRegisterClass(MVT::v4i64, Subtarget.hasVLX() ? &X86::VR256XRegClass
1226 : &X86::VR256RegClass);
1227 addRegisterClass(MVT::v4f64, Subtarget.hasVLX() ? &X86::VR256XRegClass
1228 : &X86::VR256RegClass);
1229
1230 for (auto VT : { MVT::v8f32, MVT::v4f64 }) {
1231 setOperationAction(ISD::FFLOOR, VT, Legal);
1232 setOperationAction(ISD::STRICT_FFLOOR, VT, Legal);
1233 setOperationAction(ISD::FCEIL, VT, Legal);
1234 setOperationAction(ISD::STRICT_FCEIL, VT, Legal);
1235 setOperationAction(ISD::FTRUNC, VT, Legal);
1236 setOperationAction(ISD::STRICT_FTRUNC, VT, Legal);
1237 setOperationAction(ISD::FRINT, VT, Legal);
1238 setOperationAction(ISD::STRICT_FRINT, VT, Legal);
1239 setOperationAction(ISD::FNEARBYINT, VT, Legal);
1240 setOperationAction(ISD::STRICT_FNEARBYINT, VT, Legal);
1241 setOperationAction(ISD::FROUNDEVEN, VT, Legal);
1242 setOperationAction(ISD::STRICT_FROUNDEVEN, VT, Legal);
1243
1244 setOperationAction(ISD::FROUND, VT, Custom);
1245
1246 setOperationAction(ISD::FNEG, VT, Custom);
1247 setOperationAction(ISD::FABS, VT, Custom);
1248 setOperationAction(ISD::FCOPYSIGN, VT, Custom);
1249 }
1250
1251 // (fp_to_int:v8i16 (v8f32 ..)) requires the result type to be promoted
1252 // even though v8i16 is a legal type.
1253 setOperationPromotedToType(ISD::FP_TO_SINT, MVT::v8i16, MVT::v8i32);
1254 setOperationPromotedToType(ISD::FP_TO_UINT, MVT::v8i16, MVT::v8i32);
1255 setOperationPromotedToType(ISD::STRICT_FP_TO_SINT, MVT::v8i16, MVT::v8i32);
1256 setOperationPromotedToType(ISD::STRICT_FP_TO_UINT, MVT::v8i16, MVT::v8i32);
1257 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1258 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Custom);
1259 setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::v8i32, Legal);
1260
1261 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1262 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::v8i32, Legal);
1263
1264 setOperationAction(ISD::STRICT_FP_ROUND, MVT::v4f32, Legal);
1265 setOperationAction(ISD::STRICT_FADD, MVT::v8f32, Legal);
1266 setOperationAction(ISD::STRICT_FADD, MVT::v4f64, Legal);
1267 setOperationAction(ISD::STRICT_FSUB, MVT::v8f32, Legal);
1268 setOperationAction(ISD::STRICT_FSUB, MVT::v4f64, Legal);
1269 setOperationAction(ISD::STRICT_FMUL, MVT::v8f32, Legal);
1270 setOperationAction(ISD::STRICT_FMUL, MVT::v4f64, Legal);
1271 setOperationAction(ISD::STRICT_FDIV, MVT::v8f32, Legal);
1272 setOperationAction(ISD::STRICT_FDIV, MVT::v4f64, Legal);
1273 setOperationAction(ISD::STRICT_FP_EXTEND, MVT::v4f64, Legal);
1274 setOperationAction(ISD::STRICT_FSQRT, MVT::v8f32, Legal);
1275 setOperationAction(ISD::STRICT_FSQRT, MVT::v4f64, Legal);
1276
1277 if (!Subtarget.hasAVX512())
1278 setOperationAction(ISD::BITCAST, MVT::v32i1, Custom);
1279
1280 // In the customized shift lowering, the legal v8i32/v4i64 cases
1281 // in AVX2 will be recognized.
1282 for (auto VT : { MVT::v32i8, MVT::v16i16, MVT::v8i32, MVT::v4i64 }) {
1283 setOperationAction(ISD::SRL, VT, Custom);
1284 setOperationAction(ISD::SHL, VT, Custom);
1285 setOperationAction(ISD::SRA, VT, Custom);
1286 }
1287
1288 // These types need custom splitting if their input is a 128-bit vector.
1289 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i64, Custom);
1290 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom);
1291 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i64, Custom);
1292 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i32, Custom);
1293
1294 setOperationAction(ISD::ROTL, MVT::v8i32, Custom);
1295 setOperationAction(ISD::ROTL, MVT::v16i16, Custom);
1296
1297 // With BWI, expanding (and promoting the shifts) is the better.
1298 if (!Subtarget.useBWIRegs())
1299 setOperationAction(ISD::ROTL, MVT::v32i8, Custom);
1300
1301 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1302 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1303 setOperationAction(ISD::SELECT, MVT::v8i32, Custom);
1304 setOperationAction(ISD::SELECT, MVT::v16i16, Custom);
1305 setOperationAction(ISD::SELECT, MVT::v32i8, Custom);
1306 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1307
1308 for (auto VT : { MVT::v16i16, MVT::v8i32, MVT::v4i64 }) {
1309 setOperationAction(ISD::SIGN_EXTEND, VT, Custom);
1310 setOperationAction(ISD::ZERO_EXTEND, VT, Custom);
1311 setOperationAction(ISD::ANY_EXTEND, VT, Custom);
1312 }
1313
1314 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1315 setOperationAction(ISD::TRUNCATE, MVT::v8i16, Custom);
1316 setOperationAction(ISD::TRUNCATE, MVT::v4i32, Custom);
1317 setOperationAction(ISD::BITREVERSE, MVT::v32i8, Custom);
1318
1319 for (auto VT : { MVT::v32i8, MVT::v16i16, MVT::v8i32, MVT::v4i64 }) {
1320 setOperationAction(ISD::SETCC, VT, Custom);
1321 setOperationAction(ISD::STRICT_FSETCC, VT, Custom);
1322 setOperationAction(ISD::STRICT_FSETCCS, VT, Custom);
1323 setOperationAction(ISD::CTPOP, VT, Custom);
1324 setOperationAction(ISD::CTLZ, VT, Custom);
1325
1326 // The condition codes aren't legal in SSE/AVX and under AVX512 we use
1327 // setcc all the way to isel and prefer SETGT in some isel patterns.
1328 setCondCodeAction(ISD::SETLT, VT, Custom);
1329 setCondCodeAction(ISD::SETLE, VT, Custom);
1330 }
1331
1332 if (Subtarget.hasAnyFMA()) {
1333 for (auto VT : { MVT::f32, MVT::f64, MVT::v4f32, MVT::v8f32,
1334 MVT::v2f64, MVT::v4f64 }) {
1335 setOperationAction(ISD::FMA, VT, Legal);
1336 setOperationAction(ISD::STRICT_FMA, VT, Legal);
1337 }
1338 }
1339
1340 for (auto VT : { MVT::v32i8, MVT::v16i16, MVT::v8i32, MVT::v4i64 }) {
1341 setOperationAction(ISD::ADD, VT, HasInt256 ? Legal : Custom);
1342 setOperationAction(ISD::SUB, VT, HasInt256 ? Legal : Custom);
1343 }
1344
1345 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1346 setOperationAction(ISD::MUL, MVT::v8i32, HasInt256 ? Legal : Custom);
1347 setOperationAction(ISD::MUL, MVT::v16i16, HasInt256 ? Legal : Custom);
1348 setOperationAction(ISD::MUL, MVT::v32i8, Custom);
1349
1350 setOperationAction(ISD::MULHU, MVT::v8i32, Custom);
1351 setOperationAction(ISD::MULHS, MVT::v8i32, Custom);
1352 setOperationAction(ISD::MULHU, MVT::v16i16, HasInt256 ? Legal : Custom);
1353 setOperationAction(ISD::MULHS, MVT::v16i16, HasInt256 ? Legal : Custom);
1354 setOperationAction(ISD::MULHU, MVT::v32i8, Custom);
1355 setOperationAction(ISD::MULHS, MVT::v32i8, Custom);
1356
1357 setOperationAction(ISD::SMULO, MVT::v32i8, Custom);
1358 setOperationAction(ISD::UMULO, MVT::v32i8, Custom);
1359
1360 setOperationAction(ISD::ABS, MVT::v4i64, Custom);
1361 setOperationAction(ISD::SMAX, MVT::v4i64, Custom);
1362 setOperationAction(ISD::UMAX, MVT::v4i64, Custom);
1363 setOperationAction(ISD::SMIN, MVT::v4i64, Custom);
1364 setOperationAction(ISD::UMIN, MVT::v4i64, Custom);
1365
1366 setOperationAction(ISD::UADDSAT, MVT::v32i8, HasInt256 ? Legal : Custom);
1367 setOperationAction(ISD::SADDSAT, MVT::v32i8, HasInt256 ? Legal : Custom);
1368 setOperationAction(ISD::USUBSAT, MVT::v32i8, HasInt256 ? Legal : Custom);
1369 setOperationAction(ISD::SSUBSAT, MVT::v32i8, HasInt256 ? Legal : Custom);
1370 setOperationAction(ISD::UADDSAT, MVT::v16i16, HasInt256 ? Legal : Custom);
1371 setOperationAction(ISD::SADDSAT, MVT::v16i16, HasInt256 ? Legal : Custom);
1372 setOperationAction(ISD::USUBSAT, MVT::v16i16, HasInt256 ? Legal : Custom);
1373 setOperationAction(ISD::SSUBSAT, MVT::v16i16, HasInt256 ? Legal : Custom);
1374 setOperationAction(ISD::UADDSAT, MVT::v8i32, Custom);
1375 setOperationAction(ISD::USUBSAT, MVT::v8i32, Custom);
1376 setOperationAction(ISD::UADDSAT, MVT::v4i64, Custom);
1377 setOperationAction(ISD::USUBSAT, MVT::v4i64, Custom);
1378
1379 for (auto VT : { MVT::v32i8, MVT::v16i16, MVT::v8i32 }) {
1380 setOperationAction(ISD::ABS, VT, HasInt256 ? Legal : Custom);
1381 setOperationAction(ISD::SMAX, VT, HasInt256 ? Legal : Custom);
1382 setOperationAction(ISD::UMAX, VT, HasInt256 ? Legal : Custom);
1383 setOperationAction(ISD::SMIN, VT, HasInt256 ? Legal : Custom);
1384 setOperationAction(ISD::UMIN, VT, HasInt256 ? Legal : Custom);
1385 }
1386
1387 for (auto VT : {MVT::v16i16, MVT::v8i32, MVT::v4i64}) {
1388 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, VT, Custom);
1389 setOperationAction(ISD::ZERO_EXTEND_VECTOR_INREG, VT, Custom);
1390 }
1391
1392 if (HasInt256) {
1393 // The custom lowering for UINT_TO_FP for v8i32 becomes interesting
1394 // when we have a 256bit-wide blend with immediate.
1395 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Custom);
1396 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::v8i32, Custom);
1397
1398 // AVX2 also has wider vector sign/zero extending loads, VPMOV[SZ]X
1399 for (auto LoadExtOp : { ISD::SEXTLOAD, ISD::ZEXTLOAD }) {
1400 setLoadExtAction(LoadExtOp, MVT::v16i16, MVT::v16i8, Legal);
1401 setLoadExtAction(LoadExtOp, MVT::v8i32, MVT::v8i8, Legal);
1402 setLoadExtAction(LoadExtOp, MVT::v4i64, MVT::v4i8, Legal);
1403 setLoadExtAction(LoadExtOp, MVT::v8i32, MVT::v8i16, Legal);
1404 setLoadExtAction(LoadExtOp, MVT::v4i64, MVT::v4i16, Legal);
1405 setLoadExtAction(LoadExtOp, MVT::v4i64, MVT::v4i32, Legal);
1406 }
1407 }
1408
1409 for (auto VT : { MVT::v4i32, MVT::v8i32, MVT::v2i64, MVT::v4i64,
1410 MVT::v4f32, MVT::v8f32, MVT::v2f64, MVT::v4f64 }) {
1411 setOperationAction(ISD::MLOAD, VT, Subtarget.hasVLX() ? Legal : Custom);
1412 setOperationAction(ISD::MSTORE, VT, Legal);
1413 }
1414
1415 // Extract subvector is special because the value type
1416 // (result) is 128-bit but the source is 256-bit wide.
1417 for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64,
1418 MVT::v4f32, MVT::v2f64 }) {
1419 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
1420 }
1421
1422 // Custom lower several nodes for 256-bit types.
1423 for (MVT VT : { MVT::v32i8, MVT::v16i16, MVT::v8i32, MVT::v4i64,
1424 MVT::v8f32, MVT::v4f64 }) {
1425 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1426 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1427 setOperationAction(ISD::VSELECT, VT, Custom);
1428 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1429 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1430 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1431 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Legal);
1432 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1433 setOperationAction(ISD::STORE, VT, Custom);
1434 }
1435
1436 if (HasInt256) {
1437 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1438
1439 // Custom legalize 2x32 to get a little better code.
1440 setOperationAction(ISD::MGATHER, MVT::v2f32, Custom);
1441 setOperationAction(ISD::MGATHER, MVT::v2i32, Custom);
1442
1443 for (auto VT : { MVT::v4i32, MVT::v8i32, MVT::v2i64, MVT::v4i64,
1444 MVT::v4f32, MVT::v8f32, MVT::v2f64, MVT::v4f64 })
1445 setOperationAction(ISD::MGATHER, VT, Custom);
1446 }
1447 }
1448
1449 // This block controls legalization of the mask vector sizes that are
1450 // available with AVX512. 512-bit vectors are in a separate block controlled
1451 // by useAVX512Regs.
1452 if (!Subtarget.useSoftFloat() && Subtarget.hasAVX512()) {
1453 addRegisterClass(MVT::v1i1, &X86::VK1RegClass);
1454 addRegisterClass(MVT::v2i1, &X86::VK2RegClass);
1455 addRegisterClass(MVT::v4i1, &X86::VK4RegClass);
1456 addRegisterClass(MVT::v8i1, &X86::VK8RegClass);
1457 addRegisterClass(MVT::v16i1, &X86::VK16RegClass);
1458
1459 setOperationAction(ISD::SELECT, MVT::v1i1, Custom);
1460 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v1i1, Custom);
1461 setOperationAction(ISD::BUILD_VECTOR, MVT::v1i1, Custom);
1462
1463 setOperationPromotedToType(ISD::FP_TO_SINT, MVT::v8i1, MVT::v8i32);
1464 setOperationPromotedToType(ISD::FP_TO_UINT, MVT::v8i1, MVT::v8i32);
1465 setOperationPromotedToType(ISD::FP_TO_SINT, MVT::v4i1, MVT::v4i32);
1466 setOperationPromotedToType(ISD::FP_TO_UINT, MVT::v4i1, MVT::v4i32);
1467 setOperationPromotedToType(ISD::STRICT_FP_TO_SINT, MVT::v8i1, MVT::v8i32);
1468 setOperationPromotedToType(ISD::STRICT_FP_TO_UINT, MVT::v8i1, MVT::v8i32);
1469 setOperationPromotedToType(ISD::STRICT_FP_TO_SINT, MVT::v4i1, MVT::v4i32);
1470 setOperationPromotedToType(ISD::STRICT_FP_TO_UINT, MVT::v4i1, MVT::v4i32);
1471 setOperationAction(ISD::FP_TO_SINT, MVT::v2i1, Custom);
1472 setOperationAction(ISD::FP_TO_UINT, MVT::v2i1, Custom);
1473 setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::v2i1, Custom);
1474 setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::v2i1, Custom);
1475
1476 // There is no byte sized k-register load or store without AVX512DQ.
1477 if (!Subtarget.hasDQI()) {
1478 setOperationAction(ISD::LOAD, MVT::v1i1, Custom);
1479 setOperationAction(ISD::LOAD, MVT::v2i1, Custom);
1480 setOperationAction(ISD::LOAD, MVT::v4i1, Custom);
1481 setOperationAction(ISD::LOAD, MVT::v8i1, Custom);
1482
1483 setOperationAction(ISD::STORE, MVT::v1i1, Custom);
1484 setOperationAction(ISD::STORE, MVT::v2i1, Custom);
1485 setOperationAction(ISD::STORE, MVT::v4i1, Custom);
1486 setOperationAction(ISD::STORE, MVT::v8i1, Custom);
1487 }
1488
1489 // Extends of v16i1/v8i1/v4i1/v2i1 to 128-bit vectors.
1490 for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64 }) {
1491 setOperationAction(ISD::SIGN_EXTEND, VT, Custom);
1492 setOperationAction(ISD::ZERO_EXTEND, VT, Custom);
1493 setOperationAction(ISD::ANY_EXTEND, VT, Custom);
1494 }
1495
1496 for (auto VT : { MVT::v1i1, MVT::v2i1, MVT::v4i1, MVT::v8i1, MVT::v16i1 })
1497 setOperationAction(ISD::VSELECT, VT, Expand);
1498
1499 for (auto VT : { MVT::v2i1, MVT::v4i1, MVT::v8i1, MVT::v16i1 }) {
1500 setOperationAction(ISD::SETCC, VT, Custom);
1501 setOperationAction(ISD::STRICT_FSETCC, VT, Custom);
1502 setOperationAction(ISD::STRICT_FSETCCS, VT, Custom);
1503 setOperationAction(ISD::SELECT, VT, Custom);
1504 setOperationAction(ISD::TRUNCATE, VT, Custom);
1505
1506 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1507 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1508 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1509 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1510 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1511 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1512 }
1513
1514 for (auto VT : { MVT::v1i1, MVT::v2i1, MVT::v4i1, MVT::v8i1 })
1515 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1516 }
1517
1518 // This block controls legalization for 512-bit operations with 32/64 bit
1519 // elements. 512-bits can be disabled based on prefer-vector-width and
1520 // required-vector-width function attributes.
1521 if (!Subtarget.useSoftFloat() && Subtarget.useAVX512Regs()) {
1522 bool HasBWI = Subtarget.hasBWI();
1523
1524 addRegisterClass(MVT::v16i32, &X86::VR512RegClass);
1525 addRegisterClass(MVT::v16f32, &X86::VR512RegClass);
1526 addRegisterClass(MVT::v8i64, &X86::VR512RegClass);
1527 addRegisterClass(MVT::v8f64, &X86::VR512RegClass);
1528 addRegisterClass(MVT::v32i16, &X86::VR512RegClass);
1529 addRegisterClass(MVT::v64i8, &X86::VR512RegClass);
1530
1531 for (auto ExtType : {ISD::ZEXTLOAD, ISD::SEXTLOAD}) {
1532 setLoadExtAction(ExtType, MVT::v16i32, MVT::v16i8, Legal);
1533 setLoadExtAction(ExtType, MVT::v16i32, MVT::v16i16, Legal);
1534 setLoadExtAction(ExtType, MVT::v8i64, MVT::v8i8, Legal);
1535 setLoadExtAction(ExtType, MVT::v8i64, MVT::v8i16, Legal);
1536 setLoadExtAction(ExtType, MVT::v8i64, MVT::v8i32, Legal);
1537 if (HasBWI)
1538 setLoadExtAction(ExtType, MVT::v32i16, MVT::v32i8, Legal);
1539 }
1540
1541 for (MVT VT : { MVT::v16f32, MVT::v8f64 }) {
1542 setOperationAction(ISD::FNEG, VT, Custom);
1543 setOperationAction(ISD::FABS, VT, Custom);
1544 setOperationAction(ISD::FMA, VT, Legal);
1545 setOperationAction(ISD::STRICT_FMA, VT, Legal);
1546 setOperationAction(ISD::FCOPYSIGN, VT, Custom);
1547 }
1548
1549 for (MVT VT : { MVT::v16i1, MVT::v16i8, MVT::v16i16 }) {
1550 setOperationPromotedToType(ISD::FP_TO_SINT , VT, MVT::v16i32);
1551 setOperationPromotedToType(ISD::FP_TO_UINT , VT, MVT::v16i32);
1552 setOperationPromotedToType(ISD::STRICT_FP_TO_SINT, VT, MVT::v16i32);
1553 setOperationPromotedToType(ISD::STRICT_FP_TO_UINT, VT, MVT::v16i32);
1554 }
1555 setOperationAction(ISD::FP_TO_SINT, MVT::v16i32, Legal);
1556 setOperationAction(ISD::FP_TO_UINT, MVT::v16i32, Legal);
1557 setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::v16i32, Legal);
1558 setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::v16i32, Legal);
1559 setOperationAction(ISD::SINT_TO_FP, MVT::v16i32, Legal);
1560 setOperationAction(ISD::UINT_TO_FP, MVT::v16i32, Legal);
1561 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::v16i32, Legal);
1562 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::v16i32, Legal);
1563
1564 setOperationAction(ISD::STRICT_FADD, MVT::v16f32, Legal);
1565 setOperationAction(ISD::STRICT_FADD, MVT::v8f64, Legal);
1566 setOperationAction(ISD::STRICT_FSUB, MVT::v16f32, Legal);
1567 setOperationAction(ISD::STRICT_FSUB, MVT::v8f64, Legal);
1568 setOperationAction(ISD::STRICT_FMUL, MVT::v16f32, Legal);
1569 setOperationAction(ISD::STRICT_FMUL, MVT::v8f64, Legal);
1570 setOperationAction(ISD::STRICT_FDIV, MVT::v16f32, Legal);
1571 setOperationAction(ISD::STRICT_FDIV, MVT::v8f64, Legal);
1572 setOperationAction(ISD::STRICT_FSQRT, MVT::v16f32, Legal);
1573 setOperationAction(ISD::STRICT_FSQRT, MVT::v8f64, Legal);
1574 setOperationAction(ISD::STRICT_FP_EXTEND, MVT::v8f64, Legal);
1575 setOperationAction(ISD::STRICT_FP_ROUND, MVT::v8f32, Legal);
1576
1577 setTruncStoreAction(MVT::v8i64, MVT::v8i8, Legal);
1578 setTruncStoreAction(MVT::v8i64, MVT::v8i16, Legal);
1579 setTruncStoreAction(MVT::v8i64, MVT::v8i32, Legal);
1580 setTruncStoreAction(MVT::v16i32, MVT::v16i8, Legal);
1581 setTruncStoreAction(MVT::v16i32, MVT::v16i16, Legal);
1582 if (HasBWI)
1583 setTruncStoreAction(MVT::v32i16, MVT::v32i8, Legal);
1584
1585 // With 512-bit vectors and no VLX, we prefer to widen MLOAD/MSTORE
1586 // to 512-bit rather than use the AVX2 instructions so that we can use
1587 // k-masks.
1588 if (!Subtarget.hasVLX()) {
1589 for (auto VT : {MVT::v4i32, MVT::v8i32, MVT::v2i64, MVT::v4i64,
1590 MVT::v4f32, MVT::v8f32, MVT::v2f64, MVT::v4f64}) {
1591 setOperationAction(ISD::MLOAD, VT, Custom);
1592 setOperationAction(ISD::MSTORE, VT, Custom);
1593 }
1594 }
1595
1596 setOperationAction(ISD::TRUNCATE, MVT::v8i32, Legal);
1597 setOperationAction(ISD::TRUNCATE, MVT::v16i16, Legal);
1598 setOperationAction(ISD::TRUNCATE, MVT::v32i8, HasBWI ? Legal : Custom);
1599 setOperationAction(ISD::TRUNCATE, MVT::v16i64, Custom);
1600 setOperationAction(ISD::ZERO_EXTEND, MVT::v32i16, Custom);
1601 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i32, Custom);
1602 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i64, Custom);
1603 setOperationAction(ISD::ANY_EXTEND, MVT::v32i16, Custom);
1604 setOperationAction(ISD::ANY_EXTEND, MVT::v16i32, Custom);
1605 setOperationAction(ISD::ANY_EXTEND, MVT::v8i64, Custom);
1606 setOperationAction(ISD::SIGN_EXTEND, MVT::v32i16, Custom);
1607 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom);
1608 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i64, Custom);
1609
1610 if (HasBWI) {
1611 // Extends from v64i1 masks to 512-bit vectors.
1612 setOperationAction(ISD::SIGN_EXTEND, MVT::v64i8, Custom);
1613 setOperationAction(ISD::ZERO_EXTEND, MVT::v64i8, Custom);
1614 setOperationAction(ISD::ANY_EXTEND, MVT::v64i8, Custom);
1615 }
1616
1617 for (auto VT : { MVT::v16f32, MVT::v8f64 }) {
1618 setOperationAction(ISD::FFLOOR, VT, Legal);
1619 setOperationAction(ISD::STRICT_FFLOOR, VT, Legal);
1620 setOperationAction(ISD::FCEIL, VT, Legal);
1621 setOperationAction(ISD::STRICT_FCEIL, VT, Legal);
1622 setOperationAction(ISD::FTRUNC, VT, Legal);
1623 setOperationAction(ISD::STRICT_FTRUNC, VT, Legal);
1624 setOperationAction(ISD::FRINT, VT, Legal);
1625 setOperationAction(ISD::STRICT_FRINT, VT, Legal);
1626 setOperationAction(ISD::FNEARBYINT, VT, Legal);
1627 setOperationAction(ISD::STRICT_FNEARBYINT, VT, Legal);
1628 setOperationAction(ISD::FROUNDEVEN, VT, Legal);
1629 setOperationAction(ISD::STRICT_FROUNDEVEN, VT, Legal);
1630
1631 setOperationAction(ISD::FROUND, VT, Custom);
1632 }
1633
1634 for (auto VT : {MVT::v32i16, MVT::v16i32, MVT::v8i64}) {
1635 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, VT, Custom);
1636 setOperationAction(ISD::ZERO_EXTEND_VECTOR_INREG, VT, Custom);
1637 }
1638
1639 setOperationAction(ISD::ADD, MVT::v32i16, HasBWI ? Legal : Custom);
1640 setOperationAction(ISD::SUB, MVT::v32i16, HasBWI ? Legal : Custom);
1641 setOperationAction(ISD::ADD, MVT::v64i8, HasBWI ? Legal : Custom);
1642 setOperationAction(ISD::SUB, MVT::v64i8, HasBWI ? Legal : Custom);
1643
1644 setOperationAction(ISD::MUL, MVT::v8i64, Custom);
1645 setOperationAction(ISD::MUL, MVT::v16i32, Legal);
1646 setOperationAction(ISD::MUL, MVT::v32i16, HasBWI ? Legal : Custom);
1647 setOperationAction(ISD::MUL, MVT::v64i8, Custom);
1648
1649 setOperationAction(ISD::MULHU, MVT::v16i32, Custom);
1650 setOperationAction(ISD::MULHS, MVT::v16i32, Custom);
1651 setOperationAction(ISD::MULHS, MVT::v32i16, HasBWI ? Legal : Custom);
1652 setOperationAction(ISD::MULHU, MVT::v32i16, HasBWI ? Legal : Custom);
1653 setOperationAction(ISD::MULHS, MVT::v64i8, Custom);
1654 setOperationAction(ISD::MULHU, MVT::v64i8, Custom);
1655
1656 setOperationAction(ISD::SMULO, MVT::v64i8, Custom);
1657 setOperationAction(ISD::UMULO, MVT::v64i8, Custom);
1658
1659 setOperationAction(ISD::BITREVERSE, MVT::v64i8, Custom);
1660
1661 for (auto VT : { MVT::v64i8, MVT::v32i16, MVT::v16i32, MVT::v8i64 }) {
1662 setOperationAction(ISD::SRL, VT, Custom);
1663 setOperationAction(ISD::SHL, VT, Custom);
1664 setOperationAction(ISD::SRA, VT, Custom);
1665 setOperationAction(ISD::SETCC, VT, Custom);
1666
1667 // The condition codes aren't legal in SSE/AVX and under AVX512 we use
1668 // setcc all the way to isel and prefer SETGT in some isel patterns.
1669 setCondCodeAction(ISD::SETLT, VT, Custom);
1670 setCondCodeAction(ISD::SETLE, VT, Custom);
1671 }
1672 for (auto VT : { MVT::v16i32, MVT::v8i64 }) {
1673 setOperationAction(ISD::SMAX, VT, Legal);
1674 setOperationAction(ISD::UMAX, VT, Legal);
1675 setOperationAction(ISD::SMIN, VT, Legal);
1676 setOperationAction(ISD::UMIN, VT, Legal);
1677 setOperationAction(ISD::ABS, VT, Legal);
1678 setOperationAction(ISD::CTPOP, VT, Custom);
1679 setOperationAction(ISD::ROTL, VT, Custom);
1680 setOperationAction(ISD::ROTR, VT, Custom);
1681 setOperationAction(ISD::STRICT_FSETCC, VT, Custom);
1682 setOperationAction(ISD::STRICT_FSETCCS, VT, Custom);
1683 }
1684
1685 for (auto VT : { MVT::v64i8, MVT::v32i16 }) {
1686 setOperationAction(ISD::ABS, VT, HasBWI ? Legal : Custom);
1687 setOperationAction(ISD::CTPOP, VT, Subtarget.hasBITALG() ? Legal : Custom);
1688 setOperationAction(ISD::CTLZ, VT, Custom);
1689 setOperationAction(ISD::SMAX, VT, HasBWI ? Legal : Custom);
1690 setOperationAction(ISD::UMAX, VT, HasBWI ? Legal : Custom);
1691 setOperationAction(ISD::SMIN, VT, HasBWI ? Legal : Custom);
1692 setOperationAction(ISD::UMIN, VT, HasBWI ? Legal : Custom);
1693 setOperationAction(ISD::UADDSAT, VT, HasBWI ? Legal : Custom);
1694 setOperationAction(ISD::SADDSAT, VT, HasBWI ? Legal : Custom);
1695 setOperationAction(ISD::USUBSAT, VT, HasBWI ? Legal : Custom);
1696 setOperationAction(ISD::SSUBSAT, VT, HasBWI ? Legal : Custom);
1697 }
1698
1699 if (Subtarget.hasDQI()) {
1700 setOperationAction(ISD::SINT_TO_FP, MVT::v8i64, Legal);
1701 setOperationAction(ISD::UINT_TO_FP, MVT::v8i64, Legal);
1702 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::v8i64, Legal);
1703 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::v8i64, Legal);
1704 setOperationAction(ISD::FP_TO_SINT, MVT::v8i64, Legal);
1705 setOperationAction(ISD::FP_TO_UINT, MVT::v8i64, Legal);
1706 setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::v8i64, Legal);
1707 setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::v8i64, Legal);
1708
1709 setOperationAction(ISD::MUL, MVT::v8i64, Legal);
1710 }
1711
1712 if (Subtarget.hasCDI()) {
1713 // NonVLX sub-targets extend 128/256 vectors to use the 512 version.
1714 for (auto VT : { MVT::v16i32, MVT::v8i64} ) {
1715 setOperationAction(ISD::CTLZ, VT, Legal);
1716 }
1717 } // Subtarget.hasCDI()
1718
1719 if (Subtarget.hasVPOPCNTDQ()) {
1720 for (auto VT : { MVT::v16i32, MVT::v8i64 })
1721 setOperationAction(ISD::CTPOP, VT, Legal);
1722 }
1723
1724 // Extract subvector is special because the value type
1725 // (result) is 256-bit but the source is 512-bit wide.
1726 // 128-bit was made Legal under AVX1.
1727 for (auto VT : { MVT::v32i8, MVT::v16i16, MVT::v8i32, MVT::v4i64,
1728 MVT::v8f32, MVT::v4f64 })
1729 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
1730
1731 for (auto VT : { MVT::v64i8, MVT::v32i16, MVT::v16i32, MVT::v8i64,
1732 MVT::v16f32, MVT::v8f64 }) {
1733 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1734 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Legal);
1735 setOperationAction(ISD::SELECT, VT, Custom);
1736 setOperationAction(ISD::VSELECT, VT, Custom);
1737 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1738 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1739 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1740 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1741 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1742 }
1743
1744 for (auto VT : { MVT::v16i32, MVT::v8i64, MVT::v16f32, MVT::v8f64 }) {
1745 setOperationAction(ISD::MLOAD, VT, Legal);
1746 setOperationAction(ISD::MSTORE, VT, Legal);
1747 setOperationAction(ISD::MGATHER, VT, Custom);
1748 setOperationAction(ISD::MSCATTER, VT, Custom);
1749 }
1750 if (HasBWI) {
1751 for (auto VT : { MVT::v64i8, MVT::v32i16 }) {
1752 setOperationAction(ISD::MLOAD, VT, Legal);
1753 setOperationAction(ISD::MSTORE, VT, Legal);
1754 }
1755 } else {
1756 setOperationAction(ISD::STORE, MVT::v32i16, Custom);
1757 setOperationAction(ISD::STORE, MVT::v64i8, Custom);
1758 }
1759
1760 if (Subtarget.hasVBMI2()) {
1761 for (auto VT : { MVT::v8i16, MVT::v4i32, MVT::v2i64,
1762 MVT::v16i16, MVT::v8i32, MVT::v4i64,
1763 MVT::v32i16, MVT::v16i32, MVT::v8i64 }) {
1764 setOperationAction(ISD::FSHL, VT, Custom);
1765 setOperationAction(ISD::FSHR, VT, Custom);
1766 }
1767
1768 setOperationAction(ISD::ROTL, MVT::v32i16, Custom);
1769 setOperationAction(ISD::ROTR, MVT::v8i16, Custom);
1770 setOperationAction(ISD::ROTR, MVT::v16i16, Custom);
1771 setOperationAction(ISD::ROTR, MVT::v32i16, Custom);
1772 }
1773 }// useAVX512Regs
1774
1775 // This block controls legalization for operations that don't have
1776 // pre-AVX512 equivalents. Without VLX we use 512-bit operations for
1777 // narrower widths.
1778 if (!Subtarget.useSoftFloat() && Subtarget.hasAVX512()) {
1779 // These operations are handled on non-VLX by artificially widening in
1780 // isel patterns.
1781
1782 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32,
1783 Subtarget.hasVLX() ? Legal : Custom);
1784 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32,
1785 Subtarget.hasVLX() ? Legal : Custom);
1786 setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::v8i32,
1787 Subtarget.hasVLX() ? Legal : Custom);
1788 setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::v4i32,
1789 Subtarget.hasVLX() ? Legal : Custom);
1790 setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::v2i32, Custom);
1791 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32,
1792 Subtarget.hasVLX() ? Legal : Custom);
1793 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32,
1794 Subtarget.hasVLX() ? Legal : Custom);
1795 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::v8i32,
1796 Subtarget.hasVLX() ? Legal : Custom);
1797 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::v4i32,
1798 Subtarget.hasVLX() ? Legal : Custom);
1799
1800 if (Subtarget.hasDQI()) {
1801 // Fast v2f32 SINT_TO_FP( v2i64 ) custom conversion.
1802 // v2f32 UINT_TO_FP is already custom under SSE2.
1803 assert(isOperationCustom(ISD::UINT_TO_FP, MVT::v2f32) &&(static_cast <bool> (isOperationCustom(ISD::UINT_TO_FP,
MVT::v2f32) && isOperationCustom(ISD::STRICT_UINT_TO_FP
, MVT::v2f32) && "Unexpected operation action!") ? void
(0) : __assert_fail ("isOperationCustom(ISD::UINT_TO_FP, MVT::v2f32) && isOperationCustom(ISD::STRICT_UINT_TO_FP, MVT::v2f32) && \"Unexpected operation action!\""
, "/build/llvm-toolchain-snapshot-14~++20211016100712+8e1d532707fd/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 1805, __extension__ __PRETTY_FUNCTION__))
1804 isOperationCustom(ISD::STRICT_UINT_TO_FP, MVT::v2f32) &&(static_cast <bool> (isOperationCustom(ISD::UINT_TO_FP,
MVT::v2f32) && isOperationCustom(ISD::STRICT_UINT_TO_FP
, MVT::v2f32) && "Unexpected operation action!") ? void
(0) : __assert_fail ("isOperationCustom(ISD::UINT_TO_FP, MVT::v2f32) && isOperationCustom(ISD::STRICT_UINT_TO_FP, MVT::v2f32) && \"Unexpected operation action!\""
, "/build/llvm-toolchain-snapshot-14~++20211016100712+8e1d532707fd/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 1805, __extension__ __PRETTY_FUNCTION__))
1805 "Unexpected operation action!")(static_cast <bool> (isOperationCustom(ISD::UINT_TO_FP,
MVT::v2f32) && isOperationCustom(ISD::STRICT_UINT_TO_FP
, MVT::v2f32) && "Unexpected operation action!") ? void
(0) : __assert_fail ("isOperationCustom(ISD::UINT_TO_FP, MVT::v2f32) && isOperationCustom(ISD::STRICT_UINT_TO_FP, MVT::v2f32) && \"Unexpected operation action!\""
, "/build/llvm-toolchain-snapshot-14~++20211016100712+8e1d532707fd/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 1805, __extension__ __PRETTY_FUNCTION__))
;
1806 // v2i64 FP_TO_S/UINT(v2f32) custom conversion.
1807 setOperationAction(ISD::FP_TO_SINT, MVT::v2f32, Custom);
1808 setOperationAction(ISD::FP_TO_UINT, MVT::v2f32, Custom);
1809 setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::v2f32, Custom);
1810 setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::v2f32, Custom);
1811 }
1812
1813 for (auto VT : { MVT::v2i64, MVT::v4i64 }) {
1814 setOperationAction(ISD::SMAX, VT, Legal);
1815 setOperationAction(ISD::UMAX, VT, Legal);
1816 setOperationAction(ISD::SMIN, VT, Legal);
1817 setOperationAction(ISD::UMIN, VT, Legal);
1818 setOperationAction(ISD::ABS, VT, Legal);
1819 }
1820
1821 for (auto VT : { MVT::v4i32, MVT::v8i32, MVT::v2i64, MVT::v4i64 }) {
1822 setOperationAction(ISD::ROTL, VT, Custom);
1823 setOperationAction(ISD::ROTR, VT, Custom);
1824 }
1825
1826 // Custom legalize 2x32 to get a little better code.
1827 setOperationAction(ISD::MSCATTER, MVT::v2f32, Custom);
1828 setOperationAction(ISD::MSCATTER, MVT::v2i32, Custom);
1829
1830 for (auto VT : { MVT::v4i32, MVT::v8i32, MVT::v2i64, MVT::v4i64,
1831 MVT::v4f32, MVT::v8f32, MVT::v2f64, MVT::v4f64 })
1832 setOperationAction(ISD::MSCATTER, VT, Custom);
1833
1834 if (Subtarget.hasDQI()) {
1835 for (auto VT : { MVT::v2i64, MVT::v4i64 }) {
1836 setOperationAction(ISD::SINT_TO_FP, VT,
1837 Subtarget.hasVLX() ? Legal : Custom);
1838 setOperationAction(ISD::UINT_TO_FP, VT,
1839 Subtarget.hasVLX() ? Legal : Custom);
1840 setOperationAction(ISD::STRICT_SINT_TO_FP, VT,
1841 Subtarget.hasVLX() ? Legal : Custom);
1842 setOperationAction(ISD::STRICT_UINT_TO_FP, VT,
1843 Subtarget.hasVLX() ? Legal : Custom);
1844 setOperationAction(ISD::FP_TO_SINT, VT,
1845 Subtarget.hasVLX() ? Legal : Custom);
1846 setOperationAction(ISD::FP_TO_UINT, VT,
1847 Subtarget.hasVLX() ? Legal : Custom);
1848 setOperationAction(ISD::STRICT_FP_TO_SINT, VT,
1849 Subtarget.hasVLX() ? Legal : Custom);
1850 setOperationAction(ISD::STRICT_FP_TO_UINT, VT,
1851 Subtarget.hasVLX() ? Legal : Custom);
1852 setOperationAction(ISD::MUL, VT, Legal);
1853 }
1854 }
1855
1856 if (Subtarget.hasCDI()) {
1857 for (auto VT : { MVT::v4i32, MVT::v8i32, MVT::v2i64, MVT::v4i64 }) {
1858 setOperationAction(ISD::CTLZ, VT, Legal);
1859 }
1860 } // Subtarget.hasCDI()
1861
1862 if (Subtarget.hasVPOPCNTDQ()) {
1863 for (auto VT : { MVT::v4i32, MVT::v8i32, MVT::v2i64, MVT::v4i64 })
1864 setOperationAction(ISD::CTPOP, VT, Legal);
1865 }
1866 }
1867
1868 // This block control legalization of v32i1/v64i1 which are available with
1869 // AVX512BW. 512-bit v32i16 and v64i8 vector legalization is controlled with
1870 // useBWIRegs.
1871 if (!Subtarget.useSoftFloat() && Subtarget.hasBWI()) {
1872 addRegisterClass(MVT::v32i1, &X86::VK32RegClass);
1873 addRegisterClass(MVT::v64i1, &X86::VK64RegClass);
1874
1875 for (auto VT : { MVT::v32i1, MVT::v64i1 }) {
1876 setOperationAction(ISD::VSELECT, VT, Expand);
1877 setOperationAction(ISD::TRUNCATE, VT, Custom);
1878 setOperationAction(ISD::SETCC, VT, Custom);
1879 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1880 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1881 setOperationAction(ISD::SELECT, VT, Custom);
1882 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1883 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1884 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1885 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1886 }
1887
1888 for (auto VT : { MVT::v16i1, MVT::v32i1 })
1889 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1890
1891 // Extends from v32i1 masks to 256-bit vectors.
1892 setOperationAction(ISD::SIGN_EXTEND, MVT::v32i8, Custom);
1893 setOperationAction(ISD::ZERO_EXTEND, MVT::v32i8, Custom);
1894 setOperationAction(ISD::ANY_EXTEND, MVT::v32i8, Custom);
1895
1896 for (auto VT : { MVT::v32i8, MVT::v16i8, MVT::v16i16, MVT::v8i16 }) {
1897 setOperationAction(ISD::MLOAD, VT, Subtarget.hasVLX() ? Legal : Custom);
1898 setOperationAction(ISD::MSTORE, VT, Subtarget.hasVLX() ? Legal : Custom);
1899 }
1900
1901 // These operations are handled on non-VLX by artificially widening in
1902 // isel patterns.
1903 // TODO: Custom widen in lowering on non-VLX and drop the isel patterns?
1904
1905 if (Subtarget.hasBITALG()) {
1906 for (auto VT : { MVT::v16i8, MVT::v32i8, MVT::v8i16, MVT::v16i16 })
1907 setOperationAction(ISD::CTPOP, VT, Legal);
1908 }
1909 }
1910
1911 if (!Subtarget.useSoftFloat() && Subtarget.hasFP16()) {
1912 auto setGroup = [&] (MVT VT) {
1913 setOperationAction(ISD::FADD, VT, Legal);
1914 setOperationAction(ISD::STRICT_FADD, VT, Legal);
1915 setOperationAction(ISD::FSUB, VT, Legal);
1916 setOperationAction(ISD::STRICT_FSUB, VT, Legal);
1917 setOperationAction(ISD::FMUL, VT, Legal);
1918 setOperationAction(ISD::STRICT_FMUL, VT, Legal);
1919 setOperationAction(ISD::FDIV, VT, Legal);
1920 setOperationAction(ISD::STRICT_FDIV, VT, Legal);
1921 setOperationAction(ISD::FSQRT, VT, Legal);
1922 setOperationAction(ISD::STRICT_FSQRT, VT, Legal);
1923
1924 setOperationAction(ISD::FFLOOR, VT, Legal);
1925 setOperationAction(ISD::STRICT_FFLOOR, VT, Legal);
1926 setOperationAction(ISD::FCEIL, VT, Legal);
1927 setOperationAction(ISD::STRICT_FCEIL, VT, Legal);
1928 setOperationAction(ISD::FTRUNC, VT, Legal);
1929 setOperationAction(ISD::STRICT_FTRUNC, VT, Legal);
1930 setOperationAction(ISD::FRINT, VT, Legal);
1931 setOperationAction(ISD::STRICT_FRINT, VT, Legal);
1932 setOperationAction(ISD::FNEARBYINT, VT, Legal);
1933 setOperationAction(ISD::STRICT_FNEARBYINT, VT, Legal);
1934
1935 setOperationAction(ISD::LOAD, VT, Legal);
1936 setOperationAction(ISD::STORE, VT, Legal);
1937
1938 setOperationAction(ISD::FMA, VT, Legal);
1939 setOperationAction(ISD::STRICT_FMA, VT, Legal);
1940 setOperationAction(ISD::VSELECT, VT, Legal);
1941 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1942 setOperationAction(ISD::SELECT, VT, Custom);
1943
1944 setOperationAction(ISD::FNEG, VT, Custom);
1945 setOperationAction(ISD::FABS, VT, Custom);
1946 setOperationAction(ISD::FCOPYSIGN, VT, Custom);
1947 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1948 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1949 };
1950
1951 // AVX512_FP16 scalar operations
1952 setGroup(MVT::f16);
1953 addRegisterClass(MVT::f16, &X86::FR16XRegClass);
1954 setOperationAction(ISD::SELECT_CC, MVT::f16, Expand);
1955 setOperationAction(ISD::BR_CC, MVT::f16, Expand);
1956 setOperationAction(ISD::SETCC, MVT::f16, Custom);
1957 setOperationAction(ISD::STRICT_FSETCC, MVT::f16, Custom);
1958 setOperationAction(ISD::STRICT_FSETCCS, MVT::f16, Custom);
1959 setOperationAction(ISD::FROUND, MVT::f16, Custom);
1960 setOperationAction(ISD::STRICT_FROUND, MVT::f16, Custom);
1961 setOperationAction(ISD::FROUNDEVEN, MVT::f16, Legal);
1962 setOperationAction(ISD::STRICT_FROUNDEVEN, MVT::f16, Legal);
1963 setOperationAction(ISD::FP_ROUND, MVT::f16, Custom);
1964 setOperationAction(ISD::STRICT_FP_ROUND, MVT::f16, Custom);
1965 setOperationAction(ISD::STRICT_FP_EXTEND, MVT::f32, Legal);
1966 if (isTypeLegal(MVT::f80)) {
1967 setOperationAction(ISD::FP_EXTEND, MVT::f80, Custom);
1968 setOperationAction(ISD::STRICT_FP_EXTEND, MVT::f80, Custom);
1969 }
1970
1971 setCondCodeAction(ISD::SETOEQ, MVT::f16, Expand);
1972 setCondCodeAction(ISD::SETUNE, MVT::f16, Expand);
1973
1974 if (Subtarget.useAVX512Regs()) {
1975 setGroup(MVT::v32f16);
1976 addRegisterClass(MVT::v32f16, &X86::VR512RegClass);
1977 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v32f16, Custom);
1978 setOperationAction(ISD::SINT_TO_FP, MVT::v32i16, Legal);
1979 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::v32i16, Legal);
1980 setOperationAction(ISD::UINT_TO_FP, MVT::v32i16, Legal);
1981 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::v32i16, Legal);
1982 setOperationAction(ISD::STRICT_FP_ROUND, MVT::v16f16, Legal);
1983 setOperationAction(ISD::STRICT_FP_EXTEND, MVT::v16f32, Legal);
1984 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v32f16, Custom);
1985
1986 setOperationAction(ISD::FP_TO_SINT, MVT::v32i16, Custom);
1987 setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::v32i16, Custom);
1988 setOperationAction(ISD::FP_TO_UINT, MVT::v32i16, Custom);
1989 setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::v32i16, Custom);
1990 setOperationPromotedToType(ISD::FP_TO_SINT, MVT::v32i8, MVT::v32i16);
1991 setOperationPromotedToType(ISD::STRICT_FP_TO_SINT, MVT::v32i8,
1992 MVT::v32i16);
1993 setOperationPromotedToType(ISD::FP_TO_UINT, MVT::v32i8, MVT::v32i16);
1994 setOperationPromotedToType(ISD::STRICT_FP_TO_UINT, MVT::v32i8,
1995 MVT::v32i16);
1996 setOperationPromotedToType(ISD::FP_TO_SINT, MVT::v32i1, MVT::v32i16);
1997 setOperationPromotedToType(ISD::STRICT_FP_TO_SINT, MVT::v32i1,
1998 MVT::v32i16);
1999 setOperationPromotedToType(ISD::FP_TO_UINT, MVT::v32i1, MVT::v32i16);
2000 setOperationPromotedToType(ISD::STRICT_FP_TO_UINT, MVT::v32i1,
2001 MVT::v32i16);
2002
2003 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v16f16, Legal);
2004 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v32f16, Legal);
2005 setOperationAction(ISD::CONCAT_VECTORS, MVT::v32f16, Custom);
2006
2007 setLoadExtAction(ISD::EXTLOAD, MVT::v8f64, MVT::v8f16, Legal);
2008 setLoadExtAction(ISD::EXTLOAD, MVT::v16f32, MVT::v16f16, Legal);
2009
2010 setOperationAction(ISD::STRICT_FSETCC, MVT::v32i1, Custom);
2011 setOperationAction(ISD::STRICT_FSETCCS, MVT::v32i1, Custom);
2012 }
2013
2014 if (Subtarget.hasVLX()) {
2015 addRegisterClass(MVT::v8f16, &X86::VR128XRegClass);
2016 addRegisterClass(MVT::v16f16, &X86::VR256XRegClass);
2017 setGroup(MVT::v8f16);
2018 setGroup(MVT::v16f16);
2019
2020 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8f16, Legal);
2021 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16f16, Custom);
2022 setOperationAction(ISD::SINT_TO_FP, MVT::v16i16, Legal);
2023 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::v16i16, Legal);
2024 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Legal);
2025 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::v8i16, Legal);
2026 setOperationAction(ISD::UINT_TO_FP, MVT::v16i16, Legal);
2027 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::v16i16, Legal);
2028 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Legal);
2029 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::v8i16, Legal);
2030
2031 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Custom);
2032 setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::v8i16, Custom);
2033 setOperationAction(ISD::FP_TO_UINT, MVT::v8i16, Custom);
2034 setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::v8i16, Custom);
2035 setOperationAction(ISD::STRICT_FP_ROUND, MVT::v8f16, Legal);
2036 setOperationAction(ISD::STRICT_FP_EXTEND, MVT::v8f32, Legal);
2037
2038 // INSERT_VECTOR_ELT v8f16 extended to VECTOR_SHUFFLE
2039 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8f16, Custom);
2040 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16f16, Custom);
2041
2042 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v8f16, Legal);
2043 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v16f16, Legal);
2044 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16f16, Custom);
2045
2046 setLoadExtAction(ISD::EXTLOAD, MVT::v4f64, MVT::v4f16, Legal);
2047 setLoadExtAction(ISD::EXTLOAD, MVT::v2f64, MVT::v2f16, Legal);
2048 setLoadExtAction(ISD::EXTLOAD, MVT::v8f32, MVT::v8f16, Legal);
2049 setLoadExtAction(ISD::EXTLOAD, MVT::v4f32, MVT::v4f16, Legal);
2050
2051 // Need to custom widen these to prevent scalarization.
2052 setOperationAction(ISD::LOAD, MVT::v4f16, Custom);
2053 setOperationAction(ISD::STORE, MVT::v4f16, Custom);
2054 }
2055
2056 // Support fp16 0 immediate
2057 addLegalFPImmediate(APFloat::getZero(APFloat::IEEEhalf()));
2058 }
2059
2060 if (!Subtarget.useSoftFloat() && Subtarget.hasVLX()) {
2061 setTruncStoreAction(MVT::v4i64, MVT::v4i8, Legal);
2062 setTruncStoreAction(MVT::v4i64, MVT::v4i16, Legal);
2063 setTruncStoreAction(MVT::v4i64, MVT::v4i32, Legal);
2064 setTruncStoreAction(MVT::v8i32, MVT::v8i8, Legal);
2065 setTruncStoreAction(MVT::v8i32, MVT::v8i16, Legal);
2066
2067 setTruncStoreAction(MVT::v2i64, MVT::v2i8, Legal);
2068 setTruncStoreAction(MVT::v2i64, MVT::v2i16, Legal);
2069 setTruncStoreAction(MVT::v2i64, MVT::v2i32, Legal);
2070 setTruncStoreAction(MVT::v4i32, MVT::v4i8, Legal);
2071 setTruncStoreAction(MVT::v4i32, MVT::v4i16, Legal);
2072
2073 if (Subtarget.hasBWI()) {
2074 setTruncStoreAction(MVT::v16i16, MVT::v16i8, Legal);
2075 setTruncStoreAction(MVT::v8i16, MVT::v8i8, Legal);
2076 }
2077
2078 if (Subtarget.hasFP16()) {
2079 // vcvttph2[u]dq v4f16 -> v4i32/64, v2f16 -> v2i32/64
2080 setOperationAction(ISD::FP_TO_SINT, MVT::v2f16, Custom);
2081 setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::v2f16, Custom);
2082 setOperationAction(ISD::FP_TO_UINT, MVT::v2f16, Custom);
2083 setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::v2f16, Custom);
2084 setOperationAction(ISD::FP_TO_SINT, MVT::v4f16, Custom);
2085 setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::v4f16, Custom);
2086 setOperationAction(ISD::FP_TO_UINT, MVT::v4f16, Custom);
2087 setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::v4f16, Custom);
2088 // vcvt[u]dq2ph v4i32/64 -> v4f16, v2i32/64 -> v2f16
2089 setOperationAction(ISD::SINT_TO_FP, MVT::v2f16, Custom);
2090 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::v2f16, Custom);
2091 setOperationAction(ISD::UINT_TO_FP, MVT::v2f16, Custom);
2092 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::v2f16, Custom);
2093 setOperationAction(ISD::SINT_TO_FP, MVT::v4f16, Custom);
2094 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::v4f16, Custom);
2095 setOperationAction(ISD::UINT_TO_FP, MVT::v4f16, Custom);
2096 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::v4f16, Custom);
2097 // vcvtps2phx v4f32 -> v4f16, v2f32 -> v2f16
2098 setOperationAction(ISD::FP_ROUND, MVT::v2f16, Custom);
2099 setOperationAction(ISD::STRICT_FP_ROUND, MVT::v2f16, Custom);
2100 setOperationAction(ISD::FP_ROUND, MVT::v4f16, Custom);
2101 setOperationAction(ISD::STRICT_FP_ROUND, MVT::v4f16, Custom);
2102 // vcvtph2psx v4f16 -> v4f32, v2f16 -> v2f32
2103 setOperationAction(ISD::FP_EXTEND, MVT::v2f16, Custom);
2104 setOperationAction(ISD::STRICT_FP_EXTEND, MVT::v2f16, Custom);
2105 setOperationAction(ISD::FP_EXTEND, MVT::v4f16, Custom);
2106 setOperationAction(ISD::STRICT_FP_EXTEND, MVT::v4f16, Custom);
2107 }
2108
2109 setOperationAction(ISD::TRUNCATE, MVT::v16i32, Custom);
2110 setOperationAction(ISD::TRUNCATE, MVT::v8i64, Custom);
2111 setOperationAction(ISD::TRUNCATE, MVT::v16i64, Custom);
2112 }
2113
2114 if (Subtarget.hasAMXTILE()) {
2115 addRegisterClass(MVT::x86amx, &X86::TILERegClass);
2116 }
2117
2118 // We want to custom lower some of our intrinsics.
2119 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
2120 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
2121 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
2122 if (!Subtarget.is64Bit()) {
2123 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom);
2124 }
2125
2126 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
2127 // handle type legalization for these operations here.
2128 //
2129 // FIXME: We really should do custom legalization for addition and
2130 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
2131 // than generic legalization for 64-bit multiplication-with-overflow, though.
2132 for (auto VT : { MVT::i8, MVT::i16, MVT::i32, MVT::i64 }) {
2133 if (VT == MVT::i64 && !Subtarget.is64Bit())
2134 continue;
2135 // Add/Sub/Mul with overflow operations are custom lowered.
2136 setOperationAction(ISD::SADDO, VT, Custom);
2137 setOperationAction(ISD::UADDO, VT, Custom);
2138 setOperationAction(ISD::SSUBO, VT, Custom);
2139 setOperationAction(ISD::USUBO, VT, Custom);
2140 setOperationAction(ISD::SMULO, VT, Custom);
2141 setOperationAction(ISD::UMULO, VT, Custom);
2142
2143 // Support carry in as value rather than glue.
2144 setOperationAction(ISD::ADDCARRY, VT, Custom);
2145 setOperationAction(ISD::SUBCARRY, VT, Custom);
2146 setOperationAction(ISD::SETCCCARRY, VT, Custom);
2147 setOperationAction(ISD::SADDO_CARRY, VT, Custom);
2148 setOperationAction(ISD::SSUBO_CARRY, VT, Custom);
2149 }
2150
2151 if (!Subtarget.is64Bit()) {
2152 // These libcalls are not available in 32-bit.
2153 setLibcallName(RTLIB::SHL_I128, nullptr);
2154 setLibcallName(RTLIB::SRL_I128, nullptr);
2155 setLibcallName(RTLIB::SRA_I128, nullptr);
2156 setLibcallName(RTLIB::MUL_I128, nullptr);
2157 // The MULO libcall is not part of libgcc, only compiler-rt.
2158 setLibcallName(RTLIB::MULO_I64, nullptr);
2159 }
2160 // The MULO libcall is not part of libgcc, only compiler-rt.
2161 setLibcallName(RTLIB::MULO_I128, nullptr);
2162
2163 // Combine sin / cos into _sincos_stret if it is available.
2164 if (getLibcallName(RTLIB::SINCOS_STRET_F32) != nullptr &&
2165 getLibcallName(RTLIB::SINCOS_STRET_F64) != nullptr) {
2166 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
2167 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
2168 }
2169
2170 if (Subtarget.isTargetWin64()) {
2171 setOperationAction(ISD::SDIV, MVT::i128, Custom);
2172 setOperationAction(ISD::UDIV, MVT::i128, Custom);
2173 setOperationAction(ISD::SREM, MVT::i128, Custom);
2174 setOperationAction(ISD::UREM, MVT::i128, Custom);
2175 setOperationAction(ISD::FP_TO_SINT, MVT::i128, Custom);
2176 setOperationAction(ISD::FP_TO_UINT, MVT::i128, Custom);
2177 setOperationAction(ISD::SINT_TO_FP, MVT::i128, Custom);
2178 setOperationAction(ISD::UINT_TO_FP, MVT::i128, Custom);
2179 setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::i128, Custom);
2180 setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::i128, Custom);
2181 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::i128, Custom);
2182 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::i128, Custom);
2183 }
2184
2185 // On 32 bit MSVC, `fmodf(f32)` is not defined - only `fmod(f64)`
2186 // is. We should promote the value to 64-bits to solve this.
2187 // This is what the CRT headers do - `fmodf` is an inline header
2188 // function casting to f64 and calling `fmod`.
2189 if (Subtarget.is32Bit() &&
2190 (Subtarget.isTargetWindowsMSVC() || Subtarget.isTargetWindowsItanium()))
2191 for (ISD::NodeType Op :
2192 {ISD::FCEIL, ISD::STRICT_FCEIL,
2193 ISD::FCOS, ISD::STRICT_FCOS,
2194 ISD::FEXP, ISD::STRICT_FEXP,
2195 ISD::FFLOOR, ISD::STRICT_FFLOOR,
2196 ISD::FREM, ISD::STRICT_FREM,
2197 ISD::FLOG, ISD::STRICT_FLOG,
2198 ISD::FLOG10, ISD::STRICT_FLOG10,
2199 ISD::FPOW, ISD::STRICT_FPOW,
2200 ISD::FSIN, ISD::STRICT_FSIN})
2201 if (isOperationExpand(Op, MVT::f32))
2202 setOperationAction(Op, MVT::f32, Promote);
2203
2204 // We have target-specific dag combine patterns for the following nodes:
2205 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
2206 setTargetDAGCombine(ISD::SCALAR_TO_VECTOR);
2207 setTargetDAGCombine(ISD::INSERT_VECTOR_ELT);
2208 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
2209 setTargetDAGCombine(ISD::CONCAT_VECTORS);
2210 setTargetDAGCombine(ISD::INSERT_SUBVECTOR);
2211 setTargetDAGCombine(ISD::EXTRACT_SUBVECTOR);
2212 setTargetDAGCombine(ISD::BITCAST);
2213 setTargetDAGCombine(ISD::VSELECT);
2214 setTargetDAGCombine(ISD::SELECT);
2215 setTargetDAGCombine(ISD::SHL);
2216 setTargetDAGCombine(ISD::SRA);
2217 setTargetDAGCombine(ISD::SRL);
2218 setTargetDAGCombine(ISD::OR);
2219 setTargetDAGCombine(ISD::AND);
2220 setTargetDAGCombine(ISD::ADD);
2221 setTargetDAGCombine(ISD::FADD);
2222 setTargetDAGCombine(ISD::FSUB);
2223 setTargetDAGCombine(ISD::FNEG);
2224 setTargetDAGCombine(ISD::FMA);
2225 setTargetDAGCombine(ISD::STRICT_FMA);
2226 setTargetDAGCombine(ISD::FMINNUM);
2227 setTargetDAGCombine(ISD::FMAXNUM);
2228 setTargetDAGCombine(ISD::SUB);
2229 setTargetDAGCombine(ISD::LOAD);
2230 setTargetDAGCombine(ISD::MLOAD);
2231 setTargetDAGCombine(ISD::STORE);
2232 setTargetDAGCombine(ISD::MSTORE);
2233 setTargetDAGCombine(ISD::TRUNCATE);
2234 setTargetDAGCombine(ISD::ZERO_EXTEND);
2235 setTargetDAGCombine(ISD::ANY_EXTEND);
2236 setTargetDAGCombine(ISD::SIGN_EXTEND);
2237 setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
2238 setTargetDAGCombine(ISD::ANY_EXTEND_VECTOR_INREG);
2239 setTargetDAGCombine(ISD::SIGN_EXTEND_VECTOR_INREG);
2240 setTargetDAGCombine(ISD::ZERO_EXTEND_VECTOR_INREG);
2241 setTargetDAGCombine(ISD::SINT_TO_FP);
2242 setTargetDAGCombine(ISD::UINT_TO_FP);
2243 setTargetDAGCombine(ISD::STRICT_SINT_TO_FP);
2244 setTargetDAGCombine(ISD::STRICT_UINT_TO_FP);
2245 setTargetDAGCombine(ISD::SETCC);
2246 setTargetDAGCombine(ISD::MUL);
2247 setTargetDAGCombine(ISD::XOR);
2248 setTargetDAGCombine(ISD::MSCATTER);
2249 setTargetDAGCombine(ISD::MGATHER);
2250 setTargetDAGCombine(ISD::FP16_TO_FP);
2251 setTargetDAGCombine(ISD::FP_EXTEND);
2252 setTargetDAGCombine(ISD::STRICT_FP_EXTEND);
2253 setTargetDAGCombine(ISD::FP_ROUND);
2254
2255 computeRegisterProperties(Subtarget.getRegisterInfo());
2256
2257 MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
2258 MaxStoresPerMemsetOptSize = 8;
2259 MaxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
2260 MaxStoresPerMemcpyOptSize = 4;
2261 MaxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
2262 MaxStoresPerMemmoveOptSize = 4;
2263
2264 // TODO: These control memcmp expansion in CGP and could be raised higher, but
2265 // that needs to benchmarked and balanced with the potential use of vector
2266 // load/store types (PR33329, PR33914).
2267 MaxLoadsPerMemcmp = 2;
2268 MaxLoadsPerMemcmpOptSize = 2;
2269
2270 // Default loop alignment, which can be overridden by -align-loops.
2271 setPrefLoopAlignment(Align(16));
2272
2273 // An out-of-order CPU can speculatively execute past a predictable branch,
2274 // but a conditional move could be stalled by an expensive earlier operation.
2275 PredictableSelectIsExpensive = Subtarget.getSchedModel().isOutOfOrder();
2276 EnableExtLdPromotion = true;
2277 setPrefFunctionAlignment(Align(16));
2278
2279 verifyIntrinsicTables();
2280
2281 // Default to having -disable-strictnode-mutation on
2282 IsStrictFPEnabled = true;
2283}
2284
2285// This has so far only been implemented for 64-bit MachO.
2286bool X86TargetLowering::useLoadStackGuardNode() const {
2287 return Subtarget.isTargetMachO() && Subtarget.is64Bit();
2288}
2289
2290bool X86TargetLowering::useStackGuardXorFP() const {
2291 // Currently only MSVC CRTs XOR the frame pointer into the stack guard value.
2292 return Subtarget.getTargetTriple().isOSMSVCRT() && !Subtarget.isTargetMachO();
2293}
2294
2295SDValue X86TargetLowering::emitStackGuardXorFP(SelectionDAG &DAG, SDValue Val,
2296 const SDLoc &DL) const {
2297 EVT PtrTy = getPointerTy(DAG.getDataLayout());
2298 unsigned XorOp = Subtarget.is64Bit() ? X86::XOR64_FP : X86::XOR32_FP;
2299 MachineSDNode *Node = DAG.getMachineNode(XorOp, DL, PtrTy, Val);
2300 return SDValue(Node, 0);
2301}
2302
2303TargetLoweringBase::LegalizeTypeAction
2304X86TargetLowering::getPreferredVectorAction(MVT VT) const {
2305 if ((VT == MVT::v32i1 || VT == MVT::v64i1) && Subtarget.hasAVX512() &&
2306 !Subtarget.hasBWI())
2307 return TypeSplitVector;
2308
2309 if (!VT.isScalableVector() && VT.getVectorNumElements() != 1 &&
2310 VT.getVectorElementType() != MVT::i1)
2311 return TypeWidenVector;
2312
2313 return TargetLoweringBase::getPreferredVectorAction(VT);
2314}
2315
2316static std::pair<MVT, unsigned>
2317handleMaskRegisterForCallingConv(unsigned NumElts, CallingConv::ID CC,
2318 const X86Subtarget &Subtarget) {
2319 // v2i1/v4i1/v8i1/v16i1 all pass in xmm registers unless the calling
2320 // convention is one that uses k registers.
2321 if (NumElts == 2)
2322 return {MVT::v2i64, 1};
2323 if (NumElts == 4)
2324 return {MVT::v4i32, 1};
2325 if (NumElts == 8 && CC != CallingConv::X86_RegCall &&
2326 CC != CallingConv::Intel_OCL_BI)
2327 return {MVT::v8i16, 1};
2328 if (NumElts == 16 && CC != CallingConv::X86_RegCall &&
2329 CC != CallingConv::Intel_OCL_BI)
2330 return {MVT::v16i8, 1};
2331 // v32i1 passes in ymm unless we have BWI and the calling convention is
2332 // regcall.
2333 if (NumElts == 32 && (!Subtarget.hasBWI() || CC != CallingConv::X86_RegCall))
2334 return {MVT::v32i8, 1};
2335 // Split v64i1 vectors if we don't have v64i8 available.
2336 if (NumElts == 64 && Subtarget.hasBWI() && CC != CallingConv::X86_RegCall) {
2337 if (Subtarget.useAVX512Regs())
2338 return {MVT::v64i8, 1};
2339 return {MVT::v32i8, 2};
2340 }
2341
2342 // Break wide or odd vXi1 vectors into scalars to match avx2 behavior.
2343 if (!isPowerOf2_32(NumElts) || (NumElts == 64 && !Subtarget.hasBWI()) ||
2344 NumElts > 64)
2345 return {MVT::i8, NumElts};
2346
2347 return {MVT::INVALID_SIMPLE_VALUE_TYPE, 0};
2348}
2349
2350MVT X86TargetLowering::getRegisterTypeForCallingConv(LLVMContext &Context,
2351 CallingConv::ID CC,
2352 EVT VT) const {
2353 if (VT.isVector() && VT.getVectorElementType() == MVT::i1 &&
2354 Subtarget.hasAVX512()) {
2355 unsigned NumElts = VT.getVectorNumElements();
2356
2357 MVT RegisterVT;
2358 unsigned NumRegisters;
2359 std::tie(RegisterVT, NumRegisters) =
2360 handleMaskRegisterForCallingConv(NumElts, CC, Subtarget);
2361 if (RegisterVT != MVT::INVALID_SIMPLE_VALUE_TYPE)
2362 return RegisterVT;
2363 }
2364
2365 // v3f16 will be widen to v4f16. But we don't assign register class for v4f16.
2366 // So its default register type is f16. We override the type to v8f16 here.
2367 if (VT == MVT::v3f16 && Subtarget.hasFP16())
2368 return MVT::v8f16;
2369
2370 return TargetLowering::getRegisterTypeForCallingConv(Context, CC, VT);
2371}
2372
2373unsigned X86TargetLowering::getNumRegistersForCallingConv(LLVMContext &Context,
2374 CallingConv::ID CC,
2375 EVT VT) const {
2376 if (VT.isVector() && VT.getVectorElementType() == MVT::i1 &&
2377 Subtarget.hasAVX512()) {
2378 unsigned NumElts = VT.getVectorNumElements();
2379
2380 MVT RegisterVT;
2381 unsigned NumRegisters;
2382 std::tie(RegisterVT, NumRegisters) =
2383 handleMaskRegisterForCallingConv(NumElts, CC, Subtarget);
2384 if (RegisterVT != MVT::INVALID_SIMPLE_VALUE_TYPE)
2385 return NumRegisters;
2386 }
2387
2388 // v3f16 will be widen to v4f16. But we don't assign register class for v4f16.
2389 // So its default register number is 3. We override the number to 1 here.
2390 if (VT == MVT::v3f16 && Subtarget.hasFP16())
2391 return 1;
2392
2393 return TargetLowering::getNumRegistersForCallingConv(Context, CC, VT);
2394}
2395
2396unsigned X86TargetLowering::getVectorTypeBreakdownForCallingConv(
2397 LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT,
2398 unsigned &NumIntermediates, MVT &RegisterVT) const {
2399 // Break wide or odd vXi1 vectors into scalars to match avx2 behavior.
2400 if (VT.isVector() && VT.getVectorElementType() == MVT::i1 &&
2401 Subtarget.hasAVX512() &&
2402 (!isPowerOf2_32(VT.getVectorNumElements()) ||
2403 (VT.getVectorNumElements() == 64 && !Subtarget.hasBWI()) ||
2404 VT.getVectorNumElements() > 64)) {
2405 RegisterVT = MVT::i8;
2406 IntermediateVT = MVT::i1;
2407 NumIntermediates = VT.getVectorNumElements();
2408 return NumIntermediates;
2409 }
2410
2411 // Split v64i1 vectors if we don't have v64i8 available.
2412 if (VT == MVT::v64i1 && Subtarget.hasBWI() && !Subtarget.useAVX512Regs() &&
2413 CC != CallingConv::X86_RegCall) {
2414 RegisterVT = MVT::v32i8;
2415 IntermediateVT = MVT::v32i1;
2416 NumIntermediates = 2;
2417 return 2;
2418 }
2419
2420 return TargetLowering::getVectorTypeBreakdownForCallingConv(Context, CC, VT, IntermediateVT,
2421 NumIntermediates, RegisterVT);
2422}
2423
2424EVT X86TargetLowering::getSetCCResultType(const DataLayout &DL,
2425 LLVMContext& Context,
2426 EVT VT) const {
2427 if (!VT.isVector())
2428 return MVT::i8;
2429
2430 if (Subtarget.hasAVX512()) {
2431 // Figure out what this type will be legalized to.
2432 EVT LegalVT = VT;
2433 while (getTypeAction(Context, LegalVT) != TypeLegal)
2434 LegalVT = getTypeToTransformTo(Context, LegalVT);
2435
2436 // If we got a 512-bit vector then we'll definitely have a vXi1 compare.
2437 if (LegalVT.getSimpleVT().is512BitVector())
2438 return EVT::getVectorVT(Context, MVT::i1, VT.getVectorElementCount());
2439
2440 if (LegalVT.getSimpleVT().isVector() && Subtarget.hasVLX()) {
2441 // If we legalized to less than a 512-bit vector, then we will use a vXi1
2442 // compare for vXi32/vXi64 for sure. If we have BWI we will also support
2443 // vXi16/vXi8.
2444 MVT EltVT = LegalVT.getSimpleVT().getVectorElementType();
2445 if (Subtarget.hasBWI() || EltVT.getSizeInBits() >= 32)
2446 return EVT::getVectorVT(Context, MVT::i1, VT.getVectorElementCount());
2447 }
2448 }
2449
2450 return VT.changeVectorElementTypeToInteger();
2451}
2452
2453/// Helper for getByValTypeAlignment to determine
2454/// the desired ByVal argument alignment.
2455static void getMaxByValAlign(Type *Ty, Align &MaxAlign) {
2456 if (MaxAlign == 16)
2457 return;
2458 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
2459 if (VTy->getPrimitiveSizeInBits().getFixedSize() == 128)
2460 MaxAlign = Align(16);
2461 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
2462 Align EltAlign;
2463 getMaxByValAlign(ATy->getElementType(), EltAlign);
2464 if (EltAlign > MaxAlign)
2465 MaxAlign = EltAlign;
2466 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
2467 for (auto *EltTy : STy->elements()) {
2468 Align EltAlign;
2469 getMaxByValAlign(EltTy, EltAlign);
2470 if (EltAlign > MaxAlign)
2471 MaxAlign = EltAlign;
2472 if (MaxAlign == 16)
2473 break;
2474 }
2475 }
2476}
2477
2478/// Return the desired alignment for ByVal aggregate
2479/// function arguments in the caller parameter area. For X86, aggregates
2480/// that contain SSE vectors are placed at 16-byte boundaries while the rest
2481/// are at 4-byte boundaries.
2482uint64_t X86TargetLowering::getByValTypeAlignment(Type *Ty,
2483 const DataLayout &DL) const {
2484 if (Subtarget.is64Bit()) {
2485 // Max of 8 and alignment of type.
2486 Align TyAlign = DL.getABITypeAlign(Ty);
2487 if (TyAlign > 8)
2488 return TyAlign.value();
2489 return 8;
2490 }
2491
2492 Align Alignment(4);
2493 if (Subtarget.hasSSE1())
2494 getMaxByValAlign(Ty, Alignment);
2495 return Alignment.value();
2496}
2497
2498/// It returns EVT::Other if the type should be determined using generic
2499/// target-independent logic.
2500/// For vector ops we check that the overall size isn't larger than our
2501/// preferred vector width.
2502EVT X86TargetLowering::getOptimalMemOpType(
2503 const MemOp &Op, const AttributeList &FuncAttributes) const {
2504 if (!FuncAttributes.hasFnAttr(Attribute::NoImplicitFloat)) {
2505 if (Op.size() >= 16 &&
2506 (!Subtarget.isUnalignedMem16Slow() || Op.isAligned(Align(16)))) {
2507 // FIXME: Check if unaligned 64-byte accesses are slow.
2508 if (Op.size() >= 64 && Subtarget.hasAVX512() &&
2509 (Subtarget.getPreferVectorWidth() >= 512)) {
2510 return Subtarget.hasBWI() ? MVT::v64i8 : MVT::v16i32;
2511 }
2512 // FIXME: Check if unaligned 32-byte accesses are slow.
2513 if (Op.size() >= 32 && Subtarget.hasAVX() &&
2514 (Subtarget.getPreferVectorWidth() >= 256)) {
2515 // Although this isn't a well-supported type for AVX1, we'll let
2516 // legalization and shuffle lowering produce the optimal codegen. If we
2517 // choose an optimal type with a vector element larger than a byte,
2518 // getMemsetStores() may create an intermediate splat (using an integer
2519 // multiply) before we splat as a vector.
2520 return MVT::v32i8;
2521 }
2522 if (Subtarget.hasSSE2() && (Subtarget.getPreferVectorWidth() >= 128))
2523 return MVT::v16i8;
2524 // TODO: Can SSE1 handle a byte vector?
2525 // If we have SSE1 registers we should be able to use them.
2526 if (Subtarget.hasSSE1() && (Subtarget.is64Bit() || Subtarget.hasX87()) &&
2527 (Subtarget.getPreferVectorWidth() >= 128))
2528 return MVT::v4f32;
2529 } else if (((Op.isMemcpy() && !Op.isMemcpyStrSrc()) || Op.isZeroMemset()) &&
2530 Op.size() >= 8 && !Subtarget.is64Bit() && Subtarget.hasSSE2()) {
2531 // Do not use f64 to lower memcpy if source is string constant. It's
2532 // better to use i32 to avoid the loads.
2533 // Also, do not use f64 to lower memset unless this is a memset of zeros.
2534 // The gymnastics of splatting a byte value into an XMM register and then
2535 // only using 8-byte stores (because this is a CPU with slow unaligned
2536 // 16-byte accesses) makes that a loser.
2537 return MVT::f64;
2538 }
2539 }
2540 // This is a compromise. If we reach here, unaligned accesses may be slow on
2541 // this target. However, creating smaller, aligned accesses could be even
2542 // slower and would certainly be a lot more code.
2543 if (Subtarget.is64Bit() && Op.size() >= 8)
2544 return MVT::i64;
2545 return MVT::i32;
2546}
2547
2548bool X86TargetLowering::isSafeMemOpType(MVT VT) const {
2549 if (VT == MVT::f32)
2550 return X86ScalarSSEf32;
2551 if (VT == MVT::f64)
2552 return X86ScalarSSEf64;
2553 return true;
2554}
2555
2556bool X86TargetLowering::allowsMisalignedMemoryAccesses(
2557 EVT VT, unsigned, Align Alignment, MachineMemOperand::Flags Flags,
2558 bool *Fast) const {
2559 if (Fast) {
2560 switch (VT.getSizeInBits()) {
2561 default:
2562 // 8-byte and under are always assumed to be fast.
2563 *Fast = true;
2564 break;
2565 case 128:
2566 *Fast = !Subtarget.isUnalignedMem16Slow();
2567 break;
2568 case 256:
2569 *Fast = !Subtarget.isUnalignedMem32Slow();
2570 break;
2571 // TODO: What about AVX-512 (512-bit) accesses?
2572 }
2573 }
2574 // NonTemporal vector memory ops must be aligned.
2575 if (!!(Flags & MachineMemOperand::MONonTemporal) && VT.isVector()) {
2576 // NT loads can only be vector aligned, so if its less aligned than the
2577 // minimum vector size (which we can split the vector down to), we might as
2578 // well use a regular unaligned vector load.
2579 // We don't have any NT loads pre-SSE41.
2580 if (!!(Flags & MachineMemOperand::MOLoad))
2581 return (Alignment < 16 || !Subtarget.hasSSE41());
2582 return false;
2583 }
2584 // Misaligned accesses of any size are always allowed.
2585 return true;
2586}
2587
2588/// Return the entry encoding for a jump table in the
2589/// current function. The returned value is a member of the
2590/// MachineJumpTableInfo::JTEntryKind enum.
2591unsigned X86TargetLowering::getJumpTableEncoding() const {
2592 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
2593 // symbol.
2594 if (isPositionIndependent() && Subtarget.isPICStyleGOT())
2595 return MachineJumpTableInfo::EK_Custom32;
2596
2597 // Otherwise, use the normal jump table encoding heuristics.
2598 return TargetLowering::getJumpTableEncoding();
2599}
2600
2601bool X86TargetLowering::useSoftFloat() const {
2602 return Subtarget.useSoftFloat();
2603}
2604
2605void X86TargetLowering::markLibCallAttributes(MachineFunction *MF, unsigned CC,
2606 ArgListTy &Args) const {
2607
2608 // Only relabel X86-32 for C / Stdcall CCs.
2609 if (Subtarget.is64Bit())
2610 return;
2611 if (CC != CallingConv::C && CC != CallingConv::X86_StdCall)
2612 return;
2613 unsigned ParamRegs = 0;
2614 if (auto *M = MF->getFunction().getParent())
2615 ParamRegs = M->getNumberRegisterParameters();
2616
2617 // Mark the first N int arguments as having reg
2618 for (auto &Arg : Args) {
2619 Type *T = Arg.Ty;
2620 if (T->isIntOrPtrTy())
2621 if (MF->getDataLayout().getTypeAllocSize(T) <= 8) {
2622 unsigned numRegs = 1;
2623 if (MF->getDataLayout().getTypeAllocSize(T) > 4)
2624 numRegs = 2;
2625 if (ParamRegs < numRegs)
2626 return;
2627 ParamRegs -= numRegs;
2628 Arg.IsInReg = true;
2629 }
2630 }
2631}
2632
2633const MCExpr *
2634X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
2635 const MachineBasicBlock *MBB,
2636 unsigned uid,MCContext &Ctx) const{
2637 assert(isPositionIndependent() && Subtarget.isPICStyleGOT())(static_cast <bool> (isPositionIndependent() &&
Subtarget.isPICStyleGOT()) ? void (0) : __assert_fail ("isPositionIndependent() && Subtarget.isPICStyleGOT()"
, "/build/llvm-toolchain-snapshot-14~++20211016100712+8e1d532707fd/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 2637, __extension__ __PRETTY_FUNCTION__))
;
2638 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
2639 // entries.
2640 return MCSymbolRefExpr::create(MBB->getSymbol(),
2641 MCSymbolRefExpr::VK_GOTOFF, Ctx);
2642}
2643
2644/// Returns relocation base for the given PIC jumptable.
2645SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
2646 SelectionDAG &DAG) const {
2647 if (!Subtarget.is64Bit())
2648 // This doesn't have SDLoc associated with it, but is not really the
2649 // same as a Register.
2650 return DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(),
2651 getPointerTy(DAG.getDataLayout()));
2652 return Table;
2653}
2654
2655/// This returns the relocation base for the given PIC jumptable,
2656/// the same as getPICJumpTableRelocBase, but as an MCExpr.
2657const MCExpr *X86TargetLowering::
2658getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
2659 MCContext &Ctx) const {
2660 // X86-64 uses RIP relative addressing based on the jump table label.
2661 if (Subtarget.isPICStyleRIPRel())
2662 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
2663
2664 // Otherwise, the reference is relative to the PIC base.
2665 return MCSymbolRefExpr::create(MF->getPICBaseSymbol(), Ctx);
2666}
2667
2668std::pair<const TargetRegisterClass *, uint8_t>
2669X86TargetLowering::findRepresentativeClass(const TargetRegisterInfo *TRI,
2670 MVT VT) const {
2671 const TargetRegisterClass *RRC = nullptr;
2672 uint8_t Cost = 1;
2673 switch (VT.SimpleTy) {
2674 default:
2675 return TargetLowering::findRepresentativeClass(TRI, VT);
2676 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
2677 RRC = Subtarget.is64Bit() ? &X86::GR64RegClass : &X86::GR32RegClass;
2678 break;
2679 case MVT::x86mmx:
2680 RRC = &X86::VR64RegClass;
2681 break;
2682 case MVT::f32: case MVT::f64:
2683 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
2684 case MVT::v4f32: case MVT::v2f64:
2685 case MVT::v32i8: case MVT::v16i16: case MVT::v8i32: case MVT::v4i64:
2686 case MVT::v8f32: case MVT::v4f64:
2687 case MVT::v64i8: case MVT::v32i16: case MVT::v16i32: case MVT::v8i64:
2688 case MVT::v16f32: case MVT::v8f64:
2689 RRC = &X86::VR128XRegClass;
2690 break;
2691 }
2692 return std::make_pair(RRC, Cost);
2693}
2694
2695unsigned X86TargetLowering::getAddressSpace() const {
2696 if (Subtarget.is64Bit())
2697 return (getTargetMachine().getCodeModel() == CodeModel::Kernel) ? 256 : 257;
2698 return 256;
2699}
2700
2701static bool hasStackGuardSlotTLS(const Triple &TargetTriple) {
2702 return TargetTriple.isOSGlibc() || TargetTriple.isOSFuchsia() ||
2703 (TargetTriple.isAndroid() && !TargetTriple.isAndroidVersionLT(17));
2704}
2705
2706static Constant* SegmentOffset(IRBuilderBase &IRB,
2707 int Offset, unsigned AddressSpace) {
2708 return ConstantExpr::getIntToPtr(
2709 ConstantInt::get(Type::getInt32Ty(IRB.getContext()), Offset),
2710 Type::getInt8PtrTy(IRB.getContext())->getPointerTo(AddressSpace));
2711}
2712
2713Value *X86TargetLowering::getIRStackGuard(IRBuilderBase &IRB) const {
2714 // glibc, bionic, and Fuchsia have a special slot for the stack guard in
2715 // tcbhead_t; use it instead of the usual global variable (see
2716 // sysdeps/{i386,x86_64}/nptl/tls.h)
2717 if (hasStackGuardSlotTLS(Subtarget.getTargetTriple())) {
2718 if (Subtarget.isTargetFuchsia()) {
2719 // <zircon/tls.h> defines ZX_TLS_STACK_GUARD_OFFSET with this value.
2720 return SegmentOffset(IRB, 0x10, getAddressSpace());
2721 } else {
2722 unsigned AddressSpace = getAddressSpace();
2723 Module *M = IRB.GetInsertBlock()->getParent()->getParent();
2724 // Specially, some users may customize the base reg and offset.
2725 int Offset = M->getStackProtectorGuardOffset();
2726 // If we don't set -stack-protector-guard-offset value:
2727 // %fs:0x28, unless we're using a Kernel code model, in which case
2728 // it's %gs:0x28. gs:0x14 on i386.
2729 if (Offset == INT_MAX2147483647)
2730 Offset = (Subtarget.is64Bit()) ? 0x28 : 0x14;
2731
2732 StringRef GuardReg = M->getStackProtectorGuardReg();
2733 if (GuardReg == "fs")
2734 AddressSpace = X86AS::FS;
2735 else if (GuardReg == "gs")
2736 AddressSpace = X86AS::GS;
2737 return SegmentOffset(IRB, Offset, AddressSpace);
2738 }
2739 }
2740 return TargetLowering::getIRStackGuard(IRB);
2741}
2742
2743void X86TargetLowering::insertSSPDeclarations(Module &M) const {
2744 // MSVC CRT provides functionalities for stack protection.
2745 if (Subtarget.getTargetTriple().isWindowsMSVCEnvironment() ||
2746 Subtarget.getTargetTriple().isWindowsItaniumEnvironment()) {
2747 // MSVC CRT has a global variable holding security cookie.
2748 M.getOrInsertGlobal("__security_cookie",
2749 Type::getInt8PtrTy(M.getContext()));
2750
2751 // MSVC CRT has a function to validate security cookie.
2752 FunctionCallee SecurityCheckCookie = M.getOrInsertFunction(
2753 "__security_check_cookie", Type::getVoidTy(M.getContext()),
2754 Type::getInt8PtrTy(M.getContext()));
2755 if (Function *F = dyn_cast<Function>(SecurityCheckCookie.getCallee())) {
2756 F->setCallingConv(CallingConv::X86_FastCall);
2757 F->addParamAttr(0, Attribute::AttrKind::InReg);
2758 }
2759 return;
2760 }
2761
2762 StringRef GuardMode = M.getStackProtectorGuard();
2763
2764 // glibc, bionic, and Fuchsia have a special slot for the stack guard.
2765 if ((GuardMode == "tls" || GuardMode.empty()) &&
2766 hasStackGuardSlotTLS(Subtarget.getTargetTriple()))
2767 return;
2768 TargetLowering::insertSSPDeclarations(M);
2769}
2770
2771Value *X86TargetLowering::getSDagStackGuard(const Module &M) const {
2772 // MSVC CRT has a global variable holding security cookie.
2773 if (Subtarget.getTargetTriple().isWindowsMSVCEnvironment() ||
2774 Subtarget.getTargetTriple().isWindowsItaniumEnvironment()) {
2775 return M.getGlobalVariable("__security_cookie");
2776 }
2777 return TargetLowering::getSDagStackGuard(M);
2778}
2779
2780Function *X86TargetLowering::getSSPStackGuardCheck(const Module &M) const {
2781 // MSVC CRT has a function to validate security cookie.
2782 if (Subtarget.getTargetTriple().isWindowsMSVCEnvironment() ||
2783 Subtarget.getTargetTriple().isWindowsItaniumEnvironment()) {
2784 return M.getFunction("__security_check_cookie");
2785 }
2786 return TargetLowering::getSSPStackGuardCheck(M);
2787}
2788
2789Value *
2790X86TargetLowering::getSafeStackPointerLocation(IRBuilderBase &IRB) const {
2791 if (Subtarget.getTargetTriple().isOSContiki())
2792 return getDefaultSafeStackPointerLocation(IRB, false);
2793
2794 // Android provides a fixed TLS slot for the SafeStack pointer. See the
2795 // definition of TLS_SLOT_SAFESTACK in
2796 // https://android.googlesource.com/platform/bionic/+/master/libc/private/bionic_tls.h
2797 if (Subtarget.isTargetAndroid()) {
2798 // %fs:0x48, unless we're using a Kernel code model, in which case it's %gs:
2799 // %gs:0x24 on i386
2800 int Offset = (Subtarget.is64Bit()) ? 0x48 : 0x24;
2801 return SegmentOffset(IRB, Offset, getAddressSpace());
2802 }
2803
2804 // Fuchsia is similar.
2805 if (Subtarget.isTargetFuchsia()) {
2806 // <zircon/tls.h> defines ZX_TLS_UNSAFE_SP_OFFSET with this value.
2807 return SegmentOffset(IRB, 0x18, getAddressSpace());
2808 }
2809
2810 return TargetLowering::getSafeStackPointerLocation(IRB);
2811}
2812
2813//===----------------------------------------------------------------------===//
2814// Return Value Calling Convention Implementation
2815//===----------------------------------------------------------------------===//
2816
2817bool X86TargetLowering::CanLowerReturn(
2818 CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg,
2819 const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const {
2820 SmallVector<CCValAssign, 16> RVLocs;
2821 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
2822 return CCInfo.CheckReturn(Outs, RetCC_X86);
2823}
2824
2825const MCPhysReg *X86TargetLowering::getScratchRegisters(CallingConv::ID) const {
2826 static const MCPhysReg ScratchRegs[] = { X86::R11, 0 };
2827 return ScratchRegs;
2828}
2829
2830/// Lowers masks values (v*i1) to the local register values
2831/// \returns DAG node after lowering to register type
2832static SDValue lowerMasksToReg(const SDValue &ValArg, const EVT &ValLoc,
2833 const SDLoc &Dl, SelectionDAG &DAG) {
2834 EVT ValVT = ValArg.getValueType();
2835
2836 if (ValVT == MVT::v1i1)
2837 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, Dl, ValLoc, ValArg,
2838 DAG.getIntPtrConstant(0, Dl));
2839
2840 if ((ValVT == MVT::v8i1 && (ValLoc == MVT::i8 || ValLoc == MVT::i32)) ||
2841 (ValVT == MVT::v16i1 && (ValLoc == MVT::i16 || ValLoc == MVT::i32))) {
2842 // Two stage lowering might be required
2843 // bitcast: v8i1 -> i8 / v16i1 -> i16
2844 // anyextend: i8 -> i32 / i16 -> i32
2845 EVT TempValLoc = ValVT == MVT::v8i1 ? MVT::i8 : MVT::i16;
2846 SDValue ValToCopy = DAG.getBitcast(TempValLoc, ValArg);
2847 if (ValLoc == MVT::i32)
2848 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, Dl, ValLoc, ValToCopy);
2849 return ValToCopy;
2850 }
2851
2852 if ((ValVT == MVT::v32i1 && ValLoc == MVT::i32) ||
2853 (ValVT == MVT::v64i1 && ValLoc == MVT::i64)) {
2854 // One stage lowering is required
2855 // bitcast: v32i1 -> i32 / v64i1 -> i64
2856 return DAG.getBitcast(ValLoc, ValArg);
2857 }
2858
2859 return DAG.getNode(ISD::ANY_EXTEND, Dl, ValLoc, ValArg);
2860}
2861
2862/// Breaks v64i1 value into two registers and adds the new node to the DAG
2863static void Passv64i1ArgInRegs(
2864 const SDLoc &Dl, SelectionDAG &DAG, SDValue &Arg,
2865 SmallVectorImpl<std::pair<Register, SDValue>> &RegsToPass, CCValAssign &VA,
2866 CCValAssign &NextVA, const X86Subtarget &Subtarget) {
2867 assert(Subtarget.hasBWI() && "Expected AVX512BW target!")(static_cast <bool> (Subtarget.hasBWI() && "Expected AVX512BW target!"
) ? void (0) : __assert_fail ("Subtarget.hasBWI() && \"Expected AVX512BW target!\""
, "/build/llvm-toolchain-snapshot-14~++20211016100712+8e1d532707fd/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 2867, __extension__ __PRETTY_FUNCTION__))
;
2868 assert(Subtarget.is32Bit() && "Expecting 32 bit target")(static_cast <bool> (Subtarget.is32Bit() && "Expecting 32 bit target"
) ? void (0) : __assert_fail ("Subtarget.is32Bit() && \"Expecting 32 bit target\""
, "/build/llvm-toolchain-snapshot-14~++20211016100712+8e1d532707fd/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 2868, __extension__ __PRETTY_FUNCTION__))
;
2869 assert(Arg.getValueType() == MVT::i64 && "Expecting 64 bit value")(static_cast <bool> (Arg.getValueType() == MVT::i64 &&
"Expecting 64 bit value") ? void (0) : __assert_fail ("Arg.getValueType() == MVT::i64 && \"Expecting 64 bit value\""
, "/build/llvm-toolchain-snapshot-14~++20211016100712+8e1d532707fd/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 2869, __extension__ __PRETTY_FUNCTION__))
;
2870 assert(VA.isRegLoc() && NextVA.isRegLoc() &&(static_cast <bool> (VA.isRegLoc() && NextVA.isRegLoc
() && "The value should reside in two registers") ? void
(0) : __assert_fail ("VA.isRegLoc() && NextVA.isRegLoc() && \"The value should reside in two registers\""
, "/build/llvm-toolchain-snapshot-14~++20211016100712+8e1d532707fd/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 2871, __extension__ __PRETTY_FUNCTION__))
2871 "The value should reside in two registers")(static_cast <bool> (VA.isRegLoc() && NextVA.isRegLoc
() && "The value should reside in two registers") ? void
(0) : __assert_fail ("VA.isRegLoc() && NextVA.isRegLoc() && \"The value should reside in two registers\""
, "/build/llvm-toolchain-snapshot-14~++20211016100712+8e1d532707fd/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 2871, __extension__ __PRETTY_FUNCTION__))
;
2872
2873 // Before splitting the value we cast it to i64
2874 Arg = DAG.getBitcast(MVT::i64, Arg);
2875
2876 // Splitting the value into two i32 types
2877 SDValue Lo, Hi;
2878 Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, Dl, MVT::i32, Arg,
2879 DAG.getConstant(0, Dl, MVT::i32));
2880 Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, Dl, MVT::i32, Arg,
2881 DAG.getConstant(1, Dl, MVT::i32));
2882
2883 // Attach the two i32 types into corresponding registers
2884 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Lo));
2885 RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), Hi));
2886}
2887
2888SDValue
2889X86TargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
2890 bool isVarArg,
2891 const SmallVectorImpl<ISD::OutputArg> &Outs,
2892 const SmallVectorImpl<SDValue> &OutVals,
2893 const SDLoc &dl, SelectionDAG &DAG) const {
2894 MachineFunction &MF = DAG.getMachineFunction();
2895 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2896
2897 // In some cases we need to disable registers from the default CSR list.
2898 // For example, when they are used for argument passing.
2899 bool ShouldDisableCalleeSavedRegister =
2900 CallConv == CallingConv::X86_RegCall ||
2901 MF.getFunction().hasFnAttribute("no_caller_saved_registers");
2902
2903 if (CallConv == CallingConv::X86_INTR && !Outs.empty())
2904 report_fatal_error("X86 interrupts may not return any value");
2905
2906 SmallVector<CCValAssign, 16> RVLocs;
2907 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, *DAG.getContext());
2908 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
2909
2910 SmallVector<std::pair<Register, SDValue>, 4> RetVals;
2911 for (unsigned I = 0, OutsIndex = 0, E = RVLocs.size(); I != E;
2912 ++I, ++OutsIndex) {
2913 CCValAssign &VA = RVLocs[I];
2914 assert(VA.isRegLoc() && "Can only return in registers!")(static_cast <bool> (VA.isRegLoc() && "Can only return in registers!"
) ? void (0) : __assert_fail ("VA.isRegLoc() && \"Can only return in registers!\""
, "/build/llvm-toolchain-snapshot-14~++20211016100712+8e1d532707fd/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 2914, __extension__ __PRETTY_FUNCTION__))
;
2915
2916 // Add the register to the CalleeSaveDisableRegs list.
2917 if (ShouldDisableCalleeSavedRegister)
2918 MF.getRegInfo().disableCalleeSavedRegister(VA.getLocReg());
2919
2920 SDValue ValToCopy = OutVals[OutsIndex];
2921 EVT ValVT = ValToCopy.getValueType();
2922
2923 // Promote values to the appropriate types.
2924 if (VA.getLocInfo() == CCValAssign::SExt)
2925 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
2926 else if (VA.getLocInfo() == CCValAssign::ZExt)
2927 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy);
2928 else if (VA.getLocInfo() == CCValAssign::AExt) {
2929 if (ValVT.isVector() && ValVT.getVectorElementType() == MVT::i1)
2930 ValToCopy = lowerMasksToReg(ValToCopy, VA.getLocVT(), dl, DAG);
2931 else
2932 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy);
2933 }
2934 else if (VA.getLocInfo() == CCValAssign::BCvt)
2935 ValToCopy = DAG.getBitcast(VA.getLocVT(), ValToCopy);
2936
2937 assert(VA.getLocInfo() != CCValAssign::FPExt &&(static_cast <bool> (VA.getLocInfo() != CCValAssign::FPExt
&& "Unexpected FP-extend for return value.") ? void (
0) : __assert_fail ("VA.getLocInfo() != CCValAssign::FPExt && \"Unexpected FP-extend for return value.\""
, "/build/llvm-toolchain-snapshot-14~++20211016100712+8e1d532707fd/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 2938, __extension__ __PRETTY_FUNCTION__))
2938 "Unexpected FP-extend for return value.")(static_cast <bool> (VA.getLocInfo() != CCValAssign::FPExt
&& "Unexpected FP-extend for return value.") ? void (
0) : __assert_fail ("VA.getLocInfo() != CCValAssign::FPExt && \"Unexpected FP-extend for return value.\""
, "/build/llvm-toolchain-snapshot-14~++20211016100712+8e1d532707fd/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 2938, __extension__ __PRETTY_FUNCTION__))
;
2939
2940 // Report an error if we have attempted to return a value via an XMM
2941 // register and SSE was disabled.
2942 if (!Subtarget.hasSSE1() && X86::FR32XRegClass.contains(VA.getLocReg())) {
2943 errorUnsupported(DAG, dl, "SSE register return with SSE disabled");
2944 VA.convertToReg(X86::FP0); // Set reg to FP0, avoid hitting asserts.
2945 } else if (!Subtarget.hasSSE2() &&
2946 X86::FR64XRegClass.contains(VA.getLocReg()) &&
2947 ValVT == MVT::f64) {
2948 // When returning a double via an XMM register, report an error if SSE2 is
2949 // not enabled.
2950 errorUnsupported(DAG, dl, "SSE2 register return with SSE2 disabled");
2951 VA.convertToReg(X86::FP0); // Set reg to FP0, avoid hitting asserts.
2952 }
2953
2954 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
2955 // the RET instruction and handled by the FP Stackifier.
2956 if (VA.getLocReg() == X86::FP0 ||
2957 VA.getLocReg() == X86::FP1) {
2958 // If this is a copy from an xmm register to ST(0), use an FPExtend to
2959 // change the value to the FP stack register class.
2960 if (isScalarFPTypeInSSEReg(VA.getValVT()))
2961 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
2962 RetVals.push_back(std::make_pair(VA.getLocReg(), ValToCopy));
2963 // Don't emit a copytoreg.
2964 continue;
2965 }
2966
2967 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
2968 // which is returned in RAX / RDX.
2969 if (Subtarget.is64Bit()) {
2970 if (ValVT == MVT::x86mmx) {
2971 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
2972 ValToCopy = DAG.getBitcast(MVT::i64, ValToCopy);
2973 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
2974 ValToCopy);
2975 // If we don't have SSE2 available, convert to v4f32 so the generated
2976 // register is legal.
2977 if (!Subtarget.hasSSE2())
2978 ValToCopy = DAG.getBitcast(MVT::v4f32, ValToCopy);
2979 }
2980 }
2981 }
2982
2983 if (VA.needsCustom()) {
2984 assert(VA.getValVT() == MVT::v64i1 &&(static_cast <bool> (VA.getValVT() == MVT::v64i1 &&
"Currently the only custom case is when we split v64i1 to 2 regs"
) ? void (0) : __assert_fail ("VA.getValVT() == MVT::v64i1 && \"Currently the only custom case is when we split v64i1 to 2 regs\""
, "/build/llvm-toolchain-snapshot-14~++20211016100712+8e1d532707fd/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 2985, __extension__ __PRETTY_FUNCTION__))
2985 "Currently the only custom case is when we split v64i1 to 2 regs")(static_cast <bool> (VA.getValVT() == MVT::v64i1 &&
"Currently the only custom case is when we split v64i1 to 2 regs"
) ? void (0) : __assert_fail ("VA.getValVT() == MVT::v64i1 && \"Currently the only custom case is when we split v64i1 to 2 regs\""
, "/build/llvm-toolchain-snapshot-14~++20211016100712+8e1d532707fd/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 2985, __extension__ __PRETTY_FUNCTION__))
;
2986
2987 Passv64i1ArgInRegs(dl, DAG, ValToCopy, RetVals, VA, RVLocs[++I],
2988 Subtarget);
2989
2990 // Add the second register to the CalleeSaveDisableRegs list.
2991 if (ShouldDisableCalleeSavedRegister)
2992 MF.getRegInfo().disableCalleeSavedRegister(RVLocs[I].getLocReg());
2993 } else {
2994 RetVals.push_back(std::make_pair(VA.getLocReg(), ValToCopy));
2995 }
2996 }
2997
2998 SDValue Flag;
2999 SmallVector<SDValue, 6> RetOps;
3000 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
3001 // Operand #1 = Bytes To Pop
3002 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(), dl,
3003 MVT::i32));
3004
3005 // Copy the result values into the output registers.
3006 for (auto &RetVal : RetVals) {
3007 if (RetVal.first == X86::FP0 || RetVal.first == X86::FP1) {
3008 RetOps.push_back(RetVal.second);
3009 continue; // Don't emit a copytoreg.
3010 }
3011
3012 Chain = DAG.getCopyToReg(Chain, dl, RetVal.first, RetVal.second, Flag);
3013 Flag = Chain.getValue(1);
3014 RetOps.push_back(
3015 DAG.getRegister(RetVal.first, RetVal.second.getValueType()));
3016 }
3017
3018 // Swift calling convention does not require we copy the sret argument
3019 // into %rax/%eax for the return, and SRetReturnReg is not set for Swift.
3020
3021 // All x86 ABIs require that for returning structs by value we copy
3022 // the sret argument into %rax/%eax (depending on ABI) for the return.
3023 // We saved the argument into a virtual register in the entry block,
3024 // so now we copy the value out and into %rax/%eax.
3025 //
3026 // Checking Function.hasStructRetAttr() here is insufficient because the IR
3027 // may not have an explicit sret argument. If FuncInfo.CanLowerReturn is
3028 // false, then an sret argument may be implicitly inserted in the SelDAG. In
3029 // either case FuncInfo->setSRetReturnReg() will have been called.
3030 if (Register SRetReg = FuncInfo->getSRetReturnReg()) {
3031 // When we have both sret and another return value, we should use the
3032 // original Chain stored in RetOps[0], instead of the current Chain updated
3033 // in the above loop. If we only have sret, RetOps[0] equals to Chain.
3034
3035 // For the case of sret and another return value, we have
3036 // Chain_0 at the function entry
3037 // Chain_1 = getCopyToReg(Chain_0) in the above loop
3038 // If we use Chain_1 in getCopyFromReg, we will have
3039 // Val = getCopyFromReg(Chain_1)
3040 // Chain_2 = getCopyToReg(Chain_1, Val) from below
3041
3042 // getCopyToReg(Chain_0) will be glued together with
3043 // getCopyToReg(Chain_1, Val) into Unit A, getCopyFromReg(Chain_1) will be
3044 // in Unit B, and we will have cyclic dependency between Unit A and Unit B:
3045 // Data dependency from Unit B to Unit A due to usage of Val in
3046 // getCopyToReg(Chain_1, Val)
3047 // Chain dependency from Unit A to Unit B
3048
3049 // So here, we use RetOps[0] (i.e Chain_0) for getCopyFromReg.
3050 SDValue Val = DAG.getCopyFromReg(RetOps[0], dl, SRetReg,
3051 getPointerTy(MF.getDataLayout()));
3052
3053 Register RetValReg
3054 = (Subtarget.is64Bit() && !Subtarget.isTarget64BitILP32()) ?
3055 X86::RAX : X86::EAX;
3056 Chain = DAG.getCopyToReg(Chain, dl, RetValReg, Val, Flag);
3057 Flag = Chain.getValue(1);
3058
3059 // RAX/EAX now acts like a return value.
3060 RetOps.push_back(
3061 DAG.getRegister(RetValReg, getPointerTy(DAG.getDataLayout())));
3062
3063 // Add the returned register to the CalleeSaveDisableRegs list.
3064 if (ShouldDisableCalleeSavedRegister)
3065 MF.getRegInfo().disableCalleeSavedRegister(RetValReg);
3066 }
3067
3068 const X86RegisterInfo *TRI = Subtarget.getRegisterInfo();
3069 const MCPhysReg *I =
3070 TRI->getCalleeSavedRegsViaCopy(&DAG.getMachineFunction());
3071 if (I) {
3072 for (; *I; ++I) {
3073 if (X86::GR64RegClass.contains(*I))
3074 RetOps.push_back(DAG.getRegister(*I, MVT::i64));
3075 else
3076 llvm_unreachable("Unexpected register class in CSRsViaCopy!")::llvm::llvm_unreachable_internal("Unexpected register class in CSRsViaCopy!"
, "/build/llvm-toolchain-snapshot-14~++20211016100712+8e1d532707fd/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 3076)
;
3077 }
3078 }
3079
3080 RetOps[0] = Chain; // Update chain.
3081
3082 // Add the flag if we have it.
3083 if (Flag.getNode())
3084 RetOps.push_back(Flag);
3085
3086 X86ISD::NodeType opcode = X86ISD::RET_FLAG;
3087 if (CallConv == CallingConv::X86_INTR)
3088 opcode = X86ISD::IRET;
3089 return DAG.getNode(opcode, dl, MVT::Other, RetOps);
3090}
3091
3092bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
3093 if (N->getNumValues() != 1 || !N->hasNUsesOfValue(1, 0))
3094 return false;
3095
3096 SDValue TCChain = Chain;
3097 SDNode *Copy = *N->use_begin();
3098 if (Copy->getOpcode() == ISD::CopyToReg) {
3099 // If the copy has a glue operand, we conservatively assume it isn't safe to
3100 // perform a tail call.
3101 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
3102 return false;
3103 TCChain = Copy->getOperand(0);
3104 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
3105 return false;
3106
3107 bool HasRet = false;
3108 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
3109 UI != UE; ++UI) {
3110 if (UI->getOpcode() != X86ISD::RET_FLAG)
3111 return false;
3112 // If we are returning more than one value, we can definitely
3113 // not make a tail call see PR19530
3114 if (UI->getNumOperands() > 4)
3115 return false;
3116 if (UI->getNumOperands() == 4 &&
3117 UI->getOperand(UI->getNumOperands()-1).getValueType() != MVT::Glue)
3118 return false;
3119 HasRet = true;
3120 }
3121
3122 if (!HasRet)
3123 return false;
3124
3125 Chain = TCChain;
3126 return true;
3127}
3128
3129EVT X86TargetLowering::getTypeForExtReturn(LLVMContext &Context, EVT VT,
3130 ISD::NodeType ExtendKind) const {
3131 MVT ReturnMVT = MVT::i32;
3132
3133 bool Darwin = Subtarget.getTargetTriple().isOSDarwin();
3134 if (VT == MVT::i1 || (!Darwin && (VT == MVT::i8 || VT == MVT::i16))) {
3135 // The ABI does not require i1, i8 or i16 to be extended.
3136 //
3137 // On Darwin, there is code in the wild relying on Clang's old behaviour of
3138 // always extending i8/i16 return values, so keep doing that for now.
3139 // (PR26665).
3140 ReturnMVT = MVT::i8;
3141 }
3142
3143 EVT MinVT = getRegisterType(Context, ReturnMVT);
3144 return VT.bitsLT(MinVT) ? MinVT : VT;
3145}
3146
3147/// Reads two 32 bit registers and creates a 64 bit mask value.
3148/// \param VA The current 32 bit value that need to be assigned.
3149/// \param NextVA The next 32 bit value that need to be assigned.
3150/// \param Root The parent DAG node.
3151/// \param [in,out] InFlag Represents SDvalue in the parent DAG node for
3152/// glue purposes. In the case the DAG is already using
3153/// physical register instead of virtual, we should glue
3154/// our new SDValue to InFlag SDvalue.
3155/// \return a new SDvalue of size 64bit.
3156static SDValue getv64i1Argument(CCValAssign &VA, CCValAssign &NextVA,
3157 SDValue &Root, SelectionDAG &DAG,
3158 const SDLoc &Dl, const X86Subtarget &Subtarget,
3159 SDValue *InFlag = nullptr) {
3160 assert((Subtarget.hasBWI()) && "Expected AVX512BW target!")(static_cast <bool> ((Subtarget.hasBWI()) && "Expected AVX512BW target!"
) ? void (0) : __assert_fail ("(Subtarget.hasBWI()) && \"Expected AVX512BW target!\""
, "/build/llvm-toolchain-snapshot-14~++20211016100712+8e1d532707fd/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 3160, __extension__ __PRETTY_FUNCTION__))
;
3161 assert(Subtarget.is32Bit() && "Expecting 32 bit target")(static_cast <bool> (Subtarget.is32Bit() && "Expecting 32 bit target"
) ? void (0) : __assert_fail ("Subtarget.is32Bit() && \"Expecting 32 bit target\""
, "/build/llvm-toolchain-snapshot-14~++20211016100712+8e1d532707fd/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 3161, __extension__ __PRETTY_FUNCTION__))
;
3162 assert(VA.getValVT() == MVT::v64i1 &&(static_cast <bool> (VA.getValVT() == MVT::v64i1 &&
"Expecting first location of 64 bit width type") ? void (0) :
__assert_fail ("VA.getValVT() == MVT::v64i1 && \"Expecting first location of 64 bit width type\""
, "/build/llvm-toolchain-snapshot-14~++20211016100712+8e1d532707fd/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 3163, __extension__ __PRETTY_FUNCTION__))
3163 "Expecting first location of 64 bit width type")(static_cast <bool> (VA.getValVT() == MVT::v64i1 &&
"Expecting first location of 64 bit width type") ? void (0) :
__assert_fail ("VA.getValVT() == MVT::v64i1 && \"Expecting first location of 64 bit width type\""
, "/build/llvm-toolchain-snapshot-14~++20211016100712+8e1d532707fd/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 3163, __extension__ __PRETTY_FUNCTION__))
;
3164 assert(NextVA.getValVT() == VA.getValVT() &&(static_cast <bool> (NextVA.getValVT() == VA.getValVT()
&& "The locations should have the same type") ? void
(0) : __assert_fail ("NextVA.getValVT() == VA.getValVT() && \"The locations should have the same type\""
, "/build/llvm-toolchain-snapshot-14~++20211016100712+8e1d532707fd/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 3165, __extension__ __PRETTY_FUNCTION__))
3165 "The locations should have the same type")(static_cast <bool> (NextVA.getValVT() == VA.getValVT()
&& "The locations should have the same type") ? void
(0) : __assert_fail ("NextVA.getValVT() == VA.getValVT() && \"The locations should have the same type\""
, "/build/llvm-toolchain-snapshot-14~++20211016100712+8e1d532707fd/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 3165, __extension__ __PRETTY_FUNCTION__))
;
3166 assert(VA.isRegLoc() && NextVA.isRegLoc() &&(static_cast <bool> (VA.isRegLoc() && NextVA.isRegLoc
() && "The values should reside in two registers") ? void
(0) : __assert_fail ("VA.isRegLoc() && NextVA.isRegLoc() && \"The values should reside in two registers\""
, "/build/llvm-toolchain-snapshot-14~++20211016100712+8e1d532707fd/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 3167, __extension__ __PRETTY_FUNCTION__))
3167 "The values should reside in two registers")(static_cast <bool> (VA.isRegLoc() && NextVA.isRegLoc
() && "The values should reside in two registers") ? void
(0) : __assert_fail ("VA.isRegLoc() && NextVA.isRegLoc() && \"The values should reside in two registers\""
, "/build/llvm-toolchain-snapshot-14~++20211016100712+8e1d532707fd/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 3167, __extension__ __PRETTY_FUNCTION__))
;
3168
3169 SDValue Lo, Hi;
3170 SDValue ArgValueLo, ArgValueHi;
3171
3172 MachineFunction &MF = DAG.getMachineFunction();
3173 const TargetRegisterClass *RC = &X86::GR32RegClass;
3174
3175 // Read a 32 bit value from the registers.
3176 if (nullptr == InFlag) {
3177 // When no physical register is present,
3178 // create an intermediate virtual register.
3179 Register Reg = MF.addLiveIn(VA.getLocReg(), RC);
3180 ArgValueLo = DAG.getCopyFromReg(Root, Dl, Reg, MVT::i32);
3181 Reg = MF.addLiveIn(NextVA.getLocReg(), RC);
3182 ArgValueHi = DAG.getCopyFromReg(Root, Dl, Reg, MVT::i32);
3183 } else {
3184 // When a physical register is available read the value from it and glue
3185 // the reads together.
3186 ArgValueLo =
3187 DAG.getCopyFromReg(Root, Dl, VA.getLocReg(), MVT::i32, *InFlag);
3188 *InFlag = ArgValueLo.getValue(2);
3189 ArgValueHi =
3190 DAG.getCopyFromReg(Root, Dl, NextVA.getLocReg(), MVT::i32, *InFlag);
3191 *InFlag = ArgValueHi.getValue(2);
3192 }
3193
3194 // Convert the i32 type into v32i1 type.
3195 Lo = DAG.getBitcast(MVT::v32i1, ArgValueLo);
3196
3197 // Convert the i32 type into v32i1 type.
3198 Hi = DAG.getBitcast(MVT::v32i1, ArgValueHi);
3199
3200 // Concatenate the two values together.
3201 return DAG.getNode(ISD::CONCAT_VECTORS, Dl, MVT::v64i1, Lo, Hi);
3202}
3203
3204/// The function will lower a register of various sizes (8/16/32/64)
3205/// to a mask value of the expected size (v8i1/v16i1/v32i1/v64i1)
3206/// \returns a DAG node contains the operand after lowering to mask type.
3207static SDValue lowerRegToMasks(const SDValue &ValArg, const EVT &ValVT,
3208 const EVT &ValLoc, const SDLoc &Dl,
3209 SelectionDAG &DAG) {
3210 SDValue ValReturned = ValArg;
3211
3212 if (ValVT == MVT::v1i1)
3213 return DAG.getNode(ISD::SCALAR_TO_VECTOR, Dl, MVT::v1i1, ValReturned);
3214
3215 if (ValVT == MVT::v64i1) {
3216 // In 32 bit machine, this case is handled by getv64i1Argument
3217 assert(ValLoc == MVT::i64 && "Expecting only i64 locations")(static_cast <bool> (ValLoc == MVT::i64 && "Expecting only i64 locations"
) ? void (0) : __assert_fail ("ValLoc == MVT::i64 && \"Expecting only i64 locations\""
, "/build/llvm-toolchain-snapshot-14~++20211016100712+8e1d532707fd/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 3217, __extension__ __PRETTY_FUNCTION__))
;
3218 // In 64 bit machine, There is no need to truncate the value only bitcast
3219 } else {
3220 MVT maskLen;
3221 switch (ValVT.getSimpleVT().SimpleTy) {
3222 case MVT::v8i1:
3223 maskLen = MVT::i8;
3224 break;
3225 case MVT::v16i1:
3226 maskLen = MVT::i16;
3227 break;
3228 case MVT::v32i1:
3229 maskLen = MVT::i32;
3230 break;
3231 default:
3232 llvm_unreachable("Expecting a vector of i1 types")::llvm::llvm_unreachable_internal("Expecting a vector of i1 types"
, "/build/llvm-toolchain-snapshot-14~++20211016100712+8e1d532707fd/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 3232)
;
3233 }
3234
3235 ValReturned = DAG.getNode(ISD::TRUNCATE, Dl, maskLen, ValReturned);
3236 }
3237 return DAG.getBitcast(ValVT, ValReturned);
3238}
3239
3240/// Lower the result values of a call into the
3241/// appropriate copies out of appropriate physical registers.
3242///
3243SDValue X86TargetLowering::LowerCallResult(
3244 SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg,
3245 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
3246 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals,
3247 uint32_t *RegMask) const {
3248
3249 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
3250 // Assign locations to each value returned by this call.
3251 SmallVector<CCValAssign, 16> RVLocs;
3252 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
3253 *DAG.getContext());
3254 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
3255
3256 // Copy all of the result registers out of their specified physreg.
3257 for (unsigned I = 0, InsIndex = 0, E = RVLocs.size(); I != E;
3258 ++I, ++InsIndex) {
3259 CCValAssign &VA = RVLocs[I];
3260 EVT CopyVT = VA.getLocVT();
3261
3262 // In some calling conventions we need to remove the used registers
3263 // from the register mask.
3264 if (RegMask) {
3265 for (MCSubRegIterator SubRegs(VA.getLocReg(), TRI, /*IncludeSelf=*/true);
3266 SubRegs.isValid(); ++SubRegs)
3267 RegMask[*SubRegs / 32] &= ~(1u << (*SubRegs % 32));
3268 }
3269
3270 // Report an error if there was an attempt to return FP values via XMM
3271 // registers.
3272 if (!Subtarget.hasSSE1() && X86::FR32XRegClass.contains(VA.getLocReg())) {
3273 errorUnsupported(DAG, dl, "SSE register return with SSE disabled");
3274 if (VA.getLocReg() == X86::XMM1)
3275 VA.convertToReg(X86::FP1); // Set reg to FP1, avoid hitting asserts.
3276 else
3277 VA.convertToReg(X86::FP0); // Set reg to FP0, avoid hitting asserts.
3278 } else if (!Subtarget.hasSSE2() &&
3279 X86::FR64XRegClass.contains(VA.getLocReg()) &&
3280 CopyVT == MVT::f64) {
3281 errorUnsupported(DAG, dl, "SSE2 register return with SSE2 disabled");
3282 if (VA.getLocReg() == X86::XMM1)
3283 VA.convertToReg(X86::FP1); // Set reg to FP1, avoid hitting asserts.
3284 else
3285 VA.convertToReg(X86::FP0); // Set reg to FP0, avoid hitting asserts.
3286 }
3287
3288 // If we prefer to use the value in xmm registers, copy it out as f80 and
3289 // use a truncate to move it from fp stack reg to xmm reg.
3290 bool RoundAfterCopy = false;
3291 if ((VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1) &&
3292 isScalarFPTypeInSSEReg(VA.getValVT())) {
3293 if (!Subtarget.hasX87())
3294 report_fatal_error("X87 register return with X87 disabled");
3295 CopyVT = MVT::f80;
3296 RoundAfterCopy = (CopyVT != VA.getLocVT());
3297 }
3298
3299 SDValue Val;
3300 if (VA.needsCustom()) {
3301 assert(VA.getValVT() == MVT::v64i1 &&(static_cast <bool> (VA.getValVT() == MVT::v64i1 &&
"Currently the only custom case is when we split v64i1 to 2 regs"
) ? void (0) : __assert_fail ("VA.getValVT() == MVT::v64i1 && \"Currently the only custom case is when we split v64i1 to 2 regs\""
, "/build/llvm-toolchain-snapshot-14~++20211016100712+8e1d532707fd/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 3302, __extension__ __PRETTY_FUNCTION__))
3302 "Currently the only custom case is when we split v64i1 to 2 regs")(static_cast <bool> (VA.getValVT() == MVT::v64i1 &&
"Currently the only custom case is when we split v64i1 to 2 regs"
) ? void (0) : __assert_fail ("VA.getValVT() == MVT::v64i1 && \"Currently the only custom case is when we split v64i1 to 2 regs\""
, "/build/llvm-toolchain-snapshot-14~++20211016100712+8e1d532707fd/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 3302, __extension__ __PRETTY_FUNCTION__))
;
3303 Val =
3304 getv64i1Argument(VA, RVLocs[++I], Chain, DAG, dl, Subtarget, &InFlag);
3305 } else {
3306 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), CopyVT, InFlag)
3307 .getValue(1);
3308 Val = Chain.getValue(0);
3309 InFlag = Chain.getValue(2);
3310 }
3311
3312 if (RoundAfterCopy)
3313 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
3314 // This truncation won't change the value.
3315 DAG.getIntPtrConstant(1, dl));
3316
3317 if (VA.isExtInLoc()) {
3318 if (VA.getValVT().isVector() &&
3319 VA.getValVT().getScalarType() == MVT::i1 &&
3320 ((VA.getLocVT() == MVT::i64) || (VA.getLocVT() == MVT::i32) ||
3321 (VA.getLocVT() == MVT::i16) || (VA.getLocVT() == MVT::i8))) {
3322 // promoting a mask type (v*i1) into a register of type i64/i32/i16/i8
3323 Val = lowerRegToMasks(Val, VA.getValVT(), VA.getLocVT(), dl, DAG);
3324 } else
3325 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
3326 }
3327
3328 if (VA.getLocInfo() == CCValAssign::BCvt)
3329 Val = DAG.getBitcast(VA.getValVT(), Val);
3330
3331 InVals.push_back(Val);
3332 }
3333
3334 return Chain;
3335}
3336
3337//===----------------------------------------------------------------------===//
3338// C & StdCall & Fast Calling Convention implementation
3339//===----------------------------------------------------------------------===//
3340// StdCall calling convention seems to be standard for many Windows' API
3341// routines and around. It differs from C calling convention just a little:
3342// callee should clean up the stack, not caller. Symbols should be also
3343// decorated in some fancy way :) It doesn't support any vector arguments.
3344// For info on fast calling convention see Fast Calling Convention (tail call)
3345// implementation LowerX86_32FastCCCallTo.
3346
3347/// Determines whether Args, either a set of outgoing arguments to a call, or a
3348/// set of incoming args of a call, contains an sret pointer that the callee
3349/// pops
3350template <typename T>
3351static bool hasCalleePopSRet(const SmallVectorImpl<T> &Args,
3352 const X86Subtarget &Subtarget) {
3353 // Not C++20 (yet), so no concepts available.
3354 static_assert(std::is_same<T, ISD::OutputArg>::value ||
3355 std::is_same<T, ISD::InputArg>::value,
3356 "requires ISD::OutputArg or ISD::InputArg");
3357
3358 // Only 32-bit pops the sret. It's a 64-bit world these days, so early-out
3359 // for most compilations.
3360 if (!Subtarget.is32Bit())
3361 return false;
3362
3363 if (Args.empty())
3364 return false;
3365
3366 // Most calls do not have an sret argument, check the arg next.
3367 const ISD::ArgFlagsTy &Flags = Args[0].Flags;
3368 if (!Flags.isSRet() || Flags.isInReg())
3369 return false;
3370
3371 // The MSVCabi does not pop the sret.
3372 if (Subtarget.getTargetTriple().isOSMSVCRT())
3373 return false;
3374
3375 // MCUs don't pop the sret
3376 if (Subtarget.isTargetMCU())
3377 return false;
3378
3379 // Callee pops argument
3380 return true;
3381}
3382
3383/// Make a copy of an aggregate at address specified by "Src" to address
3384/// "Dst" with size and alignment information specified by the specific
3385/// parameter attribute. The copy will be passed as a byval function parameter.
3386static SDValue CreateCopyOfByValArgument(SDValue Src, SDValue Dst,
3387 SDValue Chain, ISD::ArgFlagsTy Flags,
3388 SelectionDAG &DAG, const SDLoc &dl) {
3389 SDValue SizeNode = DAG.getIntPtrConstant(Flags.getByValSize(), dl);
3390
3391 return DAG.getMemcpy(
3392 Chain, dl, Dst, Src, SizeNode, Flags.getNonZeroByValAlign(),
3393 /*isVolatile*/ false, /*AlwaysInline=*/true,
3394 /*isTailCall*/ false, MachinePointerInfo(), MachinePointerInfo());
3395}
3396
3397/// Return true if the calling convention is one that we can guarantee TCO for.
3398static bool canGuaranteeTCO(CallingConv::ID CC) {
3399 return (CC == CallingConv::Fast || CC == CallingConv::GHC ||
3400 CC == CallingConv::X86_RegCall || CC == CallingConv::HiPE ||
3401 CC == CallingConv::HHVM || CC == CallingConv::Tail ||
3402 CC == CallingConv::SwiftTail);
3403}
3404
3405/// Return true if we might ever do TCO for calls with this calling convention.
3406static bool mayTailCallThisCC(CallingConv::ID CC) {
3407 switch (CC) {
3408 // C calling conventions:
3409 case CallingConv::C:
3410 case CallingConv::Win64:
3411 case CallingConv::X86_64_SysV:
3412 // Callee pop conventions:
3413 case CallingConv::X86_ThisCall:
3414 case CallingConv::X86_StdCall:
3415 case CallingConv::X86_VectorCall:
3416 case CallingConv::X86_FastCall:
3417 // Swift:
3418 case CallingConv::Swift:
3419 return true;
3420 default:
3421 return canGuaranteeTCO(CC);
3422 }
3423}
3424
3425/// Return true if the function is being made into a tailcall target by
3426/// changing its ABI.
3427static bool shouldGuaranteeTCO(CallingConv::ID CC, bool GuaranteedTailCallOpt) {
3428 return (GuaranteedTailCallOpt && canGuaranteeTCO(CC)) ||
3429 CC == CallingConv::Tail || CC == CallingConv::SwiftTail;
3430}
3431
3432bool X86TargetLowering::mayBeEmittedAsTailCall(const CallInst *CI) const {
3433 if (!CI->isTailCall())
3434 return false;
3435
3436 CallingConv::ID CalleeCC = CI->getCallingConv();
3437 if (!mayTailCallThisCC(CalleeCC))
3438 return false;
3439
3440 return true;
3441}
3442
3443SDValue
3444X86TargetLowering::LowerMemArgument(SDValue Chain, CallingConv::ID CallConv,
3445 const SmallVectorImpl<ISD::InputArg> &Ins,
3446 const SDLoc &dl, SelectionDAG &DAG,
3447 const CCValAssign &VA,
3448 MachineFrameInfo &MFI, unsigned i) const {
3449 // Create the nodes corresponding to a load from this parameter slot.
3450 ISD::ArgFlagsTy Flags = Ins[i].Flags;
3451 bool AlwaysUseMutable = shouldGuaranteeTCO(
3452 CallConv, DAG.getTarget().Options.GuaranteedTailCallOpt);
3453 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
3454 EVT ValVT;
3455 MVT PtrVT = getPointerTy(DAG.getDataLayout());
3456
3457 // If value is passed by pointer we have address passed instead of the value
3458 // itself. No need to extend if the mask value and location share the same
3459 // absolute size.
3460 bool ExtendedInMem =
3461 VA.isExtInLoc() && VA.getValVT().getScalarType() == MVT::i1 &&
3462 VA.getValVT().getSizeInBits() != VA.getLocVT().getSizeInBits();
3463
3464 if (VA.getLocInfo() == CCValAssign::Indirect || ExtendedInMem)
3465 ValVT = VA.getLocVT();
3466 else
3467 ValVT = VA.getValVT();
3468
3469 // FIXME: For now, all byval parameter objects are marked mutable. This can be
3470 // changed with more analysis.
3471 // In case of tail call optimization mark all arguments mutable. Since they
3472 // could be overwritten by lowering of arguments in case of a tail call.
3473 if (Flags.isByVal()) {
3474 unsigned Bytes = Flags.getByValSize();
3475 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
3476
3477 // FIXME: For now, all byval parameter objects are marked as aliasing. This
3478 // can be improved with deeper analysis.
3479 int FI = MFI.CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable,
3480 /*isAliased=*/true);
3481 return DAG.getFrameIndex(FI, PtrVT);
3482 }
3483
3484 EVT ArgVT = Ins[i].ArgVT;
3485
3486 // If this is a vector that has been split into multiple parts, and the
3487 // scalar size of the parts don't match the vector element size, then we can't
3488 // elide the copy. The parts will have padding between them instead of being
3489 // packed like a vector.
3490 bool ScalarizedAndExtendedVector =
3491 ArgVT.isVector() && !VA.getLocVT().isVector() &&
3492 VA.getLocVT().getSizeInBits() != ArgVT.getScalarSizeInBits();
3493
3494 // This is an argument in memory. We might be able to perform copy elision.
3495 // If the argument is passed directly in memory without any extension, then we
3496 // can perform copy elision. Large vector types, for example, may be passed
3497 // indirectly by pointer.
3498 if (Flags.isCopyElisionCandidate() &&
3499 VA.getLocInfo() != CCValAssign::Indirect && !ExtendedInMem &&
3500 !ScalarizedAndExtendedVector) {
3501 SDValue PartAddr;
3502 if (Ins[i].PartOffset == 0) {
3503 // If this is a one-part value or the first part of a multi-part value,
3504 // create a stack object for the entire argument value type and return a
3505 // load from our portion of it. This assumes that if the first part of an
3506 // argument is in memory, the rest will also be in memory.
3507 int FI = MFI.CreateFixedObject(ArgVT.getStoreSize(), VA.getLocMemOffset(),
3508 /*IsImmutable=*/false);
3509 PartAddr = DAG.getFrameIndex(FI, PtrVT);
3510 return DAG.getLoad(
3511 ValVT, dl, Chain, PartAddr,
3512 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI));
3513 } else {
3514 // This is not the first piece of an argument in memory. See if there is
3515 // already a fixed stack object including this offset. If so, assume it
3516 // was created by the PartOffset == 0 branch above and create a load from
3517 // the appropriate offset into it.
3518 int64_t PartBegin = VA.getLocMemOffset();
3519 int64_t PartEnd = PartBegin + ValVT.getSizeInBits() / 8;
3520 int FI = MFI.getObjectIndexBegin();
3521 for (; MFI.isFixedObjectIndex(FI); ++FI) {
3522 int64_t ObjBegin = MFI.getObjectOffset(FI);
3523 int64_t ObjEnd = ObjBegin + MFI.getObjectSize(FI);
3524 if (ObjBegin <= PartBegin && PartEnd <= ObjEnd)
3525 break;
3526 }
3527 if (MFI.isFixedObjectIndex(FI)) {
3528 SDValue Addr =
3529 DAG.getNode(ISD::ADD, dl, PtrVT, DAG.getFrameIndex(FI, PtrVT),
3530 DAG.getIntPtrConstant(Ins[i].PartOffset, dl));
3531 return DAG.getLoad(
3532 ValVT, dl, Chain, Addr,
3533 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI,
3534 Ins[i].PartOffset));
3535 }
3536 }
3537 }
3538
3539 int FI = MFI.CreateFixedObject(ValVT.getSizeInBits() / 8,
3540 VA.getLocMemOffset(), isImmutable);
3541
3542 // Set SExt or ZExt flag.
3543 if (VA.getLocInfo() == CCValAssign::ZExt) {
3544 MFI.setObjectZExt(FI, true);
3545 } else if (VA.getLocInfo() == CCValAssign::SExt) {
3546 MFI.setObjectSExt(FI, true);
3547 }
3548
3549 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3550 SDValue Val = DAG.getLoad(
3551 ValVT, dl, Chain, FIN,
3552 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI));
3553 return ExtendedInMem
3554 ? (VA.getValVT().isVector()
3555 ? DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VA.getValVT(), Val)
3556 : DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val))
3557 : Val;
3558}
3559
3560// FIXME: Get this from tablegen.
3561static ArrayRef<MCPhysReg> get64BitArgumentGPRs(CallingConv::ID CallConv,
3562 const X86Subtarget &Subtarget) {
3563 assert(Subtarget.is64Bit())(static_cast <bool> (Subtarget.is64Bit()) ? void (0) : __assert_fail
("Subtarget.is64Bit()", "/build/llvm-toolchain-snapshot-14~++20211016100712+8e1d532707fd/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 3563, __extension__ __PRETTY_FUNCTION__))
;
3564
3565 if (Subtarget.isCallingConvWin64(CallConv)) {
3566 static const MCPhysReg GPR64ArgRegsWin64[] = {
3567 X86::RCX, X86::RDX, X86::R8, X86::R9
3568 };
3569 return makeArrayRef(std::begin(GPR64ArgRegsWin64), std::end(GPR64ArgRegsWin64));
3570 }
3571
3572 static const MCPhysReg GPR64ArgRegs64Bit[] = {
3573 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
3574 };
3575 return makeArrayRef(std::begin(GPR64ArgRegs64Bit), std::end(GPR64ArgRegs64Bit));
3576}
3577
3578// FIXME: Get this from tablegen.
3579static ArrayRef<MCPhysReg> get64BitArgumentXMMs(MachineFunction &MF,
3580 CallingConv::ID CallConv,
3581 const X86Subtarget &Subtarget) {
3582 assert(Subtarget.is64Bit())(static_cast <bool> (Subtarget.is64Bit()) ? void (0) : __assert_fail
("Subtarget.is64Bit()", "/build/llvm-toolchain-snapshot-14~++20211016100712+8e1d532707fd/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 3582, __extension__ __PRETTY_FUNCTION__))
;
3583 if (Subtarget.isCallingConvWin64(CallConv)) {
3584 // The XMM registers which might contain var arg parameters are shadowed
3585 // in their paired GPR. So we only need to save the GPR to their home
3586 // slots.
3587 // TODO: __vectorcall will change this.
3588 return None;
3589 }
3590
3591 bool isSoftFloat = Subtarget.useSoftFloat();
3592 if (isSoftFloat || !Subtarget.hasSSE1())
3593 // Kernel mode asks for SSE to be disabled, so there are no XMM argument
3594 // registers.
3595 return None;
3596
3597 static const MCPhysReg XMMArgRegs64Bit[] = {
3598 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
3599 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
3600 };
3601 return makeArrayRef(std::begin(XMMArgRegs64Bit), std::end(XMMArgRegs64Bit));
3602}
3603
3604#ifndef NDEBUG
3605static bool isSortedByValueNo(ArrayRef<CCValAssign> ArgLocs) {
3606 return llvm::is_sorted(
3607 ArgLocs, [](const CCValAssign &A, const CCValAssign &B) -> bool {
3608 return A.getValNo() < B.getValNo();
3609 });
3610}
3611#endif
3612
3613namespace {
3614/// This is a helper class for lowering variable arguments parameters.
3615class VarArgsLoweringHelper {
3616public:
3617 VarArgsLoweringHelper(X86MachineFunctionInfo *FuncInfo, const SDLoc &Loc,
3618 SelectionDAG &DAG, const X86Subtarget &Subtarget,
3619 CallingConv::ID CallConv, CCState &CCInfo)
3620 : FuncInfo(FuncInfo), DL(Loc), DAG(DAG), Subtarget(Subtarget),
3621 TheMachineFunction(DAG.getMachineFunction()),
3622 TheFunction(TheMachineFunction.getFunction()),
3623 FrameInfo(TheMachineFunction.getFrameInfo()),
3624 FrameLowering(*Subtarget.getFrameLowering()),
3625 TargLowering(DAG.getTargetLoweringInfo()), CallConv(CallConv),
3626 CCInfo(CCInfo) {}
3627
3628 // Lower variable arguments parameters.
3629 void lowerVarArgsParameters(SDValue &Chain, unsigned StackSize);
3630
3631private:
3632 void createVarArgAreaAndStoreRegisters(SDValue &Chain, unsigned StackSize);
3633
3634 void forwardMustTailParameters(SDValue &Chain);
3635
3636 bool is64Bit() const { return Subtarget.is64Bit(); }
3637 bool isWin64() const { return Subtarget.isCallingConvWin64(CallConv); }
3638
3639 X86MachineFunctionInfo *FuncInfo;
3640 const SDLoc &DL;
3641 SelectionDAG &DAG;
3642 const X86Subtarget &Subtarget;
3643 MachineFunction &TheMachineFunction;
3644 const Function &TheFunction;
3645 MachineFrameInfo &FrameInfo;
3646 const TargetFrameLowering &FrameLowering;
3647 const TargetLowering &TargLowering;
3648 CallingConv::ID CallConv;
3649 CCState &CCInfo;
3650};
3651} // namespace
3652
3653void VarArgsLoweringHelper::createVarArgAreaAndStoreRegisters(
3654 SDValue &Chain, unsigned StackSize) {
3655 // If the function takes variable number of arguments, make a frame index for
3656 // the start of the first vararg value... for expansion of llvm.va_start. We
3657 // can skip this if there are no va_start calls.
3658 if (is64Bit() || (CallConv != CallingConv::X86_FastCall &&
3659 CallConv != CallingConv::X86_ThisCall)) {
3660 FuncInfo->setVarArgsFrameIndex(
3661 FrameInfo.CreateFixedObject(1, StackSize, true));
3662 }
3663
3664 // 64-bit calling conventions support varargs and register parameters, so we
3665 // have to do extra work to spill them in the prologue.
3666 if (is64Bit()) {
3667 // Find the first unallocated argument registers.
3668 ArrayRef<MCPhysReg> ArgGPRs = get64BitArgumentGPRs(CallConv, Subtarget);
3669 ArrayRef<MCPhysReg> ArgXMMs =
3670 get64BitArgumentXMMs(TheMachineFunction, CallConv, Subtarget);
3671 unsigned NumIntRegs = CCInfo.getFirstUnallocated(ArgGPRs);
3672 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(ArgXMMs);
3673
3674 assert(!(NumXMMRegs && !Subtarget.hasSSE1()) &&(static_cast <bool> (!(NumXMMRegs && !Subtarget
.hasSSE1()) && "SSE register cannot be used when SSE is disabled!"
) ? void (0) : __assert_fail ("!(NumXMMRegs && !Subtarget.hasSSE1()) && \"SSE register cannot be used when SSE is disabled!\""
, "/build/llvm-toolchain-snapshot-14~++20211016100712+8e1d532707fd/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 3675, __extension__ __PRETTY_FUNCTION__))
3675 "SSE register cannot be used when SSE is disabled!")(static_cast <bool> (!(NumXMMRegs && !Subtarget
.hasSSE1()) && "SSE register cannot be used when SSE is disabled!"
) ? void (0) : __assert_fail ("!(NumXMMRegs && !Subtarget.hasSSE1()) && \"SSE register cannot be used when SSE is disabled!\""
, "/build/llvm-toolchain-snapshot-14~++20211016100712+8e1d532707fd/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 3675, __extension__ __PRETTY_FUNCTION__))
;
3676
3677 if (isWin64()) {
3678 // Get to the caller-allocated home save location. Add 8 to account
3679 // for the return address.
3680 int HomeOffset = FrameLowering.getOffsetOfLocalArea() + 8;
3681 FuncInfo->setRegSaveFrameIndex(
3682 FrameInfo.CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
3683 // Fixup to set vararg frame on shadow area (4 x i64).
3684 if (NumIntRegs < 4)
3685 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
3686 } else {
3687 // For X86-64, if there are vararg parameters that are passed via
3688 // registers, then we must store them to their spots on the stack so
3689 // they may be loaded by dereferencing the result of va_next.
3690 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
3691 FuncInfo->setVarArgsFPOffset(ArgGPRs.size() * 8 + NumXMMRegs * 16);
3692 FuncInfo->setRegSaveFrameIndex(FrameInfo.CreateStackObject(
3693 ArgGPRs.size() * 8 + ArgXMMs.size() * 16, Align(16), false));
3694 }
3695
3696 SmallVector<SDValue, 6>
3697 LiveGPRs; // list of SDValue for GPR registers keeping live input value
3698 SmallVector<SDValue, 8> LiveXMMRegs; // list of SDValue for XMM registers
3699 // keeping live input value
3700 SDValue ALVal; // if applicable keeps SDValue for %al register
3701
3702 // Gather all the live in physical registers.
3703 for (MCPhysReg Reg : ArgGPRs.slice(NumIntRegs)) {
3704 Register GPR = TheMachineFunction.addLiveIn(Reg, &X86::GR64RegClass);
3705 LiveGPRs.push_back(DAG.getCopyFromReg(Chain, DL, GPR, MVT::i64));
3706 }
3707 const auto &AvailableXmms = ArgXMMs.slice(NumXMMRegs);
3708 if (!AvailableXmms.empty()) {
3709 Register AL = TheMachineFunction.addLiveIn(X86::AL, &X86::GR8RegClass);
3710 ALVal = DAG.getCopyFromReg(Chain, DL, AL, MVT::i8);
3711 for (MCPhysReg Reg : AvailableXmms) {
3712 // FastRegisterAllocator spills virtual registers at basic
3713 // block boundary. That leads to usages of xmm registers
3714 // outside of check for %al. Pass physical registers to
3715 // VASTART_SAVE_XMM_REGS to avoid unneccessary spilling.
3716 TheMachineFunction.getRegInfo().addLiveIn(Reg);
3717 LiveXMMRegs.push_back(DAG.getRegister(Reg, MVT::v4f32));
3718 }
3719 }
3720
3721 // Store the integer parameter registers.
3722 SmallVector<SDValue, 8> MemOps;
3723 SDValue RSFIN =
3724 DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
3725 TargLowering.getPointerTy(DAG.getDataLayout()));
3726 unsigned Offset = FuncInfo->getVarArgsGPOffset();
3727 for (SDValue Val : LiveGPRs) {
3728 SDValue FIN = DAG.getNode(ISD::ADD, DL,
3729 TargLowering.getPointerTy(DAG.getDataLayout()),
3730 RSFIN, DAG.getIntPtrConstant(Offset, DL));
3731 SDValue Store =
3732 DAG.getStore(Val.getValue(1), DL, Val, FIN,
3733 MachinePointerInfo::getFixedStack(
3734 DAG.getMachineFunction(),
3735 FuncInfo->getRegSaveFrameIndex(), Offset));
3736 MemOps.push_back(Store);
3737 Offset += 8;
3738 }
3739
3740 // Now store the XMM (fp + vector) parameter registers.
3741 if (!LiveXMMRegs.empty()) {
3742 SmallVector<SDValue, 12> SaveXMMOps;
3743 SaveXMMOps.push_back(Chain);
3744 SaveXMMOps.push_back(ALVal);
3745 SaveXMMOps.push_back(
3746 DAG.getTargetConstant(FuncInfo->getRegSaveFrameIndex(), DL, MVT::i32));
3747 SaveXMMOps.push_back(
3748 DAG.getTargetConstant(FuncInfo->getVarArgsFPOffset(), DL, MVT::i32));
3749 llvm::append_range(SaveXMMOps, LiveXMMRegs);
3750 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, DL,
3751 MVT::Other, SaveXMMOps));
3752 }
3753
3754 if (!MemOps.empty())
3755 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
3756 }
3757}
3758
3759void VarArgsLoweringHelper::forwardMustTailParameters(SDValue &Chain) {
3760 // Find the largest legal vector type.
3761 MVT VecVT = MVT::Other;
3762 // FIXME: Only some x86_32 calling conventions support AVX512.
3763 if (Subtarget.useAVX512Regs() &&
3764 (is64Bit() || (CallConv == CallingConv::X86_VectorCall ||
3765 CallConv == CallingConv::Intel_OCL_BI)))
3766 VecVT = MVT::v16f32;
3767 else if (Subtarget.hasAVX())
3768 VecVT = MVT::v8f32;
3769 else if (Subtarget.hasSSE2())
3770 VecVT = MVT::v4f32;
3771
3772 // We forward some GPRs and some vector types.
3773 SmallVector<MVT, 2> RegParmTypes;
3774 MVT IntVT = is64Bit() ? MVT::i64 : MVT::i32;
3775 RegParmTypes.push_back(IntVT);
3776 if (VecVT != MVT::Other)
3777 RegParmTypes.push_back(VecVT);
3778
3779 // Compute the set of forwarded registers. The rest are scratch.
3780 SmallVectorImpl<ForwardedRegister> &Forwards =
3781 FuncInfo->getForwardedMustTailRegParms();
3782 CCInfo.analyzeMustTailForwardedRegisters(Forwards, RegParmTypes, CC_X86);
3783
3784 // Forward AL for SysV x86_64 targets, since it is used for varargs.
3785 if (is64Bit() && !isWin64() && !CCInfo.isAllocated(X86::AL)) {
3786 Register ALVReg = TheMachineFunction.addLiveIn(X86::AL, &X86::GR8RegClass);
3787 Forwards.push_back(ForwardedRegister(ALVReg, X86::AL, MVT::i8));
3788 }
3789
3790 // Copy all forwards from physical to virtual registers.
3791 for (ForwardedRegister &FR : Forwards) {
3792 // FIXME: Can we use a less constrained schedule?
3793 SDValue RegVal = DAG.getCopyFromReg(Chain, DL, FR.VReg, FR.VT);
3794 FR.VReg = TheMachineFunction.getRegInfo().createVirtualRegister(
3795 TargLowering.getRegClassFor(FR.VT));
3796 Chain = DAG.getCopyToReg(Chain, DL, FR.VReg, RegVal);
3797 }
3798}
3799
3800void VarArgsLoweringHelper::lowerVarArgsParameters(SDValue &Chain,
3801 unsigned StackSize) {
3802 // Set FrameIndex to the 0xAAAAAAA value to mark unset state.
3803 // If necessary, it would be set into the correct value later.
3804 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
3805 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
3806
3807 if (FrameInfo.hasVAStart())
3808 createVarArgAreaAndStoreRegisters(Chain, StackSize);
3809
3810 if (FrameInfo.hasMustTailInVarArgFunc())
3811 forwardMustTailParameters(Chain);
3812}
3813
3814SDValue X86TargetLowering::LowerFormalArguments(
3815 SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
3816 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
3817 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
3818 MachineFunction &MF = DAG.getMachineFunction();
3819 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
3820
3821 const Function &F = MF.getFunction();
3822 if (F.hasExternalLinkage() && Subtarget.isTargetCygMing() &&
3823 F.getName() == "main")
3824 FuncInfo->setForceFramePointer(true);
3825
3826 MachineFrameInfo &MFI = MF.getFrameInfo();
3827 bool Is64Bit = Subtarget.is64Bit();
3828 bool IsWin64 = Subtarget.isCallingConvWin64(CallConv);
3829
3830 assert((static_cast <bool> (!(IsVarArg && canGuaranteeTCO
(CallConv)) && "Var args not supported with calling conv' regcall, fastcc, ghc or hipe"
) ? void (0) : __assert_fail ("!(IsVarArg && canGuaranteeTCO(CallConv)) && \"Var args not supported with calling conv' regcall, fastcc, ghc or hipe\""
, "/build/llvm-toolchain-snapshot-14~++20211016100712+8e1d532707fd/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 3832, __extension__ __PRETTY_FUNCTION__))
3831 !(IsVarArg && canGuaranteeTCO(CallConv)) &&(static_cast <bool> (!(IsVarArg && canGuaranteeTCO
(CallConv)) && "Var args not supported with calling conv' regcall, fastcc, ghc or hipe"
) ? void (0) : __assert_fail ("!(IsVarArg && canGuaranteeTCO(CallConv)) && \"Var args not supported with calling conv' regcall, fastcc, ghc or hipe\""
, "/build/llvm-toolchain-snapshot-14~++20211016100712+8e1d532707fd/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 3832, __extension__ __PRETTY_FUNCTION__))
3832 "Var args not supported with calling conv' regcall, fastcc, ghc or hipe")(static_cast <bool> (!(IsVarArg && canGuaranteeTCO
(CallConv)) && "Var args not supported with calling conv' regcall, fastcc, ghc or hipe"
) ? void (0) : __assert_fail ("!(IsVarArg && canGuaranteeTCO(CallConv)) && \"Var args not supported with calling conv' regcall, fastcc, ghc or hipe\""
, "/build/llvm-toolchain-snapshot-14~++20211016100712+8e1d532707fd/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 3832, __extension__ __PRETTY_FUNCTION__))
;
3833
3834 // Assign locations to all of the incoming arguments.
3835 SmallVector<CCValAssign, 16> ArgLocs;
3836 CCState CCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext());
3837
3838 // Allocate shadow area for Win64.
3839 if (IsWin64)
3840 CCInfo.AllocateStack(32, Align(8));
3841
3842 CCInfo.AnalyzeArguments(Ins, CC_X86);
3843
3844 // In vectorcall calling convention a second pass is required for the HVA
3845 // types.
3846 if (CallingConv::X86_VectorCall == CallConv) {
3847 CCInfo.AnalyzeArgumentsSecondPass(Ins, CC_X86);
3848 }
3849
3850 // The next loop assumes that the locations are in the same order of the
3851 // input arguments.
3852 assert(isSortedByValueNo(ArgLocs) &&(static_cast <bool> (isSortedByValueNo(ArgLocs) &&
"Argument Location list must be sorted before lowering") ? void
(0) : __assert_fail ("isSortedByValueNo(ArgLocs) && \"Argument Location list must be sorted before lowering\""
, "/build/llvm-toolchain-snapshot-14~++20211016100712+8e1d532707fd/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 3853, __extension__ __PRETTY_FUNCTION__))
3853 "Argument Location list must be sorted before lowering")(static_cast <bool> (isSortedByValueNo(ArgLocs) &&
"Argument Location list must be sorted before lowering") ? void
(0) : __assert_fail ("isSortedByValueNo(ArgLocs) && \"Argument Location list must be sorted before lowering\""
, "/build/llvm-toolchain-snapshot-14~++20211016100712+8e1d532707fd/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 3853, __extension__ __PRETTY_FUNCTION__))
;
3854
3855 SDValue ArgValue;
3856 for (unsigned I = 0, InsIndex = 0, E = ArgLocs.size(); I != E;
3857 ++I, ++InsIndex) {
3858 assert(InsIndex < Ins.size() && "Invalid Ins index")(static_cast <bool> (InsIndex < Ins.size() &&
"Invalid Ins index") ? void (0) : __assert_fail ("InsIndex < Ins.size() && \"Invalid Ins index\""
, "/build/llvm-toolchain-snapshot-14~++20211016100712+8e1d532707fd/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 3858, __extension__ __PRETTY_FUNCTION__))
;
3859 CCValAssign &VA = ArgLocs[I];
3860
3861 if (VA.isRegLoc()) {
3862 EVT RegVT = VA.getLocVT();
3863 if (VA.needsCustom()) {
3864 assert((static_cast <bool> (VA.getValVT() == MVT::v64i1 &&
"Currently the only custom case is when we split v64i1 to 2 regs"
) ? void (0) : __assert_fail ("VA.getValVT() == MVT::v64i1 && \"Currently the only custom case is when we split v64i1 to 2 regs\""
, "/build/llvm-toolchain-snapshot-14~++20211016100712+8e1d532707fd/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 3866, __extension__ __PRETTY_FUNCTION__))
3865 VA.getValVT() == MVT::v64i1 &&(static_cast <bool> (VA.getValVT() == MVT::v64i1 &&
"Currently the only custom case is when we split v64i1 to 2 regs"
) ? void (0) : __assert_fail ("VA.getValVT() == MVT::v64i1 && \"Currently the only custom case is when we split v64i1 to 2 regs\""
, "/build/llvm-toolchain-snapshot-14~++20211016100712+8e1d532707fd/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 3866, __extension__ __PRETTY_FUNCTION__))
3866 "Currently the only custom case is when we split v64i1 to 2 regs")(static_cast <bool> (VA.getValVT() == MVT::v64i1 &&
"Currently the only custom case is when we split v64i1 to 2 regs"
) ? void (0) : __assert_fail ("VA.getValVT() == MVT::v64i1 && \"Currently the only custom case is when we split v64i1 to 2 regs\""
, "/build/llvm-toolchain-snapshot-14~++20211016100712+8e1d532707fd/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 3866, __extension__ __PRETTY_FUNCTION__))
;
3867
3868 // v64i1 values, in regcall calling convention, that are
3869 // compiled to 32 bit arch, are split up into two registers.
3870 ArgValue =
3871 getv64i1Argument(VA, ArgLocs[++I], Chain, DAG, dl, Subtarget);
3872 } else {
3873 const TargetRegisterClass *RC;
3874 if (RegVT == MVT::i8)
3875 RC = &X86::GR8RegClass;
3876 else if (RegVT == MVT::i16)
3877 RC = &X86::GR16RegClass;
3878 else if (RegVT == MVT::i32)
3879 RC = &X86::GR32RegClass;
3880 else if (Is64Bit && RegVT == MVT::i64)
3881 RC = &X86::GR64RegClass;
3882 else if (RegVT == MVT::f16)
3883 RC = &X86::FR16XRegClass;
3884 else if (RegVT == MVT::f32)
3885 RC = Subtarget.hasAVX512() ? &X86::FR32XRegClass : &X86::FR32RegClass;
3886 else if (RegVT == MVT::f64)
3887 RC = Subtarget.hasAVX512() ? &X86::FR64XRegClass : &X86::FR64RegClass;
3888 else if (RegVT == MVT::f80)
3889 RC = &X86::RFP80RegClass;
3890 else if (RegVT == MVT::f128)
3891 RC = &X86::VR128RegClass;
3892 else if (RegVT.is512BitVector())
3893 RC = &X86::VR512RegClass;
3894 else if (RegVT.is256BitVector())
3895 RC = Subtarget.hasVLX() ? &X86::VR256XRegClass : &X86::VR256RegClass;
3896 else if (RegVT.is128BitVector())
3897 RC = Subtarget.hasVLX() ? &X86::VR128XRegClass : &X86::VR128RegClass;
3898 else if (RegVT == MVT::x86mmx)
3899 RC = &X86::VR64RegClass;
3900 else if (RegVT == MVT::v1i1)
3901 RC = &X86::VK1RegClass;
3902 else if (RegVT == MVT::v8i1)
3903 RC = &X86::VK8RegClass;
3904 else if (RegVT == MVT::v16i1)
3905 RC = &X86::VK16RegClass;
3906 else if (RegVT == MVT::v32i1)
3907 RC = &X86::VK32RegClass;
3908 else if (RegVT == MVT::v64i1)
3909 RC = &X86::VK64RegClass;
3910 else
3911 llvm_unreachable("Unknown argument type!")::llvm::llvm_unreachable_internal("Unknown argument type!", "/build/llvm-toolchain-snapshot-14~++20211016100712+8e1d532707fd/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 3911)
;
3912
3913 Register Reg = MF.addLiveIn(VA.getLocReg(), RC);
3914 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
3915 }
3916
3917 // If this is an 8 or 16-bit value, it is really passed promoted to 32
3918 // bits. Insert an assert[sz]ext to capture this, then truncate to the
3919 // right size.
3920 if (VA.getLocInfo() == CCValAssign::SExt)
3921 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
3922 DAG.getValueType(VA.getValVT()));
3923 else if (VA.getLocInfo() == CCValAssign::ZExt)
3924 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
3925 DAG.getValueType(VA.getValVT()));
3926 else if (VA.getLocInfo() == CCValAssign::BCvt)
3927 ArgValue = DAG.getBitcast(VA.getValVT(), ArgValue);
3928
3929 if (VA.isExtInLoc()) {
3930 // Handle MMX values passed in XMM regs.
3931 if (RegVT.isVector() && VA.getValVT().getScalarType() != MVT::i1)
3932 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), ArgValue);
3933 else if (VA.getValVT().isVector() &&
3934 VA.getValVT().getScalarType() == MVT::i1 &&
3935 ((VA.getLocVT() == MVT::i64) || (VA.getLocVT() == MVT::i32) ||
3936 (VA.getLocVT() == MVT::i16) || (VA.getLocVT() == MVT::i8))) {
3937 // Promoting a mask type (v*i1) into a register of type i64/i32/i16/i8
3938 ArgValue = lowerRegToMasks(ArgValue, VA.getValVT(), RegVT, dl, DAG);
3939 } else
3940 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
3941 }
3942 } else {
3943 assert(VA.isMemLoc())(static_cast <bool> (VA.isMemLoc()) ? void (0) : __assert_fail
("VA.isMemLoc()", "/build/llvm-toolchain-snapshot-14~++20211016100712+8e1d532707fd/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 3943, __extension__ __PRETTY_FUNCTION__))
;
3944 ArgValue =
3945 LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, InsIndex);
3946 }
3947
3948 // If value is passed via pointer - do a load.
3949 if (VA.getLocInfo() == CCValAssign::Indirect && !Ins[I].Flags.isByVal())
3950 ArgValue =
3951 DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue, MachinePointerInfo());
3952
3953 InVals.push_back(ArgValue);
3954 }
3955
3956 for (unsigned I = 0, E = Ins.size(); I != E; ++I) {
3957 if (Ins[I].Flags.isSwiftAsync()) {
3958 auto X86FI = MF.getInfo<X86MachineFunctionInfo>();
3959 if (Subtarget.is64Bit())
3960 X86FI->setHasSwiftAsyncContext(true);
3961 else {
3962 int FI = MF.getFrameInfo().CreateStackObject(4, Align(4), false);
3963 X86FI->setSwiftAsyncContextFrameIdx(FI);
3964 SDValue St = DAG.getStore(DAG.getEntryNode(), dl, InVals[I],
3965 DAG.getFrameIndex(FI, MVT::i32),
3966 MachinePointerInfo::getFixedStack(MF, FI));
3967 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, St, Chain);
3968 }
3969 }
3970
3971 // Swift calling convention does not require we copy the sret argument
3972 // into %rax/%eax for the return. We don't set SRetReturnReg for Swift.
3973 if (CallConv == CallingConv::Swift || CallConv == CallingConv::SwiftTail)
3974 continue;
3975
3976 // All x86 ABIs require that for returning structs by value we copy the
3977 // sret argument into %rax/%eax (depending on ABI) for the return. Save
3978 // the argument into a virtual register so that we can access it from the
3979 // return points.
3980 if (Ins[I].Flags.isSRet()) {
3981 assert(!FuncInfo->getSRetReturnReg() &&(static_cast <bool> (!FuncInfo->getSRetReturnReg() &&
"SRet return has already been set") ? void (0) : __assert_fail
("!FuncInfo->getSRetReturnReg() && \"SRet return has already been set\""
, "/build/llvm-toolchain-snapshot-14~++20211016100712+8e1d532707fd/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 3982, __extension__ __PRETTY_FUNCTION__))
3982 "SRet return has already been set")(static_cast <bool> (!FuncInfo->getSRetReturnReg() &&
"SRet return has already been set") ? void (0) : __assert_fail
("!FuncInfo->getSRetReturnReg() && \"SRet return has already been set\""
, "/build/llvm-toolchain-snapshot-14~++20211016100712+8e1d532707fd/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 3982, __extension__ __PRETTY_FUNCTION__))
;
3983 MVT PtrTy = getPointerTy(DAG.getDataLayout());
3984 Register Reg =
3985 MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy));
3986 FuncInfo->setSRetReturnReg(Reg);
3987 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[I]);
3988 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
3989 break;
3990 }
3991 }
3992
3993 unsigned StackSize = CCInfo.getNextStackOffset();
3994 // Align stack specially for tail calls.
3995 if (shouldGuaranteeTCO(CallConv,
3996 MF.getTarget().Options.GuaranteedTailCallOpt))
3997 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
3998
3999 if (IsVarArg)
4000 VarArgsLoweringHelper(FuncInfo, dl, DAG, Subtarget, CallConv, CCInfo)
4001 .lowerVarArgsParameters(Chain, StackSize);
4002
4003 // Some CCs need callee pop.
4004 if (X86::isCalleePop(CallConv, Is64Bit, IsVarArg,
4005 MF.getTarget().Options.GuaranteedTailCallOpt)) {
4006 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
4007 } else if (CallConv == CallingConv::X86_INTR && Ins.size() == 2) {
4008 // X86 interrupts must pop the error code (and the alignment padding) if
4009 // present.
4010 FuncInfo->setBytesToPopOnReturn(Is64Bit ? 16 : 4);
4011 } else {
4012 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
4013 // If this is an sret function, the return should pop the hidden pointer.
4014 if (!canGuaranteeTCO(CallConv) && hasCalleePopSRet(Ins, Subtarget))
4015 FuncInfo->setBytesToPopOnReturn(4);
4016 }
4017
4018 if (!Is64Bit) {
4019 // RegSaveFrameIndex is X86-64 only.
4020 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
4021 }
4022
4023 FuncInfo->setArgumentStackSize(StackSize);
4024
4025 if (WinEHFuncInfo *EHInfo = MF.getWinEHFuncInfo()) {
4026 EHPersonality Personality = classifyEHPersonality(F.getPersonalityFn());
4027 if (Personality == EHPersonality::CoreCLR) {
4028 assert(Is64Bit)(static_cast <bool> (Is64Bit) ? void (0) : __assert_fail
("Is64Bit", "/build/llvm-toolchain-snapshot-14~++20211016100712+8e1d532707fd/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 4028, __extension__ __PRETTY_FUNCTION__))
;
4029 // TODO: Add a mechanism to frame lowering that will allow us to indicate
4030 // that we'd prefer this slot be allocated towards the bottom of the frame
4031 // (i.e. near the stack pointer after allocating the frame). Every
4032 // funclet needs a copy of this slot in its (mostly empty) frame, and the
4033 // offset from the bottom of this and each funclet's frame must be the
4034 // same, so the size of funclets' (mostly empty) frames is dictated by
4035 // how far this slot is from the bottom (since they allocate just enough
4036 // space to accommodate holding this slot at the correct offset).
4037 int PSPSymFI = MFI.CreateStackObject(8, Align(8), /*isSpillSlot=*/false);
4038 EHInfo->PSPSymFrameIdx = PSPSymFI;
4039 }
4040 }
4041
4042 if (CallConv == CallingConv::X86_RegCall ||
4043 F.hasFnAttribute("no_caller_saved_registers")) {
4044 MachineRegisterInfo &MRI = MF.getRegInfo();
4045 for (std::pair<Register, Register> Pair : MRI.liveins())
4046 MRI.disableCalleeSavedRegister(Pair.first);
4047 }
4048
4049 return Chain;
4050}
4051
4052SDValue X86TargetLowering::LowerMemOpCallTo(SDValue Chain, SDValue StackPtr,
4053 SDValue Arg, const SDLoc &dl,
4054 SelectionDAG &DAG,
4055 const CCValAssign &VA,
4056 ISD::ArgFlagsTy Flags,
4057 bool isByVal) const {
4058 unsigned LocMemOffset = VA.getLocMemOffset();
4059 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset, dl);
4060 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(DAG.getDataLayout()),
4061 StackPtr, PtrOff);
4062 if (isByVal)
4063 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
4064
4065 return DAG.getStore(
4066 Chain, dl, Arg, PtrOff,
4067 MachinePointerInfo::getStack(DAG.getMachineFunction(), LocMemOffset));
4068}
4069
4070/// Emit a load of return address if tail call
4071/// optimization is performed and it is required.
4072SDValue X86TargetLowering::EmitTailCallLoadRetAddr(
4073 SelectionDAG &DAG, SDValue &OutRetAddr, SDValue Chain, bool IsTailCall,
4074 bool Is64Bit, int FPDiff, const SDLoc &dl) const {
4075 // Adjust the Return address stack slot.
4076 EVT VT = getPointerTy(DAG.getDataLayout());
4077 OutRetAddr = getReturnAddressFrameIndex(DAG);
4078
4079 // Load the "old" Return address.
4080 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo());
4081 return SDValue(OutRetAddr.getNode(), 1);
4082}
4083
4084/// Emit a store of the return address if tail call
4085/// optimization is performed and it is required (FPDiff!=0).
4086static SDValue EmitTailCallStoreRetAddr(SelectionDAG &DAG, MachineFunction &MF,
4087 SDValue Chain, SDValue RetAddrFrIdx,
4088 EVT PtrVT, unsigned SlotSize,
4089 int FPDiff, const SDLoc &dl) {
4090 // Store the return address to the appropriate stack slot.
4091 if (!FPDiff) return Chain;
4092 // Calculate the new stack slot for the return address.
4093 int NewReturnAddrFI =
4094 MF.getFrameInfo().CreateFixedObject(SlotSize, (int64_t)FPDiff - SlotSize,
4095 false);
4096 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, PtrVT);
4097 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
4098 MachinePointerInfo::getFixedStack(
4099 DAG.getMachineFunction(), NewReturnAddrFI));
4100 return Chain;
4101}
4102
4103/// Returns a vector_shuffle mask for an movs{s|d}, movd
4104/// operation of specified width.
4105static SDValue getMOVL(SelectionDAG &DAG, const SDLoc &dl, MVT VT, SDValue V1,
4106 SDValue V2) {
4107 unsigned NumElems = VT.getVectorNumElements();
4108 SmallVector<int, 8> Mask;
4109 Mask.push_back(NumElems);
4110 for (unsigned i = 1; i != NumElems; ++i)
4111 Mask.push_back(i);
4112 return DAG.getVectorShuffle(VT, dl, V1, V2, Mask);
4113}
4114
4115SDValue
4116X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
4117 SmallVectorImpl<SDValue> &InVals) const {
4118 SelectionDAG &DAG = CLI.DAG;
4119 SDLoc &dl = CLI.DL;
4120 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
4121 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
4122 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
4123 SDValue Chain = CLI.Chain;
4124 SDValue Callee = CLI.Callee;
4125 CallingConv::ID CallConv = CLI.CallConv;
4126 bool &isTailCall = CLI.IsTailCall;
4127 bool isVarArg = CLI.IsVarArg;
4128 const auto *CB = CLI.CB;
4129
4130 MachineFunction &MF = DAG.getMachineFunction();
4131 bool Is64Bit = Subtarget.is64Bit();
4132 bool IsWin64 = Subtarget.isCallingConvWin64(CallConv);
4133 bool IsSibcall = false;
4134 bool IsGuaranteeTCO = MF.getTarget().Options.GuaranteedTailCallOpt ||
4135 CallConv == CallingConv::Tail || CallConv == CallingConv::SwiftTail;
4136 bool IsCalleePopSRet = !IsGuaranteeTCO && hasCalleePopSRet(Outs, Subtarget);
4137 X86MachineFunctionInfo *X86Info = MF.getInfo<X86MachineFunctionInfo>();
4138 bool HasNCSR = (CB && isa<CallInst>(CB) &&
4139 CB->hasFnAttr("no_caller_saved_registers"));
4140 bool HasNoCfCheck = (CB && CB->doesNoCfCheck());
4141 bool IsIndirectCall = (CB && isa<CallInst>(CB) && CB->isIndirectCall());
4142 const Module *M = MF.getMMI().getModule();
4143 Metadata *IsCFProtectionSupported = M->getModuleFlag("cf-protection-branch");
4144
4145 MachineFunction::CallSiteInfo CSInfo;
4146 if (CallConv == CallingConv::X86_INTR)
4147 report_fatal_error("X86 interrupts may not be called directly");
4148
4149 bool IsMustTail = CLI.CB && CLI.CB->isMustTailCall();
4150 if (Subtarget.isPICStyleGOT() && !IsGuaranteeTCO && !IsMustTail) {
4151 // If we are using a GOT, disable tail calls to external symbols with
4152 // default visibility. Tail calling such a symbol requires using a GOT
4153 // relocation, which forces early binding of the symbol. This breaks code
4154 // that require lazy function symbol resolution. Using musttail or
4155 // GuaranteedTailCallOpt will override this.
4156 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
4157 if (!G || (!G->getGlobal()->hasLocalLinkage() &&
4158 G->getGlobal()->hasDefaultVisibility()))
4159 isTailCall = false;
4160 }
4161
4162 if (isTailCall && !IsMustTail) {
4163 // Check if it's really possible to do a tail call.
4164 isTailCall = IsEligibleForTailCallOptimization(
4165 Callee, CallConv, IsCalleePopSRet, isVarArg, CLI.RetTy, Outs, OutVals,
4166 Ins, DAG);
4167
4168 // Sibcalls are automatically detected tailcalls which do not require
4169 // ABI changes.
4170 if (!IsGuaranteeTCO && isTailCall)
4171 IsSibcall = true;
4172
4173 if (isTailCall)
4174 ++NumTailCalls;
4175 }
4176
4177 if (IsMustTail && !isTailCall)
4178 report_fatal_error("failed to perform tail call elimination on a call "
4179 "site marked musttail");
4180
4181 assert(!(isVarArg && canGuaranteeTCO(CallConv)) &&(static_cast <bool> (!(isVarArg && canGuaranteeTCO
(CallConv)) && "Var args not supported with calling convention fastcc, ghc or hipe"
) ? void (0) : __assert_fail ("!(isVarArg && canGuaranteeTCO(CallConv)) && \"Var args not supported with calling convention fastcc, ghc or hipe\""
, "/build/llvm-toolchain-snapshot-14~++20211016100712+8e1d532707fd/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 4182, __extension__ __PRETTY_FUNCTION__))
4182 "Var args not supported with calling convention fastcc, ghc or hipe")(static_cast <bool> (!(isVarArg && canGuaranteeTCO
(CallConv)) && "Var args not supported with calling convention fastcc, ghc or hipe"
) ? void (0) : __assert_fail ("!(isVarArg && canGuaranteeTCO(CallConv)) && \"Var args not supported with calling convention fastcc, ghc or hipe\""
, "/build/llvm-toolchain-snapshot-14~++20211016100712+8e1d532707fd/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 4182, __extension__ __PRETTY_FUNCTION__))
;
4183
4184 // Analyze operands of the call, assigning locations to each operand.
4185 SmallVector<CCValAssign, 16> ArgLocs;
4186 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
4187
4188 // Allocate shadow area for Win64.
4189 if (IsWin64)
4190 CCInfo.AllocateStack(32, Align(8));
4191
4192 CCInfo.AnalyzeArguments(Outs, CC_X86);
4193
4194 // In vectorcall calling convention a second pass is required for the HVA
4195 // types.
4196 if (CallingConv::X86_VectorCall == CallConv) {
4197 CCInfo.AnalyzeArgumentsSecondPass(Outs, CC_X86);
4198 }
4199
4200 // Get a count of how many bytes are to be pushed on the stack.
4201 unsigned NumBytes = CCInfo.getAlignedCallFrameSize();
4202 if (IsSibcall)
4203 // This is a sibcall. The memory operands are available in caller's
4204 // own caller's stack.
4205 NumBytes = 0;
4206 else if (IsGuaranteeTCO && canGuaranteeTCO(CallConv))
4207 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
4208
4209 int FPDiff = 0;
4210 if (isTailCall &&
4211 shouldGuaranteeTCO(CallConv,
4212 MF.getTarget().Options.GuaranteedTailCallOpt)) {
4213 // Lower arguments at fp - stackoffset + fpdiff.
4214 unsigned NumBytesCallerPushed = X86Info->getBytesToPopOnReturn();
4215
4216 FPDiff = NumBytesCallerPushed - NumBytes;
4217
4218 // Set the delta of movement of the returnaddr stackslot.
4219 // But only set if delta is greater than previous delta.
4220 if (FPDiff < X86Info->getTCReturnAddrDelta())
4221 X86Info->setTCReturnAddrDelta(FPDiff);
4222 }
4223
4224 unsigned NumBytesToPush = NumBytes;
4225 unsigned NumBytesToPop = NumBytes;
4226
4227 // If we have an inalloca argument, all stack space has already been allocated
4228 // for us and be right at the top of the stack. We don't support multiple
4229 // arguments passed in memory when using inalloca.
4230 if (!Outs.empty() && Outs.back().Flags.isInAlloca()) {
4231 NumBytesToPush = 0;
4232 if (!ArgLocs.back().isMemLoc())
4233 report_fatal_error("cannot use inalloca attribute on a register "
4234 "parameter");
4235 if (ArgLocs.back().getLocMemOffset() != 0)
4236 report_fatal_error("any parameter with the inalloca attribute must be "
4237 "the only memory argument");
4238 } else if (CLI.IsPreallocated) {
4239 assert(ArgLocs.back().isMemLoc() &&(static_cast <bool> (ArgLocs.back().isMemLoc() &&
"cannot use preallocated attribute on a register " "parameter"
) ? void (0) : __assert_fail ("ArgLocs.back().isMemLoc() && \"cannot use preallocated attribute on a register \" \"parameter\""
, "/build/llvm-toolchain-snapshot-14~++20211016100712+8e1d532707fd/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 4241, __extension__ __PRETTY_FUNCTION__))
4240 "cannot use preallocated attribute on a register "(static_cast <bool> (ArgLocs.back().isMemLoc() &&
"cannot use preallocated attribute on a register " "parameter"
) ? void (0) : __assert_fail ("ArgLocs.back().isMemLoc() && \"cannot use preallocated attribute on a register \" \"parameter\""
, "/build/llvm-toolchain-snapshot-14~++20211016100712+8e1d532707fd/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 4241, __extension__ __PRETTY_FUNCTION__))
4241 "parameter")(static_cast <bool> (ArgLocs.back().isMemLoc() &&
"cannot use preallocated attribute on a register " "parameter"
) ? void (0) : __assert_fail ("ArgLocs.back().isMemLoc() && \"cannot use preallocated attribute on a register \" \"parameter\""
, "/build/llvm-toolchain-snapshot-14~++20211016100712+8e1d532707fd/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 4241, __extension__ __PRETTY_FUNCTION__))
;
4242 SmallVector<size_t, 4> PreallocatedOffsets;
4243 for (size_t i = 0; i < CLI.OutVals.size(); ++i) {
4244 if (CLI.CB->paramHasAttr(i, Attribute::Preallocated)) {
4245 PreallocatedOffsets.push_back(ArgLocs[i].getLocMemOffset());
4246 }
4247 }
4248 auto *MFI = DAG.getMachineFunction().getInfo<X86MachineFunctionInfo>();
4249 size_t PreallocatedId = MFI->getPreallocatedIdForCallSite(CLI.CB);
4250 MFI->setPreallocatedStackSize(PreallocatedId, NumBytes);
4251 MFI->setPreallocatedArgOffsets(PreallocatedId, PreallocatedOffsets);
4252 NumBytesToPush = 0;
4253 }
4254
4255 if (!IsSibcall && !IsMustTail)
4256 Chain = DAG.getCALLSEQ_START(Chain, NumBytesToPush,
4257 NumBytes - NumBytesToPush, dl);
4258
4259 SDValue RetAddrFrIdx;
4260 // Load return address for tail calls.
4261 if (isTailCall && FPDiff)
4262 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
4263 Is64Bit, FPDiff, dl);
4264
4265 SmallVector<std::pair<Register, SDValue>, 8> RegsToPass;
4266 SmallVector<SDValue, 8> MemOpChains;
4267 SDValue StackPtr;
4268
4269 // The next loop assumes that the locations are in the same order of the
4270 // input arguments.
4271 assert(isSortedByValueNo(ArgLocs) &&(static_cast <bool> (isSortedByValueNo(ArgLocs) &&
"Argument Location list must be sorted before lowering") ? void
(0) : __assert_fail ("isSortedByValueNo(ArgLocs) && \"Argument Location list must be sorted before lowering\""
, "/build/llvm-toolchain-snapshot-14~++20211016100712+8e1d532707fd/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 4272, __extension__ __PRETTY_FUNCTION__))
4272 "Argument Location list must be sorted before lowering")(static_cast <bool> (isSortedByValueNo(ArgLocs) &&
"Argument Location list must be sorted before lowering") ? void
(0) : __assert_fail ("isSortedByValueNo(ArgLocs) && \"Argument Location list must be sorted before lowering\""
, "/build/llvm-toolchain-snapshot-14~++20211016100712+8e1d532707fd/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 4272, __extension__ __PRETTY_FUNCTION__))
;
4273
4274 // Walk the register/memloc assignments, inserting copies/loads. In the case
4275 // of tail call optimization arguments are handle later.
4276 const X86RegisterInfo *RegInfo = Subtarget.getRegisterInfo();
4277 for (unsigned I = 0, OutIndex = 0, E = ArgLocs.size(); I != E;
4278 ++I, ++OutIndex) {
4279 assert(OutIndex < Outs.size() && "Invalid Out index")(static_cast <bool> (OutIndex < Outs.size() &&
"Invalid Out index") ? void (0) : __assert_fail ("OutIndex < Outs.size() && \"Invalid Out index\""
, "/build/llvm-toolchain-snapshot-14~++20211016100712+8e1d532707fd/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 4279, __extension__ __PRETTY_FUNCTION__))
;
4280 // Skip inalloca/preallocated arguments, they have already been written.
4281 ISD::ArgFlagsTy Flags = Outs[OutIndex].Flags;
4282 if (Flags.isInAlloca() || Flags.isPreallocated())
4283 continue;
4284
4285 CCValAssign &VA = ArgLocs[I];
4286 EVT RegVT = VA.getLocVT();
4287 SDValue Arg = OutVals[OutIndex];
4288 bool isByVal = Flags.isByVal();
4289
4290 // Promote the value if needed.
4291 switch (VA.getLocInfo()) {
4292 default: llvm_unreachable("Unknown loc info!")::llvm::llvm_unreachable_internal("Unknown loc info!", "/build/llvm-toolchain-snapshot-14~++20211016100712+8e1d532707fd/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 4292)
;
4293 case CCValAssign::Full: break;
4294 case CCValAssign::SExt:
4295 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
4296 break;
4297 case CCValAssign::ZExt:
4298 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
4299 break;
4300 case CCValAssign::AExt:
4301 if (Arg.getValueType().isVector() &&
4302 Arg.getValueType().getVectorElementType() == MVT::i1)
4303 Arg = lowerMasksToReg(Arg, RegVT, dl, DAG);
4304 else if (RegVT.is128BitVector()) {
4305 // Special case: passing MMX values in XMM registers.
4306 Arg = DAG.getBitcast(MVT::i64, Arg);
4307 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
4308 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
4309 } else
4310 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
4311 break;
4312 case CCValAssign::BCvt:
4313 Arg = DAG.getBitcast(RegVT, Arg);
4314 break;
4315 case CCValAssign::Indirect: {
4316 if (isByVal) {
4317 // Memcpy the argument to a temporary stack slot to prevent
4318 // the caller from seeing any modifications the callee may make
4319 // as guaranteed by the `byval` attribute.
4320 int FrameIdx = MF.getFrameInfo().CreateStackObject(
4321 Flags.getByValSize(),
4322 std::max(Align(16), Flags.getNonZeroByValAlign()), false);
4323 SDValue StackSlot =
4324 DAG.getFrameIndex(FrameIdx, getPointerTy(DAG.getDataLayout()));
4325 Chain =
4326 CreateCopyOfByValArgument(Arg, StackSlot, Chain, Flags, DAG, dl);
4327 // From now on treat this as a regular pointer
4328 Arg = StackSlot;
4329 isByVal = false;
4330 } else {
4331 // Store the argument.
4332 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
4333 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
4334 Chain = DAG.getStore(
4335 Chain, dl, Arg, SpillSlot,
4336 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI));
4337 Arg = SpillSlot;
4338 }
4339 break;
4340 }
4341 }
4342
4343 if (VA.needsCustom()) {
4344 assert(VA.getValVT() == MVT::v64i1 &&(static_cast <bool> (VA.getValVT() == MVT::v64i1 &&
"Currently the only custom case is when we split v64i1 to 2 regs"
) ? void (0) : __assert_fail ("VA.getValVT() == MVT::v64i1 && \"Currently the only custom case is when we split v64i1 to 2 regs\""
, "/build/llvm-toolchain-snapshot-14~++20211016100712+8e1d532707fd/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 4345, __extension__ __PRETTY_FUNCTION__))
4345 "Currently the only custom case is when we split v64i1 to 2 regs")(static_cast <bool> (VA.getValVT() == MVT::v64i1 &&
"Currently the only custom case is when we split v64i1 to 2 regs"
) ? void (0) : __assert_fail ("VA.getValVT() == MVT::v64i1 && \"Currently the only custom case is when we split v64i1 to 2 regs\""
, "/build/llvm-toolchain-snapshot-14~++20211016100712+8e1d532707fd/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 4345, __extension__ __PRETTY_FUNCTION__))
;
4346 // Split v64i1 value into two registers
4347 Passv64i1ArgInRegs(dl, DAG, Arg, RegsToPass, VA, ArgLocs[++I], Subtarget);
4348 } else if (VA.isRegLoc()) {
4349 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
4350 const TargetOptions &Options = DAG.getTarget().Options;
4351 if (Options.EmitCallSiteInfo)
4352 CSInfo.emplace_back(VA.getLocReg(), I);
4353 if (isVarArg && IsWin64) {
4354 // Win64 ABI requires argument XMM reg to be copied to the corresponding
4355 // shadow reg if callee is a varargs function.
4356 Register ShadowReg;
4357 switch (VA.getLocReg()) {
4358 case X86::XMM0: ShadowReg = X86::RCX; break;
4359 case X86::XMM1: ShadowReg = X86::RDX; break;
4360 case X86::XMM2: ShadowReg = X86::R8; break;
4361 case X86::XMM3: ShadowReg = X86::R9; break;
4362 }
4363 if (ShadowReg)
4364 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
4365 }
4366 } else if (!IsSibcall && (!isTailCall || isByVal)) {
4367 assert(VA.isMemLoc())(static_cast <bool> (VA.isMemLoc()) ? void (0) : __assert_fail
("VA.isMemLoc()", "/build/llvm-toolchain-snapshot-14~++20211016100712+8e1d532707fd/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 4367, __extension__ __PRETTY_FUNCTION__))
;
4368 if (!StackPtr.getNode())
4369 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
4370 getPointerTy(DAG.getDataLayout()));
4371 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
4372 dl, DAG, VA, Flags, isByVal));
4373 }
4374 }
4375
4376 if (!MemOpChains.empty())
4377 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
4378
4379 if (Subtarget.isPICStyleGOT()) {
4380 // ELF / PIC requires GOT in the EBX register before function calls via PLT
4381 // GOT pointer (except regcall).
4382 if (!isTailCall) {
4383 // Indirect call with RegCall calling convertion may use up all the
4384 // general registers, so it is not suitable to bind EBX reister for
4385 // GOT address, just let register allocator handle it.
4386 if (CallConv != CallingConv::X86_RegCall)
4387 RegsToPass.push_back(std::make_pair(
4388 Register(X86::EBX), DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(),
4389 getPointerTy(DAG.getDataLayout()))));
4390 } else {
4391 // If we are tail calling and generating PIC/GOT style code load the
4392 // address of the callee into ECX. The value in ecx is used as target of
4393 // the tail jump. This is done to circumvent the ebx/callee-saved problem
4394 // for tail calls on PIC/GOT architectures. Normally we would just put the
4395 // address of GOT into ebx and then call target@PLT. But for tail calls
4396 // ebx would be restored (since ebx is callee saved) before jumping to the
4397 // target@PLT.
4398
4399 // Note: The actual moving to ECX is done further down.
4400 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
4401 if (G && !G->getGlobal()->hasLocalLinkage() &&
4402 G->getGlobal()->hasDefaultVisibility())
4403 Callee = LowerGlobalAddress(Callee, DAG);
4404 else if (isa<ExternalSymbolSDNode>(Callee))
4405 Callee = LowerExternalSymbol(Callee, DAG);
4406 }
4407 }
4408
4409 if (Is64Bit && isVarArg && !IsWin64 && !IsMustTail) {
4410 // From AMD64 ABI document:
4411 // For calls that may call functions that use varargs or stdargs
4412 // (prototype-less calls or calls to functions containing ellipsis (...) in
4413 // the declaration) %al is used as hidden argument to specify the number
4414 // of SSE registers used. The contents of %al do not need to match exactly
4415 // the number of registers, but must be an ubound on the number of SSE
4416 // registers used and is in the range 0 - 8 inclusive.
4417
4418 // Count the number of XMM registers allocated.
4419 static const MCPhysReg XMMArgRegs[] = {
4420 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
4421 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
4422 };
4423 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs);
4424 assert((Subtarget.hasSSE1() || !NumXMMRegs)(static_cast <bool> ((Subtarget.hasSSE1() || !NumXMMRegs
) && "SSE registers cannot be used when SSE is disabled"
) ? void (0) : __assert_fail ("(Subtarget.hasSSE1() || !NumXMMRegs) && \"SSE registers cannot be used when SSE is disabled\""
, "/build/llvm-toolchain-snapshot-14~++20211016100712+8e1d532707fd/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 4425, __extension__ __PRETTY_FUNCTION__))
4425 && "SSE registers cannot be used when SSE is disabled")(static_cast <bool> ((Subtarget.hasSSE1() || !NumXMMRegs
) && "SSE registers cannot be used when SSE is disabled"
) ? void (0) : __assert_fail ("(Subtarget.hasSSE1() || !NumXMMRegs) && \"SSE registers cannot be used when SSE is disabled\""
, "/build/llvm-toolchain-snapshot-14~++20211016100712+8e1d532707fd/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 4425, __extension__ __PRETTY_FUNCTION__))
;
4426 RegsToPass.push_back(std::make_pair(Register(X86::AL),
4427 DAG.getConstant(NumXMMRegs, dl,
4428 MVT::i8)));
4429 }
4430
4431 if (isVarArg && IsMustTail) {
4432 const auto &Forwards = X86Info->getForwardedMustTailRegParms();
4433 for (const auto &F : Forwards) {
4434 SDValue Val = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
4435 RegsToPass.push_back(std::make_pair(F.PReg, Val));
4436 }
4437 }
4438
4439 // For tail calls lower the arguments to the 'real' stack slots. Sibcalls
4440 // don't need this because the eligibility check rejects calls that require
4441 // shuffling arguments passed in memory.
4442 if (!IsSibcall && isTailCall) {
4443 // Force all the incoming stack arguments to be loaded from the stack
4444 // before any new outgoing arguments are stored to the stack, because the
4445 // outgoing stack slots may alias the incoming argument stack slots, and
4446 // the alias isn't otherwise explicit. This is slightly more conservative
4447 // than necessary, because it means that each store effectively depends
4448 // on every argument instead of just those arguments it would clobber.
4449 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
4450
4451 SmallVector<SDValue, 8> MemOpChains2;
4452 SDValue FIN;
4453 int FI = 0;
4454 for (unsigned I = 0, OutsIndex = 0, E = ArgLocs.size(); I != E;
4455 ++I, ++OutsIndex) {
4456 CCValAssign &VA = ArgLocs[I];
4457
4458 if (VA.isRegLoc()) {
4459 if (VA.needsCustom()) {
4460 assert((CallConv == CallingConv::X86_RegCall) &&(static_cast <bool> ((CallConv == CallingConv::X86_RegCall
) && "Expecting custom case only in regcall calling convention"
) ? void (0) : __assert_fail ("(CallConv == CallingConv::X86_RegCall) && \"Expecting custom case only in regcall calling convention\""
, "/build/llvm-toolchain-snapshot-14~++20211016100712+8e1d532707fd/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 4461, __extension__ __PRETTY_FUNCTION__))
4461 "Expecting custom case only in regcall calling convention")(static_cast <bool> ((CallConv == CallingConv::X86_RegCall
) && "Expecting custom case only in regcall calling convention"
) ? void (0) : __assert_fail ("(CallConv == CallingConv::X86_RegCall) && \"Expecting custom case only in regcall calling convention\""
, "/build/llvm-toolchain-snapshot-14~++20211016100712+8e1d532707fd/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 4461, __extension__ __PRETTY_FUNCTION__))
;
4462 // This means that we are in special case where one argument was
4463 // passed through two register locations - Skip the next location
4464 ++I;
4465 }
4466
4467 continue;
4468 }
4469
4470 assert(VA.isMemLoc())(static_cast <bool> (VA.isMemLoc()) ? void (0) : __assert_fail
("VA.isMemLoc()", "/build/llvm-toolchain-snapshot-14~++20211016100712+8e1d532707fd/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 4470, __extension__ __PRETTY_FUNCTION__))
;
4471 SDValue Arg = OutVals[OutsIndex];
4472 ISD::ArgFlagsTy Flags = Outs[OutsIndex].Flags;
4473 // Skip inalloca/preallocated arguments. They don't require any work.
4474 if (Flags.isInAlloca() || Flags.isPreallocated())
4475 continue;
4476 // Create frame index.
4477 int32_t Offset = VA.getLocMemOffset()+FPDiff;
4478 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
4479 FI = MF.getFrameInfo().CreateFixedObject(OpSize, Offset, true);
4480 FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
4481
4482 if (Flags.isByVal()) {
4483 // Copy relative to framepointer.
4484 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset(), dl);
4485 if (!StackPtr.getNode())
4486 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
4487 getPointerTy(DAG.getDataLayout()));
4488 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(DAG.getDataLayout()),
4489 StackPtr, Source);
4490
4491 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
4492 ArgChain,
4493 Flags, DAG, dl));
4494 } else {
4495 // Store relative to framepointer.
4496 MemOpChains2.push_back(DAG.getStore(
4497 ArgChain, dl, Arg, FIN,
4498 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI)));
4499 }
4500 }
4501
4502 if (!MemOpChains2.empty())
4503 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
4504
4505 // Store the return address to the appropriate stack slot.
4506 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx,
4507 getPointerTy(DAG.getDataLayout()),
4508 RegInfo->getSlotSize(), FPDiff, dl);
4509 }
4510
4511 // Build a sequence of copy-to-reg nodes chained together with token chain
4512 // and flag operands which copy the outgoing args into registers.
4513 SDValue InFlag;
4514 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
4515 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
4516 RegsToPass[i].second, InFlag);
4517 InFlag = Chain.getValue(1);
4518 }
4519
4520 if (DAG.getTarget().getCodeModel() == CodeModel::Large) {
4521 assert(Is64Bit && "Large code model is only legal in 64-bit mode.")(static_cast <bool> (Is64Bit && "Large code model is only legal in 64-bit mode."
) ? void (0) : __assert_fail ("Is64Bit && \"Large code model is only legal in 64-bit mode.\""
, "/build/llvm-toolchain-snapshot-14~++20211016100712+8e1d532707fd/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 4521, __extension__ __PRETTY_FUNCTION__))
;
4522 // In the 64-bit large code model, we have to make all calls
4523 // through a register, since the call instruction's 32-bit
4524 // pc-relative offset may not be large enough to hold the whole
4525 // address.
4526 } else if (Callee->getOpcode() == ISD::GlobalAddress ||
4527 Callee->getOpcode() == ISD::ExternalSymbol) {
4528 // Lower direct calls to global addresses and external symbols. Setting
4529 // ForCall to true here has the effect of removing WrapperRIP when possible
4530 // to allow direct calls to be selected without first materializing the
4531 // address into a register.
4532 Callee = LowerGlobalOrExternal(Callee, DAG, /*ForCall=*/true);
4533 } else if (Subtarget.isTarget64BitILP32() &&
4534 Callee->getValueType(0) == MVT::i32) {
4535 // Zero-extend the 32-bit Callee address into a 64-bit according to x32 ABI
4536 Callee = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Callee);
4537 }
4538
4539 // Returns a chain & a flag for retval copy to use.
4540 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
4541 SmallVector<SDValue, 8> Ops;
4542
4543 if (!IsSibcall && isTailCall && !IsMustTail) {
4544 Chain = DAG.getCALLSEQ_END(Chain,
4545 DAG.getIntPtrConstant(NumBytesToPop, dl, true),
4546 DAG.getIntPtrConstant(0, dl, true), InFlag, dl);
4547 InFlag = Chain.getValue(1);
4548 }
4549
4550 Ops.push_back(Chain);
4551 Ops.push_back(Callee);
4552
4553 if (isTailCall)
4554 Ops.push_back(DAG.getTargetConstant(FPDiff, dl, MVT::i32));
4555
4556 // Add argument registers to the end of the list so that they are known live
4557 // into the call.
4558 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
4559 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
4560 RegsToPass[i].second.getValueType()));
4561
4562 // Add a register mask operand representing the call-preserved registers.
4563 const uint32_t *Mask = [&]() {
4564 auto AdaptedCC = CallConv;
4565 // If HasNCSR is asserted (attribute NoCallerSavedRegisters exists),
4566 // use X86_INTR calling convention because it has the same CSR mask
4567 // (same preserved registers).
4568 if (HasNCSR)
4569 AdaptedCC = (CallingConv::ID)CallingConv::X86_INTR;
4570 // If NoCalleeSavedRegisters is requested, than use GHC since it happens
4571 // to use the CSR_NoRegs_RegMask.
4572 if (CB && CB->hasFnAttr("no_callee_saved_registers"))
4573 AdaptedCC = (CallingConv::ID)CallingConv::GHC;
4574 return RegInfo->getCallPreservedMask(MF, AdaptedCC);
4575 }();
4576 assert(Mask && "Missing call preserved mask for calling convention")(static_cast <bool> (Mask && "Missing call preserved mask for calling convention"
) ? void (0) : __assert_fail ("Mask && \"Missing call preserved mask for calling convention\""
, "/build/llvm-toolchain-snapshot-14~++20211016100712+8e1d532707fd/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 4576, __extension__ __PRETTY_FUNCTION__))
;
4577
4578 // If this is an invoke in a 32-bit function using a funclet-based
4579 // personality, assume the function clobbers all registers. If an exception
4580 // is thrown, the runtime will not restore CSRs.
4581 // FIXME: Model this more precisely so that we can register allocate across
4582 // the normal edge and spill and fill across the exceptional edge.
4583 if (!Is64Bit && CLI.CB && isa<InvokeInst>(CLI.CB)) {
4584 const Function &CallerFn = MF.getFunction();
4585 EHPersonality Pers =
4586 CallerFn.hasPersonalityFn()
4587 ? classifyEHPersonality(CallerFn.getPersonalityFn())
4588 : EHPersonality::Unknown;
4589 if (isFuncletEHPersonality(Pers))
4590 Mask = RegInfo->getNoPreservedMask();
4591 }
4592
4593 // Define a new register mask from the existing mask.
4594 uint32_t *RegMask = nullptr;
4595
4596 // In some calling conventions we need to remove the used physical registers
4597 // from the reg mask.
4598 if (CallConv == CallingConv::X86_RegCall || HasNCSR) {
4599 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
4600
4601 // Allocate a new Reg Mask and copy Mask.
4602 RegMask = MF.allocateRegMask();
4603 unsigned RegMaskSize = MachineOperand::getRegMaskSize(TRI->getNumRegs());
4604 memcpy(RegMask, Mask, sizeof(RegMask[0]) * RegMaskSize);
4605
4606 // Make sure all sub registers of the argument registers are reset
4607 // in the RegMask.
4608 for (auto const &RegPair : RegsToPass)
4609 for (MCSubRegIterator SubRegs(RegPair.first, TRI, /*IncludeSelf=*/true);
4610 SubRegs.isValid(); ++SubRegs)
4611 RegMask[*SubRegs / 32] &= ~(1u << (*SubRegs % 32));
4612
4613 // Create the RegMask Operand according to our updated mask.
4614 Ops.push_back(DAG.getRegisterMask(RegMask));
4615 } else {
4616 // Create the RegMask Operand according to the static mask.
4617 Ops.push_back(DAG.getRegisterMask(Mask));
4618 }
4619
4620 if (InFlag.getNode())
4621 Ops.push_back(InFlag);
4622
4623 if (isTailCall) {
4624 // We used to do:
4625 //// If this is the first return lowered for this function, add the regs
4626 //// to the liveout set for the function.
4627 // This isn't right, although it's probably harmless on x86; liveouts
4628 // should be computed from returns not tail calls. Consider a void
4629 // function making a tail call to a function returning int.
4630 MF.getFrameInfo().setHasTailCall();
4631 SDValue Ret = DAG.getNode(X86ISD::TC_RETURN, dl, NodeTys, Ops);
4632 DAG.addCallSiteInfo(Ret.getNode(), std::move(CSInfo));
4633 return Ret;
4634 }
4635
4636 if (HasNoCfCheck && IsCFProtectionSupported && IsIndirectCall) {
4637 Chain = DAG.getNode(X86ISD::NT_CALL, dl, NodeTys, Ops);
4638 } else if (CLI.CB && objcarc::hasAttachedCallOpBundle(CLI.CB)) {
4639 // Calls with a "clang.arc.attachedcall" bundle are special. They should be
4640 // expanded to the call, directly followed by a special marker sequence and
4641 // a call to a ObjC library function. Use the CALL_RVMARKER to do that.
4642 assert(!isTailCall &&(static_cast <bool> (!isTailCall && "tail calls cannot be marked with clang.arc.attachedcall"
) ? void (0) : __assert_fail ("!isTailCall && \"tail calls cannot be marked with clang.arc.attachedcall\""
, "/build/llvm-toolchain-snapshot-14~++20211016100712+8e1d532707fd/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 4643, __extension__ __PRETTY_FUNCTION__))
4643 "tail calls cannot be marked with clang.arc.attachedcall")(static_cast <bool> (!isTailCall && "tail calls cannot be marked with clang.arc.attachedcall"
) ? void (0) : __assert_fail ("!isTailCall && \"tail calls cannot be marked with clang.arc.attachedcall\""
, "/build/llvm-toolchain-snapshot-14~++20211016100712+8e1d532707fd/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 4643, __extension__ __PRETTY_FUNCTION__))
;
4644 assert(Is64Bit && "clang.arc.attachedcall is only supported in 64bit mode")(static_cast <bool> (Is64Bit && "clang.arc.attachedcall is only supported in 64bit mode"
) ? void (0) : __assert_fail ("Is64Bit && \"clang.arc.attachedcall is only supported in 64bit mode\""
, "/build/llvm-toolchain-snapshot-14~++20211016100712+8e1d532707fd/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 4644, __extension__ __PRETTY_FUNCTION__))
;
4645
4646 // Add a target global address for the retainRV/claimRV runtime function
4647 // just before the call target.
4648 Function *ARCFn = *objcarc::getAttachedARCFunction(CLI.CB);
4649 auto PtrVT = getPointerTy(DAG.getDataLayout());
4650 auto GA = DAG.getTargetGlobalAddress(ARCFn, dl, PtrVT);
4651 Ops.insert(Ops.begin() + 1, GA);
4652 Chain = DAG.getNode(X86ISD::CALL_RVMARKER, dl, NodeTys, Ops);
4653 } else {
4654 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, Ops);
4655 }
4656
4657 InFlag = Chain.getValue(1);
4658 DAG.addNoMergeSiteInfo(Chain.getNode(), CLI.NoMerge);
4659 DAG.addCallSiteInfo(Chain.getNode(), std::move(CSInfo));
4660
4661 // Save heapallocsite metadata.
4662 if (CLI.CB)
4663 if (MDNode *HeapAlloc = CLI.CB->getMetadata("heapallocsite"))
4664 DAG.addHeapAllocSite(Chain.getNode(), HeapAlloc);
4665
4666 // Create the CALLSEQ_END node.
4667 unsigned NumBytesForCalleeToPop = 0; // Callee pops nothing.
4668 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
4669 DAG.getTarget().Options.GuaranteedTailCallOpt))
4670 NumBytesForCalleeToPop = NumBytes; // Callee pops everything
4671 else if (!canGuaranteeTCO(CallConv) && IsCalleePopSRet)
4672 // If this call passes a struct-return pointer, the callee
4673 // pops that struct pointer.
4674 NumBytesForCalleeToPop = 4;
4675
4676 // Returns a flag for retval copy to use.
4677 if (!IsSibcall) {
4678 Chain = DAG.getCALLSEQ_END(Chain,
4679 DAG.getIntPtrConstant(NumBytesToPop, dl, true),
4680 DAG.getIntPtrConstant(NumBytesForCalleeToPop, dl,
4681 true),
4682 InFlag, dl);
4683 InFlag = Chain.getValue(1);
4684 }
4685
4686 // Handle result values, copying them out of physregs into vregs that we
4687 // return.
4688 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins, dl, DAG,
4689 InVals, RegMask);
4690}
4691
4692//===----------------------------------------------------------------------===//
4693// Fast Calling Convention (tail call) implementation
4694//===----------------------------------------------------------------------===//
4695
4696// Like std call, callee cleans arguments, convention except that ECX is
4697// reserved for storing the tail called function address. Only 2 registers are
4698// free for argument passing (inreg). Tail call optimization is performed
4699// provided:
4700// * tailcallopt is enabled
4701// * caller/callee are fastcc
4702// On X86_64 architecture with GOT-style position independent code only local
4703// (within module) calls are supported at the moment.
4704// To keep the stack aligned according to platform abi the function
4705// GetAlignedArgumentStackSize ensures that argument delta is always multiples
4706// of stack alignment. (Dynamic linkers need this - Darwin's dyld for example)
4707// If a tail called function callee has more arguments than the caller the
4708// caller needs to make sure that there is room to move the RETADDR to. This is
4709// achieved by reserving an area the size of the argument delta right after the
4710// original RETADDR, but before the saved framepointer or the spilled registers
4711// e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
4712// stack layout:
4713// arg1
4714// arg2
4715// RETADDR
4716// [ new RETADDR
4717// move area ]
4718// (possible EBP)
4719// ESI
4720// EDI
4721// local1 ..
4722
4723/// Make the stack size align e.g 16n + 12 aligned for a 16-byte align
4724/// requirement.
4725unsigned
4726X86TargetLowering::GetAlignedArgumentStackSize(const unsigned StackSize,
4727 SelectionDAG &DAG) const {
4728 const Align StackAlignment = Subtarget.getFrameLowering()->getStackAlign();
4729 const uint64_t SlotSize = Subtarget.getRegisterInfo()->getSlotSize();
4730 assert(StackSize % SlotSize == 0 &&(static_cast <bool> (StackSize % SlotSize == 0 &&
"StackSize must be a multiple of SlotSize") ? void (0) : __assert_fail
("StackSize % SlotSize == 0 && \"StackSize must be a multiple of SlotSize\""
, "/build/llvm-toolchain-snapshot-14~++20211016100712+8e1d532707fd/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 4731, __extension__ __PRETTY_FUNCTION__))
4731 "StackSize must be a multiple of SlotSize")(static_cast <bool> (StackSize % SlotSize == 0 &&
"StackSize must be a multiple of SlotSize") ? void (0) : __assert_fail
("StackSize % SlotSize == 0 && \"StackSize must be a multiple of SlotSize\""
, "/build/llvm-toolchain-snapshot-14~++20211016100712+8e1d532707fd/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 4731, __extension__ __PRETTY_FUNCTION__))
;
4732 return alignTo(StackSize + SlotSize, StackAlignment) - SlotSize;
4733}
4734
4735/// Return true if the given stack call argument is already available in the
4736/// same position (relatively) of the caller's incoming argument stack.
4737static
4738bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
4739 MachineFrameInfo &MFI, const MachineRegisterInfo *MRI,
4740 const X86InstrInfo *TII, const CCValAssign &VA) {
4741 unsigned Bytes = Arg.getValueSizeInBits() / 8;
4742
4743 for (;;) {
4744 // Look through nodes that don't alter the bits of the incoming value.
4745 unsigned Op = Arg.getOpcode();
4746 if (Op == ISD::ZERO_EXTEND || Op == ISD::ANY_EXTEND || Op == ISD::BITCAST) {
4747 Arg = Arg.getOperand(0);
4748 continue;
4749 }
4750 if (Op == ISD::TRUNCATE) {
4751 const SDValue &TruncInput = Arg.getOperand(0);
4752 if (TruncInput.getOpcode() == ISD::AssertZext &&
4753 cast<VTSDNode>(TruncInput.getOperand(1))->getVT() ==
4754 Arg.getValueType()) {
4755 Arg = TruncInput.getOperand(0);
4756 continue;
4757 }
4758 }
4759 break;
4760 }
4761
4762 int FI = INT_MAX2147483647;
4763 if (Arg.getOpcode() == ISD::CopyFromReg) {
4764 Register VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
4765 if (!VR.isVirtual())
4766 return false;
4767 MachineInstr *Def = MRI->getVRegDef(VR);
4768 if (!Def)
4769 return false;
4770 if (!Flags.isByVal()) {
4771 if (!TII->isLoadFromStackSlot(*Def, FI))
4772 return false;
4773 } else {
4774 unsigned Opcode = Def->getOpcode();
4775 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r ||
4776 Opcode == X86::LEA64_32r) &&
4777 Def->getOperand(1).isFI()) {
4778 FI = Def->getOperand(1).getIndex();
4779 Bytes = Flags.getByValSize();
4780 } else
4781 return false;
4782 }
4783 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
4784 if (Flags.isByVal())
4785 // ByVal argument is passed in as a pointer but it's now being
4786 // dereferenced. e.g.
4787 // define @foo(%struct.X* %A) {
4788 // tail call @bar(%struct.X* byval %A)
4789 // }
4790 return false;
4791 SDValue Ptr = Ld->getBasePtr();
4792 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
4793 if (!FINode)
4794 return false;
4795 FI = FINode->getIndex();
4796 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
4797 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
4798 FI = FINode->getIndex();
4799 Bytes = Flags.getByValSize();
4800 } else
4801 return false;
4802
4803 assert(FI != INT_MAX)(static_cast <bool> (FI != 2147483647) ? void (0) : __assert_fail
("FI != INT_MAX", "/build/llvm-toolchain-snapshot-14~++20211016100712+8e1d532707fd/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 4803, __extension__ __PRETTY_FUNCTION__))
;
4804 if (!MFI.isFixedObjectIndex(FI))
4805 return false;
4806
4807 if (Offset != MFI.getObjectOffset(FI))
4808 return false;
4809
4810 // If this is not byval, check that the argument stack object is immutable.
4811 // inalloca and argument copy elision can create mutable argument stack
4812 // objects. Byval objects can be mutated, but a byval call intends to pass the
4813 // mutated memory.
4814 if (!Flags.isByVal() && !MFI.isImmutableObjectIndex(FI))
4815 return false;
4816
4817 if (VA.getLocVT().getFixedSizeInBits() >
4818 Arg.getValueSizeInBits().getFixedSize()) {
4819 // If the argument location is wider than the argument type, check that any
4820 // extension flags match.
4821 if (Flags.isZExt() != MFI.isObjectZExt(FI) ||
4822 Flags.isSExt() != MFI.isObjectSExt(FI)) {
4823 return false;
4824 }
4825 }
4826
4827 return Bytes == MFI.getObjectSize(FI);
4828}
4829
4830/// Check whether the call is eligible for tail call optimization. Targets
4831/// that want to do tail call optimization should implement this function.
4832bool X86TargetLowering::IsEligibleForTailCallOptimization(
4833 SDValue Callee, CallingConv::ID CalleeCC, bool IsCalleePopSRet,
4834 bool isVarArg, Type *RetTy, const SmallVectorImpl<ISD::OutputArg> &Outs,
4835 const SmallVectorImpl<SDValue> &OutVals,
4836 const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG) const {
4837 if (!mayTailCallThisCC(CalleeCC))
4838 return false;
4839
4840 // If -tailcallopt is specified, make fastcc functions tail-callable.
4841 MachineFunction &MF = DAG.getMachineFunction();
4842 const Function &CallerF = MF.getFunction();
4843
4844 // If the function return type is x86_fp80 and the callee return type is not,
4845 // then the FP_EXTEND of the call result is not a nop. It's not safe to
4846 // perform a tailcall optimization here.
4847 if (CallerF.getReturnType()->isX86_FP80Ty() && !RetTy->isX86_FP80Ty())
4848 return false;
4849
4850 CallingConv::ID CallerCC = CallerF.getCallingConv();
4851 bool CCMatch = CallerCC == CalleeCC;
4852 bool IsCalleeWin64 = Subtarget.isCallingConvWin64(CalleeCC);
4853 bool IsCallerWin64 = Subtarget.isCallingConvWin64(CallerCC);
4854 bool IsGuaranteeTCO = DAG.getTarget().Options.GuaranteedTailCallOpt ||
4855 CalleeCC == CallingConv::Tail || CalleeCC == CallingConv::SwiftTail;
4856
4857 // Win64 functions have extra shadow space for argument homing. Don't do the
4858 // sibcall if the caller and callee have mismatched expectations for this
4859 // space.
4860 if (IsCalleeWin64 != IsCallerWin64)
4861 return false;
4862
4863 if (IsGuaranteeTCO) {
4864 if (canGuaranteeTCO(CalleeCC) && CCMatch)
4865 return true;
4866 return false;
4867 }
4868
4869 // Look for obvious safe cases to perform tail call optimization that do not
4870 // require ABI changes. This is what gcc calls sibcall.
4871
4872 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
4873 // emit a special epilogue.
4874 const X86RegisterInfo *RegInfo = Subtarget.getRegisterInfo();
4875 if (RegInfo->hasStackRealignment(MF))
4876 return false;
4877
4878 // Also avoid sibcall optimization if we're an sret return fn and the callee
4879 // is incompatible. See comment in LowerReturn about why hasStructRetAttr is
4880 // insufficient.
4881 if (MF.getInfo<X86MachineFunctionInfo>()->getSRetReturnReg()) {
4882 // For a compatible tail call the callee must return our sret pointer. So it
4883 // needs to be (a) an sret function itself and (b) we pass our sret as its
4884 // sret. Condition #b is harder to determine.
4885 return false;
4886 } else if (IsCalleePopSRet)
4887 // The callee pops an sret, so we cannot tail-call, as our caller doesn't
4888 // expect that.
4889 return false;
4890
4891 // Do not sibcall optimize vararg calls unless all arguments are passed via
4892 // registers.
4893 LLVMContext &C = *DAG.getContext();
4894 if (isVarArg && !Outs.empty()) {
4895 // Optimizing for varargs on Win64 is unlikely to be safe without
4896 // additional testing.
4897 if (IsCalleeWin64 || IsCallerWin64)
4898 return false;
4899
4900 SmallVector<CCValAssign, 16> ArgLocs;
4901 CCState CCInfo(CalleeCC, isVarArg, MF, ArgLocs, C);
4902
4903 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
4904 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
4905 if (!ArgLocs[i].isRegLoc())
4906 return false;
4907 }
4908
4909 // If the call result is in ST0 / ST1, it needs to be popped off the x87
4910 // stack. Therefore, if it's not used by the call it is not safe to optimize
4911 // this into a sibcall.
4912 bool Unused = false;
4913 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
4914 if (!Ins[i].Used) {
4915 Unused = true;
4916 break;
4917 }
4918 }
4919 if (Unused) {
4920 SmallVector<CCValAssign, 16> RVLocs;
4921 CCState CCInfo(CalleeCC, false, MF, RVLocs, C);
4922 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
4923 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
4924 CCValAssign &VA = RVLocs[i];
4925 if (VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1)
4926 return false;
4927 }
4928 }
4929
4930 // Check that the call results are passed in the same way.
4931 if (!CCState::resultsCompatible(CalleeCC, CallerCC, MF, C, Ins,
4932 RetCC_X86, RetCC_X86))
4933 return false;
4934 // The callee has to preserve all registers the caller needs to preserve.
4935 const X86RegisterInfo *TRI = Subtarget.getRegisterInfo();
4936 const uint32_t *CallerPreserved = TRI->getCallPreservedMask(MF, CallerCC);
4937 if (!CCMatch) {
4938 const uint32_t *CalleePreserved = TRI->getCallPreservedMask(MF, CalleeCC);
4939 if (!TRI->regmaskSubsetEqual(CallerPreserved, CalleePreserved))
4940 return false;
4941 }
4942
4943 unsigned StackArgsSize = 0;
4944
4945 // If the callee takes no arguments then go on to check the results of the
4946 // call.
4947 if (!Outs.empty()) {
4948 // Check if stack adjustment is needed. For now, do not do this if any
4949 // argument is passed on the stack.
4950 SmallVector<CCValAssign, 16> ArgLocs;
4951 CCState CCInfo(CalleeCC, isVarArg, MF, ArgLocs, C);
4952
4953 // Allocate shadow area for Win64
4954 if (IsCalleeWin64)
4955 CCInfo.AllocateStack(32, Align(8));
4956
4957 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
4958 StackArgsSize = CCInfo.getNextStackOffset();
4959
4960 if (CCInfo.getNextStackOffset()) {
4961 // Check if the arguments are already laid out in the right way as
4962 // the caller's fixed stack objects.
4963 MachineFrameInfo &MFI = MF.getFrameInfo();
4964 const MachineRegisterInfo *MRI = &MF.getRegInfo();
4965 const X86InstrInfo *TII = Subtarget.getInstrInfo();
4966 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
4967 CCValAssign &VA = ArgLocs[i];
4968 SDValue Arg = OutVals[i];
4969 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4970 if (VA.getLocInfo() == CCValAssign::Indirect)
4971 return false;
4972 if (!VA.isRegLoc()) {
4973 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
4974 MFI, MRI, TII, VA))
4975 return false;
4976 }
4977 }
4978 }
4979
4980 bool PositionIndependent = isPositionIndependent();
4981 // If the tailcall address may be in a register, then make sure it's
4982 // possible to register allocate for it. In 32-bit, the call address can
4983 // only target EAX, EDX, or ECX since the tail call must be scheduled after
4984 // callee-saved registers are restored. These happen to be the same
4985 // registers used to pass 'inreg' arguments so watch out for those.
4986 if (!Subtarget.is64Bit() && ((!isa<GlobalAddressSDNode>(Callee) &&
4987 !isa<ExternalSymbolSDNode>(Callee)) ||
4988 PositionIndependent)) {
4989 unsigned NumInRegs = 0;
4990 // In PIC we need an extra register to formulate the address computation
4991 // for the callee.
4992 unsigned MaxInRegs = PositionIndependent ? 2 : 3;
4993
4994 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
4995 CCValAssign &VA = ArgLocs[i];
4996 if (!VA.isRegLoc())
4997 continue;
4998 Register Reg = VA.getLocReg();
4999 switch (Reg) {
5000 default: break;
5001 case X86::EAX: case X86::EDX: case X86::ECX:
5002 if (++NumInRegs == MaxInRegs)
5003 return false;
5004 break;
5005 }
5006 }
5007 }
5008
5009 const MachineRegisterInfo &MRI = MF.getRegInfo();
5010 if (!parametersInCSRMatch(MRI, CallerPreserved, ArgLocs, OutVals))
5011 return false;
5012 }
5013
5014 bool CalleeWillPop =
5015 X86::isCalleePop(CalleeCC, Subtarget.is64Bit(), isVarArg,
5016 MF.getTarget().Options.GuaranteedTailCallOpt);
5017
5018 if (unsigned BytesToPop =
5019 MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn()) {
5020 // If we have bytes to pop, the callee must pop them.
5021 bool CalleePopMatches = CalleeWillPop && BytesToPop == StackArgsSize;
5022 if (!CalleePopMatches)
5023 return false;
5024 } else if (CalleeWillPop && StackArgsSize > 0) {
5025 // If we don't have bytes to pop, make sure the callee doesn't pop any.
5026 return false;
5027 }
5028
5029 return true;
5030}
5031
5032FastISel *
5033X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
5034 const TargetLibraryInfo *libInfo) const {
5035 return X86::createFastISel(funcInfo, libInfo);
5036}
5037
5038//===----------------------------------------------------------------------===//
5039// Other Lowering Hooks
5040//===----------------------------------------------------------------------===//
5041
5042static bool MayFoldLoad(SDValue Op, bool AssumeSingleUse = false) {
5043 return (AssumeSingleUse || Op.hasOneUse()) && ISD::isNormalLoad(Op.getNode());
5044}
5045
5046static bool MayFoldLoadIntoBroadcastFromMem(SDValue Op, MVT EltVT,
5047 bool AssumeSingleUse = false) {
5048 if (!MayFoldLoad(Op, AssumeSingleUse))
5049 return false;
5050
5051 // We can not replace a wide volatile load with a broadcast-from-memory,
5052 // because that would narrow the load, which isn't legal for volatiles.
5053 const LoadSDNode *Ld = dyn_cast<LoadSDNode>(Op.getNode());
5054 return !Ld->isVolatile() ||
5055 Ld->getValueSizeInBits(0) == EltVT.getScalarSizeInBits();
5056}
5057
5058static bool MayFoldIntoStore(SDValue Op) {
5059 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
5060}
5061
5062static bool MayFoldIntoZeroExtend(SDValue Op) {
5063 if (Op.hasOneUse()) {
5064 unsigned Opcode = Op.getNode()->use_begin()->getOpcode();
5065 return (ISD::ZERO_EXTEND == Opcode);
5066 }
5067 return false;
5068}
5069
5070static bool isTargetShuffle(unsigned Opcode) {
5071 switch(Opcode) {
5072 default: return false;
5073 case X86ISD::BLENDI:
5074 case X86ISD::PSHUFB:
5075 case X86ISD::PSHUFD:
5076 case X86ISD::PSHUFHW:
5077 case X86ISD::PSHUFLW:
5078 case X86ISD::SHUFP:
5079 case X86ISD::INSERTPS:
5080 case X86ISD::EXTRQI:
5081 case X86ISD::INSERTQI:
5082 case X86ISD::VALIGN:
5083 case X86ISD::PALIGNR:
5084 case X86ISD::VSHLDQ:
5085 case X86ISD::VSRLDQ:
5086 case X86ISD::MOVLHPS:
5087 case X86ISD::MOVHLPS:
5088 case X86ISD::MOVSHDUP:
5089 case X86ISD::MOVSLDUP:
5090 case X86ISD::MOVDDUP:
5091 case X86ISD::MOVSS:
5092 case X86ISD::MOVSD:
5093 case X86ISD::MOVSH:
5094 case X86ISD::UNPCKL:
5095 case X86ISD::UNPCKH:
5096 case X86ISD::VBROADCAST:
5097 case X86ISD::VPERMILPI:
5098 case X86ISD::VPERMILPV:
5099 case X86ISD::VPERM2X128:
5100 case X86ISD::SHUF128:
5101 case X86ISD::VPERMIL2:
5102 case X86ISD::VPERMI:
5103 case X86ISD::VPPERM:
5104 case X86ISD::VPERMV:
5105 case X86ISD::VPERMV3:
5106 case X86ISD::VZEXT_MOVL:
5107 return true;
5108 }
5109}
5110
5111static bool isTargetShuffleVariableMask(unsigned Opcode) {
5112 switch (Opcode) {
5113 default: return false;
5114 // Target Shuffles.
5115 case X86ISD::PSHUFB:
5116 case X86ISD::VPERMILPV:
5117 case X86ISD::VPERMIL2:
5118 case X86ISD::VPPERM:
5119 case X86ISD::VPERMV:
5120 case X86ISD::VPERMV3:
5121 return true;
5122 // 'Faux' Target Shuffles.
5123 case ISD::OR:
5124 case ISD::AND:
5125 case X86ISD::ANDNP:
5126 return true;
5127 }
5128}
5129
5130static bool isTargetShuffleSplat(SDValue Op) {
5131 unsigned Opcode = Op.getOpcode();
5132 if (Opcode == ISD::EXTRACT_SUBVECTOR)
5133 return isTargetShuffleSplat(Op.getOperand(0));
5134 return Opcode == X86ISD::VBROADCAST || Opcode == X86ISD::VBROADCAST_LOAD;
5135}
5136
5137SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
5138 MachineFunction &MF = DAG.getMachineFunction();
5139 const X86RegisterInfo *RegInfo = Subtarget.getRegisterInfo();
5140 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
5141 int ReturnAddrIndex = FuncInfo->getRAIndex();
5142
5143 if (ReturnAddrIndex == 0) {
5144 // Set up a frame object for the return address.
5145 unsigned SlotSize = RegInfo->getSlotSize();
5146 ReturnAddrIndex = MF.getFrameInfo().CreateFixedObject(SlotSize,
5147 -(int64_t)SlotSize,
5148 false);
5149 FuncInfo->setRAIndex(ReturnAddrIndex);
5150 }
5151
5152 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy(DAG.getDataLayout()));
5153}
5154
5155bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
5156 bool hasSymbolicDisplacement) {
5157 // Offset should fit into 32 bit immediate field.
5158 if (!isInt<32>(Offset))
5159 return false;
5160
5161 // If we don't have a symbolic displacement - we don't have any extra
5162 // restrictions.
5163 if (!hasSymbolicDisplacement)
5164 return true;
5165
5166 // FIXME: Some tweaks might be needed for medium code model.
5167 if (M != CodeModel::Small && M != CodeModel::Kernel)
5168 return false;
5169
5170 // For small code model we assume that latest object is 16MB before end of 31
5171 // bits boundary. We may also accept pretty large negative constants knowing
5172 // that all objects are in the positive half of address space.
5173 if (M == CodeModel::Small && Offset < 16*1024*1024)
5174 return true;
5175
5176 // For kernel code model we know that all object resist in the negative half
5177 // of 32bits address space. We may not accept negative offsets, since they may
5178 // be just off and we may accept pretty large positive ones.
5179 if (M == CodeModel::Kernel && Offset >= 0)
5180 return true;
5181
5182 return false;
5183}
5184
5185/// Determines whether the callee is required to pop its own arguments.
5186/// Callee pop is necessary to support tail calls.
5187bool X86::isCalleePop(CallingConv::ID CallingConv,
5188 bool is64Bit, bool IsVarArg, bool GuaranteeTCO) {
5189 // If GuaranteeTCO is true, we force some calls to be callee pop so that we
5190 // can guarantee TCO.
5191 if (!IsVarArg && shouldGuaranteeTCO(CallingConv, GuaranteeTCO))
5192 return true;
5193
5194 switch (CallingConv) {
5195 default:
5196 return false;
5197 case CallingConv::X86_StdCall:
5198 case CallingConv::X86_FastCall:
5199 case CallingConv::X86_ThisCall:
5200 case CallingConv::X86_VectorCall:
5201 return !is64Bit;
5202 }
5203}
5204
5205/// Return true if the condition is an signed comparison operation.
5206static bool isX86CCSigned(unsigned X86CC) {
5207 switch (X86CC) {
5208 default:
5209 llvm_unreachable("Invalid integer condition!")::llvm::llvm_unreachable_internal("Invalid integer condition!"
, "/build/llvm-toolchain-snapshot-14~++20211016100712+8e1d532707fd/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 5209)
;
5210 case X86::COND_E:
5211 case X86::COND_NE:
5212 case X86::COND_B:
5213 case X86::COND_A:
5214 case X86::COND_BE:
5215 case X86::COND_AE:
5216 return false;
5217 case X86::COND_G:
5218 case X86::COND_GE:
5219 case X86::COND_L:
5220 case X86::COND_LE:
5221 return true;
5222 }
5223}
5224
5225static X86::CondCode TranslateIntegerX86CC(ISD::CondCode SetCCOpcode) {
5226 switch (SetCCOpcode) {
5227 default: llvm_unreachable("Invalid integer condition!")::llvm::llvm_unreachable_internal("Invalid integer condition!"
, "/build/llvm-toolchain-snapshot-14~++20211016100712+8e1d532707fd/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 5227)
;
5228 case ISD::SETEQ: return X86::COND_E;
5229 case ISD::SETGT: return X86::COND_G;
5230 case ISD::SETGE: return X86::COND_GE;
5231 case ISD::SETLT: return X86::COND_L;
5232 case ISD::SETLE: return X86::COND_LE;
5233 case ISD::SETNE: return X86::COND_NE;
5234 case ISD::SETULT: return X86::COND_B;
5235 case ISD::SETUGT: return X86::COND_A;
5236 case ISD::SETULE: return X86::COND_BE;
5237 case ISD::SETUGE: return X86::COND_AE;
5238 }
5239}
5240
5241/// Do a one-to-one translation of a ISD::CondCode to the X86-specific
5242/// condition code, returning the condition code and the LHS/RHS of the
5243/// comparison to make.
5244static X86::CondCode TranslateX86CC(ISD::CondCode SetCCOpcode, const SDLoc &DL,
5245 bool isFP, SDValue &LHS, SDValue &RHS,
5246 SelectionDAG &DAG) {
5247 if (!isFP) {
5248 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
5249 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnes()) {
5250 // X > -1 -> X == 0, jump !sign.
5251 RHS = DAG.getConstant(0, DL, RHS.getValueType());
5252 return X86::COND_NS;
5253 }
5254 if (SetCCOpcode == ISD::SETLT && RHSC->isZero()) {
5255 // X < 0 -> X == 0, jump on sign.
5256 return X86::COND_S;
5257 }
5258 if (SetCCOpcode == ISD::SETGE && RHSC->isZero()) {
5259 // X >= 0 -> X == 0, jump on !sign.
5260 return X86::COND_NS;
5261 }
5262 if (SetCCOpcode == ISD::SETLT && RHSC->isOne()) {
5263 // X < 1 -> X <= 0
5264 RHS = DAG.getConstant(0, DL, RHS.getValueType());
5265 return X86::COND_LE;
5266 }
5267 }
5268
5269 return TranslateIntegerX86CC(SetCCOpcode);
5270 }
5271
5272 // First determine if it is required or is profitable to flip the operands.
5273
5274 // If LHS is a foldable load, but RHS is not, flip the condition.
5275 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
5276 !ISD::isNON_EXTLoad(RHS.getNode())) {
5277 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
5278 std::swap(LHS, RHS);
5279 }
5280
5281 switch (SetCCOpcode) {
5282 default: break;
5283 case ISD::SETOLT:
5284 case ISD::SETOLE:
5285 case ISD::SETUGT:
5286 case ISD::SETUGE:
5287 std::swap(LHS, RHS);
5288 break;
5289 }
5290
5291 // On a floating point condition, the flags are set as follows:
5292 // ZF PF CF op
5293 // 0 | 0 | 0 | X > Y
5294 // 0 | 0 | 1 | X < Y
5295 // 1 | 0 | 0 | X == Y
5296 // 1 | 1 | 1 | unordered
5297 switch (SetCCOpcode) {
5298 default: llvm_unreachable("Condcode should be pre-legalized away")::llvm::llvm_unreachable_internal("Condcode should be pre-legalized away"
, "/build/llvm-toolchain-snapshot-14~++20211016100712+8e1d532707fd/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 5298)
;
5299 case ISD::SETUEQ:
5300 case ISD::SETEQ: return X86::COND_E;
5301 case ISD::SETOLT: // flipped
5302 case ISD::SETOGT:
5303 case ISD::SETGT: return X86::COND_A;
5304 case ISD::SETOLE: // flipped
5305 case ISD::SETOGE:
5306 case ISD::SETGE: return X86::COND_AE;
5307 case ISD::SETUGT: // flipped
5308 case ISD::SETULT:
5309 case ISD::SETLT: return X86::COND_B;
5310 case ISD::SETUGE: // flipped
5311 case ISD::SETULE:
5312 case ISD::SETLE: return X86::COND_BE;
5313 case ISD::SETONE:
5314 case ISD::SETNE: return X86::COND_NE;
5315 case ISD::SETUO: return X86::COND_P;
5316 case ISD::SETO: return X86::COND_NP;
5317 case ISD::SETOEQ:
5318 case ISD::SETUNE: return X86::COND_INVALID;
5319 }
5320}
5321
5322/// Is there a floating point cmov for the specific X86 condition code?
5323/// Current x86 isa includes the following FP cmov instructions:
5324/// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
5325static bool hasFPCMov(unsigned X86CC) {
5326 switch (X86CC) {
5327 default:
5328 return false;
5329 case X86::COND_B:
5330 case X86::COND_BE:
5331 case X86::COND_E:
5332 case X86::COND_P:
5333 case X86::COND_A:
5334 case X86::COND_AE:
5335 case X86::COND_NE:
5336 case X86::COND_NP:
5337 return true;
5338 }
5339}
5340
5341
5342bool X86TargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
5343 const CallInst &I,
5344 MachineFunction &MF,
5345 unsigned Intrinsic) const {
5346 Info.flags = MachineMemOperand::MONone;
5347 Info.offset = 0;
5348
5349 const IntrinsicData* IntrData = getIntrinsicWithChain(Intrinsic);
5350 if (!IntrData) {
5351 switch (Intrinsic) {
5352 case Intrinsic::x86_aesenc128kl:
5353 case Intrinsic::x86_aesdec128kl:
5354 Info.opc = ISD::INTRINSIC_W_CHAIN;
5355 Info.ptrVal = I.getArgOperand(1);
5356 Info.memVT = EVT::getIntegerVT(I.getType()->getContext(), 48);
5357 Info.align = Align(1);
5358 Info.flags |= MachineMemOperand::MOLoad;
5359 return true;
5360 case Intrinsic::x86_aesenc256kl:
5361 case Intrinsic::x86_aesdec256kl:
5362 Info.opc = ISD::INTRINSIC_W_CHAIN;
5363 Info.ptrVal = I.getArgOperand(1);
5364 Info.memVT = EVT::getIntegerVT(I.getType()->getContext(), 64);
5365 Info.align = Align(1);
5366 Info.flags |= MachineMemOperand::MOLoad;
5367 return true;
5368 case Intrinsic::x86_aesencwide128kl:
5369 case Intrinsic::x86_aesdecwide128kl:
5370 Info.opc = ISD::INTRINSIC_W_CHAIN;
5371 Info.ptrVal = I.getArgOperand(0);
5372 Info.memVT = EVT::getIntegerVT(I.getType()->getContext(), 48);
5373 Info.align = Align(1);
5374 Info.flags |= MachineMemOperand::MOLoad;
5375 return true;
5376 case Intrinsic::x86_aesencwide256kl:
5377 case Intrinsic::x86_aesdecwide256kl:
5378 Info.opc = ISD::INTRINSIC_W_CHAIN;
5379 Info.ptrVal = I.getArgOperand(0);
5380 Info.memVT = EVT::getIntegerVT(I.getType()->getContext(), 64);
5381 Info.align = Align(1);
5382 Info.flags |= MachineMemOperand::MOLoad;
5383 return true;
5384 }
5385 return false;
5386 }
5387
5388 switch (IntrData->Type) {
5389 case TRUNCATE_TO_MEM_VI8:
5390 case TRUNCATE_TO_MEM_VI16:
5391 case TRUNCATE_TO_MEM_VI32: {
5392 Info.opc = ISD::INTRINSIC_VOID;
5393 Info.ptrVal = I.getArgOperand(0);
5394 MVT VT = MVT::getVT(I.getArgOperand(1)->getType());
5395 MVT ScalarVT = MVT::INVALID_SIMPLE_VALUE_TYPE;
5396 if (IntrData->Type == TRUNCATE_TO_MEM_VI8)
5397 ScalarVT = MVT::i8;
5398 else if (IntrData->Type == TRUNCATE_TO_MEM_VI16)
5399 ScalarVT = MVT::i16;
5400 else if (IntrData->Type == TRUNCATE_TO_MEM_VI32)
5401 ScalarVT = MVT::i32;
5402
5403 Info.memVT = MVT::getVectorVT(ScalarVT, VT.getVectorNumElements());
5404 Info.align = Align(1);
5405 Info.flags |= MachineMemOperand::MOStore;
5406 break;
5407 }
5408 case GATHER:
5409 case GATHER_AVX2: {
5410 Info.opc = ISD::INTRINSIC_W_CHAIN;
5411 Info.ptrVal = nullptr;
5412 MVT DataVT = MVT::getVT(I.getType());
5413 MVT IndexVT = MVT::getVT(I.getArgOperand(2)->getType());
5414 unsigned NumElts = std::min(DataVT.getVectorNumElements(),
5415 IndexVT.getVectorNumElements());
5416 Info.memVT = MVT::getVectorVT(DataVT.getVectorElementType(), NumElts);
5417 Info.align = Align(1);
5418 Info.flags |= MachineMemOperand::MOLoad;
5419 break;
5420 }
5421 case SCATTER: {
5422 Info.opc = ISD::INTRINSIC_VOID;
5423 Info.ptrVal = nullptr;
5424 MVT DataVT = MVT::getVT(I.getArgOperand(3)->getType());
5425 MVT IndexVT = MVT::getVT(I.getArgOperand(2)->getType());
5426 unsigned NumElts = std::min(DataVT.getVectorNumElements(),
5427 IndexVT.getVectorNumElements());
5428 Info.memVT = MVT::getVectorVT(DataVT.getVectorElementType(), NumElts);
5429 Info.align = Align(1);
5430 Info.flags |= MachineMemOperand::MOStore;
5431 break;
5432 }
5433 default:
5434 return false;
5435 }
5436
5437 return true;
5438}
5439
5440/// Returns true if the target can instruction select the
5441/// specified FP immediate natively. If false, the legalizer will
5442/// materialize the FP immediate as a load from a constant pool.
5443bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT,
5444 bool ForCodeSize) const {
5445 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
5446 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
5447 return true;
5448 }
5449 return false;
5450}
5451
5452bool X86TargetLowering::shouldReduceLoadWidth(SDNode *Load,
5453 ISD::LoadExtType ExtTy,
5454 EVT NewVT) const {
5455 assert(cast<LoadSDNode>(Load)->isSimple() && "illegal to narrow")(static_cast <bool> (cast<LoadSDNode>(Load)->isSimple
() && "illegal to narrow") ? void (0) : __assert_fail
("cast<LoadSDNode>(Load)->isSimple() && \"illegal to narrow\""
, "/build/llvm-toolchain-snapshot-14~++20211016100712+8e1d532707fd/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 5455, __extension__ __PRETTY_FUNCTION__))
;
5456
5457 // "ELF Handling for Thread-Local Storage" specifies that R_X86_64_GOTTPOFF
5458 // relocation target a movq or addq instruction: don't let the load shrink.
5459 SDValue BasePtr = cast<LoadSDNode>(Load)->getBasePtr();
5460 if (BasePtr.getOpcode() == X86ISD::WrapperRIP)
5461 if (const auto *GA = dyn_cast<GlobalAddressSDNode>(BasePtr.getOperand(0)))
5462 return GA->getTargetFlags() != X86II::MO_GOTTPOFF;
5463
5464 // If this is an (1) AVX vector load with (2) multiple uses and (3) all of
5465 // those uses are extracted directly into a store, then the extract + store
5466 // can be store-folded. Therefore, it's probably not worth splitting the load.
5467 EVT VT = Load->getValueType(0);
5468 if ((VT.is256BitVector() || VT.is512BitVector()) && !Load->hasOneUse()) {
5469 for (auto UI = Load->use_begin(), UE = Load->use_end(); UI != UE; ++UI) {
5470 // Skip uses of the chain value. Result 0 of the node is the load value.
5471 if (UI.getUse().getResNo() != 0)
5472 continue;
5473
5474 // If this use is not an extract + store, it's probably worth splitting.
5475 if (UI->getOpcode() != ISD::EXTRACT_SUBVECTOR || !UI->hasOneUse() ||
5476 UI->use_begin()->getOpcode() != ISD::STORE)
5477 return true;
5478 }
5479 // All non-chain uses are extract + store.
5480 return false;
5481 }
5482
5483 return true;
5484}
5485
5486/// Returns true if it is beneficial to convert a load of a constant
5487/// to just the constant itself.
5488bool X86TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
5489 Type *Ty) const {
5490 assert(Ty->isIntegerTy())(static_cast <bool> (Ty->isIntegerTy()) ? void (0) :
__assert_fail ("Ty->isIntegerTy()", "/build/llvm-toolchain-snapshot-14~++20211016100712+8e1d532707fd/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 5490, __extension__ __PRETTY_FUNCTION__))
;
5491
5492 unsigned BitSize = Ty->getPrimitiveSizeInBits();
5493 if (BitSize == 0 || BitSize > 64)
5494 return false;
5495 return true;
5496}
5497
5498bool X86TargetLowering::reduceSelectOfFPConstantLoads(EVT CmpOpVT) const {
5499 // If we are using XMM registers in the ABI and the condition of the select is
5500 // a floating-point compare and we have blendv or conditional move, then it is
5501 // cheaper to select instead of doing a cross-register move and creating a
5502 // load that depends on the compare result.
5503 bool IsFPSetCC = CmpOpVT.isFloatingPoint() && CmpOpVT != MVT::f128;
5504 return !IsFPSetCC || !Subtarget.isTarget64BitLP64() || !Subtarget.hasAVX();
5505}
5506
5507bool X86TargetLowering::convertSelectOfConstantsToMath(EVT VT) const {
5508 // TODO: It might be a win to ease or lift this restriction, but the generic
5509 // folds in DAGCombiner conflict with vector folds for an AVX512 target.
5510 if (VT.isVector() && Subtarget.hasAVX512())
5511 return false;
5512
5513 return true;
5514}
5515
5516bool X86TargetLowering::decomposeMulByConstant(LLVMContext &Context, EVT VT,
5517 SDValue C) const {
5518 // TODO: We handle scalars using custom code, but generic combining could make
5519 // that unnecessary.
5520 APInt MulC;
5521 if (!ISD::isConstantSplatVector(C.getNode(), MulC))
5522 return false;
5523
5524 // Find the type this will be legalized too. Otherwise we might prematurely
5525 // convert this to shl+add/sub and then still have to type legalize those ops.
5526 // Another choice would be to defer the decision for illegal types until
5527 // after type legalization. But constant splat vectors of i64 can't make it
5528 // through type legalization on 32-bit targets so we would need to special
5529 // case vXi64.
5530 while (getTypeAction(Context, VT) != TypeLegal)
5531 VT = getTypeToTransformTo(Context, VT);
5532
5533 // If vector multiply is legal, assume that's faster than shl + add/sub.
5534 // Multiply is a complex op with higher latency and lower throughput in
5535 // most implementations, sub-vXi32 vector multiplies are always fast,
5536 // vXi32 mustn't have a SlowMULLD implementation, and anything larger (vXi64)
5537 // is always going to be slow.
5538 unsigned EltSizeInBits = VT.getScalarSizeInBits();
5539 if (isOperationLegal(ISD::MUL, VT) && EltSizeInBits <= 32 &&
5540 (EltSizeInBits != 32 || !Subtarget.isPMULLDSlow()))
5541 return false;
5542
5543 // shl+add, shl+sub, shl+add+neg
5544 return (MulC + 1).isPowerOf2() || (MulC - 1).isPowerOf2() ||
5545 (1 - MulC).isPowerOf2() || (-(MulC + 1)).isPowerOf2();
5546}
5547
5548bool X86TargetLowering::isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
5549 unsigned Index) const {
5550 if (!isOperationLegalOrCustom(ISD::EXTRACT_SUBVECTOR, ResVT))
5551 return false;
5552
5553 // Mask vectors support all subregister combinations and operations that
5554 // extract half of vector.
5555 if (ResVT.getVectorElementType() == MVT::i1)
5556 return Index == 0 || ((ResVT.getSizeInBits() == SrcVT.getSizeInBits()*2) &&
5557 (Index == ResVT.getVectorNumElements()));
5558
5559 return (Index % ResVT.getVectorNumElements()) == 0;
5560}
5561
5562bool X86TargetLowering::shouldScalarizeBinop(SDValue VecOp) const {
5563 unsigned Opc = VecOp.getOpcode();
5564
5565 // Assume target opcodes can't be scalarized.
5566 // TODO - do we have any exceptions?
5567 if (Opc >= ISD::BUILTIN_OP_END)
5568 return false;
5569
5570 // If the vector op is not supported, try to convert to scalar.
5571 EVT VecVT = VecOp.getValueType();
5572 if (!isOperationLegalOrCustomOrPromote(Opc, VecVT))
5573 return true;
5574
5575 // If the vector op is supported, but the scalar op is not, the transform may
5576 // not be worthwhile.
5577 EVT ScalarVT = VecVT.getScalarType();
5578 return isOperationLegalOrCustomOrPromote(Opc, ScalarVT);
5579}
5580
5581bool X86TargetLowering::shouldFormOverflowOp(unsigned Opcode, EVT VT,
5582 bool) const {
5583 // TODO: Allow vectors?
5584 if (VT.isVector())
5585 return false;
5586 return VT.isSimple() || !isOperationExpand(Opcode, VT);
5587}
5588
5589bool X86TargetLowering::isCheapToSpeculateCttz() const {
5590 // Speculate cttz only if we can directly use TZCNT.
5591 return Subtarget.hasBMI();
5592}
5593
5594bool X86TargetLowering::isCheapToSpeculateCtlz() const {
5595 // Speculate ctlz only if we can directly use LZCNT.
5596 return Subtarget.hasLZCNT();
5597}
5598
5599bool X86TargetLowering::isLoadBitCastBeneficial(EVT LoadVT, EVT BitcastVT,
5600 const SelectionDAG &DAG,
5601 const MachineMemOperand &MMO) const {
5602 if (!Subtarget.hasAVX512() && !LoadVT.isVector() && BitcastVT.isVector() &&
5603 BitcastVT.getVectorElementType() == MVT::i1)
5604 return false;
5605
5606 if (!Subtarget.hasDQI() && BitcastVT == MVT::v8i1 && LoadVT == MVT::i8)
5607 return false;
5608
5609 // If both types are legal vectors, it's always ok to convert them.
5610 if (LoadVT.isVector() && BitcastVT.isVector() &&
5611 isTypeLegal(LoadVT) && isTypeLegal(BitcastVT))
5612 return true;
5613
5614 return TargetLowering::isLoadBitCastBeneficial(LoadVT, BitcastVT, DAG, MMO);
5615}
5616
5617bool X86TargetLowering::canMergeStoresTo(unsigned AddressSpace, EVT MemVT,
5618 const MachineFunction &MF) const {
5619 // Do not merge to float value size (128 bytes) if no implicit
5620 // float attribute is set.
5621 bool NoFloat = MF.getFunction().hasFnAttribute(Attribute::NoImplicitFloat);
5622
5623 if (NoFloat) {
5624 unsigned MaxIntSize = Subtarget.is64Bit() ? 64 : 32;
5625 return (MemVT.getSizeInBits() <= MaxIntSize);
5626 }
5627 // Make sure we don't merge greater than our preferred vector
5628 // width.
5629 if (MemVT.getSizeInBits() > Subtarget.getPreferVectorWidth())
5630 return false;
5631
5632 return true;
5633}
5634
5635bool X86TargetLowering::isCtlzFast() const {
5636 return Subtarget.hasFastLZCNT();
5637}
5638
5639bool X86TargetLowering::isMaskAndCmp0FoldingBeneficial(
5640 const Instruction &AndI) const {
5641 return true;
5642}
5643
5644bool X86TargetLowering::hasAndNotCompare(SDValue Y) const {
5645 EVT VT = Y.getValueType();
5646
5647 if (VT.isVector())
5648 return false;
5649
5650 if (!Subtarget.hasBMI())
5651 return false;
5652
5653 // There are only 32-bit and 64-bit forms for 'andn'.
5654 if (VT != MVT::i32 && VT != MVT::i64)
5655 return false;
5656
5657 return !isa<ConstantSDNode>(Y);
5658}
5659
5660bool X86TargetLowering::hasAndNot(SDValue Y) const {
5661 EVT VT = Y.getValueType();
5662
5663 if (!VT.isVector())
5664 return hasAndNotCompare(Y);
5665
5666 // Vector.
5667
5668 if (!Subtarget.hasSSE1() || VT.getSizeInBits() < 128)
5669 return false;
5670
5671 if (VT == MVT::v4i32)
5672 return true;
5673
5674 return Subtarget.hasSSE2();
5675}
5676
5677bool X86TargetLowering::hasBitTest(SDValue X, SDValue Y) const {
5678 return X.getValueType().isScalarInteger(); // 'bt'
5679}
5680
5681bool X86TargetLowering::
5682 shouldProduceAndByConstByHoistingConstFromShiftsLHSOfAnd(
5683 SDValue X, ConstantSDNode *XC, ConstantSDNode *CC, SDValue Y,
5684 unsigned OldShiftOpcode, unsigned NewShiftOpcode,
5685 SelectionDAG &DAG) const {
5686 // Does baseline recommend not to perform the fold by default?
5687 if (!TargetLowering::shouldProduceAndByConstByHoistingConstFromShiftsLHSOfAnd(
5688 X, XC, CC, Y, OldShiftOpcode, NewShiftOpcode, DAG))
5689 return false;
5690 // For scalars this transform is always beneficial.
5691 if (X.getValueType().isScalarInteger())
5692 return true;
5693 // If all the shift amounts are identical, then transform is beneficial even
5694 // with rudimentary SSE2 shifts.
5695 if (DAG.isSplatValue(Y, /*AllowUndefs=*/true))
5696 return true;
5697 // If we have AVX2 with it's powerful shift operations, then it's also good.
5698 if (Subtarget.hasAVX2())
5699 return true;
5700 // Pre-AVX2 vector codegen for this pattern is best for variant with 'shl'.
5701 return NewShiftOpcode == ISD::SHL;
5702}
5703
5704bool X86TargetLowering::shouldFoldConstantShiftPairToMask(
5705 const SDNode *N, CombineLevel Level) const {
5706 assert(((N->getOpcode() == ISD::SHL &&(static_cast <bool> (((N->getOpcode() == ISD::SHL &&
N->getOperand(0).getOpcode() == ISD::SRL) || (N->getOpcode
() == ISD::SRL && N->getOperand(0).getOpcode() == ISD
::SHL)) && "Expected shift-shift mask") ? void (0) : __assert_fail
("((N->getOpcode() == ISD::SHL && N->getOperand(0).getOpcode() == ISD::SRL) || (N->getOpcode() == ISD::SRL && N->getOperand(0).getOpcode() == ISD::SHL)) && \"Expected shift-shift mask\""
, "/build/llvm-toolchain-snapshot-14~++20211016100712+8e1d532707fd/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 5710, __extension__ __PRETTY_FUNCTION__))
5707 N->getOperand(0).getOpcode() == ISD::SRL) ||(static_cast <bool> (((N->getOpcode() == ISD::SHL &&
N->getOperand(0).getOpcode() == ISD::SRL) || (N->getOpcode
() == ISD::SRL && N->getOperand(0).getOpcode() == ISD
::SHL)) && "Expected shift-shift mask") ? void (0) : __assert_fail
("((N->getOpcode() == ISD::SHL && N->getOperand(0).getOpcode() == ISD::SRL) || (N->getOpcode() == ISD::SRL && N->getOperand(0).getOpcode() == ISD::SHL)) && \"Expected shift-shift mask\""
, "/build/llvm-toolchain-snapshot-14~++20211016100712+8e1d532707fd/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 5710, __extension__ __PRETTY_FUNCTION__))
5708 (N->getOpcode() == ISD::SRL &&(static_cast <bool> (((N->getOpcode() == ISD::SHL &&
N->getOperand(0).getOpcode() == ISD::SRL) || (N->getOpcode
() == ISD::SRL && N->getOperand(0).getOpcode() == ISD
::SHL)) && "Expected shift-shift mask") ? void (0) : __assert_fail
("((N->getOpcode() == ISD::SHL && N->getOperand(0).getOpcode() == ISD::SRL) || (N->getOpcode() == ISD::SRL && N->getOperand(0).getOpcode() == ISD::SHL)) && \"Expected shift-shift mask\""
, "/build/llvm-toolchain-snapshot-14~++20211016100712+8e1d532707fd/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 5710, __extension__ __PRETTY_FUNCTION__))
5709 N->getOperand(0).getOpcode() == ISD::SHL)) &&(static_cast <bool> (((N->getOpcode() == ISD::SHL &&
N->getOperand(0).getOpcode() == ISD::SRL) || (N->getOpcode
() == ISD::SRL && N->getOperand(0).getOpcode() == ISD
::SHL)) && "Expected shift-shift mask") ? void (0) : __assert_fail
("((N->getOpcode() == ISD::SHL && N->getOperand(0).getOpcode() == ISD::SRL) || (N->getOpcode() == ISD::SRL && N->getOperand(0).getOpcode() == ISD::SHL)) && \"Expected shift-shift mask\""
, "/build/llvm-toolchain-snapshot-14~++20211016100712+8e1d532707fd/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 5710, __extension__ __PRETTY_FUNCTION__))
5710 "Expected shift-shift mask")(static_cast <bool> (((N->getOpcode() == ISD::SHL &&
N->getOperand(0).getOpcode() == ISD::SRL) || (N->getOpcode
() == ISD::SRL && N->getOperand(0).getOpcode() == ISD
::SHL)) && "Expected shift-shift mask") ? void (0) : __assert_fail
("((N->getOpcode() == ISD::SHL && N->getOperand(0).getOpcode() == ISD::SRL) || (N->getOpcode() == ISD::SRL && N->getOperand(0).getOpcode() == ISD::SHL)) && \"Expected shift-shift mask\""
, "/build/llvm-toolchain-snapshot-14~++20211016100712+8e1d532707fd/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 5710, __extension__ __PRETTY_FUNCTION__))
;
5711 EVT VT = N->getValueType(0);
5712 if ((Subtarget.hasFastVectorShiftMasks() && VT.isVector()) ||
5713 (Subtarget.hasFastScalarShiftMasks() && !VT.isVector())) {
5714 // Only fold if the shift values are equal - so it folds to AND.
5715 // TODO - we should fold if either is a non-uniform vector but we don't do
5716 // the fold for non-splats yet.
5717 return N->getOperand(1) == N->getOperand(0).getOperand(1);
5718 }
5719 return TargetLoweringBase::shouldFoldConstantShiftPairToMask(N, Level);
5720}
5721
5722bool X86TargetLowering::shouldFoldMaskToVariableShiftPair(SDValue Y) const {
5723 EVT VT = Y.getValueType();
5724
5725 // For vectors, we don't have a preference, but we probably want a mask.
5726 if (VT.isVector())
5727 return false;
5728
5729 // 64-bit shifts on 32-bit targets produce really bad bloated code.
5730 if (VT == MVT::i64 && !Subtarget.is64Bit())
5731 return false;
5732
5733 return true;
5734}
5735
5736bool X86TargetLowering::shouldExpandShift(SelectionDAG &DAG,
5737 SDNode *N) const {
5738 if (DAG.getMachineFunction().getFunction().hasMinSize() &&
5739 !Subtarget.isOSWindows())
5740 return false;
5741 return true;
5742}
5743
5744bool X86TargetLowering::shouldSplatInsEltVarIndex(EVT VT) const {
5745 // Any legal vector type can be splatted more efficiently than
5746 // loading/spilling from memory.
5747 return isTypeLegal(VT);
5748}
5749
5750MVT X86TargetLowering::hasFastEqualityCompare(unsigned NumBits) const {
5751 MVT VT = MVT::getIntegerVT(NumBits);
5752 if (isTypeLegal(VT))
5753 return VT;
5754
5755 // PMOVMSKB can handle this.
5756 if (NumBits == 128 && isTypeLegal(MVT::v16i8))
5757 return MVT::v16i8;
5758
5759 // VPMOVMSKB can handle this.
5760 if (NumBits == 256 && isTypeLegal(MVT::v32i8))
5761 return MVT::v32i8;
5762
5763 // TODO: Allow 64-bit type for 32-bit target.
5764 // TODO: 512-bit types should be allowed, but make sure that those
5765 // cases are handled in combineVectorSizedSetCCEquality().
5766
5767 return MVT::INVALID_SIMPLE_VALUE_TYPE;
5768}
5769
5770/// Val is the undef sentinel value or equal to the specified value.
5771static bool isUndefOrEqual(int Val, int CmpVal) {
5772 return ((Val == SM_SentinelUndef) || (Val == CmpVal));
5773}
5774
5775/// Return true if every element in Mask is the undef sentinel value or equal to
5776/// the specified value..
5777static bool isUndefOrEqual(ArrayRef<int> Mask, int CmpVal) {
5778 return llvm::all_of(Mask, [CmpVal](int M) {
5779 return (M == SM_SentinelUndef) || (M == CmpVal);
5780 });
5781}
5782
5783/// Val is either the undef or zero sentinel value.
5784static bool isUndefOrZero(int Val) {
5785 return ((Val == SM_SentinelUndef) || (Val == SM_SentinelZero));
5786}
5787
5788/// Return true if every element in Mask, beginning from position Pos and ending
5789/// in Pos+Size is the undef sentinel value.
5790static bool isUndefInRange(ArrayRef<int> Mask, unsigned Pos, unsigned Size) {
5791 return llvm::all_of(Mask.slice(Pos, Size),
5792 [](int M) { return M == SM_SentinelUndef; });
5793}
5794
5795/// Return true if the mask creates a vector whose lower half is undefined.
5796static bool isUndefLowerHalf(ArrayRef<int> Mask) {
5797 unsigned NumElts = Mask.size();
5798 return isUndefInRange(Mask, 0, NumElts / 2);
5799}
5800
5801/// Return true if the mask creates a vector whose upper half is undefined.
5802static bool isUndefUpperHalf(ArrayRef<int> Mask) {
5803 unsigned NumElts = Mask.size();
5804 return isUndefInRange(Mask, NumElts / 2, NumElts / 2);
5805}
5806
5807/// Return true if Val falls within the specified range (L, H].
5808static bool isInRange(int Val, int Low, int Hi) {
5809 return (Val >= Low && Val < Hi);
5810}
5811
5812/// Return true if the value of any element in Mask falls within the specified
5813/// range (L, H].
5814static bool isAnyInRange(ArrayRef<int> Mask, int Low, int Hi) {
5815 return llvm::any_of(Mask, [Low, Hi](int M) { return isInRange(M, Low, Hi); });
5816}
5817
5818/// Return true if the value of any element in Mask is the zero sentinel value.
5819static bool isAnyZero(ArrayRef<int> Mask) {
5820 return llvm::any_of(Mask, [](int M) { return M == SM_SentinelZero; });
5821}
5822
5823/// Return true if the value of any element in Mask is the zero or undef
5824/// sentinel values.
5825static bool isAnyZeroOrUndef(ArrayRef<int> Mask) {
5826 return llvm::any_of(Mask, [](int M) {
5827 return M == SM_SentinelZero || M == SM_SentinelUndef;
5828 });
5829}
5830
5831/// Return true if Val is undef or if its value falls within the
5832/// specified range (L, H].
5833static bool isUndefOrInRange(int Val, int Low, int Hi) {
5834 return (Val == SM_SentinelUndef) || isInRange(Val, Low, Hi);
5835}
5836
5837/// Return true if every element in Mask is undef or if its value
5838/// falls within the specified range (L, H].
5839static bool isUndefOrInRange(ArrayRef<int> Mask, int Low, int Hi) {
5840 return llvm::all_of(
5841 Mask, [Low, Hi](int M) { return isUndefOrInRange(M, Low, Hi); });
5842}
5843
5844/// Return true if Val is undef, zero or if its value falls within the
5845/// specified range (L, H].
5846static bool isUndefOrZeroOrInRange(int Val, int Low, int Hi) {
5847 return isUndefOrZero(Val) || isInRange(Val, Low, Hi);
5848}
5849
5850/// Return true if every element in Mask is undef, zero or if its value
5851/// falls within the specified range (L, H].
5852static bool isUndefOrZeroOrInRange(ArrayRef<int> Mask, int Low, int Hi) {
5853 return llvm::all_of(
5854 Mask, [Low, Hi](int M) { return isUndefOrZeroOrInRange(M, Low, Hi); });
5855}
5856
5857/// Return true if every element in Mask, beginning
5858/// from position Pos and ending in Pos + Size, falls within the specified
5859/// sequence (Low, Low + Step, ..., Low + (Size - 1) * Step) or is undef.
5860static bool isSequentialOrUndefInRange(ArrayRef<int> Mask, unsigned Pos,
5861 unsigned Size, int Low, int Step = 1) {
5862 for (unsigned i = Pos, e = Pos + Size; i != e; ++i, Low += Step)
5863 if (!isUndefOrEqual(Mask[i], Low))
5864 return false;
5865 return true;
5866}
5867
5868/// Return true if every element in Mask, beginning
5869/// from position Pos and ending in Pos+Size, falls within the specified
5870/// sequential range (Low, Low+Size], or is undef or is zero.
5871static bool isSequentialOrUndefOrZeroInRange(ArrayRef<int> Mask, unsigned Pos,
5872 unsigned Size, int Low,
5873 int Step = 1) {
5874 for (unsigned i = Pos, e = Pos + Size; i != e; ++i, Low += Step)
5875 if (!isUndefOrZero(Mask[i]) && Mask[i] != Low)
5876 return false;
5877 return true;
5878}
5879
5880/// Return true if every element in Mask, beginning
5881/// from position Pos and ending in Pos+Size is undef or is zero.
5882static bool isUndefOrZeroInRange(ArrayRef<int> Mask, unsigned Pos,
5883 unsigned Size) {
5884 return llvm::all_of(Mask.slice(Pos, Size),
5885 [](int</