Bug Summary

File:llvm/lib/Target/X86/X86ISelLowering.cpp
Warning:line 15254, column 21
The result of the '/' expression is undefined

Annotated Source Code

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clang -cc1 -triple x86_64-pc-linux-gnu -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name X86ISelLowering.cpp -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=cplusplus -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -analyzer-config-compatibility-mode=true -mrelocation-model pic -pic-level 2 -mthread-model posix -mframe-pointer=none -fmath-errno -fno-rounding-math -masm-verbose -mconstructor-aliases -munwind-tables -target-cpu x86-64 -dwarf-column-info -fno-split-dwarf-inlining -debugger-tuning=gdb -ffunction-sections -fdata-sections -resource-dir /usr/lib/llvm-11/lib/clang/11.0.0 -D _DEBUG -D _GNU_SOURCE -D __STDC_CONSTANT_MACROS -D __STDC_FORMAT_MACROS -D __STDC_LIMIT_MACROS -I /build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/build-llvm/lib/Target/X86 -I /build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/X86 -I /build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/build-llvm/include -I /build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/include -U NDEBUG -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/x86_64-linux-gnu/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/x86_64-linux-gnu/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/c++/6.3.0/backward -internal-isystem /usr/local/include -internal-isystem /usr/lib/llvm-11/lib/clang/11.0.0/include -internal-externc-isystem /usr/include/x86_64-linux-gnu -internal-externc-isystem /include -internal-externc-isystem /usr/include -O2 -Wno-unused-parameter -Wwrite-strings -Wno-missing-field-initializers -Wno-long-long -Wno-maybe-uninitialized -Wno-comment -std=c++14 -fdeprecated-macro -fdebug-compilation-dir /build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/build-llvm/lib/Target/X86 -fdebug-prefix-map=/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347=. -ferror-limit 19 -fmessage-length 0 -fvisibility hidden -fvisibility-inlines-hidden -stack-protector 2 -fgnuc-version=4.2.1 -fobjc-runtime=gcc -fdiagnostics-show-option -vectorize-loops -vectorize-slp -analyzer-output=html -analyzer-config stable-report-filename=true -faddrsig -o /tmp/scan-build-2020-03-09-184146-41876-1 -x c++ /build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/X86/X86ISelLowering.cpp

/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/X86/X86ISelLowering.cpp

1//===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines the interfaces that X86 uses to lower LLVM code into a
10// selection DAG.
11//
12//===----------------------------------------------------------------------===//
13
14#include "X86ISelLowering.h"
15#include "Utils/X86ShuffleDecode.h"
16#include "X86CallingConv.h"
17#include "X86FrameLowering.h"
18#include "X86InstrBuilder.h"
19#include "X86IntrinsicsInfo.h"
20#include "X86MachineFunctionInfo.h"
21#include "X86TargetMachine.h"
22#include "X86TargetObjectFile.h"
23#include "llvm/ADT/SmallBitVector.h"
24#include "llvm/ADT/SmallSet.h"
25#include "llvm/ADT/Statistic.h"
26#include "llvm/ADT/StringExtras.h"
27#include "llvm/ADT/StringSwitch.h"
28#include "llvm/Analysis/BlockFrequencyInfo.h"
29#include "llvm/Analysis/EHPersonalities.h"
30#include "llvm/Analysis/ProfileSummaryInfo.h"
31#include "llvm/Analysis/VectorUtils.h"
32#include "llvm/CodeGen/IntrinsicLowering.h"
33#include "llvm/CodeGen/MachineFrameInfo.h"
34#include "llvm/CodeGen/MachineFunction.h"
35#include "llvm/CodeGen/MachineInstrBuilder.h"
36#include "llvm/CodeGen/MachineJumpTableInfo.h"
37#include "llvm/CodeGen/MachineModuleInfo.h"
38#include "llvm/CodeGen/MachineRegisterInfo.h"
39#include "llvm/CodeGen/TargetLowering.h"
40#include "llvm/CodeGen/WinEHFuncInfo.h"
41#include "llvm/IR/CallSite.h"
42#include "llvm/IR/CallingConv.h"
43#include "llvm/IR/Constants.h"
44#include "llvm/IR/DerivedTypes.h"
45#include "llvm/IR/DiagnosticInfo.h"
46#include "llvm/IR/Function.h"
47#include "llvm/IR/GlobalAlias.h"
48#include "llvm/IR/GlobalVariable.h"
49#include "llvm/IR/Instructions.h"
50#include "llvm/IR/Intrinsics.h"
51#include "llvm/MC/MCAsmInfo.h"
52#include "llvm/MC/MCContext.h"
53#include "llvm/MC/MCExpr.h"
54#include "llvm/MC/MCSymbol.h"
55#include "llvm/Support/CommandLine.h"
56#include "llvm/Support/Debug.h"
57#include "llvm/Support/ErrorHandling.h"
58#include "llvm/Support/KnownBits.h"
59#include "llvm/Support/MathExtras.h"
60#include "llvm/Target/TargetOptions.h"
61#include <algorithm>
62#include <bitset>
63#include <cctype>
64#include <numeric>
65using namespace llvm;
66
67#define DEBUG_TYPE"x86-isel" "x86-isel"
68
69STATISTIC(NumTailCalls, "Number of tail calls")static llvm::Statistic NumTailCalls = {"x86-isel", "NumTailCalls"
, "Number of tail calls"}
;
70
71static cl::opt<int> ExperimentalPrefLoopAlignment(
72 "x86-experimental-pref-loop-alignment", cl::init(4),
73 cl::desc(
74 "Sets the preferable loop alignment for experiments (as log2 bytes)"
75 "(the last x86-experimental-pref-loop-alignment bits"
76 " of the loop header PC will be 0)."),
77 cl::Hidden);
78
79// Added in 10.0.
80static cl::opt<bool> EnableOldKNLABI(
81 "x86-enable-old-knl-abi", cl::init(false),
82 cl::desc("Enables passing v32i16 and v64i8 in 2 YMM registers instead of "
83 "one ZMM register on AVX512F, but not AVX512BW targets."),
84 cl::Hidden);
85
86static cl::opt<bool> MulConstantOptimization(
87 "mul-constant-optimization", cl::init(true),
88 cl::desc("Replace 'mul x, Const' with more effective instructions like "
89 "SHIFT, LEA, etc."),
90 cl::Hidden);
91
92static cl::opt<bool> ExperimentalUnorderedISEL(
93 "x86-experimental-unordered-atomic-isel", cl::init(false),
94 cl::desc("Use LoadSDNode and StoreSDNode instead of "
95 "AtomicSDNode for unordered atomic loads and "
96 "stores respectively."),
97 cl::Hidden);
98
99/// Call this when the user attempts to do something unsupported, like
100/// returning a double without SSE2 enabled on x86_64. This is not fatal, unlike
101/// report_fatal_error, so calling code should attempt to recover without
102/// crashing.
103static void errorUnsupported(SelectionDAG &DAG, const SDLoc &dl,
104 const char *Msg) {
105 MachineFunction &MF = DAG.getMachineFunction();
106 DAG.getContext()->diagnose(
107 DiagnosticInfoUnsupported(MF.getFunction(), Msg, dl.getDebugLoc()));
108}
109
110X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
111 const X86Subtarget &STI)
112 : TargetLowering(TM), Subtarget(STI) {
113 bool UseX87 = !Subtarget.useSoftFloat() && Subtarget.hasX87();
114 X86ScalarSSEf64 = Subtarget.hasSSE2();
115 X86ScalarSSEf32 = Subtarget.hasSSE1();
116 MVT PtrVT = MVT::getIntegerVT(TM.getPointerSizeInBits(0));
117
118 // Set up the TargetLowering object.
119
120 // X86 is weird. It always uses i8 for shift amounts and setcc results.
121 setBooleanContents(ZeroOrOneBooleanContent);
122 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
123 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
124
125 // For 64-bit, since we have so many registers, use the ILP scheduler.
126 // For 32-bit, use the register pressure specific scheduling.
127 // For Atom, always use ILP scheduling.
128 if (Subtarget.isAtom())
129 setSchedulingPreference(Sched::ILP);
130 else if (Subtarget.is64Bit())
131 setSchedulingPreference(Sched::ILP);
132 else
133 setSchedulingPreference(Sched::RegPressure);
134 const X86RegisterInfo *RegInfo = Subtarget.getRegisterInfo();
135 setStackPointerRegisterToSaveRestore(RegInfo->getStackRegister());
136
137 // Bypass expensive divides and use cheaper ones.
138 if (TM.getOptLevel() >= CodeGenOpt::Default) {
139 if (Subtarget.hasSlowDivide32())
140 addBypassSlowDiv(32, 8);
141 if (Subtarget.hasSlowDivide64() && Subtarget.is64Bit())
142 addBypassSlowDiv(64, 32);
143 }
144
145 if (Subtarget.isTargetWindowsMSVC() ||
146 Subtarget.isTargetWindowsItanium()) {
147 // Setup Windows compiler runtime calls.
148 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
149 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
150 setLibcallName(RTLIB::SREM_I64, "_allrem");
151 setLibcallName(RTLIB::UREM_I64, "_aullrem");
152 setLibcallName(RTLIB::MUL_I64, "_allmul");
153 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
154 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
155 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
156 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
157 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
158 }
159
160 if (Subtarget.getTargetTriple().isOSMSVCRT()) {
161 // MSVCRT doesn't have powi; fall back to pow
162 setLibcallName(RTLIB::POWI_F32, nullptr);
163 setLibcallName(RTLIB::POWI_F64, nullptr);
164 }
165
166 // If we don't have cmpxchg8b(meaing this is a 386/486), limit atomic size to
167 // 32 bits so the AtomicExpandPass will expand it so we don't need cmpxchg8b.
168 // FIXME: Should we be limiting the atomic size on other configs? Default is
169 // 1024.
170 if (!Subtarget.hasCmpxchg8b())
171 setMaxAtomicSizeInBitsSupported(32);
172
173 // Set up the register classes.
174 addRegisterClass(MVT::i8, &X86::GR8RegClass);
175 addRegisterClass(MVT::i16, &X86::GR16RegClass);
176 addRegisterClass(MVT::i32, &X86::GR32RegClass);
177 if (Subtarget.is64Bit())
178 addRegisterClass(MVT::i64, &X86::GR64RegClass);
179
180 for (MVT VT : MVT::integer_valuetypes())
181 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
182
183 // We don't accept any truncstore of integer registers.
184 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
185 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
186 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
187 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
188 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
189 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
190
191 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
192
193 // SETOEQ and SETUNE require checking two conditions.
194 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
195 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
196 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
197 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
198 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
199 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
200
201 // Integer absolute.
202 if (Subtarget.hasCMov()) {
203 setOperationAction(ISD::ABS , MVT::i16 , Custom);
204 setOperationAction(ISD::ABS , MVT::i32 , Custom);
205 }
206 setOperationAction(ISD::ABS , MVT::i64 , Custom);
207
208 // Funnel shifts.
209 for (auto ShiftOp : {ISD::FSHL, ISD::FSHR}) {
210 setOperationAction(ShiftOp , MVT::i16 , Custom);
211 setOperationAction(ShiftOp , MVT::i32 , Custom);
212 if (Subtarget.is64Bit())
213 setOperationAction(ShiftOp , MVT::i64 , Custom);
214 }
215
216 if (!Subtarget.useSoftFloat()) {
217 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
218 // operation.
219 setOperationAction(ISD::UINT_TO_FP, MVT::i8, Promote);
220 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::i8, Promote);
221 setOperationAction(ISD::UINT_TO_FP, MVT::i16, Promote);
222 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::i16, Promote);
223 // We have an algorithm for SSE2, and we turn this into a 64-bit
224 // FILD or VCVTUSI2SS/SD for other targets.
225 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
226 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::i32, Custom);
227 // We have an algorithm for SSE2->double, and we turn this into a
228 // 64-bit FILD followed by conditional FADD for other targets.
229 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
230 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::i64, Custom);
231
232 // Promote i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
233 // this operation.
234 setOperationAction(ISD::SINT_TO_FP, MVT::i8, Promote);
235 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::i8, Promote);
236 // SSE has no i16 to fp conversion, only i32. We promote in the handler
237 // to allow f80 to use i16 and f64 to use i16 with sse1 only
238 setOperationAction(ISD::SINT_TO_FP, MVT::i16, Custom);
239 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::i16, Custom);
240 // f32 and f64 cases are Legal with SSE1/SSE2, f80 case is not
241 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
242 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::i32, Custom);
243 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
244 // are Legal, f80 is custom lowered.
245 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
246 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::i64, Custom);
247
248 // Promote i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
249 // this operation.
250 setOperationAction(ISD::FP_TO_SINT, MVT::i8, Promote);
251 // FIXME: This doesn't generate invalid exception when it should. PR44019.
252 setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::i8, Promote);
253 setOperationAction(ISD::FP_TO_SINT, MVT::i16, Custom);
254 setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::i16, Custom);
255 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
256 setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::i32, Custom);
257 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
258 // are Legal, f80 is custom lowered.
259 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
260 setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::i64, Custom);
261
262 // Handle FP_TO_UINT by promoting the destination to a larger signed
263 // conversion.
264 setOperationAction(ISD::FP_TO_UINT, MVT::i8, Promote);
265 // FIXME: This doesn't generate invalid exception when it should. PR44019.
266 setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::i8, Promote);
267 setOperationAction(ISD::FP_TO_UINT, MVT::i16, Promote);
268 // FIXME: This doesn't generate invalid exception when it should. PR44019.
269 setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::i16, Promote);
270 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
271 setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::i32, Custom);
272 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
273 setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::i64, Custom);
274
275 setOperationAction(ISD::LRINT, MVT::f32, Custom);
276 setOperationAction(ISD::LRINT, MVT::f64, Custom);
277 setOperationAction(ISD::LLRINT, MVT::f32, Custom);
278 setOperationAction(ISD::LLRINT, MVT::f64, Custom);
279
280 if (!Subtarget.is64Bit()) {
281 setOperationAction(ISD::LRINT, MVT::i64, Custom);
282 setOperationAction(ISD::LLRINT, MVT::i64, Custom);
283 }
284 }
285
286 // Handle address space casts between mixed sized pointers.
287 setOperationAction(ISD::ADDRSPACECAST, MVT::i32, Custom);
288 setOperationAction(ISD::ADDRSPACECAST, MVT::i64, Custom);
289
290 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
291 if (!X86ScalarSSEf64) {
292 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
293 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
294 if (Subtarget.is64Bit()) {
295 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
296 // Without SSE, i64->f64 goes through memory.
297 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
298 }
299 } else if (!Subtarget.is64Bit())
300 setOperationAction(ISD::BITCAST , MVT::i64 , Custom);
301
302 // Scalar integer divide and remainder are lowered to use operations that
303 // produce two results, to match the available instructions. This exposes
304 // the two-result form to trivial CSE, which is able to combine x/y and x%y
305 // into a single instruction.
306 //
307 // Scalar integer multiply-high is also lowered to use two-result
308 // operations, to match the available instructions. However, plain multiply
309 // (low) operations are left as Legal, as there are single-result
310 // instructions for this in x86. Using the two-result multiply instructions
311 // when both high and low results are needed must be arranged by dagcombine.
312 for (auto VT : { MVT::i8, MVT::i16, MVT::i32, MVT::i64 }) {
313 setOperationAction(ISD::MULHS, VT, Expand);
314 setOperationAction(ISD::MULHU, VT, Expand);
315 setOperationAction(ISD::SDIV, VT, Expand);
316 setOperationAction(ISD::UDIV, VT, Expand);
317 setOperationAction(ISD::SREM, VT, Expand);
318 setOperationAction(ISD::UREM, VT, Expand);
319 }
320
321 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
322 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
323 for (auto VT : { MVT::f32, MVT::f64, MVT::f80, MVT::f128,
324 MVT::i8, MVT::i16, MVT::i32, MVT::i64 }) {
325 setOperationAction(ISD::BR_CC, VT, Expand);
326 setOperationAction(ISD::SELECT_CC, VT, Expand);
327 }
328 if (Subtarget.is64Bit())
329 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
330 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
331 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
332 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
333
334 setOperationAction(ISD::FREM , MVT::f32 , Expand);
335 setOperationAction(ISD::FREM , MVT::f64 , Expand);
336 setOperationAction(ISD::FREM , MVT::f80 , Expand);
337 setOperationAction(ISD::FREM , MVT::f128 , Expand);
338 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
339
340 // Promote the i8 variants and force them on up to i32 which has a shorter
341 // encoding.
342 setOperationPromotedToType(ISD::CTTZ , MVT::i8 , MVT::i32);
343 setOperationPromotedToType(ISD::CTTZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
344 if (!Subtarget.hasBMI()) {
345 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
346 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
347 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Legal);
348 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Legal);
349 if (Subtarget.is64Bit()) {
350 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
351 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Legal);
352 }
353 }
354
355 if (Subtarget.hasLZCNT()) {
356 // When promoting the i8 variants, force them to i32 for a shorter
357 // encoding.
358 setOperationPromotedToType(ISD::CTLZ , MVT::i8 , MVT::i32);
359 setOperationPromotedToType(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
360 } else {
361 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
362 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
363 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
364 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
365 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
366 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
367 if (Subtarget.is64Bit()) {
368 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
369 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
370 }
371 }
372
373 // Special handling for half-precision floating point conversions.
374 // If we don't have F16C support, then lower half float conversions
375 // into library calls.
376 if (!Subtarget.useSoftFloat() && Subtarget.hasF16C()) {
377 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Custom);
378 setOperationAction(ISD::STRICT_FP16_TO_FP, MVT::f32, Custom);
379 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Custom);
380 setOperationAction(ISD::STRICT_FP_TO_FP16, MVT::f32, Custom);
381 } else {
382 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
383 setOperationAction(ISD::STRICT_FP16_TO_FP, MVT::f32, Expand);
384 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
385 setOperationAction(ISD::STRICT_FP_TO_FP16, MVT::f32, Expand);
386 }
387
388 // There's never any support for operations beyond MVT::f32.
389 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
390 setOperationAction(ISD::FP16_TO_FP, MVT::f80, Expand);
391 setOperationAction(ISD::FP16_TO_FP, MVT::f128, Expand);
392 setOperationAction(ISD::STRICT_FP16_TO_FP, MVT::f64, Expand);
393 setOperationAction(ISD::STRICT_FP16_TO_FP, MVT::f80, Expand);
394 setOperationAction(ISD::STRICT_FP16_TO_FP, MVT::f128, Expand);
395 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
396 setOperationAction(ISD::FP_TO_FP16, MVT::f80, Expand);
397 setOperationAction(ISD::FP_TO_FP16, MVT::f128, Expand);
398 setOperationAction(ISD::STRICT_FP_TO_FP16, MVT::f64, Expand);
399 setOperationAction(ISD::STRICT_FP_TO_FP16, MVT::f80, Expand);
400 setOperationAction(ISD::STRICT_FP_TO_FP16, MVT::f128, Expand);
401
402 setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Expand);
403 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Expand);
404 setLoadExtAction(ISD::EXTLOAD, MVT::f80, MVT::f16, Expand);
405 setLoadExtAction(ISD::EXTLOAD, MVT::f128, MVT::f16, Expand);
406 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
407 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
408 setTruncStoreAction(MVT::f80, MVT::f16, Expand);
409 setTruncStoreAction(MVT::f128, MVT::f16, Expand);
410
411 if (Subtarget.hasPOPCNT()) {
412 setOperationPromotedToType(ISD::CTPOP, MVT::i8, MVT::i32);
413 } else {
414 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
415 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
416 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
417 if (Subtarget.is64Bit())
418 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
419 else
420 setOperationAction(ISD::CTPOP , MVT::i64 , Custom);
421 }
422
423 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
424
425 if (!Subtarget.hasMOVBE())
426 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
427
428 // X86 wants to expand cmov itself.
429 for (auto VT : { MVT::f32, MVT::f64, MVT::f80, MVT::f128 }) {
430 setOperationAction(ISD::SELECT, VT, Custom);
431 setOperationAction(ISD::SETCC, VT, Custom);
432 setOperationAction(ISD::STRICT_FSETCC, VT, Custom);
433 setOperationAction(ISD::STRICT_FSETCCS, VT, Custom);
434 }
435 for (auto VT : { MVT::i8, MVT::i16, MVT::i32, MVT::i64 }) {
436 if (VT == MVT::i64 && !Subtarget.is64Bit())
437 continue;
438 setOperationAction(ISD::SELECT, VT, Custom);
439 setOperationAction(ISD::SETCC, VT, Custom);
440 }
441
442 // Custom action for SELECT MMX and expand action for SELECT_CC MMX
443 setOperationAction(ISD::SELECT, MVT::x86mmx, Custom);
444 setOperationAction(ISD::SELECT_CC, MVT::x86mmx, Expand);
445
446 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
447 // NOTE: EH_SJLJ_SETJMP/_LONGJMP are not recommended, since
448 // LLVM/Clang supports zero-cost DWARF and SEH exception handling.
449 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
450 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
451 setOperationAction(ISD::EH_SJLJ_SETUP_DISPATCH, MVT::Other, Custom);
452 if (TM.Options.ExceptionModel == ExceptionHandling::SjLj)
453 setLibcallName(RTLIB::UNWIND_RESUME, "_Unwind_SjLj_Resume");
454
455 // Darwin ABI issue.
456 for (auto VT : { MVT::i32, MVT::i64 }) {
457 if (VT == MVT::i64 && !Subtarget.is64Bit())
458 continue;
459 setOperationAction(ISD::ConstantPool , VT, Custom);
460 setOperationAction(ISD::JumpTable , VT, Custom);
461 setOperationAction(ISD::GlobalAddress , VT, Custom);
462 setOperationAction(ISD::GlobalTLSAddress, VT, Custom);
463 setOperationAction(ISD::ExternalSymbol , VT, Custom);
464 setOperationAction(ISD::BlockAddress , VT, Custom);
465 }
466
467 // 64-bit shl, sra, srl (iff 32-bit x86)
468 for (auto VT : { MVT::i32, MVT::i64 }) {
469 if (VT == MVT::i64 && !Subtarget.is64Bit())
470 continue;
471 setOperationAction(ISD::SHL_PARTS, VT, Custom);
472 setOperationAction(ISD::SRA_PARTS, VT, Custom);
473 setOperationAction(ISD::SRL_PARTS, VT, Custom);
474 }
475
476 if (Subtarget.hasSSEPrefetch() || Subtarget.has3DNow())
477 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
478
479 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
480
481 // Expand certain atomics
482 for (auto VT : { MVT::i8, MVT::i16, MVT::i32, MVT::i64 }) {
483 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Custom);
484 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
485 setOperationAction(ISD::ATOMIC_LOAD_ADD, VT, Custom);
486 setOperationAction(ISD::ATOMIC_LOAD_OR, VT, Custom);
487 setOperationAction(ISD::ATOMIC_LOAD_XOR, VT, Custom);
488 setOperationAction(ISD::ATOMIC_LOAD_AND, VT, Custom);
489 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
490 }
491
492 if (!Subtarget.is64Bit())
493 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Custom);
494
495 if (Subtarget.hasCmpxchg16b()) {
496 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, MVT::i128, Custom);
497 }
498
499 // FIXME - use subtarget debug flags
500 if (!Subtarget.isTargetDarwin() && !Subtarget.isTargetELF() &&
501 !Subtarget.isTargetCygMing() && !Subtarget.isTargetWin64() &&
502 TM.Options.ExceptionModel != ExceptionHandling::SjLj) {
503 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
504 }
505
506 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
507 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
508
509 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
510 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
511
512 setOperationAction(ISD::TRAP, MVT::Other, Legal);
513 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
514
515 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
516 setOperationAction(ISD::VASTART , MVT::Other, Custom);
517 setOperationAction(ISD::VAEND , MVT::Other, Expand);
518 bool Is64Bit = Subtarget.is64Bit();
519 setOperationAction(ISD::VAARG, MVT::Other, Is64Bit ? Custom : Expand);
520 setOperationAction(ISD::VACOPY, MVT::Other, Is64Bit ? Custom : Expand);
521
522 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
523 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
524
525 setOperationAction(ISD::DYNAMIC_STACKALLOC, PtrVT, Custom);
526
527 // GC_TRANSITION_START and GC_TRANSITION_END need custom lowering.
528 setOperationAction(ISD::GC_TRANSITION_START, MVT::Other, Custom);
529 setOperationAction(ISD::GC_TRANSITION_END, MVT::Other, Custom);
530
531 if (!Subtarget.useSoftFloat() && X86ScalarSSEf64) {
532 // f32 and f64 use SSE.
533 // Set up the FP register classes.
534 addRegisterClass(MVT::f32, Subtarget.hasAVX512() ? &X86::FR32XRegClass
535 : &X86::FR32RegClass);
536 addRegisterClass(MVT::f64, Subtarget.hasAVX512() ? &X86::FR64XRegClass
537 : &X86::FR64RegClass);
538
539 // Disable f32->f64 extload as we can only generate this in one instruction
540 // under optsize. So its easier to pattern match (fpext (load)) for that
541 // case instead of needing to emit 2 instructions for extload in the
542 // non-optsize case.
543 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f32, Expand);
544
545 for (auto VT : { MVT::f32, MVT::f64 }) {
546 // Use ANDPD to simulate FABS.
547 setOperationAction(ISD::FABS, VT, Custom);
548
549 // Use XORP to simulate FNEG.
550 setOperationAction(ISD::FNEG, VT, Custom);
551
552 // Use ANDPD and ORPD to simulate FCOPYSIGN.
553 setOperationAction(ISD::FCOPYSIGN, VT, Custom);
554
555 // These might be better off as horizontal vector ops.
556 setOperationAction(ISD::FADD, VT, Custom);
557 setOperationAction(ISD::FSUB, VT, Custom);
558
559 // We don't support sin/cos/fmod
560 setOperationAction(ISD::FSIN , VT, Expand);
561 setOperationAction(ISD::FCOS , VT, Expand);
562 setOperationAction(ISD::FSINCOS, VT, Expand);
563 }
564
565 // Lower this to MOVMSK plus an AND.
566 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
567 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
568
569 } else if (!Subtarget.useSoftFloat() && X86ScalarSSEf32 &&
570 (UseX87 || Is64Bit)) {
571 // Use SSE for f32, x87 for f64.
572 // Set up the FP register classes.
573 addRegisterClass(MVT::f32, &X86::FR32RegClass);
574 if (UseX87)
575 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
576
577 // Use ANDPS to simulate FABS.
578 setOperationAction(ISD::FABS , MVT::f32, Custom);
579
580 // Use XORP to simulate FNEG.
581 setOperationAction(ISD::FNEG , MVT::f32, Custom);
582
583 if (UseX87)
584 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
585
586 // Use ANDPS and ORPS to simulate FCOPYSIGN.
587 if (UseX87)
588 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
589 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
590
591 // We don't support sin/cos/fmod
592 setOperationAction(ISD::FSIN , MVT::f32, Expand);
593 setOperationAction(ISD::FCOS , MVT::f32, Expand);
594 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
595
596 if (UseX87) {
597 // Always expand sin/cos functions even though x87 has an instruction.
598 setOperationAction(ISD::FSIN, MVT::f64, Expand);
599 setOperationAction(ISD::FCOS, MVT::f64, Expand);
600 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
601 }
602 } else if (UseX87) {
603 // f32 and f64 in x87.
604 // Set up the FP register classes.
605 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
606 addRegisterClass(MVT::f32, &X86::RFP32RegClass);
607
608 for (auto VT : { MVT::f32, MVT::f64 }) {
609 setOperationAction(ISD::UNDEF, VT, Expand);
610 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
611
612 // Always expand sin/cos functions even though x87 has an instruction.
613 setOperationAction(ISD::FSIN , VT, Expand);
614 setOperationAction(ISD::FCOS , VT, Expand);
615 setOperationAction(ISD::FSINCOS, VT, Expand);
616 }
617 }
618
619 // Expand FP32 immediates into loads from the stack, save special cases.
620 if (isTypeLegal(MVT::f32)) {
621 if (UseX87 && (getRegClassFor(MVT::f32) == &X86::RFP32RegClass)) {
622 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
623 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
624 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
625 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
626 } else // SSE immediates.
627 addLegalFPImmediate(APFloat(+0.0f)); // xorps
628 }
629 // Expand FP64 immediates into loads from the stack, save special cases.
630 if (isTypeLegal(MVT::f64)) {
631 if (UseX87 && getRegClassFor(MVT::f64) == &X86::RFP64RegClass) {
632 addLegalFPImmediate(APFloat(+0.0)); // FLD0
633 addLegalFPImmediate(APFloat(+1.0)); // FLD1
634 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
635 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
636 } else // SSE immediates.
637 addLegalFPImmediate(APFloat(+0.0)); // xorpd
638 }
639 // Handle constrained floating-point operations of scalar.
640 setOperationAction(ISD::STRICT_FADD, MVT::f32, Legal);
641 setOperationAction(ISD::STRICT_FADD, MVT::f64, Legal);
642 setOperationAction(ISD::STRICT_FSUB, MVT::f32, Legal);
643 setOperationAction(ISD::STRICT_FSUB, MVT::f64, Legal);
644 setOperationAction(ISD::STRICT_FMUL, MVT::f32, Legal);
645 setOperationAction(ISD::STRICT_FMUL, MVT::f64, Legal);
646 setOperationAction(ISD::STRICT_FDIV, MVT::f32, Legal);
647 setOperationAction(ISD::STRICT_FDIV, MVT::f64, Legal);
648 setOperationAction(ISD::STRICT_FP_EXTEND, MVT::f64, Legal);
649 setOperationAction(ISD::STRICT_FP_ROUND, MVT::f32, Legal);
650 setOperationAction(ISD::STRICT_FP_ROUND, MVT::f64, Legal);
651 setOperationAction(ISD::STRICT_FSQRT, MVT::f32, Legal);
652 setOperationAction(ISD::STRICT_FSQRT, MVT::f64, Legal);
653
654 // We don't support FMA.
655 setOperationAction(ISD::FMA, MVT::f64, Expand);
656 setOperationAction(ISD::FMA, MVT::f32, Expand);
657
658 // f80 always uses X87.
659 if (UseX87) {
660 addRegisterClass(MVT::f80, &X86::RFP80RegClass);
661 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
662 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
663 {
664 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended());
665 addLegalFPImmediate(TmpFlt); // FLD0
666 TmpFlt.changeSign();
667 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
668
669 bool ignored;
670 APFloat TmpFlt2(+1.0);
671 TmpFlt2.convert(APFloat::x87DoubleExtended(), APFloat::rmNearestTiesToEven,
672 &ignored);
673 addLegalFPImmediate(TmpFlt2); // FLD1
674 TmpFlt2.changeSign();
675 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
676 }
677
678 // Always expand sin/cos functions even though x87 has an instruction.
679 setOperationAction(ISD::FSIN , MVT::f80, Expand);
680 setOperationAction(ISD::FCOS , MVT::f80, Expand);
681 setOperationAction(ISD::FSINCOS, MVT::f80, Expand);
682
683 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
684 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
685 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
686 setOperationAction(ISD::FRINT, MVT::f80, Expand);
687 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
688 setOperationAction(ISD::FMA, MVT::f80, Expand);
689 setOperationAction(ISD::LROUND, MVT::f80, Expand);
690 setOperationAction(ISD::LLROUND, MVT::f80, Expand);
691 setOperationAction(ISD::LRINT, MVT::f80, Custom);
692 setOperationAction(ISD::LLRINT, MVT::f80, Custom);
693
694 // Handle constrained floating-point operations of scalar.
695 setOperationAction(ISD::STRICT_FADD , MVT::f80, Legal);
696 setOperationAction(ISD::STRICT_FSUB , MVT::f80, Legal);
697 setOperationAction(ISD::STRICT_FMUL , MVT::f80, Legal);
698 setOperationAction(ISD::STRICT_FDIV , MVT::f80, Legal);
699 setOperationAction(ISD::STRICT_FSQRT , MVT::f80, Legal);
700 setOperationAction(ISD::STRICT_FP_EXTEND, MVT::f80, Legal);
701 // FIXME: When the target is 64-bit, STRICT_FP_ROUND will be overwritten
702 // as Custom.
703 setOperationAction(ISD::STRICT_FP_ROUND, MVT::f80, Legal);
704 }
705
706 // f128 uses xmm registers, but most operations require libcalls.
707 if (!Subtarget.useSoftFloat() && Subtarget.is64Bit() && Subtarget.hasSSE1()) {
708 addRegisterClass(MVT::f128, Subtarget.hasVLX() ? &X86::VR128XRegClass
709 : &X86::VR128RegClass);
710
711 addLegalFPImmediate(APFloat::getZero(APFloat::IEEEquad())); // xorps
712
713 setOperationAction(ISD::FADD, MVT::f128, LibCall);
714 setOperationAction(ISD::STRICT_FADD, MVT::f128, LibCall);
715 setOperationAction(ISD::FSUB, MVT::f128, LibCall);
716 setOperationAction(ISD::STRICT_FSUB, MVT::f128, LibCall);
717 setOperationAction(ISD::FDIV, MVT::f128, LibCall);
718 setOperationAction(ISD::STRICT_FDIV, MVT::f128, LibCall);
719 setOperationAction(ISD::FMUL, MVT::f128, LibCall);
720 setOperationAction(ISD::STRICT_FMUL, MVT::f128, LibCall);
721 setOperationAction(ISD::FMA, MVT::f128, LibCall);
722 setOperationAction(ISD::STRICT_FMA, MVT::f128, LibCall);
723
724 setOperationAction(ISD::FABS, MVT::f128, Custom);
725 setOperationAction(ISD::FNEG, MVT::f128, Custom);
726 setOperationAction(ISD::FCOPYSIGN, MVT::f128, Custom);
727
728 setOperationAction(ISD::FSIN, MVT::f128, LibCall);
729 setOperationAction(ISD::STRICT_FSIN, MVT::f128, LibCall);
730 setOperationAction(ISD::FCOS, MVT::f128, LibCall);
731 setOperationAction(ISD::STRICT_FCOS, MVT::f128, LibCall);
732 setOperationAction(ISD::FSINCOS, MVT::f128, LibCall);
733 // No STRICT_FSINCOS
734 setOperationAction(ISD::FSQRT, MVT::f128, LibCall);
735 setOperationAction(ISD::STRICT_FSQRT, MVT::f128, LibCall);
736
737 setOperationAction(ISD::FP_EXTEND, MVT::f128, Custom);
738 setOperationAction(ISD::STRICT_FP_EXTEND, MVT::f128, Custom);
739 // We need to custom handle any FP_ROUND with an f128 input, but
740 // LegalizeDAG uses the result type to know when to run a custom handler.
741 // So we have to list all legal floating point result types here.
742 if (isTypeLegal(MVT::f32)) {
743 setOperationAction(ISD::FP_ROUND, MVT::f32, Custom);
744 setOperationAction(ISD::STRICT_FP_ROUND, MVT::f32, Custom);
745 }
746 if (isTypeLegal(MVT::f64)) {
747 setOperationAction(ISD::FP_ROUND, MVT::f64, Custom);
748 setOperationAction(ISD::STRICT_FP_ROUND, MVT::f64, Custom);
749 }
750 if (isTypeLegal(MVT::f80)) {
751 setOperationAction(ISD::FP_ROUND, MVT::f80, Custom);
752 setOperationAction(ISD::STRICT_FP_ROUND, MVT::f80, Custom);
753 }
754
755 setOperationAction(ISD::SETCC, MVT::f128, Custom);
756
757 setLoadExtAction(ISD::EXTLOAD, MVT::f128, MVT::f32, Expand);
758 setLoadExtAction(ISD::EXTLOAD, MVT::f128, MVT::f64, Expand);
759 setLoadExtAction(ISD::EXTLOAD, MVT::f128, MVT::f80, Expand);
760 setTruncStoreAction(MVT::f128, MVT::f32, Expand);
761 setTruncStoreAction(MVT::f128, MVT::f64, Expand);
762 setTruncStoreAction(MVT::f128, MVT::f80, Expand);
763 }
764
765 // Always use a library call for pow.
766 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
767 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
768 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
769 setOperationAction(ISD::FPOW , MVT::f128 , Expand);
770
771 setOperationAction(ISD::FLOG, MVT::f80, Expand);
772 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
773 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
774 setOperationAction(ISD::FEXP, MVT::f80, Expand);
775 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
776 setOperationAction(ISD::FMINNUM, MVT::f80, Expand);
777 setOperationAction(ISD::FMAXNUM, MVT::f80, Expand);
778
779 // Some FP actions are always expanded for vector types.
780 for (auto VT : { MVT::v4f32, MVT::v8f32, MVT::v16f32,
781 MVT::v2f64, MVT::v4f64, MVT::v8f64 }) {
782 setOperationAction(ISD::FSIN, VT, Expand);
783 setOperationAction(ISD::FSINCOS, VT, Expand);
784 setOperationAction(ISD::FCOS, VT, Expand);
785 setOperationAction(ISD::FREM, VT, Expand);
786 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
787 setOperationAction(ISD::FPOW, VT, Expand);
788 setOperationAction(ISD::FLOG, VT, Expand);
789 setOperationAction(ISD::FLOG2, VT, Expand);
790 setOperationAction(ISD::FLOG10, VT, Expand);
791 setOperationAction(ISD::FEXP, VT, Expand);
792 setOperationAction(ISD::FEXP2, VT, Expand);
793 }
794
795 // First set operation action for all vector types to either promote
796 // (for widening) or expand (for scalarization). Then we will selectively
797 // turn on ones that can be effectively codegen'd.
798 for (MVT VT : MVT::fixedlen_vector_valuetypes()) {
799 setOperationAction(ISD::SDIV, VT, Expand);
800 setOperationAction(ISD::UDIV, VT, Expand);
801 setOperationAction(ISD::SREM, VT, Expand);
802 setOperationAction(ISD::UREM, VT, Expand);
803 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT,Expand);
804 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
805 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT,Expand);
806 setOperationAction(ISD::INSERT_SUBVECTOR, VT,Expand);
807 setOperationAction(ISD::FMA, VT, Expand);
808 setOperationAction(ISD::FFLOOR, VT, Expand);
809 setOperationAction(ISD::FCEIL, VT, Expand);
810 setOperationAction(ISD::FTRUNC, VT, Expand);
811 setOperationAction(ISD::FRINT, VT, Expand);
812 setOperationAction(ISD::FNEARBYINT, VT, Expand);
813 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
814 setOperationAction(ISD::MULHS, VT, Expand);
815 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
816 setOperationAction(ISD::MULHU, VT, Expand);
817 setOperationAction(ISD::SDIVREM, VT, Expand);
818 setOperationAction(ISD::UDIVREM, VT, Expand);
819 setOperationAction(ISD::CTPOP, VT, Expand);
820 setOperationAction(ISD::CTTZ, VT, Expand);
821 setOperationAction(ISD::CTLZ, VT, Expand);
822 setOperationAction(ISD::ROTL, VT, Expand);
823 setOperationAction(ISD::ROTR, VT, Expand);
824 setOperationAction(ISD::BSWAP, VT, Expand);
825 setOperationAction(ISD::SETCC, VT, Expand);
826 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
827 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
828 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
829 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
830 setOperationAction(ISD::SIGN_EXTEND_INREG, VT,Expand);
831 setOperationAction(ISD::TRUNCATE, VT, Expand);
832 setOperationAction(ISD::SIGN_EXTEND, VT, Expand);
833 setOperationAction(ISD::ZERO_EXTEND, VT, Expand);
834 setOperationAction(ISD::ANY_EXTEND, VT, Expand);
835 setOperationAction(ISD::SELECT_CC, VT, Expand);
836 for (MVT InnerVT : MVT::fixedlen_vector_valuetypes()) {
837 setTruncStoreAction(InnerVT, VT, Expand);
838
839 setLoadExtAction(ISD::SEXTLOAD, InnerVT, VT, Expand);
840 setLoadExtAction(ISD::ZEXTLOAD, InnerVT, VT, Expand);
841
842 // N.b. ISD::EXTLOAD legality is basically ignored except for i1-like
843 // types, we have to deal with them whether we ask for Expansion or not.
844 // Setting Expand causes its own optimisation problems though, so leave
845 // them legal.
846 if (VT.getVectorElementType() == MVT::i1)
847 setLoadExtAction(ISD::EXTLOAD, InnerVT, VT, Expand);
848
849 // EXTLOAD for MVT::f16 vectors is not legal because f16 vectors are
850 // split/scalarized right now.
851 if (VT.getVectorElementType() == MVT::f16)
852 setLoadExtAction(ISD::EXTLOAD, InnerVT, VT, Expand);
853 }
854 }
855
856 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
857 // with -msoft-float, disable use of MMX as well.
858 if (!Subtarget.useSoftFloat() && Subtarget.hasMMX()) {
859 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
860 // No operations on x86mmx supported, everything uses intrinsics.
861 }
862
863 if (!Subtarget.useSoftFloat() && Subtarget.hasSSE1()) {
864 addRegisterClass(MVT::v4f32, Subtarget.hasVLX() ? &X86::VR128XRegClass
865 : &X86::VR128RegClass);
866
867 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
868 setOperationAction(ISD::FABS, MVT::v4f32, Custom);
869 setOperationAction(ISD::FCOPYSIGN, MVT::v4f32, Custom);
870 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
871 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
872 setOperationAction(ISD::VSELECT, MVT::v4f32, Custom);
873 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
874 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
875
876 setOperationAction(ISD::LOAD, MVT::v2f32, Custom);
877 setOperationAction(ISD::STORE, MVT::v2f32, Custom);
878
879 setOperationAction(ISD::STRICT_FADD, MVT::v4f32, Legal);
880 setOperationAction(ISD::STRICT_FSUB, MVT::v4f32, Legal);
881 setOperationAction(ISD::STRICT_FMUL, MVT::v4f32, Legal);
882 setOperationAction(ISD::STRICT_FDIV, MVT::v4f32, Legal);
883 setOperationAction(ISD::STRICT_FSQRT, MVT::v4f32, Legal);
884 }
885
886 if (!Subtarget.useSoftFloat() && Subtarget.hasSSE2()) {
887 addRegisterClass(MVT::v2f64, Subtarget.hasVLX() ? &X86::VR128XRegClass
888 : &X86::VR128RegClass);
889
890 // FIXME: Unfortunately, -soft-float and -no-implicit-float mean XMM
891 // registers cannot be used even for integer operations.
892 addRegisterClass(MVT::v16i8, Subtarget.hasVLX() ? &X86::VR128XRegClass
893 : &X86::VR128RegClass);
894 addRegisterClass(MVT::v8i16, Subtarget.hasVLX() ? &X86::VR128XRegClass
895 : &X86::VR128RegClass);
896 addRegisterClass(MVT::v4i32, Subtarget.hasVLX() ? &X86::VR128XRegClass
897 : &X86::VR128RegClass);
898 addRegisterClass(MVT::v2i64, Subtarget.hasVLX() ? &X86::VR128XRegClass
899 : &X86::VR128RegClass);
900
901 for (auto VT : { MVT::v2i8, MVT::v4i8, MVT::v8i8,
902 MVT::v2i16, MVT::v4i16, MVT::v2i32 }) {
903 setOperationAction(ISD::SDIV, VT, Custom);
904 setOperationAction(ISD::SREM, VT, Custom);
905 setOperationAction(ISD::UDIV, VT, Custom);
906 setOperationAction(ISD::UREM, VT, Custom);
907 }
908
909 setOperationAction(ISD::MUL, MVT::v2i8, Custom);
910 setOperationAction(ISD::MUL, MVT::v4i8, Custom);
911 setOperationAction(ISD::MUL, MVT::v8i8, Custom);
912
913 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
914 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
915 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
916 setOperationAction(ISD::MULHU, MVT::v4i32, Custom);
917 setOperationAction(ISD::MULHS, MVT::v4i32, Custom);
918 setOperationAction(ISD::MULHU, MVT::v16i8, Custom);
919 setOperationAction(ISD::MULHS, MVT::v16i8, Custom);
920 setOperationAction(ISD::MULHU, MVT::v8i16, Legal);
921 setOperationAction(ISD::MULHS, MVT::v8i16, Legal);
922 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
923 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
924 setOperationAction(ISD::FABS, MVT::v2f64, Custom);
925 setOperationAction(ISD::FCOPYSIGN, MVT::v2f64, Custom);
926
927 for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64 }) {
928 setOperationAction(ISD::SMAX, VT, VT == MVT::v8i16 ? Legal : Custom);
929 setOperationAction(ISD::SMIN, VT, VT == MVT::v8i16 ? Legal : Custom);
930 setOperationAction(ISD::UMAX, VT, VT == MVT::v16i8 ? Legal : Custom);
931 setOperationAction(ISD::UMIN, VT, VT == MVT::v16i8 ? Legal : Custom);
932 }
933
934 setOperationAction(ISD::UADDSAT, MVT::v16i8, Legal);
935 setOperationAction(ISD::SADDSAT, MVT::v16i8, Legal);
936 setOperationAction(ISD::USUBSAT, MVT::v16i8, Legal);
937 setOperationAction(ISD::SSUBSAT, MVT::v16i8, Legal);
938 setOperationAction(ISD::UADDSAT, MVT::v8i16, Legal);
939 setOperationAction(ISD::SADDSAT, MVT::v8i16, Legal);
940 setOperationAction(ISD::USUBSAT, MVT::v8i16, Legal);
941 setOperationAction(ISD::SSUBSAT, MVT::v8i16, Legal);
942 setOperationAction(ISD::UADDSAT, MVT::v4i32, Custom);
943 setOperationAction(ISD::USUBSAT, MVT::v4i32, Custom);
944 setOperationAction(ISD::UADDSAT, MVT::v2i64, Custom);
945 setOperationAction(ISD::USUBSAT, MVT::v2i64, Custom);
946
947 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
948 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
949 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
950
951 for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64 }) {
952 setOperationAction(ISD::SETCC, VT, Custom);
953 setOperationAction(ISD::STRICT_FSETCC, VT, Custom);
954 setOperationAction(ISD::STRICT_FSETCCS, VT, Custom);
955 setOperationAction(ISD::CTPOP, VT, Custom);
956 setOperationAction(ISD::ABS, VT, Custom);
957
958 // The condition codes aren't legal in SSE/AVX and under AVX512 we use
959 // setcc all the way to isel and prefer SETGT in some isel patterns.
960 setCondCodeAction(ISD::SETLT, VT, Custom);
961 setCondCodeAction(ISD::SETLE, VT, Custom);
962 }
963
964 for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32 }) {
965 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
966 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
967 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
968 setOperationAction(ISD::VSELECT, VT, Custom);
969 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
970 }
971
972 for (auto VT : { MVT::v2f64, MVT::v2i64 }) {
973 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
974 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
975 setOperationAction(ISD::VSELECT, VT, Custom);
976
977 if (VT == MVT::v2i64 && !Subtarget.is64Bit())
978 continue;
979
980 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
981 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
982 }
983
984 // Custom lower v2i64 and v2f64 selects.
985 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
986 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
987 setOperationAction(ISD::SELECT, MVT::v4i32, Custom);
988 setOperationAction(ISD::SELECT, MVT::v8i16, Custom);
989 setOperationAction(ISD::SELECT, MVT::v16i8, Custom);
990
991 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
992 setOperationAction(ISD::FP_TO_SINT, MVT::v2i32, Custom);
993 setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::v4i32, Legal);
994 setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::v2i32, Custom);
995
996 // Custom legalize these to avoid over promotion or custom promotion.
997 for (auto VT : {MVT::v2i8, MVT::v4i8, MVT::v8i8, MVT::v2i16, MVT::v4i16}) {
998 setOperationAction(ISD::FP_TO_SINT, VT, Custom);
999 setOperationAction(ISD::FP_TO_UINT, VT, Custom);
1000 setOperationAction(ISD::STRICT_FP_TO_SINT, VT, Custom);
1001 setOperationAction(ISD::STRICT_FP_TO_UINT, VT, Custom);
1002 }
1003
1004 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
1005 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::v4i32, Legal);
1006 setOperationAction(ISD::SINT_TO_FP, MVT::v2i32, Custom);
1007 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::v2i32, Custom);
1008
1009 setOperationAction(ISD::UINT_TO_FP, MVT::v2i32, Custom);
1010 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::v2i32, Custom);
1011
1012 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Custom);
1013 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::v4i32, Custom);
1014
1015 // Fast v2f32 UINT_TO_FP( v2i32 ) custom conversion.
1016 setOperationAction(ISD::SINT_TO_FP, MVT::v2f32, Custom);
1017 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::v2f32, Custom);
1018 setOperationAction(ISD::UINT_TO_FP, MVT::v2f32, Custom);
1019 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::v2f32, Custom);
1020
1021 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
1022 setOperationAction(ISD::STRICT_FP_EXTEND, MVT::v2f32, Custom);
1023 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Custom);
1024 setOperationAction(ISD::STRICT_FP_ROUND, MVT::v2f32, Custom);
1025
1026 // We want to legalize this to an f64 load rather than an i64 load on
1027 // 64-bit targets and two 32-bit loads on a 32-bit target. Similar for
1028 // store.
1029 setOperationAction(ISD::LOAD, MVT::v2i32, Custom);
1030 setOperationAction(ISD::LOAD, MVT::v4i16, Custom);
1031 setOperationAction(ISD::LOAD, MVT::v8i8, Custom);
1032 setOperationAction(ISD::STORE, MVT::v2i32, Custom);
1033 setOperationAction(ISD::STORE, MVT::v4i16, Custom);
1034 setOperationAction(ISD::STORE, MVT::v8i8, Custom);
1035
1036 setOperationAction(ISD::BITCAST, MVT::v2i32, Custom);
1037 setOperationAction(ISD::BITCAST, MVT::v4i16, Custom);
1038 setOperationAction(ISD::BITCAST, MVT::v8i8, Custom);
1039 if (!Subtarget.hasAVX512())
1040 setOperationAction(ISD::BITCAST, MVT::v16i1, Custom);
1041
1042 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v2i64, Custom);
1043 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v4i32, Custom);
1044 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v8i16, Custom);
1045
1046 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i64, Custom);
1047
1048 setOperationAction(ISD::TRUNCATE, MVT::v2i8, Custom);
1049 setOperationAction(ISD::TRUNCATE, MVT::v2i16, Custom);
1050 setOperationAction(ISD::TRUNCATE, MVT::v2i32, Custom);
1051 setOperationAction(ISD::TRUNCATE, MVT::v4i8, Custom);
1052 setOperationAction(ISD::TRUNCATE, MVT::v4i16, Custom);
1053 setOperationAction(ISD::TRUNCATE, MVT::v8i8, Custom);
1054
1055 // In the customized shift lowering, the legal v4i32/v2i64 cases
1056 // in AVX2 will be recognized.
1057 for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64 }) {
1058 setOperationAction(ISD::SRL, VT, Custom);
1059 setOperationAction(ISD::SHL, VT, Custom);
1060 setOperationAction(ISD::SRA, VT, Custom);
1061 }
1062
1063 setOperationAction(ISD::ROTL, MVT::v4i32, Custom);
1064 setOperationAction(ISD::ROTL, MVT::v8i16, Custom);
1065
1066 // With AVX512, expanding (and promoting the shifts) is better.
1067 if (!Subtarget.hasAVX512())
1068 setOperationAction(ISD::ROTL, MVT::v16i8, Custom);
1069
1070 setOperationAction(ISD::STRICT_FSQRT, MVT::v2f64, Legal);
1071 setOperationAction(ISD::STRICT_FADD, MVT::v2f64, Legal);
1072 setOperationAction(ISD::STRICT_FSUB, MVT::v2f64, Legal);
1073 setOperationAction(ISD::STRICT_FMUL, MVT::v2f64, Legal);
1074 setOperationAction(ISD::STRICT_FDIV, MVT::v2f64, Legal);
1075 }
1076
1077 if (!Subtarget.useSoftFloat() && Subtarget.hasSSSE3()) {
1078 setOperationAction(ISD::ABS, MVT::v16i8, Legal);
1079 setOperationAction(ISD::ABS, MVT::v8i16, Legal);
1080 setOperationAction(ISD::ABS, MVT::v4i32, Legal);
1081 setOperationAction(ISD::BITREVERSE, MVT::v16i8, Custom);
1082 setOperationAction(ISD::CTLZ, MVT::v16i8, Custom);
1083 setOperationAction(ISD::CTLZ, MVT::v8i16, Custom);
1084 setOperationAction(ISD::CTLZ, MVT::v4i32, Custom);
1085 setOperationAction(ISD::CTLZ, MVT::v2i64, Custom);
1086
1087 // These might be better off as horizontal vector ops.
1088 setOperationAction(ISD::ADD, MVT::i16, Custom);
1089 setOperationAction(ISD::ADD, MVT::i32, Custom);
1090 setOperationAction(ISD::SUB, MVT::i16, Custom);
1091 setOperationAction(ISD::SUB, MVT::i32, Custom);
1092 }
1093
1094 if (!Subtarget.useSoftFloat() && Subtarget.hasSSE41()) {
1095 for (MVT RoundedTy : {MVT::f32, MVT::f64, MVT::v4f32, MVT::v2f64}) {
1096 setOperationAction(ISD::FFLOOR, RoundedTy, Legal);
1097 setOperationAction(ISD::STRICT_FFLOOR, RoundedTy, Legal);
1098 setOperationAction(ISD::FCEIL, RoundedTy, Legal);
1099 setOperationAction(ISD::STRICT_FCEIL, RoundedTy, Legal);
1100 setOperationAction(ISD::FTRUNC, RoundedTy, Legal);
1101 setOperationAction(ISD::STRICT_FTRUNC, RoundedTy, Legal);
1102 setOperationAction(ISD::FRINT, RoundedTy, Legal);
1103 setOperationAction(ISD::STRICT_FRINT, RoundedTy, Legal);
1104 setOperationAction(ISD::FNEARBYINT, RoundedTy, Legal);
1105 setOperationAction(ISD::STRICT_FNEARBYINT, RoundedTy, Legal);
1106
1107 setOperationAction(ISD::FROUND, RoundedTy, Custom);
1108 }
1109
1110 setOperationAction(ISD::SMAX, MVT::v16i8, Legal);
1111 setOperationAction(ISD::SMAX, MVT::v4i32, Legal);
1112 setOperationAction(ISD::UMAX, MVT::v8i16, Legal);
1113 setOperationAction(ISD::UMAX, MVT::v4i32, Legal);
1114 setOperationAction(ISD::SMIN, MVT::v16i8, Legal);
1115 setOperationAction(ISD::SMIN, MVT::v4i32, Legal);
1116 setOperationAction(ISD::UMIN, MVT::v8i16, Legal);
1117 setOperationAction(ISD::UMIN, MVT::v4i32, Legal);
1118
1119 // FIXME: Do we need to handle scalar-to-vector here?
1120 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
1121
1122 // We directly match byte blends in the backend as they match the VSELECT
1123 // condition form.
1124 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
1125
1126 // SSE41 brings specific instructions for doing vector sign extend even in
1127 // cases where we don't have SRA.
1128 for (auto VT : { MVT::v8i16, MVT::v4i32, MVT::v2i64 }) {
1129 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, VT, Legal);
1130 setOperationAction(ISD::ZERO_EXTEND_VECTOR_INREG, VT, Legal);
1131 }
1132
1133 // SSE41 also has vector sign/zero extending loads, PMOV[SZ]X
1134 for (auto LoadExtOp : { ISD::SEXTLOAD, ISD::ZEXTLOAD }) {
1135 setLoadExtAction(LoadExtOp, MVT::v8i16, MVT::v8i8, Legal);
1136 setLoadExtAction(LoadExtOp, MVT::v4i32, MVT::v4i8, Legal);
1137 setLoadExtAction(LoadExtOp, MVT::v2i64, MVT::v2i8, Legal);
1138 setLoadExtAction(LoadExtOp, MVT::v4i32, MVT::v4i16, Legal);
1139 setLoadExtAction(LoadExtOp, MVT::v2i64, MVT::v2i16, Legal);
1140 setLoadExtAction(LoadExtOp, MVT::v2i64, MVT::v2i32, Legal);
1141 }
1142
1143 // i8 vectors are custom because the source register and source
1144 // source memory operand types are not the same width.
1145 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
1146
1147 if (Subtarget.is64Bit() && !Subtarget.hasAVX512()) {
1148 // We need to scalarize v4i64->v432 uint_to_fp using cvtsi2ss, but we can
1149 // do the pre and post work in the vector domain.
1150 setOperationAction(ISD::UINT_TO_FP, MVT::v4i64, Custom);
1151 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::v4i64, Custom);
1152 // We need to mark SINT_TO_FP as Custom even though we want to expand it
1153 // so that DAG combine doesn't try to turn it into uint_to_fp.
1154 setOperationAction(ISD::SINT_TO_FP, MVT::v4i64, Custom);
1155 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::v4i64, Custom);
1156 }
1157 }
1158
1159 if (!Subtarget.useSoftFloat() && Subtarget.hasXOP()) {
1160 for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64,
1161 MVT::v32i8, MVT::v16i16, MVT::v8i32, MVT::v4i64 })
1162 setOperationAction(ISD::ROTL, VT, Custom);
1163
1164 // XOP can efficiently perform BITREVERSE with VPPERM.
1165 for (auto VT : { MVT::i8, MVT::i16, MVT::i32, MVT::i64 })
1166 setOperationAction(ISD::BITREVERSE, VT, Custom);
1167
1168 for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64,
1169 MVT::v32i8, MVT::v16i16, MVT::v8i32, MVT::v4i64 })
1170 setOperationAction(ISD::BITREVERSE, VT, Custom);
1171 }
1172
1173 if (!Subtarget.useSoftFloat() && Subtarget.hasAVX()) {
1174 bool HasInt256 = Subtarget.hasInt256();
1175
1176 addRegisterClass(MVT::v32i8, Subtarget.hasVLX() ? &X86::VR256XRegClass
1177 : &X86::VR256RegClass);
1178 addRegisterClass(MVT::v16i16, Subtarget.hasVLX() ? &X86::VR256XRegClass
1179 : &X86::VR256RegClass);
1180 addRegisterClass(MVT::v8i32, Subtarget.hasVLX() ? &X86::VR256XRegClass
1181 : &X86::VR256RegClass);
1182 addRegisterClass(MVT::v8f32, Subtarget.hasVLX() ? &X86::VR256XRegClass
1183 : &X86::VR256RegClass);
1184 addRegisterClass(MVT::v4i64, Subtarget.hasVLX() ? &X86::VR256XRegClass
1185 : &X86::VR256RegClass);
1186 addRegisterClass(MVT::v4f64, Subtarget.hasVLX() ? &X86::VR256XRegClass
1187 : &X86::VR256RegClass);
1188
1189 for (auto VT : { MVT::v8f32, MVT::v4f64 }) {
1190 setOperationAction(ISD::FFLOOR, VT, Legal);
1191 setOperationAction(ISD::STRICT_FFLOOR, VT, Legal);
1192 setOperationAction(ISD::FCEIL, VT, Legal);
1193 setOperationAction(ISD::STRICT_FCEIL, VT, Legal);
1194 setOperationAction(ISD::FTRUNC, VT, Legal);
1195 setOperationAction(ISD::STRICT_FTRUNC, VT, Legal);
1196 setOperationAction(ISD::FRINT, VT, Legal);
1197 setOperationAction(ISD::STRICT_FRINT, VT, Legal);
1198 setOperationAction(ISD::FNEARBYINT, VT, Legal);
1199 setOperationAction(ISD::STRICT_FNEARBYINT, VT, Legal);
1200
1201 setOperationAction(ISD::FROUND, VT, Custom);
1202
1203 setOperationAction(ISD::FNEG, VT, Custom);
1204 setOperationAction(ISD::FABS, VT, Custom);
1205 setOperationAction(ISD::FCOPYSIGN, VT, Custom);
1206 }
1207
1208 // (fp_to_int:v8i16 (v8f32 ..)) requires the result type to be promoted
1209 // even though v8i16 is a legal type.
1210 setOperationPromotedToType(ISD::FP_TO_SINT, MVT::v8i16, MVT::v8i32);
1211 setOperationPromotedToType(ISD::FP_TO_UINT, MVT::v8i16, MVT::v8i32);
1212 setOperationPromotedToType(ISD::STRICT_FP_TO_SINT, MVT::v8i16, MVT::v8i32);
1213 setOperationPromotedToType(ISD::STRICT_FP_TO_UINT, MVT::v8i16, MVT::v8i32);
1214 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1215 setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::v8i32, Legal);
1216
1217 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1218 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::v8i32, Legal);
1219
1220 setOperationAction(ISD::STRICT_FP_ROUND, MVT::v4f32, Legal);
1221 setOperationAction(ISD::STRICT_FADD, MVT::v8f32, Legal);
1222 setOperationAction(ISD::STRICT_FADD, MVT::v4f64, Legal);
1223 setOperationAction(ISD::STRICT_FSUB, MVT::v8f32, Legal);
1224 setOperationAction(ISD::STRICT_FSUB, MVT::v4f64, Legal);
1225 setOperationAction(ISD::STRICT_FMUL, MVT::v8f32, Legal);
1226 setOperationAction(ISD::STRICT_FMUL, MVT::v4f64, Legal);
1227 setOperationAction(ISD::STRICT_FDIV, MVT::v8f32, Legal);
1228 setOperationAction(ISD::STRICT_FDIV, MVT::v4f64, Legal);
1229 setOperationAction(ISD::STRICT_FP_EXTEND, MVT::v4f64, Legal);
1230 setOperationAction(ISD::STRICT_FSQRT, MVT::v8f32, Legal);
1231 setOperationAction(ISD::STRICT_FSQRT, MVT::v4f64, Legal);
1232
1233 if (!Subtarget.hasAVX512())
1234 setOperationAction(ISD::BITCAST, MVT::v32i1, Custom);
1235
1236 // In the customized shift lowering, the legal v8i32/v4i64 cases
1237 // in AVX2 will be recognized.
1238 for (auto VT : { MVT::v32i8, MVT::v16i16, MVT::v8i32, MVT::v4i64 }) {
1239 setOperationAction(ISD::SRL, VT, Custom);
1240 setOperationAction(ISD::SHL, VT, Custom);
1241 setOperationAction(ISD::SRA, VT, Custom);
1242 }
1243
1244 // These types need custom splitting if their input is a 128-bit vector.
1245 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i64, Custom);
1246 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom);
1247 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i64, Custom);
1248 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i32, Custom);
1249
1250 setOperationAction(ISD::ROTL, MVT::v8i32, Custom);
1251 setOperationAction(ISD::ROTL, MVT::v16i16, Custom);
1252
1253 // With BWI, expanding (and promoting the shifts) is the better.
1254 if (!Subtarget.hasBWI())
1255 setOperationAction(ISD::ROTL, MVT::v32i8, Custom);
1256
1257 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1258 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1259 setOperationAction(ISD::SELECT, MVT::v8i32, Custom);
1260 setOperationAction(ISD::SELECT, MVT::v16i16, Custom);
1261 setOperationAction(ISD::SELECT, MVT::v32i8, Custom);
1262 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1263
1264 for (auto VT : { MVT::v16i16, MVT::v8i32, MVT::v4i64 }) {
1265 setOperationAction(ISD::SIGN_EXTEND, VT, Custom);
1266 setOperationAction(ISD::ZERO_EXTEND, VT, Custom);
1267 setOperationAction(ISD::ANY_EXTEND, VT, Custom);
1268 }
1269
1270 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1271 setOperationAction(ISD::TRUNCATE, MVT::v8i16, Custom);
1272 setOperationAction(ISD::TRUNCATE, MVT::v4i32, Custom);
1273 setOperationAction(ISD::BITREVERSE, MVT::v32i8, Custom);
1274
1275 for (auto VT : { MVT::v32i8, MVT::v16i16, MVT::v8i32, MVT::v4i64 }) {
1276 setOperationAction(ISD::SETCC, VT, Custom);
1277 setOperationAction(ISD::STRICT_FSETCC, VT, Custom);
1278 setOperationAction(ISD::STRICT_FSETCCS, VT, Custom);
1279 setOperationAction(ISD::CTPOP, VT, Custom);
1280 setOperationAction(ISD::CTLZ, VT, Custom);
1281
1282 // The condition codes aren't legal in SSE/AVX and under AVX512 we use
1283 // setcc all the way to isel and prefer SETGT in some isel patterns.
1284 setCondCodeAction(ISD::SETLT, VT, Custom);
1285 setCondCodeAction(ISD::SETLE, VT, Custom);
1286 }
1287
1288 if (Subtarget.hasAnyFMA()) {
1289 for (auto VT : { MVT::f32, MVT::f64, MVT::v4f32, MVT::v8f32,
1290 MVT::v2f64, MVT::v4f64 }) {
1291 setOperationAction(ISD::FMA, VT, Legal);
1292 setOperationAction(ISD::STRICT_FMA, VT, Legal);
1293 }
1294 }
1295
1296 for (auto VT : { MVT::v32i8, MVT::v16i16, MVT::v8i32, MVT::v4i64 }) {
1297 setOperationAction(ISD::ADD, VT, HasInt256 ? Legal : Custom);
1298 setOperationAction(ISD::SUB, VT, HasInt256 ? Legal : Custom);
1299 }
1300
1301 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1302 setOperationAction(ISD::MUL, MVT::v8i32, HasInt256 ? Legal : Custom);
1303 setOperationAction(ISD::MUL, MVT::v16i16, HasInt256 ? Legal : Custom);
1304 setOperationAction(ISD::MUL, MVT::v32i8, Custom);
1305
1306 setOperationAction(ISD::MULHU, MVT::v8i32, Custom);
1307 setOperationAction(ISD::MULHS, MVT::v8i32, Custom);
1308 setOperationAction(ISD::MULHU, MVT::v16i16, HasInt256 ? Legal : Custom);
1309 setOperationAction(ISD::MULHS, MVT::v16i16, HasInt256 ? Legal : Custom);
1310 setOperationAction(ISD::MULHU, MVT::v32i8, Custom);
1311 setOperationAction(ISD::MULHS, MVT::v32i8, Custom);
1312
1313 setOperationAction(ISD::ABS, MVT::v4i64, Custom);
1314 setOperationAction(ISD::SMAX, MVT::v4i64, Custom);
1315 setOperationAction(ISD::UMAX, MVT::v4i64, Custom);
1316 setOperationAction(ISD::SMIN, MVT::v4i64, Custom);
1317 setOperationAction(ISD::UMIN, MVT::v4i64, Custom);
1318
1319 setOperationAction(ISD::UADDSAT, MVT::v32i8, HasInt256 ? Legal : Custom);
1320 setOperationAction(ISD::SADDSAT, MVT::v32i8, HasInt256 ? Legal : Custom);
1321 setOperationAction(ISD::USUBSAT, MVT::v32i8, HasInt256 ? Legal : Custom);
1322 setOperationAction(ISD::SSUBSAT, MVT::v32i8, HasInt256 ? Legal : Custom);
1323 setOperationAction(ISD::UADDSAT, MVT::v16i16, HasInt256 ? Legal : Custom);
1324 setOperationAction(ISD::SADDSAT, MVT::v16i16, HasInt256 ? Legal : Custom);
1325 setOperationAction(ISD::USUBSAT, MVT::v16i16, HasInt256 ? Legal : Custom);
1326 setOperationAction(ISD::SSUBSAT, MVT::v16i16, HasInt256 ? Legal : Custom);
1327
1328 for (auto VT : { MVT::v32i8, MVT::v16i16, MVT::v8i32 }) {
1329 setOperationAction(ISD::ABS, VT, HasInt256 ? Legal : Custom);
1330 setOperationAction(ISD::SMAX, VT, HasInt256 ? Legal : Custom);
1331 setOperationAction(ISD::UMAX, VT, HasInt256 ? Legal : Custom);
1332 setOperationAction(ISD::SMIN, VT, HasInt256 ? Legal : Custom);
1333 setOperationAction(ISD::UMIN, VT, HasInt256 ? Legal : Custom);
1334 }
1335
1336 for (auto VT : {MVT::v16i16, MVT::v8i32, MVT::v4i64}) {
1337 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, VT, Custom);
1338 setOperationAction(ISD::ZERO_EXTEND_VECTOR_INREG, VT, Custom);
1339 }
1340
1341 if (HasInt256) {
1342 // The custom lowering for UINT_TO_FP for v8i32 becomes interesting
1343 // when we have a 256bit-wide blend with immediate.
1344 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Custom);
1345 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::v8i32, Custom);
1346
1347 // AVX2 also has wider vector sign/zero extending loads, VPMOV[SZ]X
1348 for (auto LoadExtOp : { ISD::SEXTLOAD, ISD::ZEXTLOAD }) {
1349 setLoadExtAction(LoadExtOp, MVT::v16i16, MVT::v16i8, Legal);
1350 setLoadExtAction(LoadExtOp, MVT::v8i32, MVT::v8i8, Legal);
1351 setLoadExtAction(LoadExtOp, MVT::v4i64, MVT::v4i8, Legal);
1352 setLoadExtAction(LoadExtOp, MVT::v8i32, MVT::v8i16, Legal);
1353 setLoadExtAction(LoadExtOp, MVT::v4i64, MVT::v4i16, Legal);
1354 setLoadExtAction(LoadExtOp, MVT::v4i64, MVT::v4i32, Legal);
1355 }
1356 }
1357
1358 for (auto VT : { MVT::v4i32, MVT::v8i32, MVT::v2i64, MVT::v4i64,
1359 MVT::v4f32, MVT::v8f32, MVT::v2f64, MVT::v4f64 }) {
1360 setOperationAction(ISD::MLOAD, VT, Subtarget.hasVLX() ? Legal : Custom);
1361 setOperationAction(ISD::MSTORE, VT, Legal);
1362 }
1363
1364 // Extract subvector is special because the value type
1365 // (result) is 128-bit but the source is 256-bit wide.
1366 for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64,
1367 MVT::v4f32, MVT::v2f64 }) {
1368 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
1369 }
1370
1371 // Custom lower several nodes for 256-bit types.
1372 for (MVT VT : { MVT::v32i8, MVT::v16i16, MVT::v8i32, MVT::v4i64,
1373 MVT::v8f32, MVT::v4f64 }) {
1374 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1375 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1376 setOperationAction(ISD::VSELECT, VT, Custom);
1377 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1378 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1379 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1380 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Legal);
1381 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1382 setOperationAction(ISD::STORE, VT, Custom);
1383 }
1384
1385 if (HasInt256) {
1386 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1387
1388 // Custom legalize 2x32 to get a little better code.
1389 setOperationAction(ISD::MGATHER, MVT::v2f32, Custom);
1390 setOperationAction(ISD::MGATHER, MVT::v2i32, Custom);
1391
1392 for (auto VT : { MVT::v4i32, MVT::v8i32, MVT::v2i64, MVT::v4i64,
1393 MVT::v4f32, MVT::v8f32, MVT::v2f64, MVT::v4f64 })
1394 setOperationAction(ISD::MGATHER, VT, Custom);
1395 }
1396 }
1397
1398 // This block controls legalization of the mask vector sizes that are
1399 // available with AVX512. 512-bit vectors are in a separate block controlled
1400 // by useAVX512Regs.
1401 if (!Subtarget.useSoftFloat() && Subtarget.hasAVX512()) {
1402 addRegisterClass(MVT::v1i1, &X86::VK1RegClass);
1403 addRegisterClass(MVT::v2i1, &X86::VK2RegClass);
1404 addRegisterClass(MVT::v4i1, &X86::VK4RegClass);
1405 addRegisterClass(MVT::v8i1, &X86::VK8RegClass);
1406 addRegisterClass(MVT::v16i1, &X86::VK16RegClass);
1407
1408 setOperationAction(ISD::SELECT, MVT::v1i1, Custom);
1409 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v1i1, Custom);
1410 setOperationAction(ISD::BUILD_VECTOR, MVT::v1i1, Custom);
1411
1412 setOperationPromotedToType(ISD::FP_TO_SINT, MVT::v8i1, MVT::v8i32);
1413 setOperationPromotedToType(ISD::FP_TO_UINT, MVT::v8i1, MVT::v8i32);
1414 setOperationPromotedToType(ISD::FP_TO_SINT, MVT::v4i1, MVT::v4i32);
1415 setOperationPromotedToType(ISD::FP_TO_UINT, MVT::v4i1, MVT::v4i32);
1416 setOperationPromotedToType(ISD::STRICT_FP_TO_SINT, MVT::v8i1, MVT::v8i32);
1417 setOperationPromotedToType(ISD::STRICT_FP_TO_UINT, MVT::v8i1, MVT::v8i32);
1418 setOperationPromotedToType(ISD::STRICT_FP_TO_SINT, MVT::v4i1, MVT::v4i32);
1419 setOperationPromotedToType(ISD::STRICT_FP_TO_UINT, MVT::v4i1, MVT::v4i32);
1420 setOperationAction(ISD::FP_TO_SINT, MVT::v2i1, Custom);
1421 setOperationAction(ISD::FP_TO_UINT, MVT::v2i1, Custom);
1422 setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::v2i1, Custom);
1423 setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::v2i1, Custom);
1424
1425 // There is no byte sized k-register load or store without AVX512DQ.
1426 if (!Subtarget.hasDQI()) {
1427 setOperationAction(ISD::LOAD, MVT::v1i1, Custom);
1428 setOperationAction(ISD::LOAD, MVT::v2i1, Custom);
1429 setOperationAction(ISD::LOAD, MVT::v4i1, Custom);
1430 setOperationAction(ISD::LOAD, MVT::v8i1, Custom);
1431
1432 setOperationAction(ISD::STORE, MVT::v1i1, Custom);
1433 setOperationAction(ISD::STORE, MVT::v2i1, Custom);
1434 setOperationAction(ISD::STORE, MVT::v4i1, Custom);
1435 setOperationAction(ISD::STORE, MVT::v8i1, Custom);
1436 }
1437
1438 // Extends of v16i1/v8i1/v4i1/v2i1 to 128-bit vectors.
1439 for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64 }) {
1440 setOperationAction(ISD::SIGN_EXTEND, VT, Custom);
1441 setOperationAction(ISD::ZERO_EXTEND, VT, Custom);
1442 setOperationAction(ISD::ANY_EXTEND, VT, Custom);
1443 }
1444
1445 for (auto VT : { MVT::v1i1, MVT::v2i1, MVT::v4i1, MVT::v8i1, MVT::v16i1 }) {
1446 setOperationAction(ISD::ADD, VT, Custom);
1447 setOperationAction(ISD::SUB, VT, Custom);
1448 setOperationAction(ISD::MUL, VT, Custom);
1449 setOperationAction(ISD::UADDSAT, VT, Custom);
1450 setOperationAction(ISD::SADDSAT, VT, Custom);
1451 setOperationAction(ISD::USUBSAT, VT, Custom);
1452 setOperationAction(ISD::SSUBSAT, VT, Custom);
1453 setOperationAction(ISD::VSELECT, VT, Expand);
1454 }
1455
1456 for (auto VT : { MVT::v2i1, MVT::v4i1, MVT::v8i1, MVT::v16i1 }) {
1457 setOperationAction(ISD::SETCC, VT, Custom);
1458 setOperationAction(ISD::STRICT_FSETCC, VT, Custom);
1459 setOperationAction(ISD::STRICT_FSETCCS, VT, Custom);
1460 setOperationAction(ISD::SELECT, VT, Custom);
1461 setOperationAction(ISD::TRUNCATE, VT, Custom);
1462
1463 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1464 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1465 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1466 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1467 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1468 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1469 }
1470
1471 for (auto VT : { MVT::v1i1, MVT::v2i1, MVT::v4i1, MVT::v8i1 })
1472 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1473 }
1474
1475 // This block controls legalization for 512-bit operations with 32/64 bit
1476 // elements. 512-bits can be disabled based on prefer-vector-width and
1477 // required-vector-width function attributes.
1478 if (!Subtarget.useSoftFloat() && Subtarget.useAVX512Regs()) {
1479 addRegisterClass(MVT::v16i32, &X86::VR512RegClass);
1480 addRegisterClass(MVT::v16f32, &X86::VR512RegClass);
1481 addRegisterClass(MVT::v8i64, &X86::VR512RegClass);
1482 addRegisterClass(MVT::v8f64, &X86::VR512RegClass);
1483
1484 for (auto ExtType : {ISD::ZEXTLOAD, ISD::SEXTLOAD}) {
1485 setLoadExtAction(ExtType, MVT::v16i32, MVT::v16i8, Legal);
1486 setLoadExtAction(ExtType, MVT::v16i32, MVT::v16i16, Legal);
1487 setLoadExtAction(ExtType, MVT::v8i64, MVT::v8i8, Legal);
1488 setLoadExtAction(ExtType, MVT::v8i64, MVT::v8i16, Legal);
1489 setLoadExtAction(ExtType, MVT::v8i64, MVT::v8i32, Legal);
1490 }
1491
1492 for (MVT VT : { MVT::v16f32, MVT::v8f64 }) {
1493 setOperationAction(ISD::FNEG, VT, Custom);
1494 setOperationAction(ISD::FABS, VT, Custom);
1495 setOperationAction(ISD::FMA, VT, Legal);
1496 setOperationAction(ISD::STRICT_FMA, VT, Legal);
1497 setOperationAction(ISD::FCOPYSIGN, VT, Custom);
1498 }
1499
1500 for (MVT VT : { MVT::v16i1, MVT::v16i8, MVT::v16i16 }) {
1501 setOperationPromotedToType(ISD::FP_TO_SINT , VT, MVT::v16i32);
1502 setOperationPromotedToType(ISD::FP_TO_UINT , VT, MVT::v16i32);
1503 setOperationPromotedToType(ISD::STRICT_FP_TO_SINT, VT, MVT::v16i32);
1504 setOperationPromotedToType(ISD::STRICT_FP_TO_UINT, VT, MVT::v16i32);
1505 }
1506 setOperationAction(ISD::FP_TO_SINT, MVT::v16i32, Legal);
1507 setOperationAction(ISD::FP_TO_UINT, MVT::v16i32, Legal);
1508 setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::v16i32, Legal);
1509 setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::v16i32, Legal);
1510 setOperationAction(ISD::SINT_TO_FP, MVT::v16i32, Legal);
1511 setOperationAction(ISD::UINT_TO_FP, MVT::v16i32, Legal);
1512 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::v16i32, Legal);
1513 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::v16i32, Legal);
1514
1515 setOperationAction(ISD::STRICT_FADD, MVT::v16f32, Legal);
1516 setOperationAction(ISD::STRICT_FADD, MVT::v8f64, Legal);
1517 setOperationAction(ISD::STRICT_FSUB, MVT::v16f32, Legal);
1518 setOperationAction(ISD::STRICT_FSUB, MVT::v8f64, Legal);
1519 setOperationAction(ISD::STRICT_FMUL, MVT::v16f32, Legal);
1520 setOperationAction(ISD::STRICT_FMUL, MVT::v8f64, Legal);
1521 setOperationAction(ISD::STRICT_FDIV, MVT::v16f32, Legal);
1522 setOperationAction(ISD::STRICT_FDIV, MVT::v8f64, Legal);
1523 setOperationAction(ISD::STRICT_FSQRT, MVT::v16f32, Legal);
1524 setOperationAction(ISD::STRICT_FSQRT, MVT::v8f64, Legal);
1525 setOperationAction(ISD::STRICT_FP_EXTEND, MVT::v8f64, Legal);
1526 setOperationAction(ISD::STRICT_FP_ROUND, MVT::v8f32, Legal);
1527
1528 setTruncStoreAction(MVT::v8i64, MVT::v8i8, Legal);
1529 setTruncStoreAction(MVT::v8i64, MVT::v8i16, Legal);
1530 setTruncStoreAction(MVT::v8i64, MVT::v8i32, Legal);
1531 setTruncStoreAction(MVT::v16i32, MVT::v16i8, Legal);
1532 setTruncStoreAction(MVT::v16i32, MVT::v16i16, Legal);
1533
1534 // With 512-bit vectors and no VLX, we prefer to widen MLOAD/MSTORE
1535 // to 512-bit rather than use the AVX2 instructions so that we can use
1536 // k-masks.
1537 if (!Subtarget.hasVLX()) {
1538 for (auto VT : {MVT::v4i32, MVT::v8i32, MVT::v2i64, MVT::v4i64,
1539 MVT::v4f32, MVT::v8f32, MVT::v2f64, MVT::v4f64}) {
1540 setOperationAction(ISD::MLOAD, VT, Custom);
1541 setOperationAction(ISD::MSTORE, VT, Custom);
1542 }
1543 }
1544
1545 setOperationAction(ISD::TRUNCATE, MVT::v8i32, Custom);
1546 setOperationAction(ISD::TRUNCATE, MVT::v16i16, Custom);
1547 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i32, Custom);
1548 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i64, Custom);
1549 setOperationAction(ISD::ANY_EXTEND, MVT::v16i32, Custom);
1550 setOperationAction(ISD::ANY_EXTEND, MVT::v8i64, Custom);
1551 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom);
1552 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i64, Custom);
1553
1554 // Need to custom widen this if we don't have AVX512BW.
1555 setOperationAction(ISD::ANY_EXTEND, MVT::v8i8, Custom);
1556 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i8, Custom);
1557 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i8, Custom);
1558
1559 for (auto VT : { MVT::v16f32, MVT::v8f64 }) {
1560 setOperationAction(ISD::FFLOOR, VT, Legal);
1561 setOperationAction(ISD::STRICT_FFLOOR, VT, Legal);
1562 setOperationAction(ISD::FCEIL, VT, Legal);
1563 setOperationAction(ISD::STRICT_FCEIL, VT, Legal);
1564 setOperationAction(ISD::FTRUNC, VT, Legal);
1565 setOperationAction(ISD::STRICT_FTRUNC, VT, Legal);
1566 setOperationAction(ISD::FRINT, VT, Legal);
1567 setOperationAction(ISD::STRICT_FRINT, VT, Legal);
1568 setOperationAction(ISD::FNEARBYINT, VT, Legal);
1569 setOperationAction(ISD::STRICT_FNEARBYINT, VT, Legal);
1570
1571 setOperationAction(ISD::FROUND, VT, Custom);
1572
1573 setOperationAction(ISD::SELECT, VT, Custom);
1574 }
1575
1576 // Without BWI we need to use custom lowering to handle MVT::v64i8 input.
1577 for (auto VT : {MVT::v16i32, MVT::v8i64, MVT::v64i8}) {
1578 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, VT, Custom);
1579 setOperationAction(ISD::ZERO_EXTEND_VECTOR_INREG, VT, Custom);
1580 }
1581
1582 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f64, Custom);
1583 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i64, Custom);
1584 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16f32, Custom);
1585 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i32, Custom);
1586
1587 setOperationAction(ISD::MUL, MVT::v8i64, Custom);
1588 setOperationAction(ISD::MUL, MVT::v16i32, Legal);
1589
1590 setOperationAction(ISD::MULHU, MVT::v16i32, Custom);
1591 setOperationAction(ISD::MULHS, MVT::v16i32, Custom);
1592
1593 for (auto VT : { MVT::v16i32, MVT::v8i64 }) {
1594 setOperationAction(ISD::SMAX, VT, Legal);
1595 setOperationAction(ISD::UMAX, VT, Legal);
1596 setOperationAction(ISD::SMIN, VT, Legal);
1597 setOperationAction(ISD::UMIN, VT, Legal);
1598 setOperationAction(ISD::ABS, VT, Legal);
1599 setOperationAction(ISD::SRL, VT, Custom);
1600 setOperationAction(ISD::SHL, VT, Custom);
1601 setOperationAction(ISD::SRA, VT, Custom);
1602 setOperationAction(ISD::CTPOP, VT, Custom);
1603 setOperationAction(ISD::ROTL, VT, Custom);
1604 setOperationAction(ISD::ROTR, VT, Custom);
1605 setOperationAction(ISD::SETCC, VT, Custom);
1606 setOperationAction(ISD::STRICT_FSETCC, VT, Custom);
1607 setOperationAction(ISD::STRICT_FSETCCS, VT, Custom);
1608 setOperationAction(ISD::SELECT, VT, Custom);
1609
1610 // The condition codes aren't legal in SSE/AVX and under AVX512 we use
1611 // setcc all the way to isel and prefer SETGT in some isel patterns.
1612 setCondCodeAction(ISD::SETLT, VT, Custom);
1613 setCondCodeAction(ISD::SETLE, VT, Custom);
1614 }
1615
1616 if (Subtarget.hasDQI()) {
1617 setOperationAction(ISD::SINT_TO_FP, MVT::v8i64, Legal);
1618 setOperationAction(ISD::UINT_TO_FP, MVT::v8i64, Legal);
1619 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::v8i64, Legal);
1620 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::v8i64, Legal);
1621 setOperationAction(ISD::FP_TO_SINT, MVT::v8i64, Legal);
1622 setOperationAction(ISD::FP_TO_UINT, MVT::v8i64, Legal);
1623 setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::v8i64, Legal);
1624 setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::v8i64, Legal);
1625
1626 setOperationAction(ISD::MUL, MVT::v8i64, Legal);
1627 }
1628
1629 if (Subtarget.hasCDI()) {
1630 // NonVLX sub-targets extend 128/256 vectors to use the 512 version.
1631 for (auto VT : { MVT::v16i32, MVT::v8i64} ) {
1632 setOperationAction(ISD::CTLZ, VT, Legal);
1633 }
1634 } // Subtarget.hasCDI()
1635
1636 if (Subtarget.hasVPOPCNTDQ()) {
1637 for (auto VT : { MVT::v16i32, MVT::v8i64 })
1638 setOperationAction(ISD::CTPOP, VT, Legal);
1639 }
1640
1641 // Extract subvector is special because the value type
1642 // (result) is 256-bit but the source is 512-bit wide.
1643 // 128-bit was made Legal under AVX1.
1644 for (auto VT : { MVT::v32i8, MVT::v16i16, MVT::v8i32, MVT::v4i64,
1645 MVT::v8f32, MVT::v4f64 })
1646 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
1647
1648 for (auto VT : { MVT::v16i32, MVT::v8i64, MVT::v16f32, MVT::v8f64 }) {
1649 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1650 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1651 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1652 setOperationAction(ISD::VSELECT, VT, Custom);
1653 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1654 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1655 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Legal);
1656 setOperationAction(ISD::MLOAD, VT, Legal);
1657 setOperationAction(ISD::MSTORE, VT, Legal);
1658 setOperationAction(ISD::MGATHER, VT, Custom);
1659 setOperationAction(ISD::MSCATTER, VT, Custom);
1660 }
1661 if (!Subtarget.hasBWI()) {
1662 // Need to custom split v32i16/v64i8 bitcasts.
1663 setOperationAction(ISD::BITCAST, MVT::v32i16, Custom);
1664 setOperationAction(ISD::BITCAST, MVT::v64i8, Custom);
1665
1666 // Better to split these into two 256-bit ops.
1667 setOperationAction(ISD::BITREVERSE, MVT::v8i64, Custom);
1668 setOperationAction(ISD::BITREVERSE, MVT::v16i32, Custom);
1669 }
1670
1671 if (Subtarget.hasVBMI2()) {
1672 for (auto VT : { MVT::v16i32, MVT::v8i64 }) {
1673 setOperationAction(ISD::FSHL, VT, Custom);
1674 setOperationAction(ISD::FSHR, VT, Custom);
1675 }
1676 }
1677 }// has AVX-512
1678
1679 // This block controls legalization for operations that don't have
1680 // pre-AVX512 equivalents. Without VLX we use 512-bit operations for
1681 // narrower widths.
1682 if (!Subtarget.useSoftFloat() && Subtarget.hasAVX512()) {
1683 // These operations are handled on non-VLX by artificially widening in
1684 // isel patterns.
1685
1686 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32,
1687 Subtarget.hasVLX() ? Legal : Custom);
1688 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32,
1689 Subtarget.hasVLX() ? Legal : Custom);
1690 setOperationAction(ISD::FP_TO_UINT, MVT::v2i32, Custom);
1691 setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::v8i32,
1692 Subtarget.hasVLX() ? Legal : Custom);
1693 setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::v4i32,
1694 Subtarget.hasVLX() ? Legal : Custom);
1695 setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::v2i32, Custom);
1696 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32,
1697 Subtarget.hasVLX() ? Legal : Custom);
1698 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32,
1699 Subtarget.hasVLX() ? Legal : Custom);
1700 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::v8i32,
1701 Subtarget.hasVLX() ? Legal : Custom);
1702 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::v4i32,
1703 Subtarget.hasVLX() ? Legal : Custom);
1704
1705 for (auto VT : { MVT::v2i64, MVT::v4i64 }) {
1706 setOperationAction(ISD::SMAX, VT, Legal);
1707 setOperationAction(ISD::UMAX, VT, Legal);
1708 setOperationAction(ISD::SMIN, VT, Legal);
1709 setOperationAction(ISD::UMIN, VT, Legal);
1710 setOperationAction(ISD::ABS, VT, Legal);
1711 }
1712
1713 for (auto VT : { MVT::v4i32, MVT::v8i32, MVT::v2i64, MVT::v4i64 }) {
1714 setOperationAction(ISD::ROTL, VT, Custom);
1715 setOperationAction(ISD::ROTR, VT, Custom);
1716 }
1717
1718 // Custom legalize 2x32 to get a little better code.
1719 setOperationAction(ISD::MSCATTER, MVT::v2f32, Custom);
1720 setOperationAction(ISD::MSCATTER, MVT::v2i32, Custom);
1721
1722 for (auto VT : { MVT::v4i32, MVT::v8i32, MVT::v2i64, MVT::v4i64,
1723 MVT::v4f32, MVT::v8f32, MVT::v2f64, MVT::v4f64 })
1724 setOperationAction(ISD::MSCATTER, VT, Custom);
1725
1726 if (Subtarget.hasDQI()) {
1727 for (auto VT : { MVT::v2i64, MVT::v4i64 }) {
1728 setOperationAction(ISD::SINT_TO_FP, VT,
1729 Subtarget.hasVLX() ? Legal : Custom);
1730 setOperationAction(ISD::UINT_TO_FP, VT,
1731 Subtarget.hasVLX() ? Legal : Custom);
1732 setOperationAction(ISD::STRICT_SINT_TO_FP, VT,
1733 Subtarget.hasVLX() ? Legal : Custom);
1734 setOperationAction(ISD::STRICT_UINT_TO_FP, VT,
1735 Subtarget.hasVLX() ? Legal : Custom);
1736 setOperationAction(ISD::FP_TO_SINT, VT,
1737 Subtarget.hasVLX() ? Legal : Custom);
1738 setOperationAction(ISD::FP_TO_UINT, VT,
1739 Subtarget.hasVLX() ? Legal : Custom);
1740 setOperationAction(ISD::STRICT_FP_TO_SINT, VT,
1741 Subtarget.hasVLX() ? Legal : Custom);
1742 setOperationAction(ISD::STRICT_FP_TO_UINT, VT,
1743 Subtarget.hasVLX() ? Legal : Custom);
1744 setOperationAction(ISD::MUL, VT, Legal);
1745 }
1746 }
1747
1748 if (Subtarget.hasCDI()) {
1749 for (auto VT : { MVT::v4i32, MVT::v8i32, MVT::v2i64, MVT::v4i64 }) {
1750 setOperationAction(ISD::CTLZ, VT, Legal);
1751 }
1752 } // Subtarget.hasCDI()
1753
1754 if (Subtarget.hasVPOPCNTDQ()) {
1755 for (auto VT : { MVT::v4i32, MVT::v8i32, MVT::v2i64, MVT::v4i64 })
1756 setOperationAction(ISD::CTPOP, VT, Legal);
1757 }
1758 }
1759
1760 // This block control legalization of v32i1/v64i1 which are available with
1761 // AVX512BW. 512-bit v32i16 and v64i8 vector legalization is controlled with
1762 // useBWIRegs.
1763 if (!Subtarget.useSoftFloat() && Subtarget.hasBWI()) {
1764 addRegisterClass(MVT::v32i1, &X86::VK32RegClass);
1765 addRegisterClass(MVT::v64i1, &X86::VK64RegClass);
1766
1767 for (auto VT : { MVT::v32i1, MVT::v64i1 }) {
1768 setOperationAction(ISD::ADD, VT, Custom);
1769 setOperationAction(ISD::SUB, VT, Custom);
1770 setOperationAction(ISD::MUL, VT, Custom);
1771 setOperationAction(ISD::VSELECT, VT, Expand);
1772 setOperationAction(ISD::UADDSAT, VT, Custom);
1773 setOperationAction(ISD::SADDSAT, VT, Custom);
1774 setOperationAction(ISD::USUBSAT, VT, Custom);
1775 setOperationAction(ISD::SSUBSAT, VT, Custom);
1776
1777 setOperationAction(ISD::TRUNCATE, VT, Custom);
1778 setOperationAction(ISD::SETCC, VT, Custom);
1779 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1780 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1781 setOperationAction(ISD::SELECT, VT, Custom);
1782 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1783 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1784 }
1785
1786 setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i1, Custom);
1787 setOperationAction(ISD::CONCAT_VECTORS, MVT::v64i1, Custom);
1788 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v32i1, Custom);
1789 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v64i1, Custom);
1790 for (auto VT : { MVT::v16i1, MVT::v32i1 })
1791 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1792
1793 // Extends from v32i1 masks to 256-bit vectors.
1794 setOperationAction(ISD::SIGN_EXTEND, MVT::v32i8, Custom);
1795 setOperationAction(ISD::ZERO_EXTEND, MVT::v32i8, Custom);
1796 setOperationAction(ISD::ANY_EXTEND, MVT::v32i8, Custom);
1797 }
1798
1799 // This block controls legalization for v32i16 and v64i8. 512-bits can be
1800 // disabled based on prefer-vector-width and required-vector-width function
1801 // attributes.
1802 if (!Subtarget.useSoftFloat() && Subtarget.useBWIRegs()) {
1803 addRegisterClass(MVT::v32i16, &X86::VR512RegClass);
1804 addRegisterClass(MVT::v64i8, &X86::VR512RegClass);
1805
1806 // Extends from v64i1 masks to 512-bit vectors.
1807 setOperationAction(ISD::SIGN_EXTEND, MVT::v64i8, Custom);
1808 setOperationAction(ISD::ZERO_EXTEND, MVT::v64i8, Custom);
1809 setOperationAction(ISD::ANY_EXTEND, MVT::v64i8, Custom);
1810
1811 setOperationAction(ISD::MUL, MVT::v32i16, Legal);
1812 setOperationAction(ISD::MUL, MVT::v64i8, Custom);
1813 setOperationAction(ISD::MULHS, MVT::v32i16, Legal);
1814 setOperationAction(ISD::MULHU, MVT::v32i16, Legal);
1815 setOperationAction(ISD::MULHS, MVT::v64i8, Custom);
1816 setOperationAction(ISD::MULHU, MVT::v64i8, Custom);
1817 setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i16, Custom);
1818 setOperationAction(ISD::CONCAT_VECTORS, MVT::v64i8, Custom);
1819 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v32i16, Legal);
1820 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v64i8, Legal);
1821 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v32i16, Custom);
1822 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v64i8, Custom);
1823 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v32i16, Custom);
1824 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v64i8, Custom);
1825 setOperationAction(ISD::SIGN_EXTEND, MVT::v32i16, Custom);
1826 setOperationAction(ISD::ZERO_EXTEND, MVT::v32i16, Custom);
1827 setOperationAction(ISD::ANY_EXTEND, MVT::v32i16, Custom);
1828 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v32i16, Custom);
1829 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v64i8, Custom);
1830 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v32i16, Custom);
1831 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v64i8, Custom);
1832 setOperationAction(ISD::TRUNCATE, MVT::v32i8, Custom);
1833 setOperationAction(ISD::BITREVERSE, MVT::v64i8, Custom);
1834
1835 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v32i16, Custom);
1836 setOperationAction(ISD::ZERO_EXTEND_VECTOR_INREG, MVT::v32i16, Custom);
1837
1838 setTruncStoreAction(MVT::v32i16, MVT::v32i8, Legal);
1839
1840 for (auto VT : { MVT::v64i8, MVT::v32i16 }) {
1841 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1842 setOperationAction(ISD::VSELECT, VT, Custom);
1843 setOperationAction(ISD::ABS, VT, Legal);
1844 setOperationAction(ISD::SRL, VT, Custom);
1845 setOperationAction(ISD::SHL, VT, Custom);
1846 setOperationAction(ISD::SRA, VT, Custom);
1847 setOperationAction(ISD::MLOAD, VT, Legal);
1848 setOperationAction(ISD::MSTORE, VT, Legal);
1849 setOperationAction(ISD::CTPOP, VT, Custom);
1850 setOperationAction(ISD::CTLZ, VT, Custom);
1851 setOperationAction(ISD::SMAX, VT, Legal);
1852 setOperationAction(ISD::UMAX, VT, Legal);
1853 setOperationAction(ISD::SMIN, VT, Legal);
1854 setOperationAction(ISD::UMIN, VT, Legal);
1855 setOperationAction(ISD::SETCC, VT, Custom);
1856 setOperationAction(ISD::UADDSAT, VT, Legal);
1857 setOperationAction(ISD::SADDSAT, VT, Legal);
1858 setOperationAction(ISD::USUBSAT, VT, Legal);
1859 setOperationAction(ISD::SSUBSAT, VT, Legal);
1860 setOperationAction(ISD::SELECT, VT, Custom);
1861
1862 // The condition codes aren't legal in SSE/AVX and under AVX512 we use
1863 // setcc all the way to isel and prefer SETGT in some isel patterns.
1864 setCondCodeAction(ISD::SETLT, VT, Custom);
1865 setCondCodeAction(ISD::SETLE, VT, Custom);
1866 }
1867
1868 for (auto ExtType : {ISD::ZEXTLOAD, ISD::SEXTLOAD}) {
1869 setLoadExtAction(ExtType, MVT::v32i16, MVT::v32i8, Legal);
1870 }
1871
1872 if (Subtarget.hasBITALG()) {
1873 for (auto VT : { MVT::v64i8, MVT::v32i16 })
1874 setOperationAction(ISD::CTPOP, VT, Legal);
1875 }
1876
1877 if (Subtarget.hasVBMI2()) {
1878 setOperationAction(ISD::FSHL, MVT::v32i16, Custom);
1879 setOperationAction(ISD::FSHR, MVT::v32i16, Custom);
1880 }
1881 }
1882
1883 if (!Subtarget.useSoftFloat() && Subtarget.hasBWI()) {
1884 for (auto VT : { MVT::v32i8, MVT::v16i8, MVT::v16i16, MVT::v8i16 }) {
1885 setOperationAction(ISD::MLOAD, VT, Subtarget.hasVLX() ? Legal : Custom);
1886 setOperationAction(ISD::MSTORE, VT, Subtarget.hasVLX() ? Legal : Custom);
1887 }
1888
1889 // These operations are handled on non-VLX by artificially widening in
1890 // isel patterns.
1891 // TODO: Custom widen in lowering on non-VLX and drop the isel patterns?
1892
1893 if (Subtarget.hasBITALG()) {
1894 for (auto VT : { MVT::v16i8, MVT::v32i8, MVT::v8i16, MVT::v16i16 })
1895 setOperationAction(ISD::CTPOP, VT, Legal);
1896 }
1897 }
1898
1899 if (!Subtarget.useSoftFloat() && Subtarget.hasVLX()) {
1900 setTruncStoreAction(MVT::v4i64, MVT::v4i8, Legal);
1901 setTruncStoreAction(MVT::v4i64, MVT::v4i16, Legal);
1902 setTruncStoreAction(MVT::v4i64, MVT::v4i32, Legal);
1903 setTruncStoreAction(MVT::v8i32, MVT::v8i8, Legal);
1904 setTruncStoreAction(MVT::v8i32, MVT::v8i16, Legal);
1905
1906 setTruncStoreAction(MVT::v2i64, MVT::v2i8, Legal);
1907 setTruncStoreAction(MVT::v2i64, MVT::v2i16, Legal);
1908 setTruncStoreAction(MVT::v2i64, MVT::v2i32, Legal);
1909 setTruncStoreAction(MVT::v4i32, MVT::v4i8, Legal);
1910 setTruncStoreAction(MVT::v4i32, MVT::v4i16, Legal);
1911
1912 if (Subtarget.hasDQI()) {
1913 // Fast v2f32 SINT_TO_FP( v2i64 ) custom conversion.
1914 // v2f32 UINT_TO_FP is already custom under SSE2.
1915 assert(isOperationCustom(ISD::UINT_TO_FP, MVT::v2f32) &&((isOperationCustom(ISD::UINT_TO_FP, MVT::v2f32) && isOperationCustom
(ISD::STRICT_UINT_TO_FP, MVT::v2f32) && "Unexpected operation action!"
) ? static_cast<void> (0) : __assert_fail ("isOperationCustom(ISD::UINT_TO_FP, MVT::v2f32) && isOperationCustom(ISD::STRICT_UINT_TO_FP, MVT::v2f32) && \"Unexpected operation action!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 1917, __PRETTY_FUNCTION__))
1916 isOperationCustom(ISD::STRICT_UINT_TO_FP, MVT::v2f32) &&((isOperationCustom(ISD::UINT_TO_FP, MVT::v2f32) && isOperationCustom
(ISD::STRICT_UINT_TO_FP, MVT::v2f32) && "Unexpected operation action!"
) ? static_cast<void> (0) : __assert_fail ("isOperationCustom(ISD::UINT_TO_FP, MVT::v2f32) && isOperationCustom(ISD::STRICT_UINT_TO_FP, MVT::v2f32) && \"Unexpected operation action!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 1917, __PRETTY_FUNCTION__))
1917 "Unexpected operation action!")((isOperationCustom(ISD::UINT_TO_FP, MVT::v2f32) && isOperationCustom
(ISD::STRICT_UINT_TO_FP, MVT::v2f32) && "Unexpected operation action!"
) ? static_cast<void> (0) : __assert_fail ("isOperationCustom(ISD::UINT_TO_FP, MVT::v2f32) && isOperationCustom(ISD::STRICT_UINT_TO_FP, MVT::v2f32) && \"Unexpected operation action!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 1917, __PRETTY_FUNCTION__))
;
1918 // v2i64 FP_TO_S/UINT(v2f32) custom conversion.
1919 setOperationAction(ISD::FP_TO_SINT, MVT::v2f32, Custom);
1920 setOperationAction(ISD::FP_TO_UINT, MVT::v2f32, Custom);
1921 setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::v2f32, Custom);
1922 setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::v2f32, Custom);
1923 }
1924
1925 if (Subtarget.hasBWI()) {
1926 setTruncStoreAction(MVT::v16i16, MVT::v16i8, Legal);
1927 setTruncStoreAction(MVT::v8i16, MVT::v8i8, Legal);
1928 }
1929
1930 if (Subtarget.hasVBMI2()) {
1931 // TODO: Make these legal even without VLX?
1932 for (auto VT : { MVT::v8i16, MVT::v4i32, MVT::v2i64,
1933 MVT::v16i16, MVT::v8i32, MVT::v4i64 }) {
1934 setOperationAction(ISD::FSHL, VT, Custom);
1935 setOperationAction(ISD::FSHR, VT, Custom);
1936 }
1937 }
1938
1939 setOperationAction(ISD::TRUNCATE, MVT::v16i32, Custom);
1940 setOperationAction(ISD::TRUNCATE, MVT::v8i64, Custom);
1941 setOperationAction(ISD::TRUNCATE, MVT::v16i64, Custom);
1942 }
1943
1944 // We want to custom lower some of our intrinsics.
1945 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1946 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
1947 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
1948 if (!Subtarget.is64Bit()) {
1949 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom);
1950 }
1951
1952 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1953 // handle type legalization for these operations here.
1954 //
1955 // FIXME: We really should do custom legalization for addition and
1956 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1957 // than generic legalization for 64-bit multiplication-with-overflow, though.
1958 for (auto VT : { MVT::i8, MVT::i16, MVT::i32, MVT::i64 }) {
1959 if (VT == MVT::i64 && !Subtarget.is64Bit())
1960 continue;
1961 // Add/Sub/Mul with overflow operations are custom lowered.
1962 setOperationAction(ISD::SADDO, VT, Custom);
1963 setOperationAction(ISD::UADDO, VT, Custom);
1964 setOperationAction(ISD::SSUBO, VT, Custom);
1965 setOperationAction(ISD::USUBO, VT, Custom);
1966 setOperationAction(ISD::SMULO, VT, Custom);
1967 setOperationAction(ISD::UMULO, VT, Custom);
1968
1969 // Support carry in as value rather than glue.
1970 setOperationAction(ISD::ADDCARRY, VT, Custom);
1971 setOperationAction(ISD::SUBCARRY, VT, Custom);
1972 setOperationAction(ISD::SETCCCARRY, VT, Custom);
1973 }
1974
1975 if (!Subtarget.is64Bit()) {
1976 // These libcalls are not available in 32-bit.
1977 setLibcallName(RTLIB::SHL_I128, nullptr);
1978 setLibcallName(RTLIB::SRL_I128, nullptr);
1979 setLibcallName(RTLIB::SRA_I128, nullptr);
1980 setLibcallName(RTLIB::MUL_I128, nullptr);
1981 }
1982
1983 // Combine sin / cos into _sincos_stret if it is available.
1984 if (getLibcallName(RTLIB::SINCOS_STRET_F32) != nullptr &&
1985 getLibcallName(RTLIB::SINCOS_STRET_F64) != nullptr) {
1986 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
1987 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
1988 }
1989
1990 if (Subtarget.isTargetWin64()) {
1991 setOperationAction(ISD::SDIV, MVT::i128, Custom);
1992 setOperationAction(ISD::UDIV, MVT::i128, Custom);
1993 setOperationAction(ISD::SREM, MVT::i128, Custom);
1994 setOperationAction(ISD::UREM, MVT::i128, Custom);
1995 setOperationAction(ISD::SDIVREM, MVT::i128, Custom);
1996 setOperationAction(ISD::UDIVREM, MVT::i128, Custom);
1997 }
1998
1999 // On 32 bit MSVC, `fmodf(f32)` is not defined - only `fmod(f64)`
2000 // is. We should promote the value to 64-bits to solve this.
2001 // This is what the CRT headers do - `fmodf` is an inline header
2002 // function casting to f64 and calling `fmod`.
2003 if (Subtarget.is32Bit() &&
2004 (Subtarget.isTargetWindowsMSVC() || Subtarget.isTargetWindowsItanium()))
2005 for (ISD::NodeType Op :
2006 {ISD::FCEIL, ISD::STRICT_FCEIL,
2007 ISD::FCOS, ISD::STRICT_FCOS,
2008 ISD::FEXP, ISD::STRICT_FEXP,
2009 ISD::FFLOOR, ISD::STRICT_FFLOOR,
2010 ISD::FREM, ISD::STRICT_FREM,
2011 ISD::FLOG, ISD::STRICT_FLOG,
2012 ISD::FLOG10, ISD::STRICT_FLOG10,
2013 ISD::FPOW, ISD::STRICT_FPOW,
2014 ISD::FSIN, ISD::STRICT_FSIN})
2015 if (isOperationExpand(Op, MVT::f32))
2016 setOperationAction(Op, MVT::f32, Promote);
2017
2018 // We have target-specific dag combine patterns for the following nodes:
2019 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
2020 setTargetDAGCombine(ISD::SCALAR_TO_VECTOR);
2021 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
2022 setTargetDAGCombine(ISD::CONCAT_VECTORS);
2023 setTargetDAGCombine(ISD::INSERT_SUBVECTOR);
2024 setTargetDAGCombine(ISD::EXTRACT_SUBVECTOR);
2025 setTargetDAGCombine(ISD::BITCAST);
2026 setTargetDAGCombine(ISD::VSELECT);
2027 setTargetDAGCombine(ISD::SELECT);
2028 setTargetDAGCombine(ISD::SHL);
2029 setTargetDAGCombine(ISD::SRA);
2030 setTargetDAGCombine(ISD::SRL);
2031 setTargetDAGCombine(ISD::OR);
2032 setTargetDAGCombine(ISD::AND);
2033 setTargetDAGCombine(ISD::ADD);
2034 setTargetDAGCombine(ISD::FADD);
2035 setTargetDAGCombine(ISD::FSUB);
2036 setTargetDAGCombine(ISD::FNEG);
2037 setTargetDAGCombine(ISD::FMA);
2038 setTargetDAGCombine(ISD::STRICT_FMA);
2039 setTargetDAGCombine(ISD::FMINNUM);
2040 setTargetDAGCombine(ISD::FMAXNUM);
2041 setTargetDAGCombine(ISD::SUB);
2042 setTargetDAGCombine(ISD::LOAD);
2043 setTargetDAGCombine(ISD::MLOAD);
2044 setTargetDAGCombine(ISD::STORE);
2045 setTargetDAGCombine(ISD::MSTORE);
2046 setTargetDAGCombine(ISD::TRUNCATE);
2047 setTargetDAGCombine(ISD::ZERO_EXTEND);
2048 setTargetDAGCombine(ISD::ANY_EXTEND);
2049 setTargetDAGCombine(ISD::SIGN_EXTEND);
2050 setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
2051 setTargetDAGCombine(ISD::ANY_EXTEND_VECTOR_INREG);
2052 setTargetDAGCombine(ISD::SIGN_EXTEND_VECTOR_INREG);
2053 setTargetDAGCombine(ISD::ZERO_EXTEND_VECTOR_INREG);
2054 setTargetDAGCombine(ISD::SINT_TO_FP);
2055 setTargetDAGCombine(ISD::UINT_TO_FP);
2056 setTargetDAGCombine(ISD::STRICT_SINT_TO_FP);
2057 setTargetDAGCombine(ISD::STRICT_UINT_TO_FP);
2058 setTargetDAGCombine(ISD::SETCC);
2059 setTargetDAGCombine(ISD::MUL);
2060 setTargetDAGCombine(ISD::XOR);
2061 setTargetDAGCombine(ISD::MSCATTER);
2062 setTargetDAGCombine(ISD::MGATHER);
2063 setTargetDAGCombine(ISD::FP16_TO_FP);
2064 setTargetDAGCombine(ISD::FP_EXTEND);
2065 setTargetDAGCombine(ISD::STRICT_FP_EXTEND);
2066 setTargetDAGCombine(ISD::FP_ROUND);
2067
2068 computeRegisterProperties(Subtarget.getRegisterInfo());
2069
2070 MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
2071 MaxStoresPerMemsetOptSize = 8;
2072 MaxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
2073 MaxStoresPerMemcpyOptSize = 4;
2074 MaxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
2075 MaxStoresPerMemmoveOptSize = 4;
2076
2077 // TODO: These control memcmp expansion in CGP and could be raised higher, but
2078 // that needs to benchmarked and balanced with the potential use of vector
2079 // load/store types (PR33329, PR33914).
2080 MaxLoadsPerMemcmp = 2;
2081 MaxLoadsPerMemcmpOptSize = 2;
2082
2083 // Set loop alignment to 2^ExperimentalPrefLoopAlignment bytes (default: 2^4).
2084 setPrefLoopAlignment(Align(1ULL << ExperimentalPrefLoopAlignment));
2085
2086 // An out-of-order CPU can speculatively execute past a predictable branch,
2087 // but a conditional move could be stalled by an expensive earlier operation.
2088 PredictableSelectIsExpensive = Subtarget.getSchedModel().isOutOfOrder();
2089 EnableExtLdPromotion = true;
2090 setPrefFunctionAlignment(Align(16));
2091
2092 verifyIntrinsicTables();
2093
2094 // Default to having -disable-strictnode-mutation on
2095 IsStrictFPEnabled = true;
2096}
2097
2098// This has so far only been implemented for 64-bit MachO.
2099bool X86TargetLowering::useLoadStackGuardNode() const {
2100 return Subtarget.isTargetMachO() && Subtarget.is64Bit();
2101}
2102
2103bool X86TargetLowering::useStackGuardXorFP() const {
2104 // Currently only MSVC CRTs XOR the frame pointer into the stack guard value.
2105 return Subtarget.getTargetTriple().isOSMSVCRT() && !Subtarget.isTargetMachO();
2106}
2107
2108SDValue X86TargetLowering::emitStackGuardXorFP(SelectionDAG &DAG, SDValue Val,
2109 const SDLoc &DL) const {
2110 EVT PtrTy = getPointerTy(DAG.getDataLayout());
2111 unsigned XorOp = Subtarget.is64Bit() ? X86::XOR64_FP : X86::XOR32_FP;
2112 MachineSDNode *Node = DAG.getMachineNode(XorOp, DL, PtrTy, Val);
2113 return SDValue(Node, 0);
2114}
2115
2116TargetLoweringBase::LegalizeTypeAction
2117X86TargetLowering::getPreferredVectorAction(MVT VT) const {
2118 if (VT == MVT::v32i1 && Subtarget.hasAVX512() && !Subtarget.hasBWI())
2119 return TypeSplitVector;
2120
2121 if (VT.getVectorNumElements() != 1 &&
2122 VT.getVectorElementType() != MVT::i1)
2123 return TypeWidenVector;
2124
2125 return TargetLoweringBase::getPreferredVectorAction(VT);
2126}
2127
2128static std::pair<MVT, unsigned>
2129handleMaskRegisterForCallingConv(unsigned NumElts, CallingConv::ID CC,
2130 const X86Subtarget &Subtarget) {
2131 // v2i1/v4i1/v8i1/v16i1 all pass in xmm registers unless the calling
2132 // convention is one that uses k registers.
2133 if (NumElts == 2)
2134 return {MVT::v2i64, 1};
2135 if (NumElts == 4)
2136 return {MVT::v4i32, 1};
2137 if (NumElts == 8 && CC != CallingConv::X86_RegCall &&
2138 CC != CallingConv::Intel_OCL_BI)
2139 return {MVT::v8i16, 1};
2140 if (NumElts == 16 && CC != CallingConv::X86_RegCall &&
2141 CC != CallingConv::Intel_OCL_BI)
2142 return {MVT::v16i8, 1};
2143 // v32i1 passes in ymm unless we have BWI and the calling convention is
2144 // regcall.
2145 if (NumElts == 32 && (!Subtarget.hasBWI() || CC != CallingConv::X86_RegCall))
2146 return {MVT::v32i8, 1};
2147 // Split v64i1 vectors if we don't have v64i8 available.
2148 if (NumElts == 64 && Subtarget.hasBWI() && CC != CallingConv::X86_RegCall) {
2149 if (Subtarget.useAVX512Regs())
2150 return {MVT::v64i8, 1};
2151 return {MVT::v32i8, 2};
2152 }
2153
2154 // Break wide or odd vXi1 vectors into scalars to match avx2 behavior.
2155 if (!isPowerOf2_32(NumElts) || (NumElts == 64 && !Subtarget.hasBWI()) ||
2156 NumElts > 64)
2157 return {MVT::i8, NumElts};
2158
2159 return {MVT::INVALID_SIMPLE_VALUE_TYPE, 0};
2160}
2161
2162MVT X86TargetLowering::getRegisterTypeForCallingConv(LLVMContext &Context,
2163 CallingConv::ID CC,
2164 EVT VT) const {
2165 if (VT.isVector() && VT.getVectorElementType() == MVT::i1 &&
2166 Subtarget.hasAVX512()) {
2167 unsigned NumElts = VT.getVectorNumElements();
2168
2169 MVT RegisterVT;
2170 unsigned NumRegisters;
2171 std::tie(RegisterVT, NumRegisters) =
2172 handleMaskRegisterForCallingConv(NumElts, CC, Subtarget);
2173 if (RegisterVT != MVT::INVALID_SIMPLE_VALUE_TYPE)
2174 return RegisterVT;
2175 }
2176
2177 // FIXME: Should we just make these types legal and custom split operations?
2178 if ((VT == MVT::v32i16 || VT == MVT::v64i8) && !EnableOldKNLABI &&
2179 Subtarget.useAVX512Regs() && !Subtarget.hasBWI())
2180 return MVT::v16i32;
2181
2182 return TargetLowering::getRegisterTypeForCallingConv(Context, CC, VT);
2183}
2184
2185unsigned X86TargetLowering::getNumRegistersForCallingConv(LLVMContext &Context,
2186 CallingConv::ID CC,
2187 EVT VT) const {
2188 if (VT.isVector() && VT.getVectorElementType() == MVT::i1 &&
2189 Subtarget.hasAVX512()) {
2190 unsigned NumElts = VT.getVectorNumElements();
2191
2192 MVT RegisterVT;
2193 unsigned NumRegisters;
2194 std::tie(RegisterVT, NumRegisters) =
2195 handleMaskRegisterForCallingConv(NumElts, CC, Subtarget);
2196 if (RegisterVT != MVT::INVALID_SIMPLE_VALUE_TYPE)
2197 return NumRegisters;
2198 }
2199
2200 // FIXME: Should we just make these types legal and custom split operations?
2201 if ((VT == MVT::v32i16 || VT == MVT::v64i8) && !EnableOldKNLABI &&
2202 Subtarget.useAVX512Regs() && !Subtarget.hasBWI())
2203 return 1;
2204
2205 return TargetLowering::getNumRegistersForCallingConv(Context, CC, VT);
2206}
2207
2208unsigned X86TargetLowering::getVectorTypeBreakdownForCallingConv(
2209 LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT,
2210 unsigned &NumIntermediates, MVT &RegisterVT) const {
2211 // Break wide or odd vXi1 vectors into scalars to match avx2 behavior.
2212 if (VT.isVector() && VT.getVectorElementType() == MVT::i1 &&
2213 Subtarget.hasAVX512() &&
2214 (!isPowerOf2_32(VT.getVectorNumElements()) ||
2215 (VT.getVectorNumElements() == 64 && !Subtarget.hasBWI()) ||
2216 VT.getVectorNumElements() > 64)) {
2217 RegisterVT = MVT::i8;
2218 IntermediateVT = MVT::i1;
2219 NumIntermediates = VT.getVectorNumElements();
2220 return NumIntermediates;
2221 }
2222
2223 // Split v64i1 vectors if we don't have v64i8 available.
2224 if (VT == MVT::v64i1 && Subtarget.hasBWI() && !Subtarget.useAVX512Regs() &&
2225 CC != CallingConv::X86_RegCall) {
2226 RegisterVT = MVT::v32i8;
2227 IntermediateVT = MVT::v32i1;
2228 NumIntermediates = 2;
2229 return 2;
2230 }
2231
2232 return TargetLowering::getVectorTypeBreakdownForCallingConv(Context, CC, VT, IntermediateVT,
2233 NumIntermediates, RegisterVT);
2234}
2235
2236EVT X86TargetLowering::getSetCCResultType(const DataLayout &DL,
2237 LLVMContext& Context,
2238 EVT VT) const {
2239 if (!VT.isVector())
2240 return MVT::i8;
2241
2242 if (Subtarget.hasAVX512()) {
2243 const unsigned NumElts = VT.getVectorNumElements();
2244
2245 // Figure out what this type will be legalized to.
2246 EVT LegalVT = VT;
2247 while (getTypeAction(Context, LegalVT) != TypeLegal)
2248 LegalVT = getTypeToTransformTo(Context, LegalVT);
2249
2250 // If we got a 512-bit vector then we'll definitely have a vXi1 compare.
2251 if (LegalVT.getSimpleVT().is512BitVector())
2252 return EVT::getVectorVT(Context, MVT::i1, NumElts);
2253
2254 if (LegalVT.getSimpleVT().isVector() && Subtarget.hasVLX()) {
2255 // If we legalized to less than a 512-bit vector, then we will use a vXi1
2256 // compare for vXi32/vXi64 for sure. If we have BWI we will also support
2257 // vXi16/vXi8.
2258 MVT EltVT = LegalVT.getSimpleVT().getVectorElementType();
2259 if (Subtarget.hasBWI() || EltVT.getSizeInBits() >= 32)
2260 return EVT::getVectorVT(Context, MVT::i1, NumElts);
2261 }
2262 }
2263
2264 return VT.changeVectorElementTypeToInteger();
2265}
2266
2267/// Helper for getByValTypeAlignment to determine
2268/// the desired ByVal argument alignment.
2269static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
2270 if (MaxAlign == 16)
2271 return;
2272 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
2273 if (VTy->getBitWidth() == 128)
2274 MaxAlign = 16;
2275 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
2276 unsigned EltAlign = 0;
2277 getMaxByValAlign(ATy->getElementType(), EltAlign);
2278 if (EltAlign > MaxAlign)
2279 MaxAlign = EltAlign;
2280 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
2281 for (auto *EltTy : STy->elements()) {
2282 unsigned EltAlign = 0;
2283 getMaxByValAlign(EltTy, EltAlign);
2284 if (EltAlign > MaxAlign)
2285 MaxAlign = EltAlign;
2286 if (MaxAlign == 16)
2287 break;
2288 }
2289 }
2290}
2291
2292/// Return the desired alignment for ByVal aggregate
2293/// function arguments in the caller parameter area. For X86, aggregates
2294/// that contain SSE vectors are placed at 16-byte boundaries while the rest
2295/// are at 4-byte boundaries.
2296unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty,
2297 const DataLayout &DL) const {
2298 if (Subtarget.is64Bit()) {
2299 // Max of 8 and alignment of type.
2300 unsigned TyAlign = DL.getABITypeAlignment(Ty);
2301 if (TyAlign > 8)
2302 return TyAlign;
2303 return 8;
2304 }
2305
2306 unsigned Align = 4;
2307 if (Subtarget.hasSSE1())
2308 getMaxByValAlign(Ty, Align);
2309 return Align;
2310}
2311
2312/// It returns EVT::Other if the type should be determined using generic
2313/// target-independent logic.
2314/// For vector ops we check that the overall size isn't larger than our
2315/// preferred vector width.
2316EVT X86TargetLowering::getOptimalMemOpType(
2317 const MemOp &Op, const AttributeList &FuncAttributes) const {
2318 if (!FuncAttributes.hasFnAttribute(Attribute::NoImplicitFloat)) {
2319 if (Op.size() >= 16 &&
2320 (!Subtarget.isUnalignedMem16Slow() || Op.isAligned(Align(16)))) {
2321 // FIXME: Check if unaligned 64-byte accesses are slow.
2322 if (Op.size() >= 64 && Subtarget.hasAVX512() &&
2323 (Subtarget.getPreferVectorWidth() >= 512)) {
2324 return Subtarget.hasBWI() ? MVT::v64i8 : MVT::v16i32;
2325 }
2326 // FIXME: Check if unaligned 32-byte accesses are slow.
2327 if (Op.size() >= 32 && Subtarget.hasAVX() &&
2328 (Subtarget.getPreferVectorWidth() >= 256)) {
2329 // Although this isn't a well-supported type for AVX1, we'll let
2330 // legalization and shuffle lowering produce the optimal codegen. If we
2331 // choose an optimal type with a vector element larger than a byte,
2332 // getMemsetStores() may create an intermediate splat (using an integer
2333 // multiply) before we splat as a vector.
2334 return MVT::v32i8;
2335 }
2336 if (Subtarget.hasSSE2() && (Subtarget.getPreferVectorWidth() >= 128))
2337 return MVT::v16i8;
2338 // TODO: Can SSE1 handle a byte vector?
2339 // If we have SSE1 registers we should be able to use them.
2340 if (Subtarget.hasSSE1() && (Subtarget.is64Bit() || Subtarget.hasX87()) &&
2341 (Subtarget.getPreferVectorWidth() >= 128))
2342 return MVT::v4f32;
2343 } else if (((Op.isMemcpy() && !Op.isMemcpyStrSrc()) || Op.isZeroMemset()) &&
2344 Op.size() >= 8 && !Subtarget.is64Bit() && Subtarget.hasSSE2()) {
2345 // Do not use f64 to lower memcpy if source is string constant. It's
2346 // better to use i32 to avoid the loads.
2347 // Also, do not use f64 to lower memset unless this is a memset of zeros.
2348 // The gymnastics of splatting a byte value into an XMM register and then
2349 // only using 8-byte stores (because this is a CPU with slow unaligned
2350 // 16-byte accesses) makes that a loser.
2351 return MVT::f64;
2352 }
2353 }
2354 // This is a compromise. If we reach here, unaligned accesses may be slow on
2355 // this target. However, creating smaller, aligned accesses could be even
2356 // slower and would certainly be a lot more code.
2357 if (Subtarget.is64Bit() && Op.size() >= 8)
2358 return MVT::i64;
2359 return MVT::i32;
2360}
2361
2362bool X86TargetLowering::isSafeMemOpType(MVT VT) const {
2363 if (VT == MVT::f32)
2364 return X86ScalarSSEf32;
2365 else if (VT == MVT::f64)
2366 return X86ScalarSSEf64;
2367 return true;
2368}
2369
2370bool X86TargetLowering::allowsMisalignedMemoryAccesses(
2371 EVT VT, unsigned, unsigned Align, MachineMemOperand::Flags Flags,
2372 bool *Fast) const {
2373 if (Fast) {
2374 switch (VT.getSizeInBits()) {
2375 default:
2376 // 8-byte and under are always assumed to be fast.
2377 *Fast = true;
2378 break;
2379 case 128:
2380 *Fast = !Subtarget.isUnalignedMem16Slow();
2381 break;
2382 case 256:
2383 *Fast = !Subtarget.isUnalignedMem32Slow();
2384 break;
2385 // TODO: What about AVX-512 (512-bit) accesses?
2386 }
2387 }
2388 // NonTemporal vector memory ops must be aligned.
2389 if (!!(Flags & MachineMemOperand::MONonTemporal) && VT.isVector()) {
2390 // NT loads can only be vector aligned, so if its less aligned than the
2391 // minimum vector size (which we can split the vector down to), we might as
2392 // well use a regular unaligned vector load.
2393 // We don't have any NT loads pre-SSE41.
2394 if (!!(Flags & MachineMemOperand::MOLoad))
2395 return (Align < 16 || !Subtarget.hasSSE41());
2396 return false;
2397 }
2398 // Misaligned accesses of any size are always allowed.
2399 return true;
2400}
2401
2402/// Return the entry encoding for a jump table in the
2403/// current function. The returned value is a member of the
2404/// MachineJumpTableInfo::JTEntryKind enum.
2405unsigned X86TargetLowering::getJumpTableEncoding() const {
2406 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
2407 // symbol.
2408 if (isPositionIndependent() && Subtarget.isPICStyleGOT())
2409 return MachineJumpTableInfo::EK_Custom32;
2410
2411 // Otherwise, use the normal jump table encoding heuristics.
2412 return TargetLowering::getJumpTableEncoding();
2413}
2414
2415bool X86TargetLowering::useSoftFloat() const {
2416 return Subtarget.useSoftFloat();
2417}
2418
2419void X86TargetLowering::markLibCallAttributes(MachineFunction *MF, unsigned CC,
2420 ArgListTy &Args) const {
2421
2422 // Only relabel X86-32 for C / Stdcall CCs.
2423 if (Subtarget.is64Bit())
2424 return;
2425 if (CC != CallingConv::C && CC != CallingConv::X86_StdCall)
2426 return;
2427 unsigned ParamRegs = 0;
2428 if (auto *M = MF->getFunction().getParent())
2429 ParamRegs = M->getNumberRegisterParameters();
2430
2431 // Mark the first N int arguments as having reg
2432 for (unsigned Idx = 0; Idx < Args.size(); Idx++) {
2433 Type *T = Args[Idx].Ty;
2434 if (T->isIntOrPtrTy())
2435 if (MF->getDataLayout().getTypeAllocSize(T) <= 8) {
2436 unsigned numRegs = 1;
2437 if (MF->getDataLayout().getTypeAllocSize(T) > 4)
2438 numRegs = 2;
2439 if (ParamRegs < numRegs)
2440 return;
2441 ParamRegs -= numRegs;
2442 Args[Idx].IsInReg = true;
2443 }
2444 }
2445}
2446
2447const MCExpr *
2448X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
2449 const MachineBasicBlock *MBB,
2450 unsigned uid,MCContext &Ctx) const{
2451 assert(isPositionIndependent() && Subtarget.isPICStyleGOT())((isPositionIndependent() && Subtarget.isPICStyleGOT(
)) ? static_cast<void> (0) : __assert_fail ("isPositionIndependent() && Subtarget.isPICStyleGOT()"
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 2451, __PRETTY_FUNCTION__))
;
2452 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
2453 // entries.
2454 return MCSymbolRefExpr::create(MBB->getSymbol(),
2455 MCSymbolRefExpr::VK_GOTOFF, Ctx);
2456}
2457
2458/// Returns relocation base for the given PIC jumptable.
2459SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
2460 SelectionDAG &DAG) const {
2461 if (!Subtarget.is64Bit())
2462 // This doesn't have SDLoc associated with it, but is not really the
2463 // same as a Register.
2464 return DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(),
2465 getPointerTy(DAG.getDataLayout()));
2466 return Table;
2467}
2468
2469/// This returns the relocation base for the given PIC jumptable,
2470/// the same as getPICJumpTableRelocBase, but as an MCExpr.
2471const MCExpr *X86TargetLowering::
2472getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
2473 MCContext &Ctx) const {
2474 // X86-64 uses RIP relative addressing based on the jump table label.
2475 if (Subtarget.isPICStyleRIPRel())
2476 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
2477
2478 // Otherwise, the reference is relative to the PIC base.
2479 return MCSymbolRefExpr::create(MF->getPICBaseSymbol(), Ctx);
2480}
2481
2482std::pair<const TargetRegisterClass *, uint8_t>
2483X86TargetLowering::findRepresentativeClass(const TargetRegisterInfo *TRI,
2484 MVT VT) const {
2485 const TargetRegisterClass *RRC = nullptr;
2486 uint8_t Cost = 1;
2487 switch (VT.SimpleTy) {
2488 default:
2489 return TargetLowering::findRepresentativeClass(TRI, VT);
2490 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
2491 RRC = Subtarget.is64Bit() ? &X86::GR64RegClass : &X86::GR32RegClass;
2492 break;
2493 case MVT::x86mmx:
2494 RRC = &X86::VR64RegClass;
2495 break;
2496 case MVT::f32: case MVT::f64:
2497 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
2498 case MVT::v4f32: case MVT::v2f64:
2499 case MVT::v32i8: case MVT::v16i16: case MVT::v8i32: case MVT::v4i64:
2500 case MVT::v8f32: case MVT::v4f64:
2501 case MVT::v64i8: case MVT::v32i16: case MVT::v16i32: case MVT::v8i64:
2502 case MVT::v16f32: case MVT::v8f64:
2503 RRC = &X86::VR128XRegClass;
2504 break;
2505 }
2506 return std::make_pair(RRC, Cost);
2507}
2508
2509unsigned X86TargetLowering::getAddressSpace() const {
2510 if (Subtarget.is64Bit())
2511 return (getTargetMachine().getCodeModel() == CodeModel::Kernel) ? 256 : 257;
2512 return 256;
2513}
2514
2515static bool hasStackGuardSlotTLS(const Triple &TargetTriple) {
2516 return TargetTriple.isOSGlibc() || TargetTriple.isOSFuchsia() ||
2517 (TargetTriple.isAndroid() && !TargetTriple.isAndroidVersionLT(17));
2518}
2519
2520static Constant* SegmentOffset(IRBuilder<> &IRB,
2521 unsigned Offset, unsigned AddressSpace) {
2522 return ConstantExpr::getIntToPtr(
2523 ConstantInt::get(Type::getInt32Ty(IRB.getContext()), Offset),
2524 Type::getInt8PtrTy(IRB.getContext())->getPointerTo(AddressSpace));
2525}
2526
2527Value *X86TargetLowering::getIRStackGuard(IRBuilder<> &IRB) const {
2528 // glibc, bionic, and Fuchsia have a special slot for the stack guard in
2529 // tcbhead_t; use it instead of the usual global variable (see
2530 // sysdeps/{i386,x86_64}/nptl/tls.h)
2531 if (hasStackGuardSlotTLS(Subtarget.getTargetTriple())) {
2532 if (Subtarget.isTargetFuchsia()) {
2533 // <zircon/tls.h> defines ZX_TLS_STACK_GUARD_OFFSET with this value.
2534 return SegmentOffset(IRB, 0x10, getAddressSpace());
2535 } else {
2536 // %fs:0x28, unless we're using a Kernel code model, in which case
2537 // it's %gs:0x28. gs:0x14 on i386.
2538 unsigned Offset = (Subtarget.is64Bit()) ? 0x28 : 0x14;
2539 return SegmentOffset(IRB, Offset, getAddressSpace());
2540 }
2541 }
2542
2543 return TargetLowering::getIRStackGuard(IRB);
2544}
2545
2546void X86TargetLowering::insertSSPDeclarations(Module &M) const {
2547 // MSVC CRT provides functionalities for stack protection.
2548 if (Subtarget.getTargetTriple().isWindowsMSVCEnvironment() ||
2549 Subtarget.getTargetTriple().isWindowsItaniumEnvironment()) {
2550 // MSVC CRT has a global variable holding security cookie.
2551 M.getOrInsertGlobal("__security_cookie",
2552 Type::getInt8PtrTy(M.getContext()));
2553
2554 // MSVC CRT has a function to validate security cookie.
2555 FunctionCallee SecurityCheckCookie = M.getOrInsertFunction(
2556 "__security_check_cookie", Type::getVoidTy(M.getContext()),
2557 Type::getInt8PtrTy(M.getContext()));
2558 if (Function *F = dyn_cast<Function>(SecurityCheckCookie.getCallee())) {
2559 F->setCallingConv(CallingConv::X86_FastCall);
2560 F->addAttribute(1, Attribute::AttrKind::InReg);
2561 }
2562 return;
2563 }
2564 // glibc, bionic, and Fuchsia have a special slot for the stack guard.
2565 if (hasStackGuardSlotTLS(Subtarget.getTargetTriple()))
2566 return;
2567 TargetLowering::insertSSPDeclarations(M);
2568}
2569
2570Value *X86TargetLowering::getSDagStackGuard(const Module &M) const {
2571 // MSVC CRT has a global variable holding security cookie.
2572 if (Subtarget.getTargetTriple().isWindowsMSVCEnvironment() ||
2573 Subtarget.getTargetTriple().isWindowsItaniumEnvironment()) {
2574 return M.getGlobalVariable("__security_cookie");
2575 }
2576 return TargetLowering::getSDagStackGuard(M);
2577}
2578
2579Function *X86TargetLowering::getSSPStackGuardCheck(const Module &M) const {
2580 // MSVC CRT has a function to validate security cookie.
2581 if (Subtarget.getTargetTriple().isWindowsMSVCEnvironment() ||
2582 Subtarget.getTargetTriple().isWindowsItaniumEnvironment()) {
2583 return M.getFunction("__security_check_cookie");
2584 }
2585 return TargetLowering::getSSPStackGuardCheck(M);
2586}
2587
2588Value *X86TargetLowering::getSafeStackPointerLocation(IRBuilder<> &IRB) const {
2589 if (Subtarget.getTargetTriple().isOSContiki())
2590 return getDefaultSafeStackPointerLocation(IRB, false);
2591
2592 // Android provides a fixed TLS slot for the SafeStack pointer. See the
2593 // definition of TLS_SLOT_SAFESTACK in
2594 // https://android.googlesource.com/platform/bionic/+/master/libc/private/bionic_tls.h
2595 if (Subtarget.isTargetAndroid()) {
2596 // %fs:0x48, unless we're using a Kernel code model, in which case it's %gs:
2597 // %gs:0x24 on i386
2598 unsigned Offset = (Subtarget.is64Bit()) ? 0x48 : 0x24;
2599 return SegmentOffset(IRB, Offset, getAddressSpace());
2600 }
2601
2602 // Fuchsia is similar.
2603 if (Subtarget.isTargetFuchsia()) {
2604 // <zircon/tls.h> defines ZX_TLS_UNSAFE_SP_OFFSET with this value.
2605 return SegmentOffset(IRB, 0x18, getAddressSpace());
2606 }
2607
2608 return TargetLowering::getSafeStackPointerLocation(IRB);
2609}
2610
2611bool X86TargetLowering::isNoopAddrSpaceCast(unsigned SrcAS,
2612 unsigned DestAS) const {
2613 assert(SrcAS != DestAS && "Expected different address spaces!")((SrcAS != DestAS && "Expected different address spaces!"
) ? static_cast<void> (0) : __assert_fail ("SrcAS != DestAS && \"Expected different address spaces!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 2613, __PRETTY_FUNCTION__))
;
2614
2615 const TargetMachine &TM = getTargetMachine();
2616 if (TM.getPointerSize(SrcAS) != TM.getPointerSize(DestAS))
2617 return false;
2618
2619 return SrcAS < 256 && DestAS < 256;
2620}
2621
2622//===----------------------------------------------------------------------===//
2623// Return Value Calling Convention Implementation
2624//===----------------------------------------------------------------------===//
2625
2626bool X86TargetLowering::CanLowerReturn(
2627 CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg,
2628 const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const {
2629 SmallVector<CCValAssign, 16> RVLocs;
2630 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
2631 return CCInfo.CheckReturn(Outs, RetCC_X86);
2632}
2633
2634const MCPhysReg *X86TargetLowering::getScratchRegisters(CallingConv::ID) const {
2635 static const MCPhysReg ScratchRegs[] = { X86::R11, 0 };
2636 return ScratchRegs;
2637}
2638
2639/// Lowers masks values (v*i1) to the local register values
2640/// \returns DAG node after lowering to register type
2641static SDValue lowerMasksToReg(const SDValue &ValArg, const EVT &ValLoc,
2642 const SDLoc &Dl, SelectionDAG &DAG) {
2643 EVT ValVT = ValArg.getValueType();
2644
2645 if (ValVT == MVT::v1i1)
2646 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, Dl, ValLoc, ValArg,
2647 DAG.getIntPtrConstant(0, Dl));
2648
2649 if ((ValVT == MVT::v8i1 && (ValLoc == MVT::i8 || ValLoc == MVT::i32)) ||
2650 (ValVT == MVT::v16i1 && (ValLoc == MVT::i16 || ValLoc == MVT::i32))) {
2651 // Two stage lowering might be required
2652 // bitcast: v8i1 -> i8 / v16i1 -> i16
2653 // anyextend: i8 -> i32 / i16 -> i32
2654 EVT TempValLoc = ValVT == MVT::v8i1 ? MVT::i8 : MVT::i16;
2655 SDValue ValToCopy = DAG.getBitcast(TempValLoc, ValArg);
2656 if (ValLoc == MVT::i32)
2657 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, Dl, ValLoc, ValToCopy);
2658 return ValToCopy;
2659 }
2660
2661 if ((ValVT == MVT::v32i1 && ValLoc == MVT::i32) ||
2662 (ValVT == MVT::v64i1 && ValLoc == MVT::i64)) {
2663 // One stage lowering is required
2664 // bitcast: v32i1 -> i32 / v64i1 -> i64
2665 return DAG.getBitcast(ValLoc, ValArg);
2666 }
2667
2668 return DAG.getNode(ISD::ANY_EXTEND, Dl, ValLoc, ValArg);
2669}
2670
2671/// Breaks v64i1 value into two registers and adds the new node to the DAG
2672static void Passv64i1ArgInRegs(
2673 const SDLoc &Dl, SelectionDAG &DAG, SDValue &Arg,
2674 SmallVectorImpl<std::pair<unsigned, SDValue>> &RegsToPass, CCValAssign &VA,
2675 CCValAssign &NextVA, const X86Subtarget &Subtarget) {
2676 assert(Subtarget.hasBWI() && "Expected AVX512BW target!")((Subtarget.hasBWI() && "Expected AVX512BW target!") ?
static_cast<void> (0) : __assert_fail ("Subtarget.hasBWI() && \"Expected AVX512BW target!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 2676, __PRETTY_FUNCTION__))
;
2677 assert(Subtarget.is32Bit() && "Expecting 32 bit target")((Subtarget.is32Bit() && "Expecting 32 bit target") ?
static_cast<void> (0) : __assert_fail ("Subtarget.is32Bit() && \"Expecting 32 bit target\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 2677, __PRETTY_FUNCTION__))
;
2678 assert(Arg.getValueType() == MVT::i64 && "Expecting 64 bit value")((Arg.getValueType() == MVT::i64 && "Expecting 64 bit value"
) ? static_cast<void> (0) : __assert_fail ("Arg.getValueType() == MVT::i64 && \"Expecting 64 bit value\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 2678, __PRETTY_FUNCTION__))
;
2679 assert(VA.isRegLoc() && NextVA.isRegLoc() &&((VA.isRegLoc() && NextVA.isRegLoc() && "The value should reside in two registers"
) ? static_cast<void> (0) : __assert_fail ("VA.isRegLoc() && NextVA.isRegLoc() && \"The value should reside in two registers\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 2680, __PRETTY_FUNCTION__))
2680 "The value should reside in two registers")((VA.isRegLoc() && NextVA.isRegLoc() && "The value should reside in two registers"
) ? static_cast<void> (0) : __assert_fail ("VA.isRegLoc() && NextVA.isRegLoc() && \"The value should reside in two registers\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 2680, __PRETTY_FUNCTION__))
;
2681
2682 // Before splitting the value we cast it to i64
2683 Arg = DAG.getBitcast(MVT::i64, Arg);
2684
2685 // Splitting the value into two i32 types
2686 SDValue Lo, Hi;
2687 Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, Dl, MVT::i32, Arg,
2688 DAG.getConstant(0, Dl, MVT::i32));
2689 Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, Dl, MVT::i32, Arg,
2690 DAG.getConstant(1, Dl, MVT::i32));
2691
2692 // Attach the two i32 types into corresponding registers
2693 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Lo));
2694 RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), Hi));
2695}
2696
2697SDValue
2698X86TargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
2699 bool isVarArg,
2700 const SmallVectorImpl<ISD::OutputArg> &Outs,
2701 const SmallVectorImpl<SDValue> &OutVals,
2702 const SDLoc &dl, SelectionDAG &DAG) const {
2703 MachineFunction &MF = DAG.getMachineFunction();
2704 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2705
2706 // In some cases we need to disable registers from the default CSR list.
2707 // For example, when they are used for argument passing.
2708 bool ShouldDisableCalleeSavedRegister =
2709 CallConv == CallingConv::X86_RegCall ||
2710 MF.getFunction().hasFnAttribute("no_caller_saved_registers");
2711
2712 if (CallConv == CallingConv::X86_INTR && !Outs.empty())
2713 report_fatal_error("X86 interrupts may not return any value");
2714
2715 SmallVector<CCValAssign, 16> RVLocs;
2716 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, *DAG.getContext());
2717 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
2718
2719 SmallVector<std::pair<unsigned, SDValue>, 4> RetVals;
2720 for (unsigned I = 0, OutsIndex = 0, E = RVLocs.size(); I != E;
2721 ++I, ++OutsIndex) {
2722 CCValAssign &VA = RVLocs[I];
2723 assert(VA.isRegLoc() && "Can only return in registers!")((VA.isRegLoc() && "Can only return in registers!") ?
static_cast<void> (0) : __assert_fail ("VA.isRegLoc() && \"Can only return in registers!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 2723, __PRETTY_FUNCTION__))
;
2724
2725 // Add the register to the CalleeSaveDisableRegs list.
2726 if (ShouldDisableCalleeSavedRegister)
2727 MF.getRegInfo().disableCalleeSavedRegister(VA.getLocReg());
2728
2729 SDValue ValToCopy = OutVals[OutsIndex];
2730 EVT ValVT = ValToCopy.getValueType();
2731
2732 // Promote values to the appropriate types.
2733 if (VA.getLocInfo() == CCValAssign::SExt)
2734 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
2735 else if (VA.getLocInfo() == CCValAssign::ZExt)
2736 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy);
2737 else if (VA.getLocInfo() == CCValAssign::AExt) {
2738 if (ValVT.isVector() && ValVT.getVectorElementType() == MVT::i1)
2739 ValToCopy = lowerMasksToReg(ValToCopy, VA.getLocVT(), dl, DAG);
2740 else
2741 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy);
2742 }
2743 else if (VA.getLocInfo() == CCValAssign::BCvt)
2744 ValToCopy = DAG.getBitcast(VA.getLocVT(), ValToCopy);
2745
2746 assert(VA.getLocInfo() != CCValAssign::FPExt &&((VA.getLocInfo() != CCValAssign::FPExt && "Unexpected FP-extend for return value."
) ? static_cast<void> (0) : __assert_fail ("VA.getLocInfo() != CCValAssign::FPExt && \"Unexpected FP-extend for return value.\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 2747, __PRETTY_FUNCTION__))
2747 "Unexpected FP-extend for return value.")((VA.getLocInfo() != CCValAssign::FPExt && "Unexpected FP-extend for return value."
) ? static_cast<void> (0) : __assert_fail ("VA.getLocInfo() != CCValAssign::FPExt && \"Unexpected FP-extend for return value.\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 2747, __PRETTY_FUNCTION__))
;
2748
2749 // Report an error if we have attempted to return a value via an XMM
2750 // register and SSE was disabled.
2751 if (!Subtarget.hasSSE1() && X86::FR32XRegClass.contains(VA.getLocReg())) {
2752 errorUnsupported(DAG, dl, "SSE register return with SSE disabled");
2753 VA.convertToReg(X86::FP0); // Set reg to FP0, avoid hitting asserts.
2754 } else if (!Subtarget.hasSSE2() &&
2755 X86::FR64XRegClass.contains(VA.getLocReg()) &&
2756 ValVT == MVT::f64) {
2757 // When returning a double via an XMM register, report an error if SSE2 is
2758 // not enabled.
2759 errorUnsupported(DAG, dl, "SSE2 register return with SSE2 disabled");
2760 VA.convertToReg(X86::FP0); // Set reg to FP0, avoid hitting asserts.
2761 }
2762
2763 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
2764 // the RET instruction and handled by the FP Stackifier.
2765 if (VA.getLocReg() == X86::FP0 ||
2766 VA.getLocReg() == X86::FP1) {
2767 // If this is a copy from an xmm register to ST(0), use an FPExtend to
2768 // change the value to the FP stack register class.
2769 if (isScalarFPTypeInSSEReg(VA.getValVT()))
2770 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
2771 RetVals.push_back(std::make_pair(VA.getLocReg(), ValToCopy));
2772 // Don't emit a copytoreg.
2773 continue;
2774 }
2775
2776 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
2777 // which is returned in RAX / RDX.
2778 if (Subtarget.is64Bit()) {
2779 if (ValVT == MVT::x86mmx) {
2780 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
2781 ValToCopy = DAG.getBitcast(MVT::i64, ValToCopy);
2782 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
2783 ValToCopy);
2784 // If we don't have SSE2 available, convert to v4f32 so the generated
2785 // register is legal.
2786 if (!Subtarget.hasSSE2())
2787 ValToCopy = DAG.getBitcast(MVT::v4f32, ValToCopy);
2788 }
2789 }
2790 }
2791
2792 if (VA.needsCustom()) {
2793 assert(VA.getValVT() == MVT::v64i1 &&((VA.getValVT() == MVT::v64i1 && "Currently the only custom case is when we split v64i1 to 2 regs"
) ? static_cast<void> (0) : __assert_fail ("VA.getValVT() == MVT::v64i1 && \"Currently the only custom case is when we split v64i1 to 2 regs\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 2794, __PRETTY_FUNCTION__))
2794 "Currently the only custom case is when we split v64i1 to 2 regs")((VA.getValVT() == MVT::v64i1 && "Currently the only custom case is when we split v64i1 to 2 regs"
) ? static_cast<void> (0) : __assert_fail ("VA.getValVT() == MVT::v64i1 && \"Currently the only custom case is when we split v64i1 to 2 regs\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 2794, __PRETTY_FUNCTION__))
;
2795
2796 Passv64i1ArgInRegs(dl, DAG, ValToCopy, RetVals, VA, RVLocs[++I],
2797 Subtarget);
2798
2799 // Add the second register to the CalleeSaveDisableRegs list.
2800 if (ShouldDisableCalleeSavedRegister)
2801 MF.getRegInfo().disableCalleeSavedRegister(RVLocs[I].getLocReg());
2802 } else {
2803 RetVals.push_back(std::make_pair(VA.getLocReg(), ValToCopy));
2804 }
2805 }
2806
2807 SDValue Flag;
2808 SmallVector<SDValue, 6> RetOps;
2809 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
2810 // Operand #1 = Bytes To Pop
2811 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(), dl,
2812 MVT::i32));
2813
2814 // Copy the result values into the output registers.
2815 for (auto &RetVal : RetVals) {
2816 if (RetVal.first == X86::FP0 || RetVal.first == X86::FP1) {
2817 RetOps.push_back(RetVal.second);
2818 continue; // Don't emit a copytoreg.
2819 }
2820
2821 Chain = DAG.getCopyToReg(Chain, dl, RetVal.first, RetVal.second, Flag);
2822 Flag = Chain.getValue(1);
2823 RetOps.push_back(
2824 DAG.getRegister(RetVal.first, RetVal.second.getValueType()));
2825 }
2826
2827 // Swift calling convention does not require we copy the sret argument
2828 // into %rax/%eax for the return, and SRetReturnReg is not set for Swift.
2829
2830 // All x86 ABIs require that for returning structs by value we copy
2831 // the sret argument into %rax/%eax (depending on ABI) for the return.
2832 // We saved the argument into a virtual register in the entry block,
2833 // so now we copy the value out and into %rax/%eax.
2834 //
2835 // Checking Function.hasStructRetAttr() here is insufficient because the IR
2836 // may not have an explicit sret argument. If FuncInfo.CanLowerReturn is
2837 // false, then an sret argument may be implicitly inserted in the SelDAG. In
2838 // either case FuncInfo->setSRetReturnReg() will have been called.
2839 if (unsigned SRetReg = FuncInfo->getSRetReturnReg()) {
2840 // When we have both sret and another return value, we should use the
2841 // original Chain stored in RetOps[0], instead of the current Chain updated
2842 // in the above loop. If we only have sret, RetOps[0] equals to Chain.
2843
2844 // For the case of sret and another return value, we have
2845 // Chain_0 at the function entry
2846 // Chain_1 = getCopyToReg(Chain_0) in the above loop
2847 // If we use Chain_1 in getCopyFromReg, we will have
2848 // Val = getCopyFromReg(Chain_1)
2849 // Chain_2 = getCopyToReg(Chain_1, Val) from below
2850
2851 // getCopyToReg(Chain_0) will be glued together with
2852 // getCopyToReg(Chain_1, Val) into Unit A, getCopyFromReg(Chain_1) will be
2853 // in Unit B, and we will have cyclic dependency between Unit A and Unit B:
2854 // Data dependency from Unit B to Unit A due to usage of Val in
2855 // getCopyToReg(Chain_1, Val)
2856 // Chain dependency from Unit A to Unit B
2857
2858 // So here, we use RetOps[0] (i.e Chain_0) for getCopyFromReg.
2859 SDValue Val = DAG.getCopyFromReg(RetOps[0], dl, SRetReg,
2860 getPointerTy(MF.getDataLayout()));
2861
2862 unsigned RetValReg
2863 = (Subtarget.is64Bit() && !Subtarget.isTarget64BitILP32()) ?
2864 X86::RAX : X86::EAX;
2865 Chain = DAG.getCopyToReg(Chain, dl, RetValReg, Val, Flag);
2866 Flag = Chain.getValue(1);
2867
2868 // RAX/EAX now acts like a return value.
2869 RetOps.push_back(
2870 DAG.getRegister(RetValReg, getPointerTy(DAG.getDataLayout())));
2871
2872 // Add the returned register to the CalleeSaveDisableRegs list.
2873 if (ShouldDisableCalleeSavedRegister)
2874 MF.getRegInfo().disableCalleeSavedRegister(RetValReg);
2875 }
2876
2877 const X86RegisterInfo *TRI = Subtarget.getRegisterInfo();
2878 const MCPhysReg *I =
2879 TRI->getCalleeSavedRegsViaCopy(&DAG.getMachineFunction());
2880 if (I) {
2881 for (; *I; ++I) {
2882 if (X86::GR64RegClass.contains(*I))
2883 RetOps.push_back(DAG.getRegister(*I, MVT::i64));
2884 else
2885 llvm_unreachable("Unexpected register class in CSRsViaCopy!")::llvm::llvm_unreachable_internal("Unexpected register class in CSRsViaCopy!"
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 2885)
;
2886 }
2887 }
2888
2889 RetOps[0] = Chain; // Update chain.
2890
2891 // Add the flag if we have it.
2892 if (Flag.getNode())
2893 RetOps.push_back(Flag);
2894
2895 X86ISD::NodeType opcode = X86ISD::RET_FLAG;
2896 if (CallConv == CallingConv::X86_INTR)
2897 opcode = X86ISD::IRET;
2898 return DAG.getNode(opcode, dl, MVT::Other, RetOps);
2899}
2900
2901bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
2902 if (N->getNumValues() != 1 || !N->hasNUsesOfValue(1, 0))
2903 return false;
2904
2905 SDValue TCChain = Chain;
2906 SDNode *Copy = *N->use_begin();
2907 if (Copy->getOpcode() == ISD::CopyToReg) {
2908 // If the copy has a glue operand, we conservatively assume it isn't safe to
2909 // perform a tail call.
2910 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
2911 return false;
2912 TCChain = Copy->getOperand(0);
2913 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
2914 return false;
2915
2916 bool HasRet = false;
2917 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
2918 UI != UE; ++UI) {
2919 if (UI->getOpcode() != X86ISD::RET_FLAG)
2920 return false;
2921 // If we are returning more than one value, we can definitely
2922 // not make a tail call see PR19530
2923 if (UI->getNumOperands() > 4)
2924 return false;
2925 if (UI->getNumOperands() == 4 &&
2926 UI->getOperand(UI->getNumOperands()-1).getValueType() != MVT::Glue)
2927 return false;
2928 HasRet = true;
2929 }
2930
2931 if (!HasRet)
2932 return false;
2933
2934 Chain = TCChain;
2935 return true;
2936}
2937
2938EVT X86TargetLowering::getTypeForExtReturn(LLVMContext &Context, EVT VT,
2939 ISD::NodeType ExtendKind) const {
2940 MVT ReturnMVT = MVT::i32;
2941
2942 bool Darwin = Subtarget.getTargetTriple().isOSDarwin();
2943 if (VT == MVT::i1 || (!Darwin && (VT == MVT::i8 || VT == MVT::i16))) {
2944 // The ABI does not require i1, i8 or i16 to be extended.
2945 //
2946 // On Darwin, there is code in the wild relying on Clang's old behaviour of
2947 // always extending i8/i16 return values, so keep doing that for now.
2948 // (PR26665).
2949 ReturnMVT = MVT::i8;
2950 }
2951
2952 EVT MinVT = getRegisterType(Context, ReturnMVT);
2953 return VT.bitsLT(MinVT) ? MinVT : VT;
2954}
2955
2956/// Reads two 32 bit registers and creates a 64 bit mask value.
2957/// \param VA The current 32 bit value that need to be assigned.
2958/// \param NextVA The next 32 bit value that need to be assigned.
2959/// \param Root The parent DAG node.
2960/// \param [in,out] InFlag Represents SDvalue in the parent DAG node for
2961/// glue purposes. In the case the DAG is already using
2962/// physical register instead of virtual, we should glue
2963/// our new SDValue to InFlag SDvalue.
2964/// \return a new SDvalue of size 64bit.
2965static SDValue getv64i1Argument(CCValAssign &VA, CCValAssign &NextVA,
2966 SDValue &Root, SelectionDAG &DAG,
2967 const SDLoc &Dl, const X86Subtarget &Subtarget,
2968 SDValue *InFlag = nullptr) {
2969 assert((Subtarget.hasBWI()) && "Expected AVX512BW target!")(((Subtarget.hasBWI()) && "Expected AVX512BW target!"
) ? static_cast<void> (0) : __assert_fail ("(Subtarget.hasBWI()) && \"Expected AVX512BW target!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 2969, __PRETTY_FUNCTION__))
;
2970 assert(Subtarget.is32Bit() && "Expecting 32 bit target")((Subtarget.is32Bit() && "Expecting 32 bit target") ?
static_cast<void> (0) : __assert_fail ("Subtarget.is32Bit() && \"Expecting 32 bit target\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 2970, __PRETTY_FUNCTION__))
;
2971 assert(VA.getValVT() == MVT::v64i1 &&((VA.getValVT() == MVT::v64i1 && "Expecting first location of 64 bit width type"
) ? static_cast<void> (0) : __assert_fail ("VA.getValVT() == MVT::v64i1 && \"Expecting first location of 64 bit width type\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 2972, __PRETTY_FUNCTION__))
2972 "Expecting first location of 64 bit width type")((VA.getValVT() == MVT::v64i1 && "Expecting first location of 64 bit width type"
) ? static_cast<void> (0) : __assert_fail ("VA.getValVT() == MVT::v64i1 && \"Expecting first location of 64 bit width type\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 2972, __PRETTY_FUNCTION__))
;
2973 assert(NextVA.getValVT() == VA.getValVT() &&((NextVA.getValVT() == VA.getValVT() && "The locations should have the same type"
) ? static_cast<void> (0) : __assert_fail ("NextVA.getValVT() == VA.getValVT() && \"The locations should have the same type\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 2974, __PRETTY_FUNCTION__))
2974 "The locations should have the same type")((NextVA.getValVT() == VA.getValVT() && "The locations should have the same type"
) ? static_cast<void> (0) : __assert_fail ("NextVA.getValVT() == VA.getValVT() && \"The locations should have the same type\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 2974, __PRETTY_FUNCTION__))
;
2975 assert(VA.isRegLoc() && NextVA.isRegLoc() &&((VA.isRegLoc() && NextVA.isRegLoc() && "The values should reside in two registers"
) ? static_cast<void> (0) : __assert_fail ("VA.isRegLoc() && NextVA.isRegLoc() && \"The values should reside in two registers\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 2976, __PRETTY_FUNCTION__))
2976 "The values should reside in two registers")((VA.isRegLoc() && NextVA.isRegLoc() && "The values should reside in two registers"
) ? static_cast<void> (0) : __assert_fail ("VA.isRegLoc() && NextVA.isRegLoc() && \"The values should reside in two registers\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 2976, __PRETTY_FUNCTION__))
;
2977
2978 SDValue Lo, Hi;
2979 SDValue ArgValueLo, ArgValueHi;
2980
2981 MachineFunction &MF = DAG.getMachineFunction();
2982 const TargetRegisterClass *RC = &X86::GR32RegClass;
2983
2984 // Read a 32 bit value from the registers.
2985 if (nullptr == InFlag) {
2986 // When no physical register is present,
2987 // create an intermediate virtual register.
2988 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2989 ArgValueLo = DAG.getCopyFromReg(Root, Dl, Reg, MVT::i32);
2990 Reg = MF.addLiveIn(NextVA.getLocReg(), RC);
2991 ArgValueHi = DAG.getCopyFromReg(Root, Dl, Reg, MVT::i32);
2992 } else {
2993 // When a physical register is available read the value from it and glue
2994 // the reads together.
2995 ArgValueLo =
2996 DAG.getCopyFromReg(Root, Dl, VA.getLocReg(), MVT::i32, *InFlag);
2997 *InFlag = ArgValueLo.getValue(2);
2998 ArgValueHi =
2999 DAG.getCopyFromReg(Root, Dl, NextVA.getLocReg(), MVT::i32, *InFlag);
3000 *InFlag = ArgValueHi.getValue(2);
3001 }
3002
3003 // Convert the i32 type into v32i1 type.
3004 Lo = DAG.getBitcast(MVT::v32i1, ArgValueLo);
3005
3006 // Convert the i32 type into v32i1 type.
3007 Hi = DAG.getBitcast(MVT::v32i1, ArgValueHi);
3008
3009 // Concatenate the two values together.
3010 return DAG.getNode(ISD::CONCAT_VECTORS, Dl, MVT::v64i1, Lo, Hi);
3011}
3012
3013/// The function will lower a register of various sizes (8/16/32/64)
3014/// to a mask value of the expected size (v8i1/v16i1/v32i1/v64i1)
3015/// \returns a DAG node contains the operand after lowering to mask type.
3016static SDValue lowerRegToMasks(const SDValue &ValArg, const EVT &ValVT,
3017 const EVT &ValLoc, const SDLoc &Dl,
3018 SelectionDAG &DAG) {
3019 SDValue ValReturned = ValArg;
3020
3021 if (ValVT == MVT::v1i1)
3022 return DAG.getNode(ISD::SCALAR_TO_VECTOR, Dl, MVT::v1i1, ValReturned);
3023
3024 if (ValVT == MVT::v64i1) {
3025 // In 32 bit machine, this case is handled by getv64i1Argument
3026 assert(ValLoc == MVT::i64 && "Expecting only i64 locations")((ValLoc == MVT::i64 && "Expecting only i64 locations"
) ? static_cast<void> (0) : __assert_fail ("ValLoc == MVT::i64 && \"Expecting only i64 locations\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 3026, __PRETTY_FUNCTION__))
;
3027 // In 64 bit machine, There is no need to truncate the value only bitcast
3028 } else {
3029 MVT maskLen;
3030 switch (ValVT.getSimpleVT().SimpleTy) {
3031 case MVT::v8i1:
3032 maskLen = MVT::i8;
3033 break;
3034 case MVT::v16i1:
3035 maskLen = MVT::i16;
3036 break;
3037 case MVT::v32i1:
3038 maskLen = MVT::i32;
3039 break;
3040 default:
3041 llvm_unreachable("Expecting a vector of i1 types")::llvm::llvm_unreachable_internal("Expecting a vector of i1 types"
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 3041)
;
3042 }
3043
3044 ValReturned = DAG.getNode(ISD::TRUNCATE, Dl, maskLen, ValReturned);
3045 }
3046 return DAG.getBitcast(ValVT, ValReturned);
3047}
3048
3049/// Lower the result values of a call into the
3050/// appropriate copies out of appropriate physical registers.
3051///
3052SDValue X86TargetLowering::LowerCallResult(
3053 SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg,
3054 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
3055 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals,
3056 uint32_t *RegMask) const {
3057
3058 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
3059 // Assign locations to each value returned by this call.
3060 SmallVector<CCValAssign, 16> RVLocs;
3061 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
3062 *DAG.getContext());
3063 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
3064
3065 // Copy all of the result registers out of their specified physreg.
3066 for (unsigned I = 0, InsIndex = 0, E = RVLocs.size(); I != E;
3067 ++I, ++InsIndex) {
3068 CCValAssign &VA = RVLocs[I];
3069 EVT CopyVT = VA.getLocVT();
3070
3071 // In some calling conventions we need to remove the used registers
3072 // from the register mask.
3073 if (RegMask) {
3074 for (MCSubRegIterator SubRegs(VA.getLocReg(), TRI, /*IncludeSelf=*/true);
3075 SubRegs.isValid(); ++SubRegs)
3076 RegMask[*SubRegs / 32] &= ~(1u << (*SubRegs % 32));
3077 }
3078
3079 // Report an error if there was an attempt to return FP values via XMM
3080 // registers.
3081 if (!Subtarget.hasSSE1() && X86::FR32XRegClass.contains(VA.getLocReg())) {
3082 errorUnsupported(DAG, dl, "SSE register return with SSE disabled");
3083 if (VA.getLocReg() == X86::XMM1)
3084 VA.convertToReg(X86::FP1); // Set reg to FP1, avoid hitting asserts.
3085 else
3086 VA.convertToReg(X86::FP0); // Set reg to FP0, avoid hitting asserts.
3087 } else if (!Subtarget.hasSSE2() &&
3088 X86::FR64XRegClass.contains(VA.getLocReg()) &&
3089 CopyVT == MVT::f64) {
3090 errorUnsupported(DAG, dl, "SSE2 register return with SSE2 disabled");
3091 if (VA.getLocReg() == X86::XMM1)
3092 VA.convertToReg(X86::FP1); // Set reg to FP1, avoid hitting asserts.
3093 else
3094 VA.convertToReg(X86::FP0); // Set reg to FP0, avoid hitting asserts.
3095 }
3096
3097 // If we prefer to use the value in xmm registers, copy it out as f80 and
3098 // use a truncate to move it from fp stack reg to xmm reg.
3099 bool RoundAfterCopy = false;
3100 if ((VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1) &&
3101 isScalarFPTypeInSSEReg(VA.getValVT())) {
3102 if (!Subtarget.hasX87())
3103 report_fatal_error("X87 register return with X87 disabled");
3104 CopyVT = MVT::f80;
3105 RoundAfterCopy = (CopyVT != VA.getLocVT());
3106 }
3107
3108 SDValue Val;
3109 if (VA.needsCustom()) {
3110 assert(VA.getValVT() == MVT::v64i1 &&((VA.getValVT() == MVT::v64i1 && "Currently the only custom case is when we split v64i1 to 2 regs"
) ? static_cast<void> (0) : __assert_fail ("VA.getValVT() == MVT::v64i1 && \"Currently the only custom case is when we split v64i1 to 2 regs\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 3111, __PRETTY_FUNCTION__))
3111 "Currently the only custom case is when we split v64i1 to 2 regs")((VA.getValVT() == MVT::v64i1 && "Currently the only custom case is when we split v64i1 to 2 regs"
) ? static_cast<void> (0) : __assert_fail ("VA.getValVT() == MVT::v64i1 && \"Currently the only custom case is when we split v64i1 to 2 regs\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 3111, __PRETTY_FUNCTION__))
;
3112 Val =
3113 getv64i1Argument(VA, RVLocs[++I], Chain, DAG, dl, Subtarget, &InFlag);
3114 } else {
3115 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), CopyVT, InFlag)
3116 .getValue(1);
3117 Val = Chain.getValue(0);
3118 InFlag = Chain.getValue(2);
3119 }
3120
3121 if (RoundAfterCopy)
3122 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
3123 // This truncation won't change the value.
3124 DAG.getIntPtrConstant(1, dl));
3125
3126 if (VA.isExtInLoc() && (VA.getValVT().getScalarType() == MVT::i1)) {
3127 if (VA.getValVT().isVector() &&
3128 ((VA.getLocVT() == MVT::i64) || (VA.getLocVT() == MVT::i32) ||
3129 (VA.getLocVT() == MVT::i16) || (VA.getLocVT() == MVT::i8))) {
3130 // promoting a mask type (v*i1) into a register of type i64/i32/i16/i8
3131 Val = lowerRegToMasks(Val, VA.getValVT(), VA.getLocVT(), dl, DAG);
3132 } else
3133 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
3134 }
3135
3136 if (VA.getLocInfo() == CCValAssign::BCvt)
3137 Val = DAG.getBitcast(VA.getValVT(), Val);
3138
3139 InVals.push_back(Val);
3140 }
3141
3142 return Chain;
3143}
3144
3145//===----------------------------------------------------------------------===//
3146// C & StdCall & Fast Calling Convention implementation
3147//===----------------------------------------------------------------------===//
3148// StdCall calling convention seems to be standard for many Windows' API
3149// routines and around. It differs from C calling convention just a little:
3150// callee should clean up the stack, not caller. Symbols should be also
3151// decorated in some fancy way :) It doesn't support any vector arguments.
3152// For info on fast calling convention see Fast Calling Convention (tail call)
3153// implementation LowerX86_32FastCCCallTo.
3154
3155/// CallIsStructReturn - Determines whether a call uses struct return
3156/// semantics.
3157enum StructReturnType {
3158 NotStructReturn,
3159 RegStructReturn,
3160 StackStructReturn
3161};
3162static StructReturnType
3163callIsStructReturn(ArrayRef<ISD::OutputArg> Outs, bool IsMCU) {
3164 if (Outs.empty())
3165 return NotStructReturn;
3166
3167 const ISD::ArgFlagsTy &Flags = Outs[0].Flags;
3168 if (!Flags.isSRet())
3169 return NotStructReturn;
3170 if (Flags.isInReg() || IsMCU)
3171 return RegStructReturn;
3172 return StackStructReturn;
3173}
3174
3175/// Determines whether a function uses struct return semantics.
3176static StructReturnType
3177argsAreStructReturn(ArrayRef<ISD::InputArg> Ins, bool IsMCU) {
3178 if (Ins.empty())
3179 return NotStructReturn;
3180
3181 const ISD::ArgFlagsTy &Flags = Ins[0].Flags;
3182 if (!Flags.isSRet())
3183 return NotStructReturn;
3184 if (Flags.isInReg() || IsMCU)
3185 return RegStructReturn;
3186 return StackStructReturn;
3187}
3188
3189/// Make a copy of an aggregate at address specified by "Src" to address
3190/// "Dst" with size and alignment information specified by the specific
3191/// parameter attribute. The copy will be passed as a byval function parameter.
3192static SDValue CreateCopyOfByValArgument(SDValue Src, SDValue Dst,
3193 SDValue Chain, ISD::ArgFlagsTy Flags,
3194 SelectionDAG &DAG, const SDLoc &dl) {
3195 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), dl, MVT::i32);
3196
3197 return DAG.getMemcpy(
3198 Chain, dl, Dst, Src, SizeNode, Flags.getNonZeroByValAlign(),
3199 /*isVolatile*/ false, /*AlwaysInline=*/true,
3200 /*isTailCall*/ false, MachinePointerInfo(), MachinePointerInfo());
3201}
3202
3203/// Return true if the calling convention is one that we can guarantee TCO for.
3204static bool canGuaranteeTCO(CallingConv::ID CC) {
3205 return (CC == CallingConv::Fast || CC == CallingConv::GHC ||
3206 CC == CallingConv::X86_RegCall || CC == CallingConv::HiPE ||
3207 CC == CallingConv::HHVM || CC == CallingConv::Tail);
3208}
3209
3210/// Return true if we might ever do TCO for calls with this calling convention.
3211static bool mayTailCallThisCC(CallingConv::ID CC) {
3212 switch (CC) {
3213 // C calling conventions:
3214 case CallingConv::C:
3215 case CallingConv::Win64:
3216 case CallingConv::X86_64_SysV:
3217 // Callee pop conventions:
3218 case CallingConv::X86_ThisCall:
3219 case CallingConv::X86_StdCall:
3220 case CallingConv::X86_VectorCall:
3221 case CallingConv::X86_FastCall:
3222 // Swift:
3223 case CallingConv::Swift:
3224 return true;
3225 default:
3226 return canGuaranteeTCO(CC);
3227 }
3228}
3229
3230/// Return true if the function is being made into a tailcall target by
3231/// changing its ABI.
3232static bool shouldGuaranteeTCO(CallingConv::ID CC, bool GuaranteedTailCallOpt) {
3233 return (GuaranteedTailCallOpt && canGuaranteeTCO(CC)) || CC == CallingConv::Tail;
3234}
3235
3236bool X86TargetLowering::mayBeEmittedAsTailCall(const CallInst *CI) const {
3237 if (!CI->isTailCall())
3238 return false;
3239
3240 ImmutableCallSite CS(CI);
3241 CallingConv::ID CalleeCC = CS.getCallingConv();
3242 if (!mayTailCallThisCC(CalleeCC))
3243 return false;
3244
3245 return true;
3246}
3247
3248SDValue
3249X86TargetLowering::LowerMemArgument(SDValue Chain, CallingConv::ID CallConv,
3250 const SmallVectorImpl<ISD::InputArg> &Ins,
3251 const SDLoc &dl, SelectionDAG &DAG,
3252 const CCValAssign &VA,
3253 MachineFrameInfo &MFI, unsigned i) const {
3254 // Create the nodes corresponding to a load from this parameter slot.
3255 ISD::ArgFlagsTy Flags = Ins[i].Flags;
3256 bool AlwaysUseMutable = shouldGuaranteeTCO(
3257 CallConv, DAG.getTarget().Options.GuaranteedTailCallOpt);
3258 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
3259 EVT ValVT;
3260 MVT PtrVT = getPointerTy(DAG.getDataLayout());
3261
3262 // If value is passed by pointer we have address passed instead of the value
3263 // itself. No need to extend if the mask value and location share the same
3264 // absolute size.
3265 bool ExtendedInMem =
3266 VA.isExtInLoc() && VA.getValVT().getScalarType() == MVT::i1 &&
3267 VA.getValVT().getSizeInBits() != VA.getLocVT().getSizeInBits();
3268
3269 if (VA.getLocInfo() == CCValAssign::Indirect || ExtendedInMem)
3270 ValVT = VA.getLocVT();
3271 else
3272 ValVT = VA.getValVT();
3273
3274 // FIXME: For now, all byval parameter objects are marked mutable. This can be
3275 // changed with more analysis.
3276 // In case of tail call optimization mark all arguments mutable. Since they
3277 // could be overwritten by lowering of arguments in case of a tail call.
3278 if (Flags.isByVal()) {
3279 unsigned Bytes = Flags.getByValSize();
3280 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
3281
3282 // FIXME: For now, all byval parameter objects are marked as aliasing. This
3283 // can be improved with deeper analysis.
3284 int FI = MFI.CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable,
3285 /*isAliased=*/true);
3286 return DAG.getFrameIndex(FI, PtrVT);
3287 }
3288
3289 // This is an argument in memory. We might be able to perform copy elision.
3290 // If the argument is passed directly in memory without any extension, then we
3291 // can perform copy elision. Large vector types, for example, may be passed
3292 // indirectly by pointer.
3293 if (Flags.isCopyElisionCandidate() &&
3294 VA.getLocInfo() != CCValAssign::Indirect && !ExtendedInMem) {
3295 EVT ArgVT = Ins[i].ArgVT;
3296 SDValue PartAddr;
3297 if (Ins[i].PartOffset == 0) {
3298 // If this is a one-part value or the first part of a multi-part value,
3299 // create a stack object for the entire argument value type and return a
3300 // load from our portion of it. This assumes that if the first part of an
3301 // argument is in memory, the rest will also be in memory.
3302 int FI = MFI.CreateFixedObject(ArgVT.getStoreSize(), VA.getLocMemOffset(),
3303 /*IsImmutable=*/false);
3304 PartAddr = DAG.getFrameIndex(FI, PtrVT);
3305 return DAG.getLoad(
3306 ValVT, dl, Chain, PartAddr,
3307 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI));
3308 } else {
3309 // This is not the first piece of an argument in memory. See if there is
3310 // already a fixed stack object including this offset. If so, assume it
3311 // was created by the PartOffset == 0 branch above and create a load from
3312 // the appropriate offset into it.
3313 int64_t PartBegin = VA.getLocMemOffset();
3314 int64_t PartEnd = PartBegin + ValVT.getSizeInBits() / 8;
3315 int FI = MFI.getObjectIndexBegin();
3316 for (; MFI.isFixedObjectIndex(FI); ++FI) {
3317 int64_t ObjBegin = MFI.getObjectOffset(FI);
3318 int64_t ObjEnd = ObjBegin + MFI.getObjectSize(FI);
3319 if (ObjBegin <= PartBegin && PartEnd <= ObjEnd)
3320 break;
3321 }
3322 if (MFI.isFixedObjectIndex(FI)) {
3323 SDValue Addr =
3324 DAG.getNode(ISD::ADD, dl, PtrVT, DAG.getFrameIndex(FI, PtrVT),
3325 DAG.getIntPtrConstant(Ins[i].PartOffset, dl));
3326 return DAG.getLoad(
3327 ValVT, dl, Chain, Addr,
3328 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI,
3329 Ins[i].PartOffset));
3330 }
3331 }
3332 }
3333
3334 int FI = MFI.CreateFixedObject(ValVT.getSizeInBits() / 8,
3335 VA.getLocMemOffset(), isImmutable);
3336
3337 // Set SExt or ZExt flag.
3338 if (VA.getLocInfo() == CCValAssign::ZExt) {
3339 MFI.setObjectZExt(FI, true);
3340 } else if (VA.getLocInfo() == CCValAssign::SExt) {
3341 MFI.setObjectSExt(FI, true);
3342 }
3343
3344 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3345 SDValue Val = DAG.getLoad(
3346 ValVT, dl, Chain, FIN,
3347 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI));
3348 return ExtendedInMem
3349 ? (VA.getValVT().isVector()
3350 ? DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VA.getValVT(), Val)
3351 : DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val))
3352 : Val;
3353}
3354
3355// FIXME: Get this from tablegen.
3356static ArrayRef<MCPhysReg> get64BitArgumentGPRs(CallingConv::ID CallConv,
3357 const X86Subtarget &Subtarget) {
3358 assert(Subtarget.is64Bit())((Subtarget.is64Bit()) ? static_cast<void> (0) : __assert_fail
("Subtarget.is64Bit()", "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 3358, __PRETTY_FUNCTION__))
;
3359
3360 if (Subtarget.isCallingConvWin64(CallConv)) {
3361 static const MCPhysReg GPR64ArgRegsWin64[] = {
3362 X86::RCX, X86::RDX, X86::R8, X86::R9
3363 };
3364 return makeArrayRef(std::begin(GPR64ArgRegsWin64), std::end(GPR64ArgRegsWin64));
3365 }
3366
3367 static const MCPhysReg GPR64ArgRegs64Bit[] = {
3368 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
3369 };
3370 return makeArrayRef(std::begin(GPR64ArgRegs64Bit), std::end(GPR64ArgRegs64Bit));
3371}
3372
3373// FIXME: Get this from tablegen.
3374static ArrayRef<MCPhysReg> get64BitArgumentXMMs(MachineFunction &MF,
3375 CallingConv::ID CallConv,
3376 const X86Subtarget &Subtarget) {
3377 assert(Subtarget.is64Bit())((Subtarget.is64Bit()) ? static_cast<void> (0) : __assert_fail
("Subtarget.is64Bit()", "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 3377, __PRETTY_FUNCTION__))
;
3378 if (Subtarget.isCallingConvWin64(CallConv)) {
3379 // The XMM registers which might contain var arg parameters are shadowed
3380 // in their paired GPR. So we only need to save the GPR to their home
3381 // slots.
3382 // TODO: __vectorcall will change this.
3383 return None;
3384 }
3385
3386 const Function &F = MF.getFunction();
3387 bool NoImplicitFloatOps = F.hasFnAttribute(Attribute::NoImplicitFloat);
3388 bool isSoftFloat = Subtarget.useSoftFloat();
3389 assert(!(isSoftFloat && NoImplicitFloatOps) &&((!(isSoftFloat && NoImplicitFloatOps) && "SSE register cannot be used when SSE is disabled!"
) ? static_cast<void> (0) : __assert_fail ("!(isSoftFloat && NoImplicitFloatOps) && \"SSE register cannot be used when SSE is disabled!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 3390, __PRETTY_FUNCTION__))
3390 "SSE register cannot be used when SSE is disabled!")((!(isSoftFloat && NoImplicitFloatOps) && "SSE register cannot be used when SSE is disabled!"
) ? static_cast<void> (0) : __assert_fail ("!(isSoftFloat && NoImplicitFloatOps) && \"SSE register cannot be used when SSE is disabled!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 3390, __PRETTY_FUNCTION__))
;
3391 if (isSoftFloat || NoImplicitFloatOps || !Subtarget.hasSSE1())
3392 // Kernel mode asks for SSE to be disabled, so there are no XMM argument
3393 // registers.
3394 return None;
3395
3396 static const MCPhysReg XMMArgRegs64Bit[] = {
3397 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
3398 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
3399 };
3400 return makeArrayRef(std::begin(XMMArgRegs64Bit), std::end(XMMArgRegs64Bit));
3401}
3402
3403#ifndef NDEBUG
3404static bool isSortedByValueNo(ArrayRef<CCValAssign> ArgLocs) {
3405 return std::is_sorted(ArgLocs.begin(), ArgLocs.end(),
3406 [](const CCValAssign &A, const CCValAssign &B) -> bool {
3407 return A.getValNo() < B.getValNo();
3408 });
3409}
3410#endif
3411
3412SDValue X86TargetLowering::LowerFormalArguments(
3413 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
3414 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
3415 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
3416 MachineFunction &MF = DAG.getMachineFunction();
3417 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
3418 const TargetFrameLowering &TFI = *Subtarget.getFrameLowering();
3419
3420 const Function &F = MF.getFunction();
3421 if (F.hasExternalLinkage() && Subtarget.isTargetCygMing() &&
3422 F.getName() == "main")
3423 FuncInfo->setForceFramePointer(true);
3424
3425 MachineFrameInfo &MFI = MF.getFrameInfo();
3426 bool Is64Bit = Subtarget.is64Bit();
3427 bool IsWin64 = Subtarget.isCallingConvWin64(CallConv);
3428
3429 assert(((!(isVarArg && canGuaranteeTCO(CallConv)) &&
"Var args not supported with calling conv' regcall, fastcc, ghc or hipe"
) ? static_cast<void> (0) : __assert_fail ("!(isVarArg && canGuaranteeTCO(CallConv)) && \"Var args not supported with calling conv' regcall, fastcc, ghc or hipe\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 3431, __PRETTY_FUNCTION__))
3430 !(isVarArg && canGuaranteeTCO(CallConv)) &&((!(isVarArg && canGuaranteeTCO(CallConv)) &&
"Var args not supported with calling conv' regcall, fastcc, ghc or hipe"
) ? static_cast<void> (0) : __assert_fail ("!(isVarArg && canGuaranteeTCO(CallConv)) && \"Var args not supported with calling conv' regcall, fastcc, ghc or hipe\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 3431, __PRETTY_FUNCTION__))
3431 "Var args not supported with calling conv' regcall, fastcc, ghc or hipe")((!(isVarArg && canGuaranteeTCO(CallConv)) &&
"Var args not supported with calling conv' regcall, fastcc, ghc or hipe"
) ? static_cast<void> (0) : __assert_fail ("!(isVarArg && canGuaranteeTCO(CallConv)) && \"Var args not supported with calling conv' regcall, fastcc, ghc or hipe\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 3431, __PRETTY_FUNCTION__))
;
3432
3433 // Assign locations to all of the incoming arguments.
3434 SmallVector<CCValAssign, 16> ArgLocs;
3435 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
3436
3437 // Allocate shadow area for Win64.
3438 if (IsWin64)
3439 CCInfo.AllocateStack(32, 8);
3440
3441 CCInfo.AnalyzeArguments(Ins, CC_X86);
3442
3443 // In vectorcall calling convention a second pass is required for the HVA
3444 // types.
3445 if (CallingConv::X86_VectorCall == CallConv) {
3446 CCInfo.AnalyzeArgumentsSecondPass(Ins, CC_X86);
3447 }
3448
3449 // The next loop assumes that the locations are in the same order of the
3450 // input arguments.
3451 assert(isSortedByValueNo(ArgLocs) &&((isSortedByValueNo(ArgLocs) && "Argument Location list must be sorted before lowering"
) ? static_cast<void> (0) : __assert_fail ("isSortedByValueNo(ArgLocs) && \"Argument Location list must be sorted before lowering\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 3452, __PRETTY_FUNCTION__))
3452 "Argument Location list must be sorted before lowering")((isSortedByValueNo(ArgLocs) && "Argument Location list must be sorted before lowering"
) ? static_cast<void> (0) : __assert_fail ("isSortedByValueNo(ArgLocs) && \"Argument Location list must be sorted before lowering\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 3452, __PRETTY_FUNCTION__))
;
3453
3454 SDValue ArgValue;
3455 for (unsigned I = 0, InsIndex = 0, E = ArgLocs.size(); I != E;
3456 ++I, ++InsIndex) {
3457 assert(InsIndex < Ins.size() && "Invalid Ins index")((InsIndex < Ins.size() && "Invalid Ins index") ? static_cast
<void> (0) : __assert_fail ("InsIndex < Ins.size() && \"Invalid Ins index\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 3457, __PRETTY_FUNCTION__))
;
3458 CCValAssign &VA = ArgLocs[I];
3459
3460 if (VA.isRegLoc()) {
3461 EVT RegVT = VA.getLocVT();
3462 if (VA.needsCustom()) {
3463 assert(((VA.getValVT() == MVT::v64i1 && "Currently the only custom case is when we split v64i1 to 2 regs"
) ? static_cast<void> (0) : __assert_fail ("VA.getValVT() == MVT::v64i1 && \"Currently the only custom case is when we split v64i1 to 2 regs\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 3465, __PRETTY_FUNCTION__))
3464 VA.getValVT() == MVT::v64i1 &&((VA.getValVT() == MVT::v64i1 && "Currently the only custom case is when we split v64i1 to 2 regs"
) ? static_cast<void> (0) : __assert_fail ("VA.getValVT() == MVT::v64i1 && \"Currently the only custom case is when we split v64i1 to 2 regs\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 3465, __PRETTY_FUNCTION__))
3465 "Currently the only custom case is when we split v64i1 to 2 regs")((VA.getValVT() == MVT::v64i1 && "Currently the only custom case is when we split v64i1 to 2 regs"
) ? static_cast<void> (0) : __assert_fail ("VA.getValVT() == MVT::v64i1 && \"Currently the only custom case is when we split v64i1 to 2 regs\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 3465, __PRETTY_FUNCTION__))
;
3466
3467 // v64i1 values, in regcall calling convention, that are
3468 // compiled to 32 bit arch, are split up into two registers.
3469 ArgValue =
3470 getv64i1Argument(VA, ArgLocs[++I], Chain, DAG, dl, Subtarget);
3471 } else {
3472 const TargetRegisterClass *RC;
3473 if (RegVT == MVT::i8)
3474 RC = &X86::GR8RegClass;
3475 else if (RegVT == MVT::i16)
3476 RC = &X86::GR16RegClass;
3477 else if (RegVT == MVT::i32)
3478 RC = &X86::GR32RegClass;
3479 else if (Is64Bit && RegVT == MVT::i64)
3480 RC = &X86::GR64RegClass;
3481 else if (RegVT == MVT::f32)
3482 RC = Subtarget.hasAVX512() ? &X86::FR32XRegClass : &X86::FR32RegClass;
3483 else if (RegVT == MVT::f64)
3484 RC = Subtarget.hasAVX512() ? &X86::FR64XRegClass : &X86::FR64RegClass;
3485 else if (RegVT == MVT::f80)
3486 RC = &X86::RFP80RegClass;
3487 else if (RegVT == MVT::f128)
3488 RC = &X86::VR128RegClass;
3489 else if (RegVT.is512BitVector())
3490 RC = &X86::VR512RegClass;
3491 else if (RegVT.is256BitVector())
3492 RC = Subtarget.hasVLX() ? &X86::VR256XRegClass : &X86::VR256RegClass;
3493 else if (RegVT.is128BitVector())
3494 RC = Subtarget.hasVLX() ? &X86::VR128XRegClass : &X86::VR128RegClass;
3495 else if (RegVT == MVT::x86mmx)
3496 RC = &X86::VR64RegClass;
3497 else if (RegVT == MVT::v1i1)
3498 RC = &X86::VK1RegClass;
3499 else if (RegVT == MVT::v8i1)
3500 RC = &X86::VK8RegClass;
3501 else if (RegVT == MVT::v16i1)
3502 RC = &X86::VK16RegClass;
3503 else if (RegVT == MVT::v32i1)
3504 RC = &X86::VK32RegClass;
3505 else if (RegVT == MVT::v64i1)
3506 RC = &X86::VK64RegClass;
3507 else
3508 llvm_unreachable("Unknown argument type!")::llvm::llvm_unreachable_internal("Unknown argument type!", "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 3508)
;
3509
3510 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
3511 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
3512 }
3513
3514 // If this is an 8 or 16-bit value, it is really passed promoted to 32
3515 // bits. Insert an assert[sz]ext to capture this, then truncate to the
3516 // right size.
3517 if (VA.getLocInfo() == CCValAssign::SExt)
3518 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
3519 DAG.getValueType(VA.getValVT()));
3520 else if (VA.getLocInfo() == CCValAssign::ZExt)
3521 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
3522 DAG.getValueType(VA.getValVT()));
3523 else if (VA.getLocInfo() == CCValAssign::BCvt)
3524 ArgValue = DAG.getBitcast(VA.getValVT(), ArgValue);
3525
3526 if (VA.isExtInLoc()) {
3527 // Handle MMX values passed in XMM regs.
3528 if (RegVT.isVector() && VA.getValVT().getScalarType() != MVT::i1)
3529 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), ArgValue);
3530 else if (VA.getValVT().isVector() &&
3531 VA.getValVT().getScalarType() == MVT::i1 &&
3532 ((VA.getLocVT() == MVT::i64) || (VA.getLocVT() == MVT::i32) ||
3533 (VA.getLocVT() == MVT::i16) || (VA.getLocVT() == MVT::i8))) {
3534 // Promoting a mask type (v*i1) into a register of type i64/i32/i16/i8
3535 ArgValue = lowerRegToMasks(ArgValue, VA.getValVT(), RegVT, dl, DAG);
3536 } else
3537 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
3538 }
3539 } else {
3540 assert(VA.isMemLoc())((VA.isMemLoc()) ? static_cast<void> (0) : __assert_fail
("VA.isMemLoc()", "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 3540, __PRETTY_FUNCTION__))
;
3541 ArgValue =
3542 LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, InsIndex);
3543 }
3544
3545 // If value is passed via pointer - do a load.
3546 if (VA.getLocInfo() == CCValAssign::Indirect && !Ins[I].Flags.isByVal())
3547 ArgValue =
3548 DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue, MachinePointerInfo());
3549
3550 InVals.push_back(ArgValue);
3551 }
3552
3553 for (unsigned I = 0, E = Ins.size(); I != E; ++I) {
3554 // Swift calling convention does not require we copy the sret argument
3555 // into %rax/%eax for the return. We don't set SRetReturnReg for Swift.
3556 if (CallConv == CallingConv::Swift)
3557 continue;
3558
3559 // All x86 ABIs require that for returning structs by value we copy the
3560 // sret argument into %rax/%eax (depending on ABI) for the return. Save
3561 // the argument into a virtual register so that we can access it from the
3562 // return points.
3563 if (Ins[I].Flags.isSRet()) {
3564 unsigned Reg = FuncInfo->getSRetReturnReg();
3565 if (!Reg) {
3566 MVT PtrTy = getPointerTy(DAG.getDataLayout());
3567 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy));
3568 FuncInfo->setSRetReturnReg(Reg);
3569 }
3570 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[I]);
3571 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
3572 break;
3573 }
3574 }
3575
3576 unsigned StackSize = CCInfo.getNextStackOffset();
3577 // Align stack specially for tail calls.
3578 if (shouldGuaranteeTCO(CallConv,
3579 MF.getTarget().Options.GuaranteedTailCallOpt))
3580 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
3581
3582 // If the function takes variable number of arguments, make a frame index for
3583 // the start of the first vararg value... for expansion of llvm.va_start. We
3584 // can skip this if there are no va_start calls.
3585 if (MFI.hasVAStart() &&
3586 (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
3587 CallConv != CallingConv::X86_ThisCall))) {
3588 FuncInfo->setVarArgsFrameIndex(MFI.CreateFixedObject(1, StackSize, true));
3589 }
3590
3591 // Figure out if XMM registers are in use.
3592 assert(!(Subtarget.useSoftFloat() &&((!(Subtarget.useSoftFloat() && F.hasFnAttribute(Attribute
::NoImplicitFloat)) && "SSE register cannot be used when SSE is disabled!"
) ? static_cast<void> (0) : __assert_fail ("!(Subtarget.useSoftFloat() && F.hasFnAttribute(Attribute::NoImplicitFloat)) && \"SSE register cannot be used when SSE is disabled!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 3594, __PRETTY_FUNCTION__))
3593 F.hasFnAttribute(Attribute::NoImplicitFloat)) &&((!(Subtarget.useSoftFloat() && F.hasFnAttribute(Attribute
::NoImplicitFloat)) && "SSE register cannot be used when SSE is disabled!"
) ? static_cast<void> (0) : __assert_fail ("!(Subtarget.useSoftFloat() && F.hasFnAttribute(Attribute::NoImplicitFloat)) && \"SSE register cannot be used when SSE is disabled!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 3594, __PRETTY_FUNCTION__))
3594 "SSE register cannot be used when SSE is disabled!")((!(Subtarget.useSoftFloat() && F.hasFnAttribute(Attribute
::NoImplicitFloat)) && "SSE register cannot be used when SSE is disabled!"
) ? static_cast<void> (0) : __assert_fail ("!(Subtarget.useSoftFloat() && F.hasFnAttribute(Attribute::NoImplicitFloat)) && \"SSE register cannot be used when SSE is disabled!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 3594, __PRETTY_FUNCTION__))
;
3595
3596 // 64-bit calling conventions support varargs and register parameters, so we
3597 // have to do extra work to spill them in the prologue.
3598 if (Is64Bit && isVarArg && MFI.hasVAStart()) {
3599 // Find the first unallocated argument registers.
3600 ArrayRef<MCPhysReg> ArgGPRs = get64BitArgumentGPRs(CallConv, Subtarget);
3601 ArrayRef<MCPhysReg> ArgXMMs = get64BitArgumentXMMs(MF, CallConv, Subtarget);
3602 unsigned NumIntRegs = CCInfo.getFirstUnallocated(ArgGPRs);
3603 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(ArgXMMs);
3604 assert(!(NumXMMRegs && !Subtarget.hasSSE1()) &&((!(NumXMMRegs && !Subtarget.hasSSE1()) && "SSE register cannot be used when SSE is disabled!"
) ? static_cast<void> (0) : __assert_fail ("!(NumXMMRegs && !Subtarget.hasSSE1()) && \"SSE register cannot be used when SSE is disabled!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 3605, __PRETTY_FUNCTION__))
3605 "SSE register cannot be used when SSE is disabled!")((!(NumXMMRegs && !Subtarget.hasSSE1()) && "SSE register cannot be used when SSE is disabled!"
) ? static_cast<void> (0) : __assert_fail ("!(NumXMMRegs && !Subtarget.hasSSE1()) && \"SSE register cannot be used when SSE is disabled!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 3605, __PRETTY_FUNCTION__))
;
3606
3607 // Gather all the live in physical registers.
3608 SmallVector<SDValue, 6> LiveGPRs;
3609 SmallVector<SDValue, 8> LiveXMMRegs;
3610 SDValue ALVal;
3611 for (MCPhysReg Reg : ArgGPRs.slice(NumIntRegs)) {
3612 unsigned GPR = MF.addLiveIn(Reg, &X86::GR64RegClass);
3613 LiveGPRs.push_back(
3614 DAG.getCopyFromReg(Chain, dl, GPR, MVT::i64));
3615 }
3616 if (!ArgXMMs.empty()) {
3617 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
3618 ALVal = DAG.getCopyFromReg(Chain, dl, AL, MVT::i8);
3619 for (MCPhysReg Reg : ArgXMMs.slice(NumXMMRegs)) {
3620 unsigned XMMReg = MF.addLiveIn(Reg, &X86::VR128RegClass);
3621 LiveXMMRegs.push_back(
3622 DAG.getCopyFromReg(Chain, dl, XMMReg, MVT::v4f32));
3623 }
3624 }
3625
3626 if (IsWin64) {
3627 // Get to the caller-allocated home save location. Add 8 to account
3628 // for the return address.
3629 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
3630 FuncInfo->setRegSaveFrameIndex(
3631 MFI.CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
3632 // Fixup to set vararg frame on shadow area (4 x i64).
3633 if (NumIntRegs < 4)
3634 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
3635 } else {
3636 // For X86-64, if there are vararg parameters that are passed via
3637 // registers, then we must store them to their spots on the stack so
3638 // they may be loaded by dereferencing the result of va_next.
3639 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
3640 FuncInfo->setVarArgsFPOffset(ArgGPRs.size() * 8 + NumXMMRegs * 16);
3641 FuncInfo->setRegSaveFrameIndex(MFI.CreateStackObject(
3642 ArgGPRs.size() * 8 + ArgXMMs.size() * 16, 16, false));
3643 }
3644
3645 // Store the integer parameter registers.
3646 SmallVector<SDValue, 8> MemOps;
3647 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
3648 getPointerTy(DAG.getDataLayout()));
3649 unsigned Offset = FuncInfo->getVarArgsGPOffset();
3650 for (SDValue Val : LiveGPRs) {
3651 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(DAG.getDataLayout()),
3652 RSFIN, DAG.getIntPtrConstant(Offset, dl));
3653 SDValue Store =
3654 DAG.getStore(Val.getValue(1), dl, Val, FIN,
3655 MachinePointerInfo::getFixedStack(
3656 DAG.getMachineFunction(),
3657 FuncInfo->getRegSaveFrameIndex(), Offset));
3658 MemOps.push_back(Store);
3659 Offset += 8;
3660 }
3661
3662 if (!ArgXMMs.empty() && NumXMMRegs != ArgXMMs.size()) {
3663 // Now store the XMM (fp + vector) parameter registers.
3664 SmallVector<SDValue, 12> SaveXMMOps;
3665 SaveXMMOps.push_back(Chain);
3666 SaveXMMOps.push_back(ALVal);
3667 SaveXMMOps.push_back(DAG.getIntPtrConstant(
3668 FuncInfo->getRegSaveFrameIndex(), dl));
3669 SaveXMMOps.push_back(DAG.getIntPtrConstant(
3670 FuncInfo->getVarArgsFPOffset(), dl));
3671 SaveXMMOps.insert(SaveXMMOps.end(), LiveXMMRegs.begin(),
3672 LiveXMMRegs.end());
3673 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
3674 MVT::Other, SaveXMMOps));
3675 }
3676
3677 if (!MemOps.empty())
3678 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
3679 }
3680
3681 if (isVarArg && MFI.hasMustTailInVarArgFunc()) {
3682 // Find the largest legal vector type.
3683 MVT VecVT = MVT::Other;
3684 // FIXME: Only some x86_32 calling conventions support AVX512.
3685 if (Subtarget.useAVX512Regs() &&
3686 (Is64Bit || (CallConv == CallingConv::X86_VectorCall ||
3687 CallConv == CallingConv::Intel_OCL_BI)))
3688 VecVT = MVT::v16f32;
3689 else if (Subtarget.hasAVX())
3690 VecVT = MVT::v8f32;
3691 else if (Subtarget.hasSSE2())
3692 VecVT = MVT::v4f32;
3693
3694 // We forward some GPRs and some vector types.
3695 SmallVector<MVT, 2> RegParmTypes;
3696 MVT IntVT = Is64Bit ? MVT::i64 : MVT::i32;
3697 RegParmTypes.push_back(IntVT);
3698 if (VecVT != MVT::Other)
3699 RegParmTypes.push_back(VecVT);
3700
3701 // Compute the set of forwarded registers. The rest are scratch.
3702 SmallVectorImpl<ForwardedRegister> &Forwards =
3703 FuncInfo->getForwardedMustTailRegParms();
3704 CCInfo.analyzeMustTailForwardedRegisters(Forwards, RegParmTypes, CC_X86);
3705
3706 // Forward AL for SysV x86_64 targets, since it is used for varargs.
3707 if (Is64Bit && !IsWin64 && !CCInfo.isAllocated(X86::AL)) {
3708 unsigned ALVReg = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
3709 Forwards.push_back(ForwardedRegister(ALVReg, X86::AL, MVT::i8));
3710 }
3711
3712 // Copy all forwards from physical to virtual registers.
3713 for (ForwardedRegister &FR : Forwards) {
3714 // FIXME: Can we use a less constrained schedule?
3715 SDValue RegVal = DAG.getCopyFromReg(Chain, dl, FR.VReg, FR.VT);
3716 FR.VReg = MF.getRegInfo().createVirtualRegister(getRegClassFor(FR.VT));
3717 Chain = DAG.getCopyToReg(Chain, dl, FR.VReg, RegVal);
3718 }
3719 }
3720
3721 // Some CCs need callee pop.
3722 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
3723 MF.getTarget().Options.GuaranteedTailCallOpt)) {
3724 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
3725 } else if (CallConv == CallingConv::X86_INTR && Ins.size() == 2) {
3726 // X86 interrupts must pop the error code (and the alignment padding) if
3727 // present.
3728 FuncInfo->setBytesToPopOnReturn(Is64Bit ? 16 : 4);
3729 } else {
3730 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
3731 // If this is an sret function, the return should pop the hidden pointer.
3732 if (!Is64Bit && !canGuaranteeTCO(CallConv) &&
3733 !Subtarget.getTargetTriple().isOSMSVCRT() &&
3734 argsAreStructReturn(Ins, Subtarget.isTargetMCU()) == StackStructReturn)
3735 FuncInfo->setBytesToPopOnReturn(4);
3736 }
3737
3738 if (!Is64Bit) {
3739 // RegSaveFrameIndex is X86-64 only.
3740 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
3741 if (CallConv == CallingConv::X86_FastCall ||
3742 CallConv == CallingConv::X86_ThisCall)
3743 // fastcc functions can't have varargs.
3744 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
3745 }
3746
3747 FuncInfo->setArgumentStackSize(StackSize);
3748
3749 if (WinEHFuncInfo *EHInfo = MF.getWinEHFuncInfo()) {
3750 EHPersonality Personality = classifyEHPersonality(F.getPersonalityFn());
3751 if (Personality == EHPersonality::CoreCLR) {
3752 assert(Is64Bit)((Is64Bit) ? static_cast<void> (0) : __assert_fail ("Is64Bit"
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 3752, __PRETTY_FUNCTION__))
;
3753 // TODO: Add a mechanism to frame lowering that will allow us to indicate
3754 // that we'd prefer this slot be allocated towards the bottom of the frame
3755 // (i.e. near the stack pointer after allocating the frame). Every
3756 // funclet needs a copy of this slot in its (mostly empty) frame, and the
3757 // offset from the bottom of this and each funclet's frame must be the
3758 // same, so the size of funclets' (mostly empty) frames is dictated by
3759 // how far this slot is from the bottom (since they allocate just enough
3760 // space to accommodate holding this slot at the correct offset).
3761 int PSPSymFI = MFI.CreateStackObject(8, 8, /*isSS=*/false);
3762 EHInfo->PSPSymFrameIdx = PSPSymFI;
3763 }
3764 }
3765
3766 if (CallConv == CallingConv::X86_RegCall ||
3767 F.hasFnAttribute("no_caller_saved_registers")) {
3768 MachineRegisterInfo &MRI = MF.getRegInfo();
3769 for (std::pair<unsigned, unsigned> Pair : MRI.liveins())
3770 MRI.disableCalleeSavedRegister(Pair.first);
3771 }
3772
3773 return Chain;
3774}
3775
3776SDValue X86TargetLowering::LowerMemOpCallTo(SDValue Chain, SDValue StackPtr,
3777 SDValue Arg, const SDLoc &dl,
3778 SelectionDAG &DAG,
3779 const CCValAssign &VA,
3780 ISD::ArgFlagsTy Flags) const {
3781 unsigned LocMemOffset = VA.getLocMemOffset();
3782 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset, dl);
3783 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(DAG.getDataLayout()),
3784 StackPtr, PtrOff);
3785 if (Flags.isByVal())
3786 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
3787
3788 return DAG.getStore(
3789 Chain, dl, Arg, PtrOff,
3790 MachinePointerInfo::getStack(DAG.getMachineFunction(), LocMemOffset));
3791}
3792
3793/// Emit a load of return address if tail call
3794/// optimization is performed and it is required.
3795SDValue X86TargetLowering::EmitTailCallLoadRetAddr(
3796 SelectionDAG &DAG, SDValue &OutRetAddr, SDValue Chain, bool IsTailCall,
3797 bool Is64Bit, int FPDiff, const SDLoc &dl) const {
3798 // Adjust the Return address stack slot.
3799 EVT VT = getPointerTy(DAG.getDataLayout());
3800 OutRetAddr = getReturnAddressFrameIndex(DAG);
3801
3802 // Load the "old" Return address.
3803 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo());
3804 return SDValue(OutRetAddr.getNode(), 1);
3805}
3806
3807/// Emit a store of the return address if tail call
3808/// optimization is performed and it is required (FPDiff!=0).
3809static SDValue EmitTailCallStoreRetAddr(SelectionDAG &DAG, MachineFunction &MF,
3810 SDValue Chain, SDValue RetAddrFrIdx,
3811 EVT PtrVT, unsigned SlotSize,
3812 int FPDiff, const SDLoc &dl) {
3813 // Store the return address to the appropriate stack slot.
3814 if (!FPDiff) return Chain;
3815 // Calculate the new stack slot for the return address.
3816 int NewReturnAddrFI =
3817 MF.getFrameInfo().CreateFixedObject(SlotSize, (int64_t)FPDiff - SlotSize,
3818 false);
3819 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, PtrVT);
3820 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
3821 MachinePointerInfo::getFixedStack(
3822 DAG.getMachineFunction(), NewReturnAddrFI));
3823 return Chain;
3824}
3825
3826/// Returns a vector_shuffle mask for an movs{s|d}, movd
3827/// operation of specified width.
3828static SDValue getMOVL(SelectionDAG &DAG, const SDLoc &dl, MVT VT, SDValue V1,
3829 SDValue V2) {
3830 unsigned NumElems = VT.getVectorNumElements();
3831 SmallVector<int, 8> Mask;
3832 Mask.push_back(NumElems);
3833 for (unsigned i = 1; i != NumElems; ++i)
3834 Mask.push_back(i);
3835 return DAG.getVectorShuffle(VT, dl, V1, V2, Mask);
3836}
3837
3838SDValue
3839X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
3840 SmallVectorImpl<SDValue> &InVals) const {
3841 SelectionDAG &DAG = CLI.DAG;
3842 SDLoc &dl = CLI.DL;
3843 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
3844 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
3845 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
3846 SDValue Chain = CLI.Chain;
3847 SDValue Callee = CLI.Callee;
3848 CallingConv::ID CallConv = CLI.CallConv;
3849 bool &isTailCall = CLI.IsTailCall;
3850 bool isVarArg = CLI.IsVarArg;
3851
3852 MachineFunction &MF = DAG.getMachineFunction();
3853 bool Is64Bit = Subtarget.is64Bit();
3854 bool IsWin64 = Subtarget.isCallingConvWin64(CallConv);
3855 StructReturnType SR = callIsStructReturn(Outs, Subtarget.isTargetMCU());
3856 bool IsSibcall = false;
3857 bool IsGuaranteeTCO = MF.getTarget().Options.GuaranteedTailCallOpt ||
3858 CallConv == CallingConv::Tail;
3859 X86MachineFunctionInfo *X86Info = MF.getInfo<X86MachineFunctionInfo>();
3860 const auto *CI = dyn_cast_or_null<CallInst>(CLI.CS.getInstruction());
3861 const Function *Fn = CI ? CI->getCalledFunction() : nullptr;
3862 bool HasNCSR = (CI && CI->hasFnAttr("no_caller_saved_registers")) ||
3863 (Fn && Fn->hasFnAttribute("no_caller_saved_registers"));
3864 const auto *II = dyn_cast_or_null<InvokeInst>(CLI.CS.getInstruction());
3865 bool HasNoCfCheck =
3866 (CI && CI->doesNoCfCheck()) || (II && II->doesNoCfCheck());
3867 const Module *M = MF.getMMI().getModule();
3868 Metadata *IsCFProtectionSupported = M->getModuleFlag("cf-protection-branch");
3869
3870 MachineFunction::CallSiteInfo CSInfo;
3871
3872 if (CallConv == CallingConv::X86_INTR)
3873 report_fatal_error("X86 interrupts may not be called directly");
3874
3875 if (Subtarget.isPICStyleGOT() && !IsGuaranteeTCO) {
3876 // If we are using a GOT, disable tail calls to external symbols with
3877 // default visibility. Tail calling such a symbol requires using a GOT
3878 // relocation, which forces early binding of the symbol. This breaks code
3879 // that require lazy function symbol resolution. Using musttail or
3880 // GuaranteedTailCallOpt will override this.
3881 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
3882 if (!G || (!G->getGlobal()->hasLocalLinkage() &&
3883 G->getGlobal()->hasDefaultVisibility()))
3884 isTailCall = false;
3885 }
3886
3887 bool IsMustTail = CLI.CS && CLI.CS.isMustTailCall();
3888 if (IsMustTail) {
3889 // Force this to be a tail call. The verifier rules are enough to ensure
3890 // that we can lower this successfully without moving the return address
3891 // around.
3892 isTailCall = true;
3893 } else if (isTailCall) {
3894 // Check if it's really possible to do a tail call.
3895 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
3896 isVarArg, SR != NotStructReturn,
3897 MF.getFunction().hasStructRetAttr(), CLI.RetTy,
3898 Outs, OutVals, Ins, DAG);
3899
3900 // Sibcalls are automatically detected tailcalls which do not require
3901 // ABI changes.
3902 if (!IsGuaranteeTCO && isTailCall)
3903 IsSibcall = true;
3904
3905 if (isTailCall)
3906 ++NumTailCalls;
3907 }
3908
3909 assert(!(isVarArg && canGuaranteeTCO(CallConv)) &&((!(isVarArg && canGuaranteeTCO(CallConv)) &&
"Var args not supported with calling convention fastcc, ghc or hipe"
) ? static_cast<void> (0) : __assert_fail ("!(isVarArg && canGuaranteeTCO(CallConv)) && \"Var args not supported with calling convention fastcc, ghc or hipe\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 3910, __PRETTY_FUNCTION__))
3910 "Var args not supported with calling convention fastcc, ghc or hipe")((!(isVarArg && canGuaranteeTCO(CallConv)) &&
"Var args not supported with calling convention fastcc, ghc or hipe"
) ? static_cast<void> (0) : __assert_fail ("!(isVarArg && canGuaranteeTCO(CallConv)) && \"Var args not supported with calling convention fastcc, ghc or hipe\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 3910, __PRETTY_FUNCTION__))
;
3911
3912 // Analyze operands of the call, assigning locations to each operand.
3913 SmallVector<CCValAssign, 16> ArgLocs;
3914 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
3915
3916 // Allocate shadow area for Win64.
3917 if (IsWin64)
3918 CCInfo.AllocateStack(32, 8);
3919
3920 CCInfo.AnalyzeArguments(Outs, CC_X86);
3921
3922 // In vectorcall calling convention a second pass is required for the HVA
3923 // types.
3924 if (CallingConv::X86_VectorCall == CallConv) {
3925 CCInfo.AnalyzeArgumentsSecondPass(Outs, CC_X86);
3926 }
3927
3928 // Get a count of how many bytes are to be pushed on the stack.
3929 unsigned NumBytes = CCInfo.getAlignedCallFrameSize();
3930 if (IsSibcall)
3931 // This is a sibcall. The memory operands are available in caller's
3932 // own caller's stack.
3933 NumBytes = 0;
3934 else if (IsGuaranteeTCO && canGuaranteeTCO(CallConv))
3935 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
3936
3937 int FPDiff = 0;
3938 if (isTailCall && !IsSibcall && !IsMustTail) {
3939 // Lower arguments at fp - stackoffset + fpdiff.
3940 unsigned NumBytesCallerPushed = X86Info->getBytesToPopOnReturn();
3941
3942 FPDiff = NumBytesCallerPushed - NumBytes;
3943
3944 // Set the delta of movement of the returnaddr stackslot.
3945 // But only set if delta is greater than previous delta.
3946 if (FPDiff < X86Info->getTCReturnAddrDelta())
3947 X86Info->setTCReturnAddrDelta(FPDiff);
3948 }
3949
3950 unsigned NumBytesToPush = NumBytes;
3951 unsigned NumBytesToPop = NumBytes;
3952
3953 // If we have an inalloca argument, all stack space has already been allocated
3954 // for us and be right at the top of the stack. We don't support multiple
3955 // arguments passed in memory when using inalloca.
3956 if (!Outs.empty() && Outs.back().Flags.isInAlloca()) {
3957 NumBytesToPush = 0;
3958 if (!ArgLocs.back().isMemLoc())
3959 report_fatal_error("cannot use inalloca attribute on a register "
3960 "parameter");
3961 if (ArgLocs.back().getLocMemOffset() != 0)
3962 report_fatal_error("any parameter with the inalloca attribute must be "
3963 "the only memory argument");
3964 }
3965
3966 if (!IsSibcall && !IsMustTail)
3967 Chain = DAG.getCALLSEQ_START(Chain, NumBytesToPush,
3968 NumBytes - NumBytesToPush, dl);
3969
3970 SDValue RetAddrFrIdx;
3971 // Load return address for tail calls.
3972 if (isTailCall && FPDiff)
3973 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
3974 Is64Bit, FPDiff, dl);
3975
3976 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
3977 SmallVector<SDValue, 8> MemOpChains;
3978 SDValue StackPtr;
3979
3980 // The next loop assumes that the locations are in the same order of the
3981 // input arguments.
3982 assert(isSortedByValueNo(ArgLocs) &&((isSortedByValueNo(ArgLocs) && "Argument Location list must be sorted before lowering"
) ? static_cast<void> (0) : __assert_fail ("isSortedByValueNo(ArgLocs) && \"Argument Location list must be sorted before lowering\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 3983, __PRETTY_FUNCTION__))
3983 "Argument Location list must be sorted before lowering")((isSortedByValueNo(ArgLocs) && "Argument Location list must be sorted before lowering"
) ? static_cast<void> (0) : __assert_fail ("isSortedByValueNo(ArgLocs) && \"Argument Location list must be sorted before lowering\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 3983, __PRETTY_FUNCTION__))
;
3984
3985 // Walk the register/memloc assignments, inserting copies/loads. In the case
3986 // of tail call optimization arguments are handle later.
3987 const X86RegisterInfo *RegInfo = Subtarget.getRegisterInfo();
3988 for (unsigned I = 0, OutIndex = 0, E = ArgLocs.size(); I != E;
3989 ++I, ++OutIndex) {
3990 assert(OutIndex < Outs.size() && "Invalid Out index")((OutIndex < Outs.size() && "Invalid Out index") ?
static_cast<void> (0) : __assert_fail ("OutIndex < Outs.size() && \"Invalid Out index\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 3990, __PRETTY_FUNCTION__))
;
3991 // Skip inalloca arguments, they have already been written.
3992 ISD::ArgFlagsTy Flags = Outs[OutIndex].Flags;
3993 if (Flags.isInAlloca())
3994 continue;
3995
3996 CCValAssign &VA = ArgLocs[I];
3997 EVT RegVT = VA.getLocVT();
3998 SDValue Arg = OutVals[OutIndex];
3999 bool isByVal = Flags.isByVal();
4000
4001 // Promote the value if needed.
4002 switch (VA.getLocInfo()) {
4003 default: llvm_unreachable("Unknown loc info!")::llvm::llvm_unreachable_internal("Unknown loc info!", "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 4003)
;
4004 case CCValAssign::Full: break;
4005 case CCValAssign::SExt:
4006 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
4007 break;
4008 case CCValAssign::ZExt:
4009 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
4010 break;
4011 case CCValAssign::AExt:
4012 if (Arg.getValueType().isVector() &&
4013 Arg.getValueType().getVectorElementType() == MVT::i1)
4014 Arg = lowerMasksToReg(Arg, RegVT, dl, DAG);
4015 else if (RegVT.is128BitVector()) {
4016 // Special case: passing MMX values in XMM registers.
4017 Arg = DAG.getBitcast(MVT::i64, Arg);
4018 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
4019 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
4020 } else
4021 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
4022 break;
4023 case CCValAssign::BCvt:
4024 Arg = DAG.getBitcast(RegVT, Arg);
4025 break;
4026 case CCValAssign::Indirect: {
4027 if (isByVal) {
4028 // Memcpy the argument to a temporary stack slot to prevent
4029 // the caller from seeing any modifications the callee may make
4030 // as guaranteed by the `byval` attribute.
4031 int FrameIdx = MF.getFrameInfo().CreateStackObject(
4032 Flags.getByValSize(),
4033 std::max(Align(16), Flags.getNonZeroByValAlign()), false);
4034 SDValue StackSlot =
4035 DAG.getFrameIndex(FrameIdx, getPointerTy(DAG.getDataLayout()));
4036 Chain =
4037 CreateCopyOfByValArgument(Arg, StackSlot, Chain, Flags, DAG, dl);
4038 // From now on treat this as a regular pointer
4039 Arg = StackSlot;
4040 isByVal = false;
4041 } else {
4042 // Store the argument.
4043 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
4044 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
4045 Chain = DAG.getStore(
4046 Chain, dl, Arg, SpillSlot,
4047 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI));
4048 Arg = SpillSlot;
4049 }
4050 break;
4051 }
4052 }
4053
4054 if (VA.needsCustom()) {
4055 assert(VA.getValVT() == MVT::v64i1 &&((VA.getValVT() == MVT::v64i1 && "Currently the only custom case is when we split v64i1 to 2 regs"
) ? static_cast<void> (0) : __assert_fail ("VA.getValVT() == MVT::v64i1 && \"Currently the only custom case is when we split v64i1 to 2 regs\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 4056, __PRETTY_FUNCTION__))
4056 "Currently the only custom case is when we split v64i1 to 2 regs")((VA.getValVT() == MVT::v64i1 && "Currently the only custom case is when we split v64i1 to 2 regs"
) ? static_cast<void> (0) : __assert_fail ("VA.getValVT() == MVT::v64i1 && \"Currently the only custom case is when we split v64i1 to 2 regs\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 4056, __PRETTY_FUNCTION__))
;
4057 // Split v64i1 value into two registers
4058 Passv64i1ArgInRegs(dl, DAG, Arg, RegsToPass, VA, ArgLocs[++I], Subtarget);
4059 } else if (VA.isRegLoc()) {
4060 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
4061 const TargetOptions &Options = DAG.getTarget().Options;
4062 if (Options.EnableDebugEntryValues)
4063 CSInfo.emplace_back(VA.getLocReg(), I);
4064 if (isVarArg && IsWin64) {
4065 // Win64 ABI requires argument XMM reg to be copied to the corresponding
4066 // shadow reg if callee is a varargs function.
4067 unsigned ShadowReg = 0;
4068 switch (VA.getLocReg()) {
4069 case X86::XMM0: ShadowReg = X86::RCX; break;
4070 case X86::XMM1: ShadowReg = X86::RDX; break;
4071 case X86::XMM2: ShadowReg = X86::R8; break;
4072 case X86::XMM3: ShadowReg = X86::R9; break;
4073 }
4074 if (ShadowReg)
4075 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
4076 }
4077 } else if (!IsSibcall && (!isTailCall || isByVal)) {
4078 assert(VA.isMemLoc())((VA.isMemLoc()) ? static_cast<void> (0) : __assert_fail
("VA.isMemLoc()", "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 4078, __PRETTY_FUNCTION__))
;
4079 if (!StackPtr.getNode())
4080 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
4081 getPointerTy(DAG.getDataLayout()));
4082 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
4083 dl, DAG, VA, Flags));
4084 }
4085 }
4086
4087 if (!MemOpChains.empty())
4088 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
4089
4090 if (Subtarget.isPICStyleGOT()) {
4091 // ELF / PIC requires GOT in the EBX register before function calls via PLT
4092 // GOT pointer.
4093 if (!isTailCall) {
4094 RegsToPass.push_back(std::make_pair(
4095 unsigned(X86::EBX), DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(),
4096 getPointerTy(DAG.getDataLayout()))));
4097 } else {
4098 // If we are tail calling and generating PIC/GOT style code load the
4099 // address of the callee into ECX. The value in ecx is used as target of
4100 // the tail jump. This is done to circumvent the ebx/callee-saved problem
4101 // for tail calls on PIC/GOT architectures. Normally we would just put the
4102 // address of GOT into ebx and then call target@PLT. But for tail calls
4103 // ebx would be restored (since ebx is callee saved) before jumping to the
4104 // target@PLT.
4105
4106 // Note: The actual moving to ECX is done further down.
4107 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
4108 if (G && !G->getGlobal()->hasLocalLinkage() &&
4109 G->getGlobal()->hasDefaultVisibility())
4110 Callee = LowerGlobalAddress(Callee, DAG);
4111 else if (isa<ExternalSymbolSDNode>(Callee))
4112 Callee = LowerExternalSymbol(Callee, DAG);
4113 }
4114 }
4115
4116 if (Is64Bit && isVarArg && !IsWin64 && !IsMustTail) {
4117 // From AMD64 ABI document:
4118 // For calls that may call functions that use varargs or stdargs
4119 // (prototype-less calls or calls to functions containing ellipsis (...) in
4120 // the declaration) %al is used as hidden argument to specify the number
4121 // of SSE registers used. The contents of %al do not need to match exactly
4122 // the number of registers, but must be an ubound on the number of SSE
4123 // registers used and is in the range 0 - 8 inclusive.
4124
4125 // Count the number of XMM registers allocated.
4126 static const MCPhysReg XMMArgRegs[] = {
4127 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
4128 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
4129 };
4130 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs);
4131 assert((Subtarget.hasSSE1() || !NumXMMRegs)(((Subtarget.hasSSE1() || !NumXMMRegs) && "SSE registers cannot be used when SSE is disabled"
) ? static_cast<void> (0) : __assert_fail ("(Subtarget.hasSSE1() || !NumXMMRegs) && \"SSE registers cannot be used when SSE is disabled\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 4132, __PRETTY_FUNCTION__))
4132 && "SSE registers cannot be used when SSE is disabled")(((Subtarget.hasSSE1() || !NumXMMRegs) && "SSE registers cannot be used when SSE is disabled"
) ? static_cast<void> (0) : __assert_fail ("(Subtarget.hasSSE1() || !NumXMMRegs) && \"SSE registers cannot be used when SSE is disabled\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 4132, __PRETTY_FUNCTION__))
;
4133
4134 RegsToPass.push_back(std::make_pair(unsigned(X86::AL),
4135 DAG.getConstant(NumXMMRegs, dl,
4136 MVT::i8)));
4137 }
4138
4139 if (isVarArg && IsMustTail) {
4140 const auto &Forwards = X86Info->getForwardedMustTailRegParms();
4141 for (const auto &F : Forwards) {
4142 SDValue Val = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
4143 RegsToPass.push_back(std::make_pair(unsigned(F.PReg), Val));
4144 }
4145 }
4146
4147 // For tail calls lower the arguments to the 'real' stack slots. Sibcalls
4148 // don't need this because the eligibility check rejects calls that require
4149 // shuffling arguments passed in memory.
4150 if (!IsSibcall && isTailCall) {
4151 // Force all the incoming stack arguments to be loaded from the stack
4152 // before any new outgoing arguments are stored to the stack, because the
4153 // outgoing stack slots may alias the incoming argument stack slots, and
4154 // the alias isn't otherwise explicit. This is slightly more conservative
4155 // than necessary, because it means that each store effectively depends
4156 // on every argument instead of just those arguments it would clobber.
4157 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
4158
4159 SmallVector<SDValue, 8> MemOpChains2;
4160 SDValue FIN;
4161 int FI = 0;
4162 for (unsigned I = 0, OutsIndex = 0, E = ArgLocs.size(); I != E;
4163 ++I, ++OutsIndex) {
4164 CCValAssign &VA = ArgLocs[I];
4165
4166 if (VA.isRegLoc()) {
4167 if (VA.needsCustom()) {
4168 assert((CallConv == CallingConv::X86_RegCall) &&(((CallConv == CallingConv::X86_RegCall) && "Expecting custom case only in regcall calling convention"
) ? static_cast<void> (0) : __assert_fail ("(CallConv == CallingConv::X86_RegCall) && \"Expecting custom case only in regcall calling convention\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 4169, __PRETTY_FUNCTION__))
4169 "Expecting custom case only in regcall calling convention")(((CallConv == CallingConv::X86_RegCall) && "Expecting custom case only in regcall calling convention"
) ? static_cast<void> (0) : __assert_fail ("(CallConv == CallingConv::X86_RegCall) && \"Expecting custom case only in regcall calling convention\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 4169, __PRETTY_FUNCTION__))
;
4170 // This means that we are in special case where one argument was
4171 // passed through two register locations - Skip the next location
4172 ++I;
4173 }
4174
4175 continue;
4176 }
4177
4178 assert(VA.isMemLoc())((VA.isMemLoc()) ? static_cast<void> (0) : __assert_fail
("VA.isMemLoc()", "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 4178, __PRETTY_FUNCTION__))
;
4179 SDValue Arg = OutVals[OutsIndex];
4180 ISD::ArgFlagsTy Flags = Outs[OutsIndex].Flags;
4181 // Skip inalloca arguments. They don't require any work.
4182 if (Flags.isInAlloca())
4183 continue;
4184 // Create frame index.
4185 int32_t Offset = VA.getLocMemOffset()+FPDiff;
4186 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
4187 FI = MF.getFrameInfo().CreateFixedObject(OpSize, Offset, true);
4188 FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
4189
4190 if (Flags.isByVal()) {
4191 // Copy relative to framepointer.
4192 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset(), dl);
4193 if (!StackPtr.getNode())
4194 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
4195 getPointerTy(DAG.getDataLayout()));
4196 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(DAG.getDataLayout()),
4197 StackPtr, Source);
4198
4199 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
4200 ArgChain,
4201 Flags, DAG, dl));
4202 } else {
4203 // Store relative to framepointer.
4204 MemOpChains2.push_back(DAG.getStore(
4205 ArgChain, dl, Arg, FIN,
4206 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI)));
4207 }
4208 }
4209
4210 if (!MemOpChains2.empty())
4211 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
4212
4213 // Store the return address to the appropriate stack slot.
4214 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx,
4215 getPointerTy(DAG.getDataLayout()),
4216 RegInfo->getSlotSize(), FPDiff, dl);
4217 }
4218
4219 // Build a sequence of copy-to-reg nodes chained together with token chain
4220 // and flag operands which copy the outgoing args into registers.
4221 SDValue InFlag;
4222 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
4223 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
4224 RegsToPass[i].second, InFlag);
4225 InFlag = Chain.getValue(1);
4226 }
4227
4228 if (DAG.getTarget().getCodeModel() == CodeModel::Large) {
4229 assert(Is64Bit && "Large code model is only legal in 64-bit mode.")((Is64Bit && "Large code model is only legal in 64-bit mode."
) ? static_cast<void> (0) : __assert_fail ("Is64Bit && \"Large code model is only legal in 64-bit mode.\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 4229, __PRETTY_FUNCTION__))
;
4230 // In the 64-bit large code model, we have to make all calls
4231 // through a register, since the call instruction's 32-bit
4232 // pc-relative offset may not be large enough to hold the whole
4233 // address.
4234 } else if (Callee->getOpcode() == ISD::GlobalAddress ||
4235 Callee->getOpcode() == ISD::ExternalSymbol) {
4236 // Lower direct calls to global addresses and external symbols. Setting
4237 // ForCall to true here has the effect of removing WrapperRIP when possible
4238 // to allow direct calls to be selected without first materializing the
4239 // address into a register.
4240 Callee = LowerGlobalOrExternal(Callee, DAG, /*ForCall=*/true);
4241 } else if (Subtarget.isTarget64BitILP32() &&
4242 Callee->getValueType(0) == MVT::i32) {
4243 // Zero-extend the 32-bit Callee address into a 64-bit according to x32 ABI
4244 Callee = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Callee);
4245 }
4246
4247 // Returns a chain & a flag for retval copy to use.
4248 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
4249 SmallVector<SDValue, 8> Ops;
4250
4251 if (!IsSibcall && isTailCall && !IsMustTail) {
4252 Chain = DAG.getCALLSEQ_END(Chain,
4253 DAG.getIntPtrConstant(NumBytesToPop, dl, true),
4254 DAG.getIntPtrConstant(0, dl, true), InFlag, dl);
4255 InFlag = Chain.getValue(1);
4256 }
4257
4258 Ops.push_back(Chain);
4259 Ops.push_back(Callee);
4260
4261 if (isTailCall)
4262 Ops.push_back(DAG.getConstant(FPDiff, dl, MVT::i32));
4263
4264 // Add argument registers to the end of the list so that they are known live
4265 // into the call.
4266 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
4267 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
4268 RegsToPass[i].second.getValueType()));
4269
4270 // Add a register mask operand representing the call-preserved registers.
4271 // If HasNCSR is asserted (attribute NoCallerSavedRegisters exists) then we
4272 // set X86_INTR calling convention because it has the same CSR mask
4273 // (same preserved registers).
4274 const uint32_t *Mask = RegInfo->getCallPreservedMask(
4275 MF, HasNCSR ? (CallingConv::ID)CallingConv::X86_INTR : CallConv);
4276 assert(Mask && "Missing call preserved mask for calling convention")((Mask && "Missing call preserved mask for calling convention"
) ? static_cast<void> (0) : __assert_fail ("Mask && \"Missing call preserved mask for calling convention\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 4276, __PRETTY_FUNCTION__))
;
4277
4278 // If this is an invoke in a 32-bit function using a funclet-based
4279 // personality, assume the function clobbers all registers. If an exception
4280 // is thrown, the runtime will not restore CSRs.
4281 // FIXME: Model this more precisely so that we can register allocate across
4282 // the normal edge and spill and fill across the exceptional edge.
4283 if (!Is64Bit && CLI.CS && CLI.CS.isInvoke()) {
4284 const Function &CallerFn = MF.getFunction();
4285 EHPersonality Pers =
4286 CallerFn.hasPersonalityFn()
4287 ? classifyEHPersonality(CallerFn.getPersonalityFn())
4288 : EHPersonality::Unknown;
4289 if (isFuncletEHPersonality(Pers))
4290 Mask = RegInfo->getNoPreservedMask();
4291 }
4292
4293 // Define a new register mask from the existing mask.
4294 uint32_t *RegMask = nullptr;
4295
4296 // In some calling conventions we need to remove the used physical registers
4297 // from the reg mask.
4298 if (CallConv == CallingConv::X86_RegCall || HasNCSR) {
4299 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
4300
4301 // Allocate a new Reg Mask and copy Mask.
4302 RegMask = MF.allocateRegMask();
4303 unsigned RegMaskSize = MachineOperand::getRegMaskSize(TRI->getNumRegs());
4304 memcpy(RegMask, Mask, sizeof(RegMask[0]) * RegMaskSize);
4305
4306 // Make sure all sub registers of the argument registers are reset
4307 // in the RegMask.
4308 for (auto const &RegPair : RegsToPass)
4309 for (MCSubRegIterator SubRegs(RegPair.first, TRI, /*IncludeSelf=*/true);
4310 SubRegs.isValid(); ++SubRegs)
4311 RegMask[*SubRegs / 32] &= ~(1u << (*SubRegs % 32));
4312
4313 // Create the RegMask Operand according to our updated mask.
4314 Ops.push_back(DAG.getRegisterMask(RegMask));
4315 } else {
4316 // Create the RegMask Operand according to the static mask.
4317 Ops.push_back(DAG.getRegisterMask(Mask));
4318 }
4319
4320 if (InFlag.getNode())
4321 Ops.push_back(InFlag);
4322
4323 if (isTailCall) {
4324 // We used to do:
4325 //// If this is the first return lowered for this function, add the regs
4326 //// to the liveout set for the function.
4327 // This isn't right, although it's probably harmless on x86; liveouts
4328 // should be computed from returns not tail calls. Consider a void
4329 // function making a tail call to a function returning int.
4330 MF.getFrameInfo().setHasTailCall();
4331 SDValue Ret = DAG.getNode(X86ISD::TC_RETURN, dl, NodeTys, Ops);
4332 DAG.addCallSiteInfo(Ret.getNode(), std::move(CSInfo));
4333 return Ret;
4334 }
4335
4336 if (HasNoCfCheck && IsCFProtectionSupported) {
4337 Chain = DAG.getNode(X86ISD::NT_CALL, dl, NodeTys, Ops);
4338 } else {
4339 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, Ops);
4340 }
4341 InFlag = Chain.getValue(1);
4342 DAG.addCallSiteInfo(Chain.getNode(), std::move(CSInfo));
4343
4344 // Save heapallocsite metadata.
4345 if (CLI.CS)
4346 if (MDNode *HeapAlloc = CLI.CS->getMetadata("heapallocsite"))
4347 DAG.addHeapAllocSite(Chain.getNode(), HeapAlloc);
4348
4349 // Create the CALLSEQ_END node.
4350 unsigned NumBytesForCalleeToPop;
4351 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
4352 DAG.getTarget().Options.GuaranteedTailCallOpt))
4353 NumBytesForCalleeToPop = NumBytes; // Callee pops everything
4354 else if (!Is64Bit && !canGuaranteeTCO(CallConv) &&
4355 !Subtarget.getTargetTriple().isOSMSVCRT() &&
4356 SR == StackStructReturn)
4357 // If this is a call to a struct-return function, the callee
4358 // pops the hidden struct pointer, so we have to push it back.
4359 // This is common for Darwin/X86, Linux & Mingw32 targets.
4360 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
4361 NumBytesForCalleeToPop = 4;
4362 else
4363 NumBytesForCalleeToPop = 0; // Callee pops nothing.
4364
4365 // Returns a flag for retval copy to use.
4366 if (!IsSibcall) {
4367 Chain = DAG.getCALLSEQ_END(Chain,
4368 DAG.getIntPtrConstant(NumBytesToPop, dl, true),
4369 DAG.getIntPtrConstant(NumBytesForCalleeToPop, dl,
4370 true),
4371 InFlag, dl);
4372 InFlag = Chain.getValue(1);
4373 }
4374
4375 // Handle result values, copying them out of physregs into vregs that we
4376 // return.
4377 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins, dl, DAG,
4378 InVals, RegMask);
4379}
4380
4381//===----------------------------------------------------------------------===//
4382// Fast Calling Convention (tail call) implementation
4383//===----------------------------------------------------------------------===//
4384
4385// Like std call, callee cleans arguments, convention except that ECX is
4386// reserved for storing the tail called function address. Only 2 registers are
4387// free for argument passing (inreg). Tail call optimization is performed
4388// provided:
4389// * tailcallopt is enabled
4390// * caller/callee are fastcc
4391// On X86_64 architecture with GOT-style position independent code only local
4392// (within module) calls are supported at the moment.
4393// To keep the stack aligned according to platform abi the function
4394// GetAlignedArgumentStackSize ensures that argument delta is always multiples
4395// of stack alignment. (Dynamic linkers need this - Darwin's dyld for example)
4396// If a tail called function callee has more arguments than the caller the
4397// caller needs to make sure that there is room to move the RETADDR to. This is
4398// achieved by reserving an area the size of the argument delta right after the
4399// original RETADDR, but before the saved framepointer or the spilled registers
4400// e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
4401// stack layout:
4402// arg1
4403// arg2
4404// RETADDR
4405// [ new RETADDR
4406// move area ]
4407// (possible EBP)
4408// ESI
4409// EDI
4410// local1 ..
4411
4412/// Make the stack size align e.g 16n + 12 aligned for a 16-byte align
4413/// requirement.
4414unsigned
4415X86TargetLowering::GetAlignedArgumentStackSize(const unsigned StackSize,
4416 SelectionDAG &DAG) const {
4417 const Align StackAlignment(Subtarget.getFrameLowering()->getStackAlignment());
4418 const uint64_t SlotSize = Subtarget.getRegisterInfo()->getSlotSize();
4419 assert(StackSize % SlotSize == 0 &&((StackSize % SlotSize == 0 && "StackSize must be a multiple of SlotSize"
) ? static_cast<void> (0) : __assert_fail ("StackSize % SlotSize == 0 && \"StackSize must be a multiple of SlotSize\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 4420, __PRETTY_FUNCTION__))
4420 "StackSize must be a multiple of SlotSize")((StackSize % SlotSize == 0 && "StackSize must be a multiple of SlotSize"
) ? static_cast<void> (0) : __assert_fail ("StackSize % SlotSize == 0 && \"StackSize must be a multiple of SlotSize\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 4420, __PRETTY_FUNCTION__))
;
4421 return alignTo(StackSize + SlotSize, StackAlignment) - SlotSize;
4422}
4423
4424/// Return true if the given stack call argument is already available in the
4425/// same position (relatively) of the caller's incoming argument stack.
4426static
4427bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
4428 MachineFrameInfo &MFI, const MachineRegisterInfo *MRI,
4429 const X86InstrInfo *TII, const CCValAssign &VA) {
4430 unsigned Bytes = Arg.getValueSizeInBits() / 8;
4431
4432 for (;;) {
4433 // Look through nodes that don't alter the bits of the incoming value.
4434 unsigned Op = Arg.getOpcode();
4435 if (Op == ISD::ZERO_EXTEND || Op == ISD::ANY_EXTEND || Op == ISD::BITCAST) {
4436 Arg = Arg.getOperand(0);
4437 continue;
4438 }
4439 if (Op == ISD::TRUNCATE) {
4440 const SDValue &TruncInput = Arg.getOperand(0);
4441 if (TruncInput.getOpcode() == ISD::AssertZext &&
4442 cast<VTSDNode>(TruncInput.getOperand(1))->getVT() ==
4443 Arg.getValueType()) {
4444 Arg = TruncInput.getOperand(0);
4445 continue;
4446 }
4447 }
4448 break;
4449 }
4450
4451 int FI = INT_MAX2147483647;
4452 if (Arg.getOpcode() == ISD::CopyFromReg) {
4453 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
4454 if (!Register::isVirtualRegister(VR))
4455 return false;
4456 MachineInstr *Def = MRI->getVRegDef(VR);
4457 if (!Def)
4458 return false;
4459 if (!Flags.isByVal()) {
4460 if (!TII->isLoadFromStackSlot(*Def, FI))
4461 return false;
4462 } else {
4463 unsigned Opcode = Def->getOpcode();
4464 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r ||
4465 Opcode == X86::LEA64_32r) &&
4466 Def->getOperand(1).isFI()) {
4467 FI = Def->getOperand(1).getIndex();
4468 Bytes = Flags.getByValSize();
4469 } else
4470 return false;
4471 }
4472 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
4473 if (Flags.isByVal())
4474 // ByVal argument is passed in as a pointer but it's now being
4475 // dereferenced. e.g.
4476 // define @foo(%struct.X* %A) {
4477 // tail call @bar(%struct.X* byval %A)
4478 // }
4479 return false;
4480 SDValue Ptr = Ld->getBasePtr();
4481 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
4482 if (!FINode)
4483 return false;
4484 FI = FINode->getIndex();
4485 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
4486 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
4487 FI = FINode->getIndex();
4488 Bytes = Flags.getByValSize();
4489 } else
4490 return false;
4491
4492 assert(FI != INT_MAX)((FI != 2147483647) ? static_cast<void> (0) : __assert_fail
("FI != INT_MAX", "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 4492, __PRETTY_FUNCTION__))
;
4493 if (!MFI.isFixedObjectIndex(FI))
4494 return false;
4495
4496 if (Offset != MFI.getObjectOffset(FI))
4497 return false;
4498
4499 // If this is not byval, check that the argument stack object is immutable.
4500 // inalloca and argument copy elision can create mutable argument stack
4501 // objects. Byval objects can be mutated, but a byval call intends to pass the
4502 // mutated memory.
4503 if (!Flags.isByVal() && !MFI.isImmutableObjectIndex(FI))
4504 return false;
4505
4506 if (VA.getLocVT().getSizeInBits() > Arg.getValueSizeInBits()) {
4507 // If the argument location is wider than the argument type, check that any
4508 // extension flags match.
4509 if (Flags.isZExt() != MFI.isObjectZExt(FI) ||
4510 Flags.isSExt() != MFI.isObjectSExt(FI)) {
4511 return false;
4512 }
4513 }
4514
4515 return Bytes == MFI.getObjectSize(FI);
4516}
4517
4518/// Check whether the call is eligible for tail call optimization. Targets
4519/// that want to do tail call optimization should implement this function.
4520bool X86TargetLowering::IsEligibleForTailCallOptimization(
4521 SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg,
4522 bool isCalleeStructRet, bool isCallerStructRet, Type *RetTy,
4523 const SmallVectorImpl<ISD::OutputArg> &Outs,
4524 const SmallVectorImpl<SDValue> &OutVals,
4525 const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG) const {
4526 if (!mayTailCallThisCC(CalleeCC))
4527 return false;
4528
4529 // If -tailcallopt is specified, make fastcc functions tail-callable.
4530 MachineFunction &MF = DAG.getMachineFunction();
4531 const Function &CallerF = MF.getFunction();
4532
4533 // If the function return type is x86_fp80 and the callee return type is not,
4534 // then the FP_EXTEND of the call result is not a nop. It's not safe to
4535 // perform a tailcall optimization here.
4536 if (CallerF.getReturnType()->isX86_FP80Ty() && !RetTy->isX86_FP80Ty())
4537 return false;
4538
4539 CallingConv::ID CallerCC = CallerF.getCallingConv();
4540 bool CCMatch = CallerCC == CalleeCC;
4541 bool IsCalleeWin64 = Subtarget.isCallingConvWin64(CalleeCC);
4542 bool IsCallerWin64 = Subtarget.isCallingConvWin64(CallerCC);
4543 bool IsGuaranteeTCO = DAG.getTarget().Options.GuaranteedTailCallOpt ||
4544 CalleeCC == CallingConv::Tail;
4545
4546 // Win64 functions have extra shadow space for argument homing. Don't do the
4547 // sibcall if the caller and callee have mismatched expectations for this
4548 // space.
4549 if (IsCalleeWin64 != IsCallerWin64)
4550 return false;
4551
4552 if (IsGuaranteeTCO) {
4553 if (canGuaranteeTCO(CalleeCC) && CCMatch)
4554 return true;
4555 return false;
4556 }
4557
4558 // Look for obvious safe cases to perform tail call optimization that do not
4559 // require ABI changes. This is what gcc calls sibcall.
4560
4561 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
4562 // emit a special epilogue.
4563 const X86RegisterInfo *RegInfo = Subtarget.getRegisterInfo();
4564 if (RegInfo->needsStackRealignment(MF))
4565 return false;
4566
4567 // Also avoid sibcall optimization if either caller or callee uses struct
4568 // return semantics.
4569 if (isCalleeStructRet || isCallerStructRet)
4570 return false;
4571
4572 // Do not sibcall optimize vararg calls unless all arguments are passed via
4573 // registers.
4574 LLVMContext &C = *DAG.getContext();
4575 if (isVarArg && !Outs.empty()) {
4576 // Optimizing for varargs on Win64 is unlikely to be safe without
4577 // additional testing.
4578 if (IsCalleeWin64 || IsCallerWin64)
4579 return false;
4580
4581 SmallVector<CCValAssign, 16> ArgLocs;
4582 CCState CCInfo(CalleeCC, isVarArg, MF, ArgLocs, C);
4583
4584 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
4585 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
4586 if (!ArgLocs[i].isRegLoc())
4587 return false;
4588 }
4589
4590 // If the call result is in ST0 / ST1, it needs to be popped off the x87
4591 // stack. Therefore, if it's not used by the call it is not safe to optimize
4592 // this into a sibcall.
4593 bool Unused = false;
4594 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
4595 if (!Ins[i].Used) {
4596 Unused = true;
4597 break;
4598 }
4599 }
4600 if (Unused) {
4601 SmallVector<CCValAssign, 16> RVLocs;
4602 CCState CCInfo(CalleeCC, false, MF, RVLocs, C);
4603 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
4604 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
4605 CCValAssign &VA = RVLocs[i];
4606 if (VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1)
4607 return false;
4608 }
4609 }
4610
4611 // Check that the call results are passed in the same way.
4612 if (!CCState::resultsCompatible(CalleeCC, CallerCC, MF, C, Ins,
4613 RetCC_X86, RetCC_X86))
4614 return false;
4615 // The callee has to preserve all registers the caller needs to preserve.
4616 const X86RegisterInfo *TRI = Subtarget.getRegisterInfo();
4617 const uint32_t *CallerPreserved = TRI->getCallPreservedMask(MF, CallerCC);
4618 if (!CCMatch) {
4619 const uint32_t *CalleePreserved = TRI->getCallPreservedMask(MF, CalleeCC);
4620 if (!TRI->regmaskSubsetEqual(CallerPreserved, CalleePreserved))
4621 return false;
4622 }
4623
4624 unsigned StackArgsSize = 0;
4625
4626 // If the callee takes no arguments then go on to check the results of the
4627 // call.
4628 if (!Outs.empty()) {
4629 // Check if stack adjustment is needed. For now, do not do this if any
4630 // argument is passed on the stack.
4631 SmallVector<CCValAssign, 16> ArgLocs;
4632 CCState CCInfo(CalleeCC, isVarArg, MF, ArgLocs, C);
4633
4634 // Allocate shadow area for Win64
4635 if (IsCalleeWin64)
4636 CCInfo.AllocateStack(32, 8);
4637
4638 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
4639 StackArgsSize = CCInfo.getNextStackOffset();
4640
4641 if (CCInfo.getNextStackOffset()) {
4642 // Check if the arguments are already laid out in the right way as
4643 // the caller's fixed stack objects.
4644 MachineFrameInfo &MFI = MF.getFrameInfo();
4645 const MachineRegisterInfo *MRI = &MF.getRegInfo();
4646 const X86InstrInfo *TII = Subtarget.getInstrInfo();
4647 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
4648 CCValAssign &VA = ArgLocs[i];
4649 SDValue Arg = OutVals[i];
4650 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4651 if (VA.getLocInfo() == CCValAssign::Indirect)
4652 return false;
4653 if (!VA.isRegLoc()) {
4654 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
4655 MFI, MRI, TII, VA))
4656 return false;
4657 }
4658 }
4659 }
4660
4661 bool PositionIndependent = isPositionIndependent();
4662 // If the tailcall address may be in a register, then make sure it's
4663 // possible to register allocate for it. In 32-bit, the call address can
4664 // only target EAX, EDX, or ECX since the tail call must be scheduled after
4665 // callee-saved registers are restored. These happen to be the same
4666 // registers used to pass 'inreg' arguments so watch out for those.
4667 if (!Subtarget.is64Bit() && ((!isa<GlobalAddressSDNode>(Callee) &&
4668 !isa<ExternalSymbolSDNode>(Callee)) ||
4669 PositionIndependent)) {
4670 unsigned NumInRegs = 0;
4671 // In PIC we need an extra register to formulate the address computation
4672 // for the callee.
4673 unsigned MaxInRegs = PositionIndependent ? 2 : 3;
4674
4675 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
4676 CCValAssign &VA = ArgLocs[i];
4677 if (!VA.isRegLoc())
4678 continue;
4679 Register Reg = VA.getLocReg();
4680 switch (Reg) {
4681 default: break;
4682 case X86::EAX: case X86::EDX: case X86::ECX:
4683 if (++NumInRegs == MaxInRegs)
4684 return false;
4685 break;
4686 }
4687 }
4688 }
4689
4690 const MachineRegisterInfo &MRI = MF.getRegInfo();
4691 if (!parametersInCSRMatch(MRI, CallerPreserved, ArgLocs, OutVals))
4692 return false;
4693 }
4694
4695 bool CalleeWillPop =
4696 X86::isCalleePop(CalleeCC, Subtarget.is64Bit(), isVarArg,
4697 MF.getTarget().Options.GuaranteedTailCallOpt);
4698
4699 if (unsigned BytesToPop =
4700 MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn()) {
4701 // If we have bytes to pop, the callee must pop them.
4702 bool CalleePopMatches = CalleeWillPop && BytesToPop == StackArgsSize;
4703 if (!CalleePopMatches)
4704 return false;
4705 } else if (CalleeWillPop && StackArgsSize > 0) {
4706 // If we don't have bytes to pop, make sure the callee doesn't pop any.
4707 return false;
4708 }
4709
4710 return true;
4711}
4712
4713FastISel *
4714X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
4715 const TargetLibraryInfo *libInfo) const {
4716 return X86::createFastISel(funcInfo, libInfo);
4717}
4718
4719//===----------------------------------------------------------------------===//
4720// Other Lowering Hooks
4721//===----------------------------------------------------------------------===//
4722
4723static bool MayFoldLoad(SDValue Op) {
4724 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
4725}
4726
4727static bool MayFoldIntoStore(SDValue Op) {
4728 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
4729}
4730
4731static bool MayFoldIntoZeroExtend(SDValue Op) {
4732 if (Op.hasOneUse()) {
4733 unsigned Opcode = Op.getNode()->use_begin()->getOpcode();
4734 return (ISD::ZERO_EXTEND == Opcode);
4735 }
4736 return false;
4737}
4738
4739static bool isTargetShuffle(unsigned Opcode) {
4740 switch(Opcode) {
4741 default: return false;
4742 case X86ISD::BLENDI:
4743 case X86ISD::PSHUFB:
4744 case X86ISD::PSHUFD:
4745 case X86ISD::PSHUFHW:
4746 case X86ISD::PSHUFLW:
4747 case X86ISD::SHUFP:
4748 case X86ISD::INSERTPS:
4749 case X86ISD::EXTRQI:
4750 case X86ISD::INSERTQI:
4751 case X86ISD::PALIGNR:
4752 case X86ISD::VSHLDQ:
4753 case X86ISD::VSRLDQ:
4754 case X86ISD::MOVLHPS:
4755 case X86ISD::MOVHLPS:
4756 case X86ISD::MOVSHDUP:
4757 case X86ISD::MOVSLDUP:
4758 case X86ISD::MOVDDUP:
4759 case X86ISD::MOVSS:
4760 case X86ISD::MOVSD:
4761 case X86ISD::UNPCKL:
4762 case X86ISD::UNPCKH:
4763 case X86ISD::VBROADCAST:
4764 case X86ISD::VPERMILPI:
4765 case X86ISD::VPERMILPV:
4766 case X86ISD::VPERM2X128:
4767 case X86ISD::SHUF128:
4768 case X86ISD::VPERMIL2:
4769 case X86ISD::VPERMI:
4770 case X86ISD::VPPERM:
4771 case X86ISD::VPERMV:
4772 case X86ISD::VPERMV3:
4773 case X86ISD::VZEXT_MOVL:
4774 return true;
4775 }
4776}
4777
4778static bool isTargetShuffleVariableMask(unsigned Opcode) {
4779 switch (Opcode) {
4780 default: return false;
4781 // Target Shuffles.
4782 case X86ISD::PSHUFB:
4783 case X86ISD::VPERMILPV:
4784 case X86ISD::VPERMIL2:
4785 case X86ISD::VPPERM:
4786 case X86ISD::VPERMV:
4787 case X86ISD::VPERMV3:
4788 return true;
4789 // 'Faux' Target Shuffles.
4790 case ISD::OR:
4791 case ISD::AND:
4792 case X86ISD::ANDNP:
4793 return true;
4794 }
4795}
4796
4797SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
4798 MachineFunction &MF = DAG.getMachineFunction();
4799 const X86RegisterInfo *RegInfo = Subtarget.getRegisterInfo();
4800 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
4801 int ReturnAddrIndex = FuncInfo->getRAIndex();
4802
4803 if (ReturnAddrIndex == 0) {
4804 // Set up a frame object for the return address.
4805 unsigned SlotSize = RegInfo->getSlotSize();
4806 ReturnAddrIndex = MF.getFrameInfo().CreateFixedObject(SlotSize,
4807 -(int64_t)SlotSize,
4808 false);
4809 FuncInfo->setRAIndex(ReturnAddrIndex);
4810 }
4811
4812 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy(DAG.getDataLayout()));
4813}
4814
4815bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
4816 bool hasSymbolicDisplacement) {
4817 // Offset should fit into 32 bit immediate field.
4818 if (!isInt<32>(Offset))
4819 return false;
4820
4821 // If we don't have a symbolic displacement - we don't have any extra
4822 // restrictions.
4823 if (!hasSymbolicDisplacement)
4824 return true;
4825
4826 // FIXME: Some tweaks might be needed for medium code model.
4827 if (M != CodeModel::Small && M != CodeModel::Kernel)
4828 return false;
4829
4830 // For small code model we assume that latest object is 16MB before end of 31
4831 // bits boundary. We may also accept pretty large negative constants knowing
4832 // that all objects are in the positive half of address space.
4833 if (M == CodeModel::Small && Offset < 16*1024*1024)
4834 return true;
4835
4836 // For kernel code model we know that all object resist in the negative half
4837 // of 32bits address space. We may not accept negative offsets, since they may
4838 // be just off and we may accept pretty large positive ones.
4839 if (M == CodeModel::Kernel && Offset >= 0)
4840 return true;
4841
4842 return false;
4843}
4844
4845/// Determines whether the callee is required to pop its own arguments.
4846/// Callee pop is necessary to support tail calls.
4847bool X86::isCalleePop(CallingConv::ID CallingConv,
4848 bool is64Bit, bool IsVarArg, bool GuaranteeTCO) {
4849 // If GuaranteeTCO is true, we force some calls to be callee pop so that we
4850 // can guarantee TCO.
4851 if (!IsVarArg && shouldGuaranteeTCO(CallingConv, GuaranteeTCO))
4852 return true;
4853
4854 switch (CallingConv) {
4855 default:
4856 return false;
4857 case CallingConv::X86_StdCall:
4858 case CallingConv::X86_FastCall:
4859 case CallingConv::X86_ThisCall:
4860 case CallingConv::X86_VectorCall:
4861 return !is64Bit;
4862 }
4863}
4864
4865/// Return true if the condition is an signed comparison operation.
4866static bool isX86CCSigned(unsigned X86CC) {
4867 switch (X86CC) {
4868 default:
4869 llvm_unreachable("Invalid integer condition!")::llvm::llvm_unreachable_internal("Invalid integer condition!"
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 4869)
;
4870 case X86::COND_E:
4871 case X86::COND_NE:
4872 case X86::COND_B:
4873 case X86::COND_A:
4874 case X86::COND_BE:
4875 case X86::COND_AE:
4876 return false;
4877 case X86::COND_G:
4878 case X86::COND_GE:
4879 case X86::COND_L:
4880 case X86::COND_LE:
4881 return true;
4882 }
4883}
4884
4885static X86::CondCode TranslateIntegerX86CC(ISD::CondCode SetCCOpcode) {
4886 switch (SetCCOpcode) {
4887 default: llvm_unreachable("Invalid integer condition!")::llvm::llvm_unreachable_internal("Invalid integer condition!"
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 4887)
;
4888 case ISD::SETEQ: return X86::COND_E;
4889 case ISD::SETGT: return X86::COND_G;
4890 case ISD::SETGE: return X86::COND_GE;
4891 case ISD::SETLT: return X86::COND_L;
4892 case ISD::SETLE: return X86::COND_LE;
4893 case ISD::SETNE: return X86::COND_NE;
4894 case ISD::SETULT: return X86::COND_B;
4895 case ISD::SETUGT: return X86::COND_A;
4896 case ISD::SETULE: return X86::COND_BE;
4897 case ISD::SETUGE: return X86::COND_AE;
4898 }
4899}
4900
4901/// Do a one-to-one translation of a ISD::CondCode to the X86-specific
4902/// condition code, returning the condition code and the LHS/RHS of the
4903/// comparison to make.
4904static X86::CondCode TranslateX86CC(ISD::CondCode SetCCOpcode, const SDLoc &DL,
4905 bool isFP, SDValue &LHS, SDValue &RHS,
4906 SelectionDAG &DAG) {
4907 if (!isFP) {
4908 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
4909 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
4910 // X > -1 -> X == 0, jump !sign.
4911 RHS = DAG.getConstant(0, DL, RHS.getValueType());
4912 return X86::COND_NS;
4913 }
4914 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
4915 // X < 0 -> X == 0, jump on sign.
4916 return X86::COND_S;
4917 }
4918 if (SetCCOpcode == ISD::SETGE && RHSC->isNullValue()) {
4919 // X >= 0 -> X == 0, jump on !sign.
4920 return X86::COND_NS;
4921 }
4922 if (SetCCOpcode == ISD::SETLT && RHSC->isOne()) {
4923 // X < 1 -> X <= 0
4924 RHS = DAG.getConstant(0, DL, RHS.getValueType());
4925 return X86::COND_LE;
4926 }
4927 }
4928
4929 return TranslateIntegerX86CC(SetCCOpcode);
4930 }
4931
4932 // First determine if it is required or is profitable to flip the operands.
4933
4934 // If LHS is a foldable load, but RHS is not, flip the condition.
4935 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
4936 !ISD::isNON_EXTLoad(RHS.getNode())) {
4937 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
4938 std::swap(LHS, RHS);
4939 }
4940
4941 switch (SetCCOpcode) {
4942 default: break;
4943 case ISD::SETOLT:
4944 case ISD::SETOLE:
4945 case ISD::SETUGT:
4946 case ISD::SETUGE:
4947 std::swap(LHS, RHS);
4948 break;
4949 }
4950
4951 // On a floating point condition, the flags are set as follows:
4952 // ZF PF CF op
4953 // 0 | 0 | 0 | X > Y
4954 // 0 | 0 | 1 | X < Y
4955 // 1 | 0 | 0 | X == Y
4956 // 1 | 1 | 1 | unordered
4957 switch (SetCCOpcode) {
4958 default: llvm_unreachable("Condcode should be pre-legalized away")::llvm::llvm_unreachable_internal("Condcode should be pre-legalized away"
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 4958)
;
4959 case ISD::SETUEQ:
4960 case ISD::SETEQ: return X86::COND_E;
4961 case ISD::SETOLT: // flipped
4962 case ISD::SETOGT:
4963 case ISD::SETGT: return X86::COND_A;
4964 case ISD::SETOLE: // flipped
4965 case ISD::SETOGE:
4966 case ISD::SETGE: return X86::COND_AE;
4967 case ISD::SETUGT: // flipped
4968 case ISD::SETULT:
4969 case ISD::SETLT: return X86::COND_B;
4970 case ISD::SETUGE: // flipped
4971 case ISD::SETULE:
4972 case ISD::SETLE: return X86::COND_BE;
4973 case ISD::SETONE:
4974 case ISD::SETNE: return X86::COND_NE;
4975 case ISD::SETUO: return X86::COND_P;
4976 case ISD::SETO: return X86::COND_NP;
4977 case ISD::SETOEQ:
4978 case ISD::SETUNE: return X86::COND_INVALID;
4979 }
4980}
4981
4982/// Is there a floating point cmov for the specific X86 condition code?
4983/// Current x86 isa includes the following FP cmov instructions:
4984/// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
4985static bool hasFPCMov(unsigned X86CC) {
4986 switch (X86CC) {
4987 default:
4988 return false;
4989 case X86::COND_B:
4990 case X86::COND_BE:
4991 case X86::COND_E:
4992 case X86::COND_P:
4993 case X86::COND_A:
4994 case X86::COND_AE:
4995 case X86::COND_NE:
4996 case X86::COND_NP:
4997 return true;
4998 }
4999}
5000
5001
5002bool X86TargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
5003 const CallInst &I,
5004 MachineFunction &MF,
5005 unsigned Intrinsic) const {
5006
5007 const IntrinsicData* IntrData = getIntrinsicWithChain(Intrinsic);
5008 if (!IntrData)
5009 return false;
5010
5011 Info.flags = MachineMemOperand::MONone;
5012 Info.offset = 0;
5013
5014 switch (IntrData->Type) {
5015 case TRUNCATE_TO_MEM_VI8:
5016 case TRUNCATE_TO_MEM_VI16:
5017 case TRUNCATE_TO_MEM_VI32: {
5018 Info.opc = ISD::INTRINSIC_VOID;
5019 Info.ptrVal = I.getArgOperand(0);
5020 MVT VT = MVT::getVT(I.getArgOperand(1)->getType());
5021 MVT ScalarVT = MVT::INVALID_SIMPLE_VALUE_TYPE;
5022 if (IntrData->Type == TRUNCATE_TO_MEM_VI8)
5023 ScalarVT = MVT::i8;
5024 else if (IntrData->Type == TRUNCATE_TO_MEM_VI16)
5025 ScalarVT = MVT::i16;
5026 else if (IntrData->Type == TRUNCATE_TO_MEM_VI32)
5027 ScalarVT = MVT::i32;
5028
5029 Info.memVT = MVT::getVectorVT(ScalarVT, VT.getVectorNumElements());
5030 Info.align = Align(1);
5031 Info.flags |= MachineMemOperand::MOStore;
5032 break;
5033 }
5034 case GATHER:
5035 case GATHER_AVX2: {
5036 Info.opc = ISD::INTRINSIC_W_CHAIN;
5037 Info.ptrVal = nullptr;
5038 MVT DataVT = MVT::getVT(I.getType());
5039 MVT IndexVT = MVT::getVT(I.getArgOperand(2)->getType());
5040 unsigned NumElts = std::min(DataVT.getVectorNumElements(),
5041 IndexVT.getVectorNumElements());
5042 Info.memVT = MVT::getVectorVT(DataVT.getVectorElementType(), NumElts);
5043 Info.align = Align(1);
5044 Info.flags |= MachineMemOperand::MOLoad;
5045 break;
5046 }
5047 case SCATTER: {
5048 Info.opc = ISD::INTRINSIC_VOID;
5049 Info.ptrVal = nullptr;
5050 MVT DataVT = MVT::getVT(I.getArgOperand(3)->getType());
5051 MVT IndexVT = MVT::getVT(I.getArgOperand(2)->getType());
5052 unsigned NumElts = std::min(DataVT.getVectorNumElements(),
5053 IndexVT.getVectorNumElements());
5054 Info.memVT = MVT::getVectorVT(DataVT.getVectorElementType(), NumElts);
5055 Info.align = Align(1);
5056 Info.flags |= MachineMemOperand::MOStore;
5057 break;
5058 }
5059 default:
5060 return false;
5061 }
5062
5063 return true;
5064}
5065
5066/// Returns true if the target can instruction select the
5067/// specified FP immediate natively. If false, the legalizer will
5068/// materialize the FP immediate as a load from a constant pool.
5069bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT,
5070 bool ForCodeSize) const {
5071 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
5072 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
5073 return true;
5074 }
5075 return false;
5076}
5077
5078bool X86TargetLowering::shouldReduceLoadWidth(SDNode *Load,
5079 ISD::LoadExtType ExtTy,
5080 EVT NewVT) const {
5081 assert(cast<LoadSDNode>(Load)->isSimple() && "illegal to narrow")((cast<LoadSDNode>(Load)->isSimple() && "illegal to narrow"
) ? static_cast<void> (0) : __assert_fail ("cast<LoadSDNode>(Load)->isSimple() && \"illegal to narrow\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 5081, __PRETTY_FUNCTION__))
;
5082
5083 // "ELF Handling for Thread-Local Storage" specifies that R_X86_64_GOTTPOFF
5084 // relocation target a movq or addq instruction: don't let the load shrink.
5085 SDValue BasePtr = cast<LoadSDNode>(Load)->getBasePtr();
5086 if (BasePtr.getOpcode() == X86ISD::WrapperRIP)
5087 if (const auto *GA = dyn_cast<GlobalAddressSDNode>(BasePtr.getOperand(0)))
5088 return GA->getTargetFlags() != X86II::MO_GOTTPOFF;
5089
5090 // If this is an (1) AVX vector load with (2) multiple uses and (3) all of
5091 // those uses are extracted directly into a store, then the extract + store
5092 // can be store-folded. Therefore, it's probably not worth splitting the load.
5093 EVT VT = Load->getValueType(0);
5094 if ((VT.is256BitVector() || VT.is512BitVector()) && !Load->hasOneUse()) {
5095 for (auto UI = Load->use_begin(), UE = Load->use_end(); UI != UE; ++UI) {
5096 // Skip uses of the chain value. Result 0 of the node is the load value.
5097 if (UI.getUse().getResNo() != 0)
5098 continue;
5099
5100 // If this use is not an extract + store, it's probably worth splitting.
5101 if (UI->getOpcode() != ISD::EXTRACT_SUBVECTOR || !UI->hasOneUse() ||
5102 UI->use_begin()->getOpcode() != ISD::STORE)
5103 return true;
5104 }
5105 // All non-chain uses are extract + store.
5106 return false;
5107 }
5108
5109 return true;
5110}
5111
5112/// Returns true if it is beneficial to convert a load of a constant
5113/// to just the constant itself.
5114bool X86TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
5115 Type *Ty) const {
5116 assert(Ty->isIntegerTy())((Ty->isIntegerTy()) ? static_cast<void> (0) : __assert_fail
("Ty->isIntegerTy()", "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 5116, __PRETTY_FUNCTION__))
;
5117
5118 unsigned BitSize = Ty->getPrimitiveSizeInBits();
5119 if (BitSize == 0 || BitSize > 64)
5120 return false;
5121 return true;
5122}
5123
5124bool X86TargetLowering::reduceSelectOfFPConstantLoads(EVT CmpOpVT) const {
5125 // If we are using XMM registers in the ABI and the condition of the select is
5126 // a floating-point compare and we have blendv or conditional move, then it is
5127 // cheaper to select instead of doing a cross-register move and creating a
5128 // load that depends on the compare result.
5129 bool IsFPSetCC = CmpOpVT.isFloatingPoint() && CmpOpVT != MVT::f128;
5130 return !IsFPSetCC || !Subtarget.isTarget64BitLP64() || !Subtarget.hasAVX();
5131}
5132
5133bool X86TargetLowering::convertSelectOfConstantsToMath(EVT VT) const {
5134 // TODO: It might be a win to ease or lift this restriction, but the generic
5135 // folds in DAGCombiner conflict with vector folds for an AVX512 target.
5136 if (VT.isVector() && Subtarget.hasAVX512())
5137 return false;
5138
5139 return true;
5140}
5141
5142bool X86TargetLowering::decomposeMulByConstant(LLVMContext &Context, EVT VT,
5143 SDValue C) const {
5144 // TODO: We handle scalars using custom code, but generic combining could make
5145 // that unnecessary.
5146 APInt MulC;
5147 if (!ISD::isConstantSplatVector(C.getNode(), MulC))
5148 return false;
5149
5150 // Find the type this will be legalized too. Otherwise we might prematurely
5151 // convert this to shl+add/sub and then still have to type legalize those ops.
5152 // Another choice would be to defer the decision for illegal types until
5153 // after type legalization. But constant splat vectors of i64 can't make it
5154 // through type legalization on 32-bit targets so we would need to special
5155 // case vXi64.
5156 while (getTypeAction(Context, VT) != TypeLegal)
5157 VT = getTypeToTransformTo(Context, VT);
5158
5159 // If vector multiply is legal, assume that's faster than shl + add/sub.
5160 // TODO: Multiply is a complex op with higher latency and lower throughput in
5161 // most implementations, so this check could be loosened based on type
5162 // and/or a CPU attribute.
5163 if (isOperationLegal(ISD::MUL, VT))
5164 return false;
5165
5166 // shl+add, shl+sub, shl+add+neg
5167 return (MulC + 1).isPowerOf2() || (MulC - 1).isPowerOf2() ||
5168 (1 - MulC).isPowerOf2() || (-(MulC + 1)).isPowerOf2();
5169}
5170
5171bool X86TargetLowering::isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
5172 unsigned Index) const {
5173 if (!isOperationLegalOrCustom(ISD::EXTRACT_SUBVECTOR, ResVT))
5174 return false;
5175
5176 // Mask vectors support all subregister combinations and operations that
5177 // extract half of vector.
5178 if (ResVT.getVectorElementType() == MVT::i1)
5179 return Index == 0 || ((ResVT.getSizeInBits() == SrcVT.getSizeInBits()*2) &&
5180 (Index == ResVT.getVectorNumElements()));
5181
5182 return (Index % ResVT.getVectorNumElements()) == 0;
5183}
5184
5185bool X86TargetLowering::shouldScalarizeBinop(SDValue VecOp) const {
5186 unsigned Opc = VecOp.getOpcode();
5187
5188 // Assume target opcodes can't be scalarized.
5189 // TODO - do we have any exceptions?
5190 if (Opc >= ISD::BUILTIN_OP_END)
5191 return false;
5192
5193 // If the vector op is not supported, try to convert to scalar.
5194 EVT VecVT = VecOp.getValueType();
5195 if (!isOperationLegalOrCustomOrPromote(Opc, VecVT))
5196 return true;
5197
5198 // If the vector op is supported, but the scalar op is not, the transform may
5199 // not be worthwhile.
5200 EVT ScalarVT = VecVT.getScalarType();
5201 return isOperationLegalOrCustomOrPromote(Opc, ScalarVT);
5202}
5203
5204bool X86TargetLowering::shouldFormOverflowOp(unsigned Opcode, EVT VT,
5205 bool) const {
5206 // TODO: Allow vectors?
5207 if (VT.isVector())
5208 return false;
5209 return VT.isSimple() || !isOperationExpand(Opcode, VT);
5210}
5211
5212bool X86TargetLowering::isCheapToSpeculateCttz() const {
5213 // Speculate cttz only if we can directly use TZCNT.
5214 return Subtarget.hasBMI();
5215}
5216
5217bool X86TargetLowering::isCheapToSpeculateCtlz() const {
5218 // Speculate ctlz only if we can directly use LZCNT.
5219 return Subtarget.hasLZCNT();
5220}
5221
5222bool X86TargetLowering::isLoadBitCastBeneficial(EVT LoadVT, EVT BitcastVT,
5223 const SelectionDAG &DAG,
5224 const MachineMemOperand &MMO) const {
5225 if (!Subtarget.hasAVX512() && !LoadVT.isVector() && BitcastVT.isVector() &&
5226 BitcastVT.getVectorElementType() == MVT::i1)
5227 return false;
5228
5229 if (!Subtarget.hasDQI() && BitcastVT == MVT::v8i1 && LoadVT == MVT::i8)
5230 return false;
5231
5232 // If both types are legal vectors, it's always ok to convert them.
5233 if (LoadVT.isVector() && BitcastVT.isVector() &&
5234 isTypeLegal(LoadVT) && isTypeLegal(BitcastVT))
5235 return true;
5236
5237 return TargetLowering::isLoadBitCastBeneficial(LoadVT, BitcastVT, DAG, MMO);
5238}
5239
5240bool X86TargetLowering::canMergeStoresTo(unsigned AddressSpace, EVT MemVT,
5241 const SelectionDAG &DAG) const {
5242 // Do not merge to float value size (128 bytes) if no implicit
5243 // float attribute is set.
5244 bool NoFloat = DAG.getMachineFunction().getFunction().hasFnAttribute(
5245 Attribute::NoImplicitFloat);
5246
5247 if (NoFloat) {
5248 unsigned MaxIntSize = Subtarget.is64Bit() ? 64 : 32;
5249 return (MemVT.getSizeInBits() <= MaxIntSize);
5250 }
5251 // Make sure we don't merge greater than our preferred vector
5252 // width.
5253 if (MemVT.getSizeInBits() > Subtarget.getPreferVectorWidth())
5254 return false;
5255 return true;
5256}
5257
5258bool X86TargetLowering::isCtlzFast() const {
5259 return Subtarget.hasFastLZCNT();
5260}
5261
5262bool X86TargetLowering::isMaskAndCmp0FoldingBeneficial(
5263 const Instruction &AndI) const {
5264 return true;
5265}
5266
5267bool X86TargetLowering::hasAndNotCompare(SDValue Y) const {
5268 EVT VT = Y.getValueType();
5269
5270 if (VT.isVector())
5271 return false;
5272
5273 if (!Subtarget.hasBMI())
5274 return false;
5275
5276 // There are only 32-bit and 64-bit forms for 'andn'.
5277 if (VT != MVT::i32 && VT != MVT::i64)
5278 return false;
5279
5280 return !isa<ConstantSDNode>(Y);
5281}
5282
5283bool X86TargetLowering::hasAndNot(SDValue Y) const {
5284 EVT VT = Y.getValueType();
5285
5286 if (!VT.isVector())
5287 return hasAndNotCompare(Y);
5288
5289 // Vector.
5290
5291 if (!Subtarget.hasSSE1() || VT.getSizeInBits() < 128)
5292 return false;
5293
5294 if (VT == MVT::v4i32)
5295 return true;
5296
5297 return Subtarget.hasSSE2();
5298}
5299
5300bool X86TargetLowering::hasBitTest(SDValue X, SDValue Y) const {
5301 return X.getValueType().isScalarInteger(); // 'bt'
5302}
5303
5304bool X86TargetLowering::
5305 shouldProduceAndByConstByHoistingConstFromShiftsLHSOfAnd(
5306 SDValue X, ConstantSDNode *XC, ConstantSDNode *CC, SDValue Y,
5307 unsigned OldShiftOpcode, unsigned NewShiftOpcode,
5308 SelectionDAG &DAG) const {
5309 // Does baseline recommend not to perform the fold by default?
5310 if (!TargetLowering::shouldProduceAndByConstByHoistingConstFromShiftsLHSOfAnd(
5311 X, XC, CC, Y, OldShiftOpcode, NewShiftOpcode, DAG))
5312 return false;
5313 // For scalars this transform is always beneficial.
5314 if (X.getValueType().isScalarInteger())
5315 return true;
5316 // If all the shift amounts are identical, then transform is beneficial even
5317 // with rudimentary SSE2 shifts.
5318 if (DAG.isSplatValue(Y, /*AllowUndefs=*/true))
5319 return true;
5320 // If we have AVX2 with it's powerful shift operations, then it's also good.
5321 if (Subtarget.hasAVX2())
5322 return true;
5323 // Pre-AVX2 vector codegen for this pattern is best for variant with 'shl'.
5324 return NewShiftOpcode == ISD::SHL;
5325}
5326
5327bool X86TargetLowering::shouldFoldConstantShiftPairToMask(
5328 const SDNode *N, CombineLevel Level) const {
5329 assert(((N->getOpcode() == ISD::SHL &&((((N->getOpcode() == ISD::SHL && N->getOperand
(0).getOpcode() == ISD::SRL) || (N->getOpcode() == ISD::SRL
&& N->getOperand(0).getOpcode() == ISD::SHL)) &&
"Expected shift-shift mask") ? static_cast<void> (0) :
__assert_fail ("((N->getOpcode() == ISD::SHL && N->getOperand(0).getOpcode() == ISD::SRL) || (N->getOpcode() == ISD::SRL && N->getOperand(0).getOpcode() == ISD::SHL)) && \"Expected shift-shift mask\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 5333, __PRETTY_FUNCTION__))
5330 N->getOperand(0).getOpcode() == ISD::SRL) ||((((N->getOpcode() == ISD::SHL && N->getOperand
(0).getOpcode() == ISD::SRL) || (N->getOpcode() == ISD::SRL
&& N->getOperand(0).getOpcode() == ISD::SHL)) &&
"Expected shift-shift mask") ? static_cast<void> (0) :
__assert_fail ("((N->getOpcode() == ISD::SHL && N->getOperand(0).getOpcode() == ISD::SRL) || (N->getOpcode() == ISD::SRL && N->getOperand(0).getOpcode() == ISD::SHL)) && \"Expected shift-shift mask\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 5333, __PRETTY_FUNCTION__))
5331 (N->getOpcode() == ISD::SRL &&((((N->getOpcode() == ISD::SHL && N->getOperand
(0).getOpcode() == ISD::SRL) || (N->getOpcode() == ISD::SRL
&& N->getOperand(0).getOpcode() == ISD::SHL)) &&
"Expected shift-shift mask") ? static_cast<void> (0) :
__assert_fail ("((N->getOpcode() == ISD::SHL && N->getOperand(0).getOpcode() == ISD::SRL) || (N->getOpcode() == ISD::SRL && N->getOperand(0).getOpcode() == ISD::SHL)) && \"Expected shift-shift mask\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 5333, __PRETTY_FUNCTION__))
5332 N->getOperand(0).getOpcode() == ISD::SHL)) &&((((N->getOpcode() == ISD::SHL && N->getOperand
(0).getOpcode() == ISD::SRL) || (N->getOpcode() == ISD::SRL
&& N->getOperand(0).getOpcode() == ISD::SHL)) &&
"Expected shift-shift mask") ? static_cast<void> (0) :
__assert_fail ("((N->getOpcode() == ISD::SHL && N->getOperand(0).getOpcode() == ISD::SRL) || (N->getOpcode() == ISD::SRL && N->getOperand(0).getOpcode() == ISD::SHL)) && \"Expected shift-shift mask\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 5333, __PRETTY_FUNCTION__))
5333 "Expected shift-shift mask")((((N->getOpcode() == ISD::SHL && N->getOperand
(0).getOpcode() == ISD::SRL) || (N->getOpcode() == ISD::SRL
&& N->getOperand(0).getOpcode() == ISD::SHL)) &&
"Expected shift-shift mask") ? static_cast<void> (0) :
__assert_fail ("((N->getOpcode() == ISD::SHL && N->getOperand(0).getOpcode() == ISD::SRL) || (N->getOpcode() == ISD::SRL && N->getOperand(0).getOpcode() == ISD::SHL)) && \"Expected shift-shift mask\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 5333, __PRETTY_FUNCTION__))
;
5334 EVT VT = N->getValueType(0);
5335 if ((Subtarget.hasFastVectorShiftMasks() && VT.isVector()) ||
5336 (Subtarget.hasFastScalarShiftMasks() && !VT.isVector())) {
5337 // Only fold if the shift values are equal - so it folds to AND.
5338 // TODO - we should fold if either is a non-uniform vector but we don't do
5339 // the fold for non-splats yet.
5340 return N->getOperand(1) == N->getOperand(0).getOperand(1);
5341 }
5342 return TargetLoweringBase::shouldFoldConstantShiftPairToMask(N, Level);
5343}
5344
5345bool X86TargetLowering::shouldFoldMaskToVariableShiftPair(SDValue Y) const {
5346 EVT VT = Y.getValueType();
5347
5348 // For vectors, we don't have a preference, but we probably want a mask.
5349 if (VT.isVector())
5350 return false;
5351
5352 // 64-bit shifts on 32-bit targets produce really bad bloated code.
5353 if (VT == MVT::i64 && !Subtarget.is64Bit())
5354 return false;
5355
5356 return true;
5357}
5358
5359bool X86TargetLowering::shouldExpandShift(SelectionDAG &DAG,
5360 SDNode *N) const {
5361 if (DAG.getMachineFunction().getFunction().hasMinSize() &&
5362 !Subtarget.isOSWindows())
5363 return false;
5364 return true;
5365}
5366
5367bool X86TargetLowering::shouldSplatInsEltVarIndex(EVT VT) const {
5368 // Any legal vector type can be splatted more efficiently than
5369 // loading/spilling from memory.
5370 return isTypeLegal(VT);
5371}
5372
5373MVT X86TargetLowering::hasFastEqualityCompare(unsigned NumBits) const {
5374 MVT VT = MVT::getIntegerVT(NumBits);
5375 if (isTypeLegal(VT))
5376 return VT;
5377
5378 // PMOVMSKB can handle this.
5379 if (NumBits == 128 && isTypeLegal(MVT::v16i8))
5380 return MVT::v16i8;
5381
5382 // VPMOVMSKB can handle this.
5383 if (NumBits == 256 && isTypeLegal(MVT::v32i8))
5384 return MVT::v32i8;
5385
5386 // TODO: Allow 64-bit type for 32-bit target.
5387 // TODO: 512-bit types should be allowed, but make sure that those
5388 // cases are handled in combineVectorSizedSetCCEquality().
5389
5390 return MVT::INVALID_SIMPLE_VALUE_TYPE;
5391}
5392
5393/// Val is the undef sentinel value or equal to the specified value.
5394static bool isUndefOrEqual(int Val, int CmpVal) {
5395 return ((Val == SM_SentinelUndef) || (Val == CmpVal));
5396}
5397
5398/// Val is either the undef or zero sentinel value.
5399static bool isUndefOrZero(int Val) {
5400 return ((Val == SM_SentinelUndef) || (Val == SM_SentinelZero));
5401}
5402
5403/// Return true if every element in Mask, beginning from position Pos and ending
5404/// in Pos+Size is the undef sentinel value.
5405static bool isUndefInRange(ArrayRef<int> Mask, unsigned Pos, unsigned Size) {
5406 return llvm::all_of(Mask.slice(Pos, Size),
5407 [](int M) { return M == SM_SentinelUndef; });
5408}
5409
5410/// Return true if the mask creates a vector whose lower half is undefined.
5411static bool isUndefLowerHalf(ArrayRef<int> Mask) {
5412 unsigned NumElts = Mask.size();
5413 return isUndefInRange(Mask, 0, NumElts / 2);
5414}
5415
5416/// Return true if the mask creates a vector whose upper half is undefined.
5417static bool isUndefUpperHalf(ArrayRef<int> Mask) {
5418 unsigned NumElts = Mask.size();
5419 return isUndefInRange(Mask, NumElts / 2, NumElts / 2);
5420}
5421
5422/// Return true if Val falls within the specified range (L, H].
5423static bool isInRange(int Val, int Low, int Hi) {
5424 return (Val >= Low && Val < Hi);
5425}
5426
5427/// Return true if the value of any element in Mask falls within the specified
5428/// range (L, H].
5429static bool isAnyInRange(ArrayRef<int> Mask, int Low, int Hi) {
5430 return llvm::any_of(Mask, [Low, Hi](int M) { return isInRange(M, Low, Hi); });
5431}
5432
5433/// Return true if Val is undef or if its value falls within the
5434/// specified range (L, H].
5435static bool isUndefOrInRange(int Val, int Low, int Hi) {
5436 return (Val == SM_SentinelUndef) || isInRange(Val, Low, Hi);
5437}
5438
5439/// Return true if every element in Mask is undef or if its value
5440/// falls within the specified range (L, H].
5441static bool isUndefOrInRange(ArrayRef<int> Mask, int Low, int Hi) {
5442 return llvm::all_of(
5443 Mask, [Low, Hi](int M) { return isUndefOrInRange(M, Low, Hi); });
5444}
5445
5446/// Return true if Val is undef, zero or if its value falls within the
5447/// specified range (L, H].
5448static bool isUndefOrZeroOrInRange(int Val, int Low, int Hi) {
5449 return isUndefOrZero(Val) || isInRange(Val, Low, Hi);
5450}
5451
5452/// Return true if every element in Mask is undef, zero or if its value
5453/// falls within the specified range (L, H].
5454static bool isUndefOrZeroOrInRange(ArrayRef<int> Mask, int Low, int Hi) {
5455 return llvm::all_of(
5456 Mask, [Low, Hi](int M) { return isUndefOrZeroOrInRange(M, Low, Hi); });
5457}
5458
5459/// Return true if every element in Mask, beginning
5460/// from position Pos and ending in Pos + Size, falls within the specified
5461/// sequence (Low, Low + Step, ..., Low + (Size - 1) * Step) or is undef.
5462static bool isSequentialOrUndefInRange(ArrayRef<int> Mask, unsigned Pos,
5463 unsigned Size, int Low, int Step = 1) {
5464 for (unsigned i = Pos, e = Pos + Size; i != e; ++i, Low += Step)
5465 if (!isUndefOrEqual(Mask[i], Low))
5466 return false;
5467 return true;
5468}
5469
5470/// Return true if every element in Mask, beginning
5471/// from position Pos and ending in Pos+Size, falls within the specified
5472/// sequential range (Low, Low+Size], or is undef or is zero.
5473static bool isSequentialOrUndefOrZeroInRange(ArrayRef<int> Mask, unsigned Pos,
5474 unsigned Size, int Low,
5475 int Step = 1) {
5476 for (unsigned i = Pos, e = Pos + Size; i != e; ++i, Low += Step)
5477 if (!isUndefOrZero(Mask[i]) && Mask[i] != Low)
5478 return false;
5479 return true;
5480}
5481
5482/// Return true if every element in Mask, beginning
5483/// from position Pos and ending in Pos+Size is undef or is zero.
5484static bool isUndefOrZeroInRange(ArrayRef<int> Mask, unsigned Pos,
5485 unsigned Size) {
5486 return llvm::all_of(Mask.slice(Pos, Size),
5487 [](int M) { return isUndefOrZero(M); });
5488}
5489
5490/// Helper function to test whether a shuffle mask could be
5491/// simplified by widening the elements being shuffled.
5492///
5493/// Appends the mask for wider elements in WidenedMask if valid. Otherwise
5494/// leaves it in an unspecified state.
5495///
5496/// NOTE: This must handle normal vector shuffle masks and *target* vector
5497/// shuffle masks. The latter have the special property of a '-2' representing
5498/// a zero-ed lane of a vector.
5499static bool canWidenShuffleElements(ArrayRef<int> Mask,
5500 SmallVectorImpl<int> &WidenedMask) {
5501 WidenedMask.assign(Mask.size() / 2, 0);
5502 for (int i = 0, Size = Mask.size(); i < Size; i += 2) {
5503 int M0 = Mask[i];
5504 int M1 = Mask[i + 1];
5505
5506 // If both elements are undef, its trivial.
5507 if (M0 == SM_SentinelUndef && M1 == SM_SentinelUndef) {
5508 WidenedMask[i / 2] = SM_SentinelUndef;
5509 continue;
5510 }
5511
5512 // Check for an undef mask and a mask value properly aligned to fit with
5513 // a pair of values. If we find such a case, use the non-undef mask's value.
5514 if (M0 == SM_SentinelUndef && M1 >= 0 && (M1 % 2) == 1) {
5515 WidenedMask[i / 2] = M1 / 2;
5516 continue;
5517 }
5518 if (M1 == SM_SentinelUndef && M0 >= 0 && (M0 % 2) == 0) {
5519 WidenedMask[i / 2] = M0 / 2;
5520 continue;
5521 }
5522
5523 // When zeroing, we need to spread the zeroing across both lanes to widen.
5524 if (M0 == SM_SentinelZero || M1 == SM_SentinelZero) {
5525 if ((M0 == SM_SentinelZero || M0 == SM_SentinelUndef) &&
5526 (M1 == SM_SentinelZero || M1 == SM_SentinelUndef)) {
5527 WidenedMask[i / 2] = SM_SentinelZero;
5528 continue;
5529 }
5530 return false;
5531 }
5532
5533 // Finally check if the two mask values are adjacent and aligned with
5534 // a pair.
5535 if (M0 != SM_SentinelUndef && (M0 % 2) == 0 && (M0 + 1) == M1) {
5536 WidenedMask[i / 2] = M0 / 2;
5537 continue;
5538 }
5539
5540 // Otherwise we can't safely widen the elements used in this shuffle.
5541 return false;
5542 }
5543 assert(WidenedMask.size() == Mask.size() / 2 &&((WidenedMask.size() == Mask.size() / 2 && "Incorrect size of mask after widening the elements!"
) ? static_cast<void> (0) : __assert_fail ("WidenedMask.size() == Mask.size() / 2 && \"Incorrect size of mask after widening the elements!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 5544, __PRETTY_FUNCTION__))
5544 "Incorrect size of mask after widening the elements!")((WidenedMask.size() == Mask.size() / 2 && "Incorrect size of mask after widening the elements!"
) ? static_cast<void> (0) : __assert_fail ("WidenedMask.size() == Mask.size() / 2 && \"Incorrect size of mask after widening the elements!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 5544, __PRETTY_FUNCTION__))
;
5545
5546 return true;
5547}
5548
5549static bool canWidenShuffleElements(ArrayRef<int> Mask,
5550 const APInt &Zeroable,
5551 bool V2IsZero,
5552 SmallVectorImpl<int> &WidenedMask) {
5553 // Create an alternative mask with info about zeroable elements.
5554 // Here we do not set undef elements as zeroable.
5555 SmallVector<int, 64> ZeroableMask(Mask.begin(), Mask.end());
5556 if (V2IsZero) {
5557 assert(!Zeroable.isNullValue() && "V2's non-undef elements are used?!")((!Zeroable.isNullValue() && "V2's non-undef elements are used?!"
) ? static_cast<void> (0) : __assert_fail ("!Zeroable.isNullValue() && \"V2's non-undef elements are used?!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 5557, __PRETTY_FUNCTION__))
;
5558 for (int i = 0, Size = Mask.size(); i != Size; ++i)
5559 if (Mask[i] != SM_SentinelUndef && Zeroable[i])
5560 ZeroableMask[i] = SM_SentinelZero;
5561 }
5562 return canWidenShuffleElements(ZeroableMask, WidenedMask);
5563}
5564
5565static bool canWidenShuffleElements(ArrayRef<int> Mask) {
5566 SmallVector<int, 32> WidenedMask;
5567 return canWidenShuffleElements(Mask, WidenedMask);
5568}
5569
5570/// Returns true if Elt is a constant zero or a floating point constant +0.0.
5571bool X86::isZeroNode(SDValue Elt) {
5572 return isNullConstant(Elt) || isNullFPConstant(Elt);
5573}
5574
5575// Build a vector of constants.
5576// Use an UNDEF node if MaskElt == -1.
5577// Split 64-bit constants in the 32-bit mode.
5578static SDValue getConstVector(ArrayRef<int> Values, MVT VT, SelectionDAG &DAG,
5579 const SDLoc &dl, bool IsMask = false) {
5580
5581 SmallVector<SDValue, 32> Ops;
5582 bool Split = false;
5583
5584 MVT ConstVecVT = VT;
5585 unsigned NumElts = VT.getVectorNumElements();
5586 bool In64BitMode = DAG.getTargetLoweringInfo().isTypeLegal(MVT::i64);
5587 if (!In64BitMode && VT.getVectorElementType() == MVT::i64) {
5588 ConstVecVT = MVT::getVectorVT(MVT::i32, NumElts * 2);
5589 Split = true;
5590 }
5591
5592 MVT EltVT = ConstVecVT.getVectorElementType();
5593 for (unsigned i = 0; i < NumElts; ++i) {
5594 bool IsUndef = Values[i] < 0 && IsMask;
5595 SDValue OpNode = IsUndef ? DAG.getUNDEF(EltVT) :
5596 DAG.getConstant(Values[i], dl, EltVT);
5597 Ops.push_back(OpNode);
5598 if (Split)
5599 Ops.push_back(IsUndef ? DAG.getUNDEF(EltVT) :
5600 DAG.getConstant(0, dl, EltVT));
5601 }
5602 SDValue ConstsNode = DAG.getBuildVector(ConstVecVT, dl, Ops);
5603 if (Split)
5604 ConstsNode = DAG.getBitcast(VT, ConstsNode);
5605 return ConstsNode;
5606}
5607
5608static SDValue getConstVector(ArrayRef<APInt> Bits, APInt &Undefs,
5609 MVT VT, SelectionDAG &DAG, const SDLoc &dl) {
5610 assert(Bits.size() == Undefs.getBitWidth() &&((Bits.size() == Undefs.getBitWidth() && "Unequal constant and undef arrays"
) ? static_cast<void> (0) : __assert_fail ("Bits.size() == Undefs.getBitWidth() && \"Unequal constant and undef arrays\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 5611, __PRETTY_FUNCTION__))
5611 "Unequal constant and undef arrays")((Bits.size() == Undefs.getBitWidth() && "Unequal constant and undef arrays"
) ? static_cast<void> (0) : __assert_fail ("Bits.size() == Undefs.getBitWidth() && \"Unequal constant and undef arrays\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 5611, __PRETTY_FUNCTION__))
;
5612 SmallVector<SDValue, 32> Ops;
5613 bool Split = false;
5614
5615 MVT ConstVecVT = VT;
5616 unsigned NumElts = VT.getVectorNumElements();
5617 bool In64BitMode = DAG.getTargetLoweringInfo().isTypeLegal(MVT::i64);
5618 if (!In64BitMode && VT.getVectorElementType() == MVT::i64) {
5619 ConstVecVT = MVT::getVectorVT(MVT::i32, NumElts * 2);
5620 Split = true;
5621 }
5622
5623 MVT EltVT = ConstVecVT.getVectorElementType();
5624 for (unsigned i = 0, e = Bits.size(); i != e; ++i) {
5625 if (Undefs[i]) {
5626 Ops.append(Split ? 2 : 1, DAG.getUNDEF(EltVT));
5627 continue;
5628 }
5629 const APInt &V = Bits[i];
5630 assert(V.getBitWidth() == VT.getScalarSizeInBits() && "Unexpected sizes")((V.getBitWidth() == VT.getScalarSizeInBits() && "Unexpected sizes"
) ? static_cast<void> (0) : __assert_fail ("V.getBitWidth() == VT.getScalarSizeInBits() && \"Unexpected sizes\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 5630, __PRETTY_FUNCTION__))
;
5631 if (Split) {
5632 Ops.push_back(DAG.getConstant(V.trunc(32), dl, EltVT));
5633 Ops.push_back(DAG.getConstant(V.lshr(32).trunc(32), dl, EltVT));
5634 } else if (EltVT == MVT::f32) {
5635 APFloat FV(APFloat::IEEEsingle(), V);
5636 Ops.push_back(DAG.getConstantFP(FV, dl, EltVT));
5637 } else if (EltVT == MVT::f64) {
5638 APFloat FV(APFloat::IEEEdouble(), V);
5639 Ops.push_back(DAG.getConstantFP(FV, dl, EltVT));
5640 } else {
5641 Ops.push_back(DAG.getConstant(V, dl, EltVT));
5642 }
5643 }
5644
5645 SDValue ConstsNode = DAG.getBuildVector(ConstVecVT, dl, Ops);
5646 return DAG.getBitcast(VT, ConstsNode);
5647}
5648
5649/// Returns a vector of specified type with all zero elements.
5650static SDValue getZeroVector(MVT VT, const X86Subtarget &Subtarget,
5651 SelectionDAG &DAG, const SDLoc &dl) {
5652 assert((VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector() ||(((VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector
() || VT.getVectorElementType() == MVT::i1) && "Unexpected vector type"
) ? static_cast<void> (0) : __assert_fail ("(VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector() || VT.getVectorElementType() == MVT::i1) && \"Unexpected vector type\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 5654, __PRETTY_FUNCTION__))
5653 VT.getVectorElementType() == MVT::i1) &&(((VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector
() || VT.getVectorElementType() == MVT::i1) && "Unexpected vector type"
) ? static_cast<void> (0) : __assert_fail ("(VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector() || VT.getVectorElementType() == MVT::i1) && \"Unexpected vector type\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 5654, __PRETTY_FUNCTION__))
5654 "Unexpected vector type")(((VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector
() || VT.getVectorElementType() == MVT::i1) && "Unexpected vector type"
) ? static_cast<void> (0) : __assert_fail ("(VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector() || VT.getVectorElementType() == MVT::i1) && \"Unexpected vector type\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 5654, __PRETTY_FUNCTION__))
;
5655
5656 // Try to build SSE/AVX zero vectors as <N x i32> bitcasted to their dest
5657 // type. This ensures they get CSE'd. But if the integer type is not
5658 // available, use a floating-point +0.0 instead.
5659 SDValue Vec;
5660 if (!Subtarget.hasSSE2() && VT.is128BitVector()) {
5661 Vec = DAG.getConstantFP(+0.0, dl, MVT::v4f32);
5662 } else if (VT.isFloatingPoint()) {
5663 Vec = DAG.getConstantFP(+0.0, dl, VT);
5664 } else if (VT.getVectorElementType() == MVT::i1) {
5665 assert((Subtarget.hasBWI() || VT.getVectorNumElements() <= 16) &&(((Subtarget.hasBWI() || VT.getVectorNumElements() <= 16) &&
"Unexpected vector type") ? static_cast<void> (0) : __assert_fail
("(Subtarget.hasBWI() || VT.getVectorNumElements() <= 16) && \"Unexpected vector type\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 5666, __PRETTY_FUNCTION__))
5666 "Unexpected vector type")(((Subtarget.hasBWI() || VT.getVectorNumElements() <= 16) &&
"Unexpected vector type") ? static_cast<void> (0) : __assert_fail
("(Subtarget.hasBWI() || VT.getVectorNumElements() <= 16) && \"Unexpected vector type\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 5666, __PRETTY_FUNCTION__))
;
5667 Vec = DAG.getConstant(0, dl, VT);
5668 } else {
5669 unsigned Num32BitElts = VT.getSizeInBits() / 32;
5670 Vec = DAG.getConstant(0, dl, MVT::getVectorVT(MVT::i32, Num32BitElts));
5671 }
5672 return DAG.getBitcast(VT, Vec);
5673}
5674
5675static SDValue extractSubVector(SDValue Vec, unsigned IdxVal, SelectionDAG &DAG,
5676 const SDLoc &dl, unsigned vectorWidth) {
5677 EVT VT = Vec.getValueType();
5678 EVT ElVT = VT.getVectorElementType();
5679 unsigned Factor = VT.getSizeInBits()/vectorWidth;
5680 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
5681 VT.getVectorNumElements()/Factor);
5682
5683 // Extract the relevant vectorWidth bits. Generate an EXTRACT_SUBVECTOR
5684 unsigned ElemsPerChunk = vectorWidth / ElVT.getSizeInBits();
5685 assert(isPowerOf2_32(ElemsPerChunk) && "Elements per chunk not power of 2")((isPowerOf2_32(ElemsPerChunk) && "Elements per chunk not power of 2"
) ? static_cast<void> (0) : __assert_fail ("isPowerOf2_32(ElemsPerChunk) && \"Elements per chunk not power of 2\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 5685, __PRETTY_FUNCTION__))
;
5686
5687 // This is the index of the first element of the vectorWidth-bit chunk
5688 // we want. Since ElemsPerChunk is a power of 2 just need to clear bits.
5689 IdxVal &= ~(ElemsPerChunk - 1);
5690
5691 // If the input is a buildvector just emit a smaller one.
5692 if (Vec.getOpcode() == ISD::BUILD_VECTOR)
5693 return DAG.getBuildVector(ResultVT, dl,
5694 Vec->ops().slice(IdxVal, ElemsPerChunk));
5695
5696 SDValue VecIdx = DAG.getIntPtrConstant(IdxVal, dl);
5697 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec, VecIdx);
5698}
5699
5700/// Generate a DAG to grab 128-bits from a vector > 128 bits. This
5701/// sets things up to match to an AVX VEXTRACTF128 / VEXTRACTI128
5702/// or AVX-512 VEXTRACTF32x4 / VEXTRACTI32x4
5703/// instructions or a simple subregister reference. Idx is an index in the
5704/// 128 bits we want. It need not be aligned to a 128-bit boundary. That makes
5705/// lowering EXTRACT_VECTOR_ELT operations easier.
5706static SDValue extract128BitVector(SDValue Vec, unsigned IdxVal,
5707 SelectionDAG &DAG, const SDLoc &dl) {
5708 assert((Vec.getValueType().is256BitVector() ||(((Vec.getValueType().is256BitVector() || Vec.getValueType().
is512BitVector()) && "Unexpected vector size!") ? static_cast
<void> (0) : __assert_fail ("(Vec.getValueType().is256BitVector() || Vec.getValueType().is512BitVector()) && \"Unexpected vector size!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 5709, __PRETTY_FUNCTION__))
5709 Vec.getValueType().is512BitVector()) && "Unexpected vector size!")(((Vec.getValueType().is256BitVector() || Vec.getValueType().
is512BitVector()) && "Unexpected vector size!") ? static_cast
<void> (0) : __assert_fail ("(Vec.getValueType().is256BitVector() || Vec.getValueType().is512BitVector()) && \"Unexpected vector size!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 5709, __PRETTY_FUNCTION__))
;
5710 return extractSubVector(Vec, IdxVal, DAG, dl, 128);
5711}
5712
5713/// Generate a DAG to grab 256-bits from a 512-bit vector.
5714static SDValue extract256BitVector(SDValue Vec, unsigned IdxVal,
5715 SelectionDAG &DAG, const SDLoc &dl) {
5716 assert(Vec.getValueType().is512BitVector() && "Unexpected vector size!")((Vec.getValueType().is512BitVector() && "Unexpected vector size!"
) ? static_cast<void> (0) : __assert_fail ("Vec.getValueType().is512BitVector() && \"Unexpected vector size!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 5716, __PRETTY_FUNCTION__))
;
5717 return extractSubVector(Vec, IdxVal, DAG, dl, 256);
5718}
5719
5720static SDValue insertSubVector(SDValue Result, SDValue Vec, unsigned IdxVal,
5721 SelectionDAG &DAG, const SDLoc &dl,
5722 unsigned vectorWidth) {
5723 assert((vectorWidth == 128 || vectorWidth == 256) &&(((vectorWidth == 128 || vectorWidth == 256) && "Unsupported vector width"
) ? static_cast<void> (0) : __assert_fail ("(vectorWidth == 128 || vectorWidth == 256) && \"Unsupported vector width\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 5724, __PRETTY_FUNCTION__))
5724 "Unsupported vector width")(((vectorWidth == 128 || vectorWidth == 256) && "Unsupported vector width"
) ? static_cast<void> (0) : __assert_fail ("(vectorWidth == 128 || vectorWidth == 256) && \"Unsupported vector width\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 5724, __PRETTY_FUNCTION__))
;
5725 // Inserting UNDEF is Result
5726 if (Vec.isUndef())
5727 return Result;
5728 EVT VT = Vec.getValueType();
5729 EVT ElVT = VT.getVectorElementType();
5730 EVT ResultVT = Result.getValueType();
5731
5732 // Insert the relevant vectorWidth bits.
5733 unsigned ElemsPerChunk = vectorWidth/ElVT.getSizeInBits();
5734 assert(isPowerOf2_32(ElemsPerChunk) && "Elements per chunk not power of 2")((isPowerOf2_32(ElemsPerChunk) && "Elements per chunk not power of 2"
) ? static_cast<void> (0) : __assert_fail ("isPowerOf2_32(ElemsPerChunk) && \"Elements per chunk not power of 2\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 5734, __PRETTY_FUNCTION__))
;
5735
5736 // This is the index of the first element of the vectorWidth-bit chunk
5737 // we want. Since ElemsPerChunk is a power of 2 just need to clear bits.
5738 IdxVal &= ~(ElemsPerChunk - 1);
5739
5740 SDValue VecIdx = DAG.getIntPtrConstant(IdxVal, dl);
5741 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec, VecIdx);
5742}
5743
5744/// Generate a DAG to put 128-bits into a vector > 128 bits. This
5745/// sets things up to match to an AVX VINSERTF128/VINSERTI128 or
5746/// AVX-512 VINSERTF32x4/VINSERTI32x4 instructions or a
5747/// simple superregister reference. Idx is an index in the 128 bits
5748/// we want. It need not be aligned to a 128-bit boundary. That makes
5749/// lowering INSERT_VECTOR_ELT operations easier.
5750static SDValue insert128BitVector(SDValue Result, SDValue Vec, unsigned IdxVal,
5751 SelectionDAG &DAG, const SDLoc &dl) {
5752 assert(Vec.getValueType().is128BitVector() && "Unexpected vector size!")((Vec.getValueType().is128BitVector() && "Unexpected vector size!"
) ? static_cast<void> (0) : __assert_fail ("Vec.getValueType().is128BitVector() && \"Unexpected vector size!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 5752, __PRETTY_FUNCTION__))
;
5753 return insertSubVector(Result, Vec, IdxVal, DAG, dl, 128);
5754}
5755
5756/// Widen a vector to a larger size with the same scalar type, with the new
5757/// elements either zero or undef.
5758static SDValue widenSubVector(MVT VT, SDValue Vec, bool ZeroNewElements,
5759 const X86Subtarget &Subtarget, SelectionDAG &DAG,
5760 const SDLoc &dl) {
5761 assert(Vec.getValueSizeInBits() < VT.getSizeInBits() &&((Vec.getValueSizeInBits() < VT.getSizeInBits() &&
Vec.getValueType().getScalarType() == VT.getScalarType() &&
"Unsupported vector widening type") ? static_cast<void>
(0) : __assert_fail ("Vec.getValueSizeInBits() < VT.getSizeInBits() && Vec.getValueType().getScalarType() == VT.getScalarType() && \"Unsupported vector widening type\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 5763, __PRETTY_FUNCTION__))
5762 Vec.getValueType().getScalarType() == VT.getScalarType() &&((Vec.getValueSizeInBits() < VT.getSizeInBits() &&
Vec.getValueType().getScalarType() == VT.getScalarType() &&
"Unsupported vector widening type") ? static_cast<void>
(0) : __assert_fail ("Vec.getValueSizeInBits() < VT.getSizeInBits() && Vec.getValueType().getScalarType() == VT.getScalarType() && \"Unsupported vector widening type\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 5763, __PRETTY_FUNCTION__))
5763 "Unsupported vector widening type")((Vec.getValueSizeInBits() < VT.getSizeInBits() &&
Vec.getValueType().getScalarType() == VT.getScalarType() &&
"Unsupported vector widening type") ? static_cast<void>
(0) : __assert_fail ("Vec.getValueSizeInBits() < VT.getSizeInBits() && Vec.getValueType().getScalarType() == VT.getScalarType() && \"Unsupported vector widening type\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 5763, __PRETTY_FUNCTION__))
;
5764 SDValue Res = ZeroNewElements ? getZeroVector(VT, Subtarget, DAG, dl)
5765 : DAG.getUNDEF(VT);
5766 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, VT, Res, Vec,
5767 DAG.getIntPtrConstant(0, dl));
5768}
5769
5770/// Widen a vector to a larger size with the same scalar type, with the new
5771/// elements either zero or undef.
5772static SDValue widenSubVector(SDValue Vec, bool ZeroNewElements,
5773 const X86Subtarget &Subtarget, SelectionDAG &DAG,
5774 const SDLoc &dl, unsigned WideSizeInBits) {
5775 assert(Vec.getValueSizeInBits() < WideSizeInBits &&((Vec.getValueSizeInBits() < WideSizeInBits && (WideSizeInBits
% Vec.getScalarValueSizeInBits()) == 0 && "Unsupported vector widening type"
) ? static_cast<void> (0) : __assert_fail ("Vec.getValueSizeInBits() < WideSizeInBits && (WideSizeInBits % Vec.getScalarValueSizeInBits()) == 0 && \"Unsupported vector widening type\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 5777, __PRETTY_FUNCTION__))
5776 (WideSizeInBits % Vec.getScalarValueSizeInBits()) == 0 &&((Vec.getValueSizeInBits() < WideSizeInBits && (WideSizeInBits
% Vec.getScalarValueSizeInBits()) == 0 && "Unsupported vector widening type"
) ? static_cast<void> (0) : __assert_fail ("Vec.getValueSizeInBits() < WideSizeInBits && (WideSizeInBits % Vec.getScalarValueSizeInBits()) == 0 && \"Unsupported vector widening type\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 5777, __PRETTY_FUNCTION__))
5777 "Unsupported vector widening type")((Vec.getValueSizeInBits() < WideSizeInBits && (WideSizeInBits
% Vec.getScalarValueSizeInBits()) == 0 && "Unsupported vector widening type"
) ? static_cast<void> (0) : __assert_fail ("Vec.getValueSizeInBits() < WideSizeInBits && (WideSizeInBits % Vec.getScalarValueSizeInBits()) == 0 && \"Unsupported vector widening type\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 5777, __PRETTY_FUNCTION__))
;
5778 unsigned WideNumElts = WideSizeInBits / Vec.getScalarValueSizeInBits();
5779 MVT SVT = Vec.getSimpleValueType().getScalarType();
5780 MVT VT = MVT::getVectorVT(SVT, WideNumElts);
5781 return widenSubVector(VT, Vec, ZeroNewElements, Subtarget, DAG, dl);
5782}
5783
5784// Helper function to collect subvector ops that are concatenated together,
5785// either by ISD::CONCAT_VECTORS or a ISD::INSERT_SUBVECTOR series.
5786// The subvectors in Ops are guaranteed to be the same type.
5787static bool collectConcatOps(SDNode *N, SmallVectorImpl<SDValue> &Ops) {
5788 assert(Ops.empty() && "Expected an empty ops vector")((Ops.empty() && "Expected an empty ops vector") ? static_cast
<void> (0) : __assert_fail ("Ops.empty() && \"Expected an empty ops vector\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 5788, __PRETTY_FUNCTION__))
;
5789
5790 if (N->getOpcode() == ISD::CONCAT_VECTORS) {
5791 Ops.append(N->op_begin(), N->op_end());
5792 return true;
5793 }
5794
5795 if (N->getOpcode() == ISD::INSERT_SUBVECTOR &&
5796 isa<ConstantSDNode>(N->getOperand(2))) {
5797 SDValue Src = N->getOperand(0);
5798 SDValue Sub = N->getOperand(1);
5799 const APInt &Idx = N->getConstantOperandAPInt(2);
5800 EVT VT = Src.getValueType();
5801 EVT SubVT = Sub.getValueType();
5802
5803 // TODO - Handle more general insert_subvector chains.
5804 if (VT.getSizeInBits() == (SubVT.getSizeInBits() * 2) &&
5805 Idx == (VT.getVectorNumElements() / 2) &&
5806 Src.getOpcode() == ISD::INSERT_SUBVECTOR &&
5807 Src.getOperand(1).getValueType() == SubVT &&
5808 isNullConstant(Src.getOperand(2))) {
5809 Ops.push_back(Src.getOperand(1));
5810 Ops.push_back(Sub);
5811 return true;
5812 }
5813 }
5814
5815 return false;
5816}
5817
5818// Helper for splitting operands of an operation to legal target size and
5819// apply a function on each part.
5820// Useful for operations that are available on SSE2 in 128-bit, on AVX2 in
5821// 256-bit and on AVX512BW in 512-bit. The argument VT is the type used for
5822// deciding if/how to split Ops. Ops elements do *not* have to be of type VT.
5823// The argument Builder is a function that will be applied on each split part:
5824// SDValue Builder(SelectionDAG&G, SDLoc, ArrayRef<SDValue>)
5825template <typename F>
5826SDValue SplitOpsAndApply(SelectionDAG &DAG, const X86Subtarget &Subtarget,
5827 const SDLoc &DL, EVT VT, ArrayRef<SDValue> Ops,
5828 F Builder, bool CheckBWI = true) {
5829 assert(Subtarget.hasSSE2() && "Target assumed to support at least SSE2")((Subtarget.hasSSE2() && "Target assumed to support at least SSE2"
) ? static_cast<void> (0) : __assert_fail ("Subtarget.hasSSE2() && \"Target assumed to support at least SSE2\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 5829, __PRETTY_FUNCTION__))
;
5830 unsigned NumSubs = 1;
5831 if ((CheckBWI && Subtarget.useBWIRegs()) ||
5832 (!CheckBWI && Subtarget.useAVX512Regs())) {
5833 if (VT.getSizeInBits() > 512) {
5834 NumSubs = VT.getSizeInBits() / 512;
5835 assert((VT.getSizeInBits() % 512) == 0 && "Illegal vector size")(((VT.getSizeInBits() % 512) == 0 && "Illegal vector size"
) ? static_cast<void> (0) : __assert_fail ("(VT.getSizeInBits() % 512) == 0 && \"Illegal vector size\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 5835, __PRETTY_FUNCTION__))
;
5836 }
5837 } else if (Subtarget.hasAVX2()) {
5838 if (VT.getSizeInBits() > 256) {
5839 NumSubs = VT.getSizeInBits() / 256;
5840 assert((VT.getSizeInBits() % 256) == 0 && "Illegal vector size")(((VT.getSizeInBits() % 256) == 0 && "Illegal vector size"
) ? static_cast<void> (0) : __assert_fail ("(VT.getSizeInBits() % 256) == 0 && \"Illegal vector size\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 5840, __PRETTY_FUNCTION__))
;
5841 }
5842 } else {
5843 if (VT.getSizeInBits() > 128) {
5844 NumSubs = VT.getSizeInBits() / 128;
5845 assert((VT.getSizeInBits() % 128) == 0 && "Illegal vector size")(((VT.getSizeInBits() % 128) == 0 && "Illegal vector size"
) ? static_cast<void> (0) : __assert_fail ("(VT.getSizeInBits() % 128) == 0 && \"Illegal vector size\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/X86/X86ISelLowering.cpp"
, 5845, __PRETTY_FUNCTION__))
;
5846 }
5847 }
5848
5849 if (NumSubs == 1)
5850 return Builder(DAG, DL, Ops);
5851
5852 SmallVector<SDValue, 4> Subs;
5853 for (unsigned i = 0; i != NumSubs; ++i) {
5854 SmallVector<SDValue, 2> SubOps;
5855 for (SDValue Op : Ops) {
5856 EVT OpVT = Op.getValueType();
5857 unsigned NumSubElts = OpVT.getVectorNumElements() / NumSubs;
5858 unsigned SizeSub = OpVT.getSizeInBits() / NumSubs;
5859 SubOps.push_back(extractSubVector(Op, i * NumSubElts, DAG, DL, SizeSub));
5860 }
5861 Subs.push_back(Builder(DAG, DL, SubOps));
5862 }
5863 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Subs);
5864}
5865
5866/// Insert i1-subvector to i1-vector.
5867static SDValue insert1BitVector(SDValue Op, SelectionDAG &DAG,
5868 const X86Subtarget &Subtarget) {
5869
5870 SDLoc dl(Op);
5871 SDValue Vec = Op.getOperand(0);
5872 SDValue SubVec = Op.getOperand(1);
5873 SDValue Idx = Op.getOperand(2);
5874
5875 if (!isa<ConstantSDNode>(Idx))
5876 return SDValue();
5877
5878 // Inserting undef is a nop. We can just return the original vector.
5879 if (SubVec.isUndef())
5880 return Vec;
5881
5882 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
5883 if (IdxVal == 0 && Vec.isUndef()) // the operation is legal
5884 return Op;
5885
5886 MVT OpVT = Op.getSimpleValueType();
5887 unsigned NumElems = OpVT.getVectorNumElements();
5888
5889 SDValue ZeroIdx = DAG.getIntPtrConstant(0, dl);
5890
5891 // Extend to natively supported kshift.
5892 MVT WideOpVT = OpVT;
5893 if ((!Subtarget.hasDQI() && NumElems == 8) || NumElems < 8)
5894