Bug Summary

File:llvm/lib/Target/X86/X86InstrInfo.cpp
Warning:line 3904, column 19
Value stored to 'NewMI' during its initialization is never read

Annotated Source Code

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clang -cc1 -cc1 -triple x86_64-pc-linux-gnu -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name X86InstrInfo.cpp -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=cplusplus -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -analyzer-config-compatibility-mode=true -mrelocation-model pic -pic-level 2 -mframe-pointer=none -fmath-errno -fno-rounding-math -mconstructor-aliases -munwind-tables -target-cpu x86-64 -tune-cpu generic -debugger-tuning=gdb -ffunction-sections -fdata-sections -fcoverage-compilation-dir=/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/build-llvm/lib/Target/X86 -resource-dir /usr/lib/llvm-14/lib/clang/14.0.0 -D _DEBUG -D _GNU_SOURCE -D __STDC_CONSTANT_MACROS -D __STDC_FORMAT_MACROS -D __STDC_LIMIT_MACROS -I /build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/build-llvm/lib/Target/X86 -I /build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/X86 -I /build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/build-llvm/include -I /build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/include -D NDEBUG -U NDEBUG -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/10/../../../../include/c++/10 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/10/../../../../include/x86_64-linux-gnu/c++/10 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/10/../../../../include/c++/10/backward -internal-isystem /usr/lib/llvm-14/lib/clang/14.0.0/include -internal-isystem /usr/local/include -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/10/../../../../x86_64-linux-gnu/include -internal-externc-isystem /usr/include/x86_64-linux-gnu -internal-externc-isystem /include -internal-externc-isystem /usr/include -O2 -Wno-unused-parameter -Wwrite-strings -Wno-missing-field-initializers -Wno-long-long -Wno-maybe-uninitialized -Wno-class-memaccess -Wno-redundant-move -Wno-pessimizing-move -Wno-noexcept-type -Wno-comment -std=c++14 -fdeprecated-macro -fdebug-compilation-dir=/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/build-llvm/lib/Target/X86 -fdebug-prefix-map=/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0=. -ferror-limit 19 -fvisibility hidden -fvisibility-inlines-hidden -stack-protector 2 -fgnuc-version=4.2.1 -vectorize-loops -vectorize-slp -analyzer-output=html -analyzer-config stable-report-filename=true -faddrsig -D__GCC_HAVE_DWARF2_CFI_ASM=1 -o /tmp/scan-build-2021-08-28-193554-24367-1 -x c++ /build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/X86/X86InstrInfo.cpp
1//===-- X86InstrInfo.cpp - X86 Instruction Information --------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the X86 implementation of the TargetInstrInfo class.
10//
11//===----------------------------------------------------------------------===//
12
13#include "X86InstrInfo.h"
14#include "X86.h"
15#include "X86InstrBuilder.h"
16#include "X86InstrFoldTables.h"
17#include "X86MachineFunctionInfo.h"
18#include "X86Subtarget.h"
19#include "X86TargetMachine.h"
20#include "llvm/ADT/STLExtras.h"
21#include "llvm/ADT/Sequence.h"
22#include "llvm/CodeGen/LivePhysRegs.h"
23#include "llvm/CodeGen/LiveVariables.h"
24#include "llvm/CodeGen/MachineConstantPool.h"
25#include "llvm/CodeGen/MachineDominators.h"
26#include "llvm/CodeGen/MachineFrameInfo.h"
27#include "llvm/CodeGen/MachineInstrBuilder.h"
28#include "llvm/CodeGen/MachineModuleInfo.h"
29#include "llvm/CodeGen/MachineRegisterInfo.h"
30#include "llvm/CodeGen/StackMaps.h"
31#include "llvm/IR/DebugInfoMetadata.h"
32#include "llvm/IR/DerivedTypes.h"
33#include "llvm/IR/Function.h"
34#include "llvm/MC/MCAsmInfo.h"
35#include "llvm/MC/MCExpr.h"
36#include "llvm/MC/MCInst.h"
37#include "llvm/Support/CommandLine.h"
38#include "llvm/Support/Debug.h"
39#include "llvm/Support/ErrorHandling.h"
40#include "llvm/Support/raw_ostream.h"
41#include "llvm/Target/TargetOptions.h"
42
43using namespace llvm;
44
45#define DEBUG_TYPE"x86-instr-info" "x86-instr-info"
46
47#define GET_INSTRINFO_CTOR_DTOR
48#include "X86GenInstrInfo.inc"
49
50static cl::opt<bool>
51 NoFusing("disable-spill-fusing",
52 cl::desc("Disable fusing of spill code into instructions"),
53 cl::Hidden);
54static cl::opt<bool>
55PrintFailedFusing("print-failed-fuse-candidates",
56 cl::desc("Print instructions that the allocator wants to"
57 " fuse, but the X86 backend currently can't"),
58 cl::Hidden);
59static cl::opt<bool>
60ReMatPICStubLoad("remat-pic-stub-load",
61 cl::desc("Re-materialize load from stub in PIC mode"),
62 cl::init(false), cl::Hidden);
63static cl::opt<unsigned>
64PartialRegUpdateClearance("partial-reg-update-clearance",
65 cl::desc("Clearance between two register writes "
66 "for inserting XOR to avoid partial "
67 "register update"),
68 cl::init(64), cl::Hidden);
69static cl::opt<unsigned>
70UndefRegClearance("undef-reg-clearance",
71 cl::desc("How many idle instructions we would like before "
72 "certain undef register reads"),
73 cl::init(128), cl::Hidden);
74
75
76// Pin the vtable to this file.
77void X86InstrInfo::anchor() {}
78
79X86InstrInfo::X86InstrInfo(X86Subtarget &STI)
80 : X86GenInstrInfo((STI.isTarget64BitLP64() ? X86::ADJCALLSTACKDOWN64
81 : X86::ADJCALLSTACKDOWN32),
82 (STI.isTarget64BitLP64() ? X86::ADJCALLSTACKUP64
83 : X86::ADJCALLSTACKUP32),
84 X86::CATCHRET,
85 (STI.is64Bit() ? X86::RETQ : X86::RETL)),
86 Subtarget(STI), RI(STI.getTargetTriple()) {
87}
88
89bool
90X86InstrInfo::isCoalescableExtInstr(const MachineInstr &MI,
91 Register &SrcReg, Register &DstReg,
92 unsigned &SubIdx) const {
93 switch (MI.getOpcode()) {
94 default: break;
95 case X86::MOVSX16rr8:
96 case X86::MOVZX16rr8:
97 case X86::MOVSX32rr8:
98 case X86::MOVZX32rr8:
99 case X86::MOVSX64rr8:
100 if (!Subtarget.is64Bit())
101 // It's not always legal to reference the low 8-bit of the larger
102 // register in 32-bit mode.
103 return false;
104 LLVM_FALLTHROUGH[[gnu::fallthrough]];
105 case X86::MOVSX32rr16:
106 case X86::MOVZX32rr16:
107 case X86::MOVSX64rr16:
108 case X86::MOVSX64rr32: {
109 if (MI.getOperand(0).getSubReg() || MI.getOperand(1).getSubReg())
110 // Be conservative.
111 return false;
112 SrcReg = MI.getOperand(1).getReg();
113 DstReg = MI.getOperand(0).getReg();
114 switch (MI.getOpcode()) {
115 default: llvm_unreachable("Unreachable!")::llvm::llvm_unreachable_internal("Unreachable!", "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 115)
;
116 case X86::MOVSX16rr8:
117 case X86::MOVZX16rr8:
118 case X86::MOVSX32rr8:
119 case X86::MOVZX32rr8:
120 case X86::MOVSX64rr8:
121 SubIdx = X86::sub_8bit;
122 break;
123 case X86::MOVSX32rr16:
124 case X86::MOVZX32rr16:
125 case X86::MOVSX64rr16:
126 SubIdx = X86::sub_16bit;
127 break;
128 case X86::MOVSX64rr32:
129 SubIdx = X86::sub_32bit;
130 break;
131 }
132 return true;
133 }
134 }
135 return false;
136}
137
138bool X86InstrInfo::isDataInvariant(MachineInstr &MI) {
139 switch (MI.getOpcode()) {
140 default:
141 // By default, assume that the instruction is not data invariant.
142 return false;
143
144 // Some target-independent operations that trivially lower to data-invariant
145 // instructions.
146 case TargetOpcode::COPY:
147 case TargetOpcode::INSERT_SUBREG:
148 case TargetOpcode::SUBREG_TO_REG:
149 return true;
150
151 // On x86 it is believed that imul is constant time w.r.t. the loaded data.
152 // However, they set flags and are perhaps the most surprisingly constant
153 // time operations so we call them out here separately.
154 case X86::IMUL16rr:
155 case X86::IMUL16rri8:
156 case X86::IMUL16rri:
157 case X86::IMUL32rr:
158 case X86::IMUL32rri8:
159 case X86::IMUL32rri:
160 case X86::IMUL64rr:
161 case X86::IMUL64rri32:
162 case X86::IMUL64rri8:
163
164 // Bit scanning and counting instructions that are somewhat surprisingly
165 // constant time as they scan across bits and do other fairly complex
166 // operations like popcnt, but are believed to be constant time on x86.
167 // However, these set flags.
168 case X86::BSF16rr:
169 case X86::BSF32rr:
170 case X86::BSF64rr:
171 case X86::BSR16rr:
172 case X86::BSR32rr:
173 case X86::BSR64rr:
174 case X86::LZCNT16rr:
175 case X86::LZCNT32rr:
176 case X86::LZCNT64rr:
177 case X86::POPCNT16rr:
178 case X86::POPCNT32rr:
179 case X86::POPCNT64rr:
180 case X86::TZCNT16rr:
181 case X86::TZCNT32rr:
182 case X86::TZCNT64rr:
183
184 // Bit manipulation instructions are effectively combinations of basic
185 // arithmetic ops, and should still execute in constant time. These also
186 // set flags.
187 case X86::BLCFILL32rr:
188 case X86::BLCFILL64rr:
189 case X86::BLCI32rr:
190 case X86::BLCI64rr:
191 case X86::BLCIC32rr:
192 case X86::BLCIC64rr:
193 case X86::BLCMSK32rr:
194 case X86::BLCMSK64rr:
195 case X86::BLCS32rr:
196 case X86::BLCS64rr:
197 case X86::BLSFILL32rr:
198 case X86::BLSFILL64rr:
199 case X86::BLSI32rr:
200 case X86::BLSI64rr:
201 case X86::BLSIC32rr:
202 case X86::BLSIC64rr:
203 case X86::BLSMSK32rr:
204 case X86::BLSMSK64rr:
205 case X86::BLSR32rr:
206 case X86::BLSR64rr:
207 case X86::TZMSK32rr:
208 case X86::TZMSK64rr:
209
210 // Bit extracting and clearing instructions should execute in constant time,
211 // and set flags.
212 case X86::BEXTR32rr:
213 case X86::BEXTR64rr:
214 case X86::BEXTRI32ri:
215 case X86::BEXTRI64ri:
216 case X86::BZHI32rr:
217 case X86::BZHI64rr:
218
219 // Shift and rotate.
220 case X86::ROL8r1:
221 case X86::ROL16r1:
222 case X86::ROL32r1:
223 case X86::ROL64r1:
224 case X86::ROL8rCL:
225 case X86::ROL16rCL:
226 case X86::ROL32rCL:
227 case X86::ROL64rCL:
228 case X86::ROL8ri:
229 case X86::ROL16ri:
230 case X86::ROL32ri:
231 case X86::ROL64ri:
232 case X86::ROR8r1:
233 case X86::ROR16r1:
234 case X86::ROR32r1:
235 case X86::ROR64r1:
236 case X86::ROR8rCL:
237 case X86::ROR16rCL:
238 case X86::ROR32rCL:
239 case X86::ROR64rCL:
240 case X86::ROR8ri:
241 case X86::ROR16ri:
242 case X86::ROR32ri:
243 case X86::ROR64ri:
244 case X86::SAR8r1:
245 case X86::SAR16r1:
246 case X86::SAR32r1:
247 case X86::SAR64r1:
248 case X86::SAR8rCL:
249 case X86::SAR16rCL:
250 case X86::SAR32rCL:
251 case X86::SAR64rCL:
252 case X86::SAR8ri:
253 case X86::SAR16ri:
254 case X86::SAR32ri:
255 case X86::SAR64ri:
256 case X86::SHL8r1:
257 case X86::SHL16r1:
258 case X86::SHL32r1:
259 case X86::SHL64r1:
260 case X86::SHL8rCL:
261 case X86::SHL16rCL:
262 case X86::SHL32rCL:
263 case X86::SHL64rCL:
264 case X86::SHL8ri:
265 case X86::SHL16ri:
266 case X86::SHL32ri:
267 case X86::SHL64ri:
268 case X86::SHR8r1:
269 case X86::SHR16r1:
270 case X86::SHR32r1:
271 case X86::SHR64r1:
272 case X86::SHR8rCL:
273 case X86::SHR16rCL:
274 case X86::SHR32rCL:
275 case X86::SHR64rCL:
276 case X86::SHR8ri:
277 case X86::SHR16ri:
278 case X86::SHR32ri:
279 case X86::SHR64ri:
280 case X86::SHLD16rrCL:
281 case X86::SHLD32rrCL:
282 case X86::SHLD64rrCL:
283 case X86::SHLD16rri8:
284 case X86::SHLD32rri8:
285 case X86::SHLD64rri8:
286 case X86::SHRD16rrCL:
287 case X86::SHRD32rrCL:
288 case X86::SHRD64rrCL:
289 case X86::SHRD16rri8:
290 case X86::SHRD32rri8:
291 case X86::SHRD64rri8:
292
293 // Basic arithmetic is constant time on the input but does set flags.
294 case X86::ADC8rr:
295 case X86::ADC8ri:
296 case X86::ADC16rr:
297 case X86::ADC16ri:
298 case X86::ADC16ri8:
299 case X86::ADC32rr:
300 case X86::ADC32ri:
301 case X86::ADC32ri8:
302 case X86::ADC64rr:
303 case X86::ADC64ri8:
304 case X86::ADC64ri32:
305 case X86::ADD8rr:
306 case X86::ADD8ri:
307 case X86::ADD16rr:
308 case X86::ADD16ri:
309 case X86::ADD16ri8:
310 case X86::ADD32rr:
311 case X86::ADD32ri:
312 case X86::ADD32ri8:
313 case X86::ADD64rr:
314 case X86::ADD64ri8:
315 case X86::ADD64ri32:
316 case X86::AND8rr:
317 case X86::AND8ri:
318 case X86::AND16rr:
319 case X86::AND16ri:
320 case X86::AND16ri8:
321 case X86::AND32rr:
322 case X86::AND32ri:
323 case X86::AND32ri8:
324 case X86::AND64rr:
325 case X86::AND64ri8:
326 case X86::AND64ri32:
327 case X86::OR8rr:
328 case X86::OR8ri:
329 case X86::OR16rr:
330 case X86::OR16ri:
331 case X86::OR16ri8:
332 case X86::OR32rr:
333 case X86::OR32ri:
334 case X86::OR32ri8:
335 case X86::OR64rr:
336 case X86::OR64ri8:
337 case X86::OR64ri32:
338 case X86::SBB8rr:
339 case X86::SBB8ri:
340 case X86::SBB16rr:
341 case X86::SBB16ri:
342 case X86::SBB16ri8:
343 case X86::SBB32rr:
344 case X86::SBB32ri:
345 case X86::SBB32ri8:
346 case X86::SBB64rr:
347 case X86::SBB64ri8:
348 case X86::SBB64ri32:
349 case X86::SUB8rr:
350 case X86::SUB8ri:
351 case X86::SUB16rr:
352 case X86::SUB16ri:
353 case X86::SUB16ri8:
354 case X86::SUB32rr:
355 case X86::SUB32ri:
356 case X86::SUB32ri8:
357 case X86::SUB64rr:
358 case X86::SUB64ri8:
359 case X86::SUB64ri32:
360 case X86::XOR8rr:
361 case X86::XOR8ri:
362 case X86::XOR16rr:
363 case X86::XOR16ri:
364 case X86::XOR16ri8:
365 case X86::XOR32rr:
366 case X86::XOR32ri:
367 case X86::XOR32ri8:
368 case X86::XOR64rr:
369 case X86::XOR64ri8:
370 case X86::XOR64ri32:
371 // Arithmetic with just 32-bit and 64-bit variants and no immediates.
372 case X86::ADCX32rr:
373 case X86::ADCX64rr:
374 case X86::ADOX32rr:
375 case X86::ADOX64rr:
376 case X86::ANDN32rr:
377 case X86::ANDN64rr:
378 // Unary arithmetic operations.
379 case X86::DEC8r:
380 case X86::DEC16r:
381 case X86::DEC32r:
382 case X86::DEC64r:
383 case X86::INC8r:
384 case X86::INC16r:
385 case X86::INC32r:
386 case X86::INC64r:
387 case X86::NEG8r:
388 case X86::NEG16r:
389 case X86::NEG32r:
390 case X86::NEG64r:
391
392 // Unlike other arithmetic, NOT doesn't set EFLAGS.
393 case X86::NOT8r:
394 case X86::NOT16r:
395 case X86::NOT32r:
396 case X86::NOT64r:
397
398 // Various move instructions used to zero or sign extend things. Note that we
399 // intentionally don't support the _NOREX variants as we can't handle that
400 // register constraint anyways.
401 case X86::MOVSX16rr8:
402 case X86::MOVSX32rr8:
403 case X86::MOVSX32rr16:
404 case X86::MOVSX64rr8:
405 case X86::MOVSX64rr16:
406 case X86::MOVSX64rr32:
407 case X86::MOVZX16rr8:
408 case X86::MOVZX32rr8:
409 case X86::MOVZX32rr16:
410 case X86::MOVZX64rr8:
411 case X86::MOVZX64rr16:
412 case X86::MOV32rr:
413
414 // Arithmetic instructions that are both constant time and don't set flags.
415 case X86::RORX32ri:
416 case X86::RORX64ri:
417 case X86::SARX32rr:
418 case X86::SARX64rr:
419 case X86::SHLX32rr:
420 case X86::SHLX64rr:
421 case X86::SHRX32rr:
422 case X86::SHRX64rr:
423
424 // LEA doesn't actually access memory, and its arithmetic is constant time.
425 case X86::LEA16r:
426 case X86::LEA32r:
427 case X86::LEA64_32r:
428 case X86::LEA64r:
429 return true;
430 }
431}
432
433bool X86InstrInfo::isDataInvariantLoad(MachineInstr &MI) {
434 switch (MI.getOpcode()) {
435 default:
436 // By default, assume that the load will immediately leak.
437 return false;
438
439 // On x86 it is believed that imul is constant time w.r.t. the loaded data.
440 // However, they set flags and are perhaps the most surprisingly constant
441 // time operations so we call them out here separately.
442 case X86::IMUL16rm:
443 case X86::IMUL16rmi8:
444 case X86::IMUL16rmi:
445 case X86::IMUL32rm:
446 case X86::IMUL32rmi8:
447 case X86::IMUL32rmi:
448 case X86::IMUL64rm:
449 case X86::IMUL64rmi32:
450 case X86::IMUL64rmi8:
451
452 // Bit scanning and counting instructions that are somewhat surprisingly
453 // constant time as they scan across bits and do other fairly complex
454 // operations like popcnt, but are believed to be constant time on x86.
455 // However, these set flags.
456 case X86::BSF16rm:
457 case X86::BSF32rm:
458 case X86::BSF64rm:
459 case X86::BSR16rm:
460 case X86::BSR32rm:
461 case X86::BSR64rm:
462 case X86::LZCNT16rm:
463 case X86::LZCNT32rm:
464 case X86::LZCNT64rm:
465 case X86::POPCNT16rm:
466 case X86::POPCNT32rm:
467 case X86::POPCNT64rm:
468 case X86::TZCNT16rm:
469 case X86::TZCNT32rm:
470 case X86::TZCNT64rm:
471
472 // Bit manipulation instructions are effectively combinations of basic
473 // arithmetic ops, and should still execute in constant time. These also
474 // set flags.
475 case X86::BLCFILL32rm:
476 case X86::BLCFILL64rm:
477 case X86::BLCI32rm:
478 case X86::BLCI64rm:
479 case X86::BLCIC32rm:
480 case X86::BLCIC64rm:
481 case X86::BLCMSK32rm:
482 case X86::BLCMSK64rm:
483 case X86::BLCS32rm:
484 case X86::BLCS64rm:
485 case X86::BLSFILL32rm:
486 case X86::BLSFILL64rm:
487 case X86::BLSI32rm:
488 case X86::BLSI64rm:
489 case X86::BLSIC32rm:
490 case X86::BLSIC64rm:
491 case X86::BLSMSK32rm:
492 case X86::BLSMSK64rm:
493 case X86::BLSR32rm:
494 case X86::BLSR64rm:
495 case X86::TZMSK32rm:
496 case X86::TZMSK64rm:
497
498 // Bit extracting and clearing instructions should execute in constant time,
499 // and set flags.
500 case X86::BEXTR32rm:
501 case X86::BEXTR64rm:
502 case X86::BEXTRI32mi:
503 case X86::BEXTRI64mi:
504 case X86::BZHI32rm:
505 case X86::BZHI64rm:
506
507 // Basic arithmetic is constant time on the input but does set flags.
508 case X86::ADC8rm:
509 case X86::ADC16rm:
510 case X86::ADC32rm:
511 case X86::ADC64rm:
512 case X86::ADCX32rm:
513 case X86::ADCX64rm:
514 case X86::ADD8rm:
515 case X86::ADD16rm:
516 case X86::ADD32rm:
517 case X86::ADD64rm:
518 case X86::ADOX32rm:
519 case X86::ADOX64rm:
520 case X86::AND8rm:
521 case X86::AND16rm:
522 case X86::AND32rm:
523 case X86::AND64rm:
524 case X86::ANDN32rm:
525 case X86::ANDN64rm:
526 case X86::OR8rm:
527 case X86::OR16rm:
528 case X86::OR32rm:
529 case X86::OR64rm:
530 case X86::SBB8rm:
531 case X86::SBB16rm:
532 case X86::SBB32rm:
533 case X86::SBB64rm:
534 case X86::SUB8rm:
535 case X86::SUB16rm:
536 case X86::SUB32rm:
537 case X86::SUB64rm:
538 case X86::XOR8rm:
539 case X86::XOR16rm:
540 case X86::XOR32rm:
541 case X86::XOR64rm:
542
543 // Integer multiply w/o affecting flags is still believed to be constant
544 // time on x86. Called out separately as this is among the most surprising
545 // instructions to exhibit that behavior.
546 case X86::MULX32rm:
547 case X86::MULX64rm:
548
549 // Arithmetic instructions that are both constant time and don't set flags.
550 case X86::RORX32mi:
551 case X86::RORX64mi:
552 case X86::SARX32rm:
553 case X86::SARX64rm:
554 case X86::SHLX32rm:
555 case X86::SHLX64rm:
556 case X86::SHRX32rm:
557 case X86::SHRX64rm:
558
559 // Conversions are believed to be constant time and don't set flags.
560 case X86::CVTTSD2SI64rm:
561 case X86::VCVTTSD2SI64rm:
562 case X86::VCVTTSD2SI64Zrm:
563 case X86::CVTTSD2SIrm:
564 case X86::VCVTTSD2SIrm:
565 case X86::VCVTTSD2SIZrm:
566 case X86::CVTTSS2SI64rm:
567 case X86::VCVTTSS2SI64rm:
568 case X86::VCVTTSS2SI64Zrm:
569 case X86::CVTTSS2SIrm:
570 case X86::VCVTTSS2SIrm:
571 case X86::VCVTTSS2SIZrm:
572 case X86::CVTSI2SDrm:
573 case X86::VCVTSI2SDrm:
574 case X86::VCVTSI2SDZrm:
575 case X86::CVTSI2SSrm:
576 case X86::VCVTSI2SSrm:
577 case X86::VCVTSI2SSZrm:
578 case X86::CVTSI642SDrm:
579 case X86::VCVTSI642SDrm:
580 case X86::VCVTSI642SDZrm:
581 case X86::CVTSI642SSrm:
582 case X86::VCVTSI642SSrm:
583 case X86::VCVTSI642SSZrm:
584 case X86::CVTSS2SDrm:
585 case X86::VCVTSS2SDrm:
586 case X86::VCVTSS2SDZrm:
587 case X86::CVTSD2SSrm:
588 case X86::VCVTSD2SSrm:
589 case X86::VCVTSD2SSZrm:
590 // AVX512 added unsigned integer conversions.
591 case X86::VCVTTSD2USI64Zrm:
592 case X86::VCVTTSD2USIZrm:
593 case X86::VCVTTSS2USI64Zrm:
594 case X86::VCVTTSS2USIZrm:
595 case X86::VCVTUSI2SDZrm:
596 case X86::VCVTUSI642SDZrm:
597 case X86::VCVTUSI2SSZrm:
598 case X86::VCVTUSI642SSZrm:
599
600 // Loads to register don't set flags.
601 case X86::MOV8rm:
602 case X86::MOV8rm_NOREX:
603 case X86::MOV16rm:
604 case X86::MOV32rm:
605 case X86::MOV64rm:
606 case X86::MOVSX16rm8:
607 case X86::MOVSX32rm16:
608 case X86::MOVSX32rm8:
609 case X86::MOVSX32rm8_NOREX:
610 case X86::MOVSX64rm16:
611 case X86::MOVSX64rm32:
612 case X86::MOVSX64rm8:
613 case X86::MOVZX16rm8:
614 case X86::MOVZX32rm16:
615 case X86::MOVZX32rm8:
616 case X86::MOVZX32rm8_NOREX:
617 case X86::MOVZX64rm16:
618 case X86::MOVZX64rm8:
619 return true;
620 }
621}
622
623int X86InstrInfo::getSPAdjust(const MachineInstr &MI) const {
624 const MachineFunction *MF = MI.getParent()->getParent();
625 const TargetFrameLowering *TFI = MF->getSubtarget().getFrameLowering();
626
627 if (isFrameInstr(MI)) {
628 int SPAdj = alignTo(getFrameSize(MI), TFI->getStackAlign());
629 SPAdj -= getFrameAdjustment(MI);
630 if (!isFrameSetup(MI))
631 SPAdj = -SPAdj;
632 return SPAdj;
633 }
634
635 // To know whether a call adjusts the stack, we need information
636 // that is bound to the following ADJCALLSTACKUP pseudo.
637 // Look for the next ADJCALLSTACKUP that follows the call.
638 if (MI.isCall()) {
639 const MachineBasicBlock *MBB = MI.getParent();
640 auto I = ++MachineBasicBlock::const_iterator(MI);
641 for (auto E = MBB->end(); I != E; ++I) {
642 if (I->getOpcode() == getCallFrameDestroyOpcode() ||
643 I->isCall())
644 break;
645 }
646
647 // If we could not find a frame destroy opcode, then it has already
648 // been simplified, so we don't care.
649 if (I->getOpcode() != getCallFrameDestroyOpcode())
650 return 0;
651
652 return -(I->getOperand(1).getImm());
653 }
654
655 // Currently handle only PUSHes we can reasonably expect to see
656 // in call sequences
657 switch (MI.getOpcode()) {
658 default:
659 return 0;
660 case X86::PUSH32i8:
661 case X86::PUSH32r:
662 case X86::PUSH32rmm:
663 case X86::PUSH32rmr:
664 case X86::PUSHi32:
665 return 4;
666 case X86::PUSH64i8:
667 case X86::PUSH64r:
668 case X86::PUSH64rmm:
669 case X86::PUSH64rmr:
670 case X86::PUSH64i32:
671 return 8;
672 }
673}
674
675/// Return true and the FrameIndex if the specified
676/// operand and follow operands form a reference to the stack frame.
677bool X86InstrInfo::isFrameOperand(const MachineInstr &MI, unsigned int Op,
678 int &FrameIndex) const {
679 if (MI.getOperand(Op + X86::AddrBaseReg).isFI() &&
680 MI.getOperand(Op + X86::AddrScaleAmt).isImm() &&
681 MI.getOperand(Op + X86::AddrIndexReg).isReg() &&
682 MI.getOperand(Op + X86::AddrDisp).isImm() &&
683 MI.getOperand(Op + X86::AddrScaleAmt).getImm() == 1 &&
684 MI.getOperand(Op + X86::AddrIndexReg).getReg() == 0 &&
685 MI.getOperand(Op + X86::AddrDisp).getImm() == 0) {
686 FrameIndex = MI.getOperand(Op + X86::AddrBaseReg).getIndex();
687 return true;
688 }
689 return false;
690}
691
692static bool isFrameLoadOpcode(int Opcode, unsigned &MemBytes) {
693 switch (Opcode) {
694 default:
695 return false;
696 case X86::MOV8rm:
697 case X86::KMOVBkm:
698 MemBytes = 1;
699 return true;
700 case X86::MOV16rm:
701 case X86::KMOVWkm:
702 case X86::VMOVSHZrm:
703 case X86::VMOVSHZrm_alt:
704 MemBytes = 2;
705 return true;
706 case X86::MOV32rm:
707 case X86::MOVSSrm:
708 case X86::MOVSSrm_alt:
709 case X86::VMOVSSrm:
710 case X86::VMOVSSrm_alt:
711 case X86::VMOVSSZrm:
712 case X86::VMOVSSZrm_alt:
713 case X86::KMOVDkm:
714 MemBytes = 4;
715 return true;
716 case X86::MOV64rm:
717 case X86::LD_Fp64m:
718 case X86::MOVSDrm:
719 case X86::MOVSDrm_alt:
720 case X86::VMOVSDrm:
721 case X86::VMOVSDrm_alt:
722 case X86::VMOVSDZrm:
723 case X86::VMOVSDZrm_alt:
724 case X86::MMX_MOVD64rm:
725 case X86::MMX_MOVQ64rm:
726 case X86::KMOVQkm:
727 MemBytes = 8;
728 return true;
729 case X86::MOVAPSrm:
730 case X86::MOVUPSrm:
731 case X86::MOVAPDrm:
732 case X86::MOVUPDrm:
733 case X86::MOVDQArm:
734 case X86::MOVDQUrm:
735 case X86::VMOVAPSrm:
736 case X86::VMOVUPSrm:
737 case X86::VMOVAPDrm:
738 case X86::VMOVUPDrm:
739 case X86::VMOVDQArm:
740 case X86::VMOVDQUrm:
741 case X86::VMOVAPSZ128rm:
742 case X86::VMOVUPSZ128rm:
743 case X86::VMOVAPSZ128rm_NOVLX:
744 case X86::VMOVUPSZ128rm_NOVLX:
745 case X86::VMOVAPDZ128rm:
746 case X86::VMOVUPDZ128rm:
747 case X86::VMOVDQU8Z128rm:
748 case X86::VMOVDQU16Z128rm:
749 case X86::VMOVDQA32Z128rm:
750 case X86::VMOVDQU32Z128rm:
751 case X86::VMOVDQA64Z128rm:
752 case X86::VMOVDQU64Z128rm:
753 MemBytes = 16;
754 return true;
755 case X86::VMOVAPSYrm:
756 case X86::VMOVUPSYrm:
757 case X86::VMOVAPDYrm:
758 case X86::VMOVUPDYrm:
759 case X86::VMOVDQAYrm:
760 case X86::VMOVDQUYrm:
761 case X86::VMOVAPSZ256rm:
762 case X86::VMOVUPSZ256rm:
763 case X86::VMOVAPSZ256rm_NOVLX:
764 case X86::VMOVUPSZ256rm_NOVLX:
765 case X86::VMOVAPDZ256rm:
766 case X86::VMOVUPDZ256rm:
767 case X86::VMOVDQU8Z256rm:
768 case X86::VMOVDQU16Z256rm:
769 case X86::VMOVDQA32Z256rm:
770 case X86::VMOVDQU32Z256rm:
771 case X86::VMOVDQA64Z256rm:
772 case X86::VMOVDQU64Z256rm:
773 MemBytes = 32;
774 return true;
775 case X86::VMOVAPSZrm:
776 case X86::VMOVUPSZrm:
777 case X86::VMOVAPDZrm:
778 case X86::VMOVUPDZrm:
779 case X86::VMOVDQU8Zrm:
780 case X86::VMOVDQU16Zrm:
781 case X86::VMOVDQA32Zrm:
782 case X86::VMOVDQU32Zrm:
783 case X86::VMOVDQA64Zrm:
784 case X86::VMOVDQU64Zrm:
785 MemBytes = 64;
786 return true;
787 }
788}
789
790static bool isFrameStoreOpcode(int Opcode, unsigned &MemBytes) {
791 switch (Opcode) {
792 default:
793 return false;
794 case X86::MOV8mr:
795 case X86::KMOVBmk:
796 MemBytes = 1;
797 return true;
798 case X86::MOV16mr:
799 case X86::KMOVWmk:
800 case X86::VMOVSHZmr:
801 MemBytes = 2;
802 return true;
803 case X86::MOV32mr:
804 case X86::MOVSSmr:
805 case X86::VMOVSSmr:
806 case X86::VMOVSSZmr:
807 case X86::KMOVDmk:
808 MemBytes = 4;
809 return true;
810 case X86::MOV64mr:
811 case X86::ST_FpP64m:
812 case X86::MOVSDmr:
813 case X86::VMOVSDmr:
814 case X86::VMOVSDZmr:
815 case X86::MMX_MOVD64mr:
816 case X86::MMX_MOVQ64mr:
817 case X86::MMX_MOVNTQmr:
818 case X86::KMOVQmk:
819 MemBytes = 8;
820 return true;
821 case X86::MOVAPSmr:
822 case X86::MOVUPSmr:
823 case X86::MOVAPDmr:
824 case X86::MOVUPDmr:
825 case X86::MOVDQAmr:
826 case X86::MOVDQUmr:
827 case X86::VMOVAPSmr:
828 case X86::VMOVUPSmr:
829 case X86::VMOVAPDmr:
830 case X86::VMOVUPDmr:
831 case X86::VMOVDQAmr:
832 case X86::VMOVDQUmr:
833 case X86::VMOVUPSZ128mr:
834 case X86::VMOVAPSZ128mr:
835 case X86::VMOVUPSZ128mr_NOVLX:
836 case X86::VMOVAPSZ128mr_NOVLX:
837 case X86::VMOVUPDZ128mr:
838 case X86::VMOVAPDZ128mr:
839 case X86::VMOVDQA32Z128mr:
840 case X86::VMOVDQU32Z128mr:
841 case X86::VMOVDQA64Z128mr:
842 case X86::VMOVDQU64Z128mr:
843 case X86::VMOVDQU8Z128mr:
844 case X86::VMOVDQU16Z128mr:
845 MemBytes = 16;
846 return true;
847 case X86::VMOVUPSYmr:
848 case X86::VMOVAPSYmr:
849 case X86::VMOVUPDYmr:
850 case X86::VMOVAPDYmr:
851 case X86::VMOVDQUYmr:
852 case X86::VMOVDQAYmr:
853 case X86::VMOVUPSZ256mr:
854 case X86::VMOVAPSZ256mr:
855 case X86::VMOVUPSZ256mr_NOVLX:
856 case X86::VMOVAPSZ256mr_NOVLX:
857 case X86::VMOVUPDZ256mr:
858 case X86::VMOVAPDZ256mr:
859 case X86::VMOVDQU8Z256mr:
860 case X86::VMOVDQU16Z256mr:
861 case X86::VMOVDQA32Z256mr:
862 case X86::VMOVDQU32Z256mr:
863 case X86::VMOVDQA64Z256mr:
864 case X86::VMOVDQU64Z256mr:
865 MemBytes = 32;
866 return true;
867 case X86::VMOVUPSZmr:
868 case X86::VMOVAPSZmr:
869 case X86::VMOVUPDZmr:
870 case X86::VMOVAPDZmr:
871 case X86::VMOVDQU8Zmr:
872 case X86::VMOVDQU16Zmr:
873 case X86::VMOVDQA32Zmr:
874 case X86::VMOVDQU32Zmr:
875 case X86::VMOVDQA64Zmr:
876 case X86::VMOVDQU64Zmr:
877 MemBytes = 64;
878 return true;
879 }
880 return false;
881}
882
883unsigned X86InstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
884 int &FrameIndex) const {
885 unsigned Dummy;
886 return X86InstrInfo::isLoadFromStackSlot(MI, FrameIndex, Dummy);
887}
888
889unsigned X86InstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
890 int &FrameIndex,
891 unsigned &MemBytes) const {
892 if (isFrameLoadOpcode(MI.getOpcode(), MemBytes))
893 if (MI.getOperand(0).getSubReg() == 0 && isFrameOperand(MI, 1, FrameIndex))
894 return MI.getOperand(0).getReg();
895 return 0;
896}
897
898unsigned X86InstrInfo::isLoadFromStackSlotPostFE(const MachineInstr &MI,
899 int &FrameIndex) const {
900 unsigned Dummy;
901 if (isFrameLoadOpcode(MI.getOpcode(), Dummy)) {
902 unsigned Reg;
903 if ((Reg = isLoadFromStackSlot(MI, FrameIndex)))
904 return Reg;
905 // Check for post-frame index elimination operations
906 SmallVector<const MachineMemOperand *, 1> Accesses;
907 if (hasLoadFromStackSlot(MI, Accesses)) {
908 FrameIndex =
909 cast<FixedStackPseudoSourceValue>(Accesses.front()->getPseudoValue())
910 ->getFrameIndex();
911 return MI.getOperand(0).getReg();
912 }
913 }
914 return 0;
915}
916
917unsigned X86InstrInfo::isStoreToStackSlot(const MachineInstr &MI,
918 int &FrameIndex) const {
919 unsigned Dummy;
920 return X86InstrInfo::isStoreToStackSlot(MI, FrameIndex, Dummy);
921}
922
923unsigned X86InstrInfo::isStoreToStackSlot(const MachineInstr &MI,
924 int &FrameIndex,
925 unsigned &MemBytes) const {
926 if (isFrameStoreOpcode(MI.getOpcode(), MemBytes))
927 if (MI.getOperand(X86::AddrNumOperands).getSubReg() == 0 &&
928 isFrameOperand(MI, 0, FrameIndex))
929 return MI.getOperand(X86::AddrNumOperands).getReg();
930 return 0;
931}
932
933unsigned X86InstrInfo::isStoreToStackSlotPostFE(const MachineInstr &MI,
934 int &FrameIndex) const {
935 unsigned Dummy;
936 if (isFrameStoreOpcode(MI.getOpcode(), Dummy)) {
937 unsigned Reg;
938 if ((Reg = isStoreToStackSlot(MI, FrameIndex)))
939 return Reg;
940 // Check for post-frame index elimination operations
941 SmallVector<const MachineMemOperand *, 1> Accesses;
942 if (hasStoreToStackSlot(MI, Accesses)) {
943 FrameIndex =
944 cast<FixedStackPseudoSourceValue>(Accesses.front()->getPseudoValue())
945 ->getFrameIndex();
946 return MI.getOperand(X86::AddrNumOperands).getReg();
947 }
948 }
949 return 0;
950}
951
952/// Return true if register is PIC base; i.e.g defined by X86::MOVPC32r.
953static bool regIsPICBase(Register BaseReg, const MachineRegisterInfo &MRI) {
954 // Don't waste compile time scanning use-def chains of physregs.
955 if (!BaseReg.isVirtual())
956 return false;
957 bool isPICBase = false;
958 for (MachineRegisterInfo::def_instr_iterator I = MRI.def_instr_begin(BaseReg),
959 E = MRI.def_instr_end(); I != E; ++I) {
960 MachineInstr *DefMI = &*I;
961 if (DefMI->getOpcode() != X86::MOVPC32r)
962 return false;
963 assert(!isPICBase && "More than one PIC base?")(static_cast <bool> (!isPICBase && "More than one PIC base?"
) ? void (0) : __assert_fail ("!isPICBase && \"More than one PIC base?\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 963, __extension__ __PRETTY_FUNCTION__))
;
964 isPICBase = true;
965 }
966 return isPICBase;
967}
968
969bool X86InstrInfo::isReallyTriviallyReMaterializable(const MachineInstr &MI,
970 AAResults *AA) const {
971 switch (MI.getOpcode()) {
972 default:
973 // This function should only be called for opcodes with the ReMaterializable
974 // flag set.
975 llvm_unreachable("Unknown rematerializable operation!")::llvm::llvm_unreachable_internal("Unknown rematerializable operation!"
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 975)
;
976 break;
977
978 case X86::LOAD_STACK_GUARD:
979 case X86::AVX1_SETALLONES:
980 case X86::AVX2_SETALLONES:
981 case X86::AVX512_128_SET0:
982 case X86::AVX512_256_SET0:
983 case X86::AVX512_512_SET0:
984 case X86::AVX512_512_SETALLONES:
985 case X86::AVX512_FsFLD0SD:
986 case X86::AVX512_FsFLD0SH:
987 case X86::AVX512_FsFLD0SS:
988 case X86::AVX512_FsFLD0F128:
989 case X86::AVX_SET0:
990 case X86::FsFLD0SD:
991 case X86::FsFLD0SS:
992 case X86::FsFLD0F128:
993 case X86::KSET0D:
994 case X86::KSET0Q:
995 case X86::KSET0W:
996 case X86::KSET1D:
997 case X86::KSET1Q:
998 case X86::KSET1W:
999 case X86::MMX_SET0:
1000 case X86::MOV32ImmSExti8:
1001 case X86::MOV32r0:
1002 case X86::MOV32r1:
1003 case X86::MOV32r_1:
1004 case X86::MOV32ri64:
1005 case X86::MOV64ImmSExti8:
1006 case X86::V_SET0:
1007 case X86::V_SETALLONES:
1008 case X86::MOV16ri:
1009 case X86::MOV32ri:
1010 case X86::MOV64ri:
1011 case X86::MOV64ri32:
1012 case X86::MOV8ri:
1013 case X86::PTILEZEROV:
1014 return true;
1015
1016 case X86::MOV8rm:
1017 case X86::MOV8rm_NOREX:
1018 case X86::MOV16rm:
1019 case X86::MOV32rm:
1020 case X86::MOV64rm:
1021 case X86::MOVSSrm:
1022 case X86::MOVSSrm_alt:
1023 case X86::MOVSDrm:
1024 case X86::MOVSDrm_alt:
1025 case X86::MOVAPSrm:
1026 case X86::MOVUPSrm:
1027 case X86::MOVAPDrm:
1028 case X86::MOVUPDrm:
1029 case X86::MOVDQArm:
1030 case X86::MOVDQUrm:
1031 case X86::VMOVSSrm:
1032 case X86::VMOVSSrm_alt:
1033 case X86::VMOVSDrm:
1034 case X86::VMOVSDrm_alt:
1035 case X86::VMOVAPSrm:
1036 case X86::VMOVUPSrm:
1037 case X86::VMOVAPDrm:
1038 case X86::VMOVUPDrm:
1039 case X86::VMOVDQArm:
1040 case X86::VMOVDQUrm:
1041 case X86::VMOVAPSYrm:
1042 case X86::VMOVUPSYrm:
1043 case X86::VMOVAPDYrm:
1044 case X86::VMOVUPDYrm:
1045 case X86::VMOVDQAYrm:
1046 case X86::VMOVDQUYrm:
1047 case X86::MMX_MOVD64rm:
1048 case X86::MMX_MOVQ64rm:
1049 // AVX-512
1050 case X86::VMOVSSZrm:
1051 case X86::VMOVSSZrm_alt:
1052 case X86::VMOVSDZrm:
1053 case X86::VMOVSDZrm_alt:
1054 case X86::VMOVSHZrm:
1055 case X86::VMOVSHZrm_alt:
1056 case X86::VMOVAPDZ128rm:
1057 case X86::VMOVAPDZ256rm:
1058 case X86::VMOVAPDZrm:
1059 case X86::VMOVAPSZ128rm:
1060 case X86::VMOVAPSZ256rm:
1061 case X86::VMOVAPSZ128rm_NOVLX:
1062 case X86::VMOVAPSZ256rm_NOVLX:
1063 case X86::VMOVAPSZrm:
1064 case X86::VMOVDQA32Z128rm:
1065 case X86::VMOVDQA32Z256rm:
1066 case X86::VMOVDQA32Zrm:
1067 case X86::VMOVDQA64Z128rm:
1068 case X86::VMOVDQA64Z256rm:
1069 case X86::VMOVDQA64Zrm:
1070 case X86::VMOVDQU16Z128rm:
1071 case X86::VMOVDQU16Z256rm:
1072 case X86::VMOVDQU16Zrm:
1073 case X86::VMOVDQU32Z128rm:
1074 case X86::VMOVDQU32Z256rm:
1075 case X86::VMOVDQU32Zrm:
1076 case X86::VMOVDQU64Z128rm:
1077 case X86::VMOVDQU64Z256rm:
1078 case X86::VMOVDQU64Zrm:
1079 case X86::VMOVDQU8Z128rm:
1080 case X86::VMOVDQU8Z256rm:
1081 case X86::VMOVDQU8Zrm:
1082 case X86::VMOVUPDZ128rm:
1083 case X86::VMOVUPDZ256rm:
1084 case X86::VMOVUPDZrm:
1085 case X86::VMOVUPSZ128rm:
1086 case X86::VMOVUPSZ256rm:
1087 case X86::VMOVUPSZ128rm_NOVLX:
1088 case X86::VMOVUPSZ256rm_NOVLX:
1089 case X86::VMOVUPSZrm: {
1090 // Loads from constant pools are trivially rematerializable.
1091 if (MI.getOperand(1 + X86::AddrBaseReg).isReg() &&
1092 MI.getOperand(1 + X86::AddrScaleAmt).isImm() &&
1093 MI.getOperand(1 + X86::AddrIndexReg).isReg() &&
1094 MI.getOperand(1 + X86::AddrIndexReg).getReg() == 0 &&
1095 MI.isDereferenceableInvariantLoad(AA)) {
1096 Register BaseReg = MI.getOperand(1 + X86::AddrBaseReg).getReg();
1097 if (BaseReg == 0 || BaseReg == X86::RIP)
1098 return true;
1099 // Allow re-materialization of PIC load.
1100 if (!ReMatPICStubLoad && MI.getOperand(1 + X86::AddrDisp).isGlobal())
1101 return false;
1102 const MachineFunction &MF = *MI.getParent()->getParent();
1103 const MachineRegisterInfo &MRI = MF.getRegInfo();
1104 return regIsPICBase(BaseReg, MRI);
1105 }
1106 return false;
1107 }
1108
1109 case X86::LEA32r:
1110 case X86::LEA64r: {
1111 if (MI.getOperand(1 + X86::AddrScaleAmt).isImm() &&
1112 MI.getOperand(1 + X86::AddrIndexReg).isReg() &&
1113 MI.getOperand(1 + X86::AddrIndexReg).getReg() == 0 &&
1114 !MI.getOperand(1 + X86::AddrDisp).isReg()) {
1115 // lea fi#, lea GV, etc. are all rematerializable.
1116 if (!MI.getOperand(1 + X86::AddrBaseReg).isReg())
1117 return true;
1118 Register BaseReg = MI.getOperand(1 + X86::AddrBaseReg).getReg();
1119 if (BaseReg == 0)
1120 return true;
1121 // Allow re-materialization of lea PICBase + x.
1122 const MachineFunction &MF = *MI.getParent()->getParent();
1123 const MachineRegisterInfo &MRI = MF.getRegInfo();
1124 return regIsPICBase(BaseReg, MRI);
1125 }
1126 return false;
1127 }
1128 }
1129}
1130
1131void X86InstrInfo::reMaterialize(MachineBasicBlock &MBB,
1132 MachineBasicBlock::iterator I,
1133 Register DestReg, unsigned SubIdx,
1134 const MachineInstr &Orig,
1135 const TargetRegisterInfo &TRI) const {
1136 bool ClobbersEFLAGS = Orig.modifiesRegister(X86::EFLAGS, &TRI);
1137 if (ClobbersEFLAGS && MBB.computeRegisterLiveness(&TRI, X86::EFLAGS, I) !=
1138 MachineBasicBlock::LQR_Dead) {
1139 // The instruction clobbers EFLAGS. Re-materialize as MOV32ri to avoid side
1140 // effects.
1141 int Value;
1142 switch (Orig.getOpcode()) {
1143 case X86::MOV32r0: Value = 0; break;
1144 case X86::MOV32r1: Value = 1; break;
1145 case X86::MOV32r_1: Value = -1; break;
1146 default:
1147 llvm_unreachable("Unexpected instruction!")::llvm::llvm_unreachable_internal("Unexpected instruction!", "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 1147)
;
1148 }
1149
1150 const DebugLoc &DL = Orig.getDebugLoc();
1151 BuildMI(MBB, I, DL, get(X86::MOV32ri))
1152 .add(Orig.getOperand(0))
1153 .addImm(Value);
1154 } else {
1155 MachineInstr *MI = MBB.getParent()->CloneMachineInstr(&Orig);
1156 MBB.insert(I, MI);
1157 }
1158
1159 MachineInstr &NewMI = *std::prev(I);
1160 NewMI.substituteRegister(Orig.getOperand(0).getReg(), DestReg, SubIdx, TRI);
1161}
1162
1163/// True if MI has a condition code def, e.g. EFLAGS, that is not marked dead.
1164bool X86InstrInfo::hasLiveCondCodeDef(MachineInstr &MI) const {
1165 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
1166 MachineOperand &MO = MI.getOperand(i);
1167 if (MO.isReg() && MO.isDef() &&
1168 MO.getReg() == X86::EFLAGS && !MO.isDead()) {
1169 return true;
1170 }
1171 }
1172 return false;
1173}
1174
1175/// Check whether the shift count for a machine operand is non-zero.
1176inline static unsigned getTruncatedShiftCount(const MachineInstr &MI,
1177 unsigned ShiftAmtOperandIdx) {
1178 // The shift count is six bits with the REX.W prefix and five bits without.
1179 unsigned ShiftCountMask = (MI.getDesc().TSFlags & X86II::REX_W) ? 63 : 31;
1180 unsigned Imm = MI.getOperand(ShiftAmtOperandIdx).getImm();
1181 return Imm & ShiftCountMask;
1182}
1183
1184/// Check whether the given shift count is appropriate
1185/// can be represented by a LEA instruction.
1186inline static bool isTruncatedShiftCountForLEA(unsigned ShAmt) {
1187 // Left shift instructions can be transformed into load-effective-address
1188 // instructions if we can encode them appropriately.
1189 // A LEA instruction utilizes a SIB byte to encode its scale factor.
1190 // The SIB.scale field is two bits wide which means that we can encode any
1191 // shift amount less than 4.
1192 return ShAmt < 4 && ShAmt > 0;
1193}
1194
1195bool X86InstrInfo::classifyLEAReg(MachineInstr &MI, const MachineOperand &Src,
1196 unsigned Opc, bool AllowSP, Register &NewSrc,
1197 bool &isKill, MachineOperand &ImplicitOp,
1198 LiveVariables *LV) const {
1199 MachineFunction &MF = *MI.getParent()->getParent();
1200 const TargetRegisterClass *RC;
1201 if (AllowSP) {
1202 RC = Opc != X86::LEA32r ? &X86::GR64RegClass : &X86::GR32RegClass;
1203 } else {
1204 RC = Opc != X86::LEA32r ?
1205 &X86::GR64_NOSPRegClass : &X86::GR32_NOSPRegClass;
1206 }
1207 Register SrcReg = Src.getReg();
1208
1209 // For both LEA64 and LEA32 the register already has essentially the right
1210 // type (32-bit or 64-bit) we may just need to forbid SP.
1211 if (Opc != X86::LEA64_32r) {
1212 NewSrc = SrcReg;
1213 isKill = Src.isKill();
1214 assert(!Src.isUndef() && "Undef op doesn't need optimization")(static_cast <bool> (!Src.isUndef() && "Undef op doesn't need optimization"
) ? void (0) : __assert_fail ("!Src.isUndef() && \"Undef op doesn't need optimization\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 1214, __extension__ __PRETTY_FUNCTION__))
;
1215
1216 if (NewSrc.isVirtual() && !MF.getRegInfo().constrainRegClass(NewSrc, RC))
1217 return false;
1218
1219 return true;
1220 }
1221
1222 // This is for an LEA64_32r and incoming registers are 32-bit. One way or
1223 // another we need to add 64-bit registers to the final MI.
1224 if (SrcReg.isPhysical()) {
1225 ImplicitOp = Src;
1226 ImplicitOp.setImplicit();
1227
1228 NewSrc = getX86SubSuperRegister(Src.getReg(), 64);
1229 isKill = Src.isKill();
1230 assert(!Src.isUndef() && "Undef op doesn't need optimization")(static_cast <bool> (!Src.isUndef() && "Undef op doesn't need optimization"
) ? void (0) : __assert_fail ("!Src.isUndef() && \"Undef op doesn't need optimization\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 1230, __extension__ __PRETTY_FUNCTION__))
;
1231 } else {
1232 // Virtual register of the wrong class, we have to create a temporary 64-bit
1233 // vreg to feed into the LEA.
1234 NewSrc = MF.getRegInfo().createVirtualRegister(RC);
1235 MachineInstr *Copy =
1236 BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(TargetOpcode::COPY))
1237 .addReg(NewSrc, RegState::Define | RegState::Undef, X86::sub_32bit)
1238 .add(Src);
1239
1240 // Which is obviously going to be dead after we're done with it.
1241 isKill = true;
1242
1243 if (LV)
1244 LV->replaceKillInstruction(SrcReg, MI, *Copy);
1245 }
1246
1247 // We've set all the parameters without issue.
1248 return true;
1249}
1250
1251MachineInstr *X86InstrInfo::convertToThreeAddressWithLEA(
1252 unsigned MIOpc, MachineFunction::iterator &MFI, MachineInstr &MI,
1253 LiveVariables *LV, bool Is8BitOp) const {
1254 // We handle 8-bit adds and various 16-bit opcodes in the switch below.
1255 MachineRegisterInfo &RegInfo = MFI->getParent()->getRegInfo();
1256 assert((Is8BitOp || RegInfo.getTargetRegisterInfo()->getRegSizeInBits((static_cast <bool> ((Is8BitOp || RegInfo.getTargetRegisterInfo
()->getRegSizeInBits( *RegInfo.getRegClass(MI.getOperand(0
).getReg())) == 16) && "Unexpected type for LEA transform"
) ? void (0) : __assert_fail ("(Is8BitOp || RegInfo.getTargetRegisterInfo()->getRegSizeInBits( *RegInfo.getRegClass(MI.getOperand(0).getReg())) == 16) && \"Unexpected type for LEA transform\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 1258, __extension__ __PRETTY_FUNCTION__))
1257 *RegInfo.getRegClass(MI.getOperand(0).getReg())) == 16) &&(static_cast <bool> ((Is8BitOp || RegInfo.getTargetRegisterInfo
()->getRegSizeInBits( *RegInfo.getRegClass(MI.getOperand(0
).getReg())) == 16) && "Unexpected type for LEA transform"
) ? void (0) : __assert_fail ("(Is8BitOp || RegInfo.getTargetRegisterInfo()->getRegSizeInBits( *RegInfo.getRegClass(MI.getOperand(0).getReg())) == 16) && \"Unexpected type for LEA transform\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 1258, __extension__ __PRETTY_FUNCTION__))
1258 "Unexpected type for LEA transform")(static_cast <bool> ((Is8BitOp || RegInfo.getTargetRegisterInfo
()->getRegSizeInBits( *RegInfo.getRegClass(MI.getOperand(0
).getReg())) == 16) && "Unexpected type for LEA transform"
) ? void (0) : __assert_fail ("(Is8BitOp || RegInfo.getTargetRegisterInfo()->getRegSizeInBits( *RegInfo.getRegClass(MI.getOperand(0).getReg())) == 16) && \"Unexpected type for LEA transform\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 1258, __extension__ __PRETTY_FUNCTION__))
;
1259
1260 // TODO: For a 32-bit target, we need to adjust the LEA variables with
1261 // something like this:
1262 // Opcode = X86::LEA32r;
1263 // InRegLEA = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
1264 // OutRegLEA =
1265 // Is8BitOp ? RegInfo.createVirtualRegister(&X86::GR32ABCD_RegClass)
1266 // : RegInfo.createVirtualRegister(&X86::GR32RegClass);
1267 if (!Subtarget.is64Bit())
1268 return nullptr;
1269
1270 unsigned Opcode = X86::LEA64_32r;
1271 Register InRegLEA = RegInfo.createVirtualRegister(&X86::GR64_NOSPRegClass);
1272 Register OutRegLEA = RegInfo.createVirtualRegister(&X86::GR32RegClass);
1273
1274 // Build and insert into an implicit UNDEF value. This is OK because
1275 // we will be shifting and then extracting the lower 8/16-bits.
1276 // This has the potential to cause partial register stall. e.g.
1277 // movw (%rbp,%rcx,2), %dx
1278 // leal -65(%rdx), %esi
1279 // But testing has shown this *does* help performance in 64-bit mode (at
1280 // least on modern x86 machines).
1281 MachineBasicBlock::iterator MBBI = MI.getIterator();
1282 Register Dest = MI.getOperand(0).getReg();
1283 Register Src = MI.getOperand(1).getReg();
1284 bool IsDead = MI.getOperand(0).isDead();
1285 bool IsKill = MI.getOperand(1).isKill();
1286 unsigned SubReg = Is8BitOp ? X86::sub_8bit : X86::sub_16bit;
1287 assert(!MI.getOperand(1).isUndef() && "Undef op doesn't need optimization")(static_cast <bool> (!MI.getOperand(1).isUndef() &&
"Undef op doesn't need optimization") ? void (0) : __assert_fail
("!MI.getOperand(1).isUndef() && \"Undef op doesn't need optimization\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 1287, __extension__ __PRETTY_FUNCTION__))
;
1288 BuildMI(*MFI, MBBI, MI.getDebugLoc(), get(X86::IMPLICIT_DEF), InRegLEA);
1289 MachineInstr *InsMI =
1290 BuildMI(*MFI, MBBI, MI.getDebugLoc(), get(TargetOpcode::COPY))
1291 .addReg(InRegLEA, RegState::Define, SubReg)
1292 .addReg(Src, getKillRegState(IsKill));
1293
1294 MachineInstrBuilder MIB =
1295 BuildMI(*MFI, MBBI, MI.getDebugLoc(), get(Opcode), OutRegLEA);
1296 switch (MIOpc) {
1297 default: llvm_unreachable("Unreachable!")::llvm::llvm_unreachable_internal("Unreachable!", "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 1297)
;
1298 case X86::SHL8ri:
1299 case X86::SHL16ri: {
1300 unsigned ShAmt = MI.getOperand(2).getImm();
1301 MIB.addReg(0).addImm(1ULL << ShAmt)
1302 .addReg(InRegLEA, RegState::Kill).addImm(0).addReg(0);
1303 break;
1304 }
1305 case X86::INC8r:
1306 case X86::INC16r:
1307 addRegOffset(MIB, InRegLEA, true, 1);
1308 break;
1309 case X86::DEC8r:
1310 case X86::DEC16r:
1311 addRegOffset(MIB, InRegLEA, true, -1);
1312 break;
1313 case X86::ADD8ri:
1314 case X86::ADD8ri_DB:
1315 case X86::ADD16ri:
1316 case X86::ADD16ri8:
1317 case X86::ADD16ri_DB:
1318 case X86::ADD16ri8_DB:
1319 addRegOffset(MIB, InRegLEA, true, MI.getOperand(2).getImm());
1320 break;
1321 case X86::ADD8rr:
1322 case X86::ADD8rr_DB:
1323 case X86::ADD16rr:
1324 case X86::ADD16rr_DB: {
1325 Register Src2 = MI.getOperand(2).getReg();
1326 bool IsKill2 = MI.getOperand(2).isKill();
1327 assert(!MI.getOperand(2).isUndef() && "Undef op doesn't need optimization")(static_cast <bool> (!MI.getOperand(2).isUndef() &&
"Undef op doesn't need optimization") ? void (0) : __assert_fail
("!MI.getOperand(2).isUndef() && \"Undef op doesn't need optimization\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 1327, __extension__ __PRETTY_FUNCTION__))
;
1328 unsigned InRegLEA2 = 0;
1329 MachineInstr *InsMI2 = nullptr;
1330 if (Src == Src2) {
1331 // ADD8rr/ADD16rr killed %reg1028, %reg1028
1332 // just a single insert_subreg.
1333 addRegReg(MIB, InRegLEA, true, InRegLEA, false);
1334 } else {
1335 if (Subtarget.is64Bit())
1336 InRegLEA2 = RegInfo.createVirtualRegister(&X86::GR64_NOSPRegClass);
1337 else
1338 InRegLEA2 = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
1339 // Build and insert into an implicit UNDEF value. This is OK because
1340 // we will be shifting and then extracting the lower 8/16-bits.
1341 BuildMI(*MFI, &*MIB, MI.getDebugLoc(), get(X86::IMPLICIT_DEF), InRegLEA2);
1342 InsMI2 = BuildMI(*MFI, &*MIB, MI.getDebugLoc(), get(TargetOpcode::COPY))
1343 .addReg(InRegLEA2, RegState::Define, SubReg)
1344 .addReg(Src2, getKillRegState(IsKill2));
1345 addRegReg(MIB, InRegLEA, true, InRegLEA2, true);
1346 }
1347 if (LV && IsKill2 && InsMI2)
1348 LV->replaceKillInstruction(Src2, MI, *InsMI2);
1349 break;
1350 }
1351 }
1352
1353 MachineInstr *NewMI = MIB;
1354 MachineInstr *ExtMI =
1355 BuildMI(*MFI, MBBI, MI.getDebugLoc(), get(TargetOpcode::COPY))
1356 .addReg(Dest, RegState::Define | getDeadRegState(IsDead))
1357 .addReg(OutRegLEA, RegState::Kill, SubReg);
1358
1359 if (LV) {
1360 // Update live variables.
1361 LV->getVarInfo(InRegLEA).Kills.push_back(NewMI);
1362 LV->getVarInfo(OutRegLEA).Kills.push_back(ExtMI);
1363 if (IsKill)
1364 LV->replaceKillInstruction(Src, MI, *InsMI);
1365 if (IsDead)
1366 LV->replaceKillInstruction(Dest, MI, *ExtMI);
1367 }
1368
1369 return ExtMI;
1370}
1371
1372/// This method must be implemented by targets that
1373/// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
1374/// may be able to convert a two-address instruction into a true
1375/// three-address instruction on demand. This allows the X86 target (for
1376/// example) to convert ADD and SHL instructions into LEA instructions if they
1377/// would require register copies due to two-addressness.
1378///
1379/// This method returns a null pointer if the transformation cannot be
1380/// performed, otherwise it returns the new instruction.
1381///
1382MachineInstr *
1383X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
1384 MachineInstr &MI, LiveVariables *LV) const {
1385 // The following opcodes also sets the condition code register(s). Only
1386 // convert them to equivalent lea if the condition code register def's
1387 // are dead!
1388 if (hasLiveCondCodeDef(MI))
1389 return nullptr;
1390
1391 MachineFunction &MF = *MI.getParent()->getParent();
1392 // All instructions input are two-addr instructions. Get the known operands.
1393 const MachineOperand &Dest = MI.getOperand(0);
1394 const MachineOperand &Src = MI.getOperand(1);
1395
1396 // Ideally, operations with undef should be folded before we get here, but we
1397 // can't guarantee it. Bail out because optimizing undefs is a waste of time.
1398 // Without this, we have to forward undef state to new register operands to
1399 // avoid machine verifier errors.
1400 if (Src.isUndef())
1401 return nullptr;
1402 if (MI.getNumOperands() > 2)
1403 if (MI.getOperand(2).isReg() && MI.getOperand(2).isUndef())
1404 return nullptr;
1405
1406 MachineInstr *NewMI = nullptr;
1407 bool Is64Bit = Subtarget.is64Bit();
1408
1409 bool Is8BitOp = false;
1410 unsigned MIOpc = MI.getOpcode();
1411 switch (MIOpc) {
1412 default: llvm_unreachable("Unreachable!")::llvm::llvm_unreachable_internal("Unreachable!", "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 1412)
;
1413 case X86::SHL64ri: {
1414 assert(MI.getNumOperands() >= 3 && "Unknown shift instruction!")(static_cast <bool> (MI.getNumOperands() >= 3 &&
"Unknown shift instruction!") ? void (0) : __assert_fail ("MI.getNumOperands() >= 3 && \"Unknown shift instruction!\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 1414, __extension__ __PRETTY_FUNCTION__))
;
1415 unsigned ShAmt = getTruncatedShiftCount(MI, 2);
1416 if (!isTruncatedShiftCountForLEA(ShAmt)) return nullptr;
1417
1418 // LEA can't handle RSP.
1419 if (Src.getReg().isVirtual() && !MF.getRegInfo().constrainRegClass(
1420 Src.getReg(), &X86::GR64_NOSPRegClass))
1421 return nullptr;
1422
1423 NewMI = BuildMI(MF, MI.getDebugLoc(), get(X86::LEA64r))
1424 .add(Dest)
1425 .addReg(0)
1426 .addImm(1ULL << ShAmt)
1427 .add(Src)
1428 .addImm(0)
1429 .addReg(0);
1430 break;
1431 }
1432 case X86::SHL32ri: {
1433 assert(MI.getNumOperands() >= 3 && "Unknown shift instruction!")(static_cast <bool> (MI.getNumOperands() >= 3 &&
"Unknown shift instruction!") ? void (0) : __assert_fail ("MI.getNumOperands() >= 3 && \"Unknown shift instruction!\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 1433, __extension__ __PRETTY_FUNCTION__))
;
1434 unsigned ShAmt = getTruncatedShiftCount(MI, 2);
1435 if (!isTruncatedShiftCountForLEA(ShAmt)) return nullptr;
1436
1437 unsigned Opc = Is64Bit ? X86::LEA64_32r : X86::LEA32r;
1438
1439 // LEA can't handle ESP.
1440 bool isKill;
1441 Register SrcReg;
1442 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
1443 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false,
1444 SrcReg, isKill, ImplicitOp, LV))
1445 return nullptr;
1446
1447 MachineInstrBuilder MIB =
1448 BuildMI(MF, MI.getDebugLoc(), get(Opc))
1449 .add(Dest)
1450 .addReg(0)
1451 .addImm(1ULL << ShAmt)
1452 .addReg(SrcReg, getKillRegState(isKill))
1453 .addImm(0)
1454 .addReg(0);
1455 if (ImplicitOp.getReg() != 0)
1456 MIB.add(ImplicitOp);
1457 NewMI = MIB;
1458
1459 break;
1460 }
1461 case X86::SHL8ri:
1462 Is8BitOp = true;
1463 LLVM_FALLTHROUGH[[gnu::fallthrough]];
1464 case X86::SHL16ri: {
1465 assert(MI.getNumOperands() >= 3 && "Unknown shift instruction!")(static_cast <bool> (MI.getNumOperands() >= 3 &&
"Unknown shift instruction!") ? void (0) : __assert_fail ("MI.getNumOperands() >= 3 && \"Unknown shift instruction!\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 1465, __extension__ __PRETTY_FUNCTION__))
;
1466 unsigned ShAmt = getTruncatedShiftCount(MI, 2);
1467 if (!isTruncatedShiftCountForLEA(ShAmt))
1468 return nullptr;
1469 return convertToThreeAddressWithLEA(MIOpc, MFI, MI, LV, Is8BitOp);
1470 }
1471 case X86::INC64r:
1472 case X86::INC32r: {
1473 assert(MI.getNumOperands() >= 2 && "Unknown inc instruction!")(static_cast <bool> (MI.getNumOperands() >= 2 &&
"Unknown inc instruction!") ? void (0) : __assert_fail ("MI.getNumOperands() >= 2 && \"Unknown inc instruction!\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 1473, __extension__ __PRETTY_FUNCTION__))
;
1474 unsigned Opc = MIOpc == X86::INC64r ? X86::LEA64r :
1475 (Is64Bit ? X86::LEA64_32r : X86::LEA32r);
1476 bool isKill;
1477 Register SrcReg;
1478 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
1479 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false, SrcReg, isKill,
1480 ImplicitOp, LV))
1481 return nullptr;
1482
1483 MachineInstrBuilder MIB =
1484 BuildMI(MF, MI.getDebugLoc(), get(Opc))
1485 .add(Dest)
1486 .addReg(SrcReg, getKillRegState(isKill));
1487 if (ImplicitOp.getReg() != 0)
1488 MIB.add(ImplicitOp);
1489
1490 NewMI = addOffset(MIB, 1);
1491 break;
1492 }
1493 case X86::DEC64r:
1494 case X86::DEC32r: {
1495 assert(MI.getNumOperands() >= 2 && "Unknown dec instruction!")(static_cast <bool> (MI.getNumOperands() >= 2 &&
"Unknown dec instruction!") ? void (0) : __assert_fail ("MI.getNumOperands() >= 2 && \"Unknown dec instruction!\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 1495, __extension__ __PRETTY_FUNCTION__))
;
1496 unsigned Opc = MIOpc == X86::DEC64r ? X86::LEA64r
1497 : (Is64Bit ? X86::LEA64_32r : X86::LEA32r);
1498
1499 bool isKill;
1500 Register SrcReg;
1501 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
1502 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false, SrcReg, isKill,
1503 ImplicitOp, LV))
1504 return nullptr;
1505
1506 MachineInstrBuilder MIB = BuildMI(MF, MI.getDebugLoc(), get(Opc))
1507 .add(Dest)
1508 .addReg(SrcReg, getKillRegState(isKill));
1509 if (ImplicitOp.getReg() != 0)
1510 MIB.add(ImplicitOp);
1511
1512 NewMI = addOffset(MIB, -1);
1513
1514 break;
1515 }
1516 case X86::DEC8r:
1517 case X86::INC8r:
1518 Is8BitOp = true;
1519 LLVM_FALLTHROUGH[[gnu::fallthrough]];
1520 case X86::DEC16r:
1521 case X86::INC16r:
1522 return convertToThreeAddressWithLEA(MIOpc, MFI, MI, LV, Is8BitOp);
1523 case X86::ADD64rr:
1524 case X86::ADD64rr_DB:
1525 case X86::ADD32rr:
1526 case X86::ADD32rr_DB: {
1527 assert(MI.getNumOperands() >= 3 && "Unknown add instruction!")(static_cast <bool> (MI.getNumOperands() >= 3 &&
"Unknown add instruction!") ? void (0) : __assert_fail ("MI.getNumOperands() >= 3 && \"Unknown add instruction!\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 1527, __extension__ __PRETTY_FUNCTION__))
;
1528 unsigned Opc;
1529 if (MIOpc == X86::ADD64rr || MIOpc == X86::ADD64rr_DB)
1530 Opc = X86::LEA64r;
1531 else
1532 Opc = Is64Bit ? X86::LEA64_32r : X86::LEA32r;
1533
1534 bool isKill;
1535 Register SrcReg;
1536 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
1537 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ true,
1538 SrcReg, isKill, ImplicitOp, LV))
1539 return nullptr;
1540
1541 const MachineOperand &Src2 = MI.getOperand(2);
1542 bool isKill2;
1543 Register SrcReg2;
1544 MachineOperand ImplicitOp2 = MachineOperand::CreateReg(0, false);
1545 if (!classifyLEAReg(MI, Src2, Opc, /*AllowSP=*/ false,
1546 SrcReg2, isKill2, ImplicitOp2, LV))
1547 return nullptr;
1548
1549 MachineInstrBuilder MIB = BuildMI(MF, MI.getDebugLoc(), get(Opc)).add(Dest);
1550 if (ImplicitOp.getReg() != 0)
1551 MIB.add(ImplicitOp);
1552 if (ImplicitOp2.getReg() != 0)
1553 MIB.add(ImplicitOp2);
1554
1555 NewMI = addRegReg(MIB, SrcReg, isKill, SrcReg2, isKill2);
1556 if (LV && Src2.isKill())
1557 LV->replaceKillInstruction(SrcReg2, MI, *NewMI);
1558 break;
1559 }
1560 case X86::ADD8rr:
1561 case X86::ADD8rr_DB:
1562 Is8BitOp = true;
1563 LLVM_FALLTHROUGH[[gnu::fallthrough]];
1564 case X86::ADD16rr:
1565 case X86::ADD16rr_DB:
1566 return convertToThreeAddressWithLEA(MIOpc, MFI, MI, LV, Is8BitOp);
1567 case X86::ADD64ri32:
1568 case X86::ADD64ri8:
1569 case X86::ADD64ri32_DB:
1570 case X86::ADD64ri8_DB:
1571 assert(MI.getNumOperands() >= 3 && "Unknown add instruction!")(static_cast <bool> (MI.getNumOperands() >= 3 &&
"Unknown add instruction!") ? void (0) : __assert_fail ("MI.getNumOperands() >= 3 && \"Unknown add instruction!\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 1571, __extension__ __PRETTY_FUNCTION__))
;
1572 NewMI = addOffset(
1573 BuildMI(MF, MI.getDebugLoc(), get(X86::LEA64r)).add(Dest).add(Src),
1574 MI.getOperand(2));
1575 break;
1576 case X86::ADD32ri:
1577 case X86::ADD32ri8:
1578 case X86::ADD32ri_DB:
1579 case X86::ADD32ri8_DB: {
1580 assert(MI.getNumOperands() >= 3 && "Unknown add instruction!")(static_cast <bool> (MI.getNumOperands() >= 3 &&
"Unknown add instruction!") ? void (0) : __assert_fail ("MI.getNumOperands() >= 3 && \"Unknown add instruction!\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 1580, __extension__ __PRETTY_FUNCTION__))
;
1581 unsigned Opc = Is64Bit ? X86::LEA64_32r : X86::LEA32r;
1582
1583 bool isKill;
1584 Register SrcReg;
1585 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
1586 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ true,
1587 SrcReg, isKill, ImplicitOp, LV))
1588 return nullptr;
1589
1590 MachineInstrBuilder MIB = BuildMI(MF, MI.getDebugLoc(), get(Opc))
1591 .add(Dest)
1592 .addReg(SrcReg, getKillRegState(isKill));
1593 if (ImplicitOp.getReg() != 0)
1594 MIB.add(ImplicitOp);
1595
1596 NewMI = addOffset(MIB, MI.getOperand(2));
1597 break;
1598 }
1599 case X86::ADD8ri:
1600 case X86::ADD8ri_DB:
1601 Is8BitOp = true;
1602 LLVM_FALLTHROUGH[[gnu::fallthrough]];
1603 case X86::ADD16ri:
1604 case X86::ADD16ri8:
1605 case X86::ADD16ri_DB:
1606 case X86::ADD16ri8_DB:
1607 return convertToThreeAddressWithLEA(MIOpc, MFI, MI, LV, Is8BitOp);
1608 case X86::SUB8ri:
1609 case X86::SUB16ri8:
1610 case X86::SUB16ri:
1611 /// FIXME: Support these similar to ADD8ri/ADD16ri*.
1612 return nullptr;
1613 case X86::SUB32ri8:
1614 case X86::SUB32ri: {
1615 if (!MI.getOperand(2).isImm())
1616 return nullptr;
1617 int64_t Imm = MI.getOperand(2).getImm();
1618 if (!isInt<32>(-Imm))
1619 return nullptr;
1620
1621 assert(MI.getNumOperands() >= 3 && "Unknown add instruction!")(static_cast <bool> (MI.getNumOperands() >= 3 &&
"Unknown add instruction!") ? void (0) : __assert_fail ("MI.getNumOperands() >= 3 && \"Unknown add instruction!\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 1621, __extension__ __PRETTY_FUNCTION__))
;
1622 unsigned Opc = Is64Bit ? X86::LEA64_32r : X86::LEA32r;
1623
1624 bool isKill;
1625 Register SrcReg;
1626 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
1627 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ true,
1628 SrcReg, isKill, ImplicitOp, LV))
1629 return nullptr;
1630
1631 MachineInstrBuilder MIB = BuildMI(MF, MI.getDebugLoc(), get(Opc))
1632 .add(Dest)
1633 .addReg(SrcReg, getKillRegState(isKill));
1634 if (ImplicitOp.getReg() != 0)
1635 MIB.add(ImplicitOp);
1636
1637 NewMI = addOffset(MIB, -Imm);
1638 break;
1639 }
1640
1641 case X86::SUB64ri8:
1642 case X86::SUB64ri32: {
1643 if (!MI.getOperand(2).isImm())
1644 return nullptr;
1645 int64_t Imm = MI.getOperand(2).getImm();
1646 if (!isInt<32>(-Imm))
1647 return nullptr;
1648
1649 assert(MI.getNumOperands() >= 3 && "Unknown sub instruction!")(static_cast <bool> (MI.getNumOperands() >= 3 &&
"Unknown sub instruction!") ? void (0) : __assert_fail ("MI.getNumOperands() >= 3 && \"Unknown sub instruction!\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 1649, __extension__ __PRETTY_FUNCTION__))
;
1650
1651 MachineInstrBuilder MIB = BuildMI(MF, MI.getDebugLoc(),
1652 get(X86::LEA64r)).add(Dest).add(Src);
1653 NewMI = addOffset(MIB, -Imm);
1654 break;
1655 }
1656
1657 case X86::VMOVDQU8Z128rmk:
1658 case X86::VMOVDQU8Z256rmk:
1659 case X86::VMOVDQU8Zrmk:
1660 case X86::VMOVDQU16Z128rmk:
1661 case X86::VMOVDQU16Z256rmk:
1662 case X86::VMOVDQU16Zrmk:
1663 case X86::VMOVDQU32Z128rmk: case X86::VMOVDQA32Z128rmk:
1664 case X86::VMOVDQU32Z256rmk: case X86::VMOVDQA32Z256rmk:
1665 case X86::VMOVDQU32Zrmk: case X86::VMOVDQA32Zrmk:
1666 case X86::VMOVDQU64Z128rmk: case X86::VMOVDQA64Z128rmk:
1667 case X86::VMOVDQU64Z256rmk: case X86::VMOVDQA64Z256rmk:
1668 case X86::VMOVDQU64Zrmk: case X86::VMOVDQA64Zrmk:
1669 case X86::VMOVUPDZ128rmk: case X86::VMOVAPDZ128rmk:
1670 case X86::VMOVUPDZ256rmk: case X86::VMOVAPDZ256rmk:
1671 case X86::VMOVUPDZrmk: case X86::VMOVAPDZrmk:
1672 case X86::VMOVUPSZ128rmk: case X86::VMOVAPSZ128rmk:
1673 case X86::VMOVUPSZ256rmk: case X86::VMOVAPSZ256rmk:
1674 case X86::VMOVUPSZrmk: case X86::VMOVAPSZrmk:
1675 case X86::VBROADCASTSDZ256rmk:
1676 case X86::VBROADCASTSDZrmk:
1677 case X86::VBROADCASTSSZ128rmk:
1678 case X86::VBROADCASTSSZ256rmk:
1679 case X86::VBROADCASTSSZrmk:
1680 case X86::VPBROADCASTDZ128rmk:
1681 case X86::VPBROADCASTDZ256rmk:
1682 case X86::VPBROADCASTDZrmk:
1683 case X86::VPBROADCASTQZ128rmk:
1684 case X86::VPBROADCASTQZ256rmk:
1685 case X86::VPBROADCASTQZrmk: {
1686 unsigned Opc;
1687 switch (MIOpc) {
1688 default: llvm_unreachable("Unreachable!")::llvm::llvm_unreachable_internal("Unreachable!", "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 1688)
;
1689 case X86::VMOVDQU8Z128rmk: Opc = X86::VPBLENDMBZ128rmk; break;
1690 case X86::VMOVDQU8Z256rmk: Opc = X86::VPBLENDMBZ256rmk; break;
1691 case X86::VMOVDQU8Zrmk: Opc = X86::VPBLENDMBZrmk; break;
1692 case X86::VMOVDQU16Z128rmk: Opc = X86::VPBLENDMWZ128rmk; break;
1693 case X86::VMOVDQU16Z256rmk: Opc = X86::VPBLENDMWZ256rmk; break;
1694 case X86::VMOVDQU16Zrmk: Opc = X86::VPBLENDMWZrmk; break;
1695 case X86::VMOVDQU32Z128rmk: Opc = X86::VPBLENDMDZ128rmk; break;
1696 case X86::VMOVDQU32Z256rmk: Opc = X86::VPBLENDMDZ256rmk; break;
1697 case X86::VMOVDQU32Zrmk: Opc = X86::VPBLENDMDZrmk; break;
1698 case X86::VMOVDQU64Z128rmk: Opc = X86::VPBLENDMQZ128rmk; break;
1699 case X86::VMOVDQU64Z256rmk: Opc = X86::VPBLENDMQZ256rmk; break;
1700 case X86::VMOVDQU64Zrmk: Opc = X86::VPBLENDMQZrmk; break;
1701 case X86::VMOVUPDZ128rmk: Opc = X86::VBLENDMPDZ128rmk; break;
1702 case X86::VMOVUPDZ256rmk: Opc = X86::VBLENDMPDZ256rmk; break;
1703 case X86::VMOVUPDZrmk: Opc = X86::VBLENDMPDZrmk; break;
1704 case X86::VMOVUPSZ128rmk: Opc = X86::VBLENDMPSZ128rmk; break;
1705 case X86::VMOVUPSZ256rmk: Opc = X86::VBLENDMPSZ256rmk; break;
1706 case X86::VMOVUPSZrmk: Opc = X86::VBLENDMPSZrmk; break;
1707 case X86::VMOVDQA32Z128rmk: Opc = X86::VPBLENDMDZ128rmk; break;
1708 case X86::VMOVDQA32Z256rmk: Opc = X86::VPBLENDMDZ256rmk; break;
1709 case X86::VMOVDQA32Zrmk: Opc = X86::VPBLENDMDZrmk; break;
1710 case X86::VMOVDQA64Z128rmk: Opc = X86::VPBLENDMQZ128rmk; break;
1711 case X86::VMOVDQA64Z256rmk: Opc = X86::VPBLENDMQZ256rmk; break;
1712 case X86::VMOVDQA64Zrmk: Opc = X86::VPBLENDMQZrmk; break;
1713 case X86::VMOVAPDZ128rmk: Opc = X86::VBLENDMPDZ128rmk; break;
1714 case X86::VMOVAPDZ256rmk: Opc = X86::VBLENDMPDZ256rmk; break;
1715 case X86::VMOVAPDZrmk: Opc = X86::VBLENDMPDZrmk; break;
1716 case X86::VMOVAPSZ128rmk: Opc = X86::VBLENDMPSZ128rmk; break;
1717 case X86::VMOVAPSZ256rmk: Opc = X86::VBLENDMPSZ256rmk; break;
1718 case X86::VMOVAPSZrmk: Opc = X86::VBLENDMPSZrmk; break;
1719 case X86::VBROADCASTSDZ256rmk: Opc = X86::VBLENDMPDZ256rmbk; break;
1720 case X86::VBROADCASTSDZrmk: Opc = X86::VBLENDMPDZrmbk; break;
1721 case X86::VBROADCASTSSZ128rmk: Opc = X86::VBLENDMPSZ128rmbk; break;
1722 case X86::VBROADCASTSSZ256rmk: Opc = X86::VBLENDMPSZ256rmbk; break;
1723 case X86::VBROADCASTSSZrmk: Opc = X86::VBLENDMPSZrmbk; break;
1724 case X86::VPBROADCASTDZ128rmk: Opc = X86::VPBLENDMDZ128rmbk; break;
1725 case X86::VPBROADCASTDZ256rmk: Opc = X86::VPBLENDMDZ256rmbk; break;
1726 case X86::VPBROADCASTDZrmk: Opc = X86::VPBLENDMDZrmbk; break;
1727 case X86::VPBROADCASTQZ128rmk: Opc = X86::VPBLENDMQZ128rmbk; break;
1728 case X86::VPBROADCASTQZ256rmk: Opc = X86::VPBLENDMQZ256rmbk; break;
1729 case X86::VPBROADCASTQZrmk: Opc = X86::VPBLENDMQZrmbk; break;
1730 }
1731
1732 NewMI = BuildMI(MF, MI.getDebugLoc(), get(Opc))
1733 .add(Dest)
1734 .add(MI.getOperand(2))
1735 .add(Src)
1736 .add(MI.getOperand(3))
1737 .add(MI.getOperand(4))
1738 .add(MI.getOperand(5))
1739 .add(MI.getOperand(6))
1740 .add(MI.getOperand(7));
1741 break;
1742 }
1743
1744 case X86::VMOVDQU8Z128rrk:
1745 case X86::VMOVDQU8Z256rrk:
1746 case X86::VMOVDQU8Zrrk:
1747 case X86::VMOVDQU16Z128rrk:
1748 case X86::VMOVDQU16Z256rrk:
1749 case X86::VMOVDQU16Zrrk:
1750 case X86::VMOVDQU32Z128rrk: case X86::VMOVDQA32Z128rrk:
1751 case X86::VMOVDQU32Z256rrk: case X86::VMOVDQA32Z256rrk:
1752 case X86::VMOVDQU32Zrrk: case X86::VMOVDQA32Zrrk:
1753 case X86::VMOVDQU64Z128rrk: case X86::VMOVDQA64Z128rrk:
1754 case X86::VMOVDQU64Z256rrk: case X86::VMOVDQA64Z256rrk:
1755 case X86::VMOVDQU64Zrrk: case X86::VMOVDQA64Zrrk:
1756 case X86::VMOVUPDZ128rrk: case X86::VMOVAPDZ128rrk:
1757 case X86::VMOVUPDZ256rrk: case X86::VMOVAPDZ256rrk:
1758 case X86::VMOVUPDZrrk: case X86::VMOVAPDZrrk:
1759 case X86::VMOVUPSZ128rrk: case X86::VMOVAPSZ128rrk:
1760 case X86::VMOVUPSZ256rrk: case X86::VMOVAPSZ256rrk:
1761 case X86::VMOVUPSZrrk: case X86::VMOVAPSZrrk: {
1762 unsigned Opc;
1763 switch (MIOpc) {
1764 default: llvm_unreachable("Unreachable!")::llvm::llvm_unreachable_internal("Unreachable!", "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 1764)
;
1765 case X86::VMOVDQU8Z128rrk: Opc = X86::VPBLENDMBZ128rrk; break;
1766 case X86::VMOVDQU8Z256rrk: Opc = X86::VPBLENDMBZ256rrk; break;
1767 case X86::VMOVDQU8Zrrk: Opc = X86::VPBLENDMBZrrk; break;
1768 case X86::VMOVDQU16Z128rrk: Opc = X86::VPBLENDMWZ128rrk; break;
1769 case X86::VMOVDQU16Z256rrk: Opc = X86::VPBLENDMWZ256rrk; break;
1770 case X86::VMOVDQU16Zrrk: Opc = X86::VPBLENDMWZrrk; break;
1771 case X86::VMOVDQU32Z128rrk: Opc = X86::VPBLENDMDZ128rrk; break;
1772 case X86::VMOVDQU32Z256rrk: Opc = X86::VPBLENDMDZ256rrk; break;
1773 case X86::VMOVDQU32Zrrk: Opc = X86::VPBLENDMDZrrk; break;
1774 case X86::VMOVDQU64Z128rrk: Opc = X86::VPBLENDMQZ128rrk; break;
1775 case X86::VMOVDQU64Z256rrk: Opc = X86::VPBLENDMQZ256rrk; break;
1776 case X86::VMOVDQU64Zrrk: Opc = X86::VPBLENDMQZrrk; break;
1777 case X86::VMOVUPDZ128rrk: Opc = X86::VBLENDMPDZ128rrk; break;
1778 case X86::VMOVUPDZ256rrk: Opc = X86::VBLENDMPDZ256rrk; break;
1779 case X86::VMOVUPDZrrk: Opc = X86::VBLENDMPDZrrk; break;
1780 case X86::VMOVUPSZ128rrk: Opc = X86::VBLENDMPSZ128rrk; break;
1781 case X86::VMOVUPSZ256rrk: Opc = X86::VBLENDMPSZ256rrk; break;
1782 case X86::VMOVUPSZrrk: Opc = X86::VBLENDMPSZrrk; break;
1783 case X86::VMOVDQA32Z128rrk: Opc = X86::VPBLENDMDZ128rrk; break;
1784 case X86::VMOVDQA32Z256rrk: Opc = X86::VPBLENDMDZ256rrk; break;
1785 case X86::VMOVDQA32Zrrk: Opc = X86::VPBLENDMDZrrk; break;
1786 case X86::VMOVDQA64Z128rrk: Opc = X86::VPBLENDMQZ128rrk; break;
1787 case X86::VMOVDQA64Z256rrk: Opc = X86::VPBLENDMQZ256rrk; break;
1788 case X86::VMOVDQA64Zrrk: Opc = X86::VPBLENDMQZrrk; break;
1789 case X86::VMOVAPDZ128rrk: Opc = X86::VBLENDMPDZ128rrk; break;
1790 case X86::VMOVAPDZ256rrk: Opc = X86::VBLENDMPDZ256rrk; break;
1791 case X86::VMOVAPDZrrk: Opc = X86::VBLENDMPDZrrk; break;
1792 case X86::VMOVAPSZ128rrk: Opc = X86::VBLENDMPSZ128rrk; break;
1793 case X86::VMOVAPSZ256rrk: Opc = X86::VBLENDMPSZ256rrk; break;
1794 case X86::VMOVAPSZrrk: Opc = X86::VBLENDMPSZrrk; break;
1795 }
1796
1797 NewMI = BuildMI(MF, MI.getDebugLoc(), get(Opc))
1798 .add(Dest)
1799 .add(MI.getOperand(2))
1800 .add(Src)
1801 .add(MI.getOperand(3));
1802 break;
1803 }
1804 }
1805
1806 if (!NewMI) return nullptr;
1807
1808 if (LV) { // Update live variables
1809 if (Src.isKill())
1810 LV->replaceKillInstruction(Src.getReg(), MI, *NewMI);
1811 if (Dest.isDead())
1812 LV->replaceKillInstruction(Dest.getReg(), MI, *NewMI);
1813 }
1814
1815 MFI->insert(MI.getIterator(), NewMI); // Insert the new inst
1816 return NewMI;
1817}
1818
1819/// This determines which of three possible cases of a three source commute
1820/// the source indexes correspond to taking into account any mask operands.
1821/// All prevents commuting a passthru operand. Returns -1 if the commute isn't
1822/// possible.
1823/// Case 0 - Possible to commute the first and second operands.
1824/// Case 1 - Possible to commute the first and third operands.
1825/// Case 2 - Possible to commute the second and third operands.
1826static unsigned getThreeSrcCommuteCase(uint64_t TSFlags, unsigned SrcOpIdx1,
1827 unsigned SrcOpIdx2) {
1828 // Put the lowest index to SrcOpIdx1 to simplify the checks below.
1829 if (SrcOpIdx1 > SrcOpIdx2)
1830 std::swap(SrcOpIdx1, SrcOpIdx2);
1831
1832 unsigned Op1 = 1, Op2 = 2, Op3 = 3;
1833 if (X86II::isKMasked(TSFlags)) {
1834 Op2++;
1835 Op3++;
1836 }
1837
1838 if (SrcOpIdx1 == Op1 && SrcOpIdx2 == Op2)
1839 return 0;
1840 if (SrcOpIdx1 == Op1 && SrcOpIdx2 == Op3)
1841 return 1;
1842 if (SrcOpIdx1 == Op2 && SrcOpIdx2 == Op3)
1843 return 2;
1844 llvm_unreachable("Unknown three src commute case.")::llvm::llvm_unreachable_internal("Unknown three src commute case."
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 1844)
;
1845}
1846
1847unsigned X86InstrInfo::getFMA3OpcodeToCommuteOperands(
1848 const MachineInstr &MI, unsigned SrcOpIdx1, unsigned SrcOpIdx2,
1849 const X86InstrFMA3Group &FMA3Group) const {
1850
1851 unsigned Opc = MI.getOpcode();
1852
1853 // TODO: Commuting the 1st operand of FMA*_Int requires some additional
1854 // analysis. The commute optimization is legal only if all users of FMA*_Int
1855 // use only the lowest element of the FMA*_Int instruction. Such analysis are
1856 // not implemented yet. So, just return 0 in that case.
1857 // When such analysis are available this place will be the right place for
1858 // calling it.
1859 assert(!(FMA3Group.isIntrinsic() && (SrcOpIdx1 == 1 || SrcOpIdx2 == 1)) &&(static_cast <bool> (!(FMA3Group.isIntrinsic() &&
(SrcOpIdx1 == 1 || SrcOpIdx2 == 1)) && "Intrinsic instructions can't commute operand 1"
) ? void (0) : __assert_fail ("!(FMA3Group.isIntrinsic() && (SrcOpIdx1 == 1 || SrcOpIdx2 == 1)) && \"Intrinsic instructions can't commute operand 1\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 1860, __extension__ __PRETTY_FUNCTION__))
1860 "Intrinsic instructions can't commute operand 1")(static_cast <bool> (!(FMA3Group.isIntrinsic() &&
(SrcOpIdx1 == 1 || SrcOpIdx2 == 1)) && "Intrinsic instructions can't commute operand 1"
) ? void (0) : __assert_fail ("!(FMA3Group.isIntrinsic() && (SrcOpIdx1 == 1 || SrcOpIdx2 == 1)) && \"Intrinsic instructions can't commute operand 1\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 1860, __extension__ __PRETTY_FUNCTION__))
;
1861
1862 // Determine which case this commute is or if it can't be done.
1863 unsigned Case = getThreeSrcCommuteCase(MI.getDesc().TSFlags, SrcOpIdx1,
1864 SrcOpIdx2);
1865 assert(Case < 3 && "Unexpected case number!")(static_cast <bool> (Case < 3 && "Unexpected case number!"
) ? void (0) : __assert_fail ("Case < 3 && \"Unexpected case number!\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 1865, __extension__ __PRETTY_FUNCTION__))
;
1866
1867 // Define the FMA forms mapping array that helps to map input FMA form
1868 // to output FMA form to preserve the operation semantics after
1869 // commuting the operands.
1870 const unsigned Form132Index = 0;
1871 const unsigned Form213Index = 1;
1872 const unsigned Form231Index = 2;
1873 static const unsigned FormMapping[][3] = {
1874 // 0: SrcOpIdx1 == 1 && SrcOpIdx2 == 2;
1875 // FMA132 A, C, b; ==> FMA231 C, A, b;
1876 // FMA213 B, A, c; ==> FMA213 A, B, c;
1877 // FMA231 C, A, b; ==> FMA132 A, C, b;
1878 { Form231Index, Form213Index, Form132Index },
1879 // 1: SrcOpIdx1 == 1 && SrcOpIdx2 == 3;
1880 // FMA132 A, c, B; ==> FMA132 B, c, A;
1881 // FMA213 B, a, C; ==> FMA231 C, a, B;
1882 // FMA231 C, a, B; ==> FMA213 B, a, C;
1883 { Form132Index, Form231Index, Form213Index },
1884 // 2: SrcOpIdx1 == 2 && SrcOpIdx2 == 3;
1885 // FMA132 a, C, B; ==> FMA213 a, B, C;
1886 // FMA213 b, A, C; ==> FMA132 b, C, A;
1887 // FMA231 c, A, B; ==> FMA231 c, B, A;
1888 { Form213Index, Form132Index, Form231Index }
1889 };
1890
1891 unsigned FMAForms[3];
1892 FMAForms[0] = FMA3Group.get132Opcode();
1893 FMAForms[1] = FMA3Group.get213Opcode();
1894 FMAForms[2] = FMA3Group.get231Opcode();
1895 unsigned FormIndex;
1896 for (FormIndex = 0; FormIndex < 3; FormIndex++)
1897 if (Opc == FMAForms[FormIndex])
1898 break;
1899
1900 // Everything is ready, just adjust the FMA opcode and return it.
1901 FormIndex = FormMapping[Case][FormIndex];
1902 return FMAForms[FormIndex];
1903}
1904
1905static void commuteVPTERNLOG(MachineInstr &MI, unsigned SrcOpIdx1,
1906 unsigned SrcOpIdx2) {
1907 // Determine which case this commute is or if it can't be done.
1908 unsigned Case = getThreeSrcCommuteCase(MI.getDesc().TSFlags, SrcOpIdx1,
1909 SrcOpIdx2);
1910 assert(Case < 3 && "Unexpected case value!")(static_cast <bool> (Case < 3 && "Unexpected case value!"
) ? void (0) : __assert_fail ("Case < 3 && \"Unexpected case value!\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 1910, __extension__ __PRETTY_FUNCTION__))
;
1911
1912 // For each case we need to swap two pairs of bits in the final immediate.
1913 static const uint8_t SwapMasks[3][4] = {
1914 { 0x04, 0x10, 0x08, 0x20 }, // Swap bits 2/4 and 3/5.
1915 { 0x02, 0x10, 0x08, 0x40 }, // Swap bits 1/4 and 3/6.
1916 { 0x02, 0x04, 0x20, 0x40 }, // Swap bits 1/2 and 5/6.
1917 };
1918
1919 uint8_t Imm = MI.getOperand(MI.getNumOperands()-1).getImm();
1920 // Clear out the bits we are swapping.
1921 uint8_t NewImm = Imm & ~(SwapMasks[Case][0] | SwapMasks[Case][1] |
1922 SwapMasks[Case][2] | SwapMasks[Case][3]);
1923 // If the immediate had a bit of the pair set, then set the opposite bit.
1924 if (Imm & SwapMasks[Case][0]) NewImm |= SwapMasks[Case][1];
1925 if (Imm & SwapMasks[Case][1]) NewImm |= SwapMasks[Case][0];
1926 if (Imm & SwapMasks[Case][2]) NewImm |= SwapMasks[Case][3];
1927 if (Imm & SwapMasks[Case][3]) NewImm |= SwapMasks[Case][2];
1928 MI.getOperand(MI.getNumOperands()-1).setImm(NewImm);
1929}
1930
1931// Returns true if this is a VPERMI2 or VPERMT2 instruction that can be
1932// commuted.
1933static bool isCommutableVPERMV3Instruction(unsigned Opcode) {
1934#define VPERM_CASES(Suffix) \
1935 case X86::VPERMI2##Suffix##128rr: case X86::VPERMT2##Suffix##128rr: \
1936 case X86::VPERMI2##Suffix##256rr: case X86::VPERMT2##Suffix##256rr: \
1937 case X86::VPERMI2##Suffix##rr: case X86::VPERMT2##Suffix##rr: \
1938 case X86::VPERMI2##Suffix##128rm: case X86::VPERMT2##Suffix##128rm: \
1939 case X86::VPERMI2##Suffix##256rm: case X86::VPERMT2##Suffix##256rm: \
1940 case X86::VPERMI2##Suffix##rm: case X86::VPERMT2##Suffix##rm: \
1941 case X86::VPERMI2##Suffix##128rrkz: case X86::VPERMT2##Suffix##128rrkz: \
1942 case X86::VPERMI2##Suffix##256rrkz: case X86::VPERMT2##Suffix##256rrkz: \
1943 case X86::VPERMI2##Suffix##rrkz: case X86::VPERMT2##Suffix##rrkz: \
1944 case X86::VPERMI2##Suffix##128rmkz: case X86::VPERMT2##Suffix##128rmkz: \
1945 case X86::VPERMI2##Suffix##256rmkz: case X86::VPERMT2##Suffix##256rmkz: \
1946 case X86::VPERMI2##Suffix##rmkz: case X86::VPERMT2##Suffix##rmkz:
1947
1948#define VPERM_CASES_BROADCAST(Suffix) \
1949 VPERM_CASES(Suffix) \
1950 case X86::VPERMI2##Suffix##128rmb: case X86::VPERMT2##Suffix##128rmb: \
1951 case X86::VPERMI2##Suffix##256rmb: case X86::VPERMT2##Suffix##256rmb: \
1952 case X86::VPERMI2##Suffix##rmb: case X86::VPERMT2##Suffix##rmb: \
1953 case X86::VPERMI2##Suffix##128rmbkz: case X86::VPERMT2##Suffix##128rmbkz: \
1954 case X86::VPERMI2##Suffix##256rmbkz: case X86::VPERMT2##Suffix##256rmbkz: \
1955 case X86::VPERMI2##Suffix##rmbkz: case X86::VPERMT2##Suffix##rmbkz:
1956
1957 switch (Opcode) {
1958 default: return false;
1959 VPERM_CASES(B)
1960 VPERM_CASES_BROADCAST(D)
1961 VPERM_CASES_BROADCAST(PD)
1962 VPERM_CASES_BROADCAST(PS)
1963 VPERM_CASES_BROADCAST(Q)
1964 VPERM_CASES(W)
1965 return true;
1966 }
1967#undef VPERM_CASES_BROADCAST
1968#undef VPERM_CASES
1969}
1970
1971// Returns commuted opcode for VPERMI2 and VPERMT2 instructions by switching
1972// from the I opcode to the T opcode and vice versa.
1973static unsigned getCommutedVPERMV3Opcode(unsigned Opcode) {
1974#define VPERM_CASES(Orig, New) \
1975 case X86::Orig##128rr: return X86::New##128rr; \
1976 case X86::Orig##128rrkz: return X86::New##128rrkz; \
1977 case X86::Orig##128rm: return X86::New##128rm; \
1978 case X86::Orig##128rmkz: return X86::New##128rmkz; \
1979 case X86::Orig##256rr: return X86::New##256rr; \
1980 case X86::Orig##256rrkz: return X86::New##256rrkz; \
1981 case X86::Orig##256rm: return X86::New##256rm; \
1982 case X86::Orig##256rmkz: return X86::New##256rmkz; \
1983 case X86::Orig##rr: return X86::New##rr; \
1984 case X86::Orig##rrkz: return X86::New##rrkz; \
1985 case X86::Orig##rm: return X86::New##rm; \
1986 case X86::Orig##rmkz: return X86::New##rmkz;
1987
1988#define VPERM_CASES_BROADCAST(Orig, New) \
1989 VPERM_CASES(Orig, New) \
1990 case X86::Orig##128rmb: return X86::New##128rmb; \
1991 case X86::Orig##128rmbkz: return X86::New##128rmbkz; \
1992 case X86::Orig##256rmb: return X86::New##256rmb; \
1993 case X86::Orig##256rmbkz: return X86::New##256rmbkz; \
1994 case X86::Orig##rmb: return X86::New##rmb; \
1995 case X86::Orig##rmbkz: return X86::New##rmbkz;
1996
1997 switch (Opcode) {
1998 VPERM_CASES(VPERMI2B, VPERMT2B)
1999 VPERM_CASES_BROADCAST(VPERMI2D, VPERMT2D)
2000 VPERM_CASES_BROADCAST(VPERMI2PD, VPERMT2PD)
2001 VPERM_CASES_BROADCAST(VPERMI2PS, VPERMT2PS)
2002 VPERM_CASES_BROADCAST(VPERMI2Q, VPERMT2Q)
2003 VPERM_CASES(VPERMI2W, VPERMT2W)
2004 VPERM_CASES(VPERMT2B, VPERMI2B)
2005 VPERM_CASES_BROADCAST(VPERMT2D, VPERMI2D)
2006 VPERM_CASES_BROADCAST(VPERMT2PD, VPERMI2PD)
2007 VPERM_CASES_BROADCAST(VPERMT2PS, VPERMI2PS)
2008 VPERM_CASES_BROADCAST(VPERMT2Q, VPERMI2Q)
2009 VPERM_CASES(VPERMT2W, VPERMI2W)
2010 }
2011
2012 llvm_unreachable("Unreachable!")::llvm::llvm_unreachable_internal("Unreachable!", "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 2012)
;
2013#undef VPERM_CASES_BROADCAST
2014#undef VPERM_CASES
2015}
2016
2017MachineInstr *X86InstrInfo::commuteInstructionImpl(MachineInstr &MI, bool NewMI,
2018 unsigned OpIdx1,
2019 unsigned OpIdx2) const {
2020 auto cloneIfNew = [NewMI](MachineInstr &MI) -> MachineInstr & {
2021 if (NewMI)
2022 return *MI.getParent()->getParent()->CloneMachineInstr(&MI);
2023 return MI;
2024 };
2025
2026 switch (MI.getOpcode()) {
2027 case X86::SHRD16rri8: // A = SHRD16rri8 B, C, I -> A = SHLD16rri8 C, B, (16-I)
2028 case X86::SHLD16rri8: // A = SHLD16rri8 B, C, I -> A = SHRD16rri8 C, B, (16-I)
2029 case X86::SHRD32rri8: // A = SHRD32rri8 B, C, I -> A = SHLD32rri8 C, B, (32-I)
2030 case X86::SHLD32rri8: // A = SHLD32rri8 B, C, I -> A = SHRD32rri8 C, B, (32-I)
2031 case X86::SHRD64rri8: // A = SHRD64rri8 B, C, I -> A = SHLD64rri8 C, B, (64-I)
2032 case X86::SHLD64rri8:{// A = SHLD64rri8 B, C, I -> A = SHRD64rri8 C, B, (64-I)
2033 unsigned Opc;
2034 unsigned Size;
2035 switch (MI.getOpcode()) {
2036 default: llvm_unreachable("Unreachable!")::llvm::llvm_unreachable_internal("Unreachable!", "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 2036)
;
2037 case X86::SHRD16rri8: Size = 16; Opc = X86::SHLD16rri8; break;
2038 case X86::SHLD16rri8: Size = 16; Opc = X86::SHRD16rri8; break;
2039 case X86::SHRD32rri8: Size = 32; Opc = X86::SHLD32rri8; break;
2040 case X86::SHLD32rri8: Size = 32; Opc = X86::SHRD32rri8; break;
2041 case X86::SHRD64rri8: Size = 64; Opc = X86::SHLD64rri8; break;
2042 case X86::SHLD64rri8: Size = 64; Opc = X86::SHRD64rri8; break;
2043 }
2044 unsigned Amt = MI.getOperand(3).getImm();
2045 auto &WorkingMI = cloneIfNew(MI);
2046 WorkingMI.setDesc(get(Opc));
2047 WorkingMI.getOperand(3).setImm(Size - Amt);
2048 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
2049 OpIdx1, OpIdx2);
2050 }
2051 case X86::PFSUBrr:
2052 case X86::PFSUBRrr: {
2053 // PFSUB x, y: x = x - y
2054 // PFSUBR x, y: x = y - x
2055 unsigned Opc =
2056 (X86::PFSUBRrr == MI.getOpcode() ? X86::PFSUBrr : X86::PFSUBRrr);
2057 auto &WorkingMI = cloneIfNew(MI);
2058 WorkingMI.setDesc(get(Opc));
2059 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
2060 OpIdx1, OpIdx2);
2061 }
2062 case X86::BLENDPDrri:
2063 case X86::BLENDPSrri:
2064 case X86::VBLENDPDrri:
2065 case X86::VBLENDPSrri:
2066 // If we're optimizing for size, try to use MOVSD/MOVSS.
2067 if (MI.getParent()->getParent()->getFunction().hasOptSize()) {
2068 unsigned Mask, Opc;
2069 switch (MI.getOpcode()) {
2070 default: llvm_unreachable("Unreachable!")::llvm::llvm_unreachable_internal("Unreachable!", "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 2070)
;
2071 case X86::BLENDPDrri: Opc = X86::MOVSDrr; Mask = 0x03; break;
2072 case X86::BLENDPSrri: Opc = X86::MOVSSrr; Mask = 0x0F; break;
2073 case X86::VBLENDPDrri: Opc = X86::VMOVSDrr; Mask = 0x03; break;
2074 case X86::VBLENDPSrri: Opc = X86::VMOVSSrr; Mask = 0x0F; break;
2075 }
2076 if ((MI.getOperand(3).getImm() ^ Mask) == 1) {
2077 auto &WorkingMI = cloneIfNew(MI);
2078 WorkingMI.setDesc(get(Opc));
2079 WorkingMI.RemoveOperand(3);
2080 return TargetInstrInfo::commuteInstructionImpl(WorkingMI,
2081 /*NewMI=*/false,
2082 OpIdx1, OpIdx2);
2083 }
2084 }
2085 LLVM_FALLTHROUGH[[gnu::fallthrough]];
2086 case X86::PBLENDWrri:
2087 case X86::VBLENDPDYrri:
2088 case X86::VBLENDPSYrri:
2089 case X86::VPBLENDDrri:
2090 case X86::VPBLENDWrri:
2091 case X86::VPBLENDDYrri:
2092 case X86::VPBLENDWYrri:{
2093 int8_t Mask;
2094 switch (MI.getOpcode()) {
2095 default: llvm_unreachable("Unreachable!")::llvm::llvm_unreachable_internal("Unreachable!", "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 2095)
;
2096 case X86::BLENDPDrri: Mask = (int8_t)0x03; break;
2097 case X86::BLENDPSrri: Mask = (int8_t)0x0F; break;
2098 case X86::PBLENDWrri: Mask = (int8_t)0xFF; break;
2099 case X86::VBLENDPDrri: Mask = (int8_t)0x03; break;
2100 case X86::VBLENDPSrri: Mask = (int8_t)0x0F; break;
2101 case X86::VBLENDPDYrri: Mask = (int8_t)0x0F; break;
2102 case X86::VBLENDPSYrri: Mask = (int8_t)0xFF; break;
2103 case X86::VPBLENDDrri: Mask = (int8_t)0x0F; break;
2104 case X86::VPBLENDWrri: Mask = (int8_t)0xFF; break;
2105 case X86::VPBLENDDYrri: Mask = (int8_t)0xFF; break;
2106 case X86::VPBLENDWYrri: Mask = (int8_t)0xFF; break;
2107 }
2108 // Only the least significant bits of Imm are used.
2109 // Using int8_t to ensure it will be sign extended to the int64_t that
2110 // setImm takes in order to match isel behavior.
2111 int8_t Imm = MI.getOperand(3).getImm() & Mask;
2112 auto &WorkingMI = cloneIfNew(MI);
2113 WorkingMI.getOperand(3).setImm(Mask ^ Imm);
2114 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
2115 OpIdx1, OpIdx2);
2116 }
2117 case X86::INSERTPSrr:
2118 case X86::VINSERTPSrr:
2119 case X86::VINSERTPSZrr: {
2120 unsigned Imm = MI.getOperand(MI.getNumOperands() - 1).getImm();
2121 unsigned ZMask = Imm & 15;
2122 unsigned DstIdx = (Imm >> 4) & 3;
2123 unsigned SrcIdx = (Imm >> 6) & 3;
2124
2125 // We can commute insertps if we zero 2 of the elements, the insertion is
2126 // "inline" and we don't override the insertion with a zero.
2127 if (DstIdx == SrcIdx && (ZMask & (1 << DstIdx)) == 0 &&
2128 countPopulation(ZMask) == 2) {
2129 unsigned AltIdx = findFirstSet((ZMask | (1 << DstIdx)) ^ 15);
2130 assert(AltIdx < 4 && "Illegal insertion index")(static_cast <bool> (AltIdx < 4 && "Illegal insertion index"
) ? void (0) : __assert_fail ("AltIdx < 4 && \"Illegal insertion index\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 2130, __extension__ __PRETTY_FUNCTION__))
;
2131 unsigned AltImm = (AltIdx << 6) | (AltIdx << 4) | ZMask;
2132 auto &WorkingMI = cloneIfNew(MI);
2133 WorkingMI.getOperand(MI.getNumOperands() - 1).setImm(AltImm);
2134 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
2135 OpIdx1, OpIdx2);
2136 }
2137 return nullptr;
2138 }
2139 case X86::MOVSDrr:
2140 case X86::MOVSSrr:
2141 case X86::VMOVSDrr:
2142 case X86::VMOVSSrr:{
2143 // On SSE41 or later we can commute a MOVSS/MOVSD to a BLENDPS/BLENDPD.
2144 if (Subtarget.hasSSE41()) {
2145 unsigned Mask, Opc;
2146 switch (MI.getOpcode()) {
2147 default: llvm_unreachable("Unreachable!")::llvm::llvm_unreachable_internal("Unreachable!", "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 2147)
;
2148 case X86::MOVSDrr: Opc = X86::BLENDPDrri; Mask = 0x02; break;
2149 case X86::MOVSSrr: Opc = X86::BLENDPSrri; Mask = 0x0E; break;
2150 case X86::VMOVSDrr: Opc = X86::VBLENDPDrri; Mask = 0x02; break;
2151 case X86::VMOVSSrr: Opc = X86::VBLENDPSrri; Mask = 0x0E; break;
2152 }
2153
2154 auto &WorkingMI = cloneIfNew(MI);
2155 WorkingMI.setDesc(get(Opc));
2156 WorkingMI.addOperand(MachineOperand::CreateImm(Mask));
2157 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
2158 OpIdx1, OpIdx2);
2159 }
2160
2161 // Convert to SHUFPD.
2162 assert(MI.getOpcode() == X86::MOVSDrr &&(static_cast <bool> (MI.getOpcode() == X86::MOVSDrr &&
"Can only commute MOVSDrr without SSE4.1") ? void (0) : __assert_fail
("MI.getOpcode() == X86::MOVSDrr && \"Can only commute MOVSDrr without SSE4.1\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 2163, __extension__ __PRETTY_FUNCTION__))
2163 "Can only commute MOVSDrr without SSE4.1")(static_cast <bool> (MI.getOpcode() == X86::MOVSDrr &&
"Can only commute MOVSDrr without SSE4.1") ? void (0) : __assert_fail
("MI.getOpcode() == X86::MOVSDrr && \"Can only commute MOVSDrr without SSE4.1\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 2163, __extension__ __PRETTY_FUNCTION__))
;
2164
2165 auto &WorkingMI = cloneIfNew(MI);
2166 WorkingMI.setDesc(get(X86::SHUFPDrri));
2167 WorkingMI.addOperand(MachineOperand::CreateImm(0x02));
2168 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
2169 OpIdx1, OpIdx2);
2170 }
2171 case X86::SHUFPDrri: {
2172 // Commute to MOVSD.
2173 assert(MI.getOperand(3).getImm() == 0x02 && "Unexpected immediate!")(static_cast <bool> (MI.getOperand(3).getImm() == 0x02 &&
"Unexpected immediate!") ? void (0) : __assert_fail ("MI.getOperand(3).getImm() == 0x02 && \"Unexpected immediate!\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 2173, __extension__ __PRETTY_FUNCTION__))
;
2174 auto &WorkingMI = cloneIfNew(MI);
2175 WorkingMI.setDesc(get(X86::MOVSDrr));
2176 WorkingMI.RemoveOperand(3);
2177 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
2178 OpIdx1, OpIdx2);
2179 }
2180 case X86::PCLMULQDQrr:
2181 case X86::VPCLMULQDQrr:
2182 case X86::VPCLMULQDQYrr:
2183 case X86::VPCLMULQDQZrr:
2184 case X86::VPCLMULQDQZ128rr:
2185 case X86::VPCLMULQDQZ256rr: {
2186 // SRC1 64bits = Imm[0] ? SRC1[127:64] : SRC1[63:0]
2187 // SRC2 64bits = Imm[4] ? SRC2[127:64] : SRC2[63:0]
2188 unsigned Imm = MI.getOperand(3).getImm();
2189 unsigned Src1Hi = Imm & 0x01;
2190 unsigned Src2Hi = Imm & 0x10;
2191 auto &WorkingMI = cloneIfNew(MI);
2192 WorkingMI.getOperand(3).setImm((Src1Hi << 4) | (Src2Hi >> 4));
2193 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
2194 OpIdx1, OpIdx2);
2195 }
2196 case X86::VPCMPBZ128rri: case X86::VPCMPUBZ128rri:
2197 case X86::VPCMPBZ256rri: case X86::VPCMPUBZ256rri:
2198 case X86::VPCMPBZrri: case X86::VPCMPUBZrri:
2199 case X86::VPCMPDZ128rri: case X86::VPCMPUDZ128rri:
2200 case X86::VPCMPDZ256rri: case X86::VPCMPUDZ256rri:
2201 case X86::VPCMPDZrri: case X86::VPCMPUDZrri:
2202 case X86::VPCMPQZ128rri: case X86::VPCMPUQZ128rri:
2203 case X86::VPCMPQZ256rri: case X86::VPCMPUQZ256rri:
2204 case X86::VPCMPQZrri: case X86::VPCMPUQZrri:
2205 case X86::VPCMPWZ128rri: case X86::VPCMPUWZ128rri:
2206 case X86::VPCMPWZ256rri: case X86::VPCMPUWZ256rri:
2207 case X86::VPCMPWZrri: case X86::VPCMPUWZrri:
2208 case X86::VPCMPBZ128rrik: case X86::VPCMPUBZ128rrik:
2209 case X86::VPCMPBZ256rrik: case X86::VPCMPUBZ256rrik:
2210 case X86::VPCMPBZrrik: case X86::VPCMPUBZrrik:
2211 case X86::VPCMPDZ128rrik: case X86::VPCMPUDZ128rrik:
2212 case X86::VPCMPDZ256rrik: case X86::VPCMPUDZ256rrik:
2213 case X86::VPCMPDZrrik: case X86::VPCMPUDZrrik:
2214 case X86::VPCMPQZ128rrik: case X86::VPCMPUQZ128rrik:
2215 case X86::VPCMPQZ256rrik: case X86::VPCMPUQZ256rrik:
2216 case X86::VPCMPQZrrik: case X86::VPCMPUQZrrik:
2217 case X86::VPCMPWZ128rrik: case X86::VPCMPUWZ128rrik:
2218 case X86::VPCMPWZ256rrik: case X86::VPCMPUWZ256rrik:
2219 case X86::VPCMPWZrrik: case X86::VPCMPUWZrrik: {
2220 // Flip comparison mode immediate (if necessary).
2221 unsigned Imm = MI.getOperand(MI.getNumOperands() - 1).getImm() & 0x7;
2222 Imm = X86::getSwappedVPCMPImm(Imm);
2223 auto &WorkingMI = cloneIfNew(MI);
2224 WorkingMI.getOperand(MI.getNumOperands() - 1).setImm(Imm);
2225 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
2226 OpIdx1, OpIdx2);
2227 }
2228 case X86::VPCOMBri: case X86::VPCOMUBri:
2229 case X86::VPCOMDri: case X86::VPCOMUDri:
2230 case X86::VPCOMQri: case X86::VPCOMUQri:
2231 case X86::VPCOMWri: case X86::VPCOMUWri: {
2232 // Flip comparison mode immediate (if necessary).
2233 unsigned Imm = MI.getOperand(3).getImm() & 0x7;
2234 Imm = X86::getSwappedVPCOMImm(Imm);
2235 auto &WorkingMI = cloneIfNew(MI);
2236 WorkingMI.getOperand(3).setImm(Imm);
2237 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
2238 OpIdx1, OpIdx2);
2239 }
2240 case X86::VCMPSDZrr:
2241 case X86::VCMPSSZrr:
2242 case X86::VCMPPDZrri:
2243 case X86::VCMPPSZrri:
2244 case X86::VCMPSHZrr:
2245 case X86::VCMPPHZrri:
2246 case X86::VCMPPHZ128rri:
2247 case X86::VCMPPHZ256rri:
2248 case X86::VCMPPDZ128rri:
2249 case X86::VCMPPSZ128rri:
2250 case X86::VCMPPDZ256rri:
2251 case X86::VCMPPSZ256rri:
2252 case X86::VCMPPDZrrik:
2253 case X86::VCMPPSZrrik:
2254 case X86::VCMPPDZ128rrik:
2255 case X86::VCMPPSZ128rrik:
2256 case X86::VCMPPDZ256rrik:
2257 case X86::VCMPPSZ256rrik: {
2258 unsigned Imm =
2259 MI.getOperand(MI.getNumExplicitOperands() - 1).getImm() & 0x1f;
2260 Imm = X86::getSwappedVCMPImm(Imm);
2261 auto &WorkingMI = cloneIfNew(MI);
2262 WorkingMI.getOperand(MI.getNumExplicitOperands() - 1).setImm(Imm);
2263 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
2264 OpIdx1, OpIdx2);
2265 }
2266 case X86::VPERM2F128rr:
2267 case X86::VPERM2I128rr: {
2268 // Flip permute source immediate.
2269 // Imm & 0x02: lo = if set, select Op1.lo/hi else Op0.lo/hi.
2270 // Imm & 0x20: hi = if set, select Op1.lo/hi else Op0.lo/hi.
2271 int8_t Imm = MI.getOperand(3).getImm() & 0xFF;
2272 auto &WorkingMI = cloneIfNew(MI);
2273 WorkingMI.getOperand(3).setImm(Imm ^ 0x22);
2274 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
2275 OpIdx1, OpIdx2);
2276 }
2277 case X86::MOVHLPSrr:
2278 case X86::UNPCKHPDrr:
2279 case X86::VMOVHLPSrr:
2280 case X86::VUNPCKHPDrr:
2281 case X86::VMOVHLPSZrr:
2282 case X86::VUNPCKHPDZ128rr: {
2283 assert(Subtarget.hasSSE2() && "Commuting MOVHLP/UNPCKHPD requires SSE2!")(static_cast <bool> (Subtarget.hasSSE2() && "Commuting MOVHLP/UNPCKHPD requires SSE2!"
) ? void (0) : __assert_fail ("Subtarget.hasSSE2() && \"Commuting MOVHLP/UNPCKHPD requires SSE2!\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 2283, __extension__ __PRETTY_FUNCTION__))
;
2284
2285 unsigned Opc = MI.getOpcode();
2286 switch (Opc) {
2287 default: llvm_unreachable("Unreachable!")::llvm::llvm_unreachable_internal("Unreachable!", "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 2287)
;
2288 case X86::MOVHLPSrr: Opc = X86::UNPCKHPDrr; break;
2289 case X86::UNPCKHPDrr: Opc = X86::MOVHLPSrr; break;
2290 case X86::VMOVHLPSrr: Opc = X86::VUNPCKHPDrr; break;
2291 case X86::VUNPCKHPDrr: Opc = X86::VMOVHLPSrr; break;
2292 case X86::VMOVHLPSZrr: Opc = X86::VUNPCKHPDZ128rr; break;
2293 case X86::VUNPCKHPDZ128rr: Opc = X86::VMOVHLPSZrr; break;
2294 }
2295 auto &WorkingMI = cloneIfNew(MI);
2296 WorkingMI.setDesc(get(Opc));
2297 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
2298 OpIdx1, OpIdx2);
2299 }
2300 case X86::CMOV16rr: case X86::CMOV32rr: case X86::CMOV64rr: {
2301 auto &WorkingMI = cloneIfNew(MI);
2302 unsigned OpNo = MI.getDesc().getNumOperands() - 1;
2303 X86::CondCode CC = static_cast<X86::CondCode>(MI.getOperand(OpNo).getImm());
2304 WorkingMI.getOperand(OpNo).setImm(X86::GetOppositeBranchCondition(CC));
2305 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
2306 OpIdx1, OpIdx2);
2307 }
2308 case X86::VPTERNLOGDZrri: case X86::VPTERNLOGDZrmi:
2309 case X86::VPTERNLOGDZ128rri: case X86::VPTERNLOGDZ128rmi:
2310 case X86::VPTERNLOGDZ256rri: case X86::VPTERNLOGDZ256rmi:
2311 case X86::VPTERNLOGQZrri: case X86::VPTERNLOGQZrmi:
2312 case X86::VPTERNLOGQZ128rri: case X86::VPTERNLOGQZ128rmi:
2313 case X86::VPTERNLOGQZ256rri: case X86::VPTERNLOGQZ256rmi:
2314 case X86::VPTERNLOGDZrrik:
2315 case X86::VPTERNLOGDZ128rrik:
2316 case X86::VPTERNLOGDZ256rrik:
2317 case X86::VPTERNLOGQZrrik:
2318 case X86::VPTERNLOGQZ128rrik:
2319 case X86::VPTERNLOGQZ256rrik:
2320 case X86::VPTERNLOGDZrrikz: case X86::VPTERNLOGDZrmikz:
2321 case X86::VPTERNLOGDZ128rrikz: case X86::VPTERNLOGDZ128rmikz:
2322 case X86::VPTERNLOGDZ256rrikz: case X86::VPTERNLOGDZ256rmikz:
2323 case X86::VPTERNLOGQZrrikz: case X86::VPTERNLOGQZrmikz:
2324 case X86::VPTERNLOGQZ128rrikz: case X86::VPTERNLOGQZ128rmikz:
2325 case X86::VPTERNLOGQZ256rrikz: case X86::VPTERNLOGQZ256rmikz:
2326 case X86::VPTERNLOGDZ128rmbi:
2327 case X86::VPTERNLOGDZ256rmbi:
2328 case X86::VPTERNLOGDZrmbi:
2329 case X86::VPTERNLOGQZ128rmbi:
2330 case X86::VPTERNLOGQZ256rmbi:
2331 case X86::VPTERNLOGQZrmbi:
2332 case X86::VPTERNLOGDZ128rmbikz:
2333 case X86::VPTERNLOGDZ256rmbikz:
2334 case X86::VPTERNLOGDZrmbikz:
2335 case X86::VPTERNLOGQZ128rmbikz:
2336 case X86::VPTERNLOGQZ256rmbikz:
2337 case X86::VPTERNLOGQZrmbikz: {
2338 auto &WorkingMI = cloneIfNew(MI);
2339 commuteVPTERNLOG(WorkingMI, OpIdx1, OpIdx2);
2340 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
2341 OpIdx1, OpIdx2);
2342 }
2343 default: {
2344 if (isCommutableVPERMV3Instruction(MI.getOpcode())) {
2345 unsigned Opc = getCommutedVPERMV3Opcode(MI.getOpcode());
2346 auto &WorkingMI = cloneIfNew(MI);
2347 WorkingMI.setDesc(get(Opc));
2348 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
2349 OpIdx1, OpIdx2);
2350 }
2351
2352 const X86InstrFMA3Group *FMA3Group = getFMA3Group(MI.getOpcode(),
2353 MI.getDesc().TSFlags);
2354 if (FMA3Group) {
2355 unsigned Opc =
2356 getFMA3OpcodeToCommuteOperands(MI, OpIdx1, OpIdx2, *FMA3Group);
2357 auto &WorkingMI = cloneIfNew(MI);
2358 WorkingMI.setDesc(get(Opc));
2359 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
2360 OpIdx1, OpIdx2);
2361 }
2362
2363 return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
2364 }
2365 }
2366}
2367
2368bool
2369X86InstrInfo::findThreeSrcCommutedOpIndices(const MachineInstr &MI,
2370 unsigned &SrcOpIdx1,
2371 unsigned &SrcOpIdx2,
2372 bool IsIntrinsic) const {
2373 uint64_t TSFlags = MI.getDesc().TSFlags;
2374
2375 unsigned FirstCommutableVecOp = 1;
2376 unsigned LastCommutableVecOp = 3;
2377 unsigned KMaskOp = -1U;
2378 if (X86II::isKMasked(TSFlags)) {
2379 // For k-zero-masked operations it is Ok to commute the first vector
2380 // operand. Unless this is an intrinsic instruction.
2381 // For regular k-masked operations a conservative choice is done as the
2382 // elements of the first vector operand, for which the corresponding bit
2383 // in the k-mask operand is set to 0, are copied to the result of the
2384 // instruction.
2385 // TODO/FIXME: The commute still may be legal if it is known that the
2386 // k-mask operand is set to either all ones or all zeroes.
2387 // It is also Ok to commute the 1st operand if all users of MI use only
2388 // the elements enabled by the k-mask operand. For example,
2389 // v4 = VFMADD213PSZrk v1, k, v2, v3; // v1[i] = k[i] ? v2[i]*v1[i]+v3[i]
2390 // : v1[i];
2391 // VMOVAPSZmrk <mem_addr>, k, v4; // this is the ONLY user of v4 ->
2392 // // Ok, to commute v1 in FMADD213PSZrk.
2393
2394 // The k-mask operand has index = 2 for masked and zero-masked operations.
2395 KMaskOp = 2;
2396
2397 // The operand with index = 1 is used as a source for those elements for
2398 // which the corresponding bit in the k-mask is set to 0.
2399 if (X86II::isKMergeMasked(TSFlags) || IsIntrinsic)
2400 FirstCommutableVecOp = 3;
2401
2402 LastCommutableVecOp++;
2403 } else if (IsIntrinsic) {
2404 // Commuting the first operand of an intrinsic instruction isn't possible
2405 // unless we can prove that only the lowest element of the result is used.
2406 FirstCommutableVecOp = 2;
2407 }
2408
2409 if (isMem(MI, LastCommutableVecOp))
2410 LastCommutableVecOp--;
2411
2412 // Only the first RegOpsNum operands are commutable.
2413 // Also, the value 'CommuteAnyOperandIndex' is valid here as it means
2414 // that the operand is not specified/fixed.
2415 if (SrcOpIdx1 != CommuteAnyOperandIndex &&
2416 (SrcOpIdx1 < FirstCommutableVecOp || SrcOpIdx1 > LastCommutableVecOp ||
2417 SrcOpIdx1 == KMaskOp))
2418 return false;
2419 if (SrcOpIdx2 != CommuteAnyOperandIndex &&
2420 (SrcOpIdx2 < FirstCommutableVecOp || SrcOpIdx2 > LastCommutableVecOp ||
2421 SrcOpIdx2 == KMaskOp))
2422 return false;
2423
2424 // Look for two different register operands assumed to be commutable
2425 // regardless of the FMA opcode. The FMA opcode is adjusted later.
2426 if (SrcOpIdx1 == CommuteAnyOperandIndex ||
2427 SrcOpIdx2 == CommuteAnyOperandIndex) {
2428 unsigned CommutableOpIdx2 = SrcOpIdx2;
2429
2430 // At least one of operands to be commuted is not specified and
2431 // this method is free to choose appropriate commutable operands.
2432 if (SrcOpIdx1 == SrcOpIdx2)
2433 // Both of operands are not fixed. By default set one of commutable
2434 // operands to the last register operand of the instruction.
2435 CommutableOpIdx2 = LastCommutableVecOp;
2436 else if (SrcOpIdx2 == CommuteAnyOperandIndex)
2437 // Only one of operands is not fixed.
2438 CommutableOpIdx2 = SrcOpIdx1;
2439
2440 // CommutableOpIdx2 is well defined now. Let's choose another commutable
2441 // operand and assign its index to CommutableOpIdx1.
2442 Register Op2Reg = MI.getOperand(CommutableOpIdx2).getReg();
2443
2444 unsigned CommutableOpIdx1;
2445 for (CommutableOpIdx1 = LastCommutableVecOp;
2446 CommutableOpIdx1 >= FirstCommutableVecOp; CommutableOpIdx1--) {
2447 // Just ignore and skip the k-mask operand.
2448 if (CommutableOpIdx1 == KMaskOp)
2449 continue;
2450
2451 // The commuted operands must have different registers.
2452 // Otherwise, the commute transformation does not change anything and
2453 // is useless then.
2454 if (Op2Reg != MI.getOperand(CommutableOpIdx1).getReg())
2455 break;
2456 }
2457
2458 // No appropriate commutable operands were found.
2459 if (CommutableOpIdx1 < FirstCommutableVecOp)
2460 return false;
2461
2462 // Assign the found pair of commutable indices to SrcOpIdx1 and SrcOpidx2
2463 // to return those values.
2464 if (!fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2,
2465 CommutableOpIdx1, CommutableOpIdx2))
2466 return false;
2467 }
2468
2469 return true;
2470}
2471
2472bool X86InstrInfo::findCommutedOpIndices(const MachineInstr &MI,
2473 unsigned &SrcOpIdx1,
2474 unsigned &SrcOpIdx2) const {
2475 const MCInstrDesc &Desc = MI.getDesc();
2476 if (!Desc.isCommutable())
2477 return false;
2478
2479 switch (MI.getOpcode()) {
2480 case X86::CMPSDrr:
2481 case X86::CMPSSrr:
2482 case X86::CMPPDrri:
2483 case X86::CMPPSrri:
2484 case X86::VCMPSDrr:
2485 case X86::VCMPSSrr:
2486 case X86::VCMPPDrri:
2487 case X86::VCMPPSrri:
2488 case X86::VCMPPDYrri:
2489 case X86::VCMPPSYrri:
2490 case X86::VCMPSDZrr:
2491 case X86::VCMPSSZrr:
2492 case X86::VCMPPDZrri:
2493 case X86::VCMPPSZrri:
2494 case X86::VCMPSHZrr:
2495 case X86::VCMPPHZrri:
2496 case X86::VCMPPHZ128rri:
2497 case X86::VCMPPHZ256rri:
2498 case X86::VCMPPDZ128rri:
2499 case X86::VCMPPSZ128rri:
2500 case X86::VCMPPDZ256rri:
2501 case X86::VCMPPSZ256rri:
2502 case X86::VCMPPDZrrik:
2503 case X86::VCMPPSZrrik:
2504 case X86::VCMPPDZ128rrik:
2505 case X86::VCMPPSZ128rrik:
2506 case X86::VCMPPDZ256rrik:
2507 case X86::VCMPPSZ256rrik: {
2508 unsigned OpOffset = X86II::isKMasked(Desc.TSFlags) ? 1 : 0;
2509
2510 // Float comparison can be safely commuted for
2511 // Ordered/Unordered/Equal/NotEqual tests
2512 unsigned Imm = MI.getOperand(3 + OpOffset).getImm() & 0x7;
2513 switch (Imm) {
2514 default:
2515 // EVEX versions can be commuted.
2516 if ((Desc.TSFlags & X86II::EncodingMask) == X86II::EVEX)
2517 break;
2518 return false;
2519 case 0x00: // EQUAL
2520 case 0x03: // UNORDERED
2521 case 0x04: // NOT EQUAL
2522 case 0x07: // ORDERED
2523 break;
2524 }
2525
2526 // The indices of the commutable operands are 1 and 2 (or 2 and 3
2527 // when masked).
2528 // Assign them to the returned operand indices here.
2529 return fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2, 1 + OpOffset,
2530 2 + OpOffset);
2531 }
2532 case X86::MOVSSrr:
2533 // X86::MOVSDrr is always commutable. MOVSS is only commutable if we can
2534 // form sse4.1 blend. We assume VMOVSSrr/VMOVSDrr is always commutable since
2535 // AVX implies sse4.1.
2536 if (Subtarget.hasSSE41())
2537 return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
2538 return false;
2539 case X86::SHUFPDrri:
2540 // We can commute this to MOVSD.
2541 if (MI.getOperand(3).getImm() == 0x02)
2542 return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
2543 return false;
2544 case X86::MOVHLPSrr:
2545 case X86::UNPCKHPDrr:
2546 case X86::VMOVHLPSrr:
2547 case X86::VUNPCKHPDrr:
2548 case X86::VMOVHLPSZrr:
2549 case X86::VUNPCKHPDZ128rr:
2550 if (Subtarget.hasSSE2())
2551 return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
2552 return false;
2553 case X86::VPTERNLOGDZrri: case X86::VPTERNLOGDZrmi:
2554 case X86::VPTERNLOGDZ128rri: case X86::VPTERNLOGDZ128rmi:
2555 case X86::VPTERNLOGDZ256rri: case X86::VPTERNLOGDZ256rmi:
2556 case X86::VPTERNLOGQZrri: case X86::VPTERNLOGQZrmi:
2557 case X86::VPTERNLOGQZ128rri: case X86::VPTERNLOGQZ128rmi:
2558 case X86::VPTERNLOGQZ256rri: case X86::VPTERNLOGQZ256rmi:
2559 case X86::VPTERNLOGDZrrik:
2560 case X86::VPTERNLOGDZ128rrik:
2561 case X86::VPTERNLOGDZ256rrik:
2562 case X86::VPTERNLOGQZrrik:
2563 case X86::VPTERNLOGQZ128rrik:
2564 case X86::VPTERNLOGQZ256rrik:
2565 case X86::VPTERNLOGDZrrikz: case X86::VPTERNLOGDZrmikz:
2566 case X86::VPTERNLOGDZ128rrikz: case X86::VPTERNLOGDZ128rmikz:
2567 case X86::VPTERNLOGDZ256rrikz: case X86::VPTERNLOGDZ256rmikz:
2568 case X86::VPTERNLOGQZrrikz: case X86::VPTERNLOGQZrmikz:
2569 case X86::VPTERNLOGQZ128rrikz: case X86::VPTERNLOGQZ128rmikz:
2570 case X86::VPTERNLOGQZ256rrikz: case X86::VPTERNLOGQZ256rmikz:
2571 case X86::VPTERNLOGDZ128rmbi:
2572 case X86::VPTERNLOGDZ256rmbi:
2573 case X86::VPTERNLOGDZrmbi:
2574 case X86::VPTERNLOGQZ128rmbi:
2575 case X86::VPTERNLOGQZ256rmbi:
2576 case X86::VPTERNLOGQZrmbi:
2577 case X86::VPTERNLOGDZ128rmbikz:
2578 case X86::VPTERNLOGDZ256rmbikz:
2579 case X86::VPTERNLOGDZrmbikz:
2580 case X86::VPTERNLOGQZ128rmbikz:
2581 case X86::VPTERNLOGQZ256rmbikz:
2582 case X86::VPTERNLOGQZrmbikz:
2583 return findThreeSrcCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
2584 case X86::VPDPWSSDYrr:
2585 case X86::VPDPWSSDrr:
2586 case X86::VPDPWSSDSYrr:
2587 case X86::VPDPWSSDSrr:
2588 case X86::VPDPWSSDZ128r:
2589 case X86::VPDPWSSDZ128rk:
2590 case X86::VPDPWSSDZ128rkz:
2591 case X86::VPDPWSSDZ256r:
2592 case X86::VPDPWSSDZ256rk:
2593 case X86::VPDPWSSDZ256rkz:
2594 case X86::VPDPWSSDZr:
2595 case X86::VPDPWSSDZrk:
2596 case X86::VPDPWSSDZrkz:
2597 case X86::VPDPWSSDSZ128r:
2598 case X86::VPDPWSSDSZ128rk:
2599 case X86::VPDPWSSDSZ128rkz:
2600 case X86::VPDPWSSDSZ256r:
2601 case X86::VPDPWSSDSZ256rk:
2602 case X86::VPDPWSSDSZ256rkz:
2603 case X86::VPDPWSSDSZr:
2604 case X86::VPDPWSSDSZrk:
2605 case X86::VPDPWSSDSZrkz:
2606 case X86::VPMADD52HUQZ128r:
2607 case X86::VPMADD52HUQZ128rk:
2608 case X86::VPMADD52HUQZ128rkz:
2609 case X86::VPMADD52HUQZ256r:
2610 case X86::VPMADD52HUQZ256rk:
2611 case X86::VPMADD52HUQZ256rkz:
2612 case X86::VPMADD52HUQZr:
2613 case X86::VPMADD52HUQZrk:
2614 case X86::VPMADD52HUQZrkz:
2615 case X86::VPMADD52LUQZ128r:
2616 case X86::VPMADD52LUQZ128rk:
2617 case X86::VPMADD52LUQZ128rkz:
2618 case X86::VPMADD52LUQZ256r:
2619 case X86::VPMADD52LUQZ256rk:
2620 case X86::VPMADD52LUQZ256rkz:
2621 case X86::VPMADD52LUQZr:
2622 case X86::VPMADD52LUQZrk:
2623 case X86::VPMADD52LUQZrkz: {
2624 unsigned CommutableOpIdx1 = 2;
2625 unsigned CommutableOpIdx2 = 3;
2626 if (X86II::isKMasked(Desc.TSFlags)) {
2627 // Skip the mask register.
2628 ++CommutableOpIdx1;
2629 ++CommutableOpIdx2;
2630 }
2631 if (!fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2,
2632 CommutableOpIdx1, CommutableOpIdx2))
2633 return false;
2634 if (!MI.getOperand(SrcOpIdx1).isReg() ||
2635 !MI.getOperand(SrcOpIdx2).isReg())
2636 // No idea.
2637 return false;
2638 return true;
2639 }
2640
2641 default:
2642 const X86InstrFMA3Group *FMA3Group = getFMA3Group(MI.getOpcode(),
2643 MI.getDesc().TSFlags);
2644 if (FMA3Group)
2645 return findThreeSrcCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2,
2646 FMA3Group->isIntrinsic());
2647
2648 // Handled masked instructions since we need to skip over the mask input
2649 // and the preserved input.
2650 if (X86II::isKMasked(Desc.TSFlags)) {
2651 // First assume that the first input is the mask operand and skip past it.
2652 unsigned CommutableOpIdx1 = Desc.getNumDefs() + 1;
2653 unsigned CommutableOpIdx2 = Desc.getNumDefs() + 2;
2654 // Check if the first input is tied. If there isn't one then we only
2655 // need to skip the mask operand which we did above.
2656 if ((MI.getDesc().getOperandConstraint(Desc.getNumDefs(),
2657 MCOI::TIED_TO) != -1)) {
2658 // If this is zero masking instruction with a tied operand, we need to
2659 // move the first index back to the first input since this must
2660 // be a 3 input instruction and we want the first two non-mask inputs.
2661 // Otherwise this is a 2 input instruction with a preserved input and
2662 // mask, so we need to move the indices to skip one more input.
2663 if (X86II::isKMergeMasked(Desc.TSFlags)) {
2664 ++CommutableOpIdx1;
2665 ++CommutableOpIdx2;
2666 } else {
2667 --CommutableOpIdx1;
2668 }
2669 }
2670
2671 if (!fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2,
2672 CommutableOpIdx1, CommutableOpIdx2))
2673 return false;
2674
2675 if (!MI.getOperand(SrcOpIdx1).isReg() ||
2676 !MI.getOperand(SrcOpIdx2).isReg())
2677 // No idea.
2678 return false;
2679 return true;
2680 }
2681
2682 return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
2683 }
2684 return false;
2685}
2686
2687static bool isConvertibleLEA(MachineInstr *MI) {
2688 unsigned Opcode = MI->getOpcode();
2689 if (Opcode != X86::LEA32r && Opcode != X86::LEA64r &&
2690 Opcode != X86::LEA64_32r)
2691 return false;
2692
2693 const MachineOperand &Scale = MI->getOperand(1 + X86::AddrScaleAmt);
2694 const MachineOperand &Disp = MI->getOperand(1 + X86::AddrDisp);
2695 const MachineOperand &Segment = MI->getOperand(1 + X86::AddrSegmentReg);
2696
2697 if (Segment.getReg() != 0 || !Disp.isImm() || Disp.getImm() != 0 ||
2698 Scale.getImm() > 1)
2699 return false;
2700
2701 return true;
2702}
2703
2704bool X86InstrInfo::hasCommutePreference(MachineInstr &MI, bool &Commute) const {
2705 // Currently we're interested in following sequence only.
2706 // r3 = lea r1, r2
2707 // r5 = add r3, r4
2708 // Both r3 and r4 are killed in add, we hope the add instruction has the
2709 // operand order
2710 // r5 = add r4, r3
2711 // So later in X86FixupLEAs the lea instruction can be rewritten as add.
2712 unsigned Opcode = MI.getOpcode();
2713 if (Opcode != X86::ADD32rr && Opcode != X86::ADD64rr)
2714 return false;
2715
2716 const MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
2717 Register Reg1 = MI.getOperand(1).getReg();
2718 Register Reg2 = MI.getOperand(2).getReg();
2719
2720 // Check if Reg1 comes from LEA in the same MBB.
2721 if (MachineInstr *Inst = MRI.getUniqueVRegDef(Reg1)) {
2722 if (isConvertibleLEA(Inst) && Inst->getParent() == MI.getParent()) {
2723 Commute = true;
2724 return true;
2725 }
2726 }
2727
2728 // Check if Reg2 comes from LEA in the same MBB.
2729 if (MachineInstr *Inst = MRI.getUniqueVRegDef(Reg2)) {
2730 if (isConvertibleLEA(Inst) && Inst->getParent() == MI.getParent()) {
2731 Commute = false;
2732 return true;
2733 }
2734 }
2735
2736 return false;
2737}
2738
2739X86::CondCode X86::getCondFromBranch(const MachineInstr &MI) {
2740 switch (MI.getOpcode()) {
2741 default: return X86::COND_INVALID;
2742 case X86::JCC_1:
2743 return static_cast<X86::CondCode>(
2744 MI.getOperand(MI.getDesc().getNumOperands() - 1).getImm());
2745 }
2746}
2747
2748/// Return condition code of a SETCC opcode.
2749X86::CondCode X86::getCondFromSETCC(const MachineInstr &MI) {
2750 switch (MI.getOpcode()) {
2751 default: return X86::COND_INVALID;
2752 case X86::SETCCr: case X86::SETCCm:
2753 return static_cast<X86::CondCode>(
2754 MI.getOperand(MI.getDesc().getNumOperands() - 1).getImm());
2755 }
2756}
2757
2758/// Return condition code of a CMov opcode.
2759X86::CondCode X86::getCondFromCMov(const MachineInstr &MI) {
2760 switch (MI.getOpcode()) {
2761 default: return X86::COND_INVALID;
2762 case X86::CMOV16rr: case X86::CMOV32rr: case X86::CMOV64rr:
2763 case X86::CMOV16rm: case X86::CMOV32rm: case X86::CMOV64rm:
2764 return static_cast<X86::CondCode>(
2765 MI.getOperand(MI.getDesc().getNumOperands() - 1).getImm());
2766 }
2767}
2768
2769/// Return the inverse of the specified condition,
2770/// e.g. turning COND_E to COND_NE.
2771X86::CondCode X86::GetOppositeBranchCondition(X86::CondCode CC) {
2772 switch (CC) {
2773 default: llvm_unreachable("Illegal condition code!")::llvm::llvm_unreachable_internal("Illegal condition code!", "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 2773)
;
2774 case X86::COND_E: return X86::COND_NE;
2775 case X86::COND_NE: return X86::COND_E;
2776 case X86::COND_L: return X86::COND_GE;
2777 case X86::COND_LE: return X86::COND_G;
2778 case X86::COND_G: return X86::COND_LE;
2779 case X86::COND_GE: return X86::COND_L;
2780 case X86::COND_B: return X86::COND_AE;
2781 case X86::COND_BE: return X86::COND_A;
2782 case X86::COND_A: return X86::COND_BE;
2783 case X86::COND_AE: return X86::COND_B;
2784 case X86::COND_S: return X86::COND_NS;
2785 case X86::COND_NS: return X86::COND_S;
2786 case X86::COND_P: return X86::COND_NP;
2787 case X86::COND_NP: return X86::COND_P;
2788 case X86::COND_O: return X86::COND_NO;
2789 case X86::COND_NO: return X86::COND_O;
2790 case X86::COND_NE_OR_P: return X86::COND_E_AND_NP;
2791 case X86::COND_E_AND_NP: return X86::COND_NE_OR_P;
2792 }
2793}
2794
2795/// Assuming the flags are set by MI(a,b), return the condition code if we
2796/// modify the instructions such that flags are set by MI(b,a).
2797static X86::CondCode getSwappedCondition(X86::CondCode CC) {
2798 switch (CC) {
2799 default: return X86::COND_INVALID;
2800 case X86::COND_E: return X86::COND_E;
2801 case X86::COND_NE: return X86::COND_NE;
2802 case X86::COND_L: return X86::COND_G;
2803 case X86::COND_LE: return X86::COND_GE;
2804 case X86::COND_G: return X86::COND_L;
2805 case X86::COND_GE: return X86::COND_LE;
2806 case X86::COND_B: return X86::COND_A;
2807 case X86::COND_BE: return X86::COND_AE;
2808 case X86::COND_A: return X86::COND_B;
2809 case X86::COND_AE: return X86::COND_BE;
2810 }
2811}
2812
2813std::pair<X86::CondCode, bool>
2814X86::getX86ConditionCode(CmpInst::Predicate Predicate) {
2815 X86::CondCode CC = X86::COND_INVALID;
2816 bool NeedSwap = false;
2817 switch (Predicate) {
2818 default: break;
2819 // Floating-point Predicates
2820 case CmpInst::FCMP_UEQ: CC = X86::COND_E; break;
2821 case CmpInst::FCMP_OLT: NeedSwap = true; LLVM_FALLTHROUGH[[gnu::fallthrough]];
2822 case CmpInst::FCMP_OGT: CC = X86::COND_A; break;
2823 case CmpInst::FCMP_OLE: NeedSwap = true; LLVM_FALLTHROUGH[[gnu::fallthrough]];
2824 case CmpInst::FCMP_OGE: CC = X86::COND_AE; break;
2825 case CmpInst::FCMP_UGT: NeedSwap = true; LLVM_FALLTHROUGH[[gnu::fallthrough]];
2826 case CmpInst::FCMP_ULT: CC = X86::COND_B; break;
2827 case CmpInst::FCMP_UGE: NeedSwap = true; LLVM_FALLTHROUGH[[gnu::fallthrough]];
2828 case CmpInst::FCMP_ULE: CC = X86::COND_BE; break;
2829 case CmpInst::FCMP_ONE: CC = X86::COND_NE; break;
2830 case CmpInst::FCMP_UNO: CC = X86::COND_P; break;
2831 case CmpInst::FCMP_ORD: CC = X86::COND_NP; break;
2832 case CmpInst::FCMP_OEQ: LLVM_FALLTHROUGH[[gnu::fallthrough]];
2833 case CmpInst::FCMP_UNE: CC = X86::COND_INVALID; break;
2834
2835 // Integer Predicates
2836 case CmpInst::ICMP_EQ: CC = X86::COND_E; break;
2837 case CmpInst::ICMP_NE: CC = X86::COND_NE; break;
2838 case CmpInst::ICMP_UGT: CC = X86::COND_A; break;
2839 case CmpInst::ICMP_UGE: CC = X86::COND_AE; break;
2840 case CmpInst::ICMP_ULT: CC = X86::COND_B; break;
2841 case CmpInst::ICMP_ULE: CC = X86::COND_BE; break;
2842 case CmpInst::ICMP_SGT: CC = X86::COND_G; break;
2843 case CmpInst::ICMP_SGE: CC = X86::COND_GE; break;
2844 case CmpInst::ICMP_SLT: CC = X86::COND_L; break;
2845 case CmpInst::ICMP_SLE: CC = X86::COND_LE; break;
2846 }
2847
2848 return std::make_pair(CC, NeedSwap);
2849}
2850
2851/// Return a setcc opcode based on whether it has memory operand.
2852unsigned X86::getSETOpc(bool HasMemoryOperand) {
2853 return HasMemoryOperand ? X86::SETCCr : X86::SETCCm;
2854}
2855
2856/// Return a cmov opcode for the given register size in bytes, and operand type.
2857unsigned X86::getCMovOpcode(unsigned RegBytes, bool HasMemoryOperand) {
2858 switch(RegBytes) {
2859 default: llvm_unreachable("Illegal register size!")::llvm::llvm_unreachable_internal("Illegal register size!", "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 2859)
;
2860 case 2: return HasMemoryOperand ? X86::CMOV16rm : X86::CMOV16rr;
2861 case 4: return HasMemoryOperand ? X86::CMOV32rm : X86::CMOV32rr;
2862 case 8: return HasMemoryOperand ? X86::CMOV64rm : X86::CMOV64rr;
2863 }
2864}
2865
2866/// Get the VPCMP immediate for the given condition.
2867unsigned X86::getVPCMPImmForCond(ISD::CondCode CC) {
2868 switch (CC) {
2869 default: llvm_unreachable("Unexpected SETCC condition")::llvm::llvm_unreachable_internal("Unexpected SETCC condition"
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 2869)
;
2870 case ISD::SETNE: return 4;
2871 case ISD::SETEQ: return 0;
2872 case ISD::SETULT:
2873 case ISD::SETLT: return 1;
2874 case ISD::SETUGT:
2875 case ISD::SETGT: return 6;
2876 case ISD::SETUGE:
2877 case ISD::SETGE: return 5;
2878 case ISD::SETULE:
2879 case ISD::SETLE: return 2;
2880 }
2881}
2882
2883/// Get the VPCMP immediate if the operands are swapped.
2884unsigned X86::getSwappedVPCMPImm(unsigned Imm) {
2885 switch (Imm) {
2886 default: llvm_unreachable("Unreachable!")::llvm::llvm_unreachable_internal("Unreachable!", "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 2886)
;
2887 case 0x01: Imm = 0x06; break; // LT -> NLE
2888 case 0x02: Imm = 0x05; break; // LE -> NLT
2889 case 0x05: Imm = 0x02; break; // NLT -> LE
2890 case 0x06: Imm = 0x01; break; // NLE -> LT
2891 case 0x00: // EQ
2892 case 0x03: // FALSE
2893 case 0x04: // NE
2894 case 0x07: // TRUE
2895 break;
2896 }
2897
2898 return Imm;
2899}
2900
2901/// Get the VPCOM immediate if the operands are swapped.
2902unsigned X86::getSwappedVPCOMImm(unsigned Imm) {
2903 switch (Imm) {
2904 default: llvm_unreachable("Unreachable!")::llvm::llvm_unreachable_internal("Unreachable!", "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 2904)
;
2905 case 0x00: Imm = 0x02; break; // LT -> GT
2906 case 0x01: Imm = 0x03; break; // LE -> GE
2907 case 0x02: Imm = 0x00; break; // GT -> LT
2908 case 0x03: Imm = 0x01; break; // GE -> LE
2909 case 0x04: // EQ
2910 case 0x05: // NE
2911 case 0x06: // FALSE
2912 case 0x07: // TRUE
2913 break;
2914 }
2915
2916 return Imm;
2917}
2918
2919/// Get the VCMP immediate if the operands are swapped.
2920unsigned X86::getSwappedVCMPImm(unsigned Imm) {
2921 // Only need the lower 2 bits to distinquish.
2922 switch (Imm & 0x3) {
2923 default: llvm_unreachable("Unreachable!")::llvm::llvm_unreachable_internal("Unreachable!", "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 2923)
;
2924 case 0x00: case 0x03:
2925 // EQ/NE/TRUE/FALSE/ORD/UNORD don't change immediate when commuted.
2926 break;
2927 case 0x01: case 0x02:
2928 // Need to toggle bits 3:0. Bit 4 stays the same.
2929 Imm ^= 0xf;
2930 break;
2931 }
2932
2933 return Imm;
2934}
2935
2936bool X86InstrInfo::isUnconditionalTailCall(const MachineInstr &MI) const {
2937 switch (MI.getOpcode()) {
2938 case X86::TCRETURNdi:
2939 case X86::TCRETURNri:
2940 case X86::TCRETURNmi:
2941 case X86::TCRETURNdi64:
2942 case X86::TCRETURNri64:
2943 case X86::TCRETURNmi64:
2944 return true;
2945 default:
2946 return false;
2947 }
2948}
2949
2950bool X86InstrInfo::canMakeTailCallConditional(
2951 SmallVectorImpl<MachineOperand> &BranchCond,
2952 const MachineInstr &TailCall) const {
2953 if (TailCall.getOpcode() != X86::TCRETURNdi &&
2954 TailCall.getOpcode() != X86::TCRETURNdi64) {
2955 // Only direct calls can be done with a conditional branch.
2956 return false;
2957 }
2958
2959 const MachineFunction *MF = TailCall.getParent()->getParent();
2960 if (Subtarget.isTargetWin64() && MF->hasWinCFI()) {
2961 // Conditional tail calls confuse the Win64 unwinder.
2962 return false;
2963 }
2964
2965 assert(BranchCond.size() == 1)(static_cast <bool> (BranchCond.size() == 1) ? void (0)
: __assert_fail ("BranchCond.size() == 1", "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 2965, __extension__ __PRETTY_FUNCTION__))
;
2966 if (BranchCond[0].getImm() > X86::LAST_VALID_COND) {
2967 // Can't make a conditional tail call with this condition.
2968 return false;
2969 }
2970
2971 const X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
2972 if (X86FI->getTCReturnAddrDelta() != 0 ||
2973 TailCall.getOperand(1).getImm() != 0) {
2974 // A conditional tail call cannot do any stack adjustment.
2975 return false;
2976 }
2977
2978 return true;
2979}
2980
2981void X86InstrInfo::replaceBranchWithTailCall(
2982 MachineBasicBlock &MBB, SmallVectorImpl<MachineOperand> &BranchCond,
2983 const MachineInstr &TailCall) const {
2984 assert(canMakeTailCallConditional(BranchCond, TailCall))(static_cast <bool> (canMakeTailCallConditional(BranchCond
, TailCall)) ? void (0) : __assert_fail ("canMakeTailCallConditional(BranchCond, TailCall)"
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 2984, __extension__ __PRETTY_FUNCTION__))
;
2985
2986 MachineBasicBlock::iterator I = MBB.end();
2987 while (I != MBB.begin()) {
2988 --I;
2989 if (I->isDebugInstr())
2990 continue;
2991 if (!I->isBranch())
2992 assert(0 && "Can't find the branch to replace!")(static_cast <bool> (0 && "Can't find the branch to replace!"
) ? void (0) : __assert_fail ("0 && \"Can't find the branch to replace!\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 2992, __extension__ __PRETTY_FUNCTION__))
;
2993
2994 X86::CondCode CC = X86::getCondFromBranch(*I);
2995 assert(BranchCond.size() == 1)(static_cast <bool> (BranchCond.size() == 1) ? void (0)
: __assert_fail ("BranchCond.size() == 1", "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 2995, __extension__ __PRETTY_FUNCTION__))
;
2996 if (CC != BranchCond[0].getImm())
2997 continue;
2998
2999 break;
3000 }
3001
3002 unsigned Opc = TailCall.getOpcode() == X86::TCRETURNdi ? X86::TCRETURNdicc
3003 : X86::TCRETURNdi64cc;
3004
3005 auto MIB = BuildMI(MBB, I, MBB.findDebugLoc(I), get(Opc));
3006 MIB->addOperand(TailCall.getOperand(0)); // Destination.
3007 MIB.addImm(0); // Stack offset (not used).
3008 MIB->addOperand(BranchCond[0]); // Condition.
3009 MIB.copyImplicitOps(TailCall); // Regmask and (imp-used) parameters.
3010
3011 // Add implicit uses and defs of all live regs potentially clobbered by the
3012 // call. This way they still appear live across the call.
3013 LivePhysRegs LiveRegs(getRegisterInfo());
3014 LiveRegs.addLiveOuts(MBB);
3015 SmallVector<std::pair<MCPhysReg, const MachineOperand *>, 8> Clobbers;
3016 LiveRegs.stepForward(*MIB, Clobbers);
3017 for (const auto &C : Clobbers) {
3018 MIB.addReg(C.first, RegState::Implicit);
3019 MIB.addReg(C.first, RegState::Implicit | RegState::Define);
3020 }
3021
3022 I->eraseFromParent();
3023}
3024
3025// Given a MBB and its TBB, find the FBB which was a fallthrough MBB (it may
3026// not be a fallthrough MBB now due to layout changes). Return nullptr if the
3027// fallthrough MBB cannot be identified.
3028static MachineBasicBlock *getFallThroughMBB(MachineBasicBlock *MBB,
3029 MachineBasicBlock *TBB) {
3030 // Look for non-EHPad successors other than TBB. If we find exactly one, it
3031 // is the fallthrough MBB. If we find zero, then TBB is both the target MBB
3032 // and fallthrough MBB. If we find more than one, we cannot identify the
3033 // fallthrough MBB and should return nullptr.
3034 MachineBasicBlock *FallthroughBB = nullptr;
3035 for (auto SI = MBB->succ_begin(), SE = MBB->succ_end(); SI != SE; ++SI) {
3036 if ((*SI)->isEHPad() || (*SI == TBB && FallthroughBB))
3037 continue;
3038 // Return a nullptr if we found more than one fallthrough successor.
3039 if (FallthroughBB && FallthroughBB != TBB)
3040 return nullptr;
3041 FallthroughBB = *SI;
3042 }
3043 return FallthroughBB;
3044}
3045
3046bool X86InstrInfo::AnalyzeBranchImpl(
3047 MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB,
3048 SmallVectorImpl<MachineOperand> &Cond,
3049 SmallVectorImpl<MachineInstr *> &CondBranches, bool AllowModify) const {
3050
3051 // Start from the bottom of the block and work up, examining the
3052 // terminator instructions.
3053 MachineBasicBlock::iterator I = MBB.end();
3054 MachineBasicBlock::iterator UnCondBrIter = MBB.end();
3055 while (I != MBB.begin()) {
3056 --I;
3057 if (I->isDebugInstr())
3058 continue;
3059
3060 // Working from the bottom, when we see a non-terminator instruction, we're
3061 // done.
3062 if (!isUnpredicatedTerminator(*I))
3063 break;
3064
3065 // A terminator that isn't a branch can't easily be handled by this
3066 // analysis.
3067 if (!I->isBranch())
3068 return true;
3069
3070 // Handle unconditional branches.
3071 if (I->getOpcode() == X86::JMP_1) {
3072 UnCondBrIter = I;
3073
3074 if (!AllowModify) {
3075 TBB = I->getOperand(0).getMBB();
3076 continue;
3077 }
3078
3079 // If the block has any instructions after a JMP, delete them.
3080 while (std::next(I) != MBB.end())
3081 std::next(I)->eraseFromParent();
3082
3083 Cond.clear();
3084 FBB = nullptr;
3085
3086 // Delete the JMP if it's equivalent to a fall-through.
3087 if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
3088 TBB = nullptr;
3089 I->eraseFromParent();
3090 I = MBB.end();
3091 UnCondBrIter = MBB.end();
3092 continue;
3093 }
3094
3095 // TBB is used to indicate the unconditional destination.
3096 TBB = I->getOperand(0).getMBB();
3097 continue;
3098 }
3099
3100 // Handle conditional branches.
3101 X86::CondCode BranchCode = X86::getCondFromBranch(*I);
3102 if (BranchCode == X86::COND_INVALID)
3103 return true; // Can't handle indirect branch.
3104
3105 // In practice we should never have an undef eflags operand, if we do
3106 // abort here as we are not prepared to preserve the flag.
3107 if (I->findRegisterUseOperand(X86::EFLAGS)->isUndef())
3108 return true;
3109
3110 // Working from the bottom, handle the first conditional branch.
3111 if (Cond.empty()) {
3112 MachineBasicBlock *TargetBB = I->getOperand(0).getMBB();
3113 if (AllowModify && UnCondBrIter != MBB.end() &&
3114 MBB.isLayoutSuccessor(TargetBB)) {
3115 // If we can modify the code and it ends in something like:
3116 //
3117 // jCC L1
3118 // jmp L2
3119 // L1:
3120 // ...
3121 // L2:
3122 //
3123 // Then we can change this to:
3124 //
3125 // jnCC L2
3126 // L1:
3127 // ...
3128 // L2:
3129 //
3130 // Which is a bit more efficient.
3131 // We conditionally jump to the fall-through block.
3132 BranchCode = GetOppositeBranchCondition(BranchCode);
3133 MachineBasicBlock::iterator OldInst = I;
3134
3135 BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(X86::JCC_1))
3136 .addMBB(UnCondBrIter->getOperand(0).getMBB())
3137 .addImm(BranchCode);
3138 BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(X86::JMP_1))
3139 .addMBB(TargetBB);
3140
3141 OldInst->eraseFromParent();
3142 UnCondBrIter->eraseFromParent();
3143
3144 // Restart the analysis.
3145 UnCondBrIter = MBB.end();
3146 I = MBB.end();
3147 continue;
3148 }
3149
3150 FBB = TBB;
3151 TBB = I->getOperand(0).getMBB();
3152 Cond.push_back(MachineOperand::CreateImm(BranchCode));
3153 CondBranches.push_back(&*I);
3154 continue;
3155 }
3156
3157 // Handle subsequent conditional branches. Only handle the case where all
3158 // conditional branches branch to the same destination and their condition
3159 // opcodes fit one of the special multi-branch idioms.
3160 assert(Cond.size() == 1)(static_cast <bool> (Cond.size() == 1) ? void (0) : __assert_fail
("Cond.size() == 1", "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 3160, __extension__ __PRETTY_FUNCTION__))
;
3161 assert(TBB)(static_cast <bool> (TBB) ? void (0) : __assert_fail ("TBB"
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 3161, __extension__ __PRETTY_FUNCTION__))
;
3162
3163 // If the conditions are the same, we can leave them alone.
3164 X86::CondCode OldBranchCode = (X86::CondCode)Cond[0].getImm();
3165 auto NewTBB = I->getOperand(0).getMBB();
3166 if (OldBranchCode == BranchCode && TBB == NewTBB)
3167 continue;
3168
3169 // If they differ, see if they fit one of the known patterns. Theoretically,
3170 // we could handle more patterns here, but we shouldn't expect to see them
3171 // if instruction selection has done a reasonable job.
3172 if (TBB == NewTBB &&
3173 ((OldBranchCode == X86::COND_P && BranchCode == X86::COND_NE) ||
3174 (OldBranchCode == X86::COND_NE && BranchCode == X86::COND_P))) {
3175 BranchCode = X86::COND_NE_OR_P;
3176 } else if ((OldBranchCode == X86::COND_NP && BranchCode == X86::COND_NE) ||
3177 (OldBranchCode == X86::COND_E && BranchCode == X86::COND_P)) {
3178 if (NewTBB != (FBB ? FBB : getFallThroughMBB(&MBB, TBB)))
3179 return true;
3180
3181 // X86::COND_E_AND_NP usually has two different branch destinations.
3182 //
3183 // JP B1
3184 // JE B2
3185 // JMP B1
3186 // B1:
3187 // B2:
3188 //
3189 // Here this condition branches to B2 only if NP && E. It has another
3190 // equivalent form:
3191 //
3192 // JNE B1
3193 // JNP B2
3194 // JMP B1
3195 // B1:
3196 // B2:
3197 //
3198 // Similarly it branches to B2 only if E && NP. That is why this condition
3199 // is named with COND_E_AND_NP.
3200 BranchCode = X86::COND_E_AND_NP;
3201 } else
3202 return true;
3203
3204 // Update the MachineOperand.
3205 Cond[0].setImm(BranchCode);
3206 CondBranches.push_back(&*I);
3207 }
3208
3209 return false;
3210}
3211
3212bool X86InstrInfo::analyzeBranch(MachineBasicBlock &MBB,
3213 MachineBasicBlock *&TBB,
3214 MachineBasicBlock *&FBB,
3215 SmallVectorImpl<MachineOperand> &Cond,
3216 bool AllowModify) const {
3217 SmallVector<MachineInstr *, 4> CondBranches;
3218 return AnalyzeBranchImpl(MBB, TBB, FBB, Cond, CondBranches, AllowModify);
3219}
3220
3221bool X86InstrInfo::analyzeBranchPredicate(MachineBasicBlock &MBB,
3222 MachineBranchPredicate &MBP,
3223 bool AllowModify) const {
3224 using namespace std::placeholders;
3225
3226 SmallVector<MachineOperand, 4> Cond;
3227 SmallVector<MachineInstr *, 4> CondBranches;
3228 if (AnalyzeBranchImpl(MBB, MBP.TrueDest, MBP.FalseDest, Cond, CondBranches,
3229 AllowModify))
3230 return true;
3231
3232 if (Cond.size() != 1)
3233 return true;
3234
3235 assert(MBP.TrueDest && "expected!")(static_cast <bool> (MBP.TrueDest && "expected!"
) ? void (0) : __assert_fail ("MBP.TrueDest && \"expected!\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 3235, __extension__ __PRETTY_FUNCTION__))
;
3236
3237 if (!MBP.FalseDest)
3238 MBP.FalseDest = MBB.getNextNode();
3239
3240 const TargetRegisterInfo *TRI = &getRegisterInfo();
3241
3242 MachineInstr *ConditionDef = nullptr;
3243 bool SingleUseCondition = true;
3244
3245 for (auto I = std::next(MBB.rbegin()), E = MBB.rend(); I != E; ++I) {
3246 if (I->modifiesRegister(X86::EFLAGS, TRI)) {
3247 ConditionDef = &*I;
3248 break;
3249 }
3250
3251 if (I->readsRegister(X86::EFLAGS, TRI))
3252 SingleUseCondition = false;
3253 }
3254
3255 if (!ConditionDef)
3256 return true;
3257
3258 if (SingleUseCondition) {
3259 for (auto *Succ : MBB.successors())
3260 if (Succ->isLiveIn(X86::EFLAGS))
3261 SingleUseCondition = false;
3262 }
3263
3264 MBP.ConditionDef = ConditionDef;
3265 MBP.SingleUseCondition = SingleUseCondition;
3266
3267 // Currently we only recognize the simple pattern:
3268 //
3269 // test %reg, %reg
3270 // je %label
3271 //
3272 const unsigned TestOpcode =
3273 Subtarget.is64Bit() ? X86::TEST64rr : X86::TEST32rr;
3274
3275 if (ConditionDef->getOpcode() == TestOpcode &&
3276 ConditionDef->getNumOperands() == 3 &&
3277 ConditionDef->getOperand(0).isIdenticalTo(ConditionDef->getOperand(1)) &&
3278 (Cond[0].getImm() == X86::COND_NE || Cond[0].getImm() == X86::COND_E)) {
3279 MBP.LHS = ConditionDef->getOperand(0);
3280 MBP.RHS = MachineOperand::CreateImm(0);
3281 MBP.Predicate = Cond[0].getImm() == X86::COND_NE
3282 ? MachineBranchPredicate::PRED_NE
3283 : MachineBranchPredicate::PRED_EQ;
3284 return false;
3285 }
3286
3287 return true;
3288}
3289
3290unsigned X86InstrInfo::removeBranch(MachineBasicBlock &MBB,
3291 int *BytesRemoved) const {
3292 assert(!BytesRemoved && "code size not handled")(static_cast <bool> (!BytesRemoved && "code size not handled"
) ? void (0) : __assert_fail ("!BytesRemoved && \"code size not handled\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 3292, __extension__ __PRETTY_FUNCTION__))
;
3293
3294 MachineBasicBlock::iterator I = MBB.end();
3295 unsigned Count = 0;
3296
3297 while (I != MBB.begin()) {
3298 --I;
3299 if (I->isDebugInstr())
3300 continue;
3301 if (I->getOpcode() != X86::JMP_1 &&
3302 X86::getCondFromBranch(*I) == X86::COND_INVALID)
3303 break;
3304 // Remove the branch.
3305 I->eraseFromParent();
3306 I = MBB.end();
3307 ++Count;
3308 }
3309
3310 return Count;
3311}
3312
3313unsigned X86InstrInfo::insertBranch(MachineBasicBlock &MBB,
3314 MachineBasicBlock *TBB,
3315 MachineBasicBlock *FBB,
3316 ArrayRef<MachineOperand> Cond,
3317 const DebugLoc &DL,
3318 int *BytesAdded) const {
3319 // Shouldn't be a fall through.
3320 assert(TBB && "insertBranch must not be told to insert a fallthrough")(static_cast <bool> (TBB && "insertBranch must not be told to insert a fallthrough"
) ? void (0) : __assert_fail ("TBB && \"insertBranch must not be told to insert a fallthrough\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 3320, __extension__ __PRETTY_FUNCTION__))
;
3321 assert((Cond.size() == 1 || Cond.size() == 0) &&(static_cast <bool> ((Cond.size() == 1 || Cond.size() ==
0) && "X86 branch conditions have one component!") ?
void (0) : __assert_fail ("(Cond.size() == 1 || Cond.size() == 0) && \"X86 branch conditions have one component!\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 3322, __extension__ __PRETTY_FUNCTION__))
3322 "X86 branch conditions have one component!")(static_cast <bool> ((Cond.size() == 1 || Cond.size() ==
0) && "X86 branch conditions have one component!") ?
void (0) : __assert_fail ("(Cond.size() == 1 || Cond.size() == 0) && \"X86 branch conditions have one component!\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 3322, __extension__ __PRETTY_FUNCTION__))
;
3323 assert(!BytesAdded && "code size not handled")(static_cast <bool> (!BytesAdded && "code size not handled"
) ? void (0) : __assert_fail ("!BytesAdded && \"code size not handled\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 3323, __extension__ __PRETTY_FUNCTION__))
;
3324
3325 if (Cond.empty()) {
3326 // Unconditional branch?
3327 assert(!FBB && "Unconditional branch with multiple successors!")(static_cast <bool> (!FBB && "Unconditional branch with multiple successors!"
) ? void (0) : __assert_fail ("!FBB && \"Unconditional branch with multiple successors!\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 3327, __extension__ __PRETTY_FUNCTION__))
;
3328 BuildMI(&MBB, DL, get(X86::JMP_1)).addMBB(TBB);
3329 return 1;
3330 }
3331
3332 // If FBB is null, it is implied to be a fall-through block.
3333 bool FallThru = FBB == nullptr;
3334
3335 // Conditional branch.
3336 unsigned Count = 0;
3337 X86::CondCode CC = (X86::CondCode)Cond[0].getImm();
3338 switch (CC) {
3339 case X86::COND_NE_OR_P:
3340 // Synthesize NE_OR_P with two branches.
3341 BuildMI(&MBB, DL, get(X86::JCC_1)).addMBB(TBB).addImm(X86::COND_NE);
3342 ++Count;
3343 BuildMI(&MBB, DL, get(X86::JCC_1)).addMBB(TBB).addImm(X86::COND_P);
3344 ++Count;
3345 break;
3346 case X86::COND_E_AND_NP:
3347 // Use the next block of MBB as FBB if it is null.
3348 if (FBB == nullptr) {
3349 FBB = getFallThroughMBB(&MBB, TBB);
3350 assert(FBB && "MBB cannot be the last block in function when the false "(static_cast <bool> (FBB && "MBB cannot be the last block in function when the false "
"body is a fall-through.") ? void (0) : __assert_fail ("FBB && \"MBB cannot be the last block in function when the false \" \"body is a fall-through.\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 3351, __extension__ __PRETTY_FUNCTION__))
3351 "body is a fall-through.")(static_cast <bool> (FBB && "MBB cannot be the last block in function when the false "
"body is a fall-through.") ? void (0) : __assert_fail ("FBB && \"MBB cannot be the last block in function when the false \" \"body is a fall-through.\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 3351, __extension__ __PRETTY_FUNCTION__))
;
3352 }
3353 // Synthesize COND_E_AND_NP with two branches.
3354 BuildMI(&MBB, DL, get(X86::JCC_1)).addMBB(FBB).addImm(X86::COND_NE);
3355 ++Count;
3356 BuildMI(&MBB, DL, get(X86::JCC_1)).addMBB(TBB).addImm(X86::COND_NP);
3357 ++Count;
3358 break;
3359 default: {
3360 BuildMI(&MBB, DL, get(X86::JCC_1)).addMBB(TBB).addImm(CC);
3361 ++Count;
3362 }
3363 }
3364 if (!FallThru) {
3365 // Two-way Conditional branch. Insert the second branch.
3366 BuildMI(&MBB, DL, get(X86::JMP_1)).addMBB(FBB);
3367 ++Count;
3368 }
3369 return Count;
3370}
3371
3372bool X86InstrInfo::canInsertSelect(const MachineBasicBlock &MBB,
3373 ArrayRef<MachineOperand> Cond,
3374 Register DstReg, Register TrueReg,
3375 Register FalseReg, int &CondCycles,
3376 int &TrueCycles, int &FalseCycles) const {
3377 // Not all subtargets have cmov instructions.
3378 if (!Subtarget.hasCMov())
3379 return false;
3380 if (Cond.size() != 1)
3381 return false;
3382 // We cannot do the composite conditions, at least not in SSA form.
3383 if ((X86::CondCode)Cond[0].getImm() > X86::LAST_VALID_COND)
3384 return false;
3385
3386 // Check register classes.
3387 const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
3388 const TargetRegisterClass *RC =
3389 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
3390 if (!RC)
3391 return false;
3392
3393 // We have cmov instructions for 16, 32, and 64 bit general purpose registers.
3394 if (X86::GR16RegClass.hasSubClassEq(RC) ||
3395 X86::GR32RegClass.hasSubClassEq(RC) ||
3396 X86::GR64RegClass.hasSubClassEq(RC)) {
3397 // This latency applies to Pentium M, Merom, Wolfdale, Nehalem, and Sandy
3398 // Bridge. Probably Ivy Bridge as well.
3399 CondCycles = 2;
3400 TrueCycles = 2;
3401 FalseCycles = 2;
3402 return true;
3403 }
3404
3405 // Can't do vectors.
3406 return false;
3407}
3408
3409void X86InstrInfo::insertSelect(MachineBasicBlock &MBB,
3410 MachineBasicBlock::iterator I,
3411 const DebugLoc &DL, Register DstReg,
3412 ArrayRef<MachineOperand> Cond, Register TrueReg,
3413 Register FalseReg) const {
3414 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
3415 const TargetRegisterInfo &TRI = *MRI.getTargetRegisterInfo();
3416 const TargetRegisterClass &RC = *MRI.getRegClass(DstReg);
3417 assert(Cond.size() == 1 && "Invalid Cond array")(static_cast <bool> (Cond.size() == 1 && "Invalid Cond array"
) ? void (0) : __assert_fail ("Cond.size() == 1 && \"Invalid Cond array\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 3417, __extension__ __PRETTY_FUNCTION__))
;
3418 unsigned Opc = X86::getCMovOpcode(TRI.getRegSizeInBits(RC) / 8,
3419 false /*HasMemoryOperand*/);
3420 BuildMI(MBB, I, DL, get(Opc), DstReg)
3421 .addReg(FalseReg)
3422 .addReg(TrueReg)
3423 .addImm(Cond[0].getImm());
3424}
3425
3426/// Test if the given register is a physical h register.
3427static bool isHReg(unsigned Reg) {
3428 return X86::GR8_ABCD_HRegClass.contains(Reg);
3429}
3430
3431// Try and copy between VR128/VR64 and GR64 registers.
3432static unsigned CopyToFromAsymmetricReg(unsigned DestReg, unsigned SrcReg,
3433 const X86Subtarget &Subtarget) {
3434 bool HasAVX = Subtarget.hasAVX();
3435 bool HasAVX512 = Subtarget.hasAVX512();
3436
3437 // SrcReg(MaskReg) -> DestReg(GR64)
3438 // SrcReg(MaskReg) -> DestReg(GR32)
3439
3440 // All KMASK RegClasses hold the same k registers, can be tested against anyone.
3441 if (X86::VK16RegClass.contains(SrcReg)) {
3442 if (X86::GR64RegClass.contains(DestReg)) {
3443 assert(Subtarget.hasBWI())(static_cast <bool> (Subtarget.hasBWI()) ? void (0) : __assert_fail
("Subtarget.hasBWI()", "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 3443, __extension__ __PRETTY_FUNCTION__))
;
3444 return X86::KMOVQrk;
3445 }
3446 if (X86::GR32RegClass.contains(DestReg))
3447 return Subtarget.hasBWI() ? X86::KMOVDrk : X86::KMOVWrk;
3448 }
3449
3450 // SrcReg(GR64) -> DestReg(MaskReg)
3451 // SrcReg(GR32) -> DestReg(MaskReg)
3452
3453 // All KMASK RegClasses hold the same k registers, can be tested against anyone.
3454 if (X86::VK16RegClass.contains(DestReg)) {
3455 if (X86::GR64RegClass.contains(SrcReg)) {
3456 assert(Subtarget.hasBWI())(static_cast <bool> (Subtarget.hasBWI()) ? void (0) : __assert_fail
("Subtarget.hasBWI()", "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 3456, __extension__ __PRETTY_FUNCTION__))
;
3457 return X86::KMOVQkr;
3458 }
3459 if (X86::GR32RegClass.contains(SrcReg))
3460 return Subtarget.hasBWI() ? X86::KMOVDkr : X86::KMOVWkr;
3461 }
3462
3463
3464 // SrcReg(VR128) -> DestReg(GR64)
3465 // SrcReg(VR64) -> DestReg(GR64)
3466 // SrcReg(GR64) -> DestReg(VR128)
3467 // SrcReg(GR64) -> DestReg(VR64)
3468
3469 if (X86::GR64RegClass.contains(DestReg)) {
3470 if (X86::VR128XRegClass.contains(SrcReg))
3471 // Copy from a VR128 register to a GR64 register.
3472 return HasAVX512 ? X86::VMOVPQIto64Zrr :
3473 HasAVX ? X86::VMOVPQIto64rr :
3474 X86::MOVPQIto64rr;
3475 if (X86::VR64RegClass.contains(SrcReg))
3476 // Copy from a VR64 register to a GR64 register.
3477 return X86::MMX_MOVD64from64rr;
3478 } else if (X86::GR64RegClass.contains(SrcReg)) {
3479 // Copy from a GR64 register to a VR128 register.
3480 if (X86::VR128XRegClass.contains(DestReg))
3481 return HasAVX512 ? X86::VMOV64toPQIZrr :
3482 HasAVX ? X86::VMOV64toPQIrr :
3483 X86::MOV64toPQIrr;
3484 // Copy from a GR64 register to a VR64 register.
3485 if (X86::VR64RegClass.contains(DestReg))
3486 return X86::MMX_MOVD64to64rr;
3487 }
3488
3489 // SrcReg(VR128) -> DestReg(GR32)
3490 // SrcReg(GR32) -> DestReg(VR128)
3491
3492 if (X86::GR32RegClass.contains(DestReg) &&
3493 X86::VR128XRegClass.contains(SrcReg))
3494 // Copy from a VR128 register to a GR32 register.
3495 return HasAVX512 ? X86::VMOVPDI2DIZrr :
3496 HasAVX ? X86::VMOVPDI2DIrr :
3497 X86::MOVPDI2DIrr;
3498
3499 if (X86::VR128XRegClass.contains(DestReg) &&
3500 X86::GR32RegClass.contains(SrcReg))
3501 // Copy from a VR128 register to a VR128 register.
3502 return HasAVX512 ? X86::VMOVDI2PDIZrr :
3503 HasAVX ? X86::VMOVDI2PDIrr :
3504 X86::MOVDI2PDIrr;
3505 return 0;
3506}
3507
3508void X86InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
3509 MachineBasicBlock::iterator MI,
3510 const DebugLoc &DL, MCRegister DestReg,
3511 MCRegister SrcReg, bool KillSrc) const {
3512 // First deal with the normal symmetric copies.
3513 bool HasAVX = Subtarget.hasAVX();
3514 bool HasVLX = Subtarget.hasVLX();
3515 unsigned Opc = 0;
3516 if (X86::GR64RegClass.contains(DestReg, SrcReg))
3517 Opc = X86::MOV64rr;
3518 else if (X86::GR32RegClass.contains(DestReg, SrcReg))
3519 Opc = X86::MOV32rr;
3520 else if (X86::GR16RegClass.contains(DestReg, SrcReg))
3521 Opc = X86::MOV16rr;
3522 else if (X86::GR8RegClass.contains(DestReg, SrcReg)) {
3523 // Copying to or from a physical H register on x86-64 requires a NOREX
3524 // move. Otherwise use a normal move.
3525 if ((isHReg(DestReg) || isHReg(SrcReg)) &&
3526 Subtarget.is64Bit()) {
3527 Opc = X86::MOV8rr_NOREX;
3528 // Both operands must be encodable without an REX prefix.
3529 assert(X86::GR8_NOREXRegClass.contains(SrcReg, DestReg) &&(static_cast <bool> (X86::GR8_NOREXRegClass.contains(SrcReg
, DestReg) && "8-bit H register can not be copied outside GR8_NOREX"
) ? void (0) : __assert_fail ("X86::GR8_NOREXRegClass.contains(SrcReg, DestReg) && \"8-bit H register can not be copied outside GR8_NOREX\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 3530, __extension__ __PRETTY_FUNCTION__))
3530 "8-bit H register can not be copied outside GR8_NOREX")(static_cast <bool> (X86::GR8_NOREXRegClass.contains(SrcReg
, DestReg) && "8-bit H register can not be copied outside GR8_NOREX"
) ? void (0) : __assert_fail ("X86::GR8_NOREXRegClass.contains(SrcReg, DestReg) && \"8-bit H register can not be copied outside GR8_NOREX\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 3530, __extension__ __PRETTY_FUNCTION__))
;
3531 } else
3532 Opc = X86::MOV8rr;
3533 }
3534 else if (X86::VR64RegClass.contains(DestReg, SrcReg))
3535 Opc = X86::MMX_MOVQ64rr;
3536 else if (X86::VR128XRegClass.contains(DestReg, SrcReg)) {
3537 if (HasVLX)
3538 Opc = X86::VMOVAPSZ128rr;
3539 else if (X86::VR128RegClass.contains(DestReg, SrcReg))
3540 Opc = HasAVX ? X86::VMOVAPSrr : X86::MOVAPSrr;
3541 else {
3542 // If this an extended register and we don't have VLX we need to use a
3543 // 512-bit move.
3544 Opc = X86::VMOVAPSZrr;
3545 const TargetRegisterInfo *TRI = &getRegisterInfo();
3546 DestReg = TRI->getMatchingSuperReg(DestReg, X86::sub_xmm,
3547 &X86::VR512RegClass);
3548 SrcReg = TRI->getMatchingSuperReg(SrcReg, X86::sub_xmm,
3549 &X86::VR512RegClass);
3550 }
3551 } else if (X86::VR256XRegClass.contains(DestReg, SrcReg)) {
3552 if (HasVLX)
3553 Opc = X86::VMOVAPSZ256rr;
3554 else if (X86::VR256RegClass.contains(DestReg, SrcReg))
3555 Opc = X86::VMOVAPSYrr;
3556 else {
3557 // If this an extended register and we don't have VLX we need to use a
3558 // 512-bit move.
3559 Opc = X86::VMOVAPSZrr;
3560 const TargetRegisterInfo *TRI = &getRegisterInfo();
3561 DestReg = TRI->getMatchingSuperReg(DestReg, X86::sub_ymm,
3562 &X86::VR512RegClass);
3563 SrcReg = TRI->getMatchingSuperReg(SrcReg, X86::sub_ymm,
3564 &X86::VR512RegClass);
3565 }
3566 } else if (X86::VR512RegClass.contains(DestReg, SrcReg))
3567 Opc = X86::VMOVAPSZrr;
3568 // All KMASK RegClasses hold the same k registers, can be tested against anyone.
3569 else if (X86::VK16RegClass.contains(DestReg, SrcReg))
3570 Opc = Subtarget.hasBWI() ? X86::KMOVQkk : X86::KMOVWkk;
3571 if (!Opc)
3572 Opc = CopyToFromAsymmetricReg(DestReg, SrcReg, Subtarget);
3573
3574 if (Opc) {
3575 BuildMI(MBB, MI, DL, get(Opc), DestReg)
3576 .addReg(SrcReg, getKillRegState(KillSrc));
3577 return;
3578 }
3579
3580 if (SrcReg == X86::EFLAGS || DestReg == X86::EFLAGS) {
3581 // FIXME: We use a fatal error here because historically LLVM has tried
3582 // lower some of these physreg copies and we want to ensure we get
3583 // reasonable bug reports if someone encounters a case no other testing
3584 // found. This path should be removed after the LLVM 7 release.
3585 report_fatal_error("Unable to copy EFLAGS physical register!");
3586 }
3587
3588 LLVM_DEBUG(dbgs() << "Cannot copy " << RI.getName(SrcReg) << " to "do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("x86-instr-info")) { dbgs() << "Cannot copy " <<
RI.getName(SrcReg) << " to " << RI.getName(DestReg
) << '\n'; } } while (false)
3589 << RI.getName(DestReg) << '\n')do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("x86-instr-info")) { dbgs() << "Cannot copy " <<
RI.getName(SrcReg) << " to " << RI.getName(DestReg
) << '\n'; } } while (false)
;
3590 report_fatal_error("Cannot emit physreg copy instruction");
3591}
3592
3593Optional<DestSourcePair>
3594X86InstrInfo::isCopyInstrImpl(const MachineInstr &MI) const {
3595 if (MI.isMoveReg())
3596 return DestSourcePair{MI.getOperand(0), MI.getOperand(1)};
3597 return None;
3598}
3599
3600static unsigned getLoadStoreRegOpcode(Register Reg,
3601 const TargetRegisterClass *RC,
3602 bool IsStackAligned,
3603 const X86Subtarget &STI, bool load) {
3604 bool HasAVX = STI.hasAVX();
3605 bool HasAVX512 = STI.hasAVX512();
3606 bool HasVLX = STI.hasVLX();
3607
3608 switch (STI.getRegisterInfo()->getSpillSize(*RC)) {
3609 default:
3610 llvm_unreachable("Unknown spill size")::llvm::llvm_unreachable_internal("Unknown spill size", "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 3610)
;
3611 case 1:
3612 assert(X86::GR8RegClass.hasSubClassEq(RC) && "Unknown 1-byte regclass")(static_cast <bool> (X86::GR8RegClass.hasSubClassEq(RC)
&& "Unknown 1-byte regclass") ? void (0) : __assert_fail
("X86::GR8RegClass.hasSubClassEq(RC) && \"Unknown 1-byte regclass\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 3612, __extension__ __PRETTY_FUNCTION__))
;
3613 if (STI.is64Bit())
3614 // Copying to or from a physical H register on x86-64 requires a NOREX
3615 // move. Otherwise use a normal move.
3616 if (isHReg(Reg) || X86::GR8_ABCD_HRegClass.hasSubClassEq(RC))
3617 return load ? X86::MOV8rm_NOREX : X86::MOV8mr_NOREX;
3618 return load ? X86::MOV8rm : X86::MOV8mr;
3619 case 2:
3620 if (X86::VK16RegClass.hasSubClassEq(RC))
3621 return load ? X86::KMOVWkm : X86::KMOVWmk;
3622 if (X86::FR16XRegClass.hasSubClassEq(RC)) {
3623 assert(STI.hasFP16())(static_cast <bool> (STI.hasFP16()) ? void (0) : __assert_fail
("STI.hasFP16()", "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 3623, __extension__ __PRETTY_FUNCTION__))
;
3624 return load ? X86::VMOVSHZrm_alt : X86::VMOVSHZmr;
3625 }
3626 assert(X86::GR16RegClass.hasSubClassEq(RC) && "Unknown 2-byte regclass")(static_cast <bool> (X86::GR16RegClass.hasSubClassEq(RC
) && "Unknown 2-byte regclass") ? void (0) : __assert_fail
("X86::GR16RegClass.hasSubClassEq(RC) && \"Unknown 2-byte regclass\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 3626, __extension__ __PRETTY_FUNCTION__))
;
3627 return load ? X86::MOV16rm : X86::MOV16mr;
3628 case 4:
3629 if (X86::GR32RegClass.hasSubClassEq(RC))
3630 return load ? X86::MOV32rm : X86::MOV32mr;
3631 if (X86::FR32XRegClass.hasSubClassEq(RC))
3632 return load ?
3633 (HasAVX512 ? X86::VMOVSSZrm_alt :
3634 HasAVX ? X86::VMOVSSrm_alt :
3635 X86::MOVSSrm_alt) :
3636 (HasAVX512 ? X86::VMOVSSZmr :
3637 HasAVX ? X86::VMOVSSmr :
3638 X86::MOVSSmr);
3639 if (X86::RFP32RegClass.hasSubClassEq(RC))
3640 return load ? X86::LD_Fp32m : X86::ST_Fp32m;
3641 if (X86::VK32RegClass.hasSubClassEq(RC)) {
3642 assert(STI.hasBWI() && "KMOVD requires BWI")(static_cast <bool> (STI.hasBWI() && "KMOVD requires BWI"
) ? void (0) : __assert_fail ("STI.hasBWI() && \"KMOVD requires BWI\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 3642, __extension__ __PRETTY_FUNCTION__))
;
3643 return load ? X86::KMOVDkm : X86::KMOVDmk;
3644 }
3645 // All of these mask pair classes have the same spill size, the same kind
3646 // of kmov instructions can be used with all of them.
3647 if (X86::VK1PAIRRegClass.hasSubClassEq(RC) ||
3648 X86::VK2PAIRRegClass.hasSubClassEq(RC) ||
3649 X86::VK4PAIRRegClass.hasSubClassEq(RC) ||
3650 X86::VK8PAIRRegClass.hasSubClassEq(RC) ||
3651 X86::VK16PAIRRegClass.hasSubClassEq(RC))
3652 return load ? X86::MASKPAIR16LOAD : X86::MASKPAIR16STORE;
3653 llvm_unreachable("Unknown 4-byte regclass")::llvm::llvm_unreachable_internal("Unknown 4-byte regclass", "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 3653)
;
3654 case 8:
3655 if (X86::GR64RegClass.hasSubClassEq(RC))
3656 return load ? X86::MOV64rm : X86::MOV64mr;
3657 if (X86::FR64XRegClass.hasSubClassEq(RC))
3658 return load ?
3659 (HasAVX512 ? X86::VMOVSDZrm_alt :
3660 HasAVX ? X86::VMOVSDrm_alt :
3661 X86::MOVSDrm_alt) :
3662 (HasAVX512 ? X86::VMOVSDZmr :
3663 HasAVX ? X86::VMOVSDmr :
3664 X86::MOVSDmr);
3665 if (X86::VR64RegClass.hasSubClassEq(RC))
3666 return load ? X86::MMX_MOVQ64rm : X86::MMX_MOVQ64mr;
3667 if (X86::RFP64RegClass.hasSubClassEq(RC))
3668 return load ? X86::LD_Fp64m : X86::ST_Fp64m;
3669 if (X86::VK64RegClass.hasSubClassEq(RC)) {
3670 assert(STI.hasBWI() && "KMOVQ requires BWI")(static_cast <bool> (STI.hasBWI() && "KMOVQ requires BWI"
) ? void (0) : __assert_fail ("STI.hasBWI() && \"KMOVQ requires BWI\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 3670, __extension__ __PRETTY_FUNCTION__))
;
3671 return load ? X86::KMOVQkm : X86::KMOVQmk;
3672 }
3673 llvm_unreachable("Unknown 8-byte regclass")::llvm::llvm_unreachable_internal("Unknown 8-byte regclass", "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 3673)
;
3674 case 10:
3675 assert(X86::RFP80RegClass.hasSubClassEq(RC) && "Unknown 10-byte regclass")(static_cast <bool> (X86::RFP80RegClass.hasSubClassEq(RC
) && "Unknown 10-byte regclass") ? void (0) : __assert_fail
("X86::RFP80RegClass.hasSubClassEq(RC) && \"Unknown 10-byte regclass\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 3675, __extension__ __PRETTY_FUNCTION__))
;
3676 return load ? X86::LD_Fp80m : X86::ST_FpP80m;
3677 case 16: {
3678 if (X86::VR128XRegClass.hasSubClassEq(RC)) {
3679 // If stack is realigned we can use aligned stores.
3680 if (IsStackAligned)
3681 return load ?
3682 (HasVLX ? X86::VMOVAPSZ128rm :
3683 HasAVX512 ? X86::VMOVAPSZ128rm_NOVLX :
3684 HasAVX ? X86::VMOVAPSrm :
3685 X86::MOVAPSrm):
3686 (HasVLX ? X86::VMOVAPSZ128mr :
3687 HasAVX512 ? X86::VMOVAPSZ128mr_NOVLX :
3688 HasAVX ? X86::VMOVAPSmr :
3689 X86::MOVAPSmr);
3690 else
3691 return load ?
3692 (HasVLX ? X86::VMOVUPSZ128rm :
3693 HasAVX512 ? X86::VMOVUPSZ128rm_NOVLX :
3694 HasAVX ? X86::VMOVUPSrm :
3695 X86::MOVUPSrm):
3696 (HasVLX ? X86::VMOVUPSZ128mr :
3697 HasAVX512 ? X86::VMOVUPSZ128mr_NOVLX :
3698 HasAVX ? X86::VMOVUPSmr :
3699 X86::MOVUPSmr);
3700 }
3701 if (X86::BNDRRegClass.hasSubClassEq(RC)) {
3702 if (STI.is64Bit())
3703 return load ? X86::BNDMOV64rm : X86::BNDMOV64mr;
3704 else
3705 return load ? X86::BNDMOV32rm : X86::BNDMOV32mr;
3706 }
3707 llvm_unreachable("Unknown 16-byte regclass")::llvm::llvm_unreachable_internal("Unknown 16-byte regclass",
"/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 3707)
;
3708 }
3709 case 32:
3710 assert(X86::VR256XRegClass.hasSubClassEq(RC) && "Unknown 32-byte regclass")(static_cast <bool> (X86::VR256XRegClass.hasSubClassEq(
RC) && "Unknown 32-byte regclass") ? void (0) : __assert_fail
("X86::VR256XRegClass.hasSubClassEq(RC) && \"Unknown 32-byte regclass\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 3710, __extension__ __PRETTY_FUNCTION__))
;
3711 // If stack is realigned we can use aligned stores.
3712 if (IsStackAligned)
3713 return load ?
3714 (HasVLX ? X86::VMOVAPSZ256rm :
3715 HasAVX512 ? X86::VMOVAPSZ256rm_NOVLX :
3716 X86::VMOVAPSYrm) :
3717 (HasVLX ? X86::VMOVAPSZ256mr :
3718 HasAVX512 ? X86::VMOVAPSZ256mr_NOVLX :
3719 X86::VMOVAPSYmr);
3720 else
3721 return load ?
3722 (HasVLX ? X86::VMOVUPSZ256rm :
3723 HasAVX512 ? X86::VMOVUPSZ256rm_NOVLX :
3724 X86::VMOVUPSYrm) :
3725 (HasVLX ? X86::VMOVUPSZ256mr :
3726 HasAVX512 ? X86::VMOVUPSZ256mr_NOVLX :
3727 X86::VMOVUPSYmr);
3728 case 64:
3729 assert(X86::VR512RegClass.hasSubClassEq(RC) && "Unknown 64-byte regclass")(static_cast <bool> (X86::VR512RegClass.hasSubClassEq(RC
) && "Unknown 64-byte regclass") ? void (0) : __assert_fail
("X86::VR512RegClass.hasSubClassEq(RC) && \"Unknown 64-byte regclass\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 3729, __extension__ __PRETTY_FUNCTION__))
;
3730 assert(STI.hasAVX512() && "Using 512-bit register requires AVX512")(static_cast <bool> (STI.hasAVX512() && "Using 512-bit register requires AVX512"
) ? void (0) : __assert_fail ("STI.hasAVX512() && \"Using 512-bit register requires AVX512\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 3730, __extension__ __PRETTY_FUNCTION__))
;
3731 if (IsStackAligned)
3732 return load ? X86::VMOVAPSZrm : X86::VMOVAPSZmr;
3733 else
3734 return load ? X86::VMOVUPSZrm : X86::VMOVUPSZmr;
3735 }
3736}
3737
3738Optional<ExtAddrMode>
3739X86InstrInfo::getAddrModeFromMemoryOp(const MachineInstr &MemI,
3740 const TargetRegisterInfo *TRI) const {
3741 const MCInstrDesc &Desc = MemI.getDesc();
3742 int MemRefBegin = X86II::getMemoryOperandNo(Desc.TSFlags);
3743 if (MemRefBegin < 0)
3744 return None;
3745
3746 MemRefBegin += X86II::getOperandBias(Desc);
3747
3748 auto &BaseOp = MemI.getOperand(MemRefBegin + X86::AddrBaseReg);
3749 if (!BaseOp.isReg()) // Can be an MO_FrameIndex
3750 return None;
3751
3752 const MachineOperand &DispMO = MemI.getOperand(MemRefBegin + X86::AddrDisp);
3753 // Displacement can be symbolic
3754 if (!DispMO.isImm())
3755 return None;
3756
3757 ExtAddrMode AM;
3758 AM.BaseReg = BaseOp.getReg();
3759 AM.ScaledReg = MemI.getOperand(MemRefBegin + X86::AddrIndexReg).getReg();
3760 AM.Scale = MemI.getOperand(MemRefBegin + X86::AddrScaleAmt).getImm();
3761 AM.Displacement = DispMO.getImm();
3762 return AM;
3763}
3764
3765bool X86InstrInfo::getConstValDefinedInReg(const MachineInstr &MI,
3766 const Register Reg,
3767 int64_t &ImmVal) const {
3768 if (MI.getOpcode() != X86::MOV32ri && MI.getOpcode() != X86::MOV64ri)
3769 return false;
3770 // Mov Src can be a global address.
3771 if (!MI.getOperand(1).isImm() || MI.getOperand(0).getReg() != Reg)
3772 return false;
3773 ImmVal = MI.getOperand(1).getImm();
3774 return true;
3775}
3776
3777bool X86InstrInfo::preservesZeroValueInReg(
3778 const MachineInstr *MI, const Register NullValueReg,
3779 const TargetRegisterInfo *TRI) const {
3780 if (!MI->modifiesRegister(NullValueReg, TRI))
3781 return true;
3782 switch (MI->getOpcode()) {
3783 // Shift right/left of a null unto itself is still a null, i.e. rax = shl rax
3784 // X.
3785 case X86::SHR64ri:
3786 case X86::SHR32ri:
3787 case X86::SHL64ri:
3788 case X86::SHL32ri:
3789 assert(MI->getOperand(0).isDef() && MI->getOperand(1).isUse() &&(static_cast <bool> (MI->getOperand(0).isDef() &&
MI->getOperand(1).isUse() && "expected for shift opcode!"
) ? void (0) : __assert_fail ("MI->getOperand(0).isDef() && MI->getOperand(1).isUse() && \"expected for shift opcode!\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 3790, __extension__ __PRETTY_FUNCTION__))
3790 "expected for shift opcode!")(static_cast <bool> (MI->getOperand(0).isDef() &&
MI->getOperand(1).isUse() && "expected for shift opcode!"
) ? void (0) : __assert_fail ("MI->getOperand(0).isDef() && MI->getOperand(1).isUse() && \"expected for shift opcode!\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 3790, __extension__ __PRETTY_FUNCTION__))
;
3791 return MI->getOperand(0).getReg() == NullValueReg &&
3792 MI->getOperand(1).getReg() == NullValueReg;
3793 // Zero extend of a sub-reg of NullValueReg into itself does not change the
3794 // null value.
3795 case X86::MOV32rr:
3796 return llvm::all_of(MI->operands(), [&](const MachineOperand &MO) {
3797 return TRI->isSubRegisterEq(NullValueReg, MO.getReg());
3798 });
3799 default:
3800 return false;
3801 }
3802 llvm_unreachable("Should be handled above!")::llvm::llvm_unreachable_internal("Should be handled above!",
"/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 3802)
;
3803}
3804
3805bool X86InstrInfo::getMemOperandsWithOffsetWidth(
3806 const MachineInstr &MemOp, SmallVectorImpl<const MachineOperand *> &BaseOps,
3807 int64_t &Offset, bool &OffsetIsScalable, unsigned &Width,
3808 const TargetRegisterInfo *TRI) const {
3809 const MCInstrDesc &Desc = MemOp.getDesc();
3810 int MemRefBegin = X86II::getMemoryOperandNo(Desc.TSFlags);
3811 if (MemRefBegin < 0)
3812 return false;
3813
3814 MemRefBegin += X86II::getOperandBias(Desc);
3815
3816 const MachineOperand *BaseOp =
3817 &MemOp.getOperand(MemRefBegin + X86::AddrBaseReg);
3818 if (!BaseOp->isReg()) // Can be an MO_FrameIndex
3819 return false;
3820
3821 if (MemOp.getOperand(MemRefBegin + X86::AddrScaleAmt).getImm() != 1)
3822 return false;
3823
3824 if (MemOp.getOperand(MemRefBegin + X86::AddrIndexReg).getReg() !=
3825 X86::NoRegister)
3826 return false;
3827
3828 const MachineOperand &DispMO = MemOp.getOperand(MemRefBegin + X86::AddrDisp);
3829
3830 // Displacement can be symbolic
3831 if (!DispMO.isImm())
3832 return false;
3833
3834 Offset = DispMO.getImm();
3835
3836 if (!BaseOp->isReg())
3837 return false;
3838
3839 OffsetIsScalable = false;
3840 // FIXME: Relying on memoperands() may not be right thing to do here. Check
3841 // with X86 maintainers, and fix it accordingly. For now, it is ok, since
3842 // there is no use of `Width` for X86 back-end at the moment.
3843 Width =
3844 !MemOp.memoperands_empty() ? MemOp.memoperands().front()->getSize() : 0;
3845 BaseOps.push_back(BaseOp);
3846 return true;
3847}
3848
3849static unsigned getStoreRegOpcode(Register SrcReg,
3850 const TargetRegisterClass *RC,
3851 bool IsStackAligned,
3852 const X86Subtarget &STI) {
3853 return getLoadStoreRegOpcode(SrcReg, RC, IsStackAligned, STI, false);
3854}
3855
3856static unsigned getLoadRegOpcode(Register DestReg,
3857 const TargetRegisterClass *RC,
3858 bool IsStackAligned, const X86Subtarget &STI) {
3859 return getLoadStoreRegOpcode(DestReg, RC, IsStackAligned, STI, true);
3860}
3861
3862void X86InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
3863 MachineBasicBlock::iterator MI,
3864 Register SrcReg, bool isKill, int FrameIdx,
3865 const TargetRegisterClass *RC,
3866 const TargetRegisterInfo *TRI) const {
3867 const MachineFunction &MF = *MBB.getParent();
3868 const MachineFrameInfo &MFI = MF.getFrameInfo();
3869 assert(MFI.getObjectSize(FrameIdx) >= TRI->getSpillSize(*RC) &&(static_cast <bool> (MFI.getObjectSize(FrameIdx) >= TRI
->getSpillSize(*RC) && "Stack slot too small for store"
) ? void (0) : __assert_fail ("MFI.getObjectSize(FrameIdx) >= TRI->getSpillSize(*RC) && \"Stack slot too small for store\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 3870, __extension__ __PRETTY_FUNCTION__))
3870 "Stack slot too small for store")(static_cast <bool> (MFI.getObjectSize(FrameIdx) >= TRI
->getSpillSize(*RC) && "Stack slot too small for store"
) ? void (0) : __assert_fail ("MFI.getObjectSize(FrameIdx) >= TRI->getSpillSize(*RC) && \"Stack slot too small for store\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 3870, __extension__ __PRETTY_FUNCTION__))
;
3871 if (RC->getID() == X86::TILERegClassID) {
3872 unsigned Opc = X86::TILESTORED;
3873 // tilestored %tmm, (%sp, %idx)
3874 MachineRegisterInfo &RegInfo = MBB.getParent()->getRegInfo();
3875 Register VirtReg = RegInfo.createVirtualRegister(&X86::GR64_NOSPRegClass);
3876 BuildMI(MBB, MI, DebugLoc(), get(X86::MOV64ri), VirtReg).addImm(64);
3877 MachineInstr *NewMI =
3878 addFrameReference(BuildMI(MBB, MI, DebugLoc(), get(Opc)), FrameIdx)
3879 .addReg(SrcReg, getKillRegState(isKill));
3880 MachineOperand &MO = NewMI->getOperand(2);
3881 MO.setReg(VirtReg);
3882 MO.setIsKill(true);
3883 } else {
3884 unsigned Alignment = std::max<uint32_t>(TRI->getSpillSize(*RC), 16);
3885 bool isAligned =
3886 (Subtarget.getFrameLowering()->getStackAlign() >= Alignment) ||
3887 (RI.canRealignStack(MF) && !MFI.isFixedObjectIndex(FrameIdx));
3888 unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, Subtarget);
3889 addFrameReference(BuildMI(MBB, MI, DebugLoc(), get(Opc)), FrameIdx)
3890 .addReg(SrcReg, getKillRegState(isKill));
3891 }
3892}
3893
3894void X86InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
3895 MachineBasicBlock::iterator MI,
3896 Register DestReg, int FrameIdx,
3897 const TargetRegisterClass *RC,
3898 const TargetRegisterInfo *TRI) const {
3899 if (RC->getID() == X86::TILERegClassID) {
3900 unsigned Opc = X86::TILELOADD;
3901 // tileloadd (%sp, %idx), %tmm
3902 MachineRegisterInfo &RegInfo = MBB.getParent()->getRegInfo();
3903 Register VirtReg = RegInfo.createVirtualRegister(&X86::GR64_NOSPRegClass);
3904 MachineInstr *NewMI =
Value stored to 'NewMI' during its initialization is never read
3905 BuildMI(MBB, MI, DebugLoc(), get(X86::MOV64ri), VirtReg).addImm(64);
3906 NewMI = addFrameReference(BuildMI(MBB, MI, DebugLoc(), get(Opc), DestReg),
3907 FrameIdx);
3908 MachineOperand &MO = NewMI->getOperand(3);
3909 MO.setReg(VirtReg);
3910 MO.setIsKill(true);
3911 } else {
3912 const MachineFunction &MF = *MBB.getParent();
3913 const MachineFrameInfo &MFI = MF.getFrameInfo();
3914 unsigned Alignment = std::max<uint32_t>(TRI->getSpillSize(*RC), 16);
3915 bool isAligned =
3916 (Subtarget.getFrameLowering()->getStackAlign() >= Alignment) ||
3917 (RI.canRealignStack(MF) && !MFI.isFixedObjectIndex(FrameIdx));
3918 unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, Subtarget);
3919 addFrameReference(BuildMI(MBB, MI, DebugLoc(), get(Opc), DestReg),
3920 FrameIdx);
3921 }
3922}
3923
3924bool X86InstrInfo::analyzeCompare(const MachineInstr &MI, Register &SrcReg,
3925 Register &SrcReg2, int &CmpMask,
3926 int &CmpValue) const {
3927 switch (MI.getOpcode()) {
3928 default: break;
3929 case X86::CMP64ri32:
3930 case X86::CMP64ri8:
3931 case X86::CMP32ri:
3932 case X86::CMP32ri8:
3933 case X86::CMP16ri:
3934 case X86::CMP16ri8:
3935 case X86::CMP8ri:
3936 SrcReg = MI.getOperand(0).getReg();
3937 SrcReg2 = 0;
3938 if (MI.getOperand(1).isImm()) {
3939 CmpMask = ~0;
3940 CmpValue = MI.getOperand(1).getImm();
3941 } else {
3942 CmpMask = CmpValue = 0;
3943 }
3944 return true;
3945 // A SUB can be used to perform comparison.
3946 case X86::SUB64rm:
3947 case X86::SUB32rm:
3948 case X86::SUB16rm:
3949 case X86::SUB8rm:
3950 SrcReg = MI.getOperand(1).getReg();
3951 SrcReg2 = 0;
3952 CmpMask = 0;
3953 CmpValue = 0;
3954 return true;
3955 case X86::SUB64rr:
3956 case X86::SUB32rr:
3957 case X86::SUB16rr:
3958 case X86::SUB8rr:
3959 SrcReg = MI.getOperand(1).getReg();
3960 SrcReg2 = MI.getOperand(2).getReg();
3961 CmpMask = 0;
3962 CmpValue = 0;
3963 return true;
3964 case X86::SUB64ri32:
3965 case X86::SUB64ri8:
3966 case X86::SUB32ri:
3967 case X86::SUB32ri8:
3968 case X86::SUB16ri:
3969 case X86::SUB16ri8:
3970 case X86::SUB8ri:
3971 SrcReg = MI.getOperand(1).getReg();
3972 SrcReg2 = 0;
3973 if (MI.getOperand(2).isImm()) {
3974 CmpMask = ~0;
3975 CmpValue = MI.getOperand(2).getImm();
3976 } else {
3977 CmpMask = CmpValue = 0;
3978 }
3979 return true;
3980 case X86::CMP64rr:
3981 case X86::CMP32rr:
3982 case X86::CMP16rr:
3983 case X86::CMP8rr:
3984 SrcReg = MI.getOperand(0).getReg();
3985 SrcReg2 = MI.getOperand(1).getReg();
3986 CmpMask = 0;
3987 CmpValue = 0;
3988 return true;
3989 case X86::TEST8rr:
3990 case X86::TEST16rr:
3991 case X86::TEST32rr:
3992 case X86::TEST64rr:
3993 SrcReg = MI.getOperand(0).getReg();
3994 if (MI.getOperand(1).getReg() != SrcReg)
3995 return false;
3996 // Compare against zero.
3997 SrcReg2 = 0;
3998 CmpMask = ~0;
3999 CmpValue = 0;
4000 return true;
4001 }
4002 return false;
4003}
4004
4005/// Check whether the first instruction, whose only
4006/// purpose is to update flags, can be made redundant.
4007/// CMPrr can be made redundant by SUBrr if the operands are the same.
4008/// This function can be extended later on.
4009/// SrcReg, SrcRegs: register operands for FlagI.
4010/// ImmValue: immediate for FlagI if it takes an immediate.
4011inline static bool isRedundantFlagInstr(const MachineInstr &FlagI,
4012 Register SrcReg, Register SrcReg2,
4013 int ImmMask, int ImmValue,
4014 const MachineInstr &OI) {
4015 if (((FlagI.getOpcode() == X86::CMP64rr && OI.getOpcode() == X86::SUB64rr) ||
4016 (FlagI.getOpcode() == X86::CMP32rr && OI.getOpcode() == X86::SUB32rr) ||
4017 (FlagI.getOpcode() == X86::CMP16rr && OI.getOpcode() == X86::SUB16rr) ||
4018 (FlagI.getOpcode() == X86::CMP8rr && OI.getOpcode() == X86::SUB8rr)) &&
4019 ((OI.getOperand(1).getReg() == SrcReg &&
4020 OI.getOperand(2).getReg() == SrcReg2) ||
4021 (OI.getOperand(1).getReg() == SrcReg2 &&
4022 OI.getOperand(2).getReg() == SrcReg)))
4023 return true;
4024
4025 if (ImmMask != 0 &&
4026 ((FlagI.getOpcode() == X86::CMP64ri32 &&
4027 OI.getOpcode() == X86::SUB64ri32) ||
4028 (FlagI.getOpcode() == X86::CMP64ri8 &&
4029 OI.getOpcode() == X86::SUB64ri8) ||
4030 (FlagI.getOpcode() == X86::CMP32ri && OI.getOpcode() == X86::SUB32ri) ||
4031 (FlagI.getOpcode() == X86::CMP32ri8 &&
4032 OI.getOpcode() == X86::SUB32ri8) ||
4033 (FlagI.getOpcode() == X86::CMP16ri && OI.getOpcode() == X86::SUB16ri) ||
4034 (FlagI.getOpcode() == X86::CMP16ri8 &&
4035 OI.getOpcode() == X86::SUB16ri8) ||
4036 (FlagI.getOpcode() == X86::CMP8ri && OI.getOpcode() == X86::SUB8ri)) &&
4037 OI.getOperand(1).getReg() == SrcReg &&
4038 OI.getOperand(2).getImm() == ImmValue)
4039 return true;
4040 return false;
4041}
4042
4043/// Check whether the definition can be converted
4044/// to remove a comparison against zero.
4045inline static bool isDefConvertible(const MachineInstr &MI, bool &NoSignFlag,
4046 bool &ClearsOverflowFlag) {
4047 NoSignFlag = false;
4048 ClearsOverflowFlag = false;
4049
4050 switch (MI.getOpcode()) {
4051 default: return false;
4052
4053 // The shift instructions only modify ZF if their shift count is non-zero.
4054 // N.B.: The processor truncates the shift count depending on the encoding.
4055 case X86::SAR8ri: case X86::SAR16ri: case X86::SAR32ri:case X86::SAR64ri:
4056 case X86::SHR8ri: case X86::SHR16ri: case X86::SHR32ri:case X86::SHR64ri:
4057 return getTruncatedShiftCount(MI, 2) != 0;
4058
4059 // Some left shift instructions can be turned into LEA instructions but only
4060 // if their flags aren't used. Avoid transforming such instructions.
4061 case X86::SHL8ri: case X86::SHL16ri: case X86::SHL32ri:case X86::SHL64ri:{
4062 unsigned ShAmt = getTruncatedShiftCount(MI, 2);
4063 if (isTruncatedShiftCountForLEA(ShAmt)) return false;
4064 return ShAmt != 0;
4065 }
4066
4067 case X86::SHRD16rri8:case X86::SHRD32rri8:case X86::SHRD64rri8:
4068 case X86::SHLD16rri8:case X86::SHLD32rri8:case X86::SHLD64rri8:
4069 return getTruncatedShiftCount(MI, 3) != 0;
4070
4071 case X86::SUB64ri32: case X86::SUB64ri8: case X86::SUB32ri:
4072 case X86::SUB32ri8: case X86::SUB16ri: case X86::SUB16ri8:
4073 case X86::SUB8ri: case X86::SUB64rr: case X86::SUB32rr:
4074 case X86::SUB16rr: case X86::SUB8rr: case X86::SUB64rm:
4075 case X86::SUB32rm: case X86::SUB16rm: case X86::SUB8rm:
4076 case X86::DEC64r: case X86::DEC32r: case X86::DEC16r: case X86::DEC8r:
4077 case X86::ADD64ri32: case X86::ADD64ri8: case X86::ADD32ri:
4078 case X86::ADD32ri8: case X86::ADD16ri: case X86::ADD16ri8:
4079 case X86::ADD8ri: case X86::ADD64rr: case X86::ADD32rr:
4080 case X86::ADD16rr: case X86::ADD8rr: case X86::ADD64rm:
4081 case X86::ADD32rm: case X86::ADD16rm: case X86::ADD8rm:
4082 case X86::INC64r: case X86::INC32r: case X86::INC16r: case X86::INC8r:
4083 case X86::ADC64ri32: case X86::ADC64ri8: case X86::ADC32ri:
4084 case X86::ADC32ri8: case X86::ADC16ri: case X86::ADC16ri8:
4085 case X86::ADC8ri: case X86::ADC64rr: case X86::ADC32rr:
4086 case X86::ADC16rr: case X86::ADC8rr: case X86::ADC64rm:
4087 case X86::ADC32rm: case X86::ADC16rm: case X86::ADC8rm:
4088 case X86::SBB64ri32: case X86::SBB64ri8: case X86::SBB32ri:
4089 case X86::SBB32ri8: case X86::SBB16ri: case X86::SBB16ri8:
4090 case X86::SBB8ri: case X86::SBB64rr: case X86::SBB32rr:
4091 case X86::SBB16rr: case X86::SBB8rr: case X86::SBB64rm:
4092 case X86::SBB32rm: case X86::SBB16rm: case X86::SBB8rm:
4093 case X86::NEG8r: case X86::NEG16r: case X86::NEG32r: case X86::NEG64r:
4094 case X86::SAR8r1: case X86::SAR16r1: case X86::SAR32r1:case X86::SAR64r1:
4095 case X86::SHR8r1: case X86::SHR16r1: case X86::SHR32r1:case X86::SHR64r1:
4096 case X86::SHL8r1: case X86::SHL16r1: case X86::SHL32r1:case X86::SHL64r1:
4097 case X86::LZCNT16rr: case X86::LZCNT16rm:
4098 case X86::LZCNT32rr: case X86::LZCNT32rm:
4099 case X86::LZCNT64rr: case X86::LZCNT64rm:
4100 case X86::POPCNT16rr:case X86::POPCNT16rm:
4101 case X86::POPCNT32rr:case X86::POPCNT32rm:
4102 case X86::POPCNT64rr:case X86::POPCNT64rm:
4103 case X86::TZCNT16rr: case X86::TZCNT16rm:
4104 case X86::TZCNT32rr: case X86::TZCNT32rm:
4105 case X86::TZCNT64rr: case X86::TZCNT64rm:
4106 return true;
4107 case X86::AND64ri32: case X86::AND64ri8: case X86::AND32ri:
4108 case X86::AND32ri8: case X86::AND16ri: case X86::AND16ri8:
4109 case X86::AND8ri: case X86::AND64rr: case X86::AND32rr:
4110 case X86::AND16rr: case X86::AND8rr: case X86::AND64rm:
4111 case X86::AND32rm: case X86::AND16rm: case X86::AND8rm:
4112 case X86::XOR64ri32: case X86::XOR64ri8: case X86::XOR32ri:
4113 case X86::XOR32ri8: case X86::XOR16ri: case X86::XOR16ri8:
4114 case X86::XOR8ri: case X86::XOR64rr: case X86::XOR32rr:
4115 case X86::XOR16rr: case X86::XOR8rr: case X86::XOR64rm:
4116 case X86::XOR32rm: case X86::XOR16rm: case X86::XOR8rm:
4117 case X86::OR64ri32: case X86::OR64ri8: case X86::OR32ri:
4118 case X86::OR32ri8: case X86::OR16ri: case X86::OR16ri8:
4119 case X86::OR8ri: case X86::OR64rr: case X86::OR32rr:
4120 case X86::OR16rr: case X86::OR8rr: case X86::OR64rm:
4121 case X86::OR32rm: case X86::OR16rm: case X86::OR8rm:
4122 case X86::ANDN32rr: case X86::ANDN32rm:
4123 case X86::ANDN64rr: case X86::ANDN64rm:
4124 case X86::BLSI32rr: case X86::BLSI32rm:
4125 case X86::BLSI64rr: case X86::BLSI64rm:
4126 case X86::BLSMSK32rr: case X86::BLSMSK32rm:
4127 case X86::BLSMSK64rr: case X86::BLSMSK64rm:
4128 case X86::BLSR32rr: case X86::BLSR32rm:
4129 case X86::BLSR64rr: case X86::BLSR64rm:
4130 case X86::BLCFILL32rr: case X86::BLCFILL32rm:
4131 case X86::BLCFILL64rr: case X86::BLCFILL64rm:
4132 case X86::BLCI32rr: case X86::BLCI32rm:
4133 case X86::BLCI64rr: case X86::BLCI64rm:
4134 case X86::BLCIC32rr: case X86::BLCIC32rm:
4135 case X86::BLCIC64rr: case X86::BLCIC64rm:
4136 case X86::BLCMSK32rr: case X86::BLCMSK32rm:
4137 case X86::BLCMSK64rr: case X86::BLCMSK64rm:
4138 case X86::BLCS32rr: case X86::BLCS32rm:
4139 case X86::BLCS64rr: case X86::BLCS64rm:
4140 case X86::BLSFILL32rr: case X86::BLSFILL32rm:
4141 case X86::BLSFILL64rr: case X86::BLSFILL64rm:
4142 case X86::BLSIC32rr: case X86::BLSIC32rm:
4143 case X86::BLSIC64rr: case X86::BLSIC64rm:
4144 case X86::BZHI32rr: case X86::BZHI32rm:
4145 case X86::BZHI64rr: case X86::BZHI64rm:
4146 case X86::T1MSKC32rr: case X86::T1MSKC32rm:
4147 case X86::T1MSKC64rr: case X86::T1MSKC64rm:
4148 case X86::TZMSK32rr: case X86::TZMSK32rm:
4149 case X86::TZMSK64rr: case X86::TZMSK64rm:
4150 // These instructions clear the overflow flag just like TEST.
4151 // FIXME: These are not the only instructions in this switch that clear the
4152 // overflow flag.
4153 ClearsOverflowFlag = true;
4154 return true;
4155 case X86::BEXTR32rr: case X86::BEXTR64rr:
4156 case X86::BEXTR32rm: case X86::BEXTR64rm:
4157 case X86::BEXTRI32ri: case X86::BEXTRI32mi:
4158 case X86::BEXTRI64ri: case X86::BEXTRI64mi:
4159 // BEXTR doesn't update the sign flag so we can't use it. It does clear
4160 // the overflow flag, but that's not useful without the sign flag.
4161 NoSignFlag = true;
4162 return true;
4163 }
4164}
4165
4166/// Check whether the use can be converted to remove a comparison against zero.
4167static X86::CondCode isUseDefConvertible(const MachineInstr &MI) {
4168 switch (MI.getOpcode()) {
4169 default: return X86::COND_INVALID;
4170 case X86::NEG8r:
4171 case X86::NEG16r:
4172 case X86::NEG32r:
4173 case X86::NEG64r:
4174 return X86::COND_AE;
4175 case X86::LZCNT16rr:
4176 case X86::LZCNT32rr:
4177 case X86::LZCNT64rr:
4178 return X86::COND_B;
4179 case X86::POPCNT16rr:
4180 case X86::POPCNT32rr:
4181 case X86::POPCNT64rr:
4182 return X86::COND_E;
4183 case X86::TZCNT16rr:
4184 case X86::TZCNT32rr:
4185 case X86::TZCNT64rr:
4186 return X86::COND_B;
4187 case X86::BSF16rr:
4188 case X86::BSF32rr:
4189 case X86::BSF64rr:
4190 case X86::BSR16rr:
4191 case X86::BSR32rr:
4192 case X86::BSR64rr:
4193 return X86::COND_E;
4194 case X86::BLSI32rr:
4195 case X86::BLSI64rr:
4196 return X86::COND_AE;
4197 case X86::BLSR32rr:
4198 case X86::BLSR64rr:
4199 case X86::BLSMSK32rr:
4200 case X86::BLSMSK64rr:
4201 return X86::COND_B;
4202 // TODO: TBM instructions.
4203 }
4204}
4205
4206/// Check if there exists an earlier instruction that
4207/// operates on the same source operands and sets flags in the same way as
4208/// Compare; remove Compare if possible.
4209bool X86InstrInfo::optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg,
4210 Register SrcReg2, int CmpMask,
4211 int CmpValue,
4212 const MachineRegisterInfo *MRI) const {
4213 // Check whether we can replace SUB with CMP.
4214 switch (CmpInstr.getOpcode()) {
4215 default: break;
4216 case X86::SUB64ri32:
4217 case X86::SUB64ri8:
4218 case X86::SUB32ri:
4219 case X86::SUB32ri8:
4220 case X86::SUB16ri:
4221 case X86::SUB16ri8:
4222 case X86::SUB8ri:
4223 case X86::SUB64rm:
4224 case X86::SUB32rm:
4225 case X86::SUB16rm:
4226 case X86::SUB8rm:
4227 case X86::SUB64rr:
4228 case X86::SUB32rr:
4229 case X86::SUB16rr:
4230 case X86::SUB8rr: {
4231 if (!MRI->use_nodbg_empty(CmpInstr.getOperand(0).getReg()))
4232 return false;
4233 // There is no use of the destination register, we can replace SUB with CMP.
4234 unsigned NewOpcode = 0;
4235 switch (CmpInstr.getOpcode()) {
4236 default: llvm_unreachable("Unreachable!")::llvm::llvm_unreachable_internal("Unreachable!", "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 4236)
;
4237 case X86::SUB64rm: NewOpcode = X86::CMP64rm; break;
4238 case X86::SUB32rm: NewOpcode = X86::CMP32rm; break;
4239 case X86::SUB16rm: NewOpcode = X86::CMP16rm; break;
4240 case X86::SUB8rm: NewOpcode = X86::CMP8rm; break;
4241 case X86::SUB64rr: NewOpcode = X86::CMP64rr; break;
4242 case X86::SUB32rr: NewOpcode = X86::CMP32rr; break;
4243 case X86::SUB16rr: NewOpcode = X86::CMP16rr; break;
4244 case X86::SUB8rr: NewOpcode = X86::CMP8rr; break;
4245 case X86::SUB64ri32: NewOpcode = X86::CMP64ri32; break;
4246 case X86::SUB64ri8: NewOpcode = X86::CMP64ri8; break;
4247 case X86::SUB32ri: NewOpcode = X86::CMP32ri; break;
4248 case X86::SUB32ri8: NewOpcode = X86::CMP32ri8; break;
4249 case X86::SUB16ri: NewOpcode = X86::CMP16ri; break;
4250 case X86::SUB16ri8: NewOpcode = X86::CMP16ri8; break;
4251 case X86::SUB8ri: NewOpcode = X86::CMP8ri; break;
4252 }
4253 CmpInstr.setDesc(get(NewOpcode));
4254 CmpInstr.RemoveOperand(0);
4255 // Mutating this instruction invalidates any debug data associated with it.
4256 CmpInstr.dropDebugNumber();
4257 // Fall through to optimize Cmp if Cmp is CMPrr or CMPri.
4258 if (NewOpcode == X86::CMP64rm || NewOpcode == X86::CMP32rm ||
4259 NewOpcode == X86::CMP16rm || NewOpcode == X86::CMP8rm)
4260 return false;
4261 }
4262 }
4263
4264 // Get the unique definition of SrcReg.
4265 MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg);
4266 if (!MI) return false;
4267
4268 // CmpInstr is the first instruction of the BB.
4269 MachineBasicBlock::iterator I = CmpInstr, Def = MI;
4270
4271 // If we are comparing against zero, check whether we can use MI to update
4272 // EFLAGS. If MI is not in the same BB as CmpInstr, do not optimize.
4273 bool IsCmpZero = (CmpMask != 0 && CmpValue == 0);
4274 if (IsCmpZero && MI->getParent() != CmpInstr.getParent())
4275 return false;
4276
4277 // If we have a use of the source register between the def and our compare
4278 // instruction we can eliminate the compare iff the use sets EFLAGS in the
4279 // right way.
4280 bool ShouldUpdateCC = false;
4281 bool NoSignFlag = false;
4282 bool ClearsOverflowFlag = false;
4283 X86::CondCode NewCC = X86::COND_INVALID;
4284 if (IsCmpZero && !isDefConvertible(*MI, NoSignFlag, ClearsOverflowFlag)) {
4285 // Scan forward from the use until we hit the use we're looking for or the
4286 // compare instruction.
4287 for (MachineBasicBlock::iterator J = MI;; ++J) {
4288 // Do we have a convertible instruction?
4289 NewCC = isUseDefConvertible(*J);
4290 if (NewCC != X86::COND_INVALID && J->getOperand(1).isReg() &&
4291 J->getOperand(1).getReg() == SrcReg) {
4292 assert(J->definesRegister(X86::EFLAGS) && "Must be an EFLAGS def!")(static_cast <bool> (J->definesRegister(X86::EFLAGS)
&& "Must be an EFLAGS def!") ? void (0) : __assert_fail
("J->definesRegister(X86::EFLAGS) && \"Must be an EFLAGS def!\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 4292, __extension__ __PRETTY_FUNCTION__))
;
4293 ShouldUpdateCC = true; // Update CC later on.
4294 // This is not a def of SrcReg, but still a def of EFLAGS. Keep going
4295 // with the new def.
4296 Def = J;
4297 MI = &*Def;
4298 break;
4299 }
4300
4301 if (J == I)
4302 return false;
4303 }
4304 }
4305
4306 // We are searching for an earlier instruction that can make CmpInstr
4307 // redundant and that instruction will be saved in Sub.
4308 MachineInstr *Sub = nullptr;
4309 const TargetRegisterInfo *TRI = &getRegisterInfo();
4310
4311 // We iterate backward, starting from the instruction before CmpInstr and
4312 // stop when reaching the definition of a source register or done with the BB.
4313 // RI points to the instruction before CmpInstr.
4314 // If the definition is in this basic block, RE points to the definition;
4315 // otherwise, RE is the rend of the basic block.
4316 MachineBasicBlock::reverse_iterator
4317 RI = ++I.getReverse(),
4318 RE = CmpInstr.getParent() == MI->getParent()
4319 ? Def.getReverse() /* points to MI */
4320 : CmpInstr.getParent()->rend();
4321 MachineInstr *Movr0Inst = nullptr;
4322 for (; RI != RE; ++RI) {
4323 MachineInstr &Instr = *RI;
4324 // Check whether CmpInstr can be made redundant by the current instruction.
4325 if (!IsCmpZero && isRedundantFlagInstr(CmpInstr, SrcReg, SrcReg2, CmpMask,
4326 CmpValue, Instr)) {
4327 Sub = &Instr;
4328 break;
4329 }
4330
4331 if (Instr.modifiesRegister(X86::EFLAGS, TRI) ||
4332 Instr.readsRegister(X86::EFLAGS, TRI)) {
4333 // This instruction modifies or uses EFLAGS.
4334
4335 // MOV32r0 etc. are implemented with xor which clobbers condition code.
4336 // They are safe to move up, if the definition to EFLAGS is dead and
4337 // earlier instructions do not read or write EFLAGS.
4338 if (!Movr0Inst && Instr.getOpcode() == X86::MOV32r0 &&
4339 Instr.registerDefIsDead(X86::EFLAGS, TRI)) {
4340 Movr0Inst = &Instr;
4341 continue;
4342 }
4343
4344 // We can't remove CmpInstr.
4345 return false;
4346 }
4347 }
4348
4349 // Return false if no candidates exist.
4350 if (!IsCmpZero && !Sub)
4351 return false;
4352
4353 bool IsSwapped =
4354 (SrcReg2 != 0 && Sub && Sub->getOperand(1).getReg() == SrcReg2 &&
4355 Sub->getOperand(2).getReg() == SrcReg);
4356
4357 // Scan forward from the instruction after CmpInstr for uses of EFLAGS.
4358 // It is safe to remove CmpInstr if EFLAGS is redefined or killed.
4359 // If we are done with the basic block, we need to check whether EFLAGS is
4360 // live-out.
4361 bool IsSafe = false;
4362 SmallVector<std::pair<MachineInstr*, X86::CondCode>, 4> OpsToUpdate;
4363 MachineBasicBlock::iterator E = CmpInstr.getParent()->end();
4364 for (++I; I != E; ++I) {
4365 const MachineInstr &Instr = *I;
4366 bool ModifyEFLAGS = Instr.modifiesRegister(X86::EFLAGS, TRI);
4367 bool UseEFLAGS = Instr.readsRegister(X86::EFLAGS, TRI);
4368 // We should check the usage if this instruction uses and updates EFLAGS.
4369 if (!UseEFLAGS && ModifyEFLAGS) {
4370 // It is safe to remove CmpInstr if EFLAGS is updated again.
4371 IsSafe = true;
4372 break;
4373 }
4374 if (!UseEFLAGS && !ModifyEFLAGS)
4375 continue;
4376
4377 // EFLAGS is used by this instruction.
4378 X86::CondCode OldCC = X86::COND_INVALID;
4379 if (IsCmpZero || IsSwapped) {
4380 // We decode the condition code from opcode.
4381 if (Instr.isBranch())
4382 OldCC = X86::getCondFromBranch(Instr);
4383 else {
4384 OldCC = X86::getCondFromSETCC(Instr);
4385 if (OldCC == X86::COND_INVALID)
4386 OldCC = X86::getCondFromCMov(Instr);
4387 }
4388 if (OldCC == X86::COND_INVALID) return false;
4389 }
4390 X86::CondCode ReplacementCC = X86::COND_INVALID;
4391 if (IsCmpZero) {
4392 switch (OldCC) {
4393 default: break;
4394 case X86::COND_A: case X86::COND_AE:
4395 case X86::COND_B: case X86::COND_BE:
4396 // CF is used, we can't perform this optimization.
4397 return false;
4398 case X86::COND_G: case X86::COND_GE:
4399 case X86::COND_L: case X86::COND_LE:
4400 case X86::COND_O: case X86::COND_NO:
4401 // If OF is used, the instruction needs to clear it like CmpZero does.
4402 if (!ClearsOverflowFlag)
4403 return false;
4404 break;
4405 case X86::COND_S: case X86::COND_NS:
4406 // If SF is used, but the instruction doesn't update the SF, then we
4407 // can't do the optimization.
4408 if (NoSignFlag)
4409 return false;
4410 break;
4411 }
4412
4413 // If we're updating the condition code check if we have to reverse the
4414 // condition.
4415 if (ShouldUpdateCC)
4416 switch (OldCC) {
4417 default:
4418 return false;
4419 case X86::COND_E:
4420 ReplacementCC = NewCC;
4421 break;
4422 case X86::COND_NE:
4423 ReplacementCC = GetOppositeBranchCondition(NewCC);
4424 break;
4425 }
4426 } else if (IsSwapped) {
4427 // If we have SUB(r1, r2) and CMP(r2, r1), the condition code needs
4428 // to be changed from r2 > r1 to r1 < r2, from r2 < r1 to r1 > r2, etc.
4429 // We swap the condition code and synthesize the new opcode.
4430 ReplacementCC = getSwappedCondition(OldCC);
4431 if (ReplacementCC == X86::COND_INVALID) return false;
4432 }
4433
4434 if ((ShouldUpdateCC || IsSwapped) && ReplacementCC != OldCC) {
4435 // Push the MachineInstr to OpsToUpdate.
4436 // If it is safe to remove CmpInstr, the condition code of these
4437 // instructions will be modified.
4438 OpsToUpdate.push_back(std::make_pair(&*I, ReplacementCC));
4439 }
4440 if (ModifyEFLAGS || Instr.killsRegister(X86::EFLAGS, TRI)) {
4441 // It is safe to remove CmpInstr if EFLAGS is updated again or killed.
4442 IsSafe = true;
4443 break;
4444 }
4445 }
4446
4447 // If EFLAGS is not killed nor re-defined, we should check whether it is
4448 // live-out. If it is live-out, do not optimize.
4449 if ((IsCmpZero || IsSwapped) && !IsSafe) {
4450 MachineBasicBlock *MBB = CmpInstr.getParent();
4451 for (MachineBasicBlock *Successor : MBB->successors())
4452 if (Successor->isLiveIn(X86::EFLAGS))
4453 return false;
4454 }
4455
4456 // The instruction to be updated is either Sub or MI.
4457 Sub = IsCmpZero ? MI : Sub;
4458 // Move Movr0Inst to the appropriate place before Sub.
4459 if (Movr0Inst) {
4460 // Look backwards until we find a def that doesn't use the current EFLAGS.
4461 Def = Sub;
4462 MachineBasicBlock::reverse_iterator InsertI = Def.getReverse(),
4463 InsertE = Sub->getParent()->rend();
4464 for (; InsertI != InsertE; ++InsertI) {
4465 MachineInstr *Instr = &*InsertI;
4466 if (!Instr->readsRegister(X86::EFLAGS, TRI) &&
4467 Instr->modifiesRegister(X86::EFLAGS, TRI)) {
4468 Sub->getParent()->remove(Movr0Inst);
4469 Instr->getParent()->insert(MachineBasicBlock::iterator(Instr),
4470 Movr0Inst);
4471 break;
4472 }
4473 }
4474 if (InsertI == InsertE)
4475 return false;
4476 }
4477
4478 // Make sure Sub instruction defines EFLAGS and mark the def live.
4479 MachineOperand *FlagDef = Sub->findRegisterDefOperand(X86::EFLAGS);
4480 assert(FlagDef && "Unable to locate a def EFLAGS operand")(static_cast <bool> (FlagDef && "Unable to locate a def EFLAGS operand"
) ? void (0) : __assert_fail ("FlagDef && \"Unable to locate a def EFLAGS operand\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 4480, __extension__ __PRETTY_FUNCTION__))
;
4481 FlagDef->setIsDead(false);
4482
4483 CmpInstr.eraseFromParent();
4484
4485 // Modify the condition code of instructions in OpsToUpdate.
4486 for (auto &Op : OpsToUpdate) {
4487 Op.first->getOperand(Op.first->getDesc().getNumOperands() - 1)
4488 .setImm(Op.second);
4489 }
4490 return true;
4491}
4492
4493/// Try to remove the load by folding it to a register
4494/// operand at the use. We fold the load instructions if load defines a virtual
4495/// register, the virtual register is used once in the same BB, and the
4496/// instructions in-between do not load or store, and have no side effects.
4497MachineInstr *X86InstrInfo::optimizeLoadInstr(MachineInstr &MI,
4498 const MachineRegisterInfo *MRI,
4499 Register &FoldAsLoadDefReg,
4500 MachineInstr *&DefMI) const {
4501 // Check whether we can move DefMI here.
4502 DefMI = MRI->getVRegDef(FoldAsLoadDefReg);
4503 assert(DefMI)(static_cast <bool> (DefMI) ? void (0) : __assert_fail (
"DefMI", "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 4503, __extension__ __PRETTY_FUNCTION__))
;
4504 bool SawStore = false;
4505 if (!DefMI->isSafeToMove(nullptr, SawStore))
4506 return nullptr;
4507
4508 // Collect information about virtual register operands of MI.
4509 SmallVector<unsigned, 1> SrcOperandIds;
4510 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
4511 MachineOperand &MO = MI.getOperand(i);
4512 if (!MO.isReg())
4513 continue;
4514 Register Reg = MO.getReg();
4515 if (Reg != FoldAsLoadDefReg)
4516 continue;
4517 // Do not fold if we have a subreg use or a def.
4518 if (MO.getSubReg() || MO.isDef())
4519 return nullptr;
4520 SrcOperandIds.push_back(i);
4521 }
4522 if (SrcOperandIds.empty())
4523 return nullptr;
4524
4525 // Check whether we can fold the def into SrcOperandId.
4526 if (MachineInstr *FoldMI = foldMemoryOperand(MI, SrcOperandIds, *DefMI)) {
4527 FoldAsLoadDefReg = 0;
4528 return FoldMI;
4529 }
4530
4531 return nullptr;
4532}
4533
4534/// Expand a single-def pseudo instruction to a two-addr
4535/// instruction with two undef reads of the register being defined.
4536/// This is used for mapping:
4537/// %xmm4 = V_SET0
4538/// to:
4539/// %xmm4 = PXORrr undef %xmm4, undef %xmm4
4540///
4541static bool Expand2AddrUndef(MachineInstrBuilder &MIB,
4542 const MCInstrDesc &Desc) {
4543 assert(Desc.getNumOperands() == 3 && "Expected two-addr instruction.")(static_cast <bool> (Desc.getNumOperands() == 3 &&
"Expected two-addr instruction.") ? void (0) : __assert_fail
("Desc.getNumOperands() == 3 && \"Expected two-addr instruction.\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 4543, __extension__ __PRETTY_FUNCTION__))
;
4544 Register Reg = MIB.getReg(0);
4545 MIB->setDesc(Desc);
4546
4547 // MachineInstr::addOperand() will insert explicit operands before any
4548 // implicit operands.
4549 MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef);
4550 // But we don't trust that.
4551 assert(MIB.getReg(1) == Reg &&(static_cast <bool> (MIB.getReg(1) == Reg && MIB
.getReg(2) == Reg && "Misplaced operand") ? void (0) :
__assert_fail ("MIB.getReg(1) == Reg && MIB.getReg(2) == Reg && \"Misplaced operand\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 4552, __extension__ __PRETTY_FUNCTION__))
4552 MIB.getReg(2) == Reg && "Misplaced operand")(static_cast <bool> (MIB.getReg(1) == Reg && MIB
.getReg(2) == Reg && "Misplaced operand") ? void (0) :
__assert_fail ("MIB.getReg(1) == Reg && MIB.getReg(2) == Reg && \"Misplaced operand\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 4552, __extension__ __PRETTY_FUNCTION__))
;
4553 return true;
4554}
4555
4556/// Expand a single-def pseudo instruction to a two-addr
4557/// instruction with two %k0 reads.
4558/// This is used for mapping:
4559/// %k4 = K_SET1
4560/// to:
4561/// %k4 = KXNORrr %k0, %k0
4562static bool Expand2AddrKreg(MachineInstrBuilder &MIB, const MCInstrDesc &Desc,
4563 Register Reg) {
4564 assert(Desc.getNumOperands() == 3 && "Expected two-addr instruction.")(static_cast <bool> (Desc.getNumOperands() == 3 &&
"Expected two-addr instruction.") ? void (0) : __assert_fail
("Desc.getNumOperands() == 3 && \"Expected two-addr instruction.\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 4564, __extension__ __PRETTY_FUNCTION__))
;
4565 MIB->setDesc(Desc);
4566 MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef);
4567 return true;
4568}
4569
4570static bool expandMOV32r1(MachineInstrBuilder &MIB, const TargetInstrInfo &TII,
4571 bool MinusOne) {
4572 MachineBasicBlock &MBB = *MIB->getParent();
4573 const DebugLoc &DL = MIB->getDebugLoc();
4574 Register Reg = MIB.getReg(0);
4575
4576 // Insert the XOR.
4577 BuildMI(MBB, MIB.getInstr(), DL, TII.get(X86::XOR32rr), Reg)
4578 .addReg(Reg, RegState::Undef)
4579 .addReg(Reg, RegState::Undef);
4580
4581 // Turn the pseudo into an INC or DEC.
4582 MIB->setDesc(TII.get(MinusOne ? X86::DEC32r : X86::INC32r));
4583 MIB.addReg(Reg);
4584
4585 return true;
4586}
4587
4588static bool ExpandMOVImmSExti8(MachineInstrBuilder &MIB,
4589 const TargetInstrInfo &TII,
4590 const X86Subtarget &Subtarget) {
4591 MachineBasicBlock &MBB = *MIB->getParent();
4592 const DebugLoc &DL = MIB->getDebugLoc();
4593 int64_t Imm = MIB->getOperand(1).getImm();
4594 assert(Imm != 0 && "Using push/pop for 0 is not efficient.")(static_cast <bool> (Imm != 0 && "Using push/pop for 0 is not efficient."
) ? void (0) : __assert_fail ("Imm != 0 && \"Using push/pop for 0 is not efficient.\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 4594, __extension__ __PRETTY_FUNCTION__))
;
4595 MachineBasicBlock::iterator I = MIB.getInstr();
4596
4597 int StackAdjustment;
4598
4599 if (Subtarget.is64Bit()) {
4600 assert(MIB->getOpcode() == X86::MOV64ImmSExti8 ||(static_cast <bool> (MIB->getOpcode() == X86::MOV64ImmSExti8
|| MIB->getOpcode() == X86::MOV32ImmSExti8) ? void (0) : __assert_fail
("MIB->getOpcode() == X86::MOV64ImmSExti8 || MIB->getOpcode() == X86::MOV32ImmSExti8"
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 4601, __extension__ __PRETTY_FUNCTION__))
4601 MIB->getOpcode() == X86::MOV32ImmSExti8)(static_cast <bool> (MIB->getOpcode() == X86::MOV64ImmSExti8
|| MIB->getOpcode() == X86::MOV32ImmSExti8) ? void (0) : __assert_fail
("MIB->getOpcode() == X86::MOV64ImmSExti8 || MIB->getOpcode() == X86::MOV32ImmSExti8"
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 4601, __extension__ __PRETTY_FUNCTION__))
;
4602
4603 // Can't use push/pop lowering if the function might write to the red zone.
4604 X86MachineFunctionInfo *X86FI =
4605 MBB.getParent()->getInfo<X86MachineFunctionInfo>();
4606 if (X86FI->getUsesRedZone()) {
4607 MIB->setDesc(TII.get(MIB->getOpcode() ==
4608 X86::MOV32ImmSExti8 ? X86::MOV32ri : X86::MOV64ri));
4609 return true;
4610 }
4611
4612 // 64-bit mode doesn't have 32-bit push/pop, so use 64-bit operations and
4613 // widen the register if necessary.
4614 StackAdjustment = 8;
4615 BuildMI(MBB, I, DL, TII.get(X86::PUSH64i8)).addImm(Imm);
4616 MIB->setDesc(TII.get(X86::POP64r));
4617 MIB->getOperand(0)
4618 .setReg(getX86SubSuperRegister(MIB.getReg(0), 64));
4619 } else {
4620 assert(MIB->getOpcode() == X86::MOV32ImmSExti8)(static_cast <bool> (MIB->getOpcode() == X86::MOV32ImmSExti8
) ? void (0) : __assert_fail ("MIB->getOpcode() == X86::MOV32ImmSExti8"
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 4620, __extension__ __PRETTY_FUNCTION__))
;
4621 StackAdjustment = 4;
4622 BuildMI(MBB, I, DL, TII.get(X86::PUSH32i8)).addImm(Imm);
4623 MIB->setDesc(TII.get(X86::POP32r));
4624 }
4625 MIB->RemoveOperand(1);
4626 MIB->addImplicitDefUseOperands(*MBB.getParent());
4627
4628 // Build CFI if necessary.
4629 MachineFunction &MF = *MBB.getParent();
4630 const X86FrameLowering *TFL = Subtarget.getFrameLowering();
4631 bool IsWin64Prologue = MF.getTarget().getMCAsmInfo()->usesWindowsCFI();
4632 bool NeedsDwarfCFI = !IsWin64Prologue && MF.needsFrameMoves();
4633 bool EmitCFI = !TFL->hasFP(MF) && NeedsDwarfCFI;
4634 if (EmitCFI) {
4635 TFL->BuildCFI(MBB, I, DL,
4636 MCCFIInstruction::createAdjustCfaOffset(nullptr, StackAdjustment));
4637 TFL->BuildCFI(MBB, std::next(I), DL,
4638 MCCFIInstruction::createAdjustCfaOffset(nullptr, -StackAdjustment));
4639 }
4640
4641 return true;
4642}
4643
4644// LoadStackGuard has so far only been implemented for 64-bit MachO. Different
4645// code sequence is needed for other targets.
4646static void expandLoadStackGuard(MachineInstrBuilder &MIB,
4647 const TargetInstrInfo &TII) {
4648 MachineBasicBlock &MBB = *MIB->getParent();
4649 const DebugLoc &DL = MIB->getDebugLoc();
4650 Register Reg = MIB.getReg(0);
4651 const GlobalValue *GV =
4652 cast<GlobalValue>((*MIB->memoperands_begin())->getValue());
4653 auto Flags = MachineMemOperand::MOLoad |
4654 MachineMemOperand::MODereferenceable |
4655 MachineMemOperand::MOInvariant;
4656 MachineMemOperand *MMO = MBB.getParent()->getMachineMemOperand(
4657 MachinePointerInfo::getGOT(*MBB.getParent()), Flags, 8, Align(8));
4658 MachineBasicBlock::iterator I = MIB.getInstr();
4659
4660 BuildMI(MBB, I, DL, TII.get(X86::MOV64rm), Reg).addReg(X86::RIP).addImm(1)
4661 .addReg(0).addGlobalAddress(GV, 0, X86II::MO_GOTPCREL).addReg(0)
4662 .addMemOperand(MMO);
4663 MIB->setDebugLoc(DL);
4664 MIB->setDesc(TII.get(X86::MOV64rm));
4665 MIB.addReg(Reg, RegState::Kill).addImm(1).addReg(0).addImm(0).addReg(0);
4666}
4667
4668static bool expandXorFP(MachineInstrBuilder &MIB, const TargetInstrInfo &TII) {
4669 MachineBasicBlock &MBB = *MIB->getParent();
4670 MachineFunction &MF = *MBB.getParent();
4671 const X86Subtarget &Subtarget = MF.getSubtarget<X86Subtarget>();
4672 const X86RegisterInfo *TRI = Subtarget.getRegisterInfo();
4673 unsigned XorOp =
4674 MIB->getOpcode() == X86::XOR64_FP ? X86::XOR64rr : X86::XOR32rr;
4675 MIB->setDesc(TII.get(XorOp));
4676 MIB.addReg(TRI->getFrameRegister(MF), RegState::Undef);
4677 return true;
4678}
4679
4680// This is used to handle spills for 128/256-bit registers when we have AVX512,
4681// but not VLX. If it uses an extended register we need to use an instruction
4682// that loads the lower 128/256-bit, but is available with only AVX512F.
4683static bool expandNOVLXLoad(MachineInstrBuilder &MIB,
4684 const TargetRegisterInfo *TRI,
4685 const MCInstrDesc &LoadDesc,
4686 const MCInstrDesc &BroadcastDesc,
4687 unsigned SubIdx) {
4688 Register DestReg = MIB.getReg(0);
4689 // Check if DestReg is XMM16-31 or YMM16-31.
4690 if (TRI->getEncodingValue(DestReg) < 16) {
4691 // We can use a normal VEX encoded load.
4692 MIB->setDesc(LoadDesc);
4693 } else {
4694 // Use a 128/256-bit VBROADCAST instruction.
4695 MIB->setDesc(BroadcastDesc);
4696 // Change the destination to a 512-bit register.
4697 DestReg = TRI->getMatchingSuperReg(DestReg, SubIdx, &X86::VR512RegClass);
4698 MIB->getOperand(0).setReg(DestReg);
4699 }
4700 return true;
4701}
4702
4703// This is used to handle spills for 128/256-bit registers when we have AVX512,
4704// but not VLX. If it uses an extended register we need to use an instruction
4705// that stores the lower 128/256-bit, but is available with only AVX512F.
4706static bool expandNOVLXStore(MachineInstrBuilder &MIB,
4707 const TargetRegisterInfo *TRI,
4708 const MCInstrDesc &StoreDesc,
4709 const MCInstrDesc &ExtractDesc,
4710 unsigned SubIdx) {
4711 Register SrcReg = MIB.getReg(X86::AddrNumOperands);
4712 // Check if DestReg is XMM16-31 or YMM16-31.
4713 if (TRI->getEncodingValue(SrcReg) < 16) {
4714 // We can use a normal VEX encoded store.
4715 MIB->setDesc(StoreDesc);
4716 } else {
4717 // Use a VEXTRACTF instruction.
4718 MIB->setDesc(ExtractDesc);
4719 // Change the destination to a 512-bit register.
4720 SrcReg = TRI->getMatchingSuperReg(SrcReg, SubIdx, &X86::VR512RegClass);
4721 MIB->getOperand(X86::AddrNumOperands).setReg(SrcReg);
4722 MIB.addImm(0x0); // Append immediate to extract from the lower bits.
4723 }
4724
4725 return true;
4726}
4727
4728static bool expandSHXDROT(MachineInstrBuilder &MIB, const MCInstrDesc &Desc) {
4729 MIB->setDesc(Desc);
4730 int64_t ShiftAmt = MIB->getOperand(2).getImm();
4731 // Temporarily remove the immediate so we can add another source register.
4732 MIB->RemoveOperand(2);
4733 // Add the register. Don't copy the kill flag if there is one.
4734 MIB.addReg(MIB.getReg(1),
4735 getUndefRegState(MIB->getOperand(1).isUndef()));
4736 // Add back the immediate.
4737 MIB.addImm(ShiftAmt);
4738 return true;
4739}
4740
4741bool X86InstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
4742 bool HasAVX = Subtarget.hasAVX();
4743 MachineInstrBuilder MIB(*MI.getParent()->getParent(), MI);
4744 switch (MI.getOpcode()) {
4745 case X86::MOV32r0:
4746 return Expand2AddrUndef(MIB, get(X86::XOR32rr));
4747 case X86::MOV32r1:
4748 return expandMOV32r1(MIB, *this, /*MinusOne=*/ false);
4749 case X86::MOV32r_1:
4750 return expandMOV32r1(MIB, *this, /*MinusOne=*/ true);
4751 case X86::MOV32ImmSExti8:
4752 case X86::MOV64ImmSExti8:
4753 return ExpandMOVImmSExti8(MIB, *this, Subtarget);
4754 case X86::SETB_C32r:
4755 return Expand2AddrUndef(MIB, get(X86::SBB32rr));
4756 case X86::SETB_C64r:
4757 return Expand2AddrUndef(MIB, get(X86::SBB64rr));
4758 case X86::MMX_SET0:
4759 return Expand2AddrUndef(MIB, get(X86::MMX_PXORirr));
4760 case X86::V_SET0:
4761 case X86::FsFLD0SS:
4762 case X86::FsFLD0SD:
4763 case X86::FsFLD0F128:
4764 return Expand2AddrUndef(MIB, get(HasAVX ? X86::VXORPSrr : X86::XORPSrr));
4765 case X86::AVX_SET0: {
4766 assert(HasAVX && "AVX not supported")(static_cast <bool> (HasAVX && "AVX not supported"
) ? void (0) : __assert_fail ("HasAVX && \"AVX not supported\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 4766, __extension__ __PRETTY_FUNCTION__))
;
4767 const TargetRegisterInfo *TRI = &getRegisterInfo();
4768 Register SrcReg = MIB.getReg(0);
4769 Register XReg = TRI->getSubReg(SrcReg, X86::sub_xmm);
4770 MIB->getOperand(0).setReg(XReg);
4771 Expand2AddrUndef(MIB, get(X86::VXORPSrr));
4772 MIB.addReg(SrcReg, RegState::ImplicitDefine);
4773 return true;
4774 }
4775 case X86::AVX512_128_SET0:
4776 case X86::AVX512_FsFLD0SH:
4777 case X86::AVX512_FsFLD0SS:
4778 case X86::AVX512_FsFLD0SD:
4779 case X86::AVX512_FsFLD0F128: {
4780 bool HasVLX = Subtarget.hasVLX();
4781 Register SrcReg = MIB.getReg(0);
4782 const TargetRegisterInfo *TRI = &getRegisterInfo();
4783 if (HasVLX || TRI->getEncodingValue(SrcReg) < 16)
4784 return Expand2AddrUndef(MIB,
4785 get(HasVLX ? X86::VPXORDZ128rr : X86::VXORPSrr));
4786 // Extended register without VLX. Use a larger XOR.
4787 SrcReg =
4788 TRI->getMatchingSuperReg(SrcReg, X86::sub_xmm, &X86::VR512RegClass);
4789 MIB->getOperand(0).setReg(SrcReg);
4790 return Expand2AddrUndef(MIB, get(X86::VPXORDZrr));
4791 }
4792 case X86::AVX512_256_SET0:
4793 case X86::AVX512_512_SET0: {
4794 bool HasVLX = Subtarget.hasVLX();
4795 Register SrcReg = MIB.getReg(0);
4796 const TargetRegisterInfo *TRI = &getRegisterInfo();
4797 if (HasVLX || TRI->getEncodingValue(SrcReg) < 16) {
4798 Register XReg = TRI->getSubReg(SrcReg, X86::sub_xmm);
4799 MIB->getOperand(0).setReg(XReg);
4800 Expand2AddrUndef(MIB,
4801 get(HasVLX ? X86::VPXORDZ128rr : X86::VXORPSrr));
4802 MIB.addReg(SrcReg, RegState::ImplicitDefine);
4803 return true;
4804 }
4805 if (MI.getOpcode() == X86::AVX512_256_SET0) {
4806 // No VLX so we must reference a zmm.
4807 unsigned ZReg =
4808 TRI->getMatchingSuperReg(SrcReg, X86::sub_ymm, &X86::VR512RegClass);
4809 MIB->getOperand(0).setReg(ZReg);
4810 }
4811 return Expand2AddrUndef(MIB, get(X86::VPXORDZrr));
4812 }
4813 case X86::V_SETALLONES:
4814 return Expand2AddrUndef(MIB, get(HasAVX ? X86::VPCMPEQDrr : X86::PCMPEQDrr));
4815 case X86::AVX2_SETALLONES:
4816 return Expand2AddrUndef(MIB, get(X86::VPCMPEQDYrr));
4817 case X86::AVX1_SETALLONES: {
4818 Register Reg = MIB.getReg(0);
4819 // VCMPPSYrri with an immediate 0xf should produce VCMPTRUEPS.
4820 MIB->setDesc(get(X86::VCMPPSYrri));
4821 MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef).addImm(0xf);
4822 return true;
4823 }
4824 case X86::AVX512_512_SETALLONES: {
4825 Register Reg = MIB.getReg(0);
4826 MIB->setDesc(get(X86::VPTERNLOGDZrri));
4827 // VPTERNLOGD needs 3 register inputs and an immediate.
4828 // 0xff will return 1s for any input.
4829 MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef)
4830 .addReg(Reg, RegState::Undef).addImm(0xff);
4831 return true;
4832 }
4833 case X86::AVX512_512_SEXT_MASK_32:
4834 case X86::AVX512_512_SEXT_MASK_64: {
4835 Register Reg = MIB.getReg(0);
4836 Register MaskReg = MIB.getReg(1);
4837 unsigned MaskState = getRegState(MIB->getOperand(1));
4838 unsigned Opc = (MI.getOpcode() == X86::AVX512_512_SEXT_MASK_64) ?
4839 X86::VPTERNLOGQZrrikz : X86::VPTERNLOGDZrrikz;
4840 MI.RemoveOperand(1);
4841 MIB->setDesc(get(Opc));
4842 // VPTERNLOG needs 3 register inputs and an immediate.
4843 // 0xff will return 1s for any input.
4844 MIB.addReg(Reg, RegState::Undef).addReg(MaskReg, MaskState)
4845 .addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef).addImm(0xff);
4846 return true;
4847 }
4848 case X86::VMOVAPSZ128rm_NOVLX:
4849 return expandNOVLXLoad(MIB, &getRegisterInfo(), get(X86::VMOVAPSrm),
4850 get(X86::VBROADCASTF32X4rm), X86::sub_xmm);
4851 case X86::VMOVUPSZ128rm_NOVLX:
4852 return expandNOVLXLoad(MIB, &getRegisterInfo(), get(X86::VMOVUPSrm),
4853 get(X86::VBROADCASTF32X4rm), X86::sub_xmm);
4854 case X86::VMOVAPSZ256rm_NOVLX:
4855 return expandNOVLXLoad(MIB, &getRegisterInfo(), get(X86::VMOVAPSYrm),
4856 get(X86::VBROADCASTF64X4rm), X86::sub_ymm);
4857 case X86::VMOVUPSZ256rm_NOVLX:
4858 return expandNOVLXLoad(MIB, &getRegisterInfo(), get(X86::VMOVUPSYrm),
4859 get(X86::VBROADCASTF64X4rm), X86::sub_ymm);
4860 case X86::VMOVAPSZ128mr_NOVLX:
4861 return expandNOVLXStore(MIB, &getRegisterInfo(), get(X86::VMOVAPSmr),
4862 get(X86::VEXTRACTF32x4Zmr), X86::sub_xmm);
4863 case X86::VMOVUPSZ128mr_NOVLX:
4864 return expandNOVLXStore(MIB, &getRegisterInfo(), get(X86::VMOVUPSmr),
4865 get(X86::VEXTRACTF32x4Zmr), X86::sub_xmm);
4866 case X86::VMOVAPSZ256mr_NOVLX:
4867 return expandNOVLXStore(MIB, &getRegisterInfo(), get(X86::VMOVAPSYmr),
4868 get(X86::VEXTRACTF64x4Zmr), X86::sub_ymm);
4869 case X86::VMOVUPSZ256mr_NOVLX:
4870 return expandNOVLXStore(MIB, &getRegisterInfo(), get(X86::VMOVUPSYmr),
4871 get(X86::VEXTRACTF64x4Zmr), X86::sub_ymm);
4872 case X86::MOV32ri64: {
4873 Register Reg = MIB.getReg(0);
4874 Register Reg32 = RI.getSubReg(Reg, X86::sub_32bit);
4875 MI.setDesc(get(X86::MOV32ri));
4876 MIB->getOperand(0).setReg(Reg32);
4877 MIB.addReg(Reg, RegState::ImplicitDefine);
4878 return true;
4879 }
4880
4881 // KNL does not recognize dependency-breaking idioms for mask registers,
4882 // so kxnor %k1, %k1, %k2 has a RAW dependence on %k1.
4883 // Using %k0 as the undef input register is a performance heuristic based
4884 // on the assumption that %k0 is used less frequently than the other mask
4885 // registers, since it is not usable as a write mask.
4886 // FIXME: A more advanced approach would be to choose the best input mask
4887 // register based on context.
4888 case X86::KSET0W: return Expand2AddrKreg(MIB, get(X86::KXORWrr), X86::K0);
4889 case X86::KSET0D: return Expand2AddrKreg(MIB, get(X86::KXORDrr), X86::K0);
4890 case X86::KSET0Q: return Expand2AddrKreg(MIB, get(X86::KXORQrr), X86::K0);
4891 case X86::KSET1W: return Expand2AddrKreg(MIB, get(X86::KXNORWrr), X86::K0);
4892 case X86::KSET1D: return Expand2AddrKreg(MIB, get(X86::KXNORDrr), X86::K0);
4893 case X86::KSET1Q: return Expand2AddrKreg(MIB, get(X86::KXNORQrr), X86::K0);
4894 case TargetOpcode::LOAD_STACK_GUARD:
4895 expandLoadStackGuard(MIB, *this);
4896 return true;
4897 case X86::XOR64_FP:
4898 case X86::XOR32_FP:
4899 return expandXorFP(MIB, *this);
4900 case X86::SHLDROT32ri: return expandSHXDROT(MIB, get(X86::SHLD32rri8));
4901 case X86::SHLDROT64ri: return expandSHXDROT(MIB, get(X86::SHLD64rri8));
4902 case X86::SHRDROT32ri: return expandSHXDROT(MIB, get(X86::SHRD32rri8));
4903 case X86::SHRDROT64ri: return expandSHXDROT(MIB, get(X86::SHRD64rri8));
4904 case X86::ADD8rr_DB: MIB->setDesc(get(X86::OR8rr)); break;
4905 case X86::ADD16rr_DB: MIB->setDesc(get(X86::OR16rr)); break;
4906 case X86::ADD32rr_DB: MIB->setDesc(get(X86::OR32rr)); break;
4907 case X86::ADD64rr_DB: MIB->setDesc(get(X86::OR64rr)); break;
4908 case X86::ADD8ri_DB: MIB->setDesc(get(X86::OR8ri)); break;
4909 case X86::ADD16ri_DB: MIB->setDesc(get(X86::OR16ri)); break;
4910 case X86::ADD32ri_DB: MIB->setDesc(get(X86::OR32ri)); break;
4911 case X86::ADD64ri32_DB: MIB->setDesc(get(X86::OR64ri32)); break;
4912 case X86::ADD16ri8_DB: MIB->setDesc(get(X86::OR16ri8)); break;
4913 case X86::ADD32ri8_DB: MIB->setDesc(get(X86::OR32ri8)); break;
4914 case X86::ADD64ri8_DB: MIB->setDesc(get(X86::OR64ri8)); break;
4915 }
4916 return false;
4917}
4918
4919/// Return true for all instructions that only update
4920/// the first 32 or 64-bits of the destination register and leave the rest
4921/// unmodified. This can be used to avoid folding loads if the instructions
4922/// only update part of the destination register, and the non-updated part is
4923/// not needed. e.g. cvtss2sd, sqrtss. Unfolding the load from these
4924/// instructions breaks the partial register dependency and it can improve
4925/// performance. e.g.:
4926///
4927/// movss (%rdi), %xmm0
4928/// cvtss2sd %xmm0, %xmm0
4929///
4930/// Instead of
4931/// cvtss2sd (%rdi), %xmm0
4932///
4933/// FIXME: This should be turned into a TSFlags.
4934///
4935static bool hasPartialRegUpdate(unsigned Opcode,
4936 const X86Subtarget &Subtarget,
4937 bool ForLoadFold = false) {
4938 switch (Opcode) {
4939 case X86::CVTSI2SSrr:
4940 case X86::CVTSI2SSrm:
4941 case X86::CVTSI642SSrr:
4942 case X86::CVTSI642SSrm:
4943 case X86::CVTSI2SDrr:
4944 case X86::CVTSI2SDrm:
4945 case X86::CVTSI642SDrr:
4946 case X86::CVTSI642SDrm:
4947 // Load folding won't effect the undef register update since the input is
4948 // a GPR.
4949 return !ForLoadFold;
4950 case X86::CVTSD2SSrr:
4951 case X86::CVTSD2SSrm:
4952 case X86::CVTSS2SDrr:
4953 case X86::CVTSS2SDrm:
4954 case X86::MOVHPDrm:
4955 case X86::MOVHPSrm:
4956 case X86::MOVLPDrm:
4957 case X86::MOVLPSrm:
4958 case X86::RCPSSr:
4959 case X86::RCPSSm:
4960 case X86::RCPSSr_Int:
4961 case X86::RCPSSm_Int:
4962 case X86::ROUNDSDr:
4963 case X86::ROUNDSDm:
4964 case X86::ROUNDSSr:
4965 case X86::ROUNDSSm:
4966 case X86::RSQRTSSr:
4967 case X86::RSQRTSSm:
4968 case X86::RSQRTSSr_Int:
4969 case X86::RSQRTSSm_Int:
4970 case X86::SQRTSSr:
4971 case X86::SQRTSSm:
4972 case X86::SQRTSSr_Int:
4973 case X86::SQRTSSm_Int:
4974 case X86::SQRTSDr:
4975 case X86::SQRTSDm:
4976 case X86::SQRTSDr_Int:
4977 case X86::SQRTSDm_Int:
4978 return true;
4979 // GPR
4980 case X86::POPCNT32rm:
4981 case X86::POPCNT32rr:
4982 case X86::POPCNT64rm:
4983 case X86::POPCNT64rr:
4984 return Subtarget.hasPOPCNTFalseDeps();
4985 case X86::LZCNT32rm:
4986 case X86::LZCNT32rr:
4987 case X86::LZCNT64rm:
4988 case X86::LZCNT64rr:
4989 case X86::TZCNT32rm:
4990 case X86::TZCNT32rr:
4991 case X86::TZCNT64rm:
4992 case X86::TZCNT64rr:
4993 return Subtarget.hasLZCNTFalseDeps();
4994 }
4995
4996 return false;
4997}
4998
4999/// Inform the BreakFalseDeps pass how many idle
5000/// instructions we would like before a partial register update.
5001unsigned X86InstrInfo::getPartialRegUpdateClearance(
5002 const MachineInstr &MI, unsigned OpNum,
5003 const TargetRegisterInfo *TRI) const {
5004 if (OpNum != 0 || !hasPartialRegUpdate(MI.getOpcode(), Subtarget))
5005 return 0;
5006
5007 // If MI is marked as reading Reg, the partial register update is wanted.
5008 const MachineOperand &MO = MI.getOperand(0);
5009 Register Reg = MO.getReg();
5010 if (Reg.isVirtual()) {
5011 if (MO.readsReg() || MI.readsVirtualRegister(Reg))
5012 return 0;
5013 } else {
5014 if (MI.readsRegister(Reg, TRI))
5015 return 0;
5016 }
5017
5018 // If any instructions in the clearance range are reading Reg, insert a
5019 // dependency breaking instruction, which is inexpensive and is likely to
5020 // be hidden in other instruction's cycles.
5021 return PartialRegUpdateClearance;
5022}
5023
5024// Return true for any instruction the copies the high bits of the first source
5025// operand into the unused high bits of the destination operand.
5026// Also returns true for instructions that have two inputs where one may
5027// be undef and we want it to use the same register as the other input.
5028static bool hasUndefRegUpdate(unsigned Opcode, unsigned OpNum,
5029 bool ForLoadFold = false) {
5030 // Set the OpNum parameter to the first source operand.
5031 switch (Opcode) {
5032 case X86::MMX_PUNPCKHBWirr:
5033 case X86::MMX_PUNPCKHWDirr:
5034 case X86::MMX_PUNPCKHDQirr:
5035 case X86::MMX_PUNPCKLBWirr:
5036 case X86::MMX_PUNPCKLWDirr:
5037 case X86::MMX_PUNPCKLDQirr:
5038 case X86::MOVHLPSrr:
5039 case X86::PACKSSWBrr:
5040 case X86::PACKUSWBrr:
5041 case X86::PACKSSDWrr:
5042 case X86::PACKUSDWrr:
5043 case X86::PUNPCKHBWrr:
5044 case X86::PUNPCKLBWrr:
5045 case X86::PUNPCKHWDrr:
5046 case X86::PUNPCKLWDrr:
5047 case X86::PUNPCKHDQrr:
5048 case X86::PUNPCKLDQrr:
5049 case X86::PUNPCKHQDQrr:
5050 case X86::PUNPCKLQDQrr:
5051 case X86::SHUFPDrri:
5052 case X86::SHUFPSrri:
5053 // These instructions are sometimes used with an undef first or second
5054 // source. Return true here so BreakFalseDeps will assign this source to the
5055 // same register as the first source to avoid a false dependency.
5056 // Operand 1 of these instructions is tied so they're separate from their
5057 // VEX counterparts.
5058 return OpNum == 2 && !ForLoadFold;
5059
5060 case X86::VMOVLHPSrr:
5061 case X86::VMOVLHPSZrr:
5062 case X86::VPACKSSWBrr:
5063 case X86::VPACKUSWBrr:
5064 case X86::VPACKSSDWrr:
5065 case X86::VPACKUSDWrr:
5066 case X86::VPACKSSWBZ128rr:
5067 case X86::VPACKUSWBZ128rr:
5068 case X86::VPACKSSDWZ128rr:
5069 case X86::VPACKUSDWZ128rr:
5070 case X86::VPERM2F128rr:
5071 case X86::VPERM2I128rr:
5072 case X86::VSHUFF32X4Z256rri:
5073 case X86::VSHUFF32X4Zrri:
5074 case X86::VSHUFF64X2Z256rri:
5075 case X86::VSHUFF64X2Zrri:
5076 case X86::VSHUFI32X4Z256rri:
5077 case X86::VSHUFI32X4Zrri:
5078 case X86::VSHUFI64X2Z256rri:
5079 case X86::VSHUFI64X2Zrri:
5080 case X86::VPUNPCKHBWrr:
5081 case X86::VPUNPCKLBWrr:
5082 case X86::VPUNPCKHBWYrr:
5083 case X86::VPUNPCKLBWYrr:
5084 case X86::VPUNPCKHBWZ128rr:
5085 case X86::VPUNPCKLBWZ128rr:
5086 case X86::VPUNPCKHBWZ256rr:
5087 case X86::VPUNPCKLBWZ256rr:
5088 case X86::VPUNPCKHBWZrr:
5089 case X86::VPUNPCKLBWZrr:
5090 case X86::VPUNPCKHWDrr:
5091 case X86::VPUNPCKLWDrr:
5092 case X86::VPUNPCKHWDYrr:
5093 case X86::VPUNPCKLWDYrr:
5094 case X86::VPUNPCKHWDZ128rr:
5095 case X86::VPUNPCKLWDZ128rr:
5096 case X86::VPUNPCKHWDZ256rr:
5097 case X86::VPUNPCKLWDZ256rr:
5098 case X86::VPUNPCKHWDZrr:
5099 case X86::VPUNPCKLWDZrr:
5100 case X86::VPUNPCKHDQrr:
5101 case X86::VPUNPCKLDQrr:
5102 case X86::VPUNPCKHDQYrr:
5103 case X86::VPUNPCKLDQYrr:
5104 case X86::VPUNPCKHDQZ128rr:
5105 case X86::VPUNPCKLDQZ128rr:
5106 case X86::VPUNPCKHDQZ256rr:
5107 case X86::VPUNPCKLDQZ256rr:
5108 case X86::VPUNPCKHDQZrr:
5109 case X86::VPUNPCKLDQZrr:
5110 case X86::VPUNPCKHQDQrr:
5111 case X86::VPUNPCKLQDQrr:
5112 case X86::VPUNPCKHQDQYrr:
5113 case X86::VPUNPCKLQDQYrr:
5114 case X86::VPUNPCKHQDQZ128rr:
5115 case X86::VPUNPCKLQDQZ128rr:
5116 case X86::VPUNPCKHQDQZ256rr:
5117 case X86::VPUNPCKLQDQZ256rr:
5118 case X86::VPUNPCKHQDQZrr:
5119 case X86::VPUNPCKLQDQZrr:
5120 // These instructions are sometimes used with an undef first or second
5121 // source. Return true here so BreakFalseDeps will assign this source to the
5122 // same register as the first source to avoid a false dependency.
5123 return (OpNum == 1 || OpNum == 2) && !ForLoadFold;
5124
5125 case X86::VCVTSI2SSrr:
5126 case X86::VCVTSI2SSrm:
5127 case X86::VCVTSI2SSrr_Int:
5128 case X86::VCVTSI2SSrm_Int:
5129 case X86::VCVTSI642SSrr:
5130 case X86::VCVTSI642SSrm:
5131 case X86::VCVTSI642SSrr_Int:
5132 case X86::VCVTSI642SSrm_Int:
5133 case X86::VCVTSI2SDrr:
5134 case X86::VCVTSI2SDrm:
5135 case X86::VCVTSI2SDrr_Int:
5136 case X86::VCVTSI2SDrm_Int:
5137 case X86::VCVTSI642SDrr:
5138 case X86::VCVTSI642SDrm:
5139 case X86::VCVTSI642SDrr_Int:
5140 case X86::VCVTSI642SDrm_Int:
5141 // AVX-512
5142 case X86::VCVTSI2SSZrr:
5143 case X86::VCVTSI2SSZrm:
5144 case X86::VCVTSI2SSZrr_Int:
5145 case X86::VCVTSI2SSZrrb_Int:
5146 case X86::VCVTSI2SSZrm_Int:
5147 case X86::VCVTSI642SSZrr:
5148 case X86::VCVTSI642SSZrm:
5149 case X86::VCVTSI642SSZrr_Int:
5150 case X86::VCVTSI642SSZrrb_Int:
5151 case X86::VCVTSI642SSZrm_Int:
5152 case X86::VCVTSI2SDZrr:
5153 case X86::VCVTSI2SDZrm:
5154 case X86::VCVTSI2SDZrr_Int:
5155 case X86::VCVTSI2SDZrm_Int:
5156 case X86::VCVTSI642SDZrr:
5157 case X86::VCVTSI642SDZrm:
5158 case X86::VCVTSI642SDZrr_Int:
5159 case X86::VCVTSI642SDZrrb_Int:
5160 case X86::VCVTSI642SDZrm_Int:
5161 case X86::VCVTUSI2SSZrr:
5162 case X86::VCVTUSI2SSZrm:
5163 case X86::VCVTUSI2SSZrr_Int:
5164 case X86::VCVTUSI2SSZrrb_Int:
5165 case X86::VCVTUSI2SSZrm_Int:
5166 case X86::VCVTUSI642SSZrr:
5167 case X86::VCVTUSI642SSZrm:
5168 case X86::VCVTUSI642SSZrr_Int:
5169 case X86::VCVTUSI642SSZrrb_Int:
5170 case X86::VCVTUSI642SSZrm_Int:
5171 case X86::VCVTUSI2SDZrr:
5172 case X86::VCVTUSI2SDZrm:
5173 case X86::VCVTUSI2SDZrr_Int:
5174 case X86::VCVTUSI2SDZrm_Int:
5175 case X86::VCVTUSI642SDZrr:
5176 case X86::VCVTUSI642SDZrm:
5177 case X86::VCVTUSI642SDZrr_Int:
5178 case X86::VCVTUSI642SDZrrb_Int:
5179 case X86::VCVTUSI642SDZrm_Int:
5180 case X86::VCVTSI2SHZrr:
5181 case X86::VCVTSI2SHZrm:
5182 case X86::VCVTSI2SHZrr_Int:
5183 case X86::VCVTSI2SHZrrb_Int:
5184 case X86::VCVTSI2SHZrm_Int:
5185 case X86::VCVTSI642SHZrr:
5186 case X86::VCVTSI642SHZrm:
5187 case X86::VCVTSI642SHZrr_Int:
5188 case X86::VCVTSI642SHZrrb_Int:
5189 case X86::VCVTSI642SHZrm_Int:
5190 case X86::VCVTUSI2SHZrr:
5191 case X86::VCVTUSI2SHZrm:
5192 case X86::VCVTUSI2SHZrr_Int:
5193 case X86::VCVTUSI2SHZrrb_Int:
5194 case X86::VCVTUSI2SHZrm_Int:
5195 case X86::VCVTUSI642SHZrr:
5196 case X86::VCVTUSI642SHZrm:
5197 case X86::VCVTUSI642SHZrr_Int:
5198 case X86::VCVTUSI642SHZrrb_Int:
5199 case X86::VCVTUSI642SHZrm_Int:
5200 // Load folding won't effect the undef register update since the input is
5201 // a GPR.
5202 return OpNum == 1 && !ForLoadFold;
5203 case X86::VCVTSD2SSrr:
5204 case X86::VCVTSD2SSrm:
5205 case X86::VCVTSD2SSrr_Int:
5206 case X86::VCVTSD2SSrm_Int:
5207 case X86::VCVTSS2SDrr:
5208 case X86::VCVTSS2SDrm:
5209 case X86::VCVTSS2SDrr_Int:
5210 case X86::VCVTSS2SDrm_Int:
5211 case X86::VRCPSSr:
5212 case X86::VRCPSSr_Int:
5213 case X86::VRCPSSm:
5214 case X86::VRCPSSm_Int:
5215 case X86::VROUNDSDr:
5216 case X86::VROUNDSDm:
5217 case X86::VROUNDSDr_Int:
5218 case X86::VROUNDSDm_Int:
5219 case X86::VROUNDSSr:
5220 case X86::VROUNDSSm:
5221 case X86::VROUNDSSr_Int:
5222 case X86::VROUNDSSm_Int:
5223 case X86::VRSQRTSSr:
5224 case X86::VRSQRTSSr_Int:
5225 case X86::VRSQRTSSm:
5226 case X86::VRSQRTSSm_Int:
5227 case X86::VSQRTSSr:
5228 case X86::VSQRTSSr_Int:
5229 case X86::VSQRTSSm:
5230 case X86::VSQRTSSm_Int:
5231 case X86::VSQRTSDr:
5232 case X86::VSQRTSDr_Int:
5233 case X86::VSQRTSDm:
5234 case X86::VSQRTSDm_Int:
5235 // AVX-512
5236 case X86::VCVTSD2SSZrr:
5237 case X86::VCVTSD2SSZrr_Int:
5238 case X86::VCVTSD2SSZrrb_Int:
5239 case X86::VCVTSD2SSZrm:
5240 case X86::VCVTSD2SSZrm_Int:
5241 case X86::VCVTSS2SDZrr:
5242 case X86::VCVTSS2SDZrr_Int:
5243 case X86::VCVTSS2SDZrrb_Int:
5244 case X86::VCVTSS2SDZrm:
5245 case X86::VCVTSS2SDZrm_Int:
5246 case X86::VGETEXPSDZr:
5247 case X86::VGETEXPSDZrb:
5248 case X86::VGETEXPSDZm:
5249 case X86::VGETEXPSSZr:
5250 case X86::VGETEXPSSZrb:
5251 case X86::VGETEXPSSZm:
5252 case X86::VGETMANTSDZrri:
5253 case X86::VGETMANTSDZrrib:
5254 case X86::VGETMANTSDZrmi:
5255 case X86::VGETMANTSSZrri:
5256 case X86::VGETMANTSSZrrib:
5257 case X86::VGETMANTSSZrmi:
5258 case X86::VRNDSCALESDZr:
5259 case X86::VRNDSCALESDZr_Int:
5260 case X86::VRNDSCALESDZrb_Int:
5261 case X86::VRNDSCALESDZm:
5262 case X86::VRNDSCALESDZm_Int:
5263 case X86::VRNDSCALESSZr:
5264 case X86::VRNDSCALESSZr_Int:
5265 case X86::VRNDSCALESSZrb_Int:
5266 case X86::VRNDSCALESSZm:
5267 case X86::VRNDSCALESSZm_Int:
5268 case X86::VRCP14SDZrr:
5269 case X86::VRCP14SDZrm:
5270 case X86::VRCP14SSZrr:
5271 case X86::VRCP14SSZrm:
5272 case X86::VRCPSHZrr:
5273 case X86::VRCPSHZrm:
5274 case X86::VRSQRTSHZrr:
5275 case X86::VRSQRTSHZrm:
5276 case X86::VREDUCESHZrmi:
5277 case X86::VREDUCESHZrri:
5278 case X86::VREDUCESHZrrib:
5279 case X86::VGETEXPSHZr:
5280 case X86::VGETEXPSHZrb:
5281 case X86::VGETEXPSHZm:
5282 case X86::VGETMANTSHZrri:
5283 case X86::VGETMANTSHZrrib:
5284 case X86::VGETMANTSHZrmi:
5285 case X86::VRNDSCALESHZr:
5286 case X86::VRNDSCALESHZr_Int:
5287 case X86::VRNDSCALESHZrb_Int:
5288 case X86::VRNDSCALESHZm:
5289 case X86::VRNDSCALESHZm_Int:
5290 case X86::VSQRTSHZr:
5291 case X86::VSQRTSHZr_Int:
5292 case X86::VSQRTSHZrb_Int:
5293 case X86::VSQRTSHZm:
5294 case X86::VSQRTSHZm_Int:
5295 case X86::VRCP28SDZr:
5296 case X86::VRCP28SDZrb:
5297 case X86::VRCP28SDZm:
5298 case X86::VRCP28SSZr:
5299 case X86::VRCP28SSZrb:
5300 case X86::VRCP28SSZm:
5301 case X86::VREDUCESSZrmi:
5302 case X86::VREDUCESSZrri:
5303 case X86::VREDUCESSZrrib:
5304 case X86::VRSQRT14SDZrr:
5305 case X86::VRSQRT14SDZrm:
5306 case X86::VRSQRT14SSZrr:
5307 case X86::VRSQRT14SSZrm:
5308 case X86::VRSQRT28SDZr:
5309 case X86::VRSQRT28SDZrb:
5310 case X86::VRSQRT28SDZm:
5311 case X86::VRSQRT28SSZr:
5312 case X86::VRSQRT28SSZrb:
5313 case X86::VRSQRT28SSZm:
5314 case X86::VSQRTSSZr:
5315 case X86::VSQRTSSZr_Int:
5316 case X86::VSQRTSSZrb_Int:
5317 case X86::VSQRTSSZm:
5318 case X86::VSQRTSSZm_Int:
5319 case X86::VSQRTSDZr:
5320 case X86::VSQRTSDZr_Int:
5321 case X86::VSQRTSDZrb_Int:
5322 case X86::VSQRTSDZm:
5323 case X86::VSQRTSDZm_Int:
5324 case X86::VCVTSD2SHZrr:
5325 case X86::VCVTSD2SHZrr_Int:
5326 case X86::VCVTSD2SHZrrb_Int:
5327 case X86::VCVTSD2SHZrm:
5328 case X86::VCVTSD2SHZrm_Int:
5329 case X86::VCVTSS2SHZrr:
5330 case X86::VCVTSS2SHZrr_Int:
5331 case X86::VCVTSS2SHZrrb_Int:
5332 case X86::VCVTSS2SHZrm:
5333 case X86::VCVTSS2SHZrm_Int:
5334 case X86::VCVTSH2SDZrr:
5335 case X86::VCVTSH2SDZrr_Int:
5336 case X86::VCVTSH2SDZrrb_Int:
5337 case X86::VCVTSH2SDZrm:
5338 case X86::VCVTSH2SDZrm_Int:
5339 case X86::VCVTSH2SSZrr:
5340 case X86::VCVTSH2SSZrr_Int:
5341 case X86::VCVTSH2SSZrrb_Int:
5342 case X86::VCVTSH2SSZrm:
5343 case X86::VCVTSH2SSZrm_Int:
5344 return OpNum == 1;
5345 case X86::VMOVSSZrrk:
5346 case X86::VMOVSDZrrk:
5347 return OpNum == 3 && !ForLoadFold;
5348 case X86::VMOVSSZrrkz:
5349 case X86::VMOVSDZrrkz:
5350 return OpNum == 2 && !ForLoadFold;
5351 }
5352
5353 return false;
5354}
5355
5356/// Inform the BreakFalseDeps pass how many idle instructions we would like
5357/// before certain undef register reads.
5358///
5359/// This catches the VCVTSI2SD family of instructions:
5360///
5361/// vcvtsi2sdq %rax, undef %xmm0, %xmm14
5362///
5363/// We should to be careful *not* to catch VXOR idioms which are presumably
5364/// handled specially in the pipeline:
5365///
5366/// vxorps undef %xmm1, undef %xmm1, %xmm1
5367///
5368/// Like getPartialRegUpdateClearance, this makes a strong assumption that the
5369/// high bits that are passed-through are not live.
5370unsigned
5371X86InstrInfo::getUndefRegClearance(const MachineInstr &MI, unsigned OpNum,
5372 const TargetRegisterInfo *TRI) const {
5373 const MachineOperand &MO = MI.getOperand(OpNum);
5374 if (Register::isPhysicalRegister(MO.getReg()) &&
5375 hasUndefRegUpdate(MI.getOpcode(), OpNum))
5376 return UndefRegClearance;
5377
5378 return 0;
5379}
5380
5381void X86InstrInfo::breakPartialRegDependency(
5382 MachineInstr &MI, unsigned OpNum, const TargetRegisterInfo *TRI) const {
5383 Register Reg = MI.getOperand(OpNum).getReg();
5384 // If MI kills this register, the false dependence is already broken.
5385 if (MI.killsRegister(Reg, TRI))
5386 return;
5387
5388 if (X86::VR128RegClass.contains(Reg)) {
5389 // These instructions are all floating point domain, so xorps is the best
5390 // choice.
5391 unsigned Opc = Subtarget.hasAVX() ? X86::VXORPSrr : X86::XORPSrr;
5392 BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(Opc), Reg)
5393 .addReg(Reg, RegState::Undef)
5394 .addReg(Reg, RegState::Undef);
5395 MI.addRegisterKilled(Reg, TRI, true);
5396 } else if (X86::VR256RegClass.contains(Reg)) {
5397 // Use vxorps to clear the full ymm register.
5398 // It wants to read and write the xmm sub-register.
5399 Register XReg = TRI->getSubReg(Reg, X86::sub_xmm);
5400 BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(X86::VXORPSrr), XReg)
5401 .addReg(XReg, RegState::Undef)
5402 .addReg(XReg, RegState::Undef)
5403 .addReg(Reg, RegState::ImplicitDefine);
5404 MI.addRegisterKilled(Reg, TRI, true);
5405 } else if (X86::GR64RegClass.contains(Reg)) {
5406 // Using XOR32rr because it has shorter encoding and zeros up the upper bits
5407 // as well.
5408 Register XReg = TRI->getSubReg(Reg, X86::sub_32bit);
5409 BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(X86::XOR32rr), XReg)
5410 .addReg(XReg, RegState::Undef)
5411 .addReg(XReg, RegState::Undef)
5412 .addReg(Reg, RegState::ImplicitDefine);
5413 MI.addRegisterKilled(Reg, TRI, true);
5414 } else if (X86::GR32RegClass.contains(Reg)) {
5415 BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(X86::XOR32rr), Reg)
5416 .addReg(Reg, RegState::Undef)
5417 .addReg(Reg, RegState::Undef);
5418 MI.addRegisterKilled(Reg, TRI, true);
5419 }
5420}
5421
5422static void addOperands(MachineInstrBuilder &MIB, ArrayRef<MachineOperand> MOs,
5423 int PtrOffset = 0) {
5424 unsigned NumAddrOps = MOs.size();
5425
5426 if (NumAddrOps < 4) {
5427 // FrameIndex only - add an immediate offset (whether its zero or not).
5428 for (unsigned i = 0; i != NumAddrOps; ++i)
5429 MIB.add(MOs[i]);
5430 addOffset(MIB, PtrOffset);
5431 } else {
5432 // General Memory Addressing - we need to add any offset to an existing
5433 // offset.
5434 assert(MOs.size() == 5 && "Unexpected memory operand list length")(static_cast <bool> (MOs.size() == 5 && "Unexpected memory operand list length"
) ? void (0) : __assert_fail ("MOs.size() == 5 && \"Unexpected memory operand list length\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 5434, __extension__ __PRETTY_FUNCTION__))
;
5435 for (unsigned i = 0; i != NumAddrOps; ++i) {
5436 const MachineOperand &MO = MOs[i];
5437 if (i == 3 && PtrOffset != 0) {
5438 MIB.addDisp(MO, PtrOffset);
5439 } else {
5440 MIB.add(MO);
5441 }
5442 }
5443 }
5444}
5445
5446static void updateOperandRegConstraints(MachineFunction &MF,
5447 MachineInstr &NewMI,
5448 const TargetInstrInfo &TII) {
5449 MachineRegisterInfo &MRI = MF.getRegInfo();
5450 const TargetRegisterInfo &TRI = *MRI.getTargetRegisterInfo();
5451
5452 for (int Idx : llvm::seq<int>(0, NewMI.getNumOperands())) {
5453 MachineOperand &MO = NewMI.getOperand(Idx);
5454 // We only need to update constraints on virtual register operands.
5455 if (!MO.isReg())
5456 continue;
5457 Register Reg = MO.getReg();
5458 if (!Reg.isVirtual())
5459 continue;
5460
5461 auto *NewRC = MRI.constrainRegClass(
5462 Reg, TII.getRegClass(NewMI.getDesc(), Idx, &TRI, MF));
5463 if (!NewRC) {
5464 LLVM_DEBUG(do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("x86-instr-info")) { dbgs() << "WARNING: Unable to update register constraint for operand "
<< Idx << " of instruction:\n"; NewMI.dump(); dbgs
() << "\n"; } } while (false)
5465 dbgs() << "WARNING: Unable to update register constraint for operand "do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("x86-instr-info")) { dbgs() << "WARNING: Unable to update register constraint for operand "
<< Idx << " of instruction:\n"; NewMI.dump(); dbgs
() << "\n"; } } while (false)
5466 << Idx << " of instruction:\n";do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("x86-instr-info")) { dbgs() << "WARNING: Unable to update register constraint for operand "
<< Idx << " of instruction:\n"; NewMI.dump(); dbgs
() << "\n"; } } while (false)
5467 NewMI.dump(); dbgs() << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("x86-instr-info")) { dbgs() << "WARNING: Unable to update register constraint for operand "
<< Idx << " of instruction:\n"; NewMI.dump(); dbgs
() << "\n"; } } while (false)
;
5468 }
5469 }
5470}
5471
5472static MachineInstr *FuseTwoAddrInst(MachineFunction &MF, unsigned Opcode,
5473 ArrayRef<MachineOperand> MOs,
5474 MachineBasicBlock::iterator InsertPt,
5475 MachineInstr &MI,
5476 const TargetInstrInfo &TII) {
5477 // Create the base instruction with the memory operand as the first part.
5478 // Omit the implicit operands, something BuildMI can't do.
5479 MachineInstr *NewMI =
5480 MF.CreateMachineInstr(TII.get(Opcode), MI.getDebugLoc(), true);
5481 MachineInstrBuilder MIB(MF, NewMI);
5482 addOperands(MIB, MOs);
5483
5484 // Loop over the rest of the ri operands, converting them over.
5485 unsigned NumOps = MI.getDesc().getNumOperands() - 2;
5486 for (unsigned i = 0; i != NumOps; ++i) {
5487 MachineOperand &MO = MI.getOperand(i + 2);
5488 MIB.add(MO);
5489 }
5490 for (unsigned i = NumOps + 2, e = MI.getNumOperands(); i != e; ++i) {
5491 MachineOperand &MO = MI.getOperand(i);
5492 MIB.add(MO);
5493 }
5494
5495 updateOperandRegConstraints(MF, *NewMI, TII);
5496
5497 MachineBasicBlock *MBB = InsertPt->getParent();
5498 MBB->insert(InsertPt, NewMI);
5499
5500 return MIB;
5501}
5502
5503static MachineInstr *FuseInst(MachineFunction &MF, unsigned Opcode,
5504 unsigned OpNo, ArrayRef<MachineOperand> MOs,
5505 MachineBasicBlock::iterator InsertPt,
5506 MachineInstr &MI, const TargetInstrInfo &TII,
5507 int PtrOffset = 0) {
5508 // Omit the implicit operands, something BuildMI can't do.
5509 MachineInstr *NewMI =
5510 MF.CreateMachineInstr(TII.get(Opcode), MI.getDebugLoc(), true);
5511 MachineInstrBuilder MIB(MF, NewMI);
5512
5513 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
5514 MachineOperand &MO = MI.getOperand(i);
5515 if (i == OpNo) {
5516 assert(MO.isReg() && "Expected to fold into reg operand!")(static_cast <bool> (MO.isReg() && "Expected to fold into reg operand!"
) ? void (0) : __assert_fail ("MO.isReg() && \"Expected to fold into reg operand!\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 5516, __extension__ __PRETTY_FUNCTION__))
;
5517 addOperands(MIB, MOs, PtrOffset);
5518 } else {
5519 MIB.add(MO);
5520 }
5521 }
5522
5523 updateOperandRegConstraints(MF, *NewMI, TII);
5524
5525 // Copy the NoFPExcept flag from the instruction we're fusing.
5526 if (MI.getFlag(MachineInstr::MIFlag::NoFPExcept))
5527 NewMI->setFlag(MachineInstr::MIFlag::NoFPExcept);
5528
5529 MachineBasicBlock *MBB = InsertPt->getParent();
5530 MBB->insert(InsertPt, NewMI);
5531
5532 return MIB;
5533}
5534
5535static MachineInstr *MakeM0Inst(const TargetInstrInfo &TII, unsigned Opcode,
5536 ArrayRef<MachineOperand> MOs,
5537 MachineBasicBlock::iterator InsertPt,
5538 MachineInstr &MI) {
5539 MachineInstrBuilder MIB = BuildMI(*InsertPt->getParent(), InsertPt,
5540 MI.getDebugLoc(), TII.get(Opcode));
5541 addOperands(MIB, MOs);
5542 return MIB.addImm(0);
5543}
5544
5545MachineInstr *X86InstrInfo::foldMemoryOperandCustom(
5546 MachineFunction &MF, MachineInstr &MI, unsigned OpNum,
5547 ArrayRef<MachineOperand> MOs, MachineBasicBlock::iterator InsertPt,
5548 unsigned Size, Align Alignment) const {
5549 switch (MI.getOpcode()) {
5550 case X86::INSERTPSrr:
5551 case X86::VINSERTPSrr:
5552 case X86::VINSERTPSZrr:
5553 // Attempt to convert the load of inserted vector into a fold load
5554 // of a single float.
5555 if (OpNum == 2) {
5556 unsigned Imm = MI.getOperand(MI.getNumOperands() - 1).getImm();
5557 unsigned ZMask = Imm & 15;
5558 unsigned DstIdx = (Imm >> 4) & 3;
5559 unsigned SrcIdx = (Imm >> 6) & 3;
5560
5561 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
5562 const TargetRegisterClass *RC = getRegClass(MI.getDesc(), OpNum, &RI, MF);
5563 unsigned RCSize = TRI.getRegSizeInBits(*RC) / 8;
5564 if ((Size == 0 || Size >= 16) && RCSize >= 16 && Alignment >= Align(4)) {
5565 int PtrOffset = SrcIdx * 4;
5566 unsigned NewImm = (DstIdx << 4) | ZMask;
5567 unsigned NewOpCode =
5568 (MI.getOpcode() == X86::VINSERTPSZrr) ? X86::VINSERTPSZrm :
5569 (MI.getOpcode() == X86::VINSERTPSrr) ? X86::VINSERTPSrm :
5570 X86::INSERTPSrm;
5571 MachineInstr *NewMI =
5572 FuseInst(MF, NewOpCode, OpNum, MOs, InsertPt, MI, *this, PtrOffset);
5573 NewMI->getOperand(NewMI->getNumOperands() - 1).setImm(NewImm);
5574 return NewMI;
5575 }
5576 }
5577 break;
5578 case X86::MOVHLPSrr:
5579 case X86::VMOVHLPSrr:
5580 case X86::VMOVHLPSZrr:
5581 // Move the upper 64-bits of the second operand to the lower 64-bits.
5582 // To fold the load, adjust the pointer to the upper and use (V)MOVLPS.
5583 // TODO: In most cases AVX doesn't have a 8-byte alignment requirement.
5584 if (OpNum == 2) {
5585 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
5586 const TargetRegisterClass *RC = getRegClass(MI.getDesc(), OpNum, &RI, MF);
5587 unsigned RCSize = TRI.getRegSizeInBits(*RC) / 8;
5588 if ((Size == 0 || Size >= 16) && RCSize >= 16 && Alignment >= Align(8)) {
5589 unsigned NewOpCode =
5590 (MI.getOpcode() == X86::VMOVHLPSZrr) ? X86::VMOVLPSZ128rm :
5591 (MI.getOpcode() == X86::VMOVHLPSrr) ? X86::VMOVLPSrm :
5592 X86::MOVLPSrm;
5593 MachineInstr *NewMI =
5594 FuseInst(MF, NewOpCode, OpNum, MOs, InsertPt, MI, *this, 8);
5595 return NewMI;
5596 }
5597 }
5598 break;
5599 case X86::UNPCKLPDrr:
5600 // If we won't be able to fold this to the memory form of UNPCKL, use
5601 // MOVHPD instead. Done as custom because we can't have this in the load
5602 // table twice.
5603 if (OpNum == 2) {
5604 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
5605 const TargetRegisterClass *RC = getRegClass(MI.getDesc(), OpNum, &RI, MF);
5606 unsigned RCSize = TRI.getRegSizeInBits(*RC) / 8;
5607 if ((Size == 0 || Size >= 16) && RCSize >= 16 && Alignment < Align(16)) {
5608 MachineInstr *NewMI =
5609 FuseInst(MF, X86::MOVHPDrm, OpNum, MOs, InsertPt, MI, *this);
5610 return NewMI;
5611 }
5612 }
5613 break;
5614 }
5615
5616 return nullptr;
5617}
5618
5619static bool shouldPreventUndefRegUpdateMemFold(MachineFunction &MF,
5620 MachineInstr &MI) {
5621 if (!hasUndefRegUpdate(MI.getOpcode(), 1, /*ForLoadFold*/true) ||
5622 !MI.getOperand(1).isReg())
5623 return false;
5624
5625 // The are two cases we need to handle depending on where in the pipeline
5626 // the folding attempt is being made.
5627 // -Register has the undef flag set.
5628 // -Register is produced by the IMPLICIT_DEF instruction.
5629
5630 if (MI.getOperand(1).isUndef())
5631 return true;
5632
5633 MachineRegisterInfo &RegInfo = MF.getRegInfo();
5634 MachineInstr *VRegDef = RegInfo.getUniqueVRegDef(MI.getOperand(1).getReg());
5635 return VRegDef && VRegDef->isImplicitDef();
5636}
5637
5638MachineInstr *X86InstrInfo::foldMemoryOperandImpl(
5639 MachineFunction &MF, MachineInstr &MI, unsigned OpNum,
5640 ArrayRef<MachineOperand> MOs, MachineBasicBlock::iterator InsertPt,
5641 unsigned Size, Align Alignment, bool AllowCommute) const {
5642 bool isSlowTwoMemOps = Subtarget.slowTwoMemOps();
5643 bool isTwoAddrFold = false;
5644
5645 // For CPUs that favor the register form of a call or push,
5646 // do not fold loads into calls or pushes, unless optimizing for size
5647 // aggressively.
5648 if (isSlowTwoMemOps && !MF.getFunction().hasMinSize() &&
5649 (MI.getOpcode() == X86::CALL32r || MI.getOpcode() == X86::CALL64r ||
5650 MI.getOpcode() == X86::PUSH16r || MI.getOpcode() == X86::PUSH32r ||
5651 MI.getOpcode() == X86::PUSH64r))
5652 return nullptr;
5653
5654 // Avoid partial and undef register update stalls unless optimizing for size.
5655 if (!MF.getFunction().hasOptSize() &&
5656 (hasPartialRegUpdate(MI.getOpcode(), Subtarget, /*ForLoadFold*/true) ||
5657 shouldPreventUndefRegUpdateMemFold(MF, MI)))
5658 return nullptr;
5659
5660 unsigned NumOps = MI.getDesc().getNumOperands();
5661 bool isTwoAddr =
5662 NumOps > 1 && MI.getDesc().getOperandConstraint(1, MCOI::TIED_TO) != -1;
5663
5664 // FIXME: AsmPrinter doesn't know how to handle
5665 // X86II::MO_GOT_ABSOLUTE_ADDRESS after folding.
5666 if (MI.getOpcode() == X86::ADD32ri &&
5667 MI.getOperand(2).getTargetFlags() == X86II::MO_GOT_ABSOLUTE_ADDRESS)
5668 return nullptr;
5669
5670 // GOTTPOFF relocation loads can only be folded into add instructions.
5671 // FIXME: Need to exclude other relocations that only support specific
5672 // instructions.
5673 if (MOs.size() == X86::AddrNumOperands &&
5674 MOs[X86::AddrDisp].getTargetFlags() == X86II::MO_GOTTPOFF &&
5675 MI.getOpcode() != X86::ADD64rr)
5676 return nullptr;
5677
5678 MachineInstr *NewMI = nullptr;
5679
5680 // Attempt to fold any custom cases we have.
5681 if (MachineInstr *CustomMI = foldMemoryOperandCustom(
5682 MF, MI, OpNum, MOs, InsertPt, Size, Alignment))
5683 return CustomMI;
5684
5685 const X86MemoryFoldTableEntry *I = nullptr;
5686
5687 // Folding a memory location into the two-address part of a two-address
5688 // instruction is different than folding it other places. It requires
5689 // replacing the *two* registers with the memory location.
5690 if (isTwoAddr && NumOps >= 2 && OpNum < 2 && MI.getOperand(0).isReg() &&
5691 MI.getOperand(1).isReg() &&
5692 MI.getOperand(0).getReg() == MI.getOperand(1).getReg()) {
5693 I = lookupTwoAddrFoldTable(MI.getOpcode());
5694 isTwoAddrFold = true;
5695 } else {
5696 if (OpNum == 0) {
5697 if (MI.getOpcode() == X86::MOV32r0) {
5698 NewMI = MakeM0Inst(*this, X86::MOV32mi, MOs, InsertPt, MI);
5699 if (NewMI)
5700 return NewMI;
5701 }
5702 }
5703
5704 I = lookupFoldTable(MI.getOpcode(), OpNum);
5705 }
5706
5707 if (I != nullptr) {
5708 unsigned Opcode = I->DstOp;
5709 bool FoldedLoad =
5710 isTwoAddrFold || (OpNum == 0 && I->Flags & TB_FOLDED_LOAD) || OpNum > 0;
5711 bool FoldedStore =
5712 isTwoAddrFold || (OpNum == 0 && I->Flags & TB_FOLDED_STORE);
5713 MaybeAlign MinAlign =
5714 decodeMaybeAlign((I->Flags & TB_ALIGN_MASK) >> TB_ALIGN_SHIFT);
5715 if (MinAlign && Alignment < *MinAlign)
5716 return nullptr;
5717 bool NarrowToMOV32rm = false;
5718 if (Size) {
5719 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
5720 const TargetRegisterClass *RC = getRegClass(MI.getDesc(), OpNum,
5721 &RI, MF);
5722 unsigned RCSize = TRI.getRegSizeInBits(*RC) / 8;
5723 // Check if it's safe to fold the load. If the size of the object is
5724 // narrower than the load width, then it's not.
5725 // FIXME: Allow scalar intrinsic instructions like ADDSSrm_Int.
5726 if (FoldedLoad && Size < RCSize) {
5727 // If this is a 64-bit load, but the spill slot is 32, then we can do
5728 // a 32-bit load which is implicitly zero-extended. This likely is
5729 // due to live interval analysis remat'ing a load from stack slot.
5730 if (Opcode != X86::MOV64rm || RCSize != 8 || Size != 4)
5731 return nullptr;
5732 if (MI.getOperand(0).getSubReg() || MI.getOperand(1).getSubReg())
5733 return nullptr;
5734 Opcode = X86::MOV32rm;
5735 NarrowToMOV32rm = true;
5736 }
5737 // For stores, make sure the size of the object is equal to the size of
5738 // the store. If the object is larger, the extra bits would be garbage. If
5739 // the object is smaller we might overwrite another object or fault.
5740 if (FoldedStore && Size != RCSize)
5741 return nullptr;
5742 }
5743
5744 if (isTwoAddrFold)
5745 NewMI = FuseTwoAddrInst(MF, Opcode, MOs, InsertPt, MI, *this);
5746 else
5747 NewMI = FuseInst(MF, Opcode, OpNum, MOs, InsertPt, MI, *this);
5748
5749 if (NarrowToMOV32rm) {
5750 // If this is the special case where we use a MOV32rm to load a 32-bit
5751 // value and zero-extend the top bits. Change the destination register
5752 // to a 32-bit one.
5753 Register DstReg = NewMI->getOperand(0).getReg();
5754 if (DstReg.isPhysical())
5755 NewMI->getOperand(0).setReg(RI.getSubReg(DstReg, X86::sub_32bit));
5756 else
5757 NewMI->getOperand(0).setSubReg(X86::sub_32bit);
5758 }
5759 return NewMI;
5760 }
5761
5762 // If the instruction and target operand are commutable, commute the
5763 // instruction and try again.
5764 if (AllowCommute) {
5765 unsigned CommuteOpIdx1 = OpNum, CommuteOpIdx2 = CommuteAnyOperandIndex;
5766 if (findCommutedOpIndices(MI, CommuteOpIdx1, CommuteOpIdx2)) {
5767 bool HasDef = MI.getDesc().getNumDefs();
5768 Register Reg0 = HasDef ? MI.getOperand(0).getReg() : Register();
5769 Register Reg1 = MI.getOperand(CommuteOpIdx1).getReg();
5770 Register Reg2 = MI.getOperand(CommuteOpIdx2).getReg();
5771 bool Tied1 =
5772 0 == MI.getDesc().getOperandConstraint(CommuteOpIdx1, MCOI::TIED_TO);
5773 bool Tied2 =
5774 0 == MI.getDesc().getOperandConstraint(CommuteOpIdx2, MCOI::TIED_TO);
5775
5776 // If either of the commutable operands are tied to the destination
5777 // then we can not commute + fold.
5778 if ((HasDef && Reg0 == Reg1 && Tied1) ||
5779 (HasDef && Reg0 == Reg2 && Tied2))
5780 return nullptr;
5781
5782 MachineInstr *CommutedMI =
5783 commuteInstruction(MI, false, CommuteOpIdx1, CommuteOpIdx2);
5784 if (!CommutedMI) {
5785 // Unable to commute.
5786 return nullptr;
5787 }
5788 if (CommutedMI != &MI) {
5789 // New instruction. We can't fold from this.
5790 CommutedMI->eraseFromParent();
5791 return nullptr;
5792 }
5793
5794 // Attempt to fold with the commuted version of the instruction.
5795 NewMI = foldMemoryOperandImpl(MF, MI, CommuteOpIdx2, MOs, I