Bug Summary

File:llvm/lib/Target/X86/X86InstrInfo.cpp
Warning:line 3918, column 19
Value stored to 'NewMI' during its initialization is never read

Annotated Source Code

Press '?' to see keyboard shortcuts

clang -cc1 -cc1 -triple x86_64-pc-linux-gnu -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name X86InstrInfo.cpp -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=cplusplus -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -analyzer-config-compatibility-mode=true -mrelocation-model pic -pic-level 2 -mframe-pointer=none -fmath-errno -fno-rounding-math -mconstructor-aliases -munwind-tables -target-cpu x86-64 -tune-cpu generic -debugger-tuning=gdb -ffunction-sections -fdata-sections -fcoverage-compilation-dir=/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/build-llvm -resource-dir /usr/lib/llvm-14/lib/clang/14.0.0 -D _DEBUG -D _GNU_SOURCE -D __STDC_CONSTANT_MACROS -D __STDC_FORMAT_MACROS -D __STDC_LIMIT_MACROS -I lib/Target/X86 -I /build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/X86 -I include -I /build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/include -D NDEBUG -U NDEBUG -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/10/../../../../include/c++/10 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/10/../../../../include/x86_64-linux-gnu/c++/10 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/10/../../../../include/c++/10/backward -internal-isystem /usr/lib/llvm-14/lib/clang/14.0.0/include -internal-isystem /usr/local/include -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/10/../../../../x86_64-linux-gnu/include -internal-externc-isystem /usr/include/x86_64-linux-gnu -internal-externc-isystem /include -internal-externc-isystem /usr/include -O2 -Wno-unused-command-line-argument -Wno-unknown-warning-option -Wno-unused-parameter -Wwrite-strings -Wno-missing-field-initializers -Wno-long-long -Wno-maybe-uninitialized -Wno-class-memaccess -Wno-redundant-move -Wno-pessimizing-move -Wno-noexcept-type -Wno-comment -std=c++14 -fdeprecated-macro -fdebug-compilation-dir=/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/build-llvm -ferror-limit 19 -fvisibility hidden -fvisibility-inlines-hidden -fgnuc-version=4.2.1 -fcolor-diagnostics -vectorize-loops -vectorize-slp -analyzer-output=html -analyzer-config stable-report-filename=true -faddrsig -D__GCC_HAVE_DWARF2_CFI_ASM=1 -o /tmp/scan-build-2021-09-26-234817-15343-1 -x c++ /build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/X86/X86InstrInfo.cpp
1//===-- X86InstrInfo.cpp - X86 Instruction Information --------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the X86 implementation of the TargetInstrInfo class.
10//
11//===----------------------------------------------------------------------===//
12
13#include "X86InstrInfo.h"
14#include "X86.h"
15#include "X86InstrBuilder.h"
16#include "X86InstrFoldTables.h"
17#include "X86MachineFunctionInfo.h"
18#include "X86Subtarget.h"
19#include "X86TargetMachine.h"
20#include "llvm/ADT/STLExtras.h"
21#include "llvm/ADT/Sequence.h"
22#include "llvm/CodeGen/LivePhysRegs.h"
23#include "llvm/CodeGen/LiveVariables.h"
24#include "llvm/CodeGen/MachineConstantPool.h"
25#include "llvm/CodeGen/MachineDominators.h"
26#include "llvm/CodeGen/MachineFrameInfo.h"
27#include "llvm/CodeGen/MachineInstrBuilder.h"
28#include "llvm/CodeGen/MachineModuleInfo.h"
29#include "llvm/CodeGen/MachineRegisterInfo.h"
30#include "llvm/CodeGen/StackMaps.h"
31#include "llvm/IR/DebugInfoMetadata.h"
32#include "llvm/IR/DerivedTypes.h"
33#include "llvm/IR/Function.h"
34#include "llvm/MC/MCAsmInfo.h"
35#include "llvm/MC/MCExpr.h"
36#include "llvm/MC/MCInst.h"
37#include "llvm/Support/CommandLine.h"
38#include "llvm/Support/Debug.h"
39#include "llvm/Support/ErrorHandling.h"
40#include "llvm/Support/raw_ostream.h"
41#include "llvm/Target/TargetOptions.h"
42
43using namespace llvm;
44
45#define DEBUG_TYPE"x86-instr-info" "x86-instr-info"
46
47#define GET_INSTRINFO_CTOR_DTOR
48#include "X86GenInstrInfo.inc"
49
50static cl::opt<bool>
51 NoFusing("disable-spill-fusing",
52 cl::desc("Disable fusing of spill code into instructions"),
53 cl::Hidden);
54static cl::opt<bool>
55PrintFailedFusing("print-failed-fuse-candidates",
56 cl::desc("Print instructions that the allocator wants to"
57 " fuse, but the X86 backend currently can't"),
58 cl::Hidden);
59static cl::opt<bool>
60ReMatPICStubLoad("remat-pic-stub-load",
61 cl::desc("Re-materialize load from stub in PIC mode"),
62 cl::init(false), cl::Hidden);
63static cl::opt<unsigned>
64PartialRegUpdateClearance("partial-reg-update-clearance",
65 cl::desc("Clearance between two register writes "
66 "for inserting XOR to avoid partial "
67 "register update"),
68 cl::init(64), cl::Hidden);
69static cl::opt<unsigned>
70UndefRegClearance("undef-reg-clearance",
71 cl::desc("How many idle instructions we would like before "
72 "certain undef register reads"),
73 cl::init(128), cl::Hidden);
74
75
76// Pin the vtable to this file.
77void X86InstrInfo::anchor() {}
78
79X86InstrInfo::X86InstrInfo(X86Subtarget &STI)
80 : X86GenInstrInfo((STI.isTarget64BitLP64() ? X86::ADJCALLSTACKDOWN64
81 : X86::ADJCALLSTACKDOWN32),
82 (STI.isTarget64BitLP64() ? X86::ADJCALLSTACKUP64
83 : X86::ADJCALLSTACKUP32),
84 X86::CATCHRET,
85 (STI.is64Bit() ? X86::RETQ : X86::RETL)),
86 Subtarget(STI), RI(STI.getTargetTriple()) {
87}
88
89bool
90X86InstrInfo::isCoalescableExtInstr(const MachineInstr &MI,
91 Register &SrcReg, Register &DstReg,
92 unsigned &SubIdx) const {
93 switch (MI.getOpcode()) {
94 default: break;
95 case X86::MOVSX16rr8:
96 case X86::MOVZX16rr8:
97 case X86::MOVSX32rr8:
98 case X86::MOVZX32rr8:
99 case X86::MOVSX64rr8:
100 if (!Subtarget.is64Bit())
101 // It's not always legal to reference the low 8-bit of the larger
102 // register in 32-bit mode.
103 return false;
104 LLVM_FALLTHROUGH[[gnu::fallthrough]];
105 case X86::MOVSX32rr16:
106 case X86::MOVZX32rr16:
107 case X86::MOVSX64rr16:
108 case X86::MOVSX64rr32: {
109 if (MI.getOperand(0).getSubReg() || MI.getOperand(1).getSubReg())
110 // Be conservative.
111 return false;
112 SrcReg = MI.getOperand(1).getReg();
113 DstReg = MI.getOperand(0).getReg();
114 switch (MI.getOpcode()) {
115 default: llvm_unreachable("Unreachable!")::llvm::llvm_unreachable_internal("Unreachable!", "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 115)
;
116 case X86::MOVSX16rr8:
117 case X86::MOVZX16rr8:
118 case X86::MOVSX32rr8:
119 case X86::MOVZX32rr8:
120 case X86::MOVSX64rr8:
121 SubIdx = X86::sub_8bit;
122 break;
123 case X86::MOVSX32rr16:
124 case X86::MOVZX32rr16:
125 case X86::MOVSX64rr16:
126 SubIdx = X86::sub_16bit;
127 break;
128 case X86::MOVSX64rr32:
129 SubIdx = X86::sub_32bit;
130 break;
131 }
132 return true;
133 }
134 }
135 return false;
136}
137
138bool X86InstrInfo::isDataInvariant(MachineInstr &MI) {
139 switch (MI.getOpcode()) {
140 default:
141 // By default, assume that the instruction is not data invariant.
142 return false;
143
144 // Some target-independent operations that trivially lower to data-invariant
145 // instructions.
146 case TargetOpcode::COPY:
147 case TargetOpcode::INSERT_SUBREG:
148 case TargetOpcode::SUBREG_TO_REG:
149 return true;
150
151 // On x86 it is believed that imul is constant time w.r.t. the loaded data.
152 // However, they set flags and are perhaps the most surprisingly constant
153 // time operations so we call them out here separately.
154 case X86::IMUL16rr:
155 case X86::IMUL16rri8:
156 case X86::IMUL16rri:
157 case X86::IMUL32rr:
158 case X86::IMUL32rri8:
159 case X86::IMUL32rri:
160 case X86::IMUL64rr:
161 case X86::IMUL64rri32:
162 case X86::IMUL64rri8:
163
164 // Bit scanning and counting instructions that are somewhat surprisingly
165 // constant time as they scan across bits and do other fairly complex
166 // operations like popcnt, but are believed to be constant time on x86.
167 // However, these set flags.
168 case X86::BSF16rr:
169 case X86::BSF32rr:
170 case X86::BSF64rr:
171 case X86::BSR16rr:
172 case X86::BSR32rr:
173 case X86::BSR64rr:
174 case X86::LZCNT16rr:
175 case X86::LZCNT32rr:
176 case X86::LZCNT64rr:
177 case X86::POPCNT16rr:
178 case X86::POPCNT32rr:
179 case X86::POPCNT64rr:
180 case X86::TZCNT16rr:
181 case X86::TZCNT32rr:
182 case X86::TZCNT64rr:
183
184 // Bit manipulation instructions are effectively combinations of basic
185 // arithmetic ops, and should still execute in constant time. These also
186 // set flags.
187 case X86::BLCFILL32rr:
188 case X86::BLCFILL64rr:
189 case X86::BLCI32rr:
190 case X86::BLCI64rr:
191 case X86::BLCIC32rr:
192 case X86::BLCIC64rr:
193 case X86::BLCMSK32rr:
194 case X86::BLCMSK64rr:
195 case X86::BLCS32rr:
196 case X86::BLCS64rr:
197 case X86::BLSFILL32rr:
198 case X86::BLSFILL64rr:
199 case X86::BLSI32rr:
200 case X86::BLSI64rr:
201 case X86::BLSIC32rr:
202 case X86::BLSIC64rr:
203 case X86::BLSMSK32rr:
204 case X86::BLSMSK64rr:
205 case X86::BLSR32rr:
206 case X86::BLSR64rr:
207 case X86::TZMSK32rr:
208 case X86::TZMSK64rr:
209
210 // Bit extracting and clearing instructions should execute in constant time,
211 // and set flags.
212 case X86::BEXTR32rr:
213 case X86::BEXTR64rr:
214 case X86::BEXTRI32ri:
215 case X86::BEXTRI64ri:
216 case X86::BZHI32rr:
217 case X86::BZHI64rr:
218
219 // Shift and rotate.
220 case X86::ROL8r1:
221 case X86::ROL16r1:
222 case X86::ROL32r1:
223 case X86::ROL64r1:
224 case X86::ROL8rCL:
225 case X86::ROL16rCL:
226 case X86::ROL32rCL:
227 case X86::ROL64rCL:
228 case X86::ROL8ri:
229 case X86::ROL16ri:
230 case X86::ROL32ri:
231 case X86::ROL64ri:
232 case X86::ROR8r1:
233 case X86::ROR16r1:
234 case X86::ROR32r1:
235 case X86::ROR64r1:
236 case X86::ROR8rCL:
237 case X86::ROR16rCL:
238 case X86::ROR32rCL:
239 case X86::ROR64rCL:
240 case X86::ROR8ri:
241 case X86::ROR16ri:
242 case X86::ROR32ri:
243 case X86::ROR64ri:
244 case X86::SAR8r1:
245 case X86::SAR16r1:
246 case X86::SAR32r1:
247 case X86::SAR64r1:
248 case X86::SAR8rCL:
249 case X86::SAR16rCL:
250 case X86::SAR32rCL:
251 case X86::SAR64rCL:
252 case X86::SAR8ri:
253 case X86::SAR16ri:
254 case X86::SAR32ri:
255 case X86::SAR64ri:
256 case X86::SHL8r1:
257 case X86::SHL16r1:
258 case X86::SHL32r1:
259 case X86::SHL64r1:
260 case X86::SHL8rCL:
261 case X86::SHL16rCL:
262 case X86::SHL32rCL:
263 case X86::SHL64rCL:
264 case X86::SHL8ri:
265 case X86::SHL16ri:
266 case X86::SHL32ri:
267 case X86::SHL64ri:
268 case X86::SHR8r1:
269 case X86::SHR16r1:
270 case X86::SHR32r1:
271 case X86::SHR64r1:
272 case X86::SHR8rCL:
273 case X86::SHR16rCL:
274 case X86::SHR32rCL:
275 case X86::SHR64rCL:
276 case X86::SHR8ri:
277 case X86::SHR16ri:
278 case X86::SHR32ri:
279 case X86::SHR64ri:
280 case X86::SHLD16rrCL:
281 case X86::SHLD32rrCL:
282 case X86::SHLD64rrCL:
283 case X86::SHLD16rri8:
284 case X86::SHLD32rri8:
285 case X86::SHLD64rri8:
286 case X86::SHRD16rrCL:
287 case X86::SHRD32rrCL:
288 case X86::SHRD64rrCL:
289 case X86::SHRD16rri8:
290 case X86::SHRD32rri8:
291 case X86::SHRD64rri8:
292
293 // Basic arithmetic is constant time on the input but does set flags.
294 case X86::ADC8rr:
295 case X86::ADC8ri:
296 case X86::ADC16rr:
297 case X86::ADC16ri:
298 case X86::ADC16ri8:
299 case X86::ADC32rr:
300 case X86::ADC32ri:
301 case X86::ADC32ri8:
302 case X86::ADC64rr:
303 case X86::ADC64ri8:
304 case X86::ADC64ri32:
305 case X86::ADD8rr:
306 case X86::ADD8ri:
307 case X86::ADD16rr:
308 case X86::ADD16ri:
309 case X86::ADD16ri8:
310 case X86::ADD32rr:
311 case X86::ADD32ri:
312 case X86::ADD32ri8:
313 case X86::ADD64rr:
314 case X86::ADD64ri8:
315 case X86::ADD64ri32:
316 case X86::AND8rr:
317 case X86::AND8ri:
318 case X86::AND16rr:
319 case X86::AND16ri:
320 case X86::AND16ri8:
321 case X86::AND32rr:
322 case X86::AND32ri:
323 case X86::AND32ri8:
324 case X86::AND64rr:
325 case X86::AND64ri8:
326 case X86::AND64ri32:
327 case X86::OR8rr:
328 case X86::OR8ri:
329 case X86::OR16rr:
330 case X86::OR16ri:
331 case X86::OR16ri8:
332 case X86::OR32rr:
333 case X86::OR32ri:
334 case X86::OR32ri8:
335 case X86::OR64rr:
336 case X86::OR64ri8:
337 case X86::OR64ri32:
338 case X86::SBB8rr:
339 case X86::SBB8ri:
340 case X86::SBB16rr:
341 case X86::SBB16ri:
342 case X86::SBB16ri8:
343 case X86::SBB32rr:
344 case X86::SBB32ri:
345 case X86::SBB32ri8:
346 case X86::SBB64rr:
347 case X86::SBB64ri8:
348 case X86::SBB64ri32:
349 case X86::SUB8rr:
350 case X86::SUB8ri:
351 case X86::SUB16rr:
352 case X86::SUB16ri:
353 case X86::SUB16ri8:
354 case X86::SUB32rr:
355 case X86::SUB32ri:
356 case X86::SUB32ri8:
357 case X86::SUB64rr:
358 case X86::SUB64ri8:
359 case X86::SUB64ri32:
360 case X86::XOR8rr:
361 case X86::XOR8ri:
362 case X86::XOR16rr:
363 case X86::XOR16ri:
364 case X86::XOR16ri8:
365 case X86::XOR32rr:
366 case X86::XOR32ri:
367 case X86::XOR32ri8:
368 case X86::XOR64rr:
369 case X86::XOR64ri8:
370 case X86::XOR64ri32:
371 // Arithmetic with just 32-bit and 64-bit variants and no immediates.
372 case X86::ADCX32rr:
373 case X86::ADCX64rr:
374 case X86::ADOX32rr:
375 case X86::ADOX64rr:
376 case X86::ANDN32rr:
377 case X86::ANDN64rr:
378 // Unary arithmetic operations.
379 case X86::DEC8r:
380 case X86::DEC16r:
381 case X86::DEC32r:
382 case X86::DEC64r:
383 case X86::INC8r:
384 case X86::INC16r:
385 case X86::INC32r:
386 case X86::INC64r:
387 case X86::NEG8r:
388 case X86::NEG16r:
389 case X86::NEG32r:
390 case X86::NEG64r:
391
392 // Unlike other arithmetic, NOT doesn't set EFLAGS.
393 case X86::NOT8r:
394 case X86::NOT16r:
395 case X86::NOT32r:
396 case X86::NOT64r:
397
398 // Various move instructions used to zero or sign extend things. Note that we
399 // intentionally don't support the _NOREX variants as we can't handle that
400 // register constraint anyways.
401 case X86::MOVSX16rr8:
402 case X86::MOVSX32rr8:
403 case X86::MOVSX32rr16:
404 case X86::MOVSX64rr8:
405 case X86::MOVSX64rr16:
406 case X86::MOVSX64rr32:
407 case X86::MOVZX16rr8:
408 case X86::MOVZX32rr8:
409 case X86::MOVZX32rr16:
410 case X86::MOVZX64rr8:
411 case X86::MOVZX64rr16:
412 case X86::MOV32rr:
413
414 // Arithmetic instructions that are both constant time and don't set flags.
415 case X86::RORX32ri:
416 case X86::RORX64ri:
417 case X86::SARX32rr:
418 case X86::SARX64rr:
419 case X86::SHLX32rr:
420 case X86::SHLX64rr:
421 case X86::SHRX32rr:
422 case X86::SHRX64rr:
423
424 // LEA doesn't actually access memory, and its arithmetic is constant time.
425 case X86::LEA16r:
426 case X86::LEA32r:
427 case X86::LEA64_32r:
428 case X86::LEA64r:
429 return true;
430 }
431}
432
433bool X86InstrInfo::isDataInvariantLoad(MachineInstr &MI) {
434 switch (MI.getOpcode()) {
435 default:
436 // By default, assume that the load will immediately leak.
437 return false;
438
439 // On x86 it is believed that imul is constant time w.r.t. the loaded data.
440 // However, they set flags and are perhaps the most surprisingly constant
441 // time operations so we call them out here separately.
442 case X86::IMUL16rm:
443 case X86::IMUL16rmi8:
444 case X86::IMUL16rmi:
445 case X86::IMUL32rm:
446 case X86::IMUL32rmi8:
447 case X86::IMUL32rmi:
448 case X86::IMUL64rm:
449 case X86::IMUL64rmi32:
450 case X86::IMUL64rmi8:
451
452 // Bit scanning and counting instructions that are somewhat surprisingly
453 // constant time as they scan across bits and do other fairly complex
454 // operations like popcnt, but are believed to be constant time on x86.
455 // However, these set flags.
456 case X86::BSF16rm:
457 case X86::BSF32rm:
458 case X86::BSF64rm:
459 case X86::BSR16rm:
460 case X86::BSR32rm:
461 case X86::BSR64rm:
462 case X86::LZCNT16rm:
463 case X86::LZCNT32rm:
464 case X86::LZCNT64rm:
465 case X86::POPCNT16rm:
466 case X86::POPCNT32rm:
467 case X86::POPCNT64rm:
468 case X86::TZCNT16rm:
469 case X86::TZCNT32rm:
470 case X86::TZCNT64rm:
471
472 // Bit manipulation instructions are effectively combinations of basic
473 // arithmetic ops, and should still execute in constant time. These also
474 // set flags.
475 case X86::BLCFILL32rm:
476 case X86::BLCFILL64rm:
477 case X86::BLCI32rm:
478 case X86::BLCI64rm:
479 case X86::BLCIC32rm:
480 case X86::BLCIC64rm:
481 case X86::BLCMSK32rm:
482 case X86::BLCMSK64rm:
483 case X86::BLCS32rm:
484 case X86::BLCS64rm:
485 case X86::BLSFILL32rm:
486 case X86::BLSFILL64rm:
487 case X86::BLSI32rm:
488 case X86::BLSI64rm:
489 case X86::BLSIC32rm:
490 case X86::BLSIC64rm:
491 case X86::BLSMSK32rm:
492 case X86::BLSMSK64rm:
493 case X86::BLSR32rm:
494 case X86::BLSR64rm:
495 case X86::TZMSK32rm:
496 case X86::TZMSK64rm:
497
498 // Bit extracting and clearing instructions should execute in constant time,
499 // and set flags.
500 case X86::BEXTR32rm:
501 case X86::BEXTR64rm:
502 case X86::BEXTRI32mi:
503 case X86::BEXTRI64mi:
504 case X86::BZHI32rm:
505 case X86::BZHI64rm:
506
507 // Basic arithmetic is constant time on the input but does set flags.
508 case X86::ADC8rm:
509 case X86::ADC16rm:
510 case X86::ADC32rm:
511 case X86::ADC64rm:
512 case X86::ADCX32rm:
513 case X86::ADCX64rm:
514 case X86::ADD8rm:
515 case X86::ADD16rm:
516 case X86::ADD32rm:
517 case X86::ADD64rm:
518 case X86::ADOX32rm:
519 case X86::ADOX64rm:
520 case X86::AND8rm:
521 case X86::AND16rm:
522 case X86::AND32rm:
523 case X86::AND64rm:
524 case X86::ANDN32rm:
525 case X86::ANDN64rm:
526 case X86::OR8rm:
527 case X86::OR16rm:
528 case X86::OR32rm:
529 case X86::OR64rm:
530 case X86::SBB8rm:
531 case X86::SBB16rm:
532 case X86::SBB32rm:
533 case X86::SBB64rm:
534 case X86::SUB8rm:
535 case X86::SUB16rm:
536 case X86::SUB32rm:
537 case X86::SUB64rm:
538 case X86::XOR8rm:
539 case X86::XOR16rm:
540 case X86::XOR32rm:
541 case X86::XOR64rm:
542
543 // Integer multiply w/o affecting flags is still believed to be constant
544 // time on x86. Called out separately as this is among the most surprising
545 // instructions to exhibit that behavior.
546 case X86::MULX32rm:
547 case X86::MULX64rm:
548
549 // Arithmetic instructions that are both constant time and don't set flags.
550 case X86::RORX32mi:
551 case X86::RORX64mi:
552 case X86::SARX32rm:
553 case X86::SARX64rm:
554 case X86::SHLX32rm:
555 case X86::SHLX64rm:
556 case X86::SHRX32rm:
557 case X86::SHRX64rm:
558
559 // Conversions are believed to be constant time and don't set flags.
560 case X86::CVTTSD2SI64rm:
561 case X86::VCVTTSD2SI64rm:
562 case X86::VCVTTSD2SI64Zrm:
563 case X86::CVTTSD2SIrm:
564 case X86::VCVTTSD2SIrm:
565 case X86::VCVTTSD2SIZrm:
566 case X86::CVTTSS2SI64rm:
567 case X86::VCVTTSS2SI64rm:
568 case X86::VCVTTSS2SI64Zrm:
569 case X86::CVTTSS2SIrm:
570 case X86::VCVTTSS2SIrm:
571 case X86::VCVTTSS2SIZrm:
572 case X86::CVTSI2SDrm:
573 case X86::VCVTSI2SDrm:
574 case X86::VCVTSI2SDZrm:
575 case X86::CVTSI2SSrm:
576 case X86::VCVTSI2SSrm:
577 case X86::VCVTSI2SSZrm:
578 case X86::CVTSI642SDrm:
579 case X86::VCVTSI642SDrm:
580 case X86::VCVTSI642SDZrm:
581 case X86::CVTSI642SSrm:
582 case X86::VCVTSI642SSrm:
583 case X86::VCVTSI642SSZrm:
584 case X86::CVTSS2SDrm:
585 case X86::VCVTSS2SDrm:
586 case X86::VCVTSS2SDZrm:
587 case X86::CVTSD2SSrm:
588 case X86::VCVTSD2SSrm:
589 case X86::VCVTSD2SSZrm:
590 // AVX512 added unsigned integer conversions.
591 case X86::VCVTTSD2USI64Zrm:
592 case X86::VCVTTSD2USIZrm:
593 case X86::VCVTTSS2USI64Zrm:
594 case X86::VCVTTSS2USIZrm:
595 case X86::VCVTUSI2SDZrm:
596 case X86::VCVTUSI642SDZrm:
597 case X86::VCVTUSI2SSZrm:
598 case X86::VCVTUSI642SSZrm:
599
600 // Loads to register don't set flags.
601 case X86::MOV8rm:
602 case X86::MOV8rm_NOREX:
603 case X86::MOV16rm:
604 case X86::MOV32rm:
605 case X86::MOV64rm:
606 case X86::MOVSX16rm8:
607 case X86::MOVSX32rm16:
608 case X86::MOVSX32rm8:
609 case X86::MOVSX32rm8_NOREX:
610 case X86::MOVSX64rm16:
611 case X86::MOVSX64rm32:
612 case X86::MOVSX64rm8:
613 case X86::MOVZX16rm8:
614 case X86::MOVZX32rm16:
615 case X86::MOVZX32rm8:
616 case X86::MOVZX32rm8_NOREX:
617 case X86::MOVZX64rm16:
618 case X86::MOVZX64rm8:
619 return true;
620 }
621}
622
623int X86InstrInfo::getSPAdjust(const MachineInstr &MI) const {
624 const MachineFunction *MF = MI.getParent()->getParent();
625 const TargetFrameLowering *TFI = MF->getSubtarget().getFrameLowering();
626
627 if (isFrameInstr(MI)) {
628 int SPAdj = alignTo(getFrameSize(MI), TFI->getStackAlign());
629 SPAdj -= getFrameAdjustment(MI);
630 if (!isFrameSetup(MI))
631 SPAdj = -SPAdj;
632 return SPAdj;
633 }
634
635 // To know whether a call adjusts the stack, we need information
636 // that is bound to the following ADJCALLSTACKUP pseudo.
637 // Look for the next ADJCALLSTACKUP that follows the call.
638 if (MI.isCall()) {
639 const MachineBasicBlock *MBB = MI.getParent();
640 auto I = ++MachineBasicBlock::const_iterator(MI);
641 for (auto E = MBB->end(); I != E; ++I) {
642 if (I->getOpcode() == getCallFrameDestroyOpcode() ||
643 I->isCall())
644 break;
645 }
646
647 // If we could not find a frame destroy opcode, then it has already
648 // been simplified, so we don't care.
649 if (I->getOpcode() != getCallFrameDestroyOpcode())
650 return 0;
651
652 return -(I->getOperand(1).getImm());
653 }
654
655 // Currently handle only PUSHes we can reasonably expect to see
656 // in call sequences
657 switch (MI.getOpcode()) {
658 default:
659 return 0;
660 case X86::PUSH32i8:
661 case X86::PUSH32r:
662 case X86::PUSH32rmm:
663 case X86::PUSH32rmr:
664 case X86::PUSHi32:
665 return 4;
666 case X86::PUSH64i8:
667 case X86::PUSH64r:
668 case X86::PUSH64rmm:
669 case X86::PUSH64rmr:
670 case X86::PUSH64i32:
671 return 8;
672 }
673}
674
675/// Return true and the FrameIndex if the specified
676/// operand and follow operands form a reference to the stack frame.
677bool X86InstrInfo::isFrameOperand(const MachineInstr &MI, unsigned int Op,
678 int &FrameIndex) const {
679 if (MI.getOperand(Op + X86::AddrBaseReg).isFI() &&
680 MI.getOperand(Op + X86::AddrScaleAmt).isImm() &&
681 MI.getOperand(Op + X86::AddrIndexReg).isReg() &&
682 MI.getOperand(Op + X86::AddrDisp).isImm() &&
683 MI.getOperand(Op + X86::AddrScaleAmt).getImm() == 1 &&
684 MI.getOperand(Op + X86::AddrIndexReg).getReg() == 0 &&
685 MI.getOperand(Op + X86::AddrDisp).getImm() == 0) {
686 FrameIndex = MI.getOperand(Op + X86::AddrBaseReg).getIndex();
687 return true;
688 }
689 return false;
690}
691
692static bool isFrameLoadOpcode(int Opcode, unsigned &MemBytes) {
693 switch (Opcode) {
694 default:
695 return false;
696 case X86::MOV8rm:
697 case X86::KMOVBkm:
698 MemBytes = 1;
699 return true;
700 case X86::MOV16rm:
701 case X86::KMOVWkm:
702 case X86::VMOVSHZrm:
703 case X86::VMOVSHZrm_alt:
704 MemBytes = 2;
705 return true;
706 case X86::MOV32rm:
707 case X86::MOVSSrm:
708 case X86::MOVSSrm_alt:
709 case X86::VMOVSSrm:
710 case X86::VMOVSSrm_alt:
711 case X86::VMOVSSZrm:
712 case X86::VMOVSSZrm_alt:
713 case X86::KMOVDkm:
714 MemBytes = 4;
715 return true;
716 case X86::MOV64rm:
717 case X86::LD_Fp64m:
718 case X86::MOVSDrm:
719 case X86::MOVSDrm_alt:
720 case X86::VMOVSDrm:
721 case X86::VMOVSDrm_alt:
722 case X86::VMOVSDZrm:
723 case X86::VMOVSDZrm_alt:
724 case X86::MMX_MOVD64rm:
725 case X86::MMX_MOVQ64rm:
726 case X86::KMOVQkm:
727 MemBytes = 8;
728 return true;
729 case X86::MOVAPSrm:
730 case X86::MOVUPSrm:
731 case X86::MOVAPDrm:
732 case X86::MOVUPDrm:
733 case X86::MOVDQArm:
734 case X86::MOVDQUrm:
735 case X86::VMOVAPSrm:
736 case X86::VMOVUPSrm:
737 case X86::VMOVAPDrm:
738 case X86::VMOVUPDrm:
739 case X86::VMOVDQArm:
740 case X86::VMOVDQUrm:
741 case X86::VMOVAPSZ128rm:
742 case X86::VMOVUPSZ128rm:
743 case X86::VMOVAPSZ128rm_NOVLX:
744 case X86::VMOVUPSZ128rm_NOVLX:
745 case X86::VMOVAPDZ128rm:
746 case X86::VMOVUPDZ128rm:
747 case X86::VMOVDQU8Z128rm:
748 case X86::VMOVDQU16Z128rm:
749 case X86::VMOVDQA32Z128rm:
750 case X86::VMOVDQU32Z128rm:
751 case X86::VMOVDQA64Z128rm:
752 case X86::VMOVDQU64Z128rm:
753 MemBytes = 16;
754 return true;
755 case X86::VMOVAPSYrm:
756 case X86::VMOVUPSYrm:
757 case X86::VMOVAPDYrm:
758 case X86::VMOVUPDYrm:
759 case X86::VMOVDQAYrm:
760 case X86::VMOVDQUYrm:
761 case X86::VMOVAPSZ256rm:
762 case X86::VMOVUPSZ256rm:
763 case X86::VMOVAPSZ256rm_NOVLX:
764 case X86::VMOVUPSZ256rm_NOVLX:
765 case X86::VMOVAPDZ256rm:
766 case X86::VMOVUPDZ256rm:
767 case X86::VMOVDQU8Z256rm:
768 case X86::VMOVDQU16Z256rm:
769 case X86::VMOVDQA32Z256rm:
770 case X86::VMOVDQU32Z256rm:
771 case X86::VMOVDQA64Z256rm:
772 case X86::VMOVDQU64Z256rm:
773 MemBytes = 32;
774 return true;
775 case X86::VMOVAPSZrm:
776 case X86::VMOVUPSZrm:
777 case X86::VMOVAPDZrm:
778 case X86::VMOVUPDZrm:
779 case X86::VMOVDQU8Zrm:
780 case X86::VMOVDQU16Zrm:
781 case X86::VMOVDQA32Zrm:
782 case X86::VMOVDQU32Zrm:
783 case X86::VMOVDQA64Zrm:
784 case X86::VMOVDQU64Zrm:
785 MemBytes = 64;
786 return true;
787 }
788}
789
790static bool isFrameStoreOpcode(int Opcode, unsigned &MemBytes) {
791 switch (Opcode) {
792 default:
793 return false;
794 case X86::MOV8mr:
795 case X86::KMOVBmk:
796 MemBytes = 1;
797 return true;
798 case X86::MOV16mr:
799 case X86::KMOVWmk:
800 case X86::VMOVSHZmr:
801 MemBytes = 2;
802 return true;
803 case X86::MOV32mr:
804 case X86::MOVSSmr:
805 case X86::VMOVSSmr:
806 case X86::VMOVSSZmr:
807 case X86::KMOVDmk:
808 MemBytes = 4;
809 return true;
810 case X86::MOV64mr:
811 case X86::ST_FpP64m:
812 case X86::MOVSDmr:
813 case X86::VMOVSDmr:
814 case X86::VMOVSDZmr:
815 case X86::MMX_MOVD64mr:
816 case X86::MMX_MOVQ64mr:
817 case X86::MMX_MOVNTQmr:
818 case X86::KMOVQmk:
819 MemBytes = 8;
820 return true;
821 case X86::MOVAPSmr:
822 case X86::MOVUPSmr:
823 case X86::MOVAPDmr:
824 case X86::MOVUPDmr:
825 case X86::MOVDQAmr:
826 case X86::MOVDQUmr:
827 case X86::VMOVAPSmr:
828 case X86::VMOVUPSmr:
829 case X86::VMOVAPDmr:
830 case X86::VMOVUPDmr:
831 case X86::VMOVDQAmr:
832 case X86::VMOVDQUmr:
833 case X86::VMOVUPSZ128mr:
834 case X86::VMOVAPSZ128mr:
835 case X86::VMOVUPSZ128mr_NOVLX:
836 case X86::VMOVAPSZ128mr_NOVLX:
837 case X86::VMOVUPDZ128mr:
838 case X86::VMOVAPDZ128mr:
839 case X86::VMOVDQA32Z128mr:
840 case X86::VMOVDQU32Z128mr:
841 case X86::VMOVDQA64Z128mr:
842 case X86::VMOVDQU64Z128mr:
843 case X86::VMOVDQU8Z128mr:
844 case X86::VMOVDQU16Z128mr:
845 MemBytes = 16;
846 return true;
847 case X86::VMOVUPSYmr:
848 case X86::VMOVAPSYmr:
849 case X86::VMOVUPDYmr:
850 case X86::VMOVAPDYmr:
851 case X86::VMOVDQUYmr:
852 case X86::VMOVDQAYmr:
853 case X86::VMOVUPSZ256mr:
854 case X86::VMOVAPSZ256mr:
855 case X86::VMOVUPSZ256mr_NOVLX:
856 case X86::VMOVAPSZ256mr_NOVLX:
857 case X86::VMOVUPDZ256mr:
858 case X86::VMOVAPDZ256mr:
859 case X86::VMOVDQU8Z256mr:
860 case X86::VMOVDQU16Z256mr:
861 case X86::VMOVDQA32Z256mr:
862 case X86::VMOVDQU32Z256mr:
863 case X86::VMOVDQA64Z256mr:
864 case X86::VMOVDQU64Z256mr:
865 MemBytes = 32;
866 return true;
867 case X86::VMOVUPSZmr:
868 case X86::VMOVAPSZmr:
869 case X86::VMOVUPDZmr:
870 case X86::VMOVAPDZmr:
871 case X86::VMOVDQU8Zmr:
872 case X86::VMOVDQU16Zmr:
873 case X86::VMOVDQA32Zmr:
874 case X86::VMOVDQU32Zmr:
875 case X86::VMOVDQA64Zmr:
876 case X86::VMOVDQU64Zmr:
877 MemBytes = 64;
878 return true;
879 }
880 return false;
881}
882
883unsigned X86InstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
884 int &FrameIndex) const {
885 unsigned Dummy;
886 return X86InstrInfo::isLoadFromStackSlot(MI, FrameIndex, Dummy);
887}
888
889unsigned X86InstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
890 int &FrameIndex,
891 unsigned &MemBytes) const {
892 if (isFrameLoadOpcode(MI.getOpcode(), MemBytes))
893 if (MI.getOperand(0).getSubReg() == 0 && isFrameOperand(MI, 1, FrameIndex))
894 return MI.getOperand(0).getReg();
895 return 0;
896}
897
898unsigned X86InstrInfo::isLoadFromStackSlotPostFE(const MachineInstr &MI,
899 int &FrameIndex) const {
900 unsigned Dummy;
901 if (isFrameLoadOpcode(MI.getOpcode(), Dummy)) {
902 unsigned Reg;
903 if ((Reg = isLoadFromStackSlot(MI, FrameIndex)))
904 return Reg;
905 // Check for post-frame index elimination operations
906 SmallVector<const MachineMemOperand *, 1> Accesses;
907 if (hasLoadFromStackSlot(MI, Accesses)) {
908 FrameIndex =
909 cast<FixedStackPseudoSourceValue>(Accesses.front()->getPseudoValue())
910 ->getFrameIndex();
911 return MI.getOperand(0).getReg();
912 }
913 }
914 return 0;
915}
916
917unsigned X86InstrInfo::isStoreToStackSlot(const MachineInstr &MI,
918 int &FrameIndex) const {
919 unsigned Dummy;
920 return X86InstrInfo::isStoreToStackSlot(MI, FrameIndex, Dummy);
921}
922
923unsigned X86InstrInfo::isStoreToStackSlot(const MachineInstr &MI,
924 int &FrameIndex,
925 unsigned &MemBytes) const {
926 if (isFrameStoreOpcode(MI.getOpcode(), MemBytes))
927 if (MI.getOperand(X86::AddrNumOperands).getSubReg() == 0 &&
928 isFrameOperand(MI, 0, FrameIndex))
929 return MI.getOperand(X86::AddrNumOperands).getReg();
930 return 0;
931}
932
933unsigned X86InstrInfo::isStoreToStackSlotPostFE(const MachineInstr &MI,
934 int &FrameIndex) const {
935 unsigned Dummy;
936 if (isFrameStoreOpcode(MI.getOpcode(), Dummy)) {
937 unsigned Reg;
938 if ((Reg = isStoreToStackSlot(MI, FrameIndex)))
939 return Reg;
940 // Check for post-frame index elimination operations
941 SmallVector<const MachineMemOperand *, 1> Accesses;
942 if (hasStoreToStackSlot(MI, Accesses)) {
943 FrameIndex =
944 cast<FixedStackPseudoSourceValue>(Accesses.front()->getPseudoValue())
945 ->getFrameIndex();
946 return MI.getOperand(X86::AddrNumOperands).getReg();
947 }
948 }
949 return 0;
950}
951
952/// Return true if register is PIC base; i.e.g defined by X86::MOVPC32r.
953static bool regIsPICBase(Register BaseReg, const MachineRegisterInfo &MRI) {
954 // Don't waste compile time scanning use-def chains of physregs.
955 if (!BaseReg.isVirtual())
956 return false;
957 bool isPICBase = false;
958 for (MachineRegisterInfo::def_instr_iterator I = MRI.def_instr_begin(BaseReg),
959 E = MRI.def_instr_end(); I != E; ++I) {
960 MachineInstr *DefMI = &*I;
961 if (DefMI->getOpcode() != X86::MOVPC32r)
962 return false;
963 assert(!isPICBase && "More than one PIC base?")(static_cast <bool> (!isPICBase && "More than one PIC base?"
) ? void (0) : __assert_fail ("!isPICBase && \"More than one PIC base?\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 963, __extension__ __PRETTY_FUNCTION__))
;
964 isPICBase = true;
965 }
966 return isPICBase;
967}
968
969bool X86InstrInfo::isReallyTriviallyReMaterializable(const MachineInstr &MI,
970 AAResults *AA) const {
971 switch (MI.getOpcode()) {
972 default:
973 // This function should only be called for opcodes with the ReMaterializable
974 // flag set.
975 llvm_unreachable("Unknown rematerializable operation!")::llvm::llvm_unreachable_internal("Unknown rematerializable operation!"
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 975)
;
976 break;
977
978 case X86::LOAD_STACK_GUARD:
979 case X86::AVX1_SETALLONES:
980 case X86::AVX2_SETALLONES:
981 case X86::AVX512_128_SET0:
982 case X86::AVX512_256_SET0:
983 case X86::AVX512_512_SET0:
984 case X86::AVX512_512_SETALLONES:
985 case X86::AVX512_FsFLD0SD:
986 case X86::AVX512_FsFLD0SH:
987 case X86::AVX512_FsFLD0SS:
988 case X86::AVX512_FsFLD0F128:
989 case X86::AVX_SET0:
990 case X86::FsFLD0SD:
991 case X86::FsFLD0SS:
992 case X86::FsFLD0F128:
993 case X86::KSET0D:
994 case X86::KSET0Q:
995 case X86::KSET0W:
996 case X86::KSET1D:
997 case X86::KSET1Q:
998 case X86::KSET1W:
999 case X86::MMX_SET0:
1000 case X86::MOV32ImmSExti8:
1001 case X86::MOV32r0:
1002 case X86::MOV32r1:
1003 case X86::MOV32r_1:
1004 case X86::MOV32ri64:
1005 case X86::MOV64ImmSExti8:
1006 case X86::V_SET0:
1007 case X86::V_SETALLONES:
1008 case X86::MOV16ri:
1009 case X86::MOV32ri:
1010 case X86::MOV64ri:
1011 case X86::MOV64ri32:
1012 case X86::MOV8ri:
1013 case X86::PTILEZEROV:
1014 return true;
1015
1016 case X86::MOV8rm:
1017 case X86::MOV8rm_NOREX:
1018 case X86::MOV16rm:
1019 case X86::MOV32rm:
1020 case X86::MOV64rm:
1021 case X86::MOVSSrm:
1022 case X86::MOVSSrm_alt:
1023 case X86::MOVSDrm:
1024 case X86::MOVSDrm_alt:
1025 case X86::MOVAPSrm:
1026 case X86::MOVUPSrm:
1027 case X86::MOVAPDrm:
1028 case X86::MOVUPDrm:
1029 case X86::MOVDQArm:
1030 case X86::MOVDQUrm:
1031 case X86::VMOVSSrm:
1032 case X86::VMOVSSrm_alt:
1033 case X86::VMOVSDrm:
1034 case X86::VMOVSDrm_alt:
1035 case X86::VMOVAPSrm:
1036 case X86::VMOVUPSrm:
1037 case X86::VMOVAPDrm:
1038 case X86::VMOVUPDrm:
1039 case X86::VMOVDQArm:
1040 case X86::VMOVDQUrm:
1041 case X86::VMOVAPSYrm:
1042 case X86::VMOVUPSYrm:
1043 case X86::VMOVAPDYrm:
1044 case X86::VMOVUPDYrm:
1045 case X86::VMOVDQAYrm:
1046 case X86::VMOVDQUYrm:
1047 case X86::MMX_MOVD64rm:
1048 case X86::MMX_MOVQ64rm:
1049 // AVX-512
1050 case X86::VMOVSSZrm:
1051 case X86::VMOVSSZrm_alt:
1052 case X86::VMOVSDZrm:
1053 case X86::VMOVSDZrm_alt:
1054 case X86::VMOVSHZrm:
1055 case X86::VMOVSHZrm_alt:
1056 case X86::VMOVAPDZ128rm:
1057 case X86::VMOVAPDZ256rm:
1058 case X86::VMOVAPDZrm:
1059 case X86::VMOVAPSZ128rm:
1060 case X86::VMOVAPSZ256rm:
1061 case X86::VMOVAPSZ128rm_NOVLX:
1062 case X86::VMOVAPSZ256rm_NOVLX:
1063 case X86::VMOVAPSZrm:
1064 case X86::VMOVDQA32Z128rm:
1065 case X86::VMOVDQA32Z256rm:
1066 case X86::VMOVDQA32Zrm:
1067 case X86::VMOVDQA64Z128rm:
1068 case X86::VMOVDQA64Z256rm:
1069 case X86::VMOVDQA64Zrm:
1070 case X86::VMOVDQU16Z128rm:
1071 case X86::VMOVDQU16Z256rm:
1072 case X86::VMOVDQU16Zrm:
1073 case X86::VMOVDQU32Z128rm:
1074 case X86::VMOVDQU32Z256rm:
1075 case X86::VMOVDQU32Zrm:
1076 case X86::VMOVDQU64Z128rm:
1077 case X86::VMOVDQU64Z256rm:
1078 case X86::VMOVDQU64Zrm:
1079 case X86::VMOVDQU8Z128rm:
1080 case X86::VMOVDQU8Z256rm:
1081 case X86::VMOVDQU8Zrm:
1082 case X86::VMOVUPDZ128rm:
1083 case X86::VMOVUPDZ256rm:
1084 case X86::VMOVUPDZrm:
1085 case X86::VMOVUPSZ128rm:
1086 case X86::VMOVUPSZ256rm:
1087 case X86::VMOVUPSZ128rm_NOVLX:
1088 case X86::VMOVUPSZ256rm_NOVLX:
1089 case X86::VMOVUPSZrm: {
1090 // Loads from constant pools are trivially rematerializable.
1091 if (MI.getOperand(1 + X86::AddrBaseReg).isReg() &&
1092 MI.getOperand(1 + X86::AddrScaleAmt).isImm() &&
1093 MI.getOperand(1 + X86::AddrIndexReg).isReg() &&
1094 MI.getOperand(1 + X86::AddrIndexReg).getReg() == 0 &&
1095 MI.isDereferenceableInvariantLoad(AA)) {
1096 Register BaseReg = MI.getOperand(1 + X86::AddrBaseReg).getReg();
1097 if (BaseReg == 0 || BaseReg == X86::RIP)
1098 return true;
1099 // Allow re-materialization of PIC load.
1100 if (!ReMatPICStubLoad && MI.getOperand(1 + X86::AddrDisp).isGlobal())
1101 return false;
1102 const MachineFunction &MF = *MI.getParent()->getParent();
1103 const MachineRegisterInfo &MRI = MF.getRegInfo();
1104 return regIsPICBase(BaseReg, MRI);
1105 }
1106 return false;
1107 }
1108
1109 case X86::LEA32r:
1110 case X86::LEA64r: {
1111 if (MI.getOperand(1 + X86::AddrScaleAmt).isImm() &&
1112 MI.getOperand(1 + X86::AddrIndexReg).isReg() &&
1113 MI.getOperand(1 + X86::AddrIndexReg).getReg() == 0 &&
1114 !MI.getOperand(1 + X86::AddrDisp).isReg()) {
1115 // lea fi#, lea GV, etc. are all rematerializable.
1116 if (!MI.getOperand(1 + X86::AddrBaseReg).isReg())
1117 return true;
1118 Register BaseReg = MI.getOperand(1 + X86::AddrBaseReg).getReg();
1119 if (BaseReg == 0)
1120 return true;
1121 // Allow re-materialization of lea PICBase + x.
1122 const MachineFunction &MF = *MI.getParent()->getParent();
1123 const MachineRegisterInfo &MRI = MF.getRegInfo();
1124 return regIsPICBase(BaseReg, MRI);
1125 }
1126 return false;
1127 }
1128 }
1129}
1130
1131void X86InstrInfo::reMaterialize(MachineBasicBlock &MBB,
1132 MachineBasicBlock::iterator I,
1133 Register DestReg, unsigned SubIdx,
1134 const MachineInstr &Orig,
1135 const TargetRegisterInfo &TRI) const {
1136 bool ClobbersEFLAGS = Orig.modifiesRegister(X86::EFLAGS, &TRI);
1137 if (ClobbersEFLAGS && MBB.computeRegisterLiveness(&TRI, X86::EFLAGS, I) !=
1138 MachineBasicBlock::LQR_Dead) {
1139 // The instruction clobbers EFLAGS. Re-materialize as MOV32ri to avoid side
1140 // effects.
1141 int Value;
1142 switch (Orig.getOpcode()) {
1143 case X86::MOV32r0: Value = 0; break;
1144 case X86::MOV32r1: Value = 1; break;
1145 case X86::MOV32r_1: Value = -1; break;
1146 default:
1147 llvm_unreachable("Unexpected instruction!")::llvm::llvm_unreachable_internal("Unexpected instruction!", "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 1147)
;
1148 }
1149
1150 const DebugLoc &DL = Orig.getDebugLoc();
1151 BuildMI(MBB, I, DL, get(X86::MOV32ri))
1152 .add(Orig.getOperand(0))
1153 .addImm(Value);
1154 } else {
1155 MachineInstr *MI = MBB.getParent()->CloneMachineInstr(&Orig);
1156 MBB.insert(I, MI);
1157 }
1158
1159 MachineInstr &NewMI = *std::prev(I);
1160 NewMI.substituteRegister(Orig.getOperand(0).getReg(), DestReg, SubIdx, TRI);
1161}
1162
1163/// True if MI has a condition code def, e.g. EFLAGS, that is not marked dead.
1164bool X86InstrInfo::hasLiveCondCodeDef(MachineInstr &MI) const {
1165 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
1166 MachineOperand &MO = MI.getOperand(i);
1167 if (MO.isReg() && MO.isDef() &&
1168 MO.getReg() == X86::EFLAGS && !MO.isDead()) {
1169 return true;
1170 }
1171 }
1172 return false;
1173}
1174
1175/// Check whether the shift count for a machine operand is non-zero.
1176inline static unsigned getTruncatedShiftCount(const MachineInstr &MI,
1177 unsigned ShiftAmtOperandIdx) {
1178 // The shift count is six bits with the REX.W prefix and five bits without.
1179 unsigned ShiftCountMask = (MI.getDesc().TSFlags & X86II::REX_W) ? 63 : 31;
1180 unsigned Imm = MI.getOperand(ShiftAmtOperandIdx).getImm();
1181 return Imm & ShiftCountMask;
1182}
1183
1184/// Check whether the given shift count is appropriate
1185/// can be represented by a LEA instruction.
1186inline static bool isTruncatedShiftCountForLEA(unsigned ShAmt) {
1187 // Left shift instructions can be transformed into load-effective-address
1188 // instructions if we can encode them appropriately.
1189 // A LEA instruction utilizes a SIB byte to encode its scale factor.
1190 // The SIB.scale field is two bits wide which means that we can encode any
1191 // shift amount less than 4.
1192 return ShAmt < 4 && ShAmt > 0;
1193}
1194
1195bool X86InstrInfo::classifyLEAReg(MachineInstr &MI, const MachineOperand &Src,
1196 unsigned Opc, bool AllowSP, Register &NewSrc,
1197 bool &isKill, MachineOperand &ImplicitOp,
1198 LiveVariables *LV) const {
1199 MachineFunction &MF = *MI.getParent()->getParent();
1200 const TargetRegisterClass *RC;
1201 if (AllowSP) {
1202 RC = Opc != X86::LEA32r ? &X86::GR64RegClass : &X86::GR32RegClass;
1203 } else {
1204 RC = Opc != X86::LEA32r ?
1205 &X86::GR64_NOSPRegClass : &X86::GR32_NOSPRegClass;
1206 }
1207 Register SrcReg = Src.getReg();
1208
1209 // For both LEA64 and LEA32 the register already has essentially the right
1210 // type (32-bit or 64-bit) we may just need to forbid SP.
1211 if (Opc != X86::LEA64_32r) {
1212 NewSrc = SrcReg;
1213 isKill = Src.isKill();
1214 assert(!Src.isUndef() && "Undef op doesn't need optimization")(static_cast <bool> (!Src.isUndef() && "Undef op doesn't need optimization"
) ? void (0) : __assert_fail ("!Src.isUndef() && \"Undef op doesn't need optimization\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 1214, __extension__ __PRETTY_FUNCTION__))
;
1215
1216 if (NewSrc.isVirtual() && !MF.getRegInfo().constrainRegClass(NewSrc, RC))
1217 return false;
1218
1219 return true;
1220 }
1221
1222 // This is for an LEA64_32r and incoming registers are 32-bit. One way or
1223 // another we need to add 64-bit registers to the final MI.
1224 if (SrcReg.isPhysical()) {
1225 ImplicitOp = Src;
1226 ImplicitOp.setImplicit();
1227
1228 NewSrc = getX86SubSuperRegister(Src.getReg(), 64);
1229 isKill = Src.isKill();
1230 assert(!Src.isUndef() && "Undef op doesn't need optimization")(static_cast <bool> (!Src.isUndef() && "Undef op doesn't need optimization"
) ? void (0) : __assert_fail ("!Src.isUndef() && \"Undef op doesn't need optimization\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 1230, __extension__ __PRETTY_FUNCTION__))
;
1231 } else {
1232 // Virtual register of the wrong class, we have to create a temporary 64-bit
1233 // vreg to feed into the LEA.
1234 NewSrc = MF.getRegInfo().createVirtualRegister(RC);
1235 MachineInstr *Copy =
1236 BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(TargetOpcode::COPY))
1237 .addReg(NewSrc, RegState::Define | RegState::Undef, X86::sub_32bit)
1238 .add(Src);
1239
1240 // Which is obviously going to be dead after we're done with it.
1241 isKill = true;
1242
1243 if (LV)
1244 LV->replaceKillInstruction(SrcReg, MI, *Copy);
1245 }
1246
1247 // We've set all the parameters without issue.
1248 return true;
1249}
1250
1251MachineInstr *X86InstrInfo::convertToThreeAddressWithLEA(unsigned MIOpc,
1252 MachineInstr &MI,
1253 LiveVariables *LV,
1254 bool Is8BitOp) const {
1255 // We handle 8-bit adds and various 16-bit opcodes in the switch below.
1256 MachineBasicBlock &MBB = *MI.getParent();
1257 MachineRegisterInfo &RegInfo = MBB.getParent()->getRegInfo();
1258 assert((Is8BitOp || RegInfo.getTargetRegisterInfo()->getRegSizeInBits((static_cast <bool> ((Is8BitOp || RegInfo.getTargetRegisterInfo
()->getRegSizeInBits( *RegInfo.getRegClass(MI.getOperand(0
).getReg())) == 16) && "Unexpected type for LEA transform"
) ? void (0) : __assert_fail ("(Is8BitOp || RegInfo.getTargetRegisterInfo()->getRegSizeInBits( *RegInfo.getRegClass(MI.getOperand(0).getReg())) == 16) && \"Unexpected type for LEA transform\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 1260, __extension__ __PRETTY_FUNCTION__))
1259 *RegInfo.getRegClass(MI.getOperand(0).getReg())) == 16) &&(static_cast <bool> ((Is8BitOp || RegInfo.getTargetRegisterInfo
()->getRegSizeInBits( *RegInfo.getRegClass(MI.getOperand(0
).getReg())) == 16) && "Unexpected type for LEA transform"
) ? void (0) : __assert_fail ("(Is8BitOp || RegInfo.getTargetRegisterInfo()->getRegSizeInBits( *RegInfo.getRegClass(MI.getOperand(0).getReg())) == 16) && \"Unexpected type for LEA transform\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 1260, __extension__ __PRETTY_FUNCTION__))
1260 "Unexpected type for LEA transform")(static_cast <bool> ((Is8BitOp || RegInfo.getTargetRegisterInfo
()->getRegSizeInBits( *RegInfo.getRegClass(MI.getOperand(0
).getReg())) == 16) && "Unexpected type for LEA transform"
) ? void (0) : __assert_fail ("(Is8BitOp || RegInfo.getTargetRegisterInfo()->getRegSizeInBits( *RegInfo.getRegClass(MI.getOperand(0).getReg())) == 16) && \"Unexpected type for LEA transform\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 1260, __extension__ __PRETTY_FUNCTION__))
;
1261
1262 // TODO: For a 32-bit target, we need to adjust the LEA variables with
1263 // something like this:
1264 // Opcode = X86::LEA32r;
1265 // InRegLEA = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
1266 // OutRegLEA =
1267 // Is8BitOp ? RegInfo.createVirtualRegister(&X86::GR32ABCD_RegClass)
1268 // : RegInfo.createVirtualRegister(&X86::GR32RegClass);
1269 if (!Subtarget.is64Bit())
1270 return nullptr;
1271
1272 unsigned Opcode = X86::LEA64_32r;
1273 Register InRegLEA = RegInfo.createVirtualRegister(&X86::GR64_NOSPRegClass);
1274 Register OutRegLEA = RegInfo.createVirtualRegister(&X86::GR32RegClass);
1275
1276 // Build and insert into an implicit UNDEF value. This is OK because
1277 // we will be shifting and then extracting the lower 8/16-bits.
1278 // This has the potential to cause partial register stall. e.g.
1279 // movw (%rbp,%rcx,2), %dx
1280 // leal -65(%rdx), %esi
1281 // But testing has shown this *does* help performance in 64-bit mode (at
1282 // least on modern x86 machines).
1283 MachineBasicBlock::iterator MBBI = MI.getIterator();
1284 Register Dest = MI.getOperand(0).getReg();
1285 Register Src = MI.getOperand(1).getReg();
1286 bool IsDead = MI.getOperand(0).isDead();
1287 bool IsKill = MI.getOperand(1).isKill();
1288 unsigned SubReg = Is8BitOp ? X86::sub_8bit : X86::sub_16bit;
1289 assert(!MI.getOperand(1).isUndef() && "Undef op doesn't need optimization")(static_cast <bool> (!MI.getOperand(1).isUndef() &&
"Undef op doesn't need optimization") ? void (0) : __assert_fail
("!MI.getOperand(1).isUndef() && \"Undef op doesn't need optimization\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 1289, __extension__ __PRETTY_FUNCTION__))
;
1290 BuildMI(MBB, MBBI, MI.getDebugLoc(), get(X86::IMPLICIT_DEF), InRegLEA);
1291 MachineInstr *InsMI =
1292 BuildMI(MBB, MBBI, MI.getDebugLoc(), get(TargetOpcode::COPY))
1293 .addReg(InRegLEA, RegState::Define, SubReg)
1294 .addReg(Src, getKillRegState(IsKill));
1295
1296 MachineInstrBuilder MIB =
1297 BuildMI(MBB, MBBI, MI.getDebugLoc(), get(Opcode), OutRegLEA);
1298 switch (MIOpc) {
1299 default: llvm_unreachable("Unreachable!")::llvm::llvm_unreachable_internal("Unreachable!", "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 1299)
;
1300 case X86::SHL8ri:
1301 case X86::SHL16ri: {
1302 unsigned ShAmt = MI.getOperand(2).getImm();
1303 MIB.addReg(0).addImm(1ULL << ShAmt)
1304 .addReg(InRegLEA, RegState::Kill).addImm(0).addReg(0);
1305 break;
1306 }
1307 case X86::INC8r:
1308 case X86::INC16r:
1309 addRegOffset(MIB, InRegLEA, true, 1);
1310 break;
1311 case X86::DEC8r:
1312 case X86::DEC16r:
1313 addRegOffset(MIB, InRegLEA, true, -1);
1314 break;
1315 case X86::ADD8ri:
1316 case X86::ADD8ri_DB:
1317 case X86::ADD16ri:
1318 case X86::ADD16ri8:
1319 case X86::ADD16ri_DB:
1320 case X86::ADD16ri8_DB:
1321 addRegOffset(MIB, InRegLEA, true, MI.getOperand(2).getImm());
1322 break;
1323 case X86::ADD8rr:
1324 case X86::ADD8rr_DB:
1325 case X86::ADD16rr:
1326 case X86::ADD16rr_DB: {
1327 Register Src2 = MI.getOperand(2).getReg();
1328 bool IsKill2 = MI.getOperand(2).isKill();
1329 assert(!MI.getOperand(2).isUndef() && "Undef op doesn't need optimization")(static_cast <bool> (!MI.getOperand(2).isUndef() &&
"Undef op doesn't need optimization") ? void (0) : __assert_fail
("!MI.getOperand(2).isUndef() && \"Undef op doesn't need optimization\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 1329, __extension__ __PRETTY_FUNCTION__))
;
1330 unsigned InRegLEA2 = 0;
1331 MachineInstr *InsMI2 = nullptr;
1332 if (Src == Src2) {
1333 // ADD8rr/ADD16rr killed %reg1028, %reg1028
1334 // just a single insert_subreg.
1335 addRegReg(MIB, InRegLEA, true, InRegLEA, false);
1336 } else {
1337 if (Subtarget.is64Bit())
1338 InRegLEA2 = RegInfo.createVirtualRegister(&X86::GR64_NOSPRegClass);
1339 else
1340 InRegLEA2 = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
1341 // Build and insert into an implicit UNDEF value. This is OK because
1342 // we will be shifting and then extracting the lower 8/16-bits.
1343 BuildMI(MBB, &*MIB, MI.getDebugLoc(), get(X86::IMPLICIT_DEF), InRegLEA2);
1344 InsMI2 = BuildMI(MBB, &*MIB, MI.getDebugLoc(), get(TargetOpcode::COPY))
1345 .addReg(InRegLEA2, RegState::Define, SubReg)
1346 .addReg(Src2, getKillRegState(IsKill2));
1347 addRegReg(MIB, InRegLEA, true, InRegLEA2, true);
1348 }
1349 if (LV && IsKill2 && InsMI2)
1350 LV->replaceKillInstruction(Src2, MI, *InsMI2);
1351 break;
1352 }
1353 }
1354
1355 MachineInstr *NewMI = MIB;
1356 MachineInstr *ExtMI =
1357 BuildMI(MBB, MBBI, MI.getDebugLoc(), get(TargetOpcode::COPY))
1358 .addReg(Dest, RegState::Define | getDeadRegState(IsDead))
1359 .addReg(OutRegLEA, RegState::Kill, SubReg);
1360
1361 if (LV) {
1362 // Update live variables.
1363 LV->getVarInfo(InRegLEA).Kills.push_back(NewMI);
1364 LV->getVarInfo(OutRegLEA).Kills.push_back(ExtMI);
1365 if (IsKill)
1366 LV->replaceKillInstruction(Src, MI, *InsMI);
1367 if (IsDead)
1368 LV->replaceKillInstruction(Dest, MI, *ExtMI);
1369 }
1370
1371 return ExtMI;
1372}
1373
1374/// This method must be implemented by targets that
1375/// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
1376/// may be able to convert a two-address instruction into a true
1377/// three-address instruction on demand. This allows the X86 target (for
1378/// example) to convert ADD and SHL instructions into LEA instructions if they
1379/// would require register copies due to two-addressness.
1380///
1381/// This method returns a null pointer if the transformation cannot be
1382/// performed, otherwise it returns the new instruction.
1383///
1384MachineInstr *X86InstrInfo::convertToThreeAddress(MachineInstr &MI,
1385 LiveVariables *LV) const {
1386 // The following opcodes also sets the condition code register(s). Only
1387 // convert them to equivalent lea if the condition code register def's
1388 // are dead!
1389 if (hasLiveCondCodeDef(MI))
1390 return nullptr;
1391
1392 MachineFunction &MF = *MI.getParent()->getParent();
1393 // All instructions input are two-addr instructions. Get the known operands.
1394 const MachineOperand &Dest = MI.getOperand(0);
1395 const MachineOperand &Src = MI.getOperand(1);
1396
1397 // Ideally, operations with undef should be folded before we get here, but we
1398 // can't guarantee it. Bail out because optimizing undefs is a waste of time.
1399 // Without this, we have to forward undef state to new register operands to
1400 // avoid machine verifier errors.
1401 if (Src.isUndef())
1402 return nullptr;
1403 if (MI.getNumOperands() > 2)
1404 if (MI.getOperand(2).isReg() && MI.getOperand(2).isUndef())
1405 return nullptr;
1406
1407 MachineInstr *NewMI = nullptr;
1408 bool Is64Bit = Subtarget.is64Bit();
1409
1410 bool Is8BitOp = false;
1411 unsigned MIOpc = MI.getOpcode();
1412 switch (MIOpc) {
1413 default: llvm_unreachable("Unreachable!")::llvm::llvm_unreachable_internal("Unreachable!", "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 1413)
;
1414 case X86::SHL64ri: {
1415 assert(MI.getNumOperands() >= 3 && "Unknown shift instruction!")(static_cast <bool> (MI.getNumOperands() >= 3 &&
"Unknown shift instruction!") ? void (0) : __assert_fail ("MI.getNumOperands() >= 3 && \"Unknown shift instruction!\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 1415, __extension__ __PRETTY_FUNCTION__))
;
1416 unsigned ShAmt = getTruncatedShiftCount(MI, 2);
1417 if (!isTruncatedShiftCountForLEA(ShAmt)) return nullptr;
1418
1419 // LEA can't handle RSP.
1420 if (Src.getReg().isVirtual() && !MF.getRegInfo().constrainRegClass(
1421 Src.getReg(), &X86::GR64_NOSPRegClass))
1422 return nullptr;
1423
1424 NewMI = BuildMI(MF, MI.getDebugLoc(), get(X86::LEA64r))
1425 .add(Dest)
1426 .addReg(0)
1427 .addImm(1ULL << ShAmt)
1428 .add(Src)
1429 .addImm(0)
1430 .addReg(0);
1431 break;
1432 }
1433 case X86::SHL32ri: {
1434 assert(MI.getNumOperands() >= 3 && "Unknown shift instruction!")(static_cast <bool> (MI.getNumOperands() >= 3 &&
"Unknown shift instruction!") ? void (0) : __assert_fail ("MI.getNumOperands() >= 3 && \"Unknown shift instruction!\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 1434, __extension__ __PRETTY_FUNCTION__))
;
1435 unsigned ShAmt = getTruncatedShiftCount(MI, 2);
1436 if (!isTruncatedShiftCountForLEA(ShAmt)) return nullptr;
1437
1438 unsigned Opc = Is64Bit ? X86::LEA64_32r : X86::LEA32r;
1439
1440 // LEA can't handle ESP.
1441 bool isKill;
1442 Register SrcReg;
1443 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
1444 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false,
1445 SrcReg, isKill, ImplicitOp, LV))
1446 return nullptr;
1447
1448 MachineInstrBuilder MIB =
1449 BuildMI(MF, MI.getDebugLoc(), get(Opc))
1450 .add(Dest)
1451 .addReg(0)
1452 .addImm(1ULL << ShAmt)
1453 .addReg(SrcReg, getKillRegState(isKill))
1454 .addImm(0)
1455 .addReg(0);
1456 if (ImplicitOp.getReg() != 0)
1457 MIB.add(ImplicitOp);
1458 NewMI = MIB;
1459
1460 break;
1461 }
1462 case X86::SHL8ri:
1463 Is8BitOp = true;
1464 LLVM_FALLTHROUGH[[gnu::fallthrough]];
1465 case X86::SHL16ri: {
1466 assert(MI.getNumOperands() >= 3 && "Unknown shift instruction!")(static_cast <bool> (MI.getNumOperands() >= 3 &&
"Unknown shift instruction!") ? void (0) : __assert_fail ("MI.getNumOperands() >= 3 && \"Unknown shift instruction!\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 1466, __extension__ __PRETTY_FUNCTION__))
;
1467 unsigned ShAmt = getTruncatedShiftCount(MI, 2);
1468 if (!isTruncatedShiftCountForLEA(ShAmt))
1469 return nullptr;
1470 return convertToThreeAddressWithLEA(MIOpc, MI, LV, Is8BitOp);
1471 }
1472 case X86::INC64r:
1473 case X86::INC32r: {
1474 assert(MI.getNumOperands() >= 2 && "Unknown inc instruction!")(static_cast <bool> (MI.getNumOperands() >= 2 &&
"Unknown inc instruction!") ? void (0) : __assert_fail ("MI.getNumOperands() >= 2 && \"Unknown inc instruction!\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 1474, __extension__ __PRETTY_FUNCTION__))
;
1475 unsigned Opc = MIOpc == X86::INC64r ? X86::LEA64r :
1476 (Is64Bit ? X86::LEA64_32r : X86::LEA32r);
1477 bool isKill;
1478 Register SrcReg;
1479 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
1480 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false, SrcReg, isKill,
1481 ImplicitOp, LV))
1482 return nullptr;
1483
1484 MachineInstrBuilder MIB =
1485 BuildMI(MF, MI.getDebugLoc(), get(Opc))
1486 .add(Dest)
1487 .addReg(SrcReg, getKillRegState(isKill));
1488 if (ImplicitOp.getReg() != 0)
1489 MIB.add(ImplicitOp);
1490
1491 NewMI = addOffset(MIB, 1);
1492 break;
1493 }
1494 case X86::DEC64r:
1495 case X86::DEC32r: {
1496 assert(MI.getNumOperands() >= 2 && "Unknown dec instruction!")(static_cast <bool> (MI.getNumOperands() >= 2 &&
"Unknown dec instruction!") ? void (0) : __assert_fail ("MI.getNumOperands() >= 2 && \"Unknown dec instruction!\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 1496, __extension__ __PRETTY_FUNCTION__))
;
1497 unsigned Opc = MIOpc == X86::DEC64r ? X86::LEA64r
1498 : (Is64Bit ? X86::LEA64_32r : X86::LEA32r);
1499
1500 bool isKill;
1501 Register SrcReg;
1502 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
1503 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false, SrcReg, isKill,
1504 ImplicitOp, LV))
1505 return nullptr;
1506
1507 MachineInstrBuilder MIB = BuildMI(MF, MI.getDebugLoc(), get(Opc))
1508 .add(Dest)
1509 .addReg(SrcReg, getKillRegState(isKill));
1510 if (ImplicitOp.getReg() != 0)
1511 MIB.add(ImplicitOp);
1512
1513 NewMI = addOffset(MIB, -1);
1514
1515 break;
1516 }
1517 case X86::DEC8r:
1518 case X86::INC8r:
1519 Is8BitOp = true;
1520 LLVM_FALLTHROUGH[[gnu::fallthrough]];
1521 case X86::DEC16r:
1522 case X86::INC16r:
1523 return convertToThreeAddressWithLEA(MIOpc, MI, LV, Is8BitOp);
1524 case X86::ADD64rr:
1525 case X86::ADD64rr_DB:
1526 case X86::ADD32rr:
1527 case X86::ADD32rr_DB: {
1528 assert(MI.getNumOperands() >= 3 && "Unknown add instruction!")(static_cast <bool> (MI.getNumOperands() >= 3 &&
"Unknown add instruction!") ? void (0) : __assert_fail ("MI.getNumOperands() >= 3 && \"Unknown add instruction!\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 1528, __extension__ __PRETTY_FUNCTION__))
;
1529 unsigned Opc;
1530 if (MIOpc == X86::ADD64rr || MIOpc == X86::ADD64rr_DB)
1531 Opc = X86::LEA64r;
1532 else
1533 Opc = Is64Bit ? X86::LEA64_32r : X86::LEA32r;
1534
1535 bool isKill;
1536 Register SrcReg;
1537 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
1538 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ true,
1539 SrcReg, isKill, ImplicitOp, LV))
1540 return nullptr;
1541
1542 const MachineOperand &Src2 = MI.getOperand(2);
1543 bool isKill2;
1544 Register SrcReg2;
1545 MachineOperand ImplicitOp2 = MachineOperand::CreateReg(0, false);
1546 if (!classifyLEAReg(MI, Src2, Opc, /*AllowSP=*/ false,
1547 SrcReg2, isKill2, ImplicitOp2, LV))
1548 return nullptr;
1549
1550 MachineInstrBuilder MIB = BuildMI(MF, MI.getDebugLoc(), get(Opc)).add(Dest);
1551 if (ImplicitOp.getReg() != 0)
1552 MIB.add(ImplicitOp);
1553 if (ImplicitOp2.getReg() != 0)
1554 MIB.add(ImplicitOp2);
1555
1556 NewMI = addRegReg(MIB, SrcReg, isKill, SrcReg2, isKill2);
1557 if (LV && Src2.isKill())
1558 LV->replaceKillInstruction(SrcReg2, MI, *NewMI);
1559 break;
1560 }
1561 case X86::ADD8rr:
1562 case X86::ADD8rr_DB:
1563 Is8BitOp = true;
1564 LLVM_FALLTHROUGH[[gnu::fallthrough]];
1565 case X86::ADD16rr:
1566 case X86::ADD16rr_DB:
1567 return convertToThreeAddressWithLEA(MIOpc, MI, LV, Is8BitOp);
1568 case X86::ADD64ri32:
1569 case X86::ADD64ri8:
1570 case X86::ADD64ri32_DB:
1571 case X86::ADD64ri8_DB:
1572 assert(MI.getNumOperands() >= 3 && "Unknown add instruction!")(static_cast <bool> (MI.getNumOperands() >= 3 &&
"Unknown add instruction!") ? void (0) : __assert_fail ("MI.getNumOperands() >= 3 && \"Unknown add instruction!\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 1572, __extension__ __PRETTY_FUNCTION__))
;
1573 NewMI = addOffset(
1574 BuildMI(MF, MI.getDebugLoc(), get(X86::LEA64r)).add(Dest).add(Src),
1575 MI.getOperand(2));
1576 break;
1577 case X86::ADD32ri:
1578 case X86::ADD32ri8:
1579 case X86::ADD32ri_DB:
1580 case X86::ADD32ri8_DB: {
1581 assert(MI.getNumOperands() >= 3 && "Unknown add instruction!")(static_cast <bool> (MI.getNumOperands() >= 3 &&
"Unknown add instruction!") ? void (0) : __assert_fail ("MI.getNumOperands() >= 3 && \"Unknown add instruction!\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 1581, __extension__ __PRETTY_FUNCTION__))
;
1582 unsigned Opc = Is64Bit ? X86::LEA64_32r : X86::LEA32r;
1583
1584 bool isKill;
1585 Register SrcReg;
1586 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
1587 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ true,
1588 SrcReg, isKill, ImplicitOp, LV))
1589 return nullptr;
1590
1591 MachineInstrBuilder MIB = BuildMI(MF, MI.getDebugLoc(), get(Opc))
1592 .add(Dest)
1593 .addReg(SrcReg, getKillRegState(isKill));
1594 if (ImplicitOp.getReg() != 0)
1595 MIB.add(ImplicitOp);
1596
1597 NewMI = addOffset(MIB, MI.getOperand(2));
1598 break;
1599 }
1600 case X86::ADD8ri:
1601 case X86::ADD8ri_DB:
1602 Is8BitOp = true;
1603 LLVM_FALLTHROUGH[[gnu::fallthrough]];
1604 case X86::ADD16ri:
1605 case X86::ADD16ri8:
1606 case X86::ADD16ri_DB:
1607 case X86::ADD16ri8_DB:
1608 return convertToThreeAddressWithLEA(MIOpc, MI, LV, Is8BitOp);
1609 case X86::SUB8ri:
1610 case X86::SUB16ri8:
1611 case X86::SUB16ri:
1612 /// FIXME: Support these similar to ADD8ri/ADD16ri*.
1613 return nullptr;
1614 case X86::SUB32ri8:
1615 case X86::SUB32ri: {
1616 if (!MI.getOperand(2).isImm())
1617 return nullptr;
1618 int64_t Imm = MI.getOperand(2).getImm();
1619 if (!isInt<32>(-Imm))
1620 return nullptr;
1621
1622 assert(MI.getNumOperands() >= 3 && "Unknown add instruction!")(static_cast <bool> (MI.getNumOperands() >= 3 &&
"Unknown add instruction!") ? void (0) : __assert_fail ("MI.getNumOperands() >= 3 && \"Unknown add instruction!\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 1622, __extension__ __PRETTY_FUNCTION__))
;
1623 unsigned Opc = Is64Bit ? X86::LEA64_32r : X86::LEA32r;
1624
1625 bool isKill;
1626 Register SrcReg;
1627 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
1628 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ true,
1629 SrcReg, isKill, ImplicitOp, LV))
1630 return nullptr;
1631
1632 MachineInstrBuilder MIB = BuildMI(MF, MI.getDebugLoc(), get(Opc))
1633 .add(Dest)
1634 .addReg(SrcReg, getKillRegState(isKill));
1635 if (ImplicitOp.getReg() != 0)
1636 MIB.add(ImplicitOp);
1637
1638 NewMI = addOffset(MIB, -Imm);
1639 break;
1640 }
1641
1642 case X86::SUB64ri8:
1643 case X86::SUB64ri32: {
1644 if (!MI.getOperand(2).isImm())
1645 return nullptr;
1646 int64_t Imm = MI.getOperand(2).getImm();
1647 if (!isInt<32>(-Imm))
1648 return nullptr;
1649
1650 assert(MI.getNumOperands() >= 3 && "Unknown sub instruction!")(static_cast <bool> (MI.getNumOperands() >= 3 &&
"Unknown sub instruction!") ? void (0) : __assert_fail ("MI.getNumOperands() >= 3 && \"Unknown sub instruction!\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 1650, __extension__ __PRETTY_FUNCTION__))
;
1651
1652 MachineInstrBuilder MIB = BuildMI(MF, MI.getDebugLoc(),
1653 get(X86::LEA64r)).add(Dest).add(Src);
1654 NewMI = addOffset(MIB, -Imm);
1655 break;
1656 }
1657
1658 case X86::VMOVDQU8Z128rmk:
1659 case X86::VMOVDQU8Z256rmk:
1660 case X86::VMOVDQU8Zrmk:
1661 case X86::VMOVDQU16Z128rmk:
1662 case X86::VMOVDQU16Z256rmk:
1663 case X86::VMOVDQU16Zrmk:
1664 case X86::VMOVDQU32Z128rmk: case X86::VMOVDQA32Z128rmk:
1665 case X86::VMOVDQU32Z256rmk: case X86::VMOVDQA32Z256rmk:
1666 case X86::VMOVDQU32Zrmk: case X86::VMOVDQA32Zrmk:
1667 case X86::VMOVDQU64Z128rmk: case X86::VMOVDQA64Z128rmk:
1668 case X86::VMOVDQU64Z256rmk: case X86::VMOVDQA64Z256rmk:
1669 case X86::VMOVDQU64Zrmk: case X86::VMOVDQA64Zrmk:
1670 case X86::VMOVUPDZ128rmk: case X86::VMOVAPDZ128rmk:
1671 case X86::VMOVUPDZ256rmk: case X86::VMOVAPDZ256rmk:
1672 case X86::VMOVUPDZrmk: case X86::VMOVAPDZrmk:
1673 case X86::VMOVUPSZ128rmk: case X86::VMOVAPSZ128rmk:
1674 case X86::VMOVUPSZ256rmk: case X86::VMOVAPSZ256rmk:
1675 case X86::VMOVUPSZrmk: case X86::VMOVAPSZrmk:
1676 case X86::VBROADCASTSDZ256rmk:
1677 case X86::VBROADCASTSDZrmk:
1678 case X86::VBROADCASTSSZ128rmk:
1679 case X86::VBROADCASTSSZ256rmk:
1680 case X86::VBROADCASTSSZrmk:
1681 case X86::VPBROADCASTDZ128rmk:
1682 case X86::VPBROADCASTDZ256rmk:
1683 case X86::VPBROADCASTDZrmk:
1684 case X86::VPBROADCASTQZ128rmk:
1685 case X86::VPBROADCASTQZ256rmk:
1686 case X86::VPBROADCASTQZrmk: {
1687 unsigned Opc;
1688 switch (MIOpc) {
1689 default: llvm_unreachable("Unreachable!")::llvm::llvm_unreachable_internal("Unreachable!", "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 1689)
;
1690 case X86::VMOVDQU8Z128rmk: Opc = X86::VPBLENDMBZ128rmk; break;
1691 case X86::VMOVDQU8Z256rmk: Opc = X86::VPBLENDMBZ256rmk; break;
1692 case X86::VMOVDQU8Zrmk: Opc = X86::VPBLENDMBZrmk; break;
1693 case X86::VMOVDQU16Z128rmk: Opc = X86::VPBLENDMWZ128rmk; break;
1694 case X86::VMOVDQU16Z256rmk: Opc = X86::VPBLENDMWZ256rmk; break;
1695 case X86::VMOVDQU16Zrmk: Opc = X86::VPBLENDMWZrmk; break;
1696 case X86::VMOVDQU32Z128rmk: Opc = X86::VPBLENDMDZ128rmk; break;
1697 case X86::VMOVDQU32Z256rmk: Opc = X86::VPBLENDMDZ256rmk; break;
1698 case X86::VMOVDQU32Zrmk: Opc = X86::VPBLENDMDZrmk; break;
1699 case X86::VMOVDQU64Z128rmk: Opc = X86::VPBLENDMQZ128rmk; break;
1700 case X86::VMOVDQU64Z256rmk: Opc = X86::VPBLENDMQZ256rmk; break;
1701 case X86::VMOVDQU64Zrmk: Opc = X86::VPBLENDMQZrmk; break;
1702 case X86::VMOVUPDZ128rmk: Opc = X86::VBLENDMPDZ128rmk; break;
1703 case X86::VMOVUPDZ256rmk: Opc = X86::VBLENDMPDZ256rmk; break;
1704 case X86::VMOVUPDZrmk: Opc = X86::VBLENDMPDZrmk; break;
1705 case X86::VMOVUPSZ128rmk: Opc = X86::VBLENDMPSZ128rmk; break;
1706 case X86::VMOVUPSZ256rmk: Opc = X86::VBLENDMPSZ256rmk; break;
1707 case X86::VMOVUPSZrmk: Opc = X86::VBLENDMPSZrmk; break;
1708 case X86::VMOVDQA32Z128rmk: Opc = X86::VPBLENDMDZ128rmk; break;
1709 case X86::VMOVDQA32Z256rmk: Opc = X86::VPBLENDMDZ256rmk; break;
1710 case X86::VMOVDQA32Zrmk: Opc = X86::VPBLENDMDZrmk; break;
1711 case X86::VMOVDQA64Z128rmk: Opc = X86::VPBLENDMQZ128rmk; break;
1712 case X86::VMOVDQA64Z256rmk: Opc = X86::VPBLENDMQZ256rmk; break;
1713 case X86::VMOVDQA64Zrmk: Opc = X86::VPBLENDMQZrmk; break;
1714 case X86::VMOVAPDZ128rmk: Opc = X86::VBLENDMPDZ128rmk; break;
1715 case X86::VMOVAPDZ256rmk: Opc = X86::VBLENDMPDZ256rmk; break;
1716 case X86::VMOVAPDZrmk: Opc = X86::VBLENDMPDZrmk; break;
1717 case X86::VMOVAPSZ128rmk: Opc = X86::VBLENDMPSZ128rmk; break;
1718 case X86::VMOVAPSZ256rmk: Opc = X86::VBLENDMPSZ256rmk; break;
1719 case X86::VMOVAPSZrmk: Opc = X86::VBLENDMPSZrmk; break;
1720 case X86::VBROADCASTSDZ256rmk: Opc = X86::VBLENDMPDZ256rmbk; break;
1721 case X86::VBROADCASTSDZrmk: Opc = X86::VBLENDMPDZrmbk; break;
1722 case X86::VBROADCASTSSZ128rmk: Opc = X86::VBLENDMPSZ128rmbk; break;
1723 case X86::VBROADCASTSSZ256rmk: Opc = X86::VBLENDMPSZ256rmbk; break;
1724 case X86::VBROADCASTSSZrmk: Opc = X86::VBLENDMPSZrmbk; break;
1725 case X86::VPBROADCASTDZ128rmk: Opc = X86::VPBLENDMDZ128rmbk; break;
1726 case X86::VPBROADCASTDZ256rmk: Opc = X86::VPBLENDMDZ256rmbk; break;
1727 case X86::VPBROADCASTDZrmk: Opc = X86::VPBLENDMDZrmbk; break;
1728 case X86::VPBROADCASTQZ128rmk: Opc = X86::VPBLENDMQZ128rmbk; break;
1729 case X86::VPBROADCASTQZ256rmk: Opc = X86::VPBLENDMQZ256rmbk; break;
1730 case X86::VPBROADCASTQZrmk: Opc = X86::VPBLENDMQZrmbk; break;
1731 }
1732
1733 NewMI = BuildMI(MF, MI.getDebugLoc(), get(Opc))
1734 .add(Dest)
1735 .add(MI.getOperand(2))
1736 .add(Src)
1737 .add(MI.getOperand(3))
1738 .add(MI.getOperand(4))
1739 .add(MI.getOperand(5))
1740 .add(MI.getOperand(6))
1741 .add(MI.getOperand(7));
1742 break;
1743 }
1744
1745 case X86::VMOVDQU8Z128rrk:
1746 case X86::VMOVDQU8Z256rrk:
1747 case X86::VMOVDQU8Zrrk:
1748 case X86::VMOVDQU16Z128rrk:
1749 case X86::VMOVDQU16Z256rrk:
1750 case X86::VMOVDQU16Zrrk:
1751 case X86::VMOVDQU32Z128rrk: case X86::VMOVDQA32Z128rrk:
1752 case X86::VMOVDQU32Z256rrk: case X86::VMOVDQA32Z256rrk:
1753 case X86::VMOVDQU32Zrrk: case X86::VMOVDQA32Zrrk:
1754 case X86::VMOVDQU64Z128rrk: case X86::VMOVDQA64Z128rrk:
1755 case X86::VMOVDQU64Z256rrk: case X86::VMOVDQA64Z256rrk:
1756 case X86::VMOVDQU64Zrrk: case X86::VMOVDQA64Zrrk:
1757 case X86::VMOVUPDZ128rrk: case X86::VMOVAPDZ128rrk:
1758 case X86::VMOVUPDZ256rrk: case X86::VMOVAPDZ256rrk:
1759 case X86::VMOVUPDZrrk: case X86::VMOVAPDZrrk:
1760 case X86::VMOVUPSZ128rrk: case X86::VMOVAPSZ128rrk:
1761 case X86::VMOVUPSZ256rrk: case X86::VMOVAPSZ256rrk:
1762 case X86::VMOVUPSZrrk: case X86::VMOVAPSZrrk: {
1763 unsigned Opc;
1764 switch (MIOpc) {
1765 default: llvm_unreachable("Unreachable!")::llvm::llvm_unreachable_internal("Unreachable!", "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 1765)
;
1766 case X86::VMOVDQU8Z128rrk: Opc = X86::VPBLENDMBZ128rrk; break;
1767 case X86::VMOVDQU8Z256rrk: Opc = X86::VPBLENDMBZ256rrk; break;
1768 case X86::VMOVDQU8Zrrk: Opc = X86::VPBLENDMBZrrk; break;
1769 case X86::VMOVDQU16Z128rrk: Opc = X86::VPBLENDMWZ128rrk; break;
1770 case X86::VMOVDQU16Z256rrk: Opc = X86::VPBLENDMWZ256rrk; break;
1771 case X86::VMOVDQU16Zrrk: Opc = X86::VPBLENDMWZrrk; break;
1772 case X86::VMOVDQU32Z128rrk: Opc = X86::VPBLENDMDZ128rrk; break;
1773 case X86::VMOVDQU32Z256rrk: Opc = X86::VPBLENDMDZ256rrk; break;
1774 case X86::VMOVDQU32Zrrk: Opc = X86::VPBLENDMDZrrk; break;
1775 case X86::VMOVDQU64Z128rrk: Opc = X86::VPBLENDMQZ128rrk; break;
1776 case X86::VMOVDQU64Z256rrk: Opc = X86::VPBLENDMQZ256rrk; break;
1777 case X86::VMOVDQU64Zrrk: Opc = X86::VPBLENDMQZrrk; break;
1778 case X86::VMOVUPDZ128rrk: Opc = X86::VBLENDMPDZ128rrk; break;
1779 case X86::VMOVUPDZ256rrk: Opc = X86::VBLENDMPDZ256rrk; break;
1780 case X86::VMOVUPDZrrk: Opc = X86::VBLENDMPDZrrk; break;
1781 case X86::VMOVUPSZ128rrk: Opc = X86::VBLENDMPSZ128rrk; break;
1782 case X86::VMOVUPSZ256rrk: Opc = X86::VBLENDMPSZ256rrk; break;
1783 case X86::VMOVUPSZrrk: Opc = X86::VBLENDMPSZrrk; break;
1784 case X86::VMOVDQA32Z128rrk: Opc = X86::VPBLENDMDZ128rrk; break;
1785 case X86::VMOVDQA32Z256rrk: Opc = X86::VPBLENDMDZ256rrk; break;
1786 case X86::VMOVDQA32Zrrk: Opc = X86::VPBLENDMDZrrk; break;
1787 case X86::VMOVDQA64Z128rrk: Opc = X86::VPBLENDMQZ128rrk; break;
1788 case X86::VMOVDQA64Z256rrk: Opc = X86::VPBLENDMQZ256rrk; break;
1789 case X86::VMOVDQA64Zrrk: Opc = X86::VPBLENDMQZrrk; break;
1790 case X86::VMOVAPDZ128rrk: Opc = X86::VBLENDMPDZ128rrk; break;
1791 case X86::VMOVAPDZ256rrk: Opc = X86::VBLENDMPDZ256rrk; break;
1792 case X86::VMOVAPDZrrk: Opc = X86::VBLENDMPDZrrk; break;
1793 case X86::VMOVAPSZ128rrk: Opc = X86::VBLENDMPSZ128rrk; break;
1794 case X86::VMOVAPSZ256rrk: Opc = X86::VBLENDMPSZ256rrk; break;
1795 case X86::VMOVAPSZrrk: Opc = X86::VBLENDMPSZrrk; break;
1796 }
1797
1798 NewMI = BuildMI(MF, MI.getDebugLoc(), get(Opc))
1799 .add(Dest)
1800 .add(MI.getOperand(2))
1801 .add(Src)
1802 .add(MI.getOperand(3));
1803 break;
1804 }
1805 }
1806
1807 if (!NewMI) return nullptr;
1808
1809 if (LV) { // Update live variables
1810 if (Src.isKill())
1811 LV->replaceKillInstruction(Src.getReg(), MI, *NewMI);
1812 if (Dest.isDead())
1813 LV->replaceKillInstruction(Dest.getReg(), MI, *NewMI);
1814 }
1815
1816 MachineBasicBlock &MBB = *MI.getParent();
1817 MBB.insert(MI.getIterator(), NewMI); // Insert the new inst
1818 return NewMI;
1819}
1820
1821/// This determines which of three possible cases of a three source commute
1822/// the source indexes correspond to taking into account any mask operands.
1823/// All prevents commuting a passthru operand. Returns -1 if the commute isn't
1824/// possible.
1825/// Case 0 - Possible to commute the first and second operands.
1826/// Case 1 - Possible to commute the first and third operands.
1827/// Case 2 - Possible to commute the second and third operands.
1828static unsigned getThreeSrcCommuteCase(uint64_t TSFlags, unsigned SrcOpIdx1,
1829 unsigned SrcOpIdx2) {
1830 // Put the lowest index to SrcOpIdx1 to simplify the checks below.
1831 if (SrcOpIdx1 > SrcOpIdx2)
1832 std::swap(SrcOpIdx1, SrcOpIdx2);
1833
1834 unsigned Op1 = 1, Op2 = 2, Op3 = 3;
1835 if (X86II::isKMasked(TSFlags)) {
1836 Op2++;
1837 Op3++;
1838 }
1839
1840 if (SrcOpIdx1 == Op1 && SrcOpIdx2 == Op2)
1841 return 0;
1842 if (SrcOpIdx1 == Op1 && SrcOpIdx2 == Op3)
1843 return 1;
1844 if (SrcOpIdx1 == Op2 && SrcOpIdx2 == Op3)
1845 return 2;
1846 llvm_unreachable("Unknown three src commute case.")::llvm::llvm_unreachable_internal("Unknown three src commute case."
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 1846)
;
1847}
1848
1849unsigned X86InstrInfo::getFMA3OpcodeToCommuteOperands(
1850 const MachineInstr &MI, unsigned SrcOpIdx1, unsigned SrcOpIdx2,
1851 const X86InstrFMA3Group &FMA3Group) const {
1852
1853 unsigned Opc = MI.getOpcode();
1854
1855 // TODO: Commuting the 1st operand of FMA*_Int requires some additional
1856 // analysis. The commute optimization is legal only if all users of FMA*_Int
1857 // use only the lowest element of the FMA*_Int instruction. Such analysis are
1858 // not implemented yet. So, just return 0 in that case.
1859 // When such analysis are available this place will be the right place for
1860 // calling it.
1861 assert(!(FMA3Group.isIntrinsic() && (SrcOpIdx1 == 1 || SrcOpIdx2 == 1)) &&(static_cast <bool> (!(FMA3Group.isIntrinsic() &&
(SrcOpIdx1 == 1 || SrcOpIdx2 == 1)) && "Intrinsic instructions can't commute operand 1"
) ? void (0) : __assert_fail ("!(FMA3Group.isIntrinsic() && (SrcOpIdx1 == 1 || SrcOpIdx2 == 1)) && \"Intrinsic instructions can't commute operand 1\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 1862, __extension__ __PRETTY_FUNCTION__))
1862 "Intrinsic instructions can't commute operand 1")(static_cast <bool> (!(FMA3Group.isIntrinsic() &&
(SrcOpIdx1 == 1 || SrcOpIdx2 == 1)) && "Intrinsic instructions can't commute operand 1"
) ? void (0) : __assert_fail ("!(FMA3Group.isIntrinsic() && (SrcOpIdx1 == 1 || SrcOpIdx2 == 1)) && \"Intrinsic instructions can't commute operand 1\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 1862, __extension__ __PRETTY_FUNCTION__))
;
1863
1864 // Determine which case this commute is or if it can't be done.
1865 unsigned Case = getThreeSrcCommuteCase(MI.getDesc().TSFlags, SrcOpIdx1,
1866 SrcOpIdx2);
1867 assert(Case < 3 && "Unexpected case number!")(static_cast <bool> (Case < 3 && "Unexpected case number!"
) ? void (0) : __assert_fail ("Case < 3 && \"Unexpected case number!\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 1867, __extension__ __PRETTY_FUNCTION__))
;
1868
1869 // Define the FMA forms mapping array that helps to map input FMA form
1870 // to output FMA form to preserve the operation semantics after
1871 // commuting the operands.
1872 const unsigned Form132Index = 0;
1873 const unsigned Form213Index = 1;
1874 const unsigned Form231Index = 2;
1875 static const unsigned FormMapping[][3] = {
1876 // 0: SrcOpIdx1 == 1 && SrcOpIdx2 == 2;
1877 // FMA132 A, C, b; ==> FMA231 C, A, b;
1878 // FMA213 B, A, c; ==> FMA213 A, B, c;
1879 // FMA231 C, A, b; ==> FMA132 A, C, b;
1880 { Form231Index, Form213Index, Form132Index },
1881 // 1: SrcOpIdx1 == 1 && SrcOpIdx2 == 3;
1882 // FMA132 A, c, B; ==> FMA132 B, c, A;
1883 // FMA213 B, a, C; ==> FMA231 C, a, B;
1884 // FMA231 C, a, B; ==> FMA213 B, a, C;
1885 { Form132Index, Form231Index, Form213Index },
1886 // 2: SrcOpIdx1 == 2 && SrcOpIdx2 == 3;
1887 // FMA132 a, C, B; ==> FMA213 a, B, C;
1888 // FMA213 b, A, C; ==> FMA132 b, C, A;
1889 // FMA231 c, A, B; ==> FMA231 c, B, A;
1890 { Form213Index, Form132Index, Form231Index }
1891 };
1892
1893 unsigned FMAForms[3];
1894 FMAForms[0] = FMA3Group.get132Opcode();
1895 FMAForms[1] = FMA3Group.get213Opcode();
1896 FMAForms[2] = FMA3Group.get231Opcode();
1897 unsigned FormIndex;
1898 for (FormIndex = 0; FormIndex < 3; FormIndex++)
1899 if (Opc == FMAForms[FormIndex])
1900 break;
1901
1902 // Everything is ready, just adjust the FMA opcode and return it.
1903 FormIndex = FormMapping[Case][FormIndex];
1904 return FMAForms[FormIndex];
1905}
1906
1907static void commuteVPTERNLOG(MachineInstr &MI, unsigned SrcOpIdx1,
1908 unsigned SrcOpIdx2) {
1909 // Determine which case this commute is or if it can't be done.
1910 unsigned Case = getThreeSrcCommuteCase(MI.getDesc().TSFlags, SrcOpIdx1,
1911 SrcOpIdx2);
1912 assert(Case < 3 && "Unexpected case value!")(static_cast <bool> (Case < 3 && "Unexpected case value!"
) ? void (0) : __assert_fail ("Case < 3 && \"Unexpected case value!\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 1912, __extension__ __PRETTY_FUNCTION__))
;
1913
1914 // For each case we need to swap two pairs of bits in the final immediate.
1915 static const uint8_t SwapMasks[3][4] = {
1916 { 0x04, 0x10, 0x08, 0x20 }, // Swap bits 2/4 and 3/5.
1917 { 0x02, 0x10, 0x08, 0x40 }, // Swap bits 1/4 and 3/6.
1918 { 0x02, 0x04, 0x20, 0x40 }, // Swap bits 1/2 and 5/6.
1919 };
1920
1921 uint8_t Imm = MI.getOperand(MI.getNumOperands()-1).getImm();
1922 // Clear out the bits we are swapping.
1923 uint8_t NewImm = Imm & ~(SwapMasks[Case][0] | SwapMasks[Case][1] |
1924 SwapMasks[Case][2] | SwapMasks[Case][3]);
1925 // If the immediate had a bit of the pair set, then set the opposite bit.
1926 if (Imm & SwapMasks[Case][0]) NewImm |= SwapMasks[Case][1];
1927 if (Imm & SwapMasks[Case][1]) NewImm |= SwapMasks[Case][0];
1928 if (Imm & SwapMasks[Case][2]) NewImm |= SwapMasks[Case][3];
1929 if (Imm & SwapMasks[Case][3]) NewImm |= SwapMasks[Case][2];
1930 MI.getOperand(MI.getNumOperands()-1).setImm(NewImm);
1931}
1932
1933// Returns true if this is a VPERMI2 or VPERMT2 instruction that can be
1934// commuted.
1935static bool isCommutableVPERMV3Instruction(unsigned Opcode) {
1936#define VPERM_CASES(Suffix) \
1937 case X86::VPERMI2##Suffix##128rr: case X86::VPERMT2##Suffix##128rr: \
1938 case X86::VPERMI2##Suffix##256rr: case X86::VPERMT2##Suffix##256rr: \
1939 case X86::VPERMI2##Suffix##rr: case X86::VPERMT2##Suffix##rr: \
1940 case X86::VPERMI2##Suffix##128rm: case X86::VPERMT2##Suffix##128rm: \
1941 case X86::VPERMI2##Suffix##256rm: case X86::VPERMT2##Suffix##256rm: \
1942 case X86::VPERMI2##Suffix##rm: case X86::VPERMT2##Suffix##rm: \
1943 case X86::VPERMI2##Suffix##128rrkz: case X86::VPERMT2##Suffix##128rrkz: \
1944 case X86::VPERMI2##Suffix##256rrkz: case X86::VPERMT2##Suffix##256rrkz: \
1945 case X86::VPERMI2##Suffix##rrkz: case X86::VPERMT2##Suffix##rrkz: \
1946 case X86::VPERMI2##Suffix##128rmkz: case X86::VPERMT2##Suffix##128rmkz: \
1947 case X86::VPERMI2##Suffix##256rmkz: case X86::VPERMT2##Suffix##256rmkz: \
1948 case X86::VPERMI2##Suffix##rmkz: case X86::VPERMT2##Suffix##rmkz:
1949
1950#define VPERM_CASES_BROADCAST(Suffix) \
1951 VPERM_CASES(Suffix) \
1952 case X86::VPERMI2##Suffix##128rmb: case X86::VPERMT2##Suffix##128rmb: \
1953 case X86::VPERMI2##Suffix##256rmb: case X86::VPERMT2##Suffix##256rmb: \
1954 case X86::VPERMI2##Suffix##rmb: case X86::VPERMT2##Suffix##rmb: \
1955 case X86::VPERMI2##Suffix##128rmbkz: case X86::VPERMT2##Suffix##128rmbkz: \
1956 case X86::VPERMI2##Suffix##256rmbkz: case X86::VPERMT2##Suffix##256rmbkz: \
1957 case X86::VPERMI2##Suffix##rmbkz: case X86::VPERMT2##Suffix##rmbkz:
1958
1959 switch (Opcode) {
1960 default: return false;
1961 VPERM_CASES(B)
1962 VPERM_CASES_BROADCAST(D)
1963 VPERM_CASES_BROADCAST(PD)
1964 VPERM_CASES_BROADCAST(PS)
1965 VPERM_CASES_BROADCAST(Q)
1966 VPERM_CASES(W)
1967 return true;
1968 }
1969#undef VPERM_CASES_BROADCAST
1970#undef VPERM_CASES
1971}
1972
1973// Returns commuted opcode for VPERMI2 and VPERMT2 instructions by switching
1974// from the I opcode to the T opcode and vice versa.
1975static unsigned getCommutedVPERMV3Opcode(unsigned Opcode) {
1976#define VPERM_CASES(Orig, New) \
1977 case X86::Orig##128rr: return X86::New##128rr; \
1978 case X86::Orig##128rrkz: return X86::New##128rrkz; \
1979 case X86::Orig##128rm: return X86::New##128rm; \
1980 case X86::Orig##128rmkz: return X86::New##128rmkz; \
1981 case X86::Orig##256rr: return X86::New##256rr; \
1982 case X86::Orig##256rrkz: return X86::New##256rrkz; \
1983 case X86::Orig##256rm: return X86::New##256rm; \
1984 case X86::Orig##256rmkz: return X86::New##256rmkz; \
1985 case X86::Orig##rr: return X86::New##rr; \
1986 case X86::Orig##rrkz: return X86::New##rrkz; \
1987 case X86::Orig##rm: return X86::New##rm; \
1988 case X86::Orig##rmkz: return X86::New##rmkz;
1989
1990#define VPERM_CASES_BROADCAST(Orig, New) \
1991 VPERM_CASES(Orig, New) \
1992 case X86::Orig##128rmb: return X86::New##128rmb; \
1993 case X86::Orig##128rmbkz: return X86::New##128rmbkz; \
1994 case X86::Orig##256rmb: return X86::New##256rmb; \
1995 case X86::Orig##256rmbkz: return X86::New##256rmbkz; \
1996 case X86::Orig##rmb: return X86::New##rmb; \
1997 case X86::Orig##rmbkz: return X86::New##rmbkz;
1998
1999 switch (Opcode) {
2000 VPERM_CASES(VPERMI2B, VPERMT2B)
2001 VPERM_CASES_BROADCAST(VPERMI2D, VPERMT2D)
2002 VPERM_CASES_BROADCAST(VPERMI2PD, VPERMT2PD)
2003 VPERM_CASES_BROADCAST(VPERMI2PS, VPERMT2PS)
2004 VPERM_CASES_BROADCAST(VPERMI2Q, VPERMT2Q)
2005 VPERM_CASES(VPERMI2W, VPERMT2W)
2006 VPERM_CASES(VPERMT2B, VPERMI2B)
2007 VPERM_CASES_BROADCAST(VPERMT2D, VPERMI2D)
2008 VPERM_CASES_BROADCAST(VPERMT2PD, VPERMI2PD)
2009 VPERM_CASES_BROADCAST(VPERMT2PS, VPERMI2PS)
2010 VPERM_CASES_BROADCAST(VPERMT2Q, VPERMI2Q)
2011 VPERM_CASES(VPERMT2W, VPERMI2W)
2012 }
2013
2014 llvm_unreachable("Unreachable!")::llvm::llvm_unreachable_internal("Unreachable!", "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 2014)
;
2015#undef VPERM_CASES_BROADCAST
2016#undef VPERM_CASES
2017}
2018
2019MachineInstr *X86InstrInfo::commuteInstructionImpl(MachineInstr &MI, bool NewMI,
2020 unsigned OpIdx1,
2021 unsigned OpIdx2) const {
2022 auto cloneIfNew = [NewMI](MachineInstr &MI) -> MachineInstr & {
2023 if (NewMI)
2024 return *MI.getParent()->getParent()->CloneMachineInstr(&MI);
2025 return MI;
2026 };
2027
2028 switch (MI.getOpcode()) {
2029 case X86::SHRD16rri8: // A = SHRD16rri8 B, C, I -> A = SHLD16rri8 C, B, (16-I)
2030 case X86::SHLD16rri8: // A = SHLD16rri8 B, C, I -> A = SHRD16rri8 C, B, (16-I)
2031 case X86::SHRD32rri8: // A = SHRD32rri8 B, C, I -> A = SHLD32rri8 C, B, (32-I)
2032 case X86::SHLD32rri8: // A = SHLD32rri8 B, C, I -> A = SHRD32rri8 C, B, (32-I)
2033 case X86::SHRD64rri8: // A = SHRD64rri8 B, C, I -> A = SHLD64rri8 C, B, (64-I)
2034 case X86::SHLD64rri8:{// A = SHLD64rri8 B, C, I -> A = SHRD64rri8 C, B, (64-I)
2035 unsigned Opc;
2036 unsigned Size;
2037 switch (MI.getOpcode()) {
2038 default: llvm_unreachable("Unreachable!")::llvm::llvm_unreachable_internal("Unreachable!", "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 2038)
;
2039 case X86::SHRD16rri8: Size = 16; Opc = X86::SHLD16rri8; break;
2040 case X86::SHLD16rri8: Size = 16; Opc = X86::SHRD16rri8; break;
2041 case X86::SHRD32rri8: Size = 32; Opc = X86::SHLD32rri8; break;
2042 case X86::SHLD32rri8: Size = 32; Opc = X86::SHRD32rri8; break;
2043 case X86::SHRD64rri8: Size = 64; Opc = X86::SHLD64rri8; break;
2044 case X86::SHLD64rri8: Size = 64; Opc = X86::SHRD64rri8; break;
2045 }
2046 unsigned Amt = MI.getOperand(3).getImm();
2047 auto &WorkingMI = cloneIfNew(MI);
2048 WorkingMI.setDesc(get(Opc));
2049 WorkingMI.getOperand(3).setImm(Size - Amt);
2050 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
2051 OpIdx1, OpIdx2);
2052 }
2053 case X86::PFSUBrr:
2054 case X86::PFSUBRrr: {
2055 // PFSUB x, y: x = x - y
2056 // PFSUBR x, y: x = y - x
2057 unsigned Opc =
2058 (X86::PFSUBRrr == MI.getOpcode() ? X86::PFSUBrr : X86::PFSUBRrr);
2059 auto &WorkingMI = cloneIfNew(MI);
2060 WorkingMI.setDesc(get(Opc));
2061 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
2062 OpIdx1, OpIdx2);
2063 }
2064 case X86::BLENDPDrri:
2065 case X86::BLENDPSrri:
2066 case X86::VBLENDPDrri:
2067 case X86::VBLENDPSrri:
2068 // If we're optimizing for size, try to use MOVSD/MOVSS.
2069 if (MI.getParent()->getParent()->getFunction().hasOptSize()) {
2070 unsigned Mask, Opc;
2071 switch (MI.getOpcode()) {
2072 default: llvm_unreachable("Unreachable!")::llvm::llvm_unreachable_internal("Unreachable!", "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 2072)
;
2073 case X86::BLENDPDrri: Opc = X86::MOVSDrr; Mask = 0x03; break;
2074 case X86::BLENDPSrri: Opc = X86::MOVSSrr; Mask = 0x0F; break;
2075 case X86::VBLENDPDrri: Opc = X86::VMOVSDrr; Mask = 0x03; break;
2076 case X86::VBLENDPSrri: Opc = X86::VMOVSSrr; Mask = 0x0F; break;
2077 }
2078 if ((MI.getOperand(3).getImm() ^ Mask) == 1) {
2079 auto &WorkingMI = cloneIfNew(MI);
2080 WorkingMI.setDesc(get(Opc));
2081 WorkingMI.RemoveOperand(3);
2082 return TargetInstrInfo::commuteInstructionImpl(WorkingMI,
2083 /*NewMI=*/false,
2084 OpIdx1, OpIdx2);
2085 }
2086 }
2087 LLVM_FALLTHROUGH[[gnu::fallthrough]];
2088 case X86::PBLENDWrri:
2089 case X86::VBLENDPDYrri:
2090 case X86::VBLENDPSYrri:
2091 case X86::VPBLENDDrri:
2092 case X86::VPBLENDWrri:
2093 case X86::VPBLENDDYrri:
2094 case X86::VPBLENDWYrri:{
2095 int8_t Mask;
2096 switch (MI.getOpcode()) {
2097 default: llvm_unreachable("Unreachable!")::llvm::llvm_unreachable_internal("Unreachable!", "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 2097)
;
2098 case X86::BLENDPDrri: Mask = (int8_t)0x03; break;
2099 case X86::BLENDPSrri: Mask = (int8_t)0x0F; break;
2100 case X86::PBLENDWrri: Mask = (int8_t)0xFF; break;
2101 case X86::VBLENDPDrri: Mask = (int8_t)0x03; break;
2102 case X86::VBLENDPSrri: Mask = (int8_t)0x0F; break;
2103 case X86::VBLENDPDYrri: Mask = (int8_t)0x0F; break;
2104 case X86::VBLENDPSYrri: Mask = (int8_t)0xFF; break;
2105 case X86::VPBLENDDrri: Mask = (int8_t)0x0F; break;
2106 case X86::VPBLENDWrri: Mask = (int8_t)0xFF; break;
2107 case X86::VPBLENDDYrri: Mask = (int8_t)0xFF; break;
2108 case X86::VPBLENDWYrri: Mask = (int8_t)0xFF; break;
2109 }
2110 // Only the least significant bits of Imm are used.
2111 // Using int8_t to ensure it will be sign extended to the int64_t that
2112 // setImm takes in order to match isel behavior.
2113 int8_t Imm = MI.getOperand(3).getImm() & Mask;
2114 auto &WorkingMI = cloneIfNew(MI);
2115 WorkingMI.getOperand(3).setImm(Mask ^ Imm);
2116 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
2117 OpIdx1, OpIdx2);
2118 }
2119 case X86::INSERTPSrr:
2120 case X86::VINSERTPSrr:
2121 case X86::VINSERTPSZrr: {
2122 unsigned Imm = MI.getOperand(MI.getNumOperands() - 1).getImm();
2123 unsigned ZMask = Imm & 15;
2124 unsigned DstIdx = (Imm >> 4) & 3;
2125 unsigned SrcIdx = (Imm >> 6) & 3;
2126
2127 // We can commute insertps if we zero 2 of the elements, the insertion is
2128 // "inline" and we don't override the insertion with a zero.
2129 if (DstIdx == SrcIdx && (ZMask & (1 << DstIdx)) == 0 &&
2130 countPopulation(ZMask) == 2) {
2131 unsigned AltIdx = findFirstSet((ZMask | (1 << DstIdx)) ^ 15);
2132 assert(AltIdx < 4 && "Illegal insertion index")(static_cast <bool> (AltIdx < 4 && "Illegal insertion index"
) ? void (0) : __assert_fail ("AltIdx < 4 && \"Illegal insertion index\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 2132, __extension__ __PRETTY_FUNCTION__))
;
2133 unsigned AltImm = (AltIdx << 6) | (AltIdx << 4) | ZMask;
2134 auto &WorkingMI = cloneIfNew(MI);
2135 WorkingMI.getOperand(MI.getNumOperands() - 1).setImm(AltImm);
2136 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
2137 OpIdx1, OpIdx2);
2138 }
2139 return nullptr;
2140 }
2141 case X86::MOVSDrr:
2142 case X86::MOVSSrr:
2143 case X86::VMOVSDrr:
2144 case X86::VMOVSSrr:{
2145 // On SSE41 or later we can commute a MOVSS/MOVSD to a BLENDPS/BLENDPD.
2146 if (Subtarget.hasSSE41()) {
2147 unsigned Mask, Opc;
2148 switch (MI.getOpcode()) {
2149 default: llvm_unreachable("Unreachable!")::llvm::llvm_unreachable_internal("Unreachable!", "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 2149)
;
2150 case X86::MOVSDrr: Opc = X86::BLENDPDrri; Mask = 0x02; break;
2151 case X86::MOVSSrr: Opc = X86::BLENDPSrri; Mask = 0x0E; break;
2152 case X86::VMOVSDrr: Opc = X86::VBLENDPDrri; Mask = 0x02; break;
2153 case X86::VMOVSSrr: Opc = X86::VBLENDPSrri; Mask = 0x0E; break;
2154 }
2155
2156 auto &WorkingMI = cloneIfNew(MI);
2157 WorkingMI.setDesc(get(Opc));
2158 WorkingMI.addOperand(MachineOperand::CreateImm(Mask));
2159 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
2160 OpIdx1, OpIdx2);
2161 }
2162
2163 // Convert to SHUFPD.
2164 assert(MI.getOpcode() == X86::MOVSDrr &&(static_cast <bool> (MI.getOpcode() == X86::MOVSDrr &&
"Can only commute MOVSDrr without SSE4.1") ? void (0) : __assert_fail
("MI.getOpcode() == X86::MOVSDrr && \"Can only commute MOVSDrr without SSE4.1\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 2165, __extension__ __PRETTY_FUNCTION__))
2165 "Can only commute MOVSDrr without SSE4.1")(static_cast <bool> (MI.getOpcode() == X86::MOVSDrr &&
"Can only commute MOVSDrr without SSE4.1") ? void (0) : __assert_fail
("MI.getOpcode() == X86::MOVSDrr && \"Can only commute MOVSDrr without SSE4.1\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 2165, __extension__ __PRETTY_FUNCTION__))
;
2166
2167 auto &WorkingMI = cloneIfNew(MI);
2168 WorkingMI.setDesc(get(X86::SHUFPDrri));
2169 WorkingMI.addOperand(MachineOperand::CreateImm(0x02));
2170 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
2171 OpIdx1, OpIdx2);
2172 }
2173 case X86::SHUFPDrri: {
2174 // Commute to MOVSD.
2175 assert(MI.getOperand(3).getImm() == 0x02 && "Unexpected immediate!")(static_cast <bool> (MI.getOperand(3).getImm() == 0x02 &&
"Unexpected immediate!") ? void (0) : __assert_fail ("MI.getOperand(3).getImm() == 0x02 && \"Unexpected immediate!\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 2175, __extension__ __PRETTY_FUNCTION__))
;
2176 auto &WorkingMI = cloneIfNew(MI);
2177 WorkingMI.setDesc(get(X86::MOVSDrr));
2178 WorkingMI.RemoveOperand(3);
2179 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
2180 OpIdx1, OpIdx2);
2181 }
2182 case X86::PCLMULQDQrr:
2183 case X86::VPCLMULQDQrr:
2184 case X86::VPCLMULQDQYrr:
2185 case X86::VPCLMULQDQZrr:
2186 case X86::VPCLMULQDQZ128rr:
2187 case X86::VPCLMULQDQZ256rr: {
2188 // SRC1 64bits = Imm[0] ? SRC1[127:64] : SRC1[63:0]
2189 // SRC2 64bits = Imm[4] ? SRC2[127:64] : SRC2[63:0]
2190 unsigned Imm = MI.getOperand(3).getImm();
2191 unsigned Src1Hi = Imm & 0x01;
2192 unsigned Src2Hi = Imm & 0x10;
2193 auto &WorkingMI = cloneIfNew(MI);
2194 WorkingMI.getOperand(3).setImm((Src1Hi << 4) | (Src2Hi >> 4));
2195 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
2196 OpIdx1, OpIdx2);
2197 }
2198 case X86::VPCMPBZ128rri: case X86::VPCMPUBZ128rri:
2199 case X86::VPCMPBZ256rri: case X86::VPCMPUBZ256rri:
2200 case X86::VPCMPBZrri: case X86::VPCMPUBZrri:
2201 case X86::VPCMPDZ128rri: case X86::VPCMPUDZ128rri:
2202 case X86::VPCMPDZ256rri: case X86::VPCMPUDZ256rri:
2203 case X86::VPCMPDZrri: case X86::VPCMPUDZrri:
2204 case X86::VPCMPQZ128rri: case X86::VPCMPUQZ128rri:
2205 case X86::VPCMPQZ256rri: case X86::VPCMPUQZ256rri:
2206 case X86::VPCMPQZrri: case X86::VPCMPUQZrri:
2207 case X86::VPCMPWZ128rri: case X86::VPCMPUWZ128rri:
2208 case X86::VPCMPWZ256rri: case X86::VPCMPUWZ256rri:
2209 case X86::VPCMPWZrri: case X86::VPCMPUWZrri:
2210 case X86::VPCMPBZ128rrik: case X86::VPCMPUBZ128rrik:
2211 case X86::VPCMPBZ256rrik: case X86::VPCMPUBZ256rrik:
2212 case X86::VPCMPBZrrik: case X86::VPCMPUBZrrik:
2213 case X86::VPCMPDZ128rrik: case X86::VPCMPUDZ128rrik:
2214 case X86::VPCMPDZ256rrik: case X86::VPCMPUDZ256rrik:
2215 case X86::VPCMPDZrrik: case X86::VPCMPUDZrrik:
2216 case X86::VPCMPQZ128rrik: case X86::VPCMPUQZ128rrik:
2217 case X86::VPCMPQZ256rrik: case X86::VPCMPUQZ256rrik:
2218 case X86::VPCMPQZrrik: case X86::VPCMPUQZrrik:
2219 case X86::VPCMPWZ128rrik: case X86::VPCMPUWZ128rrik:
2220 case X86::VPCMPWZ256rrik: case X86::VPCMPUWZ256rrik:
2221 case X86::VPCMPWZrrik: case X86::VPCMPUWZrrik: {
2222 // Flip comparison mode immediate (if necessary).
2223 unsigned Imm = MI.getOperand(MI.getNumOperands() - 1).getImm() & 0x7;
2224 Imm = X86::getSwappedVPCMPImm(Imm);
2225 auto &WorkingMI = cloneIfNew(MI);
2226 WorkingMI.getOperand(MI.getNumOperands() - 1).setImm(Imm);
2227 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
2228 OpIdx1, OpIdx2);
2229 }
2230 case X86::VPCOMBri: case X86::VPCOMUBri:
2231 case X86::VPCOMDri: case X86::VPCOMUDri:
2232 case X86::VPCOMQri: case X86::VPCOMUQri:
2233 case X86::VPCOMWri: case X86::VPCOMUWri: {
2234 // Flip comparison mode immediate (if necessary).
2235 unsigned Imm = MI.getOperand(3).getImm() & 0x7;
2236 Imm = X86::getSwappedVPCOMImm(Imm);
2237 auto &WorkingMI = cloneIfNew(MI);
2238 WorkingMI.getOperand(3).setImm(Imm);
2239 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
2240 OpIdx1, OpIdx2);
2241 }
2242 case X86::VCMPSDZrr:
2243 case X86::VCMPSSZrr:
2244 case X86::VCMPPDZrri:
2245 case X86::VCMPPSZrri:
2246 case X86::VCMPSHZrr:
2247 case X86::VCMPPHZrri:
2248 case X86::VCMPPHZ128rri:
2249 case X86::VCMPPHZ256rri:
2250 case X86::VCMPPDZ128rri:
2251 case X86::VCMPPSZ128rri:
2252 case X86::VCMPPDZ256rri:
2253 case X86::VCMPPSZ256rri:
2254 case X86::VCMPPDZrrik:
2255 case X86::VCMPPSZrrik:
2256 case X86::VCMPPDZ128rrik:
2257 case X86::VCMPPSZ128rrik:
2258 case X86::VCMPPDZ256rrik:
2259 case X86::VCMPPSZ256rrik: {
2260 unsigned Imm =
2261 MI.getOperand(MI.getNumExplicitOperands() - 1).getImm() & 0x1f;
2262 Imm = X86::getSwappedVCMPImm(Imm);
2263 auto &WorkingMI = cloneIfNew(MI);
2264 WorkingMI.getOperand(MI.getNumExplicitOperands() - 1).setImm(Imm);
2265 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
2266 OpIdx1, OpIdx2);
2267 }
2268 case X86::VPERM2F128rr:
2269 case X86::VPERM2I128rr: {
2270 // Flip permute source immediate.
2271 // Imm & 0x02: lo = if set, select Op1.lo/hi else Op0.lo/hi.
2272 // Imm & 0x20: hi = if set, select Op1.lo/hi else Op0.lo/hi.
2273 int8_t Imm = MI.getOperand(3).getImm() & 0xFF;
2274 auto &WorkingMI = cloneIfNew(MI);
2275 WorkingMI.getOperand(3).setImm(Imm ^ 0x22);
2276 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
2277 OpIdx1, OpIdx2);
2278 }
2279 case X86::MOVHLPSrr:
2280 case X86::UNPCKHPDrr:
2281 case X86::VMOVHLPSrr:
2282 case X86::VUNPCKHPDrr:
2283 case X86::VMOVHLPSZrr:
2284 case X86::VUNPCKHPDZ128rr: {
2285 assert(Subtarget.hasSSE2() && "Commuting MOVHLP/UNPCKHPD requires SSE2!")(static_cast <bool> (Subtarget.hasSSE2() && "Commuting MOVHLP/UNPCKHPD requires SSE2!"
) ? void (0) : __assert_fail ("Subtarget.hasSSE2() && \"Commuting MOVHLP/UNPCKHPD requires SSE2!\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 2285, __extension__ __PRETTY_FUNCTION__))
;
2286
2287 unsigned Opc = MI.getOpcode();
2288 switch (Opc) {
2289 default: llvm_unreachable("Unreachable!")::llvm::llvm_unreachable_internal("Unreachable!", "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 2289)
;
2290 case X86::MOVHLPSrr: Opc = X86::UNPCKHPDrr; break;
2291 case X86::UNPCKHPDrr: Opc = X86::MOVHLPSrr; break;
2292 case X86::VMOVHLPSrr: Opc = X86::VUNPCKHPDrr; break;
2293 case X86::VUNPCKHPDrr: Opc = X86::VMOVHLPSrr; break;
2294 case X86::VMOVHLPSZrr: Opc = X86::VUNPCKHPDZ128rr; break;
2295 case X86::VUNPCKHPDZ128rr: Opc = X86::VMOVHLPSZrr; break;
2296 }
2297 auto &WorkingMI = cloneIfNew(MI);
2298 WorkingMI.setDesc(get(Opc));
2299 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
2300 OpIdx1, OpIdx2);
2301 }
2302 case X86::CMOV16rr: case X86::CMOV32rr: case X86::CMOV64rr: {
2303 auto &WorkingMI = cloneIfNew(MI);
2304 unsigned OpNo = MI.getDesc().getNumOperands() - 1;
2305 X86::CondCode CC = static_cast<X86::CondCode>(MI.getOperand(OpNo).getImm());
2306 WorkingMI.getOperand(OpNo).setImm(X86::GetOppositeBranchCondition(CC));
2307 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
2308 OpIdx1, OpIdx2);
2309 }
2310 case X86::VPTERNLOGDZrri: case X86::VPTERNLOGDZrmi:
2311 case X86::VPTERNLOGDZ128rri: case X86::VPTERNLOGDZ128rmi:
2312 case X86::VPTERNLOGDZ256rri: case X86::VPTERNLOGDZ256rmi:
2313 case X86::VPTERNLOGQZrri: case X86::VPTERNLOGQZrmi:
2314 case X86::VPTERNLOGQZ128rri: case X86::VPTERNLOGQZ128rmi:
2315 case X86::VPTERNLOGQZ256rri: case X86::VPTERNLOGQZ256rmi:
2316 case X86::VPTERNLOGDZrrik:
2317 case X86::VPTERNLOGDZ128rrik:
2318 case X86::VPTERNLOGDZ256rrik:
2319 case X86::VPTERNLOGQZrrik:
2320 case X86::VPTERNLOGQZ128rrik:
2321 case X86::VPTERNLOGQZ256rrik:
2322 case X86::VPTERNLOGDZrrikz: case X86::VPTERNLOGDZrmikz:
2323 case X86::VPTERNLOGDZ128rrikz: case X86::VPTERNLOGDZ128rmikz:
2324 case X86::VPTERNLOGDZ256rrikz: case X86::VPTERNLOGDZ256rmikz:
2325 case X86::VPTERNLOGQZrrikz: case X86::VPTERNLOGQZrmikz:
2326 case X86::VPTERNLOGQZ128rrikz: case X86::VPTERNLOGQZ128rmikz:
2327 case X86::VPTERNLOGQZ256rrikz: case X86::VPTERNLOGQZ256rmikz:
2328 case X86::VPTERNLOGDZ128rmbi:
2329 case X86::VPTERNLOGDZ256rmbi:
2330 case X86::VPTERNLOGDZrmbi:
2331 case X86::VPTERNLOGQZ128rmbi:
2332 case X86::VPTERNLOGQZ256rmbi:
2333 case X86::VPTERNLOGQZrmbi:
2334 case X86::VPTERNLOGDZ128rmbikz:
2335 case X86::VPTERNLOGDZ256rmbikz:
2336 case X86::VPTERNLOGDZrmbikz:
2337 case X86::VPTERNLOGQZ128rmbikz:
2338 case X86::VPTERNLOGQZ256rmbikz:
2339 case X86::VPTERNLOGQZrmbikz: {
2340 auto &WorkingMI = cloneIfNew(MI);
2341 commuteVPTERNLOG(WorkingMI, OpIdx1, OpIdx2);
2342 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
2343 OpIdx1, OpIdx2);
2344 }
2345 default: {
2346 if (isCommutableVPERMV3Instruction(MI.getOpcode())) {
2347 unsigned Opc = getCommutedVPERMV3Opcode(MI.getOpcode());
2348 auto &WorkingMI = cloneIfNew(MI);
2349 WorkingMI.setDesc(get(Opc));
2350 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
2351 OpIdx1, OpIdx2);
2352 }
2353
2354 const X86InstrFMA3Group *FMA3Group = getFMA3Group(MI.getOpcode(),
2355 MI.getDesc().TSFlags);
2356 if (FMA3Group) {
2357 unsigned Opc =
2358 getFMA3OpcodeToCommuteOperands(MI, OpIdx1, OpIdx2, *FMA3Group);
2359 auto &WorkingMI = cloneIfNew(MI);
2360 WorkingMI.setDesc(get(Opc));
2361 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
2362 OpIdx1, OpIdx2);
2363 }
2364
2365 return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
2366 }
2367 }
2368}
2369
2370bool
2371X86InstrInfo::findThreeSrcCommutedOpIndices(const MachineInstr &MI,
2372 unsigned &SrcOpIdx1,
2373 unsigned &SrcOpIdx2,
2374 bool IsIntrinsic) const {
2375 uint64_t TSFlags = MI.getDesc().TSFlags;
2376
2377 unsigned FirstCommutableVecOp = 1;
2378 unsigned LastCommutableVecOp = 3;
2379 unsigned KMaskOp = -1U;
2380 if (X86II::isKMasked(TSFlags)) {
2381 // For k-zero-masked operations it is Ok to commute the first vector
2382 // operand. Unless this is an intrinsic instruction.
2383 // For regular k-masked operations a conservative choice is done as the
2384 // elements of the first vector operand, for which the corresponding bit
2385 // in the k-mask operand is set to 0, are copied to the result of the
2386 // instruction.
2387 // TODO/FIXME: The commute still may be legal if it is known that the
2388 // k-mask operand is set to either all ones or all zeroes.
2389 // It is also Ok to commute the 1st operand if all users of MI use only
2390 // the elements enabled by the k-mask operand. For example,
2391 // v4 = VFMADD213PSZrk v1, k, v2, v3; // v1[i] = k[i] ? v2[i]*v1[i]+v3[i]
2392 // : v1[i];
2393 // VMOVAPSZmrk <mem_addr>, k, v4; // this is the ONLY user of v4 ->
2394 // // Ok, to commute v1 in FMADD213PSZrk.
2395
2396 // The k-mask operand has index = 2 for masked and zero-masked operations.
2397 KMaskOp = 2;
2398
2399 // The operand with index = 1 is used as a source for those elements for
2400 // which the corresponding bit in the k-mask is set to 0.
2401 if (X86II::isKMergeMasked(TSFlags) || IsIntrinsic)
2402 FirstCommutableVecOp = 3;
2403
2404 LastCommutableVecOp++;
2405 } else if (IsIntrinsic) {
2406 // Commuting the first operand of an intrinsic instruction isn't possible
2407 // unless we can prove that only the lowest element of the result is used.
2408 FirstCommutableVecOp = 2;
2409 }
2410
2411 if (isMem(MI, LastCommutableVecOp))
2412 LastCommutableVecOp--;
2413
2414 // Only the first RegOpsNum operands are commutable.
2415 // Also, the value 'CommuteAnyOperandIndex' is valid here as it means
2416 // that the operand is not specified/fixed.
2417 if (SrcOpIdx1 != CommuteAnyOperandIndex &&
2418 (SrcOpIdx1 < FirstCommutableVecOp || SrcOpIdx1 > LastCommutableVecOp ||
2419 SrcOpIdx1 == KMaskOp))
2420 return false;
2421 if (SrcOpIdx2 != CommuteAnyOperandIndex &&
2422 (SrcOpIdx2 < FirstCommutableVecOp || SrcOpIdx2 > LastCommutableVecOp ||
2423 SrcOpIdx2 == KMaskOp))
2424 return false;
2425
2426 // Look for two different register operands assumed to be commutable
2427 // regardless of the FMA opcode. The FMA opcode is adjusted later.
2428 if (SrcOpIdx1 == CommuteAnyOperandIndex ||
2429 SrcOpIdx2 == CommuteAnyOperandIndex) {
2430 unsigned CommutableOpIdx2 = SrcOpIdx2;
2431
2432 // At least one of operands to be commuted is not specified and
2433 // this method is free to choose appropriate commutable operands.
2434 if (SrcOpIdx1 == SrcOpIdx2)
2435 // Both of operands are not fixed. By default set one of commutable
2436 // operands to the last register operand of the instruction.
2437 CommutableOpIdx2 = LastCommutableVecOp;
2438 else if (SrcOpIdx2 == CommuteAnyOperandIndex)
2439 // Only one of operands is not fixed.
2440 CommutableOpIdx2 = SrcOpIdx1;
2441
2442 // CommutableOpIdx2 is well defined now. Let's choose another commutable
2443 // operand and assign its index to CommutableOpIdx1.
2444 Register Op2Reg = MI.getOperand(CommutableOpIdx2).getReg();
2445
2446 unsigned CommutableOpIdx1;
2447 for (CommutableOpIdx1 = LastCommutableVecOp;
2448 CommutableOpIdx1 >= FirstCommutableVecOp; CommutableOpIdx1--) {
2449 // Just ignore and skip the k-mask operand.
2450 if (CommutableOpIdx1 == KMaskOp)
2451 continue;
2452
2453 // The commuted operands must have different registers.
2454 // Otherwise, the commute transformation does not change anything and
2455 // is useless then.
2456 if (Op2Reg != MI.getOperand(CommutableOpIdx1).getReg())
2457 break;
2458 }
2459
2460 // No appropriate commutable operands were found.
2461 if (CommutableOpIdx1 < FirstCommutableVecOp)
2462 return false;
2463
2464 // Assign the found pair of commutable indices to SrcOpIdx1 and SrcOpidx2
2465 // to return those values.
2466 if (!fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2,
2467 CommutableOpIdx1, CommutableOpIdx2))
2468 return false;
2469 }
2470
2471 return true;
2472}
2473
2474bool X86InstrInfo::findCommutedOpIndices(const MachineInstr &MI,
2475 unsigned &SrcOpIdx1,
2476 unsigned &SrcOpIdx2) const {
2477 const MCInstrDesc &Desc = MI.getDesc();
2478 if (!Desc.isCommutable())
2479 return false;
2480
2481 switch (MI.getOpcode()) {
2482 case X86::CMPSDrr:
2483 case X86::CMPSSrr:
2484 case X86::CMPPDrri:
2485 case X86::CMPPSrri:
2486 case X86::VCMPSDrr:
2487 case X86::VCMPSSrr:
2488 case X86::VCMPPDrri:
2489 case X86::VCMPPSrri:
2490 case X86::VCMPPDYrri:
2491 case X86::VCMPPSYrri:
2492 case X86::VCMPSDZrr:
2493 case X86::VCMPSSZrr:
2494 case X86::VCMPPDZrri:
2495 case X86::VCMPPSZrri:
2496 case X86::VCMPSHZrr:
2497 case X86::VCMPPHZrri:
2498 case X86::VCMPPHZ128rri:
2499 case X86::VCMPPHZ256rri:
2500 case X86::VCMPPDZ128rri:
2501 case X86::VCMPPSZ128rri:
2502 case X86::VCMPPDZ256rri:
2503 case X86::VCMPPSZ256rri:
2504 case X86::VCMPPDZrrik:
2505 case X86::VCMPPSZrrik:
2506 case X86::VCMPPDZ128rrik:
2507 case X86::VCMPPSZ128rrik:
2508 case X86::VCMPPDZ256rrik:
2509 case X86::VCMPPSZ256rrik: {
2510 unsigned OpOffset = X86II::isKMasked(Desc.TSFlags) ? 1 : 0;
2511
2512 // Float comparison can be safely commuted for
2513 // Ordered/Unordered/Equal/NotEqual tests
2514 unsigned Imm = MI.getOperand(3 + OpOffset).getImm() & 0x7;
2515 switch (Imm) {
2516 default:
2517 // EVEX versions can be commuted.
2518 if ((Desc.TSFlags & X86II::EncodingMask) == X86II::EVEX)
2519 break;
2520 return false;
2521 case 0x00: // EQUAL
2522 case 0x03: // UNORDERED
2523 case 0x04: // NOT EQUAL
2524 case 0x07: // ORDERED
2525 break;
2526 }
2527
2528 // The indices of the commutable operands are 1 and 2 (or 2 and 3
2529 // when masked).
2530 // Assign them to the returned operand indices here.
2531 return fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2, 1 + OpOffset,
2532 2 + OpOffset);
2533 }
2534 case X86::MOVSSrr:
2535 // X86::MOVSDrr is always commutable. MOVSS is only commutable if we can
2536 // form sse4.1 blend. We assume VMOVSSrr/VMOVSDrr is always commutable since
2537 // AVX implies sse4.1.
2538 if (Subtarget.hasSSE41())
2539 return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
2540 return false;
2541 case X86::SHUFPDrri:
2542 // We can commute this to MOVSD.
2543 if (MI.getOperand(3).getImm() == 0x02)
2544 return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
2545 return false;
2546 case X86::MOVHLPSrr:
2547 case X86::UNPCKHPDrr:
2548 case X86::VMOVHLPSrr:
2549 case X86::VUNPCKHPDrr:
2550 case X86::VMOVHLPSZrr:
2551 case X86::VUNPCKHPDZ128rr:
2552 if (Subtarget.hasSSE2())
2553 return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
2554 return false;
2555 case X86::VPTERNLOGDZrri: case X86::VPTERNLOGDZrmi:
2556 case X86::VPTERNLOGDZ128rri: case X86::VPTERNLOGDZ128rmi:
2557 case X86::VPTERNLOGDZ256rri: case X86::VPTERNLOGDZ256rmi:
2558 case X86::VPTERNLOGQZrri: case X86::VPTERNLOGQZrmi:
2559 case X86::VPTERNLOGQZ128rri: case X86::VPTERNLOGQZ128rmi:
2560 case X86::VPTERNLOGQZ256rri: case X86::VPTERNLOGQZ256rmi:
2561 case X86::VPTERNLOGDZrrik:
2562 case X86::VPTERNLOGDZ128rrik:
2563 case X86::VPTERNLOGDZ256rrik:
2564 case X86::VPTERNLOGQZrrik:
2565 case X86::VPTERNLOGQZ128rrik:
2566 case X86::VPTERNLOGQZ256rrik:
2567 case X86::VPTERNLOGDZrrikz: case X86::VPTERNLOGDZrmikz:
2568 case X86::VPTERNLOGDZ128rrikz: case X86::VPTERNLOGDZ128rmikz:
2569 case X86::VPTERNLOGDZ256rrikz: case X86::VPTERNLOGDZ256rmikz:
2570 case X86::VPTERNLOGQZrrikz: case X86::VPTERNLOGQZrmikz:
2571 case X86::VPTERNLOGQZ128rrikz: case X86::VPTERNLOGQZ128rmikz:
2572 case X86::VPTERNLOGQZ256rrikz: case X86::VPTERNLOGQZ256rmikz:
2573 case X86::VPTERNLOGDZ128rmbi:
2574 case X86::VPTERNLOGDZ256rmbi:
2575 case X86::VPTERNLOGDZrmbi:
2576 case X86::VPTERNLOGQZ128rmbi:
2577 case X86::VPTERNLOGQZ256rmbi:
2578 case X86::VPTERNLOGQZrmbi:
2579 case X86::VPTERNLOGDZ128rmbikz:
2580 case X86::VPTERNLOGDZ256rmbikz:
2581 case X86::VPTERNLOGDZrmbikz:
2582 case X86::VPTERNLOGQZ128rmbikz:
2583 case X86::VPTERNLOGQZ256rmbikz:
2584 case X86::VPTERNLOGQZrmbikz:
2585 return findThreeSrcCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
2586 case X86::VPDPWSSDYrr:
2587 case X86::VPDPWSSDrr:
2588 case X86::VPDPWSSDSYrr:
2589 case X86::VPDPWSSDSrr:
2590 case X86::VPDPWSSDZ128r:
2591 case X86::VPDPWSSDZ128rk:
2592 case X86::VPDPWSSDZ128rkz:
2593 case X86::VPDPWSSDZ256r:
2594 case X86::VPDPWSSDZ256rk:
2595 case X86::VPDPWSSDZ256rkz:
2596 case X86::VPDPWSSDZr:
2597 case X86::VPDPWSSDZrk:
2598 case X86::VPDPWSSDZrkz:
2599 case X86::VPDPWSSDSZ128r:
2600 case X86::VPDPWSSDSZ128rk:
2601 case X86::VPDPWSSDSZ128rkz:
2602 case X86::VPDPWSSDSZ256r:
2603 case X86::VPDPWSSDSZ256rk:
2604 case X86::VPDPWSSDSZ256rkz:
2605 case X86::VPDPWSSDSZr:
2606 case X86::VPDPWSSDSZrk:
2607 case X86::VPDPWSSDSZrkz:
2608 case X86::VPMADD52HUQZ128r:
2609 case X86::VPMADD52HUQZ128rk:
2610 case X86::VPMADD52HUQZ128rkz:
2611 case X86::VPMADD52HUQZ256r:
2612 case X86::VPMADD52HUQZ256rk:
2613 case X86::VPMADD52HUQZ256rkz:
2614 case X86::VPMADD52HUQZr:
2615 case X86::VPMADD52HUQZrk:
2616 case X86::VPMADD52HUQZrkz:
2617 case X86::VPMADD52LUQZ128r:
2618 case X86::VPMADD52LUQZ128rk:
2619 case X86::VPMADD52LUQZ128rkz:
2620 case X86::VPMADD52LUQZ256r:
2621 case X86::VPMADD52LUQZ256rk:
2622 case X86::VPMADD52LUQZ256rkz:
2623 case X86::VPMADD52LUQZr:
2624 case X86::VPMADD52LUQZrk:
2625 case X86::VPMADD52LUQZrkz:
2626 case X86::VFMADDCPHZr:
2627 case X86::VFMADDCPHZrk:
2628 case X86::VFMADDCPHZrkz:
2629 case X86::VFMADDCPHZ128r:
2630 case X86::VFMADDCPHZ128rk:
2631 case X86::VFMADDCPHZ128rkz:
2632 case X86::VFMADDCPHZ256r:
2633 case X86::VFMADDCPHZ256rk:
2634 case X86::VFMADDCPHZ256rkz:
2635 case X86::VFMADDCSHZr:
2636 case X86::VFMADDCSHZrk:
2637 case X86::VFMADDCSHZrkz: {
2638 unsigned CommutableOpIdx1 = 2;
2639 unsigned CommutableOpIdx2 = 3;
2640 if (X86II::isKMasked(Desc.TSFlags)) {
2641 // Skip the mask register.
2642 ++CommutableOpIdx1;
2643 ++CommutableOpIdx2;
2644 }
2645 if (!fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2,
2646 CommutableOpIdx1, CommutableOpIdx2))
2647 return false;
2648 if (!MI.getOperand(SrcOpIdx1).isReg() ||
2649 !MI.getOperand(SrcOpIdx2).isReg())
2650 // No idea.
2651 return false;
2652 return true;
2653 }
2654
2655 default:
2656 const X86InstrFMA3Group *FMA3Group = getFMA3Group(MI.getOpcode(),
2657 MI.getDesc().TSFlags);
2658 if (FMA3Group)
2659 return findThreeSrcCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2,
2660 FMA3Group->isIntrinsic());
2661
2662 // Handled masked instructions since we need to skip over the mask input
2663 // and the preserved input.
2664 if (X86II::isKMasked(Desc.TSFlags)) {
2665 // First assume that the first input is the mask operand and skip past it.
2666 unsigned CommutableOpIdx1 = Desc.getNumDefs() + 1;
2667 unsigned CommutableOpIdx2 = Desc.getNumDefs() + 2;
2668 // Check if the first input is tied. If there isn't one then we only
2669 // need to skip the mask operand which we did above.
2670 if ((MI.getDesc().getOperandConstraint(Desc.getNumDefs(),
2671 MCOI::TIED_TO) != -1)) {
2672 // If this is zero masking instruction with a tied operand, we need to
2673 // move the first index back to the first input since this must
2674 // be a 3 input instruction and we want the first two non-mask inputs.
2675 // Otherwise this is a 2 input instruction with a preserved input and
2676 // mask, so we need to move the indices to skip one more input.
2677 if (X86II::isKMergeMasked(Desc.TSFlags)) {
2678 ++CommutableOpIdx1;
2679 ++CommutableOpIdx2;
2680 } else {
2681 --CommutableOpIdx1;
2682 }
2683 }
2684
2685 if (!fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2,
2686 CommutableOpIdx1, CommutableOpIdx2))
2687 return false;
2688
2689 if (!MI.getOperand(SrcOpIdx1).isReg() ||
2690 !MI.getOperand(SrcOpIdx2).isReg())
2691 // No idea.
2692 return false;
2693 return true;
2694 }
2695
2696 return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
2697 }
2698 return false;
2699}
2700
2701static bool isConvertibleLEA(MachineInstr *MI) {
2702 unsigned Opcode = MI->getOpcode();
2703 if (Opcode != X86::LEA32r && Opcode != X86::LEA64r &&
2704 Opcode != X86::LEA64_32r)
2705 return false;
2706
2707 const MachineOperand &Scale = MI->getOperand(1 + X86::AddrScaleAmt);
2708 const MachineOperand &Disp = MI->getOperand(1 + X86::AddrDisp);
2709 const MachineOperand &Segment = MI->getOperand(1 + X86::AddrSegmentReg);
2710
2711 if (Segment.getReg() != 0 || !Disp.isImm() || Disp.getImm() != 0 ||
2712 Scale.getImm() > 1)
2713 return false;
2714
2715 return true;
2716}
2717
2718bool X86InstrInfo::hasCommutePreference(MachineInstr &MI, bool &Commute) const {
2719 // Currently we're interested in following sequence only.
2720 // r3 = lea r1, r2
2721 // r5 = add r3, r4
2722 // Both r3 and r4 are killed in add, we hope the add instruction has the
2723 // operand order
2724 // r5 = add r4, r3
2725 // So later in X86FixupLEAs the lea instruction can be rewritten as add.
2726 unsigned Opcode = MI.getOpcode();
2727 if (Opcode != X86::ADD32rr && Opcode != X86::ADD64rr)
2728 return false;
2729
2730 const MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
2731 Register Reg1 = MI.getOperand(1).getReg();
2732 Register Reg2 = MI.getOperand(2).getReg();
2733
2734 // Check if Reg1 comes from LEA in the same MBB.
2735 if (MachineInstr *Inst = MRI.getUniqueVRegDef(Reg1)) {
2736 if (isConvertibleLEA(Inst) && Inst->getParent() == MI.getParent()) {
2737 Commute = true;
2738 return true;
2739 }
2740 }
2741
2742 // Check if Reg2 comes from LEA in the same MBB.
2743 if (MachineInstr *Inst = MRI.getUniqueVRegDef(Reg2)) {
2744 if (isConvertibleLEA(Inst) && Inst->getParent() == MI.getParent()) {
2745 Commute = false;
2746 return true;
2747 }
2748 }
2749
2750 return false;
2751}
2752
2753X86::CondCode X86::getCondFromBranch(const MachineInstr &MI) {
2754 switch (MI.getOpcode()) {
2755 default: return X86::COND_INVALID;
2756 case X86::JCC_1:
2757 return static_cast<X86::CondCode>(
2758 MI.getOperand(MI.getDesc().getNumOperands() - 1).getImm());
2759 }
2760}
2761
2762/// Return condition code of a SETCC opcode.
2763X86::CondCode X86::getCondFromSETCC(const MachineInstr &MI) {
2764 switch (MI.getOpcode()) {
2765 default: return X86::COND_INVALID;
2766 case X86::SETCCr: case X86::SETCCm:
2767 return static_cast<X86::CondCode>(
2768 MI.getOperand(MI.getDesc().getNumOperands() - 1).getImm());
2769 }
2770}
2771
2772/// Return condition code of a CMov opcode.
2773X86::CondCode X86::getCondFromCMov(const MachineInstr &MI) {
2774 switch (MI.getOpcode()) {
2775 default: return X86::COND_INVALID;
2776 case X86::CMOV16rr: case X86::CMOV32rr: case X86::CMOV64rr:
2777 case X86::CMOV16rm: case X86::CMOV32rm: case X86::CMOV64rm:
2778 return static_cast<X86::CondCode>(
2779 MI.getOperand(MI.getDesc().getNumOperands() - 1).getImm());
2780 }
2781}
2782
2783/// Return the inverse of the specified condition,
2784/// e.g. turning COND_E to COND_NE.
2785X86::CondCode X86::GetOppositeBranchCondition(X86::CondCode CC) {
2786 switch (CC) {
2787 default: llvm_unreachable("Illegal condition code!")::llvm::llvm_unreachable_internal("Illegal condition code!", "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 2787)
;
2788 case X86::COND_E: return X86::COND_NE;
2789 case X86::COND_NE: return X86::COND_E;
2790 case X86::COND_L: return X86::COND_GE;
2791 case X86::COND_LE: return X86::COND_G;
2792 case X86::COND_G: return X86::COND_LE;
2793 case X86::COND_GE: return X86::COND_L;
2794 case X86::COND_B: return X86::COND_AE;
2795 case X86::COND_BE: return X86::COND_A;
2796 case X86::COND_A: return X86::COND_BE;
2797 case X86::COND_AE: return X86::COND_B;
2798 case X86::COND_S: return X86::COND_NS;
2799 case X86::COND_NS: return X86::COND_S;
2800 case X86::COND_P: return X86::COND_NP;
2801 case X86::COND_NP: return X86::COND_P;
2802 case X86::COND_O: return X86::COND_NO;
2803 case X86::COND_NO: return X86::COND_O;
2804 case X86::COND_NE_OR_P: return X86::COND_E_AND_NP;
2805 case X86::COND_E_AND_NP: return X86::COND_NE_OR_P;
2806 }
2807}
2808
2809/// Assuming the flags are set by MI(a,b), return the condition code if we
2810/// modify the instructions such that flags are set by MI(b,a).
2811static X86::CondCode getSwappedCondition(X86::CondCode CC) {
2812 switch (CC) {
2813 default: return X86::COND_INVALID;
2814 case X86::COND_E: return X86::COND_E;
2815 case X86::COND_NE: return X86::COND_NE;
2816 case X86::COND_L: return X86::COND_G;
2817 case X86::COND_LE: return X86::COND_GE;
2818 case X86::COND_G: return X86::COND_L;
2819 case X86::COND_GE: return X86::COND_LE;
2820 case X86::COND_B: return X86::COND_A;
2821 case X86::COND_BE: return X86::COND_AE;
2822 case X86::COND_A: return X86::COND_B;
2823 case X86::COND_AE: return X86::COND_BE;
2824 }
2825}
2826
2827std::pair<X86::CondCode, bool>
2828X86::getX86ConditionCode(CmpInst::Predicate Predicate) {
2829 X86::CondCode CC = X86::COND_INVALID;
2830 bool NeedSwap = false;
2831 switch (Predicate) {
2832 default: break;
2833 // Floating-point Predicates
2834 case CmpInst::FCMP_UEQ: CC = X86::COND_E; break;
2835 case CmpInst::FCMP_OLT: NeedSwap = true; LLVM_FALLTHROUGH[[gnu::fallthrough]];
2836 case CmpInst::FCMP_OGT: CC = X86::COND_A; break;
2837 case CmpInst::FCMP_OLE: NeedSwap = true; LLVM_FALLTHROUGH[[gnu::fallthrough]];
2838 case CmpInst::FCMP_OGE: CC = X86::COND_AE; break;
2839 case CmpInst::FCMP_UGT: NeedSwap = true; LLVM_FALLTHROUGH[[gnu::fallthrough]];
2840 case CmpInst::FCMP_ULT: CC = X86::COND_B; break;
2841 case CmpInst::FCMP_UGE: NeedSwap = true; LLVM_FALLTHROUGH[[gnu::fallthrough]];
2842 case CmpInst::FCMP_ULE: CC = X86::COND_BE; break;
2843 case CmpInst::FCMP_ONE: CC = X86::COND_NE; break;
2844 case CmpInst::FCMP_UNO: CC = X86::COND_P; break;
2845 case CmpInst::FCMP_ORD: CC = X86::COND_NP; break;
2846 case CmpInst::FCMP_OEQ: LLVM_FALLTHROUGH[[gnu::fallthrough]];
2847 case CmpInst::FCMP_UNE: CC = X86::COND_INVALID; break;
2848
2849 // Integer Predicates
2850 case CmpInst::ICMP_EQ: CC = X86::COND_E; break;
2851 case CmpInst::ICMP_NE: CC = X86::COND_NE; break;
2852 case CmpInst::ICMP_UGT: CC = X86::COND_A; break;
2853 case CmpInst::ICMP_UGE: CC = X86::COND_AE; break;
2854 case CmpInst::ICMP_ULT: CC = X86::COND_B; break;
2855 case CmpInst::ICMP_ULE: CC = X86::COND_BE; break;
2856 case CmpInst::ICMP_SGT: CC = X86::COND_G; break;
2857 case CmpInst::ICMP_SGE: CC = X86::COND_GE; break;
2858 case CmpInst::ICMP_SLT: CC = X86::COND_L; break;
2859 case CmpInst::ICMP_SLE: CC = X86::COND_LE; break;
2860 }
2861
2862 return std::make_pair(CC, NeedSwap);
2863}
2864
2865/// Return a setcc opcode based on whether it has memory operand.
2866unsigned X86::getSETOpc(bool HasMemoryOperand) {
2867 return HasMemoryOperand ? X86::SETCCr : X86::SETCCm;
2868}
2869
2870/// Return a cmov opcode for the given register size in bytes, and operand type.
2871unsigned X86::getCMovOpcode(unsigned RegBytes, bool HasMemoryOperand) {
2872 switch(RegBytes) {
2873 default: llvm_unreachable("Illegal register size!")::llvm::llvm_unreachable_internal("Illegal register size!", "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 2873)
;
2874 case 2: return HasMemoryOperand ? X86::CMOV16rm : X86::CMOV16rr;
2875 case 4: return HasMemoryOperand ? X86::CMOV32rm : X86::CMOV32rr;
2876 case 8: return HasMemoryOperand ? X86::CMOV64rm : X86::CMOV64rr;
2877 }
2878}
2879
2880/// Get the VPCMP immediate for the given condition.
2881unsigned X86::getVPCMPImmForCond(ISD::CondCode CC) {
2882 switch (CC) {
2883 default: llvm_unreachable("Unexpected SETCC condition")::llvm::llvm_unreachable_internal("Unexpected SETCC condition"
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 2883)
;
2884 case ISD::SETNE: return 4;
2885 case ISD::SETEQ: return 0;
2886 case ISD::SETULT:
2887 case ISD::SETLT: return 1;
2888 case ISD::SETUGT:
2889 case ISD::SETGT: return 6;
2890 case ISD::SETUGE:
2891 case ISD::SETGE: return 5;
2892 case ISD::SETULE:
2893 case ISD::SETLE: return 2;
2894 }
2895}
2896
2897/// Get the VPCMP immediate if the operands are swapped.
2898unsigned X86::getSwappedVPCMPImm(unsigned Imm) {
2899 switch (Imm) {
2900 default: llvm_unreachable("Unreachable!")::llvm::llvm_unreachable_internal("Unreachable!", "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 2900)
;
2901 case 0x01: Imm = 0x06; break; // LT -> NLE
2902 case 0x02: Imm = 0x05; break; // LE -> NLT
2903 case 0x05: Imm = 0x02; break; // NLT -> LE
2904 case 0x06: Imm = 0x01; break; // NLE -> LT
2905 case 0x00: // EQ
2906 case 0x03: // FALSE
2907 case 0x04: // NE
2908 case 0x07: // TRUE
2909 break;
2910 }
2911
2912 return Imm;
2913}
2914
2915/// Get the VPCOM immediate if the operands are swapped.
2916unsigned X86::getSwappedVPCOMImm(unsigned Imm) {
2917 switch (Imm) {
2918 default: llvm_unreachable("Unreachable!")::llvm::llvm_unreachable_internal("Unreachable!", "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 2918)
;
2919 case 0x00: Imm = 0x02; break; // LT -> GT
2920 case 0x01: Imm = 0x03; break; // LE -> GE
2921 case 0x02: Imm = 0x00; break; // GT -> LT
2922 case 0x03: Imm = 0x01; break; // GE -> LE
2923 case 0x04: // EQ
2924 case 0x05: // NE
2925 case 0x06: // FALSE
2926 case 0x07: // TRUE
2927 break;
2928 }
2929
2930 return Imm;
2931}
2932
2933/// Get the VCMP immediate if the operands are swapped.
2934unsigned X86::getSwappedVCMPImm(unsigned Imm) {
2935 // Only need the lower 2 bits to distinquish.
2936 switch (Imm & 0x3) {
2937 default: llvm_unreachable("Unreachable!")::llvm::llvm_unreachable_internal("Unreachable!", "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 2937)
;
2938 case 0x00: case 0x03:
2939 // EQ/NE/TRUE/FALSE/ORD/UNORD don't change immediate when commuted.
2940 break;
2941 case 0x01: case 0x02:
2942 // Need to toggle bits 3:0. Bit 4 stays the same.
2943 Imm ^= 0xf;
2944 break;
2945 }
2946
2947 return Imm;
2948}
2949
2950bool X86InstrInfo::isUnconditionalTailCall(const MachineInstr &MI) const {
2951 switch (MI.getOpcode()) {
2952 case X86::TCRETURNdi:
2953 case X86::TCRETURNri:
2954 case X86::TCRETURNmi:
2955 case X86::TCRETURNdi64:
2956 case X86::TCRETURNri64:
2957 case X86::TCRETURNmi64:
2958 return true;
2959 default:
2960 return false;
2961 }
2962}
2963
2964bool X86InstrInfo::canMakeTailCallConditional(
2965 SmallVectorImpl<MachineOperand> &BranchCond,
2966 const MachineInstr &TailCall) const {
2967 if (TailCall.getOpcode() != X86::TCRETURNdi &&
2968 TailCall.getOpcode() != X86::TCRETURNdi64) {
2969 // Only direct calls can be done with a conditional branch.
2970 return false;
2971 }
2972
2973 const MachineFunction *MF = TailCall.getParent()->getParent();
2974 if (Subtarget.isTargetWin64() && MF->hasWinCFI()) {
2975 // Conditional tail calls confuse the Win64 unwinder.
2976 return false;
2977 }
2978
2979 assert(BranchCond.size() == 1)(static_cast <bool> (BranchCond.size() == 1) ? void (0)
: __assert_fail ("BranchCond.size() == 1", "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 2979, __extension__ __PRETTY_FUNCTION__))
;
2980 if (BranchCond[0].getImm() > X86::LAST_VALID_COND) {
2981 // Can't make a conditional tail call with this condition.
2982 return false;
2983 }
2984
2985 const X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
2986 if (X86FI->getTCReturnAddrDelta() != 0 ||
2987 TailCall.getOperand(1).getImm() != 0) {
2988 // A conditional tail call cannot do any stack adjustment.
2989 return false;
2990 }
2991
2992 return true;
2993}
2994
2995void X86InstrInfo::replaceBranchWithTailCall(
2996 MachineBasicBlock &MBB, SmallVectorImpl<MachineOperand> &BranchCond,
2997 const MachineInstr &TailCall) const {
2998 assert(canMakeTailCallConditional(BranchCond, TailCall))(static_cast <bool> (canMakeTailCallConditional(BranchCond
, TailCall)) ? void (0) : __assert_fail ("canMakeTailCallConditional(BranchCond, TailCall)"
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 2998, __extension__ __PRETTY_FUNCTION__))
;
2999
3000 MachineBasicBlock::iterator I = MBB.end();
3001 while (I != MBB.begin()) {
3002 --I;
3003 if (I->isDebugInstr())
3004 continue;
3005 if (!I->isBranch())
3006 assert(0 && "Can't find the branch to replace!")(static_cast <bool> (0 && "Can't find the branch to replace!"
) ? void (0) : __assert_fail ("0 && \"Can't find the branch to replace!\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 3006, __extension__ __PRETTY_FUNCTION__))
;
3007
3008 X86::CondCode CC = X86::getCondFromBranch(*I);
3009 assert(BranchCond.size() == 1)(static_cast <bool> (BranchCond.size() == 1) ? void (0)
: __assert_fail ("BranchCond.size() == 1", "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 3009, __extension__ __PRETTY_FUNCTION__))
;
3010 if (CC != BranchCond[0].getImm())
3011 continue;
3012
3013 break;
3014 }
3015
3016 unsigned Opc = TailCall.getOpcode() == X86::TCRETURNdi ? X86::TCRETURNdicc
3017 : X86::TCRETURNdi64cc;
3018
3019 auto MIB = BuildMI(MBB, I, MBB.findDebugLoc(I), get(Opc));
3020 MIB->addOperand(TailCall.getOperand(0)); // Destination.
3021 MIB.addImm(0); // Stack offset (not used).
3022 MIB->addOperand(BranchCond[0]); // Condition.
3023 MIB.copyImplicitOps(TailCall); // Regmask and (imp-used) parameters.
3024
3025 // Add implicit uses and defs of all live regs potentially clobbered by the
3026 // call. This way they still appear live across the call.
3027 LivePhysRegs LiveRegs(getRegisterInfo());
3028 LiveRegs.addLiveOuts(MBB);
3029 SmallVector<std::pair<MCPhysReg, const MachineOperand *>, 8> Clobbers;
3030 LiveRegs.stepForward(*MIB, Clobbers);
3031 for (const auto &C : Clobbers) {
3032 MIB.addReg(C.first, RegState::Implicit);
3033 MIB.addReg(C.first, RegState::Implicit | RegState::Define);
3034 }
3035
3036 I->eraseFromParent();
3037}
3038
3039// Given a MBB and its TBB, find the FBB which was a fallthrough MBB (it may
3040// not be a fallthrough MBB now due to layout changes). Return nullptr if the
3041// fallthrough MBB cannot be identified.
3042static MachineBasicBlock *getFallThroughMBB(MachineBasicBlock *MBB,
3043 MachineBasicBlock *TBB) {
3044 // Look for non-EHPad successors other than TBB. If we find exactly one, it
3045 // is the fallthrough MBB. If we find zero, then TBB is both the target MBB
3046 // and fallthrough MBB. If we find more than one, we cannot identify the
3047 // fallthrough MBB and should return nullptr.
3048 MachineBasicBlock *FallthroughBB = nullptr;
3049 for (auto SI = MBB->succ_begin(), SE = MBB->succ_end(); SI != SE; ++SI) {
3050 if ((*SI)->isEHPad() || (*SI == TBB && FallthroughBB))
3051 continue;
3052 // Return a nullptr if we found more than one fallthrough successor.
3053 if (FallthroughBB && FallthroughBB != TBB)
3054 return nullptr;
3055 FallthroughBB = *SI;
3056 }
3057 return FallthroughBB;
3058}
3059
3060bool X86InstrInfo::AnalyzeBranchImpl(
3061 MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB,
3062 SmallVectorImpl<MachineOperand> &Cond,
3063 SmallVectorImpl<MachineInstr *> &CondBranches, bool AllowModify) const {
3064
3065 // Start from the bottom of the block and work up, examining the
3066 // terminator instructions.
3067 MachineBasicBlock::iterator I = MBB.end();
3068 MachineBasicBlock::iterator UnCondBrIter = MBB.end();
3069 while (I != MBB.begin()) {
3070 --I;
3071 if (I->isDebugInstr())
3072 continue;
3073
3074 // Working from the bottom, when we see a non-terminator instruction, we're
3075 // done.
3076 if (!isUnpredicatedTerminator(*I))
3077 break;
3078
3079 // A terminator that isn't a branch can't easily be handled by this
3080 // analysis.
3081 if (!I->isBranch())
3082 return true;
3083
3084 // Handle unconditional branches.
3085 if (I->getOpcode() == X86::JMP_1) {
3086 UnCondBrIter = I;
3087
3088 if (!AllowModify) {
3089 TBB = I->getOperand(0).getMBB();
3090 continue;
3091 }
3092
3093 // If the block has any instructions after a JMP, delete them.
3094 while (std::next(I) != MBB.end())
3095 std::next(I)->eraseFromParent();
3096
3097 Cond.clear();
3098 FBB = nullptr;
3099
3100 // Delete the JMP if it's equivalent to a fall-through.
3101 if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
3102 TBB = nullptr;
3103 I->eraseFromParent();
3104 I = MBB.end();
3105 UnCondBrIter = MBB.end();
3106 continue;
3107 }
3108
3109 // TBB is used to indicate the unconditional destination.
3110 TBB = I->getOperand(0).getMBB();
3111 continue;
3112 }
3113
3114 // Handle conditional branches.
3115 X86::CondCode BranchCode = X86::getCondFromBranch(*I);
3116 if (BranchCode == X86::COND_INVALID)
3117 return true; // Can't handle indirect branch.
3118
3119 // In practice we should never have an undef eflags operand, if we do
3120 // abort here as we are not prepared to preserve the flag.
3121 if (I->findRegisterUseOperand(X86::EFLAGS)->isUndef())
3122 return true;
3123
3124 // Working from the bottom, handle the first conditional branch.
3125 if (Cond.empty()) {
3126 MachineBasicBlock *TargetBB = I->getOperand(0).getMBB();
3127 if (AllowModify && UnCondBrIter != MBB.end() &&
3128 MBB.isLayoutSuccessor(TargetBB)) {
3129 // If we can modify the code and it ends in something like:
3130 //
3131 // jCC L1
3132 // jmp L2
3133 // L1:
3134 // ...
3135 // L2:
3136 //
3137 // Then we can change this to:
3138 //
3139 // jnCC L2
3140 // L1:
3141 // ...
3142 // L2:
3143 //
3144 // Which is a bit more efficient.
3145 // We conditionally jump to the fall-through block.
3146 BranchCode = GetOppositeBranchCondition(BranchCode);
3147 MachineBasicBlock::iterator OldInst = I;
3148
3149 BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(X86::JCC_1))
3150 .addMBB(UnCondBrIter->getOperand(0).getMBB())
3151 .addImm(BranchCode);
3152 BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(X86::JMP_1))
3153 .addMBB(TargetBB);
3154
3155 OldInst->eraseFromParent();
3156 UnCondBrIter->eraseFromParent();
3157
3158 // Restart the analysis.
3159 UnCondBrIter = MBB.end();
3160 I = MBB.end();
3161 continue;
3162 }
3163
3164 FBB = TBB;
3165 TBB = I->getOperand(0).getMBB();
3166 Cond.push_back(MachineOperand::CreateImm(BranchCode));
3167 CondBranches.push_back(&*I);
3168 continue;
3169 }
3170
3171 // Handle subsequent conditional branches. Only handle the case where all
3172 // conditional branches branch to the same destination and their condition
3173 // opcodes fit one of the special multi-branch idioms.
3174 assert(Cond.size() == 1)(static_cast <bool> (Cond.size() == 1) ? void (0) : __assert_fail
("Cond.size() == 1", "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 3174, __extension__ __PRETTY_FUNCTION__))
;
3175 assert(TBB)(static_cast <bool> (TBB) ? void (0) : __assert_fail ("TBB"
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 3175, __extension__ __PRETTY_FUNCTION__))
;
3176
3177 // If the conditions are the same, we can leave them alone.
3178 X86::CondCode OldBranchCode = (X86::CondCode)Cond[0].getImm();
3179 auto NewTBB = I->getOperand(0).getMBB();
3180 if (OldBranchCode == BranchCode && TBB == NewTBB)
3181 continue;
3182
3183 // If they differ, see if they fit one of the known patterns. Theoretically,
3184 // we could handle more patterns here, but we shouldn't expect to see them
3185 // if instruction selection has done a reasonable job.
3186 if (TBB == NewTBB &&
3187 ((OldBranchCode == X86::COND_P && BranchCode == X86::COND_NE) ||
3188 (OldBranchCode == X86::COND_NE && BranchCode == X86::COND_P))) {
3189 BranchCode = X86::COND_NE_OR_P;
3190 } else if ((OldBranchCode == X86::COND_NP && BranchCode == X86::COND_NE) ||
3191 (OldBranchCode == X86::COND_E && BranchCode == X86::COND_P)) {
3192 if (NewTBB != (FBB ? FBB : getFallThroughMBB(&MBB, TBB)))
3193 return true;
3194
3195 // X86::COND_E_AND_NP usually has two different branch destinations.
3196 //
3197 // JP B1
3198 // JE B2
3199 // JMP B1
3200 // B1:
3201 // B2:
3202 //
3203 // Here this condition branches to B2 only if NP && E. It has another
3204 // equivalent form:
3205 //
3206 // JNE B1
3207 // JNP B2
3208 // JMP B1
3209 // B1:
3210 // B2:
3211 //
3212 // Similarly it branches to B2 only if E && NP. That is why this condition
3213 // is named with COND_E_AND_NP.
3214 BranchCode = X86::COND_E_AND_NP;
3215 } else
3216 return true;
3217
3218 // Update the MachineOperand.
3219 Cond[0].setImm(BranchCode);
3220 CondBranches.push_back(&*I);
3221 }
3222
3223 return false;
3224}
3225
3226bool X86InstrInfo::analyzeBranch(MachineBasicBlock &MBB,
3227 MachineBasicBlock *&TBB,
3228 MachineBasicBlock *&FBB,
3229 SmallVectorImpl<MachineOperand> &Cond,
3230 bool AllowModify) const {
3231 SmallVector<MachineInstr *, 4> CondBranches;
3232 return AnalyzeBranchImpl(MBB, TBB, FBB, Cond, CondBranches, AllowModify);
3233}
3234
3235bool X86InstrInfo::analyzeBranchPredicate(MachineBasicBlock &MBB,
3236 MachineBranchPredicate &MBP,
3237 bool AllowModify) const {
3238 using namespace std::placeholders;
3239
3240 SmallVector<MachineOperand, 4> Cond;
3241 SmallVector<MachineInstr *, 4> CondBranches;
3242 if (AnalyzeBranchImpl(MBB, MBP.TrueDest, MBP.FalseDest, Cond, CondBranches,
3243 AllowModify))
3244 return true;
3245
3246 if (Cond.size() != 1)
3247 return true;
3248
3249 assert(MBP.TrueDest && "expected!")(static_cast <bool> (MBP.TrueDest && "expected!"
) ? void (0) : __assert_fail ("MBP.TrueDest && \"expected!\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 3249, __extension__ __PRETTY_FUNCTION__))
;
3250
3251 if (!MBP.FalseDest)
3252 MBP.FalseDest = MBB.getNextNode();
3253
3254 const TargetRegisterInfo *TRI = &getRegisterInfo();
3255
3256 MachineInstr *ConditionDef = nullptr;
3257 bool SingleUseCondition = true;
3258
3259 for (auto I = std::next(MBB.rbegin()), E = MBB.rend(); I != E; ++I) {
3260 if (I->modifiesRegister(X86::EFLAGS, TRI)) {
3261 ConditionDef = &*I;
3262 break;
3263 }
3264
3265 if (I->readsRegister(X86::EFLAGS, TRI))
3266 SingleUseCondition = false;
3267 }
3268
3269 if (!ConditionDef)
3270 return true;
3271
3272 if (SingleUseCondition) {
3273 for (auto *Succ : MBB.successors())
3274 if (Succ->isLiveIn(X86::EFLAGS))
3275 SingleUseCondition = false;
3276 }
3277
3278 MBP.ConditionDef = ConditionDef;
3279 MBP.SingleUseCondition = SingleUseCondition;
3280
3281 // Currently we only recognize the simple pattern:
3282 //
3283 // test %reg, %reg
3284 // je %label
3285 //
3286 const unsigned TestOpcode =
3287 Subtarget.is64Bit() ? X86::TEST64rr : X86::TEST32rr;
3288
3289 if (ConditionDef->getOpcode() == TestOpcode &&
3290 ConditionDef->getNumOperands() == 3 &&
3291 ConditionDef->getOperand(0).isIdenticalTo(ConditionDef->getOperand(1)) &&
3292 (Cond[0].getImm() == X86::COND_NE || Cond[0].getImm() == X86::COND_E)) {
3293 MBP.LHS = ConditionDef->getOperand(0);
3294 MBP.RHS = MachineOperand::CreateImm(0);
3295 MBP.Predicate = Cond[0].getImm() == X86::COND_NE
3296 ? MachineBranchPredicate::PRED_NE
3297 : MachineBranchPredicate::PRED_EQ;
3298 return false;
3299 }
3300
3301 return true;
3302}
3303
3304unsigned X86InstrInfo::removeBranch(MachineBasicBlock &MBB,
3305 int *BytesRemoved) const {
3306 assert(!BytesRemoved && "code size not handled")(static_cast <bool> (!BytesRemoved && "code size not handled"
) ? void (0) : __assert_fail ("!BytesRemoved && \"code size not handled\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 3306, __extension__ __PRETTY_FUNCTION__))
;
3307
3308 MachineBasicBlock::iterator I = MBB.end();
3309 unsigned Count = 0;
3310
3311 while (I != MBB.begin()) {
3312 --I;
3313 if (I->isDebugInstr())
3314 continue;
3315 if (I->getOpcode() != X86::JMP_1 &&
3316 X86::getCondFromBranch(*I) == X86::COND_INVALID)
3317 break;
3318 // Remove the branch.
3319 I->eraseFromParent();
3320 I = MBB.end();
3321 ++Count;
3322 }
3323
3324 return Count;
3325}
3326
3327unsigned X86InstrInfo::insertBranch(MachineBasicBlock &MBB,
3328 MachineBasicBlock *TBB,
3329 MachineBasicBlock *FBB,
3330 ArrayRef<MachineOperand> Cond,
3331 const DebugLoc &DL,
3332 int *BytesAdded) const {
3333 // Shouldn't be a fall through.
3334 assert(TBB && "insertBranch must not be told to insert a fallthrough")(static_cast <bool> (TBB && "insertBranch must not be told to insert a fallthrough"
) ? void (0) : __assert_fail ("TBB && \"insertBranch must not be told to insert a fallthrough\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 3334, __extension__ __PRETTY_FUNCTION__))
;
3335 assert((Cond.size() == 1 || Cond.size() == 0) &&(static_cast <bool> ((Cond.size() == 1 || Cond.size() ==
0) && "X86 branch conditions have one component!") ?
void (0) : __assert_fail ("(Cond.size() == 1 || Cond.size() == 0) && \"X86 branch conditions have one component!\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 3336, __extension__ __PRETTY_FUNCTION__))
3336 "X86 branch conditions have one component!")(static_cast <bool> ((Cond.size() == 1 || Cond.size() ==
0) && "X86 branch conditions have one component!") ?
void (0) : __assert_fail ("(Cond.size() == 1 || Cond.size() == 0) && \"X86 branch conditions have one component!\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 3336, __extension__ __PRETTY_FUNCTION__))
;
3337 assert(!BytesAdded && "code size not handled")(static_cast <bool> (!BytesAdded && "code size not handled"
) ? void (0) : __assert_fail ("!BytesAdded && \"code size not handled\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 3337, __extension__ __PRETTY_FUNCTION__))
;
3338
3339 if (Cond.empty()) {
3340 // Unconditional branch?
3341 assert(!FBB && "Unconditional branch with multiple successors!")(static_cast <bool> (!FBB && "Unconditional branch with multiple successors!"
) ? void (0) : __assert_fail ("!FBB && \"Unconditional branch with multiple successors!\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 3341, __extension__ __PRETTY_FUNCTION__))
;
3342 BuildMI(&MBB, DL, get(X86::JMP_1)).addMBB(TBB);
3343 return 1;
3344 }
3345
3346 // If FBB is null, it is implied to be a fall-through block.
3347 bool FallThru = FBB == nullptr;
3348
3349 // Conditional branch.
3350 unsigned Count = 0;
3351 X86::CondCode CC = (X86::CondCode)Cond[0].getImm();
3352 switch (CC) {
3353 case X86::COND_NE_OR_P:
3354 // Synthesize NE_OR_P with two branches.
3355 BuildMI(&MBB, DL, get(X86::JCC_1)).addMBB(TBB).addImm(X86::COND_NE);
3356 ++Count;
3357 BuildMI(&MBB, DL, get(X86::JCC_1)).addMBB(TBB).addImm(X86::COND_P);
3358 ++Count;
3359 break;
3360 case X86::COND_E_AND_NP:
3361 // Use the next block of MBB as FBB if it is null.
3362 if (FBB == nullptr) {
3363 FBB = getFallThroughMBB(&MBB, TBB);
3364 assert(FBB && "MBB cannot be the last block in function when the false "(static_cast <bool> (FBB && "MBB cannot be the last block in function when the false "
"body is a fall-through.") ? void (0) : __assert_fail ("FBB && \"MBB cannot be the last block in function when the false \" \"body is a fall-through.\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 3365, __extension__ __PRETTY_FUNCTION__))
3365 "body is a fall-through.")(static_cast <bool> (FBB && "MBB cannot be the last block in function when the false "
"body is a fall-through.") ? void (0) : __assert_fail ("FBB && \"MBB cannot be the last block in function when the false \" \"body is a fall-through.\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 3365, __extension__ __PRETTY_FUNCTION__))
;
3366 }
3367 // Synthesize COND_E_AND_NP with two branches.
3368 BuildMI(&MBB, DL, get(X86::JCC_1)).addMBB(FBB).addImm(X86::COND_NE);
3369 ++Count;
3370 BuildMI(&MBB, DL, get(X86::JCC_1)).addMBB(TBB).addImm(X86::COND_NP);
3371 ++Count;
3372 break;
3373 default: {
3374 BuildMI(&MBB, DL, get(X86::JCC_1)).addMBB(TBB).addImm(CC);
3375 ++Count;
3376 }
3377 }
3378 if (!FallThru) {
3379 // Two-way Conditional branch. Insert the second branch.
3380 BuildMI(&MBB, DL, get(X86::JMP_1)).addMBB(FBB);
3381 ++Count;
3382 }
3383 return Count;
3384}
3385
3386bool X86InstrInfo::canInsertSelect(const MachineBasicBlock &MBB,
3387 ArrayRef<MachineOperand> Cond,
3388 Register DstReg, Register TrueReg,
3389 Register FalseReg, int &CondCycles,
3390 int &TrueCycles, int &FalseCycles) const {
3391 // Not all subtargets have cmov instructions.
3392 if (!Subtarget.hasCMov())
3393 return false;
3394 if (Cond.size() != 1)
3395 return false;
3396 // We cannot do the composite conditions, at least not in SSA form.
3397 if ((X86::CondCode)Cond[0].getImm() > X86::LAST_VALID_COND)
3398 return false;
3399
3400 // Check register classes.
3401 const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
3402 const TargetRegisterClass *RC =
3403 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
3404 if (!RC)
3405 return false;
3406
3407 // We have cmov instructions for 16, 32, and 64 bit general purpose registers.
3408 if (X86::GR16RegClass.hasSubClassEq(RC) ||
3409 X86::GR32RegClass.hasSubClassEq(RC) ||
3410 X86::GR64RegClass.hasSubClassEq(RC)) {
3411 // This latency applies to Pentium M, Merom, Wolfdale, Nehalem, and Sandy
3412 // Bridge. Probably Ivy Bridge as well.
3413 CondCycles = 2;
3414 TrueCycles = 2;
3415 FalseCycles = 2;
3416 return true;
3417 }
3418
3419 // Can't do vectors.
3420 return false;
3421}
3422
3423void X86InstrInfo::insertSelect(MachineBasicBlock &MBB,
3424 MachineBasicBlock::iterator I,
3425 const DebugLoc &DL, Register DstReg,
3426 ArrayRef<MachineOperand> Cond, Register TrueReg,
3427 Register FalseReg) const {
3428 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
3429 const TargetRegisterInfo &TRI = *MRI.getTargetRegisterInfo();
3430 const TargetRegisterClass &RC = *MRI.getRegClass(DstReg);
3431 assert(Cond.size() == 1 && "Invalid Cond array")(static_cast <bool> (Cond.size() == 1 && "Invalid Cond array"
) ? void (0) : __assert_fail ("Cond.size() == 1 && \"Invalid Cond array\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 3431, __extension__ __PRETTY_FUNCTION__))
;
3432 unsigned Opc = X86::getCMovOpcode(TRI.getRegSizeInBits(RC) / 8,
3433 false /*HasMemoryOperand*/);
3434 BuildMI(MBB, I, DL, get(Opc), DstReg)
3435 .addReg(FalseReg)
3436 .addReg(TrueReg)
3437 .addImm(Cond[0].getImm());
3438}
3439
3440/// Test if the given register is a physical h register.
3441static bool isHReg(unsigned Reg) {
3442 return X86::GR8_ABCD_HRegClass.contains(Reg);
3443}
3444
3445// Try and copy between VR128/VR64 and GR64 registers.
3446static unsigned CopyToFromAsymmetricReg(unsigned DestReg, unsigned SrcReg,
3447 const X86Subtarget &Subtarget) {
3448 bool HasAVX = Subtarget.hasAVX();
3449 bool HasAVX512 = Subtarget.hasAVX512();
3450
3451 // SrcReg(MaskReg) -> DestReg(GR64)
3452 // SrcReg(MaskReg) -> DestReg(GR32)
3453
3454 // All KMASK RegClasses hold the same k registers, can be tested against anyone.
3455 if (X86::VK16RegClass.contains(SrcReg)) {
3456 if (X86::GR64RegClass.contains(DestReg)) {
3457 assert(Subtarget.hasBWI())(static_cast <bool> (Subtarget.hasBWI()) ? void (0) : __assert_fail
("Subtarget.hasBWI()", "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 3457, __extension__ __PRETTY_FUNCTION__))
;
3458 return X86::KMOVQrk;
3459 }
3460 if (X86::GR32RegClass.contains(DestReg))
3461 return Subtarget.hasBWI() ? X86::KMOVDrk : X86::KMOVWrk;
3462 }
3463
3464 // SrcReg(GR64) -> DestReg(MaskReg)
3465 // SrcReg(GR32) -> DestReg(MaskReg)
3466
3467 // All KMASK RegClasses hold the same k registers, can be tested against anyone.
3468 if (X86::VK16RegClass.contains(DestReg)) {
3469 if (X86::GR64RegClass.contains(SrcReg)) {
3470 assert(Subtarget.hasBWI())(static_cast <bool> (Subtarget.hasBWI()) ? void (0) : __assert_fail
("Subtarget.hasBWI()", "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 3470, __extension__ __PRETTY_FUNCTION__))
;
3471 return X86::KMOVQkr;
3472 }
3473 if (X86::GR32RegClass.contains(SrcReg))
3474 return Subtarget.hasBWI() ? X86::KMOVDkr : X86::KMOVWkr;
3475 }
3476
3477
3478 // SrcReg(VR128) -> DestReg(GR64)
3479 // SrcReg(VR64) -> DestReg(GR64)
3480 // SrcReg(GR64) -> DestReg(VR128)
3481 // SrcReg(GR64) -> DestReg(VR64)
3482
3483 if (X86::GR64RegClass.contains(DestReg)) {
3484 if (X86::VR128XRegClass.contains(SrcReg))
3485 // Copy from a VR128 register to a GR64 register.
3486 return HasAVX512 ? X86::VMOVPQIto64Zrr :
3487 HasAVX ? X86::VMOVPQIto64rr :
3488 X86::MOVPQIto64rr;
3489 if (X86::VR64RegClass.contains(SrcReg))
3490 // Copy from a VR64 register to a GR64 register.
3491 return X86::MMX_MOVD64from64rr;
3492 } else if (X86::GR64RegClass.contains(SrcReg)) {
3493 // Copy from a GR64 register to a VR128 register.
3494 if (X86::VR128XRegClass.contains(DestReg))
3495 return HasAVX512 ? X86::VMOV64toPQIZrr :
3496 HasAVX ? X86::VMOV64toPQIrr :
3497 X86::MOV64toPQIrr;
3498 // Copy from a GR64 register to a VR64 register.
3499 if (X86::VR64RegClass.contains(DestReg))
3500 return X86::MMX_MOVD64to64rr;
3501 }
3502
3503 // SrcReg(VR128) -> DestReg(GR32)
3504 // SrcReg(GR32) -> DestReg(VR128)
3505
3506 if (X86::GR32RegClass.contains(DestReg) &&
3507 X86::VR128XRegClass.contains(SrcReg))
3508 // Copy from a VR128 register to a GR32 register.
3509 return HasAVX512 ? X86::VMOVPDI2DIZrr :
3510 HasAVX ? X86::VMOVPDI2DIrr :
3511 X86::MOVPDI2DIrr;
3512
3513 if (X86::VR128XRegClass.contains(DestReg) &&
3514 X86::GR32RegClass.contains(SrcReg))
3515 // Copy from a VR128 register to a VR128 register.
3516 return HasAVX512 ? X86::VMOVDI2PDIZrr :
3517 HasAVX ? X86::VMOVDI2PDIrr :
3518 X86::MOVDI2PDIrr;
3519 return 0;
3520}
3521
3522void X86InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
3523 MachineBasicBlock::iterator MI,
3524 const DebugLoc &DL, MCRegister DestReg,
3525 MCRegister SrcReg, bool KillSrc) const {
3526 // First deal with the normal symmetric copies.
3527 bool HasAVX = Subtarget.hasAVX();
3528 bool HasVLX = Subtarget.hasVLX();
3529 unsigned Opc = 0;
3530 if (X86::GR64RegClass.contains(DestReg, SrcReg))
3531 Opc = X86::MOV64rr;
3532 else if (X86::GR32RegClass.contains(DestReg, SrcReg))
3533 Opc = X86::MOV32rr;
3534 else if (X86::GR16RegClass.contains(DestReg, SrcReg))
3535 Opc = X86::MOV16rr;
3536 else if (X86::GR8RegClass.contains(DestReg, SrcReg)) {
3537 // Copying to or from a physical H register on x86-64 requires a NOREX
3538 // move. Otherwise use a normal move.
3539 if ((isHReg(DestReg) || isHReg(SrcReg)) &&
3540 Subtarget.is64Bit()) {
3541 Opc = X86::MOV8rr_NOREX;
3542 // Both operands must be encodable without an REX prefix.
3543 assert(X86::GR8_NOREXRegClass.contains(SrcReg, DestReg) &&(static_cast <bool> (X86::GR8_NOREXRegClass.contains(SrcReg
, DestReg) && "8-bit H register can not be copied outside GR8_NOREX"
) ? void (0) : __assert_fail ("X86::GR8_NOREXRegClass.contains(SrcReg, DestReg) && \"8-bit H register can not be copied outside GR8_NOREX\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 3544, __extension__ __PRETTY_FUNCTION__))
3544 "8-bit H register can not be copied outside GR8_NOREX")(static_cast <bool> (X86::GR8_NOREXRegClass.contains(SrcReg
, DestReg) && "8-bit H register can not be copied outside GR8_NOREX"
) ? void (0) : __assert_fail ("X86::GR8_NOREXRegClass.contains(SrcReg, DestReg) && \"8-bit H register can not be copied outside GR8_NOREX\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 3544, __extension__ __PRETTY_FUNCTION__))
;
3545 } else
3546 Opc = X86::MOV8rr;
3547 }
3548 else if (X86::VR64RegClass.contains(DestReg, SrcReg))
3549 Opc = X86::MMX_MOVQ64rr;
3550 else if (X86::VR128XRegClass.contains(DestReg, SrcReg)) {
3551 if (HasVLX)
3552 Opc = X86::VMOVAPSZ128rr;
3553 else if (X86::VR128RegClass.contains(DestReg, SrcReg))
3554 Opc = HasAVX ? X86::VMOVAPSrr : X86::MOVAPSrr;
3555 else {
3556 // If this an extended register and we don't have VLX we need to use a
3557 // 512-bit move.
3558 Opc = X86::VMOVAPSZrr;
3559 const TargetRegisterInfo *TRI = &getRegisterInfo();
3560 DestReg = TRI->getMatchingSuperReg(DestReg, X86::sub_xmm,
3561 &X86::VR512RegClass);
3562 SrcReg = TRI->getMatchingSuperReg(SrcReg, X86::sub_xmm,
3563 &X86::VR512RegClass);
3564 }
3565 } else if (X86::VR256XRegClass.contains(DestReg, SrcReg)) {
3566 if (HasVLX)
3567 Opc = X86::VMOVAPSZ256rr;
3568 else if (X86::VR256RegClass.contains(DestReg, SrcReg))
3569 Opc = X86::VMOVAPSYrr;
3570 else {
3571 // If this an extended register and we don't have VLX we need to use a
3572 // 512-bit move.
3573 Opc = X86::VMOVAPSZrr;
3574 const TargetRegisterInfo *TRI = &getRegisterInfo();
3575 DestReg = TRI->getMatchingSuperReg(DestReg, X86::sub_ymm,
3576 &X86::VR512RegClass);
3577 SrcReg = TRI->getMatchingSuperReg(SrcReg, X86::sub_ymm,
3578 &X86::VR512RegClass);
3579 }
3580 } else if (X86::VR512RegClass.contains(DestReg, SrcReg))
3581 Opc = X86::VMOVAPSZrr;
3582 // All KMASK RegClasses hold the same k registers, can be tested against anyone.
3583 else if (X86::VK16RegClass.contains(DestReg, SrcReg))
3584 Opc = Subtarget.hasBWI() ? X86::KMOVQkk : X86::KMOVWkk;
3585 if (!Opc)
3586 Opc = CopyToFromAsymmetricReg(DestReg, SrcReg, Subtarget);
3587
3588 if (Opc) {
3589 BuildMI(MBB, MI, DL, get(Opc), DestReg)
3590 .addReg(SrcReg, getKillRegState(KillSrc));
3591 return;
3592 }
3593
3594 if (SrcReg == X86::EFLAGS || DestReg == X86::EFLAGS) {
3595 // FIXME: We use a fatal error here because historically LLVM has tried
3596 // lower some of these physreg copies and we want to ensure we get
3597 // reasonable bug reports if someone encounters a case no other testing
3598 // found. This path should be removed after the LLVM 7 release.
3599 report_fatal_error("Unable to copy EFLAGS physical register!");
3600 }
3601
3602 LLVM_DEBUG(dbgs() << "Cannot copy " << RI.getName(SrcReg) << " to "do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("x86-instr-info")) { dbgs() << "Cannot copy " <<
RI.getName(SrcReg) << " to " << RI.getName(DestReg
) << '\n'; } } while (false)
3603 << RI.getName(DestReg) << '\n')do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("x86-instr-info")) { dbgs() << "Cannot copy " <<
RI.getName(SrcReg) << " to " << RI.getName(DestReg
) << '\n'; } } while (false)
;
3604 report_fatal_error("Cannot emit physreg copy instruction");
3605}
3606
3607Optional<DestSourcePair>
3608X86InstrInfo::isCopyInstrImpl(const MachineInstr &MI) const {
3609 if (MI.isMoveReg())
3610 return DestSourcePair{MI.getOperand(0), MI.getOperand(1)};
3611 return None;
3612}
3613
3614static unsigned getLoadStoreRegOpcode(Register Reg,
3615 const TargetRegisterClass *RC,
3616 bool IsStackAligned,
3617 const X86Subtarget &STI, bool load) {
3618 bool HasAVX = STI.hasAVX();
3619 bool HasAVX512 = STI.hasAVX512();
3620 bool HasVLX = STI.hasVLX();
3621
3622 switch (STI.getRegisterInfo()->getSpillSize(*RC)) {
3623 default:
3624 llvm_unreachable("Unknown spill size")::llvm::llvm_unreachable_internal("Unknown spill size", "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 3624)
;
3625 case 1:
3626 assert(X86::GR8RegClass.hasSubClassEq(RC) && "Unknown 1-byte regclass")(static_cast <bool> (X86::GR8RegClass.hasSubClassEq(RC)
&& "Unknown 1-byte regclass") ? void (0) : __assert_fail
("X86::GR8RegClass.hasSubClassEq(RC) && \"Unknown 1-byte regclass\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 3626, __extension__ __PRETTY_FUNCTION__))
;
3627 if (STI.is64Bit())
3628 // Copying to or from a physical H register on x86-64 requires a NOREX
3629 // move. Otherwise use a normal move.
3630 if (isHReg(Reg) || X86::GR8_ABCD_HRegClass.hasSubClassEq(RC))
3631 return load ? X86::MOV8rm_NOREX : X86::MOV8mr_NOREX;
3632 return load ? X86::MOV8rm : X86::MOV8mr;
3633 case 2:
3634 if (X86::VK16RegClass.hasSubClassEq(RC))
3635 return load ? X86::KMOVWkm : X86::KMOVWmk;
3636 if (X86::FR16XRegClass.hasSubClassEq(RC)) {
3637 assert(STI.hasFP16())(static_cast <bool> (STI.hasFP16()) ? void (0) : __assert_fail
("STI.hasFP16()", "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 3637, __extension__ __PRETTY_FUNCTION__))
;
3638 return load ? X86::VMOVSHZrm_alt : X86::VMOVSHZmr;
3639 }
3640 assert(X86::GR16RegClass.hasSubClassEq(RC) && "Unknown 2-byte regclass")(static_cast <bool> (X86::GR16RegClass.hasSubClassEq(RC
) && "Unknown 2-byte regclass") ? void (0) : __assert_fail
("X86::GR16RegClass.hasSubClassEq(RC) && \"Unknown 2-byte regclass\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 3640, __extension__ __PRETTY_FUNCTION__))
;
3641 return load ? X86::MOV16rm : X86::MOV16mr;
3642 case 4:
3643 if (X86::GR32RegClass.hasSubClassEq(RC))
3644 return load ? X86::MOV32rm : X86::MOV32mr;
3645 if (X86::FR32XRegClass.hasSubClassEq(RC))
3646 return load ?
3647 (HasAVX512 ? X86::VMOVSSZrm_alt :
3648 HasAVX ? X86::VMOVSSrm_alt :
3649 X86::MOVSSrm_alt) :
3650 (HasAVX512 ? X86::VMOVSSZmr :
3651 HasAVX ? X86::VMOVSSmr :
3652 X86::MOVSSmr);
3653 if (X86::RFP32RegClass.hasSubClassEq(RC))
3654 return load ? X86::LD_Fp32m : X86::ST_Fp32m;
3655 if (X86::VK32RegClass.hasSubClassEq(RC)) {
3656 assert(STI.hasBWI() && "KMOVD requires BWI")(static_cast <bool> (STI.hasBWI() && "KMOVD requires BWI"
) ? void (0) : __assert_fail ("STI.hasBWI() && \"KMOVD requires BWI\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 3656, __extension__ __PRETTY_FUNCTION__))
;
3657 return load ? X86::KMOVDkm : X86::KMOVDmk;
3658 }
3659 // All of these mask pair classes have the same spill size, the same kind
3660 // of kmov instructions can be used with all of them.
3661 if (X86::VK1PAIRRegClass.hasSubClassEq(RC) ||
3662 X86::VK2PAIRRegClass.hasSubClassEq(RC) ||
3663 X86::VK4PAIRRegClass.hasSubClassEq(RC) ||
3664 X86::VK8PAIRRegClass.hasSubClassEq(RC) ||
3665 X86::VK16PAIRRegClass.hasSubClassEq(RC))
3666 return load ? X86::MASKPAIR16LOAD : X86::MASKPAIR16STORE;
3667 llvm_unreachable("Unknown 4-byte regclass")::llvm::llvm_unreachable_internal("Unknown 4-byte regclass", "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 3667)
;
3668 case 8:
3669 if (X86::GR64RegClass.hasSubClassEq(RC))
3670 return load ? X86::MOV64rm : X86::MOV64mr;
3671 if (X86::FR64XRegClass.hasSubClassEq(RC))
3672 return load ?
3673 (HasAVX512 ? X86::VMOVSDZrm_alt :
3674 HasAVX ? X86::VMOVSDrm_alt :
3675 X86::MOVSDrm_alt) :
3676 (HasAVX512 ? X86::VMOVSDZmr :
3677 HasAVX ? X86::VMOVSDmr :
3678 X86::MOVSDmr);
3679 if (X86::VR64RegClass.hasSubClassEq(RC))
3680 return load ? X86::MMX_MOVQ64rm : X86::MMX_MOVQ64mr;
3681 if (X86::RFP64RegClass.hasSubClassEq(RC))
3682 return load ? X86::LD_Fp64m : X86::ST_Fp64m;
3683 if (X86::VK64RegClass.hasSubClassEq(RC)) {
3684 assert(STI.hasBWI() && "KMOVQ requires BWI")(static_cast <bool> (STI.hasBWI() && "KMOVQ requires BWI"
) ? void (0) : __assert_fail ("STI.hasBWI() && \"KMOVQ requires BWI\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 3684, __extension__ __PRETTY_FUNCTION__))
;
3685 return load ? X86::KMOVQkm : X86::KMOVQmk;
3686 }
3687 llvm_unreachable("Unknown 8-byte regclass")::llvm::llvm_unreachable_internal("Unknown 8-byte regclass", "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 3687)
;
3688 case 10:
3689 assert(X86::RFP80RegClass.hasSubClassEq(RC) && "Unknown 10-byte regclass")(static_cast <bool> (X86::RFP80RegClass.hasSubClassEq(RC
) && "Unknown 10-byte regclass") ? void (0) : __assert_fail
("X86::RFP80RegClass.hasSubClassEq(RC) && \"Unknown 10-byte regclass\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 3689, __extension__ __PRETTY_FUNCTION__))
;
3690 return load ? X86::LD_Fp80m : X86::ST_FpP80m;
3691 case 16: {
3692 if (X86::VR128XRegClass.hasSubClassEq(RC)) {
3693 // If stack is realigned we can use aligned stores.
3694 if (IsStackAligned)
3695 return load ?
3696 (HasVLX ? X86::VMOVAPSZ128rm :
3697 HasAVX512 ? X86::VMOVAPSZ128rm_NOVLX :
3698 HasAVX ? X86::VMOVAPSrm :
3699 X86::MOVAPSrm):
3700 (HasVLX ? X86::VMOVAPSZ128mr :
3701 HasAVX512 ? X86::VMOVAPSZ128mr_NOVLX :
3702 HasAVX ? X86::VMOVAPSmr :
3703 X86::MOVAPSmr);
3704 else
3705 return load ?
3706 (HasVLX ? X86::VMOVUPSZ128rm :
3707 HasAVX512 ? X86::VMOVUPSZ128rm_NOVLX :
3708 HasAVX ? X86::VMOVUPSrm :
3709 X86::MOVUPSrm):
3710 (HasVLX ? X86::VMOVUPSZ128mr :
3711 HasAVX512 ? X86::VMOVUPSZ128mr_NOVLX :
3712 HasAVX ? X86::VMOVUPSmr :
3713 X86::MOVUPSmr);
3714 }
3715 if (X86::BNDRRegClass.hasSubClassEq(RC)) {
3716 if (STI.is64Bit())
3717 return load ? X86::BNDMOV64rm : X86::BNDMOV64mr;
3718 else
3719 return load ? X86::BNDMOV32rm : X86::BNDMOV32mr;
3720 }
3721 llvm_unreachable("Unknown 16-byte regclass")::llvm::llvm_unreachable_internal("Unknown 16-byte regclass",
"/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 3721)
;
3722 }
3723 case 32:
3724 assert(X86::VR256XRegClass.hasSubClassEq(RC) && "Unknown 32-byte regclass")(static_cast <bool> (X86::VR256XRegClass.hasSubClassEq(
RC) && "Unknown 32-byte regclass") ? void (0) : __assert_fail
("X86::VR256XRegClass.hasSubClassEq(RC) && \"Unknown 32-byte regclass\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 3724, __extension__ __PRETTY_FUNCTION__))
;
3725 // If stack is realigned we can use aligned stores.
3726 if (IsStackAligned)
3727 return load ?
3728 (HasVLX ? X86::VMOVAPSZ256rm :
3729 HasAVX512 ? X86::VMOVAPSZ256rm_NOVLX :
3730 X86::VMOVAPSYrm) :
3731 (HasVLX ? X86::VMOVAPSZ256mr :
3732 HasAVX512 ? X86::VMOVAPSZ256mr_NOVLX :
3733 X86::VMOVAPSYmr);
3734 else
3735 return load ?
3736 (HasVLX ? X86::VMOVUPSZ256rm :
3737 HasAVX512 ? X86::VMOVUPSZ256rm_NOVLX :
3738 X86::VMOVUPSYrm) :
3739 (HasVLX ? X86::VMOVUPSZ256mr :
3740 HasAVX512 ? X86::VMOVUPSZ256mr_NOVLX :
3741 X86::VMOVUPSYmr);
3742 case 64:
3743 assert(X86::VR512RegClass.hasSubClassEq(RC) && "Unknown 64-byte regclass")(static_cast <bool> (X86::VR512RegClass.hasSubClassEq(RC
) && "Unknown 64-byte regclass") ? void (0) : __assert_fail
("X86::VR512RegClass.hasSubClassEq(RC) && \"Unknown 64-byte regclass\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 3743, __extension__ __PRETTY_FUNCTION__))
;
3744 assert(STI.hasAVX512() && "Using 512-bit register requires AVX512")(static_cast <bool> (STI.hasAVX512() && "Using 512-bit register requires AVX512"
) ? void (0) : __assert_fail ("STI.hasAVX512() && \"Using 512-bit register requires AVX512\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 3744, __extension__ __PRETTY_FUNCTION__))
;
3745 if (IsStackAligned)
3746 return load ? X86::VMOVAPSZrm : X86::VMOVAPSZmr;
3747 else
3748 return load ? X86::VMOVUPSZrm : X86::VMOVUPSZmr;
3749 }
3750}
3751
3752Optional<ExtAddrMode>
3753X86InstrInfo::getAddrModeFromMemoryOp(const MachineInstr &MemI,
3754 const TargetRegisterInfo *TRI) const {
3755 const MCInstrDesc &Desc = MemI.getDesc();
3756 int MemRefBegin = X86II::getMemoryOperandNo(Desc.TSFlags);
3757 if (MemRefBegin < 0)
3758 return None;
3759
3760 MemRefBegin += X86II::getOperandBias(Desc);
3761
3762 auto &BaseOp = MemI.getOperand(MemRefBegin + X86::AddrBaseReg);
3763 if (!BaseOp.isReg()) // Can be an MO_FrameIndex
3764 return None;
3765
3766 const MachineOperand &DispMO = MemI.getOperand(MemRefBegin + X86::AddrDisp);
3767 // Displacement can be symbolic
3768 if (!DispMO.isImm())
3769 return None;
3770
3771 ExtAddrMode AM;
3772 AM.BaseReg = BaseOp.getReg();
3773 AM.ScaledReg = MemI.getOperand(MemRefBegin + X86::AddrIndexReg).getReg();
3774 AM.Scale = MemI.getOperand(MemRefBegin + X86::AddrScaleAmt).getImm();
3775 AM.Displacement = DispMO.getImm();
3776 return AM;
3777}
3778
3779bool X86InstrInfo::getConstValDefinedInReg(const MachineInstr &MI,
3780 const Register Reg,
3781 int64_t &ImmVal) const {
3782 if (MI.getOpcode() != X86::MOV32ri && MI.getOpcode() != X86::MOV64ri)
3783 return false;
3784 // Mov Src can be a global address.
3785 if (!MI.getOperand(1).isImm() || MI.getOperand(0).getReg() != Reg)
3786 return false;
3787 ImmVal = MI.getOperand(1).getImm();
3788 return true;
3789}
3790
3791bool X86InstrInfo::preservesZeroValueInReg(
3792 const MachineInstr *MI, const Register NullValueReg,
3793 const TargetRegisterInfo *TRI) const {
3794 if (!MI->modifiesRegister(NullValueReg, TRI))
3795 return true;
3796 switch (MI->getOpcode()) {
3797 // Shift right/left of a null unto itself is still a null, i.e. rax = shl rax
3798 // X.
3799 case X86::SHR64ri:
3800 case X86::SHR32ri:
3801 case X86::SHL64ri:
3802 case X86::SHL32ri:
3803 assert(MI->getOperand(0).isDef() && MI->getOperand(1).isUse() &&(static_cast <bool> (MI->getOperand(0).isDef() &&
MI->getOperand(1).isUse() && "expected for shift opcode!"
) ? void (0) : __assert_fail ("MI->getOperand(0).isDef() && MI->getOperand(1).isUse() && \"expected for shift opcode!\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 3804, __extension__ __PRETTY_FUNCTION__))
3804 "expected for shift opcode!")(static_cast <bool> (MI->getOperand(0).isDef() &&
MI->getOperand(1).isUse() && "expected for shift opcode!"
) ? void (0) : __assert_fail ("MI->getOperand(0).isDef() && MI->getOperand(1).isUse() && \"expected for shift opcode!\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 3804, __extension__ __PRETTY_FUNCTION__))
;
3805 return MI->getOperand(0).getReg() == NullValueReg &&
3806 MI->getOperand(1).getReg() == NullValueReg;
3807 // Zero extend of a sub-reg of NullValueReg into itself does not change the
3808 // null value.
3809 case X86::MOV32rr:
3810 return llvm::all_of(MI->operands(), [&](const MachineOperand &MO) {
3811 return TRI->isSubRegisterEq(NullValueReg, MO.getReg());
3812 });
3813 default:
3814 return false;
3815 }
3816 llvm_unreachable("Should be handled above!")::llvm::llvm_unreachable_internal("Should be handled above!",
"/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 3816)
;
3817}
3818
3819bool X86InstrInfo::getMemOperandsWithOffsetWidth(
3820 const MachineInstr &MemOp, SmallVectorImpl<const MachineOperand *> &BaseOps,
3821 int64_t &Offset, bool &OffsetIsScalable, unsigned &Width,
3822 const TargetRegisterInfo *TRI) const {
3823 const MCInstrDesc &Desc = MemOp.getDesc();
3824 int MemRefBegin = X86II::getMemoryOperandNo(Desc.TSFlags);
3825 if (MemRefBegin < 0)
3826 return false;
3827
3828 MemRefBegin += X86II::getOperandBias(Desc);
3829
3830 const MachineOperand *BaseOp =
3831 &MemOp.getOperand(MemRefBegin + X86::AddrBaseReg);
3832 if (!BaseOp->isReg()) // Can be an MO_FrameIndex
3833 return false;
3834
3835 if (MemOp.getOperand(MemRefBegin + X86::AddrScaleAmt).getImm() != 1)
3836 return false;
3837
3838 if (MemOp.getOperand(MemRefBegin + X86::AddrIndexReg).getReg() !=
3839 X86::NoRegister)
3840 return false;
3841
3842 const MachineOperand &DispMO = MemOp.getOperand(MemRefBegin + X86::AddrDisp);
3843
3844 // Displacement can be symbolic
3845 if (!DispMO.isImm())
3846 return false;
3847
3848 Offset = DispMO.getImm();
3849
3850 if (!BaseOp->isReg())
3851 return false;
3852
3853 OffsetIsScalable = false;
3854 // FIXME: Relying on memoperands() may not be right thing to do here. Check
3855 // with X86 maintainers, and fix it accordingly. For now, it is ok, since
3856 // there is no use of `Width` for X86 back-end at the moment.
3857 Width =
3858 !MemOp.memoperands_empty() ? MemOp.memoperands().front()->getSize() : 0;
3859 BaseOps.push_back(BaseOp);
3860 return true;
3861}
3862
3863static unsigned getStoreRegOpcode(Register SrcReg,
3864 const TargetRegisterClass *RC,
3865 bool IsStackAligned,
3866 const X86Subtarget &STI) {
3867 return getLoadStoreRegOpcode(SrcReg, RC, IsStackAligned, STI, false);
3868}
3869
3870static unsigned getLoadRegOpcode(Register DestReg,
3871 const TargetRegisterClass *RC,
3872 bool IsStackAligned, const X86Subtarget &STI) {
3873 return getLoadStoreRegOpcode(DestReg, RC, IsStackAligned, STI, true);
3874}
3875
3876void X86InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
3877 MachineBasicBlock::iterator MI,
3878 Register SrcReg, bool isKill, int FrameIdx,
3879 const TargetRegisterClass *RC,
3880 const TargetRegisterInfo *TRI) const {
3881 const MachineFunction &MF = *MBB.getParent();
3882 const MachineFrameInfo &MFI = MF.getFrameInfo();
3883 assert(MFI.getObjectSize(FrameIdx) >= TRI->getSpillSize(*RC) &&(static_cast <bool> (MFI.getObjectSize(FrameIdx) >= TRI
->getSpillSize(*RC) && "Stack slot too small for store"
) ? void (0) : __assert_fail ("MFI.getObjectSize(FrameIdx) >= TRI->getSpillSize(*RC) && \"Stack slot too small for store\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 3884, __extension__ __PRETTY_FUNCTION__))
3884 "Stack slot too small for store")(static_cast <bool> (MFI.getObjectSize(FrameIdx) >= TRI
->getSpillSize(*RC) && "Stack slot too small for store"
) ? void (0) : __assert_fail ("MFI.getObjectSize(FrameIdx) >= TRI->getSpillSize(*RC) && \"Stack slot too small for store\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 3884, __extension__ __PRETTY_FUNCTION__))
;
3885 if (RC->getID() == X86::TILERegClassID) {
3886 unsigned Opc = X86::TILESTORED;
3887 // tilestored %tmm, (%sp, %idx)
3888 MachineRegisterInfo &RegInfo = MBB.getParent()->getRegInfo();
3889 Register VirtReg = RegInfo.createVirtualRegister(&X86::GR64_NOSPRegClass);
3890 BuildMI(MBB, MI, DebugLoc(), get(X86::MOV64ri), VirtReg).addImm(64);
3891 MachineInstr *NewMI =
3892 addFrameReference(BuildMI(MBB, MI, DebugLoc(), get(Opc)), FrameIdx)
3893 .addReg(SrcReg, getKillRegState(isKill));
3894 MachineOperand &MO = NewMI->getOperand(2);
3895 MO.setReg(VirtReg);
3896 MO.setIsKill(true);
3897 } else {
3898 unsigned Alignment = std::max<uint32_t>(TRI->getSpillSize(*RC), 16);
3899 bool isAligned =
3900 (Subtarget.getFrameLowering()->getStackAlign() >= Alignment) ||
3901 (RI.canRealignStack(MF) && !MFI.isFixedObjectIndex(FrameIdx));
3902 unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, Subtarget);
3903 addFrameReference(BuildMI(MBB, MI, DebugLoc(), get(Opc)), FrameIdx)
3904 .addReg(SrcReg, getKillRegState(isKill));
3905 }
3906}
3907
3908void X86InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
3909 MachineBasicBlock::iterator MI,
3910 Register DestReg, int FrameIdx,
3911 const TargetRegisterClass *RC,
3912 const TargetRegisterInfo *TRI) const {
3913 if (RC->getID() == X86::TILERegClassID) {
3914 unsigned Opc = X86::TILELOADD;
3915 // tileloadd (%sp, %idx), %tmm
3916 MachineRegisterInfo &RegInfo = MBB.getParent()->getRegInfo();
3917 Register VirtReg = RegInfo.createVirtualRegister(&X86::GR64_NOSPRegClass);
3918 MachineInstr *NewMI =
Value stored to 'NewMI' during its initialization is never read
3919 BuildMI(MBB, MI, DebugLoc(), get(X86::MOV64ri), VirtReg).addImm(64);
3920 NewMI = addFrameReference(BuildMI(MBB, MI, DebugLoc(), get(Opc), DestReg),
3921 FrameIdx);
3922 MachineOperand &MO = NewMI->getOperand(3);
3923 MO.setReg(VirtReg);
3924 MO.setIsKill(true);
3925 } else {
3926 const MachineFunction &MF = *MBB.getParent();
3927 const MachineFrameInfo &MFI = MF.getFrameInfo();
3928 unsigned Alignment = std::max<uint32_t>(TRI->getSpillSize(*RC), 16);
3929 bool isAligned =
3930 (Subtarget.getFrameLowering()->getStackAlign() >= Alignment) ||
3931 (RI.canRealignStack(MF) && !MFI.isFixedObjectIndex(FrameIdx));
3932 unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, Subtarget);
3933 addFrameReference(BuildMI(MBB, MI, DebugLoc(), get(Opc), DestReg),
3934 FrameIdx);
3935 }
3936}
3937
3938bool X86InstrInfo::analyzeCompare(const MachineInstr &MI, Register &SrcReg,
3939 Register &SrcReg2, int64_t &CmpMask,
3940 int64_t &CmpValue) const {
3941 switch (MI.getOpcode()) {
3942 default: break;
3943 case X86::CMP64ri32:
3944 case X86::CMP64ri8:
3945 case X86::CMP32ri:
3946 case X86::CMP32ri8:
3947 case X86::CMP16ri:
3948 case X86::CMP16ri8:
3949 case X86::CMP8ri:
3950 SrcReg = MI.getOperand(0).getReg();
3951 SrcReg2 = 0;
3952 if (MI.getOperand(1).isImm()) {
3953 CmpMask = ~0;
3954 CmpValue = MI.getOperand(1).getImm();
3955 } else {
3956 CmpMask = CmpValue = 0;
3957 }
3958 return true;
3959 // A SUB can be used to perform comparison.
3960 case X86::SUB64rm:
3961 case X86::SUB32rm:
3962 case X86::SUB16rm:
3963 case X86::SUB8rm:
3964 SrcReg = MI.getOperand(1).getReg();
3965 SrcReg2 = 0;
3966 CmpMask = 0;
3967 CmpValue = 0;
3968 return true;
3969 case X86::SUB64rr:
3970 case X86::SUB32rr:
3971 case X86::SUB16rr:
3972 case X86::SUB8rr:
3973 SrcReg = MI.getOperand(1).getReg();
3974 SrcReg2 = MI.getOperand(2).getReg();
3975 CmpMask = 0;
3976 CmpValue = 0;
3977 return true;
3978 case X86::SUB64ri32:
3979 case X86::SUB64ri8:
3980 case X86::SUB32ri:
3981 case X86::SUB32ri8:
3982 case X86::SUB16ri:
3983 case X86::SUB16ri8:
3984 case X86::SUB8ri:
3985 SrcReg = MI.getOperand(1).getReg();
3986 SrcReg2 = 0;
3987 if (MI.getOperand(2).isImm()) {
3988 CmpMask = ~0;
3989 CmpValue = MI.getOperand(2).getImm();
3990 } else {
3991 CmpMask = CmpValue = 0;
3992 }
3993 return true;
3994 case X86::CMP64rr:
3995 case X86::CMP32rr:
3996 case X86::CMP16rr:
3997 case X86::CMP8rr:
3998 SrcReg = MI.getOperand(0).getReg();
3999 SrcReg2 = MI.getOperand(1).getReg();
4000 CmpMask = 0;
4001 CmpValue = 0;
4002 return true;
4003 case X86::TEST8rr:
4004 case X86::TEST16rr:
4005 case X86::TEST32rr:
4006 case X86::TEST64rr:
4007 SrcReg = MI.getOperand(0).getReg();
4008 if (MI.getOperand(1).getReg() != SrcReg)
4009 return false;
4010 // Compare against zero.
4011 SrcReg2 = 0;
4012 CmpMask = ~0;
4013 CmpValue = 0;
4014 return true;
4015 }
4016 return false;
4017}
4018
4019/// Check whether the first instruction, whose only
4020/// purpose is to update flags, can be made redundant.
4021/// CMPrr can be made redundant by SUBrr if the operands are the same.
4022/// This function can be extended later on.
4023/// SrcReg, SrcRegs: register operands for FlagI.
4024/// ImmValue: immediate for FlagI if it takes an immediate.
4025inline static bool isRedundantFlagInstr(const MachineInstr &FlagI,
4026 Register SrcReg, Register SrcReg2,
4027 int64_t ImmMask, int64_t ImmValue,
4028 const MachineInstr &OI) {
4029 if (((FlagI.getOpcode() == X86::CMP64rr && OI.getOpcode() == X86::SUB64rr) ||
4030 (FlagI.getOpcode() == X86::CMP32rr && OI.getOpcode() == X86::SUB32rr) ||
4031 (FlagI.getOpcode() == X86::CMP16rr && OI.getOpcode() == X86::SUB16rr) ||
4032 (FlagI.getOpcode() == X86::CMP8rr && OI.getOpcode() == X86::SUB8rr)) &&
4033 ((OI.getOperand(1).getReg() == SrcReg &&
4034 OI.getOperand(2).getReg() == SrcReg2) ||
4035 (OI.getOperand(1).getReg() == SrcReg2 &&
4036 OI.getOperand(2).getReg() == SrcReg)))
4037 return true;
4038
4039 if (ImmMask != 0 &&
4040 ((FlagI.getOpcode() == X86::CMP64ri32 &&
4041 OI.getOpcode() == X86::SUB64ri32) ||
4042 (FlagI.getOpcode() == X86::CMP64ri8 &&
4043 OI.getOpcode() == X86::SUB64ri8) ||
4044 (FlagI.getOpcode() == X86::CMP32ri && OI.getOpcode() == X86::SUB32ri) ||
4045 (FlagI.getOpcode() == X86::CMP32ri8 &&
4046 OI.getOpcode() == X86::SUB32ri8) ||
4047 (FlagI.getOpcode() == X86::CMP16ri && OI.getOpcode() == X86::SUB16ri) ||
4048 (FlagI.getOpcode() == X86::CMP16ri8 &&
4049 OI.getOpcode() == X86::SUB16ri8) ||
4050 (FlagI.getOpcode() == X86::CMP8ri && OI.getOpcode() == X86::SUB8ri)) &&
4051 OI.getOperand(1).getReg() == SrcReg &&
4052 OI.getOperand(2).getImm() == ImmValue)
4053 return true;
4054 return false;
4055}
4056
4057/// Check whether the definition can be converted
4058/// to remove a comparison against zero.
4059inline static bool isDefConvertible(const MachineInstr &MI, bool &NoSignFlag,
4060 bool &ClearsOverflowFlag) {
4061 NoSignFlag = false;
4062 ClearsOverflowFlag = false;
4063
4064 switch (MI.getOpcode()) {
4065 default: return false;
4066
4067 // The shift instructions only modify ZF if their shift count is non-zero.
4068 // N.B.: The processor truncates the shift count depending on the encoding.
4069 case X86::SAR8ri: case X86::SAR16ri: case X86::SAR32ri:case X86::SAR64ri:
4070 case X86::SHR8ri: case X86::SHR16ri: case X86::SHR32ri:case X86::SHR64ri:
4071 return getTruncatedShiftCount(MI, 2) != 0;
4072
4073 // Some left shift instructions can be turned into LEA instructions but only
4074 // if their flags aren't used. Avoid transforming such instructions.
4075 case X86::SHL8ri: case X86::SHL16ri: case X86::SHL32ri:case X86::SHL64ri:{
4076 unsigned ShAmt = getTruncatedShiftCount(MI, 2);
4077 if (isTruncatedShiftCountForLEA(ShAmt)) return false;
4078 return ShAmt != 0;
4079 }
4080
4081 case X86::SHRD16rri8:case X86::SHRD32rri8:case X86::SHRD64rri8:
4082 case X86::SHLD16rri8:case X86::SHLD32rri8:case X86::SHLD64rri8:
4083 return getTruncatedShiftCount(MI, 3) != 0;
4084
4085 case X86::SUB64ri32: case X86::SUB64ri8: case X86::SUB32ri:
4086 case X86::SUB32ri8: case X86::SUB16ri: case X86::SUB16ri8:
4087 case X86::SUB8ri: case X86::SUB64rr: case X86::SUB32rr:
4088 case X86::SUB16rr: case X86::SUB8rr: case X86::SUB64rm:
4089 case X86::SUB32rm: case X86::SUB16rm: case X86::SUB8rm:
4090 case X86::DEC64r: case X86::DEC32r: case X86::DEC16r: case X86::DEC8r:
4091 case X86::ADD64ri32: case X86::ADD64ri8: case X86::ADD32ri:
4092 case X86::ADD32ri8: case X86::ADD16ri: case X86::ADD16ri8:
4093 case X86::ADD8ri: case X86::ADD64rr: case X86::ADD32rr:
4094 case X86::ADD16rr: case X86::ADD8rr: case X86::ADD64rm:
4095 case X86::ADD32rm: case X86::ADD16rm: case X86::ADD8rm:
4096 case X86::INC64r: case X86::INC32r: case X86::INC16r: case X86::INC8r:
4097 case X86::ADC64ri32: case X86::ADC64ri8: case X86::ADC32ri:
4098 case X86::ADC32ri8: case X86::ADC16ri: case X86::ADC16ri8:
4099 case X86::ADC8ri: case X86::ADC64rr: case X86::ADC32rr:
4100 case X86::ADC16rr: case X86::ADC8rr: case X86::ADC64rm:
4101 case X86::ADC32rm: case X86::ADC16rm: case X86::ADC8rm:
4102 case X86::SBB64ri32: case X86::SBB64ri8: case X86::SBB32ri:
4103 case X86::SBB32ri8: case X86::SBB16ri: case X86::SBB16ri8:
4104 case X86::SBB8ri: case X86::SBB64rr: case X86::SBB32rr:
4105 case X86::SBB16rr: case X86::SBB8rr: case X86::SBB64rm:
4106 case X86::SBB32rm: case X86::SBB16rm: case X86::SBB8rm:
4107 case X86::NEG8r: case X86::NEG16r: case X86::NEG32r: case X86::NEG64r:
4108 case X86::SAR8r1: case X86::SAR16r1: case X86::SAR32r1:case X86::SAR64r1:
4109 case X86::SHR8r1: case X86::SHR16r1: case X86::SHR32r1:case X86::SHR64r1:
4110 case X86::SHL8r1: case X86::SHL16r1: case X86::SHL32r1:case X86::SHL64r1:
4111 case X86::LZCNT16rr: case X86::LZCNT16rm:
4112 case X86::LZCNT32rr: case X86::LZCNT32rm:
4113 case X86::LZCNT64rr: case X86::LZCNT64rm:
4114 case X86::POPCNT16rr:case X86::POPCNT16rm:
4115 case X86::POPCNT32rr:case X86::POPCNT32rm:
4116 case X86::POPCNT64rr:case X86::POPCNT64rm:
4117 case X86::TZCNT16rr: case X86::TZCNT16rm:
4118 case X86::TZCNT32rr: case X86::TZCNT32rm:
4119 case X86::TZCNT64rr: case X86::TZCNT64rm:
4120 return true;
4121 case X86::AND64ri32: case X86::AND64ri8: case X86::AND32ri:
4122 case X86::AND32ri8: case X86::AND16ri: case X86::AND16ri8:
4123 case X86::AND8ri: case X86::AND64rr: case X86::AND32rr:
4124 case X86::AND16rr: case X86::AND8rr: case X86::AND64rm:
4125 case X86::AND32rm: case X86::AND16rm: case X86::AND8rm:
4126 case X86::XOR64ri32: case X86::XOR64ri8: case X86::XOR32ri:
4127 case X86::XOR32ri8: case X86::XOR16ri: case X86::XOR16ri8:
4128 case X86::XOR8ri: case X86::XOR64rr: case X86::XOR32rr:
4129 case X86::XOR16rr: case X86::XOR8rr: case X86::XOR64rm:
4130 case X86::XOR32rm: case X86::XOR16rm: case X86::XOR8rm:
4131 case X86::OR64ri32: case X86::OR64ri8: case X86::OR32ri:
4132 case X86::OR32ri8: case X86::OR16ri: case X86::OR16ri8:
4133 case X86::OR8ri: case X86::OR64rr: case X86::OR32rr:
4134 case X86::OR16rr: case X86::OR8rr: case X86::OR64rm:
4135 case X86::OR32rm: case X86::OR16rm: case X86::OR8rm:
4136 case X86::ANDN32rr: case X86::ANDN32rm:
4137 case X86::ANDN64rr: case X86::ANDN64rm:
4138 case X86::BLSI32rr: case X86::BLSI32rm:
4139 case X86::BLSI64rr: case X86::BLSI64rm:
4140 case X86::BLSMSK32rr: case X86::BLSMSK32rm:
4141 case X86::BLSMSK64rr: case X86::BLSMSK64rm:
4142 case X86::BLSR32rr: case X86::BLSR32rm:
4143 case X86::BLSR64rr: case X86::BLSR64rm:
4144 case X86::BLCFILL32rr: case X86::BLCFILL32rm:
4145 case X86::BLCFILL64rr: case X86::BLCFILL64rm:
4146 case X86::BLCI32rr: case X86::BLCI32rm:
4147 case X86::BLCI64rr: case X86::BLCI64rm:
4148 case X86::BLCIC32rr: case X86::BLCIC32rm:
4149 case X86::BLCIC64rr: case X86::BLCIC64rm:
4150 case X86::BLCMSK32rr: case X86::BLCMSK32rm:
4151 case X86::BLCMSK64rr: case X86::BLCMSK64rm:
4152 case X86::BLCS32rr: case X86::BLCS32rm:
4153 case X86::BLCS64rr: case X86::BLCS64rm:
4154 case X86::BLSFILL32rr: case X86::BLSFILL32rm:
4155 case X86::BLSFILL64rr: case X86::BLSFILL64rm:
4156 case X86::BLSIC32rr: case X86::BLSIC32rm:
4157 case X86::BLSIC64rr: case X86::BLSIC64rm:
4158 case X86::BZHI32rr: case X86::BZHI32rm:
4159 case X86::BZHI64rr: case X86::BZHI64rm:
4160 case X86::T1MSKC32rr: case X86::T1MSKC32rm:
4161 case X86::T1MSKC64rr: case X86::T1MSKC64rm:
4162 case X86::TZMSK32rr: case X86::TZMSK32rm:
4163 case X86::TZMSK64rr: case X86::TZMSK64rm:
4164 // These instructions clear the overflow flag just like TEST.
4165 // FIXME: These are not the only instructions in this switch that clear the
4166 // overflow flag.
4167 ClearsOverflowFlag = true;
4168 return true;
4169 case X86::BEXTR32rr: case X86::BEXTR64rr:
4170 case X86::BEXTR32rm: case X86::BEXTR64rm:
4171 case X86::BEXTRI32ri: case X86::BEXTRI32mi:
4172 case X86::BEXTRI64ri: case X86::BEXTRI64mi:
4173 // BEXTR doesn't update the sign flag so we can't use it. It does clear
4174 // the overflow flag, but that's not useful without the sign flag.
4175 NoSignFlag = true;
4176 return true;
4177 }
4178}
4179
4180/// Check whether the use can be converted to remove a comparison against zero.
4181static X86::CondCode isUseDefConvertible(const MachineInstr &MI) {
4182 switch (MI.getOpcode()) {
4183 default: return X86::COND_INVALID;
4184 case X86::NEG8r:
4185 case X86::NEG16r:
4186 case X86::NEG32r:
4187 case X86::NEG64r:
4188 return X86::COND_AE;
4189 case X86::LZCNT16rr:
4190 case X86::LZCNT32rr:
4191 case X86::LZCNT64rr:
4192 return X86::COND_B;
4193 case X86::POPCNT16rr:
4194 case X86::POPCNT32rr:
4195 case X86::POPCNT64rr:
4196 return X86::COND_E;
4197 case X86::TZCNT16rr:
4198 case X86::TZCNT32rr:
4199 case X86::TZCNT64rr:
4200 return X86::COND_B;
4201 case X86::BSF16rr:
4202 case X86::BSF32rr:
4203 case X86::BSF64rr:
4204 case X86::BSR16rr:
4205 case X86::BSR32rr:
4206 case X86::BSR64rr:
4207 return X86::COND_E;
4208 case X86::BLSI32rr:
4209 case X86::BLSI64rr:
4210 return X86::COND_AE;
4211 case X86::BLSR32rr:
4212 case X86::BLSR64rr:
4213 case X86::BLSMSK32rr:
4214 case X86::BLSMSK64rr:
4215 return X86::COND_B;
4216 // TODO: TBM instructions.
4217 }
4218}
4219
4220/// Check if there exists an earlier instruction that
4221/// operates on the same source operands and sets flags in the same way as
4222/// Compare; remove Compare if possible.
4223bool X86InstrInfo::optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg,
4224 Register SrcReg2, int64_t CmpMask,
4225 int64_t CmpValue,
4226 const MachineRegisterInfo *MRI) const {
4227 // Check whether we can replace SUB with CMP.
4228 switch (CmpInstr.getOpcode()) {
4229 default: break;
4230 case X86::SUB64ri32:
4231 case X86::SUB64ri8:
4232 case X86::SUB32ri:
4233 case X86::SUB32ri8:
4234 case X86::SUB16ri:
4235 case X86::SUB16ri8:
4236 case X86::SUB8ri:
4237 case X86::SUB64rm:
4238 case X86::SUB32rm:
4239 case X86::SUB16rm:
4240 case X86::SUB8rm:
4241 case X86::SUB64rr:
4242 case X86::SUB32rr:
4243 case X86::SUB16rr:
4244 case X86::SUB8rr: {
4245 if (!MRI->use_nodbg_empty(CmpInstr.getOperand(0).getReg()))
4246 return false;
4247 // There is no use of the destination register, we can replace SUB with CMP.
4248 unsigned NewOpcode = 0;
4249 switch (CmpInstr.getOpcode()) {
4250 default: llvm_unreachable("Unreachable!")::llvm::llvm_unreachable_internal("Unreachable!", "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 4250)
;
4251 case X86::SUB64rm: NewOpcode = X86::CMP64rm; break;
4252 case X86::SUB32rm: NewOpcode = X86::CMP32rm; break;
4253 case X86::SUB16rm: NewOpcode = X86::CMP16rm; break;
4254 case X86::SUB8rm: NewOpcode = X86::CMP8rm; break;
4255 case X86::SUB64rr: NewOpcode = X86::CMP64rr; break;
4256 case X86::SUB32rr: NewOpcode = X86::CMP32rr; break;
4257 case X86::SUB16rr: NewOpcode = X86::CMP16rr; break;
4258 case X86::SUB8rr: NewOpcode = X86::CMP8rr; break;
4259 case X86::SUB64ri32: NewOpcode = X86::CMP64ri32; break;
4260 case X86::SUB64ri8: NewOpcode = X86::CMP64ri8; break;
4261 case X86::SUB32ri: NewOpcode = X86::CMP32ri; break;
4262 case X86::SUB32ri8: NewOpcode = X86::CMP32ri8; break;
4263 case X86::SUB16ri: NewOpcode = X86::CMP16ri; break;
4264 case X86::SUB16ri8: NewOpcode = X86::CMP16ri8; break;
4265 case X86::SUB8ri: NewOpcode = X86::CMP8ri; break;
4266 }
4267 CmpInstr.setDesc(get(NewOpcode));
4268 CmpInstr.RemoveOperand(0);
4269 // Mutating this instruction invalidates any debug data associated with it.
4270 CmpInstr.dropDebugNumber();
4271 // Fall through to optimize Cmp if Cmp is CMPrr or CMPri.
4272 if (NewOpcode == X86::CMP64rm || NewOpcode == X86::CMP32rm ||
4273 NewOpcode == X86::CMP16rm || NewOpcode == X86::CMP8rm)
4274 return false;
4275 }
4276 }
4277
4278 // Get the unique definition of SrcReg.
4279 MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg);
4280 if (!MI) return false;
4281
4282 // CmpInstr is the first instruction of the BB.
4283 MachineBasicBlock::iterator I = CmpInstr, Def = MI;
4284
4285 // If we are comparing against zero, check whether we can use MI to update
4286 // EFLAGS. If MI is not in the same BB as CmpInstr, do not optimize.
4287 bool IsCmpZero = (CmpMask != 0 && CmpValue == 0);
4288 if (IsCmpZero && MI->getParent() != CmpInstr.getParent())
4289 return false;
4290
4291 // If we have a use of the source register between the def and our compare
4292 // instruction we can eliminate the compare iff the use sets EFLAGS in the
4293 // right way.
4294 bool ShouldUpdateCC = false;
4295 bool NoSignFlag = false;
4296 bool ClearsOverflowFlag = false;
4297 X86::CondCode NewCC = X86::COND_INVALID;
4298 if (IsCmpZero && !isDefConvertible(*MI, NoSignFlag, ClearsOverflowFlag)) {
4299 // Scan forward from the use until we hit the use we're looking for or the
4300 // compare instruction.
4301 for (MachineBasicBlock::iterator J = MI;; ++J) {
4302 // Do we have a convertible instruction?
4303 NewCC = isUseDefConvertible(*J);
4304 if (NewCC != X86::COND_INVALID && J->getOperand(1).isReg() &&
4305 J->getOperand(1).getReg() == SrcReg) {
4306 assert(J->definesRegister(X86::EFLAGS) && "Must be an EFLAGS def!")(static_cast <bool> (J->definesRegister(X86::EFLAGS)
&& "Must be an EFLAGS def!") ? void (0) : __assert_fail
("J->definesRegister(X86::EFLAGS) && \"Must be an EFLAGS def!\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 4306, __extension__ __PRETTY_FUNCTION__))
;
4307 ShouldUpdateCC = true; // Update CC later on.
4308 // This is not a def of SrcReg, but still a def of EFLAGS. Keep going
4309 // with the new def.
4310 Def = J;
4311 MI = &*Def;
4312 break;
4313 }
4314
4315 if (J == I)
4316 return false;
4317 }
4318 }
4319
4320 // We are searching for an earlier instruction that can make CmpInstr
4321 // redundant and that instruction will be saved in Sub.
4322 MachineInstr *Sub = nullptr;
4323 const TargetRegisterInfo *TRI = &getRegisterInfo();
4324
4325 // We iterate backward, starting from the instruction before CmpInstr and
4326 // stop when reaching the definition of a source register or done with the BB.
4327 // RI points to the instruction before CmpInstr.
4328 // If the definition is in this basic block, RE points to the definition;
4329 // otherwise, RE is the rend of the basic block.
4330 MachineBasicBlock::reverse_iterator
4331 RI = ++I.getReverse(),
4332 RE = CmpInstr.getParent() == MI->getParent()
4333 ? Def.getReverse() /* points to MI */
4334 : CmpInstr.getParent()->rend();
4335 MachineInstr *Movr0Inst = nullptr;
4336 for (; RI != RE; ++RI) {
4337 MachineInstr &Instr = *RI;
4338 // Check whether CmpInstr can be made redundant by the current instruction.
4339 if (!IsCmpZero && isRedundantFlagInstr(CmpInstr, SrcReg, SrcReg2, CmpMask,
4340 CmpValue, Instr)) {
4341 Sub = &Instr;
4342 break;
4343 }
4344
4345 if (Instr.modifiesRegister(X86::EFLAGS, TRI) ||
4346 Instr.readsRegister(X86::EFLAGS, TRI)) {
4347 // This instruction modifies or uses EFLAGS.
4348
4349 // MOV32r0 etc. are implemented with xor which clobbers condition code.
4350 // They are safe to move up, if the definition to EFLAGS is dead and
4351 // earlier instructions do not read or write EFLAGS.
4352 if (!Movr0Inst && Instr.getOpcode() == X86::MOV32r0 &&
4353 Instr.registerDefIsDead(X86::EFLAGS, TRI)) {
4354 Movr0Inst = &Instr;
4355 continue;
4356 }
4357
4358 // We can't remove CmpInstr.
4359 return false;
4360 }
4361 }
4362
4363 // Return false if no candidates exist.
4364 if (!IsCmpZero && !Sub)
4365 return false;
4366
4367 bool IsSwapped =
4368 (SrcReg2 != 0 && Sub && Sub->getOperand(1).getReg() == SrcReg2 &&
4369 Sub->getOperand(2).getReg() == SrcReg);
4370
4371 // Scan forward from the instruction after CmpInstr for uses of EFLAGS.
4372 // It is safe to remove CmpInstr if EFLAGS is redefined or killed.
4373 // If we are done with the basic block, we need to check whether EFLAGS is
4374 // live-out.
4375 bool IsSafe = false;
4376 SmallVector<std::pair<MachineInstr*, X86::CondCode>, 4> OpsToUpdate;
4377 MachineBasicBlock::iterator E = CmpInstr.getParent()->end();
4378 for (++I; I != E; ++I) {
4379 const MachineInstr &Instr = *I;
4380 bool ModifyEFLAGS = Instr.modifiesRegister(X86::EFLAGS, TRI);
4381 bool UseEFLAGS = Instr.readsRegister(X86::EFLAGS, TRI);
4382 // We should check the usage if this instruction uses and updates EFLAGS.
4383 if (!UseEFLAGS && ModifyEFLAGS) {
4384 // It is safe to remove CmpInstr if EFLAGS is updated again.
4385 IsSafe = true;
4386 break;
4387 }
4388 if (!UseEFLAGS && !ModifyEFLAGS)
4389 continue;
4390
4391 // EFLAGS is used by this instruction.
4392 X86::CondCode OldCC = X86::COND_INVALID;
4393 if (IsCmpZero || IsSwapped) {
4394 // We decode the condition code from opcode.
4395 if (Instr.isBranch())
4396 OldCC = X86::getCondFromBranch(Instr);
4397 else {
4398 OldCC = X86::getCondFromSETCC(Instr);
4399 if (OldCC == X86::COND_INVALID)
4400 OldCC = X86::getCondFromCMov(Instr);
4401 }
4402 if (OldCC == X86::COND_INVALID) return false;
4403 }
4404 X86::CondCode ReplacementCC = X86::COND_INVALID;
4405 if (IsCmpZero) {
4406 switch (OldCC) {
4407 default: break;
4408 case X86::COND_A: case X86::COND_AE:
4409 case X86::COND_B: case X86::COND_BE:
4410 // CF is used, we can't perform this optimization.
4411 return false;
4412 case X86::COND_G: case X86::COND_GE:
4413 case X86::COND_L: case X86::COND_LE:
4414 case X86::COND_O: case X86::COND_NO:
4415 // If OF is used, the instruction needs to clear it like CmpZero does.
4416 if (!ClearsOverflowFlag)
4417 return false;
4418 break;
4419 case X86::COND_S: case X86::COND_NS:
4420 // If SF is used, but the instruction doesn't update the SF, then we
4421 // can't do the optimization.
4422 if (NoSignFlag)
4423 return false;
4424 break;
4425 }
4426
4427 // If we're updating the condition code check if we have to reverse the
4428 // condition.
4429 if (ShouldUpdateCC)
4430 switch (OldCC) {
4431 default:
4432 return false;
4433 case X86::COND_E:
4434 ReplacementCC = NewCC;
4435 break;
4436 case X86::COND_NE:
4437 ReplacementCC = GetOppositeBranchCondition(NewCC);
4438 break;
4439 }
4440 } else if (IsSwapped) {
4441 // If we have SUB(r1, r2) and CMP(r2, r1), the condition code needs
4442 // to be changed from r2 > r1 to r1 < r2, from r2 < r1 to r1 > r2, etc.
4443 // We swap the condition code and synthesize the new opcode.
4444 ReplacementCC = getSwappedCondition(OldCC);
4445 if (ReplacementCC == X86::COND_INVALID) return false;
4446 }
4447
4448 if ((ShouldUpdateCC || IsSwapped) && ReplacementCC != OldCC) {
4449 // Push the MachineInstr to OpsToUpdate.
4450 // If it is safe to remove CmpInstr, the condition code of these
4451 // instructions will be modified.
4452 OpsToUpdate.push_back(std::make_pair(&*I, ReplacementCC));
4453 }
4454 if (ModifyEFLAGS || Instr.killsRegister(X86::EFLAGS, TRI)) {
4455 // It is safe to remove CmpInstr if EFLAGS is updated again or killed.
4456 IsSafe = true;
4457 break;
4458 }
4459 }
4460
4461 // If EFLAGS is not killed nor re-defined, we should check whether it is
4462 // live-out. If it is live-out, do not optimize.
4463 if ((IsCmpZero || IsSwapped) && !IsSafe) {
4464 MachineBasicBlock *MBB = CmpInstr.getParent();
4465 for (MachineBasicBlock *Successor : MBB->successors())
4466 if (Successor->isLiveIn(X86::EFLAGS))
4467 return false;
4468 }
4469
4470 // The instruction to be updated is either Sub or MI.
4471 Sub = IsCmpZero ? MI : Sub;
4472 // Move Movr0Inst to the appropriate place before Sub.
4473 if (Movr0Inst) {
4474 // Look backwards until we find a def that doesn't use the current EFLAGS.
4475 Def = Sub;
4476 MachineBasicBlock::reverse_iterator InsertI = Def.getReverse(),
4477 InsertE = Sub->getParent()->rend();
4478 for (; InsertI != InsertE; ++InsertI) {
4479 MachineInstr *Instr = &*InsertI;
4480 if (!Instr->readsRegister(X86::EFLAGS, TRI) &&
4481 Instr->modifiesRegister(X86::EFLAGS, TRI)) {
4482 Sub->getParent()->remove(Movr0Inst);
4483 Instr->getParent()->insert(MachineBasicBlock::iterator(Instr),
4484 Movr0Inst);
4485 break;
4486 }
4487 }
4488 if (InsertI == InsertE)
4489 return false;
4490 }
4491
4492 // Make sure Sub instruction defines EFLAGS and mark the def live.
4493 MachineOperand *FlagDef = Sub->findRegisterDefOperand(X86::EFLAGS);
4494 assert(FlagDef && "Unable to locate a def EFLAGS operand")(static_cast <bool> (FlagDef && "Unable to locate a def EFLAGS operand"
) ? void (0) : __assert_fail ("FlagDef && \"Unable to locate a def EFLAGS operand\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 4494, __extension__ __PRETTY_FUNCTION__))
;
4495 FlagDef->setIsDead(false);
4496
4497 CmpInstr.eraseFromParent();
4498
4499 // Modify the condition code of instructions in OpsToUpdate.
4500 for (auto &Op : OpsToUpdate) {
4501 Op.first->getOperand(Op.first->getDesc().getNumOperands() - 1)
4502 .setImm(Op.second);
4503 }
4504 return true;
4505}
4506
4507/// Try to remove the load by folding it to a register
4508/// operand at the use. We fold the load instructions if load defines a virtual
4509/// register, the virtual register is used once in the same BB, and the
4510/// instructions in-between do not load or store, and have no side effects.
4511MachineInstr *X86InstrInfo::optimizeLoadInstr(MachineInstr &MI,
4512 const MachineRegisterInfo *MRI,
4513 Register &FoldAsLoadDefReg,
4514 MachineInstr *&DefMI) const {
4515 // Check whether we can move DefMI here.
4516 DefMI = MRI->getVRegDef(FoldAsLoadDefReg);
4517 assert(DefMI)(static_cast <bool> (DefMI) ? void (0) : __assert_fail (
"DefMI", "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 4517, __extension__ __PRETTY_FUNCTION__))
;
4518 bool SawStore = false;
4519 if (!DefMI->isSafeToMove(nullptr, SawStore))
4520 return nullptr;
4521
4522 // Collect information about virtual register operands of MI.
4523 SmallVector<unsigned, 1> SrcOperandIds;
4524 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
4525 MachineOperand &MO = MI.getOperand(i);
4526 if (!MO.isReg())
4527 continue;
4528 Register Reg = MO.getReg();
4529 if (Reg != FoldAsLoadDefReg)
4530 continue;
4531 // Do not fold if we have a subreg use or a def.
4532 if (MO.getSubReg() || MO.isDef())
4533 return nullptr;
4534 SrcOperandIds.push_back(i);
4535 }
4536 if (SrcOperandIds.empty())
4537 return nullptr;
4538
4539 // Check whether we can fold the def into SrcOperandId.
4540 if (MachineInstr *FoldMI = foldMemoryOperand(MI, SrcOperandIds, *DefMI)) {
4541 FoldAsLoadDefReg = 0;
4542 return FoldMI;
4543 }
4544
4545 return nullptr;
4546}
4547
4548/// Expand a single-def pseudo instruction to a two-addr
4549/// instruction with two undef reads of the register being defined.
4550/// This is used for mapping:
4551/// %xmm4 = V_SET0
4552/// to:
4553/// %xmm4 = PXORrr undef %xmm4, undef %xmm4
4554///
4555static bool Expand2AddrUndef(MachineInstrBuilder &MIB,
4556 const MCInstrDesc &Desc) {
4557 assert(Desc.getNumOperands() == 3 && "Expected two-addr instruction.")(static_cast <bool> (Desc.getNumOperands() == 3 &&
"Expected two-addr instruction.") ? void (0) : __assert_fail
("Desc.getNumOperands() == 3 && \"Expected two-addr instruction.\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 4557, __extension__ __PRETTY_FUNCTION__))
;
4558 Register Reg = MIB.getReg(0);
4559 MIB->setDesc(Desc);
4560
4561 // MachineInstr::addOperand() will insert explicit operands before any
4562 // implicit operands.
4563 MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef);
4564 // But we don't trust that.
4565 assert(MIB.getReg(1) == Reg &&(static_cast <bool> (MIB.getReg(1) == Reg && MIB
.getReg(2) == Reg && "Misplaced operand") ? void (0) :
__assert_fail ("MIB.getReg(1) == Reg && MIB.getReg(2) == Reg && \"Misplaced operand\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 4566, __extension__ __PRETTY_FUNCTION__))
4566 MIB.getReg(2) == Reg && "Misplaced operand")(static_cast <bool> (MIB.getReg(1) == Reg && MIB
.getReg(2) == Reg && "Misplaced operand") ? void (0) :
__assert_fail ("MIB.getReg(1) == Reg && MIB.getReg(2) == Reg && \"Misplaced operand\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 4566, __extension__ __PRETTY_FUNCTION__))
;
4567 return true;
4568}
4569
4570/// Expand a single-def pseudo instruction to a two-addr
4571/// instruction with two %k0 reads.
4572/// This is used for mapping:
4573/// %k4 = K_SET1
4574/// to:
4575/// %k4 = KXNORrr %k0, %k0
4576static bool Expand2AddrKreg(MachineInstrBuilder &MIB, const MCInstrDesc &Desc,
4577 Register Reg) {
4578 assert(Desc.getNumOperands() == 3 && "Expected two-addr instruction.")(static_cast <bool> (Desc.getNumOperands() == 3 &&
"Expected two-addr instruction.") ? void (0) : __assert_fail
("Desc.getNumOperands() == 3 && \"Expected two-addr instruction.\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 4578, __extension__ __PRETTY_FUNCTION__))
;
4579 MIB->setDesc(Desc);
4580 MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef);
4581 return true;
4582}
4583
4584static bool expandMOV32r1(MachineInstrBuilder &MIB, const TargetInstrInfo &TII,
4585 bool MinusOne) {
4586 MachineBasicBlock &MBB = *MIB->getParent();
4587 const DebugLoc &DL = MIB->getDebugLoc();
4588 Register Reg = MIB.getReg(0);
4589
4590 // Insert the XOR.
4591 BuildMI(MBB, MIB.getInstr(), DL, TII.get(X86::XOR32rr), Reg)
4592 .addReg(Reg, RegState::Undef)
4593 .addReg(Reg, RegState::Undef);
4594
4595 // Turn the pseudo into an INC or DEC.
4596 MIB->setDesc(TII.get(MinusOne ? X86::DEC32r : X86::INC32r));
4597 MIB.addReg(Reg);
4598
4599 return true;
4600}
4601
4602static bool ExpandMOVImmSExti8(MachineInstrBuilder &MIB,
4603 const TargetInstrInfo &TII,
4604 const X86Subtarget &Subtarget) {
4605 MachineBasicBlock &MBB = *MIB->getParent();
4606 const DebugLoc &DL = MIB->getDebugLoc();
4607 int64_t Imm = MIB->getOperand(1).getImm();
4608 assert(Imm != 0 && "Using push/pop for 0 is not efficient.")(static_cast <bool> (Imm != 0 && "Using push/pop for 0 is not efficient."
) ? void (0) : __assert_fail ("Imm != 0 && \"Using push/pop for 0 is not efficient.\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 4608, __extension__ __PRETTY_FUNCTION__))
;
4609 MachineBasicBlock::iterator I = MIB.getInstr();
4610
4611 int StackAdjustment;
4612
4613 if (Subtarget.is64Bit()) {
4614 assert(MIB->getOpcode() == X86::MOV64ImmSExti8 ||(static_cast <bool> (MIB->getOpcode() == X86::MOV64ImmSExti8
|| MIB->getOpcode() == X86::MOV32ImmSExti8) ? void (0) : __assert_fail
("MIB->getOpcode() == X86::MOV64ImmSExti8 || MIB->getOpcode() == X86::MOV32ImmSExti8"
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 4615, __extension__ __PRETTY_FUNCTION__))
4615 MIB->getOpcode() == X86::MOV32ImmSExti8)(static_cast <bool> (MIB->getOpcode() == X86::MOV64ImmSExti8
|| MIB->getOpcode() == X86::MOV32ImmSExti8) ? void (0) : __assert_fail
("MIB->getOpcode() == X86::MOV64ImmSExti8 || MIB->getOpcode() == X86::MOV32ImmSExti8"
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 4615, __extension__ __PRETTY_FUNCTION__))
;
4616
4617 // Can't use push/pop lowering if the function might write to the red zone.
4618 X86MachineFunctionInfo *X86FI =
4619 MBB.getParent()->getInfo<X86MachineFunctionInfo>();
4620 if (X86FI->getUsesRedZone()) {
4621 MIB->setDesc(TII.get(MIB->getOpcode() ==
4622 X86::MOV32ImmSExti8 ? X86::MOV32ri : X86::MOV64ri));
4623 return true;
4624 }
4625
4626 // 64-bit mode doesn't have 32-bit push/pop, so use 64-bit operations and
4627 // widen the register if necessary.
4628 StackAdjustment = 8;
4629 BuildMI(MBB, I, DL, TII.get(X86::PUSH64i8)).addImm(Imm);
4630 MIB->setDesc(TII.get(X86::POP64r));
4631 MIB->getOperand(0)
4632 .setReg(getX86SubSuperRegister(MIB.getReg(0), 64));
4633 } else {
4634 assert(MIB->getOpcode() == X86::MOV32ImmSExti8)(static_cast <bool> (MIB->getOpcode() == X86::MOV32ImmSExti8
) ? void (0) : __assert_fail ("MIB->getOpcode() == X86::MOV32ImmSExti8"
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 4634, __extension__ __PRETTY_FUNCTION__))
;
4635 StackAdjustment = 4;
4636 BuildMI(MBB, I, DL, TII.get(X86::PUSH32i8)).addImm(Imm);
4637 MIB->setDesc(TII.get(X86::POP32r));
4638 }
4639 MIB->RemoveOperand(1);
4640 MIB->addImplicitDefUseOperands(*MBB.getParent());
4641
4642 // Build CFI if necessary.
4643 MachineFunction &MF = *MBB.getParent();
4644 const X86FrameLowering *TFL = Subtarget.getFrameLowering();
4645 bool IsWin64Prologue = MF.getTarget().getMCAsmInfo()->usesWindowsCFI();
4646 bool NeedsDwarfCFI = !IsWin64Prologue && MF.needsFrameMoves();
4647 bool EmitCFI = !TFL->hasFP(MF) && NeedsDwarfCFI;
4648 if (EmitCFI) {
4649 TFL->BuildCFI(MBB, I, DL,
4650 MCCFIInstruction::createAdjustCfaOffset(nullptr, StackAdjustment));
4651 TFL->BuildCFI(MBB, std::next(I), DL,
4652 MCCFIInstruction::createAdjustCfaOffset(nullptr, -StackAdjustment));
4653 }
4654
4655 return true;
4656}
4657
4658// LoadStackGuard has so far only been implemented for 64-bit MachO. Different
4659// code sequence is needed for other targets.
4660static void expandLoadStackGuard(MachineInstrBuilder &MIB,
4661 const TargetInstrInfo &TII) {
4662 MachineBasicBlock &MBB = *MIB->getParent();
4663 const DebugLoc &DL = MIB->getDebugLoc();
4664 Register Reg = MIB.getReg(0);
4665 const GlobalValue *GV =
4666 cast<GlobalValue>((*MIB->memoperands_begin())->getValue());
4667 auto Flags = MachineMemOperand::MOLoad |
4668 MachineMemOperand::MODereferenceable |
4669 MachineMemOperand::MOInvariant;
4670 MachineMemOperand *MMO = MBB.getParent()->getMachineMemOperand(
4671 MachinePointerInfo::getGOT(*MBB.getParent()), Flags, 8, Align(8));
4672 MachineBasicBlock::iterator I = MIB.getInstr();
4673
4674 BuildMI(MBB, I, DL, TII.get(X86::MOV64rm), Reg).addReg(X86::RIP).addImm(1)
4675 .addReg(0).addGlobalAddress(GV, 0, X86II::MO_GOTPCREL).addReg(0)
4676 .addMemOperand(MMO);
4677 MIB->setDebugLoc(DL);
4678 MIB->setDesc(TII.get(X86::MOV64rm));
4679 MIB.addReg(Reg, RegState::Kill).addImm(1).addReg(0).addImm(0).addReg(0);
4680}
4681
4682static bool expandXorFP(MachineInstrBuilder &MIB, const TargetInstrInfo &TII) {
4683 MachineBasicBlock &MBB = *MIB->getParent();
4684 MachineFunction &MF = *MBB.getParent();
4685 const X86Subtarget &Subtarget = MF.getSubtarget<X86Subtarget>();
4686 const X86RegisterInfo *TRI = Subtarget.getRegisterInfo();
4687 unsigned XorOp =
4688 MIB->getOpcode() == X86::XOR64_FP ? X86::XOR64rr : X86::XOR32rr;
4689 MIB->setDesc(TII.get(XorOp));
4690 MIB.addReg(TRI->getFrameRegister(MF), RegState::Undef);
4691 return true;
4692}
4693
4694// This is used to handle spills for 128/256-bit registers when we have AVX512,
4695// but not VLX. If it uses an extended register we need to use an instruction
4696// that loads the lower 128/256-bit, but is available with only AVX512F.
4697static bool expandNOVLXLoad(MachineInstrBuilder &MIB,
4698 const TargetRegisterInfo *TRI,
4699 const MCInstrDesc &LoadDesc,
4700 const MCInstrDesc &BroadcastDesc,
4701 unsigned SubIdx) {
4702 Register DestReg = MIB.getReg(0);
4703 // Check if DestReg is XMM16-31 or YMM16-31.
4704 if (TRI->getEncodingValue(DestReg) < 16) {
4705 // We can use a normal VEX encoded load.
4706 MIB->setDesc(LoadDesc);
4707 } else {
4708 // Use a 128/256-bit VBROADCAST instruction.
4709 MIB->setDesc(BroadcastDesc);
4710 // Change the destination to a 512-bit register.
4711 DestReg = TRI->getMatchingSuperReg(DestReg, SubIdx, &X86::VR512RegClass);
4712 MIB->getOperand(0).setReg(DestReg);
4713 }
4714 return true;
4715}
4716
4717// This is used to handle spills for 128/256-bit registers when we have AVX512,
4718// but not VLX. If it uses an extended register we need to use an instruction
4719// that stores the lower 128/256-bit, but is available with only AVX512F.
4720static bool expandNOVLXStore(MachineInstrBuilder &MIB,
4721 const TargetRegisterInfo *TRI,
4722 const MCInstrDesc &StoreDesc,
4723 const MCInstrDesc &ExtractDesc,
4724 unsigned SubIdx) {
4725 Register SrcReg = MIB.getReg(X86::AddrNumOperands);
4726 // Check if DestReg is XMM16-31 or YMM16-31.
4727 if (TRI->getEncodingValue(SrcReg) < 16) {
4728 // We can use a normal VEX encoded store.
4729 MIB->setDesc(StoreDesc);
4730 } else {
4731 // Use a VEXTRACTF instruction.
4732 MIB->setDesc(ExtractDesc);
4733 // Change the destination to a 512-bit register.
4734 SrcReg = TRI->getMatchingSuperReg(SrcReg, SubIdx, &X86::VR512RegClass);
4735 MIB->getOperand(X86::AddrNumOperands).setReg(SrcReg);
4736 MIB.addImm(0x0); // Append immediate to extract from the lower bits.
4737 }
4738
4739 return true;
4740}
4741
4742static bool expandSHXDROT(MachineInstrBuilder &MIB, const MCInstrDesc &Desc) {
4743 MIB->setDesc(Desc);
4744 int64_t ShiftAmt = MIB->getOperand(2).getImm();
4745 // Temporarily remove the immediate so we can add another source register.
4746 MIB->RemoveOperand(2);
4747 // Add the register. Don't copy the kill flag if there is one.
4748 MIB.addReg(MIB.getReg(1),
4749 getUndefRegState(MIB->getOperand(1).isUndef()));
4750 // Add back the immediate.
4751 MIB.addImm(ShiftAmt);
4752 return true;
4753}
4754
4755bool X86InstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
4756 bool HasAVX = Subtarget.hasAVX();
4757 MachineInstrBuilder MIB(*MI.getParent()->getParent(), MI);
4758 switch (MI.getOpcode()) {
4759 case X86::MOV32r0:
4760 return Expand2AddrUndef(MIB, get(X86::XOR32rr));
4761 case X86::MOV32r1:
4762 return expandMOV32r1(MIB, *this, /*MinusOne=*/ false);
4763 case X86::MOV32r_1:
4764 return expandMOV32r1(MIB, *this, /*MinusOne=*/ true);
4765 case X86::MOV32ImmSExti8:
4766 case X86::MOV64ImmSExti8:
4767 return ExpandMOVImmSExti8(MIB, *this, Subtarget);
4768 case X86::SETB_C32r:
4769 return Expand2AddrUndef(MIB, get(X86::SBB32rr));
4770 case X86::SETB_C64r:
4771 return Expand2AddrUndef(MIB, get(X86::SBB64rr));
4772 case X86::MMX_SET0:
4773 return Expand2AddrUndef(MIB, get(X86::MMX_PXORirr));
4774 case X86::V_SET0:
4775 case X86::FsFLD0SS:
4776 case X86::FsFLD0SD:
4777 case X86::FsFLD0F128:
4778 return Expand2AddrUndef(MIB, get(HasAVX ? X86::VXORPSrr : X86::XORPSrr));
4779 case X86::AVX_SET0: {
4780 assert(HasAVX && "AVX not supported")(static_cast <bool> (HasAVX && "AVX not supported"
) ? void (0) : __assert_fail ("HasAVX && \"AVX not supported\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 4780, __extension__ __PRETTY_FUNCTION__))
;
4781 const TargetRegisterInfo *TRI = &getRegisterInfo();
4782 Register SrcReg = MIB.getReg(0);
4783 Register XReg = TRI->getSubReg(SrcReg, X86::sub_xmm);
4784 MIB->getOperand(0).setReg(XReg);
4785 Expand2AddrUndef(MIB, get(X86::VXORPSrr));
4786 MIB.addReg(SrcReg, RegState::ImplicitDefine);
4787 return true;
4788 }
4789 case X86::AVX512_128_SET0:
4790 case X86::AVX512_FsFLD0SH:
4791 case X86::AVX512_FsFLD0SS:
4792 case X86::AVX512_FsFLD0SD:
4793 case X86::AVX512_FsFLD0F128: {
4794 bool HasVLX = Subtarget.hasVLX();
4795 Register SrcReg = MIB.getReg(0);
4796 const TargetRegisterInfo *TRI = &getRegisterInfo();
4797 if (HasVLX || TRI->getEncodingValue(SrcReg) < 16)
4798 return Expand2AddrUndef(MIB,
4799 get(HasVLX ? X86::VPXORDZ128rr : X86::VXORPSrr));
4800 // Extended register without VLX. Use a larger XOR.
4801 SrcReg =
4802 TRI->getMatchingSuperReg(SrcReg, X86::sub_xmm, &X86::VR512RegClass);
4803 MIB->getOperand(0).setReg(SrcReg);
4804 return Expand2AddrUndef(MIB, get(X86::VPXORDZrr));
4805 }
4806 case X86::AVX512_256_SET0:
4807 case X86::AVX512_512_SET0: {
4808 bool HasVLX = Subtarget.hasVLX();
4809 Register SrcReg = MIB.getReg(0);
4810 const TargetRegisterInfo *TRI = &getRegisterInfo();
4811 if (HasVLX || TRI->getEncodingValue(SrcReg) < 16) {
4812 Register XReg = TRI->getSubReg(SrcReg, X86::sub_xmm);
4813 MIB->getOperand(0).setReg(XReg);
4814 Expand2AddrUndef(MIB,
4815 get(HasVLX ? X86::VPXORDZ128rr : X86::VXORPSrr));
4816 MIB.addReg(SrcReg, RegState::ImplicitDefine);
4817 return true;
4818 }
4819 if (MI.getOpcode() == X86::AVX512_256_SET0) {
4820 // No VLX so we must reference a zmm.
4821 unsigned ZReg =
4822 TRI->getMatchingSuperReg(SrcReg, X86::sub_ymm, &X86::VR512RegClass);
4823 MIB->getOperand(0).setReg(ZReg);
4824 }
4825 return Expand2AddrUndef(MIB, get(X86::VPXORDZrr));
4826 }
4827 case X86::V_SETALLONES:
4828 return Expand2AddrUndef(MIB, get(HasAVX ? X86::VPCMPEQDrr : X86::PCMPEQDrr));
4829 case X86::AVX2_SETALLONES:
4830 return Expand2AddrUndef(MIB, get(X86::VPCMPEQDYrr));
4831 case X86::AVX1_SETALLONES: {
4832 Register Reg = MIB.getReg(0);
4833 // VCMPPSYrri with an immediate 0xf should produce VCMPTRUEPS.
4834 MIB->setDesc(get(X86::VCMPPSYrri));
4835 MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef).addImm(0xf);
4836 return true;
4837 }
4838 case X86::AVX512_512_SETALLONES: {
4839 Register Reg = MIB.getReg(0);
4840 MIB->setDesc(get(X86::VPTERNLOGDZrri));
4841 // VPTERNLOGD needs 3 register inputs and an immediate.
4842 // 0xff will return 1s for any input.
4843 MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef)
4844 .addReg(Reg, RegState::Undef).addImm(0xff);
4845 return true;
4846 }
4847 case X86::AVX512_512_SEXT_MASK_32:
4848 case X86::AVX512_512_SEXT_MASK_64: {
4849 Register Reg = MIB.getReg(0);
4850 Register MaskReg = MIB.getReg(1);
4851 unsigned MaskState = getRegState(MIB->getOperand(1));
4852 unsigned Opc = (MI.getOpcode() == X86::AVX512_512_SEXT_MASK_64) ?
4853 X86::VPTERNLOGQZrrikz : X86::VPTERNLOGDZrrikz;
4854 MI.RemoveOperand(1);
4855 MIB->setDesc(get(Opc));
4856 // VPTERNLOG needs 3 register inputs and an immediate.
4857 // 0xff will return 1s for any input.
4858 MIB.addReg(Reg, RegState::Undef).addReg(MaskReg, MaskState)
4859 .addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef).addImm(0xff);
4860 return true;
4861 }
4862 case X86::VMOVAPSZ128rm_NOVLX:
4863 return expandNOVLXLoad(MIB, &getRegisterInfo(), get(X86::VMOVAPSrm),
4864 get(X86::VBROADCASTF32X4rm), X86::sub_xmm);
4865 case X86::VMOVUPSZ128rm_NOVLX:
4866 return expandNOVLXLoad(MIB, &getRegisterInfo(), get(X86::VMOVUPSrm),
4867 get(X86::VBROADCASTF32X4rm), X86::sub_xmm);
4868 case X86::VMOVAPSZ256rm_NOVLX:
4869 return expandNOVLXLoad(MIB, &getRegisterInfo(), get(X86::VMOVAPSYrm),
4870 get(X86::VBROADCASTF64X4rm), X86::sub_ymm);
4871 case X86::VMOVUPSZ256rm_NOVLX:
4872 return expandNOVLXLoad(MIB, &getRegisterInfo(), get(X86::VMOVUPSYrm),
4873 get(X86::VBROADCASTF64X4rm), X86::sub_ymm);
4874 case X86::VMOVAPSZ128mr_NOVLX:
4875 return expandNOVLXStore(MIB, &getRegisterInfo(), get(X86::VMOVAPSmr),
4876 get(X86::VEXTRACTF32x4Zmr), X86::sub_xmm);
4877 case X86::VMOVUPSZ128mr_NOVLX:
4878 return expandNOVLXStore(MIB, &getRegisterInfo(), get(X86::VMOVUPSmr),
4879 get(X86::VEXTRACTF32x4Zmr), X86::sub_xmm);
4880 case X86::VMOVAPSZ256mr_NOVLX:
4881 return expandNOVLXStore(MIB, &getRegisterInfo(), get(X86::VMOVAPSYmr),
4882 get(X86::VEXTRACTF64x4Zmr), X86::sub_ymm);
4883 case X86::VMOVUPSZ256mr_NOVLX:
4884 return expandNOVLXStore(MIB, &getRegisterInfo(), get(X86::VMOVUPSYmr),
4885 get(X86::VEXTRACTF64x4Zmr), X86::sub_ymm);
4886 case X86::MOV32ri64: {
4887 Register Reg = MIB.getReg(0);
4888 Register Reg32 = RI.getSubReg(Reg, X86::sub_32bit);
4889 MI.setDesc(get(X86::MOV32ri));
4890 MIB->getOperand(0).setReg(Reg32);
4891 MIB.addReg(Reg, RegState::ImplicitDefine);
4892 return true;
4893 }
4894
4895 // KNL does not recognize dependency-breaking idioms for mask registers,
4896 // so kxnor %k1, %k1, %k2 has a RAW dependence on %k1.
4897 // Using %k0 as the undef input register is a performance heuristic based
4898 // on the assumption that %k0 is used less frequently than the other mask
4899 // registers, since it is not usable as a write mask.
4900 // FIXME: A more advanced approach would be to choose the best input mask
4901 // register based on context.
4902 case X86::KSET0W: return Expand2AddrKreg(MIB, get(X86::KXORWrr), X86::K0);
4903 case X86::KSET0D: return Expand2AddrKreg(MIB, get(X86::KXORDrr), X86::K0);
4904 case X86::KSET0Q: return Expand2AddrKreg(MIB, get(X86::KXORQrr), X86::K0);
4905 case X86::KSET1W: return Expand2AddrKreg(MIB, get(X86::KXNORWrr), X86::K0);
4906 case X86::KSET1D: return Expand2AddrKreg(MIB, get(X86::KXNORDrr), X86::K0);
4907 case X86::KSET1Q: return Expand2AddrKreg(MIB, get(X86::KXNORQrr), X86::K0);
4908 case TargetOpcode::LOAD_STACK_GUARD:
4909 expandLoadStackGuard(MIB, *this);
4910 return true;
4911 case X86::XOR64_FP:
4912 case X86::XOR32_FP:
4913 return expandXorFP(MIB, *this);
4914 case X86::SHLDROT32ri: return expandSHXDROT(MIB, get(X86::SHLD32rri8));
4915 case X86::SHLDROT64ri: return expandSHXDROT(MIB, get(X86::SHLD64rri8));
4916 case X86::SHRDROT32ri: return expandSHXDROT(MIB, get(X86::SHRD32rri8));
4917 case X86::SHRDROT64ri: return expandSHXDROT(MIB, get(X86::SHRD64rri8));
4918 case X86::ADD8rr_DB: MIB->setDesc(get(X86::OR8rr)); break;
4919 case X86::ADD16rr_DB: MIB->setDesc(get(X86::OR16rr)); break;
4920 case X86::ADD32rr_DB: MIB->setDesc(get(X86::OR32rr)); break;
4921 case X86::ADD64rr_DB: MIB->setDesc(get(X86::OR64rr)); break;
4922 case X86::ADD8ri_DB: MIB->setDesc(get(X86::OR8ri)); break;
4923 case X86::ADD16ri_DB: MIB->setDesc(get(X86::OR16ri)); break;
4924 case X86::ADD32ri_DB: MIB->setDesc(get(X86::OR32ri)); break;
4925 case X86::ADD64ri32_DB: MIB->setDesc(get(X86::OR64ri32)); break;
4926 case X86::ADD16ri8_DB: MIB->setDesc(get(X86::OR16ri8)); break;
4927 case X86::ADD32ri8_DB: MIB->setDesc(get(X86::OR32ri8)); break;
4928 case X86::ADD64ri8_DB: MIB->setDesc(get(X86::OR64ri8)); break;
4929 }
4930 return false;
4931}
4932
4933/// Return true for all instructions that only update
4934/// the first 32 or 64-bits of the destination register and leave the rest
4935/// unmodified. This can be used to avoid folding loads if the instructions
4936/// only update part of the destination register, and the non-updated part is
4937/// not needed. e.g. cvtss2sd, sqrtss. Unfolding the load from these
4938/// instructions breaks the partial register dependency and it can improve
4939/// performance. e.g.:
4940///
4941/// movss (%rdi), %xmm0
4942/// cvtss2sd %xmm0, %xmm0
4943///
4944/// Instead of
4945/// cvtss2sd (%rdi), %xmm0
4946///
4947/// FIXME: This should be turned into a TSFlags.
4948///
4949static bool hasPartialRegUpdate(unsigned Opcode,
4950 const X86Subtarget &Subtarget,
4951 bool ForLoadFold = false) {
4952 switch (Opcode) {
4953 case X86::CVTSI2SSrr:
4954 case X86::CVTSI2SSrm:
4955 case X86::CVTSI642SSrr:
4956 case X86::CVTSI642SSrm:
4957 case X86::CVTSI2SDrr:
4958 case X86::CVTSI2SDrm:
4959 case X86::CVTSI642SDrr:
4960 case X86::CVTSI642SDrm:
4961 // Load folding won't effect the undef register update since the input is
4962 // a GPR.
4963 return !ForLoadFold;
4964 case X86::CVTSD2SSrr:
4965 case X86::CVTSD2SSrm:
4966 case X86::CVTSS2SDrr:
4967 case X86::CVTSS2SDrm:
4968 case X86::MOVHPDrm:
4969 case X86::MOVHPSrm:
4970 case X86::MOVLPDrm:
4971 case X86::MOVLPSrm:
4972 case X86::RCPSSr:
4973 case X86::RCPSSm:
4974 case X86::RCPSSr_Int:
4975 case X86::RCPSSm_Int:
4976 case X86::ROUNDSDr:
4977 case X86::ROUNDSDm:
4978 case X86::ROUNDSSr:
4979 case X86::ROUNDSSm:
4980 case X86::RSQRTSSr:
4981 case X86::RSQRTSSm:
4982 case X86::RSQRTSSr_Int:
4983 case X86::RSQRTSSm_Int:
4984 case X86::SQRTSSr:
4985 case X86::SQRTSSm:
4986 case X86::SQRTSSr_Int:
4987 case X86::SQRTSSm_Int:
4988 case X86::SQRTSDr:
4989 case X86::SQRTSDm:
4990 case X86::SQRTSDr_Int:
4991 case X86::SQRTSDm_Int:
4992 return true;
4993 // GPR
4994 case X86::POPCNT32rm:
4995 case X86::POPCNT32rr:
4996 case X86::POPCNT64rm:
4997 case X86::POPCNT64rr:
4998 return Subtarget.hasPOPCNTFalseDeps();
4999 case X86::LZCNT32rm:
5000 case X86::LZCNT32rr:
5001 case X86::LZCNT64rm:
5002 case X86::LZCNT64rr:
5003 case X86::TZCNT32rm:
5004 case X86::TZCNT32rr:
5005 case X86::TZCNT64rm:
5006 case X86::TZCNT64rr:
5007 return Subtarget.hasLZCNTFalseDeps();
5008 }
5009
5010 return false;
5011}
5012
5013/// Inform the BreakFalseDeps pass how many idle
5014/// instructions we would like before a partial register update.
5015unsigned X86InstrInfo::getPartialRegUpdateClearance(
5016 const MachineInstr &MI, unsigned OpNum,
5017 const TargetRegisterInfo *TRI) const {
5018 if (OpNum != 0 || !hasPartialRegUpdate(MI.getOpcode(), Subtarget))
5019 return 0;
5020
5021 // If MI is marked as reading Reg, the partial register update is wanted.
5022 const MachineOperand &MO = MI.getOperand(0);
5023 Register Reg = MO.getReg();
5024 if (Reg.isVirtual()) {
5025 if (MO.readsReg() || MI.readsVirtualRegister(Reg))
5026 return 0;
5027 } else {
5028 if (MI.readsRegister(Reg, TRI))
5029 return 0;
5030 }
5031
5032 // If any instructions in the clearance range are reading Reg, insert a
5033 // dependency breaking instruction, which is inexpensive and is likely to
5034 // be hidden in other instruction's cycles.
5035 return PartialRegUpdateClearance;
5036}
5037
5038// Return true for any instruction the copies the high bits of the first source
5039// operand into the unused high bits of the destination operand.
5040// Also returns true for instructions that have two inputs where one may
5041// be undef and we want it to use the same register as the other input.
5042static bool hasUndefRegUpdate(unsigned Opcode, unsigned OpNum,
5043 bool ForLoadFold = false) {
5044 // Set the OpNum parameter to the first source operand.
5045 switch (Opcode) {
5046 case X86::MMX_PUNPCKHBWirr:
5047 case X86::MMX_PUNPCKHWDirr:
5048 case X86::MMX_PUNPCKHDQirr:
5049 case X86::MMX_PUNPCKLBWirr:
5050 case X86::MMX_PUNPCKLWDirr:
5051 case X86::MMX_PUNPCKLDQirr:
5052 case X86::MOVHLPSrr:
5053 case X86::PACKSSWBrr:
5054 case X86::PACKUSWBrr:
5055 case X86::PACKSSDWrr:
5056 case X86::PACKUSDWrr:
5057 case X86::PUNPCKHBWrr:
5058 case X86::PUNPCKLBWrr:
5059 case X86::PUNPCKHWDrr:
5060 case X86::PUNPCKLWDrr:
5061 case X86::PUNPCKHDQrr:
5062 case X86::PUNPCKLDQrr:
5063 case X86::PUNPCKHQDQrr:
5064 case X86::PUNPCKLQDQrr:
5065 case X86::SHUFPDrri:
5066 case X86::SHUFPSrri:
5067 // These instructions are sometimes used with an undef first or second
5068 // source. Return true here so BreakFalseDeps will assign this source to the
5069 // same register as the first source to avoid a false dependency.
5070 // Operand 1 of these instructions is tied so they're separate from their
5071 // VEX counterparts.
5072 return OpNum == 2 && !ForLoadFold;
5073
5074 case X86::VMOVLHPSrr:
5075 case X86::VMOVLHPSZrr:
5076 case X86::VPACKSSWBrr:
5077 case X86::VPACKUSWBrr:
5078 case X86::VPACKSSDWrr:
5079 case X86::VPACKUSDWrr:
5080 case X86::VPACKSSWBZ128rr:
5081 case X86::VPACKUSWBZ128rr:
5082 case X86::VPACKSSDWZ128rr:
5083 case X86::VPACKUSDWZ128rr:
5084 case X86::VPERM2F128rr:
5085 case X86::VPERM2I128rr:
5086 case X86::VSHUFF32X4Z256rri:
5087 case X86::VSHUFF32X4Zrri:
5088 case X86::VSHUFF64X2Z256rri:
5089 case X86::VSHUFF64X2Zrri:
5090 case X86::VSHUFI32X4Z256rri:
5091 case X86::VSHUFI32X4Zrri:
5092 case X86::VSHUFI64X2Z256rri:
5093 case X86::VSHUFI64X2Zrri:
5094 case X86::VPUNPCKHBWrr:
5095 case X86::VPUNPCKLBWrr:
5096 case X86::VPUNPCKHBWYrr:
5097 case X86::VPUNPCKLBWYrr:
5098 case X86::VPUNPCKHBWZ128rr:
5099 case X86::VPUNPCKLBWZ128rr:
5100 case X86::VPUNPCKHBWZ256rr:
5101 case X86::VPUNPCKLBWZ256rr:
5102 case X86::VPUNPCKHBWZrr:
5103 case X86::VPUNPCKLBWZrr:
5104 case X86::VPUNPCKHWDrr:
5105 case X86::VPUNPCKLWDrr:
5106 case X86::VPUNPCKHWDYrr:
5107 case X86::VPUNPCKLWDYrr:
5108 case X86::VPUNPCKHWDZ128rr:
5109 case X86::VPUNPCKLWDZ128rr:
5110 case X86::VPUNPCKHWDZ256rr:
5111 case X86::VPUNPCKLWDZ256rr:
5112 case X86::VPUNPCKHWDZrr:
5113 case X86::VPUNPCKLWDZrr:
5114 case X86::VPUNPCKHDQrr:
5115 case X86::VPUNPCKLDQrr:
5116 case X86::VPUNPCKHDQYrr:
5117 case X86::VPUNPCKLDQYrr:
5118 case X86::VPUNPCKHDQZ128rr:
5119 case X86::VPUNPCKLDQZ128rr:
5120 case X86::VPUNPCKHDQZ256rr:
5121 case X86::VPUNPCKLDQZ256rr:
5122 case X86::VPUNPCKHDQZrr:
5123 case X86::VPUNPCKLDQZrr:
5124 case X86::VPUNPCKHQDQrr:
5125 case X86::VPUNPCKLQDQrr:
5126 case X86::VPUNPCKHQDQYrr:
5127 case X86::VPUNPCKLQDQYrr:
5128 case X86::VPUNPCKHQDQZ128rr:
5129 case X86::VPUNPCKLQDQZ128rr:
5130 case X86::VPUNPCKHQDQZ256rr:
5131 case X86::VPUNPCKLQDQZ256rr:
5132 case X86::VPUNPCKHQDQZrr:
5133 case X86::VPUNPCKLQDQZrr:
5134 // These instructions are sometimes used with an undef first or second
5135 // source. Return true here so BreakFalseDeps will assign this source to the
5136 // same register as the first source to avoid a false dependency.
5137 return (OpNum == 1 || OpNum == 2) && !ForLoadFold;
5138
5139 case X86::VCVTSI2SSrr:
5140 case X86::VCVTSI2SSrm:
5141 case X86::VCVTSI2SSrr_Int:
5142 case X86::VCVTSI2SSrm_Int:
5143 case X86::VCVTSI642SSrr:
5144 case X86::VCVTSI642SSrm:
5145 case X86::VCVTSI642SSrr_Int:
5146 case X86::VCVTSI642SSrm_Int:
5147 case X86::VCVTSI2SDrr:
5148 case X86::VCVTSI2SDrm:
5149 case X86::VCVTSI2SDrr_Int:
5150 case X86::VCVTSI2SDrm_Int:
5151 case X86::VCVTSI642SDrr:
5152 case X86::VCVTSI642SDrm:
5153 case X86::VCVTSI642SDrr_Int:
5154 case X86::VCVTSI642SDrm_Int:
5155 // AVX-512
5156 case X86::VCVTSI2SSZrr:
5157 case X86::VCVTSI2SSZrm:
5158 case X86::VCVTSI2SSZrr_Int:
5159 case X86::VCVTSI2SSZrrb_Int:
5160 case X86::VCVTSI2SSZrm_Int:
5161 case X86::VCVTSI642SSZrr:
5162 case X86::VCVTSI642SSZrm:
5163 case X86::VCVTSI642SSZrr_Int:
5164 case X86::VCVTSI642SSZrrb_Int:
5165 case X86::VCVTSI642SSZrm_Int:
5166 case X86::VCVTSI2SDZrr:
5167 case X86::VCVTSI2SDZrm:
5168 case X86::VCVTSI2SDZrr_Int:
5169 case X86::VCVTSI2SDZrm_Int:
5170 case X86::VCVTSI642SDZrr:
5171 case X86::VCVTSI642SDZrm:
5172 case X86::VCVTSI642SDZrr_Int:
5173 case X86::VCVTSI642SDZrrb_Int:
5174 case X86::VCVTSI642SDZrm_Int:
5175 case X86::VCVTUSI2SSZrr:
5176 case X86::VCVTUSI2SSZrm:
5177 case X86::VCVTUSI2SSZrr_Int:
5178 case X86::VCVTUSI2SSZrrb_Int:
5179 case X86::VCVTUSI2SSZrm_Int:
5180 case X86::VCVTUSI642SSZrr:
5181 case X86::VCVTUSI642SSZrm:
5182 case X86::VCVTUSI642SSZrr_Int:
5183 case X86::VCVTUSI642SSZrrb_Int:
5184 case X86::VCVTUSI642SSZrm_Int:
5185 case X86::VCVTUSI2SDZrr:
5186 case X86::VCVTUSI2SDZrm:
5187 case X86::VCVTUSI2SDZrr_Int:
5188 case X86::VCVTUSI2SDZrm_Int:
5189 case X86::VCVTUSI642SDZrr:
5190 case X86::VCVTUSI642SDZrm:
5191 case X86::VCVTUSI642SDZrr_Int:
5192 case X86::VCVTUSI642SDZrrb_Int:
5193 case X86::VCVTUSI642SDZrm_Int:
5194 case X86::VCVTSI2SHZrr:
5195 case X86::VCVTSI2SHZrm:
5196 case X86::VCVTSI2SHZrr_Int:
5197 case X86::VCVTSI2SHZrrb_Int:
5198 case X86::VCVTSI2SHZrm_Int:
5199 case X86::VCVTSI642SHZrr:
5200 case X86::VCVTSI642SHZrm:
5201 case X86::VCVTSI642SHZrr_Int:
5202 case X86::VCVTSI642SHZrrb_Int:
5203 case X86::VCVTSI642SHZrm_Int:
5204 case X86::VCVTUSI2SHZrr:
5205 case X86::VCVTUSI2SHZrm:
5206 case X86::VCVTUSI2SHZrr_Int:
5207 case X86::VCVTUSI2SHZrrb_Int:
5208 case X86::VCVTUSI2SHZrm_Int:
5209 case X86::VCVTUSI642SHZrr:
5210 case X86::VCVTUSI642SHZrm:
5211 case X86::VCVTUSI642SHZrr_Int:
5212 case X86::VCVTUSI642SHZrrb_Int:
5213 case X86::VCVTUSI642SHZrm_Int:
5214 // Load folding won't effect the undef register update since the input is
5215 // a GPR.
5216 return OpNum == 1 && !ForLoadFold;
5217 case X86::VCVTSD2SSrr:
5218 case X86::VCVTSD2SSrm:
5219 case X86::VCVTSD2SSrr_Int:
5220 case X86::VCVTSD2SSrm_Int:
5221 case X86::VCVTSS2SDrr:
5222 case X86::VCVTSS2SDrm:
5223 case X86::VCVTSS2SDrr_Int:
5224 case X86::VCVTSS2SDrm_Int:
5225 case X86::VRCPSSr:
5226 case X86::VRCPSSr_Int:
5227 case X86::VRCPSSm:
5228 case X86::VRCPSSm_Int:
5229 case X86::VROUNDSDr:
5230 case X86::VROUNDSDm:
5231 case X86::VROUNDSDr_Int:
5232 case X86::VROUNDSDm_Int:
5233 case X86::VROUNDSSr:
5234 case X86::VROUNDSSm:
5235 case X86::VROUNDSSr_Int:
5236 case X86::VROUNDSSm_Int:
5237 case X86::VRSQRTSSr:
5238 case X86::VRSQRTSSr_Int:
5239 case X86::VRSQRTSSm:
5240 case X86::VRSQRTSSm_Int:
5241 case X86::VSQRTSSr:
5242 case X86::VSQRTSSr_Int:
5243 case X86::VSQRTSSm:
5244 case X86::VSQRTSSm_Int:
5245 case X86::VSQRTSDr:
5246 case X86::VSQRTSDr_Int:
5247 case X86::VSQRTSDm:
5248 case X86::VSQRTSDm_Int:
5249 // AVX-512
5250 case X86::VCVTSD2SSZrr:
5251 case X86::VCVTSD2SSZrr_Int:
5252 case X86::VCVTSD2SSZrrb_Int:
5253 case X86::VCVTSD2SSZrm:
5254 case X86::VCVTSD2SSZrm_Int:
5255 case X86::VCVTSS2SDZrr:
5256 case X86::VCVTSS2SDZrr_Int:
5257 case X86::VCVTSS2SDZrrb_Int:
5258 case X86::VCVTSS2SDZrm:
5259 case X86::VCVTSS2SDZrm_Int:
5260 case X86::VGETEXPSDZr:
5261 case X86::VGETEXPSDZrb:
5262 case X86::VGETEXPSDZm:
5263 case X86::VGETEXPSSZr:
5264 case X86::VGETEXPSSZrb:
5265 case X86::VGETEXPSSZm:
5266 case X86::VGETMANTSDZrri:
5267 case X86::VGETMANTSDZrrib:
5268 case X86::VGETMANTSDZrmi:
5269 case X86::VGETMANTSSZrri:
5270 case X86::VGETMANTSSZrrib:
5271 case X86::VGETMANTSSZrmi:
5272 case X86::VRNDSCALESDZr:
5273 case X86::VRNDSCALESDZr_Int:
5274 case X86::VRNDSCALESDZrb_Int:
5275 case X86::VRNDSCALESDZm:
5276 case X86::VRNDSCALESDZm_Int:
5277 case X86::VRNDSCALESSZr:
5278 case X86::VRNDSCALESSZr_Int:
5279 case X86::VRNDSCALESSZrb_Int:
5280 case X86::VRNDSCALESSZm:
5281 case X86::VRNDSCALESSZm_Int:
5282 case X86::VRCP14SDZrr:
5283 case X86::VRCP14SDZrm:
5284 case X86::VRCP14SSZrr:
5285 case X86::VRCP14SSZrm:
5286 case X86::VRCPSHZrr:
5287 case X86::VRCPSHZrm:
5288 case X86::VRSQRTSHZrr:
5289 case X86::VRSQRTSHZrm:
5290 case X86::VREDUCESHZrmi:
5291 case X86::VREDUCESHZrri:
5292 case X86::VREDUCESHZrrib:
5293 case X86::VGETEXPSHZr:
5294 case X86::VGETEXPSHZrb:
5295 case X86::VGETEXPSHZm:
5296 case X86::VGETMANTSHZrri:
5297 case X86::VGETMANTSHZrrib:
5298 case X86::VGETMANTSHZrmi:
5299 case X86::VRNDSCALESHZr:
5300 case X86::VRNDSCALESHZr_Int:
5301 case X86::VRNDSCALESHZrb_Int:
5302 case X86::VRNDSCALESHZm:
5303 case X86::VRNDSCALESHZm_Int:
5304 case X86::VSQRTSHZr:
5305 case X86::VSQRTSHZr_Int:
5306 case X86::VSQRTSHZrb_Int:
5307 case X86::VSQRTSHZm:
5308 case X86::VSQRTSHZm_Int:
5309 case X86::VRCP28SDZr:
5310 case X86::VRCP28SDZrb:
5311 case X86::VRCP28SDZm:
5312 case X86::VRCP28SSZr:
5313 case X86::VRCP28SSZrb:
5314 case X86::VRCP28SSZm:
5315 case X86::VREDUCESSZrmi:
5316 case X86::VREDUCESSZrri:
5317 case X86::VREDUCESSZrrib:
5318 case X86::VRSQRT14SDZrr:
5319 case X86::VRSQRT14SDZrm:
5320 case X86::VRSQRT14SSZrr:
5321 case X86::VRSQRT14SSZrm:
5322 case X86::VRSQRT28SDZr:
5323 case X86::VRSQRT28SDZrb:
5324 case X86::VRSQRT28SDZm:
5325 case X86::VRSQRT28SSZr:
5326 case X86::VRSQRT28SSZrb:
5327 case X86::VRSQRT28SSZm:
5328 case X86::VSQRTSSZr:
5329 case X86::VSQRTSSZr_Int:
5330 case X86::VSQRTSSZrb_Int:
5331 case X86::VSQRTSSZm:
5332 case X86::VSQRTSSZm_Int:
5333 case X86::VSQRTSDZr:
5334 case X86::VSQRTSDZr_Int:
5335 case X86::VSQRTSDZrb_Int:
5336 case X86::VSQRTSDZm:
5337 case X86::VSQRTSDZm_Int:
5338 case X86::VCVTSD2SHZrr:
5339 case X86::VCVTSD2SHZrr_Int:
5340 case X86::VCVTSD2SHZrrb_Int:
5341 case X86::VCVTSD2SHZrm:
5342 case X86::VCVTSD2SHZrm_Int:
5343 case X86::VCVTSS2SHZrr:
5344 case X86::VCVTSS2SHZrr_Int:
5345 case X86::VCVTSS2SHZrrb_Int:
5346 case X86::VCVTSS2SHZrm:
5347 case X86::VCVTSS2SHZrm_Int:
5348 case X86::VCVTSH2SDZrr:
5349 case X86::VCVTSH2SDZrr_Int:
5350 case X86::VCVTSH2SDZrrb_Int:
5351 case X86::VCVTSH2SDZrm:
5352 case X86::VCVTSH2SDZrm_Int:
5353 case X86::VCVTSH2SSZrr:
5354 case X86::VCVTSH2SSZrr_Int:
5355 case X86::VCVTSH2SSZrrb_Int:
5356 case X86::VCVTSH2SSZrm:
5357 case X86::VCVTSH2SSZrm_Int:
5358 return OpNum == 1;
5359 case X86::VMOVSSZrrk:
5360 case X86::VMOVSDZrrk:
5361 return OpNum == 3 && !ForLoadFold;
5362 case X86::VMOVSSZrrkz:
5363 case X86::VMOVSDZrrkz:
5364 return OpNum == 2 && !ForLoadFold;
5365 }
5366
5367 return false;
5368}
5369
5370/// Inform the BreakFalseDeps pass how many idle instructions we would like
5371/// before certain undef register reads.
5372///
5373/// This catches the VCVTSI2SD family of instructions:
5374///
5375/// vcvtsi2sdq %rax, undef %xmm0, %xmm14
5376///
5377/// We should to be careful *not* to catch VXOR idioms which are presumably
5378/// handled specially in the pipeline:
5379///
5380/// vxorps undef %xmm1, undef %xmm1, %xmm1
5381///
5382/// Like getPartialRegUpdateClearance, this makes a strong assumption that the
5383/// high bits that are passed-through are not live.
5384unsigned
5385X86InstrInfo::getUndefRegClearance(const MachineInstr &MI, unsigned OpNum,
5386 const TargetRegisterInfo *TRI) const {
5387 const MachineOperand &MO = MI.getOperand(OpNum);
5388 if (Register::isPhysicalRegister(MO.getReg()) &&
5389 hasUndefRegUpdate(MI.getOpcode(), OpNum))
5390 return UndefRegClearance;
5391
5392 return 0;
5393}
5394
5395void X86InstrInfo::breakPartialRegDependency(
5396 MachineInstr &MI, unsigned OpNum, const TargetRegisterInfo *TRI) const {
5397 Register Reg = MI.getOperand(OpNum).getReg();
5398 // If MI kills this register, the false dependence is already broken.
5399 if (MI.killsRegister(Reg, TRI))
5400 return;
5401
5402 if (X86::VR128RegClass.contains(Reg)) {
5403 // These instructions are all floating point domain, so xorps is the best
5404 // choice.
5405 unsigned Opc = Subtarget.hasAVX() ? X86::VXORPSrr : X86::XORPSrr;
5406 BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(Opc), Reg)
5407 .addReg(Reg, RegState::Undef)
5408 .addReg(Reg, RegState::Undef);
5409 MI.addRegisterKilled(Reg, TRI, true);
5410 } else if (X86::VR256RegClass.contains(Reg)) {
5411 // Use vxorps to clear the full ymm register.
5412 // It wants to read and write the xmm sub-register.
5413 Register XReg = TRI->getSubReg(Reg, X86::sub_xmm);
5414 BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(X86::VXORPSrr), XReg)
5415 .addReg(XReg, RegState::Undef)
5416 .addReg(XReg, RegState::Undef)
5417 .addReg(Reg, RegState::ImplicitDefine);
5418 MI.addRegisterKilled(Reg, TRI, true);
5419 } else if (X86::GR64RegClass.contains(Reg)) {
5420 // Using XOR32rr because it has shorter encoding and zeros up the upper bits
5421 // as well.
5422 Register XReg = TRI->getSubReg(Reg, X86::sub_32bit);
5423 BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(X86::XOR32rr), XReg)
5424 .addReg(XReg, RegState::Undef)
5425 .addReg(XReg, RegState::Undef)
5426 .addReg(Reg, RegState::ImplicitDefine);
5427 MI.addRegisterKilled(Reg, TRI, true);
5428 } else if (X86::GR32RegClass.contains(Reg)) {
5429 BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(X86::XOR32rr), Reg)
5430 .addReg(Reg, RegState::Undef)
5431 .addReg(Reg, RegState::Undef);
5432 MI.addRegisterKilled(Reg, TRI, true);
5433 }
5434}
5435
5436static void addOperands(MachineInstrBuilder &MIB, ArrayRef<MachineOperand> MOs,
5437 int PtrOffset = 0) {
5438 unsigned NumAddrOps = MOs.size();
5439
5440 if (NumAddrOps < 4) {
5441 // FrameIndex only - add an immediate offset (whether its zero or not).
5442 for (unsigned i = 0; i != NumAddrOps; ++i)
5443 MIB.add(MOs[i]);
5444 addOffset(MIB, PtrOffset);
5445 } else {
5446 // General Memory Addressing - we need to add any offset to an existing
5447 // offset.
5448 assert(MOs.size() == 5 && "Unexpected memory operand list length")(static_cast <bool> (MOs.size() == 5 && "Unexpected memory operand list length"
) ? void (0) : __assert_fail ("MOs.size() == 5 && \"Unexpected memory operand list length\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 5448, __extension__ __PRETTY_FUNCTION__))
;
5449 for (unsigned i = 0; i != NumAddrOps; ++i) {
5450 const MachineOperand &MO = MOs[i];
5451 if (i == 3 && PtrOffset != 0) {
5452 MIB.addDisp(MO, PtrOffset);
5453 } else {
5454 MIB.add(MO);
5455 }
5456 }
5457 }
5458}
5459
5460static void updateOperandRegConstraints(MachineFunction &MF,
5461 MachineInstr &NewMI,
5462 const TargetInstrInfo &TII) {
5463 MachineRegisterInfo &MRI = MF.getRegInfo();
5464 const TargetRegisterInfo &TRI = *MRI.getTargetRegisterInfo();
5465
5466 for (int Idx : llvm::seq<int>(0, NewMI.getNumOperands())) {
5467 MachineOperand &MO = NewMI.getOperand(Idx);
5468 // We only need to update constraints on virtual register operands.
5469 if (!MO.isReg())
5470 continue;
5471 Register Reg = MO.getReg();
5472 if (!Reg.isVirtual())
5473 continue;
5474
5475 auto *NewRC = MRI.constrainRegClass(
5476 Reg, TII.getRegClass(NewMI.getDesc(), Idx, &TRI, MF));
5477 if (!NewRC) {
5478 LLVM_DEBUG(do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("x86-instr-info")) { dbgs() << "WARNING: Unable to update register constraint for operand "
<< Idx << " of instruction:\n"; NewMI.dump(); dbgs
() << "\n"; } } while (false)
5479 dbgs() << "WARNING: Unable to update register constraint for operand "do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("x86-instr-info")) { dbgs() << "WARNING: Unable to update register constraint for operand "
<< Idx << " of instruction:\n"; NewMI.dump(); dbgs
() << "\n"; } } while (false)
5480 << Idx << " of instruction:\n";do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("x86-instr-info")) { dbgs() << "WARNING: Unable to update register constraint for operand "
<< Idx << " of instruction:\n"; NewMI.dump(); dbgs
() << "\n"; } } while (false)
5481 NewMI.dump(); dbgs() << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("x86-instr-info")) { dbgs() << "WARNING: Unable to update register constraint for operand "
<< Idx << " of instruction:\n"; NewMI.dump(); dbgs
() << "\n"; } } while (false)
;
5482 }
5483 }
5484}
5485
5486static MachineInstr *FuseTwoAddrInst(MachineFunction &MF, unsigned Opcode,
5487 ArrayRef<MachineOperand> MOs,
5488 MachineBasicBlock::iterator InsertPt,
5489 MachineInstr &MI,
5490 const TargetInstrInfo &TII) {
5491 // Create the base instruction with the memory operand as the first part.
5492 // Omit the implicit operands, something BuildMI can't do.
5493 MachineInstr *NewMI =
5494 MF.CreateMachineInstr(TII.get(Opcode), MI.getDebugLoc(), true);
5495 MachineInstrBuilder MIB(MF, NewMI);
5496 addOperands(MIB, MOs);
5497
5498 // Loop over the rest of the ri operands, converting them over.
5499 unsigned NumOps = MI.getDesc().getNumOperands() - 2;
5500 for (unsigned i = 0; i != NumOps; ++i) {
5501 MachineOperand &MO = MI.getOperand(i + 2);
5502 MIB.add(MO);
5503 }
5504 for (unsigned i = NumOps + 2, e = MI.getNumOperands(); i != e; ++i) {
5505 MachineOperand &MO = MI.getOperand(i);
5506 MIB.add(MO);
5507 }
5508
5509 updateOperandRegConstraints(MF, *NewMI, TII);
5510
5511 MachineBasicBlock *MBB = InsertPt->getParent();
5512 MBB->insert(InsertPt, NewMI);
5513
5514 return MIB;
5515}
5516
5517static MachineInstr *FuseInst(MachineFunction &MF, unsigned Opcode,
5518 unsigned OpNo, ArrayRef<MachineOperand> MOs,
5519 MachineBasicBlock::iterator InsertPt,
5520 MachineInstr &MI, const TargetInstrInfo &TII,
5521 int PtrOffset = 0) {
5522 // Omit the implicit operands, something BuildMI can't do.
5523 MachineInstr *NewMI =
5524 MF.CreateMachineInstr(TII.get(Opcode), MI.getDebugLoc(), true);
5525 MachineInstrBuilder MIB(MF, NewMI);
5526
5527 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
5528 MachineOperand &MO = MI.getOperand(i);
5529 if (i == OpNo) {
5530 assert(MO.isReg() && "Expected to fold into reg operand!")(static_cast <bool> (MO.isReg() && "Expected to fold into reg operand!"
) ? void (0) : __assert_fail ("MO.isReg() && \"Expected to fold into reg operand!\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/X86/X86InstrInfo.cpp"
, 5530, __extension__ __PRETTY_FUNCTION__))
;
5531 addOperands(MIB, MOs, PtrOffset);
5532 } else {
5533 MIB.add(MO);
5534 }
5535 }
5536
5537 updateOperandRegConstraints(MF, *NewMI, TII);
5538
5539 // Copy the NoFPExcept flag from the instruction we're fusing.
5540 if (MI.getFlag(MachineInstr::MIFlag::NoFPExcept))
5541 NewMI->setFlag(MachineInstr::MIFlag::NoFPExcept);
5542
5543 MachineBasicBlock *MBB = InsertPt->getParent();
5544 MBB->insert(InsertPt, NewMI);
5545
5546 return MIB;
5547}
5548
5549static MachineInstr *MakeM0Inst(const TargetInstrInfo &TII, unsigned Opcode,
5550 ArrayRef<MachineOperand> MOs,
5551 MachineBasicBlock::iterator InsertPt,
5552 MachineInstr &MI) {
5553 MachineInstrBuilder MIB = BuildMI(*InsertPt->getParent(), InsertPt,
5554 MI.getDebugLoc(), TII.get(Opcode));
5555 addOperands(MIB, MOs);
5556 return MIB.addImm(0);
5557}
5558
5559MachineInstr *X86InstrInfo::foldMemoryOperandCustom(
5560 MachineFunction &MF, MachineInstr &MI, unsigned OpNum,
5561 ArrayRef<MachineOperand> MOs, MachineBasicBlock::iterator InsertPt,
5562 unsigned Size, Align Alignment) const {
5563 switch (MI.getOpcode()) {
5564 case X86::INSERTPSrr:
5565 case X86::VINSERTPSrr:
5566 case X86::VINSERTPSZrr:
5567 // Attempt to convert the load of inserted vector into a fold load
5568 // of a single float.
5569 if (OpNum == 2) {
5570 unsigned Imm = MI.getOperand(MI.getNumOperands() - 1).getImm();
5571 unsigned ZMask = Imm & 15;
5572 unsigned DstIdx = (Imm >> 4) & 3;
5573 unsigned SrcIdx = (Imm >> 6) & 3;
5574
5575 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
5576 const TargetRegisterClass *RC = getRegClass(MI.getDesc(), OpNum, &RI, MF);
5577 unsigned RCSize = TRI.getRegSizeInBits(*RC) / 8;
5578 if ((Size == 0 || Size >= 16) && RCSize >= 16 && Alignment >= Align(4)) {
5579 int PtrOffset = SrcIdx * 4;
5580 unsigned NewImm = (DstIdx << 4) | ZMask;
5581 unsigned NewOpCode =
5582 (MI.getOpcode() == X86::VINSERTPSZrr) ? X86::VINSERTPSZrm :
5583 (MI.getOpcode() == X86::VINSERTPSrr) ? X86::VINSERTPSrm :
5584 X86::INSERTPSrm;
5585 MachineInstr *NewMI =
5586 FuseInst(MF, NewOpCode, OpNum, MOs, InsertPt, MI, *this, PtrOffset);
5587 NewMI->getOperand(NewMI->getNumOperands() - 1).setImm(NewImm);
5588 return NewMI;
5589 }
5590 }
5591 break;
5592 case X86::MOVHLPSrr:
5593 case X86::VMOVHLPSrr:
5594 case X86::VMOVHLPSZrr:
5595 // Move the upper 64-bits of the second operand to the lower 64-bits.
5596 // To fold the load, adjust the pointer to the upper and use (V)MOVLPS.
5597 // TODO: In most cases AVX doesn't have a 8-byte alignment requirement.
5598 if (OpNum == 2) {
5599 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
5600 const TargetRegisterClass *RC = getRegClass(MI.getDesc(), OpNum, &RI, MF);
5601 unsigned RCSize = TRI.getRegSizeInBits(*RC) / 8;
5602 if ((Size == 0 || Size >= 16) && RCSize >= 16 && Alignment >= Align(8)) {
5603 unsigned NewOpCode =
5604 (MI.getOpcode() == X86::VMOVHLPSZrr) ? X86::VMOVLPSZ128rm :
5605 (MI.getOpcode() == X86::VMOVHLPSrr) ? X86::VMOVLPSrm :
5606 X86::MOVLPSrm;
5607 MachineInstr *NewMI =
5608 FuseInst(MF, NewOpCode, OpNum, MOs, InsertPt, MI, *this, 8);
5609 return NewMI;
5610 }
5611 }
5612 break;
5613 case X86::UNPCKLPDrr:
5614 // If we won't be able to fold this to the memory form of UNPCKL, use
5615 // MOVHPD instead. Done as custom because we can't have this in the load
5616 // table twice.
5617 if (OpNum == 2) {
5618 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
5619 const TargetRegisterClass *RC = getRegClass(MI.getDesc(), OpNum, &RI, MF);
5620 unsigned RCSize = TRI.getRegSizeInBits(*RC) / 8;
5621 if ((Size == 0 || Size >= 16) && RCSize >= 16 && Alignment < Align(16)) {
5622 MachineInstr *NewMI =
5623 FuseInst(MF, X86::MOVHPDrm, OpNum, MOs, InsertPt, MI, *this);
5624 return NewMI;
5625 }
5626 }
5627 break;
5628 }
5629
5630 return nullptr;
5631}
5632
5633static bool shouldPreventUndefRegUpdateMemFold(MachineFunction &MF,
5634 MachineInstr &MI) {
5635 if (!hasUndefRegUpdate(MI.getOpcode(), 1, /*ForLoadFold*/true) ||
5636 !MI.getOperand(1).isReg())
5637 return false;
5638
5639 // The are two cases we need to handle depending on where in the pipeline
5640 // the folding attempt is being made.
5641 // -Register has the undef flag set.
5642 // -Register is produced by the IMPLICIT_DEF instruction.
5643
5644 if (MI.getOperand(1).isUndef())
5645 return true;
5646
5647 MachineRegisterInfo &RegInfo = MF.getRegInfo();
5648 MachineInstr *VRegDef = RegInfo.getUniqueVRegDef(MI.getOperand(1).getReg());
5649 return VRegDef && VRegDef->isImplicitDef();
5650}
5651
5652MachineInstr *X86InstrInfo::foldMemoryOperandImpl(
5653 MachineFunction &MF, MachineInstr &MI, unsigned OpNum,
5654 ArrayRef<MachineOperand> MOs, MachineBasicBlock::iterator InsertPt,
5655 unsigned Size, Align Alignment, bool AllowCommute) const {
5656 bool isSlowTwoMemOps = Subtarget.slowTwoMemOps();
5657 bool isTwoAddrFold = false;
5658
5659 // For CPUs that favor the register form of a call or push,
5660 // do not fold loads into calls or pushes, unless optimizing for size
5661 // aggressively.
5662 if (isSlowTwoMemOps && !MF.getFunction().hasMinSize() &&
5663 (MI.getOpcode() == X86::CALL32r || MI.getOpcode() == X86::CALL64r ||
5664 MI.getOpcode() == X86::PUSH16r || MI.getOpcode() == X86::PUSH32r ||
5665 MI.getOpcode() == X86::PUSH64r))
5666 return nullptr;
5667
5668 // Avoid partial and undef register update stalls unless optimizing for size.
5669 if (!MF.getFunction().hasOptSize() &&
5670 (hasPartialRegUpdate(MI.getOpcode(), Subtarget, /*ForLoadFold*/true) ||
5671 shouldPreventUndefRegUpdateMemFold(MF, MI)))
5672 return nullptr;
5673
5674 unsigned NumOps = MI.getDesc().getNumOperands();
5675 bool isTwoAddr =
5676 NumOps > 1 && MI.getDesc().getOperandConstraint(1, MCOI::TIED_TO) != -1;
5677
5678 // FIXME: AsmPrinter doesn't know how to handle
5679 // X86II::MO_GOT_ABSOLUTE_ADDRESS after folding.
5680 if (MI.getOpcode() == X86::ADD32ri &&
5681 MI.getOperand(2).getTargetFlags() == X86II::MO_GOT_ABSOLUTE_ADDRESS)
5682 return nullptr;
5683
5684 // GOTTPOFF relocation loads can only be folded into add instructions.
5685 // FIXME: Need to exclude other relocations that only support specific
5686 // instructions.
5687 if (MOs.size() == X86::AddrNumOperands &&
5688 MOs[X86::AddrDisp].getTargetFlags() == X86II::MO_GOTTPOFF &&
5689 MI.getOpcode() != X86::ADD64rr)
5690 return nullptr;
5691
5692 MachineInstr *NewMI = nullptr;
5693
5694 // Attempt to fold any custom cases we have.
5695 if (MachineInstr *CustomMI = foldMemoryOperandCustom(
5696 MF, MI, OpNum, MOs, InsertPt, Size, Alignment))
5697 return CustomMI;
5698
5699 const X86MemoryFoldTableEntry *I = nullptr;
5700
5701 // Folding a memory location into the two-address part of a two-address
5702 // instruction is different than folding it other places. It requires
5703 // replacing the *two* registers with the memory location.
5704 if (isTwoAddr && NumOps >= 2 && OpNum < 2 && MI.getOperand(0).isReg() &&
5705 MI.getOperand(1).isReg() &&
5706 MI.getOperand(0).getReg() == MI.getOperand(1).getReg()) {
5707 I = lookupTwoAddrFoldTable(MI.getOpcode());
5708 isTwoAddrFold = true;
5709 } else {
5710 if (OpNum == 0) {
5711 if (MI.getOpcode() == X86::MOV32r0) {
5712 NewMI = MakeM0Inst(*this, X86::MOV32mi, MOs, InsertPt, MI);
5713 if (NewMI)
5714 return NewMI;
5715 }
5716 }
5717
5718 I = lookupFoldTable(MI.getOpcode(), OpNum);
5719 }
5720
5721 if (I != nullptr) {
5722 unsigned Opcode = I->DstOp;
5723 bool FoldedLoad =
5724 isTwoAddrFold || (OpNum == 0 && I->Flags & TB_FOLDED_LOAD) || OpNum > 0;
5725 bool FoldedStore =
5726 isTwoAddrFold || (OpNum == 0 && I->Flags & TB_FOLDED_STORE);
5727 MaybeAlign MinAlign =
5728 decodeMaybeAlign((I->Flags & TB_ALIGN_MASK) >> TB_ALIGN_SHIFT);
5729 if (MinAlign && Alignment < *MinAlign)
5730 return nullptr;
5731 bool NarrowToMOV32rm = false;
5732 if (Size) {
5733 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
5734 const TargetRegisterClass *RC = getRegClass(MI.getDesc(), OpNum,
5735 &RI, MF);
5736 unsigned RCSize = TRI.getRegSizeInBits(*RC) / 8;
5737 // Check if it's safe to fold the load. If the size of the object is
5738 // narrower than the load width, then it's not.
5739 // FIXME: Allow scalar intrinsic instructions like ADDSSrm_Int.
5740 if (FoldedLoad && Size < RCSize) {
5741 // If this is a 64-bit load, but the spill slot is 32, then we can do
5742 // a 32-bit load which is implicitly zero-extended. This likely is
5743 // due to live interval analysis remat'ing a load from stack slot.
5744 if (Opcode != X86::MOV64rm || RCSize != 8 || Size != 4)
5745 return nullptr;
5746 if (MI.getOperand(0).getSubReg() || MI.getOperand(1).getSubReg())
5747 return nullptr;
5748 Opcode = X86::MOV32rm;
5749 NarrowToMOV32rm = true;
5750 }
5751 // For stores, make sure the size of the object is equal to the size of
5752 // the store. If the object is larger, the extra bits would be garbage. If
5753 // the object is smaller we might overwrite another object or fault.
5754 if (FoldedStore && Size != RCSize)
5755 return nullptr;
5756 }
5757
5758 if (isTwoAddrFold)
5759 NewMI = FuseTwoAddrInst(MF, Opcode, MOs, InsertPt, MI, *this);
5760 else
5761 NewMI = FuseInst(MF, Opcode, OpNum, MOs, InsertPt, MI, *this);
5762
5763 if (NarrowToMOV32rm) {
5764 // If this is the special case where we use a MOV32rm to load a 32-bit
5765 // value and zero-extend the top bits. Change the destination register
5766 // to a 32-bit one.
5767 Register DstReg = NewMI->getOperand(0).getReg();
5768 if (DstReg.isPhysical())
5769 NewMI->getOperand(0).setReg(RI.getSubReg(DstReg, X86::sub_32bit));
5770 else
5771 NewMI->getOperand(0).setSubReg(X86::sub_32bit);
5772 }
5773 return NewMI;
5774 }
5775
5776 // If the instruction and target operand are commutable, commute the
5777 // instruction and try again.
5778 if (AllowCommute) {
5779 unsigned CommuteOpIdx1 = OpNum, CommuteOpIdx2 = CommuteAnyOperandIndex;
5780 if (findCommutedOpIndices(MI, CommuteOpIdx1, CommuteOpIdx2)) {
5781 bool HasDef = MI.getDesc().getNumDefs();
5782 Register Reg0 = HasDef ? MI.getOperand(0).getReg() : Register();
5783 Register Reg1 = MI.getOperand(CommuteOpIdx1).getReg();
5784 Register Reg2 = MI.getOperand(CommuteOpIdx2).getReg();
5785 bool Tied1 =
5786 0 == MI.getDesc().getOperandConstraint(CommuteOpIdx1, MCOI::TIED_TO);
5787 bool Tied2 =
5788 0 == MI.getDesc().getOperandConstraint(CommuteOpIdx2, MCOI::TIED_TO);
5789
5790 // If either of the commutable operands are tied to the destination
5791 // then we can not commute + fold.
5792 if ((HasDef && Reg0 == Reg1 && Tied1) ||
5793 (HasDef && Reg0 == Reg2 && Tied2))
5794 return nullptr;
5795
5796 MachineInstr *CommutedMI =
5797 commuteInstruction(MI,