Bug Summary

File:lib/Target/X86/X86InstrInfo.cpp
Warning:line 3741, column 37
Called C++ object pointer is null

Annotated Source Code

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clang -cc1 -triple x86_64-pc-linux-gnu -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name X86InstrInfo.cpp -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=cplusplus -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -analyzer-config-compatibility-mode=true -mrelocation-model pic -pic-level 2 -mthread-model posix -fmath-errno -masm-verbose -mconstructor-aliases -munwind-tables -fuse-init-array -target-cpu x86-64 -dwarf-column-info -debugger-tuning=gdb -momit-leaf-frame-pointer -ffunction-sections -fdata-sections -resource-dir /usr/lib/llvm-8/lib/clang/8.0.0 -D _DEBUG -D _GNU_SOURCE -D __STDC_CONSTANT_MACROS -D __STDC_FORMAT_MACROS -D __STDC_LIMIT_MACROS -I /build/llvm-toolchain-snapshot-8~svn350071/build-llvm/lib/Target/X86 -I /build/llvm-toolchain-snapshot-8~svn350071/lib/Target/X86 -I /build/llvm-toolchain-snapshot-8~svn350071/build-llvm/include -I /build/llvm-toolchain-snapshot-8~svn350071/include -U NDEBUG -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/x86_64-linux-gnu/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/x86_64-linux-gnu/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/c++/6.3.0/backward -internal-isystem /usr/include/clang/8.0.0/include/ -internal-isystem /usr/local/include -internal-isystem /usr/lib/llvm-8/lib/clang/8.0.0/include -internal-externc-isystem /usr/include/x86_64-linux-gnu -internal-externc-isystem /include -internal-externc-isystem /usr/include -O2 -Wno-unused-parameter -Wwrite-strings -Wno-missing-field-initializers -Wno-long-long -Wno-maybe-uninitialized -Wno-comment -std=c++11 -fdeprecated-macro -fdebug-compilation-dir /build/llvm-toolchain-snapshot-8~svn350071/build-llvm/lib/Target/X86 -fdebug-prefix-map=/build/llvm-toolchain-snapshot-8~svn350071=. -ferror-limit 19 -fmessage-length 0 -fvisibility-inlines-hidden -stack-protector 2 -fobjc-runtime=gcc -fdiagnostics-show-option -vectorize-loops -vectorize-slp -analyzer-output=html -analyzer-config stable-report-filename=true -o /tmp/scan-build-2018-12-27-042839-1215-1 -x c++ /build/llvm-toolchain-snapshot-8~svn350071/lib/Target/X86/X86InstrInfo.cpp -faddrsig
1//===-- X86InstrInfo.cpp - X86 Instruction Information --------------------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the X86 implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "X86InstrInfo.h"
15#include "X86.h"
16#include "X86InstrBuilder.h"
17#include "X86InstrFoldTables.h"
18#include "X86MachineFunctionInfo.h"
19#include "X86Subtarget.h"
20#include "X86TargetMachine.h"
21#include "llvm/ADT/STLExtras.h"
22#include "llvm/ADT/Sequence.h"
23#include "llvm/CodeGen/LivePhysRegs.h"
24#include "llvm/CodeGen/LiveVariables.h"
25#include "llvm/CodeGen/MachineConstantPool.h"
26#include "llvm/CodeGen/MachineDominators.h"
27#include "llvm/CodeGen/MachineFrameInfo.h"
28#include "llvm/CodeGen/MachineInstrBuilder.h"
29#include "llvm/CodeGen/MachineModuleInfo.h"
30#include "llvm/CodeGen/MachineRegisterInfo.h"
31#include "llvm/CodeGen/StackMaps.h"
32#include "llvm/IR/DerivedTypes.h"
33#include "llvm/IR/Function.h"
34#include "llvm/IR/LLVMContext.h"
35#include "llvm/MC/MCAsmInfo.h"
36#include "llvm/MC/MCExpr.h"
37#include "llvm/MC/MCInst.h"
38#include "llvm/Support/CommandLine.h"
39#include "llvm/Support/Debug.h"
40#include "llvm/Support/ErrorHandling.h"
41#include "llvm/Support/raw_ostream.h"
42#include "llvm/Target/TargetOptions.h"
43
44using namespace llvm;
45
46#define DEBUG_TYPE"x86-instr-info" "x86-instr-info"
47
48#define GET_INSTRINFO_CTOR_DTOR
49#include "X86GenInstrInfo.inc"
50
51static cl::opt<bool>
52 NoFusing("disable-spill-fusing",
53 cl::desc("Disable fusing of spill code into instructions"),
54 cl::Hidden);
55static cl::opt<bool>
56PrintFailedFusing("print-failed-fuse-candidates",
57 cl::desc("Print instructions that the allocator wants to"
58 " fuse, but the X86 backend currently can't"),
59 cl::Hidden);
60static cl::opt<bool>
61ReMatPICStubLoad("remat-pic-stub-load",
62 cl::desc("Re-materialize load from stub in PIC mode"),
63 cl::init(false), cl::Hidden);
64static cl::opt<unsigned>
65PartialRegUpdateClearance("partial-reg-update-clearance",
66 cl::desc("Clearance between two register writes "
67 "for inserting XOR to avoid partial "
68 "register update"),
69 cl::init(64), cl::Hidden);
70static cl::opt<unsigned>
71UndefRegClearance("undef-reg-clearance",
72 cl::desc("How many idle instructions we would like before "
73 "certain undef register reads"),
74 cl::init(128), cl::Hidden);
75
76
77// Pin the vtable to this file.
78void X86InstrInfo::anchor() {}
79
80X86InstrInfo::X86InstrInfo(X86Subtarget &STI)
81 : X86GenInstrInfo((STI.isTarget64BitLP64() ? X86::ADJCALLSTACKDOWN64
82 : X86::ADJCALLSTACKDOWN32),
83 (STI.isTarget64BitLP64() ? X86::ADJCALLSTACKUP64
84 : X86::ADJCALLSTACKUP32),
85 X86::CATCHRET,
86 (STI.is64Bit() ? X86::RETQ : X86::RETL)),
87 Subtarget(STI), RI(STI.getTargetTriple()) {
88}
89
90bool
91X86InstrInfo::isCoalescableExtInstr(const MachineInstr &MI,
92 unsigned &SrcReg, unsigned &DstReg,
93 unsigned &SubIdx) const {
94 switch (MI.getOpcode()) {
95 default: break;
96 case X86::MOVSX16rr8:
97 case X86::MOVZX16rr8:
98 case X86::MOVSX32rr8:
99 case X86::MOVZX32rr8:
100 case X86::MOVSX64rr8:
101 if (!Subtarget.is64Bit())
102 // It's not always legal to reference the low 8-bit of the larger
103 // register in 32-bit mode.
104 return false;
105 LLVM_FALLTHROUGH[[clang::fallthrough]];
106 case X86::MOVSX32rr16:
107 case X86::MOVZX32rr16:
108 case X86::MOVSX64rr16:
109 case X86::MOVSX64rr32: {
110 if (MI.getOperand(0).getSubReg() || MI.getOperand(1).getSubReg())
111 // Be conservative.
112 return false;
113 SrcReg = MI.getOperand(1).getReg();
114 DstReg = MI.getOperand(0).getReg();
115 switch (MI.getOpcode()) {
116 default: llvm_unreachable("Unreachable!")::llvm::llvm_unreachable_internal("Unreachable!", "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/X86/X86InstrInfo.cpp"
, 116)
;
117 case X86::MOVSX16rr8:
118 case X86::MOVZX16rr8:
119 case X86::MOVSX32rr8:
120 case X86::MOVZX32rr8:
121 case X86::MOVSX64rr8:
122 SubIdx = X86::sub_8bit;
123 break;
124 case X86::MOVSX32rr16:
125 case X86::MOVZX32rr16:
126 case X86::MOVSX64rr16:
127 SubIdx = X86::sub_16bit;
128 break;
129 case X86::MOVSX64rr32:
130 SubIdx = X86::sub_32bit;
131 break;
132 }
133 return true;
134 }
135 }
136 return false;
137}
138
139int X86InstrInfo::getSPAdjust(const MachineInstr &MI) const {
140 const MachineFunction *MF = MI.getParent()->getParent();
141 const TargetFrameLowering *TFI = MF->getSubtarget().getFrameLowering();
142
143 if (isFrameInstr(MI)) {
144 unsigned StackAlign = TFI->getStackAlignment();
145 int SPAdj = alignTo(getFrameSize(MI), StackAlign);
146 SPAdj -= getFrameAdjustment(MI);
147 if (!isFrameSetup(MI))
148 SPAdj = -SPAdj;
149 return SPAdj;
150 }
151
152 // To know whether a call adjusts the stack, we need information
153 // that is bound to the following ADJCALLSTACKUP pseudo.
154 // Look for the next ADJCALLSTACKUP that follows the call.
155 if (MI.isCall()) {
156 const MachineBasicBlock *MBB = MI.getParent();
157 auto I = ++MachineBasicBlock::const_iterator(MI);
158 for (auto E = MBB->end(); I != E; ++I) {
159 if (I->getOpcode() == getCallFrameDestroyOpcode() ||
160 I->isCall())
161 break;
162 }
163
164 // If we could not find a frame destroy opcode, then it has already
165 // been simplified, so we don't care.
166 if (I->getOpcode() != getCallFrameDestroyOpcode())
167 return 0;
168
169 return -(I->getOperand(1).getImm());
170 }
171
172 // Currently handle only PUSHes we can reasonably expect to see
173 // in call sequences
174 switch (MI.getOpcode()) {
175 default:
176 return 0;
177 case X86::PUSH32i8:
178 case X86::PUSH32r:
179 case X86::PUSH32rmm:
180 case X86::PUSH32rmr:
181 case X86::PUSHi32:
182 return 4;
183 case X86::PUSH64i8:
184 case X86::PUSH64r:
185 case X86::PUSH64rmm:
186 case X86::PUSH64rmr:
187 case X86::PUSH64i32:
188 return 8;
189 }
190}
191
192/// Return true and the FrameIndex if the specified
193/// operand and follow operands form a reference to the stack frame.
194bool X86InstrInfo::isFrameOperand(const MachineInstr &MI, unsigned int Op,
195 int &FrameIndex) const {
196 if (MI.getOperand(Op + X86::AddrBaseReg).isFI() &&
197 MI.getOperand(Op + X86::AddrScaleAmt).isImm() &&
198 MI.getOperand(Op + X86::AddrIndexReg).isReg() &&
199 MI.getOperand(Op + X86::AddrDisp).isImm() &&
200 MI.getOperand(Op + X86::AddrScaleAmt).getImm() == 1 &&
201 MI.getOperand(Op + X86::AddrIndexReg).getReg() == 0 &&
202 MI.getOperand(Op + X86::AddrDisp).getImm() == 0) {
203 FrameIndex = MI.getOperand(Op + X86::AddrBaseReg).getIndex();
204 return true;
205 }
206 return false;
207}
208
209static bool isFrameLoadOpcode(int Opcode, unsigned &MemBytes) {
210 switch (Opcode) {
211 default:
212 return false;
213 case X86::MOV8rm:
214 case X86::KMOVBkm:
215 MemBytes = 1;
216 return true;
217 case X86::MOV16rm:
218 case X86::KMOVWkm:
219 MemBytes = 2;
220 return true;
221 case X86::MOV32rm:
222 case X86::MOVSSrm:
223 case X86::VMOVSSZrm:
224 case X86::VMOVSSrm:
225 case X86::KMOVDkm:
226 MemBytes = 4;
227 return true;
228 case X86::MOV64rm:
229 case X86::LD_Fp64m:
230 case X86::MOVSDrm:
231 case X86::VMOVSDrm:
232 case X86::VMOVSDZrm:
233 case X86::MMX_MOVD64rm:
234 case X86::MMX_MOVQ64rm:
235 case X86::KMOVQkm:
236 MemBytes = 8;
237 return true;
238 case X86::MOVAPSrm:
239 case X86::MOVUPSrm:
240 case X86::MOVAPDrm:
241 case X86::MOVUPDrm:
242 case X86::MOVDQArm:
243 case X86::MOVDQUrm:
244 case X86::VMOVAPSrm:
245 case X86::VMOVUPSrm:
246 case X86::VMOVAPDrm:
247 case X86::VMOVUPDrm:
248 case X86::VMOVDQArm:
249 case X86::VMOVDQUrm:
250 case X86::VMOVAPSZ128rm:
251 case X86::VMOVUPSZ128rm:
252 case X86::VMOVAPSZ128rm_NOVLX:
253 case X86::VMOVUPSZ128rm_NOVLX:
254 case X86::VMOVAPDZ128rm:
255 case X86::VMOVUPDZ128rm:
256 case X86::VMOVDQU8Z128rm:
257 case X86::VMOVDQU16Z128rm:
258 case X86::VMOVDQA32Z128rm:
259 case X86::VMOVDQU32Z128rm:
260 case X86::VMOVDQA64Z128rm:
261 case X86::VMOVDQU64Z128rm:
262 MemBytes = 16;
263 return true;
264 case X86::VMOVAPSYrm:
265 case X86::VMOVUPSYrm:
266 case X86::VMOVAPDYrm:
267 case X86::VMOVUPDYrm:
268 case X86::VMOVDQAYrm:
269 case X86::VMOVDQUYrm:
270 case X86::VMOVAPSZ256rm:
271 case X86::VMOVUPSZ256rm:
272 case X86::VMOVAPSZ256rm_NOVLX:
273 case X86::VMOVUPSZ256rm_NOVLX:
274 case X86::VMOVAPDZ256rm:
275 case X86::VMOVUPDZ256rm:
276 case X86::VMOVDQU8Z256rm:
277 case X86::VMOVDQU16Z256rm:
278 case X86::VMOVDQA32Z256rm:
279 case X86::VMOVDQU32Z256rm:
280 case X86::VMOVDQA64Z256rm:
281 case X86::VMOVDQU64Z256rm:
282 MemBytes = 32;
283 return true;
284 case X86::VMOVAPSZrm:
285 case X86::VMOVUPSZrm:
286 case X86::VMOVAPDZrm:
287 case X86::VMOVUPDZrm:
288 case X86::VMOVDQU8Zrm:
289 case X86::VMOVDQU16Zrm:
290 case X86::VMOVDQA32Zrm:
291 case X86::VMOVDQU32Zrm:
292 case X86::VMOVDQA64Zrm:
293 case X86::VMOVDQU64Zrm:
294 MemBytes = 64;
295 return true;
296 }
297}
298
299static bool isFrameStoreOpcode(int Opcode, unsigned &MemBytes) {
300 switch (Opcode) {
301 default:
302 return false;
303 case X86::MOV8mr:
304 case X86::KMOVBmk:
305 MemBytes = 1;
306 return true;
307 case X86::MOV16mr:
308 case X86::KMOVWmk:
309 MemBytes = 2;
310 return true;
311 case X86::MOV32mr:
312 case X86::MOVSSmr:
313 case X86::VMOVSSmr:
314 case X86::VMOVSSZmr:
315 case X86::KMOVDmk:
316 MemBytes = 4;
317 return true;
318 case X86::MOV64mr:
319 case X86::ST_FpP64m:
320 case X86::MOVSDmr:
321 case X86::VMOVSDmr:
322 case X86::VMOVSDZmr:
323 case X86::MMX_MOVD64mr:
324 case X86::MMX_MOVQ64mr:
325 case X86::MMX_MOVNTQmr:
326 case X86::KMOVQmk:
327 MemBytes = 8;
328 return true;
329 case X86::MOVAPSmr:
330 case X86::MOVUPSmr:
331 case X86::MOVAPDmr:
332 case X86::MOVUPDmr:
333 case X86::MOVDQAmr:
334 case X86::MOVDQUmr:
335 case X86::VMOVAPSmr:
336 case X86::VMOVUPSmr:
337 case X86::VMOVAPDmr:
338 case X86::VMOVUPDmr:
339 case X86::VMOVDQAmr:
340 case X86::VMOVDQUmr:
341 case X86::VMOVUPSZ128mr:
342 case X86::VMOVAPSZ128mr:
343 case X86::VMOVUPSZ128mr_NOVLX:
344 case X86::VMOVAPSZ128mr_NOVLX:
345 case X86::VMOVUPDZ128mr:
346 case X86::VMOVAPDZ128mr:
347 case X86::VMOVDQA32Z128mr:
348 case X86::VMOVDQU32Z128mr:
349 case X86::VMOVDQA64Z128mr:
350 case X86::VMOVDQU64Z128mr:
351 case X86::VMOVDQU8Z128mr:
352 case X86::VMOVDQU16Z128mr:
353 MemBytes = 16;
354 return true;
355 case X86::VMOVUPSYmr:
356 case X86::VMOVAPSYmr:
357 case X86::VMOVUPDYmr:
358 case X86::VMOVAPDYmr:
359 case X86::VMOVDQUYmr:
360 case X86::VMOVDQAYmr:
361 case X86::VMOVUPSZ256mr:
362 case X86::VMOVAPSZ256mr:
363 case X86::VMOVUPSZ256mr_NOVLX:
364 case X86::VMOVAPSZ256mr_NOVLX:
365 case X86::VMOVUPDZ256mr:
366 case X86::VMOVAPDZ256mr:
367 case X86::VMOVDQU8Z256mr:
368 case X86::VMOVDQU16Z256mr:
369 case X86::VMOVDQA32Z256mr:
370 case X86::VMOVDQU32Z256mr:
371 case X86::VMOVDQA64Z256mr:
372 case X86::VMOVDQU64Z256mr:
373 MemBytes = 32;
374 return true;
375 case X86::VMOVUPSZmr:
376 case X86::VMOVAPSZmr:
377 case X86::VMOVUPDZmr:
378 case X86::VMOVAPDZmr:
379 case X86::VMOVDQU8Zmr:
380 case X86::VMOVDQU16Zmr:
381 case X86::VMOVDQA32Zmr:
382 case X86::VMOVDQU32Zmr:
383 case X86::VMOVDQA64Zmr:
384 case X86::VMOVDQU64Zmr:
385 MemBytes = 64;
386 return true;
387 }
388 return false;
389}
390
391unsigned X86InstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
392 int &FrameIndex) const {
393 unsigned Dummy;
394 return X86InstrInfo::isLoadFromStackSlot(MI, FrameIndex, Dummy);
395}
396
397unsigned X86InstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
398 int &FrameIndex,
399 unsigned &MemBytes) const {
400 if (isFrameLoadOpcode(MI.getOpcode(), MemBytes))
401 if (MI.getOperand(0).getSubReg() == 0 && isFrameOperand(MI, 1, FrameIndex))
402 return MI.getOperand(0).getReg();
403 return 0;
404}
405
406unsigned X86InstrInfo::isLoadFromStackSlotPostFE(const MachineInstr &MI,
407 int &FrameIndex) const {
408 unsigned Dummy;
409 if (isFrameLoadOpcode(MI.getOpcode(), Dummy)) {
410 unsigned Reg;
411 if ((Reg = isLoadFromStackSlot(MI, FrameIndex)))
412 return Reg;
413 // Check for post-frame index elimination operations
414 SmallVector<const MachineMemOperand *, 1> Accesses;
415 if (hasLoadFromStackSlot(MI, Accesses)) {
416 FrameIndex =
417 cast<FixedStackPseudoSourceValue>(Accesses.front()->getPseudoValue())
418 ->getFrameIndex();
419 return 1;
420 }
421 }
422 return 0;
423}
424
425unsigned X86InstrInfo::isStoreToStackSlot(const MachineInstr &MI,
426 int &FrameIndex) const {
427 unsigned Dummy;
428 return X86InstrInfo::isStoreToStackSlot(MI, FrameIndex, Dummy);
429}
430
431unsigned X86InstrInfo::isStoreToStackSlot(const MachineInstr &MI,
432 int &FrameIndex,
433 unsigned &MemBytes) const {
434 if (isFrameStoreOpcode(MI.getOpcode(), MemBytes))
435 if (MI.getOperand(X86::AddrNumOperands).getSubReg() == 0 &&
436 isFrameOperand(MI, 0, FrameIndex))
437 return MI.getOperand(X86::AddrNumOperands).getReg();
438 return 0;
439}
440
441unsigned X86InstrInfo::isStoreToStackSlotPostFE(const MachineInstr &MI,
442 int &FrameIndex) const {
443 unsigned Dummy;
444 if (isFrameStoreOpcode(MI.getOpcode(), Dummy)) {
445 unsigned Reg;
446 if ((Reg = isStoreToStackSlot(MI, FrameIndex)))
447 return Reg;
448 // Check for post-frame index elimination operations
449 SmallVector<const MachineMemOperand *, 1> Accesses;
450 if (hasStoreToStackSlot(MI, Accesses)) {
451 FrameIndex =
452 cast<FixedStackPseudoSourceValue>(Accesses.front()->getPseudoValue())
453 ->getFrameIndex();
454 return 1;
455 }
456 }
457 return 0;
458}
459
460/// Return true if register is PIC base; i.e.g defined by X86::MOVPC32r.
461static bool regIsPICBase(unsigned BaseReg, const MachineRegisterInfo &MRI) {
462 // Don't waste compile time scanning use-def chains of physregs.
463 if (!TargetRegisterInfo::isVirtualRegister(BaseReg))
464 return false;
465 bool isPICBase = false;
466 for (MachineRegisterInfo::def_instr_iterator I = MRI.def_instr_begin(BaseReg),
467 E = MRI.def_instr_end(); I != E; ++I) {
468 MachineInstr *DefMI = &*I;
469 if (DefMI->getOpcode() != X86::MOVPC32r)
470 return false;
471 assert(!isPICBase && "More than one PIC base?")((!isPICBase && "More than one PIC base?") ? static_cast
<void> (0) : __assert_fail ("!isPICBase && \"More than one PIC base?\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/X86/X86InstrInfo.cpp"
, 471, __PRETTY_FUNCTION__))
;
472 isPICBase = true;
473 }
474 return isPICBase;
475}
476
477bool X86InstrInfo::isReallyTriviallyReMaterializable(const MachineInstr &MI,
478 AliasAnalysis *AA) const {
479 switch (MI.getOpcode()) {
480 default: break;
481 case X86::MOV8rm:
482 case X86::MOV8rm_NOREX:
483 case X86::MOV16rm:
484 case X86::MOV32rm:
485 case X86::MOV64rm:
486 case X86::LD_Fp64m:
487 case X86::MOVSSrm:
488 case X86::MOVSDrm:
489 case X86::MOVAPSrm:
490 case X86::MOVUPSrm:
491 case X86::MOVAPDrm:
492 case X86::MOVUPDrm:
493 case X86::MOVDQArm:
494 case X86::MOVDQUrm:
495 case X86::VMOVSSrm:
496 case X86::VMOVSDrm:
497 case X86::VMOVAPSrm:
498 case X86::VMOVUPSrm:
499 case X86::VMOVAPDrm:
500 case X86::VMOVUPDrm:
501 case X86::VMOVDQArm:
502 case X86::VMOVDQUrm:
503 case X86::VMOVAPSYrm:
504 case X86::VMOVUPSYrm:
505 case X86::VMOVAPDYrm:
506 case X86::VMOVUPDYrm:
507 case X86::VMOVDQAYrm:
508 case X86::VMOVDQUYrm:
509 case X86::MMX_MOVD64rm:
510 case X86::MMX_MOVQ64rm:
511 // AVX-512
512 case X86::VMOVSSZrm:
513 case X86::VMOVSDZrm:
514 case X86::VMOVAPDZ128rm:
515 case X86::VMOVAPDZ256rm:
516 case X86::VMOVAPDZrm:
517 case X86::VMOVAPSZ128rm:
518 case X86::VMOVAPSZ256rm:
519 case X86::VMOVAPSZ128rm_NOVLX:
520 case X86::VMOVAPSZ256rm_NOVLX:
521 case X86::VMOVAPSZrm:
522 case X86::VMOVDQA32Z128rm:
523 case X86::VMOVDQA32Z256rm:
524 case X86::VMOVDQA32Zrm:
525 case X86::VMOVDQA64Z128rm:
526 case X86::VMOVDQA64Z256rm:
527 case X86::VMOVDQA64Zrm:
528 case X86::VMOVDQU16Z128rm:
529 case X86::VMOVDQU16Z256rm:
530 case X86::VMOVDQU16Zrm:
531 case X86::VMOVDQU32Z128rm:
532 case X86::VMOVDQU32Z256rm:
533 case X86::VMOVDQU32Zrm:
534 case X86::VMOVDQU64Z128rm:
535 case X86::VMOVDQU64Z256rm:
536 case X86::VMOVDQU64Zrm:
537 case X86::VMOVDQU8Z128rm:
538 case X86::VMOVDQU8Z256rm:
539 case X86::VMOVDQU8Zrm:
540 case X86::VMOVUPDZ128rm:
541 case X86::VMOVUPDZ256rm:
542 case X86::VMOVUPDZrm:
543 case X86::VMOVUPSZ128rm:
544 case X86::VMOVUPSZ256rm:
545 case X86::VMOVUPSZ128rm_NOVLX:
546 case X86::VMOVUPSZ256rm_NOVLX:
547 case X86::VMOVUPSZrm: {
548 // Loads from constant pools are trivially rematerializable.
549 if (MI.getOperand(1 + X86::AddrBaseReg).isReg() &&
550 MI.getOperand(1 + X86::AddrScaleAmt).isImm() &&
551 MI.getOperand(1 + X86::AddrIndexReg).isReg() &&
552 MI.getOperand(1 + X86::AddrIndexReg).getReg() == 0 &&
553 MI.isDereferenceableInvariantLoad(AA)) {
554 unsigned BaseReg = MI.getOperand(1 + X86::AddrBaseReg).getReg();
555 if (BaseReg == 0 || BaseReg == X86::RIP)
556 return true;
557 // Allow re-materialization of PIC load.
558 if (!ReMatPICStubLoad && MI.getOperand(1 + X86::AddrDisp).isGlobal())
559 return false;
560 const MachineFunction &MF = *MI.getParent()->getParent();
561 const MachineRegisterInfo &MRI = MF.getRegInfo();
562 return regIsPICBase(BaseReg, MRI);
563 }
564 return false;
565 }
566
567 case X86::LEA32r:
568 case X86::LEA64r: {
569 if (MI.getOperand(1 + X86::AddrScaleAmt).isImm() &&
570 MI.getOperand(1 + X86::AddrIndexReg).isReg() &&
571 MI.getOperand(1 + X86::AddrIndexReg).getReg() == 0 &&
572 !MI.getOperand(1 + X86::AddrDisp).isReg()) {
573 // lea fi#, lea GV, etc. are all rematerializable.
574 if (!MI.getOperand(1 + X86::AddrBaseReg).isReg())
575 return true;
576 unsigned BaseReg = MI.getOperand(1 + X86::AddrBaseReg).getReg();
577 if (BaseReg == 0)
578 return true;
579 // Allow re-materialization of lea PICBase + x.
580 const MachineFunction &MF = *MI.getParent()->getParent();
581 const MachineRegisterInfo &MRI = MF.getRegInfo();
582 return regIsPICBase(BaseReg, MRI);
583 }
584 return false;
585 }
586 }
587
588 // All other instructions marked M_REMATERIALIZABLE are always trivially
589 // rematerializable.
590 return true;
591}
592
593bool X86InstrInfo::isSafeToClobberEFLAGS(MachineBasicBlock &MBB,
594 MachineBasicBlock::iterator I) const {
595 MachineBasicBlock::iterator E = MBB.end();
596
597 // For compile time consideration, if we are not able to determine the
598 // safety after visiting 4 instructions in each direction, we will assume
599 // it's not safe.
600 MachineBasicBlock::iterator Iter = I;
601 for (unsigned i = 0; Iter != E && i < 4; ++i) {
602 bool SeenDef = false;
603 for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) {
604 MachineOperand &MO = Iter->getOperand(j);
605 if (MO.isRegMask() && MO.clobbersPhysReg(X86::EFLAGS))
606 SeenDef = true;
607 if (!MO.isReg())
608 continue;
609 if (MO.getReg() == X86::EFLAGS) {
610 if (MO.isUse())
611 return false;
612 SeenDef = true;
613 }
614 }
615
616 if (SeenDef)
617 // This instruction defines EFLAGS, no need to look any further.
618 return true;
619 ++Iter;
620 // Skip over debug instructions.
621 while (Iter != E && Iter->isDebugInstr())
622 ++Iter;
623 }
624
625 // It is safe to clobber EFLAGS at the end of a block of no successor has it
626 // live in.
627 if (Iter == E) {
628 for (MachineBasicBlock *S : MBB.successors())
629 if (S->isLiveIn(X86::EFLAGS))
630 return false;
631 return true;
632 }
633
634 MachineBasicBlock::iterator B = MBB.begin();
635 Iter = I;
636 for (unsigned i = 0; i < 4; ++i) {
637 // If we make it to the beginning of the block, it's safe to clobber
638 // EFLAGS iff EFLAGS is not live-in.
639 if (Iter == B)
640 return !MBB.isLiveIn(X86::EFLAGS);
641
642 --Iter;
643 // Skip over debug instructions.
644 while (Iter != B && Iter->isDebugInstr())
645 --Iter;
646
647 bool SawKill = false;
648 for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) {
649 MachineOperand &MO = Iter->getOperand(j);
650 // A register mask may clobber EFLAGS, but we should still look for a
651 // live EFLAGS def.
652 if (MO.isRegMask() && MO.clobbersPhysReg(X86::EFLAGS))
653 SawKill = true;
654 if (MO.isReg() && MO.getReg() == X86::EFLAGS) {
655 if (MO.isDef()) return MO.isDead();
656 if (MO.isKill()) SawKill = true;
657 }
658 }
659
660 if (SawKill)
661 // This instruction kills EFLAGS and doesn't redefine it, so
662 // there's no need to look further.
663 return true;
664 }
665
666 // Conservative answer.
667 return false;
668}
669
670void X86InstrInfo::reMaterialize(MachineBasicBlock &MBB,
671 MachineBasicBlock::iterator I,
672 unsigned DestReg, unsigned SubIdx,
673 const MachineInstr &Orig,
674 const TargetRegisterInfo &TRI) const {
675 bool ClobbersEFLAGS = false;
676 for (const MachineOperand &MO : Orig.operands()) {
677 if (MO.isReg() && MO.isDef() && MO.getReg() == X86::EFLAGS) {
678 ClobbersEFLAGS = true;
679 break;
680 }
681 }
682
683 if (ClobbersEFLAGS && !isSafeToClobberEFLAGS(MBB, I)) {
684 // The instruction clobbers EFLAGS. Re-materialize as MOV32ri to avoid side
685 // effects.
686 int Value;
687 switch (Orig.getOpcode()) {
688 case X86::MOV32r0: Value = 0; break;
689 case X86::MOV32r1: Value = 1; break;
690 case X86::MOV32r_1: Value = -1; break;
691 default:
692 llvm_unreachable("Unexpected instruction!")::llvm::llvm_unreachable_internal("Unexpected instruction!", "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/X86/X86InstrInfo.cpp"
, 692)
;
693 }
694
695 const DebugLoc &DL = Orig.getDebugLoc();
696 BuildMI(MBB, I, DL, get(X86::MOV32ri))
697 .add(Orig.getOperand(0))
698 .addImm(Value);
699 } else {
700 MachineInstr *MI = MBB.getParent()->CloneMachineInstr(&Orig);
701 MBB.insert(I, MI);
702 }
703
704 MachineInstr &NewMI = *std::prev(I);
705 NewMI.substituteRegister(Orig.getOperand(0).getReg(), DestReg, SubIdx, TRI);
706}
707
708/// True if MI has a condition code def, e.g. EFLAGS, that is not marked dead.
709bool X86InstrInfo::hasLiveCondCodeDef(MachineInstr &MI) const {
710 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
711 MachineOperand &MO = MI.getOperand(i);
712 if (MO.isReg() && MO.isDef() &&
713 MO.getReg() == X86::EFLAGS && !MO.isDead()) {
714 return true;
715 }
716 }
717 return false;
718}
719
720/// Check whether the shift count for a machine operand is non-zero.
721inline static unsigned getTruncatedShiftCount(const MachineInstr &MI,
722 unsigned ShiftAmtOperandIdx) {
723 // The shift count is six bits with the REX.W prefix and five bits without.
724 unsigned ShiftCountMask = (MI.getDesc().TSFlags & X86II::REX_W) ? 63 : 31;
725 unsigned Imm = MI.getOperand(ShiftAmtOperandIdx).getImm();
726 return Imm & ShiftCountMask;
727}
728
729/// Check whether the given shift count is appropriate
730/// can be represented by a LEA instruction.
731inline static bool isTruncatedShiftCountForLEA(unsigned ShAmt) {
732 // Left shift instructions can be transformed into load-effective-address
733 // instructions if we can encode them appropriately.
734 // A LEA instruction utilizes a SIB byte to encode its scale factor.
735 // The SIB.scale field is two bits wide which means that we can encode any
736 // shift amount less than 4.
737 return ShAmt < 4 && ShAmt > 0;
738}
739
740bool X86InstrInfo::classifyLEAReg(MachineInstr &MI, const MachineOperand &Src,
741 unsigned Opc, bool AllowSP, unsigned &NewSrc,
742 bool &isKill, MachineOperand &ImplicitOp,
743 LiveVariables *LV) const {
744 MachineFunction &MF = *MI.getParent()->getParent();
745 const TargetRegisterClass *RC;
746 if (AllowSP) {
747 RC = Opc != X86::LEA32r ? &X86::GR64RegClass : &X86::GR32RegClass;
748 } else {
749 RC = Opc != X86::LEA32r ?
750 &X86::GR64_NOSPRegClass : &X86::GR32_NOSPRegClass;
751 }
752 unsigned SrcReg = Src.getReg();
753
754 // For both LEA64 and LEA32 the register already has essentially the right
755 // type (32-bit or 64-bit) we may just need to forbid SP.
756 if (Opc != X86::LEA64_32r) {
757 NewSrc = SrcReg;
758 isKill = Src.isKill();
759 assert(!Src.isUndef() && "Undef op doesn't need optimization")((!Src.isUndef() && "Undef op doesn't need optimization"
) ? static_cast<void> (0) : __assert_fail ("!Src.isUndef() && \"Undef op doesn't need optimization\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/X86/X86InstrInfo.cpp"
, 759, __PRETTY_FUNCTION__))
;
760
761 if (TargetRegisterInfo::isVirtualRegister(NewSrc) &&
762 !MF.getRegInfo().constrainRegClass(NewSrc, RC))
763 return false;
764
765 return true;
766 }
767
768 // This is for an LEA64_32r and incoming registers are 32-bit. One way or
769 // another we need to add 64-bit registers to the final MI.
770 if (TargetRegisterInfo::isPhysicalRegister(SrcReg)) {
771 ImplicitOp = Src;
772 ImplicitOp.setImplicit();
773
774 NewSrc = getX86SubSuperRegister(Src.getReg(), 64);
775 isKill = Src.isKill();
776 assert(!Src.isUndef() && "Undef op doesn't need optimization")((!Src.isUndef() && "Undef op doesn't need optimization"
) ? static_cast<void> (0) : __assert_fail ("!Src.isUndef() && \"Undef op doesn't need optimization\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/X86/X86InstrInfo.cpp"
, 776, __PRETTY_FUNCTION__))
;
777 } else {
778 // Virtual register of the wrong class, we have to create a temporary 64-bit
779 // vreg to feed into the LEA.
780 NewSrc = MF.getRegInfo().createVirtualRegister(RC);
781 MachineInstr *Copy =
782 BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(TargetOpcode::COPY))
783 .addReg(NewSrc, RegState::Define | RegState::Undef, X86::sub_32bit)
784 .add(Src);
785
786 // Which is obviously going to be dead after we're done with it.
787 isKill = true;
788
789 if (LV)
790 LV->replaceKillInstruction(SrcReg, MI, *Copy);
791 }
792
793 // We've set all the parameters without issue.
794 return true;
795}
796
797MachineInstr *X86InstrInfo::convertToThreeAddressWithLEA(
798 unsigned MIOpc, MachineFunction::iterator &MFI, MachineInstr &MI,
799 LiveVariables *LV) const {
800 // We handle 8-bit adds and various 16-bit opcodes in the switch below.
801 bool Is16BitOp = !(MIOpc == X86::ADD8rr || MIOpc == X86::ADD8ri);
802 MachineRegisterInfo &RegInfo = MFI->getParent()->getRegInfo();
803 assert((!Is16BitOp || RegInfo.getTargetRegisterInfo()->getRegSizeInBits((((!Is16BitOp || RegInfo.getTargetRegisterInfo()->getRegSizeInBits
( *RegInfo.getRegClass(MI.getOperand(0).getReg())) == 16) &&
"Unexpected type for LEA transform") ? static_cast<void>
(0) : __assert_fail ("(!Is16BitOp || RegInfo.getTargetRegisterInfo()->getRegSizeInBits( *RegInfo.getRegClass(MI.getOperand(0).getReg())) == 16) && \"Unexpected type for LEA transform\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/X86/X86InstrInfo.cpp"
, 805, __PRETTY_FUNCTION__))
804 *RegInfo.getRegClass(MI.getOperand(0).getReg())) == 16) &&(((!Is16BitOp || RegInfo.getTargetRegisterInfo()->getRegSizeInBits
( *RegInfo.getRegClass(MI.getOperand(0).getReg())) == 16) &&
"Unexpected type for LEA transform") ? static_cast<void>
(0) : __assert_fail ("(!Is16BitOp || RegInfo.getTargetRegisterInfo()->getRegSizeInBits( *RegInfo.getRegClass(MI.getOperand(0).getReg())) == 16) && \"Unexpected type for LEA transform\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/X86/X86InstrInfo.cpp"
, 805, __PRETTY_FUNCTION__))
805 "Unexpected type for LEA transform")(((!Is16BitOp || RegInfo.getTargetRegisterInfo()->getRegSizeInBits
( *RegInfo.getRegClass(MI.getOperand(0).getReg())) == 16) &&
"Unexpected type for LEA transform") ? static_cast<void>
(0) : __assert_fail ("(!Is16BitOp || RegInfo.getTargetRegisterInfo()->getRegSizeInBits( *RegInfo.getRegClass(MI.getOperand(0).getReg())) == 16) && \"Unexpected type for LEA transform\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/X86/X86InstrInfo.cpp"
, 805, __PRETTY_FUNCTION__))
;
806
807 // TODO: For a 32-bit target, we need to adjust the LEA variables with
808 // something like this:
809 // Opcode = X86::LEA32r;
810 // InRegLEA = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
811 // OutRegLEA =
812 // Is8BitOp ? RegInfo.createVirtualRegister(&X86::GR32ABCD_RegClass)
813 // : RegInfo.createVirtualRegister(&X86::GR32RegClass);
814 if (!Subtarget.is64Bit())
815 return nullptr;
816
817 unsigned Opcode = X86::LEA64_32r;
818 unsigned InRegLEA = RegInfo.createVirtualRegister(&X86::GR64_NOSPRegClass);
819 unsigned OutRegLEA = RegInfo.createVirtualRegister(&X86::GR32RegClass);
820
821 // Build and insert into an implicit UNDEF value. This is OK because
822 // we will be shifting and then extracting the lower 8/16-bits.
823 // This has the potential to cause partial register stall. e.g.
824 // movw (%rbp,%rcx,2), %dx
825 // leal -65(%rdx), %esi
826 // But testing has shown this *does* help performance in 64-bit mode (at
827 // least on modern x86 machines).
828 MachineBasicBlock::iterator MBBI = MI.getIterator();
829 unsigned Dest = MI.getOperand(0).getReg();
830 unsigned Src = MI.getOperand(1).getReg();
831 bool IsDead = MI.getOperand(0).isDead();
832 bool IsKill = MI.getOperand(1).isKill();
833 unsigned SubReg = Is16BitOp ? X86::sub_16bit : X86::sub_8bit;
834 assert(!MI.getOperand(1).isUndef() && "Undef op doesn't need optimization")((!MI.getOperand(1).isUndef() && "Undef op doesn't need optimization"
) ? static_cast<void> (0) : __assert_fail ("!MI.getOperand(1).isUndef() && \"Undef op doesn't need optimization\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/X86/X86InstrInfo.cpp"
, 834, __PRETTY_FUNCTION__))
;
835 BuildMI(*MFI, MBBI, MI.getDebugLoc(), get(X86::IMPLICIT_DEF), InRegLEA);
836 MachineInstr *InsMI =
837 BuildMI(*MFI, MBBI, MI.getDebugLoc(), get(TargetOpcode::COPY))
838 .addReg(InRegLEA, RegState::Define, SubReg)
839 .addReg(Src, getKillRegState(IsKill));
840
841 MachineInstrBuilder MIB =
842 BuildMI(*MFI, MBBI, MI.getDebugLoc(), get(Opcode), OutRegLEA);
843 switch (MIOpc) {
844 default: llvm_unreachable("Unreachable!")::llvm::llvm_unreachable_internal("Unreachable!", "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/X86/X86InstrInfo.cpp"
, 844)
;
845 case X86::SHL16ri: {
846 unsigned ShAmt = MI.getOperand(2).getImm();
847 MIB.addReg(0).addImm(1ULL << ShAmt)
848 .addReg(InRegLEA, RegState::Kill).addImm(0).addReg(0);
849 break;
850 }
851 case X86::INC16r:
852 addRegOffset(MIB, InRegLEA, true, 1);
853 break;
854 case X86::DEC16r:
855 addRegOffset(MIB, InRegLEA, true, -1);
856 break;
857 case X86::ADD8ri:
858 case X86::ADD16ri:
859 case X86::ADD16ri8:
860 case X86::ADD16ri_DB:
861 case X86::ADD16ri8_DB:
862 addRegOffset(MIB, InRegLEA, true, MI.getOperand(2).getImm());
863 break;
864 case X86::ADD8rr:
865 case X86::ADD16rr:
866 case X86::ADD16rr_DB: {
867 unsigned Src2 = MI.getOperand(2).getReg();
868 bool IsKill2 = MI.getOperand(2).isKill();
869 assert(!MI.getOperand(2).isUndef() && "Undef op doesn't need optimization")((!MI.getOperand(2).isUndef() && "Undef op doesn't need optimization"
) ? static_cast<void> (0) : __assert_fail ("!MI.getOperand(2).isUndef() && \"Undef op doesn't need optimization\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/X86/X86InstrInfo.cpp"
, 869, __PRETTY_FUNCTION__))
;
870 unsigned InRegLEA2 = 0;
871 MachineInstr *InsMI2 = nullptr;
872 if (Src == Src2) {
873 // ADD8rr/ADD16rr killed %reg1028, %reg1028
874 // just a single insert_subreg.
875 addRegReg(MIB, InRegLEA, true, InRegLEA, false);
876 } else {
877 if (Subtarget.is64Bit())
878 InRegLEA2 = RegInfo.createVirtualRegister(&X86::GR64_NOSPRegClass);
879 else
880 InRegLEA2 = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
881 // Build and insert into an implicit UNDEF value. This is OK because
882 // we will be shifting and then extracting the lower 8/16-bits.
883 BuildMI(*MFI, &*MIB, MI.getDebugLoc(), get(X86::IMPLICIT_DEF), InRegLEA2);
884 InsMI2 = BuildMI(*MFI, &*MIB, MI.getDebugLoc(), get(TargetOpcode::COPY))
885 .addReg(InRegLEA2, RegState::Define, SubReg)
886 .addReg(Src2, getKillRegState(IsKill2));
887 addRegReg(MIB, InRegLEA, true, InRegLEA2, true);
888 }
889 if (LV && IsKill2 && InsMI2)
890 LV->replaceKillInstruction(Src2, MI, *InsMI2);
891 break;
892 }
893 }
894
895 MachineInstr *NewMI = MIB;
896 MachineInstr *ExtMI =
897 BuildMI(*MFI, MBBI, MI.getDebugLoc(), get(TargetOpcode::COPY))
898 .addReg(Dest, RegState::Define | getDeadRegState(IsDead))
899 .addReg(OutRegLEA, RegState::Kill, SubReg);
900
901 if (LV) {
902 // Update live variables.
903 LV->getVarInfo(InRegLEA).Kills.push_back(NewMI);
904 LV->getVarInfo(OutRegLEA).Kills.push_back(ExtMI);
905 if (IsKill)
906 LV->replaceKillInstruction(Src, MI, *InsMI);
907 if (IsDead)
908 LV->replaceKillInstruction(Dest, MI, *ExtMI);
909 }
910
911 return ExtMI;
912}
913
914/// This method must be implemented by targets that
915/// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
916/// may be able to convert a two-address instruction into a true
917/// three-address instruction on demand. This allows the X86 target (for
918/// example) to convert ADD and SHL instructions into LEA instructions if they
919/// would require register copies due to two-addressness.
920///
921/// This method returns a null pointer if the transformation cannot be
922/// performed, otherwise it returns the new instruction.
923///
924MachineInstr *
925X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
926 MachineInstr &MI, LiveVariables *LV) const {
927 // The following opcodes also sets the condition code register(s). Only
928 // convert them to equivalent lea if the condition code register def's
929 // are dead!
930 if (hasLiveCondCodeDef(MI))
931 return nullptr;
932
933 MachineFunction &MF = *MI.getParent()->getParent();
934 // All instructions input are two-addr instructions. Get the known operands.
935 const MachineOperand &Dest = MI.getOperand(0);
936 const MachineOperand &Src = MI.getOperand(1);
937
938 // Ideally, operations with undef should be folded before we get here, but we
939 // can't guarantee it. Bail out because optimizing undefs is a waste of time.
940 // Without this, we have to forward undef state to new register operands to
941 // avoid machine verifier errors.
942 if (Src.isUndef())
943 return nullptr;
944 if (MI.getNumOperands() > 2)
945 if (MI.getOperand(2).isReg() && MI.getOperand(2).isUndef())
946 return nullptr;
947
948 MachineInstr *NewMI = nullptr;
949 bool Is64Bit = Subtarget.is64Bit();
950
951 unsigned MIOpc = MI.getOpcode();
952 switch (MIOpc) {
953 default: return nullptr;
954 case X86::SHL64ri: {
955 assert(MI.getNumOperands() >= 3 && "Unknown shift instruction!")((MI.getNumOperands() >= 3 && "Unknown shift instruction!"
) ? static_cast<void> (0) : __assert_fail ("MI.getNumOperands() >= 3 && \"Unknown shift instruction!\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/X86/X86InstrInfo.cpp"
, 955, __PRETTY_FUNCTION__))
;
956 unsigned ShAmt = getTruncatedShiftCount(MI, 2);
957 if (!isTruncatedShiftCountForLEA(ShAmt)) return nullptr;
958
959 // LEA can't handle RSP.
960 if (TargetRegisterInfo::isVirtualRegister(Src.getReg()) &&
961 !MF.getRegInfo().constrainRegClass(Src.getReg(),
962 &X86::GR64_NOSPRegClass))
963 return nullptr;
964
965 NewMI = BuildMI(MF, MI.getDebugLoc(), get(X86::LEA64r))
966 .add(Dest)
967 .addReg(0)
968 .addImm(1ULL << ShAmt)
969 .add(Src)
970 .addImm(0)
971 .addReg(0);
972 break;
973 }
974 case X86::SHL32ri: {
975 assert(MI.getNumOperands() >= 3 && "Unknown shift instruction!")((MI.getNumOperands() >= 3 && "Unknown shift instruction!"
) ? static_cast<void> (0) : __assert_fail ("MI.getNumOperands() >= 3 && \"Unknown shift instruction!\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/X86/X86InstrInfo.cpp"
, 975, __PRETTY_FUNCTION__))
;
976 unsigned ShAmt = getTruncatedShiftCount(MI, 2);
977 if (!isTruncatedShiftCountForLEA(ShAmt)) return nullptr;
978
979 unsigned Opc = Is64Bit ? X86::LEA64_32r : X86::LEA32r;
980
981 // LEA can't handle ESP.
982 bool isKill;
983 unsigned SrcReg;
984 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
985 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false,
986 SrcReg, isKill, ImplicitOp, LV))
987 return nullptr;
988
989 MachineInstrBuilder MIB =
990 BuildMI(MF, MI.getDebugLoc(), get(Opc))
991 .add(Dest)
992 .addReg(0)
993 .addImm(1ULL << ShAmt)
994 .addReg(SrcReg, getKillRegState(isKill))
995 .addImm(0)
996 .addReg(0);
997 if (ImplicitOp.getReg() != 0)
998 MIB.add(ImplicitOp);
999 NewMI = MIB;
1000
1001 break;
1002 }
1003 case X86::SHL16ri: {
1004 assert(MI.getNumOperands() >= 3 && "Unknown shift instruction!")((MI.getNumOperands() >= 3 && "Unknown shift instruction!"
) ? static_cast<void> (0) : __assert_fail ("MI.getNumOperands() >= 3 && \"Unknown shift instruction!\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/X86/X86InstrInfo.cpp"
, 1004, __PRETTY_FUNCTION__))
;
1005 unsigned ShAmt = getTruncatedShiftCount(MI, 2);
1006 if (!isTruncatedShiftCountForLEA(ShAmt))
1007 return nullptr;
1008 return convertToThreeAddressWithLEA(MIOpc, MFI, MI, LV);
1009 }
1010 case X86::INC64r:
1011 case X86::INC32r: {
1012 assert(MI.getNumOperands() >= 2 && "Unknown inc instruction!")((MI.getNumOperands() >= 2 && "Unknown inc instruction!"
) ? static_cast<void> (0) : __assert_fail ("MI.getNumOperands() >= 2 && \"Unknown inc instruction!\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/X86/X86InstrInfo.cpp"
, 1012, __PRETTY_FUNCTION__))
;
1013 unsigned Opc = MIOpc == X86::INC64r ? X86::LEA64r :
1014 (Is64Bit ? X86::LEA64_32r : X86::LEA32r);
1015 bool isKill;
1016 unsigned SrcReg;
1017 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
1018 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false, SrcReg, isKill,
1019 ImplicitOp, LV))
1020 return nullptr;
1021
1022 MachineInstrBuilder MIB =
1023 BuildMI(MF, MI.getDebugLoc(), get(Opc))
1024 .add(Dest)
1025 .addReg(SrcReg, getKillRegState(isKill));
1026 if (ImplicitOp.getReg() != 0)
1027 MIB.add(ImplicitOp);
1028
1029 NewMI = addOffset(MIB, 1);
1030 break;
1031 }
1032 case X86::INC16r:
1033 return convertToThreeAddressWithLEA(MIOpc, MFI, MI, LV);
1034 case X86::DEC64r:
1035 case X86::DEC32r: {
1036 assert(MI.getNumOperands() >= 2 && "Unknown dec instruction!")((MI.getNumOperands() >= 2 && "Unknown dec instruction!"
) ? static_cast<void> (0) : __assert_fail ("MI.getNumOperands() >= 2 && \"Unknown dec instruction!\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/X86/X86InstrInfo.cpp"
, 1036, __PRETTY_FUNCTION__))
;
1037 unsigned Opc = MIOpc == X86::DEC64r ? X86::LEA64r
1038 : (Is64Bit ? X86::LEA64_32r : X86::LEA32r);
1039
1040 bool isKill;
1041 unsigned SrcReg;
1042 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
1043 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false, SrcReg, isKill,
1044 ImplicitOp, LV))
1045 return nullptr;
1046
1047 MachineInstrBuilder MIB = BuildMI(MF, MI.getDebugLoc(), get(Opc))
1048 .add(Dest)
1049 .addReg(SrcReg, getKillRegState(isKill));
1050 if (ImplicitOp.getReg() != 0)
1051 MIB.add(ImplicitOp);
1052
1053 NewMI = addOffset(MIB, -1);
1054
1055 break;
1056 }
1057 case X86::DEC16r:
1058 return convertToThreeAddressWithLEA(MIOpc, MFI, MI, LV);
1059 case X86::ADD64rr:
1060 case X86::ADD64rr_DB:
1061 case X86::ADD32rr:
1062 case X86::ADD32rr_DB: {
1063 assert(MI.getNumOperands() >= 3 && "Unknown add instruction!")((MI.getNumOperands() >= 3 && "Unknown add instruction!"
) ? static_cast<void> (0) : __assert_fail ("MI.getNumOperands() >= 3 && \"Unknown add instruction!\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/X86/X86InstrInfo.cpp"
, 1063, __PRETTY_FUNCTION__))
;
1064 unsigned Opc;
1065 if (MIOpc == X86::ADD64rr || MIOpc == X86::ADD64rr_DB)
1066 Opc = X86::LEA64r;
1067 else
1068 Opc = Is64Bit ? X86::LEA64_32r : X86::LEA32r;
1069
1070 bool isKill;
1071 unsigned SrcReg;
1072 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
1073 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ true,
1074 SrcReg, isKill, ImplicitOp, LV))
1075 return nullptr;
1076
1077 const MachineOperand &Src2 = MI.getOperand(2);
1078 bool isKill2;
1079 unsigned SrcReg2;
1080 MachineOperand ImplicitOp2 = MachineOperand::CreateReg(0, false);
1081 if (!classifyLEAReg(MI, Src2, Opc, /*AllowSP=*/ false,
1082 SrcReg2, isKill2, ImplicitOp2, LV))
1083 return nullptr;
1084
1085 MachineInstrBuilder MIB = BuildMI(MF, MI.getDebugLoc(), get(Opc)).add(Dest);
1086 if (ImplicitOp.getReg() != 0)
1087 MIB.add(ImplicitOp);
1088 if (ImplicitOp2.getReg() != 0)
1089 MIB.add(ImplicitOp2);
1090
1091 NewMI = addRegReg(MIB, SrcReg, isKill, SrcReg2, isKill2);
1092 if (LV && Src2.isKill())
1093 LV->replaceKillInstruction(SrcReg2, MI, *NewMI);
1094 break;
1095 }
1096 case X86::ADD8rr:
1097 case X86::ADD16rr:
1098 case X86::ADD16rr_DB:
1099 return convertToThreeAddressWithLEA(MIOpc, MFI, MI, LV);
1100 case X86::ADD64ri32:
1101 case X86::ADD64ri8:
1102 case X86::ADD64ri32_DB:
1103 case X86::ADD64ri8_DB:
1104 assert(MI.getNumOperands() >= 3 && "Unknown add instruction!")((MI.getNumOperands() >= 3 && "Unknown add instruction!"
) ? static_cast<void> (0) : __assert_fail ("MI.getNumOperands() >= 3 && \"Unknown add instruction!\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/X86/X86InstrInfo.cpp"
, 1104, __PRETTY_FUNCTION__))
;
1105 NewMI = addOffset(
1106 BuildMI(MF, MI.getDebugLoc(), get(X86::LEA64r)).add(Dest).add(Src),
1107 MI.getOperand(2));
1108 break;
1109 case X86::ADD32ri:
1110 case X86::ADD32ri8:
1111 case X86::ADD32ri_DB:
1112 case X86::ADD32ri8_DB: {
1113 assert(MI.getNumOperands() >= 3 && "Unknown add instruction!")((MI.getNumOperands() >= 3 && "Unknown add instruction!"
) ? static_cast<void> (0) : __assert_fail ("MI.getNumOperands() >= 3 && \"Unknown add instruction!\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/X86/X86InstrInfo.cpp"
, 1113, __PRETTY_FUNCTION__))
;
1114 unsigned Opc = Is64Bit ? X86::LEA64_32r : X86::LEA32r;
1115
1116 bool isKill;
1117 unsigned SrcReg;
1118 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
1119 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ true,
1120 SrcReg, isKill, ImplicitOp, LV))
1121 return nullptr;
1122
1123 MachineInstrBuilder MIB = BuildMI(MF, MI.getDebugLoc(), get(Opc))
1124 .add(Dest)
1125 .addReg(SrcReg, getKillRegState(isKill));
1126 if (ImplicitOp.getReg() != 0)
1127 MIB.add(ImplicitOp);
1128
1129 NewMI = addOffset(MIB, MI.getOperand(2));
1130 break;
1131 }
1132 case X86::ADD8ri:
1133 case X86::ADD16ri:
1134 case X86::ADD16ri8:
1135 case X86::ADD16ri_DB:
1136 case X86::ADD16ri8_DB:
1137 return convertToThreeAddressWithLEA(MIOpc, MFI, MI, LV);
1138 case X86::VMOVDQU8Z128rmk:
1139 case X86::VMOVDQU8Z256rmk:
1140 case X86::VMOVDQU8Zrmk:
1141 case X86::VMOVDQU16Z128rmk:
1142 case X86::VMOVDQU16Z256rmk:
1143 case X86::VMOVDQU16Zrmk:
1144 case X86::VMOVDQU32Z128rmk: case X86::VMOVDQA32Z128rmk:
1145 case X86::VMOVDQU32Z256rmk: case X86::VMOVDQA32Z256rmk:
1146 case X86::VMOVDQU32Zrmk: case X86::VMOVDQA32Zrmk:
1147 case X86::VMOVDQU64Z128rmk: case X86::VMOVDQA64Z128rmk:
1148 case X86::VMOVDQU64Z256rmk: case X86::VMOVDQA64Z256rmk:
1149 case X86::VMOVDQU64Zrmk: case X86::VMOVDQA64Zrmk:
1150 case X86::VMOVUPDZ128rmk: case X86::VMOVAPDZ128rmk:
1151 case X86::VMOVUPDZ256rmk: case X86::VMOVAPDZ256rmk:
1152 case X86::VMOVUPDZrmk: case X86::VMOVAPDZrmk:
1153 case X86::VMOVUPSZ128rmk: case X86::VMOVAPSZ128rmk:
1154 case X86::VMOVUPSZ256rmk: case X86::VMOVAPSZ256rmk:
1155 case X86::VMOVUPSZrmk: case X86::VMOVAPSZrmk: {
1156 unsigned Opc;
1157 switch (MIOpc) {
1158 default: llvm_unreachable("Unreachable!")::llvm::llvm_unreachable_internal("Unreachable!", "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/X86/X86InstrInfo.cpp"
, 1158)
;
1159 case X86::VMOVDQU8Z128rmk: Opc = X86::VPBLENDMBZ128rmk; break;
1160 case X86::VMOVDQU8Z256rmk: Opc = X86::VPBLENDMBZ256rmk; break;
1161 case X86::VMOVDQU8Zrmk: Opc = X86::VPBLENDMBZrmk; break;
1162 case X86::VMOVDQU16Z128rmk: Opc = X86::VPBLENDMWZ128rmk; break;
1163 case X86::VMOVDQU16Z256rmk: Opc = X86::VPBLENDMWZ256rmk; break;
1164 case X86::VMOVDQU16Zrmk: Opc = X86::VPBLENDMWZrmk; break;
1165 case X86::VMOVDQU32Z128rmk: Opc = X86::VPBLENDMDZ128rmk; break;
1166 case X86::VMOVDQU32Z256rmk: Opc = X86::VPBLENDMDZ256rmk; break;
1167 case X86::VMOVDQU32Zrmk: Opc = X86::VPBLENDMDZrmk; break;
1168 case X86::VMOVDQU64Z128rmk: Opc = X86::VPBLENDMQZ128rmk; break;
1169 case X86::VMOVDQU64Z256rmk: Opc = X86::VPBLENDMQZ256rmk; break;
1170 case X86::VMOVDQU64Zrmk: Opc = X86::VPBLENDMQZrmk; break;
1171 case X86::VMOVUPDZ128rmk: Opc = X86::VBLENDMPDZ128rmk; break;
1172 case X86::VMOVUPDZ256rmk: Opc = X86::VBLENDMPDZ256rmk; break;
1173 case X86::VMOVUPDZrmk: Opc = X86::VBLENDMPDZrmk; break;
1174 case X86::VMOVUPSZ128rmk: Opc = X86::VBLENDMPSZ128rmk; break;
1175 case X86::VMOVUPSZ256rmk: Opc = X86::VBLENDMPSZ256rmk; break;
1176 case X86::VMOVUPSZrmk: Opc = X86::VBLENDMPSZrmk; break;
1177 case X86::VMOVDQA32Z128rmk: Opc = X86::VPBLENDMDZ128rmk; break;
1178 case X86::VMOVDQA32Z256rmk: Opc = X86::VPBLENDMDZ256rmk; break;
1179 case X86::VMOVDQA32Zrmk: Opc = X86::VPBLENDMDZrmk; break;
1180 case X86::VMOVDQA64Z128rmk: Opc = X86::VPBLENDMQZ128rmk; break;
1181 case X86::VMOVDQA64Z256rmk: Opc = X86::VPBLENDMQZ256rmk; break;
1182 case X86::VMOVDQA64Zrmk: Opc = X86::VPBLENDMQZrmk; break;
1183 case X86::VMOVAPDZ128rmk: Opc = X86::VBLENDMPDZ128rmk; break;
1184 case X86::VMOVAPDZ256rmk: Opc = X86::VBLENDMPDZ256rmk; break;
1185 case X86::VMOVAPDZrmk: Opc = X86::VBLENDMPDZrmk; break;
1186 case X86::VMOVAPSZ128rmk: Opc = X86::VBLENDMPSZ128rmk; break;
1187 case X86::VMOVAPSZ256rmk: Opc = X86::VBLENDMPSZ256rmk; break;
1188 case X86::VMOVAPSZrmk: Opc = X86::VBLENDMPSZrmk; break;
1189 }
1190
1191 NewMI = BuildMI(MF, MI.getDebugLoc(), get(Opc))
1192 .add(Dest)
1193 .add(MI.getOperand(2))
1194 .add(Src)
1195 .add(MI.getOperand(3))
1196 .add(MI.getOperand(4))
1197 .add(MI.getOperand(5))
1198 .add(MI.getOperand(6))
1199 .add(MI.getOperand(7));
1200 break;
1201 }
1202 case X86::VMOVDQU8Z128rrk:
1203 case X86::VMOVDQU8Z256rrk:
1204 case X86::VMOVDQU8Zrrk:
1205 case X86::VMOVDQU16Z128rrk:
1206 case X86::VMOVDQU16Z256rrk:
1207 case X86::VMOVDQU16Zrrk:
1208 case X86::VMOVDQU32Z128rrk: case X86::VMOVDQA32Z128rrk:
1209 case X86::VMOVDQU32Z256rrk: case X86::VMOVDQA32Z256rrk:
1210 case X86::VMOVDQU32Zrrk: case X86::VMOVDQA32Zrrk:
1211 case X86::VMOVDQU64Z128rrk: case X86::VMOVDQA64Z128rrk:
1212 case X86::VMOVDQU64Z256rrk: case X86::VMOVDQA64Z256rrk:
1213 case X86::VMOVDQU64Zrrk: case X86::VMOVDQA64Zrrk:
1214 case X86::VMOVUPDZ128rrk: case X86::VMOVAPDZ128rrk:
1215 case X86::VMOVUPDZ256rrk: case X86::VMOVAPDZ256rrk:
1216 case X86::VMOVUPDZrrk: case X86::VMOVAPDZrrk:
1217 case X86::VMOVUPSZ128rrk: case X86::VMOVAPSZ128rrk:
1218 case X86::VMOVUPSZ256rrk: case X86::VMOVAPSZ256rrk:
1219 case X86::VMOVUPSZrrk: case X86::VMOVAPSZrrk: {
1220 unsigned Opc;
1221 switch (MIOpc) {
1222 default: llvm_unreachable("Unreachable!")::llvm::llvm_unreachable_internal("Unreachable!", "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/X86/X86InstrInfo.cpp"
, 1222)
;
1223 case X86::VMOVDQU8Z128rrk: Opc = X86::VPBLENDMBZ128rrk; break;
1224 case X86::VMOVDQU8Z256rrk: Opc = X86::VPBLENDMBZ256rrk; break;
1225 case X86::VMOVDQU8Zrrk: Opc = X86::VPBLENDMBZrrk; break;
1226 case X86::VMOVDQU16Z128rrk: Opc = X86::VPBLENDMWZ128rrk; break;
1227 case X86::VMOVDQU16Z256rrk: Opc = X86::VPBLENDMWZ256rrk; break;
1228 case X86::VMOVDQU16Zrrk: Opc = X86::VPBLENDMWZrrk; break;
1229 case X86::VMOVDQU32Z128rrk: Opc = X86::VPBLENDMDZ128rrk; break;
1230 case X86::VMOVDQU32Z256rrk: Opc = X86::VPBLENDMDZ256rrk; break;
1231 case X86::VMOVDQU32Zrrk: Opc = X86::VPBLENDMDZrrk; break;
1232 case X86::VMOVDQU64Z128rrk: Opc = X86::VPBLENDMQZ128rrk; break;
1233 case X86::VMOVDQU64Z256rrk: Opc = X86::VPBLENDMQZ256rrk; break;
1234 case X86::VMOVDQU64Zrrk: Opc = X86::VPBLENDMQZrrk; break;
1235 case X86::VMOVUPDZ128rrk: Opc = X86::VBLENDMPDZ128rrk; break;
1236 case X86::VMOVUPDZ256rrk: Opc = X86::VBLENDMPDZ256rrk; break;
1237 case X86::VMOVUPDZrrk: Opc = X86::VBLENDMPDZrrk; break;
1238 case X86::VMOVUPSZ128rrk: Opc = X86::VBLENDMPSZ128rrk; break;
1239 case X86::VMOVUPSZ256rrk: Opc = X86::VBLENDMPSZ256rrk; break;
1240 case X86::VMOVUPSZrrk: Opc = X86::VBLENDMPSZrrk; break;
1241 case X86::VMOVDQA32Z128rrk: Opc = X86::VPBLENDMDZ128rrk; break;
1242 case X86::VMOVDQA32Z256rrk: Opc = X86::VPBLENDMDZ256rrk; break;
1243 case X86::VMOVDQA32Zrrk: Opc = X86::VPBLENDMDZrrk; break;
1244 case X86::VMOVDQA64Z128rrk: Opc = X86::VPBLENDMQZ128rrk; break;
1245 case X86::VMOVDQA64Z256rrk: Opc = X86::VPBLENDMQZ256rrk; break;
1246 case X86::VMOVDQA64Zrrk: Opc = X86::VPBLENDMQZrrk; break;
1247 case X86::VMOVAPDZ128rrk: Opc = X86::VBLENDMPDZ128rrk; break;
1248 case X86::VMOVAPDZ256rrk: Opc = X86::VBLENDMPDZ256rrk; break;
1249 case X86::VMOVAPDZrrk: Opc = X86::VBLENDMPDZrrk; break;
1250 case X86::VMOVAPSZ128rrk: Opc = X86::VBLENDMPSZ128rrk; break;
1251 case X86::VMOVAPSZ256rrk: Opc = X86::VBLENDMPSZ256rrk; break;
1252 case X86::VMOVAPSZrrk: Opc = X86::VBLENDMPSZrrk; break;
1253 }
1254
1255 NewMI = BuildMI(MF, MI.getDebugLoc(), get(Opc))
1256 .add(Dest)
1257 .add(MI.getOperand(2))
1258 .add(Src)
1259 .add(MI.getOperand(3));
1260 break;
1261 }
1262 }
1263
1264 if (!NewMI) return nullptr;
1265
1266 if (LV) { // Update live variables
1267 if (Src.isKill())
1268 LV->replaceKillInstruction(Src.getReg(), MI, *NewMI);
1269 if (Dest.isDead())
1270 LV->replaceKillInstruction(Dest.getReg(), MI, *NewMI);
1271 }
1272
1273 MFI->insert(MI.getIterator(), NewMI); // Insert the new inst
1274 return NewMI;
1275}
1276
1277/// This determines which of three possible cases of a three source commute
1278/// the source indexes correspond to taking into account any mask operands.
1279/// All prevents commuting a passthru operand. Returns -1 if the commute isn't
1280/// possible.
1281/// Case 0 - Possible to commute the first and second operands.
1282/// Case 1 - Possible to commute the first and third operands.
1283/// Case 2 - Possible to commute the second and third operands.
1284static unsigned getThreeSrcCommuteCase(uint64_t TSFlags, unsigned SrcOpIdx1,
1285 unsigned SrcOpIdx2) {
1286 // Put the lowest index to SrcOpIdx1 to simplify the checks below.
1287 if (SrcOpIdx1 > SrcOpIdx2)
1288 std::swap(SrcOpIdx1, SrcOpIdx2);
1289
1290 unsigned Op1 = 1, Op2 = 2, Op3 = 3;
1291 if (X86II::isKMasked(TSFlags)) {
1292 Op2++;
1293 Op3++;
1294 }
1295
1296 if (SrcOpIdx1 == Op1 && SrcOpIdx2 == Op2)
1297 return 0;
1298 if (SrcOpIdx1 == Op1 && SrcOpIdx2 == Op3)
1299 return 1;
1300 if (SrcOpIdx1 == Op2 && SrcOpIdx2 == Op3)
1301 return 2;
1302 llvm_unreachable("Unknown three src commute case.")::llvm::llvm_unreachable_internal("Unknown three src commute case."
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/X86/X86InstrInfo.cpp"
, 1302)
;
1303}
1304
1305unsigned X86InstrInfo::getFMA3OpcodeToCommuteOperands(
1306 const MachineInstr &MI, unsigned SrcOpIdx1, unsigned SrcOpIdx2,
1307 const X86InstrFMA3Group &FMA3Group) const {
1308
1309 unsigned Opc = MI.getOpcode();
1310
1311 // TODO: Commuting the 1st operand of FMA*_Int requires some additional
1312 // analysis. The commute optimization is legal only if all users of FMA*_Int
1313 // use only the lowest element of the FMA*_Int instruction. Such analysis are
1314 // not implemented yet. So, just return 0 in that case.
1315 // When such analysis are available this place will be the right place for
1316 // calling it.
1317 assert(!(FMA3Group.isIntrinsic() && (SrcOpIdx1 == 1 || SrcOpIdx2 == 1)) &&((!(FMA3Group.isIntrinsic() && (SrcOpIdx1 == 1 || SrcOpIdx2
== 1)) && "Intrinsic instructions can't commute operand 1"
) ? static_cast<void> (0) : __assert_fail ("!(FMA3Group.isIntrinsic() && (SrcOpIdx1 == 1 || SrcOpIdx2 == 1)) && \"Intrinsic instructions can't commute operand 1\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/X86/X86InstrInfo.cpp"
, 1318, __PRETTY_FUNCTION__))
1318 "Intrinsic instructions can't commute operand 1")((!(FMA3Group.isIntrinsic() && (SrcOpIdx1 == 1 || SrcOpIdx2
== 1)) && "Intrinsic instructions can't commute operand 1"
) ? static_cast<void> (0) : __assert_fail ("!(FMA3Group.isIntrinsic() && (SrcOpIdx1 == 1 || SrcOpIdx2 == 1)) && \"Intrinsic instructions can't commute operand 1\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/X86/X86InstrInfo.cpp"
, 1318, __PRETTY_FUNCTION__))
;
1319
1320 // Determine which case this commute is or if it can't be done.
1321 unsigned Case = getThreeSrcCommuteCase(MI.getDesc().TSFlags, SrcOpIdx1,
1322 SrcOpIdx2);
1323 assert(Case < 3 && "Unexpected case number!")((Case < 3 && "Unexpected case number!") ? static_cast
<void> (0) : __assert_fail ("Case < 3 && \"Unexpected case number!\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/X86/X86InstrInfo.cpp"
, 1323, __PRETTY_FUNCTION__))
;
1324
1325 // Define the FMA forms mapping array that helps to map input FMA form
1326 // to output FMA form to preserve the operation semantics after
1327 // commuting the operands.
1328 const unsigned Form132Index = 0;
1329 const unsigned Form213Index = 1;
1330 const unsigned Form231Index = 2;
1331 static const unsigned FormMapping[][3] = {
1332 // 0: SrcOpIdx1 == 1 && SrcOpIdx2 == 2;
1333 // FMA132 A, C, b; ==> FMA231 C, A, b;
1334 // FMA213 B, A, c; ==> FMA213 A, B, c;
1335 // FMA231 C, A, b; ==> FMA132 A, C, b;
1336 { Form231Index, Form213Index, Form132Index },
1337 // 1: SrcOpIdx1 == 1 && SrcOpIdx2 == 3;
1338 // FMA132 A, c, B; ==> FMA132 B, c, A;
1339 // FMA213 B, a, C; ==> FMA231 C, a, B;
1340 // FMA231 C, a, B; ==> FMA213 B, a, C;
1341 { Form132Index, Form231Index, Form213Index },
1342 // 2: SrcOpIdx1 == 2 && SrcOpIdx2 == 3;
1343 // FMA132 a, C, B; ==> FMA213 a, B, C;
1344 // FMA213 b, A, C; ==> FMA132 b, C, A;
1345 // FMA231 c, A, B; ==> FMA231 c, B, A;
1346 { Form213Index, Form132Index, Form231Index }
1347 };
1348
1349 unsigned FMAForms[3];
1350 FMAForms[0] = FMA3Group.get132Opcode();
1351 FMAForms[1] = FMA3Group.get213Opcode();
1352 FMAForms[2] = FMA3Group.get231Opcode();
1353 unsigned FormIndex;
1354 for (FormIndex = 0; FormIndex < 3; FormIndex++)
1355 if (Opc == FMAForms[FormIndex])
1356 break;
1357
1358 // Everything is ready, just adjust the FMA opcode and return it.
1359 FormIndex = FormMapping[Case][FormIndex];
1360 return FMAForms[FormIndex];
1361}
1362
1363static void commuteVPTERNLOG(MachineInstr &MI, unsigned SrcOpIdx1,
1364 unsigned SrcOpIdx2) {
1365 // Determine which case this commute is or if it can't be done.
1366 unsigned Case = getThreeSrcCommuteCase(MI.getDesc().TSFlags, SrcOpIdx1,
1367 SrcOpIdx2);
1368 assert(Case < 3 && "Unexpected case value!")((Case < 3 && "Unexpected case value!") ? static_cast
<void> (0) : __assert_fail ("Case < 3 && \"Unexpected case value!\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/X86/X86InstrInfo.cpp"
, 1368, __PRETTY_FUNCTION__))
;
1369
1370 // For each case we need to swap two pairs of bits in the final immediate.
1371 static const uint8_t SwapMasks[3][4] = {
1372 { 0x04, 0x10, 0x08, 0x20 }, // Swap bits 2/4 and 3/5.
1373 { 0x02, 0x10, 0x08, 0x40 }, // Swap bits 1/4 and 3/6.
1374 { 0x02, 0x04, 0x20, 0x40 }, // Swap bits 1/2 and 5/6.
1375 };
1376
1377 uint8_t Imm = MI.getOperand(MI.getNumOperands()-1).getImm();
1378 // Clear out the bits we are swapping.
1379 uint8_t NewImm = Imm & ~(SwapMasks[Case][0] | SwapMasks[Case][1] |
1380 SwapMasks[Case][2] | SwapMasks[Case][3]);
1381 // If the immediate had a bit of the pair set, then set the opposite bit.
1382 if (Imm & SwapMasks[Case][0]) NewImm |= SwapMasks[Case][1];
1383 if (Imm & SwapMasks[Case][1]) NewImm |= SwapMasks[Case][0];
1384 if (Imm & SwapMasks[Case][2]) NewImm |= SwapMasks[Case][3];
1385 if (Imm & SwapMasks[Case][3]) NewImm |= SwapMasks[Case][2];
1386 MI.getOperand(MI.getNumOperands()-1).setImm(NewImm);
1387}
1388
1389// Returns true if this is a VPERMI2 or VPERMT2 instruction that can be
1390// commuted.
1391static bool isCommutableVPERMV3Instruction(unsigned Opcode) {
1392#define VPERM_CASES(Suffix) \
1393 case X86::VPERMI2##Suffix##128rr: case X86::VPERMT2##Suffix##128rr: \
1394 case X86::VPERMI2##Suffix##256rr: case X86::VPERMT2##Suffix##256rr: \
1395 case X86::VPERMI2##Suffix##rr: case X86::VPERMT2##Suffix##rr: \
1396 case X86::VPERMI2##Suffix##128rm: case X86::VPERMT2##Suffix##128rm: \
1397 case X86::VPERMI2##Suffix##256rm: case X86::VPERMT2##Suffix##256rm: \
1398 case X86::VPERMI2##Suffix##rm: case X86::VPERMT2##Suffix##rm: \
1399 case X86::VPERMI2##Suffix##128rrkz: case X86::VPERMT2##Suffix##128rrkz: \
1400 case X86::VPERMI2##Suffix##256rrkz: case X86::VPERMT2##Suffix##256rrkz: \
1401 case X86::VPERMI2##Suffix##rrkz: case X86::VPERMT2##Suffix##rrkz: \
1402 case X86::VPERMI2##Suffix##128rmkz: case X86::VPERMT2##Suffix##128rmkz: \
1403 case X86::VPERMI2##Suffix##256rmkz: case X86::VPERMT2##Suffix##256rmkz: \
1404 case X86::VPERMI2##Suffix##rmkz: case X86::VPERMT2##Suffix##rmkz:
1405
1406#define VPERM_CASES_BROADCAST(Suffix) \
1407 VPERM_CASES(Suffix) \
1408 case X86::VPERMI2##Suffix##128rmb: case X86::VPERMT2##Suffix##128rmb: \
1409 case X86::VPERMI2##Suffix##256rmb: case X86::VPERMT2##Suffix##256rmb: \
1410 case X86::VPERMI2##Suffix##rmb: case X86::VPERMT2##Suffix##rmb: \
1411 case X86::VPERMI2##Suffix##128rmbkz: case X86::VPERMT2##Suffix##128rmbkz: \
1412 case X86::VPERMI2##Suffix##256rmbkz: case X86::VPERMT2##Suffix##256rmbkz: \
1413 case X86::VPERMI2##Suffix##rmbkz: case X86::VPERMT2##Suffix##rmbkz:
1414
1415 switch (Opcode) {
1416 default: return false;
1417 VPERM_CASES(B)
1418 VPERM_CASES_BROADCAST(D)
1419 VPERM_CASES_BROADCAST(PD)
1420 VPERM_CASES_BROADCAST(PS)
1421 VPERM_CASES_BROADCAST(Q)
1422 VPERM_CASES(W)
1423 return true;
1424 }
1425#undef VPERM_CASES_BROADCAST
1426#undef VPERM_CASES
1427}
1428
1429// Returns commuted opcode for VPERMI2 and VPERMT2 instructions by switching
1430// from the I opcode to the T opcode and vice versa.
1431static unsigned getCommutedVPERMV3Opcode(unsigned Opcode) {
1432#define VPERM_CASES(Orig, New) \
1433 case X86::Orig##128rr: return X86::New##128rr; \
1434 case X86::Orig##128rrkz: return X86::New##128rrkz; \
1435 case X86::Orig##128rm: return X86::New##128rm; \
1436 case X86::Orig##128rmkz: return X86::New##128rmkz; \
1437 case X86::Orig##256rr: return X86::New##256rr; \
1438 case X86::Orig##256rrkz: return X86::New##256rrkz; \
1439 case X86::Orig##256rm: return X86::New##256rm; \
1440 case X86::Orig##256rmkz: return X86::New##256rmkz; \
1441 case X86::Orig##rr: return X86::New##rr; \
1442 case X86::Orig##rrkz: return X86::New##rrkz; \
1443 case X86::Orig##rm: return X86::New##rm; \
1444 case X86::Orig##rmkz: return X86::New##rmkz;
1445
1446#define VPERM_CASES_BROADCAST(Orig, New) \
1447 VPERM_CASES(Orig, New) \
1448 case X86::Orig##128rmb: return X86::New##128rmb; \
1449 case X86::Orig##128rmbkz: return X86::New##128rmbkz; \
1450 case X86::Orig##256rmb: return X86::New##256rmb; \
1451 case X86::Orig##256rmbkz: return X86::New##256rmbkz; \
1452 case X86::Orig##rmb: return X86::New##rmb; \
1453 case X86::Orig##rmbkz: return X86::New##rmbkz;
1454
1455 switch (Opcode) {
1456 VPERM_CASES(VPERMI2B, VPERMT2B)
1457 VPERM_CASES_BROADCAST(VPERMI2D, VPERMT2D)
1458 VPERM_CASES_BROADCAST(VPERMI2PD, VPERMT2PD)
1459 VPERM_CASES_BROADCAST(VPERMI2PS, VPERMT2PS)
1460 VPERM_CASES_BROADCAST(VPERMI2Q, VPERMT2Q)
1461 VPERM_CASES(VPERMI2W, VPERMT2W)
1462 VPERM_CASES(VPERMT2B, VPERMI2B)
1463 VPERM_CASES_BROADCAST(VPERMT2D, VPERMI2D)
1464 VPERM_CASES_BROADCAST(VPERMT2PD, VPERMI2PD)
1465 VPERM_CASES_BROADCAST(VPERMT2PS, VPERMI2PS)
1466 VPERM_CASES_BROADCAST(VPERMT2Q, VPERMI2Q)
1467 VPERM_CASES(VPERMT2W, VPERMI2W)
1468 }
1469
1470 llvm_unreachable("Unreachable!")::llvm::llvm_unreachable_internal("Unreachable!", "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/X86/X86InstrInfo.cpp"
, 1470)
;
1471#undef VPERM_CASES_BROADCAST
1472#undef VPERM_CASES
1473}
1474
1475MachineInstr *X86InstrInfo::commuteInstructionImpl(MachineInstr &MI, bool NewMI,
1476 unsigned OpIdx1,
1477 unsigned OpIdx2) const {
1478 auto cloneIfNew = [NewMI](MachineInstr &MI) -> MachineInstr & {
1479 if (NewMI)
1480 return *MI.getParent()->getParent()->CloneMachineInstr(&MI);
1481 return MI;
1482 };
1483
1484 switch (MI.getOpcode()) {
1485 case X86::SHRD16rri8: // A = SHRD16rri8 B, C, I -> A = SHLD16rri8 C, B, (16-I)
1486 case X86::SHLD16rri8: // A = SHLD16rri8 B, C, I -> A = SHRD16rri8 C, B, (16-I)
1487 case X86::SHRD32rri8: // A = SHRD32rri8 B, C, I -> A = SHLD32rri8 C, B, (32-I)
1488 case X86::SHLD32rri8: // A = SHLD32rri8 B, C, I -> A = SHRD32rri8 C, B, (32-I)
1489 case X86::SHRD64rri8: // A = SHRD64rri8 B, C, I -> A = SHLD64rri8 C, B, (64-I)
1490 case X86::SHLD64rri8:{// A = SHLD64rri8 B, C, I -> A = SHRD64rri8 C, B, (64-I)
1491 unsigned Opc;
1492 unsigned Size;
1493 switch (MI.getOpcode()) {
1494 default: llvm_unreachable("Unreachable!")::llvm::llvm_unreachable_internal("Unreachable!", "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/X86/X86InstrInfo.cpp"
, 1494)
;
1495 case X86::SHRD16rri8: Size = 16; Opc = X86::SHLD16rri8; break;
1496 case X86::SHLD16rri8: Size = 16; Opc = X86::SHRD16rri8; break;
1497 case X86::SHRD32rri8: Size = 32; Opc = X86::SHLD32rri8; break;
1498 case X86::SHLD32rri8: Size = 32; Opc = X86::SHRD32rri8; break;
1499 case X86::SHRD64rri8: Size = 64; Opc = X86::SHLD64rri8; break;
1500 case X86::SHLD64rri8: Size = 64; Opc = X86::SHRD64rri8; break;
1501 }
1502 unsigned Amt = MI.getOperand(3).getImm();
1503 auto &WorkingMI = cloneIfNew(MI);
1504 WorkingMI.setDesc(get(Opc));
1505 WorkingMI.getOperand(3).setImm(Size - Amt);
1506 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
1507 OpIdx1, OpIdx2);
1508 }
1509 case X86::PFSUBrr:
1510 case X86::PFSUBRrr: {
1511 // PFSUB x, y: x = x - y
1512 // PFSUBR x, y: x = y - x
1513 unsigned Opc =
1514 (X86::PFSUBRrr == MI.getOpcode() ? X86::PFSUBrr : X86::PFSUBRrr);
1515 auto &WorkingMI = cloneIfNew(MI);
1516 WorkingMI.setDesc(get(Opc));
1517 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
1518 OpIdx1, OpIdx2);
1519 }
1520 case X86::BLENDPDrri:
1521 case X86::BLENDPSrri:
1522 case X86::VBLENDPDrri:
1523 case X86::VBLENDPSrri:
1524 // If we're optimizing for size, try to use MOVSD/MOVSS.
1525 if (MI.getParent()->getParent()->getFunction().optForSize()) {
1526 unsigned Mask, Opc;
1527 switch (MI.getOpcode()) {
1528 default: llvm_unreachable("Unreachable!")::llvm::llvm_unreachable_internal("Unreachable!", "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/X86/X86InstrInfo.cpp"
, 1528)
;
1529 case X86::BLENDPDrri: Opc = X86::MOVSDrr; Mask = 0x03; break;
1530 case X86::BLENDPSrri: Opc = X86::MOVSSrr; Mask = 0x0F; break;
1531 case X86::VBLENDPDrri: Opc = X86::VMOVSDrr; Mask = 0x03; break;
1532 case X86::VBLENDPSrri: Opc = X86::VMOVSSrr; Mask = 0x0F; break;
1533 }
1534 if ((MI.getOperand(3).getImm() ^ Mask) == 1) {
1535 auto &WorkingMI = cloneIfNew(MI);
1536 WorkingMI.setDesc(get(Opc));
1537 WorkingMI.RemoveOperand(3);
1538 return TargetInstrInfo::commuteInstructionImpl(WorkingMI,
1539 /*NewMI=*/false,
1540 OpIdx1, OpIdx2);
1541 }
1542 }
1543 LLVM_FALLTHROUGH[[clang::fallthrough]];
1544 case X86::PBLENDWrri:
1545 case X86::VBLENDPDYrri:
1546 case X86::VBLENDPSYrri:
1547 case X86::VPBLENDDrri:
1548 case X86::VPBLENDWrri:
1549 case X86::VPBLENDDYrri:
1550 case X86::VPBLENDWYrri:{
1551 unsigned Mask;
1552 switch (MI.getOpcode()) {
1553 default: llvm_unreachable("Unreachable!")::llvm::llvm_unreachable_internal("Unreachable!", "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/X86/X86InstrInfo.cpp"
, 1553)
;
1554 case X86::BLENDPDrri: Mask = 0x03; break;
1555 case X86::BLENDPSrri: Mask = 0x0F; break;
1556 case X86::PBLENDWrri: Mask = 0xFF; break;
1557 case X86::VBLENDPDrri: Mask = 0x03; break;
1558 case X86::VBLENDPSrri: Mask = 0x0F; break;
1559 case X86::VBLENDPDYrri: Mask = 0x0F; break;
1560 case X86::VBLENDPSYrri: Mask = 0xFF; break;
1561 case X86::VPBLENDDrri: Mask = 0x0F; break;
1562 case X86::VPBLENDWrri: Mask = 0xFF; break;
1563 case X86::VPBLENDDYrri: Mask = 0xFF; break;
1564 case X86::VPBLENDWYrri: Mask = 0xFF; break;
1565 }
1566 // Only the least significant bits of Imm are used.
1567 unsigned Imm = MI.getOperand(3).getImm() & Mask;
1568 auto &WorkingMI = cloneIfNew(MI);
1569 WorkingMI.getOperand(3).setImm(Mask ^ Imm);
1570 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
1571 OpIdx1, OpIdx2);
1572 }
1573 case X86::MOVSDrr:
1574 case X86::MOVSSrr:
1575 case X86::VMOVSDrr:
1576 case X86::VMOVSSrr:{
1577 // On SSE41 or later we can commute a MOVSS/MOVSD to a BLENDPS/BLENDPD.
1578 assert(Subtarget.hasSSE41() && "Commuting MOVSD/MOVSS requires SSE41!")((Subtarget.hasSSE41() && "Commuting MOVSD/MOVSS requires SSE41!"
) ? static_cast<void> (0) : __assert_fail ("Subtarget.hasSSE41() && \"Commuting MOVSD/MOVSS requires SSE41!\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/X86/X86InstrInfo.cpp"
, 1578, __PRETTY_FUNCTION__))
;
1579
1580 unsigned Mask, Opc;
1581 switch (MI.getOpcode()) {
1582 default: llvm_unreachable("Unreachable!")::llvm::llvm_unreachable_internal("Unreachable!", "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/X86/X86InstrInfo.cpp"
, 1582)
;
1583 case X86::MOVSDrr: Opc = X86::BLENDPDrri; Mask = 0x02; break;
1584 case X86::MOVSSrr: Opc = X86::BLENDPSrri; Mask = 0x0E; break;
1585 case X86::VMOVSDrr: Opc = X86::VBLENDPDrri; Mask = 0x02; break;
1586 case X86::VMOVSSrr: Opc = X86::VBLENDPSrri; Mask = 0x0E; break;
1587 }
1588
1589 auto &WorkingMI = cloneIfNew(MI);
1590 WorkingMI.setDesc(get(Opc));
1591 WorkingMI.addOperand(MachineOperand::CreateImm(Mask));
1592 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
1593 OpIdx1, OpIdx2);
1594 }
1595 case X86::PCLMULQDQrr:
1596 case X86::VPCLMULQDQrr:
1597 case X86::VPCLMULQDQYrr:
1598 case X86::VPCLMULQDQZrr:
1599 case X86::VPCLMULQDQZ128rr:
1600 case X86::VPCLMULQDQZ256rr: {
1601 // SRC1 64bits = Imm[0] ? SRC1[127:64] : SRC1[63:0]
1602 // SRC2 64bits = Imm[4] ? SRC2[127:64] : SRC2[63:0]
1603 unsigned Imm = MI.getOperand(3).getImm();
1604 unsigned Src1Hi = Imm & 0x01;
1605 unsigned Src2Hi = Imm & 0x10;
1606 auto &WorkingMI = cloneIfNew(MI);
1607 WorkingMI.getOperand(3).setImm((Src1Hi << 4) | (Src2Hi >> 4));
1608 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
1609 OpIdx1, OpIdx2);
1610 }
1611 case X86::VPCMPBZ128rri: case X86::VPCMPUBZ128rri:
1612 case X86::VPCMPBZ256rri: case X86::VPCMPUBZ256rri:
1613 case X86::VPCMPBZrri: case X86::VPCMPUBZrri:
1614 case X86::VPCMPDZ128rri: case X86::VPCMPUDZ128rri:
1615 case X86::VPCMPDZ256rri: case X86::VPCMPUDZ256rri:
1616 case X86::VPCMPDZrri: case X86::VPCMPUDZrri:
1617 case X86::VPCMPQZ128rri: case X86::VPCMPUQZ128rri:
1618 case X86::VPCMPQZ256rri: case X86::VPCMPUQZ256rri:
1619 case X86::VPCMPQZrri: case X86::VPCMPUQZrri:
1620 case X86::VPCMPWZ128rri: case X86::VPCMPUWZ128rri:
1621 case X86::VPCMPWZ256rri: case X86::VPCMPUWZ256rri:
1622 case X86::VPCMPWZrri: case X86::VPCMPUWZrri:
1623 case X86::VPCMPBZ128rrik: case X86::VPCMPUBZ128rrik:
1624 case X86::VPCMPBZ256rrik: case X86::VPCMPUBZ256rrik:
1625 case X86::VPCMPBZrrik: case X86::VPCMPUBZrrik:
1626 case X86::VPCMPDZ128rrik: case X86::VPCMPUDZ128rrik:
1627 case X86::VPCMPDZ256rrik: case X86::VPCMPUDZ256rrik:
1628 case X86::VPCMPDZrrik: case X86::VPCMPUDZrrik:
1629 case X86::VPCMPQZ128rrik: case X86::VPCMPUQZ128rrik:
1630 case X86::VPCMPQZ256rrik: case X86::VPCMPUQZ256rrik:
1631 case X86::VPCMPQZrrik: case X86::VPCMPUQZrrik:
1632 case X86::VPCMPWZ128rrik: case X86::VPCMPUWZ128rrik:
1633 case X86::VPCMPWZ256rrik: case X86::VPCMPUWZ256rrik:
1634 case X86::VPCMPWZrrik: case X86::VPCMPUWZrrik: {
1635 // Flip comparison mode immediate (if necessary).
1636 unsigned Imm = MI.getOperand(MI.getNumOperands() - 1).getImm() & 0x7;
1637 Imm = X86::getSwappedVPCMPImm(Imm);
1638 auto &WorkingMI = cloneIfNew(MI);
1639 WorkingMI.getOperand(MI.getNumOperands() - 1).setImm(Imm);
1640 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
1641 OpIdx1, OpIdx2);
1642 }
1643 case X86::VPCOMBri: case X86::VPCOMUBri:
1644 case X86::VPCOMDri: case X86::VPCOMUDri:
1645 case X86::VPCOMQri: case X86::VPCOMUQri:
1646 case X86::VPCOMWri: case X86::VPCOMUWri: {
1647 // Flip comparison mode immediate (if necessary).
1648 unsigned Imm = MI.getOperand(3).getImm() & 0x7;
1649 Imm = X86::getSwappedVPCOMImm(Imm);
1650 auto &WorkingMI = cloneIfNew(MI);
1651 WorkingMI.getOperand(3).setImm(Imm);
1652 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
1653 OpIdx1, OpIdx2);
1654 }
1655 case X86::VPERM2F128rr:
1656 case X86::VPERM2I128rr: {
1657 // Flip permute source immediate.
1658 // Imm & 0x02: lo = if set, select Op1.lo/hi else Op0.lo/hi.
1659 // Imm & 0x20: hi = if set, select Op1.lo/hi else Op0.lo/hi.
1660 unsigned Imm = MI.getOperand(3).getImm() & 0xFF;
1661 auto &WorkingMI = cloneIfNew(MI);
1662 WorkingMI.getOperand(3).setImm(Imm ^ 0x22);
1663 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
1664 OpIdx1, OpIdx2);
1665 }
1666 case X86::MOVHLPSrr:
1667 case X86::UNPCKHPDrr:
1668 case X86::VMOVHLPSrr:
1669 case X86::VUNPCKHPDrr:
1670 case X86::VMOVHLPSZrr:
1671 case X86::VUNPCKHPDZ128rr: {
1672 assert(Subtarget.hasSSE2() && "Commuting MOVHLP/UNPCKHPD requires SSE2!")((Subtarget.hasSSE2() && "Commuting MOVHLP/UNPCKHPD requires SSE2!"
) ? static_cast<void> (0) : __assert_fail ("Subtarget.hasSSE2() && \"Commuting MOVHLP/UNPCKHPD requires SSE2!\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/X86/X86InstrInfo.cpp"
, 1672, __PRETTY_FUNCTION__))
;
1673
1674 unsigned Opc = MI.getOpcode();
1675 switch (Opc) {
1676 default: llvm_unreachable("Unreachable!")::llvm::llvm_unreachable_internal("Unreachable!", "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/X86/X86InstrInfo.cpp"
, 1676)
;
1677 case X86::MOVHLPSrr: Opc = X86::UNPCKHPDrr; break;
1678 case X86::UNPCKHPDrr: Opc = X86::MOVHLPSrr; break;
1679 case X86::VMOVHLPSrr: Opc = X86::VUNPCKHPDrr; break;
1680 case X86::VUNPCKHPDrr: Opc = X86::VMOVHLPSrr; break;
1681 case X86::VMOVHLPSZrr: Opc = X86::VUNPCKHPDZ128rr; break;
1682 case X86::VUNPCKHPDZ128rr: Opc = X86::VMOVHLPSZrr; break;
1683 }
1684 auto &WorkingMI = cloneIfNew(MI);
1685 WorkingMI.setDesc(get(Opc));
1686 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
1687 OpIdx1, OpIdx2);
1688 }
1689 case X86::CMOVB16rr: case X86::CMOVB32rr: case X86::CMOVB64rr:
1690 case X86::CMOVAE16rr: case X86::CMOVAE32rr: case X86::CMOVAE64rr:
1691 case X86::CMOVE16rr: case X86::CMOVE32rr: case X86::CMOVE64rr:
1692 case X86::CMOVNE16rr: case X86::CMOVNE32rr: case X86::CMOVNE64rr:
1693 case X86::CMOVBE16rr: case X86::CMOVBE32rr: case X86::CMOVBE64rr:
1694 case X86::CMOVA16rr: case X86::CMOVA32rr: case X86::CMOVA64rr:
1695 case X86::CMOVL16rr: case X86::CMOVL32rr: case X86::CMOVL64rr:
1696 case X86::CMOVGE16rr: case X86::CMOVGE32rr: case X86::CMOVGE64rr:
1697 case X86::CMOVLE16rr: case X86::CMOVLE32rr: case X86::CMOVLE64rr:
1698 case X86::CMOVG16rr: case X86::CMOVG32rr: case X86::CMOVG64rr:
1699 case X86::CMOVS16rr: case X86::CMOVS32rr: case X86::CMOVS64rr:
1700 case X86::CMOVNS16rr: case X86::CMOVNS32rr: case X86::CMOVNS64rr:
1701 case X86::CMOVP16rr: case X86::CMOVP32rr: case X86::CMOVP64rr:
1702 case X86::CMOVNP16rr: case X86::CMOVNP32rr: case X86::CMOVNP64rr:
1703 case X86::CMOVO16rr: case X86::CMOVO32rr: case X86::CMOVO64rr:
1704 case X86::CMOVNO16rr: case X86::CMOVNO32rr: case X86::CMOVNO64rr: {
1705 unsigned Opc;
1706 switch (MI.getOpcode()) {
1707 default: llvm_unreachable("Unreachable!")::llvm::llvm_unreachable_internal("Unreachable!", "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/X86/X86InstrInfo.cpp"
, 1707)
;
1708 case X86::CMOVB16rr: Opc = X86::CMOVAE16rr; break;
1709 case X86::CMOVB32rr: Opc = X86::CMOVAE32rr; break;
1710 case X86::CMOVB64rr: Opc = X86::CMOVAE64rr; break;
1711 case X86::CMOVAE16rr: Opc = X86::CMOVB16rr; break;
1712 case X86::CMOVAE32rr: Opc = X86::CMOVB32rr; break;
1713 case X86::CMOVAE64rr: Opc = X86::CMOVB64rr; break;
1714 case X86::CMOVE16rr: Opc = X86::CMOVNE16rr; break;
1715 case X86::CMOVE32rr: Opc = X86::CMOVNE32rr; break;
1716 case X86::CMOVE64rr: Opc = X86::CMOVNE64rr; break;
1717 case X86::CMOVNE16rr: Opc = X86::CMOVE16rr; break;
1718 case X86::CMOVNE32rr: Opc = X86::CMOVE32rr; break;
1719 case X86::CMOVNE64rr: Opc = X86::CMOVE64rr; break;
1720 case X86::CMOVBE16rr: Opc = X86::CMOVA16rr; break;
1721 case X86::CMOVBE32rr: Opc = X86::CMOVA32rr; break;
1722 case X86::CMOVBE64rr: Opc = X86::CMOVA64rr; break;
1723 case X86::CMOVA16rr: Opc = X86::CMOVBE16rr; break;
1724 case X86::CMOVA32rr: Opc = X86::CMOVBE32rr; break;
1725 case X86::CMOVA64rr: Opc = X86::CMOVBE64rr; break;
1726 case X86::CMOVL16rr: Opc = X86::CMOVGE16rr; break;
1727 case X86::CMOVL32rr: Opc = X86::CMOVGE32rr; break;
1728 case X86::CMOVL64rr: Opc = X86::CMOVGE64rr; break;
1729 case X86::CMOVGE16rr: Opc = X86::CMOVL16rr; break;
1730 case X86::CMOVGE32rr: Opc = X86::CMOVL32rr; break;
1731 case X86::CMOVGE64rr: Opc = X86::CMOVL64rr; break;
1732 case X86::CMOVLE16rr: Opc = X86::CMOVG16rr; break;
1733 case X86::CMOVLE32rr: Opc = X86::CMOVG32rr; break;
1734 case X86::CMOVLE64rr: Opc = X86::CMOVG64rr; break;
1735 case X86::CMOVG16rr: Opc = X86::CMOVLE16rr; break;
1736 case X86::CMOVG32rr: Opc = X86::CMOVLE32rr; break;
1737 case X86::CMOVG64rr: Opc = X86::CMOVLE64rr; break;
1738 case X86::CMOVS16rr: Opc = X86::CMOVNS16rr; break;
1739 case X86::CMOVS32rr: Opc = X86::CMOVNS32rr; break;
1740 case X86::CMOVS64rr: Opc = X86::CMOVNS64rr; break;
1741 case X86::CMOVNS16rr: Opc = X86::CMOVS16rr; break;
1742 case X86::CMOVNS32rr: Opc = X86::CMOVS32rr; break;
1743 case X86::CMOVNS64rr: Opc = X86::CMOVS64rr; break;
1744 case X86::CMOVP16rr: Opc = X86::CMOVNP16rr; break;
1745 case X86::CMOVP32rr: Opc = X86::CMOVNP32rr; break;
1746 case X86::CMOVP64rr: Opc = X86::CMOVNP64rr; break;
1747 case X86::CMOVNP16rr: Opc = X86::CMOVP16rr; break;
1748 case X86::CMOVNP32rr: Opc = X86::CMOVP32rr; break;
1749 case X86::CMOVNP64rr: Opc = X86::CMOVP64rr; break;
1750 case X86::CMOVO16rr: Opc = X86::CMOVNO16rr; break;
1751 case X86::CMOVO32rr: Opc = X86::CMOVNO32rr; break;
1752 case X86::CMOVO64rr: Opc = X86::CMOVNO64rr; break;
1753 case X86::CMOVNO16rr: Opc = X86::CMOVO16rr; break;
1754 case X86::CMOVNO32rr: Opc = X86::CMOVO32rr; break;
1755 case X86::CMOVNO64rr: Opc = X86::CMOVO64rr; break;
1756 }
1757 auto &WorkingMI = cloneIfNew(MI);
1758 WorkingMI.setDesc(get(Opc));
1759 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
1760 OpIdx1, OpIdx2);
1761 }
1762 case X86::VPTERNLOGDZrri: case X86::VPTERNLOGDZrmi:
1763 case X86::VPTERNLOGDZ128rri: case X86::VPTERNLOGDZ128rmi:
1764 case X86::VPTERNLOGDZ256rri: case X86::VPTERNLOGDZ256rmi:
1765 case X86::VPTERNLOGQZrri: case X86::VPTERNLOGQZrmi:
1766 case X86::VPTERNLOGQZ128rri: case X86::VPTERNLOGQZ128rmi:
1767 case X86::VPTERNLOGQZ256rri: case X86::VPTERNLOGQZ256rmi:
1768 case X86::VPTERNLOGDZrrik:
1769 case X86::VPTERNLOGDZ128rrik:
1770 case X86::VPTERNLOGDZ256rrik:
1771 case X86::VPTERNLOGQZrrik:
1772 case X86::VPTERNLOGQZ128rrik:
1773 case X86::VPTERNLOGQZ256rrik:
1774 case X86::VPTERNLOGDZrrikz: case X86::VPTERNLOGDZrmikz:
1775 case X86::VPTERNLOGDZ128rrikz: case X86::VPTERNLOGDZ128rmikz:
1776 case X86::VPTERNLOGDZ256rrikz: case X86::VPTERNLOGDZ256rmikz:
1777 case X86::VPTERNLOGQZrrikz: case X86::VPTERNLOGQZrmikz:
1778 case X86::VPTERNLOGQZ128rrikz: case X86::VPTERNLOGQZ128rmikz:
1779 case X86::VPTERNLOGQZ256rrikz: case X86::VPTERNLOGQZ256rmikz:
1780 case X86::VPTERNLOGDZ128rmbi:
1781 case X86::VPTERNLOGDZ256rmbi:
1782 case X86::VPTERNLOGDZrmbi:
1783 case X86::VPTERNLOGQZ128rmbi:
1784 case X86::VPTERNLOGQZ256rmbi:
1785 case X86::VPTERNLOGQZrmbi:
1786 case X86::VPTERNLOGDZ128rmbikz:
1787 case X86::VPTERNLOGDZ256rmbikz:
1788 case X86::VPTERNLOGDZrmbikz:
1789 case X86::VPTERNLOGQZ128rmbikz:
1790 case X86::VPTERNLOGQZ256rmbikz:
1791 case X86::VPTERNLOGQZrmbikz: {
1792 auto &WorkingMI = cloneIfNew(MI);
1793 commuteVPTERNLOG(WorkingMI, OpIdx1, OpIdx2);
1794 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
1795 OpIdx1, OpIdx2);
1796 }
1797 default: {
1798 if (isCommutableVPERMV3Instruction(MI.getOpcode())) {
1799 unsigned Opc = getCommutedVPERMV3Opcode(MI.getOpcode());
1800 auto &WorkingMI = cloneIfNew(MI);
1801 WorkingMI.setDesc(get(Opc));
1802 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
1803 OpIdx1, OpIdx2);
1804 }
1805
1806 const X86InstrFMA3Group *FMA3Group = getFMA3Group(MI.getOpcode(),
1807 MI.getDesc().TSFlags);
1808 if (FMA3Group) {
1809 unsigned Opc =
1810 getFMA3OpcodeToCommuteOperands(MI, OpIdx1, OpIdx2, *FMA3Group);
1811 auto &WorkingMI = cloneIfNew(MI);
1812 WorkingMI.setDesc(get(Opc));
1813 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
1814 OpIdx1, OpIdx2);
1815 }
1816
1817 return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
1818 }
1819 }
1820}
1821
1822bool
1823X86InstrInfo::findThreeSrcCommutedOpIndices(const MachineInstr &MI,
1824 unsigned &SrcOpIdx1,
1825 unsigned &SrcOpIdx2,
1826 bool IsIntrinsic) const {
1827 uint64_t TSFlags = MI.getDesc().TSFlags;
1828
1829 unsigned FirstCommutableVecOp = 1;
1830 unsigned LastCommutableVecOp = 3;
1831 unsigned KMaskOp = -1U;
1832 if (X86II::isKMasked(TSFlags)) {
1833 // For k-zero-masked operations it is Ok to commute the first vector
1834 // operand.
1835 // For regular k-masked operations a conservative choice is done as the
1836 // elements of the first vector operand, for which the corresponding bit
1837 // in the k-mask operand is set to 0, are copied to the result of the
1838 // instruction.
1839 // TODO/FIXME: The commute still may be legal if it is known that the
1840 // k-mask operand is set to either all ones or all zeroes.
1841 // It is also Ok to commute the 1st operand if all users of MI use only
1842 // the elements enabled by the k-mask operand. For example,
1843 // v4 = VFMADD213PSZrk v1, k, v2, v3; // v1[i] = k[i] ? v2[i]*v1[i]+v3[i]
1844 // : v1[i];
1845 // VMOVAPSZmrk <mem_addr>, k, v4; // this is the ONLY user of v4 ->
1846 // // Ok, to commute v1 in FMADD213PSZrk.
1847
1848 // The k-mask operand has index = 2 for masked and zero-masked operations.
1849 KMaskOp = 2;
1850
1851 // The operand with index = 1 is used as a source for those elements for
1852 // which the corresponding bit in the k-mask is set to 0.
1853 if (X86II::isKMergeMasked(TSFlags))
1854 FirstCommutableVecOp = 3;
1855
1856 LastCommutableVecOp++;
1857 } else if (IsIntrinsic) {
1858 // Commuting the first operand of an intrinsic instruction isn't possible
1859 // unless we can prove that only the lowest element of the result is used.
1860 FirstCommutableVecOp = 2;
1861 }
1862
1863 if (isMem(MI, LastCommutableVecOp))
1864 LastCommutableVecOp--;
1865
1866 // Only the first RegOpsNum operands are commutable.
1867 // Also, the value 'CommuteAnyOperandIndex' is valid here as it means
1868 // that the operand is not specified/fixed.
1869 if (SrcOpIdx1 != CommuteAnyOperandIndex &&
1870 (SrcOpIdx1 < FirstCommutableVecOp || SrcOpIdx1 > LastCommutableVecOp ||
1871 SrcOpIdx1 == KMaskOp))
1872 return false;
1873 if (SrcOpIdx2 != CommuteAnyOperandIndex &&
1874 (SrcOpIdx2 < FirstCommutableVecOp || SrcOpIdx2 > LastCommutableVecOp ||
1875 SrcOpIdx2 == KMaskOp))
1876 return false;
1877
1878 // Look for two different register operands assumed to be commutable
1879 // regardless of the FMA opcode. The FMA opcode is adjusted later.
1880 if (SrcOpIdx1 == CommuteAnyOperandIndex ||
1881 SrcOpIdx2 == CommuteAnyOperandIndex) {
1882 unsigned CommutableOpIdx1 = SrcOpIdx1;
1883 unsigned CommutableOpIdx2 = SrcOpIdx2;
1884
1885 // At least one of operands to be commuted is not specified and
1886 // this method is free to choose appropriate commutable operands.
1887 if (SrcOpIdx1 == SrcOpIdx2)
1888 // Both of operands are not fixed. By default set one of commutable
1889 // operands to the last register operand of the instruction.
1890 CommutableOpIdx2 = LastCommutableVecOp;
1891 else if (SrcOpIdx2 == CommuteAnyOperandIndex)
1892 // Only one of operands is not fixed.
1893 CommutableOpIdx2 = SrcOpIdx1;
1894
1895 // CommutableOpIdx2 is well defined now. Let's choose another commutable
1896 // operand and assign its index to CommutableOpIdx1.
1897 unsigned Op2Reg = MI.getOperand(CommutableOpIdx2).getReg();
1898 for (CommutableOpIdx1 = LastCommutableVecOp;
1899 CommutableOpIdx1 >= FirstCommutableVecOp; CommutableOpIdx1--) {
1900 // Just ignore and skip the k-mask operand.
1901 if (CommutableOpIdx1 == KMaskOp)
1902 continue;
1903
1904 // The commuted operands must have different registers.
1905 // Otherwise, the commute transformation does not change anything and
1906 // is useless then.
1907 if (Op2Reg != MI.getOperand(CommutableOpIdx1).getReg())
1908 break;
1909 }
1910
1911 // No appropriate commutable operands were found.
1912 if (CommutableOpIdx1 < FirstCommutableVecOp)
1913 return false;
1914
1915 // Assign the found pair of commutable indices to SrcOpIdx1 and SrcOpidx2
1916 // to return those values.
1917 if (!fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2,
1918 CommutableOpIdx1, CommutableOpIdx2))
1919 return false;
1920 }
1921
1922 return true;
1923}
1924
1925bool X86InstrInfo::findCommutedOpIndices(MachineInstr &MI, unsigned &SrcOpIdx1,
1926 unsigned &SrcOpIdx2) const {
1927 const MCInstrDesc &Desc = MI.getDesc();
1928 if (!Desc.isCommutable())
1929 return false;
1930
1931 switch (MI.getOpcode()) {
1932 case X86::CMPSDrr:
1933 case X86::CMPSSrr:
1934 case X86::CMPPDrri:
1935 case X86::CMPPSrri:
1936 case X86::VCMPSDrr:
1937 case X86::VCMPSSrr:
1938 case X86::VCMPPDrri:
1939 case X86::VCMPPSrri:
1940 case X86::VCMPPDYrri:
1941 case X86::VCMPPSYrri:
1942 case X86::VCMPSDZrr:
1943 case X86::VCMPSSZrr:
1944 case X86::VCMPPDZrri:
1945 case X86::VCMPPSZrri:
1946 case X86::VCMPPDZ128rri:
1947 case X86::VCMPPSZ128rri:
1948 case X86::VCMPPDZ256rri:
1949 case X86::VCMPPSZ256rri: {
1950 // Float comparison can be safely commuted for
1951 // Ordered/Unordered/Equal/NotEqual tests
1952 unsigned Imm = MI.getOperand(3).getImm() & 0x7;
1953 switch (Imm) {
1954 case 0x00: // EQUAL
1955 case 0x03: // UNORDERED
1956 case 0x04: // NOT EQUAL
1957 case 0x07: // ORDERED
1958 // The indices of the commutable operands are 1 and 2.
1959 // Assign them to the returned operand indices here.
1960 return fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2, 1, 2);
1961 }
1962 return false;
1963 }
1964 case X86::MOVSDrr:
1965 case X86::MOVSSrr:
1966 case X86::VMOVSDrr:
1967 case X86::VMOVSSrr:
1968 if (Subtarget.hasSSE41())
1969 return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
1970 return false;
1971 case X86::MOVHLPSrr:
1972 case X86::UNPCKHPDrr:
1973 case X86::VMOVHLPSrr:
1974 case X86::VUNPCKHPDrr:
1975 case X86::VMOVHLPSZrr:
1976 case X86::VUNPCKHPDZ128rr:
1977 if (Subtarget.hasSSE2())
1978 return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
1979 return false;
1980 case X86::VPTERNLOGDZrri: case X86::VPTERNLOGDZrmi:
1981 case X86::VPTERNLOGDZ128rri: case X86::VPTERNLOGDZ128rmi:
1982 case X86::VPTERNLOGDZ256rri: case X86::VPTERNLOGDZ256rmi:
1983 case X86::VPTERNLOGQZrri: case X86::VPTERNLOGQZrmi:
1984 case X86::VPTERNLOGQZ128rri: case X86::VPTERNLOGQZ128rmi:
1985 case X86::VPTERNLOGQZ256rri: case X86::VPTERNLOGQZ256rmi:
1986 case X86::VPTERNLOGDZrrik:
1987 case X86::VPTERNLOGDZ128rrik:
1988 case X86::VPTERNLOGDZ256rrik:
1989 case X86::VPTERNLOGQZrrik:
1990 case X86::VPTERNLOGQZ128rrik:
1991 case X86::VPTERNLOGQZ256rrik:
1992 case X86::VPTERNLOGDZrrikz: case X86::VPTERNLOGDZrmikz:
1993 case X86::VPTERNLOGDZ128rrikz: case X86::VPTERNLOGDZ128rmikz:
1994 case X86::VPTERNLOGDZ256rrikz: case X86::VPTERNLOGDZ256rmikz:
1995 case X86::VPTERNLOGQZrrikz: case X86::VPTERNLOGQZrmikz:
1996 case X86::VPTERNLOGQZ128rrikz: case X86::VPTERNLOGQZ128rmikz:
1997 case X86::VPTERNLOGQZ256rrikz: case X86::VPTERNLOGQZ256rmikz:
1998 case X86::VPTERNLOGDZ128rmbi:
1999 case X86::VPTERNLOGDZ256rmbi:
2000 case X86::VPTERNLOGDZrmbi:
2001 case X86::VPTERNLOGQZ128rmbi:
2002 case X86::VPTERNLOGQZ256rmbi:
2003 case X86::VPTERNLOGQZrmbi:
2004 case X86::VPTERNLOGDZ128rmbikz:
2005 case X86::VPTERNLOGDZ256rmbikz:
2006 case X86::VPTERNLOGDZrmbikz:
2007 case X86::VPTERNLOGQZ128rmbikz:
2008 case X86::VPTERNLOGQZ256rmbikz:
2009 case X86::VPTERNLOGQZrmbikz:
2010 return findThreeSrcCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
2011 case X86::VPMADD52HUQZ128r:
2012 case X86::VPMADD52HUQZ128rk:
2013 case X86::VPMADD52HUQZ128rkz:
2014 case X86::VPMADD52HUQZ256r:
2015 case X86::VPMADD52HUQZ256rk:
2016 case X86::VPMADD52HUQZ256rkz:
2017 case X86::VPMADD52HUQZr:
2018 case X86::VPMADD52HUQZrk:
2019 case X86::VPMADD52HUQZrkz:
2020 case X86::VPMADD52LUQZ128r:
2021 case X86::VPMADD52LUQZ128rk:
2022 case X86::VPMADD52LUQZ128rkz:
2023 case X86::VPMADD52LUQZ256r:
2024 case X86::VPMADD52LUQZ256rk:
2025 case X86::VPMADD52LUQZ256rkz:
2026 case X86::VPMADD52LUQZr:
2027 case X86::VPMADD52LUQZrk:
2028 case X86::VPMADD52LUQZrkz: {
2029 unsigned CommutableOpIdx1 = 2;
2030 unsigned CommutableOpIdx2 = 3;
2031 if (X86II::isKMasked(Desc.TSFlags)) {
2032 // Skip the mask register.
2033 ++CommutableOpIdx1;
2034 ++CommutableOpIdx2;
2035 }
2036 if (!fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2,
2037 CommutableOpIdx1, CommutableOpIdx2))
2038 return false;
2039 if (!MI.getOperand(SrcOpIdx1).isReg() ||
2040 !MI.getOperand(SrcOpIdx2).isReg())
2041 // No idea.
2042 return false;
2043 return true;
2044 }
2045
2046 default:
2047 const X86InstrFMA3Group *FMA3Group = getFMA3Group(MI.getOpcode(),
2048 MI.getDesc().TSFlags);
2049 if (FMA3Group)
2050 return findThreeSrcCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2,
2051 FMA3Group->isIntrinsic());
2052
2053 // Handled masked instructions since we need to skip over the mask input
2054 // and the preserved input.
2055 if (X86II::isKMasked(Desc.TSFlags)) {
2056 // First assume that the first input is the mask operand and skip past it.
2057 unsigned CommutableOpIdx1 = Desc.getNumDefs() + 1;
2058 unsigned CommutableOpIdx2 = Desc.getNumDefs() + 2;
2059 // Check if the first input is tied. If there isn't one then we only
2060 // need to skip the mask operand which we did above.
2061 if ((MI.getDesc().getOperandConstraint(Desc.getNumDefs(),
2062 MCOI::TIED_TO) != -1)) {
2063 // If this is zero masking instruction with a tied operand, we need to
2064 // move the first index back to the first input since this must
2065 // be a 3 input instruction and we want the first two non-mask inputs.
2066 // Otherwise this is a 2 input instruction with a preserved input and
2067 // mask, so we need to move the indices to skip one more input.
2068 if (X86II::isKMergeMasked(Desc.TSFlags)) {
2069 ++CommutableOpIdx1;
2070 ++CommutableOpIdx2;
2071 } else {
2072 --CommutableOpIdx1;
2073 }
2074 }
2075
2076 if (!fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2,
2077 CommutableOpIdx1, CommutableOpIdx2))
2078 return false;
2079
2080 if (!MI.getOperand(SrcOpIdx1).isReg() ||
2081 !MI.getOperand(SrcOpIdx2).isReg())
2082 // No idea.
2083 return false;
2084 return true;
2085 }
2086
2087 return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
2088 }
2089 return false;
2090}
2091
2092X86::CondCode X86::getCondFromBranchOpc(unsigned BrOpc) {
2093 switch (BrOpc) {
2094 default: return X86::COND_INVALID;
2095 case X86::JE_1: return X86::COND_E;
2096 case X86::JNE_1: return X86::COND_NE;
2097 case X86::JL_1: return X86::COND_L;
2098 case X86::JLE_1: return X86::COND_LE;
2099 case X86::JG_1: return X86::COND_G;
2100 case X86::JGE_1: return X86::COND_GE;
2101 case X86::JB_1: return X86::COND_B;
2102 case X86::JBE_1: return X86::COND_BE;
2103 case X86::JA_1: return X86::COND_A;
2104 case X86::JAE_1: return X86::COND_AE;
2105 case X86::JS_1: return X86::COND_S;
2106 case X86::JNS_1: return X86::COND_NS;
2107 case X86::JP_1: return X86::COND_P;
2108 case X86::JNP_1: return X86::COND_NP;
2109 case X86::JO_1: return X86::COND_O;
2110 case X86::JNO_1: return X86::COND_NO;
2111 }
2112}
2113
2114/// Return condition code of a SET opcode.
2115X86::CondCode X86::getCondFromSETOpc(unsigned Opc) {
2116 switch (Opc) {
2117 default: return X86::COND_INVALID;
2118 case X86::SETAr: case X86::SETAm: return X86::COND_A;
2119 case X86::SETAEr: case X86::SETAEm: return X86::COND_AE;
2120 case X86::SETBr: case X86::SETBm: return X86::COND_B;
2121 case X86::SETBEr: case X86::SETBEm: return X86::COND_BE;
2122 case X86::SETEr: case X86::SETEm: return X86::COND_E;
2123 case X86::SETGr: case X86::SETGm: return X86::COND_G;
2124 case X86::SETGEr: case X86::SETGEm: return X86::COND_GE;
2125 case X86::SETLr: case X86::SETLm: return X86::COND_L;
2126 case X86::SETLEr: case X86::SETLEm: return X86::COND_LE;
2127 case X86::SETNEr: case X86::SETNEm: return X86::COND_NE;
2128 case X86::SETNOr: case X86::SETNOm: return X86::COND_NO;
2129 case X86::SETNPr: case X86::SETNPm: return X86::COND_NP;
2130 case X86::SETNSr: case X86::SETNSm: return X86::COND_NS;
2131 case X86::SETOr: case X86::SETOm: return X86::COND_O;
2132 case X86::SETPr: case X86::SETPm: return X86::COND_P;
2133 case X86::SETSr: case X86::SETSm: return X86::COND_S;
2134 }
2135}
2136
2137/// Return condition code of a CMov opcode.
2138X86::CondCode X86::getCondFromCMovOpc(unsigned Opc) {
2139 switch (Opc) {
2140 default: return X86::COND_INVALID;
2141 case X86::CMOVA16rm: case X86::CMOVA16rr: case X86::CMOVA32rm:
2142 case X86::CMOVA32rr: case X86::CMOVA64rm: case X86::CMOVA64rr:
2143 return X86::COND_A;
2144 case X86::CMOVAE16rm: case X86::CMOVAE16rr: case X86::CMOVAE32rm:
2145 case X86::CMOVAE32rr: case X86::CMOVAE64rm: case X86::CMOVAE64rr:
2146 return X86::COND_AE;
2147 case X86::CMOVB16rm: case X86::CMOVB16rr: case X86::CMOVB32rm:
2148 case X86::CMOVB32rr: case X86::CMOVB64rm: case X86::CMOVB64rr:
2149 return X86::COND_B;
2150 case X86::CMOVBE16rm: case X86::CMOVBE16rr: case X86::CMOVBE32rm:
2151 case X86::CMOVBE32rr: case X86::CMOVBE64rm: case X86::CMOVBE64rr:
2152 return X86::COND_BE;
2153 case X86::CMOVE16rm: case X86::CMOVE16rr: case X86::CMOVE32rm:
2154 case X86::CMOVE32rr: case X86::CMOVE64rm: case X86::CMOVE64rr:
2155 return X86::COND_E;
2156 case X86::CMOVG16rm: case X86::CMOVG16rr: case X86::CMOVG32rm:
2157 case X86::CMOVG32rr: case X86::CMOVG64rm: case X86::CMOVG64rr:
2158 return X86::COND_G;
2159 case X86::CMOVGE16rm: case X86::CMOVGE16rr: case X86::CMOVGE32rm:
2160 case X86::CMOVGE32rr: case X86::CMOVGE64rm: case X86::CMOVGE64rr:
2161 return X86::COND_GE;
2162 case X86::CMOVL16rm: case X86::CMOVL16rr: case X86::CMOVL32rm:
2163 case X86::CMOVL32rr: case X86::CMOVL64rm: case X86::CMOVL64rr:
2164 return X86::COND_L;
2165 case X86::CMOVLE16rm: case X86::CMOVLE16rr: case X86::CMOVLE32rm:
2166 case X86::CMOVLE32rr: case X86::CMOVLE64rm: case X86::CMOVLE64rr:
2167 return X86::COND_LE;
2168 case X86::CMOVNE16rm: case X86::CMOVNE16rr: case X86::CMOVNE32rm:
2169 case X86::CMOVNE32rr: case X86::CMOVNE64rm: case X86::CMOVNE64rr:
2170 return X86::COND_NE;
2171 case X86::CMOVNO16rm: case X86::CMOVNO16rr: case X86::CMOVNO32rm:
2172 case X86::CMOVNO32rr: case X86::CMOVNO64rm: case X86::CMOVNO64rr:
2173 return X86::COND_NO;
2174 case X86::CMOVNP16rm: case X86::CMOVNP16rr: case X86::CMOVNP32rm:
2175 case X86::CMOVNP32rr: case X86::CMOVNP64rm: case X86::CMOVNP64rr:
2176 return X86::COND_NP;
2177 case X86::CMOVNS16rm: case X86::CMOVNS16rr: case X86::CMOVNS32rm:
2178 case X86::CMOVNS32rr: case X86::CMOVNS64rm: case X86::CMOVNS64rr:
2179 return X86::COND_NS;
2180 case X86::CMOVO16rm: case X86::CMOVO16rr: case X86::CMOVO32rm:
2181 case X86::CMOVO32rr: case X86::CMOVO64rm: case X86::CMOVO64rr:
2182 return X86::COND_O;
2183 case X86::CMOVP16rm: case X86::CMOVP16rr: case X86::CMOVP32rm:
2184 case X86::CMOVP32rr: case X86::CMOVP64rm: case X86::CMOVP64rr:
2185 return X86::COND_P;
2186 case X86::CMOVS16rm: case X86::CMOVS16rr: case X86::CMOVS32rm:
2187 case X86::CMOVS32rr: case X86::CMOVS64rm: case X86::CMOVS64rr:
2188 return X86::COND_S;
2189 }
2190}
2191
2192unsigned X86::GetCondBranchFromCond(X86::CondCode CC) {
2193 switch (CC) {
2194 default: llvm_unreachable("Illegal condition code!")::llvm::llvm_unreachable_internal("Illegal condition code!", "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/X86/X86InstrInfo.cpp"
, 2194)
;
2195 case X86::COND_E: return X86::JE_1;
2196 case X86::COND_NE: return X86::JNE_1;
2197 case X86::COND_L: return X86::JL_1;
2198 case X86::COND_LE: return X86::JLE_1;
2199 case X86::COND_G: return X86::JG_1;
2200 case X86::COND_GE: return X86::JGE_1;
2201 case X86::COND_B: return X86::JB_1;
2202 case X86::COND_BE: return X86::JBE_1;
2203 case X86::COND_A: return X86::JA_1;
2204 case X86::COND_AE: return X86::JAE_1;
2205 case X86::COND_S: return X86::JS_1;
2206 case X86::COND_NS: return X86::JNS_1;
2207 case X86::COND_P: return X86::JP_1;
2208 case X86::COND_NP: return X86::JNP_1;
2209 case X86::COND_O: return X86::JO_1;
2210 case X86::COND_NO: return X86::JNO_1;
2211 }
2212}
2213
2214/// Return the inverse of the specified condition,
2215/// e.g. turning COND_E to COND_NE.
2216X86::CondCode X86::GetOppositeBranchCondition(X86::CondCode CC) {
2217 switch (CC) {
2218 default: llvm_unreachable("Illegal condition code!")::llvm::llvm_unreachable_internal("Illegal condition code!", "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/X86/X86InstrInfo.cpp"
, 2218)
;
2219 case X86::COND_E: return X86::COND_NE;
2220 case X86::COND_NE: return X86::COND_E;
2221 case X86::COND_L: return X86::COND_GE;
2222 case X86::COND_LE: return X86::COND_G;
2223 case X86::COND_G: return X86::COND_LE;
2224 case X86::COND_GE: return X86::COND_L;
2225 case X86::COND_B: return X86::COND_AE;
2226 case X86::COND_BE: return X86::COND_A;
2227 case X86::COND_A: return X86::COND_BE;
2228 case X86::COND_AE: return X86::COND_B;
2229 case X86::COND_S: return X86::COND_NS;
2230 case X86::COND_NS: return X86::COND_S;
2231 case X86::COND_P: return X86::COND_NP;
2232 case X86::COND_NP: return X86::COND_P;
2233 case X86::COND_O: return X86::COND_NO;
2234 case X86::COND_NO: return X86::COND_O;
2235 case X86::COND_NE_OR_P: return X86::COND_E_AND_NP;
2236 case X86::COND_E_AND_NP: return X86::COND_NE_OR_P;
2237 }
2238}
2239
2240/// Assuming the flags are set by MI(a,b), return the condition code if we
2241/// modify the instructions such that flags are set by MI(b,a).
2242static X86::CondCode getSwappedCondition(X86::CondCode CC) {
2243 switch (CC) {
2244 default: return X86::COND_INVALID;
2245 case X86::COND_E: return X86::COND_E;
2246 case X86::COND_NE: return X86::COND_NE;
2247 case X86::COND_L: return X86::COND_G;
2248 case X86::COND_LE: return X86::COND_GE;
2249 case X86::COND_G: return X86::COND_L;
2250 case X86::COND_GE: return X86::COND_LE;
2251 case X86::COND_B: return X86::COND_A;
2252 case X86::COND_BE: return X86::COND_AE;
2253 case X86::COND_A: return X86::COND_B;
2254 case X86::COND_AE: return X86::COND_BE;
2255 }
2256}
2257
2258std::pair<X86::CondCode, bool>
2259X86::getX86ConditionCode(CmpInst::Predicate Predicate) {
2260 X86::CondCode CC = X86::COND_INVALID;
2261 bool NeedSwap = false;
2262 switch (Predicate) {
2263 default: break;
2264 // Floating-point Predicates
2265 case CmpInst::FCMP_UEQ: CC = X86::COND_E; break;
2266 case CmpInst::FCMP_OLT: NeedSwap = true; LLVM_FALLTHROUGH[[clang::fallthrough]];
2267 case CmpInst::FCMP_OGT: CC = X86::COND_A; break;
2268 case CmpInst::FCMP_OLE: NeedSwap = true; LLVM_FALLTHROUGH[[clang::fallthrough]];
2269 case CmpInst::FCMP_OGE: CC = X86::COND_AE; break;
2270 case CmpInst::FCMP_UGT: NeedSwap = true; LLVM_FALLTHROUGH[[clang::fallthrough]];
2271 case CmpInst::FCMP_ULT: CC = X86::COND_B; break;
2272 case CmpInst::FCMP_UGE: NeedSwap = true; LLVM_FALLTHROUGH[[clang::fallthrough]];
2273 case CmpInst::FCMP_ULE: CC = X86::COND_BE; break;
2274 case CmpInst::FCMP_ONE: CC = X86::COND_NE; break;
2275 case CmpInst::FCMP_UNO: CC = X86::COND_P; break;
2276 case CmpInst::FCMP_ORD: CC = X86::COND_NP; break;
2277 case CmpInst::FCMP_OEQ: LLVM_FALLTHROUGH[[clang::fallthrough]];
2278 case CmpInst::FCMP_UNE: CC = X86::COND_INVALID; break;
2279
2280 // Integer Predicates
2281 case CmpInst::ICMP_EQ: CC = X86::COND_E; break;
2282 case CmpInst::ICMP_NE: CC = X86::COND_NE; break;
2283 case CmpInst::ICMP_UGT: CC = X86::COND_A; break;
2284 case CmpInst::ICMP_UGE: CC = X86::COND_AE; break;
2285 case CmpInst::ICMP_ULT: CC = X86::COND_B; break;
2286 case CmpInst::ICMP_ULE: CC = X86::COND_BE; break;
2287 case CmpInst::ICMP_SGT: CC = X86::COND_G; break;
2288 case CmpInst::ICMP_SGE: CC = X86::COND_GE; break;
2289 case CmpInst::ICMP_SLT: CC = X86::COND_L; break;
2290 case CmpInst::ICMP_SLE: CC = X86::COND_LE; break;
2291 }
2292
2293 return std::make_pair(CC, NeedSwap);
2294}
2295
2296/// Return a set opcode for the given condition and
2297/// whether it has memory operand.
2298unsigned X86::getSETFromCond(CondCode CC, bool HasMemoryOperand) {
2299 static const uint16_t Opc[16][2] = {
2300 { X86::SETAr, X86::SETAm },
2301 { X86::SETAEr, X86::SETAEm },
2302 { X86::SETBr, X86::SETBm },
2303 { X86::SETBEr, X86::SETBEm },
2304 { X86::SETEr, X86::SETEm },
2305 { X86::SETGr, X86::SETGm },
2306 { X86::SETGEr, X86::SETGEm },
2307 { X86::SETLr, X86::SETLm },
2308 { X86::SETLEr, X86::SETLEm },
2309 { X86::SETNEr, X86::SETNEm },
2310 { X86::SETNOr, X86::SETNOm },
2311 { X86::SETNPr, X86::SETNPm },
2312 { X86::SETNSr, X86::SETNSm },
2313 { X86::SETOr, X86::SETOm },
2314 { X86::SETPr, X86::SETPm },
2315 { X86::SETSr, X86::SETSm }
2316 };
2317
2318 assert(CC <= LAST_VALID_COND && "Can only handle standard cond codes")((CC <= LAST_VALID_COND && "Can only handle standard cond codes"
) ? static_cast<void> (0) : __assert_fail ("CC <= LAST_VALID_COND && \"Can only handle standard cond codes\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/X86/X86InstrInfo.cpp"
, 2318, __PRETTY_FUNCTION__))
;
2319 return Opc[CC][HasMemoryOperand ? 1 : 0];
2320}
2321
2322/// Return a cmov opcode for the given condition,
2323/// register size in bytes, and operand type.
2324unsigned X86::getCMovFromCond(CondCode CC, unsigned RegBytes,
2325 bool HasMemoryOperand) {
2326 static const uint16_t Opc[32][3] = {
2327 { X86::CMOVA16rr, X86::CMOVA32rr, X86::CMOVA64rr },
2328 { X86::CMOVAE16rr, X86::CMOVAE32rr, X86::CMOVAE64rr },
2329 { X86::CMOVB16rr, X86::CMOVB32rr, X86::CMOVB64rr },
2330 { X86::CMOVBE16rr, X86::CMOVBE32rr, X86::CMOVBE64rr },
2331 { X86::CMOVE16rr, X86::CMOVE32rr, X86::CMOVE64rr },
2332 { X86::CMOVG16rr, X86::CMOVG32rr, X86::CMOVG64rr },
2333 { X86::CMOVGE16rr, X86::CMOVGE32rr, X86::CMOVGE64rr },
2334 { X86::CMOVL16rr, X86::CMOVL32rr, X86::CMOVL64rr },
2335 { X86::CMOVLE16rr, X86::CMOVLE32rr, X86::CMOVLE64rr },
2336 { X86::CMOVNE16rr, X86::CMOVNE32rr, X86::CMOVNE64rr },
2337 { X86::CMOVNO16rr, X86::CMOVNO32rr, X86::CMOVNO64rr },
2338 { X86::CMOVNP16rr, X86::CMOVNP32rr, X86::CMOVNP64rr },
2339 { X86::CMOVNS16rr, X86::CMOVNS32rr, X86::CMOVNS64rr },
2340 { X86::CMOVO16rr, X86::CMOVO32rr, X86::CMOVO64rr },
2341 { X86::CMOVP16rr, X86::CMOVP32rr, X86::CMOVP64rr },
2342 { X86::CMOVS16rr, X86::CMOVS32rr, X86::CMOVS64rr },
2343 { X86::CMOVA16rm, X86::CMOVA32rm, X86::CMOVA64rm },
2344 { X86::CMOVAE16rm, X86::CMOVAE32rm, X86::CMOVAE64rm },
2345 { X86::CMOVB16rm, X86::CMOVB32rm, X86::CMOVB64rm },
2346 { X86::CMOVBE16rm, X86::CMOVBE32rm, X86::CMOVBE64rm },
2347 { X86::CMOVE16rm, X86::CMOVE32rm, X86::CMOVE64rm },
2348 { X86::CMOVG16rm, X86::CMOVG32rm, X86::CMOVG64rm },
2349 { X86::CMOVGE16rm, X86::CMOVGE32rm, X86::CMOVGE64rm },
2350 { X86::CMOVL16rm, X86::CMOVL32rm, X86::CMOVL64rm },
2351 { X86::CMOVLE16rm, X86::CMOVLE32rm, X86::CMOVLE64rm },
2352 { X86::CMOVNE16rm, X86::CMOVNE32rm, X86::CMOVNE64rm },
2353 { X86::CMOVNO16rm, X86::CMOVNO32rm, X86::CMOVNO64rm },
2354 { X86::CMOVNP16rm, X86::CMOVNP32rm, X86::CMOVNP64rm },
2355 { X86::CMOVNS16rm, X86::CMOVNS32rm, X86::CMOVNS64rm },
2356 { X86::CMOVO16rm, X86::CMOVO32rm, X86::CMOVO64rm },
2357 { X86::CMOVP16rm, X86::CMOVP32rm, X86::CMOVP64rm },
2358 { X86::CMOVS16rm, X86::CMOVS32rm, X86::CMOVS64rm }
2359 };
2360
2361 assert(CC < 16 && "Can only handle standard cond codes")((CC < 16 && "Can only handle standard cond codes"
) ? static_cast<void> (0) : __assert_fail ("CC < 16 && \"Can only handle standard cond codes\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/X86/X86InstrInfo.cpp"
, 2361, __PRETTY_FUNCTION__))
;
2362 unsigned Idx = HasMemoryOperand ? 16+CC : CC;
2363 switch(RegBytes) {
2364 default: llvm_unreachable("Illegal register size!")::llvm::llvm_unreachable_internal("Illegal register size!", "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/X86/X86InstrInfo.cpp"
, 2364)
;
2365 case 2: return Opc[Idx][0];
2366 case 4: return Opc[Idx][1];
2367 case 8: return Opc[Idx][2];
2368 }
2369}
2370
2371/// Get the VPCMP immediate for the given condition.
2372unsigned X86::getVPCMPImmForCond(ISD::CondCode CC) {
2373 switch (CC) {
2374 default: llvm_unreachable("Unexpected SETCC condition")::llvm::llvm_unreachable_internal("Unexpected SETCC condition"
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/X86/X86InstrInfo.cpp"
, 2374)
;
2375 case ISD::SETNE: return 4;
2376 case ISD::SETEQ: return 0;
2377 case ISD::SETULT:
2378 case ISD::SETLT: return 1;
2379 case ISD::SETUGT:
2380 case ISD::SETGT: return 6;
2381 case ISD::SETUGE:
2382 case ISD::SETGE: return 5;
2383 case ISD::SETULE:
2384 case ISD::SETLE: return 2;
2385 }
2386}
2387
2388/// Get the VPCMP immediate if the opcodes are swapped.
2389unsigned X86::getSwappedVPCMPImm(unsigned Imm) {
2390 switch (Imm) {
2391 default: llvm_unreachable("Unreachable!")::llvm::llvm_unreachable_internal("Unreachable!", "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/X86/X86InstrInfo.cpp"
, 2391)
;
2392 case 0x01: Imm = 0x06; break; // LT -> NLE
2393 case 0x02: Imm = 0x05; break; // LE -> NLT
2394 case 0x05: Imm = 0x02; break; // NLT -> LE
2395 case 0x06: Imm = 0x01; break; // NLE -> LT
2396 case 0x00: // EQ
2397 case 0x03: // FALSE
2398 case 0x04: // NE
2399 case 0x07: // TRUE
2400 break;
2401 }
2402
2403 return Imm;
2404}
2405
2406/// Get the VPCOM immediate if the opcodes are swapped.
2407unsigned X86::getSwappedVPCOMImm(unsigned Imm) {
2408 switch (Imm) {
2409 default: llvm_unreachable("Unreachable!")::llvm::llvm_unreachable_internal("Unreachable!", "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/X86/X86InstrInfo.cpp"
, 2409)
;
2410 case 0x00: Imm = 0x02; break; // LT -> GT
2411 case 0x01: Imm = 0x03; break; // LE -> GE
2412 case 0x02: Imm = 0x00; break; // GT -> LT
2413 case 0x03: Imm = 0x01; break; // GE -> LE
2414 case 0x04: // EQ
2415 case 0x05: // NE
2416 case 0x06: // FALSE
2417 case 0x07: // TRUE
2418 break;
2419 }
2420
2421 return Imm;
2422}
2423
2424bool X86InstrInfo::isUnpredicatedTerminator(const MachineInstr &MI) const {
2425 if (!MI.isTerminator()) return false;
2426
2427 // Conditional branch is a special case.
2428 if (MI.isBranch() && !MI.isBarrier())
2429 return true;
2430 if (!MI.isPredicable())
2431 return true;
2432 return !isPredicated(MI);
2433}
2434
2435bool X86InstrInfo::isUnconditionalTailCall(const MachineInstr &MI) const {
2436 switch (MI.getOpcode()) {
2437 case X86::TCRETURNdi:
2438 case X86::TCRETURNri:
2439 case X86::TCRETURNmi:
2440 case X86::TCRETURNdi64:
2441 case X86::TCRETURNri64:
2442 case X86::TCRETURNmi64:
2443 return true;
2444 default:
2445 return false;
2446 }
2447}
2448
2449bool X86InstrInfo::canMakeTailCallConditional(
2450 SmallVectorImpl<MachineOperand> &BranchCond,
2451 const MachineInstr &TailCall) const {
2452 if (TailCall.getOpcode() != X86::TCRETURNdi &&
2453 TailCall.getOpcode() != X86::TCRETURNdi64) {
2454 // Only direct calls can be done with a conditional branch.
2455 return false;
2456 }
2457
2458 const MachineFunction *MF = TailCall.getParent()->getParent();
2459 if (Subtarget.isTargetWin64() && MF->hasWinCFI()) {
2460 // Conditional tail calls confuse the Win64 unwinder.
2461 return false;
2462 }
2463
2464 assert(BranchCond.size() == 1)((BranchCond.size() == 1) ? static_cast<void> (0) : __assert_fail
("BranchCond.size() == 1", "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/X86/X86InstrInfo.cpp"
, 2464, __PRETTY_FUNCTION__))
;
2465 if (BranchCond[0].getImm() > X86::LAST_VALID_COND) {
2466 // Can't make a conditional tail call with this condition.
2467 return false;
2468 }
2469
2470 const X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
2471 if (X86FI->getTCReturnAddrDelta() != 0 ||
2472 TailCall.getOperand(1).getImm() != 0) {
2473 // A conditional tail call cannot do any stack adjustment.
2474 return false;
2475 }
2476
2477 return true;
2478}
2479
2480void X86InstrInfo::replaceBranchWithTailCall(
2481 MachineBasicBlock &MBB, SmallVectorImpl<MachineOperand> &BranchCond,
2482 const MachineInstr &TailCall) const {
2483 assert(canMakeTailCallConditional(BranchCond, TailCall))((canMakeTailCallConditional(BranchCond, TailCall)) ? static_cast
<void> (0) : __assert_fail ("canMakeTailCallConditional(BranchCond, TailCall)"
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/X86/X86InstrInfo.cpp"
, 2483, __PRETTY_FUNCTION__))
;
2484
2485 MachineBasicBlock::iterator I = MBB.end();
2486 while (I != MBB.begin()) {
2487 --I;
2488 if (I->isDebugInstr())
2489 continue;
2490 if (!I->isBranch())
2491 assert(0 && "Can't find the branch to replace!")((0 && "Can't find the branch to replace!") ? static_cast
<void> (0) : __assert_fail ("0 && \"Can't find the branch to replace!\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/X86/X86InstrInfo.cpp"
, 2491, __PRETTY_FUNCTION__))
;
2492
2493 X86::CondCode CC = X86::getCondFromBranchOpc(I->getOpcode());
2494 assert(BranchCond.size() == 1)((BranchCond.size() == 1) ? static_cast<void> (0) : __assert_fail
("BranchCond.size() == 1", "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/X86/X86InstrInfo.cpp"
, 2494, __PRETTY_FUNCTION__))
;
2495 if (CC != BranchCond[0].getImm())
2496 continue;
2497
2498 break;
2499 }
2500
2501 unsigned Opc = TailCall.getOpcode() == X86::TCRETURNdi ? X86::TCRETURNdicc
2502 : X86::TCRETURNdi64cc;
2503
2504 auto MIB = BuildMI(MBB, I, MBB.findDebugLoc(I), get(Opc));
2505 MIB->addOperand(TailCall.getOperand(0)); // Destination.
2506 MIB.addImm(0); // Stack offset (not used).
2507 MIB->addOperand(BranchCond[0]); // Condition.
2508 MIB.copyImplicitOps(TailCall); // Regmask and (imp-used) parameters.
2509
2510 // Add implicit uses and defs of all live regs potentially clobbered by the
2511 // call. This way they still appear live across the call.
2512 LivePhysRegs LiveRegs(getRegisterInfo());
2513 LiveRegs.addLiveOuts(MBB);
2514 SmallVector<std::pair<MCPhysReg, const MachineOperand *>, 8> Clobbers;
2515 LiveRegs.stepForward(*MIB, Clobbers);
2516 for (const auto &C : Clobbers) {
2517 MIB.addReg(C.first, RegState::Implicit);
2518 MIB.addReg(C.first, RegState::Implicit | RegState::Define);
2519 }
2520
2521 I->eraseFromParent();
2522}
2523
2524// Given a MBB and its TBB, find the FBB which was a fallthrough MBB (it may
2525// not be a fallthrough MBB now due to layout changes). Return nullptr if the
2526// fallthrough MBB cannot be identified.
2527static MachineBasicBlock *getFallThroughMBB(MachineBasicBlock *MBB,
2528 MachineBasicBlock *TBB) {
2529 // Look for non-EHPad successors other than TBB. If we find exactly one, it
2530 // is the fallthrough MBB. If we find zero, then TBB is both the target MBB
2531 // and fallthrough MBB. If we find more than one, we cannot identify the
2532 // fallthrough MBB and should return nullptr.
2533 MachineBasicBlock *FallthroughBB = nullptr;
2534 for (auto SI = MBB->succ_begin(), SE = MBB->succ_end(); SI != SE; ++SI) {
2535 if ((*SI)->isEHPad() || (*SI == TBB && FallthroughBB))
2536 continue;
2537 // Return a nullptr if we found more than one fallthrough successor.
2538 if (FallthroughBB && FallthroughBB != TBB)
2539 return nullptr;
2540 FallthroughBB = *SI;
2541 }
2542 return FallthroughBB;
2543}
2544
2545bool X86InstrInfo::AnalyzeBranchImpl(
2546 MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB,
2547 SmallVectorImpl<MachineOperand> &Cond,
2548 SmallVectorImpl<MachineInstr *> &CondBranches, bool AllowModify) const {
2549
2550 // Start from the bottom of the block and work up, examining the
2551 // terminator instructions.
2552 MachineBasicBlock::iterator I = MBB.end();
2553 MachineBasicBlock::iterator UnCondBrIter = MBB.end();
2554 while (I != MBB.begin()) {
2555 --I;
2556 if (I->isDebugInstr())
2557 continue;
2558
2559 // Working from the bottom, when we see a non-terminator instruction, we're
2560 // done.
2561 if (!isUnpredicatedTerminator(*I))
2562 break;
2563
2564 // A terminator that isn't a branch can't easily be handled by this
2565 // analysis.
2566 if (!I->isBranch())
2567 return true;
2568
2569 // Handle unconditional branches.
2570 if (I->getOpcode() == X86::JMP_1) {
2571 UnCondBrIter = I;
2572
2573 if (!AllowModify) {
2574 TBB = I->getOperand(0).getMBB();
2575 continue;
2576 }
2577
2578 // If the block has any instructions after a JMP, delete them.
2579 while (std::next(I) != MBB.end())
2580 std::next(I)->eraseFromParent();
2581
2582 Cond.clear();
2583 FBB = nullptr;
2584
2585 // Delete the JMP if it's equivalent to a fall-through.
2586 if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
2587 TBB = nullptr;
2588 I->eraseFromParent();
2589 I = MBB.end();
2590 UnCondBrIter = MBB.end();
2591 continue;
2592 }
2593
2594 // TBB is used to indicate the unconditional destination.
2595 TBB = I->getOperand(0).getMBB();
2596 continue;
2597 }
2598
2599 // Handle conditional branches.
2600 X86::CondCode BranchCode = X86::getCondFromBranchOpc(I->getOpcode());
2601 if (BranchCode == X86::COND_INVALID)
2602 return true; // Can't handle indirect branch.
2603
2604 // In practice we should never have an undef eflags operand, if we do
2605 // abort here as we are not prepared to preserve the flag.
2606 if (I->getOperand(1).isUndef())
2607 return true;
2608
2609 // Working from the bottom, handle the first conditional branch.
2610 if (Cond.empty()) {
2611 MachineBasicBlock *TargetBB = I->getOperand(0).getMBB();
2612 if (AllowModify && UnCondBrIter != MBB.end() &&
2613 MBB.isLayoutSuccessor(TargetBB)) {
2614 // If we can modify the code and it ends in something like:
2615 //
2616 // jCC L1
2617 // jmp L2
2618 // L1:
2619 // ...
2620 // L2:
2621 //
2622 // Then we can change this to:
2623 //
2624 // jnCC L2
2625 // L1:
2626 // ...
2627 // L2:
2628 //
2629 // Which is a bit more efficient.
2630 // We conditionally jump to the fall-through block.
2631 BranchCode = GetOppositeBranchCondition(BranchCode);
2632 unsigned JNCC = GetCondBranchFromCond(BranchCode);
2633 MachineBasicBlock::iterator OldInst = I;
2634
2635 BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(JNCC))
2636 .addMBB(UnCondBrIter->getOperand(0).getMBB());
2637 BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(X86::JMP_1))
2638 .addMBB(TargetBB);
2639
2640 OldInst->eraseFromParent();
2641 UnCondBrIter->eraseFromParent();
2642
2643 // Restart the analysis.
2644 UnCondBrIter = MBB.end();
2645 I = MBB.end();
2646 continue;
2647 }
2648
2649 FBB = TBB;
2650 TBB = I->getOperand(0).getMBB();
2651 Cond.push_back(MachineOperand::CreateImm(BranchCode));
2652 CondBranches.push_back(&*I);
2653 continue;
2654 }
2655
2656 // Handle subsequent conditional branches. Only handle the case where all
2657 // conditional branches branch to the same destination and their condition
2658 // opcodes fit one of the special multi-branch idioms.
2659 assert(Cond.size() == 1)((Cond.size() == 1) ? static_cast<void> (0) : __assert_fail
("Cond.size() == 1", "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/X86/X86InstrInfo.cpp"
, 2659, __PRETTY_FUNCTION__))
;
2660 assert(TBB)((TBB) ? static_cast<void> (0) : __assert_fail ("TBB", "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/X86/X86InstrInfo.cpp"
, 2660, __PRETTY_FUNCTION__))
;
2661
2662 // If the conditions are the same, we can leave them alone.
2663 X86::CondCode OldBranchCode = (X86::CondCode)Cond[0].getImm();
2664 auto NewTBB = I->getOperand(0).getMBB();
2665 if (OldBranchCode == BranchCode && TBB == NewTBB)
2666 continue;
2667
2668 // If they differ, see if they fit one of the known patterns. Theoretically,
2669 // we could handle more patterns here, but we shouldn't expect to see them
2670 // if instruction selection has done a reasonable job.
2671 if (TBB == NewTBB &&
2672 ((OldBranchCode == X86::COND_P && BranchCode == X86::COND_NE) ||
2673 (OldBranchCode == X86::COND_NE && BranchCode == X86::COND_P))) {
2674 BranchCode = X86::COND_NE_OR_P;
2675 } else if ((OldBranchCode == X86::COND_NP && BranchCode == X86::COND_NE) ||
2676 (OldBranchCode == X86::COND_E && BranchCode == X86::COND_P)) {
2677 if (NewTBB != (FBB ? FBB : getFallThroughMBB(&MBB, TBB)))
2678 return true;
2679
2680 // X86::COND_E_AND_NP usually has two different branch destinations.
2681 //
2682 // JP B1
2683 // JE B2
2684 // JMP B1
2685 // B1:
2686 // B2:
2687 //
2688 // Here this condition branches to B2 only if NP && E. It has another
2689 // equivalent form:
2690 //
2691 // JNE B1
2692 // JNP B2
2693 // JMP B1
2694 // B1:
2695 // B2:
2696 //
2697 // Similarly it branches to B2 only if E && NP. That is why this condition
2698 // is named with COND_E_AND_NP.
2699 BranchCode = X86::COND_E_AND_NP;
2700 } else
2701 return true;
2702
2703 // Update the MachineOperand.
2704 Cond[0].setImm(BranchCode);
2705 CondBranches.push_back(&*I);
2706 }
2707
2708 return false;
2709}
2710
2711bool X86InstrInfo::analyzeBranch(MachineBasicBlock &MBB,
2712 MachineBasicBlock *&TBB,
2713 MachineBasicBlock *&FBB,
2714 SmallVectorImpl<MachineOperand> &Cond,
2715 bool AllowModify) const {
2716 SmallVector<MachineInstr *, 4> CondBranches;
2717 return AnalyzeBranchImpl(MBB, TBB, FBB, Cond, CondBranches, AllowModify);
2718}
2719
2720bool X86InstrInfo::analyzeBranchPredicate(MachineBasicBlock &MBB,
2721 MachineBranchPredicate &MBP,
2722 bool AllowModify) const {
2723 using namespace std::placeholders;
2724
2725 SmallVector<MachineOperand, 4> Cond;
2726 SmallVector<MachineInstr *, 4> CondBranches;
2727 if (AnalyzeBranchImpl(MBB, MBP.TrueDest, MBP.FalseDest, Cond, CondBranches,
2728 AllowModify))
2729 return true;
2730
2731 if (Cond.size() != 1)
2732 return true;
2733
2734 assert(MBP.TrueDest && "expected!")((MBP.TrueDest && "expected!") ? static_cast<void>
(0) : __assert_fail ("MBP.TrueDest && \"expected!\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/X86/X86InstrInfo.cpp"
, 2734, __PRETTY_FUNCTION__))
;
2735
2736 if (!MBP.FalseDest)
2737 MBP.FalseDest = MBB.getNextNode();
2738
2739 const TargetRegisterInfo *TRI = &getRegisterInfo();
2740
2741 MachineInstr *ConditionDef = nullptr;
2742 bool SingleUseCondition = true;
2743
2744 for (auto I = std::next(MBB.rbegin()), E = MBB.rend(); I != E; ++I) {
2745 if (I->modifiesRegister(X86::EFLAGS, TRI)) {
2746 ConditionDef = &*I;
2747 break;
2748 }
2749
2750 if (I->readsRegister(X86::EFLAGS, TRI))
2751 SingleUseCondition = false;
2752 }
2753
2754 if (!ConditionDef)
2755 return true;
2756
2757 if (SingleUseCondition) {
2758 for (auto *Succ : MBB.successors())
2759 if (Succ->isLiveIn(X86::EFLAGS))
2760 SingleUseCondition = false;
2761 }
2762
2763 MBP.ConditionDef = ConditionDef;
2764 MBP.SingleUseCondition = SingleUseCondition;
2765
2766 // Currently we only recognize the simple pattern:
2767 //
2768 // test %reg, %reg
2769 // je %label
2770 //
2771 const unsigned TestOpcode =
2772 Subtarget.is64Bit() ? X86::TEST64rr : X86::TEST32rr;
2773
2774 if (ConditionDef->getOpcode() == TestOpcode &&
2775 ConditionDef->getNumOperands() == 3 &&
2776 ConditionDef->getOperand(0).isIdenticalTo(ConditionDef->getOperand(1)) &&
2777 (Cond[0].getImm() == X86::COND_NE || Cond[0].getImm() == X86::COND_E)) {
2778 MBP.LHS = ConditionDef->getOperand(0);
2779 MBP.RHS = MachineOperand::CreateImm(0);
2780 MBP.Predicate = Cond[0].getImm() == X86::COND_NE
2781 ? MachineBranchPredicate::PRED_NE
2782 : MachineBranchPredicate::PRED_EQ;
2783 return false;
2784 }
2785
2786 return true;
2787}
2788
2789unsigned X86InstrInfo::removeBranch(MachineBasicBlock &MBB,
2790 int *BytesRemoved) const {
2791 assert(!BytesRemoved && "code size not handled")((!BytesRemoved && "code size not handled") ? static_cast
<void> (0) : __assert_fail ("!BytesRemoved && \"code size not handled\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/X86/X86InstrInfo.cpp"
, 2791, __PRETTY_FUNCTION__))
;
2792
2793 MachineBasicBlock::iterator I = MBB.end();
2794 unsigned Count = 0;
2795
2796 while (I != MBB.begin()) {
2797 --I;
2798 if (I->isDebugInstr())
2799 continue;
2800 if (I->getOpcode() != X86::JMP_1 &&
2801 X86::getCondFromBranchOpc(I->getOpcode()) == X86::COND_INVALID)
2802 break;
2803 // Remove the branch.
2804 I->eraseFromParent();
2805 I = MBB.end();
2806 ++Count;
2807 }
2808
2809 return Count;
2810}
2811
2812unsigned X86InstrInfo::insertBranch(MachineBasicBlock &MBB,
2813 MachineBasicBlock *TBB,
2814 MachineBasicBlock *FBB,
2815 ArrayRef<MachineOperand> Cond,
2816 const DebugLoc &DL,
2817 int *BytesAdded) const {
2818 // Shouldn't be a fall through.
2819 assert(TBB && "insertBranch must not be told to insert a fallthrough")((TBB && "insertBranch must not be told to insert a fallthrough"
) ? static_cast<void> (0) : __assert_fail ("TBB && \"insertBranch must not be told to insert a fallthrough\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/X86/X86InstrInfo.cpp"
, 2819, __PRETTY_FUNCTION__))
;
2820 assert((Cond.size() == 1 || Cond.size() == 0) &&(((Cond.size() == 1 || Cond.size() == 0) && "X86 branch conditions have one component!"
) ? static_cast<void> (0) : __assert_fail ("(Cond.size() == 1 || Cond.size() == 0) && \"X86 branch conditions have one component!\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/X86/X86InstrInfo.cpp"
, 2821, __PRETTY_FUNCTION__))
2821 "X86 branch conditions have one component!")(((Cond.size() == 1 || Cond.size() == 0) && "X86 branch conditions have one component!"
) ? static_cast<void> (0) : __assert_fail ("(Cond.size() == 1 || Cond.size() == 0) && \"X86 branch conditions have one component!\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/X86/X86InstrInfo.cpp"
, 2821, __PRETTY_FUNCTION__))
;
2822 assert(!BytesAdded && "code size not handled")((!BytesAdded && "code size not handled") ? static_cast
<void> (0) : __assert_fail ("!BytesAdded && \"code size not handled\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/X86/X86InstrInfo.cpp"
, 2822, __PRETTY_FUNCTION__))
;
2823
2824 if (Cond.empty()) {
2825 // Unconditional branch?
2826 assert(!FBB && "Unconditional branch with multiple successors!")((!FBB && "Unconditional branch with multiple successors!"
) ? static_cast<void> (0) : __assert_fail ("!FBB && \"Unconditional branch with multiple successors!\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/X86/X86InstrInfo.cpp"
, 2826, __PRETTY_FUNCTION__))
;
2827 BuildMI(&MBB, DL, get(X86::JMP_1)).addMBB(TBB);
2828 return 1;
2829 }
2830
2831 // If FBB is null, it is implied to be a fall-through block.
2832 bool FallThru = FBB == nullptr;
2833
2834 // Conditional branch.
2835 unsigned Count = 0;
2836 X86::CondCode CC = (X86::CondCode)Cond[0].getImm();
2837 switch (CC) {
2838 case X86::COND_NE_OR_P:
2839 // Synthesize NE_OR_P with two branches.
2840 BuildMI(&MBB, DL, get(X86::JNE_1)).addMBB(TBB);
2841 ++Count;
2842 BuildMI(&MBB, DL, get(X86::JP_1)).addMBB(TBB);
2843 ++Count;
2844 break;
2845 case X86::COND_E_AND_NP:
2846 // Use the next block of MBB as FBB if it is null.
2847 if (FBB == nullptr) {
2848 FBB = getFallThroughMBB(&MBB, TBB);
2849 assert(FBB && "MBB cannot be the last block in function when the false "((FBB && "MBB cannot be the last block in function when the false "
"body is a fall-through.") ? static_cast<void> (0) : __assert_fail
("FBB && \"MBB cannot be the last block in function when the false \" \"body is a fall-through.\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/X86/X86InstrInfo.cpp"
, 2850, __PRETTY_FUNCTION__))
2850 "body is a fall-through.")((FBB && "MBB cannot be the last block in function when the false "
"body is a fall-through.") ? static_cast<void> (0) : __assert_fail
("FBB && \"MBB cannot be the last block in function when the false \" \"body is a fall-through.\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/X86/X86InstrInfo.cpp"
, 2850, __PRETTY_FUNCTION__))
;
2851 }
2852 // Synthesize COND_E_AND_NP with two branches.
2853 BuildMI(&MBB, DL, get(X86::JNE_1)).addMBB(FBB);
2854 ++Count;
2855 BuildMI(&MBB, DL, get(X86::JNP_1)).addMBB(TBB);
2856 ++Count;
2857 break;
2858 default: {
2859 unsigned Opc = GetCondBranchFromCond(CC);
2860 BuildMI(&MBB, DL, get(Opc)).addMBB(TBB);
2861 ++Count;
2862 }
2863 }
2864 if (!FallThru) {
2865 // Two-way Conditional branch. Insert the second branch.
2866 BuildMI(&MBB, DL, get(X86::JMP_1)).addMBB(FBB);
2867 ++Count;
2868 }
2869 return Count;
2870}
2871
2872bool X86InstrInfo::
2873canInsertSelect(const MachineBasicBlock &MBB,
2874 ArrayRef<MachineOperand> Cond,
2875 unsigned TrueReg, unsigned FalseReg,
2876 int &CondCycles, int &TrueCycles, int &FalseCycles) const {
2877 // Not all subtargets have cmov instructions.
2878 if (!Subtarget.hasCMov())
2879 return false;
2880 if (Cond.size() != 1)
2881 return false;
2882 // We cannot do the composite conditions, at least not in SSA form.
2883 if ((X86::CondCode)Cond[0].getImm() > X86::COND_S)
2884 return false;
2885
2886 // Check register classes.
2887 const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
2888 const TargetRegisterClass *RC =
2889 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
2890 if (!RC)
2891 return false;
2892
2893 // We have cmov instructions for 16, 32, and 64 bit general purpose registers.
2894 if (X86::GR16RegClass.hasSubClassEq(RC) ||
2895 X86::GR32RegClass.hasSubClassEq(RC) ||
2896 X86::GR64RegClass.hasSubClassEq(RC)) {
2897 // This latency applies to Pentium M, Merom, Wolfdale, Nehalem, and Sandy
2898 // Bridge. Probably Ivy Bridge as well.
2899 CondCycles = 2;
2900 TrueCycles = 2;
2901 FalseCycles = 2;
2902 return true;
2903 }
2904
2905 // Can't do vectors.
2906 return false;
2907}
2908
2909void X86InstrInfo::insertSelect(MachineBasicBlock &MBB,
2910 MachineBasicBlock::iterator I,
2911 const DebugLoc &DL, unsigned DstReg,
2912 ArrayRef<MachineOperand> Cond, unsigned TrueReg,
2913 unsigned FalseReg) const {
2914 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
2915 const TargetRegisterInfo &TRI = *MRI.getTargetRegisterInfo();
2916 const TargetRegisterClass &RC = *MRI.getRegClass(DstReg);
2917 assert(Cond.size() == 1 && "Invalid Cond array")((Cond.size() == 1 && "Invalid Cond array") ? static_cast
<void> (0) : __assert_fail ("Cond.size() == 1 && \"Invalid Cond array\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/X86/X86InstrInfo.cpp"
, 2917, __PRETTY_FUNCTION__))
;
2918 unsigned Opc = getCMovFromCond((X86::CondCode)Cond[0].getImm(),
2919 TRI.getRegSizeInBits(RC) / 8,
2920 false /*HasMemoryOperand*/);
2921 BuildMI(MBB, I, DL, get(Opc), DstReg).addReg(FalseReg).addReg(TrueReg);
2922}
2923
2924/// Test if the given register is a physical h register.
2925static bool isHReg(unsigned Reg) {
2926 return X86::GR8_ABCD_HRegClass.contains(Reg);
2927}
2928
2929// Try and copy between VR128/VR64 and GR64 registers.
2930static unsigned CopyToFromAsymmetricReg(unsigned DestReg, unsigned SrcReg,
2931 const X86Subtarget &Subtarget) {
2932 bool HasAVX = Subtarget.hasAVX();
2933 bool HasAVX512 = Subtarget.hasAVX512();
2934
2935 // SrcReg(MaskReg) -> DestReg(GR64)
2936 // SrcReg(MaskReg) -> DestReg(GR32)
2937
2938 // All KMASK RegClasses hold the same k registers, can be tested against anyone.
2939 if (X86::VK16RegClass.contains(SrcReg)) {
2940 if (X86::GR64RegClass.contains(DestReg)) {
2941 assert(Subtarget.hasBWI())((Subtarget.hasBWI()) ? static_cast<void> (0) : __assert_fail
("Subtarget.hasBWI()", "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/X86/X86InstrInfo.cpp"
, 2941, __PRETTY_FUNCTION__))
;
2942 return X86::KMOVQrk;
2943 }
2944 if (X86::GR32RegClass.contains(DestReg))
2945 return Subtarget.hasBWI() ? X86::KMOVDrk : X86::KMOVWrk;
2946 }
2947
2948 // SrcReg(GR64) -> DestReg(MaskReg)
2949 // SrcReg(GR32) -> DestReg(MaskReg)
2950
2951 // All KMASK RegClasses hold the same k registers, can be tested against anyone.
2952 if (X86::VK16RegClass.contains(DestReg)) {
2953 if (X86::GR64RegClass.contains(SrcReg)) {
2954 assert(Subtarget.hasBWI())((Subtarget.hasBWI()) ? static_cast<void> (0) : __assert_fail
("Subtarget.hasBWI()", "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/X86/X86InstrInfo.cpp"
, 2954, __PRETTY_FUNCTION__))
;
2955 return X86::KMOVQkr;
2956 }
2957 if (X86::GR32RegClass.contains(SrcReg))
2958 return Subtarget.hasBWI() ? X86::KMOVDkr : X86::KMOVWkr;
2959 }
2960
2961
2962 // SrcReg(VR128) -> DestReg(GR64)
2963 // SrcReg(VR64) -> DestReg(GR64)
2964 // SrcReg(GR64) -> DestReg(VR128)
2965 // SrcReg(GR64) -> DestReg(VR64)
2966
2967 if (X86::GR64RegClass.contains(DestReg)) {
2968 if (X86::VR128XRegClass.contains(SrcReg))
2969 // Copy from a VR128 register to a GR64 register.
2970 return HasAVX512 ? X86::VMOVPQIto64Zrr :
2971 HasAVX ? X86::VMOVPQIto64rr :
2972 X86::MOVPQIto64rr;
2973 if (X86::VR64RegClass.contains(SrcReg))
2974 // Copy from a VR64 register to a GR64 register.
2975 return X86::MMX_MOVD64from64rr;
2976 } else if (X86::GR64RegClass.contains(SrcReg)) {
2977 // Copy from a GR64 register to a VR128 register.
2978 if (X86::VR128XRegClass.contains(DestReg))
2979 return HasAVX512 ? X86::VMOV64toPQIZrr :
2980 HasAVX ? X86::VMOV64toPQIrr :
2981 X86::MOV64toPQIrr;
2982 // Copy from a GR64 register to a VR64 register.
2983 if (X86::VR64RegClass.contains(DestReg))
2984 return X86::MMX_MOVD64to64rr;
2985 }
2986
2987 // SrcReg(FR32) -> DestReg(GR32)
2988 // SrcReg(GR32) -> DestReg(FR32)
2989
2990 if (X86::GR32RegClass.contains(DestReg) &&
2991 X86::FR32XRegClass.contains(SrcReg))
2992 // Copy from a FR32 register to a GR32 register.
2993 return HasAVX512 ? X86::VMOVSS2DIZrr :
2994 HasAVX ? X86::VMOVSS2DIrr :
2995 X86::MOVSS2DIrr;
2996
2997 if (X86::FR32XRegClass.contains(DestReg) &&
2998 X86::GR32RegClass.contains(SrcReg))
2999 // Copy from a GR32 register to a FR32 register.
3000 return HasAVX512 ? X86::VMOVDI2SSZrr :
3001 HasAVX ? X86::VMOVDI2SSrr :
3002 X86::MOVDI2SSrr;
3003 return 0;
3004}
3005
3006void X86InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
3007 MachineBasicBlock::iterator MI,
3008 const DebugLoc &DL, unsigned DestReg,
3009 unsigned SrcReg, bool KillSrc) const {
3010 // First deal with the normal symmetric copies.
3011 bool HasAVX = Subtarget.hasAVX();
3012 bool HasVLX = Subtarget.hasVLX();
3013 unsigned Opc = 0;
3014 if (X86::GR64RegClass.contains(DestReg, SrcReg))
3015 Opc = X86::MOV64rr;
3016 else if (X86::GR32RegClass.contains(DestReg, SrcReg))
3017 Opc = X86::MOV32rr;
3018 else if (X86::GR16RegClass.contains(DestReg, SrcReg))
3019 Opc = X86::MOV16rr;
3020 else if (X86::GR8RegClass.contains(DestReg, SrcReg)) {
3021 // Copying to or from a physical H register on x86-64 requires a NOREX
3022 // move. Otherwise use a normal move.
3023 if ((isHReg(DestReg) || isHReg(SrcReg)) &&
3024 Subtarget.is64Bit()) {
3025 Opc = X86::MOV8rr_NOREX;
3026 // Both operands must be encodable without an REX prefix.
3027 assert(X86::GR8_NOREXRegClass.contains(SrcReg, DestReg) &&((X86::GR8_NOREXRegClass.contains(SrcReg, DestReg) &&
"8-bit H register can not be copied outside GR8_NOREX") ? static_cast
<void> (0) : __assert_fail ("X86::GR8_NOREXRegClass.contains(SrcReg, DestReg) && \"8-bit H register can not be copied outside GR8_NOREX\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/X86/X86InstrInfo.cpp"
, 3028, __PRETTY_FUNCTION__))
3028 "8-bit H register can not be copied outside GR8_NOREX")((X86::GR8_NOREXRegClass.contains(SrcReg, DestReg) &&
"8-bit H register can not be copied outside GR8_NOREX") ? static_cast
<void> (0) : __assert_fail ("X86::GR8_NOREXRegClass.contains(SrcReg, DestReg) && \"8-bit H register can not be copied outside GR8_NOREX\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/X86/X86InstrInfo.cpp"
, 3028, __PRETTY_FUNCTION__))
;
3029 } else
3030 Opc = X86::MOV8rr;
3031 }
3032 else if (X86::VR64RegClass.contains(DestReg, SrcReg))
3033 Opc = X86::MMX_MOVQ64rr;
3034 else if (X86::VR128XRegClass.contains(DestReg, SrcReg)) {
3035 if (HasVLX)
3036 Opc = X86::VMOVAPSZ128rr;
3037 else if (X86::VR128RegClass.contains(DestReg, SrcReg))
3038 Opc = HasAVX ? X86::VMOVAPSrr : X86::MOVAPSrr;
3039 else {
3040 // If this an extended register and we don't have VLX we need to use a
3041 // 512-bit move.
3042 Opc = X86::VMOVAPSZrr;
3043 const TargetRegisterInfo *TRI = &getRegisterInfo();
3044 DestReg = TRI->getMatchingSuperReg(DestReg, X86::sub_xmm,
3045 &X86::VR512RegClass);
3046 SrcReg = TRI->getMatchingSuperReg(SrcReg, X86::sub_xmm,
3047 &X86::VR512RegClass);
3048 }
3049 } else if (X86::VR256XRegClass.contains(DestReg, SrcReg)) {
3050 if (HasVLX)
3051 Opc = X86::VMOVAPSZ256rr;
3052 else if (X86::VR256RegClass.contains(DestReg, SrcReg))
3053 Opc = X86::VMOVAPSYrr;
3054 else {
3055 // If this an extended register and we don't have VLX we need to use a
3056 // 512-bit move.
3057 Opc = X86::VMOVAPSZrr;
3058 const TargetRegisterInfo *TRI = &getRegisterInfo();
3059 DestReg = TRI->getMatchingSuperReg(DestReg, X86::sub_ymm,
3060 &X86::VR512RegClass);
3061 SrcReg = TRI->getMatchingSuperReg(SrcReg, X86::sub_ymm,
3062 &X86::VR512RegClass);
3063 }
3064 } else if (X86::VR512RegClass.contains(DestReg, SrcReg))
3065 Opc = X86::VMOVAPSZrr;
3066 // All KMASK RegClasses hold the same k registers, can be tested against anyone.
3067 else if (X86::VK16RegClass.contains(DestReg, SrcReg))
3068 Opc = Subtarget.hasBWI() ? X86::KMOVQkk : X86::KMOVWkk;
3069 if (!Opc)
3070 Opc = CopyToFromAsymmetricReg(DestReg, SrcReg, Subtarget);
3071
3072 if (Opc) {
3073 BuildMI(MBB, MI, DL, get(Opc), DestReg)
3074 .addReg(SrcReg, getKillRegState(KillSrc));
3075 return;
3076 }
3077
3078 if (SrcReg == X86::EFLAGS || DestReg == X86::EFLAGS) {
3079 // FIXME: We use a fatal error here because historically LLVM has tried
3080 // lower some of these physreg copies and we want to ensure we get
3081 // reasonable bug reports if someone encounters a case no other testing
3082 // found. This path should be removed after the LLVM 7 release.
3083 report_fatal_error("Unable to copy EFLAGS physical register!");
3084 }
3085
3086 LLVM_DEBUG(dbgs() << "Cannot copy " << RI.getName(SrcReg) << " to "do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("x86-instr-info")) { dbgs() << "Cannot copy " <<
RI.getName(SrcReg) << " to " << RI.getName(DestReg
) << '\n'; } } while (false)
3087 << RI.getName(DestReg) << '\n')do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("x86-instr-info")) { dbgs() << "Cannot copy " <<
RI.getName(SrcReg) << " to " << RI.getName(DestReg
) << '\n'; } } while (false)
;
3088 report_fatal_error("Cannot emit physreg copy instruction");
3089}
3090
3091bool X86InstrInfo::isCopyInstrImpl(const MachineInstr &MI,
3092 const MachineOperand *&Src,
3093 const MachineOperand *&Dest) const {
3094 if (MI.isMoveReg()) {
3095 Dest = &MI.getOperand(0);
3096 Src = &MI.getOperand(1);
3097 return true;
3098 }
3099 return false;
3100}
3101
3102static unsigned getLoadStoreRegOpcode(unsigned Reg,
3103 const TargetRegisterClass *RC,
3104 bool isStackAligned,
3105 const X86Subtarget &STI,
3106 bool load) {
3107 bool HasAVX = STI.hasAVX();
3108 bool HasAVX512 = STI.hasAVX512();
3109 bool HasVLX = STI.hasVLX();
3110
3111 switch (STI.getRegisterInfo()->getSpillSize(*RC)) {
3112 default:
3113 llvm_unreachable("Unknown spill size")::llvm::llvm_unreachable_internal("Unknown spill size", "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/X86/X86InstrInfo.cpp"
, 3113)
;
3114 case 1:
3115 assert(X86::GR8RegClass.hasSubClassEq(RC) && "Unknown 1-byte regclass")((X86::GR8RegClass.hasSubClassEq(RC) && "Unknown 1-byte regclass"
) ? static_cast<void> (0) : __assert_fail ("X86::GR8RegClass.hasSubClassEq(RC) && \"Unknown 1-byte regclass\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/X86/X86InstrInfo.cpp"
, 3115, __PRETTY_FUNCTION__))
;
3116 if (STI.is64Bit())
3117 // Copying to or from a physical H register on x86-64 requires a NOREX
3118 // move. Otherwise use a normal move.
3119 if (isHReg(Reg) || X86::GR8_ABCD_HRegClass.hasSubClassEq(RC))
3120 return load ? X86::MOV8rm_NOREX : X86::MOV8mr_NOREX;
3121 return load ? X86::MOV8rm : X86::MOV8mr;
3122 case 2:
3123 if (X86::VK16RegClass.hasSubClassEq(RC))
3124 return load ? X86::KMOVWkm : X86::KMOVWmk;
3125 assert(X86::GR16RegClass.hasSubClassEq(RC) && "Unknown 2-byte regclass")((X86::GR16RegClass.hasSubClassEq(RC) && "Unknown 2-byte regclass"
) ? static_cast<void> (0) : __assert_fail ("X86::GR16RegClass.hasSubClassEq(RC) && \"Unknown 2-byte regclass\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/X86/X86InstrInfo.cpp"
, 3125, __PRETTY_FUNCTION__))
;
3126 return load ? X86::MOV16rm : X86::MOV16mr;
3127 case 4:
3128 if (X86::GR32RegClass.hasSubClassEq(RC))
3129 return load ? X86::MOV32rm : X86::MOV32mr;
3130 if (X86::FR32XRegClass.hasSubClassEq(RC))
3131 return load ?
3132 (HasAVX512 ? X86::VMOVSSZrm : HasAVX ? X86::VMOVSSrm : X86::MOVSSrm) :
3133 (HasAVX512 ? X86::VMOVSSZmr : HasAVX ? X86::VMOVSSmr : X86::MOVSSmr);
3134 if (X86::RFP32RegClass.hasSubClassEq(RC))
3135 return load ? X86::LD_Fp32m : X86::ST_Fp32m;
3136 if (X86::VK32RegClass.hasSubClassEq(RC)) {
3137 assert(STI.hasBWI() && "KMOVD requires BWI")((STI.hasBWI() && "KMOVD requires BWI") ? static_cast
<void> (0) : __assert_fail ("STI.hasBWI() && \"KMOVD requires BWI\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/X86/X86InstrInfo.cpp"
, 3137, __PRETTY_FUNCTION__))
;
3138 return load ? X86::KMOVDkm : X86::KMOVDmk;
3139 }
3140 llvm_unreachable("Unknown 4-byte regclass")::llvm::llvm_unreachable_internal("Unknown 4-byte regclass", "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/X86/X86InstrInfo.cpp"
, 3140)
;
3141 case 8:
3142 if (X86::GR64RegClass.hasSubClassEq(RC))
3143 return load ? X86::MOV64rm : X86::MOV64mr;
3144 if (X86::FR64XRegClass.hasSubClassEq(RC))
3145 return load ?
3146 (HasAVX512 ? X86::VMOVSDZrm : HasAVX ? X86::VMOVSDrm : X86::MOVSDrm) :
3147 (HasAVX512 ? X86::VMOVSDZmr : HasAVX ? X86::VMOVSDmr : X86::MOVSDmr);
3148 if (X86::VR64RegClass.hasSubClassEq(RC))
3149 return load ? X86::MMX_MOVQ64rm : X86::MMX_MOVQ64mr;
3150 if (X86::RFP64RegClass.hasSubClassEq(RC))
3151 return load ? X86::LD_Fp64m : X86::ST_Fp64m;
3152 if (X86::VK64RegClass.hasSubClassEq(RC)) {
3153 assert(STI.hasBWI() && "KMOVQ requires BWI")((STI.hasBWI() && "KMOVQ requires BWI") ? static_cast
<void> (0) : __assert_fail ("STI.hasBWI() && \"KMOVQ requires BWI\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/X86/X86InstrInfo.cpp"
, 3153, __PRETTY_FUNCTION__))
;
3154 return load ? X86::KMOVQkm : X86::KMOVQmk;
3155 }
3156 llvm_unreachable("Unknown 8-byte regclass")::llvm::llvm_unreachable_internal("Unknown 8-byte regclass", "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/X86/X86InstrInfo.cpp"
, 3156)
;
3157 case 10:
3158 assert(X86::RFP80RegClass.hasSubClassEq(RC) && "Unknown 10-byte regclass")((X86::RFP80RegClass.hasSubClassEq(RC) && "Unknown 10-byte regclass"
) ? static_cast<void> (0) : __assert_fail ("X86::RFP80RegClass.hasSubClassEq(RC) && \"Unknown 10-byte regclass\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/X86/X86InstrInfo.cpp"
, 3158, __PRETTY_FUNCTION__))
;
3159 return load ? X86::LD_Fp80m : X86::ST_FpP80m;
3160 case 16: {
3161 if (X86::VR128XRegClass.hasSubClassEq(RC)) {
3162 // If stack is realigned we can use aligned stores.
3163 if (isStackAligned)
3164 return load ?
3165 (HasVLX ? X86::VMOVAPSZ128rm :
3166 HasAVX512 ? X86::VMOVAPSZ128rm_NOVLX :
3167 HasAVX ? X86::VMOVAPSrm :
3168 X86::MOVAPSrm):
3169 (HasVLX ? X86::VMOVAPSZ128mr :
3170 HasAVX512 ? X86::VMOVAPSZ128mr_NOVLX :
3171 HasAVX ? X86::VMOVAPSmr :
3172 X86::MOVAPSmr);
3173 else
3174 return load ?
3175 (HasVLX ? X86::VMOVUPSZ128rm :
3176 HasAVX512 ? X86::VMOVUPSZ128rm_NOVLX :
3177 HasAVX ? X86::VMOVUPSrm :
3178 X86::MOVUPSrm):
3179 (HasVLX ? X86::VMOVUPSZ128mr :
3180 HasAVX512 ? X86::VMOVUPSZ128mr_NOVLX :
3181 HasAVX ? X86::VMOVUPSmr :
3182 X86::MOVUPSmr);
3183 }
3184 if (X86::BNDRRegClass.hasSubClassEq(RC)) {
3185 if (STI.is64Bit())
3186 return load ? X86::BNDMOV64rm : X86::BNDMOV64mr;
3187 else
3188 return load ? X86::BNDMOV32rm : X86::BNDMOV32mr;
3189 }
3190 llvm_unreachable("Unknown 16-byte regclass")::llvm::llvm_unreachable_internal("Unknown 16-byte regclass",
"/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/X86/X86InstrInfo.cpp"
, 3190)
;
3191 }
3192 case 32:
3193 assert(X86::VR256XRegClass.hasSubClassEq(RC) && "Unknown 32-byte regclass")((X86::VR256XRegClass.hasSubClassEq(RC) && "Unknown 32-byte regclass"
) ? static_cast<void> (0) : __assert_fail ("X86::VR256XRegClass.hasSubClassEq(RC) && \"Unknown 32-byte regclass\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/X86/X86InstrInfo.cpp"
, 3193, __PRETTY_FUNCTION__))
;
3194 // If stack is realigned we can use aligned stores.
3195 if (isStackAligned)
3196 return load ?
3197 (HasVLX ? X86::VMOVAPSZ256rm :
3198 HasAVX512 ? X86::VMOVAPSZ256rm_NOVLX :
3199 X86::VMOVAPSYrm) :
3200 (HasVLX ? X86::VMOVAPSZ256mr :
3201 HasAVX512 ? X86::VMOVAPSZ256mr_NOVLX :
3202 X86::VMOVAPSYmr);
3203 else
3204 return load ?
3205 (HasVLX ? X86::VMOVUPSZ256rm :
3206 HasAVX512 ? X86::VMOVUPSZ256rm_NOVLX :
3207 X86::VMOVUPSYrm) :
3208 (HasVLX ? X86::VMOVUPSZ256mr :
3209 HasAVX512 ? X86::VMOVUPSZ256mr_NOVLX :
3210 X86::VMOVUPSYmr);
3211 case 64:
3212 assert(X86::VR512RegClass.hasSubClassEq(RC) && "Unknown 64-byte regclass")((X86::VR512RegClass.hasSubClassEq(RC) && "Unknown 64-byte regclass"
) ? static_cast<void> (0) : __assert_fail ("X86::VR512RegClass.hasSubClassEq(RC) && \"Unknown 64-byte regclass\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/X86/X86InstrInfo.cpp"
, 3212, __PRETTY_FUNCTION__))
;
3213 assert(STI.hasAVX512() && "Using 512-bit register requires AVX512")((STI.hasAVX512() && "Using 512-bit register requires AVX512"
) ? static_cast<void> (0) : __assert_fail ("STI.hasAVX512() && \"Using 512-bit register requires AVX512\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/X86/X86InstrInfo.cpp"
, 3213, __PRETTY_FUNCTION__))
;
3214 if (isStackAligned)
3215 return load ? X86::VMOVAPSZrm : X86::VMOVAPSZmr;
3216 else
3217 return load ? X86::VMOVUPSZrm : X86::VMOVUPSZmr;
3218 }
3219}
3220
3221bool X86InstrInfo::getMemOperandWithOffset(
3222 MachineInstr &MemOp, MachineOperand *&BaseOp, int64_t &Offset,
3223 const TargetRegisterInfo *TRI) const {
3224 const MCInstrDesc &Desc = MemOp.getDesc();
3225 int MemRefBegin = X86II::getMemoryOperandNo(Desc.TSFlags);
3226 if (MemRefBegin < 0)
3227 return false;
3228
3229 MemRefBegin += X86II::getOperandBias(Desc);
3230
3231 BaseOp = &MemOp.getOperand(MemRefBegin + X86::AddrBaseReg);
3232 if (!BaseOp->isReg()) // Can be an MO_FrameIndex
3233 return false;
3234
3235 if (MemOp.getOperand(MemRefBegin + X86::AddrScaleAmt).getImm() != 1)
3236 return false;
3237
3238 if (MemOp.getOperand(MemRefBegin + X86::AddrIndexReg).getReg() !=
3239 X86::NoRegister)
3240 return false;
3241
3242 const MachineOperand &DispMO = MemOp.getOperand(MemRefBegin + X86::AddrDisp);
3243
3244 // Displacement can be symbolic
3245 if (!DispMO.isImm())
3246 return false;
3247
3248 Offset = DispMO.getImm();
3249
3250 assert(BaseOp->isReg() && "getMemOperandWithOffset only supports base "((BaseOp->isReg() && "getMemOperandWithOffset only supports base "
"operands of type register.") ? static_cast<void> (0) :
__assert_fail ("BaseOp->isReg() && \"getMemOperandWithOffset only supports base \" \"operands of type register.\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/X86/X86InstrInfo.cpp"
, 3251, __PRETTY_FUNCTION__))
3251 "operands of type register.")((BaseOp->isReg() && "getMemOperandWithOffset only supports base "
"operands of type register.") ? static_cast<void> (0) :
__assert_fail ("BaseOp->isReg() && \"getMemOperandWithOffset only supports base \" \"operands of type register.\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/X86/X86InstrInfo.cpp"
, 3251, __PRETTY_FUNCTION__))
;
3252 return true;
3253}
3254
3255static unsigned getStoreRegOpcode(unsigned SrcReg,
3256 const TargetRegisterClass *RC,
3257 bool isStackAligned,
3258 const X86Subtarget &STI) {
3259 return getLoadStoreRegOpcode(SrcReg, RC, isStackAligned, STI, false);
3260}
3261
3262
3263static unsigned getLoadRegOpcode(unsigned DestReg,
3264 const TargetRegisterClass *RC,
3265 bool isStackAligned,
3266 const X86Subtarget &STI) {
3267 return getLoadStoreRegOpcode(DestReg, RC, isStackAligned, STI, true);
3268}
3269
3270void X86InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
3271 MachineBasicBlock::iterator MI,
3272 unsigned SrcReg, bool isKill, int FrameIdx,
3273 const TargetRegisterClass *RC,
3274 const TargetRegisterInfo *TRI) const {
3275 const MachineFunction &MF = *MBB.getParent();
3276 assert(MF.getFrameInfo().getObjectSize(FrameIdx) >= TRI->getSpillSize(*RC) &&((MF.getFrameInfo().getObjectSize(FrameIdx) >= TRI->getSpillSize
(*RC) && "Stack slot too small for store") ? static_cast
<void> (0) : __assert_fail ("MF.getFrameInfo().getObjectSize(FrameIdx) >= TRI->getSpillSize(*RC) && \"Stack slot too small for store\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/X86/X86InstrInfo.cpp"
, 3277, __PRETTY_FUNCTION__))
3277 "Stack slot too small for store")((MF.getFrameInfo().getObjectSize(FrameIdx) >= TRI->getSpillSize
(*RC) && "Stack slot too small for store") ? static_cast
<void> (0) : __assert_fail ("MF.getFrameInfo().getObjectSize(FrameIdx) >= TRI->getSpillSize(*RC) && \"Stack slot too small for store\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/X86/X86InstrInfo.cpp"
, 3277, __PRETTY_FUNCTION__))
;
3278 unsigned Alignment = std::max<uint32_t>(TRI->getSpillSize(*RC), 16);
3279 bool isAligned =
3280 (Subtarget.getFrameLowering()->getStackAlignment() >= Alignment) ||
3281 RI.canRealignStack(MF);
3282 unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, Subtarget);
3283 addFrameReference(BuildMI(MBB, MI, DebugLoc(), get(Opc)), FrameIdx)
3284 .addReg(SrcReg, getKillRegState(isKill));
3285}
3286
3287void X86InstrInfo::storeRegToAddr(
3288 MachineFunction &MF, unsigned SrcReg, bool isKill,
3289 SmallVectorImpl<MachineOperand> &Addr, const TargetRegisterClass *RC,
3290 ArrayRef<MachineMemOperand *> MMOs,
3291 SmallVectorImpl<MachineInstr *> &NewMIs) const {
3292 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
3293 unsigned Alignment = std::max<uint32_t>(TRI.getSpillSize(*RC), 16);
3294 bool isAligned = !MMOs.empty() && MMOs.front()->getAlignment() >= Alignment;
3295 unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, Subtarget);
3296 DebugLoc DL;
3297 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc));
3298 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
3299 MIB.add(Addr[i]);
3300 MIB.addReg(SrcReg, getKillRegState(isKill));
3301 MIB.setMemRefs(MMOs);
3302 NewMIs.push_back(MIB);
3303}
3304
3305
3306void X86InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
3307 MachineBasicBlock::iterator MI,
3308 unsigned DestReg, int FrameIdx,
3309 const TargetRegisterClass *RC,
3310 const TargetRegisterInfo *TRI) const {
3311 const MachineFunction &MF = *MBB.getParent();
3312 unsigned Alignment = std::max<uint32_t>(TRI->getSpillSize(*RC), 16);
3313 bool isAligned =
3314 (Subtarget.getFrameLowering()->getStackAlignment() >= Alignment) ||
3315 RI.canRealignStack(MF);
3316 unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, Subtarget);
3317 addFrameReference(BuildMI(MBB, MI, DebugLoc(), get(Opc), DestReg), FrameIdx);
3318}
3319
3320void X86InstrInfo::loadRegFromAddr(
3321 MachineFunction &MF, unsigned DestReg,
3322 SmallVectorImpl<MachineOperand> &Addr, const TargetRegisterClass *RC,
3323 ArrayRef<MachineMemOperand *> MMOs,
3324 SmallVectorImpl<MachineInstr *> &NewMIs) const {
3325 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
3326 unsigned Alignment = std::max<uint32_t>(TRI.getSpillSize(*RC), 16);
3327 bool isAligned = !MMOs.empty() && MMOs.front()->getAlignment() >= Alignment;
3328 unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, Subtarget);
3329 DebugLoc DL;
3330 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg);
3331 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
3332 MIB.add(Addr[i]);
3333 MIB.setMemRefs(MMOs);
3334 NewMIs.push_back(MIB);
3335}
3336
3337bool X86InstrInfo::analyzeCompare(const MachineInstr &MI, unsigned &SrcReg,
3338 unsigned &SrcReg2, int &CmpMask,
3339 int &CmpValue) const {
3340 switch (MI.getOpcode()) {
3341 default: break;
3342 case X86::CMP64ri32:
3343 case X86::CMP64ri8:
3344 case X86::CMP32ri:
3345 case X86::CMP32ri8:
3346 case X86::CMP16ri:
3347 case X86::CMP16ri8:
3348 case X86::CMP8ri:
3349 SrcReg = MI.getOperand(0).getReg();
3350 SrcReg2 = 0;
3351 if (MI.getOperand(1).isImm()) {
3352 CmpMask = ~0;
3353 CmpValue = MI.getOperand(1).getImm();
3354 } else {
3355 CmpMask = CmpValue = 0;
3356 }
3357 return true;
3358 // A SUB can be used to perform comparison.
3359 case X86::SUB64rm:
3360 case X86::SUB32rm:
3361 case X86::SUB16rm:
3362 case X86::SUB8rm:
3363 SrcReg = MI.getOperand(1).getReg();
3364 SrcReg2 = 0;
3365 CmpMask = 0;
3366 CmpValue = 0;
3367 return true;
3368 case X86::SUB64rr:
3369 case X86::SUB32rr:
3370 case X86::SUB16rr:
3371 case X86::SUB8rr:
3372 SrcReg = MI.getOperand(1).getReg();
3373 SrcReg2 = MI.getOperand(2).getReg();
3374 CmpMask = 0;
3375 CmpValue = 0;
3376 return true;
3377 case X86::SUB64ri32:
3378 case X86::SUB64ri8:
3379 case X86::SUB32ri:
3380 case X86::SUB32ri8:
3381 case X86::SUB16ri:
3382 case X86::SUB16ri8:
3383 case X86::SUB8ri:
3384 SrcReg = MI.getOperand(1).getReg();
3385 SrcReg2 = 0;
3386 if (MI.getOperand(2).isImm()) {
3387 CmpMask = ~0;
3388 CmpValue = MI.getOperand(2).getImm();
3389 } else {
3390 CmpMask = CmpValue = 0;
3391 }
3392 return true;
3393 case X86::CMP64rr:
3394 case X86::CMP32rr:
3395 case X86::CMP16rr:
3396 case X86::CMP8rr:
3397 SrcReg = MI.getOperand(0).getReg();
3398 SrcReg2 = MI.getOperand(1).getReg();
3399 CmpMask = 0;
3400 CmpValue = 0;
3401 return true;
3402 case X86::TEST8rr:
3403 case X86::TEST16rr:
3404 case X86::TEST32rr:
3405 case X86::TEST64rr:
3406 SrcReg = MI.getOperand(0).getReg();
3407 if (MI.getOperand(1).getReg() != SrcReg)
3408 return false;
3409 // Compare against zero.
3410 SrcReg2 = 0;
3411 CmpMask = ~0;
3412 CmpValue = 0;
3413 return true;
3414 }
3415 return false;
3416}
3417
3418/// Check whether the first instruction, whose only
3419/// purpose is to update flags, can be made redundant.
3420/// CMPrr can be made redundant by SUBrr if the operands are the same.
3421/// This function can be extended later on.
3422/// SrcReg, SrcRegs: register operands for FlagI.
3423/// ImmValue: immediate for FlagI if it takes an immediate.
3424inline static bool isRedundantFlagInstr(const MachineInstr &FlagI,
3425 unsigned SrcReg, unsigned SrcReg2,
3426 int ImmMask, int ImmValue,
3427 const MachineInstr &OI) {
3428 if (((FlagI.getOpcode() == X86::CMP64rr && OI.getOpcode() == X86::SUB64rr) ||
3429 (FlagI.getOpcode() == X86::CMP32rr && OI.getOpcode() == X86::SUB32rr) ||
3430 (FlagI.getOpcode() == X86::CMP16rr && OI.getOpcode() == X86::SUB16rr) ||
3431 (FlagI.getOpcode() == X86::CMP8rr && OI.getOpcode() == X86::SUB8rr)) &&
3432 ((OI.getOperand(1).getReg() == SrcReg &&
3433 OI.getOperand(2).getReg() == SrcReg2) ||
3434 (OI.getOperand(1).getReg() == SrcReg2 &&
3435 OI.getOperand(2).getReg() == SrcReg)))
3436 return true;
3437
3438 if (ImmMask != 0 &&
3439 ((FlagI.getOpcode() == X86::CMP64ri32 &&
3440 OI.getOpcode() == X86::SUB64ri32) ||
3441 (FlagI.getOpcode() == X86::CMP64ri8 &&
3442 OI.getOpcode() == X86::SUB64ri8) ||
3443 (FlagI.getOpcode() == X86::CMP32ri && OI.getOpcode() == X86::SUB32ri) ||
3444 (FlagI.getOpcode() == X86::CMP32ri8 &&
3445 OI.getOpcode() == X86::SUB32ri8) ||
3446 (FlagI.getOpcode() == X86::CMP16ri && OI.getOpcode() == X86::SUB16ri) ||
3447 (FlagI.getOpcode() == X86::CMP16ri8 &&
3448 OI.getOpcode() == X86::SUB16ri8) ||
3449 (FlagI.getOpcode() == X86::CMP8ri && OI.getOpcode() == X86::SUB8ri)) &&
3450 OI.getOperand(1).getReg() == SrcReg &&
3451 OI.getOperand(2).getImm() == ImmValue)
3452 return true;
3453 return false;
3454}
3455
3456/// Check whether the definition can be converted
3457/// to remove a comparison against zero.
3458inline static bool isDefConvertible(const MachineInstr &MI, bool &NoSignFlag) {
3459 NoSignFlag = false;
3460
3461 switch (MI.getOpcode()) {
3462 default: return false;
3463
3464 // The shift instructions only modify ZF if their shift count is non-zero.
3465 // N.B.: The processor truncates the shift count depending on the encoding.
3466 case X86::SAR8ri: case X86::SAR16ri: case X86::SAR32ri:case X86::SAR64ri:
3467 case X86::SHR8ri: case X86::SHR16ri: case X86::SHR32ri:case X86::SHR64ri:
3468 return getTruncatedShiftCount(MI, 2) != 0;
3469
3470 // Some left shift instructions can be turned into LEA instructions but only
3471 // if their flags aren't used. Avoid transforming such instructions.
3472 case X86::SHL8ri: case X86::SHL16ri: case X86::SHL32ri:case X86::SHL64ri:{
3473 unsigned ShAmt = getTruncatedShiftCount(MI, 2);
3474 if (isTruncatedShiftCountForLEA(ShAmt)) return false;
3475 return ShAmt != 0;
3476 }
3477
3478 case X86::SHRD16rri8:case X86::SHRD32rri8:case X86::SHRD64rri8:
3479 case X86::SHLD16rri8:case X86::SHLD32rri8:case X86::SHLD64rri8:
3480 return getTruncatedShiftCount(MI, 3) != 0;
3481
3482 case X86::SUB64ri32: case X86::SUB64ri8: case X86::SUB32ri:
3483 case X86::SUB32ri8: case X86::SUB16ri: case X86::SUB16ri8:
3484 case X86::SUB8ri: case X86::SUB64rr: case X86::SUB32rr:
3485 case X86::SUB16rr: case X86::SUB8rr: case X86::SUB64rm:
3486 case X86::SUB32rm: case X86::SUB16rm: case X86::SUB8rm:
3487 case X86::DEC64r: case X86::DEC32r: case X86::DEC16r: case X86::DEC8r:
3488 case X86::ADD64ri32: case X86::ADD64ri8: case X86::ADD32ri:
3489 case X86::ADD32ri8: case X86::ADD16ri: case X86::ADD16ri8:
3490 case X86::ADD8ri: case X86::ADD64rr: case X86::ADD32rr:
3491 case X86::ADD16rr: case X86::ADD8rr: case X86::ADD64rm:
3492 case X86::ADD32rm: case X86::ADD16rm: case X86::ADD8rm:
3493 case X86::INC64r: case X86::INC32r: case X86::INC16r: case X86::INC8r:
3494 case X86::AND64ri32: case X86::AND64ri8: case X86::AND32ri:
3495 case X86::AND32ri8: case X86::AND16ri: case X86::AND16ri8:
3496 case X86::AND8ri: case X86::AND64rr: case X86::AND32rr:
3497 case X86::AND16rr: case X86::AND8rr: case X86::AND64rm:
3498 case X86::AND32rm: case X86::AND16rm: case X86::AND8rm:
3499 case X86::XOR64ri32: case X86::XOR64ri8: case X86::XOR32ri:
3500 case X86::XOR32ri8: case X86::XOR16ri: case X86::XOR16ri8:
3501 case X86::XOR8ri: case X86::XOR64rr: case X86::XOR32rr:
3502 case X86::XOR16rr: case X86::XOR8rr: case X86::XOR64rm:
3503 case X86::XOR32rm: case X86::XOR16rm: case X86::XOR8rm:
3504 case X86::OR64ri32: case X86::OR64ri8: case X86::OR32ri:
3505 case X86::OR32ri8: case X86::OR16ri: case X86::OR16ri8:
3506 case X86::OR8ri: case X86::OR64rr: case X86::OR32rr:
3507 case X86::OR16rr: case X86::OR8rr: case X86::OR64rm:
3508 case X86::OR32rm: case X86::OR16rm: case X86::OR8rm:
3509 case X86::ADC64ri32: case X86::ADC64ri8: case X86::ADC32ri:
3510 case X86::ADC32ri8: case X86::ADC16ri: case X86::ADC16ri8:
3511 case X86::ADC8ri: case X86::ADC64rr: case X86::ADC32rr:
3512 case X86::ADC16rr: case X86::ADC8rr: case X86::ADC64rm:
3513 case X86::ADC32rm: case X86::ADC16rm: case X86::ADC8rm:
3514 case X86::SBB64ri32: case X86::SBB64ri8: case X86::SBB32ri:
3515 case X86::SBB32ri8: case X86::SBB16ri: case X86::SBB16ri8:
3516 case X86::SBB8ri: case X86::SBB64rr: case X86::SBB32rr:
3517 case X86::SBB16rr: case X86::SBB8rr: case X86::SBB64rm:
3518 case X86::SBB32rm: case X86::SBB16rm: case X86::SBB8rm:
3519 case X86::NEG8r: case X86::NEG16r: case X86::NEG32r: case X86::NEG64r:
3520 case X86::SAR8r1: case X86::SAR16r1: case X86::SAR32r1:case X86::SAR64r1:
3521 case X86::SHR8r1: case X86::SHR16r1: case X86::SHR32r1:case X86::SHR64r1:
3522 case X86::SHL8r1: case X86::SHL16r1: case X86::SHL32r1:case X86::SHL64r1:
3523 case X86::ANDN32rr: case X86::ANDN32rm:
3524 case X86::ANDN64rr: case X86::ANDN64rm:
3525 case X86::BLSI32rr: case X86::BLSI32rm:
3526 case X86::BLSI64rr: case X86::BLSI64rm:
3527 case X86::BLSMSK32rr:case X86::BLSMSK32rm:
3528 case X86::BLSMSK64rr:case X86::BLSMSK64rm:
3529 case X86::BLSR32rr: case X86::BLSR32rm:
3530 case X86::BLSR64rr: case X86::BLSR64rm:
3531 case X86::BZHI32rr: case X86::BZHI32rm:
3532 case X86::BZHI64rr: case X86::BZHI64rm:
3533 case X86::LZCNT16rr: case X86::LZCNT16rm:
3534 case X86::LZCNT32rr: case X86::LZCNT32rm:
3535 case X86::LZCNT64rr: case X86::LZCNT64rm:
3536 case X86::POPCNT16rr:case X86::POPCNT16rm:
3537 case X86::POPCNT32rr:case X86::POPCNT32rm:
3538 case X86::POPCNT64rr:case X86::POPCNT64rm:
3539 case X86::TZCNT16rr: case X86::TZCNT16rm:
3540 case X86::TZCNT32rr: case X86::TZCNT32rm:
3541 case X86::TZCNT64rr: case X86::TZCNT64rm:
3542 case X86::BLCFILL32rr: case X86::BLCFILL32rm:
3543 case X86::BLCFILL64rr: case X86::BLCFILL64rm:
3544 case X86::BLCI32rr: case X86::BLCI32rm:
3545 case X86::BLCI64rr: case X86::BLCI64rm:
3546 case X86::BLCIC32rr: case X86::BLCIC32rm:
3547 case X86::BLCIC64rr: case X86::BLCIC64rm:
3548 case X86::BLCMSK32rr: case X86::BLCMSK32rm:
3549 case X86::BLCMSK64rr: case X86::BLCMSK64rm:
3550 case X86::BLCS32rr: case X86::BLCS32rm:
3551 case X86::BLCS64rr: case X86::BLCS64rm:
3552 case X86::BLSFILL32rr: case X86::BLSFILL32rm:
3553 case X86::BLSFILL64rr: case X86::BLSFILL64rm:
3554 case X86::BLSIC32rr: case X86::BLSIC32rm:
3555 case X86::BLSIC64rr: case X86::BLSIC64rm:
3556 case X86::T1MSKC32rr: case X86::T1MSKC32rm:
3557 case X86::T1MSKC64rr: case X86::T1MSKC64rm:
3558 case X86::TZMSK32rr: case X86::TZMSK32rm:
3559 case X86::TZMSK64rr: case X86::TZMSK64rm:
3560 return true;
3561 case X86::BEXTR32rr: case X86::BEXTR64rr:
3562 case X86::BEXTR32rm: case X86::BEXTR64rm:
3563 case X86::BEXTRI32ri: case X86::BEXTRI32mi:
3564 case X86::BEXTRI64ri: case X86::BEXTRI64mi:
3565 // BEXTR doesn't update the sign flag so we can't use it.
3566 NoSignFlag = true;
3567 return true;
3568 }
3569}
3570
3571/// Check whether the use can be converted to remove a comparison against zero.
3572static X86::CondCode isUseDefConvertible(const MachineInstr &MI) {
3573 switch (MI.getOpcode()) {
3574 default: return X86::COND_INVALID;
3575 case X86::LZCNT16rr: case X86::LZCNT16rm:
3576 case X86::LZCNT32rr: case X86::LZCNT32rm:
3577 case X86::LZCNT64rr: case X86::LZCNT64rm:
3578 return X86::COND_B;
3579 case X86::POPCNT16rr:case X86::POPCNT16rm:
3580 case X86::POPCNT32rr:case X86::POPCNT32rm:
3581 case X86::POPCNT64rr:case X86::POPCNT64rm:
3582 return X86::COND_E;
3583 case X86::TZCNT16rr: case X86::TZCNT16rm:
3584 case X86::TZCNT32rr: case X86::TZCNT32rm:
3585 case X86::TZCNT64rr: case X86::TZCNT64rm:
3586 return X86::COND_B;
3587 case X86::BSF16rr: case X86::BSF16rm:
3588 case X86::BSF32rr: case X86::BSF32rm:
3589 case X86::BSF64rr: case X86::BSF64rm:
3590 case X86::BSR16rr: case X86::BSR16rm:
3591 case X86::BSR32rr: case X86::BSR32rm:
3592 case X86::BSR64rr: case X86::BSR64rm:
3593 return X86::COND_E;
3594 }
3595}
3596
3597/// Check if there exists an earlier instruction that
3598/// operates on the same source operands and sets flags in the same way as
3599/// Compare; remove Compare if possible.
3600bool X86InstrInfo::optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg,
3601 unsigned SrcReg2, int CmpMask,
3602 int CmpValue,
3603 const MachineRegisterInfo *MRI) const {
3604 // Check whether we can replace SUB with CMP.
3605 unsigned NewOpcode = 0;
3606 switch (CmpInstr.getOpcode()) {
1
Control jumps to the 'default' case at line 3607
3607 default: break;
2
Execution continues on line 3654
3608 case X86::SUB64ri32:
3609 case X86::SUB64ri8:
3610 case X86::SUB32ri:
3611 case X86::SUB32ri8:
3612 case X86::SUB16ri:
3613 case X86::SUB16ri8:
3614 case X86::SUB8ri:
3615 case X86::SUB64rm:
3616 case X86::SUB32rm:
3617 case X86::SUB16rm:
3618 case X86::SUB8rm:
3619 case X86::SUB64rr:
3620 case X86::SUB32rr:
3621 case X86::SUB16rr:
3622 case X86::SUB8rr: {
3623 if (!MRI->use_nodbg_empty(CmpInstr.getOperand(0).getReg()))
3624 return false;
3625 // There is no use of the destination register, we can replace SUB with CMP.
3626 switch (CmpInstr.getOpcode()) {
3627 default: llvm_unreachable("Unreachable!")::llvm::llvm_unreachable_internal("Unreachable!", "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/X86/X86InstrInfo.cpp"
, 3627)
;
3628 case X86::SUB64rm: NewOpcode = X86::CMP64rm; break;
3629 case X86::SUB32rm: NewOpcode = X86::CMP32rm; break;
3630 case X86::SUB16rm: NewOpcode = X86::CMP16rm; break;
3631 case X86::SUB8rm: NewOpcode = X86::CMP8rm; break;
3632 case X86::SUB64rr: NewOpcode = X86::CMP64rr; break;
3633 case X86::SUB32rr: NewOpcode = X86::CMP32rr; break;
3634 case X86::SUB16rr: NewOpcode = X86::CMP16rr; break;
3635 case X86::SUB8rr: NewOpcode = X86::CMP8rr; break;
3636 case X86::SUB64ri32: NewOpcode = X86::CMP64ri32; break;
3637 case X86::SUB64ri8: NewOpcode = X86::CMP64ri8; break;
3638 case X86::SUB32ri: NewOpcode = X86::CMP32ri; break;
3639 case X86::SUB32ri8: NewOpcode = X86::CMP32ri8; break;
3640 case X86::SUB16ri: NewOpcode = X86::CMP16ri; break;
3641 case X86::SUB16ri8: NewOpcode = X86::CMP16ri8; break;
3642 case X86::SUB8ri: NewOpcode = X86::CMP8ri; break;
3643 }
3644 CmpInstr.setDesc(get(NewOpcode));
3645 CmpInstr.RemoveOperand(0);
3646 // Fall through to optimize Cmp if Cmp is CMPrr or CMPri.
3647 if (NewOpcode == X86::CMP64rm || NewOpcode == X86::CMP32rm ||
3648 NewOpcode == X86::CMP16rm || NewOpcode == X86::CMP8rm)
3649 return false;
3650 }
3651 }
3652
3653 // Get the unique definition of SrcReg.
3654 MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg);
3655 if (!MI) return false;
3
Assuming 'MI' is non-null
4
Taking false branch
3656
3657 // CmpInstr is the first instruction of the BB.
3658 MachineBasicBlock::iterator I = CmpInstr, Def = MI;
3659
3660 // If we are comparing against zero, check whether we can use MI to update
3661 // EFLAGS. If MI is not in the same BB as CmpInstr, do not optimize.
3662 bool IsCmpZero = (CmpMask != 0 && CmpValue == 0);
5
Assuming 'CmpMask' is not equal to 0
6
Assuming 'CmpValue' is equal to 0
3663 if (IsCmpZero && MI->getParent() != CmpInstr.getParent())
7
Assuming the condition is false
8
Taking false branch
3664 return false;
3665
3666 // If we have a use of the source register between the def and our compare
3667 // instruction we can eliminate the compare iff the use sets EFLAGS in the
3668 // right way.
3669 bool ShouldUpdateCC = false;
3670 bool NoSignFlag = false;
3671 X86::CondCode NewCC = X86::COND_INVALID;
3672 if (IsCmpZero && !isDefConvertible(*MI, NoSignFlag)) {
9
Assuming the condition is false
10
Taking false branch
3673 // Scan forward from the use until we hit the use we're looking for or the
3674 // compare instruction.
3675 for (MachineBasicBlock::iterator J = MI;; ++J) {
3676 // Do we have a convertible instruction?
3677 NewCC = isUseDefConvertible(*J);
3678 if (NewCC != X86::COND_INVALID && J->getOperand(1).isReg() &&
3679 J->getOperand(1).getReg() == SrcReg) {
3680 assert(J->definesRegister(X86::EFLAGS) && "Must be an EFLAGS def!")((J->definesRegister(X86::EFLAGS) && "Must be an EFLAGS def!"
) ? static_cast<void> (0) : __assert_fail ("J->definesRegister(X86::EFLAGS) && \"Must be an EFLAGS def!\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/X86/X86InstrInfo.cpp"
, 3680, __PRETTY_FUNCTION__))
;
3681 ShouldUpdateCC = true; // Update CC later on.
3682 // This is not a def of SrcReg, but still a def of EFLAGS. Keep going
3683 // with the new def.
3684 Def = J;
3685 MI = &*Def;
3686 break;
3687 }
3688
3689 if (J == I)
3690 return false;
3691 }
3692 }
3693
3694 // We are searching for an earlier instruction that can make CmpInstr
3695 // redundant and that instruction will be saved in Sub.
3696 MachineInstr *Sub = nullptr;
11
'Sub' initialized to a null pointer value
3697 const TargetRegisterInfo *TRI = &getRegisterInfo();
3698
3699 // We iterate backward, starting from the instruction before CmpInstr and
3700 // stop when reaching the definition of a source register or done with the BB.
3701 // RI points to the instruction before CmpInstr.
3702 // If the definition is in this basic block, RE points to the definition;
3703 // otherwise, RE is the rend of the basic block.
3704 MachineBasicBlock::reverse_iterator
3705 RI = ++I.getReverse(),
3706 RE = CmpInstr.getParent() == MI->getParent()
12
'?' condition is true
3707 ? Def.getReverse() /* points to MI */
3708 : CmpInstr.getParent()->rend();
3709 MachineInstr *Movr0Inst = nullptr;
3710 for (; RI != RE; ++RI) {
13
Loop condition is false. Execution continues on line 3738
3711 MachineInstr &Instr = *RI;
3712 // Check whether CmpInstr can be made redundant by the current instruction.
3713 if (!IsCmpZero && isRedundantFlagInstr(CmpInstr, SrcReg, SrcReg2, CmpMask,
3714 CmpValue, Instr)) {
3715 Sub = &Instr;
3716 break;
3717 }
3718
3719 if (Instr.modifiesRegister(X86::EFLAGS, TRI) ||
3720 Instr.readsRegister(X86::EFLAGS, TRI)) {
3721 // This instruction modifies or uses EFLAGS.
3722
3723 // MOV32r0 etc. are implemented with xor which clobbers condition code.
3724 // They are safe to move up, if the definition to EFLAGS is dead and
3725 // earlier instructions do not read or write EFLAGS.
3726 if (!Movr0Inst && Instr.getOpcode() == X86::MOV32r0 &&
3727 Instr.registerDefIsDead(X86::EFLAGS, TRI)) {
3728 Movr0Inst = &Instr;
3729 continue;
3730 }
3731
3732 // We can't remove CmpInstr.
3733 return false;
3734 }
3735 }
3736
3737 // Return false if no candidates exist.
3738 if (!IsCmpZero && !Sub)
3739 return false;
3740
3741 bool IsSwapped = (SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 &&
14
Assuming 'SrcReg2' is not equal to 0
15
Called C++ object pointer is null
3742 Sub->getOperand(2).getReg() == SrcReg);
3743
3744 // Scan forward from the instruction after CmpInstr for uses of EFLAGS.
3745 // It is safe to remove CmpInstr if EFLAGS is redefined or killed.
3746 // If we are done with the basic block, we need to check whether EFLAGS is
3747 // live-out.
3748 bool IsSafe = false;
3749 SmallVector<std::pair<MachineInstr*, unsigned /*NewOpc*/>, 4> OpsToUpdate;
3750 MachineBasicBlock::iterator E = CmpInstr.getParent()->end();
3751 for (++I; I != E; ++I) {
3752 const MachineInstr &Instr = *I;
3753 bool ModifyEFLAGS = Instr.modifiesRegister(X86::EFLAGS, TRI);
3754 bool UseEFLAGS = Instr.readsRegister(X86::EFLAGS, TRI);
3755 // We should check the usage if this instruction uses and updates EFLAGS.
3756 if (!UseEFLAGS && ModifyEFLAGS) {
3757 // It is safe to remove CmpInstr if EFLAGS is updated again.
3758 IsSafe = true;
3759 break;
3760 }
3761 if (!UseEFLAGS && !ModifyEFLAGS)
3762 continue;
3763
3764 // EFLAGS is used by this instruction.
3765 X86::CondCode OldCC = X86::COND_INVALID;
3766 bool OpcIsSET = false;
3767 if (IsCmpZero || IsSwapped) {
3768 // We decode the condition code from opcode.
3769 if (Instr.isBranch())
3770 OldCC = X86::getCondFromBranchOpc(Instr.getOpcode());
3771 else {
3772 OldCC = X86::getCondFromSETOpc(Instr.getOpcode());
3773 if (OldCC != X86::COND_INVALID)
3774 OpcIsSET = true;
3775 else
3776 OldCC = X86::getCondFromCMovOpc(Instr.getOpcode());
3777 }
3778 if (OldCC == X86::COND_INVALID) return false;
3779 }
3780 X86::CondCode ReplacementCC = X86::COND_INVALID;
3781 if (IsCmpZero) {
3782 switch (OldCC) {
3783 default: break;
3784 case X86::COND_A: case X86::COND_AE:
3785 case X86::COND_B: case X86::COND_BE:
3786 case X86::COND_G: case X86::COND_GE:
3787 case X86::COND_L: case X86::COND_LE:
3788 case X86::COND_O: case X86::COND_NO:
3789 // CF and OF are used, we can't perform this optimization.
3790 return false;
3791 case X86::COND_S: case X86::COND_NS:
3792 // If SF is used, but the instruction doesn't update the SF, then we
3793 // can't do the optimization.
3794 if (NoSignFlag)
3795 return false;
3796 break;
3797 }
3798
3799 // If we're updating the condition code check if we have to reverse the
3800 // condition.
3801 if (ShouldUpdateCC)
3802 switch (OldCC) {
3803 default:
3804 return false;
3805 case X86::COND_E:
3806 ReplacementCC = NewCC;
3807 break;
3808 case X86::COND_NE:
3809 ReplacementCC = GetOppositeBranchCondition(NewCC);
3810 break;
3811 }
3812 } else if (IsSwapped) {
3813 // If we have SUB(r1, r2) and CMP(r2, r1), the condition code needs
3814 // to be changed from r2 > r1 to r1 < r2, from r2 < r1 to r1 > r2, etc.
3815 // We swap the condition code and synthesize the new opcode.
3816 ReplacementCC = getSwappedCondition(OldCC);
3817 if (ReplacementCC == X86::COND_INVALID) return false;
3818 }
3819
3820 if ((ShouldUpdateCC || IsSwapped) && ReplacementCC != OldCC) {
3821 // Synthesize the new opcode.
3822 bool HasMemoryOperand = Instr.hasOneMemOperand();
3823 unsigned NewOpc;
3824 if (Instr.isBranch())
3825 NewOpc = GetCondBranchFromCond(ReplacementCC);
3826 else if(OpcIsSET)
3827 NewOpc = getSETFromCond(ReplacementCC, HasMemoryOperand);
3828 else {
3829 unsigned DstReg = Instr.getOperand(0).getReg();
3830 const TargetRegisterClass *DstRC = MRI->getRegClass(DstReg);
3831 NewOpc = getCMovFromCond(ReplacementCC, TRI->getRegSizeInBits(*DstRC)/8,
3832 HasMemoryOperand);
3833 }
3834
3835 // Push the MachineInstr to OpsToUpdate.
3836 // If it is safe to remove CmpInstr, the condition code of these
3837 // instructions will be modified.
3838 OpsToUpdate.push_back(std::make_pair(&*I, NewOpc));
3839 }
3840 if (ModifyEFLAGS || Instr.killsRegister(X86::EFLAGS, TRI)) {
3841 // It is safe to remove CmpInstr if EFLAGS is updated again or killed.
3842 IsSafe = true;
3843 break;
3844 }
3845 }
3846
3847 // If EFLAGS is not killed nor re-defined, we should check whether it is
3848 // live-out. If it is live-out, do not optimize.
3849 if ((IsCmpZero || IsSwapped) && !IsSafe) {
3850 MachineBasicBlock *MBB = CmpInstr.getParent();
3851 for (MachineBasicBlock *Successor : MBB->successors())
3852 if (Successor->isLiveIn(X86::EFLAGS))
3853 return false;
3854 }
3855
3856 // The instruction to be updated is either Sub or MI.
3857 Sub = IsCmpZero ? MI : Sub;
3858 // Move Movr0Inst to the appropriate place before Sub.
3859 if (Movr0Inst) {
3860 // Look backwards until we find a def that doesn't use the current EFLAGS.
3861 Def = Sub;
3862 MachineBasicBlock::reverse_iterator InsertI = Def.getReverse(),
3863 InsertE = Sub->getParent()->rend();
3864 for (; InsertI != InsertE; ++InsertI) {
3865 MachineInstr *Instr = &*InsertI;
3866 if (!Instr->readsRegister(X86::EFLAGS, TRI) &&
3867 Instr->modifiesRegister(X86::EFLAGS, TRI)) {
3868 Sub->getParent()->remove(Movr0Inst);
3869 Instr->getParent()->insert(MachineBasicBlock::iterator(Instr),
3870 Movr0Inst);
3871 break;
3872 }
3873 }
3874 if (InsertI == InsertE)
3875 return false;
3876 }
3877
3878 // Make sure Sub instruction defines EFLAGS and mark the def live.
3879 unsigned i = 0, e = Sub->getNumOperands();
3880 for (; i != e; ++i) {
3881 MachineOperand &MO = Sub->getOperand(i);
3882 if (MO.isReg() && MO.isDef() && MO.getReg() == X86::EFLAGS) {
3883 MO.setIsDead(false);
3884 break;
3885 }
3886 }
3887 assert(i != e && "Unable to locate a def EFLAGS operand")((i != e && "Unable to locate a def EFLAGS operand") ?
static_cast<void> (0) : __assert_fail ("i != e && \"Unable to locate a def EFLAGS operand\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/X86/X86InstrInfo.cpp"
, 3887, __PRETTY_FUNCTION__))
;
3888
3889 CmpInstr.eraseFromParent();
3890
3891 // Modify the condition code of instructions in OpsToUpdate.
3892 for (auto &Op : OpsToUpdate)
3893 Op.first->setDesc(get(Op.second));
3894 return true;
3895}
3896
3897/// Try to remove the load by folding it to a register
3898/// operand at the use. We fold the load instructions if load defines a virtual
3899/// register, the virtual register is used once in the same BB, and the
3900/// instructions in-between do not load or store, and have no side effects.
3901MachineInstr *X86InstrInfo::optimizeLoadInstr(MachineInstr &MI,
3902 const MachineRegisterInfo *MRI,
3903 unsigned &FoldAsLoadDefReg,
3904 MachineInstr *&DefMI) const {
3905 // Check whether we can move DefMI here.
3906 DefMI = MRI->getVRegDef(FoldAsLoadDefReg);
3907 assert(DefMI)((DefMI) ? static_cast<void> (0) : __assert_fail ("DefMI"
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/X86/X86InstrInfo.cpp"
, 3907, __PRETTY_FUNCTION__))
;
3908 bool SawStore = false;
3909 if (!DefMI->isSafeToMove(nullptr, SawStore))
3910 return nullptr;
3911
3912 // Collect information about virtual register operands of MI.
3913 SmallVector<unsigned, 1> SrcOperandIds;
3914 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
3915 MachineOperand &MO = MI.getOperand(i);
3916 if (!MO.isReg())
3917 continue;
3918 unsigned Reg = MO.getReg();
3919 if (Reg != FoldAsLoadDefReg)
3920 continue;
3921 // Do not fold if we have a subreg use or a def.
3922 if (MO.getSubReg() || MO.isDef())
3923 return nullptr;
3924 SrcOperandIds.push_back(i);
3925 }
3926 if (SrcOperandIds.empty())
3927 return nullptr;
3928
3929 // Check whether we can fold the def into SrcOperandId.
3930 if (MachineInstr *FoldMI = foldMemoryOperand(MI, SrcOperandIds, *DefMI)) {
3931 FoldAsLoadDefReg = 0;
3932 return FoldMI;
3933 }
3934
3935 return nullptr;
3936}
3937
3938/// Expand a single-def pseudo instruction to a two-addr
3939/// instruction with two undef reads of the register being defined.
3940/// This is used for mapping:
3941/// %xmm4 = V_SET0
3942/// to:
3943/// %xmm4 = PXORrr undef %xmm4, undef %xmm4
3944///
3945static bool Expand2AddrUndef(MachineInstrBuilder &MIB,
3946 const MCInstrDesc &Desc) {
3947 assert(Desc.getNumOperands() == 3 && "Expected two-addr instruction.")((Desc.getNumOperands() == 3 && "Expected two-addr instruction."
) ? static_cast<void> (0) : __assert_fail ("Desc.getNumOperands() == 3 && \"Expected two-addr instruction.\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/X86/X86InstrInfo.cpp"
, 3947, __PRETTY_FUNCTION__))
;
3948 unsigned Reg = MIB->getOperand(0).getReg();
3949 MIB->setDesc(Desc);
3950
3951 // MachineInstr::addOperand() will insert explicit operands before any
3952 // implicit operands.
3953 MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef);
3954 // But we don't trust that.
3955 assert(MIB->getOperand(1).getReg() == Reg &&((MIB->getOperand(1).getReg() == Reg && MIB->getOperand
(2).getReg() == Reg && "Misplaced operand") ? static_cast
<void> (0) : __assert_fail ("MIB->getOperand(1).getReg() == Reg && MIB->getOperand(2).getReg() == Reg && \"Misplaced operand\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/X86/X86InstrInfo.cpp"
, 3956, __PRETTY_FUNCTION__))
3956 MIB->getOperand(2).getReg() == Reg && "Misplaced operand")((MIB->getOperand(1).getReg() == Reg && MIB->getOperand
(2).getReg() == Reg && "Misplaced operand") ? static_cast
<void> (0) : __assert_fail ("MIB->getOperand(1).getReg() == Reg && MIB->getOperand(2).getReg() == Reg && \"Misplaced operand\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/X86/X86InstrInfo.cpp"
, 3956, __PRETTY_FUNCTION__))
;
3957 return true;
3958}
3959
3960/// Expand a single-def pseudo instruction to a two-addr
3961/// instruction with two %k0 reads.
3962/// This is used for mapping:
3963/// %k4 = K_SET1
3964/// to:
3965/// %k4 = KXNORrr %k0, %k0
3966static bool Expand2AddrKreg(MachineInstrBuilder &MIB,
3967 const MCInstrDesc &Desc, unsigned Reg) {
3968 assert(Desc.getNumOperands() == 3 && "Expected two-addr instruction.")((Desc.getNumOperands() == 3 && "Expected two-addr instruction."
) ? static_cast<void> (0) : __assert_fail ("Desc.getNumOperands() == 3 && \"Expected two-addr instruction.\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/X86/X86InstrInfo.cpp"
, 3968, __PRETTY_FUNCTION__))
;
3969 MIB->setDesc(Desc);
3970 MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef);
3971 return true;
3972}
3973
3974static bool expandMOV32r1(MachineInstrBuilder &MIB, const TargetInstrInfo &TII,
3975 bool MinusOne) {
3976 MachineBasicBlock &MBB = *MIB->getParent();
3977 DebugLoc DL = MIB->getDebugLoc();
3978 unsigned Reg = MIB->getOperand(0).getReg();
3979
3980 // Insert the XOR.
3981 BuildMI(MBB, MIB.getInstr(), DL, TII.get(X86::XOR32rr), Reg)
3982 .addReg(Reg, RegState::Undef)
3983 .addReg(Reg, RegState::Undef);
3984
3985 // Turn the pseudo into an INC or DEC.
3986 MIB->setDesc(TII.get(MinusOne ? X86::DEC32r : X86::INC32r));
3987 MIB.addReg(Reg);
3988
3989 return true;
3990}
3991
3992static bool ExpandMOVImmSExti8(MachineInstrBuilder &MIB,
3993 const TargetInstrInfo &TII,
3994 const X86Subtarget &Subtarget) {
3995 MachineBasicBlock &MBB = *MIB->getParent();
3996 DebugLoc DL = MIB->getDebugLoc();
3997 int64_t Imm = MIB->getOperand(1).getImm();
3998 assert(Imm != 0 && "Using push/pop for 0 is not efficient.")((Imm != 0 && "Using push/pop for 0 is not efficient."
) ? static_cast<void> (0) : __assert_fail ("Imm != 0 && \"Using push/pop for 0 is not efficient.\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/X86/X86InstrInfo.cpp"
, 3998, __PRETTY_FUNCTION__))
;
3999 MachineBasicBlock::iterator I = MIB.getInstr();
4000
4001 int StackAdjustment;
4002
4003 if (Subtarget.is64Bit()) {
4004 assert(MIB->getOpcode() == X86::MOV64ImmSExti8 ||((MIB->getOpcode() == X86::MOV64ImmSExti8 || MIB->getOpcode
() == X86::MOV32ImmSExti8) ? static_cast<void> (0) : __assert_fail
("MIB->getOpcode() == X86::MOV64ImmSExti8 || MIB->getOpcode() == X86::MOV32ImmSExti8"
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/X86/X86InstrInfo.cpp"
, 4005, __PRETTY_FUNCTION__))
4005 MIB->getOpcode() == X86::MOV32ImmSExti8)((MIB->getOpcode() == X86::MOV64ImmSExti8 || MIB->getOpcode
() == X86::MOV32ImmSExti8) ? static_cast<void> (0) : __assert_fail
("MIB->getOpcode() == X86::MOV64ImmSExti8 || MIB->getOpcode() == X86::MOV32ImmSExti8"
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/X86/X86InstrInfo.cpp"
, 4005, __PRETTY_FUNCTION__))
;
4006
4007 // Can't use push/pop lowering if the function might write to the red zone.
4008 X86MachineFunctionInfo *X86FI =
4009 MBB.getParent()->getInfo<X86MachineFunctionInfo>();
4010 if (X86FI->getUsesRedZone()) {
4011 MIB->setDesc(TII.get(MIB->getOpcode() ==
4012 X86::MOV32ImmSExti8 ? X86::MOV32ri : X86::MOV64ri));
4013 return true;
4014 }
4015
4016 // 64-bit mode doesn't have 32-bit push/pop, so use 64-bit operations and
4017 // widen the register if necessary.
4018 StackAdjustment = 8;
4019 BuildMI(MBB, I, DL, TII.get(X86::PUSH64i8)).addImm(Imm);
4020 MIB->setDesc(TII.get(X86::POP64r));
4021 MIB->getOperand(0)
4022 .setReg(getX86SubSuperRegister(MIB->getOperand(0).getReg(), 64));
4023 } else {
4024 assert(MIB->getOpcode() == X86::MOV32ImmSExti8)((MIB->getOpcode() == X86::MOV32ImmSExti8) ? static_cast<
void> (0) : __assert_fail ("MIB->getOpcode() == X86::MOV32ImmSExti8"
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/X86/X86InstrInfo.cpp"
, 4024, __PRETTY_FUNCTION__))
;
4025 StackAdjustment = 4;
4026 BuildMI(MBB, I, DL, TII.get(X86::PUSH32i8)).addImm(Imm);
4027 MIB->setDesc(TII.get(X86::POP32r));
4028 }
4029
4030 // Build CFI if necessary.
4031 MachineFunction &MF = *MBB.getParent();
4032 const X86FrameLowering *TFL = Subtarget.getFrameLowering();
4033 bool IsWin64Prologue = MF.getTarget().getMCAsmInfo()->usesWindowsCFI();
4034 bool NeedsDwarfCFI =
4035 !IsWin64Prologue &&
4036 (MF.getMMI().hasDebugInfo() || MF.getFunction().needsUnwindTableEntry());
4037 bool EmitCFI = !TFL->hasFP(MF) && NeedsDwarfCFI;
4038 if (EmitCFI) {
4039 TFL->BuildCFI(MBB, I, DL,
4040 MCCFIInstruction::createAdjustCfaOffset(nullptr, StackAdjustment));
4041 TFL->BuildCFI(MBB, std::next(I), DL,
4042 MCCFIInstruction::createAdjustCfaOffset(nullptr, -StackAdjustment));
4043 }
4044
4045 return true;
4046}
4047
4048// LoadStackGuard has so far only been implemented for 64-bit MachO. Different
4049// code sequence is needed for other targets.
4050static void expandLoadStackGuard(MachineInstrBuilder &MIB,
4051 const TargetInstrInfo &TII) {
4052 MachineBasicBlock &MBB = *MIB->getParent();
4053 DebugLoc DL = MIB->getDebugLoc();
4054 unsigned Reg = MIB->getOperand(0).getReg();
4055 const GlobalValue *GV =
4056 cast<GlobalValue>((*MIB->memoperands_begin())->getValue());
4057 auto Flags = MachineMemOperand::MOLoad |
4058 MachineMemOperand::MODereferenceable |
4059 MachineMemOperand::MOInvariant;
4060 MachineMemOperand *MMO = MBB.getParent()->getMachineMemOperand(
4061 MachinePointerInfo::getGOT(*MBB.getParent()), Flags, 8, 8);
4062 MachineBasicBlock::iterator I = MIB.getInstr();
4063
4064 BuildMI(MBB, I, DL, TII.get(X86::MOV64rm), Reg).addReg(X86::RIP).addImm(1)
4065 .addReg(0).addGlobalAddress(GV, 0, X86II::MO_GOTPCREL).addReg(0)
4066 .addMemOperand(MMO);
4067 MIB->setDebugLoc(DL);
4068 MIB->setDesc(TII.get(X86::MOV64rm));
4069 MIB.addReg(Reg, RegState::Kill).addImm(1).addReg(0).addImm(0).addReg(0);
4070}
4071
4072static bool expandXorFP(MachineInstrBuilder &MIB, const TargetInstrInfo &TII) {
4073 MachineBasicBlock &MBB = *MIB->getParent();
4074 MachineFunction &MF = *MBB.getParent();
4075 const X86Subtarget &Subtarget = MF.getSubtarget<X86Subtarget>();
4076 const X86RegisterInfo *TRI = Subtarget.getRegisterInfo();
4077 unsigned XorOp =
4078 MIB->getOpcode() == X86::XOR64_FP ? X86::XOR64rr : X86::XOR32rr;
4079 MIB->setDesc(TII.get(XorOp));
4080 MIB.addReg(TRI->getFrameRegister(MF), RegState::Undef);
4081 return true;
4082}
4083
4084// This is used to handle spills for 128/256-bit registers when we have AVX512,
4085// but not VLX. If it uses an extended register we need to use an instruction
4086// that loads the lower 128/256-bit, but is available with only AVX512F.
4087static bool expandNOVLXLoad(MachineInstrBuilder &MIB,
4088 const TargetRegisterInfo *TRI,
4089 const MCInstrDesc &LoadDesc,
4090 const MCInstrDesc &BroadcastDesc,
4091 unsigned SubIdx) {
4092 unsigned DestReg = MIB->getOperand(0).getReg();
4093 // Check if DestReg is XMM16-31 or YMM16-31.
4094 if (TRI->getEncodingValue(DestReg) < 16) {
4095 // We can use a normal VEX encoded load.
4096 MIB->setDesc(LoadDesc);
4097 } else {
4098 // Use a 128/256-bit VBROADCAST instruction.
4099 MIB->setDesc(BroadcastDesc);
4100 // Change the destination to a 512-bit register.
4101 DestReg = TRI->getMatchingSuperReg(DestReg, SubIdx, &X86::VR512RegClass);
4102 MIB->getOperand(0).setReg(DestReg);
4103 }
4104 return true;
4105}
4106
4107// This is used to handle spills for 128/256-bit registers when we have AVX512,
4108// but not VLX. If it uses an extended register we need to use an instruction
4109// that stores the lower 128/256-bit, but is available with only AVX512F.
4110static bool expandNOVLXStore(MachineInstrBuilder &MIB,
4111 const TargetRegisterInfo *TRI,
4112 const MCInstrDesc &StoreDesc,
4113 const MCInstrDesc &ExtractDesc,
4114 unsigned SubIdx) {
4115 unsigned SrcReg = MIB->getOperand(X86::AddrNumOperands).getReg();
4116 // Check if DestReg is XMM16-31 or YMM16-31.
4117 if (TRI->getEncodingValue(SrcReg) < 16) {
4118 // We can use a normal VEX encoded store.
4119 MIB->setDesc(StoreDesc);
4120 } else {
4121 // Use a VEXTRACTF instruction.
4122 MIB->setDesc(ExtractDesc);
4123 // Change the destination to a 512-bit register.
4124 SrcReg = TRI->getMatchingSuperReg(SrcReg, SubIdx, &X86::VR512RegClass);
4125 MIB->getOperand(X86::AddrNumOperands).setReg(SrcReg);
4126 MIB.addImm(0x0); // Append immediate to extract from the lower bits.
4127 }
4128
4129 return true;
4130}
4131bool X86InstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
4132 bool HasAVX = Subtarget.hasAVX();
4133 MachineInstrBuilder MIB(*MI.getParent()->getParent(), MI);
4134 switch (MI.getOpcode()) {
4135 case X86::MOV32r0:
4136 return Expand2AddrUndef(MIB, get(X86::XOR32rr));
4137 case X86::MOV32r1:
4138 return expandMOV32r1(MIB, *this, /*MinusOne=*/ false);
4139 case X86::MOV32r_1:
4140 return expandMOV32r1(MIB, *this, /*MinusOne=*/ true);
4141 case X86::MOV32ImmSExti8:
4142 case X86::MOV64ImmSExti8:
4143 return ExpandMOVImmSExti8(MIB, *this, Subtarget);
4144 case X86::SETB_C8r:
4145 return Expand2AddrUndef(MIB, get(X86::SBB8rr));
4146 case X86::SETB_C16r:
4147 return Expand2AddrUndef(MIB, get(X86::SBB16rr));
4148 case X86::SETB_C32r:
4149 return Expand2AddrUndef(MIB, get(X86::SBB32rr));
4150 case X86::SETB_C64r:
4151 return Expand2AddrUndef(MIB, get(X86::SBB64rr));
4152 case X86::MMX_SET0:
4153 return Expand2AddrUndef(MIB, get(X86::MMX_PXORirr));
4154 case X86::V_SET0:
4155 case X86::FsFLD0SS:
4156 case X86::FsFLD0SD:
4157 return Expand2AddrUndef(MIB, get(HasAVX ? X86::VXORPSrr : X86::XORPSrr));
4158 case X86::AVX_SET0: {
4159 assert(HasAVX && "AVX not supported")((HasAVX && "AVX not supported") ? static_cast<void
> (0) : __assert_fail ("HasAVX && \"AVX not supported\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/X86/X86InstrInfo.cpp"
, 4159, __PRETTY_FUNCTION__))
;
4160 const TargetRegisterInfo *TRI = &getRegisterInfo();
4161 unsigned SrcReg = MIB->getOperand(0).getReg();
4162 unsigned XReg = TRI->getSubReg(SrcReg, X86::sub_xmm);
4163 MIB->getOperand(0).setReg(XReg);
4164 Expand2AddrUndef(MIB, get(X86::VXORPSrr));
4165 MIB.addReg(SrcReg, RegState::ImplicitDefine);
4166 return true;
4167 }
4168 case X86::AVX512_128_SET0:
4169 case X86::AVX512_FsFLD0SS:
4170 case X86::AVX512_FsFLD0SD: {
4171 bool HasVLX = Subtarget.hasVLX();
4172 unsigned SrcReg = MIB->getOperand(0).getReg();
4173 const TargetRegisterInfo *TRI = &getRegisterInfo();
4174 if (HasVLX || TRI->getEncodingValue(SrcReg) < 16)
4175 return Expand2AddrUndef(MIB,
4176 get(HasVLX ? X86::VPXORDZ128rr : X86::VXORPSrr));
4177 // Extended register without VLX. Use a larger XOR.
4178 SrcReg =
4179 TRI->getMatchingSuperReg(SrcReg, X86::sub_xmm, &X86::VR512RegClass);
4180 MIB->getOperand(0).setReg(SrcReg);
4181 return Expand2AddrUndef(MIB, get(X86::VPXORDZrr));
4182 }
4183 case X86::AVX512_256_SET0:
4184 case X86::AVX512_512_SET0: {
4185 bool HasVLX = Subtarget.hasVLX();
4186 unsigned SrcReg = MIB->getOperand(0).getReg();
4187 const TargetRegisterInfo *TRI = &getRegisterInfo();
4188 if (HasVLX || TRI->getEncodingValue(SrcReg) < 16) {
4189 unsigned XReg = TRI->getSubReg(SrcReg, X86::sub_xmm);
4190 MIB->getOperand(0).setReg(XReg);
4191 Expand2AddrUndef(MIB,
4192 get(HasVLX ? X86::VPXORDZ128rr : X86::VXORPSrr));
4193 MIB.addReg(SrcReg, RegState::ImplicitDefine);
4194 return true;
4195 }
4196 return Expand2AddrUndef(MIB, get(X86::VPXORDZrr));
4197 }
4198 case X86::V_SETALLONES:
4199 return Expand2AddrUndef(MIB, get(HasAVX ? X86::VPCMPEQDrr : X86::PCMPEQDrr));
4200 case X86::AVX2_SETALLONES:
4201 return Expand2AddrUndef(MIB, get(X86::VPCMPEQDYrr));
4202 case X86::AVX1_SETALLONES: {
4203 unsigned Reg = MIB->getOperand(0).getReg();
4204 // VCMPPSYrri with an immediate 0xf should produce VCMPTRUEPS.
4205 MIB->setDesc(get(X86::VCMPPSYrri));
4206 MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef).addImm(0xf);
4207 return true;
4208 }
4209 case X86::AVX512_512_SETALLONES: {
4210 unsigned Reg = MIB->getOperand(0).getReg();
4211 MIB->setDesc(get(X86::VPTERNLOGDZrri));
4212 // VPTERNLOGD needs 3 register inputs and an immediate.
4213 // 0xff will return 1s for any input.
4214 MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef)
4215 .addReg(Reg, RegState::Undef).addImm(0xff);
4216 return true;
4217 }
4218 case X86::AVX512_512_SEXT_MASK_32:
4219 case X86::AVX512_512_SEXT_MASK_64: {
4220 unsigned Reg = MIB->getOperand(0).getReg();
4221 unsigned MaskReg = MIB->getOperand(1).getReg();
4222 unsigned MaskState = getRegState(MIB->getOperand(1));
4223 unsigned Opc = (MI.getOpcode() == X86::AVX512_512_SEXT_MASK_64) ?
4224 X86::VPTERNLOGQZrrikz : X86::VPTERNLOGDZrrikz;
4225 MI.RemoveOperand(1);
4226 MIB->setDesc(get(Opc));
4227 // VPTERNLOG needs 3 register inputs and an immediate.
4228 // 0xff will return 1s for any input.
4229 MIB.addReg(Reg, RegState::Undef).addReg(MaskReg, MaskState)
4230 .addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef).addImm(0xff);
4231 return true;
4232 }
4233 case X86::VMOVAPSZ128rm_NOVLX:
4234 return expandNOVLXLoad(MIB, &getRegisterInfo(), get(X86::VMOVAPSrm),
4235 get(X86::VBROADCASTF32X4rm), X86::sub_xmm);
4236 case X86::VMOVUPSZ128rm_NOVLX:
4237 return expandNOVLXLoad(MIB, &getRegisterInfo(), get(X86::VMOVUPSrm),
4238 get(X86::VBROADCASTF32X4rm), X86::sub_xmm);
4239 case X86::VMOVAPSZ256rm_NOVLX:
4240 return expandNOVLXLoad(MIB, &getRegisterInfo(), get(X86::VMOVAPSYrm),
4241 get(X86::VBROADCASTF64X4rm), X86::sub_ymm);
4242 case X86::VMOVUPSZ256rm_NOVLX:
4243 return expandNOVLXLoad(MIB, &getRegisterInfo(), get(X86::VMOVUPSYrm),
4244 get(X86::VBROADCASTF64X4rm), X86::sub_ymm);
4245 case X86::VMOVAPSZ128mr_NOVLX:
4246 return expandNOVLXStore(MIB, &getRegisterInfo(), get(X86::VMOVAPSmr),
4247 get(X86::VEXTRACTF32x4Zmr), X86::sub_xmm);
4248 case X86::VMOVUPSZ128mr_NOVLX:
4249 return expandNOVLXStore(MIB, &getRegisterInfo(), get(X86::VMOVUPSmr),
4250 get(X86::VEXTRACTF32x4Zmr), X86::sub_xmm);
4251 case X86::VMOVAPSZ256mr_NOVLX:
4252 return expandNOVLXStore(MIB, &getRegisterInfo(), get(X86::VMOVAPSYmr),
4253 get(X86::VEXTRACTF64x4Zmr), X86::sub_ymm);
4254 case X86::VMOVUPSZ256mr_NOVLX:
4255 return expandNOVLXStore(MIB, &getRegisterInfo(), get(X86::VMOVUPSYmr),
4256 get(X86::VEXTRACTF64x4Zmr), X86::sub_ymm);
4257 case X86::MOV32ri64: {
4258 unsigned Reg = MIB->getOperand(0).getReg();
4259 unsigned Reg32 = RI.getSubReg(Reg, X86::sub_32bit);
4260 MI.setDesc(get(X86::MOV32ri));
4261 MIB->getOperand(0).setReg(Reg32);
4262 MIB.addReg(Reg, RegState::ImplicitDefine);
4263 return true;
4264 }
4265
4266 // KNL does not recognize dependency-breaking idioms for mask registers,
4267 // so kxnor %k1, %k1, %k2 has a RAW dependence on %k1.
4268 // Using %k0 as the undef input register is a performance heuristic based
4269 // on the assumption that %k0 is used less frequently than the other mask
4270 // registers, since it is not usable as a write mask.
4271 // FIXME: A more advanced approach would be to choose the best input mask
4272 // register based on context.
4273 case X86::KSET0W: return Expand2AddrKreg(MIB, get(X86::KXORWrr), X86::K0);
4274 case X86::KSET0D: return Expand2AddrKreg(MIB, get(X86::KXORDrr), X86::K0);
4275 case X86::KSET0Q: return Expand2AddrKreg(MIB, get(X86::KXORQrr), X86::K0);
4276 case X86::KSET1W: return Expand2AddrKreg(MIB, get(X86::KXNORWrr), X86::K0);
4277 case X86::KSET1D: return Expand2AddrKreg(MIB, get(X86::KXNORDrr), X86::K0);
4278 case X86::KSET1Q: return Expand2AddrKreg(MIB, get(X86::KXNORQrr), X86::K0);
4279 case TargetOpcode::LOAD_STACK_GUARD:
4280 expandLoadStackGuard(MIB, *this);
4281 return true;
4282 case X86::XOR64_FP:
4283 case X86::XOR32_FP:
4284 return expandXorFP(MIB, *this);
4285 }
4286 return false;
4287}
4288
4289/// Return true for all instructions that only update
4290/// the first 32 or 64-bits of the destination register and leave the rest
4291/// unmodified. This can be used to avoid folding loads if the instructions
4292/// only update part of the destination register, and the non-updated part is
4293/// not needed. e.g. cvtss2sd, sqrtss. Unfolding the load from these
4294/// instructions breaks the partial register dependency and it can improve
4295/// performance. e.g.:
4296///
4297/// movss (%rdi), %xmm0
4298/// cvtss2sd %xmm0, %xmm0
4299///
4300/// Instead of
4301/// cvtss2sd (%rdi), %xmm0
4302///
4303/// FIXME: This should be turned into a TSFlags.
4304///
4305static bool hasPartialRegUpdate(unsigned Opcode,
4306 const X86Subtarget &Subtarget) {
4307 switch (Opcode) {
4308 case X86::CVTSI2SSrr:
4309 case X86::CVTSI2SSrm:
4310 case X86::CVTSI642SSrr:
4311 case X86::CVTSI642SSrm:
4312 case X86::CVTSI2SDrr:
4313 case X86::CVTSI2SDrm:
4314 case X86::CVTSI642SDrr:
4315 case X86::CVTSI642SDrm:
4316 case X86::CVTSD2SSrr:
4317 case X86::CVTSD2SSrm:
4318 case X86::CVTSS2SDrr:
4319 case X86::CVTSS2SDrm:
4320 case X86::MOVHPDrm:
4321 case X86::MOVHPSrm:
4322 case X86::MOVLPDrm:
4323 case X86::MOVLPSrm:
4324 case X86::RCPSSr:
4325 case X86::RCPSSm:
4326 case X86::RCPSSr_Int:
4327 case X86::RCPSSm_Int:
4328 case X86::ROUNDSDr:
4329 case X86::ROUNDSDm:
4330 case X86::ROUNDSSr:
4331 case X86::ROUNDSSm:
4332 case X86::RSQRTSSr:
4333 case X86::RSQRTSSm:
4334 case X86::RSQRTSSr_Int:
4335 case X86::RSQRTSSm_Int:
4336 case X86::SQRTSSr:
4337 case X86::SQRTSSm:
4338 case X86::SQRTSSr_Int:
4339 case X86::SQRTSSm_Int:
4340 case X86::SQRTSDr:
4341 case X86::SQRTSDm:
4342 case X86::SQRTSDr_Int:
4343 case X86::SQRTSDm_Int:
4344 return true;
4345 // GPR
4346 case X86::POPCNT32rm:
4347 case X86::POPCNT32rr:
4348 case X86::POPCNT64rm:
4349 case X86::POPCNT64rr:
4350 return Subtarget.hasPOPCNTFalseDeps();
4351 case X86::LZCNT32rm:
4352 case X86::LZCNT32rr:
4353 case X86::LZCNT64rm:
4354 case X86::LZCNT64rr:
4355 case X86::TZCNT32rm:
4356 case X86::TZCNT32rr:
4357 case X86::TZCNT64rm:
4358 case X86::TZCNT64rr:
4359 return Subtarget.hasLZCNTFalseDeps();
4360 }
4361
4362 return false;
4363}
4364
4365/// Inform the BreakFalseDeps pass how many idle
4366/// instructions we would like before a partial register update.
4367unsigned X86InstrInfo::getPartialRegUpdateClearance(
4368 const MachineInstr &MI, unsigned OpNum,
4369 const TargetRegisterInfo *TRI) const {
4370 if (OpNum != 0 || !hasPartialRegUpdate(MI.getOpcode(), Subtarget))
4371 return 0;
4372
4373 // If MI is marked as reading Reg, the partial register update is wanted.
4374 const MachineOperand &MO = MI.getOperand(0);
4375 unsigned Reg = MO.getReg();
4376 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
4377 if (MO.readsReg() || MI.readsVirtualRegister(Reg))
4378 return 0;
4379 } else {
4380 if (MI.readsRegister(Reg, TRI))
4381 return 0;
4382 }
4383
4384 // If any instructions in the clearance range are reading Reg, insert a
4385 // dependency breaking instruction, which is inexpensive and is likely to
4386 // be hidden in other instruction's cycles.
4387 return PartialRegUpdateClearance;
4388}
4389
4390// Return true for any instruction the copies the high bits of the first source
4391// operand into the unused high bits of the destination operand.
4392static bool hasUndefRegUpdate(unsigned Opcode) {
4393 switch (Opcode) {
4394 case X86::VCVTSI2SSrr:
4395 case X86::VCVTSI2SSrm:
4396 case X86::VCVTSI2SSrr_Int:
4397 case X86::VCVTSI2SSrm_Int:
4398 case X86::VCVTSI642SSrr:
4399 case X86::VCVTSI642SSrm:
4400 case X86::VCVTSI642SSrr_Int:
4401 case X86::VCVTSI642SSrm_Int:
4402 case X86::VCVTSI2SDrr:
4403 case X86::VCVTSI2SDrm:
4404 case X86::VCVTSI2SDrr_Int:
4405 case X86::VCVTSI2SDrm_Int:
4406 case X86::VCVTSI642SDrr:
4407 case X86::VCVTSI642SDrm:
4408 case X86::VCVTSI642SDrr_Int:
4409 case X86::VCVTSI642SDrm_Int:
4410 case X86::VCVTSD2SSrr:
4411 case X86::VCVTSD2SSrm:
4412 case X86::VCVTSD2SSrr_Int:
4413 case X86::VCVTSD2SSrm_Int:
4414 case X86::VCVTSS2SDrr:
4415 case X86::VCVTSS2SDrm:
4416 case X86::VCVTSS2SDrr_Int:
4417 case X86::VCVTSS2SDrm_Int:
4418 case X86::VRCPSSr:
4419 case X86::VRCPSSr_Int:
4420 case X86::VRCPSSm:
4421 case X86::VRCPSSm_Int:
4422 case X86::VROUNDSDr:
4423 case X86::VROUNDSDm:
4424 case X86::VROUNDSDr_Int:
4425 case X86::VROUNDSDm_Int:
4426 case X86::VROUNDSSr:
4427 case X86::VROUNDSSm:
4428 case X86::VROUNDSSr_Int:
4429 case X86::VROUNDSSm_Int:
4430 case X86::VRSQRTSSr:
4431 case X86::VRSQRTSSr_Int:
4432 case X86::VRSQRTSSm:
4433 case X86::VRSQRTSSm_Int:
4434 case X86::VSQRTSSr:
4435 case X86::VSQRTSSr_Int:
4436 case X86::VSQRTSSm:
4437 case X86::VSQRTSSm_Int:
4438 case X86::VSQRTSDr:
4439 case X86::VSQRTSDr_Int:
4440 case X86::VSQRTSDm:
4441 case X86::VSQRTSDm_Int:
4442 // AVX-512
4443 case X86::VCVTSI2SSZrr:
4444 case X86::VCVTSI2SSZrm:
4445 case X86::VCVTSI2SSZrr_Int:
4446 case X86::VCVTSI2SSZrrb_Int:
4447 case X86::VCVTSI2SSZrm_Int:
4448 case X86::VCVTSI642SSZrr:
4449 case X86::VCVTSI642SSZrm:
4450 case X86::VCVTSI642SSZrr_Int:
4451 case X86::VCVTSI642SSZrrb_Int:
4452 case X86::VCVTSI642SSZrm_Int:
4453 case X86::VCVTSI2SDZrr:
4454 case X86::VCVTSI2SDZrm:
4455 case X86::VCVTSI2SDZrr_Int:
4456 case X86::VCVTSI2SDZrrb_Int:
4457 case X86::VCVTSI2SDZrm_Int:
4458 case X86::VCVTSI642SDZrr:
4459 case X86::VCVTSI642SDZrm:
4460 case X86::VCVTSI642SDZrr_Int:
4461 case X86::VCVTSI642SDZrrb_Int:
4462 case X86::VCVTSI642SDZrm_Int:
4463 case X86::VCVTUSI2SSZrr:
4464 case X86::VCVTUSI2SSZrm:
4465 case X86::VCVTUSI2SSZrr_Int:
4466 case X86::VCVTUSI2SSZrrb_Int:
4467 case X86::VCVTUSI2SSZrm_Int:
4468 case X86::VCVTUSI642SSZrr:
4469 case X86::VCVTUSI642SSZrm:
4470 case X86::VCVTUSI642SSZrr_Int:
4471 case X86::VCVTUSI642SSZrrb_Int:
4472 case X86::VCVTUSI642SSZrm_Int:
4473 case X86::VCVTUSI2SDZrr:
4474 case X86::VCVTUSI2SDZrm:
4475 case X86::VCVTUSI2SDZrr_Int:
4476 case X86::VCVTUSI2SDZrm_Int:
4477 case X86::VCVTUSI642SDZrr:
4478 case X86::VCVTUSI642SDZrm:
4479 case X86::VCVTUSI642SDZrr_Int:
4480 case X86::VCVTUSI642SDZrrb_Int:
4481 case X86::VCVTUSI642SDZrm_Int:
4482 case X86::VCVTSD2SSZrr:
4483 case X86::VCVTSD2SSZrr_Int:
4484 case X86::VCVTSD2SSZrrb_Int:
4485 case X86::VCVTSD2SSZrm:
4486 case X86::VCVTSD2SSZrm_Int:
4487 case X86::VCVTSS2SDZrr:
4488 case X86::VCVTSS2SDZrr_Int:
4489 case X86::VCVTSS2SDZrrb_Int:
4490 case X86::VCVTSS2SDZrm:
4491 case X86::VCVTSS2SDZrm_Int:
4492 case X86::VGETEXPSDZr:
4493 case X86::VGETEXPSDZrb:
4494 case X86::VGETEXPSDZm:
4495 case X86::VGETEXPSSZr:
4496 case X86::VGETEXPSSZrb:
4497 case X86::VGETEXPSSZm:
4498 case X86::VGETMANTSDZrri:
4499 case X86::VGETMANTSDZrrib:
4500 case X86::VGETMANTSDZrmi:
4501 case X86::VGETMANTSSZrri:
4502 case X86::VGETMANTSSZrrib:
4503 case X86::VGETMANTSSZrmi:
4504 case X86::VRNDSCALESDZr:
4505 case X86::VRNDSCALESDZr_Int:
4506 case X86::VRNDSCALESDZrb_Int:
4507 case X86::VRNDSCALESDZm:
4508 case X86::VRNDSCALESDZm_Int:
4509 case X86::VRNDSCALESSZr:
4510 case X86::VRNDSCALESSZr_Int:
4511 case X86::VRNDSCALESSZrb_Int:
4512 case X86::VRNDSCALESSZm:
4513 case X86::VRNDSCALESSZm_Int:
4514 case X86::VRCP14SDZrr:
4515 case X86::VRCP14SDZrm:
4516 case X86::VRCP14SSZrr:
4517 case X86::VRCP14SSZrm:
4518 case X86::VRCP28SDZr:
4519 case X86::VRCP28SDZrb:
4520 case X86::VRCP28SDZm:
4521 case X86::VRCP28SSZr:
4522 case X86::VRCP28SSZrb:
4523 case X86::VRCP28SSZm:
4524 case X86::VREDUCESSZrmi:
4525 case X86::VREDUCESSZrri:
4526 case X86::VREDUCESSZrrib:
4527 case X86::VRSQRT14SDZrr:
4528 case X86::VRSQRT14SDZrm:
4529 case X86::VRSQRT14SSZrr:
4530 case X86::VRSQRT14SSZrm:
4531 case X86::VRSQRT28SDZr:
4532 case X86::VRSQRT28SDZrb:
4533 case X86::VRSQRT28SDZm:
4534 case X86::VRSQRT28SSZr:
4535 case X86::VRSQRT28SSZrb:
4536 case X86::VRSQRT28SSZm:
4537 case X86::VSQRTSSZr:
4538 case X86::VSQRTSSZr_Int:
4539 case X86::VSQRTSSZrb_Int:
4540 case X86::VSQRTSSZm:
4541 case X86::VSQRTSSZm_Int:
4542 case X86::VSQRTSDZr:
4543 case X86::VSQRTSDZr_Int:
4544 case X86::VSQRTSDZrb_Int:
4545 case X86::VSQRTSDZm:
4546 case X86::VSQRTSDZm_Int:
4547 return true;
4548 }
4549
4550 return false;
4551}
4552
4553/// Inform the BreakFalseDeps pass how many idle instructions we would like
4554/// before certain undef register reads.
4555///
4556/// This catches the VCVTSI2SD family of instructions:
4557///
4558/// vcvtsi2sdq %rax, undef %xmm0, %xmm14
4559///
4560/// We should to be careful *not* to catch VXOR idioms which are presumably
4561/// handled specially in the pipeline:
4562///
4563/// vxorps undef %xmm1, undef %xmm1, %xmm1
4564///
4565/// Like getPartialRegUpdateClearance, this makes a strong assumption that the
4566/// high bits that are passed-through are not live.
4567unsigned
4568X86InstrInfo::getUndefRegClearance(const MachineInstr &MI, unsigned &OpNum,
4569 const TargetRegisterInfo *TRI) const {
4570 if (!hasUndefRegUpdate(MI.getOpcode()))
4571 return 0;
4572
4573 // Set the OpNum parameter to the first source operand.
4574 OpNum = 1;
4575
4576 const MachineOperand &MO = MI.getOperand(OpNum);
4577 if (MO.isUndef() && TargetRegisterInfo::isPhysicalRegister(MO.getReg())) {
4578 return UndefRegClearance;
4579 }
4580 return 0;
4581}
4582
4583void X86InstrInfo::breakPartialRegDependency(
4584 MachineInstr &MI, unsigned OpNum, const TargetRegisterInfo *TRI) const {
4585 unsigned Reg = MI.getOperand(OpNum).getReg();
4586 // If MI kills this register, the false dependence is already broken.
4587 if (MI.killsRegister(Reg, TRI))
4588 return;
4589
4590 if (X86::VR128RegClass.contains(Reg)) {
4591 // These instructions are all floating point domain, so xorps is the best
4592 // choice.
4593 unsigned Opc = Subtarget.hasAVX() ? X86::VXORPSrr : X86::XORPSrr;
4594 BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(Opc), Reg)
4595 .addReg(Reg, RegState::Undef)
4596 .addReg(Reg, RegState::Undef);
4597 MI.addRegisterKilled(Reg, TRI, true);
4598 } else if (X86::VR256RegClass.contains(Reg)) {
4599 // Use vxorps to clear the full ymm register.
4600 // It wants to read and write the xmm sub-register.
4601 unsigned XReg = TRI->getSubReg(Reg, X86::sub_xmm);
4602 BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(X86::VXORPSrr), XReg)
4603 .addReg(XReg, RegState::Undef)
4604 .addReg(XReg, RegState::Undef)
4605 .addReg(Reg, RegState::ImplicitDefine);
4606 MI.addRegisterKilled(Reg, TRI, true);
4607 } else if (X86::GR64RegClass.contains(Reg)) {
4608 // Using XOR32rr because it has shorter encoding and zeros up the upper bits
4609 // as well.
4610 unsigned XReg = TRI->getSubReg(Reg, X86::sub_32bit);
4611 BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(X86::XOR32rr), XReg)
4612 .addReg(XReg, RegState::Undef)
4613 .addReg(XReg, RegState::Undef)
4614 .addReg(Reg, RegState::ImplicitDefine);
4615 MI.addRegisterKilled(Reg, TRI, true);
4616 } else if (X86::GR32RegClass.contains(Reg)) {
4617 BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(X86::XOR32rr), Reg)
4618 .addReg(Reg, RegState::Undef)
4619 .addReg(Reg, RegState::Undef);
4620 MI.addRegisterKilled(Reg, TRI, true);
4621 }
4622}
4623
4624static void addOperands(MachineInstrBuilder &MIB, ArrayRef<MachineOperand> MOs,
4625 int PtrOffset = 0) {
4626 unsigned NumAddrOps = MOs.size();
4627
4628 if (NumAddrOps < 4) {
4629 // FrameIndex only - add an immediate offset (whether its zero or not).
4630 for (unsigned i = 0; i != NumAddrOps; ++i)
4631 MIB.add(MOs[i]);
4632 addOffset(MIB, PtrOffset);
4633 } else {
4634 // General Memory Addressing - we need to add any offset to an existing
4635 // offset.
4636 assert(MOs.size() == 5 && "Unexpected memory operand list length")((MOs.size() == 5 && "Unexpected memory operand list length"
) ? static_cast<void> (0) : __assert_fail ("MOs.size() == 5 && \"Unexpected memory operand list length\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/X86/X86InstrInfo.cpp"
, 4636, __PRETTY_FUNCTION__))
;
4637 for (unsigned i = 0; i != NumAddrOps; ++i) {
4638 const MachineOperand &MO = MOs[i];
4639 if (i == 3 && PtrOffset != 0) {
4640 MIB.addDisp(MO, PtrOffset);
4641 } else {
4642 MIB.add(MO);
4643 }
4644 }
4645 }
4646}
4647
4648static void updateOperandRegConstraints(MachineFunction &MF,
4649 MachineInstr &NewMI,
4650 const TargetInstrInfo &TII) {
4651 MachineRegisterInfo &MRI = MF.getRegInfo();
4652 const TargetRegisterInfo &TRI = *MRI.getTargetRegisterInfo();
4653
4654 for (int Idx : llvm::seq<int>(0, NewMI.getNumOperands())) {
4655 MachineOperand &MO = NewMI.getOperand(Idx);
4656 // We only need to update constraints on virtual register operands.
4657 if (!MO.isReg())
4658 continue;
4659 unsigned Reg = MO.getReg();
4660 if (!TRI.isVirtualRegister(Reg))
4661 continue;
4662
4663 auto *NewRC = MRI.constrainRegClass(
4664 Reg, TII.getRegClass(NewMI.getDesc(), Idx, &TRI, MF));
4665 if (!NewRC) {
4666 LLVM_DEBUG(do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("x86-instr-info")) { dbgs() << "WARNING: Unable to update register constraint for operand "
<< Idx << " of instruction:\n"; NewMI.dump(); dbgs
() << "\n"; } } while (false)
4667 dbgs() << "WARNING: Unable to update register constraint for operand "do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("x86-instr-info")) { dbgs() << "WARNING: Unable to update register constraint for operand "
<< Idx << " of instruction:\n"; NewMI.dump(); dbgs
() << "\n"; } } while (false)
4668 << Idx << " of instruction:\n";do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("x86-instr-info")) { dbgs() << "WARNING: Unable to update register constraint for operand "
<< Idx << " of instruction:\n"; NewMI.dump(); dbgs
() << "\n"; } } while (false)
4669 NewMI.dump(); dbgs() << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("x86-instr-info")) { dbgs() << "WARNING: Unable to update register constraint for operand "
<< Idx << " of instruction:\n"; NewMI.dump(); dbgs
() << "\n"; } } while (false)
;
4670 }
4671 }
4672}
4673
4674static MachineInstr *FuseTwoAddrInst(MachineFunction &MF, unsigned Opcode,
4675 ArrayRef<MachineOperand> MOs,
4676 MachineBasicBlock::iterator InsertPt,
4677 MachineInstr &MI,
4678 const TargetInstrInfo &TII) {
4679 // Create the base instruction with the memory operand as the first part.
4680 // Omit the implicit operands, something BuildMI can't do.
4681 MachineInstr *NewMI =
4682 MF.CreateMachineInstr(TII.get(Opcode), MI.getDebugLoc(), true);
4683 MachineInstrBuilder MIB(MF, NewMI);
4684 addOperands(MIB, MOs);
4685
4686 // Loop over the rest of the ri operands, converting them over.
4687 unsigned NumOps = MI.getDesc().getNumOperands() - 2;
4688 for (unsigned i = 0; i != NumOps; ++i) {
4689 MachineOperand &MO = MI.getOperand(i + 2);
4690 MIB.add(MO);
4691 }
4692 for (unsigned i = NumOps + 2, e = MI.getNumOperands(); i != e; ++i) {
4693 MachineOperand &MO = MI.getOperand(i);
4694 MIB.add(MO);
4695 }
4696
4697 updateOperandRegConstraints(MF, *NewMI, TII);
4698
4699 MachineBasicBlock *MBB = InsertPt->getParent();
4700 MBB->insert(InsertPt, NewMI);
4701
4702 return MIB;
4703}
4704
4705static MachineInstr *FuseInst(MachineFunction &MF, unsigned Opcode,
4706 unsigned OpNo, ArrayRef<MachineOperand> MOs,
4707 MachineBasicBlock::iterator InsertPt,
4708 MachineInstr &MI, const TargetInstrInfo &TII,
4709 int PtrOffset = 0) {
4710 // Omit the implicit operands, something BuildMI can't do.
4711 MachineInstr *NewMI =
4712 MF.CreateMachineInstr(TII.get(Opcode), MI.getDebugLoc(), true);
4713 MachineInstrBuilder MIB(MF, NewMI);
4714
4715 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
4716 MachineOperand &MO = MI.getOperand(i);
4717 if (i == OpNo) {
4718 assert(MO.isReg() && "Expected to fold into reg operand!")((MO.isReg() && "Expected to fold into reg operand!")
? static_cast<void> (0) : __assert_fail ("MO.isReg() && \"Expected to fold into reg operand!\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/X86/X86InstrInfo.cpp"
, 4718, __PRETTY_FUNCTION__))
;
4719 addOperands(MIB, MOs, PtrOffset);
4720 } else {
4721 MIB.add(MO);
4722 }
4723 }
4724
4725 updateOperandRegConstraints(MF, *NewMI, TII);
4726
4727 MachineBasicBlock *MBB = InsertPt->getParent();
4728 MBB->insert(InsertPt, NewMI);
4729
4730 return MIB;
4731}
4732
4733static MachineInstr *MakeM0Inst(const TargetInstrInfo &TII, unsigned Opcode,
4734 ArrayRef<MachineOperand> MOs,
4735 MachineBasicBlock::iterator InsertPt,
4736 MachineInstr &MI) {
4737 MachineInstrBuilder MIB = BuildMI(*InsertPt->getParent(), InsertPt,
4738 MI.getDebugLoc(), TII.get(Opcode));
4739 addOperands(MIB, MOs);
4740 return MIB.addImm(0);
4741}
4742
4743MachineInstr *X86InstrInfo::foldMemoryOperandCustom(
4744 MachineFunction &MF, MachineInstr &MI, unsigned OpNum,
4745 ArrayRef<MachineOperand> MOs, MachineBasicBlock::iterator InsertPt,
4746 unsigned Size, unsigned Align) const {
4747 switch (MI.getOpcode()) {
4748 case X86::INSERTPSrr:
4749 case X86::VINSERTPSrr:
4750 case X86::VINSERTPSZrr:
4751 // Attempt to convert the load of inserted vector into a fold load
4752 // of a single float.
4753 if (OpNum == 2) {
4754 unsigned Imm = MI.getOperand(MI.getNumOperands() - 1).getImm();
4755 unsigned ZMask = Imm & 15;
4756 unsigned DstIdx = (Imm >> 4) & 3;
4757 unsigned SrcIdx = (Imm >> 6) & 3;
4758
4759 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
4760 const TargetRegisterClass *RC = getRegClass(MI.getDesc(), OpNum, &RI, MF);
4761 unsigned RCSize = TRI.getRegSizeInBits(*RC) / 8;
4762 if (Size <= RCSize && 4 <= Align) {
4763 int PtrOffset = SrcIdx * 4;
4764 unsigned NewImm = (DstIdx << 4) | ZMask;
4765 unsigned NewOpCode =
4766 (MI.getOpcode() == X86::VINSERTPSZrr) ? X86::VINSERTPSZrm :
4767 (MI.getOpcode() == X86::VINSERTPSrr) ? X86::VINSERTPSrm :
4768 X86::INSERTPSrm;
4769 MachineInstr *NewMI =
4770 FuseInst(MF, NewOpCode, OpNum, MOs, InsertPt, MI, *this, PtrOffset);
4771 NewMI->getOperand(NewMI->getNumOperands() - 1).setImm(NewImm);
4772 return NewMI;
4773 }
4774 }
4775 break;
4776 case X86::MOVHLPSrr:
4777 case X86::VMOVHLPSrr:
4778 case X86::VMOVHLPSZrr:
4779 // Move the upper 64-bits of the second operand to the lower 64-bits.
4780 // To fold the load, adjust the pointer to the upper and use (V)MOVLPS.
4781 // TODO: In most cases AVX doesn't have a 8-byte alignment requirement.
4782 if (OpNum == 2) {
4783 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
4784 const TargetRegisterClass *RC = getRegClass(MI.getDesc(), OpNum, &RI, MF);
4785 unsigned RCSize = TRI.getRegSizeInBits(*RC) / 8;
4786 if (Size <= RCSize && 8 <= Align) {
4787 unsigned NewOpCode =
4788 (MI.getOpcode() == X86::VMOVHLPSZrr) ? X86::VMOVLPSZ128rm :
4789 (MI.getOpcode() == X86::VMOVHLPSrr) ? X86::VMOVLPSrm :
4790 X86::MOVLPSrm;
4791 MachineInstr *NewMI =
4792 FuseInst(MF, NewOpCode, OpNum, MOs, InsertPt, MI, *this, 8);
4793 return NewMI;
4794 }
4795 }
4796 break;
4797 };
4798
4799 return nullptr;
4800}
4801
4802static bool shouldPreventUndefRegUpdateMemFold(MachineFunction &MF, MachineInstr &MI) {
4803 if (MF.getFunction().optForSize() || !hasUndefRegUpdate(MI.getOpcode()) ||
4804 !MI.getOperand(1).isReg())
4805 return false;
4806
4807 // The are two cases we need to handle depending on where in the pipeline
4808 // the folding attempt is being made.
4809 // -Register has the undef flag set.
4810 // -Register is produced by the IMPLICIT_DEF instruction.
4811
4812 if (MI.getOperand(1).isUndef())
4813 return true;
4814
4815 MachineRegisterInfo &RegInfo = MF.getRegInfo();
4816 MachineInstr *VRegDef = RegInfo.getUniqueVRegDef(MI.getOperand(1).getReg());
4817 return VRegDef && VRegDef->isImplicitDef();
4818}
4819
4820
4821MachineInstr *X86InstrInfo::foldMemoryOperandImpl(
4822 MachineFunction &MF, MachineInstr &MI, unsigned OpNum,
4823 ArrayRef<MachineOperand> MOs, MachineBasicBlock::iterator InsertPt,
4824 unsigned Size, unsigned Align, bool AllowCommute) const {
4825 bool isSlowTwoMemOps = Subtarget.slowTwoMemOps();
4826 bool isTwoAddrFold = false;
4827
4828 // For CPUs that favor the register form of a call or push,
4829 // do not fold loads into calls or pushes, unless optimizing for size
4830 // aggressively.
4831 if (isSlowTwoMemOps && !MF.getFunction().optForMinSize() &&
4832 (MI.getOpcode() == X86::CALL32r || MI.getOpcode() == X86::CALL64r ||
4833 MI.getOpcode() == X86::PUSH16r || MI.getOpcode() == X86::PUSH32r ||
4834 MI.getOpcode() == X86::PUSH64r))
4835 return nullptr;
4836
4837 // Avoid partial and undef register update stalls unless optimizing for size.
4838 if (!MF.getFunction().optForSize() &&
4839 (hasPartialRegUpdate(MI.getOpcode(), Subtarget) ||
4840 shouldPreventUndefRegUpdateMemFold(MF, MI)))
4841 return nullptr;
4842
4843 unsigned NumOps = MI.getDesc().getNumOperands();
4844 bool isTwoAddr =
4845 NumOps > 1 && MI.getDesc().getOperandConstraint(1, MCOI::TIED_TO) != -1;
4846
4847 // FIXME: AsmPrinter doesn't know how to handle
4848 // X86II::MO_GOT_ABSOLUTE_ADDRESS after folding.
4849 if (MI.getOpcode() == X86::ADD32ri &&
4850 MI.getOperand(2).getTargetFlags() == X86II::MO_GOT_ABSOLUTE_ADDRESS)
4851 return nullptr;
4852
4853 // GOTTPOFF relocation loads can only be folded into add instructions.
4854 // FIXME: Need to exclude other relocations that only support specific
4855 // instructions.
4856 if (MOs.size() == X86::AddrNumOperands &&
4857 MOs[X86::AddrDisp].getTargetFlags() == X86II::MO_GOTTPOFF &&
4858 MI.getOpcode() != X86::ADD64rr)
4859 return nullptr;
4860
4861 MachineInstr *NewMI = nullptr;
4862
4863 // Attempt to fold any custom cases we have.
4864 if (MachineInstr *CustomMI =
4865 foldMemoryOperandCustom(MF, MI, OpNum, MOs, InsertPt, Size, Align))
4866 return CustomMI;
4867
4868 const X86MemoryFoldTableEntry *I = nullptr;
4869
4870 // Folding a memory location into the two-address part of a two-address
4871 // instruction is different than folding it other places. It requires
4872 // replacing the *two* registers with the memory location.
4873 if (isTwoAddr && NumOps >= 2 && OpNum < 2 && MI.getOperand(0).isReg() &&
4874 MI.getOperand(1).isReg() &&
4875 MI.getOperand(0).getReg() == MI.getOperand(1).getReg()) {
4876 I = lookupTwoAddrFoldTable(MI.getOpcode());
4877 isTwoAddrFold = true;
4878 } else {
4879 if (OpNum == 0) {
4880 if (MI.getOpcode() == X86::MOV32r0) {
4881 NewMI = MakeM0Inst(*this, X86::MOV32mi, MOs, InsertPt, MI);
4882 if (NewMI)
4883 return NewMI;
4884 }
4885 }
4886
4887 I = lookupFoldTable(MI.getOpcode(), OpNum);
4888 }
4889
4890 if (I != nullptr) {
4891 unsigned Opcode = I->DstOp;
4892 unsigned MinAlign = (I->Flags & TB_ALIGN_MASK) >> TB_ALIGN_SHIFT;
4893 if (Align < MinAlign)
4894 return nullptr;
4895 bool NarrowToMOV32rm = false;
4896 if (Size) {
4897 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
4898 const TargetRegisterClass *RC = getRegClass(MI.getDesc(), OpNum,
4899 &RI, MF);
4900 unsigned RCSize = TRI.getRegSizeInBits(*RC) / 8;
4901 if (Size < RCSize) {
4902 // Check if it's safe to fold the load. If the size of the object is
4903 // narrower than the load width, then it's not.
4904 if (Opcode != X86::MOV64rm || RCSize != 8 || Size != 4)
4905 return nullptr;
4906 // If this is a 64-bit load, but the spill slot is 32, then we can do
4907 // a 32-bit load which is implicitly zero-extended. This likely is
4908 // due to live interval analysis remat'ing a load from stack slot.
4909 if (MI.getOperand(0).getSubReg() || MI.getOperand(1).getSubReg())
4910 return nullptr;
4911 Opcode = X86::MOV32rm;
4912 NarrowToMOV32rm = true;
4913 }
4914 }
4915
4916 if (isTwoAddrFold)
4917 NewMI = FuseTwoAddrInst(MF, Opcode, MOs, InsertPt, MI, *this);
4918 else
4919 NewMI = FuseInst(MF, Opcode, OpNum, MOs, InsertPt, MI, *this);
4920
4921 if (NarrowToMOV32rm) {
4922 // If this is the special case where we use a MOV32rm to load a 32-bit
4923 // value and zero-extend the top bits. Change the destination register
4924 // to a 32-bit one.
4925 unsigned DstReg = NewMI->getOperand(0).getReg();
4926 if (TargetRegisterInfo::isPhysicalRegister(DstReg))
4927 NewMI->getOperand(0).setReg(RI.getSubReg(DstReg, X86::sub_32bit));
4928 else
4929 NewMI->getOperand(0).setSubReg(X86::sub_32bit);
4930 }
4931 return NewMI;
4932 }
4933
4934 // If the instruction and target operand are commutable, commute the
4935 // instruction and try again.
4936 if (AllowCommute) {
4937 unsigned CommuteOpIdx1 = OpNum, CommuteOpIdx2 = CommuteAnyOperandIndex;
4938 if (findCommutedOpIndices(MI, CommuteOpIdx1, CommuteOpIdx2)) {
4939 bool HasDef = MI.getDesc().getNumDefs();
4940 unsigned Reg0 = HasDef ? MI.getOperand(0).getReg() : 0;
4941 unsigned Reg1 = MI.getOperand(CommuteOpIdx1).getReg();
4942 unsigned Reg2 = MI.getOperand(CommuteOpIdx2).getReg();
4943 bool Tied1 =
4944 0 == MI.getDesc().getOperandConstraint(CommuteOpIdx1, MCOI::TIED_TO);
4945 bool Tied2 =
4946 0 == MI.getDesc().getOperandConstraint(CommuteOpIdx2, MCOI::TIED_TO);
4947
4948 // If either of the commutable operands are tied to the destination
4949 // then we can not commute + fold.
4950 if ((HasDef && Reg0 == Reg1 && Tied1) ||
4951 (HasDef && Reg0 == Reg2 && Tied2))
4952 return nullptr;
4953
4954 MachineInstr *CommutedMI =
4955 commuteInstruction(MI, false, CommuteOpIdx1, CommuteOpIdx2);
4956 if (!CommutedMI) {
4957 // Unable to commute.
4958 return nullptr;
4959 }
4960 if (CommutedMI != &MI) {
4961 // New instruction. We can't fold from this.
4962 CommutedMI->eraseFromParent();
4963 return nullptr;
4964 }
4965
4966 // Attempt to fold with the commuted version of the instruction.
4967 NewMI = foldMemoryOperandImpl(MF, MI, CommuteOpIdx2, MOs, InsertPt,
4968 Size, Align, /*AllowCommute=*/false);
4969 if (NewMI)
4970 return NewMI;
4971
4972 // Folding failed again - undo the commute before returning.
4973 MachineInstr *UncommutedMI =
4974 commuteInstruction(MI, false, CommuteOpIdx1, CommuteOpIdx2);
4975 if (!UncommutedMI) {
4976 // Unable to commute.
4977 return nullptr;
4978 }
4979 if (UncommutedMI != &MI) {
4980 // New instruction. It doesn't need to be kept.
4981 UncommutedMI->eraseFromParent();
4982 return nullptr;
4983 }
4984
4985 // Return here to prevent duplicate fuse failure report.
4986 return nullptr;
4987 }
4988 }
4989
4990 // No fusion
4991 if (PrintFailedFusing && !MI.isCopy())
4992 dbgs() << "We failed to fuse operand " << OpNum << " in " << MI;
4993 return nullptr;
4994}
4995
4996MachineInstr *
4997X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI,
4998 ArrayRef<unsigned> Ops,
4999 MachineBasicBlock::iterator InsertPt,
5000 int FrameIndex, LiveIntervals *LIS) const {
5001 // Check switch flag
5002 if (NoFusing)
5003 return nullptr;
5004
5005 // Avoid partial and undef register update stalls unless optimizing for size.
5006 if (!MF.getFunction().optForSize() &&
5007 (hasPartialRegUpdate(MI.getOpcode(), Subtarget) ||
5008 shouldPreventUndefRegUpdateMemFold(MF, MI)))
5009 return nullptr;
5010
5011 // Don't fold subreg spills, or reloads that use a high subreg.
5012 for (auto Op : Ops) {
5013 MachineOperand &MO = MI.getOperand(Op);
5014 auto SubReg = MO.getSubReg();
5015 if (SubReg && (MO.isDef() || SubReg == X86::sub_8bit_hi))
5016 return nullptr;
5017 }
5018
5019 const MachineFrameInfo &MFI = MF.getFrameInfo();
5020 unsigned Size = MFI.getObjectSize(FrameIndex);
5021 unsigned Alignment = MFI.getObjectAlignment(FrameIndex);
5022 // If the function stack isn't realigned we don't want to fold instructions
5023 // that need increased alignment.
5024 if (!RI.needsStackRealignment(MF))
5025 Alignment =
5026 std::min(Alignment, Subtarget.getFrameLowering()->getStackAlignment());
5027 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
5028 unsigned NewOpc = 0;
5029 unsigned RCSize = 0;
5030 switch (MI.getOpcode()) {
5031 default: return nullptr;
5032 case X86::TEST8rr: NewOpc = X86::CMP8ri; RCSize = 1; break;
5033 case X86::TEST16rr: NewOpc = X86::CMP16ri8; RCSize = 2; break;
5034 case X86::TEST32rr: NewOpc = X86::CMP32ri8; RCSize = 4; break;
5035 case X86::TEST64rr: NewOpc = X86::CMP64ri8; RCSize = 8; break;
5036 }
5037 // Check if it's safe to fold the load. If the size of the object is
5038 // narrower than the load width, then it's not.
5039 if (Size < RCSize)
5040 return nullptr;
5041 // Change to CMPXXri r, 0 first.
5042 MI.setDesc(get(NewOpc));
5043 MI.getOperand(1).ChangeToImmediate(0);
5044 } else if (Ops.size() != 1)
5045 return nullptr;
5046
5047 return foldMemoryOperandImpl(MF, MI, Ops[0],
5048 MachineOperand::CreateFI(FrameIndex), InsertPt,
5049 Size, Alignment, /*AllowCommute=*/true);
5050}
5051
5052/// Check if \p LoadMI is a partial register load that we can't fold into \p MI
5053/// because the latter uses contents that wouldn't be defined in the folded
5054/// version. For instance, this transformation isn't legal:
5055/// movss (%rdi), %xmm0
5056/// addps %xmm0, %xmm0
5057/// ->
5058/// addps (%rdi), %xmm0
5059///
5060/// But this one is:
5061/// movss (%rdi), %xmm0
5062/// addss %xmm0, %xmm0
5063/// ->
5064/// addss (%rdi), %xmm0
5065///
5066static bool isNonFoldablePartialRegisterLoad(const MachineInstr &LoadMI,
5067 const MachineInstr &UserMI,
5068 const MachineFunction &MF) {
5069 unsigned Opc = LoadMI.getOpcode();
5070 unsigned UserOpc = UserMI.getOpcode();
5071 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
5072 const TargetRegisterClass *RC =
5073 MF.getRegInfo().getRegClass(LoadMI.getOperand(0).getReg());
5074 unsigned RegSize = TRI.getRegSizeInBits(*RC);
5075
5076 if ((Opc == X86::MOVSSrm || Opc == X86::VMOVSSrm || Opc == X86::VMOVSSZrm) &&
5077 RegSize > 32) {
5078 // These instructions only load 32 bits, we can't fold them if the
5079 // destination register is wider than 32 bits (4 bytes), and its user
5080 // instruction isn't scalar (SS).
5081 switch (UserOpc) {
5082 case X86::ADDSSrr_Int: case X86::VADDSSrr_Int: case X86::VADDSSZrr_Int:
5083 case X86::CMPSSrr_Int: case X86::VCMPSSrr_Int: case X86::VCMPSSZrr_Int:
5084 case X86::DIVSSrr_Int: case X86::VDIVSSrr_Int: case X86::VDIVSSZrr_Int:
5085 case X86::MAXSSrr_Int: case X86::VMAXSSrr_Int: case X86::VMAXSSZrr_Int:
5086 case X86::MINSSrr_Int: case X86::VMINSSrr_Int: case X86::VMINSSZrr_Int:
5087 case X86::MULSSrr_Int: case X86::VMULSSrr_Int: case X86::VMULSSZrr_Int:
5088 case X86::SUBSSrr_Int: case X86::VSUBSSrr_Int: case X86::VSUBSSZrr_Int:
5089 case X86::VADDSSZrr_Intk: case X86::VADDSSZrr_Intkz:
5090 case X86::VDIVSSZrr_Intk: case X86::VDIVSSZrr_Intkz:
5091 case X86::VMAXSSZrr_Intk: case X86::VMAXSSZrr_Intkz:
5092 case X86::VMINSSZrr_Intk: case X86::VMINSSZrr_Intkz:
5093 case X86::VMULSSZrr_Intk: case X86::VMULSSZrr_Intkz:
5094 case X86::VSUBSSZrr_Intk: case X86::VSUBSSZrr_Intkz:
5095 case X86::VFMADDSS4rr_Int: case X86::VFNMADDSS4rr_Int:
5096 case X86::VFMSUBSS4rr_Int: case X86::VFNMSUBSS4rr_Int:
5097 case X86::VFMADD132SSr_Int: case X86::VFNMADD132SSr_Int:
5098 case X86::VFMADD213SSr_Int: case X86::VFNMADD213SSr_Int:
5099 case X86::VFMADD231SSr_Int: case X86::VFNMADD231SSr_Int:
5100 case X86::VFMSUB132SSr_Int: case X86::VFNMSUB132SSr_Int:
5101 case X86::VFMSUB213SSr_Int: case X86::VFNMSUB213SSr_Int:
5102 case X86::VFMSUB231SSr_Int: case X86::VFNMSUB231SSr_Int:
5103 case X86::VFMADD132SSZr_Int: case X86::VFNMADD132SSZr_Int:
5104 case X86::VFMADD213SSZr_Int: case X86::VFNMADD213SSZr_Int:
5105 case X86::VFMADD231SSZr_Int: case X86::VFNMADD231SSZr_Int:
5106 case X86::VFMSUB132SSZr_Int: case X86::VFNMSUB132SSZr_Int:
5107 case X86::VFMSUB213SSZr_Int: case X86::VFNMSUB213SSZr_Int:
5108 case X86::VFMSUB231SSZr_Int: case X86::VFNMSUB231SSZr_Int:
5109 case X86::VFMADD132SSZr_Intk: case X86::VFNMADD132SSZr_Intk:
5110 case X86::VFMADD213SSZr_Intk: case X86::VFNMADD213SSZr_Intk:
5111 case X86::VFMADD231SSZr_Intk: case X86::VFNMADD231SSZr_Intk:
5112 case X86::VFMSUB132SSZr_Intk: case X86::VFNMSUB132SSZr_Intk:
5113 case X86::VFMSUB213SSZr_Intk: case X86::VFNMSUB213SSZr_Intk:
5114 case X86::VFMSUB231SSZr_Intk: case X86::VFNMSUB231SSZr_Intk:
5115 case X86::VFMADD132SSZr_Intkz: case X86::VFNMADD132SSZr_Intkz:
5116 case X86::VFMADD213SSZr_Intkz: case X86::VFNMADD213SSZr_Intkz:
5117 case X86::VFMADD231SSZr_Intkz: case X86::VFNMADD231SSZr_Intkz:
5118 case X86::VFMSUB132SSZr_Intkz: case X86::VFNMSUB132SSZr_Intkz:
5119 case X86::VFMSUB213SSZr_Intkz: case X86::VFNMSUB213SSZr_Intkz:
5120 case X86::VFMSUB231SSZr_Intkz: case X86::VFNMSUB231SSZr_Intkz:
5121 return false;
5122 default:
5123 return true;
5124 }
5125 }
5126
5127 if ((Opc == X86::MOVSDrm || Opc == X86::VMOVSDrm || Opc == X86::VMOVSDZrm) &&
5128 RegSize > 64) {
5129 // These instructions only load 64 bits, we can't fold them if the
5130 // destination register is wider than 64 bits (8 bytes), and its user
5131 // instruction isn't scalar (SD).
5132 switch (UserOpc) {
5133 case X86::ADDSDrr_Int: case X86::VADDSDrr_Int: case X86::VADDSDZrr_Int:
5134 case X86::CMPSDrr_Int: case X86::VCMPSDrr_Int: case X86::VCMPSDZrr_Int:
5135 case X86::DIVSDrr_Int: case X86::VDIVSDrr_Int: case X86::VDIVSDZrr_Int:
5136 case X86::MAXSDrr_Int: case X86::VMAXSDrr_Int: case X86::VMAXSDZrr_Int:
5137 case X86::MINSDrr_Int: case X86::VMINSDrr_Int: case X86::VMINSDZrr_Int:
5138 case X86::MULSDrr_Int: case X86::VMULSDrr_Int: case X86::VMULSDZrr_Int:
5139 case X86::SUBSDrr_Int: case X86::VSUBSDrr_Int: case X86::VSUBSDZrr_Int:
5140 case X86::VADDSDZrr_Intk: case X86::VADDSDZrr_Intkz:
5141 case X86::VDIVSDZrr_Intk: case X86::VDIVSDZrr_Intkz:
5142 case X86::VMAXSDZrr_Intk: case X86::VMAXSDZrr_Intkz:
5143 case X86::VMINSDZrr_Intk: case X86::VMINSDZrr_Intkz:
5144 case X86::VMULSDZrr_Intk: case X86::VMULSDZrr_Intkz:
5145 case X86::VSUBSDZrr_Intk: case X86::VSUBSDZrr_Intkz:
5146 case X86::VFMADDSD4rr_Int: case X86::VFNMADDSD4rr_Int:
5147 case X86::VFMSUBSD4rr_Int: case X86::VFNMSUBSD4rr_Int:
5148 case X86::VFMADD132SDr_Int: case X86::VFNMADD132SDr_Int:
5149 case X86::VFMADD213SDr_Int: case X86::VFNMADD213SDr_Int:
5150 case X86::VFMADD231SDr_Int: case X86::VFNMADD231SDr_Int:
5151 case X86::VFMSUB132SDr_Int: case X86::VFNMSUB132SDr_Int:
5152 case X86::VFMSUB213SDr_Int: case X86::VFNMSUB213SDr_Int:
5153 case X86::VFMSUB231SDr_Int: case X86::VFNMSUB231SDr_Int:
5154 case X86::VFMADD132SDZr_Int: case X86::VFNMADD132SDZr_Int:
5155 case X86::VFMADD213SDZr_Int: case X86::VFNMADD213SDZr_Int:
5156 case X86::VFMADD231SDZr_Int: case X86::VFNMADD231SDZr_Int:
5157 case X86::VFMSUB132SDZr_Int: case X86::VFNMSUB132SDZr_Int:
5158 case X86::VFMSUB213SDZr_Int: case X86::VFNMSUB213SDZr_Int:
5159 case X86::VFMSUB231SDZr_Int: case X86::VFNMSUB231SDZr_Int:
5160 case X86::VFMADD132SDZr_Intk: case X86::VFNMADD132SDZr_Intk:
5161 case X86::VFMADD213SDZr_Intk: case X86::VFNMADD213SDZr_Intk:
5162 case X86::VFMADD231SDZr_Intk: case X86::VFNMADD231SDZr_Intk:
5163 case X86::VFMSUB132SDZr_Intk: case X86::VFNMSUB132SDZr_Intk:
5164 case X86::VFMSUB213SDZr_Intk: case X86::VFNMSUB213SDZr_Intk:
5165 case X86::VFMSUB231SDZr_Intk: case X86::VFNMSUB231SDZr_Intk:
5166 case X86::VFMADD132SDZr_Intkz: case X86::VFNMADD132SDZr_Intkz:
5167 case X86::VFMADD213SDZr_Intkz: case X86::VFNMADD213SDZr_Intkz:
5168 case X86::VFMADD231SDZr_Intkz: case X86::VFNMADD231SDZr_Intkz:
5169 case X86::VFMSUB132SDZr_Intkz: case X86::VFNMSUB132SDZr_Intkz:
5170 case X86::VFMSUB213SDZr_Intkz: case X86::VFNMSUB213SDZr_Intkz:
5171 case X86::VFMSUB231SDZr_Intkz: case X86::VFNMSUB231SDZr_Intkz:
5172 return false;
5173 default:
5174 return true;
5175 }
5176 }
5177
5178 return false;
5179}
5180
5181MachineInstr *X86InstrInfo::foldMemoryOperandImpl(
5182 MachineFunction &MF, MachineInstr &MI, ArrayRef<unsigned> Ops,
5183 MachineBasicBlock::iterator InsertPt, MachineInstr &LoadMI,
5184 LiveIntervals *LIS) const {
5185
5186 // TODO: Support the case where LoadMI loads a wide register, but MI
5187 // only uses a subreg.
5188 for (auto Op : Ops) {
5189 if (MI.getOperand(Op).getSubReg())
5190 return nullptr;
5191 }
5192
5193 // If loading from a FrameIndex, fold directly from the FrameIndex.
5194 unsigned NumOps = LoadMI.getDesc().getNumOperands();
5195 int FrameIndex;
5196 if (isLoadFromStackSlot(LoadMI, FrameIndex)) {
5197 if (isNonFoldablePartialRegisterLoad(LoadMI, MI, MF))
5198 return nullptr;
5199 return foldMemoryOperandImpl(MF, MI, Ops, InsertPt, FrameIndex, LIS);
5200 }
5201
5202 // Check switch flag
5203 if (NoFusing) return nullptr;
5204
5205 // Avoid partial and undef register update stalls unless optimizing for size.
5206 if (!MF.getFunction().optForSize() &&
5207 (hasPartialRegUpdate(MI.getOpcode(), Subtarget) ||
5208 shouldPreventUndefRegUpdateMemFold(MF, MI)))
5209 return nullptr;
5210
5211 // Determine the alignment of the load.
5212 unsigned Alignment = 0;
5213 if (LoadMI.hasOneMemOperand())
5214 Alignment = (*LoadMI.memoperands_begin())->getAlignment();
5215 else
5216 switch (LoadMI.getOpcode()) {
5217 case X86::AVX512_512_SET0:
5218 case X86::AVX512_512_SETALLONES:
5219 Alignment = 64;
5220 break;
5221 case X86::AVX2_SETALLONES:
5222 case X86::AVX1_SETALLONES:
5223 case X86::AVX_SET0:
5224 case X86::AVX512_256_SET0:
5225 Alignment = 32;
5226 break;
5227 case X86::V_SET0:
5228 case X86::V_SETALLONES:
5229 case X86::AVX512_128_SET0:
5230 Alignment = 16;
5231 break;
5232 case X86::MMX_SET0:
5233 case X86::FsFLD0SD:
5234 case X86::AVX512_FsFLD0SD:
5235 Alignment = 8;
5236 break;
5237 case X86::FsFLD0SS:
5238 case X86::AVX512_FsFLD0SS:
5239 Alignment = 4;
5240 break;
5241 default:
5242 return nullptr;
5243 }
5244 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
5245 unsigned NewOpc = 0;
5246 switch (MI.getOpcode()) {
5247 default: return nullptr;
5248 case X86::TEST8rr: NewOpc = X86::CMP8ri; break;
5249 case X86::TEST16rr: NewOpc = X86::CMP16ri8; break;
5250 case X86::TEST32rr: NewOpc = X86::CMP32ri8; break;
5251 case X86::TEST64rr: NewOpc = X86::CMP64ri8; break;
5252 }
5253 // Change to CMPXXri r, 0 first.
5254 MI.setDesc(get(NewOpc));
5255 MI.getOperand(1).ChangeToImmediate(0);
5256 } else if (Ops.size() != 1)
5257 return nullptr;
5258
5259 // Make sure the subregisters match.
5260 // Otherwise we risk changing the size of the load.
5261 if (LoadMI.getOperand(0).getSubReg() != MI.getOperand(Ops[0]).getSubReg())
5262 return nullptr;
5263
5264 SmallVector<MachineOperand,X86::AddrNumOperands> MOs;
5265 switch (LoadMI.getOpcode()) {
5266 case X86::MMX_SET0:
5267 case X86::V_SET0:
5268 case X86::V_SETALLONES:
5269 case X86::AVX2_SETALLONES:
5270 case X86::AVX1_SETALLONES:
5271 case X86::AVX_SET0:
5272 case X86::AVX512_128_SET0:
5273 case X86::AVX512_256_SET0:
5274 case X86::AVX512_512_SET0:
5275 case X86::AVX512_512_SETALLONES:
5276 case X86::FsFLD0SD:
5277 case X86::AVX512_FsFLD0SD:
5278 case X86::FsFLD0SS:
5279 case X86::AVX512_FsFLD0SS: {
5280 // Folding a V_SET0 or V_SETALLONES as a load, to ease register pressure.
5281 // Create a constant-pool entry and operands to load from it.
5282
5283 // Medium and large mode can't fold loads this way.
5284 if (MF.getTarget().getCodeModel() != CodeModel::Small &&
5285 MF.getTarget().getCodeModel() != CodeModel::Kernel)
5286 return nullptr;
5287
5288 // x86-32 PIC requires a PIC base register for constant pools.
5289 unsigned PICBase = 0;
5290 if (MF.getTarget().isPositionIndependent()) {
5291 if (Subtarget.is64Bit())
5292 PICBase = X86::RIP;
5293 else
5294 // FIXME: PICBase = getGlobalBaseReg(&MF);
5295 // This doesn't work for several reasons.
5296 // 1. GlobalBaseReg may have been spilled.
5297 // 2. It may not be live at MI.
5298 return nullptr;
5299 }
5300
5301 // Create a constant-pool entry.
5302 MachineConstantPool &MCP = *MF.getConstantPool();
5303 Type *Ty;
5304 unsigned Opc = LoadMI.getOpcode();
5305 if (Opc == X86::FsFLD0SS || Opc == X86::AVX512_FsFLD0SS)
5306 Ty = Type::getFloatTy(MF.getFunction().getContext());
5307 else if (Opc == X86::FsFLD0SD || Opc == X86::AVX512_FsFLD0SD)
5308 Ty = Type::getDoubleTy(MF.getFunction().getContext());
5309 else if (Opc == X86::AVX512_512_SET0 || Opc == X86::AVX512_512_SETALLONES)
5310 Ty = VectorType::get(Type::getInt32Ty(MF.getFunction().getContext()),16);
5311 else if (Opc == X86::AVX2_SETALLONES || Opc == X86::AVX_SET0 ||
5312 Opc == X86::AVX512_256_SET0 || Opc == X86::AVX1_SETALLONES)
5313 Ty = VectorType::get(Type::getInt32Ty(MF.getFunction().getContext()), 8);
5314 else if (Opc == X86::MMX_SET0)
5315 Ty = VectorType::get(Type::getInt32Ty(MF.getFunction().getContext()), 2);
5316 else
5317 Ty = VectorType::get(Type::getInt32Ty(MF.getFunction().getContext()), 4);
5318
5319 bool IsAllOnes = (Opc == X86::V_SETALLONES || Opc == X86::AVX2_SETALLONES ||
5320 Opc == X86::AVX512_512_SETALLONES ||
5321 Opc == X86::AVX1_SETALLONES);
5322 const Constant *C = IsAllOnes ? Constant::getAllOnesValue(Ty) :
5323 Constant::getNullValue(Ty);
5324 unsigned CPI = MCP.getConstantPoolIndex(C, Alignment);
5325
5326 // Create operands to load from the constant pool entry.
5327 MOs.push_back(MachineOperand::CreateReg(PICBase, false));
5328 MOs.push_back(MachineOperand::CreateImm(1));
5329 MOs.push_back(MachineOperand::CreateReg(0, false));
5330 MOs.push_back(MachineOperand::CreateCPI(CPI, 0));
5331 MOs.push_back(MachineOperand::CreateReg(0, false));
5332 break;
5333 }
5334 default: {
5335 if (isNonFoldablePartialRegisterLoad(LoadMI, MI, MF))
5336 return nullptr;
5337
5338 // Folding a normal load. Just copy the load's address operands.
5339 MOs.append(LoadMI.operands_begin() + NumOps - X86::AddrNumOperands,
5340 LoadMI.operands_begin() + NumOps);
5341 break;
5342 }
5343 }
5344 return foldMemoryOperandImpl(MF, MI, Ops[0], MOs, InsertPt,
5345 /*Size=*/0, Alignment, /*AllowCommute=*/true);
5346}
5347
5348static SmallVector<MachineMemOperand *, 2>
5349extractLoadMMOs(ArrayRef<MachineMemOperand *> MMOs, MachineFunction &MF) {
5350 SmallVector<MachineMemOperand *, 2> LoadMMOs;
5351
5352 for (MachineMemOperand *MMO : MMOs) {
5353 if (!MMO->isLoad())
5354 continue;
5355
5356 if (!MMO->isStore()) {
5357 // Reuse the MMO.
5358 LoadMMOs.push_back(MMO);
5359 } else {
5360 // Clone the MMO and unset the store flag.
5361 LoadMMOs.push_back(MF.getMachineMemOperand(
5362 MMO->getPointerInfo(), MMO->getFlags() & ~MachineMemOperand::MOStore,
5363 MMO->getSize(), MMO->getBaseAlignment(), MMO->getAAInfo(), nullptr,
5364 MMO->getSyncScopeID(), MMO->getOrdering(),
5365 MMO->getFailureOrdering()));
5366 }
5367 }
5368
5369 return LoadMMOs;
5370}
5371
5372static SmallVector<MachineMemOperand *, 2>
5373extractStoreMMOs(ArrayRef<MachineMemOperand *> MMOs, MachineFunction &MF) {
5374 SmallVector<MachineMemOperand *, 2> StoreMMOs;
5375
5376 for (MachineMemOperand *MMO : MMOs) {
5377 if (!MMO->isStore())
5378 continue;
5379
5380 if (!MMO->isLoad()) {
5381 // Reuse the MMO.
5382 StoreMMOs.push_back(MMO);
5383 } else {
5384 // Clone the MMO and unset the load flag.
5385 StoreMMOs.push_back(MF.getMachineMemOperand(
5386 MMO->getPointerInfo(), MMO->getFlags() & ~MachineMemOperand::MOLoad,
5387 MMO->getSize(), MMO->getBaseAlignment(), MMO->getAAInfo(), nullptr,
5388 MMO->getSyncScopeID(), MMO->getOrdering(),
5389 MMO->getFailureOrdering()));
5390 }
5391 }
5392
5393 return StoreMMOs;
5394}
5395
5396bool X86InstrInfo::unfoldMemoryOperand(
5397 MachineFunction &MF, MachineInstr &MI, unsigned Reg, bool UnfoldLoad,
5398 bool UnfoldStore, SmallVectorImpl<MachineInstr *> &NewMIs) const {
5399 const X86MemoryFoldTableEntry *I = lookupUnfoldTable(MI.getOpcode());
5400 if (I == nullptr)
5401 return false;
5402 unsigned Opc = I->DstOp;
5403 unsigned Index = I->Flags & TB_INDEX_MASK;
5404 bool FoldedLoad = I->Flags & TB_FOLDED_LOAD;
5405 bool FoldedStore = I->Flags & TB_FOLDED_STORE;
5406 if (UnfoldLoad && !FoldedLoad)
5407 return false;
5408 UnfoldLoad &= FoldedLoad;
5409 if (UnfoldStore && !FoldedStore)
5410 return false;
5411 UnfoldStore &= FoldedStore;
5412
5413 const MCInstrDesc &MCID = get(Opc);
5414 const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI, MF);
5415 // TODO: Check if 32-byte or greater accesses are slow too?
5416 if (!MI.hasOneMemOperand() && RC == &X86::VR128RegClass &&
5417 Subtarget.isUnalignedMem16Slow())
5418 // Without memoperands, loadRegFromAddr and storeRegToStackSlot will
5419 // conservatively assume the address is unaligned. That's bad for
5420 // performance.
5421 return false;
5422 SmallVector<MachineOperand, X86::AddrNumOperands> AddrOps;
5423 SmallVector<MachineOperand,2> BeforeOps;
5424 SmallVector<MachineOperand,2> AfterOps;
5425 SmallVector<MachineOperand,4> ImpOps;
5426 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
5427 MachineOperand &Op = MI.getOperand(i);
5428 if (i >= Index && i < Index + X86::AddrNumOperands)
5429 AddrOps.push_back(Op);
5430 else if (Op.isReg() && Op.isImplicit())
5431 ImpOps.push_back(Op);
5432 else if (i < Index)
5433 BeforeOps.push_back(Op);
5434 else if (i > Index)
5435 AfterOps.push_back(Op);
5436 }
5437
5438 // Emit the load instruction.
5439 if (UnfoldLoad) {
5440 auto MMOs = extractLoadMMOs(MI.memoperands(), MF);
5441 loadRegFromAddr(MF, Reg, AddrOps, RC, MMOs, NewMIs);
5442 if (UnfoldStore) {
5443 // Address operands cannot be marked isKill.
5444 for (unsigned i = 1; i != 1 + X86::AddrNumOperands; ++i) {
5445 MachineOperand &MO = NewMIs[0]->getOperand(i);
5446 if (MO.isReg())
5447 MO.setIsKill(false);
5448 }
5449 }
5450 }
5451
5452 // Emit the data processing instruction.
5453 MachineInstr *DataMI = MF.CreateMachineInstr(MCID, MI.getDebugLoc(), true);
5454 MachineInstrBuilder MIB(MF, DataMI);
5455
5456 if (FoldedStore)
5457 MIB.addReg(Reg, RegState::Define);
5458 for (MachineOperand &BeforeOp : BeforeOps)
5459 MIB.add(BeforeOp);
5460 if (FoldedLoad)
5461 MIB.addReg(Reg);
5462 for (MachineOperand &AfterOp : AfterOps)
5463 MIB.add(AfterOp);
5464 for (MachineOperand &ImpOp : ImpOps) {
5465 MIB.addReg(ImpOp.getReg(),
5466 getDefRegState(ImpOp.isDef()) |
5467 RegState::Implicit |
5468 getKillRegState(ImpOp.isKill()) |
5469 getDeadRegState(ImpOp.isDead()) |
5470 getUndefRegState(ImpOp.isUndef()));
5471 }
5472 // Change CMP32ri r, 0 back to TEST32rr r, r, etc.
5473 switch (DataMI->getOpcode()) {
5474 default: break;
5475 case X86::CMP64ri32:
5476 case X86::CMP64ri8:
5477 case X86::CMP32ri:
5478 case X86::CMP32ri8:
5479 case X86::CMP16ri:
5480 case X86::CMP16ri8:
5481 case X86::CMP8ri: {
5482 MachineOperand &MO0 = DataMI->getOperand(0);
5483 MachineOperand &MO1 = DataMI->getOperand(1);
5484 if (MO1.getImm() == 0) {
5485 unsigned NewOpc;
5486 switch (DataMI->getOpcode()) {
5487 default: llvm_unreachable("Unreachable!")::llvm::llvm_unreachable_internal("Unreachable!", "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/X86/X86InstrInfo.cpp"
, 5487)
;
5488 case X86::CMP64ri8:
5489 case X86::CMP64ri32: NewOpc = X86::TEST64rr; break;
5490 case X86::CMP32ri8:
5491 case X86::CMP32ri: NewOpc = X86::TEST32rr; break;
5492 case X86::CMP16ri8:
5493 case X86::CMP16ri: NewOpc = X86::TEST16rr; break;
5494 case X86::CMP8ri: NewOpc = X86::TEST8rr; break;
5495 }
5496 DataMI->setDesc(get(NewOpc));
5497 MO1.ChangeToRegister(MO0.getReg(), false);
5498 }
5499 }
5500 }
5501 NewMIs.push_back(DataMI);
5502
5503 // Emit the store instruction.
5504 if (UnfoldStore) {
5505 const TargetRegisterClass *DstRC = getRegClass(MCID, 0, &RI, MF);
5506 auto MMOs = extractStoreMMOs(MI.memoperands(), MF);
5507 storeRegToAddr(MF, Reg, true, AddrOps, DstRC, MMOs, NewMIs);
5508 }
5509
5510 return true;
5511}
5512
5513bool
5514X86InstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
5515 SmallVectorImpl<SDNode*> &NewNodes) const {
5516 if (!N->isMachineOpcode())
5517 return false;
5518
5519 const X86MemoryFoldTableEntry *I = lookupUnfoldTable(N->getMachineOpcode());
5520 if (I == nullptr)
5521 return false;
5522 unsigned Opc = I->DstOp;
5523 unsigned Index = I->Flags & TB_INDEX_MASK;
5524 bool FoldedLoad = I->Flags & TB_FOLDED_LOAD;
5525 bool FoldedStore = I->Flags & TB_FOLDED_STORE;
5526 const MCInstrDesc &MCID = get(Opc);
5527 MachineFunction &MF = DAG.getMachineFunction();
5528 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
5529 const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI, MF);
5530 unsigned NumDefs = MCID.NumDefs;
5531 std::vector<SDValue> AddrOps;
5532 std::vector<SDValue> BeforeOps;
5533 std::vector<SDValue> AfterOps;
5534 SDLoc dl(N);
5535 unsigned NumOps = N->getNumOperands();
5536 for (unsigned i = 0; i != NumOps-1; ++i) {
5537 SDValue Op = N->getOperand(i);
5538 if (i >= Index-NumDefs && i < Index-NumDefs + X86::AddrNumOperands)
5539 AddrOps.push_back(Op);
5540 else if (i < Index-NumDefs)
5541 BeforeOps.push_back(Op);
5542 else if (i > Index-NumDefs)
5543 AfterOps.push_back(Op);
5544 }
5545 SDValue Chain = N->getOperand(NumOps-1);
5546 AddrOps.push_back(Chain);
5547
5548 // Emit the load instruction.
5549 SDNode *Load = nullptr;
5550 if (FoldedLoad) {
5551 EVT VT = *TRI.legalclasstypes_begin(*RC);
5552 auto MMOs = extractLoadMMOs(cast<MachineSDNode>(N)->memoperands(), MF);
5553 if (MMOs.empty() && RC == &X86::VR128RegClass &&
5554 Subtarget.isUnalignedMem16Slow())
5555 // Do not introduce a slow unaligned load.
5556 return false;
5557 // FIXME: If a VR128 can have size 32, we should be checking if a 32-byte
5558 // memory access is slow above.
5559 unsigned Alignment = std::max<uint32_t>(TRI.getSpillSize(*RC), 16);
5560 bool isAligned = !MMOs.empty() && MMOs.front()->getAlignment() >= Alignment;
5561 Load = DAG.getMachineNode(getLoadRegOpcode(0, RC, isAligned, Subtarget), dl,
5562 VT, MVT::Other, AddrOps);
5563 NewNodes.push_back(Load);
5564
5565 // Preserve memory reference information.
5566 DAG.setNodeMemRefs(cast<MachineSDNode>(Load), MMOs);
5567 }
5568
5569 // Emit the data processing instruction.
5570 std::vector<EVT> VTs;
5571 const TargetRegisterClass *DstRC = nullptr;
5572 if (MCID.getNumDefs() > 0) {
5573 DstRC = getRegClass(MCID, 0, &RI, MF);
5574 VTs.push_back(*TRI.legalclasstypes_begin(*DstRC));
5575 }
5576 for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) {
5577 EVT VT = N->getValueType(i);
5578 if (VT != MVT::Other && i >= (unsigned)MCID.getNumDefs())
5579 VTs.push_back(VT);
5580 }
5581 if (Load)
5582 BeforeOps.push_back(SDValue(Load, 0));
5583 BeforeOps.insert(BeforeOps.end(), AfterOps.begin(), AfterOps.end());
5584 // Change CMP32ri r, 0 back to TEST32rr r, r, etc.
5585 switch (Opc) {
5586 default: break;
5587 case X86::CMP64ri32:
5588 case X86::CMP64ri8:
5589 case X86::CMP32ri:
5590 case X86::CMP32ri8:
5591 case X86::CMP16ri:
5592 case X86::CMP16ri8:
5593 case X86::CMP8ri:
5594 if (isNullConstant(BeforeOps[1])) {
5595 switch (Opc) {
5596 default: llvm_unreachable("Unreachable!")::llvm::llvm_unreachable_internal("Unreachable!", "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/X86/X86InstrInfo.cpp"
, 5596)
;
5597 case X86::CMP64ri8:
5598 case X86::CMP64ri32: Opc = X86::TEST64rr; break;
5599 case X86::CMP32ri8:
5600 case X86::CMP32ri: Opc = X86::TEST32rr; break;
5601 case X86::CMP16ri8:
5602 case X86::CMP16ri: Opc = X86::TEST16rr; break;
5603 case X86::CMP8ri: Opc = X86::TEST8rr; break;
5604 }
5605 BeforeOps[1] = BeforeOps[0];
5606 }
5607 }
5608 SDNode *NewNode= DAG.getMachineNode(Opc, dl, VTs, BeforeOps);
5609 NewNodes.push_back(NewNode);
5610
5611 // Emit the store instruction.
5612 if (FoldedStore) {
5613 AddrOps.pop_back();
5614 AddrOps.push_back(SDValue(NewNode, 0));
5615 AddrOps.push_back(Chain);
5616 auto MMOs = extractStoreMMOs(cast<MachineSDNode>(N)->memoperands(), MF);
5617 if (MMOs.empty() && RC == &X86::VR128RegClass &&
5618 Subtarget.isUnalignedMem16Slow())
5619 // Do not introduce a slow unaligned store.
5620 return false;
5621 // FIXME: If a VR128 can have size 32, we should be checking if a 32-byte
5622 // memory access is slow above.
5623 unsigned Alignment = std::max<uint32_t>(TRI.getSpillSize(*RC), 16);
5624 bool isAligned = !MMOs.empty() && MMOs.front()->getAlignment() >= Alignment;
5625 SDNode *Store =
5626 DAG.getMachineNode(getStoreRegOpcode(0, DstRC, isAligned, Subtarget),
5627 dl, MVT::Other, AddrOps);
5628 NewNodes.push_back(Store);
5629
5630 // Preserve memory reference information.
5631 DAG.setNodeMemRefs(cast<MachineSDNode>(Store), MMOs);
5632 }
5633
5634 return true;
5635}
5636
5637unsigned X86InstrInfo::getOpcodeAfterMemoryUnfold(unsigned Opc,
5638 bool UnfoldLoad, bool UnfoldStore,
5639 unsigned *LoadRegIndex) const {
5640 const X86MemoryFoldTableEntry *I = lookupUnfoldTable(Opc);
5641 if (I == nullptr)
5642 return 0;
5643 bool FoldedLoad = I->Flags & TB_FOLDED_LOAD;
5644 bool FoldedStore = I->Flags & TB_FOLDED_STORE;
5645 if (UnfoldLoad && !FoldedLoad)
5646 return 0;
5647 if (UnfoldStore && !FoldedStore)
5648 return 0;
5649 if (LoadRegIndex)
5650 *LoadRegIndex = I->Flags & TB_INDEX_MASK;
5651 return I->DstOp;
5652}
5653
5654bool
5655X86InstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
5656 int64_t &Offset1, int64_t &Offset2) const {
5657 if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode())
5658 return false;
5659 unsigned Opc1 = Load1->getMachineOpcode();
5660 unsigned Opc2 = Load2->getMachineOpcode();
5661 switch (Opc1) {
5662 default: return false;
5663 case X86::MOV8rm:
5664 case X86::MOV16rm:
5665 case X86::MOV32rm:
5666 case X86::MOV64rm:
5667 case X86::LD_Fp32m:
5668 case X86::LD_Fp64m:
5669 case X86::LD_Fp80m:
5670 case X86::MOVSSrm:
5671 case X86::MOVSDrm:
5672 case X86::MMX_MOVD64rm:
5673 case X86::MMX_MOVQ64rm:
5674 case X86::MOVAPSrm:
5675 case X86::MOVUPSrm:
5676 case X86::MOVAPDrm:
5677 case X86::MOVUPDrm:
5678 case X86::MOVDQArm:
5679 case X86::MOVDQUrm:
5680 // AVX load instructions
5681 case X86::VMOVSSrm:
5682 case X86::VMOVSDrm:
5683 case X86::VMOVAPSrm:
5684 case X86::VMOVUPSrm:
5685 case X86::VMOVAPDrm:
5686 case X86::VMOVUPDrm:
5687 case X86::VMOVDQArm:
5688 case X86::VMOVDQUrm:
5689 case X86::VMOVAPSYrm:
5690 case X86::VMOVUPSYrm:
5691 case X86::VMOVAPDYrm:
5692 case X86::VMOVUPDYrm:
5693 case X86::VMOVDQAYrm:
5694 case X86::VMOVDQUYrm:
5695 // AVX512 load instructions
5696 case X86::VMOVSSZrm:
5697 case X86::VMOVSDZrm:
5698 case X86::VMOVAPSZ128rm:
5699 case X86::VMOVUPSZ128rm:
5700 case X86::VMOVAPSZ128rm_NOVLX:
5701 case X86::VMOVUPSZ128rm_NOVLX:
5702 case X86::VMOVAPDZ128rm:
5703 case X86::VMOVUPDZ128rm:
5704 case X86::VMOVDQU8Z128rm:
5705 case X86::VMOVDQU16Z128rm:
5706 case X86::VMOVDQA32Z128rm:
5707 case X86::VMOVDQU32Z128rm:
5708 case X86::VMOVDQA64Z128rm:
5709 case X86::VMOVDQU64Z128rm:
5710 case X86::VMOVAPSZ256rm:
5711 case X86::VMOVUPSZ256rm:
5712 case X86::VMOVAPSZ256rm_NOVLX:
5713 case X86::VMOVUPSZ256rm_NOVLX:
5714 case X86::VMOVAPDZ256rm:
5715 case X86::VMOVUPDZ256rm:
5716 case X86::VMOVDQU8Z256rm:
5717 case X86::VMOVDQU16Z256rm:
5718 case X86::VMOVDQA32Z256rm:
5719 case X86::VMOVDQU32Z256rm:
5720 case X86::VMOVDQA64Z256rm:
5721 case X86::VMOVDQU64Z256rm:
5722 case X86::VMOVAPSZrm:
5723 case X86::VMOVUPSZrm:
5724 case X86::VMOVAPDZrm:
5725 case X86::VMOVUPDZrm:
5726 case X86::VMOVDQU8Zrm:
5727 case X86::VMOVDQU16Zrm:
5728 case X86::VMOVDQA32Zrm:
5729 case X86::VMOVDQU32Zrm:
5730 case X86::VMOVDQA64Zrm:
5731 case X86::VMOVDQU64Zrm:
5732 case X86::KMOVBkm:
5733 case X86::KMOVWkm:
5734 case X86::KMOVDkm:
5735 case X86::KMOVQkm:
5736 break;
5737 }
5738 switch (Opc2) {
5739 default: return false;
5740 case X86::MOV8rm:
5741 case X86::MOV16rm:
5742 case X86::MOV32rm:
5743 case X86::MOV64rm:
5744 case X86::LD_Fp32m:
5745 case X86::LD_Fp64m:
5746 case X86::LD_Fp80m:
5747 case X86::MOVSSrm:
5748 case X86::MOVSDrm:
5749 case X86::MMX_MOVD64rm:
5750 case X86::MMX_MOVQ64rm:
5751 case X86::MOVAPSrm:
5752 case X86::MOVUPSrm:
5753 case X86::MOVAPDrm: