Bug Summary

File:lib/Target/X86/X86MCInstLower.cpp
Warning:line 770, column 3
Value stored to 'Opc' is never read

Annotated Source Code

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clang -cc1 -triple x86_64-pc-linux-gnu -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name X86MCInstLower.cpp -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=cplusplus -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -analyzer-config-compatibility-mode=true -mrelocation-model pic -pic-level 2 -mthread-model posix -fmath-errno -masm-verbose -mconstructor-aliases -munwind-tables -fuse-init-array -target-cpu x86-64 -dwarf-column-info -debugger-tuning=gdb -momit-leaf-frame-pointer -ffunction-sections -fdata-sections -resource-dir /usr/lib/llvm-9/lib/clang/9.0.0 -D _DEBUG -D _GNU_SOURCE -D __STDC_CONSTANT_MACROS -D __STDC_FORMAT_MACROS -D __STDC_LIMIT_MACROS -I /build/llvm-toolchain-snapshot-9~svn358520/build-llvm/lib/Target/X86 -I /build/llvm-toolchain-snapshot-9~svn358520/lib/Target/X86 -I /build/llvm-toolchain-snapshot-9~svn358520/build-llvm/include -I /build/llvm-toolchain-snapshot-9~svn358520/include -U NDEBUG -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/x86_64-linux-gnu/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/x86_64-linux-gnu/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/c++/6.3.0/backward -internal-isystem /usr/include/clang/9.0.0/include/ -internal-isystem /usr/local/include -internal-isystem /usr/lib/llvm-9/lib/clang/9.0.0/include -internal-externc-isystem /usr/include/x86_64-linux-gnu -internal-externc-isystem /include -internal-externc-isystem /usr/include -O2 -Wno-unused-parameter -Wwrite-strings -Wno-missing-field-initializers -Wno-long-long -Wno-maybe-uninitialized -Wno-comment -std=c++11 -fdeprecated-macro -fdebug-compilation-dir /build/llvm-toolchain-snapshot-9~svn358520/build-llvm/lib/Target/X86 -fdebug-prefix-map=/build/llvm-toolchain-snapshot-9~svn358520=. -ferror-limit 19 -fmessage-length 0 -fvisibility-inlines-hidden -stack-protector 2 -fobjc-runtime=gcc -fdiagnostics-show-option -vectorize-loops -vectorize-slp -analyzer-output=html -analyzer-config stable-report-filename=true -o /tmp/scan-build-2019-04-17-050842-1547-1 -x c++ /build/llvm-toolchain-snapshot-9~svn358520/lib/Target/X86/X86MCInstLower.cpp -faddrsig
1//===-- X86MCInstLower.cpp - Convert X86 MachineInstr to an MCInst --------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains code to lower X86 MachineInstrs to their corresponding
10// MCInst records.
11//
12//===----------------------------------------------------------------------===//
13
14#include "InstPrinter/X86ATTInstPrinter.h"
15#include "InstPrinter/X86InstComments.h"
16#include "MCTargetDesc/X86BaseInfo.h"
17#include "MCTargetDesc/X86TargetStreamer.h"
18#include "Utils/X86ShuffleDecode.h"
19#include "X86AsmPrinter.h"
20#include "X86RegisterInfo.h"
21#include "X86ShuffleDecodeConstantPool.h"
22#include "llvm/ADT/Optional.h"
23#include "llvm/ADT/SmallString.h"
24#include "llvm/ADT/iterator_range.h"
25#include "llvm/CodeGen/MachineConstantPool.h"
26#include "llvm/CodeGen/MachineFunction.h"
27#include "llvm/CodeGen/MachineModuleInfoImpls.h"
28#include "llvm/CodeGen/MachineOperand.h"
29#include "llvm/CodeGen/StackMaps.h"
30#include "llvm/IR/DataLayout.h"
31#include "llvm/IR/GlobalValue.h"
32#include "llvm/IR/Mangler.h"
33#include "llvm/MC/MCAsmInfo.h"
34#include "llvm/MC/MCCodeEmitter.h"
35#include "llvm/MC/MCContext.h"
36#include "llvm/MC/MCExpr.h"
37#include "llvm/MC/MCFixup.h"
38#include "llvm/MC/MCInst.h"
39#include "llvm/MC/MCInstBuilder.h"
40#include "llvm/MC/MCSection.h"
41#include "llvm/MC/MCSectionELF.h"
42#include "llvm/MC/MCStreamer.h"
43#include "llvm/MC/MCSymbol.h"
44#include "llvm/MC/MCSymbolELF.h"
45#include "llvm/Target/TargetLoweringObjectFile.h"
46
47using namespace llvm;
48
49namespace {
50
51/// X86MCInstLower - This class is used to lower an MachineInstr into an MCInst.
52class X86MCInstLower {
53 MCContext &Ctx;
54 const MachineFunction &MF;
55 const TargetMachine &TM;
56 const MCAsmInfo &MAI;
57 X86AsmPrinter &AsmPrinter;
58
59public:
60 X86MCInstLower(const MachineFunction &MF, X86AsmPrinter &asmprinter);
61
62 Optional<MCOperand> LowerMachineOperand(const MachineInstr *MI,
63 const MachineOperand &MO) const;
64 void Lower(const MachineInstr *MI, MCInst &OutMI) const;
65
66 MCSymbol *GetSymbolFromOperand(const MachineOperand &MO) const;
67 MCOperand LowerSymbolOperand(const MachineOperand &MO, MCSymbol *Sym) const;
68
69private:
70 MachineModuleInfoMachO &getMachOMMI() const;
71};
72
73} // end anonymous namespace
74
75// Emit a minimal sequence of nops spanning NumBytes bytes.
76static void EmitNops(MCStreamer &OS, unsigned NumBytes, bool Is64Bit,
77 const MCSubtargetInfo &STI);
78
79void X86AsmPrinter::StackMapShadowTracker::count(MCInst &Inst,
80 const MCSubtargetInfo &STI,
81 MCCodeEmitter *CodeEmitter) {
82 if (InShadow) {
83 SmallString<256> Code;
84 SmallVector<MCFixup, 4> Fixups;
85 raw_svector_ostream VecOS(Code);
86 CodeEmitter->encodeInstruction(Inst, VecOS, Fixups, STI);
87 CurrentShadowSize += Code.size();
88 if (CurrentShadowSize >= RequiredShadowSize)
89 InShadow = false; // The shadow is big enough. Stop counting.
90 }
91}
92
93void X86AsmPrinter::StackMapShadowTracker::emitShadowPadding(
94 MCStreamer &OutStreamer, const MCSubtargetInfo &STI) {
95 if (InShadow && CurrentShadowSize < RequiredShadowSize) {
96 InShadow = false;
97 EmitNops(OutStreamer, RequiredShadowSize - CurrentShadowSize,
98 MF->getSubtarget<X86Subtarget>().is64Bit(), STI);
99 }
100}
101
102void X86AsmPrinter::EmitAndCountInstruction(MCInst &Inst) {
103 OutStreamer->EmitInstruction(Inst, getSubtargetInfo());
104 SMShadowTracker.count(Inst, getSubtargetInfo(), CodeEmitter.get());
105}
106
107X86MCInstLower::X86MCInstLower(const MachineFunction &mf,
108 X86AsmPrinter &asmprinter)
109 : Ctx(mf.getContext()), MF(mf), TM(mf.getTarget()), MAI(*TM.getMCAsmInfo()),
110 AsmPrinter(asmprinter) {}
111
112MachineModuleInfoMachO &X86MCInstLower::getMachOMMI() const {
113 return MF.getMMI().getObjFileInfo<MachineModuleInfoMachO>();
114}
115
116/// GetSymbolFromOperand - Lower an MO_GlobalAddress or MO_ExternalSymbol
117/// operand to an MCSymbol.
118MCSymbol *X86MCInstLower::GetSymbolFromOperand(const MachineOperand &MO) const {
119 const DataLayout &DL = MF.getDataLayout();
120 assert((MO.isGlobal() || MO.isSymbol() || MO.isMBB()) &&(((MO.isGlobal() || MO.isSymbol() || MO.isMBB()) && "Isn't a symbol reference"
) ? static_cast<void> (0) : __assert_fail ("(MO.isGlobal() || MO.isSymbol() || MO.isMBB()) && \"Isn't a symbol reference\""
, "/build/llvm-toolchain-snapshot-9~svn358520/lib/Target/X86/X86MCInstLower.cpp"
, 121, __PRETTY_FUNCTION__))
121 "Isn't a symbol reference")(((MO.isGlobal() || MO.isSymbol() || MO.isMBB()) && "Isn't a symbol reference"
) ? static_cast<void> (0) : __assert_fail ("(MO.isGlobal() || MO.isSymbol() || MO.isMBB()) && \"Isn't a symbol reference\""
, "/build/llvm-toolchain-snapshot-9~svn358520/lib/Target/X86/X86MCInstLower.cpp"
, 121, __PRETTY_FUNCTION__))
;
122
123 MCSymbol *Sym = nullptr;
124 SmallString<128> Name;
125 StringRef Suffix;
126
127 switch (MO.getTargetFlags()) {
128 case X86II::MO_DLLIMPORT:
129 // Handle dllimport linkage.
130 Name += "__imp_";
131 break;
132 case X86II::MO_COFFSTUB:
133 Name += ".refptr.";
134 break;
135 case X86II::MO_DARWIN_NONLAZY:
136 case X86II::MO_DARWIN_NONLAZY_PIC_BASE:
137 Suffix = "$non_lazy_ptr";
138 break;
139 }
140
141 if (!Suffix.empty())
142 Name += DL.getPrivateGlobalPrefix();
143
144 if (MO.isGlobal()) {
145 const GlobalValue *GV = MO.getGlobal();
146 AsmPrinter.getNameWithPrefix(Name, GV);
147 } else if (MO.isSymbol()) {
148 Mangler::getNameWithPrefix(Name, MO.getSymbolName(), DL);
149 } else if (MO.isMBB()) {
150 assert(Suffix.empty())((Suffix.empty()) ? static_cast<void> (0) : __assert_fail
("Suffix.empty()", "/build/llvm-toolchain-snapshot-9~svn358520/lib/Target/X86/X86MCInstLower.cpp"
, 150, __PRETTY_FUNCTION__))
;
151 Sym = MO.getMBB()->getSymbol();
152 }
153
154 Name += Suffix;
155 if (!Sym)
156 Sym = Ctx.getOrCreateSymbol(Name);
157
158 // If the target flags on the operand changes the name of the symbol, do that
159 // before we return the symbol.
160 switch (MO.getTargetFlags()) {
161 default:
162 break;
163 case X86II::MO_COFFSTUB: {
164 MachineModuleInfoCOFF &MMICOFF =
165 MF.getMMI().getObjFileInfo<MachineModuleInfoCOFF>();
166 MachineModuleInfoImpl::StubValueTy &StubSym = MMICOFF.getGVStubEntry(Sym);
167 if (!StubSym.getPointer()) {
168 assert(MO.isGlobal() && "Extern symbol not handled yet")((MO.isGlobal() && "Extern symbol not handled yet") ?
static_cast<void> (0) : __assert_fail ("MO.isGlobal() && \"Extern symbol not handled yet\""
, "/build/llvm-toolchain-snapshot-9~svn358520/lib/Target/X86/X86MCInstLower.cpp"
, 168, __PRETTY_FUNCTION__))
;
169 StubSym = MachineModuleInfoImpl::StubValueTy(
170 AsmPrinter.getSymbol(MO.getGlobal()), true);
171 }
172 break;
173 }
174 case X86II::MO_DARWIN_NONLAZY:
175 case X86II::MO_DARWIN_NONLAZY_PIC_BASE: {
176 MachineModuleInfoImpl::StubValueTy &StubSym =
177 getMachOMMI().getGVStubEntry(Sym);
178 if (!StubSym.getPointer()) {
179 assert(MO.isGlobal() && "Extern symbol not handled yet")((MO.isGlobal() && "Extern symbol not handled yet") ?
static_cast<void> (0) : __assert_fail ("MO.isGlobal() && \"Extern symbol not handled yet\""
, "/build/llvm-toolchain-snapshot-9~svn358520/lib/Target/X86/X86MCInstLower.cpp"
, 179, __PRETTY_FUNCTION__))
;
180 StubSym = MachineModuleInfoImpl::StubValueTy(
181 AsmPrinter.getSymbol(MO.getGlobal()),
182 !MO.getGlobal()->hasInternalLinkage());
183 }
184 break;
185 }
186 }
187
188 return Sym;
189}
190
191MCOperand X86MCInstLower::LowerSymbolOperand(const MachineOperand &MO,
192 MCSymbol *Sym) const {
193 // FIXME: We would like an efficient form for this, so we don't have to do a
194 // lot of extra uniquing.
195 const MCExpr *Expr = nullptr;
196 MCSymbolRefExpr::VariantKind RefKind = MCSymbolRefExpr::VK_None;
197
198 switch (MO.getTargetFlags()) {
199 default:
200 llvm_unreachable("Unknown target flag on GV operand")::llvm::llvm_unreachable_internal("Unknown target flag on GV operand"
, "/build/llvm-toolchain-snapshot-9~svn358520/lib/Target/X86/X86MCInstLower.cpp"
, 200)
;
201 case X86II::MO_NO_FLAG: // No flag.
202 // These affect the name of the symbol, not any suffix.
203 case X86II::MO_DARWIN_NONLAZY:
204 case X86II::MO_DLLIMPORT:
205 case X86II::MO_COFFSTUB:
206 break;
207
208 case X86II::MO_TLVP:
209 RefKind = MCSymbolRefExpr::VK_TLVP;
210 break;
211 case X86II::MO_TLVP_PIC_BASE:
212 Expr = MCSymbolRefExpr::create(Sym, MCSymbolRefExpr::VK_TLVP, Ctx);
213 // Subtract the pic base.
214 Expr = MCBinaryExpr::createSub(
215 Expr, MCSymbolRefExpr::create(MF.getPICBaseSymbol(), Ctx), Ctx);
216 break;
217 case X86II::MO_SECREL:
218 RefKind = MCSymbolRefExpr::VK_SECREL;
219 break;
220 case X86II::MO_TLSGD:
221 RefKind = MCSymbolRefExpr::VK_TLSGD;
222 break;
223 case X86II::MO_TLSLD:
224 RefKind = MCSymbolRefExpr::VK_TLSLD;
225 break;
226 case X86II::MO_TLSLDM:
227 RefKind = MCSymbolRefExpr::VK_TLSLDM;
228 break;
229 case X86II::MO_GOTTPOFF:
230 RefKind = MCSymbolRefExpr::VK_GOTTPOFF;
231 break;
232 case X86II::MO_INDNTPOFF:
233 RefKind = MCSymbolRefExpr::VK_INDNTPOFF;
234 break;
235 case X86II::MO_TPOFF:
236 RefKind = MCSymbolRefExpr::VK_TPOFF;
237 break;
238 case X86II::MO_DTPOFF:
239 RefKind = MCSymbolRefExpr::VK_DTPOFF;
240 break;
241 case X86II::MO_NTPOFF:
242 RefKind = MCSymbolRefExpr::VK_NTPOFF;
243 break;
244 case X86II::MO_GOTNTPOFF:
245 RefKind = MCSymbolRefExpr::VK_GOTNTPOFF;
246 break;
247 case X86II::MO_GOTPCREL:
248 RefKind = MCSymbolRefExpr::VK_GOTPCREL;
249 break;
250 case X86II::MO_GOT:
251 RefKind = MCSymbolRefExpr::VK_GOT;
252 break;
253 case X86II::MO_GOTOFF:
254 RefKind = MCSymbolRefExpr::VK_GOTOFF;
255 break;
256 case X86II::MO_PLT:
257 RefKind = MCSymbolRefExpr::VK_PLT;
258 break;
259 case X86II::MO_ABS8:
260 RefKind = MCSymbolRefExpr::VK_X86_ABS8;
261 break;
262 case X86II::MO_PIC_BASE_OFFSET:
263 case X86II::MO_DARWIN_NONLAZY_PIC_BASE:
264 Expr = MCSymbolRefExpr::create(Sym, Ctx);
265 // Subtract the pic base.
266 Expr = MCBinaryExpr::createSub(
267 Expr, MCSymbolRefExpr::create(MF.getPICBaseSymbol(), Ctx), Ctx);
268 if (MO.isJTI()) {
269 assert(MAI.doesSetDirectiveSuppressReloc())((MAI.doesSetDirectiveSuppressReloc()) ? static_cast<void>
(0) : __assert_fail ("MAI.doesSetDirectiveSuppressReloc()", "/build/llvm-toolchain-snapshot-9~svn358520/lib/Target/X86/X86MCInstLower.cpp"
, 269, __PRETTY_FUNCTION__))
;
270 // If .set directive is supported, use it to reduce the number of
271 // relocations the assembler will generate for differences between
272 // local labels. This is only safe when the symbols are in the same
273 // section so we are restricting it to jumptable references.
274 MCSymbol *Label = Ctx.createTempSymbol();
275 AsmPrinter.OutStreamer->EmitAssignment(Label, Expr);
276 Expr = MCSymbolRefExpr::create(Label, Ctx);
277 }
278 break;
279 }
280
281 if (!Expr)
282 Expr = MCSymbolRefExpr::create(Sym, RefKind, Ctx);
283
284 if (!MO.isJTI() && !MO.isMBB() && MO.getOffset())
285 Expr = MCBinaryExpr::createAdd(
286 Expr, MCConstantExpr::create(MO.getOffset(), Ctx), Ctx);
287 return MCOperand::createExpr(Expr);
288}
289
290/// Simplify FOO $imm, %{al,ax,eax,rax} to FOO $imm, for instruction with
291/// a short fixed-register form.
292static void SimplifyShortImmForm(MCInst &Inst, unsigned Opcode) {
293 unsigned ImmOp = Inst.getNumOperands() - 1;
294 assert(Inst.getOperand(0).isReg() &&((Inst.getOperand(0).isReg() && (Inst.getOperand(ImmOp
).isImm() || Inst.getOperand(ImmOp).isExpr()) && ((Inst
.getNumOperands() == 3 && Inst.getOperand(1).isReg() &&
Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) ||
Inst.getNumOperands() == 2) && "Unexpected instruction!"
) ? static_cast<void> (0) : __assert_fail ("Inst.getOperand(0).isReg() && (Inst.getOperand(ImmOp).isImm() || Inst.getOperand(ImmOp).isExpr()) && ((Inst.getNumOperands() == 3 && Inst.getOperand(1).isReg() && Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) || Inst.getNumOperands() == 2) && \"Unexpected instruction!\""
, "/build/llvm-toolchain-snapshot-9~svn358520/lib/Target/X86/X86MCInstLower.cpp"
, 299, __PRETTY_FUNCTION__))
295 (Inst.getOperand(ImmOp).isImm() || Inst.getOperand(ImmOp).isExpr()) &&((Inst.getOperand(0).isReg() && (Inst.getOperand(ImmOp
).isImm() || Inst.getOperand(ImmOp).isExpr()) && ((Inst
.getNumOperands() == 3 && Inst.getOperand(1).isReg() &&
Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) ||
Inst.getNumOperands() == 2) && "Unexpected instruction!"
) ? static_cast<void> (0) : __assert_fail ("Inst.getOperand(0).isReg() && (Inst.getOperand(ImmOp).isImm() || Inst.getOperand(ImmOp).isExpr()) && ((Inst.getNumOperands() == 3 && Inst.getOperand(1).isReg() && Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) || Inst.getNumOperands() == 2) && \"Unexpected instruction!\""
, "/build/llvm-toolchain-snapshot-9~svn358520/lib/Target/X86/X86MCInstLower.cpp"
, 299, __PRETTY_FUNCTION__))
296 ((Inst.getNumOperands() == 3 && Inst.getOperand(1).isReg() &&((Inst.getOperand(0).isReg() && (Inst.getOperand(ImmOp
).isImm() || Inst.getOperand(ImmOp).isExpr()) && ((Inst
.getNumOperands() == 3 && Inst.getOperand(1).isReg() &&
Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) ||
Inst.getNumOperands() == 2) && "Unexpected instruction!"
) ? static_cast<void> (0) : __assert_fail ("Inst.getOperand(0).isReg() && (Inst.getOperand(ImmOp).isImm() || Inst.getOperand(ImmOp).isExpr()) && ((Inst.getNumOperands() == 3 && Inst.getOperand(1).isReg() && Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) || Inst.getNumOperands() == 2) && \"Unexpected instruction!\""
, "/build/llvm-toolchain-snapshot-9~svn358520/lib/Target/X86/X86MCInstLower.cpp"
, 299, __PRETTY_FUNCTION__))
297 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) ||((Inst.getOperand(0).isReg() && (Inst.getOperand(ImmOp
).isImm() || Inst.getOperand(ImmOp).isExpr()) && ((Inst
.getNumOperands() == 3 && Inst.getOperand(1).isReg() &&
Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) ||
Inst.getNumOperands() == 2) && "Unexpected instruction!"
) ? static_cast<void> (0) : __assert_fail ("Inst.getOperand(0).isReg() && (Inst.getOperand(ImmOp).isImm() || Inst.getOperand(ImmOp).isExpr()) && ((Inst.getNumOperands() == 3 && Inst.getOperand(1).isReg() && Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) || Inst.getNumOperands() == 2) && \"Unexpected instruction!\""
, "/build/llvm-toolchain-snapshot-9~svn358520/lib/Target/X86/X86MCInstLower.cpp"
, 299, __PRETTY_FUNCTION__))
298 Inst.getNumOperands() == 2) &&((Inst.getOperand(0).isReg() && (Inst.getOperand(ImmOp
).isImm() || Inst.getOperand(ImmOp).isExpr()) && ((Inst
.getNumOperands() == 3 && Inst.getOperand(1).isReg() &&
Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) ||
Inst.getNumOperands() == 2) && "Unexpected instruction!"
) ? static_cast<void> (0) : __assert_fail ("Inst.getOperand(0).isReg() && (Inst.getOperand(ImmOp).isImm() || Inst.getOperand(ImmOp).isExpr()) && ((Inst.getNumOperands() == 3 && Inst.getOperand(1).isReg() && Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) || Inst.getNumOperands() == 2) && \"Unexpected instruction!\""
, "/build/llvm-toolchain-snapshot-9~svn358520/lib/Target/X86/X86MCInstLower.cpp"
, 299, __PRETTY_FUNCTION__))
299 "Unexpected instruction!")((Inst.getOperand(0).isReg() && (Inst.getOperand(ImmOp
).isImm() || Inst.getOperand(ImmOp).isExpr()) && ((Inst
.getNumOperands() == 3 && Inst.getOperand(1).isReg() &&
Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) ||
Inst.getNumOperands() == 2) && "Unexpected instruction!"
) ? static_cast<void> (0) : __assert_fail ("Inst.getOperand(0).isReg() && (Inst.getOperand(ImmOp).isImm() || Inst.getOperand(ImmOp).isExpr()) && ((Inst.getNumOperands() == 3 && Inst.getOperand(1).isReg() && Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) || Inst.getNumOperands() == 2) && \"Unexpected instruction!\""
, "/build/llvm-toolchain-snapshot-9~svn358520/lib/Target/X86/X86MCInstLower.cpp"
, 299, __PRETTY_FUNCTION__))
;
300
301 // Check whether the destination register can be fixed.
302 unsigned Reg = Inst.getOperand(0).getReg();
303 if (Reg != X86::AL && Reg != X86::AX && Reg != X86::EAX && Reg != X86::RAX)
304 return;
305
306 // If so, rewrite the instruction.
307 MCOperand Saved = Inst.getOperand(ImmOp);
308 Inst = MCInst();
309 Inst.setOpcode(Opcode);
310 Inst.addOperand(Saved);
311}
312
313/// If a movsx instruction has a shorter encoding for the used register
314/// simplify the instruction to use it instead.
315static void SimplifyMOVSX(MCInst &Inst) {
316 unsigned NewOpcode = 0;
317 unsigned Op0 = Inst.getOperand(0).getReg(), Op1 = Inst.getOperand(1).getReg();
318 switch (Inst.getOpcode()) {
319 default:
320 llvm_unreachable("Unexpected instruction!")::llvm::llvm_unreachable_internal("Unexpected instruction!", "/build/llvm-toolchain-snapshot-9~svn358520/lib/Target/X86/X86MCInstLower.cpp"
, 320)
;
321 case X86::MOVSX16rr8: // movsbw %al, %ax --> cbtw
322 if (Op0 == X86::AX && Op1 == X86::AL)
323 NewOpcode = X86::CBW;
324 break;
325 case X86::MOVSX32rr16: // movswl %ax, %eax --> cwtl
326 if (Op0 == X86::EAX && Op1 == X86::AX)
327 NewOpcode = X86::CWDE;
328 break;
329 case X86::MOVSX64rr32: // movslq %eax, %rax --> cltq
330 if (Op0 == X86::RAX && Op1 == X86::EAX)
331 NewOpcode = X86::CDQE;
332 break;
333 }
334
335 if (NewOpcode != 0) {
336 Inst = MCInst();
337 Inst.setOpcode(NewOpcode);
338 }
339}
340
341/// Simplify things like MOV32rm to MOV32o32a.
342static void SimplifyShortMoveForm(X86AsmPrinter &Printer, MCInst &Inst,
343 unsigned Opcode) {
344 // Don't make these simplifications in 64-bit mode; other assemblers don't
345 // perform them because they make the code larger.
346 if (Printer.getSubtarget().is64Bit())
347 return;
348
349 bool IsStore = Inst.getOperand(0).isReg() && Inst.getOperand(1).isReg();
350 unsigned AddrBase = IsStore;
351 unsigned RegOp = IsStore ? 0 : 5;
352 unsigned AddrOp = AddrBase + 3;
353 assert(((Inst.getNumOperands() == 6 && Inst.getOperand(RegOp
).isReg() && Inst.getOperand(AddrBase + X86::AddrBaseReg
).isReg() && Inst.getOperand(AddrBase + X86::AddrScaleAmt
).isImm() && Inst.getOperand(AddrBase + X86::AddrIndexReg
).isReg() && Inst.getOperand(AddrBase + X86::AddrSegmentReg
).isReg() && (Inst.getOperand(AddrOp).isExpr() || Inst
.getOperand(AddrOp).isImm()) && "Unexpected instruction!"
) ? static_cast<void> (0) : __assert_fail ("Inst.getNumOperands() == 6 && Inst.getOperand(RegOp).isReg() && Inst.getOperand(AddrBase + X86::AddrBaseReg).isReg() && Inst.getOperand(AddrBase + X86::AddrScaleAmt).isImm() && Inst.getOperand(AddrBase + X86::AddrIndexReg).isReg() && Inst.getOperand(AddrBase + X86::AddrSegmentReg).isReg() && (Inst.getOperand(AddrOp).isExpr() || Inst.getOperand(AddrOp).isImm()) && \"Unexpected instruction!\""
, "/build/llvm-toolchain-snapshot-9~svn358520/lib/Target/X86/X86MCInstLower.cpp"
, 360, __PRETTY_FUNCTION__))
354 Inst.getNumOperands() == 6 && Inst.getOperand(RegOp).isReg() &&((Inst.getNumOperands() == 6 && Inst.getOperand(RegOp
).isReg() && Inst.getOperand(AddrBase + X86::AddrBaseReg
).isReg() && Inst.getOperand(AddrBase + X86::AddrScaleAmt
).isImm() && Inst.getOperand(AddrBase + X86::AddrIndexReg
).isReg() && Inst.getOperand(AddrBase + X86::AddrSegmentReg
).isReg() && (Inst.getOperand(AddrOp).isExpr() || Inst
.getOperand(AddrOp).isImm()) && "Unexpected instruction!"
) ? static_cast<void> (0) : __assert_fail ("Inst.getNumOperands() == 6 && Inst.getOperand(RegOp).isReg() && Inst.getOperand(AddrBase + X86::AddrBaseReg).isReg() && Inst.getOperand(AddrBase + X86::AddrScaleAmt).isImm() && Inst.getOperand(AddrBase + X86::AddrIndexReg).isReg() && Inst.getOperand(AddrBase + X86::AddrSegmentReg).isReg() && (Inst.getOperand(AddrOp).isExpr() || Inst.getOperand(AddrOp).isImm()) && \"Unexpected instruction!\""
, "/build/llvm-toolchain-snapshot-9~svn358520/lib/Target/X86/X86MCInstLower.cpp"
, 360, __PRETTY_FUNCTION__))
355 Inst.getOperand(AddrBase + X86::AddrBaseReg).isReg() &&((Inst.getNumOperands() == 6 && Inst.getOperand(RegOp
).isReg() && Inst.getOperand(AddrBase + X86::AddrBaseReg
).isReg() && Inst.getOperand(AddrBase + X86::AddrScaleAmt
).isImm() && Inst.getOperand(AddrBase + X86::AddrIndexReg
).isReg() && Inst.getOperand(AddrBase + X86::AddrSegmentReg
).isReg() && (Inst.getOperand(AddrOp).isExpr() || Inst
.getOperand(AddrOp).isImm()) && "Unexpected instruction!"
) ? static_cast<void> (0) : __assert_fail ("Inst.getNumOperands() == 6 && Inst.getOperand(RegOp).isReg() && Inst.getOperand(AddrBase + X86::AddrBaseReg).isReg() && Inst.getOperand(AddrBase + X86::AddrScaleAmt).isImm() && Inst.getOperand(AddrBase + X86::AddrIndexReg).isReg() && Inst.getOperand(AddrBase + X86::AddrSegmentReg).isReg() && (Inst.getOperand(AddrOp).isExpr() || Inst.getOperand(AddrOp).isImm()) && \"Unexpected instruction!\""
, "/build/llvm-toolchain-snapshot-9~svn358520/lib/Target/X86/X86MCInstLower.cpp"
, 360, __PRETTY_FUNCTION__))
356 Inst.getOperand(AddrBase + X86::AddrScaleAmt).isImm() &&((Inst.getNumOperands() == 6 && Inst.getOperand(RegOp
).isReg() && Inst.getOperand(AddrBase + X86::AddrBaseReg
).isReg() && Inst.getOperand(AddrBase + X86::AddrScaleAmt
).isImm() && Inst.getOperand(AddrBase + X86::AddrIndexReg
).isReg() && Inst.getOperand(AddrBase + X86::AddrSegmentReg
).isReg() && (Inst.getOperand(AddrOp).isExpr() || Inst
.getOperand(AddrOp).isImm()) && "Unexpected instruction!"
) ? static_cast<void> (0) : __assert_fail ("Inst.getNumOperands() == 6 && Inst.getOperand(RegOp).isReg() && Inst.getOperand(AddrBase + X86::AddrBaseReg).isReg() && Inst.getOperand(AddrBase + X86::AddrScaleAmt).isImm() && Inst.getOperand(AddrBase + X86::AddrIndexReg).isReg() && Inst.getOperand(AddrBase + X86::AddrSegmentReg).isReg() && (Inst.getOperand(AddrOp).isExpr() || Inst.getOperand(AddrOp).isImm()) && \"Unexpected instruction!\""
, "/build/llvm-toolchain-snapshot-9~svn358520/lib/Target/X86/X86MCInstLower.cpp"
, 360, __PRETTY_FUNCTION__))
357 Inst.getOperand(AddrBase + X86::AddrIndexReg).isReg() &&((Inst.getNumOperands() == 6 && Inst.getOperand(RegOp
).isReg() && Inst.getOperand(AddrBase + X86::AddrBaseReg
).isReg() && Inst.getOperand(AddrBase + X86::AddrScaleAmt
).isImm() && Inst.getOperand(AddrBase + X86::AddrIndexReg
).isReg() && Inst.getOperand(AddrBase + X86::AddrSegmentReg
).isReg() && (Inst.getOperand(AddrOp).isExpr() || Inst
.getOperand(AddrOp).isImm()) && "Unexpected instruction!"
) ? static_cast<void> (0) : __assert_fail ("Inst.getNumOperands() == 6 && Inst.getOperand(RegOp).isReg() && Inst.getOperand(AddrBase + X86::AddrBaseReg).isReg() && Inst.getOperand(AddrBase + X86::AddrScaleAmt).isImm() && Inst.getOperand(AddrBase + X86::AddrIndexReg).isReg() && Inst.getOperand(AddrBase + X86::AddrSegmentReg).isReg() && (Inst.getOperand(AddrOp).isExpr() || Inst.getOperand(AddrOp).isImm()) && \"Unexpected instruction!\""
, "/build/llvm-toolchain-snapshot-9~svn358520/lib/Target/X86/X86MCInstLower.cpp"
, 360, __PRETTY_FUNCTION__))
358 Inst.getOperand(AddrBase + X86::AddrSegmentReg).isReg() &&((Inst.getNumOperands() == 6 && Inst.getOperand(RegOp
).isReg() && Inst.getOperand(AddrBase + X86::AddrBaseReg
).isReg() && Inst.getOperand(AddrBase + X86::AddrScaleAmt
).isImm() && Inst.getOperand(AddrBase + X86::AddrIndexReg
).isReg() && Inst.getOperand(AddrBase + X86::AddrSegmentReg
).isReg() && (Inst.getOperand(AddrOp).isExpr() || Inst
.getOperand(AddrOp).isImm()) && "Unexpected instruction!"
) ? static_cast<void> (0) : __assert_fail ("Inst.getNumOperands() == 6 && Inst.getOperand(RegOp).isReg() && Inst.getOperand(AddrBase + X86::AddrBaseReg).isReg() && Inst.getOperand(AddrBase + X86::AddrScaleAmt).isImm() && Inst.getOperand(AddrBase + X86::AddrIndexReg).isReg() && Inst.getOperand(AddrBase + X86::AddrSegmentReg).isReg() && (Inst.getOperand(AddrOp).isExpr() || Inst.getOperand(AddrOp).isImm()) && \"Unexpected instruction!\""
, "/build/llvm-toolchain-snapshot-9~svn358520/lib/Target/X86/X86MCInstLower.cpp"
, 360, __PRETTY_FUNCTION__))
359 (Inst.getOperand(AddrOp).isExpr() || Inst.getOperand(AddrOp).isImm()) &&((Inst.getNumOperands() == 6 && Inst.getOperand(RegOp
).isReg() && Inst.getOperand(AddrBase + X86::AddrBaseReg
).isReg() && Inst.getOperand(AddrBase + X86::AddrScaleAmt
).isImm() && Inst.getOperand(AddrBase + X86::AddrIndexReg
).isReg() && Inst.getOperand(AddrBase + X86::AddrSegmentReg
).isReg() && (Inst.getOperand(AddrOp).isExpr() || Inst
.getOperand(AddrOp).isImm()) && "Unexpected instruction!"
) ? static_cast<void> (0) : __assert_fail ("Inst.getNumOperands() == 6 && Inst.getOperand(RegOp).isReg() && Inst.getOperand(AddrBase + X86::AddrBaseReg).isReg() && Inst.getOperand(AddrBase + X86::AddrScaleAmt).isImm() && Inst.getOperand(AddrBase + X86::AddrIndexReg).isReg() && Inst.getOperand(AddrBase + X86::AddrSegmentReg).isReg() && (Inst.getOperand(AddrOp).isExpr() || Inst.getOperand(AddrOp).isImm()) && \"Unexpected instruction!\""
, "/build/llvm-toolchain-snapshot-9~svn358520/lib/Target/X86/X86MCInstLower.cpp"
, 360, __PRETTY_FUNCTION__))
360 "Unexpected instruction!")((Inst.getNumOperands() == 6 && Inst.getOperand(RegOp
).isReg() && Inst.getOperand(AddrBase + X86::AddrBaseReg
).isReg() && Inst.getOperand(AddrBase + X86::AddrScaleAmt
).isImm() && Inst.getOperand(AddrBase + X86::AddrIndexReg
).isReg() && Inst.getOperand(AddrBase + X86::AddrSegmentReg
).isReg() && (Inst.getOperand(AddrOp).isExpr() || Inst
.getOperand(AddrOp).isImm()) && "Unexpected instruction!"
) ? static_cast<void> (0) : __assert_fail ("Inst.getNumOperands() == 6 && Inst.getOperand(RegOp).isReg() && Inst.getOperand(AddrBase + X86::AddrBaseReg).isReg() && Inst.getOperand(AddrBase + X86::AddrScaleAmt).isImm() && Inst.getOperand(AddrBase + X86::AddrIndexReg).isReg() && Inst.getOperand(AddrBase + X86::AddrSegmentReg).isReg() && (Inst.getOperand(AddrOp).isExpr() || Inst.getOperand(AddrOp).isImm()) && \"Unexpected instruction!\""
, "/build/llvm-toolchain-snapshot-9~svn358520/lib/Target/X86/X86MCInstLower.cpp"
, 360, __PRETTY_FUNCTION__))
;
361
362 // Check whether the destination register can be fixed.
363 unsigned Reg = Inst.getOperand(RegOp).getReg();
364 if (Reg != X86::AL && Reg != X86::AX && Reg != X86::EAX && Reg != X86::RAX)
365 return;
366
367 // Check whether this is an absolute address.
368 // FIXME: We know TLVP symbol refs aren't, but there should be a better way
369 // to do this here.
370 bool Absolute = true;
371 if (Inst.getOperand(AddrOp).isExpr()) {
372 const MCExpr *MCE = Inst.getOperand(AddrOp).getExpr();
373 if (const MCSymbolRefExpr *SRE = dyn_cast<MCSymbolRefExpr>(MCE))
374 if (SRE->getKind() == MCSymbolRefExpr::VK_TLVP)
375 Absolute = false;
376 }
377
378 if (Absolute &&
379 (Inst.getOperand(AddrBase + X86::AddrBaseReg).getReg() != 0 ||
380 Inst.getOperand(AddrBase + X86::AddrScaleAmt).getImm() != 1 ||
381 Inst.getOperand(AddrBase + X86::AddrIndexReg).getReg() != 0))
382 return;
383
384 // If so, rewrite the instruction.
385 MCOperand Saved = Inst.getOperand(AddrOp);
386 MCOperand Seg = Inst.getOperand(AddrBase + X86::AddrSegmentReg);
387 Inst = MCInst();
388 Inst.setOpcode(Opcode);
389 Inst.addOperand(Saved);
390 Inst.addOperand(Seg);
391}
392
393static unsigned getRetOpcode(const X86Subtarget &Subtarget) {
394 return Subtarget.is64Bit() ? X86::RETQ : X86::RETL;
395}
396
397Optional<MCOperand>
398X86MCInstLower::LowerMachineOperand(const MachineInstr *MI,
399 const MachineOperand &MO) const {
400 switch (MO.getType()) {
401 default:
402 MI->print(errs());
403 llvm_unreachable("unknown operand type")::llvm::llvm_unreachable_internal("unknown operand type", "/build/llvm-toolchain-snapshot-9~svn358520/lib/Target/X86/X86MCInstLower.cpp"
, 403)
;
404 case MachineOperand::MO_Register:
405 // Ignore all implicit register operands.
406 if (MO.isImplicit())
407 return None;
408 return MCOperand::createReg(MO.getReg());
409 case MachineOperand::MO_Immediate:
410 return MCOperand::createImm(MO.getImm());
411 case MachineOperand::MO_MachineBasicBlock:
412 case MachineOperand::MO_GlobalAddress:
413 case MachineOperand::MO_ExternalSymbol:
414 return LowerSymbolOperand(MO, GetSymbolFromOperand(MO));
415 case MachineOperand::MO_MCSymbol:
416 return LowerSymbolOperand(MO, MO.getMCSymbol());
417 case MachineOperand::MO_JumpTableIndex:
418 return LowerSymbolOperand(MO, AsmPrinter.GetJTISymbol(MO.getIndex()));
419 case MachineOperand::MO_ConstantPoolIndex:
420 return LowerSymbolOperand(MO, AsmPrinter.GetCPISymbol(MO.getIndex()));
421 case MachineOperand::MO_BlockAddress:
422 return LowerSymbolOperand(
423 MO, AsmPrinter.GetBlockAddressSymbol(MO.getBlockAddress()));
424 case MachineOperand::MO_RegisterMask:
425 // Ignore call clobbers.
426 return None;
427 }
428}
429
430void X86MCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const {
431 OutMI.setOpcode(MI->getOpcode());
432
433 for (const MachineOperand &MO : MI->operands())
434 if (auto MaybeMCOp = LowerMachineOperand(MI, MO))
435 OutMI.addOperand(MaybeMCOp.getValue());
436
437 // Handle a few special cases to eliminate operand modifiers.
438 switch (OutMI.getOpcode()) {
439 case X86::LEA64_32r:
440 case X86::LEA64r:
441 case X86::LEA16r:
442 case X86::LEA32r:
443 // LEA should have a segment register, but it must be empty.
444 assert(OutMI.getNumOperands() == 1 + X86::AddrNumOperands &&((OutMI.getNumOperands() == 1 + X86::AddrNumOperands &&
"Unexpected # of LEA operands") ? static_cast<void> (0
) : __assert_fail ("OutMI.getNumOperands() == 1 + X86::AddrNumOperands && \"Unexpected # of LEA operands\""
, "/build/llvm-toolchain-snapshot-9~svn358520/lib/Target/X86/X86MCInstLower.cpp"
, 445, __PRETTY_FUNCTION__))
445 "Unexpected # of LEA operands")((OutMI.getNumOperands() == 1 + X86::AddrNumOperands &&
"Unexpected # of LEA operands") ? static_cast<void> (0
) : __assert_fail ("OutMI.getNumOperands() == 1 + X86::AddrNumOperands && \"Unexpected # of LEA operands\""
, "/build/llvm-toolchain-snapshot-9~svn358520/lib/Target/X86/X86MCInstLower.cpp"
, 445, __PRETTY_FUNCTION__))
;
446 assert(OutMI.getOperand(1 + X86::AddrSegmentReg).getReg() == 0 &&((OutMI.getOperand(1 + X86::AddrSegmentReg).getReg() == 0 &&
"LEA has segment specified!") ? static_cast<void> (0) :
__assert_fail ("OutMI.getOperand(1 + X86::AddrSegmentReg).getReg() == 0 && \"LEA has segment specified!\""
, "/build/llvm-toolchain-snapshot-9~svn358520/lib/Target/X86/X86MCInstLower.cpp"
, 447, __PRETTY_FUNCTION__))
447 "LEA has segment specified!")((OutMI.getOperand(1 + X86::AddrSegmentReg).getReg() == 0 &&
"LEA has segment specified!") ? static_cast<void> (0) :
__assert_fail ("OutMI.getOperand(1 + X86::AddrSegmentReg).getReg() == 0 && \"LEA has segment specified!\""
, "/build/llvm-toolchain-snapshot-9~svn358520/lib/Target/X86/X86MCInstLower.cpp"
, 447, __PRETTY_FUNCTION__))
;
448 break;
449
450 // Commute operands to get a smaller encoding by using VEX.R instead of VEX.B
451 // if one of the registers is extended, but other isn't.
452 case X86::VMOVZPQILo2PQIrr:
453 case X86::VMOVAPDrr:
454 case X86::VMOVAPDYrr:
455 case X86::VMOVAPSrr:
456 case X86::VMOVAPSYrr:
457 case X86::VMOVDQArr:
458 case X86::VMOVDQAYrr:
459 case X86::VMOVDQUrr:
460 case X86::VMOVDQUYrr:
461 case X86::VMOVUPDrr:
462 case X86::VMOVUPDYrr:
463 case X86::VMOVUPSrr:
464 case X86::VMOVUPSYrr: {
465 if (!X86II::isX86_64ExtendedReg(OutMI.getOperand(0).getReg()) &&
466 X86II::isX86_64ExtendedReg(OutMI.getOperand(1).getReg())) {
467 unsigned NewOpc;
468 switch (OutMI.getOpcode()) {
469 default: llvm_unreachable("Invalid opcode")::llvm::llvm_unreachable_internal("Invalid opcode", "/build/llvm-toolchain-snapshot-9~svn358520/lib/Target/X86/X86MCInstLower.cpp"
, 469)
;
470 case X86::VMOVZPQILo2PQIrr: NewOpc = X86::VMOVPQI2QIrr; break;
471 case X86::VMOVAPDrr: NewOpc = X86::VMOVAPDrr_REV; break;
472 case X86::VMOVAPDYrr: NewOpc = X86::VMOVAPDYrr_REV; break;
473 case X86::VMOVAPSrr: NewOpc = X86::VMOVAPSrr_REV; break;
474 case X86::VMOVAPSYrr: NewOpc = X86::VMOVAPSYrr_REV; break;
475 case X86::VMOVDQArr: NewOpc = X86::VMOVDQArr_REV; break;
476 case X86::VMOVDQAYrr: NewOpc = X86::VMOVDQAYrr_REV; break;
477 case X86::VMOVDQUrr: NewOpc = X86::VMOVDQUrr_REV; break;
478 case X86::VMOVDQUYrr: NewOpc = X86::VMOVDQUYrr_REV; break;
479 case X86::VMOVUPDrr: NewOpc = X86::VMOVUPDrr_REV; break;
480 case X86::VMOVUPDYrr: NewOpc = X86::VMOVUPDYrr_REV; break;
481 case X86::VMOVUPSrr: NewOpc = X86::VMOVUPSrr_REV; break;
482 case X86::VMOVUPSYrr: NewOpc = X86::VMOVUPSYrr_REV; break;
483 }
484 OutMI.setOpcode(NewOpc);
485 }
486 break;
487 }
488 case X86::VMOVSDrr:
489 case X86::VMOVSSrr: {
490 if (!X86II::isX86_64ExtendedReg(OutMI.getOperand(0).getReg()) &&
491 X86II::isX86_64ExtendedReg(OutMI.getOperand(2).getReg())) {
492 unsigned NewOpc;
493 switch (OutMI.getOpcode()) {
494 default: llvm_unreachable("Invalid opcode")::llvm::llvm_unreachable_internal("Invalid opcode", "/build/llvm-toolchain-snapshot-9~svn358520/lib/Target/X86/X86MCInstLower.cpp"
, 494)
;
495 case X86::VMOVSDrr: NewOpc = X86::VMOVSDrr_REV; break;
496 case X86::VMOVSSrr: NewOpc = X86::VMOVSSrr_REV; break;
497 }
498 OutMI.setOpcode(NewOpc);
499 }
500 break;
501 }
502
503 // TAILJMPr64, CALL64r, CALL64pcrel32 - These instructions have register
504 // inputs modeled as normal uses instead of implicit uses. As such, truncate
505 // off all but the first operand (the callee). FIXME: Change isel.
506 case X86::TAILJMPr64:
507 case X86::TAILJMPr64_REX:
508 case X86::CALL64r:
509 case X86::CALL64pcrel32: {
510 unsigned Opcode = OutMI.getOpcode();
511 MCOperand Saved = OutMI.getOperand(0);
512 OutMI = MCInst();
513 OutMI.setOpcode(Opcode);
514 OutMI.addOperand(Saved);
515 break;
516 }
517
518 case X86::EH_RETURN:
519 case X86::EH_RETURN64: {
520 OutMI = MCInst();
521 OutMI.setOpcode(getRetOpcode(AsmPrinter.getSubtarget()));
522 break;
523 }
524
525 case X86::CLEANUPRET: {
526 // Replace CLEANUPRET with the appropriate RET.
527 OutMI = MCInst();
528 OutMI.setOpcode(getRetOpcode(AsmPrinter.getSubtarget()));
529 break;
530 }
531
532 case X86::CATCHRET: {
533 // Replace CATCHRET with the appropriate RET.
534 const X86Subtarget &Subtarget = AsmPrinter.getSubtarget();
535 unsigned ReturnReg = Subtarget.is64Bit() ? X86::RAX : X86::EAX;
536 OutMI = MCInst();
537 OutMI.setOpcode(getRetOpcode(Subtarget));
538 OutMI.addOperand(MCOperand::createReg(ReturnReg));
539 break;
540 }
541
542 // TAILJMPd, TAILJMPd64, TailJMPd_cc - Lower to the correct jump
543 // instruction.
544 {
545 unsigned Opcode;
546 case X86::TAILJMPr:
547 Opcode = X86::JMP32r;
548 goto SetTailJmpOpcode;
549 case X86::TAILJMPd:
550 case X86::TAILJMPd64:
551 Opcode = X86::JMP_1;
552 goto SetTailJmpOpcode;
553
554 SetTailJmpOpcode:
555 MCOperand Saved = OutMI.getOperand(0);
556 OutMI = MCInst();
557 OutMI.setOpcode(Opcode);
558 OutMI.addOperand(Saved);
559 break;
560 }
561
562 case X86::TAILJMPd_CC:
563 case X86::TAILJMPd64_CC: {
564 MCOperand Saved = OutMI.getOperand(0);
565 MCOperand Saved2 = OutMI.getOperand(1);
566 OutMI = MCInst();
567 OutMI.setOpcode(X86::JCC_1);
568 OutMI.addOperand(Saved);
569 OutMI.addOperand(Saved2);
570 break;
571 }
572
573 case X86::DEC16r:
574 case X86::DEC32r:
575 case X86::INC16r:
576 case X86::INC32r:
577 // If we aren't in 64-bit mode we can use the 1-byte inc/dec instructions.
578 if (!AsmPrinter.getSubtarget().is64Bit()) {
579 unsigned Opcode;
580 switch (OutMI.getOpcode()) {
581 default: llvm_unreachable("Invalid opcode")::llvm::llvm_unreachable_internal("Invalid opcode", "/build/llvm-toolchain-snapshot-9~svn358520/lib/Target/X86/X86MCInstLower.cpp"
, 581)
;
582 case X86::DEC16r: Opcode = X86::DEC16r_alt; break;
583 case X86::DEC32r: Opcode = X86::DEC32r_alt; break;
584 case X86::INC16r: Opcode = X86::INC16r_alt; break;
585 case X86::INC32r: Opcode = X86::INC32r_alt; break;
586 }
587 OutMI.setOpcode(Opcode);
588 }
589 break;
590
591 // We don't currently select the correct instruction form for instructions
592 // which have a short %eax, etc. form. Handle this by custom lowering, for
593 // now.
594 //
595 // Note, we are currently not handling the following instructions:
596 // MOV64ao8, MOV64o8a
597 // XCHG16ar, XCHG32ar, XCHG64ar
598 case X86::MOV8mr_NOREX:
599 case X86::MOV8mr:
600 case X86::MOV8rm_NOREX:
601 case X86::MOV8rm:
602 case X86::MOV16mr:
603 case X86::MOV16rm:
604 case X86::MOV32mr:
605 case X86::MOV32rm: {
606 unsigned NewOpc;
607 switch (OutMI.getOpcode()) {
608 default: llvm_unreachable("Invalid opcode")::llvm::llvm_unreachable_internal("Invalid opcode", "/build/llvm-toolchain-snapshot-9~svn358520/lib/Target/X86/X86MCInstLower.cpp"
, 608)
;
609 case X86::MOV8mr_NOREX:
610 case X86::MOV8mr: NewOpc = X86::MOV8o32a; break;
611 case X86::MOV8rm_NOREX:
612 case X86::MOV8rm: NewOpc = X86::MOV8ao32; break;
613 case X86::MOV16mr: NewOpc = X86::MOV16o32a; break;
614 case X86::MOV16rm: NewOpc = X86::MOV16ao32; break;
615 case X86::MOV32mr: NewOpc = X86::MOV32o32a; break;
616 case X86::MOV32rm: NewOpc = X86::MOV32ao32; break;
617 }
618 SimplifyShortMoveForm(AsmPrinter, OutMI, NewOpc);
619 break;
620 }
621
622 case X86::ADC8ri: case X86::ADC16ri: case X86::ADC32ri: case X86::ADC64ri32:
623 case X86::ADD8ri: case X86::ADD16ri: case X86::ADD32ri: case X86::ADD64ri32:
624 case X86::AND8ri: case X86::AND16ri: case X86::AND32ri: case X86::AND64ri32:
625 case X86::CMP8ri: case X86::CMP16ri: case X86::CMP32ri: case X86::CMP64ri32:
626 case X86::OR8ri: case X86::OR16ri: case X86::OR32ri: case X86::OR64ri32:
627 case X86::SBB8ri: case X86::SBB16ri: case X86::SBB32ri: case X86::SBB64ri32:
628 case X86::SUB8ri: case X86::SUB16ri: case X86::SUB32ri: case X86::SUB64ri32:
629 case X86::TEST8ri:case X86::TEST16ri:case X86::TEST32ri:case X86::TEST64ri32:
630 case X86::XOR8ri: case X86::XOR16ri: case X86::XOR32ri: case X86::XOR64ri32: {
631 unsigned NewOpc;
632 switch (OutMI.getOpcode()) {
633 default: llvm_unreachable("Invalid opcode")::llvm::llvm_unreachable_internal("Invalid opcode", "/build/llvm-toolchain-snapshot-9~svn358520/lib/Target/X86/X86MCInstLower.cpp"
, 633)
;
634 case X86::ADC8ri: NewOpc = X86::ADC8i8; break;
635 case X86::ADC16ri: NewOpc = X86::ADC16i16; break;
636 case X86::ADC32ri: NewOpc = X86::ADC32i32; break;
637 case X86::ADC64ri32: NewOpc = X86::ADC64i32; break;
638 case X86::ADD8ri: NewOpc = X86::ADD8i8; break;
639 case X86::ADD16ri: NewOpc = X86::ADD16i16; break;
640 case X86::ADD32ri: NewOpc = X86::ADD32i32; break;
641 case X86::ADD64ri32: NewOpc = X86::ADD64i32; break;
642 case X86::AND8ri: NewOpc = X86::AND8i8; break;
643 case X86::AND16ri: NewOpc = X86::AND16i16; break;
644 case X86::AND32ri: NewOpc = X86::AND32i32; break;
645 case X86::AND64ri32: NewOpc = X86::AND64i32; break;
646 case X86::CMP8ri: NewOpc = X86::CMP8i8; break;
647 case X86::CMP16ri: NewOpc = X86::CMP16i16; break;
648 case X86::CMP32ri: NewOpc = X86::CMP32i32; break;
649 case X86::CMP64ri32: NewOpc = X86::CMP64i32; break;
650 case X86::OR8ri: NewOpc = X86::OR8i8; break;
651 case X86::OR16ri: NewOpc = X86::OR16i16; break;
652 case X86::OR32ri: NewOpc = X86::OR32i32; break;
653 case X86::OR64ri32: NewOpc = X86::OR64i32; break;
654 case X86::SBB8ri: NewOpc = X86::SBB8i8; break;
655 case X86::SBB16ri: NewOpc = X86::SBB16i16; break;
656 case X86::SBB32ri: NewOpc = X86::SBB32i32; break;
657 case X86::SBB64ri32: NewOpc = X86::SBB64i32; break;
658 case X86::SUB8ri: NewOpc = X86::SUB8i8; break;
659 case X86::SUB16ri: NewOpc = X86::SUB16i16; break;
660 case X86::SUB32ri: NewOpc = X86::SUB32i32; break;
661 case X86::SUB64ri32: NewOpc = X86::SUB64i32; break;
662 case X86::TEST8ri: NewOpc = X86::TEST8i8; break;
663 case X86::TEST16ri: NewOpc = X86::TEST16i16; break;
664 case X86::TEST32ri: NewOpc = X86::TEST32i32; break;
665 case X86::TEST64ri32: NewOpc = X86::TEST64i32; break;
666 case X86::XOR8ri: NewOpc = X86::XOR8i8; break;
667 case X86::XOR16ri: NewOpc = X86::XOR16i16; break;
668 case X86::XOR32ri: NewOpc = X86::XOR32i32; break;
669 case X86::XOR64ri32: NewOpc = X86::XOR64i32; break;
670 }
671 SimplifyShortImmForm(OutMI, NewOpc);
672 break;
673 }
674
675 // Try to shrink some forms of movsx.
676 case X86::MOVSX16rr8:
677 case X86::MOVSX32rr16:
678 case X86::MOVSX64rr32:
679 SimplifyMOVSX(OutMI);
680 break;
681 }
682}
683
684void X86AsmPrinter::LowerTlsAddr(X86MCInstLower &MCInstLowering,
685 const MachineInstr &MI) {
686
687 bool is64Bits = MI.getOpcode() == X86::TLS_addr64 ||
688 MI.getOpcode() == X86::TLS_base_addr64;
689
690 bool needsPadding = MI.getOpcode() == X86::TLS_addr64;
691
692 MCContext &context = OutStreamer->getContext();
693
694 if (needsPadding)
695 EmitAndCountInstruction(MCInstBuilder(X86::DATA16_PREFIX));
696
697 MCSymbolRefExpr::VariantKind SRVK;
698 switch (MI.getOpcode()) {
699 case X86::TLS_addr32:
700 case X86::TLS_addr64:
701 SRVK = MCSymbolRefExpr::VK_TLSGD;
702 break;
703 case X86::TLS_base_addr32:
704 SRVK = MCSymbolRefExpr::VK_TLSLDM;
705 break;
706 case X86::TLS_base_addr64:
707 SRVK = MCSymbolRefExpr::VK_TLSLD;
708 break;
709 default:
710 llvm_unreachable("unexpected opcode")::llvm::llvm_unreachable_internal("unexpected opcode", "/build/llvm-toolchain-snapshot-9~svn358520/lib/Target/X86/X86MCInstLower.cpp"
, 710)
;
711 }
712
713 MCSymbol *sym = MCInstLowering.GetSymbolFromOperand(MI.getOperand(3));
714 const MCSymbolRefExpr *symRef = MCSymbolRefExpr::create(sym, SRVK, context);
715
716 MCInst LEA;
717 if (is64Bits) {
718 LEA.setOpcode(X86::LEA64r);
719 LEA.addOperand(MCOperand::createReg(X86::RDI)); // dest
720 LEA.addOperand(MCOperand::createReg(X86::RIP)); // base
721 LEA.addOperand(MCOperand::createImm(1)); // scale
722 LEA.addOperand(MCOperand::createReg(0)); // index
723 LEA.addOperand(MCOperand::createExpr(symRef)); // disp
724 LEA.addOperand(MCOperand::createReg(0)); // seg
725 } else if (SRVK == MCSymbolRefExpr::VK_TLSLDM) {
726 LEA.setOpcode(X86::LEA32r);
727 LEA.addOperand(MCOperand::createReg(X86::EAX)); // dest
728 LEA.addOperand(MCOperand::createReg(X86::EBX)); // base
729 LEA.addOperand(MCOperand::createImm(1)); // scale
730 LEA.addOperand(MCOperand::createReg(0)); // index
731 LEA.addOperand(MCOperand::createExpr(symRef)); // disp
732 LEA.addOperand(MCOperand::createReg(0)); // seg
733 } else {
734 LEA.setOpcode(X86::LEA32r);
735 LEA.addOperand(MCOperand::createReg(X86::EAX)); // dest
736 LEA.addOperand(MCOperand::createReg(0)); // base
737 LEA.addOperand(MCOperand::createImm(1)); // scale
738 LEA.addOperand(MCOperand::createReg(X86::EBX)); // index
739 LEA.addOperand(MCOperand::createExpr(symRef)); // disp
740 LEA.addOperand(MCOperand::createReg(0)); // seg
741 }
742 EmitAndCountInstruction(LEA);
743
744 if (needsPadding) {
745 EmitAndCountInstruction(MCInstBuilder(X86::DATA16_PREFIX));
746 EmitAndCountInstruction(MCInstBuilder(X86::DATA16_PREFIX));
747 EmitAndCountInstruction(MCInstBuilder(X86::REX64_PREFIX));
748 }
749
750 StringRef name = is64Bits ? "__tls_get_addr" : "___tls_get_addr";
751 MCSymbol *tlsGetAddr = context.getOrCreateSymbol(name);
752 const MCSymbolRefExpr *tlsRef =
753 MCSymbolRefExpr::create(tlsGetAddr, MCSymbolRefExpr::VK_PLT, context);
754
755 EmitAndCountInstruction(
756 MCInstBuilder(is64Bits ? X86::CALL64pcrel32 : X86::CALLpcrel32)
757 .addExpr(tlsRef));
758}
759
760/// Emit the largest nop instruction smaller than or equal to \p NumBytes
761/// bytes. Return the size of nop emitted.
762static unsigned EmitNop(MCStreamer &OS, unsigned NumBytes, bool Is64Bit,
763 const MCSubtargetInfo &STI) {
764 // This works only for 64bit. For 32bit we have to do additional checking if
765 // the CPU supports multi-byte nops.
766 assert(Is64Bit && "EmitNops only supports X86-64")((Is64Bit && "EmitNops only supports X86-64") ? static_cast
<void> (0) : __assert_fail ("Is64Bit && \"EmitNops only supports X86-64\""
, "/build/llvm-toolchain-snapshot-9~svn358520/lib/Target/X86/X86MCInstLower.cpp"
, 766, __PRETTY_FUNCTION__))
;
767
768 unsigned NopSize;
769 unsigned Opc, BaseReg, ScaleVal, IndexReg, Displacement, SegmentReg;
770 Opc = IndexReg = Displacement = SegmentReg = 0;
Value stored to 'Opc' is never read
771 BaseReg = X86::RAX;
772 ScaleVal = 1;
773 switch (NumBytes) {
774 case 0:
775 llvm_unreachable("Zero nops?")::llvm::llvm_unreachable_internal("Zero nops?", "/build/llvm-toolchain-snapshot-9~svn358520/lib/Target/X86/X86MCInstLower.cpp"
, 775)
;
776 break;
777 case 1:
778 NopSize = 1;
779 Opc = X86::NOOP;
780 break;
781 case 2:
782 NopSize = 2;
783 Opc = X86::XCHG16ar;
784 break;
785 case 3:
786 NopSize = 3;
787 Opc = X86::NOOPL;
788 break;
789 case 4:
790 NopSize = 4;
791 Opc = X86::NOOPL;
792 Displacement = 8;
793 break;
794 case 5:
795 NopSize = 5;
796 Opc = X86::NOOPL;
797 Displacement = 8;
798 IndexReg = X86::RAX;
799 break;
800 case 6:
801 NopSize = 6;
802 Opc = X86::NOOPW;
803 Displacement = 8;
804 IndexReg = X86::RAX;
805 break;
806 case 7:
807 NopSize = 7;
808 Opc = X86::NOOPL;
809 Displacement = 512;
810 break;
811 case 8:
812 NopSize = 8;
813 Opc = X86::NOOPL;
814 Displacement = 512;
815 IndexReg = X86::RAX;
816 break;
817 case 9:
818 NopSize = 9;
819 Opc = X86::NOOPW;
820 Displacement = 512;
821 IndexReg = X86::RAX;
822 break;
823 default:
824 NopSize = 10;
825 Opc = X86::NOOPW;
826 Displacement = 512;
827 IndexReg = X86::RAX;
828 SegmentReg = X86::CS;
829 break;
830 }
831
832 unsigned NumPrefixes = std::min(NumBytes - NopSize, 5U);
833 NopSize += NumPrefixes;
834 for (unsigned i = 0; i != NumPrefixes; ++i)
835 OS.EmitBytes("\x66");
836
837 switch (Opc) {
838 default: llvm_unreachable("Unexpected opcode")::llvm::llvm_unreachable_internal("Unexpected opcode", "/build/llvm-toolchain-snapshot-9~svn358520/lib/Target/X86/X86MCInstLower.cpp"
, 838)
;
839 case X86::NOOP:
840 OS.EmitInstruction(MCInstBuilder(Opc), STI);
841 break;
842 case X86::XCHG16ar:
843 OS.EmitInstruction(MCInstBuilder(Opc).addReg(X86::AX).addReg(X86::AX), STI);
844 break;
845 case X86::NOOPL:
846 case X86::NOOPW:
847 OS.EmitInstruction(MCInstBuilder(Opc)
848 .addReg(BaseReg)
849 .addImm(ScaleVal)
850 .addReg(IndexReg)
851 .addImm(Displacement)
852 .addReg(SegmentReg),
853 STI);
854 break;
855 }
856 assert(NopSize <= NumBytes && "We overemitted?")((NopSize <= NumBytes && "We overemitted?") ? static_cast
<void> (0) : __assert_fail ("NopSize <= NumBytes && \"We overemitted?\""
, "/build/llvm-toolchain-snapshot-9~svn358520/lib/Target/X86/X86MCInstLower.cpp"
, 856, __PRETTY_FUNCTION__))
;
857 return NopSize;
858}
859
860/// Emit the optimal amount of multi-byte nops on X86.
861static void EmitNops(MCStreamer &OS, unsigned NumBytes, bool Is64Bit,
862 const MCSubtargetInfo &STI) {
863 unsigned NopsToEmit = NumBytes;
864 (void)NopsToEmit;
865 while (NumBytes) {
866 NumBytes -= EmitNop(OS, NumBytes, Is64Bit, STI);
867 assert(NopsToEmit >= NumBytes && "Emitted more than I asked for!")((NopsToEmit >= NumBytes && "Emitted more than I asked for!"
) ? static_cast<void> (0) : __assert_fail ("NopsToEmit >= NumBytes && \"Emitted more than I asked for!\""
, "/build/llvm-toolchain-snapshot-9~svn358520/lib/Target/X86/X86MCInstLower.cpp"
, 867, __PRETTY_FUNCTION__))
;
868 }
869}
870
871void X86AsmPrinter::LowerSTATEPOINT(const MachineInstr &MI,
872 X86MCInstLower &MCIL) {
873 assert(Subtarget->is64Bit() && "Statepoint currently only supports X86-64")((Subtarget->is64Bit() && "Statepoint currently only supports X86-64"
) ? static_cast<void> (0) : __assert_fail ("Subtarget->is64Bit() && \"Statepoint currently only supports X86-64\""
, "/build/llvm-toolchain-snapshot-9~svn358520/lib/Target/X86/X86MCInstLower.cpp"
, 873, __PRETTY_FUNCTION__))
;
874
875 StatepointOpers SOpers(&MI);
876 if (unsigned PatchBytes = SOpers.getNumPatchBytes()) {
877 EmitNops(*OutStreamer, PatchBytes, Subtarget->is64Bit(),
878 getSubtargetInfo());
879 } else {
880 // Lower call target and choose correct opcode
881 const MachineOperand &CallTarget = SOpers.getCallTarget();
882 MCOperand CallTargetMCOp;
883 unsigned CallOpcode;
884 switch (CallTarget.getType()) {
885 case MachineOperand::MO_GlobalAddress:
886 case MachineOperand::MO_ExternalSymbol:
887 CallTargetMCOp = MCIL.LowerSymbolOperand(
888 CallTarget, MCIL.GetSymbolFromOperand(CallTarget));
889 CallOpcode = X86::CALL64pcrel32;
890 // Currently, we only support relative addressing with statepoints.
891 // Otherwise, we'll need a scratch register to hold the target
892 // address. You'll fail asserts during load & relocation if this
893 // symbol is to far away. (TODO: support non-relative addressing)
894 break;
895 case MachineOperand::MO_Immediate:
896 CallTargetMCOp = MCOperand::createImm(CallTarget.getImm());
897 CallOpcode = X86::CALL64pcrel32;
898 // Currently, we only support relative addressing with statepoints.
899 // Otherwise, we'll need a scratch register to hold the target
900 // immediate. You'll fail asserts during load & relocation if this
901 // address is to far away. (TODO: support non-relative addressing)
902 break;
903 case MachineOperand::MO_Register:
904 // FIXME: Add retpoline support and remove this.
905 if (Subtarget->useRetpolineIndirectCalls())
906 report_fatal_error("Lowering register statepoints with retpoline not "
907 "yet implemented.");
908 CallTargetMCOp = MCOperand::createReg(CallTarget.getReg());
909 CallOpcode = X86::CALL64r;
910 break;
911 default:
912 llvm_unreachable("Unsupported operand type in statepoint call target")::llvm::llvm_unreachable_internal("Unsupported operand type in statepoint call target"
, "/build/llvm-toolchain-snapshot-9~svn358520/lib/Target/X86/X86MCInstLower.cpp"
, 912)
;
913 break;
914 }
915
916 // Emit call
917 MCInst CallInst;
918 CallInst.setOpcode(CallOpcode);
919 CallInst.addOperand(CallTargetMCOp);
920 OutStreamer->EmitInstruction(CallInst, getSubtargetInfo());
921 }
922
923 // Record our statepoint node in the same section used by STACKMAP
924 // and PATCHPOINT
925 SM.recordStatepoint(MI);
926}
927
928void X86AsmPrinter::LowerFAULTING_OP(const MachineInstr &FaultingMI,
929 X86MCInstLower &MCIL) {
930 // FAULTING_LOAD_OP <def>, <faltinf type>, <MBB handler>,
931 // <opcode>, <operands>
932
933 unsigned DefRegister = FaultingMI.getOperand(0).getReg();
934 FaultMaps::FaultKind FK =
935 static_cast<FaultMaps::FaultKind>(FaultingMI.getOperand(1).getImm());
936 MCSymbol *HandlerLabel = FaultingMI.getOperand(2).getMBB()->getSymbol();
937 unsigned Opcode = FaultingMI.getOperand(3).getImm();
938 unsigned OperandsBeginIdx = 4;
939
940 assert(FK < FaultMaps::FaultKindMax && "Invalid Faulting Kind!")((FK < FaultMaps::FaultKindMax && "Invalid Faulting Kind!"
) ? static_cast<void> (0) : __assert_fail ("FK < FaultMaps::FaultKindMax && \"Invalid Faulting Kind!\""
, "/build/llvm-toolchain-snapshot-9~svn358520/lib/Target/X86/X86MCInstLower.cpp"
, 940, __PRETTY_FUNCTION__))
;
941 FM.recordFaultingOp(FK, HandlerLabel);
942
943 MCInst MI;
944 MI.setOpcode(Opcode);
945
946 if (DefRegister != X86::NoRegister)
947 MI.addOperand(MCOperand::createReg(DefRegister));
948
949 for (auto I = FaultingMI.operands_begin() + OperandsBeginIdx,
950 E = FaultingMI.operands_end();
951 I != E; ++I)
952 if (auto MaybeOperand = MCIL.LowerMachineOperand(&FaultingMI, *I))
953 MI.addOperand(MaybeOperand.getValue());
954
955 OutStreamer->AddComment("on-fault: " + HandlerLabel->getName());
956 OutStreamer->EmitInstruction(MI, getSubtargetInfo());
957}
958
959void X86AsmPrinter::LowerFENTRY_CALL(const MachineInstr &MI,
960 X86MCInstLower &MCIL) {
961 bool Is64Bits = Subtarget->is64Bit();
962 MCContext &Ctx = OutStreamer->getContext();
963 MCSymbol *fentry = Ctx.getOrCreateSymbol("__fentry__");
964 const MCSymbolRefExpr *Op =
965 MCSymbolRefExpr::create(fentry, MCSymbolRefExpr::VK_None, Ctx);
966
967 EmitAndCountInstruction(
968 MCInstBuilder(Is64Bits ? X86::CALL64pcrel32 : X86::CALLpcrel32)
969 .addExpr(Op));
970}
971
972void X86AsmPrinter::LowerPATCHABLE_OP(const MachineInstr &MI,
973 X86MCInstLower &MCIL) {
974 // PATCHABLE_OP minsize, opcode, operands
975
976 unsigned MinSize = MI.getOperand(0).getImm();
977 unsigned Opcode = MI.getOperand(1).getImm();
978
979 MCInst MCI;
980 MCI.setOpcode(Opcode);
981 for (auto &MO : make_range(MI.operands_begin() + 2, MI.operands_end()))
982 if (auto MaybeOperand = MCIL.LowerMachineOperand(&MI, MO))
983 MCI.addOperand(MaybeOperand.getValue());
984
985 SmallString<256> Code;
986 SmallVector<MCFixup, 4> Fixups;
987 raw_svector_ostream VecOS(Code);
988 CodeEmitter->encodeInstruction(MCI, VecOS, Fixups, getSubtargetInfo());
989
990 if (Code.size() < MinSize) {
991 if (MinSize == 2 && Opcode == X86::PUSH64r) {
992 // This is an optimization that lets us get away without emitting a nop in
993 // many cases.
994 //
995 // NB! In some cases the encoding for PUSH64r (e.g. PUSH64r %r9) takes two
996 // bytes too, so the check on MinSize is important.
997 MCI.setOpcode(X86::PUSH64rmr);
998 } else {
999 unsigned NopSize = EmitNop(*OutStreamer, MinSize, Subtarget->is64Bit(),
1000 getSubtargetInfo());
1001 assert(NopSize == MinSize && "Could not implement MinSize!")((NopSize == MinSize && "Could not implement MinSize!"
) ? static_cast<void> (0) : __assert_fail ("NopSize == MinSize && \"Could not implement MinSize!\""
, "/build/llvm-toolchain-snapshot-9~svn358520/lib/Target/X86/X86MCInstLower.cpp"
, 1001, __PRETTY_FUNCTION__))
;
1002 (void)NopSize;
1003 }
1004 }
1005
1006 OutStreamer->EmitInstruction(MCI, getSubtargetInfo());
1007}
1008
1009// Lower a stackmap of the form:
1010// <id>, <shadowBytes>, ...
1011void X86AsmPrinter::LowerSTACKMAP(const MachineInstr &MI) {
1012 SMShadowTracker.emitShadowPadding(*OutStreamer, getSubtargetInfo());
1013 SM.recordStackMap(MI);
1014 unsigned NumShadowBytes = MI.getOperand(1).getImm();
1015 SMShadowTracker.reset(NumShadowBytes);
1016}
1017
1018// Lower a patchpoint of the form:
1019// [<def>], <id>, <numBytes>, <target>, <numArgs>, <cc>, ...
1020void X86AsmPrinter::LowerPATCHPOINT(const MachineInstr &MI,
1021 X86MCInstLower &MCIL) {
1022 assert(Subtarget->is64Bit() && "Patchpoint currently only supports X86-64")((Subtarget->is64Bit() && "Patchpoint currently only supports X86-64"
) ? static_cast<void> (0) : __assert_fail ("Subtarget->is64Bit() && \"Patchpoint currently only supports X86-64\""
, "/build/llvm-toolchain-snapshot-9~svn358520/lib/Target/X86/X86MCInstLower.cpp"
, 1022, __PRETTY_FUNCTION__))
;
1023
1024 SMShadowTracker.emitShadowPadding(*OutStreamer, getSubtargetInfo());
1025
1026 SM.recordPatchPoint(MI);
1027
1028 PatchPointOpers opers(&MI);
1029 unsigned ScratchIdx = opers.getNextScratchIdx();
1030 unsigned EncodedBytes = 0;
1031 const MachineOperand &CalleeMO = opers.getCallTarget();
1032
1033 // Check for null target. If target is non-null (i.e. is non-zero or is
1034 // symbolic) then emit a call.
1035 if (!(CalleeMO.isImm() && !CalleeMO.getImm())) {
1036 MCOperand CalleeMCOp;
1037 switch (CalleeMO.getType()) {
1038 default:
1039 /// FIXME: Add a verifier check for bad callee types.
1040 llvm_unreachable("Unrecognized callee operand type.")::llvm::llvm_unreachable_internal("Unrecognized callee operand type."
, "/build/llvm-toolchain-snapshot-9~svn358520/lib/Target/X86/X86MCInstLower.cpp"
, 1040)
;
1041 case MachineOperand::MO_Immediate:
1042 if (CalleeMO.getImm())
1043 CalleeMCOp = MCOperand::createImm(CalleeMO.getImm());
1044 break;
1045 case MachineOperand::MO_ExternalSymbol:
1046 case MachineOperand::MO_GlobalAddress:
1047 CalleeMCOp = MCIL.LowerSymbolOperand(CalleeMO,
1048 MCIL.GetSymbolFromOperand(CalleeMO));
1049 break;
1050 }
1051
1052 // Emit MOV to materialize the target address and the CALL to target.
1053 // This is encoded with 12-13 bytes, depending on which register is used.
1054 unsigned ScratchReg = MI.getOperand(ScratchIdx).getReg();
1055 if (X86II::isX86_64ExtendedReg(ScratchReg))
1056 EncodedBytes = 13;
1057 else
1058 EncodedBytes = 12;
1059
1060 EmitAndCountInstruction(
1061 MCInstBuilder(X86::MOV64ri).addReg(ScratchReg).addOperand(CalleeMCOp));
1062 // FIXME: Add retpoline support and remove this.
1063 if (Subtarget->useRetpolineIndirectCalls())
1064 report_fatal_error(
1065 "Lowering patchpoint with retpoline not yet implemented.");
1066 EmitAndCountInstruction(MCInstBuilder(X86::CALL64r).addReg(ScratchReg));
1067 }
1068
1069 // Emit padding.
1070 unsigned NumBytes = opers.getNumPatchBytes();
1071 assert(NumBytes >= EncodedBytes &&((NumBytes >= EncodedBytes && "Patchpoint can't request size less than the length of a call."
) ? static_cast<void> (0) : __assert_fail ("NumBytes >= EncodedBytes && \"Patchpoint can't request size less than the length of a call.\""
, "/build/llvm-toolchain-snapshot-9~svn358520/lib/Target/X86/X86MCInstLower.cpp"
, 1072, __PRETTY_FUNCTION__))
1072 "Patchpoint can't request size less than the length of a call.")((NumBytes >= EncodedBytes && "Patchpoint can't request size less than the length of a call."
) ? static_cast<void> (0) : __assert_fail ("NumBytes >= EncodedBytes && \"Patchpoint can't request size less than the length of a call.\""
, "/build/llvm-toolchain-snapshot-9~svn358520/lib/Target/X86/X86MCInstLower.cpp"
, 1072, __PRETTY_FUNCTION__))
;
1073
1074 EmitNops(*OutStreamer, NumBytes - EncodedBytes, Subtarget->is64Bit(),
1075 getSubtargetInfo());
1076}
1077
1078void X86AsmPrinter::LowerPATCHABLE_EVENT_CALL(const MachineInstr &MI,
1079 X86MCInstLower &MCIL) {
1080 assert(Subtarget->is64Bit() && "XRay custom events only supports X86-64")((Subtarget->is64Bit() && "XRay custom events only supports X86-64"
) ? static_cast<void> (0) : __assert_fail ("Subtarget->is64Bit() && \"XRay custom events only supports X86-64\""
, "/build/llvm-toolchain-snapshot-9~svn358520/lib/Target/X86/X86MCInstLower.cpp"
, 1080, __PRETTY_FUNCTION__))
;
1081
1082 // We want to emit the following pattern, which follows the x86 calling
1083 // convention to prepare for the trampoline call to be patched in.
1084 //
1085 // .p2align 1, ...
1086 // .Lxray_event_sled_N:
1087 // jmp +N // jump across the instrumentation sled
1088 // ... // set up arguments in register
1089 // callq __xray_CustomEvent@plt // force dependency to symbol
1090 // ...
1091 // <jump here>
1092 //
1093 // After patching, it would look something like:
1094 //
1095 // nopw (2-byte nop)
1096 // ...
1097 // callq __xrayCustomEvent // already lowered
1098 // ...
1099 //
1100 // ---
1101 // First we emit the label and the jump.
1102 auto CurSled = OutContext.createTempSymbol("xray_event_sled_", true);
1103 OutStreamer->AddComment("# XRay Custom Event Log");
1104 OutStreamer->EmitCodeAlignment(2);
1105 OutStreamer->EmitLabel(CurSled);
1106
1107 // Use a two-byte `jmp`. This version of JMP takes an 8-bit relative offset as
1108 // an operand (computed as an offset from the jmp instruction).
1109 // FIXME: Find another less hacky way do force the relative jump.
1110 OutStreamer->EmitBinaryData("\xeb\x0f");
1111
1112 // The default C calling convention will place two arguments into %rcx and
1113 // %rdx -- so we only work with those.
1114 unsigned DestRegs[] = {X86::RDI, X86::RSI};
1115 bool UsedMask[] = {false, false};
1116 // Filled out in loop.
1117 unsigned SrcRegs[] = {0, 0};
1118
1119 // Then we put the operands in the %rdi and %rsi registers. We spill the
1120 // values in the register before we clobber them, and mark them as used in
1121 // UsedMask. In case the arguments are already in the correct register, we use
1122 // emit nops appropriately sized to keep the sled the same size in every
1123 // situation.
1124 for (unsigned I = 0; I < MI.getNumOperands(); ++I)
1125 if (auto Op = MCIL.LowerMachineOperand(&MI, MI.getOperand(I))) {
1126 assert(Op->isReg() && "Only support arguments in registers")((Op->isReg() && "Only support arguments in registers"
) ? static_cast<void> (0) : __assert_fail ("Op->isReg() && \"Only support arguments in registers\""
, "/build/llvm-toolchain-snapshot-9~svn358520/lib/Target/X86/X86MCInstLower.cpp"
, 1126, __PRETTY_FUNCTION__))
;
1127 SrcRegs[I] = Op->getReg();
1128 if (SrcRegs[I] != DestRegs[I]) {
1129 UsedMask[I] = true;
1130 EmitAndCountInstruction(
1131 MCInstBuilder(X86::PUSH64r).addReg(DestRegs[I]));
1132 } else {
1133 EmitNops(*OutStreamer, 4, Subtarget->is64Bit(), getSubtargetInfo());
1134 }
1135 }
1136
1137 // Now that the register values are stashed, mov arguments into place.
1138 for (unsigned I = 0; I < MI.getNumOperands(); ++I)
1139 if (SrcRegs[I] != DestRegs[I])
1140 EmitAndCountInstruction(
1141 MCInstBuilder(X86::MOV64rr).addReg(DestRegs[I]).addReg(SrcRegs[I]));
1142
1143 // We emit a hard dependency on the __xray_CustomEvent symbol, which is the
1144 // name of the trampoline to be implemented by the XRay runtime.
1145 auto TSym = OutContext.getOrCreateSymbol("__xray_CustomEvent");
1146 MachineOperand TOp = MachineOperand::CreateMCSymbol(TSym);
1147 if (isPositionIndependent())
1148 TOp.setTargetFlags(X86II::MO_PLT);
1149
1150 // Emit the call instruction.
1151 EmitAndCountInstruction(MCInstBuilder(X86::CALL64pcrel32)
1152 .addOperand(MCIL.LowerSymbolOperand(TOp, TSym)));
1153
1154 // Restore caller-saved and used registers.
1155 for (unsigned I = sizeof UsedMask; I-- > 0;)
1156 if (UsedMask[I])
1157 EmitAndCountInstruction(MCInstBuilder(X86::POP64r).addReg(DestRegs[I]));
1158 else
1159 EmitNops(*OutStreamer, 1, Subtarget->is64Bit(), getSubtargetInfo());
1160
1161 OutStreamer->AddComment("xray custom event end.");
1162
1163 // Record the sled version. Older versions of this sled were spelled
1164 // differently, so we let the runtime handle the different offsets we're
1165 // using.
1166 recordSled(CurSled, MI, SledKind::CUSTOM_EVENT, 1);
1167}
1168
1169void X86AsmPrinter::LowerPATCHABLE_TYPED_EVENT_CALL(const MachineInstr &MI,
1170 X86MCInstLower &MCIL) {
1171 assert(Subtarget->is64Bit() && "XRay typed events only supports X86-64")((Subtarget->is64Bit() && "XRay typed events only supports X86-64"
) ? static_cast<void> (0) : __assert_fail ("Subtarget->is64Bit() && \"XRay typed events only supports X86-64\""
, "/build/llvm-toolchain-snapshot-9~svn358520/lib/Target/X86/X86MCInstLower.cpp"
, 1171, __PRETTY_FUNCTION__))
;
1172
1173 // We want to emit the following pattern, which follows the x86 calling
1174 // convention to prepare for the trampoline call to be patched in.
1175 //
1176 // .p2align 1, ...
1177 // .Lxray_event_sled_N:
1178 // jmp +N // jump across the instrumentation sled
1179 // ... // set up arguments in register
1180 // callq __xray_TypedEvent@plt // force dependency to symbol
1181 // ...
1182 // <jump here>
1183 //
1184 // After patching, it would look something like:
1185 //
1186 // nopw (2-byte nop)
1187 // ...
1188 // callq __xrayTypedEvent // already lowered
1189 // ...
1190 //
1191 // ---
1192 // First we emit the label and the jump.
1193 auto CurSled = OutContext.createTempSymbol("xray_typed_event_sled_", true);
1194 OutStreamer->AddComment("# XRay Typed Event Log");
1195 OutStreamer->EmitCodeAlignment(2);
1196 OutStreamer->EmitLabel(CurSled);
1197
1198 // Use a two-byte `jmp`. This version of JMP takes an 8-bit relative offset as
1199 // an operand (computed as an offset from the jmp instruction).
1200 // FIXME: Find another less hacky way do force the relative jump.
1201 OutStreamer->EmitBinaryData("\xeb\x14");
1202
1203 // An x86-64 convention may place three arguments into %rcx, %rdx, and R8,
1204 // so we'll work with those. Or we may be called via SystemV, in which case
1205 // we don't have to do any translation.
1206 unsigned DestRegs[] = {X86::RDI, X86::RSI, X86::RDX};
1207 bool UsedMask[] = {false, false, false};
1208
1209 // Will fill out src regs in the loop.
1210 unsigned SrcRegs[] = {0, 0, 0};
1211
1212 // Then we put the operands in the SystemV registers. We spill the values in
1213 // the registers before we clobber them, and mark them as used in UsedMask.
1214 // In case the arguments are already in the correct register, we emit nops
1215 // appropriately sized to keep the sled the same size in every situation.
1216 for (unsigned I = 0; I < MI.getNumOperands(); ++I)
1217 if (auto Op = MCIL.LowerMachineOperand(&MI, MI.getOperand(I))) {
1218 // TODO: Is register only support adequate?
1219 assert(Op->isReg() && "Only supports arguments in registers")((Op->isReg() && "Only supports arguments in registers"
) ? static_cast<void> (0) : __assert_fail ("Op->isReg() && \"Only supports arguments in registers\""
, "/build/llvm-toolchain-snapshot-9~svn358520/lib/Target/X86/X86MCInstLower.cpp"
, 1219, __PRETTY_FUNCTION__))
;
1220 SrcRegs[I] = Op->getReg();
1221 if (SrcRegs[I] != DestRegs[I]) {
1222 UsedMask[I] = true;
1223 EmitAndCountInstruction(
1224 MCInstBuilder(X86::PUSH64r).addReg(DestRegs[I]));
1225 } else {
1226 EmitNops(*OutStreamer, 4, Subtarget->is64Bit(), getSubtargetInfo());
1227 }
1228 }
1229
1230 // In the above loop we only stash all of the destination registers or emit
1231 // nops if the arguments are already in the right place. Doing the actually
1232 // moving is postponed until after all the registers are stashed so nothing
1233 // is clobbers. We've already added nops to account for the size of mov and
1234 // push if the register is in the right place, so we only have to worry about
1235 // emitting movs.
1236 for (unsigned I = 0; I < MI.getNumOperands(); ++I)
1237 if (UsedMask[I])
1238 EmitAndCountInstruction(
1239 MCInstBuilder(X86::MOV64rr).addReg(DestRegs[I]).addReg(SrcRegs[I]));
1240
1241 // We emit a hard dependency on the __xray_TypedEvent symbol, which is the
1242 // name of the trampoline to be implemented by the XRay runtime.
1243 auto TSym = OutContext.getOrCreateSymbol("__xray_TypedEvent");
1244 MachineOperand TOp = MachineOperand::CreateMCSymbol(TSym);
1245 if (isPositionIndependent())
1246 TOp.setTargetFlags(X86II::MO_PLT);
1247
1248 // Emit the call instruction.
1249 EmitAndCountInstruction(MCInstBuilder(X86::CALL64pcrel32)
1250 .addOperand(MCIL.LowerSymbolOperand(TOp, TSym)));
1251
1252 // Restore caller-saved and used registers.
1253 for (unsigned I = sizeof UsedMask; I-- > 0;)
1254 if (UsedMask[I])
1255 EmitAndCountInstruction(MCInstBuilder(X86::POP64r).addReg(DestRegs[I]));
1256 else
1257 EmitNops(*OutStreamer, 1, Subtarget->is64Bit(), getSubtargetInfo());
1258
1259 OutStreamer->AddComment("xray typed event end.");
1260
1261 // Record the sled version.
1262 recordSled(CurSled, MI, SledKind::TYPED_EVENT, 0);
1263}
1264
1265void X86AsmPrinter::LowerPATCHABLE_FUNCTION_ENTER(const MachineInstr &MI,
1266 X86MCInstLower &MCIL) {
1267 // We want to emit the following pattern:
1268 //
1269 // .p2align 1, ...
1270 // .Lxray_sled_N:
1271 // jmp .tmpN
1272 // # 9 bytes worth of noops
1273 //
1274 // We need the 9 bytes because at runtime, we'd be patching over the full 11
1275 // bytes with the following pattern:
1276 //
1277 // mov %r10, <function id, 32-bit> // 6 bytes
1278 // call <relative offset, 32-bits> // 5 bytes
1279 //
1280 auto CurSled = OutContext.createTempSymbol("xray_sled_", true);
1281 OutStreamer->EmitCodeAlignment(2);
1282 OutStreamer->EmitLabel(CurSled);
1283
1284 // Use a two-byte `jmp`. This version of JMP takes an 8-bit relative offset as
1285 // an operand (computed as an offset from the jmp instruction).
1286 // FIXME: Find another less hacky way do force the relative jump.
1287 OutStreamer->EmitBytes("\xeb\x09");
1288 EmitNops(*OutStreamer, 9, Subtarget->is64Bit(), getSubtargetInfo());
1289 recordSled(CurSled, MI, SledKind::FUNCTION_ENTER);
1290}
1291
1292void X86AsmPrinter::LowerPATCHABLE_RET(const MachineInstr &MI,
1293 X86MCInstLower &MCIL) {
1294 // Since PATCHABLE_RET takes the opcode of the return statement as an
1295 // argument, we use that to emit the correct form of the RET that we want.
1296 // i.e. when we see this:
1297 //
1298 // PATCHABLE_RET X86::RET ...
1299 //
1300 // We should emit the RET followed by sleds.
1301 //
1302 // .p2align 1, ...
1303 // .Lxray_sled_N:
1304 // ret # or equivalent instruction
1305 // # 10 bytes worth of noops
1306 //
1307 // This just makes sure that the alignment for the next instruction is 2.
1308 auto CurSled = OutContext.createTempSymbol("xray_sled_", true);
1309 OutStreamer->EmitCodeAlignment(2);
1310 OutStreamer->EmitLabel(CurSled);
1311 unsigned OpCode = MI.getOperand(0).getImm();
1312 MCInst Ret;
1313 Ret.setOpcode(OpCode);
1314 for (auto &MO : make_range(MI.operands_begin() + 1, MI.operands_end()))
1315 if (auto MaybeOperand = MCIL.LowerMachineOperand(&MI, MO))
1316 Ret.addOperand(MaybeOperand.getValue());
1317 OutStreamer->EmitInstruction(Ret, getSubtargetInfo());
1318 EmitNops(*OutStreamer, 10, Subtarget->is64Bit(), getSubtargetInfo());
1319 recordSled(CurSled, MI, SledKind::FUNCTION_EXIT);
1320}
1321
1322void X86AsmPrinter::LowerPATCHABLE_TAIL_CALL(const MachineInstr &MI,
1323 X86MCInstLower &MCIL) {
1324 // Like PATCHABLE_RET, we have the actual instruction in the operands to this
1325 // instruction so we lower that particular instruction and its operands.
1326 // Unlike PATCHABLE_RET though, we put the sled before the JMP, much like how
1327 // we do it for PATCHABLE_FUNCTION_ENTER. The sled should be very similar to
1328 // the PATCHABLE_FUNCTION_ENTER case, followed by the lowering of the actual
1329 // tail call much like how we have it in PATCHABLE_RET.
1330 auto CurSled = OutContext.createTempSymbol("xray_sled_", true);
1331 OutStreamer->EmitCodeAlignment(2);
1332 OutStreamer->EmitLabel(CurSled);
1333 auto Target = OutContext.createTempSymbol();
1334
1335 // Use a two-byte `jmp`. This version of JMP takes an 8-bit relative offset as
1336 // an operand (computed as an offset from the jmp instruction).
1337 // FIXME: Find another less hacky way do force the relative jump.
1338 OutStreamer->EmitBytes("\xeb\x09");
1339 EmitNops(*OutStreamer, 9, Subtarget->is64Bit(), getSubtargetInfo());
1340 OutStreamer->EmitLabel(Target);
1341 recordSled(CurSled, MI, SledKind::TAIL_CALL);
1342
1343 unsigned OpCode = MI.getOperand(0).getImm();
1344 MCInst TC;
1345 TC.setOpcode(OpCode);
1346
1347 // Before emitting the instruction, add a comment to indicate that this is
1348 // indeed a tail call.
1349 OutStreamer->AddComment("TAILCALL");
1350 for (auto &MO : make_range(MI.operands_begin() + 1, MI.operands_end()))
1351 if (auto MaybeOperand = MCIL.LowerMachineOperand(&MI, MO))
1352 TC.addOperand(MaybeOperand.getValue());
1353 OutStreamer->EmitInstruction(TC, getSubtargetInfo());
1354}
1355
1356// Returns instruction preceding MBBI in MachineFunction.
1357// If MBBI is the first instruction of the first basic block, returns null.
1358static MachineBasicBlock::const_iterator
1359PrevCrossBBInst(MachineBasicBlock::const_iterator MBBI) {
1360 const MachineBasicBlock *MBB = MBBI->getParent();
1361 while (MBBI == MBB->begin()) {
1362 if (MBB == &MBB->getParent()->front())
1363 return MachineBasicBlock::const_iterator();
1364 MBB = MBB->getPrevNode();
1365 MBBI = MBB->end();
1366 }
1367 return --MBBI;
1368}
1369
1370static const Constant *getConstantFromPool(const MachineInstr &MI,
1371 const MachineOperand &Op) {
1372 if (!Op.isCPI() || Op.getOffset() != 0)
1373 return nullptr;
1374
1375 ArrayRef<MachineConstantPoolEntry> Constants =
1376 MI.getParent()->getParent()->getConstantPool()->getConstants();
1377 const MachineConstantPoolEntry &ConstantEntry = Constants[Op.getIndex()];
1378
1379 // Bail if this is a machine constant pool entry, we won't be able to dig out
1380 // anything useful.
1381 if (ConstantEntry.isMachineConstantPoolEntry())
1382 return nullptr;
1383
1384 const Constant *C = ConstantEntry.Val.ConstVal;
1385 assert((!C || ConstantEntry.getType() == C->getType()) &&(((!C || ConstantEntry.getType() == C->getType()) &&
"Expected a constant of the same type!") ? static_cast<void
> (0) : __assert_fail ("(!C || ConstantEntry.getType() == C->getType()) && \"Expected a constant of the same type!\""
, "/build/llvm-toolchain-snapshot-9~svn358520/lib/Target/X86/X86MCInstLower.cpp"
, 1386, __PRETTY_FUNCTION__))
1386 "Expected a constant of the same type!")(((!C || ConstantEntry.getType() == C->getType()) &&
"Expected a constant of the same type!") ? static_cast<void
> (0) : __assert_fail ("(!C || ConstantEntry.getType() == C->getType()) && \"Expected a constant of the same type!\""
, "/build/llvm-toolchain-snapshot-9~svn358520/lib/Target/X86/X86MCInstLower.cpp"
, 1386, __PRETTY_FUNCTION__))
;
1387 return C;
1388}
1389
1390static std::string getShuffleComment(const MachineInstr *MI, unsigned SrcOp1Idx,
1391 unsigned SrcOp2Idx, ArrayRef<int> Mask) {
1392 std::string Comment;
1393
1394 // Compute the name for a register. This is really goofy because we have
1395 // multiple instruction printers that could (in theory) use different
1396 // names. Fortunately most people use the ATT style (outside of Windows)
1397 // and they actually agree on register naming here. Ultimately, this is
1398 // a comment, and so its OK if it isn't perfect.
1399 auto GetRegisterName = [](unsigned RegNum) -> StringRef {
1400 return X86ATTInstPrinter::getRegisterName(RegNum);
1401 };
1402
1403 const MachineOperand &DstOp = MI->getOperand(0);
1404 const MachineOperand &SrcOp1 = MI->getOperand(SrcOp1Idx);
1405 const MachineOperand &SrcOp2 = MI->getOperand(SrcOp2Idx);
1406
1407 StringRef DstName = DstOp.isReg() ? GetRegisterName(DstOp.getReg()) : "mem";
1408 StringRef Src1Name =
1409 SrcOp1.isReg() ? GetRegisterName(SrcOp1.getReg()) : "mem";
1410 StringRef Src2Name =
1411 SrcOp2.isReg() ? GetRegisterName(SrcOp2.getReg()) : "mem";
1412
1413 // One source operand, fix the mask to print all elements in one span.
1414 SmallVector<int, 8> ShuffleMask(Mask.begin(), Mask.end());
1415 if (Src1Name == Src2Name)
1416 for (int i = 0, e = ShuffleMask.size(); i != e; ++i)
1417 if (ShuffleMask[i] >= e)
1418 ShuffleMask[i] -= e;
1419
1420 raw_string_ostream CS(Comment);
1421 CS << DstName;
1422
1423 // Handle AVX512 MASK/MASXZ write mask comments.
1424 // MASK: zmmX {%kY}
1425 // MASKZ: zmmX {%kY} {z}
1426 if (SrcOp1Idx > 1) {
1427 assert((SrcOp1Idx == 2 || SrcOp1Idx == 3) && "Unexpected writemask")(((SrcOp1Idx == 2 || SrcOp1Idx == 3) && "Unexpected writemask"
) ? static_cast<void> (0) : __assert_fail ("(SrcOp1Idx == 2 || SrcOp1Idx == 3) && \"Unexpected writemask\""
, "/build/llvm-toolchain-snapshot-9~svn358520/lib/Target/X86/X86MCInstLower.cpp"
, 1427, __PRETTY_FUNCTION__))
;
1428
1429 const MachineOperand &WriteMaskOp = MI->getOperand(SrcOp1Idx - 1);
1430 if (WriteMaskOp.isReg()) {
1431 CS << " {%" << GetRegisterName(WriteMaskOp.getReg()) << "}";
1432
1433 if (SrcOp1Idx == 2) {
1434 CS << " {z}";
1435 }
1436 }
1437 }
1438
1439 CS << " = ";
1440
1441 for (int i = 0, e = ShuffleMask.size(); i != e; ++i) {
1442 if (i != 0)
1443 CS << ",";
1444 if (ShuffleMask[i] == SM_SentinelZero) {
1445 CS << "zero";
1446 continue;
1447 }
1448
1449 // Otherwise, it must come from src1 or src2. Print the span of elements
1450 // that comes from this src.
1451 bool isSrc1 = ShuffleMask[i] < (int)e;
1452 CS << (isSrc1 ? Src1Name : Src2Name) << '[';
1453
1454 bool IsFirst = true;
1455 while (i != e && ShuffleMask[i] != SM_SentinelZero &&
1456 (ShuffleMask[i] < (int)e) == isSrc1) {
1457 if (!IsFirst)
1458 CS << ',';
1459 else
1460 IsFirst = false;
1461 if (ShuffleMask[i] == SM_SentinelUndef)
1462 CS << "u";
1463 else
1464 CS << ShuffleMask[i] % (int)e;
1465 ++i;
1466 }
1467 CS << ']';
1468 --i; // For loop increments element #.
1469 }
1470 CS.flush();
1471
1472 return Comment;
1473}
1474
1475static void printConstant(const APInt &Val, raw_ostream &CS) {
1476 if (Val.getBitWidth() <= 64) {
1477 CS << Val.getZExtValue();
1478 } else {
1479 // print multi-word constant as (w0,w1)
1480 CS << "(";
1481 for (int i = 0, N = Val.getNumWords(); i < N; ++i) {
1482 if (i > 0)
1483 CS << ",";
1484 CS << Val.getRawData()[i];
1485 }
1486 CS << ")";
1487 }
1488}
1489
1490static void printConstant(const APFloat &Flt, raw_ostream &CS) {
1491 SmallString<32> Str;
1492 // Force scientific notation to distinquish from integers.
1493 Flt.toString(Str, 0, 0);
1494 CS << Str;
1495}
1496
1497static void printConstant(const Constant *COp, raw_ostream &CS) {
1498 if (isa<UndefValue>(COp)) {
1499 CS << "u";
1500 } else if (auto *CI = dyn_cast<ConstantInt>(COp)) {
1501 printConstant(CI->getValue(), CS);
1502 } else if (auto *CF = dyn_cast<ConstantFP>(COp)) {
1503 printConstant(CF->getValueAPF(), CS);
1504 } else {
1505 CS << "?";
1506 }
1507}
1508
1509void X86AsmPrinter::EmitSEHInstruction(const MachineInstr *MI) {
1510 assert(MF->hasWinCFI() && "SEH_ instruction in function without WinCFI?")((MF->hasWinCFI() && "SEH_ instruction in function without WinCFI?"
) ? static_cast<void> (0) : __assert_fail ("MF->hasWinCFI() && \"SEH_ instruction in function without WinCFI?\""
, "/build/llvm-toolchain-snapshot-9~svn358520/lib/Target/X86/X86MCInstLower.cpp"
, 1510, __PRETTY_FUNCTION__))
;
1511 assert(getSubtarget().isOSWindows() && "SEH_ instruction Windows only")((getSubtarget().isOSWindows() && "SEH_ instruction Windows only"
) ? static_cast<void> (0) : __assert_fail ("getSubtarget().isOSWindows() && \"SEH_ instruction Windows only\""
, "/build/llvm-toolchain-snapshot-9~svn358520/lib/Target/X86/X86MCInstLower.cpp"
, 1511, __PRETTY_FUNCTION__))
;
1512 const X86RegisterInfo *RI =
1513 MF->getSubtarget<X86Subtarget>().getRegisterInfo();
1514
1515 // Use the .cv_fpo directives if we're emitting CodeView on 32-bit x86.
1516 if (EmitFPOData) {
1517 X86TargetStreamer *XTS =
1518 static_cast<X86TargetStreamer *>(OutStreamer->getTargetStreamer());
1519 switch (MI->getOpcode()) {
1520 case X86::SEH_PushReg:
1521 XTS->emitFPOPushReg(MI->getOperand(0).getImm());
1522 break;
1523 case X86::SEH_StackAlloc:
1524 XTS->emitFPOStackAlloc(MI->getOperand(0).getImm());
1525 break;
1526 case X86::SEH_StackAlign:
1527 XTS->emitFPOStackAlign(MI->getOperand(0).getImm());
1528 break;
1529 case X86::SEH_SetFrame:
1530 assert(MI->getOperand(1).getImm() == 0 &&((MI->getOperand(1).getImm() == 0 && ".cv_fpo_setframe takes no offset"
) ? static_cast<void> (0) : __assert_fail ("MI->getOperand(1).getImm() == 0 && \".cv_fpo_setframe takes no offset\""
, "/build/llvm-toolchain-snapshot-9~svn358520/lib/Target/X86/X86MCInstLower.cpp"
, 1531, __PRETTY_FUNCTION__))
1531 ".cv_fpo_setframe takes no offset")((MI->getOperand(1).getImm() == 0 && ".cv_fpo_setframe takes no offset"
) ? static_cast<void> (0) : __assert_fail ("MI->getOperand(1).getImm() == 0 && \".cv_fpo_setframe takes no offset\""
, "/build/llvm-toolchain-snapshot-9~svn358520/lib/Target/X86/X86MCInstLower.cpp"
, 1531, __PRETTY_FUNCTION__))
;
1532 XTS->emitFPOSetFrame(MI->getOperand(0).getImm());
1533 break;
1534 case X86::SEH_EndPrologue:
1535 XTS->emitFPOEndPrologue();
1536 break;
1537 case X86::SEH_SaveReg:
1538 case X86::SEH_SaveXMM:
1539 case X86::SEH_PushFrame:
1540 llvm_unreachable("SEH_ directive incompatible with FPO")::llvm::llvm_unreachable_internal("SEH_ directive incompatible with FPO"
, "/build/llvm-toolchain-snapshot-9~svn358520/lib/Target/X86/X86MCInstLower.cpp"
, 1540)
;
1541 break;
1542 default:
1543 llvm_unreachable("expected SEH_ instruction")::llvm::llvm_unreachable_internal("expected SEH_ instruction"
, "/build/llvm-toolchain-snapshot-9~svn358520/lib/Target/X86/X86MCInstLower.cpp"
, 1543)
;
1544 }
1545 return;
1546 }
1547
1548 // Otherwise, use the .seh_ directives for all other Windows platforms.
1549 switch (MI->getOpcode()) {
1550 case X86::SEH_PushReg:
1551 OutStreamer->EmitWinCFIPushReg(
1552 RI->getSEHRegNum(MI->getOperand(0).getImm()));
1553 break;
1554
1555 case X86::SEH_SaveReg:
1556 OutStreamer->EmitWinCFISaveReg(RI->getSEHRegNum(MI->getOperand(0).getImm()),
1557 MI->getOperand(1).getImm());
1558 break;
1559
1560 case X86::SEH_SaveXMM:
1561 OutStreamer->EmitWinCFISaveXMM(RI->getSEHRegNum(MI->getOperand(0).getImm()),
1562 MI->getOperand(1).getImm());
1563 break;
1564
1565 case X86::SEH_StackAlloc:
1566 OutStreamer->EmitWinCFIAllocStack(MI->getOperand(0).getImm());
1567 break;
1568
1569 case X86::SEH_SetFrame:
1570 OutStreamer->EmitWinCFISetFrame(
1571 RI->getSEHRegNum(MI->getOperand(0).getImm()),
1572 MI->getOperand(1).getImm());
1573 break;
1574
1575 case X86::SEH_PushFrame:
1576 OutStreamer->EmitWinCFIPushFrame(MI->getOperand(0).getImm());
1577 break;
1578
1579 case X86::SEH_EndPrologue:
1580 OutStreamer->EmitWinCFIEndProlog();
1581 break;
1582
1583 default:
1584 llvm_unreachable("expected SEH_ instruction")::llvm::llvm_unreachable_internal("expected SEH_ instruction"
, "/build/llvm-toolchain-snapshot-9~svn358520/lib/Target/X86/X86MCInstLower.cpp"
, 1584)
;
1585 }
1586}
1587
1588static unsigned getRegisterWidth(const MCOperandInfo &Info) {
1589 if (Info.RegClass == X86::VR128RegClassID ||
1590 Info.RegClass == X86::VR128XRegClassID)
1591 return 128;
1592 if (Info.RegClass == X86::VR256RegClassID ||
1593 Info.RegClass == X86::VR256XRegClassID)
1594 return 256;
1595 if (Info.RegClass == X86::VR512RegClassID)
1596 return 512;
1597 llvm_unreachable("Unknown register class!")::llvm::llvm_unreachable_internal("Unknown register class!", "/build/llvm-toolchain-snapshot-9~svn358520/lib/Target/X86/X86MCInstLower.cpp"
, 1597)
;
1598}
1599
1600void X86AsmPrinter::EmitInstruction(const MachineInstr *MI) {
1601 X86MCInstLower MCInstLowering(*MF, *this);
1602 const X86RegisterInfo *RI =
1603 MF->getSubtarget<X86Subtarget>().getRegisterInfo();
1604
1605 // Add a comment about EVEX-2-VEX compression for AVX-512 instrs that
1606 // are compressed from EVEX encoding to VEX encoding.
1607 if (TM.Options.MCOptions.ShowMCEncoding) {
1608 if (MI->getAsmPrinterFlags() & X86::AC_EVEX_2_VEX)
1609 OutStreamer->AddComment("EVEX TO VEX Compression ", false);
1610 }
1611
1612 switch (MI->getOpcode()) {
1613 case TargetOpcode::DBG_VALUE:
1614 llvm_unreachable("Should be handled target independently")::llvm::llvm_unreachable_internal("Should be handled target independently"
, "/build/llvm-toolchain-snapshot-9~svn358520/lib/Target/X86/X86MCInstLower.cpp"
, 1614)
;
1615
1616 // Emit nothing here but a comment if we can.
1617 case X86::Int_MemBarrier:
1618 OutStreamer->emitRawComment("MEMBARRIER");
1619 return;
1620
1621 case X86::EH_RETURN:
1622 case X86::EH_RETURN64: {
1623 // Lower these as normal, but add some comments.
1624 unsigned Reg = MI->getOperand(0).getReg();
1625 OutStreamer->AddComment(StringRef("eh_return, addr: %") +
1626 X86ATTInstPrinter::getRegisterName(Reg));
1627 break;
1628 }
1629 case X86::CLEANUPRET: {
1630 // Lower these as normal, but add some comments.
1631 OutStreamer->AddComment("CLEANUPRET");
1632 break;
1633 }
1634
1635 case X86::CATCHRET: {
1636 // Lower these as normal, but add some comments.
1637 OutStreamer->AddComment("CATCHRET");
1638 break;
1639 }
1640
1641 case X86::TAILJMPr:
1642 case X86::TAILJMPm:
1643 case X86::TAILJMPd:
1644 case X86::TAILJMPd_CC:
1645 case X86::TAILJMPr64:
1646 case X86::TAILJMPm64:
1647 case X86::TAILJMPd64:
1648 case X86::TAILJMPd64_CC:
1649 case X86::TAILJMPr64_REX:
1650 case X86::TAILJMPm64_REX:
1651 // Lower these as normal, but add some comments.
1652 OutStreamer->AddComment("TAILCALL");
1653 break;
1654
1655 case X86::TLS_addr32:
1656 case X86::TLS_addr64:
1657 case X86::TLS_base_addr32:
1658 case X86::TLS_base_addr64:
1659 return LowerTlsAddr(MCInstLowering, *MI);
1660
1661 case X86::MOVPC32r: {
1662 // This is a pseudo op for a two instruction sequence with a label, which
1663 // looks like:
1664 // call "L1$pb"
1665 // "L1$pb":
1666 // popl %esi
1667
1668 // Emit the call.
1669 MCSymbol *PICBase = MF->getPICBaseSymbol();
1670 // FIXME: We would like an efficient form for this, so we don't have to do a
1671 // lot of extra uniquing.
1672 EmitAndCountInstruction(
1673 MCInstBuilder(X86::CALLpcrel32)
1674 .addExpr(MCSymbolRefExpr::create(PICBase, OutContext)));
1675
1676 const X86FrameLowering *FrameLowering =
1677 MF->getSubtarget<X86Subtarget>().getFrameLowering();
1678 bool hasFP = FrameLowering->hasFP(*MF);
1679
1680 // TODO: This is needed only if we require precise CFA.
1681 bool HasActiveDwarfFrame = OutStreamer->getNumFrameInfos() &&
1682 !OutStreamer->getDwarfFrameInfos().back().End;
1683
1684 int stackGrowth = -RI->getSlotSize();
1685
1686 if (HasActiveDwarfFrame && !hasFP) {
1687 OutStreamer->EmitCFIAdjustCfaOffset(-stackGrowth);
1688 }
1689
1690 // Emit the label.
1691 OutStreamer->EmitLabel(PICBase);
1692
1693 // popl $reg
1694 EmitAndCountInstruction(
1695 MCInstBuilder(X86::POP32r).addReg(MI->getOperand(0).getReg()));
1696
1697 if (HasActiveDwarfFrame && !hasFP) {
1698 OutStreamer->EmitCFIAdjustCfaOffset(stackGrowth);
1699 }
1700 return;
1701 }
1702
1703 case X86::ADD32ri: {
1704 // Lower the MO_GOT_ABSOLUTE_ADDRESS form of ADD32ri.
1705 if (MI->getOperand(2).getTargetFlags() != X86II::MO_GOT_ABSOLUTE_ADDRESS)
1706 break;
1707
1708 // Okay, we have something like:
1709 // EAX = ADD32ri EAX, MO_GOT_ABSOLUTE_ADDRESS(@MYGLOBAL)
1710
1711 // For this, we want to print something like:
1712 // MYGLOBAL + (. - PICBASE)
1713 // However, we can't generate a ".", so just emit a new label here and refer
1714 // to it.
1715 MCSymbol *DotSym = OutContext.createTempSymbol();
1716 OutStreamer->EmitLabel(DotSym);
1717
1718 // Now that we have emitted the label, lower the complex operand expression.
1719 MCSymbol *OpSym = MCInstLowering.GetSymbolFromOperand(MI->getOperand(2));
1720
1721 const MCExpr *DotExpr = MCSymbolRefExpr::create(DotSym, OutContext);
1722 const MCExpr *PICBase =
1723 MCSymbolRefExpr::create(MF->getPICBaseSymbol(), OutContext);
1724 DotExpr = MCBinaryExpr::createSub(DotExpr, PICBase, OutContext);
1725
1726 DotExpr = MCBinaryExpr::createAdd(
1727 MCSymbolRefExpr::create(OpSym, OutContext), DotExpr, OutContext);
1728
1729 EmitAndCountInstruction(MCInstBuilder(X86::ADD32ri)
1730 .addReg(MI->getOperand(0).getReg())
1731 .addReg(MI->getOperand(1).getReg())
1732 .addExpr(DotExpr));
1733 return;
1734 }
1735 case TargetOpcode::STATEPOINT:
1736 return LowerSTATEPOINT(*MI, MCInstLowering);
1737
1738 case TargetOpcode::FAULTING_OP:
1739 return LowerFAULTING_OP(*MI, MCInstLowering);
1740
1741 case TargetOpcode::FENTRY_CALL:
1742 return LowerFENTRY_CALL(*MI, MCInstLowering);
1743
1744 case TargetOpcode::PATCHABLE_OP:
1745 return LowerPATCHABLE_OP(*MI, MCInstLowering);
1746
1747 case TargetOpcode::STACKMAP:
1748 return LowerSTACKMAP(*MI);
1749
1750 case TargetOpcode::PATCHPOINT:
1751 return LowerPATCHPOINT(*MI, MCInstLowering);
1752
1753 case TargetOpcode::PATCHABLE_FUNCTION_ENTER:
1754 return LowerPATCHABLE_FUNCTION_ENTER(*MI, MCInstLowering);
1755
1756 case TargetOpcode::PATCHABLE_RET:
1757 return LowerPATCHABLE_RET(*MI, MCInstLowering);
1758
1759 case TargetOpcode::PATCHABLE_TAIL_CALL:
1760 return LowerPATCHABLE_TAIL_CALL(*MI, MCInstLowering);
1761
1762 case TargetOpcode::PATCHABLE_EVENT_CALL:
1763 return LowerPATCHABLE_EVENT_CALL(*MI, MCInstLowering);
1764
1765 case TargetOpcode::PATCHABLE_TYPED_EVENT_CALL:
1766 return LowerPATCHABLE_TYPED_EVENT_CALL(*MI, MCInstLowering);
1767
1768 case X86::MORESTACK_RET:
1769 EmitAndCountInstruction(MCInstBuilder(getRetOpcode(*Subtarget)));
1770 return;
1771
1772 case X86::MORESTACK_RET_RESTORE_R10:
1773 // Return, then restore R10.
1774 EmitAndCountInstruction(MCInstBuilder(getRetOpcode(*Subtarget)));
1775 EmitAndCountInstruction(
1776 MCInstBuilder(X86::MOV64rr).addReg(X86::R10).addReg(X86::RAX));
1777 return;
1778
1779 case X86::SEH_PushReg:
1780 case X86::SEH_SaveReg:
1781 case X86::SEH_SaveXMM:
1782 case X86::SEH_StackAlloc:
1783 case X86::SEH_StackAlign:
1784 case X86::SEH_SetFrame:
1785 case X86::SEH_PushFrame:
1786 case X86::SEH_EndPrologue:
1787 EmitSEHInstruction(MI);
1788 return;
1789
1790 case X86::SEH_Epilogue: {
1791 assert(MF->hasWinCFI() && "SEH_ instruction in function without WinCFI?")((MF->hasWinCFI() && "SEH_ instruction in function without WinCFI?"
) ? static_cast<void> (0) : __assert_fail ("MF->hasWinCFI() && \"SEH_ instruction in function without WinCFI?\""
, "/build/llvm-toolchain-snapshot-9~svn358520/lib/Target/X86/X86MCInstLower.cpp"
, 1791, __PRETTY_FUNCTION__))
;
1792 MachineBasicBlock::const_iterator MBBI(MI);
1793 // Check if preceded by a call and emit nop if so.
1794 for (MBBI = PrevCrossBBInst(MBBI);
1795 MBBI != MachineBasicBlock::const_iterator();
1796 MBBI = PrevCrossBBInst(MBBI)) {
1797 // Conservatively assume that pseudo instructions don't emit code and keep
1798 // looking for a call. We may emit an unnecessary nop in some cases.
1799 if (!MBBI->isPseudo()) {
1800 if (MBBI->isCall())
1801 EmitAndCountInstruction(MCInstBuilder(X86::NOOP));
1802 break;
1803 }
1804 }
1805 return;
1806 }
1807
1808 // Lower PSHUFB and VPERMILP normally but add a comment if we can find
1809 // a constant shuffle mask. We won't be able to do this at the MC layer
1810 // because the mask isn't an immediate.
1811 case X86::PSHUFBrm:
1812 case X86::VPSHUFBrm:
1813 case X86::VPSHUFBYrm:
1814 case X86::VPSHUFBZ128rm:
1815 case X86::VPSHUFBZ128rmk:
1816 case X86::VPSHUFBZ128rmkz:
1817 case X86::VPSHUFBZ256rm:
1818 case X86::VPSHUFBZ256rmk:
1819 case X86::VPSHUFBZ256rmkz:
1820 case X86::VPSHUFBZrm:
1821 case X86::VPSHUFBZrmk:
1822 case X86::VPSHUFBZrmkz: {
1823 if (!OutStreamer->isVerboseAsm())
1824 break;
1825 unsigned SrcIdx, MaskIdx;
1826 switch (MI->getOpcode()) {
1827 default: llvm_unreachable("Invalid opcode")::llvm::llvm_unreachable_internal("Invalid opcode", "/build/llvm-toolchain-snapshot-9~svn358520/lib/Target/X86/X86MCInstLower.cpp"
, 1827)
;
1828 case X86::PSHUFBrm:
1829 case X86::VPSHUFBrm:
1830 case X86::VPSHUFBYrm:
1831 case X86::VPSHUFBZ128rm:
1832 case X86::VPSHUFBZ256rm:
1833 case X86::VPSHUFBZrm:
1834 SrcIdx = 1; MaskIdx = 5; break;
1835 case X86::VPSHUFBZ128rmkz:
1836 case X86::VPSHUFBZ256rmkz:
1837 case X86::VPSHUFBZrmkz:
1838 SrcIdx = 2; MaskIdx = 6; break;
1839 case X86::VPSHUFBZ128rmk:
1840 case X86::VPSHUFBZ256rmk:
1841 case X86::VPSHUFBZrmk:
1842 SrcIdx = 3; MaskIdx = 7; break;
1843 }
1844
1845 assert(MI->getNumOperands() >= 6 &&((MI->getNumOperands() >= 6 && "We should always have at least 6 operands!"
) ? static_cast<void> (0) : __assert_fail ("MI->getNumOperands() >= 6 && \"We should always have at least 6 operands!\""
, "/build/llvm-toolchain-snapshot-9~svn358520/lib/Target/X86/X86MCInstLower.cpp"
, 1846, __PRETTY_FUNCTION__))
1846 "We should always have at least 6 operands!")((MI->getNumOperands() >= 6 && "We should always have at least 6 operands!"
) ? static_cast<void> (0) : __assert_fail ("MI->getNumOperands() >= 6 && \"We should always have at least 6 operands!\""
, "/build/llvm-toolchain-snapshot-9~svn358520/lib/Target/X86/X86MCInstLower.cpp"
, 1846, __PRETTY_FUNCTION__))
;
1847
1848 const MachineOperand &MaskOp = MI->getOperand(MaskIdx);
1849 if (auto *C = getConstantFromPool(*MI, MaskOp)) {
1850 unsigned Width = getRegisterWidth(MI->getDesc().OpInfo[0]);
1851 SmallVector<int, 64> Mask;
1852 DecodePSHUFBMask(C, Width, Mask);
1853 if (!Mask.empty())
1854 OutStreamer->AddComment(getShuffleComment(MI, SrcIdx, SrcIdx, Mask));
1855 }
1856 break;
1857 }
1858
1859 case X86::VPERMILPSrm:
1860 case X86::VPERMILPSYrm:
1861 case X86::VPERMILPSZ128rm:
1862 case X86::VPERMILPSZ128rmk:
1863 case X86::VPERMILPSZ128rmkz:
1864 case X86::VPERMILPSZ256rm:
1865 case X86::VPERMILPSZ256rmk:
1866 case X86::VPERMILPSZ256rmkz:
1867 case X86::VPERMILPSZrm:
1868 case X86::VPERMILPSZrmk:
1869 case X86::VPERMILPSZrmkz:
1870 case X86::VPERMILPDrm:
1871 case X86::VPERMILPDYrm:
1872 case X86::VPERMILPDZ128rm:
1873 case X86::VPERMILPDZ128rmk:
1874 case X86::VPERMILPDZ128rmkz:
1875 case X86::VPERMILPDZ256rm:
1876 case X86::VPERMILPDZ256rmk:
1877 case X86::VPERMILPDZ256rmkz:
1878 case X86::VPERMILPDZrm:
1879 case X86::VPERMILPDZrmk:
1880 case X86::VPERMILPDZrmkz: {
1881 if (!OutStreamer->isVerboseAsm())
1882 break;
1883 unsigned SrcIdx, MaskIdx;
1884 unsigned ElSize;
1885 switch (MI->getOpcode()) {
1886 default: llvm_unreachable("Invalid opcode")::llvm::llvm_unreachable_internal("Invalid opcode", "/build/llvm-toolchain-snapshot-9~svn358520/lib/Target/X86/X86MCInstLower.cpp"
, 1886)
;
1887 case X86::VPERMILPSrm:
1888 case X86::VPERMILPSYrm:
1889 case X86::VPERMILPSZ128rm:
1890 case X86::VPERMILPSZ256rm:
1891 case X86::VPERMILPSZrm:
1892 SrcIdx = 1; MaskIdx = 5; ElSize = 32; break;
1893 case X86::VPERMILPSZ128rmkz:
1894 case X86::VPERMILPSZ256rmkz:
1895 case X86::VPERMILPSZrmkz:
1896 SrcIdx = 2; MaskIdx = 6; ElSize = 32; break;
1897 case X86::VPERMILPSZ128rmk:
1898 case X86::VPERMILPSZ256rmk:
1899 case X86::VPERMILPSZrmk:
1900 SrcIdx = 3; MaskIdx = 7; ElSize = 32; break;
1901 case X86::VPERMILPDrm:
1902 case X86::VPERMILPDYrm:
1903 case X86::VPERMILPDZ128rm:
1904 case X86::VPERMILPDZ256rm:
1905 case X86::VPERMILPDZrm:
1906 SrcIdx = 1; MaskIdx = 5; ElSize = 64; break;
1907 case X86::VPERMILPDZ128rmkz:
1908 case X86::VPERMILPDZ256rmkz:
1909 case X86::VPERMILPDZrmkz:
1910 SrcIdx = 2; MaskIdx = 6; ElSize = 64; break;
1911 case X86::VPERMILPDZ128rmk:
1912 case X86::VPERMILPDZ256rmk:
1913 case X86::VPERMILPDZrmk:
1914 SrcIdx = 3; MaskIdx = 7; ElSize = 64; break;
1915 }
1916
1917 assert(MI->getNumOperands() >= 6 &&((MI->getNumOperands() >= 6 && "We should always have at least 6 operands!"
) ? static_cast<void> (0) : __assert_fail ("MI->getNumOperands() >= 6 && \"We should always have at least 6 operands!\""
, "/build/llvm-toolchain-snapshot-9~svn358520/lib/Target/X86/X86MCInstLower.cpp"
, 1918, __PRETTY_FUNCTION__))
1918 "We should always have at least 6 operands!")((MI->getNumOperands() >= 6 && "We should always have at least 6 operands!"
) ? static_cast<void> (0) : __assert_fail ("MI->getNumOperands() >= 6 && \"We should always have at least 6 operands!\""
, "/build/llvm-toolchain-snapshot-9~svn358520/lib/Target/X86/X86MCInstLower.cpp"
, 1918, __PRETTY_FUNCTION__))
;
1919
1920 const MachineOperand &MaskOp = MI->getOperand(MaskIdx);
1921 if (auto *C = getConstantFromPool(*MI, MaskOp)) {
1922 unsigned Width = getRegisterWidth(MI->getDesc().OpInfo[0]);
1923 SmallVector<int, 16> Mask;
1924 DecodeVPERMILPMask(C, ElSize, Width, Mask);
1925 if (!Mask.empty())
1926 OutStreamer->AddComment(getShuffleComment(MI, SrcIdx, SrcIdx, Mask));
1927 }
1928 break;
1929 }
1930
1931 case X86::VPERMIL2PDrm:
1932 case X86::VPERMIL2PSrm:
1933 case X86::VPERMIL2PDYrm:
1934 case X86::VPERMIL2PSYrm: {
1935 if (!OutStreamer->isVerboseAsm())
1936 break;
1937 assert(MI->getNumOperands() >= 8 &&((MI->getNumOperands() >= 8 && "We should always have at least 8 operands!"
) ? static_cast<void> (0) : __assert_fail ("MI->getNumOperands() >= 8 && \"We should always have at least 8 operands!\""
, "/build/llvm-toolchain-snapshot-9~svn358520/lib/Target/X86/X86MCInstLower.cpp"
, 1938, __PRETTY_FUNCTION__))
1938 "We should always have at least 8 operands!")((MI->getNumOperands() >= 8 && "We should always have at least 8 operands!"
) ? static_cast<void> (0) : __assert_fail ("MI->getNumOperands() >= 8 && \"We should always have at least 8 operands!\""
, "/build/llvm-toolchain-snapshot-9~svn358520/lib/Target/X86/X86MCInstLower.cpp"
, 1938, __PRETTY_FUNCTION__))
;
1939
1940 const MachineOperand &CtrlOp = MI->getOperand(MI->getNumOperands() - 1);
1941 if (!CtrlOp.isImm())
1942 break;
1943
1944 unsigned ElSize;
1945 switch (MI->getOpcode()) {
1946 default: llvm_unreachable("Invalid opcode")::llvm::llvm_unreachable_internal("Invalid opcode", "/build/llvm-toolchain-snapshot-9~svn358520/lib/Target/X86/X86MCInstLower.cpp"
, 1946)
;
1947 case X86::VPERMIL2PSrm: case X86::VPERMIL2PSYrm: ElSize = 32; break;
1948 case X86::VPERMIL2PDrm: case X86::VPERMIL2PDYrm: ElSize = 64; break;
1949 }
1950
1951 const MachineOperand &MaskOp = MI->getOperand(6);
1952 if (auto *C = getConstantFromPool(*MI, MaskOp)) {
1953 unsigned Width = getRegisterWidth(MI->getDesc().OpInfo[0]);
1954 SmallVector<int, 16> Mask;
1955 DecodeVPERMIL2PMask(C, (unsigned)CtrlOp.getImm(), ElSize, Width, Mask);
1956 if (!Mask.empty())
1957 OutStreamer->AddComment(getShuffleComment(MI, 1, 2, Mask));
1958 }
1959 break;
1960 }
1961
1962 case X86::VPPERMrrm: {
1963 if (!OutStreamer->isVerboseAsm())
1964 break;
1965 assert(MI->getNumOperands() >= 7 &&((MI->getNumOperands() >= 7 && "We should always have at least 7 operands!"
) ? static_cast<void> (0) : __assert_fail ("MI->getNumOperands() >= 7 && \"We should always have at least 7 operands!\""
, "/build/llvm-toolchain-snapshot-9~svn358520/lib/Target/X86/X86MCInstLower.cpp"
, 1966, __PRETTY_FUNCTION__))
1966 "We should always have at least 7 operands!")((MI->getNumOperands() >= 7 && "We should always have at least 7 operands!"
) ? static_cast<void> (0) : __assert_fail ("MI->getNumOperands() >= 7 && \"We should always have at least 7 operands!\""
, "/build/llvm-toolchain-snapshot-9~svn358520/lib/Target/X86/X86MCInstLower.cpp"
, 1966, __PRETTY_FUNCTION__))
;
1967
1968 const MachineOperand &MaskOp = MI->getOperand(6);
1969 if (auto *C = getConstantFromPool(*MI, MaskOp)) {
1970 unsigned Width = getRegisterWidth(MI->getDesc().OpInfo[0]);
1971 SmallVector<int, 16> Mask;
1972 DecodeVPPERMMask(C, Width, Mask);
1973 if (!Mask.empty())
1974 OutStreamer->AddComment(getShuffleComment(MI, 1, 2, Mask));
1975 }
1976 break;
1977 }
1978
1979 case X86::MMX_MOVQ64rm: {
1980 if (!OutStreamer->isVerboseAsm())
1981 break;
1982 if (MI->getNumOperands() <= 4)
1983 break;
1984 if (auto *C = getConstantFromPool(*MI, MI->getOperand(4))) {
1985 std::string Comment;
1986 raw_string_ostream CS(Comment);
1987 const MachineOperand &DstOp = MI->getOperand(0);
1988 CS << X86ATTInstPrinter::getRegisterName(DstOp.getReg()) << " = ";
1989 if (auto *CF = dyn_cast<ConstantFP>(C)) {
1990 CS << "0x" << CF->getValueAPF().bitcastToAPInt().toString(16, false);
1991 OutStreamer->AddComment(CS.str());
1992 }
1993 }
1994 break;
1995 }
1996
1997#define MOV_CASE(Prefix, Suffix)case X86::PrefixMOVAPDSuffixrm: case X86::PrefixMOVAPSSuffixrm
: case X86::PrefixMOVUPDSuffixrm: case X86::PrefixMOVUPSSuffixrm
: case X86::PrefixMOVDQASuffixrm: case X86::PrefixMOVDQUSuffixrm
:
\
1998 case X86::Prefix##MOVAPD##Suffix##rm: \
1999 case X86::Prefix##MOVAPS##Suffix##rm: \
2000 case X86::Prefix##MOVUPD##Suffix##rm: \
2001 case X86::Prefix##MOVUPS##Suffix##rm: \
2002 case X86::Prefix##MOVDQA##Suffix##rm: \
2003 case X86::Prefix##MOVDQU##Suffix##rm:
2004
2005#define MOV_AVX512_CASE(Suffix)case X86::VMOVDQA64Suffixrm: case X86::VMOVDQA32Suffixrm: case
X86::VMOVDQU64Suffixrm: case X86::VMOVDQU32Suffixrm: case X86
::VMOVDQU16Suffixrm: case X86::VMOVDQU8Suffixrm: case X86::VMOVAPSSuffixrm
: case X86::VMOVAPDSuffixrm: case X86::VMOVUPSSuffixrm: case X86
::VMOVUPDSuffixrm:
\
2006 case X86::VMOVDQA64##Suffix##rm: \
2007 case X86::VMOVDQA32##Suffix##rm: \
2008 case X86::VMOVDQU64##Suffix##rm: \
2009 case X86::VMOVDQU32##Suffix##rm: \
2010 case X86::VMOVDQU16##Suffix##rm: \
2011 case X86::VMOVDQU8##Suffix##rm: \
2012 case X86::VMOVAPS##Suffix##rm: \
2013 case X86::VMOVAPD##Suffix##rm: \
2014 case X86::VMOVUPS##Suffix##rm: \
2015 case X86::VMOVUPD##Suffix##rm:
2016
2017#define CASE_ALL_MOV_RM()case X86::MOVAPDrm: case X86::MOVAPSrm: case X86::MOVUPDrm: case
X86::MOVUPSrm: case X86::MOVDQArm: case X86::MOVDQUrm: case X86
::VMOVAPDrm: case X86::VMOVAPSrm: case X86::VMOVUPDrm: case X86
::VMOVUPSrm: case X86::VMOVDQArm: case X86::VMOVDQUrm: case X86
::VMOVAPDYrm: case X86::VMOVAPSYrm: case X86::VMOVUPDYrm: case
X86::VMOVUPSYrm: case X86::VMOVDQAYrm: case X86::VMOVDQUYrm:
case X86::VMOVDQA64Zrm: case X86::VMOVDQA32Zrm: case X86::VMOVDQU64Zrm
: case X86::VMOVDQU32Zrm: case X86::VMOVDQU16Zrm: case X86::VMOVDQU8Zrm
: case X86::VMOVAPSZrm: case X86::VMOVAPDZrm: case X86::VMOVUPSZrm
: case X86::VMOVUPDZrm: case X86::VMOVDQA64Z256rm: case X86::
VMOVDQA32Z256rm: case X86::VMOVDQU64Z256rm: case X86::VMOVDQU32Z256rm
: case X86::VMOVDQU16Z256rm: case X86::VMOVDQU8Z256rm: case X86
::VMOVAPSZ256rm: case X86::VMOVAPDZ256rm: case X86::VMOVUPSZ256rm
: case X86::VMOVUPDZ256rm: case X86::VMOVDQA64Z128rm: case X86
::VMOVDQA32Z128rm: case X86::VMOVDQU64Z128rm: case X86::VMOVDQU32Z128rm
: case X86::VMOVDQU16Z128rm: case X86::VMOVDQU8Z128rm: case X86
::VMOVAPSZ128rm: case X86::VMOVAPDZ128rm: case X86::VMOVUPSZ128rm
: case X86::VMOVUPDZ128rm:
\
2018 MOV_CASE(, )case X86::MOVAPDrm: case X86::MOVAPSrm: case X86::MOVUPDrm: case
X86::MOVUPSrm: case X86::MOVDQArm: case X86::MOVDQUrm:
/* SSE */ \
2019 MOV_CASE(V, )case X86::VMOVAPDrm: case X86::VMOVAPSrm: case X86::VMOVUPDrm
: case X86::VMOVUPSrm: case X86::VMOVDQArm: case X86::VMOVDQUrm
:
/* AVX-128 */ \
2020 MOV_CASE(V, Y)case X86::VMOVAPDYrm: case X86::VMOVAPSYrm: case X86::VMOVUPDYrm
: case X86::VMOVUPSYrm: case X86::VMOVDQAYrm: case X86::VMOVDQUYrm
:
/* AVX-256 */ \
2021 MOV_AVX512_CASE(Z)case X86::VMOVDQA64Zrm: case X86::VMOVDQA32Zrm: case X86::VMOVDQU64Zrm
: case X86::VMOVDQU32Zrm: case X86::VMOVDQU16Zrm: case X86::VMOVDQU8Zrm
: case X86::VMOVAPSZrm: case X86::VMOVAPDZrm: case X86::VMOVUPSZrm
: case X86::VMOVUPDZrm:
\
2022 MOV_AVX512_CASE(Z256)case X86::VMOVDQA64Z256rm: case X86::VMOVDQA32Z256rm: case X86
::VMOVDQU64Z256rm: case X86::VMOVDQU32Z256rm: case X86::VMOVDQU16Z256rm
: case X86::VMOVDQU8Z256rm: case X86::VMOVAPSZ256rm: case X86
::VMOVAPDZ256rm: case X86::VMOVUPSZ256rm: case X86::VMOVUPDZ256rm
:
\
2023 MOV_AVX512_CASE(Z128)case X86::VMOVDQA64Z128rm: case X86::VMOVDQA32Z128rm: case X86
::VMOVDQU64Z128rm: case X86::VMOVDQU32Z128rm: case X86::VMOVDQU16Z128rm
: case X86::VMOVDQU8Z128rm: case X86::VMOVAPSZ128rm: case X86
::VMOVAPDZ128rm: case X86::VMOVUPSZ128rm: case X86::VMOVUPDZ128rm
:
2024
2025 // For loads from a constant pool to a vector register, print the constant
2026 // loaded.
2027 CASE_ALL_MOV_RM()case X86::MOVAPDrm: case X86::MOVAPSrm: case X86::MOVUPDrm: case
X86::MOVUPSrm: case X86::MOVDQArm: case X86::MOVDQUrm: case X86
::VMOVAPDrm: case X86::VMOVAPSrm: case X86::VMOVUPDrm: case X86
::VMOVUPSrm: case X86::VMOVDQArm: case X86::VMOVDQUrm: case X86
::VMOVAPDYrm: case X86::VMOVAPSYrm: case X86::VMOVUPDYrm: case
X86::VMOVUPSYrm: case X86::VMOVDQAYrm: case X86::VMOVDQUYrm:
case X86::VMOVDQA64Zrm: case X86::VMOVDQA32Zrm: case X86::VMOVDQU64Zrm
: case X86::VMOVDQU32Zrm: case X86::VMOVDQU16Zrm: case X86::VMOVDQU8Zrm
: case X86::VMOVAPSZrm: case X86::VMOVAPDZrm: case X86::VMOVUPSZrm
: case X86::VMOVUPDZrm: case X86::VMOVDQA64Z256rm: case X86::
VMOVDQA32Z256rm: case X86::VMOVDQU64Z256rm: case X86::VMOVDQU32Z256rm
: case X86::VMOVDQU16Z256rm: case X86::VMOVDQU8Z256rm: case X86
::VMOVAPSZ256rm: case X86::VMOVAPDZ256rm: case X86::VMOVUPSZ256rm
: case X86::VMOVUPDZ256rm: case X86::VMOVDQA64Z128rm: case X86
::VMOVDQA32Z128rm: case X86::VMOVDQU64Z128rm: case X86::VMOVDQU32Z128rm
: case X86::VMOVDQU16Z128rm: case X86::VMOVDQU8Z128rm: case X86
::VMOVAPSZ128rm: case X86::VMOVAPDZ128rm: case X86::VMOVUPSZ128rm
: case X86::VMOVUPDZ128rm:
2028 case X86::VBROADCASTF128:
2029 case X86::VBROADCASTI128:
2030 case X86::VBROADCASTF32X4Z256rm:
2031 case X86::VBROADCASTF32X4rm:
2032 case X86::VBROADCASTF32X8rm:
2033 case X86::VBROADCASTF64X2Z128rm:
2034 case X86::VBROADCASTF64X2rm:
2035 case X86::VBROADCASTF64X4rm:
2036 case X86::VBROADCASTI32X4Z256rm:
2037 case X86::VBROADCASTI32X4rm:
2038 case X86::VBROADCASTI32X8rm:
2039 case X86::VBROADCASTI64X2Z128rm:
2040 case X86::VBROADCASTI64X2rm:
2041 case X86::VBROADCASTI64X4rm:
2042 if (!OutStreamer->isVerboseAsm())
2043 break;
2044 if (MI->getNumOperands() <= 4)
2045 break;
2046 if (auto *C = getConstantFromPool(*MI, MI->getOperand(4))) {
2047 int NumLanes = 1;
2048 // Override NumLanes for the broadcast instructions.
2049 switch (MI->getOpcode()) {
2050 case X86::VBROADCASTF128: NumLanes = 2; break;
2051 case X86::VBROADCASTI128: NumLanes = 2; break;
2052 case X86::VBROADCASTF32X4Z256rm: NumLanes = 2; break;
2053 case X86::VBROADCASTF32X4rm: NumLanes = 4; break;
2054 case X86::VBROADCASTF32X8rm: NumLanes = 2; break;
2055 case X86::VBROADCASTF64X2Z128rm: NumLanes = 2; break;
2056 case X86::VBROADCASTF64X2rm: NumLanes = 4; break;
2057 case X86::VBROADCASTF64X4rm: NumLanes = 2; break;
2058 case X86::VBROADCASTI32X4Z256rm: NumLanes = 2; break;
2059 case X86::VBROADCASTI32X4rm: NumLanes = 4; break;
2060 case X86::VBROADCASTI32X8rm: NumLanes = 2; break;
2061 case X86::VBROADCASTI64X2Z128rm: NumLanes = 2; break;
2062 case X86::VBROADCASTI64X2rm: NumLanes = 4; break;
2063 case X86::VBROADCASTI64X4rm: NumLanes = 2; break;
2064 }
2065
2066 std::string Comment;
2067 raw_string_ostream CS(Comment);
2068 const MachineOperand &DstOp = MI->getOperand(0);
2069 CS << X86ATTInstPrinter::getRegisterName(DstOp.getReg()) << " = ";
2070 if (auto *CDS = dyn_cast<ConstantDataSequential>(C)) {
2071 CS << "[";
2072 for (int l = 0; l != NumLanes; ++l) {
2073 for (int i = 0, NumElements = CDS->getNumElements(); i < NumElements;
2074 ++i) {
2075 if (i != 0 || l != 0)
2076 CS << ",";
2077 if (CDS->getElementType()->isIntegerTy())
2078 printConstant(CDS->getElementAsAPInt(i), CS);
2079 else if (CDS->getElementType()->isHalfTy() ||
2080 CDS->getElementType()->isFloatTy() ||
2081 CDS->getElementType()->isDoubleTy())
2082 printConstant(CDS->getElementAsAPFloat(i), CS);
2083 else
2084 CS << "?";
2085 }
2086 }
2087 CS << "]";
2088 OutStreamer->AddComment(CS.str());
2089 } else if (auto *CV = dyn_cast<ConstantVector>(C)) {
2090 CS << "<";
2091 for (int l = 0; l != NumLanes; ++l) {
2092 for (int i = 0, NumOperands = CV->getNumOperands(); i < NumOperands;
2093 ++i) {
2094 if (i != 0 || l != 0)
2095 CS << ",";
2096 printConstant(CV->getOperand(i), CS);
2097 }
2098 }
2099 CS << ">";
2100 OutStreamer->AddComment(CS.str());
2101 }
2102 }
2103 break;
2104 case X86::MOVDDUPrm:
2105 case X86::VMOVDDUPrm:
2106 case X86::VMOVDDUPZ128rm:
2107 case X86::VBROADCASTSSrm:
2108 case X86::VBROADCASTSSYrm:
2109 case X86::VBROADCASTSSZ128m:
2110 case X86::VBROADCASTSSZ256m:
2111 case X86::VBROADCASTSSZm:
2112 case X86::VBROADCASTSDYrm:
2113 case X86::VBROADCASTSDZ256m:
2114 case X86::VBROADCASTSDZm:
2115 case X86::VPBROADCASTBrm:
2116 case X86::VPBROADCASTBYrm:
2117 case X86::VPBROADCASTBZ128m:
2118 case X86::VPBROADCASTBZ256m:
2119 case X86::VPBROADCASTBZm:
2120 case X86::VPBROADCASTDrm:
2121 case X86::VPBROADCASTDYrm:
2122 case X86::VPBROADCASTDZ128m:
2123 case X86::VPBROADCASTDZ256m:
2124 case X86::VPBROADCASTDZm:
2125 case X86::VPBROADCASTQrm:
2126 case X86::VPBROADCASTQYrm:
2127 case X86::VPBROADCASTQZ128m:
2128 case X86::VPBROADCASTQZ256m:
2129 case X86::VPBROADCASTQZm:
2130 case X86::VPBROADCASTWrm:
2131 case X86::VPBROADCASTWYrm:
2132 case X86::VPBROADCASTWZ128m:
2133 case X86::VPBROADCASTWZ256m:
2134 case X86::VPBROADCASTWZm:
2135 if (!OutStreamer->isVerboseAsm())
2136 break;
2137 if (MI->getNumOperands() <= 4)
2138 break;
2139 if (auto *C = getConstantFromPool(*MI, MI->getOperand(4))) {
2140 int NumElts;
2141 switch (MI->getOpcode()) {
2142 default: llvm_unreachable("Invalid opcode")::llvm::llvm_unreachable_internal("Invalid opcode", "/build/llvm-toolchain-snapshot-9~svn358520/lib/Target/X86/X86MCInstLower.cpp"
, 2142)
;
2143 case X86::MOVDDUPrm: NumElts = 2; break;
2144 case X86::VMOVDDUPrm: NumElts = 2; break;
2145 case X86::VMOVDDUPZ128rm: NumElts = 2; break;
2146 case X86::VBROADCASTSSrm: NumElts = 4; break;
2147 case X86::VBROADCASTSSYrm: NumElts = 8; break;
2148 case X86::VBROADCASTSSZ128m: NumElts = 4; break;
2149 case X86::VBROADCASTSSZ256m: NumElts = 8; break;
2150 case X86::VBROADCASTSSZm: NumElts = 16; break;
2151 case X86::VBROADCASTSDYrm: NumElts = 4; break;
2152 case X86::VBROADCASTSDZ256m: NumElts = 4; break;
2153 case X86::VBROADCASTSDZm: NumElts = 8; break;
2154 case X86::VPBROADCASTBrm: NumElts = 16; break;
2155 case X86::VPBROADCASTBYrm: NumElts = 32; break;
2156 case X86::VPBROADCASTBZ128m: NumElts = 16; break;
2157 case X86::VPBROADCASTBZ256m: NumElts = 32; break;
2158 case X86::VPBROADCASTBZm: NumElts = 64; break;
2159 case X86::VPBROADCASTDrm: NumElts = 4; break;
2160 case X86::VPBROADCASTDYrm: NumElts = 8; break;
2161 case X86::VPBROADCASTDZ128m: NumElts = 4; break;
2162 case X86::VPBROADCASTDZ256m: NumElts = 8; break;
2163 case X86::VPBROADCASTDZm: NumElts = 16; break;
2164 case X86::VPBROADCASTQrm: NumElts = 2; break;
2165 case X86::VPBROADCASTQYrm: NumElts = 4; break;
2166 case X86::VPBROADCASTQZ128m: NumElts = 2; break;
2167 case X86::VPBROADCASTQZ256m: NumElts = 4; break;
2168 case X86::VPBROADCASTQZm: NumElts = 8; break;
2169 case X86::VPBROADCASTWrm: NumElts = 8; break;
2170 case X86::VPBROADCASTWYrm: NumElts = 16; break;
2171 case X86::VPBROADCASTWZ128m: NumElts = 8; break;
2172 case X86::VPBROADCASTWZ256m: NumElts = 16; break;
2173 case X86::VPBROADCASTWZm: NumElts = 32; break;
2174 }
2175
2176 std::string Comment;
2177 raw_string_ostream CS(Comment);
2178 const MachineOperand &DstOp = MI->getOperand(0);
2179 CS << X86ATTInstPrinter::getRegisterName(DstOp.getReg()) << " = ";
2180 CS << "[";
2181 for (int i = 0; i != NumElts; ++i) {
2182 if (i != 0)
2183 CS << ",";
2184 printConstant(C, CS);
2185 }
2186 CS << "]";
2187 OutStreamer->AddComment(CS.str());
2188 }
2189 }
2190
2191 MCInst TmpInst;
2192 MCInstLowering.Lower(MI, TmpInst);
2193
2194 // Stackmap shadows cannot include branch targets, so we can count the bytes
2195 // in a call towards the shadow, but must ensure that the no thread returns
2196 // in to the stackmap shadow. The only way to achieve this is if the call
2197 // is at the end of the shadow.
2198 if (MI->isCall()) {
2199 // Count then size of the call towards the shadow
2200 SMShadowTracker.count(TmpInst, getSubtargetInfo(), CodeEmitter.get());
2201 // Then flush the shadow so that we fill with nops before the call, not
2202 // after it.
2203 SMShadowTracker.emitShadowPadding(*OutStreamer, getSubtargetInfo());
2204 // Then emit the call
2205 OutStreamer->EmitInstruction(TmpInst, getSubtargetInfo());
2206 return;
2207 }
2208
2209 EmitAndCountInstruction(TmpInst);
2210}