Bug Summary

File:build/source/llvm/lib/Target/X86/X86TargetTransformInfo.cpp
Warning:line 4373, column 15
Division by zero

Annotated Source Code

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clang -cc1 -cc1 -triple x86_64-pc-linux-gnu -analyze -disable-free -clear-ast-before-backend -disable-llvm-verifier -discard-value-names -main-file-name X86TargetTransformInfo.cpp -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=cplusplus -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -analyzer-config-compatibility-mode=true -mrelocation-model pic -pic-level 2 -mframe-pointer=none -fmath-errno -ffp-contract=on -fno-rounding-math -mconstructor-aliases -funwind-tables=2 -target-cpu x86-64 -tune-cpu generic -debugger-tuning=gdb -ffunction-sections -fdata-sections -fcoverage-compilation-dir=/build/source/build-llvm/tools/clang/stage2-bins -resource-dir /usr/lib/llvm-17/lib/clang/17 -D _DEBUG -D _GLIBCXX_ASSERTIONS -D _GNU_SOURCE -D _LIBCPP_ENABLE_ASSERTIONS -D __STDC_CONSTANT_MACROS -D __STDC_FORMAT_MACROS -D __STDC_LIMIT_MACROS -I lib/Target/X86 -I /build/source/llvm/lib/Target/X86 -I include -I /build/source/llvm/include -D _FORTIFY_SOURCE=2 -D NDEBUG -U NDEBUG -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/10/../../../../include/c++/10 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/10/../../../../include/x86_64-linux-gnu/c++/10 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/10/../../../../include/c++/10/backward -internal-isystem /usr/lib/llvm-17/lib/clang/17/include -internal-isystem /usr/local/include -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/10/../../../../x86_64-linux-gnu/include -internal-externc-isystem /usr/include/x86_64-linux-gnu -internal-externc-isystem /include -internal-externc-isystem /usr/include -fmacro-prefix-map=/build/source/build-llvm/tools/clang/stage2-bins=build-llvm/tools/clang/stage2-bins -fmacro-prefix-map=/build/source/= -fcoverage-prefix-map=/build/source/build-llvm/tools/clang/stage2-bins=build-llvm/tools/clang/stage2-bins -fcoverage-prefix-map=/build/source/= -source-date-epoch 1683717183 -O2 -Wno-unused-command-line-argument -Wno-unused-parameter -Wwrite-strings -Wno-missing-field-initializers -Wno-long-long -Wno-maybe-uninitialized -Wno-class-memaccess -Wno-redundant-move -Wno-pessimizing-move -Wno-noexcept-type -Wno-comment -Wno-misleading-indentation -std=c++17 -fdeprecated-macro -fdebug-compilation-dir=/build/source/build-llvm/tools/clang/stage2-bins -fdebug-prefix-map=/build/source/build-llvm/tools/clang/stage2-bins=build-llvm/tools/clang/stage2-bins -fdebug-prefix-map=/build/source/= -ferror-limit 19 -fvisibility=hidden -fvisibility-inlines-hidden -stack-protector 2 -fgnuc-version=4.2.1 -fcolor-diagnostics -vectorize-loops -vectorize-slp -analyzer-output=html -analyzer-config stable-report-filename=true -faddrsig -D__GCC_HAVE_DWARF2_CFI_ASM=1 -o /tmp/scan-build-2023-05-10-133810-16478-1 -x c++ /build/source/llvm/lib/Target/X86/X86TargetTransformInfo.cpp
1//===-- X86TargetTransformInfo.cpp - X86 specific TTI pass ----------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8/// \file
9/// This file implements a TargetTransformInfo analysis pass specific to the
10/// X86 target machine. It uses the target's detailed information to provide
11/// more precise answers to certain TTI queries, while letting the target
12/// independent and default TTI implementations handle the rest.
13///
14//===----------------------------------------------------------------------===//
15/// About Cost Model numbers used below it's necessary to say the following:
16/// the numbers correspond to some "generic" X86 CPU instead of usage of a
17/// specific CPU model. Usually the numbers correspond to the CPU where the
18/// feature first appeared. For example, if we do Subtarget.hasSSE42() in
19/// the lookups below the cost is based on Nehalem as that was the first CPU
20/// to support that feature level and thus has most likely the worst case cost,
21/// although we may discard an outlying worst cost from one CPU (e.g. Atom).
22///
23/// Some examples of other technologies/CPUs:
24/// SSE 3 - Pentium4 / Athlon64
25/// SSE 4.1 - Penryn
26/// SSE 4.2 - Nehalem / Silvermont
27/// AVX - Sandy Bridge / Jaguar / Bulldozer
28/// AVX2 - Haswell / Ryzen
29/// AVX-512 - Xeon Phi / Skylake
30///
31/// And some examples of instruction target dependent costs (latency)
32/// divss sqrtss rsqrtss
33/// AMD K7 11-16 19 3
34/// Piledriver 9-24 13-15 5
35/// Jaguar 14 16 2
36/// Pentium II,III 18 30 2
37/// Nehalem 7-14 7-18 3
38/// Haswell 10-13 11 5
39///
40/// Interpreting the 4 TargetCostKind types:
41/// TCK_RecipThroughput and TCK_Latency should try to match the worst case
42/// values reported by the CPU scheduler models (and llvm-mca).
43/// TCK_CodeSize should match the instruction count (e.g. divss = 1), NOT the
44/// actual encoding size of the instruction.
45/// TCK_SizeAndLatency should match the worst case micro-op counts reported by
46/// by the CPU scheduler models (and llvm-mca), to ensure that they are
47/// compatible with the MicroOpBufferSize and LoopMicroOpBufferSize values which are
48/// often used as the cost thresholds where TCK_SizeAndLatency is requested.
49//===----------------------------------------------------------------------===//
50
51#include "X86TargetTransformInfo.h"
52#include "llvm/Analysis/TargetTransformInfo.h"
53#include "llvm/CodeGen/BasicTTIImpl.h"
54#include "llvm/CodeGen/CostTable.h"
55#include "llvm/CodeGen/TargetLowering.h"
56#include "llvm/IR/InstIterator.h"
57#include "llvm/IR/IntrinsicInst.h"
58#include "llvm/Support/Debug.h"
59#include <optional>
60
61using namespace llvm;
62
63#define DEBUG_TYPE"x86tti" "x86tti"
64
65//===----------------------------------------------------------------------===//
66//
67// X86 cost model.
68//
69//===----------------------------------------------------------------------===//
70
71// Helper struct to store/access costs for each cost kind.
72// TODO: Move this to allow other targets to use it?
73struct CostKindCosts {
74 unsigned RecipThroughputCost = ~0U;
75 unsigned LatencyCost = ~0U;
76 unsigned CodeSizeCost = ~0U;
77 unsigned SizeAndLatencyCost = ~0U;
78
79 std::optional<unsigned>
80 operator[](TargetTransformInfo::TargetCostKind Kind) const {
81 unsigned Cost = ~0U;
82 switch (Kind) {
83 case TargetTransformInfo::TCK_RecipThroughput:
84 Cost = RecipThroughputCost;
85 break;
86 case TargetTransformInfo::TCK_Latency:
87 Cost = LatencyCost;
88 break;
89 case TargetTransformInfo::TCK_CodeSize:
90 Cost = CodeSizeCost;
91 break;
92 case TargetTransformInfo::TCK_SizeAndLatency:
93 Cost = SizeAndLatencyCost;
94 break;
95 }
96 if (Cost == ~0U)
97 return std::nullopt;
98 return Cost;
99 }
100};
101using CostKindTblEntry = CostTblEntryT<CostKindCosts>;
102
103TargetTransformInfo::PopcntSupportKind
104X86TTIImpl::getPopcntSupport(unsigned TyWidth) {
105 assert(isPowerOf2_32(TyWidth) && "Ty width must be power of 2")(static_cast <bool> (isPowerOf2_32(TyWidth) && "Ty width must be power of 2"
) ? void (0) : __assert_fail ("isPowerOf2_32(TyWidth) && \"Ty width must be power of 2\""
, "llvm/lib/Target/X86/X86TargetTransformInfo.cpp", 105, __extension__
__PRETTY_FUNCTION__));
106 // TODO: Currently the __builtin_popcount() implementation using SSE3
107 // instructions is inefficient. Once the problem is fixed, we should
108 // call ST->hasSSE3() instead of ST->hasPOPCNT().
109 return ST->hasPOPCNT() ? TTI::PSK_FastHardware : TTI::PSK_Software;
110}
111
112std::optional<unsigned> X86TTIImpl::getCacheSize(
113 TargetTransformInfo::CacheLevel Level) const {
114 switch (Level) {
115 case TargetTransformInfo::CacheLevel::L1D:
116 // - Penryn
117 // - Nehalem
118 // - Westmere
119 // - Sandy Bridge
120 // - Ivy Bridge
121 // - Haswell
122 // - Broadwell
123 // - Skylake
124 // - Kabylake
125 return 32 * 1024; // 32 KByte
126 case TargetTransformInfo::CacheLevel::L2D:
127 // - Penryn
128 // - Nehalem
129 // - Westmere
130 // - Sandy Bridge
131 // - Ivy Bridge
132 // - Haswell
133 // - Broadwell
134 // - Skylake
135 // - Kabylake
136 return 256 * 1024; // 256 KByte
137 }
138
139 llvm_unreachable("Unknown TargetTransformInfo::CacheLevel")::llvm::llvm_unreachable_internal("Unknown TargetTransformInfo::CacheLevel"
, "llvm/lib/Target/X86/X86TargetTransformInfo.cpp", 139);
140}
141
142std::optional<unsigned> X86TTIImpl::getCacheAssociativity(
143 TargetTransformInfo::CacheLevel Level) const {
144 // - Penryn
145 // - Nehalem
146 // - Westmere
147 // - Sandy Bridge
148 // - Ivy Bridge
149 // - Haswell
150 // - Broadwell
151 // - Skylake
152 // - Kabylake
153 switch (Level) {
154 case TargetTransformInfo::CacheLevel::L1D:
155 [[fallthrough]];
156 case TargetTransformInfo::CacheLevel::L2D:
157 return 8;
158 }
159
160 llvm_unreachable("Unknown TargetTransformInfo::CacheLevel")::llvm::llvm_unreachable_internal("Unknown TargetTransformInfo::CacheLevel"
, "llvm/lib/Target/X86/X86TargetTransformInfo.cpp", 160);
161}
162
163unsigned X86TTIImpl::getNumberOfRegisters(unsigned ClassID) const {
164 bool Vector = (ClassID == 1);
165 if (Vector && !ST->hasSSE1())
166 return 0;
167
168 if (ST->is64Bit()) {
169 if (Vector && ST->hasAVX512())
170 return 32;
171 return 16;
172 }
173 return 8;
174}
175
176TypeSize
177X86TTIImpl::getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const {
178 unsigned PreferVectorWidth = ST->getPreferVectorWidth();
179 switch (K) {
180 case TargetTransformInfo::RGK_Scalar:
181 return TypeSize::getFixed(ST->is64Bit() ? 64 : 32);
182 case TargetTransformInfo::RGK_FixedWidthVector:
183 if (ST->hasAVX512() && PreferVectorWidth >= 512)
184 return TypeSize::getFixed(512);
185 if (ST->hasAVX() && PreferVectorWidth >= 256)
186 return TypeSize::getFixed(256);
187 if (ST->hasSSE1() && PreferVectorWidth >= 128)
188 return TypeSize::getFixed(128);
189 return TypeSize::getFixed(0);
190 case TargetTransformInfo::RGK_ScalableVector:
191 return TypeSize::getScalable(0);
192 }
193
194 llvm_unreachable("Unsupported register kind")::llvm::llvm_unreachable_internal("Unsupported register kind"
, "llvm/lib/Target/X86/X86TargetTransformInfo.cpp", 194);
195}
196
197unsigned X86TTIImpl::getLoadStoreVecRegBitWidth(unsigned) const {
198 return getRegisterBitWidth(TargetTransformInfo::RGK_FixedWidthVector)
199 .getFixedValue();
200}
201
202unsigned X86TTIImpl::getMaxInterleaveFactor(ElementCount VF) {
203 // If the loop will not be vectorized, don't interleave the loop.
204 // Let regular unroll to unroll the loop, which saves the overflow
205 // check and memory check cost.
206 if (VF.isScalar())
207 return 1;
208
209 if (ST->isAtom())
210 return 1;
211
212 // Sandybridge and Haswell have multiple execution ports and pipelined
213 // vector units.
214 if (ST->hasAVX())
215 return 4;
216
217 return 2;
218}
219
220InstructionCost X86TTIImpl::getArithmeticInstrCost(
221 unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind,
222 TTI::OperandValueInfo Op1Info, TTI::OperandValueInfo Op2Info,
223 ArrayRef<const Value *> Args,
224 const Instruction *CxtI) {
225
226 // vXi8 multiplications are always promoted to vXi16.
227 // Sub-128-bit types can be extended/packed more efficiently.
228 if (Opcode == Instruction::Mul && Ty->isVectorTy() &&
229 Ty->getPrimitiveSizeInBits() <= 64 && Ty->getScalarSizeInBits() == 8) {
230 Type *WideVecTy =
231 VectorType::getExtendedElementVectorType(cast<VectorType>(Ty));
232 return getCastInstrCost(Instruction::ZExt, WideVecTy, Ty,
233 TargetTransformInfo::CastContextHint::None,
234 CostKind) +
235 getCastInstrCost(Instruction::Trunc, Ty, WideVecTy,
236 TargetTransformInfo::CastContextHint::None,
237 CostKind) +
238 getArithmeticInstrCost(Opcode, WideVecTy, CostKind, Op1Info, Op2Info);
239 }
240
241 // Legalize the type.
242 std::pair<InstructionCost, MVT> LT = getTypeLegalizationCost(Ty);
243
244 int ISD = TLI->InstructionOpcodeToISD(Opcode);
245 assert(ISD && "Invalid opcode")(static_cast <bool> (ISD && "Invalid opcode") ?
void (0) : __assert_fail ("ISD && \"Invalid opcode\""
, "llvm/lib/Target/X86/X86TargetTransformInfo.cpp", 245, __extension__
__PRETTY_FUNCTION__));
246
247 if (ISD == ISD::MUL && Args.size() == 2 && LT.second.isVector() &&
248 LT.second.getScalarType() == MVT::i32) {
249 // Check if the operands can be represented as a smaller datatype.
250 bool Op1Signed = false, Op2Signed = false;
251 unsigned Op1MinSize = BaseT::minRequiredElementSize(Args[0], Op1Signed);
252 unsigned Op2MinSize = BaseT::minRequiredElementSize(Args[1], Op2Signed);
253 unsigned OpMinSize = std::max(Op1MinSize, Op2MinSize);
254 bool SignedMode = Op1Signed || Op2Signed;
255
256 // If both are representable as i15 and at least one is constant,
257 // zero-extended, or sign-extended from vXi16 (or less pre-SSE41) then we
258 // can treat this as PMADDWD which has the same costs as a vXi16 multiply.
259 if (OpMinSize <= 15 && !ST->isPMADDWDSlow()) {
260 bool Op1Constant =
261 isa<ConstantDataVector>(Args[0]) || isa<ConstantVector>(Args[0]);
262 bool Op2Constant =
263 isa<ConstantDataVector>(Args[1]) || isa<ConstantVector>(Args[1]);
264 bool Op1Sext = isa<SExtInst>(Args[0]) &&
265 (Op1MinSize == 15 || (Op1MinSize < 15 && !ST->hasSSE41()));
266 bool Op2Sext = isa<SExtInst>(Args[1]) &&
267 (Op2MinSize == 15 || (Op2MinSize < 15 && !ST->hasSSE41()));
268
269 bool IsZeroExtended = !Op1Signed || !Op2Signed;
270 bool IsConstant = Op1Constant || Op2Constant;
271 bool IsSext = Op1Sext || Op2Sext;
272 if (IsConstant || IsZeroExtended || IsSext)
273 LT.second =
274 MVT::getVectorVT(MVT::i16, 2 * LT.second.getVectorNumElements());
275 }
276
277 // Check if the vXi32 operands can be shrunk into a smaller datatype.
278 // This should match the codegen from reduceVMULWidth.
279 // TODO: Make this generic (!ST->SSE41 || ST->isPMULLDSlow()).
280 if (ST->useSLMArithCosts() && LT.second == MVT::v4i32) {
281 if (OpMinSize <= 7)
282 return LT.first * 3; // pmullw/sext
283 if (!SignedMode && OpMinSize <= 8)
284 return LT.first * 3; // pmullw/zext
285 if (OpMinSize <= 15)
286 return LT.first * 5; // pmullw/pmulhw/pshuf
287 if (!SignedMode && OpMinSize <= 16)
288 return LT.first * 5; // pmullw/pmulhw/pshuf
289 }
290 }
291
292 // Vector multiply by pow2 will be simplified to shifts.
293 // Vector multiply by -pow2 will be simplified to shifts/negates.
294 if (ISD == ISD::MUL && Op2Info.isConstant() &&
295 (Op2Info.isPowerOf2() || Op2Info.isNegatedPowerOf2())) {
296 InstructionCost Cost =
297 getArithmeticInstrCost(Instruction::Shl, Ty, CostKind,
298 Op1Info.getNoProps(), Op2Info.getNoProps());
299 if (Op2Info.isNegatedPowerOf2())
300 Cost += getArithmeticInstrCost(Instruction::Sub, Ty, CostKind);
301 return Cost;
302 }
303
304 // On X86, vector signed division by constants power-of-two are
305 // normally expanded to the sequence SRA + SRL + ADD + SRA.
306 // The OperandValue properties may not be the same as that of the previous
307 // operation; conservatively assume OP_None.
308 if ((ISD == ISD::SDIV || ISD == ISD::SREM) &&
309 Op2Info.isConstant() && Op2Info.isPowerOf2()) {
310 InstructionCost Cost =
311 2 * getArithmeticInstrCost(Instruction::AShr, Ty, CostKind,
312 Op1Info.getNoProps(), Op2Info.getNoProps());
313 Cost += getArithmeticInstrCost(Instruction::LShr, Ty, CostKind,
314 Op1Info.getNoProps(), Op2Info.getNoProps());
315 Cost += getArithmeticInstrCost(Instruction::Add, Ty, CostKind,
316 Op1Info.getNoProps(), Op2Info.getNoProps());
317
318 if (ISD == ISD::SREM) {
319 // For SREM: (X % C) is the equivalent of (X - (X/C)*C)
320 Cost += getArithmeticInstrCost(Instruction::Mul, Ty, CostKind, Op1Info.getNoProps(),
321 Op2Info.getNoProps());
322 Cost += getArithmeticInstrCost(Instruction::Sub, Ty, CostKind, Op1Info.getNoProps(),
323 Op2Info.getNoProps());
324 }
325
326 return Cost;
327 }
328
329 // Vector unsigned division/remainder will be simplified to shifts/masks.
330 if ((ISD == ISD::UDIV || ISD == ISD::UREM) &&
331 Op2Info.isConstant() && Op2Info.isPowerOf2()) {
332 if (ISD == ISD::UDIV)
333 return getArithmeticInstrCost(Instruction::LShr, Ty, CostKind,
334 Op1Info.getNoProps(), Op2Info.getNoProps());
335 // UREM
336 return getArithmeticInstrCost(Instruction::And, Ty, CostKind,
337 Op1Info.getNoProps(), Op2Info.getNoProps());
338 }
339
340 static const CostKindTblEntry AVX512BWUniformConstCostTable[] = {
341 { ISD::SHL, MVT::v16i8, { 1, 7, 2, 3 } }, // psllw + pand.
342 { ISD::SRL, MVT::v16i8, { 1, 7, 2, 3 } }, // psrlw + pand.
343 { ISD::SRA, MVT::v16i8, { 1, 8, 4, 5 } }, // psrlw, pand, pxor, psubb.
344 { ISD::SHL, MVT::v32i8, { 1, 8, 2, 3 } }, // psllw + pand.
345 { ISD::SRL, MVT::v32i8, { 1, 8, 2, 3 } }, // psrlw + pand.
346 { ISD::SRA, MVT::v32i8, { 1, 9, 4, 5 } }, // psrlw, pand, pxor, psubb.
347 { ISD::SHL, MVT::v64i8, { 1, 8, 2, 3 } }, // psllw + pand.
348 { ISD::SRL, MVT::v64i8, { 1, 8, 2, 3 } }, // psrlw + pand.
349 { ISD::SRA, MVT::v64i8, { 1, 9, 4, 6 } }, // psrlw, pand, pxor, psubb.
350
351 { ISD::SHL, MVT::v16i16, { 1, 1, 1, 1 } }, // psllw
352 { ISD::SRL, MVT::v16i16, { 1, 1, 1, 1 } }, // psrlw
353 { ISD::SRA, MVT::v16i16, { 1, 1, 1, 1 } }, // psrlw
354 { ISD::SHL, MVT::v32i16, { 1, 1, 1, 1 } }, // psllw
355 { ISD::SRL, MVT::v32i16, { 1, 1, 1, 1 } }, // psrlw
356 { ISD::SRA, MVT::v32i16, { 1, 1, 1, 1 } }, // psrlw
357 };
358
359 if (Op2Info.isUniform() && Op2Info.isConstant() && ST->hasBWI())
360 if (const auto *Entry =
361 CostTableLookup(AVX512BWUniformConstCostTable, ISD, LT.second))
362 if (auto KindCost = Entry->Cost[CostKind])
363 return LT.first * *KindCost;
364
365 static const CostKindTblEntry AVX512UniformConstCostTable[] = {
366 { ISD::SHL, MVT::v64i8, { 2, 12, 5, 6 } }, // psllw + pand.
367 { ISD::SRL, MVT::v64i8, { 2, 12, 5, 6 } }, // psrlw + pand.
368 { ISD::SRA, MVT::v64i8, { 3, 10, 12, 12 } }, // psrlw, pand, pxor, psubb.
369
370 { ISD::SHL, MVT::v16i16, { 2, 7, 4, 4 } }, // psllw + split.
371 { ISD::SRL, MVT::v16i16, { 2, 7, 4, 4 } }, // psrlw + split.
372 { ISD::SRA, MVT::v16i16, { 2, 7, 4, 4 } }, // psraw + split.
373
374 { ISD::SHL, MVT::v8i32, { 1, 1, 1, 1 } }, // pslld
375 { ISD::SRL, MVT::v8i32, { 1, 1, 1, 1 } }, // psrld
376 { ISD::SRA, MVT::v8i32, { 1, 1, 1, 1 } }, // psrad
377 { ISD::SHL, MVT::v16i32, { 1, 1, 1, 1 } }, // pslld
378 { ISD::SRL, MVT::v16i32, { 1, 1, 1, 1 } }, // psrld
379 { ISD::SRA, MVT::v16i32, { 1, 1, 1, 1 } }, // psrad
380
381 { ISD::SRA, MVT::v2i64, { 1, 1, 1, 1 } }, // psraq
382 { ISD::SHL, MVT::v4i64, { 1, 1, 1, 1 } }, // psllq
383 { ISD::SRL, MVT::v4i64, { 1, 1, 1, 1 } }, // psrlq
384 { ISD::SRA, MVT::v4i64, { 1, 1, 1, 1 } }, // psraq
385 { ISD::SHL, MVT::v8i64, { 1, 1, 1, 1 } }, // psllq
386 { ISD::SRL, MVT::v8i64, { 1, 1, 1, 1 } }, // psrlq
387 { ISD::SRA, MVT::v8i64, { 1, 1, 1, 1 } }, // psraq
388
389 { ISD::SDIV, MVT::v16i32, { 6 } }, // pmuludq sequence
390 { ISD::SREM, MVT::v16i32, { 8 } }, // pmuludq+mul+sub sequence
391 { ISD::UDIV, MVT::v16i32, { 5 } }, // pmuludq sequence
392 { ISD::UREM, MVT::v16i32, { 7 } }, // pmuludq+mul+sub sequence
393 };
394
395 if (Op2Info.isUniform() && Op2Info.isConstant() && ST->hasAVX512())
396 if (const auto *Entry =
397 CostTableLookup(AVX512UniformConstCostTable, ISD, LT.second))
398 if (auto KindCost = Entry->Cost[CostKind])
399 return LT.first * *KindCost;
400
401 static const CostKindTblEntry AVX2UniformConstCostTable[] = {
402 { ISD::SHL, MVT::v16i8, { 1, 8, 2, 3 } }, // psllw + pand.
403 { ISD::SRL, MVT::v16i8, { 1, 8, 2, 3 } }, // psrlw + pand.
404 { ISD::SRA, MVT::v16i8, { 2, 10, 5, 6 } }, // psrlw, pand, pxor, psubb.
405 { ISD::SHL, MVT::v32i8, { 2, 8, 2, 4 } }, // psllw + pand.
406 { ISD::SRL, MVT::v32i8, { 2, 8, 2, 4 } }, // psrlw + pand.
407 { ISD::SRA, MVT::v32i8, { 3, 10, 5, 9 } }, // psrlw, pand, pxor, psubb.
408
409 { ISD::SHL, MVT::v8i16, { 1, 1, 1, 1 } }, // psllw
410 { ISD::SRL, MVT::v8i16, { 1, 1, 1, 1 } }, // psrlw
411 { ISD::SRA, MVT::v8i16, { 1, 1, 1, 1 } }, // psraw
412 { ISD::SHL, MVT::v16i16,{ 2, 2, 1, 2 } }, // psllw
413 { ISD::SRL, MVT::v16i16,{ 2, 2, 1, 2 } }, // psrlw
414 { ISD::SRA, MVT::v16i16,{ 2, 2, 1, 2 } }, // psraw
415
416 { ISD::SHL, MVT::v4i32, { 1, 1, 1, 1 } }, // pslld
417 { ISD::SRL, MVT::v4i32, { 1, 1, 1, 1 } }, // psrld
418 { ISD::SRA, MVT::v4i32, { 1, 1, 1, 1 } }, // psrad
419 { ISD::SHL, MVT::v8i32, { 2, 2, 1, 2 } }, // pslld
420 { ISD::SRL, MVT::v8i32, { 2, 2, 1, 2 } }, // psrld
421 { ISD::SRA, MVT::v8i32, { 2, 2, 1, 2 } }, // psrad
422
423 { ISD::SHL, MVT::v2i64, { 1, 1, 1, 1 } }, // psllq
424 { ISD::SRL, MVT::v2i64, { 1, 1, 1, 1 } }, // psrlq
425 { ISD::SRA, MVT::v2i64, { 2, 3, 3, 3 } }, // psrad + shuffle.
426 { ISD::SHL, MVT::v4i64, { 2, 2, 1, 2 } }, // psllq
427 { ISD::SRL, MVT::v4i64, { 2, 2, 1, 2 } }, // psrlq
428 { ISD::SRA, MVT::v4i64, { 4, 4, 3, 6 } }, // psrad + shuffle + split.
429
430 { ISD::SDIV, MVT::v8i32, { 6 } }, // pmuludq sequence
431 { ISD::SREM, MVT::v8i32, { 8 } }, // pmuludq+mul+sub sequence
432 { ISD::UDIV, MVT::v8i32, { 5 } }, // pmuludq sequence
433 { ISD::UREM, MVT::v8i32, { 7 } }, // pmuludq+mul+sub sequence
434 };
435
436 if (Op2Info.isUniform() && Op2Info.isConstant() && ST->hasAVX2())
437 if (const auto *Entry =
438 CostTableLookup(AVX2UniformConstCostTable, ISD, LT.second))
439 if (auto KindCost = Entry->Cost[CostKind])
440 return LT.first * *KindCost;
441
442 static const CostKindTblEntry AVXUniformConstCostTable[] = {
443 { ISD::SHL, MVT::v16i8, { 2, 7, 2, 3 } }, // psllw + pand.
444 { ISD::SRL, MVT::v16i8, { 2, 7, 2, 3 } }, // psrlw + pand.
445 { ISD::SRA, MVT::v16i8, { 3, 9, 5, 6 } }, // psrlw, pand, pxor, psubb.
446 { ISD::SHL, MVT::v32i8, { 4, 7, 7, 8 } }, // 2*(psllw + pand) + split.
447 { ISD::SRL, MVT::v32i8, { 4, 7, 7, 8 } }, // 2*(psrlw + pand) + split.
448 { ISD::SRA, MVT::v32i8, { 7, 7, 12, 13 } }, // 2*(psrlw, pand, pxor, psubb) + split.
449
450 { ISD::SHL, MVT::v8i16, { 1, 2, 1, 1 } }, // psllw.
451 { ISD::SRL, MVT::v8i16, { 1, 2, 1, 1 } }, // psrlw.
452 { ISD::SRA, MVT::v8i16, { 1, 2, 1, 1 } }, // psraw.
453 { ISD::SHL, MVT::v16i16,{ 3, 6, 4, 5 } }, // psllw + split.
454 { ISD::SRL, MVT::v16i16,{ 3, 6, 4, 5 } }, // psrlw + split.
455 { ISD::SRA, MVT::v16i16,{ 3, 6, 4, 5 } }, // psraw + split.
456
457 { ISD::SHL, MVT::v4i32, { 1, 2, 1, 1 } }, // pslld.
458 { ISD::SRL, MVT::v4i32, { 1, 2, 1, 1 } }, // psrld.
459 { ISD::SRA, MVT::v4i32, { 1, 2, 1, 1 } }, // psrad.
460 { ISD::SHL, MVT::v8i32, { 3, 6, 4, 5 } }, // pslld + split.
461 { ISD::SRL, MVT::v8i32, { 3, 6, 4, 5 } }, // psrld + split.
462 { ISD::SRA, MVT::v8i32, { 3, 6, 4, 5 } }, // psrad + split.
463
464 { ISD::SHL, MVT::v2i64, { 1, 2, 1, 1 } }, // psllq.
465 { ISD::SRL, MVT::v2i64, { 1, 2, 1, 1 } }, // psrlq.
466 { ISD::SRA, MVT::v2i64, { 2, 3, 3, 3 } }, // psrad + shuffle.
467 { ISD::SHL, MVT::v4i64, { 3, 6, 4, 5 } }, // 2 x psllq + split.
468 { ISD::SRL, MVT::v4i64, { 3, 6, 4, 5 } }, // 2 x psllq + split.
469 { ISD::SRA, MVT::v4i64, { 5, 7, 8, 9 } }, // 2 x psrad + shuffle + split.
470
471 { ISD::SDIV, MVT::v8i32, { 14 } }, // 2*pmuludq sequence + split.
472 { ISD::SREM, MVT::v8i32, { 18 } }, // 2*pmuludq+mul+sub sequence + split.
473 { ISD::UDIV, MVT::v8i32, { 12 } }, // 2*pmuludq sequence + split.
474 { ISD::UREM, MVT::v8i32, { 16 } }, // 2*pmuludq+mul+sub sequence + split.
475 };
476
477 // XOP has faster vXi8 shifts.
478 if (Op2Info.isUniform() && Op2Info.isConstant() && ST->hasAVX() &&
479 (!ST->hasXOP() || LT.second.getScalarSizeInBits() != 8))
480 if (const auto *Entry =
481 CostTableLookup(AVXUniformConstCostTable, ISD, LT.second))
482 if (auto KindCost = Entry->Cost[CostKind])
483 return LT.first * *KindCost;
484
485 static const CostKindTblEntry SSE2UniformConstCostTable[] = {
486 { ISD::SHL, MVT::v16i8, { 1, 7, 2, 3 } }, // psllw + pand.
487 { ISD::SRL, MVT::v16i8, { 1, 7, 2, 3 } }, // psrlw + pand.
488 { ISD::SRA, MVT::v16i8, { 3, 9, 5, 6 } }, // psrlw, pand, pxor, psubb.
489
490 { ISD::SHL, MVT::v8i16, { 1, 1, 1, 1 } }, // psllw.
491 { ISD::SRL, MVT::v8i16, { 1, 1, 1, 1 } }, // psrlw.
492 { ISD::SRA, MVT::v8i16, { 1, 1, 1, 1 } }, // psraw.
493
494 { ISD::SHL, MVT::v4i32, { 1, 1, 1, 1 } }, // pslld
495 { ISD::SRL, MVT::v4i32, { 1, 1, 1, 1 } }, // psrld.
496 { ISD::SRA, MVT::v4i32, { 1, 1, 1, 1 } }, // psrad.
497
498 { ISD::SHL, MVT::v2i64, { 1, 1, 1, 1 } }, // psllq.
499 { ISD::SRL, MVT::v2i64, { 1, 1, 1, 1 } }, // psrlq.
500 { ISD::SRA, MVT::v2i64, { 3, 5, 6, 6 } }, // 2 x psrad + shuffle.
501
502 { ISD::SDIV, MVT::v4i32, { 6 } }, // pmuludq sequence
503 { ISD::SREM, MVT::v4i32, { 8 } }, // pmuludq+mul+sub sequence
504 { ISD::UDIV, MVT::v4i32, { 5 } }, // pmuludq sequence
505 { ISD::UREM, MVT::v4i32, { 7 } }, // pmuludq+mul+sub sequence
506 };
507
508 // XOP has faster vXi8 shifts.
509 if (Op2Info.isUniform() && Op2Info.isConstant() && ST->hasSSE2() &&
510 (!ST->hasXOP() || LT.second.getScalarSizeInBits() != 8))
511 if (const auto *Entry =
512 CostTableLookup(SSE2UniformConstCostTable, ISD, LT.second))
513 if (auto KindCost = Entry->Cost[CostKind])
514 return LT.first * *KindCost;
515
516 static const CostKindTblEntry AVX512BWConstCostTable[] = {
517 { ISD::SDIV, MVT::v64i8, { 14 } }, // 2*ext+2*pmulhw sequence
518 { ISD::SREM, MVT::v64i8, { 16 } }, // 2*ext+2*pmulhw+mul+sub sequence
519 { ISD::UDIV, MVT::v64i8, { 14 } }, // 2*ext+2*pmulhw sequence
520 { ISD::UREM, MVT::v64i8, { 16 } }, // 2*ext+2*pmulhw+mul+sub sequence
521
522 { ISD::SDIV, MVT::v32i16, { 6 } }, // vpmulhw sequence
523 { ISD::SREM, MVT::v32i16, { 8 } }, // vpmulhw+mul+sub sequence
524 { ISD::UDIV, MVT::v32i16, { 6 } }, // vpmulhuw sequence
525 { ISD::UREM, MVT::v32i16, { 8 } }, // vpmulhuw+mul+sub sequence
526 };
527
528 if (Op2Info.isConstant() && ST->hasBWI())
529 if (const auto *Entry =
530 CostTableLookup(AVX512BWConstCostTable, ISD, LT.second))
531 if (auto KindCost = Entry->Cost[CostKind])
532 return LT.first * *KindCost;
533
534 static const CostKindTblEntry AVX512ConstCostTable[] = {
535 { ISD::SDIV, MVT::v64i8, { 28 } }, // 4*ext+4*pmulhw sequence
536 { ISD::SREM, MVT::v64i8, { 32 } }, // 4*ext+4*pmulhw+mul+sub sequence
537 { ISD::UDIV, MVT::v64i8, { 28 } }, // 4*ext+4*pmulhw sequence
538 { ISD::UREM, MVT::v64i8, { 32 } }, // 4*ext+4*pmulhw+mul+sub sequence
539
540 { ISD::SDIV, MVT::v32i16, { 12 } }, // 2*vpmulhw sequence
541 { ISD::SREM, MVT::v32i16, { 16 } }, // 2*vpmulhw+mul+sub sequence
542 { ISD::UDIV, MVT::v32i16, { 12 } }, // 2*vpmulhuw sequence
543 { ISD::UREM, MVT::v32i16, { 16 } }, // 2*vpmulhuw+mul+sub sequence
544
545 { ISD::SDIV, MVT::v16i32, { 15 } }, // vpmuldq sequence
546 { ISD::SREM, MVT::v16i32, { 17 } }, // vpmuldq+mul+sub sequence
547 { ISD::UDIV, MVT::v16i32, { 15 } }, // vpmuludq sequence
548 { ISD::UREM, MVT::v16i32, { 17 } }, // vpmuludq+mul+sub sequence
549 };
550
551 if (Op2Info.isConstant() && ST->hasAVX512())
552 if (const auto *Entry =
553 CostTableLookup(AVX512ConstCostTable, ISD, LT.second))
554 if (auto KindCost = Entry->Cost[CostKind])
555 return LT.first * *KindCost;
556
557 static const CostKindTblEntry AVX2ConstCostTable[] = {
558 { ISD::SDIV, MVT::v32i8, { 14 } }, // 2*ext+2*pmulhw sequence
559 { ISD::SREM, MVT::v32i8, { 16 } }, // 2*ext+2*pmulhw+mul+sub sequence
560 { ISD::UDIV, MVT::v32i8, { 14 } }, // 2*ext+2*pmulhw sequence
561 { ISD::UREM, MVT::v32i8, { 16 } }, // 2*ext+2*pmulhw+mul+sub sequence
562
563 { ISD::SDIV, MVT::v16i16, { 6 } }, // vpmulhw sequence
564 { ISD::SREM, MVT::v16i16, { 8 } }, // vpmulhw+mul+sub sequence
565 { ISD::UDIV, MVT::v16i16, { 6 } }, // vpmulhuw sequence
566 { ISD::UREM, MVT::v16i16, { 8 } }, // vpmulhuw+mul+sub sequence
567
568 { ISD::SDIV, MVT::v8i32, { 15 } }, // vpmuldq sequence
569 { ISD::SREM, MVT::v8i32, { 19 } }, // vpmuldq+mul+sub sequence
570 { ISD::UDIV, MVT::v8i32, { 15 } }, // vpmuludq sequence
571 { ISD::UREM, MVT::v8i32, { 19 } }, // vpmuludq+mul+sub sequence
572 };
573
574 if (Op2Info.isConstant() && ST->hasAVX2())
575 if (const auto *Entry = CostTableLookup(AVX2ConstCostTable, ISD, LT.second))
576 if (auto KindCost = Entry->Cost[CostKind])
577 return LT.first * *KindCost;
578
579 static const CostKindTblEntry AVXConstCostTable[] = {
580 { ISD::SDIV, MVT::v32i8, { 30 } }, // 4*ext+4*pmulhw sequence + split.
581 { ISD::SREM, MVT::v32i8, { 34 } }, // 4*ext+4*pmulhw+mul+sub sequence + split.
582 { ISD::UDIV, MVT::v32i8, { 30 } }, // 4*ext+4*pmulhw sequence + split.
583 { ISD::UREM, MVT::v32i8, { 34 } }, // 4*ext+4*pmulhw+mul+sub sequence + split.
584
585 { ISD::SDIV, MVT::v16i16, { 14 } }, // 2*pmulhw sequence + split.
586 { ISD::SREM, MVT::v16i16, { 18 } }, // 2*pmulhw+mul+sub sequence + split.
587 { ISD::UDIV, MVT::v16i16, { 14 } }, // 2*pmulhuw sequence + split.
588 { ISD::UREM, MVT::v16i16, { 18 } }, // 2*pmulhuw+mul+sub sequence + split.
589
590 { ISD::SDIV, MVT::v8i32, { 32 } }, // vpmuludq sequence
591 { ISD::SREM, MVT::v8i32, { 38 } }, // vpmuludq+mul+sub sequence
592 { ISD::UDIV, MVT::v8i32, { 32 } }, // 2*pmuludq sequence + split.
593 { ISD::UREM, MVT::v8i32, { 42 } }, // 2*pmuludq+mul+sub sequence + split.
594 };
595
596 if (Op2Info.isConstant() && ST->hasAVX())
597 if (const auto *Entry = CostTableLookup(AVXConstCostTable, ISD, LT.second))
598 if (auto KindCost = Entry->Cost[CostKind])
599 return LT.first * *KindCost;
600
601 static const CostKindTblEntry SSE41ConstCostTable[] = {
602 { ISD::SDIV, MVT::v4i32, { 15 } }, // vpmuludq sequence
603 { ISD::SREM, MVT::v4i32, { 20 } }, // vpmuludq+mul+sub sequence
604 };
605
606 if (Op2Info.isConstant() && ST->hasSSE41())
607 if (const auto *Entry =
608 CostTableLookup(SSE41ConstCostTable, ISD, LT.second))
609 if (auto KindCost = Entry->Cost[CostKind])
610 return LT.first * *KindCost;
611
612 static const CostKindTblEntry SSE2ConstCostTable[] = {
613 { ISD::SDIV, MVT::v16i8, { 14 } }, // 2*ext+2*pmulhw sequence
614 { ISD::SREM, MVT::v16i8, { 16 } }, // 2*ext+2*pmulhw+mul+sub sequence
615 { ISD::UDIV, MVT::v16i8, { 14 } }, // 2*ext+2*pmulhw sequence
616 { ISD::UREM, MVT::v16i8, { 16 } }, // 2*ext+2*pmulhw+mul+sub sequence
617
618 { ISD::SDIV, MVT::v8i16, { 6 } }, // pmulhw sequence
619 { ISD::SREM, MVT::v8i16, { 8 } }, // pmulhw+mul+sub sequence
620 { ISD::UDIV, MVT::v8i16, { 6 } }, // pmulhuw sequence
621 { ISD::UREM, MVT::v8i16, { 8 } }, // pmulhuw+mul+sub sequence
622
623 { ISD::SDIV, MVT::v4i32, { 19 } }, // pmuludq sequence
624 { ISD::SREM, MVT::v4i32, { 24 } }, // pmuludq+mul+sub sequence
625 { ISD::UDIV, MVT::v4i32, { 15 } }, // pmuludq sequence
626 { ISD::UREM, MVT::v4i32, { 20 } }, // pmuludq+mul+sub sequence
627 };
628
629 if (Op2Info.isConstant() && ST->hasSSE2())
630 if (const auto *Entry = CostTableLookup(SSE2ConstCostTable, ISD, LT.second))
631 if (auto KindCost = Entry->Cost[CostKind])
632 return LT.first * *KindCost;
633
634 static const CostKindTblEntry AVX512BWUniformCostTable[] = {
635 { ISD::SHL, MVT::v16i8, { 3, 5, 5, 7 } }, // psllw + pand.
636 { ISD::SRL, MVT::v16i8, { 3,10, 5, 8 } }, // psrlw + pand.
637 { ISD::SRA, MVT::v16i8, { 4,12, 8,12 } }, // psrlw, pand, pxor, psubb.
638 { ISD::SHL, MVT::v32i8, { 4, 7, 6, 8 } }, // psllw + pand.
639 { ISD::SRL, MVT::v32i8, { 4, 8, 7, 9 } }, // psrlw + pand.
640 { ISD::SRA, MVT::v32i8, { 5,10,10,13 } }, // psrlw, pand, pxor, psubb.
641 { ISD::SHL, MVT::v64i8, { 4, 7, 6, 8 } }, // psllw + pand.
642 { ISD::SRL, MVT::v64i8, { 4, 8, 7,10 } }, // psrlw + pand.
643 { ISD::SRA, MVT::v64i8, { 5,10,10,15 } }, // psrlw, pand, pxor, psubb.
644
645 { ISD::SHL, MVT::v32i16, { 2, 4, 2, 3 } }, // psllw
646 { ISD::SRL, MVT::v32i16, { 2, 4, 2, 3 } }, // psrlw
647 { ISD::SRA, MVT::v32i16, { 2, 4, 2, 3 } }, // psrqw
648 };
649
650 if (ST->hasBWI() && Op2Info.isUniform())
651 if (const auto *Entry =
652 CostTableLookup(AVX512BWUniformCostTable, ISD, LT.second))
653 if (auto KindCost = Entry->Cost[CostKind])
654 return LT.first * *KindCost;
655
656 static const CostKindTblEntry AVX512UniformCostTable[] = {
657 { ISD::SHL, MVT::v32i16, { 5,10, 5, 7 } }, // psllw + split.
658 { ISD::SRL, MVT::v32i16, { 5,10, 5, 7 } }, // psrlw + split.
659 { ISD::SRA, MVT::v32i16, { 5,10, 5, 7 } }, // psraw + split.
660
661 { ISD::SHL, MVT::v16i32, { 2, 4, 2, 3 } }, // pslld
662 { ISD::SRL, MVT::v16i32, { 2, 4, 2, 3 } }, // psrld
663 { ISD::SRA, MVT::v16i32, { 2, 4, 2, 3 } }, // psrad
664
665 { ISD::SRA, MVT::v2i64, { 1, 2, 1, 2 } }, // psraq
666 { ISD::SHL, MVT::v4i64, { 1, 4, 1, 2 } }, // psllq
667 { ISD::SRL, MVT::v4i64, { 1, 4, 1, 2 } }, // psrlq
668 { ISD::SRA, MVT::v4i64, { 1, 4, 1, 2 } }, // psraq
669 { ISD::SHL, MVT::v8i64, { 1, 4, 1, 2 } }, // psllq
670 { ISD::SRL, MVT::v8i64, { 1, 4, 1, 2 } }, // psrlq
671 { ISD::SRA, MVT::v8i64, { 1, 4, 1, 2 } }, // psraq
672 };
673
674 if (ST->hasAVX512() && Op2Info.isUniform())
675 if (const auto *Entry =
676 CostTableLookup(AVX512UniformCostTable, ISD, LT.second))
677 if (auto KindCost = Entry->Cost[CostKind])
678 return LT.first * *KindCost;
679
680 static const CostKindTblEntry AVX2UniformCostTable[] = {
681 // Uniform splats are cheaper for the following instructions.
682 { ISD::SHL, MVT::v16i8, { 3, 5, 5, 7 } }, // psllw + pand.
683 { ISD::SRL, MVT::v16i8, { 3, 9, 5, 8 } }, // psrlw + pand.
684 { ISD::SRA, MVT::v16i8, { 4, 5, 9,13 } }, // psrlw, pand, pxor, psubb.
685 { ISD::SHL, MVT::v32i8, { 4, 7, 6, 8 } }, // psllw + pand.
686 { ISD::SRL, MVT::v32i8, { 4, 8, 7, 9 } }, // psrlw + pand.
687 { ISD::SRA, MVT::v32i8, { 6, 9,11,16 } }, // psrlw, pand, pxor, psubb.
688
689 { ISD::SHL, MVT::v8i16, { 1, 2, 1, 2 } }, // psllw.
690 { ISD::SRL, MVT::v8i16, { 1, 2, 1, 2 } }, // psrlw.
691 { ISD::SRA, MVT::v8i16, { 1, 2, 1, 2 } }, // psraw.
692 { ISD::SHL, MVT::v16i16, { 2, 4, 2, 3 } }, // psllw.
693 { ISD::SRL, MVT::v16i16, { 2, 4, 2, 3 } }, // psrlw.
694 { ISD::SRA, MVT::v16i16, { 2, 4, 2, 3 } }, // psraw.
695
696 { ISD::SHL, MVT::v4i32, { 1, 2, 1, 2 } }, // pslld
697 { ISD::SRL, MVT::v4i32, { 1, 2, 1, 2 } }, // psrld
698 { ISD::SRA, MVT::v4i32, { 1, 2, 1, 2 } }, // psrad
699 { ISD::SHL, MVT::v8i32, { 2, 4, 2, 3 } }, // pslld
700 { ISD::SRL, MVT::v8i32, { 2, 4, 2, 3 } }, // psrld
701 { ISD::SRA, MVT::v8i32, { 2, 4, 2, 3 } }, // psrad
702
703 { ISD::SHL, MVT::v2i64, { 1, 2, 1, 2 } }, // psllq
704 { ISD::SRL, MVT::v2i64, { 1, 2, 1, 2 } }, // psrlq
705 { ISD::SRA, MVT::v2i64, { 2, 4, 5, 7 } }, // 2 x psrad + shuffle.
706 { ISD::SHL, MVT::v4i64, { 2, 4, 1, 2 } }, // psllq
707 { ISD::SRL, MVT::v4i64, { 2, 4, 1, 2 } }, // psrlq
708 { ISD::SRA, MVT::v4i64, { 4, 6, 5, 9 } }, // 2 x psrad + shuffle.
709 };
710
711 if (ST->hasAVX2() && Op2Info.isUniform())
712 if (const auto *Entry =
713 CostTableLookup(AVX2UniformCostTable, ISD, LT.second))
714 if (auto KindCost = Entry->Cost[CostKind])
715 return LT.first * *KindCost;
716
717 static const CostKindTblEntry AVXUniformCostTable[] = {
718 { ISD::SHL, MVT::v16i8, { 4, 4, 6, 8 } }, // psllw + pand.
719 { ISD::SRL, MVT::v16i8, { 4, 8, 5, 8 } }, // psrlw + pand.
720 { ISD::SRA, MVT::v16i8, { 6, 6, 9,13 } }, // psrlw, pand, pxor, psubb.
721 { ISD::SHL, MVT::v32i8, { 7, 8,11,14 } }, // psllw + pand + split.
722 { ISD::SRL, MVT::v32i8, { 7, 9,10,14 } }, // psrlw + pand + split.
723 { ISD::SRA, MVT::v32i8, { 10,11,16,21 } }, // psrlw, pand, pxor, psubb + split.
724
725 { ISD::SHL, MVT::v8i16, { 1, 3, 1, 2 } }, // psllw.
726 { ISD::SRL, MVT::v8i16, { 1, 3, 1, 2 } }, // psrlw.
727 { ISD::SRA, MVT::v8i16, { 1, 3, 1, 2 } }, // psraw.
728 { ISD::SHL, MVT::v16i16, { 3, 7, 5, 7 } }, // psllw + split.
729 { ISD::SRL, MVT::v16i16, { 3, 7, 5, 7 } }, // psrlw + split.
730 { ISD::SRA, MVT::v16i16, { 3, 7, 5, 7 } }, // psraw + split.
731
732 { ISD::SHL, MVT::v4i32, { 1, 3, 1, 2 } }, // pslld.
733 { ISD::SRL, MVT::v4i32, { 1, 3, 1, 2 } }, // psrld.
734 { ISD::SRA, MVT::v4i32, { 1, 3, 1, 2 } }, // psrad.
735 { ISD::SHL, MVT::v8i32, { 3, 7, 5, 7 } }, // pslld + split.
736 { ISD::SRL, MVT::v8i32, { 3, 7, 5, 7 } }, // psrld + split.
737 { ISD::SRA, MVT::v8i32, { 3, 7, 5, 7 } }, // psrad + split.
738
739 { ISD::SHL, MVT::v2i64, { 1, 3, 1, 2 } }, // psllq.
740 { ISD::SRL, MVT::v2i64, { 1, 3, 1, 2 } }, // psrlq.
741 { ISD::SRA, MVT::v2i64, { 3, 4, 5, 7 } }, // 2 x psrad + shuffle.
742 { ISD::SHL, MVT::v4i64, { 3, 7, 4, 6 } }, // psllq + split.
743 { ISD::SRL, MVT::v4i64, { 3, 7, 4, 6 } }, // psrlq + split.
744 { ISD::SRA, MVT::v4i64, { 6, 7,10,13 } }, // 2 x (2 x psrad + shuffle) + split.
745 };
746
747 // XOP has faster vXi8 shifts.
748 if (ST->hasAVX() && Op2Info.isUniform() &&
749 (!ST->hasXOP() || LT.second.getScalarSizeInBits() != 8))
750 if (const auto *Entry =
751 CostTableLookup(AVXUniformCostTable, ISD, LT.second))
752 if (auto KindCost = Entry->Cost[CostKind])
753 return LT.first * *KindCost;
754
755 static const CostKindTblEntry SSE2UniformCostTable[] = {
756 // Uniform splats are cheaper for the following instructions.
757 { ISD::SHL, MVT::v16i8, { 9, 10, 6, 9 } }, // psllw + pand.
758 { ISD::SRL, MVT::v16i8, { 9, 13, 5, 9 } }, // psrlw + pand.
759 { ISD::SRA, MVT::v16i8, { 11, 15, 9,13 } }, // pcmpgtb sequence.
760
761 { ISD::SHL, MVT::v8i16, { 2, 2, 1, 2 } }, // psllw.
762 { ISD::SRL, MVT::v8i16, { 2, 2, 1, 2 } }, // psrlw.
763 { ISD::SRA, MVT::v8i16, { 2, 2, 1, 2 } }, // psraw.
764
765 { ISD::SHL, MVT::v4i32, { 2, 2, 1, 2 } }, // pslld
766 { ISD::SRL, MVT::v4i32, { 2, 2, 1, 2 } }, // psrld.
767 { ISD::SRA, MVT::v4i32, { 2, 2, 1, 2 } }, // psrad.
768
769 { ISD::SHL, MVT::v2i64, { 2, 2, 1, 2 } }, // psllq.
770 { ISD::SRL, MVT::v2i64, { 2, 2, 1, 2 } }, // psrlq.
771 { ISD::SRA, MVT::v2i64, { 5, 9, 5, 7 } }, // 2*psrlq + xor + sub.
772 };
773
774 if (ST->hasSSE2() && Op2Info.isUniform() &&
775 (!ST->hasXOP() || LT.second.getScalarSizeInBits() != 8))
776 if (const auto *Entry =
777 CostTableLookup(SSE2UniformCostTable, ISD, LT.second))
778 if (auto KindCost = Entry->Cost[CostKind])
779 return LT.first * *KindCost;
780
781 static const CostKindTblEntry AVX512DQCostTable[] = {
782 { ISD::MUL, MVT::v2i64, { 2, 15, 1, 3 } }, // pmullq
783 { ISD::MUL, MVT::v4i64, { 2, 15, 1, 3 } }, // pmullq
784 { ISD::MUL, MVT::v8i64, { 3, 15, 1, 3 } } // pmullq
785 };
786
787 // Look for AVX512DQ lowering tricks for custom cases.
788 if (ST->hasDQI())
789 if (const auto *Entry = CostTableLookup(AVX512DQCostTable, ISD, LT.second))
790 if (auto KindCost = Entry->Cost[CostKind])
791 return LT.first * *KindCost;
792
793 static const CostKindTblEntry AVX512BWCostTable[] = {
794 { ISD::SHL, MVT::v16i8, { 4, 8, 4, 5 } }, // extend/vpsllvw/pack sequence.
795 { ISD::SRL, MVT::v16i8, { 4, 8, 4, 5 } }, // extend/vpsrlvw/pack sequence.
796 { ISD::SRA, MVT::v16i8, { 4, 8, 4, 5 } }, // extend/vpsravw/pack sequence.
797 { ISD::SHL, MVT::v32i8, { 4, 23,11,16 } }, // extend/vpsllvw/pack sequence.
798 { ISD::SRL, MVT::v32i8, { 4, 30,12,18 } }, // extend/vpsrlvw/pack sequence.
799 { ISD::SRA, MVT::v32i8, { 6, 13,24,30 } }, // extend/vpsravw/pack sequence.
800 { ISD::SHL, MVT::v64i8, { 6, 19,13,15 } }, // extend/vpsllvw/pack sequence.
801 { ISD::SRL, MVT::v64i8, { 7, 27,15,18 } }, // extend/vpsrlvw/pack sequence.
802 { ISD::SRA, MVT::v64i8, { 15, 15,30,30 } }, // extend/vpsravw/pack sequence.
803
804 { ISD::SHL, MVT::v8i16, { 1, 1, 1, 1 } }, // vpsllvw
805 { ISD::SRL, MVT::v8i16, { 1, 1, 1, 1 } }, // vpsrlvw
806 { ISD::SRA, MVT::v8i16, { 1, 1, 1, 1 } }, // vpsravw
807 { ISD::SHL, MVT::v16i16, { 1, 1, 1, 1 } }, // vpsllvw
808 { ISD::SRL, MVT::v16i16, { 1, 1, 1, 1 } }, // vpsrlvw
809 { ISD::SRA, MVT::v16i16, { 1, 1, 1, 1 } }, // vpsravw
810 { ISD::SHL, MVT::v32i16, { 1, 1, 1, 1 } }, // vpsllvw
811 { ISD::SRL, MVT::v32i16, { 1, 1, 1, 1 } }, // vpsrlvw
812 { ISD::SRA, MVT::v32i16, { 1, 1, 1, 1 } }, // vpsravw
813
814 { ISD::ADD, MVT::v64i8, { 1, 1, 1, 1 } }, // paddb
815 { ISD::ADD, MVT::v32i16, { 1, 1, 1, 1 } }, // paddw
816
817 { ISD::ADD, MVT::v32i8, { 1, 1, 1, 1 } }, // paddb
818 { ISD::ADD, MVT::v16i16, { 1, 1, 1, 1 } }, // paddw
819 { ISD::ADD, MVT::v8i32, { 1, 1, 1, 1 } }, // paddd
820 { ISD::ADD, MVT::v4i64, { 1, 1, 1, 1 } }, // paddq
821
822 { ISD::SUB, MVT::v64i8, { 1, 1, 1, 1 } }, // psubb
823 { ISD::SUB, MVT::v32i16, { 1, 1, 1, 1 } }, // psubw
824
825 { ISD::MUL, MVT::v64i8, { 5, 10,10,11 } },
826 { ISD::MUL, MVT::v32i16, { 1, 5, 1, 1 } }, // pmullw
827
828 { ISD::SUB, MVT::v32i8, { 1, 1, 1, 1 } }, // psubb
829 { ISD::SUB, MVT::v16i16, { 1, 1, 1, 1 } }, // psubw
830 { ISD::SUB, MVT::v8i32, { 1, 1, 1, 1 } }, // psubd
831 { ISD::SUB, MVT::v4i64, { 1, 1, 1, 1 } }, // psubq
832 };
833
834 // Look for AVX512BW lowering tricks for custom cases.
835 if (ST->hasBWI())
836 if (const auto *Entry = CostTableLookup(AVX512BWCostTable, ISD, LT.second))
837 if (auto KindCost = Entry->Cost[CostKind])
838 return LT.first * *KindCost;
839
840 static const CostKindTblEntry AVX512CostTable[] = {
841 { ISD::SHL, MVT::v64i8, { 15, 19,27,33 } }, // vpblendv+split sequence.
842 { ISD::SRL, MVT::v64i8, { 15, 19,30,36 } }, // vpblendv+split sequence.
843 { ISD::SRA, MVT::v64i8, { 37, 37,51,63 } }, // vpblendv+split sequence.
844
845 { ISD::SHL, MVT::v32i16, { 11, 16,11,15 } }, // 2*extend/vpsrlvd/pack sequence.
846 { ISD::SRL, MVT::v32i16, { 11, 16,11,15 } }, // 2*extend/vpsrlvd/pack sequence.
847 { ISD::SRA, MVT::v32i16, { 11, 16,11,15 } }, // 2*extend/vpsravd/pack sequence.
848
849 { ISD::SHL, MVT::v4i32, { 1, 1, 1, 1 } },
850 { ISD::SRL, MVT::v4i32, { 1, 1, 1, 1 } },
851 { ISD::SRA, MVT::v4i32, { 1, 1, 1, 1 } },
852 { ISD::SHL, MVT::v8i32, { 1, 1, 1, 1 } },
853 { ISD::SRL, MVT::v8i32, { 1, 1, 1, 1 } },
854 { ISD::SRA, MVT::v8i32, { 1, 1, 1, 1 } },
855 { ISD::SHL, MVT::v16i32, { 1, 1, 1, 1 } },
856 { ISD::SRL, MVT::v16i32, { 1, 1, 1, 1 } },
857 { ISD::SRA, MVT::v16i32, { 1, 1, 1, 1 } },
858
859 { ISD::SHL, MVT::v2i64, { 1, 1, 1, 1 } },
860 { ISD::SRL, MVT::v2i64, { 1, 1, 1, 1 } },
861 { ISD::SRA, MVT::v2i64, { 1, 1, 1, 1 } },
862 { ISD::SHL, MVT::v4i64, { 1, 1, 1, 1 } },
863 { ISD::SRL, MVT::v4i64, { 1, 1, 1, 1 } },
864 { ISD::SRA, MVT::v4i64, { 1, 1, 1, 1 } },
865 { ISD::SHL, MVT::v8i64, { 1, 1, 1, 1 } },
866 { ISD::SRL, MVT::v8i64, { 1, 1, 1, 1 } },
867 { ISD::SRA, MVT::v8i64, { 1, 1, 1, 1 } },
868
869 { ISD::ADD, MVT::v64i8, { 3, 7, 5, 5 } }, // 2*paddb + split
870 { ISD::ADD, MVT::v32i16, { 3, 7, 5, 5 } }, // 2*paddw + split
871
872 { ISD::SUB, MVT::v64i8, { 3, 7, 5, 5 } }, // 2*psubb + split
873 { ISD::SUB, MVT::v32i16, { 3, 7, 5, 5 } }, // 2*psubw + split
874
875 { ISD::AND, MVT::v32i8, { 1, 1, 1, 1 } },
876 { ISD::AND, MVT::v16i16, { 1, 1, 1, 1 } },
877 { ISD::AND, MVT::v8i32, { 1, 1, 1, 1 } },
878 { ISD::AND, MVT::v4i64, { 1, 1, 1, 1 } },
879
880 { ISD::OR, MVT::v32i8, { 1, 1, 1, 1 } },
881 { ISD::OR, MVT::v16i16, { 1, 1, 1, 1 } },
882 { ISD::OR, MVT::v8i32, { 1, 1, 1, 1 } },
883 { ISD::OR, MVT::v4i64, { 1, 1, 1, 1 } },
884
885 { ISD::XOR, MVT::v32i8, { 1, 1, 1, 1 } },
886 { ISD::XOR, MVT::v16i16, { 1, 1, 1, 1 } },
887 { ISD::XOR, MVT::v8i32, { 1, 1, 1, 1 } },
888 { ISD::XOR, MVT::v4i64, { 1, 1, 1, 1 } },
889
890 { ISD::MUL, MVT::v16i32, { 1, 10, 1, 2 } }, // pmulld (Skylake from agner.org)
891 { ISD::MUL, MVT::v8i32, { 1, 10, 1, 2 } }, // pmulld (Skylake from agner.org)
892 { ISD::MUL, MVT::v4i32, { 1, 10, 1, 2 } }, // pmulld (Skylake from agner.org)
893 { ISD::MUL, MVT::v8i64, { 6, 9, 8, 8 } }, // 3*pmuludq/3*shift/2*add
894 { ISD::MUL, MVT::i64, { 1 } }, // Skylake from http://www.agner.org/
895
896 { ISD::FNEG, MVT::v8f64, { 1, 1, 1, 2 } }, // Skylake from http://www.agner.org/
897 { ISD::FADD, MVT::v8f64, { 1, 4, 1, 1 } }, // Skylake from http://www.agner.org/
898 { ISD::FADD, MVT::v4f64, { 1, 4, 1, 1 } }, // Skylake from http://www.agner.org/
899 { ISD::FSUB, MVT::v8f64, { 1, 4, 1, 1 } }, // Skylake from http://www.agner.org/
900 { ISD::FSUB, MVT::v4f64, { 1, 4, 1, 1 } }, // Skylake from http://www.agner.org/
901 { ISD::FMUL, MVT::v8f64, { 1, 4, 1, 1 } }, // Skylake from http://www.agner.org/
902 { ISD::FMUL, MVT::v4f64, { 1, 4, 1, 1 } }, // Skylake from http://www.agner.org/
903 { ISD::FMUL, MVT::v2f64, { 1, 4, 1, 1 } }, // Skylake from http://www.agner.org/
904 { ISD::FMUL, MVT::f64, { 1, 4, 1, 1 } }, // Skylake from http://www.agner.org/
905
906 { ISD::FDIV, MVT::f64, { 4, 14, 1, 1 } }, // Skylake from http://www.agner.org/
907 { ISD::FDIV, MVT::v2f64, { 4, 14, 1, 1 } }, // Skylake from http://www.agner.org/
908 { ISD::FDIV, MVT::v4f64, { 8, 14, 1, 1 } }, // Skylake from http://www.agner.org/
909 { ISD::FDIV, MVT::v8f64, { 16, 23, 1, 3 } }, // Skylake from http://www.agner.org/
910
911 { ISD::FNEG, MVT::v16f32, { 1, 1, 1, 2 } }, // Skylake from http://www.agner.org/
912 { ISD::FADD, MVT::v16f32, { 1, 4, 1, 1 } }, // Skylake from http://www.agner.org/
913 { ISD::FADD, MVT::v8f32, { 1, 4, 1, 1 } }, // Skylake from http://www.agner.org/
914 { ISD::FSUB, MVT::v16f32, { 1, 4, 1, 1 } }, // Skylake from http://www.agner.org/
915 { ISD::FSUB, MVT::v8f32, { 1, 4, 1, 1 } }, // Skylake from http://www.agner.org/
916 { ISD::FMUL, MVT::v16f32, { 1, 4, 1, 1 } }, // Skylake from http://www.agner.org/
917 { ISD::FMUL, MVT::v8f32, { 1, 4, 1, 1 } }, // Skylake from http://www.agner.org/
918 { ISD::FMUL, MVT::v4f32, { 1, 4, 1, 1 } }, // Skylake from http://www.agner.org/
919 { ISD::FMUL, MVT::f32, { 1, 4, 1, 1 } }, // Skylake from http://www.agner.org/
920
921 { ISD::FDIV, MVT::f32, { 3, 11, 1, 1 } }, // Skylake from http://www.agner.org/
922 { ISD::FDIV, MVT::v4f32, { 3, 11, 1, 1 } }, // Skylake from http://www.agner.org/
923 { ISD::FDIV, MVT::v8f32, { 5, 11, 1, 1 } }, // Skylake from http://www.agner.org/
924 { ISD::FDIV, MVT::v16f32, { 10, 18, 1, 3 } }, // Skylake from http://www.agner.org/
925 };
926
927 if (ST->hasAVX512())
928 if (const auto *Entry = CostTableLookup(AVX512CostTable, ISD, LT.second))
929 if (auto KindCost = Entry->Cost[CostKind])
930 return LT.first * *KindCost;
931
932 static const CostKindTblEntry AVX2ShiftCostTable[] = {
933 // Shifts on vXi64/vXi32 on AVX2 is legal even though we declare to
934 // customize them to detect the cases where shift amount is a scalar one.
935 { ISD::SHL, MVT::v4i32, { 2, 3, 1, 3 } }, // vpsllvd (Haswell from agner.org)
936 { ISD::SRL, MVT::v4i32, { 2, 3, 1, 3 } }, // vpsrlvd (Haswell from agner.org)
937 { ISD::SRA, MVT::v4i32, { 2, 3, 1, 3 } }, // vpsravd (Haswell from agner.org)
938 { ISD::SHL, MVT::v8i32, { 4, 4, 1, 3 } }, // vpsllvd (Haswell from agner.org)
939 { ISD::SRL, MVT::v8i32, { 4, 4, 1, 3 } }, // vpsrlvd (Haswell from agner.org)
940 { ISD::SRA, MVT::v8i32, { 4, 4, 1, 3 } }, // vpsravd (Haswell from agner.org)
941 { ISD::SHL, MVT::v2i64, { 2, 3, 1, 1 } }, // vpsllvq (Haswell from agner.org)
942 { ISD::SRL, MVT::v2i64, { 2, 3, 1, 1 } }, // vpsrlvq (Haswell from agner.org)
943 { ISD::SHL, MVT::v4i64, { 4, 4, 1, 2 } }, // vpsllvq (Haswell from agner.org)
944 { ISD::SRL, MVT::v4i64, { 4, 4, 1, 2 } }, // vpsrlvq (Haswell from agner.org)
945 };
946
947 if (ST->hasAVX512()) {
948 if (ISD == ISD::SHL && LT.second == MVT::v32i16 && Op2Info.isConstant())
949 // On AVX512, a packed v32i16 shift left by a constant build_vector
950 // is lowered into a vector multiply (vpmullw).
951 return getArithmeticInstrCost(Instruction::Mul, Ty, CostKind,
952 Op1Info.getNoProps(), Op2Info.getNoProps());
953 }
954
955 // Look for AVX2 lowering tricks (XOP is always better at v4i32 shifts).
956 if (ST->hasAVX2() && !(ST->hasXOP() && LT.second == MVT::v4i32)) {
957 if (ISD == ISD::SHL && LT.second == MVT::v16i16 &&
958 Op2Info.isConstant())
959 // On AVX2, a packed v16i16 shift left by a constant build_vector
960 // is lowered into a vector multiply (vpmullw).
961 return getArithmeticInstrCost(Instruction::Mul, Ty, CostKind,
962 Op1Info.getNoProps(), Op2Info.getNoProps());
963
964 if (const auto *Entry = CostTableLookup(AVX2ShiftCostTable, ISD, LT.second))
965 if (auto KindCost = Entry->Cost[CostKind])
966 return LT.first * *KindCost;
967 }
968
969 static const CostKindTblEntry XOPShiftCostTable[] = {
970 // 128bit shifts take 1cy, but right shifts require negation beforehand.
971 { ISD::SHL, MVT::v16i8, { 1, 3, 1, 1 } },
972 { ISD::SRL, MVT::v16i8, { 2, 3, 1, 1 } },
973 { ISD::SRA, MVT::v16i8, { 2, 3, 1, 1 } },
974 { ISD::SHL, MVT::v8i16, { 1, 3, 1, 1 } },
975 { ISD::SRL, MVT::v8i16, { 2, 3, 1, 1 } },
976 { ISD::SRA, MVT::v8i16, { 2, 3, 1, 1 } },
977 { ISD::SHL, MVT::v4i32, { 1, 3, 1, 1 } },
978 { ISD::SRL, MVT::v4i32, { 2, 3, 1, 1 } },
979 { ISD::SRA, MVT::v4i32, { 2, 3, 1, 1 } },
980 { ISD::SHL, MVT::v2i64, { 1, 3, 1, 1 } },
981 { ISD::SRL, MVT::v2i64, { 2, 3, 1, 1 } },
982 { ISD::SRA, MVT::v2i64, { 2, 3, 1, 1 } },
983 // 256bit shifts require splitting if AVX2 didn't catch them above.
984 { ISD::SHL, MVT::v32i8, { 4, 7, 5, 6 } },
985 { ISD::SRL, MVT::v32i8, { 6, 7, 5, 6 } },
986 { ISD::SRA, MVT::v32i8, { 6, 7, 5, 6 } },
987 { ISD::SHL, MVT::v16i16, { 4, 7, 5, 6 } },
988 { ISD::SRL, MVT::v16i16, { 6, 7, 5, 6 } },
989 { ISD::SRA, MVT::v16i16, { 6, 7, 5, 6 } },
990 { ISD::SHL, MVT::v8i32, { 4, 7, 5, 6 } },
991 { ISD::SRL, MVT::v8i32, { 6, 7, 5, 6 } },
992 { ISD::SRA, MVT::v8i32, { 6, 7, 5, 6 } },
993 { ISD::SHL, MVT::v4i64, { 4, 7, 5, 6 } },
994 { ISD::SRL, MVT::v4i64, { 6, 7, 5, 6 } },
995 { ISD::SRA, MVT::v4i64, { 6, 7, 5, 6 } },
996 };
997
998 // Look for XOP lowering tricks.
999 if (ST->hasXOP()) {
1000 // If the right shift is constant then we'll fold the negation so
1001 // it's as cheap as a left shift.
1002 int ShiftISD = ISD;
1003 if ((ShiftISD == ISD::SRL || ShiftISD == ISD::SRA) && Op2Info.isConstant())
1004 ShiftISD = ISD::SHL;
1005 if (const auto *Entry =
1006 CostTableLookup(XOPShiftCostTable, ShiftISD, LT.second))
1007 if (auto KindCost = Entry->Cost[CostKind])
1008 return LT.first * *KindCost;
1009 }
1010
1011 if (ISD == ISD::SHL && !Op2Info.isUniform() && Op2Info.isConstant()) {
1012 MVT VT = LT.second;
1013 // Vector shift left by non uniform constant can be lowered
1014 // into vector multiply.
1015 if (((VT == MVT::v8i16 || VT == MVT::v4i32) && ST->hasSSE2()) ||
1016 ((VT == MVT::v16i16 || VT == MVT::v8i32) && ST->hasAVX()))
1017 ISD = ISD::MUL;
1018 }
1019
1020 static const CostKindTblEntry GLMCostTable[] = {
1021 { ISD::FDIV, MVT::f32, { 18, 19, 1, 1 } }, // divss
1022 { ISD::FDIV, MVT::v4f32, { 35, 36, 1, 1 } }, // divps
1023 { ISD::FDIV, MVT::f64, { 33, 34, 1, 1 } }, // divsd
1024 { ISD::FDIV, MVT::v2f64, { 65, 66, 1, 1 } }, // divpd
1025 };
1026
1027 if (ST->useGLMDivSqrtCosts())
1028 if (const auto *Entry = CostTableLookup(GLMCostTable, ISD, LT.second))
1029 if (auto KindCost = Entry->Cost[CostKind])
1030 return LT.first * *KindCost;
1031
1032 static const CostKindTblEntry SLMCostTable[] = {
1033 { ISD::MUL, MVT::v4i32, { 11, 11, 1, 7 } }, // pmulld
1034 { ISD::MUL, MVT::v8i16, { 2, 5, 1, 1 } }, // pmullw
1035 { ISD::FMUL, MVT::f64, { 2, 5, 1, 1 } }, // mulsd
1036 { ISD::FMUL, MVT::f32, { 1, 4, 1, 1 } }, // mulss
1037 { ISD::FMUL, MVT::v2f64, { 4, 7, 1, 1 } }, // mulpd
1038 { ISD::FMUL, MVT::v4f32, { 2, 5, 1, 1 } }, // mulps
1039 { ISD::FDIV, MVT::f32, { 17, 19, 1, 1 } }, // divss
1040 { ISD::FDIV, MVT::v4f32, { 39, 39, 1, 6 } }, // divps
1041 { ISD::FDIV, MVT::f64, { 32, 34, 1, 1 } }, // divsd
1042 { ISD::FDIV, MVT::v2f64, { 69, 69, 1, 6 } }, // divpd
1043 { ISD::FADD, MVT::v2f64, { 2, 4, 1, 1 } }, // addpd
1044 { ISD::FSUB, MVT::v2f64, { 2, 4, 1, 1 } }, // subpd
1045 // v2i64/v4i64 mul is custom lowered as a series of long:
1046 // multiplies(3), shifts(3) and adds(2)
1047 // slm muldq version throughput is 2 and addq throughput 4
1048 // thus: 3X2 (muldq throughput) + 3X1 (shift throughput) +
1049 // 3X4 (addq throughput) = 17
1050 { ISD::MUL, MVT::v2i64, { 17, 22, 9, 9 } },
1051 // slm addq\subq throughput is 4
1052 { ISD::ADD, MVT::v2i64, { 4, 2, 1, 2 } },
1053 { ISD::SUB, MVT::v2i64, { 4, 2, 1, 2 } },
1054 };
1055
1056 if (ST->useSLMArithCosts())
1057 if (const auto *Entry = CostTableLookup(SLMCostTable, ISD, LT.second))
1058 if (auto KindCost = Entry->Cost[CostKind])
1059 return LT.first * *KindCost;
1060
1061 static const CostKindTblEntry AVX2CostTable[] = {
1062 { ISD::SHL, MVT::v16i8, { 6, 21,11,16 } }, // vpblendvb sequence.
1063 { ISD::SHL, MVT::v32i8, { 6, 23,11,22 } }, // vpblendvb sequence.
1064 { ISD::SHL, MVT::v8i16, { 5, 18, 5,10 } }, // extend/vpsrlvd/pack sequence.
1065 { ISD::SHL, MVT::v16i16, { 8, 10,10,14 } }, // extend/vpsrlvd/pack sequence.
1066
1067 { ISD::SRL, MVT::v16i8, { 6, 27,12,18 } }, // vpblendvb sequence.
1068 { ISD::SRL, MVT::v32i8, { 8, 30,12,24 } }, // vpblendvb sequence.
1069 { ISD::SRL, MVT::v8i16, { 5, 11, 5,10 } }, // extend/vpsrlvd/pack sequence.
1070 { ISD::SRL, MVT::v16i16, { 8, 10,10,14 } }, // extend/vpsrlvd/pack sequence.
1071
1072 { ISD::SRA, MVT::v16i8, { 17, 17,24,30 } }, // vpblendvb sequence.
1073 { ISD::SRA, MVT::v32i8, { 18, 20,24,43 } }, // vpblendvb sequence.
1074 { ISD::SRA, MVT::v8i16, { 5, 11, 5,10 } }, // extend/vpsravd/pack sequence.
1075 { ISD::SRA, MVT::v16i16, { 8, 10,10,14 } }, // extend/vpsravd/pack sequence.
1076 { ISD::SRA, MVT::v2i64, { 4, 5, 5, 5 } }, // srl/xor/sub sequence.
1077 { ISD::SRA, MVT::v4i64, { 8, 8, 5, 9 } }, // srl/xor/sub sequence.
1078
1079 { ISD::SUB, MVT::v32i8, { 1, 1, 1, 2 } }, // psubb
1080 { ISD::ADD, MVT::v32i8, { 1, 1, 1, 2 } }, // paddb
1081 { ISD::SUB, MVT::v16i16, { 1, 1, 1, 2 } }, // psubw
1082 { ISD::ADD, MVT::v16i16, { 1, 1, 1, 2 } }, // paddw
1083 { ISD::SUB, MVT::v8i32, { 1, 1, 1, 2 } }, // psubd
1084 { ISD::ADD, MVT::v8i32, { 1, 1, 1, 2 } }, // paddd
1085 { ISD::SUB, MVT::v4i64, { 1, 1, 1, 2 } }, // psubq
1086 { ISD::ADD, MVT::v4i64, { 1, 1, 1, 2 } }, // paddq
1087
1088 { ISD::MUL, MVT::v16i8, { 5, 18, 6,12 } }, // extend/pmullw/pack
1089 { ISD::MUL, MVT::v32i8, { 6, 11,10,19 } }, // unpack/pmullw
1090 { ISD::MUL, MVT::v16i16, { 2, 5, 1, 2 } }, // pmullw
1091 { ISD::MUL, MVT::v8i32, { 4, 10, 1, 2 } }, // pmulld
1092 { ISD::MUL, MVT::v4i32, { 2, 10, 1, 2 } }, // pmulld
1093 { ISD::MUL, MVT::v4i64, { 6, 10, 8,13 } }, // 3*pmuludq/3*shift/2*add
1094 { ISD::MUL, MVT::v2i64, { 6, 10, 8, 8 } }, // 3*pmuludq/3*shift/2*add
1095
1096 { ISD::FNEG, MVT::v4f64, { 1, 1, 1, 2 } }, // vxorpd
1097 { ISD::FNEG, MVT::v8f32, { 1, 1, 1, 2 } }, // vxorps
1098
1099 { ISD::FADD, MVT::f64, { 1, 4, 1, 1 } }, // vaddsd
1100 { ISD::FADD, MVT::f32, { 1, 4, 1, 1 } }, // vaddss
1101 { ISD::FADD, MVT::v2f64, { 1, 4, 1, 1 } }, // vaddpd
1102 { ISD::FADD, MVT::v4f32, { 1, 4, 1, 1 } }, // vaddps
1103 { ISD::FADD, MVT::v4f64, { 1, 4, 1, 2 } }, // vaddpd
1104 { ISD::FADD, MVT::v8f32, { 1, 4, 1, 2 } }, // vaddps
1105
1106 { ISD::FSUB, MVT::f64, { 1, 4, 1, 1 } }, // vsubsd
1107 { ISD::FSUB, MVT::f32, { 1, 4, 1, 1 } }, // vsubss
1108 { ISD::FSUB, MVT::v2f64, { 1, 4, 1, 1 } }, // vsubpd
1109 { ISD::FSUB, MVT::v4f32, { 1, 4, 1, 1 } }, // vsubps
1110 { ISD::FSUB, MVT::v4f64, { 1, 4, 1, 2 } }, // vsubpd
1111 { ISD::FSUB, MVT::v8f32, { 1, 4, 1, 2 } }, // vsubps
1112
1113 { ISD::FMUL, MVT::f64, { 1, 5, 1, 1 } }, // vmulsd
1114 { ISD::FMUL, MVT::f32, { 1, 5, 1, 1 } }, // vmulss
1115 { ISD::FMUL, MVT::v2f64, { 1, 5, 1, 1 } }, // vmulpd
1116 { ISD::FMUL, MVT::v4f32, { 1, 5, 1, 1 } }, // vmulps
1117 { ISD::FMUL, MVT::v4f64, { 1, 5, 1, 2 } }, // vmulpd
1118 { ISD::FMUL, MVT::v8f32, { 1, 5, 1, 2 } }, // vmulps
1119
1120 { ISD::FDIV, MVT::f32, { 7, 13, 1, 1 } }, // vdivss
1121 { ISD::FDIV, MVT::v4f32, { 7, 13, 1, 1 } }, // vdivps
1122 { ISD::FDIV, MVT::v8f32, { 14, 21, 1, 3 } }, // vdivps
1123 { ISD::FDIV, MVT::f64, { 14, 20, 1, 1 } }, // vdivsd
1124 { ISD::FDIV, MVT::v2f64, { 14, 20, 1, 1 } }, // vdivpd
1125 { ISD::FDIV, MVT::v4f64, { 28, 35, 1, 3 } }, // vdivpd
1126 };
1127
1128 // Look for AVX2 lowering tricks for custom cases.
1129 if (ST->hasAVX2())
1130 if (const auto *Entry = CostTableLookup(AVX2CostTable, ISD, LT.second))
1131 if (auto KindCost = Entry->Cost[CostKind])
1132 return LT.first * *KindCost;
1133
1134 static const CostKindTblEntry AVX1CostTable[] = {
1135 // We don't have to scalarize unsupported ops. We can issue two half-sized
1136 // operations and we only need to extract the upper YMM half.
1137 // Two ops + 1 extract + 1 insert = 4.
1138 { ISD::MUL, MVT::v32i8, { 12, 13, 22, 23 } }, // unpack/pmullw + split
1139 { ISD::MUL, MVT::v16i16, { 4, 8, 5, 6 } }, // pmullw + split
1140 { ISD::MUL, MVT::v8i32, { 5, 8, 5, 10 } }, // pmulld + split
1141 { ISD::MUL, MVT::v4i32, { 2, 5, 1, 3 } }, // pmulld
1142 { ISD::MUL, MVT::v4i64, { 12, 15, 19, 20 } },
1143
1144 { ISD::AND, MVT::v32i8, { 1, 1, 1, 2 } }, // vandps
1145 { ISD::AND, MVT::v16i16, { 1, 1, 1, 2 } }, // vandps
1146 { ISD::AND, MVT::v8i32, { 1, 1, 1, 2 } }, // vandps
1147 { ISD::AND, MVT::v4i64, { 1, 1, 1, 2 } }, // vandps
1148
1149 { ISD::OR, MVT::v32i8, { 1, 1, 1, 2 } }, // vorps
1150 { ISD::OR, MVT::v16i16, { 1, 1, 1, 2 } }, // vorps
1151 { ISD::OR, MVT::v8i32, { 1, 1, 1, 2 } }, // vorps
1152 { ISD::OR, MVT::v4i64, { 1, 1, 1, 2 } }, // vorps
1153
1154 { ISD::XOR, MVT::v32i8, { 1, 1, 1, 2 } }, // vxorps
1155 { ISD::XOR, MVT::v16i16, { 1, 1, 1, 2 } }, // vxorps
1156 { ISD::XOR, MVT::v8i32, { 1, 1, 1, 2 } }, // vxorps
1157 { ISD::XOR, MVT::v4i64, { 1, 1, 1, 2 } }, // vxorps
1158
1159 { ISD::SUB, MVT::v32i8, { 4, 2, 5, 6 } }, // psubb + split
1160 { ISD::ADD, MVT::v32i8, { 4, 2, 5, 6 } }, // paddb + split
1161 { ISD::SUB, MVT::v16i16, { 4, 2, 5, 6 } }, // psubw + split
1162 { ISD::ADD, MVT::v16i16, { 4, 2, 5, 6 } }, // paddw + split
1163 { ISD::SUB, MVT::v8i32, { 4, 2, 5, 6 } }, // psubd + split
1164 { ISD::ADD, MVT::v8i32, { 4, 2, 5, 6 } }, // paddd + split
1165 { ISD::SUB, MVT::v4i64, { 4, 2, 5, 6 } }, // psubq + split
1166 { ISD::ADD, MVT::v4i64, { 4, 2, 5, 6 } }, // paddq + split
1167 { ISD::SUB, MVT::v2i64, { 1, 1, 1, 1 } }, // psubq
1168 { ISD::ADD, MVT::v2i64, { 1, 1, 1, 1 } }, // paddq
1169
1170 { ISD::SHL, MVT::v16i8, { 10, 21,11,17 } }, // pblendvb sequence.
1171 { ISD::SHL, MVT::v32i8, { 22, 22,27,40 } }, // pblendvb sequence + split.
1172 { ISD::SHL, MVT::v8i16, { 6, 9,11,11 } }, // pblendvb sequence.
1173 { ISD::SHL, MVT::v16i16, { 13, 16,24,25 } }, // pblendvb sequence + split.
1174 { ISD::SHL, MVT::v4i32, { 3, 11, 4, 6 } }, // pslld/paddd/cvttps2dq/pmulld
1175 { ISD::SHL, MVT::v8i32, { 9, 11,12,17 } }, // pslld/paddd/cvttps2dq/pmulld + split
1176 { ISD::SHL, MVT::v2i64, { 2, 4, 4, 6 } }, // Shift each lane + blend.
1177 { ISD::SHL, MVT::v4i64, { 6, 7,11,15 } }, // Shift each lane + blend + split.
1178
1179 { ISD::SRL, MVT::v16i8, { 11, 27,12,18 } }, // pblendvb sequence.
1180 { ISD::SRL, MVT::v32i8, { 23, 23,30,43 } }, // pblendvb sequence + split.
1181 { ISD::SRL, MVT::v8i16, { 13, 16,14,22 } }, // pblendvb sequence.
1182 { ISD::SRL, MVT::v16i16, { 28, 30,31,48 } }, // pblendvb sequence + split.
1183 { ISD::SRL, MVT::v4i32, { 6, 7,12,16 } }, // Shift each lane + blend.
1184 { ISD::SRL, MVT::v8i32, { 14, 14,26,34 } }, // Shift each lane + blend + split.
1185 { ISD::SRL, MVT::v2i64, { 2, 4, 4, 6 } }, // Shift each lane + blend.
1186 { ISD::SRL, MVT::v4i64, { 6, 7,11,15 } }, // Shift each lane + blend + split.
1187
1188 { ISD::SRA, MVT::v16i8, { 21, 22,24,36 } }, // pblendvb sequence.
1189 { ISD::SRA, MVT::v32i8, { 44, 45,51,76 } }, // pblendvb sequence + split.
1190 { ISD::SRA, MVT::v8i16, { 13, 16,14,22 } }, // pblendvb sequence.
1191 { ISD::SRA, MVT::v16i16, { 28, 30,31,48 } }, // pblendvb sequence + split.
1192 { ISD::SRA, MVT::v4i32, { 6, 7,12,16 } }, // Shift each lane + blend.
1193 { ISD::SRA, MVT::v8i32, { 14, 14,26,34 } }, // Shift each lane + blend + split.
1194 { ISD::SRA, MVT::v2i64, { 5, 6,10,14 } }, // Shift each lane + blend.
1195 { ISD::SRA, MVT::v4i64, { 12, 12,22,30 } }, // Shift each lane + blend + split.
1196
1197 { ISD::FNEG, MVT::v4f64, { 2, 2, 1, 2 } }, // BTVER2 from http://www.agner.org/
1198 { ISD::FNEG, MVT::v8f32, { 2, 2, 1, 2 } }, // BTVER2 from http://www.agner.org/
1199
1200 { ISD::FADD, MVT::f64, { 1, 5, 1, 1 } }, // BDVER2 from http://www.agner.org/
1201 { ISD::FADD, MVT::f32, { 1, 5, 1, 1 } }, // BDVER2 from http://www.agner.org/
1202 { ISD::FADD, MVT::v2f64, { 1, 5, 1, 1 } }, // BDVER2 from http://www.agner.org/
1203 { ISD::FADD, MVT::v4f32, { 1, 5, 1, 1 } }, // BDVER2 from http://www.agner.org/
1204 { ISD::FADD, MVT::v4f64, { 2, 5, 1, 2 } }, // BDVER2 from http://www.agner.org/
1205 { ISD::FADD, MVT::v8f32, { 2, 5, 1, 2 } }, // BDVER2 from http://www.agner.org/
1206
1207 { ISD::FSUB, MVT::f64, { 1, 5, 1, 1 } }, // BDVER2 from http://www.agner.org/
1208 { ISD::FSUB, MVT::f32, { 1, 5, 1, 1 } }, // BDVER2 from http://www.agner.org/
1209 { ISD::FSUB, MVT::v2f64, { 1, 5, 1, 1 } }, // BDVER2 from http://www.agner.org/
1210 { ISD::FSUB, MVT::v4f32, { 1, 5, 1, 1 } }, // BDVER2 from http://www.agner.org/
1211 { ISD::FSUB, MVT::v4f64, { 2, 5, 1, 2 } }, // BDVER2 from http://www.agner.org/
1212 { ISD::FSUB, MVT::v8f32, { 2, 5, 1, 2 } }, // BDVER2 from http://www.agner.org/
1213
1214 { ISD::FMUL, MVT::f64, { 2, 5, 1, 1 } }, // BTVER2 from http://www.agner.org/
1215 { ISD::FMUL, MVT::f32, { 1, 5, 1, 1 } }, // BTVER2 from http://www.agner.org/
1216 { ISD::FMUL, MVT::v2f64, { 2, 5, 1, 1 } }, // BTVER2 from http://www.agner.org/
1217 { ISD::FMUL, MVT::v4f32, { 1, 5, 1, 1 } }, // BTVER2 from http://www.agner.org/
1218 { ISD::FMUL, MVT::v4f64, { 4, 5, 1, 2 } }, // BTVER2 from http://www.agner.org/
1219 { ISD::FMUL, MVT::v8f32, { 2, 5, 1, 2 } }, // BTVER2 from http://www.agner.org/
1220
1221 { ISD::FDIV, MVT::f32, { 14, 14, 1, 1 } }, // SNB from http://www.agner.org/
1222 { ISD::FDIV, MVT::v4f32, { 14, 14, 1, 1 } }, // SNB from http://www.agner.org/
1223 { ISD::FDIV, MVT::v8f32, { 28, 29, 1, 3 } }, // SNB from http://www.agner.org/
1224 { ISD::FDIV, MVT::f64, { 22, 22, 1, 1 } }, // SNB from http://www.agner.org/
1225 { ISD::FDIV, MVT::v2f64, { 22, 22, 1, 1 } }, // SNB from http://www.agner.org/
1226 { ISD::FDIV, MVT::v4f64, { 44, 45, 1, 3 } }, // SNB from http://www.agner.org/
1227 };
1228
1229 if (ST->hasAVX())
1230 if (const auto *Entry = CostTableLookup(AVX1CostTable, ISD, LT.second))
1231 if (auto KindCost = Entry->Cost[CostKind])
1232 return LT.first * *KindCost;
1233
1234 static const CostKindTblEntry SSE42CostTable[] = {
1235 { ISD::FADD, MVT::f64, { 1, 3, 1, 1 } }, // Nehalem from http://www.agner.org/
1236 { ISD::FADD, MVT::f32, { 1, 3, 1, 1 } }, // Nehalem from http://www.agner.org/
1237 { ISD::FADD, MVT::v2f64, { 1, 3, 1, 1 } }, // Nehalem from http://www.agner.org/
1238 { ISD::FADD, MVT::v4f32, { 1, 3, 1, 1 } }, // Nehalem from http://www.agner.org/
1239
1240 { ISD::FSUB, MVT::f64, { 1, 3, 1, 1 } }, // Nehalem from http://www.agner.org/
1241 { ISD::FSUB, MVT::f32 , { 1, 3, 1, 1 } }, // Nehalem from http://www.agner.org/
1242 { ISD::FSUB, MVT::v2f64, { 1, 3, 1, 1 } }, // Nehalem from http://www.agner.org/
1243 { ISD::FSUB, MVT::v4f32, { 1, 3, 1, 1 } }, // Nehalem from http://www.agner.org/
1244
1245 { ISD::FMUL, MVT::f64, { 1, 5, 1, 1 } }, // Nehalem from http://www.agner.org/
1246 { ISD::FMUL, MVT::f32, { 1, 5, 1, 1 } }, // Nehalem from http://www.agner.org/
1247 { ISD::FMUL, MVT::v2f64, { 1, 5, 1, 1 } }, // Nehalem from http://www.agner.org/
1248 { ISD::FMUL, MVT::v4f32, { 1, 5, 1, 1 } }, // Nehalem from http://www.agner.org/
1249
1250 { ISD::FDIV, MVT::f32, { 14, 14, 1, 1 } }, // Nehalem from http://www.agner.org/
1251 { ISD::FDIV, MVT::v4f32, { 14, 14, 1, 1 } }, // Nehalem from http://www.agner.org/
1252 { ISD::FDIV, MVT::f64, { 22, 22, 1, 1 } }, // Nehalem from http://www.agner.org/
1253 { ISD::FDIV, MVT::v2f64, { 22, 22, 1, 1 } }, // Nehalem from http://www.agner.org/
1254
1255 { ISD::MUL, MVT::v2i64, { 6, 10,10,10 } } // 3*pmuludq/3*shift/2*add
1256 };
1257
1258 if (ST->hasSSE42())
1259 if (const auto *Entry = CostTableLookup(SSE42CostTable, ISD, LT.second))
1260 if (auto KindCost = Entry->Cost[CostKind])
1261 return LT.first * *KindCost;
1262
1263 static const CostKindTblEntry SSE41CostTable[] = {
1264 { ISD::SHL, MVT::v16i8, { 15, 24,17,22 } }, // pblendvb sequence.
1265 { ISD::SHL, MVT::v8i16, { 11, 14,11,11 } }, // pblendvb sequence.
1266 { ISD::SHL, MVT::v4i32, { 14, 20, 4,10 } }, // pslld/paddd/cvttps2dq/pmulld
1267
1268 { ISD::SRL, MVT::v16i8, { 16, 27,18,24 } }, // pblendvb sequence.
1269 { ISD::SRL, MVT::v8i16, { 22, 26,23,27 } }, // pblendvb sequence.
1270 { ISD::SRL, MVT::v4i32, { 16, 17,15,19 } }, // Shift each lane + blend.
1271 { ISD::SRL, MVT::v2i64, { 4, 6, 5, 7 } }, // splat+shuffle sequence.
1272
1273 { ISD::SRA, MVT::v16i8, { 38, 41,30,36 } }, // pblendvb sequence.
1274 { ISD::SRA, MVT::v8i16, { 22, 26,23,27 } }, // pblendvb sequence.
1275 { ISD::SRA, MVT::v4i32, { 16, 17,15,19 } }, // Shift each lane + blend.
1276 { ISD::SRA, MVT::v2i64, { 8, 17, 5, 7 } }, // splat+shuffle sequence.
1277
1278 { ISD::MUL, MVT::v16i8, { 5, 18,10,12 } }, // 2*unpack/2*pmullw/2*and/pack
1279 { ISD::MUL, MVT::v4i32, { 2, 11, 1, 1 } } // pmulld (Nehalem from agner.org)
1280 };
1281
1282 if (ST->hasSSE41())
1283 if (const auto *Entry = CostTableLookup(SSE41CostTable, ISD, LT.second))
1284 if (auto KindCost = Entry->Cost[CostKind])
1285 return LT.first * *KindCost;
1286
1287 static const CostKindTblEntry SSE2CostTable[] = {
1288 // We don't correctly identify costs of casts because they are marked as
1289 // custom.
1290 { ISD::SHL, MVT::v16i8, { 13, 21,26,28 } }, // cmpgtb sequence.
1291 { ISD::SHL, MVT::v8i16, { 24, 27,16,20 } }, // cmpgtw sequence.
1292 { ISD::SHL, MVT::v4i32, { 17, 19,10,12 } }, // pslld/paddd/cvttps2dq/pmuludq.
1293 { ISD::SHL, MVT::v2i64, { 4, 6, 5, 7 } }, // splat+shuffle sequence.
1294
1295 { ISD::SRL, MVT::v16i8, { 14, 28,27,30 } }, // cmpgtb sequence.
1296 { ISD::SRL, MVT::v8i16, { 16, 19,31,31 } }, // cmpgtw sequence.
1297 { ISD::SRL, MVT::v4i32, { 12, 12,15,19 } }, // Shift each lane + blend.
1298 { ISD::SRL, MVT::v2i64, { 4, 6, 5, 7 } }, // splat+shuffle sequence.
1299
1300 { ISD::SRA, MVT::v16i8, { 27, 30,54,54 } }, // unpacked cmpgtb sequence.
1301 { ISD::SRA, MVT::v8i16, { 16, 19,31,31 } }, // cmpgtw sequence.
1302 { ISD::SRA, MVT::v4i32, { 12, 12,15,19 } }, // Shift each lane + blend.
1303 { ISD::SRA, MVT::v2i64, { 8, 11,12,16 } }, // srl/xor/sub splat+shuffle sequence.
1304
1305 { ISD::AND, MVT::v16i8, { 1, 1, 1, 1 } }, // pand
1306 { ISD::AND, MVT::v8i16, { 1, 1, 1, 1 } }, // pand
1307 { ISD::AND, MVT::v4i32, { 1, 1, 1, 1 } }, // pand
1308 { ISD::AND, MVT::v2i64, { 1, 1, 1, 1 } }, // pand
1309
1310 { ISD::OR, MVT::v16i8, { 1, 1, 1, 1 } }, // por
1311 { ISD::OR, MVT::v8i16, { 1, 1, 1, 1 } }, // por
1312 { ISD::OR, MVT::v4i32, { 1, 1, 1, 1 } }, // por
1313 { ISD::OR, MVT::v2i64, { 1, 1, 1, 1 } }, // por
1314
1315 { ISD::XOR, MVT::v16i8, { 1, 1, 1, 1 } }, // pxor
1316 { ISD::XOR, MVT::v8i16, { 1, 1, 1, 1 } }, // pxor
1317 { ISD::XOR, MVT::v4i32, { 1, 1, 1, 1 } }, // pxor
1318 { ISD::XOR, MVT::v2i64, { 1, 1, 1, 1 } }, // pxor
1319
1320 { ISD::ADD, MVT::v2i64, { 1, 2, 1, 2 } }, // paddq
1321 { ISD::SUB, MVT::v2i64, { 1, 2, 1, 2 } }, // psubq
1322
1323 { ISD::MUL, MVT::v16i8, { 5, 18,12,12 } }, // 2*unpack/2*pmullw/2*and/pack
1324 { ISD::MUL, MVT::v8i16, { 1, 5, 1, 1 } }, // pmullw
1325 { ISD::MUL, MVT::v4i32, { 6, 8, 7, 7 } }, // 3*pmuludq/4*shuffle
1326 { ISD::MUL, MVT::v2i64, { 8, 10, 8, 8 } }, // 3*pmuludq/3*shift/2*add
1327
1328 { ISD::FDIV, MVT::f32, { 23, 23, 1, 1 } }, // Pentium IV from http://www.agner.org/
1329 { ISD::FDIV, MVT::v4f32, { 39, 39, 1, 1 } }, // Pentium IV from http://www.agner.org/
1330 { ISD::FDIV, MVT::f64, { 38, 38, 1, 1 } }, // Pentium IV from http://www.agner.org/
1331 { ISD::FDIV, MVT::v2f64, { 69, 69, 1, 1 } }, // Pentium IV from http://www.agner.org/
1332
1333 { ISD::FNEG, MVT::f32, { 1, 1, 1, 1 } }, // Pentium IV from http://www.agner.org/
1334 { ISD::FNEG, MVT::f64, { 1, 1, 1, 1 } }, // Pentium IV from http://www.agner.org/
1335 { ISD::FNEG, MVT::v4f32, { 1, 1, 1, 1 } }, // Pentium IV from http://www.agner.org/
1336 { ISD::FNEG, MVT::v2f64, { 1, 1, 1, 1 } }, // Pentium IV from http://www.agner.org/
1337
1338 { ISD::FADD, MVT::f32, { 2, 3, 1, 1 } }, // Pentium IV from http://www.agner.org/
1339 { ISD::FADD, MVT::f64, { 2, 3, 1, 1 } }, // Pentium IV from http://www.agner.org/
1340 { ISD::FADD, MVT::v2f64, { 2, 3, 1, 1 } }, // Pentium IV from http://www.agner.org/
1341
1342 { ISD::FSUB, MVT::f32, { 2, 3, 1, 1 } }, // Pentium IV from http://www.agner.org/
1343 { ISD::FSUB, MVT::f64, { 2, 3, 1, 1 } }, // Pentium IV from http://www.agner.org/
1344 { ISD::FSUB, MVT::v2f64, { 2, 3, 1, 1 } }, // Pentium IV from http://www.agner.org/
1345
1346 { ISD::FMUL, MVT::f64, { 2, 5, 1, 1 } }, // Pentium IV from http://www.agner.org/
1347 { ISD::FMUL, MVT::v2f64, { 2, 5, 1, 1 } }, // Pentium IV from http://www.agner.org/
1348 };
1349
1350 if (ST->hasSSE2())
1351 if (const auto *Entry = CostTableLookup(SSE2CostTable, ISD, LT.second))
1352 if (auto KindCost = Entry->Cost[CostKind])
1353 return LT.first * *KindCost;
1354
1355 static const CostKindTblEntry SSE1CostTable[] = {
1356 { ISD::FDIV, MVT::f32, { 17, 18, 1, 1 } }, // Pentium III from http://www.agner.org/
1357 { ISD::FDIV, MVT::v4f32, { 34, 48, 1, 1 } }, // Pentium III from http://www.agner.org/
1358
1359 { ISD::FNEG, MVT::f32, { 2, 2, 1, 2 } }, // Pentium III from http://www.agner.org/
1360 { ISD::FNEG, MVT::v4f32, { 2, 2, 1, 2 } }, // Pentium III from http://www.agner.org/
1361
1362 { ISD::FADD, MVT::f32, { 1, 3, 1, 1 } }, // Pentium III from http://www.agner.org/
1363 { ISD::FADD, MVT::v4f32, { 2, 3, 1, 1 } }, // Pentium III from http://www.agner.org/
1364
1365 { ISD::FSUB, MVT::f32, { 1, 3, 1, 1 } }, // Pentium III from http://www.agner.org/
1366 { ISD::FSUB, MVT::v4f32, { 2, 3, 1, 1 } }, // Pentium III from http://www.agner.org/
1367
1368 { ISD::FMUL, MVT::f32, { 2, 5, 1, 1 } }, // Pentium III from http://www.agner.org/
1369 { ISD::FMUL, MVT::v4f32, { 2, 5, 1, 1 } }, // Pentium III from http://www.agner.org/
1370 };
1371
1372 if (ST->hasSSE1())
1373 if (const auto *Entry = CostTableLookup(SSE1CostTable, ISD, LT.second))
1374 if (auto KindCost = Entry->Cost[CostKind])
1375 return LT.first * *KindCost;
1376
1377 static const CostKindTblEntry X64CostTbl[] = { // 64-bit targets
1378 { ISD::ADD, MVT::i64, { 1 } }, // Core (Merom) from http://www.agner.org/
1379 { ISD::SUB, MVT::i64, { 1 } }, // Core (Merom) from http://www.agner.org/
1380 { ISD::MUL, MVT::i64, { 2, 6, 1, 2 } },
1381 };
1382
1383 if (ST->is64Bit())
1384 if (const auto *Entry = CostTableLookup(X64CostTbl, ISD, LT.second))
1385 if (auto KindCost = Entry->Cost[CostKind])
1386 return LT.first * *KindCost;
1387
1388 static const CostKindTblEntry X86CostTbl[] = { // 32 or 64-bit targets
1389 { ISD::ADD, MVT::i8, { 1 } }, // Pentium III from http://www.agner.org/
1390 { ISD::ADD, MVT::i16, { 1 } }, // Pentium III from http://www.agner.org/
1391 { ISD::ADD, MVT::i32, { 1 } }, // Pentium III from http://www.agner.org/
1392
1393 { ISD::SUB, MVT::i8, { 1 } }, // Pentium III from http://www.agner.org/
1394 { ISD::SUB, MVT::i16, { 1 } }, // Pentium III from http://www.agner.org/
1395 { ISD::SUB, MVT::i32, { 1 } }, // Pentium III from http://www.agner.org/
1396
1397 { ISD::MUL, MVT::i8, { 3, 4, 1, 1 } },
1398 { ISD::MUL, MVT::i16, { 2, 4, 1, 1 } },
1399 { ISD::MUL, MVT::i32, { 1, 4, 1, 1 } },
1400
1401 { ISD::FNEG, MVT::f64, { 2, 2, 1, 3 } }, // (x87)
1402 { ISD::FADD, MVT::f64, { 2, 3, 1, 1 } }, // (x87)
1403 { ISD::FSUB, MVT::f64, { 2, 3, 1, 1 } }, // (x87)
1404 { ISD::FMUL, MVT::f64, { 2, 5, 1, 1 } }, // (x87)
1405 { ISD::FDIV, MVT::f64, { 38, 38, 1, 1 } }, // (x87)
1406 };
1407
1408 if (const auto *Entry = CostTableLookup(X86CostTbl, ISD, LT.second))
1409 if (auto KindCost = Entry->Cost[CostKind])
1410 return LT.first * *KindCost;
1411
1412 // It is not a good idea to vectorize division. We have to scalarize it and
1413 // in the process we will often end up having to spilling regular
1414 // registers. The overhead of division is going to dominate most kernels
1415 // anyways so try hard to prevent vectorization of division - it is
1416 // generally a bad idea. Assume somewhat arbitrarily that we have to be able
1417 // to hide "20 cycles" for each lane.
1418 if (CostKind == TTI::TCK_RecipThroughput && LT.second.isVector() &&
1419 (ISD == ISD::SDIV || ISD == ISD::SREM || ISD == ISD::UDIV ||
1420 ISD == ISD::UREM)) {
1421 InstructionCost ScalarCost =
1422 getArithmeticInstrCost(Opcode, Ty->getScalarType(), CostKind,
1423 Op1Info.getNoProps(), Op2Info.getNoProps());
1424 return 20 * LT.first * LT.second.getVectorNumElements() * ScalarCost;
1425 }
1426
1427 // Handle some basic single instruction code size cases.
1428 if (CostKind == TTI::TCK_CodeSize) {
1429 switch (ISD) {
1430 case ISD::FADD:
1431 case ISD::FSUB:
1432 case ISD::FMUL:
1433 case ISD::FDIV:
1434 case ISD::FNEG:
1435 case ISD::AND:
1436 case ISD::OR:
1437 case ISD::XOR:
1438 return LT.first;
1439 break;
1440 }
1441 }
1442
1443 // Fallback to the default implementation.
1444 return BaseT::getArithmeticInstrCost(Opcode, Ty, CostKind, Op1Info, Op2Info,
1445 Args, CxtI);
1446}
1447
1448InstructionCost X86TTIImpl::getShuffleCost(TTI::ShuffleKind Kind,
1449 VectorType *BaseTp,
1450 ArrayRef<int> Mask,
1451 TTI::TargetCostKind CostKind,
1452 int Index, VectorType *SubTp,
1453 ArrayRef<const Value *> Args) {
1454 // 64-bit packed float vectors (v2f32) are widened to type v4f32.
1455 // 64-bit packed integer vectors (v2i32) are widened to type v4i32.
1456 std::pair<InstructionCost, MVT> LT = getTypeLegalizationCost(BaseTp);
1457
1458 Kind = improveShuffleKindFromMask(Kind, Mask);
1459
1460 // Treat Transpose as 2-op shuffles - there's no difference in lowering.
1461 if (Kind == TTI::SK_Transpose)
1462 Kind = TTI::SK_PermuteTwoSrc;
1463
1464 // For Broadcasts we are splatting the first element from the first input
1465 // register, so only need to reference that input and all the output
1466 // registers are the same.
1467 if (Kind == TTI::SK_Broadcast)
1468 LT.first = 1;
1469
1470 // Subvector extractions are free if they start at the beginning of a
1471 // vector and cheap if the subvectors are aligned.
1472 if (Kind == TTI::SK_ExtractSubvector && LT.second.isVector()) {
1473 int NumElts = LT.second.getVectorNumElements();
1474 if ((Index % NumElts) == 0)
1475 return 0;
1476 std::pair<InstructionCost, MVT> SubLT = getTypeLegalizationCost(SubTp);
1477 if (SubLT.second.isVector()) {
1478 int NumSubElts = SubLT.second.getVectorNumElements();
1479 if ((Index % NumSubElts) == 0 && (NumElts % NumSubElts) == 0)
1480 return SubLT.first;
1481 // Handle some cases for widening legalization. For now we only handle
1482 // cases where the original subvector was naturally aligned and evenly
1483 // fit in its legalized subvector type.
1484 // FIXME: Remove some of the alignment restrictions.
1485 // FIXME: We can use permq for 64-bit or larger extracts from 256-bit
1486 // vectors.
1487 int OrigSubElts = cast<FixedVectorType>(SubTp)->getNumElements();
1488 if (NumSubElts > OrigSubElts && (Index % OrigSubElts) == 0 &&
1489 (NumSubElts % OrigSubElts) == 0 &&
1490 LT.second.getVectorElementType() ==
1491 SubLT.second.getVectorElementType() &&
1492 LT.second.getVectorElementType().getSizeInBits() ==
1493 BaseTp->getElementType()->getPrimitiveSizeInBits()) {
1494 assert(NumElts >= NumSubElts && NumElts > OrigSubElts &&(static_cast <bool> (NumElts >= NumSubElts &&
NumElts > OrigSubElts && "Unexpected number of elements!"
) ? void (0) : __assert_fail ("NumElts >= NumSubElts && NumElts > OrigSubElts && \"Unexpected number of elements!\""
, "llvm/lib/Target/X86/X86TargetTransformInfo.cpp", 1495, __extension__
__PRETTY_FUNCTION__))
1495 "Unexpected number of elements!")(static_cast <bool> (NumElts >= NumSubElts &&
NumElts > OrigSubElts && "Unexpected number of elements!"
) ? void (0) : __assert_fail ("NumElts >= NumSubElts && NumElts > OrigSubElts && \"Unexpected number of elements!\""
, "llvm/lib/Target/X86/X86TargetTransformInfo.cpp", 1495, __extension__
__PRETTY_FUNCTION__));
1496 auto *VecTy = FixedVectorType::get(BaseTp->getElementType(),
1497 LT.second.getVectorNumElements());
1498 auto *SubTy = FixedVectorType::get(BaseTp->getElementType(),
1499 SubLT.second.getVectorNumElements());
1500 int ExtractIndex = alignDown((Index % NumElts), NumSubElts);
1501 InstructionCost ExtractCost =
1502 getShuffleCost(TTI::SK_ExtractSubvector, VecTy, std::nullopt,
1503 CostKind, ExtractIndex, SubTy);
1504
1505 // If the original size is 32-bits or more, we can use pshufd. Otherwise
1506 // if we have SSSE3 we can use pshufb.
1507 if (SubTp->getPrimitiveSizeInBits() >= 32 || ST->hasSSSE3())
1508 return ExtractCost + 1; // pshufd or pshufb
1509
1510 assert(SubTp->getPrimitiveSizeInBits() == 16 &&(static_cast <bool> (SubTp->getPrimitiveSizeInBits()
== 16 && "Unexpected vector size") ? void (0) : __assert_fail
("SubTp->getPrimitiveSizeInBits() == 16 && \"Unexpected vector size\""
, "llvm/lib/Target/X86/X86TargetTransformInfo.cpp", 1511, __extension__
__PRETTY_FUNCTION__))
1511 "Unexpected vector size")(static_cast <bool> (SubTp->getPrimitiveSizeInBits()
== 16 && "Unexpected vector size") ? void (0) : __assert_fail
("SubTp->getPrimitiveSizeInBits() == 16 && \"Unexpected vector size\""
, "llvm/lib/Target/X86/X86TargetTransformInfo.cpp", 1511, __extension__
__PRETTY_FUNCTION__));
1512
1513 return ExtractCost + 2; // worst case pshufhw + pshufd
1514 }
1515 }
1516 }
1517
1518 // Subvector insertions are cheap if the subvectors are aligned.
1519 // Note that in general, the insertion starting at the beginning of a vector
1520 // isn't free, because we need to preserve the rest of the wide vector.
1521 if (Kind == TTI::SK_InsertSubvector && LT.second.isVector()) {
1522 int NumElts = LT.second.getVectorNumElements();
1523 std::pair<InstructionCost, MVT> SubLT = getTypeLegalizationCost(SubTp);
1524 if (SubLT.second.isVector()) {
1525 int NumSubElts = SubLT.second.getVectorNumElements();
1526 if ((Index % NumSubElts) == 0 && (NumElts % NumSubElts) == 0)
1527 return SubLT.first;
1528 }
1529
1530 // If the insertion isn't aligned, treat it like a 2-op shuffle.
1531 Kind = TTI::SK_PermuteTwoSrc;
1532 }
1533
1534 // Handle some common (illegal) sub-vector types as they are often very cheap
1535 // to shuffle even on targets without PSHUFB.
1536 EVT VT = TLI->getValueType(DL, BaseTp);
1537 if (VT.isSimple() && VT.isVector() && VT.getSizeInBits() < 128 &&
1538 !ST->hasSSSE3()) {
1539 static const CostTblEntry SSE2SubVectorShuffleTbl[] = {
1540 {TTI::SK_Broadcast, MVT::v4i16, 1}, // pshuflw
1541 {TTI::SK_Broadcast, MVT::v2i16, 1}, // pshuflw
1542 {TTI::SK_Broadcast, MVT::v8i8, 2}, // punpck/pshuflw
1543 {TTI::SK_Broadcast, MVT::v4i8, 2}, // punpck/pshuflw
1544 {TTI::SK_Broadcast, MVT::v2i8, 1}, // punpck
1545
1546 {TTI::SK_Reverse, MVT::v4i16, 1}, // pshuflw
1547 {TTI::SK_Reverse, MVT::v2i16, 1}, // pshuflw
1548 {TTI::SK_Reverse, MVT::v4i8, 3}, // punpck/pshuflw/packus
1549 {TTI::SK_Reverse, MVT::v2i8, 1}, // punpck
1550
1551 {TTI::SK_Splice, MVT::v4i16, 2}, // punpck+psrldq
1552 {TTI::SK_Splice, MVT::v2i16, 2}, // punpck+psrldq
1553 {TTI::SK_Splice, MVT::v4i8, 2}, // punpck+psrldq
1554 {TTI::SK_Splice, MVT::v2i8, 2}, // punpck+psrldq
1555
1556 {TTI::SK_PermuteTwoSrc, MVT::v4i16, 2}, // punpck/pshuflw
1557 {TTI::SK_PermuteTwoSrc, MVT::v2i16, 2}, // punpck/pshuflw
1558 {TTI::SK_PermuteTwoSrc, MVT::v8i8, 7}, // punpck/pshuflw
1559 {TTI::SK_PermuteTwoSrc, MVT::v4i8, 4}, // punpck/pshuflw
1560 {TTI::SK_PermuteTwoSrc, MVT::v2i8, 2}, // punpck
1561
1562 {TTI::SK_PermuteSingleSrc, MVT::v4i16, 1}, // pshuflw
1563 {TTI::SK_PermuteSingleSrc, MVT::v2i16, 1}, // pshuflw
1564 {TTI::SK_PermuteSingleSrc, MVT::v8i8, 5}, // punpck/pshuflw
1565 {TTI::SK_PermuteSingleSrc, MVT::v4i8, 3}, // punpck/pshuflw
1566 {TTI::SK_PermuteSingleSrc, MVT::v2i8, 1}, // punpck
1567 };
1568
1569 if (ST->hasSSE2())
1570 if (const auto *Entry =
1571 CostTableLookup(SSE2SubVectorShuffleTbl, Kind, VT.getSimpleVT()))
1572 return Entry->Cost;
1573 }
1574
1575 // We are going to permute multiple sources and the result will be in multiple
1576 // destinations. Providing an accurate cost only for splits where the element
1577 // type remains the same.
1578 if (Kind == TTI::SK_PermuteSingleSrc && LT.first != 1) {
1579 MVT LegalVT = LT.second;
1580 if (LegalVT.isVector() &&
1581 LegalVT.getVectorElementType().getSizeInBits() ==
1582 BaseTp->getElementType()->getPrimitiveSizeInBits() &&
1583 LegalVT.getVectorNumElements() <
1584 cast<FixedVectorType>(BaseTp)->getNumElements()) {
1585
1586 unsigned VecTySize = DL.getTypeStoreSize(BaseTp);
1587 unsigned LegalVTSize = LegalVT.getStoreSize();
1588 // Number of source vectors after legalization:
1589 unsigned NumOfSrcs = (VecTySize + LegalVTSize - 1) / LegalVTSize;
1590 // Number of destination vectors after legalization:
1591 InstructionCost NumOfDests = LT.first;
1592
1593 auto *SingleOpTy = FixedVectorType::get(BaseTp->getElementType(),
1594 LegalVT.getVectorNumElements());
1595
1596 if (!Mask.empty() && NumOfDests.isValid()) {
1597 // Try to perform better estimation of the permutation.
1598 // 1. Split the source/destination vectors into real registers.
1599 // 2. Do the mask analysis to identify which real registers are
1600 // permuted. If more than 1 source registers are used for the
1601 // destination register building, the cost for this destination register
1602 // is (Number_of_source_register - 1) * Cost_PermuteTwoSrc. If only one
1603 // source register is used, build mask and calculate the cost as a cost
1604 // of PermuteSingleSrc.
1605 // Also, for the single register permute we try to identify if the
1606 // destination register is just a copy of the source register or the
1607 // copy of the previous destination register (the cost is
1608 // TTI::TCC_Basic). If the source register is just reused, the cost for
1609 // this operation is 0.
1610 unsigned E = *NumOfDests.getValue();
1611 unsigned NormalizedVF =
1612 LegalVT.getVectorNumElements() * std::max(NumOfSrcs, E);
1613 unsigned NumOfSrcRegs = NormalizedVF / LegalVT.getVectorNumElements();
1614 unsigned NumOfDestRegs = NormalizedVF / LegalVT.getVectorNumElements();
1615 SmallVector<int> NormalizedMask(NormalizedVF, PoisonMaskElem);
1616 copy(Mask, NormalizedMask.begin());
1617 unsigned PrevSrcReg = 0;
1618 ArrayRef<int> PrevRegMask;
1619 InstructionCost Cost = 0;
1620 processShuffleMasks(
1621 NormalizedMask, NumOfSrcRegs, NumOfDestRegs, NumOfDestRegs, []() {},
1622 [this, SingleOpTy, CostKind, &PrevSrcReg, &PrevRegMask,
1623 &Cost](ArrayRef<int> RegMask, unsigned SrcReg, unsigned DestReg) {
1624 if (!ShuffleVectorInst::isIdentityMask(RegMask)) {
1625 // Check if the previous register can be just copied to the next
1626 // one.
1627 if (PrevRegMask.empty() || PrevSrcReg != SrcReg ||
1628 PrevRegMask != RegMask)
1629 Cost += getShuffleCost(TTI::SK_PermuteSingleSrc, SingleOpTy,
1630 RegMask, CostKind, 0, nullptr);
1631 else
1632 // Just a copy of previous destination register.
1633 Cost += TTI::TCC_Basic;
1634 return;
1635 }
1636 if (SrcReg != DestReg &&
1637 any_of(RegMask, [](int I) { return I != PoisonMaskElem; })) {
1638 // Just a copy of the source register.
1639 Cost += TTI::TCC_Basic;
1640 }
1641 PrevSrcReg = SrcReg;
1642 PrevRegMask = RegMask;
1643 },
1644 [this, SingleOpTy, CostKind, &Cost](ArrayRef<int> RegMask,
1645 unsigned /*Unused*/,
1646 unsigned /*Unused*/) {
1647 Cost += getShuffleCost(TTI::SK_PermuteTwoSrc, SingleOpTy, RegMask,
1648 CostKind, 0, nullptr);
1649 });
1650 return Cost;
1651 }
1652
1653 InstructionCost NumOfShuffles = (NumOfSrcs - 1) * NumOfDests;
1654 return NumOfShuffles * getShuffleCost(TTI::SK_PermuteTwoSrc, SingleOpTy,
1655 std::nullopt, CostKind, 0, nullptr);
1656 }
1657
1658 return BaseT::getShuffleCost(Kind, BaseTp, Mask, CostKind, Index, SubTp);
1659 }
1660
1661 // For 2-input shuffles, we must account for splitting the 2 inputs into many.
1662 if (Kind == TTI::SK_PermuteTwoSrc && LT.first != 1) {
1663 // We assume that source and destination have the same vector type.
1664 InstructionCost NumOfDests = LT.first;
1665 InstructionCost NumOfShufflesPerDest = LT.first * 2 - 1;
1666 LT.first = NumOfDests * NumOfShufflesPerDest;
1667 }
1668
1669 static const CostTblEntry AVX512VBMIShuffleTbl[] = {
1670 {TTI::SK_Reverse, MVT::v64i8, 1}, // vpermb
1671 {TTI::SK_Reverse, MVT::v32i8, 1}, // vpermb
1672
1673 {TTI::SK_PermuteSingleSrc, MVT::v64i8, 1}, // vpermb
1674 {TTI::SK_PermuteSingleSrc, MVT::v32i8, 1}, // vpermb
1675
1676 {TTI::SK_PermuteTwoSrc, MVT::v64i8, 2}, // vpermt2b
1677 {TTI::SK_PermuteTwoSrc, MVT::v32i8, 2}, // vpermt2b
1678 {TTI::SK_PermuteTwoSrc, MVT::v16i8, 2} // vpermt2b
1679 };
1680
1681 if (ST->hasVBMI())
1682 if (const auto *Entry =
1683 CostTableLookup(AVX512VBMIShuffleTbl, Kind, LT.second))
1684 return LT.first * Entry->Cost;
1685
1686 static const CostTblEntry AVX512BWShuffleTbl[] = {
1687 {TTI::SK_Broadcast, MVT::v32i16, 1}, // vpbroadcastw
1688 {TTI::SK_Broadcast, MVT::v32f16, 1}, // vpbroadcastw
1689 {TTI::SK_Broadcast, MVT::v64i8, 1}, // vpbroadcastb
1690
1691 {TTI::SK_Reverse, MVT::v32i16, 2}, // vpermw
1692 {TTI::SK_Reverse, MVT::v32f16, 2}, // vpermw
1693 {TTI::SK_Reverse, MVT::v16i16, 2}, // vpermw
1694 {TTI::SK_Reverse, MVT::v64i8, 2}, // pshufb + vshufi64x2
1695
1696 {TTI::SK_PermuteSingleSrc, MVT::v32i16, 2}, // vpermw
1697 {TTI::SK_PermuteSingleSrc, MVT::v32f16, 2}, // vpermw
1698 {TTI::SK_PermuteSingleSrc, MVT::v16i16, 2}, // vpermw
1699 {TTI::SK_PermuteSingleSrc, MVT::v16f16, 2}, // vpermw
1700 {TTI::SK_PermuteSingleSrc, MVT::v64i8, 8}, // extend to v32i16
1701
1702 {TTI::SK_PermuteTwoSrc, MVT::v32i16, 2}, // vpermt2w
1703 {TTI::SK_PermuteTwoSrc, MVT::v32f16, 2}, // vpermt2w
1704 {TTI::SK_PermuteTwoSrc, MVT::v16i16, 2}, // vpermt2w
1705 {TTI::SK_PermuteTwoSrc, MVT::v8i16, 2}, // vpermt2w
1706 {TTI::SK_PermuteTwoSrc, MVT::v64i8, 19}, // 6 * v32i8 + 1
1707
1708 {TTI::SK_Select, MVT::v32i16, 1}, // vblendmw
1709 {TTI::SK_Select, MVT::v64i8, 1}, // vblendmb
1710
1711 {TTI::SK_Splice, MVT::v32i16, 2}, // vshufi64x2 + palignr
1712 {TTI::SK_Splice, MVT::v32f16, 2}, // vshufi64x2 + palignr
1713 {TTI::SK_Splice, MVT::v64i8, 2}, // vshufi64x2 + palignr
1714 };
1715
1716 if (ST->hasBWI())
1717 if (const auto *Entry =
1718 CostTableLookup(AVX512BWShuffleTbl, Kind, LT.second))
1719 return LT.first * Entry->Cost;
1720
1721 static const CostKindTblEntry AVX512ShuffleTbl[] = {
1722 {TTI::SK_Broadcast, MVT::v8f64, { 1, 1, 1, 1 } }, // vbroadcastsd
1723 {TTI::SK_Broadcast, MVT::v16f32, { 1, 1, 1, 1 } }, // vbroadcastss
1724 {TTI::SK_Broadcast, MVT::v8i64, { 1, 1, 1, 1 } }, // vpbroadcastq
1725 {TTI::SK_Broadcast, MVT::v16i32, { 1, 1, 1, 1 } }, // vpbroadcastd
1726 {TTI::SK_Broadcast, MVT::v32i16, { 1, 1, 1, 1 } }, // vpbroadcastw
1727 {TTI::SK_Broadcast, MVT::v32f16, { 1, 1, 1, 1 } }, // vpbroadcastw
1728 {TTI::SK_Broadcast, MVT::v64i8, { 1, 1, 1, 1 } }, // vpbroadcastb
1729
1730 {TTI::SK_Reverse, MVT::v8f64, { 1, 3, 1, 1 } }, // vpermpd
1731 {TTI::SK_Reverse, MVT::v16f32, { 1, 3, 1, 1 } }, // vpermps
1732 {TTI::SK_Reverse, MVT::v8i64, { 1, 3, 1, 1 } }, // vpermq
1733 {TTI::SK_Reverse, MVT::v16i32, { 1, 3, 1, 1 } }, // vpermd
1734 {TTI::SK_Reverse, MVT::v32i16, { 7, 7, 7, 7 } }, // per mca
1735 {TTI::SK_Reverse, MVT::v32f16, { 7, 7, 7, 7 } }, // per mca
1736 {TTI::SK_Reverse, MVT::v64i8, { 7, 7, 7, 7 } }, // per mca
1737
1738 {TTI::SK_Splice, MVT::v8f64, { 1, 1, 1, 1 } }, // vpalignd
1739 {TTI::SK_Splice, MVT::v4f64, { 1, 1, 1, 1 } }, // vpalignd
1740 {TTI::SK_Splice, MVT::v16f32, { 1, 1, 1, 1 } }, // vpalignd
1741 {TTI::SK_Splice, MVT::v8f32, { 1, 1, 1, 1 } }, // vpalignd
1742 {TTI::SK_Splice, MVT::v8i64, { 1, 1, 1, 1 } }, // vpalignd
1743 {TTI::SK_Splice, MVT::v4i64, { 1, 1, 1, 1 } }, // vpalignd
1744 {TTI::SK_Splice, MVT::v16i32, { 1, 1, 1, 1 } }, // vpalignd
1745 {TTI::SK_Splice, MVT::v8i32, { 1, 1, 1, 1 } }, // vpalignd
1746 {TTI::SK_Splice, MVT::v32i16, { 4, 4, 4, 4 } }, // split + palignr
1747 {TTI::SK_Splice, MVT::v32f16, { 4, 4, 4, 4 } }, // split + palignr
1748 {TTI::SK_Splice, MVT::v64i8, { 4, 4, 4, 4 } }, // split + palignr
1749
1750 {TTI::SK_PermuteSingleSrc, MVT::v8f64, { 1, 3, 1, 1 } }, // vpermpd
1751 {TTI::SK_PermuteSingleSrc, MVT::v4f64, { 1, 3, 1, 1 } }, // vpermpd
1752 {TTI::SK_PermuteSingleSrc, MVT::v2f64, { 1, 3, 1, 1 } }, // vpermpd
1753 {TTI::SK_PermuteSingleSrc, MVT::v16f32, { 1, 3, 1, 1 } }, // vpermps
1754 {TTI::SK_PermuteSingleSrc, MVT::v8f32, { 1, 3, 1, 1 } }, // vpermps
1755 {TTI::SK_PermuteSingleSrc, MVT::v4f32, { 1, 3, 1, 1 } }, // vpermps
1756 {TTI::SK_PermuteSingleSrc, MVT::v8i64, { 1, 3, 1, 1 } }, // vpermq
1757 {TTI::SK_PermuteSingleSrc, MVT::v4i64, { 1, 3, 1, 1 } }, // vpermq
1758 {TTI::SK_PermuteSingleSrc, MVT::v2i64, { 1, 3, 1, 1 } }, // vpermq
1759 {TTI::SK_PermuteSingleSrc, MVT::v16i32, { 1, 3, 1, 1 } }, // vpermd
1760 {TTI::SK_PermuteSingleSrc, MVT::v8i32, { 1, 3, 1, 1 } }, // vpermd
1761 {TTI::SK_PermuteSingleSrc, MVT::v4i32, { 1, 3, 1, 1 } }, // vpermd
1762 {TTI::SK_PermuteSingleSrc, MVT::v16i8, { 1, 3, 1, 1 } }, // pshufb
1763
1764 {TTI::SK_PermuteTwoSrc, MVT::v8f64, { 1, 3, 1, 1 } }, // vpermt2pd
1765 {TTI::SK_PermuteTwoSrc, MVT::v16f32, { 1, 3, 1, 1 } }, // vpermt2ps
1766 {TTI::SK_PermuteTwoSrc, MVT::v8i64, { 1, 3, 1, 1 } }, // vpermt2q
1767 {TTI::SK_PermuteTwoSrc, MVT::v16i32, { 1, 3, 1, 1 } }, // vpermt2d
1768 {TTI::SK_PermuteTwoSrc, MVT::v4f64, { 1, 3, 1, 1 } }, // vpermt2pd
1769 {TTI::SK_PermuteTwoSrc, MVT::v8f32, { 1, 3, 1, 1 } }, // vpermt2ps
1770 {TTI::SK_PermuteTwoSrc, MVT::v4i64, { 1, 3, 1, 1 } }, // vpermt2q
1771 {TTI::SK_PermuteTwoSrc, MVT::v8i32, { 1, 3, 1, 1 } }, // vpermt2d
1772 {TTI::SK_PermuteTwoSrc, MVT::v2f64, { 1, 3, 1, 1 } }, // vpermt2pd
1773 {TTI::SK_PermuteTwoSrc, MVT::v4f32, { 1, 3, 1, 1 } }, // vpermt2ps
1774 {TTI::SK_PermuteTwoSrc, MVT::v2i64, { 1, 3, 1, 1 } }, // vpermt2q
1775 {TTI::SK_PermuteTwoSrc, MVT::v4i32, { 1, 3, 1, 1 } }, // vpermt2d
1776
1777 // FIXME: This just applies the type legalization cost rules above
1778 // assuming these completely split.
1779 {TTI::SK_PermuteSingleSrc, MVT::v32i16, { 14, 14, 14, 14 } },
1780 {TTI::SK_PermuteSingleSrc, MVT::v32f16, { 14, 14, 14, 14 } },
1781 {TTI::SK_PermuteSingleSrc, MVT::v64i8, { 14, 14, 14, 14 } },
1782 {TTI::SK_PermuteTwoSrc, MVT::v32i16, { 42, 42, 42, 42 } },
1783 {TTI::SK_PermuteTwoSrc, MVT::v32f16, { 42, 42, 42, 42 } },
1784 {TTI::SK_PermuteTwoSrc, MVT::v64i8, { 42, 42, 42, 42 } },
1785
1786 {TTI::SK_Select, MVT::v32i16, { 1, 1, 1, 1 } }, // vpternlogq
1787 {TTI::SK_Select, MVT::v32f16, { 1, 1, 1, 1 } }, // vpternlogq
1788 {TTI::SK_Select, MVT::v64i8, { 1, 1, 1, 1 } }, // vpternlogq
1789 {TTI::SK_Select, MVT::v8f64, { 1, 1, 1, 1 } }, // vblendmpd
1790 {TTI::SK_Select, MVT::v16f32, { 1, 1, 1, 1 } }, // vblendmps
1791 {TTI::SK_Select, MVT::v8i64, { 1, 1, 1, 1 } }, // vblendmq
1792 {TTI::SK_Select, MVT::v16i32, { 1, 1, 1, 1 } }, // vblendmd
1793 };
1794
1795 if (ST->hasAVX512())
1796 if (const auto *Entry = CostTableLookup(AVX512ShuffleTbl, Kind, LT.second))
1797 if (auto KindCost = Entry->Cost[CostKind])
1798 return LT.first * *KindCost;
1799
1800 static const CostTblEntry AVX2ShuffleTbl[] = {
1801 {TTI::SK_Broadcast, MVT::v4f64, 1}, // vbroadcastpd
1802 {TTI::SK_Broadcast, MVT::v8f32, 1}, // vbroadcastps
1803 {TTI::SK_Broadcast, MVT::v4i64, 1}, // vpbroadcastq
1804 {TTI::SK_Broadcast, MVT::v8i32, 1}, // vpbroadcastd
1805 {TTI::SK_Broadcast, MVT::v16i16, 1}, // vpbroadcastw
1806 {TTI::SK_Broadcast, MVT::v16f16, 1}, // vpbroadcastw
1807 {TTI::SK_Broadcast, MVT::v32i8, 1}, // vpbroadcastb
1808
1809 {TTI::SK_Reverse, MVT::v4f64, 1}, // vpermpd
1810 {TTI::SK_Reverse, MVT::v8f32, 1}, // vpermps
1811 {TTI::SK_Reverse, MVT::v4i64, 1}, // vpermq
1812 {TTI::SK_Reverse, MVT::v8i32, 1}, // vpermd
1813 {TTI::SK_Reverse, MVT::v16i16, 2}, // vperm2i128 + pshufb
1814 {TTI::SK_Reverse, MVT::v16f16, 2}, // vperm2i128 + pshufb
1815 {TTI::SK_Reverse, MVT::v32i8, 2}, // vperm2i128 + pshufb
1816
1817 {TTI::SK_Select, MVT::v16i16, 1}, // vpblendvb
1818 {TTI::SK_Select, MVT::v16f16, 1}, // vpblendvb
1819 {TTI::SK_Select, MVT::v32i8, 1}, // vpblendvb
1820
1821 {TTI::SK_Splice, MVT::v8i32, 2}, // vperm2i128 + vpalignr
1822 {TTI::SK_Splice, MVT::v8f32, 2}, // vperm2i128 + vpalignr
1823 {TTI::SK_Splice, MVT::v16i16, 2}, // vperm2i128 + vpalignr
1824 {TTI::SK_Splice, MVT::v16f16, 2}, // vperm2i128 + vpalignr
1825 {TTI::SK_Splice, MVT::v32i8, 2}, // vperm2i128 + vpalignr
1826
1827 {TTI::SK_PermuteSingleSrc, MVT::v4f64, 1}, // vpermpd
1828 {TTI::SK_PermuteSingleSrc, MVT::v8f32, 1}, // vpermps
1829 {TTI::SK_PermuteSingleSrc, MVT::v4i64, 1}, // vpermq
1830 {TTI::SK_PermuteSingleSrc, MVT::v8i32, 1}, // vpermd
1831 {TTI::SK_PermuteSingleSrc, MVT::v16i16, 4}, // vperm2i128 + 2*vpshufb
1832 // + vpblendvb
1833 {TTI::SK_PermuteSingleSrc, MVT::v16f16, 4}, // vperm2i128 + 2*vpshufb
1834 // + vpblendvb
1835 {TTI::SK_PermuteSingleSrc, MVT::v32i8, 4}, // vperm2i128 + 2*vpshufb
1836 // + vpblendvb
1837
1838 {TTI::SK_PermuteTwoSrc, MVT::v4f64, 3}, // 2*vpermpd + vblendpd
1839 {TTI::SK_PermuteTwoSrc, MVT::v8f32, 3}, // 2*vpermps + vblendps
1840 {TTI::SK_PermuteTwoSrc, MVT::v4i64, 3}, // 2*vpermq + vpblendd
1841 {TTI::SK_PermuteTwoSrc, MVT::v8i32, 3}, // 2*vpermd + vpblendd
1842 {TTI::SK_PermuteTwoSrc, MVT::v16i16, 7}, // 2*vperm2i128 + 4*vpshufb
1843 // + vpblendvb
1844 {TTI::SK_PermuteTwoSrc, MVT::v16f16, 7}, // 2*vperm2i128 + 4*vpshufb
1845 // + vpblendvb
1846 {TTI::SK_PermuteTwoSrc, MVT::v32i8, 7}, // 2*vperm2i128 + 4*vpshufb
1847 // + vpblendvb
1848 };
1849
1850 if (ST->hasAVX2())
1851 if (const auto *Entry = CostTableLookup(AVX2ShuffleTbl, Kind, LT.second))
1852 return LT.first * Entry->Cost;
1853
1854 static const CostTblEntry XOPShuffleTbl[] = {
1855 {TTI::SK_PermuteSingleSrc, MVT::v4f64, 2}, // vperm2f128 + vpermil2pd
1856 {TTI::SK_PermuteSingleSrc, MVT::v8f32, 2}, // vperm2f128 + vpermil2ps
1857 {TTI::SK_PermuteSingleSrc, MVT::v4i64, 2}, // vperm2f128 + vpermil2pd
1858 {TTI::SK_PermuteSingleSrc, MVT::v8i32, 2}, // vperm2f128 + vpermil2ps
1859 {TTI::SK_PermuteSingleSrc, MVT::v16i16, 4}, // vextractf128 + 2*vpperm
1860 // + vinsertf128
1861 {TTI::SK_PermuteSingleSrc, MVT::v32i8, 4}, // vextractf128 + 2*vpperm
1862 // + vinsertf128
1863
1864 {TTI::SK_PermuteTwoSrc, MVT::v16i16, 9}, // 2*vextractf128 + 6*vpperm
1865 // + vinsertf128
1866 {TTI::SK_PermuteTwoSrc, MVT::v8i16, 1}, // vpperm
1867 {TTI::SK_PermuteTwoSrc, MVT::v32i8, 9}, // 2*vextractf128 + 6*vpperm
1868 // + vinsertf128
1869 {TTI::SK_PermuteTwoSrc, MVT::v16i8, 1}, // vpperm
1870 };
1871
1872 if (ST->hasXOP())
1873 if (const auto *Entry = CostTableLookup(XOPShuffleTbl, Kind, LT.second))
1874 return LT.first * Entry->Cost;
1875
1876 static const CostTblEntry AVX1ShuffleTbl[] = {
1877 {TTI::SK_Broadcast, MVT::v4f64, 2}, // vperm2f128 + vpermilpd
1878 {TTI::SK_Broadcast, MVT::v8f32, 2}, // vperm2f128 + vpermilps
1879 {TTI::SK_Broadcast, MVT::v4i64, 2}, // vperm2f128 + vpermilpd
1880 {TTI::SK_Broadcast, MVT::v8i32, 2}, // vperm2f128 + vpermilps
1881 {TTI::SK_Broadcast, MVT::v16i16, 3}, // vpshuflw + vpshufd + vinsertf128
1882 {TTI::SK_Broadcast, MVT::v16f16, 3}, // vpshuflw + vpshufd + vinsertf128
1883 {TTI::SK_Broadcast, MVT::v32i8, 2}, // vpshufb + vinsertf128
1884
1885 {TTI::SK_Reverse, MVT::v4f64, 2}, // vperm2f128 + vpermilpd
1886 {TTI::SK_Reverse, MVT::v8f32, 2}, // vperm2f128 + vpermilps
1887 {TTI::SK_Reverse, MVT::v4i64, 2}, // vperm2f128 + vpermilpd
1888 {TTI::SK_Reverse, MVT::v8i32, 2}, // vperm2f128 + vpermilps
1889 {TTI::SK_Reverse, MVT::v16i16, 4}, // vextractf128 + 2*pshufb
1890 // + vinsertf128
1891 {TTI::SK_Reverse, MVT::v16f16, 4}, // vextractf128 + 2*pshufb
1892 // + vinsertf128
1893 {TTI::SK_Reverse, MVT::v32i8, 4}, // vextractf128 + 2*pshufb
1894 // + vinsertf128
1895
1896 {TTI::SK_Select, MVT::v4i64, 1}, // vblendpd
1897 {TTI::SK_Select, MVT::v4f64, 1}, // vblendpd
1898 {TTI::SK_Select, MVT::v8i32, 1}, // vblendps
1899 {TTI::SK_Select, MVT::v8f32, 1}, // vblendps
1900 {TTI::SK_Select, MVT::v16i16, 3}, // vpand + vpandn + vpor
1901 {TTI::SK_Select, MVT::v16f16, 3}, // vpand + vpandn + vpor
1902 {TTI::SK_Select, MVT::v32i8, 3}, // vpand + vpandn + vpor
1903
1904 {TTI::SK_Splice, MVT::v4i64, 2}, // vperm2f128 + shufpd
1905 {TTI::SK_Splice, MVT::v4f64, 2}, // vperm2f128 + shufpd
1906 {TTI::SK_Splice, MVT::v8i32, 4}, // 2*vperm2f128 + 2*vshufps
1907 {TTI::SK_Splice, MVT::v8f32, 4}, // 2*vperm2f128 + 2*vshufps
1908 {TTI::SK_Splice, MVT::v16i16, 5}, // 2*vperm2f128 + 2*vpalignr + vinsertf128
1909 {TTI::SK_Splice, MVT::v16f16, 5}, // 2*vperm2f128 + 2*vpalignr + vinsertf128
1910 {TTI::SK_Splice, MVT::v32i8, 5}, // 2*vperm2f128 + 2*vpalignr + vinsertf128
1911
1912 {TTI::SK_PermuteSingleSrc, MVT::v4f64, 2}, // vperm2f128 + vshufpd
1913 {TTI::SK_PermuteSingleSrc, MVT::v4i64, 2}, // vperm2f128 + vshufpd
1914 {TTI::SK_PermuteSingleSrc, MVT::v8f32, 4}, // 2*vperm2f128 + 2*vshufps
1915 {TTI::SK_PermuteSingleSrc, MVT::v8i32, 4}, // 2*vperm2f128 + 2*vshufps
1916 {TTI::SK_PermuteSingleSrc, MVT::v16i16, 8}, // vextractf128 + 4*pshufb
1917 // + 2*por + vinsertf128
1918 {TTI::SK_PermuteSingleSrc, MVT::v16f16, 8}, // vextractf128 + 4*pshufb
1919 // + 2*por + vinsertf128
1920 {TTI::SK_PermuteSingleSrc, MVT::v32i8, 8}, // vextractf128 + 4*pshufb
1921 // + 2*por + vinsertf128
1922
1923 {TTI::SK_PermuteTwoSrc, MVT::v4f64, 3}, // 2*vperm2f128 + vshufpd
1924 {TTI::SK_PermuteTwoSrc, MVT::v4i64, 3}, // 2*vperm2f128 + vshufpd
1925 {TTI::SK_PermuteTwoSrc, MVT::v8f32, 4}, // 2*vperm2f128 + 2*vshufps
1926 {TTI::SK_PermuteTwoSrc, MVT::v8i32, 4}, // 2*vperm2f128 + 2*vshufps
1927 {TTI::SK_PermuteTwoSrc, MVT::v16i16, 15}, // 2*vextractf128 + 8*pshufb
1928 // + 4*por + vinsertf128
1929 {TTI::SK_PermuteTwoSrc, MVT::v16f16, 15}, // 2*vextractf128 + 8*pshufb
1930 // + 4*por + vinsertf128
1931 {TTI::SK_PermuteTwoSrc, MVT::v32i8, 15}, // 2*vextractf128 + 8*pshufb
1932 // + 4*por + vinsertf128
1933 };
1934
1935 if (ST->hasAVX())
1936 if (const auto *Entry = CostTableLookup(AVX1ShuffleTbl, Kind, LT.second))
1937 return LT.first * Entry->Cost;
1938
1939 static const CostTblEntry SSE41ShuffleTbl[] = {
1940 {TTI::SK_Select, MVT::v2i64, 1}, // pblendw
1941 {TTI::SK_Select, MVT::v2f64, 1}, // movsd
1942 {TTI::SK_Select, MVT::v4i32, 1}, // pblendw
1943 {TTI::SK_Select, MVT::v4f32, 1}, // blendps
1944 {TTI::SK_Select, MVT::v8i16, 1}, // pblendw
1945 {TTI::SK_Select, MVT::v8f16, 1}, // pblendw
1946 {TTI::SK_Select, MVT::v16i8, 1} // pblendvb
1947 };
1948
1949 if (ST->hasSSE41())
1950 if (const auto *Entry = CostTableLookup(SSE41ShuffleTbl, Kind, LT.second))
1951 return LT.first * Entry->Cost;
1952
1953 static const CostTblEntry SSSE3ShuffleTbl[] = {
1954 {TTI::SK_Broadcast, MVT::v8i16, 1}, // pshufb
1955 {TTI::SK_Broadcast, MVT::v8f16, 1}, // pshufb
1956 {TTI::SK_Broadcast, MVT::v16i8, 1}, // pshufb
1957
1958 {TTI::SK_Reverse, MVT::v8i16, 1}, // pshufb
1959 {TTI::SK_Reverse, MVT::v8f16, 1}, // pshufb
1960 {TTI::SK_Reverse, MVT::v16i8, 1}, // pshufb
1961
1962 {TTI::SK_Select, MVT::v8i16, 3}, // 2*pshufb + por
1963 {TTI::SK_Select, MVT::v8f16, 3}, // 2*pshufb + por
1964 {TTI::SK_Select, MVT::v16i8, 3}, // 2*pshufb + por
1965
1966 {TTI::SK_Splice, MVT::v4i32, 1}, // palignr
1967 {TTI::SK_Splice, MVT::v4f32, 1}, // palignr
1968 {TTI::SK_Splice, MVT::v8i16, 1}, // palignr
1969 {TTI::SK_Splice, MVT::v8f16, 1}, // palignr
1970 {TTI::SK_Splice, MVT::v16i8, 1}, // palignr
1971
1972 {TTI::SK_PermuteSingleSrc, MVT::v8i16, 1}, // pshufb
1973 {TTI::SK_PermuteSingleSrc, MVT::v8f16, 1}, // pshufb
1974 {TTI::SK_PermuteSingleSrc, MVT::v16i8, 1}, // pshufb
1975
1976 {TTI::SK_PermuteTwoSrc, MVT::v8i16, 3}, // 2*pshufb + por
1977 {TTI::SK_PermuteTwoSrc, MVT::v8f16, 3}, // 2*pshufb + por
1978 {TTI::SK_PermuteTwoSrc, MVT::v16i8, 3}, // 2*pshufb + por
1979 };
1980
1981 if (ST->hasSSSE3())
1982 if (const auto *Entry = CostTableLookup(SSSE3ShuffleTbl, Kind, LT.second))
1983 return LT.first * Entry->Cost;
1984
1985 static const CostTblEntry SSE2ShuffleTbl[] = {
1986 {TTI::SK_Broadcast, MVT::v2f64, 1}, // shufpd
1987 {TTI::SK_Broadcast, MVT::v2i64, 1}, // pshufd
1988 {TTI::SK_Broadcast, MVT::v4i32, 1}, // pshufd
1989 {TTI::SK_Broadcast, MVT::v8i16, 2}, // pshuflw + pshufd
1990 {TTI::SK_Broadcast, MVT::v8f16, 2}, // pshuflw + pshufd
1991 {TTI::SK_Broadcast, MVT::v16i8, 3}, // unpck + pshuflw + pshufd
1992
1993 {TTI::SK_Reverse, MVT::v2f64, 1}, // shufpd
1994 {TTI::SK_Reverse, MVT::v2i64, 1}, // pshufd
1995 {TTI::SK_Reverse, MVT::v4i32, 1}, // pshufd
1996 {TTI::SK_Reverse, MVT::v8i16, 3}, // pshuflw + pshufhw + pshufd
1997 {TTI::SK_Reverse, MVT::v8f16, 3}, // pshuflw + pshufhw + pshufd
1998 {TTI::SK_Reverse, MVT::v16i8, 9}, // 2*pshuflw + 2*pshufhw
1999 // + 2*pshufd + 2*unpck + packus
2000
2001 {TTI::SK_Select, MVT::v2i64, 1}, // movsd
2002 {TTI::SK_Select, MVT::v2f64, 1}, // movsd
2003 {TTI::SK_Select, MVT::v4i32, 2}, // 2*shufps
2004 {TTI::SK_Select, MVT::v8i16, 3}, // pand + pandn + por
2005 {TTI::SK_Select, MVT::v8f16, 3}, // pand + pandn + por
2006 {TTI::SK_Select, MVT::v16i8, 3}, // pand + pandn + por
2007
2008 {TTI::SK_Splice, MVT::v2i64, 1}, // shufpd
2009 {TTI::SK_Splice, MVT::v2f64, 1}, // shufpd
2010 {TTI::SK_Splice, MVT::v4i32, 2}, // 2*{unpck,movsd,pshufd}
2011 {TTI::SK_Splice, MVT::v8i16, 3}, // psrldq + psrlldq + por
2012 {TTI::SK_Splice, MVT::v8f16, 3}, // psrldq + psrlldq + por
2013 {TTI::SK_Splice, MVT::v16i8, 3}, // psrldq + psrlldq + por
2014
2015 {TTI::SK_PermuteSingleSrc, MVT::v2f64, 1}, // shufpd
2016 {TTI::SK_PermuteSingleSrc, MVT::v2i64, 1}, // pshufd
2017 {TTI::SK_PermuteSingleSrc, MVT::v4i32, 1}, // pshufd
2018 {TTI::SK_PermuteSingleSrc, MVT::v8i16, 5}, // 2*pshuflw + 2*pshufhw
2019 // + pshufd/unpck
2020 {TTI::SK_PermuteSingleSrc, MVT::v8f16, 5}, // 2*pshuflw + 2*pshufhw
2021 // + pshufd/unpck
2022 { TTI::SK_PermuteSingleSrc, MVT::v16i8, 10 }, // 2*pshuflw + 2*pshufhw
2023 // + 2*pshufd + 2*unpck + 2*packus
2024
2025 { TTI::SK_PermuteTwoSrc, MVT::v2f64, 1 }, // shufpd
2026 { TTI::SK_PermuteTwoSrc, MVT::v2i64, 1 }, // shufpd
2027 { TTI::SK_PermuteTwoSrc, MVT::v4i32, 2 }, // 2*{unpck,movsd,pshufd}
2028 { TTI::SK_PermuteTwoSrc, MVT::v8i16, 8 }, // blend+permute
2029 { TTI::SK_PermuteTwoSrc, MVT::v8f16, 8 }, // blend+permute
2030 { TTI::SK_PermuteTwoSrc, MVT::v16i8, 13 }, // blend+permute
2031 };
2032
2033 static const CostTblEntry SSE3BroadcastLoadTbl[] = {
2034 {TTI::SK_Broadcast, MVT::v2f64, 0}, // broadcast handled by movddup
2035 };
2036
2037 if (ST->hasSSE2()) {
2038 bool IsLoad =
2039 llvm::any_of(Args, [](const auto &V) { return isa<LoadInst>(V); });
2040 if (ST->hasSSE3() && IsLoad)
2041 if (const auto *Entry =
2042 CostTableLookup(SSE3BroadcastLoadTbl, Kind, LT.second)) {
2043 assert(isLegalBroadcastLoad(BaseTp->getElementType(),(static_cast <bool> (isLegalBroadcastLoad(BaseTp->getElementType
(), LT.second.getVectorElementCount()) && "Table entry missing from isLegalBroadcastLoad()"
) ? void (0) : __assert_fail ("isLegalBroadcastLoad(BaseTp->getElementType(), LT.second.getVectorElementCount()) && \"Table entry missing from isLegalBroadcastLoad()\""
, "llvm/lib/Target/X86/X86TargetTransformInfo.cpp", 2045, __extension__
__PRETTY_FUNCTION__))
2044 LT.second.getVectorElementCount()) &&(static_cast <bool> (isLegalBroadcastLoad(BaseTp->getElementType
(), LT.second.getVectorElementCount()) && "Table entry missing from isLegalBroadcastLoad()"
) ? void (0) : __assert_fail ("isLegalBroadcastLoad(BaseTp->getElementType(), LT.second.getVectorElementCount()) && \"Table entry missing from isLegalBroadcastLoad()\""
, "llvm/lib/Target/X86/X86TargetTransformInfo.cpp", 2045, __extension__
__PRETTY_FUNCTION__))
2045 "Table entry missing from isLegalBroadcastLoad()")(static_cast <bool> (isLegalBroadcastLoad(BaseTp->getElementType
(), LT.second.getVectorElementCount()) && "Table entry missing from isLegalBroadcastLoad()"
) ? void (0) : __assert_fail ("isLegalBroadcastLoad(BaseTp->getElementType(), LT.second.getVectorElementCount()) && \"Table entry missing from isLegalBroadcastLoad()\""
, "llvm/lib/Target/X86/X86TargetTransformInfo.cpp", 2045, __extension__
__PRETTY_FUNCTION__));
2046 return LT.first * Entry->Cost;
2047 }
2048
2049 if (const auto *Entry = CostTableLookup(SSE2ShuffleTbl, Kind, LT.second))
2050 return LT.first * Entry->Cost;
2051 }
2052
2053 static const CostTblEntry SSE1ShuffleTbl[] = {
2054 { TTI::SK_Broadcast, MVT::v4f32, 1 }, // shufps
2055 { TTI::SK_Reverse, MVT::v4f32, 1 }, // shufps
2056 { TTI::SK_Select, MVT::v4f32, 2 }, // 2*shufps
2057 { TTI::SK_Splice, MVT::v4f32, 2 }, // 2*shufps
2058 { TTI::SK_PermuteSingleSrc, MVT::v4f32, 1 }, // shufps
2059 { TTI::SK_PermuteTwoSrc, MVT::v4f32, 2 }, // 2*shufps
2060 };
2061
2062 if (ST->hasSSE1())
2063 if (const auto *Entry = CostTableLookup(SSE1ShuffleTbl, Kind, LT.second))
2064 return LT.first * Entry->Cost;
2065
2066 return BaseT::getShuffleCost(Kind, BaseTp, Mask, CostKind, Index, SubTp);
2067}
2068
2069InstructionCost X86TTIImpl::getCastInstrCost(unsigned Opcode, Type *Dst,
2070 Type *Src,
2071 TTI::CastContextHint CCH,
2072 TTI::TargetCostKind CostKind,
2073 const Instruction *I) {
2074 int ISD = TLI->InstructionOpcodeToISD(Opcode);
2075 assert(ISD && "Invalid opcode")(static_cast <bool> (ISD && "Invalid opcode") ?
void (0) : __assert_fail ("ISD && \"Invalid opcode\""
, "llvm/lib/Target/X86/X86TargetTransformInfo.cpp", 2075, __extension__
__PRETTY_FUNCTION__));
2076
2077 // TODO: Allow non-throughput costs that aren't binary.
2078 auto AdjustCost = [&CostKind](InstructionCost Cost) -> InstructionCost {
2079 if (CostKind != TTI::TCK_RecipThroughput)
2080 return Cost == 0 ? 0 : 1;
2081 return Cost;
2082 };
2083
2084 // The cost tables include both specific, custom (non-legal) src/dst type
2085 // conversions and generic, legalized types. We test for customs first, before
2086 // falling back to legalization.
2087 // FIXME: Need a better design of the cost table to handle non-simple types of
2088 // potential massive combinations (elem_num x src_type x dst_type).
2089 static const TypeConversionCostTblEntry AVX512BWConversionTbl[] {
2090 { ISD::SIGN_EXTEND, MVT::v32i16, MVT::v32i8, 1 },
2091 { ISD::ZERO_EXTEND, MVT::v32i16, MVT::v32i8, 1 },
2092
2093 // Mask sign extend has an instruction.
2094 { ISD::SIGN_EXTEND, MVT::v2i8, MVT::v2i1, 1 },
2095 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v2i1, 1 },
2096 { ISD::SIGN_EXTEND, MVT::v2i16, MVT::v2i1, 1 },
2097 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v2i1, 1 },
2098 { ISD::SIGN_EXTEND, MVT::v4i8, MVT::v4i1, 1 },
2099 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v4i1, 1 },
2100 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i1, 1 },
2101 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v4i1, 1 },
2102 { ISD::SIGN_EXTEND, MVT::v8i8, MVT::v8i1, 1 },
2103 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v8i1, 1 },
2104 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i1, 1 },
2105 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v16i1, 1 },
2106 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 1 },
2107 { ISD::SIGN_EXTEND, MVT::v32i8, MVT::v32i1, 1 },
2108 { ISD::SIGN_EXTEND, MVT::v32i16, MVT::v32i1, 1 },
2109 { ISD::SIGN_EXTEND, MVT::v64i8, MVT::v64i1, 1 },
2110 { ISD::SIGN_EXTEND, MVT::v32i16, MVT::v64i1, 1 },
2111
2112 // Mask zero extend is a sext + shift.
2113 { ISD::ZERO_EXTEND, MVT::v2i8, MVT::v2i1, 2 },
2114 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v2i1, 2 },
2115 { ISD::ZERO_EXTEND, MVT::v2i16, MVT::v2i1, 2 },
2116 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v2i1, 2 },
2117 { ISD::ZERO_EXTEND, MVT::v4i8, MVT::v4i1, 2 },
2118 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v4i1, 2 },
2119 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i1, 2 },
2120 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v4i1, 2 },
2121 { ISD::ZERO_EXTEND, MVT::v8i8, MVT::v8i1, 2 },
2122 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v8i1, 2 },
2123 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i1, 2 },
2124 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v16i1, 2 },
2125 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 2 },
2126 { ISD::ZERO_EXTEND, MVT::v32i8, MVT::v32i1, 2 },
2127 { ISD::ZERO_EXTEND, MVT::v32i16, MVT::v32i1, 2 },
2128 { ISD::ZERO_EXTEND, MVT::v64i8, MVT::v64i1, 2 },
2129 { ISD::ZERO_EXTEND, MVT::v32i16, MVT::v64i1, 2 },
2130
2131 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i8, 2 },
2132 { ISD::TRUNCATE, MVT::v2i1, MVT::v16i8, 2 },
2133 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i16, 2 },
2134 { ISD::TRUNCATE, MVT::v2i1, MVT::v8i16, 2 },
2135 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i8, 2 },
2136 { ISD::TRUNCATE, MVT::v4i1, MVT::v16i8, 2 },
2137 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i16, 2 },
2138 { ISD::TRUNCATE, MVT::v4i1, MVT::v8i16, 2 },
2139 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i8, 2 },
2140 { ISD::TRUNCATE, MVT::v8i1, MVT::v16i8, 2 },
2141 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i16, 2 },
2142 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i8, 2 },
2143 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i16, 2 },
2144 { ISD::TRUNCATE, MVT::v32i1, MVT::v32i8, 2 },
2145 { ISD::TRUNCATE, MVT::v32i1, MVT::v32i16, 2 },
2146 { ISD::TRUNCATE, MVT::v64i1, MVT::v64i8, 2 },
2147 { ISD::TRUNCATE, MVT::v64i1, MVT::v32i16, 2 },
2148
2149 { ISD::TRUNCATE, MVT::v32i8, MVT::v32i16, 2 },
2150 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 2 }, // widen to zmm
2151 { ISD::TRUNCATE, MVT::v2i8, MVT::v2i16, 2 }, // vpmovwb
2152 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i16, 2 }, // vpmovwb
2153 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i16, 2 }, // vpmovwb
2154 };
2155
2156 static const TypeConversionCostTblEntry AVX512DQConversionTbl[] = {
2157 // Mask sign extend has an instruction.
2158 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v2i1, 1 },
2159 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v2i1, 1 },
2160 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i1, 1 },
2161 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 1 },
2162 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 1 },
2163 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v16i1, 1 },
2164 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i1, 1 },
2165 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i1, 1 },
2166
2167 // Mask zero extend is a sext + shift.
2168 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v2i1, 2 },
2169 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v2i1, 2 },
2170 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i1, 2 },
2171 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 2 },
2172 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 2 },
2173 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v16i1, 2 },
2174 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i1, 2 },
2175 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i1, 2 },
2176
2177 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i64, 2 },
2178 { ISD::TRUNCATE, MVT::v2i1, MVT::v4i32, 2 },
2179 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i32, 2 },
2180 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i64, 2 },
2181 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i32, 2 },
2182 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i64, 2 },
2183 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i32, 2 },
2184 { ISD::TRUNCATE, MVT::v16i1, MVT::v8i64, 2 },
2185
2186 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i64, 1 },
2187 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i64, 1 },
2188
2189 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i64, 1 },
2190 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i64, 1 },
2191
2192 { ISD::FP_TO_SINT, MVT::v8i64, MVT::v8f32, 1 },
2193 { ISD::FP_TO_SINT, MVT::v8i64, MVT::v8f64, 1 },
2194
2195 { ISD::FP_TO_UINT, MVT::v8i64, MVT::v8f32, 1 },
2196 { ISD::FP_TO_UINT, MVT::v8i64, MVT::v8f64, 1 },
2197 };
2198
2199 // TODO: For AVX512DQ + AVX512VL, we also have cheap casts for 128-bit and
2200 // 256-bit wide vectors.
2201
2202 static const TypeConversionCostTblEntry AVX512FConversionTbl[] = {
2203 { ISD::FP_EXTEND, MVT::v8f64, MVT::v8f32, 1 },
2204 { ISD::FP_EXTEND, MVT::v8f64, MVT::v16f32, 3 },
2205 { ISD::FP_ROUND, MVT::v8f32, MVT::v8f64, 1 },
2206
2207 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i8, 3 }, // sext+vpslld+vptestmd
2208 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i8, 3 }, // sext+vpslld+vptestmd
2209 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i8, 3 }, // sext+vpslld+vptestmd
2210 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i8, 3 }, // sext+vpslld+vptestmd
2211 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i16, 3 }, // sext+vpsllq+vptestmq
2212 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i16, 3 }, // sext+vpsllq+vptestmq
2213 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i16, 3 }, // sext+vpsllq+vptestmq
2214 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i16, 3 }, // sext+vpslld+vptestmd
2215 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i32, 2 }, // zmm vpslld+vptestmd
2216 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i32, 2 }, // zmm vpslld+vptestmd
2217 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i32, 2 }, // zmm vpslld+vptestmd
2218 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i32, 2 }, // vpslld+vptestmd
2219 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i64, 2 }, // zmm vpsllq+vptestmq
2220 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i64, 2 }, // zmm vpsllq+vptestmq
2221 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i64, 2 }, // vpsllq+vptestmq
2222 { ISD::TRUNCATE, MVT::v2i8, MVT::v2i32, 2 }, // vpmovdb
2223 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i32, 2 }, // vpmovdb
2224 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 2 }, // vpmovdb
2225 { ISD::TRUNCATE, MVT::v32i8, MVT::v16i32, 2 }, // vpmovdb
2226 { ISD::TRUNCATE, MVT::v64i8, MVT::v16i32, 2 }, // vpmovdb
2227 { ISD::TRUNCATE, MVT::v16i16, MVT::v16i32, 2 }, // vpmovdw
2228 { ISD::TRUNCATE, MVT::v32i16, MVT::v16i32, 2 }, // vpmovdw
2229 { ISD::TRUNCATE, MVT::v2i8, MVT::v2i64, 2 }, // vpmovqb
2230 { ISD::TRUNCATE, MVT::v2i16, MVT::v2i64, 1 }, // vpshufb
2231 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i64, 2 }, // vpmovqb
2232 { ISD::TRUNCATE, MVT::v16i8, MVT::v8i64, 2 }, // vpmovqb
2233 { ISD::TRUNCATE, MVT::v32i8, MVT::v8i64, 2 }, // vpmovqb
2234 { ISD::TRUNCATE, MVT::v64i8, MVT::v8i64, 2 }, // vpmovqb
2235 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i64, 2 }, // vpmovqw
2236 { ISD::TRUNCATE, MVT::v16i16, MVT::v8i64, 2 }, // vpmovqw
2237 { ISD::TRUNCATE, MVT::v32i16, MVT::v8i64, 2 }, // vpmovqw
2238 { ISD::TRUNCATE, MVT::v8i32, MVT::v8i64, 1 }, // vpmovqd
2239 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 1 }, // zmm vpmovqd
2240 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i64, 5 },// 2*vpmovqd+concat+vpmovdb
2241
2242 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 3 }, // extend to v16i32
2243 { ISD::TRUNCATE, MVT::v32i8, MVT::v32i16, 8 },
2244 { ISD::TRUNCATE, MVT::v64i8, MVT::v32i16, 8 },
2245
2246 // Sign extend is zmm vpternlogd+vptruncdb.
2247 // Zero extend is zmm broadcast load+vptruncdw.
2248 { ISD::SIGN_EXTEND, MVT::v2i8, MVT::v2i1, 3 },
2249 { ISD::ZERO_EXTEND, MVT::v2i8, MVT::v2i1, 4 },
2250 { ISD::SIGN_EXTEND, MVT::v4i8, MVT::v4i1, 3 },
2251 { ISD::ZERO_EXTEND, MVT::v4i8, MVT::v4i1, 4 },
2252 { ISD::SIGN_EXTEND, MVT::v8i8, MVT::v8i1, 3 },
2253 { ISD::ZERO_EXTEND, MVT::v8i8, MVT::v8i1, 4 },
2254 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v16i1, 3 },
2255 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v16i1, 4 },
2256
2257 // Sign extend is zmm vpternlogd+vptruncdw.
2258 // Zero extend is zmm vpternlogd+vptruncdw+vpsrlw.
2259 { ISD::SIGN_EXTEND, MVT::v2i16, MVT::v2i1, 3 },
2260 { ISD::ZERO_EXTEND, MVT::v2i16, MVT::v2i1, 4 },
2261 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i1, 3 },
2262 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i1, 4 },
2263 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i1, 3 },
2264 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i1, 4 },
2265 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 3 },
2266 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 4 },
2267
2268 { ISD::SIGN_EXTEND, MVT::v2i32, MVT::v2i1, 1 }, // zmm vpternlogd
2269 { ISD::ZERO_EXTEND, MVT::v2i32, MVT::v2i1, 2 }, // zmm vpternlogd+psrld
2270 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i1, 1 }, // zmm vpternlogd
2271 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i1, 2 }, // zmm vpternlogd+psrld
2272 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 1 }, // zmm vpternlogd
2273 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 2 }, // zmm vpternlogd+psrld
2274 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v2i1, 1 }, // zmm vpternlogq
2275 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v2i1, 2 }, // zmm vpternlogq+psrlq
2276 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 1 }, // zmm vpternlogq
2277 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 2 }, // zmm vpternlogq+psrlq
2278
2279 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i1, 1 }, // vpternlogd
2280 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i1, 2 }, // vpternlogd+psrld
2281 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i1, 1 }, // vpternlogq
2282 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i1, 2 }, // vpternlogq+psrlq
2283
2284 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 1 },
2285 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 1 },
2286 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i16, 1 },
2287 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i16, 1 },
2288 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i8, 1 },
2289 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i8, 1 },
2290 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i16, 1 },
2291 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i16, 1 },
2292 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i32, 1 },
2293 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i32, 1 },
2294
2295 { ISD::SIGN_EXTEND, MVT::v32i16, MVT::v32i8, 3 }, // FIXME: May not be right
2296 { ISD::ZERO_EXTEND, MVT::v32i16, MVT::v32i8, 3 }, // FIXME: May not be right
2297
2298 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i1, 4 },
2299 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i1, 3 },
2300 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v16i8, 2 },
2301 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i8, 1 },
2302 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i16, 2 },
2303 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i16, 1 },
2304 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i32, 1 },
2305 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i32, 1 },
2306
2307 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i1, 4 },
2308 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i1, 3 },
2309 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v16i8, 2 },
2310 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i8, 1 },
2311 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i16, 2 },
2312 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i16, 1 },
2313 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i32, 1 },
2314 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i32, 1 },
2315 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i64, 26 },
2316 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i64, 5 },
2317
2318 { ISD::FP_TO_SINT, MVT::v16i8, MVT::v16f32, 2 },
2319 { ISD::FP_TO_SINT, MVT::v16i8, MVT::v16f64, 7 },
2320 { ISD::FP_TO_SINT, MVT::v32i8, MVT::v32f64,15 },
2321 { ISD::FP_TO_SINT, MVT::v64i8, MVT::v64f32,11 },
2322 { ISD::FP_TO_SINT, MVT::v64i8, MVT::v64f64,31 },
2323 { ISD::FP_TO_SINT, MVT::v8i16, MVT::v8f64, 3 },
2324 { ISD::FP_TO_SINT, MVT::v16i16, MVT::v16f64, 7 },
2325 { ISD::FP_TO_SINT, MVT::v32i16, MVT::v32f32, 5 },
2326 { ISD::FP_TO_SINT, MVT::v32i16, MVT::v32f64,15 },
2327 { ISD::FP_TO_SINT, MVT::v8i32, MVT::v8f64, 1 },
2328 { ISD::FP_TO_SINT, MVT::v16i32, MVT::v16f64, 3 },
2329
2330 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v8f64, 1 },
2331 { ISD::FP_TO_UINT, MVT::v8i16, MVT::v8f64, 3 },
2332 { ISD::FP_TO_UINT, MVT::v8i8, MVT::v8f64, 3 },
2333 { ISD::FP_TO_UINT, MVT::v16i32, MVT::v16f32, 1 },
2334 { ISD::FP_TO_UINT, MVT::v16i16, MVT::v16f32, 3 },
2335 { ISD::FP_TO_UINT, MVT::v16i8, MVT::v16f32, 3 },
2336 };
2337
2338 static const TypeConversionCostTblEntry AVX512BWVLConversionTbl[] {
2339 // Mask sign extend has an instruction.
2340 { ISD::SIGN_EXTEND, MVT::v2i8, MVT::v2i1, 1 },
2341 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v2i1, 1 },
2342 { ISD::SIGN_EXTEND, MVT::v2i16, MVT::v2i1, 1 },
2343 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v2i1, 1 },
2344 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i1, 1 },
2345 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v4i1, 1 },
2346 { ISD::SIGN_EXTEND, MVT::v4i8, MVT::v4i1, 1 },
2347 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v4i1, 1 },
2348 { ISD::SIGN_EXTEND, MVT::v8i8, MVT::v8i1, 1 },
2349 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v8i1, 1 },
2350 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i1, 1 },
2351 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v16i1, 1 },
2352 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 1 },
2353 { ISD::SIGN_EXTEND, MVT::v32i8, MVT::v32i1, 1 },
2354 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v32i1, 1 },
2355 { ISD::SIGN_EXTEND, MVT::v32i8, MVT::v64i1, 1 },
2356 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v64i1, 1 },
2357
2358 // Mask zero extend is a sext + shift.
2359 { ISD::ZERO_EXTEND, MVT::v2i8, MVT::v2i1, 2 },
2360 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v2i1, 2 },
2361 { ISD::ZERO_EXTEND, MVT::v2i16, MVT::v2i1, 2 },
2362 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v2i1, 2 },
2363 { ISD::ZERO_EXTEND, MVT::v4i8, MVT::v4i1, 2 },
2364 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v4i1, 2 },
2365 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i1, 2 },
2366 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v4i1, 2 },
2367 { ISD::ZERO_EXTEND, MVT::v8i8, MVT::v8i1, 2 },
2368 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v8i1, 2 },
2369 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i1, 2 },
2370 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v16i1, 2 },
2371 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 2 },
2372 { ISD::ZERO_EXTEND, MVT::v32i8, MVT::v32i1, 2 },
2373 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v32i1, 2 },
2374 { ISD::ZERO_EXTEND, MVT::v32i8, MVT::v64i1, 2 },
2375 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v64i1, 2 },
2376
2377 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i8, 2 },
2378 { ISD::TRUNCATE, MVT::v2i1, MVT::v16i8, 2 },
2379 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i16, 2 },
2380 { ISD::TRUNCATE, MVT::v2i1, MVT::v8i16, 2 },
2381 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i8, 2 },
2382 { ISD::TRUNCATE, MVT::v4i1, MVT::v16i8, 2 },
2383 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i16, 2 },
2384 { ISD::TRUNCATE, MVT::v4i1, MVT::v8i16, 2 },
2385 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i8, 2 },
2386 { ISD::TRUNCATE, MVT::v8i1, MVT::v16i8, 2 },
2387 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i16, 2 },
2388 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i8, 2 },
2389 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i16, 2 },
2390 { ISD::TRUNCATE, MVT::v32i1, MVT::v32i8, 2 },
2391 { ISD::TRUNCATE, MVT::v32i1, MVT::v16i16, 2 },
2392 { ISD::TRUNCATE, MVT::v64i1, MVT::v32i8, 2 },
2393 { ISD::TRUNCATE, MVT::v64i1, MVT::v16i16, 2 },
2394
2395 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 2 },
2396 };
2397
2398 static const TypeConversionCostTblEntry AVX512DQVLConversionTbl[] = {
2399 // Mask sign extend has an instruction.
2400 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v2i1, 1 },
2401 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v2i1, 1 },
2402 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i1, 1 },
2403 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v16i1, 1 },
2404 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 1 },
2405 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v8i1, 1 },
2406 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v16i1, 1 },
2407 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 1 },
2408
2409 // Mask zero extend is a sext + shift.
2410 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v2i1, 2 },
2411 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v2i1, 2 },
2412 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i1, 2 },
2413 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v16i1, 2 },
2414 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 2 },
2415 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v8i1, 2 },
2416 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v16i1, 2 },
2417 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 2 },
2418
2419 { ISD::TRUNCATE, MVT::v16i1, MVT::v4i64, 2 },
2420 { ISD::TRUNCATE, MVT::v16i1, MVT::v8i32, 2 },
2421 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i64, 2 },
2422 { ISD::TRUNCATE, MVT::v2i1, MVT::v4i32, 2 },
2423 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i32, 2 },
2424 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i64, 2 },
2425 { ISD::TRUNCATE, MVT::v8i1, MVT::v4i64, 2 },
2426 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i32, 2 },
2427
2428 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i64, 1 },
2429 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i64, 1 },
2430 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i64, 1 },
2431 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i64, 1 },
2432
2433 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i64, 1 },
2434 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 1 },
2435 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i64, 1 },
2436 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i64, 1 },
2437
2438 { ISD::FP_TO_SINT, MVT::v2i64, MVT::v4f32, 1 },
2439 { ISD::FP_TO_SINT, MVT::v4i64, MVT::v4f32, 1 },
2440 { ISD::FP_TO_SINT, MVT::v2i64, MVT::v2f64, 1 },
2441 { ISD::FP_TO_SINT, MVT::v4i64, MVT::v4f64, 1 },
2442
2443 { ISD::FP_TO_UINT, MVT::v2i64, MVT::v4f32, 1 },
2444 { ISD::FP_TO_UINT, MVT::v4i64, MVT::v4f32, 1 },
2445 { ISD::FP_TO_UINT, MVT::v2i64, MVT::v2f64, 1 },
2446 { ISD::FP_TO_UINT, MVT::v4i64, MVT::v4f64, 1 },
2447 };
2448
2449 static const TypeConversionCostTblEntry AVX512VLConversionTbl[] = {
2450 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i8, 3 }, // sext+vpslld+vptestmd
2451 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i8, 3 }, // sext+vpslld+vptestmd
2452 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i8, 3 }, // sext+vpslld+vptestmd
2453 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i8, 8 }, // split+2*v8i8
2454 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i16, 3 }, // sext+vpsllq+vptestmq
2455 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i16, 3 }, // sext+vpsllq+vptestmq
2456 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i16, 3 }, // sext+vpsllq+vptestmq
2457 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i16, 8 }, // split+2*v8i16
2458 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i32, 2 }, // vpslld+vptestmd
2459 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i32, 2 }, // vpslld+vptestmd
2460 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i32, 2 }, // vpslld+vptestmd
2461 { ISD::TRUNCATE, MVT::v16i1, MVT::v8i32, 2 }, // vpslld+vptestmd
2462 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i64, 2 }, // vpsllq+vptestmq
2463 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i64, 2 }, // vpsllq+vptestmq
2464 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 1 }, // vpmovqd
2465 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i64, 2 }, // vpmovqb
2466 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i64, 2 }, // vpmovqw
2467 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 2 }, // vpmovwb
2468
2469 // sign extend is vpcmpeq+maskedmove+vpmovdw+vpacksswb
2470 // zero extend is vpcmpeq+maskedmove+vpmovdw+vpsrlw+vpackuswb
2471 { ISD::SIGN_EXTEND, MVT::v2i8, MVT::v2i1, 5 },
2472 { ISD::ZERO_EXTEND, MVT::v2i8, MVT::v2i1, 6 },
2473 { ISD::SIGN_EXTEND, MVT::v4i8, MVT::v4i1, 5 },
2474 { ISD::ZERO_EXTEND, MVT::v4i8, MVT::v4i1, 6 },
2475 { ISD::SIGN_EXTEND, MVT::v8i8, MVT::v8i1, 5 },
2476 { ISD::ZERO_EXTEND, MVT::v8i8, MVT::v8i1, 6 },
2477 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v16i1, 10 },
2478 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v16i1, 12 },
2479
2480 // sign extend is vpcmpeq+maskedmove+vpmovdw
2481 // zero extend is vpcmpeq+maskedmove+vpmovdw+vpsrlw
2482 { ISD::SIGN_EXTEND, MVT::v2i16, MVT::v2i1, 4 },
2483 { ISD::ZERO_EXTEND, MVT::v2i16, MVT::v2i1, 5 },
2484 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i1, 4 },
2485 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i1, 5 },
2486 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i1, 4 },
2487 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i1, 5 },
2488 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 10 },
2489 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 12 },
2490
2491 { ISD::SIGN_EXTEND, MVT::v2i32, MVT::v2i1, 1 }, // vpternlogd
2492 { ISD::ZERO_EXTEND, MVT::v2i32, MVT::v2i1, 2 }, // vpternlogd+psrld
2493 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i1, 1 }, // vpternlogd
2494 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i1, 2 }, // vpternlogd+psrld
2495 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 1 }, // vpternlogd
2496 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 2 }, // vpternlogd+psrld
2497 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v16i1, 1 }, // vpternlogd
2498 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v16i1, 2 }, // vpternlogd+psrld
2499
2500 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v2i1, 1 }, // vpternlogq
2501 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v2i1, 2 }, // vpternlogq+psrlq
2502 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 1 }, // vpternlogq
2503 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 2 }, // vpternlogq+psrlq
2504
2505 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v16i8, 1 },
2506 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v16i8, 1 },
2507 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v16i8, 1 },
2508 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v16i8, 1 },
2509 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 1 },
2510 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 1 },
2511 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v8i16, 1 },
2512 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v8i16, 1 },
2513 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 1 },
2514 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 1 },
2515 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 1 },
2516 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 1 },
2517
2518 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v16i8, 1 },
2519 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v16i8, 1 },
2520 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v8i16, 1 },
2521 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i16, 1 },
2522
2523 { ISD::UINT_TO_FP, MVT::f32, MVT::i64, 1 },
2524 { ISD::UINT_TO_FP, MVT::f64, MVT::i64, 1 },
2525 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v16i8, 1 },
2526 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v16i8, 1 },
2527 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v8i16, 1 },
2528 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i16, 1 },
2529 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i32, 1 },
2530 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 },
2531 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i32, 1 },
2532 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 1 },
2533 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i64, 5 },
2534 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 5 },
2535 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i64, 5 },
2536
2537 { ISD::FP_TO_SINT, MVT::v16i8, MVT::v8f32, 2 },
2538 { ISD::FP_TO_SINT, MVT::v16i8, MVT::v16f32, 2 },
2539 { ISD::FP_TO_SINT, MVT::v32i8, MVT::v32f32, 5 },
2540
2541 { ISD::FP_TO_UINT, MVT::i64, MVT::f32, 1 },
2542 { ISD::FP_TO_UINT, MVT::i64, MVT::f64, 1 },
2543 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f32, 1 },
2544 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v2f64, 1 },
2545 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f64, 1 },
2546 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v8f32, 1 },
2547 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v8f64, 1 },
2548 };
2549
2550 static const TypeConversionCostTblEntry AVX2ConversionTbl[] = {
2551 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 3 },
2552 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 3 },
2553 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 3 },
2554 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 3 },
2555 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 1 },
2556 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 1 },
2557
2558 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v16i8, 2 },
2559 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v16i8, 2 },
2560 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v16i8, 2 },
2561 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v16i8, 2 },
2562 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 2 },
2563 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 2 },
2564 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v8i16, 2 },
2565 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v8i16, 2 },
2566 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 2 },
2567 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 2 },
2568 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i16, 3 },
2569 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i16, 3 },
2570 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 2 },
2571 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 2 },
2572
2573 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i32, 2 },
2574
2575 { ISD::TRUNCATE, MVT::v16i16, MVT::v16i32, 4 },
2576 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 4 },
2577 { ISD::TRUNCATE, MVT::v16i8, MVT::v8i16, 1 },
2578 { ISD::TRUNCATE, MVT::v16i8, MVT::v4i32, 1 },
2579 { ISD::TRUNCATE, MVT::v16i8, MVT::v2i64, 1 },
2580 { ISD::TRUNCATE, MVT::v16i8, MVT::v8i32, 4 },
2581 { ISD::TRUNCATE, MVT::v16i8, MVT::v4i64, 4 },
2582 { ISD::TRUNCATE, MVT::v8i16, MVT::v4i32, 1 },
2583 { ISD::TRUNCATE, MVT::v8i16, MVT::v2i64, 1 },
2584 { ISD::TRUNCATE, MVT::v8i16, MVT::v4i64, 5 },
2585 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 1 },
2586 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 2 },
2587
2588 { ISD::FP_EXTEND, MVT::v8f64, MVT::v8f32, 3 },
2589 { ISD::FP_ROUND, MVT::v8f32, MVT::v8f64, 3 },
2590
2591 { ISD::FP_TO_SINT, MVT::v16i16, MVT::v8f32, 1 },
2592 { ISD::FP_TO_SINT, MVT::v4i32, MVT::v4f64, 1 },
2593 { ISD::FP_TO_SINT, MVT::v8i32, MVT::v8f32, 1 },
2594 { ISD::FP_TO_SINT, MVT::v8i32, MVT::v8f64, 3 },
2595
2596 { ISD::FP_TO_UINT, MVT::i64, MVT::f32, 3 },
2597 { ISD::FP_TO_UINT, MVT::i64, MVT::f64, 3 },
2598 { ISD::FP_TO_UINT, MVT::v16i16, MVT::v8f32, 1 },
2599 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f32, 3 },
2600 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v2f64, 4 },
2601 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f64, 4 },
2602 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v8f32, 3 },
2603 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v4f64, 4 },
2604
2605 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v16i8, 2 },
2606 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v16i8, 2 },
2607 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v8i16, 2 },
2608 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i16, 2 },
2609 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i32, 1 },
2610 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i32, 1 },
2611 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i32, 3 },
2612
2613 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v16i8, 2 },
2614 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v16i8, 2 },
2615 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v8i16, 2 },
2616 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i16, 2 },
2617 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i32, 2 },
2618 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i32, 1 },
2619 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 2 },
2620 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i32, 2 },
2621 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 2 },
2622 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i32, 4 },
2623 };
2624
2625 static const TypeConversionCostTblEntry AVXConversionTbl[] = {
2626 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 6 },
2627 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 4 },
2628 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 7 },
2629 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 4 },
2630 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 4 },
2631 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 4 },
2632
2633 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v16i8, 3 },
2634 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v16i8, 3 },
2635 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v16i8, 3 },
2636 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v16i8, 3 },
2637 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 3 },
2638 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 3 },
2639 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v8i16, 3 },
2640 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v8i16, 3 },
2641 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 3 },
2642 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 3 },
2643 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 3 },
2644 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 3 },
2645
2646 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i64, 4 },
2647 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i32, 5 },
2648 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i16, 4 },
2649 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i64, 9 },
2650 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i64, 11 },
2651
2652 { ISD::TRUNCATE, MVT::v16i16, MVT::v16i32, 6 },
2653 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 6 },
2654 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 2 }, // and+extract+packuswb
2655 { ISD::TRUNCATE, MVT::v16i8, MVT::v8i32, 5 },
2656 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 5 },
2657 { ISD::TRUNCATE, MVT::v16i8, MVT::v4i64, 5 },
2658 { ISD::TRUNCATE, MVT::v8i16, MVT::v4i64, 3 }, // and+extract+2*packusdw
2659 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 2 },
2660
2661 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i1, 3 },
2662 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i1, 3 },
2663 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i1, 8 },
2664 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v16i8, 4 },
2665 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v16i8, 2 },
2666 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i16, 4 },
2667 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v8i16, 2 },
2668 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i32, 2 },
2669 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i32, 2 },
2670 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i32, 4 },
2671 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v2i64, 5 },
2672 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i64, 8 },
2673
2674 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i1, 7 },
2675 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i1, 7 },
2676 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i1, 6 },
2677 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v16i8, 4 },
2678 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v16i8, 2 },
2679 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i16, 4 },
2680 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v8i16, 2 },
2681 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i32, 4 },
2682 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i32, 4 },
2683 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 5 },
2684 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i32, 6 },
2685 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 8 },
2686 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i32, 10 },
2687 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i64, 10 },
2688 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i64, 18 },
2689 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 5 },
2690 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i64, 10 },
2691
2692 { ISD::FP_TO_SINT, MVT::v16i8, MVT::v8f32, 2 },
2693 { ISD::FP_TO_SINT, MVT::v16i8, MVT::v4f64, 2 },
2694 { ISD::FP_TO_SINT, MVT::v32i8, MVT::v8f32, 2 },
2695 { ISD::FP_TO_SINT, MVT::v32i8, MVT::v4f64, 2 },
2696 { ISD::FP_TO_SINT, MVT::v8i16, MVT::v8f32, 2 },
2697 { ISD::FP_TO_SINT, MVT::v8i16, MVT::v4f64, 2 },
2698 { ISD::FP_TO_SINT, MVT::v16i16, MVT::v8f32, 2 },
2699 { ISD::FP_TO_SINT, MVT::v16i16, MVT::v4f64, 2 },
2700 { ISD::FP_TO_SINT, MVT::v4i32, MVT::v4f64, 2 },
2701 { ISD::FP_TO_SINT, MVT::v8i32, MVT::v8f32, 2 },
2702 { ISD::FP_TO_SINT, MVT::v8i32, MVT::v8f64, 5 },
2703
2704 { ISD::FP_TO_UINT, MVT::v16i8, MVT::v8f32, 2 },
2705 { ISD::FP_TO_UINT, MVT::v16i8, MVT::v4f64, 2 },
2706 { ISD::FP_TO_UINT, MVT::v32i8, MVT::v8f32, 2 },
2707 { ISD::FP_TO_UINT, MVT::v32i8, MVT::v4f64, 2 },
2708 { ISD::FP_TO_UINT, MVT::v8i16, MVT::v8f32, 2 },
2709 { ISD::FP_TO_UINT, MVT::v8i16, MVT::v4f64, 2 },
2710 { ISD::FP_TO_UINT, MVT::v16i16, MVT::v8f32, 2 },
2711 { ISD::FP_TO_UINT, MVT::v16i16, MVT::v4f64, 2 },
2712 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f32, 3 },
2713 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v2f64, 4 },
2714 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f64, 6 },
2715 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v8f32, 7 },
2716 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v4f64, 7 },
2717
2718 { ISD::FP_EXTEND, MVT::v4f64, MVT::v4f32, 1 },
2719 { ISD::FP_ROUND, MVT::v4f32, MVT::v4f64, 1 },
2720 };
2721
2722 static const TypeConversionCostTblEntry SSE41ConversionTbl[] = {
2723 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v16i8, 1 },
2724 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v16i8, 1 },
2725 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v16i8, 1 },
2726 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v16i8, 1 },
2727 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v16i8, 1 },
2728 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v16i8, 1 },
2729 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v8i16, 1 },
2730 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v8i16, 1 },
2731 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v8i16, 1 },
2732 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v8i16, 1 },
2733 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v4i32, 1 },
2734 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v4i32, 1 },
2735
2736 // These truncates end up widening elements.
2737 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i8, 1 }, // PMOVXZBQ
2738 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i16, 1 }, // PMOVXZWQ
2739 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i8, 1 }, // PMOVXZBD
2740
2741 { ISD::TRUNCATE, MVT::v16i8, MVT::v4i32, 2 },
2742 { ISD::TRUNCATE, MVT::v8i16, MVT::v4i32, 2 },
2743 { ISD::TRUNCATE, MVT::v16i8, MVT::v2i64, 2 },
2744
2745 { ISD::SINT_TO_FP, MVT::f32, MVT::i32, 1 },
2746 { ISD::SINT_TO_FP, MVT::f64, MVT::i32, 1 },
2747 { ISD::SINT_TO_FP, MVT::f32, MVT::i64, 1 },
2748 { ISD::SINT_TO_FP, MVT::f64, MVT::i64, 1 },
2749 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v16i8, 1 },
2750 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v16i8, 1 },
2751 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v8i16, 1 },
2752 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v8i16, 1 },
2753 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 },
2754 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v4i32, 1 },
2755 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i32, 2 },
2756
2757 { ISD::UINT_TO_FP, MVT::f32, MVT::i32, 1 },
2758 { ISD::UINT_TO_FP, MVT::f64, MVT::i32, 1 },
2759 { ISD::UINT_TO_FP, MVT::f32, MVT::i64, 4 },
2760 { ISD::UINT_TO_FP, MVT::f64, MVT::i64, 4 },
2761 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v16i8, 1 },
2762 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v16i8, 1 },
2763 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v8i16, 1 },
2764 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v8i16, 1 },
2765 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i32, 3 },
2766 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 3 },
2767 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v4i32, 2 },
2768 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v2i64, 12 },
2769 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i64, 22 },
2770 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 4 },
2771
2772 { ISD::FP_TO_SINT, MVT::i32, MVT::f32, 1 },
2773 { ISD::FP_TO_SINT, MVT::i64, MVT::f32, 1 },
2774 { ISD::FP_TO_SINT, MVT::i32, MVT::f64, 1 },
2775 { ISD::FP_TO_SINT, MVT::i64, MVT::f64, 1 },
2776 { ISD::FP_TO_SINT, MVT::v16i8, MVT::v4f32, 2 },
2777 { ISD::FP_TO_SINT, MVT::v16i8, MVT::v2f64, 2 },
2778 { ISD::FP_TO_SINT, MVT::v8i16, MVT::v4f32, 1 },
2779 { ISD::FP_TO_SINT, MVT::v8i16, MVT::v2f64, 1 },
2780 { ISD::FP_TO_SINT, MVT::v4i32, MVT::v4f32, 1 },
2781 { ISD::FP_TO_SINT, MVT::v4i32, MVT::v2f64, 1 },
2782
2783 { ISD::FP_TO_UINT, MVT::i32, MVT::f32, 1 },
2784 { ISD::FP_TO_UINT, MVT::i64, MVT::f32, 4 },
2785 { ISD::FP_TO_UINT, MVT::i32, MVT::f64, 1 },
2786 { ISD::FP_TO_UINT, MVT::i64, MVT::f64, 4 },
2787 { ISD::FP_TO_UINT, MVT::v16i8, MVT::v4f32, 2 },
2788 { ISD::FP_TO_UINT, MVT::v16i8, MVT::v2f64, 2 },
2789 { ISD::FP_TO_UINT, MVT::v8i16, MVT::v4f32, 1 },
2790 { ISD::FP_TO_UINT, MVT::v8i16, MVT::v2f64, 1 },
2791 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f32, 4 },
2792 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v2f64, 4 },
2793 };
2794
2795 static const TypeConversionCostTblEntry SSE2ConversionTbl[] = {
2796 // These are somewhat magic numbers justified by comparing the
2797 // output of llvm-mca for our various supported scheduler models
2798 // and basing it off the worst case scenario.
2799 { ISD::SINT_TO_FP, MVT::f32, MVT::i32, 3 },
2800 { ISD::SINT_TO_FP, MVT::f64, MVT::i32, 3 },
2801 { ISD::SINT_TO_FP, MVT::f32, MVT::i64, 3 },
2802 { ISD::SINT_TO_FP, MVT::f64, MVT::i64, 3 },
2803 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v16i8, 3 },
2804 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v16i8, 4 },
2805 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v8i16, 3 },
2806 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v8i16, 4 },
2807 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 3 },
2808 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v4i32, 4 },
2809 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v2i64, 8 },
2810 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i64, 8 },
2811
2812 { ISD::UINT_TO_FP, MVT::f32, MVT::i32, 3 },
2813 { ISD::UINT_TO_FP, MVT::f64, MVT::i32, 3 },
2814 { ISD::UINT_TO_FP, MVT::f32, MVT::i64, 8 },
2815 { ISD::UINT_TO_FP, MVT::f64, MVT::i64, 9 },
2816 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v16i8, 4 },
2817 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v16i8, 4 },
2818 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v8i16, 4 },
2819 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v8i16, 4 },
2820 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i32, 7 },
2821 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v4i32, 7 },
2822 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 5 },
2823 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 15 },
2824 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v2i64, 18 },
2825
2826 { ISD::FP_TO_SINT, MVT::i32, MVT::f32, 4 },
2827 { ISD::FP_TO_SINT, MVT::i64, MVT::f32, 4 },
2828 { ISD::FP_TO_SINT, MVT::i32, MVT::f64, 4 },
2829 { ISD::FP_TO_SINT, MVT::i64, MVT::f64, 4 },
2830 { ISD::FP_TO_SINT, MVT::v16i8, MVT::v4f32, 6 },
2831 { ISD::FP_TO_SINT, MVT::v16i8, MVT::v2f64, 6 },
2832 { ISD::FP_TO_SINT, MVT::v8i16, MVT::v4f32, 5 },
2833 { ISD::FP_TO_SINT, MVT::v8i16, MVT::v2f64, 5 },
2834 { ISD::FP_TO_SINT, MVT::v4i32, MVT::v4f32, 4 },
2835 { ISD::FP_TO_SINT, MVT::v4i32, MVT::v2f64, 4 },
2836
2837 { ISD::FP_TO_UINT, MVT::i32, MVT::f32, 4 },
2838 { ISD::FP_TO_UINT, MVT::i64, MVT::f32, 4 },
2839 { ISD::FP_TO_UINT, MVT::i32, MVT::f64, 4 },
2840 { ISD::FP_TO_UINT, MVT::i64, MVT::f64, 15 },
2841 { ISD::FP_TO_UINT, MVT::v16i8, MVT::v4f32, 6 },
2842 { ISD::FP_TO_UINT, MVT::v16i8, MVT::v2f64, 6 },
2843 { ISD::FP_TO_UINT, MVT::v8i16, MVT::v4f32, 5 },
2844 { ISD::FP_TO_UINT, MVT::v8i16, MVT::v2f64, 5 },
2845 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f32, 8 },
2846 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v2f64, 8 },
2847
2848 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v16i8, 4 },
2849 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v16i8, 4 },
2850 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v16i8, 2 },
2851 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v16i8, 3 },
2852 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v16i8, 1 },
2853 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v16i8, 2 },
2854 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v8i16, 2 },
2855 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v8i16, 3 },
2856 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v8i16, 1 },
2857 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v8i16, 2 },
2858 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v4i32, 1 },
2859 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v4i32, 2 },
2860
2861 // These truncates are really widening elements.
2862 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i32, 1 }, // PSHUFD
2863 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i16, 2 }, // PUNPCKLWD+DQ
2864 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i8, 3 }, // PUNPCKLBW+WD+PSHUFD
2865 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i16, 1 }, // PUNPCKLWD
2866 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i8, 2 }, // PUNPCKLBW+WD
2867 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i8, 1 }, // PUNPCKLBW
2868
2869 { ISD::TRUNCATE, MVT::v16i8, MVT::v8i16, 2 }, // PAND+PACKUSWB
2870 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 3 },
2871 { ISD::TRUNCATE, MVT::v16i8, MVT::v4i32, 3 }, // PAND+2*PACKUSWB
2872 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 7 },
2873 { ISD::TRUNCATE, MVT::v2i16, MVT::v2i32, 1 },
2874 { ISD::TRUNCATE, MVT::v8i16, MVT::v4i32, 3 },
2875 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 5 },
2876 { ISD::TRUNCATE, MVT::v16i16, MVT::v16i32,10 },
2877 { ISD::TRUNCATE, MVT::v16i8, MVT::v2i64, 4 }, // PAND+3*PACKUSWB
2878 { ISD::TRUNCATE, MVT::v8i16, MVT::v2i64, 2 }, // PSHUFD+PSHUFLW
2879 { ISD::TRUNCATE, MVT::v4i32, MVT::v2i64, 1 }, // PSHUFD
2880 };
2881
2882 // Attempt to map directly to (simple) MVT types to let us match custom entries.
2883 EVT SrcTy = TLI->getValueType(DL, Src);
2884 EVT DstTy = TLI->getValueType(DL, Dst);
2885
2886 // The function getSimpleVT only handles simple value types.
2887 if (SrcTy.isSimple() && DstTy.isSimple()) {
2888 MVT SimpleSrcTy = SrcTy.getSimpleVT();
2889 MVT SimpleDstTy = DstTy.getSimpleVT();
2890
2891 if (ST->useAVX512Regs()) {
2892 if (ST->hasBWI())
2893 if (const auto *Entry = ConvertCostTableLookup(
2894 AVX512BWConversionTbl, ISD, SimpleDstTy, SimpleSrcTy))
2895 return AdjustCost(Entry->Cost);
2896
2897 if (ST->hasDQI())
2898 if (const auto *Entry = ConvertCostTableLookup(
2899 AVX512DQConversionTbl, ISD, SimpleDstTy, SimpleSrcTy))
2900 return AdjustCost(Entry->Cost);
2901
2902 if (ST->hasAVX512())
2903 if (const auto *Entry = ConvertCostTableLookup(
2904 AVX512FConversionTbl, ISD, SimpleDstTy, SimpleSrcTy))
2905 return AdjustCost(Entry->Cost);
2906 }
2907
2908 if (ST->hasBWI())
2909 if (const auto *Entry = ConvertCostTableLookup(
2910 AVX512BWVLConversionTbl, ISD, SimpleDstTy, SimpleSrcTy))
2911 return AdjustCost(Entry->Cost);
2912
2913 if (ST->hasDQI())
2914 if (const auto *Entry = ConvertCostTableLookup(
2915 AVX512DQVLConversionTbl, ISD, SimpleDstTy, SimpleSrcTy))
2916 return AdjustCost(Entry->Cost);
2917
2918 if (ST->hasAVX512())
2919 if (const auto *Entry = ConvertCostTableLookup(AVX512VLConversionTbl, ISD,
2920 SimpleDstTy, SimpleSrcTy))
2921 return AdjustCost(Entry->Cost);
2922
2923 if (ST->hasAVX2()) {
2924 if (const auto *Entry = ConvertCostTableLookup(AVX2ConversionTbl, ISD,
2925 SimpleDstTy, SimpleSrcTy))
2926 return AdjustCost(Entry->Cost);
2927 }
2928
2929 if (ST->hasAVX()) {
2930 if (const auto *Entry = ConvertCostTableLookup(AVXConversionTbl, ISD,
2931 SimpleDstTy, SimpleSrcTy))
2932 return AdjustCost(Entry->Cost);
2933 }
2934
2935 if (ST->hasSSE41()) {
2936 if (const auto *Entry = ConvertCostTableLookup(SSE41ConversionTbl, ISD,
2937 SimpleDstTy, SimpleSrcTy))
2938 return AdjustCost(Entry->Cost);
2939 }
2940
2941 if (ST->hasSSE2()) {
2942 if (const auto *Entry = ConvertCostTableLookup(SSE2ConversionTbl, ISD,
2943 SimpleDstTy, SimpleSrcTy))
2944 return AdjustCost(Entry->Cost);
2945 }
2946 }
2947
2948 // Fall back to legalized types.
2949 std::pair<InstructionCost, MVT> LTSrc = getTypeLegalizationCost(Src);
2950 std::pair<InstructionCost, MVT> LTDest = getTypeLegalizationCost(Dst);
2951
2952 // If we're truncating to the same legalized type - just assume its free.
2953 if (ISD == ISD::TRUNCATE && LTSrc.second == LTDest.second)
2954 return TTI::TCC_Free;
2955
2956 if (ST->useAVX512Regs()) {
2957 if (ST->hasBWI())
2958 if (const auto *Entry = ConvertCostTableLookup(
2959 AVX512BWConversionTbl, ISD, LTDest.second, LTSrc.second))
2960 return AdjustCost(std::max(LTSrc.first, LTDest.first) * Entry->Cost);
2961
2962 if (ST->hasDQI())
2963 if (const auto *Entry = ConvertCostTableLookup(
2964 AVX512DQConversionTbl, ISD, LTDest.second, LTSrc.second))
2965 return AdjustCost(std::max(LTSrc.first, LTDest.first) * Entry->Cost);
2966
2967 if (ST->hasAVX512())
2968 if (const auto *Entry = ConvertCostTableLookup(
2969 AVX512FConversionTbl, ISD, LTDest.second, LTSrc.second))
2970 return AdjustCost(std::max(LTSrc.first, LTDest.first) * Entry->Cost);
2971 }
2972
2973 if (ST->hasBWI())
2974 if (const auto *Entry = ConvertCostTableLookup(AVX512BWVLConversionTbl, ISD,
2975 LTDest.second, LTSrc.second))
2976 return AdjustCost(std::max(LTSrc.first, LTDest.first) * Entry->Cost);
2977
2978 if (ST->hasDQI())
2979 if (const auto *Entry = ConvertCostTableLookup(AVX512DQVLConversionTbl, ISD,
2980 LTDest.second, LTSrc.second))
2981 return AdjustCost(std::max(LTSrc.first, LTDest.first) * Entry->Cost);
2982
2983 if (ST->hasAVX512())
2984 if (const auto *Entry = ConvertCostTableLookup(AVX512VLConversionTbl, ISD,
2985 LTDest.second, LTSrc.second))
2986 return AdjustCost(std::max(LTSrc.first, LTDest.first) * Entry->Cost);
2987
2988 if (ST->hasAVX2())
2989 if (const auto *Entry = ConvertCostTableLookup(AVX2ConversionTbl, ISD,
2990 LTDest.second, LTSrc.second))
2991 return AdjustCost(std::max(LTSrc.first, LTDest.first) * Entry->Cost);
2992
2993 if (ST->hasAVX())
2994 if (const auto *Entry = ConvertCostTableLookup(AVXConversionTbl, ISD,
2995 LTDest.second, LTSrc.second))
2996 return AdjustCost(std::max(LTSrc.first, LTDest.first) * Entry->Cost);
2997
2998 if (ST->hasSSE41())
2999 if (const auto *Entry = ConvertCostTableLookup(SSE41ConversionTbl, ISD,
3000 LTDest.second, LTSrc.second))
3001 return AdjustCost(std::max(LTSrc.first, LTDest.first) * Entry->Cost);
3002
3003 if (ST->hasSSE2())
3004 if (const auto *Entry = ConvertCostTableLookup(SSE2ConversionTbl, ISD,
3005 LTDest.second, LTSrc.second))
3006 return AdjustCost(std::max(LTSrc.first, LTDest.first) * Entry->Cost);
3007
3008 // Fallback, for i8/i16 sitofp/uitofp cases we need to extend to i32 for
3009 // sitofp.
3010 if ((ISD == ISD::SINT_TO_FP || ISD == ISD::UINT_TO_FP) &&
3011 1 < Src->getScalarSizeInBits() && Src->getScalarSizeInBits() < 32) {
3012 Type *ExtSrc = Src->getWithNewBitWidth(32);
3013 unsigned ExtOpc =
3014 (ISD == ISD::SINT_TO_FP) ? Instruction::SExt : Instruction::ZExt;
3015
3016 // For scalar loads the extend would be free.
3017 InstructionCost ExtCost = 0;
3018 if (!(Src->isIntegerTy() && I && isa<LoadInst>(I->getOperand(0))))
3019 ExtCost = getCastInstrCost(ExtOpc, ExtSrc, Src, CCH, CostKind);
3020
3021 return ExtCost + getCastInstrCost(Instruction::SIToFP, Dst, ExtSrc,
3022 TTI::CastContextHint::None, CostKind);
3023 }
3024
3025 // Fallback for fptosi/fptoui i8/i16 cases we need to truncate from fptosi
3026 // i32.
3027 if ((ISD == ISD::FP_TO_SINT || ISD == ISD::FP_TO_UINT) &&
3028 1 < Dst->getScalarSizeInBits() && Dst->getScalarSizeInBits() < 32) {
3029 Type *TruncDst = Dst->getWithNewBitWidth(32);
3030 return getCastInstrCost(Instruction::FPToSI, TruncDst, Src, CCH, CostKind) +
3031 getCastInstrCost(Instruction::Trunc, Dst, TruncDst,
3032 TTI::CastContextHint::None, CostKind);
3033 }
3034
3035 return AdjustCost(
3036 BaseT::getCastInstrCost(Opcode, Dst, Src, CCH, CostKind, I));
3037}
3038
3039InstructionCost X86TTIImpl::getCmpSelInstrCost(unsigned Opcode, Type *ValTy,
3040 Type *CondTy,
3041 CmpInst::Predicate VecPred,
3042 TTI::TargetCostKind CostKind,
3043 const Instruction *I) {
3044 // Early out if this type isn't scalar/vector integer/float.
3045 if (!(ValTy->isIntOrIntVectorTy() || ValTy->isFPOrFPVectorTy()))
3046 return BaseT::getCmpSelInstrCost(Opcode, ValTy, CondTy, VecPred, CostKind,
3047 I);
3048
3049 // Legalize the type.
3050 std::pair<InstructionCost, MVT> LT = getTypeLegalizationCost(ValTy);
3051
3052 MVT MTy = LT.second;
3053
3054 int ISD = TLI->InstructionOpcodeToISD(Opcode);
3055 assert(ISD && "Invalid opcode")(static_cast <bool> (ISD && "Invalid opcode") ?
void (0) : __assert_fail ("ISD && \"Invalid opcode\""
, "llvm/lib/Target/X86/X86TargetTransformInfo.cpp", 3055, __extension__
__PRETTY_FUNCTION__));
3056
3057 InstructionCost ExtraCost = 0;
3058 if (Opcode == Instruction::ICmp || Opcode == Instruction::FCmp) {
3059 // Some vector comparison predicates cost extra instructions.
3060 // TODO: Should we invert this and assume worst case cmp costs
3061 // and reduce for particular predicates?
3062 if (MTy.isVector() &&
3063 !((ST->hasXOP() && (!ST->hasAVX2() || MTy.is128BitVector())) ||
3064 (ST->hasAVX512() && 32 <= MTy.getScalarSizeInBits()) ||
3065 ST->hasBWI())) {
3066 // Fallback to I if a specific predicate wasn't specified.
3067 CmpInst::Predicate Pred = VecPred;
3068 if (I && (Pred == CmpInst::BAD_ICMP_PREDICATE ||
3069 Pred == CmpInst::BAD_FCMP_PREDICATE))
3070 Pred = cast<CmpInst>(I)->getPredicate();
3071
3072 switch (Pred) {
3073 case CmpInst::Predicate::ICMP_NE:
3074 // xor(cmpeq(x,y),-1)
3075 ExtraCost = 1;
3076 break;
3077 case CmpInst::Predicate::ICMP_SGE:
3078 case CmpInst::Predicate::ICMP_SLE:
3079 // xor(cmpgt(x,y),-1)
3080 ExtraCost = 1;
3081 break;
3082 case CmpInst::Predicate::ICMP_ULT:
3083 case CmpInst::Predicate::ICMP_UGT:
3084 // cmpgt(xor(x,signbit),xor(y,signbit))
3085 // xor(cmpeq(pmaxu(x,y),x),-1)
3086 ExtraCost = 2;
3087 break;
3088 case CmpInst::Predicate::ICMP_ULE:
3089 case CmpInst::Predicate::ICMP_UGE:
3090 if ((ST->hasSSE41() && MTy.getScalarSizeInBits() == 32) ||
3091 (ST->hasSSE2() && MTy.getScalarSizeInBits() < 32)) {
3092 // cmpeq(psubus(x,y),0)
3093 // cmpeq(pminu(x,y),x)
3094 ExtraCost = 1;
3095 } else {
3096 // xor(cmpgt(xor(x,signbit),xor(y,signbit)),-1)
3097 ExtraCost = 3;
3098 }
3099 break;
3100 case CmpInst::Predicate::FCMP_ONE:
3101 case CmpInst::Predicate::FCMP_UEQ:
3102 // Without AVX we need to expand FCMP_ONE/FCMP_UEQ cases.
3103 // Use FCMP_UEQ expansion - FCMP_ONE should be the same.
3104 if (CondTy && !ST->hasAVX())
3105 return getCmpSelInstrCost(Opcode, ValTy, CondTy,
3106 CmpInst::Predicate::FCMP_UNO, CostKind) +
3107 getCmpSelInstrCost(Opcode, ValTy, CondTy,
3108 CmpInst::Predicate::FCMP_OEQ, CostKind) +
3109 getArithmeticInstrCost(Instruction::Or, CondTy, CostKind);
3110
3111 break;
3112 case CmpInst::Predicate::BAD_ICMP_PREDICATE:
3113 case CmpInst::Predicate::BAD_FCMP_PREDICATE:
3114 // Assume worst case scenario and add the maximum extra cost.
3115 ExtraCost = 3;
3116 break;
3117 default:
3118 break;
3119 }
3120 }
3121 }
3122
3123 static const CostKindTblEntry SLMCostTbl[] = {
3124 // slm pcmpeq/pcmpgt throughput is 2
3125 { ISD::SETCC, MVT::v2i64, { 2, 5, 1, 2 } },
3126 // slm pblendvb/blendvpd/blendvps throughput is 4
3127 { ISD::SELECT, MVT::v2f64, { 4, 4, 1, 3 } }, // vblendvpd
3128 { ISD::SELECT, MVT::v4f32, { 4, 4, 1, 3 } }, // vblendvps
3129 { ISD::SELECT, MVT::v2i64, { 4, 4, 1, 3 } }, // pblendvb
3130 { ISD::SELECT, MVT::v8i32, { 4, 4, 1, 3 } }, // pblendvb
3131 { ISD::SELECT, MVT::v8i16, { 4, 4, 1, 3 } }, // pblendvb
3132 { ISD::SELECT, MVT::v16i8, { 4, 4, 1, 3 } }, // pblendvb
3133 };
3134
3135 static const CostKindTblEntry AVX512BWCostTbl[] = {
3136 { ISD::SETCC, MVT::v32i16, { 1, 1, 1, 1 } },
3137 { ISD::SETCC, MVT::v16i16, { 1, 1, 1, 1 } },
3138 { ISD::SETCC, MVT::v64i8, { 1, 1, 1, 1 } },
3139 { ISD::SETCC, MVT::v32i8, { 1, 1, 1, 1 } },
3140
3141 { ISD::SELECT, MVT::v32i16, { 1, 1, 1, 1 } },
3142 { ISD::SELECT, MVT::v64i8, { 1, 1, 1, 1 } },
3143 };
3144
3145 static const CostKindTblEntry AVX512CostTbl[] = {
3146 { ISD::SETCC, MVT::v8f64, { 1, 4, 1, 1 } },
3147 { ISD::SETCC, MVT::v4f64, { 1, 4, 1, 1 } },
3148 { ISD::SETCC, MVT::v16f32, { 1, 4, 1, 1 } },
3149 { ISD::SETCC, MVT::v8f32, { 1, 4, 1, 1 } },
3150
3151 { ISD::SETCC, MVT::v8i64, { 1, 1, 1, 1 } },
3152 { ISD::SETCC, MVT::v4i64, { 1, 1, 1, 1 } },
3153 { ISD::SETCC, MVT::v2i64, { 1, 1, 1, 1 } },
3154 { ISD::SETCC, MVT::v16i32, { 1, 1, 1, 1 } },
3155 { ISD::SETCC, MVT::v8i32, { 1, 1, 1, 1 } },
3156 { ISD::SETCC, MVT::v32i16, { 3, 7, 5, 5 } },
3157 { ISD::SETCC, MVT::v64i8, { 3, 7, 5, 5 } },
3158
3159 { ISD::SELECT, MVT::v8i64, { 1, 1, 1, 1 } },
3160 { ISD::SELECT, MVT::v4i64, { 1, 1, 1, 1 } },
3161 { ISD::SELECT, MVT::v2i64, { 1, 1, 1, 1 } },
3162 { ISD::SELECT, MVT::v16i32, { 1, 1, 1, 1 } },
3163 { ISD::SELECT, MVT::v8i32, { 1, 1, 1, 1 } },
3164 { ISD::SELECT, MVT::v4i32, { 1, 1, 1, 1 } },
3165 { ISD::SELECT, MVT::v8f64, { 1, 1, 1, 1 } },
3166 { ISD::SELECT, MVT::v4f64, { 1, 1, 1, 1 } },
3167 { ISD::SELECT, MVT::v2f64, { 1, 1, 1, 1 } },
3168 { ISD::SELECT, MVT::f64, { 1, 1, 1, 1 } },
3169 { ISD::SELECT, MVT::v16f32, { 1, 1, 1, 1 } },
3170 { ISD::SELECT, MVT::v8f32 , { 1, 1, 1, 1 } },
3171 { ISD::SELECT, MVT::v4f32, { 1, 1, 1, 1 } },
3172 { ISD::SELECT, MVT::f32 , { 1, 1, 1, 1 } },
3173
3174 { ISD::SELECT, MVT::v32i16, { 2, 2, 4, 4 } },
3175 { ISD::SELECT, MVT::v16i16, { 1, 1, 1, 1 } },
3176 { ISD::SELECT, MVT::v8i16, { 1, 1, 1, 1 } },
3177 { ISD::SELECT, MVT::v64i8, { 2, 2, 4, 4 } },
3178 { ISD::SELECT, MVT::v32i8, { 1, 1, 1, 1 } },
3179 { ISD::SELECT, MVT::v16i8, { 1, 1, 1, 1 } },
3180 };
3181
3182 static const CostKindTblEntry AVX2CostTbl[] = {
3183 { ISD::SETCC, MVT::v4f64, { 1, 4, 1, 2 } },
3184 { ISD::SETCC, MVT::v2f64, { 1, 4, 1, 1 } },
3185 { ISD::SETCC, MVT::f64, { 1, 4, 1, 1 } },
3186 { ISD::SETCC, MVT::v8f32, { 1, 4, 1, 2 } },
3187 { ISD::SETCC, MVT::v4f32, { 1, 4, 1, 1 } },
3188 { ISD::SETCC, MVT::f32, { 1, 4, 1, 1 } },
3189
3190 { ISD::SETCC, MVT::v4i64, { 1, 1, 1, 2 } },
3191 { ISD::SETCC, MVT::v8i32, { 1, 1, 1, 2 } },
3192 { ISD::SETCC, MVT::v16i16, { 1, 1, 1, 2 } },
3193 { ISD::SETCC, MVT::v32i8, { 1, 1, 1, 2 } },
3194
3195 { ISD::SELECT, MVT::v4f64, { 2, 2, 1, 2 } }, // vblendvpd
3196 { ISD::SELECT, MVT::v8f32, { 2, 2, 1, 2 } }, // vblendvps
3197 { ISD::SELECT, MVT::v4i64, { 2, 2, 1, 2 } }, // pblendvb
3198 { ISD::SELECT, MVT::v8i32, { 2, 2, 1, 2 } }, // pblendvb
3199 { ISD::SELECT, MVT::v16i16, { 2, 2, 1, 2 } }, // pblendvb
3200 { ISD::SELECT, MVT::v32i8, { 2, 2, 1, 2 } }, // pblendvb
3201 };
3202
3203 static const CostKindTblEntry XOPCostTbl[] = {
3204 { ISD::SETCC, MVT::v4i64, { 4, 2, 5, 6 } },
3205 { ISD::SETCC, MVT::v2i64, { 1, 1, 1, 1 } },
3206 };
3207
3208 static const CostKindTblEntry AVX1CostTbl[] = {
3209 { ISD::SETCC, MVT::v4f64, { 2, 3, 1, 2 } },
3210 { ISD::SETCC, MVT::v2f64, { 1, 3, 1, 1 } },
3211 { ISD::SETCC, MVT::f64, { 1, 3, 1, 1 } },
3212 { ISD::SETCC, MVT::v8f32, { 2, 3, 1, 2 } },
3213 { ISD::SETCC, MVT::v4f32, { 1, 3, 1, 1 } },
3214 { ISD::SETCC, MVT::f32, { 1, 3, 1, 1 } },
3215
3216 // AVX1 does not support 8-wide integer compare.
3217 { ISD::SETCC, MVT::v4i64, { 4, 2, 5, 6 } },
3218 { ISD::SETCC, MVT::v8i32, { 4, 2, 5, 6 } },
3219 { ISD::SETCC, MVT::v16i16, { 4, 2, 5, 6 } },
3220 { ISD::SETCC, MVT::v32i8, { 4, 2, 5, 6 } },
3221
3222 { ISD::SELECT, MVT::v4f64, { 3, 3, 1, 2 } }, // vblendvpd
3223 { ISD::SELECT, MVT::v8f32, { 3, 3, 1, 2 } }, // vblendvps
3224 { ISD::SELECT, MVT::v4i64, { 3, 3, 1, 2 } }, // vblendvpd
3225 { ISD::SELECT, MVT::v8i32, { 3, 3, 1, 2 } }, // vblendvps
3226 { ISD::SELECT, MVT::v16i16, { 3, 3, 3, 3 } }, // vandps + vandnps + vorps
3227 { ISD::SELECT, MVT::v32i8, { 3, 3, 3, 3 } }, // vandps + vandnps + vorps
3228 };
3229
3230 static const CostKindTblEntry SSE42CostTbl[] = {
3231 { ISD::SETCC, MVT::v2i64, { 1, 2, 1, 2 } },
3232 };
3233
3234 static const CostKindTblEntry SSE41CostTbl[] = {
3235 { ISD::SETCC, MVT::v2f64, { 1, 5, 1, 1 } },
3236 { ISD::SETCC, MVT::v4f32, { 1, 5, 1, 1 } },
3237
3238 { ISD::SELECT, MVT::v2f64, { 2, 2, 1, 2 } }, // blendvpd
3239 { ISD::SELECT, MVT::f64, { 2, 2, 1, 2 } }, // blendvpd
3240 { ISD::SELECT, MVT::v4f32, { 2, 2, 1, 2 } }, // blendvps
3241 { ISD::SELECT, MVT::f32 , { 2, 2, 1, 2 } }, // blendvps
3242 { ISD::SELECT, MVT::v2i64, { 2, 2, 1, 2 } }, // pblendvb
3243 { ISD::SELECT, MVT::v4i32, { 2, 2, 1, 2 } }, // pblendvb
3244 { ISD::SELECT, MVT::v8i16, { 2, 2, 1, 2 } }, // pblendvb
3245 { ISD::SELECT, MVT::v16i8, { 2, 2, 1, 2 } }, // pblendvb
3246 };
3247
3248 static const CostKindTblEntry SSE2CostTbl[] = {
3249 { ISD::SETCC, MVT::v2f64, { 2, 5, 1, 1 } },
3250 { ISD::SETCC, MVT::f64, { 1, 5, 1, 1 } },
3251
3252 { ISD::SETCC, MVT::v2i64, { 5, 4, 5, 5 } }, // pcmpeqd/pcmpgtd expansion
3253 { ISD::SETCC, MVT::v4i32, { 1, 1, 1, 1 } },
3254 { ISD::SETCC, MVT::v8i16, { 1, 1, 1, 1 } },
3255 { ISD::SETCC, MVT::v16i8, { 1, 1, 1, 1 } },
3256
3257 { ISD::SELECT, MVT::v2f64, { 2, 2, 3, 3 } }, // andpd + andnpd + orpd
3258 { ISD::SELECT, MVT::f64, { 2, 2, 3, 3 } }, // andpd + andnpd + orpd
3259 { ISD::SELECT, MVT::v2i64, { 2, 2, 3, 3 } }, // pand + pandn + por
3260 { ISD::SELECT, MVT::v4i32, { 2, 2, 3, 3 } }, // pand + pandn + por
3261 { ISD::SELECT, MVT::v8i16, { 2, 2, 3, 3 } }, // pand + pandn + por
3262 { ISD::SELECT, MVT::v16i8, { 2, 2, 3, 3 } }, // pand + pandn + por
3263 };
3264
3265 static const CostKindTblEntry SSE1CostTbl[] = {
3266 { ISD::SETCC, MVT::v4f32, { 2, 5, 1, 1 } },
3267 { ISD::SETCC, MVT::f32, { 1, 5, 1, 1 } },
3268
3269 { ISD::SELECT, MVT::v4f32, { 2, 2, 3, 3 } }, // andps + andnps + orps
3270 { ISD::SELECT, MVT::f32, { 2, 2, 3, 3 } }, // andps + andnps + orps
3271 };
3272
3273 if (ST->useSLMArithCosts())
3274 if (const auto *Entry = CostTableLookup(SLMCostTbl, ISD, MTy))
3275 if (auto KindCost = Entry->Cost[CostKind])
3276 return LT.first * (ExtraCost + *KindCost);
3277
3278 if (ST->hasBWI())
3279 if (const auto *Entry = CostTableLookup(AVX512BWCostTbl, ISD, MTy))
3280 if (auto KindCost = Entry->Cost[CostKind])
3281 return LT.first * (ExtraCost + *KindCost);
3282
3283 if (ST->hasAVX512())
3284 if (const auto *Entry = CostTableLookup(AVX512CostTbl, ISD, MTy))
3285 if (auto KindCost = Entry->Cost[CostKind])
3286 return LT.first * (ExtraCost + *KindCost);
3287
3288 if (ST->hasAVX2())
3289 if (const auto *Entry = CostTableLookup(AVX2CostTbl, ISD, MTy))
3290 if (auto KindCost = Entry->Cost[CostKind])
3291 return LT.first * (ExtraCost + *KindCost);
3292
3293 if (ST->hasXOP())
3294 if (const auto *Entry = CostTableLookup(XOPCostTbl, ISD, MTy))
3295 if (auto KindCost = Entry->Cost[CostKind])
3296 return LT.first * (ExtraCost + *KindCost);
3297
3298 if (ST->hasAVX())
3299 if (const auto *Entry = CostTableLookup(AVX1CostTbl, ISD, MTy))
3300 if (auto KindCost = Entry->Cost[CostKind])
3301 return LT.first * (ExtraCost + *KindCost);
3302
3303 if (ST->hasSSE42())
3304 if (const auto *Entry = CostTableLookup(SSE42CostTbl, ISD, MTy))
3305 if (auto KindCost = Entry->Cost[CostKind])
3306 return LT.first * (ExtraCost + *KindCost);
3307
3308 if (ST->hasSSE41())
3309 if (const auto *Entry = CostTableLookup(SSE41CostTbl, ISD, MTy))
3310 if (auto KindCost = Entry->Cost[CostKind])
3311 return LT.first * (ExtraCost + *KindCost);
3312
3313 if (ST->hasSSE2())
3314 if (const auto *Entry = CostTableLookup(SSE2CostTbl, ISD, MTy))
3315 if (auto KindCost = Entry->Cost[CostKind])
3316 return LT.first * (ExtraCost + *KindCost);
3317
3318 if (ST->hasSSE1())
3319 if (const auto *Entry = CostTableLookup(SSE1CostTbl, ISD, MTy))
3320 if (auto KindCost = Entry->Cost[CostKind])
3321 return LT.first * (ExtraCost + *KindCost);
3322
3323 // Assume a 3cy latency for fp select ops.
3324 if (CostKind == TTI::TCK_Latency && Opcode == Instruction::Select)
3325 if (ValTy->getScalarType()->isFloatingPointTy())
3326 return 3;
3327
3328 return BaseT::getCmpSelInstrCost(Opcode, ValTy, CondTy, VecPred, CostKind, I);
3329}
3330
3331unsigned X86TTIImpl::getAtomicMemIntrinsicMaxElementSize() const { return 16; }
3332
3333InstructionCost
3334X86TTIImpl::getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA,
3335 TTI::TargetCostKind CostKind) {
3336 // Costs should match the codegen from:
3337 // BITREVERSE: llvm\test\CodeGen\X86\vector-bitreverse.ll
3338 // BSWAP: llvm\test\CodeGen\X86\bswap-vector.ll
3339 // CTLZ: llvm\test\CodeGen\X86\vector-lzcnt-*.ll
3340 // CTPOP: llvm\test\CodeGen\X86\vector-popcnt-*.ll
3341 // CTTZ: llvm\test\CodeGen\X86\vector-tzcnt-*.ll
3342
3343 // TODO: Overflow intrinsics (*ADDO, *SUBO, *MULO) with vector types are not
3344 // specialized in these tables yet.
3345 static const CostKindTblEntry AVX512VBMI2CostTbl[] = {
3346 { ISD::FSHL, MVT::v8i64, { 1, 1, 1, 1 } },
3347 { ISD::FSHL, MVT::v4i64, { 1, 1, 1, 1 } },
3348 { ISD::FSHL, MVT::v2i64, { 1, 1, 1, 1 } },
3349 { ISD::FSHL, MVT::v16i32, { 1, 1, 1, 1 } },
3350 { ISD::FSHL, MVT::v8i32, { 1, 1, 1, 1 } },
3351 { ISD::FSHL, MVT::v4i32, { 1, 1, 1, 1 } },
3352 { ISD::FSHL, MVT::v32i16, { 1, 1, 1, 1 } },
3353 { ISD::FSHL, MVT::v16i16, { 1, 1, 1, 1 } },
3354 { ISD::FSHL, MVT::v8i16, { 1, 1, 1, 1 } },
3355 { ISD::ROTL, MVT::v32i16, { 1, 1, 1, 1 } },
3356 { ISD::ROTL, MVT::v16i16, { 1, 1, 1, 1 } },
3357 { ISD::ROTL, MVT::v8i16, { 1, 1, 1, 1 } },
3358 { ISD::ROTR, MVT::v32i16, { 1, 1, 1, 1 } },
3359 { ISD::ROTR, MVT::v16i16, { 1, 1, 1, 1 } },
3360 { ISD::ROTR, MVT::v8i16, { 1, 1, 1, 1 } },
3361 };
3362 static const CostKindTblEntry AVX512BITALGCostTbl[] = {
3363 { ISD::CTPOP, MVT::v32i16, { 1, 1, 1, 1 } },
3364 { ISD::CTPOP, MVT::v64i8, { 1, 1, 1, 1 } },
3365 { ISD::CTPOP, MVT::v16i16, { 1, 1, 1, 1 } },
3366 { ISD::CTPOP, MVT::v32i8, { 1, 1, 1, 1 } },
3367 { ISD::CTPOP, MVT::v8i16, { 1, 1, 1, 1 } },
3368 { ISD::CTPOP, MVT::v16i8, { 1, 1, 1, 1 } },
3369 };
3370 static const CostKindTblEntry AVX512VPOPCNTDQCostTbl[] = {
3371 { ISD::CTPOP, MVT::v8i64, { 1, 1, 1, 1 } },
3372 { ISD::CTPOP, MVT::v16i32, { 1, 1, 1, 1 } },
3373 { ISD::CTPOP, MVT::v4i64, { 1, 1, 1, 1 } },
3374 { ISD::CTPOP, MVT::v8i32, { 1, 1, 1, 1 } },
3375 { ISD::CTPOP, MVT::v2i64, { 1, 1, 1, 1 } },
3376 { ISD::CTPOP, MVT::v4i32, { 1, 1, 1, 1 } },
3377 };
3378 static const CostKindTblEntry AVX512CDCostTbl[] = {
3379 { ISD::CTLZ, MVT::v8i64, { 1, 5, 1, 1 } },
3380 { ISD::CTLZ, MVT::v16i32, { 1, 5, 1, 1 } },
3381 { ISD::CTLZ, MVT::v32i16, { 18, 27, 23, 27 } },
3382 { ISD::CTLZ, MVT::v64i8, { 3, 16, 9, 11 } },
3383 { ISD::CTLZ, MVT::v4i64, { 1, 5, 1, 1 } },
3384 { ISD::CTLZ, MVT::v8i32, { 1, 5, 1, 1 } },
3385 { ISD::CTLZ, MVT::v16i16, { 8, 19, 11, 13 } },
3386 { ISD::CTLZ, MVT::v32i8, { 2, 11, 9, 10 } },
3387 { ISD::CTLZ, MVT::v2i64, { 1, 5, 1, 1 } },
3388 { ISD::CTLZ, MVT::v4i32, { 1, 5, 1, 1 } },
3389 { ISD::CTLZ, MVT::v8i16, { 3, 15, 4, 6 } },
3390 { ISD::CTLZ, MVT::v16i8, { 2, 10, 9, 10 } },
3391
3392 { ISD::CTTZ, MVT::v8i64, { 2, 8, 6, 7 } },
3393 { ISD::CTTZ, MVT::v16i32, { 2, 8, 6, 7 } },
3394 { ISD::CTTZ, MVT::v4i64, { 1, 8, 6, 6 } },
3395 { ISD::CTTZ, MVT::v8i32, { 1, 8, 6, 6 } },
3396 { ISD::CTTZ, MVT::v2i64, { 1, 8, 6, 6 } },
3397 { ISD::CTTZ, MVT::v4i32, { 1, 8, 6, 6 } },
3398 };
3399 static const CostKindTblEntry AVX512BWCostTbl[] = {
3400 { ISD::ABS, MVT::v32i16, { 1, 1, 1, 1 } },
3401 { ISD::ABS, MVT::v64i8, { 1, 1, 1, 1 } },
3402 { ISD::BITREVERSE, MVT::v2i64, { 3, 10, 10, 11 } },
3403 { ISD::BITREVERSE, MVT::v4i64, { 3, 11, 10, 11 } },
3404 { ISD::BITREVERSE, MVT::v8i64, { 3, 12, 10, 14 } },
3405 { ISD::BITREVERSE, MVT::v4i32, { 3, 10, 10, 11 } },
3406 { ISD::BITREVERSE, MVT::v8i32, { 3, 11, 10, 11 } },
3407 { ISD::BITREVERSE, MVT::v16i32, { 3, 12, 10, 14 } },
3408 { ISD::BITREVERSE, MVT::v8i16, { 3, 10, 10, 11 } },
3409 { ISD::BITREVERSE, MVT::v16i16, { 3, 11, 10, 11 } },
3410 { ISD::BITREVERSE, MVT::v32i16, { 3, 12, 10, 14 } },
3411 { ISD::BITREVERSE, MVT::v16i8, { 2, 5, 9, 9 } },
3412 { ISD::BITREVERSE, MVT::v32i8, { 2, 5, 9, 9 } },
3413 { ISD::BITREVERSE, MVT::v64i8, { 2, 5, 9, 12 } },
3414 { ISD::BSWAP, MVT::v2i64, { 1, 1, 1, 2 } },
3415 { ISD::BSWAP, MVT::v4i64, { 1, 1, 1, 2 } },
3416 { ISD::BSWAP, MVT::v8i64, { 1, 1, 1, 2 } },
3417 { ISD::BSWAP, MVT::v4i32, { 1, 1, 1, 2 } },
3418 { ISD::BSWAP, MVT::v8i32, { 1, 1, 1, 2 } },
3419 { ISD::BSWAP, MVT::v16i32, { 1, 1, 1, 2 } },
3420 { ISD::BSWAP, MVT::v8i16, { 1, 1, 1, 2 } },
3421 { ISD::BSWAP, MVT::v16i16, { 1, 1, 1, 2 } },
3422 { ISD::BSWAP, MVT::v32i16, { 1, 1, 1, 2 } },
3423 { ISD::CTLZ, MVT::v8i64, { 8, 22, 23, 23 } },
3424 { ISD::CTLZ, MVT::v16i32, { 8, 23, 25, 25 } },
3425 { ISD::CTLZ, MVT::v32i16, { 4, 15, 15, 16 } },
3426 { ISD::CTLZ, MVT::v64i8, { 3, 12, 10, 9 } },
3427 { ISD::CTPOP, MVT::v2i64, { 3, 7, 10, 10 } },
3428 { ISD::CTPOP, MVT::v4i64, { 3, 7, 10, 10 } },
3429 { ISD::CTPOP, MVT::v8i64, { 3, 8, 10, 12 } },
3430 { ISD::CTPOP, MVT::v4i32, { 7, 11, 14, 14 } },
3431 { ISD::CTPOP, MVT::v8i32, { 7, 11, 14, 14 } },
3432 { ISD::CTPOP, MVT::v16i32, { 7, 12, 14, 16 } },
3433 { ISD::CTPOP, MVT::v8i16, { 2, 7, 11, 11 } },
3434 { ISD::CTPOP, MVT::v16i16, { 2, 7, 11, 11 } },
3435 { ISD::CTPOP, MVT::v32i16, { 3, 7, 11, 13 } },
3436 { ISD::CTPOP, MVT::v16i8, { 2, 4, 8, 8 } },
3437 { ISD::CTPOP, MVT::v32i8, { 2, 4, 8, 8 } },
3438 { ISD::CTPOP, MVT::v64i8, { 2, 5, 8, 10 } },
3439 { ISD::CTTZ, MVT::v8i16, { 3, 9, 14, 14 } },
3440 { ISD::CTTZ, MVT::v16i16, { 3, 9, 14, 14 } },
3441 { ISD::CTTZ, MVT::v32i16, { 3, 10, 14, 16 } },
3442 { ISD::CTTZ, MVT::v16i8, { 2, 6, 11, 11 } },
3443 { ISD::CTTZ, MVT::v32i8, { 2, 6, 11, 11 } },
3444 { ISD::CTTZ, MVT::v64i8, { 3, 7, 11, 13 } },
3445 { ISD::ROTL, MVT::v32i16, { 2, 8, 6, 8 } },
3446 { ISD::ROTL, MVT::v16i16, { 2, 8, 6, 7 } },
3447 { ISD::ROTL, MVT::v8i16, { 2, 7, 6, 7 } },
3448 { ISD::ROTL, MVT::v64i8, { 5, 6, 11, 12 } },
3449 { ISD::ROTL, MVT::v32i8, { 5, 15, 7, 10 } },
3450 { ISD::ROTL, MVT::v16i8, { 5, 15, 7, 10 } },
3451 { ISD::ROTR, MVT::v32i16, { 2, 8, 6, 8 } },
3452 { ISD::ROTR, MVT::v16i16, { 2, 8, 6, 7 } },
3453 { ISD::ROTR, MVT::v8i16, { 2, 7, 6, 7 } },
3454 { ISD::ROTR, MVT::v64i8, { 5, 6, 12, 14 } },
3455 { ISD::ROTR, MVT::v32i8, { 5, 14, 6, 9 } },
3456 { ISD::ROTR, MVT::v16i8, { 5, 14, 6, 9 } },
3457 { ISD::SADDSAT, MVT::v32i16, { 1 } },
3458 { ISD::SADDSAT, MVT::v64i8, { 1 } },
3459 { ISD::SMAX, MVT::v32i16, { 1, 1, 1, 1 } },
3460 { ISD::SMAX, MVT::v64i8, { 1, 1, 1, 1 } },
3461 { ISD::SMIN, MVT::v32i16, { 1, 1, 1, 1 } },
3462 { ISD::SMIN, MVT::v64i8, { 1, 1, 1, 1 } },
3463 { ISD::SSUBSAT, MVT::v32i16, { 1 } },
3464 { ISD::SSUBSAT, MVT::v64i8, { 1 } },
3465 { ISD::UADDSAT, MVT::v32i16, { 1 } },
3466 { ISD::UADDSAT, MVT::v64i8, { 1 } },
3467 { ISD::UMAX, MVT::v32i16, { 1, 1, 1, 1 } },
3468 { ISD::UMAX, MVT::v64i8, { 1, 1, 1, 1 } },
3469 { ISD::UMIN, MVT::v32i16, { 1, 1, 1, 1 } },
3470 { ISD::UMIN, MVT::v64i8, { 1, 1, 1, 1 } },
3471 { ISD::USUBSAT, MVT::v32i16, { 1 } },
3472 { ISD::USUBSAT, MVT::v64i8, { 1 } },
3473 };
3474 static const CostKindTblEntry AVX512CostTbl[] = {
3475 { ISD::ABS, MVT::v8i64, { 1, 1, 1, 1 } },
3476 { ISD::ABS, MVT::v4i64, { 1, 1, 1, 1 } },
3477 { ISD::ABS, MVT::v2i64, { 1, 1, 1, 1 } },
3478 { ISD::ABS, MVT::v16i32, { 1, 1, 1, 1 } },
3479 { ISD::ABS, MVT::v8i32, { 1, 1, 1, 1 } },
3480 { ISD::ABS, MVT::v32i16, { 2, 7, 4, 4 } },
3481 { ISD::ABS, MVT::v16i16, { 1, 1, 1, 1 } },
3482 { ISD::ABS, MVT::v64i8, { 2, 7, 4, 4 } },
3483 { ISD::ABS, MVT::v32i8, { 1, 1, 1, 1 } },
3484 { ISD::BITREVERSE, MVT::v8i64, { 9, 13, 20, 20 } },
3485 { ISD::BITREVERSE, MVT::v16i32, { 9, 13, 20, 20 } },
3486 { ISD::BITREVERSE, MVT::v32i16, { 9, 13, 20, 20 } },
3487 { ISD::BITREVERSE, MVT::v64i8, { 6, 11, 17, 17 } },
3488 { ISD::BSWAP, MVT::v8i64, { 4, 7, 5, 5 } },
3489 { ISD::BSWAP, MVT::v16i32, { 4, 7, 5, 5 } },
3490 { ISD::BSWAP, MVT::v32i16, { 4, 7, 5, 5 } },
3491 { ISD::CTLZ, MVT::v8i64, { 10, 28, 32, 32 } },
3492 { ISD::CTLZ, MVT::v16i32, { 12, 30, 38, 38 } },
3493 { ISD::CTLZ, MVT::v32i16, { 8, 15, 29, 29 } },
3494 { ISD::CTLZ, MVT::v64i8, { 6, 11, 19, 19 } },
3495 { ISD::CTPOP, MVT::v8i64, { 16, 16, 19, 19 } },
3496 { ISD::CTPOP, MVT::v16i32, { 24, 19, 27, 27 } },
3497 { ISD::CTPOP, MVT::v32i16, { 18, 15, 22, 22 } },
3498 { ISD::CTPOP, MVT::v64i8, { 12, 11, 16, 16 } },
3499 { ISD::CTTZ, MVT::v8i64, { 2, 8, 6, 7 } },
3500 { ISD::CTTZ, MVT::v16i32, { 2, 8, 6, 7 } },
3501 { ISD::CTTZ, MVT::v32i16, { 7, 17, 27, 27 } },
3502 { ISD::CTTZ, MVT::v64i8, { 6, 13, 21, 21 } },
3503 { ISD::ROTL, MVT::v8i64, { 1, 1, 1, 1 } },
3504 { ISD::ROTL, MVT::v4i64, { 1, 1, 1, 1 } },
3505 { ISD::ROTL, MVT::v2i64, { 1, 1, 1, 1 } },
3506 { ISD::ROTL, MVT::v16i32, { 1, 1, 1, 1 } },
3507 { ISD::ROTL, MVT::v8i32, { 1, 1, 1, 1 } },
3508 { ISD::ROTL, MVT::v4i32, { 1, 1, 1, 1 } },
3509 { ISD::ROTR, MVT::v8i64, { 1, 1, 1, 1 } },
3510 { ISD::ROTR, MVT::v4i64, { 1, 1, 1, 1 } },
3511 { ISD::ROTR, MVT::v2i64, { 1, 1, 1, 1 } },
3512 { ISD::ROTR, MVT::v16i32, { 1, 1, 1, 1 } },
3513 { ISD::ROTR, MVT::v8i32, { 1, 1, 1, 1 } },
3514 { ISD::ROTR, MVT::v4i32, { 1, 1, 1, 1 } },
3515 { ISD::SMAX, MVT::v8i64, { 1, 3, 1, 1 } },
3516 { ISD::SMAX, MVT::v16i32, { 1, 1, 1, 1 } },
3517 { ISD::SMAX, MVT::v32i16, { 3, 7, 5, 5 } },
3518 { ISD::SMAX, MVT::v64i8, { 3, 7, 5, 5 } },
3519 { ISD::SMAX, MVT::v4i64, { 1, 3, 1, 1 } },
3520 { ISD::SMAX, MVT::v2i64, { 1, 3, 1, 1 } },
3521 { ISD::SMIN, MVT::v8i64, { 1, 3, 1, 1 } },
3522 { ISD::SMIN, MVT::v16i32, { 1, 1, 1, 1 } },
3523 { ISD::SMIN, MVT::v32i16, { 3, 7, 5, 5 } },
3524 { ISD::SMIN, MVT::v64i8, { 3, 7, 5, 5 } },
3525 { ISD::SMIN, MVT::v4i64, { 1, 3, 1, 1 } },
3526 { ISD::SMIN, MVT::v2i64, { 1, 3, 1, 1 } },
3527 { ISD::UMAX, MVT::v8i64, { 1, 3, 1, 1 } },
3528 { ISD::UMAX, MVT::v16i32, { 1, 1, 1, 1 } },
3529 { ISD::UMAX, MVT::v32i16, { 3, 7, 5, 5 } },
3530 { ISD::UMAX, MVT::v64i8, { 3, 7, 5, 5 } },
3531 { ISD::UMAX, MVT::v4i64, { 1, 3, 1, 1 } },
3532 { ISD::UMAX, MVT::v2i64, { 1, 3, 1, 1 } },
3533 { ISD::UMIN, MVT::v8i64, { 1, 3, 1, 1 } },
3534 { ISD::UMIN, MVT::v16i32, { 1, 1, 1, 1 } },
3535 { ISD::UMIN, MVT::v32i16, { 3, 7, 5, 5 } },
3536 { ISD::UMIN, MVT::v64i8, { 3, 7, 5, 5 } },
3537 { ISD::UMIN, MVT::v4i64, { 1, 3, 1, 1 } },
3538 { ISD::UMIN, MVT::v2i64, { 1, 3, 1, 1 } },
3539 { ISD::USUBSAT, MVT::v16i32, { 2 } }, // pmaxud + psubd
3540 { ISD::USUBSAT, MVT::v2i64, { 2 } }, // pmaxuq + psubq
3541 { ISD::USUBSAT, MVT::v4i64, { 2 } }, // pmaxuq + psubq
3542 { ISD::USUBSAT, MVT::v8i64, { 2 } }, // pmaxuq + psubq
3543 { ISD::UADDSAT, MVT::v16i32, { 3 } }, // not + pminud + paddd
3544 { ISD::UADDSAT, MVT::v2i64, { 3 } }, // not + pminuq + paddq
3545 { ISD::UADDSAT, MVT::v4i64, { 3 } }, // not + pminuq + paddq
3546 { ISD::UADDSAT, MVT::v8i64, { 3 } }, // not + pminuq + paddq
3547 { ISD::SADDSAT, MVT::v32i16, { 2 } },
3548 { ISD::SADDSAT, MVT::v64i8, { 2 } },
3549 { ISD::SSUBSAT, MVT::v32i16, { 2 } },
3550 { ISD::SSUBSAT, MVT::v64i8, { 2 } },
3551 { ISD::UADDSAT, MVT::v32i16, { 2 } },
3552 { ISD::UADDSAT, MVT::v64i8, { 2 } },
3553 { ISD::USUBSAT, MVT::v32i16, { 2 } },
3554 { ISD::USUBSAT, MVT::v64i8, { 2 } },
3555 { ISD::FMAXNUM, MVT::f32, { 2, 2, 3, 3 } },
3556 { ISD::FMAXNUM, MVT::v4f32, { 1, 1, 3, 3 } },
3557 { ISD::FMAXNUM, MVT::v8f32, { 2, 2, 3, 3 } },
3558 { ISD::FMAXNUM, MVT::v16f32, { 4, 4, 3, 3 } },
3559 { ISD::FMAXNUM, MVT::f64, { 2, 2, 3, 3 } },
3560 { ISD::FMAXNUM, MVT::v2f64, { 1, 1, 3, 3 } },
3561 { ISD::FMAXNUM, MVT::v4f64, { 2, 2, 3, 3 } },
3562 { ISD::FMAXNUM, MVT::v8f64, { 3, 3, 3, 3 } },
3563 { ISD::FSQRT, MVT::f32, { 3, 12, 1, 1 } }, // Skylake from http://www.agner.org/
3564 { ISD::FSQRT, MVT::v4f32, { 3, 12, 1, 1 } }, // Skylake from http://www.agner.org/
3565 { ISD::FSQRT, MVT::v8f32, { 6, 12, 1, 1 } }, // Skylake from http://www.agner.org/
3566 { ISD::FSQRT, MVT::v16f32, { 12, 20, 1, 3 } }, // Skylake from http://www.agner.org/
3567 { ISD::FSQRT, MVT::f64, { 6, 18, 1, 1 } }, // Skylake from http://www.agner.org/
3568 { ISD::FSQRT, MVT::v2f64, { 6, 18, 1, 1 } }, // Skylake from http://www.agner.org/
3569 { ISD::FSQRT, MVT::v4f64, { 12, 18, 1, 1 } }, // Skylake from http://www.agner.org/
3570 { ISD::FSQRT, MVT::v8f64, { 24, 32, 1, 3 } }, // Skylake from http://www.agner.org/
3571 };
3572 static const CostKindTblEntry XOPCostTbl[] = {
3573 { ISD::BITREVERSE, MVT::v4i64, { 3, 6, 5, 6 } },
3574 { ISD::BITREVERSE, MVT::v8i32, { 3, 6, 5, 6 } },
3575 { ISD::BITREVERSE, MVT::v16i16, { 3, 6, 5, 6 } },
3576 { ISD::BITREVERSE, MVT::v32i8, { 3, 6, 5, 6 } },
3577 { ISD::BITREVERSE, MVT::v2i64, { 2, 7, 1, 1 } },
3578 { ISD::BITREVERSE, MVT::v4i32, { 2, 7, 1, 1 } },
3579 { ISD::BITREVERSE, MVT::v8i16, { 2, 7, 1, 1 } },
3580 { ISD::BITREVERSE, MVT::v16i8, { 2, 7, 1, 1 } },
3581 { ISD::BITREVERSE, MVT::i64, { 2, 2, 3, 4 } },
3582 { ISD::BITREVERSE, MVT::i32, { 2, 2, 3, 4 } },
3583 { ISD::BITREVERSE, MVT::i16, { 2, 2, 3, 4 } },
3584 { ISD::BITREVERSE, MVT::i8, { 2, 2, 3, 4 } },
3585 // XOP: ROTL = VPROT(X,Y), ROTR = VPROT(X,SUB(0,Y))
3586 { ISD::ROTL, MVT::v4i64, { 4, 7, 5, 6 } },
3587 { ISD::ROTL, MVT::v8i32, { 4, 7, 5, 6 } },
3588 { ISD::ROTL, MVT::v16i16, { 4, 7, 5, 6 } },
3589 { ISD::ROTL, MVT::v32i8, { 4, 7, 5, 6 } },
3590 { ISD::ROTL, MVT::v2i64, { 1, 3, 1, 1 } },
3591 { ISD::ROTL, MVT::v4i32, { 1, 3, 1, 1 } },
3592 { ISD::ROTL, MVT::v8i16, { 1, 3, 1, 1 } },
3593 { ISD::ROTL, MVT::v16i8, { 1, 3, 1, 1 } },
3594 { ISD::ROTR, MVT::v4i64, { 4, 7, 8, 9 } },
3595 { ISD::ROTR, MVT::v8i32, { 4, 7, 8, 9 } },
3596 { ISD::ROTR, MVT::v16i16, { 4, 7, 8, 9 } },
3597 { ISD::ROTR, MVT::v32i8, { 4, 7, 8, 9 } },
3598 { ISD::ROTR, MVT::v2i64, { 1, 3, 3, 3 } },
3599 { ISD::ROTR, MVT::v4i32, { 1, 3, 3, 3 } },
3600 { ISD::ROTR, MVT::v8i16, { 1, 3, 3, 3 } },
3601 { ISD::ROTR, MVT::v16i8, { 1, 3, 3, 3 } }
3602 };
3603 static const CostKindTblEntry AVX2CostTbl[] = {
3604 { ISD::ABS, MVT::v2i64, { 2, 4, 3, 5 } }, // VBLENDVPD(X,VPSUBQ(0,X),X)
3605 { ISD::ABS, MVT::v4i64, { 2, 4, 3, 5 } }, // VBLENDVPD(X,VPSUBQ(0,X),X)
3606 { ISD::ABS, MVT::v4i32, { 1, 1, 1, 1 } },
3607 { ISD::ABS, MVT::v8i32, { 1, 1, 1, 2 } },
3608 { ISD::ABS, MVT::v8i16, { 1, 1, 1, 1 } },
3609 { ISD::ABS, MVT::v16i16, { 1, 1, 1, 2 } },
3610 { ISD::ABS, MVT::v16i8, { 1, 1, 1, 1 } },
3611 { ISD::ABS, MVT::v32i8, { 1, 1, 1, 2 } },
3612 { ISD::BITREVERSE, MVT::v2i64, { 3, 11, 10, 11 } },
3613 { ISD::BITREVERSE, MVT::v4i64, { 5, 11, 10, 17 } },
3614 { ISD::BITREVERSE, MVT::v4i32, { 3, 11, 10, 11 } },
3615 { ISD::BITREVERSE, MVT::v8i32, { 5, 11, 10, 17 } },
3616 { ISD::BITREVERSE, MVT::v8i16, { 3, 11, 10, 11 } },
3617 { ISD::BITREVERSE, MVT::v16i16, { 5, 11, 10, 17 } },
3618 { ISD::BITREVERSE, MVT::v16i8, { 3, 6, 9, 9 } },
3619 { ISD::BITREVERSE, MVT::v32i8, { 4, 5, 9, 15 } },
3620 { ISD::BSWAP, MVT::v2i64, { 1, 2, 1, 2 } },
3621 { ISD::BSWAP, MVT::v4i64, { 1, 3, 1, 2 } },
3622 { ISD::BSWAP, MVT::v4i32, { 1, 2, 1, 2 } },
3623 { ISD::BSWAP, MVT::v8i32, { 1, 3, 1, 2 } },
3624 { ISD::BSWAP, MVT::v8i16, { 1, 2, 1, 2 } },
3625 { ISD::BSWAP, MVT::v16i16, { 1, 3, 1, 2 } },
3626 { ISD::CTLZ, MVT::v2i64, { 7, 18, 24, 25 } },
3627 { ISD::CTLZ, MVT::v4i64, { 14, 18, 24, 44 } },
3628 { ISD::CTLZ, MVT::v4i32, { 5, 16, 19, 20 } },
3629 { ISD::CTLZ, MVT::v8i32, { 10, 16, 19, 34 } },
3630 { ISD::CTLZ, MVT::v8i16, { 4, 13, 14, 15 } },
3631 { ISD::CTLZ, MVT::v16i16, { 6, 14, 14, 24 } },
3632 { ISD::CTLZ, MVT::v16i8, { 3, 12, 9, 10 } },
3633 { ISD::CTLZ, MVT::v32i8, { 4, 12, 9, 14 } },
3634 { ISD::CTPOP, MVT::v2i64, { 3, 9, 10, 10 } },
3635 { ISD::CTPOP, MVT::v4i64, { 4, 9, 10, 14 } },
3636 { ISD::CTPOP, MVT::v4i32, { 7, 12, 14, 14 } },
3637 { ISD::CTPOP, MVT::v8i32, { 7, 12, 14, 18 } },
3638 { ISD::CTPOP, MVT::v8i16, { 3, 7, 11, 11 } },
3639 { ISD::CTPOP, MVT::v16i16, { 6, 8, 11, 18 } },
3640 { ISD::CTPOP, MVT::v16i8, { 2, 5, 8, 8 } },
3641 { ISD::CTPOP, MVT::v32i8, { 3, 5, 8, 12 } },
3642 { ISD::CTTZ, MVT::v2i64, { 4, 11, 13, 13 } },
3643 { ISD::CTTZ, MVT::v4i64, { 5, 11, 13, 20 } },
3644 { ISD::CTTZ, MVT::v4i32, { 7, 14, 17, 17 } },
3645 { ISD::CTTZ, MVT::v8i32, { 7, 15, 17, 24 } },
3646 { ISD::CTTZ, MVT::v8i16, { 4, 9, 14, 14 } },
3647 { ISD::CTTZ, MVT::v16i16, { 6, 9, 14, 24 } },
3648 { ISD::CTTZ, MVT::v16i8, { 3, 7, 11, 11 } },
3649 { ISD::CTTZ, MVT::v32i8, { 5, 7, 11, 18 } },
3650 { ISD::SADDSAT, MVT::v16i16, { 1 } },
3651 { ISD::SADDSAT, MVT::v32i8, { 1 } },
3652 { ISD::SMAX, MVT::v2i64, { 2, 7, 2, 3 } },
3653 { ISD::SMAX, MVT::v4i64, { 2, 7, 2, 3 } },
3654 { ISD::SMAX, MVT::v8i32, { 1, 1, 1, 2 } },
3655 { ISD::SMAX, MVT::v16i16, { 1, 1, 1, 2 } },
3656 { ISD::SMAX, MVT::v32i8, { 1, 1, 1, 2 } },
3657 { ISD::SMIN, MVT::v2i64, { 2, 7, 2, 3 } },
3658 { ISD::SMIN, MVT::v4i64, { 2, 7, 2, 3 } },
3659 { ISD::SMIN, MVT::v8i32, { 1, 1, 1, 2 } },
3660 { ISD::SMIN, MVT::v16i16, { 1, 1, 1, 2 } },
3661 { ISD::SMIN, MVT::v32i8, { 1, 1, 1, 2 } },
3662 { ISD::SSUBSAT, MVT::v16i16, { 1 } },
3663 { ISD::SSUBSAT, MVT::v32i8, { 1 } },
3664 { ISD::UADDSAT, MVT::v16i16, { 1 } },
3665 { ISD::UADDSAT, MVT::v32i8, { 1 } },
3666 { ISD::UADDSAT, MVT::v8i32, { 3 } }, // not + pminud + paddd
3667 { ISD::UMAX, MVT::v2i64, { 2, 8, 5, 6 } },
3668 { ISD::UMAX, MVT::v4i64, { 2, 8, 5, 8 } },
3669 { ISD::UMAX, MVT::v8i32, { 1, 1, 1, 2 } },
3670 { ISD::UMAX, MVT::v16i16, { 1, 1, 1, 2 } },
3671 { ISD::UMAX, MVT::v32i8, { 1, 1, 1, 2 } },
3672 { ISD::UMIN, MVT::v2i64, { 2, 8, 5, 6 } },
3673 { ISD::UMIN, MVT::v4i64, { 2, 8, 5, 8 } },
3674 { ISD::UMIN, MVT::v8i32, { 1, 1, 1, 2 } },
3675 { ISD::UMIN, MVT::v16i16, { 1, 1, 1, 2 } },
3676 { ISD::UMIN, MVT::v32i8, { 1, 1, 1, 2 } },
3677 { ISD::USUBSAT, MVT::v16i16, { 1 } },
3678 { ISD::USUBSAT, MVT::v32i8, { 1 } },
3679 { ISD::USUBSAT, MVT::v8i32, { 2 } }, // pmaxud + psubd
3680 { ISD::FMAXNUM, MVT::f32, { 2, 7, 3, 5 } }, // MAXSS + CMPUNORDSS + BLENDVPS
3681 { ISD::FMAXNUM, MVT::v4f32, { 2, 7, 3, 5 } }, // MAXPS + CMPUNORDPS + BLENDVPS
3682 { ISD::FMAXNUM, MVT::v8f32, { 3, 7, 3, 6 } }, // MAXPS + CMPUNORDPS + BLENDVPS
3683 { ISD::FMAXNUM, MVT::f64, { 2, 7, 3, 5 } }, // MAXSD + CMPUNORDSD + BLENDVPD
3684 { ISD::FMAXNUM, MVT::v2f64, { 2, 7, 3, 5 } }, // MAXPD + CMPUNORDPD + BLENDVPD
3685 { ISD::FMAXNUM, MVT::v4f64, { 3, 7, 3, 6 } }, // MAXPD + CMPUNORDPD + BLENDVPD
3686 { ISD::FSQRT, MVT::f32, { 7, 15, 1, 1 } }, // vsqrtss
3687 { ISD::FSQRT, MVT::v4f32, { 7, 15, 1, 1 } }, // vsqrtps
3688 { ISD::FSQRT, MVT::v8f32, { 14, 21, 1, 3 } }, // vsqrtps
3689 { ISD::FSQRT, MVT::f64, { 14, 21, 1, 1 } }, // vsqrtsd
3690 { ISD::FSQRT, MVT::v2f64, { 14, 21, 1, 1 } }, // vsqrtpd
3691 { ISD::FSQRT, MVT::v4f64, { 28, 35, 1, 3 } }, // vsqrtpd
3692 };
3693 static const CostKindTblEntry AVX1CostTbl[] = {
3694 { ISD::ABS, MVT::v4i64, { 6, 8, 6, 12 } }, // VBLENDVPD(X,VPSUBQ(0,X),X)
3695 { ISD::ABS, MVT::v8i32, { 3, 6, 4, 5 } },
3696 { ISD::ABS, MVT::v16i16, { 3, 6, 4, 5 } },
3697 { ISD::ABS, MVT::v32i8, { 3, 6, 4, 5 } },
3698 { ISD::BITREVERSE, MVT::v4i64, { 17, 20, 20, 33 } }, // 2 x 128-bit Op + extract/insert
3699 { ISD::BITREVERSE, MVT::v2i64, { 8, 13, 10, 16 } },
3700 { ISD::BITREVERSE, MVT::v8i32, { 17, 20, 20, 33 } }, // 2 x 128-bit Op + extract/insert
3701 { ISD::BITREVERSE, MVT::v4i32, { 8, 13, 10, 16 } },
3702 { ISD::BITREVERSE, MVT::v16i16, { 17, 20, 20, 33 } }, // 2 x 128-bit Op + extract/insert
3703 { ISD::BITREVERSE, MVT::v8i16, { 8, 13, 10, 16 } },
3704 { ISD::BITREVERSE, MVT::v32i8, { 13, 15, 17, 26 } }, // 2 x 128-bit Op + extract/insert
3705 { ISD::BITREVERSE, MVT::v16i8, { 7, 7, 9, 13 } },
3706 { ISD::BSWAP, MVT::v4i64, { 5, 7, 5, 10 } },
3707 { ISD::BSWAP, MVT::v2i64, { 2, 3, 1, 3 } },
3708 { ISD::BSWAP, MVT::v8i32, { 5, 7, 5, 10 } },
3709 { ISD::BSWAP, MVT::v4i32, { 2, 3, 1, 3 } },
3710 { ISD::BSWAP, MVT::v16i16, { 5, 6, 5, 10 } },
3711 { ISD::BSWAP, MVT::v8i16, { 2, 2, 1, 3 } },
3712 { ISD::CTLZ, MVT::v4i64, { 29, 33, 49, 58 } }, // 2 x 128-bit Op + extract/insert
3713 { ISD::CTLZ, MVT::v2i64, { 14, 24, 24, 28 } },
3714 { ISD::CTLZ, MVT::v8i32, { 24, 28, 39, 48 } }, // 2 x 128-bit Op + extract/insert
3715 { ISD::CTLZ, MVT::v4i32, { 12, 20, 19, 23 } },
3716 { ISD::CTLZ, MVT::v16i16, { 19, 22, 29, 38 } }, // 2 x 128-bit Op + extract/insert
3717 { ISD::CTLZ, MVT::v8i16, { 9, 16, 14, 18 } },
3718 { ISD::CTLZ, MVT::v32i8, { 14, 15, 19, 28 } }, // 2 x 128-bit Op + extract/insert
3719 { ISD::CTLZ, MVT::v16i8, { 7, 12, 9, 13 } },
3720 { ISD::CTPOP, MVT::v4i64, { 14, 18, 19, 28 } }, // 2 x 128-bit Op + extract/insert
3721 { ISD::CTPOP, MVT::v2i64, { 7, 14, 10, 14 } },
3722 { ISD::CTPOP, MVT::v8i32, { 18, 24, 27, 36 } }, // 2 x 128-bit Op + extract/insert
3723 { ISD::CTPOP, MVT::v4i32, { 9, 20, 14, 18 } },
3724 { ISD::CTPOP, MVT::v16i16, { 16, 21, 22, 31 } }, // 2 x 128-bit Op + extract/insert
3725 { ISD::CTPOP, MVT::v8i16, { 8, 18, 11, 15 } },
3726 { ISD::CTPOP, MVT::v32i8, { 13, 15, 16, 25 } }, // 2 x 128-bit Op + extract/insert
3727 { ISD::CTPOP, MVT::v16i8, { 6, 12, 8, 12 } },
3728 { ISD::CTTZ, MVT::v4i64, { 17, 22, 24, 33 } }, // 2 x 128-bit Op + extract/insert
3729 { ISD::CTTZ, MVT::v2i64, { 9, 19, 13, 17 } },
3730 { ISD::CTTZ, MVT::v8i32, { 21, 27, 32, 41 } }, // 2 x 128-bit Op + extract/insert
3731 { ISD::CTTZ, MVT::v4i32, { 11, 24, 17, 21 } },
3732 { ISD::CTTZ, MVT::v16i16, { 18, 24, 27, 36 } }, // 2 x 128-bit Op + extract/insert
3733 { ISD::CTTZ, MVT::v8i16, { 9, 21, 14, 18 } },
3734 { ISD::CTTZ, MVT::v32i8, { 15, 18, 21, 30 } }, // 2 x 128-bit Op + extract/insert
3735 { ISD::CTTZ, MVT::v16i8, { 8, 16, 11, 15 } },
3736 { ISD::SADDSAT, MVT::v16i16, { 4 } }, // 2 x 128-bit Op + extract/insert
3737 { ISD::SADDSAT, MVT::v32i8, { 4 } }, // 2 x 128-bit Op + extract/insert
3738 { ISD::SMAX, MVT::v4i64, { 6, 9, 6, 12 } }, // 2 x 128-bit Op + extract/insert
3739 { ISD::SMAX, MVT::v2i64, { 3, 7, 2, 4 } },
3740 { ISD::SMAX, MVT::v8i32, { 4, 6, 5, 6 } }, // 2 x 128-bit Op + extract/insert
3741 { ISD::SMAX, MVT::v16i16, { 4, 6, 5, 6 } }, // 2 x 128-bit Op + extract/insert
3742 { ISD::SMAX, MVT::v32i8, { 4, 6, 5, 6 } }, // 2 x 128-bit Op + extract/insert
3743 { ISD::SMIN, MVT::v4i64, { 6, 9, 6, 12 } }, // 2 x 128-bit Op + extract/insert
3744 { ISD::SMIN, MVT::v2i64, { 3, 7, 2, 3 } },
3745 { ISD::SMIN, MVT::v8i32, { 4, 6, 5, 6 } }, // 2 x 128-bit Op + extract/insert
3746 { ISD::SMIN, MVT::v16i16, { 4, 6, 5, 6 } }, // 2 x 128-bit Op + extract/insert
3747 { ISD::SMIN, MVT::v32i8, { 4, 6, 5, 6 } }, // 2 x 128-bit Op + extract/insert
3748 { ISD::SSUBSAT, MVT::v16i16, { 4 } }, // 2 x 128-bit Op + extract/insert
3749 { ISD::SSUBSAT, MVT::v32i8, { 4 } }, // 2 x 128-bit Op + extract/insert
3750 { ISD::UADDSAT, MVT::v16i16, { 4 } }, // 2 x 128-bit Op + extract/insert
3751 { ISD::UADDSAT, MVT::v32i8, { 4 } }, // 2 x 128-bit Op + extract/insert
3752 { ISD::UADDSAT, MVT::v8i32, { 8 } }, // 2 x 128-bit Op + extract/insert
3753 { ISD::UMAX, MVT::v4i64, { 9, 10, 11, 17 } }, // 2 x 128-bit Op + extract/insert
3754 { ISD::UMAX, MVT::v2i64, { 4, 8, 5, 7 } },
3755 { ISD::UMAX, MVT::v8i32, { 4, 6, 5, 6 } }, // 2 x 128-bit Op + extract/insert
3756 { ISD::UMAX, MVT::v16i16, { 4, 6, 5, 6 } }, // 2 x 128-bit Op + extract/insert
3757 { ISD::UMAX, MVT::v32i8, { 4, 6, 5, 6 } }, // 2 x 128-bit Op + extract/insert
3758 { ISD::UMIN, MVT::v4i64, { 9, 10, 11, 17 } }, // 2 x 128-bit Op + extract/insert
3759 { ISD::UMIN, MVT::v2i64, { 4, 8, 5, 7 } },
3760 { ISD::UMIN, MVT::v8i32, { 4, 6, 5, 6 } }, // 2 x 128-bit Op + extract/insert
3761 { ISD::UMIN, MVT::v16i16, { 4, 6, 5, 6 } }, // 2 x 128-bit Op + extract/insert
3762 { ISD::UMIN, MVT::v32i8, { 4, 6, 5, 6 } }, // 2 x 128-bit Op + extract/insert
3763 { ISD::USUBSAT, MVT::v16i16, { 4 } }, // 2 x 128-bit Op + extract/insert
3764 { ISD::USUBSAT, MVT::v32i8, { 4 } }, // 2 x 128-bit Op + extract/insert
3765 { ISD::USUBSAT, MVT::v8i32, { 6 } }, // 2 x 128-bit Op + extract/insert
3766 { ISD::FMAXNUM, MVT::f32, { 3, 6, 3, 5 } }, // MAXSS + CMPUNORDSS + BLENDVPS
3767 { ISD::FMAXNUM, MVT::v4f32, { 3, 6, 3, 5 } }, // MAXPS + CMPUNORDPS + BLENDVPS
3768 { ISD::FMAXNUM, MVT::v8f32, { 5, 7, 3, 10 } }, // MAXPS + CMPUNORDPS + BLENDVPS
3769 { ISD::FMAXNUM, MVT::f64, { 3, 6, 3, 5 } }, // MAXSD + CMPUNORDSD + BLENDVPD
3770 { ISD::FMAXNUM, MVT::v2f64, { 3, 6, 3, 5 } }, // MAXPD + CMPUNORDPD + BLENDVPD
3771 { ISD::FMAXNUM, MVT::v4f64, { 5, 7, 3, 10 } }, // MAXPD + CMPUNORDPD + BLENDVPD
3772 { ISD::FSQRT, MVT::f32, { 21, 21, 1, 1 } }, // vsqrtss
3773 { ISD::FSQRT, MVT::v4f32, { 21, 21, 1, 1 } }, // vsqrtps
3774 { ISD::FSQRT, MVT::v8f32, { 42, 42, 1, 3 } }, // vsqrtps
3775 { ISD::FSQRT, MVT::f64, { 27, 27, 1, 1 } }, // vsqrtsd
3776 { ISD::FSQRT, MVT::v2f64, { 27, 27, 1, 1 } }, // vsqrtpd
3777 { ISD::FSQRT, MVT::v4f64, { 54, 54, 1, 3 } }, // vsqrtpd
3778 };
3779 static const CostKindTblEntry GLMCostTbl[] = {
3780 { ISD::FSQRT, MVT::f32, { 19, 20, 1, 1 } }, // sqrtss
3781 { ISD::FSQRT, MVT::v4f32, { 37, 41, 1, 5 } }, // sqrtps
3782 { ISD::FSQRT, MVT::f64, { 34, 35, 1, 1 } }, // sqrtsd
3783 { ISD::FSQRT, MVT::v2f64, { 67, 71, 1, 5 } }, // sqrtpd
3784 };
3785 static const CostKindTblEntry SLMCostTbl[] = {
3786 { ISD::FSQRT, MVT::f32, { 20, 20, 1, 1 } }, // sqrtss
3787 { ISD::FSQRT, MVT::v4f32, { 40, 41, 1, 5 } }, // sqrtps
3788 { ISD::FSQRT, MVT::f64, { 35, 35, 1, 1 } }, // sqrtsd
3789 { ISD::FSQRT, MVT::v2f64, { 70, 71, 1, 5 } }, // sqrtpd
3790 };
3791 static const CostKindTblEntry SSE42CostTbl[] = {
3792 { ISD::USUBSAT, MVT::v4i32, { 2 } }, // pmaxud + psubd
3793 { ISD::UADDSAT, MVT::v4i32, { 3 } }, // not + pminud + paddd
3794 { ISD::FMAXNUM, MVT::f32, { 5, 5, 7, 7 } }, // MAXSS + CMPUNORDSS + BLENDVPS
3795 { ISD::FMAXNUM, MVT::v4f32, { 4, 4, 4, 5 } }, // MAXPS + CMPUNORDPS + BLENDVPS
3796 { ISD::FMAXNUM, MVT::f64, { 5, 5, 7, 7 } }, // MAXSD + CMPUNORDSD + BLENDVPD
3797 { ISD::FMAXNUM, MVT::v2f64, { 4, 4, 4, 5 } }, // MAXPD + CMPUNORDPD + BLENDVPD
3798 { ISD::FSQRT, MVT::f32, { 18, 18, 1, 1 } }, // Nehalem from http://www.agner.org/
3799 { ISD::FSQRT, MVT::v4f32, { 18, 18, 1, 1 } }, // Nehalem from http://www.agner.org/
3800 };
3801 static const CostKindTblEntry SSE41CostTbl[] = {
3802 { ISD::ABS, MVT::v2i64, { 3, 4, 3, 5 } }, // BLENDVPD(X,PSUBQ(0,X),X)
3803 { ISD::SMAX, MVT::v2i64, { 3, 7, 2, 3 } },
3804 { ISD::SMAX, MVT::v4i32, { 1, 1, 1, 1 } },
3805 { ISD::SMAX, MVT::v16i8, { 1, 1, 1, 1 } },
3806 { ISD::SMIN, MVT::v2i64, { 3, 7, 2, 3 } },
3807 { ISD::SMIN, MVT::v4i32, { 1, 1, 1, 1 } },
3808 { ISD::SMIN, MVT::v16i8, { 1, 1, 1, 1 } },
3809 { ISD::UMAX, MVT::v2i64, { 2, 11, 6, 7 } },
3810 { ISD::UMAX, MVT::v4i32, { 1, 1, 1, 1 } },
3811 { ISD::UMAX, MVT::v8i16, { 1, 1, 1, 1 } },
3812 { ISD::UMIN, MVT::v2i64, { 2, 11, 6, 7 } },
3813 { ISD::UMIN, MVT::v4i32, { 1, 1, 1, 1 } },
3814 { ISD::UMIN, MVT::v8i16, { 1, 1, 1, 1 } },
3815 };
3816 static const CostKindTblEntry SSSE3CostTbl[] = {
3817 { ISD::ABS, MVT::v4i32, { 1, 2, 1, 1 } },
3818 { ISD::ABS, MVT::v8i16, { 1, 2, 1, 1 } },
3819 { ISD::ABS, MVT::v16i8, { 1, 2, 1, 1 } },
3820 { ISD::BITREVERSE, MVT::v2i64, { 16, 20, 11, 21 } },
3821 { ISD::BITREVERSE, MVT::v4i32, { 16, 20, 11, 21 } },
3822 { ISD::BITREVERSE, MVT::v8i16, { 16, 20, 11, 21 } },
3823 { ISD::BITREVERSE, MVT::v16i8, { 11, 12, 10, 16 } },
3824 { ISD::BSWAP, MVT::v2i64, { 5, 5, 1, 5 } },
3825 { ISD::BSWAP, MVT::v4i32, { 5, 5, 1, 5 } },
3826 { ISD::BSWAP, MVT::v8i16, { 5, 5, 1, 5 } },
3827 { ISD::CTLZ, MVT::v2i64, { 18, 28, 28, 35 } },
3828 { ISD::CTLZ, MVT::v4i32, { 15, 20, 22, 28 } },
3829 { ISD::CTLZ, MVT::v8i16, { 13, 17, 16, 22 } },
3830 { ISD::CTLZ, MVT::v16i8, { 11, 15, 10, 16 } },
3831 { ISD::CTPOP, MVT::v2i64, { 13, 19, 12, 18 } },
3832 { ISD::CTPOP, MVT::v4i32, { 18, 24, 16, 22 } },
3833 { ISD::CTPOP, MVT::v8i16, { 13, 18, 14, 20 } },
3834 { ISD::CTPOP, MVT::v16i8, { 11, 12, 10, 16 } },
3835 { ISD::CTTZ, MVT::v2i64, { 13, 25, 15, 22 } },
3836 { ISD::CTTZ, MVT::v4i32, { 18, 26, 19, 25 } },
3837 { ISD::CTTZ, MVT::v8i16, { 13, 20, 17, 23 } },
3838 { ISD::CTTZ, MVT::v16i8, { 11, 16, 13, 19 } }
3839 };
3840 static const CostKindTblEntry SSE2CostTbl[] = {
3841 { ISD::ABS, MVT::v2i64, { 3, 6, 5, 5 } },
3842 { ISD::ABS, MVT::v4i32, { 1, 4, 4, 4 } },
3843 { ISD::ABS, MVT::v8i16, { 1, 2, 3, 3 } },
3844 { ISD::ABS, MVT::v16i8, { 1, 2, 3, 3 } },
3845 { ISD::BITREVERSE, MVT::v2i64, { 16, 20, 32, 32 } },
3846 { ISD::BITREVERSE, MVT::v4i32, { 16, 20, 30, 30 } },
3847 { ISD::BITREVERSE, MVT::v8i16, { 16, 20, 25, 25 } },
3848 { ISD::BITREVERSE, MVT::v16i8, { 11, 12, 21, 21 } },
3849 { ISD::BSWAP, MVT::v2i64, { 5, 6, 11, 11 } },
3850 { ISD::BSWAP, MVT::v4i32, { 5, 5, 9, 9 } },
3851 { ISD::BSWAP, MVT::v8i16, { 5, 5, 4, 5 } },
3852 { ISD::CTLZ, MVT::v2i64, { 10, 45, 36, 38 } },
3853 { ISD::CTLZ, MVT::v4i32, { 10, 45, 38, 40 } },
3854 { ISD::CTLZ, MVT::v8i16, { 9, 38, 32, 34 } },
3855 { ISD::CTLZ, MVT::v16i8, { 8, 39, 29, 32 } },
3856 { ISD::CTPOP, MVT::v2i64, { 12, 26, 16, 18 } },
3857 { ISD::CTPOP, MVT::v4i32, { 15, 29, 21, 23 } },
3858 { ISD::CTPOP, MVT::v8i16, { 13, 25, 18, 20 } },
3859 { ISD::CTPOP, MVT::v16i8, { 10, 21, 14, 16 } },
3860 { ISD::CTTZ, MVT::v2i64, { 14, 28, 19, 21 } },
3861 { ISD::CTTZ, MVT::v4i32, { 18, 31, 24, 26 } },
3862 { ISD::CTTZ, MVT::v8i16, { 16, 27, 21, 23 } },
3863 { ISD::CTTZ, MVT::v16i8, { 13, 23, 17, 19 } },
3864 { ISD::SADDSAT, MVT::v8i16, { 1 } },
3865 { ISD::SADDSAT, MVT::v16i8, { 1 } },
3866 { ISD::SMAX, MVT::v2i64, { 4, 8, 15, 15 } },
3867 { ISD::SMAX, MVT::v4i32, { 2, 4, 5, 5 } },
3868 { ISD::SMAX, MVT::v8i16, { 1, 1, 1, 1 } },
3869 { ISD::SMAX, MVT::v16i8, { 2, 4, 5, 5 } },
3870 { ISD::SMIN, MVT::v2i64, { 4, 8, 15, 15 } },
3871 { ISD::SMIN, MVT::v4i32, { 2, 4, 5, 5 } },
3872 { ISD::SMIN, MVT::v8i16, { 1, 1, 1, 1 } },
3873 { ISD::SMIN, MVT::v16i8, { 2, 4, 5, 5 } },
3874 { ISD::SSUBSAT, MVT::v8i16, { 1 } },
3875 { ISD::SSUBSAT, MVT::v16i8, { 1 } },
3876 { ISD::UADDSAT, MVT::v8i16, { 1 } },
3877 { ISD::UADDSAT, MVT::v16i8, { 1 } },
3878 { ISD::UMAX, MVT::v2i64, { 4, 8, 15, 15 } },
3879 { ISD::UMAX, MVT::v4i32, { 2, 5, 8, 8 } },
3880 { ISD::UMAX, MVT::v8i16, { 1, 3, 3, 3 } },
3881 { ISD::UMAX, MVT::v16i8, { 1, 1, 1, 1 } },
3882 { ISD::UMIN, MVT::v2i64, { 4, 8, 15, 15 } },
3883 { ISD::UMIN, MVT::v4i32, { 2, 5, 8, 8 } },
3884 { ISD::UMIN, MVT::v8i16, { 1, 3, 3, 3 } },
3885 { ISD::UMIN, MVT::v16i8, { 1, 1, 1, 1 } },
3886 { ISD::USUBSAT, MVT::v8i16, { 1 } },
3887 { ISD::USUBSAT, MVT::v16i8, { 1 } },
3888 { ISD::FMAXNUM, MVT::f64, { 5, 5, 7, 7 } },
3889 { ISD::FMAXNUM, MVT::v2f64, { 4, 6, 6, 6 } },
3890 { ISD::FSQRT, MVT::f64, { 32, 32, 1, 1 } }, // Nehalem from http://www.agner.org/
3891 { ISD::FSQRT, MVT::v2f64, { 32, 32, 1, 1 } }, // Nehalem from http://www.agner.org/
3892 };
3893 static const CostKindTblEntry SSE1CostTbl[] = {
3894 { ISD::FMAXNUM, MVT::f32, { 5, 5, 7, 7 } },
3895 { ISD::FMAXNUM, MVT::v4f32, { 4, 6, 6, 6 } },
3896 { ISD::FSQRT, MVT::f32, { 28, 30, 1, 2 } }, // Pentium III from http://www.agner.org/
3897 { ISD::FSQRT, MVT::v4f32, { 56, 56, 1, 2 } }, // Pentium III from http://www.agner.org/
3898 };
3899 static const CostKindTblEntry BMI64CostTbl[] = { // 64-bit targets
3900 { ISD::CTTZ, MVT::i64, { 1 } },
3901 };
3902 static const CostKindTblEntry BMI32CostTbl[] = { // 32 or 64-bit targets
3903 { ISD::CTTZ, MVT::i32, { 1 } },
3904 { ISD::CTTZ, MVT::i16, { 1 } },
3905 { ISD::CTTZ, MVT::i8, { 1 } },
3906 };
3907 static const CostKindTblEntry LZCNT64CostTbl[] = { // 64-bit targets
3908 { ISD::CTLZ, MVT::i64, { 1 } },
3909 };
3910 static const CostKindTblEntry LZCNT32CostTbl[] = { // 32 or 64-bit targets
3911 { ISD::CTLZ, MVT::i32, { 1 } },
3912 { ISD::CTLZ, MVT::i16, { 2 } },
3913 { ISD::CTLZ, MVT::i8, { 2 } },
3914 };
3915 static const CostKindTblEntry POPCNT64CostTbl[] = { // 64-bit targets
3916 { ISD::CTPOP, MVT::i64, { 1, 1, 1, 1 } }, // popcnt
3917 };
3918 static const CostKindTblEntry POPCNT32CostTbl[] = { // 32 or 64-bit targets
3919 { ISD::CTPOP, MVT::i32, { 1, 1, 1, 1 } }, // popcnt
3920 { ISD::CTPOP, MVT::i16, { 1, 1, 2, 2 } }, // popcnt(zext())
3921 { ISD::CTPOP, MVT::i8, { 1, 1, 2, 2 } }, // popcnt(zext())
3922 };
3923 static const CostKindTblEntry X64CostTbl[] = { // 64-bit targets
3924 { ISD::ABS, MVT::i64, { 1, 2, 3, 4 } }, // SUB+CMOV
3925 { ISD::BITREVERSE, MVT::i64, { 10, 12, 20, 22 } },
3926 { ISD::BSWAP, MVT::i64, { 1, 2, 1, 2 } },
3927 { ISD::CTLZ, MVT::i64, { 4 } }, // BSR+XOR or BSR+XOR+CMOV
3928 { ISD::CTLZ_ZERO_UNDEF, MVT::i64,{ 1, 1, 1, 1 } }, // BSR+XOR
3929 { ISD::CTTZ, MVT::i64, { 3 } }, // TEST+BSF+CMOV/BRANCH
3930 { ISD::CTTZ_ZERO_UNDEF, MVT::i64,{ 1, 1, 1, 1 } }, // BSR
3931 { ISD::CTPOP, MVT::i64, { 10, 6, 19, 19 } },
3932 { ISD::ROTL, MVT::i64, { 2, 3, 1, 3 } },
3933 { ISD::ROTR, MVT::i64, { 2, 3, 1, 3 } },
3934 { ISD::FSHL, MVT::i64, { 4, 4, 1, 4 } },
3935 { ISD::SMAX, MVT::i64, { 1, 3, 2, 3 } },
3936 { ISD::SMIN, MVT::i64, { 1, 3, 2, 3 } },
3937 { ISD::UMAX, MVT::i64, { 1, 3, 2, 3 } },
3938 { ISD::UMIN, MVT::i64, { 1, 3, 2, 3 } },
3939 { ISD::SADDO, MVT::i64, { 1 } },
3940 { ISD::UADDO, MVT::i64, { 1 } },
3941 { ISD::UMULO, MVT::i64, { 2 } }, // mulq + seto
3942 };
3943 static const CostKindTblEntry X86CostTbl[] = { // 32 or 64-bit targets
3944 { ISD::ABS, MVT::i32, { 1, 2, 3, 4 } }, // SUB+XOR+SRA or SUB+CMOV
3945 { ISD::ABS, MVT::i16, { 2, 2, 3, 4 } }, // SUB+XOR+SRA or SUB+CMOV
3946 { ISD::ABS, MVT::i8, { 2, 4, 4, 4 } }, // SUB+XOR+SRA
3947 { ISD::BITREVERSE, MVT::i32, { 9, 12, 17, 19 } },
3948 { ISD::BITREVERSE, MVT::i16, { 9, 12, 17, 19 } },
3949 { ISD::BITREVERSE, MVT::i8, { 7, 9, 13, 14 } },
3950 { ISD::BSWAP, MVT::i32, { 1, 1, 1, 1 } },
3951 { ISD::BSWAP, MVT::i16, { 1, 2, 1, 2 } }, // ROL
3952 { ISD::CTLZ, MVT::i32, { 4 } }, // BSR+XOR or BSR+XOR+CMOV
3953 { ISD::CTLZ, MVT::i16, { 4 } }, // BSR+XOR or BSR+XOR+CMOV
3954 { ISD::CTLZ, MVT::i8, { 4 } }, // BSR+XOR or BSR+XOR+CMOV
3955 { ISD::CTLZ_ZERO_UNDEF, MVT::i32,{ 1, 1, 1, 1 } }, // BSR+XOR
3956 { ISD::CTLZ_ZERO_UNDEF, MVT::i16,{ 2, 2, 3, 3 } }, // BSR+XOR
3957 { ISD::CTLZ_ZERO_UNDEF, MVT::i8, { 2, 2, 3, 3 } }, // BSR+XOR
3958 { ISD::CTTZ, MVT::i32, { 3 } }, // TEST+BSF+CMOV/BRANCH
3959 { ISD::CTTZ, MVT::i16, { 3 } }, // TEST+BSF+CMOV/BRANCH
3960 { ISD::CTTZ, MVT::i8, { 3 } }, // TEST+BSF+CMOV/BRANCH
3961 { ISD::CTTZ_ZERO_UNDEF, MVT::i32,{ 1, 1, 1, 1 } }, // BSF
3962 { ISD::CTTZ_ZERO_UNDEF, MVT::i16,{ 2, 2, 1, 1 } }, // BSF
3963 { ISD::CTTZ_ZERO_UNDEF, MVT::i8, { 2, 2, 1, 1 } }, // BSF
3964 { ISD::CTPOP, MVT::i32, { 8, 7, 15, 15 } },
3965 { ISD::CTPOP, MVT::i16, { 9, 8, 17, 17 } },
3966 { ISD::CTPOP, MVT::i8, { 7, 6, 13, 13 } },
3967 { ISD::ROTL, MVT::i32, { 2, 3, 1, 3 } },
3968 { ISD::ROTL, MVT::i16, { 2, 3, 1, 3 } },
3969 { ISD::ROTL, MVT::i8, { 2, 3, 1, 3 } },
3970 { ISD::ROTR, MVT::i32, { 2, 3, 1, 3 } },
3971 { ISD::ROTR, MVT::i16, { 2, 3, 1, 3 } },
3972 { ISD::ROTR, MVT::i8, { 2, 3, 1, 3 } },
3973 { ISD::FSHL, MVT::i32, { 4, 4, 1, 4 } },
3974 { ISD::FSHL, MVT::i16, { 4, 4, 2, 5 } },
3975 { ISD::FSHL, MVT::i8, { 4, 4, 2, 5 } },
3976 { ISD::SMAX, MVT::i32, { 1, 2, 2, 3 } },
3977 { ISD::SMAX, MVT::i16, { 1, 4, 2, 4 } },
3978 { ISD::SMAX, MVT::i8, { 1, 4, 2, 4 } },
3979 { ISD::SMIN, MVT::i32, { 1, 2, 2, 3 } },
3980 { ISD::SMIN, MVT::i16, { 1, 4, 2, 4 } },
3981 { ISD::SMIN, MVT::i8, { 1, 4, 2, 4 } },
3982 { ISD::UMAX, MVT::i32, { 1, 2, 2, 3 } },
3983 { ISD::UMAX, MVT::i16, { 1, 4, 2, 4 } },
3984 { ISD::UMAX, MVT::i8, { 1, 4, 2, 4 } },
3985 { ISD::UMIN, MVT::i32, { 1, 2, 2, 3 } },
3986 { ISD::UMIN, MVT::i16, { 1, 4, 2, 4 } },
3987 { ISD::UMIN, MVT::i8, { 1, 4, 2, 4 } },
3988 { ISD::SADDO, MVT::i32, { 1 } },
3989 { ISD::SADDO, MVT::i16, { 1 } },
3990 { ISD::SADDO, MVT::i8, { 1 } },
3991 { ISD::UADDO, MVT::i32, { 1 } },
3992 { ISD::UADDO, MVT::i16, { 1 } },
3993 { ISD::UADDO, MVT::i8, { 1 } },
3994 { ISD::UMULO, MVT::i32, { 2 } }, // mul + seto
3995 { ISD::UMULO, MVT::i16, { 2 } },
3996 { ISD::UMULO, MVT::i8, { 2 } },
3997 };
3998
3999 Type *RetTy = ICA.getReturnType();
4000 Type *OpTy = RetTy;
4001 Intrinsic::ID IID = ICA.getID();
4002 unsigned ISD = ISD::DELETED_NODE;
4003 switch (IID) {
4004 default:
4005 break;
4006 case Intrinsic::abs:
4007 ISD = ISD::ABS;
4008 break;
4009 case Intrinsic::bitreverse:
4010 ISD = ISD::BITREVERSE;
4011 break;
4012 case Intrinsic::bswap:
4013 ISD = ISD::BSWAP;
4014 break;
4015 case Intrinsic::ctlz:
4016 ISD = ISD::CTLZ;
4017 break;
4018 case Intrinsic::ctpop:
4019 ISD = ISD::CTPOP;
4020 break;
4021 case Intrinsic::cttz:
4022 ISD = ISD::CTTZ;
4023 break;
4024 case Intrinsic::fshl:
4025 ISD = ISD::FSHL;
4026 if (!ICA.isTypeBasedOnly()) {
4027 const SmallVectorImpl<const Value *> &Args = ICA.getArgs();
4028 if (Args[0] == Args[1])
4029 ISD = ISD::ROTL;
4030 }
4031 break;
4032 case Intrinsic::fshr:
4033 // FSHR has same costs so don't duplicate.
4034 ISD = ISD::FSHL;
4035 if (!ICA.isTypeBasedOnly()) {
4036 const SmallVectorImpl<const Value *> &Args = ICA.getArgs();
4037 if (Args[0] == Args[1])
4038 ISD = ISD::ROTR;
4039 }
4040 break;
4041 case Intrinsic::maxnum:
4042 case Intrinsic::minnum:
4043 // FMINNUM has same costs so don't duplicate.
4044 ISD = ISD::FMAXNUM;
4045 break;
4046 case Intrinsic::sadd_sat:
4047 ISD = ISD::SADDSAT;
4048 break;
4049 case Intrinsic::smax:
4050 ISD = ISD::SMAX;
4051 break;
4052 case Intrinsic::smin:
4053 ISD = ISD::SMIN;
4054 break;
4055 case Intrinsic::ssub_sat:
4056 ISD = ISD::SSUBSAT;
4057 break;
4058 case Intrinsic::uadd_sat:
4059 ISD = ISD::UADDSAT;
4060 break;
4061 case Intrinsic::umax:
4062 ISD = ISD::UMAX;
4063 break;
4064 case Intrinsic::umin:
4065 ISD = ISD::UMIN;
4066 break;
4067 case Intrinsic::usub_sat:
4068 ISD = ISD::USUBSAT;
4069 break;
4070 case Intrinsic::sqrt:
4071 ISD = ISD::FSQRT;
4072 break;
4073 case Intrinsic::sadd_with_overflow:
4074 case Intrinsic::ssub_with_overflow:
4075 // SSUBO has same costs so don't duplicate.
4076 ISD = ISD::SADDO;
4077 OpTy = RetTy->getContainedType(0);
4078 break;
4079 case Intrinsic::uadd_with_overflow:
4080 case Intrinsic::usub_with_overflow:
4081 // USUBO has same costs so don't duplicate.
4082 ISD = ISD::UADDO;
4083 OpTy = RetTy->getContainedType(0);
4084 break;
4085 case Intrinsic::umul_with_overflow:
4086 case Intrinsic::smul_with_overflow:
4087 // SMULO has same costs so don't duplicate.
4088 ISD = ISD::UMULO;
4089 OpTy = RetTy->getContainedType(0);
4090 break;
4091 }
4092
4093 if (ISD != ISD::DELETED_NODE) {
4094 // Legalize the type.
4095 std::pair<InstructionCost, MVT> LT = getTypeLegalizationCost(OpTy);
4096 MVT MTy = LT.second;
4097
4098 // Attempt to lookup cost.
4099 if (ISD == ISD::BITREVERSE && ST->hasGFNI() && ST->hasSSSE3() &&
4100 MTy.isVector()) {
4101 // With PSHUFB the code is very similar for all types. If we have integer
4102 // byte operations, we just need a GF2P8AFFINEQB for vXi8. For other types
4103 // we also need a PSHUFB.
4104 unsigned Cost = MTy.getVectorElementType() == MVT::i8 ? 1 : 2;
4105
4106 // Without byte operations, we need twice as many GF2P8AFFINEQB and PSHUFB
4107 // instructions. We also need an extract and an insert.
4108 if (!(MTy.is128BitVector() || (ST->hasAVX2() && MTy.is256BitVector()) ||
4109 (ST->hasBWI() && MTy.is512BitVector())))
4110 Cost = Cost * 2 + 2;
4111
4112 return LT.first * Cost;
4113 }
4114
4115 // Without BMI/LZCNT see if we're only looking for a *_ZERO_UNDEF cost.
4116 if (((ISD == ISD::CTTZ && !ST->hasBMI()) ||
4117 (ISD == ISD::CTLZ && !ST->hasLZCNT())) &&
4118 !MTy.isVector() && !ICA.isTypeBasedOnly()) {
4119 const SmallVectorImpl<const Value *> &Args = ICA.getArgs();
4120 if (auto *Cst = dyn_cast<ConstantInt>(Args[1]))
4121 if (Cst->isAllOnesValue())
4122 ISD = ISD == ISD::CTTZ ? ISD::CTTZ_ZERO_UNDEF : ISD::CTLZ_ZERO_UNDEF;
4123 }
4124
4125 // FSQRT is a single instruction.
4126 if (ISD == ISD::FSQRT && CostKind == TTI::TCK_CodeSize)
4127 return LT.first;
4128
4129 auto adjustTableCost = [](int ISD, unsigned Cost,
4130 InstructionCost LegalizationCost,
4131 FastMathFlags FMF) {
4132 // If there are no NANs to deal with, then these are reduced to a
4133 // single MIN** or MAX** instruction instead of the MIN/CMP/SELECT that we
4134 // assume is used in the non-fast case.
4135 if (ISD == ISD::FMAXNUM || ISD == ISD::FMINNUM) {
4136 if (FMF.noNaNs())
4137 return LegalizationCost * 1;
4138 }
4139 return LegalizationCost * (int)Cost;
4140 };
4141
4142 if (ST->useGLMDivSqrtCosts())
4143 if (const auto *Entry = CostTableLookup(GLMCostTbl, ISD, MTy))
4144 if (auto KindCost = Entry->Cost[CostKind])
4145 return adjustTableCost(Entry->ISD, *KindCost, LT.first,
4146 ICA.getFlags());
4147
4148 if (ST->useSLMArithCosts())
4149 if (const auto *Entry = CostTableLookup(SLMCostTbl, ISD, MTy))
4150 if (auto KindCost = Entry->Cost[CostKind])
4151 return adjustTableCost(Entry->ISD, *KindCost, LT.first,
4152 ICA.getFlags());
4153
4154 if (ST->hasVBMI2())
4155 if (const auto *Entry = CostTableLookup(AVX512VBMI2CostTbl, ISD, MTy))
4156 if (auto KindCost = Entry->Cost[CostKind])
4157 return adjustTableCost(Entry->ISD, *KindCost, LT.first,
4158 ICA.getFlags());
4159
4160 if (ST->hasBITALG())
4161 if (const auto *Entry = CostTableLookup(AVX512BITALGCostTbl, ISD, MTy))
4162 if (auto KindCost = Entry->Cost[CostKind])
4163 return adjustTableCost(Entry->ISD, *KindCost, LT.first,
4164 ICA.getFlags());
4165
4166 if (ST->hasVPOPCNTDQ())
4167 if (const auto *Entry = CostTableLookup(AVX512VPOPCNTDQCostTbl, ISD, MTy))
4168 if (auto KindCost = Entry->Cost[CostKind])
4169 return adjustTableCost(Entry->ISD, *KindCost, LT.first,
4170 ICA.getFlags());
4171
4172 if (ST->hasCDI())
4173 if (const auto *Entry = CostTableLookup(AVX512CDCostTbl, ISD, MTy))
4174 if (auto KindCost = Entry->Cost[CostKind])
4175 return adjustTableCost(Entry->ISD, *KindCost, LT.first,
4176 ICA.getFlags());
4177
4178 if (ST->hasBWI())
4179 if (const auto *Entry = CostTableLookup(AVX512BWCostTbl, ISD, MTy))
4180 if (auto KindCost = Entry->Cost[CostKind])
4181 return adjustTableCost(Entry->ISD, *KindCost, LT.first,
4182 ICA.getFlags());
4183
4184 if (ST->hasAVX512())
4185 if (const auto *Entry = CostTableLookup(AVX512CostTbl, ISD, MTy))
4186 if (auto KindCost = Entry->Cost[CostKind])
4187 return adjustTableCost(Entry->ISD, *KindCost, LT.first,
4188 ICA.getFlags());
4189
4190 if (ST->hasXOP())
4191 if (const auto *Entry = CostTableLookup(XOPCostTbl, ISD, MTy))
4192 if (auto KindCost = Entry->Cost[CostKind])
4193 return adjustTableCost(Entry->ISD, *KindCost, LT.first,
4194 ICA.getFlags());
4195
4196 if (ST->hasAVX2())
4197 if (const auto *Entry = CostTableLookup(AVX2CostTbl, ISD, MTy))
4198 if (auto KindCost = Entry->Cost[CostKind])
4199 return adjustTableCost(Entry->ISD, *KindCost, LT.first,
4200 ICA.getFlags());
4201
4202 if (ST->hasAVX())
4203 if (const auto *Entry = CostTableLookup(AVX1CostTbl, ISD, MTy))
4204 if (auto KindCost = Entry->Cost[CostKind])
4205 return adjustTableCost(Entry->ISD, *KindCost, LT.first,
4206 ICA.getFlags());
4207
4208 if (ST->hasSSE42())
4209 if (const auto *Entry = CostTableLookup(SSE42CostTbl, ISD, MTy))
4210 if (auto KindCost = Entry->Cost[CostKind])
4211 return adjustTableCost(Entry->ISD, *KindCost, LT.first,
4212 ICA.getFlags());
4213
4214 if (ST->hasSSE41())
4215 if (const auto *Entry = CostTableLookup(SSE41CostTbl, ISD, MTy))
4216 if (auto KindCost = Entry->Cost[CostKind])
4217 return adjustTableCost(Entry->ISD, *KindCost, LT.first,
4218 ICA.getFlags());
4219
4220 if (ST->hasSSSE3())
4221 if (const auto *Entry = CostTableLookup(SSSE3CostTbl, ISD, MTy))
4222 if (auto KindCost = Entry->Cost[CostKind])
4223 return adjustTableCost(Entry->ISD, *KindCost, LT.first,
4224 ICA.getFlags());
4225
4226 if (ST->hasSSE2())
4227 if (const auto *Entry = CostTableLookup(SSE2CostTbl, ISD, MTy))
4228 if (auto KindCost = Entry->Cost[CostKind])
4229 return adjustTableCost(Entry->ISD, *KindCost, LT.first,
4230 ICA.getFlags());
4231
4232 if (ST->hasSSE1())
4233 if (const auto *Entry = CostTableLookup(SSE1CostTbl, ISD, MTy))
4234 if (auto KindCost = Entry->Cost[CostKind])
4235 return adjustTableCost(Entry->ISD, *KindCost, LT.first,
4236 ICA.getFlags());
4237
4238 if (ST->hasBMI()) {
4239 if (ST->is64Bit())
4240 if (const auto *Entry = CostTableLookup(BMI64CostTbl, ISD, MTy))
4241 if (auto KindCost = Entry->Cost[CostKind])
4242 return adjustTableCost(Entry->ISD, *KindCost, LT.first,
4243 ICA.getFlags());
4244
4245 if (const auto *Entry = CostTableLookup(BMI32CostTbl, ISD, MTy))
4246 if (auto KindCost = Entry->Cost[CostKind])
4247 return adjustTableCost(Entry->ISD, *KindCost, LT.first,
4248 ICA.getFlags());
4249 }
4250
4251 if (ST->hasLZCNT()) {
4252 if (ST->is64Bit())
4253 if (const auto *Entry = CostTableLookup(LZCNT64CostTbl, ISD, MTy))
4254 if (auto KindCost = Entry->Cost[CostKind])
4255 return adjustTableCost(Entry->ISD, *KindCost, LT.first,
4256 ICA.getFlags());
4257
4258 if (const auto *Entry = CostTableLookup(LZCNT32CostTbl, ISD, MTy))
4259 if (auto KindCost = Entry->Cost[CostKind])
4260 return adjustTableCost(Entry->ISD, *KindCost, LT.first,
4261 ICA.getFlags());
4262 }
4263
4264 if (ST->hasPOPCNT()) {
4265 if (ST->is64Bit())
4266 if (const auto *Entry = CostTableLookup(POPCNT64CostTbl, ISD, MTy))
4267 if (auto KindCost = Entry->Cost[CostKind])
4268 return adjustTableCost(Entry->ISD, *KindCost, LT.first,
4269 ICA.getFlags());
4270
4271 if (const auto *Entry = CostTableLookup(POPCNT32CostTbl, ISD, MTy))
4272 if (auto KindCost = Entry->Cost[CostKind])
4273 return adjustTableCost(Entry->ISD, *KindCost, LT.first,
4274 ICA.getFlags());
4275 }
4276
4277 if (ISD == ISD::BSWAP && ST->hasMOVBE() && ST->hasFastMOVBE()) {
4278 if (const Instruction *II = ICA.getInst()) {
4279 if (II->hasOneUse() && isa<StoreInst>(II->user_back()))
4280 return TTI::TCC_Free;
4281 if (auto *LI = dyn_cast<LoadInst>(II->getOperand(0))) {
4282 if (LI->hasOneUse())
4283 return TTI::TCC_Free;
4284 }
4285 }
4286 }
4287
4288 if (ST->is64Bit())
4289 if (const auto *Entry = CostTableLookup(X64CostTbl, ISD, MTy))
4290 if (auto KindCost = Entry->Cost[CostKind])
4291 return adjustTableCost(Entry->ISD, *KindCost, LT.first,
4292 ICA.getFlags());
4293
4294 if (const auto *Entry = CostTableLookup(X86CostTbl, ISD, MTy))
4295 if (auto KindCost = Entry->Cost[CostKind])
4296 return adjustTableCost(Entry->ISD, *KindCost, LT.first, ICA.getFlags());
4297 }
4298
4299 return BaseT::getIntrinsicInstrCost(ICA, CostKind);
4300}
4301
4302InstructionCost X86TTIImpl::getVectorInstrCost(unsigned Opcode, Type *Val,
4303 TTI::TargetCostKind CostKind,
4304 unsigned Index, Value *Op0,
4305 Value *Op1) {
4306 static const CostTblEntry SLMCostTbl[] = {
4307 { ISD::EXTRACT_VECTOR_ELT, MVT::i8, 4 },
4308 { ISD::EXTRACT_VECTOR_ELT, MVT::i16, 4 },
4309 { ISD::EXTRACT_VECTOR_ELT, MVT::i32, 4 },
4310 { ISD::EXTRACT_VECTOR_ELT, MVT::i64, 7 }
4311 };
4312
4313 assert(Val->isVectorTy() && "This must be a vector type")(static_cast <bool> (Val->isVectorTy() && "This must be a vector type"
) ? void (0) : __assert_fail ("Val->isVectorTy() && \"This must be a vector type\""
, "llvm/lib/Target/X86/X86TargetTransformInfo.cpp", 4313, __extension__
__PRETTY_FUNCTION__));
16
←
'?' condition is true
→
4314 Type *ScalarType = Val->getScalarType();
4315 InstructionCost RegisterFileMoveCost = 0;
4316
4317 // Non-immediate extraction/insertion can be handled as a sequence of
4318 // aliased loads+stores via the stack.
4319 if (Index == -1U && (Opcode == Instruction::ExtractElement ||
4320 Opcode == Instruction::InsertElement)) {
4321 // TODO: On some SSE41+ targets, we expand to cmp+splat+select patterns:
4322 // inselt N0, N1, N2 --> select (SplatN2 == {0,1,2...}) ? SplatN1 : N0.
4323
4324 // TODO: Move this to BasicTTIImpl.h? We'd need better gep + index handling.
4325 assert(isa<FixedVectorType>(Val) && "Fixed vector type expected")(static_cast <bool> (isa<FixedVectorType>(Val) &&
"Fixed vector type expected") ? void (0) : __assert_fail ("isa<FixedVectorType>(Val) && \"Fixed vector type expected\""
, "llvm/lib/Target/X86/X86TargetTransformInfo.cpp", 4325, __extension__
__PRETTY_FUNCTION__));
4326 Align VecAlign = DL.getPrefTypeAlign(Val);
4327 Align SclAlign = DL.getPrefTypeAlign(ScalarType);
4328
4329 // Extract - store vector to stack, load scalar.
4330 if (Opcode == Instruction::ExtractElement) {
4331 return getMemoryOpCost(Instruction::Store, Val, VecAlign, 0, CostKind) +
4332 getMemoryOpCost(Instruction::Load, ScalarType, SclAlign, 0,
4333 CostKind);
4334 }
4335 // Insert - store vector to stack, store scalar, load vector.
4336 if (Opcode == Instruction::InsertElement) {
4337 return getMemoryOpCost(Instruction::Store, Val, VecAlign, 0, CostKind) +
4338 getMemoryOpCost(Instruction::Store, ScalarType, SclAlign, 0,
4339 CostKind) +
4340 getMemoryOpCost(Instruction::Load, Val, VecAlign, 0, CostKind);
4341 }
4342 }
4343
4344 if (Index != -1U && (Opcode
16.1
'Opcode' is equal to ExtractElement
 == Instruction::ExtractElement ||
4345 Opcode == Instruction::InsertElement)) {
4346 // Extraction of vXi1 elements are now efficiently handled by MOVMSK.
4347 if (Opcode
16.2
'Opcode' is equal to ExtractElement
 == Instruction::ExtractElement &&
4348 ScalarType->getScalarSizeInBits() == 1 &&
17
←
Assuming the condition is false
→
4349 cast<FixedVectorType>(Val)->getNumElements() > 1)
4350 return 1;
4351
4352 // Legalize the type.
4353 std::pair<InstructionCost, MVT> LT = getTypeLegalizationCost(Val);
4354
4355 // This type is legalized to a scalar type.
4356 if (!LT.second.isVector())
18
←
Taking false branch
→
4357 return 0;
4358
4359 // The type may be split. Normalize the index to the new type.
4360 unsigned SizeInBits = LT.second.getSizeInBits();
4361 unsigned NumElts = LT.second.getVectorNumElements();
4362 unsigned SubNumElts = NumElts;
4363 Index = Index % NumElts;
4364
4365 // For >128-bit vectors, we need to extract higher 128-bit subvectors.
4366 // For inserts, we also need to insert the subvector back.
4367 if (SizeInBits > 128) {
19
←
Assuming 'SizeInBits' is > 128
→
4368 assert((SizeInBits % 128) == 0 && "Illegal vector")(static_cast <bool> ((SizeInBits % 128) == 0 &&
"Illegal vector") ? void (0) : __assert_fail ("(SizeInBits % 128) == 0 && \"Illegal vector\""
, "llvm/lib/Target/X86/X86TargetTransformInfo.cpp", 4368, __extension__
__PRETTY_FUNCTION__));
20
←
Taking true branch
→
21
←
Assuming the condition is true
→
22
←
'?' condition is true
→
4369 unsigned NumSubVecs = SizeInBits / 128;
4370 SubNumElts = NumElts / NumSubVecs;
23
←
Value assigned to 'SubNumElts'
→
4371 if (SubNumElts <= Index) {
24
←
Assuming 'SubNumElts' is <= 'Index'
→
25
←
Taking true branch
→
4372 RegisterFileMoveCost += (Opcode
25.1
'Opcode' is not equal to InsertElement
 == Instruction::InsertElement ? 2 : 1);
26
←
'?' condition is false
→
4373 Index %= SubNumElts;
27
←
Division by zero
4374 }
4375 }
4376
4377 MVT MScalarTy = LT.second.getScalarType();
4378 auto IsCheapPInsrPExtrInsertPS = [&]() {
4379 // Assume pinsr/pextr XMM <-> GPR is relatively cheap on all targets.
4380 // Also, assume insertps is relatively cheap on all >= SSE41 targets.
4381 return (MScalarTy == MVT::i16 && ST->hasSSE2()) ||
4382 (MScalarTy.isInteger() && ST->hasSSE41()) ||
4383 (MScalarTy == MVT::f32 && ST->hasSSE41() &&
4384 Opcode == Instruction::InsertElement);
4385 };
4386
4387 if (Index == 0) {
4388 // Floating point scalars are already located in index #0.
4389 // Many insertions to #0 can fold away for scalar fp-ops, so let's assume
4390 // true for all.
4391 if (ScalarType->isFloatingPointTy() &&
4392 (Opcode != Instruction::InsertElement || !Op0 ||
4393 isa<UndefValue>(Op0)))
4394 return RegisterFileMoveCost;
4395
4396 if (Opcode == Instruction::InsertElement &&
4397 isa_and_nonnull<UndefValue>(Op0)) {
4398 // Consider the gather cost to be cheap.
4399 if (isa_and_nonnull<LoadInst>(Op1))
4400 return RegisterFileMoveCost;
4401 if (!IsCheapPInsrPExtrInsertPS()) {
4402 // mov constant-to-GPR + movd/movq GPR -> XMM.
4403 if (isa_and_nonnull<Constant>(Op1) && Op1->getType()->isIntegerTy())
4404 return 2 + RegisterFileMoveCost;
4405 // Assume movd/movq GPR -> XMM is relatively cheap on all targets.
4406 return 1 + RegisterFileMoveCost;
4407 }
4408 }
4409
4410 // Assume movd/movq XMM -> GPR is relatively cheap on all targets.
4411 if (ScalarType->isIntegerTy() && Opcode == Instruction::ExtractElement)
4412 return 1 + RegisterFileMoveCost;
4413 }
4414
4415 int ISD = TLI->InstructionOpcodeToISD(Opcode);
4416 assert(ISD && "Unexpected vector opcode")(static_cast <bool> (ISD && "Unexpected vector opcode"
) ? void (0) : __assert_fail ("ISD && \"Unexpected vector opcode\""
, "llvm/lib/Target/X86/X86TargetTransformInfo.cpp", 4416, __extension__
__PRETTY_FUNCTION__));
4417 if (ST->useSLMArithCosts())
4418 if (auto *Entry = CostTableLookup(SLMCostTbl, ISD, MScalarTy))
4419 return Entry->Cost + RegisterFileMoveCost;
4420
4421 // Consider cheap cases.
4422 if (IsCheapPInsrPExtrInsertPS())
4423 return 1 + RegisterFileMoveCost;
4424
4425 // For extractions we just need to shuffle the element to index 0, which
4426 // should be very cheap (assume cost = 1). For insertions we need to shuffle
4427 // the elements to its destination. In both cases we must handle the
4428 // subvector move(s).
4429 // If the vector type is already less than 128-bits then don't reduce it.
4430 // TODO: Under what circumstances should we shuffle using the full width?
4431 InstructionCost ShuffleCost = 1;
4432 if (Opcode == Instruction::InsertElement) {
4433 auto *SubTy = cast<VectorType>(Val);
4434 EVT VT = TLI->getValueType(DL, Val);
4435 if (VT.getScalarType() != MScalarTy || VT.getSizeInBits() >= 128)
4436 SubTy = FixedVectorType::get(ScalarType, SubNumElts);
4437 ShuffleCost = getShuffleCost(TTI::SK_PermuteTwoSrc, SubTy, std::nullopt,
4438 CostKind, 0, SubTy);
4439 }
4440 int IntOrFpCost = ScalarType->isFloatingPointTy() ? 0 : 1;
4441 return ShuffleCost + IntOrFpCost + RegisterFileMoveCost;
4442 }
4443
4444 return BaseT::getVectorInstrCost(Opcode, Val, CostKind, Index, Op0, Op1) +
4445 RegisterFileMoveCost;
4446}
4447
4448InstructionCost
4449X86TTIImpl::getScalarizationOverhead(VectorType *Ty, const APInt &DemandedElts,
4450 bool Insert, bool Extract,
4451 TTI::TargetCostKind CostKind) {
4452 assert(DemandedElts.getBitWidth() ==(static_cast <bool> (DemandedElts.getBitWidth() == cast
<FixedVectorType>(Ty)->getNumElements() && "Vector size mismatch"
) ? void (0) : __assert_fail ("DemandedElts.getBitWidth() == cast<FixedVectorType>(Ty)->getNumElements() && \"Vector size mismatch\""
, "llvm/lib/Target/X86/X86TargetTransformInfo.cpp", 4454, __extension__
__PRETTY_FUNCTION__))
4453 cast<FixedVectorType>(Ty)->getNumElements() &&(static_cast <bool> (DemandedElts.getBitWidth() == cast
<FixedVectorType>(Ty)->getNumElements() && "Vector size mismatch"
) ? void (0) : __assert_fail ("DemandedElts.getBitWidth() == cast<FixedVectorType>(Ty)->getNumElements() && \"Vector size mismatch\""
, "llvm/lib/Target/X86/X86TargetTransformInfo.cpp", 4454, __extension__
__PRETTY_FUNCTION__))
4454 "Vector size mismatch")(static_cast <bool> (DemandedElts.getBitWidth() == cast
<FixedVectorType>(Ty)->getNumElements() && "Vector size mismatch"
) ? void (0) : __assert_fail ("DemandedElts.getBitWidth() == cast<FixedVectorType>(Ty)->getNumElements() && \"Vector size mismatch\""
, "llvm/lib/Target/X86/X86TargetTransformInfo.cpp", 4454, __extension__
__PRETTY_FUNCTION__));
4455
4456 std::pair<InstructionCost, MVT> LT = getTypeLegalizationCost(Ty);
4457 MVT MScalarTy = LT.second.getScalarType();
4458 unsigned LegalVectorBitWidth = LT.second.getSizeInBits();
4459 InstructionCost Cost = 0;
4460
4461 constexpr unsigned LaneBitWidth = 128;
4462 assert((LegalVectorBitWidth < LaneBitWidth ||(static_cast <bool> ((LegalVectorBitWidth < LaneBitWidth
|| (LegalVectorBitWidth % LaneBitWidth) == 0) && "Illegal vector"
) ? void (0) : __assert_fail ("(LegalVectorBitWidth < LaneBitWidth || (LegalVectorBitWidth % LaneBitWidth) == 0) && \"Illegal vector\""
, "llvm/lib/Target/X86/X86TargetTransformInfo.cpp", 4464, __extension__
__PRETTY_FUNCTION__))
4463 (LegalVectorBitWidth % LaneBitWidth) == 0) &&(static_cast <bool> ((LegalVectorBitWidth < LaneBitWidth
|| (LegalVectorBitWidth % LaneBitWidth) == 0) && "Illegal vector"
) ? void (0) : __assert_fail ("(LegalVectorBitWidth < LaneBitWidth || (LegalVectorBitWidth % LaneBitWidth) == 0) && \"Illegal vector\""
, "llvm/lib/Target/X86/X86TargetTransformInfo.cpp", 4464, __extension__
__PRETTY_FUNCTION__))
4464 "Illegal vector")(static_cast <bool> ((LegalVectorBitWidth < LaneBitWidth
|| (LegalVectorBitWidth % LaneBitWidth) == 0) && "Illegal vector"
) ? void (0) : __assert_fail ("(LegalVectorBitWidth < LaneBitWidth || (LegalVectorBitWidth % LaneBitWidth) == 0) && \"Illegal vector\""
, "llvm/lib/Target/X86/X86TargetTransformInfo.cpp", 4464, __extension__
__PRETTY_FUNCTION__));
4465
4466 const int NumLegalVectors = *LT.first.getValue();
4467 assert(NumLegalVectors >= 0 && "Negative cost!")(static_cast <bool> (NumLegalVectors >= 0 &&
"Negative cost!") ? void (0) : __assert_fail ("NumLegalVectors >= 0 && \"Negative cost!\""
, "llvm/lib/Target/X86/X86TargetTransformInfo.cpp", 4467, __extension__
__PRETTY_FUNCTION__));
4468
4469 // For insertions, a ISD::BUILD_VECTOR style vector initialization can be much
4470 // cheaper than an accumulation of ISD::INSERT_VECTOR_ELT.
4471 if (Insert) {
4472 if ((MScalarTy == MVT::i16 && ST->hasSSE2()) ||
4473 (MScalarTy.isInteger() && ST->hasSSE41()) ||
4474 (MScalarTy == MVT::f32 && ST->hasSSE41())) {
4475 // For types we can insert directly, insertion into 128-bit sub vectors is
4476 // cheap, followed by a cheap chain of concatenations.
4477 if (LegalVectorBitWidth <= LaneBitWidth) {
4478 Cost += BaseT::getScalarizationOverhead(Ty, DemandedElts, Insert,
4479 /*Extract*/ false, CostKind);
4480 } else {
4481 // In each 128-lane, if at least one index is demanded but not all
4482 // indices are demanded and this 128-lane is not the first 128-lane of
4483 // the legalized-vector, then this 128-lane needs a extracti128; If in
4484 // each 128-lane, there is at least one demanded index, this 128-lane
4485 // needs a inserti128.
4486
4487 // The following cases will help you build a better understanding:
4488 // Assume we insert several elements into a v8i32 vector in avx2,
4489 // Case#1: inserting into 1th index needs vpinsrd + inserti128.
4490 // Case#2: inserting into 5th index needs extracti128 + vpinsrd +
4491 // inserti128.
4492 // Case#3: inserting into 4,5,6,7 index needs 4*vpinsrd + inserti128.
4493 assert((LegalVectorBitWidth % LaneBitWidth) == 0 && "Illegal vector")(static_cast <bool> ((LegalVectorBitWidth % LaneBitWidth
) == 0 && "Illegal vector") ? void (0) : __assert_fail
("(LegalVectorBitWidth % LaneBitWidth) == 0 && \"Illegal vector\""
, "llvm/lib/Target/X86/X86TargetTransformInfo.cpp", 4493, __extension__
__PRETTY_FUNCTION__));
4494 unsigned NumLegalLanes = LegalVectorBitWidth / LaneBitWidth;
4495 unsigned NumLanesTotal = NumLegalLanes * NumLegalVectors;
4496 unsigned NumLegalElts =
4497 LT.second.getVectorNumElements() * NumLegalVectors;
4498 assert(NumLegalElts >= DemandedElts.getBitWidth() &&(static_cast <bool> (NumLegalElts >= DemandedElts.getBitWidth
() && "Vector has been legalized to smaller element count"
) ? void (0) : __assert_fail ("NumLegalElts >= DemandedElts.getBitWidth() && \"Vector has been legalized to smaller element count\""
, "llvm/lib/Target/X86/X86TargetTransformInfo.cpp", 4499, __extension__
__PRETTY_FUNCTION__))
4499 "Vector has been legalized to smaller element count")(static_cast <bool> (NumLegalElts >= DemandedElts.getBitWidth
() && "Vector has been legalized to smaller element count"
) ? void (0) : __assert_fail ("NumLegalElts >= DemandedElts.getBitWidth() && \"Vector has been legalized to smaller element count\""
, "llvm/lib/Target/X86/X86TargetTransformInfo.cpp", 4499, __extension__
__PRETTY_FUNCTION__));
4500 assert((NumLegalElts % NumLanesTotal) == 0 &&(static_cast <bool> ((NumLegalElts % NumLanesTotal) == 0
&& "Unexpected elts per lane") ? void (0) : __assert_fail
("(NumLegalElts % NumLanesTotal) == 0 && \"Unexpected elts per lane\""
, "llvm/lib/Target/X86/X86TargetTransformInfo.cpp", 4501, __extension__
__PRETTY_FUNCTION__))
4501 "Unexpected elts per lane")(static_cast <bool> ((NumLegalElts % NumLanesTotal) == 0
&& "Unexpected elts per lane") ? void (0) : __assert_fail
("(NumLegalElts % NumLanesTotal) == 0 && \"Unexpected elts per lane\""
, "llvm/lib/Target/X86/X86TargetTransformInfo.cpp", 4501, __extension__
__PRETTY_FUNCTION__));
4502 unsigned NumEltsPerLane = NumLegalElts / NumLanesTotal;
4503
4504 APInt WidenedDemandedElts = DemandedElts.zext(NumLegalElts);
4505 auto *LaneTy =
4506 FixedVectorType::get(Ty->getElementType(), NumEltsPerLane);
4507
4508 for (unsigned I = 0; I != NumLanesTotal; ++I) {
4509 APInt LaneEltMask = WidenedDemandedElts.extractBits(
4510 NumEltsPerLane, NumEltsPerLane * I);
4511 if (LaneEltMask.isZero())
4512 continue;
4513 // FIXME: we don't need to extract if all non-demanded elements
4514 // are legalization-inserted padding.
4515 if (!LaneEltMask.isAllOnes())
4516 Cost += getShuffleCost(TTI::SK_ExtractSubvector, Ty, std::nullopt,
4517 CostKind, I * NumEltsPerLane, LaneTy);
4518 Cost += BaseT::getScalarizationOverhead(LaneTy, LaneEltMask, Insert,
4519 /*Extract*/ false, CostKind);
4520 }
4521
4522 APInt AffectedLanes =
4523 APIntOps::ScaleBitMask(WidenedDemandedElts, NumLanesTotal);
4524 APInt FullyAffectedLegalVectors = APIntOps::ScaleBitMask(
4525 AffectedLanes, NumLegalVectors, /*MatchAllBits=*/true);
4526 for (int LegalVec = 0; LegalVec != NumLegalVectors; ++LegalVec) {
4527 for (unsigned Lane = 0; Lane != NumLegalLanes; ++Lane) {
4528 unsigned I = NumLegalLanes * LegalVec + Lane;
4529 // No need to insert unaffected lane; or lane 0 of each legal vector
4530 // iff ALL lanes of that vector were affected and will be inserted.
4531 if (!AffectedLanes[I] ||
4532 (Lane == 0 && FullyAffectedLegalVectors[LegalVec]))
4533 continue;
4534 Cost += getShuffleCost(TTI::SK_InsertSubvector, Ty, std::nullopt,
4535 CostKind, I * NumEltsPerLane, LaneTy);
4536 }
4537 }
4538 }
4539 } else if (LT.second.isVector()) {
4540 // Without fast insertion, we need to use MOVD/MOVQ to pass each demanded
4541 // integer element as a SCALAR_TO_VECTOR, then we build the vector as a
4542 // series of UNPCK followed by CONCAT_VECTORS - all of these can be
4543 // considered cheap.
4544 if (Ty->isIntOrIntVectorTy())
4545 Cost += DemandedElts.popcount();
4546
4547 // Get the smaller of the legalized or original pow2-extended number of
4548 // vector elements, which represents the number of unpacks we'll end up
4549 // performing.
4550 unsigned NumElts = LT.second.getVectorNumElements();
4551 unsigned Pow2Elts =
4552 PowerOf2Ceil(cast<FixedVectorType>(Ty)->getNumElements());
4553 Cost += (std::min<unsigned>(NumElts, Pow2Elts) - 1) * LT.first;
4554 }
4555 }
4556
4557 if (Extract) {
4558 // vXi1 can be efficiently extracted with MOVMSK.
4559 // TODO: AVX512 predicate mask handling.
4560 // NOTE: This doesn't work well for roundtrip scalarization.
4561 if (!Insert && Ty->getScalarSizeInBits() == 1 && !ST->hasAVX512()) {
4562 unsigned NumElts = cast<FixedVectorType>(Ty)->getNumElements();
4563 unsigned MaxElts = ST->hasAVX2() ? 32 : 16;
4564 unsigned MOVMSKCost = (NumElts + MaxElts - 1) / MaxElts;
4565 return MOVMSKCost;
4566 }
4567
4568 if (LT.second.isVector()) {
4569 unsigned NumLegalElts =
4570 LT.second.getVectorNumElements() * NumLegalVectors;
4571 assert(NumLegalElts >= DemandedElts.getBitWidth() &&(static_cast <bool> (NumLegalElts >= DemandedElts.getBitWidth
() && "Vector has been legalized to smaller element count"
) ? void (0) : __assert_fail ("NumLegalElts >= DemandedElts.getBitWidth() && \"Vector has been legalized to smaller element count\""
, "llvm/lib/Target/X86/X86TargetTransformInfo.cpp", 4572, __extension__
__PRETTY_FUNCTION__))
4572 "Vector has been legalized to smaller element count")(static_cast <bool> (NumLegalElts >= DemandedElts.getBitWidth
() && "Vector has been legalized to smaller element count"
) ? void (0) : __assert_fail ("NumLegalElts >= DemandedElts.getBitWidth() && \"Vector has been legalized to smaller element count\""
, "llvm/lib/Target/X86/X86TargetTransformInfo.cpp", 4572, __extension__
__PRETTY_FUNCTION__));
4573
4574 // If we're extracting elements from a 128-bit subvector lane,
4575 // we only need to extract each lane once, not for every element.
4576 if (LegalVectorBitWidth > LaneBitWidth) {
4577 unsigned NumLegalLanes = LegalVectorBitWidth / LaneBitWidth;
4578 unsigned NumLanesTotal = NumLegalLanes * NumLegalVectors;
4579 assert((NumLegalElts % NumLanesTotal) == 0 &&(static_cast <bool> ((NumLegalElts % NumLanesTotal) == 0
&& "Unexpected elts per lane") ? void (0) : __assert_fail
("(NumLegalElts % NumLanesTotal) == 0 && \"Unexpected elts per lane\""
, "llvm/lib/Target/X86/X86TargetTransformInfo.cpp", 4580, __extension__
__PRETTY_FUNCTION__))
4580 "Unexpected elts per lane")(static_cast <bool> ((NumLegalElts % NumLanesTotal) == 0
&& "Unexpected elts per lane") ? void (0) : __assert_fail
("(NumLegalElts % NumLanesTotal) == 0 && \"Unexpected elts per lane\""
, "llvm/lib/Target/X86/X86TargetTransformInfo.cpp", 4580, __extension__
__PRETTY_FUNCTION__));
4581 unsigned NumEltsPerLane = NumLegalElts / NumLanesTotal;
4582
4583 // Add cost for each demanded 128-bit subvector extraction.
4584 // Luckily this is a lot easier than for insertion.
4585 APInt WidenedDemandedElts = DemandedElts.zext(NumLegalElts);
4586 auto *LaneTy =
4587 FixedVectorType::get(Ty->getElementType(), NumEltsPerLane);
4588
4589 for (unsigned I = 0; I != NumLanesTotal; ++I) {
4590 APInt LaneEltMask = WidenedDemandedElts.extractBits(
4591 NumEltsPerLane, I * NumEltsPerLane);
4592 if (LaneEltMask.isZero())
4593 continue;
4594 Cost += getShuffleCost(TTI::SK_ExtractSubvector, Ty, std::nullopt,
4595 CostKind, I * NumEltsPerLane, LaneTy);
4596 Cost += BaseT::getScalarizationOverhead(
4597 LaneTy, LaneEltMask, /*Insert*/ false, Extract, CostKind);
4598 }
4599
4600 return Cost;
4601 }
4602 }
4603
4604 // Fallback to default extraction.
4605 Cost += BaseT::getScalarizationOverhead(Ty, DemandedElts, /*Insert*/ false,
4606 Extract, CostKind);
4607 }
4608
4609 return Cost;
4610}
4611
4612InstructionCost
4613X86TTIImpl::getReplicationShuffleCost(Type *EltTy, int ReplicationFactor,
4614 int VF, const APInt &DemandedDstElts,
4615 TTI::TargetCostKind CostKind) {
4616 const unsigned EltTyBits = DL.getTypeSizeInBits(EltTy);
4617 // We don't differentiate element types here, only element bit width.
4618 EltTy = IntegerType::getIntNTy(EltTy->getContext(), EltTyBits);
4619
4620 auto bailout = [&]() {
4621 return BaseT::getReplicationShuffleCost(EltTy, ReplicationFactor, VF,
4622 DemandedDstElts, CostKind);
4623 };
4624
4625 // For now, only deal with AVX512 cases.
4626 if (!ST->hasAVX512())
4627 return bailout();
4628
4629 // Do we have a native shuffle for this element type, or should we promote?
4630 unsigned PromEltTyBits = EltTyBits;
4631 switch (EltTyBits) {
4632 case 32:
4633 case 64:
4634 break; // AVX512F.
4635 case 16:
4636 if (!ST->hasBWI())
4637 PromEltTyBits = 32; // promote to i32, AVX512F.
4638 break; // AVX512BW
4639 case 8:
4640 if (!ST->hasVBMI())
4641 PromEltTyBits = 32; // promote to i32, AVX512F.
4642 break; // AVX512VBMI
4643 case 1:
4644 // There is no support for shuffling i1 elements. We *must* promote.
4645 if (ST->hasBWI()) {
4646 if (ST->hasVBMI())
4647 PromEltTyBits = 8; // promote to i8, AVX512VBMI.
4648 else
4649 PromEltTyBits = 16; // promote to i16, AVX512BW.
4650 break;
4651 }
4652 PromEltTyBits = 32; // promote to i32, AVX512F.
4653 break;
4654 default:
4655 return bailout();
4656 }
4657 auto *PromEltTy = IntegerType::getIntNTy(EltTy->getContext(), PromEltTyBits);
4658
4659 auto *SrcVecTy = FixedVectorType::get(EltTy, VF);
4660 auto *PromSrcVecTy = FixedVectorType::get(PromEltTy, VF);
4661
4662 int NumDstElements = VF * ReplicationFactor;
4663 auto *PromDstVecTy = FixedVectorType::get(PromEltTy, NumDstElements);
4664 auto *DstVecTy = FixedVectorType::get(EltTy, NumDstElements);
4665
4666 // Legalize the types.
4667 MVT LegalSrcVecTy = getTypeLegalizationCost(SrcVecTy).second;
4668 MVT LegalPromSrcVecTy = getTypeLegalizationCost(PromSrcVecTy).second;
4669 MVT LegalPromDstVecTy = getTypeLegalizationCost(PromDstVecTy).second;
4670 MVT LegalDstVecTy = getTypeLegalizationCost(DstVecTy).second;
4671 // They should have legalized into vector types.
4672 if (!LegalSrcVecTy.isVector() || !LegalPromSrcVecTy.isVector() ||
4673 !LegalPromDstVecTy.isVector() || !LegalDstVecTy.isVector())
4674 return bailout();
4675
4676 if (PromEltTyBits != EltTyBits) {
4677 // If we have to perform the shuffle with wider elt type than our data type,
4678 // then we will first need to anyext (we don't care about the new bits)
4679 // the source elements, and then truncate Dst elements.
4680 InstructionCost PromotionCost;
4681 PromotionCost += getCastInstrCost(
4682 Instruction::SExt, /*Dst=*/PromSrcVecTy, /*Src=*/SrcVecTy,
4683 TargetTransformInfo::CastContextHint::None, CostKind);
4684 PromotionCost +=
4685 getCastInstrCost(Instruction::Trunc, /*Dst=*/DstVecTy,
4686 /*Src=*/PromDstVecTy,
4687 TargetTransformInfo::CastContextHint::None, CostKind);
4688 return PromotionCost + getReplicationShuffleCost(PromEltTy,
4689 ReplicationFactor, VF,
4690 DemandedDstElts, CostKind);
4691 }
4692
4693 assert(LegalSrcVecTy.getScalarSizeInBits() == EltTyBits &&(static_cast <bool> (LegalSrcVecTy.getScalarSizeInBits(
) == EltTyBits && LegalSrcVecTy.getScalarType() == LegalDstVecTy
.getScalarType() && "We expect that the legalization doesn't affect the element width, "
"doesn't coalesce/split elements.") ? void (0) : __assert_fail
("LegalSrcVecTy.getScalarSizeInBits() == EltTyBits && LegalSrcVecTy.getScalarType() == LegalDstVecTy.getScalarType() && \"We expect that the legalization doesn't affect the element width, \" \"doesn't coalesce/split elements.\""
, "llvm/lib/Target/X86/X86TargetTransformInfo.cpp", 4696, __extension__
__PRETTY_FUNCTION__))
4694 LegalSrcVecTy.getScalarType() == LegalDstVecTy.getScalarType() &&(static_cast <bool> (LegalSrcVecTy.getScalarSizeInBits(
) == EltTyBits && LegalSrcVecTy.getScalarType() == LegalDstVecTy
.getScalarType() && "We expect that the legalization doesn't affect the element width, "
"doesn't coalesce/split elements.") ? void (0) : __assert_fail
("LegalSrcVecTy.getScalarSizeInBits() == EltTyBits && LegalSrcVecTy.getScalarType() == LegalDstVecTy.getScalarType() && \"We expect that the legalization doesn't affect the element width, \" \"doesn't coalesce/split elements.\""
, "llvm/lib/Target/X86/X86TargetTransformInfo.cpp", 4696, __extension__
__PRETTY_FUNCTION__))
4695 "We expect that the legalization doesn't affect the element width, "(static_cast <bool> (LegalSrcVecTy.getScalarSizeInBits(
) == EltTyBits && LegalSrcVecTy.getScalarType() == LegalDstVecTy
.getScalarType() && "We expect that the legalization doesn't affect the element width, "
"doesn't coalesce/split elements.") ? void (0) : __assert_fail
("LegalSrcVecTy.getScalarSizeInBits() == EltTyBits && LegalSrcVecTy.getScalarType() == LegalDstVecTy.getScalarType() && \"We expect that the legalization doesn't affect the element width, \" \"doesn't coalesce/split elements.\""
, "llvm/lib/Target/X86/X86TargetTransformInfo.cpp", 4696, __extension__
__PRETTY_FUNCTION__))
4696 "doesn't coalesce/split elements.")(static_cast <bool> (LegalSrcVecTy.getScalarSizeInBits(
) == EltTyBits && LegalSrcVecTy.getScalarType() == LegalDstVecTy
.getScalarType() && "We expect that the legalization doesn't affect the element width, "
"doesn't coalesce/split elements.") ? void (0) : __assert_fail
("LegalSrcVecTy.getScalarSizeInBits() == EltTyBits && LegalSrcVecTy.getScalarType() == LegalDstVecTy.getScalarType() && \"We expect that the legalization doesn't affect the element width, \" \"doesn't coalesce/split elements.\""
, "llvm/lib/Target/X86/X86TargetTransformInfo.cpp", 4696, __extension__
__PRETTY_FUNCTION__));
4697
4698 unsigned NumEltsPerDstVec = LegalDstVecTy.getVectorNumElements();
4699 unsigned NumDstVectors =
4700 divideCeil(DstVecTy->getNumElements(), NumEltsPerDstVec);
4701
4702 auto *SingleDstVecTy = FixedVectorType::get(EltTy, NumEltsPerDstVec);
4703
4704 // Not all the produced Dst elements may be demanded. In our case,
4705 // given that a single Dst vector is formed by a single shuffle,
4706 // if all elements that will form a single Dst vector aren't demanded,
4707 // then we won't need to do that shuffle, so adjust the cost accordingly.
4708 APInt DemandedDstVectors = APIntOps::ScaleBitMask(
4709 DemandedDstElts.zext(NumDstVectors * NumEltsPerDstVec), NumDstVectors);
4710 unsigned NumDstVectorsDemanded = DemandedDstVectors.popcount();
4711
4712 InstructionCost SingleShuffleCost = getShuffleCost(
4713 TTI::SK_PermuteSingleSrc, SingleDstVecTy, /*Mask=*/std::nullopt, CostKind,
4714 /*Index=*/0, /*SubTp=*/nullptr);
4715 return NumDstVectorsDemanded * SingleShuffleCost;
4716}
4717
4718InstructionCost X86TTIImpl::getMemoryOpCost(unsigned Opcode, Type *Src,
4719 MaybeAlign Alignment,
4720 unsigned AddressSpace,
4721 TTI::TargetCostKind CostKind,
4722 TTI::OperandValueInfo OpInfo,
4723 const Instruction *I) {
4724 // TODO: Handle other cost kinds.
4725 if (CostKind != TTI::TCK_RecipThroughput) {
4726 if (auto *SI = dyn_cast_or_null<StoreInst>(I)) {
4727 // Store instruction with index and scale costs 2 Uops.
4728 // Check the preceding GEP to identify non-const indices.
4729 if (auto *GEP = dyn_cast<GetElementPtrInst>(SI->getPointerOperand())) {
4730 if (!all_of(GEP->indices(), [](Value *V) { return isa<Constant>(V); }))
4731 return TTI::TCC_Basic * 2;
4732 }
4733 }
4734 return TTI::TCC_Basic;
4735 }
4736
4737 assert((Opcode == Instruction::Load || Opcode == Instruction::Store) &&(static_cast <bool> ((Opcode == Instruction::Load || Opcode
== Instruction::Store) && "Invalid Opcode") ? void (
0) : __assert_fail ("(Opcode == Instruction::Load || Opcode == Instruction::Store) && \"Invalid Opcode\""
, "llvm/lib/Target/X86/X86TargetTransformInfo.cpp", 4738, __extension__
__PRETTY_FUNCTION__))
4738 "Invalid Opcode")(static_cast <bool> ((Opcode == Instruction::Load || Opcode
== Instruction::Store) && "Invalid Opcode") ? void (
0) : __assert_fail ("(Opcode == Instruction::Load || Opcode == Instruction::Store) && \"Invalid Opcode\""
, "llvm/lib/Target/X86/X86TargetTransformInfo.cpp", 4738, __extension__
__PRETTY_FUNCTION__));
4739 // Type legalization can't handle structs
4740 if (TLI->getValueType(DL, Src, true) == MVT::Other)
4741 return BaseT::getMemoryOpCost(Opcode, Src, Alignment, AddressSpace,
4742 CostKind);
4743
4744 // Legalize the type.
4745 std::pair<InstructionCost, MVT> LT = getTypeLegalizationCost(Src);
4746
4747 auto *VTy = dyn_cast<FixedVectorType>(Src);
4748
4749 InstructionCost Cost = 0;
4750
4751 // Add a cost for constant load to vector.
4752 if (Opcode == Instruction::Store && OpInfo.isConstant())
4753 Cost += getMemoryOpCost(Instruction::Load, Src, DL.getABITypeAlign(Src),
4754 /*AddressSpace=*/0, CostKind);
4755
4756 // Handle the simple case of non-vectors.
4757 // NOTE: this assumes that legalization never creates vector from scalars!
4758 if (!VTy || !LT.second.isVector()) {
4759 // Each load/store unit costs 1.
4760 return (LT.second.isFloatingPoint() ? Cost : 0) + LT.first * 1;
4761 }
4762
4763 bool IsLoad = Opcode == Instruction::Load;
4764
4765 Type *EltTy = VTy->getElementType();
4766
4767 const int EltTyBits = DL.getTypeSizeInBits(EltTy);
4768
4769 // Source of truth: how many elements were there in the original IR vector?
4770 const unsigned SrcNumElt = VTy->getNumElements();
4771
4772 // How far have we gotten?
4773 int NumEltRemaining = SrcNumElt;
4774 // Note that we intentionally capture by-reference, NumEltRemaining changes.
4775 auto NumEltDone = [&]() { return SrcNumElt - NumEltRemaining; };
4776
4777 const int MaxLegalOpSizeBytes = divideCeil(LT.second.getSizeInBits(), 8);
4778
4779 // Note that even if we can store 64 bits of an XMM, we still operate on XMM.
4780 const unsigned XMMBits = 128;
4781 if (XMMBits % EltTyBits != 0)
4782 // Vector size must be a multiple of the element size. I.e. no padding.
4783 return BaseT::getMemoryOpCost(Opcode, Src, Alignment, AddressSpace,
4784 CostKind);
4785 const int NumEltPerXMM = XMMBits / EltTyBits;
4786
4787 auto *XMMVecTy = FixedVectorType::get(EltTy, NumEltPerXMM);
4788
4789 for (int CurrOpSizeBytes = MaxLegalOpSizeBytes, SubVecEltsLeft = 0;
4790 NumEltRemaining > 0; CurrOpSizeBytes /= 2) {
4791 // How many elements would a single op deal with at once?
4792 if ((8 * CurrOpSizeBytes) % EltTyBits != 0)
4793 // Vector size must be a multiple of the element size. I.e. no padding.
4794 return BaseT::getMemoryOpCost(Opcode, Src, Alignment, AddressSpace,
4795 CostKind);
4796 int CurrNumEltPerOp = (8 * CurrOpSizeBytes) / EltTyBits;
4797
4798 assert(CurrOpSizeBytes > 0 && CurrNumEltPerOp > 0 && "How'd we get here?")(static_cast <bool> (CurrOpSizeBytes > 0 && CurrNumEltPerOp
> 0 && "How'd we get here?") ? void (0) : __assert_fail
("CurrOpSizeBytes > 0 && CurrNumEltPerOp > 0 && \"How'd we get here?\""
, "llvm/lib/Target/X86/X86TargetTransformInfo.cpp", 4798, __extension__
__PRETTY_FUNCTION__));
4799 assert((((NumEltRemaining * EltTyBits) < (2 * 8 * CurrOpSizeBytes)) ||(static_cast <bool> ((((NumEltRemaining * EltTyBits) <
(2 * 8 * CurrOpSizeBytes)) || (CurrOpSizeBytes == MaxLegalOpSizeBytes
)) && "Unless we haven't halved the op size yet, " "we have less than two op's sized units of work left."
) ? void (0) : __assert_fail ("(((NumEltRemaining * EltTyBits) < (2 * 8 * CurrOpSizeBytes)) || (CurrOpSizeBytes == MaxLegalOpSizeBytes)) && \"Unless we haven't halved the op size yet, \" \"we have less than two op's sized units of work left.\""
, "llvm/lib/Target/X86/X86TargetTransformInfo.cpp", 4802, __extension__
__PRETTY_FUNCTION__))
4800 (CurrOpSizeBytes == MaxLegalOpSizeBytes)) &&(static_cast <bool> ((((NumEltRemaining * EltTyBits) <
(2 * 8 * CurrOpSizeBytes)) || (CurrOpSizeBytes == MaxLegalOpSizeBytes
)) && "Unless we haven't halved the op size yet, " "we have less than two op's sized units of work left."
) ? void (0) : __assert_fail ("(((NumEltRemaining * EltTyBits) < (2 * 8 * CurrOpSizeBytes)) || (CurrOpSizeBytes == MaxLegalOpSizeBytes)) && \"Unless we haven't halved the op size yet, \" \"we have less than two op's sized units of work left.\""
, "llvm/lib/Target/X86/X86TargetTransformInfo.cpp", 4802, __extension__
__PRETTY_FUNCTION__))
4801 "Unless we haven't halved the op size yet, "(static_cast <bool> ((((NumEltRemaining * EltTyBits) <
(2 * 8 * CurrOpSizeBytes)) || (CurrOpSizeBytes == MaxLegalOpSizeBytes
)) && "Unless we haven't halved the op size yet, " "we have less than two op's sized units of work left."
) ? void (0) : __assert_fail ("(((NumEltRemaining * EltTyBits) < (2 * 8 * CurrOpSizeBytes)) || (CurrOpSizeBytes == MaxLegalOpSizeBytes)) && \"Unless we haven't halved the op size yet, \" \"we have less than two op's sized units of work left.\""
, "llvm/lib/Target/X86/X86TargetTransformInfo.cpp", 4802, __extension__
__PRETTY_FUNCTION__))
4802 "we have less than two op's sized units of work left.")(static_cast <bool> ((((NumEltRemaining * EltTyBits) <
(2 * 8 * CurrOpSizeBytes)) || (CurrOpSizeBytes == MaxLegalOpSizeBytes
)) && "Unless we haven't halved the op size yet, " "we have less than two op's sized units of work left."
) ? void (0) : __assert_fail ("(((NumEltRemaining * EltTyBits) < (2 * 8 * CurrOpSizeBytes)) || (CurrOpSizeBytes == MaxLegalOpSizeBytes)) && \"Unless we haven't halved the op size yet, \" \"we have less than two op's sized units of work left.\""
, "llvm/lib/Target/X86/X86TargetTransformInfo.cpp", 4802, __extension__
__PRETTY_FUNCTION__));
4803
4804 auto *CurrVecTy = CurrNumEltPerOp > NumEltPerXMM
4805 ? FixedVectorType::get(EltTy, CurrNumEltPerOp)
4806 : XMMVecTy;
4807
4808 assert(CurrVecTy->getNumElements() % CurrNumEltPerOp == 0 &&(static_cast <bool> (CurrVecTy->getNumElements() % CurrNumEltPerOp
== 0 && "After halving sizes, the vector elt count is no longer a multiple "
"of number of elements per operation?") ? void (0) : __assert_fail
("CurrVecTy->getNumElements() % CurrNumEltPerOp == 0 && \"After halving sizes, the vector elt count is no longer a multiple \" \"of number of elements per operation?\""
, "llvm/lib/Target/X86/X86TargetTransformInfo.cpp", 4810, __extension__
__PRETTY_FUNCTION__))
4809 "After halving sizes, the vector elt count is no longer a multiple "(static_cast <bool> (CurrVecTy->getNumElements() % CurrNumEltPerOp
== 0 && "After halving sizes, the vector elt count is no longer a multiple "
"of number of elements per operation?") ? void (0) : __assert_fail
("CurrVecTy->getNumElements() % CurrNumEltPerOp == 0 && \"After halving sizes, the vector elt count is no longer a multiple \" \"of number of elements per operation?\""
, "llvm/lib/Target/X86/X86TargetTransformInfo.cpp", 4810, __extension__
__PRETTY_FUNCTION__))
4810 "of number of elements per operation?")(static_cast <bool> (CurrVecTy->getNumElements() % CurrNumEltPerOp
== 0 && "After halving sizes, the vector elt count is no longer a multiple "
"of number of elements per operation?") ? void (0) : __assert_fail
("CurrVecTy->getNumElements() % CurrNumEltPerOp == 0 && \"After halving sizes, the vector elt count is no longer a multiple \" \"of number of elements per operation?\""
, "llvm/lib/Target/X86/X86TargetTransformInfo.cpp", 4810, __extension__
__PRETTY_FUNCTION__));
4811 auto *CoalescedVecTy =
4812 CurrNumEltPerOp == 1
4813 ? CurrVecTy
4814 : FixedVectorType::get(
4815 IntegerType::get(Src->getContext(),
4816 EltTyBits * CurrNumEltPerOp),
4817 CurrVecTy->getNumElements() / CurrNumEltPerOp);
4818 assert(DL.getTypeSizeInBits(CoalescedVecTy) ==(static_cast <bool> (DL.getTypeSizeInBits(CoalescedVecTy
) == DL.getTypeSizeInBits(CurrVecTy) && "coalesciing elements doesn't change vector width."
) ? void (0) : __assert_fail ("DL.getTypeSizeInBits(CoalescedVecTy) == DL.getTypeSizeInBits(CurrVecTy) && \"coalesciing elements doesn't change vector width.\""
, "llvm/lib/Target/X86/X86TargetTransformInfo.cpp", 4820, __extension__
__PRETTY_FUNCTION__))
4819 DL.getTypeSizeInBits(CurrVecTy) &&(static_cast <bool> (DL.getTypeSizeInBits(CoalescedVecTy
) == DL.getTypeSizeInBits(CurrVecTy) && "coalesciing elements doesn't change vector width."
) ? void (0) : __assert_fail ("DL.getTypeSizeInBits(CoalescedVecTy) == DL.getTypeSizeInBits(CurrVecTy) && \"coalesciing elements doesn't change vector width.\""
, "llvm/lib/Target/X86/X86TargetTransformInfo.cpp", 4820, __extension__
__PRETTY_FUNCTION__))
4820 "coalesciing elements doesn't change vector width.")(static_cast <bool> (DL.getTypeSizeInBits(CoalescedVecTy
) == DL.getTypeSizeInBits(CurrVecTy) && "coalesciing elements doesn't change vector width."
) ? void (0) : __assert_fail ("DL.getTypeSizeInBits(CoalescedVecTy) == DL.getTypeSizeInBits(CurrVecTy) && \"coalesciing elements doesn't change vector width.\""
, "llvm/lib/Target/X86/X86TargetTransformInfo.cpp", 4820, __extension__
__PRETTY_FUNCTION__));
4821
4822 while (NumEltRemaining > 0) {
4823 assert(SubVecEltsLeft >= 0 && "Subreg element count overconsumtion?")(static_cast <bool> (SubVecEltsLeft >= 0 && "Subreg element count overconsumtion?"
) ? void (0) : __assert_fail ("SubVecEltsLeft >= 0 && \"Subreg element count overconsumtion?\""
, "llvm/lib/Target/X86/X86TargetTransformInfo.cpp", 4823, __extension__
__PRETTY_FUNCTION__));
4824
4825 // Can we use this vector size, as per the remaining element count?
4826 // Iff the vector is naturally aligned, we can do a wide load regardless.
4827 if (NumEltRemaining < CurrNumEltPerOp &&
4828 (!IsLoad || Alignment.valueOrOne() < CurrOpSizeBytes) &&
4829 CurrOpSizeBytes != 1)
4830 break; // Try smalled vector size.
4831
4832 bool Is0thSubVec = (NumEltDone() % LT.second.getVectorNumElements()) == 0;
4833
4834 // If we have fully processed the previous reg, we need to replenish it.
4835 if (SubVecEltsLeft == 0) {
4836 SubVecEltsLeft += CurrVecTy->getNumElements();
4837 // And that's free only for the 0'th subvector of a legalized vector.
4838 if (!Is0thSubVec)
4839 Cost += getShuffleCost(IsLoad ? TTI::ShuffleKind::SK_InsertSubvector
4840 : TTI::ShuffleKind::SK_ExtractSubvector,
4841 VTy, std::nullopt, CostKind, NumEltDone(),
4842 CurrVecTy);
4843 }
4844
4845 // While we can directly load/store ZMM, YMM, and 64-bit halves of XMM,
4846 // for smaller widths (32/16/8) we have to insert/extract them separately.
4847 // Again, it's free for the 0'th subreg (if op is 32/64 bit wide,
4848 // but let's pretend that it is also true for 16/8 bit wide ops...)
4849 if (CurrOpSizeBytes <= 32 / 8 && !Is0thSubVec) {
4850 int NumEltDoneInCurrXMM = NumEltDone() % NumEltPerXMM;
4851 assert(NumEltDoneInCurrXMM % CurrNumEltPerOp == 0 && "")(static_cast <bool> (NumEltDoneInCurrXMM % CurrNumEltPerOp
== 0 && "") ? void (0) : __assert_fail ("NumEltDoneInCurrXMM % CurrNumEltPerOp == 0 && \"\""
, "llvm/lib/Target/X86/X86TargetTransformInfo.cpp", 4851, __extension__
__PRETTY_FUNCTION__));
4852 int CoalescedVecEltIdx = NumEltDoneInCurrXMM / CurrNumEltPerOp;
4853 APInt DemandedElts =
4854 APInt::getBitsSet(CoalescedVecTy->getNumElements(),
4855 CoalescedVecEltIdx, CoalescedVecEltIdx + 1);
4856 assert(DemandedElts.popcount() == 1 && "Inserting single value")(static_cast <bool> (DemandedElts.popcount() == 1 &&
"Inserting single value") ? void (0) : __assert_fail ("DemandedElts.popcount() == 1 && \"Inserting single value\""
, "llvm/lib/Target/X86/X86TargetTransformInfo.cpp", 4856, __extension__
__PRETTY_FUNCTION__));
4857 Cost += getScalarizationOverhead(CoalescedVecTy, DemandedElts, IsLoad,
4858 !IsLoad, CostKind);
4859 }
4860
4861 // This isn't exactly right. We're using slow unaligned 32-byte accesses
4862 // as a proxy for a double-pumped AVX memory interface such as on
4863 // Sandybridge.
4864 // Sub-32-bit loads/stores will be slower either with PINSR*/PEXTR* or
4865 // will be scalarized.
4866 if (CurrOpSizeBytes == 32 && ST->isUnalignedMem32Slow())
4867 Cost += 2;
4868 else if (CurrOpSizeBytes < 4)
4869 Cost += 2;
4870 else
4871 Cost += 1;
4872
4873 SubVecEltsLeft -= CurrNumEltPerOp;
4874 NumEltRemaining -= CurrNumEltPerOp;
4875 Alignment = commonAlignment(Alignment.valueOrOne(), CurrOpSizeBytes);
4876 }
4877 }
4878
4879 assert(NumEltRemaining <= 0 && "Should have processed all the elements.")(static_cast <bool> (NumEltRemaining <= 0 &&
"Should have processed all the elements.") ? void (0) : __assert_fail
("NumEltRemaining <= 0 && \"Should have processed all the elements.\""
, "llvm/lib/Target/X86/X86TargetTransformInfo.cpp", 4879, __extension__
__PRETTY_FUNCTION__));
4880
4881 return Cost;
4882}
4883
4884InstructionCost
4885X86TTIImpl::getMaskedMemoryOpCost(unsigned Opcode, Type *SrcTy, Align Alignment,
4886 unsigned AddressSpace,
4887 TTI::TargetCostKind CostKind) {
4888 bool IsLoad = (Instruction::Load == Opcode);
4889 bool IsStore = (Instruction::Store == Opcode);
4890
4891 auto *SrcVTy = dyn_cast<FixedVectorType>(SrcTy);
4892 if (!SrcVTy)
4893 // To calculate scalar take the regular cost, without mask
4894 return getMemoryOpCost(Opcode, SrcTy, Alignment, AddressSpace, CostKind);
4895
4896 unsigned NumElem = SrcVTy->getNumElements();
4897 auto *MaskTy =
4898 FixedVectorType::get(Type::getInt8Ty(SrcVTy->getContext()), NumElem);
4899 if ((IsLoad && !isLegalMaskedLoad(SrcVTy, Alignment)) ||
4900 (IsStore && !isLegalMaskedStore(SrcVTy, Alignment))) {
4901 // Scalarization
4902 APInt DemandedElts = APInt::getAllOnes(NumElem);
4903 InstructionCost MaskSplitCost = getScalarizationOverhead(
4904 MaskTy, DemandedElts, /*Insert*/ false, /*Extract*/ true, CostKind);
4905 InstructionCost ScalarCompareCost = getCmpSelInstrCost(
4906 Instruction::ICmp, Type::getInt8Ty(SrcVTy->getContext()), nullptr,
4907 CmpInst::BAD_ICMP_PREDICATE, CostKind);
4908 InstructionCost BranchCost = getCFInstrCost(Instruction::Br, CostKind);
4909 InstructionCost MaskCmpCost = NumElem * (BranchCost + ScalarCompareCost);
4910 InstructionCost ValueSplitCost = getScalarizationOverhead(
4911 SrcVTy, DemandedElts, IsLoad, IsStore, CostKind);
4912 InstructionCost MemopCost =
4913 NumElem * BaseT::getMemoryOpCost(Opcode, SrcVTy->getScalarType(),
4914 Alignment, AddressSpace, CostKind);
4915 return MemopCost + ValueSplitCost + MaskSplitCost + MaskCmpCost;
4916 }
4917
4918 // Legalize the type.
4919 std::pair<InstructionCost, MVT> LT = getTypeLegalizationCost(SrcVTy);
4920 auto VT = TLI->getValueType(DL, SrcVTy);
4921 InstructionCost Cost = 0;
4922 if (VT.isSimple() && LT.second != VT.getSimpleVT() &&
4923 LT.second.getVectorNumElements() == NumElem)
4924 // Promotion requires extend/truncate for data and a shuffle for mask.
4925 Cost += getShuffleCost(TTI::SK_PermuteTwoSrc, SrcVTy, std::nullopt,
4926 CostKind, 0, nullptr) +
4927 getShuffleCost(TTI::SK_PermuteTwoSrc, MaskTy, std::nullopt,
4928 CostKind, 0, nullptr);
4929
4930 else if (LT.first * LT.second.getVectorNumElements() > NumElem) {
4931 auto *NewMaskTy = FixedVectorType::get(MaskTy->getElementType(),
4932 LT.second.getVectorNumElements());
4933 // Expanding requires fill mask with zeroes
4934 Cost += getShuffleCost(TTI::SK_InsertSubvector, NewMaskTy, std::nullopt,
4935 CostKind, 0, MaskTy);
4936 }
4937
4938 // Pre-AVX512 - each maskmov load costs 2 + store costs ~8.
4939 if (!ST->hasAVX512())
4940 return Cost + LT.first * (IsLoad ? 2 : 8);
4941
4942 // AVX-512 masked load/store is cheaper
4943 return Cost + LT.first;
4944}
4945
4946InstructionCost X86TTIImpl::getPointersChainCost(
4947 ArrayRef<const Value *> Ptrs, const Value *Base,
4948 const TTI::PointersChainInfo &Info, TTI::TargetCostKind CostKind) {
4949 if (Info.isSameBase() && Info.isKnownStride()) {
4950 // If all the pointers have known stride all the differences are translated
4951 // into constants. X86 memory addressing allows encoding it into
4952 // displacement. So we just need to take the base GEP cost.
4953 if (const auto *BaseGEP = dyn_cast<GetElementPtrInst>(Base)) {
4954 SmallVector<const Value *> Indices(BaseGEP->indices());
4955 return getGEPCost(BaseGEP->getSourceElementType(),
4956 BaseGEP->getPointerOperand(), Indices, CostKind);
4957 }
4958 return TTI::TCC_Free;
4959 }
4960 return BaseT::getPointersChainCost(Ptrs, Base, Info, CostKind);
4961}
4962
4963InstructionCost X86TTIImpl::getAddressComputationCost(Type *Ty,
4964 ScalarEvolution *SE,
4965 const SCEV *Ptr) {
4966 // Address computations in vectorized code with non-consecutive addresses will
4967 // likely result in more instructions compared to scalar code where the
4968 // computation can more often be merged into the index mode. The resulting
4969 // extra micro-ops can significantly decrease throughput.
4970 const unsigned NumVectorInstToHideOverhead = 10;
4971
4972 // Cost modeling of Strided Access Computation is hidden by the indexing
4973 // modes of X86 regardless of the stride value. We dont believe that there
4974 // is a difference between constant strided access in gerenal and constant
4975 // strided value which is less than or equal to 64.
4976 // Even in the case of (loop invariant) stride whose value is not known at
4977 // compile time, the address computation will not incur more than one extra
4978 // ADD instruction.
4979 if (Ty->isVectorTy() && SE && !ST->hasAVX2()) {
4980 // TODO: AVX2 is the current cut-off because we don't have correct
4981 // interleaving costs for prior ISA's.
4982 if (!BaseT::isStridedAccess(Ptr))
4983 return NumVectorInstToHideOverhead;
4984 if (!BaseT::getConstantStrideStep(SE, Ptr))
4985 return 1;
4986 }
4987
4988 return BaseT::getAddressComputationCost(Ty, SE, Ptr);
4989}
4990
4991InstructionCost
4992X86TTIImpl::getArithmeticReductionCost(unsigned Opcode, VectorType *ValTy,
4993 std::optional<FastMathFlags> FMF,
4994 TTI::TargetCostKind CostKind) {
4995 if (TTI::requiresOrderedReduction(FMF))
4996 return BaseT::getArithmeticReductionCost(Opcode, ValTy, FMF, CostKind);
4997
4998 // We use the Intel Architecture Code Analyzer(IACA) to measure the throughput
4999 // and make it as the cost.
5000
5001 static const CostTblEntry SLMCostTbl[] = {
5002 { ISD::FADD, MVT::v2f64, 3 },
5003 { ISD::ADD, MVT::v2i64, 5 },
5004 };
5005
5006 static const CostTblEntry SSE2CostTbl[] = {
5007 { ISD::FADD, MVT::v2f64, 2 },
5008 { ISD::FADD, MVT::v2f32, 2 },
5009 { ISD::FADD, MVT::v4f32, 4 },
5010 { ISD::ADD, MVT::v2i64, 2 }, // The data reported by the IACA tool is "1.6".
5011 { ISD::ADD, MVT::v2i32, 2 }, // FIXME: chosen to be less than v4i32
5012 { ISD::ADD, MVT::v4i32, 3 }, // The data reported by the IACA tool is "3.3".
5013 { ISD::ADD, MVT::v2i16, 2 }, // The data reported by the IACA tool is "4.3".
5014 { ISD::ADD, MVT::v4i16, 3 }, // The data reported by the IACA tool is "4.3".
5015 { ISD::ADD, MVT::v8i16, 4 }, // The data reported by the IACA tool is "4.3".
5016 { ISD::ADD, MVT::v2i8, 2 },
5017 { ISD::ADD, MVT::v4i8, 2 },
5018 { ISD::ADD, MVT::v8i8, 2 },
5019 { ISD::ADD, MVT::v16i8, 3 },
5020 };
5021
5022 static const CostTblEntry AVX1CostTbl[] = {
5023 { ISD::FADD, MVT::v4f64, 3 },
5024 { ISD::FADD, MVT::v4f32, 3 },
5025 { ISD::FADD, MVT::v8f32, 4 },
5026 { ISD::ADD, MVT::v2i64, 1 }, // The data reported by the IACA tool is "1.5".
5027 { ISD::ADD, MVT::v4i64, 3 },
5028 { ISD::ADD, MVT::v8i32, 5 },
5029 { ISD::ADD, MVT::v16i16, 5 },
5030 { ISD::ADD, MVT::v32i8, 4 },
5031 };
5032
5033 int ISD = TLI->InstructionOpcodeToISD(Opcode);
5034 assert(ISD && "Invalid opcode")(static_cast <bool> (ISD && "Invalid opcode") ?
void (0) : __assert_fail ("ISD && \"Invalid opcode\""
, "llvm/lib/Target/X86/X86TargetTransformInfo.cpp", 5034, __extension__
__PRETTY_FUNCTION__));
5035
5036 // Before legalizing the type, give a chance to look up illegal narrow types
5037 // in the table.
5038 // FIXME: Is there a better way to do this?
5039 EVT VT = TLI->getValueType(DL, ValTy);
5040 if (VT.isSimple()) {
5041 MVT MTy = VT.getSimpleVT();
5042 if (ST->useSLMArithCosts())
5043 if (const auto *Entry = CostTableLookup(SLMCostTbl, ISD, MTy))
5044 return Entry->Cost;
5045
5046 if (ST->hasAVX())
5047 if (const auto *Entry = CostTableLookup(AVX1CostTbl, ISD, MTy))
5048 return Entry->Cost;
5049
5050 if (ST->hasSSE2())
5051 if (const auto *Entry = CostTableLookup(SSE2CostTbl, ISD, MTy))
5052 return Entry->Cost;
5053 }
5054
5055 std::pair<InstructionCost, MVT> LT = getTypeLegalizationCost(ValTy);
5056
5057 MVT MTy = LT.second;
5058
5059 auto *ValVTy = cast<FixedVectorType>(ValTy);
5060
5061 // Special case: vXi8 mul reductions are performed as vXi16.
5062 if (ISD == ISD::MUL && MTy.getScalarType() == MVT::i8) {
5063 auto *WideSclTy = IntegerType::get(ValVTy->getContext(), 16);
5064 auto *WideVecTy = FixedVectorType::get(WideSclTy, ValVTy->getNumElements());
5065 return getCastInstrCost(Instruction::ZExt, WideVecTy, ValTy,
5066 TargetTransformInfo::CastContextHint::None,
5067 CostKind) +
5068 getArithmeticReductionCost(Opcode, WideVecTy, FMF, CostKind);
5069 }
5070
5071 InstructionCost ArithmeticCost = 0;
5072 if (LT.first != 1 && MTy.isVector() &&
5073 MTy.getVectorNumElements() < ValVTy->getNumElements()) {
5074 // Type needs to be split. We need LT.first - 1 arithmetic ops.
5075 auto *SingleOpTy = FixedVectorType::get(ValVTy->getElementType(),
5076 MTy.getVectorNumElements());
5077 ArithmeticCost = getArithmeticInstrCost(Opcode, SingleOpTy, CostKind);
5078 ArithmeticCost *= LT.first - 1;
5079 }
5080
5081 if (ST->useSLMArithCosts())
5082 if (const auto *Entry = CostTableLookup(SLMCostTbl, ISD, MTy))
5083 return ArithmeticCost + Entry->Cost;
5084
5085 if (ST->hasAVX())
5086 if (const auto *Entry = CostTableLookup(AVX1CostTbl, ISD, MTy))
5087 return ArithmeticCost + Entry->Cost;
5088
5089 if (ST->hasSSE2())
5090 if (const auto *Entry = CostTableLookup(SSE2CostTbl, ISD, MTy))
5091 return ArithmeticCost + Entry->Cost;
5092
5093 // FIXME: These assume a naive kshift+binop lowering, which is probably
5094 // conservative in most cases.
5095 static const CostTblEntry AVX512BoolReduction[] = {
5096 { ISD::AND, MVT::v2i1, 3 },
5097 { ISD::AND, MVT::v4i1, 5 },
5098 { ISD::AND, MVT::v8i1, 7 },
5099 { ISD::AND, MVT::v16i1, 9 },
5100 { ISD::AND, MVT::v32i1, 11 },
5101 { ISD::AND, MVT::v64i1, 13 },
5102 { ISD::OR, MVT::v2i1, 3 },
5103 { ISD::OR, MVT::v4i1, 5 },
5104 { ISD::OR, MVT::v8i1, 7 },
5105 { ISD::OR, MVT::v16i1, 9 },
5106 { ISD::OR, MVT::v32i1, 11 },
5107 { ISD::OR, MVT::v64i1, 13 },
5108 };
5109
5110 static const CostTblEntry AVX2BoolReduction[] = {
5111 { ISD::AND, MVT::v16i16, 2 }, // vpmovmskb + cmp
5112 { ISD::AND, MVT::v32i8, 2 }, // vpmovmskb + cmp
5113 { ISD::OR, MVT::v16i16, 2 }, // vpmovmskb + cmp
5114 { ISD::OR, MVT::v32i8, 2 }, // vpmovmskb + cmp
5115 };
5116
5117 static const CostTblEntry AVX1BoolReduction[] = {
5118 { ISD::AND, MVT::v4i64, 2 }, // vmovmskpd + cmp
5119 { ISD::AND, MVT::v8i32, 2 }, // vmovmskps + cmp
5120 { ISD::AND, MVT::v16i16, 4 }, // vextractf128 + vpand + vpmovmskb + cmp
5121 { ISD::AND, MVT::v32i8, 4 }, // vextractf128 + vpand + vpmovmskb + cmp
5122 { ISD::OR, MVT::v4i64, 2 }, // vmovmskpd + cmp
5123 { ISD::OR, MVT::v8i32, 2 }, // vmovmskps + cmp
5124 { ISD::OR, MVT::v16i16, 4 }, // vextractf128 + vpor + vpmovmskb + cmp
5125 { ISD::OR, MVT::v32i8, 4 }, // vextractf128 + vpor + vpmovmskb + cmp
5126 };
5127
5128 static const CostTblEntry SSE2BoolReduction[] = {
5129 { ISD::AND, MVT::v2i64, 2 }, // movmskpd + cmp
5130 { ISD::AND, MVT::v4i32, 2 }, // movmskps + cmp
5131 { ISD::AND, MVT::v8i16, 2 }, // pmovmskb + cmp
5132 { ISD::AND, MVT::v16i8, 2 }, // pmovmskb + cmp
5133 { ISD::OR, MVT::v2i64, 2 }, // movmskpd + cmp
5134 { ISD::OR, MVT::v4i32, 2 }, // movmskps + cmp
5135 { ISD::OR, MVT::v8i16, 2 }, // pmovmskb + cmp
5136 { ISD::OR, MVT::v16i8, 2 }, // pmovmskb + cmp
5137 };
5138
5139 // Handle bool allof/anyof patterns.
5140 if (ValVTy->getElementType()->isIntegerTy(1)) {
5141 InstructionCost ArithmeticCost = 0;
5142 if (LT.first != 1 && MTy.isVector() &&
5143 MTy.getVectorNumElements() < ValVTy->getNumElements()) {
5144 // Type needs to be split. We need LT.first - 1 arithmetic ops.
5145 auto *SingleOpTy = FixedVectorType::get(ValVTy->getElementType(),
5146 MTy.getVectorNumElements());
5147 ArithmeticCost = getArithmeticInstrCost(Opcode, SingleOpTy, CostKind);
5148 ArithmeticCost *= LT.first - 1;
5149 }
5150
5151 if (ST->hasAVX512())
5152 if (const auto *Entry = CostTableLookup(AVX512BoolReduction, ISD, MTy))
5153 return ArithmeticCost + Entry->Cost;
5154 if (ST->hasAVX2())
5155 if (const auto *Entry = CostTableLookup(AVX2BoolReduction, ISD, MTy))
5156 return ArithmeticCost + Entry->Cost;
5157 if (ST->hasAVX())
5158 if (const auto *Entry = CostTableLookup(AVX1BoolReduction, ISD, MTy))
5159 return ArithmeticCost + Entry->Cost;
5160 if (ST->hasSSE2())
5161 if (const auto *Entry = CostTableLookup(SSE2BoolReduction, ISD, MTy))
5162 return ArithmeticCost + Entry->Cost;
5163
5164 return BaseT::getArithmeticReductionCost(Opcode, ValVTy, FMF, CostKind);
5165 }
5166
5167 unsigned NumVecElts = ValVTy->getNumElements();
5168 unsigned ScalarSize = ValVTy->getScalarSizeInBits();
5169
5170 // Special case power of 2 reductions where the scalar type isn't changed
5171 // by type legalization.
5172 if (!isPowerOf2_32(NumVecElts) || ScalarSize != MTy.getScalarSizeInBits())
5173 return BaseT::getArithmeticReductionCost(Opcode, ValVTy, FMF, CostKind);
5174
5175 InstructionCost ReductionCost = 0;
5176
5177 auto *Ty = ValVTy;
5178 if (LT.first != 1 && MTy.isVector() &&
5179 MTy.getVectorNumElements() < ValVTy->getNumElements()) {
5180 // Type needs to be split. We need LT.first - 1 arithmetic ops.
5181 Ty = FixedVectorType::get(ValVTy->getElementType(),
5182 MTy.getVectorNumElements());
5183 ReductionCost = getArithmeticInstrCost(Opcode, Ty, CostKind);
5184 ReductionCost *= LT.first - 1;
5185 NumVecElts = MTy.getVectorNumElements();
5186 }
5187
5188 // Now handle reduction with the legal type, taking into account size changes
5189 // at each level.
5190 while (NumVecElts > 1) {
5191 // Determine the size of the remaining vector we need to reduce.
5192 unsigned Size = NumVecElts * ScalarSize;
5193 NumVecElts /= 2;
5194 // If we're reducing from 256/512 bits, use an extract_subvector.
5195 if (Size > 128) {
5196 auto *SubTy = FixedVectorType::get(ValVTy->getElementType(), NumVecElts);
5197 ReductionCost +=
5198 getShuffleCost(TTI::SK_ExtractSubvector, Ty, std::nullopt, CostKind,
5199 NumVecElts, SubTy);
5200 Ty = SubTy;
5201 } else if (Size == 128) {
5202 // Reducing from 128 bits is a permute of v2f64/v2i64.
5203 FixedVectorType *ShufTy;
5204 if (ValVTy->isFloatingPointTy())
5205 ShufTy =
5206 FixedVectorType::get(Type::getDoubleTy(ValVTy->getContext()), 2);
5207 else
5208 ShufTy =
5209 FixedVectorType::get(Type::getInt64Ty(ValVTy->getContext()), 2);
5210 ReductionCost += getShuffleCost(TTI::SK_PermuteSingleSrc, ShufTy,
5211 std::nullopt, CostKind, 0, nullptr);
5212 } else if (Size == 64) {
5213 // Reducing from 64 bits is a shuffle of v4f32/v4i32.
5214 FixedVectorType *ShufTy;
5215 if (ValVTy->isFloatingPointTy())
5216 ShufTy =
5217 FixedVectorType::get(Type::getFloatTy(ValVTy->getContext()), 4);
5218 else
5219 ShufTy =
5220 FixedVectorType::get(Type::getInt32Ty(ValVTy->getContext()), 4);
5221 ReductionCost += getShuffleCost(TTI::SK_PermuteSingleSrc, ShufTy,
5222 std::nullopt, CostKind, 0, nullptr);
5223 } else {
5224 // Reducing from smaller size is a shift by immediate.
5225 auto *ShiftTy = FixedVectorType::get(
5226 Type::getIntNTy(ValVTy->getContext(), Size), 128 / Size);
5227 ReductionCost += getArithmeticInstrCost(
5228 Instruction::LShr, ShiftTy, CostKind,
5229 {TargetTransformInfo::OK_AnyValue, TargetTransformInfo::OP_None},
5230 {TargetTransformInfo::OK_UniformConstantValue, TargetTransformInfo::OP_None});
5231 }
5232
5233 // Add the arithmetic op for this level.
5234 ReductionCost += getArithmeticInstrCost(Opcode, Ty, CostKind);
5235 }
5236
5237 // Add the final extract element to the cost.
5238 return ReductionCost + getVectorInstrCost(Instruction::ExtractElement, Ty,
5239 CostKind, 0, nullptr, nullptr);
5240}
5241
5242InstructionCost X86TTIImpl::getMinMaxCost(Type *Ty, Type *CondTy,
5243 TTI::TargetCostKind CostKind,
5244 bool IsUnsigned, FastMathFlags FMF) {
5245 Intrinsic::ID Id;
5246 if (Ty->isIntOrIntVectorTy()) {
5247 Id = IsUnsigned ? Intrinsic::umin : Intrinsic::smin;
5248 } else {
5249 assert(Ty->isFPOrFPVectorTy() &&(static_cast <bool> (Ty->isFPOrFPVectorTy() &&
"Expected float point or integer vector type.") ? void (0) :
__assert_fail ("Ty->isFPOrFPVectorTy() && \"Expected float point or integer vector type.\""
, "llvm/lib/Target/X86/X86TargetTransformInfo.cpp", 5250, __extension__
__PRETTY_FUNCTION__))
5250 "Expected float point or integer vector type.")(static_cast <bool> (Ty->isFPOrFPVectorTy() &&
"Expected float point or integer vector type.") ? void (0) :
__assert_fail ("Ty->isFPOrFPVectorTy() && \"Expected float point or integer vector type.\""
, "llvm/lib/Target/X86/X86TargetTransformInfo.cpp", 5250, __extension__
__PRETTY_FUNCTION__));
5251 Id = Intrinsic::minnum;
5252 }
5253
5254 IntrinsicCostAttributes ICA(Id, Ty, {Ty, Ty}, FMF);
5255 return getIntrinsicInstrCost(ICA, CostKind);
5256}
5257
5258InstructionCost
5259X86TTIImpl::getMinMaxReductionCost(VectorType *ValTy, VectorType *CondTy,
5260 bool IsUnsigned, FastMathFlags FMF,
5261 TTI::TargetCostKind CostKind) {
5262 std::pair<InstructionCost, MVT> LT = getTypeLegalizationCost(ValTy);
5263
5264 MVT MTy = LT.second;
5265
5266 int ISD;
5267 if (ValTy->isIntOrIntVectorTy()) {
5268 ISD = IsUnsigned ? ISD::UMIN : ISD::SMIN;
1
Taking true branch
→
2
←
Assuming 'IsUnsigned' is false
→
3
←
'?' condition is false
→
5269 } else {
5270 assert(ValTy->isFPOrFPVectorTy() &&(static_cast <bool> (ValTy->isFPOrFPVectorTy() &&
"Expected float point or integer vector type.") ? void (0) :
__assert_fail ("ValTy->isFPOrFPVectorTy() && \"Expected float point or integer vector type.\""
, "llvm/lib/Target/X86/X86TargetTransformInfo.cpp", 5271, __extension__
__PRETTY_FUNCTION__))
5271 "Expected float point or integer vector type.")(static_cast <bool> (ValTy->isFPOrFPVectorTy() &&
"Expected float point or integer vector type.") ? void (0) :
__assert_fail ("ValTy->isFPOrFPVectorTy() && \"Expected float point or integer vector type.\""
, "llvm/lib/Target/X86/X86TargetTransformInfo.cpp", 5271, __extension__
__PRETTY_FUNCTION__));
5272 ISD = ISD::FMINNUM;
5273 }
5274
5275 // We use the Intel Architecture Code Analyzer(IACA) to measure the throughput
5276 // and make it as the cost.
5277
5278 static const CostTblEntry SSE2CostTbl[] = {
5279 {ISD::UMIN, MVT::v2i16, 5}, // need pxors to use pminsw/pmaxsw
5280 {ISD::UMIN, MVT::v4i16, 7}, // need pxors to use pminsw/pmaxsw
5281 {ISD::UMIN, MVT::v8i16, 9}, // need pxors to use pminsw/pmaxsw
5282 };
5283
5284 static const CostTblEntry SSE41CostTbl[] = {
5285 {ISD::SMIN, MVT::v2i16, 3}, // same as sse2
5286 {ISD::SMIN, MVT::v4i16, 5}, // same as sse2
5287 {ISD::UMIN, MVT::v2i16, 5}, // same as sse2
5288 {ISD::UMIN, MVT::v4i16, 7}, // same as sse2
5289 {ISD::SMIN, MVT::v8i16, 4}, // phminposuw+xor
5290 {ISD::UMIN, MVT::v8i16, 4}, // FIXME: umin is cheaper than umax
5291 {ISD::SMIN, MVT::v2i8, 3}, // pminsb
5292 {ISD::SMIN, MVT::v4i8, 5}, // pminsb
5293 {ISD::SMIN, MVT::v8i8, 7}, // pminsb
5294 {ISD::SMIN, MVT::v16i8, 6},
5295 {ISD::UMIN, MVT::v2i8, 3}, // same as sse2
5296 {ISD::UMIN, MVT::v4i8, 5}, // same as sse2
5297 {ISD::UMIN, MVT::v8i8, 7}, // same as sse2
5298 {ISD::UMIN, MVT::v16i8, 6}, // FIXME: umin is cheaper than umax
5299 };
5300
5301 static const CostTblEntry AVX1CostTbl[] = {
5302 {ISD::SMIN, MVT::v16i16, 6},
5303 {ISD::UMIN, MVT::v16i16, 6}, // FIXME: umin is cheaper than umax
5304 {ISD::SMIN, MVT::v32i8, 8},
5305 {ISD::UMIN, MVT::v32i8, 8},
5306 };
5307
5308 static const CostTblEntry AVX512BWCostTbl[] = {
5309 {ISD::SMIN, MVT::v32i16, 8},
5310 {ISD::UMIN, MVT::v32i16, 8}, // FIXME: umin is cheaper than umax
5311 {ISD::SMIN, MVT::v64i8, 10},
5312 {ISD::UMIN, MVT::v64i8, 10},
5313 };
5314
5315 // Before legalizing the type, give a chance to look up illegal narrow types
5316 // in the table.
5317 // FIXME: Is there a better way to do this?
5318 EVT VT = TLI->getValueType(DL, ValTy);
5319 if (VT.isSimple()) {
4
←
Taking false branch
→
5320 MVT MTy = VT.getSimpleVT();
5321 if (ST->hasBWI())
5322 if (const auto *Entry = CostTableLookup(AVX512BWCostTbl, ISD, MTy))
5323 return Entry->Cost;
5324
5325 if (ST->hasAVX())
5326 if (const auto *Entry = CostTableLookup(AVX1CostTbl, ISD, MTy))
5327 return Entry->Cost;
5328
5329 if (ST->hasSSE41())
5330 if (const auto *Entry = CostTableLookup(SSE41CostTbl, ISD, MTy))
5331 return Entry->Cost;
5332
5333 if (ST->hasSSE2())
5334 if (const auto *Entry = CostTableLookup(SSE2CostTbl, ISD, MTy))
5335 return Entry->Cost;
5336 }
5337
5338 auto *ValVTy = cast<FixedVectorType>(ValTy);
5
←
'ValTy' is a 'CastReturnType'
→
5339 unsigned NumVecElts = ValVTy->getNumElements();
5340
5341 auto *Ty = ValVTy;
5342 InstructionCost MinMaxCost = 0;
5343 if (LT.first != 1 && MTy.isVector() &&
5344 MTy.getVectorNumElements() < ValVTy->getNumElements()) {
5345 // Type needs to be split. We need LT.first - 1 operations ops.
5346 Ty = FixedVectorType::get(ValVTy->getElementType(),
5347 MTy.getVectorNumElements());
5348 auto *SubCondTy = FixedVectorType::get(CondTy->getElementType(),
5349 MTy.getVectorNumElements());
5350 MinMaxCost = getMinMaxCost(Ty, SubCondTy, CostKind, IsUnsigned, FMF);
5351 MinMaxCost *= LT.first - 1;
5352 NumVecElts = MTy.getVectorNumElements();
5353 }
5354
5355 if (ST->hasBWI())
6
←
Assuming the condition is false
→
7
←
Taking false branch
→
5356 if (const auto *Entry = CostTableLookup(AVX512BWCostTbl, ISD, MTy))
5357 return MinMaxCost + Entry->Cost;
5358
5359 if (ST->hasAVX())
8
←
Taking false branch
→
5360 if (const auto *Entry = CostTableLookup(AVX1CostTbl, ISD, MTy))
5361 return MinMaxCost + Entry->Cost;
5362
5363 if (ST->hasSSE41())
9
←
Taking false branch
→
5364 if (const auto *Entry = CostTableLookup(SSE41CostTbl, ISD, MTy))
5365 return MinMaxCost + Entry->Cost;
5366
5367 if (ST->hasSSE2())
10
←
Taking false branch
→
5368 if (const auto *Entry = CostTableLookup(SSE2CostTbl, ISD, MTy))
5369 return MinMaxCost + Entry->Cost;
5370
5371 unsigned ScalarSize = ValTy->getScalarSizeInBits();
5372
5373 // Special case power of 2 reductions where the scalar type isn't changed
5374 // by type legalization.
5375 if (!isPowerOf2_32(ValVTy->getNumElements()) ||
12
←
Taking false branch
→
5376 ScalarSize != MTy.getScalarSizeInBits())
11
←
Assuming the condition is false
→
5377 return BaseT::getMinMaxReductionCost(ValTy, CondTy, IsUnsigned, FMF,
5378 CostKind);
5379
5380 // Now handle reduction with the legal type, taking into account size changes
5381 // at each level.
5382 while (NumVecElts > 1) {
13
←
Assuming 'NumVecElts' is <= 1
→
14
←
Loop condition is false. Execution continues on line 5428
→
5383 // Determine the size of the remaining vector we need to reduce.
5384 unsigned Size = NumVecElts * ScalarSize;
5385 NumVecElts /= 2;
5386 // If we're reducing from 256/512 bits, use an extract_subvector.
5387 if (Size > 128) {
5388 auto *SubTy = FixedVectorType::get(ValVTy->getElementType(), NumVecElts);
5389 MinMaxCost += getShuffleCost(TTI::SK_ExtractSubvector, Ty, std::nullopt,
5390 CostKind, NumVecElts, SubTy);
5391 Ty = SubTy;
5392 } else if (Size == 128) {
5393 // Reducing from 128 bits is a permute of v2f64/v2i64.
5394 VectorType *ShufTy;
5395 if (ValTy->isFloatingPointTy())
5396 ShufTy =
5397 FixedVectorType::get(Type::getDoubleTy(ValTy->getContext()), 2);
5398 else
5399 ShufTy = FixedVectorType::get(Type::getInt64Ty(ValTy->getContext()), 2);
5400 MinMaxCost += getShuffleCost(TTI::SK_PermuteSingleSrc, ShufTy,
5401 std::nullopt, CostKind, 0, nullptr);
5402 } else if (Size == 64) {
5403 // Reducing from 64 bits is a shuffle of v4f32/v4i32.
5404 FixedVectorType *ShufTy;
5405 if (ValTy->isFloatingPointTy())
5406 ShufTy = FixedVectorType::get(Type::getFloatTy(ValTy->getContext()), 4);
5407 else
5408 ShufTy = FixedVectorType::get(Type::getInt32Ty(ValTy->getContext()), 4);
5409 MinMaxCost += getShuffleCost(TTI::SK_PermuteSingleSrc, ShufTy,
5410 std::nullopt, CostKind, 0, nullptr);
5411 } else {
5412 // Reducing from smaller size is a shift by immediate.
5413 auto *ShiftTy = FixedVectorType::get(
5414 Type::getIntNTy(ValTy->getContext(), Size), 128 / Size);
5415 MinMaxCost += getArithmeticInstrCost(
5416 Instruction::LShr, ShiftTy, TTI::TCK_RecipThroughput,
5417 {TargetTransformInfo::OK_AnyValue, TargetTransformInfo::OP_None},
5418 {TargetTransformInfo::OK_UniformConstantValue, TargetTransformInfo::OP_None});
5419 }
5420
5421 // Add the arithmetic op for this level.
5422 auto *SubCondTy =
5423 FixedVectorType::get(CondTy->getElementType(), Ty->getNumElements());
5424 MinMaxCost += getMinMaxCost(Ty, SubCondTy, CostKind, IsUnsigned, FMF);
5425 }
5426
5427 // Add the final extract element to the cost.
5428 return MinMaxCost + getVectorInstrCost(Instruction::ExtractElement, Ty,
15
←
Calling 'X86TTIImpl::getVectorInstrCost'
→
5429 CostKind, 0, nullptr, nullptr);
5430}
5431
5432/// Calculate the cost of materializing a 64-bit value. This helper
5433/// method might only calculate a fraction of a larger immediate. Therefore it
5434/// is valid to return a cost of ZERO.
5435InstructionCost X86TTIImpl::getIntImmCost(int64_t Val) {
5436 if (Val == 0)
5437 return TTI::TCC_Free;
5438
5439 if (isInt<32>(Val))
5440 return TTI::TCC_Basic;
5441
5442 return 2 * TTI::TCC_Basic;
5443}
5444
5445InstructionCost X86TTIImpl::getIntImmCost(const APInt &Imm, Type *Ty,
5446 TTI::TargetCostKind CostKind) {
5447 assert(Ty->isIntegerTy())(static_cast <bool> (Ty->isIntegerTy()) ? void (0) :
__assert_fail ("Ty->isIntegerTy()", "llvm/lib/Target/X86/X86TargetTransformInfo.cpp"
, 5447, __extension__ __PRETTY_FUNCTION__));
5448
5449 unsigned BitSize = Ty->getPrimitiveSizeInBits();
5450 if (BitSize == 0)
5451 return ~0U;
5452
5453 // Never hoist constants larger than 128bit, because this might lead to
5454 // incorrect code generation or assertions in codegen.
5455 // Fixme: Create a cost model for types larger than i128 once the codegen
5456 // issues have been fixed.
5457 if (BitSize > 128)
5458 return TTI::TCC_Free;
5459
5460 if (Imm == 0)
5461 return TTI::TCC_Free;
5462
5463 // Sign-extend all constants to a multiple of 64-bit.
5464 APInt ImmVal = Imm;
5465 if (BitSize % 64 != 0)
5466 ImmVal = Imm.sext(alignTo(BitSize, 64));
5467
5468 // Split the constant into 64-bit chunks and calculate the cost for each
5469 // chunk.
5470 InstructionCost Cost = 0;
5471 for (unsigned ShiftVal = 0; ShiftVal < BitSize; ShiftVal += 64) {
5472 APInt Tmp = ImmVal.ashr(ShiftVal).sextOrTrunc(64);
5473 int64_t Val = Tmp.getSExtValue();
5474 Cost += getIntImmCost(Val);
5475 }
5476 // We need at least one instruction to materialize the constant.
5477 return std::max<InstructionCost>(1, Cost);
5478}
5479
5480InstructionCost X86TTIImpl::getIntImmCostInst(unsigned Opcode, unsigned Idx,
5481 const APInt &Imm, Type *Ty,
5482 TTI::TargetCostKind CostKind,
5483 Instruction *Inst) {
5484 assert(Ty->isIntegerTy())(static_cast <bool> (Ty->isIntegerTy()) ? void (0) :
__assert_fail ("Ty->isIntegerTy()", "llvm/lib/Target/X86/X86TargetTransformInfo.cpp"
, 5484, __extension__ __PRETTY_FUNCTION__));
5485
5486 unsigned BitSize = Ty->getPrimitiveSizeInBits();
5487 // There is no cost model for constants with a bit size of 0. Return TCC_Free
5488 // here, so that constant hoisting will ignore this constant.
5489 if (BitSize == 0)
5490 return TTI::TCC_Free;
5491
5492 unsigned ImmIdx = ~0U;
5493 switch (Opcode) {
5494 default:
5495 return TTI::TCC_Free;
5496 case Instruction::GetElementPtr:
5497 // Always hoist the base address of a GetElementPtr. This prevents the
5498 // creation of new constants for every base constant that gets constant
5499 // folded with the offset.
5500 if (Idx == 0)
5501 return 2 * TTI::TCC_Basic;
5502 return TTI::TCC_Free;
5503 case Instruction::Store:
5504 ImmIdx = 0;
5505 break;
5506 case Instruction::ICmp:
5507 // This is an imperfect hack to prevent constant hoisting of
5508 // compares that might be trying to check if a 64-bit value fits in
5509 // 32-bits. The backend can optimize these cases using a right shift by 32.
5510 // Ideally we would check the compare predicate here. There also other
5511 // similar immediates the backend can use shifts for.
5512 if (Idx == 1 && Imm.getBitWidth() == 64) {
5513 uint64_t ImmVal = Imm.getZExtValue();
5514 if (ImmVal == 0x100000000ULL || ImmVal == 0xffffffff)
5515 return TTI::TCC_Free;
5516 }
5517 ImmIdx = 1;
5518 break;
5519 case Instruction::And:
5520 // We support 64-bit ANDs with immediates with 32-bits of leading zeroes
5521 // by using a 32-bit operation with implicit zero extension. Detect such
5522 // immediates here as the normal path expects bit 31 to be sign extended.
5523 if (Idx == 1 && Imm.getBitWidth() == 64 && Imm.isIntN(32))
5524 return TTI::TCC_Free;
5525 ImmIdx = 1;
5526 break;
5527 case Instruction::Add:
5528 case Instruction::Sub:
5529 // For add/sub, we can use the opposite instruction for INT32_MIN.
5530 if (Idx == 1 && Imm.getBitWidth() == 64 && Imm.getZExtValue() == 0x80000000)
5531 return TTI::TCC_Free;
5532 ImmIdx = 1;
5533 break;
5534 case Instruction::UDiv:
5535 case Instruction::SDiv:
5536 case Instruction::URem:
5537 case Instruction::SRem:
5538 // Division by constant is typically expanded later into a different
5539 // instruction sequence. This completely changes the constants.
5540 // Report them as "free" to stop ConstantHoist from marking them as opaque.
5541 return TTI::TCC_Free;
5542 case Instruction::Mul:
5543 case Instruction::Or:
5544 case Instruction::Xor:
5545 ImmIdx = 1;
5546 break;
5547 // Always return TCC_Free for the shift value of a shift instruction.
5548 case Instruction::Shl:
5549 case Instruction::LShr:
5550 case Instruction::AShr:
5551 if (Idx == 1)
5552 return TTI::TCC_Free;
5553 break;
5554 case Instruction::Trunc:
5555 case Instruction::ZExt:
5556 case Instruction::SExt:
5557 case Instruction::IntToPtr:
5558 case Instruction::PtrToInt:
5559 case Instruction::BitCast:
5560 case Instruction::PHI:
5561 case Instruction::Call:
5562 case Instruction::Select:
5563 case Instruction::Ret:
5564 case Instruction::Load:
5565 break;
5566 }
5567
5568 if (Idx == ImmIdx) {
5569 int NumConstants = divideCeil(BitSize, 64);
5570 InstructionCost Cost = X86TTIImpl::getIntImmCost(Imm, Ty, CostKind);
5571 return (Cost <= NumConstants * TTI::TCC_Basic)
5572 ? static_cast<int>(TTI::TCC_Free)
5573 : Cost;
5574 }
5575
5576 return X86TTIImpl::getIntImmCost(Imm, Ty, CostKind);
5577}
5578
5579InstructionCost X86TTIImpl::getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx,
5580 const APInt &Imm, Type *Ty,
5581 TTI::TargetCostKind CostKind) {
5582 assert(Ty->isIntegerTy())(static_cast <bool> (Ty->isIntegerTy()) ? void (0) :
__assert_fail ("Ty->isIntegerTy()", "llvm/lib/Target/X86/X86TargetTransformInfo.cpp"
, 5582, __extension__ __PRETTY_FUNCTION__));
5583
5584 unsigned BitSize = Ty->getPrimitiveSizeInBits();
5585 // There is no cost model for constants with a bit size of 0. Return TCC_Free
5586 // here, so that constant hoisting will ignore this constant.
5587 if (BitSize == 0)
5588 return TTI::TCC_Free;
5589
5590 switch (IID) {
5591 default:
5592 return TTI::TCC_Free;
5593 case Intrinsic::sadd_with_overflow:
5594 case Intrinsic::uadd_with_overflow:
5595 case Intrinsic::ssub_with_overflow:
5596 case Intrinsic::usub_with_overflow:
5597 case Intrinsic::smul_with_overflow:
5598 case Intrinsic::umul_with_overflow:
5599 if ((Idx == 1) && Imm.getBitWidth() <= 64 && Imm.isSignedIntN(32))
5600 return TTI::TCC_Free;
5601 break;
5602 case Intrinsic::experimental_stackmap:
5603 if ((Idx < 2) || (Imm.getBitWidth() <= 64 && Imm.isSignedIntN(64)))
5604 return TTI::TCC_Free;
5605 break;
5606 case Intrinsic::experimental_patchpoint_void:
5607 case Intrinsic::experimental_patchpoint_i64:
5608 if ((Idx < 4) || (Imm.getBitWidth() <= 64 && Imm.isSignedIntN(64)))
5609 return TTI::TCC_Free;
5610 break;
5611 }
5612 return X86TTIImpl::getIntImmCost(Imm, Ty, CostKind);
5613}
5614
5615InstructionCost X86TTIImpl::getCFInstrCost(unsigned Opcode,
5616 TTI::TargetCostKind CostKind,
5617 const Instruction *I) {
5618 if (CostKind != TTI::TCK_RecipThroughput)
5619 return Opcode == Instruction::PHI ? 0 : 1;
5620 // Branches are assumed to be predicted.
5621 return 0;
5622}
5623
5624int X86TTIImpl::getGatherOverhead() const {
5625 // Some CPUs have more overhead for gather. The specified overhead is relative
5626 // to the Load operation. "2" is the number provided by Intel architects. This
5627 // parameter is used for cost estimation of Gather Op and comparison with
5628 // other alternatives.
5629 // TODO: Remove the explicit hasAVX512()?, That would mean we would only
5630 // enable gather with a -march.
5631 if (ST->hasAVX512() || (ST->hasAVX2() && ST->hasFastGather()))
5632 return 2;
5633
5634 return 1024;
5635}
5636
5637int X86TTIImpl::getScatterOverhead() const {
5638 if (ST->hasAVX512())
5639 return 2;
5640
5641 return 1024;
5642}
5643
5644// Return an average cost of Gather / Scatter instruction, maybe improved later.
5645// FIXME: Add TargetCostKind support.
5646InstructionCost X86TTIImpl::getGSVectorCost(unsigned Opcode, Type *SrcVTy,
5647 const Value *Ptr, Align Alignment,
5648 unsigned AddressSpace) {
5649
5650 assert(isa<VectorType>(SrcVTy) && "Unexpected type in getGSVectorCost")(static_cast <bool> (isa<VectorType>(SrcVTy) &&
"Unexpected type in getGSVectorCost") ? void (0) : __assert_fail
("isa<VectorType>(SrcVTy) && \"Unexpected type in getGSVectorCost\""
, "llvm/lib/Target/X86/X86TargetTransformInfo.cpp", 5650, __extension__
__PRETTY_FUNCTION__));
5651 unsigned VF = cast<FixedVectorType>(SrcVTy)->getNumElements();
5652
5653 // Try to reduce index size from 64 bit (default for GEP)
5654 // to 32. It is essential for VF 16. If the index can't be reduced to 32, the
5655 // operation will use 16 x 64 indices which do not fit in a zmm and needs
5656 // to split. Also check that the base pointer is the same for all lanes,
5657 // and that there's at most one variable index.
5658 auto getIndexSizeInBits = [](const Value *Ptr, const DataLayout &DL) {
5659 unsigned IndexSize = DL.getPointerSizeInBits();
5660 const GetElementPtrInst *GEP = dyn_cast<GetElementPtrInst>(Ptr);
5661 if (IndexSize < 64 || !GEP)
5662 return IndexSize;
5663
5664 unsigned NumOfVarIndices = 0;
5665 const Value *Ptrs = GEP->getPointerOperand();
5666 if (Ptrs->getType()->isVectorTy() && !getSplatValue(Ptrs))
5667 return IndexSize;
5668 for (unsigned i = 1; i < GEP->getNumOperands(); ++i) {
5669 if (isa<Constant>(GEP->getOperand(i)))
5670 continue;
5671 Type *IndxTy = GEP->getOperand(i)->getType();
5672 if (auto *IndexVTy = dyn_cast<VectorType>(IndxTy))
5673 IndxTy = IndexVTy->getElementType();
5674 if ((IndxTy->getPrimitiveSizeInBits() == 64 &&
5675 !isa<SExtInst>(GEP->getOperand(i))) ||
5676 ++NumOfVarIndices > 1)
5677 return IndexSize; // 64
5678 }
5679 return (unsigned)32;
5680 };
5681
5682 // Trying to reduce IndexSize to 32 bits for vector 16.
5683 // By default the IndexSize is equal to pointer size.
5684 unsigned IndexSize = (ST->hasAVX512() && VF >= 16)
5685 ? getIndexSizeInBits(Ptr, DL)
5686 : DL.getPointerSizeInBits();
5687
5688 auto *IndexVTy = FixedVectorType::get(
5689 IntegerType::get(SrcVTy->getContext(), IndexSize), VF);
5690 std::pair<InstructionCost, MVT> IdxsLT = getTypeLegalizationCost(IndexVTy);
5691 std::pair<InstructionCost, MVT> SrcLT = getTypeLegalizationCost(SrcVTy);
5692 InstructionCost::CostType SplitFactor =
5693 *std::max(IdxsLT.first, SrcLT.first).getValue();
5694 if (SplitFactor > 1) {
5695 // Handle splitting of vector of pointers
5696 auto *SplitSrcTy =
5697 FixedVectorType::get(SrcVTy->getScalarType(), VF / SplitFactor);
5698 return SplitFactor * getGSVectorCost(Opcode, SplitSrcTy, Ptr, Alignment,
5699 AddressSpace);
5700 }
5701
5702 // The gather / scatter cost is given by Intel architects. It is a rough
5703 // number since we are looking at one instruction in a time.
5704 const int GSOverhead = (Opcode == Instruction::Load)
5705 ? getGatherOverhead()
5706 : getScatterOverhead();
5707 return GSOverhead + VF * getMemoryOpCost(Opcode, SrcVTy->getScalarType(),
5708 MaybeAlign(Alignment), AddressSpace,
5709 TTI::TCK_RecipThroughput);
5710}
5711
5712/// Return the cost of full scalarization of gather / scatter operation.
5713///
5714/// Opcode - Load or Store instruction.
5715/// SrcVTy - The type of the data vector that should be gathered or scattered.
5716/// VariableMask - The mask is non-constant at compile time.
5717/// Alignment - Alignment for one element.
5718/// AddressSpace - pointer[s] address space.
5719///
5720/// FIXME: Add TargetCostKind support.
5721InstructionCost X86TTIImpl::getGSScalarCost(unsigned Opcode, Type *SrcVTy,
5722 bool VariableMask, Align Alignment,
5723 unsigned AddressSpace) {
5724 Type *ScalarTy = SrcVTy->getScalarType();
5725 unsigned VF = cast<FixedVectorType>(SrcVTy)->getNumElements();
5726 APInt DemandedElts = APInt::getAllOnes(VF);
5727 TTI::TargetCostKind CostKind = TTI::TCK_RecipThroughput;
5728
5729 InstructionCost MaskUnpackCost = 0;
5730 if (VariableMask) {
5731 auto *MaskTy =
5732 FixedVectorType::get(Type::getInt1Ty(SrcVTy->getContext()), VF);
5733 MaskUnpackCost = getScalarizationOverhead(
5734 MaskTy, DemandedElts, /*Insert=*/false, /*Extract=*/true, CostKind);
5735 InstructionCost ScalarCompareCost = getCmpSelInstrCost(
5736 Instruction::ICmp, Type::getInt1Ty(SrcVTy->getContext()), nullptr,
5737 CmpInst::BAD_ICMP_PREDICATE, CostKind);
5738 InstructionCost BranchCost = getCFInstrCost(Instruction::Br, CostKind);
5739 MaskUnpackCost += VF * (BranchCost + ScalarCompareCost);
5740 }
5741
5742 InstructionCost AddressUnpackCost = getScalarizationOverhead(
5743 FixedVectorType::get(ScalarTy->getPointerTo(), VF), DemandedElts,
5744 /*Insert=*/false, /*Extract=*/true, CostKind);
5745
5746 // The cost of the scalar loads/stores.
5747 InstructionCost MemoryOpCost =
5748 VF * getMemoryOpCost(Opcode, ScalarTy, MaybeAlign(Alignment),
5749 AddressSpace, CostKind);
5750
5751 // The cost of forming the vector from loaded scalars/
5752 // scalarizing the vector to perform scalar stores.
5753 InstructionCost InsertExtractCost = getScalarizationOverhead(
5754 cast<FixedVectorType>(SrcVTy), DemandedElts,
5755 /*Insert=*/Opcode == Instruction::Load,
5756 /*Extract=*/Opcode == Instruction::Store, CostKind);
5757
5758 return AddressUnpackCost + MemoryOpCost + MaskUnpackCost + InsertExtractCost;
5759}
5760
5761/// Calculate the cost of Gather / Scatter operation
5762InstructionCost X86TTIImpl::getGatherScatterOpCost(
5763 unsigned Opcode, Type *SrcVTy, const Value *Ptr, bool VariableMask,
5764 Align Alignment, TTI::TargetCostKind CostKind,
5765 const Instruction *I = nullptr) {
5766 if (CostKind != TTI::TCK_RecipThroughput) {
5767 if ((Opcode == Instruction::Load &&
5768 isLegalMaskedGather(SrcVTy, Align(Alignment)) &&
5769 !forceScalarizeMaskedGather(cast<VectorType>(SrcVTy),
5770 Align(Alignment))) ||
5771 (Opcode == Instruction::Store &&
5772 isLegalMaskedScatter(SrcVTy, Align(Alignment)) &&
5773 !forceScalarizeMaskedScatter(cast<VectorType>(SrcVTy),
5774 Align(Alignment))))
5775 return 1;
5776 return BaseT::getGatherScatterOpCost(Opcode, SrcVTy, Ptr, VariableMask,
5777 Alignment, CostKind, I);
5778 }
5779
5780 assert(SrcVTy->isVectorTy() && "Unexpected data type for Gather/Scatter")(static_cast <bool> (SrcVTy->isVectorTy() &&
"Unexpected data type for Gather/Scatter") ? void (0) : __assert_fail
("SrcVTy->isVectorTy() && \"Unexpected data type for Gather/Scatter\""
, "llvm/lib/Target/X86/X86TargetTransformInfo.cpp", 5780, __extension__
__PRETTY_FUNCTION__));
5781 PointerType *PtrTy = dyn_cast<PointerType>(Ptr->getType());
5782 if (!PtrTy && Ptr->getType()->isVectorTy())
5783 PtrTy = dyn_cast<PointerType>(
5784 cast<VectorType>(Ptr->getType())->getElementType());
5785 assert(PtrTy && "Unexpected type for Ptr argument")(static_cast <bool> (PtrTy && "Unexpected type for Ptr argument"
) ? void (0) : __assert_fail ("PtrTy && \"Unexpected type for Ptr argument\""
, "llvm/lib/Target/X86/X86TargetTransformInfo.cpp", 5785, __extension__
__PRETTY_FUNCTION__));
5786 unsigned AddressSpace = PtrTy->getAddressSpace();
5787
5788 if ((Opcode == Instruction::Load &&
5789 (!isLegalMaskedGather(SrcVTy, Align(Alignment)) ||
5790 forceScalarizeMaskedGather(cast<VectorType>(SrcVTy),
5791 Align(Alignment)))) ||
5792 (Opcode == Instruction::Store &&
5793 (!isLegalMaskedScatter(SrcVTy, Align(Alignment)) ||
5794 forceScalarizeMaskedScatter(cast<VectorType>(SrcVTy),
5795 Align(Alignment)))))
5796 return getGSScalarCost(Opcode, SrcVTy, VariableMask, Alignment,
5797 AddressSpace);
5798
5799 return getGSVectorCost(Opcode, SrcVTy, Ptr, Alignment, AddressSpace);
5800}
5801
5802bool X86TTIImpl::isLSRCostLess(const TargetTransformInfo::LSRCost &C1,
5803 const TargetTransformInfo::LSRCost &C2) {
5804 // X86 specific here are "instruction number 1st priority".
5805 return std::tie(C1.Insns, C1.NumRegs, C1.AddRecCost,
5806 C1.NumIVMuls, C1.NumBaseAdds,
5807 C1.ScaleCost, C1.ImmCost, C1.SetupCost) <
5808 std::tie(C2.Insns, C2.NumRegs, C2.AddRecCost,
5809 C2.NumIVMuls, C2.NumBaseAdds,
5810 C2.ScaleCost, C2.ImmCost, C2.SetupCost);
5811}
5812
5813bool X86TTIImpl::canMacroFuseCmp() {
5814 return ST->hasMacroFusion() || ST->hasBranchFusion();
5815}
5816
5817bool X86TTIImpl::isLegalMaskedLoad(Type *DataTy, Align Alignment) {
5818 if (!ST->hasAVX())
5819 return false;
5820
5821 // The backend can't handle a single element vector.
5822 if (isa<VectorType>(DataTy) &&
5823 cast<FixedVectorType>(DataTy)->getNumElements() == 1)
5824 return false;
5825 Type *ScalarTy = DataTy->getScalarType();
5826
5827 if (ScalarTy->isPointerTy())
5828 return true;
5829
5830 if (ScalarTy->isFloatTy() || ScalarTy->isDoubleTy())
5831 return true;
5832
5833 if (ScalarTy->isHalfTy() && ST->hasBWI())
5834 return true;
5835
5836 if (!ScalarTy->isIntegerTy())
5837 return false;
5838
5839 unsigned IntWidth = ScalarTy->getIntegerBitWidth();
5840 return IntWidth == 32 || IntWidth == 64 ||
5841 ((IntWidth == 8 || IntWidth == 16) && ST->hasBWI());
5842}
5843
5844bool X86TTIImpl::isLegalMaskedStore(Type *DataType, Align Alignment) {
5845 return isLegalMaskedLoad(DataType, Alignment);
5846}
5847
5848bool X86TTIImpl::isLegalNTLoad(Type *DataType, Align Alignment) {
5849 unsigned DataSize = DL.getTypeStoreSize(DataType);
5850 // The only supported nontemporal loads are for aligned vectors of 16 or 32
5851 // bytes. Note that 32-byte nontemporal vector loads are supported by AVX2
5852 // (the equivalent stores only require AVX).
5853 if (Alignment >= DataSize && (DataSize == 16 || DataSize == 32))
5854 return DataSize == 16 ? ST->hasSSE1() : ST->hasAVX2();
5855
5856 return false;
5857}
5858
5859bool X86TTIImpl::isLegalNTStore(Type *DataType, Align Alignment) {
5860 unsigned DataSize = DL.getTypeStoreSize(DataType);
5861
5862 // SSE4A supports nontemporal stores of float and double at arbitrary
5863 // alignment.
5864 if (ST->hasSSE4A() && (DataType->isFloatTy() || DataType->isDoubleTy()))
5865 return true;
5866
5867 // Besides the SSE4A subtarget exception above, only aligned stores are
5868 // available nontemporaly on any other subtarget. And only stores with a size
5869 // of 4..32 bytes (powers of 2, only) are permitted.
5870 if (Alignment < DataSize || DataSize < 4 || DataSize > 32 ||
5871 !isPowerOf2_32(DataSize))
5872 return false;
5873
5874 // 32-byte vector nontemporal stores are supported by AVX (the equivalent
5875 // loads require AVX2).
5876 if (DataSize == 32)
5877 return ST->hasAVX();
5878 if (DataSize == 16)
5879 return ST->hasSSE1();
5880 return true;
5881}
5882
5883bool X86TTIImpl::isLegalBroadcastLoad(Type *ElementTy,
5884 ElementCount NumElements) const {
5885 // movddup
5886 return ST->hasSSE3() && !NumElements.isScalable() &&
5887 NumElements.getFixedValue() == 2 &&
5888 ElementTy == Type::getDoubleTy(ElementTy->getContext());
5889}
5890
5891bool X86TTIImpl::isLegalMaskedExpandLoad(Type *DataTy) {
5892 if (!isa<VectorType>(DataTy))
5893 return false;
5894
5895 if (!ST->hasAVX512())
5896 return false;
5897
5898 // The backend can't handle a single element vector.
5899 if (cast<FixedVectorType>(DataTy)->getNumElements() == 1)
5900 return false;
5901
5902 Type *ScalarTy = cast<VectorType>(DataTy)->getElementType();
5903
5904 if (ScalarTy->isFloatTy() || ScalarTy->isDoubleTy())
5905 return true;
5906
5907 if (!ScalarTy->isIntegerTy())
5908 return false;
5909
5910 unsigned IntWidth = ScalarTy->getIntegerBitWidth();
5911 return IntWidth == 32 || IntWidth == 64 ||
5912 ((IntWidth == 8 || IntWidth == 16) && ST->hasVBMI2());
5913}
5914
5915bool X86TTIImpl::isLegalMaskedCompressStore(Type *DataTy) {
5916 return isLegalMaskedExpandLoad(DataTy);
5917}
5918
5919bool X86TTIImpl::supportsGather() const {
5920 // Some CPUs have better gather performance than others.
5921 // TODO: Remove the explicit ST->hasAVX512()?, That would mean we would only
5922 // enable gather with a -march.
5923 return ST->hasAVX512() || (ST->hasFastGather() && ST->hasAVX2());
5924}
5925
5926bool X86TTIImpl::forceScalarizeMaskedGather(VectorType *VTy, Align Alignment) {
5927 // Gather / Scatter for vector 2 is not profitable on KNL / SKX
5928 // Vector-4 of gather/scatter instruction does not exist on KNL. We can extend
5929 // it to 8 elements, but zeroing upper bits of the mask vector will add more
5930 // instructions. Right now we give the scalar cost of vector-4 for KNL. TODO:
5931 // Check, maybe the gather/scatter instruction is better in the VariableMask
5932 // case.
5933 unsigned NumElts = cast<FixedVectorType>(VTy)->getNumElements();
5934 return NumElts == 1 ||
5935 (ST->hasAVX512() && (NumElts == 2 || (NumElts == 4 && !ST->hasVLX())));
5936}
5937
5938bool X86TTIImpl::isLegalMaskedGather(Type *DataTy, Align Alignment) {
5939 if (!supportsGather())
5940 return false;
5941 Type *ScalarTy = DataTy->getScalarType();
5942 if (ScalarTy->isPointerTy())
5943 return true;
5944
5945 if (ScalarTy->isFloatTy() || ScalarTy->isDoubleTy())
5946 return true;
5947
5948 if (!ScalarTy->isIntegerTy())
5949 return false;
5950
5951 unsigned IntWidth = ScalarTy->getIntegerBitWidth();
5952 return IntWidth == 32 || IntWidth == 64;
5953}
5954
5955bool X86TTIImpl::isLegalAltInstr(VectorType *VecTy, unsigned Opcode0,
5956 unsigned Opcode1,
5957 const SmallBitVector &OpcodeMask) const {
5958 // ADDSUBPS 4xf32 SSE3
5959 // VADDSUBPS 4xf32 AVX
5960 // VADDSUBPS 8xf32 AVX2
5961 // ADDSUBPD 2xf64 SSE3
5962 // VADDSUBPD 2xf64 AVX
5963 // VADDSUBPD 4xf64 AVX2
5964
5965 unsigned NumElements = cast<FixedVectorType>(VecTy)->getNumElements();
5966 assert(OpcodeMask.size() == NumElements && "Mask and VecTy are incompatible")(static_cast <bool> (OpcodeMask.size() == NumElements &&
"Mask and VecTy are incompatible") ? void (0) : __assert_fail
("OpcodeMask.size() == NumElements && \"Mask and VecTy are incompatible\""
, "llvm/lib/Target/X86/X86TargetTransformInfo.cpp", 5966, __extension__
__PRETTY_FUNCTION__));
5967 if (!isPowerOf2_32(NumElements))
5968 return false;
5969 // Check the opcode pattern. We apply the mask on the opcode arguments and
5970 // then check if it is what we expect.
5971 for (int Lane : seq<int>(0, NumElements)) {
5972 unsigned Opc = OpcodeMask.test(Lane) ? Opcode1 : Opcode0;
5973 // We expect FSub for even lanes and FAdd for odd lanes.
5974 if (Lane % 2 == 0 && Opc != Instruction::FSub)
5975 return false;
5976 if (Lane % 2 == 1 && Opc != Instruction::FAdd)
5977 return false;
5978 }
5979 // Now check that the pattern is supported by the target ISA.
5980 Type *ElemTy = cast<VectorType>(VecTy)->getElementType();
5981 if (ElemTy->isFloatTy())
5982 return ST->hasSSE3() && NumElements % 4 == 0;
5983 if (ElemTy->isDoubleTy())
5984 return ST->hasSSE3() && NumElements % 2 == 0;
5985 return false;
5986}
5987
5988bool X86TTIImpl::isLegalMaskedScatter(Type *DataType, Align Alignment) {
5989 // AVX2 doesn't support scatter
5990 if (!ST->hasAVX512())
5991 return false;
5992 return isLegalMaskedGather(DataType, Alignment);
5993}
5994
5995bool X86TTIImpl::hasDivRemOp(Type *DataType, bool IsSigned) {
5996 EVT VT = TLI->getValueType(DL, DataType);
5997 return TLI->isOperationLegal(IsSigned ? ISD::SDIVREM : ISD::UDIVREM, VT);
5998}
5999
6000bool X86TTIImpl::isExpensiveToSpeculativelyExecute(const Instruction* I) {
6001 // FDIV is always expensive, even if it has a very low uop count.
6002 // TODO: Still necessary for recent CPUs with low latency/throughput fdiv?
6003 if (I->getOpcode() == Instruction::FDiv)
6004 return true;
6005
6006 return BaseT::isExpensiveToSpeculativelyExecute(I);
6007}
6008
6009bool X86TTIImpl::isFCmpOrdCheaperThanFCmpZero(Type *Ty) {
6010 return false;
6011}
6012
6013bool X86TTIImpl::areInlineCompatible(const Function *Caller,
6014 const Function *Callee) const {
6015 const TargetMachine &TM = getTLI()->getTargetMachine();
6016
6017 // Work this as a subsetting of subtarget features.
6018 const FeatureBitset &CallerBits =
6019 TM.getSubtargetImpl(*Caller)->getFeatureBits();
6020 const FeatureBitset &CalleeBits =
6021 TM.getSubtargetImpl(*Callee)->getFeatureBits();
6022
6023 // Check whether features are the same (apart from the ignore list).
6024 FeatureBitset RealCallerBits = CallerBits & ~InlineFeatureIgnoreList;
6025 FeatureBitset RealCalleeBits = CalleeBits & ~InlineFeatureIgnoreList;
6026 if (RealCallerBits == RealCalleeBits)
6027 return true;
6028
6029 // If the features are a subset, we need to additionally check for calls
6030 // that may become ABI-incompatible as a result of inlining.
6031 if ((RealCallerBits & RealCalleeBits) != RealCalleeBits)
6032 return false;
6033
6034 for (const Instruction &I : instructions(Callee)) {
6035 if (const auto *CB = dyn_cast<CallBase>(&I)) {
6036 SmallVector<Type *, 8> Types;
6037 for (Value *Arg : CB->args())
6038 Types.push_back(Arg->getType());
6039 if (!CB->getType()->isVoidTy())
6040 Types.push_back(CB->getType());
6041
6042 // Simple types are always ABI compatible.
6043 auto IsSimpleTy = [](Type *Ty) {
6044 return !Ty->isVectorTy() && !Ty->isAggregateType();
6045 };
6046 if (all_of(Types, IsSimpleTy))
6047 continue;
6048
6049 if (Function *NestedCallee = CB->getCalledFunction()) {
6050 // Assume that intrinsics are always ABI compatible.
6051 if (NestedCallee->isIntrinsic())
6052 continue;
6053
6054 // Do a precise compatibility check.
6055 if (!areTypesABICompatible(Caller, NestedCallee, Types))
6056 return false;
6057 } else {
6058 // We don't know the target features of the callee,
6059 // assume it is incompatible.
6060 return false;
6061 }
6062 }
6063 }
6064 return true;
6065}
6066
6067bool X86TTIImpl::areTypesABICompatible(const Function *Caller,
6068 const Function *Callee,
6069 const ArrayRef<Type *> &Types) const {
6070 if (!BaseT::areTypesABICompatible(Caller, Callee, Types))
6071 return false;
6072
6073 // If we get here, we know the target features match. If one function
6074 // considers 512-bit vectors legal and the other does not, consider them
6075 // incompatible.
6076 const TargetMachine &TM = getTLI()->getTargetMachine();
6077
6078 if (TM.getSubtarget<X86Subtarget>(*Caller).useAVX512Regs() ==
6079 TM.getSubtarget<X86Subtarget>(*Callee).useAVX512Regs())
6080 return true;
6081
6082 // Consider the arguments compatible if they aren't vectors or aggregates.
6083 // FIXME: Look at the size of vectors.
6084 // FIXME: Look at the element types of aggregates to see if there are vectors.
6085 return llvm::none_of(Types,
6086 [](Type *T) { return T->isVectorTy() || T->isAggregateType(); });
6087}
6088
6089X86TTIImpl::TTI::MemCmpExpansionOptions
6090X86TTIImpl::enableMemCmpExpansion(bool OptSize, bool IsZeroCmp) const {
6091 TTI::MemCmpExpansionOptions Options;
6092 Options.MaxNumLoads = TLI->getMaxExpandSizeMemcmp(OptSize);
6093 Options.NumLoadsPerBlock = 2;
6094 // All GPR and vector loads can be unaligned.
6095 Options.AllowOverlappingLoads = true;
6096 if (IsZeroCmp) {
6097 // Only enable vector loads for equality comparison. Right now the vector
6098 // version is not as fast for three way compare (see #33329).
6099 const unsigned PreferredWidth = ST->getPreferVectorWidth();
6100 if (PreferredWidth >= 512 && ST->hasAVX512()) Options.LoadSizes.push_back(64);
6101 if (PreferredWidth >= 256 && ST->hasAVX()) Options.LoadSizes.push_back(32);
6102 if (PreferredWidth >= 128 && ST->hasSSE2()) Options.LoadSizes.push_back(16);
6103 }
6104 if (ST->is64Bit()) {
6105 Options.LoadSizes.push_back(8);
6106 }
6107 Options.LoadSizes.push_back(4);
6108 Options.LoadSizes.push_back(2);
6109 Options.LoadSizes.push_back(1);
6110 return Options;
6111}
6112
6113bool X86TTIImpl::prefersVectorizedAddressing() const {
6114 return supportsGather();
6115}
6116
6117bool X86TTIImpl::supportsEfficientVectorElementLoadStore() const {
6118 return false;
6119}
6120
6121bool X86TTIImpl::enableInterleavedAccessVectorization() {
6122 // TODO: We expect this to be beneficial regardless of arch,
6123 // but there are currently some unexplained performance artifacts on Atom.
6124 // As a temporary solution, disable on Atom.
6125 return !(ST->isAtom());
6126}
6127
6128// Get estimation for interleaved load/store operations and strided load.
6129// \p Indices contains indices for strided load.
6130// \p Factor - the factor of interleaving.
6131// AVX-512 provides 3-src shuffles that significantly reduces the cost.
6132InstructionCost X86TTIImpl::getInterleavedMemoryOpCostAVX512(
6133 unsigned Opcode, FixedVectorType *VecTy, unsigned Factor,
6134 ArrayRef<unsigned> Indices, Align Alignment, unsigned AddressSpace,
6135 TTI::TargetCostKind CostKind, bool UseMaskForCond, bool UseMaskForGaps) {
6136 // VecTy for interleave memop is <VF*Factor x Elt>.
6137 // So, for VF=4, Interleave Factor = 3, Element type = i32 we have
6138 // VecTy = <12 x i32>.
6139
6140 // Calculate the number of memory operations (NumOfMemOps), required
6141 // for load/store the VecTy.
6142 MVT LegalVT = getTypeLegalizationCost(VecTy).second;
6143 unsigned VecTySize = DL.getTypeStoreSize(VecTy);
6144 unsigned LegalVTSize = LegalVT.getStoreSize();
6145 unsigned NumOfMemOps = (VecTySize + LegalVTSize - 1) / LegalVTSize;
6146
6147 // Get the cost of one memory operation.
6148 auto *SingleMemOpTy = FixedVectorType::get(VecTy->getElementType(),
6149 LegalVT.getVectorNumElements());
6150 InstructionCost MemOpCost;
6151 bool UseMaskedMemOp = UseMaskForCond || UseMaskForGaps;
6152 if (UseMaskedMemOp)
6153 MemOpCost = getMaskedMemoryOpCost(Opcode, SingleMemOpTy, Alignment,
6154 AddressSpace, CostKind);
6155 else
6156 MemOpCost = getMemoryOpCost(Opcode, SingleMemOpTy, MaybeAlign(Alignment),
6157 AddressSpace, CostKind);
6158
6159 unsigned VF = VecTy->getNumElements() / Factor;
6160 MVT VT = MVT::getVectorVT(MVT::getVT(VecTy->getScalarType()), VF);
6161
6162 InstructionCost MaskCost;
6163 if (UseMaskedMemOp) {
6164 APInt DemandedLoadStoreElts = APInt::getZero(VecTy->getNumElements());
6165 for (unsigned Index : Indices) {
6166 assert(Index < Factor && "Invalid index for interleaved memory op")(static_cast <bool> (Index < Factor && "Invalid index for interleaved memory op"
) ? void (0) : __assert_fail ("Index < Factor && \"Invalid index for interleaved memory op\""
, "llvm/lib/Target/X86/X86TargetTransformInfo.cpp", 6166, __extension__
__PRETTY_FUNCTION__));
6167 for (unsigned Elm = 0; Elm < VF; Elm++)
6168 DemandedLoadStoreElts.setBit(Index + Elm * Factor);
6169 }
6170
6171 Type *I1Type = Type::getInt1Ty(VecTy->getContext());
6172
6173 MaskCost = getReplicationShuffleCost(
6174 I1Type, Factor, VF,
6175 UseMaskForGaps ? DemandedLoadStoreElts
6176 : APInt::getAllOnes(VecTy->getNumElements()),
6177 CostKind);
6178
6179 // The Gaps mask is invariant and created outside the loop, therefore the
6180 // cost of creating it is not accounted for here. However if we have both
6181 // a MaskForGaps and some other mask that guards the execution of the
6182 // memory access, we need to account for the cost of And-ing the two masks
6183 // inside the loop.
6184 if (UseMaskForGaps) {
6185 auto *MaskVT = FixedVectorType::get(I1Type, VecTy->getNumElements());
6186 MaskCost += getArithmeticInstrCost(BinaryOperator::And, MaskVT, CostKind);
6187 }
6188 }
6189
6190 if (Opcode == Instruction::Load) {
6191 // The tables (AVX512InterleavedLoadTbl and AVX512InterleavedStoreTbl)
6192 // contain the cost of the optimized shuffle sequence that the
6193 // X86InterleavedAccess pass will generate.
6194 // The cost of loads and stores are computed separately from the table.
6195
6196 // X86InterleavedAccess support only the following interleaved-access group.
6197 static const CostTblEntry AVX512InterleavedLoadTbl[] = {
6198 {3, MVT::v16i8, 12}, //(load 48i8 and) deinterleave into 3 x 16i8
6199 {3, MVT::v32i8, 14}, //(load 96i8 and) deinterleave into 3 x 32i8
6200 {3, MVT::v64i8, 22}, //(load 96i8 and) deinterleave into 3 x 32i8
6201 };
6202
6203 if (const auto *Entry =
6204 CostTableLookup(AVX512InterleavedLoadTbl, Factor, VT))
6205 return MaskCost + NumOfMemOps * MemOpCost + Entry->Cost;
6206 //If an entry does not exist, fallback to the default implementation.
6207
6208 // Kind of shuffle depends on number of loaded values.
6209 // If we load the entire data in one register, we can use a 1-src shuffle.
6210 // Otherwise, we'll merge 2 sources in each operation.
6211 TTI::ShuffleKind ShuffleKind =
6212 (NumOfMemOps > 1) ? TTI::SK_PermuteTwoSrc : TTI::SK_PermuteSingleSrc;
6213
6214 InstructionCost ShuffleCost = getShuffleCost(
6215 ShuffleKind, SingleMemOpTy, std::nullopt, CostKind, 0, nullptr);
6216
6217 unsigned NumOfLoadsInInterleaveGrp =
6218 Indices.size() ? Indices.size() : Factor;
6219 auto *ResultTy = FixedVectorType::get(VecTy->getElementType(),
6220 VecTy->getNumElements() / Factor);
6221 InstructionCost NumOfResults =
6222 getTypeLegalizationCost(ResultTy).first * NumOfLoadsInInterleaveGrp;
6223
6224 // About a half of the loads may be folded in shuffles when we have only
6225 // one result. If we have more than one result, or the loads are masked,
6226 // we do not fold loads at all.
6227 unsigned NumOfUnfoldedLoads =
6228 UseMaskedMemOp || NumOfResults > 1 ? NumOfMemOps : NumOfMemOps / 2;
6229
6230 // Get a number of shuffle operations per result.
6231 unsigned NumOfShufflesPerResult =
6232 std::max((unsigned)1, (unsigned)(NumOfMemOps - 1));
6233
6234 // The SK_MergeTwoSrc shuffle clobbers one of src operands.
6235 // When we have more than one destination, we need additional instructions
6236 // to keep sources.
6237 InstructionCost NumOfMoves = 0;
6238 if (NumOfResults > 1 && ShuffleKind == TTI::SK_PermuteTwoSrc)
6239 NumOfMoves = NumOfResults * NumOfShufflesPerResult / 2;
6240
6241 InstructionCost Cost = NumOfResults * NumOfShufflesPerResult * ShuffleCost +
6242 MaskCost + NumOfUnfoldedLoads * MemOpCost +
6243 NumOfMoves;
6244
6245 return Cost;
6246 }
6247
6248 // Store.
6249 assert(Opcode == Instruction::Store &&(static_cast <bool> (Opcode == Instruction::Store &&
"Expected Store Instruction at this point") ? void (0) : __assert_fail
("Opcode == Instruction::Store && \"Expected Store Instruction at this point\""
, "llvm/lib/Target/X86/X86TargetTransformInfo.cpp", 6250, __extension__
__PRETTY_FUNCTION__))
6250 "Expected Store Instruction at this point")(static_cast <bool> (Opcode == Instruction::Store &&
"Expected Store Instruction at this point") ? void (0) : __assert_fail
("Opcode == Instruction::Store && \"Expected Store Instruction at this point\""
, "llvm/lib/Target/X86/X86TargetTransformInfo.cpp", 6250, __extension__
__PRETTY_FUNCTION__));
6251 // X86InterleavedAccess support only the following interleaved-access group.
6252 static const CostTblEntry AVX512InterleavedStoreTbl[] = {
6253 {3, MVT::v16i8, 12}, // interleave 3 x 16i8 into 48i8 (and store)
6254 {3, MVT::v32i8, 14}, // interleave 3 x 32i8 into 96i8 (and store)
6255 {3, MVT::v64i8, 26}, // interleave 3 x 64i8 into 96i8 (and store)
6256
6257 {4, MVT::v8i8, 10}, // interleave 4 x 8i8 into 32i8 (and store)
6258 {4, MVT::v16i8, 11}, // interleave 4 x 16i8 into 64i8 (and store)
6259 {4, MVT::v32i8, 14}, // interleave 4 x 32i8 into 128i8 (and store)
6260 {4, MVT::v64i8, 24} // interleave 4 x 32i8 into 256i8 (and store)
6261 };
6262
6263 if (const auto *Entry =
6264 CostTableLookup(AVX512InterleavedStoreTbl, Factor, VT))
6265 return MaskCost + NumOfMemOps * MemOpCost + Entry->Cost;
6266 //If an entry does not exist, fallback to the default implementation.
6267
6268 // There is no strided stores meanwhile. And store can't be folded in
6269 // shuffle.
6270 unsigned NumOfSources = Factor; // The number of values to be merged.
6271 InstructionCost ShuffleCost = getShuffleCost(
6272 TTI::SK_PermuteTwoSrc, SingleMemOpTy, std::nullopt, CostKind, 0, nullptr);
6273 unsigned NumOfShufflesPerStore = NumOfSources - 1;
6274
6275 // The SK_MergeTwoSrc shuffle clobbers one of src operands.
6276 // We need additional instructions to keep sources.
6277 unsigned NumOfMoves = NumOfMemOps * NumOfShufflesPerStore / 2;
6278 InstructionCost Cost =
6279 MaskCost +
6280 NumOfMemOps * (MemOpCost + NumOfShufflesPerStore * ShuffleCost) +
6281 NumOfMoves;
6282 return Cost;
6283}
6284
6285InstructionCost X86TTIImpl::getInterleavedMemoryOpCost(
6286 unsigned Opcode, Type *BaseTy, unsigned Factor, ArrayRef<unsigned> Indices,
6287 Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind,
6288 bool UseMaskForCond, bool UseMaskForGaps) {
6289 auto *VecTy = cast<FixedVectorType>(BaseTy);
6290
6291 auto isSupportedOnAVX512 = [&](Type *VecTy, bool HasBW) {
6292 Type *EltTy = cast<VectorType>(VecTy)->getElementType();
6293 if (EltTy->isFloatTy() || EltTy->isDoubleTy() || EltTy->isIntegerTy(64) ||
6294 EltTy->isIntegerTy(32) || EltTy->isPointerTy())
6295 return true;
6296 if (EltTy->isIntegerTy(16) || EltTy->isIntegerTy(8) || EltTy->isHalfTy())
6297 return HasBW;
6298 return false;
6299 };
6300 if (ST->hasAVX512() && isSupportedOnAVX512(VecTy, ST->hasBWI()))
6301 return getInterleavedMemoryOpCostAVX512(
6302 Opcode, VecTy, Factor, Indices, Alignment,
6303 AddressSpace, CostKind, UseMaskForCond, UseMaskForGaps);
6304
6305 if (UseMaskForCond || UseMaskForGaps)
6306 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices,
6307 Alignment, AddressSpace, CostKind,
6308 UseMaskForCond, UseMaskForGaps);
6309
6310 // Get estimation for interleaved load/store operations for SSE-AVX2.
6311 // As opposed to AVX-512, SSE-AVX2 do not have generic shuffles that allow
6312 // computing the cost using a generic formula as a function of generic
6313 // shuffles. We therefore use a lookup table instead, filled according to
6314 // the instruction sequences that codegen currently generates.
6315
6316 // VecTy for interleave memop is <VF*Factor x Elt>.
6317 // So, for VF=4, Interleave Factor = 3, Element type = i32 we have
6318 // VecTy = <12 x i32>.
6319 MVT LegalVT = getTypeLegalizationCost(VecTy).second;
6320
6321 // This function can be called with VecTy=<6xi128>, Factor=3, in which case
6322 // the VF=2, while v2i128 is an unsupported MVT vector type
6323 // (see MachineValueType.h::getVectorVT()).
6324 if (!LegalVT.isVector())
6325 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices,
6326 Alignment, AddressSpace, CostKind);
6327
6328 unsigned VF = VecTy->getNumElements() / Factor;
6329 Type *ScalarTy = VecTy->getElementType();
6330 // Deduplicate entries, model floats/pointers as appropriately-sized integers.
6331 if (!ScalarTy->isIntegerTy())
6332 ScalarTy =
6333 Type::getIntNTy(ScalarTy->getContext(), DL.getTypeSizeInBits(ScalarTy));
6334
6335 // Get the cost of all the memory operations.
6336 // FIXME: discount dead loads.
6337 InstructionCost MemOpCosts = getMemoryOpCost(
6338 Opcode, VecTy, MaybeAlign(Alignment), AddressSpace, CostKind);
6339
6340 auto *VT = FixedVectorType::get(ScalarTy, VF);
6341 EVT ETy = TLI->getValueType(DL, VT);
6342 if (!ETy.isSimple())
6343 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices,
6344 Alignment, AddressSpace, CostKind);
6345
6346 // TODO: Complete for other data-types and strides.
6347 // Each combination of Stride, element bit width and VF results in a different
6348 // sequence; The cost tables are therefore accessed with:
6349 // Factor (stride) and VectorType=VFxiN.
6350 // The Cost accounts only for the shuffle sequence;
6351 // The cost of the loads/stores is accounted for separately.
6352 //
6353 static const CostTblEntry AVX2InterleavedLoadTbl[] = {
6354 {2, MVT::v2i8, 2}, // (load 4i8 and) deinterleave into 2 x 2i8
6355 {2, MVT::v4i8, 2}, // (load 8i8 and) deinterleave into 2 x 4i8
6356 {2, MVT::v8i8, 2}, // (load 16i8 and) deinterleave into 2 x 8i8
6357 {2, MVT::v16i8, 4}, // (load 32i8 and) deinterleave into 2 x 16i8
6358 {2, MVT::v32i8, 6}, // (load 64i8 and) deinterleave into 2 x 32i8
6359
6360 {2, MVT::v8i16, 6}, // (load 16i16 and) deinterleave into 2 x 8i16
6361 {2, MVT::v16i16, 9}, // (load 32i16 and) deinterleave into 2 x 16i16
6362 {2, MVT::v32i16, 18}, // (load 64i16 and) deinterleave into 2 x 32i16
6363
6364 {2, MVT::v8i32, 4}, // (load 16i32 and) deinterleave into 2 x 8i32
6365 {2, MVT::v16i32, 8}, // (load 32i32 and) deinterleave into 2 x 16i32
6366 {2, MVT::v32i32, 16}, // (load 64i32 and) deinterleave into 2 x 32i32
6367
6368 {2, MVT::v4i64, 4}, // (load 8i64 and) deinterleave into 2 x 4i64
6369 {2, MVT::v8i64, 8}, // (load 16i64 and) deinterleave into 2 x 8i64
6370 {2, MVT::v16i64, 16}, // (load 32i64 and) deinterleave into 2 x 16i64
6371 {2, MVT::v32i64, 32}, // (load 64i64 and) deinterleave into 2 x 32i64
6372
6373 {3, MVT::v2i8, 3}, // (load 6i8 and) deinterleave into 3 x 2i8
6374 {3, MVT::v4i8, 3}, // (load 12i8 and) deinterleave into 3 x 4i8
6375 {3, MVT::v8i8, 6}, // (load 24i8 and) deinterleave into 3 x 8i8
6376 {3, MVT::v16i8, 11}, // (load 48i8 and) deinterleave into 3 x 16i8
6377 {3, MVT::v32i8, 14}, // (load 96i8 and) deinterleave into 3 x 32i8
6378
6379 {3, MVT::v2i16, 5}, // (load 6i16 and) deinterleave into 3 x 2i16
6380 {3, MVT::v4i16, 7}, // (load 12i16 and) deinterleave into 3 x 4i16
6381 {3, MVT::v8i16, 9}, // (load 24i16 and) deinterleave into 3 x 8i16
6382 {3, MVT::v16i16, 28}, // (load 48i16 and) deinterleave into 3 x 16i16
6383 {3, MVT::v32i16, 56}, // (load 96i16 and) deinterleave into 3 x 32i16
6384
6385 {3, MVT::v2i32, 3}, // (load 6i32 and) deinterleave into 3 x 2i32
6386 {3, MVT::v4i32, 3}, // (load 12i32 and) deinterleave into 3 x 4i32
6387 {3, MVT::v8i32, 7}, // (load 24i32 and) deinterleave into 3 x 8i32
6388 {3, MVT::v16i32, 14}, // (load 48i32 and) deinterleave into 3 x 16i32
6389 {3, MVT::v32i32, 32}, // (load 96i32 and) deinterleave into 3 x 32i32
6390
6391 {3, MVT::v2i64, 1}, // (load 6i64 and) deinterleave into 3 x 2i64
6392 {3, MVT::v4i64, 5}, // (load 12i64 and) deinterleave into 3 x 4i64
6393 {3, MVT::v8i64, 10}, // (load 24i64 and) deinterleave into 3 x 8i64
6394 {3, MVT::v16i64, 20}, // (load 48i64 and) deinterleave into 3 x 16i64
6395
6396 {4, MVT::v2i8, 4}, // (load 8i8 and) deinterleave into 4 x 2i8
6397 {4, MVT::v4i8, 4}, // (load 16i8 and) deinterleave into 4 x 4i8
6398 {4, MVT::v8i8, 12}, // (load 32i8 and) deinterleave into 4 x 8i8
6399 {4, MVT::v16i8, 24}, // (load 64i8 and) deinterleave into 4 x 16i8
6400 {4, MVT::v32i8, 56}, // (load 128i8 and) deinterleave into 4 x 32i8
6401
6402 {4, MVT::v2i16, 6}, // (load 8i16 and) deinterleave into 4 x 2i16
6403 {4, MVT::v4i16, 17}, // (load 16i16 and) deinterleave into 4 x 4i16
6404 {4, MVT::v8i16, 33}, // (load 32i16 and) deinterleave into 4 x 8i16
6405 {4, MVT::v16i16, 75}, // (load 64i16 and) deinterleave into 4 x 16i16
6406 {4, MVT::v32i16, 150}, // (load 128i16 and) deinterleave into 4 x 32i16
6407
6408 {4, MVT::v2i32, 4}, // (load 8i32 and) deinterleave into 4 x 2i32
6409 {4, MVT::v4i32, 8}, // (load 16i32 and) deinterleave into 4 x 4i32
6410 {4, MVT::v8i32, 16}, // (load 32i32 and) deinterleave into 4 x 8i32
6411 {4, MVT::v16i32, 32}, // (load 64i32 and) deinterleave into 4 x 16i32
6412 {4, MVT::v32i32, 68}, // (load 128i32 and) deinterleave into 4 x 32i32
6413
6414 {4, MVT::v2i64, 6}, // (load 8i64 and) deinterleave into 4 x 2i64
6415 {4, MVT::v4i64, 8}, // (load 16i64 and) deinterleave into 4 x 4i64
6416 {4, MVT::v8i64, 20}, // (load 32i64 and) deinterleave into 4 x 8i64
6417 {4, MVT::v16i64, 40}, // (load 64i64 and) deinterleave into 4 x 16i64
6418
6419 {6, MVT::v2i8, 6}, // (load 12i8 and) deinterleave into 6 x 2i8
6420 {6, MVT::v4i8, 14}, // (load 24i8 and) deinterleave into 6 x 4i8
6421 {6, MVT::v8i8, 18}, // (load 48i8 and) deinterleave into 6 x 8i8
6422 {6, MVT::v16i8, 43}, // (load 96i8 and) deinterleave into 6 x 16i8
6423 {6, MVT::v32i8, 82}, // (load 192i8 and) deinterleave into 6 x 32i8
6424
6425 {6, MVT::v2i16, 13}, // (load 12i16 and) deinterleave into 6 x 2i16
6426 {6, MVT::v4i16, 9}, // (load 24i16 and) deinterleave into 6 x 4i16
6427 {6, MVT::v8i16, 39}, // (load 48i16 and) deinterleave into 6 x 8i16
6428 {6, MVT::v16i16, 106}, // (load 96i16 and) deinterleave into 6 x 16i16
6429 {6, MVT::v32i16, 212}, // (load 192i16 and) deinterleave into 6 x 32i16
6430
6431 {6, MVT::v2i32, 6}, // (load 12i32 and) deinterleave into 6 x 2i32
6432 {6, MVT::v4i32, 15}, // (load 24i32 and) deinterleave into 6 x 4i32
6433 {6, MVT::v8i32, 31}, // (load 48i32 and) deinterleave into 6 x 8i32
6434 {6, MVT::v16i32, 64}, // (load 96i32 and) deinterleave into 6 x 16i32
6435
6436 {6, MVT::v2i64, 6}, // (load 12i64 and) deinterleave into 6 x 2i64
6437 {6, MVT::v4i64, 18}, // (load 24i64 and) deinterleave into 6 x 4i64
6438 {6, MVT::v8i64, 36}, // (load 48i64 and) deinterleave into 6 x 8i64
6439
6440 {8, MVT::v8i32, 40} // (load 64i32 and) deinterleave into 8 x 8i32
6441 };
6442
6443 static const CostTblEntry SSSE3InterleavedLoadTbl[] = {
6444 {2, MVT::v4i16, 2}, // (load 8i16 and) deinterleave into 2 x 4i16
6445 };
6446
6447 static const CostTblEntry SSE2InterleavedLoadTbl[] = {
6448 {2, MVT::v2i16, 2}, // (load 4i16 and) deinterleave into 2 x 2i16
6449 {2, MVT::v4i16, 7}, // (load 8i16 and) deinterleave into 2 x 4i16
6450
6451 {2, MVT::v2i32, 2}, // (load 4i32 and) deinterleave into 2 x 2i32
6452 {2, MVT::v4i32, 2}, // (load 8i32 and) deinterleave into 2 x 4i32
6453
6454 {2, MVT::v2i64, 2}, // (load 4i64 and) deinterleave into 2 x 2i64
6455 };
6456
6457 static const CostTblEntry AVX2InterleavedStoreTbl[] = {
6458 {2, MVT::v16i8, 3}, // interleave 2 x 16i8 into 32i8 (and store)
6459 {2, MVT::v32i8, 4}, // interleave 2 x 32i8 into 64i8 (and store)
6460
6461 {2, MVT::v8i16, 3}, // interleave 2 x 8i16 into 16i16 (and store)
6462 {2, MVT::v16i16, 4}, // interleave 2 x 16i16 into 32i16 (and store)
6463 {2, MVT::v32i16, 8}, // interleave 2 x 32i16 into 64i16 (and store)
6464
6465 {2, MVT::v4i32, 2}, // interleave 2 x 4i32 into 8i32 (and store)
6466 {2, MVT::v8i32, 4}, // interleave 2 x 8i32 into 16i32 (and store)
6467 {2, MVT::v16i32, 8}, // interleave 2 x 16i32 into 32i32 (and store)
6468 {2, MVT::v32i32, 16}, // interleave 2 x 32i32 into 64i32 (and store)
6469
6470 {2, MVT::v2i64, 2}, // interleave 2 x 2i64 into 4i64 (and store)
6471 {2, MVT::v4i64, 4}, // interleave 2 x 4i64 into 8i64 (and store)
6472 {2, MVT::v8i64, 8}, // interleave 2 x 8i64 into 16i64 (and store)
6473 {2, MVT::v16i64, 16}, // interleave 2 x 16i64 into 32i64 (and store)
6474 {2, MVT::v32i64, 32}, // interleave 2 x 32i64 into 64i64 (and store)
6475
6476 {3, MVT::v2i8, 4}, // interleave 3 x 2i8 into 6i8 (and store)
6477 {3, MVT::v4i8, 4}, // interleave 3 x 4i8 into 12i8 (and store)
6478 {3, MVT::v8i8, 6}, // interleave 3 x 8i8 into 24i8 (and store)
6479 {3, MVT::v16i8, 11}, // interleave 3 x 16i8 into 48i8 (and store)
6480 {3, MVT::v32i8, 13}, // interleave 3 x 32i8 into 96i8 (and store)
6481
6482 {3, MVT::v2i16, 4}, // interleave 3 x 2i16 into 6i16 (and store)
6483 {3, MVT::v4i16, 6}, // interleave 3 x 4i16 into 12i16 (and store)
6484 {3, MVT::v8i16, 12}, // interleave 3 x 8i16 into 24i16 (and store)
6485 {3, MVT::v16i16, 27}, // interleave 3 x 16i16 into 48i16 (and store)
6486 {3, MVT::v32i16, 54}, // interleave 3 x 32i16 into 96i16 (and store)
6487
6488 {3, MVT::v2i32, 4}, // interleave 3 x 2i32 into 6i32 (and store)
6489 {3, MVT::v4i32, 5}, // interleave 3 x 4i32 into 12i32 (and store)
6490 {3, MVT::v8i32, 11}, // interleave 3 x 8i32 into 24i32 (and store)
6491 {3, MVT::v16i32, 22}, // interleave 3 x 16i32 into 48i32 (and store)
6492 {3, MVT::v32i32, 48}, // interleave 3 x 32i32 into 96i32 (and store)
6493
6494 {3, MVT::v2i64, 4}, // interleave 3 x 2i64 into 6i64 (and store)
6495 {3, MVT::v4i64, 6}, // interleave 3 x 4i64 into 12i64 (and store)
6496 {3, MVT::v8i64, 12}, // interleave 3 x 8i64 into 24i64 (and store)
6497 {3, MVT::v16i64, 24}, // interleave 3 x 16i64 into 48i64 (and store)
6498
6499 {4, MVT::v2i8, 4}, // interleave 4 x 2i8 into 8i8 (and store)
6500 {4, MVT::v4i8, 4}, // interleave 4 x 4i8 into 16i8 (and store)
6501 {4, MVT::v8i8, 4}, // interleave 4 x 8i8 into 32i8 (and store)
6502 {4, MVT::v16i8, 8}, // interleave 4 x 16i8 into 64i8 (and store)
6503 {4, MVT::v32i8, 12}, // interleave 4 x 32i8 into 128i8 (and store)
6504
6505 {4, MVT::v2i16, 2}, // interleave 4 x 2i16 into 8i16 (and store)
6506 {4, MVT::v4i16, 6}, // interleave 4 x 4i16 into 16i16 (and store)
6507 {4, MVT::v8i16, 10}, // interleave 4 x 8i16 into 32i16 (and store)
6508 {4, MVT::v16i16, 32}, // interleave 4 x 16i16 into 64i16 (and store)
6509 {4, MVT::v32i16, 64}, // interleave 4 x 32i16 into 128i16 (and store)
6510
6511 {4, MVT::v2i32, 5}, // interleave 4 x 2i32 into 8i32 (and store)
6512 {4, MVT::v4i32, 6}, // interleave 4 x 4i32 into 16i32 (and store)
6513 {4, MVT::v8i32, 16}, // interleave 4 x 8i32 into 32i32 (and store)
6514 {4, MVT::v16i32, 32}, // interleave 4 x 16i32 into 64i32 (and store)
6515 {4, MVT::v32i32, 64}, // interleave 4 x 32i32 into 128i32 (and store)
6516
6517 {4, MVT::v2i64, 6}, // interleave 4 x 2i64 into 8i64 (and store)
6518 {4, MVT::v4i64, 8}, // interleave 4 x 4i64 into 16i64 (and store)
6519 {4, MVT::v8i64, 20}, // interleave 4 x 8i64 into 32i64 (and store)
6520 {4, MVT::v16i64, 40}, // interleave 4 x 16i64 into 64i64 (and store)
6521
6522 {6, MVT::v2i8, 7}, // interleave 6 x 2i8 into 12i8 (and store)
6523 {6, MVT::v4i8, 9}, // interleave 6 x 4i8 into 24i8 (and store)
6524 {6, MVT::v8i8, 16}, // interleave 6 x 8i8 into 48i8 (and store)
6525 {6, MVT::v16i8, 27}, // interleave 6 x 16i8 into 96i8 (and store)
6526 {6, MVT::v32i8, 90}, // interleave 6 x 32i8 into 192i8 (and store)
6527
6528 {6, MVT::v2i16, 10}, // interleave 6 x 2i16 into 12i16 (and store)
6529 {6, MVT::v4i16, 15}, // interleave 6 x 4i16 into 24i16 (and store)
6530 {6, MVT::v8i16, 21}, // interleave 6 x 8i16 into 48i16 (and store)
6531 {6, MVT::v16i16, 58}, // interleave 6 x 16i16 into 96i16 (and store)
6532 {6, MVT::v32i16, 90}, // interleave 6 x 32i16 into 192i16 (and store)
6533
6534 {6, MVT::v2i32, 9}, // interleave 6 x 2i32 into 12i32 (and store)
6535 {6, MVT::v4i32, 12}, // interleave 6 x 4i32 into 24i32 (and store)
6536 {6, MVT::v8i32, 33}, // interleave 6 x 8i32 into 48i32 (and store)
6537 {6, MVT::v16i32, 66}, // interleave 6 x 16i32 into 96i32 (and store)
6538
6539 {6, MVT::v2i64, 8}, // interleave 6 x 2i64 into 12i64 (and store)
6540 {6, MVT::v4i64, 15}, // interleave 6 x 4i64 into 24i64 (and store)
6541 {6, MVT::v8i64, 30}, // interleave 6 x 8i64 into 48i64 (and store)
6542 };
6543
6544 static const CostTblEntry SSE2InterleavedStoreTbl[] = {
6545 {2, MVT::v2i8, 1}, // interleave 2 x 2i8 into 4i8 (and store)
6546 {2, MVT::v4i8, 1}, // interleave 2 x 4i8 into 8i8 (and store)
6547 {2, MVT::v8i8, 1}, // interleave 2 x 8i8 into 16i8 (and store)
6548
6549 {2, MVT::v2i16, 1}, // interleave 2 x 2i16 into 4i16 (and store)
6550 {2, MVT::v4i16, 1}, // interleave 2 x 4i16 into 8i16 (and store)
6551
6552 {2, MVT::v2i32, 1}, // interleave 2 x 2i32 into 4i32 (and store)
6553 };
6554
6555 if (Opcode == Instruction::Load) {
6556 auto GetDiscountedCost = [Factor, NumMembers = Indices.size(),
6557 MemOpCosts](const CostTblEntry *Entry) {
6558 // NOTE: this is just an approximation!
6559 // It can over/under -estimate the cost!
6560 return MemOpCosts + divideCeil(NumMembers * Entry->Cost, Factor);
6561 };
6562
6563 if (ST->hasAVX2())
6564 if (const auto *Entry = CostTableLookup(AVX2InterleavedLoadTbl, Factor,
6565 ETy.getSimpleVT()))
6566 return GetDiscountedCost(Entry);
6567
6568 if (ST->hasSSSE3())
6569 if (const auto *Entry = CostTableLookup(SSSE3InterleavedLoadTbl, Factor,
6570 ETy.getSimpleVT()))
6571 return GetDiscountedCost(Entry);
6572
6573 if (ST->hasSSE2())
6574 if (const auto *Entry = CostTableLookup(SSE2InterleavedLoadTbl, Factor,
6575 ETy.getSimpleVT()))
6576 return GetDiscountedCost(Entry);
6577 } else {
6578 assert(Opcode == Instruction::Store &&(static_cast <bool> (Opcode == Instruction::Store &&
"Expected Store Instruction at this point") ? void (0) : __assert_fail
("Opcode == Instruction::Store && \"Expected Store Instruction at this point\""
, "llvm/lib/Target/X86/X86TargetTransformInfo.cpp", 6579, __extension__
__PRETTY_FUNCTION__))
6579 "Expected Store Instruction at this point")(static_cast <bool> (Opcode == Instruction::Store &&
"Expected Store Instruction at this point") ? void (0) : __assert_fail
("Opcode == Instruction::Store && \"Expected Store Instruction at this point\""
, "llvm/lib/Target/X86/X86TargetTransformInfo.cpp", 6579, __extension__
__PRETTY_FUNCTION__));
6580 assert((!Indices.size() || Indices.size() == Factor) &&(static_cast <bool> ((!Indices.size() || Indices.size()
== Factor) && "Interleaved store only supports fully-interleaved groups."
) ? void (0) : __assert_fail ("(!Indices.size() || Indices.size() == Factor) && \"Interleaved store only supports fully-interleaved groups.\""
, "llvm/lib/Target/X86/X86TargetTransformInfo.cpp", 6581, __extension__
__PRETTY_FUNCTION__))
6581 "Interleaved store only supports fully-interleaved groups.")(static_cast <bool> ((!Indices.size() || Indices.size()
== Factor) && "Interleaved store only supports fully-interleaved groups."
) ? void (0) : __assert_fail ("(!Indices.size() || Indices.size() == Factor) && \"Interleaved store only supports fully-interleaved groups.\""
, "llvm/lib/Target/X86/X86TargetTransformInfo.cpp", 6581, __extension__
__PRETTY_FUNCTION__));
6582 if (ST->hasAVX2())
6583 if (const auto *Entry = CostTableLookup(AVX2InterleavedStoreTbl, Factor,
6584 ETy.getSimpleVT()))
6585 return MemOpCosts + Entry->Cost;
6586
6587 if (ST->hasSSE2())
6588 if (const auto *Entry = CostTableLookup(SSE2InterleavedStoreTbl, Factor,
6589 ETy.getSimpleVT()))
6590 return MemOpCosts + Entry->Cost;
6591 }
6592
6593 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices,
6594 Alignment, AddressSpace, CostKind,
6595 UseMaskForCond, UseMaskForGaps);
6596}
6597
6598InstructionCost X86TTIImpl::getScalingFactorCost(Type *Ty, GlobalValue *BaseGV,
6599 int64_t BaseOffset,
6600 bool HasBaseReg, int64_t Scale,
6601 unsigned AddrSpace) const {
6602 // Scaling factors are not free at all.
6603 // An indexed folded instruction, i.e., inst (reg1, reg2, scale),
6604 // will take 2 allocations in the out of order engine instead of 1
6605 // for plain addressing mode, i.e. inst (reg1).
6606 // E.g.,
6607 // vaddps (%rsi,%rdx), %ymm0, %ymm1
6608 // Requires two allocations (one for the load, one for the computation)
6609 // whereas:
6610 // vaddps (%rsi), %ymm0, %ymm1
6611 // Requires just 1 allocation, i.e., freeing allocations for other operations
6612 // and having less micro operations to execute.
6613 //
6614 // For some X86 architectures, this is even worse because for instance for
6615 // stores, the complex addressing mode forces the instruction to use the
6616 // "load" ports instead of the dedicated "store" port.
6617 // E.g., on Haswell:
6618 // vmovaps %ymm1, (%r8, %rdi) can use port 2 or 3.
6619 // vmovaps %ymm1, (%r8) can use port 2, 3, or 7.
6620 TargetLoweringBase::AddrMode AM;
6621 AM.BaseGV = BaseGV;
6622 AM.BaseOffs = BaseOffset;
6623 AM.HasBaseReg = HasBaseReg;
6624 AM.Scale = Scale;
6625 if (getTLI()->isLegalAddressingMode(DL, AM, Ty, AddrSpace))
6626 // Scale represents reg2 * scale, thus account for 1
6627 // as soon as we use a second register.
6628 return AM.Scale != 0;
6629 return -1;
6630}