Bug Summary

File:llvm/lib/Target/XCore/MCTargetDesc/XCoreInstPrinter.cpp
Warning:line 59, column 14
Called C++ object pointer is null

Annotated Source Code

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clang -cc1 -cc1 -triple x86_64-pc-linux-gnu -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name XCoreInstPrinter.cpp -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=cplusplus -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -analyzer-config-compatibility-mode=true -mrelocation-model pic -pic-level 2 -mframe-pointer=none -fmath-errno -fno-rounding-math -mconstructor-aliases -munwind-tables -target-cpu x86-64 -tune-cpu generic -debugger-tuning=gdb -ffunction-sections -fdata-sections -fcoverage-compilation-dir=/build/llvm-toolchain-snapshot-14~++20210903100615+fd66b44ec19e/build-llvm/lib/Target/XCore/MCTargetDesc -resource-dir /usr/lib/llvm-14/lib/clang/14.0.0 -D _GNU_SOURCE -D __STDC_CONSTANT_MACROS -D __STDC_FORMAT_MACROS -D __STDC_LIMIT_MACROS -I /build/llvm-toolchain-snapshot-14~++20210903100615+fd66b44ec19e/build-llvm/lib/Target/XCore/MCTargetDesc -I /build/llvm-toolchain-snapshot-14~++20210903100615+fd66b44ec19e/llvm/lib/Target/XCore/MCTargetDesc -I /build/llvm-toolchain-snapshot-14~++20210903100615+fd66b44ec19e/llvm/lib/Target/XCore -I /build/llvm-toolchain-snapshot-14~++20210903100615+fd66b44ec19e/build-llvm/lib/Target/XCore -I /build/llvm-toolchain-snapshot-14~++20210903100615+fd66b44ec19e/build-llvm/include -I /build/llvm-toolchain-snapshot-14~++20210903100615+fd66b44ec19e/llvm/include -D NDEBUG -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/10/../../../../include/c++/10 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/10/../../../../include/x86_64-linux-gnu/c++/10 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/10/../../../../include/c++/10/backward -internal-isystem /usr/lib/llvm-14/lib/clang/14.0.0/include -internal-isystem /usr/local/include -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/10/../../../../x86_64-linux-gnu/include -internal-externc-isystem /usr/include/x86_64-linux-gnu -internal-externc-isystem /include -internal-externc-isystem /usr/include -O2 -Wno-unused-parameter -Wwrite-strings -Wno-missing-field-initializers -Wno-long-long -Wno-maybe-uninitialized -Wno-class-memaccess -Wno-redundant-move -Wno-pessimizing-move -Wno-noexcept-type -Wno-comment -std=c++14 -fdeprecated-macro -fdebug-compilation-dir=/build/llvm-toolchain-snapshot-14~++20210903100615+fd66b44ec19e/build-llvm/lib/Target/XCore/MCTargetDesc -fdebug-prefix-map=/build/llvm-toolchain-snapshot-14~++20210903100615+fd66b44ec19e=. -ferror-limit 19 -fvisibility hidden -fvisibility-inlines-hidden -stack-protector 2 -fgnuc-version=4.2.1 -vectorize-loops -vectorize-slp -analyzer-output=html -analyzer-config stable-report-filename=true -faddrsig -D__GCC_HAVE_DWARF2_CFI_ASM=1 -o /tmp/scan-build-2021-09-04-040900-46481-1 -x c++ /build/llvm-toolchain-snapshot-14~++20210903100615+fd66b44ec19e/llvm/lib/Target/XCore/MCTargetDesc/XCoreInstPrinter.cpp

/build/llvm-toolchain-snapshot-14~++20210903100615+fd66b44ec19e/llvm/lib/Target/XCore/MCTargetDesc/XCoreInstPrinter.cpp

1//===-- XCoreInstPrinter.cpp - Convert XCore MCInst to assembly syntax ----===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This class prints an XCore MCInst to a .s file.
10//
11//===----------------------------------------------------------------------===//
12
13#include "XCoreInstPrinter.h"
14#include "llvm/ADT/StringRef.h"
15#include "llvm/MC/MCExpr.h"
16#include "llvm/MC/MCInst.h"
17#include "llvm/MC/MCSymbol.h"
18#include "llvm/Support/Casting.h"
19#include "llvm/Support/ErrorHandling.h"
20#include "llvm/Support/raw_ostream.h"
21#include <cassert>
22
23using namespace llvm;
24
25#define DEBUG_TYPE"asm-printer" "asm-printer"
26
27#include "XCoreGenAsmWriter.inc"
28
29void XCoreInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
30 OS << StringRef(getRegisterName(RegNo)).lower();
31}
32
33void XCoreInstPrinter::printInst(const MCInst *MI, uint64_t Address,
34 StringRef Annot, const MCSubtargetInfo &STI,
35 raw_ostream &O) {
36 printInstruction(MI, Address, O);
1
Calling 'XCoreInstPrinter::printInstruction'
37 printAnnotation(O, Annot);
38}
39
40void XCoreInstPrinter::
41printInlineJT(const MCInst *MI, int opNum, raw_ostream &O) {
42 report_fatal_error("can't handle InlineJT");
43}
44
45void XCoreInstPrinter::
46printInlineJT32(const MCInst *MI, int opNum, raw_ostream &O) {
47 report_fatal_error("can't handle InlineJT32");
48}
49
50static void printExpr(const MCExpr *Expr, const MCAsmInfo *MAI,
51 raw_ostream &OS) {
52 int Offset = 0;
53 const MCSymbolRefExpr *SRE;
54
55 if (const MCBinaryExpr *BE
7.1
'BE' is non-null
7.1
'BE' is non-null
= dyn_cast<MCBinaryExpr>(Expr)) {
7
Assuming 'Expr' is a 'MCBinaryExpr'
8
Taking true branch
56 SRE = dyn_cast<MCSymbolRefExpr>(BE->getLHS());
9
Assuming the object is not a 'MCSymbolRefExpr'
57 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(BE->getRHS());
10
Assuming the object is not a 'MCConstantExpr'
11
'CE' initialized to a null pointer value
58 assert(SRE && CE && "Binary expression must be sym+const.")(static_cast<void> (0));
59 Offset = CE->getValue();
12
Called C++ object pointer is null
60 } else {
61 SRE = dyn_cast<MCSymbolRefExpr>(Expr);
62 assert(SRE && "Unexpected MCExpr type.")(static_cast<void> (0));
63 }
64 assert(SRE->getKind() == MCSymbolRefExpr::VK_None)(static_cast<void> (0));
65
66 SRE->getSymbol().print(OS, MAI);
67
68 if (Offset) {
69 if (Offset > 0)
70 OS << '+';
71 OS << Offset;
72 }
73}
74
75void XCoreInstPrinter::
76printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
77 const MCOperand &Op = MI->getOperand(OpNo);
78 if (Op.isReg()) {
4
Taking false branch
79 printRegName(O, Op.getReg());
80 return;
81 }
82
83 if (Op.isImm()) {
5
Taking false branch
84 O << Op.getImm();
85 return;
86 }
87
88 assert(Op.isExpr() && "unknown operand kind in printOperand")(static_cast<void> (0));
89 printExpr(Op.getExpr(), &MAI, O);
6
Calling 'printExpr'
90}

/build/llvm-toolchain-snapshot-14~++20210903100615+fd66b44ec19e/build-llvm/lib/Target/XCore/XCoreGenAsmWriter.inc

1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Assembly Writer Source Fragment *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9/// getMnemonic - This method is automatically generated by tablegen
10/// from the instruction set description.
11std::pair<const char *, uint64_t> XCoreInstPrinter::getMnemonic(const MCInst *MI) {
12
13#ifdef __GNUC__4
14#pragma GCC diagnostic push
15#pragma GCC diagnostic ignored "-Woverlength-strings"
16#endif
17 static const char AsmStrs[] = {
18 /* 0 */ "ldap r11, \0"
19 /* 11 */ "getsr r11, \0"
20 /* 23 */ "set cp, \0"
21 /* 32 */ "set dp, \0"
22 /* 41 */ "set sp, \0"
23 /* 50 */ "crc32 \0"
24 /* 57 */ "lda16 \0"
25 /* 64 */ "st16 \0"
26 /* 70 */ "crc8 \0"
27 /* 76 */ "st8 \0"
28 /* 81 */ "# LDAWFI \0"
29 /* 91 */ "# LDWFI \0"
30 /* 100 */ "# STWFI \0"
31 /* 109 */ "# EH_RETURN \0"
32 /* 122 */ "# ADJCALLSTACKDOWN \0"
33 /* 142 */ "# ADJCALLSTACKUP \0"
34 /* 160 */ "# FRAME_TO_ARGS_OFFSET \0"
35 /* 184 */ "bla \0"
36 /* 189 */ "lsub \0"
37 /* 195 */ "ldc \0"
38 /* 200 */ "ladd \0"
39 /* 206 */ "and \0"
40 /* 211 */ "getd \0"
41 /* 217 */ "bf \0"
42 /* 221 */ "eef \0"
43 /* 226 */ "waitef \0"
44 /* 234 */ "ecallf \0"
45 /* 242 */ "neg \0"
46 /* 247 */ "dgetreg \0"
47 /* 256 */ "peek \0"
48 /* 262 */ "mkmsk \0"
49 /* 269 */ "bl \0"
50 /* 273 */ "testlcl \0"
51 /* 282 */ "shl \0"
52 /* 287 */ "kcall \0"
53 /* 294 */ "lmul \0"
54 /* 300 */ "endin \0"
55 /* 307 */ "getn \0"
56 /* 313 */ "extdp \0"
57 /* 320 */ "retsp \0"
58 /* 327 */ "kentsp \0"
59 /* 335 */ "krestsp \0"
60 /* 344 */ "extsp \0"
61 /* 351 */ "eq \0"
62 /* 355 */ "ashr \0"
63 /* 361 */ "inshr \0"
64 /* 368 */ "xor \0"
65 /* 373 */ "clrsr \0"
66 /* 380 */ "setsr \0"
67 /* 387 */ "getr \0"
68 /* 393 */ "ld16s \0"
69 /* 400 */ "maccs \0"
70 /* 407 */ "rems \0"
71 /* 413 */ "lss \0"
72 /* 418 */ "getts \0"
73 /* 425 */ "divs \0"
74 /* 431 */ "blat \0"
75 /* 437 */ "bt \0"
76 /* 441 */ "inct \0"
77 /* 447 */ "testct \0"
78 /* 455 */ "testwct \0"
79 /* 464 */ "eet \0"
80 /* 469 */ "get \0"
81 /* 474 */ "waitet \0"
82 /* 482 */ "ecallt \0"
83 /* 490 */ "int \0"
84 /* 495 */ "andnot \0"
85 /* 503 */ "getst \0"
86 /* 510 */ "sext \0"
87 /* 516 */ "zext \0"
88 /* 522 */ "ld8u \0"
89 /* 528 */ "bau \0"
90 /* 533 */ "bu \0"
91 /* 537 */ "maccu \0"
92 /* 544 */ "remu \0"
93 /* 550 */ "bru \0"
94 /* 555 */ "lsu \0"
95 /* 560 */ "ldivu \0"
96 /* 567 */ "byterev \0"
97 /* 576 */ "bitrev \0"
98 /* 584 */ "ldaw \0"
99 /* 590 */ "ldw \0"
100 /* 595 */ "inpw \0"
101 /* 601 */ "stw \0"
102 /* 606 */ "clz \0"
103 /* 611 */ "# SELECT_CC PSEUDO!\0"
104 /* 631 */ "# XRay Function Patchable RET.\0"
105 /* 662 */ "# XRay Typed Event Log.\0"
106 /* 686 */ "# XRay Custom Event Log.\0"
107 /* 711 */ "# XRay Function Enter.\0"
108 /* 734 */ "# XRay Tail Call Exit.\0"
109 /* 757 */ "# XRay Function Exit.\0"
110 /* 779 */ "set kep, r11\0"
111 /* 792 */ "LIFETIME_END\0"
112 /* 805 */ "PSEUDO_PROBE\0"
113 /* 818 */ "BUNDLE\0"
114 /* 825 */ "DBG_VALUE\0"
115 /* 835 */ "DBG_INSTR_REF\0"
116 /* 849 */ "DBG_PHI\0"
117 /* 857 */ "DBG_LABEL\0"
118 /* 867 */ "#MEMBARRIER\0"
119 /* 879 */ "LIFETIME_START\0"
120 /* 894 */ "DBG_VALUE_LIST\0"
121 /* 909 */ "ldaw r11, cp[\0"
122 /* 923 */ "ldw r11, cp[\0"
123 /* 936 */ "bla cp[\0"
124 /* 944 */ "msync res[\0"
125 /* 955 */ "setpsc res[\0"
126 /* 967 */ "setc res[\0"
127 /* 977 */ "setd res[\0"
128 /* 987 */ "setclk res[\0"
129 /* 999 */ "mjoin res[\0"
130 /* 1010 */ "setn res[\0"
131 /* 1020 */ "syncr res[\0"
132 /* 1031 */ "freer res[\0"
133 /* 1042 */ "outshr res[\0"
134 /* 1054 */ "chkct res[\0"
135 /* 1065 */ "outct res[\0"
136 /* 1076 */ "clrpt res[\0"
137 /* 1087 */ "setpt res[\0"
138 /* 1098 */ "outt res[\0"
139 /* 1108 */ "out res[\0"
140 /* 1117 */ "edu res[\0"
141 /* 1126 */ "eeu res[\0"
142 /* 1135 */ "setev res[\0"
143 /* 1146 */ "setv res[\0"
144 /* 1156 */ "outpw res[\0"
145 /* 1167 */ "settw res[\0"
146 /* 1178 */ "setrdy res[\0"
147 /* 1190 */ "set ps[\0"
148 /* 1198 */ "set t[\0"
149 /* 1205 */ "init t[\0"
150 /* 1213 */ "start t[\0"
151 /* 1222 */ "ldw spc, sp[1]\0"
152 /* 1237 */ "stw spc, sp[1]\0"
153 /* 1252 */ "ldw ssr, sp[2]\0"
154 /* 1267 */ "stw ssr, sp[2]\0"
155 /* 1282 */ "ldw sed, sp[3]\0"
156 /* 1297 */ "stw sed, sp[3]\0"
157 /* 1312 */ "ldw et, sp[4]\0"
158 /* 1326 */ "stw et, sp[4]\0"
159 /* 1340 */ "ssync\0"
160 /* 1346 */ "get r11, ed\0"
161 /* 1358 */ "get r11, id\0"
162 /* 1370 */ "clre\0"
163 /* 1375 */ "# FEntry call\0"
164 /* 1389 */ "dcall\0"
165 /* 1395 */ "get r11, kep\0"
166 /* 1408 */ "get r11, ksp\0"
167 /* 1421 */ "dentsp\0"
168 /* 1428 */ "drestsp\0"
169 /* 1436 */ "tsetmr r\0"
170 /* 1445 */ "get r11, et\0"
171 /* 1457 */ "freet\0"
172 /* 1463 */ "dret\0"
173 /* 1468 */ "kret\0"
174 /* 1473 */ "waiteu\0"
175};
176#ifdef __GNUC__4
177#pragma GCC diagnostic pop
178#endif
179
180 static const uint32_t OpInfo0[] = {
181 0U, // PHI
182 0U, // INLINEASM
183 0U, // INLINEASM_BR
184 0U, // CFI_INSTRUCTION
185 0U, // EH_LABEL
186 0U, // GC_LABEL
187 0U, // ANNOTATION_LABEL
188 0U, // KILL
189 0U, // EXTRACT_SUBREG
190 0U, // INSERT_SUBREG
191 0U, // IMPLICIT_DEF
192 0U, // SUBREG_TO_REG
193 0U, // COPY_TO_REGCLASS
194 826U, // DBG_VALUE
195 895U, // DBG_VALUE_LIST
196 836U, // DBG_INSTR_REF
197 850U, // DBG_PHI
198 858U, // DBG_LABEL
199 0U, // REG_SEQUENCE
200 0U, // COPY
201 819U, // BUNDLE
202 880U, // LIFETIME_START
203 793U, // LIFETIME_END
204 806U, // PSEUDO_PROBE
205 0U, // ARITH_FENCE
206 0U, // STACKMAP
207 1376U, // FENTRY_CALL
208 0U, // PATCHPOINT
209 0U, // LOAD_STACK_GUARD
210 0U, // PREALLOCATED_SETUP
211 0U, // PREALLOCATED_ARG
212 0U, // STATEPOINT
213 0U, // LOCAL_ESCAPE
214 0U, // FAULTING_OP
215 0U, // PATCHABLE_OP
216 712U, // PATCHABLE_FUNCTION_ENTER
217 632U, // PATCHABLE_RET
218 758U, // PATCHABLE_FUNCTION_EXIT
219 735U, // PATCHABLE_TAIL_CALL
220 687U, // PATCHABLE_EVENT_CALL
221 663U, // PATCHABLE_TYPED_EVENT_CALL
222 0U, // ICALL_BRANCH_FUNNEL
223 0U, // G_ASSERT_SEXT
224 0U, // G_ASSERT_ZEXT
225 0U, // G_ADD
226 0U, // G_SUB
227 0U, // G_MUL
228 0U, // G_SDIV
229 0U, // G_UDIV
230 0U, // G_SREM
231 0U, // G_UREM
232 0U, // G_SDIVREM
233 0U, // G_UDIVREM
234 0U, // G_AND
235 0U, // G_OR
236 0U, // G_XOR
237 0U, // G_IMPLICIT_DEF
238 0U, // G_PHI
239 0U, // G_FRAME_INDEX
240 0U, // G_GLOBAL_VALUE
241 0U, // G_EXTRACT
242 0U, // G_UNMERGE_VALUES
243 0U, // G_INSERT
244 0U, // G_MERGE_VALUES
245 0U, // G_BUILD_VECTOR
246 0U, // G_BUILD_VECTOR_TRUNC
247 0U, // G_CONCAT_VECTORS
248 0U, // G_PTRTOINT
249 0U, // G_INTTOPTR
250 0U, // G_BITCAST
251 0U, // G_FREEZE
252 0U, // G_INTRINSIC_TRUNC
253 0U, // G_INTRINSIC_ROUND
254 0U, // G_INTRINSIC_LRINT
255 0U, // G_INTRINSIC_ROUNDEVEN
256 0U, // G_READCYCLECOUNTER
257 0U, // G_LOAD
258 0U, // G_SEXTLOAD
259 0U, // G_ZEXTLOAD
260 0U, // G_INDEXED_LOAD
261 0U, // G_INDEXED_SEXTLOAD
262 0U, // G_INDEXED_ZEXTLOAD
263 0U, // G_STORE
264 0U, // G_INDEXED_STORE
265 0U, // G_ATOMIC_CMPXCHG_WITH_SUCCESS
266 0U, // G_ATOMIC_CMPXCHG
267 0U, // G_ATOMICRMW_XCHG
268 0U, // G_ATOMICRMW_ADD
269 0U, // G_ATOMICRMW_SUB
270 0U, // G_ATOMICRMW_AND
271 0U, // G_ATOMICRMW_NAND
272 0U, // G_ATOMICRMW_OR
273 0U, // G_ATOMICRMW_XOR
274 0U, // G_ATOMICRMW_MAX
275 0U, // G_ATOMICRMW_MIN
276 0U, // G_ATOMICRMW_UMAX
277 0U, // G_ATOMICRMW_UMIN
278 0U, // G_ATOMICRMW_FADD
279 0U, // G_ATOMICRMW_FSUB
280 0U, // G_FENCE
281 0U, // G_BRCOND
282 0U, // G_BRINDIRECT
283 0U, // G_INTRINSIC
284 0U, // G_INTRINSIC_W_SIDE_EFFECTS
285 0U, // G_ANYEXT
286 0U, // G_TRUNC
287 0U, // G_CONSTANT
288 0U, // G_FCONSTANT
289 0U, // G_VASTART
290 0U, // G_VAARG
291 0U, // G_SEXT
292 0U, // G_SEXT_INREG
293 0U, // G_ZEXT
294 0U, // G_SHL
295 0U, // G_LSHR
296 0U, // G_ASHR
297 0U, // G_FSHL
298 0U, // G_FSHR
299 0U, // G_ROTR
300 0U, // G_ROTL
301 0U, // G_ICMP
302 0U, // G_FCMP
303 0U, // G_SELECT
304 0U, // G_UADDO
305 0U, // G_UADDE
306 0U, // G_USUBO
307 0U, // G_USUBE
308 0U, // G_SADDO
309 0U, // G_SADDE
310 0U, // G_SSUBO
311 0U, // G_SSUBE
312 0U, // G_UMULO
313 0U, // G_SMULO
314 0U, // G_UMULH
315 0U, // G_SMULH
316 0U, // G_UADDSAT
317 0U, // G_SADDSAT
318 0U, // G_USUBSAT
319 0U, // G_SSUBSAT
320 0U, // G_USHLSAT
321 0U, // G_SSHLSAT
322 0U, // G_SMULFIX
323 0U, // G_UMULFIX
324 0U, // G_SMULFIXSAT
325 0U, // G_UMULFIXSAT
326 0U, // G_SDIVFIX
327 0U, // G_UDIVFIX
328 0U, // G_SDIVFIXSAT
329 0U, // G_UDIVFIXSAT
330 0U, // G_FADD
331 0U, // G_FSUB
332 0U, // G_FMUL
333 0U, // G_FMA
334 0U, // G_FMAD
335 0U, // G_FDIV
336 0U, // G_FREM
337 0U, // G_FPOW
338 0U, // G_FPOWI
339 0U, // G_FEXP
340 0U, // G_FEXP2
341 0U, // G_FLOG
342 0U, // G_FLOG2
343 0U, // G_FLOG10
344 0U, // G_FNEG
345 0U, // G_FPEXT
346 0U, // G_FPTRUNC
347 0U, // G_FPTOSI
348 0U, // G_FPTOUI
349 0U, // G_SITOFP
350 0U, // G_UITOFP
351 0U, // G_FABS
352 0U, // G_FCOPYSIGN
353 0U, // G_FCANONICALIZE
354 0U, // G_FMINNUM
355 0U, // G_FMAXNUM
356 0U, // G_FMINNUM_IEEE
357 0U, // G_FMAXNUM_IEEE
358 0U, // G_FMINIMUM
359 0U, // G_FMAXIMUM
360 0U, // G_PTR_ADD
361 0U, // G_PTRMASK
362 0U, // G_SMIN
363 0U, // G_SMAX
364 0U, // G_UMIN
365 0U, // G_UMAX
366 0U, // G_ABS
367 0U, // G_LROUND
368 0U, // G_LLROUND
369 0U, // G_BR
370 0U, // G_BRJT
371 0U, // G_INSERT_VECTOR_ELT
372 0U, // G_EXTRACT_VECTOR_ELT
373 0U, // G_SHUFFLE_VECTOR
374 0U, // G_CTTZ
375 0U, // G_CTTZ_ZERO_UNDEF
376 0U, // G_CTLZ
377 0U, // G_CTLZ_ZERO_UNDEF
378 0U, // G_CTPOP
379 0U, // G_BSWAP
380 0U, // G_BITREVERSE
381 0U, // G_FCEIL
382 0U, // G_FCOS
383 0U, // G_FSIN
384 0U, // G_FSQRT
385 0U, // G_FFLOOR
386 0U, // G_FRINT
387 0U, // G_FNEARBYINT
388 0U, // G_ADDRSPACE_CAST
389 0U, // G_BLOCK_ADDR
390 0U, // G_JUMP_TABLE
391 0U, // G_DYN_STACKALLOC
392 0U, // G_STRICT_FADD
393 0U, // G_STRICT_FSUB
394 0U, // G_STRICT_FMUL
395 0U, // G_STRICT_FDIV
396 0U, // G_STRICT_FREM
397 0U, // G_STRICT_FMA
398 0U, // G_STRICT_FSQRT
399 0U, // G_READ_REGISTER
400 0U, // G_WRITE_REGISTER
401 0U, // G_MEMCPY
402 0U, // G_MEMCPY_INLINE
403 0U, // G_MEMMOVE
404 0U, // G_MEMSET
405 0U, // G_BZERO
406 0U, // G_VECREDUCE_SEQ_FADD
407 0U, // G_VECREDUCE_SEQ_FMUL
408 0U, // G_VECREDUCE_FADD
409 0U, // G_VECREDUCE_FMUL
410 0U, // G_VECREDUCE_FMAX
411 0U, // G_VECREDUCE_FMIN
412 0U, // G_VECREDUCE_ADD
413 0U, // G_VECREDUCE_MUL
414 0U, // G_VECREDUCE_AND
415 0U, // G_VECREDUCE_OR
416 0U, // G_VECREDUCE_XOR
417 0U, // G_VECREDUCE_SMAX
418 0U, // G_VECREDUCE_SMIN
419 0U, // G_VECREDUCE_UMAX
420 0U, // G_VECREDUCE_UMIN
421 0U, // G_SBFX
422 0U, // G_UBFX
423 2171U, // ADJCALLSTACKDOWN
424 10383U, // ADJCALLSTACKUP
425 283175U, // BR_JT
426 545319U, // BR_JT32
427 2158U, // EH_RETURN
428 10401U, // FRAME_TO_ARGS_OFFSET
429 868U, // Int_MemBarrier
430 2130U, // LDAWFI
431 2140U, // LDWFI
432 612U, // SELECT_CC
433 2149U, // STWFI
434 2099402U, // ADD_2rus
435 2099402U, // ADD_3r
436 788976U, // ANDNOT_2r
437 2099407U, // AND_3r
438 2099556U, // ASHR_l2rus
439 2099556U, // ASHR_l3r
440 10769U, // BAU_1r
441 2625U, // BITREV_l2r
442 27561U, // BLACP_lu10
443 27561U, // BLACP_u10
444 10672U, // BLAT_lu6
445 10672U, // BLAT_u6
446 10425U, // BLA_1r
447 10510U, // BLRB_lu10
448 10510U, // BLRB_u10
449 10510U, // BLRF_lu10
450 10510U, // BLRF_u10
451 2266U, // BRBF_lru6
452 2266U, // BRBF_ru6
453 2486U, // BRBT_lru6
454 2486U, // BRBT_ru6
455 10774U, // BRBU_lu6
456 10774U, // BRBU_u6
457 2266U, // BRFF_lru6
458 2266U, // BRFF_ru6
459 2486U, // BRFT_lru6
460 2486U, // BRFT_ru6
461 10774U, // BRFU_lu6
462 10774U, // BRFU_u6
463 10791U, // BRU_1r
464 2616U, // BYTEREV_l2r
465 35871U, // CHKCT_2r
466 35871U, // CHKCT_rus
467 1371U, // CLRE_0R
468 27701U, // CLRPT_1R
469 10614U, // CLRSR_branch_lu6
470 10614U, // CLRSR_branch_u6
471 10614U, // CLRSR_lu6
472 10614U, // CLRSR_u6
473 2655U, // CLZ_l2r
474 5247047U, // CRC8_l4r
475 19662899U, // CRC_l3r
476 1390U, // DCALL_0R
477 1422U, // DENTSP_0R
478 10488U, // DGETREG_1r
479 2099626U, // DIVS_l3r
480 2099762U, // DIVU_l3r
481 1429U, // DRESTSP_0R
482 1464U, // DRET_0R
483 10475U, // ECALLF_1r
484 10723U, // ECALLT_1r
485 27742U, // EDU_1r
486 6334686U, // EEF_2r
487 6334929U, // EET_2r
488 27751U, // EEU_1r
489 6334765U, // ENDIN_2r
490 10569U, // ENTSP_lu6
491 10569U, // ENTSP_u6
492 2099552U, // EQ_2rus
493 2099552U, // EQ_3r
494 10554U, // EXTDP_lu6
495 10554U, // EXTDP_u6
496 10585U, // EXTSP_lu6
497 10585U, // EXTSP_u6
498 27656U, // FREER_1r
499 1458U, // FREET_0R
500 6334676U, // GETD_l2r
501 1347U, // GETED_0R
502 1446U, // GETET_0R
503 1359U, // GETID_0R
504 1396U, // GETKEP_0R
505 1409U, // GETKSP_0R
506 6334772U, // GETN_l2r
507 51670U, // GETPS_l2r
508 2436U, // GETR_rus
509 10252U, // GETSR_lu6
510 10252U, // GETSR_u6
511 6334968U, // GETST_2r
512 6334883U, // GETTS_2r
513 6334906U, // INCT_2r
514 62646U, // INITCP_2r
515 70838U, // INITDP_2r
516 79030U, // INITLR_l2r
517 87222U, // INITPC_2r
518 95414U, // INITSP_2r
519 8432212U, // INPW_l2rus
520 7121258U, // INSHR_2r
521 6334955U, // INT_2r
522 6334768U, // IN_2r
523 10528U, // KCALL_1r
524 10528U, // KCALL_lu6
525 10528U, // KCALL_u6
526 10568U, // KENTSP_lu6
527 10568U, // KENTSP_u6
528 10576U, // KRESTSP_lu6
529 10576U, // KRESTSP_u6
530 1469U, // KRET_0R
531 45093065U, // LADD_l5r
532 12585354U, // LD16S_3r
533 12585483U, // LD8U_3r
534 14682170U, // LDA16B_l3r
535 12585018U, // LDA16F_l3r
536 10241U, // LDAPB_lu10
537 10241U, // LDAPB_u10
538 10241U, // LDAPF_lu10
539 10241U, // LDAPF_lu10_ba
540 10241U, // LDAPF_u10
541 14682697U, // LDAWB_l2rus
542 14682697U, // LDAWB_l3r
543 27534U, // LDAWCP_lu6
544 27534U, // LDAWCP_u6
545 100937U, // LDAWDP_lru6
546 100937U, // LDAWDP_ru6
547 12585545U, // LDAWF_l2rus
548 12585545U, // LDAWF_l3r
549 109129U, // LDAWSP_lru6
550 109129U, // LDAWSP_ru6
551 2244U, // LDC_lru6
552 2244U, // LDC_ru6
553 1313U, // LDET_0R
554 186649137U, // LDIVU_l5r
555 1283U, // LDSED_0R
556 1223U, // LDSPC_0R
557 1253U, // LDSSR_0R
558 117327U, // LDWCP_lru6
559 27548U, // LDWCP_lu10
560 117327U, // LDWCP_ru6
561 27548U, // LDWCP_u10
562 100943U, // LDWDP_lru6
563 100943U, // LDWDP_ru6
564 109135U, // LDWSP_lru6
565 109135U, // LDWSP_ru6
566 12585551U, // LDW_2rus
567 12585551U, // LDW_3r
568 270534951U, // LMUL_l6r
569 2099614U, // LSS_3r
570 45093054U, // LSUB_l5r
571 2099756U, // LSU_3r
572 455084433U, // MACCS_l4r
573 455084570U, // MACCU_l4r
574 27624U, // MJOIN_1r
575 2311U, // MKMSK_2r
576 2311U, // MKMSK_rus
577 27569U, // MSYNC_1r
578 2099496U, // MUL_l3r
579 2291U, // NEG
580 2547U, // NOT
581 2099570U, // OR_3r
582 35882U, // OUTCT_2r
583 35882U, // OUTCT_rus
584 78681221U, // OUTPW_l2rus
585 39955U, // OUTSHR_2r
586 35915U, // OUTT_2r
587 35925U, // OUT_2r
588 6334721U, // PEEK_2r
589 2099608U, // REMS_l3r
590 2099745U, // REMU_l3r
591 10561U, // RETSP_lu6
592 10561U, // RETSP_u6
593 35804U, // SETCLK_l2r
594 10264U, // SETCP_1r
595 35784U, // SETC_l2r
596 35784U, // SETC_lru6
597 35784U, // SETC_ru6
598 10273U, // SETDP_1r
599 35794U, // SETD_2r
600 126064U, // SETEV_1r
601 780U, // SETKEP_0R
602 35827U, // SETN_l2r
603 35772U, // SETPSC_2r
604 36007U, // SETPS_l2r
605 35904U, // SETPT_2r
606 35995U, // SETRDY_l2r
607 10282U, // SETSP_1r
608 10621U, // SETSR_branch_lu6
609 10621U, // SETSR_branch_u6
610 10621U, // SETSR_lu6
611 10621U, // SETSR_u6
612 35984U, // SETTW_l2r
613 126075U, // SETV_1r
614 788991U, // SEXT_2r
615 788991U, // SEXT_rus
616 2099483U, // SHL_2rus
617 2099483U, // SHL_3r
618 2099557U, // SHR_2rus
619 2099557U, // SHR_3r
620 1341U, // SSYNC_0r
621 12585025U, // ST16_l3r
622 12585037U, // ST8_l3r
623 1327U, // STET_0R
624 1298U, // STSED_0R
625 1238U, // STSPC_0R
626 1268U, // STSSR_0R
627 100954U, // STWDP_lru6
628 100954U, // STWDP_ru6
629 109146U, // STWSP_lru6
630 109146U, // STWSP_ru6
631 12585562U, // STW_2rus
632 12585562U, // STW_l3r
633 2099391U, // SUB_2rus
634 2099391U, // SUB_3r
635 27645U, // SYNCR_1r
636 6334912U, // TESTCT_2r
637 6334738U, // TESTLCL_l2r
638 6334920U, // TESTWCT_2r
639 3485U, // TSETMR_2r
640 138415U, // TSETR_3r
641 27838U, // TSTART_1R
642 10467U, // WAITEF_1R
643 10715U, // WAITET_1R
644 1474U, // WAITEU_0R
645 2099569U, // XOR_l3r
646 788997U, // ZEXT_2r
647 788997U, // ZEXT_rus
648 };
649
650 // Emit the opcode for the instruction.
651 uint32_t Bits = 0;
652 Bits |= OpInfo0[MI->getOpcode()] << 0;
653 return {AsmStrs+(Bits & 2047)-1, Bits};
654
655}
656/// printInstruction - This method is automatically generated by tablegen
657/// from the instruction set description.
658void XCoreInstPrinter::printInstruction(const MCInst *MI, uint64_t Address, raw_ostream &O) {
659 O << "\t";
660
661 auto MnemonicInfo = getMnemonic(MI);
662
663 O << MnemonicInfo.first;
664
665 uint32_t Bits = MnemonicInfo.second;
666 assert(Bits != 0 && "Cannot print this instruction.")(static_cast<void> (0));
667
668 // Fragment 0 encoded into 2 bits for 4 unique commands.
669 switch ((Bits >> 11) & 3) {
2
Control jumps to 'case 3:' at line 683
670 default: llvm_unreachable("Invalid command number.")__builtin_unreachable();
671 case 0:
672 // DBG_VALUE, DBG_VALUE_LIST, DBG_INSTR_REF, DBG_PHI, DBG_LABEL, BUNDLE, ...
673 return;
674 break;
675 case 1:
676 // ADJCALLSTACKDOWN, ADJCALLSTACKUP, EH_RETURN, FRAME_TO_ARGS_OFFSET, LDA...
677 printOperand(MI, 0, O);
678 break;
679 case 2:
680 // BR_JT, BR_JT32, CRC8_l4r, INITCP_2r, INITDP_2r, INITLR_l2r, INITPC_2r,...
681 printOperand(MI, 1, O);
682 break;
683 case 3:
684 // OUTSHR_2r, TSETR_3r
685 printOperand(MI, 2, O);
3
Calling 'XCoreInstPrinter::printOperand'
686 break;
687 }
688
689
690 // Fragment 1 encoded into 5 bits for 17 unique commands.
691 switch ((Bits >> 13) & 31) {
692 default: llvm_unreachable("Invalid command number.")__builtin_unreachable();
693 case 0:
694 // ADJCALLSTACKDOWN, EH_RETURN, LDAWFI, LDWFI, STWFI, ADD_2rus, ADD_3r, A...
695 O << ", ";
696 break;
697 case 1:
698 // ADJCALLSTACKUP, FRAME_TO_ARGS_OFFSET, BAU_1r, BLAT_lu6, BLAT_u6, BLA_1...
699 return;
700 break;
701 case 2:
702 // BR_JT, BR_JT32
703 O << "\n";
704 break;
705 case 3:
706 // BLACP_lu10, BLACP_u10, CLRPT_1R, EDU_1r, EEU_1r, FREER_1r, LDAWCP_lu6,...
707 O << ']';
708 return;
709 break;
710 case 4:
711 // CHKCT_2r, CHKCT_rus, OUTCT_2r, OUTCT_rus, OUTPW_l2rus, OUTSHR_2r, OUTT...
712 O << "], ";
713 break;
714 case 5:
715 // EEF_2r, EET_2r, ENDIN_2r, GETD_l2r, GETN_l2r, GETST_2r, GETTS_2r, INCT...
716 O << ", res[";
717 break;
718 case 6:
719 // GETPS_l2r
720 O << ", ps[";
721 printOperand(MI, 1, O);
722 O << ']';
723 return;
724 break;
725 case 7:
726 // INITCP_2r
727 O << "]:cp, ";
728 printOperand(MI, 0, O);
729 return;
730 break;
731 case 8:
732 // INITDP_2r
733 O << "]:dp, ";
734 printOperand(MI, 0, O);
735 return;
736 break;
737 case 9:
738 // INITLR_l2r
739 O << "]:lr, ";
740 printOperand(MI, 0, O);
741 return;
742 break;
743 case 10:
744 // INITPC_2r
745 O << "]:pc, ";
746 printOperand(MI, 0, O);
747 return;
748 break;
749 case 11:
750 // INITSP_2r
751 O << "]:sp, ";
752 printOperand(MI, 0, O);
753 return;
754 break;
755 case 12:
756 // LDAWDP_lru6, LDAWDP_ru6, LDWDP_lru6, LDWDP_ru6, STWDP_lru6, STWDP_ru6
757 O << ", dp[";
758 printOperand(MI, 1, O);
759 O << ']';
760 return;
761 break;
762 case 13:
763 // LDAWSP_lru6, LDAWSP_ru6, LDWSP_lru6, LDWSP_ru6, STWSP_lru6, STWSP_ru6
764 O << ", sp[";
765 printOperand(MI, 1, O);
766 O << ']';
767 return;
768 break;
769 case 14:
770 // LDWCP_lru6, LDWCP_ru6
771 O << ", cp[";
772 printOperand(MI, 1, O);
773 O << ']';
774 return;
775 break;
776 case 15:
777 // SETEV_1r, SETV_1r
778 O << "], r11";
779 return;
780 break;
781 case 16:
782 // TSETR_3r
783 O << "]:r";
784 printOperand(MI, 0, O);
785 O << ", ";
786 printOperand(MI, 1, O);
787 return;
788 break;
789 }
790
791
792 // Fragment 2 encoded into 3 bits for 5 unique commands.
793 switch ((Bits >> 18) & 7) {
794 default: llvm_unreachable("Invalid command number.")__builtin_unreachable();
795 case 0:
796 // ADJCALLSTACKDOWN, EH_RETURN, LDAWFI, LDWFI, STWFI, ADD_2rus, ADD_3r, A...
797 printOperand(MI, 1, O);
798 break;
799 case 1:
800 // BR_JT
801 printInlineJT(MI, 0, O);
802 return;
803 break;
804 case 2:
805 // BR_JT32
806 printInlineJT32(MI, 0, O);
807 return;
808 break;
809 case 3:
810 // ANDNOT_2r, CRC_l3r, INSHR_2r, SEXT_2r, SEXT_rus, ZEXT_2r, ZEXT_rus
811 printOperand(MI, 2, O);
812 break;
813 case 4:
814 // CRC8_l4r, LADD_l5r, LSUB_l5r, OUTPW_l2rus
815 printOperand(MI, 0, O);
816 O << ", ";
817 break;
818 }
819
820
821 // Fragment 3 encoded into 3 bits for 8 unique commands.
822 switch ((Bits >> 21) & 7) {
823 default: llvm_unreachable("Invalid command number.")__builtin_unreachable();
824 case 0:
825 // ADJCALLSTACKDOWN, EH_RETURN, LDAWFI, LDWFI, STWFI, ANDNOT_2r, BITREV_l...
826 return;
827 break;
828 case 1:
829 // ADD_2rus, ADD_3r, AND_3r, ASHR_l2rus, ASHR_l3r, CRC_l3r, DIVS_l3r, DIV...
830 O << ", ";
831 break;
832 case 2:
833 // CRC8_l4r
834 printOperand(MI, 3, O);
835 O << ", ";
836 printOperand(MI, 4, O);
837 return;
838 break;
839 case 3:
840 // EEF_2r, EET_2r, ENDIN_2r, GETD_l2r, GETN_l2r, GETST_2r, GETTS_2r, INCT...
841 O << ']';
842 return;
843 break;
844 case 4:
845 // INPW_l2rus
846 O << "], ";
847 printOperand(MI, 2, O);
848 return;
849 break;
850 case 5:
851 // LADD_l5r, LSUB_l5r, OUTPW_l2rus
852 printOperand(MI, 2, O);
853 break;
854 case 6:
855 // LD16S_3r, LD8U_3r, LDA16F_l3r, LDAWF_l2rus, LDAWF_l3r, LDW_2rus, LDW_3...
856 O << '[';
857 printOperand(MI, 2, O);
858 O << ']';
859 return;
860 break;
861 case 7:
862 // LDA16B_l3r, LDAWB_l2rus, LDAWB_l3r
863 O << "[-";
864 printOperand(MI, 2, O);
865 O << ']';
866 return;
867 break;
868 }
869
870
871 // Fragment 4 encoded into 3 bits for 5 unique commands.
872 switch ((Bits >> 24) & 7) {
873 default: llvm_unreachable("Invalid command number.")__builtin_unreachable();
874 case 0:
875 // ADD_2rus, ADD_3r, AND_3r, ASHR_l2rus, ASHR_l3r, DIVS_l3r, DIVU_l3r, EQ...
876 printOperand(MI, 2, O);
877 break;
878 case 1:
879 // CRC_l3r
880 printOperand(MI, 3, O);
881 return;
882 break;
883 case 2:
884 // LADD_l5r, LSUB_l5r
885 O << ", ";
886 printOperand(MI, 3, O);
887 O << ", ";
888 printOperand(MI, 4, O);
889 return;
890 break;
891 case 3:
892 // LDIVU_l5r, MACCS_l4r, MACCU_l4r
893 printOperand(MI, 4, O);
894 O << ", ";
895 break;
896 case 4:
897 // OUTPW_l2rus
898 return;
899 break;
900 }
901
902
903 // Fragment 5 encoded into 2 bits for 4 unique commands.
904 switch ((Bits >> 27) & 3) {
905 default: llvm_unreachable("Invalid command number.")__builtin_unreachable();
906 case 0:
907 // ADD_2rus, ADD_3r, AND_3r, ASHR_l2rus, ASHR_l3r, DIVS_l3r, DIVU_l3r, EQ...
908 return;
909 break;
910 case 1:
911 // LDIVU_l5r
912 printOperand(MI, 2, O);
913 O << ", ";
914 printOperand(MI, 3, O);
915 return;
916 break;
917 case 2:
918 // LMUL_l6r
919 O << ", ";
920 printOperand(MI, 3, O);
921 O << ", ";
922 printOperand(MI, 4, O);
923 O << ", ";
924 printOperand(MI, 5, O);
925 return;
926 break;
927 case 3:
928 // MACCS_l4r, MACCU_l4r
929 printOperand(MI, 5, O);
930 return;
931 break;
932 }
933
934}
935
936
937/// getRegisterName - This method is automatically generated by tblgen
938/// from the register set description. This returns the assembler name
939/// for the specified register.
940const char *XCoreInstPrinter::getRegisterName(unsigned RegNo) {
941 assert(RegNo && RegNo < 17 && "Invalid register number!")(static_cast<void> (0));
942
943
944#ifdef __GNUC__4
945#pragma GCC diagnostic push
946#pragma GCC diagnostic ignored "-Woverlength-strings"
947#endif
948 static const char AsmStrs[] = {
949 /* 0 */ "r10\0"
950 /* 4 */ "r0\0"
951 /* 7 */ "r11\0"
952 /* 11 */ "r1\0"
953 /* 14 */ "r2\0"
954 /* 17 */ "r3\0"
955 /* 20 */ "r4\0"
956 /* 23 */ "r5\0"
957 /* 26 */ "r6\0"
958 /* 29 */ "r7\0"
959 /* 32 */ "r8\0"
960 /* 35 */ "r9\0"
961 /* 38 */ "cp\0"
962 /* 41 */ "dp\0"
963 /* 44 */ "sp\0"
964 /* 47 */ "lr\0"
965};
966#ifdef __GNUC__4
967#pragma GCC diagnostic pop
968#endif
969
970 static const uint8_t RegAsmOffset[] = {
971 38, 41, 47, 44, 4, 11, 14, 17, 20, 23, 26, 29, 32, 35,
972 0, 7,
973 };
974
975 assert (*(AsmStrs+RegAsmOffset[RegNo-1]) &&(static_cast<void> (0))
976 "Invalid alt name index for register!")(static_cast<void> (0));
977 return AsmStrs+RegAsmOffset[RegNo-1];
978}
979
980#ifdef PRINT_ALIAS_INSTR
981#undef PRINT_ALIAS_INSTR
982
983bool XCoreInstPrinter::printAliasInstr(const MCInst *MI, uint64_t Address, raw_ostream &OS) {
984 return false;
985}
986
987#endif // PRINT_ALIAS_INSTR