File: | projects/compiler-rt/lib/scudo/scudo_utils.cpp |
Warning: | line 69, column 29 The left operand of '==' is a garbage value |
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1 | //===-- scudo_utils.cpp -----------------------------------------*- C++ -*-===// | |||
2 | // | |||
3 | // The LLVM Compiler Infrastructure | |||
4 | // | |||
5 | // This file is distributed under the University of Illinois Open Source | |||
6 | // License. See LICENSE.TXT for details. | |||
7 | // | |||
8 | //===----------------------------------------------------------------------===// | |||
9 | /// | |||
10 | /// Platform specific utility functions. | |||
11 | /// | |||
12 | //===----------------------------------------------------------------------===// | |||
13 | ||||
14 | #include "scudo_utils.h" | |||
15 | ||||
16 | #if defined(__x86_64__1) || defined(__i386__) | |||
17 | # include <cpuid.h> | |||
18 | #elif defined(__arm__) || defined(__aarch64__) | |||
19 | # include "sanitizer_common/sanitizer_getauxval.h" | |||
20 | # if SANITIZER_FUCHSIA0 | |||
21 | # include <zircon/syscalls.h> | |||
22 | # include <zircon/features.h> | |||
23 | # elif SANITIZER_POSIX(0 || 1 || 0 || 0 || 0 || 0) | |||
24 | # include "sanitizer_common/sanitizer_posix.h" | |||
25 | # include <fcntl.h> | |||
26 | # endif | |||
27 | #endif | |||
28 | ||||
29 | #include <stdarg.h> | |||
30 | ||||
31 | // TODO(kostyak): remove __sanitizer *Printf uses in favor for our own less | |||
32 | // complicated string formatting code. The following is a | |||
33 | // temporary workaround to be able to use __sanitizer::VSNPrintf. | |||
34 | namespace __sanitizer { | |||
35 | ||||
36 | extern int VSNPrintf(char *buff, int buff_length, const char *format, | |||
37 | va_list args); | |||
38 | ||||
39 | } // namespace __sanitizer | |||
40 | ||||
41 | namespace __scudo { | |||
42 | ||||
43 | FORMAT(1, 2)__attribute__((format(printf, 1, 2))) void NORETURN__attribute__((noreturn)) dieWithMessage(const char *Format, ...) { | |||
44 | static const char ScudoError[] = "Scudo ERROR: "; | |||
45 | static constexpr uptr PrefixSize = sizeof(ScudoError) - 1; | |||
46 | // Our messages are tiny, 256 characters is more than enough. | |||
47 | char Message[256]; | |||
48 | va_list Args; | |||
49 | va_start(Args, Format)__builtin_va_start(Args, Format); | |||
50 | internal_memcpy(Message, ScudoError, PrefixSize); | |||
51 | VSNPrintf(Message + PrefixSize, sizeof(Message) - PrefixSize, Format, Args); | |||
52 | va_end(Args)__builtin_va_end(Args); | |||
53 | LogMessageOnPrintf(Message); | |||
54 | if (common_flags()->abort_on_error) | |||
55 | SetAbortMessage(Message); | |||
56 | RawWrite(Message); | |||
57 | Die(); | |||
58 | } | |||
59 | ||||
60 | #if defined(__x86_64__1) || defined(__i386__) | |||
61 | // i386 and x86_64 specific code to detect CRC32 hardware support via CPUID. | |||
62 | // CRC32 requires the SSE 4.2 instruction set. | |||
63 | # ifndef bit_SSE4_20x00100000 | |||
64 | # define bit_SSE4_20x00100000 bit_SSE420x00100000 // clang and gcc have different defines. | |||
65 | # endif | |||
66 | bool hasHardwareCRC32() { | |||
67 | u32 Eax, Ebx, Ecx, Edx; | |||
| ||||
68 | __get_cpuid(0, &Eax, &Ebx, &Ecx, &Edx); | |||
69 | const bool IsIntel = (Ebx == signature_INTEL_ebx0x756e6547) && | |||
| ||||
70 | (Edx == signature_INTEL_edx0x49656e69) && | |||
71 | (Ecx == signature_INTEL_ecx0x6c65746e); | |||
72 | const bool IsAMD = (Ebx == signature_AMD_ebx0x68747541) && | |||
73 | (Edx == signature_AMD_edx0x69746e65) && | |||
74 | (Ecx == signature_AMD_ecx0x444d4163); | |||
75 | if (!IsIntel && !IsAMD) | |||
76 | return false; | |||
77 | __get_cpuid(1, &Eax, &Ebx, &Ecx, &Edx); | |||
78 | return !!(Ecx & bit_SSE4_20x00100000); | |||
79 | } | |||
80 | #elif defined(__arm__) || defined(__aarch64__) | |||
81 | // For ARM and AArch64, hardware CRC32 support is indicated in the AT_HWCAP | |||
82 | // auxiliary vector. | |||
83 | # ifndef AT_HWCAP | |||
84 | # define AT_HWCAP 16 | |||
85 | # endif | |||
86 | # ifndef HWCAP_CRC32 | |||
87 | # define HWCAP_CRC32 (1 << 7) // HWCAP_CRC32 is missing on older platforms. | |||
88 | # endif | |||
89 | # if SANITIZER_POSIX(0 || 1 || 0 || 0 || 0 || 0) | |||
90 | bool hasHardwareCRC32ARMPosix() { | |||
91 | uptr F = internal_open("/proc/self/auxv", O_RDONLY); | |||
92 | if (internal_iserror(F)) | |||
93 | return false; | |||
94 | struct { uptr Tag; uptr Value; } Entry = { 0, 0 }; | |||
95 | for (;;) { | |||
96 | uptr N = internal_read(F, &Entry, sizeof(Entry)); | |||
97 | if (internal_iserror(N) || N != sizeof(Entry) || | |||
98 | (Entry.Tag == 0 && Entry.Value == 0) || Entry.Tag == AT_HWCAP) | |||
99 | break; | |||
100 | } | |||
101 | internal_close(F); | |||
102 | return (Entry.Tag == AT_HWCAP && (Entry.Value & HWCAP_CRC32) != 0); | |||
103 | } | |||
104 | # else | |||
105 | bool hasHardwareCRC32ARMPosix() { return false; } | |||
106 | # endif // SANITIZER_POSIX | |||
107 | ||||
108 | // Bionic doesn't initialize its globals early enough. This causes issues when | |||
109 | // trying to access them from a preinit_array (b/25751302) or from another | |||
110 | // constructor called before the libc one (b/68046352). __progname is | |||
111 | // initialized after the other globals, so we can check its value to know if | |||
112 | // calling getauxval is safe. | |||
113 | extern "C" SANITIZER_WEAK_ATTRIBUTE__attribute__((weak)) char *__progname; | |||
114 | INLINEinline bool areBionicGlobalsInitialized() { | |||
115 | return !SANITIZER_ANDROID0 || (&__progname && __progname); | |||
116 | } | |||
117 | ||||
118 | bool hasHardwareCRC32() { | |||
119 | #if SANITIZER_FUCHSIA0 | |||
120 | u32 HWCap; | |||
121 | zx_status_t Status = zx_system_get_features(ZX_FEATURE_KIND_CPU, &HWCap); | |||
122 | if (Status != ZX_OK || (HWCap & ZX_ARM64_FEATURE_ISA_CRC32) == 0) | |||
123 | return false; | |||
124 | return true; | |||
125 | #else | |||
126 | if (&getauxval && areBionicGlobalsInitialized()) | |||
127 | return !!(getauxval(AT_HWCAP) & HWCAP_CRC32); | |||
128 | return hasHardwareCRC32ARMPosix(); | |||
129 | #endif // SANITIZER_FUCHSIA | |||
130 | } | |||
131 | #else | |||
132 | bool hasHardwareCRC32() { return false; } | |||
133 | #endif // defined(__x86_64__) || defined(__i386__) | |||
134 | ||||
135 | } // namespace __scudo |
1 | /*===---- cpuid.h - X86 cpu model detection --------------------------------=== |
2 | * |
3 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
4 | * of this software and associated documentation files (the "Software"), to deal |
5 | * in the Software without restriction, including without limitation the rights |
6 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
7 | * copies of the Software, and to permit persons to whom the Software is |
8 | * furnished to do so, subject to the following conditions: |
9 | * |
10 | * The above copyright notice and this permission notice shall be included in |
11 | * all copies or substantial portions of the Software. |
12 | * |
13 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
14 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
15 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE |
16 | * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
17 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
18 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN |
19 | * THE SOFTWARE. |
20 | * |
21 | *===-----------------------------------------------------------------------=== |
22 | */ |
23 | |
24 | #if !(__x86_64__1 || __i386__) |
25 | #error this header is for x86 only |
26 | #endif |
27 | |
28 | /* Responses identification request with %eax 0 */ |
29 | /* AMD: "AuthenticAMD" */ |
30 | #define signature_AMD_ebx0x68747541 0x68747541 |
31 | #define signature_AMD_edx0x69746e65 0x69746e65 |
32 | #define signature_AMD_ecx0x444d4163 0x444d4163 |
33 | /* CENTAUR: "CentaurHauls" */ |
34 | #define signature_CENTAUR_ebx0x746e6543 0x746e6543 |
35 | #define signature_CENTAUR_edx0x48727561 0x48727561 |
36 | #define signature_CENTAUR_ecx0x736c7561 0x736c7561 |
37 | /* CYRIX: "CyrixInstead" */ |
38 | #define signature_CYRIX_ebx0x69727943 0x69727943 |
39 | #define signature_CYRIX_edx0x736e4978 0x736e4978 |
40 | #define signature_CYRIX_ecx0x64616574 0x64616574 |
41 | /* INTEL: "GenuineIntel" */ |
42 | #define signature_INTEL_ebx0x756e6547 0x756e6547 |
43 | #define signature_INTEL_edx0x49656e69 0x49656e69 |
44 | #define signature_INTEL_ecx0x6c65746e 0x6c65746e |
45 | /* TM1: "TransmetaCPU" */ |
46 | #define signature_TM1_ebx0x6e617254 0x6e617254 |
47 | #define signature_TM1_edx0x74656d73 0x74656d73 |
48 | #define signature_TM1_ecx0x55504361 0x55504361 |
49 | /* TM2: "GenuineTMx86" */ |
50 | #define signature_TM2_ebx0x756e6547 0x756e6547 |
51 | #define signature_TM2_edx0x54656e69 0x54656e69 |
52 | #define signature_TM2_ecx0x3638784d 0x3638784d |
53 | /* NSC: "Geode by NSC" */ |
54 | #define signature_NSC_ebx0x646f6547 0x646f6547 |
55 | #define signature_NSC_edx0x43534e20 0x43534e20 |
56 | #define signature_NSC_ecx0x79622065 0x79622065 |
57 | /* NEXGEN: "NexGenDriven" */ |
58 | #define signature_NEXGEN_ebx0x4778654e 0x4778654e |
59 | #define signature_NEXGEN_edx0x72446e65 0x72446e65 |
60 | #define signature_NEXGEN_ecx0x6e657669 0x6e657669 |
61 | /* RISE: "RiseRiseRise" */ |
62 | #define signature_RISE_ebx0x65736952 0x65736952 |
63 | #define signature_RISE_edx0x65736952 0x65736952 |
64 | #define signature_RISE_ecx0x65736952 0x65736952 |
65 | /* SIS: "SiS SiS SiS " */ |
66 | #define signature_SIS_ebx0x20536953 0x20536953 |
67 | #define signature_SIS_edx0x20536953 0x20536953 |
68 | #define signature_SIS_ecx0x20536953 0x20536953 |
69 | /* UMC: "UMC UMC UMC " */ |
70 | #define signature_UMC_ebx0x20434d55 0x20434d55 |
71 | #define signature_UMC_edx0x20434d55 0x20434d55 |
72 | #define signature_UMC_ecx0x20434d55 0x20434d55 |
73 | /* VIA: "VIA VIA VIA " */ |
74 | #define signature_VIA_ebx0x20414956 0x20414956 |
75 | #define signature_VIA_edx0x20414956 0x20414956 |
76 | #define signature_VIA_ecx0x20414956 0x20414956 |
77 | /* VORTEX: "Vortex86 SoC" */ |
78 | #define signature_VORTEX_ebx0x74726f56 0x74726f56 |
79 | #define signature_VORTEX_edx0x36387865 0x36387865 |
80 | #define signature_VORTEX_ecx0x436f5320 0x436f5320 |
81 | |
82 | /* Features in %ecx for leaf 1 */ |
83 | #define bit_SSE30x00000001 0x00000001 |
84 | #define bit_PCLMULQDQ0x00000002 0x00000002 |
85 | #define bit_PCLMUL0x00000002 bit_PCLMULQDQ0x00000002 /* for gcc compat */ |
86 | #define bit_DTES640x00000004 0x00000004 |
87 | #define bit_MONITOR0x00000008 0x00000008 |
88 | #define bit_DSCPL0x00000010 0x00000010 |
89 | #define bit_VMX0x00000020 0x00000020 |
90 | #define bit_SMX0x00000040 0x00000040 |
91 | #define bit_EIST0x00000080 0x00000080 |
92 | #define bit_TM20x00000100 0x00000100 |
93 | #define bit_SSSE30x00000200 0x00000200 |
94 | #define bit_CNXTID0x00000400 0x00000400 |
95 | #define bit_FMA0x00001000 0x00001000 |
96 | #define bit_CMPXCHG16B0x00002000 0x00002000 |
97 | #define bit_xTPR0x00004000 0x00004000 |
98 | #define bit_PDCM0x00008000 0x00008000 |
99 | #define bit_PCID0x00020000 0x00020000 |
100 | #define bit_DCA0x00040000 0x00040000 |
101 | #define bit_SSE410x00080000 0x00080000 |
102 | #define bit_SSE4_10x00080000 bit_SSE410x00080000 /* for gcc compat */ |
103 | #define bit_SSE420x00100000 0x00100000 |
104 | #define bit_SSE4_20x00100000 bit_SSE420x00100000 /* for gcc compat */ |
105 | #define bit_x2APIC0x00200000 0x00200000 |
106 | #define bit_MOVBE0x00400000 0x00400000 |
107 | #define bit_POPCNT0x00800000 0x00800000 |
108 | #define bit_TSCDeadline0x01000000 0x01000000 |
109 | #define bit_AESNI0x02000000 0x02000000 |
110 | #define bit_AES0x02000000 bit_AESNI0x02000000 /* for gcc compat */ |
111 | #define bit_XSAVE0x04000000 0x04000000 |
112 | #define bit_OSXSAVE0x08000000 0x08000000 |
113 | #define bit_AVX0x10000000 0x10000000 |
114 | #define bit_F16C0x20000000 0x20000000 |
115 | #define bit_RDRND0x40000000 0x40000000 |
116 | |
117 | /* Features in %edx for leaf 1 */ |
118 | #define bit_FPU0x00000001 0x00000001 |
119 | #define bit_VME0x00000002 0x00000002 |
120 | #define bit_DE0x00000004 0x00000004 |
121 | #define bit_PSE0x00000008 0x00000008 |
122 | #define bit_TSC0x00000010 0x00000010 |
123 | #define bit_MSR0x00000020 0x00000020 |
124 | #define bit_PAE0x00000040 0x00000040 |
125 | #define bit_MCE0x00000080 0x00000080 |
126 | #define bit_CX80x00000100 0x00000100 |
127 | #define bit_CMPXCHG8B0x00000100 bit_CX80x00000100 /* for gcc compat */ |
128 | #define bit_APIC0x00000200 0x00000200 |
129 | #define bit_SEP0x00000800 0x00000800 |
130 | #define bit_MTRR0x00001000 0x00001000 |
131 | #define bit_PGE0x00002000 0x00002000 |
132 | #define bit_MCA0x00004000 0x00004000 |
133 | #define bit_CMOV0x00008000 0x00008000 |
134 | #define bit_PAT0x00010000 0x00010000 |
135 | #define bit_PSE360x00020000 0x00020000 |
136 | #define bit_PSN0x00040000 0x00040000 |
137 | #define bit_CLFSH0x00080000 0x00080000 |
138 | #define bit_DS0x00200000 0x00200000 |
139 | #define bit_ACPI0x00400000 0x00400000 |
140 | #define bit_MMX0x00800000 0x00800000 |
141 | #define bit_FXSR0x01000000 0x01000000 |
142 | #define bit_FXSAVE0x01000000 bit_FXSR0x01000000 /* for gcc compat */ |
143 | #define bit_SSE0x02000000 0x02000000 |
144 | #define bit_SSE20x04000000 0x04000000 |
145 | #define bit_SS0x08000000 0x08000000 |
146 | #define bit_HTT0x10000000 0x10000000 |
147 | #define bit_TM0x20000000 0x20000000 |
148 | #define bit_PBE0x80000000 0x80000000 |
149 | |
150 | /* Features in %ebx for leaf 7 sub-leaf 0 */ |
151 | #define bit_FSGSBASE0x00000001 0x00000001 |
152 | #define bit_SGX0x00000004 0x00000004 |
153 | #define bit_BMI0x00000008 0x00000008 |
154 | #define bit_HLE0x00000010 0x00000010 |
155 | #define bit_AVX20x00000020 0x00000020 |
156 | #define bit_SMEP0x00000080 0x00000080 |
157 | #define bit_BMI20x00000100 0x00000100 |
158 | #define bit_ENH_MOVSB0x00000200 0x00000200 |
159 | #define bit_INVPCID0x00000400 0x00000400 |
160 | #define bit_RTM0x00000800 0x00000800 |
161 | #define bit_MPX0x00004000 0x00004000 |
162 | #define bit_AVX512F0x00010000 0x00010000 |
163 | #define bit_AVX512DQ0x00020000 0x00020000 |
164 | #define bit_RDSEED0x00040000 0x00040000 |
165 | #define bit_ADX0x00080000 0x00080000 |
166 | #define bit_AVX512IFMA0x00200000 0x00200000 |
167 | #define bit_CLFLUSHOPT0x00800000 0x00800000 |
168 | #define bit_CLWB0x01000000 0x01000000 |
169 | #define bit_AVX512PF0x04000000 0x04000000 |
170 | #define bit_AVX512ER0x08000000 0x08000000 |
171 | #define bit_AVX512CD0x10000000 0x10000000 |
172 | #define bit_SHA0x20000000 0x20000000 |
173 | #define bit_AVX512BW0x40000000 0x40000000 |
174 | #define bit_AVX512VL0x80000000 0x80000000 |
175 | |
176 | /* Features in %ecx for leaf 7 sub-leaf 0 */ |
177 | #define bit_PREFTCHWT10x00000001 0x00000001 |
178 | #define bit_AVX512VBMI0x00000002 0x00000002 |
179 | #define bit_PKU0x00000004 0x00000004 |
180 | #define bit_OSPKE0x00000010 0x00000010 |
181 | #define bit_WAITPKG0x00000020 0x00000020 |
182 | #define bit_AVX512VBMI20x00000040 0x00000040 |
183 | #define bit_SHSTK0x00000080 0x00000080 |
184 | #define bit_GFNI0x00000100 0x00000100 |
185 | #define bit_VAES0x00000200 0x00000200 |
186 | #define bit_VPCLMULQDQ0x00000400 0x00000400 |
187 | #define bit_AVX512VNNI0x00000800 0x00000800 |
188 | #define bit_AVX512BITALG0x00001000 0x00001000 |
189 | #define bit_AVX512VPOPCNTDQ0x00004000 0x00004000 |
190 | #define bit_RDPID0x00400000 0x00400000 |
191 | #define bit_CLDEMOTE0x02000000 0x02000000 |
192 | #define bit_MOVDIRI0x08000000 0x08000000 |
193 | #define bit_MOVDIR64B0x10000000 0x10000000 |
194 | |
195 | /* Features in %edx for leaf 7 sub-leaf 0 */ |
196 | #define bit_AVX5124VNNIW0x00000004 0x00000004 |
197 | #define bit_AVX5124FMAPS0x00000008 0x00000008 |
198 | #define bit_PCONFIG0x00040000 0x00040000 |
199 | #define bit_IBT0x00100000 0x00100000 |
200 | |
201 | /* Features in %eax for leaf 13 sub-leaf 1 */ |
202 | #define bit_XSAVEOPT0x00000001 0x00000001 |
203 | #define bit_XSAVEC0x00000002 0x00000002 |
204 | #define bit_XSAVES0x00000008 0x00000008 |
205 | |
206 | /* Features in %eax for leaf 0x14 sub-leaf 0 */ |
207 | #define bit_PTWRITE0x00000010 0x00000010 |
208 | |
209 | /* Features in %ecx for leaf 0x80000001 */ |
210 | #define bit_LAHF_LM0x00000001 0x00000001 |
211 | #define bit_ABM0x00000020 0x00000020 |
212 | #define bit_LZCNT0x00000020 bit_ABM0x00000020 /* for gcc compat */ |
213 | #define bit_SSE4a0x00000040 0x00000040 |
214 | #define bit_PRFCHW0x00000100 0x00000100 |
215 | #define bit_XOP0x00000800 0x00000800 |
216 | #define bit_LWP0x00008000 0x00008000 |
217 | #define bit_FMA40x00010000 0x00010000 |
218 | #define bit_TBM0x00200000 0x00200000 |
219 | #define bit_MWAITX0x20000000 0x20000000 |
220 | |
221 | /* Features in %edx for leaf 0x80000001 */ |
222 | #define bit_MMXEXT0x00400000 0x00400000 |
223 | #define bit_LM0x20000000 0x20000000 |
224 | #define bit_3DNOWP0x40000000 0x40000000 |
225 | #define bit_3DNOW0x80000000 0x80000000 |
226 | |
227 | /* Features in %ebx for leaf 0x80000008 */ |
228 | #define bit_CLZERO0x00000001 0x00000001 |
229 | #define bit_WBNOINVD0x00000200 0x00000200 |
230 | |
231 | |
232 | #if __i386__ |
233 | #define __cpuid(__leaf, __eax, __ebx, __ecx, __edx)__asm(" xchgq %%rbx,%q1\n" " cpuid\n" " xchgq %%rbx,%q1" : "=a"(__eax), "=r" (__ebx), "=c"(__ecx), "=d"(__edx) : "0"( __leaf)) \ |
234 | __asm("cpuid" : "=a"(__eax), "=b" (__ebx), "=c"(__ecx), "=d"(__edx) \ |
235 | : "0"(__leaf)) |
236 | |
237 | #define __cpuid_count(__leaf, __count, __eax, __ebx, __ecx, __edx)__asm(" xchgq %%rbx,%q1\n" " cpuid\n" " xchgq %%rbx,%q1" : "=a"(__eax), "=r" (__ebx), "=c"(__ecx), "=d"(__edx) : "0"( __leaf), "2"(__count)) \ |
238 | __asm("cpuid" : "=a"(__eax), "=b" (__ebx), "=c"(__ecx), "=d"(__edx) \ |
239 | : "0"(__leaf), "2"(__count)) |
240 | #else |
241 | /* x86-64 uses %rbx as the base register, so preserve it. */ |
242 | #define __cpuid(__leaf, __eax, __ebx, __ecx, __edx)__asm(" xchgq %%rbx,%q1\n" " cpuid\n" " xchgq %%rbx,%q1" : "=a"(__eax), "=r" (__ebx), "=c"(__ecx), "=d"(__edx) : "0"( __leaf)) \ |
243 | __asm(" xchgq %%rbx,%q1\n" \ |
244 | " cpuid\n" \ |
245 | " xchgq %%rbx,%q1" \ |
246 | : "=a"(__eax), "=r" (__ebx), "=c"(__ecx), "=d"(__edx) \ |
247 | : "0"(__leaf)) |
248 | |
249 | #define __cpuid_count(__leaf, __count, __eax, __ebx, __ecx, __edx)__asm(" xchgq %%rbx,%q1\n" " cpuid\n" " xchgq %%rbx,%q1" : "=a"(__eax), "=r" (__ebx), "=c"(__ecx), "=d"(__edx) : "0"( __leaf), "2"(__count)) \ |
250 | __asm(" xchgq %%rbx,%q1\n" \ |
251 | " cpuid\n" \ |
252 | " xchgq %%rbx,%q1" \ |
253 | : "=a"(__eax), "=r" (__ebx), "=c"(__ecx), "=d"(__edx) \ |
254 | : "0"(__leaf), "2"(__count)) |
255 | #endif |
256 | |
257 | static __inline int __get_cpuid_max (unsigned int __leaf, unsigned int *__sig) |
258 | { |
259 | unsigned int __eax, __ebx, __ecx, __edx; |
260 | #if __i386__ |
261 | int __cpuid_supported; |
262 | |
263 | __asm(" pushfl\n" |
264 | " popl %%eax\n" |
265 | " movl %%eax,%%ecx\n" |
266 | " xorl $0x00200000,%%eax\n" |
267 | " pushl %%eax\n" |
268 | " popfl\n" |
269 | " pushfl\n" |
270 | " popl %%eax\n" |
271 | " movl $0,%0\n" |
272 | " cmpl %%eax,%%ecx\n" |
273 | " je 1f\n" |
274 | " movl $1,%0\n" |
275 | "1:" |
276 | : "=r" (__cpuid_supported) : : "eax", "ecx"); |
277 | if (!__cpuid_supported) |
278 | return 0; |
279 | #endif |
280 | |
281 | __cpuid(__leaf, __eax, __ebx, __ecx, __edx)__asm(" xchgq %%rbx,%q1\n" " cpuid\n" " xchgq %%rbx,%q1" : "=a"(__eax), "=r" (__ebx), "=c"(__ecx), "=d"(__edx) : "0"( __leaf)); |
282 | if (__sig) |
283 | *__sig = __ebx; |
284 | return __eax; |
285 | } |
286 | |
287 | static __inline int __get_cpuid (unsigned int __leaf, unsigned int *__eax, |
288 | unsigned int *__ebx, unsigned int *__ecx, |
289 | unsigned int *__edx) |
290 | { |
291 | unsigned int __max_leaf = __get_cpuid_max(__leaf & 0x80000000, 0); |
292 | |
293 | if (__max_leaf == 0 || __max_leaf < __leaf) |
294 | return 0; |
295 | |
296 | __cpuid(__leaf, *__eax, *__ebx, *__ecx, *__edx)__asm(" xchgq %%rbx,%q1\n" " cpuid\n" " xchgq %%rbx,%q1" : "=a"(*__eax), "=r" (*__ebx), "=c"(*__ecx), "=d"(*__edx) : "0" (__leaf)); |
297 | return 1; |
298 | } |
299 | |
300 | static __inline int __get_cpuid_count (unsigned int __leaf, |
301 | unsigned int __subleaf, |
302 | unsigned int *__eax, unsigned int *__ebx, |
303 | unsigned int *__ecx, unsigned int *__edx) |
304 | { |
305 | unsigned int __max_leaf = __get_cpuid_max(__leaf & 0x80000000, 0); |
306 | |
307 | if (__max_leaf == 0 || __max_leaf < __leaf) |
308 | return 0; |
309 | |
310 | __cpuid_count(__leaf, __subleaf, *__eax, *__ebx, *__ecx, *__edx)__asm(" xchgq %%rbx,%q1\n" " cpuid\n" " xchgq %%rbx,%q1" : "=a"(*__eax), "=r" (*__ebx), "=c"(*__ecx), "=d"(*__edx) : "0" (__leaf), "2"(__subleaf)); |
311 | return 1; |
312 | } |