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Memory Mapped I/O Intrinsics do not fence memory #938

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llvmbot opened this issue May 18, 2005 · 1 comment
Closed

Memory Mapped I/O Intrinsics do not fence memory #938

llvmbot opened this issue May 18, 2005 · 1 comment
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backend:X86 bugzilla Issues migrated from bugzilla wontfix Issue is real, but we can't or won't fix it. Not invalid

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@llvmbot
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llvmbot commented May 18, 2005

Bugzilla Link 566
Resolution WONTFIX
Resolved on Mar 06, 2010 14:00
Version 1.5
OS Linux
Reporter LLVM Bugzilla Contributor

Extended Description

According to the design in the language reference manual, the LLVM readio and
writeio intrinsics should strongly order I/O memory accesses.

However, the current implementation lowers these intrinsics to volatile loads
and stores on ix86. These loads and stores may or may not be properly ordered,
depending on the processor on which they run.

The correct solution is not obvious. Certain fencing instructions are not found
on older Pentium processors, and we will need a general fencing model for SMP
systems anyway. Such a design has not been discussed, though, as far as I know.
@lattner
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lattner commented Mar 3, 2006

This bug is obsolete.

@llvmbot llvmbot transferred this issue from llvm/llvm-bugzilla-archive Dec 3, 2021
@Quuxplusone Quuxplusone added the wontfix Issue is real, but we can't or won't fix it. Not invalid label Jan 20, 2022
trevor-m pushed a commit to trevor-m/llvm-project that referenced this issue Apr 20, 2023
@lattner
enhance llvm-mc -show-inst to print the enum of an instruction, like so:
b1913c4 
	testb	%al, %al                ## <MCInst llvm#2412 TEST8rr
                                        ##   <MCOperand Reg:2>
                                        ##   <MCOperand Reg:2>>
	jne	LBB1_7                  ## <MCInst llvm#938 JNE_1
                                        ##   <MCOperand Expr:(LBB1_7)>>

llvm-svn: 95935
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backend:X86 bugzilla Issues migrated from bugzilla wontfix Issue is real, but we can't or won't fix it. Not invalid
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@Quuxplusone @lattner @llvmbot