LLVM  mainline
InlineAsm.h
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00001 //===-- llvm/InlineAsm.h - Class to represent inline asm strings-*- C++ -*-===//
00002 //
00003 //                     The LLVM Compiler Infrastructure
00004 //
00005 // This file is distributed under the University of Illinois Open Source
00006 // License. See LICENSE.TXT for details.
00007 //
00008 //===----------------------------------------------------------------------===//
00009 //
00010 // This class represents the inline asm strings, which are Value*'s that are
00011 // used as the callee operand of call instructions.  InlineAsm's are uniqued
00012 // like constants, and created via InlineAsm::get(...).
00013 //
00014 //===----------------------------------------------------------------------===//
00015 
00016 #ifndef LLVM_IR_INLINEASM_H
00017 #define LLVM_IR_INLINEASM_H
00018 
00019 #include "llvm/ADT/StringRef.h"
00020 #include "llvm/IR/Value.h"
00021 #include <vector>
00022 
00023 namespace llvm {
00024 
00025 class PointerType;
00026 class FunctionType;
00027 class Module;
00028 
00029 struct InlineAsmKeyType;
00030 template <class ConstantClass> class ConstantUniqueMap;
00031 
00032 class InlineAsm : public Value {
00033 public:
00034   enum AsmDialect {
00035     AD_ATT,
00036     AD_Intel
00037   };
00038 
00039 private:
00040   friend struct InlineAsmKeyType;
00041   friend class ConstantUniqueMap<InlineAsm>;
00042 
00043   InlineAsm(const InlineAsm &) = delete;
00044   void operator=(const InlineAsm&) = delete;
00045 
00046   std::string AsmString, Constraints;
00047   bool HasSideEffects;
00048   bool IsAlignStack;
00049   AsmDialect Dialect;
00050 
00051   InlineAsm(PointerType *Ty, const std::string &AsmString,
00052             const std::string &Constraints, bool hasSideEffects,
00053             bool isAlignStack, AsmDialect asmDialect);
00054   ~InlineAsm() override;
00055 
00056   /// When the ConstantUniqueMap merges two types and makes two InlineAsms
00057   /// identical, it destroys one of them with this method.
00058   void destroyConstant();
00059 public:
00060 
00061   /// InlineAsm::get - Return the specified uniqued inline asm string.
00062   ///
00063   static InlineAsm *get(FunctionType *Ty, StringRef AsmString,
00064                         StringRef Constraints, bool hasSideEffects,
00065                         bool isAlignStack = false,
00066                         AsmDialect asmDialect = AD_ATT);
00067   
00068   bool hasSideEffects() const { return HasSideEffects; }
00069   bool isAlignStack() const { return IsAlignStack; }
00070   AsmDialect getDialect() const { return Dialect; }
00071 
00072   /// getType - InlineAsm's are always pointers.
00073   ///
00074   PointerType *getType() const {
00075     return reinterpret_cast<PointerType*>(Value::getType());
00076   }
00077   
00078   /// getFunctionType - InlineAsm's are always pointers to functions.
00079   ///
00080   FunctionType *getFunctionType() const;
00081   
00082   const std::string &getAsmString() const { return AsmString; }
00083   const std::string &getConstraintString() const { return Constraints; }
00084 
00085   /// Verify - This static method can be used by the parser to check to see if
00086   /// the specified constraint string is legal for the type.  This returns true
00087   /// if legal, false if not.
00088   ///
00089   static bool Verify(FunctionType *Ty, StringRef Constraints);
00090 
00091   // Constraint String Parsing 
00092   enum ConstraintPrefix {
00093     isInput,            // 'x'
00094     isOutput,           // '=x'
00095     isClobber           // '~x'
00096   };
00097   
00098   typedef std::vector<std::string> ConstraintCodeVector;
00099   
00100   struct SubConstraintInfo {
00101     /// MatchingInput - If this is not -1, this is an output constraint where an
00102     /// input constraint is required to match it (e.g. "0").  The value is the
00103     /// constraint number that matches this one (for example, if this is
00104     /// constraint #0 and constraint #4 has the value "0", this will be 4).
00105     signed char MatchingInput;
00106     /// Code - The constraint code, either the register name (in braces) or the
00107     /// constraint letter/number.
00108     ConstraintCodeVector Codes;
00109     /// Default constructor.
00110     SubConstraintInfo() : MatchingInput(-1) {}
00111   };
00112 
00113   typedef std::vector<SubConstraintInfo> SubConstraintInfoVector;
00114   struct ConstraintInfo;
00115   typedef std::vector<ConstraintInfo> ConstraintInfoVector;
00116   
00117   struct ConstraintInfo {
00118     /// Type - The basic type of the constraint: input/output/clobber
00119     ///
00120     ConstraintPrefix Type;
00121     
00122     /// isEarlyClobber - "&": output operand writes result before inputs are all
00123     /// read.  This is only ever set for an output operand.
00124     bool isEarlyClobber; 
00125     
00126     /// MatchingInput - If this is not -1, this is an output constraint where an
00127     /// input constraint is required to match it (e.g. "0").  The value is the
00128     /// constraint number that matches this one (for example, if this is
00129     /// constraint #0 and constraint #4 has the value "0", this will be 4).
00130     signed char MatchingInput;
00131     
00132     /// hasMatchingInput - Return true if this is an output constraint that has
00133     /// a matching input constraint.
00134     bool hasMatchingInput() const { return MatchingInput != -1; }
00135     
00136     /// isCommutative - This is set to true for a constraint that is commutative
00137     /// with the next operand.
00138     bool isCommutative;
00139     
00140     /// isIndirect - True if this operand is an indirect operand.  This means
00141     /// that the address of the source or destination is present in the call
00142     /// instruction, instead of it being returned or passed in explicitly.  This
00143     /// is represented with a '*' in the asm string.
00144     bool isIndirect;
00145     
00146     /// Code - The constraint code, either the register name (in braces) or the
00147     /// constraint letter/number.
00148     ConstraintCodeVector Codes;
00149     
00150     /// isMultipleAlternative - '|': has multiple-alternative constraints.
00151     bool isMultipleAlternative;
00152     
00153     /// multipleAlternatives - If there are multiple alternative constraints,
00154     /// this array will contain them.  Otherwise it will be empty.
00155     SubConstraintInfoVector multipleAlternatives;
00156     
00157     /// The currently selected alternative constraint index.
00158     unsigned currentAlternativeIndex;
00159     
00160     ///Default constructor.
00161     ConstraintInfo();
00162     
00163     /// Parse - Analyze the specified string (e.g. "=*&{eax}") and fill in the
00164     /// fields in this structure.  If the constraint string is not understood,
00165     /// return true, otherwise return false.
00166     bool Parse(StringRef Str, ConstraintInfoVector &ConstraintsSoFar);
00167                
00168     /// selectAlternative - Point this constraint to the alternative constraint
00169     /// indicated by the index.
00170     void selectAlternative(unsigned index);
00171   };
00172   
00173   /// ParseConstraints - Split up the constraint string into the specific
00174   /// constraints and their prefixes.  If this returns an empty vector, and if
00175   /// the constraint string itself isn't empty, there was an error parsing.
00176   static ConstraintInfoVector ParseConstraints(StringRef ConstraintString);
00177   
00178   /// ParseConstraints - Parse the constraints of this inlineasm object, 
00179   /// returning them the same way that ParseConstraints(str) does.
00180   ConstraintInfoVector ParseConstraints() const {
00181     return ParseConstraints(Constraints);
00182   }
00183   
00184   // Methods for support type inquiry through isa, cast, and dyn_cast:
00185   static inline bool classof(const Value *V) {
00186     return V->getValueID() == Value::InlineAsmVal;
00187   }
00188 
00189   
00190   // These are helper methods for dealing with flags in the INLINEASM SDNode
00191   // in the backend.
00192   //
00193   // The encoding of the flag word is currently:
00194   //   Bits 2-0 - A Kind_* value indicating the kind of the operand.
00195   //   Bits 15-3 - The number of SDNode operands associated with this inline
00196   //               assembly operand.
00197   //   If bit 31 is set:
00198   //     Bit 30-16 - The operand number that this operand must match.
00199   //                 When bits 2-0 are Kind_Mem, the Constraint_* value must be
00200   //                 obtained from the flags for this operand number.
00201   //   Else if bits 2-0 are Kind_Mem:
00202   //     Bit 30-16 - A Constraint_* value indicating the original constraint
00203   //                 code.
00204   //   Else:
00205   //     Bit 30-16 - The register class ID to use for the operand.
00206   
00207   enum : uint32_t {
00208     // Fixed operands on an INLINEASM SDNode.
00209     Op_InputChain = 0,
00210     Op_AsmString = 1,
00211     Op_MDNode = 2,
00212     Op_ExtraInfo = 3,    // HasSideEffects, IsAlignStack, AsmDialect.
00213     Op_FirstOperand = 4,
00214 
00215     // Fixed operands on an INLINEASM MachineInstr.
00216     MIOp_AsmString = 0,
00217     MIOp_ExtraInfo = 1,    // HasSideEffects, IsAlignStack, AsmDialect.
00218     MIOp_FirstOperand = 2,
00219 
00220     // Interpretation of the MIOp_ExtraInfo bit field.
00221     Extra_HasSideEffects = 1,
00222     Extra_IsAlignStack = 2,
00223     Extra_AsmDialect = 4,
00224     Extra_MayLoad = 8,
00225     Extra_MayStore = 16,
00226 
00227     // Inline asm operands map to multiple SDNode / MachineInstr operands.
00228     // The first operand is an immediate describing the asm operand, the low
00229     // bits is the kind:
00230     Kind_RegUse = 1,             // Input register, "r".
00231     Kind_RegDef = 2,             // Output register, "=r".
00232     Kind_RegDefEarlyClobber = 3, // Early-clobber output register, "=&r".
00233     Kind_Clobber = 4,            // Clobbered register, "~r".
00234     Kind_Imm = 5,                // Immediate.
00235     Kind_Mem = 6,                // Memory operand, "m".
00236 
00237     // Memory constraint codes.
00238     // These could be tablegenerated but there's little need to do that since
00239     // there's plenty of space in the encoding to support the union of all
00240     // constraint codes for all targets.
00241     Constraint_Unknown = 0,
00242     Constraint_es,
00243     Constraint_i,
00244     Constraint_m,
00245     Constraint_o,
00246     Constraint_v,
00247     Constraint_Q,
00248     Constraint_R,
00249     Constraint_S,
00250     Constraint_T,
00251     Constraint_Um,
00252     Constraint_Un,
00253     Constraint_Uq,
00254     Constraint_Us,
00255     Constraint_Ut,
00256     Constraint_Uv,
00257     Constraint_Uy,
00258     Constraint_X,
00259     Constraint_Z,
00260     Constraint_ZC,
00261     Constraint_Zy,
00262     Constraints_Max = Constraint_Zy,
00263     Constraints_ShiftAmount = 16,
00264 
00265     Flag_MatchingOperand = 0x80000000
00266   };
00267   
00268   static unsigned getFlagWord(unsigned Kind, unsigned NumOps) {
00269     assert(((NumOps << 3) & ~0xffff) == 0 && "Too many inline asm operands!");
00270     assert(Kind >= Kind_RegUse && Kind <= Kind_Mem && "Invalid Kind");
00271     return Kind | (NumOps << 3);
00272   }
00273   
00274   /// getFlagWordForMatchingOp - Augment an existing flag word returned by
00275   /// getFlagWord with information indicating that this input operand is tied 
00276   /// to a previous output operand.
00277   static unsigned getFlagWordForMatchingOp(unsigned InputFlag,
00278                                            unsigned MatchedOperandNo) {
00279     assert(MatchedOperandNo <= 0x7fff && "Too big matched operand");
00280     assert((InputFlag & ~0xffff) == 0 && "High bits already contain data");
00281     return InputFlag | Flag_MatchingOperand | (MatchedOperandNo << 16);
00282   }
00283 
00284   /// getFlagWordForRegClass - Augment an existing flag word returned by
00285   /// getFlagWord with the required register class for the following register
00286   /// operands.
00287   /// A tied use operand cannot have a register class, use the register class
00288   /// from the def operand instead.
00289   static unsigned getFlagWordForRegClass(unsigned InputFlag, unsigned RC) {
00290     // Store RC + 1, reserve the value 0 to mean 'no register class'.
00291     ++RC;
00292     assert(RC <= 0x7fff && "Too large register class ID");
00293     assert((InputFlag & ~0xffff) == 0 && "High bits already contain data");
00294     return InputFlag | (RC << 16);
00295   }
00296 
00297   /// Augment an existing flag word returned by getFlagWord with the constraint
00298   /// code for a memory constraint.
00299   static unsigned getFlagWordForMem(unsigned InputFlag, unsigned Constraint) {
00300     assert(Constraint <= 0x7fff && "Too large a memory constraint ID");
00301     assert(Constraint <= Constraints_Max && "Unknown constraint ID");
00302     assert((InputFlag & ~0xffff) == 0 && "High bits already contain data");
00303     return InputFlag | (Constraint << Constraints_ShiftAmount);
00304   }
00305 
00306   static unsigned convertMemFlagWordToMatchingFlagWord(unsigned InputFlag) {
00307     assert(isMemKind(InputFlag));
00308     return InputFlag & ~(0x7fff << Constraints_ShiftAmount);
00309   }
00310 
00311   static unsigned getKind(unsigned Flags) {
00312     return Flags & 7;
00313   }
00314 
00315   static bool isRegDefKind(unsigned Flag){ return getKind(Flag) == Kind_RegDef;}
00316   static bool isImmKind(unsigned Flag) { return getKind(Flag) == Kind_Imm; }
00317   static bool isMemKind(unsigned Flag) { return getKind(Flag) == Kind_Mem; }
00318   static bool isRegDefEarlyClobberKind(unsigned Flag) {
00319     return getKind(Flag) == Kind_RegDefEarlyClobber;
00320   }
00321   static bool isClobberKind(unsigned Flag) {
00322     return getKind(Flag) == Kind_Clobber;
00323   }
00324 
00325   static unsigned getMemoryConstraintID(unsigned Flag) {
00326     assert(isMemKind(Flag));
00327     return (Flag >> Constraints_ShiftAmount) & 0x7fff;
00328   }
00329 
00330   /// getNumOperandRegisters - Extract the number of registers field from the
00331   /// inline asm operand flag.
00332   static unsigned getNumOperandRegisters(unsigned Flag) {
00333     return (Flag & 0xffff) >> 3;
00334   }
00335 
00336   /// isUseOperandTiedToDef - Return true if the flag of the inline asm
00337   /// operand indicates it is an use operand that's matched to a def operand.
00338   static bool isUseOperandTiedToDef(unsigned Flag, unsigned &Idx) {
00339     if ((Flag & Flag_MatchingOperand) == 0)
00340       return false;
00341     Idx = (Flag & ~Flag_MatchingOperand) >> 16;
00342     return true;
00343   }
00344 
00345   /// hasRegClassConstraint - Returns true if the flag contains a register
00346   /// class constraint.  Sets RC to the register class ID.
00347   static bool hasRegClassConstraint(unsigned Flag, unsigned &RC) {
00348     if (Flag & Flag_MatchingOperand)
00349       return false;
00350     unsigned High = Flag >> 16;
00351     // getFlagWordForRegClass() uses 0 to mean no register class, and otherwise
00352     // stores RC + 1.
00353     if (!High)
00354       return false;
00355     RC = High - 1;
00356     return true;
00357   }
00358 
00359 };
00360 
00361 } // End llvm namespace
00362 
00363 #endif