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MCSubtargetInfo.h
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00001 //==-- llvm/MC/MCSubtargetInfo.h - Subtarget Information ---------*- C++ -*-==//
00002 //
00003 //                     The LLVM Compiler Infrastructure
00004 //
00005 // This file is distributed under the University of Illinois Open Source
00006 // License. See LICENSE.TXT for details.
00007 //
00008 //===----------------------------------------------------------------------===//
00009 //
00010 // This file describes the subtarget options of a Target machine.
00011 //
00012 //===----------------------------------------------------------------------===//
00013 
00014 #ifndef LLVM_MC_MCSUBTARGETINFO_H
00015 #define LLVM_MC_MCSUBTARGETINFO_H
00016 
00017 #include "llvm/MC/MCInstrItineraries.h"
00018 #include "llvm/MC/SubtargetFeature.h"
00019 #include <string>
00020 
00021 namespace llvm {
00022 
00023 class StringRef;
00024 
00025 //===----------------------------------------------------------------------===//
00026 ///
00027 /// MCSubtargetInfo - Generic base class for all target subtargets.
00028 ///
00029 class MCSubtargetInfo {
00030   Triple TargetTriple;                        // Target triple
00031   std::string CPU; // CPU being targeted.
00032   ArrayRef<SubtargetFeatureKV> ProcFeatures;  // Processor feature list
00033   ArrayRef<SubtargetFeatureKV> ProcDesc;  // Processor descriptions
00034 
00035   // Scheduler machine model
00036   const SubtargetInfoKV *ProcSchedModels;
00037   const MCWriteProcResEntry *WriteProcResTable;
00038   const MCWriteLatencyEntry *WriteLatencyTable;
00039   const MCReadAdvanceEntry *ReadAdvanceTable;
00040   MCSchedModel CPUSchedModel;
00041 
00042   const InstrStage *Stages;            // Instruction itinerary stages
00043   const unsigned *OperandCycles;       // Itinerary operand cycles
00044   const unsigned *ForwardingPaths;     // Forwarding paths
00045   FeatureBitset FeatureBits;           // Feature bits for current CPU + FS
00046 
00047 public:
00048   void InitMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS,
00049                            ArrayRef<SubtargetFeatureKV> PF,
00050                            ArrayRef<SubtargetFeatureKV> PD,
00051                            const SubtargetInfoKV *ProcSched,
00052                            const MCWriteProcResEntry *WPR,
00053                            const MCWriteLatencyEntry *WL,
00054                            const MCReadAdvanceEntry *RA, const InstrStage *IS,
00055                            const unsigned *OC, const unsigned *FP);
00056 
00057   /// getTargetTriple - Return the target triple string.
00058   const Triple &getTargetTriple() const { return TargetTriple; }
00059 
00060   /// getCPU - Return the CPU string.
00061   StringRef getCPU() const {
00062     return CPU;
00063   }
00064 
00065   /// getFeatureBits - Return the feature bits.
00066   ///
00067   const FeatureBitset& getFeatureBits() const {
00068     return FeatureBits;
00069   }
00070 
00071   /// setFeatureBits - Set the feature bits.
00072   ///
00073   void setFeatureBits(const FeatureBitset &FeatureBits_) {
00074     FeatureBits = FeatureBits_;
00075   }
00076 
00077   /// InitMCProcessorInfo - Set or change the CPU (optionally supplemented with
00078   /// feature string). Recompute feature bits and scheduling model.
00079   void InitMCProcessorInfo(StringRef CPU, StringRef FS);
00080 
00081   /// InitCPUSchedModel - Recompute scheduling model based on CPU.
00082   void InitCPUSchedModel(StringRef CPU);
00083 
00084   /// ToggleFeature - Toggle a feature and returns the re-computed feature
00085   /// bits. This version does not change the implied bits.
00086   FeatureBitset ToggleFeature(uint64_t FB);
00087 
00088   /// ToggleFeature - Toggle a feature and returns the re-computed feature
00089   /// bits. This version does not change the implied bits.
00090   FeatureBitset ToggleFeature(const FeatureBitset& FB);
00091 
00092   /// ToggleFeature - Toggle a set of features and returns the re-computed
00093   /// feature bits. This version will also change all implied bits.
00094   FeatureBitset ToggleFeature(StringRef FS);
00095 
00096   /// Apply a feature flag and return the re-computed feature bits, including
00097   /// all feature bits implied by the flag.
00098   FeatureBitset ApplyFeatureFlag(StringRef FS);
00099 
00100   /// getSchedModelForCPU - Get the machine model of a CPU.
00101   ///
00102   MCSchedModel getSchedModelForCPU(StringRef CPU) const;
00103 
00104   /// getSchedModel - Get the machine model for this subtarget's CPU.
00105   ///
00106   const MCSchedModel &getSchedModel() const { return CPUSchedModel; }
00107 
00108   /// Return an iterator at the first process resource consumed by the given
00109   /// scheduling class.
00110   const MCWriteProcResEntry *getWriteProcResBegin(
00111     const MCSchedClassDesc *SC) const {
00112     return &WriteProcResTable[SC->WriteProcResIdx];
00113   }
00114   const MCWriteProcResEntry *getWriteProcResEnd(
00115     const MCSchedClassDesc *SC) const {
00116     return getWriteProcResBegin(SC) + SC->NumWriteProcResEntries;
00117   }
00118 
00119   const MCWriteLatencyEntry *getWriteLatencyEntry(const MCSchedClassDesc *SC,
00120                                                   unsigned DefIdx) const {
00121     assert(DefIdx < SC->NumWriteLatencyEntries &&
00122            "MachineModel does not specify a WriteResource for DefIdx");
00123 
00124     return &WriteLatencyTable[SC->WriteLatencyIdx + DefIdx];
00125   }
00126 
00127   int getReadAdvanceCycles(const MCSchedClassDesc *SC, unsigned UseIdx,
00128                            unsigned WriteResID) const {
00129     // TODO: The number of read advance entries in a class can be significant
00130     // (~50). Consider compressing the WriteID into a dense ID of those that are
00131     // used by ReadAdvance and representing them as a bitset.
00132     for (const MCReadAdvanceEntry *I = &ReadAdvanceTable[SC->ReadAdvanceIdx],
00133            *E = I + SC->NumReadAdvanceEntries; I != E; ++I) {
00134       if (I->UseIdx < UseIdx)
00135         continue;
00136       if (I->UseIdx > UseIdx)
00137         break;
00138       // Find the first WriteResIdx match, which has the highest cycle count.
00139       if (!I->WriteResourceID || I->WriteResourceID == WriteResID) {
00140         return I->Cycles;
00141       }
00142     }
00143     return 0;
00144   }
00145 
00146   /// getInstrItineraryForCPU - Get scheduling itinerary of a CPU.
00147   ///
00148   InstrItineraryData getInstrItineraryForCPU(StringRef CPU) const;
00149 
00150   /// Initialize an InstrItineraryData instance.
00151   void initInstrItins(InstrItineraryData &InstrItins) const;
00152 
00153   /// Check whether the CPU string is valid.
00154   bool isCPUStringValid(StringRef CPU) {
00155     auto Found = std::find_if(ProcDesc.begin(), ProcDesc.end(),
00156                               [=](const SubtargetFeatureKV &KV) {
00157                                 return CPU == KV.Key; 
00158                               });
00159     return Found != ProcDesc.end();
00160   }
00161 };
00162 
00163 } // End llvm namespace
00164 
00165 #endif