LLVM API Documentation

MCSubtargetInfo.h
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00001 //==-- llvm/MC/MCSubtargetInfo.h - Subtarget Information ---------*- C++ -*-==//
00002 //
00003 //                     The LLVM Compiler Infrastructure
00004 //
00005 // This file is distributed under the University of Illinois Open Source
00006 // License. See LICENSE.TXT for details.
00007 //
00008 //===----------------------------------------------------------------------===//
00009 //
00010 // This file describes the subtarget options of a Target machine.
00011 //
00012 //===----------------------------------------------------------------------===//
00013 
00014 #ifndef LLVM_MC_MCSUBTARGET_H
00015 #define LLVM_MC_MCSUBTARGET_H
00016 
00017 #include "llvm/MC/MCInstrItineraries.h"
00018 #include "llvm/MC/SubtargetFeature.h"
00019 #include <string>
00020 
00021 namespace llvm {
00022 
00023 class StringRef;
00024 
00025 //===----------------------------------------------------------------------===//
00026 ///
00027 /// MCSubtargetInfo - Generic base class for all target subtargets.
00028 ///
00029 class MCSubtargetInfo {
00030   std::string TargetTriple;            // Target triple
00031   const SubtargetFeatureKV *ProcFeatures;  // Processor feature list
00032   const SubtargetFeatureKV *ProcDesc;  // Processor descriptions
00033 
00034   // Scheduler machine model
00035   const SubtargetInfoKV *ProcSchedModels;
00036   const MCWriteProcResEntry *WriteProcResTable;
00037   const MCWriteLatencyEntry *WriteLatencyTable;
00038   const MCReadAdvanceEntry *ReadAdvanceTable;
00039   const MCSchedModel *CPUSchedModel;
00040 
00041   const InstrStage *Stages;            // Instruction itinerary stages
00042   const unsigned *OperandCycles;       // Itinerary operand cycles
00043   const unsigned *ForwardingPaths;     // Forwarding paths
00044   unsigned NumFeatures;                // Number of processor features
00045   unsigned NumProcs;                   // Number of processors
00046   uint64_t FeatureBits;                // Feature bits for current CPU + FS
00047 
00048 public:
00049   void InitMCSubtargetInfo(StringRef TT, StringRef CPU, StringRef FS,
00050                            const SubtargetFeatureKV *PF,
00051                            const SubtargetFeatureKV *PD,
00052                            const SubtargetInfoKV *ProcSched,
00053                            const MCWriteProcResEntry *WPR,
00054                            const MCWriteLatencyEntry *WL,
00055                            const MCReadAdvanceEntry *RA,
00056                            const InstrStage *IS,
00057                            const unsigned *OC, const unsigned *FP,
00058                            unsigned NF, unsigned NP);
00059 
00060   /// getTargetTriple - Return the target triple string.
00061   StringRef getTargetTriple() const {
00062     return TargetTriple;
00063   }
00064 
00065   /// getFeatureBits - Return the feature bits.
00066   ///
00067   uint64_t getFeatureBits() const {
00068     return FeatureBits;
00069   }
00070 
00071   /// InitMCProcessorInfo - Set or change the CPU (optionally supplemented with
00072   /// feature string). Recompute feature bits and scheduling model.
00073   void InitMCProcessorInfo(StringRef CPU, StringRef FS);
00074 
00075   /// InitCPUSchedModel - Recompute scheduling model based on CPU.
00076   void InitCPUSchedModel(StringRef CPU);
00077 
00078   /// ToggleFeature - Toggle a feature and returns the re-computed feature
00079   /// bits. This version does not change the implied bits.
00080   uint64_t ToggleFeature(uint64_t FB);
00081 
00082   /// ToggleFeature - Toggle a feature and returns the re-computed feature
00083   /// bits. This version will also change all implied bits.
00084   uint64_t ToggleFeature(StringRef FS);
00085 
00086   /// getSchedModelForCPU - Get the machine model of a CPU.
00087   ///
00088   const MCSchedModel *getSchedModelForCPU(StringRef CPU) const;
00089 
00090   /// getSchedModel - Get the machine model for this subtarget's CPU.
00091   ///
00092   const MCSchedModel *getSchedModel() const { return CPUSchedModel; }
00093 
00094   /// Return an iterator at the first process resource consumed by the given
00095   /// scheduling class.
00096   const MCWriteProcResEntry *getWriteProcResBegin(
00097     const MCSchedClassDesc *SC) const {
00098     return &WriteProcResTable[SC->WriteProcResIdx];
00099   }
00100   const MCWriteProcResEntry *getWriteProcResEnd(
00101     const MCSchedClassDesc *SC) const {
00102     return getWriteProcResBegin(SC) + SC->NumWriteProcResEntries;
00103   }
00104 
00105   const MCWriteLatencyEntry *getWriteLatencyEntry(const MCSchedClassDesc *SC,
00106                                                   unsigned DefIdx) const {
00107     assert(DefIdx < SC->NumWriteLatencyEntries &&
00108            "MachineModel does not specify a WriteResource for DefIdx");
00109 
00110     return &WriteLatencyTable[SC->WriteLatencyIdx + DefIdx];
00111   }
00112 
00113   int getReadAdvanceCycles(const MCSchedClassDesc *SC, unsigned UseIdx,
00114                            unsigned WriteResID) const {
00115     // TODO: The number of read advance entries in a class can be significant
00116     // (~50). Consider compressing the WriteID into a dense ID of those that are
00117     // used by ReadAdvance and representing them as a bitset.
00118     for (const MCReadAdvanceEntry *I = &ReadAdvanceTable[SC->ReadAdvanceIdx],
00119            *E = I + SC->NumReadAdvanceEntries; I != E; ++I) {
00120       if (I->UseIdx < UseIdx)
00121         continue;
00122       if (I->UseIdx > UseIdx)
00123         break;
00124       // Find the first WriteResIdx match, which has the highest cycle count.
00125       if (!I->WriteResourceID || I->WriteResourceID == WriteResID) {
00126         return I->Cycles;
00127       }
00128     }
00129     return 0;
00130   }
00131 
00132   /// getInstrItineraryForCPU - Get scheduling itinerary of a CPU.
00133   ///
00134   InstrItineraryData getInstrItineraryForCPU(StringRef CPU) const;
00135 
00136   /// Initialize an InstrItineraryData instance.
00137   void initInstrItins(InstrItineraryData &InstrItins) const;
00138 };
00139 
00140 } // End llvm namespace
00141 
00142 #endif