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MCSubtargetInfo.h
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00001 //==-- llvm/MC/MCSubtargetInfo.h - Subtarget Information ---------*- C++ -*-==//
00002 //
00003 //                     The LLVM Compiler Infrastructure
00004 //
00005 // This file is distributed under the University of Illinois Open Source
00006 // License. See LICENSE.TXT for details.
00007 //
00008 //===----------------------------------------------------------------------===//
00009 //
00010 // This file describes the subtarget options of a Target machine.
00011 //
00012 //===----------------------------------------------------------------------===//
00013 
00014 #ifndef LLVM_MC_MCSUBTARGETINFO_H
00015 #define LLVM_MC_MCSUBTARGETINFO_H
00016 
00017 #include "llvm/MC/MCInstrItineraries.h"
00018 #include "llvm/MC/SubtargetFeature.h"
00019 #include <string>
00020 
00021 namespace llvm {
00022 
00023 class StringRef;
00024 
00025 //===----------------------------------------------------------------------===//
00026 ///
00027 /// MCSubtargetInfo - Generic base class for all target subtargets.
00028 ///
00029 class MCSubtargetInfo {
00030   std::string TargetTriple;            // Target triple
00031   std::string CPU; // CPU being targeted.
00032   ArrayRef<SubtargetFeatureKV> ProcFeatures;  // Processor feature list
00033   ArrayRef<SubtargetFeatureKV> ProcDesc;  // Processor descriptions
00034 
00035   // Scheduler machine model
00036   const SubtargetInfoKV *ProcSchedModels;
00037   const MCWriteProcResEntry *WriteProcResTable;
00038   const MCWriteLatencyEntry *WriteLatencyTable;
00039   const MCReadAdvanceEntry *ReadAdvanceTable;
00040   MCSchedModel CPUSchedModel;
00041 
00042   const InstrStage *Stages;            // Instruction itinerary stages
00043   const unsigned *OperandCycles;       // Itinerary operand cycles
00044   const unsigned *ForwardingPaths;     // Forwarding paths
00045   uint64_t FeatureBits;                // Feature bits for current CPU + FS
00046 
00047 public:
00048   void InitMCSubtargetInfo(StringRef TT, StringRef CPU, StringRef FS,
00049                            ArrayRef<SubtargetFeatureKV> PF,
00050                            ArrayRef<SubtargetFeatureKV> PD,
00051                            const SubtargetInfoKV *ProcSched,
00052                            const MCWriteProcResEntry *WPR,
00053                            const MCWriteLatencyEntry *WL,
00054                            const MCReadAdvanceEntry *RA,
00055                            const InstrStage *IS,
00056                            const unsigned *OC, const unsigned *FP);
00057 
00058   /// getTargetTriple - Return the target triple string.
00059   StringRef getTargetTriple() const {
00060     return TargetTriple;
00061   }
00062 
00063   /// getCPU - Return the CPU string.
00064   StringRef getCPU() const {
00065     return CPU;
00066   }
00067 
00068   /// getFeatureBits - Return the feature bits.
00069   ///
00070   uint64_t getFeatureBits() const {
00071     return FeatureBits;
00072   }
00073 
00074   /// setFeatureBits - Set the feature bits.
00075   ///
00076   void setFeatureBits(uint64_t FeatureBits_) { FeatureBits = FeatureBits_; }
00077 
00078   /// InitMCProcessorInfo - Set or change the CPU (optionally supplemented with
00079   /// feature string). Recompute feature bits and scheduling model.
00080   void InitMCProcessorInfo(StringRef CPU, StringRef FS);
00081 
00082   /// InitCPUSchedModel - Recompute scheduling model based on CPU.
00083   void InitCPUSchedModel(StringRef CPU);
00084 
00085   /// ToggleFeature - Toggle a feature and returns the re-computed feature
00086   /// bits. This version does not change the implied bits.
00087   uint64_t ToggleFeature(uint64_t FB);
00088 
00089   /// ToggleFeature - Toggle a feature and returns the re-computed feature
00090   /// bits. This version will also change all implied bits.
00091   uint64_t ToggleFeature(StringRef FS);
00092 
00093   /// getSchedModelForCPU - Get the machine model of a CPU.
00094   ///
00095   MCSchedModel getSchedModelForCPU(StringRef CPU) const;
00096 
00097   /// getSchedModel - Get the machine model for this subtarget's CPU.
00098   ///
00099   const MCSchedModel &getSchedModel() const { return CPUSchedModel; }
00100 
00101   /// Return an iterator at the first process resource consumed by the given
00102   /// scheduling class.
00103   const MCWriteProcResEntry *getWriteProcResBegin(
00104     const MCSchedClassDesc *SC) const {
00105     return &WriteProcResTable[SC->WriteProcResIdx];
00106   }
00107   const MCWriteProcResEntry *getWriteProcResEnd(
00108     const MCSchedClassDesc *SC) const {
00109     return getWriteProcResBegin(SC) + SC->NumWriteProcResEntries;
00110   }
00111 
00112   const MCWriteLatencyEntry *getWriteLatencyEntry(const MCSchedClassDesc *SC,
00113                                                   unsigned DefIdx) const {
00114     assert(DefIdx < SC->NumWriteLatencyEntries &&
00115            "MachineModel does not specify a WriteResource for DefIdx");
00116 
00117     return &WriteLatencyTable[SC->WriteLatencyIdx + DefIdx];
00118   }
00119 
00120   int getReadAdvanceCycles(const MCSchedClassDesc *SC, unsigned UseIdx,
00121                            unsigned WriteResID) const {
00122     // TODO: The number of read advance entries in a class can be significant
00123     // (~50). Consider compressing the WriteID into a dense ID of those that are
00124     // used by ReadAdvance and representing them as a bitset.
00125     for (const MCReadAdvanceEntry *I = &ReadAdvanceTable[SC->ReadAdvanceIdx],
00126            *E = I + SC->NumReadAdvanceEntries; I != E; ++I) {
00127       if (I->UseIdx < UseIdx)
00128         continue;
00129       if (I->UseIdx > UseIdx)
00130         break;
00131       // Find the first WriteResIdx match, which has the highest cycle count.
00132       if (!I->WriteResourceID || I->WriteResourceID == WriteResID) {
00133         return I->Cycles;
00134       }
00135     }
00136     return 0;
00137   }
00138 
00139   /// getInstrItineraryForCPU - Get scheduling itinerary of a CPU.
00140   ///
00141   InstrItineraryData getInstrItineraryForCPU(StringRef CPU) const;
00142 
00143   /// Initialize an InstrItineraryData instance.
00144   void initInstrItins(InstrItineraryData &InstrItins) const;
00145 
00146   /// Check whether the CPU string is valid.
00147   bool isCPUStringValid(StringRef CPU) {
00148     auto Found = std::find_if(ProcDesc.begin(), ProcDesc.end(),
00149                               [=](const SubtargetFeatureKV &KV) {
00150                                 return CPU == KV.Key; 
00151                               });
00152     return Found != ProcDesc.end();
00153   }
00154 };
00155 
00156 } // End llvm namespace
00157 
00158 #endif