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MCSubtargetInfo.h
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00001 //==-- llvm/MC/MCSubtargetInfo.h - Subtarget Information ---------*- C++ -*-==//
00002 //
00003 //                     The LLVM Compiler Infrastructure
00004 //
00005 // This file is distributed under the University of Illinois Open Source
00006 // License. See LICENSE.TXT for details.
00007 //
00008 //===----------------------------------------------------------------------===//
00009 //
00010 // This file describes the subtarget options of a Target machine.
00011 //
00012 //===----------------------------------------------------------------------===//
00013 
00014 #ifndef LLVM_MC_MCSUBTARGETINFO_H
00015 #define LLVM_MC_MCSUBTARGETINFO_H
00016 
00017 #include "llvm/MC/MCInstrItineraries.h"
00018 #include "llvm/MC/SubtargetFeature.h"
00019 #include <string>
00020 
00021 namespace llvm {
00022 
00023 class StringRef;
00024 
00025 //===----------------------------------------------------------------------===//
00026 ///
00027 /// MCSubtargetInfo - Generic base class for all target subtargets.
00028 ///
00029 class MCSubtargetInfo {
00030   Triple TargetTriple;                        // Target triple
00031   std::string CPU; // CPU being targeted.
00032   ArrayRef<SubtargetFeatureKV> ProcFeatures;  // Processor feature list
00033   ArrayRef<SubtargetFeatureKV> ProcDesc;  // Processor descriptions
00034 
00035   // Scheduler machine model
00036   const SubtargetInfoKV *ProcSchedModels;
00037   const MCWriteProcResEntry *WriteProcResTable;
00038   const MCWriteLatencyEntry *WriteLatencyTable;
00039   const MCReadAdvanceEntry *ReadAdvanceTable;
00040   const MCSchedModel *CPUSchedModel;
00041 
00042   const InstrStage *Stages;            // Instruction itinerary stages
00043   const unsigned *OperandCycles;       // Itinerary operand cycles
00044   const unsigned *ForwardingPaths;     // Forwarding paths
00045   FeatureBitset FeatureBits;           // Feature bits for current CPU + FS
00046 
00047   MCSubtargetInfo() = delete;
00048   MCSubtargetInfo &operator=(MCSubtargetInfo &&) = delete;
00049   MCSubtargetInfo &operator=(const MCSubtargetInfo &) = delete;
00050 
00051 public:
00052   MCSubtargetInfo(const MCSubtargetInfo &) = default;
00053   MCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS,
00054                   ArrayRef<SubtargetFeatureKV> PF,
00055                   ArrayRef<SubtargetFeatureKV> PD,
00056                   const SubtargetInfoKV *ProcSched,
00057                   const MCWriteProcResEntry *WPR, const MCWriteLatencyEntry *WL,
00058                   const MCReadAdvanceEntry *RA, const InstrStage *IS,
00059                   const unsigned *OC, const unsigned *FP);
00060 
00061   /// getTargetTriple - Return the target triple string.
00062   const Triple &getTargetTriple() const { return TargetTriple; }
00063 
00064   /// getCPU - Return the CPU string.
00065   StringRef getCPU() const {
00066     return CPU;
00067   }
00068 
00069   /// getFeatureBits - Return the feature bits.
00070   ///
00071   const FeatureBitset& getFeatureBits() const {
00072     return FeatureBits;
00073   }
00074 
00075   /// setFeatureBits - Set the feature bits.
00076   ///
00077   void setFeatureBits(const FeatureBitset &FeatureBits_) {
00078     FeatureBits = FeatureBits_;
00079   }
00080 
00081 protected:
00082   /// Initialize the scheduling model and feature bits.
00083   ///
00084   /// FIXME: Find a way to stick this in the constructor, since it should only
00085   /// be called during initialization.
00086   void InitMCProcessorInfo(StringRef CPU, StringRef FS);
00087 
00088 public:
00089   /// Set the features to the default for the given CPU with an appended feature
00090   /// string.
00091   void setDefaultFeatures(StringRef CPU, StringRef FS);
00092 
00093   /// ToggleFeature - Toggle a feature and returns the re-computed feature
00094   /// bits. This version does not change the implied bits.
00095   FeatureBitset ToggleFeature(uint64_t FB);
00096 
00097   /// ToggleFeature - Toggle a feature and returns the re-computed feature
00098   /// bits. This version does not change the implied bits.
00099   FeatureBitset ToggleFeature(const FeatureBitset& FB);
00100 
00101   /// ToggleFeature - Toggle a set of features and returns the re-computed
00102   /// feature bits. This version will also change all implied bits.
00103   FeatureBitset ToggleFeature(StringRef FS);
00104 
00105   /// Apply a feature flag and return the re-computed feature bits, including
00106   /// all feature bits implied by the flag.
00107   FeatureBitset ApplyFeatureFlag(StringRef FS);
00108 
00109   /// getSchedModelForCPU - Get the machine model of a CPU.
00110   ///
00111   const MCSchedModel &getSchedModelForCPU(StringRef CPU) const;
00112 
00113   /// Get the machine model for this subtarget's CPU.
00114   const MCSchedModel &getSchedModel() const { return *CPUSchedModel; }
00115 
00116   /// Return an iterator at the first process resource consumed by the given
00117   /// scheduling class.
00118   const MCWriteProcResEntry *getWriteProcResBegin(
00119     const MCSchedClassDesc *SC) const {
00120     return &WriteProcResTable[SC->WriteProcResIdx];
00121   }
00122   const MCWriteProcResEntry *getWriteProcResEnd(
00123     const MCSchedClassDesc *SC) const {
00124     return getWriteProcResBegin(SC) + SC->NumWriteProcResEntries;
00125   }
00126 
00127   const MCWriteLatencyEntry *getWriteLatencyEntry(const MCSchedClassDesc *SC,
00128                                                   unsigned DefIdx) const {
00129     assert(DefIdx < SC->NumWriteLatencyEntries &&
00130            "MachineModel does not specify a WriteResource for DefIdx");
00131 
00132     return &WriteLatencyTable[SC->WriteLatencyIdx + DefIdx];
00133   }
00134 
00135   int getReadAdvanceCycles(const MCSchedClassDesc *SC, unsigned UseIdx,
00136                            unsigned WriteResID) const {
00137     // TODO: The number of read advance entries in a class can be significant
00138     // (~50). Consider compressing the WriteID into a dense ID of those that are
00139     // used by ReadAdvance and representing them as a bitset.
00140     for (const MCReadAdvanceEntry *I = &ReadAdvanceTable[SC->ReadAdvanceIdx],
00141            *E = I + SC->NumReadAdvanceEntries; I != E; ++I) {
00142       if (I->UseIdx < UseIdx)
00143         continue;
00144       if (I->UseIdx > UseIdx)
00145         break;
00146       // Find the first WriteResIdx match, which has the highest cycle count.
00147       if (!I->WriteResourceID || I->WriteResourceID == WriteResID) {
00148         return I->Cycles;
00149       }
00150     }
00151     return 0;
00152   }
00153 
00154   /// getInstrItineraryForCPU - Get scheduling itinerary of a CPU.
00155   ///
00156   InstrItineraryData getInstrItineraryForCPU(StringRef CPU) const;
00157 
00158   /// Initialize an InstrItineraryData instance.
00159   void initInstrItins(InstrItineraryData &InstrItins) const;
00160 
00161   /// Check whether the CPU string is valid.
00162   bool isCPUStringValid(StringRef CPU) const {
00163     auto Found = std::lower_bound(ProcDesc.begin(), ProcDesc.end(), CPU);
00164     return Found != ProcDesc.end() && StringRef(Found->Key) == CPU;
00165   }
00166 };
00167 
00168 } // End llvm namespace
00169 
00170 #endif