LLVM API Documentation

MCSubtargetInfo.h
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00001 //==-- llvm/MC/MCSubtargetInfo.h - Subtarget Information ---------*- C++ -*-==//
00002 //
00003 //                     The LLVM Compiler Infrastructure
00004 //
00005 // This file is distributed under the University of Illinois Open Source
00006 // License. See LICENSE.TXT for details.
00007 //
00008 //===----------------------------------------------------------------------===//
00009 //
00010 // This file describes the subtarget options of a Target machine.
00011 //
00012 //===----------------------------------------------------------------------===//
00013 
00014 #ifndef LLVM_MC_MCSUBTARGET_H
00015 #define LLVM_MC_MCSUBTARGET_H
00016 
00017 #include "llvm/MC/MCInstrItineraries.h"
00018 #include "llvm/MC/SubtargetFeature.h"
00019 #include <string>
00020 
00021 namespace llvm {
00022 
00023 class StringRef;
00024 
00025 //===----------------------------------------------------------------------===//
00026 ///
00027 /// MCSubtargetInfo - Generic base class for all target subtargets.
00028 ///
00029 class MCSubtargetInfo {
00030   std::string TargetTriple;            // Target triple
00031   ArrayRef<SubtargetFeatureKV> ProcFeatures;  // Processor feature list
00032   ArrayRef<SubtargetFeatureKV> ProcDesc;  // Processor descriptions
00033 
00034   // Scheduler machine model
00035   const SubtargetInfoKV *ProcSchedModels;
00036   const MCWriteProcResEntry *WriteProcResTable;
00037   const MCWriteLatencyEntry *WriteLatencyTable;
00038   const MCReadAdvanceEntry *ReadAdvanceTable;
00039   const MCSchedModel *CPUSchedModel;
00040 
00041   const InstrStage *Stages;            // Instruction itinerary stages
00042   const unsigned *OperandCycles;       // Itinerary operand cycles
00043   const unsigned *ForwardingPaths;     // Forwarding paths
00044   uint64_t FeatureBits;                // Feature bits for current CPU + FS
00045 
00046 public:
00047   void InitMCSubtargetInfo(StringRef TT, StringRef CPU, StringRef FS,
00048                            ArrayRef<SubtargetFeatureKV> PF,
00049                            ArrayRef<SubtargetFeatureKV> PD,
00050                            const SubtargetInfoKV *ProcSched,
00051                            const MCWriteProcResEntry *WPR,
00052                            const MCWriteLatencyEntry *WL,
00053                            const MCReadAdvanceEntry *RA,
00054                            const InstrStage *IS,
00055                            const unsigned *OC, const unsigned *FP);
00056 
00057   /// getTargetTriple - Return the target triple string.
00058   StringRef getTargetTriple() const {
00059     return TargetTriple;
00060   }
00061 
00062   /// getFeatureBits - Return the feature bits.
00063   ///
00064   uint64_t getFeatureBits() const {
00065     return FeatureBits;
00066   }
00067 
00068   /// InitMCProcessorInfo - Set or change the CPU (optionally supplemented with
00069   /// feature string). Recompute feature bits and scheduling model.
00070   void InitMCProcessorInfo(StringRef CPU, StringRef FS);
00071 
00072   /// InitCPUSchedModel - Recompute scheduling model based on CPU.
00073   void InitCPUSchedModel(StringRef CPU);
00074 
00075   /// ToggleFeature - Toggle a feature and returns the re-computed feature
00076   /// bits. This version does not change the implied bits.
00077   uint64_t ToggleFeature(uint64_t FB);
00078 
00079   /// ToggleFeature - Toggle a feature and returns the re-computed feature
00080   /// bits. This version will also change all implied bits.
00081   uint64_t ToggleFeature(StringRef FS);
00082 
00083   /// getSchedModelForCPU - Get the machine model of a CPU.
00084   ///
00085   const MCSchedModel *getSchedModelForCPU(StringRef CPU) const;
00086 
00087   /// getSchedModel - Get the machine model for this subtarget's CPU.
00088   ///
00089   const MCSchedModel *getSchedModel() const { return CPUSchedModel; }
00090 
00091   /// Return an iterator at the first process resource consumed by the given
00092   /// scheduling class.
00093   const MCWriteProcResEntry *getWriteProcResBegin(
00094     const MCSchedClassDesc *SC) const {
00095     return &WriteProcResTable[SC->WriteProcResIdx];
00096   }
00097   const MCWriteProcResEntry *getWriteProcResEnd(
00098     const MCSchedClassDesc *SC) const {
00099     return getWriteProcResBegin(SC) + SC->NumWriteProcResEntries;
00100   }
00101 
00102   const MCWriteLatencyEntry *getWriteLatencyEntry(const MCSchedClassDesc *SC,
00103                                                   unsigned DefIdx) const {
00104     assert(DefIdx < SC->NumWriteLatencyEntries &&
00105            "MachineModel does not specify a WriteResource for DefIdx");
00106 
00107     return &WriteLatencyTable[SC->WriteLatencyIdx + DefIdx];
00108   }
00109 
00110   int getReadAdvanceCycles(const MCSchedClassDesc *SC, unsigned UseIdx,
00111                            unsigned WriteResID) const {
00112     // TODO: The number of read advance entries in a class can be significant
00113     // (~50). Consider compressing the WriteID into a dense ID of those that are
00114     // used by ReadAdvance and representing them as a bitset.
00115     for (const MCReadAdvanceEntry *I = &ReadAdvanceTable[SC->ReadAdvanceIdx],
00116            *E = I + SC->NumReadAdvanceEntries; I != E; ++I) {
00117       if (I->UseIdx < UseIdx)
00118         continue;
00119       if (I->UseIdx > UseIdx)
00120         break;
00121       // Find the first WriteResIdx match, which has the highest cycle count.
00122       if (!I->WriteResourceID || I->WriteResourceID == WriteResID) {
00123         return I->Cycles;
00124       }
00125     }
00126     return 0;
00127   }
00128 
00129   /// getInstrItineraryForCPU - Get scheduling itinerary of a CPU.
00130   ///
00131   InstrItineraryData getInstrItineraryForCPU(StringRef CPU) const;
00132 
00133   /// Initialize an InstrItineraryData instance.
00134   void initInstrItins(InstrItineraryData &InstrItins) const;
00135 };
00136 
00137 } // End llvm namespace
00138 
00139 #endif