LLVM API Documentation

MipsSubtarget.h
Go to the documentation of this file.
00001 //===-- MipsSubtarget.h - Define Subtarget for the Mips ---------*- C++ -*-===//
00002 //
00003 //                     The LLVM Compiler Infrastructure
00004 //
00005 // This file is distributed under the University of Illinois Open Source
00006 // License. See LICENSE.TXT for details.
00007 //
00008 //===----------------------------------------------------------------------===//
00009 //
00010 // This file declares the Mips specific subclass of TargetSubtargetInfo.
00011 //
00012 //===----------------------------------------------------------------------===//
00013 
00014 #ifndef LLVM_LIB_TARGET_MIPS_MIPSSUBTARGET_H
00015 #define LLVM_LIB_TARGET_MIPS_MIPSSUBTARGET_H
00016 
00017 #include "MipsFrameLowering.h"
00018 #include "MipsISelLowering.h"
00019 #include "MipsInstrInfo.h"
00020 #include "MipsSelectionDAGInfo.h"
00021 #include "llvm/IR/DataLayout.h"
00022 #include "llvm/MC/MCInstrItineraries.h"
00023 #include "llvm/Support/ErrorHandling.h"
00024 #include "llvm/Target/TargetSubtargetInfo.h"
00025 #include <string>
00026 
00027 #define GET_SUBTARGETINFO_HEADER
00028 #include "MipsGenSubtargetInfo.inc"
00029 
00030 namespace llvm {
00031 class StringRef;
00032 
00033 class MipsTargetMachine;
00034 
00035 class MipsSubtarget : public MipsGenSubtargetInfo {
00036   virtual void anchor();
00037 
00038 public:
00039   // NOTE: O64 will not be supported.
00040   enum MipsABIEnum {
00041     UnknownABI, O32, N32, N64, EABI
00042   };
00043 
00044 protected:
00045   enum MipsArchEnum {
00046     Mips1, Mips2, Mips32, Mips32r2, Mips32r6, Mips3, Mips4, Mips5, Mips64,
00047     Mips64r2, Mips64r6
00048   };
00049 
00050   // Mips architecture version
00051   MipsArchEnum MipsArchVersion;
00052 
00053   // Mips supported ABIs
00054   MipsABIEnum MipsABI;
00055 
00056   // IsLittle - The target is Little Endian
00057   bool IsLittle;
00058 
00059   // IsSingleFloat - The target only supports single precision float
00060   // point operations. This enable the target to use all 32 32-bit
00061   // floating point registers instead of only using even ones.
00062   bool IsSingleFloat;
00063 
00064   // IsFPXX - MIPS O32 modeless ABI.
00065   bool IsFPXX;
00066 
00067   // NoABICalls - Disable SVR4-style position-independent code.
00068   bool NoABICalls;
00069 
00070   // IsFP64bit - The target processor has 64-bit floating point registers.
00071   bool IsFP64bit;
00072 
00073   /// Are odd single-precision registers permitted?
00074   /// This corresponds to -modd-spreg and -mno-odd-spreg
00075   bool UseOddSPReg;
00076 
00077   // IsNan2008 - IEEE 754-2008 NaN encoding.
00078   bool IsNaN2008bit;
00079 
00080   // IsFP64bit - General-purpose registers are 64 bits wide
00081   bool IsGP64bit;
00082 
00083   // HasVFPU - Processor has a vector floating point unit.
00084   bool HasVFPU;
00085 
00086   // CPU supports cnMIPS (Cavium Networks Octeon CPU).
00087   bool HasCnMips;
00088 
00089   // isLinux - Target system is Linux. Is false we consider ELFOS for now.
00090   bool IsLinux;
00091 
00092   // UseSmallSection - Small section is used.
00093   bool UseSmallSection;
00094 
00095   /// Features related to the presence of specific instructions.
00096 
00097   // HasMips3_32 - The subset of MIPS-III instructions added to MIPS32
00098   bool HasMips3_32;
00099 
00100   // HasMips3_32r2 - The subset of MIPS-III instructions added to MIPS32r2
00101   bool HasMips3_32r2;
00102 
00103   // HasMips4_32 - Has the subset of MIPS-IV present in MIPS32
00104   bool HasMips4_32;
00105 
00106   // HasMips4_32r2 - Has the subset of MIPS-IV present in MIPS32r2
00107   bool HasMips4_32r2;
00108 
00109   // HasMips5_32r2 - Has the subset of MIPS-V present in MIPS32r2
00110   bool HasMips5_32r2;
00111 
00112   // InMips16 -- can process Mips16 instructions
00113   bool InMips16Mode;
00114 
00115   // Mips16 hard float
00116   bool InMips16HardFloat;
00117 
00118   // PreviousInMips16 -- the function we just processed was in Mips 16 Mode
00119   bool PreviousInMips16Mode;
00120 
00121   // InMicroMips -- can process MicroMips instructions
00122   bool InMicroMipsMode;
00123 
00124   // HasDSP, HasDSPR2 -- supports DSP ASE.
00125   bool HasDSP, HasDSPR2;
00126 
00127   // Allow mixed Mips16 and Mips32 in one source file
00128   bool AllowMixed16_32;
00129 
00130   // Optimize for space by compiling all functions as Mips 16 unless
00131   // it needs floating point. Functions needing floating point are
00132   // compiled as Mips32
00133   bool Os16;
00134 
00135   // HasMSA -- supports MSA ASE.
00136   bool HasMSA;
00137 
00138   InstrItineraryData InstrItins;
00139 
00140   // We can override the determination of whether we are in mips16 mode
00141   // as from the command line
00142   enum {NoOverride, Mips16Override, NoMips16Override} OverrideMode;
00143 
00144   const MipsTargetMachine *TM;
00145 
00146   Triple TargetTriple;
00147 
00148   const DataLayout DL; // Calculates type size & alignment
00149   const MipsSelectionDAGInfo TSInfo;
00150   std::unique_ptr<const MipsInstrInfo> InstrInfo;
00151   std::unique_ptr<const MipsFrameLowering> FrameLowering;
00152   std::unique_ptr<const MipsTargetLowering> TLInfo;
00153 
00154 public:
00155   /// This overrides the PostRAScheduler bit in the SchedModel for each CPU.
00156   bool enablePostMachineScheduler() const override;
00157   void getCriticalPathRCs(RegClassVector &CriticalPathRCs) const override;
00158   CodeGenOpt::Level getOptLevelToEnablePostRAScheduler() const override;
00159 
00160   /// Only O32 and EABI supported right now.
00161   bool isABI_EABI() const { return MipsABI == EABI; }
00162   bool isABI_N64() const { return MipsABI == N64; }
00163   bool isABI_N32() const { return MipsABI == N32; }
00164   bool isABI_O32() const { return MipsABI == O32; }
00165   bool isABI_FPXX() const { return isABI_O32() && IsFPXX; }
00166   unsigned getTargetABI() const { return MipsABI; }
00167 
00168   /// This constructor initializes the data members to match that
00169   /// of the specified triple.
00170   MipsSubtarget(const std::string &TT, const std::string &CPU,
00171                 const std::string &FS, bool little,
00172                 const MipsTargetMachine *TM);
00173 
00174   /// ParseSubtargetFeatures - Parses features string setting specified
00175   /// subtarget options.  Definition of function is auto generated by tblgen.
00176   void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
00177 
00178   bool hasMips1() const { return MipsArchVersion >= Mips1; }
00179   bool hasMips2() const { return MipsArchVersion >= Mips2; }
00180   bool hasMips3() const { return MipsArchVersion >= Mips3; }
00181   bool hasMips4() const { return MipsArchVersion >= Mips4; }
00182   bool hasMips5() const { return MipsArchVersion >= Mips5; }
00183   bool hasMips4_32() const { return HasMips4_32; }
00184   bool hasMips4_32r2() const { return HasMips4_32r2; }
00185   bool hasMips32() const {
00186     return MipsArchVersion >= Mips32 && MipsArchVersion != Mips3 &&
00187            MipsArchVersion != Mips4 && MipsArchVersion != Mips5;
00188   }
00189   bool hasMips32r2() const {
00190     return MipsArchVersion == Mips32r2 || MipsArchVersion == Mips32r6 ||
00191            MipsArchVersion == Mips64r2 || MipsArchVersion == Mips64r6;
00192   }
00193   bool hasMips32r6() const {
00194     return MipsArchVersion == Mips32r6 || MipsArchVersion == Mips64r6;
00195   }
00196   bool hasMips64() const { return MipsArchVersion >= Mips64; }
00197   bool hasMips64r2() const {
00198     return MipsArchVersion == Mips64r2 || MipsArchVersion == Mips64r6;
00199   }
00200   bool hasMips64r6() const { return MipsArchVersion == Mips64r6; }
00201 
00202   bool hasCnMips() const { return HasCnMips; }
00203 
00204   bool isLittle() const { return IsLittle; }
00205   bool isABICalls() const { return !NoABICalls; }
00206   bool isFPXX() const { return IsFPXX; }
00207   bool isFP64bit() const { return IsFP64bit; }
00208   bool useOddSPReg() const { return UseOddSPReg; }
00209   bool noOddSPReg() const { return !UseOddSPReg; }
00210   bool isNaN2008() const { return IsNaN2008bit; }
00211   bool isGP64bit() const { return IsGP64bit; }
00212   bool isGP32bit() const { return !IsGP64bit; }
00213   unsigned getGPRSizeInBytes() const { return isGP64bit() ? 8 : 4; }
00214   bool isSingleFloat() const { return IsSingleFloat; }
00215   bool hasVFPU() const { return HasVFPU; }
00216   bool inMips16Mode() const { return InMips16Mode; }
00217   bool inMips16ModeDefault() const {
00218     return InMips16Mode;
00219   }
00220   // Hard float for mips16 means essentially to compile as soft float
00221   // but to use a runtime library for soft float that is written with
00222   // native mips32 floating point instructions (those runtime routines
00223   // run in mips32 hard float mode).
00224   bool inMips16HardFloat() const {
00225     return inMips16Mode() && InMips16HardFloat;
00226   }
00227   bool inMicroMipsMode() const { return InMicroMipsMode; }
00228   bool hasDSP() const { return HasDSP; }
00229   bool hasDSPR2() const { return HasDSPR2; }
00230   bool hasMSA() const { return HasMSA; }
00231   bool isLinux() const { return IsLinux; }
00232   bool useSmallSection() const { return UseSmallSection; }
00233 
00234   bool hasStandardEncoding() const { return !inMips16Mode(); }
00235 
00236   bool abiUsesSoftFloat() const;
00237 
00238   bool enableLongBranchPass() const {
00239     return hasStandardEncoding() || allowMixed16_32();
00240   }
00241 
00242   /// Features related to the presence of specific instructions.
00243   bool hasExtractInsert() const { return !inMips16Mode() && hasMips32r2(); }
00244   bool hasMTHC1() const { return hasMips32r2(); }
00245 
00246   bool allowMixed16_32() const { return inMips16ModeDefault() |
00247                                         AllowMixed16_32;}
00248 
00249   bool os16() const { return Os16;};
00250 
00251   bool isTargetNaCl() const { return TargetTriple.isOSNaCl(); }
00252 
00253   // for now constant islands are on for the whole compilation unit but we only
00254   // really use them if in addition we are in mips16 mode
00255   static bool useConstantIslands();
00256 
00257   unsigned stackAlignment() const { return hasMips64() ? 16 : 8; }
00258 
00259   // Grab relocation model
00260   Reloc::Model getRelocationModel() const;
00261 
00262   MipsSubtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS,
00263                                                  const TargetMachine *TM);
00264 
00265   /// Does the system support unaligned memory access.
00266   ///
00267   /// MIPS32r6/MIPS64r6 require full unaligned access support but does not
00268   /// specify which component of the system provides it. Hardware, software, and
00269   /// hybrid implementations are all valid.
00270   bool systemSupportsUnalignedAccess() const { return hasMips32r6(); }
00271 
00272   // Set helper classes
00273   void setHelperClassesMips16();
00274   void setHelperClassesMipsSE();
00275 
00276   const MipsSelectionDAGInfo *getSelectionDAGInfo() const override {
00277     return &TSInfo;
00278   }
00279   const DataLayout *getDataLayout() const override { return &DL; }
00280   const MipsInstrInfo *getInstrInfo() const override { return InstrInfo.get(); }
00281   const TargetFrameLowering *getFrameLowering() const override {
00282     return FrameLowering.get();
00283   }
00284   const MipsRegisterInfo *getRegisterInfo() const override {
00285     return &InstrInfo->getRegisterInfo();
00286   }
00287   const MipsTargetLowering *getTargetLowering() const override {
00288     return TLInfo.get();
00289   }
00290   const InstrItineraryData *getInstrItineraryData() const override {
00291     return &InstrItins;
00292   }
00293 };
00294 } // End llvm namespace
00295 
00296 #endif