LLVM API Documentation

MipsSubtarget.h
Go to the documentation of this file.
00001 //===-- MipsSubtarget.h - Define Subtarget for the Mips ---------*- C++ -*-===//
00002 //
00003 //                     The LLVM Compiler Infrastructure
00004 //
00005 // This file is distributed under the University of Illinois Open Source
00006 // License. See LICENSE.TXT for details.
00007 //
00008 //===----------------------------------------------------------------------===//
00009 //
00010 // This file declares the Mips specific subclass of TargetSubtargetInfo.
00011 //
00012 //===----------------------------------------------------------------------===//
00013 
00014 #ifndef LLVM_LIB_TARGET_MIPS_MIPSSUBTARGET_H
00015 #define LLVM_LIB_TARGET_MIPS_MIPSSUBTARGET_H
00016 
00017 #include "MipsFrameLowering.h"
00018 #include "MipsISelLowering.h"
00019 #include "MipsInstrInfo.h"
00020 #include "MipsJITInfo.h"
00021 #include "MipsSelectionDAGInfo.h"
00022 #include "llvm/IR/DataLayout.h"
00023 #include "llvm/MC/MCInstrItineraries.h"
00024 #include "llvm/Support/ErrorHandling.h"
00025 #include "llvm/Target/TargetSubtargetInfo.h"
00026 #include <string>
00027 
00028 #define GET_SUBTARGETINFO_HEADER
00029 #include "MipsGenSubtargetInfo.inc"
00030 
00031 namespace llvm {
00032 class StringRef;
00033 
00034 class MipsTargetMachine;
00035 
00036 class MipsSubtarget : public MipsGenSubtargetInfo {
00037   virtual void anchor();
00038 
00039 public:
00040   // NOTE: O64 will not be supported.
00041   enum MipsABIEnum {
00042     UnknownABI, O32, N32, N64, EABI
00043   };
00044 
00045 protected:
00046   enum MipsArchEnum {
00047     Mips1, Mips2, Mips32, Mips32r2, Mips32r6, Mips3, Mips4, Mips5, Mips64,
00048     Mips64r2, Mips64r6
00049   };
00050 
00051   // Mips architecture version
00052   MipsArchEnum MipsArchVersion;
00053 
00054   // Mips supported ABIs
00055   MipsABIEnum MipsABI;
00056 
00057   // IsLittle - The target is Little Endian
00058   bool IsLittle;
00059 
00060   // IsSingleFloat - The target only supports single precision float
00061   // point operations. This enable the target to use all 32 32-bit
00062   // floating point registers instead of only using even ones.
00063   bool IsSingleFloat;
00064 
00065   // IsFPXX - MIPS O32 modeless ABI.
00066   bool IsFPXX;
00067 
00068   // NoABICalls - Disable SVR4-style position-independent code.
00069   bool NoABICalls;
00070 
00071   // IsFP64bit - The target processor has 64-bit floating point registers.
00072   bool IsFP64bit;
00073 
00074   /// Are odd single-precision registers permitted?
00075   /// This corresponds to -modd-spreg and -mno-odd-spreg
00076   bool UseOddSPReg;
00077 
00078   // IsNan2008 - IEEE 754-2008 NaN encoding.
00079   bool IsNaN2008bit;
00080 
00081   // IsFP64bit - General-purpose registers are 64 bits wide
00082   bool IsGP64bit;
00083 
00084   // HasVFPU - Processor has a vector floating point unit.
00085   bool HasVFPU;
00086 
00087   // CPU supports cnMIPS (Cavium Networks Octeon CPU).
00088   bool HasCnMips;
00089 
00090   // isLinux - Target system is Linux. Is false we consider ELFOS for now.
00091   bool IsLinux;
00092 
00093   // UseSmallSection - Small section is used.
00094   bool UseSmallSection;
00095 
00096   /// Features related to the presence of specific instructions.
00097 
00098   // HasMips3_32 - The subset of MIPS-III instructions added to MIPS32
00099   bool HasMips3_32;
00100 
00101   // HasMips3_32r2 - The subset of MIPS-III instructions added to MIPS32r2
00102   bool HasMips3_32r2;
00103 
00104   // HasMips4_32 - Has the subset of MIPS-IV present in MIPS32
00105   bool HasMips4_32;
00106 
00107   // HasMips4_32r2 - Has the subset of MIPS-IV present in MIPS32r2
00108   bool HasMips4_32r2;
00109 
00110   // HasMips5_32r2 - Has the subset of MIPS-V present in MIPS32r2
00111   bool HasMips5_32r2;
00112 
00113   // InMips16 -- can process Mips16 instructions
00114   bool InMips16Mode;
00115 
00116   // Mips16 hard float
00117   bool InMips16HardFloat;
00118 
00119   // PreviousInMips16 -- the function we just processed was in Mips 16 Mode
00120   bool PreviousInMips16Mode;
00121 
00122   // InMicroMips -- can process MicroMips instructions
00123   bool InMicroMipsMode;
00124 
00125   // HasDSP, HasDSPR2 -- supports DSP ASE.
00126   bool HasDSP, HasDSPR2;
00127 
00128   // Allow mixed Mips16 and Mips32 in one source file
00129   bool AllowMixed16_32;
00130 
00131   // Optimize for space by compiling all functions as Mips 16 unless
00132   // it needs floating point. Functions needing floating point are
00133   // compiled as Mips32
00134   bool Os16;
00135 
00136   // HasMSA -- supports MSA ASE.
00137   bool HasMSA;
00138 
00139   InstrItineraryData InstrItins;
00140 
00141   // We can override the determination of whether we are in mips16 mode
00142   // as from the command line
00143   enum {NoOverride, Mips16Override, NoMips16Override} OverrideMode;
00144 
00145   MipsTargetMachine *TM;
00146 
00147   Triple TargetTriple;
00148 
00149   const DataLayout DL; // Calculates type size & alignment
00150   const MipsSelectionDAGInfo TSInfo;
00151   MipsJITInfo JITInfo;
00152   std::unique_ptr<const MipsInstrInfo> InstrInfo;
00153   std::unique_ptr<const MipsFrameLowering> FrameLowering;
00154   std::unique_ptr<const MipsTargetLowering> TLInfo;
00155 
00156 public:
00157   /// This overrides the PostRAScheduler bit in the SchedModel for each CPU.
00158   bool enablePostMachineScheduler() const override;
00159   void getCriticalPathRCs(RegClassVector &CriticalPathRCs) const override;
00160   CodeGenOpt::Level getOptLevelToEnablePostRAScheduler() const override;
00161 
00162   /// Only O32 and EABI supported right now.
00163   bool isABI_EABI() const { return MipsABI == EABI; }
00164   bool isABI_N64() const { return MipsABI == N64; }
00165   bool isABI_N32() const { return MipsABI == N32; }
00166   bool isABI_O32() const { return MipsABI == O32; }
00167   bool isABI_FPXX() const { return isABI_O32() && IsFPXX; }
00168   unsigned getTargetABI() const { return MipsABI; }
00169 
00170   /// This constructor initializes the data members to match that
00171   /// of the specified triple.
00172   MipsSubtarget(const std::string &TT, const std::string &CPU,
00173                 const std::string &FS, bool little, MipsTargetMachine *TM);
00174 
00175   /// ParseSubtargetFeatures - Parses features string setting specified
00176   /// subtarget options.  Definition of function is auto generated by tblgen.
00177   void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
00178 
00179   bool hasMips1() const { return MipsArchVersion >= Mips1; }
00180   bool hasMips2() const { return MipsArchVersion >= Mips2; }
00181   bool hasMips3() const { return MipsArchVersion >= Mips3; }
00182   bool hasMips4() const { return MipsArchVersion >= Mips4; }
00183   bool hasMips5() const { return MipsArchVersion >= Mips5; }
00184   bool hasMips4_32() const { return HasMips4_32; }
00185   bool hasMips4_32r2() const { return HasMips4_32r2; }
00186   bool hasMips32() const {
00187     return MipsArchVersion >= Mips32 && MipsArchVersion != Mips3 &&
00188            MipsArchVersion != Mips4 && MipsArchVersion != Mips5;
00189   }
00190   bool hasMips32r2() const {
00191     return MipsArchVersion == Mips32r2 || MipsArchVersion == Mips32r6 ||
00192            MipsArchVersion == Mips64r2 || MipsArchVersion == Mips64r6;
00193   }
00194   bool hasMips32r6() const {
00195     return MipsArchVersion == Mips32r6 || MipsArchVersion == Mips64r6;
00196   }
00197   bool hasMips64() const { return MipsArchVersion >= Mips64; }
00198   bool hasMips64r2() const {
00199     return MipsArchVersion == Mips64r2 || MipsArchVersion == Mips64r6;
00200   }
00201   bool hasMips64r6() const { return MipsArchVersion == Mips64r6; }
00202 
00203   bool hasCnMips() const { return HasCnMips; }
00204 
00205   bool isLittle() const { return IsLittle; }
00206   bool isABICalls() const { return !NoABICalls; }
00207   bool isFPXX() const { return IsFPXX; }
00208   bool isFP64bit() const { return IsFP64bit; }
00209   bool useOddSPReg() const { return UseOddSPReg; }
00210   bool noOddSPReg() const { return !UseOddSPReg; }
00211   bool isNaN2008() const { return IsNaN2008bit; }
00212   bool isNotFP64bit() const { return !IsFP64bit; }
00213   bool isGP64bit() const { return IsGP64bit; }
00214   bool isGP32bit() const { return !IsGP64bit; }
00215   bool isSingleFloat() const { return IsSingleFloat; }
00216   bool isNotSingleFloat() const { return !IsSingleFloat; }
00217   bool hasVFPU() const { return HasVFPU; }
00218   bool inMips16Mode() const { return InMips16Mode; }
00219   bool inMips16ModeDefault() const {
00220     return InMips16Mode;
00221   }
00222   // Hard float for mips16 means essentially to compile as soft float
00223   // but to use a runtime library for soft float that is written with
00224   // native mips32 floating point instructions (those runtime routines
00225   // run in mips32 hard float mode).
00226   bool inMips16HardFloat() const {
00227     return inMips16Mode() && InMips16HardFloat;
00228   }
00229   bool inMicroMipsMode() const { return InMicroMipsMode; }
00230   bool hasDSP() const { return HasDSP; }
00231   bool hasDSPR2() const { return HasDSPR2; }
00232   bool hasMSA() const { return HasMSA; }
00233   bool isLinux() const { return IsLinux; }
00234   bool useSmallSection() const { return UseSmallSection; }
00235 
00236   bool hasStandardEncoding() const { return !inMips16Mode(); }
00237 
00238   bool abiUsesSoftFloat() const;
00239 
00240   bool enableLongBranchPass() const {
00241     return hasStandardEncoding() || allowMixed16_32();
00242   }
00243 
00244   /// Features related to the presence of specific instructions.
00245   bool hasExtractInsert() const { return !inMips16Mode() && hasMips32r2(); }
00246   bool hasMTHC1() const { return hasMips32r2(); }
00247 
00248   bool allowMixed16_32() const { return inMips16ModeDefault() |
00249                                         AllowMixed16_32;}
00250 
00251   bool os16() const { return Os16;};
00252 
00253   bool isTargetNaCl() const { return TargetTriple.isOSNaCl(); }
00254   bool isNotTargetNaCl() const { return !TargetTriple.isOSNaCl(); }
00255 
00256   // for now constant islands are on for the whole compilation unit but we only
00257   // really use them if in addition we are in mips16 mode
00258   static bool useConstantIslands();
00259 
00260   unsigned stackAlignment() const { return hasMips64() ? 16 : 8; }
00261 
00262   // Grab relocation model
00263   Reloc::Model getRelocationModel() const;
00264 
00265   MipsSubtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS,
00266                                                  const TargetMachine *TM);
00267 
00268   /// Does the system support unaligned memory access.
00269   ///
00270   /// MIPS32r6/MIPS64r6 require full unaligned access support but does not
00271   /// specify which component of the system provides it. Hardware, software, and
00272   /// hybrid implementations are all valid.
00273   bool systemSupportsUnalignedAccess() const { return hasMips32r6(); }
00274 
00275   // Set helper classes
00276   void setHelperClassesMips16();
00277   void setHelperClassesMipsSE();
00278 
00279   MipsJITInfo *getJITInfo() override { return &JITInfo; }
00280   const MipsSelectionDAGInfo *getSelectionDAGInfo() const override {
00281     return &TSInfo;
00282   }
00283   const DataLayout *getDataLayout() const override { return &DL; }
00284   const MipsInstrInfo *getInstrInfo() const override { return InstrInfo.get(); }
00285   const TargetFrameLowering *getFrameLowering() const override {
00286     return FrameLowering.get();
00287   }
00288   const MipsRegisterInfo *getRegisterInfo() const override {
00289     return &InstrInfo->getRegisterInfo();
00290   }
00291   const MipsTargetLowering *getTargetLowering() const override {
00292     return TLInfo.get();
00293   }
00294   const InstrItineraryData *getInstrItineraryData() const override {
00295     return &InstrItins;
00296   }
00297 };
00298 } // End llvm namespace
00299 
00300 #endif