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MipsSubtarget.h
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00001 //===-- MipsSubtarget.h - Define Subtarget for the Mips ---------*- C++ -*-===//
00002 //
00003 //                     The LLVM Compiler Infrastructure
00004 //
00005 // This file is distributed under the University of Illinois Open Source
00006 // License. See LICENSE.TXT for details.
00007 //
00008 //===----------------------------------------------------------------------===//
00009 //
00010 // This file declares the Mips specific subclass of TargetSubtargetInfo.
00011 //
00012 //===----------------------------------------------------------------------===//
00013 
00014 #ifndef LLVM_LIB_TARGET_MIPS_MIPSSUBTARGET_H
00015 #define LLVM_LIB_TARGET_MIPS_MIPSSUBTARGET_H
00016 
00017 #include "MCTargetDesc/MipsABIInfo.h"
00018 #include "MipsFrameLowering.h"
00019 #include "MipsISelLowering.h"
00020 #include "MipsInstrInfo.h"
00021 #include "MipsSelectionDAGInfo.h"
00022 #include "llvm/IR/DataLayout.h"
00023 #include "llvm/MC/MCInstrItineraries.h"
00024 #include "llvm/Support/ErrorHandling.h"
00025 #include "llvm/Target/TargetSubtargetInfo.h"
00026 #include <string>
00027 
00028 #define GET_SUBTARGETINFO_HEADER
00029 #include "MipsGenSubtargetInfo.inc"
00030 
00031 namespace llvm {
00032 class StringRef;
00033 
00034 class MipsTargetMachine;
00035 
00036 class MipsSubtarget : public MipsGenSubtargetInfo {
00037   virtual void anchor();
00038 
00039   enum MipsArchEnum {
00040     MipsDefault,
00041     Mips1, Mips2, Mips32, Mips32r2, Mips32r3, Mips32r5, Mips32r6, Mips32Max,
00042     Mips3, Mips4, Mips5, Mips64, Mips64r2, Mips64r3, Mips64r5, Mips64r6
00043   };
00044 
00045   // Mips architecture version
00046   MipsArchEnum MipsArchVersion;
00047 
00048   // IsLittle - The target is Little Endian
00049   bool IsLittle;
00050 
00051   // IsSingleFloat - The target only supports single precision float
00052   // point operations. This enable the target to use all 32 32-bit
00053   // floating point registers instead of only using even ones.
00054   bool IsSingleFloat;
00055 
00056   // IsFPXX - MIPS O32 modeless ABI.
00057   bool IsFPXX;
00058 
00059   // NoABICalls - Disable SVR4-style position-independent code.
00060   bool NoABICalls;
00061 
00062   // IsFP64bit - The target processor has 64-bit floating point registers.
00063   bool IsFP64bit;
00064 
00065   /// Are odd single-precision registers permitted?
00066   /// This corresponds to -modd-spreg and -mno-odd-spreg
00067   bool UseOddSPReg;
00068 
00069   // IsNan2008 - IEEE 754-2008 NaN encoding.
00070   bool IsNaN2008bit;
00071 
00072   // IsFP64bit - General-purpose registers are 64 bits wide
00073   bool IsGP64bit;
00074 
00075   // HasVFPU - Processor has a vector floating point unit.
00076   bool HasVFPU;
00077 
00078   // CPU supports cnMIPS (Cavium Networks Octeon CPU).
00079   bool HasCnMips;
00080 
00081   // isLinux - Target system is Linux. Is false we consider ELFOS for now.
00082   bool IsLinux;
00083 
00084   // UseSmallSection - Small section is used.
00085   bool UseSmallSection;
00086 
00087   /// Features related to the presence of specific instructions.
00088 
00089   // HasMips3_32 - The subset of MIPS-III instructions added to MIPS32
00090   bool HasMips3_32;
00091 
00092   // HasMips3_32r2 - The subset of MIPS-III instructions added to MIPS32r2
00093   bool HasMips3_32r2;
00094 
00095   // HasMips4_32 - Has the subset of MIPS-IV present in MIPS32
00096   bool HasMips4_32;
00097 
00098   // HasMips4_32r2 - Has the subset of MIPS-IV present in MIPS32r2
00099   bool HasMips4_32r2;
00100 
00101   // HasMips5_32r2 - Has the subset of MIPS-V present in MIPS32r2
00102   bool HasMips5_32r2;
00103 
00104   // InMips16 -- can process Mips16 instructions
00105   bool InMips16Mode;
00106 
00107   // Mips16 hard float
00108   bool InMips16HardFloat;
00109 
00110   // PreviousInMips16 -- the function we just processed was in Mips 16 Mode
00111   bool PreviousInMips16Mode;
00112 
00113   // InMicroMips -- can process MicroMips instructions
00114   bool InMicroMipsMode;
00115 
00116   // HasDSP, HasDSPR2 -- supports DSP ASE.
00117   bool HasDSP, HasDSPR2;
00118 
00119   // Allow mixed Mips16 and Mips32 in one source file
00120   bool AllowMixed16_32;
00121 
00122   // Optimize for space by compiling all functions as Mips 16 unless
00123   // it needs floating point. Functions needing floating point are
00124   // compiled as Mips32
00125   bool Os16;
00126 
00127   // HasMSA -- supports MSA ASE.
00128   bool HasMSA;
00129 
00130   InstrItineraryData InstrItins;
00131 
00132   // We can override the determination of whether we are in mips16 mode
00133   // as from the command line
00134   enum {NoOverride, Mips16Override, NoMips16Override} OverrideMode;
00135 
00136   const MipsTargetMachine &TM;
00137 
00138   Triple TargetTriple;
00139 
00140   const MipsSelectionDAGInfo TSInfo;
00141   std::unique_ptr<const MipsInstrInfo> InstrInfo;
00142   std::unique_ptr<const MipsFrameLowering> FrameLowering;
00143   std::unique_ptr<const MipsTargetLowering> TLInfo;
00144 
00145 public:
00146   /// This overrides the PostRAScheduler bit in the SchedModel for each CPU.
00147   bool enablePostMachineScheduler() const override;
00148   void getCriticalPathRCs(RegClassVector &CriticalPathRCs) const override;
00149   CodeGenOpt::Level getOptLevelToEnablePostRAScheduler() const override;
00150 
00151   /// Only O32 and EABI supported right now.
00152   bool isABI_EABI() const;
00153   bool isABI_N64() const;
00154   bool isABI_N32() const;
00155   bool isABI_O32() const;
00156   const MipsABIInfo &getABI() const;
00157   bool isABI_FPXX() const { return isABI_O32() && IsFPXX; }
00158 
00159   /// This constructor initializes the data members to match that
00160   /// of the specified triple.
00161   MipsSubtarget(const std::string &TT, const std::string &CPU,
00162                 const std::string &FS, bool little,
00163                 const MipsTargetMachine &TM);
00164 
00165   /// ParseSubtargetFeatures - Parses features string setting specified
00166   /// subtarget options.  Definition of function is auto generated by tblgen.
00167   void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
00168 
00169   bool hasMips1() const { return MipsArchVersion >= Mips1; }
00170   bool hasMips2() const { return MipsArchVersion >= Mips2; }
00171   bool hasMips3() const { return MipsArchVersion >= Mips3; }
00172   bool hasMips4() const { return MipsArchVersion >= Mips4; }
00173   bool hasMips5() const { return MipsArchVersion >= Mips5; }
00174   bool hasMips4_32() const { return HasMips4_32; }
00175   bool hasMips4_32r2() const { return HasMips4_32r2; }
00176   bool hasMips32() const {
00177     return (MipsArchVersion >= Mips32 && MipsArchVersion < Mips32Max) ||
00178            hasMips64();
00179   }
00180   bool hasMips32r2() const {
00181     return (MipsArchVersion >= Mips32r2 && MipsArchVersion < Mips32Max) ||
00182            hasMips64r2();
00183   }
00184   bool hasMips32r3() const {
00185     return (MipsArchVersion >= Mips32r3 && MipsArchVersion < Mips32Max) ||
00186            hasMips64r2();
00187   }
00188   bool hasMips32r5() const {
00189     return (MipsArchVersion >= Mips32r5 && MipsArchVersion < Mips32Max) ||
00190            hasMips64r2();
00191   }
00192   bool hasMips32r6() const {
00193     return (MipsArchVersion >= Mips32r6 && MipsArchVersion < Mips32Max) ||
00194            hasMips64r6();
00195   }
00196   bool hasMips64() const { return MipsArchVersion >= Mips64; }
00197   bool hasMips64r2() const { return MipsArchVersion >= Mips64r2; }
00198   bool hasMips64r3() const { return MipsArchVersion >= Mips64r3; }
00199   bool hasMips64r5() const { return MipsArchVersion >= Mips64r5; }
00200   bool hasMips64r6() const { return MipsArchVersion >= Mips64r6; }
00201 
00202   bool hasCnMips() const { return HasCnMips; }
00203 
00204   bool isLittle() const { return IsLittle; }
00205   bool isABICalls() const { return !NoABICalls; }
00206   bool isFPXX() const { return IsFPXX; }
00207   bool isFP64bit() const { return IsFP64bit; }
00208   bool useOddSPReg() const { return UseOddSPReg; }
00209   bool noOddSPReg() const { return !UseOddSPReg; }
00210   bool isNaN2008() const { return IsNaN2008bit; }
00211   bool isGP64bit() const { return IsGP64bit; }
00212   bool isGP32bit() const { return !IsGP64bit; }
00213   unsigned getGPRSizeInBytes() const { return isGP64bit() ? 8 : 4; }
00214   bool isSingleFloat() const { return IsSingleFloat; }
00215   bool hasVFPU() const { return HasVFPU; }
00216   bool inMips16Mode() const { return InMips16Mode; }
00217   bool inMips16ModeDefault() const {
00218     return InMips16Mode;
00219   }
00220   // Hard float for mips16 means essentially to compile as soft float
00221   // but to use a runtime library for soft float that is written with
00222   // native mips32 floating point instructions (those runtime routines
00223   // run in mips32 hard float mode).
00224   bool inMips16HardFloat() const {
00225     return inMips16Mode() && InMips16HardFloat;
00226   }
00227   bool inMicroMipsMode() const { return InMicroMipsMode; }
00228   bool hasDSP() const { return HasDSP; }
00229   bool hasDSPR2() const { return HasDSPR2; }
00230   bool hasMSA() const { return HasMSA; }
00231   bool useSmallSection() const { return UseSmallSection; }
00232 
00233   bool hasStandardEncoding() const { return !inMips16Mode(); }
00234 
00235   bool abiUsesSoftFloat() const;
00236 
00237   bool enableLongBranchPass() const {
00238     return hasStandardEncoding() || allowMixed16_32();
00239   }
00240 
00241   /// Features related to the presence of specific instructions.
00242   bool hasExtractInsert() const { return !inMips16Mode() && hasMips32r2(); }
00243   bool hasMTHC1() const { return hasMips32r2(); }
00244 
00245   bool allowMixed16_32() const { return inMips16ModeDefault() |
00246                                         AllowMixed16_32; }
00247 
00248   bool os16() const { return Os16; }
00249 
00250   bool isTargetNaCl() const { return TargetTriple.isOSNaCl(); }
00251 
00252   // for now constant islands are on for the whole compilation unit but we only
00253   // really use them if in addition we are in mips16 mode
00254   static bool useConstantIslands();
00255 
00256   unsigned stackAlignment() const { return hasMips64() ? 16 : 8; }
00257 
00258   // Grab relocation model
00259   Reloc::Model getRelocationModel() const;
00260 
00261   MipsSubtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS,
00262                                                  const TargetMachine &TM);
00263 
00264   /// Does the system support unaligned memory access.
00265   ///
00266   /// MIPS32r6/MIPS64r6 require full unaligned access support but does not
00267   /// specify which component of the system provides it. Hardware, software, and
00268   /// hybrid implementations are all valid.
00269   bool systemSupportsUnalignedAccess() const { return hasMips32r6(); }
00270 
00271   // Set helper classes
00272   void setHelperClassesMips16();
00273   void setHelperClassesMipsSE();
00274 
00275   const MipsSelectionDAGInfo *getSelectionDAGInfo() const override {
00276     return &TSInfo;
00277   }
00278   const MipsInstrInfo *getInstrInfo() const override { return InstrInfo.get(); }
00279   const TargetFrameLowering *getFrameLowering() const override {
00280     return FrameLowering.get();
00281   }
00282   const MipsRegisterInfo *getRegisterInfo() const override {
00283     return &InstrInfo->getRegisterInfo();
00284   }
00285   const MipsTargetLowering *getTargetLowering() const override {
00286     return TLInfo.get();
00287   }
00288   const InstrItineraryData *getInstrItineraryData() const override {
00289     return &InstrItins;
00290   }
00291 };
00292 } // End llvm namespace
00293 
00294 #endif