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MipsSubtarget.h
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00001 //===-- MipsSubtarget.h - Define Subtarget for the Mips ---------*- C++ -*-===//
00002 //
00003 //                     The LLVM Compiler Infrastructure
00004 //
00005 // This file is distributed under the University of Illinois Open Source
00006 // License. See LICENSE.TXT for details.
00007 //
00008 //===----------------------------------------------------------------------===//
00009 //
00010 // This file declares the Mips specific subclass of TargetSubtargetInfo.
00011 //
00012 //===----------------------------------------------------------------------===//
00013 
00014 #ifndef LLVM_LIB_TARGET_MIPS_MIPSSUBTARGET_H
00015 #define LLVM_LIB_TARGET_MIPS_MIPSSUBTARGET_H
00016 
00017 #include "MCTargetDesc/MipsABIInfo.h"
00018 #include "MipsFrameLowering.h"
00019 #include "MipsISelLowering.h"
00020 #include "MipsInstrInfo.h"
00021 #include "llvm/IR/DataLayout.h"
00022 #include "llvm/MC/MCInstrItineraries.h"
00023 #include "llvm/Support/ErrorHandling.h"
00024 #include "llvm/Target/TargetSelectionDAGInfo.h"
00025 #include "llvm/Target/TargetSubtargetInfo.h"
00026 #include <string>
00027 
00028 #define GET_SUBTARGETINFO_HEADER
00029 #include "MipsGenSubtargetInfo.inc"
00030 
00031 namespace llvm {
00032 class StringRef;
00033 
00034 class MipsTargetMachine;
00035 
00036 class MipsSubtarget : public MipsGenSubtargetInfo {
00037   virtual void anchor();
00038 
00039   enum MipsArchEnum {
00040     MipsDefault,
00041     Mips1, Mips2, Mips32, Mips32r2, Mips32r3, Mips32r5, Mips32r6, Mips32Max,
00042     Mips3, Mips4, Mips5, Mips64, Mips64r2, Mips64r3, Mips64r5, Mips64r6
00043   };
00044 
00045   enum class CPU { P5600 };
00046 
00047   // Mips architecture version
00048   MipsArchEnum MipsArchVersion;
00049 
00050   // Processor implementation (unused but required to exist by
00051   // tablegen-erated code).
00052   CPU ProcImpl;
00053 
00054   // IsLittle - The target is Little Endian
00055   bool IsLittle;
00056 
00057   // IsSoftFloat - The target does not support any floating point instructions.
00058   bool IsSoftFloat;
00059 
00060   // IsSingleFloat - The target only supports single precision float
00061   // point operations. This enable the target to use all 32 32-bit
00062   // floating point registers instead of only using even ones.
00063   bool IsSingleFloat;
00064 
00065   // IsFPXX - MIPS O32 modeless ABI.
00066   bool IsFPXX;
00067 
00068   // NoABICalls - Disable SVR4-style position-independent code.
00069   bool NoABICalls;
00070 
00071   // IsFP64bit - The target processor has 64-bit floating point registers.
00072   bool IsFP64bit;
00073 
00074   /// Are odd single-precision registers permitted?
00075   /// This corresponds to -modd-spreg and -mno-odd-spreg
00076   bool UseOddSPReg;
00077 
00078   // IsNan2008 - IEEE 754-2008 NaN encoding.
00079   bool IsNaN2008bit;
00080 
00081   // IsFP64bit - General-purpose registers are 64 bits wide
00082   bool IsGP64bit;
00083 
00084   // HasVFPU - Processor has a vector floating point unit.
00085   bool HasVFPU;
00086 
00087   // CPU supports cnMIPS (Cavium Networks Octeon CPU).
00088   bool HasCnMips;
00089 
00090   // isLinux - Target system is Linux. Is false we consider ELFOS for now.
00091   bool IsLinux;
00092 
00093   // UseSmallSection - Small section is used.
00094   bool UseSmallSection;
00095 
00096   /// Features related to the presence of specific instructions.
00097 
00098   // HasMips3_32 - The subset of MIPS-III instructions added to MIPS32
00099   bool HasMips3_32;
00100 
00101   // HasMips3_32r2 - The subset of MIPS-III instructions added to MIPS32r2
00102   bool HasMips3_32r2;
00103 
00104   // HasMips4_32 - Has the subset of MIPS-IV present in MIPS32
00105   bool HasMips4_32;
00106 
00107   // HasMips4_32r2 - Has the subset of MIPS-IV present in MIPS32r2
00108   bool HasMips4_32r2;
00109 
00110   // HasMips5_32r2 - Has the subset of MIPS-V present in MIPS32r2
00111   bool HasMips5_32r2;
00112 
00113   // InMips16 -- can process Mips16 instructions
00114   bool InMips16Mode;
00115 
00116   // Mips16 hard float
00117   bool InMips16HardFloat;
00118 
00119   // PreviousInMips16 -- the function we just processed was in Mips 16 Mode
00120   bool PreviousInMips16Mode;
00121 
00122   // InMicroMips -- can process MicroMips instructions
00123   bool InMicroMipsMode;
00124 
00125   // HasDSP, HasDSPR2, HasDSPR3 -- supports DSP ASE.
00126   bool HasDSP, HasDSPR2, HasDSPR3;
00127 
00128   // Allow mixed Mips16 and Mips32 in one source file
00129   bool AllowMixed16_32;
00130 
00131   // Optimize for space by compiling all functions as Mips 16 unless
00132   // it needs floating point. Functions needing floating point are
00133   // compiled as Mips32
00134   bool Os16;
00135 
00136   // HasMSA -- supports MSA ASE.
00137   bool HasMSA;
00138 
00139   // UseTCCInDIV -- Enables the use of trapping in the assembler.
00140   bool UseTCCInDIV;
00141 
00142   // HasEVA -- supports EVA ASE.
00143   bool HasEVA;
00144 
00145   InstrItineraryData InstrItins;
00146 
00147   // We can override the determination of whether we are in mips16 mode
00148   // as from the command line
00149   enum {NoOverride, Mips16Override, NoMips16Override} OverrideMode;
00150 
00151   const MipsTargetMachine &TM;
00152 
00153   Triple TargetTriple;
00154 
00155   const TargetSelectionDAGInfo TSInfo;
00156   std::unique_ptr<const MipsInstrInfo> InstrInfo;
00157   std::unique_ptr<const MipsFrameLowering> FrameLowering;
00158   std::unique_ptr<const MipsTargetLowering> TLInfo;
00159 
00160 public:
00161   /// This overrides the PostRAScheduler bit in the SchedModel for each CPU.
00162   bool enablePostRAScheduler() const override;
00163   void getCriticalPathRCs(RegClassVector &CriticalPathRCs) const override;
00164   CodeGenOpt::Level getOptLevelToEnablePostRAScheduler() const override;
00165 
00166   /// Only O32 and EABI supported right now.
00167   bool isABI_EABI() const;
00168   bool isABI_N64() const;
00169   bool isABI_N32() const;
00170   bool isABI_O32() const;
00171   const MipsABIInfo &getABI() const;
00172   bool isABI_FPXX() const { return isABI_O32() && IsFPXX; }
00173 
00174   /// This constructor initializes the data members to match that
00175   /// of the specified triple.
00176   MipsSubtarget(const Triple &TT, const std::string &CPU, const std::string &FS,
00177                 bool little, const MipsTargetMachine &TM);
00178 
00179   /// ParseSubtargetFeatures - Parses features string setting specified
00180   /// subtarget options.  Definition of function is auto generated by tblgen.
00181   void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
00182 
00183   bool hasMips1() const { return MipsArchVersion >= Mips1; }
00184   bool hasMips2() const { return MipsArchVersion >= Mips2; }
00185   bool hasMips3() const { return MipsArchVersion >= Mips3; }
00186   bool hasMips4() const { return MipsArchVersion >= Mips4; }
00187   bool hasMips5() const { return MipsArchVersion >= Mips5; }
00188   bool hasMips4_32() const { return HasMips4_32; }
00189   bool hasMips4_32r2() const { return HasMips4_32r2; }
00190   bool hasMips32() const {
00191     return (MipsArchVersion >= Mips32 && MipsArchVersion < Mips32Max) ||
00192            hasMips64();
00193   }
00194   bool hasMips32r2() const {
00195     return (MipsArchVersion >= Mips32r2 && MipsArchVersion < Mips32Max) ||
00196            hasMips64r2();
00197   }
00198   bool hasMips32r3() const {
00199     return (MipsArchVersion >= Mips32r3 && MipsArchVersion < Mips32Max) ||
00200            hasMips64r2();
00201   }
00202   bool hasMips32r5() const {
00203     return (MipsArchVersion >= Mips32r5 && MipsArchVersion < Mips32Max) ||
00204            hasMips64r5();
00205   }
00206   bool hasMips32r6() const {
00207     return (MipsArchVersion >= Mips32r6 && MipsArchVersion < Mips32Max) ||
00208            hasMips64r6();
00209   }
00210   bool hasMips64() const { return MipsArchVersion >= Mips64; }
00211   bool hasMips64r2() const { return MipsArchVersion >= Mips64r2; }
00212   bool hasMips64r3() const { return MipsArchVersion >= Mips64r3; }
00213   bool hasMips64r5() const { return MipsArchVersion >= Mips64r5; }
00214   bool hasMips64r6() const { return MipsArchVersion >= Mips64r6; }
00215 
00216   bool hasCnMips() const { return HasCnMips; }
00217 
00218   bool isLittle() const { return IsLittle; }
00219   bool isABICalls() const { return !NoABICalls; }
00220   bool isFPXX() const { return IsFPXX; }
00221   bool isFP64bit() const { return IsFP64bit; }
00222   bool useOddSPReg() const { return UseOddSPReg; }
00223   bool noOddSPReg() const { return !UseOddSPReg; }
00224   bool isNaN2008() const { return IsNaN2008bit; }
00225   bool isGP64bit() const { return IsGP64bit; }
00226   bool isGP32bit() const { return !IsGP64bit; }
00227   unsigned getGPRSizeInBytes() const { return isGP64bit() ? 8 : 4; }
00228   bool isSingleFloat() const { return IsSingleFloat; }
00229   bool hasVFPU() const { return HasVFPU; }
00230   bool inMips16Mode() const { return InMips16Mode; }
00231   bool inMips16ModeDefault() const {
00232     return InMips16Mode;
00233   }
00234   // Hard float for mips16 means essentially to compile as soft float
00235   // but to use a runtime library for soft float that is written with
00236   // native mips32 floating point instructions (those runtime routines
00237   // run in mips32 hard float mode).
00238   bool inMips16HardFloat() const {
00239     return inMips16Mode() && InMips16HardFloat;
00240   }
00241   bool inMicroMipsMode() const { return InMicroMipsMode; }
00242   bool inMicroMips32r6Mode() const { return InMicroMipsMode && hasMips32r6(); }
00243   bool inMicroMips64r6Mode() const { return InMicroMipsMode && hasMips64r6(); }
00244   bool hasDSP() const { return HasDSP; }
00245   bool hasDSPR2() const { return HasDSPR2; }
00246   bool hasDSPR3() const { return HasDSPR3; }
00247   bool hasMSA() const { return HasMSA; }
00248   bool hasEVA() const { return HasEVA; }
00249   bool useSmallSection() const { return UseSmallSection; }
00250 
00251   bool hasStandardEncoding() const { return !inMips16Mode(); }
00252 
00253   bool useSoftFloat() const { return IsSoftFloat; }
00254 
00255   bool enableLongBranchPass() const {
00256     return hasStandardEncoding() || allowMixed16_32();
00257   }
00258 
00259   /// Features related to the presence of specific instructions.
00260   bool hasExtractInsert() const { return !inMips16Mode() && hasMips32r2(); }
00261   bool hasMTHC1() const { return hasMips32r2(); }
00262 
00263   bool allowMixed16_32() const { return inMips16ModeDefault() |
00264                                         AllowMixed16_32; }
00265 
00266   bool os16() const { return Os16; }
00267 
00268   bool isTargetNaCl() const { return TargetTriple.isOSNaCl(); }
00269 
00270   // for now constant islands are on for the whole compilation unit but we only
00271   // really use them if in addition we are in mips16 mode
00272   static bool useConstantIslands();
00273 
00274   unsigned stackAlignment() const { return hasMips64() ? 16 : 8; }
00275 
00276   // Grab relocation model
00277   Reloc::Model getRelocationModel() const;
00278 
00279   MipsSubtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS,
00280                                                  const TargetMachine &TM);
00281 
00282   /// Does the system support unaligned memory access.
00283   ///
00284   /// MIPS32r6/MIPS64r6 require full unaligned access support but does not
00285   /// specify which component of the system provides it. Hardware, software, and
00286   /// hybrid implementations are all valid.
00287   bool systemSupportsUnalignedAccess() const { return hasMips32r6(); }
00288 
00289   // Set helper classes
00290   void setHelperClassesMips16();
00291   void setHelperClassesMipsSE();
00292 
00293   const TargetSelectionDAGInfo *getSelectionDAGInfo() const override {
00294     return &TSInfo;
00295   }
00296   const MipsInstrInfo *getInstrInfo() const override { return InstrInfo.get(); }
00297   const TargetFrameLowering *getFrameLowering() const override {
00298     return FrameLowering.get();
00299   }
00300   const MipsRegisterInfo *getRegisterInfo() const override {
00301     return &InstrInfo->getRegisterInfo();
00302   }
00303   const MipsTargetLowering *getTargetLowering() const override {
00304     return TLInfo.get();
00305   }
00306   const InstrItineraryData *getInstrItineraryData() const override {
00307     return &InstrItins;
00308   }
00309 };
00310 } // End llvm namespace
00311 
00312 #endif