LLVM API Documentation

MipsSubtarget.h
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00001 //===-- MipsSubtarget.h - Define Subtarget for the Mips ---------*- C++ -*-===//
00002 //
00003 //                     The LLVM Compiler Infrastructure
00004 //
00005 // This file is distributed under the University of Illinois Open Source
00006 // License. See LICENSE.TXT for details.
00007 //
00008 //===----------------------------------------------------------------------===//
00009 //
00010 // This file declares the Mips specific subclass of TargetSubtargetInfo.
00011 //
00012 //===----------------------------------------------------------------------===//
00013 
00014 #ifndef MIPSSUBTARGET_H
00015 #define MIPSSUBTARGET_H
00016 
00017 #include "llvm/MC/MCInstrItineraries.h"
00018 #include "llvm/Support/ErrorHandling.h"
00019 #include "llvm/Target/TargetSubtargetInfo.h"
00020 #include <string>
00021 
00022 #define GET_SUBTARGETINFO_HEADER
00023 #include "MipsGenSubtargetInfo.inc"
00024 
00025 namespace llvm {
00026 class StringRef;
00027 
00028 class MipsTargetMachine;
00029 
00030 class MipsSubtarget : public MipsGenSubtargetInfo {
00031   virtual void anchor();
00032 
00033 public:
00034   // NOTE: O64 will not be supported.
00035   enum MipsABIEnum {
00036     UnknownABI, O32, N32, N64, EABI
00037   };
00038 
00039 protected:
00040   enum MipsArchEnum { Mips32, Mips32r2, Mips4, Mips64, Mips64r2 };
00041 
00042   // Mips architecture version
00043   MipsArchEnum MipsArchVersion;
00044 
00045   // Mips supported ABIs
00046   MipsABIEnum MipsABI;
00047 
00048   // IsLittle - The target is Little Endian
00049   bool IsLittle;
00050 
00051   // IsSingleFloat - The target only supports single precision float
00052   // point operations. This enable the target to use all 32 32-bit
00053   // floating point registers instead of only using even ones.
00054   bool IsSingleFloat;
00055 
00056   // IsFP64bit - The target processor has 64-bit floating point registers.
00057   bool IsFP64bit;
00058 
00059   // IsNan2008 - IEEE 754-2008 NaN encoding.
00060   bool IsNaN2008bit;
00061 
00062   // IsFP64bit - General-purpose registers are 64 bits wide
00063   bool IsGP64bit;
00064 
00065   // HasVFPU - Processor has a vector floating point unit.
00066   bool HasVFPU;
00067 
00068   // CPU supports cnMIPS (Cavium Networks Octeon CPU).
00069   bool HasCnMips;
00070 
00071   // isLinux - Target system is Linux. Is false we consider ELFOS for now.
00072   bool IsLinux;
00073 
00074   // UseSmallSection - Small section is used.
00075   bool UseSmallSection;
00076 
00077   /// Features related to the presence of specific instructions.
00078 
00079   // HasSEInReg - SEB and SEH (signext in register) instructions.
00080   bool HasSEInReg;
00081 
00082   // HasCondMov - Conditional mov (MOVZ, MOVN) instructions.
00083   bool HasCondMov;
00084 
00085   // HasSwap - Byte and half swap instructions.
00086   bool HasSwap;
00087 
00088   // HasBitCount - Count leading '1' and '0' bits.
00089   bool HasBitCount;
00090 
00091   // HasFPIdx -- Floating point indexed load/store instructions.
00092   bool HasFPIdx;
00093 
00094   // InMips16 -- can process Mips16 instructions
00095   bool InMips16Mode;
00096 
00097   // Mips16 hard float
00098   bool InMips16HardFloat;
00099 
00100   // PreviousInMips16 -- the function we just processed was in Mips 16 Mode
00101   bool PreviousInMips16Mode;
00102 
00103   // InMicroMips -- can process MicroMips instructions
00104   bool InMicroMipsMode;
00105 
00106   // HasDSP, HasDSPR2 -- supports DSP ASE.
00107   bool HasDSP, HasDSPR2;
00108 
00109   // Allow mixed Mips16 and Mips32 in one source file
00110   bool AllowMixed16_32;
00111 
00112   // Optimize for space by compiling all functions as Mips 16 unless
00113   // it needs floating point. Functions needing floating point are
00114   // compiled as Mips32
00115   bool Os16;
00116 
00117   // HasMSA -- supports MSA ASE.
00118   bool HasMSA;
00119 
00120   InstrItineraryData InstrItins;
00121 
00122   // Relocation Model
00123   Reloc::Model RM;
00124 
00125   // We can override the determination of whether we are in mips16 mode
00126   // as from the command line
00127   enum {NoOverride, Mips16Override, NoMips16Override} OverrideMode;
00128 
00129   MipsTargetMachine *TM;
00130 
00131   Triple TargetTriple;
00132 public:
00133   virtual bool enablePostRAScheduler(CodeGenOpt::Level OptLevel,
00134                                      AntiDepBreakMode& Mode,
00135                                      RegClassVector& CriticalPathRCs) const;
00136 
00137   /// Only O32 and EABI supported right now.
00138   bool isABI_EABI() const { return MipsABI == EABI; }
00139   bool isABI_N64() const { return MipsABI == N64; }
00140   bool isABI_N32() const { return MipsABI == N32; }
00141   bool isABI_O32() const { return MipsABI == O32; }
00142   unsigned getTargetABI() const { return MipsABI; }
00143 
00144   /// This constructor initializes the data members to match that
00145   /// of the specified triple.
00146   MipsSubtarget(const std::string &TT, const std::string &CPU,
00147                 const std::string &FS, bool little, Reloc::Model RM,
00148                 MipsTargetMachine *TM);
00149 
00150   /// ParseSubtargetFeatures - Parses features string setting specified
00151   /// subtarget options.  Definition of function is auto generated by tblgen.
00152   void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
00153 
00154   bool hasMips32() const { return MipsArchVersion >= Mips32; }
00155   bool hasMips32r2() const { return MipsArchVersion == Mips32r2 ||
00156                                    MipsArchVersion == Mips64r2; }
00157   bool hasMips64() const { return MipsArchVersion >= Mips64; }
00158   bool hasMips64r2() const { return MipsArchVersion == Mips64r2; }
00159 
00160   bool hasCnMips() const { return HasCnMips; }
00161 
00162   bool isLittle() const { return IsLittle; }
00163   bool isFP64bit() const { return IsFP64bit; }
00164   bool isNaN2008() const { return IsNaN2008bit; }
00165   bool isNotFP64bit() const { return !IsFP64bit; }
00166   bool isGP64bit() const { return IsGP64bit; }
00167   bool isGP32bit() const { return !IsGP64bit; }
00168   bool isSingleFloat() const { return IsSingleFloat; }
00169   bool isNotSingleFloat() const { return !IsSingleFloat; }
00170   bool hasVFPU() const { return HasVFPU; }
00171   bool inMips16Mode() const {
00172     switch (OverrideMode) {
00173     case NoOverride:
00174       return InMips16Mode;
00175     case Mips16Override:
00176       return true;
00177     case NoMips16Override:
00178       return false;
00179     }
00180     llvm_unreachable("Unexpected mode");
00181   }
00182   bool inMips16ModeDefault() const {
00183     return InMips16Mode;
00184   }
00185   bool inMips16HardFloat() const {
00186     return inMips16Mode() && InMips16HardFloat;
00187   }
00188   bool inMicroMipsMode() const { return InMicroMipsMode; }
00189   bool hasDSP() const { return HasDSP; }
00190   bool hasDSPR2() const { return HasDSPR2; }
00191   bool hasMSA() const { return HasMSA; }
00192   bool isLinux() const { return IsLinux; }
00193   bool useSmallSection() const { return UseSmallSection; }
00194 
00195   bool hasStandardEncoding() const { return !inMips16Mode(); }
00196 
00197   bool mipsSEUsesSoftFloat() const;
00198 
00199   bool enableLongBranchPass() const {
00200     return hasStandardEncoding() || allowMixed16_32();
00201   }
00202 
00203   /// Features related to the presence of specific instructions.
00204   bool hasSEInReg()   const { return HasSEInReg; }
00205   bool hasCondMov()   const { return HasCondMov; }
00206   bool hasSwap()      const { return HasSwap; }
00207   bool hasBitCount()  const { return HasBitCount; }
00208   bool hasFPIdx()     const { return HasFPIdx; }
00209   bool hasExtractInsert() const { return !inMips16Mode() && hasMips32r2(); }
00210 
00211   const InstrItineraryData &getInstrItineraryData() const { return InstrItins; }
00212   bool allowMixed16_32() const { return inMips16ModeDefault() |
00213                                         AllowMixed16_32;}
00214 
00215   bool os16() const { return Os16;};
00216 
00217   bool isTargetNaCl() const { return TargetTriple.isOSNaCl(); }
00218   bool isNotTargetNaCl() const { return !TargetTriple.isOSNaCl(); }
00219 
00220   // for now constant islands are on for the whole compilation unit but we only
00221   // really use them if in addition we are in mips16 mode
00222   static bool useConstantIslands();
00223 
00224   unsigned stackAlignment() const { return hasMips64() ? 16 : 8; }
00225 
00226   // Grab relocation model
00227   Reloc::Model getRelocationModel() const {return RM;}
00228 
00229   /// \brief Reset the subtarget for the Mips target.
00230   void resetSubtarget(MachineFunction *MF);
00231 
00232 
00233 };
00234 } // End llvm namespace
00235 
00236 #endif