LLVM API Documentation

MipsSubtarget.h
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00001 //===-- MipsSubtarget.h - Define Subtarget for the Mips ---------*- C++ -*-===//
00002 //
00003 //                     The LLVM Compiler Infrastructure
00004 //
00005 // This file is distributed under the University of Illinois Open Source
00006 // License. See LICENSE.TXT for details.
00007 //
00008 //===----------------------------------------------------------------------===//
00009 //
00010 // This file declares the Mips specific subclass of TargetSubtargetInfo.
00011 //
00012 //===----------------------------------------------------------------------===//
00013 
00014 #ifndef LLVM_LIB_TARGET_MIPS_MIPSSUBTARGET_H
00015 #define LLVM_LIB_TARGET_MIPS_MIPSSUBTARGET_H
00016 
00017 #include "MipsFrameLowering.h"
00018 #include "MipsISelLowering.h"
00019 #include "MipsInstrInfo.h"
00020 #include "MipsSelectionDAGInfo.h"
00021 #include "llvm/IR/DataLayout.h"
00022 #include "llvm/MC/MCInstrItineraries.h"
00023 #include "llvm/Support/ErrorHandling.h"
00024 #include "llvm/Target/TargetSubtargetInfo.h"
00025 #include "MCTargetDesc/MipsABIInfo.h"
00026 #include <string>
00027 
00028 #define GET_SUBTARGETINFO_HEADER
00029 #include "MipsGenSubtargetInfo.inc"
00030 
00031 namespace llvm {
00032 class StringRef;
00033 
00034 class MipsTargetMachine;
00035 
00036 class MipsSubtarget : public MipsGenSubtargetInfo {
00037   virtual void anchor();
00038 
00039   enum MipsArchEnum {
00040     MipsDefault,
00041     Mips1, Mips2, Mips32, Mips32r2, Mips32r6, Mips3, Mips4, Mips5, Mips64,
00042     Mips64r2, Mips64r6
00043   };
00044 
00045   // Mips architecture version
00046   MipsArchEnum MipsArchVersion;
00047 
00048   // Selected ABI
00049   MipsABIInfo ABI;
00050 
00051   // IsLittle - The target is Little Endian
00052   bool IsLittle;
00053 
00054   // IsSingleFloat - The target only supports single precision float
00055   // point operations. This enable the target to use all 32 32-bit
00056   // floating point registers instead of only using even ones.
00057   bool IsSingleFloat;
00058 
00059   // IsFPXX - MIPS O32 modeless ABI.
00060   bool IsFPXX;
00061 
00062   // NoABICalls - Disable SVR4-style position-independent code.
00063   bool NoABICalls;
00064 
00065   // IsFP64bit - The target processor has 64-bit floating point registers.
00066   bool IsFP64bit;
00067 
00068   /// Are odd single-precision registers permitted?
00069   /// This corresponds to -modd-spreg and -mno-odd-spreg
00070   bool UseOddSPReg;
00071 
00072   // IsNan2008 - IEEE 754-2008 NaN encoding.
00073   bool IsNaN2008bit;
00074 
00075   // IsFP64bit - General-purpose registers are 64 bits wide
00076   bool IsGP64bit;
00077 
00078   // HasVFPU - Processor has a vector floating point unit.
00079   bool HasVFPU;
00080 
00081   // CPU supports cnMIPS (Cavium Networks Octeon CPU).
00082   bool HasCnMips;
00083 
00084   // isLinux - Target system is Linux. Is false we consider ELFOS for now.
00085   bool IsLinux;
00086 
00087   // UseSmallSection - Small section is used.
00088   bool UseSmallSection;
00089 
00090   /// Features related to the presence of specific instructions.
00091 
00092   // HasMips3_32 - The subset of MIPS-III instructions added to MIPS32
00093   bool HasMips3_32;
00094 
00095   // HasMips3_32r2 - The subset of MIPS-III instructions added to MIPS32r2
00096   bool HasMips3_32r2;
00097 
00098   // HasMips4_32 - Has the subset of MIPS-IV present in MIPS32
00099   bool HasMips4_32;
00100 
00101   // HasMips4_32r2 - Has the subset of MIPS-IV present in MIPS32r2
00102   bool HasMips4_32r2;
00103 
00104   // HasMips5_32r2 - Has the subset of MIPS-V present in MIPS32r2
00105   bool HasMips5_32r2;
00106 
00107   // InMips16 -- can process Mips16 instructions
00108   bool InMips16Mode;
00109 
00110   // Mips16 hard float
00111   bool InMips16HardFloat;
00112 
00113   // PreviousInMips16 -- the function we just processed was in Mips 16 Mode
00114   bool PreviousInMips16Mode;
00115 
00116   // InMicroMips -- can process MicroMips instructions
00117   bool InMicroMipsMode;
00118 
00119   // HasDSP, HasDSPR2 -- supports DSP ASE.
00120   bool HasDSP, HasDSPR2;
00121 
00122   // Allow mixed Mips16 and Mips32 in one source file
00123   bool AllowMixed16_32;
00124 
00125   // Optimize for space by compiling all functions as Mips 16 unless
00126   // it needs floating point. Functions needing floating point are
00127   // compiled as Mips32
00128   bool Os16;
00129 
00130   // HasMSA -- supports MSA ASE.
00131   bool HasMSA;
00132 
00133   InstrItineraryData InstrItins;
00134 
00135   // We can override the determination of whether we are in mips16 mode
00136   // as from the command line
00137   enum {NoOverride, Mips16Override, NoMips16Override} OverrideMode;
00138 
00139   const MipsTargetMachine *TM;
00140 
00141   Triple TargetTriple;
00142 
00143   const DataLayout DL; // Calculates type size & alignment
00144   const MipsSelectionDAGInfo TSInfo;
00145   std::unique_ptr<const MipsInstrInfo> InstrInfo;
00146   std::unique_ptr<const MipsFrameLowering> FrameLowering;
00147   std::unique_ptr<const MipsTargetLowering> TLInfo;
00148 
00149 public:
00150   /// This overrides the PostRAScheduler bit in the SchedModel for each CPU.
00151   bool enablePostMachineScheduler() const override;
00152   void getCriticalPathRCs(RegClassVector &CriticalPathRCs) const override;
00153   CodeGenOpt::Level getOptLevelToEnablePostRAScheduler() const override;
00154 
00155   /// Only O32 and EABI supported right now.
00156   bool isABI_EABI() const { return ABI.IsEABI(); }
00157   bool isABI_N64() const { return ABI.IsN64(); }
00158   bool isABI_N32() const { return ABI.IsN32(); }
00159   bool isABI_O32() const { return ABI.IsO32(); }
00160   bool isABI_FPXX() const { return isABI_O32() && IsFPXX; }
00161   const MipsABIInfo &getABI() const { return ABI; }
00162 
00163   /// This constructor initializes the data members to match that
00164   /// of the specified triple.
00165   MipsSubtarget(const std::string &TT, const std::string &CPU,
00166                 const std::string &FS, bool little,
00167                 const MipsTargetMachine *TM);
00168 
00169   /// ParseSubtargetFeatures - Parses features string setting specified
00170   /// subtarget options.  Definition of function is auto generated by tblgen.
00171   void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
00172 
00173   bool hasMips1() const { return MipsArchVersion >= Mips1; }
00174   bool hasMips2() const { return MipsArchVersion >= Mips2; }
00175   bool hasMips3() const { return MipsArchVersion >= Mips3; }
00176   bool hasMips4() const { return MipsArchVersion >= Mips4; }
00177   bool hasMips5() const { return MipsArchVersion >= Mips5; }
00178   bool hasMips4_32() const { return HasMips4_32; }
00179   bool hasMips4_32r2() const { return HasMips4_32r2; }
00180   bool hasMips32() const {
00181     return MipsArchVersion >= Mips32 && MipsArchVersion != Mips3 &&
00182            MipsArchVersion != Mips4 && MipsArchVersion != Mips5;
00183   }
00184   bool hasMips32r2() const {
00185     return MipsArchVersion == Mips32r2 || MipsArchVersion == Mips32r6 ||
00186            MipsArchVersion == Mips64r2 || MipsArchVersion == Mips64r6;
00187   }
00188   bool hasMips32r6() const {
00189     return MipsArchVersion == Mips32r6 || MipsArchVersion == Mips64r6;
00190   }
00191   bool hasMips64() const { return MipsArchVersion >= Mips64; }
00192   bool hasMips64r2() const {
00193     return MipsArchVersion == Mips64r2 || MipsArchVersion == Mips64r6;
00194   }
00195   bool hasMips64r6() const { return MipsArchVersion == Mips64r6; }
00196 
00197   bool hasCnMips() const { return HasCnMips; }
00198 
00199   bool isLittle() const { return IsLittle; }
00200   bool isABICalls() const { return !NoABICalls; }
00201   bool isFPXX() const { return IsFPXX; }
00202   bool isFP64bit() const { return IsFP64bit; }
00203   bool useOddSPReg() const { return UseOddSPReg; }
00204   bool noOddSPReg() const { return !UseOddSPReg; }
00205   bool isNaN2008() const { return IsNaN2008bit; }
00206   bool isGP64bit() const { return IsGP64bit; }
00207   bool isGP32bit() const { return !IsGP64bit; }
00208   unsigned getGPRSizeInBytes() const { return isGP64bit() ? 8 : 4; }
00209   bool isSingleFloat() const { return IsSingleFloat; }
00210   bool hasVFPU() const { return HasVFPU; }
00211   bool inMips16Mode() const { return InMips16Mode; }
00212   bool inMips16ModeDefault() const {
00213     return InMips16Mode;
00214   }
00215   // Hard float for mips16 means essentially to compile as soft float
00216   // but to use a runtime library for soft float that is written with
00217   // native mips32 floating point instructions (those runtime routines
00218   // run in mips32 hard float mode).
00219   bool inMips16HardFloat() const {
00220     return inMips16Mode() && InMips16HardFloat;
00221   }
00222   bool inMicroMipsMode() const { return InMicroMipsMode; }
00223   bool hasDSP() const { return HasDSP; }
00224   bool hasDSPR2() const { return HasDSPR2; }
00225   bool hasMSA() const { return HasMSA; }
00226   bool isLinux() const { return IsLinux; }
00227   bool useSmallSection() const { return UseSmallSection; }
00228 
00229   bool hasStandardEncoding() const { return !inMips16Mode(); }
00230 
00231   bool abiUsesSoftFloat() const;
00232 
00233   bool enableLongBranchPass() const {
00234     return hasStandardEncoding() || allowMixed16_32();
00235   }
00236 
00237   /// Features related to the presence of specific instructions.
00238   bool hasExtractInsert() const { return !inMips16Mode() && hasMips32r2(); }
00239   bool hasMTHC1() const { return hasMips32r2(); }
00240 
00241   bool allowMixed16_32() const { return inMips16ModeDefault() |
00242                                         AllowMixed16_32;}
00243 
00244   bool os16() const { return Os16;};
00245 
00246   bool isTargetNaCl() const { return TargetTriple.isOSNaCl(); }
00247 
00248   // for now constant islands are on for the whole compilation unit but we only
00249   // really use them if in addition we are in mips16 mode
00250   static bool useConstantIslands();
00251 
00252   unsigned stackAlignment() const { return hasMips64() ? 16 : 8; }
00253 
00254   // Grab relocation model
00255   Reloc::Model getRelocationModel() const;
00256 
00257   MipsSubtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS,
00258                                                  const TargetMachine *TM);
00259 
00260   /// Does the system support unaligned memory access.
00261   ///
00262   /// MIPS32r6/MIPS64r6 require full unaligned access support but does not
00263   /// specify which component of the system provides it. Hardware, software, and
00264   /// hybrid implementations are all valid.
00265   bool systemSupportsUnalignedAccess() const { return hasMips32r6(); }
00266 
00267   // Set helper classes
00268   void setHelperClassesMips16();
00269   void setHelperClassesMipsSE();
00270 
00271   const MipsSelectionDAGInfo *getSelectionDAGInfo() const override {
00272     return &TSInfo;
00273   }
00274   const DataLayout *getDataLayout() const override { return &DL; }
00275   const MipsInstrInfo *getInstrInfo() const override { return InstrInfo.get(); }
00276   const TargetFrameLowering *getFrameLowering() const override {
00277     return FrameLowering.get();
00278   }
00279   const MipsRegisterInfo *getRegisterInfo() const override {
00280     return &InstrInfo->getRegisterInfo();
00281   }
00282   const MipsTargetLowering *getTargetLowering() const override {
00283     return TLInfo.get();
00284   }
00285   const InstrItineraryData *getInstrItineraryData() const override {
00286     return &InstrItins;
00287   }
00288 };
00289 } // End llvm namespace
00290 
00291 #endif