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MipsSubtarget.h
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00001 //===-- MipsSubtarget.h - Define Subtarget for the Mips ---------*- C++ -*-===//
00002 //
00003 //                     The LLVM Compiler Infrastructure
00004 //
00005 // This file is distributed under the University of Illinois Open Source
00006 // License. See LICENSE.TXT for details.
00007 //
00008 //===----------------------------------------------------------------------===//
00009 //
00010 // This file declares the Mips specific subclass of TargetSubtargetInfo.
00011 //
00012 //===----------------------------------------------------------------------===//
00013 
00014 #ifndef LLVM_LIB_TARGET_MIPS_MIPSSUBTARGET_H
00015 #define LLVM_LIB_TARGET_MIPS_MIPSSUBTARGET_H
00016 
00017 #include "MCTargetDesc/MipsABIInfo.h"
00018 #include "MipsFrameLowering.h"
00019 #include "MipsISelLowering.h"
00020 #include "MipsInstrInfo.h"
00021 #include "MipsSelectionDAGInfo.h"
00022 #include "llvm/IR/DataLayout.h"
00023 #include "llvm/MC/MCInstrItineraries.h"
00024 #include "llvm/Support/ErrorHandling.h"
00025 #include "llvm/Target/TargetSubtargetInfo.h"
00026 #include <string>
00027 
00028 #define GET_SUBTARGETINFO_HEADER
00029 #include "MipsGenSubtargetInfo.inc"
00030 
00031 namespace llvm {
00032 class StringRef;
00033 
00034 class MipsTargetMachine;
00035 
00036 class MipsSubtarget : public MipsGenSubtargetInfo {
00037   virtual void anchor();
00038 
00039   enum MipsArchEnum {
00040     MipsDefault,
00041     Mips1, Mips2, Mips32, Mips32r2, Mips32r3, Mips32r5, Mips32r6, Mips32Max,
00042     Mips3, Mips4, Mips5, Mips64, Mips64r2, Mips64r3, Mips64r5, Mips64r6
00043   };
00044 
00045   // Mips architecture version
00046   MipsArchEnum MipsArchVersion;
00047 
00048   // IsLittle - The target is Little Endian
00049   bool IsLittle;
00050 
00051   // IsSoftFloat - The target does not support any floating point instructions.
00052   bool IsSoftFloat;
00053 
00054   // IsSingleFloat - The target only supports single precision float
00055   // point operations. This enable the target to use all 32 32-bit
00056   // floating point registers instead of only using even ones.
00057   bool IsSingleFloat;
00058 
00059   // IsFPXX - MIPS O32 modeless ABI.
00060   bool IsFPXX;
00061 
00062   // NoABICalls - Disable SVR4-style position-independent code.
00063   bool NoABICalls;
00064 
00065   // IsFP64bit - The target processor has 64-bit floating point registers.
00066   bool IsFP64bit;
00067 
00068   /// Are odd single-precision registers permitted?
00069   /// This corresponds to -modd-spreg and -mno-odd-spreg
00070   bool UseOddSPReg;
00071 
00072   // IsNan2008 - IEEE 754-2008 NaN encoding.
00073   bool IsNaN2008bit;
00074 
00075   // IsFP64bit - General-purpose registers are 64 bits wide
00076   bool IsGP64bit;
00077 
00078   // HasVFPU - Processor has a vector floating point unit.
00079   bool HasVFPU;
00080 
00081   // CPU supports cnMIPS (Cavium Networks Octeon CPU).
00082   bool HasCnMips;
00083 
00084   // isLinux - Target system is Linux. Is false we consider ELFOS for now.
00085   bool IsLinux;
00086 
00087   // UseSmallSection - Small section is used.
00088   bool UseSmallSection;
00089 
00090   /// Features related to the presence of specific instructions.
00091 
00092   // HasMips3_32 - The subset of MIPS-III instructions added to MIPS32
00093   bool HasMips3_32;
00094 
00095   // HasMips3_32r2 - The subset of MIPS-III instructions added to MIPS32r2
00096   bool HasMips3_32r2;
00097 
00098   // HasMips4_32 - Has the subset of MIPS-IV present in MIPS32
00099   bool HasMips4_32;
00100 
00101   // HasMips4_32r2 - Has the subset of MIPS-IV present in MIPS32r2
00102   bool HasMips4_32r2;
00103 
00104   // HasMips5_32r2 - Has the subset of MIPS-V present in MIPS32r2
00105   bool HasMips5_32r2;
00106 
00107   // InMips16 -- can process Mips16 instructions
00108   bool InMips16Mode;
00109 
00110   // Mips16 hard float
00111   bool InMips16HardFloat;
00112 
00113   // PreviousInMips16 -- the function we just processed was in Mips 16 Mode
00114   bool PreviousInMips16Mode;
00115 
00116   // InMicroMips -- can process MicroMips instructions
00117   bool InMicroMipsMode;
00118 
00119   // HasDSP, HasDSPR2 -- supports DSP ASE.
00120   bool HasDSP, HasDSPR2;
00121 
00122   // Allow mixed Mips16 and Mips32 in one source file
00123   bool AllowMixed16_32;
00124 
00125   // Optimize for space by compiling all functions as Mips 16 unless
00126   // it needs floating point. Functions needing floating point are
00127   // compiled as Mips32
00128   bool Os16;
00129 
00130   // HasMSA -- supports MSA ASE.
00131   bool HasMSA;
00132 
00133   InstrItineraryData InstrItins;
00134 
00135   // We can override the determination of whether we are in mips16 mode
00136   // as from the command line
00137   enum {NoOverride, Mips16Override, NoMips16Override} OverrideMode;
00138 
00139   const MipsTargetMachine &TM;
00140 
00141   Triple TargetTriple;
00142 
00143   const MipsSelectionDAGInfo TSInfo;
00144   std::unique_ptr<const MipsInstrInfo> InstrInfo;
00145   std::unique_ptr<const MipsFrameLowering> FrameLowering;
00146   std::unique_ptr<const MipsTargetLowering> TLInfo;
00147 
00148 public:
00149   /// This overrides the PostRAScheduler bit in the SchedModel for each CPU.
00150   bool enablePostMachineScheduler() const override;
00151   void getCriticalPathRCs(RegClassVector &CriticalPathRCs) const override;
00152   CodeGenOpt::Level getOptLevelToEnablePostRAScheduler() const override;
00153 
00154   /// Only O32 and EABI supported right now.
00155   bool isABI_EABI() const;
00156   bool isABI_N64() const;
00157   bool isABI_N32() const;
00158   bool isABI_O32() const;
00159   const MipsABIInfo &getABI() const;
00160   bool isABI_FPXX() const { return isABI_O32() && IsFPXX; }
00161 
00162   /// This constructor initializes the data members to match that
00163   /// of the specified triple.
00164   MipsSubtarget(const std::string &TT, const std::string &CPU,
00165                 const std::string &FS, bool little,
00166                 const MipsTargetMachine &TM);
00167 
00168   /// ParseSubtargetFeatures - Parses features string setting specified
00169   /// subtarget options.  Definition of function is auto generated by tblgen.
00170   void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
00171 
00172   bool hasMips1() const { return MipsArchVersion >= Mips1; }
00173   bool hasMips2() const { return MipsArchVersion >= Mips2; }
00174   bool hasMips3() const { return MipsArchVersion >= Mips3; }
00175   bool hasMips4() const { return MipsArchVersion >= Mips4; }
00176   bool hasMips5() const { return MipsArchVersion >= Mips5; }
00177   bool hasMips4_32() const { return HasMips4_32; }
00178   bool hasMips4_32r2() const { return HasMips4_32r2; }
00179   bool hasMips32() const {
00180     return (MipsArchVersion >= Mips32 && MipsArchVersion < Mips32Max) ||
00181            hasMips64();
00182   }
00183   bool hasMips32r2() const {
00184     return (MipsArchVersion >= Mips32r2 && MipsArchVersion < Mips32Max) ||
00185            hasMips64r2();
00186   }
00187   bool hasMips32r3() const {
00188     return (MipsArchVersion >= Mips32r3 && MipsArchVersion < Mips32Max) ||
00189            hasMips64r2();
00190   }
00191   bool hasMips32r5() const {
00192     return (MipsArchVersion >= Mips32r5 && MipsArchVersion < Mips32Max) ||
00193            hasMips64r2();
00194   }
00195   bool hasMips32r6() const {
00196     return (MipsArchVersion >= Mips32r6 && MipsArchVersion < Mips32Max) ||
00197            hasMips64r6();
00198   }
00199   bool hasMips64() const { return MipsArchVersion >= Mips64; }
00200   bool hasMips64r2() const { return MipsArchVersion >= Mips64r2; }
00201   bool hasMips64r3() const { return MipsArchVersion >= Mips64r3; }
00202   bool hasMips64r5() const { return MipsArchVersion >= Mips64r5; }
00203   bool hasMips64r6() const { return MipsArchVersion >= Mips64r6; }
00204 
00205   bool hasCnMips() const { return HasCnMips; }
00206 
00207   bool isLittle() const { return IsLittle; }
00208   bool isABICalls() const { return !NoABICalls; }
00209   bool isFPXX() const { return IsFPXX; }
00210   bool isFP64bit() const { return IsFP64bit; }
00211   bool useOddSPReg() const { return UseOddSPReg; }
00212   bool noOddSPReg() const { return !UseOddSPReg; }
00213   bool isNaN2008() const { return IsNaN2008bit; }
00214   bool isGP64bit() const { return IsGP64bit; }
00215   bool isGP32bit() const { return !IsGP64bit; }
00216   unsigned getGPRSizeInBytes() const { return isGP64bit() ? 8 : 4; }
00217   bool isSingleFloat() const { return IsSingleFloat; }
00218   bool hasVFPU() const { return HasVFPU; }
00219   bool inMips16Mode() const { return InMips16Mode; }
00220   bool inMips16ModeDefault() const {
00221     return InMips16Mode;
00222   }
00223   // Hard float for mips16 means essentially to compile as soft float
00224   // but to use a runtime library for soft float that is written with
00225   // native mips32 floating point instructions (those runtime routines
00226   // run in mips32 hard float mode).
00227   bool inMips16HardFloat() const {
00228     return inMips16Mode() && InMips16HardFloat;
00229   }
00230   bool inMicroMipsMode() const { return InMicroMipsMode; }
00231   bool inMicroMips32r6Mode() const { return InMicroMipsMode && hasMips32r6(); }
00232   bool hasDSP() const { return HasDSP; }
00233   bool hasDSPR2() const { return HasDSPR2; }
00234   bool hasMSA() const { return HasMSA; }
00235   bool useSmallSection() const { return UseSmallSection; }
00236 
00237   bool hasStandardEncoding() const { return !inMips16Mode(); }
00238 
00239   bool useSoftFloat() const { return IsSoftFloat; }
00240 
00241   bool enableLongBranchPass() const {
00242     return hasStandardEncoding() || allowMixed16_32();
00243   }
00244 
00245   /// Features related to the presence of specific instructions.
00246   bool hasExtractInsert() const { return !inMips16Mode() && hasMips32r2(); }
00247   bool hasMTHC1() const { return hasMips32r2(); }
00248 
00249   bool allowMixed16_32() const { return inMips16ModeDefault() |
00250                                         AllowMixed16_32; }
00251 
00252   bool os16() const { return Os16; }
00253 
00254   bool isTargetNaCl() const { return TargetTriple.isOSNaCl(); }
00255 
00256   // for now constant islands are on for the whole compilation unit but we only
00257   // really use them if in addition we are in mips16 mode
00258   static bool useConstantIslands();
00259 
00260   unsigned stackAlignment() const { return hasMips64() ? 16 : 8; }
00261 
00262   // Grab relocation model
00263   Reloc::Model getRelocationModel() const;
00264 
00265   MipsSubtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS,
00266                                                  const TargetMachine &TM);
00267 
00268   /// Does the system support unaligned memory access.
00269   ///
00270   /// MIPS32r6/MIPS64r6 require full unaligned access support but does not
00271   /// specify which component of the system provides it. Hardware, software, and
00272   /// hybrid implementations are all valid.
00273   bool systemSupportsUnalignedAccess() const { return hasMips32r6(); }
00274 
00275   // Set helper classes
00276   void setHelperClassesMips16();
00277   void setHelperClassesMipsSE();
00278 
00279   const MipsSelectionDAGInfo *getSelectionDAGInfo() const override {
00280     return &TSInfo;
00281   }
00282   const MipsInstrInfo *getInstrInfo() const override { return InstrInfo.get(); }
00283   const TargetFrameLowering *getFrameLowering() const override {
00284     return FrameLowering.get();
00285   }
00286   const MipsRegisterInfo *getRegisterInfo() const override {
00287     return &InstrInfo->getRegisterInfo();
00288   }
00289   const MipsTargetLowering *getTargetLowering() const override {
00290     return TLInfo.get();
00291   }
00292   const InstrItineraryData *getInstrItineraryData() const override {
00293     return &InstrItins;
00294   }
00295 };
00296 } // End llvm namespace
00297 
00298 #endif