LLVM  10.0.0svn
AMDHSAKernelDescriptor.h
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1 //===--- AMDHSAKernelDescriptor.h -----------------------------*- C++ -*---===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 /// AMDHSA kernel descriptor definitions. For more information, visit
11 /// https://llvm.org/docs/AMDGPUUsage.html#kernel-descriptor
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #ifndef LLVM_SUPPORT_AMDHSAKERNELDESCRIPTOR_H
16 #define LLVM_SUPPORT_AMDHSAKERNELDESCRIPTOR_H
17 
18 #include <cstddef>
19 #include <cstdint>
20 
21 // Gets offset of specified member in specified type.
22 #ifndef offsetof
23 #define offsetof(TYPE, MEMBER) ((size_t)&((TYPE*)0)->MEMBER)
24 #endif // offsetof
25 
26 // Creates enumeration entries used for packing bits into integers. Enumeration
27 // entries include bit shift amount, bit width, and bit mask.
28 #ifndef AMDHSA_BITS_ENUM_ENTRY
29 #define AMDHSA_BITS_ENUM_ENTRY(NAME, SHIFT, WIDTH) \
30  NAME ## _SHIFT = (SHIFT), \
31  NAME ## _WIDTH = (WIDTH), \
32  NAME = (((1 << (WIDTH)) - 1) << (SHIFT))
33 #endif // AMDHSA_BITS_ENUM_ENTRY
34 
35 // Gets bits for specified bit mask from specified source.
36 #ifndef AMDHSA_BITS_GET
37 #define AMDHSA_BITS_GET(SRC, MSK) ((SRC & MSK) >> MSK ## _SHIFT)
38 #endif // AMDHSA_BITS_GET
39 
40 // Sets bits for specified bit mask in specified destination.
41 #ifndef AMDHSA_BITS_SET
42 #define AMDHSA_BITS_SET(DST, MSK, VAL) \
43  DST &= ~MSK; \
44  DST |= ((VAL << MSK ## _SHIFT) & MSK)
45 #endif // AMDHSA_BITS_SET
46 
47 namespace llvm {
48 namespace amdhsa {
49 
50 // Floating point rounding modes. Must match hardware definition.
51 enum : uint8_t {
56 };
57 
58 // Floating point denorm modes. Must match hardware definition.
59 enum : uint8_t {
64 };
65 
66 // System VGPR workitem IDs. Must match hardware definition.
67 enum : uint8_t {
72 };
73 
74 // Compute program resource register 1. Must match hardware definition.
75 #define COMPUTE_PGM_RSRC1(NAME, SHIFT, WIDTH) \
76  AMDHSA_BITS_ENUM_ENTRY(COMPUTE_PGM_RSRC1_ ## NAME, SHIFT, WIDTH)
77 enum : int32_t {
78  COMPUTE_PGM_RSRC1(GRANULATED_WORKITEM_VGPR_COUNT, 0, 6),
79  COMPUTE_PGM_RSRC1(GRANULATED_WAVEFRONT_SGPR_COUNT, 6, 4),
80  COMPUTE_PGM_RSRC1(PRIORITY, 10, 2),
81  COMPUTE_PGM_RSRC1(FLOAT_ROUND_MODE_32, 12, 2),
82  COMPUTE_PGM_RSRC1(FLOAT_ROUND_MODE_16_64, 14, 2),
83  COMPUTE_PGM_RSRC1(FLOAT_DENORM_MODE_32, 16, 2),
84  COMPUTE_PGM_RSRC1(FLOAT_DENORM_MODE_16_64, 18, 2),
85  COMPUTE_PGM_RSRC1(PRIV, 20, 1),
86  COMPUTE_PGM_RSRC1(ENABLE_DX10_CLAMP, 21, 1),
87  COMPUTE_PGM_RSRC1(DEBUG_MODE, 22, 1),
88  COMPUTE_PGM_RSRC1(ENABLE_IEEE_MODE, 23, 1),
89  COMPUTE_PGM_RSRC1(BULKY, 24, 1),
90  COMPUTE_PGM_RSRC1(CDBG_USER, 25, 1),
91  COMPUTE_PGM_RSRC1(FP16_OVFL, 26, 1), // GFX9+
92  COMPUTE_PGM_RSRC1(RESERVED0, 27, 2),
93  COMPUTE_PGM_RSRC1(WGP_MODE, 29, 1), // GFX10+
94  COMPUTE_PGM_RSRC1(MEM_ORDERED, 30, 1), // GFX10+
95  COMPUTE_PGM_RSRC1(FWD_PROGRESS, 31, 1), // GFX10+
96 };
97 #undef COMPUTE_PGM_RSRC1
98 
99 // Compute program resource register 2. Must match hardware definition.
100 #define COMPUTE_PGM_RSRC2(NAME, SHIFT, WIDTH) \
101  AMDHSA_BITS_ENUM_ENTRY(COMPUTE_PGM_RSRC2_ ## NAME, SHIFT, WIDTH)
102 enum : int32_t {
103  COMPUTE_PGM_RSRC2(ENABLE_SGPR_PRIVATE_SEGMENT_WAVEFRONT_OFFSET, 0, 1),
104  COMPUTE_PGM_RSRC2(USER_SGPR_COUNT, 1, 5),
105  COMPUTE_PGM_RSRC2(ENABLE_TRAP_HANDLER, 6, 1),
106  COMPUTE_PGM_RSRC2(ENABLE_SGPR_WORKGROUP_ID_X, 7, 1),
107  COMPUTE_PGM_RSRC2(ENABLE_SGPR_WORKGROUP_ID_Y, 8, 1),
108  COMPUTE_PGM_RSRC2(ENABLE_SGPR_WORKGROUP_ID_Z, 9, 1),
109  COMPUTE_PGM_RSRC2(ENABLE_SGPR_WORKGROUP_INFO, 10, 1),
110  COMPUTE_PGM_RSRC2(ENABLE_VGPR_WORKITEM_ID, 11, 2),
111  COMPUTE_PGM_RSRC2(ENABLE_EXCEPTION_ADDRESS_WATCH, 13, 1),
112  COMPUTE_PGM_RSRC2(ENABLE_EXCEPTION_MEMORY, 14, 1),
113  COMPUTE_PGM_RSRC2(GRANULATED_LDS_SIZE, 15, 9),
114  COMPUTE_PGM_RSRC2(ENABLE_EXCEPTION_IEEE_754_FP_INVALID_OPERATION, 24, 1),
115  COMPUTE_PGM_RSRC2(ENABLE_EXCEPTION_FP_DENORMAL_SOURCE, 25, 1),
116  COMPUTE_PGM_RSRC2(ENABLE_EXCEPTION_IEEE_754_FP_DIVISION_BY_ZERO, 26, 1),
117  COMPUTE_PGM_RSRC2(ENABLE_EXCEPTION_IEEE_754_FP_OVERFLOW, 27, 1),
118  COMPUTE_PGM_RSRC2(ENABLE_EXCEPTION_IEEE_754_FP_UNDERFLOW, 28, 1),
119  COMPUTE_PGM_RSRC2(ENABLE_EXCEPTION_IEEE_754_FP_INEXACT, 29, 1),
120  COMPUTE_PGM_RSRC2(ENABLE_EXCEPTION_INT_DIVIDE_BY_ZERO, 30, 1),
121  COMPUTE_PGM_RSRC2(RESERVED0, 31, 1),
122 };
123 #undef COMPUTE_PGM_RSRC2
124 
125 // Compute program resource register 3. Must match hardware definition.
126 #define COMPUTE_PGM_RSRC3(NAME, SHIFT, WIDTH) \
127  AMDHSA_BITS_ENUM_ENTRY(COMPUTE_PGM_RSRC3_ ## NAME, SHIFT, WIDTH)
128 enum : int32_t {
129  COMPUTE_PGM_RSRC3(SHARED_VGPR_COUNT, 0, 4), // GFX10+
130  COMPUTE_PGM_RSRC3(RESERVED0, 4, 28),
131 };
132 #undef COMPUTE_PGM_RSRC3
133 
134 // Kernel code properties. Must be kept backwards compatible.
135 #define KERNEL_CODE_PROPERTY(NAME, SHIFT, WIDTH) \
136  AMDHSA_BITS_ENUM_ENTRY(KERNEL_CODE_PROPERTY_ ## NAME, SHIFT, WIDTH)
137 enum : int32_t {
138  KERNEL_CODE_PROPERTY(ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER, 0, 1),
139  KERNEL_CODE_PROPERTY(ENABLE_SGPR_DISPATCH_PTR, 1, 1),
140  KERNEL_CODE_PROPERTY(ENABLE_SGPR_QUEUE_PTR, 2, 1),
141  KERNEL_CODE_PROPERTY(ENABLE_SGPR_KERNARG_SEGMENT_PTR, 3, 1),
142  KERNEL_CODE_PROPERTY(ENABLE_SGPR_DISPATCH_ID, 4, 1),
143  KERNEL_CODE_PROPERTY(ENABLE_SGPR_FLAT_SCRATCH_INIT, 5, 1),
144  KERNEL_CODE_PROPERTY(ENABLE_SGPR_PRIVATE_SEGMENT_SIZE, 6, 1),
145  KERNEL_CODE_PROPERTY(RESERVED0, 7, 3),
146  KERNEL_CODE_PROPERTY(ENABLE_WAVEFRONT_SIZE32, 10, 1), // GFX10+
147  KERNEL_CODE_PROPERTY(RESERVED1, 11, 5),
148 };
149 #undef KERNEL_CODE_PROPERTY
150 
151 // Kernel descriptor. Must be kept backwards compatible.
155  uint8_t reserved0[8];
157  uint8_t reserved1[20];
162  uint8_t reserved2[6];
163 };
164 
165 static_assert(
166  sizeof(kernel_descriptor_t) == 64,
167  "invalid size for kernel_descriptor_t");
168 static_assert(
170  "invalid offset for group_segment_fixed_size");
171 static_assert(
173  "invalid offset for private_segment_fixed_size");
174 static_assert(
176  "invalid offset for reserved0");
177 static_assert(
179  "invalid offset for kernel_code_entry_byte_offset");
180 static_assert(
182  "invalid offset for reserved1");
183 static_assert(
185  "invalid offset for compute_pgm_rsrc3");
186 static_assert(
188  "invalid offset for compute_pgm_rsrc1");
189 static_assert(
191  "invalid offset for compute_pgm_rsrc2");
192 static_assert(
194  "invalid offset for kernel_code_properties");
195 static_assert(
197  "invalid offset for reserved2");
198 
199 } // end namespace amdhsa
200 } // end namespace llvm
201 
202 #endif // LLVM_SUPPORT_AMDHSAKERNELDESCRIPTOR_H
This class represents lattice values for constants.
Definition: AllocatorList.h:23
#define offsetof(TYPE, MEMBER)