LLVM  6.0.0svn
llvm::AArch64InstrInfo Member List

This is the complete list of members for llvm::AArch64InstrInfo, including all inherited members.

AArch64InstrInfo(const AArch64Subtarget &STI)llvm::AArch64InstrInfoexplicit
analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify=false) const overridellvm::AArch64InstrInfo
analyzeCompare(const MachineInstr &MI, unsigned &SrcReg, unsigned &SrcReg2, int &CmpMask, int &CmpValue) const overridellvm::AArch64InstrInfo
areMemAccessesTriviallyDisjoint(MachineInstr &MIa, MachineInstr &MIb, AliasAnalysis *AA=nullptr) const overridellvm::AArch64InstrInfo
canInsertSelect(const MachineBasicBlock &, ArrayRef< MachineOperand > Cond, unsigned, unsigned, int &, int &, int &) const overridellvm::AArch64InstrInfo
canOutlineWithoutLRSave(MachineBasicBlock::iterator &CallInsertionPt) constllvm::AArch64InstrInfo
convertToFlagSettingOpc(unsigned Opc, bool &Is64Bit)llvm::AArch64InstrInfoinlinestatic
copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const overridellvm::AArch64InstrInfo
copyPhysRegTuple(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, bool KillSrc, unsigned Opcode, llvm::ArrayRef< unsigned > Indices) constllvm::AArch64InstrInfo
decomposeMachineOperandsTargetFlags(unsigned TF) const overridellvm::AArch64InstrInfo
expandPostRAPseudo(MachineInstr &MI) const overridellvm::AArch64InstrInfo
foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, int FrameIndex, LiveIntervals *LIS=nullptr) const overridellvm::AArch64InstrInfo
genAlternativeCodeSequence(MachineInstr &Root, MachineCombinerPattern Pattern, SmallVectorImpl< MachineInstr *> &InsInstrs, SmallVectorImpl< MachineInstr *> &DelInstrs, DenseMap< unsigned, unsigned > &InstrIdxForVirtReg) const overridellvm::AArch64InstrInfo
getBranchDestBlock(const MachineInstr &MI) const overridellvm::AArch64InstrInfo
getInstSizeInBytes(const MachineInstr &MI) const overridellvm::AArch64InstrInfo
getMachineCombinerPatterns(MachineInstr &Root, SmallVectorImpl< MachineCombinerPattern > &Patterns) const overridellvm::AArch64InstrInfo
getMemOpBaseRegImmOfs(MachineInstr &LdSt, unsigned &BaseReg, int64_t &Offset, const TargetRegisterInfo *TRI) const overridellvm::AArch64InstrInfo
getMemOpBaseRegImmOfsOffsetOperand(MachineInstr &LdSt) constllvm::AArch64InstrInfo
getMemOpBaseRegImmOfsWidth(MachineInstr &LdSt, unsigned &BaseReg, int64_t &Offset, unsigned &Width, const TargetRegisterInfo *TRI) constllvm::AArch64InstrInfo
getMemOpInfo(unsigned Opcode, unsigned &Scale, unsigned &Width, int64_t &MinOffset, int64_t &MaxOffset) constllvm::AArch64InstrInfo
getNoop(MCInst &NopInst) const overridellvm::AArch64InstrInfo
getOutliningType(MachineInstr &MI) const overridellvm::AArch64InstrInfo
getOutlininingCandidateInfo(std::vector< std::pair< MachineBasicBlock::iterator, MachineBasicBlock::iterator >> &RepeatedSequenceLocs) const overridellvm::AArch64InstrInfo
getRegisterInfo() constllvm::AArch64InstrInfoinline
getSerializableBitmaskMachineOperandTargetFlags() const overridellvm::AArch64InstrInfo
getSerializableDirectMachineOperandTargetFlags() const overridellvm::AArch64InstrInfo
getSerializableMachineMemOperandTargetFlags() const overridellvm::AArch64InstrInfo
hasExtendedReg(const MachineInstr &MI) constllvm::AArch64InstrInfo
hasShiftedReg(const MachineInstr &MI) constllvm::AArch64InstrInfo
insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const overridellvm::AArch64InstrInfo
insertOutlinedCall(Module &M, MachineBasicBlock &MBB, MachineBasicBlock::iterator &It, MachineFunction &MF, const MachineOutlinerInfo &MInfo) const overridellvm::AArch64InstrInfo
insertOutlinerEpilogue(MachineBasicBlock &MBB, MachineFunction &MF, const MachineOutlinerInfo &MInfo) const overridellvm::AArch64InstrInfo
insertOutlinerPrologue(MachineBasicBlock &MBB, MachineFunction &MF, const MachineOutlinerInfo &MInfo) const overridellvm::AArch64InstrInfo
insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, unsigned DstReg, ArrayRef< MachineOperand > Cond, unsigned TrueReg, unsigned FalseReg) const overridellvm::AArch64InstrInfo
isAsCheapAsAMove(const MachineInstr &MI) const overridellvm::AArch64InstrInfo
isAssociativeAndCommutative(const MachineInstr &Inst) const overridellvm::AArch64InstrInfo
isBranchOffsetInRange(unsigned BranchOpc, int64_t BrOffset) const overridellvm::AArch64InstrInfo
isCandidateToMergeOrPair(MachineInstr &MI) constllvm::AArch64InstrInfo
isCoalescableExtInstr(const MachineInstr &MI, unsigned &SrcReg, unsigned &DstReg, unsigned &SubIdx) const overridellvm::AArch64InstrInfo
isExynosShiftLeftFast(const MachineInstr &MI) constllvm::AArch64InstrInfo
isFalkorShiftExtFast(const MachineInstr &MI) constllvm::AArch64InstrInfo
isFPRCopy(const MachineInstr &MI) constllvm::AArch64InstrInfo
isFunctionSafeToOutlineFrom(MachineFunction &MF, bool OutlineFromLinkOnceODRs) const overridellvm::AArch64InstrInfo
isGPRCopy(const MachineInstr &MI) constllvm::AArch64InstrInfo
isGPRZero(const MachineInstr &MI) constllvm::AArch64InstrInfo
isLdStPairSuppressed(const MachineInstr &MI) constllvm::AArch64InstrInfo
isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const overridellvm::AArch64InstrInfo
isPairableLdStInst(const MachineInstr &MI)llvm::AArch64InstrInfoinlinestatic
isScaledAddr(const MachineInstr &MI) constllvm::AArch64InstrInfo
isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const overridellvm::AArch64InstrInfo
isStridedAccess(const MachineInstr &MI) constllvm::AArch64InstrInfo
isSubregFoldable() const overridellvm::AArch64InstrInfoinline
isThroughputPattern(MachineCombinerPattern Pattern) const overridellvm::AArch64InstrInfo
isUnscaledLdSt(unsigned Opc) constllvm::AArch64InstrInfo
isUnscaledLdSt(MachineInstr &MI) constllvm::AArch64InstrInfo
loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const overridellvm::AArch64InstrInfo
optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg, unsigned SrcReg2, int CmpMask, int CmpValue, const MachineRegisterInfo *MRI) const overridellvm::AArch64InstrInfo
optimizeCondBranch(MachineInstr &MI) const overridellvm::AArch64InstrInfo
removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const overridellvm::AArch64InstrInfo
reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const overridellvm::AArch64InstrInfo
shouldClusterMemOps(MachineInstr &FirstLdSt, unsigned BaseReg1, MachineInstr &SecondLdSt, unsigned BaseReg2, unsigned NumLoads) const overridellvm::AArch64InstrInfo
storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const overridellvm::AArch64InstrInfo
suppressLdStPair(MachineInstr &MI) constllvm::AArch64InstrInfo
useMachineCombiner() const overridellvm::AArch64InstrInfo