LLVM  6.0.0svn
Public Member Functions | Static Public Member Functions | List of all members
llvm::AArch64InstrInfo Class Referencefinal

#include "Target/AArch64/AArch64InstrInfo.h"

Inheritance diagram for llvm::AArch64InstrInfo:
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Collaboration diagram for llvm::AArch64InstrInfo:
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Public Member Functions

 AArch64InstrInfo (const AArch64Subtarget &STI)
 
const AArch64RegisterInfogetRegisterInfo () const
 getRegisterInfo - TargetInstrInfo is a superset of MRegister info. More...
 
unsigned getInstSizeInBytes (const MachineInstr &MI) const override
 GetInstSize - Return the number of bytes of code the specified instruction may be. More...
 
bool isAsCheapAsAMove (const MachineInstr &MI) const override
 
bool isCoalescableExtInstr (const MachineInstr &MI, unsigned &SrcReg, unsigned &DstReg, unsigned &SubIdx) const override
 
bool areMemAccessesTriviallyDisjoint (MachineInstr &MIa, MachineInstr &MIb, AliasAnalysis *AA=nullptr) const override
 
unsigned isLoadFromStackSlot (const MachineInstr &MI, int &FrameIndex) const override
 
unsigned isStoreToStackSlot (const MachineInstr &MI, int &FrameIndex) const override
 
bool hasShiftedReg (const MachineInstr &MI) const
 Returns true if there is a shiftable register and that the shift value is non-zero. More...
 
bool hasExtendedReg (const MachineInstr &MI) const
 Returns true if there is an extendable register and that the extending value is non-zero. More...
 
bool isGPRZero (const MachineInstr &MI) const
 Does this instruction set its full destination register to zero? More...
 
bool isGPRCopy (const MachineInstr &MI) const
 Does this instruction rename a GPR without modifying bits? More...
 
bool isFPRCopy (const MachineInstr &MI) const
 Does this instruction rename an FPR without modifying bits? More...
 
bool isScaledAddr (const MachineInstr &MI) const
 Return true if this is load/store scales or extends its register offset. More...
 
bool isLdStPairSuppressed (const MachineInstr &MI) const
 Return true if pairing the given load or store is hinted to be unprofitable. More...
 
bool isStridedAccess (const MachineInstr &MI) const
 Return true if the given load or store is a strided memory access. More...
 
bool isUnscaledLdSt (unsigned Opc) const
 Return true if this is an unscaled load/store. More...
 
bool isUnscaledLdSt (MachineInstr &MI) const
 Return true if this is an unscaled load/store. More...
 
bool isCandidateToMergeOrPair (MachineInstr &MI) const
 Return true if this is a load/store that can be potentially paired/merged. More...
 
void suppressLdStPair (MachineInstr &MI) const
 Hint that pairing the given load or store is unprofitable. More...
 
bool getMemOpBaseRegImmOfs (MachineInstr &LdSt, unsigned &BaseReg, int64_t &Offset, const TargetRegisterInfo *TRI) const override
 
bool getMemOpBaseRegImmOfsWidth (MachineInstr &LdSt, unsigned &BaseReg, int64_t &Offset, unsigned &Width, const TargetRegisterInfo *TRI) const
 
MachineOperandgetMemOpBaseRegImmOfsOffsetOperand (MachineInstr &LdSt) const
 Return the immediate offset of the base register in a load/store LdSt. More...
 
bool getMemOpInfo (unsigned Opcode, unsigned &Scale, unsigned &Width, int64_t &MinOffset, int64_t &MaxOffset) const
 Returns true if opcode Opc is a memory operation. More...
 
bool shouldClusterMemOps (MachineInstr &FirstLdSt, unsigned BaseReg1, MachineInstr &SecondLdSt, unsigned BaseReg2, unsigned NumLoads) const override
 Detect opportunities for ldp/stp formation. More...
 
void copyPhysRegTuple (MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, bool KillSrc, unsigned Opcode, llvm::ArrayRef< unsigned > Indices) const
 
void copyPhysReg (MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const override
 
void storeRegToStackSlot (MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
 
void loadRegFromStackSlot (MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
 
bool isSubregFoldable () const override
 
MachineInstrfoldMemoryOperandImpl (MachineFunction &MF, MachineInstr &MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, int FrameIndex, LiveIntervals *LIS=nullptr) const override
 
bool isBranchOffsetInRange (unsigned BranchOpc, int64_t BrOffset) const override
 
MachineBasicBlockgetBranchDestBlock (const MachineInstr &MI) const override
 
bool analyzeBranch (MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify=false) const override
 
unsigned removeBranch (MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
 
unsigned insertBranch (MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
 
bool reverseBranchCondition (SmallVectorImpl< MachineOperand > &Cond) const override
 
bool canInsertSelect (const MachineBasicBlock &, ArrayRef< MachineOperand > Cond, unsigned, unsigned, int &, int &, int &) const override
 
void insertSelect (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, unsigned DstReg, ArrayRef< MachineOperand > Cond, unsigned TrueReg, unsigned FalseReg) const override
 
void getNoop (MCInst &NopInst) const override
 
bool analyzeCompare (const MachineInstr &MI, unsigned &SrcReg, unsigned &SrcReg2, int &CmpMask, int &CmpValue) const override
 analyzeCompare - For a comparison instruction, return the source registers in SrcReg and SrcReg2, and the value it compares against in CmpValue. More...
 
bool optimizeCompareInstr (MachineInstr &CmpInstr, unsigned SrcReg, unsigned SrcReg2, int CmpMask, int CmpValue, const MachineRegisterInfo *MRI) const override
 optimizeCompareInstr - Convert the instruction supplying the argument to the comparison into one that sets the zero bit in the flags register. More...
 
bool optimizeCondBranch (MachineInstr &MI) const override
 Replace csincr-branch sequence by simple conditional branch. More...
 
bool isThroughputPattern (MachineCombinerPattern Pattern) const override
 Return true when a code sequence can improve throughput. More...
 
bool getMachineCombinerPatterns (MachineInstr &Root, SmallVectorImpl< MachineCombinerPattern > &Patterns) const override
 Return true when there is potentially a faster code sequence for an instruction chain ending in Root. More...
 
bool isAssociativeAndCommutative (const MachineInstr &Inst) const override
 Return true when Inst is associative and commutative so that it can be reassociated. More...
 
void genAlternativeCodeSequence (MachineInstr &Root, MachineCombinerPattern Pattern, SmallVectorImpl< MachineInstr *> &InsInstrs, SmallVectorImpl< MachineInstr *> &DelInstrs, DenseMap< unsigned, unsigned > &InstrIdxForVirtReg) const override
 When getMachineCombinerPatterns() finds patterns, this function generates the instructions that could replace the original code sequence. More...
 
bool useMachineCombiner () const override
 AArch64 supports MachineCombiner. More...
 
bool expandPostRAPseudo (MachineInstr &MI) const override
 
std::pair< unsigned, unsigneddecomposeMachineOperandsTargetFlags (unsigned TF) const override
 
ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags () const override
 
ArrayRef< std::pair< unsigned, const char * > > getSerializableBitmaskMachineOperandTargetFlags () const override
 
ArrayRef< std::pair< MachineMemOperand::Flags, const char * > > getSerializableMachineMemOperandTargetFlags () const override
 
bool canOutlineWithoutLRSave (MachineBasicBlock::iterator &CallInsertionPt) const
 
bool isFunctionSafeToOutlineFrom (MachineFunction &MF, bool OutlineFromLinkOnceODRs) const override
 
MachineOutlinerInfo getOutlininingCandidateInfo (std::vector< std::pair< MachineBasicBlock::iterator, MachineBasicBlock::iterator >> &RepeatedSequenceLocs) const override
 
AArch64GenInstrInfo::MachineOutlinerInstrType getOutliningType (MachineInstr &MI) const override
 
void insertOutlinerEpilogue (MachineBasicBlock &MBB, MachineFunction &MF, const MachineOutlinerInfo &MInfo) const override
 
void insertOutlinerPrologue (MachineBasicBlock &MBB, MachineFunction &MF, const MachineOutlinerInfo &MInfo) const override
 
MachineBasicBlock::iterator insertOutlinedCall (Module &M, MachineBasicBlock &MBB, MachineBasicBlock::iterator &It, MachineFunction &MF, const MachineOutlinerInfo &MInfo) const override
 
bool isExynosShiftLeftFast (const MachineInstr &MI) const
 Returns true if the instruction has a shift left that can be executed more efficiently. More...
 
bool isFalkorShiftExtFast (const MachineInstr &MI) const
 Returns true if the instruction has a shift by immediate that can be executed in one cycle less. More...
 

Static Public Member Functions

static bool isPairableLdStInst (const MachineInstr &MI)
 
static unsigned convertToFlagSettingOpc (unsigned Opc, bool &Is64Bit)
 Return the opcode that set flags when possible. More...
 

Detailed Description

Definition at line 37 of file AArch64InstrInfo.h.

Constructor & Destructor Documentation

◆ AArch64InstrInfo()

AArch64InstrInfo::AArch64InstrInfo ( const AArch64Subtarget STI)
explicit

Definition at line 68 of file AArch64InstrInfo.cpp.

Member Function Documentation

◆ analyzeBranch()

bool AArch64InstrInfo::analyzeBranch ( MachineBasicBlock MBB,
MachineBasicBlock *&  TBB,
MachineBasicBlock *&  FBB,
SmallVectorImpl< MachineOperand > &  Cond,
bool  AllowModify = false 
) const
override

◆ analyzeCompare()

bool AArch64InstrInfo::analyzeCompare ( const MachineInstr MI,
unsigned SrcReg,
unsigned SrcReg2,
int &  CmpMask,
int &  CmpValue 
) const
override

analyzeCompare - For a comparison instruction, return the source registers in SrcReg and SrcReg2, and the value it compares against in CmpValue.

Return true if the comparison instruction can be analyzed.

Definition at line 1038 of file AArch64InstrInfo.cpp.

References assert(), llvm::AArch64_AM::decodeLogicalImmediate(), llvm::MachineOperand::getImm(), llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), and llvm::MachineOperand::isReg().

Referenced by isSubregFoldable().

◆ areMemAccessesTriviallyDisjoint()

bool AArch64InstrInfo::areMemAccessesTriviallyDisjoint ( MachineInstr MIa,
MachineInstr MIb,
AliasAnalysis AA = nullptr 
) const
override

◆ canInsertSelect()

bool AArch64InstrInfo::canInsertSelect ( const MachineBasicBlock MBB,
ArrayRef< MachineOperand Cond,
unsigned  TrueReg,
unsigned  FalseReg,
int &  CondCycles,
int &  TrueCycles,
int &  FalseCycles 
) const
override

◆ canOutlineWithoutLRSave()

bool AArch64InstrInfo::canOutlineWithoutLRSave ( MachineBasicBlock::iterator CallInsertionPt) const

◆ convertToFlagSettingOpc()

static unsigned llvm::AArch64InstrInfo::convertToFlagSettingOpc ( unsigned  Opc,
bool Is64Bit 
)
inlinestatic

Return the opcode that set flags when possible.

The caller is responsible for ensuring the opc has a flag setting equivalent.

Definition at line 134 of file AArch64InstrInfo.h.

References copyPhysReg(), copyPhysRegTuple(), getMemOpBaseRegImmOfs(), getMemOpBaseRegImmOfsOffsetOperand(), getMemOpBaseRegImmOfsWidth(), getMemOpInfo(), I, isCandidateToMergeOrPair(), llvm_unreachable, loadRegFromStackSlot(), shouldClusterMemOps(), storeRegToStackSlot(), and suppressLdStPair().

◆ copyPhysReg()

void AArch64InstrInfo::copyPhysReg ( MachineBasicBlock MBB,
MachineBasicBlock::iterator  I,
const DebugLoc DL,
unsigned  DestReg,
unsigned  SrcReg,
bool  KillSrc 
) const
override

◆ copyPhysRegTuple()

void AArch64InstrInfo::copyPhysRegTuple ( MachineBasicBlock MBB,
MachineBasicBlock::iterator  I,
const DebugLoc DL,
unsigned  DestReg,
unsigned  SrcReg,
bool  KillSrc,
unsigned  Opcode,
llvm::ArrayRef< unsigned Indices 
) const

◆ decomposeMachineOperandsTargetFlags()

std::pair< unsigned, unsigned > AArch64InstrInfo::decomposeMachineOperandsTargetFlags ( unsigned  TF) const
override

◆ expandPostRAPseudo()

bool AArch64InstrInfo::expandPostRAPseudo ( MachineInstr MI) const
override

◆ foldMemoryOperandImpl()

MachineInstr * AArch64InstrInfo::foldMemoryOperandImpl ( MachineFunction MF,
MachineInstr MI,
ArrayRef< unsigned Ops,
MachineBasicBlock::iterator  InsertPt,
int  FrameIndex,
LiveIntervals LIS = nullptr 
) const
override

◆ genAlternativeCodeSequence()

void AArch64InstrInfo::genAlternativeCodeSequence ( MachineInstr Root,
MachineCombinerPattern  Pattern,
SmallVectorImpl< MachineInstr *> &  InsInstrs,
SmallVectorImpl< MachineInstr *> &  DelInstrs,
DenseMap< unsigned, unsigned > &  InstrIdxForVirtReg 
) const
override

When getMachineCombinerPatterns() finds patterns, this function generates the instructions that could replace the original code sequence.

When getMachineCombinerPatterns() finds potential patterns, this function generates the instructions that could replace the original code sequence.

Definition at line 3938 of file AArch64InstrInfo.cpp.

References Accumulator, llvm::ARM_AM::add, llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addImm(), llvm::BuildMI(), llvm::MachineRegisterInfo::createVirtualRegister(), llvm::FMLAv1i32_indexed_OP1, llvm::FMLAv1i32_indexed_OP2, llvm::FMLAv1i64_indexed_OP1, llvm::FMLAv1i64_indexed_OP2, llvm::FMLAv2f32_OP1, llvm::FMLAv2f32_OP2, llvm::FMLAv2f64_OP1, llvm::FMLAv2f64_OP2, llvm::FMLAv2i32_indexed_OP1, llvm::FMLAv2i32_indexed_OP2, llvm::FMLAv2i64_indexed_OP1, llvm::FMLAv2i64_indexed_OP2, llvm::FMLAv4f32_OP1, llvm::FMLAv4f32_OP2, llvm::FMLAv4i32_indexed_OP1, llvm::FMLAv4i32_indexed_OP2, llvm::FMLSv1i32_indexed_OP2, llvm::FMLSv1i64_indexed_OP2, llvm::FMLSv2f32_OP1, llvm::FMLSv2f32_OP2, llvm::FMLSv2f64_OP1, llvm::FMLSv2f64_OP2, llvm::FMLSv2i32_indexed_OP1, llvm::FMLSv2i32_indexed_OP2, llvm::FMLSv2i64_indexed_OP1, llvm::FMLSv2i64_indexed_OP2, llvm::FMLSv4f32_OP1, llvm::FMLSv4f32_OP2, llvm::FMLSv4i32_indexed_OP1, llvm::FMLSv4i32_indexed_OP2, llvm::FMULADDD_OP1, llvm::FMULADDD_OP2, llvm::FMULADDS_OP1, llvm::FMULADDS_OP2, llvm::FMULSUBD_OP1, llvm::FMULSUBD_OP2, llvm::FMULSUBS_OP1, llvm::FMULSUBS_OP2, llvm::FNMULSUBD_OP1, llvm::FNMULSUBS_OP1, llvm::TargetInstrInfo::genAlternativeCodeSequence(), genFusedMultiply(), genMaddR(), llvm::MCInstrInfo::get(), llvm::MachineInstr::getDebugLoc(), llvm::MachineOperand::getImm(), llvm::TargetSubtargetInfo::getInstrInfo(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getRegInfo(), llvm::MachineFunction::getSubtarget(), Indexed, llvm::DenseMapBase< DerivedT, KeyT, ValueT, KeyInfoT, BucketT >::insert(), llvm::MachineOperand::isImm(), llvm::ISD::MUL, llvm::MULADDW_OP1, llvm::MULADDW_OP2, llvm::MULADDWI_OP1, llvm::MULADDX_OP1, llvm::MULADDX_OP2, llvm::MULADDXI_OP1, llvm::MULSUBW_OP1, llvm::MULSUBW_OP2, llvm::MULSUBWI_OP1, llvm::MULSUBX_OP1, llvm::MULSUBX_OP2, llvm::MULSUBXI_OP1, llvm::AArch64_AM::processLogicalImmediate(), llvm::SmallVectorTemplateBase< T, isPodLike >::push_back(), llvm::SignExtend64(), and TII.

Referenced by isSubregFoldable().

◆ getBranchDestBlock()

MachineBasicBlock * AArch64InstrInfo::getBranchDestBlock ( const MachineInstr MI) const
override

◆ getInstSizeInBytes()

unsigned AArch64InstrInfo::getInstSizeInBytes ( const MachineInstr MI) const
override

◆ getMachineCombinerPatterns()

bool AArch64InstrInfo::getMachineCombinerPatterns ( MachineInstr Root,
SmallVectorImpl< MachineCombinerPattern > &  Patterns 
) const
override

Return true when there is potentially a faster code sequence for an instruction chain ending in Root.

Return true when there is potentially a faster code sequence for an instruction chain ending in Root.

All potential patterns are listed in the Patterns array.

All potential patterns are listed in the Pattern vector. Pattern should be sorted in priority order since the pattern evaluator stops checking as soon as it finds a faster sequence.

Definition at line 3789 of file AArch64InstrInfo.cpp.

References getFMAPatterns(), llvm::TargetInstrInfo::getMachineCombinerPatterns(), and getMaddPatterns().

Referenced by isSubregFoldable().

◆ getMemOpBaseRegImmOfs()

bool AArch64InstrInfo::getMemOpBaseRegImmOfs ( MachineInstr LdSt,
unsigned BaseReg,
int64_t &  Offset,
const TargetRegisterInfo TRI 
) const
override

Definition at line 1913 of file AArch64InstrInfo.cpp.

References getMemOpBaseRegImmOfsWidth().

Referenced by convertToFlagSettingOpc().

◆ getMemOpBaseRegImmOfsOffsetOperand()

MachineOperand & AArch64InstrInfo::getMemOpBaseRegImmOfsOffsetOperand ( MachineInstr LdSt) const

Return the immediate offset of the base register in a load/store LdSt.

Definition at line 1961 of file AArch64InstrInfo.cpp.

References assert(), llvm::MachineInstr::getNumExplicitOperands(), llvm::MachineInstr::getOperand(), and llvm::MachineInstr::mayLoadOrStore().

Referenced by convertToFlagSettingOpc(), and getOutliningType().

◆ getMemOpBaseRegImmOfsWidth()

bool AArch64InstrInfo::getMemOpBaseRegImmOfsWidth ( MachineInstr LdSt,
unsigned BaseReg,
int64_t &  Offset,
unsigned Width,
const TargetRegisterInfo TRI 
) const

◆ getMemOpInfo()

bool AArch64InstrInfo::getMemOpInfo ( unsigned  Opcode,
unsigned Scale,
unsigned Width,
int64_t &  MinOffset,
int64_t &  MaxOffset 
) const

Returns true if opcode Opc is a memory operation.

If it is, set Scale, Width, MinOffset, and MaxOffset accordingly.

For unscaled instructions, Scale is set to 1.

Definition at line 1968 of file AArch64InstrInfo.cpp.

Referenced by convertToFlagSettingOpc(), getMemOpBaseRegImmOfsWidth(), and getOutliningType().

◆ getNoop()

void AArch64InstrInfo::getNoop ( MCInst NopInst) const
override

◆ getOutliningType()

AArch64GenInstrInfo::MachineOutlinerInstrType AArch64InstrInfo::getOutliningType ( MachineInstr MI) const
override

◆ getOutlininingCandidateInfo()

AArch64GenInstrInfo::MachineOutlinerInfo AArch64InstrInfo::getOutlininingCandidateInfo ( std::vector< std::pair< MachineBasicBlock::iterator, MachineBasicBlock::iterator >> &  RepeatedSequenceLocs) const
override

◆ getRegisterInfo()

const AArch64RegisterInfo& llvm::AArch64InstrInfo::getRegisterInfo ( ) const
inline

◆ getSerializableBitmaskMachineOperandTargetFlags()

ArrayRef< std::pair< unsigned, const char * > > AArch64InstrInfo::getSerializableBitmaskMachineOperandTargetFlags ( ) const
override

◆ getSerializableDirectMachineOperandTargetFlags()

ArrayRef< std::pair< unsigned, const char * > > AArch64InstrInfo::getSerializableDirectMachineOperandTargetFlags ( ) const
override

◆ getSerializableMachineMemOperandTargetFlags()

ArrayRef< std::pair< MachineMemOperand::Flags, const char * > > AArch64InstrInfo::getSerializableMachineMemOperandTargetFlags ( ) const
override

◆ hasExtendedReg()

bool AArch64InstrInfo::hasExtendedReg ( const MachineInstr MI) const

Returns true if there is an extendable register and that the extending value is non-zero.

Return true if this is this instruction has a non-zero immediate.

Definition at line 1614 of file AArch64InstrInfo.cpp.

References llvm::MachineOperand::getImm(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), and llvm::MachineOperand::isImm().

Referenced by getRegisterInfo().

◆ hasShiftedReg()

bool AArch64InstrInfo::hasShiftedReg ( const MachineInstr MI) const

Returns true if there is a shiftable register and that the shift value is non-zero.

Return true if this is this instruction has a non-zero immediate.

Definition at line 1576 of file AArch64InstrInfo.cpp.

References llvm::MachineOperand::getImm(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), and llvm::MachineOperand::isImm().

Referenced by getRegisterInfo().

◆ insertBranch()

unsigned AArch64InstrInfo::insertBranch ( MachineBasicBlock MBB,
MachineBasicBlock TBB,
MachineBasicBlock FBB,
ArrayRef< MachineOperand Cond,
const DebugLoc DL,
int *  BytesAdded = nullptr 
) const
override

◆ insertOutlinedCall()

MachineBasicBlock::iterator AArch64InstrInfo::insertOutlinedCall ( Module M,
MachineBasicBlock MBB,
MachineBasicBlock::iterator It,
MachineFunction MF,
const MachineOutlinerInfo &  MInfo 
) const
override

◆ insertOutlinerEpilogue()

void AArch64InstrInfo::insertOutlinerEpilogue ( MachineBasicBlock MBB,
MachineFunction MF,
const MachineOutlinerInfo &  MInfo 
) const
override

◆ insertOutlinerPrologue()

void AArch64InstrInfo::insertOutlinerPrologue ( MachineBasicBlock MBB,
MachineFunction MF,
const MachineOutlinerInfo &  MInfo 
) const
override

Definition at line 4910 of file AArch64InstrInfo.cpp.

Referenced by isSubregFoldable().

◆ insertSelect()

void AArch64InstrInfo::insertSelect ( MachineBasicBlock MBB,
MachineBasicBlock::iterator  MI,
const DebugLoc DL,
unsigned  DstReg,
ArrayRef< MachineOperand Cond,
unsigned  TrueReg,
unsigned  FalseReg 
) const
override

◆ isAsCheapAsAMove()

bool AArch64InstrInfo::isAsCheapAsAMove ( const MachineInstr MI) const
override

◆ isAssociativeAndCommutative()

bool AArch64InstrInfo::isAssociativeAndCommutative ( const MachineInstr Inst) const
override

Return true when Inst is associative and commutative so that it can be reassociated.

Definition at line 3393 of file AArch64InstrInfo.cpp.

References llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getParent(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getTarget(), llvm::TargetMachine::Options, and llvm::TargetOptions::UnsafeFPMath.

Referenced by isSubregFoldable().

◆ isBranchOffsetInRange()

bool AArch64InstrInfo::isBranchOffsetInRange ( unsigned  BranchOpc,
int64_t  BrOffset 
) const
override
Returns
true if a branch from an instruction with opcode BranchOpc bytes is capable of jumping to a position BrOffset bytes away.

Definition at line 168 of file AArch64InstrInfo.cpp.

References assert(), llvm::tgtok::Bits, getBranchDisplacementBits(), and llvm::isIntN().

Referenced by isSubregFoldable().

◆ isCandidateToMergeOrPair()

bool AArch64InstrInfo::isCandidateToMergeOrPair ( MachineInstr MI) const

◆ isCoalescableExtInstr()

bool AArch64InstrInfo::isCoalescableExtInstr ( const MachineInstr MI,
unsigned SrcReg,
unsigned DstReg,
unsigned SubIdx 
) const
override

◆ isExynosShiftLeftFast()

bool AArch64InstrInfo::isExynosShiftLeftFast ( const MachineInstr MI) const

◆ isFalkorShiftExtFast()

bool AArch64InstrInfo::isFalkorShiftExtFast ( const MachineInstr MI) const

◆ isFPRCopy()

bool AArch64InstrInfo::isFPRCopy ( const MachineInstr MI) const

◆ isFunctionSafeToOutlineFrom()

bool AArch64InstrInfo::isFunctionSafeToOutlineFrom ( MachineFunction MF,
bool  OutlineFromLinkOnceODRs 
) const
override

◆ isGPRCopy()

bool AArch64InstrInfo::isGPRCopy ( const MachineInstr MI) const

◆ isGPRZero()

bool AArch64InstrInfo::isGPRZero ( const MachineInstr MI) const

◆ isLdStPairSuppressed()

bool AArch64InstrInfo::isLdStPairSuppressed ( const MachineInstr MI) const

Return true if pairing the given load or store is hinted to be unprofitable.

Check all MachineMemOperands for a hint to suppress pairing.

Definition at line 1824 of file AArch64InstrInfo.cpp.

References llvm::any_of(), llvm::MachineInstr::memoperands(), and llvm::MOSuppressPair.

Referenced by areCandidatesToMergeOrPair(), getRegisterInfo(), and isCandidateToMergeOrPair().

◆ isLoadFromStackSlot()

unsigned AArch64InstrInfo::isLoadFromStackSlot ( const MachineInstr MI,
int &  FrameIndex 
) const
override

◆ isPairableLdStInst()

static bool llvm::AArch64InstrInfo::isPairableLdStInst ( const MachineInstr MI)
inlinestatic

Definition at line 100 of file AArch64InstrInfo.h.

References llvm::MachineInstr::getOpcode().

Referenced by shouldClusterMemOps().

◆ isScaledAddr()

bool AArch64InstrInfo::isScaledAddr ( const MachineInstr MI) const

Return true if this is load/store scales or extends its register offset.

This refers to scaling a dynamic index as opposed to scaled immediates. MI should be a memory op that allows scaled addressing.

Definition at line 1765 of file AArch64InstrInfo.cpp.

References llvm::MachineOperand::getImm(), llvm::AArch64_AM::getMemDoShift(), llvm::AArch64_AM::getMemExtendType(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), and llvm::AArch64_AM::UXTX.

Referenced by getRegisterInfo().

◆ isStoreToStackSlot()

unsigned AArch64InstrInfo::isStoreToStackSlot ( const MachineInstr MI,
int &  FrameIndex 
) const
override

◆ isStridedAccess()

bool AArch64InstrInfo::isStridedAccess ( const MachineInstr MI) const

Return true if the given load or store is a strided memory access.

Check all MachineMemOperands for a hint that the load/store is strided.

Definition at line 1838 of file AArch64InstrInfo.cpp.

References llvm::any_of(), llvm::MachineInstr::memoperands(), and llvm::MOStridedAccess.

Referenced by getRegisterInfo().

◆ isSubregFoldable()

bool llvm::AArch64InstrInfo::isSubregFoldable ( ) const
inlineoverride

◆ isThroughputPattern()

bool AArch64InstrInfo::isThroughputPattern ( MachineCombinerPattern  Pattern) const
override

◆ isUnscaledLdSt() [1/2]

bool AArch64InstrInfo::isUnscaledLdSt ( unsigned  Opc) const

Return true if this is an unscaled load/store.

Definition at line 1844 of file AArch64InstrInfo.cpp.

Referenced by areCandidatesToMergeOrPair(), getRegisterInfo(), isLdOffsetInRangeOfSt(), isUnscaledLdSt(), and shouldClusterMemOps().

◆ isUnscaledLdSt() [2/2]

bool AArch64InstrInfo::isUnscaledLdSt ( MachineInstr MI) const

Return true if this is an unscaled load/store.

Definition at line 1869 of file AArch64InstrInfo.cpp.

References llvm::MachineInstr::getOpcode(), and isUnscaledLdSt().

◆ loadRegFromStackSlot()

void AArch64InstrInfo::loadRegFromStackSlot ( MachineBasicBlock MBB,
MachineBasicBlock::iterator  MBBI,
unsigned  DestReg,
int  FrameIndex,
const TargetRegisterClass RC,
const TargetRegisterInfo TRI 
) const
override

◆ optimizeCompareInstr()

bool AArch64InstrInfo::optimizeCompareInstr ( MachineInstr CmpInstr,
unsigned  SrcReg,
unsigned  SrcReg2,
int  CmpMask,
int  CmpValue,
const MachineRegisterInfo MRI 
) const
override

optimizeCompareInstr - Convert the instruction supplying the argument to the comparison into one that sets the zero bit in the flags register.

Try to optimize a compare instruction.

A compare instruction is an instruction which produces AArch64::NZCV. It can be truly compare instruction when there are no uses of its destination register.

The following steps are tried in order:

  1. Convert CmpInstr into an unconditional version.
  2. Remove CmpInstr if above there is an instruction producing a needed condition code or an instruction which can be converted into such an instruction. Only comparison with zero is supported.

Definition at line 1233 of file AArch64InstrInfo.cpp.

References assert(), convertToNonFlagSettingOpc(), llvm::MachineInstr::definesRegister(), llvm::MachineInstr::eraseFromParent(), llvm::MachineInstr::findRegisterDefOperandIdx(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getReg(), llvm::MachineInstr::RemoveOperand(), llvm::MachineInstr::setDesc(), UpdateOperandRegClass(), and llvm::MachineRegisterInfo::use_nodbg_empty().

Referenced by isSubregFoldable().

◆ optimizeCondBranch()

bool AArch64InstrInfo::optimizeCondBranch ( MachineInstr MI) const
override

Replace csincr-branch sequence by simple conditional branch.

Examples:

  1. csinc w9, wzr, wzr, <condition code>
    tbnz w9, #0, 0x44
    to
    b.<inverted condition code>
  2. csinc w9, wzr, wzr, <condition code>
    tbz w9, #0, 0x44
    to
    b.<condition code>

Replace compare and branch sequence by TBZ/TBNZ instruction when the compare's constant operand is power of 2.

Examples:

and w8, w8, #0x400
cbnz w8, L1

to

tbnz w8, #10, L1
Parameters
MIConditional Branch
Returns
True when the simple conditional branch is generated

Definition at line 4471 of file AArch64InstrInfo.cpp.

References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMBB(), llvm::MachineInstrBuilder::addReg(), AK_Write, areCFlagsAccessedBetweenInstrs(), assert(), llvm::BuildMI(), llvm::AArch64_AM::decodeLogicalImmediate(), llvm::MachineRegisterInfo::def_empty(), DefMI, llvm::MachineInstr::eraseFromParent(), llvm::MachineInstr::findRegisterDefOperandIdx(), llvm::MachineInstr::getDebugLoc(), llvm::MachineOperand::getImm(), llvm::AArch64CC::getInvertedCondCode(), llvm::MachineOperand::getMBB(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getReg(), llvm::MachineFunction::getRegInfo(), getRegisterInfo(), llvm::MachineRegisterInfo::getVRegDef(), llvm::MachineRegisterInfo::hasOneDef(), llvm::MachineRegisterInfo::hasOneNonDBGUse(), llvm::MachineInstr::isCopy(), llvm::isPowerOf2_64(), llvm::TargetRegisterInfo::isVirtualRegister(), llvm_unreachable, llvm::Log2_64(), llvm::BitmaskEnumDetail::Mask(), llvm::MachineOperand::setIsKill(), and llvm::MachineOperand::setSubReg().

Referenced by isSubregFoldable().

◆ removeBranch()

unsigned AArch64InstrInfo::removeBranch ( MachineBasicBlock MBB,
int *  BytesRemoved = nullptr 
) const
override

◆ reverseBranchCondition()

bool AArch64InstrInfo::reverseBranchCondition ( SmallVectorImpl< MachineOperand > &  Cond) const
override

Definition at line 285 of file AArch64InstrInfo.cpp.

References llvm::AArch64CC::getInvertedCondCode(), and llvm_unreachable.

Referenced by isSubregFoldable().

◆ shouldClusterMemOps()

bool AArch64InstrInfo::shouldClusterMemOps ( MachineInstr FirstLdSt,
unsigned  BaseReg1,
MachineInstr SecondLdSt,
unsigned  BaseReg2,
unsigned  NumLoads 
) const
override

Detect opportunities for ldp/stp formation.

Only called for LdSt for which getMemOpBaseRegImmOfs returns true.

Definition at line 2168 of file AArch64InstrInfo.cpp.

References assert(), canPairLdStOpc(), llvm::MachineOperand::getImm(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), isCandidateToMergeOrPair(), isPairableLdStInst(), isUnscaledLdSt(), and scaleOffset().

Referenced by convertToFlagSettingOpc().

◆ storeRegToStackSlot()

void AArch64InstrInfo::storeRegToStackSlot ( MachineBasicBlock MBB,
MachineBasicBlock::iterator  MBBI,
unsigned  SrcReg,
bool  isKill,
int  FrameIndex,
const TargetRegisterClass RC,
const TargetRegisterInfo TRI 
) const
override

◆ suppressLdStPair()

void AArch64InstrInfo::suppressLdStPair ( MachineInstr MI) const

Hint that pairing the given load or store is unprofitable.

Set a flag on the first MachineMemOperand to suppress pairing.

Definition at line 1831 of file AArch64InstrInfo.cpp.

References llvm::MachineInstr::memoperands_begin(), llvm::MachineInstr::memoperands_empty(), and llvm::MOSuppressPair.

Referenced by convertToFlagSettingOpc().

◆ useMachineCombiner()

bool AArch64InstrInfo::useMachineCombiner ( ) const
override

AArch64 supports MachineCombiner.

Definition at line 3259 of file AArch64InstrInfo.cpp.

Referenced by isSubregFoldable().


The documentation for this class was generated from the following files: