LLVM  8.0.0svn
AArch64FrameLowering.cpp
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1 //===- AArch64FrameLowering.cpp - AArch64 Frame Lowering -------*- C++ -*-====//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the AArch64 implementation of TargetFrameLowering class.
11 //
12 // On AArch64, stack frames are structured as follows:
13 //
14 // The stack grows downward.
15 //
16 // All of the individual frame areas on the frame below are optional, i.e. it's
17 // possible to create a function so that the particular area isn't present
18 // in the frame.
19 //
20 // At function entry, the "frame" looks as follows:
21 //
22 // | | Higher address
23 // |-----------------------------------|
24 // | |
25 // | arguments passed on the stack |
26 // | |
27 // |-----------------------------------| <- sp
28 // | | Lower address
29 //
30 //
31 // After the prologue has run, the frame has the following general structure.
32 // Note that this doesn't depict the case where a red-zone is used. Also,
33 // technically the last frame area (VLAs) doesn't get created until in the
34 // main function body, after the prologue is run. However, it's depicted here
35 // for completeness.
36 //
37 // | | Higher address
38 // |-----------------------------------|
39 // | |
40 // | arguments passed on the stack |
41 // | |
42 // |-----------------------------------|
43 // | |
44 // | (Win64 only) varargs from reg |
45 // | |
46 // |-----------------------------------|
47 // | |
48 // | prev_fp, prev_lr |
49 // | (a.k.a. "frame record") |
50 // |-----------------------------------| <- fp(=x29)
51 // | |
52 // | other callee-saved registers |
53 // | |
54 // |-----------------------------------|
55 // |.empty.space.to.make.part.below....|
56 // |.aligned.in.case.it.needs.more.than| (size of this area is unknown at
57 // |.the.standard.16-byte.alignment....| compile time; if present)
58 // |-----------------------------------|
59 // | |
60 // | local variables of fixed size |
61 // | including spill slots |
62 // |-----------------------------------| <- bp(not defined by ABI,
63 // |.variable-sized.local.variables....| LLVM chooses X19)
64 // |.(VLAs)............................| (size of this area is unknown at
65 // |...................................| compile time)
66 // |-----------------------------------| <- sp
67 // | | Lower address
68 //
69 //
70 // To access the data in a frame, at-compile time, a constant offset must be
71 // computable from one of the pointers (fp, bp, sp) to access it. The size
72 // of the areas with a dotted background cannot be computed at compile-time
73 // if they are present, making it required to have all three of fp, bp and
74 // sp to be set up to be able to access all contents in the frame areas,
75 // assuming all of the frame areas are non-empty.
76 //
77 // For most functions, some of the frame areas are empty. For those functions,
78 // it may not be necessary to set up fp or bp:
79 // * A base pointer is definitely needed when there are both VLAs and local
80 // variables with more-than-default alignment requirements.
81 // * A frame pointer is definitely needed when there are local variables with
82 // more-than-default alignment requirements.
83 //
84 // In some cases when a base pointer is not strictly needed, it is generated
85 // anyway when offsets from the frame pointer to access local variables become
86 // so large that the offset can't be encoded in the immediate fields of loads
87 // or stores.
88 //
89 // FIXME: also explain the redzone concept.
90 // FIXME: also explain the concept of reserved call frames.
91 //
92 //===----------------------------------------------------------------------===//
93 
94 #include "AArch64FrameLowering.h"
95 #include "AArch64InstrInfo.h"
97 #include "AArch64RegisterInfo.h"
98 #include "AArch64Subtarget.h"
99 #include "AArch64TargetMachine.h"
101 #include "llvm/ADT/ScopeExit.h"
102 #include "llvm/ADT/SmallVector.h"
103 #include "llvm/ADT/Statistic.h"
118 #include "llvm/IR/Attributes.h"
119 #include "llvm/IR/CallingConv.h"
120 #include "llvm/IR/DataLayout.h"
121 #include "llvm/IR/DebugLoc.h"
122 #include "llvm/IR/Function.h"
123 #include "llvm/MC/MCDwarf.h"
125 #include "llvm/Support/Debug.h"
127 #include "llvm/Support/MathExtras.h"
131 #include <cassert>
132 #include <cstdint>
133 #include <iterator>
134 #include <vector>
135 
136 using namespace llvm;
137 
138 #define DEBUG_TYPE "frame-info"
139 
140 static cl::opt<bool> EnableRedZone("aarch64-redzone",
141  cl::desc("enable use of redzone on AArch64"),
142  cl::init(false), cl::Hidden);
143 
144 static cl::opt<bool>
145  ReverseCSRRestoreSeq("reverse-csr-restore-seq",
146  cl::desc("reverse the CSR restore sequence"),
147  cl::init(false), cl::Hidden);
148 
149 STATISTIC(NumRedZoneFunctions, "Number of functions using red zone");
150 
151 /// This is the biggest offset to the stack pointer we can encode in aarch64
152 /// instructions (without using a separate calculation and a temp register).
153 /// Note that the exception here are vector stores/loads which cannot encode any
154 /// displacements (see estimateRSStackSizeLimit(), isAArch64FrameOffsetLegal()).
155 static const unsigned DefaultSafeSPDisplacement = 255;
156 
157 /// Look at each instruction that references stack frames and return the stack
158 /// size limit beyond which some of these instructions will require a scratch
159 /// register during their expansion later.
161  // FIXME: For now, just conservatively guestimate based on unscaled indexing
162  // range. We'll end up allocating an unnecessary spill slot a lot, but
163  // realistically that's not a big deal at this stage of the game.
164  for (MachineBasicBlock &MBB : MF) {
165  for (MachineInstr &MI : MBB) {
166  if (MI.isDebugInstr() || MI.isPseudo() ||
167  MI.getOpcode() == AArch64::ADDXri ||
168  MI.getOpcode() == AArch64::ADDSXri)
169  continue;
170 
171  for (const MachineOperand &MO : MI.operands()) {
172  if (!MO.isFI())
173  continue;
174 
175  int Offset = 0;
176  if (isAArch64FrameOffsetLegal(MI, Offset, nullptr, nullptr, nullptr) ==
178  return 0;
179  }
180  }
181  }
183 }
184 
186  if (!EnableRedZone)
187  return false;
188  // Don't use the red zone if the function explicitly asks us not to.
189  // This is typically used for kernel code.
190  if (MF.getFunction().hasFnAttribute(Attribute::NoRedZone))
191  return false;
192 
193  const MachineFrameInfo &MFI = MF.getFrameInfo();
195  unsigned NumBytes = AFI->getLocalStackSize();
196 
197  return !(MFI.hasCalls() || hasFP(MF) || NumBytes > 128);
198 }
199 
200 /// hasFP - Return true if the specified function should have a dedicated frame
201 /// pointer register.
203  const MachineFrameInfo &MFI = MF.getFrameInfo();
204  const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo();
205  // Retain behavior of always omitting the FP for leaf functions when possible.
206  if (MFI.hasCalls() && MF.getTarget().Options.DisableFramePointerElim(MF))
207  return true;
208  if (MFI.hasVarSizedObjects() || MFI.isFrameAddressTaken() ||
209  MFI.hasStackMap() || MFI.hasPatchPoint() ||
210  RegInfo->needsStackRealignment(MF))
211  return true;
212  // With large callframes around we may need to use FP to access the scavenging
213  // emergency spillslot.
214  //
215  // Unfortunately some calls to hasFP() like machine verifier ->
216  // getReservedReg() -> hasFP in the middle of global isel are too early
217  // to know the max call frame size. Hopefully conservatively returning "true"
218  // in those cases is fine.
219  // DefaultSafeSPDisplacement is fine as we only emergency spill GP regs.
220  if (!MFI.isMaxCallFrameSizeComputed() ||
222  return true;
223 
224  return false;
225 }
226 
227 /// hasReservedCallFrame - Under normal circumstances, when a frame pointer is
228 /// not required, we reserve argument space for call sites in the function
229 /// immediately on entry to the current function. This eliminates the need for
230 /// add/sub sp brackets around call sites. Returns true if the call frame is
231 /// included as part of the stack frame.
232 bool
234  return !MF.getFrameInfo().hasVarSizedObjects();
235 }
236 
240  const AArch64InstrInfo *TII =
241  static_cast<const AArch64InstrInfo *>(MF.getSubtarget().getInstrInfo());
242  DebugLoc DL = I->getDebugLoc();
243  unsigned Opc = I->getOpcode();
244  bool IsDestroy = Opc == TII->getCallFrameDestroyOpcode();
245  uint64_t CalleePopAmount = IsDestroy ? I->getOperand(1).getImm() : 0;
246 
248  if (!TFI->hasReservedCallFrame(MF)) {
249  unsigned Align = getStackAlignment();
250 
251  int64_t Amount = I->getOperand(0).getImm();
252  Amount = alignTo(Amount, Align);
253  if (!IsDestroy)
254  Amount = -Amount;
255 
256  // N.b. if CalleePopAmount is valid but zero (i.e. callee would pop, but it
257  // doesn't have to pop anything), then the first operand will be zero too so
258  // this adjustment is a no-op.
259  if (CalleePopAmount == 0) {
260  // FIXME: in-function stack adjustment for calls is limited to 24-bits
261  // because there's no guaranteed temporary register available.
262  //
263  // ADD/SUB (immediate) has only LSL #0 and LSL #12 available.
264  // 1) For offset <= 12-bit, we use LSL #0
265  // 2) For 12-bit <= offset <= 24-bit, we use two instructions. One uses
266  // LSL #0, and the other uses LSL #12.
267  //
268  // Most call frames will be allocated at the start of a function so
269  // this is OK, but it is a limitation that needs dealing with.
270  assert(Amount > -0xffffff && Amount < 0xffffff && "call frame too large");
271  emitFrameOffset(MBB, I, DL, AArch64::SP, AArch64::SP, Amount, TII);
272  }
273  } else if (CalleePopAmount != 0) {
274  // If the calling convention demands that the callee pops arguments from the
275  // stack, we want to add it back if we have a reserved call frame.
276  assert(CalleePopAmount < 0xffffff && "call frame too large");
277  emitFrameOffset(MBB, I, DL, AArch64::SP, AArch64::SP, -CalleePopAmount,
278  TII);
279  }
280  return MBB.erase(I);
281 }
282 
284  // The function should be signed in the following situations:
285  // - sign-return-address=all
286  // - sign-return-address=non-leaf and the functions spills the LR
287 
288  const Function &F = MF.getFunction();
289  if (!F.hasFnAttribute("sign-return-address"))
290  return false;
291 
292  StringRef Scope = F.getFnAttribute("sign-return-address").getValueAsString();
293  if (Scope.equals("none"))
294  return false;
295 
296  if (Scope.equals("all"))
297  return true;
298 
299  assert(Scope.equals("non-leaf") && "Expected all, none or non-leaf");
300 
301  for (const auto &Info : MF.getFrameInfo().getCalleeSavedInfo())
302  if (Info.getReg() == AArch64::LR)
303  return true;
304 
305  return false;
306 }
307 
310  MachineFunction &MF = *MBB.getParent();
311  MachineFrameInfo &MFI = MF.getFrameInfo();
312  const TargetSubtargetInfo &STI = MF.getSubtarget();
313  const MCRegisterInfo *MRI = STI.getRegisterInfo();
314  const TargetInstrInfo *TII = STI.getInstrInfo();
315  DebugLoc DL = MBB.findDebugLoc(MBBI);
316 
317  // Add callee saved registers to move list.
318  const std::vector<CalleeSavedInfo> &CSI = MFI.getCalleeSavedInfo();
319  if (CSI.empty())
320  return;
321 
322  for (const auto &Info : CSI) {
323  unsigned Reg = Info.getReg();
324  int64_t Offset =
325  MFI.getObjectOffset(Info.getFrameIdx()) - getOffsetOfLocalArea();
326  unsigned DwarfReg = MRI->getDwarfRegNum(Reg, true);
327  unsigned CFIIndex = MF.addFrameInst(
328  MCCFIInstruction::createOffset(nullptr, DwarfReg, Offset));
329  BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
330  .addCFIIndex(CFIIndex)
332  }
333 }
334 
335 // Find a scratch register that we can use at the start of the prologue to
336 // re-align the stack pointer. We avoid using callee-save registers since they
337 // may appear to be free when this is called from canUseAsPrologue (during
338 // shrink wrapping), but then no longer be free when this is called from
339 // emitPrologue.
340 //
341 // FIXME: This is a bit conservative, since in the above case we could use one
342 // of the callee-save registers as a scratch temp to re-align the stack pointer,
343 // but we would then have to make sure that we were in fact saving at least one
344 // callee-save register in the prologue, which is additional complexity that
345 // doesn't seem worth the benefit.
347  MachineFunction *MF = MBB->getParent();
348 
349  // If MBB is an entry block, use X9 as the scratch register
350  if (&MF->front() == MBB)
351  return AArch64::X9;
352 
353  const AArch64Subtarget &Subtarget = MF->getSubtarget<AArch64Subtarget>();
354  const AArch64RegisterInfo &TRI = *Subtarget.getRegisterInfo();
355  LivePhysRegs LiveRegs(TRI);
356  LiveRegs.addLiveIns(*MBB);
357 
358  // Mark callee saved registers as used so we will not choose them.
359  const MCPhysReg *CSRegs = TRI.getCalleeSavedRegs(MF);
360  for (unsigned i = 0; CSRegs[i]; ++i)
361  LiveRegs.addReg(CSRegs[i]);
362 
363  // Prefer X9 since it was historically used for the prologue scratch reg.
364  const MachineRegisterInfo &MRI = MF->getRegInfo();
365  if (LiveRegs.available(MRI, AArch64::X9))
366  return AArch64::X9;
367 
368  for (unsigned Reg : AArch64::GPR64RegClass) {
369  if (LiveRegs.available(MRI, Reg))
370  return Reg;
371  }
372  return AArch64::NoRegister;
373 }
374 
376  const MachineBasicBlock &MBB) const {
377  const MachineFunction *MF = MBB.getParent();
378  MachineBasicBlock *TmpMBB = const_cast<MachineBasicBlock *>(&MBB);
379  const AArch64Subtarget &Subtarget = MF->getSubtarget<AArch64Subtarget>();
380  const AArch64RegisterInfo *RegInfo = Subtarget.getRegisterInfo();
381 
382  // Don't need a scratch register if we're not going to re-align the stack.
383  if (!RegInfo->needsStackRealignment(*MF))
384  return true;
385  // Otherwise, we can use any block as long as it has a scratch register
386  // available.
387  return findScratchNonCalleeSaveRegister(TmpMBB) != AArch64::NoRegister;
388 }
389 
391  unsigned StackSizeInBytes) {
392  const AArch64Subtarget &Subtarget = MF.getSubtarget<AArch64Subtarget>();
393  if (!Subtarget.isTargetWindows())
394  return false;
395  const Function &F = MF.getFunction();
396  // TODO: When implementing stack protectors, take that into account
397  // for the probe threshold.
398  unsigned StackProbeSize = 4096;
399  if (F.hasFnAttribute("stack-probe-size"))
400  F.getFnAttribute("stack-probe-size")
402  .getAsInteger(0, StackProbeSize);
403  return (StackSizeInBytes >= StackProbeSize) &&
404  !F.hasFnAttribute("no-stack-arg-probe");
405 }
406 
407 bool AArch64FrameLowering::shouldCombineCSRLocalStackBump(
408  MachineFunction &MF, unsigned StackBumpBytes) const {
410  const MachineFrameInfo &MFI = MF.getFrameInfo();
411  const AArch64Subtarget &Subtarget = MF.getSubtarget<AArch64Subtarget>();
412  const AArch64RegisterInfo *RegInfo = Subtarget.getRegisterInfo();
413 
414  if (AFI->getLocalStackSize() == 0)
415  return false;
416 
417  // 512 is the maximum immediate for stp/ldp that will be used for
418  // callee-save save/restores
419  if (StackBumpBytes >= 512 || windowsRequiresStackProbe(MF, StackBumpBytes))
420  return false;
421 
422  if (MFI.hasVarSizedObjects())
423  return false;
424 
425  if (RegInfo->needsStackRealignment(MF))
426  return false;
427 
428  // This isn't strictly necessary, but it simplifies things a bit since the
429  // current RedZone handling code assumes the SP is adjusted by the
430  // callee-save save/restore code.
431  if (canUseRedZone(MF))
432  return false;
433 
434  return true;
435 }
436 
437 // Convert callee-save register save/restore instruction to do stack pointer
438 // decrement/increment to allocate/deallocate the callee-save stack area by
439 // converting store/load to use pre/post increment version.
442  const DebugLoc &DL, const TargetInstrInfo *TII, int CSStackSizeInc) {
443  // Ignore instructions that do not operate on SP, i.e. shadow call stack
444  // instructions.
445  while (MBBI->getOpcode() == AArch64::STRXpost ||
446  MBBI->getOpcode() == AArch64::LDRXpre) {
447  assert(MBBI->getOperand(0).getReg() != AArch64::SP);
448  ++MBBI;
449  }
450 
451  unsigned NewOpc;
452  int Scale = 1;
453  switch (MBBI->getOpcode()) {
454  default:
455  llvm_unreachable("Unexpected callee-save save/restore opcode!");
456  case AArch64::STPXi:
457  NewOpc = AArch64::STPXpre;
458  Scale = 8;
459  break;
460  case AArch64::STPDi:
461  NewOpc = AArch64::STPDpre;
462  Scale = 8;
463  break;
464  case AArch64::STPQi:
465  NewOpc = AArch64::STPQpre;
466  Scale = 16;
467  break;
468  case AArch64::STRXui:
469  NewOpc = AArch64::STRXpre;
470  break;
471  case AArch64::STRDui:
472  NewOpc = AArch64::STRDpre;
473  break;
474  case AArch64::STRQui:
475  NewOpc = AArch64::STRQpre;
476  break;
477  case AArch64::LDPXi:
478  NewOpc = AArch64::LDPXpost;
479  Scale = 8;
480  break;
481  case AArch64::LDPDi:
482  NewOpc = AArch64::LDPDpost;
483  Scale = 8;
484  break;
485  case AArch64::LDPQi:
486  NewOpc = AArch64::LDPQpost;
487  Scale = 16;
488  break;
489  case AArch64::LDRXui:
490  NewOpc = AArch64::LDRXpost;
491  break;
492  case AArch64::LDRDui:
493  NewOpc = AArch64::LDRDpost;
494  break;
495  case AArch64::LDRQui:
496  NewOpc = AArch64::LDRQpost;
497  break;
498  }
499 
500  MachineInstrBuilder MIB = BuildMI(MBB, MBBI, DL, TII->get(NewOpc));
501  MIB.addReg(AArch64::SP, RegState::Define);
502 
503  // Copy all operands other than the immediate offset.
504  unsigned OpndIdx = 0;
505  for (unsigned OpndEnd = MBBI->getNumOperands() - 1; OpndIdx < OpndEnd;
506  ++OpndIdx)
507  MIB.add(MBBI->getOperand(OpndIdx));
508 
509  assert(MBBI->getOperand(OpndIdx).getImm() == 0 &&
510  "Unexpected immediate offset in first/last callee-save save/restore "
511  "instruction!");
512  assert(MBBI->getOperand(OpndIdx - 1).getReg() == AArch64::SP &&
513  "Unexpected base register in callee-save save/restore instruction!");
514  assert(CSStackSizeInc % Scale == 0);
515  MIB.addImm(CSStackSizeInc / Scale);
516 
517  MIB.setMIFlags(MBBI->getFlags());
518  MIB.setMemRefs(MBBI->memoperands());
519 
520  return std::prev(MBB.erase(MBBI));
521 }
522 
523 // Fixup callee-save register save/restore instructions to take into account
524 // combined SP bump by adding the local stack size to the stack offsets.
526  unsigned LocalStackSize) {
527  unsigned Opc = MI.getOpcode();
528 
529  // Ignore instructions that do not operate on SP, i.e. shadow call stack
530  // instructions.
531  if (Opc == AArch64::STRXpost || Opc == AArch64::LDRXpre) {
532  assert(MI.getOperand(0).getReg() != AArch64::SP);
533  return;
534  }
535 
536  unsigned Scale;
537  switch (Opc) {
538  case AArch64::STPXi:
539  case AArch64::STRXui:
540  case AArch64::STPDi:
541  case AArch64::STRDui:
542  case AArch64::LDPXi:
543  case AArch64::LDRXui:
544  case AArch64::LDPDi:
545  case AArch64::LDRDui:
546  Scale = 8;
547  break;
548  case AArch64::STPQi:
549  case AArch64::STRQui:
550  case AArch64::LDPQi:
551  case AArch64::LDRQui:
552  Scale = 16;
553  break;
554  default:
555  llvm_unreachable("Unexpected callee-save save/restore opcode!");
556  }
557 
558  unsigned OffsetIdx = MI.getNumExplicitOperands() - 1;
559  assert(MI.getOperand(OffsetIdx - 1).getReg() == AArch64::SP &&
560  "Unexpected base register in callee-save save/restore instruction!");
561  // Last operand is immediate offset that needs fixing.
562  MachineOperand &OffsetOpnd = MI.getOperand(OffsetIdx);
563  // All generated opcodes have scaled offsets.
564  assert(LocalStackSize % Scale == 0);
565  OffsetOpnd.setImm(OffsetOpnd.getImm() + LocalStackSize / Scale);
566 }
567 
569  MachineBasicBlock::iterator FirstSPPopI,
570  MachineBasicBlock::iterator LastPopI) {
571  // Sometimes (when we restore in the same order as we save), we can end up
572  // with code like this:
573  //
574  // ldp x26, x25, [sp]
575  // ldp x24, x23, [sp, #16]
576  // ldp x22, x21, [sp, #32]
577  // ldp x20, x19, [sp, #48]
578  // add sp, sp, #64
579  //
580  // In this case, it is always better to put the first ldp at the end, so
581  // that the load-store optimizer can run and merge the ldp and the add into
582  // a post-index ldp.
583  // If we managed to grab the first pop instruction, move it to the end.
585  MBB.splice(FirstSPPopI, &MBB, LastPopI);
586  // We should end up with something like this now:
587  //
588  // ldp x24, x23, [sp, #16]
589  // ldp x22, x21, [sp, #32]
590  // ldp x20, x19, [sp, #48]
591  // ldp x26, x25, [sp]
592  // add sp, sp, #64
593  //
594  // and the load-store optimizer can merge the last two instructions into:
595  //
596  // ldp x26, x25, [sp], #64
597  //
598 }
599 
601  MachineBasicBlock &MBB) const {
602  MachineBasicBlock::iterator MBBI = MBB.begin();
603  const MachineFrameInfo &MFI = MF.getFrameInfo();
604  const Function &F = MF.getFunction();
605  const AArch64Subtarget &Subtarget = MF.getSubtarget<AArch64Subtarget>();
606  const AArch64RegisterInfo *RegInfo = Subtarget.getRegisterInfo();
607  const TargetInstrInfo *TII = Subtarget.getInstrInfo();
608  MachineModuleInfo &MMI = MF.getMMI();
610  bool needsFrameMoves = MMI.hasDebugInfo() || F.needsUnwindTableEntry();
611  bool HasFP = hasFP(MF);
612 
613  // At this point, we're going to decide whether or not the function uses a
614  // redzone. In most cases, the function doesn't have a redzone so let's
615  // assume that's false and set it to true in the case that there's a redzone.
616  AFI->setHasRedZone(false);
617 
618  // Debug location must be unknown since the first debug location is used
619  // to determine the end of the prologue.
620  DebugLoc DL;
621 
622  if (ShouldSignReturnAddress(MF)) {
623  BuildMI(MBB, MBBI, DL, TII->get(AArch64::PACIASP))
624  .setMIFlag(MachineInstr::FrameSetup);
625  }
626 
627  // All calls are tail calls in GHC calling conv, and functions have no
628  // prologue/epilogue.
630  return;
631 
632  int NumBytes = (int)MFI.getStackSize();
633  if (!AFI->hasStackFrame() && !windowsRequiresStackProbe(MF, NumBytes)) {
634  assert(!HasFP && "unexpected function without stack frame but with FP");
635 
636  // All of the stack allocation is for locals.
637  AFI->setLocalStackSize(NumBytes);
638 
639  if (!NumBytes)
640  return;
641  // REDZONE: If the stack size is less than 128 bytes, we don't need
642  // to actually allocate.
643  if (canUseRedZone(MF)) {
644  AFI->setHasRedZone(true);
645  ++NumRedZoneFunctions;
646  } else {
647  emitFrameOffset(MBB, MBBI, DL, AArch64::SP, AArch64::SP, -NumBytes, TII,
649 
650  // Label used to tie together the PROLOG_LABEL and the MachineMoves.
651  MCSymbol *FrameLabel = MMI.getContext().createTempSymbol();
652  // Encode the stack size of the leaf function.
653  unsigned CFIIndex = MF.addFrameInst(
654  MCCFIInstruction::createDefCfaOffset(FrameLabel, -NumBytes));
655  BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
656  .addCFIIndex(CFIIndex)
658  }
659  return;
660  }
661 
662  bool IsWin64 =
664  unsigned FixedObject = IsWin64 ? alignTo(AFI->getVarArgsGPRSize(), 16) : 0;
665 
666  auto PrologueSaveSize = AFI->getCalleeSavedStackSize() + FixedObject;
667  // All of the remaining stack allocations are for locals.
668  AFI->setLocalStackSize(NumBytes - PrologueSaveSize);
669 
670  bool CombineSPBump = shouldCombineCSRLocalStackBump(MF, NumBytes);
671  if (CombineSPBump) {
672  emitFrameOffset(MBB, MBBI, DL, AArch64::SP, AArch64::SP, -NumBytes, TII,
674  NumBytes = 0;
675  } else if (PrologueSaveSize != 0) {
676  MBBI = convertCalleeSaveRestoreToSPPrePostIncDec(MBB, MBBI, DL, TII,
677  -PrologueSaveSize);
678  NumBytes -= PrologueSaveSize;
679  }
680  assert(NumBytes >= 0 && "Negative stack allocation size!?");
681 
682  // Move past the saves of the callee-saved registers, fixing up the offsets
683  // and pre-inc if we decided to combine the callee-save and local stack
684  // pointer bump above.
685  MachineBasicBlock::iterator End = MBB.end();
686  while (MBBI != End && MBBI->getFlag(MachineInstr::FrameSetup)) {
687  if (CombineSPBump)
689  ++MBBI;
690  }
691  if (HasFP) {
692  // Only set up FP if we actually need to. Frame pointer is fp =
693  // sp - fixedobject - 16.
694  int FPOffset = AFI->getCalleeSavedStackSize() - 16;
695  if (CombineSPBump)
696  FPOffset += AFI->getLocalStackSize();
697 
698  // Issue sub fp, sp, FPOffset or
699  // mov fp,sp when FPOffset is zero.
700  // Note: All stores of callee-saved registers are marked as "FrameSetup".
701  // This code marks the instruction(s) that set the FP also.
702  emitFrameOffset(MBB, MBBI, DL, AArch64::FP, AArch64::SP, FPOffset, TII,
704  }
705 
706  if (windowsRequiresStackProbe(MF, NumBytes)) {
707  uint32_t NumWords = NumBytes >> 4;
708 
709  BuildMI(MBB, MBBI, DL, TII->get(AArch64::MOVi64imm), AArch64::X15)
710  .addImm(NumWords)
712 
713  switch (MF.getTarget().getCodeModel()) {
714  case CodeModel::Tiny:
715  case CodeModel::Small:
716  case CodeModel::Medium:
717  case CodeModel::Kernel:
718  BuildMI(MBB, MBBI, DL, TII->get(AArch64::BL))
719  .addExternalSymbol("__chkstk")
720  .addReg(AArch64::X15, RegState::Implicit)
722  break;
723  case CodeModel::Large:
724  BuildMI(MBB, MBBI, DL, TII->get(AArch64::MOVaddrEXT))
725  .addReg(AArch64::X16, RegState::Define)
726  .addExternalSymbol("__chkstk")
727  .addExternalSymbol("__chkstk")
729 
730  BuildMI(MBB, MBBI, DL, TII->get(AArch64::BLR))
731  .addReg(AArch64::X16, RegState::Kill)
732  .addReg(AArch64::X15, RegState::Implicit | RegState::Define)
734  break;
735  }
736 
737  BuildMI(MBB, MBBI, DL, TII->get(AArch64::SUBXrx64), AArch64::SP)
738  .addReg(AArch64::SP, RegState::Kill)
739  .addReg(AArch64::X15, RegState::Kill)
742  NumBytes = 0;
743  }
744 
745  // Allocate space for the rest of the frame.
746  if (NumBytes) {
747  const bool NeedsRealignment = RegInfo->needsStackRealignment(MF);
748  unsigned scratchSPReg = AArch64::SP;
749 
750  if (NeedsRealignment) {
751  scratchSPReg = findScratchNonCalleeSaveRegister(&MBB);
752  assert(scratchSPReg != AArch64::NoRegister);
753  }
754 
755  // If we're a leaf function, try using the red zone.
756  if (!canUseRedZone(MF))
757  // FIXME: in the case of dynamic re-alignment, NumBytes doesn't have
758  // the correct value here, as NumBytes also includes padding bytes,
759  // which shouldn't be counted here.
760  emitFrameOffset(MBB, MBBI, DL, scratchSPReg, AArch64::SP, -NumBytes, TII,
762 
763  if (NeedsRealignment) {
764  const unsigned Alignment = MFI.getMaxAlignment();
765  const unsigned NrBitsToZero = countTrailingZeros(Alignment);
766  assert(NrBitsToZero > 1);
767  assert(scratchSPReg != AArch64::SP);
768 
769  // SUB X9, SP, NumBytes
770  // -- X9 is temporary register, so shouldn't contain any live data here,
771  // -- free to use. This is already produced by emitFrameOffset above.
772  // AND SP, X9, 0b11111...0000
773  // The logical immediates have a non-trivial encoding. The following
774  // formula computes the encoded immediate with all ones but
775  // NrBitsToZero zero bits as least significant bits.
776  uint32_t andMaskEncoded = (1 << 12) // = N
777  | ((64 - NrBitsToZero) << 6) // immr
778  | ((64 - NrBitsToZero - 1) << 0); // imms
779 
780  BuildMI(MBB, MBBI, DL, TII->get(AArch64::ANDXri), AArch64::SP)
781  .addReg(scratchSPReg, RegState::Kill)
782  .addImm(andMaskEncoded);
783  AFI->setStackRealigned(true);
784  }
785  }
786 
787  // If we need a base pointer, set it up here. It's whatever the value of the
788  // stack pointer is at this point. Any variable size objects will be allocated
789  // after this, so we can still use the base pointer to reference locals.
790  //
791  // FIXME: Clarify FrameSetup flags here.
792  // Note: Use emitFrameOffset() like above for FP if the FrameSetup flag is
793  // needed.
794  if (RegInfo->hasBasePointer(MF)) {
795  TII->copyPhysReg(MBB, MBBI, DL, RegInfo->getBaseRegister(), AArch64::SP,
796  false);
797  }
798 
799  if (needsFrameMoves) {
800  const DataLayout &TD = MF.getDataLayout();
801  const int StackGrowth = -TD.getPointerSize(0);
802  unsigned FramePtr = RegInfo->getFrameRegister(MF);
803  // An example of the prologue:
804  //
805  // .globl __foo
806  // .align 2
807  // __foo:
808  // Ltmp0:
809  // .cfi_startproc
810  // .cfi_personality 155, ___gxx_personality_v0
811  // Leh_func_begin:
812  // .cfi_lsda 16, Lexception33
813  //
814  // stp xa,bx, [sp, -#offset]!
815  // ...
816  // stp x28, x27, [sp, #offset-32]
817  // stp fp, lr, [sp, #offset-16]
818  // add fp, sp, #offset - 16
819  // sub sp, sp, #1360
820  //
821  // The Stack:
822  // +-------------------------------------------+
823  // 10000 | ........ | ........ | ........ | ........ |
824  // 10004 | ........ | ........ | ........ | ........ |
825  // +-------------------------------------------+
826  // 10008 | ........ | ........ | ........ | ........ |
827  // 1000c | ........ | ........ | ........ | ........ |
828  // +===========================================+
829  // 10010 | X28 Register |
830  // 10014 | X28 Register |
831  // +-------------------------------------------+
832  // 10018 | X27 Register |
833  // 1001c | X27 Register |
834  // +===========================================+
835  // 10020 | Frame Pointer |
836  // 10024 | Frame Pointer |
837  // +-------------------------------------------+
838  // 10028 | Link Register |
839  // 1002c | Link Register |
840  // +===========================================+
841  // 10030 | ........ | ........ | ........ | ........ |
842  // 10034 | ........ | ........ | ........ | ........ |
843  // +-------------------------------------------+
844  // 10038 | ........ | ........ | ........ | ........ |
845  // 1003c | ........ | ........ | ........ | ........ |
846  // +-------------------------------------------+
847  //
848  // [sp] = 10030 :: >>initial value<<
849  // sp = 10020 :: stp fp, lr, [sp, #-16]!
850  // fp = sp == 10020 :: mov fp, sp
851  // [sp] == 10020 :: stp x28, x27, [sp, #-16]!
852  // sp == 10010 :: >>final value<<
853  //
854  // The frame pointer (w29) points to address 10020. If we use an offset of
855  // '16' from 'w29', we get the CFI offsets of -8 for w30, -16 for w29, -24
856  // for w27, and -32 for w28:
857  //
858  // Ltmp1:
859  // .cfi_def_cfa w29, 16
860  // Ltmp2:
861  // .cfi_offset w30, -8
862  // Ltmp3:
863  // .cfi_offset w29, -16
864  // Ltmp4:
865  // .cfi_offset w27, -24
866  // Ltmp5:
867  // .cfi_offset w28, -32
868 
869  if (HasFP) {
870  // Define the current CFA rule to use the provided FP.
871  unsigned Reg = RegInfo->getDwarfRegNum(FramePtr, true);
872  unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createDefCfa(
873  nullptr, Reg, 2 * StackGrowth - FixedObject));
874  BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
875  .addCFIIndex(CFIIndex)
877  } else {
878  // Encode the stack size of the leaf function.
879  unsigned CFIIndex = MF.addFrameInst(
881  BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
882  .addCFIIndex(CFIIndex)
884  }
885 
886  // Now emit the moves for whatever callee saved regs we have (including FP,
887  // LR if those are saved).
888  emitCalleeSavedFrameMoves(MBB, MBBI);
889  }
890 }
891 
893  MachineBasicBlock &MBB) {
894  if (!ShouldSignReturnAddress(MF))
895  return;
896  const AArch64Subtarget &Subtarget = MF.getSubtarget<AArch64Subtarget>();
897  const TargetInstrInfo *TII = Subtarget.getInstrInfo();
898 
900  DebugLoc DL;
901  if (MBBI != MBB.end())
902  DL = MBBI->getDebugLoc();
903 
904  // The AUTIASP instruction assembles to a hint instruction before v8.3a so
905  // this instruction can safely used for any v8a architecture.
906  // From v8.3a onwards there are optimised authenticate LR and return
907  // instructions, namely RETA{A,B}, that can be used instead.
908  if (Subtarget.hasV8_3aOps() && MBBI != MBB.end() &&
909  MBBI->getOpcode() == AArch64::RET_ReallyLR) {
910  BuildMI(MBB, MBBI, DL, TII->get(AArch64::RETAA)).copyImplicitOps(*MBBI);
911  MBB.erase(MBBI);
912  } else {
913  BuildMI(MBB, MBBI, DL, TII->get(AArch64::AUTIASP))
914  .setMIFlag(MachineInstr::FrameDestroy);
915  }
916 }
917 
919  MachineBasicBlock &MBB) const {
921  MachineFrameInfo &MFI = MF.getFrameInfo();
922  const AArch64Subtarget &Subtarget = MF.getSubtarget<AArch64Subtarget>();
923  const TargetInstrInfo *TII = Subtarget.getInstrInfo();
924  DebugLoc DL;
925  bool IsTailCallReturn = false;
926  if (MBB.end() != MBBI) {
927  DL = MBBI->getDebugLoc();
928  unsigned RetOpcode = MBBI->getOpcode();
929  IsTailCallReturn = RetOpcode == AArch64::TCRETURNdi ||
930  RetOpcode == AArch64::TCRETURNri;
931  }
932  int NumBytes = MFI.getStackSize();
934 
935  // All calls are tail calls in GHC calling conv, and functions have no
936  // prologue/epilogue.
938  return;
939 
940  // Initial and residual are named for consistency with the prologue. Note that
941  // in the epilogue, the residual adjustment is executed first.
942  uint64_t ArgumentPopSize = 0;
943  if (IsTailCallReturn) {
944  MachineOperand &StackAdjust = MBBI->getOperand(1);
945 
946  // For a tail-call in a callee-pops-arguments environment, some or all of
947  // the stack may actually be in use for the call's arguments, this is
948  // calculated during LowerCall and consumed here...
949  ArgumentPopSize = StackAdjust.getImm();
950  } else {
951  // ... otherwise the amount to pop is *all* of the argument space,
952  // conveniently stored in the MachineFunctionInfo by
953  // LowerFormalArguments. This will, of course, be zero for the C calling
954  // convention.
955  ArgumentPopSize = AFI->getArgumentStackToRestore();
956  }
957 
958  // The stack frame should be like below,
959  //
960  // ---------------------- ---
961  // | | |
962  // | BytesInStackArgArea| CalleeArgStackSize
963  // | (NumReusableBytes) | (of tail call)
964  // | | ---
965  // | | |
966  // ---------------------| --- |
967  // | | | |
968  // | CalleeSavedReg | | |
969  // | (CalleeSavedStackSize)| | |
970  // | | | |
971  // ---------------------| | NumBytes
972  // | | StackSize (StackAdjustUp)
973  // | LocalStackSize | | |
974  // | (covering callee | | |
975  // | args) | | |
976  // | | | |
977  // ---------------------- --- ---
978  //
979  // So NumBytes = StackSize + BytesInStackArgArea - CalleeArgStackSize
980  // = StackSize + ArgumentPopSize
981  //
982  // AArch64TargetLowering::LowerCall figures out ArgumentPopSize and keeps
983  // it as the 2nd argument of AArch64ISD::TC_RETURN.
984 
985  auto Cleanup = make_scope_exit([&] { InsertReturnAddressAuth(MF, MBB); });
986 
987  bool IsWin64 =
989  unsigned FixedObject = IsWin64 ? alignTo(AFI->getVarArgsGPRSize(), 16) : 0;
990 
991  uint64_t AfterCSRPopSize = ArgumentPopSize;
992  auto PrologueSaveSize = AFI->getCalleeSavedStackSize() + FixedObject;
993  bool CombineSPBump = shouldCombineCSRLocalStackBump(MF, NumBytes);
994  // Assume we can't combine the last pop with the sp restore.
995 
996  if (!CombineSPBump && PrologueSaveSize != 0) {
997  MachineBasicBlock::iterator Pop = std::prev(MBB.getFirstTerminator());
998  // Converting the last ldp to a post-index ldp is valid only if the last
999  // ldp's offset is 0.
1000  const MachineOperand &OffsetOp = Pop->getOperand(Pop->getNumOperands() - 1);
1001  // If the offset is 0, convert it to a post-index ldp.
1002  if (OffsetOp.getImm() == 0) {
1004  PrologueSaveSize);
1005  } else {
1006  // If not, make sure to emit an add after the last ldp.
1007  // We're doing this by transfering the size to be restored from the
1008  // adjustment *before* the CSR pops to the adjustment *after* the CSR
1009  // pops.
1010  AfterCSRPopSize += PrologueSaveSize;
1011  }
1012  }
1013 
1014  // Move past the restores of the callee-saved registers.
1015  // If we plan on combining the sp bump of the local stack size and the callee
1016  // save stack size, we might need to adjust the CSR save and restore offsets.
1018  MachineBasicBlock::iterator Begin = MBB.begin();
1019  while (LastPopI != Begin) {
1020  --LastPopI;
1021  if (!LastPopI->getFlag(MachineInstr::FrameDestroy)) {
1022  ++LastPopI;
1023  break;
1024  } else if (CombineSPBump)
1026  }
1027 
1028  // If there is a single SP update, insert it before the ret and we're done.
1029  if (CombineSPBump) {
1030  emitFrameOffset(MBB, MBB.getFirstTerminator(), DL, AArch64::SP, AArch64::SP,
1031  NumBytes + AfterCSRPopSize, TII,
1033  return;
1034  }
1035 
1036  NumBytes -= PrologueSaveSize;
1037  assert(NumBytes >= 0 && "Negative stack allocation size!?");
1038 
1039  if (!hasFP(MF)) {
1040  bool RedZone = canUseRedZone(MF);
1041  // If this was a redzone leaf function, we don't need to restore the
1042  // stack pointer (but we may need to pop stack args for fastcc).
1043  if (RedZone && AfterCSRPopSize == 0)
1044  return;
1045 
1046  bool NoCalleeSaveRestore = PrologueSaveSize == 0;
1047  int StackRestoreBytes = RedZone ? 0 : NumBytes;
1048  if (NoCalleeSaveRestore)
1049  StackRestoreBytes += AfterCSRPopSize;
1050 
1051  // If we were able to combine the local stack pop with the argument pop,
1052  // then we're done.
1053  bool Done = NoCalleeSaveRestore || AfterCSRPopSize == 0;
1054 
1055  // If we're done after this, make sure to help the load store optimizer.
1056  if (Done)
1057  adaptForLdStOpt(MBB, MBB.getFirstTerminator(), LastPopI);
1058 
1059  emitFrameOffset(MBB, LastPopI, DL, AArch64::SP, AArch64::SP,
1060  StackRestoreBytes, TII, MachineInstr::FrameDestroy);
1061  if (Done)
1062  return;
1063 
1064  NumBytes = 0;
1065  }
1066 
1067  // Restore the original stack pointer.
1068  // FIXME: Rather than doing the math here, we should instead just use
1069  // non-post-indexed loads for the restores if we aren't actually going to
1070  // be able to save any instructions.
1071  if (MFI.hasVarSizedObjects() || AFI->isStackRealigned())
1072  emitFrameOffset(MBB, LastPopI, DL, AArch64::SP, AArch64::FP,
1073  -AFI->getCalleeSavedStackSize() + 16, TII,
1075  else if (NumBytes)
1076  emitFrameOffset(MBB, LastPopI, DL, AArch64::SP, AArch64::SP, NumBytes, TII,
1078 
1079  // This must be placed after the callee-save restore code because that code
1080  // assumes the SP is at the same location as it was after the callee-save save
1081  // code in the prologue.
1082  if (AfterCSRPopSize) {
1083  // Find an insertion point for the first ldp so that it goes before the
1084  // shadow call stack epilog instruction. This ensures that the restore of
1085  // lr from x18 is placed after the restore from sp.
1086  auto FirstSPPopI = MBB.getFirstTerminator();
1087  while (FirstSPPopI != Begin) {
1088  auto Prev = std::prev(FirstSPPopI);
1089  if (Prev->getOpcode() != AArch64::LDRXpre ||
1090  Prev->getOperand(0).getReg() == AArch64::SP)
1091  break;
1092  FirstSPPopI = Prev;
1093  }
1094 
1095  adaptForLdStOpt(MBB, FirstSPPopI, LastPopI);
1096 
1097  emitFrameOffset(MBB, FirstSPPopI, DL, AArch64::SP, AArch64::SP,
1098  AfterCSRPopSize, TII, MachineInstr::FrameDestroy);
1099  }
1100 }
1101 
1102 /// getFrameIndexReference - Provide a base+offset reference to an FI slot for
1103 /// debug info. It's the same as what we use for resolving the code-gen
1104 /// references for now. FIXME: This can go wrong when references are
1105 /// SP-relative and simple call frames aren't used.
1107  int FI,
1108  unsigned &FrameReg) const {
1109  return resolveFrameIndexReference(MF, FI, FrameReg);
1110 }
1111 
1113  int FI, unsigned &FrameReg,
1114  bool PreferFP) const {
1115  const MachineFrameInfo &MFI = MF.getFrameInfo();
1116  const AArch64RegisterInfo *RegInfo = static_cast<const AArch64RegisterInfo *>(
1117  MF.getSubtarget().getRegisterInfo());
1118  const AArch64FunctionInfo *AFI = MF.getInfo<AArch64FunctionInfo>();
1119  const AArch64Subtarget &Subtarget = MF.getSubtarget<AArch64Subtarget>();
1120  bool IsWin64 =
1121  Subtarget.isCallingConvWin64(MF.getFunction().getCallingConv());
1122  unsigned FixedObject = IsWin64 ? alignTo(AFI->getVarArgsGPRSize(), 16) : 0;
1123  int FPOffset = MFI.getObjectOffset(FI) + FixedObject + 16;
1124  int Offset = MFI.getObjectOffset(FI) + MFI.getStackSize();
1125  bool isFixed = MFI.isFixedObjectIndex(FI);
1126  bool isCSR = !isFixed && MFI.getObjectOffset(FI) >=
1127  -((int)AFI->getCalleeSavedStackSize());
1128 
1129  // Use frame pointer to reference fixed objects. Use it for locals if
1130  // there are VLAs or a dynamically realigned SP (and thus the SP isn't
1131  // reliable as a base). Make sure useFPForScavengingIndex() does the
1132  // right thing for the emergency spill slot.
1133  bool UseFP = false;
1134  if (AFI->hasStackFrame()) {
1135  // Note: Keeping the following as multiple 'if' statements rather than
1136  // merging to a single expression for readability.
1137  //
1138  // Argument access should always use the FP.
1139  if (isFixed) {
1140  UseFP = hasFP(MF);
1141  } else if (isCSR && RegInfo->needsStackRealignment(MF)) {
1142  // References to the CSR area must use FP if we're re-aligning the stack
1143  // since the dynamically-sized alignment padding is between the SP/BP and
1144  // the CSR area.
1145  assert(hasFP(MF) && "Re-aligned stack must have frame pointer");
1146  UseFP = true;
1147  } else if (hasFP(MF) && !RegInfo->needsStackRealignment(MF)) {
1148  // If the FPOffset is negative, we have to keep in mind that the
1149  // available offset range for negative offsets is smaller than for
1150  // positive ones. If an offset is
1151  // available via the FP and the SP, use whichever is closest.
1152  bool FPOffsetFits = FPOffset >= -256;
1153  PreferFP |= Offset > -FPOffset;
1154 
1155  if (MFI.hasVarSizedObjects()) {
1156  // If we have variable sized objects, we can use either FP or BP, as the
1157  // SP offset is unknown. We can use the base pointer if we have one and
1158  // FP is not preferred. If not, we're stuck with using FP.
1159  bool CanUseBP = RegInfo->hasBasePointer(MF);
1160  if (FPOffsetFits && CanUseBP) // Both are ok. Pick the best.
1161  UseFP = PreferFP;
1162  else if (!CanUseBP) // Can't use BP. Forced to use FP.
1163  UseFP = true;
1164  // else we can use BP and FP, but the offset from FP won't fit.
1165  // That will make us scavenge registers which we can probably avoid by
1166  // using BP. If it won't fit for BP either, we'll scavenge anyway.
1167  } else if (FPOffset >= 0) {
1168  // Use SP or FP, whichever gives us the best chance of the offset
1169  // being in range for direct access. If the FPOffset is positive,
1170  // that'll always be best, as the SP will be even further away.
1171  UseFP = true;
1172  } else {
1173  // We have the choice between FP and (SP or BP).
1174  if (FPOffsetFits && PreferFP) // If FP is the best fit, use it.
1175  UseFP = true;
1176  }
1177  }
1178  }
1179 
1180  assert(((isFixed || isCSR) || !RegInfo->needsStackRealignment(MF) || !UseFP) &&
1181  "In the presence of dynamic stack pointer realignment, "
1182  "non-argument/CSR objects cannot be accessed through the frame pointer");
1183 
1184  if (UseFP) {
1185  FrameReg = RegInfo->getFrameRegister(MF);
1186  return FPOffset;
1187  }
1188 
1189  // Use the base pointer if we have one.
1190  if (RegInfo->hasBasePointer(MF))
1191  FrameReg = RegInfo->getBaseRegister();
1192  else {
1193  assert(!MFI.hasVarSizedObjects() &&
1194  "Can't use SP when we have var sized objects.");
1195  FrameReg = AArch64::SP;
1196  // If we're using the red zone for this function, the SP won't actually
1197  // be adjusted, so the offsets will be negative. They're also all
1198  // within range of the signed 9-bit immediate instructions.
1199  if (canUseRedZone(MF))
1200  Offset -= AFI->getLocalStackSize();
1201  }
1202 
1203  return Offset;
1204 }
1205 
1206 static unsigned getPrologueDeath(MachineFunction &MF, unsigned Reg) {
1207  // Do not set a kill flag on values that are also marked as live-in. This
1208  // happens with the @llvm-returnaddress intrinsic and with arguments passed in
1209  // callee saved registers.
1210  // Omitting the kill flags is conservatively correct even if the live-in
1211  // is not used after all.
1212  bool IsLiveIn = MF.getRegInfo().isLiveIn(Reg);
1213  return getKillRegState(!IsLiveIn);
1214 }
1215 
1217  const AArch64Subtarget &Subtarget = MF.getSubtarget<AArch64Subtarget>();
1219  return Subtarget.isTargetMachO() &&
1220  !(Subtarget.getTargetLowering()->supportSwiftError() &&
1221  Attrs.hasAttrSomewhere(Attribute::SwiftError));
1222 }
1223 
1224 namespace {
1225 
1226 struct RegPairInfo {
1227  unsigned Reg1 = AArch64::NoRegister;
1228  unsigned Reg2 = AArch64::NoRegister;
1229  int FrameIdx;
1230  int Offset;
1231  enum RegType { GPR, FPR64, FPR128 } Type;
1232 
1233  RegPairInfo() = default;
1234 
1235  bool isPaired() const { return Reg2 != AArch64::NoRegister; }
1236 };
1237 
1238 } // end anonymous namespace
1239 
1241  MachineFunction &MF, const std::vector<CalleeSavedInfo> &CSI,
1243  bool &NeedShadowCallStackProlog) {
1244 
1245  if (CSI.empty())
1246  return;
1247 
1249  MachineFrameInfo &MFI = MF.getFrameInfo();
1251  unsigned Count = CSI.size();
1252  (void)CC;
1253  // MachO's compact unwind format relies on all registers being stored in
1254  // pairs.
1256  CC == CallingConv::PreserveMost ||
1257  (Count & 1) == 0) &&
1258  "Odd number of callee-saved regs to spill!");
1259  int Offset = AFI->getCalleeSavedStackSize();
1260 
1261  for (unsigned i = 0; i < Count; ++i) {
1262  RegPairInfo RPI;
1263  RPI.Reg1 = CSI[i].getReg();
1264 
1265  if (AArch64::GPR64RegClass.contains(RPI.Reg1))
1266  RPI.Type = RegPairInfo::GPR;
1267  else if (AArch64::FPR64RegClass.contains(RPI.Reg1))
1268  RPI.Type = RegPairInfo::FPR64;
1269  else if (AArch64::FPR128RegClass.contains(RPI.Reg1))
1270  RPI.Type = RegPairInfo::FPR128;
1271  else
1272  llvm_unreachable("Unsupported register class.");
1273 
1274  // Add the next reg to the pair if it is in the same register class.
1275  if (i + 1 < Count) {
1276  unsigned NextReg = CSI[i + 1].getReg();
1277  switch (RPI.Type) {
1278  case RegPairInfo::GPR:
1279  if (AArch64::GPR64RegClass.contains(NextReg))
1280  RPI.Reg2 = NextReg;
1281  break;
1282  case RegPairInfo::FPR64:
1283  if (AArch64::FPR64RegClass.contains(NextReg))
1284  RPI.Reg2 = NextReg;
1285  break;
1286  case RegPairInfo::FPR128:
1287  if (AArch64::FPR128RegClass.contains(NextReg))
1288  RPI.Reg2 = NextReg;
1289  break;
1290  }
1291  }
1292 
1293  // If either of the registers to be saved is the lr register, it means that
1294  // we also need to save lr in the shadow call stack.
1295  if ((RPI.Reg1 == AArch64::LR || RPI.Reg2 == AArch64::LR) &&
1296  MF.getFunction().hasFnAttribute(Attribute::ShadowCallStack)) {
1298  report_fatal_error("Must reserve x18 to use shadow call stack");
1299  NeedShadowCallStackProlog = true;
1300  }
1301 
1302  // GPRs and FPRs are saved in pairs of 64-bit regs. We expect the CSI
1303  // list to come in sorted by frame index so that we can issue the store
1304  // pair instructions directly. Assert if we see anything otherwise.
1305  //
1306  // The order of the registers in the list is controlled by
1307  // getCalleeSavedRegs(), so they will always be in-order, as well.
1308  assert((!RPI.isPaired() ||
1309  (CSI[i].getFrameIdx() + 1 == CSI[i + 1].getFrameIdx())) &&
1310  "Out of order callee saved regs!");
1311 
1312  // MachO's compact unwind format relies on all registers being stored in
1313  // adjacent register pairs.
1315  CC == CallingConv::PreserveMost ||
1316  (RPI.isPaired() &&
1317  ((RPI.Reg1 == AArch64::LR && RPI.Reg2 == AArch64::FP) ||
1318  RPI.Reg1 + 1 == RPI.Reg2))) &&
1319  "Callee-save registers not saved as adjacent register pair!");
1320 
1321  RPI.FrameIdx = CSI[i].getFrameIdx();
1322 
1323  int Scale = RPI.Type == RegPairInfo::FPR128 ? 16 : 8;
1324  Offset -= RPI.isPaired() ? 2 * Scale : Scale;
1325 
1326  // Round up size of non-pair to pair size if we need to pad the
1327  // callee-save area to ensure 16-byte alignment.
1328  if (AFI->hasCalleeSaveStackFreeSpace() &&
1329  RPI.Type != RegPairInfo::FPR128 && !RPI.isPaired()) {
1330  Offset -= 8;
1331  assert(Offset % 16 == 0);
1332  assert(MFI.getObjectAlignment(RPI.FrameIdx) <= 16);
1333  MFI.setObjectAlignment(RPI.FrameIdx, 16);
1334  }
1335 
1336  assert(Offset % Scale == 0);
1337  RPI.Offset = Offset / Scale;
1338  assert((RPI.Offset >= -64 && RPI.Offset <= 63) &&
1339  "Offset out of bounds for LDP/STP immediate");
1340 
1341  RegPairs.push_back(RPI);
1342  if (RPI.isPaired())
1343  ++i;
1344  }
1345 }
1346 
1349  const std::vector<CalleeSavedInfo> &CSI,
1350  const TargetRegisterInfo *TRI) const {
1351  MachineFunction &MF = *MBB.getParent();
1352  const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
1353  DebugLoc DL;
1354  SmallVector<RegPairInfo, 8> RegPairs;
1355 
1356  bool NeedShadowCallStackProlog = false;
1357  computeCalleeSaveRegisterPairs(MF, CSI, TRI, RegPairs,
1358  NeedShadowCallStackProlog);
1359  const MachineRegisterInfo &MRI = MF.getRegInfo();
1360 
1361  if (NeedShadowCallStackProlog) {
1362  // Shadow call stack prolog: str x30, [x18], #8
1363  BuildMI(MBB, MI, DL, TII.get(AArch64::STRXpost))
1364  .addReg(AArch64::X18, RegState::Define)
1365  .addReg(AArch64::LR)
1366  .addReg(AArch64::X18)
1367  .addImm(8)
1369 
1370  // This instruction also makes x18 live-in to the entry block.
1371  MBB.addLiveIn(AArch64::X18);
1372  }
1373 
1374  for (auto RPII = RegPairs.rbegin(), RPIE = RegPairs.rend(); RPII != RPIE;
1375  ++RPII) {
1376  RegPairInfo RPI = *RPII;
1377  unsigned Reg1 = RPI.Reg1;
1378  unsigned Reg2 = RPI.Reg2;
1379  unsigned StrOpc;
1380 
1381  // Issue sequence of spills for cs regs. The first spill may be converted
1382  // to a pre-decrement store later by emitPrologue if the callee-save stack
1383  // area allocation can't be combined with the local stack area allocation.
1384  // For example:
1385  // stp x22, x21, [sp, #0] // addImm(+0)
1386  // stp x20, x19, [sp, #16] // addImm(+2)
1387  // stp fp, lr, [sp, #32] // addImm(+4)
1388  // Rationale: This sequence saves uop updates compared to a sequence of
1389  // pre-increment spills like stp xi,xj,[sp,#-16]!
1390  // Note: Similar rationale and sequence for restores in epilog.
1391  unsigned Size, Align;
1392  switch (RPI.Type) {
1393  case RegPairInfo::GPR:
1394  StrOpc = RPI.isPaired() ? AArch64::STPXi : AArch64::STRXui;
1395  Size = 8;
1396  Align = 8;
1397  break;
1398  case RegPairInfo::FPR64:
1399  StrOpc = RPI.isPaired() ? AArch64::STPDi : AArch64::STRDui;
1400  Size = 8;
1401  Align = 8;
1402  break;
1403  case RegPairInfo::FPR128:
1404  StrOpc = RPI.isPaired() ? AArch64::STPQi : AArch64::STRQui;
1405  Size = 16;
1406  Align = 16;
1407  break;
1408  }
1409  LLVM_DEBUG(dbgs() << "CSR spill: (" << printReg(Reg1, TRI);
1410  if (RPI.isPaired()) dbgs() << ", " << printReg(Reg2, TRI);
1411  dbgs() << ") -> fi#(" << RPI.FrameIdx;
1412  if (RPI.isPaired()) dbgs() << ", " << RPI.FrameIdx + 1;
1413  dbgs() << ")\n");
1414 
1415  MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(StrOpc));
1416  if (!MRI.isReserved(Reg1))
1417  MBB.addLiveIn(Reg1);
1418  if (RPI.isPaired()) {
1419  if (!MRI.isReserved(Reg2))
1420  MBB.addLiveIn(Reg2);
1421  MIB.addReg(Reg2, getPrologueDeath(MF, Reg2));
1422  MIB.addMemOperand(MF.getMachineMemOperand(
1423  MachinePointerInfo::getFixedStack(MF, RPI.FrameIdx + 1),
1424  MachineMemOperand::MOStore, Size, Align));
1425  }
1426  MIB.addReg(Reg1, getPrologueDeath(MF, Reg1))
1427  .addReg(AArch64::SP)
1428  .addImm(RPI.Offset) // [sp, #offset*scale],
1429  // where factor*scale is implicit
1430  .setMIFlag(MachineInstr::FrameSetup);
1431  MIB.addMemOperand(MF.getMachineMemOperand(
1432  MachinePointerInfo::getFixedStack(MF, RPI.FrameIdx),
1433  MachineMemOperand::MOStore, Size, Align));
1434  }
1435  return true;
1436 }
1437 
1440  std::vector<CalleeSavedInfo> &CSI,
1441  const TargetRegisterInfo *TRI) const {
1442  MachineFunction &MF = *MBB.getParent();
1443  const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
1444  DebugLoc DL;
1445  SmallVector<RegPairInfo, 8> RegPairs;
1446 
1447  if (MI != MBB.end())
1448  DL = MI->getDebugLoc();
1449 
1450  bool NeedShadowCallStackProlog = false;
1451  computeCalleeSaveRegisterPairs(MF, CSI, TRI, RegPairs,
1452  NeedShadowCallStackProlog);
1453 
1454  auto EmitMI = [&](const RegPairInfo &RPI) {
1455  unsigned Reg1 = RPI.Reg1;
1456  unsigned Reg2 = RPI.Reg2;
1457 
1458  // Issue sequence of restores for cs regs. The last restore may be converted
1459  // to a post-increment load later by emitEpilogue if the callee-save stack
1460  // area allocation can't be combined with the local stack area allocation.
1461  // For example:
1462  // ldp fp, lr, [sp, #32] // addImm(+4)
1463  // ldp x20, x19, [sp, #16] // addImm(+2)
1464  // ldp x22, x21, [sp, #0] // addImm(+0)
1465  // Note: see comment in spillCalleeSavedRegisters()
1466  unsigned LdrOpc;
1467  unsigned Size, Align;
1468  switch (RPI.Type) {
1469  case RegPairInfo::GPR:
1470  LdrOpc = RPI.isPaired() ? AArch64::LDPXi : AArch64::LDRXui;
1471  Size = 8;
1472  Align = 8;
1473  break;
1474  case RegPairInfo::FPR64:
1475  LdrOpc = RPI.isPaired() ? AArch64::LDPDi : AArch64::LDRDui;
1476  Size = 8;
1477  Align = 8;
1478  break;
1479  case RegPairInfo::FPR128:
1480  LdrOpc = RPI.isPaired() ? AArch64::LDPQi : AArch64::LDRQui;
1481  Size = 16;
1482  Align = 16;
1483  break;
1484  }
1485  LLVM_DEBUG(dbgs() << "CSR restore: (" << printReg(Reg1, TRI);
1486  if (RPI.isPaired()) dbgs() << ", " << printReg(Reg2, TRI);
1487  dbgs() << ") -> fi#(" << RPI.FrameIdx;
1488  if (RPI.isPaired()) dbgs() << ", " << RPI.FrameIdx + 1;
1489  dbgs() << ")\n");
1490 
1491  MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(LdrOpc));
1492  if (RPI.isPaired()) {
1493  MIB.addReg(Reg2, getDefRegState(true));
1495  MachinePointerInfo::getFixedStack(MF, RPI.FrameIdx + 1),
1496  MachineMemOperand::MOLoad, Size, Align));
1497  }
1498  MIB.addReg(Reg1, getDefRegState(true))
1499  .addReg(AArch64::SP)
1500  .addImm(RPI.Offset) // [sp, #offset*scale]
1501  // where factor*scale is implicit
1504  MachinePointerInfo::getFixedStack(MF, RPI.FrameIdx),
1505  MachineMemOperand::MOLoad, Size, Align));
1506  };
1507 
1509  for (const RegPairInfo &RPI : reverse(RegPairs))
1510  EmitMI(RPI);
1511  else
1512  for (const RegPairInfo &RPI : RegPairs)
1513  EmitMI(RPI);
1514 
1515  if (NeedShadowCallStackProlog) {
1516  // Shadow call stack epilog: ldr x30, [x18, #-8]!
1517  BuildMI(MBB, MI, DL, TII.get(AArch64::LDRXpre))
1518  .addReg(AArch64::X18, RegState::Define)
1519  .addReg(AArch64::LR, RegState::Define)
1520  .addReg(AArch64::X18)
1521  .addImm(-8)
1523  }
1524 
1525  return true;
1526 }
1527 
1529  BitVector &SavedRegs,
1530  RegScavenger *RS) const {
1531  // All calls are tail calls in GHC calling conv, and functions have no
1532  // prologue/epilogue.
1534  return;
1535 
1536  TargetFrameLowering::determineCalleeSaves(MF, SavedRegs, RS);
1537  const AArch64RegisterInfo *RegInfo = static_cast<const AArch64RegisterInfo *>(
1538  MF.getSubtarget().getRegisterInfo());
1540  unsigned UnspilledCSGPR = AArch64::NoRegister;
1541  unsigned UnspilledCSGPRPaired = AArch64::NoRegister;
1542 
1543  MachineFrameInfo &MFI = MF.getFrameInfo();
1544  const MCPhysReg *CSRegs = RegInfo->getCalleeSavedRegs(&MF);
1545 
1546  unsigned BasePointerReg = RegInfo->hasBasePointer(MF)
1547  ? RegInfo->getBaseRegister()
1548  : (unsigned)AArch64::NoRegister;
1549 
1550  unsigned ExtraCSSpill = 0;
1551  // Figure out which callee-saved registers to save/restore.
1552  for (unsigned i = 0; CSRegs[i]; ++i) {
1553  const unsigned Reg = CSRegs[i];
1554 
1555  // Add the base pointer register to SavedRegs if it is callee-save.
1556  if (Reg == BasePointerReg)
1557  SavedRegs.set(Reg);
1558 
1559  bool RegUsed = SavedRegs.test(Reg);
1560  unsigned PairedReg = CSRegs[i ^ 1];
1561  if (!RegUsed) {
1562  if (AArch64::GPR64RegClass.contains(Reg) &&
1563  !RegInfo->isReservedReg(MF, Reg)) {
1564  UnspilledCSGPR = Reg;
1565  UnspilledCSGPRPaired = PairedReg;
1566  }
1567  continue;
1568  }
1569 
1570  // MachO's compact unwind format relies on all registers being stored in
1571  // pairs.
1572  // FIXME: the usual format is actually better if unwinding isn't needed.
1573  if (produceCompactUnwindFrame(MF) && PairedReg != AArch64::NoRegister &&
1574  !SavedRegs.test(PairedReg)) {
1575  SavedRegs.set(PairedReg);
1576  if (AArch64::GPR64RegClass.contains(PairedReg) &&
1577  !RegInfo->isReservedReg(MF, PairedReg))
1578  ExtraCSSpill = PairedReg;
1579  }
1580  }
1581 
1582  // Calculates the callee saved stack size.
1583  unsigned CSStackSize = 0;
1585  const MachineRegisterInfo &MRI = MF.getRegInfo();
1586  for (unsigned Reg : SavedRegs.set_bits())
1587  CSStackSize += TRI->getRegSizeInBits(Reg, MRI) / 8;
1588 
1589  // Save number of saved regs, so we can easily update CSStackSize later.
1590  unsigned NumSavedRegs = SavedRegs.count();
1591 
1592  // The frame record needs to be created by saving the appropriate registers
1593  unsigned EstimatedStackSize = MFI.estimateStackSize(MF);
1594  if (hasFP(MF) ||
1595  windowsRequiresStackProbe(MF, EstimatedStackSize + CSStackSize + 16)) {
1596  SavedRegs.set(AArch64::FP);
1597  SavedRegs.set(AArch64::LR);
1598  }
1599 
1600  LLVM_DEBUG(dbgs() << "*** determineCalleeSaves\nUsed CSRs:";
1601  for (unsigned Reg
1602  : SavedRegs.set_bits()) dbgs()
1603  << ' ' << printReg(Reg, RegInfo);
1604  dbgs() << "\n";);
1605 
1606  // If any callee-saved registers are used, the frame cannot be eliminated.
1607  bool CanEliminateFrame = SavedRegs.count() == 0;
1608 
1609  // The CSR spill slots have not been allocated yet, so estimateStackSize
1610  // won't include them.
1611  unsigned EstimatedStackSizeLimit = estimateRSStackSizeLimit(MF);
1612  bool BigStack = (EstimatedStackSize + CSStackSize) > EstimatedStackSizeLimit;
1613  if (BigStack || !CanEliminateFrame || RegInfo->cannotEliminateFrame(MF))
1614  AFI->setHasStackFrame(true);
1615 
1616  // Estimate if we might need to scavenge a register at some point in order
1617  // to materialize a stack offset. If so, either spill one additional
1618  // callee-saved register or reserve a special spill slot to facilitate
1619  // register scavenging. If we already spilled an extra callee-saved register
1620  // above to keep the number of spills even, we don't need to do anything else
1621  // here.
1622  if (BigStack) {
1623  if (!ExtraCSSpill && UnspilledCSGPR != AArch64::NoRegister) {
1624  LLVM_DEBUG(dbgs() << "Spilling " << printReg(UnspilledCSGPR, RegInfo)
1625  << " to get a scratch register.\n");
1626  SavedRegs.set(UnspilledCSGPR);
1627  // MachO's compact unwind format relies on all registers being stored in
1628  // pairs, so if we need to spill one extra for BigStack, then we need to
1629  // store the pair.
1630  if (produceCompactUnwindFrame(MF))
1631  SavedRegs.set(UnspilledCSGPRPaired);
1632  ExtraCSSpill = UnspilledCSGPRPaired;
1633  }
1634 
1635  // If we didn't find an extra callee-saved register to spill, create
1636  // an emergency spill slot.
1637  if (!ExtraCSSpill || MF.getRegInfo().isPhysRegUsed(ExtraCSSpill)) {
1638  const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
1639  const TargetRegisterClass &RC = AArch64::GPR64RegClass;
1640  unsigned Size = TRI->getSpillSize(RC);
1641  unsigned Align = TRI->getSpillAlignment(RC);
1642  int FI = MFI.CreateStackObject(Size, Align, false);
1643  RS->addScavengingFrameIndex(FI);
1644  LLVM_DEBUG(dbgs() << "No available CS registers, allocated fi#" << FI
1645  << " as the emergency spill slot.\n");
1646  }
1647  }
1648 
1649  // Adding the size of additional 64bit GPR saves.
1650  CSStackSize += 8 * (SavedRegs.count() - NumSavedRegs);
1651  unsigned AlignedCSStackSize = alignTo(CSStackSize, 16);
1652  LLVM_DEBUG(dbgs() << "Estimated stack frame size: "
1653  << EstimatedStackSize + AlignedCSStackSize
1654  << " bytes.\n");
1655 
1656  // Round up to register pair alignment to avoid additional SP adjustment
1657  // instructions.
1658  AFI->setCalleeSavedStackSize(AlignedCSStackSize);
1659  AFI->setCalleeSaveStackHasFreeSpace(AlignedCSStackSize != CSStackSize);
1660 }
1661 
1663  const MachineFunction &MF) const {
1664  const AArch64FunctionInfo *AFI = MF.getInfo<AArch64FunctionInfo>();
1665  return AFI->hasCalleeSaveStackFreeSpace();
1666 }
bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, std::vector< CalleeSavedInfo > &CSI, const TargetRegisterInfo *TRI) const override
restoreCalleeSavedRegisters - Issues instruction(s) to restore all callee saved registers and returns...
static cl::opt< bool > ReverseCSRRestoreSeq("reverse-csr-restore-seq", cl::desc("reverse the CSR restore sequence"), cl::init(false), cl::Hidden)
const MachineInstrBuilder & setMemRefs(ArrayRef< MachineMemOperand *> MMOs) const
const MachineInstrBuilder & add(const MachineOperand &MO) const
A parsed version of the target data layout string in and methods for querying it. ...
Definition: DataLayout.h:111
constexpr char Align[]
Key for Kernel::Arg::Metadata::mAlign.
BitVector & set()
Definition: BitVector.h:398
Type
MessagePack types as defined in the standard, with the exception of Integer being divided into a sign...
Definition: MsgPackReader.h:49
bool hasStackMap() const
This method may be called any time after instruction selection is complete to determine if there is a...
AArch64FunctionInfo - This class is derived from MachineFunctionInfo and contains private AArch64-spe...
bool hasDebugInfo() const
Returns true if valid debug info is present.
bool available(const MachineRegisterInfo &MRI, unsigned Reg) const
Returns true if register Reg and no aliasing register is in the set.
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:139
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:42
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
class llvm::RegisterBankInfo GPR
static void computeCalleeSaveRegisterPairs(MachineFunction &MF, const std::vector< CalleeSavedInfo > &CSI, const TargetRegisterInfo *TRI, SmallVectorImpl< RegPairInfo > &RegPairs, bool &NeedShadowCallStackProlog)
bool cannotEliminateFrame(const MachineFunction &MF) const
iterator getFirstTerminator()
Returns an iterator to the first terminator instruction of this basic block.
unsigned getReg() const
getReg - Returns the register number.
static MCCFIInstruction createOffset(MCSymbol *L, unsigned Register, int Offset)
.cfi_offset Previous value of Register is saved at offset Offset from CFA.
Definition: MCDwarf.h:487
unsigned Reg
bool test(unsigned Idx) const
Definition: BitVector.h:502
LLVM_NODISCARD detail::scope_exit< typename std::decay< Callable >::type > make_scope_exit(Callable &&F)
Definition: ScopeExit.h:59
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
Definition: Function.h:321
STATISTIC(NumFunctions, "Total number of functions")
unsigned const TargetRegisterInfo * TRI
A debug info location.
Definition: DebugLoc.h:34
F(f)
MachineModuleInfo & getMMI() const
uint64_t alignTo(uint64_t Value, uint64_t Align, uint64_t Skew=0)
Returns the next integer (mod 2**64) that is greater than or equal to Value and is a multiple of Alig...
Definition: MathExtras.h:685
bool canUseRedZone(const MachineFunction &MF) const
Can this function use the red zone for local allocations.
int getOffsetOfLocalArea() const
getOffsetOfLocalArea - This method returns the offset of the local area from the stack pointer on ent...
static MCCFIInstruction createDefCfaOffset(MCSymbol *L, int Offset)
.cfi_def_cfa_offset modifies a rule for computing CFA.
Definition: MCDwarf.h:474
int CreateStackObject(uint64_t Size, unsigned Alignment, bool isSpillSlot, const AllocaInst *Alloca=nullptr, uint8_t ID=0)
Create a new statically sized stack object, returning a nonnegative identifier to represent it...
bool isCallingConvWin64(CallingConv::ID CC) const
unsigned getSpillSize(const TargetRegisterClass &RC) const
Return the size in bytes of the stack slot allocated to hold a spilled copy of a register from class ...
const MachineInstrBuilder & setMIFlag(MachineInstr::MIFlag Flag) const
return AArch64::GPR64RegClass contains(Reg)
static unsigned findScratchNonCalleeSaveRegister(MachineBasicBlock *MBB)
virtual void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs, RegScavenger *RS=nullptr) const
This method determines which of the registers reported by TargetRegisterInfo::getCalleeSavedRegs() sh...
bool supportSwiftError() const override
Return true if the target supports swifterror attribute.
unsigned getFrameRegister(const MachineFunction &MF) const override
static unsigned getPrologueDeath(MachineFunction &MF, unsigned Reg)
unsigned getSpillAlignment(const TargetRegisterClass &RC) const
Return the minimum required alignment in bytes for a spill slot for a register of this class...
bool isFrameAddressTaken() const
This method may be called any time after instruction selection is complete to determine if there is a...
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
const HexagonInstrInfo * TII
Printable printReg(unsigned Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
static MachineBasicBlock::iterator convertCalleeSaveRestoreToSPPrePostIncDec(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, const TargetInstrInfo *TII, int CSStackSizeInc)
bool hasReservedCallFrame(const MachineFunction &MF) const override
hasReservedCallFrame - Under normal circumstances, when a frame pointer is not required, we reserve argument space for call sites in the function immediately on entry to the current function.
const TargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
int getFrameIndexReference(const MachineFunction &MF, int FI, unsigned &FrameReg) const override
getFrameIndexReference - Provide a base+offset reference to an FI slot for debug info.
int64_t getObjectOffset(int ObjectIdx) const
Return the assigned stack offset of the specified object from the incoming stack pointer.
This file contains the simple types necessary to represent the attributes associated with functions a...
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
bool hasVarSizedObjects() const
This method may be called any time after instruction selection is complete to determine if the stack ...
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:409
int getDwarfRegNum(unsigned RegNum, bool isEH) const
Map a target register to an equivalent dwarf register number.
LLVM_NODISCARD unsigned addFrameInst(const MCCFIInstruction &Inst)
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, uint64_t s, unsigned base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
bool canUseAsPrologue(const MachineBasicBlock &MBB) const override
Check whether or not the given MBB can be used as a prologue for the target.
static unsigned estimateRSStackSizeLimit(MachineFunction &MF)
Look at each instruction that references stack frames and return the stack size limit beyond which so...
auto reverse(ContainerTy &&C, typename std::enable_if< has_rbegin< ContainerTy >::value >::type *=nullptr) -> decltype(make_range(C.rbegin(), C.rend()))
Definition: STLExtras.h:251
void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs, RegScavenger *RS) const override
This method determines which of the registers reported by TargetRegisterInfo::getCalleeSavedRegs() sh...
int isAArch64FrameOffsetLegal(const MachineInstr &MI, int &Offset, bool *OutUseUnscaledOp=nullptr, unsigned *OutUnscaledOp=nullptr, int *EmittableOffset=nullptr)
Check if the Offset is a valid frame offset for MI.
void emitPrologue(MachineFunction &MF, MachineBasicBlock &MBB) const override
emitProlog/emitEpilog - These methods insert prolog and epilog code into the function.
virtual void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const
Emit instructions to copy a pair of physical registers.
const AArch64RegisterInfo * getRegisterInfo() const override
bool DisableFramePointerElim(const MachineFunction &MF) const
DisableFramePointerElim - This returns true if frame pointer elimination optimization should be disab...
const MCContext & getContext() const
iterator getLastNonDebugInstr()
Returns an iterator to the last non-debug instruction in the basic block, or end().
AttributeList getAttributes() const
Return the attribute list for this Function.
Definition: Function.h:224
void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const override
virtual const TargetInstrInfo * getInstrInfo() const
constexpr char Attrs[]
Key for Kernel::Metadata::mAttrs.
bool isXRegisterReserved(size_t i) const
const DataLayout & getDataLayout() const
Return the DataLayout attached to the Module associated to this MF.
unsigned getKillRegState(bool B)
void emitFrameOffset(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, int Offset, const TargetInstrInfo *TII, MachineInstr::MIFlag=MachineInstr::NoFlags, bool SetNZCV=false)
emitFrameOffset - Emit instructions as needed to set DestReg to SrcReg plus Offset.
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
TargetInstrInfo - Interface to description of machine instruction set.
unsigned getDefRegState(bool B)
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
const AArch64TargetLowering * getTargetLowering() const override
static MDTuple * get(LLVMContext &Context, ArrayRef< Metadata *> MDs)
Definition: Metadata.h:1164
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:410
void addLiveIn(MCPhysReg PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())
Adds the specified register as a live in.
This file declares the machine register scavenger class.
MCSymbol * createTempSymbol(bool CanBeUnnamed=true)
Create and return a new assembler temporary symbol with a unique but unspecified name.
Definition: MCContext.cpp:217
unsigned const MachineRegisterInfo * MRI
std::size_t countTrailingZeros(T Val, ZeroBehavior ZB=ZB_Width)
Count number of 0&#39;s from the least significant bit to the most stopping at the first 1...
Definition: MathExtras.h:120
static MCCFIInstruction createDefCfa(MCSymbol *L, unsigned Register, int Offset)
.cfi_def_cfa defines a rule for computing CFA as: take address from Register and add Offset to it...
Definition: MCDwarf.h:460
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
static bool ShouldSignReturnAddress(MachineFunction &MF)
unsigned getPointerSize(unsigned AS=0) const
Layout pointer size FIXME: The defaults need to be removed once all of the backends/clients are updat...
Definition: DataLayout.cpp:629
int resolveFrameIndexReference(const MachineFunction &MF, int FI, unsigned &FrameReg, bool PreferFP=false) const
void addLiveIns(const MachineBasicBlock &MBB)
Adds all live-in registers of basic block MBB.
DebugLoc findDebugLoc(instr_iterator MBBI)
Find the next valid DebugLoc starting at MBBI, skipping any DBG_VALUE and DBG_LABEL instructions...
bool isFixedObjectIndex(int ObjectIdx) const
Returns true if the specified index corresponds to a fixed stack object.
unsigned getMaxAlignment() const
Return the alignment in bytes that this function must be aligned to, which is greater than the defaul...
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override
Code Generation virtual methods...
static cl::opt< bool > EnableRedZone("aarch64-redzone", cl::desc("enable use of redzone on AArch64"), cl::init(false), cl::Hidden)
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
const MachineBasicBlock & front() const
This file implements the LivePhysRegs utility for tracking liveness of physical registers.
unsigned getStackAlignment() const
getStackAlignment - This method returns the number of bytes to which the stack pointer must be aligne...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
virtual bool hasReservedCallFrame(const MachineFunction &MF) const
hasReservedCallFrame - Under normal circumstances, when a frame pointer is not required, we reserve argument space for call sites in the function immediately on entry to the current function.
unsigned getNumExplicitOperands() const
Returns the number of non-implicit operands.
void emitCalleeSavedFrameMoves(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) const
The memory access writes data.
std::enable_if< std::numeric_limits< T >::is_signed, bool >::type getAsInteger(unsigned Radix, T &Result) const
Parse the current string as an integer of the specified radix.
Definition: StringRef.h:497
size_type count() const
count - Returns the number of bits which are set.
Definition: BitVector.h:173
static void InsertReturnAddressAuth(MachineFunction &MF, MachineBasicBlock &MBB)
unsigned getMaxCallFrameSize() const
Return the maximum size of a call frame that must be allocated for an outgoing function call...
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
Definition: Function.h:213
void addScavengingFrameIndex(int FI)
Add a scavenging frame index.
MachineOperand class - Representation of each machine instruction operand.
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:847
unsigned estimateStackSize(const MachineFunction &MF) const
Estimate and return the size of the stack frame.
static const unsigned DefaultSafeSPDisplacement
This is the biggest offset to the stack pointer we can encode in aarch64 instructions (without using ...
Information about stack frame layout on the target.
const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const
int64_t getImm() const
const Function & getFunction() const
Return the LLVM function that this machine code represents.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:133
bool needsUnwindTableEntry() const
True if this function needs an unwind table.
Definition: Function.h:573
bool isPhysRegUsed(unsigned PhysReg) const
Return true if the specified register is modified or read in this function.
bool enableStackSlotScavenging(const MachineFunction &MF) const override
Returns true if the stack slot holes in the fixed and callee-save stack area should be used when allo...
CodeModel::Model getCodeModel() const
Returns the code model.
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE bool equals(StringRef RHS) const
equals - Check for string equality, this is more efficient than compare() when the relative ordering ...
Definition: StringRef.h:169
static unsigned getArithExtendImm(AArch64_AM::ShiftExtendType ET, unsigned Imm)
getArithExtendImm - Encode the extend type and shift amount for an arithmetic instruction: imm: 3-bit...
static bool windowsRequiresStackProbe(MachineFunction &MF, unsigned StackSizeInBytes)
bool hasFP(const MachineFunction &MF) const override
hasFP - Return true if the specified function should have a dedicated frame pointer register...
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
The memory access reads data.
TargetSubtargetInfo - Generic base class for all target subtargets.
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
bool isReservedReg(const MachineFunction &MF, unsigned Reg) const
bool isLiveIn(unsigned Reg) const
Representation of each machine instruction.
Definition: MachineInstr.h:64
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
static void adaptForLdStOpt(MachineBasicBlock &MBB, MachineBasicBlock::iterator FirstSPPopI, MachineBasicBlock::iterator LastPopI)
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Take an instruction from MBB &#39;Other&#39; at the position From, and insert it into this MBB right before &#39;...
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
A set of physical registers with utility functions to track liveness when walking backward/forward th...
Definition: LivePhysRegs.h:49
const MachineInstrBuilder & setMIFlags(unsigned Flags) const
StringRef getValueAsString() const
Return the attribute&#39;s value as a string.
Definition: Attributes.cpp:195
const std::vector< CalleeSavedInfo > & getCalleeSavedInfo() const
Returns a reference to call saved info vector for the current function.
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode...
Definition: MCInstrInfo.h:45
TargetOptions Options
Definition: TargetMachine.h:98
const MachineInstrBuilder & addExternalSymbol(const char *FnName, unsigned char TargetFlags=0) const
#define I(x, y, z)
Definition: MD5.cpp:58
virtual const TargetFrameLowering * getFrameLowering() const
static void fixupCalleeSaveRestoreStackOffset(MachineInstr &MI, unsigned LocalStackSize)
bool spillCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const std::vector< CalleeSavedInfo > &CSI, const TargetRegisterInfo *TRI) const override
spillCalleeSavedRegisters - Issues instruction(s) to spill all callee saved registers and returns tru...
uint32_t Size
Definition: Profile.cpp:47
MachineBasicBlock::iterator eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const override
This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy p...
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
static bool produceCompactUnwindFrame(MachineFunction &MF)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
bool hasBasePointer(const MachineFunction &MF) const
iterator_range< const_set_bits_iterator > set_bits() const
Definition: BitVector.h:130
bool needsStackRealignment(const MachineFunction &MF) const
True if storage within the function requires the stack pointer to be aligned more than the normal cal...
const AArch64InstrInfo * getInstrInfo() const override
Attribute getFnAttribute(Attribute::AttrKind Kind) const
Return the attribute for the given attribute kind.
Definition: Function.h:331
static const unsigned FramePtr
bool isMaxCallFrameSizeComputed() const
IRTranslator LLVM IR MI
bool hasPatchPoint() const
This method may be called any time after instruction selection is complete to determine if there is a...
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:49
unsigned getRegSizeInBits(const TargetRegisterClass &RC) const
Return the size in bits of a register from class RC.
#define LLVM_DEBUG(X)
Definition: Debug.h:123
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:414
uint64_t getStackSize() const
Return the number of bytes that must be allocated to hold all of the fixed size frame objects...
bool isReserved(unsigned PhysReg) const
isReserved - Returns true when PhysReg is a reserved register.
void setCalleeSavedStackSize(unsigned Size)
This class contains meta information specific to a module.
bool hasCalls() const
Return true if the current function has any function calls.
void addReg(unsigned Reg)
Adds a physical register and all its sub-registers to the set.
Definition: LivePhysRegs.h:79