LLVM  7.0.0svn
MachineRegisterInfo.cpp
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1 //===- lib/Codegen/MachineRegisterInfo.cpp --------------------------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // Implementation of the MachineRegisterInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13 
25 #include "llvm/IR/Attributes.h"
26 #include "llvm/IR/DebugLoc.h"
27 #include "llvm/IR/Function.h"
28 #include "llvm/MC/MCRegisterInfo.h"
29 #include "llvm/Support/Casting.h"
31 #include "llvm/Support/Compiler.h"
34 #include <cassert>
35 
36 using namespace llvm;
37 
38 static cl::opt<bool> EnableSubRegLiveness("enable-subreg-liveness", cl::Hidden,
39  cl::init(true), cl::desc("Enable subregister liveness tracking."));
40 
41 // Pin the vtable to this file.
42 void MachineRegisterInfo::Delegate::anchor() {}
43 
45  : MF(MF), TracksSubRegLiveness(MF->getSubtarget().enableSubRegLiveness() &&
47  IsUpdatedCSRsInitialized(false) {
48  unsigned NumRegs = getTargetRegisterInfo()->getNumRegs();
49  VRegInfo.reserve(256);
50  RegAllocHints.reserve(256);
51  UsedPhysRegMask.resize(NumRegs);
52  PhysRegUseDefLists.reset(new MachineOperand*[NumRegs]());
53 }
54 
55 /// setRegClass - Set the register class of the specified virtual register.
56 ///
57 void
59  assert(RC && RC->isAllocatable() && "Invalid RC for virtual register");
60  VRegInfo[Reg].first = RC;
61 }
62 
64  const RegisterBank &RegBank) {
65  VRegInfo[Reg].first = &RegBank;
66 }
67 
68 static const TargetRegisterClass *
70  const TargetRegisterClass *OldRC,
71  const TargetRegisterClass *RC, unsigned MinNumRegs) {
72  if (OldRC == RC)
73  return RC;
74  const TargetRegisterClass *NewRC =
75  MRI.getTargetRegisterInfo()->getCommonSubClass(OldRC, RC);
76  if (!NewRC || NewRC == OldRC)
77  return NewRC;
78  if (NewRC->getNumRegs() < MinNumRegs)
79  return nullptr;
80  MRI.setRegClass(Reg, NewRC);
81  return NewRC;
82 }
83 
84 const TargetRegisterClass *
86  const TargetRegisterClass *RC,
87  unsigned MinNumRegs) {
88  return ::constrainRegClass(*this, Reg, getRegClass(Reg), RC, MinNumRegs);
89 }
90 
91 bool
93  unsigned ConstrainingReg,
94  unsigned MinNumRegs) {
95  auto const *OldRC = getRegClassOrNull(Reg);
96  auto const *RC = getRegClassOrNull(ConstrainingReg);
97  // A virtual register at any point must have either a low-level type
98  // or a class assigned, but not both. The only exception is the internals of
99  // GlobalISel's instruction selection pass, which is allowed to temporarily
100  // introduce registers with types and classes both.
101  assert((OldRC || getType(Reg).isValid()) && "Reg has neither class nor type");
102  assert((!OldRC || !getType(Reg).isValid()) && "Reg has class and type both");
103  assert((RC || getType(ConstrainingReg).isValid()) &&
104  "ConstrainingReg has neither class nor type");
105  assert((!RC || !getType(ConstrainingReg).isValid()) &&
106  "ConstrainingReg has class and type both");
107  if (OldRC && RC)
108  return ::constrainRegClass(*this, Reg, OldRC, RC, MinNumRegs);
109  // If one of the virtual registers is generic (used in generic machine
110  // instructions, has a low-level type, doesn't have a class), and the other is
111  // concrete (used in target specific instructions, doesn't have a low-level
112  // type, has a class), we can not unify them.
113  if (OldRC || RC)
114  return false;
115  // At this point, both registers are guaranteed to have a valid low-level
116  // type, and they must agree.
117  if (getType(Reg) != getType(ConstrainingReg))
118  return false;
119  auto const *OldRB = getRegBankOrNull(Reg);
120  auto const *RB = getRegBankOrNull(ConstrainingReg);
121  if (OldRB)
122  return !RB || RB == OldRB;
123  if (RB)
124  setRegBank(Reg, *RB);
125  return true;
126 }
127 
128 bool
130  const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
131  const TargetRegisterClass *OldRC = getRegClass(Reg);
132  const TargetRegisterClass *NewRC =
134 
135  // Stop early if there is no room to grow.
136  if (NewRC == OldRC)
137  return false;
138 
139  // Accumulate constraints from all uses.
140  for (MachineOperand &MO : reg_nodbg_operands(Reg)) {
141  // Apply the effect of the given operand to NewRC.
142  MachineInstr *MI = MO.getParent();
143  unsigned OpNo = &MO - &MI->getOperand(0);
144  NewRC = MI->getRegClassConstraintEffect(OpNo, NewRC, TII,
146  if (!NewRC || NewRC == OldRC)
147  return false;
148  }
149  setRegClass(Reg, NewRC);
150  return true;
151 }
152 
155  VRegInfo.grow(Reg);
156  RegAllocHints.grow(Reg);
157  insertVRegByName(Name, Reg);
158  return Reg;
159 }
160 
161 /// createVirtualRegister - Create and return a new virtual register in the
162 /// function with the specified register class.
163 ///
164 unsigned
166  StringRef Name) {
167  assert(RegClass && "Cannot create register without RegClass!");
168  assert(RegClass->isAllocatable() &&
169  "Virtual register RegClass must be allocatable.");
170 
171  // New virtual register number.
172  unsigned Reg = createIncompleteVirtualRegister(Name);
173  VRegInfo[Reg].first = RegClass;
174  if (TheDelegate)
175  TheDelegate->MRI_NoteNewVirtualRegister(Reg);
176  return Reg;
177 }
178 
179 LLT MachineRegisterInfo::getType(unsigned VReg) const {
181  return TypeIt != getVRegToType().end() ? TypeIt->second : LLT{};
182 }
183 
184 void MachineRegisterInfo::setType(unsigned VReg, LLT Ty) {
185  // Check that VReg doesn't have a class.
186  assert((getRegClassOrRegBank(VReg).isNull() ||
187  !getRegClassOrRegBank(VReg).is<const TargetRegisterClass *>()) &&
188  "Can't set the size of a non-generic virtual register");
189  getVRegToType()[VReg] = Ty;
190 }
191 
192 unsigned
194  // New virtual register number.
195  unsigned Reg = createIncompleteVirtualRegister(Name);
196  // FIXME: Should we use a dummy register class?
197  VRegInfo[Reg].first = static_cast<RegisterBank *>(nullptr);
198  getVRegToType()[Reg] = Ty;
199  if (TheDelegate)
200  TheDelegate->MRI_NoteNewVirtualRegister(Reg);
201  return Reg;
202 }
203 
205  getVRegToType().clear();
206 }
207 
208 /// clearVirtRegs - Remove all virtual registers (after physreg assignment).
210 #ifndef NDEBUG
211  for (unsigned i = 0, e = getNumVirtRegs(); i != e; ++i) {
213  if (!VRegInfo[Reg].second)
214  continue;
215  verifyUseList(Reg);
216  llvm_unreachable("Remaining virtual register operands");
217  }
218 #endif
219  VRegInfo.clear();
220  for (auto &I : LiveIns)
221  I.second = 0;
222 }
223 
225 #ifndef NDEBUG
226  bool Valid = true;
227  for (MachineOperand &M : reg_operands(Reg)) {
228  MachineOperand *MO = &M;
229  MachineInstr *MI = MO->getParent();
230  if (!MI) {
231  errs() << printReg(Reg, getTargetRegisterInfo())
232  << " use list MachineOperand " << MO
233  << " has no parent instruction.\n";
234  Valid = false;
235  continue;
236  }
237  MachineOperand *MO0 = &MI->getOperand(0);
238  unsigned NumOps = MI->getNumOperands();
239  if (!(MO >= MO0 && MO < MO0+NumOps)) {
240  errs() << printReg(Reg, getTargetRegisterInfo())
241  << " use list MachineOperand " << MO
242  << " doesn't belong to parent MI: " << *MI;
243  Valid = false;
244  }
245  if (!MO->isReg()) {
246  errs() << printReg(Reg, getTargetRegisterInfo())
247  << " MachineOperand " << MO << ": " << *MO
248  << " is not a register\n";
249  Valid = false;
250  }
251  if (MO->getReg() != Reg) {
252  errs() << printReg(Reg, getTargetRegisterInfo())
253  << " use-list MachineOperand " << MO << ": "
254  << *MO << " is the wrong register\n";
255  Valid = false;
256  }
257  }
258  assert(Valid && "Invalid use list");
259 #endif
260 }
261 
263 #ifndef NDEBUG
264  for (unsigned i = 0, e = getNumVirtRegs(); i != e; ++i)
266  for (unsigned i = 1, e = getTargetRegisterInfo()->getNumRegs(); i != e; ++i)
267  verifyUseList(i);
268 #endif
269 }
270 
271 /// Add MO to the linked list of operands for its register.
273  assert(!MO->isOnRegUseList() && "Already on list");
274  MachineOperand *&HeadRef = getRegUseDefListHead(MO->getReg());
275  MachineOperand *const Head = HeadRef;
276 
277  // Head points to the first list element.
278  // Next is NULL on the last list element.
279  // Prev pointers are circular, so Head->Prev == Last.
280 
281  // Head is NULL for an empty list.
282  if (!Head) {
283  MO->Contents.Reg.Prev = MO;
284  MO->Contents.Reg.Next = nullptr;
285  HeadRef = MO;
286  return;
287  }
288  assert(MO->getReg() == Head->getReg() && "Different regs on the same list!");
289 
290  // Insert MO between Last and Head in the circular Prev chain.
291  MachineOperand *Last = Head->Contents.Reg.Prev;
292  assert(Last && "Inconsistent use list");
293  assert(MO->getReg() == Last->getReg() && "Different regs on the same list!");
294  Head->Contents.Reg.Prev = MO;
295  MO->Contents.Reg.Prev = Last;
296 
297  // Def operands always precede uses. This allows def_iterator to stop early.
298  // Insert def operands at the front, and use operands at the back.
299  if (MO->isDef()) {
300  // Insert def at the front.
301  MO->Contents.Reg.Next = Head;
302  HeadRef = MO;
303  } else {
304  // Insert use at the end.
305  MO->Contents.Reg.Next = nullptr;
306  Last->Contents.Reg.Next = MO;
307  }
308 }
309 
310 /// Remove MO from its use-def list.
312  assert(MO->isOnRegUseList() && "Operand not on use list");
313  MachineOperand *&HeadRef = getRegUseDefListHead(MO->getReg());
314  MachineOperand *const Head = HeadRef;
315  assert(Head && "List already empty");
316 
317  // Unlink this from the doubly linked list of operands.
318  MachineOperand *Next = MO->Contents.Reg.Next;
319  MachineOperand *Prev = MO->Contents.Reg.Prev;
320 
321  // Prev links are circular, next link is NULL instead of looping back to Head.
322  if (MO == Head)
323  HeadRef = Next;
324  else
325  Prev->Contents.Reg.Next = Next;
326 
327  (Next ? Next : Head)->Contents.Reg.Prev = Prev;
328 
329  MO->Contents.Reg.Prev = nullptr;
330  MO->Contents.Reg.Next = nullptr;
331 }
332 
333 /// Move NumOps operands from Src to Dst, updating use-def lists as needed.
334 ///
335 /// The Dst range is assumed to be uninitialized memory. (Or it may contain
336 /// operands that won't be destroyed, which is OK because the MO destructor is
337 /// trivial anyway).
338 ///
339 /// The Src and Dst ranges may overlap.
341  MachineOperand *Src,
342  unsigned NumOps) {
343  assert(Src != Dst && NumOps && "Noop moveOperands");
344 
345  // Copy backwards if Dst is within the Src range.
346  int Stride = 1;
347  if (Dst >= Src && Dst < Src + NumOps) {
348  Stride = -1;
349  Dst += NumOps - 1;
350  Src += NumOps - 1;
351  }
352 
353  // Copy one operand at a time.
354  do {
355  new (Dst) MachineOperand(*Src);
356 
357  // Dst takes Src's place in the use-def chain.
358  if (Src->isReg()) {
359  MachineOperand *&Head = getRegUseDefListHead(Src->getReg());
360  MachineOperand *Prev = Src->Contents.Reg.Prev;
361  MachineOperand *Next = Src->Contents.Reg.Next;
362  assert(Head && "List empty, but operand is chained");
363  assert(Prev && "Operand was not on use-def list");
364 
365  // Prev links are circular, next link is NULL instead of looping back to
366  // Head.
367  if (Src == Head)
368  Head = Dst;
369  else
370  Prev->Contents.Reg.Next = Dst;
371 
372  // Update Prev pointer. This also works when Src was pointing to itself
373  // in a 1-element list. In that case Head == Dst.
374  (Next ? Next : Head)->Contents.Reg.Prev = Dst;
375  }
376 
377  Dst += Stride;
378  Src += Stride;
379  } while (--NumOps);
380 }
381 
382 /// replaceRegWith - Replace all instances of FromReg with ToReg in the
383 /// machine function. This is like llvm-level X->replaceAllUsesWith(Y),
384 /// except that it also changes any definitions of the register as well.
385 /// If ToReg is a physical register we apply the sub register to obtain the
386 /// final/proper physical register.
387 void MachineRegisterInfo::replaceRegWith(unsigned FromReg, unsigned ToReg) {
388  assert(FromReg != ToReg && "Cannot replace a reg with itself");
389 
391 
392  // TODO: This could be more efficient by bulk changing the operands.
393  for (reg_iterator I = reg_begin(FromReg), E = reg_end(); I != E; ) {
394  MachineOperand &O = *I;
395  ++I;
397  O.substPhysReg(ToReg, *TRI);
398  } else {
399  O.setReg(ToReg);
400  }
401  }
402 }
403 
404 /// getVRegDef - Return the machine instr that defines the specified virtual
405 /// register or null if none is found. This assumes that the code is in SSA
406 /// form, so there should only be one definition.
408  // Since we are in SSA form, we can use the first definition.
410  assert((I.atEnd() || std::next(I) == def_instr_end()) &&
411  "getVRegDef assumes a single definition or no definition");
412  return !I.atEnd() ? &*I : nullptr;
413 }
414 
415 /// getUniqueVRegDef - Return the unique machine instr that defines the
416 /// specified virtual register or null if none is found. If there are
417 /// multiple definitions or no definition, return null.
419  if (def_empty(Reg)) return nullptr;
421  if (std::next(I) != def_instr_end())
422  return nullptr;
423  return &*I;
424 }
425 
426 bool MachineRegisterInfo::hasOneNonDBGUse(unsigned RegNo) const {
428  if (UI == use_nodbg_end())
429  return false;
430  return ++UI == use_nodbg_end();
431 }
432 
433 /// clearKillFlags - Iterate over all the uses of the given register and
434 /// clear the kill flag from the MachineOperand. This function is used by
435 /// optimization passes which extend register lifetimes and need only
436 /// preserve conservative kill flag information.
438  for (MachineOperand &MO : use_operands(Reg))
439  MO.setIsKill(false);
440 }
441 
442 bool MachineRegisterInfo::isLiveIn(unsigned Reg) const {
443  for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I)
444  if (I->first == Reg || I->second == Reg)
445  return true;
446  return false;
447 }
448 
449 /// getLiveInPhysReg - If VReg is a live-in virtual register, return the
450 /// corresponding live-in physical register.
451 unsigned MachineRegisterInfo::getLiveInPhysReg(unsigned VReg) const {
452  for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I)
453  if (I->second == VReg)
454  return I->first;
455  return 0;
456 }
457 
458 /// getLiveInVirtReg - If PReg is a live-in physical register, return the
459 /// corresponding live-in physical register.
460 unsigned MachineRegisterInfo::getLiveInVirtReg(unsigned PReg) const {
461  for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I)
462  if (I->first == PReg)
463  return I->second;
464  return 0;
465 }
466 
467 /// EmitLiveInCopies - Emit copies to initialize livein virtual registers
468 /// into the given entry block.
469 void
471  const TargetRegisterInfo &TRI,
472  const TargetInstrInfo &TII) {
473  // Emit the copies into the top of the block.
474  for (unsigned i = 0, e = LiveIns.size(); i != e; ++i)
475  if (LiveIns[i].second) {
476  if (use_nodbg_empty(LiveIns[i].second)) {
477  // The livein has no non-dbg uses. Drop it.
478  //
479  // It would be preferable to have isel avoid creating live-in
480  // records for unused arguments in the first place, but it's
481  // complicated by the debug info code for arguments.
482  LiveIns.erase(LiveIns.begin() + i);
483  --i; --e;
484  } else {
485  // Emit a copy.
486  BuildMI(*EntryMBB, EntryMBB->begin(), DebugLoc(),
487  TII.get(TargetOpcode::COPY), LiveIns[i].second)
488  .addReg(LiveIns[i].first);
489 
490  // Add the register to the entry block live-in set.
491  EntryMBB->addLiveIn(LiveIns[i].first);
492  }
493  } else {
494  // Add the register to the entry block live-in set.
495  EntryMBB->addLiveIn(LiveIns[i].first);
496  }
497 }
498 
500  // Lane masks are only defined for vregs.
502  const TargetRegisterClass &TRC = *getRegClass(Reg);
503  return TRC.getLaneMask();
504 }
505 
506 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
508  for (MachineInstr &I : use_instructions(Reg))
509  I.dump();
510 }
511 #endif
512 
514  ReservedRegs = getTargetRegisterInfo()->getReservedRegs(MF);
515  assert(ReservedRegs.size() == getTargetRegisterInfo()->getNumRegs() &&
516  "Invalid ReservedRegs vector from target");
517 }
518 
519 bool MachineRegisterInfo::isConstantPhysReg(unsigned PhysReg) const {
521 
523  if (TRI->isConstantPhysReg(PhysReg))
524  return true;
525 
526  // Check if any overlapping register is modified, or allocatable so it may be
527  // used later.
528  for (MCRegAliasIterator AI(PhysReg, TRI, true);
529  AI.isValid(); ++AI)
530  if (!def_empty(*AI) || isAllocatable(*AI))
531  return false;
532  return true;
533 }
534 
535 bool
538  return isConstantPhysReg(PhysReg) ||
539  TRI->isCallerPreservedPhysReg(PhysReg, *MF);
540 }
541 
542 /// markUsesInDebugValueAsUndef - Mark every DBG_VALUE referencing the
543 /// specified register as undefined which causes the DBG_VALUE to be
544 /// deleted during LiveDebugVariables analysis.
546  // Mark any DBG_VALUE that uses Reg as undef (but don't delete it.)
549  I != E; I = nextI) {
550  nextI = std::next(I); // I is invalidated by the setReg
551  MachineInstr *UseMI = &*I;
552  if (UseMI->isDebugValue())
553  UseMI->getOperand(0).setReg(0U);
554  }
555 }
556 
557 static const Function *getCalledFunction(const MachineInstr &MI) {
558  for (const MachineOperand &MO : MI.operands()) {
559  if (!MO.isGlobal())
560  continue;
561  const Function *Func = dyn_cast<Function>(MO.getGlobal());
562  if (Func != nullptr)
563  return Func;
564  }
565  return nullptr;
566 }
567 
568 static bool isNoReturnDef(const MachineOperand &MO) {
569  // Anything which is not a noreturn function is a real def.
570  const MachineInstr &MI = *MO.getParent();
571  if (!MI.isCall())
572  return false;
573  const MachineBasicBlock &MBB = *MI.getParent();
574  if (!MBB.succ_empty())
575  return false;
576  const MachineFunction &MF = *MBB.getParent();
577  // We need to keep correct unwind information even if the function will
578  // not return, since the runtime may need it.
579  if (MF.getFunction().hasFnAttribute(Attribute::UWTable))
580  return false;
581  const Function *Called = getCalledFunction(MI);
582  return !(Called == nullptr || !Called->hasFnAttribute(Attribute::NoReturn) ||
583  !Called->hasFnAttribute(Attribute::NoUnwind));
584 }
585 
587  bool SkipNoReturnDef) const {
588  if (UsedPhysRegMask.test(PhysReg))
589  return true;
591  for (MCRegAliasIterator AI(PhysReg, TRI, true); AI.isValid(); ++AI) {
592  for (const MachineOperand &MO : make_range(def_begin(*AI), def_end())) {
593  if (!SkipNoReturnDef && isNoReturnDef(MO))
594  continue;
595  return true;
596  }
597  }
598  return false;
599 }
600 
601 bool MachineRegisterInfo::isPhysRegUsed(unsigned PhysReg) const {
602  if (UsedPhysRegMask.test(PhysReg))
603  return true;
605  for (MCRegAliasIterator AliasReg(PhysReg, TRI, true); AliasReg.isValid();
606  ++AliasReg) {
607  if (!reg_nodbg_empty(*AliasReg))
608  return true;
609  }
610  return false;
611 }
612 
614 
616  assert(Reg && (Reg < TRI->getNumRegs()) &&
617  "Trying to disable an invalid register");
618 
619  if (!IsUpdatedCSRsInitialized) {
620  const MCPhysReg *CSR = TRI->getCalleeSavedRegs(MF);
621  for (const MCPhysReg *I = CSR; *I; ++I)
622  UpdatedCSRs.push_back(*I);
623 
624  // Zero value represents the end of the register list
625  // (no more registers should be pushed).
626  UpdatedCSRs.push_back(0);
627 
628  IsUpdatedCSRsInitialized = true;
629  }
630 
631  // Remove the register (and its aliases from the list).
632  for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI)
633  UpdatedCSRs.erase(std::remove(UpdatedCSRs.begin(), UpdatedCSRs.end(), *AI),
634  UpdatedCSRs.end());
635 }
636 
638  if (IsUpdatedCSRsInitialized)
639  return UpdatedCSRs.data();
640 
642 }
643 
645  if (IsUpdatedCSRsInitialized)
646  UpdatedCSRs.clear();
647 
648  for (MCPhysReg Reg : CSRs)
649  UpdatedCSRs.push_back(Reg);
650 
651  // Zero value represents the end of the register list
652  // (no more registers should be pushed).
653  UpdatedCSRs.push_back(0);
654  IsUpdatedCSRsInitialized = true;
655 }
656 
657 bool MachineRegisterInfo::isReservedRegUnit(unsigned Unit) const {
659  for (MCRegUnitRootIterator Root(Unit, TRI); Root.isValid(); ++Root) {
660  bool IsRootReserved = true;
661  for (MCSuperRegIterator Super(*Root, TRI, /*IncludeSelf=*/true);
662  Super.isValid(); ++Super) {
663  unsigned Reg = *Super;
664  if (!isReserved(Reg)) {
665  IsRootReserved = false;
666  break;
667  }
668  }
669  if (IsRootReserved)
670  return true;
671  }
672  return false;
673 }
bool reg_nodbg_empty(unsigned RegNo) const
reg_nodbg_empty - Return true if the only instructions using or defining Reg are Debug instructions...
void resize(unsigned N, bool t=false)
resize - Grow or shrink the bitvector.
Definition: BitVector.h:372
const TargetRegisterClass * getCommonSubClass(const TargetRegisterClass *A, const TargetRegisterClass *B, const MVT::SimpleValueType SVT=MVT::SimpleValueType::Any) const
Find the largest common subclass of A and B.
void push_back(const T &Elt)
Definition: SmallVector.h:212
void EmitLiveInCopies(MachineBasicBlock *EntryMBB, const TargetRegisterInfo &TRI, const TargetInstrInfo &TII)
EmitLiveInCopies - Emit copies to initialize livein virtual registers into the given entry block...
raw_ostream & errs()
This returns a reference to a raw_ostream for standard error.
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
bool use_nodbg_empty(unsigned RegNo) const
use_nodbg_empty - Return true if there are no non-Debug instructions using the specified register...
bool isCall(QueryType Type=AnyInBundle) const
Definition: MachineInstr.h:461
const TargetRegisterClass * getRegClass(unsigned Reg) const
Return the register class of the specified virtual register.
livein_iterator livein_begin() const
void removeRegOperandFromUseList(MachineOperand *MO)
Remove MO from its use-def list.
bool isAllocatable(unsigned PhysReg) const
isAllocatable - Returns true when PhysReg belongs to an allocatable register class and it hasn&#39;t been...
void clearVirtRegTypes()
Remove all types associated to virtual registers (after instruction selection and constraining of all...
LaneBitmask getMaxLaneMaskForVReg(unsigned Reg) const
Returns a mask covering all bits that can appear in lane masks of subregisters of the virtual registe...
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
unsigned getNumRegs() const
Return the number of registers in this class.
static const TargetRegisterClass * constrainRegClass(MachineRegisterInfo &MRI, unsigned Reg, const TargetRegisterClass *OldRC, const TargetRegisterClass *RC, unsigned MinNumRegs)
static unsigned index2VirtReg(unsigned Index)
Convert a 0-based index to a virtual register number.
std::error_code remove(const Twine &path, bool IgnoreNonExisting=true)
Remove path.
bool isPhysRegModified(unsigned PhysReg, bool SkipNoReturnDef=false) const
Return true if the specified register is modified in this function.
This provides a very simple, boring adaptor for a begin and end iterator into a range type...
unsigned getReg() const
getReg - Returns the register number.
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
iterator_range< reg_nodbg_iterator > reg_nodbg_operands(unsigned Reg) const
bool test(unsigned Idx) const
Definition: BitVector.h:502
iterator_range< reg_iterator > reg_operands(unsigned Reg) const
bool constrainRegAttrs(unsigned Reg, unsigned ConstrainingReg, unsigned MinNumRegs=0)
Constrain the register class or the register bank of the virtual register Reg to be a common subclass...
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
Definition: Function.h:302
unsigned second
A debug info location.
Definition: DebugLoc.h:34
void setRegBank(unsigned Reg, const RegisterBank &RegBank)
Set the register bank to RegBank for Reg.
struct llvm::MachineOperand::@147::@149 Reg
iterator_range< mop_iterator > operands()
Definition: MachineInstr.h:335
use_nodbg_iterator use_nodbg_begin(unsigned RegNo) const
void verifyUseLists() const
Verify the use list of all registers.
static use_nodbg_iterator use_nodbg_end()
void clearVirtRegs()
clearVirtRegs - Remove all virtual registers (after physreg assignment).
MCSuperRegIterator enumerates all super-registers of Reg.
const HexagonInstrInfo * TII
unsigned getNumOperands() const
Access to explicit operands of the instruction.
Definition: MachineInstr.h:296
void freezeReservedRegs(const MachineFunction &)
freezeReservedRegs - Called by the register allocator to freeze the set of reserved registers before ...
Reg
All possible values of the reg field in the ModR/M byte.
This file contains the simple types necessary to represent the attributes associated with functions a...
def_iterator def_begin(unsigned RegNo) const
#define LLVM_DUMP_METHOD
Mark debug helper function definitions like dump() that should not be stripped from debug builds...
Definition: Compiler.h:449
const TargetRegisterClass * getRegClassConstraintEffect(unsigned OpIdx, const TargetRegisterClass *CurRC, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const
Applies the constraints (def/use) implied by the OpIdx operand to the given CurRC.
unsigned getLiveInPhysReg(unsigned VReg) const
getLiveInPhysReg - If VReg is a live-in virtual register, return the corresponding live-in physical r...
MachineInstr * getVRegDef(unsigned Reg) const
getVRegDef - Return the machine instr that defines the specified virtual register or null if none is ...
defusechain_iterator - This class provides iterator support for machine operands in the function that...
static cl::opt< bool > EnableSubRegLiveness("enable-subreg-liveness", cl::Hidden, cl::init(true), cl::desc("Enable subregister liveness tracking."))
void insertVRegByName(StringRef Name, unsigned Reg)
void clearKillFlags(unsigned Reg) const
clearKillFlags - Iterate over all the uses of the given register and clear the kill flag from the Mac...
const RegClassOrRegBank & getRegClassOrRegBank(unsigned Reg) const
Return the register bank or register class of Reg.
MCRegUnitRootIterator enumerates the root registers of a register unit.
livein_iterator livein_end() const
static def_instr_iterator def_instr_end()
virtual const TargetRegisterClass * getLargestLegalSuperClass(const TargetRegisterClass *RC, const MachineFunction &) const
Returns the largest super class of RC that is legal to use in the current sub-target and has the same...
virtual const TargetInstrInfo * getInstrInfo() const
LaneBitmask getLaneMask() const
Returns the combination of all lane masks of register in this class.
virtual const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const =0
Return a null-terminated list of all of the callee-saved registers on this target.
void disableCalleeSavedRegister(unsigned Reg)
Disables the register from the list of CSRs.
const TargetRegisterClass * constrainRegClass(unsigned Reg, const TargetRegisterClass *RC, unsigned MinNumRegs=0)
constrainRegClass - Constrain the register class of the specified virtual register to be a common sub...
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
TargetInstrInfo - Interface to description of machine instruction set.
iterator find(const_arg_type_t< KeyT > Val)
Definition: DenseMap.h:146
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
unsigned getNumRegs() const
Return the number of registers this target has (useful for sizing arrays holding per register informa...
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:406
void addLiveIn(MCPhysReg PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())
Adds the specified register as a live in.
const TargetRegisterInfo * getTargetRegisterInfo() const
unsigned const MachineRegisterInfo * MRI
Printable printReg(unsigned Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubRegIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
bool isCallerPreservedOrConstPhysReg(unsigned PhysReg) const
Returns true if either isConstantPhysReg or TRI->isCallerPreservedPhysReg returns true...
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineInstrBuilder & UseMI
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
LLVM_ATTRIBUTE_ALWAYS_INLINE iterator begin()
Definition: SmallVector.h:116
void setType(unsigned VReg, LLT Ty)
Set the low-level type of VReg to Ty.
MCRegAliasIterator enumerates all registers aliasing Reg.
use_instr_iterator use_instr_begin(unsigned RegNo) const
VRegToTypeMap & getVRegToType() const
Accessor for VRegToType.
void substPhysReg(unsigned Reg, const TargetRegisterInfo &)
substPhysReg - Substitute the current register with the physical register Reg, taking any existing Su...
bool def_empty(unsigned RegNo) const
def_empty - Return true if there are no instructions defining the specified register (it may be live-...
const RegisterBank * getRegBankOrNull(unsigned Reg) const
Return the register bank of Reg, or null if Reg has not been assigned a register bank or has been ass...
void setCalleeSavedRegs(ArrayRef< MCPhysReg > CSRs)
Sets the updated Callee Saved Registers list.
unsigned getNumVirtRegs() const
getNumVirtRegs - Return the number of virtual registers created.
virtual bool isConstantPhysReg(unsigned PhysReg) const
Returns true if PhysReg is unallocatable and constant throughout the function.
iterator erase(const_iterator CI)
Definition: SmallVector.h:447
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
static const Function * getCalledFunction(const MachineInstr &MI)
bool isConstantPhysReg(unsigned PhysReg) const
Returns true if PhysReg is unallocatable and constant throughout the function.
unsigned first
unsigned createGenericVirtualRegister(LLT Ty, StringRef Name="")
Create and return a new generic virtual register with low-level type Ty.
iterator_range< T > make_range(T x, T y)
Convenience function for iterating over sub-ranges.
unsigned createIncompleteVirtualRegister(StringRef Name="")
Creates a new virtual register that has no register class, register bank or size assigned yet...
iterator_range< use_iterator > use_operands(unsigned Reg) const
bool isDebugValue() const
Definition: MachineInstr.h:819
MachineOperand class - Representation of each machine instruction operand.
bool atEnd() const
atEnd - return true if this iterator is equal to reg_end() on the value.
bool isReservedRegUnit(unsigned Unit) const
Returns true when the given register unit is considered reserved.
reg_iterator reg_begin(unsigned RegNo) const
This class implements the register bank concept.
Definition: RegisterBank.h:29
bool recomputeRegClass(unsigned Reg)
recomputeRegClass - Try to find a legal super-class of Reg&#39;s register class that still satisfies the ...
MachineInstr * getUniqueVRegDef(unsigned Reg) const
getUniqueVRegDef - Return the unique machine instr that defines the specified virtual register or nul...
const Function & getFunction() const
Return the LLVM function that this machine code represents.
bool isPhysRegUsed(unsigned PhysReg) const
Return true if the specified register is modified or read in this function.
virtual BitVector getReservedRegs(const MachineFunction &MF) const =0
Returns a bitset indexed by physical register number indicating if a register is a special register t...
bool isValid() const
isValid - returns true if this iterator is not yet at the end.
void verifyUseList(unsigned Reg) const
Verify the sanity of the use list for Reg.
void dumpUses(unsigned RegNo) const
def_instr_iterator def_instr_begin(unsigned RegNo) const
void replaceRegWith(unsigned FromReg, unsigned ToReg)
replaceRegWith - Replace all instances of FromReg with ToReg in the machine function.
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:142
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
bool isLiveIn(unsigned Reg) const
Representation of each machine instruction.
Definition: MachineInstr.h:60
std::vector< std::pair< unsigned, unsigned > >::const_iterator livein_iterator
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
LLVM_ATTRIBUTE_ALWAYS_INLINE iterator end()
Definition: SmallVector.h:120
pointer data()
Return a pointer to the vector&#39;s buffer, even if empty().
Definition: SmallVector.h:143
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode...
Definition: MCInstrInfo.h:45
void setReg(unsigned Reg)
Change the register this operand corresponds to.
#define I(x, y, z)
Definition: MD5.cpp:58
iterator end()
Definition: DenseMap.h:79
LLT getType(unsigned VReg) const
Get the low-level type of VReg or LLT{} if VReg is not a generic (target independent) virtual registe...
virtual bool isCallerPreservedPhysReg(unsigned PhysReg, const MachineFunction &MF) const
Physical registers that may be modified within a function but are guaranteed to be restored before an...
LLVM_NODISCARD std::enable_if<!is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
Definition: Casting.h:323
void markUsesInDebugValueAsUndef(unsigned Reg) const
markUsesInDebugValueAsUndef - Mark every DBG_VALUE referencing the specified register as undefined wh...
size_type size() const
size - Returns the number of bits in this bitvector.
Definition: BitVector.h:170
bool isAllocatable() const
Return true if this register class may be used to create virtual registers.
bool hasOneNonDBGUse(unsigned RegNo) const
hasOneNonDBGUse - Return true if there is exactly one non-Debug instruction using the specified regis...
bool isReg() const
isReg - Tests if this is a MO_Register operand.
iterator_range< use_instr_iterator > use_instructions(unsigned Reg) const
const TargetRegisterClass * getRegClassOrNull(unsigned Reg) const
Return the register class of Reg, or null if Reg has not been assigned a register class yet...
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static def_iterator def_end()
MachineRegisterInfo(MachineFunction *MF)
static bool isNoReturnDef(const MachineOperand &MO)
void moveOperands(MachineOperand *Dst, MachineOperand *Src, unsigned NumOps)
Move NumOps operands from Src to Dst, updating use-def lists as needed.
static use_instr_iterator use_instr_end()
const MCPhysReg * getCalleeSavedRegs() const
Returns list of callee saved registers.
IRTranslator LLVM IR MI
void setRegClass(unsigned Reg, const TargetRegisterClass *RC)
setRegClass - Set the register class of the specified virtual register.
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:49
virtual void MRI_NoteNewVirtualRegister(unsigned Reg)=0
bool isValid() const
Check if the iterator is at the end of the list.
static reg_iterator reg_end()
unsigned getLiveInVirtReg(unsigned PReg) const
getLiveInVirtReg - If PReg is a live-in physical register, return the corresponding live-in physical ...
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:298
reg_begin/reg_end - Provide iteration support to walk over all definitions and uses of a register wit...
unsigned createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
bool isReserved(unsigned PhysReg) const
isReserved - Returns true when PhysReg is a reserved register.
void addRegOperandToUseList(MachineOperand *MO)
Add MO to the linked list of operands for its register.