LLVM  7.0.0svn
MachineRegisterInfo.cpp
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1 //===- lib/Codegen/MachineRegisterInfo.cpp --------------------------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // Implementation of the MachineRegisterInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13 
25 #include "llvm/IR/Attributes.h"
26 #include "llvm/IR/DebugLoc.h"
27 #include "llvm/IR/Function.h"
28 #include "llvm/MC/MCRegisterInfo.h"
29 #include "llvm/Support/Casting.h"
31 #include "llvm/Support/Compiler.h"
34 #include <cassert>
35 
36 using namespace llvm;
37 
38 static cl::opt<bool> EnableSubRegLiveness("enable-subreg-liveness", cl::Hidden,
39  cl::init(true), cl::desc("Enable subregister liveness tracking."));
40 
41 // Pin the vtable to this file.
42 void MachineRegisterInfo::Delegate::anchor() {}
43 
45  : MF(MF), TracksSubRegLiveness(MF->getSubtarget().enableSubRegLiveness() &&
47  IsUpdatedCSRsInitialized(false) {
48  unsigned NumRegs = getTargetRegisterInfo()->getNumRegs();
49  VRegInfo.reserve(256);
50  RegAllocHints.reserve(256);
51  UsedPhysRegMask.resize(NumRegs);
52  PhysRegUseDefLists.reset(new MachineOperand*[NumRegs]());
53 }
54 
55 /// setRegClass - Set the register class of the specified virtual register.
56 ///
57 void
59  assert(RC && RC->isAllocatable() && "Invalid RC for virtual register");
60  VRegInfo[Reg].first = RC;
61 }
62 
64  const RegisterBank &RegBank) {
65  VRegInfo[Reg].first = &RegBank;
66 }
67 
68 static const TargetRegisterClass *
70  const TargetRegisterClass *OldRC,
71  const TargetRegisterClass *RC, unsigned MinNumRegs) {
72  if (OldRC == RC)
73  return RC;
74  const TargetRegisterClass *NewRC =
75  MRI.getTargetRegisterInfo()->getCommonSubClass(OldRC, RC);
76  if (!NewRC || NewRC == OldRC)
77  return NewRC;
78  if (NewRC->getNumRegs() < MinNumRegs)
79  return nullptr;
80  MRI.setRegClass(Reg, NewRC);
81  return NewRC;
82 }
83 
84 const TargetRegisterClass *
86  const TargetRegisterClass *RC,
87  unsigned MinNumRegs) {
88  return ::constrainRegClass(*this, Reg, getRegClass(Reg), RC, MinNumRegs);
89 }
90 
91 bool
93  unsigned ConstrainingReg,
94  unsigned MinNumRegs) {
95  auto const *OldRC = getRegClassOrNull(Reg);
96  auto const *RC = getRegClassOrNull(ConstrainingReg);
97  // A virtual register at any point must have either a low-level type
98  // or a class assigned, but not both. The only exception is the internals of
99  // GlobalISel's instruction selection pass, which is allowed to temporarily
100  // introduce registers with types and classes both.
101  assert((OldRC || getType(Reg).isValid()) && "Reg has neither class nor type");
102  assert((!OldRC || !getType(Reg).isValid()) && "Reg has class and type both");
103  assert((RC || getType(ConstrainingReg).isValid()) &&
104  "ConstrainingReg has neither class nor type");
105  assert((!RC || !getType(ConstrainingReg).isValid()) &&
106  "ConstrainingReg has class and type both");
107  if (OldRC && RC)
108  return ::constrainRegClass(*this, Reg, OldRC, RC, MinNumRegs);
109  // If one of the virtual registers is generic (used in generic machine
110  // instructions, has a low-level type, doesn't have a class), and the other is
111  // concrete (used in target specific instructions, doesn't have a low-level
112  // type, has a class), we can not unify them.
113  if (OldRC || RC)
114  return false;
115  // At this point, both registers are guaranteed to have a valid low-level
116  // type, and they must agree.
117  if (getType(Reg) != getType(ConstrainingReg))
118  return false;
119  auto const *OldRB = getRegBankOrNull(Reg);
120  auto const *RB = getRegBankOrNull(ConstrainingReg);
121  if (OldRB)
122  return !RB || RB == OldRB;
123  if (RB)
124  setRegBank(Reg, *RB);
125  return true;
126 }
127 
128 bool
130  const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
131  const TargetRegisterClass *OldRC = getRegClass(Reg);
132  const TargetRegisterClass *NewRC =
134 
135  // Stop early if there is no room to grow.
136  if (NewRC == OldRC)
137  return false;
138 
139  // Accumulate constraints from all uses.
140  for (MachineOperand &MO : reg_nodbg_operands(Reg)) {
141  // Apply the effect of the given operand to NewRC.
142  MachineInstr *MI = MO.getParent();
143  unsigned OpNo = &MO - &MI->getOperand(0);
144  NewRC = MI->getRegClassConstraintEffect(OpNo, NewRC, TII,
146  if (!NewRC || NewRC == OldRC)
147  return false;
148  }
149  setRegClass(Reg, NewRC);
150  return true;
151 }
152 
155  VRegInfo.grow(Reg);
156  RegAllocHints.grow(Reg);
157  return Reg;
158 }
159 
160 /// createVirtualRegister - Create and return a new virtual register in the
161 /// function with the specified register class.
162 ///
163 unsigned
165  assert(RegClass && "Cannot create register without RegClass!");
166  assert(RegClass->isAllocatable() &&
167  "Virtual register RegClass must be allocatable.");
168 
169  // New virtual register number.
171  VRegInfo[Reg].first = RegClass;
172  if (TheDelegate)
173  TheDelegate->MRI_NoteNewVirtualRegister(Reg);
174  return Reg;
175 }
176 
177 LLT MachineRegisterInfo::getType(unsigned VReg) const {
179  return TypeIt != getVRegToType().end() ? TypeIt->second : LLT{};
180 }
181 
182 void MachineRegisterInfo::setType(unsigned VReg, LLT Ty) {
183  // Check that VReg doesn't have a class.
184  assert((getRegClassOrRegBank(VReg).isNull() ||
185  !getRegClassOrRegBank(VReg).is<const TargetRegisterClass *>()) &&
186  "Can't set the size of a non-generic virtual register");
187  getVRegToType()[VReg] = Ty;
188 }
189 
190 unsigned
192  // New virtual register number.
194  // FIXME: Should we use a dummy register class?
195  VRegInfo[Reg].first = static_cast<RegisterBank *>(nullptr);
196  getVRegToType()[Reg] = Ty;
197  if (TheDelegate)
198  TheDelegate->MRI_NoteNewVirtualRegister(Reg);
199  return Reg;
200 }
201 
203  getVRegToType().clear();
204 }
205 
206 /// clearVirtRegs - Remove all virtual registers (after physreg assignment).
208 #ifndef NDEBUG
209  for (unsigned i = 0, e = getNumVirtRegs(); i != e; ++i) {
211  if (!VRegInfo[Reg].second)
212  continue;
213  verifyUseList(Reg);
214  llvm_unreachable("Remaining virtual register operands");
215  }
216 #endif
217  VRegInfo.clear();
218  for (auto &I : LiveIns)
219  I.second = 0;
220 }
221 
223 #ifndef NDEBUG
224  bool Valid = true;
225  for (MachineOperand &M : reg_operands(Reg)) {
226  MachineOperand *MO = &M;
227  MachineInstr *MI = MO->getParent();
228  if (!MI) {
229  errs() << printReg(Reg, getTargetRegisterInfo())
230  << " use list MachineOperand " << MO
231  << " has no parent instruction.\n";
232  Valid = false;
233  continue;
234  }
235  MachineOperand *MO0 = &MI->getOperand(0);
236  unsigned NumOps = MI->getNumOperands();
237  if (!(MO >= MO0 && MO < MO0+NumOps)) {
238  errs() << printReg(Reg, getTargetRegisterInfo())
239  << " use list MachineOperand " << MO
240  << " doesn't belong to parent MI: " << *MI;
241  Valid = false;
242  }
243  if (!MO->isReg()) {
244  errs() << printReg(Reg, getTargetRegisterInfo())
245  << " MachineOperand " << MO << ": " << *MO
246  << " is not a register\n";
247  Valid = false;
248  }
249  if (MO->getReg() != Reg) {
250  errs() << printReg(Reg, getTargetRegisterInfo())
251  << " use-list MachineOperand " << MO << ": "
252  << *MO << " is the wrong register\n";
253  Valid = false;
254  }
255  }
256  assert(Valid && "Invalid use list");
257 #endif
258 }
259 
261 #ifndef NDEBUG
262  for (unsigned i = 0, e = getNumVirtRegs(); i != e; ++i)
264  for (unsigned i = 1, e = getTargetRegisterInfo()->getNumRegs(); i != e; ++i)
265  verifyUseList(i);
266 #endif
267 }
268 
269 /// Add MO to the linked list of operands for its register.
271  assert(!MO->isOnRegUseList() && "Already on list");
272  MachineOperand *&HeadRef = getRegUseDefListHead(MO->getReg());
273  MachineOperand *const Head = HeadRef;
274 
275  // Head points to the first list element.
276  // Next is NULL on the last list element.
277  // Prev pointers are circular, so Head->Prev == Last.
278 
279  // Head is NULL for an empty list.
280  if (!Head) {
281  MO->Contents.Reg.Prev = MO;
282  MO->Contents.Reg.Next = nullptr;
283  HeadRef = MO;
284  return;
285  }
286  assert(MO->getReg() == Head->getReg() && "Different regs on the same list!");
287 
288  // Insert MO between Last and Head in the circular Prev chain.
289  MachineOperand *Last = Head->Contents.Reg.Prev;
290  assert(Last && "Inconsistent use list");
291  assert(MO->getReg() == Last->getReg() && "Different regs on the same list!");
292  Head->Contents.Reg.Prev = MO;
293  MO->Contents.Reg.Prev = Last;
294 
295  // Def operands always precede uses. This allows def_iterator to stop early.
296  // Insert def operands at the front, and use operands at the back.
297  if (MO->isDef()) {
298  // Insert def at the front.
299  MO->Contents.Reg.Next = Head;
300  HeadRef = MO;
301  } else {
302  // Insert use at the end.
303  MO->Contents.Reg.Next = nullptr;
304  Last->Contents.Reg.Next = MO;
305  }
306 }
307 
308 /// Remove MO from its use-def list.
310  assert(MO->isOnRegUseList() && "Operand not on use list");
311  MachineOperand *&HeadRef = getRegUseDefListHead(MO->getReg());
312  MachineOperand *const Head = HeadRef;
313  assert(Head && "List already empty");
314 
315  // Unlink this from the doubly linked list of operands.
316  MachineOperand *Next = MO->Contents.Reg.Next;
317  MachineOperand *Prev = MO->Contents.Reg.Prev;
318 
319  // Prev links are circular, next link is NULL instead of looping back to Head.
320  if (MO == Head)
321  HeadRef = Next;
322  else
323  Prev->Contents.Reg.Next = Next;
324 
325  (Next ? Next : Head)->Contents.Reg.Prev = Prev;
326 
327  MO->Contents.Reg.Prev = nullptr;
328  MO->Contents.Reg.Next = nullptr;
329 }
330 
331 /// Move NumOps operands from Src to Dst, updating use-def lists as needed.
332 ///
333 /// The Dst range is assumed to be uninitialized memory. (Or it may contain
334 /// operands that won't be destroyed, which is OK because the MO destructor is
335 /// trivial anyway).
336 ///
337 /// The Src and Dst ranges may overlap.
339  MachineOperand *Src,
340  unsigned NumOps) {
341  assert(Src != Dst && NumOps && "Noop moveOperands");
342 
343  // Copy backwards if Dst is within the Src range.
344  int Stride = 1;
345  if (Dst >= Src && Dst < Src + NumOps) {
346  Stride = -1;
347  Dst += NumOps - 1;
348  Src += NumOps - 1;
349  }
350 
351  // Copy one operand at a time.
352  do {
353  new (Dst) MachineOperand(*Src);
354 
355  // Dst takes Src's place in the use-def chain.
356  if (Src->isReg()) {
357  MachineOperand *&Head = getRegUseDefListHead(Src->getReg());
358  MachineOperand *Prev = Src->Contents.Reg.Prev;
359  MachineOperand *Next = Src->Contents.Reg.Next;
360  assert(Head && "List empty, but operand is chained");
361  assert(Prev && "Operand was not on use-def list");
362 
363  // Prev links are circular, next link is NULL instead of looping back to
364  // Head.
365  if (Src == Head)
366  Head = Dst;
367  else
368  Prev->Contents.Reg.Next = Dst;
369 
370  // Update Prev pointer. This also works when Src was pointing to itself
371  // in a 1-element list. In that case Head == Dst.
372  (Next ? Next : Head)->Contents.Reg.Prev = Dst;
373  }
374 
375  Dst += Stride;
376  Src += Stride;
377  } while (--NumOps);
378 }
379 
380 /// replaceRegWith - Replace all instances of FromReg with ToReg in the
381 /// machine function. This is like llvm-level X->replaceAllUsesWith(Y),
382 /// except that it also changes any definitions of the register as well.
383 /// If ToReg is a physical register we apply the sub register to obtain the
384 /// final/proper physical register.
385 void MachineRegisterInfo::replaceRegWith(unsigned FromReg, unsigned ToReg) {
386  assert(FromReg != ToReg && "Cannot replace a reg with itself");
387 
389 
390  // TODO: This could be more efficient by bulk changing the operands.
391  for (reg_iterator I = reg_begin(FromReg), E = reg_end(); I != E; ) {
392  MachineOperand &O = *I;
393  ++I;
395  O.substPhysReg(ToReg, *TRI);
396  } else {
397  O.setReg(ToReg);
398  }
399  }
400 }
401 
402 /// getVRegDef - Return the machine instr that defines the specified virtual
403 /// register or null if none is found. This assumes that the code is in SSA
404 /// form, so there should only be one definition.
406  // Since we are in SSA form, we can use the first definition.
408  assert((I.atEnd() || std::next(I) == def_instr_end()) &&
409  "getVRegDef assumes a single definition or no definition");
410  return !I.atEnd() ? &*I : nullptr;
411 }
412 
413 /// getUniqueVRegDef - Return the unique machine instr that defines the
414 /// specified virtual register or null if none is found. If there are
415 /// multiple definitions or no definition, return null.
417  if (def_empty(Reg)) return nullptr;
419  if (std::next(I) != def_instr_end())
420  return nullptr;
421  return &*I;
422 }
423 
424 bool MachineRegisterInfo::hasOneNonDBGUse(unsigned RegNo) const {
426  if (UI == use_nodbg_end())
427  return false;
428  return ++UI == use_nodbg_end();
429 }
430 
431 /// clearKillFlags - Iterate over all the uses of the given register and
432 /// clear the kill flag from the MachineOperand. This function is used by
433 /// optimization passes which extend register lifetimes and need only
434 /// preserve conservative kill flag information.
436  for (MachineOperand &MO : use_operands(Reg))
437  MO.setIsKill(false);
438 }
439 
440 bool MachineRegisterInfo::isLiveIn(unsigned Reg) const {
441  for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I)
442  if (I->first == Reg || I->second == Reg)
443  return true;
444  return false;
445 }
446 
447 /// getLiveInPhysReg - If VReg is a live-in virtual register, return the
448 /// corresponding live-in physical register.
449 unsigned MachineRegisterInfo::getLiveInPhysReg(unsigned VReg) const {
450  for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I)
451  if (I->second == VReg)
452  return I->first;
453  return 0;
454 }
455 
456 /// getLiveInVirtReg - If PReg is a live-in physical register, return the
457 /// corresponding live-in physical register.
458 unsigned MachineRegisterInfo::getLiveInVirtReg(unsigned PReg) const {
459  for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I)
460  if (I->first == PReg)
461  return I->second;
462  return 0;
463 }
464 
465 /// EmitLiveInCopies - Emit copies to initialize livein virtual registers
466 /// into the given entry block.
467 void
469  const TargetRegisterInfo &TRI,
470  const TargetInstrInfo &TII) {
471  // Emit the copies into the top of the block.
472  for (unsigned i = 0, e = LiveIns.size(); i != e; ++i)
473  if (LiveIns[i].second) {
474  if (use_nodbg_empty(LiveIns[i].second)) {
475  // The livein has no non-dbg uses. Drop it.
476  //
477  // It would be preferable to have isel avoid creating live-in
478  // records for unused arguments in the first place, but it's
479  // complicated by the debug info code for arguments.
480  LiveIns.erase(LiveIns.begin() + i);
481  --i; --e;
482  } else {
483  // Emit a copy.
484  BuildMI(*EntryMBB, EntryMBB->begin(), DebugLoc(),
485  TII.get(TargetOpcode::COPY), LiveIns[i].second)
486  .addReg(LiveIns[i].first);
487 
488  // Add the register to the entry block live-in set.
489  EntryMBB->addLiveIn(LiveIns[i].first);
490  }
491  } else {
492  // Add the register to the entry block live-in set.
493  EntryMBB->addLiveIn(LiveIns[i].first);
494  }
495 }
496 
498  // Lane masks are only defined for vregs.
500  const TargetRegisterClass &TRC = *getRegClass(Reg);
501  return TRC.getLaneMask();
502 }
503 
504 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
506  for (MachineInstr &I : use_instructions(Reg))
507  I.dump();
508 }
509 #endif
510 
512  ReservedRegs = getTargetRegisterInfo()->getReservedRegs(MF);
513  assert(ReservedRegs.size() == getTargetRegisterInfo()->getNumRegs() &&
514  "Invalid ReservedRegs vector from target");
515 }
516 
517 bool MachineRegisterInfo::isConstantPhysReg(unsigned PhysReg) const {
519 
521  if (TRI->isConstantPhysReg(PhysReg))
522  return true;
523 
524  // Check if any overlapping register is modified, or allocatable so it may be
525  // used later.
526  for (MCRegAliasIterator AI(PhysReg, TRI, true);
527  AI.isValid(); ++AI)
528  if (!def_empty(*AI) || isAllocatable(*AI))
529  return false;
530  return true;
531 }
532 
533 bool
536  return isConstantPhysReg(PhysReg) ||
537  TRI->isCallerPreservedPhysReg(PhysReg, *MF);
538 }
539 
540 /// markUsesInDebugValueAsUndef - Mark every DBG_VALUE referencing the
541 /// specified register as undefined which causes the DBG_VALUE to be
542 /// deleted during LiveDebugVariables analysis.
544  // Mark any DBG_VALUE that uses Reg as undef (but don't delete it.)
547  I != E; I = nextI) {
548  nextI = std::next(I); // I is invalidated by the setReg
549  MachineInstr *UseMI = &*I;
550  if (UseMI->isDebugValue())
551  UseMI->getOperand(0).setReg(0U);
552  }
553 }
554 
555 static const Function *getCalledFunction(const MachineInstr &MI) {
556  for (const MachineOperand &MO : MI.operands()) {
557  if (!MO.isGlobal())
558  continue;
559  const Function *Func = dyn_cast<Function>(MO.getGlobal());
560  if (Func != nullptr)
561  return Func;
562  }
563  return nullptr;
564 }
565 
566 static bool isNoReturnDef(const MachineOperand &MO) {
567  // Anything which is not a noreturn function is a real def.
568  const MachineInstr &MI = *MO.getParent();
569  if (!MI.isCall())
570  return false;
571  const MachineBasicBlock &MBB = *MI.getParent();
572  if (!MBB.succ_empty())
573  return false;
574  const MachineFunction &MF = *MBB.getParent();
575  // We need to keep correct unwind information even if the function will
576  // not return, since the runtime may need it.
577  if (MF.getFunction().hasFnAttribute(Attribute::UWTable))
578  return false;
579  const Function *Called = getCalledFunction(MI);
580  return !(Called == nullptr || !Called->hasFnAttribute(Attribute::NoReturn) ||
581  !Called->hasFnAttribute(Attribute::NoUnwind));
582 }
583 
585  bool SkipNoReturnDef) const {
586  if (UsedPhysRegMask.test(PhysReg))
587  return true;
589  for (MCRegAliasIterator AI(PhysReg, TRI, true); AI.isValid(); ++AI) {
590  for (const MachineOperand &MO : make_range(def_begin(*AI), def_end())) {
591  if (!SkipNoReturnDef && isNoReturnDef(MO))
592  continue;
593  return true;
594  }
595  }
596  return false;
597 }
598 
599 bool MachineRegisterInfo::isPhysRegUsed(unsigned PhysReg) const {
600  if (UsedPhysRegMask.test(PhysReg))
601  return true;
603  for (MCRegAliasIterator AliasReg(PhysReg, TRI, true); AliasReg.isValid();
604  ++AliasReg) {
605  if (!reg_nodbg_empty(*AliasReg))
606  return true;
607  }
608  return false;
609 }
610 
612 
614  assert(Reg && (Reg < TRI->getNumRegs()) &&
615  "Trying to disable an invalid register");
616 
617  if (!IsUpdatedCSRsInitialized) {
618  const MCPhysReg *CSR = TRI->getCalleeSavedRegs(MF);
619  for (const MCPhysReg *I = CSR; *I; ++I)
620  UpdatedCSRs.push_back(*I);
621 
622  // Zero value represents the end of the register list
623  // (no more registers should be pushed).
624  UpdatedCSRs.push_back(0);
625 
626  IsUpdatedCSRsInitialized = true;
627  }
628 
629  // Remove the register (and its aliases from the list).
630  for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI)
631  UpdatedCSRs.erase(std::remove(UpdatedCSRs.begin(), UpdatedCSRs.end(), *AI),
632  UpdatedCSRs.end());
633 }
634 
636  if (IsUpdatedCSRsInitialized)
637  return UpdatedCSRs.data();
638 
640 }
641 
643  if (IsUpdatedCSRsInitialized)
644  UpdatedCSRs.clear();
645 
646  for (MCPhysReg Reg : CSRs)
647  UpdatedCSRs.push_back(Reg);
648 
649  // Zero value represents the end of the register list
650  // (no more registers should be pushed).
651  UpdatedCSRs.push_back(0);
652  IsUpdatedCSRsInitialized = true;
653 }
654 
655 bool MachineRegisterInfo::isReservedRegUnit(unsigned Unit) const {
657  for (MCRegUnitRootIterator Root(Unit, TRI); Root.isValid(); ++Root) {
658  bool IsRootReserved = true;
659  for (MCSuperRegIterator Super(*Root, TRI, /*IncludeSelf=*/true);
660  Super.isValid(); ++Super) {
661  unsigned Reg = *Super;
662  if (!isReserved(Reg)) {
663  IsRootReserved = false;
664  break;
665  }
666  }
667  if (IsRootReserved)
668  return true;
669  }
670  return false;
671 }
bool reg_nodbg_empty(unsigned RegNo) const
reg_nodbg_empty - Return true if the only instructions using or defining Reg are Debug instructions...
void resize(unsigned N, bool t=false)
resize - Grow or shrink the bitvector.
Definition: BitVector.h:372
const TargetRegisterClass * getCommonSubClass(const TargetRegisterClass *A, const TargetRegisterClass *B, const MVT::SimpleValueType SVT=MVT::SimpleValueType::Any) const
Find the largest common subclass of A and B.
void push_back(const T &Elt)
Definition: SmallVector.h:212
void EmitLiveInCopies(MachineBasicBlock *EntryMBB, const TargetRegisterInfo &TRI, const TargetInstrInfo &TII)
EmitLiveInCopies - Emit copies to initialize livein virtual registers into the given entry block...
raw_ostream & errs()
This returns a reference to a raw_ostream for standard error.
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
bool use_nodbg_empty(unsigned RegNo) const
use_nodbg_empty - Return true if there are no non-Debug instructions using the specified register...
bool isCall(QueryType Type=AnyInBundle) const
Definition: MachineInstr.h:461
const TargetRegisterClass * getRegClass(unsigned Reg) const
Return the register class of the specified virtual register.
livein_iterator livein_begin() const
void removeRegOperandFromUseList(MachineOperand *MO)
Remove MO from its use-def list.
bool isAllocatable(unsigned PhysReg) const
isAllocatable - Returns true when PhysReg belongs to an allocatable register class and it hasn&#39;t been...
void clearVirtRegTypes()
Remove all types associated to virtual registers (after instruction selection and constraining of all...
LaneBitmask getMaxLaneMaskForVReg(unsigned Reg) const
Returns a mask covering all bits that can appear in lane masks of subregisters of the virtual registe...
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
#define LLVM_DUMP_METHOD
Mark debug helper function definitions like dump() that should not be stripped from debug builds...
Definition: Compiler.h:449
unsigned getNumRegs() const
Return the number of registers in this class.
static const TargetRegisterClass * constrainRegClass(MachineRegisterInfo &MRI, unsigned Reg, const TargetRegisterClass *OldRC, const TargetRegisterClass *RC, unsigned MinNumRegs)
static unsigned index2VirtReg(unsigned Index)
Convert a 0-based index to a virtual register number.
unsigned createVirtualRegister(const TargetRegisterClass *RegClass)
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
std::error_code remove(const Twine &path, bool IgnoreNonExisting=true)
Remove path.
bool isPhysRegModified(unsigned PhysReg, bool SkipNoReturnDef=false) const
Return true if the specified register is modified in this function.
This provides a very simple, boring adaptor for a begin and end iterator into a range type...
unsigned getReg() const
getReg - Returns the register number.
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
iterator_range< reg_nodbg_iterator > reg_nodbg_operands(unsigned Reg) const
bool test(unsigned Idx) const
Definition: BitVector.h:502
iterator_range< reg_iterator > reg_operands(unsigned Reg) const
bool constrainRegAttrs(unsigned Reg, unsigned ConstrainingReg, unsigned MinNumRegs=0)
Constrain the register class or the register bank of the virtual register Reg to be a common subclass...
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
Definition: Function.h:302
unsigned second
A debug info location.
Definition: DebugLoc.h:34
void setRegBank(unsigned Reg, const RegisterBank &RegBank)
Set the register bank to RegBank for Reg.
unsigned createGenericVirtualRegister(LLT Ty)
Create and return a new generic virtual register with low-level type Ty.
iterator_range< mop_iterator > operands()
Definition: MachineInstr.h:335
use_nodbg_iterator use_nodbg_begin(unsigned RegNo) const
void verifyUseLists() const
Verify the use list of all registers.
static use_nodbg_iterator use_nodbg_end()
void clearVirtRegs()
clearVirtRegs - Remove all virtual registers (after physreg assignment).
MCSuperRegIterator enumerates all super-registers of Reg.
const HexagonInstrInfo * TII
unsigned getNumOperands() const
Access to explicit operands of the instruction.
Definition: MachineInstr.h:296
void freezeReservedRegs(const MachineFunction &)
freezeReservedRegs - Called by the register allocator to freeze the set of reserved registers before ...
Reg
All possible values of the reg field in the ModR/M byte.
This file contains the simple types necessary to represent the attributes associated with functions a...
def_iterator def_begin(unsigned RegNo) const
const TargetRegisterClass * getRegClassConstraintEffect(unsigned OpIdx, const TargetRegisterClass *CurRC, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const
Applies the constraints (def/use) implied by the OpIdx operand to the given CurRC.
unsigned getLiveInPhysReg(unsigned VReg) const
getLiveInPhysReg - If VReg is a live-in virtual register, return the corresponding live-in physical r...
MachineInstr * getVRegDef(unsigned Reg) const
getVRegDef - Return the machine instr that defines the specified virtual register or null if none is ...
defusechain_iterator - This class provides iterator support for machine operands in the function that...
static cl::opt< bool > EnableSubRegLiveness("enable-subreg-liveness", cl::Hidden, cl::init(true), cl::desc("Enable subregister liveness tracking."))
Printable printReg(unsigned Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubRegIdx=0)
Prints virtual and physical registers with or without a TRI instance.
void clearKillFlags(unsigned Reg) const
clearKillFlags - Iterate over all the uses of the given register and clear the kill flag from the Mac...
const RegClassOrRegBank & getRegClassOrRegBank(unsigned Reg) const
Return the register bank or register class of Reg.
MCRegUnitRootIterator enumerates the root registers of a register unit.
livein_iterator livein_end() const
static def_instr_iterator def_instr_end()
virtual const TargetRegisterClass * getLargestLegalSuperClass(const TargetRegisterClass *RC, const MachineFunction &) const
Returns the largest super class of RC that is legal to use in the current sub-target and has the same...
virtual const TargetInstrInfo * getInstrInfo() const
LaneBitmask getLaneMask() const
Returns the combination of all lane masks of register in this class.
virtual const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const =0
Return a null-terminated list of all of the callee-saved registers on this target.
void disableCalleeSavedRegister(unsigned Reg)
Disables the register from the list of CSRs.
const TargetRegisterClass * constrainRegClass(unsigned Reg, const TargetRegisterClass *RC, unsigned MinNumRegs=0)
constrainRegClass - Constrain the register class of the specified virtual register to be a common sub...
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
TargetInstrInfo - Interface to description of machine instruction set.
iterator find(const_arg_type_t< KeyT > Val)
Definition: DenseMap.h:146
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
unsigned getNumRegs() const
Return the number of registers this target has (useful for sizing arrays holding per register informa...
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:406
void addLiveIn(MCPhysReg PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())
Adds the specified register as a live in.
const TargetRegisterInfo * getTargetRegisterInfo() const
unsigned const MachineRegisterInfo * MRI
bool isCallerPreservedOrConstPhysReg(unsigned PhysReg) const
Returns true if either isConstantPhysReg or TRI->isCallerPreservedPhysReg returns true...
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineInstrBuilder & UseMI
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
LLVM_ATTRIBUTE_ALWAYS_INLINE iterator begin()
Definition: SmallVector.h:116
void setType(unsigned VReg, LLT Ty)
Set the low-level type of VReg to Ty.
MCRegAliasIterator enumerates all registers aliasing Reg.
unsigned createIncompleteVirtualRegister()
Creates a new virtual register that has no register class, register bank or size assigned yet...
use_instr_iterator use_instr_begin(unsigned RegNo) const
VRegToTypeMap & getVRegToType() const
Accessor for VRegToType.
void substPhysReg(unsigned Reg, const TargetRegisterInfo &)
substPhysReg - Substitute the current register with the physical register Reg, taking any existing Su...
bool def_empty(unsigned RegNo) const
def_empty - Return true if there are no instructions defining the specified register (it may be live-...
const RegisterBank * getRegBankOrNull(unsigned Reg) const
Return the register bank of Reg, or null if Reg has not been assigned a register bank or has been ass...
void setCalleeSavedRegs(ArrayRef< MCPhysReg > CSRs)
Sets the updated Callee Saved Registers list.
unsigned getNumVirtRegs() const
getNumVirtRegs - Return the number of virtual registers created.
virtual bool isConstantPhysReg(unsigned PhysReg) const
Returns true if PhysReg is unallocatable and constant throughout the function.
iterator erase(const_iterator CI)
Definition: SmallVector.h:447
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
static const Function * getCalledFunction(const MachineInstr &MI)
bool isConstantPhysReg(unsigned PhysReg) const
Returns true if PhysReg is unallocatable and constant throughout the function.
unsigned first
iterator_range< T > make_range(T x, T y)
Convenience function for iterating over sub-ranges.
iterator_range< use_iterator > use_operands(unsigned Reg) const
bool isDebugValue() const
Definition: MachineInstr.h:819
MachineOperand class - Representation of each machine instruction operand.
bool atEnd() const
atEnd - return true if this iterator is equal to reg_end() on the value.
bool isReservedRegUnit(unsigned Unit) const
Returns true when the given register unit is considered reserved.
reg_iterator reg_begin(unsigned RegNo) const
This class implements the register bank concept.
Definition: RegisterBank.h:29
bool recomputeRegClass(unsigned Reg)
recomputeRegClass - Try to find a legal super-class of Reg&#39;s register class that still satisfies the ...
MachineInstr * getUniqueVRegDef(unsigned Reg) const
getUniqueVRegDef - Return the unique machine instr that defines the specified virtual register or nul...
const Function & getFunction() const
Return the LLVM function that this machine code represents.
bool isPhysRegUsed(unsigned PhysReg) const
Return true if the specified register is modified or read in this function.
virtual BitVector getReservedRegs(const MachineFunction &MF) const =0
Returns a bitset indexed by physical register number indicating if a register is a special register t...
bool isValid() const
isValid - returns true if this iterator is not yet at the end.
void verifyUseList(unsigned Reg) const
Verify the sanity of the use list for Reg.
void dumpUses(unsigned RegNo) const
def_instr_iterator def_instr_begin(unsigned RegNo) const
void replaceRegWith(unsigned FromReg, unsigned ToReg)
replaceRegWith - Replace all instances of FromReg with ToReg in the machine function.
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:142
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
bool isLiveIn(unsigned Reg) const
Representation of each machine instruction.
Definition: MachineInstr.h:60
std::vector< std::pair< unsigned, unsigned > >::const_iterator livein_iterator
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
LLVM_ATTRIBUTE_ALWAYS_INLINE iterator end()
Definition: SmallVector.h:120
pointer data()
Return a pointer to the vector&#39;s buffer, even if empty().
Definition: SmallVector.h:143
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode...
Definition: MCInstrInfo.h:45
void setReg(unsigned Reg)
Change the register this operand corresponds to.
#define I(x, y, z)
Definition: MD5.cpp:58
iterator end()
Definition: DenseMap.h:79
LLT getType(unsigned VReg) const
Get the low-level type of VReg or LLT{} if VReg is not a generic (target independent) virtual registe...
virtual bool isCallerPreservedPhysReg(unsigned PhysReg, const MachineFunction &MF) const
Physical registers that may be modified within a function but are guaranteed to be restored before an...
LLVM_NODISCARD std::enable_if<!is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
Definition: Casting.h:323
void markUsesInDebugValueAsUndef(unsigned Reg) const
markUsesInDebugValueAsUndef - Mark every DBG_VALUE referencing the specified register as undefined wh...
size_type size() const
size - Returns the number of bits in this bitvector.
Definition: BitVector.h:170
bool isAllocatable() const
Return true if this register class may be used to create virtual registers.
bool hasOneNonDBGUse(unsigned RegNo) const
hasOneNonDBGUse - Return true if there is exactly one non-Debug instruction using the specified regis...
bool isReg() const
isReg - Tests if this is a MO_Register operand.
struct llvm::MachineOperand::@144::@146 Reg
iterator_range< use_instr_iterator > use_instructions(unsigned Reg) const
const TargetRegisterClass * getRegClassOrNull(unsigned Reg) const
Return the register class of Reg, or null if Reg has not been assigned a register class yet...
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static def_iterator def_end()
MachineRegisterInfo(MachineFunction *MF)
static bool isNoReturnDef(const MachineOperand &MO)
void moveOperands(MachineOperand *Dst, MachineOperand *Src, unsigned NumOps)
Move NumOps operands from Src to Dst, updating use-def lists as needed.
static use_instr_iterator use_instr_end()
const MCPhysReg * getCalleeSavedRegs() const
Returns list of callee saved registers.
IRTranslator LLVM IR MI
void setRegClass(unsigned Reg, const TargetRegisterClass *RC)
setRegClass - Set the register class of the specified virtual register.
virtual void MRI_NoteNewVirtualRegister(unsigned Reg)=0
bool isValid() const
Check if the iterator is at the end of the list.
static reg_iterator reg_end()
unsigned getLiveInVirtReg(unsigned PReg) const
getLiveInVirtReg - If PReg is a live-in physical register, return the corresponding live-in physical ...
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:298
reg_begin/reg_end - Provide iteration support to walk over all definitions and uses of a register wit...
bool isReserved(unsigned PhysReg) const
isReserved - Returns true when PhysReg is a reserved register.
void addRegOperandToUseList(MachineOperand *MO)
Add MO to the linked list of operands for its register.