LLVM  9.0.0svn
MachineRegisterInfo.cpp
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1 //===- lib/Codegen/MachineRegisterInfo.cpp --------------------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // Implementation of the MachineRegisterInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12 
24 #include "llvm/Config/llvm-config.h"
25 #include "llvm/IR/Attributes.h"
26 #include "llvm/IR/DebugLoc.h"
27 #include "llvm/IR/Function.h"
28 #include "llvm/MC/MCRegisterInfo.h"
29 #include "llvm/Support/Casting.h"
31 #include "llvm/Support/Compiler.h"
34 #include <cassert>
35 
36 using namespace llvm;
37 
38 static cl::opt<bool> EnableSubRegLiveness("enable-subreg-liveness", cl::Hidden,
39  cl::init(true), cl::desc("Enable subregister liveness tracking."));
40 
41 // Pin the vtable to this file.
42 void MachineRegisterInfo::Delegate::anchor() {}
43 
45  : MF(MF), TracksSubRegLiveness(MF->getSubtarget().enableSubRegLiveness() &&
47  IsUpdatedCSRsInitialized(false) {
48  unsigned NumRegs = getTargetRegisterInfo()->getNumRegs();
49  VRegInfo.reserve(256);
50  RegAllocHints.reserve(256);
51  UsedPhysRegMask.resize(NumRegs);
52  PhysRegUseDefLists.reset(new MachineOperand*[NumRegs]());
53 }
54 
55 /// setRegClass - Set the register class of the specified virtual register.
56 ///
57 void
59  assert(RC && RC->isAllocatable() && "Invalid RC for virtual register");
60  VRegInfo[Reg].first = RC;
61 }
62 
64  const RegisterBank &RegBank) {
65  VRegInfo[Reg].first = &RegBank;
66 }
67 
68 static const TargetRegisterClass *
70  const TargetRegisterClass *OldRC,
71  const TargetRegisterClass *RC, unsigned MinNumRegs) {
72  if (OldRC == RC)
73  return RC;
74  const TargetRegisterClass *NewRC =
75  MRI.getTargetRegisterInfo()->getCommonSubClass(OldRC, RC);
76  if (!NewRC || NewRC == OldRC)
77  return NewRC;
78  if (NewRC->getNumRegs() < MinNumRegs)
79  return nullptr;
80  MRI.setRegClass(Reg, NewRC);
81  return NewRC;
82 }
83 
84 const TargetRegisterClass *
86  const TargetRegisterClass *RC,
87  unsigned MinNumRegs) {
88  return ::constrainRegClass(*this, Reg, getRegClass(Reg), RC, MinNumRegs);
89 }
90 
91 bool
93  unsigned ConstrainingReg,
94  unsigned MinNumRegs) {
95  const LLT RegTy = getType(Reg);
96  const LLT ConstrainingRegTy = getType(ConstrainingReg);
97  if (RegTy.isValid() && ConstrainingRegTy.isValid() &&
98  RegTy != ConstrainingRegTy)
99  return false;
100  const auto ConstrainingRegCB = getRegClassOrRegBank(ConstrainingReg);
101  if (!ConstrainingRegCB.isNull()) {
102  const auto RegCB = getRegClassOrRegBank(Reg);
103  if (RegCB.isNull())
104  setRegClassOrRegBank(Reg, ConstrainingRegCB);
105  else if (RegCB.is<const TargetRegisterClass *>() !=
106  ConstrainingRegCB.is<const TargetRegisterClass *>())
107  return false;
108  else if (RegCB.is<const TargetRegisterClass *>()) {
109  if (!::constrainRegClass(
110  *this, Reg, RegCB.get<const TargetRegisterClass *>(),
111  ConstrainingRegCB.get<const TargetRegisterClass *>(), MinNumRegs))
112  return false;
113  } else if (RegCB != ConstrainingRegCB)
114  return false;
115  }
116  if (ConstrainingRegTy.isValid())
117  setType(Reg, ConstrainingRegTy);
118  return true;
119 }
120 
121 bool
123  const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
124  const TargetRegisterClass *OldRC = getRegClass(Reg);
125  const TargetRegisterClass *NewRC =
127 
128  // Stop early if there is no room to grow.
129  if (NewRC == OldRC)
130  return false;
131 
132  // Accumulate constraints from all uses.
133  for (MachineOperand &MO : reg_nodbg_operands(Reg)) {
134  // Apply the effect of the given operand to NewRC.
135  MachineInstr *MI = MO.getParent();
136  unsigned OpNo = &MO - &MI->getOperand(0);
137  NewRC = MI->getRegClassConstraintEffect(OpNo, NewRC, TII,
139  if (!NewRC || NewRC == OldRC)
140  return false;
141  }
142  setRegClass(Reg, NewRC);
143  return true;
144 }
145 
148  VRegInfo.grow(Reg);
149  RegAllocHints.grow(Reg);
150  insertVRegByName(Name, Reg);
151  return Reg;
152 }
153 
154 /// createVirtualRegister - Create and return a new virtual register in the
155 /// function with the specified register class.
156 ///
157 unsigned
159  StringRef Name) {
160  assert(RegClass && "Cannot create register without RegClass!");
161  assert(RegClass->isAllocatable() &&
162  "Virtual register RegClass must be allocatable.");
163 
164  // New virtual register number.
165  unsigned Reg = createIncompleteVirtualRegister(Name);
166  VRegInfo[Reg].first = RegClass;
167  if (TheDelegate)
168  TheDelegate->MRI_NoteNewVirtualRegister(Reg);
169  return Reg;
170 }
171 
173  StringRef Name) {
174  unsigned Reg = createIncompleteVirtualRegister(Name);
175  VRegInfo[Reg].first = VRegInfo[VReg].first;
176  setType(Reg, getType(VReg));
177  if (TheDelegate)
178  TheDelegate->MRI_NoteNewVirtualRegister(Reg);
179  return Reg;
180 }
181 
182 void MachineRegisterInfo::setType(unsigned VReg, LLT Ty) {
183  VRegToType.grow(VReg);
184  VRegToType[VReg] = Ty;
185 }
186 
187 unsigned
189  // New virtual register number.
190  unsigned Reg = createIncompleteVirtualRegister(Name);
191  // FIXME: Should we use a dummy register class?
192  VRegInfo[Reg].first = static_cast<RegisterBank *>(nullptr);
193  setType(Reg, Ty);
194  if (TheDelegate)
195  TheDelegate->MRI_NoteNewVirtualRegister(Reg);
196  return Reg;
197 }
198 
200 
201 /// clearVirtRegs - Remove all virtual registers (after physreg assignment).
203 #ifndef NDEBUG
204  for (unsigned i = 0, e = getNumVirtRegs(); i != e; ++i) {
206  if (!VRegInfo[Reg].second)
207  continue;
208  verifyUseList(Reg);
209  llvm_unreachable("Remaining virtual register operands");
210  }
211 #endif
212  VRegInfo.clear();
213  for (auto &I : LiveIns)
214  I.second = 0;
215 }
216 
218 #ifndef NDEBUG
219  bool Valid = true;
220  for (MachineOperand &M : reg_operands(Reg)) {
221  MachineOperand *MO = &M;
222  MachineInstr *MI = MO->getParent();
223  if (!MI) {
224  errs() << printReg(Reg, getTargetRegisterInfo())
225  << " use list MachineOperand " << MO
226  << " has no parent instruction.\n";
227  Valid = false;
228  continue;
229  }
230  MachineOperand *MO0 = &MI->getOperand(0);
231  unsigned NumOps = MI->getNumOperands();
232  if (!(MO >= MO0 && MO < MO0+NumOps)) {
233  errs() << printReg(Reg, getTargetRegisterInfo())
234  << " use list MachineOperand " << MO
235  << " doesn't belong to parent MI: " << *MI;
236  Valid = false;
237  }
238  if (!MO->isReg()) {
239  errs() << printReg(Reg, getTargetRegisterInfo())
240  << " MachineOperand " << MO << ": " << *MO
241  << " is not a register\n";
242  Valid = false;
243  }
244  if (MO->getReg() != Reg) {
245  errs() << printReg(Reg, getTargetRegisterInfo())
246  << " use-list MachineOperand " << MO << ": "
247  << *MO << " is the wrong register\n";
248  Valid = false;
249  }
250  }
251  assert(Valid && "Invalid use list");
252 #endif
253 }
254 
256 #ifndef NDEBUG
257  for (unsigned i = 0, e = getNumVirtRegs(); i != e; ++i)
259  for (unsigned i = 1, e = getTargetRegisterInfo()->getNumRegs(); i != e; ++i)
260  verifyUseList(i);
261 #endif
262 }
263 
264 /// Add MO to the linked list of operands for its register.
266  assert(!MO->isOnRegUseList() && "Already on list");
267  MachineOperand *&HeadRef = getRegUseDefListHead(MO->getReg());
268  MachineOperand *const Head = HeadRef;
269 
270  // Head points to the first list element.
271  // Next is NULL on the last list element.
272  // Prev pointers are circular, so Head->Prev == Last.
273 
274  // Head is NULL for an empty list.
275  if (!Head) {
276  MO->Contents.Reg.Prev = MO;
277  MO->Contents.Reg.Next = nullptr;
278  HeadRef = MO;
279  return;
280  }
281  assert(MO->getReg() == Head->getReg() && "Different regs on the same list!");
282 
283  // Insert MO between Last and Head in the circular Prev chain.
284  MachineOperand *Last = Head->Contents.Reg.Prev;
285  assert(Last && "Inconsistent use list");
286  assert(MO->getReg() == Last->getReg() && "Different regs on the same list!");
287  Head->Contents.Reg.Prev = MO;
288  MO->Contents.Reg.Prev = Last;
289 
290  // Def operands always precede uses. This allows def_iterator to stop early.
291  // Insert def operands at the front, and use operands at the back.
292  if (MO->isDef()) {
293  // Insert def at the front.
294  MO->Contents.Reg.Next = Head;
295  HeadRef = MO;
296  } else {
297  // Insert use at the end.
298  MO->Contents.Reg.Next = nullptr;
299  Last->Contents.Reg.Next = MO;
300  }
301 }
302 
303 /// Remove MO from its use-def list.
305  assert(MO->isOnRegUseList() && "Operand not on use list");
306  MachineOperand *&HeadRef = getRegUseDefListHead(MO->getReg());
307  MachineOperand *const Head = HeadRef;
308  assert(Head && "List already empty");
309 
310  // Unlink this from the doubly linked list of operands.
311  MachineOperand *Next = MO->Contents.Reg.Next;
312  MachineOperand *Prev = MO->Contents.Reg.Prev;
313 
314  // Prev links are circular, next link is NULL instead of looping back to Head.
315  if (MO == Head)
316  HeadRef = Next;
317  else
318  Prev->Contents.Reg.Next = Next;
319 
320  (Next ? Next : Head)->Contents.Reg.Prev = Prev;
321 
322  MO->Contents.Reg.Prev = nullptr;
323  MO->Contents.Reg.Next = nullptr;
324 }
325 
326 /// Move NumOps operands from Src to Dst, updating use-def lists as needed.
327 ///
328 /// The Dst range is assumed to be uninitialized memory. (Or it may contain
329 /// operands that won't be destroyed, which is OK because the MO destructor is
330 /// trivial anyway).
331 ///
332 /// The Src and Dst ranges may overlap.
334  MachineOperand *Src,
335  unsigned NumOps) {
336  assert(Src != Dst && NumOps && "Noop moveOperands");
337 
338  // Copy backwards if Dst is within the Src range.
339  int Stride = 1;
340  if (Dst >= Src && Dst < Src + NumOps) {
341  Stride = -1;
342  Dst += NumOps - 1;
343  Src += NumOps - 1;
344  }
345 
346  // Copy one operand at a time.
347  do {
348  new (Dst) MachineOperand(*Src);
349 
350  // Dst takes Src's place in the use-def chain.
351  if (Src->isReg()) {
352  MachineOperand *&Head = getRegUseDefListHead(Src->getReg());
353  MachineOperand *Prev = Src->Contents.Reg.Prev;
354  MachineOperand *Next = Src->Contents.Reg.Next;
355  assert(Head && "List empty, but operand is chained");
356  assert(Prev && "Operand was not on use-def list");
357 
358  // Prev links are circular, next link is NULL instead of looping back to
359  // Head.
360  if (Src == Head)
361  Head = Dst;
362  else
363  Prev->Contents.Reg.Next = Dst;
364 
365  // Update Prev pointer. This also works when Src was pointing to itself
366  // in a 1-element list. In that case Head == Dst.
367  (Next ? Next : Head)->Contents.Reg.Prev = Dst;
368  }
369 
370  Dst += Stride;
371  Src += Stride;
372  } while (--NumOps);
373 }
374 
375 /// replaceRegWith - Replace all instances of FromReg with ToReg in the
376 /// machine function. This is like llvm-level X->replaceAllUsesWith(Y),
377 /// except that it also changes any definitions of the register as well.
378 /// If ToReg is a physical register we apply the sub register to obtain the
379 /// final/proper physical register.
380 void MachineRegisterInfo::replaceRegWith(unsigned FromReg, unsigned ToReg) {
381  assert(FromReg != ToReg && "Cannot replace a reg with itself");
382 
384 
385  // TODO: This could be more efficient by bulk changing the operands.
386  for (reg_iterator I = reg_begin(FromReg), E = reg_end(); I != E; ) {
387  MachineOperand &O = *I;
388  ++I;
390  O.substPhysReg(ToReg, *TRI);
391  } else {
392  O.setReg(ToReg);
393  }
394  }
395 }
396 
397 /// getVRegDef - Return the machine instr that defines the specified virtual
398 /// register or null if none is found. This assumes that the code is in SSA
399 /// form, so there should only be one definition.
401  // Since we are in SSA form, we can use the first definition.
403  assert((I.atEnd() || std::next(I) == def_instr_end()) &&
404  "getVRegDef assumes a single definition or no definition");
405  return !I.atEnd() ? &*I : nullptr;
406 }
407 
408 /// getUniqueVRegDef - Return the unique machine instr that defines the
409 /// specified virtual register or null if none is found. If there are
410 /// multiple definitions or no definition, return null.
412  if (def_empty(Reg)) return nullptr;
414  if (std::next(I) != def_instr_end())
415  return nullptr;
416  return &*I;
417 }
418 
419 bool MachineRegisterInfo::hasOneNonDBGUse(unsigned RegNo) const {
421  if (UI == use_nodbg_end())
422  return false;
423  return ++UI == use_nodbg_end();
424 }
425 
426 /// clearKillFlags - Iterate over all the uses of the given register and
427 /// clear the kill flag from the MachineOperand. This function is used by
428 /// optimization passes which extend register lifetimes and need only
429 /// preserve conservative kill flag information.
431  for (MachineOperand &MO : use_operands(Reg))
432  MO.setIsKill(false);
433 }
434 
435 bool MachineRegisterInfo::isLiveIn(unsigned Reg) const {
436  for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I)
437  if (I->first == Reg || I->second == Reg)
438  return true;
439  return false;
440 }
441 
442 /// getLiveInPhysReg - If VReg is a live-in virtual register, return the
443 /// corresponding live-in physical register.
444 unsigned MachineRegisterInfo::getLiveInPhysReg(unsigned VReg) const {
445  for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I)
446  if (I->second == VReg)
447  return I->first;
448  return 0;
449 }
450 
451 /// getLiveInVirtReg - If PReg is a live-in physical register, return the
452 /// corresponding live-in physical register.
453 unsigned MachineRegisterInfo::getLiveInVirtReg(unsigned PReg) const {
454  for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I)
455  if (I->first == PReg)
456  return I->second;
457  return 0;
458 }
459 
460 /// EmitLiveInCopies - Emit copies to initialize livein virtual registers
461 /// into the given entry block.
462 void
464  const TargetRegisterInfo &TRI,
465  const TargetInstrInfo &TII) {
466  // Emit the copies into the top of the block.
467  for (unsigned i = 0, e = LiveIns.size(); i != e; ++i)
468  if (LiveIns[i].second) {
469  if (use_nodbg_empty(LiveIns[i].second)) {
470  // The livein has no non-dbg uses. Drop it.
471  //
472  // It would be preferable to have isel avoid creating live-in
473  // records for unused arguments in the first place, but it's
474  // complicated by the debug info code for arguments.
475  LiveIns.erase(LiveIns.begin() + i);
476  --i; --e;
477  } else {
478  // Emit a copy.
479  BuildMI(*EntryMBB, EntryMBB->begin(), DebugLoc(),
480  TII.get(TargetOpcode::COPY), LiveIns[i].second)
481  .addReg(LiveIns[i].first);
482 
483  // Add the register to the entry block live-in set.
484  EntryMBB->addLiveIn(LiveIns[i].first);
485  }
486  } else {
487  // Add the register to the entry block live-in set.
488  EntryMBB->addLiveIn(LiveIns[i].first);
489  }
490 }
491 
493  // Lane masks are only defined for vregs.
495  const TargetRegisterClass &TRC = *getRegClass(Reg);
496  return TRC.getLaneMask();
497 }
498 
499 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
501  for (MachineInstr &I : use_instructions(Reg))
502  I.dump();
503 }
504 #endif
505 
507  ReservedRegs = getTargetRegisterInfo()->getReservedRegs(MF);
508  assert(ReservedRegs.size() == getTargetRegisterInfo()->getNumRegs() &&
509  "Invalid ReservedRegs vector from target");
510 }
511 
512 bool MachineRegisterInfo::isConstantPhysReg(unsigned PhysReg) const {
514 
516  if (TRI->isConstantPhysReg(PhysReg))
517  return true;
518 
519  // Check if any overlapping register is modified, or allocatable so it may be
520  // used later.
521  for (MCRegAliasIterator AI(PhysReg, TRI, true);
522  AI.isValid(); ++AI)
523  if (!def_empty(*AI) || isAllocatable(*AI))
524  return false;
525  return true;
526 }
527 
528 bool
531  return isConstantPhysReg(PhysReg) ||
532  TRI->isCallerPreservedPhysReg(PhysReg, *MF);
533 }
534 
535 /// markUsesInDebugValueAsUndef - Mark every DBG_VALUE referencing the
536 /// specified register as undefined which causes the DBG_VALUE to be
537 /// deleted during LiveDebugVariables analysis.
539  // Mark any DBG_VALUE that uses Reg as undef (but don't delete it.)
542  I != E; I = nextI) {
543  nextI = std::next(I); // I is invalidated by the setReg
544  MachineInstr *UseMI = &*I;
545  if (UseMI->isDebugValue())
546  UseMI->getOperand(0).setReg(0U);
547  }
548 }
549 
550 static const Function *getCalledFunction(const MachineInstr &MI) {
551  for (const MachineOperand &MO : MI.operands()) {
552  if (!MO.isGlobal())
553  continue;
554  const Function *Func = dyn_cast<Function>(MO.getGlobal());
555  if (Func != nullptr)
556  return Func;
557  }
558  return nullptr;
559 }
560 
561 static bool isNoReturnDef(const MachineOperand &MO) {
562  // Anything which is not a noreturn function is a real def.
563  const MachineInstr &MI = *MO.getParent();
564  if (!MI.isCall())
565  return false;
566  const MachineBasicBlock &MBB = *MI.getParent();
567  if (!MBB.succ_empty())
568  return false;
569  const MachineFunction &MF = *MBB.getParent();
570  // We need to keep correct unwind information even if the function will
571  // not return, since the runtime may need it.
572  if (MF.getFunction().hasFnAttribute(Attribute::UWTable))
573  return false;
574  const Function *Called = getCalledFunction(MI);
575  return !(Called == nullptr || !Called->hasFnAttribute(Attribute::NoReturn) ||
576  !Called->hasFnAttribute(Attribute::NoUnwind));
577 }
578 
580  bool SkipNoReturnDef) const {
581  if (UsedPhysRegMask.test(PhysReg))
582  return true;
584  for (MCRegAliasIterator AI(PhysReg, TRI, true); AI.isValid(); ++AI) {
585  for (const MachineOperand &MO : make_range(def_begin(*AI), def_end())) {
586  if (!SkipNoReturnDef && isNoReturnDef(MO))
587  continue;
588  return true;
589  }
590  }
591  return false;
592 }
593 
594 bool MachineRegisterInfo::isPhysRegUsed(unsigned PhysReg) const {
595  if (UsedPhysRegMask.test(PhysReg))
596  return true;
598  for (MCRegAliasIterator AliasReg(PhysReg, TRI, true); AliasReg.isValid();
599  ++AliasReg) {
600  if (!reg_nodbg_empty(*AliasReg))
601  return true;
602  }
603  return false;
604 }
605 
607 
609  assert(Reg && (Reg < TRI->getNumRegs()) &&
610  "Trying to disable an invalid register");
611 
612  if (!IsUpdatedCSRsInitialized) {
613  const MCPhysReg *CSR = TRI->getCalleeSavedRegs(MF);
614  for (const MCPhysReg *I = CSR; *I; ++I)
615  UpdatedCSRs.push_back(*I);
616 
617  // Zero value represents the end of the register list
618  // (no more registers should be pushed).
619  UpdatedCSRs.push_back(0);
620 
621  IsUpdatedCSRsInitialized = true;
622  }
623 
624  // Remove the register (and its aliases from the list).
625  for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI)
626  UpdatedCSRs.erase(std::remove(UpdatedCSRs.begin(), UpdatedCSRs.end(), *AI),
627  UpdatedCSRs.end());
628 }
629 
631  if (IsUpdatedCSRsInitialized)
632  return UpdatedCSRs.data();
633 
635 }
636 
638  if (IsUpdatedCSRsInitialized)
639  UpdatedCSRs.clear();
640 
641  for (MCPhysReg Reg : CSRs)
642  UpdatedCSRs.push_back(Reg);
643 
644  // Zero value represents the end of the register list
645  // (no more registers should be pushed).
646  UpdatedCSRs.push_back(0);
647  IsUpdatedCSRsInitialized = true;
648 }
649 
650 bool MachineRegisterInfo::isReservedRegUnit(unsigned Unit) const {
652  for (MCRegUnitRootIterator Root(Unit, TRI); Root.isValid(); ++Root) {
653  bool IsRootReserved = true;
654  for (MCSuperRegIterator Super(*Root, TRI, /*IncludeSelf=*/true);
655  Super.isValid(); ++Super) {
656  unsigned Reg = *Super;
657  if (!isReserved(Reg)) {
658  IsRootReserved = false;
659  break;
660  }
661  }
662  if (IsRootReserved)
663  return true;
664  }
665  return false;
666 }
bool reg_nodbg_empty(unsigned RegNo) const
reg_nodbg_empty - Return true if the only instructions using or defining Reg are Debug instructions...
void resize(unsigned N, bool t=false)
resize - Grow or shrink the bitvector.
Definition: BitVector.h:371
const TargetRegisterClass * getCommonSubClass(const TargetRegisterClass *A, const TargetRegisterClass *B, const MVT::SimpleValueType SVT=MVT::SimpleValueType::Any) const
Find the largest common subclass of A and B.
void EmitLiveInCopies(MachineBasicBlock *EntryMBB, const TargetRegisterInfo &TRI, const TargetInstrInfo &TII)
EmitLiveInCopies - Emit copies to initialize livein virtual registers into the given entry block...
raw_ostream & errs()
This returns a reference to a raw_ostream for standard error.
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
bool use_nodbg_empty(unsigned RegNo) const
use_nodbg_empty - Return true if there are no non-Debug instructions using the specified register...
bool isCall(QueryType Type=AnyInBundle) const
Definition: MachineInstr.h:632
const TargetRegisterClass * getRegClass(unsigned Reg) const
Return the register class of the specified virtual register.
livein_iterator livein_begin() const
void removeRegOperandFromUseList(MachineOperand *MO)
Remove MO from its use-def list.
bool isAllocatable(unsigned PhysReg) const
isAllocatable - Returns true when PhysReg belongs to an allocatable register class and it hasn&#39;t been...
void clearVirtRegTypes()
Remove all types associated to virtual registers (after instruction selection and constraining of all...
LaneBitmask getMaxLaneMaskForVReg(unsigned Reg) const
Returns a mask covering all bits that can appear in lane masks of subregisters of the virtual registe...
This class represents lattice values for constants.
Definition: AllocatorList.h:23
#define LLVM_DUMP_METHOD
Mark debug helper function definitions like dump() that should not be stripped from debug builds...
Definition: Compiler.h:464
unsigned getNumRegs() const
Return the number of registers in this class.
static const TargetRegisterClass * constrainRegClass(MachineRegisterInfo &MRI, unsigned Reg, const TargetRegisterClass *OldRC, const TargetRegisterClass *RC, unsigned MinNumRegs)
static unsigned index2VirtReg(unsigned Index)
Convert a 0-based index to a virtual register number.
amdgpu Simplify well known AMD library false FunctionCallee Value const Twine & Name
std::error_code remove(const Twine &path, bool IgnoreNonExisting=true)
Remove path.
bool isPhysRegModified(unsigned PhysReg, bool SkipNoReturnDef=false) const
Return true if the specified register is modified in this function.
void push_back(const T &Elt)
Definition: SmallVector.h:211
This provides a very simple, boring adaptor for a begin and end iterator into a range type...
unsigned getReg() const
getReg - Returns the register number.
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
iterator_range< reg_nodbg_iterator > reg_nodbg_operands(unsigned Reg) const
unsigned Reg
bool test(unsigned Idx) const
Definition: BitVector.h:501
iterator_range< reg_iterator > reg_operands(unsigned Reg) const
bool constrainRegAttrs(unsigned Reg, unsigned ConstrainingReg, unsigned MinNumRegs=0)
Constrain the register class or the register bank of the virtual register Reg (and low-level type) to...
LLT getType(unsigned Reg) const
Get the low-level type of Reg or LLT{} if Reg is not a generic (target independent) virtual register...
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
Definition: Function.h:320
unsigned second
unsigned const TargetRegisterInfo * TRI
A debug info location.
Definition: DebugLoc.h:33
void setRegBank(unsigned Reg, const RegisterBank &RegBank)
Set the register bank to RegBank for Reg.
iterator_range< mop_iterator > operands()
Definition: MachineInstr.h:458
use_nodbg_iterator use_nodbg_begin(unsigned RegNo) const
void verifyUseLists() const
Verify the use list of all registers.
static use_nodbg_iterator use_nodbg_end()
void clearVirtRegs()
clearVirtRegs - Remove all virtual registers (after physreg assignment).
MCSuperRegIterator enumerates all super-registers of Reg.
const HexagonInstrInfo * TII
unsigned getNumOperands() const
Retuns the total number of operands.
Definition: MachineInstr.h:411
Printable printReg(unsigned Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
void freezeReservedRegs(const MachineFunction &)
freezeReservedRegs - Called by the register allocator to freeze the set of reserved registers before ...
This file contains the simple types necessary to represent the attributes associated with functions a...
def_iterator def_begin(unsigned RegNo) const
const TargetRegisterClass * getRegClassConstraintEffect(unsigned OpIdx, const TargetRegisterClass *CurRC, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const
Applies the constraints (def/use) implied by the OpIdx operand to the given CurRC.
unsigned getLiveInPhysReg(unsigned VReg) const
getLiveInPhysReg - If VReg is a live-in virtual register, return the corresponding live-in physical r...
MachineInstr * getVRegDef(unsigned Reg) const
getVRegDef - Return the machine instr that defines the specified virtual register or null if none is ...
defusechain_iterator - This class provides iterator support for machine operands in the function that...
static cl::opt< bool > EnableSubRegLiveness("enable-subreg-liveness", cl::Hidden, cl::init(true), cl::desc("Enable subregister liveness tracking."))
void insertVRegByName(StringRef Name, unsigned Reg)
void clearKillFlags(unsigned Reg) const
clearKillFlags - Iterate over all the uses of the given register and clear the kill flag from the Mac...
const RegClassOrRegBank & getRegClassOrRegBank(unsigned Reg) const
Return the register bank or register class of Reg.
MCRegUnitRootIterator enumerates the root registers of a register unit.
livein_iterator livein_end() const
static def_instr_iterator def_instr_end()
virtual const TargetRegisterClass * getLargestLegalSuperClass(const TargetRegisterClass *RC, const MachineFunction &) const
Returns the largest super class of RC that is legal to use in the current sub-target and has the same...
virtual const TargetInstrInfo * getInstrInfo() const
LaneBitmask getLaneMask() const
Returns the combination of all lane masks of register in this class.
virtual const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const =0
Return a null-terminated list of all of the callee-saved registers on this target.
void disableCalleeSavedRegister(unsigned Reg)
Disables the register from the list of CSRs.
const TargetRegisterClass * constrainRegClass(unsigned Reg, const TargetRegisterClass *RC, unsigned MinNumRegs=0)
constrainRegClass - Constrain the register class of the specified virtual register to be a common sub...
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
TargetInstrInfo - Interface to description of machine instruction set.
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
unsigned getNumRegs() const
Return the number of registers this target has (useful for sizing arrays holding per register informa...
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:423
void addLiveIn(MCPhysReg PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())
Adds the specified register as a live in.
const TargetRegisterInfo * getTargetRegisterInfo() const
unsigned const MachineRegisterInfo * MRI
bool isCallerPreservedOrConstPhysReg(unsigned PhysReg) const
Returns true if either isConstantPhysReg or TRI->isCallerPreservedPhysReg returns true...
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineInstrBuilder & UseMI
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
void setType(unsigned VReg, LLT Ty)
Set the low-level type of VReg to Ty.
MCRegAliasIterator enumerates all registers aliasing Reg.
use_instr_iterator use_instr_begin(unsigned RegNo) const
bool isValid() const
void substPhysReg(unsigned Reg, const TargetRegisterInfo &)
substPhysReg - Substitute the current register with the physical register Reg, taking any existing Su...
bool def_empty(unsigned RegNo) const
def_empty - Return true if there are no instructions defining the specified register (it may be live-...
void setCalleeSavedRegs(ArrayRef< MCPhysReg > CSRs)
Sets the updated Callee Saved Registers list.
unsigned getNumVirtRegs() const
getNumVirtRegs - Return the number of virtual registers created.
virtual bool isConstantPhysReg(unsigned PhysReg) const
Returns true if PhysReg is unallocatable and constant throughout the function.
iterator erase(const_iterator CI)
Definition: SmallVector.h:438
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
static const Function * getCalledFunction(const MachineInstr &MI)
bool isConstantPhysReg(unsigned PhysReg) const
Returns true if PhysReg is unallocatable and constant throughout the function.
unsigned first
unsigned createGenericVirtualRegister(LLT Ty, StringRef Name="")
Create and return a new generic virtual register with low-level type Ty.
iterator_range< T > make_range(T x, T y)
Convenience function for iterating over sub-ranges.
unsigned createIncompleteVirtualRegister(StringRef Name="")
Creates a new virtual register that has no register class, register bank or size assigned yet...
iterator_range< use_iterator > use_operands(unsigned Reg) const
bool isDebugValue() const
Definition: MachineInstr.h:996
MachineOperand class - Representation of each machine instruction operand.
bool atEnd() const
atEnd - return true if this iterator is equal to reg_end() on the value.
bool isReservedRegUnit(unsigned Unit) const
Returns true when the given register unit is considered reserved.
reg_iterator reg_begin(unsigned RegNo) const
This class implements the register bank concept.
Definition: RegisterBank.h:28
bool recomputeRegClass(unsigned Reg)
recomputeRegClass - Try to find a legal super-class of Reg&#39;s register class that still satisfies the ...
MachineInstr * getUniqueVRegDef(unsigned Reg) const
getUniqueVRegDef - Return the unique machine instr that defines the specified virtual register or nul...
const Function & getFunction() const
Return the LLVM function that this machine code represents.
bool isPhysRegUsed(unsigned PhysReg) const
Return true if the specified register is modified or read in this function.
virtual BitVector getReservedRegs(const MachineFunction &MF) const =0
Returns a bitset indexed by physical register number indicating if a register is a special register t...
bool isValid() const
isValid - returns true if this iterator is not yet at the end.
unsigned cloneVirtualRegister(unsigned VReg, StringRef Name="")
Create and return a new virtual register in the function with the same attributes as the given regist...
void verifyUseList(unsigned Reg) const
Verify the sanity of the use list for Reg.
void dumpUses(unsigned RegNo) const
def_instr_iterator def_instr_begin(unsigned RegNo) const
void replaceRegWith(unsigned FromReg, unsigned ToReg)
replaceRegWith - Replace all instances of FromReg with ToReg in the machine function.
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:253
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
bool isLiveIn(unsigned Reg) const
Representation of each machine instruction.
Definition: MachineInstr.h:63
std::vector< std::pair< unsigned, unsigned > >::const_iterator livein_iterator
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
pointer data()
Return a pointer to the vector&#39;s buffer, even if empty().
Definition: SmallVector.h:144
struct llvm::MachineOperand::@170::@172 Reg
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode...
Definition: MCInstrInfo.h:44
void setReg(unsigned Reg)
Change the register this operand corresponds to.
#define I(x, y, z)
Definition: MD5.cpp:58
virtual bool isCallerPreservedPhysReg(unsigned PhysReg, const MachineFunction &MF) const
Physical registers that may be modified within a function but are guaranteed to be restored before an...
LLVM_NODISCARD std::enable_if<!is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
Definition: Casting.h:322
void markUsesInDebugValueAsUndef(unsigned Reg) const
markUsesInDebugValueAsUndef - Mark every DBG_VALUE referencing the specified register as undefined wh...
size_type size() const
size - Returns the number of bits in this bitvector.
Definition: BitVector.h:169
bool isAllocatable() const
Return true if this register class may be used to create virtual registers.
bool hasOneNonDBGUse(unsigned RegNo) const
hasOneNonDBGUse - Return true if there is exactly one non-Debug instruction using the specified regis...
bool isReg() const
isReg - Tests if this is a MO_Register operand.
iterator_range< use_instr_iterator > use_instructions(unsigned Reg) const
void grow(IndexT n)
Definition: IndexedMap.h:67
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static def_iterator def_end()
MachineRegisterInfo(MachineFunction *MF)
static bool isNoReturnDef(const MachineOperand &MO)
void moveOperands(MachineOperand *Dst, MachineOperand *Src, unsigned NumOps)
Move NumOps operands from Src to Dst, updating use-def lists as needed.
static use_instr_iterator use_instr_end()
const MCPhysReg * getCalleeSavedRegs() const
Returns list of callee saved registers.
IRTranslator LLVM IR MI
void setRegClass(unsigned Reg, const TargetRegisterClass *RC)
setRegClass - Set the register class of the specified virtual register.
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:48
virtual void MRI_NoteNewVirtualRegister(unsigned Reg)=0
bool isValid() const
Check if the iterator is at the end of the list.
void setRegClassOrRegBank(unsigned Reg, const RegClassOrRegBank &RCOrRB)
static reg_iterator reg_end()
unsigned getLiveInVirtReg(unsigned PReg) const
getLiveInVirtReg - If PReg is a live-in physical register, return the corresponding live-in physical ...
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:413
reg_begin/reg_end - Provide iteration support to walk over all definitions and uses of a register wit...
unsigned createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
bool isReserved(unsigned PhysReg) const
isReserved - Returns true when PhysReg is a reserved register.
void addRegOperandToUseList(MachineOperand *MO)
Add MO to the linked list of operands for its register.