LLVM  6.0.0svn
MachineRegisterInfo.cpp
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1 //===- lib/Codegen/MachineRegisterInfo.cpp --------------------------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // Implementation of the MachineRegisterInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13 
25 #include "llvm/IR/Attributes.h"
26 #include "llvm/IR/DebugLoc.h"
27 #include "llvm/IR/Function.h"
28 #include "llvm/MC/MCRegisterInfo.h"
29 #include "llvm/Support/Casting.h"
31 #include "llvm/Support/Compiler.h"
34 #include <cassert>
35 
36 using namespace llvm;
37 
38 static cl::opt<bool> EnableSubRegLiveness("enable-subreg-liveness", cl::Hidden,
39  cl::init(true), cl::desc("Enable subregister liveness tracking."));
40 
41 // Pin the vtable to this file.
42 void MachineRegisterInfo::Delegate::anchor() {}
43 
45  : MF(MF), TracksSubRegLiveness(MF->getSubtarget().enableSubRegLiveness() &&
47  IsUpdatedCSRsInitialized(false) {
48  unsigned NumRegs = getTargetRegisterInfo()->getNumRegs();
49  VRegInfo.reserve(256);
50  RegAllocHints.reserve(256);
51  UsedPhysRegMask.resize(NumRegs);
52  PhysRegUseDefLists.reset(new MachineOperand*[NumRegs]());
53 }
54 
55 /// setRegClass - Set the register class of the specified virtual register.
56 ///
57 void
59  assert(RC && RC->isAllocatable() && "Invalid RC for virtual register");
60  VRegInfo[Reg].first = RC;
61 }
62 
64  const RegisterBank &RegBank) {
65  VRegInfo[Reg].first = &RegBank;
66 }
67 
68 const TargetRegisterClass *
70  const TargetRegisterClass *RC,
71  unsigned MinNumRegs) {
72  const TargetRegisterClass *OldRC = getRegClass(Reg);
73  if (OldRC == RC)
74  return RC;
75  const TargetRegisterClass *NewRC =
77  if (!NewRC || NewRC == OldRC)
78  return NewRC;
79  if (NewRC->getNumRegs() < MinNumRegs)
80  return nullptr;
81  setRegClass(Reg, NewRC);
82  return NewRC;
83 }
84 
85 bool
88  const TargetRegisterClass *OldRC = getRegClass(Reg);
89  const TargetRegisterClass *NewRC =
91 
92  // Stop early if there is no room to grow.
93  if (NewRC == OldRC)
94  return false;
95 
96  // Accumulate constraints from all uses.
97  for (MachineOperand &MO : reg_nodbg_operands(Reg)) {
98  // Apply the effect of the given operand to NewRC.
99  MachineInstr *MI = MO.getParent();
100  unsigned OpNo = &MO - &MI->getOperand(0);
101  NewRC = MI->getRegClassConstraintEffect(OpNo, NewRC, TII,
103  if (!NewRC || NewRC == OldRC)
104  return false;
105  }
106  setRegClass(Reg, NewRC);
107  return true;
108 }
109 
112  VRegInfo.grow(Reg);
113  RegAllocHints.grow(Reg);
114  return Reg;
115 }
116 
117 /// createVirtualRegister - Create and return a new virtual register in the
118 /// function with the specified register class.
119 ///
120 unsigned
122  assert(RegClass && "Cannot create register without RegClass!");
123  assert(RegClass->isAllocatable() &&
124  "Virtual register RegClass must be allocatable.");
125 
126  // New virtual register number.
128  VRegInfo[Reg].first = RegClass;
129  if (TheDelegate)
130  TheDelegate->MRI_NoteNewVirtualRegister(Reg);
131  return Reg;
132 }
133 
134 LLT MachineRegisterInfo::getType(unsigned VReg) const {
136  return TypeIt != getVRegToType().end() ? TypeIt->second : LLT{};
137 }
138 
139 void MachineRegisterInfo::setType(unsigned VReg, LLT Ty) {
140  // Check that VReg doesn't have a class.
142  !getRegClassOrRegBank(VReg).is<const TargetRegisterClass *>()) &&
143  "Can't set the size of a non-generic virtual register");
144  getVRegToType()[VReg] = Ty;
145 }
146 
147 unsigned
149  // New virtual register number.
151  // FIXME: Should we use a dummy register class?
152  VRegInfo[Reg].first = static_cast<RegisterBank *>(nullptr);
153  getVRegToType()[Reg] = Ty;
154  if (TheDelegate)
155  TheDelegate->MRI_NoteNewVirtualRegister(Reg);
156  return Reg;
157 }
158 
160  getVRegToType().clear();
161 }
162 
163 /// clearVirtRegs - Remove all virtual registers (after physreg assignment).
165 #ifndef NDEBUG
166  for (unsigned i = 0, e = getNumVirtRegs(); i != e; ++i) {
168  if (!VRegInfo[Reg].second)
169  continue;
170  verifyUseList(Reg);
171  llvm_unreachable("Remaining virtual register operands");
172  }
173 #endif
174  VRegInfo.clear();
175  for (auto &I : LiveIns)
176  I.second = 0;
177 }
178 
180 #ifndef NDEBUG
181  bool Valid = true;
182  for (MachineOperand &M : reg_operands(Reg)) {
183  MachineOperand *MO = &M;
184  MachineInstr *MI = MO->getParent();
185  if (!MI) {
186  errs() << PrintReg(Reg, getTargetRegisterInfo())
187  << " use list MachineOperand " << MO
188  << " has no parent instruction.\n";
189  Valid = false;
190  continue;
191  }
192  MachineOperand *MO0 = &MI->getOperand(0);
193  unsigned NumOps = MI->getNumOperands();
194  if (!(MO >= MO0 && MO < MO0+NumOps)) {
195  errs() << PrintReg(Reg, getTargetRegisterInfo())
196  << " use list MachineOperand " << MO
197  << " doesn't belong to parent MI: " << *MI;
198  Valid = false;
199  }
200  if (!MO->isReg()) {
201  errs() << PrintReg(Reg, getTargetRegisterInfo())
202  << " MachineOperand " << MO << ": " << *MO
203  << " is not a register\n";
204  Valid = false;
205  }
206  if (MO->getReg() != Reg) {
207  errs() << PrintReg(Reg, getTargetRegisterInfo())
208  << " use-list MachineOperand " << MO << ": "
209  << *MO << " is the wrong register\n";
210  Valid = false;
211  }
212  }
213  assert(Valid && "Invalid use list");
214 #endif
215 }
216 
218 #ifndef NDEBUG
219  for (unsigned i = 0, e = getNumVirtRegs(); i != e; ++i)
221  for (unsigned i = 1, e = getTargetRegisterInfo()->getNumRegs(); i != e; ++i)
222  verifyUseList(i);
223 #endif
224 }
225 
226 /// Add MO to the linked list of operands for its register.
228  assert(!MO->isOnRegUseList() && "Already on list");
229  MachineOperand *&HeadRef = getRegUseDefListHead(MO->getReg());
230  MachineOperand *const Head = HeadRef;
231 
232  // Head points to the first list element.
233  // Next is NULL on the last list element.
234  // Prev pointers are circular, so Head->Prev == Last.
235 
236  // Head is NULL for an empty list.
237  if (!Head) {
238  MO->Contents.Reg.Prev = MO;
239  MO->Contents.Reg.Next = nullptr;
240  HeadRef = MO;
241  return;
242  }
243  assert(MO->getReg() == Head->getReg() && "Different regs on the same list!");
244 
245  // Insert MO between Last and Head in the circular Prev chain.
246  MachineOperand *Last = Head->Contents.Reg.Prev;
247  assert(Last && "Inconsistent use list");
248  assert(MO->getReg() == Last->getReg() && "Different regs on the same list!");
249  Head->Contents.Reg.Prev = MO;
250  MO->Contents.Reg.Prev = Last;
251 
252  // Def operands always precede uses. This allows def_iterator to stop early.
253  // Insert def operands at the front, and use operands at the back.
254  if (MO->isDef()) {
255  // Insert def at the front.
256  MO->Contents.Reg.Next = Head;
257  HeadRef = MO;
258  } else {
259  // Insert use at the end.
260  MO->Contents.Reg.Next = nullptr;
261  Last->Contents.Reg.Next = MO;
262  }
263 }
264 
265 /// Remove MO from its use-def list.
267  assert(MO->isOnRegUseList() && "Operand not on use list");
268  MachineOperand *&HeadRef = getRegUseDefListHead(MO->getReg());
269  MachineOperand *const Head = HeadRef;
270  assert(Head && "List already empty");
271 
272  // Unlink this from the doubly linked list of operands.
273  MachineOperand *Next = MO->Contents.Reg.Next;
274  MachineOperand *Prev = MO->Contents.Reg.Prev;
275 
276  // Prev links are circular, next link is NULL instead of looping back to Head.
277  if (MO == Head)
278  HeadRef = Next;
279  else
280  Prev->Contents.Reg.Next = Next;
281 
282  (Next ? Next : Head)->Contents.Reg.Prev = Prev;
283 
284  MO->Contents.Reg.Prev = nullptr;
285  MO->Contents.Reg.Next = nullptr;
286 }
287 
288 /// Move NumOps operands from Src to Dst, updating use-def lists as needed.
289 ///
290 /// The Dst range is assumed to be uninitialized memory. (Or it may contain
291 /// operands that won't be destroyed, which is OK because the MO destructor is
292 /// trivial anyway).
293 ///
294 /// The Src and Dst ranges may overlap.
296  MachineOperand *Src,
297  unsigned NumOps) {
298  assert(Src != Dst && NumOps && "Noop moveOperands");
299 
300  // Copy backwards if Dst is within the Src range.
301  int Stride = 1;
302  if (Dst >= Src && Dst < Src + NumOps) {
303  Stride = -1;
304  Dst += NumOps - 1;
305  Src += NumOps - 1;
306  }
307 
308  // Copy one operand at a time.
309  do {
310  new (Dst) MachineOperand(*Src);
311 
312  // Dst takes Src's place in the use-def chain.
313  if (Src->isReg()) {
314  MachineOperand *&Head = getRegUseDefListHead(Src->getReg());
315  MachineOperand *Prev = Src->Contents.Reg.Prev;
316  MachineOperand *Next = Src->Contents.Reg.Next;
317  assert(Head && "List empty, but operand is chained");
318  assert(Prev && "Operand was not on use-def list");
319 
320  // Prev links are circular, next link is NULL instead of looping back to
321  // Head.
322  if (Src == Head)
323  Head = Dst;
324  else
325  Prev->Contents.Reg.Next = Dst;
326 
327  // Update Prev pointer. This also works when Src was pointing to itself
328  // in a 1-element list. In that case Head == Dst.
329  (Next ? Next : Head)->Contents.Reg.Prev = Dst;
330  }
331 
332  Dst += Stride;
333  Src += Stride;
334  } while (--NumOps);
335 }
336 
337 /// replaceRegWith - Replace all instances of FromReg with ToReg in the
338 /// machine function. This is like llvm-level X->replaceAllUsesWith(Y),
339 /// except that it also changes any definitions of the register as well.
340 /// If ToReg is a physical register we apply the sub register to obtain the
341 /// final/proper physical register.
342 void MachineRegisterInfo::replaceRegWith(unsigned FromReg, unsigned ToReg) {
343  assert(FromReg != ToReg && "Cannot replace a reg with itself");
344 
346 
347  // TODO: This could be more efficient by bulk changing the operands.
348  for (reg_iterator I = reg_begin(FromReg), E = reg_end(); I != E; ) {
349  MachineOperand &O = *I;
350  ++I;
352  O.substPhysReg(ToReg, *TRI);
353  } else {
354  O.setReg(ToReg);
355  }
356  }
357 }
358 
359 /// getVRegDef - Return the machine instr that defines the specified virtual
360 /// register or null if none is found. This assumes that the code is in SSA
361 /// form, so there should only be one definition.
363  // Since we are in SSA form, we can use the first definition.
365  assert((I.atEnd() || std::next(I) == def_instr_end()) &&
366  "getVRegDef assumes a single definition or no definition");
367  return !I.atEnd() ? &*I : nullptr;
368 }
369 
370 /// getUniqueVRegDef - Return the unique machine instr that defines the
371 /// specified virtual register or null if none is found. If there are
372 /// multiple definitions or no definition, return null.
374  if (def_empty(Reg)) return nullptr;
376  if (std::next(I) != def_instr_end())
377  return nullptr;
378  return &*I;
379 }
380 
381 bool MachineRegisterInfo::hasOneNonDBGUse(unsigned RegNo) const {
383  if (UI == use_nodbg_end())
384  return false;
385  return ++UI == use_nodbg_end();
386 }
387 
388 /// clearKillFlags - Iterate over all the uses of the given register and
389 /// clear the kill flag from the MachineOperand. This function is used by
390 /// optimization passes which extend register lifetimes and need only
391 /// preserve conservative kill flag information.
393  for (MachineOperand &MO : use_operands(Reg))
394  MO.setIsKill(false);
395 }
396 
397 bool MachineRegisterInfo::isLiveIn(unsigned Reg) const {
398  for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I)
399  if (I->first == Reg || I->second == Reg)
400  return true;
401  return false;
402 }
403 
404 /// getLiveInPhysReg - If VReg is a live-in virtual register, return the
405 /// corresponding live-in physical register.
406 unsigned MachineRegisterInfo::getLiveInPhysReg(unsigned VReg) const {
407  for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I)
408  if (I->second == VReg)
409  return I->first;
410  return 0;
411 }
412 
413 /// getLiveInVirtReg - If PReg is a live-in physical register, return the
414 /// corresponding live-in physical register.
415 unsigned MachineRegisterInfo::getLiveInVirtReg(unsigned PReg) const {
416  for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I)
417  if (I->first == PReg)
418  return I->second;
419  return 0;
420 }
421 
422 /// EmitLiveInCopies - Emit copies to initialize livein virtual registers
423 /// into the given entry block.
424 void
426  const TargetRegisterInfo &TRI,
427  const TargetInstrInfo &TII) {
428  // Emit the copies into the top of the block.
429  for (unsigned i = 0, e = LiveIns.size(); i != e; ++i)
430  if (LiveIns[i].second) {
431  if (use_nodbg_empty(LiveIns[i].second)) {
432  // The livein has no non-dbg uses. Drop it.
433  //
434  // It would be preferable to have isel avoid creating live-in
435  // records for unused arguments in the first place, but it's
436  // complicated by the debug info code for arguments.
437  LiveIns.erase(LiveIns.begin() + i);
438  --i; --e;
439  } else {
440  // Emit a copy.
441  BuildMI(*EntryMBB, EntryMBB->begin(), DebugLoc(),
442  TII.get(TargetOpcode::COPY), LiveIns[i].second)
443  .addReg(LiveIns[i].first);
444 
445  // Add the register to the entry block live-in set.
446  EntryMBB->addLiveIn(LiveIns[i].first);
447  }
448  } else {
449  // Add the register to the entry block live-in set.
450  EntryMBB->addLiveIn(LiveIns[i].first);
451  }
452 }
453 
455  // Lane masks are only defined for vregs.
457  const TargetRegisterClass &TRC = *getRegClass(Reg);
458  return TRC.getLaneMask();
459 }
460 
461 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
463  for (MachineInstr &I : use_instructions(Reg))
464  I.dump();
465 }
466 #endif
467 
469  ReservedRegs = getTargetRegisterInfo()->getReservedRegs(MF);
470  assert(ReservedRegs.size() == getTargetRegisterInfo()->getNumRegs() &&
471  "Invalid ReservedRegs vector from target");
472 }
473 
474 bool MachineRegisterInfo::isConstantPhysReg(unsigned PhysReg) const {
476 
478  if (TRI->isConstantPhysReg(PhysReg))
479  return true;
480 
481  // Check if any overlapping register is modified, or allocatable so it may be
482  // used later.
483  for (MCRegAliasIterator AI(PhysReg, TRI, true);
484  AI.isValid(); ++AI)
485  if (!def_empty(*AI) || isAllocatable(*AI))
486  return false;
487  return true;
488 }
489 
490 /// markUsesInDebugValueAsUndef - Mark every DBG_VALUE referencing the
491 /// specified register as undefined which causes the DBG_VALUE to be
492 /// deleted during LiveDebugVariables analysis.
494  // Mark any DBG_VALUE that uses Reg as undef (but don't delete it.)
497  I != E; I = nextI) {
498  nextI = std::next(I); // I is invalidated by the setReg
499  MachineInstr *UseMI = &*I;
500  if (UseMI->isDebugValue())
501  UseMI->getOperand(0).setReg(0U);
502  }
503 }
504 
505 static const Function *getCalledFunction(const MachineInstr &MI) {
506  for (const MachineOperand &MO : MI.operands()) {
507  if (!MO.isGlobal())
508  continue;
509  const Function *Func = dyn_cast<Function>(MO.getGlobal());
510  if (Func != nullptr)
511  return Func;
512  }
513  return nullptr;
514 }
515 
516 static bool isNoReturnDef(const MachineOperand &MO) {
517  // Anything which is not a noreturn function is a real def.
518  const MachineInstr &MI = *MO.getParent();
519  if (!MI.isCall())
520  return false;
521  const MachineBasicBlock &MBB = *MI.getParent();
522  if (!MBB.succ_empty())
523  return false;
524  const MachineFunction &MF = *MBB.getParent();
525  // We need to keep correct unwind information even if the function will
526  // not return, since the runtime may need it.
527  if (MF.getFunction()->hasFnAttribute(Attribute::UWTable))
528  return false;
529  const Function *Called = getCalledFunction(MI);
530  return !(Called == nullptr || !Called->hasFnAttribute(Attribute::NoReturn) ||
531  !Called->hasFnAttribute(Attribute::NoUnwind));
532 }
533 
535  bool SkipNoReturnDef) const {
536  if (UsedPhysRegMask.test(PhysReg))
537  return true;
539  for (MCRegAliasIterator AI(PhysReg, TRI, true); AI.isValid(); ++AI) {
540  for (const MachineOperand &MO : make_range(def_begin(*AI), def_end())) {
541  if (!SkipNoReturnDef && isNoReturnDef(MO))
542  continue;
543  return true;
544  }
545  }
546  return false;
547 }
548 
549 bool MachineRegisterInfo::isPhysRegUsed(unsigned PhysReg) const {
550  if (UsedPhysRegMask.test(PhysReg))
551  return true;
553  for (MCRegAliasIterator AliasReg(PhysReg, TRI, true); AliasReg.isValid();
554  ++AliasReg) {
555  if (!reg_nodbg_empty(*AliasReg))
556  return true;
557  }
558  return false;
559 }
560 
562 
564  assert(Reg && (Reg < TRI->getNumRegs()) &&
565  "Trying to disable an invalid register");
566 
567  if (!IsUpdatedCSRsInitialized) {
568  const MCPhysReg *CSR = TRI->getCalleeSavedRegs(MF);
569  for (const MCPhysReg *I = CSR; *I; ++I)
570  UpdatedCSRs.push_back(*I);
571 
572  // Zero value represents the end of the register list
573  // (no more registers should be pushed).
574  UpdatedCSRs.push_back(0);
575 
576  IsUpdatedCSRsInitialized = true;
577  }
578 
579  // Remove the register (and its aliases from the list).
580  for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI)
581  UpdatedCSRs.erase(std::remove(UpdatedCSRs.begin(), UpdatedCSRs.end(), *AI),
582  UpdatedCSRs.end());
583 }
584 
586  if (IsUpdatedCSRsInitialized)
587  return UpdatedCSRs.data();
588 
590 }
591 
593  if (IsUpdatedCSRsInitialized)
594  UpdatedCSRs.clear();
595 
596  for (MCPhysReg Reg : CSRs)
597  UpdatedCSRs.push_back(Reg);
598 
599  // Zero value represents the end of the register list
600  // (no more registers should be pushed).
601  UpdatedCSRs.push_back(0);
602  IsUpdatedCSRsInitialized = true;
603 }
604 
605 bool MachineRegisterInfo::isReservedRegUnit(unsigned Unit) const {
607  for (MCRegUnitRootIterator Root(Unit, TRI); Root.isValid(); ++Root) {
608  bool IsRootReserved = true;
609  for (MCSuperRegIterator Super(*Root, TRI, /*IncludeSelf=*/true);
610  Super.isValid(); ++Super) {
611  unsigned Reg = *Super;
612  if (!isReserved(Reg)) {
613  IsRootReserved = false;
614  break;
615  }
616  }
617  if (IsRootReserved)
618  return true;
619  }
620  return false;
621 }
bool reg_nodbg_empty(unsigned RegNo) const
reg_nodbg_empty - Return true if the only instructions using or defining Reg are Debug instructions...
void resize(unsigned N, bool t=false)
resize - Grow or shrink the bitvector.
Definition: BitVector.h:372
const TargetRegisterClass * getCommonSubClass(const TargetRegisterClass *A, const TargetRegisterClass *B, const MVT::SimpleValueType SVT=MVT::SimpleValueType::Any) const
Find the largest common subclass of A and B.
void push_back(const T &Elt)
Definition: SmallVector.h:212
void EmitLiveInCopies(MachineBasicBlock *EntryMBB, const TargetRegisterInfo &TRI, const TargetInstrInfo &TII)
EmitLiveInCopies - Emit copies to initialize livein virtual registers into the given entry block...
raw_ostream & errs()
This returns a reference to a raw_ostream for standard error.
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
bool use_nodbg_empty(unsigned RegNo) const
use_nodbg_empty - Return true if there are no non-Debug instructions using the specified register...
bool isCall(QueryType Type=AnyInBundle) const
Definition: MachineInstr.h:458
const TargetRegisterClass * getRegClass(unsigned Reg) const
Return the register class of the specified virtual register.
livein_iterator livein_begin() const
void removeRegOperandFromUseList(MachineOperand *MO)
Remove MO from its use-def list.
bool isAllocatable(unsigned PhysReg) const
isAllocatable - Returns true when PhysReg belongs to an allocatable register class and it hasn&#39;t been...
void clearVirtRegTypes()
Remove all types associated to virtual registers (after instruction selection and constraining of all...
LaneBitmask getMaxLaneMaskForVReg(unsigned Reg) const
Returns a mask covering all bits that can appear in lane masks of subregisters of the virtual registe...
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
#define LLVM_DUMP_METHOD
Mark debug helper function definitions like dump() that should not be stripped from debug builds...
Definition: Compiler.h:449
unsigned getNumRegs() const
Return the number of registers in this class.
static unsigned index2VirtReg(unsigned Index)
Convert a 0-based index to a virtual register number.
unsigned createVirtualRegister(const TargetRegisterClass *RegClass)
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
std::error_code remove(const Twine &path, bool IgnoreNonExisting=true)
Remove path.
bool isPhysRegModified(unsigned PhysReg, bool SkipNoReturnDef=false) const
Return true if the specified register is modified in this function.
This provides a very simple, boring adaptor for a begin and end iterator into a range type...
unsigned getReg() const
getReg - Returns the register number.
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
iterator_range< reg_nodbg_iterator > reg_nodbg_operands(unsigned Reg) const
bool test(unsigned Idx) const
Definition: BitVector.h:502
iterator_range< reg_iterator > reg_operands(unsigned Reg) const
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
Definition: Function.h:262
unsigned second
A debug info location.
Definition: DebugLoc.h:34
void setRegBank(unsigned Reg, const RegisterBank &RegBank)
Set the register bank to RegBank for Reg.
unsigned createGenericVirtualRegister(LLT Ty)
Create and return a new generic virtual register with low-level type Ty.
iterator_range< mop_iterator > operands()
Definition: MachineInstr.h:332
use_nodbg_iterator use_nodbg_begin(unsigned RegNo) const
void verifyUseLists() const
Verify the use list of all registers.
static use_nodbg_iterator use_nodbg_end()
void clearVirtRegs()
clearVirtRegs - Remove all virtual registers (after physreg assignment).
MCSuperRegIterator enumerates all super-registers of Reg.
const HexagonInstrInfo * TII
unsigned getNumOperands() const
Access to explicit operands of the instruction.
Definition: MachineInstr.h:293
struct llvm::MachineOperand::@143::@145 Reg
void freezeReservedRegs(const MachineFunction &)
freezeReservedRegs - Called by the register allocator to freeze the set of reserved registers before ...
Reg
All possible values of the reg field in the ModR/M byte.
This file contains the simple types necessary to represent the attributes associated with functions a...
def_iterator def_begin(unsigned RegNo) const
const TargetRegisterClass * getRegClassConstraintEffect(unsigned OpIdx, const TargetRegisterClass *CurRC, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const
Applies the constraints (def/use) implied by the OpIdx operand to the given CurRC.
unsigned getLiveInPhysReg(unsigned VReg) const
getLiveInPhysReg - If VReg is a live-in virtual register, return the corresponding live-in physical r...
MachineInstr * getVRegDef(unsigned Reg) const
getVRegDef - Return the machine instr that defines the specified virtual register or null if none is ...
defusechain_iterator - This class provides iterator support for machine operands in the function that...
static cl::opt< bool > EnableSubRegLiveness("enable-subreg-liveness", cl::Hidden, cl::init(true), cl::desc("Enable subregister liveness tracking."))
void clearKillFlags(unsigned Reg) const
clearKillFlags - Iterate over all the uses of the given register and clear the kill flag from the Mac...
const RegClassOrRegBank & getRegClassOrRegBank(unsigned Reg) const
Return the register bank or register class of Reg.
MCRegUnitRootIterator enumerates the root registers of a register unit.
livein_iterator livein_end() const
static def_instr_iterator def_instr_end()
virtual const TargetRegisterClass * getLargestLegalSuperClass(const TargetRegisterClass *RC, const MachineFunction &) const
Returns the largest super class of RC that is legal to use in the current sub-target and has the same...
virtual const TargetInstrInfo * getInstrInfo() const
LaneBitmask getLaneMask() const
Returns the combination of all lane masks of register in this class.
Printable PrintReg(unsigned Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubRegIdx=0)
Prints virtual and physical registers with or without a TRI instance.
virtual const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const =0
Return a null-terminated list of all of the callee-saved registers on this target.
void disableCalleeSavedRegister(unsigned Reg)
Disables the register from the list of CSRs.
const TargetRegisterClass * constrainRegClass(unsigned Reg, const TargetRegisterClass *RC, unsigned MinNumRegs=0)
constrainRegClass - Constrain the register class of the specified virtual register to be a common sub...
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
TargetInstrInfo - Interface to description of machine instruction set.
iterator find(const_arg_type_t< KeyT > Val)
Definition: DenseMap.h:146
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
unsigned getNumRegs() const
Return the number of registers this target has (useful for sizing arrays holding per register informa...
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:406
void addLiveIn(MCPhysReg PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())
Adds the specified register as a live in.
const TargetRegisterInfo * getTargetRegisterInfo() const
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineInstrBuilder & UseMI
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
LLVM_ATTRIBUTE_ALWAYS_INLINE iterator begin()
Definition: SmallVector.h:116
void setType(unsigned VReg, LLT Ty)
Set the low-level type of VReg to Ty.
MCRegAliasIterator enumerates all registers aliasing Reg.
unsigned createIncompleteVirtualRegister()
Creates a new virtual register that has no register class, register bank or size assigned yet...
use_instr_iterator use_instr_begin(unsigned RegNo) const
VRegToTypeMap & getVRegToType() const
Accessor for VRegToType.
void substPhysReg(unsigned Reg, const TargetRegisterInfo &)
substPhysReg - Substitute the current register with the physical register Reg, taking any existing Su...
bool def_empty(unsigned RegNo) const
def_empty - Return true if there are no instructions defining the specified register (it may be live-...
void setCalleeSavedRegs(ArrayRef< MCPhysReg > CSRs)
Sets the updated Callee Saved Registers list.
unsigned getNumVirtRegs() const
getNumVirtRegs - Return the number of virtual registers created.
virtual bool isConstantPhysReg(unsigned PhysReg) const
Returns true if PhysReg is unallocatable and constant throughout the function.
iterator erase(const_iterator CI)
Definition: SmallVector.h:449
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
static const Function * getCalledFunction(const MachineInstr &MI)
bool isConstantPhysReg(unsigned PhysReg) const
Returns true if PhysReg is unallocatable and constant throughout the function.
unsigned first
iterator_range< T > make_range(T x, T y)
Convenience function for iterating over sub-ranges.
iterator_range< use_iterator > use_operands(unsigned Reg) const
bool isDebugValue() const
Definition: MachineInstr.h:816
MachineOperand class - Representation of each machine instruction operand.
bool atEnd() const
atEnd - return true if this iterator is equal to reg_end() on the value.
bool isReservedRegUnit(unsigned Unit) const
Returns true when the given register unit is considered reserved.
reg_iterator reg_begin(unsigned RegNo) const
This class implements the register bank concept.
Definition: RegisterBank.h:29
bool recomputeRegClass(unsigned Reg)
recomputeRegClass - Try to find a legal super-class of Reg&#39;s register class that still satisfies the ...
MachineInstr * getUniqueVRegDef(unsigned Reg) const
getUniqueVRegDef - Return the unique machine instr that defines the specified virtual register or nul...
bool isPhysRegUsed(unsigned PhysReg) const
Return true if the specified register is modified or read in this function.
virtual BitVector getReservedRegs(const MachineFunction &MF) const =0
Returns a bitset indexed by physical register number indicating if a register is a special register t...
bool isValid() const
isValid - returns true if this iterator is not yet at the end.
void verifyUseList(unsigned Reg) const
Verify the sanity of the use list for Reg.
void dumpUses(unsigned RegNo) const
def_instr_iterator def_instr_begin(unsigned RegNo) const
void replaceRegWith(unsigned FromReg, unsigned ToReg)
replaceRegWith - Replace all instances of FromReg with ToReg in the machine function.
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:139
bool isLiveIn(unsigned Reg) const
Representation of each machine instruction.
Definition: MachineInstr.h:59
std::vector< std::pair< unsigned, unsigned > >::const_iterator livein_iterator
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
LLVM_ATTRIBUTE_ALWAYS_INLINE iterator end()
Definition: SmallVector.h:120
pointer data()
Return a pointer to the vector&#39;s buffer, even if empty().
Definition: SmallVector.h:143
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode...
Definition: MCInstrInfo.h:45
void setReg(unsigned Reg)
Change the register this operand corresponds to.
#define I(x, y, z)
Definition: MD5.cpp:58
iterator end()
Definition: DenseMap.h:79
LLT getType(unsigned VReg) const
Get the low-level type of VReg or LLT{} if VReg is not a generic (target independent) virtual registe...
LLVM_NODISCARD std::enable_if<!is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
Definition: Casting.h:323
void markUsesInDebugValueAsUndef(unsigned Reg) const
markUsesInDebugValueAsUndef - Mark every DBG_VALUE referencing the specified register as undefined wh...
size_type size() const
size - Returns the number of bits in this bitvector.
Definition: BitVector.h:170
bool isAllocatable() const
Return true if this register class may be used to create virtual registers.
bool hasOneNonDBGUse(unsigned RegNo) const
hasOneNonDBGUse - Return true if there is exactly one non-Debug instruction using the specified regis...
bool isReg() const
isReg - Tests if this is a MO_Register operand.
iterator_range< use_instr_iterator > use_instructions(unsigned Reg) const
const Function * getFunction() const
getFunction - Return the LLVM function that this machine code represents
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static def_iterator def_end()
bool isNull(StringRef S)
Definition: YAMLTraits.h:488
MachineRegisterInfo(MachineFunction *MF)
static bool isNoReturnDef(const MachineOperand &MO)
void moveOperands(MachineOperand *Dst, MachineOperand *Src, unsigned NumOps)
Move NumOps operands from Src to Dst, updating use-def lists as needed.
static use_instr_iterator use_instr_end()
const MCPhysReg * getCalleeSavedRegs() const
Returns list of callee saved registers.
IRTranslator LLVM IR MI
void setRegClass(unsigned Reg, const TargetRegisterClass *RC)
setRegClass - Set the register class of the specified virtual register.
virtual void MRI_NoteNewVirtualRegister(unsigned Reg)=0
bool isValid() const
Check if the iterator is at the end of the list.
static reg_iterator reg_end()
unsigned getLiveInVirtReg(unsigned PReg) const
getLiveInVirtReg - If PReg is a live-in physical register, return the corresponding live-in physical ...
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:295
reg_begin/reg_end - Provide iteration support to walk over all definitions and uses of a register wit...
bool isReserved(unsigned PhysReg) const
isReserved - Returns true when PhysReg is a reserved register.
void addRegOperandToUseList(MachineOperand *MO)
Add MO to the linked list of operands for its register.