LLVM  8.0.0svn
MachineRegisterInfo.cpp
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1 //===- lib/Codegen/MachineRegisterInfo.cpp --------------------------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // Implementation of the MachineRegisterInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13 
25 #include "llvm/Config/llvm-config.h"
26 #include "llvm/IR/Attributes.h"
27 #include "llvm/IR/DebugLoc.h"
28 #include "llvm/IR/Function.h"
29 #include "llvm/MC/MCRegisterInfo.h"
30 #include "llvm/Support/Casting.h"
32 #include "llvm/Support/Compiler.h"
35 #include <cassert>
36 
37 using namespace llvm;
38 
39 static cl::opt<bool> EnableSubRegLiveness("enable-subreg-liveness", cl::Hidden,
40  cl::init(true), cl::desc("Enable subregister liveness tracking."));
41 
42 // Pin the vtable to this file.
43 void MachineRegisterInfo::Delegate::anchor() {}
44 
46  : MF(MF), TracksSubRegLiveness(MF->getSubtarget().enableSubRegLiveness() &&
48  IsUpdatedCSRsInitialized(false) {
49  unsigned NumRegs = getTargetRegisterInfo()->getNumRegs();
50  VRegInfo.reserve(256);
51  RegAllocHints.reserve(256);
52  UsedPhysRegMask.resize(NumRegs);
53  PhysRegUseDefLists.reset(new MachineOperand*[NumRegs]());
54 }
55 
56 /// setRegClass - Set the register class of the specified virtual register.
57 ///
58 void
60  assert(RC && RC->isAllocatable() && "Invalid RC for virtual register");
61  VRegInfo[Reg].first = RC;
62 }
63 
65  const RegisterBank &RegBank) {
66  VRegInfo[Reg].first = &RegBank;
67 }
68 
69 static const TargetRegisterClass *
71  const TargetRegisterClass *OldRC,
72  const TargetRegisterClass *RC, unsigned MinNumRegs) {
73  if (OldRC == RC)
74  return RC;
75  const TargetRegisterClass *NewRC =
76  MRI.getTargetRegisterInfo()->getCommonSubClass(OldRC, RC);
77  if (!NewRC || NewRC == OldRC)
78  return NewRC;
79  if (NewRC->getNumRegs() < MinNumRegs)
80  return nullptr;
81  MRI.setRegClass(Reg, NewRC);
82  return NewRC;
83 }
84 
85 const TargetRegisterClass *
87  const TargetRegisterClass *RC,
88  unsigned MinNumRegs) {
89  return ::constrainRegClass(*this, Reg, getRegClass(Reg), RC, MinNumRegs);
90 }
91 
92 bool
94  unsigned ConstrainingReg,
95  unsigned MinNumRegs) {
96  const LLT RegTy = getType(Reg);
97  const LLT ConstrainingRegTy = getType(ConstrainingReg);
98  if (RegTy.isValid() && ConstrainingRegTy.isValid() &&
99  RegTy != ConstrainingRegTy)
100  return false;
101  const auto ConstrainingRegCB = getRegClassOrRegBank(ConstrainingReg);
102  if (!ConstrainingRegCB.isNull()) {
103  const auto RegCB = getRegClassOrRegBank(Reg);
104  if (RegCB.isNull())
105  setRegClassOrRegBank(Reg, ConstrainingRegCB);
106  else if (RegCB.is<const TargetRegisterClass *>() !=
107  ConstrainingRegCB.is<const TargetRegisterClass *>())
108  return false;
109  else if (RegCB.is<const TargetRegisterClass *>()) {
110  if (!::constrainRegClass(
111  *this, Reg, RegCB.get<const TargetRegisterClass *>(),
112  ConstrainingRegCB.get<const TargetRegisterClass *>(), MinNumRegs))
113  return false;
114  } else if (RegCB != ConstrainingRegCB)
115  return false;
116  }
117  if (ConstrainingRegTy.isValid())
118  setType(Reg, ConstrainingRegTy);
119  return true;
120 }
121 
122 bool
124  const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
125  const TargetRegisterClass *OldRC = getRegClass(Reg);
126  const TargetRegisterClass *NewRC =
128 
129  // Stop early if there is no room to grow.
130  if (NewRC == OldRC)
131  return false;
132 
133  // Accumulate constraints from all uses.
134  for (MachineOperand &MO : reg_nodbg_operands(Reg)) {
135  // Apply the effect of the given operand to NewRC.
136  MachineInstr *MI = MO.getParent();
137  unsigned OpNo = &MO - &MI->getOperand(0);
138  NewRC = MI->getRegClassConstraintEffect(OpNo, NewRC, TII,
140  if (!NewRC || NewRC == OldRC)
141  return false;
142  }
143  setRegClass(Reg, NewRC);
144  return true;
145 }
146 
149  VRegInfo.grow(Reg);
150  RegAllocHints.grow(Reg);
151  insertVRegByName(Name, Reg);
152  return Reg;
153 }
154 
155 /// createVirtualRegister - Create and return a new virtual register in the
156 /// function with the specified register class.
157 ///
158 unsigned
160  StringRef Name) {
161  assert(RegClass && "Cannot create register without RegClass!");
162  assert(RegClass->isAllocatable() &&
163  "Virtual register RegClass must be allocatable.");
164 
165  // New virtual register number.
166  unsigned Reg = createIncompleteVirtualRegister(Name);
167  VRegInfo[Reg].first = RegClass;
168  if (TheDelegate)
169  TheDelegate->MRI_NoteNewVirtualRegister(Reg);
170  return Reg;
171 }
172 
174  StringRef Name) {
175  unsigned Reg = createIncompleteVirtualRegister(Name);
176  VRegInfo[Reg].first = VRegInfo[VReg].first;
177  setType(Reg, getType(VReg));
178  if (TheDelegate)
179  TheDelegate->MRI_NoteNewVirtualRegister(Reg);
180  return Reg;
181 }
182 
183 void MachineRegisterInfo::setType(unsigned VReg, LLT Ty) {
184  VRegToType.grow(VReg);
185  VRegToType[VReg] = Ty;
186 }
187 
188 unsigned
190  // New virtual register number.
191  unsigned Reg = createIncompleteVirtualRegister(Name);
192  // FIXME: Should we use a dummy register class?
193  VRegInfo[Reg].first = static_cast<RegisterBank *>(nullptr);
194  setType(Reg, Ty);
195  if (TheDelegate)
196  TheDelegate->MRI_NoteNewVirtualRegister(Reg);
197  return Reg;
198 }
199 
201 
202 /// clearVirtRegs - Remove all virtual registers (after physreg assignment).
204 #ifndef NDEBUG
205  for (unsigned i = 0, e = getNumVirtRegs(); i != e; ++i) {
207  if (!VRegInfo[Reg].second)
208  continue;
209  verifyUseList(Reg);
210  llvm_unreachable("Remaining virtual register operands");
211  }
212 #endif
213  VRegInfo.clear();
214  for (auto &I : LiveIns)
215  I.second = 0;
216 }
217 
219 #ifndef NDEBUG
220  bool Valid = true;
221  for (MachineOperand &M : reg_operands(Reg)) {
222  MachineOperand *MO = &M;
223  MachineInstr *MI = MO->getParent();
224  if (!MI) {
225  errs() << printReg(Reg, getTargetRegisterInfo())
226  << " use list MachineOperand " << MO
227  << " has no parent instruction.\n";
228  Valid = false;
229  continue;
230  }
231  MachineOperand *MO0 = &MI->getOperand(0);
232  unsigned NumOps = MI->getNumOperands();
233  if (!(MO >= MO0 && MO < MO0+NumOps)) {
234  errs() << printReg(Reg, getTargetRegisterInfo())
235  << " use list MachineOperand " << MO
236  << " doesn't belong to parent MI: " << *MI;
237  Valid = false;
238  }
239  if (!MO->isReg()) {
240  errs() << printReg(Reg, getTargetRegisterInfo())
241  << " MachineOperand " << MO << ": " << *MO
242  << " is not a register\n";
243  Valid = false;
244  }
245  if (MO->getReg() != Reg) {
246  errs() << printReg(Reg, getTargetRegisterInfo())
247  << " use-list MachineOperand " << MO << ": "
248  << *MO << " is the wrong register\n";
249  Valid = false;
250  }
251  }
252  assert(Valid && "Invalid use list");
253 #endif
254 }
255 
257 #ifndef NDEBUG
258  for (unsigned i = 0, e = getNumVirtRegs(); i != e; ++i)
260  for (unsigned i = 1, e = getTargetRegisterInfo()->getNumRegs(); i != e; ++i)
261  verifyUseList(i);
262 #endif
263 }
264 
265 /// Add MO to the linked list of operands for its register.
267  assert(!MO->isOnRegUseList() && "Already on list");
268  MachineOperand *&HeadRef = getRegUseDefListHead(MO->getReg());
269  MachineOperand *const Head = HeadRef;
270 
271  // Head points to the first list element.
272  // Next is NULL on the last list element.
273  // Prev pointers are circular, so Head->Prev == Last.
274 
275  // Head is NULL for an empty list.
276  if (!Head) {
277  MO->Contents.Reg.Prev = MO;
278  MO->Contents.Reg.Next = nullptr;
279  HeadRef = MO;
280  return;
281  }
282  assert(MO->getReg() == Head->getReg() && "Different regs on the same list!");
283 
284  // Insert MO between Last and Head in the circular Prev chain.
285  MachineOperand *Last = Head->Contents.Reg.Prev;
286  assert(Last && "Inconsistent use list");
287  assert(MO->getReg() == Last->getReg() && "Different regs on the same list!");
288  Head->Contents.Reg.Prev = MO;
289  MO->Contents.Reg.Prev = Last;
290 
291  // Def operands always precede uses. This allows def_iterator to stop early.
292  // Insert def operands at the front, and use operands at the back.
293  if (MO->isDef()) {
294  // Insert def at the front.
295  MO->Contents.Reg.Next = Head;
296  HeadRef = MO;
297  } else {
298  // Insert use at the end.
299  MO->Contents.Reg.Next = nullptr;
300  Last->Contents.Reg.Next = MO;
301  }
302 }
303 
304 /// Remove MO from its use-def list.
306  assert(MO->isOnRegUseList() && "Operand not on use list");
307  MachineOperand *&HeadRef = getRegUseDefListHead(MO->getReg());
308  MachineOperand *const Head = HeadRef;
309  assert(Head && "List already empty");
310 
311  // Unlink this from the doubly linked list of operands.
312  MachineOperand *Next = MO->Contents.Reg.Next;
313  MachineOperand *Prev = MO->Contents.Reg.Prev;
314 
315  // Prev links are circular, next link is NULL instead of looping back to Head.
316  if (MO == Head)
317  HeadRef = Next;
318  else
319  Prev->Contents.Reg.Next = Next;
320 
321  (Next ? Next : Head)->Contents.Reg.Prev = Prev;
322 
323  MO->Contents.Reg.Prev = nullptr;
324  MO->Contents.Reg.Next = nullptr;
325 }
326 
327 /// Move NumOps operands from Src to Dst, updating use-def lists as needed.
328 ///
329 /// The Dst range is assumed to be uninitialized memory. (Or it may contain
330 /// operands that won't be destroyed, which is OK because the MO destructor is
331 /// trivial anyway).
332 ///
333 /// The Src and Dst ranges may overlap.
335  MachineOperand *Src,
336  unsigned NumOps) {
337  assert(Src != Dst && NumOps && "Noop moveOperands");
338 
339  // Copy backwards if Dst is within the Src range.
340  int Stride = 1;
341  if (Dst >= Src && Dst < Src + NumOps) {
342  Stride = -1;
343  Dst += NumOps - 1;
344  Src += NumOps - 1;
345  }
346 
347  // Copy one operand at a time.
348  do {
349  new (Dst) MachineOperand(*Src);
350 
351  // Dst takes Src's place in the use-def chain.
352  if (Src->isReg()) {
353  MachineOperand *&Head = getRegUseDefListHead(Src->getReg());
354  MachineOperand *Prev = Src->Contents.Reg.Prev;
355  MachineOperand *Next = Src->Contents.Reg.Next;
356  assert(Head && "List empty, but operand is chained");
357  assert(Prev && "Operand was not on use-def list");
358 
359  // Prev links are circular, next link is NULL instead of looping back to
360  // Head.
361  if (Src == Head)
362  Head = Dst;
363  else
364  Prev->Contents.Reg.Next = Dst;
365 
366  // Update Prev pointer. This also works when Src was pointing to itself
367  // in a 1-element list. In that case Head == Dst.
368  (Next ? Next : Head)->Contents.Reg.Prev = Dst;
369  }
370 
371  Dst += Stride;
372  Src += Stride;
373  } while (--NumOps);
374 }
375 
376 /// replaceRegWith - Replace all instances of FromReg with ToReg in the
377 /// machine function. This is like llvm-level X->replaceAllUsesWith(Y),
378 /// except that it also changes any definitions of the register as well.
379 /// If ToReg is a physical register we apply the sub register to obtain the
380 /// final/proper physical register.
381 void MachineRegisterInfo::replaceRegWith(unsigned FromReg, unsigned ToReg) {
382  assert(FromReg != ToReg && "Cannot replace a reg with itself");
383 
385 
386  // TODO: This could be more efficient by bulk changing the operands.
387  for (reg_iterator I = reg_begin(FromReg), E = reg_end(); I != E; ) {
388  MachineOperand &O = *I;
389  ++I;
391  O.substPhysReg(ToReg, *TRI);
392  } else {
393  O.setReg(ToReg);
394  }
395  }
396 }
397 
398 /// getVRegDef - Return the machine instr that defines the specified virtual
399 /// register or null if none is found. This assumes that the code is in SSA
400 /// form, so there should only be one definition.
402  // Since we are in SSA form, we can use the first definition.
404  assert((I.atEnd() || std::next(I) == def_instr_end()) &&
405  "getVRegDef assumes a single definition or no definition");
406  return !I.atEnd() ? &*I : nullptr;
407 }
408 
409 /// getUniqueVRegDef - Return the unique machine instr that defines the
410 /// specified virtual register or null if none is found. If there are
411 /// multiple definitions or no definition, return null.
413  if (def_empty(Reg)) return nullptr;
415  if (std::next(I) != def_instr_end())
416  return nullptr;
417  return &*I;
418 }
419 
420 bool MachineRegisterInfo::hasOneNonDBGUse(unsigned RegNo) const {
422  if (UI == use_nodbg_end())
423  return false;
424  return ++UI == use_nodbg_end();
425 }
426 
427 /// clearKillFlags - Iterate over all the uses of the given register and
428 /// clear the kill flag from the MachineOperand. This function is used by
429 /// optimization passes which extend register lifetimes and need only
430 /// preserve conservative kill flag information.
432  for (MachineOperand &MO : use_operands(Reg))
433  MO.setIsKill(false);
434 }
435 
436 bool MachineRegisterInfo::isLiveIn(unsigned Reg) const {
437  for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I)
438  if (I->first == Reg || I->second == Reg)
439  return true;
440  return false;
441 }
442 
443 /// getLiveInPhysReg - If VReg is a live-in virtual register, return the
444 /// corresponding live-in physical register.
445 unsigned MachineRegisterInfo::getLiveInPhysReg(unsigned VReg) const {
446  for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I)
447  if (I->second == VReg)
448  return I->first;
449  return 0;
450 }
451 
452 /// getLiveInVirtReg - If PReg is a live-in physical register, return the
453 /// corresponding live-in physical register.
454 unsigned MachineRegisterInfo::getLiveInVirtReg(unsigned PReg) const {
455  for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I)
456  if (I->first == PReg)
457  return I->second;
458  return 0;
459 }
460 
461 /// EmitLiveInCopies - Emit copies to initialize livein virtual registers
462 /// into the given entry block.
463 void
465  const TargetRegisterInfo &TRI,
466  const TargetInstrInfo &TII) {
467  // Emit the copies into the top of the block.
468  for (unsigned i = 0, e = LiveIns.size(); i != e; ++i)
469  if (LiveIns[i].second) {
470  if (use_nodbg_empty(LiveIns[i].second)) {
471  // The livein has no non-dbg uses. Drop it.
472  //
473  // It would be preferable to have isel avoid creating live-in
474  // records for unused arguments in the first place, but it's
475  // complicated by the debug info code for arguments.
476  LiveIns.erase(LiveIns.begin() + i);
477  --i; --e;
478  } else {
479  // Emit a copy.
480  BuildMI(*EntryMBB, EntryMBB->begin(), DebugLoc(),
481  TII.get(TargetOpcode::COPY), LiveIns[i].second)
482  .addReg(LiveIns[i].first);
483 
484  // Add the register to the entry block live-in set.
485  EntryMBB->addLiveIn(LiveIns[i].first);
486  }
487  } else {
488  // Add the register to the entry block live-in set.
489  EntryMBB->addLiveIn(LiveIns[i].first);
490  }
491 }
492 
494  // Lane masks are only defined for vregs.
496  const TargetRegisterClass &TRC = *getRegClass(Reg);
497  return TRC.getLaneMask();
498 }
499 
500 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
502  for (MachineInstr &I : use_instructions(Reg))
503  I.dump();
504 }
505 #endif
506 
508  ReservedRegs = getTargetRegisterInfo()->getReservedRegs(MF);
509  assert(ReservedRegs.size() == getTargetRegisterInfo()->getNumRegs() &&
510  "Invalid ReservedRegs vector from target");
511 }
512 
513 bool MachineRegisterInfo::isConstantPhysReg(unsigned PhysReg) const {
515 
517  if (TRI->isConstantPhysReg(PhysReg))
518  return true;
519 
520  // Check if any overlapping register is modified, or allocatable so it may be
521  // used later.
522  for (MCRegAliasIterator AI(PhysReg, TRI, true);
523  AI.isValid(); ++AI)
524  if (!def_empty(*AI) || isAllocatable(*AI))
525  return false;
526  return true;
527 }
528 
529 bool
532  return isConstantPhysReg(PhysReg) ||
533  TRI->isCallerPreservedPhysReg(PhysReg, *MF);
534 }
535 
536 /// markUsesInDebugValueAsUndef - Mark every DBG_VALUE referencing the
537 /// specified register as undefined which causes the DBG_VALUE to be
538 /// deleted during LiveDebugVariables analysis.
540  // Mark any DBG_VALUE that uses Reg as undef (but don't delete it.)
543  I != E; I = nextI) {
544  nextI = std::next(I); // I is invalidated by the setReg
545  MachineInstr *UseMI = &*I;
546  if (UseMI->isDebugValue())
547  UseMI->getOperand(0).setReg(0U);
548  }
549 }
550 
551 static const Function *getCalledFunction(const MachineInstr &MI) {
552  for (const MachineOperand &MO : MI.operands()) {
553  if (!MO.isGlobal())
554  continue;
555  const Function *Func = dyn_cast<Function>(MO.getGlobal());
556  if (Func != nullptr)
557  return Func;
558  }
559  return nullptr;
560 }
561 
562 static bool isNoReturnDef(const MachineOperand &MO) {
563  // Anything which is not a noreturn function is a real def.
564  const MachineInstr &MI = *MO.getParent();
565  if (!MI.isCall())
566  return false;
567  const MachineBasicBlock &MBB = *MI.getParent();
568  if (!MBB.succ_empty())
569  return false;
570  const MachineFunction &MF = *MBB.getParent();
571  // We need to keep correct unwind information even if the function will
572  // not return, since the runtime may need it.
573  if (MF.getFunction().hasFnAttribute(Attribute::UWTable))
574  return false;
575  const Function *Called = getCalledFunction(MI);
576  return !(Called == nullptr || !Called->hasFnAttribute(Attribute::NoReturn) ||
577  !Called->hasFnAttribute(Attribute::NoUnwind));
578 }
579 
581  bool SkipNoReturnDef) const {
582  if (UsedPhysRegMask.test(PhysReg))
583  return true;
585  for (MCRegAliasIterator AI(PhysReg, TRI, true); AI.isValid(); ++AI) {
586  for (const MachineOperand &MO : make_range(def_begin(*AI), def_end())) {
587  if (!SkipNoReturnDef && isNoReturnDef(MO))
588  continue;
589  return true;
590  }
591  }
592  return false;
593 }
594 
595 bool MachineRegisterInfo::isPhysRegUsed(unsigned PhysReg) const {
596  if (UsedPhysRegMask.test(PhysReg))
597  return true;
599  for (MCRegAliasIterator AliasReg(PhysReg, TRI, true); AliasReg.isValid();
600  ++AliasReg) {
601  if (!reg_nodbg_empty(*AliasReg))
602  return true;
603  }
604  return false;
605 }
606 
608 
610  assert(Reg && (Reg < TRI->getNumRegs()) &&
611  "Trying to disable an invalid register");
612 
613  if (!IsUpdatedCSRsInitialized) {
614  const MCPhysReg *CSR = TRI->getCalleeSavedRegs(MF);
615  for (const MCPhysReg *I = CSR; *I; ++I)
616  UpdatedCSRs.push_back(*I);
617 
618  // Zero value represents the end of the register list
619  // (no more registers should be pushed).
620  UpdatedCSRs.push_back(0);
621 
622  IsUpdatedCSRsInitialized = true;
623  }
624 
625  // Remove the register (and its aliases from the list).
626  for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI)
627  UpdatedCSRs.erase(std::remove(UpdatedCSRs.begin(), UpdatedCSRs.end(), *AI),
628  UpdatedCSRs.end());
629 }
630 
632  if (IsUpdatedCSRsInitialized)
633  return UpdatedCSRs.data();
634 
636 }
637 
639  if (IsUpdatedCSRsInitialized)
640  UpdatedCSRs.clear();
641 
642  for (MCPhysReg Reg : CSRs)
643  UpdatedCSRs.push_back(Reg);
644 
645  // Zero value represents the end of the register list
646  // (no more registers should be pushed).
647  UpdatedCSRs.push_back(0);
648  IsUpdatedCSRsInitialized = true;
649 }
650 
653  for (MCRegUnitRootIterator Root(Unit, TRI); Root.isValid(); ++Root) {
654  bool IsRootReserved = true;
655  for (MCSuperRegIterator Super(*Root, TRI, /*IncludeSelf=*/true);
656  Super.isValid(); ++Super) {
657  unsigned Reg = *Super;
658  if (!isReserved(Reg)) {
659  IsRootReserved = false;
660  break;
661  }
662  }
663  if (IsRootReserved)
664  return true;
665  }
666  return false;
667 }
bool reg_nodbg_empty(unsigned RegNo) const
reg_nodbg_empty - Return true if the only instructions using or defining Reg are Debug instructions...
void resize(unsigned N, bool t=false)
resize - Grow or shrink the bitvector.
Definition: BitVector.h:372
const TargetRegisterClass * getCommonSubClass(const TargetRegisterClass *A, const TargetRegisterClass *B, const MVT::SimpleValueType SVT=MVT::SimpleValueType::Any) const
Find the largest common subclass of A and B.
void push_back(const T &Elt)
Definition: SmallVector.h:218
void EmitLiveInCopies(MachineBasicBlock *EntryMBB, const TargetRegisterInfo &TRI, const TargetInstrInfo &TII)
EmitLiveInCopies - Emit copies to initialize livein virtual registers into the given entry block...
raw_ostream & errs()
This returns a reference to a raw_ostream for standard error.
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
bool use_nodbg_empty(unsigned RegNo) const
use_nodbg_empty - Return true if there are no non-Debug instructions using the specified register...
bool isCall(QueryType Type=AnyInBundle) const
Definition: MachineInstr.h:633
const TargetRegisterClass * getRegClass(unsigned Reg) const
Return the register class of the specified virtual register.
livein_iterator livein_begin() const
void removeRegOperandFromUseList(MachineOperand *MO)
Remove MO from its use-def list.
bool isAllocatable(unsigned PhysReg) const
isAllocatable - Returns true when PhysReg belongs to an allocatable register class and it hasn&#39;t been...
void clearVirtRegTypes()
Remove all types associated to virtual registers (after instruction selection and constraining of all...
LaneBitmask getMaxLaneMaskForVReg(unsigned Reg) const
Returns a mask covering all bits that can appear in lane masks of subregisters of the virtual registe...
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
unsigned getNumRegs() const
Return the number of registers in this class.
static const TargetRegisterClass * constrainRegClass(MachineRegisterInfo &MRI, unsigned Reg, const TargetRegisterClass *OldRC, const TargetRegisterClass *RC, unsigned MinNumRegs)
static unsigned index2VirtReg(unsigned Index)
Convert a 0-based index to a virtual register number.
std::error_code remove(const Twine &path, bool IgnoreNonExisting=true)
Remove path.
bool isPhysRegModified(unsigned PhysReg, bool SkipNoReturnDef=false) const
Return true if the specified register is modified in this function.
This provides a very simple, boring adaptor for a begin and end iterator into a range type...
unsigned getReg() const
getReg - Returns the register number.
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
iterator_range< reg_nodbg_iterator > reg_nodbg_operands(unsigned Reg) const
unsigned Reg
bool test(unsigned Idx) const
Definition: BitVector.h:502
iterator_range< reg_iterator > reg_operands(unsigned Reg) const
bool constrainRegAttrs(unsigned Reg, unsigned ConstrainingReg, unsigned MinNumRegs=0)
Constrain the register class or the register bank of the virtual register Reg (and low-level type) to...
LLT getType(unsigned Reg) const
Get the low-level type of Reg or LLT{} if Reg is not a generic (target independent) virtual register...
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
Definition: Function.h:321
unsigned second
unsigned const TargetRegisterInfo * TRI
A debug info location.
Definition: DebugLoc.h:34
void setRegBank(unsigned Reg, const RegisterBank &RegBank)
Set the register bank to RegBank for Reg.
iterator_range< mop_iterator > operands()
Definition: MachineInstr.h:459
use_nodbg_iterator use_nodbg_begin(unsigned RegNo) const
void verifyUseLists() const
Verify the use list of all registers.
static use_nodbg_iterator use_nodbg_end()
void clearVirtRegs()
clearVirtRegs - Remove all virtual registers (after physreg assignment).
amdgpu Simplify well known AMD library false Value Value const Twine & Name
MCSuperRegIterator enumerates all super-registers of Reg.
const HexagonInstrInfo * TII
unsigned getNumOperands() const
Retuns the total number of operands.
Definition: MachineInstr.h:412
Printable printReg(unsigned Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
void freezeReservedRegs(const MachineFunction &)
freezeReservedRegs - Called by the register allocator to freeze the set of reserved registers before ...
This file contains the simple types necessary to represent the attributes associated with functions a...
def_iterator def_begin(unsigned RegNo) const
#define LLVM_DUMP_METHOD
Definition: Compiler.h:74
const TargetRegisterClass * getRegClassConstraintEffect(unsigned OpIdx, const TargetRegisterClass *CurRC, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const
Applies the constraints (def/use) implied by the OpIdx operand to the given CurRC.
unsigned getLiveInPhysReg(unsigned VReg) const
getLiveInPhysReg - If VReg is a live-in virtual register, return the corresponding live-in physical r...
MachineInstr * getVRegDef(unsigned Reg) const
getVRegDef - Return the machine instr that defines the specified virtual register or null if none is ...
defusechain_iterator - This class provides iterator support for machine operands in the function that...
static cl::opt< bool > EnableSubRegLiveness("enable-subreg-liveness", cl::Hidden, cl::init(true), cl::desc("Enable subregister liveness tracking."))
void insertVRegByName(StringRef Name, unsigned Reg)
void clearKillFlags(unsigned Reg) const
clearKillFlags - Iterate over all the uses of the given register and clear the kill flag from the Mac...
const RegClassOrRegBank & getRegClassOrRegBank(unsigned Reg) const
Return the register bank or register class of Reg.
MCRegUnitRootIterator enumerates the root registers of a register unit.
struct llvm::MachineOperand::@159::@161 Reg
livein_iterator livein_end() const
static def_instr_iterator def_instr_end()
virtual const TargetRegisterClass * getLargestLegalSuperClass(const TargetRegisterClass *RC, const MachineFunction &) const
Returns the largest super class of RC that is legal to use in the current sub-target and has the same...
virtual const TargetInstrInfo * getInstrInfo() const
LaneBitmask getLaneMask() const
Returns the combination of all lane masks of register in this class.
virtual const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const =0
Return a null-terminated list of all of the callee-saved registers on this target.
void disableCalleeSavedRegister(unsigned Reg)
Disables the register from the list of CSRs.
const TargetRegisterClass * constrainRegClass(unsigned Reg, const TargetRegisterClass *RC, unsigned MinNumRegs=0)
constrainRegClass - Constrain the register class of the specified virtual register to be a common sub...
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
TargetInstrInfo - Interface to description of machine instruction set.
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
unsigned getNumRegs() const
Return the number of registers this target has (useful for sizing arrays holding per register informa...
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:419
void addLiveIn(MCPhysReg PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())
Adds the specified register as a live in.
const TargetRegisterInfo * getTargetRegisterInfo() const
unsigned const MachineRegisterInfo * MRI
bool isCallerPreservedOrConstPhysReg(unsigned PhysReg) const
Returns true if either isConstantPhysReg or TRI->isCallerPreservedPhysReg returns true...
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineInstrBuilder & UseMI
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
LLVM_ATTRIBUTE_ALWAYS_INLINE iterator begin()
Definition: SmallVector.h:129
struct UnitT Unit
void setType(unsigned VReg, LLT Ty)
Set the low-level type of VReg to Ty.
MCRegAliasIterator enumerates all registers aliasing Reg.
use_instr_iterator use_instr_begin(unsigned RegNo) const
bool isValid() const
void substPhysReg(unsigned Reg, const TargetRegisterInfo &)
substPhysReg - Substitute the current register with the physical register Reg, taking any existing Su...
bool def_empty(unsigned RegNo) const
def_empty - Return true if there are no instructions defining the specified register (it may be live-...
void setCalleeSavedRegs(ArrayRef< MCPhysReg > CSRs)
Sets the updated Callee Saved Registers list.
unsigned getNumVirtRegs() const
getNumVirtRegs - Return the number of virtual registers created.
virtual bool isConstantPhysReg(unsigned PhysReg) const
Returns true if PhysReg is unallocatable and constant throughout the function.
iterator erase(const_iterator CI)
Definition: SmallVector.h:445
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
static const Function * getCalledFunction(const MachineInstr &MI)
bool isConstantPhysReg(unsigned PhysReg) const
Returns true if PhysReg is unallocatable and constant throughout the function.
unsigned first
unsigned createGenericVirtualRegister(LLT Ty, StringRef Name="")
Create and return a new generic virtual register with low-level type Ty.
iterator_range< T > make_range(T x, T y)
Convenience function for iterating over sub-ranges.
unsigned createIncompleteVirtualRegister(StringRef Name="")
Creates a new virtual register that has no register class, register bank or size assigned yet...
iterator_range< use_iterator > use_operands(unsigned Reg) const
bool isDebugValue() const
Definition: MachineInstr.h:997
MachineOperand class - Representation of each machine instruction operand.
bool atEnd() const
atEnd - return true if this iterator is equal to reg_end() on the value.
bool isReservedRegUnit(unsigned Unit) const
Returns true when the given register unit is considered reserved.
reg_iterator reg_begin(unsigned RegNo) const
This class implements the register bank concept.
Definition: RegisterBank.h:29
bool recomputeRegClass(unsigned Reg)
recomputeRegClass - Try to find a legal super-class of Reg&#39;s register class that still satisfies the ...
MachineInstr * getUniqueVRegDef(unsigned Reg) const
getUniqueVRegDef - Return the unique machine instr that defines the specified virtual register or nul...
const Function & getFunction() const
Return the LLVM function that this machine code represents.
bool isPhysRegUsed(unsigned PhysReg) const
Return true if the specified register is modified or read in this function.
virtual BitVector getReservedRegs(const MachineFunction &MF) const =0
Returns a bitset indexed by physical register number indicating if a register is a special register t...
bool isValid() const
isValid - returns true if this iterator is not yet at the end.
unsigned cloneVirtualRegister(unsigned VReg, StringRef Name="")
Create and return a new virtual register in the function with the same attributes as the given regist...
void verifyUseList(unsigned Reg) const
Verify the sanity of the use list for Reg.
void dumpUses(unsigned RegNo) const
def_instr_iterator def_instr_begin(unsigned RegNo) const
void replaceRegWith(unsigned FromReg, unsigned ToReg)
replaceRegWith - Replace all instances of FromReg with ToReg in the machine function.
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:254
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
bool isLiveIn(unsigned Reg) const
Representation of each machine instruction.
Definition: MachineInstr.h:64
std::vector< std::pair< unsigned, unsigned > >::const_iterator livein_iterator
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
LLVM_ATTRIBUTE_ALWAYS_INLINE iterator end()
Definition: SmallVector.h:133
pointer data()
Return a pointer to the vector&#39;s buffer, even if empty().
Definition: SmallVector.h:149
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode...
Definition: MCInstrInfo.h:45
void setReg(unsigned Reg)
Change the register this operand corresponds to.
#define I(x, y, z)
Definition: MD5.cpp:58
virtual bool isCallerPreservedPhysReg(unsigned PhysReg, const MachineFunction &MF) const
Physical registers that may be modified within a function but are guaranteed to be restored before an...
LLVM_NODISCARD std::enable_if<!is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
Definition: Casting.h:323
void markUsesInDebugValueAsUndef(unsigned Reg) const
markUsesInDebugValueAsUndef - Mark every DBG_VALUE referencing the specified register as undefined wh...
size_type size() const
size - Returns the number of bits in this bitvector.
Definition: BitVector.h:170
bool isAllocatable() const
Return true if this register class may be used to create virtual registers.
bool hasOneNonDBGUse(unsigned RegNo) const
hasOneNonDBGUse - Return true if there is exactly one non-Debug instruction using the specified regis...
bool isReg() const
isReg - Tests if this is a MO_Register operand.
iterator_range< use_instr_iterator > use_instructions(unsigned Reg) const
void grow(IndexT n)
Definition: IndexedMap.h:68
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static def_iterator def_end()
MachineRegisterInfo(MachineFunction *MF)
static bool isNoReturnDef(const MachineOperand &MO)
void moveOperands(MachineOperand *Dst, MachineOperand *Src, unsigned NumOps)
Move NumOps operands from Src to Dst, updating use-def lists as needed.
static use_instr_iterator use_instr_end()
const MCPhysReg * getCalleeSavedRegs() const
Returns list of callee saved registers.
IRTranslator LLVM IR MI
void setRegClass(unsigned Reg, const TargetRegisterClass *RC)
setRegClass - Set the register class of the specified virtual register.
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:49
virtual void MRI_NoteNewVirtualRegister(unsigned Reg)=0
bool isValid() const
Check if the iterator is at the end of the list.
void setRegClassOrRegBank(unsigned Reg, const RegClassOrRegBank &RCOrRB)
static reg_iterator reg_end()
unsigned getLiveInVirtReg(unsigned PReg) const
getLiveInVirtReg - If PReg is a live-in physical register, return the corresponding live-in physical ...
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:414
reg_begin/reg_end - Provide iteration support to walk over all definitions and uses of a register wit...
unsigned createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
bool isReserved(unsigned PhysReg) const
isReserved - Returns true when PhysReg is a reserved register.
void addRegOperandToUseList(MachineOperand *MO)
Add MO to the linked list of operands for its register.