LLVM  9.0.0svn
MachineInstr.h
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1 //===- llvm/CodeGen/MachineInstr.h - MachineInstr class ---------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the declaration of the MachineInstr class, which is the
10 // basic representation for all target dependent machine instructions used by
11 // the back end.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #ifndef LLVM_CODEGEN_MACHINEINSTR_H
16 #define LLVM_CODEGEN_MACHINEINSTR_H
17 
18 #include "llvm/ADT/DenseMapInfo.h"
20 #include "llvm/ADT/ilist.h"
21 #include "llvm/ADT/ilist_node.h"
27 #include "llvm/IR/DebugLoc.h"
28 #include "llvm/IR/InlineAsm.h"
29 #include "llvm/MC/MCInstrDesc.h"
30 #include "llvm/MC/MCSymbol.h"
33 #include <algorithm>
34 #include <cassert>
35 #include <cstdint>
36 #include <utility>
37 
38 namespace llvm {
39 
40 template <typename T> class ArrayRef;
41 class DIExpression;
42 class DILocalVariable;
43 class MachineBasicBlock;
44 class MachineFunction;
45 class MachineMemOperand;
46 class MachineRegisterInfo;
47 class ModuleSlotTracker;
48 class raw_ostream;
49 template <typename T> class SmallVectorImpl;
50 class SmallBitVector;
51 class StringRef;
52 class TargetInstrInfo;
53 class TargetRegisterClass;
54 class TargetRegisterInfo;
55 
56 //===----------------------------------------------------------------------===//
57 /// Representation of each machine instruction.
58 ///
59 /// This class isn't a POD type, but it must have a trivial destructor. When a
60 /// MachineFunction is deleted, all the contained MachineInstrs are deallocated
61 /// without having their destructor called.
62 ///
64  : public ilist_node_with_parent<MachineInstr, MachineBasicBlock,
65  ilist_sentinel_tracking<true>> {
66 public:
68 
69  /// Flags to specify different kinds of comments to output in
70  /// assembly code. These flags carry semantic information not
71  /// otherwise easily derivable from the IR text.
72  ///
73  enum CommentFlag {
74  ReloadReuse = 0x1, // higher bits are reserved for target dep comments.
76  TAsmComments = 0x4 // Target Asm comments should start from this value.
77  };
78 
79  enum MIFlag {
80  NoFlags = 0,
81  FrameSetup = 1 << 0, // Instruction is used as a part of
82  // function frame setup code.
83  FrameDestroy = 1 << 1, // Instruction is used as a part of
84  // function frame destruction code.
85  BundledPred = 1 << 2, // Instruction has bundled predecessors.
86  BundledSucc = 1 << 3, // Instruction has bundled successors.
87  FmNoNans = 1 << 4, // Instruction does not support Fast
88  // math nan values.
89  FmNoInfs = 1 << 5, // Instruction does not support Fast
90  // math infinity values.
91  FmNsz = 1 << 6, // Instruction is not required to retain
92  // signed zero values.
93  FmArcp = 1 << 7, // Instruction supports Fast math
94  // reciprocal approximations.
95  FmContract = 1 << 8, // Instruction supports Fast math
96  // contraction operations like fma.
97  FmAfn = 1 << 9, // Instruction may map to Fast math
98  // instrinsic approximation.
99  FmReassoc = 1 << 10, // Instruction supports Fast math
100  // reassociation of operand order.
101  NoUWrap = 1 << 11, // Instruction supports binary operator
102  // no unsigned wrap.
103  NoSWrap = 1 << 12, // Instruction supports binary operator
104  // no signed wrap.
105  IsExact = 1 << 13 // Instruction supports division is
106  // known to be exact.
107  };
108 
109 private:
110  const MCInstrDesc *MCID; // Instruction descriptor.
111  MachineBasicBlock *Parent = nullptr; // Pointer to the owning basic block.
112 
113  // Operands are allocated by an ArrayRecycler.
114  MachineOperand *Operands = nullptr; // Pointer to the first operand.
115  unsigned NumOperands = 0; // Number of operands on instruction.
116  using OperandCapacity = ArrayRecycler<MachineOperand>::Capacity;
117  OperandCapacity CapOperands; // Capacity of the Operands array.
118 
119  uint16_t Flags = 0; // Various bits of additional
120  // information about machine
121  // instruction.
122 
123  uint8_t AsmPrinterFlags = 0; // Various bits of information used by
124  // the AsmPrinter to emit helpful
125  // comments. This is *not* semantic
126  // information. Do not use this for
127  // anything other than to convey comment
128  // information to AsmPrinter.
129 
130  /// Internal implementation detail class that provides out-of-line storage for
131  /// extra info used by the machine instruction when this info cannot be stored
132  /// in-line within the instruction itself.
133  ///
134  /// This has to be defined eagerly due to the implementation constraints of
135  /// `PointerSumType` where it is used.
136  class ExtraInfo final
137  : TrailingObjects<ExtraInfo, MachineMemOperand *, MCSymbol *> {
138  public:
139  static ExtraInfo *create(BumpPtrAllocator &Allocator,
141  MCSymbol *PreInstrSymbol = nullptr,
142  MCSymbol *PostInstrSymbol = nullptr) {
143  bool HasPreInstrSymbol = PreInstrSymbol != nullptr;
144  bool HasPostInstrSymbol = PostInstrSymbol != nullptr;
145  auto *Result = new (Allocator.Allocate(
146  totalSizeToAlloc<MachineMemOperand *, MCSymbol *>(
147  MMOs.size(), HasPreInstrSymbol + HasPostInstrSymbol),
148  alignof(ExtraInfo)))
149  ExtraInfo(MMOs.size(), HasPreInstrSymbol, HasPostInstrSymbol);
150 
151  // Copy the actual data into the trailing objects.
152  std::copy(MMOs.begin(), MMOs.end(),
153  Result->getTrailingObjects<MachineMemOperand *>());
154 
155  if (HasPreInstrSymbol)
156  Result->getTrailingObjects<MCSymbol *>()[0] = PreInstrSymbol;
157  if (HasPostInstrSymbol)
158  Result->getTrailingObjects<MCSymbol *>()[HasPreInstrSymbol] =
159  PostInstrSymbol;
160 
161  return Result;
162  }
163 
164  ArrayRef<MachineMemOperand *> getMMOs() const {
165  return makeArrayRef(getTrailingObjects<MachineMemOperand *>(), NumMMOs);
166  }
167 
168  MCSymbol *getPreInstrSymbol() const {
169  return HasPreInstrSymbol ? getTrailingObjects<MCSymbol *>()[0] : nullptr;
170  }
171 
172  MCSymbol *getPostInstrSymbol() const {
173  return HasPostInstrSymbol
174  ? getTrailingObjects<MCSymbol *>()[HasPreInstrSymbol]
175  : nullptr;
176  }
177 
178  private:
179  friend TrailingObjects;
180 
181  // Description of the extra info, used to interpret the actual optional
182  // data appended.
183  //
184  // Note that this is not terribly space optimized. This leaves a great deal
185  // of flexibility to fit more in here later.
186  const int NumMMOs;
187  const bool HasPreInstrSymbol;
188  const bool HasPostInstrSymbol;
189 
190  // Implement the `TrailingObjects` internal API.
191  size_t numTrailingObjects(OverloadToken<MachineMemOperand *>) const {
192  return NumMMOs;
193  }
194  size_t numTrailingObjects(OverloadToken<MCSymbol *>) const {
195  return HasPreInstrSymbol + HasPostInstrSymbol;
196  }
197 
198  // Just a boring constructor to allow us to initialize the sizes. Always use
199  // the `create` routine above.
200  ExtraInfo(int NumMMOs, bool HasPreInstrSymbol, bool HasPostInstrSymbol)
201  : NumMMOs(NumMMOs), HasPreInstrSymbol(HasPreInstrSymbol),
202  HasPostInstrSymbol(HasPostInstrSymbol) {}
203  };
204 
205  /// Enumeration of the kinds of inline extra info available. It is important
206  /// that the `MachineMemOperand` inline kind has a tag value of zero to make
207  /// it accessible as an `ArrayRef`.
208  enum ExtraInfoInlineKinds {
209  EIIK_MMO = 0,
210  EIIK_PreInstrSymbol,
211  EIIK_PostInstrSymbol,
212  EIIK_OutOfLine
213  };
214 
215  // We store extra information about the instruction here. The common case is
216  // expected to be nothing or a single pointer (typically a MMO or a symbol).
217  // We work to optimize this common case by storing it inline here rather than
218  // requiring a separate allocation, but we fall back to an allocation when
219  // multiple pointers are needed.
220  PointerSumType<ExtraInfoInlineKinds,
225  Info;
226 
227  DebugLoc debugLoc; // Source line information.
228 
229  // Intrusive list support
230  friend struct ilist_traits<MachineInstr>;
232  void setParent(MachineBasicBlock *P) { Parent = P; }
233 
234  /// This constructor creates a copy of the given
235  /// MachineInstr in the given MachineFunction.
237 
238  /// This constructor create a MachineInstr and add the implicit operands.
239  /// It reserves space for number of operands specified by
240  /// MCInstrDesc. An explicit DebugLoc is supplied.
242  bool NoImp = false);
243 
244  // MachineInstrs are pool-allocated and owned by MachineFunction.
245  friend class MachineFunction;
246 
247 public:
248  MachineInstr(const MachineInstr &) = delete;
249  MachineInstr &operator=(const MachineInstr &) = delete;
250  // Use MachineFunction::DeleteMachineInstr() instead.
251  ~MachineInstr() = delete;
252 
253  const MachineBasicBlock* getParent() const { return Parent; }
254  MachineBasicBlock* getParent() { return Parent; }
255 
256  /// Return the function that contains the basic block that this instruction
257  /// belongs to.
258  ///
259  /// Note: this is undefined behaviour if the instruction does not have a
260  /// parent.
261  const MachineFunction *getMF() const;
263  return const_cast<MachineFunction *>(
264  static_cast<const MachineInstr *>(this)->getMF());
265  }
266 
267  /// Return the asm printer flags bitvector.
268  uint8_t getAsmPrinterFlags() const { return AsmPrinterFlags; }
269 
270  /// Clear the AsmPrinter bitvector.
271  void clearAsmPrinterFlags() { AsmPrinterFlags = 0; }
272 
273  /// Return whether an AsmPrinter flag is set.
275  return AsmPrinterFlags & Flag;
276  }
277 
278  /// Set a flag for the AsmPrinter.
279  void setAsmPrinterFlag(uint8_t Flag) {
280  AsmPrinterFlags |= Flag;
281  }
282 
283  /// Clear specific AsmPrinter flags.
285  AsmPrinterFlags &= ~Flag;
286  }
287 
288  /// Return the MI flags bitvector.
289  uint16_t getFlags() const {
290  return Flags;
291  }
292 
293  /// Return whether an MI flag is set.
294  bool getFlag(MIFlag Flag) const {
295  return Flags & Flag;
296  }
297 
298  /// Set a MI flag.
300  Flags |= (uint16_t)Flag;
301  }
302 
303  void setFlags(unsigned flags) {
304  // Filter out the automatically maintained flags.
305  unsigned Mask = BundledPred | BundledSucc;
306  Flags = (Flags & Mask) | (flags & ~Mask);
307  }
308 
309  /// clearFlag - Clear a MI flag.
311  Flags &= ~((uint16_t)Flag);
312  }
313 
314  /// Return true if MI is in a bundle (but not the first MI in a bundle).
315  ///
316  /// A bundle looks like this before it's finalized:
317  /// ----------------
318  /// | MI |
319  /// ----------------
320  /// |
321  /// ----------------
322  /// | MI * |
323  /// ----------------
324  /// |
325  /// ----------------
326  /// | MI * |
327  /// ----------------
328  /// In this case, the first MI starts a bundle but is not inside a bundle, the
329  /// next 2 MIs are considered "inside" the bundle.
330  ///
331  /// After a bundle is finalized, it looks like this:
332  /// ----------------
333  /// | Bundle |
334  /// ----------------
335  /// |
336  /// ----------------
337  /// | MI * |
338  /// ----------------
339  /// |
340  /// ----------------
341  /// | MI * |
342  /// ----------------
343  /// |
344  /// ----------------
345  /// | MI * |
346  /// ----------------
347  /// The first instruction has the special opcode "BUNDLE". It's not "inside"
348  /// a bundle, but the next three MIs are.
349  bool isInsideBundle() const {
350  return getFlag(BundledPred);
351  }
352 
353  /// Return true if this instruction part of a bundle. This is true
354  /// if either itself or its following instruction is marked "InsideBundle".
355  bool isBundled() const {
356  return isBundledWithPred() || isBundledWithSucc();
357  }
358 
359  /// Return true if this instruction is part of a bundle, and it is not the
360  /// first instruction in the bundle.
361  bool isBundledWithPred() const { return getFlag(BundledPred); }
362 
363  /// Return true if this instruction is part of a bundle, and it is not the
364  /// last instruction in the bundle.
365  bool isBundledWithSucc() const { return getFlag(BundledSucc); }
366 
367  /// Bundle this instruction with its predecessor. This can be an unbundled
368  /// instruction, or it can be the first instruction in a bundle.
369  void bundleWithPred();
370 
371  /// Bundle this instruction with its successor. This can be an unbundled
372  /// instruction, or it can be the last instruction in a bundle.
373  void bundleWithSucc();
374 
375  /// Break bundle above this instruction.
376  void unbundleFromPred();
377 
378  /// Break bundle below this instruction.
379  void unbundleFromSucc();
380 
381  /// Returns the debug location id of this MachineInstr.
382  const DebugLoc &getDebugLoc() const { return debugLoc; }
383 
384  /// Return the debug variable referenced by
385  /// this DBG_VALUE instruction.
386  const DILocalVariable *getDebugVariable() const;
387 
388  /// Return the complex address expression referenced by
389  /// this DBG_VALUE instruction.
390  const DIExpression *getDebugExpression() const;
391 
392  /// Return the debug label referenced by
393  /// this DBG_LABEL instruction.
394  const DILabel *getDebugLabel() const;
395 
396  /// Emit an error referring to the source location of this instruction.
397  /// This should only be used for inline assembly that is somehow
398  /// impossible to compile. Other errors should have been handled much
399  /// earlier.
400  ///
401  /// If this method returns, the caller should try to recover from the error.
402  void emitError(StringRef Msg) const;
403 
404  /// Returns the target instruction descriptor of this MachineInstr.
405  const MCInstrDesc &getDesc() const { return *MCID; }
406 
407  /// Returns the opcode of this MachineInstr.
408  unsigned getOpcode() const { return MCID->Opcode; }
409 
410  /// Retuns the total number of operands.
411  unsigned getNumOperands() const { return NumOperands; }
412 
413  const MachineOperand& getOperand(unsigned i) const {
414  assert(i < getNumOperands() && "getOperand() out of range!");
415  return Operands[i];
416  }
417  MachineOperand& getOperand(unsigned i) {
418  assert(i < getNumOperands() && "getOperand() out of range!");
419  return Operands[i];
420  }
421 
422  /// Returns the total number of definitions.
423  unsigned getNumDefs() const {
424  return getNumExplicitDefs() + MCID->getNumImplicitDefs();
425  }
426 
427  /// Return true if operand \p OpIdx is a subregister index.
428  bool isOperandSubregIdx(unsigned OpIdx) const {
430  "Expected MO_Immediate operand type.");
431  if (isExtractSubreg() && OpIdx == 2)
432  return true;
433  if (isInsertSubreg() && OpIdx == 3)
434  return true;
435  if (isRegSequence() && OpIdx > 1 && (OpIdx % 2) == 0)
436  return true;
437  if (isSubregToReg() && OpIdx == 3)
438  return true;
439  return false;
440  }
441 
442  /// Returns the number of non-implicit operands.
443  unsigned getNumExplicitOperands() const;
444 
445  /// Returns the number of non-implicit definitions.
446  unsigned getNumExplicitDefs() const;
447 
448  /// iterator/begin/end - Iterate over all operands of a machine instruction.
451 
452  mop_iterator operands_begin() { return Operands; }
453  mop_iterator operands_end() { return Operands + NumOperands; }
454 
455  const_mop_iterator operands_begin() const { return Operands; }
456  const_mop_iterator operands_end() const { return Operands + NumOperands; }
457 
460  }
463  }
465  return make_range(operands_begin(),
467  }
469  return make_range(operands_begin(),
471  }
474  }
477  }
478  /// Returns a range over all explicit operands that are register definitions.
479  /// Implicit definition are not included!
481  return make_range(operands_begin(),
483  }
484  /// \copydoc defs()
486  return make_range(operands_begin(),
488  }
489  /// Returns a range that includes all operands that are register uses.
490  /// This may include unrelated operands which are not register uses.
493  }
494  /// \copydoc uses()
497  }
501  }
505  }
506 
507  /// Returns the number of the operand iterator \p I points to.
509  return I - operands_begin();
510  }
511 
512  /// Access to memory operands of the instruction. If there are none, that does
513  /// not imply anything about whether the function accesses memory. Instead,
514  /// the caller must behave conservatively.
516  if (!Info)
517  return {};
518 
519  if (Info.is<EIIK_MMO>())
520  return makeArrayRef(Info.getAddrOfZeroTagPointer(), 1);
521 
522  if (ExtraInfo *EI = Info.get<EIIK_OutOfLine>())
523  return EI->getMMOs();
524 
525  return {};
526  }
527 
528  /// Access to memory operands of the instruction.
529  ///
530  /// If `memoperands_begin() == memoperands_end()`, that does not imply
531  /// anything about whether the function accesses memory. Instead, the caller
532  /// must behave conservatively.
533  mmo_iterator memoperands_begin() const { return memoperands().begin(); }
534 
535  /// Access to memory operands of the instruction.
536  ///
537  /// If `memoperands_begin() == memoperands_end()`, that does not imply
538  /// anything about whether the function accesses memory. Instead, the caller
539  /// must behave conservatively.
540  mmo_iterator memoperands_end() const { return memoperands().end(); }
541 
542  /// Return true if we don't have any memory operands which described the
543  /// memory access done by this instruction. If this is true, calling code
544  /// must be conservative.
545  bool memoperands_empty() const { return memoperands().empty(); }
546 
547  /// Return true if this instruction has exactly one MachineMemOperand.
548  bool hasOneMemOperand() const { return memoperands().size() == 1; }
549 
550  /// Return the number of memory operands.
551  unsigned getNumMemOperands() const { return memoperands().size(); }
552 
553  /// Helper to extract a pre-instruction symbol if one has been added.
555  if (!Info)
556  return nullptr;
557  if (MCSymbol *S = Info.get<EIIK_PreInstrSymbol>())
558  return S;
559  if (ExtraInfo *EI = Info.get<EIIK_OutOfLine>())
560  return EI->getPreInstrSymbol();
561 
562  return nullptr;
563  }
564 
565  /// Helper to extract a post-instruction symbol if one has been added.
567  if (!Info)
568  return nullptr;
569  if (MCSymbol *S = Info.get<EIIK_PostInstrSymbol>())
570  return S;
571  if (ExtraInfo *EI = Info.get<EIIK_OutOfLine>())
572  return EI->getPostInstrSymbol();
573 
574  return nullptr;
575  }
576 
577  /// API for querying MachineInstr properties. They are the same as MCInstrDesc
578  /// queries but they are bundle aware.
579 
580  enum QueryType {
581  IgnoreBundle, // Ignore bundles
582  AnyInBundle, // Return true if any instruction in bundle has property
583  AllInBundle // Return true if all instructions in bundle have property
584  };
585 
586  /// Return true if the instruction (or in the case of a bundle,
587  /// the instructions inside the bundle) has the specified property.
588  /// The first argument is the property being queried.
589  /// The second argument indicates whether the query should look inside
590  /// instruction bundles.
591  bool hasProperty(unsigned MCFlag, QueryType Type = AnyInBundle) const {
592  assert(MCFlag < 64 &&
593  "MCFlag out of range for bit mask in getFlags/hasPropertyInBundle.");
594  // Inline the fast path for unbundled or bundle-internal instructions.
595  if (Type == IgnoreBundle || !isBundled() || isBundledWithPred())
596  return getDesc().getFlags() & (1ULL << MCFlag);
597 
598  // If this is the first instruction in a bundle, take the slow path.
599  return hasPropertyInBundle(1ULL << MCFlag, Type);
600  }
601 
602  /// Return true if this instruction can have a variable number of operands.
603  /// In this case, the variable operands will be after the normal
604  /// operands but before the implicit definitions and uses (if any are
605  /// present).
608  }
609 
610  /// Set if this instruction has an optional definition, e.g.
611  /// ARM instructions which can set condition code if 's' bit is set.
614  }
615 
616  /// Return true if this is a pseudo instruction that doesn't
617  /// correspond to a real machine instruction.
619  return hasProperty(MCID::Pseudo, Type);
620  }
621 
623  return hasProperty(MCID::Return, Type);
624  }
625 
626  /// Return true if this is an instruction that marks the end of an EH scope,
627  /// i.e., a catchpad or a cleanuppad instruction.
630  }
631 
633  return hasProperty(MCID::Call, Type);
634  }
635 
636  /// Returns true if the specified instruction stops control flow
637  /// from executing the instruction immediately following it. Examples include
638  /// unconditional branches and return instructions.
640  return hasProperty(MCID::Barrier, Type);
641  }
642 
643  /// Returns true if this instruction part of the terminator for a basic block.
644  /// Typically this is things like return and branch instructions.
645  ///
646  /// Various passes use this to insert code into the bottom of a basic block,
647  /// but before control flow occurs.
650  }
651 
652  /// Returns true if this is a conditional, unconditional, or indirect branch.
653  /// Predicates below can be used to discriminate between
654  /// these cases, and the TargetInstrInfo::AnalyzeBranch method can be used to
655  /// get more information.
657  return hasProperty(MCID::Branch, Type);
658  }
659 
660  /// Return true if this is an indirect branch, such as a
661  /// branch through a register.
664  }
665 
666  /// Return true if this is a branch which may fall
667  /// through to the next instruction or may transfer control flow to some other
668  /// block. The TargetInstrInfo::AnalyzeBranch method can be used to get more
669  /// information about this branch.
672  }
673 
674  /// Return true if this is a branch which always
675  /// transfers control flow to some other block. The
676  /// TargetInstrInfo::AnalyzeBranch method can be used to get more information
677  /// about this branch.
680  }
681 
682  /// Return true if this instruction has a predicate operand that
683  /// controls execution. It may be set to 'always', or may be set to other
684  /// values. There are various methods in TargetInstrInfo that can be used to
685  /// control and modify the predicate in this instruction.
687  // If it's a bundle than all bundled instructions must be predicable for this
688  // to return true.
690  }
691 
692  /// Return true if this instruction is a comparison.
694  return hasProperty(MCID::Compare, Type);
695  }
696 
697  /// Return true if this instruction is a move immediate
698  /// (including conditional moves) instruction.
700  return hasProperty(MCID::MoveImm, Type);
701  }
702 
703  /// Return true if this instruction is a register move.
704  /// (including moving values from subreg to reg)
706  return hasProperty(MCID::MoveReg, Type);
707  }
708 
709  /// Return true if this instruction is a bitcast instruction.
711  return hasProperty(MCID::Bitcast, Type);
712  }
713 
714  /// Return true if this instruction is a select instruction.
716  return hasProperty(MCID::Select, Type);
717  }
718 
719  /// Return true if this instruction cannot be safely duplicated.
720  /// For example, if the instruction has a unique labels attached
721  /// to it, duplicating it would cause multiple definition errors.
724  }
725 
726  /// Return true if this instruction is convergent.
727  /// Convergent instructions can not be made control-dependent on any
728  /// additional values.
730  if (isInlineAsm()) {
731  unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
732  if (ExtraInfo & InlineAsm::Extra_IsConvergent)
733  return true;
734  }
736  }
737 
738  /// Returns true if the specified instruction has a delay slot
739  /// which must be filled by the code generator.
742  }
743 
744  /// Return true for instructions that can be folded as
745  /// memory operands in other instructions. The most common use for this
746  /// is instructions that are simple loads from memory that don't modify
747  /// the loaded value in any way, but it can also be used for instructions
748  /// that can be expressed as constant-pool loads, such as V_SETALLONES
749  /// on x86, to allow them to be folded when it is beneficial.
750  /// This should only be set on instructions that return a value in their
751  /// only virtual register definition.
754  }
755 
756  /// Return true if this instruction behaves
757  /// the same way as the generic REG_SEQUENCE instructions.
758  /// E.g., on ARM,
759  /// dX VMOVDRR rY, rZ
760  /// is equivalent to
761  /// dX = REG_SEQUENCE rY, ssub_0, rZ, ssub_1.
762  ///
763  /// Note that for the optimizers to be able to take advantage of
764  /// this property, TargetInstrInfo::getRegSequenceLikeInputs has to be
765  /// override accordingly.
768  }
769 
770  /// Return true if this instruction behaves
771  /// the same way as the generic EXTRACT_SUBREG instructions.
772  /// E.g., on ARM,
773  /// rX, rY VMOVRRD dZ
774  /// is equivalent to two EXTRACT_SUBREG:
775  /// rX = EXTRACT_SUBREG dZ, ssub_0
776  /// rY = EXTRACT_SUBREG dZ, ssub_1
777  ///
778  /// Note that for the optimizers to be able to take advantage of
779  /// this property, TargetInstrInfo::getExtractSubregLikeInputs has to be
780  /// override accordingly.
783  }
784 
785  /// Return true if this instruction behaves
786  /// the same way as the generic INSERT_SUBREG instructions.
787  /// E.g., on ARM,
788  /// dX = VSETLNi32 dY, rZ, Imm
789  /// is equivalent to a INSERT_SUBREG:
790  /// dX = INSERT_SUBREG dY, rZ, translateImmToSubIdx(Imm)
791  ///
792  /// Note that for the optimizers to be able to take advantage of
793  /// this property, TargetInstrInfo::getInsertSubregLikeInputs has to be
794  /// override accordingly.
797  }
798 
799  //===--------------------------------------------------------------------===//
800  // Side Effect Analysis
801  //===--------------------------------------------------------------------===//
802 
803  /// Return true if this instruction could possibly read memory.
804  /// Instructions with this flag set are not necessarily simple load
805  /// instructions, they may load a value and modify it, for example.
807  if (isInlineAsm()) {
808  unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
809  if (ExtraInfo & InlineAsm::Extra_MayLoad)
810  return true;
811  }
812  return hasProperty(MCID::MayLoad, Type);
813  }
814 
815  /// Return true if this instruction could possibly modify memory.
816  /// Instructions with this flag set are not necessarily simple store
817  /// instructions, they may store a modified value based on their operands, or
818  /// may not actually modify anything, for example.
820  if (isInlineAsm()) {
821  unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
822  if (ExtraInfo & InlineAsm::Extra_MayStore)
823  return true;
824  }
826  }
827 
828  /// Return true if this instruction could possibly read or modify memory.
830  return mayLoad(Type) || mayStore(Type);
831  }
832 
833  //===--------------------------------------------------------------------===//
834  // Flags that indicate whether an instruction can be modified by a method.
835  //===--------------------------------------------------------------------===//
836 
837  /// Return true if this may be a 2- or 3-address
838  /// instruction (of the form "X = op Y, Z, ..."), which produces the same
839  /// result if Y and Z are exchanged. If this flag is set, then the
840  /// TargetInstrInfo::commuteInstruction method may be used to hack on the
841  /// instruction.
842  ///
843  /// Note that this flag may be set on instructions that are only commutable
844  /// sometimes. In these cases, the call to commuteInstruction will fail.
845  /// Also note that some instructions require non-trivial modification to
846  /// commute them.
849  }
850 
851  /// Return true if this is a 2-address instruction
852  /// which can be changed into a 3-address instruction if needed. Doing this
853  /// transformation can be profitable in the register allocator, because it
854  /// means that the instruction can use a 2-address form if possible, but
855  /// degrade into a less efficient form if the source and dest register cannot
856  /// be assigned to the same register. For example, this allows the x86
857  /// backend to turn a "shl reg, 3" instruction into an LEA instruction, which
858  /// is the same speed as the shift but has bigger code size.
859  ///
860  /// If this returns true, then the target must implement the
861  /// TargetInstrInfo::convertToThreeAddress method for this instruction, which
862  /// is allowed to fail if the transformation isn't valid for this specific
863  /// instruction (e.g. shl reg, 4 on x86).
864  ///
867  }
868 
869  /// Return true if this instruction requires
870  /// custom insertion support when the DAG scheduler is inserting it into a
871  /// machine basic block. If this is true for the instruction, it basically
872  /// means that it is a pseudo instruction used at SelectionDAG time that is
873  /// expanded out into magic code by the target when MachineInstrs are formed.
874  ///
875  /// If this is true, the TargetLoweringInfo::InsertAtEndOfBasicBlock method
876  /// is used to insert this into the MachineBasicBlock.
879  }
880 
881  /// Return true if this instruction requires *adjustment*
882  /// after instruction selection by calling a target hook. For example, this
883  /// can be used to fill in ARM 's' optional operand depending on whether
884  /// the conditional flag register is used.
887  }
888 
889  /// Returns true if this instruction is a candidate for remat.
890  /// This flag is deprecated, please don't use it anymore. If this
891  /// flag is set, the isReallyTriviallyReMaterializable() method is called to
892  /// verify the instruction is really rematable.
894  // It's only possible to re-mat a bundle if all bundled instructions are
895  // re-materializable.
897  }
898 
899  /// Returns true if this instruction has the same cost (or less) than a move
900  /// instruction. This is useful during certain types of optimizations
901  /// (e.g., remat during two-address conversion or machine licm)
902  /// where we would like to remat or hoist the instruction, but not if it costs
903  /// more than moving the instruction into the appropriate register. Note, we
904  /// are not marking copies from and to the same register class with this flag.
906  // Only returns true for a bundle if all bundled instructions are cheap.
908  }
909 
910  /// Returns true if this instruction source operands
911  /// have special register allocation requirements that are not captured by the
912  /// operand register classes. e.g. ARM::STRD's two source registers must be an
913  /// even / odd pair, ARM::STM registers have to be in ascending order.
914  /// Post-register allocation passes should not attempt to change allocations
915  /// for sources of instructions with this flag.
918  }
919 
920  /// Returns true if this instruction def operands
921  /// have special register allocation requirements that are not captured by the
922  /// operand register classes. e.g. ARM::LDRD's two def registers must be an
923  /// even / odd pair, ARM::LDM registers have to be in ascending order.
924  /// Post-register allocation passes should not attempt to change allocations
925  /// for definitions of instructions with this flag.
928  }
929 
930  enum MICheckType {
931  CheckDefs, // Check all operands for equality
932  CheckKillDead, // Check all operands including kill / dead markers
933  IgnoreDefs, // Ignore all definitions
934  IgnoreVRegDefs // Ignore virtual register definitions
935  };
936 
937  /// Return true if this instruction is identical to \p Other.
938  /// Two instructions are identical if they have the same opcode and all their
939  /// operands are identical (with respect to MachineOperand::isIdenticalTo()).
940  /// Note that this means liveness related flags (dead, undef, kill) do not
941  /// affect the notion of identical.
942  bool isIdenticalTo(const MachineInstr &Other,
943  MICheckType Check = CheckDefs) const;
944 
945  /// Unlink 'this' from the containing basic block, and return it without
946  /// deleting it.
947  ///
948  /// This function can not be used on bundled instructions, use
949  /// removeFromBundle() to remove individual instructions from a bundle.
951 
952  /// Unlink this instruction from its basic block and return it without
953  /// deleting it.
954  ///
955  /// If the instruction is part of a bundle, the other instructions in the
956  /// bundle remain bundled.
958 
959  /// Unlink 'this' from the containing basic block and delete it.
960  ///
961  /// If this instruction is the header of a bundle, the whole bundle is erased.
962  /// This function can not be used for instructions inside a bundle, use
963  /// eraseFromBundle() to erase individual bundled instructions.
964  void eraseFromParent();
965 
966  /// Unlink 'this' from the containing basic block and delete it.
967  ///
968  /// For all definitions mark their uses in DBG_VALUE nodes
969  /// as undefined. Otherwise like eraseFromParent().
971 
972  /// Unlink 'this' form its basic block and delete it.
973  ///
974  /// If the instruction is part of a bundle, the other instructions in the
975  /// bundle remain bundled.
976  void eraseFromBundle();
977 
978  bool isEHLabel() const { return getOpcode() == TargetOpcode::EH_LABEL; }
979  bool isGCLabel() const { return getOpcode() == TargetOpcode::GC_LABEL; }
980  bool isAnnotationLabel() const {
982  }
983 
984  /// Returns true if the MachineInstr represents a label.
985  bool isLabel() const {
986  return isEHLabel() || isGCLabel() || isAnnotationLabel();
987  }
988 
989  bool isCFIInstruction() const {
990  return getOpcode() == TargetOpcode::CFI_INSTRUCTION;
991  }
992 
993  // True if the instruction represents a position in the function.
994  bool isPosition() const { return isLabel() || isCFIInstruction(); }
995 
996  bool isDebugValue() const { return getOpcode() == TargetOpcode::DBG_VALUE; }
997  bool isDebugLabel() const { return getOpcode() == TargetOpcode::DBG_LABEL; }
998  bool isDebugInstr() const { return isDebugValue() || isDebugLabel(); }
999 
1000  /// A DBG_VALUE is indirect iff the first operand is a register and
1001  /// the second operand is an immediate.
1002  bool isIndirectDebugValue() const {
1003  return isDebugValue()
1004  && getOperand(0).isReg()
1005  && getOperand(1).isImm();
1006  }
1007 
1008  bool isPHI() const {
1009  return getOpcode() == TargetOpcode::PHI ||
1010  getOpcode() == TargetOpcode::G_PHI;
1011  }
1012  bool isKill() const { return getOpcode() == TargetOpcode::KILL; }
1013  bool isImplicitDef() const { return getOpcode()==TargetOpcode::IMPLICIT_DEF; }
1014  bool isInlineAsm() const {
1015  return getOpcode() == TargetOpcode::INLINEASM ||
1017  }
1018 
1019  bool isMSInlineAsm() const {
1021  }
1022 
1023  bool isStackAligningInlineAsm() const;
1025 
1026  bool isInsertSubreg() const {
1027  return getOpcode() == TargetOpcode::INSERT_SUBREG;
1028  }
1029 
1030  bool isSubregToReg() const {
1031  return getOpcode() == TargetOpcode::SUBREG_TO_REG;
1032  }
1033 
1034  bool isRegSequence() const {
1035  return getOpcode() == TargetOpcode::REG_SEQUENCE;
1036  }
1037 
1038  bool isBundle() const {
1039  return getOpcode() == TargetOpcode::BUNDLE;
1040  }
1041 
1042  bool isCopy() const {
1043  return getOpcode() == TargetOpcode::COPY;
1044  }
1045 
1046  bool isFullCopy() const {
1047  return isCopy() && !getOperand(0).getSubReg() && !getOperand(1).getSubReg();
1048  }
1049 
1050  bool isExtractSubreg() const {
1051  return getOpcode() == TargetOpcode::EXTRACT_SUBREG;
1052  }
1053 
1054  /// Return true if the instruction behaves like a copy.
1055  /// This does not include native copy instructions.
1056  bool isCopyLike() const {
1057  return isCopy() || isSubregToReg();
1058  }
1059 
1060  /// Return true is the instruction is an identity copy.
1061  bool isIdentityCopy() const {
1062  return isCopy() && getOperand(0).getReg() == getOperand(1).getReg() &&
1064  }
1065 
1066  /// Return true if this instruction doesn't produce any output in the form of
1067  /// executable instructions.
1068  bool isMetaInstruction() const {
1069  switch (getOpcode()) {
1070  default:
1071  return false;
1072  case TargetOpcode::IMPLICIT_DEF:
1073  case TargetOpcode::KILL:
1074  case TargetOpcode::CFI_INSTRUCTION:
1076  case TargetOpcode::GC_LABEL:
1077  case TargetOpcode::DBG_VALUE:
1078  case TargetOpcode::DBG_LABEL:
1081  return true;
1082  }
1083  }
1084 
1085  /// Return true if this is a transient instruction that is either very likely
1086  /// to be eliminated during register allocation (such as copy-like
1087  /// instructions), or if this instruction doesn't have an execution-time cost.
1088  bool isTransient() const {
1089  switch (getOpcode()) {
1090  default:
1091  return isMetaInstruction();
1092  // Copy-like instructions are usually eliminated during register allocation.
1093  case TargetOpcode::PHI:
1094  case TargetOpcode::G_PHI:
1095  case TargetOpcode::COPY:
1096  case TargetOpcode::INSERT_SUBREG:
1097  case TargetOpcode::SUBREG_TO_REG:
1098  case TargetOpcode::REG_SEQUENCE:
1099  return true;
1100  }
1101  }
1102 
1103  /// Return the number of instructions inside the MI bundle, excluding the
1104  /// bundle header.
1105  ///
1106  /// This is the number of instructions that MachineBasicBlock::iterator
1107  /// skips, 0 for unbundled instructions.
1108  unsigned getBundleSize() const;
1109 
1110  /// Return true if the MachineInstr reads the specified register.
1111  /// If TargetRegisterInfo is passed, then it also checks if there
1112  /// is a read of a super-register.
1113  /// This does not count partial redefines of virtual registers as reads:
1114  /// %reg1024:6 = OP.
1115  bool readsRegister(unsigned Reg,
1116  const TargetRegisterInfo *TRI = nullptr) const {
1117  return findRegisterUseOperandIdx(Reg, false, TRI) != -1;
1118  }
1119 
1120  /// Return true if the MachineInstr reads the specified virtual register.
1121  /// Take into account that a partial define is a
1122  /// read-modify-write operation.
1123  bool readsVirtualRegister(unsigned Reg) const {
1124  return readsWritesVirtualRegister(Reg).first;
1125  }
1126 
1127  /// Return a pair of bools (reads, writes) indicating if this instruction
1128  /// reads or writes Reg. This also considers partial defines.
1129  /// If Ops is not null, all operand indices for Reg are added.
1130  std::pair<bool,bool> readsWritesVirtualRegister(unsigned Reg,
1131  SmallVectorImpl<unsigned> *Ops = nullptr) const;
1132 
1133  /// Return true if the MachineInstr kills the specified register.
1134  /// If TargetRegisterInfo is passed, then it also checks if there is
1135  /// a kill of a super-register.
1136  bool killsRegister(unsigned Reg,
1137  const TargetRegisterInfo *TRI = nullptr) const {
1138  return findRegisterUseOperandIdx(Reg, true, TRI) != -1;
1139  }
1140 
1141  /// Return true if the MachineInstr fully defines the specified register.
1142  /// If TargetRegisterInfo is passed, then it also checks
1143  /// if there is a def of a super-register.
1144  /// NOTE: It's ignoring subreg indices on virtual registers.
1145  bool definesRegister(unsigned Reg,
1146  const TargetRegisterInfo *TRI = nullptr) const {
1147  return findRegisterDefOperandIdx(Reg, false, false, TRI) != -1;
1148  }
1149 
1150  /// Return true if the MachineInstr modifies (fully define or partially
1151  /// define) the specified register.
1152  /// NOTE: It's ignoring subreg indices on virtual registers.
1153  bool modifiesRegister(unsigned Reg, const TargetRegisterInfo *TRI) const {
1154  return findRegisterDefOperandIdx(Reg, false, true, TRI) != -1;
1155  }
1156 
1157  /// Returns true if the register is dead in this machine instruction.
1158  /// If TargetRegisterInfo is passed, then it also checks
1159  /// if there is a dead def of a super-register.
1160  bool registerDefIsDead(unsigned Reg,
1161  const TargetRegisterInfo *TRI = nullptr) const {
1162  return findRegisterDefOperandIdx(Reg, true, false, TRI) != -1;
1163  }
1164 
1165  /// Returns true if the MachineInstr has an implicit-use operand of exactly
1166  /// the given register (not considering sub/super-registers).
1167  bool hasRegisterImplicitUseOperand(unsigned Reg) const;
1168 
1169  /// Returns the operand index that is a use of the specific register or -1
1170  /// if it is not found. It further tightens the search criteria to a use
1171  /// that kills the register if isKill is true.
1172  int findRegisterUseOperandIdx(unsigned Reg, bool isKill = false,
1173  const TargetRegisterInfo *TRI = nullptr) const;
1174 
1175  /// Wrapper for findRegisterUseOperandIdx, it returns
1176  /// a pointer to the MachineOperand rather than an index.
1177  MachineOperand *findRegisterUseOperand(unsigned Reg, bool isKill = false,
1178  const TargetRegisterInfo *TRI = nullptr) {
1179  int Idx = findRegisterUseOperandIdx(Reg, isKill, TRI);
1180  return (Idx == -1) ? nullptr : &getOperand(Idx);
1181  }
1182 
1184  unsigned Reg, bool isKill = false,
1185  const TargetRegisterInfo *TRI = nullptr) const {
1186  return const_cast<MachineInstr *>(this)->
1188  }
1189 
1190  /// Returns the operand index that is a def of the specified register or
1191  /// -1 if it is not found. If isDead is true, defs that are not dead are
1192  /// skipped. If Overlap is true, then it also looks for defs that merely
1193  /// overlap the specified register. If TargetRegisterInfo is non-null,
1194  /// then it also checks if there is a def of a super-register.
1195  /// This may also return a register mask operand when Overlap is true.
1196  int findRegisterDefOperandIdx(unsigned Reg,
1197  bool isDead = false, bool Overlap = false,
1198  const TargetRegisterInfo *TRI = nullptr) const;
1199 
1200  /// Wrapper for findRegisterDefOperandIdx, it returns
1201  /// a pointer to the MachineOperand rather than an index.
1202  MachineOperand *
1203  findRegisterDefOperand(unsigned Reg, bool isDead = false,
1204  bool Overlap = false,
1205  const TargetRegisterInfo *TRI = nullptr) {
1206  int Idx = findRegisterDefOperandIdx(Reg, isDead, Overlap, TRI);
1207  return (Idx == -1) ? nullptr : &getOperand(Idx);
1208  }
1209 
1210  const MachineOperand *
1211  findRegisterDefOperand(unsigned Reg, bool isDead = false,
1212  bool Overlap = false,
1213  const TargetRegisterInfo *TRI = nullptr) const {
1214  return const_cast<MachineInstr *>(this)->findRegisterDefOperand(
1215  Reg, isDead, Overlap, TRI);
1216  }
1217 
1218  /// Find the index of the first operand in the
1219  /// operand list that is used to represent the predicate. It returns -1 if
1220  /// none is found.
1221  int findFirstPredOperandIdx() const;
1222 
1223  /// Find the index of the flag word operand that
1224  /// corresponds to operand OpIdx on an inline asm instruction. Returns -1 if
1225  /// getOperand(OpIdx) does not belong to an inline asm operand group.
1226  ///
1227  /// If GroupNo is not NULL, it will receive the number of the operand group
1228  /// containing OpIdx.
1229  ///
1230  /// The flag operand is an immediate that can be decoded with methods like
1231  /// InlineAsm::hasRegClassConstraint().
1232  int findInlineAsmFlagIdx(unsigned OpIdx, unsigned *GroupNo = nullptr) const;
1233 
1234  /// Compute the static register class constraint for operand OpIdx.
1235  /// For normal instructions, this is derived from the MCInstrDesc.
1236  /// For inline assembly it is derived from the flag words.
1237  ///
1238  /// Returns NULL if the static register class constraint cannot be
1239  /// determined.
1240  const TargetRegisterClass*
1241  getRegClassConstraint(unsigned OpIdx,
1242  const TargetInstrInfo *TII,
1243  const TargetRegisterInfo *TRI) const;
1244 
1245  /// Applies the constraints (def/use) implied by this MI on \p Reg to
1246  /// the given \p CurRC.
1247  /// If \p ExploreBundle is set and MI is part of a bundle, all the
1248  /// instructions inside the bundle will be taken into account. In other words,
1249  /// this method accumulates all the constraints of the operand of this MI and
1250  /// the related bundle if MI is a bundle or inside a bundle.
1251  ///
1252  /// Returns the register class that satisfies both \p CurRC and the
1253  /// constraints set by MI. Returns NULL if such a register class does not
1254  /// exist.
1255  ///
1256  /// \pre CurRC must not be NULL.
1258  unsigned Reg, const TargetRegisterClass *CurRC,
1259  const TargetInstrInfo *TII, const TargetRegisterInfo *TRI,
1260  bool ExploreBundle = false) const;
1261 
1262  /// Applies the constraints (def/use) implied by the \p OpIdx operand
1263  /// to the given \p CurRC.
1264  ///
1265  /// Returns the register class that satisfies both \p CurRC and the
1266  /// constraints set by \p OpIdx MI. Returns NULL if such a register class
1267  /// does not exist.
1268  ///
1269  /// \pre CurRC must not be NULL.
1270  /// \pre The operand at \p OpIdx must be a register.
1271  const TargetRegisterClass *
1272  getRegClassConstraintEffect(unsigned OpIdx, const TargetRegisterClass *CurRC,
1273  const TargetInstrInfo *TII,
1274  const TargetRegisterInfo *TRI) const;
1275 
1276  /// Add a tie between the register operands at DefIdx and UseIdx.
1277  /// The tie will cause the register allocator to ensure that the two
1278  /// operands are assigned the same physical register.
1279  ///
1280  /// Tied operands are managed automatically for explicit operands in the
1281  /// MCInstrDesc. This method is for exceptional cases like inline asm.
1282  void tieOperands(unsigned DefIdx, unsigned UseIdx);
1283 
1284  /// Given the index of a tied register operand, find the
1285  /// operand it is tied to. Defs are tied to uses and vice versa. Returns the
1286  /// index of the tied operand which must exist.
1287  unsigned findTiedOperandIdx(unsigned OpIdx) const;
1288 
1289  /// Given the index of a register def operand,
1290  /// check if the register def is tied to a source operand, due to either
1291  /// two-address elimination or inline assembly constraints. Returns the
1292  /// first tied use operand index by reference if UseOpIdx is not null.
1293  bool isRegTiedToUseOperand(unsigned DefOpIdx,
1294  unsigned *UseOpIdx = nullptr) const {
1295  const MachineOperand &MO = getOperand(DefOpIdx);
1296  if (!MO.isReg() || !MO.isDef() || !MO.isTied())
1297  return false;
1298  if (UseOpIdx)
1299  *UseOpIdx = findTiedOperandIdx(DefOpIdx);
1300  return true;
1301  }
1302 
1303  /// Return true if the use operand of the specified index is tied to a def
1304  /// operand. It also returns the def operand index by reference if DefOpIdx
1305  /// is not null.
1306  bool isRegTiedToDefOperand(unsigned UseOpIdx,
1307  unsigned *DefOpIdx = nullptr) const {
1308  const MachineOperand &MO = getOperand(UseOpIdx);
1309  if (!MO.isReg() || !MO.isUse() || !MO.isTied())
1310  return false;
1311  if (DefOpIdx)
1312  *DefOpIdx = findTiedOperandIdx(UseOpIdx);
1313  return true;
1314  }
1315 
1316  /// Clears kill flags on all operands.
1317  void clearKillInfo();
1318 
1319  /// Replace all occurrences of FromReg with ToReg:SubIdx,
1320  /// properly composing subreg indices where necessary.
1321  void substituteRegister(unsigned FromReg, unsigned ToReg, unsigned SubIdx,
1322  const TargetRegisterInfo &RegInfo);
1323 
1324  /// We have determined MI kills a register. Look for the
1325  /// operand that uses it and mark it as IsKill. If AddIfNotFound is true,
1326  /// add a implicit operand if it's not found. Returns true if the operand
1327  /// exists / is added.
1328  bool addRegisterKilled(unsigned IncomingReg,
1329  const TargetRegisterInfo *RegInfo,
1330  bool AddIfNotFound = false);
1331 
1332  /// Clear all kill flags affecting Reg. If RegInfo is provided, this includes
1333  /// all aliasing registers.
1334  void clearRegisterKills(unsigned Reg, const TargetRegisterInfo *RegInfo);
1335 
1336  /// We have determined MI defined a register without a use.
1337  /// Look for the operand that defines it and mark it as IsDead. If
1338  /// AddIfNotFound is true, add a implicit operand if it's not found. Returns
1339  /// true if the operand exists / is added.
1340  bool addRegisterDead(unsigned Reg, const TargetRegisterInfo *RegInfo,
1341  bool AddIfNotFound = false);
1342 
1343  /// Clear all dead flags on operands defining register @p Reg.
1344  void clearRegisterDeads(unsigned Reg);
1345 
1346  /// Mark all subregister defs of register @p Reg with the undef flag.
1347  /// This function is used when we determined to have a subregister def in an
1348  /// otherwise undefined super register.
1349  void setRegisterDefReadUndef(unsigned Reg, bool IsUndef = true);
1350 
1351  /// We have determined MI defines a register. Make sure there is an operand
1352  /// defining Reg.
1353  void addRegisterDefined(unsigned Reg,
1354  const TargetRegisterInfo *RegInfo = nullptr);
1355 
1356  /// Mark every physreg used by this instruction as
1357  /// dead except those in the UsedRegs list.
1358  ///
1359  /// On instructions with register mask operands, also add implicit-def
1360  /// operands for all registers in UsedRegs.
1362  const TargetRegisterInfo &TRI);
1363 
1364  /// Return true if it is safe to move this instruction. If
1365  /// SawStore is set to true, it means that there is a store (or call) between
1366  /// the instruction's location and its intended destination.
1367  bool isSafeToMove(AliasAnalysis *AA, bool &SawStore) const;
1368 
1369  /// Returns true if this instruction's memory access aliases the memory
1370  /// access of Other.
1371  //
1372  /// Assumes any physical registers used to compute addresses
1373  /// have the same value for both instructions. Returns false if neither
1374  /// instruction writes to memory.
1375  ///
1376  /// @param AA Optional alias analysis, used to compare memory operands.
1377  /// @param Other MachineInstr to check aliasing against.
1378  /// @param UseTBAA Whether to pass TBAA information to alias analysis.
1379  bool mayAlias(AliasAnalysis *AA, MachineInstr &Other, bool UseTBAA);
1380 
1381  /// Return true if this instruction may have an ordered
1382  /// or volatile memory reference, or if the information describing the memory
1383  /// reference is not available. Return false if it is known to have no
1384  /// ordered or volatile memory references.
1385  bool hasOrderedMemoryRef() const;
1386 
1387  /// Return true if this load instruction never traps and points to a memory
1388  /// location whose value doesn't change during the execution of this function.
1389  ///
1390  /// Examples include loading a value from the constant pool or from the
1391  /// argument area of a function (if it does not change). If the instruction
1392  /// does multiple loads, this returns true only if all of the loads are
1393  /// dereferenceable and invariant.
1395 
1396  /// If the specified instruction is a PHI that always merges together the
1397  /// same virtual register, return the register, otherwise return 0.
1398  unsigned isConstantValuePHI() const;
1399 
1400  /// Return true if this instruction has side effects that are not modeled
1401  /// by mayLoad / mayStore, etc.
1402  /// For all instructions, the property is encoded in MCInstrDesc::Flags
1403  /// (see MCInstrDesc::hasUnmodeledSideEffects(). The only exception is
1404  /// INLINEASM instruction, in which case the side effect property is encoded
1405  /// in one of its operands (see InlineAsm::Extra_HasSideEffect).
1406  ///
1407  bool hasUnmodeledSideEffects() const;
1408 
1409  /// Returns true if it is illegal to fold a load across this instruction.
1410  bool isLoadFoldBarrier() const;
1411 
1412  /// Return true if all the defs of this instruction are dead.
1413  bool allDefsAreDead() const;
1414 
1415  /// Return a valid size if the instruction is a spill instruction.
1417 
1418  /// Return a valid size if the instruction is a folded spill instruction.
1420 
1421  /// Return a valid size if the instruction is a restore instruction.
1423 
1424  /// Return a valid size if the instruction is a folded restore instruction.
1426  getFoldedRestoreSize(const TargetInstrInfo *TII) const;
1427 
1428  /// Copy implicit register operands from specified
1429  /// instruction to this instruction.
1430  void copyImplicitOps(MachineFunction &MF, const MachineInstr &MI);
1431 
1432  /// Debugging support
1433  /// @{
1434  /// Determine the generic type to be printed (if needed) on uses and defs.
1435  LLT getTypeToPrint(unsigned OpIdx, SmallBitVector &PrintedTypes,
1436  const MachineRegisterInfo &MRI) const;
1437 
1438  /// Return true when an instruction has tied register that can't be determined
1439  /// by the instruction's descriptor. This is useful for MIR printing, to
1440  /// determine whether we need to print the ties or not.
1441  bool hasComplexRegisterTies() const;
1442 
1443  /// Print this MI to \p OS.
1444  /// Don't print information that can be inferred from other instructions if
1445  /// \p IsStandalone is false. It is usually true when only a fragment of the
1446  /// function is printed.
1447  /// Only print the defs and the opcode if \p SkipOpers is true.
1448  /// Otherwise, also print operands if \p SkipDebugLoc is true.
1449  /// Otherwise, also print the debug loc, with a terminating newline.
1450  /// \p TII is used to print the opcode name. If it's not present, but the
1451  /// MI is in a function, the opcode will be printed using the function's TII.
1452  void print(raw_ostream &OS, bool IsStandalone = true, bool SkipOpers = false,
1453  bool SkipDebugLoc = false, bool AddNewLine = true,
1454  const TargetInstrInfo *TII = nullptr) const;
1455  void print(raw_ostream &OS, ModuleSlotTracker &MST, bool IsStandalone = true,
1456  bool SkipOpers = false, bool SkipDebugLoc = false,
1457  bool AddNewLine = true,
1458  const TargetInstrInfo *TII = nullptr) const;
1459  void dump() const;
1460  /// @}
1461 
1462  //===--------------------------------------------------------------------===//
1463  // Accessors used to build up machine instructions.
1464 
1465  /// Add the specified operand to the instruction. If it is an implicit
1466  /// operand, it is added to the end of the operand list. If it is an
1467  /// explicit operand it is added at the end of the explicit operand list
1468  /// (before the first implicit operand).
1469  ///
1470  /// MF must be the machine function that was used to allocate this
1471  /// instruction.
1472  ///
1473  /// MachineInstrBuilder provides a more convenient interface for creating
1474  /// instructions and adding operands.
1475  void addOperand(MachineFunction &MF, const MachineOperand &Op);
1476 
1477  /// Add an operand without providing an MF reference. This only works for
1478  /// instructions that are inserted in a basic block.
1479  ///
1480  /// MachineInstrBuilder and the two-argument addOperand(MF, MO) should be
1481  /// preferred.
1482  void addOperand(const MachineOperand &Op);
1483 
1484  /// Replace the instruction descriptor (thus opcode) of
1485  /// the current instruction with a new one.
1486  void setDesc(const MCInstrDesc &tid) { MCID = &tid; }
1487 
1488  /// Replace current source information with new such.
1489  /// Avoid using this, the constructor argument is preferable.
1491  debugLoc = std::move(dl);
1492  assert(debugLoc.hasTrivialDestructor() && "Expected trivial destructor");
1493  }
1494 
1495  /// Erase an operand from an instruction, leaving it with one
1496  /// fewer operand than it started with.
1497  void RemoveOperand(unsigned OpNo);
1498 
1499  /// Clear this MachineInstr's memory reference descriptor list. This resets
1500  /// the memrefs to their most conservative state. This should be used only
1501  /// as a last resort since it greatly pessimizes our knowledge of the memory
1502  /// access performed by the instruction.
1503  void dropMemRefs(MachineFunction &MF);
1504 
1505  /// Assign this MachineInstr's memory reference descriptor list.
1506  ///
1507  /// Unlike other methods, this *will* allocate them into a new array
1508  /// associated with the provided `MachineFunction`.
1510 
1511  /// Add a MachineMemOperand to the machine instruction.
1512  /// This function should be used only occasionally. The setMemRefs function
1513  /// is the primary method for setting up a MachineInstr's MemRefs list.
1515 
1516  /// Clone another MachineInstr's memory reference descriptor list and replace
1517  /// ours with it.
1518  ///
1519  /// Note that `*this` may be the incoming MI!
1520  ///
1521  /// Prefer this API whenever possible as it can avoid allocations in common
1522  /// cases.
1523  void cloneMemRefs(MachineFunction &MF, const MachineInstr &MI);
1524 
1525  /// Clone the merge of multiple MachineInstrs' memory reference descriptors
1526  /// list and replace ours with it.
1527  ///
1528  /// Note that `*this` may be one of the incoming MIs!
1529  ///
1530  /// Prefer this API whenever possible as it can avoid allocations in common
1531  /// cases.
1534 
1535  /// Set a symbol that will be emitted just prior to the instruction itself.
1536  ///
1537  /// Setting this to a null pointer will remove any such symbol.
1538  ///
1539  /// FIXME: This is not fully implemented yet.
1541 
1542  /// Set a symbol that will be emitted just after the instruction itself.
1543  ///
1544  /// Setting this to a null pointer will remove any such symbol.
1545  ///
1546  /// FIXME: This is not fully implemented yet.
1547  void setPostInstrSymbol(MachineFunction &MF, MCSymbol *Symbol);
1548 
1549  /// Return the MIFlags which represent both MachineInstrs. This
1550  /// should be used when merging two MachineInstrs into one. This routine does
1551  /// not modify the MIFlags of this MachineInstr.
1552  uint16_t mergeFlagsWith(const MachineInstr& Other) const;
1553 
1554  static uint16_t copyFlagsFromInstruction(const Instruction &I);
1555 
1556  /// Copy all flags to MachineInst MIFlags
1557  void copyIRFlags(const Instruction &I);
1558 
1559  /// Break any tie involving OpIdx.
1560  void untieRegOperand(unsigned OpIdx) {
1561  MachineOperand &MO = getOperand(OpIdx);
1562  if (MO.isReg() && MO.isTied()) {
1563  getOperand(findTiedOperandIdx(OpIdx)).TiedTo = 0;
1564  MO.TiedTo = 0;
1565  }
1566  }
1567 
1568  /// Add all implicit def and use operands to this instruction.
1570 
1571  /// Scan instructions following MI and collect any matching DBG_VALUEs.
1573 
1574  /// Find all DBG_VALUEs immediately following this instruction that point
1575  /// to a register def in this instruction and point them to \p Reg instead.
1576  void changeDebugValuesDefReg(unsigned Reg);
1577 
1578 private:
1579  /// If this instruction is embedded into a MachineFunction, return the
1580  /// MachineRegisterInfo object for the current function, otherwise
1581  /// return null.
1582  MachineRegisterInfo *getRegInfo();
1583 
1584  /// Unlink all of the register operands in this instruction from their
1585  /// respective use lists. This requires that the operands already be on their
1586  /// use lists.
1587  void RemoveRegOperandsFromUseLists(MachineRegisterInfo&);
1588 
1589  /// Add all of the register operands in this instruction from their
1590  /// respective use lists. This requires that the operands not be on their
1591  /// use lists yet.
1592  void AddRegOperandsToUseLists(MachineRegisterInfo&);
1593 
1594  /// Slow path for hasProperty when we're dealing with a bundle.
1595  bool hasPropertyInBundle(uint64_t Mask, QueryType Type) const;
1596 
1597  /// Implements the logic of getRegClassConstraintEffectForVReg for the
1598  /// this MI and the given operand index \p OpIdx.
1599  /// If the related operand does not constrained Reg, this returns CurRC.
1600  const TargetRegisterClass *getRegClassConstraintEffectForVRegImpl(
1601  unsigned OpIdx, unsigned Reg, const TargetRegisterClass *CurRC,
1602  const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const;
1603 };
1604 
1605 /// Special DenseMapInfo traits to compare MachineInstr* by *value* of the
1606 /// instruction rather than by pointer value.
1607 /// The hashing and equality testing functions ignore definitions so this is
1608 /// useful for CSE, etc.
1610  static inline MachineInstr *getEmptyKey() {
1611  return nullptr;
1612  }
1613 
1614  static inline MachineInstr *getTombstoneKey() {
1615  return reinterpret_cast<MachineInstr*>(-1);
1616  }
1617 
1618  static unsigned getHashValue(const MachineInstr* const &MI);
1619 
1620  static bool isEqual(const MachineInstr* const &LHS,
1621  const MachineInstr* const &RHS) {
1622  if (RHS == getEmptyKey() || RHS == getTombstoneKey() ||
1623  LHS == getEmptyKey() || LHS == getTombstoneKey())
1624  return LHS == RHS;
1625  return LHS->isIdenticalTo(*RHS, MachineInstr::IgnoreVRegDefs);
1626  }
1627 };
1628 
1629 //===----------------------------------------------------------------------===//
1630 // Debugging Support
1631 
1633  MI.print(OS);
1634  return OS;
1635 }
1636 
1637 } // end namespace llvm
1638 
1639 #endif // LLVM_CODEGEN_MACHINEINSTR_H
ANNOTATION_LABEL - Represents a mid basic block label used by annotations.
Definition: ISDOpcodes.h:682
static bool Check(DecodeStatus &Out, DecodeStatus In)
void bundleWithPred()
Bundle this instruction with its predecessor.
LLT getTypeToPrint(unsigned OpIdx, SmallBitVector &PrintedTypes, const MachineRegisterInfo &MRI) const
Debugging supportDetermine the generic type to be printed (if needed) on uses and defs...
MachineOperand * findRegisterDefOperand(unsigned Reg, bool isDead=false, bool Overlap=false, const TargetRegisterInfo *TRI=nullptr)
Wrapper for findRegisterDefOperandIdx, it returns a pointer to the MachineOperand rather than an inde...
const_iterator end(StringRef path)
Get end iterator over path.
Definition: Path.cpp:258
mop_iterator operands_end()
Definition: MachineInstr.h:453
bool hasRegisterImplicitUseOperand(unsigned Reg) const
Returns true if the MachineInstr has an implicit-use operand of exactly the given register (not consi...
bool isDebugLabel() const
Definition: MachineInstr.h:997
bool hasPostISelHook(QueryType Type=IgnoreBundle) const
Return true if this instruction requires adjustment after instruction selection by calling a target h...
Definition: MachineInstr.h:885
bool modifiesRegister(unsigned Reg, const TargetRegisterInfo *TRI) const
Return true if the MachineInstr modifies (fully define or partially define) the specified register...
void collectDebugValues(SmallVectorImpl< MachineInstr *> &DbgValues)
Scan instructions following MI and collect any matching DBG_VALUEs.
const_mop_iterator operands_end() const
Definition: MachineInstr.h:456
bool isLabel() const
Returns true if the MachineInstr represents a label.
Definition: MachineInstr.h:985
int findFirstPredOperandIdx() const
Find the index of the first operand in the operand list that is used to represent the predicate...
bool isCall(QueryType Type=AnyInBundle) const
Definition: MachineInstr.h:632
void emitError(StringRef Msg) const
Emit an error referring to the source location of this instruction.
This is a &#39;bitvector&#39; (really, a variable-sized bit array), optimized for the case when the array is ...
unsigned getNumImplicitDefs() const
Return the number of implicit defs this instruct has.
Definition: MCInstrDesc.h:548
const MachineFunction * getMF() const
Return the function that contains the basic block that this instruction belongs to.
This class represents lattice values for constants.
Definition: AllocatorList.h:23
iterator_range< mop_iterator > uses()
Returns a range that includes all operands that are register uses.
Definition: MachineInstr.h:491
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:41
A compile time pair of an integer tag and the pointer-like type which it indexes within a sum type...
iterator_range< mop_iterator > explicit_operands()
Definition: MachineInstr.h:464
bool hasExtraDefRegAllocReq(QueryType Type=AnyInBundle) const
Returns true if this instruction def operands have special register allocation requirements that are ...
Definition: MachineInstr.h:926
iterator begin() const
Definition: ArrayRef.h:136
void setRegisterDefReadUndef(unsigned Reg, bool IsUndef=true)
Mark all subregister defs of register Reg with the undef flag.
bool addRegisterDead(unsigned Reg, const TargetRegisterInfo *RegInfo, bool AddIfNotFound=false)
We have determined MI defined a register without a use.
bool isCFIInstruction() const
Definition: MachineInstr.h:989
bool isBundledWithPred() const
Return true if this instruction is part of a bundle, and it is not the first instruction in the bundl...
Definition: MachineInstr.h:361
bool isExtractSubregLike(QueryType Type=IgnoreBundle) const
Return true if this instruction behaves the same way as the generic EXTRACT_SUBREG instructions...
Definition: MachineInstr.h:781
bool isSubregToReg() const
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:382
This provides a very simple, boring adaptor for a begin and end iterator into a range type...
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:163
unsigned getReg() const
getReg - Returns the register number.
unsigned getOperandNo(const_mop_iterator I) const
Returns the number of the operand iterator I points to.
Definition: MachineInstr.h:508
MachineOperand * findRegisterUseOperand(unsigned Reg, bool isKill=false, const TargetRegisterInfo *TRI=nullptr)
Wrapper for findRegisterUseOperandIdx, it returns a pointer to the MachineOperand rather than an inde...
unsigned Reg
bool hasDelaySlot(QueryType Type=AnyInBundle) const
Returns true if the specified instruction has a delay slot which must be filled by the code generator...
Definition: MachineInstr.h:740
unsigned getSubReg() const
static bool isEqual(const MachineInstr *const &LHS, const MachineInstr *const &RHS)
bool isInlineAsm() const
bool isPredicable(QueryType Type=AllInBundle) const
Return true if this instruction has a predicate operand that controls execution.
Definition: MachineInstr.h:686
bool isAnnotationLabel() const
Definition: MachineInstr.h:980
MachineInstr & operator=(const MachineInstr &)=delete
bool isRegSequence() const
bool mayLoadOrStore(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read or modify memory.
Definition: MachineInstr.h:829
Template traits for intrusive list.
Definition: ilist.h:89
void clearAsmPrinterFlag(CommentFlag Flag)
Clear specific AsmPrinter flags.
Definition: MachineInstr.h:284
Recycle small arrays allocated from a BumpPtrAllocator.
Definition: ArrayRecycler.h:28
bool isTransient() const
Return true if this is a transient instruction that is either very likely to be eliminated during reg...
uint16_t mergeFlagsWith(const MachineInstr &Other) const
Return the MIFlags which represent both MachineInstrs.
unsigned const TargetRegisterInfo * TRI
A debug info location.
Definition: DebugLoc.h:33
Manage lifetime of a slot tracker for printing IR.
MachineOperand & getOperand(unsigned i)
Definition: MachineInstr.h:417
bool isMetaInstruction() const
Return true if this instruction doesn&#39;t produce any output in the form of executable instructions...
iterator_range< mop_iterator > operands()
Definition: MachineInstr.h:458
bool isCopyLike() const
Return true if the instruction behaves like a copy.
bool isPHI() const
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
void setPhysRegsDeadExcept(ArrayRef< unsigned > UsedRegs, const TargetRegisterInfo &TRI)
Mark every physreg used by this instruction as dead except those in the UsedRegs list.
Special DenseMapInfo traits to compare MachineInstr* by value of the instruction rather than by point...
bool isMoveImmediate(QueryType Type=IgnoreBundle) const
Return true if this instruction is a move immediate (including conditional moves) instruction...
Definition: MachineInstr.h:699
bool isBitcast(QueryType Type=IgnoreBundle) const
Return true if this instruction is a bitcast instruction.
Definition: MachineInstr.h:710
void clearKillInfo()
Clears kill flags on all operands.
A description of a memory reference used in the backend.
const HexagonInstrInfo * TII
ArrayRef< T > makeArrayRef(const T &OneElt)
Construct an ArrayRef from a single element.
Definition: ArrayRef.h:450
const TargetRegisterClass * getRegClassConstraint(unsigned OpIdx, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const
Compute the static register class constraint for operand OpIdx.
unsigned getNumOperands() const
Retuns the total number of operands.
Definition: MachineInstr.h:411
bool isBundledWithSucc() const
Return true if this instruction is part of a bundle, and it is not the last instruction in the bundle...
Definition: MachineInstr.h:365
iterator_range< const_mop_iterator > defs() const
Returns a range over all explicit operands that are register definitions.
Definition: MachineInstr.h:485
void eraseFromParent()
Unlink &#39;this&#39; from the containing basic block and delete it.
bool isTerminator(QueryType Type=AnyInBundle) const
Returns true if this instruction part of the terminator for a basic block.
Definition: MachineInstr.h:648
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:408
void bundleWithSucc()
Bundle this instruction with its successor.
const TargetRegisterClass * getRegClassConstraintEffect(unsigned OpIdx, const TargetRegisterClass *CurRC, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const
Applies the constraints (def/use) implied by the OpIdx operand to the given CurRC.
ELFYAML::ELF_STO Other
Definition: ELFYAML.cpp:809
INLINEASM - Represents an inline asm block.
Definition: ISDOpcodes.h:668
void eraseFromParentAndMarkDBGValuesForRemoval()
Unlink &#39;this&#39; from the containing basic block and delete it.
Optional< unsigned > getFoldedRestoreSize(const TargetInstrInfo *TII) const
Return a valid size if the instruction is a folded restore instruction.
const_mop_iterator operands_begin() const
Definition: MachineInstr.h:455
void unbundleFromPred()
Break bundle above this instruction.
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
Definition: MachineInstr.h:405
bool isIndirectBranch(QueryType Type=AnyInBundle) const
Return true if this is an indirect branch, such as a branch through a register.
Definition: MachineInstr.h:662
void copyImplicitOps(MachineFunction &MF, const MachineInstr &MI)
Copy implicit register operands from specified instruction to this instruction.
bool isEHScopeReturn(QueryType Type=AnyInBundle) const
Return true if this is an instruction that marks the end of an EH scope, i.e., a catchpad or a cleanu...
Definition: MachineInstr.h:628
bool isFullCopy() const
bool isBundle() const
bool isIdentityCopy() const
Return true is the instruction is an identity copy.
Optional< unsigned > getRestoreSize(const TargetInstrInfo *TII) const
Return a valid size if the instruction is a restore instruction.
static MachineInstr * getEmptyKey()
void changeDebugValuesDefReg(unsigned Reg)
Find all DBG_VALUEs immediately following this instruction that point to a register def in this instr...
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:32
bool isMSInlineAsm() const
MachineBasicBlock * getParent()
Definition: MachineInstr.h:254
void untieRegOperand(unsigned OpIdx)
Break any tie involving OpIdx.
int findInlineAsmFlagIdx(unsigned OpIdx, unsigned *GroupNo=nullptr) const
Find the index of the flag word operand that corresponds to operand OpIdx on an inline asm instructio...
void setPostInstrSymbol(MachineFunction &MF, MCSymbol *Symbol)
Set a symbol that will be emitted just after the instruction itself.
void addMemOperand(MachineFunction &MF, MachineMemOperand *MO)
Add a MachineMemOperand to the machine instruction.
bool isInsideBundle() const
Return true if MI is in a bundle (but not the first MI in a bundle).
Definition: MachineInstr.h:349
bool mayAlias(AliasAnalysis *AA, MachineInstr &Other, bool UseTBAA)
Returns true if this instruction&#39;s memory access aliases the memory access of Other.
bool isDereferenceableInvariantLoad(AliasAnalysis *AA) const
Return true if this load instruction never traps and points to a memory location whose value doesn&#39;t ...
bool allDefsAreDead() const
Return true if all the defs of this instruction are dead.
bool isBranch(QueryType Type=AnyInBundle) const
Returns true if this is a conditional, unconditional, or indirect branch.
Definition: MachineInstr.h:656
MCSymbol * getPreInstrSymbol() const
Helper to extract a pre-instruction symbol if one has been added.
Definition: MachineInstr.h:554
Analysis containing CSE Info
Definition: CSEInfo.cpp:20
void clearRegisterKills(unsigned Reg, const TargetRegisterInfo *RegInfo)
Clear all kill flags affecting Reg.
void dropMemRefs(MachineFunction &MF)
Clear this MachineInstr&#39;s memory reference descriptor list.
Flag
These should be considered private to the implementation of the MCInstrDesc class.
Definition: MCInstrDesc.h:117
TargetInstrInfo - Interface to description of machine instruction set.
This corresponds to the llvm.lifetime.
Definition: ISDOpcodes.h:850
bool isReturn(QueryType Type=AnyInBundle) const
Definition: MachineInstr.h:622
iterator_range< const_mop_iterator > uses() const
Returns a range that includes all operands that are register uses.
Definition: MachineInstr.h:495
Optional< unsigned > getSpillSize(const TargetInstrInfo *TII) const
Return a valid size if the instruction is a spill instruction.
static MachineInstr * getTombstoneKey()
bool mayStore(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly modify memory.
Definition: MachineInstr.h:819
#define P(N)
bool isConvertibleTo3Addr(QueryType Type=IgnoreBundle) const
Return true if this is a 2-address instruction which can be changed into a 3-address instruction if n...
Definition: MachineInstr.h:865
An ilist node that can access its parent list.
Definition: ilist_node.h:256
unsigned const MachineRegisterInfo * MRI
bool getAsmPrinterFlag(CommentFlag Flag) const
Return whether an AsmPrinter flag is set.
Definition: MachineInstr.h:274
ArrayRef< MachineMemOperand * > memoperands() const
Access to memory operands of the instruction.
Definition: MachineInstr.h:515
unsigned isConstantValuePHI() const
If the specified instruction is a PHI that always merges together the same virtual register...
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:45
bool isCompare(QueryType Type=IgnoreBundle) const
Return true if this instruction is a comparison.
Definition: MachineInstr.h:693
Allocate memory in an ever growing pool, as if by bump-pointer.
Definition: Allocator.h:140
bool readsVirtualRegister(unsigned Reg) const
Return true if the MachineInstr reads the specified virtual register.
bool isPseudo(QueryType Type=IgnoreBundle) const
Return true if this is a pseudo instruction that doesn&#39;t correspond to a real machine instruction...
Definition: MachineInstr.h:618
bool registerDefIsDead(unsigned Reg, const TargetRegisterInfo *TRI=nullptr) const
Returns true if the register is dead in this machine instruction.
void clearRegisterDeads(unsigned Reg)
Clear all dead flags on operands defining register Reg.
bool isBundled() const
Return true if this instruction part of a bundle.
Definition: MachineInstr.h:355
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:148
LLVM_ATTRIBUTE_RETURNS_NONNULL LLVM_ATTRIBUTE_RETURNS_NOALIAS void * Allocate(size_t Size, size_t Alignment)
Allocate space at the specified alignment.
Definition: Allocator.h:214
bool isOperandSubregIdx(unsigned OpIdx) const
Return true if operand OpIdx is a subregister index.
Definition: MachineInstr.h:428
~MachineInstr()=delete
void setFlag(MIFlag Flag)
Set a MI flag.
Definition: MachineInstr.h:299
void clearFlag(MIFlag Flag)
clearFlag - Clear a MI flag.
Definition: MachineInstr.h:310
bool isSelect(QueryType Type=IgnoreBundle) const
Return true if this instruction is a select instruction.
Definition: MachineInstr.h:715
bool hasOneMemOperand() const
Return true if this instruction has exactly one MachineMemOperand.
Definition: MachineInstr.h:548
iterator_range< const_mop_iterator > explicit_uses() const
Definition: MachineInstr.h:502
See the file comment for details on the usage of the TrailingObjects type.
const DILabel * getDebugLabel() const
Return the debug label referenced by this DBG_LABEL instruction.
iterator_range< mop_iterator > defs()
Returns a range over all explicit operands that are register definitions.
Definition: MachineInstr.h:480
bool isEHLabel() const
Definition: MachineInstr.h:978
bool isRegTiedToDefOperand(unsigned UseOpIdx, unsigned *DefOpIdx=nullptr) const
Return true if the use operand of the specified index is tied to a def operand.
bool definesRegister(unsigned Reg, const TargetRegisterInfo *TRI=nullptr) const
Return true if the MachineInstr fully defines the specified register.
std::pair< bool, bool > readsWritesVirtualRegister(unsigned Reg, SmallVectorImpl< unsigned > *Ops=nullptr) const
Return a pair of bools (reads, writes) indicating if this instruction reads or writes Reg...
void print(raw_ostream &OS, bool IsStandalone=true, bool SkipOpers=false, bool SkipDebugLoc=false, bool AddNewLine=true, const TargetInstrInfo *TII=nullptr) const
Print this MI to OS.
bool hasComplexRegisterTies() const
Return true when an instruction has tied register that can&#39;t be determined by the instruction&#39;s descr...
bool isRematerializable(QueryType Type=AllInBundle) const
Returns true if this instruction is a candidate for remat.
Definition: MachineInstr.h:893
bool isStackAligningInlineAsm() const
bool isCopy() const
bool isInsertSubregLike(QueryType Type=IgnoreBundle) const
Return true if this instruction behaves the same way as the generic INSERT_SUBREG instructions...
Definition: MachineInstr.h:795
bool isImplicitDef() const
bool isConvergent(QueryType Type=AnyInBundle) const
Return true if this instruction is convergent.
Definition: MachineInstr.h:729
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
static wasm::ValType getType(const TargetRegisterClass *RC)
Optional< unsigned > getFoldedSpillSize(const TargetInstrInfo *TII) const
Return a valid size if the instruction is a folded spill instruction.
static uint16_t copyFlagsFromInstruction(const Instruction &I)
bool isDebugInstr() const
Definition: MachineInstr.h:998
unsigned getBundleSize() const
Return the number of instructions inside the MI bundle, excluding the bundle header.
unsigned getNumExplicitOperands() const
Returns the number of non-implicit operands.
const DIExpression * getDebugExpression() const
Return the complex address expression referenced by this DBG_VALUE instruction.
MCSymbol * getPostInstrSymbol() const
Helper to extract a post-instruction symbol if one has been added.
Definition: MachineInstr.h:566
EH_LABEL - Represents a label in mid basic block used to track locations needed for debug and excepti...
Definition: ISDOpcodes.h:676
void eraseFromBundle()
Unlink &#39;this&#39; form its basic block and delete it.
iterator_range< mop_iterator > explicit_uses()
Definition: MachineInstr.h:498
void copyIRFlags(const Instruction &I)
Copy all flags to MachineInst MIFlags.
iterator_range< T > make_range(T x, T y)
Convenience function for iterating over sub-ranges.
MachineInstr * removeFromBundle()
Unlink this instruction from its basic block and return it without deleting it.
Basic Register Allocator
bool isConditionalBranch(QueryType Type=AnyInBundle) const
Return true if this is a branch which may fall through to the next instruction or may transfer contro...
Definition: MachineInstr.h:670
void cloneMemRefs(MachineFunction &MF, const MachineInstr &MI)
Clone another MachineInstr&#39;s memory reference descriptor list and replace ours with it...
unsigned findTiedOperandIdx(unsigned OpIdx) const
Given the index of a tied register operand, find the operand it is tied to.
InlineAsm::AsmDialect getInlineAsmDialect() const
void setDesc(const MCInstrDesc &tid)
Replace the instruction descriptor (thus opcode) of the current instruction with a new one...
void substituteRegister(unsigned FromReg, unsigned ToReg, unsigned SubIdx, const TargetRegisterInfo &RegInfo)
Replace all occurrences of FromReg with ToReg:SubIdx, properly composing subreg indices where necessa...
void addOperand(MachineFunction &MF, const MachineOperand &Op)
Add the specified operand to the instruction.
mmo_iterator memoperands_begin() const
Access to memory operands of the instruction.
Definition: MachineInstr.h:533
void setFlags(unsigned flags)
Definition: MachineInstr.h:303
bool isDebugValue() const
Definition: MachineInstr.h:996
MachineOperand class - Representation of each machine instruction operand.
bool isInsertSubreg() const
iterator end() const
Definition: ArrayRef.h:137
bool hasOrderedMemoryRef() const
Return true if this instruction may have an ordered or volatile memory reference, or if the informati...
bool isVariadic(QueryType Type=IgnoreBundle) const
Return true if this instruction can have a variable number of operands.
Definition: MachineInstr.h:606
iterator_range< const_mop_iterator > explicit_operands() const
Definition: MachineInstr.h:468
int64_t getImm() const
DWARF expression.
unsigned short Opcode
Definition: MCInstrDesc.h:165
void addRegisterDefined(unsigned Reg, const TargetRegisterInfo *RegInfo=nullptr)
We have determined MI defines a register.
A range adaptor for a pair of iterators.
bool hasProperty(unsigned MCFlag, QueryType Type=AnyInBundle) const
Return true if the instruction (or in the case of a bundle, the instructions inside the bundle) has t...
Definition: MachineInstr.h:591
void setDebugLoc(DebugLoc dl)
Replace current source information with new such.
int findRegisterDefOperandIdx(unsigned Reg, bool isDead=false, bool Overlap=false, const TargetRegisterInfo *TRI=nullptr) const
Returns the operand index that is a def of the specified register or -1 if it is not found...
bool readsRegister(unsigned Reg, const TargetRegisterInfo *TRI=nullptr) const
Return true if the MachineInstr reads the specified register.
iterator_range< mop_iterator > implicit_operands()
Definition: MachineInstr.h:472
void addImplicitDefUseOperands(MachineFunction &MF)
Add all implicit def and use operands to this instruction.
bool isUnconditionalBranch(QueryType Type=AnyInBundle) const
Return true if this is a branch which always transfers control flow to some other block...
Definition: MachineInstr.h:678
QueryType
API for querying MachineInstr properties.
Definition: MachineInstr.h:580
A sum type over pointer-like types.
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:253
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
bool isRegSequenceLike(QueryType Type=IgnoreBundle) const
Return true if this instruction behaves the same way as the generic REG_SEQUENCE instructions.
Definition: MachineInstr.h:766
const MachineOperand * findRegisterUseOperand(unsigned Reg, bool isKill=false, const TargetRegisterInfo *TRI=nullptr) const
Representation of each machine instruction.
Definition: MachineInstr.h:63
bool killsRegister(unsigned Reg, const TargetRegisterInfo *TRI=nullptr) const
Return true if the MachineInstr kills the specified register.
bool isMoveReg(QueryType Type=IgnoreBundle) const
Return true if this instruction is a register move.
Definition: MachineInstr.h:705
static cl::opt< bool > UseTBAA("use-tbaa-in-sched-mi", cl::Hidden, cl::init(true), cl::desc("Enable use of TBAA during MI DAG construction"))
void setPreInstrSymbol(MachineFunction &MF, MCSymbol *Symbol)
Set a symbol that will be emitted just prior to the instruction itself.
bool canFoldAsLoad(QueryType Type=IgnoreBundle) const
Return true for instructions that can be folded as memory operands in other instructions.
Definition: MachineInstr.h:752
void cloneMergedMemRefs(MachineFunction &MF, ArrayRef< const MachineInstr *> MIs)
Clone the merge of multiple MachineInstrs&#39; memory reference descriptors list and replace ours with it...
const TargetRegisterClass * getRegClassConstraintEffectForVReg(unsigned Reg, const TargetRegisterClass *CurRC, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI, bool ExploreBundle=false) const
Applies the constraints (def/use) implied by this MI on Reg to the given CurRC.
iterator_range< const_mop_iterator > operands() const
Definition: MachineInstr.h:461
#define I(x, y, z)
Definition: MD5.cpp:58
bool hasExtraSrcRegAllocReq(QueryType Type=AnyInBundle) const
Returns true if this instruction source operands have special register allocation requirements that a...
Definition: MachineInstr.h:916
bool isGCLabel() const
Definition: MachineInstr.h:979
unsigned getNumDefs() const
Returns the total number of definitions.
Definition: MachineInstr.h:423
bool isLoadFoldBarrier() const
Returns true if it is illegal to fold a load across this instruction.
bool isKill() const
raw_ostream & operator<<(raw_ostream &OS, const APInt &I)
Definition: APInt.h:2038
bool isRegTiedToUseOperand(unsigned DefOpIdx, unsigned *UseOpIdx=nullptr) const
Given the index of a register def operand, check if the register def is tied to a source operand...
MachineInstr * removeFromParent()
Unlink &#39;this&#39; from the containing basic block, and return it without deleting it. ...
bool hasOptionalDef(QueryType Type=IgnoreBundle) const
Set if this instruction has an optional definition, e.g.
Definition: MachineInstr.h:612
unsigned getNumExplicitDefs() const
Returns the number of non-implicit definitions.
bool isReg() const
isReg - Tests if this is a MO_Register operand.
uint16_t getFlags() const
Return the MI flags bitvector.
Definition: MachineInstr.h:289
bool mayLoad(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read memory.
Definition: MachineInstr.h:806
bool memoperands_empty() const
Return true if we don&#39;t have any memory operands which described the memory access done by this instr...
Definition: MachineInstr.h:545
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
bool isIdenticalTo(const MachineInstr &Other, MICheckType Check=CheckDefs) const
Return true if this instruction is identical to Other.
bool usesCustomInsertionHook(QueryType Type=IgnoreBundle) const
Return true if this instruction requires custom insertion support when the DAG scheduler is inserting...
Definition: MachineInstr.h:877
void setMemRefs(MachineFunction &MF, ArrayRef< MachineMemOperand *> MemRefs)
Assign this MachineInstr&#39;s memory reference descriptor list.
void clearAsmPrinterFlags()
Clear the AsmPrinter bitvector.
Definition: MachineInstr.h:271
INLINEASM_BR - Terminator version of inline asm. Used by asm-goto.
Definition: ISDOpcodes.h:671
void unbundleFromSucc()
Break bundle below this instruction.
mop_iterator operands_begin()
Definition: MachineInstr.h:452
bool isPosition() const
Definition: MachineInstr.h:994
const DILocalVariable * getDebugVariable() const
Return the debug variable referenced by this DBG_VALUE instruction.
This header defines support for implementing classes that have some trailing object (or arrays of obj...
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E&#39;s largest value.
Definition: BitmaskEnum.h:80
This class implements an extremely fast bulk output stream that can only output to a stream...
Definition: raw_ostream.h:45
Callbacks do nothing by default in iplist and ilist.
Definition: ilist.h:64
iterator_range< const_mop_iterator > implicit_operands() const
Definition: MachineInstr.h:475
bool addRegisterKilled(unsigned IncomingReg, const TargetRegisterInfo *RegInfo, bool AddIfNotFound=false)
We have determined MI kills a register.
bool hasUnmodeledSideEffects() const
Return true if this instruction has side effects that are not modeled by mayLoad / mayStore...
IRTranslator LLVM IR MI
MachineFunction * getMF()
Definition: MachineInstr.h:262
bool isBarrier(QueryType Type=AnyInBundle) const
Returns true if the specified instruction stops control flow from executing the instruction immediate...
Definition: MachineInstr.h:639
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:48
void RemoveOperand(unsigned OpNo)
Erase an operand from an instruction, leaving it with one fewer operand than it started with...
void setAsmPrinterFlag(uint8_t Flag)
Set a flag for the AsmPrinter.
Definition: MachineInstr.h:279
CommentFlag
Flags to specify different kinds of comments to output in assembly code.
Definition: MachineInstr.h:73
unsigned getNumMemOperands() const
Return the number of memory operands.
Definition: MachineInstr.h:551
uint64_t getFlags() const
Return flags of this instruction.
Definition: MCInstrDesc.h:228
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:413
OutputIt copy(R &&Range, OutputIt Out)
Definition: STLExtras.h:1237
bool isIndirectDebugValue() const
A DBG_VALUE is indirect iff the first operand is a register and the second operand is an immediate...
bool isExtractSubreg() const
int findRegisterUseOperandIdx(unsigned Reg, bool isKill=false, const TargetRegisterInfo *TRI=nullptr) const
Returns the operand index that is a use of the specific register or -1 if it is not found...
bool getFlag(MIFlag Flag) const
Return whether an MI flag is set.
Definition: MachineInstr.h:294
bool isSafeToMove(AliasAnalysis *AA, bool &SawStore) const
Return true if it is safe to move this instruction.
bool isAsCheapAsAMove(QueryType Type=AllInBundle) const
Returns true if this instruction has the same cost (or less) than a move instruction.
Definition: MachineInstr.h:905
bool isCommutable(QueryType Type=IgnoreBundle) const
Return true if this may be a 2- or 3-address instruction (of the form "X = op Y, Z, ..."), which produces the same result if Y and Z are exchanged.
Definition: MachineInstr.h:847
uint8_t getAsmPrinterFlags() const
Return the asm printer flags bitvector.
Definition: MachineInstr.h:268
bool isNotDuplicable(QueryType Type=AnyInBundle) const
Return true if this instruction cannot be safely duplicated.
Definition: MachineInstr.h:722
mmo_iterator memoperands_end() const
Access to memory operands of the instruction.
Definition: MachineInstr.h:540
const MachineOperand * findRegisterDefOperand(unsigned Reg, bool isDead=false, bool Overlap=false, const TargetRegisterInfo *TRI=nullptr) const
bool hasTrivialDestructor() const
Check whether this has a trivial destructor.
Definition: DebugLoc.h:69
void tieOperands(unsigned DefIdx, unsigned UseIdx)
Add a tie between the register operands at DefIdx and UseIdx.