LLVM  7.0.0svn
MachineInstr.h
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1 //===- llvm/CodeGen/MachineInstr.h - MachineInstr class ---------*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the declaration of the MachineInstr class, which is the
11 // basic representation for all target dependent machine instructions used by
12 // the back end.
13 //
14 //===----------------------------------------------------------------------===//
15 
16 #ifndef LLVM_CODEGEN_MACHINEINSTR_H
17 #define LLVM_CODEGEN_MACHINEINSTR_H
18 
19 #include "llvm/ADT/DenseMapInfo.h"
20 #include "llvm/ADT/ilist.h"
21 #include "llvm/ADT/ilist_node.h"
26 #include "llvm/IR/DebugLoc.h"
27 #include "llvm/IR/InlineAsm.h"
28 #include "llvm/MC/MCInstrDesc.h"
30 #include <algorithm>
31 #include <cassert>
32 #include <cstdint>
33 #include <utility>
34 
35 namespace llvm {
36 
37 template <typename T> class ArrayRef;
38 class DIExpression;
39 class DILocalVariable;
40 class MachineBasicBlock;
41 class MachineFunction;
42 class MachineMemOperand;
43 class MachineRegisterInfo;
44 class ModuleSlotTracker;
45 class raw_ostream;
46 template <typename T> class SmallVectorImpl;
47 class SmallBitVector;
48 class StringRef;
49 class TargetInstrInfo;
50 class TargetRegisterClass;
51 class TargetRegisterInfo;
52 
53 //===----------------------------------------------------------------------===//
54 /// Representation of each machine instruction.
55 ///
56 /// This class isn't a POD type, but it must have a trivial destructor. When a
57 /// MachineFunction is deleted, all the contained MachineInstrs are deallocated
58 /// without having their destructor called.
59 ///
61  : public ilist_node_with_parent<MachineInstr, MachineBasicBlock,
62  ilist_sentinel_tracking<true>> {
63 public:
65 
66  /// Flags to specify different kinds of comments to output in
67  /// assembly code. These flags carry semantic information not
68  /// otherwise easily derivable from the IR text.
69  ///
70  enum CommentFlag {
71  ReloadReuse = 0x1, // higher bits are reserved for target dep comments.
73  TAsmComments = 0x4 // Target Asm comments should start from this value.
74  };
75 
76  enum MIFlag {
77  NoFlags = 0,
78  FrameSetup = 1 << 0, // Instruction is used as a part of
79  // function frame setup code.
80  FrameDestroy = 1 << 1, // Instruction is used as a part of
81  // function frame destruction code.
82  BundledPred = 1 << 2, // Instruction has bundled predecessors.
83  BundledSucc = 1 << 3 // Instruction has bundled successors.
84  };
85 
86 private:
87  const MCInstrDesc *MCID; // Instruction descriptor.
88  MachineBasicBlock *Parent = nullptr; // Pointer to the owning basic block.
89 
90  // Operands are allocated by an ArrayRecycler.
91  MachineOperand *Operands = nullptr; // Pointer to the first operand.
92  unsigned NumOperands = 0; // Number of operands on instruction.
93  using OperandCapacity = ArrayRecycler<MachineOperand>::Capacity;
94  OperandCapacity CapOperands; // Capacity of the Operands array.
95 
96  uint8_t Flags = 0; // Various bits of additional
97  // information about machine
98  // instruction.
99 
100  uint8_t AsmPrinterFlags = 0; // Various bits of information used by
101  // the AsmPrinter to emit helpful
102  // comments. This is *not* semantic
103  // information. Do not use this for
104  // anything other than to convey comment
105  // information to AsmPrinter.
106 
107  uint8_t NumMemRefs = 0; // Information on memory references.
108  // Note that MemRefs == nullptr, means 'don't know', not 'no memory access'.
109  // Calling code must treat missing information conservatively. If the number
110  // of memory operands required to be precise exceeds the maximum value of
111  // NumMemRefs - currently 256 - we remove the operands entirely. Note also
112  // that this is a non-owning reference to a shared copy on write buffer owned
113  // by the MachineFunction and created via MF.allocateMemRefsArray.
114  mmo_iterator MemRefs = nullptr;
115 
116  DebugLoc debugLoc; // Source line information.
117 
118  // Intrusive list support
119  friend struct ilist_traits<MachineInstr>;
121  void setParent(MachineBasicBlock *P) { Parent = P; }
122 
123  /// This constructor creates a copy of the given
124  /// MachineInstr in the given MachineFunction.
126 
127  /// This constructor create a MachineInstr and add the implicit operands.
128  /// It reserves space for number of operands specified by
129  /// MCInstrDesc. An explicit DebugLoc is supplied.
131  bool NoImp = false);
132 
133  // MachineInstrs are pool-allocated and owned by MachineFunction.
134  friend class MachineFunction;
135 
136 public:
137  MachineInstr(const MachineInstr &) = delete;
138  MachineInstr &operator=(const MachineInstr &) = delete;
139  // Use MachineFunction::DeleteMachineInstr() instead.
140  ~MachineInstr() = delete;
141 
142  const MachineBasicBlock* getParent() const { return Parent; }
143  MachineBasicBlock* getParent() { return Parent; }
144 
145  /// Return the function that contains the basic block that this instruction
146  /// belongs to.
147  ///
148  /// Note: this is undefined behaviour if the instruction does not have a
149  /// parent.
150  const MachineFunction *getMF() const;
152  return const_cast<MachineFunction *>(
153  static_cast<const MachineInstr *>(this)->getMF());
154  }
155 
156  /// Return the asm printer flags bitvector.
157  uint8_t getAsmPrinterFlags() const { return AsmPrinterFlags; }
158 
159  /// Clear the AsmPrinter bitvector.
160  void clearAsmPrinterFlags() { AsmPrinterFlags = 0; }
161 
162  /// Return whether an AsmPrinter flag is set.
164  return AsmPrinterFlags & Flag;
165  }
166 
167  /// Set a flag for the AsmPrinter.
168  void setAsmPrinterFlag(uint8_t Flag) {
169  AsmPrinterFlags |= Flag;
170  }
171 
172  /// Clear specific AsmPrinter flags.
174  AsmPrinterFlags &= ~Flag;
175  }
176 
177  /// Return the MI flags bitvector.
178  uint8_t getFlags() const {
179  return Flags;
180  }
181 
182  /// Return whether an MI flag is set.
183  bool getFlag(MIFlag Flag) const {
184  return Flags & Flag;
185  }
186 
187  /// Set a MI flag.
189  Flags |= (uint8_t)Flag;
190  }
191 
192  void setFlags(unsigned flags) {
193  // Filter out the automatically maintained flags.
194  unsigned Mask = BundledPred | BundledSucc;
195  Flags = (Flags & Mask) | (flags & ~Mask);
196  }
197 
198  /// clearFlag - Clear a MI flag.
200  Flags &= ~((uint8_t)Flag);
201  }
202 
203  /// Return true if MI is in a bundle (but not the first MI in a bundle).
204  ///
205  /// A bundle looks like this before it's finalized:
206  /// ----------------
207  /// | MI |
208  /// ----------------
209  /// |
210  /// ----------------
211  /// | MI * |
212  /// ----------------
213  /// |
214  /// ----------------
215  /// | MI * |
216  /// ----------------
217  /// In this case, the first MI starts a bundle but is not inside a bundle, the
218  /// next 2 MIs are considered "inside" the bundle.
219  ///
220  /// After a bundle is finalized, it looks like this:
221  /// ----------------
222  /// | Bundle |
223  /// ----------------
224  /// |
225  /// ----------------
226  /// | MI * |
227  /// ----------------
228  /// |
229  /// ----------------
230  /// | MI * |
231  /// ----------------
232  /// |
233  /// ----------------
234  /// | MI * |
235  /// ----------------
236  /// The first instruction has the special opcode "BUNDLE". It's not "inside"
237  /// a bundle, but the next three MIs are.
238  bool isInsideBundle() const {
239  return getFlag(BundledPred);
240  }
241 
242  /// Return true if this instruction part of a bundle. This is true
243  /// if either itself or its following instruction is marked "InsideBundle".
244  bool isBundled() const {
245  return isBundledWithPred() || isBundledWithSucc();
246  }
247 
248  /// Return true if this instruction is part of a bundle, and it is not the
249  /// first instruction in the bundle.
250  bool isBundledWithPred() const { return getFlag(BundledPred); }
251 
252  /// Return true if this instruction is part of a bundle, and it is not the
253  /// last instruction in the bundle.
254  bool isBundledWithSucc() const { return getFlag(BundledSucc); }
255 
256  /// Bundle this instruction with its predecessor. This can be an unbundled
257  /// instruction, or it can be the first instruction in a bundle.
258  void bundleWithPred();
259 
260  /// Bundle this instruction with its successor. This can be an unbundled
261  /// instruction, or it can be the last instruction in a bundle.
262  void bundleWithSucc();
263 
264  /// Break bundle above this instruction.
265  void unbundleFromPred();
266 
267  /// Break bundle below this instruction.
268  void unbundleFromSucc();
269 
270  /// Returns the debug location id of this MachineInstr.
271  const DebugLoc &getDebugLoc() const { return debugLoc; }
272 
273  /// Return the debug variable referenced by
274  /// this DBG_VALUE instruction.
275  const DILocalVariable *getDebugVariable() const;
276 
277  /// Return the complex address expression referenced by
278  /// this DBG_VALUE instruction.
279  const DIExpression *getDebugExpression() const;
280 
281  /// Emit an error referring to the source location of this instruction.
282  /// This should only be used for inline assembly that is somehow
283  /// impossible to compile. Other errors should have been handled much
284  /// earlier.
285  ///
286  /// If this method returns, the caller should try to recover from the error.
287  void emitError(StringRef Msg) const;
288 
289  /// Returns the target instruction descriptor of this MachineInstr.
290  const MCInstrDesc &getDesc() const { return *MCID; }
291 
292  /// Returns the opcode of this MachineInstr.
293  unsigned getOpcode() const { return MCID->Opcode; }
294 
295  /// Access to explicit operands of the instruction.
296  unsigned getNumOperands() const { return NumOperands; }
297 
298  const MachineOperand& getOperand(unsigned i) const {
299  assert(i < getNumOperands() && "getOperand() out of range!");
300  return Operands[i];
301  }
302  MachineOperand& getOperand(unsigned i) {
303  assert(i < getNumOperands() && "getOperand() out of range!");
304  return Operands[i];
305  }
306 
307  /// Return true if operand \p OpIdx is a subregister index.
308  bool isOperandSubregIdx(unsigned OpIdx) const {
310  "Expected MO_Immediate operand type.");
311  if (isExtractSubreg() && OpIdx == 2)
312  return true;
313  if (isInsertSubreg() && OpIdx == 3)
314  return true;
315  if (isRegSequence() && OpIdx > 1 && (OpIdx % 2) == 0)
316  return true;
317  if (isSubregToReg() && OpIdx == 3)
318  return true;
319  return false;
320  }
321 
322  /// Returns the number of non-implicit operands.
323  unsigned getNumExplicitOperands() const;
324 
325  /// iterator/begin/end - Iterate over all operands of a machine instruction.
328 
329  mop_iterator operands_begin() { return Operands; }
330  mop_iterator operands_end() { return Operands + NumOperands; }
331 
332  const_mop_iterator operands_begin() const { return Operands; }
333  const_mop_iterator operands_end() const { return Operands + NumOperands; }
334 
337  }
340  }
342  return make_range(operands_begin(),
344  }
346  return make_range(operands_begin(),
348  }
351  }
354  }
355  /// Returns a range over all explicit operands that are register definitions.
356  /// Implicit definition are not included!
358  return make_range(operands_begin(),
359  operands_begin() + getDesc().getNumDefs());
360  }
361  /// \copydoc defs()
363  return make_range(operands_begin(),
364  operands_begin() + getDesc().getNumDefs());
365  }
366  /// Returns a range that includes all operands that are register uses.
367  /// This may include unrelated operands which are not register uses.
369  return make_range(operands_begin() + getDesc().getNumDefs(),
370  operands_end());
371  }
372  /// \copydoc uses()
374  return make_range(operands_begin() + getDesc().getNumDefs(),
375  operands_end());
376  }
378  return make_range(operands_begin() + getDesc().getNumDefs(),
380  }
382  return make_range(operands_begin() + getDesc().getNumDefs(),
384  }
385 
386  /// Returns the number of the operand iterator \p I points to.
388  return I - operands_begin();
389  }
390 
391  /// Access to memory operands of the instruction
392  mmo_iterator memoperands_begin() const { return MemRefs; }
393  mmo_iterator memoperands_end() const { return MemRefs + NumMemRefs; }
394  /// Return true if we don't have any memory operands which described the the
395  /// memory access done by this instruction. If this is true, calling code
396  /// must be conservative.
397  bool memoperands_empty() const { return NumMemRefs == 0; }
398 
401  }
404  }
405 
406  /// Return true if this instruction has exactly one MachineMemOperand.
407  bool hasOneMemOperand() const {
408  return NumMemRefs == 1;
409  }
410 
411  /// Return the number of memory operands.
412  unsigned getNumMemOperands() const { return NumMemRefs; }
413 
414  /// API for querying MachineInstr properties. They are the same as MCInstrDesc
415  /// queries but they are bundle aware.
416 
417  enum QueryType {
418  IgnoreBundle, // Ignore bundles
419  AnyInBundle, // Return true if any instruction in bundle has property
420  AllInBundle // Return true if all instructions in bundle have property
421  };
422 
423  /// Return true if the instruction (or in the case of a bundle,
424  /// the instructions inside the bundle) has the specified property.
425  /// The first argument is the property being queried.
426  /// The second argument indicates whether the query should look inside
427  /// instruction bundles.
428  bool hasProperty(unsigned MCFlag, QueryType Type = AnyInBundle) const {
429  // Inline the fast path for unbundled or bundle-internal instructions.
430  if (Type == IgnoreBundle || !isBundled() || isBundledWithPred())
431  return getDesc().getFlags() & (1ULL << MCFlag);
432 
433  // If this is the first instruction in a bundle, take the slow path.
434  return hasPropertyInBundle(1ULL << MCFlag, Type);
435  }
436 
437  /// Return true if this instruction can have a variable number of operands.
438  /// In this case, the variable operands will be after the normal
439  /// operands but before the implicit definitions and uses (if any are
440  /// present).
443  }
444 
445  /// Set if this instruction has an optional definition, e.g.
446  /// ARM instructions which can set condition code if 's' bit is set.
449  }
450 
451  /// Return true if this is a pseudo instruction that doesn't
452  /// correspond to a real machine instruction.
454  return hasProperty(MCID::Pseudo, Type);
455  }
456 
458  return hasProperty(MCID::Return, Type);
459  }
460 
462  return hasProperty(MCID::Call, Type);
463  }
464 
465  /// Returns true if the specified instruction stops control flow
466  /// from executing the instruction immediately following it. Examples include
467  /// unconditional branches and return instructions.
469  return hasProperty(MCID::Barrier, Type);
470  }
471 
472  /// Returns true if this instruction part of the terminator for a basic block.
473  /// Typically this is things like return and branch instructions.
474  ///
475  /// Various passes use this to insert code into the bottom of a basic block,
476  /// but before control flow occurs.
479  }
480 
481  /// Returns true if this is a conditional, unconditional, or indirect branch.
482  /// Predicates below can be used to discriminate between
483  /// these cases, and the TargetInstrInfo::AnalyzeBranch method can be used to
484  /// get more information.
486  return hasProperty(MCID::Branch, Type);
487  }
488 
489  /// Return true if this is an indirect branch, such as a
490  /// branch through a register.
493  }
494 
495  /// Return true if this is a branch which may fall
496  /// through to the next instruction or may transfer control flow to some other
497  /// block. The TargetInstrInfo::AnalyzeBranch method can be used to get more
498  /// information about this branch.
501  }
502 
503  /// Return true if this is a branch which always
504  /// transfers control flow to some other block. The
505  /// TargetInstrInfo::AnalyzeBranch method can be used to get more information
506  /// about this branch.
509  }
510 
511  /// Return true if this instruction has a predicate operand that
512  /// controls execution. It may be set to 'always', or may be set to other
513  /// values. There are various methods in TargetInstrInfo that can be used to
514  /// control and modify the predicate in this instruction.
516  // If it's a bundle than all bundled instructions must be predicable for this
517  // to return true.
519  }
520 
521  /// Return true if this instruction is a comparison.
523  return hasProperty(MCID::Compare, Type);
524  }
525 
526  /// Return true if this instruction is a move immediate
527  /// (including conditional moves) instruction.
529  return hasProperty(MCID::MoveImm, Type);
530  }
531 
532  /// Return true if this instruction is a bitcast instruction.
534  return hasProperty(MCID::Bitcast, Type);
535  }
536 
537  /// Return true if this instruction is a select instruction.
539  return hasProperty(MCID::Select, Type);
540  }
541 
542  /// Return true if this instruction cannot be safely duplicated.
543  /// For example, if the instruction has a unique labels attached
544  /// to it, duplicating it would cause multiple definition errors.
547  }
548 
549  /// Return true if this instruction is convergent.
550  /// Convergent instructions can not be made control-dependent on any
551  /// additional values.
553  if (isInlineAsm()) {
554  unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
555  if (ExtraInfo & InlineAsm::Extra_IsConvergent)
556  return true;
557  }
559  }
560 
561  /// Returns true if the specified instruction has a delay slot
562  /// which must be filled by the code generator.
565  }
566 
567  /// Return true for instructions that can be folded as
568  /// memory operands in other instructions. The most common use for this
569  /// is instructions that are simple loads from memory that don't modify
570  /// the loaded value in any way, but it can also be used for instructions
571  /// that can be expressed as constant-pool loads, such as V_SETALLONES
572  /// on x86, to allow them to be folded when it is beneficial.
573  /// This should only be set on instructions that return a value in their
574  /// only virtual register definition.
577  }
578 
579  /// \brief Return true if this instruction behaves
580  /// the same way as the generic REG_SEQUENCE instructions.
581  /// E.g., on ARM,
582  /// dX VMOVDRR rY, rZ
583  /// is equivalent to
584  /// dX = REG_SEQUENCE rY, ssub_0, rZ, ssub_1.
585  ///
586  /// Note that for the optimizers to be able to take advantage of
587  /// this property, TargetInstrInfo::getRegSequenceLikeInputs has to be
588  /// override accordingly.
591  }
592 
593  /// \brief Return true if this instruction behaves
594  /// the same way as the generic EXTRACT_SUBREG instructions.
595  /// E.g., on ARM,
596  /// rX, rY VMOVRRD dZ
597  /// is equivalent to two EXTRACT_SUBREG:
598  /// rX = EXTRACT_SUBREG dZ, ssub_0
599  /// rY = EXTRACT_SUBREG dZ, ssub_1
600  ///
601  /// Note that for the optimizers to be able to take advantage of
602  /// this property, TargetInstrInfo::getExtractSubregLikeInputs has to be
603  /// override accordingly.
606  }
607 
608  /// \brief Return true if this instruction behaves
609  /// the same way as the generic INSERT_SUBREG instructions.
610  /// E.g., on ARM,
611  /// dX = VSETLNi32 dY, rZ, Imm
612  /// is equivalent to a INSERT_SUBREG:
613  /// dX = INSERT_SUBREG dY, rZ, translateImmToSubIdx(Imm)
614  ///
615  /// Note that for the optimizers to be able to take advantage of
616  /// this property, TargetInstrInfo::getInsertSubregLikeInputs has to be
617  /// override accordingly.
620  }
621 
622  //===--------------------------------------------------------------------===//
623  // Side Effect Analysis
624  //===--------------------------------------------------------------------===//
625 
626  /// Return true if this instruction could possibly read memory.
627  /// Instructions with this flag set are not necessarily simple load
628  /// instructions, they may load a value and modify it, for example.
630  if (isInlineAsm()) {
631  unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
632  if (ExtraInfo & InlineAsm::Extra_MayLoad)
633  return true;
634  }
635  return hasProperty(MCID::MayLoad, Type);
636  }
637 
638  /// Return true if this instruction could possibly modify memory.
639  /// Instructions with this flag set are not necessarily simple store
640  /// instructions, they may store a modified value based on their operands, or
641  /// may not actually modify anything, for example.
643  if (isInlineAsm()) {
644  unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
645  if (ExtraInfo & InlineAsm::Extra_MayStore)
646  return true;
647  }
649  }
650 
651  /// Return true if this instruction could possibly read or modify memory.
653  return mayLoad(Type) || mayStore(Type);
654  }
655 
656  //===--------------------------------------------------------------------===//
657  // Flags that indicate whether an instruction can be modified by a method.
658  //===--------------------------------------------------------------------===//
659 
660  /// Return true if this may be a 2- or 3-address
661  /// instruction (of the form "X = op Y, Z, ..."), which produces the same
662  /// result if Y and Z are exchanged. If this flag is set, then the
663  /// TargetInstrInfo::commuteInstruction method may be used to hack on the
664  /// instruction.
665  ///
666  /// Note that this flag may be set on instructions that are only commutable
667  /// sometimes. In these cases, the call to commuteInstruction will fail.
668  /// Also note that some instructions require non-trivial modification to
669  /// commute them.
672  }
673 
674  /// Return true if this is a 2-address instruction
675  /// which can be changed into a 3-address instruction if needed. Doing this
676  /// transformation can be profitable in the register allocator, because it
677  /// means that the instruction can use a 2-address form if possible, but
678  /// degrade into a less efficient form if the source and dest register cannot
679  /// be assigned to the same register. For example, this allows the x86
680  /// backend to turn a "shl reg, 3" instruction into an LEA instruction, which
681  /// is the same speed as the shift but has bigger code size.
682  ///
683  /// If this returns true, then the target must implement the
684  /// TargetInstrInfo::convertToThreeAddress method for this instruction, which
685  /// is allowed to fail if the transformation isn't valid for this specific
686  /// instruction (e.g. shl reg, 4 on x86).
687  ///
690  }
691 
692  /// Return true if this instruction requires
693  /// custom insertion support when the DAG scheduler is inserting it into a
694  /// machine basic block. If this is true for the instruction, it basically
695  /// means that it is a pseudo instruction used at SelectionDAG time that is
696  /// expanded out into magic code by the target when MachineInstrs are formed.
697  ///
698  /// If this is true, the TargetLoweringInfo::InsertAtEndOfBasicBlock method
699  /// is used to insert this into the MachineBasicBlock.
702  }
703 
704  /// Return true if this instruction requires *adjustment*
705  /// after instruction selection by calling a target hook. For example, this
706  /// can be used to fill in ARM 's' optional operand depending on whether
707  /// the conditional flag register is used.
710  }
711 
712  /// Returns true if this instruction is a candidate for remat.
713  /// This flag is deprecated, please don't use it anymore. If this
714  /// flag is set, the isReallyTriviallyReMaterializable() method is called to
715  /// verify the instruction is really rematable.
717  // It's only possible to re-mat a bundle if all bundled instructions are
718  // re-materializable.
720  }
721 
722  /// Returns true if this instruction has the same cost (or less) than a move
723  /// instruction. This is useful during certain types of optimizations
724  /// (e.g., remat during two-address conversion or machine licm)
725  /// where we would like to remat or hoist the instruction, but not if it costs
726  /// more than moving the instruction into the appropriate register. Note, we
727  /// are not marking copies from and to the same register class with this flag.
729  // Only returns true for a bundle if all bundled instructions are cheap.
731  }
732 
733  /// Returns true if this instruction source operands
734  /// have special register allocation requirements that are not captured by the
735  /// operand register classes. e.g. ARM::STRD's two source registers must be an
736  /// even / odd pair, ARM::STM registers have to be in ascending order.
737  /// Post-register allocation passes should not attempt to change allocations
738  /// for sources of instructions with this flag.
741  }
742 
743  /// Returns true if this instruction def operands
744  /// have special register allocation requirements that are not captured by the
745  /// operand register classes. e.g. ARM::LDRD's two def registers must be an
746  /// even / odd pair, ARM::LDM registers have to be in ascending order.
747  /// Post-register allocation passes should not attempt to change allocations
748  /// for definitions of instructions with this flag.
751  }
752 
753  enum MICheckType {
754  CheckDefs, // Check all operands for equality
755  CheckKillDead, // Check all operands including kill / dead markers
756  IgnoreDefs, // Ignore all definitions
757  IgnoreVRegDefs // Ignore virtual register definitions
758  };
759 
760  /// Return true if this instruction is identical to \p Other.
761  /// Two instructions are identical if they have the same opcode and all their
762  /// operands are identical (with respect to MachineOperand::isIdenticalTo()).
763  /// Note that this means liveness related flags (dead, undef, kill) do not
764  /// affect the notion of identical.
765  bool isIdenticalTo(const MachineInstr &Other,
766  MICheckType Check = CheckDefs) const;
767 
768  /// Unlink 'this' from the containing basic block, and return it without
769  /// deleting it.
770  ///
771  /// This function can not be used on bundled instructions, use
772  /// removeFromBundle() to remove individual instructions from a bundle.
774 
775  /// Unlink this instruction from its basic block and return it without
776  /// deleting it.
777  ///
778  /// If the instruction is part of a bundle, the other instructions in the
779  /// bundle remain bundled.
781 
782  /// Unlink 'this' from the containing basic block and delete it.
783  ///
784  /// If this instruction is the header of a bundle, the whole bundle is erased.
785  /// This function can not be used for instructions inside a bundle, use
786  /// eraseFromBundle() to erase individual bundled instructions.
787  void eraseFromParent();
788 
789  /// Unlink 'this' from the containing basic block and delete it.
790  ///
791  /// For all definitions mark their uses in DBG_VALUE nodes
792  /// as undefined. Otherwise like eraseFromParent().
794 
795  /// Unlink 'this' form its basic block and delete it.
796  ///
797  /// If the instruction is part of a bundle, the other instructions in the
798  /// bundle remain bundled.
799  void eraseFromBundle();
800 
801  bool isEHLabel() const { return getOpcode() == TargetOpcode::EH_LABEL; }
802  bool isGCLabel() const { return getOpcode() == TargetOpcode::GC_LABEL; }
803  bool isAnnotationLabel() const {
805  }
806 
807  /// Returns true if the MachineInstr represents a label.
808  bool isLabel() const {
809  return isEHLabel() || isGCLabel() || isAnnotationLabel();
810  }
811 
812  bool isCFIInstruction() const {
813  return getOpcode() == TargetOpcode::CFI_INSTRUCTION;
814  }
815 
816  // True if the instruction represents a position in the function.
817  bool isPosition() const { return isLabel() || isCFIInstruction(); }
818 
819  bool isDebugValue() const { return getOpcode() == TargetOpcode::DBG_VALUE; }
820 
821  /// A DBG_VALUE is indirect iff the first operand is a register and
822  /// the second operand is an immediate.
823  bool isIndirectDebugValue() const {
824  return isDebugValue()
825  && getOperand(0).isReg()
826  && getOperand(1).isImm();
827  }
828 
829  bool isPHI() const {
830  return getOpcode() == TargetOpcode::PHI ||
831  getOpcode() == TargetOpcode::G_PHI;
832  }
833  bool isKill() const { return getOpcode() == TargetOpcode::KILL; }
834  bool isImplicitDef() const { return getOpcode()==TargetOpcode::IMPLICIT_DEF; }
835  bool isInlineAsm() const { return getOpcode() == TargetOpcode::INLINEASM; }
836 
837  bool isMSInlineAsm() const {
839  }
840 
841  bool isStackAligningInlineAsm() const;
843 
844  bool isInsertSubreg() const {
845  return getOpcode() == TargetOpcode::INSERT_SUBREG;
846  }
847 
848  bool isSubregToReg() const {
849  return getOpcode() == TargetOpcode::SUBREG_TO_REG;
850  }
851 
852  bool isRegSequence() const {
853  return getOpcode() == TargetOpcode::REG_SEQUENCE;
854  }
855 
856  bool isBundle() const {
857  return getOpcode() == TargetOpcode::BUNDLE;
858  }
859 
860  bool isCopy() const {
861  return getOpcode() == TargetOpcode::COPY;
862  }
863 
864  bool isFullCopy() const {
865  return isCopy() && !getOperand(0).getSubReg() && !getOperand(1).getSubReg();
866  }
867 
868  bool isExtractSubreg() const {
869  return getOpcode() == TargetOpcode::EXTRACT_SUBREG;
870  }
871 
872  /// Return true if the instruction behaves like a copy.
873  /// This does not include native copy instructions.
874  bool isCopyLike() const {
875  return isCopy() || isSubregToReg();
876  }
877 
878  /// Return true is the instruction is an identity copy.
879  bool isIdentityCopy() const {
880  return isCopy() && getOperand(0).getReg() == getOperand(1).getReg() &&
882  }
883 
884  /// Return true if this instruction doesn't produce any output in the form of
885  /// executable instructions.
886  bool isMetaInstruction() const {
887  switch (getOpcode()) {
888  default:
889  return false;
890  case TargetOpcode::IMPLICIT_DEF:
891  case TargetOpcode::KILL:
892  case TargetOpcode::CFI_INSTRUCTION:
894  case TargetOpcode::GC_LABEL:
895  case TargetOpcode::DBG_VALUE:
896  return true;
897  }
898  }
899 
900  /// Return true if this is a transient instruction that is either very likely
901  /// to be eliminated during register allocation (such as copy-like
902  /// instructions), or if this instruction doesn't have an execution-time cost.
903  bool isTransient() const {
904  switch (getOpcode()) {
905  default:
906  return isMetaInstruction();
907  // Copy-like instructions are usually eliminated during register allocation.
908  case TargetOpcode::PHI:
909  case TargetOpcode::G_PHI:
910  case TargetOpcode::COPY:
911  case TargetOpcode::INSERT_SUBREG:
912  case TargetOpcode::SUBREG_TO_REG:
913  case TargetOpcode::REG_SEQUENCE:
914  return true;
915  }
916  }
917 
918  /// Return the number of instructions inside the MI bundle, excluding the
919  /// bundle header.
920  ///
921  /// This is the number of instructions that MachineBasicBlock::iterator
922  /// skips, 0 for unbundled instructions.
923  unsigned getBundleSize() const;
924 
925  /// Return true if the MachineInstr reads the specified register.
926  /// If TargetRegisterInfo is passed, then it also checks if there
927  /// is a read of a super-register.
928  /// This does not count partial redefines of virtual registers as reads:
929  /// %reg1024:6 = OP.
930  bool readsRegister(unsigned Reg,
931  const TargetRegisterInfo *TRI = nullptr) const {
932  return findRegisterUseOperandIdx(Reg, false, TRI) != -1;
933  }
934 
935  /// Return true if the MachineInstr reads the specified virtual register.
936  /// Take into account that a partial define is a
937  /// read-modify-write operation.
938  bool readsVirtualRegister(unsigned Reg) const {
939  return readsWritesVirtualRegister(Reg).first;
940  }
941 
942  /// Return a pair of bools (reads, writes) indicating if this instruction
943  /// reads or writes Reg. This also considers partial defines.
944  /// If Ops is not null, all operand indices for Reg are added.
945  std::pair<bool,bool> readsWritesVirtualRegister(unsigned Reg,
946  SmallVectorImpl<unsigned> *Ops = nullptr) const;
947 
948  /// Return true if the MachineInstr kills the specified register.
949  /// If TargetRegisterInfo is passed, then it also checks if there is
950  /// a kill of a super-register.
951  bool killsRegister(unsigned Reg,
952  const TargetRegisterInfo *TRI = nullptr) const {
953  return findRegisterUseOperandIdx(Reg, true, TRI) != -1;
954  }
955 
956  /// Return true if the MachineInstr fully defines the specified register.
957  /// If TargetRegisterInfo is passed, then it also checks
958  /// if there is a def of a super-register.
959  /// NOTE: It's ignoring subreg indices on virtual registers.
960  bool definesRegister(unsigned Reg,
961  const TargetRegisterInfo *TRI = nullptr) const {
962  return findRegisterDefOperandIdx(Reg, false, false, TRI) != -1;
963  }
964 
965  /// Return true if the MachineInstr modifies (fully define or partially
966  /// define) the specified register.
967  /// NOTE: It's ignoring subreg indices on virtual registers.
968  bool modifiesRegister(unsigned Reg, const TargetRegisterInfo *TRI) const {
969  return findRegisterDefOperandIdx(Reg, false, true, TRI) != -1;
970  }
971 
972  /// Returns true if the register is dead in this machine instruction.
973  /// If TargetRegisterInfo is passed, then it also checks
974  /// if there is a dead def of a super-register.
975  bool registerDefIsDead(unsigned Reg,
976  const TargetRegisterInfo *TRI = nullptr) const {
977  return findRegisterDefOperandIdx(Reg, true, false, TRI) != -1;
978  }
979 
980  /// Returns true if the MachineInstr has an implicit-use operand of exactly
981  /// the given register (not considering sub/super-registers).
982  bool hasRegisterImplicitUseOperand(unsigned Reg) const;
983 
984  /// Returns the operand index that is a use of the specific register or -1
985  /// if it is not found. It further tightens the search criteria to a use
986  /// that kills the register if isKill is true.
987  int findRegisterUseOperandIdx(unsigned Reg, bool isKill = false,
988  const TargetRegisterInfo *TRI = nullptr) const;
989 
990  /// Wrapper for findRegisterUseOperandIdx, it returns
991  /// a pointer to the MachineOperand rather than an index.
992  MachineOperand *findRegisterUseOperand(unsigned Reg, bool isKill = false,
993  const TargetRegisterInfo *TRI = nullptr) {
994  int Idx = findRegisterUseOperandIdx(Reg, isKill, TRI);
995  return (Idx == -1) ? nullptr : &getOperand(Idx);
996  }
997 
999  unsigned Reg, bool isKill = false,
1000  const TargetRegisterInfo *TRI = nullptr) const {
1001  return const_cast<MachineInstr *>(this)->
1002  findRegisterUseOperand(Reg, isKill, TRI);
1003  }
1004 
1005  /// Returns the operand index that is a def of the specified register or
1006  /// -1 if it is not found. If isDead is true, defs that are not dead are
1007  /// skipped. If Overlap is true, then it also looks for defs that merely
1008  /// overlap the specified register. If TargetRegisterInfo is non-null,
1009  /// then it also checks if there is a def of a super-register.
1010  /// This may also return a register mask operand when Overlap is true.
1011  int findRegisterDefOperandIdx(unsigned Reg,
1012  bool isDead = false, bool Overlap = false,
1013  const TargetRegisterInfo *TRI = nullptr) const;
1014 
1015  /// Wrapper for findRegisterDefOperandIdx, it returns
1016  /// a pointer to the MachineOperand rather than an index.
1017  MachineOperand *findRegisterDefOperand(unsigned Reg, bool isDead = false,
1018  const TargetRegisterInfo *TRI = nullptr) {
1019  int Idx = findRegisterDefOperandIdx(Reg, isDead, false, TRI);
1020  return (Idx == -1) ? nullptr : &getOperand(Idx);
1021  }
1022 
1023  /// Find the index of the first operand in the
1024  /// operand list that is used to represent the predicate. It returns -1 if
1025  /// none is found.
1026  int findFirstPredOperandIdx() const;
1027 
1028  /// Find the index of the flag word operand that
1029  /// corresponds to operand OpIdx on an inline asm instruction. Returns -1 if
1030  /// getOperand(OpIdx) does not belong to an inline asm operand group.
1031  ///
1032  /// If GroupNo is not NULL, it will receive the number of the operand group
1033  /// containing OpIdx.
1034  ///
1035  /// The flag operand is an immediate that can be decoded with methods like
1036  /// InlineAsm::hasRegClassConstraint().
1037  int findInlineAsmFlagIdx(unsigned OpIdx, unsigned *GroupNo = nullptr) const;
1038 
1039  /// Compute the static register class constraint for operand OpIdx.
1040  /// For normal instructions, this is derived from the MCInstrDesc.
1041  /// For inline assembly it is derived from the flag words.
1042  ///
1043  /// Returns NULL if the static register class constraint cannot be
1044  /// determined.
1045  const TargetRegisterClass*
1046  getRegClassConstraint(unsigned OpIdx,
1047  const TargetInstrInfo *TII,
1048  const TargetRegisterInfo *TRI) const;
1049 
1050  /// \brief Applies the constraints (def/use) implied by this MI on \p Reg to
1051  /// the given \p CurRC.
1052  /// If \p ExploreBundle is set and MI is part of a bundle, all the
1053  /// instructions inside the bundle will be taken into account. In other words,
1054  /// this method accumulates all the constraints of the operand of this MI and
1055  /// the related bundle if MI is a bundle or inside a bundle.
1056  ///
1057  /// Returns the register class that satisfies both \p CurRC and the
1058  /// constraints set by MI. Returns NULL if such a register class does not
1059  /// exist.
1060  ///
1061  /// \pre CurRC must not be NULL.
1063  unsigned Reg, const TargetRegisterClass *CurRC,
1064  const TargetInstrInfo *TII, const TargetRegisterInfo *TRI,
1065  bool ExploreBundle = false) const;
1066 
1067  /// \brief Applies the constraints (def/use) implied by the \p OpIdx operand
1068  /// to the given \p CurRC.
1069  ///
1070  /// Returns the register class that satisfies both \p CurRC and the
1071  /// constraints set by \p OpIdx MI. Returns NULL if such a register class
1072  /// does not exist.
1073  ///
1074  /// \pre CurRC must not be NULL.
1075  /// \pre The operand at \p OpIdx must be a register.
1076  const TargetRegisterClass *
1077  getRegClassConstraintEffect(unsigned OpIdx, const TargetRegisterClass *CurRC,
1078  const TargetInstrInfo *TII,
1079  const TargetRegisterInfo *TRI) const;
1080 
1081  /// Add a tie between the register operands at DefIdx and UseIdx.
1082  /// The tie will cause the register allocator to ensure that the two
1083  /// operands are assigned the same physical register.
1084  ///
1085  /// Tied operands are managed automatically for explicit operands in the
1086  /// MCInstrDesc. This method is for exceptional cases like inline asm.
1087  void tieOperands(unsigned DefIdx, unsigned UseIdx);
1088 
1089  /// Given the index of a tied register operand, find the
1090  /// operand it is tied to. Defs are tied to uses and vice versa. Returns the
1091  /// index of the tied operand which must exist.
1092  unsigned findTiedOperandIdx(unsigned OpIdx) const;
1093 
1094  /// Given the index of a register def operand,
1095  /// check if the register def is tied to a source operand, due to either
1096  /// two-address elimination or inline assembly constraints. Returns the
1097  /// first tied use operand index by reference if UseOpIdx is not null.
1098  bool isRegTiedToUseOperand(unsigned DefOpIdx,
1099  unsigned *UseOpIdx = nullptr) const {
1100  const MachineOperand &MO = getOperand(DefOpIdx);
1101  if (!MO.isReg() || !MO.isDef() || !MO.isTied())
1102  return false;
1103  if (UseOpIdx)
1104  *UseOpIdx = findTiedOperandIdx(DefOpIdx);
1105  return true;
1106  }
1107 
1108  /// Return true if the use operand of the specified index is tied to a def
1109  /// operand. It also returns the def operand index by reference if DefOpIdx
1110  /// is not null.
1111  bool isRegTiedToDefOperand(unsigned UseOpIdx,
1112  unsigned *DefOpIdx = nullptr) const {
1113  const MachineOperand &MO = getOperand(UseOpIdx);
1114  if (!MO.isReg() || !MO.isUse() || !MO.isTied())
1115  return false;
1116  if (DefOpIdx)
1117  *DefOpIdx = findTiedOperandIdx(UseOpIdx);
1118  return true;
1119  }
1120 
1121  /// Clears kill flags on all operands.
1122  void clearKillInfo();
1123 
1124  /// Replace all occurrences of FromReg with ToReg:SubIdx,
1125  /// properly composing subreg indices where necessary.
1126  void substituteRegister(unsigned FromReg, unsigned ToReg, unsigned SubIdx,
1127  const TargetRegisterInfo &RegInfo);
1128 
1129  /// We have determined MI kills a register. Look for the
1130  /// operand that uses it and mark it as IsKill. If AddIfNotFound is true,
1131  /// add a implicit operand if it's not found. Returns true if the operand
1132  /// exists / is added.
1133  bool addRegisterKilled(unsigned IncomingReg,
1134  const TargetRegisterInfo *RegInfo,
1135  bool AddIfNotFound = false);
1136 
1137  /// Clear all kill flags affecting Reg. If RegInfo is provided, this includes
1138  /// all aliasing registers.
1139  void clearRegisterKills(unsigned Reg, const TargetRegisterInfo *RegInfo);
1140 
1141  /// We have determined MI defined a register without a use.
1142  /// Look for the operand that defines it and mark it as IsDead. If
1143  /// AddIfNotFound is true, add a implicit operand if it's not found. Returns
1144  /// true if the operand exists / is added.
1145  bool addRegisterDead(unsigned Reg, const TargetRegisterInfo *RegInfo,
1146  bool AddIfNotFound = false);
1147 
1148  /// Clear all dead flags on operands defining register @p Reg.
1149  void clearRegisterDeads(unsigned Reg);
1150 
1151  /// Mark all subregister defs of register @p Reg with the undef flag.
1152  /// This function is used when we determined to have a subregister def in an
1153  /// otherwise undefined super register.
1154  void setRegisterDefReadUndef(unsigned Reg, bool IsUndef = true);
1155 
1156  /// We have determined MI defines a register. Make sure there is an operand
1157  /// defining Reg.
1158  void addRegisterDefined(unsigned Reg,
1159  const TargetRegisterInfo *RegInfo = nullptr);
1160 
1161  /// Mark every physreg used by this instruction as
1162  /// dead except those in the UsedRegs list.
1163  ///
1164  /// On instructions with register mask operands, also add implicit-def
1165  /// operands for all registers in UsedRegs.
1167  const TargetRegisterInfo &TRI);
1168 
1169  /// Return true if it is safe to move this instruction. If
1170  /// SawStore is set to true, it means that there is a store (or call) between
1171  /// the instruction's location and its intended destination.
1172  bool isSafeToMove(AliasAnalysis *AA, bool &SawStore) const;
1173 
1174  /// Returns true if this instruction's memory access aliases the memory
1175  /// access of Other.
1176  //
1177  /// Assumes any physical registers used to compute addresses
1178  /// have the same value for both instructions. Returns false if neither
1179  /// instruction writes to memory.
1180  ///
1181  /// @param AA Optional alias analysis, used to compare memory operands.
1182  /// @param Other MachineInstr to check aliasing against.
1183  /// @param UseTBAA Whether to pass TBAA information to alias analysis.
1184  bool mayAlias(AliasAnalysis *AA, MachineInstr &Other, bool UseTBAA);
1185 
1186  /// Return true if this instruction may have an ordered
1187  /// or volatile memory reference, or if the information describing the memory
1188  /// reference is not available. Return false if it is known to have no
1189  /// ordered or volatile memory references.
1190  bool hasOrderedMemoryRef() const;
1191 
1192  /// Return true if this load instruction never traps and points to a memory
1193  /// location whose value doesn't change during the execution of this function.
1194  ///
1195  /// Examples include loading a value from the constant pool or from the
1196  /// argument area of a function (if it does not change). If the instruction
1197  /// does multiple loads, this returns true only if all of the loads are
1198  /// dereferenceable and invariant.
1200 
1201  /// If the specified instruction is a PHI that always merges together the
1202  /// same virtual register, return the register, otherwise return 0.
1203  unsigned isConstantValuePHI() const;
1204 
1205  /// Return true if this instruction has side effects that are not modeled
1206  /// by mayLoad / mayStore, etc.
1207  /// For all instructions, the property is encoded in MCInstrDesc::Flags
1208  /// (see MCInstrDesc::hasUnmodeledSideEffects(). The only exception is
1209  /// INLINEASM instruction, in which case the side effect property is encoded
1210  /// in one of its operands (see InlineAsm::Extra_HasSideEffect).
1211  ///
1212  bool hasUnmodeledSideEffects() const;
1213 
1214  /// Returns true if it is illegal to fold a load across this instruction.
1215  bool isLoadFoldBarrier() const;
1216 
1217  /// Return true if all the defs of this instruction are dead.
1218  bool allDefsAreDead() const;
1219 
1220  /// Copy implicit register operands from specified
1221  /// instruction to this instruction.
1222  void copyImplicitOps(MachineFunction &MF, const MachineInstr &MI);
1223 
1224  /// Debugging support
1225  /// @{
1226  /// Determine the generic type to be printed (if needed) on uses and defs.
1227  LLT getTypeToPrint(unsigned OpIdx, SmallBitVector &PrintedTypes,
1228  const MachineRegisterInfo &MRI) const;
1229 
1230  /// Return true when an instruction has tied register that can't be determined
1231  /// by the instruction's descriptor. This is useful for MIR printing, to
1232  /// determine whether we need to print the ties or not.
1233  bool hasComplexRegisterTies() const;
1234 
1235  /// Print this MI to \p OS.
1236  /// Only print the defs and the opcode if \p SkipOpers is true.
1237  /// Otherwise, also print operands if \p SkipDebugLoc is true.
1238  /// Otherwise, also print the debug loc, with a terminating newline.
1239  /// \p TII is used to print the opcode name. If it's not present, but the
1240  /// MI is in a function, the opcode will be printed using the function's TII.
1241  void print(raw_ostream &OS, bool SkipOpers = false, bool SkipDebugLoc = false,
1242  const TargetInstrInfo *TII = nullptr) const;
1243  void print(raw_ostream &OS, ModuleSlotTracker &MST, bool SkipOpers = false,
1244  bool SkipDebugLoc = false,
1245  const TargetInstrInfo *TII = nullptr) const;
1246  void dump() const;
1247  /// @}
1248 
1249  //===--------------------------------------------------------------------===//
1250  // Accessors used to build up machine instructions.
1251 
1252  /// Add the specified operand to the instruction. If it is an implicit
1253  /// operand, it is added to the end of the operand list. If it is an
1254  /// explicit operand it is added at the end of the explicit operand list
1255  /// (before the first implicit operand).
1256  ///
1257  /// MF must be the machine function that was used to allocate this
1258  /// instruction.
1259  ///
1260  /// MachineInstrBuilder provides a more convenient interface for creating
1261  /// instructions and adding operands.
1262  void addOperand(MachineFunction &MF, const MachineOperand &Op);
1263 
1264  /// Add an operand without providing an MF reference. This only works for
1265  /// instructions that are inserted in a basic block.
1266  ///
1267  /// MachineInstrBuilder and the two-argument addOperand(MF, MO) should be
1268  /// preferred.
1269  void addOperand(const MachineOperand &Op);
1270 
1271  /// Replace the instruction descriptor (thus opcode) of
1272  /// the current instruction with a new one.
1273  void setDesc(const MCInstrDesc &tid) { MCID = &tid; }
1274 
1275  /// Replace current source information with new such.
1276  /// Avoid using this, the constructor argument is preferable.
1278  debugLoc = std::move(dl);
1279  assert(debugLoc.hasTrivialDestructor() && "Expected trivial destructor");
1280  }
1281 
1282  /// Erase an operand from an instruction, leaving it with one
1283  /// fewer operand than it started with.
1284  void RemoveOperand(unsigned i);
1285 
1286  /// Add a MachineMemOperand to the machine instruction.
1287  /// This function should be used only occasionally. The setMemRefs function
1288  /// is the primary method for setting up a MachineInstr's MemRefs list.
1290 
1291  /// Assign this MachineInstr's memory reference descriptor list.
1292  /// This does not transfer ownership.
1293  void setMemRefs(mmo_iterator NewMemRefs, mmo_iterator NewMemRefsEnd) {
1294  setMemRefs(std::make_pair(NewMemRefs, NewMemRefsEnd-NewMemRefs));
1295  }
1296 
1297  /// Assign this MachineInstr's memory reference descriptor list. First
1298  /// element in the pair is the begin iterator/pointer to the array; the
1299  /// second is the number of MemoryOperands. This does not transfer ownership
1300  /// of the underlying memory.
1301  void setMemRefs(std::pair<mmo_iterator, unsigned> NewMemRefs) {
1302  MemRefs = NewMemRefs.first;
1303  NumMemRefs = uint8_t(NewMemRefs.second);
1304  assert(NumMemRefs == NewMemRefs.second &&
1305  "Too many memrefs - must drop memory operands");
1306  }
1307 
1308  /// Return a set of memrefs (begin iterator, size) which conservatively
1309  /// describe the memory behavior of both MachineInstrs. This is appropriate
1310  /// for use when merging two MachineInstrs into one. This routine does not
1311  /// modify the memrefs of the this MachineInstr.
1312  std::pair<mmo_iterator, unsigned> mergeMemRefsWith(const MachineInstr& Other);
1313 
1314  /// Clear this MachineInstr's memory reference descriptor list. This resets
1315  /// the memrefs to their most conservative state. This should be used only
1316  /// as a last resort since it greatly pessimizes our knowledge of the memory
1317  /// access performed by the instruction.
1318  void dropMemRefs() {
1319  MemRefs = nullptr;
1320  NumMemRefs = 0;
1321  }
1322 
1323  /// Break any tie involving OpIdx.
1324  void untieRegOperand(unsigned OpIdx) {
1325  MachineOperand &MO = getOperand(OpIdx);
1326  if (MO.isReg() && MO.isTied()) {
1327  getOperand(findTiedOperandIdx(OpIdx)).TiedTo = 0;
1328  MO.TiedTo = 0;
1329  }
1330  }
1331 
1332  /// Add all implicit def and use operands to this instruction.
1334 
1335 private:
1336  /// If this instruction is embedded into a MachineFunction, return the
1337  /// MachineRegisterInfo object for the current function, otherwise
1338  /// return null.
1339  MachineRegisterInfo *getRegInfo();
1340 
1341  /// Unlink all of the register operands in this instruction from their
1342  /// respective use lists. This requires that the operands already be on their
1343  /// use lists.
1344  void RemoveRegOperandsFromUseLists(MachineRegisterInfo&);
1345 
1346  /// Add all of the register operands in this instruction from their
1347  /// respective use lists. This requires that the operands not be on their
1348  /// use lists yet.
1349  void AddRegOperandsToUseLists(MachineRegisterInfo&);
1350 
1351  /// Slow path for hasProperty when we're dealing with a bundle.
1352  bool hasPropertyInBundle(unsigned Mask, QueryType Type) const;
1353 
1354  /// \brief Implements the logic of getRegClassConstraintEffectForVReg for the
1355  /// this MI and the given operand index \p OpIdx.
1356  /// If the related operand does not constrained Reg, this returns CurRC.
1357  const TargetRegisterClass *getRegClassConstraintEffectForVRegImpl(
1358  unsigned OpIdx, unsigned Reg, const TargetRegisterClass *CurRC,
1359  const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const;
1360 };
1361 
1362 /// Special DenseMapInfo traits to compare MachineInstr* by *value* of the
1363 /// instruction rather than by pointer value.
1364 /// The hashing and equality testing functions ignore definitions so this is
1365 /// useful for CSE, etc.
1367  static inline MachineInstr *getEmptyKey() {
1368  return nullptr;
1369  }
1370 
1371  static inline MachineInstr *getTombstoneKey() {
1372  return reinterpret_cast<MachineInstr*>(-1);
1373  }
1374 
1375  static unsigned getHashValue(const MachineInstr* const &MI);
1376 
1377  static bool isEqual(const MachineInstr* const &LHS,
1378  const MachineInstr* const &RHS) {
1379  if (RHS == getEmptyKey() || RHS == getTombstoneKey() ||
1380  LHS == getEmptyKey() || LHS == getTombstoneKey())
1381  return LHS == RHS;
1382  return LHS->isIdenticalTo(*RHS, MachineInstr::IgnoreVRegDefs);
1383  }
1384 };
1385 
1386 //===----------------------------------------------------------------------===//
1387 // Debugging Support
1388 
1390  MI.print(OS);
1391  return OS;
1392 }
1393 
1394 } // end namespace llvm
1395 
1396 #endif // LLVM_CODEGEN_MACHINEINSTR_H
ANNOTATION_LABEL - Represents a mid basic block label used by annotations.
Definition: ISDOpcodes.h:646
static bool Check(DecodeStatus &Out, DecodeStatus In)
void bundleWithPred()
Bundle this instruction with its predecessor.
LLT getTypeToPrint(unsigned OpIdx, SmallBitVector &PrintedTypes, const MachineRegisterInfo &MRI) const
Debugging supportDetermine the generic type to be printed (if needed) on uses and defs...
const_iterator end(StringRef path)
Get end iterator over path.
Definition: Path.cpp:245
mop_iterator operands_end()
Definition: MachineInstr.h:330
bool hasRegisterImplicitUseOperand(unsigned Reg) const
Returns true if the MachineInstr has an implicit-use operand of exactly the given register (not consi...
bool hasPostISelHook(QueryType Type=IgnoreBundle) const
Return true if this instruction requires adjustment after instruction selection by calling a target h...
Definition: MachineInstr.h:708
bool modifiesRegister(unsigned Reg, const TargetRegisterInfo *TRI) const
Return true if the MachineInstr modifies (fully define or partially define) the specified register...
Definition: MachineInstr.h:968
const_mop_iterator operands_end() const
Definition: MachineInstr.h:333
bool isLabel() const
Returns true if the MachineInstr represents a label.
Definition: MachineInstr.h:808
int findFirstPredOperandIdx() const
Find the index of the first operand in the operand list that is used to represent the predicate...
bool isCall(QueryType Type=AnyInBundle) const
Definition: MachineInstr.h:461
void emitError(StringRef Msg) const
Emit an error referring to the source location of this instruction.
This is a &#39;bitvector&#39; (really, a variable-sized bit array), optimized for the case when the array is ...
const MachineFunction * getMF() const
Return the function that contains the basic block that this instruction belongs to.
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
iterator_range< mop_iterator > uses()
Returns a range that includes all operands that are register uses.
Definition: MachineInstr.h:368
MachineOperand * findRegisterDefOperand(unsigned Reg, bool isDead=false, const TargetRegisterInfo *TRI=nullptr)
Wrapper for findRegisterDefOperandIdx, it returns a pointer to the MachineOperand rather than an inde...
iterator_range< mop_iterator > explicit_operands()
Definition: MachineInstr.h:341
bool hasExtraDefRegAllocReq(QueryType Type=AnyInBundle) const
Returns true if this instruction def operands have special register allocation requirements that are ...
Definition: MachineInstr.h:749
void setRegisterDefReadUndef(unsigned Reg, bool IsUndef=true)
Mark all subregister defs of register Reg with the undef flag.
bool addRegisterDead(unsigned Reg, const TargetRegisterInfo *RegInfo, bool AddIfNotFound=false)
We have determined MI defined a register without a use.
bool isCFIInstruction() const
Definition: MachineInstr.h:812
bool isBundledWithPred() const
Return true if this instruction is part of a bundle, and it is not the first instruction in the bundl...
Definition: MachineInstr.h:250
bool isExtractSubregLike(QueryType Type=IgnoreBundle) const
Return true if this instruction behaves the same way as the generic EXTRACT_SUBREG instructions...
Definition: MachineInstr.h:604
bool isSubregToReg() const
Definition: MachineInstr.h:848
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:271
This provides a very simple, boring adaptor for a begin and end iterator into a range type...
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:163
unsigned getReg() const
getReg - Returns the register number.
unsigned getOperandNo(const_mop_iterator I) const
Returns the number of the operand iterator I points to.
Definition: MachineInstr.h:387
MachineOperand * findRegisterUseOperand(unsigned Reg, bool isKill=false, const TargetRegisterInfo *TRI=nullptr)
Wrapper for findRegisterUseOperandIdx, it returns a pointer to the MachineOperand rather than an inde...
Definition: MachineInstr.h:992
bool hasDelaySlot(QueryType Type=AnyInBundle) const
Returns true if the specified instruction has a delay slot which must be filled by the code generator...
Definition: MachineInstr.h:563
unsigned getSubReg() const
static bool isEqual(const MachineInstr *const &LHS, const MachineInstr *const &RHS)
bool isInlineAsm() const
Definition: MachineInstr.h:835
bool isPredicable(QueryType Type=AllInBundle) const
Return true if this instruction has a predicate operand that controls execution.
Definition: MachineInstr.h:515
bool isAnnotationLabel() const
Definition: MachineInstr.h:803
MachineInstr & operator=(const MachineInstr &)=delete
bool isRegSequence() const
Definition: MachineInstr.h:852
bool mayLoadOrStore(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read or modify memory.
Definition: MachineInstr.h:652
Template traits for intrusive list.
Definition: ilist.h:101
void clearAsmPrinterFlag(CommentFlag Flag)
Clear specific AsmPrinter flags.
Definition: MachineInstr.h:173
Recycle small arrays allocated from a BumpPtrAllocator.
Definition: ArrayRecycler.h:29
bool isTransient() const
Return true if this is a transient instruction that is either very likely to be eliminated during reg...
Definition: MachineInstr.h:903
A debug info location.
Definition: DebugLoc.h:34
Manage lifetime of a slot tracker for printing IR.
iterator_range< mmo_iterator > memoperands()
Definition: MachineInstr.h:399
MachineOperand & getOperand(unsigned i)
Definition: MachineInstr.h:302
bool isMetaInstruction() const
Return true if this instruction doesn&#39;t produce any output in the form of executable instructions...
Definition: MachineInstr.h:886
iterator_range< mop_iterator > operands()
Definition: MachineInstr.h:335
bool isCopyLike() const
Return true if the instruction behaves like a copy.
Definition: MachineInstr.h:874
bool isPHI() const
Definition: MachineInstr.h:829
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
void setPhysRegsDeadExcept(ArrayRef< unsigned > UsedRegs, const TargetRegisterInfo &TRI)
Mark every physreg used by this instruction as dead except those in the UsedRegs list.
Special DenseMapInfo traits to compare MachineInstr* by value of the instruction rather than by point...
bool isMoveImmediate(QueryType Type=IgnoreBundle) const
Return true if this instruction is a move immediate (including conditional moves) instruction...
Definition: MachineInstr.h:528
bool isBitcast(QueryType Type=IgnoreBundle) const
Return true if this instruction is a bitcast instruction.
Definition: MachineInstr.h:533
void clearKillInfo()
Clears kill flags on all operands.
A description of a memory reference used in the backend.
const HexagonInstrInfo * TII
const TargetRegisterClass * getRegClassConstraint(unsigned OpIdx, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const
Compute the static register class constraint for operand OpIdx.
unsigned getNumOperands() const
Access to explicit operands of the instruction.
Definition: MachineInstr.h:296
bool isBundledWithSucc() const
Return true if this instruction is part of a bundle, and it is not the last instruction in the bundle...
Definition: MachineInstr.h:254
iterator_range< const_mop_iterator > defs() const
Returns a range over all explicit operands that are register definitions.
Definition: MachineInstr.h:362
void eraseFromParent()
Unlink &#39;this&#39; from the containing basic block and delete it.
Reg
All possible values of the reg field in the ModR/M byte.
bool isTerminator(QueryType Type=AnyInBundle) const
Returns true if this instruction part of the terminator for a basic block.
Definition: MachineInstr.h:477
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:293
void bundleWithSucc()
Bundle this instruction with its successor.
const TargetRegisterClass * getRegClassConstraintEffect(unsigned OpIdx, const TargetRegisterClass *CurRC, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const
Applies the constraints (def/use) implied by the OpIdx operand to the given CurRC.
ELFYAML::ELF_STO Other
Definition: ELFYAML.cpp:736
INLINEASM - Represents an inline asm block.
Definition: ISDOpcodes.h:635
void eraseFromParentAndMarkDBGValuesForRemoval()
Unlink &#39;this&#39; from the containing basic block and delete it.
const_mop_iterator operands_begin() const
Definition: MachineInstr.h:332
void unbundleFromPred()
Break bundle above this instruction.
void RemoveOperand(unsigned i)
Erase an operand from an instruction, leaving it with one fewer operand than it started with...
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
Definition: MachineInstr.h:290
bool isIndirectBranch(QueryType Type=AnyInBundle) const
Return true if this is an indirect branch, such as a branch through a register.
Definition: MachineInstr.h:491
void copyImplicitOps(MachineFunction &MF, const MachineInstr &MI)
Copy implicit register operands from specified instruction to this instruction.
bool isFullCopy() const
Definition: MachineInstr.h:864
bool isBundle() const
Definition: MachineInstr.h:856
bool isIdentityCopy() const
Return true is the instruction is an identity copy.
Definition: MachineInstr.h:879
static MachineInstr * getEmptyKey()
iterator_range< mmo_iterator > memoperands() const
Definition: MachineInstr.h:402
bool isMSInlineAsm() const
Definition: MachineInstr.h:837
MachineBasicBlock * getParent()
Definition: MachineInstr.h:143
void untieRegOperand(unsigned OpIdx)
Break any tie involving OpIdx.
int findInlineAsmFlagIdx(unsigned OpIdx, unsigned *GroupNo=nullptr) const
Find the index of the flag word operand that corresponds to operand OpIdx on an inline asm instructio...
void addMemOperand(MachineFunction &MF, MachineMemOperand *MO)
Add a MachineMemOperand to the machine instruction.
bool isInsideBundle() const
Return true if MI is in a bundle (but not the first MI in a bundle).
Definition: MachineInstr.h:238
bool mayAlias(AliasAnalysis *AA, MachineInstr &Other, bool UseTBAA)
Returns true if this instruction&#39;s memory access aliases the memory access of Other.
bool isDereferenceableInvariantLoad(AliasAnalysis *AA) const
Return true if this load instruction never traps and points to a memory location whose value doesn&#39;t ...
bool allDefsAreDead() const
Return true if all the defs of this instruction are dead.
bool isBranch(QueryType Type=AnyInBundle) const
Returns true if this is a conditional, unconditional, or indirect branch.
Definition: MachineInstr.h:485
void clearRegisterKills(unsigned Reg, const TargetRegisterInfo *RegInfo)
Clear all kill flags affecting Reg.
Flag
These should be considered private to the implementation of the MCInstrDesc class.
Definition: MCInstrDesc.h:121
TargetInstrInfo - Interface to description of machine instruction set.
bool isReturn(QueryType Type=AnyInBundle) const
Definition: MachineInstr.h:457
iterator_range< const_mop_iterator > uses() const
Returns a range that includes all operands that are register uses.
Definition: MachineInstr.h:373
static MachineInstr * getTombstoneKey()
bool mayStore(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly modify memory.
Definition: MachineInstr.h:642
#define P(N)
bool isConvertibleTo3Addr(QueryType Type=IgnoreBundle) const
Return true if this is a 2-address instruction which can be changed into a 3-address instruction if n...
Definition: MachineInstr.h:688
An ilist node that can access its parent list.
Definition: ilist_node.h:257
unsigned const MachineRegisterInfo * MRI
bool getAsmPrinterFlag(CommentFlag Flag) const
Return whether an AsmPrinter flag is set.
Definition: MachineInstr.h:163
unsigned isConstantValuePHI() const
If the specified instruction is a PHI that always merges together the same virtual register...
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:46
bool isCompare(QueryType Type=IgnoreBundle) const
Return true if this instruction is a comparison.
Definition: MachineInstr.h:522
bool readsVirtualRegister(unsigned Reg) const
Return true if the MachineInstr reads the specified virtual register.
Definition: MachineInstr.h:938
bool isPseudo(QueryType Type=IgnoreBundle) const
Return true if this is a pseudo instruction that doesn&#39;t correspond to a real machine instruction...
Definition: MachineInstr.h:453
bool registerDefIsDead(unsigned Reg, const TargetRegisterInfo *TRI=nullptr) const
Returns true if the register is dead in this machine instruction.
Definition: MachineInstr.h:975
void clearRegisterDeads(unsigned Reg)
Clear all dead flags on operands defining register Reg.
bool isBundled() const
Return true if this instruction part of a bundle.
Definition: MachineInstr.h:244
bool isOperandSubregIdx(unsigned OpIdx) const
Return true if operand OpIdx is a subregister index.
Definition: MachineInstr.h:308
uint8_t getFlags() const
Return the MI flags bitvector.
Definition: MachineInstr.h:178
~MachineInstr()=delete
void setFlag(MIFlag Flag)
Set a MI flag.
Definition: MachineInstr.h:188
void clearFlag(MIFlag Flag)
clearFlag - Clear a MI flag.
Definition: MachineInstr.h:199
bool isSelect(QueryType Type=IgnoreBundle) const
Return true if this instruction is a select instruction.
Definition: MachineInstr.h:538
bool hasOneMemOperand() const
Return true if this instruction has exactly one MachineMemOperand.
Definition: MachineInstr.h:407
iterator_range< const_mop_iterator > explicit_uses() const
Definition: MachineInstr.h:381
iterator_range< mop_iterator > defs()
Returns a range over all explicit operands that are register definitions.
Definition: MachineInstr.h:357
bool isEHLabel() const
Definition: MachineInstr.h:801
bool isRegTiedToDefOperand(unsigned UseOpIdx, unsigned *DefOpIdx=nullptr) const
Return true if the use operand of the specified index is tied to a def operand.
bool definesRegister(unsigned Reg, const TargetRegisterInfo *TRI=nullptr) const
Return true if the MachineInstr fully defines the specified register.
Definition: MachineInstr.h:960
std::pair< bool, bool > readsWritesVirtualRegister(unsigned Reg, SmallVectorImpl< unsigned > *Ops=nullptr) const
Return a pair of bools (reads, writes) indicating if this instruction reads or writes Reg...
bool hasComplexRegisterTies() const
Return true when an instruction has tied register that can&#39;t be determined by the instruction&#39;s descr...
bool isRematerializable(QueryType Type=AllInBundle) const
Returns true if this instruction is a candidate for remat.
Definition: MachineInstr.h:716
bool isStackAligningInlineAsm() const
bool isCopy() const
Definition: MachineInstr.h:860
bool isInsertSubregLike(QueryType Type=IgnoreBundle) const
Return true if this instruction behaves the same way as the generic INSERT_SUBREG instructions...
Definition: MachineInstr.h:618
bool isImplicitDef() const
Definition: MachineInstr.h:834
bool isConvergent(QueryType Type=AnyInBundle) const
Return true if this instruction is convergent.
Definition: MachineInstr.h:552
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
static wasm::ValType getType(const TargetRegisterClass *RC)
unsigned getBundleSize() const
Return the number of instructions inside the MI bundle, excluding the bundle header.
unsigned getNumExplicitOperands() const
Returns the number of non-implicit operands.
const DIExpression * getDebugExpression() const
Return the complex address expression referenced by this DBG_VALUE instruction.
EH_LABEL - Represents a label in mid basic block used to track locations needed for debug and excepti...
Definition: ISDOpcodes.h:640
void eraseFromBundle()
Unlink &#39;this&#39; form its basic block and delete it.
iterator_range< mop_iterator > explicit_uses()
Definition: MachineInstr.h:377
iterator_range< T > make_range(T x, T y)
Convenience function for iterating over sub-ranges.
MachineInstr * removeFromBundle()
Unlink this instruction from its basic block and return it without deleting it.
bool isConditionalBranch(QueryType Type=AnyInBundle) const
Return true if this is a branch which may fall through to the next instruction or may transfer contro...
Definition: MachineInstr.h:499
unsigned findTiedOperandIdx(unsigned OpIdx) const
Given the index of a tied register operand, find the operand it is tied to.
InlineAsm::AsmDialect getInlineAsmDialect() const
void setDesc(const MCInstrDesc &tid)
Replace the instruction descriptor (thus opcode) of the current instruction with a new one...
void substituteRegister(unsigned FromReg, unsigned ToReg, unsigned SubIdx, const TargetRegisterInfo &RegInfo)
Replace all occurrences of FromReg with ToReg:SubIdx, properly composing subreg indices where necessa...
void addOperand(MachineFunction &MF, const MachineOperand &Op)
Add the specified operand to the instruction.
mmo_iterator memoperands_begin() const
Access to memory operands of the instruction.
Definition: MachineInstr.h:392
void dropMemRefs()
Clear this MachineInstr&#39;s memory reference descriptor list.
void setFlags(unsigned flags)
Definition: MachineInstr.h:192
bool isDebugValue() const
Definition: MachineInstr.h:819
MachineOperand class - Representation of each machine instruction operand.
bool isInsertSubreg() const
Definition: MachineInstr.h:844
bool hasOrderedMemoryRef() const
Return true if this instruction may have an ordered or volatile memory reference, or if the informati...
bool isVariadic(QueryType Type=IgnoreBundle) const
Return true if this instruction can have a variable number of operands.
Definition: MachineInstr.h:441
iterator_range< const_mop_iterator > explicit_operands() const
Definition: MachineInstr.h:345
int64_t getImm() const
DWARF expression.
unsigned short Opcode
Definition: MCInstrDesc.h:165
void addRegisterDefined(unsigned Reg, const TargetRegisterInfo *RegInfo=nullptr)
We have determined MI defines a register.
A range adaptor for a pair of iterators.
bool hasProperty(unsigned MCFlag, QueryType Type=AnyInBundle) const
Return true if the instruction (or in the case of a bundle, the instructions inside the bundle) has t...
Definition: MachineInstr.h:428
void setDebugLoc(DebugLoc dl)
Replace current source information with new such.
int findRegisterDefOperandIdx(unsigned Reg, bool isDead=false, bool Overlap=false, const TargetRegisterInfo *TRI=nullptr) const
Returns the operand index that is a def of the specified register or -1 if it is not found...
bool readsRegister(unsigned Reg, const TargetRegisterInfo *TRI=nullptr) const
Return true if the MachineInstr reads the specified register.
Definition: MachineInstr.h:930
iterator_range< mop_iterator > implicit_operands()
Definition: MachineInstr.h:349
void addImplicitDefUseOperands(MachineFunction &MF)
Add all implicit def and use operands to this instruction.
bool isUnconditionalBranch(QueryType Type=AnyInBundle) const
Return true if this is a branch which always transfers control flow to some other block...
Definition: MachineInstr.h:507
QueryType
API for querying MachineInstr properties.
Definition: MachineInstr.h:417
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:142
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
bool isRegSequenceLike(QueryType Type=IgnoreBundle) const
Return true if this instruction behaves the same way as the generic REG_SEQUENCE instructions.
Definition: MachineInstr.h:589
const MachineOperand * findRegisterUseOperand(unsigned Reg, bool isKill=false, const TargetRegisterInfo *TRI=nullptr) const
Definition: MachineInstr.h:998
Representation of each machine instruction.
Definition: MachineInstr.h:60
bool killsRegister(unsigned Reg, const TargetRegisterInfo *TRI=nullptr) const
Return true if the MachineInstr kills the specified register.
Definition: MachineInstr.h:951
static cl::opt< bool > UseTBAA("use-tbaa-in-sched-mi", cl::Hidden, cl::init(true), cl::desc("Enable use of TBAA during MI DAG construction"))
std::pair< mmo_iterator, unsigned > mergeMemRefsWith(const MachineInstr &Other)
Return a set of memrefs (begin iterator, size) which conservatively describe the memory behavior of b...
bool canFoldAsLoad(QueryType Type=IgnoreBundle) const
Return true for instructions that can be folded as memory operands in other instructions.
Definition: MachineInstr.h:575
const TargetRegisterClass * getRegClassConstraintEffectForVReg(unsigned Reg, const TargetRegisterClass *CurRC, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI, bool ExploreBundle=false) const
Applies the constraints (def/use) implied by this MI on Reg to the given CurRC.
iterator_range< const_mop_iterator > operands() const
Definition: MachineInstr.h:338
#define I(x, y, z)
Definition: MD5.cpp:58
bool hasExtraSrcRegAllocReq(QueryType Type=AnyInBundle) const
Returns true if this instruction source operands have special register allocation requirements that a...
Definition: MachineInstr.h:739
bool isGCLabel() const
Definition: MachineInstr.h:802
bool isLoadFoldBarrier() const
Returns true if it is illegal to fold a load across this instruction.
bool isKill() const
Definition: MachineInstr.h:833
raw_ostream & operator<<(raw_ostream &OS, const APInt &I)
Definition: APInt.h:2018
bool isRegTiedToUseOperand(unsigned DefOpIdx, unsigned *UseOpIdx=nullptr) const
Given the index of a register def operand, check if the register def is tied to a source operand...
void print(raw_ostream &OS, bool SkipOpers=false, bool SkipDebugLoc=false, const TargetInstrInfo *TII=nullptr) const
Print this MI to OS.
MachineInstr * removeFromParent()
Unlink &#39;this&#39; from the containing basic block, and return it without deleting it. ...
bool hasOptionalDef(QueryType Type=IgnoreBundle) const
Set if this instruction has an optional definition, e.g.
Definition: MachineInstr.h:447
bool isReg() const
isReg - Tests if this is a MO_Register operand.
bool mayLoad(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read memory.
Definition: MachineInstr.h:629
bool memoperands_empty() const
Return true if we don&#39;t have any memory operands which described the the memory access done by this i...
Definition: MachineInstr.h:397
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
bool isIdenticalTo(const MachineInstr &Other, MICheckType Check=CheckDefs) const
Return true if this instruction is identical to Other.
bool usesCustomInsertionHook(QueryType Type=IgnoreBundle) const
Return true if this instruction requires custom insertion support when the DAG scheduler is inserting...
Definition: MachineInstr.h:700
void clearAsmPrinterFlags()
Clear the AsmPrinter bitvector.
Definition: MachineInstr.h:160
void unbundleFromSucc()
Break bundle below this instruction.
mop_iterator operands_begin()
Definition: MachineInstr.h:329
bool isPosition() const
Definition: MachineInstr.h:817
const DILocalVariable * getDebugVariable() const
Return the debug variable referenced by this DBG_VALUE instruction.
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E&#39;s largest value.
Definition: BitmaskEnum.h:81
This class implements an extremely fast bulk output stream that can only output to a stream...
Definition: raw_ostream.h:44
Callbacks do nothing by default in iplist and ilist.
Definition: ilist.h:65
iterator_range< const_mop_iterator > implicit_operands() const
Definition: MachineInstr.h:352
bool addRegisterKilled(unsigned IncomingReg, const TargetRegisterInfo *RegInfo, bool AddIfNotFound=false)
We have determined MI kills a register.
bool hasUnmodeledSideEffects() const
Return true if this instruction has side effects that are not modeled by mayLoad / mayStore...
IRTranslator LLVM IR MI
MachineFunction * getMF()
Definition: MachineInstr.h:151
bool isBarrier(QueryType Type=AnyInBundle) const
Returns true if the specified instruction stops control flow from executing the instruction immediate...
Definition: MachineInstr.h:468
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:49
void setMemRefs(std::pair< mmo_iterator, unsigned > NewMemRefs)
Assign this MachineInstr&#39;s memory reference descriptor list.
void setAsmPrinterFlag(uint8_t Flag)
Set a flag for the AsmPrinter.
Definition: MachineInstr.h:168
CommentFlag
Flags to specify different kinds of comments to output in assembly code.
Definition: MachineInstr.h:70
unsigned getNumMemOperands() const
Return the number of memory operands.
Definition: MachineInstr.h:412
uint64_t getFlags() const
Return flags of this instruction.
Definition: MCInstrDesc.h:228
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:298
bool isIndirectDebugValue() const
A DBG_VALUE is indirect iff the first operand is a register and the second operand is an immediate...
Definition: MachineInstr.h:823
bool isExtractSubreg() const
Definition: MachineInstr.h:868
int findRegisterUseOperandIdx(unsigned Reg, bool isKill=false, const TargetRegisterInfo *TRI=nullptr) const
Returns the operand index that is a use of the specific register or -1 if it is not found...
void setMemRefs(mmo_iterator NewMemRefs, mmo_iterator NewMemRefsEnd)
Assign this MachineInstr&#39;s memory reference descriptor list.
bool getFlag(MIFlag Flag) const
Return whether an MI flag is set.
Definition: MachineInstr.h:183
bool isSafeToMove(AliasAnalysis *AA, bool &SawStore) const
Return true if it is safe to move this instruction.
bool isAsCheapAsAMove(QueryType Type=AllInBundle) const
Returns true if this instruction has the same cost (or less) than a move instruction.
Definition: MachineInstr.h:728
bool isCommutable(QueryType Type=IgnoreBundle) const
Return true if this may be a 2- or 3-address instruction (of the form "X = op Y, Z, ..."), which produces the same result if Y and Z are exchanged.
Definition: MachineInstr.h:670
uint8_t getAsmPrinterFlags() const
Return the asm printer flags bitvector.
Definition: MachineInstr.h:157
bool isNotDuplicable(QueryType Type=AnyInBundle) const
Return true if this instruction cannot be safely duplicated.
Definition: MachineInstr.h:545
mmo_iterator memoperands_end() const
Definition: MachineInstr.h:393
bool hasTrivialDestructor() const
Check whether this has a trivial destructor.
Definition: DebugLoc.h:70
void tieOperands(unsigned DefIdx, unsigned UseIdx)
Add a tie between the register operands at DefIdx and UseIdx.