LLVM  10.0.0svn
MachineInstr.h
Go to the documentation of this file.
1 //===- llvm/CodeGen/MachineInstr.h - MachineInstr class ---------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the declaration of the MachineInstr class, which is the
10 // basic representation for all target dependent machine instructions used by
11 // the back end.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #ifndef LLVM_CODEGEN_MACHINEINSTR_H
16 #define LLVM_CODEGEN_MACHINEINSTR_H
17 
18 #include "llvm/ADT/DenseMapInfo.h"
20 #include "llvm/ADT/ilist.h"
21 #include "llvm/ADT/ilist_node.h"
28 #include "llvm/IR/DebugLoc.h"
29 #include "llvm/IR/InlineAsm.h"
30 #include "llvm/MC/MCInstrDesc.h"
31 #include "llvm/MC/MCSymbol.h"
34 #include <algorithm>
35 #include <cassert>
36 #include <cstdint>
37 #include <utility>
38 
39 namespace llvm {
40 
41 template <typename T> class ArrayRef;
42 class DIExpression;
43 class DILocalVariable;
44 class MachineBasicBlock;
45 class MachineFunction;
46 class MachineMemOperand;
47 class MachineRegisterInfo;
48 class ModuleSlotTracker;
49 class raw_ostream;
50 template <typename T> class SmallVectorImpl;
51 class SmallBitVector;
52 class StringRef;
53 class TargetInstrInfo;
54 class TargetRegisterClass;
55 class TargetRegisterInfo;
56 
57 //===----------------------------------------------------------------------===//
58 /// Representation of each machine instruction.
59 ///
60 /// This class isn't a POD type, but it must have a trivial destructor. When a
61 /// MachineFunction is deleted, all the contained MachineInstrs are deallocated
62 /// without having their destructor called.
63 ///
65  : public ilist_node_with_parent<MachineInstr, MachineBasicBlock,
66  ilist_sentinel_tracking<true>> {
67 public:
69 
70  /// Flags to specify different kinds of comments to output in
71  /// assembly code. These flags carry semantic information not
72  /// otherwise easily derivable from the IR text.
73  ///
74  enum CommentFlag {
75  ReloadReuse = 0x1, // higher bits are reserved for target dep comments.
77  TAsmComments = 0x4 // Target Asm comments should start from this value.
78  };
79 
80  enum MIFlag {
81  NoFlags = 0,
82  FrameSetup = 1 << 0, // Instruction is used as a part of
83  // function frame setup code.
84  FrameDestroy = 1 << 1, // Instruction is used as a part of
85  // function frame destruction code.
86  BundledPred = 1 << 2, // Instruction has bundled predecessors.
87  BundledSucc = 1 << 3, // Instruction has bundled successors.
88  FmNoNans = 1 << 4, // Instruction does not support Fast
89  // math nan values.
90  FmNoInfs = 1 << 5, // Instruction does not support Fast
91  // math infinity values.
92  FmNsz = 1 << 6, // Instruction is not required to retain
93  // signed zero values.
94  FmArcp = 1 << 7, // Instruction supports Fast math
95  // reciprocal approximations.
96  FmContract = 1 << 8, // Instruction supports Fast math
97  // contraction operations like fma.
98  FmAfn = 1 << 9, // Instruction may map to Fast math
99  // instrinsic approximation.
100  FmReassoc = 1 << 10, // Instruction supports Fast math
101  // reassociation of operand order.
102  NoUWrap = 1 << 11, // Instruction supports binary operator
103  // no unsigned wrap.
104  NoSWrap = 1 << 12, // Instruction supports binary operator
105  // no signed wrap.
106  IsExact = 1 << 13, // Instruction supports division is
107  // known to be exact.
108  FPExcept = 1 << 14, // Instruction may raise floating-point
109  // exceptions.
110  };
111 
112 private:
113  const MCInstrDesc *MCID; // Instruction descriptor.
114  MachineBasicBlock *Parent = nullptr; // Pointer to the owning basic block.
115 
116  // Operands are allocated by an ArrayRecycler.
117  MachineOperand *Operands = nullptr; // Pointer to the first operand.
118  unsigned NumOperands = 0; // Number of operands on instruction.
119  using OperandCapacity = ArrayRecycler<MachineOperand>::Capacity;
120  OperandCapacity CapOperands; // Capacity of the Operands array.
121 
122  uint16_t Flags = 0; // Various bits of additional
123  // information about machine
124  // instruction.
125 
126  uint8_t AsmPrinterFlags = 0; // Various bits of information used by
127  // the AsmPrinter to emit helpful
128  // comments. This is *not* semantic
129  // information. Do not use this for
130  // anything other than to convey comment
131  // information to AsmPrinter.
132 
133  /// Internal implementation detail class that provides out-of-line storage for
134  /// extra info used by the machine instruction when this info cannot be stored
135  /// in-line within the instruction itself.
136  ///
137  /// This has to be defined eagerly due to the implementation constraints of
138  /// `PointerSumType` where it is used.
139  class ExtraInfo final
140  : TrailingObjects<ExtraInfo, MachineMemOperand *, MCSymbol *> {
141  public:
142  static ExtraInfo *create(BumpPtrAllocator &Allocator,
144  MCSymbol *PreInstrSymbol = nullptr,
145  MCSymbol *PostInstrSymbol = nullptr) {
146  bool HasPreInstrSymbol = PreInstrSymbol != nullptr;
147  bool HasPostInstrSymbol = PostInstrSymbol != nullptr;
148  auto *Result = new (Allocator.Allocate(
149  totalSizeToAlloc<MachineMemOperand *, MCSymbol *>(
150  MMOs.size(), HasPreInstrSymbol + HasPostInstrSymbol),
151  alignof(ExtraInfo)))
152  ExtraInfo(MMOs.size(), HasPreInstrSymbol, HasPostInstrSymbol);
153 
154  // Copy the actual data into the trailing objects.
155  std::copy(MMOs.begin(), MMOs.end(),
156  Result->getTrailingObjects<MachineMemOperand *>());
157 
158  if (HasPreInstrSymbol)
159  Result->getTrailingObjects<MCSymbol *>()[0] = PreInstrSymbol;
160  if (HasPostInstrSymbol)
161  Result->getTrailingObjects<MCSymbol *>()[HasPreInstrSymbol] =
162  PostInstrSymbol;
163 
164  return Result;
165  }
166 
167  ArrayRef<MachineMemOperand *> getMMOs() const {
168  return makeArrayRef(getTrailingObjects<MachineMemOperand *>(), NumMMOs);
169  }
170 
171  MCSymbol *getPreInstrSymbol() const {
172  return HasPreInstrSymbol ? getTrailingObjects<MCSymbol *>()[0] : nullptr;
173  }
174 
175  MCSymbol *getPostInstrSymbol() const {
176  return HasPostInstrSymbol
177  ? getTrailingObjects<MCSymbol *>()[HasPreInstrSymbol]
178  : nullptr;
179  }
180 
181  private:
182  friend TrailingObjects;
183 
184  // Description of the extra info, used to interpret the actual optional
185  // data appended.
186  //
187  // Note that this is not terribly space optimized. This leaves a great deal
188  // of flexibility to fit more in here later.
189  const int NumMMOs;
190  const bool HasPreInstrSymbol;
191  const bool HasPostInstrSymbol;
192 
193  // Implement the `TrailingObjects` internal API.
194  size_t numTrailingObjects(OverloadToken<MachineMemOperand *>) const {
195  return NumMMOs;
196  }
197  size_t numTrailingObjects(OverloadToken<MCSymbol *>) const {
198  return HasPreInstrSymbol + HasPostInstrSymbol;
199  }
200 
201  // Just a boring constructor to allow us to initialize the sizes. Always use
202  // the `create` routine above.
203  ExtraInfo(int NumMMOs, bool HasPreInstrSymbol, bool HasPostInstrSymbol)
204  : NumMMOs(NumMMOs), HasPreInstrSymbol(HasPreInstrSymbol),
205  HasPostInstrSymbol(HasPostInstrSymbol) {}
206  };
207 
208  /// Enumeration of the kinds of inline extra info available. It is important
209  /// that the `MachineMemOperand` inline kind has a tag value of zero to make
210  /// it accessible as an `ArrayRef`.
211  enum ExtraInfoInlineKinds {
212  EIIK_MMO = 0,
213  EIIK_PreInstrSymbol,
214  EIIK_PostInstrSymbol,
215  EIIK_OutOfLine
216  };
217 
218  // We store extra information about the instruction here. The common case is
219  // expected to be nothing or a single pointer (typically a MMO or a symbol).
220  // We work to optimize this common case by storing it inline here rather than
221  // requiring a separate allocation, but we fall back to an allocation when
222  // multiple pointers are needed.
223  PointerSumType<ExtraInfoInlineKinds,
228  Info;
229 
230  DebugLoc debugLoc; // Source line information.
231 
232  // Intrusive list support
233  friend struct ilist_traits<MachineInstr>;
235  void setParent(MachineBasicBlock *P) { Parent = P; }
236 
237  /// This constructor creates a copy of the given
238  /// MachineInstr in the given MachineFunction.
240 
241  /// This constructor create a MachineInstr and add the implicit operands.
242  /// It reserves space for number of operands specified by
243  /// MCInstrDesc. An explicit DebugLoc is supplied.
245  bool NoImp = false);
246 
247  // MachineInstrs are pool-allocated and owned by MachineFunction.
248  friend class MachineFunction;
249 
250 public:
251  MachineInstr(const MachineInstr &) = delete;
252  MachineInstr &operator=(const MachineInstr &) = delete;
253  // Use MachineFunction::DeleteMachineInstr() instead.
254  ~MachineInstr() = delete;
255 
256  const MachineBasicBlock* getParent() const { return Parent; }
257  MachineBasicBlock* getParent() { return Parent; }
258 
259  /// Return the function that contains the basic block that this instruction
260  /// belongs to.
261  ///
262  /// Note: this is undefined behaviour if the instruction does not have a
263  /// parent.
264  const MachineFunction *getMF() const;
266  return const_cast<MachineFunction *>(
267  static_cast<const MachineInstr *>(this)->getMF());
268  }
269 
270  /// Return the asm printer flags bitvector.
271  uint8_t getAsmPrinterFlags() const { return AsmPrinterFlags; }
272 
273  /// Clear the AsmPrinter bitvector.
274  void clearAsmPrinterFlags() { AsmPrinterFlags = 0; }
275 
276  /// Return whether an AsmPrinter flag is set.
278  return AsmPrinterFlags & Flag;
279  }
280 
281  /// Set a flag for the AsmPrinter.
282  void setAsmPrinterFlag(uint8_t Flag) {
283  AsmPrinterFlags |= Flag;
284  }
285 
286  /// Clear specific AsmPrinter flags.
288  AsmPrinterFlags &= ~Flag;
289  }
290 
291  /// Return the MI flags bitvector.
292  uint16_t getFlags() const {
293  return Flags;
294  }
295 
296  /// Return whether an MI flag is set.
297  bool getFlag(MIFlag Flag) const {
298  return Flags & Flag;
299  }
300 
301  /// Set a MI flag.
303  Flags |= (uint16_t)Flag;
304  }
305 
306  void setFlags(unsigned flags) {
307  // Filter out the automatically maintained flags.
308  unsigned Mask = BundledPred | BundledSucc;
309  Flags = (Flags & Mask) | (flags & ~Mask);
310  }
311 
312  /// clearFlag - Clear a MI flag.
314  Flags &= ~((uint16_t)Flag);
315  }
316 
317  /// Return true if MI is in a bundle (but not the first MI in a bundle).
318  ///
319  /// A bundle looks like this before it's finalized:
320  /// ----------------
321  /// | MI |
322  /// ----------------
323  /// |
324  /// ----------------
325  /// | MI * |
326  /// ----------------
327  /// |
328  /// ----------------
329  /// | MI * |
330  /// ----------------
331  /// In this case, the first MI starts a bundle but is not inside a bundle, the
332  /// next 2 MIs are considered "inside" the bundle.
333  ///
334  /// After a bundle is finalized, it looks like this:
335  /// ----------------
336  /// | Bundle |
337  /// ----------------
338  /// |
339  /// ----------------
340  /// | MI * |
341  /// ----------------
342  /// |
343  /// ----------------
344  /// | MI * |
345  /// ----------------
346  /// |
347  /// ----------------
348  /// | MI * |
349  /// ----------------
350  /// The first instruction has the special opcode "BUNDLE". It's not "inside"
351  /// a bundle, but the next three MIs are.
352  bool isInsideBundle() const {
353  return getFlag(BundledPred);
354  }
355 
356  /// Return true if this instruction part of a bundle. This is true
357  /// if either itself or its following instruction is marked "InsideBundle".
358  bool isBundled() const {
359  return isBundledWithPred() || isBundledWithSucc();
360  }
361 
362  /// Return true if this instruction is part of a bundle, and it is not the
363  /// first instruction in the bundle.
364  bool isBundledWithPred() const { return getFlag(BundledPred); }
365 
366  /// Return true if this instruction is part of a bundle, and it is not the
367  /// last instruction in the bundle.
368  bool isBundledWithSucc() const { return getFlag(BundledSucc); }
369 
370  /// Bundle this instruction with its predecessor. This can be an unbundled
371  /// instruction, or it can be the first instruction in a bundle.
372  void bundleWithPred();
373 
374  /// Bundle this instruction with its successor. This can be an unbundled
375  /// instruction, or it can be the last instruction in a bundle.
376  void bundleWithSucc();
377 
378  /// Break bundle above this instruction.
379  void unbundleFromPred();
380 
381  /// Break bundle below this instruction.
382  void unbundleFromSucc();
383 
384  /// Returns the debug location id of this MachineInstr.
385  const DebugLoc &getDebugLoc() const { return debugLoc; }
386 
387  /// Return the debug variable referenced by
388  /// this DBG_VALUE instruction.
389  const DILocalVariable *getDebugVariable() const;
390 
391  /// Return the complex address expression referenced by
392  /// this DBG_VALUE instruction.
393  const DIExpression *getDebugExpression() const;
394 
395  /// Return the debug label referenced by
396  /// this DBG_LABEL instruction.
397  const DILabel *getDebugLabel() const;
398 
399  /// Emit an error referring to the source location of this instruction.
400  /// This should only be used for inline assembly that is somehow
401  /// impossible to compile. Other errors should have been handled much
402  /// earlier.
403  ///
404  /// If this method returns, the caller should try to recover from the error.
405  void emitError(StringRef Msg) const;
406 
407  /// Returns the target instruction descriptor of this MachineInstr.
408  const MCInstrDesc &getDesc() const { return *MCID; }
409 
410  /// Returns the opcode of this MachineInstr.
411  unsigned getOpcode() const { return MCID->Opcode; }
412 
413  /// Retuns the total number of operands.
414  unsigned getNumOperands() const { return NumOperands; }
415 
416  const MachineOperand& getOperand(unsigned i) const {
417  assert(i < getNumOperands() && "getOperand() out of range!");
418  return Operands[i];
419  }
420  MachineOperand& getOperand(unsigned i) {
421  assert(i < getNumOperands() && "getOperand() out of range!");
422  return Operands[i];
423  }
424 
425  /// Returns the total number of definitions.
426  unsigned getNumDefs() const {
427  return getNumExplicitDefs() + MCID->getNumImplicitDefs();
428  }
429 
430  /// Return true if operand \p OpIdx is a subregister index.
431  bool isOperandSubregIdx(unsigned OpIdx) const {
433  "Expected MO_Immediate operand type.");
434  if (isExtractSubreg() && OpIdx == 2)
435  return true;
436  if (isInsertSubreg() && OpIdx == 3)
437  return true;
438  if (isRegSequence() && OpIdx > 1 && (OpIdx % 2) == 0)
439  return true;
440  if (isSubregToReg() && OpIdx == 3)
441  return true;
442  return false;
443  }
444 
445  /// Returns the number of non-implicit operands.
446  unsigned getNumExplicitOperands() const;
447 
448  /// Returns the number of non-implicit definitions.
449  unsigned getNumExplicitDefs() const;
450 
451  /// iterator/begin/end - Iterate over all operands of a machine instruction.
454 
455  mop_iterator operands_begin() { return Operands; }
456  mop_iterator operands_end() { return Operands + NumOperands; }
457 
458  const_mop_iterator operands_begin() const { return Operands; }
459  const_mop_iterator operands_end() const { return Operands + NumOperands; }
460 
463  }
466  }
468  return make_range(operands_begin(),
470  }
472  return make_range(operands_begin(),
474  }
477  }
480  }
481  /// Returns a range over all explicit operands that are register definitions.
482  /// Implicit definition are not included!
484  return make_range(operands_begin(),
486  }
487  /// \copydoc defs()
489  return make_range(operands_begin(),
491  }
492  /// Returns a range that includes all operands that are register uses.
493  /// This may include unrelated operands which are not register uses.
496  }
497  /// \copydoc uses()
500  }
504  }
508  }
509 
510  /// Returns the number of the operand iterator \p I points to.
512  return I - operands_begin();
513  }
514 
515  /// Access to memory operands of the instruction. If there are none, that does
516  /// not imply anything about whether the function accesses memory. Instead,
517  /// the caller must behave conservatively.
519  if (!Info)
520  return {};
521 
522  if (Info.is<EIIK_MMO>())
523  return makeArrayRef(Info.getAddrOfZeroTagPointer(), 1);
524 
525  if (ExtraInfo *EI = Info.get<EIIK_OutOfLine>())
526  return EI->getMMOs();
527 
528  return {};
529  }
530 
531  /// Access to memory operands of the instruction.
532  ///
533  /// If `memoperands_begin() == memoperands_end()`, that does not imply
534  /// anything about whether the function accesses memory. Instead, the caller
535  /// must behave conservatively.
536  mmo_iterator memoperands_begin() const { return memoperands().begin(); }
537 
538  /// Access to memory operands of the instruction.
539  ///
540  /// If `memoperands_begin() == memoperands_end()`, that does not imply
541  /// anything about whether the function accesses memory. Instead, the caller
542  /// must behave conservatively.
543  mmo_iterator memoperands_end() const { return memoperands().end(); }
544 
545  /// Return true if we don't have any memory operands which described the
546  /// memory access done by this instruction. If this is true, calling code
547  /// must be conservative.
548  bool memoperands_empty() const { return memoperands().empty(); }
549 
550  /// Return true if this instruction has exactly one MachineMemOperand.
551  bool hasOneMemOperand() const { return memoperands().size() == 1; }
552 
553  /// Return the number of memory operands.
554  unsigned getNumMemOperands() const { return memoperands().size(); }
555 
556  /// Helper to extract a pre-instruction symbol if one has been added.
558  if (!Info)
559  return nullptr;
560  if (MCSymbol *S = Info.get<EIIK_PreInstrSymbol>())
561  return S;
562  if (ExtraInfo *EI = Info.get<EIIK_OutOfLine>())
563  return EI->getPreInstrSymbol();
564 
565  return nullptr;
566  }
567 
568  /// Helper to extract a post-instruction symbol if one has been added.
570  if (!Info)
571  return nullptr;
572  if (MCSymbol *S = Info.get<EIIK_PostInstrSymbol>())
573  return S;
574  if (ExtraInfo *EI = Info.get<EIIK_OutOfLine>())
575  return EI->getPostInstrSymbol();
576 
577  return nullptr;
578  }
579 
580  /// API for querying MachineInstr properties. They are the same as MCInstrDesc
581  /// queries but they are bundle aware.
582 
583  enum QueryType {
584  IgnoreBundle, // Ignore bundles
585  AnyInBundle, // Return true if any instruction in bundle has property
586  AllInBundle // Return true if all instructions in bundle have property
587  };
588 
589  /// Return true if the instruction (or in the case of a bundle,
590  /// the instructions inside the bundle) has the specified property.
591  /// The first argument is the property being queried.
592  /// The second argument indicates whether the query should look inside
593  /// instruction bundles.
594  bool hasProperty(unsigned MCFlag, QueryType Type = AnyInBundle) const {
595  assert(MCFlag < 64 &&
596  "MCFlag out of range for bit mask in getFlags/hasPropertyInBundle.");
597  // Inline the fast path for unbundled or bundle-internal instructions.
598  if (Type == IgnoreBundle || !isBundled() || isBundledWithPred())
599  return getDesc().getFlags() & (1ULL << MCFlag);
600 
601  // If this is the first instruction in a bundle, take the slow path.
602  return hasPropertyInBundle(1ULL << MCFlag, Type);
603  }
604 
605  /// Return true if this instruction can have a variable number of operands.
606  /// In this case, the variable operands will be after the normal
607  /// operands but before the implicit definitions and uses (if any are
608  /// present).
611  }
612 
613  /// Set if this instruction has an optional definition, e.g.
614  /// ARM instructions which can set condition code if 's' bit is set.
617  }
618 
619  /// Return true if this is a pseudo instruction that doesn't
620  /// correspond to a real machine instruction.
622  return hasProperty(MCID::Pseudo, Type);
623  }
624 
626  return hasProperty(MCID::Return, Type);
627  }
628 
629  /// Return true if this is an instruction that marks the end of an EH scope,
630  /// i.e., a catchpad or a cleanuppad instruction.
633  }
634 
636  return hasProperty(MCID::Call, Type);
637  }
638 
639  /// Returns true if the specified instruction stops control flow
640  /// from executing the instruction immediately following it. Examples include
641  /// unconditional branches and return instructions.
643  return hasProperty(MCID::Barrier, Type);
644  }
645 
646  /// Returns true if this instruction part of the terminator for a basic block.
647  /// Typically this is things like return and branch instructions.
648  ///
649  /// Various passes use this to insert code into the bottom of a basic block,
650  /// but before control flow occurs.
653  }
654 
655  /// Returns true if this is a conditional, unconditional, or indirect branch.
656  /// Predicates below can be used to discriminate between
657  /// these cases, and the TargetInstrInfo::AnalyzeBranch method can be used to
658  /// get more information.
660  return hasProperty(MCID::Branch, Type);
661  }
662 
663  /// Return true if this is an indirect branch, such as a
664  /// branch through a register.
667  }
668 
669  /// Return true if this is a branch which may fall
670  /// through to the next instruction or may transfer control flow to some other
671  /// block. The TargetInstrInfo::AnalyzeBranch method can be used to get more
672  /// information about this branch.
675  }
676 
677  /// Return true if this is a branch which always
678  /// transfers control flow to some other block. The
679  /// TargetInstrInfo::AnalyzeBranch method can be used to get more information
680  /// about this branch.
683  }
684 
685  /// Return true if this instruction has a predicate operand that
686  /// controls execution. It may be set to 'always', or may be set to other
687  /// values. There are various methods in TargetInstrInfo that can be used to
688  /// control and modify the predicate in this instruction.
690  // If it's a bundle than all bundled instructions must be predicable for this
691  // to return true.
693  }
694 
695  /// Return true if this instruction is a comparison.
697  return hasProperty(MCID::Compare, Type);
698  }
699 
700  /// Return true if this instruction is a move immediate
701  /// (including conditional moves) instruction.
703  return hasProperty(MCID::MoveImm, Type);
704  }
705 
706  /// Return true if this instruction is a register move.
707  /// (including moving values from subreg to reg)
709  return hasProperty(MCID::MoveReg, Type);
710  }
711 
712  /// Return true if this instruction is a bitcast instruction.
714  return hasProperty(MCID::Bitcast, Type);
715  }
716 
717  /// Return true if this instruction is a select instruction.
719  return hasProperty(MCID::Select, Type);
720  }
721 
722  /// Return true if this instruction cannot be safely duplicated.
723  /// For example, if the instruction has a unique labels attached
724  /// to it, duplicating it would cause multiple definition errors.
727  }
728 
729  /// Return true if this instruction is convergent.
730  /// Convergent instructions can not be made control-dependent on any
731  /// additional values.
733  if (isInlineAsm()) {
734  unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
735  if (ExtraInfo & InlineAsm::Extra_IsConvergent)
736  return true;
737  }
739  }
740 
741  /// Returns true if the specified instruction has a delay slot
742  /// which must be filled by the code generator.
745  }
746 
747  /// Return true for instructions that can be folded as
748  /// memory operands in other instructions. The most common use for this
749  /// is instructions that are simple loads from memory that don't modify
750  /// the loaded value in any way, but it can also be used for instructions
751  /// that can be expressed as constant-pool loads, such as V_SETALLONES
752  /// on x86, to allow them to be folded when it is beneficial.
753  /// This should only be set on instructions that return a value in their
754  /// only virtual register definition.
757  }
758 
759  /// Return true if this instruction behaves
760  /// the same way as the generic REG_SEQUENCE instructions.
761  /// E.g., on ARM,
762  /// dX VMOVDRR rY, rZ
763  /// is equivalent to
764  /// dX = REG_SEQUENCE rY, ssub_0, rZ, ssub_1.
765  ///
766  /// Note that for the optimizers to be able to take advantage of
767  /// this property, TargetInstrInfo::getRegSequenceLikeInputs has to be
768  /// override accordingly.
771  }
772 
773  /// Return true if this instruction behaves
774  /// the same way as the generic EXTRACT_SUBREG instructions.
775  /// E.g., on ARM,
776  /// rX, rY VMOVRRD dZ
777  /// is equivalent to two EXTRACT_SUBREG:
778  /// rX = EXTRACT_SUBREG dZ, ssub_0
779  /// rY = EXTRACT_SUBREG dZ, ssub_1
780  ///
781  /// Note that for the optimizers to be able to take advantage of
782  /// this property, TargetInstrInfo::getExtractSubregLikeInputs has to be
783  /// override accordingly.
786  }
787 
788  /// Return true if this instruction behaves
789  /// the same way as the generic INSERT_SUBREG instructions.
790  /// E.g., on ARM,
791  /// dX = VSETLNi32 dY, rZ, Imm
792  /// is equivalent to a INSERT_SUBREG:
793  /// dX = INSERT_SUBREG dY, rZ, translateImmToSubIdx(Imm)
794  ///
795  /// Note that for the optimizers to be able to take advantage of
796  /// this property, TargetInstrInfo::getInsertSubregLikeInputs has to be
797  /// override accordingly.
800  }
801 
802  //===--------------------------------------------------------------------===//
803  // Side Effect Analysis
804  //===--------------------------------------------------------------------===//
805 
806  /// Return true if this instruction could possibly read memory.
807  /// Instructions with this flag set are not necessarily simple load
808  /// instructions, they may load a value and modify it, for example.
810  if (isInlineAsm()) {
811  unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
812  if (ExtraInfo & InlineAsm::Extra_MayLoad)
813  return true;
814  }
815  return hasProperty(MCID::MayLoad, Type);
816  }
817 
818  /// Return true if this instruction could possibly modify memory.
819  /// Instructions with this flag set are not necessarily simple store
820  /// instructions, they may store a modified value based on their operands, or
821  /// may not actually modify anything, for example.
823  if (isInlineAsm()) {
824  unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
825  if (ExtraInfo & InlineAsm::Extra_MayStore)
826  return true;
827  }
829  }
830 
831  /// Return true if this instruction could possibly read or modify memory.
833  return mayLoad(Type) || mayStore(Type);
834  }
835 
836  /// Return true if this instruction could possibly raise a floating-point
837  /// exception. This is the case if the instruction is a floating-point
838  /// instruction that can in principle raise an exception, as indicated
839  /// by the MCID::MayRaiseFPException property, *and* at the same time,
840  /// the instruction is used in a context where we expect floating-point
841  /// exceptions might be enabled, as indicated by the FPExcept MI flag.
842  bool mayRaiseFPException() const {
844  getFlag(MachineInstr::MIFlag::FPExcept);
845  }
846 
847  //===--------------------------------------------------------------------===//
848  // Flags that indicate whether an instruction can be modified by a method.
849  //===--------------------------------------------------------------------===//
850 
851  /// Return true if this may be a 2- or 3-address
852  /// instruction (of the form "X = op Y, Z, ..."), which produces the same
853  /// result if Y and Z are exchanged. If this flag is set, then the
854  /// TargetInstrInfo::commuteInstruction method may be used to hack on the
855  /// instruction.
856  ///
857  /// Note that this flag may be set on instructions that are only commutable
858  /// sometimes. In these cases, the call to commuteInstruction will fail.
859  /// Also note that some instructions require non-trivial modification to
860  /// commute them.
863  }
864 
865  /// Return true if this is a 2-address instruction
866  /// which can be changed into a 3-address instruction if needed. Doing this
867  /// transformation can be profitable in the register allocator, because it
868  /// means that the instruction can use a 2-address form if possible, but
869  /// degrade into a less efficient form if the source and dest register cannot
870  /// be assigned to the same register. For example, this allows the x86
871  /// backend to turn a "shl reg, 3" instruction into an LEA instruction, which
872  /// is the same speed as the shift but has bigger code size.
873  ///
874  /// If this returns true, then the target must implement the
875  /// TargetInstrInfo::convertToThreeAddress method for this instruction, which
876  /// is allowed to fail if the transformation isn't valid for this specific
877  /// instruction (e.g. shl reg, 4 on x86).
878  ///
881  }
882 
883  /// Return true if this instruction requires
884  /// custom insertion support when the DAG scheduler is inserting it into a
885  /// machine basic block. If this is true for the instruction, it basically
886  /// means that it is a pseudo instruction used at SelectionDAG time that is
887  /// expanded out into magic code by the target when MachineInstrs are formed.
888  ///
889  /// If this is true, the TargetLoweringInfo::InsertAtEndOfBasicBlock method
890  /// is used to insert this into the MachineBasicBlock.
893  }
894 
895  /// Return true if this instruction requires *adjustment*
896  /// after instruction selection by calling a target hook. For example, this
897  /// can be used to fill in ARM 's' optional operand depending on whether
898  /// the conditional flag register is used.
901  }
902 
903  /// Returns true if this instruction is a candidate for remat.
904  /// This flag is deprecated, please don't use it anymore. If this
905  /// flag is set, the isReallyTriviallyReMaterializable() method is called to
906  /// verify the instruction is really rematable.
908  // It's only possible to re-mat a bundle if all bundled instructions are
909  // re-materializable.
911  }
912 
913  /// Returns true if this instruction has the same cost (or less) than a move
914  /// instruction. This is useful during certain types of optimizations
915  /// (e.g., remat during two-address conversion or machine licm)
916  /// where we would like to remat or hoist the instruction, but not if it costs
917  /// more than moving the instruction into the appropriate register. Note, we
918  /// are not marking copies from and to the same register class with this flag.
920  // Only returns true for a bundle if all bundled instructions are cheap.
922  }
923 
924  /// Returns true if this instruction source operands
925  /// have special register allocation requirements that are not captured by the
926  /// operand register classes. e.g. ARM::STRD's two source registers must be an
927  /// even / odd pair, ARM::STM registers have to be in ascending order.
928  /// Post-register allocation passes should not attempt to change allocations
929  /// for sources of instructions with this flag.
932  }
933 
934  /// Returns true if this instruction def operands
935  /// have special register allocation requirements that are not captured by the
936  /// operand register classes. e.g. ARM::LDRD's two def registers must be an
937  /// even / odd pair, ARM::LDM registers have to be in ascending order.
938  /// Post-register allocation passes should not attempt to change allocations
939  /// for definitions of instructions with this flag.
942  }
943 
944  enum MICheckType {
945  CheckDefs, // Check all operands for equality
946  CheckKillDead, // Check all operands including kill / dead markers
947  IgnoreDefs, // Ignore all definitions
948  IgnoreVRegDefs // Ignore virtual register definitions
949  };
950 
951  /// Return true if this instruction is identical to \p Other.
952  /// Two instructions are identical if they have the same opcode and all their
953  /// operands are identical (with respect to MachineOperand::isIdenticalTo()).
954  /// Note that this means liveness related flags (dead, undef, kill) do not
955  /// affect the notion of identical.
956  bool isIdenticalTo(const MachineInstr &Other,
957  MICheckType Check = CheckDefs) const;
958 
959  /// Unlink 'this' from the containing basic block, and return it without
960  /// deleting it.
961  ///
962  /// This function can not be used on bundled instructions, use
963  /// removeFromBundle() to remove individual instructions from a bundle.
965 
966  /// Unlink this instruction from its basic block and return it without
967  /// deleting it.
968  ///
969  /// If the instruction is part of a bundle, the other instructions in the
970  /// bundle remain bundled.
972 
973  /// Unlink 'this' from the containing basic block and delete it.
974  ///
975  /// If this instruction is the header of a bundle, the whole bundle is erased.
976  /// This function can not be used for instructions inside a bundle, use
977  /// eraseFromBundle() to erase individual bundled instructions.
978  void eraseFromParent();
979 
980  /// Unlink 'this' from the containing basic block and delete it.
981  ///
982  /// For all definitions mark their uses in DBG_VALUE nodes
983  /// as undefined. Otherwise like eraseFromParent().
985 
986  /// Unlink 'this' form its basic block and delete it.
987  ///
988  /// If the instruction is part of a bundle, the other instructions in the
989  /// bundle remain bundled.
990  void eraseFromBundle();
991 
992  bool isEHLabel() const { return getOpcode() == TargetOpcode::EH_LABEL; }
993  bool isGCLabel() const { return getOpcode() == TargetOpcode::GC_LABEL; }
994  bool isAnnotationLabel() const {
996  }
997 
998  /// Returns true if the MachineInstr represents a label.
999  bool isLabel() const {
1000  return isEHLabel() || isGCLabel() || isAnnotationLabel();
1001  }
1002 
1003  bool isCFIInstruction() const {
1004  return getOpcode() == TargetOpcode::CFI_INSTRUCTION;
1005  }
1006 
1007  // True if the instruction represents a position in the function.
1008  bool isPosition() const { return isLabel() || isCFIInstruction(); }
1009 
1010  bool isDebugValue() const { return getOpcode() == TargetOpcode::DBG_VALUE; }
1011  bool isDebugLabel() const { return getOpcode() == TargetOpcode::DBG_LABEL; }
1012  bool isDebugInstr() const { return isDebugValue() || isDebugLabel(); }
1013 
1014  /// A DBG_VALUE is indirect iff the first operand is a register and
1015  /// the second operand is an immediate.
1016  bool isIndirectDebugValue() const {
1017  return isDebugValue()
1018  && getOperand(0).isReg()
1019  && getOperand(1).isImm();
1020  }
1021 
1022  /// A DBG_VALUE is an entry value iff its debug expression contains the
1023  /// DW_OP_entry_value DWARF operation.
1024  bool isDebugEntryValue() const {
1025  return isDebugValue() && getDebugExpression()->isEntryValue();
1026  }
1027 
1028  /// Return true if the instruction is a debug value which describes a part of
1029  /// a variable as unavailable.
1030  bool isUndefDebugValue() const {
1031  return isDebugValue() && getOperand(0).isReg() && !getOperand(0).getReg().isValid();
1032  }
1033 
1034  bool isPHI() const {
1035  return getOpcode() == TargetOpcode::PHI ||
1036  getOpcode() == TargetOpcode::G_PHI;
1037  }
1038  bool isKill() const { return getOpcode() == TargetOpcode::KILL; }
1039  bool isImplicitDef() const { return getOpcode()==TargetOpcode::IMPLICIT_DEF; }
1040  bool isInlineAsm() const {
1041  return getOpcode() == TargetOpcode::INLINEASM ||
1043  }
1044 
1045  /// FIXME: Seems like a layering violation that the AsmDialect, which is X86
1046  /// specific, be attached to a generic MachineInstr.
1047  bool isMSInlineAsm() const {
1049  }
1050 
1051  bool isStackAligningInlineAsm() const;
1053 
1054  bool isInsertSubreg() const {
1055  return getOpcode() == TargetOpcode::INSERT_SUBREG;
1056  }
1057 
1058  bool isSubregToReg() const {
1059  return getOpcode() == TargetOpcode::SUBREG_TO_REG;
1060  }
1061 
1062  bool isRegSequence() const {
1063  return getOpcode() == TargetOpcode::REG_SEQUENCE;
1064  }
1065 
1066  bool isBundle() const {
1067  return getOpcode() == TargetOpcode::BUNDLE;
1068  }
1069 
1070  bool isCopy() const {
1071  return getOpcode() == TargetOpcode::COPY;
1072  }
1073 
1074  bool isFullCopy() const {
1075  return isCopy() && !getOperand(0).getSubReg() && !getOperand(1).getSubReg();
1076  }
1077 
1078  bool isExtractSubreg() const {
1079  return getOpcode() == TargetOpcode::EXTRACT_SUBREG;
1080  }
1081 
1082  /// Return true if the instruction behaves like a copy.
1083  /// This does not include native copy instructions.
1084  bool isCopyLike() const {
1085  return isCopy() || isSubregToReg();
1086  }
1087 
1088  /// Return true is the instruction is an identity copy.
1089  bool isIdentityCopy() const {
1090  return isCopy() && getOperand(0).getReg() == getOperand(1).getReg() &&
1092  }
1093 
1094  /// Return true if this instruction doesn't produce any output in the form of
1095  /// executable instructions.
1096  bool isMetaInstruction() const {
1097  switch (getOpcode()) {
1098  default:
1099  return false;
1100  case TargetOpcode::IMPLICIT_DEF:
1101  case TargetOpcode::KILL:
1102  case TargetOpcode::CFI_INSTRUCTION:
1104  case TargetOpcode::GC_LABEL:
1105  case TargetOpcode::DBG_VALUE:
1106  case TargetOpcode::DBG_LABEL:
1109  return true;
1110  }
1111  }
1112 
1113  /// Return true if this is a transient instruction that is either very likely
1114  /// to be eliminated during register allocation (such as copy-like
1115  /// instructions), or if this instruction doesn't have an execution-time cost.
1116  bool isTransient() const {
1117  switch (getOpcode()) {
1118  default:
1119  return isMetaInstruction();
1120  // Copy-like instructions are usually eliminated during register allocation.
1121  case TargetOpcode::PHI:
1122  case TargetOpcode::G_PHI:
1123  case TargetOpcode::COPY:
1124  case TargetOpcode::INSERT_SUBREG:
1125  case TargetOpcode::SUBREG_TO_REG:
1126  case TargetOpcode::REG_SEQUENCE:
1127  return true;
1128  }
1129  }
1130 
1131  /// Return the number of instructions inside the MI bundle, excluding the
1132  /// bundle header.
1133  ///
1134  /// This is the number of instructions that MachineBasicBlock::iterator
1135  /// skips, 0 for unbundled instructions.
1136  unsigned getBundleSize() const;
1137 
1138  /// Return true if the MachineInstr reads the specified register.
1139  /// If TargetRegisterInfo is passed, then it also checks if there
1140  /// is a read of a super-register.
1141  /// This does not count partial redefines of virtual registers as reads:
1142  /// %reg1024:6 = OP.
1144  const TargetRegisterInfo *TRI = nullptr) const {
1145  return findRegisterUseOperandIdx(Reg, false, TRI) != -1;
1146  }
1147 
1148  /// Return true if the MachineInstr reads the specified virtual register.
1149  /// Take into account that a partial define is a
1150  /// read-modify-write operation.
1152  return readsWritesVirtualRegister(Reg).first;
1153  }
1154 
1155  /// Return a pair of bools (reads, writes) indicating if this instruction
1156  /// reads or writes Reg. This also considers partial defines.
1157  /// If Ops is not null, all operand indices for Reg are added.
1158  std::pair<bool,bool> readsWritesVirtualRegister(Register Reg,
1159  SmallVectorImpl<unsigned> *Ops = nullptr) const;
1160 
1161  /// Return true if the MachineInstr kills the specified register.
1162  /// If TargetRegisterInfo is passed, then it also checks if there is
1163  /// a kill of a super-register.
1165  const TargetRegisterInfo *TRI = nullptr) const {
1166  return findRegisterUseOperandIdx(Reg, true, TRI) != -1;
1167  }
1168 
1169  /// Return true if the MachineInstr fully defines the specified register.
1170  /// If TargetRegisterInfo is passed, then it also checks
1171  /// if there is a def of a super-register.
1172  /// NOTE: It's ignoring subreg indices on virtual registers.
1174  const TargetRegisterInfo *TRI = nullptr) const {
1175  return findRegisterDefOperandIdx(Reg, false, false, TRI) != -1;
1176  }
1177 
1178  /// Return true if the MachineInstr modifies (fully define or partially
1179  /// define) the specified register.
1180  /// NOTE: It's ignoring subreg indices on virtual registers.
1182  return findRegisterDefOperandIdx(Reg, false, true, TRI) != -1;
1183  }
1184 
1185  /// Returns true if the register is dead in this machine instruction.
1186  /// If TargetRegisterInfo is passed, then it also checks
1187  /// if there is a dead def of a super-register.
1189  const TargetRegisterInfo *TRI = nullptr) const {
1190  return findRegisterDefOperandIdx(Reg, true, false, TRI) != -1;
1191  }
1192 
1193  /// Returns true if the MachineInstr has an implicit-use operand of exactly
1194  /// the given register (not considering sub/super-registers).
1195  bool hasRegisterImplicitUseOperand(Register Reg) const;
1196 
1197  /// Returns the operand index that is a use of the specific register or -1
1198  /// if it is not found. It further tightens the search criteria to a use
1199  /// that kills the register if isKill is true.
1200  int findRegisterUseOperandIdx(Register Reg, bool isKill = false,
1201  const TargetRegisterInfo *TRI = nullptr) const;
1202 
1203  /// Wrapper for findRegisterUseOperandIdx, it returns
1204  /// a pointer to the MachineOperand rather than an index.
1206  const TargetRegisterInfo *TRI = nullptr) {
1207  int Idx = findRegisterUseOperandIdx(Reg, isKill, TRI);
1208  return (Idx == -1) ? nullptr : &getOperand(Idx);
1209  }
1210 
1212  Register Reg, bool isKill = false,
1213  const TargetRegisterInfo *TRI = nullptr) const {
1214  return const_cast<MachineInstr *>(this)->
1216  }
1217 
1218  /// Returns the operand index that is a def of the specified register or
1219  /// -1 if it is not found. If isDead is true, defs that are not dead are
1220  /// skipped. If Overlap is true, then it also looks for defs that merely
1221  /// overlap the specified register. If TargetRegisterInfo is non-null,
1222  /// then it also checks if there is a def of a super-register.
1223  /// This may also return a register mask operand when Overlap is true.
1225  bool isDead = false, bool Overlap = false,
1226  const TargetRegisterInfo *TRI = nullptr) const;
1227 
1228  /// Wrapper for findRegisterDefOperandIdx, it returns
1229  /// a pointer to the MachineOperand rather than an index.
1230  MachineOperand *
1231  findRegisterDefOperand(Register Reg, bool isDead = false,
1232  bool Overlap = false,
1233  const TargetRegisterInfo *TRI = nullptr) {
1234  int Idx = findRegisterDefOperandIdx(Reg, isDead, Overlap, TRI);
1235  return (Idx == -1) ? nullptr : &getOperand(Idx);
1236  }
1237 
1238  const MachineOperand *
1239  findRegisterDefOperand(Register Reg, bool isDead = false,
1240  bool Overlap = false,
1241  const TargetRegisterInfo *TRI = nullptr) const {
1242  return const_cast<MachineInstr *>(this)->findRegisterDefOperand(
1243  Reg, isDead, Overlap, TRI);
1244  }
1245 
1246  /// Find the index of the first operand in the
1247  /// operand list that is used to represent the predicate. It returns -1 if
1248  /// none is found.
1249  int findFirstPredOperandIdx() const;
1250 
1251  /// Find the index of the flag word operand that
1252  /// corresponds to operand OpIdx on an inline asm instruction. Returns -1 if
1253  /// getOperand(OpIdx) does not belong to an inline asm operand group.
1254  ///
1255  /// If GroupNo is not NULL, it will receive the number of the operand group
1256  /// containing OpIdx.
1257  ///
1258  /// The flag operand is an immediate that can be decoded with methods like
1259  /// InlineAsm::hasRegClassConstraint().
1260  int findInlineAsmFlagIdx(unsigned OpIdx, unsigned *GroupNo = nullptr) const;
1261 
1262  /// Compute the static register class constraint for operand OpIdx.
1263  /// For normal instructions, this is derived from the MCInstrDesc.
1264  /// For inline assembly it is derived from the flag words.
1265  ///
1266  /// Returns NULL if the static register class constraint cannot be
1267  /// determined.
1268  const TargetRegisterClass*
1269  getRegClassConstraint(unsigned OpIdx,
1270  const TargetInstrInfo *TII,
1271  const TargetRegisterInfo *TRI) const;
1272 
1273  /// Applies the constraints (def/use) implied by this MI on \p Reg to
1274  /// the given \p CurRC.
1275  /// If \p ExploreBundle is set and MI is part of a bundle, all the
1276  /// instructions inside the bundle will be taken into account. In other words,
1277  /// this method accumulates all the constraints of the operand of this MI and
1278  /// the related bundle if MI is a bundle or inside a bundle.
1279  ///
1280  /// Returns the register class that satisfies both \p CurRC and the
1281  /// constraints set by MI. Returns NULL if such a register class does not
1282  /// exist.
1283  ///
1284  /// \pre CurRC must not be NULL.
1286  Register Reg, const TargetRegisterClass *CurRC,
1287  const TargetInstrInfo *TII, const TargetRegisterInfo *TRI,
1288  bool ExploreBundle = false) const;
1289 
1290  /// Applies the constraints (def/use) implied by the \p OpIdx operand
1291  /// to the given \p CurRC.
1292  ///
1293  /// Returns the register class that satisfies both \p CurRC and the
1294  /// constraints set by \p OpIdx MI. Returns NULL if such a register class
1295  /// does not exist.
1296  ///
1297  /// \pre CurRC must not be NULL.
1298  /// \pre The operand at \p OpIdx must be a register.
1299  const TargetRegisterClass *
1300  getRegClassConstraintEffect(unsigned OpIdx, const TargetRegisterClass *CurRC,
1301  const TargetInstrInfo *TII,
1302  const TargetRegisterInfo *TRI) const;
1303 
1304  /// Add a tie between the register operands at DefIdx and UseIdx.
1305  /// The tie will cause the register allocator to ensure that the two
1306  /// operands are assigned the same physical register.
1307  ///
1308  /// Tied operands are managed automatically for explicit operands in the
1309  /// MCInstrDesc. This method is for exceptional cases like inline asm.
1310  void tieOperands(unsigned DefIdx, unsigned UseIdx);
1311 
1312  /// Given the index of a tied register operand, find the
1313  /// operand it is tied to. Defs are tied to uses and vice versa. Returns the
1314  /// index of the tied operand which must exist.
1315  unsigned findTiedOperandIdx(unsigned OpIdx) const;
1316 
1317  /// Given the index of a register def operand,
1318  /// check if the register def is tied to a source operand, due to either
1319  /// two-address elimination or inline assembly constraints. Returns the
1320  /// first tied use operand index by reference if UseOpIdx is not null.
1321  bool isRegTiedToUseOperand(unsigned DefOpIdx,
1322  unsigned *UseOpIdx = nullptr) const {
1323  const MachineOperand &MO = getOperand(DefOpIdx);
1324  if (!MO.isReg() || !MO.isDef() || !MO.isTied())
1325  return false;
1326  if (UseOpIdx)
1327  *UseOpIdx = findTiedOperandIdx(DefOpIdx);
1328  return true;
1329  }
1330 
1331  /// Return true if the use operand of the specified index is tied to a def
1332  /// operand. It also returns the def operand index by reference if DefOpIdx
1333  /// is not null.
1334  bool isRegTiedToDefOperand(unsigned UseOpIdx,
1335  unsigned *DefOpIdx = nullptr) const {
1336  const MachineOperand &MO = getOperand(UseOpIdx);
1337  if (!MO.isReg() || !MO.isUse() || !MO.isTied())
1338  return false;
1339  if (DefOpIdx)
1340  *DefOpIdx = findTiedOperandIdx(UseOpIdx);
1341  return true;
1342  }
1343 
1344  /// Clears kill flags on all operands.
1345  void clearKillInfo();
1346 
1347  /// Replace all occurrences of FromReg with ToReg:SubIdx,
1348  /// properly composing subreg indices where necessary.
1349  void substituteRegister(Register FromReg, Register ToReg, unsigned SubIdx,
1350  const TargetRegisterInfo &RegInfo);
1351 
1352  /// We have determined MI kills a register. Look for the
1353  /// operand that uses it and mark it as IsKill. If AddIfNotFound is true,
1354  /// add a implicit operand if it's not found. Returns true if the operand
1355  /// exists / is added.
1356  bool addRegisterKilled(Register IncomingReg,
1357  const TargetRegisterInfo *RegInfo,
1358  bool AddIfNotFound = false);
1359 
1360  /// Clear all kill flags affecting Reg. If RegInfo is provided, this includes
1361  /// all aliasing registers.
1362  void clearRegisterKills(Register Reg, const TargetRegisterInfo *RegInfo);
1363 
1364  /// We have determined MI defined a register without a use.
1365  /// Look for the operand that defines it and mark it as IsDead. If
1366  /// AddIfNotFound is true, add a implicit operand if it's not found. Returns
1367  /// true if the operand exists / is added.
1368  bool addRegisterDead(Register Reg, const TargetRegisterInfo *RegInfo,
1369  bool AddIfNotFound = false);
1370 
1371  /// Clear all dead flags on operands defining register @p Reg.
1372  void clearRegisterDeads(Register Reg);
1373 
1374  /// Mark all subregister defs of register @p Reg with the undef flag.
1375  /// This function is used when we determined to have a subregister def in an
1376  /// otherwise undefined super register.
1377  void setRegisterDefReadUndef(Register Reg, bool IsUndef = true);
1378 
1379  /// We have determined MI defines a register. Make sure there is an operand
1380  /// defining Reg.
1381  void addRegisterDefined(Register Reg,
1382  const TargetRegisterInfo *RegInfo = nullptr);
1383 
1384  /// Mark every physreg used by this instruction as
1385  /// dead except those in the UsedRegs list.
1386  ///
1387  /// On instructions with register mask operands, also add implicit-def
1388  /// operands for all registers in UsedRegs.
1390  const TargetRegisterInfo &TRI);
1391 
1392  /// Return true if it is safe to move this instruction. If
1393  /// SawStore is set to true, it means that there is a store (or call) between
1394  /// the instruction's location and its intended destination.
1395  bool isSafeToMove(AliasAnalysis *AA, bool &SawStore) const;
1396 
1397  /// Returns true if this instruction's memory access aliases the memory
1398  /// access of Other.
1399  //
1400  /// Assumes any physical registers used to compute addresses
1401  /// have the same value for both instructions. Returns false if neither
1402  /// instruction writes to memory.
1403  ///
1404  /// @param AA Optional alias analysis, used to compare memory operands.
1405  /// @param Other MachineInstr to check aliasing against.
1406  /// @param UseTBAA Whether to pass TBAA information to alias analysis.
1407  bool mayAlias(AliasAnalysis *AA, const MachineInstr &Other, bool UseTBAA) const;
1408 
1409  /// Return true if this instruction may have an ordered
1410  /// or volatile memory reference, or if the information describing the memory
1411  /// reference is not available. Return false if it is known to have no
1412  /// ordered or volatile memory references.
1413  bool hasOrderedMemoryRef() const;
1414 
1415  /// Return true if this load instruction never traps and points to a memory
1416  /// location whose value doesn't change during the execution of this function.
1417  ///
1418  /// Examples include loading a value from the constant pool or from the
1419  /// argument area of a function (if it does not change). If the instruction
1420  /// does multiple loads, this returns true only if all of the loads are
1421  /// dereferenceable and invariant.
1423 
1424  /// If the specified instruction is a PHI that always merges together the
1425  /// same virtual register, return the register, otherwise return 0.
1426  unsigned isConstantValuePHI() const;
1427 
1428  /// Return true if this instruction has side effects that are not modeled
1429  /// by mayLoad / mayStore, etc.
1430  /// For all instructions, the property is encoded in MCInstrDesc::Flags
1431  /// (see MCInstrDesc::hasUnmodeledSideEffects(). The only exception is
1432  /// INLINEASM instruction, in which case the side effect property is encoded
1433  /// in one of its operands (see InlineAsm::Extra_HasSideEffect).
1434  ///
1435  bool hasUnmodeledSideEffects() const;
1436 
1437  /// Returns true if it is illegal to fold a load across this instruction.
1438  bool isLoadFoldBarrier() const;
1439 
1440  /// Return true if all the defs of this instruction are dead.
1441  bool allDefsAreDead() const;
1442 
1443  /// Return a valid size if the instruction is a spill instruction.
1445 
1446  /// Return a valid size if the instruction is a folded spill instruction.
1448 
1449  /// Return a valid size if the instruction is a restore instruction.
1451 
1452  /// Return a valid size if the instruction is a folded restore instruction.
1454  getFoldedRestoreSize(const TargetInstrInfo *TII) const;
1455 
1456  /// Copy implicit register operands from specified
1457  /// instruction to this instruction.
1458  void copyImplicitOps(MachineFunction &MF, const MachineInstr &MI);
1459 
1460  /// Debugging support
1461  /// @{
1462  /// Determine the generic type to be printed (if needed) on uses and defs.
1463  LLT getTypeToPrint(unsigned OpIdx, SmallBitVector &PrintedTypes,
1464  const MachineRegisterInfo &MRI) const;
1465 
1466  /// Return true when an instruction has tied register that can't be determined
1467  /// by the instruction's descriptor. This is useful for MIR printing, to
1468  /// determine whether we need to print the ties or not.
1469  bool hasComplexRegisterTies() const;
1470 
1471  /// Print this MI to \p OS.
1472  /// Don't print information that can be inferred from other instructions if
1473  /// \p IsStandalone is false. It is usually true when only a fragment of the
1474  /// function is printed.
1475  /// Only print the defs and the opcode if \p SkipOpers is true.
1476  /// Otherwise, also print operands if \p SkipDebugLoc is true.
1477  /// Otherwise, also print the debug loc, with a terminating newline.
1478  /// \p TII is used to print the opcode name. If it's not present, but the
1479  /// MI is in a function, the opcode will be printed using the function's TII.
1480  void print(raw_ostream &OS, bool IsStandalone = true, bool SkipOpers = false,
1481  bool SkipDebugLoc = false, bool AddNewLine = true,
1482  const TargetInstrInfo *TII = nullptr) const;
1483  void print(raw_ostream &OS, ModuleSlotTracker &MST, bool IsStandalone = true,
1484  bool SkipOpers = false, bool SkipDebugLoc = false,
1485  bool AddNewLine = true,
1486  const TargetInstrInfo *TII = nullptr) const;
1487  void dump() const;
1488  /// @}
1489 
1490  //===--------------------------------------------------------------------===//
1491  // Accessors used to build up machine instructions.
1492 
1493  /// Add the specified operand to the instruction. If it is an implicit
1494  /// operand, it is added to the end of the operand list. If it is an
1495  /// explicit operand it is added at the end of the explicit operand list
1496  /// (before the first implicit operand).
1497  ///
1498  /// MF must be the machine function that was used to allocate this
1499  /// instruction.
1500  ///
1501  /// MachineInstrBuilder provides a more convenient interface for creating
1502  /// instructions and adding operands.
1503  void addOperand(MachineFunction &MF, const MachineOperand &Op);
1504 
1505  /// Add an operand without providing an MF reference. This only works for
1506  /// instructions that are inserted in a basic block.
1507  ///
1508  /// MachineInstrBuilder and the two-argument addOperand(MF, MO) should be
1509  /// preferred.
1510  void addOperand(const MachineOperand &Op);
1511 
1512  /// Replace the instruction descriptor (thus opcode) of
1513  /// the current instruction with a new one.
1514  void setDesc(const MCInstrDesc &tid) { MCID = &tid; }
1515 
1516  /// Replace current source information with new such.
1517  /// Avoid using this, the constructor argument is preferable.
1519  debugLoc = std::move(dl);
1520  assert(debugLoc.hasTrivialDestructor() && "Expected trivial destructor");
1521  }
1522 
1523  /// Erase an operand from an instruction, leaving it with one
1524  /// fewer operand than it started with.
1525  void RemoveOperand(unsigned OpNo);
1526 
1527  /// Clear this MachineInstr's memory reference descriptor list. This resets
1528  /// the memrefs to their most conservative state. This should be used only
1529  /// as a last resort since it greatly pessimizes our knowledge of the memory
1530  /// access performed by the instruction.
1531  void dropMemRefs(MachineFunction &MF);
1532 
1533  /// Assign this MachineInstr's memory reference descriptor list.
1534  ///
1535  /// Unlike other methods, this *will* allocate them into a new array
1536  /// associated with the provided `MachineFunction`.
1538 
1539  /// Add a MachineMemOperand to the machine instruction.
1540  /// This function should be used only occasionally. The setMemRefs function
1541  /// is the primary method for setting up a MachineInstr's MemRefs list.
1543 
1544  /// Clone another MachineInstr's memory reference descriptor list and replace
1545  /// ours with it.
1546  ///
1547  /// Note that `*this` may be the incoming MI!
1548  ///
1549  /// Prefer this API whenever possible as it can avoid allocations in common
1550  /// cases.
1551  void cloneMemRefs(MachineFunction &MF, const MachineInstr &MI);
1552 
1553  /// Clone the merge of multiple MachineInstrs' memory reference descriptors
1554  /// list and replace ours with it.
1555  ///
1556  /// Note that `*this` may be one of the incoming MIs!
1557  ///
1558  /// Prefer this API whenever possible as it can avoid allocations in common
1559  /// cases.
1562 
1563  /// Set a symbol that will be emitted just prior to the instruction itself.
1564  ///
1565  /// Setting this to a null pointer will remove any such symbol.
1566  ///
1567  /// FIXME: This is not fully implemented yet.
1569 
1570  /// Set a symbol that will be emitted just after the instruction itself.
1571  ///
1572  /// Setting this to a null pointer will remove any such symbol.
1573  ///
1574  /// FIXME: This is not fully implemented yet.
1575  void setPostInstrSymbol(MachineFunction &MF, MCSymbol *Symbol);
1576 
1577  /// Clone another MachineInstr's pre- and post- instruction symbols and
1578  /// replace ours with it.
1579  void cloneInstrSymbols(MachineFunction &MF, const MachineInstr &MI);
1580 
1581  /// Return the MIFlags which represent both MachineInstrs. This
1582  /// should be used when merging two MachineInstrs into one. This routine does
1583  /// not modify the MIFlags of this MachineInstr.
1584  uint16_t mergeFlagsWith(const MachineInstr& Other) const;
1585 
1586  static uint16_t copyFlagsFromInstruction(const Instruction &I);
1587 
1588  /// Copy all flags to MachineInst MIFlags
1589  void copyIRFlags(const Instruction &I);
1590 
1591  /// Break any tie involving OpIdx.
1592  void untieRegOperand(unsigned OpIdx) {
1593  MachineOperand &MO = getOperand(OpIdx);
1594  if (MO.isReg() && MO.isTied()) {
1595  getOperand(findTiedOperandIdx(OpIdx)).TiedTo = 0;
1596  MO.TiedTo = 0;
1597  }
1598  }
1599 
1600  /// Add all implicit def and use operands to this instruction.
1602 
1603  /// Scan instructions following MI and collect any matching DBG_VALUEs.
1605 
1606  /// Find all DBG_VALUEs immediately following this instruction that point
1607  /// to a register def in this instruction and point them to \p Reg instead.
1609 
1610  /// Returns the Intrinsic::ID for this instruction.
1611  /// \pre Must have an intrinsic ID operand.
1612  unsigned getIntrinsicID() const {
1614  }
1615 
1616 private:
1617  /// If this instruction is embedded into a MachineFunction, return the
1618  /// MachineRegisterInfo object for the current function, otherwise
1619  /// return null.
1620  MachineRegisterInfo *getRegInfo();
1621 
1622  /// Unlink all of the register operands in this instruction from their
1623  /// respective use lists. This requires that the operands already be on their
1624  /// use lists.
1625  void RemoveRegOperandsFromUseLists(MachineRegisterInfo&);
1626 
1627  /// Add all of the register operands in this instruction from their
1628  /// respective use lists. This requires that the operands not be on their
1629  /// use lists yet.
1630  void AddRegOperandsToUseLists(MachineRegisterInfo&);
1631 
1632  /// Slow path for hasProperty when we're dealing with a bundle.
1633  bool hasPropertyInBundle(uint64_t Mask, QueryType Type) const;
1634 
1635  /// Implements the logic of getRegClassConstraintEffectForVReg for the
1636  /// this MI and the given operand index \p OpIdx.
1637  /// If the related operand does not constrained Reg, this returns CurRC.
1638  const TargetRegisterClass *getRegClassConstraintEffectForVRegImpl(
1639  unsigned OpIdx, Register Reg, const TargetRegisterClass *CurRC,
1640  const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const;
1641 };
1642 
1643 /// Special DenseMapInfo traits to compare MachineInstr* by *value* of the
1644 /// instruction rather than by pointer value.
1645 /// The hashing and equality testing functions ignore definitions so this is
1646 /// useful for CSE, etc.
1648  static inline MachineInstr *getEmptyKey() {
1649  return nullptr;
1650  }
1651 
1652  static inline MachineInstr *getTombstoneKey() {
1653  return reinterpret_cast<MachineInstr*>(-1);
1654  }
1655 
1656  static unsigned getHashValue(const MachineInstr* const &MI);
1657 
1658  static bool isEqual(const MachineInstr* const &LHS,
1659  const MachineInstr* const &RHS) {
1660  if (RHS == getEmptyKey() || RHS == getTombstoneKey() ||
1661  LHS == getEmptyKey() || LHS == getTombstoneKey())
1662  return LHS == RHS;
1663  return LHS->isIdenticalTo(*RHS, MachineInstr::IgnoreVRegDefs);
1664  }
1665 };
1666 
1667 //===----------------------------------------------------------------------===//
1668 // Debugging Support
1669 
1671  MI.print(OS);
1672  return OS;
1673 }
1674 
1675 } // end namespace llvm
1676 
1677 #endif // LLVM_CODEGEN_MACHINEINSTR_H
ANNOTATION_LABEL - Represents a mid basic block label used by annotations.
Definition: ISDOpcodes.h:709
void changeDebugValuesDefReg(Register Reg)
Find all DBG_VALUEs immediately following this instruction that point to a register def in this instr...
static bool Check(DecodeStatus &Out, DecodeStatus In)
void bundleWithPred()
Bundle this instruction with its predecessor.
LLT getTypeToPrint(unsigned OpIdx, SmallBitVector &PrintedTypes, const MachineRegisterInfo &MRI) const
Debugging supportDetermine the generic type to be printed (if needed) on uses and defs...
const_iterator end(StringRef path)
Get end iterator over path.
Definition: Path.cpp:233
MachineOperand * findRegisterUseOperand(Register Reg, bool isKill=false, const TargetRegisterInfo *TRI=nullptr)
Wrapper for findRegisterUseOperandIdx, it returns a pointer to the MachineOperand rather than an inde...
mop_iterator operands_end()
Definition: MachineInstr.h:456
bool isDebugLabel() const
bool hasPostISelHook(QueryType Type=IgnoreBundle) const
Return true if this instruction requires adjustment after instruction selection by calling a target h...
Definition: MachineInstr.h:899
bool isEntryValue() const
Check if the expression consists of exactly one entry value operand.
void collectDebugValues(SmallVectorImpl< MachineInstr *> &DbgValues)
Scan instructions following MI and collect any matching DBG_VALUEs.
const_mop_iterator operands_end() const
Definition: MachineInstr.h:459
bool isLabel() const
Returns true if the MachineInstr represents a label.
Definition: MachineInstr.h:999
int findFirstPredOperandIdx() const
Find the index of the first operand in the operand list that is used to represent the predicate...
bool isCall(QueryType Type=AnyInBundle) const
Definition: MachineInstr.h:635
void emitError(StringRef Msg) const
Emit an error referring to the source location of this instruction.
This is a &#39;bitvector&#39; (really, a variable-sized bit array), optimized for the case when the array is ...
unsigned getNumImplicitDefs() const
Return the number of implicit defs this instruct has.
Definition: MCInstrDesc.h:568
const MachineFunction * getMF() const
Return the function that contains the basic block that this instruction belongs to.
This class represents lattice values for constants.
Definition: AllocatorList.h:23
iterator_range< mop_iterator > uses()
Returns a range that includes all operands that are register uses.
Definition: MachineInstr.h:494
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:41
A compile time pair of an integer tag and the pointer-like type which it indexes within a sum type...
iterator_range< mop_iterator > explicit_operands()
Definition: MachineInstr.h:467
bool hasExtraDefRegAllocReq(QueryType Type=AnyInBundle) const
Returns true if this instruction def operands have special register allocation requirements that are ...
Definition: MachineInstr.h:940
iterator begin() const
Definition: ArrayRef.h:136
bool isCFIInstruction() const
bool isBundledWithPred() const
Return true if this instruction is part of a bundle, and it is not the first instruction in the bundl...
Definition: MachineInstr.h:364
bool isExtractSubregLike(QueryType Type=IgnoreBundle) const
Return true if this instruction behaves the same way as the generic EXTRACT_SUBREG instructions...
Definition: MachineInstr.h:784
bool isSubregToReg() const
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:385
This provides a very simple, boring adaptor for a begin and end iterator into a range type...
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:178
unsigned getOperandNo(const_mop_iterator I) const
Returns the number of the operand iterator I points to.
Definition: MachineInstr.h:511
unsigned Reg
bool addRegisterDead(Register Reg, const TargetRegisterInfo *RegInfo, bool AddIfNotFound=false)
We have determined MI defined a register without a use.
int findRegisterDefOperandIdx(Register Reg, bool isDead=false, bool Overlap=false, const TargetRegisterInfo *TRI=nullptr) const
Returns the operand index that is a def of the specified register or -1 if it is not found...
bool hasDelaySlot(QueryType Type=AnyInBundle) const
Returns true if the specified instruction has a delay slot which must be filled by the code generator...
Definition: MachineInstr.h:743
unsigned getSubReg() const
static bool isEqual(const MachineInstr *const &LHS, const MachineInstr *const &RHS)
bool isInlineAsm() const
bool isPredicable(QueryType Type=AllInBundle) const
Return true if this instruction has a predicate operand that controls execution.
Definition: MachineInstr.h:689
bool isAnnotationLabel() const
Definition: MachineInstr.h:994
MachineInstr & operator=(const MachineInstr &)=delete
bool readsVirtualRegister(Register Reg) const
Return true if the MachineInstr reads the specified virtual register.
bool isRegSequence() const
bool mayLoadOrStore(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read or modify memory.
Definition: MachineInstr.h:832
Template traits for intrusive list.
Definition: ilist.h:89
void clearAsmPrinterFlag(CommentFlag Flag)
Clear specific AsmPrinter flags.
Definition: MachineInstr.h:287
Recycle small arrays allocated from a BumpPtrAllocator.
Definition: ArrayRecycler.h:28
bool isTransient() const
Return true if this is a transient instruction that is either very likely to be eliminated during reg...
uint16_t mergeFlagsWith(const MachineInstr &Other) const
Return the MIFlags which represent both MachineInstrs.
unsigned const TargetRegisterInfo * TRI
A debug info location.
Definition: DebugLoc.h:33
Manage lifetime of a slot tracker for printing IR.
MachineOperand & getOperand(unsigned i)
Definition: MachineInstr.h:420
bool isMetaInstruction() const
Return true if this instruction doesn&#39;t produce any output in the form of executable instructions...
iterator_range< mop_iterator > operands()
Definition: MachineInstr.h:461
bool isCopyLike() const
Return true if the instruction behaves like a copy.
bool isPHI() const
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
Special DenseMapInfo traits to compare MachineInstr* by value of the instruction rather than by point...
void clearRegisterDeads(Register Reg)
Clear all dead flags on operands defining register Reg.
bool isMoveImmediate(QueryType Type=IgnoreBundle) const
Return true if this instruction is a move immediate (including conditional moves) instruction...
Definition: MachineInstr.h:702
bool isBitcast(QueryType Type=IgnoreBundle) const
Return true if this instruction is a bitcast instruction.
Definition: MachineInstr.h:713
void clearKillInfo()
Clears kill flags on all operands.
A description of a memory reference used in the backend.
const HexagonInstrInfo * TII
void substituteRegister(Register FromReg, Register ToReg, unsigned SubIdx, const TargetRegisterInfo &RegInfo)
Replace all occurrences of FromReg with ToReg:SubIdx, properly composing subreg indices where necessa...
std::pair< bool, bool > readsWritesVirtualRegister(Register Reg, SmallVectorImpl< unsigned > *Ops=nullptr) const
Return a pair of bools (reads, writes) indicating if this instruction reads or writes Reg...
ArrayRef< T > makeArrayRef(const T &OneElt)
Construct an ArrayRef from a single element.
Definition: ArrayRef.h:450
const TargetRegisterClass * getRegClassConstraint(unsigned OpIdx, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const
Compute the static register class constraint for operand OpIdx.
unsigned getNumOperands() const
Retuns the total number of operands.
Definition: MachineInstr.h:414
bool isBundledWithSucc() const
Return true if this instruction is part of a bundle, and it is not the last instruction in the bundle...
Definition: MachineInstr.h:368
iterator_range< const_mop_iterator > defs() const
Returns a range over all explicit operands that are register definitions.
Definition: MachineInstr.h:488
void eraseFromParent()
Unlink &#39;this&#39; from the containing basic block and delete it.
bool isDebugEntryValue() const
A DBG_VALUE is an entry value iff its debug expression contains the DW_OP_entry_value DWARF operation...
bool isTerminator(QueryType Type=AnyInBundle) const
Returns true if this instruction part of the terminator for a basic block.
Definition: MachineInstr.h:651
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:411
void bundleWithSucc()
Bundle this instruction with its successor.
const TargetRegisterClass * getRegClassConstraintEffect(unsigned OpIdx, const TargetRegisterClass *CurRC, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const
Applies the constraints (def/use) implied by the OpIdx operand to the given CurRC.
ELFYAML::ELF_STO Other
Definition: ELFYAML.cpp:877
INLINEASM - Represents an inline asm block.
Definition: ISDOpcodes.h:695
void eraseFromParentAndMarkDBGValuesForRemoval()
Unlink &#39;this&#39; from the containing basic block and delete it.
Optional< unsigned > getFoldedRestoreSize(const TargetInstrInfo *TII) const
Return a valid size if the instruction is a folded restore instruction.
const_mop_iterator operands_begin() const
Definition: MachineInstr.h:458
void unbundleFromPred()
Break bundle above this instruction.
const TargetRegisterClass * getRegClassConstraintEffectForVReg(Register Reg, const TargetRegisterClass *CurRC, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI, bool ExploreBundle=false) const
Applies the constraints (def/use) implied by this MI on Reg to the given CurRC.
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
Definition: MachineInstr.h:408
bool isIndirectBranch(QueryType Type=AnyInBundle) const
Return true if this is an indirect branch, such as a branch through a register.
Definition: MachineInstr.h:665
void copyImplicitOps(MachineFunction &MF, const MachineInstr &MI)
Copy implicit register operands from specified instruction to this instruction.
bool isEHScopeReturn(QueryType Type=AnyInBundle) const
Return true if this is an instruction that marks the end of an EH scope, i.e., a catchpad or a cleanu...
Definition: MachineInstr.h:631
bool isFullCopy() const
bool isBundle() const
bool mayRaiseFPException() const
Return true if this instruction could possibly raise a floating-point exception.
Definition: MachineInstr.h:842
bool isIdentityCopy() const
Return true is the instruction is an identity copy.
void setRegisterDefReadUndef(Register Reg, bool IsUndef=true)
Mark all subregister defs of register Reg with the undef flag.
bool addRegisterKilled(Register IncomingReg, const TargetRegisterInfo *RegInfo, bool AddIfNotFound=false)
We have determined MI kills a register.
Optional< unsigned > getRestoreSize(const TargetInstrInfo *TII) const
Return a valid size if the instruction is a restore instruction.
static MachineInstr * getEmptyKey()
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:32
bool isMSInlineAsm() const
FIXME: Seems like a layering violation that the AsmDialect, which is X86 specific, be attached to a generic MachineInstr.
MachineBasicBlock * getParent()
Definition: MachineInstr.h:257
void untieRegOperand(unsigned OpIdx)
Break any tie involving OpIdx.
int findInlineAsmFlagIdx(unsigned OpIdx, unsigned *GroupNo=nullptr) const
Find the index of the flag word operand that corresponds to operand OpIdx on an inline asm instructio...
void setPostInstrSymbol(MachineFunction &MF, MCSymbol *Symbol)
Set a symbol that will be emitted just after the instruction itself.
void addMemOperand(MachineFunction &MF, MachineMemOperand *MO)
Add a MachineMemOperand to the machine instruction.
bool isInsideBundle() const
Return true if MI is in a bundle (but not the first MI in a bundle).
Definition: MachineInstr.h:352
bool isDereferenceableInvariantLoad(AliasAnalysis *AA) const
Return true if this load instruction never traps and points to a memory location whose value doesn&#39;t ...
bool allDefsAreDead() const
Return true if all the defs of this instruction are dead.
bool isBranch(QueryType Type=AnyInBundle) const
Returns true if this is a conditional, unconditional, or indirect branch.
Definition: MachineInstr.h:659
MCSymbol * getPreInstrSymbol() const
Helper to extract a pre-instruction symbol if one has been added.
Definition: MachineInstr.h:557
Analysis containing CSE Info
Definition: CSEInfo.cpp:20
void dropMemRefs(MachineFunction &MF)
Clear this MachineInstr&#39;s memory reference descriptor list.
Flag
These should be considered private to the implementation of the MCInstrDesc class.
Definition: MCInstrDesc.h:131
TargetInstrInfo - Interface to description of machine instruction set.
This corresponds to the llvm.lifetime.
Definition: ISDOpcodes.h:877
bool isReturn(QueryType Type=AnyInBundle) const
Definition: MachineInstr.h:625
iterator_range< const_mop_iterator > uses() const
Returns a range that includes all operands that are register uses.
Definition: MachineInstr.h:498
Optional< unsigned > getSpillSize(const TargetInstrInfo *TII) const
Return a valid size if the instruction is a spill instruction.
static MachineInstr * getTombstoneKey()
bool mayStore(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly modify memory.
Definition: MachineInstr.h:822
#define P(N)
bool isConvertibleTo3Addr(QueryType Type=IgnoreBundle) const
Return true if this is a 2-address instruction which can be changed into a 3-address instruction if n...
Definition: MachineInstr.h:879
An ilist node that can access its parent list.
Definition: ilist_node.h:256
unsigned const MachineRegisterInfo * MRI
void cloneInstrSymbols(MachineFunction &MF, const MachineInstr &MI)
Clone another MachineInstr&#39;s pre- and post- instruction symbols and replace ours with it...
bool getAsmPrinterFlag(CommentFlag Flag) const
Return whether an AsmPrinter flag is set.
Definition: MachineInstr.h:277
ArrayRef< MachineMemOperand * > memoperands() const
Access to memory operands of the instruction.
Definition: MachineInstr.h:518
unsigned isConstantValuePHI() const
If the specified instruction is a PHI that always merges together the same virtual register...
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:45
bool isCompare(QueryType Type=IgnoreBundle) const
Return true if this instruction is a comparison.
Definition: MachineInstr.h:696
bool killsRegister(Register Reg, const TargetRegisterInfo *TRI=nullptr) const
Return true if the MachineInstr kills the specified register.
Allocate memory in an ever growing pool, as if by bump-pointer.
Definition: Allocator.h:140
bool isPseudo(QueryType Type=IgnoreBundle) const
Return true if this is a pseudo instruction that doesn&#39;t correspond to a real machine instruction...
Definition: MachineInstr.h:621
bool isBundled() const
Return true if this instruction part of a bundle.
Definition: MachineInstr.h:358
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:148
LLVM_ATTRIBUTE_RETURNS_NONNULL LLVM_ATTRIBUTE_RETURNS_NOALIAS void * Allocate(size_t Size, size_t Alignment)
Allocate space at the specified alignment.
Definition: Allocator.h:214
bool isOperandSubregIdx(unsigned OpIdx) const
Return true if operand OpIdx is a subregister index.
Definition: MachineInstr.h:431
~MachineInstr()=delete
void setFlag(MIFlag Flag)
Set a MI flag.
Definition: MachineInstr.h:302
bool hasRegisterImplicitUseOperand(Register Reg) const
Returns true if the MachineInstr has an implicit-use operand of exactly the given register (not consi...
void clearFlag(MIFlag Flag)
clearFlag - Clear a MI flag.
Definition: MachineInstr.h:313
bool isSelect(QueryType Type=IgnoreBundle) const
Return true if this instruction is a select instruction.
Definition: MachineInstr.h:718
bool hasOneMemOperand() const
Return true if this instruction has exactly one MachineMemOperand.
Definition: MachineInstr.h:551
iterator_range< const_mop_iterator > explicit_uses() const
Definition: MachineInstr.h:505
See the file comment for details on the usage of the TrailingObjects type.
bool definesRegister(Register Reg, const TargetRegisterInfo *TRI=nullptr) const
Return true if the MachineInstr fully defines the specified register.
const DILabel * getDebugLabel() const
Return the debug label referenced by this DBG_LABEL instruction.
iterator_range< mop_iterator > defs()
Returns a range over all explicit operands that are register definitions.
Definition: MachineInstr.h:483
bool isEHLabel() const
Definition: MachineInstr.h:992
bool isRegTiedToDefOperand(unsigned UseOpIdx, unsigned *DefOpIdx=nullptr) const
Return true if the use operand of the specified index is tied to a def operand.
void print(raw_ostream &OS, bool IsStandalone=true, bool SkipOpers=false, bool SkipDebugLoc=false, bool AddNewLine=true, const TargetInstrInfo *TII=nullptr) const
Print this MI to OS.
bool hasComplexRegisterTies() const
Return true when an instruction has tied register that can&#39;t be determined by the instruction&#39;s descr...
const MachineOperand * findRegisterDefOperand(Register Reg, bool isDead=false, bool Overlap=false, const TargetRegisterInfo *TRI=nullptr) const
bool isRematerializable(QueryType Type=AllInBundle) const
Returns true if this instruction is a candidate for remat.
Definition: MachineInstr.h:907
bool isStackAligningInlineAsm() const
bool isCopy() const
bool isInsertSubregLike(QueryType Type=IgnoreBundle) const
Return true if this instruction behaves the same way as the generic INSERT_SUBREG instructions...
Definition: MachineInstr.h:798
bool isImplicitDef() const
bool isConvergent(QueryType Type=AnyInBundle) const
Return true if this instruction is convergent.
Definition: MachineInstr.h:732
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
static wasm::ValType getType(const TargetRegisterClass *RC)
Optional< unsigned > getFoldedSpillSize(const TargetInstrInfo *TII) const
Return a valid size if the instruction is a folded spill instruction.
static uint16_t copyFlagsFromInstruction(const Instruction &I)
bool isDebugInstr() const
unsigned getBundleSize() const
Return the number of instructions inside the MI bundle, excluding the bundle header.
unsigned getNumExplicitOperands() const
Returns the number of non-implicit operands.
const DIExpression * getDebugExpression() const
Return the complex address expression referenced by this DBG_VALUE instruction.
MachineOperand * findRegisterDefOperand(Register Reg, bool isDead=false, bool Overlap=false, const TargetRegisterInfo *TRI=nullptr)
Wrapper for findRegisterDefOperandIdx, it returns a pointer to the MachineOperand rather than an inde...
MCSymbol * getPostInstrSymbol() const
Helper to extract a post-instruction symbol if one has been added.
Definition: MachineInstr.h:569
EH_LABEL - Represents a label in mid basic block used to track locations needed for debug and excepti...
Definition: ISDOpcodes.h:703
void eraseFromBundle()
Unlink &#39;this&#39; form its basic block and delete it.
iterator_range< mop_iterator > explicit_uses()
Definition: MachineInstr.h:501
void copyIRFlags(const Instruction &I)
Copy all flags to MachineInst MIFlags.
iterator_range< T > make_range(T x, T y)
Convenience function for iterating over sub-ranges.
MachineInstr * removeFromBundle()
Unlink this instruction from its basic block and return it without deleting it.
Basic Register Allocator
bool isConditionalBranch(QueryType Type=AnyInBundle) const
Return true if this is a branch which may fall through to the next instruction or may transfer contro...
Definition: MachineInstr.h:673
bool readsRegister(Register Reg, const TargetRegisterInfo *TRI=nullptr) const
Return true if the MachineInstr reads the specified register.
void cloneMemRefs(MachineFunction &MF, const MachineInstr &MI)
Clone another MachineInstr&#39;s memory reference descriptor list and replace ours with it...
unsigned findTiedOperandIdx(unsigned OpIdx) const
Given the index of a tied register operand, find the operand it is tied to.
InlineAsm::AsmDialect getInlineAsmDialect() const
void setDesc(const MCInstrDesc &tid)
Replace the instruction descriptor (thus opcode) of the current instruction with a new one...
void addOperand(MachineFunction &MF, const MachineOperand &Op)
Add the specified operand to the instruction.
mmo_iterator memoperands_begin() const
Access to memory operands of the instruction.
Definition: MachineInstr.h:536
void setFlags(unsigned flags)
Definition: MachineInstr.h:306
bool isDebugValue() const
MachineOperand class - Representation of each machine instruction operand.
bool isInsertSubreg() const
bool modifiesRegister(Register Reg, const TargetRegisterInfo *TRI) const
Return true if the MachineInstr modifies (fully define or partially define) the specified register...
Intrinsic::ID getIntrinsicID() const
iterator end() const
Definition: ArrayRef.h:137
bool hasOrderedMemoryRef() const
Return true if this instruction may have an ordered or volatile memory reference, or if the informati...
bool isVariadic(QueryType Type=IgnoreBundle) const
Return true if this instruction can have a variable number of operands.
Definition: MachineInstr.h:609
iterator_range< const_mop_iterator > explicit_operands() const
Definition: MachineInstr.h:471
int64_t getImm() const
DWARF expression.
unsigned short Opcode
Definition: MCInstrDesc.h:180
A range adaptor for a pair of iterators.
bool hasProperty(unsigned MCFlag, QueryType Type=AnyInBundle) const
Return true if the instruction (or in the case of a bundle, the instructions inside the bundle) has t...
Definition: MachineInstr.h:594
void setDebugLoc(DebugLoc dl)
Replace current source information with new such.
iterator_range< mop_iterator > implicit_operands()
Definition: MachineInstr.h:475
void addImplicitDefUseOperands(MachineFunction &MF)
Add all implicit def and use operands to this instruction.
int findRegisterUseOperandIdx(Register Reg, bool isKill=false, const TargetRegisterInfo *TRI=nullptr) const
Returns the operand index that is a use of the specific register or -1 if it is not found...
bool isUnconditionalBranch(QueryType Type=AnyInBundle) const
Return true if this is a branch which always transfers control flow to some other block...
Definition: MachineInstr.h:681
QueryType
API for querying MachineInstr properties.
Definition: MachineInstr.h:583
A sum type over pointer-like types.
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:256
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
bool isValid() const
Definition: Register.h:115
bool isRegSequenceLike(QueryType Type=IgnoreBundle) const
Return true if this instruction behaves the same way as the generic REG_SEQUENCE instructions.
Definition: MachineInstr.h:769
Representation of each machine instruction.
Definition: MachineInstr.h:64
bool isMoveReg(QueryType Type=IgnoreBundle) const
Return true if this instruction is a register move.
Definition: MachineInstr.h:708
static cl::opt< bool > UseTBAA("use-tbaa-in-sched-mi", cl::Hidden, cl::init(true), cl::desc("Enable use of TBAA during MI DAG construction"))
void setPreInstrSymbol(MachineFunction &MF, MCSymbol *Symbol)
Set a symbol that will be emitted just prior to the instruction itself.
const MachineOperand * findRegisterUseOperand(Register Reg, bool isKill=false, const TargetRegisterInfo *TRI=nullptr) const
bool canFoldAsLoad(QueryType Type=IgnoreBundle) const
Return true for instructions that can be folded as memory operands in other instructions.
Definition: MachineInstr.h:755
void cloneMergedMemRefs(MachineFunction &MF, ArrayRef< const MachineInstr *> MIs)
Clone the merge of multiple MachineInstrs&#39; memory reference descriptors list and replace ours with it...
bool isUndefDebugValue() const
Return true if the instruction is a debug value which describes a part of a variable as unavailable...
iterator_range< const_mop_iterator > operands() const
Definition: MachineInstr.h:464
#define I(x, y, z)
Definition: MD5.cpp:58
bool hasExtraSrcRegAllocReq(QueryType Type=AnyInBundle) const
Returns true if this instruction source operands have special register allocation requirements that a...
Definition: MachineInstr.h:930
bool isGCLabel() const
Definition: MachineInstr.h:993
unsigned getNumDefs() const
Returns the total number of definitions.
Definition: MachineInstr.h:426
void setPhysRegsDeadExcept(ArrayRef< Register > UsedRegs, const TargetRegisterInfo &TRI)
Mark every physreg used by this instruction as dead except those in the UsedRegs list.
bool isLoadFoldBarrier() const
Returns true if it is illegal to fold a load across this instruction.
bool isKill() const
raw_ostream & operator<<(raw_ostream &OS, const APInt &I)
Definition: APInt.h:2045
bool isRegTiedToUseOperand(unsigned DefOpIdx, unsigned *UseOpIdx=nullptr) const
Given the index of a register def operand, check if the register def is tied to a source operand...
MachineInstr * removeFromParent()
Unlink &#39;this&#39; from the containing basic block, and return it without deleting it. ...
bool hasOptionalDef(QueryType Type=IgnoreBundle) const
Set if this instruction has an optional definition, e.g.
Definition: MachineInstr.h:615
unsigned getNumExplicitDefs() const
Returns the number of non-implicit definitions.
bool isReg() const
isReg - Tests if this is a MO_Register operand.
uint16_t getFlags() const
Return the MI flags bitvector.
Definition: MachineInstr.h:292
bool registerDefIsDead(Register Reg, const TargetRegisterInfo *TRI=nullptr) const
Returns true if the register is dead in this machine instruction.
bool mayLoad(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read memory.
Definition: MachineInstr.h:809
bool memoperands_empty() const
Return true if we don&#39;t have any memory operands which described the memory access done by this instr...
Definition: MachineInstr.h:548
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
bool isIdenticalTo(const MachineInstr &Other, MICheckType Check=CheckDefs) const
Return true if this instruction is identical to Other.
bool usesCustomInsertionHook(QueryType Type=IgnoreBundle) const
Return true if this instruction requires custom insertion support when the DAG scheduler is inserting...
Definition: MachineInstr.h:891
void setMemRefs(MachineFunction &MF, ArrayRef< MachineMemOperand *> MemRefs)
Assign this MachineInstr&#39;s memory reference descriptor list.
void clearAsmPrinterFlags()
Clear the AsmPrinter bitvector.
Definition: MachineInstr.h:274
INLINEASM_BR - Terminator version of inline asm. Used by asm-goto.
Definition: ISDOpcodes.h:698
void unbundleFromSucc()
Break bundle below this instruction.
unsigned getIntrinsicID() const
Returns the Intrinsic::ID for this instruction.
mop_iterator operands_begin()
Definition: MachineInstr.h:455
void addRegisterDefined(Register Reg, const TargetRegisterInfo *RegInfo=nullptr)
We have determined MI defines a register.
bool isPosition() const
const DILocalVariable * getDebugVariable() const
Return the debug variable referenced by this DBG_VALUE instruction.
This header defines support for implementing classes that have some trailing object (or arrays of obj...
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E&#39;s largest value.
Definition: BitmaskEnum.h:80
This class implements an extremely fast bulk output stream that can only output to a stream...
Definition: raw_ostream.h:45
Callbacks do nothing by default in iplist and ilist.
Definition: ilist.h:64
iterator_range< const_mop_iterator > implicit_operands() const
Definition: MachineInstr.h:478
bool hasUnmodeledSideEffects() const
Return true if this instruction has side effects that are not modeled by mayLoad / mayStore...
IRTranslator LLVM IR MI
MachineFunction * getMF()
Definition: MachineInstr.h:265
bool isBarrier(QueryType Type=AnyInBundle) const
Returns true if the specified instruction stops control flow from executing the instruction immediate...
Definition: MachineInstr.h:642
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:48
void RemoveOperand(unsigned OpNo)
Erase an operand from an instruction, leaving it with one fewer operand than it started with...
void setAsmPrinterFlag(uint8_t Flag)
Set a flag for the AsmPrinter.
Definition: MachineInstr.h:282
CommentFlag
Flags to specify different kinds of comments to output in assembly code.
Definition: MachineInstr.h:74
Register getReg() const
getReg - Returns the register number.
unsigned getNumMemOperands() const
Return the number of memory operands.
Definition: MachineInstr.h:554
uint64_t getFlags() const
Return flags of this instruction.
Definition: MCInstrDesc.h:243
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:416
OutputIt copy(R &&Range, OutputIt Out)
Definition: STLExtras.h:1229
void clearRegisterKills(Register Reg, const TargetRegisterInfo *RegInfo)
Clear all kill flags affecting Reg.
bool isIndirectDebugValue() const
A DBG_VALUE is indirect iff the first operand is a register and the second operand is an immediate...
bool isExtractSubreg() const
bool getFlag(MIFlag Flag) const
Return whether an MI flag is set.
Definition: MachineInstr.h:297
bool isSafeToMove(AliasAnalysis *AA, bool &SawStore) const
Return true if it is safe to move this instruction.
bool mayAlias(AliasAnalysis *AA, const MachineInstr &Other, bool UseTBAA) const
Returns true if this instruction&#39;s memory access aliases the memory access of Other.
bool isAsCheapAsAMove(QueryType Type=AllInBundle) const
Returns true if this instruction has the same cost (or less) than a move instruction.
Definition: MachineInstr.h:919
bool isCommutable(QueryType Type=IgnoreBundle) const
Return true if this may be a 2- or 3-address instruction (of the form "X = op Y, Z, ..."), which produces the same result if Y and Z are exchanged.
Definition: MachineInstr.h:861
uint8_t getAsmPrinterFlags() const
Return the asm printer flags bitvector.
Definition: MachineInstr.h:271
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
bool isNotDuplicable(QueryType Type=AnyInBundle) const
Return true if this instruction cannot be safely duplicated.
Definition: MachineInstr.h:725
mmo_iterator memoperands_end() const
Access to memory operands of the instruction.
Definition: MachineInstr.h:543
bool hasTrivialDestructor() const
Check whether this has a trivial destructor.
Definition: DebugLoc.h:69
void tieOperands(unsigned DefIdx, unsigned UseIdx)
Add a tie between the register operands at DefIdx and UseIdx.