LLVM  6.0.0svn
Public Types | Public Member Functions | Public Attributes | List of all members
llvm::MCInstrDesc Class Reference

Describe properties that are true of each instruction in the target description file. More...

#include "llvm/MC/MCInstrDesc.h"

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Public Types

using const_opInfo_iterator = const MCOperandInfo *
 

Public Member Functions

int getOperandConstraint (unsigned OpNum, MCOI::OperandConstraint Constraint) const
 Returns the value of the specific constraint if it is set. More...
 
bool getDeprecatedInfo (MCInst &MI, const MCSubtargetInfo &STI, std::string &Info) const
 Returns true if a certain instruction is deprecated and if so returns the reason in Info. More...
 
unsigned getOpcode () const
 Return the opcode number for this descriptor. More...
 
unsigned getNumOperands () const
 Return the number of declared MachineOperands for this MachineInstruction. More...
 
const_opInfo_iterator opInfo_begin () const
 
const_opInfo_iterator opInfo_end () const
 
iterator_range< const_opInfo_iteratoroperands () const
 
unsigned getNumDefs () const
 Return the number of MachineOperands that are register definitions. More...
 
uint64_t getFlags () const
 Return flags of this instruction. More...
 
bool isVariadic () const
 Return true if this instruction can have a variable number of operands. More...
 
bool hasOptionalDef () const
 Set if this instruction has an optional definition, e.g. More...
 
bool isPseudo () const
 Return true if this is a pseudo instruction that doesn't correspond to a real machine instruction. More...
 
bool isReturn () const
 Return true if the instruction is a return. More...
 
bool isAdd () const
 Return true if the instruction is an add instruction. More...
 
bool isCall () const
 Return true if the instruction is a call. More...
 
bool isBarrier () const
 Returns true if the specified instruction stops control flow from executing the instruction immediately following it. More...
 
bool isTerminator () const
 Returns true if this instruction part of the terminator for a basic block. More...
 
bool isBranch () const
 Returns true if this is a conditional, unconditional, or indirect branch. More...
 
bool isIndirectBranch () const
 Return true if this is an indirect branch, such as a branch through a register. More...
 
bool isConditionalBranch () const
 Return true if this is a branch which may fall through to the next instruction or may transfer control flow to some other block. More...
 
bool isUnconditionalBranch () const
 Return true if this is a branch which always transfers control flow to some other block. More...
 
bool mayAffectControlFlow (const MCInst &MI, const MCRegisterInfo &RI) const
 Return true if this is a branch or an instruction which directly writes to the program counter. More...
 
bool isPredicable () const
 Return true if this instruction has a predicate operand that controls execution. More...
 
bool isCompare () const
 Return true if this instruction is a comparison. More...
 
bool isMoveImmediate () const
 Return true if this instruction is a move immediate (including conditional moves) instruction. More...
 
bool isBitcast () const
 Return true if this instruction is a bitcast instruction. More...
 
bool isSelect () const
 Return true if this is a select instruction. More...
 
bool isNotDuplicable () const
 Return true if this instruction cannot be safely duplicated. More...
 
bool hasDelaySlot () const
 Returns true if the specified instruction has a delay slot which must be filled by the code generator. More...
 
bool canFoldAsLoad () const
 Return true for instructions that can be folded as memory operands in other instructions. More...
 
bool isRegSequenceLike () const
 Return true if this instruction behaves the same way as the generic REG_SEQUENCE instructions. More...
 
bool isExtractSubregLike () const
 Return true if this instruction behaves the same way as the generic EXTRACT_SUBREG instructions. More...
 
bool isInsertSubregLike () const
 Return true if this instruction behaves the same way as the generic INSERT_SUBREG instructions. More...
 
bool isConvergent () const
 Return true if this instruction is convergent. More...
 
bool mayLoad () const
 Return true if this instruction could possibly read memory. More...
 
bool mayStore () const
 Return true if this instruction could possibly modify memory. More...
 
bool hasUnmodeledSideEffects () const
 Return true if this instruction has side effects that are not modeled by other flags. More...
 
bool isCommutable () const
 Return true if this may be a 2- or 3-address instruction (of the form "X = op Y, Z, ..."), which produces the same result if Y and Z are exchanged. More...
 
bool isConvertibleTo3Addr () const
 Return true if this is a 2-address instruction which can be changed into a 3-address instruction if needed. More...
 
bool usesCustomInsertionHook () const
 Return true if this instruction requires custom insertion support when the DAG scheduler is inserting it into a machine basic block. More...
 
bool hasPostISelHook () const
 Return true if this instruction requires adjustment after instruction selection by calling a target hook. More...
 
bool isRematerializable () const
 Returns true if this instruction is a candidate for remat. More...
 
bool isAsCheapAsAMove () const
 Returns true if this instruction has the same cost (or less) than a move instruction. More...
 
bool hasExtraSrcRegAllocReq () const
 Returns true if this instruction source operands have special register allocation requirements that are not captured by the operand register classes. More...
 
bool hasExtraDefRegAllocReq () const
 Returns true if this instruction def operands have special register allocation requirements that are not captured by the operand register classes. More...
 
const MCPhysReggetImplicitUses () const
 Return a list of registers that are potentially read by any instance of this machine instruction. More...
 
unsigned getNumImplicitUses () const
 Return the number of implicit uses this instruction has. More...
 
const MCPhysReggetImplicitDefs () const
 Return a list of registers that are potentially written by any instance of this machine instruction. More...
 
unsigned getNumImplicitDefs () const
 Return the number of implicit defs this instruct has. More...
 
bool hasImplicitUseOfPhysReg (unsigned Reg) const
 Return true if this instruction implicitly uses the specified physical register. More...
 
bool hasImplicitDefOfPhysReg (unsigned Reg, const MCRegisterInfo *MRI=nullptr) const
 Return true if this instruction implicitly defines the specified physical register. More...
 
unsigned getSchedClass () const
 Return the scheduling class for this instruction. More...
 
unsigned getSize () const
 Return the number of bytes in the encoding of this instruction, or zero if the encoding size cannot be known from the opcode. More...
 
int findFirstPredOperandIdx () const
 Find the index of the first operand in the operand list that is used to represent the predicate. More...
 

Public Attributes

unsigned short Opcode
 
unsigned short NumOperands
 
unsigned char NumDefs
 
unsigned char Size
 
unsigned short SchedClass
 
uint64_t Flags
 
uint64_t TSFlags
 
const MCPhysRegImplicitUses
 
const MCPhysRegImplicitDefs
 
const MCOperandInfoOpInfo
 
int64_t DeprecatedFeature
 
bool(* ComplexDeprecationInfo )(MCInst &, const MCSubtargetInfo &, std::string &)
 

Detailed Description

Describe properties that are true of each instruction in the target description file.

This captures information about side effects, register use and many other things. There is one instance of this struct for each target instruction class, and the MachineInstr class points to this struct directly to describe itself.

Definition at line 163 of file MCInstrDesc.h.

Member Typedef Documentation

◆ const_opInfo_iterator

Definition at line 212 of file MCInstrDesc.h.

Member Function Documentation

◆ canFoldAsLoad()

bool llvm::MCInstrDesc::canFoldAsLoad ( ) const
inline

Return true for instructions that can be folded as memory operands in other instructions.

The most common use for this is instructions that are simple loads from memory that don't modify the loaded value in any way, but it can also be used for instructions that can be expressed as constant-pool loads, such as V_SETALLONES on x86, to allow them to be folded when it is beneficial. This should only be set on instructions that return a value in their only virtual register definition.

Definition at line 332 of file MCInstrDesc.h.

References llvm::MCID::FoldableAsLoad.

◆ findFirstPredOperandIdx()

int llvm::MCInstrDesc::findFirstPredOperandIdx ( ) const
inline

Find the index of the first operand in the operand list that is used to represent the predicate.

It returns -1 if none is found.

Definition at line 574 of file MCInstrDesc.h.

Referenced by instIsBreakpoint(), and llvm::IsCPSRDead< MCInst >().

◆ getDeprecatedInfo()

bool MCInstrDesc::getDeprecatedInfo ( MCInst MI,
const MCSubtargetInfo STI,
std::string &  Info 
) const

Returns true if a certain instruction is deprecated and if so returns the reason in Info.

Definition at line 22 of file MCInstrDesc.cpp.

References ComplexDeprecationInfo, DeprecatedFeature, and llvm::MCSubtargetInfo::getFeatureBits().

◆ getFlags()

uint64_t llvm::MCInstrDesc::getFlags ( ) const
inline

Return flags of this instruction.

Definition at line 228 of file MCInstrDesc.h.

Referenced by llvm::MachineInstr::hasProperty().

◆ getImplicitDefs()

const MCPhysReg* llvm::MCInstrDesc::getImplicitDefs ( ) const
inline

Return a list of registers that are potentially written by any instance of this machine instruction.

For example, on X86, many instructions implicitly set the flags register. In this case, they are marked as setting the FLAGS. Likewise, many instructions always deposit their result in a physical register. For example, the X86 divide instruction always deposits the quotient and remainder in the EAX/EDX registers. For that instruction, this will return a list containing the EAX/EDX/EFLAGS registers.

This method returns null if the instruction has no implicit defs.

Definition at line 534 of file MCInstrDesc.h.

Referenced by CheckForLiveRegDef(), llvm::InstrEmitter::EmitDbgValue(), getNodeRegMask(), getPhysicalRegisterVT(), HasImplicitCPSRDef(), llvm::rdf::TargetOperandInfo::isFixedReg(), isImplicitOperandIn(), llvm::PPCInstrInfo::optimizeCompareInstr(), and rewritesSort().

◆ getImplicitUses()

const MCPhysReg* llvm::MCInstrDesc::getImplicitUses ( ) const
inline

Return a list of registers that are potentially read by any instance of this machine instruction.

For example, on X86, the "adc" instruction adds two register operands and adds the carry bit in from the flags register. In this case, the instruction is marked as implicitly reading the flags. Likewise, the variable shift instruction on X86 is marked as implicitly reading the 'CL' register, which it always does.

This method returns null if the instruction has no implicit uses.

Definition at line 512 of file MCInstrDesc.h.

Referenced by llvm::InstrEmitter::EmitDbgValue(), llvm::rdf::TargetOperandInfo::isFixedReg(), isImplicitOperandIn(), isPCRel(), llvm::PPCInstrInfo::optimizeCompareInstr(), and raise_relocation_error().

◆ getNumDefs()

unsigned llvm::MCInstrDesc::getNumDefs ( ) const
inline

Return the number of MachineOperands that are register definitions.

Register definitions always occur at the start of the machine operand list. This is the number of "outs" in the .td file, and does not include implicit defs.

Definition at line 225 of file MCInstrDesc.h.

Referenced by AnyAliasLiveIn(), llvm::ARMBaseInstrInfo::breakPartialRegDependency(), canClobberPhysRegDefs(), canEnableCoalescing(), CC_MipsO32_FP64(), CheckForPhysRegDependency(), llvm::TargetInstrInfo::commuteInstructionImpl(), computeBytesPoppedByCalleeForSRet(), countOperands(), llvm::createR600ISelDag(), definesFullReg(), llvm::InstrEmitter::EmitDbgValue(), encodeBitmaskPerm(), llvm::LiveRangeEdit::eraseVirtReg(), llvm::FastISel::fastEmitInst_f(), llvm::FastISel::fastEmitInst_i(), llvm::FastISel::fastEmitInst_r(), llvm::FastISel::fastEmitInst_ri(), llvm::FastISel::fastEmitInst_rii(), llvm::FastISel::fastEmitInst_rr(), llvm::FastISel::fastEmitInst_rri(), llvm::FastISel::fastEmitInst_rrr(), llvm::X86InstrInfo::findCommutedOpIndices(), llvm::TargetInstrInfo::findCommutedOpIndices(), FindStartOfTree(), llvm::X86InstrInfo::foldMemoryOperandImpl(), getCompareCC(), getCopyRewriter(), llvm::ARMBaseInstrInfo::getExtractSubregLikeInputs(), llvm::ARMBaseInstrInfo::getInsertSubregLikeInputs(), llvm::ARMBaseInstrInfo::getLDMVariableDefsSize(), getNodeRegMask(), getPhysicalRegisterVT(), llvm::ARMBaseInstrInfo::getRegSequenceLikeInputs(), llvm::ARMTargetLowering::getSchedulingPreference(), INITIALIZE_PASS(), llvm::ResourcePriorityQueue::initNumRegDefsLeft(), insertPHI(), llvm::IsCPSRDead< MCInst >(), isCrossCopy(), llvm::HexagonInstrInfo::isDependent(), isMulPowOf2(), isNeitherAnorX(), isRegOrImmWithInputMods(), isSExtLoad(), isVirtualRegisterOperand(), matchPair(), mayLoadFromGOTOrConstantPool(), OneUseDominatesOtherUses(), regOverlapsSet(), rewritesSort(), llvm::Localizer::runOnMachineFunction(), and llvm::X86InstrInfo::unfoldMemoryOperand().

◆ getNumImplicitDefs()

unsigned llvm::MCInstrDesc::getNumImplicitDefs ( ) const
inline

Return the number of implicit defs this instruct has.

Definition at line 537 of file MCInstrDesc.h.

Referenced by copyExtraImplicitOps(), llvm::InstrEmitter::EmitDbgValue(), rewritesSort(), and stripExtraCopyOperands().

◆ getNumImplicitUses()

unsigned llvm::MCInstrDesc::getNumImplicitUses ( ) const
inline

◆ getNumOperands()

unsigned llvm::MCInstrDesc::getNumOperands ( ) const
inline

Return the number of declared MachineOperands for this MachineInstruction.

Note that variadic (isVariadic() returns true) instructions may have additional operands at the end of the list, and note that the machine instruction may include implicit register def/uses as well.

Definition at line 210 of file MCInstrDesc.h.

Referenced by addLiveInRegs(), llvm::ARMTargetLowering::AdjustInstrPostInstrSelection(), canClobberPhysRegDefs(), canEnableCoalescing(), llvm::ARMBaseInstrInfo::convertToThreeAddress(), copyExtraImplicitOps(), llvm::MachineInstr::copyImplicitOps(), llvm::PPCInstrInfo::copyPhysReg(), countMCSymbolRefExpr(), countOperands(), llvm::createLanaiDelaySlotFillerPass(), llvm::createR600ISelDag(), llvm::createWebAssemblyMCCodeEmitter(), CriticalPathStep(), definesFullReg(), llvm::InstrEmitter::EmitDbgValue(), Expand2AddrKreg(), Expand2AddrUndef(), llvm::SIInstrInfo::expandPostRAPseudo(), llvm::PPCInstrInfo::FoldImmediate(), llvm::ARMBaseInstrInfo::FoldImmediate(), llvm::X86InstrInfo::foldMemoryOperandImpl(), FuseTwoAddrInst(), llvm::LegalizerInfo::getAction(), getCopyRewriter(), GetDSubRegs(), llvm::ARMBaseInstrInfo::getLDMVariableDefsSize(), getLit64Encoding(), getLSMultipleTransferSize(), getMemoryOpOffset(), llvm::ARMBaseInstrInfo::getNumMicroOps(), llvm::X86II::getOperandBias(), llvm::SIInstrInfo::getOpRegClass(), llvm::TargetInstrInfo::getRegClass(), getTargetMBB(), getX86SSEConditionCode(), HasSecRelSymbolRef(), INITIALIZE_PASS(), isCopy(), llvm::SIInstrInfo::isFoldableCopy(), llvm::AArch64InstrInfo::isFPRCopy(), llvm::AArch64InstrInfo::isGPRCopy(), llvm::AArch64InstrInfo::isGPRZero(), isOperandKill(), isOperandOf(), isRegOrImmWithInputMods(), matchPair(), mayLoadFromGOTOrConstantPool(), llvm::WebAssemblyInstPrinter::printInst(), llvm::WebAssemblyInstPrinter::printOperand(), registerDefinedBetween(), regOverlapsSet(), RemoveUnusedGlue(), llvm::ARMBaseInstrInfo::setExecutionDomain(), stripExtraCopyOperands(), llvm::SIInstrInfo::verifyInstruction(), and VerifyLowRegs().

◆ getOpcode()

unsigned llvm::MCInstrDesc::getOpcode ( ) const
inline

◆ getOperandConstraint()

int llvm::MCInstrDesc::getOperandConstraint ( unsigned  OpNum,
MCOI::OperandConstraint  Constraint 
) const
inline

◆ getSchedClass()

unsigned llvm::MCInstrDesc::getSchedClass ( ) const
inline

Return the scheduling class for this instruction.

The scheduling class is an index into the InstrItineraryData table. This returns zero if there is no known scheduling information for the instruction.

Definition at line 565 of file MCInstrDesc.h.

Referenced by llvm::DFAPacketizer::canReserveResources(), llvm::TargetSchedModel::computeInstrLatency(), llvm::TargetSchedModel::computeInstrRThroughput(), llvm::TargetSchedModel::computeOperandLatency(), llvm::ScoreboardHazardRecognizer::EmitInstruction(), llvm::HexagonInstrInfo::genAllInsnTimingClasses(), llvm::ScoreboardHazardRecognizer::getHazardType(), llvm::PPCInstrInfo::getInstrLatency(), llvm::TargetInstrInfo::getInstrLatency(), llvm::HexagonInstrInfo::getInstrTimingClassLatency(), getItineraryLatency(), getLatency(), llvm::ARMBaseInstrInfo::getLDMVariableDefsSize(), llvm::TargetSchedModel::getNumMicroOps(), llvm::ARMBaseInstrInfo::getNumMicroOps(), llvm::TargetInstrInfo::getNumMicroOps(), getNumMicroOpsSwiftLdSt(), llvm::ARMBaseInstrInfo::getOperandLatency(), llvm::TargetInstrInfo::getOperandLatency(), llvm::HexagonMCInstrInfo::getOtherReservedSlots(), llvm::ARMTargetLowering::getSchedulingPreference(), getUnderlyingObjects(), llvm::HexagonMCInstrInfo::getUnits(), llvm::HexagonInstrInfo::getUnits(), llvm::TargetInstrInfo::hasLowDefLatency(), llvm::HexagonPacketizerList::ignorePseudoInstruction(), llvm::HexagonInstrInfo::isEarlySourceInstr(), llvm::HexagonInstrInfo::isLateResultInstr(), llvm::HexagonInstrInfo::isTC1(), llvm::HexagonInstrInfo::isTC2(), llvm::HexagonInstrInfo::isTC2Early(), llvm::HexagonInstrInfo::isTC4x(), llvm::DFAPacketizer::reserveResources(), and llvm::TargetSchedModel::resolveSchedClass().

◆ getSize()

unsigned llvm::MCInstrDesc::getSize ( ) const
inline

◆ hasDelaySlot()

bool llvm::MCInstrDesc::hasDelaySlot ( ) const
inline

Returns true if the specified instruction has a delay slot which must be filled by the code generator.

Definition at line 323 of file MCInstrDesc.h.

References llvm::MCID::DelaySlot.

Referenced by countMCSymbolRefExpr(), and nextReg().

◆ hasExtraDefRegAllocReq()

bool llvm::MCInstrDesc::hasExtraDefRegAllocReq ( ) const
inline

Returns true if this instruction def operands have special register allocation requirements that are not captured by the operand register classes.

e.g. ARM::LDRD's two def registers must be an even / odd pair, ARM::LDM registers have to be in ascending order. Post-register allocation passes should not attempt to change allocations for definitions of instructions with this flag.

Definition at line 500 of file MCInstrDesc.h.

References llvm::MCID::ExtraDefRegAllocReq.

◆ hasExtraSrcRegAllocReq()

bool llvm::MCInstrDesc::hasExtraSrcRegAllocReq ( ) const
inline

Returns true if this instruction source operands have special register allocation requirements that are not captured by the operand register classes.

e.g. ARM::STRD's two source registers must be an even / odd pair, ARM::STM registers have to be in ascending order. Post-register allocation passes should not attempt to change allocations for sources of instructions with this flag.

Definition at line 490 of file MCInstrDesc.h.

References llvm::MCID::ExtraSrcRegAllocReq.

◆ hasImplicitDefOfPhysReg()

bool MCInstrDesc::hasImplicitDefOfPhysReg ( unsigned  Reg,
const MCRegisterInfo MRI = nullptr 
) const

◆ hasImplicitUseOfPhysReg()

bool llvm::MCInstrDesc::hasImplicitUseOfPhysReg ( unsigned  Reg) const
inline

Return true if this instruction implicitly uses the specified physical register.

Definition at line 548 of file MCInstrDesc.h.

References MRI.

Referenced by llvm::X86InstrInfo::getOutliningType().

◆ hasOptionalDef()

bool llvm::MCInstrDesc::hasOptionalDef ( ) const
inline

Set if this instruction has an optional definition, e.g.

ARM instructions which can set condition code if 's' bit is set.

Definition at line 238 of file MCInstrDesc.h.

References llvm::MCID::HasOptionalDef.

Referenced by llvm::ARMBaseInstrInfo::FoldImmediate(), getNodeRegMask(), getRealVLDOpcode(), and VerifyLowRegs().

◆ hasPostISelHook()

bool llvm::MCInstrDesc::hasPostISelHook ( ) const
inline

Return true if this instruction requires adjustment after instruction selection by calling a target hook.

For example, this can be used to fill in ARM 's' optional operand depending on whether the conditional flag register is used.

Definition at line 461 of file MCInstrDesc.h.

References llvm::MCID::HasPostISelHook.

◆ hasUnmodeledSideEffects()

bool llvm::MCInstrDesc::hasUnmodeledSideEffects ( ) const
inline

Return true if this instruction has side effects that are not modeled by other flags.

This does not return true for instructions whose effects are captured by:

  1. Their operand list and implicit definition/use list. Register use/def info is explicit for instructions.
  2. Memory accesses. Use mayLoad/mayStore.
  3. Calling, branching, returning: use isCall/isReturn/isBranch.

Examples of side effects would be modifying 'invisible' machine state like a control register, flushing a cache, modifying a register invisible to LLVM, etc.

Definition at line 407 of file MCInstrDesc.h.

References llvm::MCID::UnmodeledSideEffects.

◆ isAdd()

bool llvm::MCInstrDesc::isAdd ( ) const
inline

Return true if the instruction is an add instruction.

Definition at line 248 of file MCInstrDesc.h.

References llvm::MCID::Add.

Referenced by llvm::createHexagonHardwareLoops(), and isImmValidForOpcode().

◆ isAsCheapAsAMove()

bool llvm::MCInstrDesc::isAsCheapAsAMove ( ) const
inline

Returns true if this instruction has the same cost (or less) than a move instruction.

This is useful during certain types of optimizations (e.g., remat during two-address conversion or machine licm) where we would like to remat or hoist the instruction, but not if it costs more than moving the instruction into the appropriate register. Note, we are not marking copies from and to the same register class with this flag.

This method could be called by interface TargetInstrInfo::isAsCheapAsAMove for different subtargets.

Definition at line 482 of file MCInstrDesc.h.

References llvm::MCID::CheapAsAMove.

◆ isBarrier()

bool llvm::MCInstrDesc::isBarrier ( ) const
inline

Returns true if the specified instruction stops control flow from executing the instruction immediately following it.

Examples include unconditional branches and return instructions.

Definition at line 256 of file MCInstrDesc.h.

References llvm::MCID::Barrier.

◆ isBitcast()

bool llvm::MCInstrDesc::isBitcast ( ) const
inline

Return true if this instruction is a bitcast instruction.

Definition at line 311 of file MCInstrDesc.h.

References llvm::MCID::Bitcast.

◆ isBranch()

bool llvm::MCInstrDesc::isBranch ( ) const
inline

Returns true if this is a conditional, unconditional, or indirect branch.

Predicates below can be used to discriminate between these cases, and the TargetInstrInfo::AnalyzeBranch method can be used to get more information.

Definition at line 270 of file MCInstrDesc.h.

References llvm::MCID::Branch.

Referenced by llvm::HexagonMCChecker::check(), countMCSymbolRefExpr(), llvm::PPCDispatchGroupSBHazardRecognizer::EmitInstruction(), llvm::HexagonMCInstrInfo::isConstExtended(), llvm::IsCPSRDead< MCInst >(), isPCRel(), mayAffectControlFlow(), and raise_relocation_error().

◆ isCall()

bool llvm::MCInstrDesc::isCall ( ) const
inline

◆ isCommutable()

bool llvm::MCInstrDesc::isCommutable ( ) const
inline

Return true if this may be a 2- or 3-address instruction (of the form "X = op Y, Z, ..."), which produces the same result if Y and Z are exchanged.

If this flag is set, then the TargetInstrInfo::commuteInstruction method may be used to hack on the instruction.

Note that this flag may be set on instructions that are only commutable sometimes. In these cases, the call to commuteInstruction will fail. Also note that some instructions require non-trivial modification to commute them.

Definition at line 425 of file MCInstrDesc.h.

References llvm::MCID::Commutable.

Referenced by llvm::X86InstrInfo::findCommutedOpIndices(), isOperandOf(), and RemoveUnusedGlue().

◆ isCompare()

bool llvm::MCInstrDesc::isCompare ( ) const
inline

Return true if this instruction is a comparison.

Definition at line 304 of file MCInstrDesc.h.

References llvm::MCID::Compare.

Referenced by getNewValueJumpOpcode().

◆ isConditionalBranch()

bool llvm::MCInstrDesc::isConditionalBranch ( ) const
inline

Return true if this is a branch which may fall through to the next instruction or may transfer control flow to some other block.

The TargetInstrInfo::AnalyzeBranch method can be used to get more information about this branch.

Definition at line 280 of file MCInstrDesc.h.

References isBranch().

◆ isConvergent()

bool llvm::MCInstrDesc::isConvergent ( ) const
inline

Return true if this instruction is convergent.

Convergent instructions may not be made control-dependent on any additional values.

Definition at line 378 of file MCInstrDesc.h.

References llvm::MCID::Convergent.

◆ isConvertibleTo3Addr()

bool llvm::MCInstrDesc::isConvertibleTo3Addr ( ) const
inline

Return true if this is a 2-address instruction which can be changed into a 3-address instruction if needed.

Doing this transformation can be profitable in the register allocator, because it means that the instruction can use a 2-address form if possible, but degrade into a less efficient form if the source and dest register cannot be assigned to the same register. For example, this allows the x86 backend to turn a "shl reg, 3" instruction into an LEA instruction, which is the same speed as the shift but has bigger code size.

If this returns true, then the target must implement the TargetInstrInfo::convertToThreeAddress method for this instruction, which is allowed to fail if the transformation isn't valid for this specific instruction (e.g. shl reg, 4 on x86).

Definition at line 441 of file MCInstrDesc.h.

References llvm::MCID::ConvertibleTo3Addr.

◆ isExtractSubregLike()

bool llvm::MCInstrDesc::isExtractSubregLike ( ) const
inline

Return true if this instruction behaves the same way as the generic EXTRACT_SUBREG instructions.

E.g., on ARM, rX, rY VMOVRRD dZ is equivalent to two EXTRACT_SUBREG: rX = EXTRACT_SUBREG dZ, ssub_0 rY = EXTRACT_SUBREG dZ, ssub_1

Note that for the optimizers to be able to take advantage of this property, TargetInstrInfo::getExtractSubregLikeInputs has to be override accordingly.

Definition at line 357 of file MCInstrDesc.h.

References llvm::MCID::ExtractSubreg.

◆ isIndirectBranch()

bool llvm::MCInstrDesc::isIndirectBranch ( ) const
inline

Return true if this is an indirect branch, such as a branch through a register.

Definition at line 274 of file MCInstrDesc.h.

References llvm::MCID::IndirectBranch.

Referenced by llvm::IsCPSRDead< MCInst >(), and mayAffectControlFlow().

◆ isInsertSubregLike()

bool llvm::MCInstrDesc::isInsertSubregLike ( ) const
inline

Return true if this instruction behaves the same way as the generic INSERT_SUBREG instructions.

E.g., on ARM, dX = VSETLNi32 dY, rZ, Imm is equivalent to a INSERT_SUBREG: dX = INSERT_SUBREG dY, rZ, translateImmToSubIdx(Imm)

Note that for the optimizers to be able to take advantage of this property, TargetInstrInfo::getInsertSubregLikeInputs has to be override accordingly.

Definition at line 371 of file MCInstrDesc.h.

References llvm::MCID::InsertSubreg.

◆ isMoveImmediate()

bool llvm::MCInstrDesc::isMoveImmediate ( ) const
inline

Return true if this instruction is a move immediate (including conditional moves) instruction.

Definition at line 308 of file MCInstrDesc.h.

References llvm::MCID::MoveImm.

◆ isNotDuplicable()

bool llvm::MCInstrDesc::isNotDuplicable ( ) const
inline

Return true if this instruction cannot be safely duplicated.

For example, if the instruction has a unique labels attached to it, duplicating it would cause multiple definition errors.

Definition at line 319 of file MCInstrDesc.h.

References llvm::MCID::NotDuplicable.

◆ isPredicable()

bool llvm::MCInstrDesc::isPredicable ( ) const
inline

Return true if this instruction has a predicate operand that controls execution.

It may be set to 'always', or may be set to other values. There are various methods in TargetInstrInfo that can be used to control and modify the predicate in this instruction.

Definition at line 301 of file MCInstrDesc.h.

References llvm::MCID::Predicable.

Referenced by llvm::MachineInstr::findFirstPredOperandIdx(), instIsBreakpoint(), llvm::IsCPSRDead< MCInst >(), llvm::HexagonInstrInfo::isPredicable(), llvm::TargetInstrInfo::isPredicable(), and VerifyLowRegs().

◆ isPseudo()

bool llvm::MCInstrDesc::isPseudo ( ) const
inline

Return true if this is a pseudo instruction that doesn't correspond to a real machine instruction.

Definition at line 242 of file MCInstrDesc.h.

References llvm::MCID::Pseudo.

Referenced by llvm::PPCInstrInfo::FoldImmediate(), and llvm::HexagonMCInstrInfo::isCanon().

◆ isRegSequenceLike()

bool llvm::MCInstrDesc::isRegSequenceLike ( ) const
inline

Return true if this instruction behaves the same way as the generic REG_SEQUENCE instructions.

E.g., on ARM, dX VMOVDRR rY, rZ is equivalent to dX = REG_SEQUENCE rY, ssub_0, rZ, ssub_1.

Note that for the optimizers to be able to take advantage of this property, TargetInstrInfo::getRegSequenceLikeInputs has to be override accordingly.

Definition at line 344 of file MCInstrDesc.h.

References llvm::MCID::RegSequence.

◆ isRematerializable()

bool llvm::MCInstrDesc::isRematerializable ( ) const
inline

Returns true if this instruction is a candidate for remat.

This flag is only used in TargetInstrInfo method isTriviallyRematerializable.

If this flag is set, the isReallyTriviallyReMaterializable() or isReallyTriviallyReMaterializableGeneric methods are called to verify the instruction is really rematable.

Definition at line 469 of file MCInstrDesc.h.

References llvm::MCID::Rematerializable.

Referenced by llvm::TargetInstrInfo::isTriviallyReMaterializable().

◆ isReturn()

bool llvm::MCInstrDesc::isReturn ( ) const
inline

Return true if the instruction is a return.

Definition at line 245 of file MCInstrDesc.h.

References llvm::MCID::Return.

Referenced by llvm::HexagonShuffler::check(), llvm::IsCPSRDead< MCInst >(), mayAffectControlFlow(), and llvm::SelectionDAGISel::runOnMachineFunction().

◆ isSelect()

bool llvm::MCInstrDesc::isSelect ( ) const
inline

Return true if this is a select instruction.

Definition at line 314 of file MCInstrDesc.h.

References llvm::MCID::Select.

Referenced by llvm::TargetInstrInfo::analyzeSelect().

◆ isTerminator()

bool llvm::MCInstrDesc::isTerminator ( ) const
inline

Returns true if this instruction part of the terminator for a basic block.

Typically this is things like return and branch instructions.

Various passes use this to insert code into the bottom of a basic block, but before control flow occurs.

Definition at line 264 of file MCInstrDesc.h.

References llvm::MCID::Terminator.

Referenced by isControlFlow(), llvm::IsCPSRDead< MCInst >(), and llvm::HexagonInstrInfo::isSchedulingBoundary().

◆ isUnconditionalBranch()

bool llvm::MCInstrDesc::isUnconditionalBranch ( ) const
inline

Return true if this is a branch which always transfers control flow to some other block.

The TargetInstrInfo::AnalyzeBranch method can be used to get more information about this branch.

Definition at line 288 of file MCInstrDesc.h.

References isBranch().

◆ isVariadic()

bool llvm::MCInstrDesc::isVariadic ( ) const
inline

Return true if this instruction can have a variable number of operands.

In this case, the variable operands will be after the normal operands but before the implicit definitions and uses (if any are present).

Definition at line 234 of file MCInstrDesc.h.

References llvm::MCID::Variadic.

Referenced by countOperands(), llvm::InstrEmitter::EmitDbgValue(), isUseSafeToFold(), isVirtualRegisterOperand(), llvm::WebAssemblyInstPrinter::printInst(), and llvm::SIInstrInfo::verifyInstruction().

◆ mayAffectControlFlow()

bool MCInstrDesc::mayAffectControlFlow ( const MCInst MI,
const MCRegisterInfo RI 
) const

Return true if this is a branch or an instruction which directly writes to the program counter.

Considered 'may' affect rather than 'does' affect as things like predication are not taken into account.

Definition at line 33 of file MCInstrDesc.cpp.

References llvm::MCInst::getNumOperands(), llvm::MCInst::getOperand(), llvm::MCRegisterInfo::getProgramCounter(), llvm::MCOperand::getReg(), isBranch(), isCall(), isIndirectBranch(), llvm::MCOperand::isReg(), isReturn(), llvm::MCRegisterInfo::isSubRegisterEq(), and NumOperands.

◆ mayLoad()

bool llvm::MCInstrDesc::mayLoad ( ) const
inline

◆ mayStore()

bool llvm::MCInstrDesc::mayStore ( ) const
inline

Return true if this instruction could possibly modify memory.

Instructions with this flag set are not necessarily simple store instructions, they may store a modified value based on their operands, or may not actually modify anything, for example.

Definition at line 393 of file MCInstrDesc.h.

References llvm::MCID::MayStore.

Referenced by llvm::addFrameReference(), buildMUBUFOffsetLoadStore(), llvm::HexagonShuffler::check(), countMCSymbolRefExpr(), llvm::HexagonInstrInfo::getNonExtOpcode(), llvm::ARMBaseInstrInfo::getNumMicroOps(), getPostIncrementOperand(), llvm::HexagonInstrInfo::hasNonExtEquivalent(), llvm::HexagonInstrInfo::isComplex(), isPCRel(), isScaledConstantInRange(), llvm::PPCHazardRecognizer970::PPCHazardRecognizer970(), raise_relocation_error(), readsVCCZ(), rewritesSort(), and llvm::SelectionDAGISel::SelectCodeCommon().

◆ operands()

iterator_range<const_opInfo_iterator> llvm::MCInstrDesc::operands ( ) const
inline

Definition at line 217 of file MCInstrDesc.h.

References llvm::make_range().

◆ opInfo_begin()

const_opInfo_iterator llvm::MCInstrDesc::opInfo_begin ( ) const
inline

Definition at line 214 of file MCInstrDesc.h.

◆ opInfo_end()

const_opInfo_iterator llvm::MCInstrDesc::opInfo_end ( ) const
inline

Definition at line 215 of file MCInstrDesc.h.

◆ usesCustomInsertionHook()

bool llvm::MCInstrDesc::usesCustomInsertionHook ( ) const
inline

Return true if this instruction requires custom insertion support when the DAG scheduler is inserting it into a machine basic block.

If this is true for the instruction, it basically means that it is a pseudo instruction used at SelectionDAG time that is expanded out into magic code by the target when MachineInstrs are formed.

If this is true, the TargetLoweringInfo::InsertAtEndOfBasicBlock method is used to insert this into the MachineBasicBlock.

Definition at line 453 of file MCInstrDesc.h.

References llvm::MCID::UsesCustomInserter.

Member Data Documentation

◆ ComplexDeprecationInfo

bool(* llvm::MCInstrDesc::ComplexDeprecationInfo) (MCInst &, const MCSubtargetInfo &, std::string &)

Definition at line 182 of file MCInstrDesc.h.

Referenced by getDeprecatedInfo().

◆ DeprecatedFeature

int64_t llvm::MCInstrDesc::DeprecatedFeature

Definition at line 178 of file MCInstrDesc.h.

Referenced by getDeprecatedInfo().

◆ Flags

uint64_t llvm::MCInstrDesc::Flags

Definition at line 170 of file MCInstrDesc.h.

◆ ImplicitDefs

const MCPhysReg* llvm::MCInstrDesc::ImplicitDefs

◆ ImplicitUses

const MCPhysReg* llvm::MCInstrDesc::ImplicitUses

◆ NumDefs

unsigned char llvm::MCInstrDesc::NumDefs

◆ NumOperands

unsigned short llvm::MCInstrDesc::NumOperands

◆ Opcode

unsigned short llvm::MCInstrDesc::Opcode

◆ OpInfo

const MCOperandInfo* llvm::MCInstrDesc::OpInfo

◆ SchedClass

unsigned short llvm::MCInstrDesc::SchedClass

Definition at line 169 of file MCInstrDesc.h.

◆ Size

unsigned char llvm::MCInstrDesc::Size

Definition at line 168 of file MCInstrDesc.h.

◆ TSFlags

uint64_t llvm::MCInstrDesc::TSFlags

Definition at line 171 of file MCInstrDesc.h.

Referenced by commuteVPTERNLOG(), llvm::ARMBaseInstrInfo::convertToThreeAddress(), countMCSymbolRefExpr(), llvm::createR600MCCodeEmitter(), llvm::createRISCVMCCodeEmitter(), llvm::createWebAssemblyMCCodeEmitter(), llvm::createX86OptimizeLEAs(), llvm::ARMBaseRegisterInfo::eliminateFrameIndex(), llvm::NVPTXAsmPrinter::emitLineNumberAsDotLoc(), llvm::X86InstrInfo::findCommutedOpIndices(), llvm::X86InstrInfo::findFMA3CommutedOpIndices(), llvm::SystemZInstrInfo::foldMemoryOperandImpl(), llvm::HexagonInstrInfo::getAddrMode(), llvm::HexagonInstrInfo::getCExtOpNum(), llvm::SIInstrInfo::getClampMask(), getCompareSourceReg(), llvm::ARMBaseInstrInfo::getExecutionDomain(), llvm::X86InstrInfo::getExecutionDomain(), llvm::HexagonMCInstrInfo::getExtendableOp(), llvm::HexagonMCInstrInfo::getExtentAlignment(), llvm::HexagonMCInstrInfo::getExtentBits(), llvm::X86InstrInfo::getFMA3OpcodeToCommuteOperands(), getFPReg(), llvm::ARMBaseRegisterInfo::getFrameIndexInstrOffset(), llvm::ARMHazardRecognizer::getHazardType(), llvm::MSP430InstrInfo::getInstSizeInBytes(), llvm::HexagonMCInstrInfo::getMaxValue(), llvm::HexagonInstrInfo::getMaxValue(), llvm::HexagonMCInstrInfo::getMemAccessSize(), llvm::HexagonInstrInfo::getMemAccessSize(), llvm::X86InstrInfo::getMemOpBaseRegImmOfs(), llvm::HexagonMCInstrInfo::getMinValue(), llvm::HexagonInstrInfo::getMinValue(), llvm::HexagonMCInstrInfo::getNewValueOp(), llvm::HexagonMCInstrInfo::getNewValueOp2(), llvm::SystemZInstrInfo::getOpcodeForOffset(), llvm::ARMBaseInstrInfo::getOperandLatency(), getRealVLDOpcode(), getSpecialRegForName(), getTruncatedShiftCount(), llvm::HexagonInstrInfo::getType(), HasConditionalBranch(), llvm::MipsInstrInfo::HasForbiddenSlot(), llvm::SIInstrInfo::hasFPClamp(), llvm::SIInstrInfo::hasIntClamp(), llvm::HexagonMCInstrInfo::hasNewValue(), llvm::HexagonMCInstrInfo::hasNewValue2(), hasRAWHazard(), HasSecRelSymbolRef(), llvm::HexagonMCInstrInfo::isAccumulator(), llvm::HexagonInstrInfo::isAccumulator(), llvm::HexagonMCInstrInfo::isCofMax1(), llvm::HexagonInstrInfo::isConstExtended(), llvm::HexagonMCInstrInfo::isCVINew(), llvm::SIInstrInfo::isDisableWQM(), llvm::SIInstrInfo::isDPP(), llvm::SIInstrInfo::isDS(), llvm::SIInstrInfo::isEXP(), llvm::HexagonMCInstrInfo::isExtendable(), llvm::HexagonInstrInfo::isExtendable(), llvm::HexagonMCInstrInfo::isExtended(), llvm::HexagonInstrInfo::isExtended(), llvm::SIInstrInfo::isFixedSize(), llvm::SIInstrInfo::isFLAT(), llvm::HexagonMCInstrInfo::isFloat(), isFpMulInstruction(), llvm::ARMBaseRegisterInfo::isFrameOffsetLegal(), llvm::SIInstrInfo::isGather4(), isLEASimpleIncOrDec(), llvm::NVPTXInstrInfo::isLoadInstr(), llvm::SIInstrInfo::isMIMG(), llvm::NVPTXInstrInfo::isMoveInstr(), llvm::SIInstrInfo::isMTBUF(), llvm::SIInstrInfo::isMUBUF(), llvm::HexagonMCInstrInfo::isNewValue(), llvm::HexagonInstrInfo::isNewValue(), llvm::HexagonInstrInfo::isNewValueStore(), llvm::HexagonInstrInfo::isOperandExtended(), llvm::ARMBaseInstrInfo::isPredicable(), llvm::HexagonInstrInfo::isPredicated(), llvm::HexagonMCInstrInfo::isPredicated(), llvm::HexagonMCInstrInfo::isPredicatedNew(), llvm::HexagonInstrInfo::isPredicatedNew(), llvm::HexagonMCInstrInfo::isPredicatedTrue(), llvm::HexagonInstrInfo::isPredicatedTrue(), llvm::HexagonMCInstrInfo::isPredicateLate(), llvm::SIInstrInfo::isSALU(), llvm::SIInstrInfo::isScalarStore(), llvm::SIInstrInfo::isScalarUnit(), llvm::SIInstrInfo::isSDWA(), llvm::SIInstrInfo::isSegmentSpecificFLAT(), llvm::SIInstrInfo::isSGPRSpill(), isSimpleBD12Move(), isSimpleMove(), llvm::SIInstrInfo::isSMRD(), llvm::HexagonInstrInfo::isSolo(), llvm::HexagonMCInstrInfo::isSoloAin1(), llvm::HexagonMCInstrInfo::isSoloAX(), llvm::SIInstrInfo::isSOP1(), llvm::SIInstrInfo::isSOP2(), llvm::SIInstrInfo::isSOPC(), llvm::SIInstrInfo::isSOPK(), llvm::SIInstrInfo::isSOPP(), llvm::NVPTXInstrInfo::isStoreInstr(), llvm::SIInstrInfo::isVALU(), llvm::SIInstrInfo::isVGPRSpill(), llvm::SIInstrInfo::isVINTRP(), llvm::SIInstrInfo::isVOP1(), llvm::SIInstrInfo::isVOP2(), llvm::SIInstrInfo::isVOP3(), llvm::SIInstrInfo::isVOP3P(), llvm::SIInstrInfo::isVOPC(), llvm::SIInstrInfo::isWQM(), llvm::HexagonInstrInfo::mayBeCurLoad(), llvm::HexagonInstrInfo::mayBeNewStore(), llvm::SystemZInstrInfo::optimizeCompareInstr(), llvm::PPCHazardRecognizer970::PPCHazardRecognizer970(), llvm::HexagonMCInstrInfo::prefersSlot3(), llvm::X86ATTInstPrinter::printInst(), llvm::X86IntelInstPrinter::printInst(), llvm::WebAssemblyInstPrinter::printInst(), llvm::WebAssemblyInstPrinter::printOperand(), readsVCCZ(), llvm::rewriteARMFrameIndex(), llvm::ThumbRegisterInfo::rewriteFrameIndex(), llvm::rewriteT2FrameIndex(), llvm::MipsInstrInfo::SafeInForbiddenSlot(), llvm::X86InstrInfo::setExecutionDomain(), llvm::SIInstrInfo::sopkIsZext(), stripRegisterPrefix(), usedAsAddr(), llvm::SIInstrInfo::usesLGKM_CNT(), and llvm::SIInstrInfo::usesVM_CNT().


The documentation for this class was generated from the following files: