LLVM  9.0.0svn
MCInstrDesc.h
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1 //===-- llvm/MC/MCInstrDesc.h - Instruction Descriptors -*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file defines the MCOperandInfo and MCInstrDesc classes, which
10 // are used to describe target instructions and their operands.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_MC_MCINSTRDESC_H
15 #define LLVM_MC_MCINSTRDESC_H
16 
17 #include "llvm/MC/MCRegisterInfo.h"
18 #include "llvm/Support/DataTypes.h"
19 #include <string>
20 
21 namespace llvm {
22  class MCInst;
23  class MCSubtargetInfo;
24  class FeatureBitset;
25 
26 //===----------------------------------------------------------------------===//
27 // Machine Operand Flags and Description
28 //===----------------------------------------------------------------------===//
29 
30 namespace MCOI {
31 // Operand constraints
33  TIED_TO = 0, // Must be allocated the same register as.
34  EARLY_CLOBBER // Operand is an early clobber register operand
35 };
36 
37 /// These are flags set on operands, but should be considered
38 /// private, all access should go through the MCOperandInfo accessors.
39 /// See the accessors for a description of what these are.
41 
42 /// Operands are tagged with one of the values of this enum.
49 
58 
60 };
61 
62 }
63 
64 /// This holds information about one operand of a machine instruction,
65 /// indicating the register class for register operands, etc.
67 public:
68  /// This specifies the register class enumeration of the operand
69  /// if the operand is a register. If isLookupPtrRegClass is set, then this is
70  /// an index that is passed to TargetRegisterInfo::getPointerRegClass(x) to
71  /// get a dynamic register class.
72  int16_t RegClass;
73 
74  /// These are flags from the MCOI::OperandFlags enum.
75  uint8_t Flags;
76 
77  /// Information about the type of the operand.
78  uint8_t OperandType;
79  /// The lower 16 bits are used to specify which constraints are set.
80  /// The higher 16 bits are used to specify the value of constraints (4 bits
81  /// each).
83 
84  /// Set if this operand is a pointer value and it requires a callback
85  /// to look up its register class.
86  bool isLookupPtrRegClass() const {
87  return Flags & (1 << MCOI::LookupPtrRegClass);
88  }
89 
90  /// Set if this is one of the operands that made up of the predicate
91  /// operand that controls an isPredicable() instruction.
92  bool isPredicate() const { return Flags & (1 << MCOI::Predicate); }
93 
94  /// Set if this operand is a optional def.
95  bool isOptionalDef() const { return Flags & (1 << MCOI::OptionalDef); }
96 
97  bool isGenericType() const {
98  return OperandType >= MCOI::OPERAND_FIRST_GENERIC &&
99  OperandType <= MCOI::OPERAND_LAST_GENERIC;
100  }
101 
102  unsigned getGenericTypeIndex() const {
103  assert(isGenericType() && "non-generic types don't have an index");
104  return OperandType - MCOI::OPERAND_FIRST_GENERIC;
105  }
106 };
107 
108 //===----------------------------------------------------------------------===//
109 // Machine Instruction Flags and Description
110 //===----------------------------------------------------------------------===//
111 
112 namespace MCID {
113 /// These should be considered private to the implementation of the
114 /// MCInstrDesc class. Clients should use the predicate methods on MCInstrDesc,
115 /// not use these directly. These all correspond to bitfields in the
116 /// MCInstrDesc::Flags field.
117 enum Flag {
118  Variadic = 0,
156 };
157 }
158 
159 /// Describe properties that are true of each instruction in the target
160 /// description file. This captures information about side effects, register
161 /// use and many other things. There is one instance of this struct for each
162 /// target instruction class, and the MachineInstr class points to this struct
163 /// directly to describe itself.
164 class MCInstrDesc {
165 public:
166  unsigned short Opcode; // The opcode number
167  unsigned short NumOperands; // Num of args (may be more if variable_ops)
168  unsigned char NumDefs; // Num of args that are definitions
169  unsigned char Size; // Number of bytes in encoding.
170  unsigned short SchedClass; // enum identifying instr sched class
171  uint64_t Flags; // Flags identifying machine instr class
172  uint64_t TSFlags; // Target Specific Flag values
173  const MCPhysReg *ImplicitUses; // Registers implicitly read by this instr
174  const MCPhysReg *ImplicitDefs; // Registers implicitly defined by this instr
175  const MCOperandInfo *OpInfo; // 'NumOperands' entries about operands
176  // Subtarget feature that this is deprecated on, if any
177  // -1 implies this is not deprecated by any single feature. It may still be
178  // deprecated due to a "complex" reason, below.
180 
181  // A complex method to determine if a certain instruction is deprecated or
182  // not, and return the reason for deprecation.
183  bool (*ComplexDeprecationInfo)(MCInst &, const MCSubtargetInfo &,
184  std::string &);
185 
186  /// Returns the value of the specific constraint if
187  /// it is set. Returns -1 if it is not set.
188  int getOperandConstraint(unsigned OpNum,
189  MCOI::OperandConstraint Constraint) const {
190  if (OpNum < NumOperands &&
191  (OpInfo[OpNum].Constraints & (1 << Constraint))) {
192  unsigned Pos = 16 + Constraint * 4;
193  return (int)(OpInfo[OpNum].Constraints >> Pos) & 0xf;
194  }
195  return -1;
196  }
197 
198  /// Returns true if a certain instruction is deprecated and if so
199  /// returns the reason in \p Info.
200  bool getDeprecatedInfo(MCInst &MI, const MCSubtargetInfo &STI,
201  std::string &Info) const;
202 
203  /// Return the opcode number for this descriptor.
204  unsigned getOpcode() const { return Opcode; }
205 
206  /// Return the number of declared MachineOperands for this
207  /// MachineInstruction. Note that variadic (isVariadic() returns true)
208  /// instructions may have additional operands at the end of the list, and note
209  /// that the machine instruction may include implicit register def/uses as
210  /// well.
211  unsigned getNumOperands() const { return NumOperands; }
212 
214 
215  const_opInfo_iterator opInfo_begin() const { return OpInfo; }
216  const_opInfo_iterator opInfo_end() const { return OpInfo + NumOperands; }
217 
219  return make_range(opInfo_begin(), opInfo_end());
220  }
221 
222  /// Return the number of MachineOperands that are register
223  /// definitions. Register definitions always occur at the start of the
224  /// machine operand list. This is the number of "outs" in the .td file,
225  /// and does not include implicit defs.
226  unsigned getNumDefs() const { return NumDefs; }
227 
228  /// Return flags of this instruction.
229  uint64_t getFlags() const { return Flags; }
230 
231  /// Return true if this instruction can have a variable number of
232  /// operands. In this case, the variable operands will be after the normal
233  /// operands but before the implicit definitions and uses (if any are
234  /// present).
235  bool isVariadic() const { return Flags & (1ULL << MCID::Variadic); }
236 
237  /// Set if this instruction has an optional definition, e.g.
238  /// ARM instructions which can set condition code if 's' bit is set.
239  bool hasOptionalDef() const { return Flags & (1ULL << MCID::HasOptionalDef); }
240 
241  /// Return true if this is a pseudo instruction that doesn't
242  /// correspond to a real machine instruction.
243  bool isPseudo() const { return Flags & (1ULL << MCID::Pseudo); }
244 
245  /// Return true if the instruction is a return.
246  bool isReturn() const { return Flags & (1ULL << MCID::Return); }
247 
248  /// Return true if the instruction is an add instruction.
249  bool isAdd() const { return Flags & (1ULL << MCID::Add); }
250 
251  /// Return true if this instruction is a trap.
252  bool isTrap() const { return Flags & (1ULL << MCID::Trap); }
253 
254  /// Return true if the instruction is a register to register move.
255  bool isMoveReg() const { return Flags & (1ULL << MCID::MoveReg); }
256 
257  /// Return true if the instruction is a call.
258  bool isCall() const { return Flags & (1ULL << MCID::Call); }
259 
260  /// Returns true if the specified instruction stops control flow
261  /// from executing the instruction immediately following it. Examples include
262  /// unconditional branches and return instructions.
263  bool isBarrier() const { return Flags & (1ULL << MCID::Barrier); }
264 
265  /// Returns true if this instruction part of the terminator for
266  /// a basic block. Typically this is things like return and branch
267  /// instructions.
268  ///
269  /// Various passes use this to insert code into the bottom of a basic block,
270  /// but before control flow occurs.
271  bool isTerminator() const { return Flags & (1ULL << MCID::Terminator); }
272 
273  /// Returns true if this is a conditional, unconditional, or
274  /// indirect branch. Predicates below can be used to discriminate between
275  /// these cases, and the TargetInstrInfo::AnalyzeBranch method can be used to
276  /// get more information.
277  bool isBranch() const { return Flags & (1ULL << MCID::Branch); }
278 
279  /// Return true if this is an indirect branch, such as a
280  /// branch through a register.
281  bool isIndirectBranch() const { return Flags & (1ULL << MCID::IndirectBranch); }
282 
283  /// Return true if this is a branch which may fall
284  /// through to the next instruction or may transfer control flow to some other
285  /// block. The TargetInstrInfo::AnalyzeBranch method can be used to get more
286  /// information about this branch.
287  bool isConditionalBranch() const {
288  return isBranch() & !isBarrier() & !isIndirectBranch();
289  }
290 
291  /// Return true if this is a branch which always
292  /// transfers control flow to some other block. The
293  /// TargetInstrInfo::AnalyzeBranch method can be used to get more information
294  /// about this branch.
295  bool isUnconditionalBranch() const {
296  return isBranch() & isBarrier() & !isIndirectBranch();
297  }
298 
299  /// Return true if this is a branch or an instruction which directly
300  /// writes to the program counter. Considered 'may' affect rather than
301  /// 'does' affect as things like predication are not taken into account.
302  bool mayAffectControlFlow(const MCInst &MI, const MCRegisterInfo &RI) const;
303 
304  /// Return true if this instruction has a predicate operand
305  /// that controls execution. It may be set to 'always', or may be set to other
306  /// values. There are various methods in TargetInstrInfo that can be used to
307  /// control and modify the predicate in this instruction.
308  bool isPredicable() const { return Flags & (1ULL << MCID::Predicable); }
309 
310  /// Return true if this instruction is a comparison.
311  bool isCompare() const { return Flags & (1ULL << MCID::Compare); }
312 
313  /// Return true if this instruction is a move immediate
314  /// (including conditional moves) instruction.
315  bool isMoveImmediate() const { return Flags & (1ULL << MCID::MoveImm); }
316 
317  /// Return true if this instruction is a bitcast instruction.
318  bool isBitcast() const { return Flags & (1ULL << MCID::Bitcast); }
319 
320  /// Return true if this is a select instruction.
321  bool isSelect() const { return Flags & (1ULL << MCID::Select); }
322 
323  /// Return true if this instruction cannot be safely
324  /// duplicated. For example, if the instruction has a unique labels attached
325  /// to it, duplicating it would cause multiple definition errors.
326  bool isNotDuplicable() const { return Flags & (1ULL << MCID::NotDuplicable); }
327 
328  /// Returns true if the specified instruction has a delay slot which
329  /// must be filled by the code generator.
330  bool hasDelaySlot() const { return Flags & (1ULL << MCID::DelaySlot); }
331 
332  /// Return true for instructions that can be folded as memory operands
333  /// in other instructions. The most common use for this is instructions that
334  /// are simple loads from memory that don't modify the loaded value in any
335  /// way, but it can also be used for instructions that can be expressed as
336  /// constant-pool loads, such as V_SETALLONES on x86, to allow them to be
337  /// folded when it is beneficial. This should only be set on instructions
338  /// that return a value in their only virtual register definition.
339  bool canFoldAsLoad() const { return Flags & (1ULL << MCID::FoldableAsLoad); }
340 
341  /// Return true if this instruction behaves
342  /// the same way as the generic REG_SEQUENCE instructions.
343  /// E.g., on ARM,
344  /// dX VMOVDRR rY, rZ
345  /// is equivalent to
346  /// dX = REG_SEQUENCE rY, ssub_0, rZ, ssub_1.
347  ///
348  /// Note that for the optimizers to be able to take advantage of
349  /// this property, TargetInstrInfo::getRegSequenceLikeInputs has to be
350  /// override accordingly.
351  bool isRegSequenceLike() const { return Flags & (1ULL << MCID::RegSequence); }
352 
353  /// Return true if this instruction behaves
354  /// the same way as the generic EXTRACT_SUBREG instructions.
355  /// E.g., on ARM,
356  /// rX, rY VMOVRRD dZ
357  /// is equivalent to two EXTRACT_SUBREG:
358  /// rX = EXTRACT_SUBREG dZ, ssub_0
359  /// rY = EXTRACT_SUBREG dZ, ssub_1
360  ///
361  /// Note that for the optimizers to be able to take advantage of
362  /// this property, TargetInstrInfo::getExtractSubregLikeInputs has to be
363  /// override accordingly.
364  bool isExtractSubregLike() const {
365  return Flags & (1ULL << MCID::ExtractSubreg);
366  }
367 
368  /// Return true if this instruction behaves
369  /// the same way as the generic INSERT_SUBREG instructions.
370  /// E.g., on ARM,
371  /// dX = VSETLNi32 dY, rZ, Imm
372  /// is equivalent to a INSERT_SUBREG:
373  /// dX = INSERT_SUBREG dY, rZ, translateImmToSubIdx(Imm)
374  ///
375  /// Note that for the optimizers to be able to take advantage of
376  /// this property, TargetInstrInfo::getInsertSubregLikeInputs has to be
377  /// override accordingly.
378  bool isInsertSubregLike() const { return Flags & (1ULL << MCID::InsertSubreg); }
379 
380 
381  /// Return true if this instruction is convergent.
382  ///
383  /// Convergent instructions may not be made control-dependent on any
384  /// additional values.
385  bool isConvergent() const { return Flags & (1ULL << MCID::Convergent); }
386 
387  /// Return true if variadic operands of this instruction are definitions.
388  bool variadicOpsAreDefs() const {
389  return Flags & (1ULL << MCID::VariadicOpsAreDefs);
390  }
391 
392  //===--------------------------------------------------------------------===//
393  // Side Effect Analysis
394  //===--------------------------------------------------------------------===//
395 
396  /// Return true if this instruction could possibly read memory.
397  /// Instructions with this flag set are not necessarily simple load
398  /// instructions, they may load a value and modify it, for example.
399  bool mayLoad() const { return Flags & (1ULL << MCID::MayLoad); }
400 
401  /// Return true if this instruction could possibly modify memory.
402  /// Instructions with this flag set are not necessarily simple store
403  /// instructions, they may store a modified value based on their operands, or
404  /// may not actually modify anything, for example.
405  bool mayStore() const { return Flags & (1ULL << MCID::MayStore); }
406 
407  /// Return true if this instruction may raise a floating-point exception.
408  bool mayRaiseFPException() const {
409  return Flags & (1ULL << MCID::MayRaiseFPException);
410  }
411 
412  /// Return true if this instruction has side
413  /// effects that are not modeled by other flags. This does not return true
414  /// for instructions whose effects are captured by:
415  ///
416  /// 1. Their operand list and implicit definition/use list. Register use/def
417  /// info is explicit for instructions.
418  /// 2. Memory accesses. Use mayLoad/mayStore.
419  /// 3. Calling, branching, returning: use isCall/isReturn/isBranch.
420  ///
421  /// Examples of side effects would be modifying 'invisible' machine state like
422  /// a control register, flushing a cache, modifying a register invisible to
423  /// LLVM, etc.
424  bool hasUnmodeledSideEffects() const {
425  return Flags & (1ULL << MCID::UnmodeledSideEffects);
426  }
427 
428  //===--------------------------------------------------------------------===//
429  // Flags that indicate whether an instruction can be modified by a method.
430  //===--------------------------------------------------------------------===//
431 
432  /// Return true if this may be a 2- or 3-address instruction (of the
433  /// form "X = op Y, Z, ..."), which produces the same result if Y and Z are
434  /// exchanged. If this flag is set, then the
435  /// TargetInstrInfo::commuteInstruction method may be used to hack on the
436  /// instruction.
437  ///
438  /// Note that this flag may be set on instructions that are only commutable
439  /// sometimes. In these cases, the call to commuteInstruction will fail.
440  /// Also note that some instructions require non-trivial modification to
441  /// commute them.
442  bool isCommutable() const { return Flags & (1ULL << MCID::Commutable); }
443 
444  /// Return true if this is a 2-address instruction which can be changed
445  /// into a 3-address instruction if needed. Doing this transformation can be
446  /// profitable in the register allocator, because it means that the
447  /// instruction can use a 2-address form if possible, but degrade into a less
448  /// efficient form if the source and dest register cannot be assigned to the
449  /// same register. For example, this allows the x86 backend to turn a "shl
450  /// reg, 3" instruction into an LEA instruction, which is the same speed as
451  /// the shift but has bigger code size.
452  ///
453  /// If this returns true, then the target must implement the
454  /// TargetInstrInfo::convertToThreeAddress method for this instruction, which
455  /// is allowed to fail if the transformation isn't valid for this specific
456  /// instruction (e.g. shl reg, 4 on x86).
457  ///
458  bool isConvertibleTo3Addr() const {
459  return Flags & (1ULL << MCID::ConvertibleTo3Addr);
460  }
461 
462  /// Return true if this instruction requires custom insertion support
463  /// when the DAG scheduler is inserting it into a machine basic block. If
464  /// this is true for the instruction, it basically means that it is a pseudo
465  /// instruction used at SelectionDAG time that is expanded out into magic code
466  /// by the target when MachineInstrs are formed.
467  ///
468  /// If this is true, the TargetLoweringInfo::InsertAtEndOfBasicBlock method
469  /// is used to insert this into the MachineBasicBlock.
470  bool usesCustomInsertionHook() const {
471  return Flags & (1ULL << MCID::UsesCustomInserter);
472  }
473 
474  /// Return true if this instruction requires *adjustment* after
475  /// instruction selection by calling a target hook. For example, this can be
476  /// used to fill in ARM 's' optional operand depending on whether the
477  /// conditional flag register is used.
478  bool hasPostISelHook() const { return Flags & (1ULL << MCID::HasPostISelHook); }
479 
480  /// Returns true if this instruction is a candidate for remat. This
481  /// flag is only used in TargetInstrInfo method isTriviallyRematerializable.
482  ///
483  /// If this flag is set, the isReallyTriviallyReMaterializable()
484  /// or isReallyTriviallyReMaterializableGeneric methods are called to verify
485  /// the instruction is really rematable.
486  bool isRematerializable() const {
487  return Flags & (1ULL << MCID::Rematerializable);
488  }
489 
490  /// Returns true if this instruction has the same cost (or less) than a
491  /// move instruction. This is useful during certain types of optimizations
492  /// (e.g., remat during two-address conversion or machine licm) where we would
493  /// like to remat or hoist the instruction, but not if it costs more than
494  /// moving the instruction into the appropriate register. Note, we are not
495  /// marking copies from and to the same register class with this flag.
496  ///
497  /// This method could be called by interface TargetInstrInfo::isAsCheapAsAMove
498  /// for different subtargets.
499  bool isAsCheapAsAMove() const { return Flags & (1ULL << MCID::CheapAsAMove); }
500 
501  /// Returns true if this instruction source operands have special
502  /// register allocation requirements that are not captured by the operand
503  /// register classes. e.g. ARM::STRD's two source registers must be an even /
504  /// odd pair, ARM::STM registers have to be in ascending order. Post-register
505  /// allocation passes should not attempt to change allocations for sources of
506  /// instructions with this flag.
507  bool hasExtraSrcRegAllocReq() const {
508  return Flags & (1ULL << MCID::ExtraSrcRegAllocReq);
509  }
510 
511  /// Returns true if this instruction def operands have special register
512  /// allocation requirements that are not captured by the operand register
513  /// classes. e.g. ARM::LDRD's two def registers must be an even / odd pair,
514  /// ARM::LDM registers have to be in ascending order. Post-register
515  /// allocation passes should not attempt to change allocations for definitions
516  /// of instructions with this flag.
517  bool hasExtraDefRegAllocReq() const {
518  return Flags & (1ULL << MCID::ExtraDefRegAllocReq);
519  }
520 
521  /// Return a list of registers that are potentially read by any
522  /// instance of this machine instruction. For example, on X86, the "adc"
523  /// instruction adds two register operands and adds the carry bit in from the
524  /// flags register. In this case, the instruction is marked as implicitly
525  /// reading the flags. Likewise, the variable shift instruction on X86 is
526  /// marked as implicitly reading the 'CL' register, which it always does.
527  ///
528  /// This method returns null if the instruction has no implicit uses.
529  const MCPhysReg *getImplicitUses() const { return ImplicitUses; }
530 
531  /// Return the number of implicit uses this instruction has.
532  unsigned getNumImplicitUses() const {
533  if (!ImplicitUses)
534  return 0;
535  unsigned i = 0;
536  for (; ImplicitUses[i]; ++i) /*empty*/
537  ;
538  return i;
539  }
540 
541  /// Return a list of registers that are potentially written by any
542  /// instance of this machine instruction. For example, on X86, many
543  /// instructions implicitly set the flags register. In this case, they are
544  /// marked as setting the FLAGS. Likewise, many instructions always deposit
545  /// their result in a physical register. For example, the X86 divide
546  /// instruction always deposits the quotient and remainder in the EAX/EDX
547  /// registers. For that instruction, this will return a list containing the
548  /// EAX/EDX/EFLAGS registers.
549  ///
550  /// This method returns null if the instruction has no implicit defs.
551  const MCPhysReg *getImplicitDefs() const { return ImplicitDefs; }
552 
553  /// Return the number of implicit defs this instruct has.
554  unsigned getNumImplicitDefs() const {
555  if (!ImplicitDefs)
556  return 0;
557  unsigned i = 0;
558  for (; ImplicitDefs[i]; ++i) /*empty*/
559  ;
560  return i;
561  }
562 
563  /// Return true if this instruction implicitly
564  /// uses the specified physical register.
565  bool hasImplicitUseOfPhysReg(unsigned Reg) const {
566  if (const MCPhysReg *ImpUses = ImplicitUses)
567  for (; *ImpUses; ++ImpUses)
568  if (*ImpUses == Reg)
569  return true;
570  return false;
571  }
572 
573  /// Return true if this instruction implicitly
574  /// defines the specified physical register.
575  bool hasImplicitDefOfPhysReg(unsigned Reg,
576  const MCRegisterInfo *MRI = nullptr) const;
577 
578  /// Return the scheduling class for this instruction. The
579  /// scheduling class is an index into the InstrItineraryData table. This
580  /// returns zero if there is no known scheduling information for the
581  /// instruction.
582  unsigned getSchedClass() const { return SchedClass; }
583 
584  /// Return the number of bytes in the encoding of this instruction,
585  /// or zero if the encoding size cannot be known from the opcode.
586  unsigned getSize() const { return Size; }
587 
588  /// Find the index of the first operand in the
589  /// operand list that is used to represent the predicate. It returns -1 if
590  /// none is found.
592  if (isPredicable()) {
593  for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
594  if (OpInfo[i].isPredicate())
595  return i;
596  }
597  return -1;
598  }
599 
600  /// Return true if this instruction defines the specified physical
601  /// register, either explicitly or implicitly.
602  bool hasDefOfPhysReg(const MCInst &MI, unsigned Reg,
603  const MCRegisterInfo &RI) const;
604 };
605 
606 } // end namespace llvm
607 
608 #endif
unsigned getNumImplicitUses() const
Return the number of implicit uses this instruction has.
Definition: MCInstrDesc.h:532
bool isMoveReg() const
Return true if the instruction is a register to register move.
Definition: MCInstrDesc.h:255
unsigned getNumImplicitDefs() const
Return the number of implicit defs this instruct has.
Definition: MCInstrDesc.h:554
This class represents lattice values for constants.
Definition: AllocatorList.h:23
bool isLookupPtrRegClass() const
Set if this operand is a pointer value and it requires a callback to look up its register class...
Definition: MCInstrDesc.h:86
bool isCommutable() const
Return true if this may be a 2- or 3-address instruction (of the form "X = op Y, Z, ..."), which produces the same result if Y and Z are exchanged.
Definition: MCInstrDesc.h:442
uint8_t Flags
These are flags from the MCOI::OperandFlags enum.
Definition: MCInstrDesc.h:75
unsigned char Size
Definition: MCInstrDesc.h:169
const MCPhysReg * getImplicitUses() const
Return a list of registers that are potentially read by any instance of this machine instruction...
Definition: MCInstrDesc.h:529
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:164
unsigned Reg
int findFirstPredOperandIdx() const
Find the index of the first operand in the operand list that is used to represent the predicate...
Definition: MCInstrDesc.h:591
bool hasUnmodeledSideEffects() const
Return true if this instruction has side effects that are not modeled by other flags.
Definition: MCInstrDesc.h:424
bool isRegSequenceLike() const
Return true if this instruction behaves the same way as the generic REG_SEQUENCE instructions.
Definition: MCInstrDesc.h:351
const_opInfo_iterator opInfo_begin() const
Definition: MCInstrDesc.h:215
bool isPseudo() const
Return true if this is a pseudo instruction that doesn&#39;t correspond to a real machine instruction...
Definition: MCInstrDesc.h:243
bool mayLoad() const
Return true if this instruction could possibly read memory.
Definition: MCInstrDesc.h:399
bool isReturn() const
Return true if the instruction is a return.
Definition: MCInstrDesc.h:246
bool isBranch() const
Returns true if this is a conditional, unconditional, or indirect branch.
Definition: MCInstrDesc.h:277
bool isCompare() const
Return true if this instruction is a comparison.
Definition: MCInstrDesc.h:311
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
Definition: MCInstrDesc.h:211
bool isTrap() const
Return true if this instruction is a trap.
Definition: MCInstrDesc.h:252
bool isExtractSubregLike() const
Return true if this instruction behaves the same way as the generic EXTRACT_SUBREG instructions...
Definition: MCInstrDesc.h:364
bool isSelect() const
Return true if this is a select instruction.
Definition: MCInstrDesc.h:321
uint8_t OperandType
Information about the type of the operand.
Definition: MCInstrDesc.h:78
bool isConvertibleTo3Addr() const
Return true if this is a 2-address instruction which can be changed into a 3-address instruction if n...
Definition: MCInstrDesc.h:458
bool isRematerializable() const
Returns true if this instruction is a candidate for remat.
Definition: MCInstrDesc.h:486
uint32_t Constraints
The lower 16 bits are used to specify which constraints are set.
Definition: MCInstrDesc.h:82
bool isAsCheapAsAMove() const
Returns true if this instruction has the same cost (or less) than a move instruction.
Definition: MCInstrDesc.h:499
bool isPredicate() const
Set if this is one of the operands that made up of the predicate operand that controls an isPredicabl...
Definition: MCInstrDesc.h:92
bool hasExtraDefRegAllocReq() const
Returns true if this instruction def operands have special register allocation requirements that are ...
Definition: MCInstrDesc.h:517
bool isMoveImmediate() const
Return true if this instruction is a move immediate (including conditional moves) instruction...
Definition: MCInstrDesc.h:315
Analysis containing CSE Info
Definition: CSEInfo.cpp:20
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:158
unsigned short NumOperands
Definition: MCInstrDesc.h:167
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
Flag
These should be considered private to the implementation of the MCInstrDesc class.
Definition: MCInstrDesc.h:117
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
unsigned getSchedClass() const
Return the scheduling class for this instruction.
Definition: MCInstrDesc.h:582
bool isGenericType() const
Definition: MCInstrDesc.h:97
const MCPhysReg * getImplicitDefs() const
Return a list of registers that are potentially written by any instance of this machine instruction...
Definition: MCInstrDesc.h:551
bool hasExtraSrcRegAllocReq() const
Returns true if this instruction source operands have special register allocation requirements that a...
Definition: MCInstrDesc.h:507
unsigned const MachineRegisterInfo * MRI
bool isOptionalDef() const
Set if this operand is a optional def.
Definition: MCInstrDesc.h:95
bool hasOptionalDef() const
Set if this instruction has an optional definition, e.g.
Definition: MCInstrDesc.h:239
bool isBarrier() const
Returns true if the specified instruction stops control flow from executing the instruction immediate...
Definition: MCInstrDesc.h:263
bool isVariadic() const
Return true if this instruction can have a variable number of operands.
Definition: MCInstrDesc.h:235
bool isConditionalBranch() const
Return true if this is a branch which may fall through to the next instruction or may transfer contro...
Definition: MCInstrDesc.h:287
int64_t DeprecatedFeature
Definition: MCInstrDesc.h:179
OperandFlags
These are flags set on operands, but should be considered private, all access should go through the M...
Definition: MCInstrDesc.h:40
const MCPhysReg * ImplicitDefs
Definition: MCInstrDesc.h:174
bool isPredicable() const
Return true if this instruction has a predicate operand that controls execution.
Definition: MCInstrDesc.h:308
bool isIndirectBranch() const
Return true if this is an indirect branch, such as a branch through a register.
Definition: MCInstrDesc.h:281
bool hasPostISelHook() const
Return true if this instruction requires adjustment after instruction selection by calling a target h...
Definition: MCInstrDesc.h:478
unsigned char NumDefs
Definition: MCInstrDesc.h:168
bool mayRaiseFPException() const
Return true if this instruction may raise a floating-point exception.
Definition: MCInstrDesc.h:408
bool isAdd() const
Return true if the instruction is an add instruction.
Definition: MCInstrDesc.h:249
bool isNotDuplicable() const
Return true if this instruction cannot be safely duplicated.
Definition: MCInstrDesc.h:326
int getOperandConstraint(unsigned OpNum, MCOI::OperandConstraint Constraint) const
Returns the value of the specific constraint if it is set.
Definition: MCInstrDesc.h:188
iterator_range< T > make_range(T x, T y)
Convenience function for iterating over sub-ranges.
bool isInsertSubregLike() const
Return true if this instruction behaves the same way as the generic INSERT_SUBREG instructions...
Definition: MCInstrDesc.h:378
bool hasDelaySlot() const
Returns true if the specified instruction has a delay slot which must be filled by the code generator...
Definition: MCInstrDesc.h:330
bool isBitcast() const
Return true if this instruction is a bitcast instruction.
Definition: MCInstrDesc.h:318
unsigned getNumDefs() const
Return the number of MachineOperands that are register definitions.
Definition: MCInstrDesc.h:226
unsigned short Opcode
Definition: MCInstrDesc.h:166
A range adaptor for a pair of iterators.
bool isConvergent() const
Return true if this instruction is convergent.
Definition: MCInstrDesc.h:385
bool mayStore() const
Return true if this instruction could possibly modify memory.
Definition: MCInstrDesc.h:405
bool isUnconditionalBranch() const
Return true if this is a branch which always transfers control flow to some other block...
Definition: MCInstrDesc.h:295
OperandType
Operands are tagged with one of the values of this enum.
Definition: MCInstrDesc.h:43
bool canFoldAsLoad() const
Return true for instructions that can be folded as memory operands in other instructions.
Definition: MCInstrDesc.h:339
int16_t RegClass
This specifies the register class enumeration of the operand if the operand is a register.
Definition: MCInstrDesc.h:72
const_opInfo_iterator opInfo_end() const
Definition: MCInstrDesc.h:216
bool isCall() const
Return true if the instruction is a call.
Definition: MCInstrDesc.h:258
Generic base class for all target subtargets.
uint32_t Size
Definition: Profile.cpp:46
bool variadicOpsAreDefs() const
Return true if variadic operands of this instruction are definitions.
Definition: MCInstrDesc.h:388
iterator_range< const_opInfo_iterator > operands() const
Definition: MCInstrDesc.h:218
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static bool isBranch(unsigned Opcode)
bool hasImplicitUseOfPhysReg(unsigned Reg) const
Return true if this instruction implicitly uses the specified physical register.
Definition: MCInstrDesc.h:565
bool isTerminator() const
Returns true if this instruction part of the terminator for a basic block.
Definition: MCInstrDesc.h:271
const MCOperandInfo * OpInfo
Definition: MCInstrDesc.h:175
unsigned getOpcode() const
Return the opcode number for this descriptor.
Definition: MCInstrDesc.h:204
unsigned getGenericTypeIndex() const
Definition: MCInstrDesc.h:102
IRTranslator LLVM IR MI
bool usesCustomInsertionHook() const
Return true if this instruction requires custom insertion support when the DAG scheduler is inserting...
Definition: MCInstrDesc.h:470
This holds information about one operand of a machine instruction, indicating the register class for ...
Definition: MCInstrDesc.h:66
uint64_t getFlags() const
Return flags of this instruction.
Definition: MCInstrDesc.h:229
unsigned short SchedClass
Definition: MCInstrDesc.h:170
const MCPhysReg * ImplicitUses
Definition: MCInstrDesc.h:173
unsigned getSize() const
Return the number of bytes in the encoding of this instruction, or zero if the encoding size cannot b...
Definition: MCInstrDesc.h:586