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MCInstrDesc.h
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1 //===-- llvm/MC/MCInstrDesc.h - Instruction Descriptors -*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines the MCOperandInfo and MCInstrDesc classes, which
11 // are used to describe target instructions and their operands.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #ifndef LLVM_MC_MCINSTRDESC_H
16 #define LLVM_MC_MCINSTRDESC_H
17 
18 #include "llvm/MC/MCRegisterInfo.h"
19 #include "llvm/Support/DataTypes.h"
20 #include <string>
21 
22 namespace llvm {
23  class MCInst;
24  class MCSubtargetInfo;
25  class FeatureBitset;
26 
27 //===----------------------------------------------------------------------===//
28 // Machine Operand Flags and Description
29 //===----------------------------------------------------------------------===//
30 
31 namespace MCOI {
32 // Operand constraints
34  TIED_TO = 0, // Must be allocated the same register as.
35  EARLY_CLOBBER // Operand is an early clobber register operand
36 };
37 
38 /// \brief These are flags set on operands, but should be considered
39 /// private, all access should go through the MCOperandInfo accessors.
40 /// See the accessors for a description of what these are.
42 
43 /// \brief Operands are tagged with one of the values of this enum.
50 
59 
61 };
62 
64 };
65 
66 }
67 
68 /// \brief This holds information about one operand of a machine instruction,
69 /// indicating the register class for register operands, etc.
71 public:
72  /// \brief This specifies the register class enumeration of the operand
73  /// if the operand is a register. If isLookupPtrRegClass is set, then this is
74  /// an index that is passed to TargetRegisterInfo::getPointerRegClass(x) to
75  /// get a dynamic register class.
76  int16_t RegClass;
77 
78  /// \brief These are flags from the MCOI::OperandFlags enum.
79  uint8_t Flags;
80 
81  /// \brief Information about the type of the operand.
82  uint8_t OperandType;
83  /// \brief The lower 16 bits are used to specify which constraints are set.
84  /// The higher 16 bits are used to specify the value of constraints (4 bits
85  /// each).
87 
88  /// \brief Set if this operand is a pointer value and it requires a callback
89  /// to look up its register class.
90  bool isLookupPtrRegClass() const {
91  return Flags & (1 << MCOI::LookupPtrRegClass);
92  }
93 
94  /// \brief Set if this is one of the operands that made up of the predicate
95  /// operand that controls an isPredicable() instruction.
96  bool isPredicate() const { return Flags & (1 << MCOI::Predicate); }
97 
98  /// \brief Set if this operand is a optional def.
99  bool isOptionalDef() const { return Flags & (1 << MCOI::OptionalDef); }
100 
101  bool isGenericType() const {
102  return OperandType >= MCOI::OPERAND_FIRST_GENERIC &&
103  OperandType <= MCOI::OPERAND_LAST_GENERIC;
104  }
105 
106  unsigned getGenericTypeIndex() const {
107  assert(isGenericType() && "non-generic types don't have an index");
108  return OperandType - MCOI::OPERAND_FIRST_GENERIC;
109  }
110 };
111 
112 //===----------------------------------------------------------------------===//
113 // Machine Instruction Flags and Description
114 //===----------------------------------------------------------------------===//
115 
116 namespace MCID {
117 /// \brief These should be considered private to the implementation of the
118 /// MCInstrDesc class. Clients should use the predicate methods on MCInstrDesc,
119 /// not use these directly. These all correspond to bitfields in the
120 /// MCInstrDesc::Flags field.
121 enum Flag {
122  Variadic = 0,
155 };
156 }
157 
158 /// \brief Describe properties that are true of each instruction in the target
159 /// description file. This captures information about side effects, register
160 /// use and many other things. There is one instance of this struct for each
161 /// target instruction class, and the MachineInstr class points to this struct
162 /// directly to describe itself.
163 class MCInstrDesc {
164 public:
165  unsigned short Opcode; // The opcode number
166  unsigned short NumOperands; // Num of args (may be more if variable_ops)
167  unsigned char NumDefs; // Num of args that are definitions
168  unsigned char Size; // Number of bytes in encoding.
169  unsigned short SchedClass; // enum identifying instr sched class
170  uint64_t Flags; // Flags identifying machine instr class
171  uint64_t TSFlags; // Target Specific Flag values
172  const MCPhysReg *ImplicitUses; // Registers implicitly read by this instr
173  const MCPhysReg *ImplicitDefs; // Registers implicitly defined by this instr
174  const MCOperandInfo *OpInfo; // 'NumOperands' entries about operands
175  // Subtarget feature that this is deprecated on, if any
176  // -1 implies this is not deprecated by any single feature. It may still be
177  // deprecated due to a "complex" reason, below.
179 
180  // A complex method to determine is a certain is deprecated or not, and return
181  // the reason for deprecation.
182  bool (*ComplexDeprecationInfo)(MCInst &, const MCSubtargetInfo &,
183  std::string &);
184 
185  /// \brief Returns the value of the specific constraint if
186  /// it is set. Returns -1 if it is not set.
187  int getOperandConstraint(unsigned OpNum,
188  MCOI::OperandConstraint Constraint) const {
189  if (OpNum < NumOperands &&
190  (OpInfo[OpNum].Constraints & (1 << Constraint))) {
191  unsigned Pos = 16 + Constraint * 4;
192  return (int)(OpInfo[OpNum].Constraints >> Pos) & 0xf;
193  }
194  return -1;
195  }
196 
197  /// \brief Returns true if a certain instruction is deprecated and if so
198  /// returns the reason in \p Info.
199  bool getDeprecatedInfo(MCInst &MI, const MCSubtargetInfo &STI,
200  std::string &Info) const;
201 
202  /// \brief Return the opcode number for this descriptor.
203  unsigned getOpcode() const { return Opcode; }
204 
205  /// \brief Return the number of declared MachineOperands for this
206  /// MachineInstruction. Note that variadic (isVariadic() returns true)
207  /// instructions may have additional operands at the end of the list, and note
208  /// that the machine instruction may include implicit register def/uses as
209  /// well.
210  unsigned getNumOperands() const { return NumOperands; }
211 
213 
214  const_opInfo_iterator opInfo_begin() const { return OpInfo; }
215  const_opInfo_iterator opInfo_end() const { return OpInfo + NumOperands; }
216 
218  return make_range(opInfo_begin(), opInfo_end());
219  }
220 
221  /// \brief Return the number of MachineOperands that are register
222  /// definitions. Register definitions always occur at the start of the
223  /// machine operand list. This is the number of "outs" in the .td file,
224  /// and does not include implicit defs.
225  unsigned getNumDefs() const { return NumDefs; }
226 
227  /// \brief Return flags of this instruction.
228  uint64_t getFlags() const { return Flags; }
229 
230  /// \brief Return true if this instruction can have a variable number of
231  /// operands. In this case, the variable operands will be after the normal
232  /// operands but before the implicit definitions and uses (if any are
233  /// present).
234  bool isVariadic() const { return Flags & (1ULL << MCID::Variadic); }
235 
236  /// \brief Set if this instruction has an optional definition, e.g.
237  /// ARM instructions which can set condition code if 's' bit is set.
238  bool hasOptionalDef() const { return Flags & (1ULL << MCID::HasOptionalDef); }
239 
240  /// \brief Return true if this is a pseudo instruction that doesn't
241  /// correspond to a real machine instruction.
242  bool isPseudo() const { return Flags & (1ULL << MCID::Pseudo); }
243 
244  /// \brief Return true if the instruction is a return.
245  bool isReturn() const { return Flags & (1ULL << MCID::Return); }
246 
247  /// \brief Return true if the instruction is an add instruction.
248  bool isAdd() const { return Flags & (1ULL << MCID::Add); }
249 
250  /// \brief Return true if the instruction is a call.
251  bool isCall() const { return Flags & (1ULL << MCID::Call); }
252 
253  /// \brief Returns true if the specified instruction stops control flow
254  /// from executing the instruction immediately following it. Examples include
255  /// unconditional branches and return instructions.
256  bool isBarrier() const { return Flags & (1ULL << MCID::Barrier); }
257 
258  /// \brief Returns true if this instruction part of the terminator for
259  /// a basic block. Typically this is things like return and branch
260  /// instructions.
261  ///
262  /// Various passes use this to insert code into the bottom of a basic block,
263  /// but before control flow occurs.
264  bool isTerminator() const { return Flags & (1ULL << MCID::Terminator); }
265 
266  /// \brief Returns true if this is a conditional, unconditional, or
267  /// indirect branch. Predicates below can be used to discriminate between
268  /// these cases, and the TargetInstrInfo::AnalyzeBranch method can be used to
269  /// get more information.
270  bool isBranch() const { return Flags & (1ULL << MCID::Branch); }
271 
272  /// \brief Return true if this is an indirect branch, such as a
273  /// branch through a register.
274  bool isIndirectBranch() const { return Flags & (1ULL << MCID::IndirectBranch); }
275 
276  /// \brief Return true if this is a branch which may fall
277  /// through to the next instruction or may transfer control flow to some other
278  /// block. The TargetInstrInfo::AnalyzeBranch method can be used to get more
279  /// information about this branch.
280  bool isConditionalBranch() const {
281  return isBranch() & !isBarrier() & !isIndirectBranch();
282  }
283 
284  /// \brief Return true if this is a branch which always
285  /// transfers control flow to some other block. The
286  /// TargetInstrInfo::AnalyzeBranch method can be used to get more information
287  /// about this branch.
288  bool isUnconditionalBranch() const {
289  return isBranch() & isBarrier() & !isIndirectBranch();
290  }
291 
292  /// \brief Return true if this is a branch or an instruction which directly
293  /// writes to the program counter. Considered 'may' affect rather than
294  /// 'does' affect as things like predication are not taken into account.
295  bool mayAffectControlFlow(const MCInst &MI, const MCRegisterInfo &RI) const;
296 
297  /// \brief Return true if this instruction has a predicate operand
298  /// that controls execution. It may be set to 'always', or may be set to other
299  /// values. There are various methods in TargetInstrInfo that can be used to
300  /// control and modify the predicate in this instruction.
301  bool isPredicable() const { return Flags & (1ULL << MCID::Predicable); }
302 
303  /// \brief Return true if this instruction is a comparison.
304  bool isCompare() const { return Flags & (1ULL << MCID::Compare); }
305 
306  /// \brief Return true if this instruction is a move immediate
307  /// (including conditional moves) instruction.
308  bool isMoveImmediate() const { return Flags & (1ULL << MCID::MoveImm); }
309 
310  /// \brief Return true if this instruction is a bitcast instruction.
311  bool isBitcast() const { return Flags & (1ULL << MCID::Bitcast); }
312 
313  /// \brief Return true if this is a select instruction.
314  bool isSelect() const { return Flags & (1ULL << MCID::Select); }
315 
316  /// \brief Return true if this instruction cannot be safely
317  /// duplicated. For example, if the instruction has a unique labels attached
318  /// to it, duplicating it would cause multiple definition errors.
319  bool isNotDuplicable() const { return Flags & (1ULL << MCID::NotDuplicable); }
320 
321  /// \brief Returns true if the specified instruction has a delay slot which
322  /// must be filled by the code generator.
323  bool hasDelaySlot() const { return Flags & (1ULL << MCID::DelaySlot); }
324 
325  /// \brief Return true for instructions that can be folded as memory operands
326  /// in other instructions. The most common use for this is instructions that
327  /// are simple loads from memory that don't modify the loaded value in any
328  /// way, but it can also be used for instructions that can be expressed as
329  /// constant-pool loads, such as V_SETALLONES on x86, to allow them to be
330  /// folded when it is beneficial. This should only be set on instructions
331  /// that return a value in their only virtual register definition.
332  bool canFoldAsLoad() const { return Flags & (1ULL << MCID::FoldableAsLoad); }
333 
334  /// \brief Return true if this instruction behaves
335  /// the same way as the generic REG_SEQUENCE instructions.
336  /// E.g., on ARM,
337  /// dX VMOVDRR rY, rZ
338  /// is equivalent to
339  /// dX = REG_SEQUENCE rY, ssub_0, rZ, ssub_1.
340  ///
341  /// Note that for the optimizers to be able to take advantage of
342  /// this property, TargetInstrInfo::getRegSequenceLikeInputs has to be
343  /// override accordingly.
344  bool isRegSequenceLike() const { return Flags & (1ULL << MCID::RegSequence); }
345 
346  /// \brief Return true if this instruction behaves
347  /// the same way as the generic EXTRACT_SUBREG instructions.
348  /// E.g., on ARM,
349  /// rX, rY VMOVRRD dZ
350  /// is equivalent to two EXTRACT_SUBREG:
351  /// rX = EXTRACT_SUBREG dZ, ssub_0
352  /// rY = EXTRACT_SUBREG dZ, ssub_1
353  ///
354  /// Note that for the optimizers to be able to take advantage of
355  /// this property, TargetInstrInfo::getExtractSubregLikeInputs has to be
356  /// override accordingly.
357  bool isExtractSubregLike() const {
358  return Flags & (1ULL << MCID::ExtractSubreg);
359  }
360 
361  /// \brief Return true if this instruction behaves
362  /// the same way as the generic INSERT_SUBREG instructions.
363  /// E.g., on ARM,
364  /// dX = VSETLNi32 dY, rZ, Imm
365  /// is equivalent to a INSERT_SUBREG:
366  /// dX = INSERT_SUBREG dY, rZ, translateImmToSubIdx(Imm)
367  ///
368  /// Note that for the optimizers to be able to take advantage of
369  /// this property, TargetInstrInfo::getInsertSubregLikeInputs has to be
370  /// override accordingly.
371  bool isInsertSubregLike() const { return Flags & (1ULL << MCID::InsertSubreg); }
372 
373 
374  /// \brief Return true if this instruction is convergent.
375  ///
376  /// Convergent instructions may not be made control-dependent on any
377  /// additional values.
378  bool isConvergent() const { return Flags & (1ULL << MCID::Convergent); }
379 
380  //===--------------------------------------------------------------------===//
381  // Side Effect Analysis
382  //===--------------------------------------------------------------------===//
383 
384  /// \brief Return true if this instruction could possibly read memory.
385  /// Instructions with this flag set are not necessarily simple load
386  /// instructions, they may load a value and modify it, for example.
387  bool mayLoad() const { return Flags & (1ULL << MCID::MayLoad); }
388 
389  /// \brief Return true if this instruction could possibly modify memory.
390  /// Instructions with this flag set are not necessarily simple store
391  /// instructions, they may store a modified value based on their operands, or
392  /// may not actually modify anything, for example.
393  bool mayStore() const { return Flags & (1ULL << MCID::MayStore); }
394 
395  /// \brief Return true if this instruction has side
396  /// effects that are not modeled by other flags. This does not return true
397  /// for instructions whose effects are captured by:
398  ///
399  /// 1. Their operand list and implicit definition/use list. Register use/def
400  /// info is explicit for instructions.
401  /// 2. Memory accesses. Use mayLoad/mayStore.
402  /// 3. Calling, branching, returning: use isCall/isReturn/isBranch.
403  ///
404  /// Examples of side effects would be modifying 'invisible' machine state like
405  /// a control register, flushing a cache, modifying a register invisible to
406  /// LLVM, etc.
407  bool hasUnmodeledSideEffects() const {
408  return Flags & (1ULL << MCID::UnmodeledSideEffects);
409  }
410 
411  //===--------------------------------------------------------------------===//
412  // Flags that indicate whether an instruction can be modified by a method.
413  //===--------------------------------------------------------------------===//
414 
415  /// \brief Return true if this may be a 2- or 3-address instruction (of the
416  /// form "X = op Y, Z, ..."), which produces the same result if Y and Z are
417  /// exchanged. If this flag is set, then the
418  /// TargetInstrInfo::commuteInstruction method may be used to hack on the
419  /// instruction.
420  ///
421  /// Note that this flag may be set on instructions that are only commutable
422  /// sometimes. In these cases, the call to commuteInstruction will fail.
423  /// Also note that some instructions require non-trivial modification to
424  /// commute them.
425  bool isCommutable() const { return Flags & (1ULL << MCID::Commutable); }
426 
427  /// \brief Return true if this is a 2-address instruction which can be changed
428  /// into a 3-address instruction if needed. Doing this transformation can be
429  /// profitable in the register allocator, because it means that the
430  /// instruction can use a 2-address form if possible, but degrade into a less
431  /// efficient form if the source and dest register cannot be assigned to the
432  /// same register. For example, this allows the x86 backend to turn a "shl
433  /// reg, 3" instruction into an LEA instruction, which is the same speed as
434  /// the shift but has bigger code size.
435  ///
436  /// If this returns true, then the target must implement the
437  /// TargetInstrInfo::convertToThreeAddress method for this instruction, which
438  /// is allowed to fail if the transformation isn't valid for this specific
439  /// instruction (e.g. shl reg, 4 on x86).
440  ///
441  bool isConvertibleTo3Addr() const {
442  return Flags & (1ULL << MCID::ConvertibleTo3Addr);
443  }
444 
445  /// \brief Return true if this instruction requires custom insertion support
446  /// when the DAG scheduler is inserting it into a machine basic block. If
447  /// this is true for the instruction, it basically means that it is a pseudo
448  /// instruction used at SelectionDAG time that is expanded out into magic code
449  /// by the target when MachineInstrs are formed.
450  ///
451  /// If this is true, the TargetLoweringInfo::InsertAtEndOfBasicBlock method
452  /// is used to insert this into the MachineBasicBlock.
453  bool usesCustomInsertionHook() const {
454  return Flags & (1ULL << MCID::UsesCustomInserter);
455  }
456 
457  /// \brief Return true if this instruction requires *adjustment* after
458  /// instruction selection by calling a target hook. For example, this can be
459  /// used to fill in ARM 's' optional operand depending on whether the
460  /// conditional flag register is used.
461  bool hasPostISelHook() const { return Flags & (1ULL << MCID::HasPostISelHook); }
462 
463  /// \brief Returns true if this instruction is a candidate for remat. This
464  /// flag is only used in TargetInstrInfo method isTriviallyRematerializable.
465  ///
466  /// If this flag is set, the isReallyTriviallyReMaterializable()
467  /// or isReallyTriviallyReMaterializableGeneric methods are called to verify
468  /// the instruction is really rematable.
469  bool isRematerializable() const {
470  return Flags & (1ULL << MCID::Rematerializable);
471  }
472 
473  /// \brief Returns true if this instruction has the same cost (or less) than a
474  /// move instruction. This is useful during certain types of optimizations
475  /// (e.g., remat during two-address conversion or machine licm) where we would
476  /// like to remat or hoist the instruction, but not if it costs more than
477  /// moving the instruction into the appropriate register. Note, we are not
478  /// marking copies from and to the same register class with this flag.
479  ///
480  /// This method could be called by interface TargetInstrInfo::isAsCheapAsAMove
481  /// for different subtargets.
482  bool isAsCheapAsAMove() const { return Flags & (1ULL << MCID::CheapAsAMove); }
483 
484  /// \brief Returns true if this instruction source operands have special
485  /// register allocation requirements that are not captured by the operand
486  /// register classes. e.g. ARM::STRD's two source registers must be an even /
487  /// odd pair, ARM::STM registers have to be in ascending order. Post-register
488  /// allocation passes should not attempt to change allocations for sources of
489  /// instructions with this flag.
490  bool hasExtraSrcRegAllocReq() const {
491  return Flags & (1ULL << MCID::ExtraSrcRegAllocReq);
492  }
493 
494  /// \brief Returns true if this instruction def operands have special register
495  /// allocation requirements that are not captured by the operand register
496  /// classes. e.g. ARM::LDRD's two def registers must be an even / odd pair,
497  /// ARM::LDM registers have to be in ascending order. Post-register
498  /// allocation passes should not attempt to change allocations for definitions
499  /// of instructions with this flag.
500  bool hasExtraDefRegAllocReq() const {
501  return Flags & (1ULL << MCID::ExtraDefRegAllocReq);
502  }
503 
504  /// \brief Return a list of registers that are potentially read by any
505  /// instance of this machine instruction. For example, on X86, the "adc"
506  /// instruction adds two register operands and adds the carry bit in from the
507  /// flags register. In this case, the instruction is marked as implicitly
508  /// reading the flags. Likewise, the variable shift instruction on X86 is
509  /// marked as implicitly reading the 'CL' register, which it always does.
510  ///
511  /// This method returns null if the instruction has no implicit uses.
512  const MCPhysReg *getImplicitUses() const { return ImplicitUses; }
513 
514  /// \brief Return the number of implicit uses this instruction has.
515  unsigned getNumImplicitUses() const {
516  if (!ImplicitUses)
517  return 0;
518  unsigned i = 0;
519  for (; ImplicitUses[i]; ++i) /*empty*/
520  ;
521  return i;
522  }
523 
524  /// \brief Return a list of registers that are potentially written by any
525  /// instance of this machine instruction. For example, on X86, many
526  /// instructions implicitly set the flags register. In this case, they are
527  /// marked as setting the FLAGS. Likewise, many instructions always deposit
528  /// their result in a physical register. For example, the X86 divide
529  /// instruction always deposits the quotient and remainder in the EAX/EDX
530  /// registers. For that instruction, this will return a list containing the
531  /// EAX/EDX/EFLAGS registers.
532  ///
533  /// This method returns null if the instruction has no implicit defs.
534  const MCPhysReg *getImplicitDefs() const { return ImplicitDefs; }
535 
536  /// \brief Return the number of implicit defs this instruct has.
537  unsigned getNumImplicitDefs() const {
538  if (!ImplicitDefs)
539  return 0;
540  unsigned i = 0;
541  for (; ImplicitDefs[i]; ++i) /*empty*/
542  ;
543  return i;
544  }
545 
546  /// \brief Return true if this instruction implicitly
547  /// uses the specified physical register.
548  bool hasImplicitUseOfPhysReg(unsigned Reg) const {
549  if (const MCPhysReg *ImpUses = ImplicitUses)
550  for (; *ImpUses; ++ImpUses)
551  if (*ImpUses == Reg)
552  return true;
553  return false;
554  }
555 
556  /// \brief Return true if this instruction implicitly
557  /// defines the specified physical register.
558  bool hasImplicitDefOfPhysReg(unsigned Reg,
559  const MCRegisterInfo *MRI = nullptr) const;
560 
561  /// \brief Return the scheduling class for this instruction. The
562  /// scheduling class is an index into the InstrItineraryData table. This
563  /// returns zero if there is no known scheduling information for the
564  /// instruction.
565  unsigned getSchedClass() const { return SchedClass; }
566 
567  /// \brief Return the number of bytes in the encoding of this instruction,
568  /// or zero if the encoding size cannot be known from the opcode.
569  unsigned getSize() const { return Size; }
570 
571  /// \brief Find the index of the first operand in the
572  /// operand list that is used to represent the predicate. It returns -1 if
573  /// none is found.
575  if (isPredicable()) {
576  for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
577  if (OpInfo[i].isPredicate())
578  return i;
579  }
580  return -1;
581  }
582 
583 private:
584 
585  /// \brief Return true if this instruction defines the specified physical
586  /// register, either explicitly or implicitly.
587  bool hasDefOfPhysReg(const MCInst &MI, unsigned Reg,
588  const MCRegisterInfo &RI) const;
589 };
590 
591 } // end namespace llvm
592 
593 #endif
unsigned getNumImplicitUses() const
Return the number of implicit uses this instruction has.
Definition: MCInstrDesc.h:515
unsigned getNumImplicitDefs() const
Return the number of implicit defs this instruct has.
Definition: MCInstrDesc.h:537
struct fuzzer::@309 Flags
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
bool isLookupPtrRegClass() const
Set if this operand is a pointer value and it requires a callback to look up its register class...
Definition: MCInstrDesc.h:90
bool isCommutable() const
Return true if this may be a 2- or 3-address instruction (of the form "X = op Y, Z, ..."), which produces the same result if Y and Z are exchanged.
Definition: MCInstrDesc.h:425
uint8_t Flags
These are flags from the MCOI::OperandFlags enum.
Definition: MCInstrDesc.h:79
unsigned char Size
Definition: MCInstrDesc.h:168
const MCPhysReg * getImplicitUses() const
Return a list of registers that are potentially read by any instance of this machine instruction...
Definition: MCInstrDesc.h:512
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:163
int findFirstPredOperandIdx() const
Find the index of the first operand in the operand list that is used to represent the predicate...
Definition: MCInstrDesc.h:574
bool hasUnmodeledSideEffects() const
Return true if this instruction has side effects that are not modeled by other flags.
Definition: MCInstrDesc.h:407
bool isRegSequenceLike() const
Return true if this instruction behaves the same way as the generic REG_SEQUENCE instructions.
Definition: MCInstrDesc.h:344
const_opInfo_iterator opInfo_begin() const
Definition: MCInstrDesc.h:214
bool isPseudo() const
Return true if this is a pseudo instruction that doesn&#39;t correspond to a real machine instruction...
Definition: MCInstrDesc.h:242
bool mayLoad() const
Return true if this instruction could possibly read memory.
Definition: MCInstrDesc.h:387
bool isReturn() const
Return true if the instruction is a return.
Definition: MCInstrDesc.h:245
bool isBranch() const
Returns true if this is a conditional, unconditional, or indirect branch.
Definition: MCInstrDesc.h:270
bool isCompare() const
Return true if this instruction is a comparison.
Definition: MCInstrDesc.h:304
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
Definition: MCInstrDesc.h:210
bool isExtractSubregLike() const
Return true if this instruction behaves the same way as the generic EXTRACT_SUBREG instructions...
Definition: MCInstrDesc.h:357
Reg
All possible values of the reg field in the ModR/M byte.
bool isSelect() const
Return true if this is a select instruction.
Definition: MCInstrDesc.h:314
uint8_t OperandType
Information about the type of the operand.
Definition: MCInstrDesc.h:82
bool isConvertibleTo3Addr() const
Return true if this is a 2-address instruction which can be changed into a 3-address instruction if n...
Definition: MCInstrDesc.h:441
bool isRematerializable() const
Returns true if this instruction is a candidate for remat.
Definition: MCInstrDesc.h:469
uint32_t Constraints
The lower 16 bits are used to specify which constraints are set.
Definition: MCInstrDesc.h:86
bool isAsCheapAsAMove() const
Returns true if this instruction has the same cost (or less) than a move instruction.
Definition: MCInstrDesc.h:482
bool isPredicate() const
Set if this is one of the operands that made up of the predicate operand that controls an isPredicabl...
Definition: MCInstrDesc.h:96
bool hasExtraDefRegAllocReq() const
Returns true if this instruction def operands have special register allocation requirements that are ...
Definition: MCInstrDesc.h:500
bool isMoveImmediate() const
Return true if this instruction is a move immediate (including conditional moves) instruction...
Definition: MCInstrDesc.h:308
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:159
unsigned short NumOperands
Definition: MCInstrDesc.h:166
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
Flag
These should be considered private to the implementation of the MCInstrDesc class.
Definition: MCInstrDesc.h:121
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
unsigned getSchedClass() const
Return the scheduling class for this instruction.
Definition: MCInstrDesc.h:565
bool isGenericType() const
Definition: MCInstrDesc.h:101
const MCPhysReg * getImplicitDefs() const
Return a list of registers that are potentially written by any instance of this machine instruction...
Definition: MCInstrDesc.h:534
bool hasExtraSrcRegAllocReq() const
Returns true if this instruction source operands have special register allocation requirements that a...
Definition: MCInstrDesc.h:490
unsigned const MachineRegisterInfo * MRI
bool isOptionalDef() const
Set if this operand is a optional def.
Definition: MCInstrDesc.h:99
bool hasOptionalDef() const
Set if this instruction has an optional definition, e.g.
Definition: MCInstrDesc.h:238
bool isBarrier() const
Returns true if the specified instruction stops control flow from executing the instruction immediate...
Definition: MCInstrDesc.h:256
bool isVariadic() const
Return true if this instruction can have a variable number of operands.
Definition: MCInstrDesc.h:234
bool isConditionalBranch() const
Return true if this is a branch which may fall through to the next instruction or may transfer contro...
Definition: MCInstrDesc.h:280
int64_t DeprecatedFeature
Definition: MCInstrDesc.h:178
OperandFlags
These are flags set on operands, but should be considered private, all access should go through the M...
Definition: MCInstrDesc.h:41
const MCPhysReg * ImplicitDefs
Definition: MCInstrDesc.h:173
bool isPredicable() const
Return true if this instruction has a predicate operand that controls execution.
Definition: MCInstrDesc.h:301
bool isIndirectBranch() const
Return true if this is an indirect branch, such as a branch through a register.
Definition: MCInstrDesc.h:274
bool hasPostISelHook() const
Return true if this instruction requires adjustment after instruction selection by calling a target h...
Definition: MCInstrDesc.h:461
unsigned char NumDefs
Definition: MCInstrDesc.h:167
bool isAdd() const
Return true if the instruction is an add instruction.
Definition: MCInstrDesc.h:248
bool isNotDuplicable() const
Return true if this instruction cannot be safely duplicated.
Definition: MCInstrDesc.h:319
int getOperandConstraint(unsigned OpNum, MCOI::OperandConstraint Constraint) const
Returns the value of the specific constraint if it is set.
Definition: MCInstrDesc.h:187
iterator_range< T > make_range(T x, T y)
Convenience function for iterating over sub-ranges.
bool isInsertSubregLike() const
Return true if this instruction behaves the same way as the generic INSERT_SUBREG instructions...
Definition: MCInstrDesc.h:371
bool hasDelaySlot() const
Returns true if the specified instruction has a delay slot which must be filled by the code generator...
Definition: MCInstrDesc.h:323
bool isBitcast() const
Return true if this instruction is a bitcast instruction.
Definition: MCInstrDesc.h:311
unsigned getNumDefs() const
Return the number of MachineOperands that are register definitions.
Definition: MCInstrDesc.h:225
unsigned short Opcode
Definition: MCInstrDesc.h:165
A range adaptor for a pair of iterators.
bool isConvergent() const
Return true if this instruction is convergent.
Definition: MCInstrDesc.h:378
bool mayStore() const
Return true if this instruction could possibly modify memory.
Definition: MCInstrDesc.h:393
bool isUnconditionalBranch() const
Return true if this is a branch which always transfers control flow to some other block...
Definition: MCInstrDesc.h:288
constexpr char Size[]
Key for Kernel::Arg::Metadata::mSize.
OperandType
Operands are tagged with one of the values of this enum.
Definition: MCInstrDesc.h:44
bool canFoldAsLoad() const
Return true for instructions that can be folded as memory operands in other instructions.
Definition: MCInstrDesc.h:332
int16_t RegClass
This specifies the register class enumeration of the operand if the operand is a register.
Definition: MCInstrDesc.h:76
const_opInfo_iterator opInfo_end() const
Definition: MCInstrDesc.h:215
bool isCall() const
Return true if the instruction is a call.
Definition: MCInstrDesc.h:251
MCSubtargetInfo - Generic base class for all target subtargets.
iterator_range< const_opInfo_iterator > operands() const
Definition: MCInstrDesc.h:217
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static bool isBranch(unsigned Opcode)
bool hasImplicitUseOfPhysReg(unsigned Reg) const
Return true if this instruction implicitly uses the specified physical register.
Definition: MCInstrDesc.h:548
bool isTerminator() const
Returns true if this instruction part of the terminator for a basic block.
Definition: MCInstrDesc.h:264
const MCOperandInfo * OpInfo
Definition: MCInstrDesc.h:174
unsigned getOpcode() const
Return the opcode number for this descriptor.
Definition: MCInstrDesc.h:203
unsigned getGenericTypeIndex() const
Definition: MCInstrDesc.h:106
IRTranslator LLVM IR MI
bool usesCustomInsertionHook() const
Return true if this instruction requires custom insertion support when the DAG scheduler is inserting...
Definition: MCInstrDesc.h:453
This holds information about one operand of a machine instruction, indicating the register class for ...
Definition: MCInstrDesc.h:70
uint64_t getFlags() const
Return flags of this instruction.
Definition: MCInstrDesc.h:228
unsigned short SchedClass
Definition: MCInstrDesc.h:169
const MCPhysReg * ImplicitUses
Definition: MCInstrDesc.h:172
unsigned getSize() const
Return the number of bytes in the encoding of this instruction, or zero if the encoding size cannot b...
Definition: MCInstrDesc.h:569