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MCInstrDesc.h
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1 //===-- llvm/MC/MCInstrDesc.h - Instruction Descriptors -*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines the MCOperandInfo and MCInstrDesc classes, which
11 // are used to describe target instructions and their operands.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #ifndef LLVM_MC_MCINSTRDESC_H
16 #define LLVM_MC_MCINSTRDESC_H
17 
18 #include "llvm/MC/MCRegisterInfo.h"
19 #include "llvm/Support/DataTypes.h"
20 #include <string>
21 
22 namespace llvm {
23  class MCInst;
24  class MCSubtargetInfo;
25  class FeatureBitset;
26 
27 //===----------------------------------------------------------------------===//
28 // Machine Operand Flags and Description
29 //===----------------------------------------------------------------------===//
30 
31 namespace MCOI {
32 // Operand constraints
34  TIED_TO = 0, // Must be allocated the same register as.
35  EARLY_CLOBBER // Operand is an early clobber register operand
36 };
37 
38 /// These are flags set on operands, but should be considered
39 /// private, all access should go through the MCOperandInfo accessors.
40 /// See the accessors for a description of what these are.
42 
43 /// Operands are tagged with one of the values of this enum.
50 
59 
61 };
62 
63 }
64 
65 /// This holds information about one operand of a machine instruction,
66 /// indicating the register class for register operands, etc.
68 public:
69  /// This specifies the register class enumeration of the operand
70  /// if the operand is a register. If isLookupPtrRegClass is set, then this is
71  /// an index that is passed to TargetRegisterInfo::getPointerRegClass(x) to
72  /// get a dynamic register class.
73  int16_t RegClass;
74 
75  /// These are flags from the MCOI::OperandFlags enum.
76  uint8_t Flags;
77 
78  /// Information about the type of the operand.
79  uint8_t OperandType;
80  /// The lower 16 bits are used to specify which constraints are set.
81  /// The higher 16 bits are used to specify the value of constraints (4 bits
82  /// each).
84 
85  /// Set if this operand is a pointer value and it requires a callback
86  /// to look up its register class.
87  bool isLookupPtrRegClass() const {
88  return Flags & (1 << MCOI::LookupPtrRegClass);
89  }
90 
91  /// Set if this is one of the operands that made up of the predicate
92  /// operand that controls an isPredicable() instruction.
93  bool isPredicate() const { return Flags & (1 << MCOI::Predicate); }
94 
95  /// Set if this operand is a optional def.
96  bool isOptionalDef() const { return Flags & (1 << MCOI::OptionalDef); }
97 
98  bool isGenericType() const {
99  return OperandType >= MCOI::OPERAND_FIRST_GENERIC &&
100  OperandType <= MCOI::OPERAND_LAST_GENERIC;
101  }
102 
103  unsigned getGenericTypeIndex() const {
104  assert(isGenericType() && "non-generic types don't have an index");
105  return OperandType - MCOI::OPERAND_FIRST_GENERIC;
106  }
107 };
108 
109 //===----------------------------------------------------------------------===//
110 // Machine Instruction Flags and Description
111 //===----------------------------------------------------------------------===//
112 
113 namespace MCID {
114 /// These should be considered private to the implementation of the
115 /// MCInstrDesc class. Clients should use the predicate methods on MCInstrDesc,
116 /// not use these directly. These all correspond to bitfields in the
117 /// MCInstrDesc::Flags field.
118 enum Flag {
119  Variadic = 0,
154 };
155 }
156 
157 /// Describe properties that are true of each instruction in the target
158 /// description file. This captures information about side effects, register
159 /// use and many other things. There is one instance of this struct for each
160 /// target instruction class, and the MachineInstr class points to this struct
161 /// directly to describe itself.
162 class MCInstrDesc {
163 public:
164  unsigned short Opcode; // The opcode number
165  unsigned short NumOperands; // Num of args (may be more if variable_ops)
166  unsigned char NumDefs; // Num of args that are definitions
167  unsigned char Size; // Number of bytes in encoding.
168  unsigned short SchedClass; // enum identifying instr sched class
169  uint64_t Flags; // Flags identifying machine instr class
170  uint64_t TSFlags; // Target Specific Flag values
171  const MCPhysReg *ImplicitUses; // Registers implicitly read by this instr
172  const MCPhysReg *ImplicitDefs; // Registers implicitly defined by this instr
173  const MCOperandInfo *OpInfo; // 'NumOperands' entries about operands
174  // Subtarget feature that this is deprecated on, if any
175  // -1 implies this is not deprecated by any single feature. It may still be
176  // deprecated due to a "complex" reason, below.
178 
179  // A complex method to determine if a certain instruction is deprecated or
180  // not, and return the reason for deprecation.
181  bool (*ComplexDeprecationInfo)(MCInst &, const MCSubtargetInfo &,
182  std::string &);
183 
184  /// Returns the value of the specific constraint if
185  /// it is set. Returns -1 if it is not set.
186  int getOperandConstraint(unsigned OpNum,
187  MCOI::OperandConstraint Constraint) const {
188  if (OpNum < NumOperands &&
189  (OpInfo[OpNum].Constraints & (1 << Constraint))) {
190  unsigned Pos = 16 + Constraint * 4;
191  return (int)(OpInfo[OpNum].Constraints >> Pos) & 0xf;
192  }
193  return -1;
194  }
195 
196  /// Returns true if a certain instruction is deprecated and if so
197  /// returns the reason in \p Info.
198  bool getDeprecatedInfo(MCInst &MI, const MCSubtargetInfo &STI,
199  std::string &Info) const;
200 
201  /// Return the opcode number for this descriptor.
202  unsigned getOpcode() const { return Opcode; }
203 
204  /// Return the number of declared MachineOperands for this
205  /// MachineInstruction. Note that variadic (isVariadic() returns true)
206  /// instructions may have additional operands at the end of the list, and note
207  /// that the machine instruction may include implicit register def/uses as
208  /// well.
209  unsigned getNumOperands() const { return NumOperands; }
210 
212 
213  const_opInfo_iterator opInfo_begin() const { return OpInfo; }
214  const_opInfo_iterator opInfo_end() const { return OpInfo + NumOperands; }
215 
217  return make_range(opInfo_begin(), opInfo_end());
218  }
219 
220  /// Return the number of MachineOperands that are register
221  /// definitions. Register definitions always occur at the start of the
222  /// machine operand list. This is the number of "outs" in the .td file,
223  /// and does not include implicit defs.
224  unsigned getNumDefs() const { return NumDefs; }
225 
226  /// Return flags of this instruction.
227  uint64_t getFlags() const { return Flags; }
228 
229  /// Return true if this instruction can have a variable number of
230  /// operands. In this case, the variable operands will be after the normal
231  /// operands but before the implicit definitions and uses (if any are
232  /// present).
233  bool isVariadic() const { return Flags & (1ULL << MCID::Variadic); }
234 
235  /// Set if this instruction has an optional definition, e.g.
236  /// ARM instructions which can set condition code if 's' bit is set.
237  bool hasOptionalDef() const { return Flags & (1ULL << MCID::HasOptionalDef); }
238 
239  /// Return true if this is a pseudo instruction that doesn't
240  /// correspond to a real machine instruction.
241  bool isPseudo() const { return Flags & (1ULL << MCID::Pseudo); }
242 
243  /// Return true if the instruction is a return.
244  bool isReturn() const { return Flags & (1ULL << MCID::Return); }
245 
246  /// Return true if the instruction is an add instruction.
247  bool isAdd() const { return Flags & (1ULL << MCID::Add); }
248 
249  /// Return true if this instruction is a trap.
250  bool isTrap() const { return Flags & (1ULL << MCID::Trap); }
251 
252  /// Return true if the instruction is a register to register move.
253  bool isMoveReg() const { return Flags & (1ULL << MCID::MoveReg); }
254 
255  /// Return true if the instruction is a call.
256  bool isCall() const { return Flags & (1ULL << MCID::Call); }
257 
258  /// Returns true if the specified instruction stops control flow
259  /// from executing the instruction immediately following it. Examples include
260  /// unconditional branches and return instructions.
261  bool isBarrier() const { return Flags & (1ULL << MCID::Barrier); }
262 
263  /// Returns true if this instruction part of the terminator for
264  /// a basic block. Typically this is things like return and branch
265  /// instructions.
266  ///
267  /// Various passes use this to insert code into the bottom of a basic block,
268  /// but before control flow occurs.
269  bool isTerminator() const { return Flags & (1ULL << MCID::Terminator); }
270 
271  /// Returns true if this is a conditional, unconditional, or
272  /// indirect branch. Predicates below can be used to discriminate between
273  /// these cases, and the TargetInstrInfo::AnalyzeBranch method can be used to
274  /// get more information.
275  bool isBranch() const { return Flags & (1ULL << MCID::Branch); }
276 
277  /// Return true if this is an indirect branch, such as a
278  /// branch through a register.
279  bool isIndirectBranch() const { return Flags & (1ULL << MCID::IndirectBranch); }
280 
281  /// Return true if this is a branch which may fall
282  /// through to the next instruction or may transfer control flow to some other
283  /// block. The TargetInstrInfo::AnalyzeBranch method can be used to get more
284  /// information about this branch.
285  bool isConditionalBranch() const {
286  return isBranch() & !isBarrier() & !isIndirectBranch();
287  }
288 
289  /// Return true if this is a branch which always
290  /// transfers control flow to some other block. The
291  /// TargetInstrInfo::AnalyzeBranch method can be used to get more information
292  /// about this branch.
293  bool isUnconditionalBranch() const {
294  return isBranch() & isBarrier() & !isIndirectBranch();
295  }
296 
297  /// Return true if this is a branch or an instruction which directly
298  /// writes to the program counter. Considered 'may' affect rather than
299  /// 'does' affect as things like predication are not taken into account.
300  bool mayAffectControlFlow(const MCInst &MI, const MCRegisterInfo &RI) const;
301 
302  /// Return true if this instruction has a predicate operand
303  /// that controls execution. It may be set to 'always', or may be set to other
304  /// values. There are various methods in TargetInstrInfo that can be used to
305  /// control and modify the predicate in this instruction.
306  bool isPredicable() const { return Flags & (1ULL << MCID::Predicable); }
307 
308  /// Return true if this instruction is a comparison.
309  bool isCompare() const { return Flags & (1ULL << MCID::Compare); }
310 
311  /// Return true if this instruction is a move immediate
312  /// (including conditional moves) instruction.
313  bool isMoveImmediate() const { return Flags & (1ULL << MCID::MoveImm); }
314 
315  /// Return true if this instruction is a bitcast instruction.
316  bool isBitcast() const { return Flags & (1ULL << MCID::Bitcast); }
317 
318  /// Return true if this is a select instruction.
319  bool isSelect() const { return Flags & (1ULL << MCID::Select); }
320 
321  /// Return true if this instruction cannot be safely
322  /// duplicated. For example, if the instruction has a unique labels attached
323  /// to it, duplicating it would cause multiple definition errors.
324  bool isNotDuplicable() const { return Flags & (1ULL << MCID::NotDuplicable); }
325 
326  /// Returns true if the specified instruction has a delay slot which
327  /// must be filled by the code generator.
328  bool hasDelaySlot() const { return Flags & (1ULL << MCID::DelaySlot); }
329 
330  /// Return true for instructions that can be folded as memory operands
331  /// in other instructions. The most common use for this is instructions that
332  /// are simple loads from memory that don't modify the loaded value in any
333  /// way, but it can also be used for instructions that can be expressed as
334  /// constant-pool loads, such as V_SETALLONES on x86, to allow them to be
335  /// folded when it is beneficial. This should only be set on instructions
336  /// that return a value in their only virtual register definition.
337  bool canFoldAsLoad() const { return Flags & (1ULL << MCID::FoldableAsLoad); }
338 
339  /// Return true if this instruction behaves
340  /// the same way as the generic REG_SEQUENCE instructions.
341  /// E.g., on ARM,
342  /// dX VMOVDRR rY, rZ
343  /// is equivalent to
344  /// dX = REG_SEQUENCE rY, ssub_0, rZ, ssub_1.
345  ///
346  /// Note that for the optimizers to be able to take advantage of
347  /// this property, TargetInstrInfo::getRegSequenceLikeInputs has to be
348  /// override accordingly.
349  bool isRegSequenceLike() const { return Flags & (1ULL << MCID::RegSequence); }
350 
351  /// Return true if this instruction behaves
352  /// the same way as the generic EXTRACT_SUBREG instructions.
353  /// E.g., on ARM,
354  /// rX, rY VMOVRRD dZ
355  /// is equivalent to two EXTRACT_SUBREG:
356  /// rX = EXTRACT_SUBREG dZ, ssub_0
357  /// rY = EXTRACT_SUBREG dZ, ssub_1
358  ///
359  /// Note that for the optimizers to be able to take advantage of
360  /// this property, TargetInstrInfo::getExtractSubregLikeInputs has to be
361  /// override accordingly.
362  bool isExtractSubregLike() const {
363  return Flags & (1ULL << MCID::ExtractSubreg);
364  }
365 
366  /// Return true if this instruction behaves
367  /// the same way as the generic INSERT_SUBREG instructions.
368  /// E.g., on ARM,
369  /// dX = VSETLNi32 dY, rZ, Imm
370  /// is equivalent to a INSERT_SUBREG:
371  /// dX = INSERT_SUBREG dY, rZ, translateImmToSubIdx(Imm)
372  ///
373  /// Note that for the optimizers to be able to take advantage of
374  /// this property, TargetInstrInfo::getInsertSubregLikeInputs has to be
375  /// override accordingly.
376  bool isInsertSubregLike() const { return Flags & (1ULL << MCID::InsertSubreg); }
377 
378 
379  /// Return true if this instruction is convergent.
380  ///
381  /// Convergent instructions may not be made control-dependent on any
382  /// additional values.
383  bool isConvergent() const { return Flags & (1ULL << MCID::Convergent); }
384 
385  //===--------------------------------------------------------------------===//
386  // Side Effect Analysis
387  //===--------------------------------------------------------------------===//
388 
389  /// Return true if this instruction could possibly read memory.
390  /// Instructions with this flag set are not necessarily simple load
391  /// instructions, they may load a value and modify it, for example.
392  bool mayLoad() const { return Flags & (1ULL << MCID::MayLoad); }
393 
394  /// Return true if this instruction could possibly modify memory.
395  /// Instructions with this flag set are not necessarily simple store
396  /// instructions, they may store a modified value based on their operands, or
397  /// may not actually modify anything, for example.
398  bool mayStore() const { return Flags & (1ULL << MCID::MayStore); }
399 
400  /// Return true if this instruction has side
401  /// effects that are not modeled by other flags. This does not return true
402  /// for instructions whose effects are captured by:
403  ///
404  /// 1. Their operand list and implicit definition/use list. Register use/def
405  /// info is explicit for instructions.
406  /// 2. Memory accesses. Use mayLoad/mayStore.
407  /// 3. Calling, branching, returning: use isCall/isReturn/isBranch.
408  ///
409  /// Examples of side effects would be modifying 'invisible' machine state like
410  /// a control register, flushing a cache, modifying a register invisible to
411  /// LLVM, etc.
412  bool hasUnmodeledSideEffects() const {
413  return Flags & (1ULL << MCID::UnmodeledSideEffects);
414  }
415 
416  //===--------------------------------------------------------------------===//
417  // Flags that indicate whether an instruction can be modified by a method.
418  //===--------------------------------------------------------------------===//
419 
420  /// Return true if this may be a 2- or 3-address instruction (of the
421  /// form "X = op Y, Z, ..."), which produces the same result if Y and Z are
422  /// exchanged. If this flag is set, then the
423  /// TargetInstrInfo::commuteInstruction method may be used to hack on the
424  /// instruction.
425  ///
426  /// Note that this flag may be set on instructions that are only commutable
427  /// sometimes. In these cases, the call to commuteInstruction will fail.
428  /// Also note that some instructions require non-trivial modification to
429  /// commute them.
430  bool isCommutable() const { return Flags & (1ULL << MCID::Commutable); }
431 
432  /// Return true if this is a 2-address instruction which can be changed
433  /// into a 3-address instruction if needed. Doing this transformation can be
434  /// profitable in the register allocator, because it means that the
435  /// instruction can use a 2-address form if possible, but degrade into a less
436  /// efficient form if the source and dest register cannot be assigned to the
437  /// same register. For example, this allows the x86 backend to turn a "shl
438  /// reg, 3" instruction into an LEA instruction, which is the same speed as
439  /// the shift but has bigger code size.
440  ///
441  /// If this returns true, then the target must implement the
442  /// TargetInstrInfo::convertToThreeAddress method for this instruction, which
443  /// is allowed to fail if the transformation isn't valid for this specific
444  /// instruction (e.g. shl reg, 4 on x86).
445  ///
446  bool isConvertibleTo3Addr() const {
447  return Flags & (1ULL << MCID::ConvertibleTo3Addr);
448  }
449 
450  /// Return true if this instruction requires custom insertion support
451  /// when the DAG scheduler is inserting it into a machine basic block. If
452  /// this is true for the instruction, it basically means that it is a pseudo
453  /// instruction used at SelectionDAG time that is expanded out into magic code
454  /// by the target when MachineInstrs are formed.
455  ///
456  /// If this is true, the TargetLoweringInfo::InsertAtEndOfBasicBlock method
457  /// is used to insert this into the MachineBasicBlock.
458  bool usesCustomInsertionHook() const {
459  return Flags & (1ULL << MCID::UsesCustomInserter);
460  }
461 
462  /// Return true if this instruction requires *adjustment* after
463  /// instruction selection by calling a target hook. For example, this can be
464  /// used to fill in ARM 's' optional operand depending on whether the
465  /// conditional flag register is used.
466  bool hasPostISelHook() const { return Flags & (1ULL << MCID::HasPostISelHook); }
467 
468  /// Returns true if this instruction is a candidate for remat. This
469  /// flag is only used in TargetInstrInfo method isTriviallyRematerializable.
470  ///
471  /// If this flag is set, the isReallyTriviallyReMaterializable()
472  /// or isReallyTriviallyReMaterializableGeneric methods are called to verify
473  /// the instruction is really rematable.
474  bool isRematerializable() const {
475  return Flags & (1ULL << MCID::Rematerializable);
476  }
477 
478  /// Returns true if this instruction has the same cost (or less) than a
479  /// move instruction. This is useful during certain types of optimizations
480  /// (e.g., remat during two-address conversion or machine licm) where we would
481  /// like to remat or hoist the instruction, but not if it costs more than
482  /// moving the instruction into the appropriate register. Note, we are not
483  /// marking copies from and to the same register class with this flag.
484  ///
485  /// This method could be called by interface TargetInstrInfo::isAsCheapAsAMove
486  /// for different subtargets.
487  bool isAsCheapAsAMove() const { return Flags & (1ULL << MCID::CheapAsAMove); }
488 
489  /// Returns true if this instruction source operands have special
490  /// register allocation requirements that are not captured by the operand
491  /// register classes. e.g. ARM::STRD's two source registers must be an even /
492  /// odd pair, ARM::STM registers have to be in ascending order. Post-register
493  /// allocation passes should not attempt to change allocations for sources of
494  /// instructions with this flag.
495  bool hasExtraSrcRegAllocReq() const {
496  return Flags & (1ULL << MCID::ExtraSrcRegAllocReq);
497  }
498 
499  /// Returns true if this instruction def operands have special register
500  /// allocation requirements that are not captured by the operand register
501  /// classes. e.g. ARM::LDRD's two def registers must be an even / odd pair,
502  /// ARM::LDM registers have to be in ascending order. Post-register
503  /// allocation passes should not attempt to change allocations for definitions
504  /// of instructions with this flag.
505  bool hasExtraDefRegAllocReq() const {
506  return Flags & (1ULL << MCID::ExtraDefRegAllocReq);
507  }
508 
509  /// Return a list of registers that are potentially read by any
510  /// instance of this machine instruction. For example, on X86, the "adc"
511  /// instruction adds two register operands and adds the carry bit in from the
512  /// flags register. In this case, the instruction is marked as implicitly
513  /// reading the flags. Likewise, the variable shift instruction on X86 is
514  /// marked as implicitly reading the 'CL' register, which it always does.
515  ///
516  /// This method returns null if the instruction has no implicit uses.
517  const MCPhysReg *getImplicitUses() const { return ImplicitUses; }
518 
519  /// Return the number of implicit uses this instruction has.
520  unsigned getNumImplicitUses() const {
521  if (!ImplicitUses)
522  return 0;
523  unsigned i = 0;
524  for (; ImplicitUses[i]; ++i) /*empty*/
525  ;
526  return i;
527  }
528 
529  /// Return a list of registers that are potentially written by any
530  /// instance of this machine instruction. For example, on X86, many
531  /// instructions implicitly set the flags register. In this case, they are
532  /// marked as setting the FLAGS. Likewise, many instructions always deposit
533  /// their result in a physical register. For example, the X86 divide
534  /// instruction always deposits the quotient and remainder in the EAX/EDX
535  /// registers. For that instruction, this will return a list containing the
536  /// EAX/EDX/EFLAGS registers.
537  ///
538  /// This method returns null if the instruction has no implicit defs.
539  const MCPhysReg *getImplicitDefs() const { return ImplicitDefs; }
540 
541  /// Return the number of implicit defs this instruct has.
542  unsigned getNumImplicitDefs() const {
543  if (!ImplicitDefs)
544  return 0;
545  unsigned i = 0;
546  for (; ImplicitDefs[i]; ++i) /*empty*/
547  ;
548  return i;
549  }
550 
551  /// Return true if this instruction implicitly
552  /// uses the specified physical register.
553  bool hasImplicitUseOfPhysReg(unsigned Reg) const {
554  if (const MCPhysReg *ImpUses = ImplicitUses)
555  for (; *ImpUses; ++ImpUses)
556  if (*ImpUses == Reg)
557  return true;
558  return false;
559  }
560 
561  /// Return true if this instruction implicitly
562  /// defines the specified physical register.
563  bool hasImplicitDefOfPhysReg(unsigned Reg,
564  const MCRegisterInfo *MRI = nullptr) const;
565 
566  /// Return the scheduling class for this instruction. The
567  /// scheduling class is an index into the InstrItineraryData table. This
568  /// returns zero if there is no known scheduling information for the
569  /// instruction.
570  unsigned getSchedClass() const { return SchedClass; }
571 
572  /// Return the number of bytes in the encoding of this instruction,
573  /// or zero if the encoding size cannot be known from the opcode.
574  unsigned getSize() const { return Size; }
575 
576  /// Find the index of the first operand in the
577  /// operand list that is used to represent the predicate. It returns -1 if
578  /// none is found.
580  if (isPredicable()) {
581  for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
582  if (OpInfo[i].isPredicate())
583  return i;
584  }
585  return -1;
586  }
587 
588  /// Return true if this instruction defines the specified physical
589  /// register, either explicitly or implicitly.
590  bool hasDefOfPhysReg(const MCInst &MI, unsigned Reg,
591  const MCRegisterInfo &RI) const;
592 };
593 
594 } // end namespace llvm
595 
596 #endif
unsigned getNumImplicitUses() const
Return the number of implicit uses this instruction has.
Definition: MCInstrDesc.h:520
bool isMoveReg() const
Return true if the instruction is a register to register move.
Definition: MCInstrDesc.h:253
unsigned getNumImplicitDefs() const
Return the number of implicit defs this instruct has.
Definition: MCInstrDesc.h:542
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
bool isLookupPtrRegClass() const
Set if this operand is a pointer value and it requires a callback to look up its register class...
Definition: MCInstrDesc.h:87
bool isCommutable() const
Return true if this may be a 2- or 3-address instruction (of the form "X = op Y, Z, ..."), which produces the same result if Y and Z are exchanged.
Definition: MCInstrDesc.h:430
uint8_t Flags
These are flags from the MCOI::OperandFlags enum.
Definition: MCInstrDesc.h:76
unsigned char Size
Definition: MCInstrDesc.h:167
const MCPhysReg * getImplicitUses() const
Return a list of registers that are potentially read by any instance of this machine instruction...
Definition: MCInstrDesc.h:517
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:162
unsigned Reg
int findFirstPredOperandIdx() const
Find the index of the first operand in the operand list that is used to represent the predicate...
Definition: MCInstrDesc.h:579
bool hasUnmodeledSideEffects() const
Return true if this instruction has side effects that are not modeled by other flags.
Definition: MCInstrDesc.h:412
bool isRegSequenceLike() const
Return true if this instruction behaves the same way as the generic REG_SEQUENCE instructions.
Definition: MCInstrDesc.h:349
const_opInfo_iterator opInfo_begin() const
Definition: MCInstrDesc.h:213
bool isPseudo() const
Return true if this is a pseudo instruction that doesn&#39;t correspond to a real machine instruction...
Definition: MCInstrDesc.h:241
bool mayLoad() const
Return true if this instruction could possibly read memory.
Definition: MCInstrDesc.h:392
bool isReturn() const
Return true if the instruction is a return.
Definition: MCInstrDesc.h:244
bool isBranch() const
Returns true if this is a conditional, unconditional, or indirect branch.
Definition: MCInstrDesc.h:275
bool isCompare() const
Return true if this instruction is a comparison.
Definition: MCInstrDesc.h:309
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
Definition: MCInstrDesc.h:209
bool isTrap() const
Return true if this instruction is a trap.
Definition: MCInstrDesc.h:250
bool isExtractSubregLike() const
Return true if this instruction behaves the same way as the generic EXTRACT_SUBREG instructions...
Definition: MCInstrDesc.h:362
bool isSelect() const
Return true if this is a select instruction.
Definition: MCInstrDesc.h:319
uint8_t OperandType
Information about the type of the operand.
Definition: MCInstrDesc.h:79
bool isConvertibleTo3Addr() const
Return true if this is a 2-address instruction which can be changed into a 3-address instruction if n...
Definition: MCInstrDesc.h:446
bool isRematerializable() const
Returns true if this instruction is a candidate for remat.
Definition: MCInstrDesc.h:474
uint32_t Constraints
The lower 16 bits are used to specify which constraints are set.
Definition: MCInstrDesc.h:83
bool isAsCheapAsAMove() const
Returns true if this instruction has the same cost (or less) than a move instruction.
Definition: MCInstrDesc.h:487
bool isPredicate() const
Set if this is one of the operands that made up of the predicate operand that controls an isPredicabl...
Definition: MCInstrDesc.h:93
bool hasExtraDefRegAllocReq() const
Returns true if this instruction def operands have special register allocation requirements that are ...
Definition: MCInstrDesc.h:505
bool isMoveImmediate() const
Return true if this instruction is a move immediate (including conditional moves) instruction...
Definition: MCInstrDesc.h:313
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:161
unsigned short NumOperands
Definition: MCInstrDesc.h:165
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
Flag
These should be considered private to the implementation of the MCInstrDesc class.
Definition: MCInstrDesc.h:118
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
unsigned getSchedClass() const
Return the scheduling class for this instruction.
Definition: MCInstrDesc.h:570
bool isGenericType() const
Definition: MCInstrDesc.h:98
const MCPhysReg * getImplicitDefs() const
Return a list of registers that are potentially written by any instance of this machine instruction...
Definition: MCInstrDesc.h:539
bool hasExtraSrcRegAllocReq() const
Returns true if this instruction source operands have special register allocation requirements that a...
Definition: MCInstrDesc.h:495
unsigned const MachineRegisterInfo * MRI
bool isOptionalDef() const
Set if this operand is a optional def.
Definition: MCInstrDesc.h:96
bool hasOptionalDef() const
Set if this instruction has an optional definition, e.g.
Definition: MCInstrDesc.h:237
bool isBarrier() const
Returns true if the specified instruction stops control flow from executing the instruction immediate...
Definition: MCInstrDesc.h:261
bool isVariadic() const
Return true if this instruction can have a variable number of operands.
Definition: MCInstrDesc.h:233
bool isConditionalBranch() const
Return true if this is a branch which may fall through to the next instruction or may transfer contro...
Definition: MCInstrDesc.h:285
int64_t DeprecatedFeature
Definition: MCInstrDesc.h:177
OperandFlags
These are flags set on operands, but should be considered private, all access should go through the M...
Definition: MCInstrDesc.h:41
const MCPhysReg * ImplicitDefs
Definition: MCInstrDesc.h:172
bool isPredicable() const
Return true if this instruction has a predicate operand that controls execution.
Definition: MCInstrDesc.h:306
bool isIndirectBranch() const
Return true if this is an indirect branch, such as a branch through a register.
Definition: MCInstrDesc.h:279
bool hasPostISelHook() const
Return true if this instruction requires adjustment after instruction selection by calling a target h...
Definition: MCInstrDesc.h:466
unsigned char NumDefs
Definition: MCInstrDesc.h:166
bool isAdd() const
Return true if the instruction is an add instruction.
Definition: MCInstrDesc.h:247
bool isNotDuplicable() const
Return true if this instruction cannot be safely duplicated.
Definition: MCInstrDesc.h:324
int getOperandConstraint(unsigned OpNum, MCOI::OperandConstraint Constraint) const
Returns the value of the specific constraint if it is set.
Definition: MCInstrDesc.h:186
iterator_range< T > make_range(T x, T y)
Convenience function for iterating over sub-ranges.
bool isInsertSubregLike() const
Return true if this instruction behaves the same way as the generic INSERT_SUBREG instructions...
Definition: MCInstrDesc.h:376
bool hasDelaySlot() const
Returns true if the specified instruction has a delay slot which must be filled by the code generator...
Definition: MCInstrDesc.h:328
bool isBitcast() const
Return true if this instruction is a bitcast instruction.
Definition: MCInstrDesc.h:316
unsigned getNumDefs() const
Return the number of MachineOperands that are register definitions.
Definition: MCInstrDesc.h:224
unsigned short Opcode
Definition: MCInstrDesc.h:164
A range adaptor for a pair of iterators.
bool isConvergent() const
Return true if this instruction is convergent.
Definition: MCInstrDesc.h:383
bool mayStore() const
Return true if this instruction could possibly modify memory.
Definition: MCInstrDesc.h:398
bool isUnconditionalBranch() const
Return true if this is a branch which always transfers control flow to some other block...
Definition: MCInstrDesc.h:293
OperandType
Operands are tagged with one of the values of this enum.
Definition: MCInstrDesc.h:44
bool canFoldAsLoad() const
Return true for instructions that can be folded as memory operands in other instructions.
Definition: MCInstrDesc.h:337
int16_t RegClass
This specifies the register class enumeration of the operand if the operand is a register.
Definition: MCInstrDesc.h:73
const_opInfo_iterator opInfo_end() const
Definition: MCInstrDesc.h:214
bool isCall() const
Return true if the instruction is a call.
Definition: MCInstrDesc.h:256
Generic base class for all target subtargets.
iterator_range< const_opInfo_iterator > operands() const
Definition: MCInstrDesc.h:216
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static bool isBranch(unsigned Opcode)
bool hasImplicitUseOfPhysReg(unsigned Reg) const
Return true if this instruction implicitly uses the specified physical register.
Definition: MCInstrDesc.h:553
bool isTerminator() const
Returns true if this instruction part of the terminator for a basic block.
Definition: MCInstrDesc.h:269
constexpr char Size[]
Key for Kernel::Arg::Metadata::mSize.
const MCOperandInfo * OpInfo
Definition: MCInstrDesc.h:173
unsigned getOpcode() const
Return the opcode number for this descriptor.
Definition: MCInstrDesc.h:202
unsigned getGenericTypeIndex() const
Definition: MCInstrDesc.h:103
IRTranslator LLVM IR MI
bool usesCustomInsertionHook() const
Return true if this instruction requires custom insertion support when the DAG scheduler is inserting...
Definition: MCInstrDesc.h:458
This holds information about one operand of a machine instruction, indicating the register class for ...
Definition: MCInstrDesc.h:67
uint64_t getFlags() const
Return flags of this instruction.
Definition: MCInstrDesc.h:227
unsigned short SchedClass
Definition: MCInstrDesc.h:168
const MCPhysReg * ImplicitUses
Definition: MCInstrDesc.h:171
unsigned getSize() const
Return the number of bytes in the encoding of this instruction, or zero if the encoding size cannot b...
Definition: MCInstrDesc.h:574