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MCInstrDesc.h
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1 //===-- llvm/MC/MCInstrDesc.h - Instruction Descriptors -*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines the MCOperandInfo and MCInstrDesc classes, which
11 // are used to describe target instructions and their operands.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #ifndef LLVM_MC_MCINSTRDESC_H
16 #define LLVM_MC_MCINSTRDESC_H
17 
18 #include "llvm/MC/MCRegisterInfo.h"
19 #include "llvm/Support/DataTypes.h"
20 #include <string>
21 
22 namespace llvm {
23  class MCInst;
24  class MCSubtargetInfo;
25  class FeatureBitset;
26 
27 //===----------------------------------------------------------------------===//
28 // Machine Operand Flags and Description
29 //===----------------------------------------------------------------------===//
30 
31 namespace MCOI {
32 // Operand constraints
34  TIED_TO = 0, // Must be allocated the same register as.
35  EARLY_CLOBBER // Operand is an early clobber register operand
36 };
37 
38 /// These are flags set on operands, but should be considered
39 /// private, all access should go through the MCOperandInfo accessors.
40 /// See the accessors for a description of what these are.
42 
43 /// Operands are tagged with one of the values of this enum.
50 
59 
61 };
62 
63 }
64 
65 /// This holds information about one operand of a machine instruction,
66 /// indicating the register class for register operands, etc.
68 public:
69  /// This specifies the register class enumeration of the operand
70  /// if the operand is a register. If isLookupPtrRegClass is set, then this is
71  /// an index that is passed to TargetRegisterInfo::getPointerRegClass(x) to
72  /// get a dynamic register class.
73  int16_t RegClass;
74 
75  /// These are flags from the MCOI::OperandFlags enum.
76  uint8_t Flags;
77 
78  /// Information about the type of the operand.
79  uint8_t OperandType;
80  /// The lower 16 bits are used to specify which constraints are set.
81  /// The higher 16 bits are used to specify the value of constraints (4 bits
82  /// each).
84 
85  /// Set if this operand is a pointer value and it requires a callback
86  /// to look up its register class.
87  bool isLookupPtrRegClass() const {
88  return Flags & (1 << MCOI::LookupPtrRegClass);
89  }
90 
91  /// Set if this is one of the operands that made up of the predicate
92  /// operand that controls an isPredicable() instruction.
93  bool isPredicate() const { return Flags & (1 << MCOI::Predicate); }
94 
95  /// Set if this operand is a optional def.
96  bool isOptionalDef() const { return Flags & (1 << MCOI::OptionalDef); }
97 
98  bool isGenericType() const {
99  return OperandType >= MCOI::OPERAND_FIRST_GENERIC &&
100  OperandType <= MCOI::OPERAND_LAST_GENERIC;
101  }
102 
103  unsigned getGenericTypeIndex() const {
104  assert(isGenericType() && "non-generic types don't have an index");
105  return OperandType - MCOI::OPERAND_FIRST_GENERIC;
106  }
107 };
108 
109 //===----------------------------------------------------------------------===//
110 // Machine Instruction Flags and Description
111 //===----------------------------------------------------------------------===//
112 
113 namespace MCID {
114 /// These should be considered private to the implementation of the
115 /// MCInstrDesc class. Clients should use the predicate methods on MCInstrDesc,
116 /// not use these directly. These all correspond to bitfields in the
117 /// MCInstrDesc::Flags field.
118 enum Flag {
119  Variadic = 0,
156 };
157 }
158 
159 /// Describe properties that are true of each instruction in the target
160 /// description file. This captures information about side effects, register
161 /// use and many other things. There is one instance of this struct for each
162 /// target instruction class, and the MachineInstr class points to this struct
163 /// directly to describe itself.
164 class MCInstrDesc {
165 public:
166  unsigned short Opcode; // The opcode number
167  unsigned short NumOperands; // Num of args (may be more if variable_ops)
168  unsigned char NumDefs; // Num of args that are definitions
169  unsigned char Size; // Number of bytes in encoding.
170  unsigned short SchedClass; // enum identifying instr sched class
171  uint64_t Flags; // Flags identifying machine instr class
172  uint64_t TSFlags; // Target Specific Flag values
173  const MCPhysReg *ImplicitUses; // Registers implicitly read by this instr
174  const MCPhysReg *ImplicitDefs; // Registers implicitly defined by this instr
175  const MCOperandInfo *OpInfo; // 'NumOperands' entries about operands
176  // Subtarget feature that this is deprecated on, if any
177  // -1 implies this is not deprecated by any single feature. It may still be
178  // deprecated due to a "complex" reason, below.
180 
181  // A complex method to determine if a certain instruction is deprecated or
182  // not, and return the reason for deprecation.
183  bool (*ComplexDeprecationInfo)(MCInst &, const MCSubtargetInfo &,
184  std::string &);
185 
186  /// Returns the value of the specific constraint if
187  /// it is set. Returns -1 if it is not set.
188  int getOperandConstraint(unsigned OpNum,
189  MCOI::OperandConstraint Constraint) const {
190  if (OpNum < NumOperands &&
191  (OpInfo[OpNum].Constraints & (1 << Constraint))) {
192  unsigned Pos = 16 + Constraint * 4;
193  return (int)(OpInfo[OpNum].Constraints >> Pos) & 0xf;
194  }
195  return -1;
196  }
197 
198  /// Returns true if a certain instruction is deprecated and if so
199  /// returns the reason in \p Info.
200  bool getDeprecatedInfo(MCInst &MI, const MCSubtargetInfo &STI,
201  std::string &Info) const;
202 
203  /// Return the opcode number for this descriptor.
204  unsigned getOpcode() const { return Opcode; }
205 
206  /// Return the number of declared MachineOperands for this
207  /// MachineInstruction. Note that variadic (isVariadic() returns true)
208  /// instructions may have additional operands at the end of the list, and note
209  /// that the machine instruction may include implicit register def/uses as
210  /// well.
211  unsigned getNumOperands() const { return NumOperands; }
212 
214 
215  const_opInfo_iterator opInfo_begin() const { return OpInfo; }
216  const_opInfo_iterator opInfo_end() const { return OpInfo + NumOperands; }
217 
219  return make_range(opInfo_begin(), opInfo_end());
220  }
221 
222  /// Return the number of MachineOperands that are register
223  /// definitions. Register definitions always occur at the start of the
224  /// machine operand list. This is the number of "outs" in the .td file,
225  /// and does not include implicit defs.
226  unsigned getNumDefs() const { return NumDefs; }
227 
228  /// Return flags of this instruction.
229  uint64_t getFlags() const { return Flags; }
230 
231  /// Return true if this instruction can have a variable number of
232  /// operands. In this case, the variable operands will be after the normal
233  /// operands but before the implicit definitions and uses (if any are
234  /// present).
235  bool isVariadic() const { return Flags & (1ULL << MCID::Variadic); }
236 
237  /// Set if this instruction has an optional definition, e.g.
238  /// ARM instructions which can set condition code if 's' bit is set.
239  bool hasOptionalDef() const { return Flags & (1ULL << MCID::HasOptionalDef); }
240 
241  /// Return true if this is a pseudo instruction that doesn't
242  /// correspond to a real machine instruction.
243  bool isPseudo() const { return Flags & (1ULL << MCID::Pseudo); }
244 
245  /// Return true if the instruction is a return.
246  bool isReturn() const { return Flags & (1ULL << MCID::Return); }
247 
248  /// Return true if the instruction is an add instruction.
249  bool isAdd() const { return Flags & (1ULL << MCID::Add); }
250 
251  /// Return true if this instruction is a trap.
252  bool isTrap() const { return Flags & (1ULL << MCID::Trap); }
253 
254  /// Return true if the instruction is a register to register move.
255  bool isMoveReg() const { return Flags & (1ULL << MCID::MoveReg); }
256 
257  /// Return true if the instruction is a call.
258  bool isCall() const { return Flags & (1ULL << MCID::Call); }
259 
260  /// Returns true if the specified instruction stops control flow
261  /// from executing the instruction immediately following it. Examples include
262  /// unconditional branches and return instructions.
263  bool isBarrier() const { return Flags & (1ULL << MCID::Barrier); }
264 
265  /// Returns true if this instruction part of the terminator for
266  /// a basic block. Typically this is things like return and branch
267  /// instructions.
268  ///
269  /// Various passes use this to insert code into the bottom of a basic block,
270  /// but before control flow occurs.
271  bool isTerminator() const { return Flags & (1ULL << MCID::Terminator); }
272 
273  /// Returns true if this is a conditional, unconditional, or
274  /// indirect branch. Predicates below can be used to discriminate between
275  /// these cases, and the TargetInstrInfo::AnalyzeBranch method can be used to
276  /// get more information.
277  bool isBranch() const { return Flags & (1ULL << MCID::Branch); }
278 
279  /// Return true if this is an indirect branch, such as a
280  /// branch through a register.
281  bool isIndirectBranch() const { return Flags & (1ULL << MCID::IndirectBranch); }
282 
283  /// Return true if this is a branch which may fall
284  /// through to the next instruction or may transfer control flow to some other
285  /// block. The TargetInstrInfo::AnalyzeBranch method can be used to get more
286  /// information about this branch.
287  bool isConditionalBranch() const {
288  return isBranch() & !isBarrier() & !isIndirectBranch();
289  }
290 
291  /// Return true if this is a branch which always
292  /// transfers control flow to some other block. The
293  /// TargetInstrInfo::AnalyzeBranch method can be used to get more information
294  /// about this branch.
295  bool isUnconditionalBranch() const {
296  return isBranch() & isBarrier() & !isIndirectBranch();
297  }
298 
299  /// Return true if this is a branch or an instruction which directly
300  /// writes to the program counter. Considered 'may' affect rather than
301  /// 'does' affect as things like predication are not taken into account.
302  bool mayAffectControlFlow(const MCInst &MI, const MCRegisterInfo &RI) const;
303 
304  /// Return true if this instruction has a predicate operand
305  /// that controls execution. It may be set to 'always', or may be set to other
306  /// values. There are various methods in TargetInstrInfo that can be used to
307  /// control and modify the predicate in this instruction.
308  bool isPredicable() const { return Flags & (1ULL << MCID::Predicable); }
309 
310  /// Return true if this instruction is a comparison.
311  bool isCompare() const { return Flags & (1ULL << MCID::Compare); }
312 
313  /// Return true if this instruction is a move immediate
314  /// (including conditional moves) instruction.
315  bool isMoveImmediate() const { return Flags & (1ULL << MCID::MoveImm); }
316 
317  /// Return true if this instruction is a bitcast instruction.
318  bool isBitcast() const { return Flags & (1ULL << MCID::Bitcast); }
319 
320  /// Return true if this is a select instruction.
321  bool isSelect() const { return Flags & (1ULL << MCID::Select); }
322 
323  /// Return true if this instruction cannot be safely
324  /// duplicated. For example, if the instruction has a unique labels attached
325  /// to it, duplicating it would cause multiple definition errors.
326  bool isNotDuplicable() const { return Flags & (1ULL << MCID::NotDuplicable); }
327 
328  /// Returns true if the specified instruction has a delay slot which
329  /// must be filled by the code generator.
330  bool hasDelaySlot() const { return Flags & (1ULL << MCID::DelaySlot); }
331 
332  /// Return true for instructions that can be folded as memory operands
333  /// in other instructions. The most common use for this is instructions that
334  /// are simple loads from memory that don't modify the loaded value in any
335  /// way, but it can also be used for instructions that can be expressed as
336  /// constant-pool loads, such as V_SETALLONES on x86, to allow them to be
337  /// folded when it is beneficial. This should only be set on instructions
338  /// that return a value in their only virtual register definition.
339  bool canFoldAsLoad() const { return Flags & (1ULL << MCID::FoldableAsLoad); }
340 
341  /// Return true if this instruction behaves
342  /// the same way as the generic REG_SEQUENCE instructions.
343  /// E.g., on ARM,
344  /// dX VMOVDRR rY, rZ
345  /// is equivalent to
346  /// dX = REG_SEQUENCE rY, ssub_0, rZ, ssub_1.
347  ///
348  /// Note that for the optimizers to be able to take advantage of
349  /// this property, TargetInstrInfo::getRegSequenceLikeInputs has to be
350  /// override accordingly.
351  bool isRegSequenceLike() const { return Flags & (1ULL << MCID::RegSequence); }
352 
353  /// Return true if this instruction behaves
354  /// the same way as the generic EXTRACT_SUBREG instructions.
355  /// E.g., on ARM,
356  /// rX, rY VMOVRRD dZ
357  /// is equivalent to two EXTRACT_SUBREG:
358  /// rX = EXTRACT_SUBREG dZ, ssub_0
359  /// rY = EXTRACT_SUBREG dZ, ssub_1
360  ///
361  /// Note that for the optimizers to be able to take advantage of
362  /// this property, TargetInstrInfo::getExtractSubregLikeInputs has to be
363  /// override accordingly.
364  bool isExtractSubregLike() const {
365  return Flags & (1ULL << MCID::ExtractSubreg);
366  }
367 
368  /// Return true if this instruction behaves
369  /// the same way as the generic INSERT_SUBREG instructions.
370  /// E.g., on ARM,
371  /// dX = VSETLNi32 dY, rZ, Imm
372  /// is equivalent to a INSERT_SUBREG:
373  /// dX = INSERT_SUBREG dY, rZ, translateImmToSubIdx(Imm)
374  ///
375  /// Note that for the optimizers to be able to take advantage of
376  /// this property, TargetInstrInfo::getInsertSubregLikeInputs has to be
377  /// override accordingly.
378  bool isInsertSubregLike() const { return Flags & (1ULL << MCID::InsertSubreg); }
379 
380 
381  /// Return true if this instruction is convergent.
382  ///
383  /// Convergent instructions may not be made control-dependent on any
384  /// additional values.
385  bool isConvergent() const { return Flags & (1ULL << MCID::Convergent); }
386 
387  /// Return true if variadic operands of this instruction are definitions.
388  bool variadicOpsAreDefs() const {
389  return Flags & (1ULL << MCID::VariadicOpsAreDefs);
390  }
391 
392  //===--------------------------------------------------------------------===//
393  // Side Effect Analysis
394  //===--------------------------------------------------------------------===//
395 
396  /// Return true if this instruction could possibly read memory.
397  /// Instructions with this flag set are not necessarily simple load
398  /// instructions, they may load a value and modify it, for example.
399  bool mayLoad() const { return Flags & (1ULL << MCID::MayLoad); }
400 
401  /// Return true if this instruction could possibly modify memory.
402  /// Instructions with this flag set are not necessarily simple store
403  /// instructions, they may store a modified value based on their operands, or
404  /// may not actually modify anything, for example.
405  bool mayStore() const { return Flags & (1ULL << MCID::MayStore); }
406 
407  /// Return true if this instruction has side
408  /// effects that are not modeled by other flags. This does not return true
409  /// for instructions whose effects are captured by:
410  ///
411  /// 1. Their operand list and implicit definition/use list. Register use/def
412  /// info is explicit for instructions.
413  /// 2. Memory accesses. Use mayLoad/mayStore.
414  /// 3. Calling, branching, returning: use isCall/isReturn/isBranch.
415  ///
416  /// Examples of side effects would be modifying 'invisible' machine state like
417  /// a control register, flushing a cache, modifying a register invisible to
418  /// LLVM, etc.
419  bool hasUnmodeledSideEffects() const {
420  return Flags & (1ULL << MCID::UnmodeledSideEffects);
421  }
422 
423  //===--------------------------------------------------------------------===//
424  // Flags that indicate whether an instruction can be modified by a method.
425  //===--------------------------------------------------------------------===//
426 
427  /// Return true if this may be a 2- or 3-address instruction (of the
428  /// form "X = op Y, Z, ..."), which produces the same result if Y and Z are
429  /// exchanged. If this flag is set, then the
430  /// TargetInstrInfo::commuteInstruction method may be used to hack on the
431  /// instruction.
432  ///
433  /// Note that this flag may be set on instructions that are only commutable
434  /// sometimes. In these cases, the call to commuteInstruction will fail.
435  /// Also note that some instructions require non-trivial modification to
436  /// commute them.
437  bool isCommutable() const { return Flags & (1ULL << MCID::Commutable); }
438 
439  /// Return true if this is a 2-address instruction which can be changed
440  /// into a 3-address instruction if needed. Doing this transformation can be
441  /// profitable in the register allocator, because it means that the
442  /// instruction can use a 2-address form if possible, but degrade into a less
443  /// efficient form if the source and dest register cannot be assigned to the
444  /// same register. For example, this allows the x86 backend to turn a "shl
445  /// reg, 3" instruction into an LEA instruction, which is the same speed as
446  /// the shift but has bigger code size.
447  ///
448  /// If this returns true, then the target must implement the
449  /// TargetInstrInfo::convertToThreeAddress method for this instruction, which
450  /// is allowed to fail if the transformation isn't valid for this specific
451  /// instruction (e.g. shl reg, 4 on x86).
452  ///
453  bool isConvertibleTo3Addr() const {
454  return Flags & (1ULL << MCID::ConvertibleTo3Addr);
455  }
456 
457  /// Return true if this instruction requires custom insertion support
458  /// when the DAG scheduler is inserting it into a machine basic block. If
459  /// this is true for the instruction, it basically means that it is a pseudo
460  /// instruction used at SelectionDAG time that is expanded out into magic code
461  /// by the target when MachineInstrs are formed.
462  ///
463  /// If this is true, the TargetLoweringInfo::InsertAtEndOfBasicBlock method
464  /// is used to insert this into the MachineBasicBlock.
465  bool usesCustomInsertionHook() const {
466  return Flags & (1ULL << MCID::UsesCustomInserter);
467  }
468 
469  /// Return true if this instruction requires *adjustment* after
470  /// instruction selection by calling a target hook. For example, this can be
471  /// used to fill in ARM 's' optional operand depending on whether the
472  /// conditional flag register is used.
473  bool hasPostISelHook() const { return Flags & (1ULL << MCID::HasPostISelHook); }
474 
475  /// Returns true if this instruction is a candidate for remat. This
476  /// flag is only used in TargetInstrInfo method isTriviallyRematerializable.
477  ///
478  /// If this flag is set, the isReallyTriviallyReMaterializable()
479  /// or isReallyTriviallyReMaterializableGeneric methods are called to verify
480  /// the instruction is really rematable.
481  bool isRematerializable() const {
482  return Flags & (1ULL << MCID::Rematerializable);
483  }
484 
485  /// Returns true if this instruction has the same cost (or less) than a
486  /// move instruction. This is useful during certain types of optimizations
487  /// (e.g., remat during two-address conversion or machine licm) where we would
488  /// like to remat or hoist the instruction, but not if it costs more than
489  /// moving the instruction into the appropriate register. Note, we are not
490  /// marking copies from and to the same register class with this flag.
491  ///
492  /// This method could be called by interface TargetInstrInfo::isAsCheapAsAMove
493  /// for different subtargets.
494  bool isAsCheapAsAMove() const { return Flags & (1ULL << MCID::CheapAsAMove); }
495 
496  /// Returns true if this instruction source operands have special
497  /// register allocation requirements that are not captured by the operand
498  /// register classes. e.g. ARM::STRD's two source registers must be an even /
499  /// odd pair, ARM::STM registers have to be in ascending order. Post-register
500  /// allocation passes should not attempt to change allocations for sources of
501  /// instructions with this flag.
502  bool hasExtraSrcRegAllocReq() const {
503  return Flags & (1ULL << MCID::ExtraSrcRegAllocReq);
504  }
505 
506  /// Returns true if this instruction def operands have special register
507  /// allocation requirements that are not captured by the operand register
508  /// classes. e.g. ARM::LDRD's two def registers must be an even / odd pair,
509  /// ARM::LDM registers have to be in ascending order. Post-register
510  /// allocation passes should not attempt to change allocations for definitions
511  /// of instructions with this flag.
512  bool hasExtraDefRegAllocReq() const {
513  return Flags & (1ULL << MCID::ExtraDefRegAllocReq);
514  }
515 
516  /// Return a list of registers that are potentially read by any
517  /// instance of this machine instruction. For example, on X86, the "adc"
518  /// instruction adds two register operands and adds the carry bit in from the
519  /// flags register. In this case, the instruction is marked as implicitly
520  /// reading the flags. Likewise, the variable shift instruction on X86 is
521  /// marked as implicitly reading the 'CL' register, which it always does.
522  ///
523  /// This method returns null if the instruction has no implicit uses.
524  const MCPhysReg *getImplicitUses() const { return ImplicitUses; }
525 
526  /// Return the number of implicit uses this instruction has.
527  unsigned getNumImplicitUses() const {
528  if (!ImplicitUses)
529  return 0;
530  unsigned i = 0;
531  for (; ImplicitUses[i]; ++i) /*empty*/
532  ;
533  return i;
534  }
535 
536  /// Return a list of registers that are potentially written by any
537  /// instance of this machine instruction. For example, on X86, many
538  /// instructions implicitly set the flags register. In this case, they are
539  /// marked as setting the FLAGS. Likewise, many instructions always deposit
540  /// their result in a physical register. For example, the X86 divide
541  /// instruction always deposits the quotient and remainder in the EAX/EDX
542  /// registers. For that instruction, this will return a list containing the
543  /// EAX/EDX/EFLAGS registers.
544  ///
545  /// This method returns null if the instruction has no implicit defs.
546  const MCPhysReg *getImplicitDefs() const { return ImplicitDefs; }
547 
548  /// Return the number of implicit defs this instruct has.
549  unsigned getNumImplicitDefs() const {
550  if (!ImplicitDefs)
551  return 0;
552  unsigned i = 0;
553  for (; ImplicitDefs[i]; ++i) /*empty*/
554  ;
555  return i;
556  }
557 
558  /// Return true if this instruction implicitly
559  /// uses the specified physical register.
560  bool hasImplicitUseOfPhysReg(unsigned Reg) const {
561  if (const MCPhysReg *ImpUses = ImplicitUses)
562  for (; *ImpUses; ++ImpUses)
563  if (*ImpUses == Reg)
564  return true;
565  return false;
566  }
567 
568  /// Return true if this instruction implicitly
569  /// defines the specified physical register.
570  bool hasImplicitDefOfPhysReg(unsigned Reg,
571  const MCRegisterInfo *MRI = nullptr) const;
572 
573  /// Return the scheduling class for this instruction. The
574  /// scheduling class is an index into the InstrItineraryData table. This
575  /// returns zero if there is no known scheduling information for the
576  /// instruction.
577  unsigned getSchedClass() const { return SchedClass; }
578 
579  /// Return the number of bytes in the encoding of this instruction,
580  /// or zero if the encoding size cannot be known from the opcode.
581  unsigned getSize() const { return Size; }
582 
583  /// Find the index of the first operand in the
584  /// operand list that is used to represent the predicate. It returns -1 if
585  /// none is found.
587  if (isPredicable()) {
588  for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
589  if (OpInfo[i].isPredicate())
590  return i;
591  }
592  return -1;
593  }
594 
595  /// Return true if this instruction defines the specified physical
596  /// register, either explicitly or implicitly.
597  bool hasDefOfPhysReg(const MCInst &MI, unsigned Reg,
598  const MCRegisterInfo &RI) const;
599 };
600 
601 } // end namespace llvm
602 
603 #endif
unsigned getNumImplicitUses() const
Return the number of implicit uses this instruction has.
Definition: MCInstrDesc.h:527
bool isMoveReg() const
Return true if the instruction is a register to register move.
Definition: MCInstrDesc.h:255
unsigned getNumImplicitDefs() const
Return the number of implicit defs this instruct has.
Definition: MCInstrDesc.h:549
This class represents lattice values for constants.
Definition: AllocatorList.h:24
bool isLookupPtrRegClass() const
Set if this operand is a pointer value and it requires a callback to look up its register class...
Definition: MCInstrDesc.h:87
bool isCommutable() const
Return true if this may be a 2- or 3-address instruction (of the form "X = op Y, Z, ..."), which produces the same result if Y and Z are exchanged.
Definition: MCInstrDesc.h:437
uint8_t Flags
These are flags from the MCOI::OperandFlags enum.
Definition: MCInstrDesc.h:76
unsigned char Size
Definition: MCInstrDesc.h:169
const MCPhysReg * getImplicitUses() const
Return a list of registers that are potentially read by any instance of this machine instruction...
Definition: MCInstrDesc.h:524
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:164
unsigned Reg
int findFirstPredOperandIdx() const
Find the index of the first operand in the operand list that is used to represent the predicate...
Definition: MCInstrDesc.h:586
bool hasUnmodeledSideEffects() const
Return true if this instruction has side effects that are not modeled by other flags.
Definition: MCInstrDesc.h:419
bool isRegSequenceLike() const
Return true if this instruction behaves the same way as the generic REG_SEQUENCE instructions.
Definition: MCInstrDesc.h:351
const_opInfo_iterator opInfo_begin() const
Definition: MCInstrDesc.h:215
bool isPseudo() const
Return true if this is a pseudo instruction that doesn&#39;t correspond to a real machine instruction...
Definition: MCInstrDesc.h:243
bool mayLoad() const
Return true if this instruction could possibly read memory.
Definition: MCInstrDesc.h:399
bool isReturn() const
Return true if the instruction is a return.
Definition: MCInstrDesc.h:246
bool isBranch() const
Returns true if this is a conditional, unconditional, or indirect branch.
Definition: MCInstrDesc.h:277
bool isCompare() const
Return true if this instruction is a comparison.
Definition: MCInstrDesc.h:311
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
Definition: MCInstrDesc.h:211
bool isTrap() const
Return true if this instruction is a trap.
Definition: MCInstrDesc.h:252
bool isExtractSubregLike() const
Return true if this instruction behaves the same way as the generic EXTRACT_SUBREG instructions...
Definition: MCInstrDesc.h:364
bool isSelect() const
Return true if this is a select instruction.
Definition: MCInstrDesc.h:321
uint8_t OperandType
Information about the type of the operand.
Definition: MCInstrDesc.h:79
bool isConvertibleTo3Addr() const
Return true if this is a 2-address instruction which can be changed into a 3-address instruction if n...
Definition: MCInstrDesc.h:453
bool isRematerializable() const
Returns true if this instruction is a candidate for remat.
Definition: MCInstrDesc.h:481
uint32_t Constraints
The lower 16 bits are used to specify which constraints are set.
Definition: MCInstrDesc.h:83
bool isAsCheapAsAMove() const
Returns true if this instruction has the same cost (or less) than a move instruction.
Definition: MCInstrDesc.h:494
bool isPredicate() const
Set if this is one of the operands that made up of the predicate operand that controls an isPredicabl...
Definition: MCInstrDesc.h:93
bool hasExtraDefRegAllocReq() const
Returns true if this instruction def operands have special register allocation requirements that are ...
Definition: MCInstrDesc.h:512
bool isMoveImmediate() const
Return true if this instruction is a move immediate (including conditional moves) instruction...
Definition: MCInstrDesc.h:315
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:161
unsigned short NumOperands
Definition: MCInstrDesc.h:167
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
Flag
These should be considered private to the implementation of the MCInstrDesc class.
Definition: MCInstrDesc.h:118
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
unsigned getSchedClass() const
Return the scheduling class for this instruction.
Definition: MCInstrDesc.h:577
bool isGenericType() const
Definition: MCInstrDesc.h:98
const MCPhysReg * getImplicitDefs() const
Return a list of registers that are potentially written by any instance of this machine instruction...
Definition: MCInstrDesc.h:546
bool hasExtraSrcRegAllocReq() const
Returns true if this instruction source operands have special register allocation requirements that a...
Definition: MCInstrDesc.h:502
unsigned const MachineRegisterInfo * MRI
bool isOptionalDef() const
Set if this operand is a optional def.
Definition: MCInstrDesc.h:96
bool hasOptionalDef() const
Set if this instruction has an optional definition, e.g.
Definition: MCInstrDesc.h:239
bool isBarrier() const
Returns true if the specified instruction stops control flow from executing the instruction immediate...
Definition: MCInstrDesc.h:263
bool isVariadic() const
Return true if this instruction can have a variable number of operands.
Definition: MCInstrDesc.h:235
bool isConditionalBranch() const
Return true if this is a branch which may fall through to the next instruction or may transfer contro...
Definition: MCInstrDesc.h:287
int64_t DeprecatedFeature
Definition: MCInstrDesc.h:179
OperandFlags
These are flags set on operands, but should be considered private, all access should go through the M...
Definition: MCInstrDesc.h:41
const MCPhysReg * ImplicitDefs
Definition: MCInstrDesc.h:174
bool isPredicable() const
Return true if this instruction has a predicate operand that controls execution.
Definition: MCInstrDesc.h:308
bool isIndirectBranch() const
Return true if this is an indirect branch, such as a branch through a register.
Definition: MCInstrDesc.h:281
bool hasPostISelHook() const
Return true if this instruction requires adjustment after instruction selection by calling a target h...
Definition: MCInstrDesc.h:473
unsigned char NumDefs
Definition: MCInstrDesc.h:168
bool isAdd() const
Return true if the instruction is an add instruction.
Definition: MCInstrDesc.h:249
bool isNotDuplicable() const
Return true if this instruction cannot be safely duplicated.
Definition: MCInstrDesc.h:326
int getOperandConstraint(unsigned OpNum, MCOI::OperandConstraint Constraint) const
Returns the value of the specific constraint if it is set.
Definition: MCInstrDesc.h:188
iterator_range< T > make_range(T x, T y)
Convenience function for iterating over sub-ranges.
bool isInsertSubregLike() const
Return true if this instruction behaves the same way as the generic INSERT_SUBREG instructions...
Definition: MCInstrDesc.h:378
bool hasDelaySlot() const
Returns true if the specified instruction has a delay slot which must be filled by the code generator...
Definition: MCInstrDesc.h:330
bool isBitcast() const
Return true if this instruction is a bitcast instruction.
Definition: MCInstrDesc.h:318
unsigned getNumDefs() const
Return the number of MachineOperands that are register definitions.
Definition: MCInstrDesc.h:226
unsigned short Opcode
Definition: MCInstrDesc.h:166
A range adaptor for a pair of iterators.
bool isConvergent() const
Return true if this instruction is convergent.
Definition: MCInstrDesc.h:385
bool mayStore() const
Return true if this instruction could possibly modify memory.
Definition: MCInstrDesc.h:405
bool isUnconditionalBranch() const
Return true if this is a branch which always transfers control flow to some other block...
Definition: MCInstrDesc.h:295
OperandType
Operands are tagged with one of the values of this enum.
Definition: MCInstrDesc.h:44
bool canFoldAsLoad() const
Return true for instructions that can be folded as memory operands in other instructions.
Definition: MCInstrDesc.h:339
int16_t RegClass
This specifies the register class enumeration of the operand if the operand is a register.
Definition: MCInstrDesc.h:73
const_opInfo_iterator opInfo_end() const
Definition: MCInstrDesc.h:216
bool isCall() const
Return true if the instruction is a call.
Definition: MCInstrDesc.h:258
Generic base class for all target subtargets.
uint32_t Size
Definition: Profile.cpp:47
bool variadicOpsAreDefs() const
Return true if variadic operands of this instruction are definitions.
Definition: MCInstrDesc.h:388
iterator_range< const_opInfo_iterator > operands() const
Definition: MCInstrDesc.h:218
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static bool isBranch(unsigned Opcode)
bool hasImplicitUseOfPhysReg(unsigned Reg) const
Return true if this instruction implicitly uses the specified physical register.
Definition: MCInstrDesc.h:560
bool isTerminator() const
Returns true if this instruction part of the terminator for a basic block.
Definition: MCInstrDesc.h:271
const MCOperandInfo * OpInfo
Definition: MCInstrDesc.h:175
unsigned getOpcode() const
Return the opcode number for this descriptor.
Definition: MCInstrDesc.h:204
unsigned getGenericTypeIndex() const
Definition: MCInstrDesc.h:103
IRTranslator LLVM IR MI
bool usesCustomInsertionHook() const
Return true if this instruction requires custom insertion support when the DAG scheduler is inserting...
Definition: MCInstrDesc.h:465
This holds information about one operand of a machine instruction, indicating the register class for ...
Definition: MCInstrDesc.h:67
uint64_t getFlags() const
Return flags of this instruction.
Definition: MCInstrDesc.h:229
unsigned short SchedClass
Definition: MCInstrDesc.h:170
const MCPhysReg * ImplicitUses
Definition: MCInstrDesc.h:173
unsigned getSize() const
Return the number of bytes in the encoding of this instruction, or zero if the encoding size cannot b...
Definition: MCInstrDesc.h:581