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MCInstrDesc.h
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1 //===-- llvm/MC/MCInstrDesc.h - Instruction Descriptors -*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines the MCOperandInfo and MCInstrDesc classes, which
11 // are used to describe target instructions and their operands.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #ifndef LLVM_MC_MCINSTRDESC_H
16 #define LLVM_MC_MCINSTRDESC_H
17 
18 #include "llvm/MC/MCRegisterInfo.h"
19 #include "llvm/Support/DataTypes.h"
20 #include <string>
21 
22 namespace llvm {
23  class MCInst;
24  class MCSubtargetInfo;
25  class FeatureBitset;
26 
27 //===----------------------------------------------------------------------===//
28 // Machine Operand Flags and Description
29 //===----------------------------------------------------------------------===//
30 
31 namespace MCOI {
32 // Operand constraints
34  TIED_TO = 0, // Must be allocated the same register as.
35  EARLY_CLOBBER // Operand is an early clobber register operand
36 };
37 
38 /// These are flags set on operands, but should be considered
39 /// private, all access should go through the MCOperandInfo accessors.
40 /// See the accessors for a description of what these are.
42 
43 /// Operands are tagged with one of the values of this enum.
50 
59 
61 };
62 
63 }
64 
65 /// This holds information about one operand of a machine instruction,
66 /// indicating the register class for register operands, etc.
68 public:
69  /// This specifies the register class enumeration of the operand
70  /// if the operand is a register. If isLookupPtrRegClass is set, then this is
71  /// an index that is passed to TargetRegisterInfo::getPointerRegClass(x) to
72  /// get a dynamic register class.
73  int16_t RegClass;
74 
75  /// These are flags from the MCOI::OperandFlags enum.
76  uint8_t Flags;
77 
78  /// Information about the type of the operand.
79  uint8_t OperandType;
80  /// The lower 16 bits are used to specify which constraints are set.
81  /// The higher 16 bits are used to specify the value of constraints (4 bits
82  /// each).
84 
85  /// Set if this operand is a pointer value and it requires a callback
86  /// to look up its register class.
87  bool isLookupPtrRegClass() const {
88  return Flags & (1 << MCOI::LookupPtrRegClass);
89  }
90 
91  /// Set if this is one of the operands that made up of the predicate
92  /// operand that controls an isPredicable() instruction.
93  bool isPredicate() const { return Flags & (1 << MCOI::Predicate); }
94 
95  /// Set if this operand is a optional def.
96  bool isOptionalDef() const { return Flags & (1 << MCOI::OptionalDef); }
97 
98  bool isGenericType() const {
99  return OperandType >= MCOI::OPERAND_FIRST_GENERIC &&
100  OperandType <= MCOI::OPERAND_LAST_GENERIC;
101  }
102 
103  unsigned getGenericTypeIndex() const {
104  assert(isGenericType() && "non-generic types don't have an index");
105  return OperandType - MCOI::OPERAND_FIRST_GENERIC;
106  }
107 };
108 
109 //===----------------------------------------------------------------------===//
110 // Machine Instruction Flags and Description
111 //===----------------------------------------------------------------------===//
112 
113 namespace MCID {
114 /// These should be considered private to the implementation of the
115 /// MCInstrDesc class. Clients should use the predicate methods on MCInstrDesc,
116 /// not use these directly. These all correspond to bitfields in the
117 /// MCInstrDesc::Flags field.
118 enum Flag {
119  Variadic = 0,
155 };
156 }
157 
158 /// Describe properties that are true of each instruction in the target
159 /// description file. This captures information about side effects, register
160 /// use and many other things. There is one instance of this struct for each
161 /// target instruction class, and the MachineInstr class points to this struct
162 /// directly to describe itself.
163 class MCInstrDesc {
164 public:
165  unsigned short Opcode; // The opcode number
166  unsigned short NumOperands; // Num of args (may be more if variable_ops)
167  unsigned char NumDefs; // Num of args that are definitions
168  unsigned char Size; // Number of bytes in encoding.
169  unsigned short SchedClass; // enum identifying instr sched class
170  uint64_t Flags; // Flags identifying machine instr class
171  uint64_t TSFlags; // Target Specific Flag values
172  const MCPhysReg *ImplicitUses; // Registers implicitly read by this instr
173  const MCPhysReg *ImplicitDefs; // Registers implicitly defined by this instr
174  const MCOperandInfo *OpInfo; // 'NumOperands' entries about operands
175  // Subtarget feature that this is deprecated on, if any
176  // -1 implies this is not deprecated by any single feature. It may still be
177  // deprecated due to a "complex" reason, below.
179 
180  // A complex method to determine if a certain instruction is deprecated or
181  // not, and return the reason for deprecation.
182  bool (*ComplexDeprecationInfo)(MCInst &, const MCSubtargetInfo &,
183  std::string &);
184 
185  /// Returns the value of the specific constraint if
186  /// it is set. Returns -1 if it is not set.
187  int getOperandConstraint(unsigned OpNum,
188  MCOI::OperandConstraint Constraint) const {
189  if (OpNum < NumOperands &&
190  (OpInfo[OpNum].Constraints & (1 << Constraint))) {
191  unsigned Pos = 16 + Constraint * 4;
192  return (int)(OpInfo[OpNum].Constraints >> Pos) & 0xf;
193  }
194  return -1;
195  }
196 
197  /// Returns true if a certain instruction is deprecated and if so
198  /// returns the reason in \p Info.
199  bool getDeprecatedInfo(MCInst &MI, const MCSubtargetInfo &STI,
200  std::string &Info) const;
201 
202  /// Return the opcode number for this descriptor.
203  unsigned getOpcode() const { return Opcode; }
204 
205  /// Return the number of declared MachineOperands for this
206  /// MachineInstruction. Note that variadic (isVariadic() returns true)
207  /// instructions may have additional operands at the end of the list, and note
208  /// that the machine instruction may include implicit register def/uses as
209  /// well.
210  unsigned getNumOperands() const { return NumOperands; }
211 
213 
214  const_opInfo_iterator opInfo_begin() const { return OpInfo; }
215  const_opInfo_iterator opInfo_end() const { return OpInfo + NumOperands; }
216 
218  return make_range(opInfo_begin(), opInfo_end());
219  }
220 
221  /// Return the number of MachineOperands that are register
222  /// definitions. Register definitions always occur at the start of the
223  /// machine operand list. This is the number of "outs" in the .td file,
224  /// and does not include implicit defs.
225  unsigned getNumDefs() const { return NumDefs; }
226 
227  /// Return flags of this instruction.
228  uint64_t getFlags() const { return Flags; }
229 
230  /// Return true if this instruction can have a variable number of
231  /// operands. In this case, the variable operands will be after the normal
232  /// operands but before the implicit definitions and uses (if any are
233  /// present).
234  bool isVariadic() const { return Flags & (1ULL << MCID::Variadic); }
235 
236  /// Set if this instruction has an optional definition, e.g.
237  /// ARM instructions which can set condition code if 's' bit is set.
238  bool hasOptionalDef() const { return Flags & (1ULL << MCID::HasOptionalDef); }
239 
240  /// Return true if this is a pseudo instruction that doesn't
241  /// correspond to a real machine instruction.
242  bool isPseudo() const { return Flags & (1ULL << MCID::Pseudo); }
243 
244  /// Return true if the instruction is a return.
245  bool isReturn() const { return Flags & (1ULL << MCID::Return); }
246 
247  /// Return true if the instruction is an add instruction.
248  bool isAdd() const { return Flags & (1ULL << MCID::Add); }
249 
250  /// Return true if this instruction is a trap.
251  bool isTrap() const { return Flags & (1ULL << MCID::Trap); }
252 
253  /// Return true if the instruction is a register to register move.
254  bool isMoveReg() const { return Flags & (1ULL << MCID::MoveReg); }
255 
256  /// Return true if the instruction is a call.
257  bool isCall() const { return Flags & (1ULL << MCID::Call); }
258 
259  /// Returns true if the specified instruction stops control flow
260  /// from executing the instruction immediately following it. Examples include
261  /// unconditional branches and return instructions.
262  bool isBarrier() const { return Flags & (1ULL << MCID::Barrier); }
263 
264  /// Returns true if this instruction part of the terminator for
265  /// a basic block. Typically this is things like return and branch
266  /// instructions.
267  ///
268  /// Various passes use this to insert code into the bottom of a basic block,
269  /// but before control flow occurs.
270  bool isTerminator() const { return Flags & (1ULL << MCID::Terminator); }
271 
272  /// Returns true if this is a conditional, unconditional, or
273  /// indirect branch. Predicates below can be used to discriminate between
274  /// these cases, and the TargetInstrInfo::AnalyzeBranch method can be used to
275  /// get more information.
276  bool isBranch() const { return Flags & (1ULL << MCID::Branch); }
277 
278  /// Return true if this is an indirect branch, such as a
279  /// branch through a register.
280  bool isIndirectBranch() const { return Flags & (1ULL << MCID::IndirectBranch); }
281 
282  /// Return true if this is a branch which may fall
283  /// through to the next instruction or may transfer control flow to some other
284  /// block. The TargetInstrInfo::AnalyzeBranch method can be used to get more
285  /// information about this branch.
286  bool isConditionalBranch() const {
287  return isBranch() & !isBarrier() & !isIndirectBranch();
288  }
289 
290  /// Return true if this is a branch which always
291  /// transfers control flow to some other block. The
292  /// TargetInstrInfo::AnalyzeBranch method can be used to get more information
293  /// about this branch.
294  bool isUnconditionalBranch() const {
295  return isBranch() & isBarrier() & !isIndirectBranch();
296  }
297 
298  /// Return true if this is a branch or an instruction which directly
299  /// writes to the program counter. Considered 'may' affect rather than
300  /// 'does' affect as things like predication are not taken into account.
301  bool mayAffectControlFlow(const MCInst &MI, const MCRegisterInfo &RI) const;
302 
303  /// Return true if this instruction has a predicate operand
304  /// that controls execution. It may be set to 'always', or may be set to other
305  /// values. There are various methods in TargetInstrInfo that can be used to
306  /// control and modify the predicate in this instruction.
307  bool isPredicable() const { return Flags & (1ULL << MCID::Predicable); }
308 
309  /// Return true if this instruction is a comparison.
310  bool isCompare() const { return Flags & (1ULL << MCID::Compare); }
311 
312  /// Return true if this instruction is a move immediate
313  /// (including conditional moves) instruction.
314  bool isMoveImmediate() const { return Flags & (1ULL << MCID::MoveImm); }
315 
316  /// Return true if this instruction is a bitcast instruction.
317  bool isBitcast() const { return Flags & (1ULL << MCID::Bitcast); }
318 
319  /// Return true if this is a select instruction.
320  bool isSelect() const { return Flags & (1ULL << MCID::Select); }
321 
322  /// Return true if this instruction cannot be safely
323  /// duplicated. For example, if the instruction has a unique labels attached
324  /// to it, duplicating it would cause multiple definition errors.
325  bool isNotDuplicable() const { return Flags & (1ULL << MCID::NotDuplicable); }
326 
327  /// Returns true if the specified instruction has a delay slot which
328  /// must be filled by the code generator.
329  bool hasDelaySlot() const { return Flags & (1ULL << MCID::DelaySlot); }
330 
331  /// Return true for instructions that can be folded as memory operands
332  /// in other instructions. The most common use for this is instructions that
333  /// are simple loads from memory that don't modify the loaded value in any
334  /// way, but it can also be used for instructions that can be expressed as
335  /// constant-pool loads, such as V_SETALLONES on x86, to allow them to be
336  /// folded when it is beneficial. This should only be set on instructions
337  /// that return a value in their only virtual register definition.
338  bool canFoldAsLoad() const { return Flags & (1ULL << MCID::FoldableAsLoad); }
339 
340  /// Return true if this instruction behaves
341  /// the same way as the generic REG_SEQUENCE instructions.
342  /// E.g., on ARM,
343  /// dX VMOVDRR rY, rZ
344  /// is equivalent to
345  /// dX = REG_SEQUENCE rY, ssub_0, rZ, ssub_1.
346  ///
347  /// Note that for the optimizers to be able to take advantage of
348  /// this property, TargetInstrInfo::getRegSequenceLikeInputs has to be
349  /// override accordingly.
350  bool isRegSequenceLike() const { return Flags & (1ULL << MCID::RegSequence); }
351 
352  /// Return true if this instruction behaves
353  /// the same way as the generic EXTRACT_SUBREG instructions.
354  /// E.g., on ARM,
355  /// rX, rY VMOVRRD dZ
356  /// is equivalent to two EXTRACT_SUBREG:
357  /// rX = EXTRACT_SUBREG dZ, ssub_0
358  /// rY = EXTRACT_SUBREG dZ, ssub_1
359  ///
360  /// Note that for the optimizers to be able to take advantage of
361  /// this property, TargetInstrInfo::getExtractSubregLikeInputs has to be
362  /// override accordingly.
363  bool isExtractSubregLike() const {
364  return Flags & (1ULL << MCID::ExtractSubreg);
365  }
366 
367  /// Return true if this instruction behaves
368  /// the same way as the generic INSERT_SUBREG instructions.
369  /// E.g., on ARM,
370  /// dX = VSETLNi32 dY, rZ, Imm
371  /// is equivalent to a INSERT_SUBREG:
372  /// dX = INSERT_SUBREG dY, rZ, translateImmToSubIdx(Imm)
373  ///
374  /// Note that for the optimizers to be able to take advantage of
375  /// this property, TargetInstrInfo::getInsertSubregLikeInputs has to be
376  /// override accordingly.
377  bool isInsertSubregLike() const { return Flags & (1ULL << MCID::InsertSubreg); }
378 
379 
380  /// Return true if this instruction is convergent.
381  ///
382  /// Convergent instructions may not be made control-dependent on any
383  /// additional values.
384  bool isConvergent() const { return Flags & (1ULL << MCID::Convergent); }
385 
386  //===--------------------------------------------------------------------===//
387  // Side Effect Analysis
388  //===--------------------------------------------------------------------===//
389 
390  /// Return true if this instruction could possibly read memory.
391  /// Instructions with this flag set are not necessarily simple load
392  /// instructions, they may load a value and modify it, for example.
393  bool mayLoad() const { return Flags & (1ULL << MCID::MayLoad); }
394 
395  /// Return true if this instruction could possibly modify memory.
396  /// Instructions with this flag set are not necessarily simple store
397  /// instructions, they may store a modified value based on their operands, or
398  /// may not actually modify anything, for example.
399  bool mayStore() const { return Flags & (1ULL << MCID::MayStore); }
400 
401  /// Return true if this instruction has side
402  /// effects that are not modeled by other flags. This does not return true
403  /// for instructions whose effects are captured by:
404  ///
405  /// 1. Their operand list and implicit definition/use list. Register use/def
406  /// info is explicit for instructions.
407  /// 2. Memory accesses. Use mayLoad/mayStore.
408  /// 3. Calling, branching, returning: use isCall/isReturn/isBranch.
409  ///
410  /// Examples of side effects would be modifying 'invisible' machine state like
411  /// a control register, flushing a cache, modifying a register invisible to
412  /// LLVM, etc.
413  bool hasUnmodeledSideEffects() const {
414  return Flags & (1ULL << MCID::UnmodeledSideEffects);
415  }
416 
417  //===--------------------------------------------------------------------===//
418  // Flags that indicate whether an instruction can be modified by a method.
419  //===--------------------------------------------------------------------===//
420 
421  /// Return true if this may be a 2- or 3-address instruction (of the
422  /// form "X = op Y, Z, ..."), which produces the same result if Y and Z are
423  /// exchanged. If this flag is set, then the
424  /// TargetInstrInfo::commuteInstruction method may be used to hack on the
425  /// instruction.
426  ///
427  /// Note that this flag may be set on instructions that are only commutable
428  /// sometimes. In these cases, the call to commuteInstruction will fail.
429  /// Also note that some instructions require non-trivial modification to
430  /// commute them.
431  bool isCommutable() const { return Flags & (1ULL << MCID::Commutable); }
432 
433  /// Return true if this is a 2-address instruction which can be changed
434  /// into a 3-address instruction if needed. Doing this transformation can be
435  /// profitable in the register allocator, because it means that the
436  /// instruction can use a 2-address form if possible, but degrade into a less
437  /// efficient form if the source and dest register cannot be assigned to the
438  /// same register. For example, this allows the x86 backend to turn a "shl
439  /// reg, 3" instruction into an LEA instruction, which is the same speed as
440  /// the shift but has bigger code size.
441  ///
442  /// If this returns true, then the target must implement the
443  /// TargetInstrInfo::convertToThreeAddress method for this instruction, which
444  /// is allowed to fail if the transformation isn't valid for this specific
445  /// instruction (e.g. shl reg, 4 on x86).
446  ///
447  bool isConvertibleTo3Addr() const {
448  return Flags & (1ULL << MCID::ConvertibleTo3Addr);
449  }
450 
451  /// Return true if this instruction requires custom insertion support
452  /// when the DAG scheduler is inserting it into a machine basic block. If
453  /// this is true for the instruction, it basically means that it is a pseudo
454  /// instruction used at SelectionDAG time that is expanded out into magic code
455  /// by the target when MachineInstrs are formed.
456  ///
457  /// If this is true, the TargetLoweringInfo::InsertAtEndOfBasicBlock method
458  /// is used to insert this into the MachineBasicBlock.
459  bool usesCustomInsertionHook() const {
460  return Flags & (1ULL << MCID::UsesCustomInserter);
461  }
462 
463  /// Return true if this instruction requires *adjustment* after
464  /// instruction selection by calling a target hook. For example, this can be
465  /// used to fill in ARM 's' optional operand depending on whether the
466  /// conditional flag register is used.
467  bool hasPostISelHook() const { return Flags & (1ULL << MCID::HasPostISelHook); }
468 
469  /// Returns true if this instruction is a candidate for remat. This
470  /// flag is only used in TargetInstrInfo method isTriviallyRematerializable.
471  ///
472  /// If this flag is set, the isReallyTriviallyReMaterializable()
473  /// or isReallyTriviallyReMaterializableGeneric methods are called to verify
474  /// the instruction is really rematable.
475  bool isRematerializable() const {
476  return Flags & (1ULL << MCID::Rematerializable);
477  }
478 
479  /// Returns true if this instruction has the same cost (or less) than a
480  /// move instruction. This is useful during certain types of optimizations
481  /// (e.g., remat during two-address conversion or machine licm) where we would
482  /// like to remat or hoist the instruction, but not if it costs more than
483  /// moving the instruction into the appropriate register. Note, we are not
484  /// marking copies from and to the same register class with this flag.
485  ///
486  /// This method could be called by interface TargetInstrInfo::isAsCheapAsAMove
487  /// for different subtargets.
488  bool isAsCheapAsAMove() const { return Flags & (1ULL << MCID::CheapAsAMove); }
489 
490  /// Returns true if this instruction source operands have special
491  /// register allocation requirements that are not captured by the operand
492  /// register classes. e.g. ARM::STRD's two source registers must be an even /
493  /// odd pair, ARM::STM registers have to be in ascending order. Post-register
494  /// allocation passes should not attempt to change allocations for sources of
495  /// instructions with this flag.
496  bool hasExtraSrcRegAllocReq() const {
497  return Flags & (1ULL << MCID::ExtraSrcRegAllocReq);
498  }
499 
500  /// Returns true if this instruction def operands have special register
501  /// allocation requirements that are not captured by the operand register
502  /// classes. e.g. ARM::LDRD's two def registers must be an even / odd pair,
503  /// ARM::LDM registers have to be in ascending order. Post-register
504  /// allocation passes should not attempt to change allocations for definitions
505  /// of instructions with this flag.
506  bool hasExtraDefRegAllocReq() const {
507  return Flags & (1ULL << MCID::ExtraDefRegAllocReq);
508  }
509 
510  /// Return a list of registers that are potentially read by any
511  /// instance of this machine instruction. For example, on X86, the "adc"
512  /// instruction adds two register operands and adds the carry bit in from the
513  /// flags register. In this case, the instruction is marked as implicitly
514  /// reading the flags. Likewise, the variable shift instruction on X86 is
515  /// marked as implicitly reading the 'CL' register, which it always does.
516  ///
517  /// This method returns null if the instruction has no implicit uses.
518  const MCPhysReg *getImplicitUses() const { return ImplicitUses; }
519 
520  /// Return the number of implicit uses this instruction has.
521  unsigned getNumImplicitUses() const {
522  if (!ImplicitUses)
523  return 0;
524  unsigned i = 0;
525  for (; ImplicitUses[i]; ++i) /*empty*/
526  ;
527  return i;
528  }
529 
530  /// Return a list of registers that are potentially written by any
531  /// instance of this machine instruction. For example, on X86, many
532  /// instructions implicitly set the flags register. In this case, they are
533  /// marked as setting the FLAGS. Likewise, many instructions always deposit
534  /// their result in a physical register. For example, the X86 divide
535  /// instruction always deposits the quotient and remainder in the EAX/EDX
536  /// registers. For that instruction, this will return a list containing the
537  /// EAX/EDX/EFLAGS registers.
538  ///
539  /// This method returns null if the instruction has no implicit defs.
540  const MCPhysReg *getImplicitDefs() const { return ImplicitDefs; }
541 
542  /// Return the number of implicit defs this instruct has.
543  unsigned getNumImplicitDefs() const {
544  if (!ImplicitDefs)
545  return 0;
546  unsigned i = 0;
547  for (; ImplicitDefs[i]; ++i) /*empty*/
548  ;
549  return i;
550  }
551 
552  /// Return true if this instruction implicitly
553  /// uses the specified physical register.
554  bool hasImplicitUseOfPhysReg(unsigned Reg) const {
555  if (const MCPhysReg *ImpUses = ImplicitUses)
556  for (; *ImpUses; ++ImpUses)
557  if (*ImpUses == Reg)
558  return true;
559  return false;
560  }
561 
562  /// Return true if this instruction implicitly
563  /// defines the specified physical register.
564  bool hasImplicitDefOfPhysReg(unsigned Reg,
565  const MCRegisterInfo *MRI = nullptr) const;
566 
567  /// Return the scheduling class for this instruction. The
568  /// scheduling class is an index into the InstrItineraryData table. This
569  /// returns zero if there is no known scheduling information for the
570  /// instruction.
571  unsigned getSchedClass() const { return SchedClass; }
572 
573  /// Return the number of bytes in the encoding of this instruction,
574  /// or zero if the encoding size cannot be known from the opcode.
575  unsigned getSize() const { return Size; }
576 
577  /// Find the index of the first operand in the
578  /// operand list that is used to represent the predicate. It returns -1 if
579  /// none is found.
581  if (isPredicable()) {
582  for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
583  if (OpInfo[i].isPredicate())
584  return i;
585  }
586  return -1;
587  }
588 
589  /// Return true if this instruction defines the specified physical
590  /// register, either explicitly or implicitly.
591  bool hasDefOfPhysReg(const MCInst &MI, unsigned Reg,
592  const MCRegisterInfo &RI) const;
593 };
594 
595 } // end namespace llvm
596 
597 #endif
unsigned getNumImplicitUses() const
Return the number of implicit uses this instruction has.
Definition: MCInstrDesc.h:521
bool isMoveReg() const
Return true if the instruction is a register to register move.
Definition: MCInstrDesc.h:254
unsigned getNumImplicitDefs() const
Return the number of implicit defs this instruct has.
Definition: MCInstrDesc.h:543
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
bool isLookupPtrRegClass() const
Set if this operand is a pointer value and it requires a callback to look up its register class...
Definition: MCInstrDesc.h:87
bool isCommutable() const
Return true if this may be a 2- or 3-address instruction (of the form "X = op Y, Z, ..."), which produces the same result if Y and Z are exchanged.
Definition: MCInstrDesc.h:431
uint8_t Flags
These are flags from the MCOI::OperandFlags enum.
Definition: MCInstrDesc.h:76
unsigned char Size
Definition: MCInstrDesc.h:168
const MCPhysReg * getImplicitUses() const
Return a list of registers that are potentially read by any instance of this machine instruction...
Definition: MCInstrDesc.h:518
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:163
unsigned Reg
int findFirstPredOperandIdx() const
Find the index of the first operand in the operand list that is used to represent the predicate...
Definition: MCInstrDesc.h:580
bool hasUnmodeledSideEffects() const
Return true if this instruction has side effects that are not modeled by other flags.
Definition: MCInstrDesc.h:413
bool isRegSequenceLike() const
Return true if this instruction behaves the same way as the generic REG_SEQUENCE instructions.
Definition: MCInstrDesc.h:350
const_opInfo_iterator opInfo_begin() const
Definition: MCInstrDesc.h:214
bool isPseudo() const
Return true if this is a pseudo instruction that doesn&#39;t correspond to a real machine instruction...
Definition: MCInstrDesc.h:242
bool mayLoad() const
Return true if this instruction could possibly read memory.
Definition: MCInstrDesc.h:393
bool isReturn() const
Return true if the instruction is a return.
Definition: MCInstrDesc.h:245
bool isBranch() const
Returns true if this is a conditional, unconditional, or indirect branch.
Definition: MCInstrDesc.h:276
bool isCompare() const
Return true if this instruction is a comparison.
Definition: MCInstrDesc.h:310
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
Definition: MCInstrDesc.h:210
bool isTrap() const
Return true if this instruction is a trap.
Definition: MCInstrDesc.h:251
bool isExtractSubregLike() const
Return true if this instruction behaves the same way as the generic EXTRACT_SUBREG instructions...
Definition: MCInstrDesc.h:363
bool isSelect() const
Return true if this is a select instruction.
Definition: MCInstrDesc.h:320
uint8_t OperandType
Information about the type of the operand.
Definition: MCInstrDesc.h:79
bool isConvertibleTo3Addr() const
Return true if this is a 2-address instruction which can be changed into a 3-address instruction if n...
Definition: MCInstrDesc.h:447
bool isRematerializable() const
Returns true if this instruction is a candidate for remat.
Definition: MCInstrDesc.h:475
uint32_t Constraints
The lower 16 bits are used to specify which constraints are set.
Definition: MCInstrDesc.h:83
bool isAsCheapAsAMove() const
Returns true if this instruction has the same cost (or less) than a move instruction.
Definition: MCInstrDesc.h:488
bool isPredicate() const
Set if this is one of the operands that made up of the predicate operand that controls an isPredicabl...
Definition: MCInstrDesc.h:93
bool hasExtraDefRegAllocReq() const
Returns true if this instruction def operands have special register allocation requirements that are ...
Definition: MCInstrDesc.h:506
bool isMoveImmediate() const
Return true if this instruction is a move immediate (including conditional moves) instruction...
Definition: MCInstrDesc.h:314
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:161
unsigned short NumOperands
Definition: MCInstrDesc.h:166
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
Flag
These should be considered private to the implementation of the MCInstrDesc class.
Definition: MCInstrDesc.h:118
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
unsigned getSchedClass() const
Return the scheduling class for this instruction.
Definition: MCInstrDesc.h:571
bool isGenericType() const
Definition: MCInstrDesc.h:98
const MCPhysReg * getImplicitDefs() const
Return a list of registers that are potentially written by any instance of this machine instruction...
Definition: MCInstrDesc.h:540
bool hasExtraSrcRegAllocReq() const
Returns true if this instruction source operands have special register allocation requirements that a...
Definition: MCInstrDesc.h:496
unsigned const MachineRegisterInfo * MRI
bool isOptionalDef() const
Set if this operand is a optional def.
Definition: MCInstrDesc.h:96
bool hasOptionalDef() const
Set if this instruction has an optional definition, e.g.
Definition: MCInstrDesc.h:238
bool isBarrier() const
Returns true if the specified instruction stops control flow from executing the instruction immediate...
Definition: MCInstrDesc.h:262
bool isVariadic() const
Return true if this instruction can have a variable number of operands.
Definition: MCInstrDesc.h:234
bool isConditionalBranch() const
Return true if this is a branch which may fall through to the next instruction or may transfer contro...
Definition: MCInstrDesc.h:286
int64_t DeprecatedFeature
Definition: MCInstrDesc.h:178
OperandFlags
These are flags set on operands, but should be considered private, all access should go through the M...
Definition: MCInstrDesc.h:41
const MCPhysReg * ImplicitDefs
Definition: MCInstrDesc.h:173
bool isPredicable() const
Return true if this instruction has a predicate operand that controls execution.
Definition: MCInstrDesc.h:307
bool isIndirectBranch() const
Return true if this is an indirect branch, such as a branch through a register.
Definition: MCInstrDesc.h:280
bool hasPostISelHook() const
Return true if this instruction requires adjustment after instruction selection by calling a target h...
Definition: MCInstrDesc.h:467
unsigned char NumDefs
Definition: MCInstrDesc.h:167
bool isAdd() const
Return true if the instruction is an add instruction.
Definition: MCInstrDesc.h:248
bool isNotDuplicable() const
Return true if this instruction cannot be safely duplicated.
Definition: MCInstrDesc.h:325
int getOperandConstraint(unsigned OpNum, MCOI::OperandConstraint Constraint) const
Returns the value of the specific constraint if it is set.
Definition: MCInstrDesc.h:187
iterator_range< T > make_range(T x, T y)
Convenience function for iterating over sub-ranges.
bool isInsertSubregLike() const
Return true if this instruction behaves the same way as the generic INSERT_SUBREG instructions...
Definition: MCInstrDesc.h:377
bool hasDelaySlot() const
Returns true if the specified instruction has a delay slot which must be filled by the code generator...
Definition: MCInstrDesc.h:329
bool isBitcast() const
Return true if this instruction is a bitcast instruction.
Definition: MCInstrDesc.h:317
unsigned getNumDefs() const
Return the number of MachineOperands that are register definitions.
Definition: MCInstrDesc.h:225
unsigned short Opcode
Definition: MCInstrDesc.h:165
A range adaptor for a pair of iterators.
bool isConvergent() const
Return true if this instruction is convergent.
Definition: MCInstrDesc.h:384
bool mayStore() const
Return true if this instruction could possibly modify memory.
Definition: MCInstrDesc.h:399
bool isUnconditionalBranch() const
Return true if this is a branch which always transfers control flow to some other block...
Definition: MCInstrDesc.h:294
OperandType
Operands are tagged with one of the values of this enum.
Definition: MCInstrDesc.h:44
bool canFoldAsLoad() const
Return true for instructions that can be folded as memory operands in other instructions.
Definition: MCInstrDesc.h:338
int16_t RegClass
This specifies the register class enumeration of the operand if the operand is a register.
Definition: MCInstrDesc.h:73
const_opInfo_iterator opInfo_end() const
Definition: MCInstrDesc.h:215
bool isCall() const
Return true if the instruction is a call.
Definition: MCInstrDesc.h:257
Generic base class for all target subtargets.
uint32_t Size
Definition: Profile.cpp:47
iterator_range< const_opInfo_iterator > operands() const
Definition: MCInstrDesc.h:217
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static bool isBranch(unsigned Opcode)
bool hasImplicitUseOfPhysReg(unsigned Reg) const
Return true if this instruction implicitly uses the specified physical register.
Definition: MCInstrDesc.h:554
bool isTerminator() const
Returns true if this instruction part of the terminator for a basic block.
Definition: MCInstrDesc.h:270
const MCOperandInfo * OpInfo
Definition: MCInstrDesc.h:174
unsigned getOpcode() const
Return the opcode number for this descriptor.
Definition: MCInstrDesc.h:203
unsigned getGenericTypeIndex() const
Definition: MCInstrDesc.h:103
IRTranslator LLVM IR MI
bool usesCustomInsertionHook() const
Return true if this instruction requires custom insertion support when the DAG scheduler is inserting...
Definition: MCInstrDesc.h:459
This holds information about one operand of a machine instruction, indicating the register class for ...
Definition: MCInstrDesc.h:67
uint64_t getFlags() const
Return flags of this instruction.
Definition: MCInstrDesc.h:228
unsigned short SchedClass
Definition: MCInstrDesc.h:169
const MCPhysReg * ImplicitUses
Definition: MCInstrDesc.h:172
unsigned getSize() const
Return the number of bytes in the encoding of this instruction, or zero if the encoding size cannot b...
Definition: MCInstrDesc.h:575