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MCInstrDesc.h
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1 //===-- llvm/MC/MCInstrDesc.h - Instruction Descriptors -*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file defines the MCOperandInfo and MCInstrDesc classes, which
10 // are used to describe target instructions and their operands.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_MC_MCINSTRDESC_H
15 #define LLVM_MC_MCINSTRDESC_H
16 
17 #include "llvm/MC/MCRegisterInfo.h"
18 #include "llvm/Support/DataTypes.h"
19 #include <string>
20 
21 namespace llvm {
22  class MCInst;
23  class MCSubtargetInfo;
24  class FeatureBitset;
25 
26 //===----------------------------------------------------------------------===//
27 // Machine Operand Flags and Description
28 //===----------------------------------------------------------------------===//
29 
30 namespace MCOI {
31 // Operand constraints
33  TIED_TO = 0, // Must be allocated the same register as.
34  EARLY_CLOBBER // Operand is an early clobber register operand
35 };
36 
37 /// These are flags set on operands, but should be considered
38 /// private, all access should go through the MCOperandInfo accessors.
39 /// See the accessors for a description of what these are.
41 
42 /// Operands are tagged with one of the values of this enum.
49 
58 
62 
64 };
65 
66 }
67 
68 /// This holds information about one operand of a machine instruction,
69 /// indicating the register class for register operands, etc.
71 public:
72  /// This specifies the register class enumeration of the operand
73  /// if the operand is a register. If isLookupPtrRegClass is set, then this is
74  /// an index that is passed to TargetRegisterInfo::getPointerRegClass(x) to
75  /// get a dynamic register class.
76  int16_t RegClass;
77 
78  /// These are flags from the MCOI::OperandFlags enum.
79  uint8_t Flags;
80 
81  /// Information about the type of the operand.
82  uint8_t OperandType;
83  /// The lower 16 bits are used to specify which constraints are set.
84  /// The higher 16 bits are used to specify the value of constraints (4 bits
85  /// each).
87 
88  /// Set if this operand is a pointer value and it requires a callback
89  /// to look up its register class.
90  bool isLookupPtrRegClass() const {
91  return Flags & (1 << MCOI::LookupPtrRegClass);
92  }
93 
94  /// Set if this is one of the operands that made up of the predicate
95  /// operand that controls an isPredicable() instruction.
96  bool isPredicate() const { return Flags & (1 << MCOI::Predicate); }
97 
98  /// Set if this operand is a optional def.
99  bool isOptionalDef() const { return Flags & (1 << MCOI::OptionalDef); }
100 
101  bool isGenericType() const {
102  return OperandType >= MCOI::OPERAND_FIRST_GENERIC &&
103  OperandType <= MCOI::OPERAND_LAST_GENERIC;
104  }
105 
106  unsigned getGenericTypeIndex() const {
107  assert(isGenericType() && "non-generic types don't have an index");
108  return OperandType - MCOI::OPERAND_FIRST_GENERIC;
109  }
110 
111  bool isGenericImm() const {
112  return OperandType >= MCOI::OPERAND_FIRST_GENERIC_IMM &&
113  OperandType <= MCOI::OPERAND_LAST_GENERIC_IMM;
114  }
115 
116  unsigned getGenericImmIndex() const {
117  assert(isGenericImm() && "non-generic immediates don't have an index");
118  return OperandType - MCOI::OPERAND_FIRST_GENERIC_IMM;
119  }
120 };
121 
122 //===----------------------------------------------------------------------===//
123 // Machine Instruction Flags and Description
124 //===----------------------------------------------------------------------===//
125 
126 namespace MCID {
127 /// These should be considered private to the implementation of the
128 /// MCInstrDesc class. Clients should use the predicate methods on MCInstrDesc,
129 /// not use these directly. These all correspond to bitfields in the
130 /// MCInstrDesc::Flags field.
131 enum Flag {
171 };
172 }
173 
174 /// Describe properties that are true of each instruction in the target
175 /// description file. This captures information about side effects, register
176 /// use and many other things. There is one instance of this struct for each
177 /// target instruction class, and the MachineInstr class points to this struct
178 /// directly to describe itself.
179 class MCInstrDesc {
180 public:
181  unsigned short Opcode; // The opcode number
182  unsigned short NumOperands; // Num of args (may be more if variable_ops)
183  unsigned char NumDefs; // Num of args that are definitions
184  unsigned char Size; // Number of bytes in encoding.
185  unsigned short SchedClass; // enum identifying instr sched class
186  uint64_t Flags; // Flags identifying machine instr class
187  uint64_t TSFlags; // Target Specific Flag values
188  const MCPhysReg *ImplicitUses; // Registers implicitly read by this instr
189  const MCPhysReg *ImplicitDefs; // Registers implicitly defined by this instr
190  const MCOperandInfo *OpInfo; // 'NumOperands' entries about operands
191  // Subtarget feature that this is deprecated on, if any
192  // -1 implies this is not deprecated by any single feature. It may still be
193  // deprecated due to a "complex" reason, below.
195 
196  // A complex method to determine if a certain instruction is deprecated or
197  // not, and return the reason for deprecation.
198  bool (*ComplexDeprecationInfo)(MCInst &, const MCSubtargetInfo &,
199  std::string &);
200 
201  /// Returns the value of the specific constraint if
202  /// it is set. Returns -1 if it is not set.
203  int getOperandConstraint(unsigned OpNum,
204  MCOI::OperandConstraint Constraint) const {
205  if (OpNum < NumOperands &&
206  (OpInfo[OpNum].Constraints & (1 << Constraint))) {
207  unsigned Pos = 16 + Constraint * 4;
208  return (int)(OpInfo[OpNum].Constraints >> Pos) & 0xf;
209  }
210  return -1;
211  }
212 
213  /// Returns true if a certain instruction is deprecated and if so
214  /// returns the reason in \p Info.
215  bool getDeprecatedInfo(MCInst &MI, const MCSubtargetInfo &STI,
216  std::string &Info) const;
217 
218  /// Return the opcode number for this descriptor.
219  unsigned getOpcode() const { return Opcode; }
220 
221  /// Return the number of declared MachineOperands for this
222  /// MachineInstruction. Note that variadic (isVariadic() returns true)
223  /// instructions may have additional operands at the end of the list, and note
224  /// that the machine instruction may include implicit register def/uses as
225  /// well.
226  unsigned getNumOperands() const { return NumOperands; }
227 
229 
230  const_opInfo_iterator opInfo_begin() const { return OpInfo; }
231  const_opInfo_iterator opInfo_end() const { return OpInfo + NumOperands; }
232 
234  return make_range(opInfo_begin(), opInfo_end());
235  }
236 
237  /// Return the number of MachineOperands that are register
238  /// definitions. Register definitions always occur at the start of the
239  /// machine operand list. This is the number of "outs" in the .td file,
240  /// and does not include implicit defs.
241  unsigned getNumDefs() const { return NumDefs; }
242 
243  /// Return flags of this instruction.
244  uint64_t getFlags() const { return Flags; }
245 
246  /// \returns true if this instruction is emitted before instruction selection
247  /// and should be legalized/regbankselected/selected.
248  bool isPreISelOpcode() const { return Flags & (1ULL << MCID::PreISelOpcode); }
249 
250  /// Return true if this instruction can have a variable number of
251  /// operands. In this case, the variable operands will be after the normal
252  /// operands but before the implicit definitions and uses (if any are
253  /// present).
254  bool isVariadic() const { return Flags & (1ULL << MCID::Variadic); }
255 
256  /// Set if this instruction has an optional definition, e.g.
257  /// ARM instructions which can set condition code if 's' bit is set.
258  bool hasOptionalDef() const { return Flags & (1ULL << MCID::HasOptionalDef); }
259 
260  /// Return true if this is a pseudo instruction that doesn't
261  /// correspond to a real machine instruction.
262  bool isPseudo() const { return Flags & (1ULL << MCID::Pseudo); }
263 
264  /// Return true if the instruction is a return.
265  bool isReturn() const { return Flags & (1ULL << MCID::Return); }
266 
267  /// Return true if the instruction is an add instruction.
268  bool isAdd() const { return Flags & (1ULL << MCID::Add); }
269 
270  /// Return true if this instruction is a trap.
271  bool isTrap() const { return Flags & (1ULL << MCID::Trap); }
272 
273  /// Return true if the instruction is a register to register move.
274  bool isMoveReg() const { return Flags & (1ULL << MCID::MoveReg); }
275 
276  /// Return true if the instruction is a call.
277  bool isCall() const { return Flags & (1ULL << MCID::Call); }
278 
279  /// Returns true if the specified instruction stops control flow
280  /// from executing the instruction immediately following it. Examples include
281  /// unconditional branches and return instructions.
282  bool isBarrier() const { return Flags & (1ULL << MCID::Barrier); }
283 
284  /// Returns true if this instruction part of the terminator for
285  /// a basic block. Typically this is things like return and branch
286  /// instructions.
287  ///
288  /// Various passes use this to insert code into the bottom of a basic block,
289  /// but before control flow occurs.
290  bool isTerminator() const { return Flags & (1ULL << MCID::Terminator); }
291 
292  /// Returns true if this is a conditional, unconditional, or
293  /// indirect branch. Predicates below can be used to discriminate between
294  /// these cases, and the TargetInstrInfo::AnalyzeBranch method can be used to
295  /// get more information.
296  bool isBranch() const { return Flags & (1ULL << MCID::Branch); }
297 
298  /// Return true if this is an indirect branch, such as a
299  /// branch through a register.
300  bool isIndirectBranch() const { return Flags & (1ULL << MCID::IndirectBranch); }
301 
302  /// Return true if this is a branch which may fall
303  /// through to the next instruction or may transfer control flow to some other
304  /// block. The TargetInstrInfo::AnalyzeBranch method can be used to get more
305  /// information about this branch.
306  bool isConditionalBranch() const {
307  return isBranch() & !isBarrier() & !isIndirectBranch();
308  }
309 
310  /// Return true if this is a branch which always
311  /// transfers control flow to some other block. The
312  /// TargetInstrInfo::AnalyzeBranch method can be used to get more information
313  /// about this branch.
314  bool isUnconditionalBranch() const {
315  return isBranch() & isBarrier() & !isIndirectBranch();
316  }
317 
318  /// Return true if this is a branch or an instruction which directly
319  /// writes to the program counter. Considered 'may' affect rather than
320  /// 'does' affect as things like predication are not taken into account.
321  bool mayAffectControlFlow(const MCInst &MI, const MCRegisterInfo &RI) const;
322 
323  /// Return true if this instruction has a predicate operand
324  /// that controls execution. It may be set to 'always', or may be set to other
325  /// values. There are various methods in TargetInstrInfo that can be used to
326  /// control and modify the predicate in this instruction.
327  bool isPredicable() const { return Flags & (1ULL << MCID::Predicable); }
328 
329  /// Return true if this instruction is a comparison.
330  bool isCompare() const { return Flags & (1ULL << MCID::Compare); }
331 
332  /// Return true if this instruction is a move immediate
333  /// (including conditional moves) instruction.
334  bool isMoveImmediate() const { return Flags & (1ULL << MCID::MoveImm); }
335 
336  /// Return true if this instruction is a bitcast instruction.
337  bool isBitcast() const { return Flags & (1ULL << MCID::Bitcast); }
338 
339  /// Return true if this is a select instruction.
340  bool isSelect() const { return Flags & (1ULL << MCID::Select); }
341 
342  /// Return true if this instruction cannot be safely
343  /// duplicated. For example, if the instruction has a unique labels attached
344  /// to it, duplicating it would cause multiple definition errors.
345  bool isNotDuplicable() const { return Flags & (1ULL << MCID::NotDuplicable); }
346 
347  /// Returns true if the specified instruction has a delay slot which
348  /// must be filled by the code generator.
349  bool hasDelaySlot() const { return Flags & (1ULL << MCID::DelaySlot); }
350 
351  /// Return true for instructions that can be folded as memory operands
352  /// in other instructions. The most common use for this is instructions that
353  /// are simple loads from memory that don't modify the loaded value in any
354  /// way, but it can also be used for instructions that can be expressed as
355  /// constant-pool loads, such as V_SETALLONES on x86, to allow them to be
356  /// folded when it is beneficial. This should only be set on instructions
357  /// that return a value in their only virtual register definition.
358  bool canFoldAsLoad() const { return Flags & (1ULL << MCID::FoldableAsLoad); }
359 
360  /// Return true if this instruction behaves
361  /// the same way as the generic REG_SEQUENCE instructions.
362  /// E.g., on ARM,
363  /// dX VMOVDRR rY, rZ
364  /// is equivalent to
365  /// dX = REG_SEQUENCE rY, ssub_0, rZ, ssub_1.
366  ///
367  /// Note that for the optimizers to be able to take advantage of
368  /// this property, TargetInstrInfo::getRegSequenceLikeInputs has to be
369  /// override accordingly.
370  bool isRegSequenceLike() const { return Flags & (1ULL << MCID::RegSequence); }
371 
372  /// Return true if this instruction behaves
373  /// the same way as the generic EXTRACT_SUBREG instructions.
374  /// E.g., on ARM,
375  /// rX, rY VMOVRRD dZ
376  /// is equivalent to two EXTRACT_SUBREG:
377  /// rX = EXTRACT_SUBREG dZ, ssub_0
378  /// rY = EXTRACT_SUBREG dZ, ssub_1
379  ///
380  /// Note that for the optimizers to be able to take advantage of
381  /// this property, TargetInstrInfo::getExtractSubregLikeInputs has to be
382  /// override accordingly.
383  bool isExtractSubregLike() const {
384  return Flags & (1ULL << MCID::ExtractSubreg);
385  }
386 
387  /// Return true if this instruction behaves
388  /// the same way as the generic INSERT_SUBREG instructions.
389  /// E.g., on ARM,
390  /// dX = VSETLNi32 dY, rZ, Imm
391  /// is equivalent to a INSERT_SUBREG:
392  /// dX = INSERT_SUBREG dY, rZ, translateImmToSubIdx(Imm)
393  ///
394  /// Note that for the optimizers to be able to take advantage of
395  /// this property, TargetInstrInfo::getInsertSubregLikeInputs has to be
396  /// override accordingly.
397  bool isInsertSubregLike() const { return Flags & (1ULL << MCID::InsertSubreg); }
398 
399 
400  /// Return true if this instruction is convergent.
401  ///
402  /// Convergent instructions may not be made control-dependent on any
403  /// additional values.
404  bool isConvergent() const { return Flags & (1ULL << MCID::Convergent); }
405 
406  /// Return true if variadic operands of this instruction are definitions.
407  bool variadicOpsAreDefs() const {
408  return Flags & (1ULL << MCID::VariadicOpsAreDefs);
409  }
410 
411  //===--------------------------------------------------------------------===//
412  // Side Effect Analysis
413  //===--------------------------------------------------------------------===//
414 
415  /// Return true if this instruction could possibly read memory.
416  /// Instructions with this flag set are not necessarily simple load
417  /// instructions, they may load a value and modify it, for example.
418  bool mayLoad() const { return Flags & (1ULL << MCID::MayLoad); }
419 
420  /// Return true if this instruction could possibly modify memory.
421  /// Instructions with this flag set are not necessarily simple store
422  /// instructions, they may store a modified value based on their operands, or
423  /// may not actually modify anything, for example.
424  bool mayStore() const { return Flags & (1ULL << MCID::MayStore); }
425 
426  /// Return true if this instruction may raise a floating-point exception.
427  bool mayRaiseFPException() const {
428  return Flags & (1ULL << MCID::MayRaiseFPException);
429  }
430 
431  /// Return true if this instruction has side
432  /// effects that are not modeled by other flags. This does not return true
433  /// for instructions whose effects are captured by:
434  ///
435  /// 1. Their operand list and implicit definition/use list. Register use/def
436  /// info is explicit for instructions.
437  /// 2. Memory accesses. Use mayLoad/mayStore.
438  /// 3. Calling, branching, returning: use isCall/isReturn/isBranch.
439  ///
440  /// Examples of side effects would be modifying 'invisible' machine state like
441  /// a control register, flushing a cache, modifying a register invisible to
442  /// LLVM, etc.
443  bool hasUnmodeledSideEffects() const {
444  return Flags & (1ULL << MCID::UnmodeledSideEffects);
445  }
446 
447  //===--------------------------------------------------------------------===//
448  // Flags that indicate whether an instruction can be modified by a method.
449  //===--------------------------------------------------------------------===//
450 
451  /// Return true if this may be a 2- or 3-address instruction (of the
452  /// form "X = op Y, Z, ..."), which produces the same result if Y and Z are
453  /// exchanged. If this flag is set, then the
454  /// TargetInstrInfo::commuteInstruction method may be used to hack on the
455  /// instruction.
456  ///
457  /// Note that this flag may be set on instructions that are only commutable
458  /// sometimes. In these cases, the call to commuteInstruction will fail.
459  /// Also note that some instructions require non-trivial modification to
460  /// commute them.
461  bool isCommutable() const { return Flags & (1ULL << MCID::Commutable); }
462 
463  /// Return true if this is a 2-address instruction which can be changed
464  /// into a 3-address instruction if needed. Doing this transformation can be
465  /// profitable in the register allocator, because it means that the
466  /// instruction can use a 2-address form if possible, but degrade into a less
467  /// efficient form if the source and dest register cannot be assigned to the
468  /// same register. For example, this allows the x86 backend to turn a "shl
469  /// reg, 3" instruction into an LEA instruction, which is the same speed as
470  /// the shift but has bigger code size.
471  ///
472  /// If this returns true, then the target must implement the
473  /// TargetInstrInfo::convertToThreeAddress method for this instruction, which
474  /// is allowed to fail if the transformation isn't valid for this specific
475  /// instruction (e.g. shl reg, 4 on x86).
476  ///
477  bool isConvertibleTo3Addr() const {
478  return Flags & (1ULL << MCID::ConvertibleTo3Addr);
479  }
480 
481  /// Return true if this instruction requires custom insertion support
482  /// when the DAG scheduler is inserting it into a machine basic block. If
483  /// this is true for the instruction, it basically means that it is a pseudo
484  /// instruction used at SelectionDAG time that is expanded out into magic code
485  /// by the target when MachineInstrs are formed.
486  ///
487  /// If this is true, the TargetLoweringInfo::InsertAtEndOfBasicBlock method
488  /// is used to insert this into the MachineBasicBlock.
489  bool usesCustomInsertionHook() const {
490  return Flags & (1ULL << MCID::UsesCustomInserter);
491  }
492 
493  /// Return true if this instruction requires *adjustment* after
494  /// instruction selection by calling a target hook. For example, this can be
495  /// used to fill in ARM 's' optional operand depending on whether the
496  /// conditional flag register is used.
497  bool hasPostISelHook() const { return Flags & (1ULL << MCID::HasPostISelHook); }
498 
499  /// Returns true if this instruction is a candidate for remat. This
500  /// flag is only used in TargetInstrInfo method isTriviallyRematerializable.
501  ///
502  /// If this flag is set, the isReallyTriviallyReMaterializable()
503  /// or isReallyTriviallyReMaterializableGeneric methods are called to verify
504  /// the instruction is really rematable.
505  bool isRematerializable() const {
506  return Flags & (1ULL << MCID::Rematerializable);
507  }
508 
509  /// Returns true if this instruction has the same cost (or less) than a
510  /// move instruction. This is useful during certain types of optimizations
511  /// (e.g., remat during two-address conversion or machine licm) where we would
512  /// like to remat or hoist the instruction, but not if it costs more than
513  /// moving the instruction into the appropriate register. Note, we are not
514  /// marking copies from and to the same register class with this flag.
515  ///
516  /// This method could be called by interface TargetInstrInfo::isAsCheapAsAMove
517  /// for different subtargets.
518  bool isAsCheapAsAMove() const { return Flags & (1ULL << MCID::CheapAsAMove); }
519 
520  /// Returns true if this instruction source operands have special
521  /// register allocation requirements that are not captured by the operand
522  /// register classes. e.g. ARM::STRD's two source registers must be an even /
523  /// odd pair, ARM::STM registers have to be in ascending order. Post-register
524  /// allocation passes should not attempt to change allocations for sources of
525  /// instructions with this flag.
526  bool hasExtraSrcRegAllocReq() const {
527  return Flags & (1ULL << MCID::ExtraSrcRegAllocReq);
528  }
529 
530  /// Returns true if this instruction def operands have special register
531  /// allocation requirements that are not captured by the operand register
532  /// classes. e.g. ARM::LDRD's two def registers must be an even / odd pair,
533  /// ARM::LDM registers have to be in ascending order. Post-register
534  /// allocation passes should not attempt to change allocations for definitions
535  /// of instructions with this flag.
536  bool hasExtraDefRegAllocReq() const {
537  return Flags & (1ULL << MCID::ExtraDefRegAllocReq);
538  }
539 
540  /// Return a list of registers that are potentially read by any
541  /// instance of this machine instruction. For example, on X86, the "adc"
542  /// instruction adds two register operands and adds the carry bit in from the
543  /// flags register. In this case, the instruction is marked as implicitly
544  /// reading the flags. Likewise, the variable shift instruction on X86 is
545  /// marked as implicitly reading the 'CL' register, which it always does.
546  ///
547  /// This method returns null if the instruction has no implicit uses.
548  const MCPhysReg *getImplicitUses() const { return ImplicitUses; }
549 
550  /// Return the number of implicit uses this instruction has.
551  unsigned getNumImplicitUses() const {
552  if (!ImplicitUses)
553  return 0;
554  unsigned i = 0;
555  for (; ImplicitUses[i]; ++i) /*empty*/
556  ;
557  return i;
558  }
559 
560  /// Return a list of registers that are potentially written by any
561  /// instance of this machine instruction. For example, on X86, many
562  /// instructions implicitly set the flags register. In this case, they are
563  /// marked as setting the FLAGS. Likewise, many instructions always deposit
564  /// their result in a physical register. For example, the X86 divide
565  /// instruction always deposits the quotient and remainder in the EAX/EDX
566  /// registers. For that instruction, this will return a list containing the
567  /// EAX/EDX/EFLAGS registers.
568  ///
569  /// This method returns null if the instruction has no implicit defs.
570  const MCPhysReg *getImplicitDefs() const { return ImplicitDefs; }
571 
572  /// Return the number of implicit defs this instruct has.
573  unsigned getNumImplicitDefs() const {
574  if (!ImplicitDefs)
575  return 0;
576  unsigned i = 0;
577  for (; ImplicitDefs[i]; ++i) /*empty*/
578  ;
579  return i;
580  }
581 
582  /// Return true if this instruction implicitly
583  /// uses the specified physical register.
584  bool hasImplicitUseOfPhysReg(unsigned Reg) const {
585  if (const MCPhysReg *ImpUses = ImplicitUses)
586  for (; *ImpUses; ++ImpUses)
587  if (*ImpUses == Reg)
588  return true;
589  return false;
590  }
591 
592  /// Return true if this instruction implicitly
593  /// defines the specified physical register.
594  bool hasImplicitDefOfPhysReg(unsigned Reg,
595  const MCRegisterInfo *MRI = nullptr) const;
596 
597  /// Return the scheduling class for this instruction. The
598  /// scheduling class is an index into the InstrItineraryData table. This
599  /// returns zero if there is no known scheduling information for the
600  /// instruction.
601  unsigned getSchedClass() const { return SchedClass; }
602 
603  /// Return the number of bytes in the encoding of this instruction,
604  /// or zero if the encoding size cannot be known from the opcode.
605  unsigned getSize() const { return Size; }
606 
607  /// Find the index of the first operand in the
608  /// operand list that is used to represent the predicate. It returns -1 if
609  /// none is found.
611  if (isPredicable()) {
612  for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
613  if (OpInfo[i].isPredicate())
614  return i;
615  }
616  return -1;
617  }
618 
619  /// Return true if this instruction defines the specified physical
620  /// register, either explicitly or implicitly.
621  bool hasDefOfPhysReg(const MCInst &MI, unsigned Reg,
622  const MCRegisterInfo &RI) const;
623 };
624 
625 } // end namespace llvm
626 
627 #endif
unsigned getNumImplicitUses() const
Return the number of implicit uses this instruction has.
Definition: MCInstrDesc.h:551
bool isMoveReg() const
Return true if the instruction is a register to register move.
Definition: MCInstrDesc.h:274
unsigned getNumImplicitDefs() const
Return the number of implicit defs this instruct has.
Definition: MCInstrDesc.h:573
This class represents lattice values for constants.
Definition: AllocatorList.h:23
bool isLookupPtrRegClass() const
Set if this operand is a pointer value and it requires a callback to look up its register class...
Definition: MCInstrDesc.h:90
bool isCommutable() const
Return true if this may be a 2- or 3-address instruction (of the form "X = op Y, Z, ..."), which produces the same result if Y and Z are exchanged.
Definition: MCInstrDesc.h:461
uint8_t Flags
These are flags from the MCOI::OperandFlags enum.
Definition: MCInstrDesc.h:79
unsigned char Size
Definition: MCInstrDesc.h:184
const MCPhysReg * getImplicitUses() const
Return a list of registers that are potentially read by any instance of this machine instruction...
Definition: MCInstrDesc.h:548
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:179
unsigned Reg
int findFirstPredOperandIdx() const
Find the index of the first operand in the operand list that is used to represent the predicate...
Definition: MCInstrDesc.h:610
bool hasUnmodeledSideEffects() const
Return true if this instruction has side effects that are not modeled by other flags.
Definition: MCInstrDesc.h:443
bool isRegSequenceLike() const
Return true if this instruction behaves the same way as the generic REG_SEQUENCE instructions.
Definition: MCInstrDesc.h:370
const_opInfo_iterator opInfo_begin() const
Definition: MCInstrDesc.h:230
bool isPseudo() const
Return true if this is a pseudo instruction that doesn&#39;t correspond to a real machine instruction...
Definition: MCInstrDesc.h:262
bool mayLoad() const
Return true if this instruction could possibly read memory.
Definition: MCInstrDesc.h:418
bool isPreISelOpcode() const
Definition: MCInstrDesc.h:248
bool isReturn() const
Return true if the instruction is a return.
Definition: MCInstrDesc.h:265
bool isBranch() const
Returns true if this is a conditional, unconditional, or indirect branch.
Definition: MCInstrDesc.h:296
bool isCompare() const
Return true if this instruction is a comparison.
Definition: MCInstrDesc.h:330
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
Definition: MCInstrDesc.h:226
bool isTrap() const
Return true if this instruction is a trap.
Definition: MCInstrDesc.h:271
bool isExtractSubregLike() const
Return true if this instruction behaves the same way as the generic EXTRACT_SUBREG instructions...
Definition: MCInstrDesc.h:383
bool isSelect() const
Return true if this is a select instruction.
Definition: MCInstrDesc.h:340
uint8_t OperandType
Information about the type of the operand.
Definition: MCInstrDesc.h:82
bool isConvertibleTo3Addr() const
Return true if this is a 2-address instruction which can be changed into a 3-address instruction if n...
Definition: MCInstrDesc.h:477
bool isRematerializable() const
Returns true if this instruction is a candidate for remat.
Definition: MCInstrDesc.h:505
uint32_t Constraints
The lower 16 bits are used to specify which constraints are set.
Definition: MCInstrDesc.h:86
bool isAsCheapAsAMove() const
Returns true if this instruction has the same cost (or less) than a move instruction.
Definition: MCInstrDesc.h:518
bool isPredicate() const
Set if this is one of the operands that made up of the predicate operand that controls an isPredicabl...
Definition: MCInstrDesc.h:96
bool hasExtraDefRegAllocReq() const
Returns true if this instruction def operands have special register allocation requirements that are ...
Definition: MCInstrDesc.h:536
bool isMoveImmediate() const
Return true if this instruction is a move immediate (including conditional moves) instruction...
Definition: MCInstrDesc.h:334
Analysis containing CSE Info
Definition: CSEInfo.cpp:20
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:158
unsigned short NumOperands
Definition: MCInstrDesc.h:182
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
Definition: MCRegister.h:19
Flag
These should be considered private to the implementation of the MCInstrDesc class.
Definition: MCInstrDesc.h:131
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
unsigned getSchedClass() const
Return the scheduling class for this instruction.
Definition: MCInstrDesc.h:601
bool isGenericType() const
Definition: MCInstrDesc.h:101
const MCPhysReg * getImplicitDefs() const
Return a list of registers that are potentially written by any instance of this machine instruction...
Definition: MCInstrDesc.h:570
bool hasExtraSrcRegAllocReq() const
Returns true if this instruction source operands have special register allocation requirements that a...
Definition: MCInstrDesc.h:526
unsigned const MachineRegisterInfo * MRI
bool isOptionalDef() const
Set if this operand is a optional def.
Definition: MCInstrDesc.h:99
bool hasOptionalDef() const
Set if this instruction has an optional definition, e.g.
Definition: MCInstrDesc.h:258
bool isBarrier() const
Returns true if the specified instruction stops control flow from executing the instruction immediate...
Definition: MCInstrDesc.h:282
bool isVariadic() const
Return true if this instruction can have a variable number of operands.
Definition: MCInstrDesc.h:254
bool isConditionalBranch() const
Return true if this is a branch which may fall through to the next instruction or may transfer contro...
Definition: MCInstrDesc.h:306
int64_t DeprecatedFeature
Definition: MCInstrDesc.h:194
OperandFlags
These are flags set on operands, but should be considered private, all access should go through the M...
Definition: MCInstrDesc.h:40
const MCPhysReg * ImplicitDefs
Definition: MCInstrDesc.h:189
constexpr double e
Definition: MathExtras.h:57
bool isPredicable() const
Return true if this instruction has a predicate operand that controls execution.
Definition: MCInstrDesc.h:327
bool isIndirectBranch() const
Return true if this is an indirect branch, such as a branch through a register.
Definition: MCInstrDesc.h:300
bool hasPostISelHook() const
Return true if this instruction requires adjustment after instruction selection by calling a target h...
Definition: MCInstrDesc.h:497
unsigned char NumDefs
Definition: MCInstrDesc.h:183
bool mayRaiseFPException() const
Return true if this instruction may raise a floating-point exception.
Definition: MCInstrDesc.h:427
bool isAdd() const
Return true if the instruction is an add instruction.
Definition: MCInstrDesc.h:268
bool isNotDuplicable() const
Return true if this instruction cannot be safely duplicated.
Definition: MCInstrDesc.h:345
int getOperandConstraint(unsigned OpNum, MCOI::OperandConstraint Constraint) const
Returns the value of the specific constraint if it is set.
Definition: MCInstrDesc.h:203
iterator_range< T > make_range(T x, T y)
Convenience function for iterating over sub-ranges.
bool isInsertSubregLike() const
Return true if this instruction behaves the same way as the generic INSERT_SUBREG instructions...
Definition: MCInstrDesc.h:397
bool hasDelaySlot() const
Returns true if the specified instruction has a delay slot which must be filled by the code generator...
Definition: MCInstrDesc.h:349
bool isBitcast() const
Return true if this instruction is a bitcast instruction.
Definition: MCInstrDesc.h:337
unsigned getNumDefs() const
Return the number of MachineOperands that are register definitions.
Definition: MCInstrDesc.h:241
unsigned short Opcode
Definition: MCInstrDesc.h:181
A range adaptor for a pair of iterators.
bool isConvergent() const
Return true if this instruction is convergent.
Definition: MCInstrDesc.h:404
bool mayStore() const
Return true if this instruction could possibly modify memory.
Definition: MCInstrDesc.h:424
bool isUnconditionalBranch() const
Return true if this is a branch which always transfers control flow to some other block...
Definition: MCInstrDesc.h:314
OperandType
Operands are tagged with one of the values of this enum.
Definition: MCInstrDesc.h:43
bool canFoldAsLoad() const
Return true for instructions that can be folded as memory operands in other instructions.
Definition: MCInstrDesc.h:358
int16_t RegClass
This specifies the register class enumeration of the operand if the operand is a register.
Definition: MCInstrDesc.h:76
const_opInfo_iterator opInfo_end() const
Definition: MCInstrDesc.h:231
bool isCall() const
Return true if the instruction is a call.
Definition: MCInstrDesc.h:277
Generic base class for all target subtargets.
bool isGenericImm() const
Definition: MCInstrDesc.h:111
uint32_t Size
Definition: Profile.cpp:46
bool variadicOpsAreDefs() const
Return true if variadic operands of this instruction are definitions.
Definition: MCInstrDesc.h:407
iterator_range< const_opInfo_iterator > operands() const
Definition: MCInstrDesc.h:233
unsigned getGenericImmIndex() const
Definition: MCInstrDesc.h:116
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static bool isBranch(unsigned Opcode)
bool hasImplicitUseOfPhysReg(unsigned Reg) const
Return true if this instruction implicitly uses the specified physical register.
Definition: MCInstrDesc.h:584
bool isTerminator() const
Returns true if this instruction part of the terminator for a basic block.
Definition: MCInstrDesc.h:290
const MCOperandInfo * OpInfo
Definition: MCInstrDesc.h:190
unsigned getOpcode() const
Return the opcode number for this descriptor.
Definition: MCInstrDesc.h:219
unsigned getGenericTypeIndex() const
Definition: MCInstrDesc.h:106
IRTranslator LLVM IR MI
bool usesCustomInsertionHook() const
Return true if this instruction requires custom insertion support when the DAG scheduler is inserting...
Definition: MCInstrDesc.h:489
This holds information about one operand of a machine instruction, indicating the register class for ...
Definition: MCInstrDesc.h:70
uint64_t getFlags() const
Return flags of this instruction.
Definition: MCInstrDesc.h:244
unsigned short SchedClass
Definition: MCInstrDesc.h:185
const MCPhysReg * ImplicitUses
Definition: MCInstrDesc.h:188
unsigned getSize() const
Return the number of bytes in the encoding of this instruction, or zero if the encoding size cannot b...
Definition: MCInstrDesc.h:605