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MCInstrDesc.h
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1 //===-- llvm/MC/MCInstrDesc.h - Instruction Descriptors -*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file defines the MCOperandInfo and MCInstrDesc classes, which
10 // are used to describe target instructions and their operands.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_MC_MCINSTRDESC_H
15 #define LLVM_MC_MCINSTRDESC_H
16 
17 #include "llvm/MC/MCRegisterInfo.h"
18 #include "llvm/Support/DataTypes.h"
19 #include <string>
20 
21 namespace llvm {
22  class MCInst;
23  class MCSubtargetInfo;
24  class FeatureBitset;
25 
26 //===----------------------------------------------------------------------===//
27 // Machine Operand Flags and Description
28 //===----------------------------------------------------------------------===//
29 
30 namespace MCOI {
31 // Operand constraints
33  TIED_TO = 0, // Must be allocated the same register as.
34  EARLY_CLOBBER // Operand is an early clobber register operand
35 };
36 
37 /// These are flags set on operands, but should be considered
38 /// private, all access should go through the MCOperandInfo accessors.
39 /// See the accessors for a description of what these are.
41 
42 /// Operands are tagged with one of the values of this enum.
49 
58 
62 
64 };
65 
66 }
67 
68 /// This holds information about one operand of a machine instruction,
69 /// indicating the register class for register operands, etc.
71 public:
72  /// This specifies the register class enumeration of the operand
73  /// if the operand is a register. If isLookupPtrRegClass is set, then this is
74  /// an index that is passed to TargetRegisterInfo::getPointerRegClass(x) to
75  /// get a dynamic register class.
76  int16_t RegClass;
77 
78  /// These are flags from the MCOI::OperandFlags enum.
79  uint8_t Flags;
80 
81  /// Information about the type of the operand.
82  uint8_t OperandType;
83  /// The lower 16 bits are used to specify which constraints are set.
84  /// The higher 16 bits are used to specify the value of constraints (4 bits
85  /// each).
87 
88  /// Set if this operand is a pointer value and it requires a callback
89  /// to look up its register class.
90  bool isLookupPtrRegClass() const {
91  return Flags & (1 << MCOI::LookupPtrRegClass);
92  }
93 
94  /// Set if this is one of the operands that made up of the predicate
95  /// operand that controls an isPredicable() instruction.
96  bool isPredicate() const { return Flags & (1 << MCOI::Predicate); }
97 
98  /// Set if this operand is a optional def.
99  bool isOptionalDef() const { return Flags & (1 << MCOI::OptionalDef); }
100 
101  bool isGenericType() const {
102  return OperandType >= MCOI::OPERAND_FIRST_GENERIC &&
103  OperandType <= MCOI::OPERAND_LAST_GENERIC;
104  }
105 
106  unsigned getGenericTypeIndex() const {
107  assert(isGenericType() && "non-generic types don't have an index");
108  return OperandType - MCOI::OPERAND_FIRST_GENERIC;
109  }
110 
111  bool isGenericImm() const {
112  return OperandType >= MCOI::OPERAND_FIRST_GENERIC_IMM &&
113  OperandType <= MCOI::OPERAND_LAST_GENERIC_IMM;
114  }
115 
116  unsigned getGenericImmIndex() const {
117  assert(isGenericImm() && "non-generic immediates don't have an index");
118  return OperandType - MCOI::OPERAND_FIRST_GENERIC_IMM;
119  }
120 };
121 
122 //===----------------------------------------------------------------------===//
123 // Machine Instruction Flags and Description
124 //===----------------------------------------------------------------------===//
125 
126 namespace MCID {
127 /// These should be considered private to the implementation of the
128 /// MCInstrDesc class. Clients should use the predicate methods on MCInstrDesc,
129 /// not use these directly. These all correspond to bitfields in the
130 /// MCInstrDesc::Flags field.
131 enum Flag {
132  Variadic = 0,
170 };
171 }
172 
173 /// Describe properties that are true of each instruction in the target
174 /// description file. This captures information about side effects, register
175 /// use and many other things. There is one instance of this struct for each
176 /// target instruction class, and the MachineInstr class points to this struct
177 /// directly to describe itself.
178 class MCInstrDesc {
179 public:
180  unsigned short Opcode; // The opcode number
181  unsigned short NumOperands; // Num of args (may be more if variable_ops)
182  unsigned char NumDefs; // Num of args that are definitions
183  unsigned char Size; // Number of bytes in encoding.
184  unsigned short SchedClass; // enum identifying instr sched class
185  uint64_t Flags; // Flags identifying machine instr class
186  uint64_t TSFlags; // Target Specific Flag values
187  const MCPhysReg *ImplicitUses; // Registers implicitly read by this instr
188  const MCPhysReg *ImplicitDefs; // Registers implicitly defined by this instr
189  const MCOperandInfo *OpInfo; // 'NumOperands' entries about operands
190  // Subtarget feature that this is deprecated on, if any
191  // -1 implies this is not deprecated by any single feature. It may still be
192  // deprecated due to a "complex" reason, below.
194 
195  // A complex method to determine if a certain instruction is deprecated or
196  // not, and return the reason for deprecation.
197  bool (*ComplexDeprecationInfo)(MCInst &, const MCSubtargetInfo &,
198  std::string &);
199 
200  /// Returns the value of the specific constraint if
201  /// it is set. Returns -1 if it is not set.
202  int getOperandConstraint(unsigned OpNum,
203  MCOI::OperandConstraint Constraint) const {
204  if (OpNum < NumOperands &&
205  (OpInfo[OpNum].Constraints & (1 << Constraint))) {
206  unsigned Pos = 16 + Constraint * 4;
207  return (int)(OpInfo[OpNum].Constraints >> Pos) & 0xf;
208  }
209  return -1;
210  }
211 
212  /// Returns true if a certain instruction is deprecated and if so
213  /// returns the reason in \p Info.
214  bool getDeprecatedInfo(MCInst &MI, const MCSubtargetInfo &STI,
215  std::string &Info) const;
216 
217  /// Return the opcode number for this descriptor.
218  unsigned getOpcode() const { return Opcode; }
219 
220  /// Return the number of declared MachineOperands for this
221  /// MachineInstruction. Note that variadic (isVariadic() returns true)
222  /// instructions may have additional operands at the end of the list, and note
223  /// that the machine instruction may include implicit register def/uses as
224  /// well.
225  unsigned getNumOperands() const { return NumOperands; }
226 
228 
229  const_opInfo_iterator opInfo_begin() const { return OpInfo; }
230  const_opInfo_iterator opInfo_end() const { return OpInfo + NumOperands; }
231 
233  return make_range(opInfo_begin(), opInfo_end());
234  }
235 
236  /// Return the number of MachineOperands that are register
237  /// definitions. Register definitions always occur at the start of the
238  /// machine operand list. This is the number of "outs" in the .td file,
239  /// and does not include implicit defs.
240  unsigned getNumDefs() const { return NumDefs; }
241 
242  /// Return flags of this instruction.
243  uint64_t getFlags() const { return Flags; }
244 
245  /// Return true if this instruction can have a variable number of
246  /// operands. In this case, the variable operands will be after the normal
247  /// operands but before the implicit definitions and uses (if any are
248  /// present).
249  bool isVariadic() const { return Flags & (1ULL << MCID::Variadic); }
250 
251  /// Set if this instruction has an optional definition, e.g.
252  /// ARM instructions which can set condition code if 's' bit is set.
253  bool hasOptionalDef() const { return Flags & (1ULL << MCID::HasOptionalDef); }
254 
255  /// Return true if this is a pseudo instruction that doesn't
256  /// correspond to a real machine instruction.
257  bool isPseudo() const { return Flags & (1ULL << MCID::Pseudo); }
258 
259  /// Return true if the instruction is a return.
260  bool isReturn() const { return Flags & (1ULL << MCID::Return); }
261 
262  /// Return true if the instruction is an add instruction.
263  bool isAdd() const { return Flags & (1ULL << MCID::Add); }
264 
265  /// Return true if this instruction is a trap.
266  bool isTrap() const { return Flags & (1ULL << MCID::Trap); }
267 
268  /// Return true if the instruction is a register to register move.
269  bool isMoveReg() const { return Flags & (1ULL << MCID::MoveReg); }
270 
271  /// Return true if the instruction is a call.
272  bool isCall() const { return Flags & (1ULL << MCID::Call); }
273 
274  /// Returns true if the specified instruction stops control flow
275  /// from executing the instruction immediately following it. Examples include
276  /// unconditional branches and return instructions.
277  bool isBarrier() const { return Flags & (1ULL << MCID::Barrier); }
278 
279  /// Returns true if this instruction part of the terminator for
280  /// a basic block. Typically this is things like return and branch
281  /// instructions.
282  ///
283  /// Various passes use this to insert code into the bottom of a basic block,
284  /// but before control flow occurs.
285  bool isTerminator() const { return Flags & (1ULL << MCID::Terminator); }
286 
287  /// Returns true if this is a conditional, unconditional, or
288  /// indirect branch. Predicates below can be used to discriminate between
289  /// these cases, and the TargetInstrInfo::AnalyzeBranch method can be used to
290  /// get more information.
291  bool isBranch() const { return Flags & (1ULL << MCID::Branch); }
292 
293  /// Return true if this is an indirect branch, such as a
294  /// branch through a register.
295  bool isIndirectBranch() const { return Flags & (1ULL << MCID::IndirectBranch); }
296 
297  /// Return true if this is a branch which may fall
298  /// through to the next instruction or may transfer control flow to some other
299  /// block. The TargetInstrInfo::AnalyzeBranch method can be used to get more
300  /// information about this branch.
301  bool isConditionalBranch() const {
302  return isBranch() & !isBarrier() & !isIndirectBranch();
303  }
304 
305  /// Return true if this is a branch which always
306  /// transfers control flow to some other block. The
307  /// TargetInstrInfo::AnalyzeBranch method can be used to get more information
308  /// about this branch.
309  bool isUnconditionalBranch() const {
310  return isBranch() & isBarrier() & !isIndirectBranch();
311  }
312 
313  /// Return true if this is a branch or an instruction which directly
314  /// writes to the program counter. Considered 'may' affect rather than
315  /// 'does' affect as things like predication are not taken into account.
316  bool mayAffectControlFlow(const MCInst &MI, const MCRegisterInfo &RI) const;
317 
318  /// Return true if this instruction has a predicate operand
319  /// that controls execution. It may be set to 'always', or may be set to other
320  /// values. There are various methods in TargetInstrInfo that can be used to
321  /// control and modify the predicate in this instruction.
322  bool isPredicable() const { return Flags & (1ULL << MCID::Predicable); }
323 
324  /// Return true if this instruction is a comparison.
325  bool isCompare() const { return Flags & (1ULL << MCID::Compare); }
326 
327  /// Return true if this instruction is a move immediate
328  /// (including conditional moves) instruction.
329  bool isMoveImmediate() const { return Flags & (1ULL << MCID::MoveImm); }
330 
331  /// Return true if this instruction is a bitcast instruction.
332  bool isBitcast() const { return Flags & (1ULL << MCID::Bitcast); }
333 
334  /// Return true if this is a select instruction.
335  bool isSelect() const { return Flags & (1ULL << MCID::Select); }
336 
337  /// Return true if this instruction cannot be safely
338  /// duplicated. For example, if the instruction has a unique labels attached
339  /// to it, duplicating it would cause multiple definition errors.
340  bool isNotDuplicable() const { return Flags & (1ULL << MCID::NotDuplicable); }
341 
342  /// Returns true if the specified instruction has a delay slot which
343  /// must be filled by the code generator.
344  bool hasDelaySlot() const { return Flags & (1ULL << MCID::DelaySlot); }
345 
346  /// Return true for instructions that can be folded as memory operands
347  /// in other instructions. The most common use for this is instructions that
348  /// are simple loads from memory that don't modify the loaded value in any
349  /// way, but it can also be used for instructions that can be expressed as
350  /// constant-pool loads, such as V_SETALLONES on x86, to allow them to be
351  /// folded when it is beneficial. This should only be set on instructions
352  /// that return a value in their only virtual register definition.
353  bool canFoldAsLoad() const { return Flags & (1ULL << MCID::FoldableAsLoad); }
354 
355  /// Return true if this instruction behaves
356  /// the same way as the generic REG_SEQUENCE instructions.
357  /// E.g., on ARM,
358  /// dX VMOVDRR rY, rZ
359  /// is equivalent to
360  /// dX = REG_SEQUENCE rY, ssub_0, rZ, ssub_1.
361  ///
362  /// Note that for the optimizers to be able to take advantage of
363  /// this property, TargetInstrInfo::getRegSequenceLikeInputs has to be
364  /// override accordingly.
365  bool isRegSequenceLike() const { return Flags & (1ULL << MCID::RegSequence); }
366 
367  /// Return true if this instruction behaves
368  /// the same way as the generic EXTRACT_SUBREG instructions.
369  /// E.g., on ARM,
370  /// rX, rY VMOVRRD dZ
371  /// is equivalent to two EXTRACT_SUBREG:
372  /// rX = EXTRACT_SUBREG dZ, ssub_0
373  /// rY = EXTRACT_SUBREG dZ, ssub_1
374  ///
375  /// Note that for the optimizers to be able to take advantage of
376  /// this property, TargetInstrInfo::getExtractSubregLikeInputs has to be
377  /// override accordingly.
378  bool isExtractSubregLike() const {
379  return Flags & (1ULL << MCID::ExtractSubreg);
380  }
381 
382  /// Return true if this instruction behaves
383  /// the same way as the generic INSERT_SUBREG instructions.
384  /// E.g., on ARM,
385  /// dX = VSETLNi32 dY, rZ, Imm
386  /// is equivalent to a INSERT_SUBREG:
387  /// dX = INSERT_SUBREG dY, rZ, translateImmToSubIdx(Imm)
388  ///
389  /// Note that for the optimizers to be able to take advantage of
390  /// this property, TargetInstrInfo::getInsertSubregLikeInputs has to be
391  /// override accordingly.
392  bool isInsertSubregLike() const { return Flags & (1ULL << MCID::InsertSubreg); }
393 
394 
395  /// Return true if this instruction is convergent.
396  ///
397  /// Convergent instructions may not be made control-dependent on any
398  /// additional values.
399  bool isConvergent() const { return Flags & (1ULL << MCID::Convergent); }
400 
401  /// Return true if variadic operands of this instruction are definitions.
402  bool variadicOpsAreDefs() const {
403  return Flags & (1ULL << MCID::VariadicOpsAreDefs);
404  }
405 
406  //===--------------------------------------------------------------------===//
407  // Side Effect Analysis
408  //===--------------------------------------------------------------------===//
409 
410  /// Return true if this instruction could possibly read memory.
411  /// Instructions with this flag set are not necessarily simple load
412  /// instructions, they may load a value and modify it, for example.
413  bool mayLoad() const { return Flags & (1ULL << MCID::MayLoad); }
414 
415  /// Return true if this instruction could possibly modify memory.
416  /// Instructions with this flag set are not necessarily simple store
417  /// instructions, they may store a modified value based on their operands, or
418  /// may not actually modify anything, for example.
419  bool mayStore() const { return Flags & (1ULL << MCID::MayStore); }
420 
421  /// Return true if this instruction may raise a floating-point exception.
422  bool mayRaiseFPException() const {
423  return Flags & (1ULL << MCID::MayRaiseFPException);
424  }
425 
426  /// Return true if this instruction has side
427  /// effects that are not modeled by other flags. This does not return true
428  /// for instructions whose effects are captured by:
429  ///
430  /// 1. Their operand list and implicit definition/use list. Register use/def
431  /// info is explicit for instructions.
432  /// 2. Memory accesses. Use mayLoad/mayStore.
433  /// 3. Calling, branching, returning: use isCall/isReturn/isBranch.
434  ///
435  /// Examples of side effects would be modifying 'invisible' machine state like
436  /// a control register, flushing a cache, modifying a register invisible to
437  /// LLVM, etc.
438  bool hasUnmodeledSideEffects() const {
439  return Flags & (1ULL << MCID::UnmodeledSideEffects);
440  }
441 
442  //===--------------------------------------------------------------------===//
443  // Flags that indicate whether an instruction can be modified by a method.
444  //===--------------------------------------------------------------------===//
445 
446  /// Return true if this may be a 2- or 3-address instruction (of the
447  /// form "X = op Y, Z, ..."), which produces the same result if Y and Z are
448  /// exchanged. If this flag is set, then the
449  /// TargetInstrInfo::commuteInstruction method may be used to hack on the
450  /// instruction.
451  ///
452  /// Note that this flag may be set on instructions that are only commutable
453  /// sometimes. In these cases, the call to commuteInstruction will fail.
454  /// Also note that some instructions require non-trivial modification to
455  /// commute them.
456  bool isCommutable() const { return Flags & (1ULL << MCID::Commutable); }
457 
458  /// Return true if this is a 2-address instruction which can be changed
459  /// into a 3-address instruction if needed. Doing this transformation can be
460  /// profitable in the register allocator, because it means that the
461  /// instruction can use a 2-address form if possible, but degrade into a less
462  /// efficient form if the source and dest register cannot be assigned to the
463  /// same register. For example, this allows the x86 backend to turn a "shl
464  /// reg, 3" instruction into an LEA instruction, which is the same speed as
465  /// the shift but has bigger code size.
466  ///
467  /// If this returns true, then the target must implement the
468  /// TargetInstrInfo::convertToThreeAddress method for this instruction, which
469  /// is allowed to fail if the transformation isn't valid for this specific
470  /// instruction (e.g. shl reg, 4 on x86).
471  ///
472  bool isConvertibleTo3Addr() const {
473  return Flags & (1ULL << MCID::ConvertibleTo3Addr);
474  }
475 
476  /// Return true if this instruction requires custom insertion support
477  /// when the DAG scheduler is inserting it into a machine basic block. If
478  /// this is true for the instruction, it basically means that it is a pseudo
479  /// instruction used at SelectionDAG time that is expanded out into magic code
480  /// by the target when MachineInstrs are formed.
481  ///
482  /// If this is true, the TargetLoweringInfo::InsertAtEndOfBasicBlock method
483  /// is used to insert this into the MachineBasicBlock.
484  bool usesCustomInsertionHook() const {
485  return Flags & (1ULL << MCID::UsesCustomInserter);
486  }
487 
488  /// Return true if this instruction requires *adjustment* after
489  /// instruction selection by calling a target hook. For example, this can be
490  /// used to fill in ARM 's' optional operand depending on whether the
491  /// conditional flag register is used.
492  bool hasPostISelHook() const { return Flags & (1ULL << MCID::HasPostISelHook); }
493 
494  /// Returns true if this instruction is a candidate for remat. This
495  /// flag is only used in TargetInstrInfo method isTriviallyRematerializable.
496  ///
497  /// If this flag is set, the isReallyTriviallyReMaterializable()
498  /// or isReallyTriviallyReMaterializableGeneric methods are called to verify
499  /// the instruction is really rematable.
500  bool isRematerializable() const {
501  return Flags & (1ULL << MCID::Rematerializable);
502  }
503 
504  /// Returns true if this instruction has the same cost (or less) than a
505  /// move instruction. This is useful during certain types of optimizations
506  /// (e.g., remat during two-address conversion or machine licm) where we would
507  /// like to remat or hoist the instruction, but not if it costs more than
508  /// moving the instruction into the appropriate register. Note, we are not
509  /// marking copies from and to the same register class with this flag.
510  ///
511  /// This method could be called by interface TargetInstrInfo::isAsCheapAsAMove
512  /// for different subtargets.
513  bool isAsCheapAsAMove() const { return Flags & (1ULL << MCID::CheapAsAMove); }
514 
515  /// Returns true if this instruction source operands have special
516  /// register allocation requirements that are not captured by the operand
517  /// register classes. e.g. ARM::STRD's two source registers must be an even /
518  /// odd pair, ARM::STM registers have to be in ascending order. Post-register
519  /// allocation passes should not attempt to change allocations for sources of
520  /// instructions with this flag.
521  bool hasExtraSrcRegAllocReq() const {
522  return Flags & (1ULL << MCID::ExtraSrcRegAllocReq);
523  }
524 
525  /// Returns true if this instruction def operands have special register
526  /// allocation requirements that are not captured by the operand register
527  /// classes. e.g. ARM::LDRD's two def registers must be an even / odd pair,
528  /// ARM::LDM registers have to be in ascending order. Post-register
529  /// allocation passes should not attempt to change allocations for definitions
530  /// of instructions with this flag.
531  bool hasExtraDefRegAllocReq() const {
532  return Flags & (1ULL << MCID::ExtraDefRegAllocReq);
533  }
534 
535  /// Return a list of registers that are potentially read by any
536  /// instance of this machine instruction. For example, on X86, the "adc"
537  /// instruction adds two register operands and adds the carry bit in from the
538  /// flags register. In this case, the instruction is marked as implicitly
539  /// reading the flags. Likewise, the variable shift instruction on X86 is
540  /// marked as implicitly reading the 'CL' register, which it always does.
541  ///
542  /// This method returns null if the instruction has no implicit uses.
543  const MCPhysReg *getImplicitUses() const { return ImplicitUses; }
544 
545  /// Return the number of implicit uses this instruction has.
546  unsigned getNumImplicitUses() const {
547  if (!ImplicitUses)
548  return 0;
549  unsigned i = 0;
550  for (; ImplicitUses[i]; ++i) /*empty*/
551  ;
552  return i;
553  }
554 
555  /// Return a list of registers that are potentially written by any
556  /// instance of this machine instruction. For example, on X86, many
557  /// instructions implicitly set the flags register. In this case, they are
558  /// marked as setting the FLAGS. Likewise, many instructions always deposit
559  /// their result in a physical register. For example, the X86 divide
560  /// instruction always deposits the quotient and remainder in the EAX/EDX
561  /// registers. For that instruction, this will return a list containing the
562  /// EAX/EDX/EFLAGS registers.
563  ///
564  /// This method returns null if the instruction has no implicit defs.
565  const MCPhysReg *getImplicitDefs() const { return ImplicitDefs; }
566 
567  /// Return the number of implicit defs this instruct has.
568  unsigned getNumImplicitDefs() const {
569  if (!ImplicitDefs)
570  return 0;
571  unsigned i = 0;
572  for (; ImplicitDefs[i]; ++i) /*empty*/
573  ;
574  return i;
575  }
576 
577  /// Return true if this instruction implicitly
578  /// uses the specified physical register.
579  bool hasImplicitUseOfPhysReg(unsigned Reg) const {
580  if (const MCPhysReg *ImpUses = ImplicitUses)
581  for (; *ImpUses; ++ImpUses)
582  if (*ImpUses == Reg)
583  return true;
584  return false;
585  }
586 
587  /// Return true if this instruction implicitly
588  /// defines the specified physical register.
589  bool hasImplicitDefOfPhysReg(unsigned Reg,
590  const MCRegisterInfo *MRI = nullptr) const;
591 
592  /// Return the scheduling class for this instruction. The
593  /// scheduling class is an index into the InstrItineraryData table. This
594  /// returns zero if there is no known scheduling information for the
595  /// instruction.
596  unsigned getSchedClass() const { return SchedClass; }
597 
598  /// Return the number of bytes in the encoding of this instruction,
599  /// or zero if the encoding size cannot be known from the opcode.
600  unsigned getSize() const { return Size; }
601 
602  /// Find the index of the first operand in the
603  /// operand list that is used to represent the predicate. It returns -1 if
604  /// none is found.
606  if (isPredicable()) {
607  for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
608  if (OpInfo[i].isPredicate())
609  return i;
610  }
611  return -1;
612  }
613 
614  /// Return true if this instruction defines the specified physical
615  /// register, either explicitly or implicitly.
616  bool hasDefOfPhysReg(const MCInst &MI, unsigned Reg,
617  const MCRegisterInfo &RI) const;
618 };
619 
620 } // end namespace llvm
621 
622 #endif
unsigned getNumImplicitUses() const
Return the number of implicit uses this instruction has.
Definition: MCInstrDesc.h:546
bool isMoveReg() const
Return true if the instruction is a register to register move.
Definition: MCInstrDesc.h:269
unsigned getNumImplicitDefs() const
Return the number of implicit defs this instruct has.
Definition: MCInstrDesc.h:568
This class represents lattice values for constants.
Definition: AllocatorList.h:23
bool isLookupPtrRegClass() const
Set if this operand is a pointer value and it requires a callback to look up its register class...
Definition: MCInstrDesc.h:90
bool isCommutable() const
Return true if this may be a 2- or 3-address instruction (of the form "X = op Y, Z, ..."), which produces the same result if Y and Z are exchanged.
Definition: MCInstrDesc.h:456
uint8_t Flags
These are flags from the MCOI::OperandFlags enum.
Definition: MCInstrDesc.h:79
unsigned char Size
Definition: MCInstrDesc.h:183
const MCPhysReg * getImplicitUses() const
Return a list of registers that are potentially read by any instance of this machine instruction...
Definition: MCInstrDesc.h:543
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:178
unsigned Reg
int findFirstPredOperandIdx() const
Find the index of the first operand in the operand list that is used to represent the predicate...
Definition: MCInstrDesc.h:605
bool hasUnmodeledSideEffects() const
Return true if this instruction has side effects that are not modeled by other flags.
Definition: MCInstrDesc.h:438
bool isRegSequenceLike() const
Return true if this instruction behaves the same way as the generic REG_SEQUENCE instructions.
Definition: MCInstrDesc.h:365
const_opInfo_iterator opInfo_begin() const
Definition: MCInstrDesc.h:229
bool isPseudo() const
Return true if this is a pseudo instruction that doesn&#39;t correspond to a real machine instruction...
Definition: MCInstrDesc.h:257
bool mayLoad() const
Return true if this instruction could possibly read memory.
Definition: MCInstrDesc.h:413
bool isReturn() const
Return true if the instruction is a return.
Definition: MCInstrDesc.h:260
bool isBranch() const
Returns true if this is a conditional, unconditional, or indirect branch.
Definition: MCInstrDesc.h:291
bool isCompare() const
Return true if this instruction is a comparison.
Definition: MCInstrDesc.h:325
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
Definition: MCInstrDesc.h:225
bool isTrap() const
Return true if this instruction is a trap.
Definition: MCInstrDesc.h:266
bool isExtractSubregLike() const
Return true if this instruction behaves the same way as the generic EXTRACT_SUBREG instructions...
Definition: MCInstrDesc.h:378
bool isSelect() const
Return true if this is a select instruction.
Definition: MCInstrDesc.h:335
uint8_t OperandType
Information about the type of the operand.
Definition: MCInstrDesc.h:82
bool isConvertibleTo3Addr() const
Return true if this is a 2-address instruction which can be changed into a 3-address instruction if n...
Definition: MCInstrDesc.h:472
bool isRematerializable() const
Returns true if this instruction is a candidate for remat.
Definition: MCInstrDesc.h:500
uint32_t Constraints
The lower 16 bits are used to specify which constraints are set.
Definition: MCInstrDesc.h:86
bool isAsCheapAsAMove() const
Returns true if this instruction has the same cost (or less) than a move instruction.
Definition: MCInstrDesc.h:513
bool isPredicate() const
Set if this is one of the operands that made up of the predicate operand that controls an isPredicabl...
Definition: MCInstrDesc.h:96
bool hasExtraDefRegAllocReq() const
Returns true if this instruction def operands have special register allocation requirements that are ...
Definition: MCInstrDesc.h:531
bool isMoveImmediate() const
Return true if this instruction is a move immediate (including conditional moves) instruction...
Definition: MCInstrDesc.h:329
Analysis containing CSE Info
Definition: CSEInfo.cpp:20
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:158
unsigned short NumOperands
Definition: MCInstrDesc.h:181
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
Definition: MCRegister.h:19
Flag
These should be considered private to the implementation of the MCInstrDesc class.
Definition: MCInstrDesc.h:131
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
unsigned getSchedClass() const
Return the scheduling class for this instruction.
Definition: MCInstrDesc.h:596
bool isGenericType() const
Definition: MCInstrDesc.h:101
const MCPhysReg * getImplicitDefs() const
Return a list of registers that are potentially written by any instance of this machine instruction...
Definition: MCInstrDesc.h:565
bool hasExtraSrcRegAllocReq() const
Returns true if this instruction source operands have special register allocation requirements that a...
Definition: MCInstrDesc.h:521
unsigned const MachineRegisterInfo * MRI
bool isOptionalDef() const
Set if this operand is a optional def.
Definition: MCInstrDesc.h:99
bool hasOptionalDef() const
Set if this instruction has an optional definition, e.g.
Definition: MCInstrDesc.h:253
bool isBarrier() const
Returns true if the specified instruction stops control flow from executing the instruction immediate...
Definition: MCInstrDesc.h:277
bool isVariadic() const
Return true if this instruction can have a variable number of operands.
Definition: MCInstrDesc.h:249
bool isConditionalBranch() const
Return true if this is a branch which may fall through to the next instruction or may transfer contro...
Definition: MCInstrDesc.h:301
int64_t DeprecatedFeature
Definition: MCInstrDesc.h:193
OperandFlags
These are flags set on operands, but should be considered private, all access should go through the M...
Definition: MCInstrDesc.h:40
const MCPhysReg * ImplicitDefs
Definition: MCInstrDesc.h:188
bool isPredicable() const
Return true if this instruction has a predicate operand that controls execution.
Definition: MCInstrDesc.h:322
bool isIndirectBranch() const
Return true if this is an indirect branch, such as a branch through a register.
Definition: MCInstrDesc.h:295
bool hasPostISelHook() const
Return true if this instruction requires adjustment after instruction selection by calling a target h...
Definition: MCInstrDesc.h:492
unsigned char NumDefs
Definition: MCInstrDesc.h:182
bool mayRaiseFPException() const
Return true if this instruction may raise a floating-point exception.
Definition: MCInstrDesc.h:422
bool isAdd() const
Return true if the instruction is an add instruction.
Definition: MCInstrDesc.h:263
bool isNotDuplicable() const
Return true if this instruction cannot be safely duplicated.
Definition: MCInstrDesc.h:340
int getOperandConstraint(unsigned OpNum, MCOI::OperandConstraint Constraint) const
Returns the value of the specific constraint if it is set.
Definition: MCInstrDesc.h:202
iterator_range< T > make_range(T x, T y)
Convenience function for iterating over sub-ranges.
bool isInsertSubregLike() const
Return true if this instruction behaves the same way as the generic INSERT_SUBREG instructions...
Definition: MCInstrDesc.h:392
bool hasDelaySlot() const
Returns true if the specified instruction has a delay slot which must be filled by the code generator...
Definition: MCInstrDesc.h:344
bool isBitcast() const
Return true if this instruction is a bitcast instruction.
Definition: MCInstrDesc.h:332
unsigned getNumDefs() const
Return the number of MachineOperands that are register definitions.
Definition: MCInstrDesc.h:240
unsigned short Opcode
Definition: MCInstrDesc.h:180
A range adaptor for a pair of iterators.
bool isConvergent() const
Return true if this instruction is convergent.
Definition: MCInstrDesc.h:399
bool mayStore() const
Return true if this instruction could possibly modify memory.
Definition: MCInstrDesc.h:419
bool isUnconditionalBranch() const
Return true if this is a branch which always transfers control flow to some other block...
Definition: MCInstrDesc.h:309
OperandType
Operands are tagged with one of the values of this enum.
Definition: MCInstrDesc.h:43
bool canFoldAsLoad() const
Return true for instructions that can be folded as memory operands in other instructions.
Definition: MCInstrDesc.h:353
int16_t RegClass
This specifies the register class enumeration of the operand if the operand is a register.
Definition: MCInstrDesc.h:76
const_opInfo_iterator opInfo_end() const
Definition: MCInstrDesc.h:230
bool isCall() const
Return true if the instruction is a call.
Definition: MCInstrDesc.h:272
Generic base class for all target subtargets.
bool isGenericImm() const
Definition: MCInstrDesc.h:111
uint32_t Size
Definition: Profile.cpp:46
bool variadicOpsAreDefs() const
Return true if variadic operands of this instruction are definitions.
Definition: MCInstrDesc.h:402
iterator_range< const_opInfo_iterator > operands() const
Definition: MCInstrDesc.h:232
unsigned getGenericImmIndex() const
Definition: MCInstrDesc.h:116
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static bool isBranch(unsigned Opcode)
bool hasImplicitUseOfPhysReg(unsigned Reg) const
Return true if this instruction implicitly uses the specified physical register.
Definition: MCInstrDesc.h:579
bool isTerminator() const
Returns true if this instruction part of the terminator for a basic block.
Definition: MCInstrDesc.h:285
const MCOperandInfo * OpInfo
Definition: MCInstrDesc.h:189
unsigned getOpcode() const
Return the opcode number for this descriptor.
Definition: MCInstrDesc.h:218
unsigned getGenericTypeIndex() const
Definition: MCInstrDesc.h:106
IRTranslator LLVM IR MI
bool usesCustomInsertionHook() const
Return true if this instruction requires custom insertion support when the DAG scheduler is inserting...
Definition: MCInstrDesc.h:484
This holds information about one operand of a machine instruction, indicating the register class for ...
Definition: MCInstrDesc.h:70
uint64_t getFlags() const
Return flags of this instruction.
Definition: MCInstrDesc.h:243
unsigned short SchedClass
Definition: MCInstrDesc.h:184
const MCPhysReg * ImplicitUses
Definition: MCInstrDesc.h:187
unsigned getSize() const
Return the number of bytes in the encoding of this instruction, or zero if the encoding size cannot b...
Definition: MCInstrDesc.h:600