LLVM  9.0.0svn
MCInstrDesc.h
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1 //===-- llvm/MC/MCInstrDesc.h - Instruction Descriptors -*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file defines the MCOperandInfo and MCInstrDesc classes, which
10 // are used to describe target instructions and their operands.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_MC_MCINSTRDESC_H
15 #define LLVM_MC_MCINSTRDESC_H
16 
17 #include "llvm/MC/MCRegisterInfo.h"
18 #include "llvm/Support/DataTypes.h"
19 #include <string>
20 
21 namespace llvm {
22  class MCInst;
23  class MCSubtargetInfo;
24  class FeatureBitset;
25 
26 //===----------------------------------------------------------------------===//
27 // Machine Operand Flags and Description
28 //===----------------------------------------------------------------------===//
29 
30 namespace MCOI {
31 // Operand constraints
33  TIED_TO = 0, // Must be allocated the same register as.
34  EARLY_CLOBBER // Operand is an early clobber register operand
35 };
36 
37 /// These are flags set on operands, but should be considered
38 /// private, all access should go through the MCOperandInfo accessors.
39 /// See the accessors for a description of what these are.
41 
42 /// Operands are tagged with one of the values of this enum.
49 
58 
60 };
61 
62 }
63 
64 /// This holds information about one operand of a machine instruction,
65 /// indicating the register class for register operands, etc.
67 public:
68  /// This specifies the register class enumeration of the operand
69  /// if the operand is a register. If isLookupPtrRegClass is set, then this is
70  /// an index that is passed to TargetRegisterInfo::getPointerRegClass(x) to
71  /// get a dynamic register class.
72  int16_t RegClass;
73 
74  /// These are flags from the MCOI::OperandFlags enum.
75  uint8_t Flags;
76 
77  /// Information about the type of the operand.
78  uint8_t OperandType;
79  /// The lower 16 bits are used to specify which constraints are set.
80  /// The higher 16 bits are used to specify the value of constraints (4 bits
81  /// each).
83 
84  /// Set if this operand is a pointer value and it requires a callback
85  /// to look up its register class.
86  bool isLookupPtrRegClass() const {
87  return Flags & (1 << MCOI::LookupPtrRegClass);
88  }
89 
90  /// Set if this is one of the operands that made up of the predicate
91  /// operand that controls an isPredicable() instruction.
92  bool isPredicate() const { return Flags & (1 << MCOI::Predicate); }
93 
94  /// Set if this operand is a optional def.
95  bool isOptionalDef() const { return Flags & (1 << MCOI::OptionalDef); }
96 
97  bool isGenericType() const {
98  return OperandType >= MCOI::OPERAND_FIRST_GENERIC &&
99  OperandType <= MCOI::OPERAND_LAST_GENERIC;
100  }
101 
102  unsigned getGenericTypeIndex() const {
103  assert(isGenericType() && "non-generic types don't have an index");
104  return OperandType - MCOI::OPERAND_FIRST_GENERIC;
105  }
106 };
107 
108 //===----------------------------------------------------------------------===//
109 // Machine Instruction Flags and Description
110 //===----------------------------------------------------------------------===//
111 
112 namespace MCID {
113 /// These should be considered private to the implementation of the
114 /// MCInstrDesc class. Clients should use the predicate methods on MCInstrDesc,
115 /// not use these directly. These all correspond to bitfields in the
116 /// MCInstrDesc::Flags field.
117 enum Flag {
118  Variadic = 0,
155 };
156 }
157 
158 /// Describe properties that are true of each instruction in the target
159 /// description file. This captures information about side effects, register
160 /// use and many other things. There is one instance of this struct for each
161 /// target instruction class, and the MachineInstr class points to this struct
162 /// directly to describe itself.
163 class MCInstrDesc {
164 public:
165  unsigned short Opcode; // The opcode number
166  unsigned short NumOperands; // Num of args (may be more if variable_ops)
167  unsigned char NumDefs; // Num of args that are definitions
168  unsigned char Size; // Number of bytes in encoding.
169  unsigned short SchedClass; // enum identifying instr sched class
170  uint64_t Flags; // Flags identifying machine instr class
171  uint64_t TSFlags; // Target Specific Flag values
172  const MCPhysReg *ImplicitUses; // Registers implicitly read by this instr
173  const MCPhysReg *ImplicitDefs; // Registers implicitly defined by this instr
174  const MCOperandInfo *OpInfo; // 'NumOperands' entries about operands
175  // Subtarget feature that this is deprecated on, if any
176  // -1 implies this is not deprecated by any single feature. It may still be
177  // deprecated due to a "complex" reason, below.
179 
180  // A complex method to determine if a certain instruction is deprecated or
181  // not, and return the reason for deprecation.
182  bool (*ComplexDeprecationInfo)(MCInst &, const MCSubtargetInfo &,
183  std::string &);
184 
185  /// Returns the value of the specific constraint if
186  /// it is set. Returns -1 if it is not set.
187  int getOperandConstraint(unsigned OpNum,
188  MCOI::OperandConstraint Constraint) const {
189  if (OpNum < NumOperands &&
190  (OpInfo[OpNum].Constraints & (1 << Constraint))) {
191  unsigned Pos = 16 + Constraint * 4;
192  return (int)(OpInfo[OpNum].Constraints >> Pos) & 0xf;
193  }
194  return -1;
195  }
196 
197  /// Returns true if a certain instruction is deprecated and if so
198  /// returns the reason in \p Info.
199  bool getDeprecatedInfo(MCInst &MI, const MCSubtargetInfo &STI,
200  std::string &Info) const;
201 
202  /// Return the opcode number for this descriptor.
203  unsigned getOpcode() const { return Opcode; }
204 
205  /// Return the number of declared MachineOperands for this
206  /// MachineInstruction. Note that variadic (isVariadic() returns true)
207  /// instructions may have additional operands at the end of the list, and note
208  /// that the machine instruction may include implicit register def/uses as
209  /// well.
210  unsigned getNumOperands() const { return NumOperands; }
211 
213 
214  const_opInfo_iterator opInfo_begin() const { return OpInfo; }
215  const_opInfo_iterator opInfo_end() const { return OpInfo + NumOperands; }
216 
218  return make_range(opInfo_begin(), opInfo_end());
219  }
220 
221  /// Return the number of MachineOperands that are register
222  /// definitions. Register definitions always occur at the start of the
223  /// machine operand list. This is the number of "outs" in the .td file,
224  /// and does not include implicit defs.
225  unsigned getNumDefs() const { return NumDefs; }
226 
227  /// Return flags of this instruction.
228  uint64_t getFlags() const { return Flags; }
229 
230  /// Return true if this instruction can have a variable number of
231  /// operands. In this case, the variable operands will be after the normal
232  /// operands but before the implicit definitions and uses (if any are
233  /// present).
234  bool isVariadic() const { return Flags & (1ULL << MCID::Variadic); }
235 
236  /// Set if this instruction has an optional definition, e.g.
237  /// ARM instructions which can set condition code if 's' bit is set.
238  bool hasOptionalDef() const { return Flags & (1ULL << MCID::HasOptionalDef); }
239 
240  /// Return true if this is a pseudo instruction that doesn't
241  /// correspond to a real machine instruction.
242  bool isPseudo() const { return Flags & (1ULL << MCID::Pseudo); }
243 
244  /// Return true if the instruction is a return.
245  bool isReturn() const { return Flags & (1ULL << MCID::Return); }
246 
247  /// Return true if the instruction is an add instruction.
248  bool isAdd() const { return Flags & (1ULL << MCID::Add); }
249 
250  /// Return true if this instruction is a trap.
251  bool isTrap() const { return Flags & (1ULL << MCID::Trap); }
252 
253  /// Return true if the instruction is a register to register move.
254  bool isMoveReg() const { return Flags & (1ULL << MCID::MoveReg); }
255 
256  /// Return true if the instruction is a call.
257  bool isCall() const { return Flags & (1ULL << MCID::Call); }
258 
259  /// Returns true if the specified instruction stops control flow
260  /// from executing the instruction immediately following it. Examples include
261  /// unconditional branches and return instructions.
262  bool isBarrier() const { return Flags & (1ULL << MCID::Barrier); }
263 
264  /// Returns true if this instruction part of the terminator for
265  /// a basic block. Typically this is things like return and branch
266  /// instructions.
267  ///
268  /// Various passes use this to insert code into the bottom of a basic block,
269  /// but before control flow occurs.
270  bool isTerminator() const { return Flags & (1ULL << MCID::Terminator); }
271 
272  /// Returns true if this is a conditional, unconditional, or
273  /// indirect branch. Predicates below can be used to discriminate between
274  /// these cases, and the TargetInstrInfo::AnalyzeBranch method can be used to
275  /// get more information.
276  bool isBranch() const { return Flags & (1ULL << MCID::Branch); }
277 
278  /// Return true if this is an indirect branch, such as a
279  /// branch through a register.
280  bool isIndirectBranch() const { return Flags & (1ULL << MCID::IndirectBranch); }
281 
282  /// Return true if this is a branch which may fall
283  /// through to the next instruction or may transfer control flow to some other
284  /// block. The TargetInstrInfo::AnalyzeBranch method can be used to get more
285  /// information about this branch.
286  bool isConditionalBranch() const {
287  return isBranch() & !isBarrier() & !isIndirectBranch();
288  }
289 
290  /// Return true if this is a branch which always
291  /// transfers control flow to some other block. The
292  /// TargetInstrInfo::AnalyzeBranch method can be used to get more information
293  /// about this branch.
294  bool isUnconditionalBranch() const {
295  return isBranch() & isBarrier() & !isIndirectBranch();
296  }
297 
298  /// Return true if this is a branch or an instruction which directly
299  /// writes to the program counter. Considered 'may' affect rather than
300  /// 'does' affect as things like predication are not taken into account.
301  bool mayAffectControlFlow(const MCInst &MI, const MCRegisterInfo &RI) const;
302 
303  /// Return true if this instruction has a predicate operand
304  /// that controls execution. It may be set to 'always', or may be set to other
305  /// values. There are various methods in TargetInstrInfo that can be used to
306  /// control and modify the predicate in this instruction.
307  bool isPredicable() const { return Flags & (1ULL << MCID::Predicable); }
308 
309  /// Return true if this instruction is a comparison.
310  bool isCompare() const { return Flags & (1ULL << MCID::Compare); }
311 
312  /// Return true if this instruction is a move immediate
313  /// (including conditional moves) instruction.
314  bool isMoveImmediate() const { return Flags & (1ULL << MCID::MoveImm); }
315 
316  /// Return true if this instruction is a bitcast instruction.
317  bool isBitcast() const { return Flags & (1ULL << MCID::Bitcast); }
318 
319  /// Return true if this is a select instruction.
320  bool isSelect() const { return Flags & (1ULL << MCID::Select); }
321 
322  /// Return true if this instruction cannot be safely
323  /// duplicated. For example, if the instruction has a unique labels attached
324  /// to it, duplicating it would cause multiple definition errors.
325  bool isNotDuplicable() const { return Flags & (1ULL << MCID::NotDuplicable); }
326 
327  /// Returns true if the specified instruction has a delay slot which
328  /// must be filled by the code generator.
329  bool hasDelaySlot() const { return Flags & (1ULL << MCID::DelaySlot); }
330 
331  /// Return true for instructions that can be folded as memory operands
332  /// in other instructions. The most common use for this is instructions that
333  /// are simple loads from memory that don't modify the loaded value in any
334  /// way, but it can also be used for instructions that can be expressed as
335  /// constant-pool loads, such as V_SETALLONES on x86, to allow them to be
336  /// folded when it is beneficial. This should only be set on instructions
337  /// that return a value in their only virtual register definition.
338  bool canFoldAsLoad() const { return Flags & (1ULL << MCID::FoldableAsLoad); }
339 
340  /// Return true if this instruction behaves
341  /// the same way as the generic REG_SEQUENCE instructions.
342  /// E.g., on ARM,
343  /// dX VMOVDRR rY, rZ
344  /// is equivalent to
345  /// dX = REG_SEQUENCE rY, ssub_0, rZ, ssub_1.
346  ///
347  /// Note that for the optimizers to be able to take advantage of
348  /// this property, TargetInstrInfo::getRegSequenceLikeInputs has to be
349  /// override accordingly.
350  bool isRegSequenceLike() const { return Flags & (1ULL << MCID::RegSequence); }
351 
352  /// Return true if this instruction behaves
353  /// the same way as the generic EXTRACT_SUBREG instructions.
354  /// E.g., on ARM,
355  /// rX, rY VMOVRRD dZ
356  /// is equivalent to two EXTRACT_SUBREG:
357  /// rX = EXTRACT_SUBREG dZ, ssub_0
358  /// rY = EXTRACT_SUBREG dZ, ssub_1
359  ///
360  /// Note that for the optimizers to be able to take advantage of
361  /// this property, TargetInstrInfo::getExtractSubregLikeInputs has to be
362  /// override accordingly.
363  bool isExtractSubregLike() const {
364  return Flags & (1ULL << MCID::ExtractSubreg);
365  }
366 
367  /// Return true if this instruction behaves
368  /// the same way as the generic INSERT_SUBREG instructions.
369  /// E.g., on ARM,
370  /// dX = VSETLNi32 dY, rZ, Imm
371  /// is equivalent to a INSERT_SUBREG:
372  /// dX = INSERT_SUBREG dY, rZ, translateImmToSubIdx(Imm)
373  ///
374  /// Note that for the optimizers to be able to take advantage of
375  /// this property, TargetInstrInfo::getInsertSubregLikeInputs has to be
376  /// override accordingly.
377  bool isInsertSubregLike() const { return Flags & (1ULL << MCID::InsertSubreg); }
378 
379 
380  /// Return true if this instruction is convergent.
381  ///
382  /// Convergent instructions may not be made control-dependent on any
383  /// additional values.
384  bool isConvergent() const { return Flags & (1ULL << MCID::Convergent); }
385 
386  /// Return true if variadic operands of this instruction are definitions.
387  bool variadicOpsAreDefs() const {
388  return Flags & (1ULL << MCID::VariadicOpsAreDefs);
389  }
390 
391  //===--------------------------------------------------------------------===//
392  // Side Effect Analysis
393  //===--------------------------------------------------------------------===//
394 
395  /// Return true if this instruction could possibly read memory.
396  /// Instructions with this flag set are not necessarily simple load
397  /// instructions, they may load a value and modify it, for example.
398  bool mayLoad() const { return Flags & (1ULL << MCID::MayLoad); }
399 
400  /// Return true if this instruction could possibly modify memory.
401  /// Instructions with this flag set are not necessarily simple store
402  /// instructions, they may store a modified value based on their operands, or
403  /// may not actually modify anything, for example.
404  bool mayStore() const { return Flags & (1ULL << MCID::MayStore); }
405 
406  /// Return true if this instruction has side
407  /// effects that are not modeled by other flags. This does not return true
408  /// for instructions whose effects are captured by:
409  ///
410  /// 1. Their operand list and implicit definition/use list. Register use/def
411  /// info is explicit for instructions.
412  /// 2. Memory accesses. Use mayLoad/mayStore.
413  /// 3. Calling, branching, returning: use isCall/isReturn/isBranch.
414  ///
415  /// Examples of side effects would be modifying 'invisible' machine state like
416  /// a control register, flushing a cache, modifying a register invisible to
417  /// LLVM, etc.
418  bool hasUnmodeledSideEffects() const {
419  return Flags & (1ULL << MCID::UnmodeledSideEffects);
420  }
421 
422  //===--------------------------------------------------------------------===//
423  // Flags that indicate whether an instruction can be modified by a method.
424  //===--------------------------------------------------------------------===//
425 
426  /// Return true if this may be a 2- or 3-address instruction (of the
427  /// form "X = op Y, Z, ..."), which produces the same result if Y and Z are
428  /// exchanged. If this flag is set, then the
429  /// TargetInstrInfo::commuteInstruction method may be used to hack on the
430  /// instruction.
431  ///
432  /// Note that this flag may be set on instructions that are only commutable
433  /// sometimes. In these cases, the call to commuteInstruction will fail.
434  /// Also note that some instructions require non-trivial modification to
435  /// commute them.
436  bool isCommutable() const { return Flags & (1ULL << MCID::Commutable); }
437 
438  /// Return true if this is a 2-address instruction which can be changed
439  /// into a 3-address instruction if needed. Doing this transformation can be
440  /// profitable in the register allocator, because it means that the
441  /// instruction can use a 2-address form if possible, but degrade into a less
442  /// efficient form if the source and dest register cannot be assigned to the
443  /// same register. For example, this allows the x86 backend to turn a "shl
444  /// reg, 3" instruction into an LEA instruction, which is the same speed as
445  /// the shift but has bigger code size.
446  ///
447  /// If this returns true, then the target must implement the
448  /// TargetInstrInfo::convertToThreeAddress method for this instruction, which
449  /// is allowed to fail if the transformation isn't valid for this specific
450  /// instruction (e.g. shl reg, 4 on x86).
451  ///
452  bool isConvertibleTo3Addr() const {
453  return Flags & (1ULL << MCID::ConvertibleTo3Addr);
454  }
455 
456  /// Return true if this instruction requires custom insertion support
457  /// when the DAG scheduler is inserting it into a machine basic block. If
458  /// this is true for the instruction, it basically means that it is a pseudo
459  /// instruction used at SelectionDAG time that is expanded out into magic code
460  /// by the target when MachineInstrs are formed.
461  ///
462  /// If this is true, the TargetLoweringInfo::InsertAtEndOfBasicBlock method
463  /// is used to insert this into the MachineBasicBlock.
464  bool usesCustomInsertionHook() const {
465  return Flags & (1ULL << MCID::UsesCustomInserter);
466  }
467 
468  /// Return true if this instruction requires *adjustment* after
469  /// instruction selection by calling a target hook. For example, this can be
470  /// used to fill in ARM 's' optional operand depending on whether the
471  /// conditional flag register is used.
472  bool hasPostISelHook() const { return Flags & (1ULL << MCID::HasPostISelHook); }
473 
474  /// Returns true if this instruction is a candidate for remat. This
475  /// flag is only used in TargetInstrInfo method isTriviallyRematerializable.
476  ///
477  /// If this flag is set, the isReallyTriviallyReMaterializable()
478  /// or isReallyTriviallyReMaterializableGeneric methods are called to verify
479  /// the instruction is really rematable.
480  bool isRematerializable() const {
481  return Flags & (1ULL << MCID::Rematerializable);
482  }
483 
484  /// Returns true if this instruction has the same cost (or less) than a
485  /// move instruction. This is useful during certain types of optimizations
486  /// (e.g., remat during two-address conversion or machine licm) where we would
487  /// like to remat or hoist the instruction, but not if it costs more than
488  /// moving the instruction into the appropriate register. Note, we are not
489  /// marking copies from and to the same register class with this flag.
490  ///
491  /// This method could be called by interface TargetInstrInfo::isAsCheapAsAMove
492  /// for different subtargets.
493  bool isAsCheapAsAMove() const { return Flags & (1ULL << MCID::CheapAsAMove); }
494 
495  /// Returns true if this instruction source operands have special
496  /// register allocation requirements that are not captured by the operand
497  /// register classes. e.g. ARM::STRD's two source registers must be an even /
498  /// odd pair, ARM::STM registers have to be in ascending order. Post-register
499  /// allocation passes should not attempt to change allocations for sources of
500  /// instructions with this flag.
501  bool hasExtraSrcRegAllocReq() const {
502  return Flags & (1ULL << MCID::ExtraSrcRegAllocReq);
503  }
504 
505  /// Returns true if this instruction def operands have special register
506  /// allocation requirements that are not captured by the operand register
507  /// classes. e.g. ARM::LDRD's two def registers must be an even / odd pair,
508  /// ARM::LDM registers have to be in ascending order. Post-register
509  /// allocation passes should not attempt to change allocations for definitions
510  /// of instructions with this flag.
511  bool hasExtraDefRegAllocReq() const {
512  return Flags & (1ULL << MCID::ExtraDefRegAllocReq);
513  }
514 
515  /// Return a list of registers that are potentially read by any
516  /// instance of this machine instruction. For example, on X86, the "adc"
517  /// instruction adds two register operands and adds the carry bit in from the
518  /// flags register. In this case, the instruction is marked as implicitly
519  /// reading the flags. Likewise, the variable shift instruction on X86 is
520  /// marked as implicitly reading the 'CL' register, which it always does.
521  ///
522  /// This method returns null if the instruction has no implicit uses.
523  const MCPhysReg *getImplicitUses() const { return ImplicitUses; }
524 
525  /// Return the number of implicit uses this instruction has.
526  unsigned getNumImplicitUses() const {
527  if (!ImplicitUses)
528  return 0;
529  unsigned i = 0;
530  for (; ImplicitUses[i]; ++i) /*empty*/
531  ;
532  return i;
533  }
534 
535  /// Return a list of registers that are potentially written by any
536  /// instance of this machine instruction. For example, on X86, many
537  /// instructions implicitly set the flags register. In this case, they are
538  /// marked as setting the FLAGS. Likewise, many instructions always deposit
539  /// their result in a physical register. For example, the X86 divide
540  /// instruction always deposits the quotient and remainder in the EAX/EDX
541  /// registers. For that instruction, this will return a list containing the
542  /// EAX/EDX/EFLAGS registers.
543  ///
544  /// This method returns null if the instruction has no implicit defs.
545  const MCPhysReg *getImplicitDefs() const { return ImplicitDefs; }
546 
547  /// Return the number of implicit defs this instruct has.
548  unsigned getNumImplicitDefs() const {
549  if (!ImplicitDefs)
550  return 0;
551  unsigned i = 0;
552  for (; ImplicitDefs[i]; ++i) /*empty*/
553  ;
554  return i;
555  }
556 
557  /// Return true if this instruction implicitly
558  /// uses the specified physical register.
559  bool hasImplicitUseOfPhysReg(unsigned Reg) const {
560  if (const MCPhysReg *ImpUses = ImplicitUses)
561  for (; *ImpUses; ++ImpUses)
562  if (*ImpUses == Reg)
563  return true;
564  return false;
565  }
566 
567  /// Return true if this instruction implicitly
568  /// defines the specified physical register.
569  bool hasImplicitDefOfPhysReg(unsigned Reg,
570  const MCRegisterInfo *MRI = nullptr) const;
571 
572  /// Return the scheduling class for this instruction. The
573  /// scheduling class is an index into the InstrItineraryData table. This
574  /// returns zero if there is no known scheduling information for the
575  /// instruction.
576  unsigned getSchedClass() const { return SchedClass; }
577 
578  /// Return the number of bytes in the encoding of this instruction,
579  /// or zero if the encoding size cannot be known from the opcode.
580  unsigned getSize() const { return Size; }
581 
582  /// Find the index of the first operand in the
583  /// operand list that is used to represent the predicate. It returns -1 if
584  /// none is found.
586  if (isPredicable()) {
587  for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
588  if (OpInfo[i].isPredicate())
589  return i;
590  }
591  return -1;
592  }
593 
594  /// Return true if this instruction defines the specified physical
595  /// register, either explicitly or implicitly.
596  bool hasDefOfPhysReg(const MCInst &MI, unsigned Reg,
597  const MCRegisterInfo &RI) const;
598 };
599 
600 } // end namespace llvm
601 
602 #endif
unsigned getNumImplicitUses() const
Return the number of implicit uses this instruction has.
Definition: MCInstrDesc.h:526
bool isMoveReg() const
Return true if the instruction is a register to register move.
Definition: MCInstrDesc.h:254
unsigned getNumImplicitDefs() const
Return the number of implicit defs this instruct has.
Definition: MCInstrDesc.h:548
This class represents lattice values for constants.
Definition: AllocatorList.h:23
bool isLookupPtrRegClass() const
Set if this operand is a pointer value and it requires a callback to look up its register class...
Definition: MCInstrDesc.h:86
bool isCommutable() const
Return true if this may be a 2- or 3-address instruction (of the form "X = op Y, Z, ..."), which produces the same result if Y and Z are exchanged.
Definition: MCInstrDesc.h:436
uint8_t Flags
These are flags from the MCOI::OperandFlags enum.
Definition: MCInstrDesc.h:75
unsigned char Size
Definition: MCInstrDesc.h:168
const MCPhysReg * getImplicitUses() const
Return a list of registers that are potentially read by any instance of this machine instruction...
Definition: MCInstrDesc.h:523
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:163
unsigned Reg
int findFirstPredOperandIdx() const
Find the index of the first operand in the operand list that is used to represent the predicate...
Definition: MCInstrDesc.h:585
bool hasUnmodeledSideEffects() const
Return true if this instruction has side effects that are not modeled by other flags.
Definition: MCInstrDesc.h:418
bool isRegSequenceLike() const
Return true if this instruction behaves the same way as the generic REG_SEQUENCE instructions.
Definition: MCInstrDesc.h:350
const_opInfo_iterator opInfo_begin() const
Definition: MCInstrDesc.h:214
bool isPseudo() const
Return true if this is a pseudo instruction that doesn&#39;t correspond to a real machine instruction...
Definition: MCInstrDesc.h:242
bool mayLoad() const
Return true if this instruction could possibly read memory.
Definition: MCInstrDesc.h:398
bool isReturn() const
Return true if the instruction is a return.
Definition: MCInstrDesc.h:245
bool isBranch() const
Returns true if this is a conditional, unconditional, or indirect branch.
Definition: MCInstrDesc.h:276
bool isCompare() const
Return true if this instruction is a comparison.
Definition: MCInstrDesc.h:310
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
Definition: MCInstrDesc.h:210
bool isTrap() const
Return true if this instruction is a trap.
Definition: MCInstrDesc.h:251
bool isExtractSubregLike() const
Return true if this instruction behaves the same way as the generic EXTRACT_SUBREG instructions...
Definition: MCInstrDesc.h:363
bool isSelect() const
Return true if this is a select instruction.
Definition: MCInstrDesc.h:320
uint8_t OperandType
Information about the type of the operand.
Definition: MCInstrDesc.h:78
bool isConvertibleTo3Addr() const
Return true if this is a 2-address instruction which can be changed into a 3-address instruction if n...
Definition: MCInstrDesc.h:452
bool isRematerializable() const
Returns true if this instruction is a candidate for remat.
Definition: MCInstrDesc.h:480
uint32_t Constraints
The lower 16 bits are used to specify which constraints are set.
Definition: MCInstrDesc.h:82
bool isAsCheapAsAMove() const
Returns true if this instruction has the same cost (or less) than a move instruction.
Definition: MCInstrDesc.h:493
bool isPredicate() const
Set if this is one of the operands that made up of the predicate operand that controls an isPredicabl...
Definition: MCInstrDesc.h:92
bool hasExtraDefRegAllocReq() const
Returns true if this instruction def operands have special register allocation requirements that are ...
Definition: MCInstrDesc.h:511
bool isMoveImmediate() const
Return true if this instruction is a move immediate (including conditional moves) instruction...
Definition: MCInstrDesc.h:314
Analysis containing CSE Info
Definition: CSEInfo.cpp:20
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:158
unsigned short NumOperands
Definition: MCInstrDesc.h:166
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
Flag
These should be considered private to the implementation of the MCInstrDesc class.
Definition: MCInstrDesc.h:117
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
unsigned getSchedClass() const
Return the scheduling class for this instruction.
Definition: MCInstrDesc.h:576
bool isGenericType() const
Definition: MCInstrDesc.h:97
const MCPhysReg * getImplicitDefs() const
Return a list of registers that are potentially written by any instance of this machine instruction...
Definition: MCInstrDesc.h:545
bool hasExtraSrcRegAllocReq() const
Returns true if this instruction source operands have special register allocation requirements that a...
Definition: MCInstrDesc.h:501
unsigned const MachineRegisterInfo * MRI
bool isOptionalDef() const
Set if this operand is a optional def.
Definition: MCInstrDesc.h:95
bool hasOptionalDef() const
Set if this instruction has an optional definition, e.g.
Definition: MCInstrDesc.h:238
bool isBarrier() const
Returns true if the specified instruction stops control flow from executing the instruction immediate...
Definition: MCInstrDesc.h:262
bool isVariadic() const
Return true if this instruction can have a variable number of operands.
Definition: MCInstrDesc.h:234
bool isConditionalBranch() const
Return true if this is a branch which may fall through to the next instruction or may transfer contro...
Definition: MCInstrDesc.h:286
int64_t DeprecatedFeature
Definition: MCInstrDesc.h:178
OperandFlags
These are flags set on operands, but should be considered private, all access should go through the M...
Definition: MCInstrDesc.h:40
const MCPhysReg * ImplicitDefs
Definition: MCInstrDesc.h:173
bool isPredicable() const
Return true if this instruction has a predicate operand that controls execution.
Definition: MCInstrDesc.h:307
bool isIndirectBranch() const
Return true if this is an indirect branch, such as a branch through a register.
Definition: MCInstrDesc.h:280
bool hasPostISelHook() const
Return true if this instruction requires adjustment after instruction selection by calling a target h...
Definition: MCInstrDesc.h:472
unsigned char NumDefs
Definition: MCInstrDesc.h:167
bool isAdd() const
Return true if the instruction is an add instruction.
Definition: MCInstrDesc.h:248
bool isNotDuplicable() const
Return true if this instruction cannot be safely duplicated.
Definition: MCInstrDesc.h:325
int getOperandConstraint(unsigned OpNum, MCOI::OperandConstraint Constraint) const
Returns the value of the specific constraint if it is set.
Definition: MCInstrDesc.h:187
iterator_range< T > make_range(T x, T y)
Convenience function for iterating over sub-ranges.
bool isInsertSubregLike() const
Return true if this instruction behaves the same way as the generic INSERT_SUBREG instructions...
Definition: MCInstrDesc.h:377
bool hasDelaySlot() const
Returns true if the specified instruction has a delay slot which must be filled by the code generator...
Definition: MCInstrDesc.h:329
bool isBitcast() const
Return true if this instruction is a bitcast instruction.
Definition: MCInstrDesc.h:317
unsigned getNumDefs() const
Return the number of MachineOperands that are register definitions.
Definition: MCInstrDesc.h:225
unsigned short Opcode
Definition: MCInstrDesc.h:165
A range adaptor for a pair of iterators.
bool isConvergent() const
Return true if this instruction is convergent.
Definition: MCInstrDesc.h:384
bool mayStore() const
Return true if this instruction could possibly modify memory.
Definition: MCInstrDesc.h:404
bool isUnconditionalBranch() const
Return true if this is a branch which always transfers control flow to some other block...
Definition: MCInstrDesc.h:294
OperandType
Operands are tagged with one of the values of this enum.
Definition: MCInstrDesc.h:43
bool canFoldAsLoad() const
Return true for instructions that can be folded as memory operands in other instructions.
Definition: MCInstrDesc.h:338
int16_t RegClass
This specifies the register class enumeration of the operand if the operand is a register.
Definition: MCInstrDesc.h:72
const_opInfo_iterator opInfo_end() const
Definition: MCInstrDesc.h:215
bool isCall() const
Return true if the instruction is a call.
Definition: MCInstrDesc.h:257
Generic base class for all target subtargets.
uint32_t Size
Definition: Profile.cpp:46
bool variadicOpsAreDefs() const
Return true if variadic operands of this instruction are definitions.
Definition: MCInstrDesc.h:387
iterator_range< const_opInfo_iterator > operands() const
Definition: MCInstrDesc.h:217
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static bool isBranch(unsigned Opcode)
bool hasImplicitUseOfPhysReg(unsigned Reg) const
Return true if this instruction implicitly uses the specified physical register.
Definition: MCInstrDesc.h:559
bool isTerminator() const
Returns true if this instruction part of the terminator for a basic block.
Definition: MCInstrDesc.h:270
const MCOperandInfo * OpInfo
Definition: MCInstrDesc.h:174
unsigned getOpcode() const
Return the opcode number for this descriptor.
Definition: MCInstrDesc.h:203
unsigned getGenericTypeIndex() const
Definition: MCInstrDesc.h:102
IRTranslator LLVM IR MI
bool usesCustomInsertionHook() const
Return true if this instruction requires custom insertion support when the DAG scheduler is inserting...
Definition: MCInstrDesc.h:464
This holds information about one operand of a machine instruction, indicating the register class for ...
Definition: MCInstrDesc.h:66
uint64_t getFlags() const
Return flags of this instruction.
Definition: MCInstrDesc.h:228
unsigned short SchedClass
Definition: MCInstrDesc.h:169
const MCPhysReg * ImplicitUses
Definition: MCInstrDesc.h:172
unsigned getSize() const
Return the number of bytes in the encoding of this instruction, or zero if the encoding size cannot b...
Definition: MCInstrDesc.h:580