LLVM  7.0.0svn
MachineSink.cpp
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1 //===- MachineSink.cpp - Sinking for machine instructions -----------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This pass moves instructions into successor blocks when possible, so that
11 // they aren't executed on paths where their results aren't needed.
12 //
13 // This pass is not intended to be a replacement or a complete alternative
14 // for an LLVM-IR-level sinking pass. It is only designed to sink simple
15 // constructs that are not exposed before lowering and instruction selection.
16 //
17 //===----------------------------------------------------------------------===//
18 
19 #include "llvm/ADT/SetVector.h"
20 #include "llvm/ADT/SmallSet.h"
21 #include "llvm/ADT/SmallVector.h"
23 #include "llvm/ADT/Statistic.h"
39 #include "llvm/IR/BasicBlock.h"
40 #include "llvm/IR/LLVMContext.h"
42 #include "llvm/Pass.h"
45 #include "llvm/Support/Debug.h"
47 #include <algorithm>
48 #include <cassert>
49 #include <cstdint>
50 #include <map>
51 #include <utility>
52 #include <vector>
53 
54 using namespace llvm;
55 
56 #define DEBUG_TYPE "machine-sink"
57 
58 static cl::opt<bool>
59 SplitEdges("machine-sink-split",
60  cl::desc("Split critical edges during machine sinking"),
61  cl::init(true), cl::Hidden);
62 
63 static cl::opt<bool>
64 UseBlockFreqInfo("machine-sink-bfi",
65  cl::desc("Use block frequency info to find successors to sink"),
66  cl::init(true), cl::Hidden);
67 
69  "machine-sink-split-probability-threshold",
70  cl::desc(
71  "Percentage threshold for splitting single-instruction critical edge. "
72  "If the branch threshold is higher than this threshold, we allow "
73  "speculative execution of up to 1 instruction to avoid branching to "
74  "splitted critical edge"),
75  cl::init(40), cl::Hidden);
76 
77 STATISTIC(NumSunk, "Number of machine instructions sunk");
78 STATISTIC(NumSplit, "Number of critical edges split");
79 STATISTIC(NumCoalesces, "Number of copies coalesced");
80 STATISTIC(NumPostRACopySink, "Number of copies sunk after RA");
81 
82 namespace {
83 
84  class MachineSinking : public MachineFunctionPass {
85  const TargetInstrInfo *TII;
86  const TargetRegisterInfo *TRI;
87  MachineRegisterInfo *MRI; // Machine register information
88  MachineDominatorTree *DT; // Machine dominator tree
89  MachinePostDominatorTree *PDT; // Machine post dominator tree
90  MachineLoopInfo *LI;
91  const MachineBlockFrequencyInfo *MBFI;
92  const MachineBranchProbabilityInfo *MBPI;
93  AliasAnalysis *AA;
94 
95  // Remember which edges have been considered for breaking.
97  CEBCandidates;
98  // Remember which edges we are about to split.
99  // This is different from CEBCandidates since those edges
100  // will be split.
102 
103  SparseBitVector<> RegsToClearKillFlags;
104 
105  using AllSuccsCache =
106  std::map<MachineBasicBlock *, SmallVector<MachineBasicBlock *, 4>>;
107 
108  public:
109  static char ID; // Pass identification
110 
111  MachineSinking() : MachineFunctionPass(ID) {
113  }
114 
115  bool runOnMachineFunction(MachineFunction &MF) override;
116 
117  void getAnalysisUsage(AnalysisUsage &AU) const override {
118  AU.setPreservesCFG();
128  if (UseBlockFreqInfo)
130  }
131 
132  void releaseMemory() override {
133  CEBCandidates.clear();
134  }
135 
136  private:
137  bool ProcessBlock(MachineBasicBlock &MBB);
138  bool isWorthBreakingCriticalEdge(MachineInstr &MI,
139  MachineBasicBlock *From,
140  MachineBasicBlock *To);
141 
142  /// Postpone the splitting of the given critical
143  /// edge (\p From, \p To).
144  ///
145  /// We do not split the edges on the fly. Indeed, this invalidates
146  /// the dominance information and thus triggers a lot of updates
147  /// of that information underneath.
148  /// Instead, we postpone all the splits after each iteration of
149  /// the main loop. That way, the information is at least valid
150  /// for the lifetime of an iteration.
151  ///
152  /// \return True if the edge is marked as toSplit, false otherwise.
153  /// False can be returned if, for instance, this is not profitable.
154  bool PostponeSplitCriticalEdge(MachineInstr &MI,
155  MachineBasicBlock *From,
156  MachineBasicBlock *To,
157  bool BreakPHIEdge);
158  bool SinkInstruction(MachineInstr &MI, bool &SawStore,
159 
160  AllSuccsCache &AllSuccessors);
161  bool AllUsesDominatedByBlock(unsigned Reg, MachineBasicBlock *MBB,
162  MachineBasicBlock *DefMBB,
163  bool &BreakPHIEdge, bool &LocalUse) const;
164  MachineBasicBlock *FindSuccToSinkTo(MachineInstr &MI, MachineBasicBlock *MBB,
165  bool &BreakPHIEdge, AllSuccsCache &AllSuccessors);
166  bool isProfitableToSinkTo(unsigned Reg, MachineInstr &MI,
167  MachineBasicBlock *MBB,
168  MachineBasicBlock *SuccToSinkTo,
169  AllSuccsCache &AllSuccessors);
170 
171  bool PerformTrivialForwardCoalescing(MachineInstr &MI,
172  MachineBasicBlock *MBB);
173 
175  GetAllSortedSuccessors(MachineInstr &MI, MachineBasicBlock *MBB,
176  AllSuccsCache &AllSuccessors) const;
177  };
178 
179 } // end anonymous namespace
180 
181 char MachineSinking::ID = 0;
182 
184 
185 INITIALIZE_PASS_BEGIN(MachineSinking, DEBUG_TYPE,
186  "Machine code sinking", false, false)
192  "Machine code sinking", false, false)
193 
194 bool MachineSinking::PerformTrivialForwardCoalescing(MachineInstr &MI,
195  MachineBasicBlock *MBB) {
196  if (!MI.isCopy())
197  return false;
198 
199  unsigned SrcReg = MI.getOperand(1).getReg();
200  unsigned DstReg = MI.getOperand(0).getReg();
203  !MRI->hasOneNonDBGUse(SrcReg))
204  return false;
205 
206  const TargetRegisterClass *SRC = MRI->getRegClass(SrcReg);
207  const TargetRegisterClass *DRC = MRI->getRegClass(DstReg);
208  if (SRC != DRC)
209  return false;
210 
211  MachineInstr *DefMI = MRI->getVRegDef(SrcReg);
212  if (DefMI->isCopyLike())
213  return false;
214  LLVM_DEBUG(dbgs() << "Coalescing: " << *DefMI);
215  LLVM_DEBUG(dbgs() << "*** to: " << MI);
216  MRI->replaceRegWith(DstReg, SrcReg);
217  MI.eraseFromParent();
218 
219  // Conservatively, clear any kill flags, since it's possible that they are no
220  // longer correct.
221  MRI->clearKillFlags(SrcReg);
222 
223  ++NumCoalesces;
224  return true;
225 }
226 
227 /// AllUsesDominatedByBlock - Return true if all uses of the specified register
228 /// occur in blocks dominated by the specified block. If any use is in the
229 /// definition block, then return false since it is never legal to move def
230 /// after uses.
231 bool
233  MachineBasicBlock *MBB,
234  MachineBasicBlock *DefMBB,
235  bool &BreakPHIEdge,
236  bool &LocalUse) const {
238  "Only makes sense for vregs");
239 
240  // Ignore debug uses because debug info doesn't affect the code.
241  if (MRI->use_nodbg_empty(Reg))
242  return true;
243 
244  // BreakPHIEdge is true if all the uses are in the successor MBB being sunken
245  // into and they are all PHI nodes. In this case, machine-sink must break
246  // the critical edge first. e.g.
247  //
248  // %bb.1: derived from LLVM BB %bb4.preheader
249  // Predecessors according to CFG: %bb.0
250  // ...
251  // %reg16385 = DEC64_32r %reg16437, implicit-def dead %eflags
252  // ...
253  // JE_4 <%bb.37>, implicit %eflags
254  // Successors according to CFG: %bb.37 %bb.2
255  //
256  // %bb.2: derived from LLVM BB %bb.nph
257  // Predecessors according to CFG: %bb.0 %bb.1
258  // %reg16386 = PHI %reg16434, %bb.0, %reg16385, %bb.1
259  BreakPHIEdge = true;
260  for (MachineOperand &MO : MRI->use_nodbg_operands(Reg)) {
261  MachineInstr *UseInst = MO.getParent();
262  unsigned OpNo = &MO - &UseInst->getOperand(0);
263  MachineBasicBlock *UseBlock = UseInst->getParent();
264  if (!(UseBlock == MBB && UseInst->isPHI() &&
265  UseInst->getOperand(OpNo+1).getMBB() == DefMBB)) {
266  BreakPHIEdge = false;
267  break;
268  }
269  }
270  if (BreakPHIEdge)
271  return true;
272 
273  for (MachineOperand &MO : MRI->use_nodbg_operands(Reg)) {
274  // Determine the block of the use.
275  MachineInstr *UseInst = MO.getParent();
276  unsigned OpNo = &MO - &UseInst->getOperand(0);
277  MachineBasicBlock *UseBlock = UseInst->getParent();
278  if (UseInst->isPHI()) {
279  // PHI nodes use the operand in the predecessor block, not the block with
280  // the PHI.
281  UseBlock = UseInst->getOperand(OpNo+1).getMBB();
282  } else if (UseBlock == DefMBB) {
283  LocalUse = true;
284  return false;
285  }
286 
287  // Check that it dominates.
288  if (!DT->dominates(MBB, UseBlock))
289  return false;
290  }
291 
292  return true;
293 }
294 
295 bool MachineSinking::runOnMachineFunction(MachineFunction &MF) {
296  if (skipFunction(MF.getFunction()))
297  return false;
298 
299  LLVM_DEBUG(dbgs() << "******** Machine Sinking ********\n");
300 
301  TII = MF.getSubtarget().getInstrInfo();
302  TRI = MF.getSubtarget().getRegisterInfo();
303  MRI = &MF.getRegInfo();
304  DT = &getAnalysis<MachineDominatorTree>();
305  PDT = &getAnalysis<MachinePostDominatorTree>();
306  LI = &getAnalysis<MachineLoopInfo>();
307  MBFI = UseBlockFreqInfo ? &getAnalysis<MachineBlockFrequencyInfo>() : nullptr;
308  MBPI = &getAnalysis<MachineBranchProbabilityInfo>();
309  AA = &getAnalysis<AAResultsWrapperPass>().getAAResults();
310 
311  bool EverMadeChange = false;
312 
313  while (true) {
314  bool MadeChange = false;
315 
316  // Process all basic blocks.
317  CEBCandidates.clear();
318  ToSplit.clear();
319  for (auto &MBB: MF)
320  MadeChange |= ProcessBlock(MBB);
321 
322  // If we have anything we marked as toSplit, split it now.
323  for (auto &Pair : ToSplit) {
324  auto NewSucc = Pair.first->SplitCriticalEdge(Pair.second, *this);
325  if (NewSucc != nullptr) {
326  LLVM_DEBUG(dbgs() << " *** Splitting critical edge: "
327  << printMBBReference(*Pair.first) << " -- "
328  << printMBBReference(*NewSucc) << " -- "
329  << printMBBReference(*Pair.second) << '\n');
330  MadeChange = true;
331  ++NumSplit;
332  } else
333  LLVM_DEBUG(dbgs() << " *** Not legal to break critical edge\n");
334  }
335  // If this iteration over the code changed anything, keep iterating.
336  if (!MadeChange) break;
337  EverMadeChange = true;
338  }
339 
340  // Now clear any kill flags for recorded registers.
341  for (auto I : RegsToClearKillFlags)
342  MRI->clearKillFlags(I);
343  RegsToClearKillFlags.clear();
344 
345  return EverMadeChange;
346 }
347 
349  // Can't sink anything out of a block that has less than two successors.
350  if (MBB.succ_size() <= 1 || MBB.empty()) return false;
351 
352  // Don't bother sinking code out of unreachable blocks. In addition to being
353  // unprofitable, it can also lead to infinite looping, because in an
354  // unreachable loop there may be nowhere to stop.
355  if (!DT->isReachableFromEntry(&MBB)) return false;
356 
357  bool MadeChange = false;
358 
359  // Cache all successors, sorted by frequency info and loop depth.
360  AllSuccsCache AllSuccessors;
361 
362  // Walk the basic block bottom-up. Remember if we saw a store.
364  --I;
365  bool ProcessedBegin, SawStore = false;
366  do {
367  MachineInstr &MI = *I; // The instruction to sink.
368 
369  // Predecrement I (if it's not begin) so that it isn't invalidated by
370  // sinking.
371  ProcessedBegin = I == MBB.begin();
372  if (!ProcessedBegin)
373  --I;
374 
375  if (MI.isDebugInstr())
376  continue;
377 
378  bool Joined = PerformTrivialForwardCoalescing(MI, &MBB);
379  if (Joined) {
380  MadeChange = true;
381  continue;
382  }
383 
384  if (SinkInstruction(MI, SawStore, AllSuccessors)) {
385  ++NumSunk;
386  MadeChange = true;
387  }
388 
389  // If we just processed the first instruction in the block, we're done.
390  } while (!ProcessedBegin);
391 
392  return MadeChange;
393 }
394 
395 bool MachineSinking::isWorthBreakingCriticalEdge(MachineInstr &MI,
396  MachineBasicBlock *From,
397  MachineBasicBlock *To) {
398  // FIXME: Need much better heuristics.
399 
400  // If the pass has already considered breaking this edge (during this pass
401  // through the function), then let's go ahead and break it. This means
402  // sinking multiple "cheap" instructions into the same block.
403  if (!CEBCandidates.insert(std::make_pair(From, To)).second)
404  return true;
405 
406  if (!MI.isCopy() && !TII->isAsCheapAsAMove(MI))
407  return true;
408 
409  if (From->isSuccessor(To) && MBPI->getEdgeProbability(From, To) <=
411  return true;
412 
413  // MI is cheap, we probably don't want to break the critical edge for it.
414  // However, if this would allow some definitions of its source operands
415  // to be sunk then it's probably worth it.
416  for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
417  const MachineOperand &MO = MI.getOperand(i);
418  if (!MO.isReg() || !MO.isUse())
419  continue;
420  unsigned Reg = MO.getReg();
421  if (Reg == 0)
422  continue;
423 
424  // We don't move live definitions of physical registers,
425  // so sinking their uses won't enable any opportunities.
427  continue;
428 
429  // If this instruction is the only user of a virtual register,
430  // check if breaking the edge will enable sinking
431  // both this instruction and the defining instruction.
432  if (MRI->hasOneNonDBGUse(Reg)) {
433  // If the definition resides in same MBB,
434  // claim it's likely we can sink these together.
435  // If definition resides elsewhere, we aren't
436  // blocking it from being sunk so don't break the edge.
437  MachineInstr *DefMI = MRI->getVRegDef(Reg);
438  if (DefMI->getParent() == MI.getParent())
439  return true;
440  }
441  }
442 
443  return false;
444 }
445 
446 bool MachineSinking::PostponeSplitCriticalEdge(MachineInstr &MI,
447  MachineBasicBlock *FromBB,
448  MachineBasicBlock *ToBB,
449  bool BreakPHIEdge) {
450  if (!isWorthBreakingCriticalEdge(MI, FromBB, ToBB))
451  return false;
452 
453  // Avoid breaking back edge. From == To means backedge for single BB loop.
454  if (!SplitEdges || FromBB == ToBB)
455  return false;
456 
457  // Check for backedges of more "complex" loops.
458  if (LI->getLoopFor(FromBB) == LI->getLoopFor(ToBB) &&
459  LI->isLoopHeader(ToBB))
460  return false;
461 
462  // It's not always legal to break critical edges and sink the computation
463  // to the edge.
464  //
465  // %bb.1:
466  // v1024
467  // Beq %bb.3
468  // <fallthrough>
469  // %bb.2:
470  // ... no uses of v1024
471  // <fallthrough>
472  // %bb.3:
473  // ...
474  // = v1024
475  //
476  // If %bb.1 -> %bb.3 edge is broken and computation of v1024 is inserted:
477  //
478  // %bb.1:
479  // ...
480  // Bne %bb.2
481  // %bb.4:
482  // v1024 =
483  // B %bb.3
484  // %bb.2:
485  // ... no uses of v1024
486  // <fallthrough>
487  // %bb.3:
488  // ...
489  // = v1024
490  //
491  // This is incorrect since v1024 is not computed along the %bb.1->%bb.2->%bb.3
492  // flow. We need to ensure the new basic block where the computation is
493  // sunk to dominates all the uses.
494  // It's only legal to break critical edge and sink the computation to the
495  // new block if all the predecessors of "To", except for "From", are
496  // not dominated by "From". Given SSA property, this means these
497  // predecessors are dominated by "To".
498  //
499  // There is no need to do this check if all the uses are PHI nodes. PHI
500  // sources are only defined on the specific predecessor edges.
501  if (!BreakPHIEdge) {
503  E = ToBB->pred_end(); PI != E; ++PI) {
504  if (*PI == FromBB)
505  continue;
506  if (!DT->dominates(ToBB, *PI))
507  return false;
508  }
509  }
510 
511  ToSplit.insert(std::make_pair(FromBB, ToBB));
512 
513  return true;
514 }
515 
516 /// collectDebgValues - Scan instructions following MI and collect any
517 /// matching DBG_VALUEs.
519  SmallVectorImpl<MachineInstr *> &DbgValues) {
520  DbgValues.clear();
521  if (!MI.getOperand(0).isReg())
522  return;
523 
524  MachineBasicBlock::iterator DI = MI; ++DI;
525  for (MachineBasicBlock::iterator DE = MI.getParent()->end();
526  DI != DE; ++DI) {
527  if (!DI->isDebugValue())
528  return;
529  if (DI->getOperand(0).isReg() &&
530  DI->getOperand(0).getReg() == MI.getOperand(0).getReg())
531  DbgValues.push_back(&*DI);
532  }
533 }
534 
535 /// isProfitableToSinkTo - Return true if it is profitable to sink MI.
536 bool MachineSinking::isProfitableToSinkTo(unsigned Reg, MachineInstr &MI,
537  MachineBasicBlock *MBB,
538  MachineBasicBlock *SuccToSinkTo,
539  AllSuccsCache &AllSuccessors) {
540  assert (SuccToSinkTo && "Invalid SinkTo Candidate BB");
541 
542  if (MBB == SuccToSinkTo)
543  return false;
544 
545  // It is profitable if SuccToSinkTo does not post dominate current block.
546  if (!PDT->dominates(SuccToSinkTo, MBB))
547  return true;
548 
549  // It is profitable to sink an instruction from a deeper loop to a shallower
550  // loop, even if the latter post-dominates the former (PR21115).
551  if (LI->getLoopDepth(MBB) > LI->getLoopDepth(SuccToSinkTo))
552  return true;
553 
554  // Check if only use in post dominated block is PHI instruction.
555  bool NonPHIUse = false;
556  for (MachineInstr &UseInst : MRI->use_nodbg_instructions(Reg)) {
557  MachineBasicBlock *UseBlock = UseInst.getParent();
558  if (UseBlock == SuccToSinkTo && !UseInst.isPHI())
559  NonPHIUse = true;
560  }
561  if (!NonPHIUse)
562  return true;
563 
564  // If SuccToSinkTo post dominates then also it may be profitable if MI
565  // can further profitably sinked into another block in next round.
566  bool BreakPHIEdge = false;
567  // FIXME - If finding successor is compile time expensive then cache results.
568  if (MachineBasicBlock *MBB2 =
569  FindSuccToSinkTo(MI, SuccToSinkTo, BreakPHIEdge, AllSuccessors))
570  return isProfitableToSinkTo(Reg, MI, SuccToSinkTo, MBB2, AllSuccessors);
571 
572  // If SuccToSinkTo is final destination and it is a post dominator of current
573  // block then it is not profitable to sink MI into SuccToSinkTo block.
574  return false;
575 }
576 
577 /// Get the sorted sequence of successors for this MachineBasicBlock, possibly
578 /// computing it if it was not already cached.
580 MachineSinking::GetAllSortedSuccessors(MachineInstr &MI, MachineBasicBlock *MBB,
581  AllSuccsCache &AllSuccessors) const {
582  // Do we have the sorted successors in cache ?
583  auto Succs = AllSuccessors.find(MBB);
584  if (Succs != AllSuccessors.end())
585  return Succs->second;
586 
588  MBB->succ_end());
589 
590  // Handle cases where sinking can happen but where the sink point isn't a
591  // successor. For example:
592  //
593  // x = computation
594  // if () {} else {}
595  // use x
596  //
597  const std::vector<MachineDomTreeNode *> &Children =
598  DT->getNode(MBB)->getChildren();
599  for (const auto &DTChild : Children)
600  // DomTree children of MBB that have MBB as immediate dominator are added.
601  if (DTChild->getIDom()->getBlock() == MI.getParent() &&
602  // Skip MBBs already added to the AllSuccs vector above.
603  !MBB->isSuccessor(DTChild->getBlock()))
604  AllSuccs.push_back(DTChild->getBlock());
605 
606  // Sort Successors according to their loop depth or block frequency info.
607  std::stable_sort(
608  AllSuccs.begin(), AllSuccs.end(),
609  [this](const MachineBasicBlock *L, const MachineBasicBlock *R) {
610  uint64_t LHSFreq = MBFI ? MBFI->getBlockFreq(L).getFrequency() : 0;
611  uint64_t RHSFreq = MBFI ? MBFI->getBlockFreq(R).getFrequency() : 0;
612  bool HasBlockFreq = LHSFreq != 0 && RHSFreq != 0;
613  return HasBlockFreq ? LHSFreq < RHSFreq
614  : LI->getLoopDepth(L) < LI->getLoopDepth(R);
615  });
616 
617  auto it = AllSuccessors.insert(std::make_pair(MBB, AllSuccs));
618 
619  return it.first->second;
620 }
621 
622 /// FindSuccToSinkTo - Find a successor to sink this instruction to.
624 MachineSinking::FindSuccToSinkTo(MachineInstr &MI, MachineBasicBlock *MBB,
625  bool &BreakPHIEdge,
626  AllSuccsCache &AllSuccessors) {
627  assert (MBB && "Invalid MachineBasicBlock!");
628 
629  // Loop over all the operands of the specified instruction. If there is
630  // anything we can't handle, bail out.
631 
632  // SuccToSinkTo - This is the successor to sink this instruction to, once we
633  // decide.
634  MachineBasicBlock *SuccToSinkTo = nullptr;
635  for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
636  const MachineOperand &MO = MI.getOperand(i);
637  if (!MO.isReg()) continue; // Ignore non-register operands.
638 
639  unsigned Reg = MO.getReg();
640  if (Reg == 0) continue;
641 
643  if (MO.isUse()) {
644  // If the physreg has no defs anywhere, it's just an ambient register
645  // and we can freely move its uses. Alternatively, if it's allocatable,
646  // it could get allocated to something with a def during allocation.
647  if (!MRI->isConstantPhysReg(Reg))
648  return nullptr;
649  } else if (!MO.isDead()) {
650  // A def that isn't dead. We can't move it.
651  return nullptr;
652  }
653  } else {
654  // Virtual register uses are always safe to sink.
655  if (MO.isUse()) continue;
656 
657  // If it's not safe to move defs of the register class, then abort.
658  if (!TII->isSafeToMoveRegClassDefs(MRI->getRegClass(Reg)))
659  return nullptr;
660 
661  // Virtual register defs can only be sunk if all their uses are in blocks
662  // dominated by one of the successors.
663  if (SuccToSinkTo) {
664  // If a previous operand picked a block to sink to, then this operand
665  // must be sinkable to the same block.
666  bool LocalUse = false;
667  if (!AllUsesDominatedByBlock(Reg, SuccToSinkTo, MBB,
668  BreakPHIEdge, LocalUse))
669  return nullptr;
670 
671  continue;
672  }
673 
674  // Otherwise, we should look at all the successors and decide which one
675  // we should sink to. If we have reliable block frequency information
676  // (frequency != 0) available, give successors with smaller frequencies
677  // higher priority, otherwise prioritize smaller loop depths.
678  for (MachineBasicBlock *SuccBlock :
679  GetAllSortedSuccessors(MI, MBB, AllSuccessors)) {
680  bool LocalUse = false;
681  if (AllUsesDominatedByBlock(Reg, SuccBlock, MBB,
682  BreakPHIEdge, LocalUse)) {
683  SuccToSinkTo = SuccBlock;
684  break;
685  }
686  if (LocalUse)
687  // Def is used locally, it's never safe to move this def.
688  return nullptr;
689  }
690 
691  // If we couldn't find a block to sink to, ignore this instruction.
692  if (!SuccToSinkTo)
693  return nullptr;
694  if (!isProfitableToSinkTo(Reg, MI, MBB, SuccToSinkTo, AllSuccessors))
695  return nullptr;
696  }
697  }
698 
699  // It is not possible to sink an instruction into its own block. This can
700  // happen with loops.
701  if (MBB == SuccToSinkTo)
702  return nullptr;
703 
704  // It's not safe to sink instructions to EH landing pad. Control flow into
705  // landing pad is implicitly defined.
706  if (SuccToSinkTo && SuccToSinkTo->isEHPad())
707  return nullptr;
708 
709  return SuccToSinkTo;
710 }
711 
712 /// Return true if MI is likely to be usable as a memory operation by the
713 /// implicit null check optimization.
714 ///
715 /// This is a "best effort" heuristic, and should not be relied upon for
716 /// correctness. This returning true does not guarantee that the implicit null
717 /// check optimization is legal over MI, and this returning false does not
718 /// guarantee MI cannot possibly be used to do a null check.
720  const TargetInstrInfo *TII,
721  const TargetRegisterInfo *TRI) {
722  using MachineBranchPredicate = TargetInstrInfo::MachineBranchPredicate;
723 
724  auto *MBB = MI.getParent();
725  if (MBB->pred_size() != 1)
726  return false;
727 
728  auto *PredMBB = *MBB->pred_begin();
729  auto *PredBB = PredMBB->getBasicBlock();
730 
731  // Frontends that don't use implicit null checks have no reason to emit
732  // branches with make.implicit metadata, and this function should always
733  // return false for them.
734  if (!PredBB ||
735  !PredBB->getTerminator()->getMetadata(LLVMContext::MD_make_implicit))
736  return false;
737 
738  unsigned BaseReg;
739  int64_t Offset;
740  if (!TII->getMemOpBaseRegImmOfs(MI, BaseReg, Offset, TRI))
741  return false;
742 
743  if (!(MI.mayLoad() && !MI.isPredicable()))
744  return false;
745 
746  MachineBranchPredicate MBP;
747  if (TII->analyzeBranchPredicate(*PredMBB, MBP, false))
748  return false;
749 
750  return MBP.LHS.isReg() && MBP.RHS.isImm() && MBP.RHS.getImm() == 0 &&
751  (MBP.Predicate == MachineBranchPredicate::PRED_NE ||
752  MBP.Predicate == MachineBranchPredicate::PRED_EQ) &&
753  MBP.LHS.getReg() == BaseReg;
754 }
755 
756 /// SinkInstruction - Determine whether it is safe to sink the specified machine
757 /// instruction out of its current block into a successor.
758 bool MachineSinking::SinkInstruction(MachineInstr &MI, bool &SawStore,
759  AllSuccsCache &AllSuccessors) {
760  // Don't sink instructions that the target prefers not to sink.
761  if (!TII->shouldSink(MI))
762  return false;
763 
764  // Check if it's safe to move the instruction.
765  if (!MI.isSafeToMove(AA, SawStore))
766  return false;
767 
768  // Convergent operations may not be made control-dependent on additional
769  // values.
770  if (MI.isConvergent())
771  return false;
772 
773  // Don't break implicit null checks. This is a performance heuristic, and not
774  // required for correctness.
775  if (SinkingPreventsImplicitNullCheck(MI, TII, TRI))
776  return false;
777 
778  // FIXME: This should include support for sinking instructions within the
779  // block they are currently in to shorten the live ranges. We often get
780  // instructions sunk into the top of a large block, but it would be better to
781  // also sink them down before their first use in the block. This xform has to
782  // be careful not to *increase* register pressure though, e.g. sinking
783  // "x = y + z" down if it kills y and z would increase the live ranges of y
784  // and z and only shrink the live range of x.
785 
786  bool BreakPHIEdge = false;
787  MachineBasicBlock *ParentBlock = MI.getParent();
788  MachineBasicBlock *SuccToSinkTo =
789  FindSuccToSinkTo(MI, ParentBlock, BreakPHIEdge, AllSuccessors);
790 
791  // If there are no outputs, it must have side-effects.
792  if (!SuccToSinkTo)
793  return false;
794 
795  // If the instruction to move defines a dead physical register which is live
796  // when leaving the basic block, don't move it because it could turn into a
797  // "zombie" define of that preg. E.g., EFLAGS. (<rdar://problem/8030636>)
798  for (unsigned I = 0, E = MI.getNumOperands(); I != E; ++I) {
799  const MachineOperand &MO = MI.getOperand(I);
800  if (!MO.isReg()) continue;
801  unsigned Reg = MO.getReg();
802  if (Reg == 0 || !TargetRegisterInfo::isPhysicalRegister(Reg)) continue;
803  if (SuccToSinkTo->isLiveIn(Reg))
804  return false;
805  }
806 
807  LLVM_DEBUG(dbgs() << "Sink instr " << MI << "\tinto block " << *SuccToSinkTo);
808 
809  // If the block has multiple predecessors, this is a critical edge.
810  // Decide if we can sink along it or need to break the edge.
811  if (SuccToSinkTo->pred_size() > 1) {
812  // We cannot sink a load across a critical edge - there may be stores in
813  // other code paths.
814  bool TryBreak = false;
815  bool store = true;
816  if (!MI.isSafeToMove(AA, store)) {
817  LLVM_DEBUG(dbgs() << " *** NOTE: Won't sink load along critical edge.\n");
818  TryBreak = true;
819  }
820 
821  // We don't want to sink across a critical edge if we don't dominate the
822  // successor. We could be introducing calculations to new code paths.
823  if (!TryBreak && !DT->dominates(ParentBlock, SuccToSinkTo)) {
824  LLVM_DEBUG(dbgs() << " *** NOTE: Critical edge found\n");
825  TryBreak = true;
826  }
827 
828  // Don't sink instructions into a loop.
829  if (!TryBreak && LI->isLoopHeader(SuccToSinkTo)) {
830  LLVM_DEBUG(dbgs() << " *** NOTE: Loop header found\n");
831  TryBreak = true;
832  }
833 
834  // Otherwise we are OK with sinking along a critical edge.
835  if (!TryBreak)
836  LLVM_DEBUG(dbgs() << "Sinking along critical edge.\n");
837  else {
838  // Mark this edge as to be split.
839  // If the edge can actually be split, the next iteration of the main loop
840  // will sink MI in the newly created block.
841  bool Status =
842  PostponeSplitCriticalEdge(MI, ParentBlock, SuccToSinkTo, BreakPHIEdge);
843  if (!Status)
844  LLVM_DEBUG(dbgs() << " *** PUNTING: Not legal or profitable to "
845  "break critical edge\n");
846  // The instruction will not be sunk this time.
847  return false;
848  }
849  }
850 
851  if (BreakPHIEdge) {
852  // BreakPHIEdge is true if all the uses are in the successor MBB being
853  // sunken into and they are all PHI nodes. In this case, machine-sink must
854  // break the critical edge first.
855  bool Status = PostponeSplitCriticalEdge(MI, ParentBlock,
856  SuccToSinkTo, BreakPHIEdge);
857  if (!Status)
858  LLVM_DEBUG(dbgs() << " *** PUNTING: Not legal or profitable to "
859  "break critical edge\n");
860  // The instruction will not be sunk this time.
861  return false;
862  }
863 
864  // Determine where to insert into. Skip phi nodes.
865  MachineBasicBlock::iterator InsertPos = SuccToSinkTo->begin();
866  while (InsertPos != SuccToSinkTo->end() && InsertPos->isPHI())
867  ++InsertPos;
868 
869  // collect matching debug values.
870  SmallVector<MachineInstr *, 2> DbgValuesToSink;
871  collectDebugValues(MI, DbgValuesToSink);
872 
873  // Merge or erase debug location to ensure consistent stepping in profilers
874  // and debuggers.
875  if (!SuccToSinkTo->empty() && InsertPos != SuccToSinkTo->end())
877  InsertPos->getDebugLoc()));
878  else
879  MI.setDebugLoc(DebugLoc());
880 
881 
882  // Move the instruction.
883  SuccToSinkTo->splice(InsertPos, ParentBlock, MI,
885 
886  // Move previously adjacent debug value instructions to the insert position.
887  for (SmallVectorImpl<MachineInstr *>::iterator DBI = DbgValuesToSink.begin(),
888  DBE = DbgValuesToSink.end(); DBI != DBE; ++DBI) {
889  MachineInstr *DbgMI = *DBI;
890  SuccToSinkTo->splice(InsertPos, ParentBlock, DbgMI,
891  ++MachineBasicBlock::iterator(DbgMI));
892  }
893 
894  // Conservatively, clear any kill flags, since it's possible that they are no
895  // longer correct.
896  // Note that we have to clear the kill flags for any register this instruction
897  // uses as we may sink over another instruction which currently kills the
898  // used registers.
899  for (MachineOperand &MO : MI.operands()) {
900  if (MO.isReg() && MO.isUse())
901  RegsToClearKillFlags.set(MO.getReg()); // Remember to clear kill flags.
902  }
903 
904  return true;
905 }
906 
907 //===----------------------------------------------------------------------===//
908 // This pass is not intended to be a replacement or a complete alternative
909 // for the pre-ra machine sink pass. It is only designed to sink COPY
910 // instructions which should be handled after RA.
911 //
912 // This pass sinks COPY instructions into a successor block, if the COPY is not
913 // used in the current block and the COPY is live-in to a single successor
914 // (i.e., doesn't require the COPY to be duplicated). This avoids executing the
915 // copy on paths where their results aren't needed. This also exposes
916 // additional opportunites for dead copy elimination and shrink wrapping.
917 //
918 // These copies were either not handled by or are inserted after the MachineSink
919 // pass. As an example of the former case, the MachineSink pass cannot sink
920 // COPY instructions with allocatable source registers; for AArch64 these type
921 // of copy instructions are frequently used to move function parameters (PhyReg)
922 // into virtual registers in the entry block.
923 //
924 // For the machine IR below, this pass will sink %w19 in the entry into its
925 // successor (%bb.1) because %w19 is only live-in in %bb.1.
926 // %bb.0:
927 // %wzr = SUBSWri %w1, 1
928 // %w19 = COPY %w0
929 // Bcc 11, %bb.2
930 // %bb.1:
931 // Live Ins: %w19
932 // BL @fun
933 // %w0 = ADDWrr %w0, %w19
934 // RET %w0
935 // %bb.2:
936 // %w0 = COPY %wzr
937 // RET %w0
938 // As we sink %w19 (CSR in AArch64) into %bb.1, the shrink-wrapping pass will be
939 // able to see %bb.0 as a candidate.
940 //===----------------------------------------------------------------------===//
941 namespace {
942 
943 class PostRAMachineSinking : public MachineFunctionPass {
944 public:
945  bool runOnMachineFunction(MachineFunction &MF) override;
946 
947  static char ID;
948  PostRAMachineSinking() : MachineFunctionPass(ID) {}
949  StringRef getPassName() const override { return "PostRA Machine Sink"; }
950 
951  void getAnalysisUsage(AnalysisUsage &AU) const override {
952  AU.setPreservesCFG();
954  }
955 
956  MachineFunctionProperties getRequiredProperties() const override {
959  }
960 
961 private:
962  /// Track which register units have been modified and used.
963  LiveRegUnits ModifiedRegUnits, UsedRegUnits;
964 
965  /// Sink Copy instructions unused in the same block close to their uses in
966  /// successors.
967  bool tryToSinkCopy(MachineBasicBlock &BB, MachineFunction &MF,
968  const TargetRegisterInfo *TRI, const TargetInstrInfo *TII);
969 };
970 } // namespace
971 
972 char PostRAMachineSinking::ID = 0;
974 
975 INITIALIZE_PASS(PostRAMachineSinking, "postra-machine-sink",
976  "PostRA Machine Sink", false, false)
977 
978 static bool aliasWithRegsInLiveIn(MachineBasicBlock &MBB, unsigned Reg,
980  LiveRegUnits LiveInRegUnits(*TRI);
981  LiveInRegUnits.addLiveIns(MBB);
982  return !LiveInRegUnits.available(Reg);
983 }
984 
985 static MachineBasicBlock *
987  const SmallPtrSetImpl<MachineBasicBlock *> &SinkableBBs,
988  unsigned Reg, const TargetRegisterInfo *TRI) {
989  // Try to find a single sinkable successor in which Reg is live-in.
990  MachineBasicBlock *BB = nullptr;
991  for (auto *SI : SinkableBBs) {
992  if (aliasWithRegsInLiveIn(*SI, Reg, TRI)) {
993  // If BB is set here, Reg is live-in to at least two sinkable successors,
994  // so quit.
995  if (BB)
996  return nullptr;
997  BB = SI;
998  }
999  }
1000  // Reg is not live-in to any sinkable successors.
1001  if (!BB)
1002  return nullptr;
1003 
1004  // Check if any register aliased with Reg is live-in in other successors.
1005  for (auto *SI : CurBB.successors()) {
1006  if (!SinkableBBs.count(SI) && aliasWithRegsInLiveIn(*SI, Reg, TRI))
1007  return nullptr;
1008  }
1009  return BB;
1010 }
1011 
1012 static MachineBasicBlock *
1014  const SmallPtrSetImpl<MachineBasicBlock *> &SinkableBBs,
1015  ArrayRef<unsigned> DefedRegsInCopy,
1016  const TargetRegisterInfo *TRI) {
1017  MachineBasicBlock *SingleBB = nullptr;
1018  for (auto DefReg : DefedRegsInCopy) {
1019  MachineBasicBlock *BB =
1020  getSingleLiveInSuccBB(CurBB, SinkableBBs, DefReg, TRI);
1021  if (!BB || (SingleBB && SingleBB != BB))
1022  return nullptr;
1023  SingleBB = BB;
1024  }
1025  return SingleBB;
1026 }
1027 
1029  SmallVectorImpl<unsigned> &UsedOpsInCopy,
1030  LiveRegUnits &UsedRegUnits,
1031  const TargetRegisterInfo *TRI) {
1032  for (auto U : UsedOpsInCopy) {
1033  MachineOperand &MO = MI->getOperand(U);
1034  unsigned SrcReg = MO.getReg();
1035  if (!UsedRegUnits.available(SrcReg)) {
1036  MachineBasicBlock::iterator NI = std::next(MI->getIterator());
1037  for (MachineInstr &UI : make_range(NI, CurBB.end())) {
1038  if (UI.killsRegister(SrcReg, TRI)) {
1039  UI.clearRegisterKills(SrcReg, TRI);
1040  MO.setIsKill(true);
1041  break;
1042  }
1043  }
1044  }
1045  }
1046 }
1047 
1049  SmallVectorImpl<unsigned> &UsedOpsInCopy,
1050  SmallVectorImpl<unsigned> &DefedRegsInCopy) {
1051  for (auto DefReg : DefedRegsInCopy)
1052  SuccBB->removeLiveIn(DefReg);
1053  for (auto U : UsedOpsInCopy) {
1054  unsigned Reg = MI->getOperand(U).getReg();
1055  if (!SuccBB->isLiveIn(Reg))
1056  SuccBB->addLiveIn(Reg);
1057  }
1058 }
1059 
1061  SmallVectorImpl<unsigned> &UsedOpsInCopy,
1062  SmallVectorImpl<unsigned> &DefedRegsInCopy,
1063  LiveRegUnits &ModifiedRegUnits,
1064  LiveRegUnits &UsedRegUnits) {
1065  bool HasRegDependency = false;
1066  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1067  MachineOperand &MO = MI->getOperand(i);
1068  if (!MO.isReg())
1069  continue;
1070  unsigned Reg = MO.getReg();
1071  if (!Reg)
1072  continue;
1073  if (MO.isDef()) {
1074  if (!ModifiedRegUnits.available(Reg) || !UsedRegUnits.available(Reg)) {
1075  HasRegDependency = true;
1076  break;
1077  }
1078  DefedRegsInCopy.push_back(Reg);
1079 
1080  // FIXME: instead of isUse(), readsReg() would be a better fix here,
1081  // For example, we can ignore modifications in reg with undef. However,
1082  // it's not perfectly clear if skipping the internal read is safe in all
1083  // other targets.
1084  } else if (MO.isUse()) {
1085  if (!ModifiedRegUnits.available(Reg)) {
1086  HasRegDependency = true;
1087  break;
1088  }
1089  UsedOpsInCopy.push_back(i);
1090  }
1091  }
1092  return HasRegDependency;
1093 }
1094 
1095 bool PostRAMachineSinking::tryToSinkCopy(MachineBasicBlock &CurBB,
1096  MachineFunction &MF,
1097  const TargetRegisterInfo *TRI,
1098  const TargetInstrInfo *TII) {
1100  // FIXME: For now, we sink only to a successor which has a single predecessor
1101  // so that we can directly sink COPY instructions to the successor without
1102  // adding any new block or branch instruction.
1103  for (MachineBasicBlock *SI : CurBB.successors())
1104  if (!SI->livein_empty() && SI->pred_size() == 1)
1105  SinkableBBs.insert(SI);
1106 
1107  if (SinkableBBs.empty())
1108  return false;
1109 
1110  bool Changed = false;
1111 
1112  // Track which registers have been modified and used between the end of the
1113  // block and the current instruction.
1114  ModifiedRegUnits.clear();
1115  UsedRegUnits.clear();
1116 
1117  for (auto I = CurBB.rbegin(), E = CurBB.rend(); I != E;) {
1118  MachineInstr *MI = &*I;
1119  ++I;
1120 
1121  // Do not move any instruction across function call.
1122  if (MI->isCall())
1123  return false;
1124 
1125  if (!MI->isCopy() || !MI->getOperand(0).isRenamable()) {
1126  LiveRegUnits::accumulateUsedDefed(*MI, ModifiedRegUnits, UsedRegUnits,
1127  TRI);
1128  continue;
1129  }
1130 
1131  // Track the operand index for use in Copy.
1132  SmallVector<unsigned, 2> UsedOpsInCopy;
1133  // Track the register number defed in Copy.
1134  SmallVector<unsigned, 2> DefedRegsInCopy;
1135 
1136  // Don't sink the COPY if it would violate a register dependency.
1137  if (hasRegisterDependency(MI, UsedOpsInCopy, DefedRegsInCopy,
1138  ModifiedRegUnits, UsedRegUnits)) {
1139  LiveRegUnits::accumulateUsedDefed(*MI, ModifiedRegUnits, UsedRegUnits,
1140  TRI);
1141  continue;
1142  }
1143  assert((!UsedOpsInCopy.empty() && !DefedRegsInCopy.empty()) &&
1144  "Unexpect SrcReg or DefReg");
1145  MachineBasicBlock *SuccBB =
1146  getSingleLiveInSuccBB(CurBB, SinkableBBs, DefedRegsInCopy, TRI);
1147  // Don't sink if we cannot find a single sinkable successor in which Reg
1148  // is live-in.
1149  if (!SuccBB) {
1150  LiveRegUnits::accumulateUsedDefed(*MI, ModifiedRegUnits, UsedRegUnits,
1151  TRI);
1152  continue;
1153  }
1154  assert((SuccBB->pred_size() == 1 && *SuccBB->pred_begin() == &CurBB) &&
1155  "Unexpected predecessor");
1156 
1157  // Clear the kill flag if SrcReg is killed between MI and the end of the
1158  // block.
1159  clearKillFlags(MI, CurBB, UsedOpsInCopy, UsedRegUnits, TRI);
1160  MachineBasicBlock::iterator InsertPos = SuccBB->getFirstNonPHI();
1161  SuccBB->splice(InsertPos, &CurBB, MI);
1162  updateLiveIn(MI, SuccBB, UsedOpsInCopy, DefedRegsInCopy);
1163 
1164  Changed = true;
1165  ++NumPostRACopySink;
1166  }
1167  return Changed;
1168 }
1169 
1170 bool PostRAMachineSinking::runOnMachineFunction(MachineFunction &MF) {
1171  bool Changed = false;
1172  const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
1173  const TargetInstrInfo *TII = MF.getSubtarget().getInstrInfo();
1174 
1175  ModifiedRegUnits.init(*TRI);
1176  UsedRegUnits.init(*TRI);
1177  for (auto &BB : MF)
1178  Changed |= tryToSinkCopy(BB, MF, TRI, TII);
1179 
1180  return Changed;
1181 }
INITIALIZE_PASS_BEGIN(MachineSinking, DEBUG_TYPE, "Machine code sinking", false, false) INITIALIZE_PASS_END(MachineSinking
void push_back(const T &Elt)
Definition: SmallVector.h:212
static void clearKillFlags(MachineInstr *MI, MachineBasicBlock &CurBB, SmallVectorImpl< unsigned > &UsedOpsInCopy, LiveRegUnits &UsedRegUnits, const TargetRegisterInfo *TRI)
AnalysisUsage & addPreserved()
Add the specified Pass class to the set of analyses preserved by this pass.
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
bool use_nodbg_empty(unsigned RegNo) const
use_nodbg_empty - Return true if there are no non-Debug instructions using the specified register...
static bool AllUsesDominatedByBlock(Instruction *Inst, BasicBlock *BB, DominatorTree &DT)
AllUsesDominatedByBlock - Return true if all uses of the specified value occur in blocks dominated by...
Definition: Sink.cpp:37
bool isCall(QueryType Type=AnyInBundle) const
Definition: MachineInstr.h:479
MachineDomTreeNode * getNode(MachineBasicBlock *BB) const
getNode - return the (Post)DominatorTree node for the specified basic block.
MachineBasicBlock * getMBB() const
virtual bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const
Return true if it&#39;s safe to move a machine instruction that defines the specified register class...
const TargetRegisterClass * getRegClass(unsigned Reg) const
Return the register class of the specified virtual register.
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
static void accumulateUsedDefed(const MachineInstr &MI, LiveRegUnits &ModifiedRegUnits, LiveRegUnits &UsedRegUnits, const TargetRegisterInfo *TRI)
For a machine instruction MI, adds all register units used in UsedRegUnits and defined or clobbered i...
Definition: LiveRegUnits.h:48
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
void set(unsigned Idx)
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:285
iterator_range< use_nodbg_iterator > use_nodbg_operands(unsigned Reg) const
unsigned getReg() const
getReg - Returns the register number.
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
unsigned Reg
bool isPredicable(QueryType Type=AllInBundle) const
Return true if this instruction has a predicate operand that controls execution.
Definition: MachineInstr.h:533
uint64_t getFrequency() const
Returns the frequency as a fixpoint number scaled by the entry frequency.
MachineBlockFrequencyInfo pass uses BlockFrequencyInfoImpl implementation to estimate machine basic b...
unsigned getLoopDepth(const MachineBasicBlock *BB) const
Return the loop nesting level of the specified block.
STATISTIC(NumFunctions, "Total number of functions")
unsigned const TargetRegisterInfo * TRI
A debug info location.
Definition: DebugLoc.h:34
iterator_range< mop_iterator > operands()
Definition: MachineInstr.h:353
bool isCopyLike() const
Return true if the instruction behaves like a copy.
Definition: MachineInstr.h:900
bool isPHI() const
Definition: MachineInstr.h:855
void removeLiveIn(MCPhysReg Reg, LaneBitmask LaneMask=LaneBitmask::getAll())
Remove the specified register from the live in set.
Represents a predicate at the MachineFunction level.
iterator_range< succ_iterator > successors()
A templated base class for SmallPtrSet which provides the typesafe interface that is common across al...
Definition: SmallPtrSet.h:344
AnalysisUsage & addRequired()
#define INITIALIZE_PASS_DEPENDENCY(depName)
Definition: PassSupport.h:51
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
const HexagonInstrInfo * TII
Printable printMBBReference(const MachineBasicBlock &MBB)
Prints a machine basic block reference.
unsigned getNumOperands() const
Access to explicit operands of the instruction.
Definition: MachineInstr.h:314
MachineInstr * getVRegDef(unsigned Reg) const
getVRegDef - Return the machine instr that defines the specified virtual register or null if none is ...
void addLiveIns(const MachineBasicBlock &MBB)
Adds registers living into block MBB.
bool insert(const value_type &X)
Insert a new element into the SetVector.
Definition: SetVector.h:142
void clear()
Definition: SmallSet.h:119
void clearKillFlags(unsigned Reg) const
clearKillFlags - Iterate over all the uses of the given register and clear the kill flag from the Mac...
const std::vector< DomTreeNodeBase * > & getChildren() const
COFF::MachineTypes Machine
Definition: COFFYAML.cpp:363
virtual const TargetInstrInfo * getInstrInfo() const
static bool ProcessBlock(BasicBlock &BB, DominatorTree &DT, LoopInfo &LI, AAResults &AA)
Definition: Sink.cpp:199
reverse_iterator rend()
reverse_iterator rbegin()
TargetInstrInfo - Interface to description of machine instruction set.
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:410
void addLiveIn(MCPhysReg PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())
Adds the specified register as a live in.
unsigned const MachineRegisterInfo * MRI
INITIALIZE_PASS(PostRAMachineSinking, "postra-machine-sink", "PostRA Machine Sink", false, false) static bool aliasWithRegsInLiveIn(MachineBasicBlock &MBB
virtual bool getMemOpBaseRegImmOfs(MachineInstr &MemOp, unsigned &BaseReg, int64_t &Offset, const TargetRegisterInfo *TRI) const
Get the base register and byte offset of an instruction that reads/writes memory. ...
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
LLVM_NODISCARD bool empty() const
Definition: SmallPtrSet.h:92
LLVM_ATTRIBUTE_ALWAYS_INLINE iterator begin()
Definition: SmallVector.h:116
SmallSet - This maintains a set of unique values, optimizing for the case when the set is small (less...
Definition: SmallSet.h:36
char & PostRAMachineSinkingID
This pass perform post-ra machine sink for COPY instructions.
std::pair< iterator, bool > insert(PtrType Ptr)
Inserts Ptr if and only if there is no element in the container equal to Ptr.
Definition: SmallPtrSet.h:371
BlockFrequency getBlockFreq(const MachineBasicBlock *MBB) const
getblockFreq - Return block frequency.
bool dominates(const MachineDomTreeNode *A, const MachineDomTreeNode *B) const
Represent the analysis usage information of a pass.
static bool SinkInstruction(Instruction *Inst, SmallPtrSetImpl< Instruction *> &Stores, DominatorTree &DT, LoopInfo &LI, AAResults &AA)
SinkInstruction - Determine whether it is safe to sink the specified machine instruction out of its c...
Definition: Sink.cpp:139
self_iterator getIterator()
Definition: ilist_node.h:82
std::pair< NoneType, bool > insert(const T &V)
insert - Insert an element into the set if it isn&#39;t already there.
Definition: SmallSet.h:81
static cl::opt< unsigned > SplitEdgeProbabilityThreshold("machine-sink-split-probability-threshold", cl::desc("Percentage threshold for splitting single-instruction critical edge. " "If the branch threshold is higher than this threshold, we allow " "speculative execution of up to 1 instruction to avoid branching to " "splitted critical edge"), cl::init(40), cl::Hidden)
virtual bool shouldSink(const MachineInstr &MI) const
Return true if the instruction should be sunk by MachineSink.
std::vector< MachineBasicBlock * >::iterator pred_iterator
bool isCopy() const
Definition: MachineInstr.h:886
bool isConvergent(QueryType Type=AnyInBundle) const
Return true if this instruction is convergent.
Definition: MachineInstr.h:576
static bool SinkingPreventsImplicitNullCheck(MachineInstr &MI, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI)
Return true if MI is likely to be usable as a memory operation by the implicit null check optimizatio...
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
bool isDebugInstr() const
Definition: MachineInstr.h:845
INITIALIZE_PASS_END(RegBankSelect, DEBUG_TYPE, "Assign register bank of generic virtual registers", false, false) RegBankSelect
bool isConstantPhysReg(unsigned PhysReg) const
Returns true if PhysReg is unallocatable and constant throughout the function.
void setIsKill(bool Val=true)
virtual bool isAsCheapAsAMove(const MachineInstr &MI) const
Return true if the instruction is as cheap as a move instruction.
iterator_range< T > make_range(T x, T y)
Convenience function for iterating over sub-ranges.
Machine code sinking
static const DILocation * getMergedLocation(const DILocation *LocA, const DILocation *LocB, bool GenerateLocation=NoGeneratedLocation)
When two instructions are combined into a single instruction we also need to combine the original loc...
#define DEBUG_TYPE
Definition: MachineSink.cpp:56
static cl::opt< bool > UseBlockFreqInfo("machine-sink-bfi", cl::desc("Use block frequency info to find successors to sink"), cl::init(true), cl::Hidden)
SmallPtrSet - This class implements a set which is optimized for holding SmallSize or less elements...
Definition: SmallPtrSet.h:418
PostDominatorTree Class - Concrete subclass of DominatorTree that is used to compute the post-dominat...
MachineOperand class - Representation of each machine instruction operand.
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:862
char & MachineSinkingID
MachineSinking - This pass performs sinking on machine instructions.
bool dominates(const MachineDomTreeNode *A, const MachineDomTreeNode *B) const
MachineInstrBuilder MachineInstrBuilder & DefMI
void setPreservesCFG()
This function should be called by the pass, iff they do not:
Definition: Pass.cpp:286
unsigned pred_size() const
const Function & getFunction() const
Return the LLVM function that this machine code represents.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:133
bool isLiveIn(MCPhysReg Reg, LaneBitmask LaneMask=LaneBitmask::getAll()) const
Return true if the specified register is in the live in set.
void clear()
Completely clear the SetVector.
Definition: SetVector.h:216
void setDebugLoc(DebugLoc dl)
Replace current source information with new such.
bool isRenamable() const
isRenamable - Returns true if this register may be renamed, i.e.
void replaceRegWith(unsigned FromReg, unsigned ToReg)
replaceRegWith - Replace all instances of FromReg with ToReg in the machine function.
unsigned succ_size() const
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:156
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
MachineFunctionProperties & set(Property P)
static MachineBasicBlock * getSingleLiveInSuccBB(MachineBasicBlock &CurBB, const SmallPtrSetImpl< MachineBasicBlock *> &SinkableBBs, unsigned Reg, const TargetRegisterInfo *TRI)
BranchProbability getEdgeProbability(const MachineBasicBlock *Src, const MachineBasicBlock *Dst) const
Representation of each machine instruction.
Definition: MachineInstr.h:60
static void updateLiveIn(MachineInstr *MI, MachineBasicBlock *SuccBB, SmallVectorImpl< unsigned > &UsedOpsInCopy, SmallVectorImpl< unsigned > &DefedRegsInCopy)
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
LLVM_ATTRIBUTE_ALWAYS_INLINE iterator end()
Definition: SmallVector.h:120
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Take an instruction from MBB &#39;Other&#39; at the position From, and insert it into this MBB right before &#39;...
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
virtual bool analyzeBranchPredicate(MachineBasicBlock &MBB, MachineBranchPredicate &MBP, bool AllowModify=false) const
Analyze the branching code at the end of MBB and parse it into the MachineBranchPredicate structure i...
bool isEHPad() const
Returns true if the block is a landing pad.
LLVM_NODISCARD bool empty() const
Definition: SmallVector.h:61
bool available(unsigned Reg) const
Returns true if no part of physical register Reg is live.
Definition: LiveRegUnits.h:118
#define I(x, y, z)
Definition: MD5.cpp:58
void initializeMachineSinkingPass(PassRegistry &)
static void collectDebugValues(MachineInstr &MI, SmallVectorImpl< MachineInstr *> &DbgValues)
collectDebgValues - Scan instructions following MI and collect any matching DBG_VALUEs.
iterator getFirstNonPHI()
Returns a pointer to the first instruction in this block that is not a PHINode instruction.
bool isSuccessor(const MachineBasicBlock *MBB) const
Return true if the specified MBB is a successor of this block.
bool hasOneNonDBGUse(unsigned RegNo) const
hasOneNonDBGUse - Return true if there is exactly one non-Debug instruction using the specified regis...
A set of register units used to track register liveness.
Definition: LiveRegUnits.h:31
bool isReg() const
isReg - Tests if this is a MO_Register operand.
bool isReachableFromEntry(const MachineBasicBlock *A)
isReachableFromEntry - Return true if A is dominated by the entry block of the function containing it...
static bool hasRegisterDependency(MachineInstr *MI, SmallVectorImpl< unsigned > &UsedOpsInCopy, SmallVectorImpl< unsigned > &DefedRegsInCopy, LiveRegUnits &ModifiedRegUnits, LiveRegUnits &UsedRegUnits)
bool mayLoad(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read memory.
Definition: MachineInstr.h:653
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static cl::opt< bool > SplitEdges("machine-sink-split", cl::desc("Split critical edges during machine sinking"), cl::init(true), cl::Hidden)
aarch64 promote const
bool isLoopHeader(const MachineBasicBlock *BB) const
True if the block is a loop header node.
A vector that has set insertion semantics.
Definition: SetVector.h:41
MachineLoop * getLoopFor(const MachineBasicBlock *BB) const
Return the innermost loop that BB lives in.
IRTranslator LLVM IR MI
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:49
A wrapper pass to provide the legacy pass manager access to a suitably prepared AAResults object...
#define LLVM_DEBUG(X)
Definition: Debug.h:119
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:316
iterator_range< use_instr_nodbg_iterator > use_nodbg_instructions(unsigned Reg) const
DominatorTree Class - Concrete subclass of DominatorTreeBase that is used to compute a normal dominat...
bool isSafeToMove(AliasAnalysis *AA, bool &SawStore) const
Return true if it is safe to move this instruction.
Properties which a MachineFunction may have at a given point in time.