LLVM  7.0.0svn
SIDefines.h
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1 //===-- SIDefines.h - SI Helper Macros ----------------------*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 /// \file
9 //===----------------------------------------------------------------------===//
10 
11 #include "llvm/MC/MCInstrDesc.h"
12 
13 #ifndef LLVM_LIB_TARGET_AMDGPU_SIDEFINES_H
14 #define LLVM_LIB_TARGET_AMDGPU_SIDEFINES_H
15 
16 namespace llvm {
17 
18 namespace SIInstrFlags {
19 // This needs to be kept in sync with the field bits in InstSI.
20 enum : uint64_t {
21  // Low bits - basic encoding information.
22  SALU = 1 << 0,
23  VALU = 1 << 1,
24 
25  // SALU instruction formats.
26  SOP1 = 1 << 2,
27  SOP2 = 1 << 3,
28  SOPC = 1 << 4,
29  SOPK = 1 << 5,
30  SOPP = 1 << 6,
31 
32  // VALU instruction formats.
33  VOP1 = 1 << 7,
34  VOP2 = 1 << 8,
35  VOPC = 1 << 9,
36 
37  // TODO: Should this be spilt into VOP3 a and b?
38  VOP3 = 1 << 10,
39  VOP3P = 1 << 12,
40 
41  VINTRP = 1 << 13,
42  SDWA = 1 << 14,
43  DPP = 1 << 15,
44 
45  // Memory instruction formats.
46  MUBUF = 1 << 16,
47  MTBUF = 1 << 17,
48  SMRD = 1 << 18,
49  MIMG = 1 << 19,
50  EXP = 1 << 20,
51  FLAT = 1 << 21,
52  DS = 1 << 22,
53 
54  // Pseudo instruction formats.
55  VGPRSpill = 1 << 23,
56  SGPRSpill = 1 << 24,
57 
58  // High bits - other information.
59  VM_CNT = UINT64_C(1) << 32,
60  EXP_CNT = UINT64_C(1) << 33,
61  LGKM_CNT = UINT64_C(1) << 34,
62 
63  WQM = UINT64_C(1) << 35,
64  DisableWQM = UINT64_C(1) << 36,
65  Gather4 = UINT64_C(1) << 37,
66  SOPK_ZEXT = UINT64_C(1) << 38,
67  SCALAR_STORE = UINT64_C(1) << 39,
68  FIXED_SIZE = UINT64_C(1) << 40,
69  VOPAsmPrefer32Bit = UINT64_C(1) << 41,
70  VOP3_OPSEL = UINT64_C(1) << 42,
71  maybeAtomic = UINT64_C(1) << 43,
72  renamedInGFX9 = UINT64_C(1) << 44,
73 
74  // Is a clamp on FP type.
75  FPClamp = UINT64_C(1) << 45,
76 
77  // Is an integer clamp
78  IntClamp = UINT64_C(1) << 46,
79 
80  // Clamps lo component of register.
81  ClampLo = UINT64_C(1) << 47,
82 
83  // Clamps hi component of register.
84  // ClampLo and ClampHi set for packed clamp.
85  ClampHi = UINT64_C(1) << 48,
86 
87  // Is a packed VOP3P instruction.
88  IsPacked = UINT64_C(1) << 49,
89 
90  // "d16" bit set or not.
91  D16 = UINT64_C(1) << 50
92 };
93 
94 // v_cmp_class_* etc. use a 10-bit mask for what operation is checked.
95 // The result is true if any of these tests are true.
96 enum ClassFlags {
97  S_NAN = 1 << 0, // Signaling NaN
98  Q_NAN = 1 << 1, // Quiet NaN
99  N_INFINITY = 1 << 2, // Negative infinity
100  N_NORMAL = 1 << 3, // Negative normal
101  N_SUBNORMAL = 1 << 4, // Negative subnormal
102  N_ZERO = 1 << 5, // Negative zero
103  P_ZERO = 1 << 6, // Positive zero
104  P_SUBNORMAL = 1 << 7, // Positive subnormal
105  P_NORMAL = 1 << 8, // Positive normal
106  P_INFINITY = 1 << 9 // Positive infinity
107 };
108 }
109 
110 namespace AMDGPU {
111  enum OperandType {
112  /// Operands with register or 32-bit immediate
119 
120  /// Operands with register or inline constant
129 
132 
135 
138 
139  // Operand for source modifiers for VOP instructions
141 
142  // Operand for SDWA instructions
144 
145  /// Operand with 32-bit immediate that uses the constant bus.
148  };
149 }
150 
151 // Input operand modifiers bit-masks
152 // NEG and SEXT share same bit-mask because they can't be set simultaneously.
153 namespace SISrcMods {
154  enum {
155  NEG = 1 << 0, // Floating-point negate modifier
156  ABS = 1 << 1, // Floating-point absolute modifier
157  SEXT = 1 << 0, // Integer sign-extend modifier
158  NEG_HI = ABS, // Floating-point negate high packed component modifier.
159  OP_SEL_0 = 1 << 2,
160  OP_SEL_1 = 1 << 3,
161  DST_OP_SEL = 1 << 3 // VOP3 dst op_sel (share mask with OP_SEL_1)
162  };
163 }
164 
165 namespace SIOutMods {
166  enum {
167  NONE = 0,
168  MUL2 = 1,
169  MUL4 = 2,
170  DIV2 = 3
171  };
172 }
173 
174 namespace VGPRIndexMode {
175  enum {
176  SRC0_ENABLE = 1 << 0,
177  SRC1_ENABLE = 1 << 1,
178  SRC2_ENABLE = 1 << 2,
179  DST_ENABLE = 1 << 3
180  };
181 }
182 
183 namespace AMDGPUAsmVariants {
184  enum {
185  DEFAULT = 0,
186  VOP3 = 1,
187  SDWA = 2,
188  SDWA9 = 3,
189  DPP = 4
190  };
191 }
192 
193 namespace AMDGPU {
194 namespace EncValues { // Encoding values of enum9/8/7 operands
195 
196 enum {
197  SGPR_MIN = 0,
198  SGPR_MAX = 101,
199  TTMP_VI_MIN = 112,
200  TTMP_VI_MAX = 123,
209  VGPR_MIN = 256,
210  VGPR_MAX = 511
211 };
212 
213 } // namespace EncValues
214 } // namespace AMDGPU
215 
216 namespace AMDGPU {
217 namespace SendMsg { // Encoding of SIMM16 used in s_sendmsg* insns.
218 
219 enum Id { // Message ID, width(4) [3:0].
224  ID_SYSMSG = 15,
225  ID_GAPS_LAST_, // Indicate that sequence has gaps.
229  ID_MASK_ = (((1 << ID_WIDTH_) - 1) << ID_SHIFT_)
230 };
231 
232 enum Op { // Both GS and SYS operation IDs.
235  // width(2) [5:4]
243  OP_GS_MASK_ = (((1 << OP_GS_WIDTH_) - 1) << OP_SHIFT_),
244  // width(3) [6:4]
253 };
254 
255 enum StreamId { // Stream ID, (2) [9:8].
262 };
263 
264 } // namespace SendMsg
265 
266 namespace Hwreg { // Encoding of SIMM16 used in s_setreg/getreg* insns.
267 
268 enum Id { // HwRegCode, (6) [5:0]
270  ID_SYMBOLIC_FIRST_ = 1, // There are corresponding symbolic names defined.
271  ID_MODE = 1,
274  ID_HW_ID = 4,
283  ID_MASK_ = (((1 << ID_WIDTH_) - 1) << ID_SHIFT_)
284 };
285 
286 enum Offset { // Offset, (5) [10:6]
291 
294 };
295 
296 enum WidthMinusOne { // WidthMinusOne, (5) [15:11]
301 
304 };
305 
306 } // namespace Hwreg
307 
308 namespace Swizzle { // Encoding of swizzle macro used in ds_swizzle_b32.
309 
310 enum Id { // id of symbolic names
316 };
317 
318 enum EncBits {
319 
320  // swizzle mode encodings
321 
322  QUAD_PERM_ENC = 0x8000,
324 
327 
328  // QUAD_PERM encodings
329 
330  LANE_MASK = 0x3,
333  LANE_NUM = 4,
334 
335  // BITMASK_PERM encodings
336 
337  BITMASK_MASK = 0x1F,
340 
344 };
345 
346 } // namespace Swizzle
347 
348 namespace SDWA {
349 
350 enum SdwaSel {
351  BYTE_0 = 0,
352  BYTE_1 = 1,
353  BYTE_2 = 2,
354  BYTE_3 = 3,
355  WORD_0 = 4,
356  WORD_1 = 5,
357  DWORD = 6,
358 };
359 
360 enum DstUnused {
364 };
365 
367  SRC_SGPR_MASK = 0x100,
371 
378 };
379 
380 } // namespace SDWA
381 } // namespace AMDGPU
382 
383 #define R_00B028_SPI_SHADER_PGM_RSRC1_PS 0x00B028
384 #define R_00B02C_SPI_SHADER_PGM_RSRC2_PS 0x00B02C
385 #define S_00B02C_EXTRA_LDS_SIZE(x) (((x) & 0xFF) << 8)
386 #define R_00B128_SPI_SHADER_PGM_RSRC1_VS 0x00B128
387 #define R_00B228_SPI_SHADER_PGM_RSRC1_GS 0x00B228
388 #define R_00B328_SPI_SHADER_PGM_RSRC1_ES 0x00B328
389 #define R_00B428_SPI_SHADER_PGM_RSRC1_HS 0x00B428
390 #define R_00B528_SPI_SHADER_PGM_RSRC1_LS 0x00B528
391 #define R_00B848_COMPUTE_PGM_RSRC1 0x00B848
392 #define S_00B028_VGPRS(x) (((x) & 0x3F) << 0)
393 #define S_00B028_SGPRS(x) (((x) & 0x0F) << 6)
394 
395 #define R_00B84C_COMPUTE_PGM_RSRC2 0x00B84C
396 #define S_00B84C_SCRATCH_EN(x) (((x) & 0x1) << 0)
397 #define G_00B84C_SCRATCH_EN(x) (((x) >> 0) & 0x1)
398 #define C_00B84C_SCRATCH_EN 0xFFFFFFFE
399 #define S_00B84C_USER_SGPR(x) (((x) & 0x1F) << 1)
400 #define G_00B84C_USER_SGPR(x) (((x) >> 1) & 0x1F)
401 #define C_00B84C_USER_SGPR 0xFFFFFFC1
402 #define S_00B84C_TRAP_HANDLER(x) (((x) & 0x1) << 6)
403 #define G_00B84C_TRAP_HANDLER(x) (((x) >> 6) & 0x1)
404 #define C_00B84C_TRAP_HANDLER 0xFFFFFFBF
405 #define S_00B84C_TGID_X_EN(x) (((x) & 0x1) << 7)
406 #define G_00B84C_TGID_X_EN(x) (((x) >> 7) & 0x1)
407 #define C_00B84C_TGID_X_EN 0xFFFFFF7F
408 #define S_00B84C_TGID_Y_EN(x) (((x) & 0x1) << 8)
409 #define G_00B84C_TGID_Y_EN(x) (((x) >> 8) & 0x1)
410 #define C_00B84C_TGID_Y_EN 0xFFFFFEFF
411 #define S_00B84C_TGID_Z_EN(x) (((x) & 0x1) << 9)
412 #define G_00B84C_TGID_Z_EN(x) (((x) >> 9) & 0x1)
413 #define C_00B84C_TGID_Z_EN 0xFFFFFDFF
414 #define S_00B84C_TG_SIZE_EN(x) (((x) & 0x1) << 10)
415 #define G_00B84C_TG_SIZE_EN(x) (((x) >> 10) & 0x1)
416 #define C_00B84C_TG_SIZE_EN 0xFFFFFBFF
417 #define S_00B84C_TIDIG_COMP_CNT(x) (((x) & 0x03) << 11)
418 #define G_00B84C_TIDIG_COMP_CNT(x) (((x) >> 11) & 0x03)
419 #define C_00B84C_TIDIG_COMP_CNT 0xFFFFE7FF
420 /* CIK */
421 #define S_00B84C_EXCP_EN_MSB(x) (((x) & 0x03) << 13)
422 #define G_00B84C_EXCP_EN_MSB(x) (((x) >> 13) & 0x03)
423 #define C_00B84C_EXCP_EN_MSB 0xFFFF9FFF
424 /* */
425 #define S_00B84C_LDS_SIZE(x) (((x) & 0x1FF) << 15)
426 #define G_00B84C_LDS_SIZE(x) (((x) >> 15) & 0x1FF)
427 #define C_00B84C_LDS_SIZE 0xFF007FFF
428 #define S_00B84C_EXCP_EN(x) (((x) & 0x7F) << 24)
429 #define G_00B84C_EXCP_EN(x) (((x) >> 24) & 0x7F)
430 #define C_00B84C_EXCP_EN
431 
432 #define R_0286CC_SPI_PS_INPUT_ENA 0x0286CC
433 #define R_0286D0_SPI_PS_INPUT_ADDR 0x0286D0
434 
435 #define R_00B848_COMPUTE_PGM_RSRC1 0x00B848
436 #define S_00B848_VGPRS(x) (((x) & 0x3F) << 0)
437 #define G_00B848_VGPRS(x) (((x) >> 0) & 0x3F)
438 #define C_00B848_VGPRS 0xFFFFFFC0
439 #define S_00B848_SGPRS(x) (((x) & 0x0F) << 6)
440 #define G_00B848_SGPRS(x) (((x) >> 6) & 0x0F)
441 #define C_00B848_SGPRS 0xFFFFFC3F
442 #define S_00B848_PRIORITY(x) (((x) & 0x03) << 10)
443 #define G_00B848_PRIORITY(x) (((x) >> 10) & 0x03)
444 #define C_00B848_PRIORITY 0xFFFFF3FF
445 #define S_00B848_FLOAT_MODE(x) (((x) & 0xFF) << 12)
446 #define G_00B848_FLOAT_MODE(x) (((x) >> 12) & 0xFF)
447 #define C_00B848_FLOAT_MODE 0xFFF00FFF
448 #define S_00B848_PRIV(x) (((x) & 0x1) << 20)
449 #define G_00B848_PRIV(x) (((x) >> 20) & 0x1)
450 #define C_00B848_PRIV 0xFFEFFFFF
451 #define S_00B848_DX10_CLAMP(x) (((x) & 0x1) << 21)
452 #define G_00B848_DX10_CLAMP(x) (((x) >> 21) & 0x1)
453 #define C_00B848_DX10_CLAMP 0xFFDFFFFF
454 #define S_00B848_DEBUG_MODE(x) (((x) & 0x1) << 22)
455 #define G_00B848_DEBUG_MODE(x) (((x) >> 22) & 0x1)
456 #define C_00B848_DEBUG_MODE 0xFFBFFFFF
457 #define S_00B848_IEEE_MODE(x) (((x) & 0x1) << 23)
458 #define G_00B848_IEEE_MODE(x) (((x) >> 23) & 0x1)
459 #define C_00B848_IEEE_MODE 0xFF7FFFFF
460 
461 
462 // Helpers for setting FLOAT_MODE
463 #define FP_ROUND_ROUND_TO_NEAREST 0
464 #define FP_ROUND_ROUND_TO_INF 1
465 #define FP_ROUND_ROUND_TO_NEGINF 2
466 #define FP_ROUND_ROUND_TO_ZERO 3
467 
468 // Bits 3:0 control rounding mode. 1:0 control single precision, 3:2 double
469 // precision.
470 #define FP_ROUND_MODE_SP(x) ((x) & 0x3)
471 #define FP_ROUND_MODE_DP(x) (((x) & 0x3) << 2)
472 
473 #define FP_DENORM_FLUSH_IN_FLUSH_OUT 0
474 #define FP_DENORM_FLUSH_OUT 1
475 #define FP_DENORM_FLUSH_IN 2
476 #define FP_DENORM_FLUSH_NONE 3
477 
478 
479 // Bits 7:4 control denormal handling. 5:4 control single precision, 6:7 double
480 // precision.
481 #define FP_DENORM_MODE_SP(x) (((x) & 0x3) << 4)
482 #define FP_DENORM_MODE_DP(x) (((x) & 0x3) << 6)
483 
484 #define R_00B860_COMPUTE_TMPRING_SIZE 0x00B860
485 #define S_00B860_WAVESIZE(x) (((x) & 0x1FFF) << 12)
486 
487 #define R_0286E8_SPI_TMPRING_SIZE 0x0286E8
488 #define S_0286E8_WAVESIZE(x) (((x) & 0x1FFF) << 12)
489 
490 #define R_SPILLED_SGPRS 0x4
491 #define R_SPILLED_VGPRS 0x8
492 } // End namespace llvm
493 
494 #endif
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
static std::vector< std::pair< int, unsigned > > Swizzle(std::vector< std::pair< int, unsigned >> Src, R600InstrInfo::BankSwizzle Swz)
Operands with register or inline constant.
Definition: SIDefines.h:121
Operands with register or 32-bit immediate.
Definition: SIDefines.h:113
Operand with 32-bit immediate that uses the constant bus.
Definition: SIDefines.h:146