LLVM  9.0.0svn
SIDefines.h
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1 //===-- SIDefines.h - SI Helper Macros ----------------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 /// \file
8 //===----------------------------------------------------------------------===//
9 
10 #include "llvm/MC/MCInstrDesc.h"
11 
12 #ifndef LLVM_LIB_TARGET_AMDGPU_SIDEFINES_H
13 #define LLVM_LIB_TARGET_AMDGPU_SIDEFINES_H
14 
15 namespace llvm {
16 
17 namespace SIInstrFlags {
18 // This needs to be kept in sync with the field bits in InstSI.
19 enum : uint64_t {
20  // Low bits - basic encoding information.
21  SALU = 1 << 0,
22  VALU = 1 << 1,
23 
24  // SALU instruction formats.
25  SOP1 = 1 << 2,
26  SOP2 = 1 << 3,
27  SOPC = 1 << 4,
28  SOPK = 1 << 5,
29  SOPP = 1 << 6,
30 
31  // VALU instruction formats.
32  VOP1 = 1 << 7,
33  VOP2 = 1 << 8,
34  VOPC = 1 << 9,
35 
36  // TODO: Should this be spilt into VOP3 a and b?
37  VOP3 = 1 << 10,
38  VOP3P = 1 << 12,
39 
40  VINTRP = 1 << 13,
41  SDWA = 1 << 14,
42  DPP = 1 << 15,
43 
44  // Memory instruction formats.
45  MUBUF = 1 << 16,
46  MTBUF = 1 << 17,
47  SMRD = 1 << 18,
48  MIMG = 1 << 19,
49  EXP = 1 << 20,
50  FLAT = 1 << 21,
51  DS = 1 << 22,
52 
53  // Pseudo instruction formats.
54  VGPRSpill = 1 << 23,
55  SGPRSpill = 1 << 24,
56 
57  // High bits - other information.
58  VM_CNT = UINT64_C(1) << 32,
59  EXP_CNT = UINT64_C(1) << 33,
60  LGKM_CNT = UINT64_C(1) << 34,
61 
62  WQM = UINT64_C(1) << 35,
63  DisableWQM = UINT64_C(1) << 36,
64  Gather4 = UINT64_C(1) << 37,
65  SOPK_ZEXT = UINT64_C(1) << 38,
66  SCALAR_STORE = UINT64_C(1) << 39,
67  FIXED_SIZE = UINT64_C(1) << 40,
68  VOPAsmPrefer32Bit = UINT64_C(1) << 41,
69  VOP3_OPSEL = UINT64_C(1) << 42,
70  maybeAtomic = UINT64_C(1) << 43,
71  renamedInGFX9 = UINT64_C(1) << 44,
72 
73  // Is a clamp on FP type.
74  FPClamp = UINT64_C(1) << 45,
75 
76  // Is an integer clamp
77  IntClamp = UINT64_C(1) << 46,
78 
79  // Clamps lo component of register.
80  ClampLo = UINT64_C(1) << 47,
81 
82  // Clamps hi component of register.
83  // ClampLo and ClampHi set for packed clamp.
84  ClampHi = UINT64_C(1) << 48,
85 
86  // Is a packed VOP3P instruction.
87  IsPacked = UINT64_C(1) << 49,
88 
89  // Is a D16 buffer instruction.
90  D16Buf = UINT64_C(1) << 50,
91 
92  // FLAT instruction accesses FLAT_GLBL or FLAT_SCRATCH segment.
93  IsNonFlatSeg = UINT64_C(1) << 51,
94 
95  // Uses floating point double precision rounding mode
96  FPDPRounding = UINT64_C(1) << 52
97 };
98 
99 // v_cmp_class_* etc. use a 10-bit mask for what operation is checked.
100 // The result is true if any of these tests are true.
101 enum ClassFlags : unsigned {
102  S_NAN = 1 << 0, // Signaling NaN
103  Q_NAN = 1 << 1, // Quiet NaN
104  N_INFINITY = 1 << 2, // Negative infinity
105  N_NORMAL = 1 << 3, // Negative normal
106  N_SUBNORMAL = 1 << 4, // Negative subnormal
107  N_ZERO = 1 << 5, // Negative zero
108  P_ZERO = 1 << 6, // Positive zero
109  P_SUBNORMAL = 1 << 7, // Positive subnormal
110  P_NORMAL = 1 << 8, // Positive normal
111  P_INFINITY = 1 << 9 // Positive infinity
112 };
113 }
114 
115 namespace AMDGPU {
116  enum OperandType : unsigned {
117  /// Operands with register or 32-bit immediate
126 
127  /// Operands with register or inline constant
136 
139 
142 
145 
146  // Operand for source modifiers for VOP instructions
148 
149  // Operand for SDWA instructions
151 
152  /// Operand with 32-bit immediate that uses the constant bus.
155  };
156 }
157 
158 // Input operand modifiers bit-masks
159 // NEG and SEXT share same bit-mask because they can't be set simultaneously.
160 namespace SISrcMods {
161  enum : unsigned {
162  NEG = 1 << 0, // Floating-point negate modifier
163  ABS = 1 << 1, // Floating-point absolute modifier
164  SEXT = 1 << 0, // Integer sign-extend modifier
165  NEG_HI = ABS, // Floating-point negate high packed component modifier.
166  OP_SEL_0 = 1 << 2,
167  OP_SEL_1 = 1 << 3,
168  DST_OP_SEL = 1 << 3 // VOP3 dst op_sel (share mask with OP_SEL_1)
169  };
170 }
171 
172 namespace SIOutMods {
173  enum : unsigned {
174  NONE = 0,
175  MUL2 = 1,
176  MUL4 = 2,
177  DIV2 = 3
178  };
179 }
180 
181 namespace AMDGPU {
182 namespace VGPRIndexMode {
183 
184 enum Id : unsigned { // id of symbolic names
185  ID_SRC0 = 0,
189 
192 };
193 
194 enum EncBits : unsigned {
195  OFF = 0,
201 };
202 
203 } // namespace VGPRIndexMode
204 } // namespace AMDGPU
205 
206 namespace AMDGPUAsmVariants {
207  enum : unsigned {
208  DEFAULT = 0,
209  VOP3 = 1,
210  SDWA = 2,
211  SDWA9 = 3,
212  DPP = 4
213  };
214 }
215 
216 namespace AMDGPU {
217 namespace EncValues { // Encoding values of enum9/8/7 operands
218 
219 enum : unsigned {
220  SGPR_MIN = 0,
221  SGPR_MAX_SI = 101,
223  TTMP_VI_MIN = 112,
224  TTMP_VI_MAX = 123,
233  VGPR_MIN = 256,
234  VGPR_MAX = 511
235 };
236 
237 } // namespace EncValues
238 } // namespace AMDGPU
239 
240 namespace AMDGPU {
241 namespace SendMsg { // Encoding of SIMM16 used in s_sendmsg* insns.
242 
243 enum Id { // Message ID, width(4) [3:0].
249  ID_SYSMSG = 15,
250  ID_GAPS_LAST_, // Indicate that sequence has gaps.
254  ID_MASK_ = (((1 << ID_WIDTH_) - 1) << ID_SHIFT_)
255 };
256 
257 enum Op { // Both GS and SYS operation IDs.
260  // width(2) [5:4]
268  OP_GS_MASK_ = (((1 << OP_GS_WIDTH_) - 1) << OP_SHIFT_),
269  // width(3) [6:4]
278 };
279 
280 enum StreamId : unsigned { // Stream ID, (2) [9:8].
287 };
288 
289 } // namespace SendMsg
290 
291 namespace Hwreg { // Encoding of SIMM16 used in s_setreg/getreg* insns.
292 
293 enum Id { // HwRegCode, (6) [5:0]
295  ID_SYMBOLIC_FIRST_ = 1, // There are corresponding symbolic names defined.
296  ID_MODE = 1,
299  ID_HW_ID = 4,
305  ID_TBA_LO = 16,
307  ID_TBA_HI = 17,
308  ID_TMA_LO = 18,
309  ID_TMA_HI = 19,
317  ID_MASK_ = (((1 << ID_WIDTH_) - 1) << ID_SHIFT_)
318 };
319 
320 enum Offset : unsigned { // Offset, (5) [10:6]
325 
328 };
329 
330 enum WidthMinusOne : unsigned { // WidthMinusOne, (5) [15:11]
335 
338 };
339 
340 // Some values from WidthMinusOne mapped into Width domain.
341 enum Width : unsigned {
343 };
344 
345 } // namespace Hwreg
346 
347 namespace Swizzle { // Encoding of swizzle macro used in ds_swizzle_b32.
348 
349 enum Id : unsigned { // id of symbolic names
355 };
356 
357 enum EncBits : unsigned {
358 
359  // swizzle mode encodings
360 
361  QUAD_PERM_ENC = 0x8000,
363 
366 
367  // QUAD_PERM encodings
368 
369  LANE_MASK = 0x3,
372  LANE_NUM = 4,
373 
374  // BITMASK_PERM encodings
375 
376  BITMASK_MASK = 0x1F,
379 
383 };
384 
385 } // namespace Swizzle
386 
387 namespace SDWA {
388 
389 enum SdwaSel : unsigned {
390  BYTE_0 = 0,
391  BYTE_1 = 1,
392  BYTE_2 = 2,
393  BYTE_3 = 3,
394  WORD_0 = 4,
395  WORD_1 = 5,
396  DWORD = 6,
397 };
398 
399 enum DstUnused : unsigned {
403 };
404 
405 enum SDWA9EncValues : unsigned {
406  SRC_SGPR_MASK = 0x100,
410 
418 };
419 
420 } // namespace SDWA
421 
422 namespace DPP {
423 
424 enum DppCtrl : unsigned {
427  DPP_UNUSED1 = 0x100,
428  ROW_SHL0 = 0x100,
429  ROW_SHL_FIRST = 0x101,
430  ROW_SHL_LAST = 0x10F,
431  DPP_UNUSED2 = 0x110,
432  ROW_SHR0 = 0x110,
433  ROW_SHR_FIRST = 0x111,
434  ROW_SHR_LAST = 0x11F,
435  DPP_UNUSED3 = 0x120,
436  ROW_ROR0 = 0x120,
437  ROW_ROR_FIRST = 0x121,
438  ROW_ROR_LAST = 0x12F,
439  WAVE_SHL1 = 0x130,
442  WAVE_ROL1 = 0x134,
445  WAVE_SHR1 = 0x138,
448  WAVE_ROR1 = 0x13C,
451  ROW_MIRROR = 0x140,
453  BCAST15 = 0x142,
454  BCAST31 = 0x143,
458  ROW_SHARE_LAST = 0x15F,
460  ROW_XMASK_LAST = 0x16F,
462 };
463 
464 enum DppFiMode {
465  DPP_FI_0 = 0,
466  DPP_FI_1 = 1,
467  DPP8_FI_0 = 0xE9,
468  DPP8_FI_1 = 0xEA,
469 };
470 
471 } // namespace DPP
472 } // namespace AMDGPU
473 
474 #define R_00B028_SPI_SHADER_PGM_RSRC1_PS 0x00B028
475 #define R_00B02C_SPI_SHADER_PGM_RSRC2_PS 0x00B02C
476 #define S_00B02C_EXTRA_LDS_SIZE(x) (((x) & 0xFF) << 8)
477 #define R_00B128_SPI_SHADER_PGM_RSRC1_VS 0x00B128
478 #define R_00B228_SPI_SHADER_PGM_RSRC1_GS 0x00B228
479 #define R_00B328_SPI_SHADER_PGM_RSRC1_ES 0x00B328
480 #define R_00B428_SPI_SHADER_PGM_RSRC1_HS 0x00B428
481 #define R_00B528_SPI_SHADER_PGM_RSRC1_LS 0x00B528
482 #define R_00B848_COMPUTE_PGM_RSRC1 0x00B848
483 #define S_00B028_VGPRS(x) (((x) & 0x3F) << 0)
484 #define S_00B028_SGPRS(x) (((x) & 0x0F) << 6)
485 
486 #define R_00B84C_COMPUTE_PGM_RSRC2 0x00B84C
487 #define S_00B84C_SCRATCH_EN(x) (((x) & 0x1) << 0)
488 #define G_00B84C_SCRATCH_EN(x) (((x) >> 0) & 0x1)
489 #define C_00B84C_SCRATCH_EN 0xFFFFFFFE
490 #define S_00B84C_USER_SGPR(x) (((x) & 0x1F) << 1)
491 #define G_00B84C_USER_SGPR(x) (((x) >> 1) & 0x1F)
492 #define C_00B84C_USER_SGPR 0xFFFFFFC1
493 #define S_00B84C_TRAP_HANDLER(x) (((x) & 0x1) << 6)
494 #define G_00B84C_TRAP_HANDLER(x) (((x) >> 6) & 0x1)
495 #define C_00B84C_TRAP_HANDLER 0xFFFFFFBF
496 #define S_00B84C_TGID_X_EN(x) (((x) & 0x1) << 7)
497 #define G_00B84C_TGID_X_EN(x) (((x) >> 7) & 0x1)
498 #define C_00B84C_TGID_X_EN 0xFFFFFF7F
499 #define S_00B84C_TGID_Y_EN(x) (((x) & 0x1) << 8)
500 #define G_00B84C_TGID_Y_EN(x) (((x) >> 8) & 0x1)
501 #define C_00B84C_TGID_Y_EN 0xFFFFFEFF
502 #define S_00B84C_TGID_Z_EN(x) (((x) & 0x1) << 9)
503 #define G_00B84C_TGID_Z_EN(x) (((x) >> 9) & 0x1)
504 #define C_00B84C_TGID_Z_EN 0xFFFFFDFF
505 #define S_00B84C_TG_SIZE_EN(x) (((x) & 0x1) << 10)
506 #define G_00B84C_TG_SIZE_EN(x) (((x) >> 10) & 0x1)
507 #define C_00B84C_TG_SIZE_EN 0xFFFFFBFF
508 #define S_00B84C_TIDIG_COMP_CNT(x) (((x) & 0x03) << 11)
509 #define G_00B84C_TIDIG_COMP_CNT(x) (((x) >> 11) & 0x03)
510 #define C_00B84C_TIDIG_COMP_CNT 0xFFFFE7FF
511 /* CIK */
512 #define S_00B84C_EXCP_EN_MSB(x) (((x) & 0x03) << 13)
513 #define G_00B84C_EXCP_EN_MSB(x) (((x) >> 13) & 0x03)
514 #define C_00B84C_EXCP_EN_MSB 0xFFFF9FFF
515 /* */
516 #define S_00B84C_LDS_SIZE(x) (((x) & 0x1FF) << 15)
517 #define G_00B84C_LDS_SIZE(x) (((x) >> 15) & 0x1FF)
518 #define C_00B84C_LDS_SIZE 0xFF007FFF
519 #define S_00B84C_EXCP_EN(x) (((x) & 0x7F) << 24)
520 #define G_00B84C_EXCP_EN(x) (((x) >> 24) & 0x7F)
521 #define C_00B84C_EXCP_EN
522 
523 #define R_0286CC_SPI_PS_INPUT_ENA 0x0286CC
524 #define R_0286D0_SPI_PS_INPUT_ADDR 0x0286D0
525 
526 #define R_00B848_COMPUTE_PGM_RSRC1 0x00B848
527 #define S_00B848_VGPRS(x) (((x) & 0x3F) << 0)
528 #define G_00B848_VGPRS(x) (((x) >> 0) & 0x3F)
529 #define C_00B848_VGPRS 0xFFFFFFC0
530 #define S_00B848_SGPRS(x) (((x) & 0x0F) << 6)
531 #define G_00B848_SGPRS(x) (((x) >> 6) & 0x0F)
532 #define C_00B848_SGPRS 0xFFFFFC3F
533 #define S_00B848_PRIORITY(x) (((x) & 0x03) << 10)
534 #define G_00B848_PRIORITY(x) (((x) >> 10) & 0x03)
535 #define C_00B848_PRIORITY 0xFFFFF3FF
536 #define S_00B848_FLOAT_MODE(x) (((x) & 0xFF) << 12)
537 #define G_00B848_FLOAT_MODE(x) (((x) >> 12) & 0xFF)
538 #define C_00B848_FLOAT_MODE 0xFFF00FFF
539 #define S_00B848_PRIV(x) (((x) & 0x1) << 20)
540 #define G_00B848_PRIV(x) (((x) >> 20) & 0x1)
541 #define C_00B848_PRIV 0xFFEFFFFF
542 #define S_00B848_DX10_CLAMP(x) (((x) & 0x1) << 21)
543 #define G_00B848_DX10_CLAMP(x) (((x) >> 21) & 0x1)
544 #define C_00B848_DX10_CLAMP 0xFFDFFFFF
545 #define S_00B848_DEBUG_MODE(x) (((x) & 0x1) << 22)
546 #define G_00B848_DEBUG_MODE(x) (((x) >> 22) & 0x1)
547 #define C_00B848_DEBUG_MODE 0xFFBFFFFF
548 #define S_00B848_IEEE_MODE(x) (((x) & 0x1) << 23)
549 #define G_00B848_IEEE_MODE(x) (((x) >> 23) & 0x1)
550 #define C_00B848_IEEE_MODE 0xFF7FFFFF
551 #define S_00B848_WGP_MODE(x) (((x) & 0x1) << 29)
552 #define G_00B848_WGP_MODE(x) (((x) >> 29) & 0x1)
553 #define C_00B848_WGP_MODE 0xDFFFFFFF
554 #define S_00B848_MEM_ORDERED(x) (((x) & 0x1) << 30)
555 #define G_00B848_MEM_ORDERED(x) (((x) >> 30) & 0x1)
556 #define C_00B848_MEM_ORDERED 0xBFFFFFFF
557 #define S_00B848_FWD_PROGRESS(x) (((x) & 0x1) << 31)
558 #define G_00B848_FWD_PROGRESS(x) (((x) >> 31) & 0x1)
559 #define C_00B848_FWD_PROGRESS 0x7FFFFFFF
560 
561 
562 // Helpers for setting FLOAT_MODE
563 #define FP_ROUND_ROUND_TO_NEAREST 0
564 #define FP_ROUND_ROUND_TO_INF 1
565 #define FP_ROUND_ROUND_TO_NEGINF 2
566 #define FP_ROUND_ROUND_TO_ZERO 3
567 
568 // Bits 3:0 control rounding mode. 1:0 control single precision, 3:2 double
569 // precision.
570 #define FP_ROUND_MODE_SP(x) ((x) & 0x3)
571 #define FP_ROUND_MODE_DP(x) (((x) & 0x3) << 2)
572 
573 #define FP_DENORM_FLUSH_IN_FLUSH_OUT 0
574 #define FP_DENORM_FLUSH_OUT 1
575 #define FP_DENORM_FLUSH_IN 2
576 #define FP_DENORM_FLUSH_NONE 3
577 
578 
579 // Bits 7:4 control denormal handling. 5:4 control single precision, 6:7 double
580 // precision.
581 #define FP_DENORM_MODE_SP(x) (((x) & 0x3) << 4)
582 #define FP_DENORM_MODE_DP(x) (((x) & 0x3) << 6)
583 
584 #define R_00B860_COMPUTE_TMPRING_SIZE 0x00B860
585 #define S_00B860_WAVESIZE(x) (((x) & 0x1FFF) << 12)
586 
587 #define R_0286E8_SPI_TMPRING_SIZE 0x0286E8
588 #define S_0286E8_WAVESIZE(x) (((x) & 0x1FFF) << 12)
589 
590 #define R_028B54_VGT_SHADER_STAGES_EN 0x028B54
591 #define S_028B54_HS_W32_EN(x) (((x) & 0x1) << 21)
592 #define S_028B54_GS_W32_EN(x) (((x) & 0x1) << 22)
593 #define S_028B54_VS_W32_EN(x) (((x) & 0x1) << 23)
594 #define R_0286D8_SPI_PS_IN_CONTROL 0x0286D8
595 #define S_0286D8_PS_W32_EN(x) (((x) & 0x1) << 15)
596 #define R_00B800_COMPUTE_DISPATCH_INITIATOR 0x00B800
597 #define S_00B800_CS_W32_EN(x) (((x) & 0x1) << 15)
598 
599 #define R_SPILLED_SGPRS 0x4
600 #define R_SPILLED_VGPRS 0x8
601 } // End namespace llvm
602 
603 #endif
This class represents lattice values for constants.
Definition: AllocatorList.h:23
Operand with 32-bit immediate that uses the constant bus.
Definition: SIDefines.h:153
static std::vector< std::pair< int, unsigned > > Swizzle(std::vector< std::pair< int, unsigned >> Src, R600InstrInfo::BankSwizzle Swz)
Operands with register or 32-bit immediate.
Definition: SIDefines.h:118
Operands with register or inline constant.
Definition: SIDefines.h:128