LLVM  6.0.0svn
SIDefines.h
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1 //===-- SIDefines.h - SI Helper Macros ----------------------*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 /// \file
9 //===----------------------------------------------------------------------===//
10 
11 #include "llvm/MC/MCInstrDesc.h"
12 
13 #ifndef LLVM_LIB_TARGET_AMDGPU_SIDEFINES_H
14 #define LLVM_LIB_TARGET_AMDGPU_SIDEFINES_H
15 
16 namespace llvm {
17 
18 namespace SIInstrFlags {
19 // This needs to be kept in sync with the field bits in InstSI.
20 enum : uint64_t {
21  // Low bits - basic encoding information.
22  SALU = 1 << 0,
23  VALU = 1 << 1,
24 
25  // SALU instruction formats.
26  SOP1 = 1 << 2,
27  SOP2 = 1 << 3,
28  SOPC = 1 << 4,
29  SOPK = 1 << 5,
30  SOPP = 1 << 6,
31 
32  // VALU instruction formats.
33  VOP1 = 1 << 7,
34  VOP2 = 1 << 8,
35  VOPC = 1 << 9,
36 
37  // TODO: Should this be spilt into VOP3 a and b?
38  VOP3 = 1 << 10,
39  VOP3P = 1 << 12,
40 
41  VINTRP = 1 << 13,
42  SDWA = 1 << 14,
43  DPP = 1 << 15,
44 
45  // Memory instruction formats.
46  MUBUF = 1 << 16,
47  MTBUF = 1 << 17,
48  SMRD = 1 << 18,
49  MIMG = 1 << 19,
50  EXP = 1 << 20,
51  FLAT = 1 << 21,
52  DS = 1 << 22,
53 
54  // Pseudo instruction formats.
55  VGPRSpill = 1 << 23,
56  SGPRSpill = 1 << 24,
57 
58  // High bits - other information.
59  VM_CNT = UINT64_C(1) << 32,
60  EXP_CNT = UINT64_C(1) << 33,
61  LGKM_CNT = UINT64_C(1) << 34,
62 
63  WQM = UINT64_C(1) << 35,
64  DisableWQM = UINT64_C(1) << 36,
65  Gather4 = UINT64_C(1) << 37,
66  SOPK_ZEXT = UINT64_C(1) << 38,
67  SCALAR_STORE = UINT64_C(1) << 39,
68  FIXED_SIZE = UINT64_C(1) << 40,
69  VOPAsmPrefer32Bit = UINT64_C(1) << 41,
70  VOP3_OPSEL = UINT64_C(1) << 42,
71  maybeAtomic = UINT64_C(1) << 43,
72  renamedInGFX9 = UINT64_C(1) << 44,
73 
74  // Is a clamp on FP type.
75  FPClamp = UINT64_C(1) << 45,
76 
77  // Is an integer clamp
78  IntClamp = UINT64_C(1) << 46,
79 
80  // Clamps lo component of register.
81  ClampLo = UINT64_C(1) << 47,
82 
83  // Clamps hi component of register.
84  // ClampLo and ClampHi set for packed clamp.
85  ClampHi = UINT64_C(1) << 48,
86 
87  // Is a packed VOP3P instruction.
88  IsPacked = UINT64_C(1) << 49
89 };
90 
91 // v_cmp_class_* etc. use a 10-bit mask for what operation is checked.
92 // The result is true if any of these tests are true.
93 enum ClassFlags {
94  S_NAN = 1 << 0, // Signaling NaN
95  Q_NAN = 1 << 1, // Quiet NaN
96  N_INFINITY = 1 << 2, // Negative infinity
97  N_NORMAL = 1 << 3, // Negative normal
98  N_SUBNORMAL = 1 << 4, // Negative subnormal
99  N_ZERO = 1 << 5, // Negative zero
100  P_ZERO = 1 << 6, // Positive zero
101  P_SUBNORMAL = 1 << 7, // Positive subnormal
102  P_NORMAL = 1 << 8, // Positive normal
103  P_INFINITY = 1 << 9 // Positive infinity
104 };
105 }
106 
107 namespace AMDGPU {
108  enum OperandType {
109  /// Operands with register or 32-bit immediate
116 
117  /// Operands with register or inline constant
126 
129 
132 
135 
136  // Operand for source modifiers for VOP instructions
138 
139  // Operand for SDWA instructions
142 
143  /// Operand with 32-bit immediate that uses the constant bus.
146  };
147 }
148 
149 // Input operand modifiers bit-masks
150 // NEG and SEXT share same bit-mask because they can't be set simultaneously.
151 namespace SISrcMods {
152  enum {
153  NEG = 1 << 0, // Floating-point negate modifier
154  ABS = 1 << 1, // Floating-point absolute modifier
155  SEXT = 1 << 0, // Integer sign-extend modifier
156  NEG_HI = ABS, // Floating-point negate high packed component modifier.
157  OP_SEL_0 = 1 << 2,
158  OP_SEL_1 = 1 << 3,
159  DST_OP_SEL = 1 << 3 // VOP3 dst op_sel (share mask with OP_SEL_1)
160  };
161 }
162 
163 namespace SIOutMods {
164  enum {
165  NONE = 0,
166  MUL2 = 1,
167  MUL4 = 2,
168  DIV2 = 3
169  };
170 }
171 
172 namespace VGPRIndexMode {
173  enum {
174  SRC0_ENABLE = 1 << 0,
175  SRC1_ENABLE = 1 << 1,
176  SRC2_ENABLE = 1 << 2,
177  DST_ENABLE = 1 << 3
178  };
179 }
180 
181 namespace AMDGPUAsmVariants {
182  enum {
183  DEFAULT = 0,
184  VOP3 = 1,
185  SDWA = 2,
186  SDWA9 = 3,
187  DPP = 4
188  };
189 }
190 
191 namespace AMDGPU {
192 namespace EncValues { // Encoding values of enum9/8/7 operands
193 
194 enum {
195  SGPR_MIN = 0,
196  SGPR_MAX = 101,
197  TTMP_MIN = 112,
198  TTMP_MAX = 123,
205  VGPR_MIN = 256,
206  VGPR_MAX = 511
207 };
208 
209 } // namespace EncValues
210 } // namespace AMDGPU
211 
212 namespace AMDGPU {
213 namespace SendMsg { // Encoding of SIMM16 used in s_sendmsg* insns.
214 
215 enum Id { // Message ID, width(4) [3:0].
220  ID_SYSMSG = 15,
221  ID_GAPS_LAST_, // Indicate that sequence has gaps.
225  ID_MASK_ = (((1 << ID_WIDTH_) - 1) << ID_SHIFT_)
226 };
227 
228 enum Op { // Both GS and SYS operation IDs.
231  // width(2) [5:4]
239  OP_GS_MASK_ = (((1 << OP_GS_WIDTH_) - 1) << OP_SHIFT_),
240  // width(3) [6:4]
249 };
250 
251 enum StreamId { // Stream ID, (2) [9:8].
258 };
259 
260 } // namespace SendMsg
261 
262 namespace Hwreg { // Encoding of SIMM16 used in s_setreg/getreg* insns.
263 
264 enum Id { // HwRegCode, (6) [5:0]
266  ID_SYMBOLIC_FIRST_ = 1, // There are corresponding symbolic names defined.
267  ID_MODE = 1,
270  ID_HW_ID = 4,
278  ID_MASK_ = (((1 << ID_WIDTH_) - 1) << ID_SHIFT_)
279 };
280 
281 enum Offset { // Offset, (5) [10:6]
286 
289 };
290 
291 enum WidthMinusOne { // WidthMinusOne, (5) [15:11]
296 
299 };
300 
301 } // namespace Hwreg
302 
303 namespace Swizzle { // Encoding of swizzle macro used in ds_swizzle_b32.
304 
305 enum Id { // id of symbolic names
311 };
312 
313 enum EncBits {
314 
315  // swizzle mode encodings
316 
317  QUAD_PERM_ENC = 0x8000,
319 
322 
323  // QUAD_PERM encodings
324 
325  LANE_MASK = 0x3,
328  LANE_NUM = 4,
329 
330  // BITMASK_PERM encodings
331 
332  BITMASK_MASK = 0x1F,
335 
339 };
340 
341 } // namespace Swizzle
342 
343 namespace SDWA {
344 
345 enum SdwaSel {
346  BYTE_0 = 0,
347  BYTE_1 = 1,
348  BYTE_2 = 2,
349  BYTE_3 = 3,
350  WORD_0 = 4,
351  WORD_1 = 5,
352  DWORD = 6,
353 };
354 
355 enum DstUnused {
359 };
360 
362  SRC_SGPR_MASK = 0x100,
366 
371 };
372 
373 } // namespace SDWA
374 } // namespace AMDGPU
375 
376 #define R_00B028_SPI_SHADER_PGM_RSRC1_PS 0x00B028
377 #define R_00B02C_SPI_SHADER_PGM_RSRC2_PS 0x00B02C
378 #define S_00B02C_EXTRA_LDS_SIZE(x) (((x) & 0xFF) << 8)
379 #define R_00B128_SPI_SHADER_PGM_RSRC1_VS 0x00B128
380 #define R_00B228_SPI_SHADER_PGM_RSRC1_GS 0x00B228
381 #define R_00B328_SPI_SHADER_PGM_RSRC1_ES 0x00B328
382 #define R_00B428_SPI_SHADER_PGM_RSRC1_HS 0x00B428
383 #define R_00B528_SPI_SHADER_PGM_RSRC1_LS 0x00B528
384 #define R_00B848_COMPUTE_PGM_RSRC1 0x00B848
385 #define S_00B028_VGPRS(x) (((x) & 0x3F) << 0)
386 #define S_00B028_SGPRS(x) (((x) & 0x0F) << 6)
387 
388 #define R_00B84C_COMPUTE_PGM_RSRC2 0x00B84C
389 #define S_00B84C_SCRATCH_EN(x) (((x) & 0x1) << 0)
390 #define G_00B84C_SCRATCH_EN(x) (((x) >> 0) & 0x1)
391 #define C_00B84C_SCRATCH_EN 0xFFFFFFFE
392 #define S_00B84C_USER_SGPR(x) (((x) & 0x1F) << 1)
393 #define G_00B84C_USER_SGPR(x) (((x) >> 1) & 0x1F)
394 #define C_00B84C_USER_SGPR 0xFFFFFFC1
395 #define S_00B84C_TRAP_HANDLER(x) (((x) & 0x1) << 6)
396 #define G_00B84C_TRAP_HANDLER(x) (((x) >> 6) & 0x1)
397 #define C_00B84C_TRAP_HANDLER 0xFFFFFFBF
398 #define S_00B84C_TGID_X_EN(x) (((x) & 0x1) << 7)
399 #define G_00B84C_TGID_X_EN(x) (((x) >> 7) & 0x1)
400 #define C_00B84C_TGID_X_EN 0xFFFFFF7F
401 #define S_00B84C_TGID_Y_EN(x) (((x) & 0x1) << 8)
402 #define G_00B84C_TGID_Y_EN(x) (((x) >> 8) & 0x1)
403 #define C_00B84C_TGID_Y_EN 0xFFFFFEFF
404 #define S_00B84C_TGID_Z_EN(x) (((x) & 0x1) << 9)
405 #define G_00B84C_TGID_Z_EN(x) (((x) >> 9) & 0x1)
406 #define C_00B84C_TGID_Z_EN 0xFFFFFDFF
407 #define S_00B84C_TG_SIZE_EN(x) (((x) & 0x1) << 10)
408 #define G_00B84C_TG_SIZE_EN(x) (((x) >> 10) & 0x1)
409 #define C_00B84C_TG_SIZE_EN 0xFFFFFBFF
410 #define S_00B84C_TIDIG_COMP_CNT(x) (((x) & 0x03) << 11)
411 #define G_00B84C_TIDIG_COMP_CNT(x) (((x) >> 11) & 0x03)
412 #define C_00B84C_TIDIG_COMP_CNT 0xFFFFE7FF
413 /* CIK */
414 #define S_00B84C_EXCP_EN_MSB(x) (((x) & 0x03) << 13)
415 #define G_00B84C_EXCP_EN_MSB(x) (((x) >> 13) & 0x03)
416 #define C_00B84C_EXCP_EN_MSB 0xFFFF9FFF
417 /* */
418 #define S_00B84C_LDS_SIZE(x) (((x) & 0x1FF) << 15)
419 #define G_00B84C_LDS_SIZE(x) (((x) >> 15) & 0x1FF)
420 #define C_00B84C_LDS_SIZE 0xFF007FFF
421 #define S_00B84C_EXCP_EN(x) (((x) & 0x7F) << 24)
422 #define G_00B84C_EXCP_EN(x) (((x) >> 24) & 0x7F)
423 #define C_00B84C_EXCP_EN
424 
425 #define R_0286CC_SPI_PS_INPUT_ENA 0x0286CC
426 #define R_0286D0_SPI_PS_INPUT_ADDR 0x0286D0
427 
428 #define R_00B848_COMPUTE_PGM_RSRC1 0x00B848
429 #define S_00B848_VGPRS(x) (((x) & 0x3F) << 0)
430 #define G_00B848_VGPRS(x) (((x) >> 0) & 0x3F)
431 #define C_00B848_VGPRS 0xFFFFFFC0
432 #define S_00B848_SGPRS(x) (((x) & 0x0F) << 6)
433 #define G_00B848_SGPRS(x) (((x) >> 6) & 0x0F)
434 #define C_00B848_SGPRS 0xFFFFFC3F
435 #define S_00B848_PRIORITY(x) (((x) & 0x03) << 10)
436 #define G_00B848_PRIORITY(x) (((x) >> 10) & 0x03)
437 #define C_00B848_PRIORITY 0xFFFFF3FF
438 #define S_00B848_FLOAT_MODE(x) (((x) & 0xFF) << 12)
439 #define G_00B848_FLOAT_MODE(x) (((x) >> 12) & 0xFF)
440 #define C_00B848_FLOAT_MODE 0xFFF00FFF
441 #define S_00B848_PRIV(x) (((x) & 0x1) << 20)
442 #define G_00B848_PRIV(x) (((x) >> 20) & 0x1)
443 #define C_00B848_PRIV 0xFFEFFFFF
444 #define S_00B848_DX10_CLAMP(x) (((x) & 0x1) << 21)
445 #define G_00B848_DX10_CLAMP(x) (((x) >> 21) & 0x1)
446 #define C_00B848_DX10_CLAMP 0xFFDFFFFF
447 #define S_00B848_DEBUG_MODE(x) (((x) & 0x1) << 22)
448 #define G_00B848_DEBUG_MODE(x) (((x) >> 22) & 0x1)
449 #define C_00B848_DEBUG_MODE 0xFFBFFFFF
450 #define S_00B848_IEEE_MODE(x) (((x) & 0x1) << 23)
451 #define G_00B848_IEEE_MODE(x) (((x) >> 23) & 0x1)
452 #define C_00B848_IEEE_MODE 0xFF7FFFFF
453 
454 
455 // Helpers for setting FLOAT_MODE
456 #define FP_ROUND_ROUND_TO_NEAREST 0
457 #define FP_ROUND_ROUND_TO_INF 1
458 #define FP_ROUND_ROUND_TO_NEGINF 2
459 #define FP_ROUND_ROUND_TO_ZERO 3
460 
461 // Bits 3:0 control rounding mode. 1:0 control single precision, 3:2 double
462 // precision.
463 #define FP_ROUND_MODE_SP(x) ((x) & 0x3)
464 #define FP_ROUND_MODE_DP(x) (((x) & 0x3) << 2)
465 
466 #define FP_DENORM_FLUSH_IN_FLUSH_OUT 0
467 #define FP_DENORM_FLUSH_OUT 1
468 #define FP_DENORM_FLUSH_IN 2
469 #define FP_DENORM_FLUSH_NONE 3
470 
471 
472 // Bits 7:4 control denormal handling. 5:4 control single precision, 6:7 double
473 // precision.
474 #define FP_DENORM_MODE_SP(x) (((x) & 0x3) << 4)
475 #define FP_DENORM_MODE_DP(x) (((x) & 0x3) << 6)
476 
477 #define R_00B860_COMPUTE_TMPRING_SIZE 0x00B860
478 #define S_00B860_WAVESIZE(x) (((x) & 0x1FFF) << 12)
479 
480 #define R_0286E8_SPI_TMPRING_SIZE 0x0286E8
481 #define S_0286E8_WAVESIZE(x) (((x) & 0x1FFF) << 12)
482 
483 #define R_SPILLED_SGPRS 0x4
484 #define R_SPILLED_VGPRS 0x8
485 } // End namespace llvm
486 
487 #endif
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
static std::vector< std::pair< int, unsigned > > Swizzle(std::vector< std::pair< int, unsigned >> Src, R600InstrInfo::BankSwizzle Swz)
Operands with register or inline constant.
Definition: SIDefines.h:118
Operands with register or 32-bit immediate.
Definition: SIDefines.h:110
Operand with 32-bit immediate that uses the constant bus.
Definition: SIDefines.h:144