46 #define GET_INSTRINFO_CTOR_DTOR 47 #include "R600GenDFAPacketizer.inc" 49 #define GET_INSTRINFO_CTOR_DTOR 50 #define GET_INSTRMAP_INFO 51 #define GET_INSTRINFO_NAMED_OPS 52 #include "R600GenInstrInfo.inc" 63 const DebugLoc &DL,
unsigned DestReg,
64 unsigned SrcReg,
bool KillSrc)
const {
65 unsigned VectorComponents = 0;
66 if ((R600::R600_Reg128RegClass.
contains(DestReg) ||
67 R600::R600_Reg128VerticalRegClass.
contains(DestReg)) &&
68 (R600::R600_Reg128RegClass.
contains(SrcReg) ||
69 R600::R600_Reg128VerticalRegClass.
contains(SrcReg))) {
71 }
else if((R600::R600_Reg64RegClass.
contains(DestReg) ||
72 R600::R600_Reg64VerticalRegClass.
contains(DestReg)) &&
73 (R600::R600_Reg64RegClass.
contains(SrcReg) ||
74 R600::R600_Reg64VerticalRegClass.
contains(SrcReg))) {
78 if (VectorComponents > 0) {
79 for (
unsigned I = 0;
I < VectorComponents;
I++) {
82 RI.getSubReg(DestReg, SubRegIndex),
83 RI.getSubReg(SrcReg, SubRegIndex))
99 E = MBBI->operands_end();
I !=
E; ++
I) {
112 case R600::MOV_IMM_F32:
113 case R600::MOV_IMM_I32:
124 default:
return false;
125 case R600::CUBE_r600_pseudo:
126 case R600::CUBE_r600_real:
127 case R600::CUBE_eg_pseudo:
128 case R600::CUBE_eg_real:
166 case R600::INTERP_PAIR_XY:
167 case R600::INTERP_PAIR_ZW:
168 case R600::INTERP_VEC_LOAD:
180 return (
get(Opcode).getSchedClass() == R600::Sched::TransALU);
188 return (
get(Opcode).getSchedClass() == R600::Sched::VecALU);
223 case R600::GROUP_BARRIER:
245 if (!
I->isReg() || !
I->isUse() ||
249 if (R600::R600_LDS_SRC_REGRegClass.
contains(
I->getReg()))
256 static const unsigned SrcSelTable[][2] = {
257 {R600::OpName::src0, R600::OpName::src0_sel},
258 {R600::OpName::src1, R600::OpName::src1_sel},
259 {R600::OpName::src2, R600::OpName::src2_sel},
260 {R600::OpName::src0_X, R600::OpName::src0_sel_X},
261 {R600::OpName::src0_Y, R600::OpName::src0_sel_Y},
262 {R600::OpName::src0_Z, R600::OpName::src0_sel_Z},
263 {R600::OpName::src0_W, R600::OpName::src0_sel_W},
264 {R600::OpName::src1_X, R600::OpName::src1_sel_X},
265 {R600::OpName::src1_Y, R600::OpName::src1_sel_Y},
266 {R600::OpName::src1_Z, R600::OpName::src1_sel_Z},
267 {R600::OpName::src1_W, R600::OpName::src1_sel_W}
270 for (
const auto &Row : SrcSelTable) {
283 static const unsigned OpTable[8][2] = {
284 {R600::OpName::src0_X, R600::OpName::src0_sel_X},
285 {R600::OpName::src0_Y, R600::OpName::src0_sel_Y},
286 {R600::OpName::src0_Z, R600::OpName::src0_sel_Z},
287 {R600::OpName::src0_W, R600::OpName::src0_sel_W},
288 {R600::OpName::src1_X, R600::OpName::src1_sel_X},
289 {R600::OpName::src1_Y, R600::OpName::src1_sel_Y},
290 {R600::OpName::src1_Z, R600::OpName::src1_sel_Z},
291 {R600::OpName::src1_W, R600::OpName::src1_sel_W},
294 for (
unsigned j = 0; j < 8; j++) {
298 if (Reg == R600::ALU_CONST) {
309 static const unsigned OpTable[3][2] = {
310 {R600::OpName::src0, R600::OpName::src0_sel},
311 {R600::OpName::src1, R600::OpName::src1_sel},
312 {R600::OpName::src2, R600::OpName::src2_sel},
315 for (
unsigned j = 0; j < 3; j++) {
321 if (Reg == R600::ALU_CONST) {
327 if (Reg == R600::ALU_LITERAL_X) {
330 if (Operand.
isImm()) {
336 Result.
push_back(std::make_pair(&MO, 0));
341 std::vector<std::pair<int, unsigned>>
344 unsigned &ConstCount)
const {
346 const std::pair<int, unsigned> DummyPair(-1, 0);
347 std::vector<std::pair<int, unsigned>> Result;
349 for (
const auto &Src :
getSrcs(MI)) {
351 unsigned Reg = Src.first->getReg();
352 int Index = RI.getEncodingValue(Reg) & 0xff;
353 if (Reg == R600::OQAP) {
354 Result.push_back(std::make_pair(Index, 0U));
356 if (PV.
find(Reg) != PV.
end()) {
358 Result.push_back(std::make_pair(255, 0U));
363 Result.push_back(DummyPair);
367 Result.push_back(std::make_pair(Index, Chan));
370 Result.push_back(DummyPair);
374 static std::vector<std::pair<int, unsigned>>
375 Swizzle(std::vector<std::pair<int, unsigned>> Src,
377 if (Src[0] == Src[1])
406 unsigned Cycles[3] = { 2, 1, 0};
410 unsigned Cycles[3] = { 1, 2, 2};
414 unsigned Cycles[3] = { 2, 1, 2};
418 unsigned Cycles[3] = { 2, 2, 1};
430 const std::vector<std::vector<std::pair<int, unsigned>>> &IGSrcs,
431 const std::vector<R600InstrInfo::BankSwizzle> &Swz,
432 const std::vector<std::pair<int, unsigned>> &TransSrcs,
435 memset(Vector, -1,
sizeof(Vector));
436 for (
unsigned i = 0, e = IGSrcs.size(); i < e; i++) {
437 const std::vector<std::pair<int, unsigned>> &Srcs =
439 for (
unsigned j = 0; j < 3; j++) {
440 const std::pair<int, unsigned> &Src = Srcs[j];
441 if (Src.first < 0 || Src.first == 255)
443 if (Src.first ==
GET_REG_INDEX(RI.getEncodingValue(R600::OQAP))) {
453 if (Vector[Src.second][j] < 0)
454 Vector[Src.second][j] = Src.first;
455 if (Vector[Src.second][j] != Src.first)
460 for (
unsigned i = 0, e = TransSrcs.size(); i < e; ++i) {
461 const std::pair<int, unsigned> &Src = TransSrcs[i];
465 if (Src.first == 255)
467 if (Vector[Src.second][Cycle] < 0)
468 Vector[Src.second][Cycle] = Src.first;
469 if (Vector[Src.second][Cycle] != Src.first)
470 return IGSrcs.size() - 1;
472 return IGSrcs.size();
480 std::vector<R600InstrInfo::BankSwizzle> &SwzCandidate,
482 assert(Idx < SwzCandidate.size());
486 for (
unsigned i = ResetIdx + 1, e = SwzCandidate.size(); i < e; i++) {
491 int NextSwizzle = SwzCandidate[ResetIdx] + 1;
499 const std::vector<std::vector<std::pair<int, unsigned>>> &IGSrcs,
500 std::vector<R600InstrInfo::BankSwizzle> &SwzCandidate,
501 const std::vector<std::pair<int, unsigned>> &TransSrcs,
503 unsigned ValidUpTo = 0;
505 ValidUpTo =
isLegalUpTo(IGSrcs, SwzCandidate, TransSrcs, TransSwz);
506 if (ValidUpTo == IGSrcs.size())
516 const std::vector<std::pair<int, unsigned>> &TransOps,
517 unsigned ConstCount) {
521 for (
unsigned i = 0, e = TransOps.size(); i < e; ++i) {
522 const std::pair<int, unsigned> &Src = TransOps[i];
526 if (ConstCount > 0 && Cycle == 0)
528 if (ConstCount > 1 && Cycle == 1)
537 std::vector<BankSwizzle> &ValidSwizzle,
542 std::vector<std::vector<std::pair<int, unsigned>>> IGSrcs;
543 ValidSwizzle.clear();
546 for (
unsigned i = 0, e = IG.size(); i < e; ++i) {
547 IGSrcs.push_back(ExtractSrcs(*IG[i], PV, ConstCount));
549 R600::OpName::bank_swizzle);
551 IG[i]->getOperand(Op).getImm());
553 std::vector<std::pair<int, unsigned>> TransOps;
557 TransOps = std::move(IGSrcs.back());
559 ValidSwizzle.pop_back();
567 for (
unsigned i = 0; i < 4; i++) {
568 TransBS = TransSwz[i];
574 ValidSwizzle.push_back(TransBS);
585 assert (Consts.size() <= 12 &&
"Too many operands in instructions group");
586 unsigned Pair1 = 0, Pair2 = 0;
587 for (
unsigned i = 0, n = Consts.size(); i < n; ++i) {
588 unsigned ReadConstHalf = Consts[i] & 2;
589 unsigned ReadConstIndex = Consts[i] & (~3);
590 unsigned ReadHalfConst = ReadConstIndex | ReadConstHalf;
592 Pair1 = ReadHalfConst;
595 if (Pair1 == ReadHalfConst)
598 Pair2 = ReadHalfConst;
601 if (Pair2 != ReadHalfConst)
610 std::vector<unsigned> Consts;
612 for (
unsigned i = 0, n = MIs.size(); i < n; i++) {
617 for (
const auto &Src :
getSrcs(MI)) {
618 if (Src.first->getReg() == R600::ALU_LITERAL_X)
619 Literals.
insert(Src.second);
620 if (Literals.
size() > 4)
622 if (Src.first->getReg() == R600::ALU_CONST)
623 Consts.push_back(Src.second);
624 if (R600::R600_KC0RegClass.
contains(Src.first->getReg()) ||
625 R600::R600_KC1RegClass.
contains(Src.first->getReg())) {
626 unsigned Index = RI.getEncodingValue(Src.first->getReg()) & 0xff;
628 Consts.push_back((Index << 2) | Chan);
638 return static_cast<const R600Subtarget &
>(STI).createDFAPacketizer(II);
654 while (I != MBB.
begin()) {
666 return Opcode == R600::JUMP || Opcode == R600::JUMP_COND;
670 return Opcode == R600::BRANCH || Opcode == R600::BRANCH_COND_i32 ||
671 Opcode == R600::BRANCH_COND_f32;
678 bool AllowModify)
const {
690 if (!
isJump(I->getOpcode())) {
695 while (I != MBB.
begin() && std::prev(I)->getOpcode() == R600::JUMP) {
698 I->removeFromParent();
706 if (LastOpc == R600::JUMP) {
709 }
else if (LastOpc == R600::JUMP_COND) {
725 unsigned SecondLastOpc = SecondLastInst.
getOpcode();
728 if (SecondLastOpc == R600::JUMP_COND && LastOpc == R600::JUMP) {
749 if (It->getOpcode() == R600::CF_ALU ||
750 It->getOpcode() == R600::CF_ALU_PUSH_BEFORE)
761 int *BytesAdded)
const {
762 assert(TBB &&
"insertBranch must not be told to insert a fallthrough");
763 assert(!BytesAdded &&
"code size not handled");
771 assert(PredSet &&
"No previous predicate !");
775 BuildMI(&MBB, DL,
get(R600::JUMP_COND))
779 if (CfAlu == MBB.
end())
781 assert (CfAlu->getOpcode() == R600::CF_ALU);
782 CfAlu->setDesc(
get(R600::CF_ALU_PUSH_BEFORE));
787 assert(PredSet &&
"No previous predicate !");
790 BuildMI(&MBB, DL,
get(R600::JUMP_COND))
795 if (CfAlu == MBB.
end())
797 assert (CfAlu->getOpcode() == R600::CF_ALU);
798 CfAlu->setDesc(
get(R600::CF_ALU_PUSH_BEFORE));
804 int *BytesRemoved)
const {
805 assert(!BytesRemoved &&
"code size not handled");
812 if (I == MBB.
begin()) {
816 switch (I->getOpcode()) {
819 case R600::JUMP_COND: {
822 I->eraseFromParent();
824 if (CfAlu == MBB.
end())
826 assert (CfAlu->getOpcode() == R600::CF_ALU_PUSH_BEFORE);
827 CfAlu->setDesc(
get(R600::CF_ALU));
831 I->eraseFromParent();
836 if (I == MBB.
begin()) {
840 switch (I->getOpcode()) {
844 case R600::JUMP_COND: {
847 I->eraseFromParent();
849 if (CfAlu == MBB.
end())
851 assert (CfAlu->getOpcode() == R600::CF_ALU_PUSH_BEFORE);
852 CfAlu->setDesc(
get(R600::CF_ALU));
856 I->eraseFromParent();
869 default:
return false;
870 case R600::PRED_SEL_ONE:
871 case R600::PRED_SEL_ZERO:
872 case R600::PREDICATE_BIT:
885 }
else if (MI.
getOpcode() == R600::CF_ALU) {
902 unsigned ExtraPredCycles,
910 unsigned ExtraTCycles,
913 unsigned ExtraFCycles,
936 case R600::PRED_SETE_INT:
937 MO.
setImm(R600::PRED_SETNE_INT);
939 case R600::PRED_SETNE_INT:
940 MO.
setImm(R600::PRED_SETE_INT);
942 case R600::PRED_SETE:
943 MO.
setImm(R600::PRED_SETNE);
945 case R600::PRED_SETNE:
946 MO.
setImm(R600::PRED_SETE);
954 case R600::PRED_SEL_ZERO:
955 MO2.
setReg(R600::PRED_SEL_ONE);
957 case R600::PRED_SEL_ONE:
958 MO2.
setReg(R600::PRED_SEL_ZERO);
967 std::vector<MachineOperand> &Pred)
const {
1011 unsigned *PredCost)
const {
1018 unsigned Channel)
const {
1031 int RegOpIdx = OffsetOpIdx + 1;
1041 if (OffsetReg == R600::INDIRECT_BASE_ADDR) {
1055 if (OffsetReg == R600::INDIRECT_BASE_ADDR) {
1070 case R600::R600_EXTRACT_ELT_V2:
1071 case R600::R600_EXTRACT_ELT_V4:
1077 case R600::R600_INSERT_ELT_V2:
1078 case R600::R600_INSERT_ELT_V4:
1102 for (
unsigned Chan = 0; Chan < StackWidth; ++Chan) {
1103 unsigned Reg = R600::R600_TReg32RegClass.getRegister((4 *
Index) + Chan);
1110 return &R600::R600_TReg32_XRegClass;
1115 unsigned ValueReg,
unsigned Address,
1116 unsigned OffsetReg)
const {
1117 return buildIndirectWrite(MBB, I, ValueReg, Address, OffsetReg, 0);
1122 unsigned ValueReg,
unsigned Address,
1124 unsigned AddrChan)
const {
1128 case 0: AddrReg = R600::R600_AddrRegClass.getRegister(Address);
break;
1129 case 1: AddrReg = R600::R600_Addr_YRegClass.getRegister(Address);
break;
1130 case 2: AddrReg = R600::R600_Addr_ZRegClass.getRegister(Address);
break;
1131 case 3: AddrReg = R600::R600_Addr_WRegClass.getRegister(Address);
break;
1134 R600::AR_X, OffsetReg);
1147 unsigned ValueReg,
unsigned Address,
1148 unsigned OffsetReg)
const {
1149 return buildIndirectRead(MBB, I, ValueReg, Address, OffsetReg, 0);
1154 unsigned ValueReg,
unsigned Address,
1156 unsigned AddrChan)
const {
1160 case 0: AddrReg = R600::R600_AddrRegClass.getRegister(Address);
break;
1161 case 1: AddrReg = R600::R600_Addr_YRegClass.getRegister(Address);
break;
1162 case 2: AddrReg = R600::R600_Addr_ZRegClass.getRegister(Address);
break;
1163 case 3: AddrReg = R600::R600_Addr_WRegClass.getRegister(Address);
break;
1193 for (std::pair<unsigned, unsigned> LI : MRI.
liveins()) {
1194 unsigned Reg = LI.first;
1201 for (RegIndex = 0, RegEnd = IndirectRC->
getNumRegs(); RegIndex != RegEnd;
1206 Offset =
std::max(Offset, (
int)RegIndex);
1228 unsigned IgnoredFrameReg;
1243 unsigned Src1Reg)
const {
1272 .
addReg(R600::PRED_SEL_OFF)
1279 #define OPERAND_CASE(Label) \ 1281 static const unsigned Ops[] = \ 1323 Opcode = R600::DOT4_r600;
1325 Opcode = R600::DOT4_eg;
1333 static const unsigned Operands[14] = {
1334 R600::OpName::update_exec_mask,
1335 R600::OpName::update_pred,
1338 R600::OpName::dst_rel,
1339 R600::OpName::clamp,
1340 R600::OpName::src0_neg,
1341 R600::OpName::src0_rel,
1342 R600::OpName::src0_abs,
1343 R600::OpName::src0_sel,
1344 R600::OpName::src1_neg,
1345 R600::OpName::src1_rel,
1346 R600::OpName::src1_abs,
1347 R600::OpName::src1_sel,
1355 for (
unsigned i = 0; i < 14; i++) {
1368 uint64_t Imm)
const {
1370 R600::ALU_LITERAL_X);
1377 unsigned DstReg,
unsigned SrcReg)
const {
1390 int64_t Imm)
const {
1392 assert(Idx != -1 &&
"Operand not supported for this instruction.");
1402 unsigned Flag)
const {
1437 assert(!IsOP3 &&
"Cannot set absolute value modifier for OP3 " 1454 assert(FlagIndex != -1 &&
"Flag not supported for this instruction");
1458 "Instruction flags not supported for this instruction");
1467 unsigned Flag)
const {
1488 unsigned Flag)
const {
1495 unsigned InstFlags = FlagOp.
getImm();
1497 FlagOp.
setImm(InstFlags);
1502 unsigned Kind)
const {
bool isMov(unsigned Opcode) const
bool usesAddressRegister(MachineInstr &MI) const
mop_iterator operands_end()
static unsigned getSubRegFromChannel(unsigned Channel)
unsigned int getPredicationCost(const MachineInstr &) const override
GCNRegPressure max(const GCNRegPressure &P1, const GCNRegPressure &P2)
bool contains(unsigned Reg) const
Return true if the specified register is included in this register class.
int findFirstPredOperandIdx() const
Find the index of the first operand in the operand list that is used to represent the predicate...
AMDGPU specific subclass of TargetSubtarget.
MachineBasicBlock * getMBB() const
bool livein_empty() const
This class represents lattice values for constants.
unsigned getNumRegs() const
Return the number of registers in this class.
unsigned getNumObjects() const
Return the number of objects.
Interface definition for R600InstrInfo.
void addFlag(MachineInstr &MI, unsigned Operand, unsigned Flag) const
Add one of the MO_FLAG* flags to the specified Operand.
bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, BranchProbability Probability) const override
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
unsigned getRegister(unsigned i) const
Return the specified register in the class.
void push_back(const T &Elt)
bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, unsigned ExtraPredCycles, BranchProbability Probability) const override
unsigned getReg() const
getReg - Returns the register number.
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
unsigned isLegalUpTo(const std::vector< std::vector< std::pair< int, unsigned > > > &IGSrcs, const std::vector< R600InstrInfo::BankSwizzle > &Swz, const std::vector< std::pair< int, unsigned > > &TransSrcs, R600InstrInfo::BankSwizzle TransSwz) const
returns how many MIs (whose inputs are represented by IGSrcs) can be packed in the same Instruction G...
static std::vector< std::pair< int, unsigned > > Swizzle(std::vector< std::pair< int, unsigned >> Src, R600InstrInfo::BankSwizzle Swz)
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const override
bool isPredicated(const MachineInstr &MI) const override
static unsigned getSlotedOps(unsigned Op, unsigned Slot)
void clearFlag(MachineInstr &MI, unsigned Operand, unsigned Flag) const
Clear the specified flag on the instruction.
bool expandPostRAPseudo(MachineInstr &MI) const override
unsigned const TargetRegisterInfo * TRI
MachineInstr * buildSlotOfVectorInstruction(MachineBasicBlock &MBB, MachineInstr *MI, unsigned Slot, unsigned DstReg) const
MachineInstrBundleIterator< const MachineInstr > const_iterator
Interface definition for R600RegisterInfo.
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
Generation getGeneration() const
return AArch64::GPR64RegClass contains(Reg)
static MachineOperand CreateReg(unsigned Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false, bool isRenamable=false)
LLVM_READONLY int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx)
unsigned int getInstrLatency(const InstrItineraryData *ItinData, const MachineInstr &MI, unsigned *PredCost=nullptr) const override
static MachineBasicBlock::iterator FindLastAluClause(MachineBasicBlock &MBB)
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
Address space for constant memory (VTX2)
static unsigned getTransSwizzle(R600InstrInfo::BankSwizzle Swz, unsigned Op)
R600InstrInfo(const R600Subtarget &)
int getFrameIndexReference(const MachineFunction &MF, int FI, unsigned &FrameReg) const override
static Optional< unsigned > getOpcode(ArrayRef< VPValue *> Values)
Returns the opcode of Values or ~0 if they do not all agree.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
MachineOperand & getFlagOp(MachineInstr &MI, unsigned SrcIdx=0, unsigned Flag=0) const
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
int getSelIdx(unsigned Opcode, unsigned SrcIdx) const
bool hasVarSizedObjects() const
This method may be called any time after instruction selection is complete to determine if the stack ...
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
void setImmOperand(MachineInstr &MI, unsigned Op, int64_t Imm) const
Helper function for setting instruction flag values.
bool isRegisterLoad(const MachineInstr &MI) const
#define HAS_NATIVE_OPERANDS(Flags)
static bool isJump(unsigned Opcode)
bool hasInstrModifiers(unsigned Opcode) const
unsigned getMaxAlusPerClause() const
bool isRegisterStore(const MachineInstr &MI) const
bool usesVertexCache(unsigned Opcode) const
unsigned getAddressSpaceForPseudoSourceKind(unsigned Kind) const override
bool mustBeLastInClause(unsigned Opcode) const
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
reverse_iterator getReverse() const
Get a reverse iterator to the same node.
Itinerary data supplied by a subtarget to be used by a target.
bool DefinesPredicate(MachineInstr &MI, std::vector< MachineOperand > &Pred) const override
iterator getLastNonDebugInstr()
Returns an iterator to the last non-debug instruction in the basic block, or end().
MachineInstrBuilder buildDefaultInstruction(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned Opcode, unsigned DstReg, unsigned Src0Reg, unsigned Src1Reg=0) const
buildDefaultInstruction - This function returns a MachineInstr with all the instruction modifiers ini...
const TargetRegisterClass * getIndirectAddrRegClass() const
reverse_iterator rbegin()
bool isPredicable(const MachineInstr &MI) const override
virtual const InstrItineraryData * getInstrItineraryData() const
getInstrItineraryData - Returns instruction itinerary data for the target or specific subtarget...
bool isExport(unsigned Opcode) const
Flag
These should be considered private to the implementation of the MCInstrDesc class.
iterator find(const_arg_type_t< KeyT > Val)
unsigned getHWRegIndex(unsigned Reg) const
const R600FrameLowering * getFrameLowering() const override
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemvoed=nullptr) const override
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
bool isCompute(CallingConv::ID cc)
unsigned const MachineRegisterInfo * MRI
bool FindSwizzleForVectorSlot(const std::vector< std::vector< std::pair< int, unsigned > > > &IGSrcs, std::vector< R600InstrInfo::BankSwizzle > &SwzCandidate, const std::vector< std::pair< int, unsigned > > &TransSrcs, R600InstrInfo::BankSwizzle TransSwz) const
Enumerate all possible Swizzle sequence to find one that can meet all read port requirements.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
DebugLoc findDebugLoc(instr_iterator MBBI)
Find the next valid DebugLoc starting at MBBI, skipping any DBG_VALUE and DBG_LABEL instructions...
SmallSet - This maintains a set of unique values, optimizing for the case when the set is small (less...
bool isLDSInstr(unsigned Opcode) const
void setImm(int64_t immVal)
int getOperandIdx(const MachineInstr &MI, unsigned Op) const
Get the index of Op in the MachineInstr.
bool isVectorOnly(unsigned Opcode) const
static MachineInstr * findFirstPredicateSetterFrom(MachineBasicBlock &MBB, MachineBasicBlock::iterator I)
std::pair< NoneType, bool > insert(const T &V)
insert - Insert an element into the set if it isn't already there.
static void write(bool isBE, void *P, T V)
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
bool fitsConstReadLimitations(const std::vector< MachineInstr *> &) const
An instruction group can only access 2 channel pair (either [XY] or [ZW]) from KCache bank on R700+...
bool hasVertexCache() const
void setIsKill(bool Val=true)
bool isTransOnly(unsigned Opcode) const
bool isVector(const MachineInstr &MI) const
Vector instructions are instructions that must fill all instruction slots within an instruction group...
static bool NextPossibleSolution(std::vector< R600InstrInfo::BankSwizzle > &SwzCandidate, unsigned Idx)
Given a swizzle sequence SwzCandidate and an index Idx, returns the next (in lexicographic term) swiz...
bool isGlobal() const
isGlobal - Tests if this is a MO_GlobalAddress operand.
bool isPhysRegLiveAcrossClauses(unsigned Reg) const
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
MachineOperand class - Representation of each machine instruction operand.
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small...
bool PredicateInstruction(MachineInstr &MI, ArrayRef< MachineOperand > Pred) const override
unsigned calculateIndirectAddress(unsigned RegIndex, unsigned Channel) const
Calculate the "Indirect Address" for the given RegIndex and Channel.
#define OPERAND_CASE(Label)
bool hasCaymanISA() const
unsigned getHWRegChan(unsigned reg) const
get the HW encoding for a register's channel.
const Function & getFunction() const
Return the LLVM function that this machine code represents.
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
bool isALUInstr(unsigned Opcode) const
static bool isPredicateSetter(unsigned Opcode)
virtual bool isPredicable(const MachineInstr &MI) const
Return true if the specified instruction can be predicated.
static unsigned getReg(const void *D, unsigned RC, unsigned RegNo)
int findRegisterDefOperandIdx(unsigned Reg, bool isDead=false, bool Overlap=false, const TargetRegisterInfo *TRI=nullptr) const
Returns the operand index that is a def of the specified register or -1 if it is not found...
ArrayRef< std::pair< unsigned, unsigned > > liveins() const
bool readsLDSSrcReg(const MachineInstr &MI) const
bool isLDSRetInstr(unsigned Opcode) const
void reserveRegisterTuples(BitVector &Reserved, unsigned Reg) const
const MachineBasicBlock * getParent() const
Contains the definition of a TargetInstrInfo class that is common to all AMD GPUs.
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
TargetSubtargetInfo - Generic base class for all target subtargets.
static bool isConstCompatible(R600InstrInfo::BankSwizzle TransSwz, const std::vector< std::pair< int, unsigned >> &TransOps, unsigned ConstCount)
Instructions in Trans slot can't read gpr at cycle 0 if they also read a const, and can't read a gpr ...
Provides AMDGPU specific target descriptions.
Representation of each machine instruction.
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
bool isReductionOp(unsigned opcode) const
#define GET_FLAG_OPERAND_IDX(Flags)
Helper for getting the operand index for the instruction flags operand.
bool fitsReadPortLimitations(const std::vector< MachineInstr *> &MIs, const DenseMap< unsigned, unsigned > &PV, std::vector< BankSwizzle > &BS, bool isLastAluTrans) const
Given the order VEC_012 < VEC_021 < VEC_120 < VEC_102 < VEC_201 < VEC_210 returns true and the first ...
void setReg(unsigned Reg)
Change the register this operand corresponds to.
int getIndirectIndexBegin(const MachineFunction &MF) const
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
SmallVector< std::pair< MachineOperand *, int64_t >, 3 > getSrcs(MachineInstr &MI) const
bool isProfitableToUnpredicate(MachineBasicBlock &TMBB, MachineBasicBlock &FMBB) const override
int getIndirectIndexEnd(const MachineFunction &MF) const
DFAPacketizer * CreateTargetScheduleState(const TargetSubtargetInfo &) const override
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
bool canBeConsideredALU(const MachineInstr &MI) const
static bool isBranch(unsigned Opcode)
mop_iterator operands_begin()
#define GET_REG_INDEX(reg)
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned char TargetFlags=0) const
MachineInstr * buildMovInstr(MachineBasicBlock *MBB, MachineBasicBlock::iterator I, unsigned DstReg, unsigned SrcReg) const
Address space for private memory.
const MachineOperand & getOperand(unsigned i) const
bool usesTextureCache(unsigned Opcode) const
void reserveIndirectRegisters(BitVector &Reserved, const MachineFunction &MF, const R600RegisterInfo &TRI) const
Reserve the registers that may be accesed using indirect addressing.
int findRegisterUseOperandIdx(unsigned Reg, bool isKill=false, const TargetRegisterInfo *TRI=nullptr) const
Returns the operand index that is a use of the specific register or -1 if it is not found...
MachineInstr * buildMovImm(MachineBasicBlock &BB, MachineBasicBlock::iterator I, unsigned DstReg, uint64_t Imm) const
bool definesAddressRegister(MachineInstr &MI) const
bool empty() const
empty - Check if the array is empty.
bool isCubeOp(unsigned opcode) const
bool isLegalToSplitMBBAt(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) const override
unsigned getStackWidth(const MachineFunction &MF) const