LLVM  8.0.0svn
IRTranslator.cpp
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1 //===- llvm/CodeGen/GlobalISel/IRTranslator.cpp - IRTranslator ---*- C++ -*-==//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 /// \file
10 /// This file implements the IRTranslator class.
11 //===----------------------------------------------------------------------===//
12 
15 #include "llvm/ADT/STLExtras.h"
16 #include "llvm/ADT/ScopeExit.h"
17 #include "llvm/ADT/SmallSet.h"
18 #include "llvm/ADT/SmallVector.h"
20 #include "llvm/CodeGen/Analysis.h"
36 #include "llvm/IR/BasicBlock.h"
37 #include "llvm/IR/CFG.h"
38 #include "llvm/IR/Constant.h"
39 #include "llvm/IR/Constants.h"
40 #include "llvm/IR/DataLayout.h"
41 #include "llvm/IR/DebugInfo.h"
42 #include "llvm/IR/DerivedTypes.h"
43 #include "llvm/IR/Function.h"
45 #include "llvm/IR/InlineAsm.h"
46 #include "llvm/IR/InstrTypes.h"
47 #include "llvm/IR/Instructions.h"
48 #include "llvm/IR/IntrinsicInst.h"
49 #include "llvm/IR/Intrinsics.h"
50 #include "llvm/IR/LLVMContext.h"
51 #include "llvm/IR/Metadata.h"
52 #include "llvm/IR/Type.h"
53 #include "llvm/IR/User.h"
54 #include "llvm/IR/Value.h"
55 #include "llvm/MC/MCContext.h"
56 #include "llvm/Pass.h"
57 #include "llvm/Support/Casting.h"
58 #include "llvm/Support/CodeGen.h"
59 #include "llvm/Support/Debug.h"
66 #include <algorithm>
67 #include <cassert>
68 #include <cstdint>
69 #include <iterator>
70 #include <string>
71 #include <utility>
72 #include <vector>
73 
74 #define DEBUG_TYPE "irtranslator"
75 
76 using namespace llvm;
77 
78 char IRTranslator::ID = 0;
79 
80 INITIALIZE_PASS_BEGIN(IRTranslator, DEBUG_TYPE, "IRTranslator LLVM IR -> MI",
81  false, false)
83 INITIALIZE_PASS_END(IRTranslator, DEBUG_TYPE, "IRTranslator LLVM IR -> MI",
84  false, false)
85 
91 
92  // Print the function name explicitly if we don't have a debug location (which
93  // makes the diagnostic less useful) or if we're going to emit a raw error.
94  if (!R.getLocation().isValid() || TPC.isGlobalISelAbortEnabled())
95  R << (" (in function: " + MF.getName() + ")").str();
96 
97  if (TPC.isGlobalISelAbortEnabled())
98  report_fatal_error(R.getMsg());
99  else
100  ORE.emit(R);
101 }
102 
105 }
106 
112 }
113 
114 static void computeValueLLTs(const DataLayout &DL, Type &Ty,
115  SmallVectorImpl<LLT> &ValueTys,
117  uint64_t StartingOffset = 0) {
118  // Given a struct type, recursively traverse the elements.
119  if (StructType *STy = dyn_cast<StructType>(&Ty)) {
120  const StructLayout *SL = DL.getStructLayout(STy);
121  for (unsigned I = 0, E = STy->getNumElements(); I != E; ++I)
122  computeValueLLTs(DL, *STy->getElementType(I), ValueTys, Offsets,
123  StartingOffset + SL->getElementOffset(I));
124  return;
125  }
126  // Given an array type, recursively traverse the elements.
127  if (ArrayType *ATy = dyn_cast<ArrayType>(&Ty)) {
128  Type *EltTy = ATy->getElementType();
129  uint64_t EltSize = DL.getTypeAllocSize(EltTy);
130  for (unsigned i = 0, e = ATy->getNumElements(); i != e; ++i)
131  computeValueLLTs(DL, *EltTy, ValueTys, Offsets,
132  StartingOffset + i * EltSize);
133  return;
134  }
135  // Interpret void as zero return values.
136  if (Ty.isVoidTy())
137  return;
138  // Base case: we can get an LLT for this LLVM IR type.
139  ValueTys.push_back(getLLTForType(Ty, DL));
140  if (Offsets != nullptr)
141  Offsets->push_back(StartingOffset * 8);
142 }
143 
145 IRTranslator::allocateVRegs(const Value &Val) {
146  assert(!VMap.contains(Val) && "Value already allocated in VMap");
147  auto *Regs = VMap.getVRegs(Val);
148  auto *Offsets = VMap.getOffsets(Val);
149  SmallVector<LLT, 4> SplitTys;
150  computeValueLLTs(*DL, *Val.getType(), SplitTys,
151  Offsets->empty() ? Offsets : nullptr);
152  for (unsigned i = 0; i < SplitTys.size(); ++i)
153  Regs->push_back(0);
154  return *Regs;
155 }
156 
157 ArrayRef<unsigned> IRTranslator::getOrCreateVRegs(const Value &Val) {
158  auto VRegsIt = VMap.findVRegs(Val);
159  if (VRegsIt != VMap.vregs_end())
160  return *VRegsIt->second;
161 
162  if (Val.getType()->isVoidTy())
163  return *VMap.getVRegs(Val);
164 
165  // Create entry for this type.
166  auto *VRegs = VMap.getVRegs(Val);
167  auto *Offsets = VMap.getOffsets(Val);
168 
169  assert(Val.getType()->isSized() &&
170  "Don't know how to create an empty vreg");
171 
172  SmallVector<LLT, 4> SplitTys;
173  computeValueLLTs(*DL, *Val.getType(), SplitTys,
174  Offsets->empty() ? Offsets : nullptr);
175 
176  if (!isa<Constant>(Val)) {
177  for (auto Ty : SplitTys)
178  VRegs->push_back(MRI->createGenericVirtualRegister(Ty));
179  return *VRegs;
180  }
181 
182  if (Val.getType()->isAggregateType()) {
183  // UndefValue, ConstantAggregateZero
184  auto &C = cast<Constant>(Val);
185  unsigned Idx = 0;
186  while (auto Elt = C.getAggregateElement(Idx++)) {
187  auto EltRegs = getOrCreateVRegs(*Elt);
188  std::copy(EltRegs.begin(), EltRegs.end(), std::back_inserter(*VRegs));
189  }
190  } else {
191  assert(SplitTys.size() == 1 && "unexpectedly split LLT");
192  VRegs->push_back(MRI->createGenericVirtualRegister(SplitTys[0]));
193  bool Success = translate(cast<Constant>(Val), VRegs->front());
194  if (!Success) {
195  OptimizationRemarkMissed R("gisel-irtranslator", "GISelFailure",
196  MF->getFunction().getSubprogram(),
197  &MF->getFunction().getEntryBlock());
198  R << "unable to translate constant: " << ore::NV("Type", Val.getType());
199  reportTranslationError(*MF, *TPC, *ORE, R);
200  return *VRegs;
201  }
202  }
203 
204  return *VRegs;
205 }
206 
207 int IRTranslator::getOrCreateFrameIndex(const AllocaInst &AI) {
208  if (FrameIndices.find(&AI) != FrameIndices.end())
209  return FrameIndices[&AI];
210 
211  unsigned ElementSize = DL->getTypeStoreSize(AI.getAllocatedType());
212  unsigned Size =
213  ElementSize * cast<ConstantInt>(AI.getArraySize())->getZExtValue();
214 
215  // Always allocate at least one byte.
216  Size = std::max(Size, 1u);
217 
218  unsigned Alignment = AI.getAlignment();
219  if (!Alignment)
220  Alignment = DL->getABITypeAlignment(AI.getAllocatedType());
221 
222  int &FI = FrameIndices[&AI];
223  FI = MF->getFrameInfo().CreateStackObject(Size, Alignment, false, &AI);
224  return FI;
225 }
226 
227 unsigned IRTranslator::getMemOpAlignment(const Instruction &I) {
228  unsigned Alignment = 0;
229  Type *ValTy = nullptr;
230  if (const StoreInst *SI = dyn_cast<StoreInst>(&I)) {
231  Alignment = SI->getAlignment();
232  ValTy = SI->getValueOperand()->getType();
233  } else if (const LoadInst *LI = dyn_cast<LoadInst>(&I)) {
234  Alignment = LI->getAlignment();
235  ValTy = LI->getType();
236  } else if (const AtomicCmpXchgInst *AI = dyn_cast<AtomicCmpXchgInst>(&I)) {
237  // TODO(PR27168): This instruction has no alignment attribute, but unlike
238  // the default alignment for load/store, the default here is to assume
239  // it has NATURAL alignment, not DataLayout-specified alignment.
240  const DataLayout &DL = AI->getModule()->getDataLayout();
241  Alignment = DL.getTypeStoreSize(AI->getCompareOperand()->getType());
242  ValTy = AI->getCompareOperand()->getType();
243  } else if (const AtomicRMWInst *AI = dyn_cast<AtomicRMWInst>(&I)) {
244  // TODO(PR27168): This instruction has no alignment attribute, but unlike
245  // the default alignment for load/store, the default here is to assume
246  // it has NATURAL alignment, not DataLayout-specified alignment.
247  const DataLayout &DL = AI->getModule()->getDataLayout();
248  Alignment = DL.getTypeStoreSize(AI->getValOperand()->getType());
249  ValTy = AI->getType();
250  } else {
251  OptimizationRemarkMissed R("gisel-irtranslator", "", &I);
252  R << "unable to translate memop: " << ore::NV("Opcode", &I);
253  reportTranslationError(*MF, *TPC, *ORE, R);
254  return 1;
255  }
256 
257  return Alignment ? Alignment : DL->getABITypeAlignment(ValTy);
258 }
259 
260 MachineBasicBlock &IRTranslator::getMBB(const BasicBlock &BB) {
261  MachineBasicBlock *&MBB = BBToMBB[&BB];
262  assert(MBB && "BasicBlock was not encountered before");
263  return *MBB;
264 }
265 
266 void IRTranslator::addMachineCFGPred(CFGEdge Edge, MachineBasicBlock *NewPred) {
267  assert(NewPred && "new predecessor must be a real MachineBasicBlock");
268  MachinePreds[Edge].push_back(NewPred);
269 }
270 
271 bool IRTranslator::translateBinaryOp(unsigned Opcode, const User &U,
272  MachineIRBuilder &MIRBuilder) {
273  // FIXME: handle signed/unsigned wrapping flags.
274 
275  // Get or create a virtual register for each value.
276  // Unless the value is a Constant => loadimm cst?
277  // or inline constant each time?
278  // Creation of a virtual register needs to have a size.
279  unsigned Op0 = getOrCreateVReg(*U.getOperand(0));
280  unsigned Op1 = getOrCreateVReg(*U.getOperand(1));
281  unsigned Res = getOrCreateVReg(U);
282  auto FBinOp = MIRBuilder.buildInstr(Opcode).addDef(Res).addUse(Op0).addUse(Op1);
283  if (isa<Instruction>(U)) {
284  MachineInstr *FBinOpMI = FBinOp.getInstr();
285  const Instruction &I = cast<Instruction>(U);
286  FBinOpMI->copyIRFlags(I);
287  }
288  return true;
289 }
290 
291 bool IRTranslator::translateFSub(const User &U, MachineIRBuilder &MIRBuilder) {
292  // -0.0 - X --> G_FNEG
293  if (isa<Constant>(U.getOperand(0)) &&
295  MIRBuilder.buildInstr(TargetOpcode::G_FNEG)
296  .addDef(getOrCreateVReg(U))
297  .addUse(getOrCreateVReg(*U.getOperand(1)));
298  return true;
299  }
300  return translateBinaryOp(TargetOpcode::G_FSUB, U, MIRBuilder);
301 }
302 
303 bool IRTranslator::translateCompare(const User &U,
304  MachineIRBuilder &MIRBuilder) {
305  const CmpInst *CI = dyn_cast<CmpInst>(&U);
306  unsigned Op0 = getOrCreateVReg(*U.getOperand(0));
307  unsigned Op1 = getOrCreateVReg(*U.getOperand(1));
308  unsigned Res = getOrCreateVReg(U);
309  CmpInst::Predicate Pred =
310  CI ? CI->getPredicate() : static_cast<CmpInst::Predicate>(
311  cast<ConstantExpr>(U).getPredicate());
312  if (CmpInst::isIntPredicate(Pred))
313  MIRBuilder.buildICmp(Pred, Res, Op0, Op1);
314  else if (Pred == CmpInst::FCMP_FALSE)
315  MIRBuilder.buildCopy(
316  Res, getOrCreateVReg(*Constant::getNullValue(CI->getType())));
317  else if (Pred == CmpInst::FCMP_TRUE)
318  MIRBuilder.buildCopy(
319  Res, getOrCreateVReg(*Constant::getAllOnesValue(CI->getType())));
320  else
321  MIRBuilder.buildFCmp(Pred, Res, Op0, Op1);
322 
323  return true;
324 }
325 
326 bool IRTranslator::translateRet(const User &U, MachineIRBuilder &MIRBuilder) {
327  const ReturnInst &RI = cast<ReturnInst>(U);
328  const Value *Ret = RI.getReturnValue();
329  if (Ret && DL->getTypeStoreSize(Ret->getType()) == 0)
330  Ret = nullptr;
331 
333  if (Ret)
334  VRegs = getOrCreateVRegs(*Ret);
335 
336  // The target may mess up with the insertion point, but
337  // this is not important as a return is the last instruction
338  // of the block anyway.
339 
340  return CLI->lowerReturn(MIRBuilder, Ret, VRegs);
341 }
342 
343 bool IRTranslator::translateBr(const User &U, MachineIRBuilder &MIRBuilder) {
344  const BranchInst &BrInst = cast<BranchInst>(U);
345  unsigned Succ = 0;
346  if (!BrInst.isUnconditional()) {
347  // We want a G_BRCOND to the true BB followed by an unconditional branch.
348  unsigned Tst = getOrCreateVReg(*BrInst.getCondition());
349  const BasicBlock &TrueTgt = *cast<BasicBlock>(BrInst.getSuccessor(Succ++));
350  MachineBasicBlock &TrueBB = getMBB(TrueTgt);
351  MIRBuilder.buildBrCond(Tst, TrueBB);
352  }
353 
354  const BasicBlock &BrTgt = *cast<BasicBlock>(BrInst.getSuccessor(Succ));
355  MachineBasicBlock &TgtBB = getMBB(BrTgt);
356  MachineBasicBlock &CurBB = MIRBuilder.getMBB();
357 
358  // If the unconditional target is the layout successor, fallthrough.
359  if (!CurBB.isLayoutSuccessor(&TgtBB))
360  MIRBuilder.buildBr(TgtBB);
361 
362  // Link successors.
363  for (const BasicBlock *Succ : successors(&BrInst))
364  CurBB.addSuccessor(&getMBB(*Succ));
365  return true;
366 }
367 
368 bool IRTranslator::translateSwitch(const User &U,
369  MachineIRBuilder &MIRBuilder) {
370  // For now, just translate as a chain of conditional branches.
371  // FIXME: could we share most of the logic/code in
372  // SelectionDAGBuilder::visitSwitch between SelectionDAG and GlobalISel?
373  // At first sight, it seems most of the logic in there is independent of
374  // SelectionDAG-specifics and a lot of work went in to optimize switch
375  // lowering in there.
376 
377  const SwitchInst &SwInst = cast<SwitchInst>(U);
378  const unsigned SwCondValue = getOrCreateVReg(*SwInst.getCondition());
379  const BasicBlock *OrigBB = SwInst.getParent();
380 
381  LLT LLTi1 = getLLTForType(*Type::getInt1Ty(U.getContext()), *DL);
382  for (auto &CaseIt : SwInst.cases()) {
383  const unsigned CaseValueReg = getOrCreateVReg(*CaseIt.getCaseValue());
384  const unsigned Tst = MRI->createGenericVirtualRegister(LLTi1);
385  MIRBuilder.buildICmp(CmpInst::ICMP_EQ, Tst, CaseValueReg, SwCondValue);
386  MachineBasicBlock &CurMBB = MIRBuilder.getMBB();
387  const BasicBlock *TrueBB = CaseIt.getCaseSuccessor();
388  MachineBasicBlock &TrueMBB = getMBB(*TrueBB);
389 
390  MIRBuilder.buildBrCond(Tst, TrueMBB);
391  CurMBB.addSuccessor(&TrueMBB);
392  addMachineCFGPred({OrigBB, TrueBB}, &CurMBB);
393 
394  MachineBasicBlock *FalseMBB =
395  MF->CreateMachineBasicBlock(SwInst.getParent());
396  // Insert the comparison blocks one after the other.
397  MF->insert(std::next(CurMBB.getIterator()), FalseMBB);
398  MIRBuilder.buildBr(*FalseMBB);
399  CurMBB.addSuccessor(FalseMBB);
400 
401  MIRBuilder.setMBB(*FalseMBB);
402  }
403  // handle default case
404  const BasicBlock *DefaultBB = SwInst.getDefaultDest();
405  MachineBasicBlock &DefaultMBB = getMBB(*DefaultBB);
406  MIRBuilder.buildBr(DefaultMBB);
407  MachineBasicBlock &CurMBB = MIRBuilder.getMBB();
408  CurMBB.addSuccessor(&DefaultMBB);
409  addMachineCFGPred({OrigBB, DefaultBB}, &CurMBB);
410 
411  return true;
412 }
413 
414 bool IRTranslator::translateIndirectBr(const User &U,
415  MachineIRBuilder &MIRBuilder) {
416  const IndirectBrInst &BrInst = cast<IndirectBrInst>(U);
417 
418  const unsigned Tgt = getOrCreateVReg(*BrInst.getAddress());
419  MIRBuilder.buildBrIndirect(Tgt);
420 
421  // Link successors.
422  MachineBasicBlock &CurBB = MIRBuilder.getMBB();
423  for (const BasicBlock *Succ : successors(&BrInst))
424  CurBB.addSuccessor(&getMBB(*Succ));
425 
426  return true;
427 }
428 
429 bool IRTranslator::translateLoad(const User &U, MachineIRBuilder &MIRBuilder) {
430  const LoadInst &LI = cast<LoadInst>(U);
431 
432  auto Flags = LI.isVolatile() ? MachineMemOperand::MOVolatile
434  Flags |= MachineMemOperand::MOLoad;
435 
436  if (DL->getTypeStoreSize(LI.getType()) == 0)
437  return true;
438 
439  ArrayRef<unsigned> Regs = getOrCreateVRegs(LI);
440  ArrayRef<uint64_t> Offsets = *VMap.getOffsets(LI);
441  unsigned Base = getOrCreateVReg(*LI.getPointerOperand());
442 
443  for (unsigned i = 0; i < Regs.size(); ++i) {
444  unsigned Addr = 0;
445  MIRBuilder.materializeGEP(Addr, Base, LLT::scalar(64), Offsets[i] / 8);
446 
447  MachinePointerInfo Ptr(LI.getPointerOperand(), Offsets[i] / 8);
448  unsigned BaseAlign = getMemOpAlignment(LI);
449  auto MMO = MF->getMachineMemOperand(
450  Ptr, Flags, (MRI->getType(Regs[i]).getSizeInBits() + 7) / 8,
451  MinAlign(BaseAlign, Offsets[i] / 8), AAMDNodes(), nullptr,
452  LI.getSyncScopeID(), LI.getOrdering());
453  MIRBuilder.buildLoad(Regs[i], Addr, *MMO);
454  }
455 
456  return true;
457 }
458 
459 bool IRTranslator::translateStore(const User &U, MachineIRBuilder &MIRBuilder) {
460  const StoreInst &SI = cast<StoreInst>(U);
461  auto Flags = SI.isVolatile() ? MachineMemOperand::MOVolatile
464 
465  if (DL->getTypeStoreSize(SI.getValueOperand()->getType()) == 0)
466  return true;
467 
468  ArrayRef<unsigned> Vals = getOrCreateVRegs(*SI.getValueOperand());
469  ArrayRef<uint64_t> Offsets = *VMap.getOffsets(*SI.getValueOperand());
470  unsigned Base = getOrCreateVReg(*SI.getPointerOperand());
471 
472  for (unsigned i = 0; i < Vals.size(); ++i) {
473  unsigned Addr = 0;
474  MIRBuilder.materializeGEP(Addr, Base, LLT::scalar(64), Offsets[i] / 8);
475 
476  MachinePointerInfo Ptr(SI.getPointerOperand(), Offsets[i] / 8);
477  unsigned BaseAlign = getMemOpAlignment(SI);
478  auto MMO = MF->getMachineMemOperand(
479  Ptr, Flags, (MRI->getType(Vals[i]).getSizeInBits() + 7) / 8,
480  MinAlign(BaseAlign, Offsets[i] / 8), AAMDNodes(), nullptr,
481  SI.getSyncScopeID(), SI.getOrdering());
482  MIRBuilder.buildStore(Vals[i], Addr, *MMO);
483  }
484  return true;
485 }
486 
487 static uint64_t getOffsetFromIndices(const User &U, const DataLayout &DL) {
488  const Value *Src = U.getOperand(0);
490 
491  // getIndexedOffsetInType is designed for GEPs, so the first index is the
492  // usual array element rather than looking into the actual aggregate.
493  SmallVector<Value *, 1> Indices;
494  Indices.push_back(ConstantInt::get(Int32Ty, 0));
495 
496  if (const ExtractValueInst *EVI = dyn_cast<ExtractValueInst>(&U)) {
497  for (auto Idx : EVI->indices())
498  Indices.push_back(ConstantInt::get(Int32Ty, Idx));
499  } else if (const InsertValueInst *IVI = dyn_cast<InsertValueInst>(&U)) {
500  for (auto Idx : IVI->indices())
501  Indices.push_back(ConstantInt::get(Int32Ty, Idx));
502  } else {
503  for (unsigned i = 1; i < U.getNumOperands(); ++i)
504  Indices.push_back(U.getOperand(i));
505  }
506 
507  return 8 * static_cast<uint64_t>(
508  DL.getIndexedOffsetInType(Src->getType(), Indices));
509 }
510 
511 bool IRTranslator::translateExtractValue(const User &U,
512  MachineIRBuilder &MIRBuilder) {
513  const Value *Src = U.getOperand(0);
514  uint64_t Offset = getOffsetFromIndices(U, *DL);
515  ArrayRef<unsigned> SrcRegs = getOrCreateVRegs(*Src);
516  ArrayRef<uint64_t> Offsets = *VMap.getOffsets(*Src);
517  unsigned Idx = std::lower_bound(Offsets.begin(), Offsets.end(), Offset) -
518  Offsets.begin();
519  auto &DstRegs = allocateVRegs(U);
520 
521  for (unsigned i = 0; i < DstRegs.size(); ++i)
522  DstRegs[i] = SrcRegs[Idx++];
523 
524  return true;
525 }
526 
527 bool IRTranslator::translateInsertValue(const User &U,
528  MachineIRBuilder &MIRBuilder) {
529  const Value *Src = U.getOperand(0);
530  uint64_t Offset = getOffsetFromIndices(U, *DL);
531  auto &DstRegs = allocateVRegs(U);
532  ArrayRef<uint64_t> DstOffsets = *VMap.getOffsets(U);
533  ArrayRef<unsigned> SrcRegs = getOrCreateVRegs(*Src);
534  ArrayRef<unsigned> InsertedRegs = getOrCreateVRegs(*U.getOperand(1));
535  auto InsertedIt = InsertedRegs.begin();
536 
537  for (unsigned i = 0; i < DstRegs.size(); ++i) {
538  if (DstOffsets[i] >= Offset && InsertedIt != InsertedRegs.end())
539  DstRegs[i] = *InsertedIt++;
540  else
541  DstRegs[i] = SrcRegs[i];
542  }
543 
544  return true;
545 }
546 
547 bool IRTranslator::translateSelect(const User &U,
548  MachineIRBuilder &MIRBuilder) {
549  unsigned Tst = getOrCreateVReg(*U.getOperand(0));
550  ArrayRef<unsigned> ResRegs = getOrCreateVRegs(U);
551  ArrayRef<unsigned> Op0Regs = getOrCreateVRegs(*U.getOperand(1));
552  ArrayRef<unsigned> Op1Regs = getOrCreateVRegs(*U.getOperand(2));
553 
554  for (unsigned i = 0; i < ResRegs.size(); ++i)
555  MIRBuilder.buildSelect(ResRegs[i], Tst, Op0Regs[i], Op1Regs[i]);
556 
557  return true;
558 }
559 
560 bool IRTranslator::translateBitCast(const User &U,
561  MachineIRBuilder &MIRBuilder) {
562  // If we're bitcasting to the source type, we can reuse the source vreg.
563  if (getLLTForType(*U.getOperand(0)->getType(), *DL) ==
564  getLLTForType(*U.getType(), *DL)) {
565  unsigned SrcReg = getOrCreateVReg(*U.getOperand(0));
566  auto &Regs = *VMap.getVRegs(U);
567  // If we already assigned a vreg for this bitcast, we can't change that.
568  // Emit a copy to satisfy the users we already emitted.
569  if (!Regs.empty())
570  MIRBuilder.buildCopy(Regs[0], SrcReg);
571  else {
572  Regs.push_back(SrcReg);
573  VMap.getOffsets(U)->push_back(0);
574  }
575  return true;
576  }
577  return translateCast(TargetOpcode::G_BITCAST, U, MIRBuilder);
578 }
579 
580 bool IRTranslator::translateCast(unsigned Opcode, const User &U,
581  MachineIRBuilder &MIRBuilder) {
582  unsigned Op = getOrCreateVReg(*U.getOperand(0));
583  unsigned Res = getOrCreateVReg(U);
584  MIRBuilder.buildInstr(Opcode).addDef(Res).addUse(Op);
585  return true;
586 }
587 
588 bool IRTranslator::translateGetElementPtr(const User &U,
589  MachineIRBuilder &MIRBuilder) {
590  // FIXME: support vector GEPs.
591  if (U.getType()->isVectorTy())
592  return false;
593 
594  Value &Op0 = *U.getOperand(0);
595  unsigned BaseReg = getOrCreateVReg(Op0);
596  Type *PtrIRTy = Op0.getType();
597  LLT PtrTy = getLLTForType(*PtrIRTy, *DL);
598  Type *OffsetIRTy = DL->getIntPtrType(PtrIRTy);
599  LLT OffsetTy = getLLTForType(*OffsetIRTy, *DL);
600 
601  int64_t Offset = 0;
602  for (gep_type_iterator GTI = gep_type_begin(&U), E = gep_type_end(&U);
603  GTI != E; ++GTI) {
604  const Value *Idx = GTI.getOperand();
605  if (StructType *StTy = GTI.getStructTypeOrNull()) {
606  unsigned Field = cast<Constant>(Idx)->getUniqueInteger().getZExtValue();
607  Offset += DL->getStructLayout(StTy)->getElementOffset(Field);
608  continue;
609  } else {
610  uint64_t ElementSize = DL->getTypeAllocSize(GTI.getIndexedType());
611 
612  // If this is a scalar constant or a splat vector of constants,
613  // handle it quickly.
614  if (const auto *CI = dyn_cast<ConstantInt>(Idx)) {
615  Offset += ElementSize * CI->getSExtValue();
616  continue;
617  }
618 
619  if (Offset != 0) {
620  unsigned NewBaseReg = MRI->createGenericVirtualRegister(PtrTy);
621  unsigned OffsetReg =
622  getOrCreateVReg(*ConstantInt::get(OffsetIRTy, Offset));
623  MIRBuilder.buildGEP(NewBaseReg, BaseReg, OffsetReg);
624 
625  BaseReg = NewBaseReg;
626  Offset = 0;
627  }
628 
629  unsigned IdxReg = getOrCreateVReg(*Idx);
630  if (MRI->getType(IdxReg) != OffsetTy) {
631  unsigned NewIdxReg = MRI->createGenericVirtualRegister(OffsetTy);
632  MIRBuilder.buildSExtOrTrunc(NewIdxReg, IdxReg);
633  IdxReg = NewIdxReg;
634  }
635 
636  // N = N + Idx * ElementSize;
637  // Avoid doing it for ElementSize of 1.
638  unsigned GepOffsetReg;
639  if (ElementSize != 1) {
640  unsigned ElementSizeReg =
641  getOrCreateVReg(*ConstantInt::get(OffsetIRTy, ElementSize));
642 
643  GepOffsetReg = MRI->createGenericVirtualRegister(OffsetTy);
644  MIRBuilder.buildMul(GepOffsetReg, ElementSizeReg, IdxReg);
645  } else
646  GepOffsetReg = IdxReg;
647 
648  unsigned NewBaseReg = MRI->createGenericVirtualRegister(PtrTy);
649  MIRBuilder.buildGEP(NewBaseReg, BaseReg, GepOffsetReg);
650  BaseReg = NewBaseReg;
651  }
652  }
653 
654  if (Offset != 0) {
655  unsigned OffsetReg = getOrCreateVReg(*ConstantInt::get(OffsetIRTy, Offset));
656  MIRBuilder.buildGEP(getOrCreateVReg(U), BaseReg, OffsetReg);
657  return true;
658  }
659 
660  MIRBuilder.buildCopy(getOrCreateVReg(U), BaseReg);
661  return true;
662 }
663 
664 bool IRTranslator::translateMemfunc(const CallInst &CI,
665  MachineIRBuilder &MIRBuilder,
666  unsigned ID) {
667  LLT SizeTy = getLLTForType(*CI.getArgOperand(2)->getType(), *DL);
668  Type *DstTy = CI.getArgOperand(0)->getType();
669  if (cast<PointerType>(DstTy)->getAddressSpace() != 0 ||
670  SizeTy.getSizeInBits() != DL->getPointerSizeInBits(0))
671  return false;
672 
674  for (int i = 0; i < 3; ++i) {
675  const auto &Arg = CI.getArgOperand(i);
676  Args.emplace_back(getOrCreateVReg(*Arg), Arg->getType());
677  }
678 
679  const char *Callee;
680  switch (ID) {
681  case Intrinsic::memmove:
682  case Intrinsic::memcpy: {
683  Type *SrcTy = CI.getArgOperand(1)->getType();
684  if(cast<PointerType>(SrcTy)->getAddressSpace() != 0)
685  return false;
686  Callee = ID == Intrinsic::memcpy ? "memcpy" : "memmove";
687  break;
688  }
689  case Intrinsic::memset:
690  Callee = "memset";
691  break;
692  default:
693  return false;
694  }
695 
696  return CLI->lowerCall(MIRBuilder, CI.getCallingConv(),
697  MachineOperand::CreateES(Callee),
698  CallLowering::ArgInfo(0, CI.getType()), Args);
699 }
700 
701 void IRTranslator::getStackGuard(unsigned DstReg,
702  MachineIRBuilder &MIRBuilder) {
704  MRI->setRegClass(DstReg, TRI->getPointerRegClass(*MF));
705  auto MIB = MIRBuilder.buildInstr(TargetOpcode::LOAD_STACK_GUARD);
706  MIB.addDef(DstReg);
707 
708  auto &TLI = *MF->getSubtarget().getTargetLowering();
709  Value *Global = TLI.getSDagStackGuard(*MF->getFunction().getParent());
710  if (!Global)
711  return;
712 
713  MachinePointerInfo MPInfo(Global);
717  MF->getMachineMemOperand(MPInfo, Flags, DL->getPointerSizeInBits() / 8,
718  DL->getPointerABIAlignment(0));
719  MIB.setMemRefs({MemRef});
720 }
721 
722 bool IRTranslator::translateOverflowIntrinsic(const CallInst &CI, unsigned Op,
723  MachineIRBuilder &MIRBuilder) {
724  ArrayRef<unsigned> ResRegs = getOrCreateVRegs(CI);
725  MIRBuilder.buildInstr(Op)
726  .addDef(ResRegs[0])
727  .addDef(ResRegs[1])
728  .addUse(getOrCreateVReg(*CI.getOperand(0)))
729  .addUse(getOrCreateVReg(*CI.getOperand(1)));
730 
731  return true;
732 }
733 
734 bool IRTranslator::translateKnownIntrinsic(const CallInst &CI, Intrinsic::ID ID,
735  MachineIRBuilder &MIRBuilder) {
736  switch (ID) {
737  default:
738  break;
739  case Intrinsic::lifetime_start:
740  case Intrinsic::lifetime_end:
741  // Stack coloring is not enabled in O0 (which we care about now) so we can
742  // drop these. Make sure someone notices when we start compiling at higher
743  // opts though.
744  if (MF->getTarget().getOptLevel() != CodeGenOpt::None)
745  return false;
746  return true;
747  case Intrinsic::dbg_declare: {
748  const DbgDeclareInst &DI = cast<DbgDeclareInst>(CI);
749  assert(DI.getVariable() && "Missing variable");
750 
751  const Value *Address = DI.getAddress();
752  if (!Address || isa<UndefValue>(Address)) {
753  LLVM_DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
754  return true;
755  }
756 
758  MIRBuilder.getDebugLoc()) &&
759  "Expected inlined-at fields to agree");
760  auto AI = dyn_cast<AllocaInst>(Address);
761  if (AI && AI->isStaticAlloca()) {
762  // Static allocas are tracked at the MF level, no need for DBG_VALUE
763  // instructions (in fact, they get ignored if they *do* exist).
765  getOrCreateFrameIndex(*AI), DI.getDebugLoc());
766  } else {
767  // A dbg.declare describes the address of a source variable, so lower it
768  // into an indirect DBG_VALUE.
769  MIRBuilder.buildIndirectDbgValue(getOrCreateVReg(*Address),
770  DI.getVariable(), DI.getExpression());
771  }
772  return true;
773  }
774  case Intrinsic::dbg_label: {
775  const DbgLabelInst &DI = cast<DbgLabelInst>(CI);
776  assert(DI.getLabel() && "Missing label");
777 
779  MIRBuilder.getDebugLoc()) &&
780  "Expected inlined-at fields to agree");
781 
782  MIRBuilder.buildDbgLabel(DI.getLabel());
783  return true;
784  }
785  case Intrinsic::vaend:
786  // No target I know of cares about va_end. Certainly no in-tree target
787  // does. Simplest intrinsic ever!
788  return true;
789  case Intrinsic::vastart: {
790  auto &TLI = *MF->getSubtarget().getTargetLowering();
791  Value *Ptr = CI.getArgOperand(0);
792  unsigned ListSize = TLI.getVaListSizeInBits(*DL) / 8;
793 
794  MIRBuilder.buildInstr(TargetOpcode::G_VASTART)
795  .addUse(getOrCreateVReg(*Ptr))
797  MachinePointerInfo(Ptr), MachineMemOperand::MOStore, ListSize, 0));
798  return true;
799  }
800  case Intrinsic::dbg_value: {
801  // This form of DBG_VALUE is target-independent.
802  const DbgValueInst &DI = cast<DbgValueInst>(CI);
803  const Value *V = DI.getValue();
805  MIRBuilder.getDebugLoc()) &&
806  "Expected inlined-at fields to agree");
807  if (!V) {
808  // Currently the optimizer can produce this; insert an undef to
809  // help debugging. Probably the optimizer should not do this.
810  MIRBuilder.buildIndirectDbgValue(0, DI.getVariable(), DI.getExpression());
811  } else if (const auto *CI = dyn_cast<Constant>(V)) {
812  MIRBuilder.buildConstDbgValue(*CI, DI.getVariable(), DI.getExpression());
813  } else {
814  unsigned Reg = getOrCreateVReg(*V);
815  // FIXME: This does not handle register-indirect values at offset 0. The
816  // direct/indirect thing shouldn't really be handled by something as
817  // implicit as reg+noreg vs reg+imm in the first palce, but it seems
818  // pretty baked in right now.
819  MIRBuilder.buildDirectDbgValue(Reg, DI.getVariable(), DI.getExpression());
820  }
821  return true;
822  }
823  case Intrinsic::uadd_with_overflow:
824  return translateOverflowIntrinsic(CI, TargetOpcode::G_UADDO, MIRBuilder);
825  case Intrinsic::sadd_with_overflow:
826  return translateOverflowIntrinsic(CI, TargetOpcode::G_SADDO, MIRBuilder);
827  case Intrinsic::usub_with_overflow:
828  return translateOverflowIntrinsic(CI, TargetOpcode::G_USUBO, MIRBuilder);
829  case Intrinsic::ssub_with_overflow:
830  return translateOverflowIntrinsic(CI, TargetOpcode::G_SSUBO, MIRBuilder);
831  case Intrinsic::umul_with_overflow:
832  return translateOverflowIntrinsic(CI, TargetOpcode::G_UMULO, MIRBuilder);
833  case Intrinsic::smul_with_overflow:
834  return translateOverflowIntrinsic(CI, TargetOpcode::G_SMULO, MIRBuilder);
835  case Intrinsic::pow:
836  MIRBuilder.buildInstr(TargetOpcode::G_FPOW)
837  .addDef(getOrCreateVReg(CI))
838  .addUse(getOrCreateVReg(*CI.getArgOperand(0)))
839  .addUse(getOrCreateVReg(*CI.getArgOperand(1)));
840  return true;
841  case Intrinsic::exp:
842  MIRBuilder.buildInstr(TargetOpcode::G_FEXP)
843  .addDef(getOrCreateVReg(CI))
844  .addUse(getOrCreateVReg(*CI.getArgOperand(0)));
845  return true;
846  case Intrinsic::exp2:
847  MIRBuilder.buildInstr(TargetOpcode::G_FEXP2)
848  .addDef(getOrCreateVReg(CI))
849  .addUse(getOrCreateVReg(*CI.getArgOperand(0)));
850  return true;
851  case Intrinsic::log:
852  MIRBuilder.buildInstr(TargetOpcode::G_FLOG)
853  .addDef(getOrCreateVReg(CI))
854  .addUse(getOrCreateVReg(*CI.getArgOperand(0)));
855  return true;
856  case Intrinsic::log2:
857  MIRBuilder.buildInstr(TargetOpcode::G_FLOG2)
858  .addDef(getOrCreateVReg(CI))
859  .addUse(getOrCreateVReg(*CI.getArgOperand(0)));
860  return true;
861  case Intrinsic::fabs:
862  MIRBuilder.buildInstr(TargetOpcode::G_FABS)
863  .addDef(getOrCreateVReg(CI))
864  .addUse(getOrCreateVReg(*CI.getArgOperand(0)));
865  return true;
866  case Intrinsic::trunc:
867  MIRBuilder.buildInstr(TargetOpcode::G_INTRINSIC_TRUNC)
868  .addDef(getOrCreateVReg(CI))
869  .addUse(getOrCreateVReg(*CI.getArgOperand(0)));
870  return true;
871  case Intrinsic::round:
872  MIRBuilder.buildInstr(TargetOpcode::G_INTRINSIC_ROUND)
873  .addDef(getOrCreateVReg(CI))
874  .addUse(getOrCreateVReg(*CI.getArgOperand(0)));
875  return true;
876  case Intrinsic::fma:
877  MIRBuilder.buildInstr(TargetOpcode::G_FMA)
878  .addDef(getOrCreateVReg(CI))
879  .addUse(getOrCreateVReg(*CI.getArgOperand(0)))
880  .addUse(getOrCreateVReg(*CI.getArgOperand(1)))
881  .addUse(getOrCreateVReg(*CI.getArgOperand(2)));
882  return true;
883  case Intrinsic::fmuladd: {
884  const TargetMachine &TM = MF->getTarget();
885  const TargetLowering &TLI = *MF->getSubtarget().getTargetLowering();
886  unsigned Dst = getOrCreateVReg(CI);
887  unsigned Op0 = getOrCreateVReg(*CI.getArgOperand(0));
888  unsigned Op1 = getOrCreateVReg(*CI.getArgOperand(1));
889  unsigned Op2 = getOrCreateVReg(*CI.getArgOperand(2));
891  TLI.isFMAFasterThanFMulAndFAdd(TLI.getValueType(*DL, CI.getType()))) {
892  // TODO: Revisit this to see if we should move this part of the
893  // lowering to the combiner.
894  MIRBuilder.buildInstr(TargetOpcode::G_FMA, Dst, Op0, Op1, Op2);
895  } else {
896  LLT Ty = getLLTForType(*CI.getType(), *DL);
897  auto FMul = MIRBuilder.buildInstr(TargetOpcode::G_FMUL, Ty, Op0, Op1);
898  MIRBuilder.buildInstr(TargetOpcode::G_FADD, Dst, FMul, Op2);
899  }
900  return true;
901  }
902  case Intrinsic::memcpy:
903  case Intrinsic::memmove:
904  case Intrinsic::memset:
905  return translateMemfunc(CI, MIRBuilder, ID);
906  case Intrinsic::eh_typeid_for: {
908  unsigned Reg = getOrCreateVReg(CI);
909  unsigned TypeID = MF->getTypeIDFor(GV);
910  MIRBuilder.buildConstant(Reg, TypeID);
911  return true;
912  }
913  case Intrinsic::objectsize: {
914  // If we don't know by now, we're never going to know.
915  const ConstantInt *Min = cast<ConstantInt>(CI.getArgOperand(1));
916 
917  MIRBuilder.buildConstant(getOrCreateVReg(CI), Min->isZero() ? -1ULL : 0);
918  return true;
919  }
920  case Intrinsic::stackguard:
921  getStackGuard(getOrCreateVReg(CI), MIRBuilder);
922  return true;
923  case Intrinsic::stackprotector: {
924  LLT PtrTy = getLLTForType(*CI.getArgOperand(0)->getType(), *DL);
925  unsigned GuardVal = MRI->createGenericVirtualRegister(PtrTy);
926  getStackGuard(GuardVal, MIRBuilder);
927 
928  AllocaInst *Slot = cast<AllocaInst>(CI.getArgOperand(1));
929  MIRBuilder.buildStore(
930  GuardVal, getOrCreateVReg(*Slot),
933  getOrCreateFrameIndex(*Slot)),
935  PtrTy.getSizeInBits() / 8, 8));
936  return true;
937  }
938  case Intrinsic::cttz:
939  case Intrinsic::ctlz: {
940  ConstantInt *Cst = cast<ConstantInt>(CI.getArgOperand(1));
941  bool isTrailing = ID == Intrinsic::cttz;
942  unsigned Opcode = isTrailing
943  ? Cst->isZero() ? TargetOpcode::G_CTTZ
944  : TargetOpcode::G_CTTZ_ZERO_UNDEF
945  : Cst->isZero() ? TargetOpcode::G_CTLZ
946  : TargetOpcode::G_CTLZ_ZERO_UNDEF;
947  MIRBuilder.buildInstr(Opcode)
948  .addDef(getOrCreateVReg(CI))
949  .addUse(getOrCreateVReg(*CI.getArgOperand(0)));
950  return true;
951  }
952  case Intrinsic::ctpop: {
953  MIRBuilder.buildInstr(TargetOpcode::G_CTPOP)
954  .addDef(getOrCreateVReg(CI))
955  .addUse(getOrCreateVReg(*CI.getArgOperand(0)));
956  return true;
957  }
958  }
959  return false;
960 }
961 
962 bool IRTranslator::translateInlineAsm(const CallInst &CI,
963  MachineIRBuilder &MIRBuilder) {
964  const InlineAsm &IA = cast<InlineAsm>(*CI.getCalledValue());
965  if (!IA.getConstraintString().empty())
966  return false;
967 
968  unsigned ExtraInfo = 0;
969  if (IA.hasSideEffects())
970  ExtraInfo |= InlineAsm::Extra_HasSideEffects;
971  if (IA.getDialect() == InlineAsm::AD_Intel)
972  ExtraInfo |= InlineAsm::Extra_AsmDialect;
973 
975  .addExternalSymbol(IA.getAsmString().c_str())
976  .addImm(ExtraInfo);
977 
978  return true;
979 }
980 
981 unsigned IRTranslator::packRegs(const Value &V,
982  MachineIRBuilder &MIRBuilder) {
983  ArrayRef<unsigned> Regs = getOrCreateVRegs(V);
984  ArrayRef<uint64_t> Offsets = *VMap.getOffsets(V);
985  LLT BigTy = getLLTForType(*V.getType(), *DL);
986 
987  if (Regs.size() == 1)
988  return Regs[0];
989 
990  unsigned Dst = MRI->createGenericVirtualRegister(BigTy);
991  MIRBuilder.buildUndef(Dst);
992  for (unsigned i = 0; i < Regs.size(); ++i) {
993  unsigned NewDst = MRI->createGenericVirtualRegister(BigTy);
994  MIRBuilder.buildInsert(NewDst, Dst, Regs[i], Offsets[i]);
995  Dst = NewDst;
996  }
997  return Dst;
998 }
999 
1000 void IRTranslator::unpackRegs(const Value &V, unsigned Src,
1001  MachineIRBuilder &MIRBuilder) {
1002  ArrayRef<unsigned> Regs = getOrCreateVRegs(V);
1003  ArrayRef<uint64_t> Offsets = *VMap.getOffsets(V);
1004 
1005  for (unsigned i = 0; i < Regs.size(); ++i)
1006  MIRBuilder.buildExtract(Regs[i], Src, Offsets[i]);
1007 }
1008 
1009 bool IRTranslator::translateCall(const User &U, MachineIRBuilder &MIRBuilder) {
1010  const CallInst &CI = cast<CallInst>(U);
1011  auto TII = MF->getTarget().getIntrinsicInfo();
1012  const Function *F = CI.getCalledFunction();
1013 
1014  // FIXME: support Windows dllimport function calls.
1015  if (F && F->hasDLLImportStorageClass())
1016  return false;
1017 
1018  if (CI.isInlineAsm())
1019  return translateInlineAsm(CI, MIRBuilder);
1020 
1022  if (F && F->isIntrinsic()) {
1023  ID = F->getIntrinsicID();
1024  if (TII && ID == Intrinsic::not_intrinsic)
1025  ID = static_cast<Intrinsic::ID>(TII->getIntrinsicID(F));
1026  }
1027 
1028  bool IsSplitType = valueIsSplit(CI);
1029  if (!F || !F->isIntrinsic() || ID == Intrinsic::not_intrinsic) {
1030  unsigned Res = IsSplitType ? MRI->createGenericVirtualRegister(
1031  getLLTForType(*CI.getType(), *DL))
1032  : getOrCreateVReg(CI);
1033 
1035  for (auto &Arg: CI.arg_operands())
1036  Args.push_back(packRegs(*Arg, MIRBuilder));
1037 
1038  MF->getFrameInfo().setHasCalls(true);
1039  bool Success = CLI->lowerCall(MIRBuilder, &CI, Res, Args, [&]() {
1040  return getOrCreateVReg(*CI.getCalledValue());
1041  });
1042 
1043  if (IsSplitType)
1044  unpackRegs(CI, Res, MIRBuilder);
1045  return Success;
1046  }
1047 
1048  assert(ID != Intrinsic::not_intrinsic && "unknown intrinsic");
1049 
1050  if (translateKnownIntrinsic(CI, ID, MIRBuilder))
1051  return true;
1052 
1053  unsigned Res = 0;
1054  if (!CI.getType()->isVoidTy()) {
1055  if (IsSplitType)
1056  Res =
1058  else
1059  Res = getOrCreateVReg(CI);
1060  }
1061  MachineInstrBuilder MIB =
1062  MIRBuilder.buildIntrinsic(ID, Res, !CI.doesNotAccessMemory());
1063 
1064  for (auto &Arg : CI.arg_operands()) {
1065  // Some intrinsics take metadata parameters. Reject them.
1066  if (isa<MetadataAsValue>(Arg))
1067  return false;
1068  MIB.addUse(packRegs(*Arg, MIRBuilder));
1069  }
1070 
1071  if (IsSplitType)
1072  unpackRegs(CI, Res, MIRBuilder);
1073 
1074  // Add a MachineMemOperand if it is a target mem intrinsic.
1075  const TargetLowering &TLI = *MF->getSubtarget().getTargetLowering();
1076  TargetLowering::IntrinsicInfo Info;
1077  // TODO: Add a GlobalISel version of getTgtMemIntrinsic.
1078  if (TLI.getTgtMemIntrinsic(Info, CI, *MF, ID)) {
1079  uint64_t Size = Info.memVT.getStoreSize();
1081  Info.flags, Size, Info.align));
1082  }
1083 
1084  return true;
1085 }
1086 
1087 bool IRTranslator::translateInvoke(const User &U,
1088  MachineIRBuilder &MIRBuilder) {
1089  const InvokeInst &I = cast<InvokeInst>(U);
1090  MCContext &Context = MF->getContext();
1091 
1092  const BasicBlock *ReturnBB = I.getSuccessor(0);
1093  const BasicBlock *EHPadBB = I.getSuccessor(1);
1094 
1095  const Value *Callee = I.getCalledValue();
1096  const Function *Fn = dyn_cast<Function>(Callee);
1097  if (isa<InlineAsm>(Callee))
1098  return false;
1099 
1100  // FIXME: support invoking patchpoint and statepoint intrinsics.
1101  if (Fn && Fn->isIntrinsic())
1102  return false;
1103 
1104  // FIXME: support whatever these are.
1106  return false;
1107 
1108  // FIXME: support Windows exception handling.
1109  if (!isa<LandingPadInst>(EHPadBB->front()))
1110  return false;
1111 
1112  // Emit the actual call, bracketed by EH_LABELs so that the MF knows about
1113  // the region covered by the try.
1114  MCSymbol *BeginSymbol = Context.createTempSymbol();
1115  MIRBuilder.buildInstr(TargetOpcode::EH_LABEL).addSym(BeginSymbol);
1116 
1117  unsigned Res =
1120  for (auto &Arg: I.arg_operands())
1121  Args.push_back(packRegs(*Arg, MIRBuilder));
1122 
1123  if (!CLI->lowerCall(MIRBuilder, &I, Res, Args,
1124  [&]() { return getOrCreateVReg(*I.getCalledValue()); }))
1125  return false;
1126 
1127  unpackRegs(I, Res, MIRBuilder);
1128 
1129  MCSymbol *EndSymbol = Context.createTempSymbol();
1130  MIRBuilder.buildInstr(TargetOpcode::EH_LABEL).addSym(EndSymbol);
1131 
1132  // FIXME: track probabilities.
1133  MachineBasicBlock &EHPadMBB = getMBB(*EHPadBB),
1134  &ReturnMBB = getMBB(*ReturnBB);
1135  MF->addInvoke(&EHPadMBB, BeginSymbol, EndSymbol);
1136  MIRBuilder.getMBB().addSuccessor(&ReturnMBB);
1137  MIRBuilder.getMBB().addSuccessor(&EHPadMBB);
1138  MIRBuilder.buildBr(ReturnMBB);
1139 
1140  return true;
1141 }
1142 
1143 bool IRTranslator::translateLandingPad(const User &U,
1144  MachineIRBuilder &MIRBuilder) {
1145  const LandingPadInst &LP = cast<LandingPadInst>(U);
1146 
1147  MachineBasicBlock &MBB = MIRBuilder.getMBB();
1148  addLandingPadInfo(LP, MBB);
1149 
1150  MBB.setIsEHPad();
1151 
1152  // If there aren't registers to copy the values into (e.g., during SjLj
1153  // exceptions), then don't bother.
1154  auto &TLI = *MF->getSubtarget().getTargetLowering();
1155  const Constant *PersonalityFn = MF->getFunction().getPersonalityFn();
1156  if (TLI.getExceptionPointerRegister(PersonalityFn) == 0 &&
1157  TLI.getExceptionSelectorRegister(PersonalityFn) == 0)
1158  return true;
1159 
1160  // If landingpad's return type is token type, we don't create DAG nodes
1161  // for its exception pointer and selector value. The extraction of exception
1162  // pointer or selector value from token type landingpads is not currently
1163  // supported.
1164  if (LP.getType()->isTokenTy())
1165  return true;
1166 
1167  // Add a label to mark the beginning of the landing pad. Deletion of the
1168  // landing pad can thus be detected via the MachineModuleInfo.
1170  .addSym(MF->addLandingPad(&MBB));
1171 
1172  LLT Ty = getLLTForType(*LP.getType(), *DL);
1173  unsigned Undef = MRI->createGenericVirtualRegister(Ty);
1174  MIRBuilder.buildUndef(Undef);
1175 
1176  SmallVector<LLT, 2> Tys;
1177  for (Type *Ty : cast<StructType>(LP.getType())->elements())
1178  Tys.push_back(getLLTForType(*Ty, *DL));
1179  assert(Tys.size() == 2 && "Only two-valued landingpads are supported");
1180 
1181  // Mark exception register as live in.
1182  unsigned ExceptionReg = TLI.getExceptionPointerRegister(PersonalityFn);
1183  if (!ExceptionReg)
1184  return false;
1185 
1186  MBB.addLiveIn(ExceptionReg);
1187  ArrayRef<unsigned> ResRegs = getOrCreateVRegs(LP);
1188  MIRBuilder.buildCopy(ResRegs[0], ExceptionReg);
1189 
1190  unsigned SelectorReg = TLI.getExceptionSelectorRegister(PersonalityFn);
1191  if (!SelectorReg)
1192  return false;
1193 
1194  MBB.addLiveIn(SelectorReg);
1195  unsigned PtrVReg = MRI->createGenericVirtualRegister(Tys[0]);
1196  MIRBuilder.buildCopy(PtrVReg, SelectorReg);
1197  MIRBuilder.buildCast(ResRegs[1], PtrVReg);
1198 
1199  return true;
1200 }
1201 
1202 bool IRTranslator::translateAlloca(const User &U,
1203  MachineIRBuilder &MIRBuilder) {
1204  auto &AI = cast<AllocaInst>(U);
1205 
1206  if (AI.isSwiftError())
1207  return false;
1208 
1209  if (AI.isStaticAlloca()) {
1210  unsigned Res = getOrCreateVReg(AI);
1211  int FI = getOrCreateFrameIndex(AI);
1212  MIRBuilder.buildFrameIndex(Res, FI);
1213  return true;
1214  }
1215 
1216  // FIXME: support stack probing for Windows.
1217  if (MF->getTarget().getTargetTriple().isOSWindows())
1218  return false;
1219 
1220  // Now we're in the harder dynamic case.
1221  Type *Ty = AI.getAllocatedType();
1222  unsigned Align =
1223  std::max((unsigned)DL->getPrefTypeAlignment(Ty), AI.getAlignment());
1224 
1225  unsigned NumElts = getOrCreateVReg(*AI.getArraySize());
1226 
1227  Type *IntPtrIRTy = DL->getIntPtrType(AI.getType());
1228  LLT IntPtrTy = getLLTForType(*IntPtrIRTy, *DL);
1229  if (MRI->getType(NumElts) != IntPtrTy) {
1230  unsigned ExtElts = MRI->createGenericVirtualRegister(IntPtrTy);
1231  MIRBuilder.buildZExtOrTrunc(ExtElts, NumElts);
1232  NumElts = ExtElts;
1233  }
1234 
1235  unsigned AllocSize = MRI->createGenericVirtualRegister(IntPtrTy);
1236  unsigned TySize =
1237  getOrCreateVReg(*ConstantInt::get(IntPtrIRTy, -DL->getTypeAllocSize(Ty)));
1238  MIRBuilder.buildMul(AllocSize, NumElts, TySize);
1239 
1240  LLT PtrTy = getLLTForType(*AI.getType(), *DL);
1241  auto &TLI = *MF->getSubtarget().getTargetLowering();
1242  unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
1243 
1244  unsigned SPTmp = MRI->createGenericVirtualRegister(PtrTy);
1245  MIRBuilder.buildCopy(SPTmp, SPReg);
1246 
1247  unsigned AllocTmp = MRI->createGenericVirtualRegister(PtrTy);
1248  MIRBuilder.buildGEP(AllocTmp, SPTmp, AllocSize);
1249 
1250  // Handle alignment. We have to realign if the allocation granule was smaller
1251  // than stack alignment, or the specific alloca requires more than stack
1252  // alignment.
1253  unsigned StackAlign =
1255  Align = std::max(Align, StackAlign);
1256  if (Align > StackAlign || DL->getTypeAllocSize(Ty) % StackAlign != 0) {
1257  // Round the size of the allocation up to the stack alignment size
1258  // by add SA-1 to the size. This doesn't overflow because we're computing
1259  // an address inside an alloca.
1260  unsigned AlignedAlloc = MRI->createGenericVirtualRegister(PtrTy);
1261  MIRBuilder.buildPtrMask(AlignedAlloc, AllocTmp, Log2_32(Align));
1262  AllocTmp = AlignedAlloc;
1263  }
1264 
1265  MIRBuilder.buildCopy(SPReg, AllocTmp);
1266  MIRBuilder.buildCopy(getOrCreateVReg(AI), AllocTmp);
1267 
1268  MF->getFrameInfo().CreateVariableSizedObject(Align ? Align : 1, &AI);
1270  return true;
1271 }
1272 
1273 bool IRTranslator::translateVAArg(const User &U, MachineIRBuilder &MIRBuilder) {
1274  // FIXME: We may need more info about the type. Because of how LLT works,
1275  // we're completely discarding the i64/double distinction here (amongst
1276  // others). Fortunately the ABIs I know of where that matters don't use va_arg
1277  // anyway but that's not guaranteed.
1278  MIRBuilder.buildInstr(TargetOpcode::G_VAARG)
1279  .addDef(getOrCreateVReg(U))
1280  .addUse(getOrCreateVReg(*U.getOperand(0)))
1281  .addImm(DL->getABITypeAlignment(U.getType()));
1282  return true;
1283 }
1284 
1285 bool IRTranslator::translateInsertElement(const User &U,
1286  MachineIRBuilder &MIRBuilder) {
1287  // If it is a <1 x Ty> vector, use the scalar as it is
1288  // not a legal vector type in LLT.
1289  if (U.getType()->getVectorNumElements() == 1) {
1290  unsigned Elt = getOrCreateVReg(*U.getOperand(1));
1291  auto &Regs = *VMap.getVRegs(U);
1292  if (Regs.empty()) {
1293  Regs.push_back(Elt);
1294  VMap.getOffsets(U)->push_back(0);
1295  } else {
1296  MIRBuilder.buildCopy(Regs[0], Elt);
1297  }
1298  return true;
1299  }
1300 
1301  unsigned Res = getOrCreateVReg(U);
1302  unsigned Val = getOrCreateVReg(*U.getOperand(0));
1303  unsigned Elt = getOrCreateVReg(*U.getOperand(1));
1304  unsigned Idx = getOrCreateVReg(*U.getOperand(2));
1305  MIRBuilder.buildInsertVectorElement(Res, Val, Elt, Idx);
1306  return true;
1307 }
1308 
1309 bool IRTranslator::translateExtractElement(const User &U,
1310  MachineIRBuilder &MIRBuilder) {
1311  // If it is a <1 x Ty> vector, use the scalar as it is
1312  // not a legal vector type in LLT.
1313  if (U.getOperand(0)->getType()->getVectorNumElements() == 1) {
1314  unsigned Elt = getOrCreateVReg(*U.getOperand(0));
1315  auto &Regs = *VMap.getVRegs(U);
1316  if (Regs.empty()) {
1317  Regs.push_back(Elt);
1318  VMap.getOffsets(U)->push_back(0);
1319  } else {
1320  MIRBuilder.buildCopy(Regs[0], Elt);
1321  }
1322  return true;
1323  }
1324  unsigned Res = getOrCreateVReg(U);
1325  unsigned Val = getOrCreateVReg(*U.getOperand(0));
1326  unsigned Idx = getOrCreateVReg(*U.getOperand(1));
1327  MIRBuilder.buildExtractVectorElement(Res, Val, Idx);
1328  return true;
1329 }
1330 
1331 bool IRTranslator::translateShuffleVector(const User &U,
1332  MachineIRBuilder &MIRBuilder) {
1333  MIRBuilder.buildInstr(TargetOpcode::G_SHUFFLE_VECTOR)
1334  .addDef(getOrCreateVReg(U))
1335  .addUse(getOrCreateVReg(*U.getOperand(0)))
1336  .addUse(getOrCreateVReg(*U.getOperand(1)))
1337  .addUse(getOrCreateVReg(*U.getOperand(2)));
1338  return true;
1339 }
1340 
1341 bool IRTranslator::translatePHI(const User &U, MachineIRBuilder &MIRBuilder) {
1342  const PHINode &PI = cast<PHINode>(U);
1343 
1345  for (auto Reg : getOrCreateVRegs(PI)) {
1346  auto MIB = MIRBuilder.buildInstr(TargetOpcode::G_PHI, Reg);
1347  Insts.push_back(MIB.getInstr());
1348  }
1349 
1350  PendingPHIs.emplace_back(&PI, std::move(Insts));
1351  return true;
1352 }
1353 
1354 bool IRTranslator::translateAtomicCmpXchg(const User &U,
1355  MachineIRBuilder &MIRBuilder) {
1356  const AtomicCmpXchgInst &I = cast<AtomicCmpXchgInst>(U);
1357 
1358  if (I.isWeak())
1359  return false;
1360 
1361  auto Flags = I.isVolatile() ? MachineMemOperand::MOVolatile
1364 
1365  Type *ResType = I.getType();
1366  Type *ValType = ResType->Type::getStructElementType(0);
1367 
1368  auto Res = getOrCreateVRegs(I);
1369  unsigned OldValRes = Res[0];
1370  unsigned SuccessRes = Res[1];
1371  unsigned Addr = getOrCreateVReg(*I.getPointerOperand());
1372  unsigned Cmp = getOrCreateVReg(*I.getCompareOperand());
1373  unsigned NewVal = getOrCreateVReg(*I.getNewValOperand());
1374 
1375  MIRBuilder.buildAtomicCmpXchgWithSuccess(
1376  OldValRes, SuccessRes, Addr, Cmp, NewVal,
1378  Flags, DL->getTypeStoreSize(ValType),
1379  getMemOpAlignment(I), AAMDNodes(), nullptr,
1381  I.getFailureOrdering()));
1382  return true;
1383 }
1384 
1385 bool IRTranslator::translateAtomicRMW(const User &U,
1386  MachineIRBuilder &MIRBuilder) {
1387  const AtomicRMWInst &I = cast<AtomicRMWInst>(U);
1388 
1389  auto Flags = I.isVolatile() ? MachineMemOperand::MOVolatile
1392 
1393  Type *ResType = I.getType();
1394 
1395  unsigned Res = getOrCreateVReg(I);
1396  unsigned Addr = getOrCreateVReg(*I.getPointerOperand());
1397  unsigned Val = getOrCreateVReg(*I.getValOperand());
1398 
1399  unsigned Opcode = 0;
1400  switch (I.getOperation()) {
1401  default:
1402  llvm_unreachable("Unknown atomicrmw op");
1403  return false;
1404  case AtomicRMWInst::Xchg:
1405  Opcode = TargetOpcode::G_ATOMICRMW_XCHG;
1406  break;
1407  case AtomicRMWInst::Add:
1408  Opcode = TargetOpcode::G_ATOMICRMW_ADD;
1409  break;
1410  case AtomicRMWInst::Sub:
1411  Opcode = TargetOpcode::G_ATOMICRMW_SUB;
1412  break;
1413  case AtomicRMWInst::And:
1414  Opcode = TargetOpcode::G_ATOMICRMW_AND;
1415  break;
1416  case AtomicRMWInst::Nand:
1417  Opcode = TargetOpcode::G_ATOMICRMW_NAND;
1418  break;
1419  case AtomicRMWInst::Or:
1420  Opcode = TargetOpcode::G_ATOMICRMW_OR;
1421  break;
1422  case AtomicRMWInst::Xor:
1423  Opcode = TargetOpcode::G_ATOMICRMW_XOR;
1424  break;
1425  case AtomicRMWInst::Max:
1426  Opcode = TargetOpcode::G_ATOMICRMW_MAX;
1427  break;
1428  case AtomicRMWInst::Min:
1429  Opcode = TargetOpcode::G_ATOMICRMW_MIN;
1430  break;
1431  case AtomicRMWInst::UMax:
1432  Opcode = TargetOpcode::G_ATOMICRMW_UMAX;
1433  break;
1434  case AtomicRMWInst::UMin:
1435  Opcode = TargetOpcode::G_ATOMICRMW_UMIN;
1436  break;
1437  }
1438 
1439  MIRBuilder.buildAtomicRMW(
1440  Opcode, Res, Addr, Val,
1442  Flags, DL->getTypeStoreSize(ResType),
1443  getMemOpAlignment(I), AAMDNodes(), nullptr,
1444  I.getSyncScopeID(), I.getOrdering()));
1445  return true;
1446 }
1447 
1448 void IRTranslator::finishPendingPhis() {
1449  for (auto &Phi : PendingPHIs) {
1450  const PHINode *PI = Phi.first;
1451  ArrayRef<MachineInstr *> ComponentPHIs = Phi.second;
1452 
1453  // All MachineBasicBlocks exist, add them to the PHI. We assume IRTranslator
1454  // won't create extra control flow here, otherwise we need to find the
1455  // dominating predecessor here (or perhaps force the weirder IRTranslators
1456  // to provide a simple boundary).
1457  SmallSet<const BasicBlock *, 4> HandledPreds;
1458 
1459  for (unsigned i = 0; i < PI->getNumIncomingValues(); ++i) {
1460  auto IRPred = PI->getIncomingBlock(i);
1461  if (HandledPreds.count(IRPred))
1462  continue;
1463 
1464  HandledPreds.insert(IRPred);
1465  ArrayRef<unsigned> ValRegs = getOrCreateVRegs(*PI->getIncomingValue(i));
1466  for (auto Pred : getMachinePredBBs({IRPred, PI->getParent()})) {
1467  assert(Pred->isSuccessor(ComponentPHIs[0]->getParent()) &&
1468  "incorrect CFG at MachineBasicBlock level");
1469  for (unsigned j = 0; j < ValRegs.size(); ++j) {
1470  MachineInstrBuilder MIB(*MF, ComponentPHIs[j]);
1471  MIB.addUse(ValRegs[j]);
1472  MIB.addMBB(Pred);
1473  }
1474  }
1475  }
1476  }
1477 }
1478 
1479 bool IRTranslator::valueIsSplit(const Value &V,
1481  SmallVector<LLT, 4> SplitTys;
1482  if (Offsets && !Offsets->empty())
1483  Offsets->clear();
1484  computeValueLLTs(*DL, *V.getType(), SplitTys, Offsets);
1485  return SplitTys.size() > 1;
1486 }
1487 
1488 bool IRTranslator::translate(const Instruction &Inst) {
1489  CurBuilder.setDebugLoc(Inst.getDebugLoc());
1490  switch(Inst.getOpcode()) {
1491 #define HANDLE_INST(NUM, OPCODE, CLASS) \
1492  case Instruction::OPCODE: return translate##OPCODE(Inst, CurBuilder);
1493 #include "llvm/IR/Instruction.def"
1494  default:
1495  return false;
1496  }
1497 }
1498 
1499 bool IRTranslator::translate(const Constant &C, unsigned Reg) {
1500  if (auto CI = dyn_cast<ConstantInt>(&C))
1501  EntryBuilder.buildConstant(Reg, *CI);
1502  else if (auto CF = dyn_cast<ConstantFP>(&C))
1503  EntryBuilder.buildFConstant(Reg, *CF);
1504  else if (isa<UndefValue>(C))
1505  EntryBuilder.buildUndef(Reg);
1506  else if (isa<ConstantPointerNull>(C)) {
1507  // As we are trying to build a constant val of 0 into a pointer,
1508  // insert a cast to make them correct with respect to types.
1509  unsigned NullSize = DL->getTypeSizeInBits(C.getType());
1510  auto *ZeroTy = Type::getIntNTy(C.getContext(), NullSize);
1511  auto *ZeroVal = ConstantInt::get(ZeroTy, 0);
1512  unsigned ZeroReg = getOrCreateVReg(*ZeroVal);
1513  EntryBuilder.buildCast(Reg, ZeroReg);
1514  } else if (auto GV = dyn_cast<GlobalValue>(&C))
1515  EntryBuilder.buildGlobalValue(Reg, GV);
1516  else if (auto CAZ = dyn_cast<ConstantAggregateZero>(&C)) {
1517  if (!CAZ->getType()->isVectorTy())
1518  return false;
1519  // Return the scalar if it is a <1 x Ty> vector.
1520  if (CAZ->getNumElements() == 1)
1521  return translate(*CAZ->getElementValue(0u), Reg);
1522  std::vector<unsigned> Ops;
1523  for (unsigned i = 0; i < CAZ->getNumElements(); ++i) {
1524  Constant &Elt = *CAZ->getElementValue(i);
1525  Ops.push_back(getOrCreateVReg(Elt));
1526  }
1527  EntryBuilder.buildMerge(Reg, Ops);
1528  } else if (auto CV = dyn_cast<ConstantDataVector>(&C)) {
1529  // Return the scalar if it is a <1 x Ty> vector.
1530  if (CV->getNumElements() == 1)
1531  return translate(*CV->getElementAsConstant(0), Reg);
1532  std::vector<unsigned> Ops;
1533  for (unsigned i = 0; i < CV->getNumElements(); ++i) {
1534  Constant &Elt = *CV->getElementAsConstant(i);
1535  Ops.push_back(getOrCreateVReg(Elt));
1536  }
1537  EntryBuilder.buildMerge(Reg, Ops);
1538  } else if (auto CE = dyn_cast<ConstantExpr>(&C)) {
1539  switch(CE->getOpcode()) {
1540 #define HANDLE_INST(NUM, OPCODE, CLASS) \
1541  case Instruction::OPCODE: return translate##OPCODE(*CE, EntryBuilder);
1542 #include "llvm/IR/Instruction.def"
1543  default:
1544  return false;
1545  }
1546  } else if (auto CV = dyn_cast<ConstantVector>(&C)) {
1547  if (CV->getNumOperands() == 1)
1548  return translate(*CV->getOperand(0), Reg);
1550  for (unsigned i = 0; i < CV->getNumOperands(); ++i) {
1551  Ops.push_back(getOrCreateVReg(*CV->getOperand(i)));
1552  }
1553  EntryBuilder.buildMerge(Reg, Ops);
1554  } else if (auto *BA = dyn_cast<BlockAddress>(&C)) {
1555  EntryBuilder.buildBlockAddress(Reg, BA);
1556  } else
1557  return false;
1558 
1559  return true;
1560 }
1561 
1562 void IRTranslator::finalizeFunction() {
1563  // Release the memory used by the different maps we
1564  // needed during the translation.
1565  PendingPHIs.clear();
1566  VMap.reset();
1567  FrameIndices.clear();
1568  MachinePreds.clear();
1569  // MachineIRBuilder::DebugLoc can outlive the DILocation it holds. Clear it
1570  // to avoid accessing free’d memory (in runOnMachineFunction) and to avoid
1571  // destroying it twice (in ~IRTranslator() and ~LLVMContext())
1572  EntryBuilder = MachineIRBuilder();
1573  CurBuilder = MachineIRBuilder();
1574 }
1575 
1577  MF = &CurMF;
1578  const Function &F = MF->getFunction();
1579  if (F.empty())
1580  return false;
1581  CLI = MF->getSubtarget().getCallLowering();
1582  CurBuilder.setMF(*MF);
1583  EntryBuilder.setMF(*MF);
1584  MRI = &MF->getRegInfo();
1585  DL = &F.getParent()->getDataLayout();
1586  TPC = &getAnalysis<TargetPassConfig>();
1587  ORE = llvm::make_unique<OptimizationRemarkEmitter>(&F);
1588 
1589  assert(PendingPHIs.empty() && "stale PHIs");
1590 
1591  if (!DL->isLittleEndian()) {
1592  // Currently we don't properly handle big endian code.
1593  OptimizationRemarkMissed R("gisel-irtranslator", "GISelFailure",
1594  F.getSubprogram(), &F.getEntryBlock());
1595  R << "unable to translate in big endian mode";
1596  reportTranslationError(*MF, *TPC, *ORE, R);
1597  }
1598 
1599  // Release the per-function state when we return, whether we succeeded or not.
1600  auto FinalizeOnReturn = make_scope_exit([this]() { finalizeFunction(); });
1601 
1602  // Setup a separate basic-block for the arguments and constants
1603  MachineBasicBlock *EntryBB = MF->CreateMachineBasicBlock();
1604  MF->push_back(EntryBB);
1605  EntryBuilder.setMBB(*EntryBB);
1606 
1607  // Create all blocks, in IR order, to preserve the layout.
1608  for (const BasicBlock &BB: F) {
1609  auto *&MBB = BBToMBB[&BB];
1610 
1611  MBB = MF->CreateMachineBasicBlock(&BB);
1612  MF->push_back(MBB);
1613 
1614  if (BB.hasAddressTaken())
1615  MBB->setHasAddressTaken();
1616  }
1617 
1618  // Make our arguments/constants entry block fallthrough to the IR entry block.
1619  EntryBB->addSuccessor(&getMBB(F.front()));
1620 
1621  // Lower the actual args into this basic block.
1622  SmallVector<unsigned, 8> VRegArgs;
1623  for (const Argument &Arg: F.args()) {
1624  if (DL->getTypeStoreSize(Arg.getType()) == 0)
1625  continue; // Don't handle zero sized types.
1626  VRegArgs.push_back(
1628  }
1629 
1630  // We don't currently support translating swifterror or swiftself functions.
1631  for (auto &Arg : F.args()) {
1632  if (Arg.hasSwiftErrorAttr() || Arg.hasSwiftSelfAttr()) {
1633  OptimizationRemarkMissed R("gisel-irtranslator", "GISelFailure",
1634  F.getSubprogram(), &F.getEntryBlock());
1635  R << "unable to lower arguments due to swifterror/swiftself: "
1636  << ore::NV("Prototype", F.getType());
1637  reportTranslationError(*MF, *TPC, *ORE, R);
1638  return false;
1639  }
1640  }
1641 
1642  if (!CLI->lowerFormalArguments(EntryBuilder, F, VRegArgs)) {
1643  OptimizationRemarkMissed R("gisel-irtranslator", "GISelFailure",
1644  F.getSubprogram(), &F.getEntryBlock());
1645  R << "unable to lower arguments: " << ore::NV("Prototype", F.getType());
1646  reportTranslationError(*MF, *TPC, *ORE, R);
1647  return false;
1648  }
1649 
1650  auto ArgIt = F.arg_begin();
1651  for (auto &VArg : VRegArgs) {
1652  // If the argument is an unsplit scalar then don't use unpackRegs to avoid
1653  // creating redundant copies.
1654  if (!valueIsSplit(*ArgIt, VMap.getOffsets(*ArgIt))) {
1655  auto &VRegs = *VMap.getVRegs(cast<Value>(*ArgIt));
1656  assert(VRegs.empty() && "VRegs already populated?");
1657  VRegs.push_back(VArg);
1658  } else {
1659  unpackRegs(*ArgIt, VArg, EntryBuilder);
1660  }
1661  ArgIt++;
1662  }
1663 
1664  // Need to visit defs before uses when translating instructions.
1666  for (const BasicBlock *BB : RPOT) {
1667  MachineBasicBlock &MBB = getMBB(*BB);
1668  // Set the insertion point of all the following translations to
1669  // the end of this basic block.
1670  CurBuilder.setMBB(MBB);
1671 
1672  for (const Instruction &Inst : *BB) {
1673  if (translate(Inst))
1674  continue;
1675 
1676  OptimizationRemarkMissed R("gisel-irtranslator", "GISelFailure",
1677  Inst.getDebugLoc(), BB);
1678  R << "unable to translate instruction: " << ore::NV("Opcode", &Inst);
1679 
1680  if (ORE->allowExtraAnalysis("gisel-irtranslator")) {
1681  std::string InstStrStorage;
1682  raw_string_ostream InstStr(InstStrStorage);
1683  InstStr << Inst;
1684 
1685  R << ": '" << InstStr.str() << "'";
1686  }
1687 
1688  reportTranslationError(*MF, *TPC, *ORE, R);
1689  return false;
1690  }
1691  }
1692 
1693  finishPendingPhis();
1694 
1695  // Merge the argument lowering and constants block with its single
1696  // successor, the LLVM-IR entry block. We want the basic block to
1697  // be maximal.
1698  assert(EntryBB->succ_size() == 1 &&
1699  "Custom BB used for lowering should have only one successor");
1700  // Get the successor of the current entry block.
1701  MachineBasicBlock &NewEntryBB = **EntryBB->succ_begin();
1702  assert(NewEntryBB.pred_size() == 1 &&
1703  "LLVM-IR entry block has a predecessor!?");
1704  // Move all the instruction from the current entry block to the
1705  // new entry block.
1706  NewEntryBB.splice(NewEntryBB.begin(), EntryBB, EntryBB->begin(),
1707  EntryBB->end());
1708 
1709  // Update the live-in information for the new entry block.
1710  for (const MachineBasicBlock::RegisterMaskPair &LiveIn : EntryBB->liveins())
1711  NewEntryBB.addLiveIn(LiveIn);
1712  NewEntryBB.sortUniqueLiveIns();
1713 
1714  // Get rid of the now empty basic block.
1715  EntryBB->removeSuccessor(&NewEntryBB);
1716  MF->remove(EntryBB);
1717  MF->DeleteMachineBasicBlock(EntryBB);
1718 
1719  assert(&MF->front() == &NewEntryBB &&
1720  "New entry wasn't next in the list of basic block!");
1721 
1722  // Initialize stack protector information.
1723  StackProtector &SP = getAnalysis<StackProtector>();
1724  SP.copyToMachineFrameInfo(MF->getFrameInfo());
1725 
1726  return false;
1727 }
MachineInstrBuilder buildCopy(unsigned Res, unsigned Op)
Build and insert Res = COPY Op.
uint64_t CallInst * C
void initializeIRTranslatorPass(PassRegistry &)
Return a value (possibly void), from a function.
Value * getValueOperand()
Definition: Instructions.h:399
bool isIntrinsic() const
isIntrinsic - Returns true if the function&#39;s name starts with "llvm.".
Definition: Function.h:199
void push_back(const T &Elt)
Definition: SmallVector.h:218
A parsed version of the target data layout string in and methods for querying it. ...
Definition: DataLayout.h:111
constexpr char Align[]
Key for Kernel::Arg::Metadata::mAlign.
Function * getCalledFunction() const
Return the function called, or null if this is an indirect function invocation.
This class is the base class for the comparison instructions.
Definition: InstrTypes.h:675
bool empty() const
Definition: Function.h:662
MachineInstrBuilder buildIndirectDbgValue(unsigned Reg, const MDNode *Variable, const MDNode *Expr)
Build and insert a DBG_VALUE instruction expressing the fact that the associated Variable lives in me...
static IntegerType * getInt1Ty(LLVMContext &C)
Definition: Type.cpp:173
Diagnostic information for missed-optimization remarks.
This instruction extracts a struct member or array element value from an aggregate value...
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
*p = old <signed v ? old : v
Definition: Instructions.h:711
iterator_range< CaseIt > cases()
Iteration adapter for range-for loops.
GCNRegPressure max(const GCNRegPressure &P1, const GCNRegPressure &P2)
This class represents an incoming formal argument to a Function.
Definition: Argument.h:30
LLVMContext & Context
DiagnosticInfoOptimizationBase::Argument NV
This represents the llvm.dbg.label instruction.
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:139
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
MachineInstrBuilder buildGEP(unsigned Res, unsigned Op0, unsigned Op1)
Build and insert Res = G_GEP Op0, Op1.
unsigned countOperandBundlesOfType(StringRef Name) const
Return the number of operand bundles with the tag Name attached to this instruction.
Definition: InstrTypes.h:1199
void getSelectionDAGFallbackAnalysisUsage(AnalysisUsage &AU)
Modify analysis usage so it preserves passes required for the SelectionDAG fallback.
Definition: Utils.cpp:238
MCSymbol * addLandingPad(MachineBasicBlock *LandingPad)
Add a new panding pad. Returns the label ID for the landing pad entry.
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:42
bool isSized(SmallPtrSetImpl< Type *> *Visited=nullptr) const
Return true if it makes sense to take the size of this type.
Definition: Type.h:265
iterator begin() const
Definition: ArrayRef.h:137
MachineInstrBuilder buildInsertVectorElement(unsigned Res, unsigned Val, unsigned Elt, unsigned Idx)
Build and insert Res = G_INSERT_VECTOR_ELT Val, Elt, Idx.
an instruction that atomically checks whether a specified value is in a memory location, and, if it is, stores a new value there.
Definition: Instructions.h:518
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
MachineInstrBuilder buildStore(unsigned Val, unsigned Addr, MachineMemOperand &MMO)
Build and insert G_STORE Val, Addr, MMO.
void addLandingPadInfo(const LandingPadInst &I, MachineBasicBlock &MBB)
Extract the exception handling information from the landingpad instruction and add them to the specif...
const StructLayout * getStructLayout(StructType *Ty) const
Returns a StructLayout object, indicating the alignment of the struct, its size, and the offsets of i...
Definition: DataLayout.cpp:588
MachineInstrBuilder buildFConstant(DstType &&Res, const ConstantFP &Val)
Build and insert Res = G_FCONSTANT Val.
MachineInstrBuilder buildUndef(DstType &&Res)
Build and insert Res = IMPLICIT_DEF.
IRTranslator LLVM IR static false void reportTranslationError(MachineFunction &MF, const TargetPassConfig &TPC, OptimizationRemarkEmitter &ORE, OptimizationRemarkMissed &R)
This class represents a function call, abstracting a target machine&#39;s calling convention.
unsigned Reg
This file contains the declarations for metadata subclasses.
Value * getCondition() const
virtual const TargetLowering * getTargetLowering() const
static uint64_t round(uint64_t Acc, uint64_t Input)
Definition: xxhash.cpp:57
SyncScope::ID getSyncScopeID() const
Returns the synchronization scope ID of this store instruction.
Definition: Instructions.h:374
gep_type_iterator gep_type_end(const User *GEP)
const std::string & getAsmString() const
Definition: InlineAsm.h:81
*p = old <unsigned v ? old : v
Definition: Instructions.h:715
bool isSwiftError() const
Return true if this alloca is used as a swifterror argument to a call.
Definition: Instructions.h:136
AtomicOrdering getOrdering() const
Returns the ordering constraint of this load instruction.
Definition: Instructions.h:237
Offsets
Offsets in bytes from the start of the input buffer.
Definition: SIInstrInfo.h:954
*p = old >unsigned v ? old : v
Definition: Instructions.h:713
LLT getType(unsigned Reg) const
Get the low-level type of Reg or LLT{} if Reg is not a generic (target independent) virtual register...
LLVM_NODISCARD detail::scope_exit< typename std::decay< Callable >::type > make_scope_exit(Callable &&F)
Definition: ScopeExit.h:59
static const MCPhysReg VRegs[32]
LLVMContext & getContext() const
All values hold a context through their type.
Definition: Value.cpp:714
bool hasDLLImportStorageClass() const
Definition: GlobalValue.h:262
BasicBlock * getSuccessor(unsigned i) const
unsigned getPointerSizeInBits(unsigned AS=0) const
Layout pointer size, in bits FIXME: The defaults need to be removed once all of the backends/clients ...
Definition: DataLayout.h:360
unsigned const TargetRegisterInfo * TRI
F(f)
An instruction for reading from memory.
Definition: Instructions.h:168
an instruction that atomically reads a memory location, combines it with another value, and then stores the result back.
Definition: Instructions.h:681
Value * getCondition() const
bool isVectorTy() const
True if this is an instance of VectorType.
Definition: Type.h:230
CallingConv::ID getCallingConv() const
getCallingConv/setCallingConv - Get or set the calling convention of this function call...
void setMBB(MachineBasicBlock &MBB)
Set the insertion point to the end of MBB.
unsigned getTypeIDFor(const GlobalValue *TI)
Return the type id for the specified typeinfo. This is function wide.
MachineInstrBuilder buildBrCond(unsigned Tst, MachineBasicBlock &Dest)
Build and insert G_BRCOND Tst, Dest.
GlobalValue * ExtractTypeInfo(Value *V)
ExtractTypeInfo - Returns the type info, possibly bitcast, encoded in V.
Definition: Analysis.cpp:118
*p = old >signed v ? old : v
Definition: Instructions.h:709
void DeleteMachineBasicBlock(MachineBasicBlock *MBB)
DeleteMachineBasicBlock - Delete the given MachineBasicBlock.
unsigned getPointerABIAlignment(unsigned AS) const
Layout pointer alignment.
Definition: DataLayout.cpp:611
virtual bool getTgtMemIntrinsic(IntrinsicInfo &, const CallInst &, MachineFunction &, unsigned) const
Given an intrinsic, checks if on the target the intrinsic will need to map to a MemIntrinsicNode (tou...
int CreateStackObject(uint64_t Size, unsigned Alignment, bool isSpillSlot, const AllocaInst *Alloca=nullptr, uint8_t ID=0)
Create a new statically sized stack object, returning a nonnegative identifier to represent it...
bool runOnMachineFunction(MachineFunction &MF) override
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
static Constant * getNullValue(Type *Ty)
Constructor to create a &#39;0&#39; constant of arbitrary type.
Definition: Constants.cpp:268
AtomicOrdering getFailureOrdering() const
Returns the failure ordering constraint of this cmpxchg instruction.
Definition: Instructions.h:585
bool hasSideEffects() const
Definition: InlineAsm.h:67
AnalysisUsage & addRequired()
Used to lazily calculate structure layout information for a target machine, based on the DataLayout s...
Definition: DataLayout.h:521
#define INITIALIZE_PASS_DEPENDENCY(depName)
Definition: PassSupport.h:51
bool isVolatile() const
Return true if this is a load from a volatile memory location.
Definition: Instructions.h:221
A description of a memory reference used in the backend.
const DataLayout & getDataLayout() const
Get the data layout for the module&#39;s target platform.
Definition: Module.cpp:363
#define DEBUG_TYPE
virtual bool lowerFormalArguments(MachineIRBuilder &MIRBuilder, const Function &F, ArrayRef< unsigned > VRegs) const
This hook must be implemented to lower the incoming (formal) arguments, described by Args...
Definition: CallLowering.h:159
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
const HexagonInstrInfo * TII
unsigned getAlignment() const
Return the alignment of the memory that is being allocated by the instruction.
Definition: Instructions.h:113
PointerType * getType() const
Overload to return most specific pointer type.
Definition: Instructions.h:97
Class to represent struct types.
Definition: DerivedTypes.h:201
const TargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
DILabel * getLabel() const
void setMF(MachineFunction &)
BinOp getOperation() const
Definition: Instructions.h:734
const MachineInstrBuilder & addUse(unsigned RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register use operand.
bool isWeak() const
Return true if this cmpxchg may spuriously fail.
Definition: Instructions.h:559
MachineInstrBuilder buildBrIndirect(unsigned Tgt)
Build and insert G_BRINDIRECT Tgt.
TypeID
Definitions of all of the base types for the Type system.
Definition: Type.h:55
The memory access is dereferenceable (i.e., doesn&#39;t trap).
bool hasVarSizedObjects() const
This method may be called any time after instruction selection is complete to determine if the stack ...
bool isVolatile() const
Return true if this is a cmpxchg from a volatile memory location.
Definition: Instructions.h:547
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, uint64_t s, unsigned base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
Target-Independent Code Generator Pass Configuration Options.
INLINEASM - Represents an inline asm block.
Definition: ISDOpcodes.h:627
MachineInstrBuilder buildConstDbgValue(const Constant &C, const MDNode *Variable, const MDNode *Expr)
Build and insert a DBG_VALUE instructions specifying that Variable is given by C (suitably modified b...
Context object for machine code objects.
Definition: MCContext.h:63
MachineInstrBuilder buildDbgLabel(const MDNode *Label)
Build and insert a DBG_LABEL instructions specifying that Label is given.
Type * getType() const
All values are typed, get the type of this value.
Definition: Value.h:245
MachineInstrBuilder buildPtrMask(unsigned Res, unsigned Op0, uint32_t NumBits)
Build and insert Res = G_PTR_MASK Op0, NumBits.
Definition: Lint.cpp:84
AtomicOrdering getSuccessOrdering() const
Returns the success ordering constraint of this cmpxchg instruction.
Definition: Instructions.h:572
Class to represent array types.
Definition: DerivedTypes.h:369
bool isLittleEndian() const
Layout endianness...
Definition: DataLayout.h:221
unsigned getOpcode() const
Returns a member of one of the enums like Instruction::Add.
Definition: Instruction.h:126
auto lower_bound(R &&Range, ForwardIt I) -> decltype(adl_begin(Range))
Provide wrappers to std::lower_bound which take ranges instead of having to pass begin/end explicitly...
Definition: STLExtras.h:1138
An instruction for storing to memory.
Definition: Instructions.h:310
static LLT scalar(unsigned SizeInBits)
Get a low-level scalar or aggregate "bag of bits".
MachineInstrBuilder buildGlobalValue(unsigned Res, const GlobalValue *GV)
Build and insert Res = G_GLOBAL_VALUE GV.
amdgpu Simplify well known AMD library false Value * Callee
MachineBasicBlock * CreateMachineBasicBlock(const BasicBlock *bb=nullptr)
CreateMachineBasicBlock - Allocate a new MachineBasicBlock.
Value * getOperand(unsigned i) const
Definition: User.h:170
bool doesNotAccessMemory() const
Determine if the call does not access memory.
Value * getOperand(unsigned i_nocapture) const
MCContext & getContext() const
bool isOSWindows() const
Tests whether the OS is Windows.
Definition: Triple.h:563
bool isVoidTy() const
Return true if this is &#39;void&#39;.
Definition: Type.h:141
The memory access is volatile.
bool isValidLocationForIntrinsic(const DILocation *DL) const
Check that a location is valid for this label.
const BasicBlock & getEntryBlock() const
Definition: Function.h:640
constexpr uint64_t MinAlign(uint64_t A, uint64_t B)
A and B are either alignments or offsets.
Definition: MathExtras.h:610
IntegerType * getIntPtrType(LLVMContext &C, unsigned AddressSpace=0) const
Returns an integer type with size at least as big as that of a pointer in the given address space...
Definition: DataLayout.cpp:742
MachineInstrBuilder buildIntrinsic(Intrinsic::ID ID, unsigned Res, bool HasSideEffects)
Build and insert either a G_INTRINSIC (if HasSideEffects is false) or G_INTRINSIC_W_SIDE_EFFECTS inst...
FPOpFusion::FPOpFusionMode AllowFPOpFusion
AllowFPOpFusion - This flag is set by the -fuse-fp-ops=xxx option.
The landingpad instruction holds all of the information necessary to generate correct exception handl...
MachineInstrBuilder buildZExtOrTrunc(DstTy &&Dst, UseArgTy &&Use)
Build and insert Res = G_ZEXT Op, Res = G_TRUNC Op, or Res = COPY Op depending on the differing sizes...
* if(!EatIfPresent(lltok::kw_thread_local)) return false
ParseOptionalThreadLocal := /*empty.
SyncScope::ID getSyncScopeID() const
Returns the synchronization scope ID of this rmw instruction.
Definition: Instructions.h:774
CodeGenOpt::Level getOptLevel() const
Returns the optimization level: None, Less, Default, or Aggressive.
LLVM Basic Block Representation.
Definition: BasicBlock.h:59
void addInvoke(MachineBasicBlock *LandingPad, MCSymbol *BeginLabel, MCSymbol *EndLabel)
Provide the begin and end labels of an invoke style call and associate it with a try landing pad bloc...
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:46
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
virtual bool lowerCall(MachineIRBuilder &MIRBuilder, CallingConv::ID CallConv, const MachineOperand &Callee, const ArgInfo &OrigRet, ArrayRef< ArgInfo > OrigArgs) const
This hook must be implemented to lower the given call instruction, including argument and return valu...
Definition: CallLowering.h:185
DISubprogram * getSubprogram() const
Get the attached subprogram.
Definition: Metadata.cpp:1508
Conditional or Unconditional Branch instruction.
Value * getAddress() const
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:149
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
This is an important base class in LLVM.
Definition: Constant.h:42
MachineInstrBuilder buildBr(MachineBasicBlock &Dest)
Build and insert G_BR Dest.
Value * getValue() const
SmallSet - This maintains a set of unique values, optimizing for the case when the set is small (less...
Definition: SmallSet.h:135
This file contains the declarations for the subclasses of Constant, which represent the different fla...
const Instruction & front() const
Definition: BasicBlock.h:276
Indirect Branch Instruction.
BasicBlock * getDefaultDest() const
DIExpression * getExpression() const
unsigned getPrefTypeAlignment(Type *Ty) const
Returns the preferred stack/global alignment for the specified type.
Definition: DataLayout.cpp:732
MachineInstrBuilder buildExtract(unsigned Res, unsigned Src, uint64_t Index)
Build and insert `Res0, ...
bool isValidLocationForIntrinsic(const DILocation *DL) const
Check that a location is valid for this variable.
Represent the analysis usage information of a pass.
MachineInstrBuilder buildDirectDbgValue(unsigned Reg, const MDNode *Variable, const MDNode *Expr)
Build and insert a DBG_VALUE instruction expressing the fact that the associated Variable lives in Re...
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
Definition: InstrTypes.h:685
virtual const CallLowering * getCallLowering() const
const Triple & getTargetTriple() const
Value * getPointerOperand()
Definition: Instructions.h:274
MachineInstrBuilder buildExtractVectorElement(unsigned Res, unsigned Val, unsigned Idx)
Build and insert Res = G_EXTRACT_VECTOR_ELT Val, Idx.
void remove(iterator MBBI)
self_iterator getIterator()
Definition: ilist_node.h:82
DebugLoc getDebugLoc()
Get the current instruction&#39;s debug location.
std::pair< NoneType, bool > insert(const T &V)
insert - Insert an element into the set if it isn&#39;t already there.
Definition: SmallSet.h:181
const MachineInstrBuilder & addSym(MCSymbol *Sym, unsigned char TargetFlags=0) const
static double log2(double V)
static Constant * getAllOnesValue(Type *Ty)
Definition: Constants.cpp:322
1 1 1 1 Always true (always folded)
Definition: InstrTypes.h:702
SyncScope::ID getSyncScopeID() const
Returns the synchronization scope ID of this cmpxchg instruction.
Definition: Instructions.h:598
iterator_range< User::op_iterator > arg_operands()
Iteration adapter for range-for loops.
BasicBlock * getSuccessor(unsigned i) const
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
const MachineBasicBlock & front() const
const Value * getArraySize() const
Get the number of elements allocated.
Definition: Instructions.h:93
size_t size() const
Definition: SmallVector.h:53
Value * getIncomingValue(unsigned i) const
Return incoming value number x.
AtomicOrdering getOrdering() const
Returns the ordering constraint of this rmw instruction.
Definition: Instructions.h:761
This class contains a discriminated union of information about pointers in memory operands...
unsigned getStackAlignment() const
getStackAlignment - This method returns the number of bytes to which the stack pointer must be aligne...
std::string & str()
Flushes the stream contents to the target string and returns the string&#39;s reference.
Definition: raw_ostream.h:499
INITIALIZE_PASS_END(RegBankSelect, DEBUG_TYPE, "Assign register bank of generic virtual registers", false, false) RegBankSelect
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
EVT getValueType(const DataLayout &DL, Type *Ty, bool AllowUnknown=false) const
Return the EVT corresponding to this LLVM type.
const std::string & getConstraintString() const
Definition: InlineAsm.h:82
Type * getAllocatedType() const
Return the type that is being allocated by the instruction.
Definition: Instructions.h:106
EH_LABEL - Represents a label in mid basic block used to track locations needed for debug and excepti...
Definition: ISDOpcodes.h:632
void copyIRFlags(const Instruction &I)
Copy all flags to MachineInst MIFlags.
LLT getLLTForType(Type &Ty, const DataLayout &DL)
Construct a low-level type based on an LLVM type.
The memory access writes data.
unsigned createGenericVirtualRegister(LLT Ty, StringRef Name="")
Create and return a new generic virtual register with low-level type Ty.
bool hasAddressTaken() const
Returns true if there are any uses of this basic block other than direct branches, switches, etc.
Definition: BasicBlock.h:387
Value * getValOperand()
Definition: Instructions.h:787
MachineInstrBuilder buildSExtOrTrunc(DstTy &&Dst, UseArgTy &&Use)
Build and insert Res = G_SEXT Op, Res = G_TRUNC Op, or Res = COPY Op depending on the differing sizes...
Predicate getPredicate(unsigned Condition, unsigned Hint)
Return predicate consisting of specified condition and hint bits.
Definition: PPCPredicates.h:88
unsigned getNumOperands() const
Definition: User.h:192
void addSuccessor(MachineBasicBlock *Succ, BranchProbability Prob=BranchProbability::getUnknown())
Add Succ as a successor of this MachineBasicBlock.
This is the shared class of boolean and integer constants.
Definition: Constants.h:84
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:847
iterator end() const
Definition: ArrayRef.h:138
unsigned getABITypeAlignment(Type *Ty) const
Returns the minimum ABI-required alignment for the specified type.
Definition: DataLayout.cpp:722
bool isAggregateType() const
Return true if the type is an aggregate type.
Definition: Type.h:258
unsigned getSizeInBits() const
Returns the total size of the type. Must only be called on sized types.
static uint64_t getOffsetFromIndices(const User &U, const DataLayout &DL)
const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const
A collection of metadata nodes that might be associated with a memory access used by the alias-analys...
Definition: Metadata.h:644
static IntegerType * getIntNTy(LLVMContext &C, unsigned N)
Definition: Type.cpp:180
MachineInstrBuilder buildFrameIndex(unsigned Res, int Idx)
Build and insert Res = G_FRAME_INDEX Idx.
static Constant * get(Type *Ty, uint64_t V, bool isSigned=false)
If Ty is a vector type, return a Constant with a splat of the given value.
Definition: Constants.cpp:621
unsigned getNumIncomingValues() const
Return the number of incoming edges.
MachineInstrBuilder buildSelect(unsigned Res, unsigned Tst, unsigned Op0, unsigned Op1)
Build and insert a Res = G_SELECT Tst, Op0, Op1.
bool isLayoutSuccessor(const MachineBasicBlock *MBB) const
Return true if the specified MBB will be emitted immediately after this block, such that if this bloc...
Intrinsic::ID getIntrinsicID() const LLVM_READONLY
getIntrinsicID - This method returns the ID number of the specified function, or Intrinsic::not_intri...
Definition: Function.h:194
const Function & getFunction() const
Return the LLVM function that this machine code represents.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:133
unsigned Log2_32(uint32_t Value)
Return the floor log base 2 of the specified value, -1 if the value is zero.
Definition: MathExtras.h:539
unsigned getVectorNumElements() const
Definition: DerivedTypes.h:462
bool isIntPredicate() const
Definition: InstrTypes.h:777
const Module * getModule() const
Return the module owning the function this instruction belongs to or nullptr it the function does not...
Definition: Instruction.cpp:56
static MachineOperand CreateES(const char *SymName, unsigned char TargetFlags=0)
static char ID
Definition: IRTranslator.h:61
virtual bool isFMAFasterThanFMulAndFAdd(EVT) const
Return true if an FMA operation is faster than a pair of fmul and fadd instructions.
MachineInstrBuilder buildConstant(unsigned Res, const ConstantInt &Val)
Build and insert Res = G_CONSTANT Val.
amdgpu Simplify well known AMD library false Value Value * Arg
MachineInstrBuilder buildAtomicRMW(unsigned Opcode, unsigned OldValRes, unsigned Addr, unsigned Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_<Opcode> Addr, Val, MMO.
virtual bool lowerReturn(MachineIRBuilder &MIRBuilder, const Value *Val, ArrayRef< unsigned > VRegs) const
This hook must be implemented to lower outgoing return values, described by Val, into the specified v...
Definition: CallLowering.h:145
The memory access reads data.
#define Success
uint64_t getTypeSizeInBits(Type *Ty) const
Size examples:
Definition: DataLayout.h:560
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
MachineInstrBuilder buildMerge(unsigned Res, ArrayRef< unsigned > Ops)
Build and insert Res = G_MERGE_VALUES Op0, ...
uint64_t getTypeAllocSize(Type *Ty) const
Returns the offset in bytes between successive objects of the specified type, including alignment pad...
Definition: DataLayout.h:428
Representation of each machine instruction.
Definition: MachineInstr.h:64
Predicate getPredicate() const
Return the predicate for this instruction.
Definition: InstrTypes.h:759
This file provides various utilities for inspecting and working with the control flow graph in LLVM I...
bool isVolatile() const
Return true if this is a store to a volatile memory location.
Definition: Instructions.h:343
const DebugLoc & getDebugLoc() const
Return the debug location for this node as a DebugLoc.
Definition: Instruction.h:307
bool isInlineAsm() const
Check if this call is an inline asm statement.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
uint64_t getElementOffset(unsigned Idx) const
Definition: DataLayout.h:543
void emplace_back(ArgTypes &&... Args)
Definition: SmallVector.h:652
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
static IntegerType * getInt32Ty(LLVMContext &C)
Definition: Type.cpp:176
LLVM_NODISCARD bool empty() const
Definition: SmallVector.h:56
AtomicOrdering getOrdering() const
Returns the ordering constraint of this store instruction.
Definition: Instructions.h:362
This represents the llvm.dbg.value instruction.
bool isTokenTy() const
Return true if this is &#39;token&#39;.
Definition: Type.h:194
Value * getPointerOperand()
Definition: Instructions.h:783
virtual const TargetIntrinsicInfo * getIntrinsicInfo() const
If intrinsic information is available, return it. If not, return null.
TargetOptions Options
Definition: TargetMachine.h:98
BasicBlock * getIncomingBlock(unsigned i) const
Return incoming basic block number i.
SyncScope::ID getSyncScopeID() const
Returns the synchronization scope ID of this load instruction.
Definition: Instructions.h:249
const MachineInstrBuilder & addExternalSymbol(const char *FnName, unsigned char TargetFlags=0) const
#define I(x, y, z)
Definition: MD5.cpp:58
MachineInstrBuilder buildLoad(unsigned Res, unsigned Addr, MachineMemOperand &MMO)
Build and insert Res = G_LOAD Addr, MMO.
static Constant * getZeroValueForNegation(Type *Ty)
Floating point negation must be implemented with f(x) = -0.0 - x.
Definition: Constants.cpp:748
Pair of physical register and lane mask.
virtual const TargetFrameLowering * getFrameLowering() const
The memory access always returns the same value (or traps).
bool isZero() const
This is just a convenience method to make client code smaller for a common code.
Definition: Constants.h:193
LLVM_NODISCARD std::enable_if<!is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
Definition: Casting.h:323
void setDebugLoc(const DebugLoc &DL)
Set the debug location to DL for all the next build instructions.
uint32_t Size
Definition: Profile.cpp:47
DILocalVariable * getVariable() const
Value * getReturnValue() const
Convenience accessor. Returns null if there is no return value.
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - This function should be overriden by passes that need analysis information to do t...
Optional< MachineInstrBuilder > materializeGEP(unsigned &Res, unsigned Op0, const LLT &ValueTy, uint64_t Value)
Materialize and insert Res = G_GEP Op0, (G_CONSTANT Value)
bool isUnconditional() const
MachineInstrBuilder buildCast(DstType &&Res, ArgType &&Arg)
Build and insert an appropriate cast between two registers of equal size.
static void computeValueLLTs(const DataLayout &DL, Type &Ty, SmallVectorImpl< LLT > &ValueTys, SmallVectorImpl< uint64_t > *Offsets=nullptr, uint64_t StartingOffset=0)
AsmDialect getDialect() const
Definition: InlineAsm.h:69
Multiway switch.
MachineInstrBuilder buildAtomicCmpXchgWithSuccess(unsigned OldValRes, unsigned SuccessRes, unsigned Addr, unsigned CmpVal, unsigned NewVal, MachineMemOperand &MMO)
Build and insert OldValRes<def>, SuccessRes<def> = G_ATOMIC_CMPXCHG_WITH_SUCCESS Addr, CmpVal, NewVal, MMO.
const Value * getCalledValue() const
Get a pointer to the function that is invoked by this instruction.
This file declares the IRTranslator pass.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
void insert(iterator MBBI, MachineBasicBlock *MBB)
Value * getArgOperand(unsigned i) const
getArgOperand/setArgOperand - Return/set the i-th call argument.
A raw_ostream that writes to an std::string.
Definition: raw_ostream.h:483
aarch64 promote const
Module * getParent()
Get the module that this global value is contained inside of...
Definition: GlobalValue.h:566
LLVM Value Representation.
Definition: Value.h:73
Constant * getPersonalityFn() const
Get the personality function associated with this function.
Definition: Function.cpp:1302
uint64_t getTypeStoreSize(Type *Ty) const
Returns the maximum number of bytes that may be overwritten by storing the specified type...
Definition: DataLayout.h:411
succ_range successors(Instruction *I)
Definition: CFG.h:262
This file describes how to lower LLVM calls to machine code calls.
void push_back(MachineBasicBlock *MBB)
unsigned getStackPointerRegisterToSaveRestore() const
If a physical register, this specifies the register that llvm.savestack/llvm.restorestack should save...
INITIALIZE_PASS_BEGIN(IRTranslator, DEBUG_TYPE, "IRTranslator LLVM IR -> MI", false, false) INITIALIZE_PASS_END(IRTranslator
MachineBasicBlock & getMBB()
Getter for the basic block we currently build.
const Value * getCalledValue() const
Get a pointer to the function that is invoked by this instruction.
Invoke instruction.
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:59
MachineInstrBuilder buildInstr(unsigned Opc, DstTy &&Ty, UseArgsTy &&... Args)
DAG like Generic method for building arbitrary instructions as above.
IRTranslator LLVM IR MI
MachineInstrBuilder buildFCmp(CmpInst::Predicate Pred, unsigned Res, unsigned Op0, unsigned Op1)
Build and insert a Res = G_FCMP PredOp0, Op1.
MachineInstrBuilder buildMul(unsigned Dst, unsigned Src0, unsigned Src1)
Build and insert Res = G_MUL Op0, Op1.
void setRegClass(unsigned Reg, const TargetRegisterClass *RC)
setRegClass - Set the register class of the specified virtual register.
const MachineInstrBuilder & addDef(unsigned RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register definition operand.
bool isStaticAlloca() const
Return true if this alloca is in the entry block of the function and is a constant size...
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned char TargetFlags=0) const
MachineInstrBuilder buildInsert(unsigned Res, unsigned Src, unsigned Op, unsigned Index)
#define LLVM_DEBUG(X)
Definition: Debug.h:123
MachineInstrBuilder buildBlockAddress(unsigned Res, const BlockAddress *BA)
Build and insert Res = G_BLOCK_ADDR BA.
OutputIt copy(R &&Range, OutputIt Out)
Definition: STLExtras.h:1094
void setVariableDbgInfo(const DILocalVariable *Var, const DIExpression *Expr, int Slot, const DILocation *Loc)
Collect information used to emit debugging information of a variable.
int CreateVariableSizedObject(unsigned Alignment, const AllocaInst *Alloca)
Notify the MachineFrameInfo object that a variable sized object has been created. ...
This represents the llvm.dbg.declare instruction.
Value * getPointerOperand()
Definition: Instructions.h:402
The optimization diagnostic interface.
Statically lint checks LLVM IR
Definition: Lint.cpp:193
constexpr char Args[]
Key for Kernel::Metadata::mArgs.
MachineInstrBuilder buildICmp(CmpInst::Predicate Pred, unsigned Res, unsigned Op0, unsigned Op1)
Build and insert a Res = G_ICMP Pred, Op0, Op1.
int64_t getIndexedOffsetInType(Type *ElemTy, ArrayRef< Value *> Indices) const
Returns the offset from the beginning of the type for the specified indices.
Definition: DataLayout.cpp:779
bool isVolatile() const
Return true if this is a RMW on a volatile memory location.
Definition: Instructions.h:746
0 0 0 0 Always false (always folded)
Definition: InstrTypes.h:687
IntegerType * Int32Ty
This file describes how to lower LLVM code to machine code.
const BasicBlock * getParent() const
Definition: Instruction.h:67
virtual const TargetRegisterClass * getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const
Returns a TargetRegisterClass used for pointer values.
an instruction to allocate memory on the stack
Definition: Instructions.h:60
This instruction inserts a struct field of array element value into an aggregate value.
gep_type_iterator gep_type_begin(const User *GEP)
size_type count(const T &V) const
count - Return 1 if the element is in the set, 0 otherwise.
Definition: SmallSet.h:165