LLVM  9.0.0svn
IRTranslator.cpp
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1 //===- llvm/CodeGen/GlobalISel/IRTranslator.cpp - IRTranslator ---*- C++ -*-==//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 /// \file
9 /// This file implements the IRTranslator class.
10 //===----------------------------------------------------------------------===//
11 
14 #include "llvm/ADT/STLExtras.h"
15 #include "llvm/ADT/ScopeExit.h"
16 #include "llvm/ADT/SmallSet.h"
17 #include "llvm/ADT/SmallVector.h"
19 #include "llvm/CodeGen/Analysis.h"
36 #include "llvm/IR/BasicBlock.h"
37 #include "llvm/IR/CFG.h"
38 #include "llvm/IR/Constant.h"
39 #include "llvm/IR/Constants.h"
40 #include "llvm/IR/DataLayout.h"
41 #include "llvm/IR/DebugInfo.h"
42 #include "llvm/IR/DerivedTypes.h"
43 #include "llvm/IR/Function.h"
45 #include "llvm/IR/InlineAsm.h"
46 #include "llvm/IR/InstrTypes.h"
47 #include "llvm/IR/Instructions.h"
48 #include "llvm/IR/IntrinsicInst.h"
49 #include "llvm/IR/Intrinsics.h"
50 #include "llvm/IR/LLVMContext.h"
51 #include "llvm/IR/Metadata.h"
52 #include "llvm/IR/Type.h"
53 #include "llvm/IR/User.h"
54 #include "llvm/IR/Value.h"
55 #include "llvm/MC/MCContext.h"
56 #include "llvm/Pass.h"
57 #include "llvm/Support/Casting.h"
58 #include "llvm/Support/CodeGen.h"
59 #include "llvm/Support/Debug.h"
66 #include <algorithm>
67 #include <cassert>
68 #include <cstdint>
69 #include <iterator>
70 #include <string>
71 #include <utility>
72 #include <vector>
73 
74 #define DEBUG_TYPE "irtranslator"
75 
76 using namespace llvm;
77 
78 static cl::opt<bool>
79  EnableCSEInIRTranslator("enable-cse-in-irtranslator",
80  cl::desc("Should enable CSE in irtranslator"),
81  cl::Optional, cl::init(false));
82 char IRTranslator::ID = 0;
83 
84 INITIALIZE_PASS_BEGIN(IRTranslator, DEBUG_TYPE, "IRTranslator LLVM IR -> MI",
85  false, false)
88 INITIALIZE_PASS_END(IRTranslator, DEBUG_TYPE, "IRTranslator LLVM IR -> MI",
89  false, false)
90 
96 
97  // Print the function name explicitly if we don't have a debug location (which
98  // makes the diagnostic less useful) or if we're going to emit a raw error.
99  if (!R.getLocation().isValid() || TPC.isGlobalISelAbortEnabled())
100  R << (" (in function: " + MF.getName() + ")").str();
101 
102  if (TPC.isGlobalISelAbortEnabled())
103  report_fatal_error(R.getMsg());
104  else
105  ORE.emit(R);
106 }
107 
110 }
111 
112 #ifndef NDEBUG
113 namespace {
114 /// Verify that every instruction created has the same DILocation as the
115 /// instruction being translated.
116 class DILocationVerifier : public GISelChangeObserver {
117  const Instruction *CurrInst = nullptr;
118 
119 public:
120  DILocationVerifier() = default;
121  ~DILocationVerifier() = default;
122 
123  const Instruction *getCurrentInst() const { return CurrInst; }
124  void setCurrentInst(const Instruction *Inst) { CurrInst = Inst; }
125 
126  void erasingInstr(MachineInstr &MI) override {}
127  void changingInstr(MachineInstr &MI) override {}
128  void changedInstr(MachineInstr &MI) override {}
129 
130  void createdInstr(MachineInstr &MI) override {
131  assert(getCurrentInst() && "Inserted instruction without a current MI");
132 
133  // Only print the check message if we're actually checking it.
134 #ifndef NDEBUG
135  LLVM_DEBUG(dbgs() << "Checking DILocation from " << *CurrInst
136  << " was copied to " << MI);
137 #endif
138  assert(CurrInst->getDebugLoc() == MI.getDebugLoc() &&
139  "Line info was not transferred to all instructions");
140  }
141 };
142 } // namespace
143 #endif // ifndef NDEBUG
144 
145 
152 }
153 
154 static void computeValueLLTs(const DataLayout &DL, Type &Ty,
155  SmallVectorImpl<LLT> &ValueTys,
157  uint64_t StartingOffset = 0) {
158  // Given a struct type, recursively traverse the elements.
159  if (StructType *STy = dyn_cast<StructType>(&Ty)) {
160  const StructLayout *SL = DL.getStructLayout(STy);
161  for (unsigned I = 0, E = STy->getNumElements(); I != E; ++I)
162  computeValueLLTs(DL, *STy->getElementType(I), ValueTys, Offsets,
163  StartingOffset + SL->getElementOffset(I));
164  return;
165  }
166  // Given an array type, recursively traverse the elements.
167  if (ArrayType *ATy = dyn_cast<ArrayType>(&Ty)) {
168  Type *EltTy = ATy->getElementType();
169  uint64_t EltSize = DL.getTypeAllocSize(EltTy);
170  for (unsigned i = 0, e = ATy->getNumElements(); i != e; ++i)
171  computeValueLLTs(DL, *EltTy, ValueTys, Offsets,
172  StartingOffset + i * EltSize);
173  return;
174  }
175  // Interpret void as zero return values.
176  if (Ty.isVoidTy())
177  return;
178  // Base case: we can get an LLT for this LLVM IR type.
179  ValueTys.push_back(getLLTForType(Ty, DL));
180  if (Offsets != nullptr)
181  Offsets->push_back(StartingOffset * 8);
182 }
183 
185 IRTranslator::allocateVRegs(const Value &Val) {
186  assert(!VMap.contains(Val) && "Value already allocated in VMap");
187  auto *Regs = VMap.getVRegs(Val);
188  auto *Offsets = VMap.getOffsets(Val);
189  SmallVector<LLT, 4> SplitTys;
190  computeValueLLTs(*DL, *Val.getType(), SplitTys,
191  Offsets->empty() ? Offsets : nullptr);
192  for (unsigned i = 0; i < SplitTys.size(); ++i)
193  Regs->push_back(0);
194  return *Regs;
195 }
196 
197 ArrayRef<unsigned> IRTranslator::getOrCreateVRegs(const Value &Val) {
198  auto VRegsIt = VMap.findVRegs(Val);
199  if (VRegsIt != VMap.vregs_end())
200  return *VRegsIt->second;
201 
202  if (Val.getType()->isVoidTy())
203  return *VMap.getVRegs(Val);
204 
205  // Create entry for this type.
206  auto *VRegs = VMap.getVRegs(Val);
207  auto *Offsets = VMap.getOffsets(Val);
208 
209  assert(Val.getType()->isSized() &&
210  "Don't know how to create an empty vreg");
211 
212  SmallVector<LLT, 4> SplitTys;
213  computeValueLLTs(*DL, *Val.getType(), SplitTys,
214  Offsets->empty() ? Offsets : nullptr);
215 
216  if (!isa<Constant>(Val)) {
217  for (auto Ty : SplitTys)
218  VRegs->push_back(MRI->createGenericVirtualRegister(Ty));
219  return *VRegs;
220  }
221 
222  if (Val.getType()->isAggregateType()) {
223  // UndefValue, ConstantAggregateZero
224  auto &C = cast<Constant>(Val);
225  unsigned Idx = 0;
226  while (auto Elt = C.getAggregateElement(Idx++)) {
227  auto EltRegs = getOrCreateVRegs(*Elt);
228  llvm::copy(EltRegs, std::back_inserter(*VRegs));
229  }
230  } else {
231  assert(SplitTys.size() == 1 && "unexpectedly split LLT");
232  VRegs->push_back(MRI->createGenericVirtualRegister(SplitTys[0]));
233  bool Success = translate(cast<Constant>(Val), VRegs->front());
234  if (!Success) {
235  OptimizationRemarkMissed R("gisel-irtranslator", "GISelFailure",
236  MF->getFunction().getSubprogram(),
237  &MF->getFunction().getEntryBlock());
238  R << "unable to translate constant: " << ore::NV("Type", Val.getType());
239  reportTranslationError(*MF, *TPC, *ORE, R);
240  return *VRegs;
241  }
242  }
243 
244  return *VRegs;
245 }
246 
247 int IRTranslator::getOrCreateFrameIndex(const AllocaInst &AI) {
248  if (FrameIndices.find(&AI) != FrameIndices.end())
249  return FrameIndices[&AI];
250 
251  unsigned ElementSize = DL->getTypeStoreSize(AI.getAllocatedType());
252  unsigned Size =
253  ElementSize * cast<ConstantInt>(AI.getArraySize())->getZExtValue();
254 
255  // Always allocate at least one byte.
256  Size = std::max(Size, 1u);
257 
258  unsigned Alignment = AI.getAlignment();
259  if (!Alignment)
260  Alignment = DL->getABITypeAlignment(AI.getAllocatedType());
261 
262  int &FI = FrameIndices[&AI];
263  FI = MF->getFrameInfo().CreateStackObject(Size, Alignment, false, &AI);
264  return FI;
265 }
266 
267 unsigned IRTranslator::getMemOpAlignment(const Instruction &I) {
268  unsigned Alignment = 0;
269  Type *ValTy = nullptr;
270  if (const StoreInst *SI = dyn_cast<StoreInst>(&I)) {
271  Alignment = SI->getAlignment();
272  ValTy = SI->getValueOperand()->getType();
273  } else if (const LoadInst *LI = dyn_cast<LoadInst>(&I)) {
274  Alignment = LI->getAlignment();
275  ValTy = LI->getType();
276  } else if (const AtomicCmpXchgInst *AI = dyn_cast<AtomicCmpXchgInst>(&I)) {
277  // TODO(PR27168): This instruction has no alignment attribute, but unlike
278  // the default alignment for load/store, the default here is to assume
279  // it has NATURAL alignment, not DataLayout-specified alignment.
280  const DataLayout &DL = AI->getModule()->getDataLayout();
281  Alignment = DL.getTypeStoreSize(AI->getCompareOperand()->getType());
282  ValTy = AI->getCompareOperand()->getType();
283  } else if (const AtomicRMWInst *AI = dyn_cast<AtomicRMWInst>(&I)) {
284  // TODO(PR27168): This instruction has no alignment attribute, but unlike
285  // the default alignment for load/store, the default here is to assume
286  // it has NATURAL alignment, not DataLayout-specified alignment.
287  const DataLayout &DL = AI->getModule()->getDataLayout();
288  Alignment = DL.getTypeStoreSize(AI->getValOperand()->getType());
289  ValTy = AI->getType();
290  } else {
291  OptimizationRemarkMissed R("gisel-irtranslator", "", &I);
292  R << "unable to translate memop: " << ore::NV("Opcode", &I);
293  reportTranslationError(*MF, *TPC, *ORE, R);
294  return 1;
295  }
296 
297  return Alignment ? Alignment : DL->getABITypeAlignment(ValTy);
298 }
299 
300 MachineBasicBlock &IRTranslator::getMBB(const BasicBlock &BB) {
301  MachineBasicBlock *&MBB = BBToMBB[&BB];
302  assert(MBB && "BasicBlock was not encountered before");
303  return *MBB;
304 }
305 
306 void IRTranslator::addMachineCFGPred(CFGEdge Edge, MachineBasicBlock *NewPred) {
307  assert(NewPred && "new predecessor must be a real MachineBasicBlock");
308  MachinePreds[Edge].push_back(NewPred);
309 }
310 
311 bool IRTranslator::translateBinaryOp(unsigned Opcode, const User &U,
312  MachineIRBuilder &MIRBuilder) {
313  // FIXME: handle signed/unsigned wrapping flags.
314 
315  // Get or create a virtual register for each value.
316  // Unless the value is a Constant => loadimm cst?
317  // or inline constant each time?
318  // Creation of a virtual register needs to have a size.
319  unsigned Op0 = getOrCreateVReg(*U.getOperand(0));
320  unsigned Op1 = getOrCreateVReg(*U.getOperand(1));
321  unsigned Res = getOrCreateVReg(U);
322  auto FBinOp = MIRBuilder.buildInstr(Opcode).addDef(Res).addUse(Op0).addUse(Op1);
323  if (isa<Instruction>(U)) {
324  MachineInstr *FBinOpMI = FBinOp.getInstr();
325  const Instruction &I = cast<Instruction>(U);
326  FBinOpMI->copyIRFlags(I);
327  }
328  return true;
329 }
330 
331 bool IRTranslator::translateFSub(const User &U, MachineIRBuilder &MIRBuilder) {
332  // -0.0 - X --> G_FNEG
333  if (isa<Constant>(U.getOperand(0)) &&
335  MIRBuilder.buildInstr(TargetOpcode::G_FNEG)
336  .addDef(getOrCreateVReg(U))
337  .addUse(getOrCreateVReg(*U.getOperand(1)));
338  return true;
339  }
340  return translateBinaryOp(TargetOpcode::G_FSUB, U, MIRBuilder);
341 }
342 
343 bool IRTranslator::translateFNeg(const User &U, MachineIRBuilder &MIRBuilder) {
344  MIRBuilder.buildInstr(TargetOpcode::G_FNEG)
345  .addDef(getOrCreateVReg(U))
346  .addUse(getOrCreateVReg(*U.getOperand(1)));
347  return true;
348 }
349 
350 bool IRTranslator::translateCompare(const User &U,
351  MachineIRBuilder &MIRBuilder) {
352  const CmpInst *CI = dyn_cast<CmpInst>(&U);
353  unsigned Op0 = getOrCreateVReg(*U.getOperand(0));
354  unsigned Op1 = getOrCreateVReg(*U.getOperand(1));
355  unsigned Res = getOrCreateVReg(U);
356  CmpInst::Predicate Pred =
357  CI ? CI->getPredicate() : static_cast<CmpInst::Predicate>(
358  cast<ConstantExpr>(U).getPredicate());
359  if (CmpInst::isIntPredicate(Pred))
360  MIRBuilder.buildICmp(Pred, Res, Op0, Op1);
361  else if (Pred == CmpInst::FCMP_FALSE)
362  MIRBuilder.buildCopy(
363  Res, getOrCreateVReg(*Constant::getNullValue(CI->getType())));
364  else if (Pred == CmpInst::FCMP_TRUE)
365  MIRBuilder.buildCopy(
366  Res, getOrCreateVReg(*Constant::getAllOnesValue(CI->getType())));
367  else {
368  auto FCmp = MIRBuilder.buildFCmp(Pred, Res, Op0, Op1);
369  FCmp->copyIRFlags(*CI);
370  }
371 
372  return true;
373 }
374 
375 bool IRTranslator::translateRet(const User &U, MachineIRBuilder &MIRBuilder) {
376  const ReturnInst &RI = cast<ReturnInst>(U);
377  const Value *Ret = RI.getReturnValue();
378  if (Ret && DL->getTypeStoreSize(Ret->getType()) == 0)
379  Ret = nullptr;
380 
381  ArrayRef<unsigned> VRegs;
382  if (Ret)
383  VRegs = getOrCreateVRegs(*Ret);
384 
385  // The target may mess up with the insertion point, but
386  // this is not important as a return is the last instruction
387  // of the block anyway.
388 
389  return CLI->lowerReturn(MIRBuilder, Ret, VRegs);
390 }
391 
392 bool IRTranslator::translateBr(const User &U, MachineIRBuilder &MIRBuilder) {
393  const BranchInst &BrInst = cast<BranchInst>(U);
394  unsigned Succ = 0;
395  if (!BrInst.isUnconditional()) {
396  // We want a G_BRCOND to the true BB followed by an unconditional branch.
397  unsigned Tst = getOrCreateVReg(*BrInst.getCondition());
398  const BasicBlock &TrueTgt = *cast<BasicBlock>(BrInst.getSuccessor(Succ++));
399  MachineBasicBlock &TrueBB = getMBB(TrueTgt);
400  MIRBuilder.buildBrCond(Tst, TrueBB);
401  }
402 
403  const BasicBlock &BrTgt = *cast<BasicBlock>(BrInst.getSuccessor(Succ));
404  MachineBasicBlock &TgtBB = getMBB(BrTgt);
405  MachineBasicBlock &CurBB = MIRBuilder.getMBB();
406 
407  // If the unconditional target is the layout successor, fallthrough.
408  if (!CurBB.isLayoutSuccessor(&TgtBB))
409  MIRBuilder.buildBr(TgtBB);
410 
411  // Link successors.
412  for (const BasicBlock *Succ : successors(&BrInst))
413  CurBB.addSuccessor(&getMBB(*Succ));
414  return true;
415 }
416 
417 bool IRTranslator::translateSwitch(const User &U,
418  MachineIRBuilder &MIRBuilder) {
419  // For now, just translate as a chain of conditional branches.
420  // FIXME: could we share most of the logic/code in
421  // SelectionDAGBuilder::visitSwitch between SelectionDAG and GlobalISel?
422  // At first sight, it seems most of the logic in there is independent of
423  // SelectionDAG-specifics and a lot of work went in to optimize switch
424  // lowering in there.
425 
426  const SwitchInst &SwInst = cast<SwitchInst>(U);
427  const unsigned SwCondValue = getOrCreateVReg(*SwInst.getCondition());
428  const BasicBlock *OrigBB = SwInst.getParent();
429 
430  LLT LLTi1 = getLLTForType(*Type::getInt1Ty(U.getContext()), *DL);
431  for (auto &CaseIt : SwInst.cases()) {
432  const unsigned CaseValueReg = getOrCreateVReg(*CaseIt.getCaseValue());
433  const unsigned Tst = MRI->createGenericVirtualRegister(LLTi1);
434  MIRBuilder.buildICmp(CmpInst::ICMP_EQ, Tst, CaseValueReg, SwCondValue);
435  MachineBasicBlock &CurMBB = MIRBuilder.getMBB();
436  const BasicBlock *TrueBB = CaseIt.getCaseSuccessor();
437  MachineBasicBlock &TrueMBB = getMBB(*TrueBB);
438 
439  MIRBuilder.buildBrCond(Tst, TrueMBB);
440  CurMBB.addSuccessor(&TrueMBB);
441  addMachineCFGPred({OrigBB, TrueBB}, &CurMBB);
442 
443  MachineBasicBlock *FalseMBB =
444  MF->CreateMachineBasicBlock(SwInst.getParent());
445  // Insert the comparison blocks one after the other.
446  MF->insert(std::next(CurMBB.getIterator()), FalseMBB);
447  MIRBuilder.buildBr(*FalseMBB);
448  CurMBB.addSuccessor(FalseMBB);
449 
450  MIRBuilder.setMBB(*FalseMBB);
451  }
452  // handle default case
453  const BasicBlock *DefaultBB = SwInst.getDefaultDest();
454  MachineBasicBlock &DefaultMBB = getMBB(*DefaultBB);
455  MIRBuilder.buildBr(DefaultMBB);
456  MachineBasicBlock &CurMBB = MIRBuilder.getMBB();
457  CurMBB.addSuccessor(&DefaultMBB);
458  addMachineCFGPred({OrigBB, DefaultBB}, &CurMBB);
459 
460  return true;
461 }
462 
463 bool IRTranslator::translateIndirectBr(const User &U,
464  MachineIRBuilder &MIRBuilder) {
465  const IndirectBrInst &BrInst = cast<IndirectBrInst>(U);
466 
467  const unsigned Tgt = getOrCreateVReg(*BrInst.getAddress());
468  MIRBuilder.buildBrIndirect(Tgt);
469 
470  // Link successors.
471  MachineBasicBlock &CurBB = MIRBuilder.getMBB();
472  for (const BasicBlock *Succ : successors(&BrInst))
473  CurBB.addSuccessor(&getMBB(*Succ));
474 
475  return true;
476 }
477 
478 bool IRTranslator::translateLoad(const User &U, MachineIRBuilder &MIRBuilder) {
479  const LoadInst &LI = cast<LoadInst>(U);
480 
481  auto Flags = LI.isVolatile() ? MachineMemOperand::MOVolatile
483  Flags |= MachineMemOperand::MOLoad;
484 
485  if (DL->getTypeStoreSize(LI.getType()) == 0)
486  return true;
487 
488  ArrayRef<unsigned> Regs = getOrCreateVRegs(LI);
489  ArrayRef<uint64_t> Offsets = *VMap.getOffsets(LI);
490  unsigned Base = getOrCreateVReg(*LI.getPointerOperand());
491 
492  for (unsigned i = 0; i < Regs.size(); ++i) {
493  unsigned Addr = 0;
494  MIRBuilder.materializeGEP(Addr, Base, LLT::scalar(64), Offsets[i] / 8);
495 
496  MachinePointerInfo Ptr(LI.getPointerOperand(), Offsets[i] / 8);
497  unsigned BaseAlign = getMemOpAlignment(LI);
498  auto MMO = MF->getMachineMemOperand(
499  Ptr, Flags, (MRI->getType(Regs[i]).getSizeInBits() + 7) / 8,
500  MinAlign(BaseAlign, Offsets[i] / 8), AAMDNodes(), nullptr,
501  LI.getSyncScopeID(), LI.getOrdering());
502  MIRBuilder.buildLoad(Regs[i], Addr, *MMO);
503  }
504 
505  return true;
506 }
507 
508 bool IRTranslator::translateStore(const User &U, MachineIRBuilder &MIRBuilder) {
509  const StoreInst &SI = cast<StoreInst>(U);
510  auto Flags = SI.isVolatile() ? MachineMemOperand::MOVolatile
513 
514  if (DL->getTypeStoreSize(SI.getValueOperand()->getType()) == 0)
515  return true;
516 
517  ArrayRef<unsigned> Vals = getOrCreateVRegs(*SI.getValueOperand());
518  ArrayRef<uint64_t> Offsets = *VMap.getOffsets(*SI.getValueOperand());
519  unsigned Base = getOrCreateVReg(*SI.getPointerOperand());
520 
521  for (unsigned i = 0; i < Vals.size(); ++i) {
522  unsigned Addr = 0;
523  MIRBuilder.materializeGEP(Addr, Base, LLT::scalar(64), Offsets[i] / 8);
524 
525  MachinePointerInfo Ptr(SI.getPointerOperand(), Offsets[i] / 8);
526  unsigned BaseAlign = getMemOpAlignment(SI);
527  auto MMO = MF->getMachineMemOperand(
528  Ptr, Flags, (MRI->getType(Vals[i]).getSizeInBits() + 7) / 8,
529  MinAlign(BaseAlign, Offsets[i] / 8), AAMDNodes(), nullptr,
530  SI.getSyncScopeID(), SI.getOrdering());
531  MIRBuilder.buildStore(Vals[i], Addr, *MMO);
532  }
533  return true;
534 }
535 
536 static uint64_t getOffsetFromIndices(const User &U, const DataLayout &DL) {
537  const Value *Src = U.getOperand(0);
539 
540  // getIndexedOffsetInType is designed for GEPs, so the first index is the
541  // usual array element rather than looking into the actual aggregate.
542  SmallVector<Value *, 1> Indices;
543  Indices.push_back(ConstantInt::get(Int32Ty, 0));
544 
545  if (const ExtractValueInst *EVI = dyn_cast<ExtractValueInst>(&U)) {
546  for (auto Idx : EVI->indices())
547  Indices.push_back(ConstantInt::get(Int32Ty, Idx));
548  } else if (const InsertValueInst *IVI = dyn_cast<InsertValueInst>(&U)) {
549  for (auto Idx : IVI->indices())
550  Indices.push_back(ConstantInt::get(Int32Ty, Idx));
551  } else {
552  for (unsigned i = 1; i < U.getNumOperands(); ++i)
553  Indices.push_back(U.getOperand(i));
554  }
555 
556  return 8 * static_cast<uint64_t>(
557  DL.getIndexedOffsetInType(Src->getType(), Indices));
558 }
559 
560 bool IRTranslator::translateExtractValue(const User &U,
561  MachineIRBuilder &MIRBuilder) {
562  const Value *Src = U.getOperand(0);
563  uint64_t Offset = getOffsetFromIndices(U, *DL);
564  ArrayRef<unsigned> SrcRegs = getOrCreateVRegs(*Src);
565  ArrayRef<uint64_t> Offsets = *VMap.getOffsets(*Src);
566  unsigned Idx = std::lower_bound(Offsets.begin(), Offsets.end(), Offset) -
567  Offsets.begin();
568  auto &DstRegs = allocateVRegs(U);
569 
570  for (unsigned i = 0; i < DstRegs.size(); ++i)
571  DstRegs[i] = SrcRegs[Idx++];
572 
573  return true;
574 }
575 
576 bool IRTranslator::translateInsertValue(const User &U,
577  MachineIRBuilder &MIRBuilder) {
578  const Value *Src = U.getOperand(0);
579  uint64_t Offset = getOffsetFromIndices(U, *DL);
580  auto &DstRegs = allocateVRegs(U);
581  ArrayRef<uint64_t> DstOffsets = *VMap.getOffsets(U);
582  ArrayRef<unsigned> SrcRegs = getOrCreateVRegs(*Src);
583  ArrayRef<unsigned> InsertedRegs = getOrCreateVRegs(*U.getOperand(1));
584  auto InsertedIt = InsertedRegs.begin();
585 
586  for (unsigned i = 0; i < DstRegs.size(); ++i) {
587  if (DstOffsets[i] >= Offset && InsertedIt != InsertedRegs.end())
588  DstRegs[i] = *InsertedIt++;
589  else
590  DstRegs[i] = SrcRegs[i];
591  }
592 
593  return true;
594 }
595 
596 bool IRTranslator::translateSelect(const User &U,
597  MachineIRBuilder &MIRBuilder) {
598  unsigned Tst = getOrCreateVReg(*U.getOperand(0));
599  ArrayRef<unsigned> ResRegs = getOrCreateVRegs(U);
600  ArrayRef<unsigned> Op0Regs = getOrCreateVRegs(*U.getOperand(1));
601  ArrayRef<unsigned> Op1Regs = getOrCreateVRegs(*U.getOperand(2));
602 
603  const SelectInst &SI = cast<SelectInst>(U);
604  const CmpInst *Cmp = dyn_cast<CmpInst>(SI.getCondition());
605  for (unsigned i = 0; i < ResRegs.size(); ++i) {
606  auto Select =
607  MIRBuilder.buildSelect(ResRegs[i], Tst, Op0Regs[i], Op1Regs[i]);
608  if (Cmp && isa<FPMathOperator>(Cmp)) {
609  Select->copyIRFlags(*Cmp);
610  }
611  }
612 
613  return true;
614 }
615 
616 bool IRTranslator::translateBitCast(const User &U,
617  MachineIRBuilder &MIRBuilder) {
618  // If we're bitcasting to the source type, we can reuse the source vreg.
619  if (getLLTForType(*U.getOperand(0)->getType(), *DL) ==
620  getLLTForType(*U.getType(), *DL)) {
621  unsigned SrcReg = getOrCreateVReg(*U.getOperand(0));
622  auto &Regs = *VMap.getVRegs(U);
623  // If we already assigned a vreg for this bitcast, we can't change that.
624  // Emit a copy to satisfy the users we already emitted.
625  if (!Regs.empty())
626  MIRBuilder.buildCopy(Regs[0], SrcReg);
627  else {
628  Regs.push_back(SrcReg);
629  VMap.getOffsets(U)->push_back(0);
630  }
631  return true;
632  }
633  return translateCast(TargetOpcode::G_BITCAST, U, MIRBuilder);
634 }
635 
636 bool IRTranslator::translateCast(unsigned Opcode, const User &U,
637  MachineIRBuilder &MIRBuilder) {
638  unsigned Op = getOrCreateVReg(*U.getOperand(0));
639  unsigned Res = getOrCreateVReg(U);
640  MIRBuilder.buildInstr(Opcode).addDef(Res).addUse(Op);
641  return true;
642 }
643 
644 bool IRTranslator::translateGetElementPtr(const User &U,
645  MachineIRBuilder &MIRBuilder) {
646  // FIXME: support vector GEPs.
647  if (U.getType()->isVectorTy())
648  return false;
649 
650  Value &Op0 = *U.getOperand(0);
651  unsigned BaseReg = getOrCreateVReg(Op0);
652  Type *PtrIRTy = Op0.getType();
653  LLT PtrTy = getLLTForType(*PtrIRTy, *DL);
654  Type *OffsetIRTy = DL->getIntPtrType(PtrIRTy);
655  LLT OffsetTy = getLLTForType(*OffsetIRTy, *DL);
656 
657  int64_t Offset = 0;
658  for (gep_type_iterator GTI = gep_type_begin(&U), E = gep_type_end(&U);
659  GTI != E; ++GTI) {
660  const Value *Idx = GTI.getOperand();
661  if (StructType *StTy = GTI.getStructTypeOrNull()) {
662  unsigned Field = cast<Constant>(Idx)->getUniqueInteger().getZExtValue();
663  Offset += DL->getStructLayout(StTy)->getElementOffset(Field);
664  continue;
665  } else {
666  uint64_t ElementSize = DL->getTypeAllocSize(GTI.getIndexedType());
667 
668  // If this is a scalar constant or a splat vector of constants,
669  // handle it quickly.
670  if (const auto *CI = dyn_cast<ConstantInt>(Idx)) {
671  Offset += ElementSize * CI->getSExtValue();
672  continue;
673  }
674 
675  if (Offset != 0) {
676  unsigned NewBaseReg = MRI->createGenericVirtualRegister(PtrTy);
677  unsigned OffsetReg =
678  getOrCreateVReg(*ConstantInt::get(OffsetIRTy, Offset));
679  MIRBuilder.buildGEP(NewBaseReg, BaseReg, OffsetReg);
680 
681  BaseReg = NewBaseReg;
682  Offset = 0;
683  }
684 
685  unsigned IdxReg = getOrCreateVReg(*Idx);
686  if (MRI->getType(IdxReg) != OffsetTy) {
687  unsigned NewIdxReg = MRI->createGenericVirtualRegister(OffsetTy);
688  MIRBuilder.buildSExtOrTrunc(NewIdxReg, IdxReg);
689  IdxReg = NewIdxReg;
690  }
691 
692  // N = N + Idx * ElementSize;
693  // Avoid doing it for ElementSize of 1.
694  unsigned GepOffsetReg;
695  if (ElementSize != 1) {
696  unsigned ElementSizeReg =
697  getOrCreateVReg(*ConstantInt::get(OffsetIRTy, ElementSize));
698 
699  GepOffsetReg = MRI->createGenericVirtualRegister(OffsetTy);
700  MIRBuilder.buildMul(GepOffsetReg, ElementSizeReg, IdxReg);
701  } else
702  GepOffsetReg = IdxReg;
703 
704  unsigned NewBaseReg = MRI->createGenericVirtualRegister(PtrTy);
705  MIRBuilder.buildGEP(NewBaseReg, BaseReg, GepOffsetReg);
706  BaseReg = NewBaseReg;
707  }
708  }
709 
710  if (Offset != 0) {
711  unsigned OffsetReg = getOrCreateVReg(*ConstantInt::get(OffsetIRTy, Offset));
712  MIRBuilder.buildGEP(getOrCreateVReg(U), BaseReg, OffsetReg);
713  return true;
714  }
715 
716  MIRBuilder.buildCopy(getOrCreateVReg(U), BaseReg);
717  return true;
718 }
719 
720 bool IRTranslator::translateMemfunc(const CallInst &CI,
721  MachineIRBuilder &MIRBuilder,
722  unsigned ID) {
723  LLT SizeTy = getLLTForType(*CI.getArgOperand(2)->getType(), *DL);
724  Type *DstTy = CI.getArgOperand(0)->getType();
725  if (cast<PointerType>(DstTy)->getAddressSpace() != 0 ||
726  SizeTy.getSizeInBits() != DL->getPointerSizeInBits(0))
727  return false;
728 
730  for (int i = 0; i < 3; ++i) {
731  const auto &Arg = CI.getArgOperand(i);
732  Args.emplace_back(getOrCreateVReg(*Arg), Arg->getType());
733  }
734 
735  const char *Callee;
736  switch (ID) {
737  case Intrinsic::memmove:
738  case Intrinsic::memcpy: {
739  Type *SrcTy = CI.getArgOperand(1)->getType();
740  if(cast<PointerType>(SrcTy)->getAddressSpace() != 0)
741  return false;
742  Callee = ID == Intrinsic::memcpy ? "memcpy" : "memmove";
743  break;
744  }
745  case Intrinsic::memset:
746  Callee = "memset";
747  break;
748  default:
749  return false;
750  }
751 
752  return CLI->lowerCall(MIRBuilder, CI.getCallingConv(),
753  MachineOperand::CreateES(Callee),
754  CallLowering::ArgInfo(0, CI.getType()), Args);
755 }
756 
757 void IRTranslator::getStackGuard(unsigned DstReg,
758  MachineIRBuilder &MIRBuilder) {
759  const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
760  MRI->setRegClass(DstReg, TRI->getPointerRegClass(*MF));
761  auto MIB = MIRBuilder.buildInstr(TargetOpcode::LOAD_STACK_GUARD);
762  MIB.addDef(DstReg);
763 
764  auto &TLI = *MF->getSubtarget().getTargetLowering();
765  Value *Global = TLI.getSDagStackGuard(*MF->getFunction().getParent());
766  if (!Global)
767  return;
768 
769  MachinePointerInfo MPInfo(Global);
773  MF->getMachineMemOperand(MPInfo, Flags, DL->getPointerSizeInBits() / 8,
774  DL->getPointerABIAlignment(0));
775  MIB.setMemRefs({MemRef});
776 }
777 
778 bool IRTranslator::translateOverflowIntrinsic(const CallInst &CI, unsigned Op,
779  MachineIRBuilder &MIRBuilder) {
780  ArrayRef<unsigned> ResRegs = getOrCreateVRegs(CI);
781  MIRBuilder.buildInstr(Op)
782  .addDef(ResRegs[0])
783  .addDef(ResRegs[1])
784  .addUse(getOrCreateVReg(*CI.getOperand(0)))
785  .addUse(getOrCreateVReg(*CI.getOperand(1)));
786 
787  return true;
788 }
789 
790 bool IRTranslator::translateKnownIntrinsic(const CallInst &CI, Intrinsic::ID ID,
791  MachineIRBuilder &MIRBuilder) {
792  switch (ID) {
793  default:
794  break;
795  case Intrinsic::lifetime_start:
796  case Intrinsic::lifetime_end:
797  // Stack coloring is not enabled in O0 (which we care about now) so we can
798  // drop these. Make sure someone notices when we start compiling at higher
799  // opts though.
800  if (MF->getTarget().getOptLevel() != CodeGenOpt::None)
801  return false;
802  return true;
803  case Intrinsic::dbg_declare: {
804  const DbgDeclareInst &DI = cast<DbgDeclareInst>(CI);
805  assert(DI.getVariable() && "Missing variable");
806 
807  const Value *Address = DI.getAddress();
808  if (!Address || isa<UndefValue>(Address)) {
809  LLVM_DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
810  return true;
811  }
812 
814  MIRBuilder.getDebugLoc()) &&
815  "Expected inlined-at fields to agree");
816  auto AI = dyn_cast<AllocaInst>(Address);
817  if (AI && AI->isStaticAlloca()) {
818  // Static allocas are tracked at the MF level, no need for DBG_VALUE
819  // instructions (in fact, they get ignored if they *do* exist).
820  MF->setVariableDbgInfo(DI.getVariable(), DI.getExpression(),
821  getOrCreateFrameIndex(*AI), DI.getDebugLoc());
822  } else {
823  // A dbg.declare describes the address of a source variable, so lower it
824  // into an indirect DBG_VALUE.
825  MIRBuilder.buildIndirectDbgValue(getOrCreateVReg(*Address),
826  DI.getVariable(), DI.getExpression());
827  }
828  return true;
829  }
830  case Intrinsic::dbg_label: {
831  const DbgLabelInst &DI = cast<DbgLabelInst>(CI);
832  assert(DI.getLabel() && "Missing label");
833 
835  MIRBuilder.getDebugLoc()) &&
836  "Expected inlined-at fields to agree");
837 
838  MIRBuilder.buildDbgLabel(DI.getLabel());
839  return true;
840  }
841  case Intrinsic::vaend:
842  // No target I know of cares about va_end. Certainly no in-tree target
843  // does. Simplest intrinsic ever!
844  return true;
845  case Intrinsic::vastart: {
846  auto &TLI = *MF->getSubtarget().getTargetLowering();
847  Value *Ptr = CI.getArgOperand(0);
848  unsigned ListSize = TLI.getVaListSizeInBits(*DL) / 8;
849 
850  MIRBuilder.buildInstr(TargetOpcode::G_VASTART)
851  .addUse(getOrCreateVReg(*Ptr))
852  .addMemOperand(MF->getMachineMemOperand(
853  MachinePointerInfo(Ptr), MachineMemOperand::MOStore, ListSize, 0));
854  return true;
855  }
856  case Intrinsic::dbg_value: {
857  // This form of DBG_VALUE is target-independent.
858  const DbgValueInst &DI = cast<DbgValueInst>(CI);
859  const Value *V = DI.getValue();
861  MIRBuilder.getDebugLoc()) &&
862  "Expected inlined-at fields to agree");
863  if (!V) {
864  // Currently the optimizer can produce this; insert an undef to
865  // help debugging. Probably the optimizer should not do this.
866  MIRBuilder.buildIndirectDbgValue(0, DI.getVariable(), DI.getExpression());
867  } else if (const auto *CI = dyn_cast<Constant>(V)) {
868  MIRBuilder.buildConstDbgValue(*CI, DI.getVariable(), DI.getExpression());
869  } else {
870  unsigned Reg = getOrCreateVReg(*V);
871  // FIXME: This does not handle register-indirect values at offset 0. The
872  // direct/indirect thing shouldn't really be handled by something as
873  // implicit as reg+noreg vs reg+imm in the first palce, but it seems
874  // pretty baked in right now.
875  MIRBuilder.buildDirectDbgValue(Reg, DI.getVariable(), DI.getExpression());
876  }
877  return true;
878  }
879  case Intrinsic::uadd_with_overflow:
880  return translateOverflowIntrinsic(CI, TargetOpcode::G_UADDO, MIRBuilder);
881  case Intrinsic::sadd_with_overflow:
882  return translateOverflowIntrinsic(CI, TargetOpcode::G_SADDO, MIRBuilder);
883  case Intrinsic::usub_with_overflow:
884  return translateOverflowIntrinsic(CI, TargetOpcode::G_USUBO, MIRBuilder);
885  case Intrinsic::ssub_with_overflow:
886  return translateOverflowIntrinsic(CI, TargetOpcode::G_SSUBO, MIRBuilder);
887  case Intrinsic::umul_with_overflow:
888  return translateOverflowIntrinsic(CI, TargetOpcode::G_UMULO, MIRBuilder);
889  case Intrinsic::smul_with_overflow:
890  return translateOverflowIntrinsic(CI, TargetOpcode::G_SMULO, MIRBuilder);
891  case Intrinsic::pow: {
892  auto Pow = MIRBuilder.buildInstr(TargetOpcode::G_FPOW)
893  .addDef(getOrCreateVReg(CI))
894  .addUse(getOrCreateVReg(*CI.getArgOperand(0)))
895  .addUse(getOrCreateVReg(*CI.getArgOperand(1)));
896  Pow->copyIRFlags(CI);
897  return true;
898  }
899  case Intrinsic::exp: {
900  auto Exp = MIRBuilder.buildInstr(TargetOpcode::G_FEXP)
901  .addDef(getOrCreateVReg(CI))
902  .addUse(getOrCreateVReg(*CI.getArgOperand(0)));
903  Exp->copyIRFlags(CI);
904  return true;
905  }
906  case Intrinsic::exp2: {
907  auto Exp2 = MIRBuilder.buildInstr(TargetOpcode::G_FEXP2)
908  .addDef(getOrCreateVReg(CI))
909  .addUse(getOrCreateVReg(*CI.getArgOperand(0)));
910  Exp2->copyIRFlags(CI);
911  return true;
912  }
913  case Intrinsic::log: {
914  auto Log = MIRBuilder.buildInstr(TargetOpcode::G_FLOG)
915  .addDef(getOrCreateVReg(CI))
916  .addUse(getOrCreateVReg(*CI.getArgOperand(0)));
917  Log->copyIRFlags(CI);
918  return true;
919  }
920  case Intrinsic::log2: {
921  auto Log2 = MIRBuilder.buildInstr(TargetOpcode::G_FLOG2)
922  .addDef(getOrCreateVReg(CI))
923  .addUse(getOrCreateVReg(*CI.getArgOperand(0)));
924  Log2->copyIRFlags(CI);
925  return true;
926  }
927  case Intrinsic::log10: {
928  auto Log10 = MIRBuilder.buildInstr(TargetOpcode::G_FLOG10)
929  .addDef(getOrCreateVReg(CI))
930  .addUse(getOrCreateVReg(*CI.getArgOperand(0)));
931  Log10->copyIRFlags(CI);
932  return true;
933  }
934  case Intrinsic::fabs: {
935  auto Fabs = MIRBuilder.buildInstr(TargetOpcode::G_FABS)
936  .addDef(getOrCreateVReg(CI))
937  .addUse(getOrCreateVReg(*CI.getArgOperand(0)));
938  Fabs->copyIRFlags(CI);
939  return true;
940  }
941  case Intrinsic::trunc:
942  MIRBuilder.buildInstr(TargetOpcode::G_INTRINSIC_TRUNC)
943  .addDef(getOrCreateVReg(CI))
944  .addUse(getOrCreateVReg(*CI.getArgOperand(0)));
945  return true;
946  case Intrinsic::round:
947  MIRBuilder.buildInstr(TargetOpcode::G_INTRINSIC_ROUND)
948  .addDef(getOrCreateVReg(CI))
949  .addUse(getOrCreateVReg(*CI.getArgOperand(0)));
950  return true;
951  case Intrinsic::fma: {
952  auto FMA = MIRBuilder.buildInstr(TargetOpcode::G_FMA)
953  .addDef(getOrCreateVReg(CI))
954  .addUse(getOrCreateVReg(*CI.getArgOperand(0)))
955  .addUse(getOrCreateVReg(*CI.getArgOperand(1)))
956  .addUse(getOrCreateVReg(*CI.getArgOperand(2)));
957  FMA->copyIRFlags(CI);
958  return true;
959  }
960  case Intrinsic::fmuladd: {
961  const TargetMachine &TM = MF->getTarget();
962  const TargetLowering &TLI = *MF->getSubtarget().getTargetLowering();
963  unsigned Dst = getOrCreateVReg(CI);
964  unsigned Op0 = getOrCreateVReg(*CI.getArgOperand(0));
965  unsigned Op1 = getOrCreateVReg(*CI.getArgOperand(1));
966  unsigned Op2 = getOrCreateVReg(*CI.getArgOperand(2));
968  TLI.isFMAFasterThanFMulAndFAdd(TLI.getValueType(*DL, CI.getType()))) {
969  // TODO: Revisit this to see if we should move this part of the
970  // lowering to the combiner.
971  auto FMA = MIRBuilder.buildInstr(TargetOpcode::G_FMA, {Dst}, {Op0, Op1, Op2});
972  FMA->copyIRFlags(CI);
973  } else {
974  LLT Ty = getLLTForType(*CI.getType(), *DL);
975  auto FMul = MIRBuilder.buildInstr(TargetOpcode::G_FMUL, {Ty}, {Op0, Op1});
976  FMul->copyIRFlags(CI);
977  auto FAdd = MIRBuilder.buildInstr(TargetOpcode::G_FADD, {Dst}, {FMul, Op2});
978  FAdd->copyIRFlags(CI);
979  }
980  return true;
981  }
982  case Intrinsic::memcpy:
983  case Intrinsic::memmove:
984  case Intrinsic::memset:
985  return translateMemfunc(CI, MIRBuilder, ID);
986  case Intrinsic::eh_typeid_for: {
988  unsigned Reg = getOrCreateVReg(CI);
989  unsigned TypeID = MF->getTypeIDFor(GV);
990  MIRBuilder.buildConstant(Reg, TypeID);
991  return true;
992  }
993  case Intrinsic::objectsize: {
994  // If we don't know by now, we're never going to know.
995  const ConstantInt *Min = cast<ConstantInt>(CI.getArgOperand(1));
996 
997  MIRBuilder.buildConstant(getOrCreateVReg(CI), Min->isZero() ? -1ULL : 0);
998  return true;
999  }
1000  case Intrinsic::is_constant:
1001  // If this wasn't constant-folded away by now, then it's not a
1002  // constant.
1003  MIRBuilder.buildConstant(getOrCreateVReg(CI), 0);
1004  return true;
1005  case Intrinsic::stackguard:
1006  getStackGuard(getOrCreateVReg(CI), MIRBuilder);
1007  return true;
1008  case Intrinsic::stackprotector: {
1009  LLT PtrTy = getLLTForType(*CI.getArgOperand(0)->getType(), *DL);
1010  unsigned GuardVal = MRI->createGenericVirtualRegister(PtrTy);
1011  getStackGuard(GuardVal, MIRBuilder);
1012 
1013  AllocaInst *Slot = cast<AllocaInst>(CI.getArgOperand(1));
1014  int FI = getOrCreateFrameIndex(*Slot);
1015  MF->getFrameInfo().setStackProtectorIndex(FI);
1016 
1017  MIRBuilder.buildStore(
1018  GuardVal, getOrCreateVReg(*Slot),
1019  *MF->getMachineMemOperand(MachinePointerInfo::getFixedStack(*MF, FI),
1022  PtrTy.getSizeInBits() / 8, 8));
1023  return true;
1024  }
1025  case Intrinsic::cttz:
1026  case Intrinsic::ctlz: {
1027  ConstantInt *Cst = cast<ConstantInt>(CI.getArgOperand(1));
1028  bool isTrailing = ID == Intrinsic::cttz;
1029  unsigned Opcode = isTrailing
1030  ? Cst->isZero() ? TargetOpcode::G_CTTZ
1031  : TargetOpcode::G_CTTZ_ZERO_UNDEF
1032  : Cst->isZero() ? TargetOpcode::G_CTLZ
1033  : TargetOpcode::G_CTLZ_ZERO_UNDEF;
1034  MIRBuilder.buildInstr(Opcode)
1035  .addDef(getOrCreateVReg(CI))
1036  .addUse(getOrCreateVReg(*CI.getArgOperand(0)));
1037  return true;
1038  }
1039  case Intrinsic::ctpop: {
1040  MIRBuilder.buildInstr(TargetOpcode::G_CTPOP)
1041  .addDef(getOrCreateVReg(CI))
1042  .addUse(getOrCreateVReg(*CI.getArgOperand(0)));
1043  return true;
1044  }
1045  case Intrinsic::invariant_start: {
1046  LLT PtrTy = getLLTForType(*CI.getArgOperand(0)->getType(), *DL);
1047  unsigned Undef = MRI->createGenericVirtualRegister(PtrTy);
1048  MIRBuilder.buildUndef(Undef);
1049  return true;
1050  }
1051  case Intrinsic::invariant_end:
1052  return true;
1053  case Intrinsic::ceil:
1054  MIRBuilder.buildInstr(TargetOpcode::G_FCEIL)
1055  .addDef(getOrCreateVReg(CI))
1056  .addUse(getOrCreateVReg(*CI.getArgOperand(0)));
1057  return true;
1058  }
1059  return false;
1060 }
1061 
1062 bool IRTranslator::translateInlineAsm(const CallInst &CI,
1063  MachineIRBuilder &MIRBuilder) {
1064  const InlineAsm &IA = cast<InlineAsm>(*CI.getCalledValue());
1065  if (!IA.getConstraintString().empty())
1066  return false;
1067 
1068  unsigned ExtraInfo = 0;
1069  if (IA.hasSideEffects())
1070  ExtraInfo |= InlineAsm::Extra_HasSideEffects;
1071  if (IA.getDialect() == InlineAsm::AD_Intel)
1072  ExtraInfo |= InlineAsm::Extra_AsmDialect;
1073 
1075  .addExternalSymbol(IA.getAsmString().c_str())
1076  .addImm(ExtraInfo);
1077 
1078  return true;
1079 }
1080 
1081 unsigned IRTranslator::packRegs(const Value &V,
1082  MachineIRBuilder &MIRBuilder) {
1083  ArrayRef<unsigned> Regs = getOrCreateVRegs(V);
1084  ArrayRef<uint64_t> Offsets = *VMap.getOffsets(V);
1085  LLT BigTy = getLLTForType(*V.getType(), *DL);
1086 
1087  if (Regs.size() == 1)
1088  return Regs[0];
1089 
1090  unsigned Dst = MRI->createGenericVirtualRegister(BigTy);
1091  MIRBuilder.buildUndef(Dst);
1092  for (unsigned i = 0; i < Regs.size(); ++i) {
1093  unsigned NewDst = MRI->createGenericVirtualRegister(BigTy);
1094  MIRBuilder.buildInsert(NewDst, Dst, Regs[i], Offsets[i]);
1095  Dst = NewDst;
1096  }
1097  return Dst;
1098 }
1099 
1100 void IRTranslator::unpackRegs(const Value &V, unsigned Src,
1101  MachineIRBuilder &MIRBuilder) {
1102  ArrayRef<unsigned> Regs = getOrCreateVRegs(V);
1103  ArrayRef<uint64_t> Offsets = *VMap.getOffsets(V);
1104 
1105  for (unsigned i = 0; i < Regs.size(); ++i)
1106  MIRBuilder.buildExtract(Regs[i], Src, Offsets[i]);
1107 }
1108 
1109 bool IRTranslator::translateCall(const User &U, MachineIRBuilder &MIRBuilder) {
1110  const CallInst &CI = cast<CallInst>(U);
1111  auto TII = MF->getTarget().getIntrinsicInfo();
1112  const Function *F = CI.getCalledFunction();
1113 
1114  // FIXME: support Windows dllimport function calls.
1115  if (F && F->hasDLLImportStorageClass())
1116  return false;
1117 
1118  if (CI.isInlineAsm())
1119  return translateInlineAsm(CI, MIRBuilder);
1120 
1122  if (F && F->isIntrinsic()) {
1123  ID = F->getIntrinsicID();
1124  if (TII && ID == Intrinsic::not_intrinsic)
1125  ID = static_cast<Intrinsic::ID>(TII->getIntrinsicID(F));
1126  }
1127 
1128  bool IsSplitType = valueIsSplit(CI);
1129  if (!F || !F->isIntrinsic() || ID == Intrinsic::not_intrinsic) {
1130  unsigned Res = IsSplitType ? MRI->createGenericVirtualRegister(
1131  getLLTForType(*CI.getType(), *DL))
1132  : getOrCreateVReg(CI);
1133 
1135  for (auto &Arg: CI.arg_operands())
1136  Args.push_back(packRegs(*Arg, MIRBuilder));
1137 
1138  MF->getFrameInfo().setHasCalls(true);
1139  bool Success = CLI->lowerCall(MIRBuilder, &CI, Res, Args, [&]() {
1140  return getOrCreateVReg(*CI.getCalledValue());
1141  });
1142 
1143  if (IsSplitType)
1144  unpackRegs(CI, Res, MIRBuilder);
1145  return Success;
1146  }
1147 
1148  assert(ID != Intrinsic::not_intrinsic && "unknown intrinsic");
1149 
1150  if (translateKnownIntrinsic(CI, ID, MIRBuilder))
1151  return true;
1152 
1153  unsigned Res = 0;
1154  if (!CI.getType()->isVoidTy()) {
1155  if (IsSplitType)
1156  Res =
1157  MRI->createGenericVirtualRegister(getLLTForType(*CI.getType(), *DL));
1158  else
1159  Res = getOrCreateVReg(CI);
1160  }
1161  MachineInstrBuilder MIB =
1162  MIRBuilder.buildIntrinsic(ID, Res, !CI.doesNotAccessMemory());
1163 
1164  for (auto &Arg : CI.arg_operands()) {
1165  // Some intrinsics take metadata parameters. Reject them.
1166  if (isa<MetadataAsValue>(Arg))
1167  return false;
1168  MIB.addUse(packRegs(*Arg, MIRBuilder));
1169  }
1170 
1171  if (IsSplitType)
1172  unpackRegs(CI, Res, MIRBuilder);
1173 
1174  // Add a MachineMemOperand if it is a target mem intrinsic.
1175  const TargetLowering &TLI = *MF->getSubtarget().getTargetLowering();
1176  TargetLowering::IntrinsicInfo Info;
1177  // TODO: Add a GlobalISel version of getTgtMemIntrinsic.
1178  if (TLI.getTgtMemIntrinsic(Info, CI, *MF, ID)) {
1179  uint64_t Size = Info.memVT.getStoreSize();
1180  MIB.addMemOperand(MF->getMachineMemOperand(MachinePointerInfo(Info.ptrVal),
1181  Info.flags, Size, Info.align));
1182  }
1183 
1184  return true;
1185 }
1186 
1187 bool IRTranslator::translateInvoke(const User &U,
1188  MachineIRBuilder &MIRBuilder) {
1189  const InvokeInst &I = cast<InvokeInst>(U);
1190  MCContext &Context = MF->getContext();
1191 
1192  const BasicBlock *ReturnBB = I.getSuccessor(0);
1193  const BasicBlock *EHPadBB = I.getSuccessor(1);
1194 
1195  const Value *Callee = I.getCalledValue();
1196  const Function *Fn = dyn_cast<Function>(Callee);
1197  if (isa<InlineAsm>(Callee))
1198  return false;
1199 
1200  // FIXME: support invoking patchpoint and statepoint intrinsics.
1201  if (Fn && Fn->isIntrinsic())
1202  return false;
1203 
1204  // FIXME: support whatever these are.
1206  return false;
1207 
1208  // FIXME: support Windows exception handling.
1209  if (!isa<LandingPadInst>(EHPadBB->front()))
1210  return false;
1211 
1212  // Emit the actual call, bracketed by EH_LABELs so that the MF knows about
1213  // the region covered by the try.
1214  MCSymbol *BeginSymbol = Context.createTempSymbol();
1215  MIRBuilder.buildInstr(TargetOpcode::EH_LABEL).addSym(BeginSymbol);
1216 
1217  unsigned Res =
1218  MRI->createGenericVirtualRegister(getLLTForType(*I.getType(), *DL));
1220  for (auto &Arg: I.arg_operands())
1221  Args.push_back(packRegs(*Arg, MIRBuilder));
1222 
1223  if (!CLI->lowerCall(MIRBuilder, &I, Res, Args,
1224  [&]() { return getOrCreateVReg(*I.getCalledValue()); }))
1225  return false;
1226 
1227  unpackRegs(I, Res, MIRBuilder);
1228 
1229  MCSymbol *EndSymbol = Context.createTempSymbol();
1230  MIRBuilder.buildInstr(TargetOpcode::EH_LABEL).addSym(EndSymbol);
1231 
1232  // FIXME: track probabilities.
1233  MachineBasicBlock &EHPadMBB = getMBB(*EHPadBB),
1234  &ReturnMBB = getMBB(*ReturnBB);
1235  MF->addInvoke(&EHPadMBB, BeginSymbol, EndSymbol);
1236  MIRBuilder.getMBB().addSuccessor(&ReturnMBB);
1237  MIRBuilder.getMBB().addSuccessor(&EHPadMBB);
1238  MIRBuilder.buildBr(ReturnMBB);
1239 
1240  return true;
1241 }
1242 
1243 bool IRTranslator::translateLandingPad(const User &U,
1244  MachineIRBuilder &MIRBuilder) {
1245  const LandingPadInst &LP = cast<LandingPadInst>(U);
1246 
1247  MachineBasicBlock &MBB = MIRBuilder.getMBB();
1248 
1249  MBB.setIsEHPad();
1250 
1251  // If there aren't registers to copy the values into (e.g., during SjLj
1252  // exceptions), then don't bother.
1253  auto &TLI = *MF->getSubtarget().getTargetLowering();
1254  const Constant *PersonalityFn = MF->getFunction().getPersonalityFn();
1255  if (TLI.getExceptionPointerRegister(PersonalityFn) == 0 &&
1256  TLI.getExceptionSelectorRegister(PersonalityFn) == 0)
1257  return true;
1258 
1259  // If landingpad's return type is token type, we don't create DAG nodes
1260  // for its exception pointer and selector value. The extraction of exception
1261  // pointer or selector value from token type landingpads is not currently
1262  // supported.
1263  if (LP.getType()->isTokenTy())
1264  return true;
1265 
1266  // Add a label to mark the beginning of the landing pad. Deletion of the
1267  // landing pad can thus be detected via the MachineModuleInfo.
1269  .addSym(MF->addLandingPad(&MBB));
1270 
1271  LLT Ty = getLLTForType(*LP.getType(), *DL);
1272  unsigned Undef = MRI->createGenericVirtualRegister(Ty);
1273  MIRBuilder.buildUndef(Undef);
1274 
1275  SmallVector<LLT, 2> Tys;
1276  for (Type *Ty : cast<StructType>(LP.getType())->elements())
1277  Tys.push_back(getLLTForType(*Ty, *DL));
1278  assert(Tys.size() == 2 && "Only two-valued landingpads are supported");
1279 
1280  // Mark exception register as live in.
1281  unsigned ExceptionReg = TLI.getExceptionPointerRegister(PersonalityFn);
1282  if (!ExceptionReg)
1283  return false;
1284 
1285  MBB.addLiveIn(ExceptionReg);
1286  ArrayRef<unsigned> ResRegs = getOrCreateVRegs(LP);
1287  MIRBuilder.buildCopy(ResRegs[0], ExceptionReg);
1288 
1289  unsigned SelectorReg = TLI.getExceptionSelectorRegister(PersonalityFn);
1290  if (!SelectorReg)
1291  return false;
1292 
1293  MBB.addLiveIn(SelectorReg);
1294  unsigned PtrVReg = MRI->createGenericVirtualRegister(Tys[0]);
1295  MIRBuilder.buildCopy(PtrVReg, SelectorReg);
1296  MIRBuilder.buildCast(ResRegs[1], PtrVReg);
1297 
1298  return true;
1299 }
1300 
1301 bool IRTranslator::translateAlloca(const User &U,
1302  MachineIRBuilder &MIRBuilder) {
1303  auto &AI = cast<AllocaInst>(U);
1304 
1305  if (AI.isSwiftError())
1306  return false;
1307 
1308  if (AI.isStaticAlloca()) {
1309  unsigned Res = getOrCreateVReg(AI);
1310  int FI = getOrCreateFrameIndex(AI);
1311  MIRBuilder.buildFrameIndex(Res, FI);
1312  return true;
1313  }
1314 
1315  // FIXME: support stack probing for Windows.
1316  if (MF->getTarget().getTargetTriple().isOSWindows())
1317  return false;
1318 
1319  // Now we're in the harder dynamic case.
1320  Type *Ty = AI.getAllocatedType();
1321  unsigned Align =
1322  std::max((unsigned)DL->getPrefTypeAlignment(Ty), AI.getAlignment());
1323 
1324  unsigned NumElts = getOrCreateVReg(*AI.getArraySize());
1325 
1326  Type *IntPtrIRTy = DL->getIntPtrType(AI.getType());
1327  LLT IntPtrTy = getLLTForType(*IntPtrIRTy, *DL);
1328  if (MRI->getType(NumElts) != IntPtrTy) {
1329  unsigned ExtElts = MRI->createGenericVirtualRegister(IntPtrTy);
1330  MIRBuilder.buildZExtOrTrunc(ExtElts, NumElts);
1331  NumElts = ExtElts;
1332  }
1333 
1334  unsigned AllocSize = MRI->createGenericVirtualRegister(IntPtrTy);
1335  unsigned TySize =
1336  getOrCreateVReg(*ConstantInt::get(IntPtrIRTy, -DL->getTypeAllocSize(Ty)));
1337  MIRBuilder.buildMul(AllocSize, NumElts, TySize);
1338 
1339  LLT PtrTy = getLLTForType(*AI.getType(), *DL);
1340  auto &TLI = *MF->getSubtarget().getTargetLowering();
1341  unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
1342 
1343  unsigned SPTmp = MRI->createGenericVirtualRegister(PtrTy);
1344  MIRBuilder.buildCopy(SPTmp, SPReg);
1345 
1346  unsigned AllocTmp = MRI->createGenericVirtualRegister(PtrTy);
1347  MIRBuilder.buildGEP(AllocTmp, SPTmp, AllocSize);
1348 
1349  // Handle alignment. We have to realign if the allocation granule was smaller
1350  // than stack alignment, or the specific alloca requires more than stack
1351  // alignment.
1352  unsigned StackAlign =
1353  MF->getSubtarget().getFrameLowering()->getStackAlignment();
1354  Align = std::max(Align, StackAlign);
1355  if (Align > StackAlign || DL->getTypeAllocSize(Ty) % StackAlign != 0) {
1356  // Round the size of the allocation up to the stack alignment size
1357  // by add SA-1 to the size. This doesn't overflow because we're computing
1358  // an address inside an alloca.
1359  unsigned AlignedAlloc = MRI->createGenericVirtualRegister(PtrTy);
1360  MIRBuilder.buildPtrMask(AlignedAlloc, AllocTmp, Log2_32(Align));
1361  AllocTmp = AlignedAlloc;
1362  }
1363 
1364  MIRBuilder.buildCopy(SPReg, AllocTmp);
1365  MIRBuilder.buildCopy(getOrCreateVReg(AI), AllocTmp);
1366 
1367  MF->getFrameInfo().CreateVariableSizedObject(Align ? Align : 1, &AI);
1368  assert(MF->getFrameInfo().hasVarSizedObjects());
1369  return true;
1370 }
1371 
1372 bool IRTranslator::translateVAArg(const User &U, MachineIRBuilder &MIRBuilder) {
1373  // FIXME: We may need more info about the type. Because of how LLT works,
1374  // we're completely discarding the i64/double distinction here (amongst
1375  // others). Fortunately the ABIs I know of where that matters don't use va_arg
1376  // anyway but that's not guaranteed.
1377  MIRBuilder.buildInstr(TargetOpcode::G_VAARG)
1378  .addDef(getOrCreateVReg(U))
1379  .addUse(getOrCreateVReg(*U.getOperand(0)))
1380  .addImm(DL->getABITypeAlignment(U.getType()));
1381  return true;
1382 }
1383 
1384 bool IRTranslator::translateInsertElement(const User &U,
1385  MachineIRBuilder &MIRBuilder) {
1386  // If it is a <1 x Ty> vector, use the scalar as it is
1387  // not a legal vector type in LLT.
1388  if (U.getType()->getVectorNumElements() == 1) {
1389  unsigned Elt = getOrCreateVReg(*U.getOperand(1));
1390  auto &Regs = *VMap.getVRegs(U);
1391  if (Regs.empty()) {
1392  Regs.push_back(Elt);
1393  VMap.getOffsets(U)->push_back(0);
1394  } else {
1395  MIRBuilder.buildCopy(Regs[0], Elt);
1396  }
1397  return true;
1398  }
1399 
1400  unsigned Res = getOrCreateVReg(U);
1401  unsigned Val = getOrCreateVReg(*U.getOperand(0));
1402  unsigned Elt = getOrCreateVReg(*U.getOperand(1));
1403  unsigned Idx = getOrCreateVReg(*U.getOperand(2));
1404  MIRBuilder.buildInsertVectorElement(Res, Val, Elt, Idx);
1405  return true;
1406 }
1407 
1408 bool IRTranslator::translateExtractElement(const User &U,
1409  MachineIRBuilder &MIRBuilder) {
1410  // If it is a <1 x Ty> vector, use the scalar as it is
1411  // not a legal vector type in LLT.
1412  if (U.getOperand(0)->getType()->getVectorNumElements() == 1) {
1413  unsigned Elt = getOrCreateVReg(*U.getOperand(0));
1414  auto &Regs = *VMap.getVRegs(U);
1415  if (Regs.empty()) {
1416  Regs.push_back(Elt);
1417  VMap.getOffsets(U)->push_back(0);
1418  } else {
1419  MIRBuilder.buildCopy(Regs[0], Elt);
1420  }
1421  return true;
1422  }
1423  unsigned Res = getOrCreateVReg(U);
1424  unsigned Val = getOrCreateVReg(*U.getOperand(0));
1425  const auto &TLI = *MF->getSubtarget().getTargetLowering();
1426  unsigned PreferredVecIdxWidth = TLI.getVectorIdxTy(*DL).getSizeInBits();
1427  unsigned Idx = 0;
1428  if (auto *CI = dyn_cast<ConstantInt>(U.getOperand(1))) {
1429  if (CI->getBitWidth() != PreferredVecIdxWidth) {
1430  APInt NewIdx = CI->getValue().sextOrTrunc(PreferredVecIdxWidth);
1431  auto *NewIdxCI = ConstantInt::get(CI->getContext(), NewIdx);
1432  Idx = getOrCreateVReg(*NewIdxCI);
1433  }
1434  }
1435  if (!Idx)
1436  Idx = getOrCreateVReg(*U.getOperand(1));
1437  if (MRI->getType(Idx).getSizeInBits() != PreferredVecIdxWidth) {
1438  const LLT &VecIdxTy = LLT::scalar(PreferredVecIdxWidth);
1439  Idx = MIRBuilder.buildSExtOrTrunc(VecIdxTy, Idx)->getOperand(0).getReg();
1440  }
1441  MIRBuilder.buildExtractVectorElement(Res, Val, Idx);
1442  return true;
1443 }
1444 
1445 bool IRTranslator::translateShuffleVector(const User &U,
1446  MachineIRBuilder &MIRBuilder) {
1447  MIRBuilder.buildInstr(TargetOpcode::G_SHUFFLE_VECTOR)
1448  .addDef(getOrCreateVReg(U))
1449  .addUse(getOrCreateVReg(*U.getOperand(0)))
1450  .addUse(getOrCreateVReg(*U.getOperand(1)))
1451  .addUse(getOrCreateVReg(*U.getOperand(2)));
1452  return true;
1453 }
1454 
1455 bool IRTranslator::translatePHI(const User &U, MachineIRBuilder &MIRBuilder) {
1456  const PHINode &PI = cast<PHINode>(U);
1457 
1459  for (auto Reg : getOrCreateVRegs(PI)) {
1460  auto MIB = MIRBuilder.buildInstr(TargetOpcode::G_PHI, {Reg}, {});
1461  Insts.push_back(MIB.getInstr());
1462  }
1463 
1464  PendingPHIs.emplace_back(&PI, std::move(Insts));
1465  return true;
1466 }
1467 
1468 bool IRTranslator::translateAtomicCmpXchg(const User &U,
1469  MachineIRBuilder &MIRBuilder) {
1470  const AtomicCmpXchgInst &I = cast<AtomicCmpXchgInst>(U);
1471 
1472  if (I.isWeak())
1473  return false;
1474 
1475  auto Flags = I.isVolatile() ? MachineMemOperand::MOVolatile
1478 
1479  Type *ResType = I.getType();
1480  Type *ValType = ResType->Type::getStructElementType(0);
1481 
1482  auto Res = getOrCreateVRegs(I);
1483  unsigned OldValRes = Res[0];
1484  unsigned SuccessRes = Res[1];
1485  unsigned Addr = getOrCreateVReg(*I.getPointerOperand());
1486  unsigned Cmp = getOrCreateVReg(*I.getCompareOperand());
1487  unsigned NewVal = getOrCreateVReg(*I.getNewValOperand());
1488 
1489  MIRBuilder.buildAtomicCmpXchgWithSuccess(
1490  OldValRes, SuccessRes, Addr, Cmp, NewVal,
1491  *MF->getMachineMemOperand(MachinePointerInfo(I.getPointerOperand()),
1492  Flags, DL->getTypeStoreSize(ValType),
1493  getMemOpAlignment(I), AAMDNodes(), nullptr,
1495  I.getFailureOrdering()));
1496  return true;
1497 }
1498 
1499 bool IRTranslator::translateAtomicRMW(const User &U,
1500  MachineIRBuilder &MIRBuilder) {
1501  const AtomicRMWInst &I = cast<AtomicRMWInst>(U);
1502 
1503  auto Flags = I.isVolatile() ? MachineMemOperand::MOVolatile
1506 
1507  Type *ResType = I.getType();
1508 
1509  unsigned Res = getOrCreateVReg(I);
1510  unsigned Addr = getOrCreateVReg(*I.getPointerOperand());
1511  unsigned Val = getOrCreateVReg(*I.getValOperand());
1512 
1513  unsigned Opcode = 0;
1514  switch (I.getOperation()) {
1515  default:
1516  llvm_unreachable("Unknown atomicrmw op");
1517  return false;
1518  case AtomicRMWInst::Xchg:
1519  Opcode = TargetOpcode::G_ATOMICRMW_XCHG;
1520  break;
1521  case AtomicRMWInst::Add:
1522  Opcode = TargetOpcode::G_ATOMICRMW_ADD;
1523  break;
1524  case AtomicRMWInst::Sub:
1525  Opcode = TargetOpcode::G_ATOMICRMW_SUB;
1526  break;
1527  case AtomicRMWInst::And:
1528  Opcode = TargetOpcode::G_ATOMICRMW_AND;
1529  break;
1530  case AtomicRMWInst::Nand:
1531  Opcode = TargetOpcode::G_ATOMICRMW_NAND;
1532  break;
1533  case AtomicRMWInst::Or:
1534  Opcode = TargetOpcode::G_ATOMICRMW_OR;
1535  break;
1536  case AtomicRMWInst::Xor:
1537  Opcode = TargetOpcode::G_ATOMICRMW_XOR;
1538  break;
1539  case AtomicRMWInst::Max:
1540  Opcode = TargetOpcode::G_ATOMICRMW_MAX;
1541  break;
1542  case AtomicRMWInst::Min:
1543  Opcode = TargetOpcode::G_ATOMICRMW_MIN;
1544  break;
1545  case AtomicRMWInst::UMax:
1546  Opcode = TargetOpcode::G_ATOMICRMW_UMAX;
1547  break;
1548  case AtomicRMWInst::UMin:
1549  Opcode = TargetOpcode::G_ATOMICRMW_UMIN;
1550  break;
1551  }
1552 
1553  MIRBuilder.buildAtomicRMW(
1554  Opcode, Res, Addr, Val,
1555  *MF->getMachineMemOperand(MachinePointerInfo(I.getPointerOperand()),
1556  Flags, DL->getTypeStoreSize(ResType),
1557  getMemOpAlignment(I), AAMDNodes(), nullptr,
1558  I.getSyncScopeID(), I.getOrdering()));
1559  return true;
1560 }
1561 
1562 void IRTranslator::finishPendingPhis() {
1563 #ifndef NDEBUG
1564  DILocationVerifier Verifier;
1565  GISelObserverWrapper WrapperObserver(&Verifier);
1566  RAIIDelegateInstaller DelInstall(*MF, &WrapperObserver);
1567 #endif // ifndef NDEBUG
1568  for (auto &Phi : PendingPHIs) {
1569  const PHINode *PI = Phi.first;
1570  ArrayRef<MachineInstr *> ComponentPHIs = Phi.second;
1571  EntryBuilder->setDebugLoc(PI->getDebugLoc());
1572 #ifndef NDEBUG
1573  Verifier.setCurrentInst(PI);
1574 #endif // ifndef NDEBUG
1575 
1576  // All MachineBasicBlocks exist, add them to the PHI. We assume IRTranslator
1577  // won't create extra control flow here, otherwise we need to find the
1578  // dominating predecessor here (or perhaps force the weirder IRTranslators
1579  // to provide a simple boundary).
1580  SmallSet<const BasicBlock *, 4> HandledPreds;
1581 
1582  for (unsigned i = 0; i < PI->getNumIncomingValues(); ++i) {
1583  auto IRPred = PI->getIncomingBlock(i);
1584  if (HandledPreds.count(IRPred))
1585  continue;
1586 
1587  HandledPreds.insert(IRPred);
1588  ArrayRef<unsigned> ValRegs = getOrCreateVRegs(*PI->getIncomingValue(i));
1589  for (auto Pred : getMachinePredBBs({IRPred, PI->getParent()})) {
1590  assert(Pred->isSuccessor(ComponentPHIs[0]->getParent()) &&
1591  "incorrect CFG at MachineBasicBlock level");
1592  for (unsigned j = 0; j < ValRegs.size(); ++j) {
1593  MachineInstrBuilder MIB(*MF, ComponentPHIs[j]);
1594  MIB.addUse(ValRegs[j]);
1595  MIB.addMBB(Pred);
1596  }
1597  }
1598  }
1599  }
1600 }
1601 
1602 bool IRTranslator::valueIsSplit(const Value &V,
1604  SmallVector<LLT, 4> SplitTys;
1605  if (Offsets && !Offsets->empty())
1606  Offsets->clear();
1607  computeValueLLTs(*DL, *V.getType(), SplitTys, Offsets);
1608  return SplitTys.size() > 1;
1609 }
1610 
1611 bool IRTranslator::translate(const Instruction &Inst) {
1612  CurBuilder->setDebugLoc(Inst.getDebugLoc());
1613  EntryBuilder->setDebugLoc(Inst.getDebugLoc());
1614  switch(Inst.getOpcode()) {
1615 #define HANDLE_INST(NUM, OPCODE, CLASS) \
1616  case Instruction::OPCODE: \
1617  return translate##OPCODE(Inst, *CurBuilder.get());
1618 #include "llvm/IR/Instruction.def"
1619  default:
1620  return false;
1621  }
1622 }
1623 
1624 bool IRTranslator::translate(const Constant &C, unsigned Reg) {
1625  if (auto CI = dyn_cast<ConstantInt>(&C))
1626  EntryBuilder->buildConstant(Reg, *CI);
1627  else if (auto CF = dyn_cast<ConstantFP>(&C))
1628  EntryBuilder->buildFConstant(Reg, *CF);
1629  else if (isa<UndefValue>(C))
1630  EntryBuilder->buildUndef(Reg);
1631  else if (isa<ConstantPointerNull>(C)) {
1632  // As we are trying to build a constant val of 0 into a pointer,
1633  // insert a cast to make them correct with respect to types.
1634  unsigned NullSize = DL->getTypeSizeInBits(C.getType());
1635  auto *ZeroTy = Type::getIntNTy(C.getContext(), NullSize);
1636  auto *ZeroVal = ConstantInt::get(ZeroTy, 0);
1637  unsigned ZeroReg = getOrCreateVReg(*ZeroVal);
1638  EntryBuilder->buildCast(Reg, ZeroReg);
1639  } else if (auto GV = dyn_cast<GlobalValue>(&C))
1640  EntryBuilder->buildGlobalValue(Reg, GV);
1641  else if (auto CAZ = dyn_cast<ConstantAggregateZero>(&C)) {
1642  if (!CAZ->getType()->isVectorTy())
1643  return false;
1644  // Return the scalar if it is a <1 x Ty> vector.
1645  if (CAZ->getNumElements() == 1)
1646  return translate(*CAZ->getElementValue(0u), Reg);
1648  for (unsigned i = 0; i < CAZ->getNumElements(); ++i) {
1649  Constant &Elt = *CAZ->getElementValue(i);
1650  Ops.push_back(getOrCreateVReg(Elt));
1651  }
1652  EntryBuilder->buildBuildVector(Reg, Ops);
1653  } else if (auto CV = dyn_cast<ConstantDataVector>(&C)) {
1654  // Return the scalar if it is a <1 x Ty> vector.
1655  if (CV->getNumElements() == 1)
1656  return translate(*CV->getElementAsConstant(0), Reg);
1658  for (unsigned i = 0; i < CV->getNumElements(); ++i) {
1659  Constant &Elt = *CV->getElementAsConstant(i);
1660  Ops.push_back(getOrCreateVReg(Elt));
1661  }
1662  EntryBuilder->buildBuildVector(Reg, Ops);
1663  } else if (auto CE = dyn_cast<ConstantExpr>(&C)) {
1664  switch(CE->getOpcode()) {
1665 #define HANDLE_INST(NUM, OPCODE, CLASS) \
1666  case Instruction::OPCODE: \
1667  return translate##OPCODE(*CE, *EntryBuilder.get());
1668 #include "llvm/IR/Instruction.def"
1669  default:
1670  return false;
1671  }
1672  } else if (auto CV = dyn_cast<ConstantVector>(&C)) {
1673  if (CV->getNumOperands() == 1)
1674  return translate(*CV->getOperand(0), Reg);
1676  for (unsigned i = 0; i < CV->getNumOperands(); ++i) {
1677  Ops.push_back(getOrCreateVReg(*CV->getOperand(i)));
1678  }
1679  EntryBuilder->buildBuildVector(Reg, Ops);
1680  } else if (auto *BA = dyn_cast<BlockAddress>(&C)) {
1681  EntryBuilder->buildBlockAddress(Reg, BA);
1682  } else
1683  return false;
1684 
1685  return true;
1686 }
1687 
1688 void IRTranslator::finalizeFunction() {
1689  // Release the memory used by the different maps we
1690  // needed during the translation.
1691  PendingPHIs.clear();
1692  VMap.reset();
1693  FrameIndices.clear();
1694  MachinePreds.clear();
1695  // MachineIRBuilder::DebugLoc can outlive the DILocation it holds. Clear it
1696  // to avoid accessing free’d memory (in runOnMachineFunction) and to avoid
1697  // destroying it twice (in ~IRTranslator() and ~LLVMContext())
1698  EntryBuilder.reset();
1699  CurBuilder.reset();
1700 }
1701 
1703  MF = &CurMF;
1704  const Function &F = MF->getFunction();
1705  if (F.empty())
1706  return false;
1708  getAnalysis<GISelCSEAnalysisWrapperPass>().getCSEWrapper();
1709  // Set the CSEConfig and run the analysis.
1710  GISelCSEInfo *CSEInfo = nullptr;
1711  TPC = &getAnalysis<TargetPassConfig>();
1712  bool IsO0 = TPC->getOptLevel() == CodeGenOpt::Level::None;
1713  // Disable CSE for O0.
1714  bool EnableCSE = !IsO0 && EnableCSEInIRTranslator;
1715  if (EnableCSE) {
1716  EntryBuilder = make_unique<CSEMIRBuilder>(CurMF);
1717  std::unique_ptr<CSEConfig> Config = make_unique<CSEConfig>();
1718  CSEInfo = &Wrapper.get(std::move(Config));
1719  EntryBuilder->setCSEInfo(CSEInfo);
1720  CurBuilder = make_unique<CSEMIRBuilder>(CurMF);
1721  CurBuilder->setCSEInfo(CSEInfo);
1722  } else {
1723  EntryBuilder = make_unique<MachineIRBuilder>();
1724  CurBuilder = make_unique<MachineIRBuilder>();
1725  }
1726  CLI = MF->getSubtarget().getCallLowering();
1727  CurBuilder->setMF(*MF);
1728  EntryBuilder->setMF(*MF);
1729  MRI = &MF->getRegInfo();
1730  DL = &F.getParent()->getDataLayout();
1731  ORE = llvm::make_unique<OptimizationRemarkEmitter>(&F);
1732 
1733  assert(PendingPHIs.empty() && "stale PHIs");
1734 
1735  if (!DL->isLittleEndian()) {
1736  // Currently we don't properly handle big endian code.
1737  OptimizationRemarkMissed R("gisel-irtranslator", "GISelFailure",
1738  F.getSubprogram(), &F.getEntryBlock());
1739  R << "unable to translate in big endian mode";
1740  reportTranslationError(*MF, *TPC, *ORE, R);
1741  }
1742 
1743  // Release the per-function state when we return, whether we succeeded or not.
1744  auto FinalizeOnReturn = make_scope_exit([this]() { finalizeFunction(); });
1745 
1746  // Setup a separate basic-block for the arguments and constants
1747  MachineBasicBlock *EntryBB = MF->CreateMachineBasicBlock();
1748  MF->push_back(EntryBB);
1749  EntryBuilder->setMBB(*EntryBB);
1750 
1751  // Create all blocks, in IR order, to preserve the layout.
1752  for (const BasicBlock &BB: F) {
1753  auto *&MBB = BBToMBB[&BB];
1754 
1755  MBB = MF->CreateMachineBasicBlock(&BB);
1756  MF->push_back(MBB);
1757 
1758  if (BB.hasAddressTaken())
1759  MBB->setHasAddressTaken();
1760  }
1761 
1762  // Make our arguments/constants entry block fallthrough to the IR entry block.
1763  EntryBB->addSuccessor(&getMBB(F.front()));
1764 
1765  // Lower the actual args into this basic block.
1766  SmallVector<unsigned, 8> VRegArgs;
1767  for (const Argument &Arg: F.args()) {
1768  if (DL->getTypeStoreSize(Arg.getType()) == 0)
1769  continue; // Don't handle zero sized types.
1770  VRegArgs.push_back(
1771  MRI->createGenericVirtualRegister(getLLTForType(*Arg.getType(), *DL)));
1772  }
1773 
1774  // We don't currently support translating swifterror or swiftself functions.
1775  for (auto &Arg : F.args()) {
1776  if (Arg.hasSwiftErrorAttr() || Arg.hasSwiftSelfAttr()) {
1777  OptimizationRemarkMissed R("gisel-irtranslator", "GISelFailure",
1778  F.getSubprogram(), &F.getEntryBlock());
1779  R << "unable to lower arguments due to swifterror/swiftself: "
1780  << ore::NV("Prototype", F.getType());
1781  reportTranslationError(*MF, *TPC, *ORE, R);
1782  return false;
1783  }
1784  }
1785 
1786  if (!CLI->lowerFormalArguments(*EntryBuilder.get(), F, VRegArgs)) {
1787  OptimizationRemarkMissed R("gisel-irtranslator", "GISelFailure",
1788  F.getSubprogram(), &F.getEntryBlock());
1789  R << "unable to lower arguments: " << ore::NV("Prototype", F.getType());
1790  reportTranslationError(*MF, *TPC, *ORE, R);
1791  return false;
1792  }
1793 
1794  auto ArgIt = F.arg_begin();
1795  for (auto &VArg : VRegArgs) {
1796  // If the argument is an unsplit scalar then don't use unpackRegs to avoid
1797  // creating redundant copies.
1798  if (!valueIsSplit(*ArgIt, VMap.getOffsets(*ArgIt))) {
1799  auto &VRegs = *VMap.getVRegs(cast<Value>(*ArgIt));
1800  assert(VRegs.empty() && "VRegs already populated?");
1801  VRegs.push_back(VArg);
1802  } else {
1803  unpackRegs(*ArgIt, VArg, *EntryBuilder.get());
1804  }
1805  ArgIt++;
1806  }
1807 
1808  // Need to visit defs before uses when translating instructions.
1809  GISelObserverWrapper WrapperObserver;
1810  if (EnableCSE && CSEInfo)
1811  WrapperObserver.addObserver(CSEInfo);
1812  {
1814 #ifndef NDEBUG
1815  DILocationVerifier Verifier;
1816  WrapperObserver.addObserver(&Verifier);
1817 #endif // ifndef NDEBUG
1818  RAIIDelegateInstaller DelInstall(*MF, &WrapperObserver);
1819  for (const BasicBlock *BB : RPOT) {
1820  MachineBasicBlock &MBB = getMBB(*BB);
1821  // Set the insertion point of all the following translations to
1822  // the end of this basic block.
1823  CurBuilder->setMBB(MBB);
1824 
1825  for (const Instruction &Inst : *BB) {
1826 #ifndef NDEBUG
1827  Verifier.setCurrentInst(&Inst);
1828 #endif // ifndef NDEBUG
1829  if (translate(Inst))
1830  continue;
1831 
1832  OptimizationRemarkMissed R("gisel-irtranslator", "GISelFailure",
1833  Inst.getDebugLoc(), BB);
1834  R << "unable to translate instruction: " << ore::NV("Opcode", &Inst);
1835 
1836  if (ORE->allowExtraAnalysis("gisel-irtranslator")) {
1837  std::string InstStrStorage;
1838  raw_string_ostream InstStr(InstStrStorage);
1839  InstStr << Inst;
1840 
1841  R << ": '" << InstStr.str() << "'";
1842  }
1843 
1844  reportTranslationError(*MF, *TPC, *ORE, R);
1845  return false;
1846  }
1847  }
1848 #ifndef NDEBUG
1849  WrapperObserver.removeObserver(&Verifier);
1850 #endif
1851  }
1852 
1853  finishPendingPhis();
1854 
1855  // Merge the argument lowering and constants block with its single
1856  // successor, the LLVM-IR entry block. We want the basic block to
1857  // be maximal.
1858  assert(EntryBB->succ_size() == 1 &&
1859  "Custom BB used for lowering should have only one successor");
1860  // Get the successor of the current entry block.
1861  MachineBasicBlock &NewEntryBB = **EntryBB->succ_begin();
1862  assert(NewEntryBB.pred_size() == 1 &&
1863  "LLVM-IR entry block has a predecessor!?");
1864  // Move all the instruction from the current entry block to the
1865  // new entry block.
1866  NewEntryBB.splice(NewEntryBB.begin(), EntryBB, EntryBB->begin(),
1867  EntryBB->end());
1868 
1869  // Update the live-in information for the new entry block.
1870  for (const MachineBasicBlock::RegisterMaskPair &LiveIn : EntryBB->liveins())
1871  NewEntryBB.addLiveIn(LiveIn);
1872  NewEntryBB.sortUniqueLiveIns();
1873 
1874  // Get rid of the now empty basic block.
1875  EntryBB->removeSuccessor(&NewEntryBB);
1876  MF->remove(EntryBB);
1877  MF->DeleteMachineBasicBlock(EntryBB);
1878 
1879  assert(&MF->front() == &NewEntryBB &&
1880  "New entry wasn't next in the list of basic block!");
1881 
1882  // Initialize stack protector information.
1883  StackProtector &SP = getAnalysis<StackProtector>();
1884  SP.copyToMachineFrameInfo(MF->getFrameInfo());
1885 
1886  return false;
1887 }
const NoneType None
Definition: None.h:23
uint64_t CallInst * C
void initializeIRTranslatorPass(PassRegistry &)
Return a value (possibly void), from a function.
Value * getValueOperand()
Definition: Instructions.h:409
bool isIntrinsic() const
isIntrinsic - Returns true if the function&#39;s name starts with "llvm.".
Definition: Function.h:198
A simple RAII based CSEInfo installer.
virtual MachineInstrBuilder buildConstant(const DstOp &Res, const ConstantInt &Val)
Build and insert Res = G_CONSTANT Val.
A parsed version of the target data layout string in and methods for querying it. ...
Definition: DataLayout.h:110
constexpr char Align[]
Key for Kernel::Arg::Metadata::mAlign.
This class is the base class for the comparison instructions.
Definition: InstrTypes.h:635
bool empty() const
Definition: Function.h:661
static IntegerType * getInt1Ty(LLVMContext &C)
Definition: Type.cpp:172
The CSE Analysis object.
Definition: CSEInfo.h:68
Diagnostic information for missed-optimization remarks.
This instruction extracts a struct member or array element value from an aggregate value...
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
MachineInstrBuilder buildZExtOrTrunc(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_ZEXT Op, Res = G_TRUNC Op, or Res = COPY Op depending on the differing sizes...
*p = old <signed v ? old : v
Definition: Instructions.h:721
iterator_range< CaseIt > cases()
Iteration adapter for range-for loops.
GCNRegPressure max(const GCNRegPressure &P1, const GCNRegPressure &P2)
This class represents an incoming formal argument to a Function.
Definition: Argument.h:29
LLVMContext & Context
bool doesNotAccessMemory(unsigned OpNo) const
Definition: InstrTypes.h:1428
MachineInstrBuilder buildGEP(unsigned Res, unsigned Op0, unsigned Op1)
Build and insert Res = G_GEP Op0, Op1.
DiagnosticInfoOptimizationBase::Argument NV
This represents the llvm.dbg.label instruction.
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:139
This class represents lattice values for constants.
Definition: AllocatorList.h:23
MachineInstrBuilder buildIndirectDbgValue(unsigned Reg, const MDNode *Variable, const MDNode *Expr)
Build and insert a DBG_VALUE instruction expressing the fact that the associated Variable lives in me...
void getSelectionDAGFallbackAnalysisUsage(AnalysisUsage &AU)
Modify analysis usage so it preserves passes required for the SelectionDAG fallback.
Definition: Utils.cpp:288
MachineInstrBuilder buildSExtOrTrunc(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_SEXT Op, Res = G_TRUNC Op, or Res = COPY Op depending on the differing sizes...
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:41
bool isSized(SmallPtrSetImpl< Type *> *Visited=nullptr) const
Return true if it makes sense to take the size of this type.
Definition: Type.h:264
iterator begin() const
Definition: ArrayRef.h:136
void setIsEHPad(bool V=true)
Indicates the block is a landing pad.
an instruction that atomically checks whether a specified value is in a memory location, and, if it is, stores a new value there.
Definition: Instructions.h:528
const StructLayout * getStructLayout(StructType *Ty) const
Returns a StructLayout object, indicating the alignment of the struct, its size, and the offsets of i...
Definition: DataLayout.cpp:587
void push_back(const T &Elt)
Definition: SmallVector.h:211
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:382
unsigned getReg() const
getReg - Returns the register number.
MachineInstrBuilder buildCast(const DstOp &Dst, const SrcOp &Src)
Build and insert an appropriate cast between two registers of equal size.
IRTranslator LLVM IR static false void reportTranslationError(MachineFunction &MF, const TargetPassConfig &TPC, OptimizationRemarkEmitter &ORE, OptimizationRemarkMissed &R)
This class represents a function call, abstracting a target machine&#39;s calling convention.
unsigned Reg
This file contains the declarations for metadata subclasses.
Value * getCondition() const
static uint64_t round(uint64_t Acc, uint64_t Input)
Definition: xxhash.cpp:57
SyncScope::ID getSyncScopeID() const
Returns the synchronization scope ID of this store instruction.
Definition: Instructions.h:384
gep_type_iterator gep_type_end(const User *GEP)
const std::string & getAsmString() const
Definition: InlineAsm.h:80
*p = old <unsigned v ? old : v
Definition: Instructions.h:725
bool isSwiftError() const
Return true if this alloca is used as a swifterror argument to a call.
Definition: Instructions.h:135
AtomicOrdering getOrdering() const
Returns the ordering constraint of this load instruction.
Definition: Instructions.h:247
Offsets
Offsets in bytes from the start of the input buffer.
Definition: SIInstrInfo.h:1024
*p = old >unsigned v ? old : v
Definition: Instructions.h:723
LLVM_NODISCARD detail::scope_exit< typename std::decay< Callable >::type > make_scope_exit(Callable &&F)
Definition: ScopeExit.h:58
LLVMContext & getContext() const
All values hold a context through their type.
Definition: Value.cpp:704
bool hasDLLImportStorageClass() const
Definition: GlobalValue.h:261
BasicBlock * getSuccessor(unsigned i) const
unsigned const TargetRegisterInfo * TRI
F(f)
The actual analysis pass wrapper.
Definition: CSEInfo.h:212
An instruction for reading from memory.
Definition: Instructions.h:167
void setMF(MachineFunction &MF)
Definition: CSEInfo.cpp:66
an instruction that atomically reads a memory location, combines it with another value, and then stores the result back.
Definition: Instructions.h:691
Value * getCondition() const
bool isVectorTy() const
True if this is an instance of VectorType.
Definition: Type.h:229
MachineInstrBuilder buildExtract(unsigned Res, unsigned Src, uint64_t Index)
Build and insert `Res0, ...
GlobalValue * ExtractTypeInfo(Value *V)
ExtractTypeInfo - Returns the type info, possibly bitcast, encoded in V.
Definition: Analysis.cpp:117
*p = old >signed v ? old : v
Definition: Instructions.h:719
virtual bool getTgtMemIntrinsic(IntrinsicInfo &, const CallInst &, MachineFunction &, unsigned) const
Given an intrinsic, checks if on the target the intrinsic will need to map to a MemIntrinsicNode (tou...
bool runOnMachineFunction(MachineFunction &MF) override
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
static Constant * getNullValue(Type *Ty)
Constructor to create a &#39;0&#39; constant of arbitrary type.
Definition: Constants.cpp:264
AtomicOrdering getFailureOrdering() const
Returns the failure ordering constraint of this cmpxchg instruction.
Definition: Instructions.h:595
bool hasSideEffects() const
Definition: InlineAsm.h:66
Value * getArgOperand(unsigned i) const
Definition: InstrTypes.h:1134
MachineInstrBuilder buildStore(unsigned Val, unsigned Addr, MachineMemOperand &MMO)
Build and insert G_STORE Val, Addr, MMO.
AnalysisUsage & addRequired()
Used to lazily calculate structure layout information for a target machine, based on the DataLayout s...
Definition: DataLayout.h:528
#define INITIALIZE_PASS_DEPENDENCY(depName)
Definition: PassSupport.h:50
bool isVolatile() const
Return true if this is a load from a volatile memory location.
Definition: Instructions.h:231
A description of a memory reference used in the backend.
GISelCSEInfo & get(std::unique_ptr< CSEConfig > CSEOpt, bool ReCompute=false)
Takes a CSEConfig object that defines what opcodes get CSEd.
Definition: CSEInfo.cpp:351
amdgpu aa AMDGPU Address space based Alias Analysis Wrapper
unsigned countOperandBundlesOfType(StringRef Name) const
Return the number of operand bundles with the tag Name attached to this instruction.
Definition: InstrTypes.h:1655
This class represents the LLVM &#39;select&#39; instruction.
const DataLayout & getDataLayout() const
Get the data layout for the module&#39;s target platform.
Definition: Module.cpp:370
#define DEBUG_TYPE
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
const HexagonInstrInfo * TII
unsigned getAlignment() const
Return the alignment of the memory that is being allocated by the instruction.
Definition: Instructions.h:112
PointerType * getType() const
Overload to return most specific pointer type.
Definition: Instructions.h:96
Class to represent struct types.
Definition: DerivedTypes.h:200
DILabel * getLabel() const
BinOp getOperation() const
Definition: Instructions.h:750
const MachineInstrBuilder & addUse(unsigned RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register use operand.
bool isWeak() const
Return true if this cmpxchg may spuriously fail.
Definition: Instructions.h:569
TypeID
Definitions of all of the base types for the Type system.
Definition: Type.h:54
The memory access is dereferenceable (i.e., doesn&#39;t trap).
bool isVolatile() const
Return true if this is a cmpxchg from a volatile memory location.
Definition: Instructions.h:557
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
Target-Independent Code Generator Pass Configuration Options.
INLINEASM - Represents an inline asm block.
Definition: ISDOpcodes.h:666
Context object for machine code objects.
Definition: MCContext.h:62
Type * getType() const
All values are typed, get the type of this value.
Definition: Value.h:244
Definition: Lint.cpp:83
AtomicOrdering getSuccessOrdering() const
Returns the success ordering constraint of this cmpxchg instruction.
Definition: Instructions.h:582
Class to represent array types.
Definition: DerivedTypes.h:368
MachineInstrBuilder buildAtomicRMW(unsigned Opcode, unsigned OldValRes, unsigned Addr, unsigned Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_<Opcode> Addr, Val, MMO.
unsigned getOpcode() const
Returns a member of one of the enums like Instruction::Add.
Definition: Instruction.h:125
iterator_range< User::op_iterator > arg_operands()
Definition: InstrTypes.h:1126
auto lower_bound(R &&Range, ForwardIt I) -> decltype(adl_begin(Range))
Provide wrappers to std::lower_bound which take ranges instead of having to pass begin/end explicitly...
Definition: STLExtras.h:1281
An instruction for storing to memory.
Definition: Instructions.h:320
static LLT scalar(unsigned SizeInBits)
Get a low-level scalar or aggregate "bag of bits".
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
amdgpu Simplify well known AMD library false Value * Callee
MachineInstrBuilder buildExtractVectorElement(const DstOp &Res, const SrcOp &Val, const SrcOp &Idx)
Build and insert Res = G_EXTRACT_VECTOR_ELT Val, Idx.
Value * getOperand(unsigned i) const
Definition: User.h:169
Analysis containing CSE Info
Definition: CSEInfo.cpp:20
MachineInstrBuilder buildDbgLabel(const MDNode *Label)
Build and insert a DBG_LABEL instructions specifying that Label is given.
bool isVoidTy() const
Return true if this is &#39;void&#39;.
Definition: Type.h:140
The memory access is volatile.
bool isValidLocationForIntrinsic(const DILocation *DL) const
Check that a location is valid for this label.
const BasicBlock & getEntryBlock() const
Definition: Function.h:639
constexpr uint64_t MinAlign(uint64_t A, uint64_t B)
A and B are either alignments or offsets.
Definition: MathExtras.h:609
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:422
Abstract class that contains various methods for clients to notify about changes. ...
FPOpFusion::FPOpFusionMode AllowFPOpFusion
AllowFPOpFusion - This flag is set by the -fuse-fp-ops=xxx option.
The landingpad instruction holds all of the information necessary to generate correct exception handl...
* if(!EatIfPresent(lltok::kw_thread_local)) return false
ParseOptionalThreadLocal := /*empty.
SyncScope::ID getSyncScopeID() const
Returns the synchronization scope ID of this rmw instruction.
Definition: Instructions.h:802
unsigned const MachineRegisterInfo * MRI
Value * getCalledValue() const
Definition: InstrTypes.h:1173
LLVM Basic Block Representation.
Definition: BasicBlock.h:57
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:45
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
DISubprogram * getSubprogram() const
Get the attached subprogram.
Definition: Metadata.cpp:1507
Conditional or Unconditional Branch instruction.
MachineInstrBuilder buildInstr(unsigned Opcode)
Build and insert <empty> = Opcode <empty>.
Value * getAddress() const
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:148
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
This is an important base class in LLVM.
Definition: Constant.h:41
Value * getValue() const
MachineInstrBuilder buildPtrMask(unsigned Res, unsigned Op0, uint32_t NumBits)
Build and insert Res = G_PTR_MASK Op0, NumBits.
SmallSet - This maintains a set of unique values, optimizing for the case when the set is small (less...
Definition: SmallSet.h:134
This file contains the declarations for the subclasses of Constant, which represent the different fla...
const Instruction & front() const
Definition: BasicBlock.h:280
Indirect Branch Instruction.
MachineInstrBuilder buildIntrinsic(Intrinsic::ID ID, unsigned Res, bool HasSideEffects)
Build and insert either a G_INTRINSIC (if HasSideEffects is false) or G_INTRINSIC_W_SIDE_EFFECTS inst...
Helper class to build MachineInstr.
BasicBlock * getDefaultDest() const
DIExpression * getExpression() const
bool isValidLocationForIntrinsic(const DILocation *DL) const
Check that a location is valid for this variable.
Represent the analysis usage information of a pass.
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
Definition: InstrTypes.h:645
MachineInstrBuilder buildInsert(unsigned Res, unsigned Src, unsigned Op, unsigned Index)
Value * getPointerOperand()
Definition: Instructions.h:284
self_iterator getIterator()
Definition: ilist_node.h:81
std::pair< NoneType, bool > insert(const T &V)
insert - Insert an element into the set if it isn&#39;t already there.
Definition: SmallSet.h:180
const MachineInstrBuilder & addSym(MCSymbol *Sym, unsigned char TargetFlags=0) const
static double log2(double V)
static Constant * getAllOnesValue(Type *Ty)
Definition: Constants.cpp:318
1 1 1 1 Always true (always folded)
Definition: InstrTypes.h:662
MachineInstrBuilder buildBrIndirect(unsigned Tgt)
Build and insert G_BRINDIRECT Tgt.
MachineInstrBuilder buildCopy(const DstOp &Res, const SrcOp &Op)
Build and insert Res = COPY Op.
SyncScope::ID getSyncScopeID() const
Returns the synchronization scope ID of this cmpxchg instruction.
Definition: Instructions.h:608
BasicBlock * getSuccessor(unsigned i) const
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
const Value * getArraySize() const
Get the number of elements allocated.
Definition: Instructions.h:92
size_t size() const
Definition: SmallVector.h:52
Value * getIncomingValue(unsigned i) const
Return incoming value number x.
AtomicOrdering getOrdering() const
Returns the ordering constraint of this rmw instruction.
Definition: Instructions.h:789
Simple wrapper that does the following.
Definition: CSEInfo.h:195
This class contains a discriminated union of information about pointers in memory operands...
std::string & str()
Flushes the stream contents to the target string and returns the string&#39;s reference.
Definition: raw_ostream.h:498
INITIALIZE_PASS_END(RegBankSelect, DEBUG_TYPE, "Assign register bank of generic virtual registers", false, false) RegBankSelect
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
EVT getValueType(const DataLayout &DL, Type *Ty, bool AllowUnknown=false) const
Return the EVT corresponding to this LLVM type.
const std::string & getConstraintString() const
Definition: InlineAsm.h:81
Type * getAllocatedType() const
Return the type that is being allocated by the instruction.
Definition: Instructions.h:105
EH_LABEL - Represents a label in mid basic block used to track locations needed for debug and excepti...
Definition: ISDOpcodes.h:671
MachineInstrBuilder buildFrameIndex(unsigned Res, int Idx)
Build and insert Res = G_FRAME_INDEX Idx.
void copyIRFlags(const Instruction &I)
Copy all flags to MachineInst MIFlags.
LLT getLLTForType(Type &Ty, const DataLayout &DL)
Construct a low-level type based on an LLVM type.
The memory access writes data.
MachineInstrBuilder buildBr(MachineBasicBlock &Dest)
Build and insert G_BR Dest.
bool hasAddressTaken() const
Returns true if there are any uses of this basic block other than direct branches, switches, etc.
Definition: BasicBlock.h:391
MachineInstrBuilder buildConstDbgValue(const Constant &C, const MDNode *Variable, const MDNode *Expr)
Build and insert a DBG_VALUE instructions specifying that Variable is given by C (suitably modified b...
Value * getValOperand()
Definition: Instructions.h:815
Predicate getPredicate(unsigned Condition, unsigned Hint)
Return predicate consisting of specified condition and hint bits.
Definition: PPCPredicates.h:87
unsigned getNumOperands() const
Definition: User.h:191
MachineInstrBuilder buildMul(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)
Build and insert Res = G_MUL Op0, Op1.
void addSuccessor(MachineBasicBlock *Succ, BranchProbability Prob=BranchProbability::getUnknown())
Add Succ as a successor of this MachineBasicBlock.
MachineInstrBuilder buildICmp(CmpInst::Predicate Pred, const DstOp &Res, const SrcOp &Op0, const SrcOp &Op1)
Build and insert a Res = G_ICMP Pred, Op0, Op1.
This is the shared class of boolean and integer constants.
Definition: Constants.h:83
double Log2(double Value)
Return the log base 2 of the specified value.
Definition: MathExtras.h:527
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:839
iterator end() const
Definition: ArrayRef.h:137
bool isAggregateType() const
Return true if the type is an aggregate type.
Definition: Type.h:257
unsigned getSizeInBits() const
Returns the total size of the type. Must only be called on sized types.
static uint64_t getOffsetFromIndices(const User &U, const DataLayout &DL)
const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const
A collection of metadata nodes that might be associated with a memory access used by the alias-analys...
Definition: Metadata.h:643
MachineInstrBuilder buildBrCond(unsigned Tst, MachineBasicBlock &Dest)
Build and insert G_BRCOND Tst, Dest.
static IntegerType * getIntNTy(LLVMContext &C, unsigned N)
Definition: Type.cpp:179
static Constant * get(Type *Ty, uint64_t V, bool isSigned=false)
If Ty is a vector type, return a Constant with a splat of the given value.
Definition: Constants.cpp:621
DebugLoc getDebugLoc()
Get the current instruction&#39;s debug location.
MachineInstrBuilder buildSelect(const DstOp &Res, const SrcOp &Tst, const SrcOp &Op0, const SrcOp &Op1)
Build and insert a Res = G_SELECT Tst, Op0, Op1.
unsigned getNumIncomingValues() const
Return the number of incoming edges.
bool isLayoutSuccessor(const MachineBasicBlock *MBB) const
Return true if the specified MBB will be emitted immediately after this block, such that if this bloc...
Intrinsic::ID getIntrinsicID() const LLVM_READONLY
getIntrinsicID - This method returns the ID number of the specified function, or Intrinsic::not_intri...
Definition: Function.h:193
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
unsigned Log2_32(uint32_t Value)
Return the floor log base 2 of the specified value, -1 if the value is zero.
Definition: MathExtras.h:538
MachineInstrBuilder buildInsertVectorElement(const DstOp &Res, const SrcOp &Val, const SrcOp &Elt, const SrcOp &Idx)
Build and insert Res = G_INSERT_VECTOR_ELT Val, Elt, Idx.
unsigned getVectorNumElements() const
Definition: DerivedTypes.h:461
bool isIntPredicate() const
Definition: InstrTypes.h:738
const Module * getModule() const
Return the module owning the function this instruction belongs to or nullptr it the function does not...
Definition: Instruction.cpp:55
Class for arbitrary precision integers.
Definition: APInt.h:69
MachineInstrBuilder buildAtomicCmpXchgWithSuccess(unsigned OldValRes, unsigned SuccessRes, unsigned Addr, unsigned CmpVal, unsigned NewVal, MachineMemOperand &MMO)
Build and insert OldValRes<def>, SuccessRes<def> = G_ATOMIC_CMPXCHG_WITH_SUCCESS Addr, CmpVal, NewVal, MMO.
static MachineOperand CreateES(const char *SymName, unsigned char TargetFlags=0)
static char ID
Definition: IRTranslator.h:60
virtual bool isFMAFasterThanFMulAndFAdd(EVT) const
Return true if an FMA operation is faster than a pair of fmul and fadd instructions.
amdgpu Simplify well known AMD library false Value Value * Arg
The memory access reads data.
#define Success
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
uint64_t getTypeAllocSize(Type *Ty) const
Returns the offset in bytes between successive objects of the specified type, including alignment pad...
Definition: DataLayout.h:435
Representation of each machine instruction.
Definition: MachineInstr.h:63
Predicate getPredicate() const
Return the predicate for this instruction.
Definition: InstrTypes.h:720
This file provides various utilities for inspecting and working with the control flow graph in LLVM I...
void addObserver(GISelChangeObserver *O)
bool isVolatile() const
Return true if this is a store to a volatile memory location.
Definition: Instructions.h:353
MachineInstrBuilder buildDirectDbgValue(unsigned Reg, const MDNode *Variable, const MDNode *Expr)
Build and insert a DBG_VALUE instruction expressing the fact that the associated Variable lives in Re...
const DebugLoc & getDebugLoc() const
Return the debug location for this node as a DebugLoc.
Definition: Instruction.h:310
bool isInlineAsm() const
Check if this call is an inline asm statement.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
MachineInstrBuilder buildFCmp(CmpInst::Predicate Pred, const DstOp &Res, const SrcOp &Op0, const SrcOp &Op1)
Build and insert a Res = G_FCMP PredOp0, Op1.
uint64_t getElementOffset(unsigned Idx) const
Definition: DataLayout.h:550
void emplace_back(ArgTypes &&... Args)
Definition: SmallVector.h:644
static IntegerType * getInt32Ty(LLVMContext &C)
Definition: Type.cpp:175
void removeObserver(GISelChangeObserver *O)
LLVM_NODISCARD bool empty() const
Definition: SmallVector.h:55
AtomicOrdering getOrdering() const
Returns the ordering constraint of this store instruction.
Definition: Instructions.h:372
This represents the llvm.dbg.value instruction.
bool isTokenTy() const
Return true if this is &#39;token&#39;.
Definition: Type.h:193
CallingConv::ID getCallingConv() const
Definition: InstrTypes.h:1224
verify safepoint Safepoint IR Verifier
Value * getPointerOperand()
Definition: Instructions.h:811
TargetOptions Options
Definition: TargetMachine.h:96
const MachineBasicBlock & getMBB() const
Getter for the basic block we currently build.
BasicBlock * getIncomingBlock(unsigned i) const
Return incoming basic block number i.
Function * getCalledFunction() const
Returns the function called, or null if this is an indirect function invocation.
Definition: InstrTypes.h:1180
static cl::opt< bool > EnableCSEInIRTranslator("enable-cse-in-irtranslator", cl::desc("Should enable CSE in irtranslator"), cl::Optional, cl::init(false))
SyncScope::ID getSyncScopeID() const
Returns the synchronization scope ID of this load instruction.
Definition: Instructions.h:259
void setMBB(MachineBasicBlock &MBB)
Set the insertion point to the end of MBB.
const MachineInstrBuilder & addExternalSymbol(const char *FnName, unsigned char TargetFlags=0) const
void push_back(MachineInstr *MI)
#define I(x, y, z)
Definition: MD5.cpp:58
static Constant * getZeroValueForNegation(Type *Ty)
Floating point negation must be implemented with f(x) = -0.0 - x.
Definition: Constants.cpp:770
Pair of physical register and lane mask.
The memory access always returns the same value (or traps).
bool isZero() const
This is just a convenience method to make client code smaller for a common code.
Definition: Constants.h:192
LLVM_NODISCARD std::enable_if<!is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
Definition: Casting.h:322
uint32_t Size
Definition: Profile.cpp:46
DILocalVariable * getVariable() const
Value * getReturnValue() const
Convenience accessor. Returns null if there is no return value.
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - This function should be overriden by passes that need analysis information to do t...
bool isUnconditional() const
Optional< MachineInstrBuilder > materializeGEP(unsigned &Res, unsigned Op0, const LLT &ValueTy, uint64_t Value)
Materialize and insert Res = G_GEP Op0, (G_CONSTANT Value)
static void computeValueLLTs(const DataLayout &DL, Type &Ty, SmallVectorImpl< LLT > &ValueTys, SmallVectorImpl< uint64_t > *Offsets=nullptr, uint64_t StartingOffset=0)
AsmDialect getDialect() const
Definition: InlineAsm.h:68
Multiway switch.
This file declares the IRTranslator pass.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
A raw_ostream that writes to an std::string.
Definition: raw_ostream.h:482
aarch64 promote const
Module * getParent()
Get the module that this global value is contained inside of...
Definition: GlobalValue.h:565
LLVM Value Representation.
Definition: Value.h:72
FMA - Perform a * b + c with no intermediate rounding step.
Definition: ISDOpcodes.h:301
uint64_t getTypeStoreSize(Type *Ty) const
Returns the maximum number of bytes that may be overwritten by storing the specified type...
Definition: DataLayout.h:418
succ_range successors(Instruction *I)
Definition: CFG.h:259
This file describes how to lower LLVM calls to machine code calls.
MachineInstrBuilder buildLoad(unsigned Res, unsigned Addr, MachineMemOperand &MMO)
Build and insert Res = G_LOAD Addr, MMO.
INITIALIZE_PASS_BEGIN(IRTranslator, DEBUG_TYPE, "IRTranslator LLVM IR -> MI", false, false) INITIALIZE_PASS_END(IRTranslator
Invoke instruction.
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:58
IRTranslator LLVM IR MI
const MachineInstrBuilder & addDef(unsigned RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register definition operand.
MachineInstrBuilder buildUndef(const DstOp &Res)
Build and insert Res = IMPLICIT_DEF.
Simple wrapper observer that takes several observers, and calls each one for each event...
bool isStaticAlloca() const
Return true if this alloca is in the entry block of the function and is a constant size...
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned char TargetFlags=0) const
#define LLVM_DEBUG(X)
Definition: Debug.h:122
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:413
OutputIt copy(R &&Range, OutputIt Out)
Definition: STLExtras.h:1237
This represents the llvm.dbg.declare instruction.
Value * getPointerOperand()
Definition: Instructions.h:412
The optimization diagnostic interface.
Statically lint checks LLVM IR
Definition: Lint.cpp:192
constexpr char Args[]
Key for Kernel::Metadata::mArgs.
int64_t getIndexedOffsetInType(Type *ElemTy, ArrayRef< Value *> Indices) const
Returns the offset from the beginning of the type for the specified indices.
Definition: DataLayout.cpp:786
bool isVolatile() const
Return true if this is a RMW on a volatile memory location.
Definition: Instructions.h:774
0 0 0 0 Always false (always folded)
Definition: InstrTypes.h:647
IntegerType * Int32Ty
This file describes how to lower LLVM code to machine code.
const BasicBlock * getParent() const
Definition: Instruction.h:66
virtual const TargetRegisterClass * getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const
Returns a TargetRegisterClass used for pointer values.
an instruction to allocate memory on the stack
Definition: Instructions.h:59
This instruction inserts a struct field of array element value into an aggregate value.
gep_type_iterator gep_type_begin(const User *GEP)
size_type count(const T &V) const
count - Return 1 if the element is in the set, 0 otherwise.
Definition: SmallSet.h:164