LLVM  7.0.0svn
IRTranslator.cpp
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1 //===- llvm/CodeGen/GlobalISel/IRTranslator.cpp - IRTranslator ---*- C++ -*-==//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 /// \file
10 /// This file implements the IRTranslator class.
11 //===----------------------------------------------------------------------===//
12 
14 #include "llvm/ADT/STLExtras.h"
15 #include "llvm/ADT/ScopeExit.h"
16 #include "llvm/ADT/SmallSet.h"
17 #include "llvm/ADT/SmallVector.h"
19 #include "llvm/CodeGen/Analysis.h"
34 #include "llvm/IR/BasicBlock.h"
35 #include "llvm/IR/Constant.h"
36 #include "llvm/IR/Constants.h"
37 #include "llvm/IR/DataLayout.h"
38 #include "llvm/IR/DebugInfo.h"
39 #include "llvm/IR/DerivedTypes.h"
40 #include "llvm/IR/Function.h"
42 #include "llvm/IR/InlineAsm.h"
43 #include "llvm/IR/InstrTypes.h"
44 #include "llvm/IR/Instructions.h"
45 #include "llvm/IR/IntrinsicInst.h"
46 #include "llvm/IR/Intrinsics.h"
47 #include "llvm/IR/LLVMContext.h"
48 #include "llvm/IR/Metadata.h"
49 #include "llvm/IR/Type.h"
50 #include "llvm/IR/User.h"
51 #include "llvm/IR/Value.h"
52 #include "llvm/MC/MCContext.h"
53 #include "llvm/Pass.h"
54 #include "llvm/Support/Casting.h"
55 #include "llvm/Support/CodeGen.h"
56 #include "llvm/Support/Debug.h"
63 #include <algorithm>
64 #include <cassert>
65 #include <cstdint>
66 #include <iterator>
67 #include <string>
68 #include <utility>
69 #include <vector>
70 
71 #define DEBUG_TYPE "irtranslator"
72 
73 using namespace llvm;
74 
75 char IRTranslator::ID = 0;
76 
77 INITIALIZE_PASS_BEGIN(IRTranslator, DEBUG_TYPE, "IRTranslator LLVM IR -> MI",
78  false, false)
80 INITIALIZE_PASS_END(IRTranslator, DEBUG_TYPE, "IRTranslator LLVM IR -> MI",
81  false, false)
82 
88 
89  // Print the function name explicitly if we don't have a debug location (which
90  // makes the diagnostic less useful) or if we're going to emit a raw error.
91  if (!R.getLocation().isValid() || TPC.isGlobalISelAbortEnabled())
92  R << (" (in function: " + MF.getName() + ")").str();
93 
94  if (TPC.isGlobalISelAbortEnabled())
95  report_fatal_error(R.getMsg());
96  else
97  ORE.emit(R);
98 }
99 
102 }
103 
107 }
108 
109 unsigned IRTranslator::getOrCreateVReg(const Value &Val) {
110  unsigned &ValReg = ValToVReg[&Val];
111 
112  if (ValReg)
113  return ValReg;
114 
115  // Fill ValRegsSequence with the sequence of registers
116  // we need to concat together to produce the value.
117  assert(Val.getType()->isSized() &&
118  "Don't know how to create an empty vreg");
119  unsigned VReg =
121  ValReg = VReg;
122 
123  if (auto CV = dyn_cast<Constant>(&Val)) {
124  bool Success = translate(*CV, VReg);
125  if (!Success) {
126  OptimizationRemarkMissed R("gisel-irtranslator", "GISelFailure",
127  MF->getFunction().getSubprogram(),
128  &MF->getFunction().getEntryBlock());
129  R << "unable to translate constant: " << ore::NV("Type", Val.getType());
130  reportTranslationError(*MF, *TPC, *ORE, R);
131  return VReg;
132  }
133  }
134 
135  return VReg;
136 }
137 
138 int IRTranslator::getOrCreateFrameIndex(const AllocaInst &AI) {
139  if (FrameIndices.find(&AI) != FrameIndices.end())
140  return FrameIndices[&AI];
141 
142  unsigned ElementSize = DL->getTypeStoreSize(AI.getAllocatedType());
143  unsigned Size =
144  ElementSize * cast<ConstantInt>(AI.getArraySize())->getZExtValue();
145 
146  // Always allocate at least one byte.
147  Size = std::max(Size, 1u);
148 
149  unsigned Alignment = AI.getAlignment();
150  if (!Alignment)
151  Alignment = DL->getABITypeAlignment(AI.getAllocatedType());
152 
153  int &FI = FrameIndices[&AI];
154  FI = MF->getFrameInfo().CreateStackObject(Size, Alignment, false, &AI);
155  return FI;
156 }
157 
158 unsigned IRTranslator::getMemOpAlignment(const Instruction &I) {
159  unsigned Alignment = 0;
160  Type *ValTy = nullptr;
161  if (const StoreInst *SI = dyn_cast<StoreInst>(&I)) {
162  Alignment = SI->getAlignment();
163  ValTy = SI->getValueOperand()->getType();
164  } else if (const LoadInst *LI = dyn_cast<LoadInst>(&I)) {
165  Alignment = LI->getAlignment();
166  ValTy = LI->getType();
167  } else {
168  OptimizationRemarkMissed R("gisel-irtranslator", "", &I);
169  R << "unable to translate memop: " << ore::NV("Opcode", &I);
170  reportTranslationError(*MF, *TPC, *ORE, R);
171  return 1;
172  }
173 
174  return Alignment ? Alignment : DL->getABITypeAlignment(ValTy);
175 }
176 
177 MachineBasicBlock &IRTranslator::getMBB(const BasicBlock &BB) {
178  MachineBasicBlock *&MBB = BBToMBB[&BB];
179  assert(MBB && "BasicBlock was not encountered before");
180  return *MBB;
181 }
182 
183 void IRTranslator::addMachineCFGPred(CFGEdge Edge, MachineBasicBlock *NewPred) {
184  assert(NewPred && "new predecessor must be a real MachineBasicBlock");
185  MachinePreds[Edge].push_back(NewPred);
186 }
187 
188 bool IRTranslator::translateBinaryOp(unsigned Opcode, const User &U,
189  MachineIRBuilder &MIRBuilder) {
190  // FIXME: handle signed/unsigned wrapping flags.
191 
192  // Get or create a virtual register for each value.
193  // Unless the value is a Constant => loadimm cst?
194  // or inline constant each time?
195  // Creation of a virtual register needs to have a size.
196  unsigned Op0 = getOrCreateVReg(*U.getOperand(0));
197  unsigned Op1 = getOrCreateVReg(*U.getOperand(1));
198  unsigned Res = getOrCreateVReg(U);
199  MIRBuilder.buildInstr(Opcode).addDef(Res).addUse(Op0).addUse(Op1);
200  return true;
201 }
202 
203 bool IRTranslator::translateFSub(const User &U, MachineIRBuilder &MIRBuilder) {
204  // -0.0 - X --> G_FNEG
205  if (isa<Constant>(U.getOperand(0)) &&
207  MIRBuilder.buildInstr(TargetOpcode::G_FNEG)
208  .addDef(getOrCreateVReg(U))
209  .addUse(getOrCreateVReg(*U.getOperand(1)));
210  return true;
211  }
212  return translateBinaryOp(TargetOpcode::G_FSUB, U, MIRBuilder);
213 }
214 
215 bool IRTranslator::translateCompare(const User &U,
216  MachineIRBuilder &MIRBuilder) {
217  const CmpInst *CI = dyn_cast<CmpInst>(&U);
218  unsigned Op0 = getOrCreateVReg(*U.getOperand(0));
219  unsigned Op1 = getOrCreateVReg(*U.getOperand(1));
220  unsigned Res = getOrCreateVReg(U);
221  CmpInst::Predicate Pred =
222  CI ? CI->getPredicate() : static_cast<CmpInst::Predicate>(
223  cast<ConstantExpr>(U).getPredicate());
224  if (CmpInst::isIntPredicate(Pred))
225  MIRBuilder.buildICmp(Pred, Res, Op0, Op1);
226  else if (Pred == CmpInst::FCMP_FALSE)
227  MIRBuilder.buildCopy(
228  Res, getOrCreateVReg(*Constant::getNullValue(CI->getType())));
229  else if (Pred == CmpInst::FCMP_TRUE)
230  MIRBuilder.buildCopy(
231  Res, getOrCreateVReg(*Constant::getAllOnesValue(CI->getType())));
232  else
233  MIRBuilder.buildFCmp(Pred, Res, Op0, Op1);
234 
235  return true;
236 }
237 
238 bool IRTranslator::translateRet(const User &U, MachineIRBuilder &MIRBuilder) {
239  const ReturnInst &RI = cast<ReturnInst>(U);
240  const Value *Ret = RI.getReturnValue();
241  if (Ret && DL->getTypeStoreSize(Ret->getType()) == 0)
242  Ret = nullptr;
243  // The target may mess up with the insertion point, but
244  // this is not important as a return is the last instruction
245  // of the block anyway.
246  return CLI->lowerReturn(MIRBuilder, Ret, !Ret ? 0 : getOrCreateVReg(*Ret));
247 }
248 
249 bool IRTranslator::translateBr(const User &U, MachineIRBuilder &MIRBuilder) {
250  const BranchInst &BrInst = cast<BranchInst>(U);
251  unsigned Succ = 0;
252  if (!BrInst.isUnconditional()) {
253  // We want a G_BRCOND to the true BB followed by an unconditional branch.
254  unsigned Tst = getOrCreateVReg(*BrInst.getCondition());
255  const BasicBlock &TrueTgt = *cast<BasicBlock>(BrInst.getSuccessor(Succ++));
256  MachineBasicBlock &TrueBB = getMBB(TrueTgt);
257  MIRBuilder.buildBrCond(Tst, TrueBB);
258  }
259 
260  const BasicBlock &BrTgt = *cast<BasicBlock>(BrInst.getSuccessor(Succ));
261  MachineBasicBlock &TgtBB = getMBB(BrTgt);
262  MachineBasicBlock &CurBB = MIRBuilder.getMBB();
263 
264  // If the unconditional target is the layout successor, fallthrough.
265  if (!CurBB.isLayoutSuccessor(&TgtBB))
266  MIRBuilder.buildBr(TgtBB);
267 
268  // Link successors.
269  for (const BasicBlock *Succ : BrInst.successors())
270  CurBB.addSuccessor(&getMBB(*Succ));
271  return true;
272 }
273 
274 bool IRTranslator::translateSwitch(const User &U,
275  MachineIRBuilder &MIRBuilder) {
276  // For now, just translate as a chain of conditional branches.
277  // FIXME: could we share most of the logic/code in
278  // SelectionDAGBuilder::visitSwitch between SelectionDAG and GlobalISel?
279  // At first sight, it seems most of the logic in there is independent of
280  // SelectionDAG-specifics and a lot of work went in to optimize switch
281  // lowering in there.
282 
283  const SwitchInst &SwInst = cast<SwitchInst>(U);
284  const unsigned SwCondValue = getOrCreateVReg(*SwInst.getCondition());
285  const BasicBlock *OrigBB = SwInst.getParent();
286 
287  LLT LLTi1 = getLLTForType(*Type::getInt1Ty(U.getContext()), *DL);
288  for (auto &CaseIt : SwInst.cases()) {
289  const unsigned CaseValueReg = getOrCreateVReg(*CaseIt.getCaseValue());
290  const unsigned Tst = MRI->createGenericVirtualRegister(LLTi1);
291  MIRBuilder.buildICmp(CmpInst::ICMP_EQ, Tst, CaseValueReg, SwCondValue);
292  MachineBasicBlock &CurMBB = MIRBuilder.getMBB();
293  const BasicBlock *TrueBB = CaseIt.getCaseSuccessor();
294  MachineBasicBlock &TrueMBB = getMBB(*TrueBB);
295 
296  MIRBuilder.buildBrCond(Tst, TrueMBB);
297  CurMBB.addSuccessor(&TrueMBB);
298  addMachineCFGPred({OrigBB, TrueBB}, &CurMBB);
299 
300  MachineBasicBlock *FalseMBB =
301  MF->CreateMachineBasicBlock(SwInst.getParent());
302  // Insert the comparison blocks one after the other.
303  MF->insert(std::next(CurMBB.getIterator()), FalseMBB);
304  MIRBuilder.buildBr(*FalseMBB);
305  CurMBB.addSuccessor(FalseMBB);
306 
307  MIRBuilder.setMBB(*FalseMBB);
308  }
309  // handle default case
310  const BasicBlock *DefaultBB = SwInst.getDefaultDest();
311  MachineBasicBlock &DefaultMBB = getMBB(*DefaultBB);
312  MIRBuilder.buildBr(DefaultMBB);
313  MachineBasicBlock &CurMBB = MIRBuilder.getMBB();
314  CurMBB.addSuccessor(&DefaultMBB);
315  addMachineCFGPred({OrigBB, DefaultBB}, &CurMBB);
316 
317  return true;
318 }
319 
320 bool IRTranslator::translateIndirectBr(const User &U,
321  MachineIRBuilder &MIRBuilder) {
322  const IndirectBrInst &BrInst = cast<IndirectBrInst>(U);
323 
324  const unsigned Tgt = getOrCreateVReg(*BrInst.getAddress());
325  MIRBuilder.buildBrIndirect(Tgt);
326 
327  // Link successors.
328  MachineBasicBlock &CurBB = MIRBuilder.getMBB();
329  for (const BasicBlock *Succ : BrInst.successors())
330  CurBB.addSuccessor(&getMBB(*Succ));
331 
332  return true;
333 }
334 
335 bool IRTranslator::translateLoad(const User &U, MachineIRBuilder &MIRBuilder) {
336  const LoadInst &LI = cast<LoadInst>(U);
337 
338  auto Flags = LI.isVolatile() ? MachineMemOperand::MOVolatile
340  Flags |= MachineMemOperand::MOLoad;
341 
342  if (DL->getTypeStoreSize(LI.getType()) == 0)
343  return true;
344 
345  unsigned Res = getOrCreateVReg(LI);
346  unsigned Addr = getOrCreateVReg(*LI.getPointerOperand());
347 
348  MIRBuilder.buildLoad(
349  Res, Addr,
351  Flags, DL->getTypeStoreSize(LI.getType()),
352  getMemOpAlignment(LI), AAMDNodes(), nullptr,
353  LI.getSyncScopeID(), LI.getOrdering()));
354  return true;
355 }
356 
357 bool IRTranslator::translateStore(const User &U, MachineIRBuilder &MIRBuilder) {
358  const StoreInst &SI = cast<StoreInst>(U);
359  auto Flags = SI.isVolatile() ? MachineMemOperand::MOVolatile
362 
363  if (DL->getTypeStoreSize(SI.getValueOperand()->getType()) == 0)
364  return true;
365 
366  unsigned Val = getOrCreateVReg(*SI.getValueOperand());
367  unsigned Addr = getOrCreateVReg(*SI.getPointerOperand());
368 
369  MIRBuilder.buildStore(
370  Val, Addr,
374  getMemOpAlignment(SI), AAMDNodes(), nullptr, SI.getSyncScopeID(),
375  SI.getOrdering()));
376  return true;
377 }
378 
379 bool IRTranslator::translateExtractValue(const User &U,
380  MachineIRBuilder &MIRBuilder) {
381  const Value *Src = U.getOperand(0);
383  SmallVector<Value *, 1> Indices;
384 
385  // If Src is a single element ConstantStruct, translate extractvalue
386  // to that element to avoid inserting a cast instruction.
387  if (auto CS = dyn_cast<ConstantStruct>(Src))
388  if (CS->getNumOperands() == 1) {
389  unsigned Res = getOrCreateVReg(*CS->getOperand(0));
390  ValToVReg[&U] = Res;
391  return true;
392  }
393 
394  // getIndexedOffsetInType is designed for GEPs, so the first index is the
395  // usual array element rather than looking into the actual aggregate.
396  Indices.push_back(ConstantInt::get(Int32Ty, 0));
397 
398  if (const ExtractValueInst *EVI = dyn_cast<ExtractValueInst>(&U)) {
399  for (auto Idx : EVI->indices())
400  Indices.push_back(ConstantInt::get(Int32Ty, Idx));
401  } else {
402  for (unsigned i = 1; i < U.getNumOperands(); ++i)
403  Indices.push_back(U.getOperand(i));
404  }
405 
406  uint64_t Offset = 8 * DL->getIndexedOffsetInType(Src->getType(), Indices);
407 
408  unsigned Res = getOrCreateVReg(U);
409  MIRBuilder.buildExtract(Res, getOrCreateVReg(*Src), Offset);
410 
411  return true;
412 }
413 
414 bool IRTranslator::translateInsertValue(const User &U,
415  MachineIRBuilder &MIRBuilder) {
416  const Value *Src = U.getOperand(0);
418  SmallVector<Value *, 1> Indices;
419 
420  // getIndexedOffsetInType is designed for GEPs, so the first index is the
421  // usual array element rather than looking into the actual aggregate.
422  Indices.push_back(ConstantInt::get(Int32Ty, 0));
423 
424  if (const InsertValueInst *IVI = dyn_cast<InsertValueInst>(&U)) {
425  for (auto Idx : IVI->indices())
426  Indices.push_back(ConstantInt::get(Int32Ty, Idx));
427  } else {
428  for (unsigned i = 2; i < U.getNumOperands(); ++i)
429  Indices.push_back(U.getOperand(i));
430  }
431 
432  uint64_t Offset = 8 * DL->getIndexedOffsetInType(Src->getType(), Indices);
433 
434  unsigned Res = getOrCreateVReg(U);
435  unsigned Inserted = getOrCreateVReg(*U.getOperand(1));
436  MIRBuilder.buildInsert(Res, getOrCreateVReg(*Src), Inserted, Offset);
437 
438  return true;
439 }
440 
441 bool IRTranslator::translateSelect(const User &U,
442  MachineIRBuilder &MIRBuilder) {
443  unsigned Res = getOrCreateVReg(U);
444  unsigned Tst = getOrCreateVReg(*U.getOperand(0));
445  unsigned Op0 = getOrCreateVReg(*U.getOperand(1));
446  unsigned Op1 = getOrCreateVReg(*U.getOperand(2));
447  MIRBuilder.buildSelect(Res, Tst, Op0, Op1);
448  return true;
449 }
450 
451 bool IRTranslator::translateBitCast(const User &U,
452  MachineIRBuilder &MIRBuilder) {
453  // If we're bitcasting to the source type, we can reuse the source vreg.
454  if (getLLTForType(*U.getOperand(0)->getType(), *DL) ==
455  getLLTForType(*U.getType(), *DL)) {
456  // Get the source vreg now, to avoid invalidating ValToVReg.
457  unsigned SrcReg = getOrCreateVReg(*U.getOperand(0));
458  unsigned &Reg = ValToVReg[&U];
459  // If we already assigned a vreg for this bitcast, we can't change that.
460  // Emit a copy to satisfy the users we already emitted.
461  if (Reg)
462  MIRBuilder.buildCopy(Reg, SrcReg);
463  else
464  Reg = SrcReg;
465  return true;
466  }
467  return translateCast(TargetOpcode::G_BITCAST, U, MIRBuilder);
468 }
469 
470 bool IRTranslator::translateCast(unsigned Opcode, const User &U,
471  MachineIRBuilder &MIRBuilder) {
472  unsigned Op = getOrCreateVReg(*U.getOperand(0));
473  unsigned Res = getOrCreateVReg(U);
474  MIRBuilder.buildInstr(Opcode).addDef(Res).addUse(Op);
475  return true;
476 }
477 
478 bool IRTranslator::translateGetElementPtr(const User &U,
479  MachineIRBuilder &MIRBuilder) {
480  // FIXME: support vector GEPs.
481  if (U.getType()->isVectorTy())
482  return false;
483 
484  Value &Op0 = *U.getOperand(0);
485  unsigned BaseReg = getOrCreateVReg(Op0);
486  Type *PtrIRTy = Op0.getType();
487  LLT PtrTy = getLLTForType(*PtrIRTy, *DL);
488  Type *OffsetIRTy = DL->getIntPtrType(PtrIRTy);
489  LLT OffsetTy = getLLTForType(*OffsetIRTy, *DL);
490 
491  int64_t Offset = 0;
492  for (gep_type_iterator GTI = gep_type_begin(&U), E = gep_type_end(&U);
493  GTI != E; ++GTI) {
494  const Value *Idx = GTI.getOperand();
495  if (StructType *StTy = GTI.getStructTypeOrNull()) {
496  unsigned Field = cast<Constant>(Idx)->getUniqueInteger().getZExtValue();
497  Offset += DL->getStructLayout(StTy)->getElementOffset(Field);
498  continue;
499  } else {
500  uint64_t ElementSize = DL->getTypeAllocSize(GTI.getIndexedType());
501 
502  // If this is a scalar constant or a splat vector of constants,
503  // handle it quickly.
504  if (const auto *CI = dyn_cast<ConstantInt>(Idx)) {
505  Offset += ElementSize * CI->getSExtValue();
506  continue;
507  }
508 
509  if (Offset != 0) {
510  unsigned NewBaseReg = MRI->createGenericVirtualRegister(PtrTy);
511  unsigned OffsetReg =
512  getOrCreateVReg(*ConstantInt::get(OffsetIRTy, Offset));
513  MIRBuilder.buildGEP(NewBaseReg, BaseReg, OffsetReg);
514 
515  BaseReg = NewBaseReg;
516  Offset = 0;
517  }
518 
519  unsigned IdxReg = getOrCreateVReg(*Idx);
520  if (MRI->getType(IdxReg) != OffsetTy) {
521  unsigned NewIdxReg = MRI->createGenericVirtualRegister(OffsetTy);
522  MIRBuilder.buildSExtOrTrunc(NewIdxReg, IdxReg);
523  IdxReg = NewIdxReg;
524  }
525 
526  // N = N + Idx * ElementSize;
527  // Avoid doing it for ElementSize of 1.
528  unsigned GepOffsetReg;
529  if (ElementSize != 1) {
530  unsigned ElementSizeReg =
531  getOrCreateVReg(*ConstantInt::get(OffsetIRTy, ElementSize));
532 
533  GepOffsetReg = MRI->createGenericVirtualRegister(OffsetTy);
534  MIRBuilder.buildMul(GepOffsetReg, ElementSizeReg, IdxReg);
535  } else
536  GepOffsetReg = IdxReg;
537 
538  unsigned NewBaseReg = MRI->createGenericVirtualRegister(PtrTy);
539  MIRBuilder.buildGEP(NewBaseReg, BaseReg, GepOffsetReg);
540  BaseReg = NewBaseReg;
541  }
542  }
543 
544  if (Offset != 0) {
545  unsigned OffsetReg = getOrCreateVReg(*ConstantInt::get(OffsetIRTy, Offset));
546  MIRBuilder.buildGEP(getOrCreateVReg(U), BaseReg, OffsetReg);
547  return true;
548  }
549 
550  MIRBuilder.buildCopy(getOrCreateVReg(U), BaseReg);
551  return true;
552 }
553 
554 bool IRTranslator::translateMemfunc(const CallInst &CI,
555  MachineIRBuilder &MIRBuilder,
556  unsigned ID) {
557  LLT SizeTy = getLLTForType(*CI.getArgOperand(2)->getType(), *DL);
558  Type *DstTy = CI.getArgOperand(0)->getType();
559  if (cast<PointerType>(DstTy)->getAddressSpace() != 0 ||
560  SizeTy.getSizeInBits() != DL->getPointerSizeInBits(0))
561  return false;
562 
564  for (int i = 0; i < 3; ++i) {
565  const auto &Arg = CI.getArgOperand(i);
566  Args.emplace_back(getOrCreateVReg(*Arg), Arg->getType());
567  }
568 
569  const char *Callee;
570  switch (ID) {
571  case Intrinsic::memmove:
572  case Intrinsic::memcpy: {
573  Type *SrcTy = CI.getArgOperand(1)->getType();
574  if(cast<PointerType>(SrcTy)->getAddressSpace() != 0)
575  return false;
576  Callee = ID == Intrinsic::memcpy ? "memcpy" : "memmove";
577  break;
578  }
579  case Intrinsic::memset:
580  Callee = "memset";
581  break;
582  default:
583  return false;
584  }
585 
586  return CLI->lowerCall(MIRBuilder, CI.getCallingConv(),
587  MachineOperand::CreateES(Callee),
588  CallLowering::ArgInfo(0, CI.getType()), Args);
589 }
590 
591 void IRTranslator::getStackGuard(unsigned DstReg,
592  MachineIRBuilder &MIRBuilder) {
593  const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
594  MRI->setRegClass(DstReg, TRI->getPointerRegClass(*MF));
595  auto MIB = MIRBuilder.buildInstr(TargetOpcode::LOAD_STACK_GUARD);
596  MIB.addDef(DstReg);
597 
598  auto &TLI = *MF->getSubtarget().getTargetLowering();
599  Value *Global = TLI.getSDagStackGuard(*MF->getFunction().getParent());
600  if (!Global)
601  return;
602 
603  MachinePointerInfo MPInfo(Global);
607  *MemRefs =
608  MF->getMachineMemOperand(MPInfo, Flags, DL->getPointerSizeInBits() / 8,
609  DL->getPointerABIAlignment(0));
610  MIB.setMemRefs(MemRefs, MemRefs + 1);
611 }
612 
613 bool IRTranslator::translateOverflowIntrinsic(const CallInst &CI, unsigned Op,
614  MachineIRBuilder &MIRBuilder) {
615  LLT Ty = getLLTForType(*CI.getOperand(0)->getType(), *DL);
616  LLT s1 = LLT::scalar(1);
617  unsigned Width = Ty.getSizeInBits();
618  unsigned Res = MRI->createGenericVirtualRegister(Ty);
619  unsigned Overflow = MRI->createGenericVirtualRegister(s1);
620  auto MIB = MIRBuilder.buildInstr(Op)
621  .addDef(Res)
622  .addDef(Overflow)
623  .addUse(getOrCreateVReg(*CI.getOperand(0)))
624  .addUse(getOrCreateVReg(*CI.getOperand(1)));
625 
626  if (Op == TargetOpcode::G_UADDE || Op == TargetOpcode::G_USUBE) {
627  unsigned Zero = getOrCreateVReg(
629  MIB.addUse(Zero);
630  }
631 
632  MIRBuilder.buildSequence(getOrCreateVReg(CI), {Res, Overflow}, {0, Width});
633  return true;
634 }
635 
636 bool IRTranslator::translateKnownIntrinsic(const CallInst &CI, Intrinsic::ID ID,
637  MachineIRBuilder &MIRBuilder) {
638  switch (ID) {
639  default:
640  break;
641  case Intrinsic::lifetime_start:
642  case Intrinsic::lifetime_end:
643  // Stack coloring is not enabled in O0 (which we care about now) so we can
644  // drop these. Make sure someone notices when we start compiling at higher
645  // opts though.
646  if (MF->getTarget().getOptLevel() != CodeGenOpt::None)
647  return false;
648  return true;
649  case Intrinsic::dbg_declare: {
650  const DbgDeclareInst &DI = cast<DbgDeclareInst>(CI);
651  assert(DI.getVariable() && "Missing variable");
652 
653  const Value *Address = DI.getAddress();
654  if (!Address || isa<UndefValue>(Address)) {
655  DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
656  return true;
657  }
658 
660  MIRBuilder.getDebugLoc()) &&
661  "Expected inlined-at fields to agree");
662  auto AI = dyn_cast<AllocaInst>(Address);
663  if (AI && AI->isStaticAlloca()) {
664  // Static allocas are tracked at the MF level, no need for DBG_VALUE
665  // instructions (in fact, they get ignored if they *do* exist).
667  getOrCreateFrameIndex(*AI), DI.getDebugLoc());
668  } else
669  MIRBuilder.buildDirectDbgValue(getOrCreateVReg(*Address),
670  DI.getVariable(), DI.getExpression());
671  return true;
672  }
673  case Intrinsic::vaend:
674  // No target I know of cares about va_end. Certainly no in-tree target
675  // does. Simplest intrinsic ever!
676  return true;
677  case Intrinsic::vastart: {
678  auto &TLI = *MF->getSubtarget().getTargetLowering();
679  Value *Ptr = CI.getArgOperand(0);
680  unsigned ListSize = TLI.getVaListSizeInBits(*DL) / 8;
681 
682  MIRBuilder.buildInstr(TargetOpcode::G_VASTART)
683  .addUse(getOrCreateVReg(*Ptr))
685  MachinePointerInfo(Ptr), MachineMemOperand::MOStore, ListSize, 0));
686  return true;
687  }
688  case Intrinsic::dbg_value: {
689  // This form of DBG_VALUE is target-independent.
690  const DbgValueInst &DI = cast<DbgValueInst>(CI);
691  const Value *V = DI.getValue();
693  MIRBuilder.getDebugLoc()) &&
694  "Expected inlined-at fields to agree");
695  if (!V) {
696  // Currently the optimizer can produce this; insert an undef to
697  // help debugging. Probably the optimizer should not do this.
698  MIRBuilder.buildIndirectDbgValue(0, DI.getVariable(), DI.getExpression());
699  } else if (const auto *CI = dyn_cast<Constant>(V)) {
700  MIRBuilder.buildConstDbgValue(*CI, DI.getVariable(), DI.getExpression());
701  } else {
702  unsigned Reg = getOrCreateVReg(*V);
703  // FIXME: This does not handle register-indirect values at offset 0. The
704  // direct/indirect thing shouldn't really be handled by something as
705  // implicit as reg+noreg vs reg+imm in the first palce, but it seems
706  // pretty baked in right now.
707  MIRBuilder.buildDirectDbgValue(Reg, DI.getVariable(), DI.getExpression());
708  }
709  return true;
710  }
711  case Intrinsic::uadd_with_overflow:
712  return translateOverflowIntrinsic(CI, TargetOpcode::G_UADDE, MIRBuilder);
713  case Intrinsic::sadd_with_overflow:
714  return translateOverflowIntrinsic(CI, TargetOpcode::G_SADDO, MIRBuilder);
715  case Intrinsic::usub_with_overflow:
716  return translateOverflowIntrinsic(CI, TargetOpcode::G_USUBE, MIRBuilder);
717  case Intrinsic::ssub_with_overflow:
718  return translateOverflowIntrinsic(CI, TargetOpcode::G_SSUBO, MIRBuilder);
719  case Intrinsic::umul_with_overflow:
720  return translateOverflowIntrinsic(CI, TargetOpcode::G_UMULO, MIRBuilder);
721  case Intrinsic::smul_with_overflow:
722  return translateOverflowIntrinsic(CI, TargetOpcode::G_SMULO, MIRBuilder);
723  case Intrinsic::pow:
724  MIRBuilder.buildInstr(TargetOpcode::G_FPOW)
725  .addDef(getOrCreateVReg(CI))
726  .addUse(getOrCreateVReg(*CI.getArgOperand(0)))
727  .addUse(getOrCreateVReg(*CI.getArgOperand(1)));
728  return true;
729  case Intrinsic::exp:
730  MIRBuilder.buildInstr(TargetOpcode::G_FEXP)
731  .addDef(getOrCreateVReg(CI))
732  .addUse(getOrCreateVReg(*CI.getArgOperand(0)));
733  return true;
734  case Intrinsic::exp2:
735  MIRBuilder.buildInstr(TargetOpcode::G_FEXP2)
736  .addDef(getOrCreateVReg(CI))
737  .addUse(getOrCreateVReg(*CI.getArgOperand(0)));
738  return true;
739  case Intrinsic::log:
740  MIRBuilder.buildInstr(TargetOpcode::G_FLOG)
741  .addDef(getOrCreateVReg(CI))
742  .addUse(getOrCreateVReg(*CI.getArgOperand(0)));
743  return true;
744  case Intrinsic::log2:
745  MIRBuilder.buildInstr(TargetOpcode::G_FLOG2)
746  .addDef(getOrCreateVReg(CI))
747  .addUse(getOrCreateVReg(*CI.getArgOperand(0)));
748  return true;
749  case Intrinsic::fma:
750  MIRBuilder.buildInstr(TargetOpcode::G_FMA)
751  .addDef(getOrCreateVReg(CI))
752  .addUse(getOrCreateVReg(*CI.getArgOperand(0)))
753  .addUse(getOrCreateVReg(*CI.getArgOperand(1)))
754  .addUse(getOrCreateVReg(*CI.getArgOperand(2)));
755  return true;
756  case Intrinsic::memcpy:
757  case Intrinsic::memmove:
758  case Intrinsic::memset:
759  return translateMemfunc(CI, MIRBuilder, ID);
760  case Intrinsic::eh_typeid_for: {
762  unsigned Reg = getOrCreateVReg(CI);
763  unsigned TypeID = MF->getTypeIDFor(GV);
764  MIRBuilder.buildConstant(Reg, TypeID);
765  return true;
766  }
767  case Intrinsic::objectsize: {
768  // If we don't know by now, we're never going to know.
769  const ConstantInt *Min = cast<ConstantInt>(CI.getArgOperand(1));
770 
771  MIRBuilder.buildConstant(getOrCreateVReg(CI), Min->isZero() ? -1ULL : 0);
772  return true;
773  }
774  case Intrinsic::stackguard:
775  getStackGuard(getOrCreateVReg(CI), MIRBuilder);
776  return true;
777  case Intrinsic::stackprotector: {
778  LLT PtrTy = getLLTForType(*CI.getArgOperand(0)->getType(), *DL);
779  unsigned GuardVal = MRI->createGenericVirtualRegister(PtrTy);
780  getStackGuard(GuardVal, MIRBuilder);
781 
782  AllocaInst *Slot = cast<AllocaInst>(CI.getArgOperand(1));
783  MIRBuilder.buildStore(
784  GuardVal, getOrCreateVReg(*Slot),
787  getOrCreateFrameIndex(*Slot)),
789  PtrTy.getSizeInBits() / 8, 8));
790  return true;
791  }
792  }
793  return false;
794 }
795 
796 bool IRTranslator::translateInlineAsm(const CallInst &CI,
797  MachineIRBuilder &MIRBuilder) {
798  const InlineAsm &IA = cast<InlineAsm>(*CI.getCalledValue());
799  if (!IA.getConstraintString().empty())
800  return false;
801 
802  unsigned ExtraInfo = 0;
803  if (IA.hasSideEffects())
804  ExtraInfo |= InlineAsm::Extra_HasSideEffects;
805  if (IA.getDialect() == InlineAsm::AD_Intel)
806  ExtraInfo |= InlineAsm::Extra_AsmDialect;
807 
809  .addExternalSymbol(IA.getAsmString().c_str())
810  .addImm(ExtraInfo);
811 
812  return true;
813 }
814 
815 bool IRTranslator::translateCall(const User &U, MachineIRBuilder &MIRBuilder) {
816  const CallInst &CI = cast<CallInst>(U);
817  auto TII = MF->getTarget().getIntrinsicInfo();
818  const Function *F = CI.getCalledFunction();
819 
820  if (CI.isInlineAsm())
821  return translateInlineAsm(CI, MIRBuilder);
822 
824  if (F && F->isIntrinsic()) {
825  ID = F->getIntrinsicID();
826  if (TII && ID == Intrinsic::not_intrinsic)
827  ID = static_cast<Intrinsic::ID>(TII->getIntrinsicID(F));
828  }
829 
830  if (!F || !F->isIntrinsic() || ID == Intrinsic::not_intrinsic) {
831  unsigned Res = CI.getType()->isVoidTy() ? 0 : getOrCreateVReg(CI);
833  for (auto &Arg: CI.arg_operands())
834  Args.push_back(getOrCreateVReg(*Arg));
835 
836  MF->getFrameInfo().setHasCalls(true);
837  return CLI->lowerCall(MIRBuilder, &CI, Res, Args, [&]() {
838  return getOrCreateVReg(*CI.getCalledValue());
839  });
840  }
841 
842  assert(ID != Intrinsic::not_intrinsic && "unknown intrinsic");
843 
844  if (translateKnownIntrinsic(CI, ID, MIRBuilder))
845  return true;
846 
847  unsigned Res = CI.getType()->isVoidTy() ? 0 : getOrCreateVReg(CI);
848  MachineInstrBuilder MIB =
849  MIRBuilder.buildIntrinsic(ID, Res, !CI.doesNotAccessMemory());
850 
851  for (auto &Arg : CI.arg_operands()) {
852  // Some intrinsics take metadata parameters. Reject them.
853  if (isa<MetadataAsValue>(Arg))
854  return false;
855  MIB.addUse(getOrCreateVReg(*Arg));
856  }
857 
858  // Add a MachineMemOperand if it is a target mem intrinsic.
859  const TargetLowering &TLI = *MF->getSubtarget().getTargetLowering();
861  // TODO: Add a GlobalISel version of getTgtMemIntrinsic.
862  if (TLI.getTgtMemIntrinsic(Info, CI, *MF, ID)) {
863  uint64_t Size = Info.memVT.getStoreSize();
865  Info.flags, Size, Info.align));
866  }
867 
868  return true;
869 }
870 
871 bool IRTranslator::translateInvoke(const User &U,
872  MachineIRBuilder &MIRBuilder) {
873  const InvokeInst &I = cast<InvokeInst>(U);
874  MCContext &Context = MF->getContext();
875 
876  const BasicBlock *ReturnBB = I.getSuccessor(0);
877  const BasicBlock *EHPadBB = I.getSuccessor(1);
878 
879  const Value *Callee = I.getCalledValue();
880  const Function *Fn = dyn_cast<Function>(Callee);
881  if (isa<InlineAsm>(Callee))
882  return false;
883 
884  // FIXME: support invoking patchpoint and statepoint intrinsics.
885  if (Fn && Fn->isIntrinsic())
886  return false;
887 
888  // FIXME: support whatever these are.
890  return false;
891 
892  // FIXME: support Windows exception handling.
893  if (!isa<LandingPadInst>(EHPadBB->front()))
894  return false;
895 
896  // Emit the actual call, bracketed by EH_LABELs so that the MF knows about
897  // the region covered by the try.
898  MCSymbol *BeginSymbol = Context.createTempSymbol();
899  MIRBuilder.buildInstr(TargetOpcode::EH_LABEL).addSym(BeginSymbol);
900 
901  unsigned Res = I.getType()->isVoidTy() ? 0 : getOrCreateVReg(I);
903  for (auto &Arg: I.arg_operands())
904  Args.push_back(getOrCreateVReg(*Arg));
905 
906  if (!CLI->lowerCall(MIRBuilder, &I, Res, Args,
907  [&]() { return getOrCreateVReg(*I.getCalledValue()); }))
908  return false;
909 
910  MCSymbol *EndSymbol = Context.createTempSymbol();
911  MIRBuilder.buildInstr(TargetOpcode::EH_LABEL).addSym(EndSymbol);
912 
913  // FIXME: track probabilities.
914  MachineBasicBlock &EHPadMBB = getMBB(*EHPadBB),
915  &ReturnMBB = getMBB(*ReturnBB);
916  MF->addInvoke(&EHPadMBB, BeginSymbol, EndSymbol);
917  MIRBuilder.getMBB().addSuccessor(&ReturnMBB);
918  MIRBuilder.getMBB().addSuccessor(&EHPadMBB);
919  MIRBuilder.buildBr(ReturnMBB);
920 
921  return true;
922 }
923 
924 bool IRTranslator::translateLandingPad(const User &U,
925  MachineIRBuilder &MIRBuilder) {
926  const LandingPadInst &LP = cast<LandingPadInst>(U);
927 
928  MachineBasicBlock &MBB = MIRBuilder.getMBB();
929  addLandingPadInfo(LP, MBB);
930 
931  MBB.setIsEHPad();
932 
933  // If there aren't registers to copy the values into (e.g., during SjLj
934  // exceptions), then don't bother.
935  auto &TLI = *MF->getSubtarget().getTargetLowering();
936  const Constant *PersonalityFn = MF->getFunction().getPersonalityFn();
937  if (TLI.getExceptionPointerRegister(PersonalityFn) == 0 &&
938  TLI.getExceptionSelectorRegister(PersonalityFn) == 0)
939  return true;
940 
941  // If landingpad's return type is token type, we don't create DAG nodes
942  // for its exception pointer and selector value. The extraction of exception
943  // pointer or selector value from token type landingpads is not currently
944  // supported.
945  if (LP.getType()->isTokenTy())
946  return true;
947 
948  // Add a label to mark the beginning of the landing pad. Deletion of the
949  // landing pad can thus be detected via the MachineModuleInfo.
951  .addSym(MF->addLandingPad(&MBB));
952 
953  LLT Ty = getLLTForType(*LP.getType(), *DL);
954  unsigned Undef = MRI->createGenericVirtualRegister(Ty);
955  MIRBuilder.buildUndef(Undef);
956 
958  for (Type *Ty : cast<StructType>(LP.getType())->elements())
959  Tys.push_back(getLLTForType(*Ty, *DL));
960  assert(Tys.size() == 2 && "Only two-valued landingpads are supported");
961 
962  // Mark exception register as live in.
963  unsigned ExceptionReg = TLI.getExceptionPointerRegister(PersonalityFn);
964  if (!ExceptionReg)
965  return false;
966 
967  MBB.addLiveIn(ExceptionReg);
968  unsigned VReg = MRI->createGenericVirtualRegister(Tys[0]),
969  Tmp = MRI->createGenericVirtualRegister(Ty);
970  MIRBuilder.buildCopy(VReg, ExceptionReg);
971  MIRBuilder.buildInsert(Tmp, Undef, VReg, 0);
972 
973  unsigned SelectorReg = TLI.getExceptionSelectorRegister(PersonalityFn);
974  if (!SelectorReg)
975  return false;
976 
977  MBB.addLiveIn(SelectorReg);
978 
979  // N.b. the exception selector register always has pointer type and may not
980  // match the actual IR-level type in the landingpad so an extra cast is
981  // needed.
982  unsigned PtrVReg = MRI->createGenericVirtualRegister(Tys[0]);
983  MIRBuilder.buildCopy(PtrVReg, SelectorReg);
984 
985  VReg = MRI->createGenericVirtualRegister(Tys[1]);
986  MIRBuilder.buildInstr(TargetOpcode::G_PTRTOINT).addDef(VReg).addUse(PtrVReg);
987  MIRBuilder.buildInsert(getOrCreateVReg(LP), Tmp, VReg,
988  Tys[0].getSizeInBits());
989  return true;
990 }
991 
992 bool IRTranslator::translateAlloca(const User &U,
993  MachineIRBuilder &MIRBuilder) {
994  auto &AI = cast<AllocaInst>(U);
995 
996  if (AI.isStaticAlloca()) {
997  unsigned Res = getOrCreateVReg(AI);
998  int FI = getOrCreateFrameIndex(AI);
999  MIRBuilder.buildFrameIndex(Res, FI);
1000  return true;
1001  }
1002 
1003  // Now we're in the harder dynamic case.
1004  Type *Ty = AI.getAllocatedType();
1005  unsigned Align =
1006  std::max((unsigned)DL->getPrefTypeAlignment(Ty), AI.getAlignment());
1007 
1008  unsigned NumElts = getOrCreateVReg(*AI.getArraySize());
1009 
1010  Type *IntPtrIRTy = DL->getIntPtrType(AI.getType());
1011  LLT IntPtrTy = getLLTForType(*IntPtrIRTy, *DL);
1012  if (MRI->getType(NumElts) != IntPtrTy) {
1013  unsigned ExtElts = MRI->createGenericVirtualRegister(IntPtrTy);
1014  MIRBuilder.buildZExtOrTrunc(ExtElts, NumElts);
1015  NumElts = ExtElts;
1016  }
1017 
1018  unsigned AllocSize = MRI->createGenericVirtualRegister(IntPtrTy);
1019  unsigned TySize =
1020  getOrCreateVReg(*ConstantInt::get(IntPtrIRTy, -DL->getTypeAllocSize(Ty)));
1021  MIRBuilder.buildMul(AllocSize, NumElts, TySize);
1022 
1023  LLT PtrTy = getLLTForType(*AI.getType(), *DL);
1024  auto &TLI = *MF->getSubtarget().getTargetLowering();
1025  unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
1026 
1027  unsigned SPTmp = MRI->createGenericVirtualRegister(PtrTy);
1028  MIRBuilder.buildCopy(SPTmp, SPReg);
1029 
1030  unsigned AllocTmp = MRI->createGenericVirtualRegister(PtrTy);
1031  MIRBuilder.buildGEP(AllocTmp, SPTmp, AllocSize);
1032 
1033  // Handle alignment. We have to realign if the allocation granule was smaller
1034  // than stack alignment, or the specific alloca requires more than stack
1035  // alignment.
1036  unsigned StackAlign =
1038  Align = std::max(Align, StackAlign);
1039  if (Align > StackAlign || DL->getTypeAllocSize(Ty) % StackAlign != 0) {
1040  // Round the size of the allocation up to the stack alignment size
1041  // by add SA-1 to the size. This doesn't overflow because we're computing
1042  // an address inside an alloca.
1043  unsigned AlignedAlloc = MRI->createGenericVirtualRegister(PtrTy);
1044  MIRBuilder.buildPtrMask(AlignedAlloc, AllocTmp, Log2_32(Align));
1045  AllocTmp = AlignedAlloc;
1046  }
1047 
1048  MIRBuilder.buildCopy(SPReg, AllocTmp);
1049  MIRBuilder.buildCopy(getOrCreateVReg(AI), AllocTmp);
1050 
1051  MF->getFrameInfo().CreateVariableSizedObject(Align ? Align : 1, &AI);
1053  return true;
1054 }
1055 
1056 bool IRTranslator::translateVAArg(const User &U, MachineIRBuilder &MIRBuilder) {
1057  // FIXME: We may need more info about the type. Because of how LLT works,
1058  // we're completely discarding the i64/double distinction here (amongst
1059  // others). Fortunately the ABIs I know of where that matters don't use va_arg
1060  // anyway but that's not guaranteed.
1061  MIRBuilder.buildInstr(TargetOpcode::G_VAARG)
1062  .addDef(getOrCreateVReg(U))
1063  .addUse(getOrCreateVReg(*U.getOperand(0)))
1064  .addImm(DL->getABITypeAlignment(U.getType()));
1065  return true;
1066 }
1067 
1068 bool IRTranslator::translateInsertElement(const User &U,
1069  MachineIRBuilder &MIRBuilder) {
1070  // If it is a <1 x Ty> vector, use the scalar as it is
1071  // not a legal vector type in LLT.
1072  if (U.getType()->getVectorNumElements() == 1) {
1073  unsigned Elt = getOrCreateVReg(*U.getOperand(1));
1074  ValToVReg[&U] = Elt;
1075  return true;
1076  }
1077  unsigned Res = getOrCreateVReg(U);
1078  unsigned Val = getOrCreateVReg(*U.getOperand(0));
1079  unsigned Elt = getOrCreateVReg(*U.getOperand(1));
1080  unsigned Idx = getOrCreateVReg(*U.getOperand(2));
1081  MIRBuilder.buildInsertVectorElement(Res, Val, Elt, Idx);
1082  return true;
1083 }
1084 
1085 bool IRTranslator::translateExtractElement(const User &U,
1086  MachineIRBuilder &MIRBuilder) {
1087  // If it is a <1 x Ty> vector, use the scalar as it is
1088  // not a legal vector type in LLT.
1089  if (U.getOperand(0)->getType()->getVectorNumElements() == 1) {
1090  unsigned Elt = getOrCreateVReg(*U.getOperand(0));
1091  ValToVReg[&U] = Elt;
1092  return true;
1093  }
1094  unsigned Res = getOrCreateVReg(U);
1095  unsigned Val = getOrCreateVReg(*U.getOperand(0));
1096  unsigned Idx = getOrCreateVReg(*U.getOperand(1));
1097  MIRBuilder.buildExtractVectorElement(Res, Val, Idx);
1098  return true;
1099 }
1100 
1101 bool IRTranslator::translateShuffleVector(const User &U,
1102  MachineIRBuilder &MIRBuilder) {
1103  MIRBuilder.buildInstr(TargetOpcode::G_SHUFFLE_VECTOR)
1104  .addDef(getOrCreateVReg(U))
1105  .addUse(getOrCreateVReg(*U.getOperand(0)))
1106  .addUse(getOrCreateVReg(*U.getOperand(1)))
1107  .addUse(getOrCreateVReg(*U.getOperand(2)));
1108  return true;
1109 }
1110 
1111 bool IRTranslator::translatePHI(const User &U, MachineIRBuilder &MIRBuilder) {
1112  const PHINode &PI = cast<PHINode>(U);
1113  auto MIB = MIRBuilder.buildInstr(TargetOpcode::G_PHI);
1114  MIB.addDef(getOrCreateVReg(PI));
1115 
1116  PendingPHIs.emplace_back(&PI, MIB.getInstr());
1117  return true;
1118 }
1119 
1120 void IRTranslator::finishPendingPhis() {
1121  for (std::pair<const PHINode *, MachineInstr *> &Phi : PendingPHIs) {
1122  const PHINode *PI = Phi.first;
1123  MachineInstrBuilder MIB(*MF, Phi.second);
1124 
1125  // All MachineBasicBlocks exist, add them to the PHI. We assume IRTranslator
1126  // won't create extra control flow here, otherwise we need to find the
1127  // dominating predecessor here (or perhaps force the weirder IRTranslators
1128  // to provide a simple boundary).
1129  SmallSet<const BasicBlock *, 4> HandledPreds;
1130 
1131  for (unsigned i = 0; i < PI->getNumIncomingValues(); ++i) {
1132  auto IRPred = PI->getIncomingBlock(i);
1133  if (HandledPreds.count(IRPred))
1134  continue;
1135 
1136  HandledPreds.insert(IRPred);
1137  unsigned ValReg = getOrCreateVReg(*PI->getIncomingValue(i));
1138  for (auto Pred : getMachinePredBBs({IRPred, PI->getParent()})) {
1139  assert(Pred->isSuccessor(MIB->getParent()) &&
1140  "incorrect CFG at MachineBasicBlock level");
1141  MIB.addUse(ValReg);
1142  MIB.addMBB(Pred);
1143  }
1144  }
1145  }
1146 }
1147 
1148 bool IRTranslator::translate(const Instruction &Inst) {
1149  CurBuilder.setDebugLoc(Inst.getDebugLoc());
1150  switch(Inst.getOpcode()) {
1151 #define HANDLE_INST(NUM, OPCODE, CLASS) \
1152  case Instruction::OPCODE: return translate##OPCODE(Inst, CurBuilder);
1153 #include "llvm/IR/Instruction.def"
1154  default:
1155  return false;
1156  }
1157 }
1158 
1159 bool IRTranslator::translate(const Constant &C, unsigned Reg) {
1160  if (auto CI = dyn_cast<ConstantInt>(&C))
1161  EntryBuilder.buildConstant(Reg, *CI);
1162  else if (auto CF = dyn_cast<ConstantFP>(&C))
1163  EntryBuilder.buildFConstant(Reg, *CF);
1164  else if (isa<UndefValue>(C))
1165  EntryBuilder.buildUndef(Reg);
1166  else if (isa<ConstantPointerNull>(C))
1167  EntryBuilder.buildConstant(Reg, 0);
1168  else if (auto GV = dyn_cast<GlobalValue>(&C))
1169  EntryBuilder.buildGlobalValue(Reg, GV);
1170  else if (auto CAZ = dyn_cast<ConstantAggregateZero>(&C)) {
1171  if (!CAZ->getType()->isVectorTy())
1172  return false;
1173  // Return the scalar if it is a <1 x Ty> vector.
1174  if (CAZ->getNumElements() == 1)
1175  return translate(*CAZ->getElementValue(0u), Reg);
1176  std::vector<unsigned> Ops;
1177  for (unsigned i = 0; i < CAZ->getNumElements(); ++i) {
1178  Constant &Elt = *CAZ->getElementValue(i);
1179  Ops.push_back(getOrCreateVReg(Elt));
1180  }
1181  EntryBuilder.buildMerge(Reg, Ops);
1182  } else if (auto CV = dyn_cast<ConstantDataVector>(&C)) {
1183  // Return the scalar if it is a <1 x Ty> vector.
1184  if (CV->getNumElements() == 1)
1185  return translate(*CV->getElementAsConstant(0), Reg);
1186  std::vector<unsigned> Ops;
1187  for (unsigned i = 0; i < CV->getNumElements(); ++i) {
1188  Constant &Elt = *CV->getElementAsConstant(i);
1189  Ops.push_back(getOrCreateVReg(Elt));
1190  }
1191  EntryBuilder.buildMerge(Reg, Ops);
1192  } else if (auto CE = dyn_cast<ConstantExpr>(&C)) {
1193  switch(CE->getOpcode()) {
1194 #define HANDLE_INST(NUM, OPCODE, CLASS) \
1195  case Instruction::OPCODE: return translate##OPCODE(*CE, EntryBuilder);
1196 #include "llvm/IR/Instruction.def"
1197  default:
1198  return false;
1199  }
1200  } else if (auto CS = dyn_cast<ConstantStruct>(&C)) {
1201  // Return the element if it is a single element ConstantStruct.
1202  if (CS->getNumOperands() == 1) {
1203  unsigned EltReg = getOrCreateVReg(*CS->getOperand(0));
1204  EntryBuilder.buildCast(Reg, EltReg);
1205  return true;
1206  }
1208  SmallVector<uint64_t, 4> Indices;
1209  uint64_t Offset = 0;
1210  for (unsigned i = 0; i < CS->getNumOperands(); ++i) {
1211  unsigned OpReg = getOrCreateVReg(*CS->getOperand(i));
1212  Ops.push_back(OpReg);
1213  Indices.push_back(Offset);
1214  Offset += MRI->getType(OpReg).getSizeInBits();
1215  }
1216  EntryBuilder.buildSequence(Reg, Ops, Indices);
1217  } else if (auto CV = dyn_cast<ConstantVector>(&C)) {
1218  if (CV->getNumOperands() == 1)
1219  return translate(*CV->getOperand(0), Reg);
1221  for (unsigned i = 0; i < CV->getNumOperands(); ++i) {
1222  Ops.push_back(getOrCreateVReg(*CV->getOperand(i)));
1223  }
1224  EntryBuilder.buildMerge(Reg, Ops);
1225  } else
1226  return false;
1227 
1228  return true;
1229 }
1230 
1231 void IRTranslator::finalizeFunction() {
1232  // Release the memory used by the different maps we
1233  // needed during the translation.
1234  PendingPHIs.clear();
1235  ValToVReg.clear();
1236  FrameIndices.clear();
1237  MachinePreds.clear();
1238  // MachineIRBuilder::DebugLoc can outlive the DILocation it holds. Clear it
1239  // to avoid accessing free’d memory (in runOnMachineFunction) and to avoid
1240  // destroying it twice (in ~IRTranslator() and ~LLVMContext())
1241  EntryBuilder = MachineIRBuilder();
1242  CurBuilder = MachineIRBuilder();
1243 }
1244 
1246  MF = &CurMF;
1247  const Function &F = MF->getFunction();
1248  if (F.empty())
1249  return false;
1250  CLI = MF->getSubtarget().getCallLowering();
1251  CurBuilder.setMF(*MF);
1252  EntryBuilder.setMF(*MF);
1253  MRI = &MF->getRegInfo();
1254  DL = &F.getParent()->getDataLayout();
1255  TPC = &getAnalysis<TargetPassConfig>();
1256  ORE = llvm::make_unique<OptimizationRemarkEmitter>(&F);
1257 
1258  assert(PendingPHIs.empty() && "stale PHIs");
1259 
1260  if (!DL->isLittleEndian()) {
1261  // Currently we don't properly handle big endian code.
1262  OptimizationRemarkMissed R("gisel-irtranslator", "GISelFailure",
1263  F.getSubprogram(), &F.getEntryBlock());
1264  R << "unable to translate in big endian mode";
1265  reportTranslationError(*MF, *TPC, *ORE, R);
1266  }
1267 
1268  // Release the per-function state when we return, whether we succeeded or not.
1269  auto FinalizeOnReturn = make_scope_exit([this]() { finalizeFunction(); });
1270 
1271  // Setup a separate basic-block for the arguments and constants
1272  MachineBasicBlock *EntryBB = MF->CreateMachineBasicBlock();
1273  MF->push_back(EntryBB);
1274  EntryBuilder.setMBB(*EntryBB);
1275 
1276  // Create all blocks, in IR order, to preserve the layout.
1277  for (const BasicBlock &BB: F) {
1278  auto *&MBB = BBToMBB[&BB];
1279 
1280  MBB = MF->CreateMachineBasicBlock(&BB);
1281  MF->push_back(MBB);
1282 
1283  if (BB.hasAddressTaken())
1284  MBB->setHasAddressTaken();
1285  }
1286 
1287  // Make our arguments/constants entry block fallthrough to the IR entry block.
1288  EntryBB->addSuccessor(&getMBB(F.front()));
1289 
1290  // Lower the actual args into this basic block.
1291  SmallVector<unsigned, 8> VRegArgs;
1292  for (const Argument &Arg: F.args()) {
1293  if (DL->getTypeStoreSize(Arg.getType()) == 0)
1294  continue; // Don't handle zero sized types.
1295  VRegArgs.push_back(getOrCreateVReg(Arg));
1296  }
1297  if (!CLI->lowerFormalArguments(EntryBuilder, F, VRegArgs)) {
1298  OptimizationRemarkMissed R("gisel-irtranslator", "GISelFailure",
1299  F.getSubprogram(), &F.getEntryBlock());
1300  R << "unable to lower arguments: " << ore::NV("Prototype", F.getType());
1301  reportTranslationError(*MF, *TPC, *ORE, R);
1302  return false;
1303  }
1304 
1305  // And translate the function!
1306  for (const BasicBlock &BB: F) {
1307  MachineBasicBlock &MBB = getMBB(BB);
1308  // Set the insertion point of all the following translations to
1309  // the end of this basic block.
1310  CurBuilder.setMBB(MBB);
1311 
1312  for (const Instruction &Inst: BB) {
1313  if (translate(Inst))
1314  continue;
1315 
1316  OptimizationRemarkMissed R("gisel-irtranslator", "GISelFailure",
1317  Inst.getDebugLoc(), &BB);
1318  R << "unable to translate instruction: " << ore::NV("Opcode", &Inst);
1319 
1320  if (ORE->allowExtraAnalysis("gisel-irtranslator")) {
1321  std::string InstStrStorage;
1322  raw_string_ostream InstStr(InstStrStorage);
1323  InstStr << Inst;
1324 
1325  R << ": '" << InstStr.str() << "'";
1326  }
1327 
1328  reportTranslationError(*MF, *TPC, *ORE, R);
1329  return false;
1330  }
1331  }
1332 
1333  finishPendingPhis();
1334 
1335  // Merge the argument lowering and constants block with its single
1336  // successor, the LLVM-IR entry block. We want the basic block to
1337  // be maximal.
1338  assert(EntryBB->succ_size() == 1 &&
1339  "Custom BB used for lowering should have only one successor");
1340  // Get the successor of the current entry block.
1341  MachineBasicBlock &NewEntryBB = **EntryBB->succ_begin();
1342  assert(NewEntryBB.pred_size() == 1 &&
1343  "LLVM-IR entry block has a predecessor!?");
1344  // Move all the instruction from the current entry block to the
1345  // new entry block.
1346  NewEntryBB.splice(NewEntryBB.begin(), EntryBB, EntryBB->begin(),
1347  EntryBB->end());
1348 
1349  // Update the live-in information for the new entry block.
1350  for (const MachineBasicBlock::RegisterMaskPair &LiveIn : EntryBB->liveins())
1351  NewEntryBB.addLiveIn(LiveIn);
1352  NewEntryBB.sortUniqueLiveIns();
1353 
1354  // Get rid of the now empty basic block.
1355  EntryBB->removeSuccessor(&NewEntryBB);
1356  MF->remove(EntryBB);
1357  MF->DeleteMachineBasicBlock(EntryBB);
1358 
1359  assert(&MF->front() == &NewEntryBB &&
1360  "New entry wasn't next in the list of basic block!");
1361 
1362  return false;
1363 }
MachineBasicBlock & getMBB()
Getter for the basic block we currently build.
uint64_t CallInst * C
void initializeIRTranslatorPass(PassRegistry &)
Return a value (possibly void), from a function.
Value * getValueOperand()
Definition: Instructions.h:395
bool isIntrinsic() const
isIntrinsic - Returns true if the function&#39;s name starts with "llvm.".
Definition: Function.h:180
void push_back(const T &Elt)
Definition: SmallVector.h:212
constexpr char Align[]
Key for Kernel::Arg::Metadata::mAlign.
This class is the base class for the comparison instructions.
Definition: InstrTypes.h:843
bool empty() const
Definition: Function.h:640
static IntegerType * getInt1Ty(LLVMContext &C)
Definition: Type.cpp:173
void setVariableDbgInfo(const DILocalVariable *Var, const DIExpression *Expr, unsigned Slot, const DILocation *Loc)
Collect information used to emit debugging information of a variable.
Diagnostic information for missed-optimization remarks.
This instruction extracts a struct member or array element value from an aggregate value...
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
iterator_range< CaseIt > cases()
Iteration adapter for range-for loops.
GCNRegPressure max(const GCNRegPressure &P1, const GCNRegPressure &P2)
This class represents an incoming formal argument to a Function.
Definition: Argument.h:30
LLVMContext & Context
MachineInstrBuilder buildGEP(unsigned Res, unsigned Op0, unsigned Op1)
Build and insert Res = G_GEP Op0, Op1.
DiagnosticInfoOptimizationBase::Argument NV
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:115
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
MachineInstrBuilder buildIndirectDbgValue(unsigned Reg, const MDNode *Variable, const MDNode *Expr)
Build and insert a DBG_VALUE instruction expressing the fact that the associated Variable lives in me...
unsigned countOperandBundlesOfType(StringRef Name) const
Return the number of operand bundles with the tag Name attached to this instruction.
Definition: InstrTypes.h:1339
MCSymbol * addLandingPad(MachineBasicBlock *LandingPad)
Add a new panding pad. Returns the label ID for the landing pad entry.
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:42
MachineInstrBuilder buildZExtOrTrunc(unsigned Res, unsigned Op)
Build and insert Res = G_ZEXT Op, Res = G_TRUNC Op, or Res = COPY Op depending on the differing sizes...
bool isSized(SmallPtrSetImpl< Type *> *Visited=nullptr) const
Return true if it makes sense to take the size of this type.
Definition: Type.h:262
LLVM_ATTRIBUTE_ALWAYS_INLINE size_type size() const
Definition: SmallVector.h:136
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
void addLandingPadInfo(const LandingPadInst &I, MachineBasicBlock &MBB)
Extract the exception handling information from the landingpad instruction and add them to the specif...
const StructLayout * getStructLayout(StructType *Ty) const
Returns a StructLayout object, indicating the alignment of the struct, its size, and the offsets of i...
Definition: DataLayout.cpp:562
IRTranslator LLVM IR static false void reportTranslationError(MachineFunction &MF, const TargetPassConfig &TPC, OptimizationRemarkEmitter &ORE, OptimizationRemarkMissed &R)
This class represents a function call, abstracting a target machine&#39;s calling convention.
This file contains the declarations for metadata subclasses.
Value * getCondition() const
virtual const TargetLowering * getTargetLowering() const
void setDebugLoc(const DebugLoc &DL)
Set the debug location to DL for all the next build instructions.
SyncScope::ID getSyncScopeID() const
Returns the synchronization scope ID of this store instruction.
Definition: Instructions.h:370
gep_type_iterator gep_type_end(const User *GEP)
const std::string & getAsmString() const
Definition: InlineAsm.h:81
AtomicOrdering getOrdering() const
Returns the ordering constraint of this load instruction.
Definition: Instructions.h:233
LLVM_NODISCARD detail::scope_exit< typename std::decay< Callable >::type > make_scope_exit(Callable &&F)
Definition: ScopeExit.h:47
LLVMContext & getContext() const
All values hold a context through their type.
Definition: Value.cpp:738
iterator_range< op_iterator > arg_operands()
Iteration adapter for range-for loops.
BasicBlock * getSuccessor(unsigned i) const
unsigned getPointerSizeInBits(unsigned AS=0) const
Layout pointer size, in bits FIXME: The defaults need to be removed once all of the backends/clients ...
Definition: DataLayout.h:344
F(f)
An instruction for reading from memory.
Definition: Instructions.h:164
Value * getCondition() const
bool isVectorTy() const
True if this is an instance of VectorType.
Definition: Type.h:227
unsigned getTypeIDFor(const GlobalValue *TI)
Return the type id for the specified typeinfo. This is function wide.
unsigned createGenericVirtualRegister(LLT Ty)
Create and return a new generic virtual register with low-level type Ty.
MachineInstrBuilder buildExtract(unsigned Res, unsigned Src, uint64_t Index)
Build and insert `Res0, ...
GlobalValue * ExtractTypeInfo(Value *V)
ExtractTypeInfo - Returns the type info, possibly bitcast, encoded in V.
Definition: Analysis.cpp:118
CallingConv::ID getCallingConv() const
getCallingConv/setCallingConv - Get or set the calling convention of this function call...
void DeleteMachineBasicBlock(MachineBasicBlock *MBB)
DeleteMachineBasicBlock - Delete the given MachineBasicBlock.
unsigned getPointerABIAlignment(unsigned AS) const
Layout pointer alignment.
Definition: DataLayout.cpp:587
virtual bool getTgtMemIntrinsic(IntrinsicInfo &, const CallInst &, MachineFunction &, unsigned) const
Given an intrinsic, checks if on the target the intrinsic will need to map to a MemIntrinsicNode (tou...
MachineInstrBuilder buildSelect(unsigned Res, unsigned Tst, unsigned Op0, unsigned Op1)
Build and insert a Res = G_SELECT Tst, Op0, Op1.
int CreateStackObject(uint64_t Size, unsigned Alignment, bool isSpillSlot, const AllocaInst *Alloca=nullptr, uint8_t ID=0)
Create a new statically sized stack object, returning a nonnegative identifier to represent it...
MachineInstrBuilder buildFCmp(CmpInst::Predicate Pred, unsigned Res, unsigned Op0, unsigned Op1)
Build and insert a Res = G_FCMP PredOp0, Op1.
bool runOnMachineFunction(MachineFunction &MF) override
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
static Constant * getNullValue(Type *Ty)
Constructor to create a &#39;0&#39; constant of arbitrary type.
Definition: Constants.cpp:206
bool hasSideEffects() const
Definition: InlineAsm.h:67
MachineInstrBuilder buildStore(unsigned Val, unsigned Addr, MachineMemOperand &MMO)
Build and insert G_STORE Val, Addr, MMO.
AnalysisUsage & addRequired()
#define INITIALIZE_PASS_DEPENDENCY(depName)
Definition: PassSupport.h:51
bool isVolatile() const
Return true if this is a load from a volatile memory location.
Definition: Instructions.h:217
A description of a memory reference used in the backend.
const DataLayout & getDataLayout() const
Get the data layout for the module&#39;s target platform.
Definition: Module.cpp:361
#define DEBUG_TYPE
virtual bool lowerFormalArguments(MachineIRBuilder &MIRBuilder, const Function &F, ArrayRef< unsigned > VRegs) const
This hook must be implemented to lower the incoming (formal) arguments, described by Args...
Definition: CallLowering.h:159
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
const HexagonInstrInfo * TII
unsigned getAlignment() const
Return the alignment of the memory that is being allocated by the instruction.
Definition: Instructions.h:109
PointerType * getType() const
Overload to return most specific pointer type.
Definition: Instructions.h:97
Class to represent struct types.
Definition: DerivedTypes.h:201
const TargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
const MachineInstrBuilder & addUse(unsigned RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register use operand.
MachineInstrBuilder buildFConstant(unsigned Res, const ConstantFP &Val)
Build and insert Res = G_FCONSTANT Val.
Reg
All possible values of the reg field in the ModR/M byte.
TypeID
Definitions of all of the base types for the Type system.
Definition: Type.h:55
unsigned getStoreSize() const
Return the number of bytes overwritten by a store of the specified value type.
Definition: ValueTypes.h:304
The memory access is dereferenceable (i.e., doesn&#39;t trap).
MachineInstrBuilder buildExtractVectorElement(unsigned Res, unsigned Val, unsigned Idx)
Build and insert Res = G_EXTRACT_VECTOR_ELT Val, Idx.
bool hasVarSizedObjects() const
This method may be called any time after instruction selection is complete to determine if the stack ...
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, uint64_t s, unsigned base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
Target-Independent Code Generator Pass Configuration Options.
INLINEASM - Represents an inline asm block.
Definition: ISDOpcodes.h:635
MachineInstrBuilder buildInsertVectorElement(unsigned Res, unsigned Val, unsigned Elt, unsigned Idx)
Build and insert Res = G_INSERT_VECTOR_ELT Val, Elt, Idx.
Context object for machine code objects.
Definition: MCContext.h:60
Type * getType() const
All values are typed, get the type of this value.
Definition: Value.h:245
bool isLittleEndian() const
Layout endianness...
Definition: DataLayout.h:216
unsigned getOpcode() const
Returns a member of one of the enums like Instruction::Add.
Definition: Instruction.h:126
An instruction for storing to memory.
Definition: Instructions.h:306
static LLT scalar(unsigned SizeInBits)
Get a low-level scalar or aggregate "bag of bits".
amdgpu Simplify well known AMD library false Value * Callee
MachineBasicBlock * CreateMachineBasicBlock(const BasicBlock *bb=nullptr)
CreateMachineBasicBlock - Allocate a new MachineBasicBlock.
Value * getOperand(unsigned i) const
Definition: User.h:154
MCContext & getContext() const
bool isVoidTy() const
Return true if this is &#39;void&#39;.
Definition: Type.h:141
The memory access is volatile.
const BasicBlock & getEntryBlock() const
Definition: Function.h:618
IntegerType * getIntPtrType(LLVMContext &C, unsigned AddressSpace=0) const
Returns an integer type with size at least as big as that of a pointer in the given address space...
Definition: DataLayout.cpp:702
succ_range successors()
Definition: InstrTypes.h:267
MachineInstrBuilder buildBr(MachineBasicBlock &BB)
Build and insert G_BR Dest.
The landingpad instruction holds all of the information necessary to generate correct exception handl...
const Value * getCalledValue() const
Get a pointer to the function that is invoked by this instruction.
CodeGenOpt::Level getOptLevel() const
Returns the optimization level: None, Less, Default, or Aggressive.
LLVM Basic Block Representation.
Definition: BasicBlock.h:59
void addInvoke(MachineBasicBlock *LandingPad, MCSymbol *BeginLabel, MCSymbol *EndLabel)
Provide the begin and end labels of an invoke style call and associate it with a try landing pad bloc...
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:46
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
virtual bool lowerCall(MachineIRBuilder &MIRBuilder, CallingConv::ID CallConv, const MachineOperand &Callee, const ArgInfo &OrigRet, ArrayRef< ArgInfo > OrigArgs) const
This hook must be implemented to lower the given call instruction, including argument and return valu...
Definition: CallLowering.h:185
DISubprogram * getSubprogram() const
Get the attached subprogram.
Definition: Metadata.cpp:1497
Conditional or Unconditional Branch instruction.
MachineInstrBuilder buildInstr(unsigned Opcode)
Build and insert <empty> = Opcode <empty>.
Value * getAddress() const
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
This is an important base class in LLVM.
Definition: Constant.h:42
Value * getValue() const
MachineInstrBuilder buildPtrMask(unsigned Res, unsigned Op0, uint32_t NumBits)
Build and insert Res = G_PTR_MASK Op0, NumBits.
SmallSet - This maintains a set of unique values, optimizing for the case when the set is small (less...
Definition: SmallSet.h:36
This file contains the declarations for the subclasses of Constant, which represent the different fla...
const Instruction & front() const
Definition: BasicBlock.h:264
Indirect Branch Instruction.
MachineInstrBuilder buildIntrinsic(Intrinsic::ID ID, unsigned Res, bool HasSideEffects)
Build and insert either a G_INTRINSIC (if HasSideEffects is false) or G_INTRINSIC_W_SIDE_EFFECTS inst...
Helper class to build MachineInstr.
BasicBlock * getDefaultDest() const
unsigned getPrefTypeAlignment(Type *Ty) const
Returns the preferred stack/global alignment for the specified type.
Definition: DataLayout.cpp:692
bool isValidLocationForIntrinsic(const DILocation *DL) const
Check that a location is valid for this variable.
Represent the analysis usage information of a pass.
DILocalVariable * getVariable() const
Definition: IntrinsicInst.h:80
MachineInstrBuilder buildICmp(CmpInst::Predicate Pred, unsigned Res, unsigned Op0, unsigned Op1)
Build and insert a Res = G_ICMP Pred, Op0, Op1.
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
Definition: InstrTypes.h:853
MachineInstrBuilder buildInsert(unsigned Res, unsigned Src, unsigned Op, unsigned Index)
virtual const CallLowering * getCallLowering() const
DIExpression * getExpression() const
Definition: IntrinsicInst.h:84
Value * getPointerOperand()
Definition: Instructions.h:270
void remove(iterator MBBI)
self_iterator getIterator()
Definition: ilist_node.h:82
std::pair< NoneType, bool > insert(const T &V)
insert - Insert an element into the set if it isn&#39;t already there.
Definition: SmallSet.h:81
const MachineInstrBuilder & addSym(MCSymbol *Sym, unsigned char TargetFlags=0) const
void setMF(MachineFunction &)
static double log2(double V)
static Constant * getAllOnesValue(Type *Ty)
Get the all ones value.
Definition: Constants.cpp:260
1 1 1 1 Always true (always folded)
Definition: InstrTypes.h:870
MachineInstrBuilder buildBrIndirect(unsigned Tgt)
Build and insert G_BRINDIRECT Tgt.
MachineInstrBuilder buildSExtOrTrunc(unsigned Res, unsigned Op)
Build and insert Res = G_SEXT Op, Res = G_TRUNC Op, or Res = COPY Op depending on the differing sizes...
BasicBlock * getSuccessor(unsigned i) const
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
const MachineBasicBlock & front() const
const Value * getArraySize() const
Get the number of elements allocated.
Definition: Instructions.h:93
Value * getIncomingValue(unsigned i) const
Return incoming value number x.
This class contains a discriminated union of information about pointers in memory operands...
unsigned getStackAlignment() const
getStackAlignment - This method returns the number of bytes to which the stack pointer must be aligne...
std::string & str()
Flushes the stream contents to the target string and returns the string&#39;s reference.
Definition: raw_ostream.h:478
INITIALIZE_PASS_END(RegBankSelect, DEBUG_TYPE, "Assign register bank of generic virtual registers", false, false) RegBankSelect
const std::string & getConstraintString() const
Definition: InlineAsm.h:82
Type * getAllocatedType() const
Return the type that is being allocated by the instruction.
Definition: Instructions.h:102
EH_LABEL - Represents a label in mid basic block used to track locations needed for debug and excepti...
Definition: ISDOpcodes.h:640
MachineInstrBuilder buildFrameIndex(unsigned Res, int Idx)
Build and insert Res = G_FRAME_INDEX Idx.
LLT getLLTForType(Type &Ty, const DataLayout &DL)
Construct a low-level type based on an LLVM type.
The memory access writes data.
bool hasAddressTaken() const
Returns true if there are any uses of this basic block other than direct branches, switches, etc.
Definition: BasicBlock.h:376
MachineInstrBuilder buildConstDbgValue(const Constant &C, const MDNode *Variable, const MDNode *Expr)
Build and insert a DBG_VALUE instructions specifying that Variable is given by C (suitably modified b...
Predicate getPredicate(unsigned Condition, unsigned Hint)
Return predicate consisting of specified condition and hint bits.
Definition: PPCPredicates.h:85
unsigned getNumOperands() const
Definition: User.h:176
void addSuccessor(MachineBasicBlock *Succ, BranchProbability Prob=BranchProbability::getUnknown())
Add Succ as a successor of this MachineBasicBlock.
This is the shared class of boolean and integer constants.
Definition: Constants.h:84
void buildSequence(unsigned Res, ArrayRef< unsigned > Ops, ArrayRef< uint64_t > Indices)
Build and insert instructions to put Ops together at the specified p Indices to form a larger registe...
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:862
MachineInstrBuilder buildCopy(unsigned Res, unsigned Op)
Build and insert Res = COPY Op.
unsigned getABITypeAlignment(Type *Ty) const
Returns the minimum ABI-required alignment for the specified type.
Definition: DataLayout.cpp:682
unsigned getSizeInBits() const
Returns the total size of the type. Must only be called on sized types.
const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const
A collection of metadata nodes that might be associated with a memory access used by the alias-analys...
Definition: Metadata.h:642
static Constant * get(Type *Ty, uint64_t V, bool isSigned=false)
If Ty is a vector type, return a Constant with a splat of the given value.
Definition: Constants.cpp:559
DebugLoc getDebugLoc()
Get the current instruction&#39;s debug location.
unsigned getNumIncomingValues() const
Return the number of incoming edges.
bool isLayoutSuccessor(const MachineBasicBlock *MBB) const
Return true if the specified MBB will be emitted immediately after this block, such that if this bloc...
Intrinsic::ID getIntrinsicID() const LLVM_READONLY
getIntrinsicID - This method returns the ID number of the specified function, or Intrinsic::not_intri...
Definition: Function.h:175
const Function & getFunction() const
Return the LLVM function that this machine code represents.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
unsigned Log2_32(uint32_t Value)
Return the floor log base 2 of the specified value, -1 if the value is zero.
Definition: MathExtras.h:531
unsigned getVectorNumElements() const
Definition: DerivedTypes.h:462
bool isIntPredicate() const
Definition: InstrTypes.h:945
static MachineOperand CreateES(const char *SymName, unsigned char TargetFlags=0)
static char ID
Definition: IRTranslator.h:60
amdgpu Simplify well known AMD library false Value Value * Arg
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:142
The memory access reads data.
#define Success
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
uint64_t getTypeAllocSize(Type *Ty) const
Returns the offset in bytes between successive objects of the specified type, including alignment pad...
Definition: DataLayout.h:403
Function * getCalledFunction() const
Return the function called, or null if this is an indirect function invocation.
Predicate getPredicate() const
Return the predicate for this instruction.
Definition: InstrTypes.h:927
MachineInstrBuilder buildUndef(unsigned Dst)
Build and insert Res = IMPLICIT_DEF.
bool isVolatile() const
Return true if this is a store to a volatile memory location.
Definition: Instructions.h:339
MachineInstrBuilder buildDirectDbgValue(unsigned Reg, const MDNode *Variable, const MDNode *Expr)
Build and insert a DBG_VALUE instruction expressing the fact that the associated Variable lives in Re...
const DebugLoc & getDebugLoc() const
Return the debug location for this node as a DebugLoc.
Definition: Instruction.h:285
bool isInlineAsm() const
Check if this call is an inline asm statement.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
uint64_t getElementOffset(unsigned Idx) const
Definition: DataLayout.h:513
void emplace_back(ArgTypes &&... Args)
Definition: SmallVector.h:654
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
static IntegerType * getInt32Ty(LLVMContext &C)
Definition: Type.cpp:176
AtomicOrdering getOrdering() const
Returns the ordering constraint of this store instruction.
Definition: Instructions.h:358
This represents the llvm.dbg.value instruction.
bool isTokenTy() const
Return true if this is &#39;token&#39;.
Definition: Type.h:194
Value * getArgOperand(unsigned i) const
getArgOperand/setArgOperand - Return/set the i-th call argument.
PointerUnion< const Value *, const PseudoSourceValue * > ptrVal
virtual const TargetIntrinsicInfo * getIntrinsicInfo() const
If intrinsic information is available, return it. If not, return null.
BasicBlock * getIncomingBlock(unsigned i) const
Return incoming basic block number i.
SyncScope::ID getSyncScopeID() const
Returns the synchronization scope ID of this load instruction.
Definition: Instructions.h:245
void setMBB(MachineBasicBlock &MBB)
Set the insertion point to the end of MBB.
MachineInstrBuilder buildConstant(unsigned Res, const ConstantInt &Val)
Build and insert Res = G_CONSTANT Val.
const MachineInstrBuilder & addExternalSymbol(const char *FnName, unsigned char TargetFlags=0) const
#define I(x, y, z)
Definition: MD5.cpp:58
static Constant * getZeroValueForNegation(Type *Ty)
Floating point negation must be implemented with f(x) = -0.0 - x.
Definition: Constants.cpp:675
MachineInstrBuilder buildMul(unsigned Res, unsigned Op0, unsigned Op1)
Build and insert Res = G_MUL Op0, Op1.
Pair of physical register and lane mask.
virtual const TargetFrameLowering * getFrameLowering() const
The memory access always returns the same value (or traps).
LLT getType(unsigned VReg) const
Get the low-level type of VReg or LLT{} if VReg is not a generic (target independent) virtual registe...
bool isZero() const
This is just a convenience method to make client code smaller for a common code.
Definition: Constants.h:193
LLVM_NODISCARD std::enable_if<!is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
Definition: Casting.h:323
Value * getReturnValue() const
Convenience accessor. Returns null if there is no return value.
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - This function should be overriden by passes that need analysis information to do t...
bool isUnconditional() const
AsmDialect getDialect() const
Definition: InlineAsm.h:69
Multiway switch.
iterator_range< op_iterator > arg_operands()
Iteration adapter for range-for loops.
const Value * getCalledValue() const
Get a pointer to the function that is invoked by this instruction.
This file declares the IRTranslator pass.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
void insert(iterator MBBI, MachineBasicBlock *MBB)
MachineInstrBuilder buildCast(unsigned Dst, unsigned Src)
Build and insert an appropriate cast between two registers of equal size.
A raw_ostream that writes to an std::string.
Definition: raw_ostream.h:462
aarch64 promote const
Module * getParent()
Get the module that this global value is contained inside of...
Definition: GlobalValue.h:561
LLVM Value Representation.
Definition: Value.h:73
Constant * getPersonalityFn() const
Get the personality function associated with this function.
Definition: Function.cpp:1260
unsigned getSizeInBits(unsigned Reg, const MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI) const
Get the size in bits of Reg.
uint64_t getTypeStoreSize(Type *Ty) const
Returns the maximum number of bytes that may be overwritten by storing the specified type...
Definition: DataLayout.h:386
constexpr char Size[]
Key for Kernel::Arg::Metadata::mSize.
This file describes how to lower LLVM calls to machine code calls.
void push_back(MachineBasicBlock *MBB)
unsigned getStackPointerRegisterToSaveRestore() const
If a physical register, this specifies the register that llvm.savestack/llvm.restorestack should save...
MachineInstrBuilder buildLoad(unsigned Res, unsigned Addr, MachineMemOperand &MMO)
Build and insert Res = G_LOAD Addr, MMO.
INITIALIZE_PASS_BEGIN(IRTranslator, DEBUG_TYPE, "IRTranslator LLVM IR -> MI", false, false) INITIALIZE_PASS_END(IRTranslator
bool doesNotAccessMemory() const
Determine if the call does not access memory.
Invoke instruction.
#define DEBUG(X)
Definition: Debug.h:118
IRTranslator LLVM IR MI
void setRegClass(unsigned Reg, const TargetRegisterClass *RC)
setRegClass - Set the register class of the specified virtual register.
const MachineInstrBuilder & addDef(unsigned RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register definition operand.
bool isStaticAlloca() const
Return true if this alloca is in the entry block of the function and is a constant size...
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned char TargetFlags=0) const
MachineInstrBuilder buildGlobalValue(unsigned Res, const GlobalValue *GV)
Build and insert Res = G_GLOBAL_VALUE GV.
virtual bool lowerReturn(MachineIRBuilder &MIRBuilder, const Value *Val, unsigned VReg) const
This hook must be implemented to lower outgoing return values, described by Val, into the specified v...
Definition: CallLowering.h:145
MachineInstrBuilder buildMerge(unsigned Res, ArrayRef< unsigned > Ops)
Build and insert Res = G_MERGE_VALUES Op0, ...
int CreateVariableSizedObject(unsigned Alignment, const AllocaInst *Alloca)
Notify the MachineFrameInfo object that a variable sized object has been created. ...
This represents the llvm.dbg.declare instruction.
Value * getPointerOperand()
Definition: Instructions.h:398
MachineInstr::mmo_iterator allocateMemRefsArray(unsigned long Num)
allocateMemRefsArray - Allocate an array to hold MachineMemOperand pointers.
The optimization diagnostic interface.
Statically lint checks LLVM IR
Definition: Lint.cpp:193
constexpr char Args[]
Key for Kernel::Metadata::mArgs.
int64_t getIndexedOffsetInType(Type *ElemTy, ArrayRef< Value *> Indices) const
Returns the offset from the beginning of the type for the specified indices.
Definition: DataLayout.cpp:729
0 0 0 0 Always false (always folded)
Definition: InstrTypes.h:855
IntegerType * Int32Ty
This file describes how to lower LLVM code to machine code.
const BasicBlock * getParent() const
Definition: Instruction.h:67
virtual const TargetRegisterClass * getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const
Returns a TargetRegisterClass used for pointer values.
an instruction to allocate memory on the stack
Definition: Instructions.h:60
This instruction inserts a struct field of array element value into an aggregate value.
gep_type_iterator gep_type_begin(const User *GEP)
size_type count(const T &V) const
count - Return 1 if the element is in the set, 0 otherwise.
Definition: SmallSet.h:65
MachineInstrBuilder buildBrCond(unsigned Tst, MachineBasicBlock &BB)
Build and insert G_BRCOND Tst, Dest.