LLVM  6.0.0svn
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llvm::TargetLoweringBase Class Reference

This base class for TargetLowering contains the SelectionDAG-independent parts that can be used from the rest of CodeGen. More...

#include "llvm/CodeGen/TargetLowering.h"

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Classes

struct  AddrMode
 This represents an addressing mode of: BaseGV + BaseOffs + BaseReg + Scale*ScaleReg If BaseGV is null, there is no BaseGV. More...
 
class  ArgListEntry
 
struct  IntrinsicInfo
 
class  ValueTypeActionImpl
 

Public Types

enum  LegalizeAction : uint8_t {
  Legal, Promote, Expand, LibCall,
  Custom
}
 This enum indicates whether operations are valid for a target, and if not, what action should be used to make them valid. More...
 
enum  LegalizeTypeAction : uint8_t {
  TypeLegal, TypePromoteInteger, TypeExpandInteger, TypeSoftenFloat,
  TypeExpandFloat, TypeScalarizeVector, TypeSplitVector, TypeWidenVector,
  TypePromoteFloat
}
 This enum indicates whether a types are legal for a target, and if not, what action should be used to make them valid. More...
 
enum  BooleanContent { UndefinedBooleanContent, ZeroOrOneBooleanContent, ZeroOrNegativeOneBooleanContent }
 Enum that describes how the target represents true/false values. More...
 
enum  SelectSupportKind { ScalarValSelect, ScalarCondVectorVal, VectorMaskSelect }
 Enum that describes what type of support for selects the target has. More...
 
enum  AtomicExpansionKind { AtomicExpansionKind::None, AtomicExpansionKind::LLSC, AtomicExpansionKind::LLOnly, AtomicExpansionKind::CmpXChg }
 Enum that specifies what an atomic load/AtomicRMWInst is expanded to, if at all. More...
 
enum  MulExpansionKind { MulExpansionKind::Always, MulExpansionKind::OnlyLegalOrCustom }
 Enum that specifies when a multiplication should be expanded. More...
 
enum  ReciprocalEstimate : int { Unspecified = -1, Disabled = 0, Enabled = 1 }
 Reciprocal estimate status values used by the functions below. More...
 
using LegalizeKind = std::pair< LegalizeTypeAction, EVT >
 LegalizeKind holds the legalization kind that needs to happen to EVT in order to type-legalize it. More...
 
using ArgListTy = std::vector< ArgListEntry >
 

Public Member Functions

virtual void markLibCallAttributes (MachineFunction *MF, unsigned CC, ArgListTy &Args) const
 
 TargetLoweringBase (const TargetMachine &TM)
 NOTE: The TargetMachine owns TLOF. More...
 
 TargetLoweringBase (const TargetLoweringBase &)=delete
 
TargetLoweringBaseoperator= (const TargetLoweringBase &)=delete
 
virtual ~TargetLoweringBase ()=default
 
const TargetMachinegetTargetMachine () const
 
virtual bool useSoftFloat () const
 
MVT getPointerTy (const DataLayout &DL, uint32_t AS=0) const
 Return the pointer type for the given address space, defaults to the pointer type from the data layout. More...
 
MVT getFrameIndexTy (const DataLayout &DL) const
 Return the type for frame index, which is determined by the alloca address space specified through the data layout. More...
 
virtual MVT getFenceOperandTy (const DataLayout &DL) const
 Return the type for operands of fence. More...
 
virtual MVT getScalarShiftAmountTy (const DataLayout &, EVT) const
 EVT is not used in-tree, but is used by out-of-tree target. More...
 
EVT getShiftAmountTy (EVT LHSTy, const DataLayout &DL) const
 
virtual MVT getVectorIdxTy (const DataLayout &DL) const
 Returns the type to be used for the index operand of: ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT, ISD::INSERT_SUBVECTOR, and ISD::EXTRACT_SUBVECTOR. More...
 
virtual bool isSelectSupported (SelectSupportKind) const
 
bool hasMultipleConditionRegisters () const
 Return true if multiple condition registers are available. More...
 
bool hasExtractBitsInsn () const
 Return true if the target has BitExtract instructions. More...
 
virtual TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction (EVT VT) const
 Return the preferred vector type legalization action. More...
 
virtual bool shouldExpandBuildVectorWithShuffles (EVT, unsigned DefinedValues) const
 
virtual bool isIntDivCheap (EVT VT, AttributeList Attr) const
 Return true if integer divide is usually cheaper than a sequence of several shifts, adds, and multiplies for this target. More...
 
virtual bool hasStandaloneRem (EVT VT) const
 Return true if the target can handle a standalone remainder operation. More...
 
virtual bool isFsqrtCheap (SDValue X, SelectionDAG &DAG) const
 Return true if SQRT(X) shouldn't be replaced with X*RSQRT(X). More...
 
int getRecipEstimateSqrtEnabled (EVT VT, MachineFunction &MF) const
 Return a ReciprocalEstimate enum value for a square root of the given type based on the function's attributes. More...
 
int getRecipEstimateDivEnabled (EVT VT, MachineFunction &MF) const
 Return a ReciprocalEstimate enum value for a division of the given type based on the function's attributes. More...
 
int getSqrtRefinementSteps (EVT VT, MachineFunction &MF) const
 Return the refinement step count for a square root of the given type based on the function's attributes. More...
 
int getDivRefinementSteps (EVT VT, MachineFunction &MF) const
 Return the refinement step count for a division of the given type based on the function's attributes. More...
 
bool isSlowDivBypassed () const
 Returns true if target has indicated at least one type should be bypassed. More...
 
const DenseMap< unsigned int, unsigned int > & getBypassSlowDivWidths () const
 Returns map of slow types for division or remainder with corresponding fast types. More...
 
bool isJumpExpensive () const
 Return true if Flow Control is an expensive operation that should be avoided. More...
 
bool isPredictableSelectExpensive () const
 Return true if selects are only cheaper than branches if the branch is unlikely to be predicted right. More...
 
virtual BranchProbability getPredictableBranchThreshold () const
 If a branch or a select condition is skewed in one direction by more than this factor, it is very likely to be predicted correctly. More...
 
virtual bool isLoadBitCastBeneficial (EVT LoadVT, EVT BitcastVT) const
 Return true if the following transform is beneficial: fold (conv (load x)) -> (load (conv*)x) On architectures that don't natively support some vector loads efficiently, casting the load to a smaller vector of larger types and loading is more efficient, however, this can be undone by optimizations in dag combiner. More...
 
virtual bool isStoreBitCastBeneficial (EVT StoreVT, EVT BitcastVT) const
 Return true if the following transform is beneficial: (store (y (conv x)), y*)) -> (store x, (x*)) More...
 
virtual bool storeOfVectorConstantIsCheap (EVT MemVT, unsigned NumElem, unsigned AddrSpace) const
 Return true if it is expected to be cheaper to do a store of a non-zero vector constant with the given size and type for the address space than to store the individual scalar element constants. More...
 
virtual bool mergeStoresAfterLegalization () const
 Allow store merging after legalization in addition to before legalization. More...
 
virtual bool canMergeStoresTo (unsigned AS, EVT MemVT, const SelectionDAG &DAG) const
 Returns if it's reasonable to merge stores to MemVT size. More...
 
virtual bool isCheapToSpeculateCttz () const
 Return true if it is cheap to speculate a call to intrinsic cttz. More...
 
virtual bool isCheapToSpeculateCtlz () const
 Return true if it is cheap to speculate a call to intrinsic ctlz. More...
 
virtual bool isCtlzFast () const
 Return true if ctlz instruction is fast. More...
 
virtual bool hasBitPreservingFPLogic (EVT VT) const
 Return true if it is safe to transform an integer-domain bitwise operation into the equivalent floating-point operation. More...
 
virtual bool isMultiStoresCheaperThanBitsMerge (EVT LTy, EVT HTy) const
 Return true if it is cheaper to split the store of a merged int val from a pair of smaller values into multiple stores. More...
 
virtual bool isMaskAndCmp0FoldingBeneficial (const Instruction &AndI) const
 Return if the target supports combining a chain like: More...
 
virtual bool convertSetCCLogicToBitwiseLogic (EVT VT) const
 Use bitwise logic to make pairs of compares more efficient. More...
 
virtual MVT hasFastEqualityCompare (unsigned NumBits) const
 Return the preferred operand type if the target has a quick way to compare integer values of the given size. More...
 
virtual bool hasAndNotCompare (SDValue Y) const
 Return true if the target should transform: (X & Y) == Y —> (~X & Y) == 0 (X & Y) != Y —> (~X & Y) != 0. More...
 
virtual bool hasAndNot (SDValue X) const
 Return true if the target has a bitwise and-not operation: X = ~A & B This can be used to simplify select or other instructions. More...
 
bool enableExtLdPromotion () const
 Return true if the target wants to use the optimization that turns ext(promotableInst1(...(promotableInstN(load)))) into promotedInst1(...(promotedInstN(ext(load)))). More...
 
virtual bool canCombineStoreAndExtract (Type *VectorTy, Value *Idx, unsigned &Cost) const
 Return true if the target can combine store(extractelement VectorTy, Idx). More...
 
bool hasFloatingPointExceptions () const
 Return true if target supports floating point exceptions. More...
 
virtual bool enableAggressiveFMAFusion (EVT VT) const
 Return true if target always beneficiates from combining into FMA for a given value type. More...
 
virtual EVT getSetCCResultType (const DataLayout &DL, LLVMContext &Context, EVT VT) const
 Return the ValueType of the result of SETCC operations. More...
 
virtual MVT::SimpleValueType getCmpLibcallReturnType () const
 Return the ValueType for comparison libcalls. More...
 
BooleanContent getBooleanContents (bool isVec, bool isFloat) const
 For targets without i1 registers, this gives the nature of the high-bits of boolean values held in types wider than i1. More...
 
BooleanContent getBooleanContents (EVT Type) const
 
Sched::Preference getSchedulingPreference () const
 Return target scheduling preference. More...
 
virtual Sched::Preference getSchedulingPreference (SDNode *) const
 Some scheduler, e.g. More...
 
virtual const TargetRegisterClassgetRegClassFor (MVT VT) const
 Return the register class that should be used for the specified value type. More...
 
virtual const TargetRegisterClassgetRepRegClassFor (MVT VT) const
 Return the 'representative' register class for the specified value type. More...
 
virtual uint8_t getRepRegClassCostFor (MVT VT) const
 Return the cost of the 'representative' register class for the specified value type. More...
 
bool isTypeLegal (EVT VT) const
 Return true if the target has native support for the specified value type. More...
 
const ValueTypeActionImplgetValueTypeActions () const
 
LegalizeTypeAction getTypeAction (LLVMContext &Context, EVT VT) const
 Return how we should legalize values of this type, either it is already legal (return 'Legal') or we need to promote it to a larger type (return 'Promote'), or we need to expand it into multiple registers of smaller integer type (return 'Expand'). More...
 
LegalizeTypeAction getTypeAction (MVT VT) const
 
EVT getTypeToTransformTo (LLVMContext &Context, EVT VT) const
 For types supported by the target, this is an identity function. More...
 
EVT getTypeToExpandTo (LLVMContext &Context, EVT VT) const
 For types supported by the target, this is an identity function. More...
 
unsigned getVectorTypeBreakdown (LLVMContext &Context, EVT VT, EVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) const
 Vector types are broken down into some number of legal first class types. More...
 
virtual unsigned getVectorTypeBreakdownForCallingConv (LLVMContext &Context, EVT VT, EVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) const
 Certain targets such as MIPS require that some types such as vectors are always broken down into scalars in some contexts. More...
 
virtual bool getTgtMemIntrinsic (IntrinsicInfo &, const CallInst &, unsigned) const
 Given an intrinsic, checks if on the target the intrinsic will need to map to a MemIntrinsicNode (touches memory). More...
 
virtual bool isFPImmLegal (const APFloat &, EVT) const
 Returns true if the target can instruction select the specified FP immediate natively. More...
 
virtual bool isShuffleMaskLegal (ArrayRef< int >, EVT) const
 Targets can use this to indicate that they only support some VECTOR_SHUFFLE operations, those with specific masks. More...
 
virtual bool canOpTrap (unsigned Op, EVT VT) const
 Returns true if the operation can trap for the value type. More...
 
virtual bool isVectorClearMaskLegal (const SmallVectorImpl< int > &, EVT) const
 Similar to isShuffleMaskLegal. More...
 
LegalizeAction getOperationAction (unsigned Op, EVT VT) const
 Return how this operation should be treated: either it is legal, needs to be promoted to a larger size, needs to be expanded to some other code sequence, or the target has a custom expander for it. More...
 
bool isOperationLegalOrCustom (unsigned Op, EVT VT) const
 Return true if the specified operation is legal on this target or can be made legal with custom lowering. More...
 
bool isOperationLegalOrPromote (unsigned Op, EVT VT) const
 Return true if the specified operation is legal on this target or can be made legal using promotion. More...
 
bool isOperationLegalOrCustomOrPromote (unsigned Op, EVT VT) const
 Return true if the specified operation is legal on this target or can be made legal with custom lowering or using promotion. More...
 
bool isOperationCustom (unsigned Op, EVT VT) const
 Return true if the operation uses custom lowering, regardless of whether the type is legal or not. More...
 
bool areJTsAllowed (const Function *Fn) const
 Return true if lowering to a jump table is allowed. More...
 
bool rangeFitsInWord (const APInt &Low, const APInt &High, const DataLayout &DL) const
 Check whether the range [Low,High] fits in a machine word. More...
 
bool isSuitableForJumpTable (const SwitchInst *SI, uint64_t NumCases, uint64_t Range) const
 Return true if lowering to a jump table is suitable for a set of case clusters which may contain NumCases cases, Range range of values. More...
 
bool isSuitableForBitTests (unsigned NumDests, unsigned NumCmps, const APInt &Low, const APInt &High, const DataLayout &DL) const
 Return true if lowering to a bit test is suitable for a set of case clusters which contains NumDests unique destinations, Low and High as its lowest and highest case values, and expects NumCmps case value comparisons. More...
 
bool isOperationExpand (unsigned Op, EVT VT) const
 Return true if the specified operation is illegal on this target or unlikely to be made legal with custom lowering. More...
 
bool isOperationLegal (unsigned Op, EVT VT) const
 Return true if the specified operation is legal on this target. More...
 
LegalizeAction getLoadExtAction (unsigned ExtType, EVT ValVT, EVT MemVT) const
 Return how this load with extension should be treated: either it is legal, needs to be promoted to a larger size, needs to be expanded to some other code sequence, or the target has a custom expander for it. More...
 
bool isLoadExtLegal (unsigned ExtType, EVT ValVT, EVT MemVT) const
 Return true if the specified load with extension is legal on this target. More...
 
bool isLoadExtLegalOrCustom (unsigned ExtType, EVT ValVT, EVT MemVT) const
 Return true if the specified load with extension is legal or custom on this target. More...
 
LegalizeAction getTruncStoreAction (EVT ValVT, EVT MemVT) const
 Return how this store with truncation should be treated: either it is legal, needs to be promoted to a larger size, needs to be expanded to some other code sequence, or the target has a custom expander for it. More...
 
bool isTruncStoreLegal (EVT ValVT, EVT MemVT) const
 Return true if the specified store with truncation is legal on this target. More...
 
bool isTruncStoreLegalOrCustom (EVT ValVT, EVT MemVT) const
 Return true if the specified store with truncation has solution on this target. More...
 
LegalizeAction getIndexedLoadAction (unsigned IdxMode, MVT VT) const
 Return how the indexed load should be treated: either it is legal, needs to be promoted to a larger size, needs to be expanded to some other code sequence, or the target has a custom expander for it. More...
 
bool isIndexedLoadLegal (unsigned IdxMode, EVT VT) const
 Return true if the specified indexed load is legal on this target. More...
 
LegalizeAction getIndexedStoreAction (unsigned IdxMode, MVT VT) const
 Return how the indexed store should be treated: either it is legal, needs to be promoted to a larger size, needs to be expanded to some other code sequence, or the target has a custom expander for it. More...
 
bool isIndexedStoreLegal (unsigned IdxMode, EVT VT) const
 Return true if the specified indexed load is legal on this target. More...
 
LegalizeAction getCondCodeAction (ISD::CondCode CC, MVT VT) const
 Return how the condition code should be treated: either it is legal, needs to be expanded to some other code sequence, or the target has a custom expander for it. More...
 
bool isCondCodeLegal (ISD::CondCode CC, MVT VT) const
 Return true if the specified condition code is legal on this target. More...
 
MVT getTypeToPromoteTo (unsigned Op, MVT VT) const
 If the action for this operation is to promote, this method returns the ValueType to promote to. More...
 
EVT getValueType (const DataLayout &DL, Type *Ty, bool AllowUnknown=false) const
 Return the EVT corresponding to this LLVM type. More...
 
MVT getSimpleValueType (const DataLayout &DL, Type *Ty, bool AllowUnknown=false) const
 Return the MVT corresponding to this LLVM type. See getValueType. More...
 
virtual unsigned getByValTypeAlignment (Type *Ty, const DataLayout &DL) const
 Return the desired alignment for ByVal or InAlloca aggregate function arguments in the caller parameter area. More...
 
MVT getRegisterType (MVT VT) const
 Return the type of registers that this ValueType will eventually require. More...
 
MVT getRegisterType (LLVMContext &Context, EVT VT) const
 Return the type of registers that this ValueType will eventually require. More...
 
unsigned getNumRegisters (LLVMContext &Context, EVT VT) const
 Return the number of registers that this ValueType will eventually require. More...
 
virtual MVT getRegisterTypeForCallingConv (MVT VT) const
 Certain combinations of ABIs, Targets and features require that types are legal for some operations and not for other operations. More...
 
virtual MVT getRegisterTypeForCallingConv (LLVMContext &Context, EVT VT) const
 
virtual unsigned getNumRegistersForCallingConv (LLVMContext &Context, EVT VT) const
 Certain targets require unusual breakdowns of certain types. More...
 
virtual unsigned getABIAlignmentForCallingConv (Type *ArgTy, DataLayout DL) const
 Certain targets have context senstive alignment requirements, where one type has the alignment requirement of another type. More...
 
virtual bool ShouldShrinkFPConstant (EVT) const
 If true, then instruction selection should seek to shrink the FP constant of the specified type to a smaller type in order to save space and / or reduce runtime. More...
 
virtual bool shouldReduceLoadWidth (SDNode *Load, ISD::LoadExtType ExtTy, EVT NewVT) const
 
bool hasBigEndianPartOrdering (EVT VT, const DataLayout &DL) const
 When splitting a value of the specified type into parts, does the Lo or Hi part come first? This usually follows the endianness, except for ppcf128, where the Hi part always comes first. More...
 
bool hasTargetDAGCombine (ISD::NodeType NT) const
 If true, the target has custom DAG combine transformations that it can perform for the specified node. More...
 
unsigned getGatherAllAliasesMaxDepth () const
 
virtual unsigned getVaListSizeInBits (const DataLayout &DL) const
 Returns the size of the platform's va_list object. More...
 
unsigned getMaxStoresPerMemset (bool OptSize) const
 Get maximum # of store operations permitted for llvm.memset. More...
 
unsigned getMaxStoresPerMemcpy (bool OptSize) const
 Get maximum # of store operations permitted for llvm.memcpy. More...
 
unsigned getMaxExpandSizeMemcmp (bool OptSize) const
 Get maximum # of load operations permitted for memcmp. More...
 
unsigned getMaxStoresPerMemmove (bool OptSize) const
 Get maximum # of store operations permitted for llvm.memmove. More...
 
virtual bool allowsMisalignedMemoryAccesses (EVT, unsigned AddrSpace=0, unsigned Align=1, bool *=nullptr) const
 Determine if the target supports unaligned memory accesses. More...
 
bool allowsMemoryAccess (LLVMContext &Context, const DataLayout &DL, EVT VT, unsigned AddrSpace=0, unsigned Alignment=1, bool *Fast=nullptr) const
 Return true if the target supports a memory access of this type for the given address space and alignment. More...
 
virtual EVT getOptimalMemOpType (uint64_t, unsigned, unsigned, bool, bool, bool, MachineFunction &) const
 Returns the target specific optimal type for load and store operations as a result of memset, memcpy, and memmove lowering. More...
 
virtual bool isSafeMemOpType (MVT) const
 Returns true if it's safe to use load / store of the specified type to expand memcpy / memset inline. More...
 
bool usesUnderscoreSetJmp () const
 Determine if we should use _setjmp or setjmp to implement llvm.setjmp. More...
 
bool usesUnderscoreLongJmp () const
 Determine if we should use _longjmp or longjmp to implement llvm.longjmp. More...
 
unsigned getMinimumJumpTableEntries () const
 Return lower limit for number of blocks in a jump table. More...
 
unsigned getMinimumJumpTableDensity (bool OptForSize) const
 Return lower limit of the density in a jump table. More...
 
unsigned getMaximumJumpTableSize () const
 Return upper limit for number of entries in a jump table. More...
 
virtual bool isJumpTableRelative () const
 
unsigned getStackPointerRegisterToSaveRestore () const
 If a physical register, this specifies the register that llvm.savestack/llvm.restorestack should save and restore. More...
 
virtual unsigned getExceptionPointerRegister (const Constant *PersonalityFn) const
 If a physical register, this returns the register that receives the exception address on entry to an EH pad. More...
 
virtual unsigned getExceptionSelectorRegister (const Constant *PersonalityFn) const
 If a physical register, this returns the register that receives the exception typeid on entry to a landing pad. More...
 
virtual bool needsFixedCatchObjects () const
 
unsigned getJumpBufSize () const
 Returns the target's jmp_buf size in bytes (if never set, the default is 200) More...
 
unsigned getJumpBufAlignment () const
 Returns the target's jmp_buf alignment in bytes (if never set, the default is 0) More...
 
unsigned getMinStackArgumentAlignment () const
 Return the minimum stack alignment of an argument. More...
 
unsigned getMinFunctionAlignment () const
 Return the minimum function alignment. More...
 
unsigned getPrefFunctionAlignment () const
 Return the preferred function alignment. More...
 
virtual unsigned getPrefLoopAlignment (MachineLoop *ML=nullptr) const
 Return the preferred loop alignment. More...
 
virtual ValuegetIRStackGuard (IRBuilder<> &IRB) const
 If the target has a standard location for the stack protector guard, returns the address of that location. More...
 
virtual void insertSSPDeclarations (Module &M) const
 Inserts necessary declarations for SSP (stack protection) purpose. More...
 
virtual ValuegetSDagStackGuard (const Module &M) const
 Return the variable that's previously inserted by insertSSPDeclarations, if any, otherwise return nullptr. More...
 
virtual ValuegetSSPStackGuardCheck (const Module &M) const
 If the target has a standard stack protection check function that performs validation and error handling, returns the function. More...
 
virtual ValuegetSafeStackPointerLocation (IRBuilder<> &IRB) const
 Returns the target-specific address of the unsafe stack pointer. More...
 
virtual StringRef getStackProbeSymbolName (MachineFunction &MF) const
 Returns the name of the symbol used to emit stack probes or the empty string if not applicable. More...
 
virtual bool isNoopAddrSpaceCast (unsigned SrcAS, unsigned DestAS) const
 Returns true if a cast between SrcAS and DestAS is a noop. More...
 
virtual bool isCheapAddrSpaceCast (unsigned SrcAS, unsigned DestAS) const
 Returns true if a cast from SrcAS to DestAS is "cheap", such that e.g. More...
 
virtual bool shouldAlignPointerArgs (CallInst *, unsigned &, unsigned &) const
 Return true if the pointer arguments to CI should be aligned by aligning the object whose address is being passed. More...
 
virtual void emitAtomicCmpXchgNoStoreLLBalance (IRBuilder<> &Builder) const
 
virtual bool shouldExpandAtomicStoreInIR (StoreInst *SI) const
 Returns true if the given (atomic) store should be expanded by the IR-level AtomicExpand pass into an "atomic xchg" which ignores its input. More...
 
virtual bool shouldSignExtendTypeInLibCall (EVT Type, bool IsSigned) const
 Returns true if arguments should be sign-extended in lib calls. More...
 
virtual AtomicExpansionKind shouldExpandAtomicLoadInIR (LoadInst *LI) const
 Returns how the given (atomic) load should be expanded by the IR-level AtomicExpand pass. More...
 
virtual bool shouldExpandAtomicCmpXchgInIR (AtomicCmpXchgInst *AI) const
 Returns true if the given atomic cmpxchg should be expanded by the IR-level AtomicExpand pass into a load-linked/store-conditional sequence (through emitLoadLinked() and emitStoreConditional()). More...
 
virtual AtomicExpansionKind shouldExpandAtomicRMWInIR (AtomicRMWInst *) const
 Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW, if at all. More...
 
virtual LoadInstlowerIdempotentRMWIntoFencedLoad (AtomicRMWInst *RMWI) const
 On some platforms, an AtomicRMW that never actually modifies the value (such as fetch_add of 0) can be turned into a fence followed by an atomic load. More...
 
virtual ISD::NodeType getExtendForAtomicOps () const
 Returns how the platform's atomic operations are extended (ZERO_EXTEND, SIGN_EXTEND, or ANY_EXTEND). More...
 
virtual bool shouldNormalizeToSelectSequence (LLVMContext &Context, EVT VT) const
 Returns true if we should normalize select(N0&N1, X, Y) => select(N0, select(N1, X, Y), Y) and select(N0|N1, X, Y) => select(N0, select(N1, X, Y, Y)) if it is likely that it saves us from materializing N0 and N1 in an integer register. More...
 
virtual bool convertSelectOfConstantsToMath (EVT VT) const
 Return true if a select of constants (select Cond, C1, C2) should be transformed into simple math ops with the condition value. More...
 
virtual bool getAddrModeArguments (IntrinsicInst *, SmallVectorImpl< Value *> &, Type *&) const
 CodeGenPrepare sinks address calculations into the same BB as Load/Store instructions reading the address. More...
 
virtual bool isLegalAddressingMode (const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AddrSpace, Instruction *I=nullptr) const
 Return true if the addressing mode represented by AM is legal for this target, for a load/store of the specified type. More...
 
virtual int getScalingFactorCost (const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS=0) const
 Return the cost of the scaling factor used in the addressing mode represented by AM for this target, for a load/store of the specified type. More...
 
virtual bool isLegalICmpImmediate (int64_t) const
 Return true if the specified immediate is legal icmp immediate, that is the target has icmp instructions which can compare a register against the immediate without having to materialize the immediate into a register. More...
 
virtual bool isLegalAddImmediate (int64_t) const
 Return true if the specified immediate is legal add immediate, that is the target has add instructions which can add a register with the immediate without having to materialize the immediate into a register. More...
 
virtual bool isVectorShiftByScalarCheap (Type *Ty) const
 Return true if it's significantly cheaper to shift a vector by a uniform scalar than by an amount which will vary across each lane. More...
 
virtual bool isCommutativeBinOp (unsigned Opcode) const
 Returns true if the opcode is a commutative binary operation. More...
 
virtual bool isTruncateFree (Type *FromTy, Type *ToTy) const
 Return true if it's free to truncate a value of type FromTy to type ToTy. More...
 
virtual bool allowTruncateForTailCall (Type *FromTy, Type *ToTy) const
 Return true if a truncation from FromTy to ToTy is permitted when deciding whether a call is in tail position. More...
 
virtual bool isTruncateFree (EVT FromVT, EVT ToVT) const
 
virtual bool isProfitableToHoist (Instruction *I) const
 
bool isExtFree (const Instruction *I) const
 Return true if the extension represented by I is free. More...
 
bool isExtLoad (const LoadInst *Load, const Instruction *Ext, const DataLayout &DL) const
 Return true if Load and Ext can form an ExtLoad. More...
 
virtual bool isZExtFree (Type *FromTy, Type *ToTy) const
 Return true if any actual instruction that defines a value of type FromTy implicitly zero-extends the value to ToTy in the result register. More...
 
virtual bool isZExtFree (EVT FromTy, EVT ToTy) const
 
virtual bool hasPairedLoad (EVT, unsigned &) const
 Return true if the target supplies and combines to a paired load two loaded values of type LoadedType next to each other in memory. More...
 
virtual unsigned getMaxSupportedInterleaveFactor () const
 Get the maximum supported factor for interleaved memory accesses. More...
 
virtual bool lowerInterleavedLoad (LoadInst *LI, ArrayRef< ShuffleVectorInst *> Shuffles, ArrayRef< unsigned > Indices, unsigned Factor) const
 Lower an interleaved load to target specific intrinsics. More...
 
virtual bool lowerInterleavedStore (StoreInst *SI, ShuffleVectorInst *SVI, unsigned Factor) const
 Lower an interleaved store to target specific intrinsics. More...
 
virtual bool isZExtFree (SDValue Val, EVT VT2) const
 Return true if zero-extending the specific node Val to type VT2 is free (either because it's implicitly zero-extended such as ARM ldrb / ldrh or because it's folded such as X86 zero-extending loads). More...
 
virtual bool isFPExtFree (EVT DestVT, EVT SrcVT) const
 Return true if an fpext operation is free (for instance, because single-precision floating-point numbers are implicitly extended to double-precision). More...
 
virtual bool isFPExtFoldable (unsigned Opcode, EVT DestVT, EVT SrcVT) const
 Return true if an fpext operation input to an Opcode operation is free (for instance, because half-precision floating-point numbers are implicitly extended to float-precision) for an FMA instruction. More...
 
virtual bool isVectorLoadExtDesirable (SDValue ExtVal) const
 Return true if folding a vector load into ExtVal (a sign, zero, or any extend node) is profitable. More...
 
virtual bool isFNegFree (EVT VT) const
 Return true if an fneg operation is free to the point where it is never worthwhile to replace it with a bitwise operation. More...
 
virtual bool isFAbsFree (EVT VT) const
 Return true if an fabs operation is free to the point where it is never worthwhile to replace it with a bitwise operation. More...
 
virtual bool isFMAFasterThanFMulAndFAdd (EVT) const
 Return true if an FMA operation is faster than a pair of fmul and fadd instructions. More...
 
virtual bool isNarrowingProfitable (EVT, EVT) const
 Return true if it's profitable to narrow operations of type VT1 to VT2. More...
 
virtual bool shouldConvertConstantLoadToIntImm (const APInt &Imm, Type *Ty) const
 Return true if it is beneficial to convert a load of a constant to just the constant itself. More...
 
virtual bool isExtractSubvectorCheap (EVT ResVT, EVT SrcVT, unsigned Index) const
 Return true if EXTRACT_SUBVECTOR is cheap for extracting this result type from this source type with this index. More...
 
virtual bool aggressivelyPreferBuildVectorSources (EVT VecVT) const
 
void setLibcallName (RTLIB::Libcall Call, const char *Name)
 Rename the default libcall routine name for the specified libcall. More...
 
const chargetLibcallName (RTLIB::Libcall Call) const
 Get the libcall routine name for the specified libcall. More...
 
void setCmpLibcallCC (RTLIB::Libcall Call, ISD::CondCode CC)
 Override the default CondCode to be used to test the result of the comparison libcall against zero. More...
 
ISD::CondCode getCmpLibcallCC (RTLIB::Libcall Call) const
 Get the CondCode that's to be used to test the result of the comparison libcall against zero. More...
 
void setLibcallCallingConv (RTLIB::Libcall Call, CallingConv::ID CC)
 Set the CallingConv that should be used for the specified libcall. More...
 
CallingConv::ID getLibcallCallingConv (RTLIB::Libcall Call) const
 Get the CallingConv that should be used for the specified libcall. More...
 
virtual void finalizeLowering (MachineFunction &MF) const
 Execute target specific actions to finalize target lowering. More...
 
Helpers for TargetTransformInfo implementations
int InstructionOpcodeToISD (unsigned Opcode) const
 Get the ISD node that corresponds to the Instruction class opcode. More...
 
std::pair< int, MVTgetTypeLegalizationCost (const DataLayout &DL, Type *Ty) const
 Estimate the cost of type-legalization and the legalized type. More...
 
Helpers for atomic expansion.
unsigned getMaxAtomicSizeInBitsSupported () const
 Returns the maximum atomic operation size (in bits) supported by the backend. More...
 
unsigned getMinCmpXchgSizeInBits () const
 Returns the size of the smallest cmpxchg or ll/sc instruction the backend supports. More...
 
virtual bool shouldInsertFencesForAtomic (const Instruction *I) const
 Whether AtomicExpandPass should automatically insert fences and reduce ordering for this atomic. More...
 
virtual ValueemitLoadLinked (IRBuilder<> &Builder, Value *Addr, AtomicOrdering Ord) const
 Perform a load-linked operation on Addr, returning a "Value *" with the corresponding pointee type. More...
 
virtual ValueemitStoreConditional (IRBuilder<> &Builder, Value *Val, Value *Addr, AtomicOrdering Ord) const
 Perform a store-conditional operation to Addr. More...
 
virtual InstructionemitLeadingFence (IRBuilder<> &Builder, Instruction *Inst, AtomicOrdering Ord) const
 Inserts in the IR a target-specific intrinsic specifying a fence. More...
 
virtual InstructionemitTrailingFence (IRBuilder<> &Builder, Instruction *Inst, AtomicOrdering Ord) const
 

Static Public Member Functions

static ISD::NodeType getExtendForContent (BooleanContent Content)
 

Protected Member Functions

void initActions ()
 Initialize all of the actions to default values. More...
 
ValuegetDefaultSafeStackPointerLocation (IRBuilder<> &IRB, bool UseTLS) const
 
void setBooleanContents (BooleanContent Ty)
 Specify how the target extends the result of integer and floating point boolean values from i1 to a wider type. More...
 
void setBooleanContents (BooleanContent IntTy, BooleanContent FloatTy)
 Specify how the target extends the result of integer and floating point boolean values from i1 to a wider type. More...
 
void setBooleanVectorContents (BooleanContent Ty)
 Specify how the target extends the result of a vector boolean value from a vector of i1 to a wider type. More...
 
void setSchedulingPreference (Sched::Preference Pref)
 Specify the target scheduling preference. More...
 
void setUseUnderscoreSetJmp (bool Val)
 Indicate whether this target prefers to use _setjmp to implement llvm.setjmp or the version without _. More...
 
void setUseUnderscoreLongJmp (bool Val)
 Indicate whether this target prefers to use _longjmp to implement llvm.longjmp or the version without _. More...
 
void setMinimumJumpTableEntries (unsigned Val)
 Indicate the minimum number of blocks to generate jump tables. More...
 
void setMaximumJumpTableSize (unsigned)
 Indicate the maximum number of entries in jump tables. More...
 
void setStackPointerRegisterToSaveRestore (unsigned R)
 If set to a physical register, this specifies the register that llvm.savestack/llvm.restorestack should save and restore. More...
 
void setHasMultipleConditionRegisters (bool hasManyRegs=true)
 Tells the code generator that the target has multiple (allocatable) condition registers that can be used to store the results of comparisons for use by selects and conditional branches. More...
 
void setHasExtractBitsInsn (bool hasExtractInsn=true)
 Tells the code generator that the target has BitExtract instructions. More...
 
void setJumpIsExpensive (bool isExpensive=true)
 Tells the code generator not to expand logic operations on comparison predicates into separate sequences that increase the amount of flow control. More...
 
void setHasFloatingPointExceptions (bool FPExceptions=true)
 Tells the code generator that this target supports floating point exceptions and cares about preserving floating point exception behavior. More...
 
void addBypassSlowDiv (unsigned int SlowBitWidth, unsigned int FastBitWidth)
 Tells the code generator which bitwidths to bypass. More...
 
void addRegisterClass (MVT VT, const TargetRegisterClass *RC)
 Add the specified register class as an available regclass for the specified value type. More...
 
virtual std::pair< const TargetRegisterClass *, uint8_t > findRepresentativeClass (const TargetRegisterInfo *TRI, MVT VT) const
 Return the largest legal super-reg register class of the register class for the specified type and its associated "cost". More...
 
void computeRegisterProperties (const TargetRegisterInfo *TRI)
 Once all of the register classes are added, this allows us to compute derived properties we expose. More...
 
void setOperationAction (unsigned Op, MVT VT, LegalizeAction Action)
 Indicate that the specified operation does not work with the specified type and indicate what to do about it. More...
 
void setLoadExtAction (unsigned ExtType, MVT ValVT, MVT MemVT, LegalizeAction Action)
 Indicate that the specified load with extension does not work with the specified type and indicate what to do about it. More...
 
void setTruncStoreAction (MVT ValVT, MVT MemVT, LegalizeAction Action)
 Indicate that the specified truncating store does not work with the specified type and indicate what to do about it. More...
 
void setIndexedLoadAction (unsigned IdxMode, MVT VT, LegalizeAction Action)
 Indicate that the specified indexed load does or does not work with the specified type and indicate what to do abort it. More...
 
void setIndexedStoreAction (unsigned IdxMode, MVT VT, LegalizeAction Action)
 Indicate that the specified indexed store does or does not work with the specified type and indicate what to do about it. More...
 
void setCondCodeAction (ISD::CondCode CC, MVT VT, LegalizeAction Action)
 Indicate that the specified condition code is or isn't supported on the target and indicate what to do about it. More...
 
void AddPromotedToType (unsigned Opc, MVT OrigVT, MVT DestVT)
 If Opc/OrigVT is specified as being promoted, the promotion code defaults to trying a larger integer/fp until it can find one that works. More...
 
void setOperationPromotedToType (unsigned Opc, MVT OrigVT, MVT DestVT)
 Convenience method to set an operation to Promote and specify the type in a single call. More...
 
void setTargetDAGCombine (ISD::NodeType NT)
 Targets should invoke this method for each target independent node that they want to provide a custom DAG combiner for by implementing the PerformDAGCombine virtual method. More...
 
void setJumpBufSize (unsigned Size)
 Set the target's required jmp_buf buffer size (in bytes); default is 200. More...
 
void setJumpBufAlignment (unsigned Align)
 Set the target's required jmp_buf buffer alignment (in bytes); default is 0. More...
 
void setMinFunctionAlignment (unsigned Align)
 Set the target's minimum function alignment (in log2(bytes)) More...
 
void setPrefFunctionAlignment (unsigned Align)
 Set the target's preferred function alignment. More...
 
void setPrefLoopAlignment (unsigned Align)
 Set the target's preferred loop alignment. More...
 
void setMinStackArgumentAlignment (unsigned Align)
 Set the minimum stack alignment of an argument (in log2(bytes)). More...
 
void setMaxAtomicSizeInBitsSupported (unsigned SizeInBits)
 Set the maximum atomic operation size supported by the backend. More...
 
void setMinCmpXchgSizeInBits (unsigned SizeInBits)
 
virtual bool isExtFreeImpl (const Instruction *I) const
 Return true if the extension represented by I is free. More...
 
bool isLegalRC (const TargetRegisterInfo &TRI, const TargetRegisterClass &RC) const
 Return true if the value types that can be represented by the specified register class are all legal. More...
 
MachineBasicBlockemitPatchPoint (MachineInstr &MI, MachineBasicBlock *MBB) const
 Replace/modify any TargetFrameIndex operands with a targte-dependent sequence of memory operands that is recognized by PrologEpilogInserter. More...
 

Protected Attributes

ValueTypeActionImpl ValueTypeActions
 
unsigned GatherAllAliasesMaxDepth
 Depth that GatherAllAliases should should continue looking for chain dependencies when trying to find a more preferable chain. More...
 
unsigned MaxStoresPerMemset
 Specify maximum number of store instructions per memset call. More...
 
unsigned MaxStoresPerMemsetOptSize
 Maximum number of stores operations that may be substituted for the call to memset, used for functions with OptSize attribute. More...
 
unsigned MaxStoresPerMemcpy
 Specify maximum bytes of store instructions per memcpy call. More...
 
unsigned MaxStoresPerMemcpyOptSize
 Maximum number of store operations that may be substituted for a call to memcpy, used for functions with OptSize attribute. More...
 
unsigned MaxLoadsPerMemcmp
 
unsigned MaxLoadsPerMemcmpOptSize
 
unsigned MaxStoresPerMemmove
 Specify maximum bytes of store instructions per memmove call. More...
 
unsigned MaxStoresPerMemmoveOptSize
 Maximum number of store instructions that may be substituted for a call to memmove, used for functions with OptSize attribute. More...
 
bool PredictableSelectIsExpensive
 Tells the code generator that select is more expensive than a branch if the branch is usually predicted right. More...
 
bool EnableExtLdPromotion
 

Detailed Description

This base class for TargetLowering contains the SelectionDAG-independent parts that can be used from the rest of CodeGen.

Definition at line 107 of file TargetLowering.h.

Member Typedef Documentation

◆ ArgListTy

Definition at line 198 of file TargetLowering.h.

◆ LegalizeKind

LegalizeKind holds the legalization kind that needs to happen to EVT in order to type-legalize it.

Definition at line 136 of file TargetLowering.h.

Member Enumeration Documentation

◆ AtomicExpansionKind

Enum that specifies what an atomic load/AtomicRMWInst is expanded to, if at all.

Exists because different targets have different levels of support for these atomic instructions, and also have different options w.r.t. what they should expand to.

Enumerator
None 
LLSC 
LLOnly 
CmpXChg 

Definition at line 158 of file TargetLowering.h.

◆ BooleanContent

Enum that describes how the target represents true/false values.

Enumerator
UndefinedBooleanContent 
ZeroOrOneBooleanContent 
ZeroOrNegativeOneBooleanContent 

Definition at line 139 of file TargetLowering.h.

◆ LegalizeAction

This enum indicates whether operations are valid for a target, and if not, what action should be used to make them valid.

Enumerator
Legal 
Promote 
Expand 
LibCall 
Custom 

Definition at line 111 of file TargetLowering.h.

◆ LegalizeTypeAction

This enum indicates whether a types are legal for a target, and if not, what action should be used to make them valid.

Enumerator
TypeLegal 
TypePromoteInteger 
TypeExpandInteger 
TypeSoftenFloat 
TypeExpandFloat 
TypeScalarizeVector 
TypeSplitVector 
TypeWidenVector 
TypePromoteFloat 

Definition at line 121 of file TargetLowering.h.

◆ MulExpansionKind

Enum that specifies when a multiplication should be expanded.

Enumerator
Always 
OnlyLegalOrCustom 

Definition at line 168 of file TargetLowering.h.

◆ ReciprocalEstimate

Reciprocal estimate status values used by the functions below.

Enumerator
Unspecified 
Disabled 
Enabled 

Definition at line 320 of file TargetLowering.h.

◆ SelectSupportKind

Enum that describes what type of support for selects the target has.

Enumerator
ScalarValSelect 
ScalarCondVectorVal 
VectorMaskSelect 

Definition at line 146 of file TargetLowering.h.

Constructor & Destructor Documentation

◆ TargetLoweringBase() [1/2]

TargetLoweringBase::TargetLoweringBase ( const TargetMachine TM)
explicit

◆ TargetLoweringBase() [2/2]

llvm::TargetLoweringBase::TargetLoweringBase ( const TargetLoweringBase )
delete

◆ ~TargetLoweringBase()

virtual llvm::TargetLoweringBase::~TargetLoweringBase ( )
virtualdefault

Member Function Documentation

◆ addBypassSlowDiv()

void llvm::TargetLoweringBase::addBypassSlowDiv ( unsigned int  SlowBitWidth,
unsigned int  FastBitWidth 
)
inlineprotected

Tells the code generator which bitwidths to bypass.

Definition at line 1682 of file TargetLowering.h.

Referenced by llvm::NVPTXTargetLowering::NVPTXTargetLowering(), and llvm::X86TargetLowering::X86TargetLowering().

◆ AddPromotedToType()

void llvm::TargetLoweringBase::AddPromotedToType ( unsigned  Opc,
MVT  OrigVT,
MVT  DestVT 
)
inlineprotected

If Opc/OrigVT is specified as being promoted, the promotion code defaults to trying a larger integer/fp until it can find one that works.

If that default is insufficient, this method can be used by the target to override the default.

Definition at line 1779 of file TargetLowering.h.

References llvm::MVT::SimpleTy.

Referenced by llvm::AArch64TargetLowering::AArch64TargetLowering(), llvm::AMDGPUTargetLowering::AMDGPUTargetLowering(), llvm::HexagonTargetLowering::HexagonTargetLowering(), llvm::MipsTargetLowering::MipsTargetLowering(), llvm::PPCTargetLowering::PPCTargetLowering(), and llvm::SITargetLowering::SITargetLowering().

◆ addRegisterClass()

void llvm::TargetLoweringBase::addRegisterClass ( MVT  VT,
const TargetRegisterClass RC 
)
inlineprotected

◆ aggressivelyPreferBuildVectorSources()

virtual bool llvm::TargetLoweringBase::aggressivelyPreferBuildVectorSources ( EVT  VecVT) const
inlinevirtual

Reimplemented in llvm::AMDGPUTargetLowering.

Definition at line 2197 of file TargetLowering.h.

Referenced by peekThroughBitcast().

◆ allowsMemoryAccess()

bool TargetLoweringBase::allowsMemoryAccess ( LLVMContext Context,
const DataLayout DL,
EVT  VT,
unsigned  AddrSpace = 0,
unsigned  Alignment = 1,
bool Fast = nullptr 
) const

Return true if the target supports a memory access of this type for the given address space and alignment.

If the access is allowed, the optional final parameter returns if the access is also fast (as defined by the target).

Definition at line 1316 of file TargetLoweringBase.cpp.

References allowsMisalignedMemoryAccesses(), llvm::DataLayout::getABITypeAlignment(), and llvm::EVT::getTypeForEVT().

Referenced by calculateByteProvider(), combineInsertSubvector(), combineLoad(), combineStore(), emitRemovedIntrinsicError(), foldBitcastedFPLogic(), getFPTernOp(), llvm::NVPTXTargetLowering::LowerOperation(), and peekThroughBitcast().

◆ allowsMisalignedMemoryAccesses()

virtual bool llvm::TargetLoweringBase::allowsMisalignedMemoryAccesses ( EVT  ,
unsigned  AddrSpace = 0,
unsigned  Align = 1,
bool = nullptr 
) const
inlinevirtual

Determine if the target supports unaligned memory accesses.

This function returns true if the target allows unaligned memory accesses of the specified type in the given address space. If true, it also returns whether the unaligned memory access is "fast" in the last argument by reference. This is used, for example, in situations where an array copy/move/set is converted to a sequence of store operations. Its use helps to ensure that such replacements don't generate code that causes an alignment error (trap) on the target machine.

Reimplemented in llvm::PPCTargetLowering, llvm::X86TargetLowering, llvm::SystemZTargetLowering, llvm::ARMTargetLowering, llvm::AArch64TargetLowering, llvm::HexagonTargetLowering, llvm::SITargetLowering, llvm::R600TargetLowering, llvm::MipsSETargetLowering, and llvm::Mips16TargetLowering.

Definition at line 1222 of file TargetLowering.h.

References llvm::CallingConv::Fast.

Referenced by allowsMemoryAccess(), llvm::BasicTTIImplBase< AMDGPUTTIImpl >::allowsMisalignedMemoryAccesses(), llvm::XCoreTargetLowering::EmitInstrWithCustomInserter(), FindOptimalMemOpLowering(), getMemCmpLoad(), isBroadcastShuffle(), isWordAligned(), llvm::AMDGPUTargetLowering::performLoadCombine(), and llvm::AMDGPUTargetLowering::performStoreCombine().

◆ allowTruncateForTailCall()

virtual bool llvm::TargetLoweringBase::allowTruncateForTailCall ( Type FromTy,
Type ToTy 
) const
inlinevirtual

Return true if a truncation from FromTy to ToTy is permitted when deciding whether a call is in tail position.

Typically this means that both results would be assigned to the same register or stack slot, but it could mean the target performs adequate checks of its own before proceeding with the tail call. Targets must return false when FromTy <= ToTy.

Reimplemented in llvm::X86TargetLowering, llvm::SystemZTargetLowering, llvm::ARMTargetLowering, and llvm::HexagonTargetLowering.

Definition at line 1974 of file TargetLowering.h.

Referenced by getNoopInput().

◆ areJTsAllowed()

bool llvm::TargetLoweringBase::areJTsAllowed ( const Function Fn) const
inline

◆ canCombineStoreAndExtract()

virtual bool llvm::TargetLoweringBase::canCombineStoreAndExtract ( Type VectorTy,
Value Idx,
unsigned Cost 
) const
inlinevirtual

Return true if the target can combine store(extractelement VectorTy, Idx).

Cost[out] gives the cost of that transformation when this is true.

Reimplemented in llvm::ARMTargetLowering.

Definition at line 518 of file TargetLowering.h.

Referenced by isBroadcastShuffle().

◆ canMergeStoresTo()

virtual bool llvm::TargetLoweringBase::canMergeStoresTo ( unsigned  AS,
EVT  MemVT,
const SelectionDAG DAG 
) const
inlinevirtual

Returns if it's reasonable to merge stores to MemVT size.

Reimplemented in llvm::X86TargetLowering, llvm::ARMTargetLowering, llvm::AArch64TargetLowering, llvm::SITargetLowering, and llvm::R600TargetLowering.

Definition at line 419 of file TargetLowering.h.

Referenced by peekThroughBitcast().

◆ canOpTrap()

bool TargetLoweringBase::canOpTrap ( unsigned  Op,
EVT  VT 
) const
virtual

Returns true if the operation can trap for the value type.

VT must be a legal type. By default, we optimistically assume most operations don't trap except for integer divide and remainder.

Definition at line 654 of file TargetLoweringBase.cpp.

References assert(), isTypeLegal(), llvm::ISD::SDIV, llvm::ISD::SREM, llvm::ISD::UDIV, and llvm::ISD::UREM.

◆ computeRegisterProperties()

void TargetLoweringBase::computeRegisterProperties ( const TargetRegisterInfo TRI)
protected

Once all of the register classes are added, this allows us to compute derived properties we expose.

computeRegisterProperties - Once all of the register classes are added, this allows us to compute derived properties we expose.

Definition at line 980 of file TargetLoweringBase.cpp.

References assert(), llvm::MVT::f128, llvm::MVT::f16, llvm::MVT::f32, llvm::MVT::f64, findRepresentativeClass(), llvm::MVT::FIRST_VECTOR_VALUETYPE, llvm::MVT::getPow2VectorType(), getPreferredVectorAction(), llvm::MVT::getScalarSizeInBits(), llvm::MVT::getSizeInBits(), llvm::MVT::getVectorElementType(), llvm::MVT::getVectorNumElements(), getVectorTypeBreakdownMVT(), llvm::MVT::i1, llvm::MVT::i128, llvm::MVT::i32, llvm::MVT::i64, isTypeLegal(), llvm::MVT::isVoid, llvm::MVT::LAST_INTEGER_VALUETYPE, llvm::MVT::LAST_INTEGER_VECTOR_VALUETYPE, llvm::MVT::LAST_VALUETYPE, llvm::MVT::LAST_VECTOR_VALUETYPE, LLVM_FALLTHROUGH, llvm_unreachable, llvm::MVT::MAX_ALLOWED_VALUETYPE, llvm::MVT::Other, llvm::MVT::ppcf128, llvm::MSP430ISD::RRC, llvm::TargetLoweringBase::ValueTypeActionImpl::setTypeAction(), TypeExpandFloat, TypeExpandInteger, TypePromoteFloat, TypePromoteInteger, TypeScalarizeVector, TypeSoftenFloat, TypeSplitVector, TypeWidenVector, and ValueTypeActions.

Referenced by llvm::AArch64TargetLowering::AArch64TargetLowering(), llvm::ARCTargetLowering::ARCTargetLowering(), llvm::ARMTargetLowering::ARMTargetLowering(), llvm::AVRTargetLowering::AVRTargetLowering(), llvm::BPFTargetLowering::BPFTargetLowering(), llvm::HexagonTargetLowering::HexagonTargetLowering(), llvm::LanaiTargetLowering::LanaiTargetLowering(), llvm::Mips16TargetLowering::Mips16TargetLowering(), llvm::MipsSETargetLowering::MipsSETargetLowering(), llvm::MSP430TargetLowering::MSP430TargetLowering(), llvm::NVPTXTargetLowering::NVPTXTargetLowering(), llvm::PPCTargetLowering::PPCTargetLowering(), llvm::R600TargetLowering::R600TargetLowering(), llvm::RISCVTargetLowering::RISCVTargetLowering(), llvm::SITargetLowering::SITargetLowering(), llvm::SparcTargetLowering::SparcTargetLowering(), llvm::SystemZTargetLowering::SystemZTargetLowering(), llvm::WebAssemblyTargetLowering::WebAssemblyTargetLowering(), llvm::X86TargetLowering::X86TargetLowering(), and llvm::XCoreTargetLowering::XCoreTargetLowering().

◆ convertSelectOfConstantsToMath()

virtual bool llvm::TargetLoweringBase::convertSelectOfConstantsToMath ( EVT  VT) const
inlinevirtual

Return true if a select of constants (select Cond, C1, C2) should be transformed into simple math ops with the condition value.

For example: select Cond, C1, C1-1 –> add (zext Cond), C1-1

Reimplemented in llvm::X86TargetLowering, and llvm::PPCTargetLowering.

Definition at line 1594 of file TargetLowering.h.

Referenced by combineMinNumMaxNum(), ConvertSelectToConcatVector(), and ExtendUsesToFormExtLoad().

◆ convertSetCCLogicToBitwiseLogic()

virtual bool llvm::TargetLoweringBase::convertSetCCLogicToBitwiseLogic ( EVT  VT) const
inlinevirtual

Use bitwise logic to make pairs of compares more efficient.

For example: and (seteq A, B), (seteq C, D) –> seteq (or (xor A, B), (xor C, D)), 0 This should be true when it takes more than one instruction to lower setcc (cmp+set on x86 scalar), when bitwise ops are faster than logic on condition bits (crand on PowerPC), and/or when reducing cmp+br is a win.

Reimplemented in llvm::X86TargetLowering, llvm::PPCTargetLowering, and llvm::ARMTargetLowering.

Definition at line 472 of file TargetLowering.h.

Referenced by simplifyDivRem().

◆ emitAtomicCmpXchgNoStoreLLBalance()

virtual void llvm::TargetLoweringBase::emitAtomicCmpXchgNoStoreLLBalance ( IRBuilder<> &  Builder) const
inlinevirtual

Reimplemented in llvm::ARMTargetLowering, and llvm::AArch64TargetLowering.

Definition at line 1517 of file TargetLowering.h.

◆ emitLeadingFence()

virtual Instruction* llvm::TargetLoweringBase::emitLeadingFence ( IRBuilder<> &  Builder,
Instruction Inst,
AtomicOrdering  Ord 
) const
inlinevirtual

Inserts in the IR a target-specific intrinsic specifying a fence.

It is called by AtomicExpandPass before expanding an AtomicRMW/AtomicCmpXchg/AtomicStore/AtomicLoad if shouldInsertFencesForAtomic returns true.

Inst is the original atomic instruction, prior to other expansions that may be performed.

This function should either return a nullptr, or a pointer to an IR-level Instruction*. Even complex fence sequences can be represented by a single Instruction* through an intrinsic to be lowered later. Backends should override this method to produce target-specific intrinsic for their fences. FIXME: Please note that the default implementation here in terms of IR-level fences exists for historical/compatibility reasons and is unsound ! Fences cannot, in general, be used to restore sequential consistency. For example, consider the following example: atomic<int> x = y = 0; int r1, r2, r3, r4; Thread 0: x.store(1); Thread 1: y.store(1); Thread 2: r1 = x.load(); r2 = y.load(); Thread 3: r3 = y.load(); r4 = x.load(); r1 = r3 = 1 and r2 = r4 = 0 is impossible as long as the accesses are all seq_cst. But if they are lowered to monotonic accesses, no amount of IR-level fences can prevent it.

Reimplemented in llvm::PPCTargetLowering, and llvm::ARMTargetLowering.

Definition at line 1493 of file TargetLowering.h.

References llvm::IRBuilder< T, Inserter >::CreateFence(), llvm::Instruction::hasAtomicStore(), and llvm::isReleaseOrStronger().

◆ emitLoadLinked()

virtual Value* llvm::TargetLoweringBase::emitLoadLinked ( IRBuilder<> &  Builder,
Value Addr,
AtomicOrdering  Ord 
) const
inlinevirtual

Perform a load-linked operation on Addr, returning a "Value *" with the corresponding pointee type.

This may entail some non-trivial operations to truncate or reconstruct types that will be illegal in the backend. See ARMISelLowering for an example implementation.

Reimplemented in llvm::ARMTargetLowering, llvm::AArch64TargetLowering, and llvm::HexagonTargetLowering.

Definition at line 1448 of file TargetLowering.h.

References llvm_unreachable.

◆ emitPatchPoint()

MachineBasicBlock * TargetLoweringBase::emitPatchPoint ( MachineInstr InitialMI,
MachineBasicBlock MBB 
) const
protected

Replace/modify any TargetFrameIndex operands with a targte-dependent sequence of memory operands that is recognized by PrologEpilogInserter.

Definition at line 866 of file TargetLoweringBase.cpp.

References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstr::addMemOperand(), assert(), llvm::BuildMI(), llvm::MachineInstr::eraseFromParent(), llvm::MachineFunction::getDataLayout(), llvm::MachineInstr::getDebugLoc(), llvm::MachineInstr::getDesc(), llvm::MachinePointerInfo::getFixedStack(), llvm::MachineFunction::getFrameInfo(), llvm::MachineOperand::getIndex(), llvm::MachineFunction::getMachineMemOperand(), llvm::MachineInstr::getMF(), llvm::MachineInstr::getNumOperands(), llvm::MachineFrameInfo::getObjectAlignment(), llvm::MachineFrameInfo::getObjectOffset(), llvm::MachineFrameInfo::getObjectSize(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::DataLayout::getPointerSize(), llvm::MachineBasicBlock::insert(), llvm::MachineOperand::isFI(), llvm::MachineFrameInfo::isStatepointSpillSlotObjectIndex(), llvm::MachineInstr::mayLoad(), llvm::MachineInstr::memoperands_begin(), llvm::MachineInstr::memoperands_end(), MI, llvm::MachineMemOperand::MOLoad, llvm::MachineMemOperand::MOStore, llvm::MachineMemOperand::MOVolatile, and llvm::MachineInstr::setMemRefs().

Referenced by llvm::AArch64TargetLowering::EmitInstrWithCustomInserter(), llvm::PPCTargetLowering::EmitInstrWithCustomInserter(), and llvm::X86TargetLowering::EmitInstrWithCustomInserter().

◆ emitStoreConditional()

virtual Value* llvm::TargetLoweringBase::emitStoreConditional ( IRBuilder<> &  Builder,
Value Val,
Value Addr,
AtomicOrdering  Ord 
) const
inlinevirtual

Perform a store-conditional operation to Addr.

Return the status of the store. This should be 0 if the store succeeded, non-zero otherwise.

Reimplemented in llvm::ARMTargetLowering, llvm::AArch64TargetLowering, and llvm::HexagonTargetLowering.

Definition at line 1455 of file TargetLowering.h.

References llvm_unreachable.

◆ emitTrailingFence()

virtual Instruction* llvm::TargetLoweringBase::emitTrailingFence ( IRBuilder<> &  Builder,
Instruction Inst,
AtomicOrdering  Ord 
) const
inlinevirtual

◆ enableAggressiveFMAFusion()

virtual bool llvm::TargetLoweringBase::enableAggressiveFMAFusion ( EVT  VT) const
inlinevirtual

Return true if target always beneficiates from combining into FMA for a given value type.

This must typically return false on targets where FMA takes more cycles to execute than FADD.

Reimplemented in llvm::PPCTargetLowering, llvm::NVPTXTargetLowering, and llvm::SITargetLowering.

Definition at line 531 of file TargetLowering.h.

References Context.

Referenced by isContractable().

◆ enableExtLdPromotion()

bool llvm::TargetLoweringBase::enableExtLdPromotion ( ) const
inline

Return true if the target wants to use the optimization that turns ext(promotableInst1(...(promotableInstN(load)))) into promotedInst1(...(promotedInstN(ext(load)))).

Definition at line 513 of file TargetLowering.h.

Referenced by hasSameExtUse().

◆ finalizeLowering()

void TargetLoweringBase::finalizeLowering ( MachineFunction MF) const
virtual

Execute target specific actions to finalize target lowering.

This is used to set extra flags in MachineFrameInformation and freezing the set of reserved registers. The default implementation just freezes the set of reserved registers.

Reimplemented in llvm::X86TargetLowering, llvm::ARMTargetLowering, and llvm::SITargetLowering.

Definition at line 1771 of file TargetLoweringBase.cpp.

References llvm::MachineRegisterInfo::freezeReservedRegs(), and llvm::MachineFunction::getRegInfo().

Referenced by llvm::SITargetLowering::finalizeLowering(), llvm::ARMTargetLowering::finalizeLowering(), llvm::X86TargetLowering::finalizeLowering(), and llvm::SelectionDAGISel::runOnMachineFunction().

◆ findRepresentativeClass()

std::pair< const TargetRegisterClass *, uint8_t > TargetLoweringBase::findRepresentativeClass ( const TargetRegisterInfo TRI,
MVT  VT 
) const
protectedvirtual

Return the largest legal super-reg register class of the register class for the specified type and its associated "cost".

findRepresentativeClass - Return the largest legal super-reg register class of the register class for the specified type and its associated "cost".

Reimplemented in llvm::X86TargetLowering, llvm::ARMTargetLowering, and llvm::HexagonTargetLowering.

Definition at line 953 of file TargetLoweringBase.cpp.

References llvm::TargetRegisterInfo::getNumRegClasses(), llvm::TargetRegisterInfo::getRegClass(), llvm::TargetRegisterInfo::getSpillSize(), isLegalRC(), llvm::SuperRegClassIterator::isValid(), llvm::BitVector::setBitsInMask(), and llvm::MVT::SimpleTy.

Referenced by computeRegisterProperties(), llvm::HexagonTargetLowering::findRepresentativeClass(), llvm::ARMTargetLowering::findRepresentativeClass(), and llvm::X86TargetLowering::findRepresentativeClass().

◆ getABIAlignmentForCallingConv()

virtual unsigned llvm::TargetLoweringBase::getABIAlignmentForCallingConv ( Type ArgTy,
DataLayout  DL 
) const
inlinevirtual

Certain targets have context senstive alignment requirements, where one type has the alignment requirement of another type.

Reimplemented in llvm::MipsTargetLowering.

Definition at line 1130 of file TargetLowering.h.

References llvm::DataLayout::getABITypeAlignment().

◆ getAddrModeArguments()

virtual bool llvm::TargetLoweringBase::getAddrModeArguments ( IntrinsicInst ,
SmallVectorImpl< Value *> &  ,
Type *&   
) const
inlinevirtual

CodeGenPrepare sinks address calculations into the same BB as Load/Store instructions reading the address.

This allows as much computation as possible to be done in the address mode for that operand. This hook lets targets also pass back when this should be done on intrinsics which load/store.

Reimplemented in llvm::SITargetLowering.

Definition at line 1857 of file TargetLowering.h.

◆ getBooleanContents() [1/2]

BooleanContent llvm::TargetLoweringBase::getBooleanContents ( bool  isVec,
bool  isFloat 
) const
inline

For targets without i1 registers, this gives the nature of the high-bits of boolean values held in types wider than i1.

"Boolean values" are special true/false values produced by nodes like SETCC and consumed (as the condition) by nodes like SELECT and BRCOND. Not to be confused with general values promoted from i1. Some cpus distinguish between vectors of boolean and scalars; the isVec parameter selects between the two kinds. For example on X86 a scalar boolean should be zero extended from i1, while the elements of a vector of booleans should be sign extended from i1.

Some cpus also treat floating point types the same way as they treat vectors instead of the way they treat scalars.

Definition at line 558 of file TargetLowering.h.

Referenced by calculateByteProvider(), combineMinNumMaxNum(), combineShuffleOfSplat(), llvm::SelectionDAG::computeKnownBits(), llvm::SelectionDAG::ComputeNumSignBits(), createBSWAPShuffleMask(), ExtendUsesToFormExtLoad(), llvm::SelectionDAG::FoldSetCC(), getAsCarry(), llvm::SelectionDAG::getBoolExtOrTrunc(), llvm::TargetLowering::getConstTrueVal(), getExpandedMinMaxOps(), llvm::SelectionDAG::getLogicalNOT(), llvm::TargetLowering::isConstFalseVal(), llvm::TargetLowering::isConstTrueVal(), llvm::TargetLowering::isExtendedTrueVal(), llvm::TargetLowering::SimplifyDemandedBits(), llvm::TargetLowering::SimplifySetCC(), llvm::LegalizerHelper::widenScalar(), and zeroExtendToMatch().

◆ getBooleanContents() [2/2]

BooleanContent llvm::TargetLoweringBase::getBooleanContents ( EVT  Type) const
inline

Definition at line 564 of file TargetLowering.h.

References llvm::EVT::isFloatingPoint(), and llvm::EVT::isVector().

◆ getBypassSlowDivWidths()

const DenseMap<unsigned int, unsigned int>& llvm::TargetLoweringBase::getBypassSlowDivWidths ( ) const
inline

Returns map of slow types for division or remainder with corresponding fast types.

Definition at line 355 of file TargetLowering.h.

◆ getByValTypeAlignment()

unsigned TargetLoweringBase::getByValTypeAlignment ( Type Ty,
const DataLayout DL 
) const
virtual

Return the desired alignment for ByVal or InAlloca aggregate function arguments in the caller parameter area.

getByValTypeAlignment - Return the desired alignment for ByVal aggregate function arguments in the caller parameter area.

This is the actual alignment, not its logarithm.

Reimplemented in llvm::PPCTargetLowering, and llvm::X86TargetLowering.

Definition at line 1311 of file TargetLoweringBase.cpp.

References llvm::DataLayout::getABITypeAlignment().

Referenced by llvm::FastISel::lowerCallTo(), and llvm::CallLowering::setArgFlags().

◆ getCmpLibcallCC()

ISD::CondCode llvm::TargetLoweringBase::getCmpLibcallCC ( RTLIB::Libcall  Call) const
inline

Get the CondCode that's to be used to test the result of the comparison libcall against zero.

Definition at line 2223 of file TargetLowering.h.

Referenced by llvm::TargetLowering::softenSetCCOperands().

◆ getCmpLibcallReturnType()

MVT::SimpleValueType TargetLoweringBase::getCmpLibcallReturnType ( ) const
virtual

Return the ValueType for comparison libcalls.

Comparions libcalls include floating point comparion calls, and Ordered/Unordered check calls on floating point numbers.

Reimplemented in llvm::AVRTargetLowering.

Definition at line 1179 of file TargetLoweringBase.cpp.

References llvm::MVT::i32.

Referenced by llvm::TargetLowering::softenSetCCOperands().

◆ getCondCodeAction()

LegalizeAction llvm::TargetLoweringBase::getCondCodeAction ( ISD::CondCode  CC,
MVT  VT 
) const
inline

Return how the condition code should be treated: either it is legal, needs to be expanded to some other code sequence, or the target has a custom expander for it.

Definition at line 973 of file TargetLowering.h.

References llvm::array_lengthof(), assert(), and llvm::MVT::SimpleTy.

Referenced by llvm::TargetLowering::SimplifySetCC().

◆ getDefaultSafeStackPointerLocation()

Value * TargetLoweringBase::getDefaultSafeStackPointerLocation ( IRBuilder<> &  IRB,
bool  UseTLS 
) const
protected

◆ getDivRefinementSteps()

int TargetLoweringBase::getDivRefinementSteps ( EVT  VT,
MachineFunction MF 
) const

Return the refinement step count for a division of the given type based on the function's attributes.

If the operation is not overridden by the function's attributes, "Unspecified" is returned and target defaults are expected to be used for instruction selection.

Definition at line 1766 of file TargetLoweringBase.cpp.

References getOpRefinementSteps(), and getRecipEstimateForFunc().

Referenced by combineShuffleOfSplat().

◆ getExceptionPointerRegister()

virtual unsigned llvm::TargetLoweringBase::getExceptionPointerRegister ( const Constant PersonalityFn) const
inlinevirtual

◆ getExceptionSelectorRegister()

virtual unsigned llvm::TargetLoweringBase::getExceptionSelectorRegister ( const Constant PersonalityFn) const
inlinevirtual

◆ getExtendForAtomicOps()

virtual ISD::NodeType llvm::TargetLoweringBase::getExtendForAtomicOps ( ) const
inlinevirtual

Returns how the platform's atomic operations are extended (ZERO_EXTEND, SIGN_EXTEND, or ANY_EXTEND).

Reimplemented in llvm::SystemZTargetLowering, and llvm::MipsTargetLowering.

Definition at line 1567 of file TargetLowering.h.

References llvm::ISD::ZERO_EXTEND.

◆ getExtendForContent()

static ISD::NodeType llvm::TargetLoweringBase::getExtendForContent ( BooleanContent  Content)
inlinestatic

◆ getFenceOperandTy()

virtual MVT llvm::TargetLoweringBase::getFenceOperandTy ( const DataLayout DL) const
inlinevirtual

Return the type for operands of fence.

TODO: Let fence operands be of i32 type and remove this.

Reimplemented in llvm::AMDGPUTargetLowering.

Definition at line 248 of file TargetLowering.h.

Referenced by getUniformBase().

◆ getFrameIndexTy()

MVT llvm::TargetLoweringBase::getFrameIndexTy ( const DataLayout DL) const
inline

Return the type for frame index, which is determined by the alloca address space specified through the data layout.

Definition at line 242 of file TargetLowering.h.

References llvm::DataLayout::getAllocaAddrSpace().

Referenced by addStackMapLiveVars(), llvm::SelectionDAG::CreateStackTemporary(), getAddressForMemoryInput(), llvm::SelectionDAGBuilder::getFrameIndexTy(), getUnderlyingArgReg(), and llvm::SelectionDAGBuilder::getValueImpl().

◆ getGatherAllAliasesMaxDepth()

unsigned llvm::TargetLoweringBase::getGatherAllAliasesMaxDepth ( ) const
inline

Definition at line 1164 of file TargetLowering.h.

Referenced by findBaseOffset().

◆ getIndexedLoadAction()

LegalizeAction llvm::TargetLoweringBase::getIndexedLoadAction ( unsigned  IdxMode,
MVT  VT 
) const
inline

Return how the indexed load should be treated: either it is legal, needs to be promoted to a larger size, needs to be expanded to some other code sequence, or the target has a custom expander for it.

Definition at line 937 of file TargetLowering.h.

References assert(), llvm::MVT::isValid(), llvm::ISD::LAST_INDEXED_MODE, and llvm::MVT::SimpleTy.

◆ getIndexedStoreAction()

LegalizeAction llvm::TargetLoweringBase::getIndexedStoreAction ( unsigned  IdxMode,
MVT  VT 
) const
inline

Return how the indexed store should be treated: either it is legal, needs to be promoted to a larger size, needs to be expanded to some other code sequence, or the target has a custom expander for it.

Definition at line 955 of file TargetLowering.h.

References assert(), llvm::MVT::isValid(), llvm::ISD::LAST_INDEXED_MODE, and llvm::MVT::SimpleTy.

◆ getIRStackGuard()

Value * TargetLoweringBase::getIRStackGuard ( IRBuilder<> &  IRB) const
virtual

If the target has a standard location for the stack protector guard, returns the address of that location.

Otherwise, returns nullptr. DEPRECATED: please override useLoadStackGuardNode and customize LOAD_STACK_GUARD, or customize .stackguard().

Reimplemented in llvm::X86TargetLowering, and llvm::AArch64TargetLowering.

Definition at line 1542 of file TargetLoweringBase.cpp.

References llvm::Module::getContext(), llvm::IRBuilderBase::GetInsertBlock(), llvm::Type::getInt8PtrTy(), llvm::Module::getOrInsertGlobal(), llvm::BasicBlock::getParent(), llvm::GlobalValue::getParent(), and getTargetMachine().

Referenced by llvm::AArch64TargetLowering::getIRStackGuard(), llvm::X86TargetLowering::getIRStackGuard(), and getStackGuard().

◆ getJumpBufAlignment()

unsigned llvm::TargetLoweringBase::getJumpBufAlignment ( ) const
inline

Returns the target's jmp_buf alignment in bytes (if never set, the default is 0)

Definition at line 1324 of file TargetLowering.h.

Referenced by llvm::BasicTTIImplBase< AMDGPUTTIImpl >::getJumpBufAlignment().

◆ getJumpBufSize()

unsigned llvm::TargetLoweringBase::getJumpBufSize ( ) const
inline

Returns the target's jmp_buf size in bytes (if never set, the default is 200)

Definition at line 1318 of file TargetLowering.h.

Referenced by llvm::BasicTTIImplBase< AMDGPUTTIImpl >::getJumpBufSize().

◆ getLibcallCallingConv()

CallingConv::ID llvm::TargetLoweringBase::getLibcallCallingConv ( RTLIB::Libcall  Call) const
inline

◆ getLibcallName()

const char* llvm::TargetLoweringBase::getLibcallName ( RTLIB::Libcall  Call) const
inline

◆ getLoadExtAction()

LegalizeAction llvm::TargetLoweringBase::getLoadExtAction ( unsigned  ExtType,
EVT  ValVT,
EVT  MemVT 
) const
inline

Return how this load with extension should be treated: either it is legal, needs to be promoted to a larger size, needs to be expanded to some other code sequence, or the target has a custom expander for it.

Definition at line 884 of file TargetLowering.h.

References assert(), llvm::EVT::getSimpleVT(), llvm::EVT::isExtended(), llvm::ISD::LAST_LOADEXT_TYPE, llvm::MVT::LAST_VALUETYPE, and llvm::MVT::SimpleTy.

Referenced by llvm::BasicTTIImplBase< AMDGPUTTIImpl >::getMemoryOpCost().

◆ getMaxAtomicSizeInBitsSupported()

unsigned llvm::TargetLoweringBase::getMaxAtomicSizeInBitsSupported ( ) const
inline

Returns the maximum atomic operation size (in bits) supported by the backend.

Atomic operations greater than this size (as well as ones that are not naturally aligned), will be expanded by AtomicExpandPass into an __atomic_* library call.

Definition at line 1424 of file TargetLowering.h.

Referenced by atomicSizeSupported().

◆ getMaxExpandSizeMemcmp()

unsigned llvm::TargetLoweringBase::getMaxExpandSizeMemcmp ( bool  OptSize) const
inline

Get maximum # of load operations permitted for memcmp.

This function returns the maximum number of load operations permitted to replace a call to memcmp. The value is set by the target at the performance threshold for such a replacement. If OptSize is true, return the limit for functions that have OptSize attribute.

Definition at line 1199 of file TargetLowering.h.

◆ getMaximumJumpTableSize()

unsigned TargetLoweringBase::getMaximumJumpTableSize ( ) const

Return upper limit for number of entries in a jump table.

Zero if no limit.

Definition at line 1579 of file TargetLoweringBase.cpp.

References MaximumJumpTableSize.

Referenced by llvm::AArch64TargetLowering::AArch64TargetLowering().

◆ getMaxStoresPerMemcpy()

unsigned llvm::TargetLoweringBase::getMaxStoresPerMemcpy ( bool  OptSize) const
inline

Get maximum # of store operations permitted for llvm.memcpy.

This function returns the maximum number of store operations permitted to replace a call to llvm.memcpy. The value is set by the target at the performance threshold for such a replacement. If OptSize is true, return the limit for functions that have OptSize attribute.

Definition at line 1189 of file TargetLowering.h.

Referenced by getMemcpyLoadsAndStores().

◆ getMaxStoresPerMemmove()

unsigned llvm::TargetLoweringBase::getMaxStoresPerMemmove ( bool  OptSize) const
inline

Get maximum # of store operations permitted for llvm.memmove.

This function returns the maximum number of store operations permitted to replace a call to llvm.memmove. The value is set by the target at the performance threshold for such a replacement. If OptSize is true, return the limit for functions that have OptSize attribute.

Definition at line 1209 of file TargetLowering.h.

Referenced by getMemmoveLoadsAndStores().

◆ getMaxStoresPerMemset()

unsigned llvm::TargetLoweringBase::getMaxStoresPerMemset ( bool  OptSize) const
inline

Get maximum # of store operations permitted for llvm.memset.

This function returns the maximum number of store operations permitted to replace a call to llvm.memset. The value is set by the target at the performance threshold for such a replacement. If OptSize is true, return the limit for functions that have OptSize attribute.

Definition at line 1179 of file TargetLowering.h.

Referenced by getMemsetStores().

◆ getMaxSupportedInterleaveFactor()

virtual unsigned llvm::TargetLoweringBase::getMaxSupportedInterleaveFactor ( ) const
inlinevirtual

Get the maximum supported factor for interleaved memory accesses.

Default to be the minimum interleave factor: 2.

Reimplemented in llvm::X86TargetLowering, llvm::ARMTargetLowering, and llvm::AArch64TargetLowering.

Definition at line 2087 of file TargetLowering.h.

◆ getMinCmpXchgSizeInBits()

unsigned llvm::TargetLoweringBase::getMinCmpXchgSizeInBits ( ) const
inline

Returns the size of the smallest cmpxchg or ll/sc instruction the backend supports.

Any smaller operations are widened in AtomicExpandPass.

Note that unlike operations above the maximum size, atomic ops are still natively supported below the minimum; they just require a more complex expansion.

Definition at line 1435 of file TargetLowering.h.

◆ getMinFunctionAlignment()

unsigned llvm::TargetLoweringBase::getMinFunctionAlignment ( ) const
inline

Return the minimum function alignment.

Definition at line 1334 of file TargetLowering.h.

Referenced by llvm::MachineFunction::MachineFunction().

◆ getMinimumJumpTableDensity()

unsigned TargetLoweringBase::getMinimumJumpTableDensity ( bool  OptForSize) const

Return lower limit of the density in a jump table.

Definition at line 1575 of file TargetLoweringBase.cpp.

References JumpTableDensity, and OptsizeJumpTableDensity.

◆ getMinimumJumpTableEntries()

unsigned TargetLoweringBase::getMinimumJumpTableEntries ( ) const

Return lower limit for number of blocks in a jump table.

Definition at line 1567 of file TargetLoweringBase.cpp.

References MinimumJumpTableEntries.

Referenced by tryToElideArgumentCopy().

◆ getMinStackArgumentAlignment()

unsigned llvm::TargetLoweringBase::getMinStackArgumentAlignment ( ) const
inline

Return the minimum stack alignment of an argument.

Definition at line 1329 of file TargetLowering.h.

Referenced by llvm::MipsTargetLowering::EmitInstrWithCustomInserter(), and llvm::SelectionDAG::expandVAArg().

◆ getNumRegisters()

unsigned llvm::TargetLoweringBase::getNumRegisters ( LLVMContext Context,
EVT  VT 
) const
inline

Return the number of registers that this ValueType will eventually require.

This is one for any types promoted to live in larger registers, but may be more than one for types (like i64) that are split into pieces. For types like i140, which are first promoted then expanded, it is the number of registers needed to hold all the bits of the original type. For an i140 on a 32 bit machine this means 5 registers.

Definition at line 1088 of file TargetLowering.h.

References llvm::array_lengthof(), assert(), llvm::EVT::getSimpleVT(), llvm::EVT::getSizeInBits(), llvm::EVT::isInteger(), llvm::EVT::isSimple(), llvm::EVT::isVector(), llvm_unreachable, and llvm::MVT::SimpleTy.

Referenced by llvm::RegsForValue::AddInlineAsmOperands(), llvm::AMDGPUTargetLowering::analyzeFormalArgumentsCompute(), llvm::FunctionLoweringInfo::ComputePHILiveOutRegInfo(), llvm::FunctionLoweringInfo::CreateRegs(), llvm::MipsTargetLowering::getNumRegistersForCallingConv(), GetRegistersForValue(), llvm::FastISel::lowerCallTo(), llvm::NVPTXTargetLowering::LowerFormalArguments(), llvm::RegsForValue::RegsForValue(), llvm::FastISel::selectExtractValue(), tryToElideArgumentCopy(), and llvm::X86CallLowering::X86CallLowering().

◆ getNumRegistersForCallingConv()

virtual unsigned llvm::TargetLoweringBase::getNumRegistersForCallingConv ( LLVMContext Context,
EVT  VT 
) const
inlinevirtual

Certain targets require unusual breakdowns of certain types.

For MIPS, this occurs when a vector type is used, as vector are passed through the integer register set.

Reimplemented in llvm::MipsTargetLowering.

Definition at line 1123 of file TargetLowering.h.

Referenced by findUnwindDestinations(), llvm::GetReturnInfo(), and llvm::RegsForValue::RegsForValue().

◆ getOperationAction()

LegalizeAction llvm::TargetLoweringBase::getOperationAction ( unsigned  Op,
EVT  VT 
) const
inline

Return how this operation should be treated: either it is legal, needs to be promoted to a larger size, needs to be expanded to some other code sequence, or the target has a custom expander for it.

Definition at line 758 of file TargetLowering.h.

References llvm::array_lengthof(), llvm::EVT::getSimpleVT(), llvm::EVT::isExtended(), and llvm::MVT::SimpleTy.

Referenced by combineShuffleOfSplat(), createBSWAPShuffleMask(), FoldIntToFPToInt(), getExpandedMinMaxOps(), getStrictFPOpcodeAction(), and llvm::SystemZTargetLowering::SystemZTargetLowering().

◆ getOptimalMemOpType()

virtual EVT llvm::TargetLoweringBase::getOptimalMemOpType ( uint64_t  ,
unsigned  ,
unsigned  ,
bool  ,
bool  ,
bool  ,
MachineFunction  
) const
inlinevirtual

Returns the target specific optimal type for load and store operations as a result of memset, memcpy, and memmove lowering.

If DstAlign is zero that means it's safe to destination alignment can satisfy any constraint. Similarly if SrcAlign is zero it means there isn't a need to check it against alignment requirement, probably because the source does not need to be loaded. If 'IsMemset' is true, that means it's expanding a memset. If 'ZeroMemset' is true, that means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy source is constant so it does not need to be loaded. It returns EVT::Other if the type should be determined using generic target-independent logic.

Reimplemented in llvm::PPCTargetLowering, llvm::X86TargetLowering, llvm::AArch64TargetLowering, llvm::ARMTargetLowering, llvm::HexagonTargetLowering, and llvm::SITargetLowering.

Definition at line 1248 of file TargetLowering.h.

References llvm::MVT::Other.

Referenced by FindOptimalMemOpLowering().

◆ getPointerTy()

MVT llvm::TargetLoweringBase::getPointerTy ( const DataLayout DL,
uint32_t  AS = 0 
) const
inline

Return the pointer type for the given address space, defaults to the pointer type from the data layout.

FIXME: The default needs to be removed once all the code is updated.

Definition at line 236 of file TargetLowering.h.

References AS, llvm::MVT::getIntegerVT(), and llvm::DataLayout::getPointerSizeInBits().

Referenced by AddCombineBUILD_VECTORToVPADDL(), AddCombineToVPADD(), AddCombineVUZPToVPADDL(), llvm::analyzeArguments(), AnalyzeReturnValues(), llvm::X86TargetLowering::BuildFILD(), CallingConvSupported(), CC_Lanai32_VarArg(), llvm::AArch64TargetLowering::CCAssignFnForReturn(), llvm::ARMTargetLowering::CCAssignFnForReturn(), CheckType(), CheckValueType(), combineExtractVectorElt(), combineShuffleOfSplat(), createPHIsForCMOVsInSinkBB(), createSwiftErrorEntriesInEntryBlock(), createVirtualRegs(), llvm::SparcTargetLowering::emitEHSjLjLongJmp(), llvm::PPCTargetLowering::emitEHSjLjLongJmp(), llvm::SparcTargetLowering::emitEHSjLjSetJmp(), llvm::PPCTargetLowering::emitEHSjLjSetJmp(), llvm::RISCVTargetLowering::EmitInstrWithCustomInserter(), llvm::MipsTargetLowering::EmitInstrWithCustomInserter(), llvm::X86TargetLowering::EmitInstrWithCustomInserter(), llvm::NVPTXAsmPrinter::emitLineNumberAsDotLoc(), llvm::HexagonSelectionDAGInfo::EmitTargetCodeForMemcpy(), llvm::XCoreSelectionDAGInfo::EmitTargetCodeForMemcpy(), llvm::AArch64SelectionDAGInfo::EmitTargetCodeForMemset(), llvm::X86SelectionDAGInfo::EmitTargetCodeForMemset(), EnsureStackAlignment(), expandf64Toi32(), llvm::SelectionDAG::expandVAArg(), llvm::SelectionDAG::expandVACopy(), findUnwindDestinations(), getAbsolute(), getAddressForMemoryInput(), getCopyFromParts(), getDivRemArgList(), getExpandedMinMaxOps(), GetExponent(), getIntOperandFromRegisterString(), llvm::SelectionDAG::getIntPtrConstant(), llvm::XCoreTargetLowering::getJumpTableEncoding(), llvm::ARMTargetLowering::getJumpTableEncoding(), getLimitedPrecisionExp2(), getLoadStackGuard(), getMemCmpLoad(), llvm::SelectionDAG::getMemcpy(), llvm::SelectionDAG::getMemmove(), llvm::SelectionDAG::getMemset(), getMOVL(), getNextIntArgReg(), getOpenCLAlignment(), llvm::MipsTargetLowering::getOpndList(), llvm::FunctionLoweringInfo::getOrCreateSwiftErrorVReg(), llvm::FunctionLoweringInfo::getOrCreateSwiftErrorVRegDefAt(), llvm::X86TargetLowering::getPICJumpTableRelocBase(), llvm::PPCTargetLowering::getPICJumpTableRelocBase(), llvm::TargetLowering::getPICJumpTableRelocBase(), llvm::PPCTargetLowering::getPICJumpTableRelocBaseExpr(), llvm::NVPTXTargetLowering::getPrototype(), llvm::FastISel::getRegForGEPIndex(), llvm::FastISel::getRegForValue(), llvm::MSP430TargetLowering::getReturnAddressFrameIndex(), llvm::X86TargetLowering::getReturnAddressFrameIndex(), llvm::AVRTargetLowering::getSetCCResultType(), llvm::ARMTargetLowering::getSetCCResultType(), getSetCCResultType(), llvm::ARCTargetLowering::getTargetNodeName(), llvm::NVPTXTargetLowering::getTgtMemIntrinsic(), getUnderlyingArgReg(), getUniformBase(), llvm::AArch64TargetLowering::getVaListSizeInBits(), llvm::SelectionDAGBuilder::getValueImpl(), getVectorCompareInfo(), llvm::TargetLowering::getVectorElementPointer(), hasExceptionPointerOrCodeUser(), hasOnlySelectUsers(), haveEfficientBuildVectorPattern(), llvm::intCCToAVRCC(), isADDADDMUL(), isBLACompatibleAddress(), llvm::PPCTargetLowering::isLegalAddressingMode(), llvm::ARMTargetLowering::isReadOnly(), IsSmallObject(), isSortedByValueNo(), llvm::SITargetLowering::isTypeDesirableForOp(), isWordAligned(), isWorthFoldingADDlow(), isXor1OfSetCC(), LowerADDC_ADDE_SUBC_SUBE(), LowerADJUST_TRAMPOLINE(), llvm::MSP430TargetLowering::LowerBlockAddress(), lowerBuildVectorAsBroadcast(), llvm::SystemZTargetLowering::LowerCall(), llvm::NVPTXTargetLowering::LowerCall(), llvm::SparcTargetLowering::LowerCall_32(), llvm::SparcTargetLowering::LowerCall_64(), LowerCallResult(), llvm::SelectionDAGBuilder::LowerCallTo(), llvm::HexagonTargetLowering::LowerEH_RETURN(), LowerExtendedLoad(), llvm::MSP430TargetLowering::LowerExternalSymbol(), llvm::SparcTargetLowering::LowerF128_LibCallArg(), llvm::SparcTargetLowering::LowerF128Compare(), llvm::SparcTargetLowering::LowerF128Op(), lowerFCOPYSIGN64(), llvm::SystemZTargetLowering::LowerFormalArguments(), llvm::NVPTXTargetLowering::LowerFormalArguments(), llvm::SparcTargetLowering::LowerFormalArguments_32(), llvm::SparcTargetLowering::LowerFormalArguments_64(), LowerFSINCOS(), llvm::LanaiTargetLowering::LowerGlobalAddress(), llvm::MSP430TargetLowering::LowerGlobalAddress(), llvm::NVPTXTargetLowering::LowerGlobalAddress(), llvm::SparcTargetLowering::LowerGlobalTLSAddress(), LowerINSERT_SUBVECTOR(), LowerINTRINSIC_W_CHAIN(), llvm::SparcTargetLowering::LowerINTRINSIC_WO_CHAIN(), llvm::LanaiTargetLowering::LowerJumpTable(), llvm::MSP430TargetLowering::LowerJumpTable(), LowerMemOpCallTo(), lowerMSABitClearImm(), LowerMUL(), LowerMULH(), llvm::R600TargetLowering::LowerOperation(), llvm::BPFTargetLowering::LowerOperation(), llvm::SparcTargetLowering::LowerReturn_32(), llvm::MSP430TargetLowering::LowerRETURNADDR(), LowerRETURNADDR(), LowerShiftParts(), llvm::TargetLowering::LowerToTLSEmulatedModel(), LowerToTLSExecModel(), lowerUINT_TO_FP_vXi32(), llvm::LanaiTargetLowering::LowerVASTART(), llvm::MSP430TargetLowering::LowerVASTART(), LowerVASTART(), LowerVectorINT_TO_FP(), llvm::SparcTargetLowering::makeAddress(), llvm::TargetLowering::makeLibCall(), mayTailCallThisCC(), llvm::X86TargetLowering::needsFixedCatchObjects(), parsePhysicalReg(), Passv64i1ArgInRegs(), llvm::PPCTargetLowering::PerformDAGCombine(), PerformSTORECombine(), PrepareCall(), propagateSwiftErrorVRegs(), recoverFramePointer(), llvm::R600TargetLowering::ReplaceNodeResults(), llvm::AVRDAGToDAGISel::SelectAddr(), llvm::PPCTargetLowering::SelectAddressRegImm(), llvm::SelectionDAGISel::SelectCodeCommon(), llvm::FastISel::selectGetElementPtr(), llvm::AVRDAGToDAGISel::selectIndexedLoad(), shouldGuaranteeTCO(), llvm::TargetLowering::SimplifySetCC(), tryToElideArgumentCopy(), UnpackFromArgumentSlot(), llvm::SelectionDAGBuilder::visitBitTestCase(), llvm::SelectionDAGBuilder::visitBitTestHeader(), llvm::SelectionDAGBuilder::visitJumpTable(), llvm::SelectionDAGBuilder::visitJumpTableHeader(), and llvm::SelectionDAGBuilder::visitSPDescriptorParent().

◆ getPredictableBranchThreshold()

BranchProbability TargetLoweringBase::getPredictableBranchThreshold ( ) const
virtual

If a branch or a select condition is skewed in one direction by more than this factor, it is very likely to be predicted correctly.

Definition at line 1338 of file TargetLoweringBase.cpp.

References MinPercentageForPredictableBranch.

Referenced by isFormingBranchFromSelectProfitable().

◆ getPreferredVectorAction()

virtual TargetLoweringBase::LegalizeTypeAction llvm::TargetLoweringBase::getPreferredVectorAction ( EVT  VT) const
inlinevirtual

◆ getPrefFunctionAlignment()

unsigned llvm::TargetLoweringBase::getPrefFunctionAlignment ( ) const
inline

Return the preferred function alignment.

Definition at line 1339 of file TargetLowering.h.

Referenced by llvm::MachineFunction::MachineFunction().

◆ getPrefLoopAlignment()

virtual unsigned llvm::TargetLoweringBase::getPrefLoopAlignment ( MachineLoop ML = nullptr) const
inlinevirtual

Return the preferred loop alignment.

Reimplemented in llvm::PPCTargetLowering.

Definition at line 1344 of file TargetLowering.h.

Referenced by getLayoutSuccessorProbThreshold(), and llvm::PPCTargetLowering::getPrefLoopAlignment().

◆ getRecipEstimateDivEnabled()

int TargetLoweringBase::getRecipEstimateDivEnabled ( EVT  VT,
MachineFunction MF 
) const

Return a ReciprocalEstimate enum value for a division of the given type based on the function's attributes.

If the operation is not overridden by the function's attributes, "Unspecified" is returned and target defaults are expected to be used for instruction selection.

Definition at line 1756 of file TargetLoweringBase.cpp.

References getOpEnabled(), and getRecipEstimateForFunc().

Referenced by combineShuffleOfSplat().

◆ getRecipEstimateSqrtEnabled()

int TargetLoweringBase::getRecipEstimateSqrtEnabled ( EVT  VT,
MachineFunction MF 
) const

Return a ReciprocalEstimate enum value for a square root of the given type based on the function's attributes.

If the operation is not overridden by the function's attributes, "Unspecified" is returned and target defaults are expected to be used for instruction selection.

Definition at line 1751 of file TargetLoweringBase.cpp.

References getOpEnabled(), and getRecipEstimateForFunc().

Referenced by combineShuffleOfSplat().

◆ getRegClassFor()

virtual const TargetRegisterClass* llvm::TargetLoweringBase::getRegClassFor ( MVT  VT) const
inlinevirtual

Return the register class that should be used for the specified value type.

Reimplemented in llvm::ARMTargetLowering.

Definition at line 582 of file TargetLowering.h.

References assert(), and llvm::MVT::SimpleTy.

Referenced by llvm::CCState::analyzeMustTailForwardedRegisters(), AnalyzeReturnValues(), CallingConvSupported(), canFoldInAddressingMode(), CC_Lanai32_VarArg(), countOperands(), createPHIsForCMOVsInSinkBB(), llvm::FunctionLoweringInfo::CreateReg(), createSwiftErrorEntriesInEntryBlock(), createVirtualRegs(), emitClzero(), llvm::PPCTargetLowering::emitEHSjLjSetJmp(), llvm::MipsTargetLowering::EmitInstrWithCustomInserter(), llvm::X86TargetLowering::EmitInstrWithCustomInserter(), llvm::FastISel::fastEmitInst_extractsubreg(), getComparePred(), llvm::FunctionLoweringInfo::getOrCreateSwiftErrorVReg(), llvm::FunctionLoweringInfo::getOrCreateSwiftErrorVRegDefAt(), llvm::ARMTargetLowering::getRegClassFor(), llvm::FastISel::getRegForValue(), getUnderlyingArgReg(), hasExceptionPointerOrCodeUser(), llvm::GenericScheduler::initPolicy(), isSortedByValueNo(), isXor1OfSetCC(), lowerFCOPYSIGN64(), llvm::SparcTargetLowering::LowerFormalArguments_64(), llvm::LanaiTargetLowering::LowerRETURNADDR(), LowerRETURNADDR(), parsePhysicalReg(), llvm::SITargetLowering::PostISelFolding(), propagateSwiftErrorVRegs(), llvm::ResourcePriorityQueue::rawRegPressureDelta(), llvm::ResourcePriorityQueue::ResourcePriorityQueue(), llvm::ResourcePriorityQueue::scheduledNode(), llvm::FastISel::selectBitCast(), llvm::FastISel::selectPatchpoint(), and UnpackFromArgumentSlot().

◆ getRegisterType() [1/2]

MVT llvm::TargetLoweringBase::getRegisterType ( MVT  VT) const
inline

◆ getRegisterType() [2/2]

MVT llvm::TargetLoweringBase::getRegisterType ( LLVMContext Context,
EVT  VT 
) const
inline

Return the type of registers that this ValueType will eventually require.

Definition at line 1060 of file TargetLowering.h.

References llvm::array_lengthof(), assert(), llvm::EVT::getSimpleVT(), llvm::EVT::isInteger(), llvm::EVT::isSimple(), llvm::EVT::isVector(), llvm_unreachable, and llvm::MVT::SimpleTy.

◆ getRegisterTypeForCallingConv() [1/2]

virtual MVT llvm::TargetLoweringBase::getRegisterTypeForCallingConv ( MVT  VT) const
inlinevirtual

Certain combinations of ABIs, Targets and features require that types are legal for some operations and not for other operations.

For MIPS all vector types must be passed through the integer register set.

Reimplemented in llvm::MipsTargetLowering.

Definition at line 1111 of file TargetLowering.h.

Referenced by findUnwindDestinations(), llvm::RegsForValue::getCopyFromRegs(), llvm::RegsForValue::getCopyToRegs(), llvm::GetReturnInfo(), and llvm::RegsForValue::RegsForValue().

◆ getRegisterTypeForCallingConv() [2/2]

virtual MVT llvm::TargetLoweringBase::getRegisterTypeForCallingConv ( LLVMContext Context,
EVT  VT 
) const
inlinevirtual

Reimplemented in llvm::MipsTargetLowering.

Definition at line 1115 of file TargetLowering.h.

◆ getRepRegClassCostFor()

virtual uint8_t llvm::TargetLoweringBase::getRepRegClassCostFor ( MVT  VT) const
inlinevirtual

Return the cost of the 'representative' register class for the specified value type.

Definition at line 602 of file TargetLowering.h.

References llvm::MVT::SimpleTy.

Referenced by GetCostForDef().

◆ getRepRegClassFor()

virtual const TargetRegisterClass* llvm::TargetLoweringBase::getRepRegClassFor ( MVT  VT) const
inlinevirtual

Return the 'representative' register class for the specified value type.

The 'representative' register class is the largest legal super-reg register class for the register class of the value type. For example, on i386 the rep register class for i8, i16, and i32 are GR32; while the rep register class is GR64 on x86_64.

Reimplemented in llvm::MipsSETargetLowering.

Definition at line 595 of file TargetLowering.h.

References llvm::MVT::SimpleTy.

Referenced by llvm::SystemZTargetLowering::EmitInstrWithCustomInserter(), GetCostForDef(), and llvm::MipsSETargetLowering::getRepRegClassFor().

◆ getSafeStackPointerLocation()

Value * TargetLoweringBase::getSafeStackPointerLocation ( IRBuilder<> &  IRB) const
virtual

◆ getScalarShiftAmountTy()

MVT TargetLoweringBase::getScalarShiftAmountTy ( const DataLayout DL,
EVT   
) const
virtual

◆ getScalingFactorCost()

virtual int llvm::TargetLoweringBase::getScalingFactorCost ( const DataLayout DL,
const AddrMode AM,
Type Ty,
unsigned  AS = 0 
) const
inlinevirtual

Return the cost of the scaling factor used in the addressing mode represented by AM for this target, for a load/store of the specified type.

If the AM is supported, the return value must be >= 0. If the AM is not supported, it returns a negative value. TODO: Handle pre/postinc as well. TODO: Remove default argument

Reimplemented in llvm::X86TargetLowering, llvm::AArch64TargetLowering, and llvm::ARMTargetLowering.

Definition at line 1899 of file TargetLowering.h.

References AS.

Referenced by llvm::BasicTTIImplBase< AMDGPUTTIImpl >::getScalingFactorCost().

◆ getSchedulingPreference() [1/2]

Sched::Preference llvm::TargetLoweringBase::getSchedulingPreference ( ) const
inline

Return target scheduling preference.

Definition at line 569 of file TargetLowering.h.

Referenced by llvm::createDefaultScheduler(), llvm::PPCTargetLowering::getSchedulingPreference(), and llvm::ScheduleDAGSDNodes::newSUnit().

◆ getSchedulingPreference() [2/2]

virtual Sched::Preference llvm::TargetLoweringBase::getSchedulingPreference ( SDNode ) const
inlinevirtual

Some scheduler, e.g.

hybrid, can switch to different scheduling heuristics for different nodes. This function returns the preference (or none) for the given node.

Reimplemented in llvm::PPCTargetLowering, and llvm::ARMTargetLowering.

Definition at line 576 of file TargetLowering.h.

References llvm::Sched::None.

◆ getSDagStackGuard()

Value * TargetLoweringBase::getSDagStackGuard ( const Module M) const
virtual

Return the variable that's previously inserted by insertSSPDeclarations, if any, otherwise return nullptr.

Should be used only when getIRStackGuard returns nullptr.

Reimplemented in llvm::X86TargetLowering.

Definition at line 1559 of file TargetLoweringBase.cpp.

References llvm::Module::getGlobalVariable().

Referenced by getLoadStackGuard(), llvm::X86TargetLowering::getSDagStackGuard(), getUnderlyingArgReg(), and llvm::SelectionDAGBuilder::visitSPDescriptorParent().

◆ getSetCCResultType()

EVT TargetLoweringBase::getSetCCResultType ( const DataLayout DL,
LLVMContext Context,
EVT  VT 
) const
virtual

◆ getShiftAmountTy()

EVT TargetLoweringBase::getShiftAmountTy ( EVT  LHSTy,
const DataLayout DL 
) const

◆ getSimpleValueType()

MVT llvm::TargetLoweringBase::getSimpleValueType ( const DataLayout DL,
Type Ty,
bool  AllowUnknown = false 
) const
inline

Return the MVT corresponding to this LLVM type. See getValueType.

Definition at line 1043 of file TargetLowering.h.

Referenced by createVirtualRegs(), and llvm::TargetLowering::ParseConstraints().

◆ getSqrtRefinementSteps()

int TargetLoweringBase::getSqrtRefinementSteps ( EVT  VT,
MachineFunction MF 
) const

Return the refinement step count for a square root of the given type based on the function's attributes.

If the operation is not overridden by the function's attributes, "Unspecified" is returned and target defaults are expected to be used for instruction selection.

Definition at line 1761 of file TargetLoweringBase.cpp.

References getOpRefinementSteps(), and getRecipEstimateForFunc().

Referenced by combineShuffleOfSplat().

◆ getSSPStackGuardCheck()

Value * TargetLoweringBase::getSSPStackGuardCheck ( const Module M) const
virtual

If the target has a standard stack protection check function that performs validation and error handling, returns the function.

Otherwise, returns nullptr. Must be previously inserted by insertSSPDeclarations. Should be used only when getIRStackGuard returns nullptr.

Reimplemented in llvm::X86TargetLowering.

Definition at line 1563 of file TargetLoweringBase.cpp.

Referenced by CreatePrologue(), llvm::X86TargetLowering::getSSPStackGuardCheck(), preassignSwiftErrorRegs(), and llvm::SelectionDAGBuilder::visitSPDescriptorParent().

◆ getStackPointerRegisterToSaveRestore()

unsigned llvm::TargetLoweringBase::getStackPointerRegisterToSaveRestore ( ) const
inline

◆ getStackProbeSymbolName()

virtual StringRef llvm::TargetLoweringBase::getStackProbeSymbolName ( MachineFunction MF) const
inlinevirtual

Returns the name of the symbol used to emit stack probes or the empty string if not applicable.

Reimplemented in llvm::X86TargetLowering.

Definition at line 1379 of file TargetLowering.h.

◆ getTargetMachine()

const TargetMachine& llvm::TargetLoweringBase::getTargetMachine ( ) const
inline

Definition at line 229 of file TargetLowering.h.

References llvm::SystemZISD::TM.

Referenced by llvm::analyzeArguments(), areCallingConvEligibleForTCO_64SVR4(), llvm::AArch64TTIImpl::areInlineCompatible(), llvm::ARMTTIImpl::areInlineCompatible(), llvm::X86TTIImpl::areInlineCompatible(), llvm::AMDGPUTTIImpl::areInlineCompatible(), llvm::ARMTargetLowering::ARMTargetLowering(), llvm::ARMTargetLowering::CCAssignFnForReturn(), llvm::MipsTargetLowering::EmitInstrWithCustomInserter(), emitPostSt(), emitRemovedIntrinsicError(), EmitVectorComparison(), EnsureStackAlignment(), expandf64Toi32(), llvm::SITargetLowering::finalizeLowering(), llvm::X86TargetLowering::findRepresentativeClass(), findUser(), FPCCToARMCC(), llvm::NVPTXTargetLowering::getDivF32Level(), getIRStackGuard(), llvm::ARMTargetLowering::getJumpTableEncoding(), llvm::TargetLowering::getJumpTableEncoding(), getMOVL(), llvm::PPCTargetLowering::getOptimalMemOpType(), llvm::PPCTargetLowering::getPICJumpTableRelocBase(), llvm::PPCTargetLowering::getPICJumpTableRelocBaseExpr(), llvm::AVRTargetLowering::getRegForInlineAsmConstraint(), llvm::isCopyMulResult(), llvm::X86TargetLowering::isLegalAddressingMode(), llvm::TargetLowering::isOffsetFoldingLegal(), llvm::SystemZSubtarget::isPC32DBLSymbol(), llvm::TargetLowering::isPositionIndependent(), llvm::AArch64TargetLowering::isProfitableToHoist(), llvm::ARMTargetLowering::isReadOnly(), IsSmallObject(), llvm::LanaiTargetLowering::LowerConstantPool(), llvm::AMDGPUTargetLowering::LowerFP_TO_FP16(), llvm::LanaiTargetLowering::LowerGlobalAddress(), llvm::SparcTargetLowering::LowerGlobalTLSAddress(), LowerINSERT_SUBVECTOR(), llvm::LanaiTargetLowering::LowerJumpTable(), llvm::SparcTargetLowering::makeAddress(), MatchingStackOffset(), llvm::AMDGPUTargetLowering::mayIgnoreSignedZero(), mayTailCallThisCC(), llvm::SITargetLowering::PerformDAGCombine(), PerformSETCCCombine(), PrepareCall(), llvm::AArch64TargetLowering::shouldExpandAtomicCmpXchgInIR(), llvm::ARMTargetLowering::shouldExpandAtomicCmpXchgInIR(), stripModuloOnShift(), llvm::NVPTXTargetLowering::usePrecSqrtF32(), and llvm::AArch64Subtarget::useSmallAddressing().

◆ getTgtMemIntrinsic()

virtual bool llvm::TargetLoweringBase::getTgtMemIntrinsic ( IntrinsicInfo ,
const CallInst ,
unsigned   
) const
inlinevirtual

Given an intrinsic, checks if on the target the intrinsic will need to map to a MemIntrinsicNode (touches memory).

If this is the case, it returns true and store the intrinsic information into the IntrinsicInfo that was passed to the function.

Reimplemented in llvm::X86TargetLowering, llvm::PPCTargetLowering, llvm::ARMTargetLowering, llvm::NVPTXTargetLowering, llvm::AArch64TargetLowering, and llvm::SITargetLowering.

Definition at line 721 of file TargetLowering.h.

Referenced by llvm::IRTranslator::getAnalysisUsage(), and getUniformBase().

◆ getTruncStoreAction()

LegalizeAction llvm::TargetLoweringBase::getTruncStoreAction ( EVT  ValVT,
EVT  MemVT 
) const
inline

Return how this store with truncation should be treated: either it is legal, needs to be promoted to a larger size, needs to be expanded to some other code sequence, or the target has a custom expander for it.

Definition at line 910 of file TargetLowering.h.

References assert(), llvm::EVT::getSimpleVT(), llvm::EVT::isExtended(), llvm::MVT::LAST_VALUETYPE, and llvm::MVT::SimpleTy.

Referenced by llvm::BasicTTIImplBase< AMDGPUTTIImpl >::getMemoryOpCost().

◆ getTypeAction() [1/2]

LegalizeTypeAction llvm::TargetLoweringBase::getTypeAction ( LLVMContext Context,
EVT  VT 
) const
inline

Return how we should legalize values of this type, either it is already legal (return 'Legal') or we need to promote it to a larger type (return 'Promote'), or we need to expand it into multiple registers of smaller integer type (return 'Expand').

'Custom' is not an option.

Definition at line 643 of file TargetLowering.h.

Referenced by ConvertSelectToConcatVector(), FindMemType(), llvm::BasicTTIImplBase< AMDGPUTTIImpl >::getCastInstrCost(), llvm::SelectionDAG::getConstant(), llvm::X86TargetLowering::getSetCCResultType(), getVectorTypeBreakdown(), isSETCCorConvertedSETCC(), OptimizeNoopCopyExpression(), peekThroughBitcast(), and tryUnmergingGEPsAcrossIndirectBr().

◆ getTypeAction() [2/2]

LegalizeTypeAction llvm::TargetLoweringBase::getTypeAction ( MVT  VT) const
inline

Definition at line 646 of file TargetLowering.h.

◆ getTypeLegalizationCost()

std::pair< int, MVT > TargetLoweringBase::getTypeLegalizationCost ( const DataLayout DL,
Type Ty 
) const

Estimate the cost of type-legalization and the legalized type.

Definition at line 1423 of file TargetLoweringBase.cpp.

References C, llvm::Type::getContext(), llvm::EVT::getSimpleVT(), getValueType(), TypeExpandInteger, TypeLegal, and TypeSplitVector.

Referenced by llvm::NVPTXTTIImpl::getArithmeticInstrCost(), llvm::X86TTIImpl::getArithmeticInstrCost(), llvm::AArch64TTIImpl::getArithmeticInstrCost(), llvm::AMDGPUTTIImpl::getArithmeticInstrCost(), llvm::ARMTTIImpl::getArithmeticInstrCost(), llvm::BasicTTIImplBase< AMDGPUTTIImpl >::getArithmeticInstrCost(), llvm::X86TTIImpl::getArithmeticReductionCost(), llvm::X86TTIImpl::getCastInstrCost(), llvm::ARMTTIImpl::getCastInstrCost(), llvm::BasicTTIImplBase< AMDGPUTTIImpl >::getCastInstrCost(), llvm::X86TTIImpl::getCmpSelInstrCost(), llvm::ARMTTIImpl::getCmpSelInstrCost(), llvm::BasicTTIImplBase< AMDGPUTTIImpl >::getCmpSelInstrCost(), llvm::AArch64TTIImpl::getExtractWithExtendCost(), llvm::PPCTTIImpl::getInterleavedMemoryOpCost(), llvm::BasicTTIImplBase< AMDGPUTTIImpl >::getInterleavedMemoryOpCost(), llvm::X86TTIImpl::getInterleavedMemoryOpCostAVX2(), llvm::X86TTIImpl::getInterleavedMemoryOpCostAVX512(), llvm::X86TTIImpl::getIntrinsicInstrCost(), llvm::BasicTTIImplBase< AMDGPUTTIImpl >::getIntrinsicInstrCost(), llvm::X86TTIImpl::getMaskedMemoryOpCost(), llvm::X86TTIImpl::getMemoryOpCost(), llvm::PPCTTIImpl::getMemoryOpCost(), llvm::AArch64TTIImpl::getMemoryOpCost(), llvm::ARMTTIImpl::getMemoryOpCost(), llvm::BasicTTIImplBase< AMDGPUTTIImpl >::getMemoryOpCost(), llvm::X86TTIImpl::getMinMaxReductionCost(), llvm::BasicTTIImplBase< AMDGPUTTIImpl >::getNumberOfParts(), llvm::AArch64TTIImpl::getPopcntSupport(), llvm::X86TTIImpl::getShuffleCost(), llvm::PPCTTIImpl::getShuffleCost(), llvm::ARMTTIImpl::getShuffleCost(), llvm::PPCTTIImpl::getUserCost(), llvm::X86TTIImpl::getUserCost(), llvm::X86TTIImpl::getVectorInstrCost(), llvm::AArch64TTIImpl::getVectorInstrCost(), and llvm::BasicTTIImplBase< AMDGPUTTIImpl >::getVectorInstrCost().

◆ getTypeToExpandTo()

EVT llvm::TargetLoweringBase::getTypeToExpandTo ( LLVMContext Context,
EVT  VT 
) const
inline

For types supported by the target, this is an identity function.

For types that must be expanded (i.e. integer types that are larger than the largest integer register or illegal floating point types), this returns the largest legal type it will be expanded to.

Definition at line 664 of file TargetLowering.h.

References assert(), llvm::EVT::isVector(), and llvm_unreachable.

Referenced by getExpandedMinMaxOps().

◆ getTypeToPromoteTo()

MVT llvm::TargetLoweringBase::getTypeToPromoteTo ( unsigned  Op,
MVT  VT 
) const
inline

If the action for this operation is to promote, this method returns the ValueType to promote to.

Definition at line 994 of file TargetLowering.h.

References assert(), llvm::MVT::isFloatingPoint(), llvm::MVT::isInteger(), llvm::MVT::isVoid, and llvm::MVT::SimpleTy.

◆ getTypeToTransformTo()

EVT llvm::TargetLoweringBase::getTypeToTransformTo ( LLVMContext Context,
EVT  VT 
) const
inline

For types supported by the target, this is an identity function.

For types that must be promoted to larger types, this returns the larger type to promote to. For integer types that are larger than the largest integer register, this contains one step in the expansion to get to the smaller register. For illegal floating point types, this returns the integer type to transform to.

Definition at line 656 of file TargetLowering.h.

Referenced by BuildVectorFromScalar(), llvm::FunctionLoweringInfo::ComputePHILiveOutRegInfo(), llvm::SelectionDAG::FoldConstantArithmetic(), llvm::SelectionDAG::FoldConstantVectorArithmetic(), llvm::SelectionDAG::getConstant(), getExpandedMinMaxOps(), GetFPLibCall(), getMemcpyLoadsAndStores(), GetPromotionOpcode(), llvm::FastISel::getRegForValue(), llvm::X86TargetLowering::getSetCCResultType(), getVectorTypeBreakdown(), isNegativeOne(), isSETCCorConvertedSETCC(), OptimizeNoopCopyExpression(), peekThroughBitcast(), and llvm::FastISel::selectBinaryOp().

◆ getVaListSizeInBits()

virtual unsigned llvm::TargetLoweringBase::getVaListSizeInBits ( const DataLayout DL) const
inlinevirtual

Returns the size of the platform's va_list object.

Reimplemented in llvm::AArch64TargetLowering.

Definition at line 1169 of file TargetLowering.h.

◆ getValueType()

EVT llvm::TargetLoweringBase::getValueType ( const DataLayout DL,
Type Ty,
bool  AllowUnknown = false 
) const
inline

Return the EVT corresponding to this LLVM type.

This is fixed by the LLVM operations except for the pointer size. If AllowUnknown is true, this will return MVT::Other for types with no EVT counterpart (e.g. structs), otherwise it will assert.

Definition at line 1021 of file TargetLowering.h.

References llvm::Type::getContext(), llvm::SequentialType::getElementType(), llvm::EVT::getEVT(), llvm::SequentialType::getNumElements(), llvm::EVT::getTypeForEVT(), llvm::EVT::getVectorVT(), and llvm::Type::isVectorTy().

Referenced by addStackMapLiveVars(), llvm::AArch64TargetLowering::CCAssignFnForReturn(), CompactSwizzlableVector(), llvm::ComputeValueVTs(), createVirtualRegs(), detectAVGPattern(), llvm::FastISel::fastEmitZExtFromI1(), generateEquivalentSub(), llvm::AMDGPUTTIImpl::getArithmeticInstrCost(), llvm::X86TTIImpl::getCastInstrCost(), llvm::AArch64TTIImpl::getCastInstrCost(), llvm::ARMTTIImpl::getCastInstrCost(), llvm::BasicTTIImplBase< AMDGPUTTIImpl >::getCastInstrCost(), llvm::AArch64TTIImpl::getCmpSelInstrCost(), llvm::ARMTTIImpl::getCmpSelInstrCost(), getComparePred(), llvm::AArch64TTIImpl::getExtractWithExtendCost(), llvm::X86TTIImpl::getInterleavedMemoryOpCostAVX2(), llvm::X86TTIImpl::getMaskedMemoryOpCost(), getMemCmpLoad(), llvm::BasicTTIImplBase< AMDGPUTTIImpl >::getMemoryOpCost(), llvm::NVPTXTargetLowering::getPrototype(), llvm::FastISel::getRegForValue(), llvm::NVPTXTargetLowering::getTgtMemIntrinsic(), getTypeLegalizationCost(), getUnderlyingArgReg(), getUniformBase(), llvm::SelectionDAGBuilder::getValueImpl(), llvm::SystemZTTIImpl::hasDivRemOp(), llvm::X86TTIImpl::hasDivRemOp(), hasOnlySelectUsers(), hasSameExtUse(), llvm::BasicTTIImplBase< AMDGPUTTIImpl >::haveFastSqrt(), isBroadcastShuffle(), llvm::ARMTargetLowering::isLegalAddressingMode(), llvm::AArch64TargetLowering::isProfitableToHoist(), isPromotedInstructionLegal(), isSupportedType(), llvm::BasicTTIImplBase< AMDGPUTTIImpl >::isTypeLegal(), isVectorReductionOp(), llvm::AMDGPUCallLowering::lowerFormalArguments(), llvm::NVPTXTargetLowering::LowerFormalArguments(), LowerInterruptReturn(), makeBitReverse(), mayTailCallThisCC(), OptimizeExtractBits(), OptimizeNoopCopyExpression(), Passv64i1ArgInRegs(), llvm::AArch64TargetLowering::PerformDAGCombine(), llvm::FastISel::selectBitCast(), llvm::FastISel::selectCast(), llvm::FastISel::selectExtractValue(), llvm::FastISel::selectFNeg(), llvm::FastISel::selectOperator(), SinkShiftAndTruncate(), SubIdx2Lane(), and tryUnmergingGEPsAcrossIndirectBr().

◆ getValueTypeActions()

const ValueTypeActionImpl& llvm::TargetLoweringBase::getValueTypeActions ( ) const
inline

Definition at line 635 of file TargetLowering.h.

◆ getVectorIdxTy()

virtual MVT llvm::TargetLoweringBase::getVectorIdxTy ( const DataLayout DL) const
inlinevirtual

◆ getVectorTypeBreakdown()

unsigned TargetLoweringBase::getVectorTypeBreakdown ( LLVMContext Context,
EVT  VT,
EVT IntermediateVT,
unsigned NumIntermediates,
MVT RegisterVT 
) const

Vector types are broken down into some number of legal first class types.

getVectorTypeBreakdown - Vector types are broken down into some number of legal first class types.

For example, EVT::v8f32 maps to 2 EVT::v4f32 with Altivec or SSE1, or 8 promoted EVT::f64 values with the X86 FP stack. Similarly, EVT::v2i64 turns into 4 EVT::i32 values with both PPC and X86.

This method returns the number of registers needed, and the VT for each register. It also returns the VT and quantity of the intermediate values before they are promoted/expanded.

For example, MVT::v8f32 maps to 2 MVT::v4f32 with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack. Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86.

This method returns the number of registers needed, and the VT for each register. It also returns the VT and quantity of the intermediate values before they are promoted/expanded.

Definition at line 1191 of file TargetLoweringBase.cpp.

References getRegisterType(), llvm::EVT::getSimpleVT(), llvm::EVT::getSizeInBits(), llvm::MVT::getSizeInBits(), getTypeAction(), getTypeToTransformTo(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::EVT::getVectorVT(), llvm::isPowerOf2_32(), isTypeLegal(), llvm::NextPowerOf2(), llvm::X86II::TA, TypePromoteInteger, and TypeWidenVector.

Referenced by getCopyFromPartsVector().

◆ getVectorTypeBreakdownForCallingConv()

virtual unsigned llvm::TargetLoweringBase::getVectorTypeBreakdownForCallingConv ( LLVMContext Context,
EVT  VT,
EVT IntermediateVT,
unsigned NumIntermediates,
MVT RegisterVT 
) const
inlinevirtual

Certain targets such as MIPS require that some types such as vectors are always broken down into scalars in some contexts.

This occurs even if the vector type is legal.

Reimplemented in llvm::MipsTargetLowering.

Definition at line 695 of file TargetLowering.h.

Referenced by getCopyFromPartsVector().

◆ hasAndNot()

virtual bool llvm::TargetLoweringBase::hasAndNot ( SDValue  X) const
inlinevirtual

Return true if the target has a bitwise and-not operation: X = ~A & B This can be used to simplify select or other instructions.

Definition at line 504 of file TargetLowering.h.

Referenced by combineShuffleOfSplat().

◆ hasAndNotCompare()

virtual bool llvm::TargetLoweringBase::hasAndNotCompare ( SDValue  Y) const
inlinevirtual

Return true if the target should transform: (X & Y) == Y —> (~X & Y) == 0 (X & Y) != Y —> (~X & Y) != 0.

This may be profitable if the target has a bitwise and-not operation that sets comparison flags. A target may want to limit the transformation based on the type of Y or if Y is a constant.

Note that the transform will not occur if Y is known to be a power-of-2 because a mask and compare of a single bit can be handled by inverting the predicate, for example: (X & 8) == 8 —> (X & 8) != 0

Reimplemented in llvm::X86TargetLowering, llvm::PPCTargetLowering, and llvm::AArch64TargetLowering.

Definition at line 497 of file TargetLowering.h.

Referenced by llvm::TargetLowering::isExtendedTrueVal().

◆ hasBigEndianPartOrdering()

bool llvm::TargetLoweringBase::hasBigEndianPartOrdering ( EVT  VT,
const DataLayout DL 
) const
inline

When splitting a value of the specified type into parts, does the Lo or Hi part come first? This usually follows the endianness, except for ppcf128, where the Hi part always comes first.

Definition at line 1153 of file TargetLowering.h.

References llvm::DataLayout::isBigEndian(), and llvm::MVT::ppcf128.

Referenced by foldBitcastedFPLogic(), and getCopyFromParts().

◆ hasBitPreservingFPLogic()

virtual bool llvm::TargetLoweringBase::hasBitPreservingFPLogic ( EVT  VT) const
inlinevirtual

Return true if it is safe to transform an integer-domain bitwise operation into the equivalent floating-point operation.

This should be set to true if the target has IEEE-754-compliant fabs/fneg operations for the input type.

Reimplemented in llvm::X86TargetLowering, llvm::AArch64TargetLowering, and llvm::SITargetLowering.

Definition at line 443 of file TargetLowering.h.

Referenced by foldBitcastedFPLogic().

◆ hasExtractBitsInsn()

bool llvm::TargetLoweringBase::hasExtractBitsInsn ( ) const
inline

Return true if the target has BitExtract instructions.

Definition at line 275 of file TargetLowering.h.

Referenced by tryUnmergingGEPsAcrossIndirectBr().

◆ hasFastEqualityCompare()

virtual MVT llvm::TargetLoweringBase::hasFastEqualityCompare ( unsigned  NumBits) const
inlinevirtual

Return the preferred operand type if the target has a quick way to compare integer values of the given size.

Assume that any legal integer type can be compared efficiently. Targets may override this to allow illegal wide types to return a vector type if there is support to compare that type.

Reimplemented in llvm::X86TargetLowering.

Definition at line 480 of file TargetLowering.h.

References llvm::MVT::getIntegerVT(), and llvm::MVT::INVALID_SIMPLE_VALUE_TYPE.

Referenced by getMemCmpLoad().

◆ hasFloatingPointExceptions()

bool llvm::TargetLoweringBase::hasFloatingPointExceptions ( ) const
inline

Return true if target supports floating point exceptions.

Definition at line 524 of file TargetLowering.h.

Referenced by llvm::SelectionDAG::getNode(), and isKnownNeverSNan().

◆ hasMultipleConditionRegisters()

bool llvm::TargetLoweringBase::hasMultipleConditionRegisters ( ) const
inline

Return true if multiple condition registers are available.

Definition at line 270 of file TargetLowering.h.

Referenced by tryUnmergingGEPsAcrossIndirectBr().

◆ hasPairedLoad()

virtual bool llvm::TargetLoweringBase::hasPairedLoad ( EVT  ,
unsigned  
) const
inlinevirtual

Return true if the target supplies and combines to a paired load two loaded values of type LoadedType next to each other in memory.

RequiredAlignment gives the minimal alignment constraints that must be met to be able to select this paired load.

This information is not used to generate actual paired loads, but it is used to generate a sequence of loads that is easier to combine into a paired load. For instance, something like this: a = load i64* addr b = trunc i64 a to i32 c = lshr i64 a, 32 d = trunc i64 c to i32 will be optimized into: b = load i32* addr1 d = load i32* addr2 Where addr1 = addr2 +/- sizeof(i32).

In other words, unless the target performs a post-isel load combining, this information should not be provided because it will generate more loads.

Reimplemented in llvm::AArch64TargetLowering.

Definition at line 2080 of file TargetLowering.h.

Referenced by peekThroughBitcast().

◆ hasStandaloneRem()

virtual bool llvm::TargetLoweringBase::hasStandaloneRem ( EVT  VT) const
inlinevirtual

Return true if the target can handle a standalone remainder operation.

Reimplemented in llvm::ARMTargetLowering.

Definition at line 309 of file TargetLowering.h.

Referenced by getComparePred().

◆ hasTargetDAGCombine()

bool llvm::TargetLoweringBase::hasTargetDAGCombine ( ISD::NodeType  NT) const
inline

If true, the target has custom DAG combine transformations that it can perform for the specified node.

Definition at line 1159 of file TargetLowering.h.

References llvm::array_lengthof(), and assert().

Referenced by matchBinaryPredicate().

◆ initActions()

void TargetLoweringBase::initActions ( )
protected

Initialize all of the actions to default values.

Definition at line 531 of file TargetLoweringBase.cpp.

References llvm::ISD::ABS, llvm::ISD::ADDCARRY, llvm::MVT::all_valuetypes(), llvm::ISD::ANY_EXTEND_VECTOR_INREG, llvm::ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, llvm::sys::path::begin(), llvm::ISD::BITREVERSE, llvm::ISD::CONCAT_VECTORS, llvm::ISD::ConstantFP, llvm::ISD::CTLZ_ZERO_UNDEF, llvm::ISD::CTTZ_ZERO_UNDEF, llvm::ISD::DEBUGTRAP, llvm::sys::path::end(), Expand, llvm::MVT::f128, llvm::MVT::f16, llvm::MVT::f32, llvm::MVT::f64, llvm::MVT::f80, llvm::ISD::FCEIL, llvm::ISD::FCOPYSIGN, llvm::ISD::FEXP, llvm::ISD::FEXP2, llvm::ISD::FFLOOR, llvm::ISD::FGETSIGN, llvm::ISD::FLOG, llvm::ISD::FLOG10, llvm::ISD::FLOG2, llvm::ISD::FMAD, llvm::ISD::FMAXNAN, llvm::ISD::FMAXNUM, llvm::ISD::FMINNAN, llvm::ISD::FMINNUM, llvm::ISD::FNEARBYINT, llvm::ISD::FPOWI, llvm::ISD::FRINT, llvm::ISD::FROUND, llvm::ISD::FTRUNC, llvm::ISD::GET_DYNAMIC_AREA_OFFSET, llvm::MVT::i64, llvm::ISD::LAST_INDEXED_MODE, llvm::MVT::Other, llvm::ISD::PRE_INC, llvm::ISD::PREFETCH, llvm::ISD::READCYCLECOUNTER, llvm::ISD::SADDO, llvm::ISD::SETCCCARRY, setIndexedLoadAction(), setIndexedStoreAction(), setOperationAction(), llvm::ISD::SIGN_EXTEND_VECTOR_INREG, llvm::ISD::SMAX, llvm::ISD::SMIN, llvm::ISD::SMULO, llvm::ISD::SSUBO, llvm::ISD::SUBCARRY, llvm::ISD::TRAP, llvm::ISD::UADDO, llvm::ISD::UMAX, llvm::ISD::UMIN, llvm::ISD::UMULO, llvm::ISD::USUBO, and llvm::ISD::ZERO_EXTEND_VECTOR_INREG.

Referenced by TargetLoweringBase().

◆ insertSSPDeclarations()

void TargetLoweringBase::insertSSPDeclarations ( Module M) const
virtual

◆ InstructionOpcodeToISD()

int TargetLoweringBase::InstructionOpcodeToISD ( unsigned  Opcode) const

Get the ISD node that corresponds to the Instruction class opcode.

Definition at line 1346 of file TargetLoweringBase.cpp.

References llvm::MCID::Add, llvm::ISD::ADD, llvm::ISD::ADDRSPACECAST, llvm::ISD::AND, llvm::ISD::BITCAST, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::ISD::FADD, llvm::ISD::FDIV, llvm::ISD::FMUL, llvm::ISD::FP_EXTEND, llvm::ISD::FP_ROUND, llvm::ISD::FP_TO_SINT, llvm::ISD::FP_TO_UINT, llvm::ISD::FREM, llvm::ISD::FSUB, llvm::ISD::INSERT_VECTOR_ELT, llvm_unreachable, llvm::SPII::Load, llvm::ISD::LOAD, llvm::ISD::MERGE_VALUES, llvm::ISD::MUL, llvm::ISD::OR, llvm::MipsISD::Ret, llvm::ISD::SDIV, llvm::MCID::Select, llvm::ISD::SELECT, llvm::ISD::SETCC, llvm::ISD::SHL, llvm::ISD::SIGN_EXTEND, llvm::ISD::SINT_TO_FP, llvm::ISD::SRA, llvm::ISD::SREM, llvm::ISD::SRL, llvm::SPII::Store, llvm::ISD::STORE, llvm::ISD::SUB, llvm::ISD::TRUNCATE, llvm::ISD::UDIV, llvm::ISD::UINT_TO_FP, llvm::ISD::UREM, llvm::ISD::VECTOR_SHUFFLE, llvm::ISD::XOR, and llvm::ISD::ZERO_EXTEND.

Referenced by llvm::NVPTXTTIImpl::getArithmeticInstrCost(), llvm::X86TTIImpl::getArithmeticInstrCost(), llvm::PPCTTIImpl::getArithmeticInstrCost(), llvm::LanaiTTIImpl::getArithmeticInstrCost(), llvm::AArch64TTIImpl::getArithmeticInstrCost(), llvm::AMDGPUTTIImpl::getArithmeticInstrCost(), llvm::ARMTTIImpl::getArithmeticInstrCost(), llvm::BasicTTIImplBase< AMDGPUTTIImpl >::getArithmeticInstrCost(), llvm::X86TTIImpl::getArithmeticReductionCost(), llvm::X86TTIImpl::getCastInstrCost(), llvm::PPCTTIImpl::getCastInstrCost(), llvm::AArch64TTIImpl::getCastInstrCost(), llvm::ARMTTIImpl::getCastInstrCost(), llvm::BasicTTIImplBase< AMDGPUTTIImpl >::getCastInstrCost(), llvm::X86TTIImpl::getCmpSelInstrCost(), llvm::AArch64TTIImpl::getCmpSelInstrCost(), llvm::ARMTTIImpl::getCmpSelInstrCost(), llvm::BasicTTIImplBase< AMDGPUTTIImpl >::getCmpSelInstrCost(), llvm::PPCTTIImpl::getVectorInstrCost(), isBroadcastShuffle(), isPromotedInstructionLegal(), and SinkShiftAndTruncate().

◆ isCheapAddrSpaceCast()

virtual bool llvm::TargetLoweringBase::isCheapAddrSpaceCast ( unsigned  SrcAS,
unsigned  DestAS 
) const
inlinevirtual

Returns true if a cast from SrcAS to DestAS is "cheap", such that e.g.

we are happy to sink it into basic blocks.

Reimplemented in llvm::SITargetLowering.

Definition at line 1390 of file TargetLowering.h.

Referenced by OptimizeNoopCopyExpression().

◆ isCheapToSpeculateCtlz()

virtual bool llvm::TargetLoweringBase::isCheapToSpeculateCtlz ( ) const
inlinevirtual

Return true if it is cheap to speculate a call to intrinsic ctlz.

Reimplemented in llvm::X86TargetLowering, llvm::PPCTargetLowering, llvm::NVPTXTargetLowering, llvm::ARMTargetLowering, llvm::AArch64TargetLowering, llvm::MipsTargetLowering, and llvm::AMDGPUTargetLowering.

Definition at line 430 of file TargetLowering.h.

Referenced by despeculateCountZeros().

◆ isCheapToSpeculateCttz()

virtual bool llvm::TargetLoweringBase::isCheapToSpeculateCttz ( ) const
inlinevirtual

Return true if it is cheap to speculate a call to intrinsic cttz.

Reimplemented in llvm::X86TargetLowering, llvm::PPCTargetLowering, llvm::ARMTargetLowering, llvm::AArch64TargetLowering, llvm::MipsTargetLowering, and llvm::AMDGPUTargetLowering.

Definition at line 425 of file TargetLowering.h.

Referenced by despeculateCountZeros().

◆ isCommutativeBinOp()

virtual bool llvm::TargetLoweringBase::isCommutativeBinOp ( unsigned  Opcode) const
inlinevirtual

◆ isCondCodeLegal()

bool llvm::TargetLoweringBase::isCondCodeLegal ( ISD::CondCode  CC,
MVT  VT 
) const
inline

◆ isCtlzFast()

virtual bool llvm::TargetLoweringBase::isCtlzFast ( ) const
inlinevirtual

Return true if ctlz instruction is fast.

Reimplemented in llvm::X86TargetLowering, and llvm::PPCTargetLowering.

Definition at line 435 of file TargetLowering.h.

Referenced by llvm::TargetLowering::lowerCmpEqZeroToCtlzSrl().

◆ isExtFree()

bool llvm::TargetLoweringBase::isExtFree ( const Instruction I) const
inline

Return true if the extension represented by I is free.

Unlikely the is[Z|FP]ExtFree family which is based on types, this method can use the context provided by I to decide whether or not I is free. This method extends the behavior of the is[Z|FP]ExtFree family. In other words, if is[Z|FP]Free returns true, then this method returns true as well. The converse is not true. The target can perform the adequate checks by overriding isExtFreeImpl.

Precondition
I must be a sign, zero, or fp extension.

Definition at line 1993 of file TargetLowering.h.

References llvm::EVT::getEVT(), llvm::Instruction::getOpcode(), llvm::User::getOperand(), llvm::Value::getType(), and llvm_unreachable.

Referenced by hasSameExtUse(), and isPromotedInstructionLegal().

◆ isExtFreeImpl()

virtual bool llvm::TargetLoweringBase::isExtFreeImpl ( const Instruction I) const
inlineprotectedvirtual

Return true if the extension represented by I is free.

Precondition
I is a sign, zero, or fp extension and is[Z|FP]ExtFree of the related types is not true.

Definition at line 2426 of file TargetLowering.h.

◆ isExtLoad()

bool llvm::TargetLoweringBase::isExtLoad ( const LoadInst Load,
const Instruction Ext,
const DataLayout DL 
) const
inline

Return true if Load and Ext can form an ExtLoad.

For example, in AArch64 L = load i8, i8* ptr E = zext i8 L to i32 can be lowered into one load instruction ldrb w0, [x0]

Definition at line 2018 of file TargetLowering.h.

References assert(), llvm::Value::getType(), llvm::Value::hasOneUse(), llvm::ISD::SEXTLOAD, and llvm::ISD::ZEXTLOAD.

Referenced by hasSameExtUse().

◆ isExtractSubvectorCheap()

virtual bool llvm::TargetLoweringBase::isExtractSubvectorCheap ( EVT  ResVT,
EVT  SrcVT,
unsigned  Index 
) const
inlinevirtual

Return true if EXTRACT_SUBVECTOR is cheap for extracting this result type from this source type with this index.

This is needed because EXTRACT_SUBVECTOR usually has custom lowering that depends on the index of the first element, and only the target knows which lowering is cheap.

Reimplemented in llvm::X86TargetLowering, and llvm::ARMTargetLowering.

Definition at line 2190 of file TargetLowering.h.

Referenced by peekThroughBitcast().

◆ isFAbsFree()

virtual bool llvm::TargetLoweringBase::isFAbsFree ( EVT  VT) const
inlinevirtual

Return true if an fabs operation is free to the point where it is never worthwhile to replace it with a bitwise operation.

Reimplemented in llvm::AMDGPUTargetLowering.

Definition at line 2152 of file TargetLowering.h.

References assert(), and llvm::EVT::isFloatingPoint().

Referenced by foldBitcastedFPLogic(), FoldIntToFPToInt(), and llvm::BasicTTIImplBase< AMDGPUTTIImpl >::getIntrinsicInstrCost().

◆ isFMAFasterThanFMulAndFAdd()

virtual bool llvm::TargetLoweringBase::isFMAFasterThanFMulAndFAdd ( EVT  ) const
inlinevirtual

Return true if an FMA operation is faster than a pair of fmul and fadd instructions.

fmuladd intrinsics will be expanded to FMAs when this method returns true, otherwise fmuladd is expanded to fmul + fadd.

NOTE: This may be called before legalization on types for which FMAs are not legal, but should return true if those types will eventually legalize to types that support FMAs. After legalization, it will only be called on types that support FMAs (via Legal or Custom actions)

Reimplemented in llvm::X86TargetLowering, llvm::PPCTargetLowering, llvm::NVPTXTargetLowering, llvm::SystemZTargetLowering, llvm::AArch64TargetLowering, llvm::SITargetLowering, and llvm::HexagonTargetLowering.

Definition at line 2165 of file TargetLowering.h.

Referenced by getUnderlyingArgReg(), and isContractable().

◆ isFNegFree()

virtual bool llvm::TargetLoweringBase::isFNegFree ( EVT  VT) const
inlinevirtual

Return true if an fneg operation is free to the point where it is never worthwhile to replace it with a bitwise operation.

Reimplemented in llvm::AMDGPUTargetLowering.

Definition at line 2145 of file TargetLowering.h.

References assert(), and llvm::EVT::isFloatingPoint().

Referenced by foldBitcastedFPLogic(), and FoldIntToFPToInt().

◆ isFPExtFoldable()

virtual bool llvm::TargetLoweringBase::isFPExtFoldable ( unsigned  Opcode,
EVT  DestVT,
EVT  SrcVT 
) const
inlinevirtual

Return true if an fpext operation input to an Opcode operation is free (for instance, because half-precision floating-point numbers are implicitly extended to float-precision) for an FMA instruction.

Reimplemented in llvm::AMDGPUTargetLowering.

Definition at line 2133 of file TargetLowering.h.

References assert(), and llvm::EVT::isFloatingPoint().

Referenced by isContractable().

◆ isFPExtFree()

virtual bool llvm::TargetLoweringBase::isFPExtFree ( EVT  DestVT,
EVT  SrcVT 
) const
inlinevirtual

Return true if an fpext operation is free (for instance, because single-precision floating-point numbers are implicitly extended to double-precision).

Reimplemented in llvm::PPCTargetLowering.

Definition at line 2124 of file TargetLowering.h.

References assert(), and llvm::EVT::isFloatingPoint().

◆ isFPImmLegal()

virtual bool llvm::TargetLoweringBase::isFPImmLegal ( const APFloat ,
EVT   
) const
inlinevirtual

Returns true if the target can instruction select the specified FP immediate natively.

If false, the legalizer will materialize the FP immediate as a load from a constant pool.

Reimplemented in llvm::X86TargetLowering, llvm::PPCTargetLowering, llvm::ARMTargetLowering, llvm::SystemZTargetLowering, llvm::AArch64TargetLowering, llvm::HexagonTargetLowering, and llvm::AMDGPUTargetLowering.

Definition at line 729 of file TargetLowering.h.

Referenced by combineShuffleOfSplat(), FoldIntToFPToInt(), isFMulNegTwo(), and isNegatibleForFree().

◆ isFsqrtCheap()

virtual bool llvm::TargetLoweringBase::isFsqrtCheap ( SDValue  X,
SelectionDAG DAG 
) const
inlinevirtual

Return true if SQRT(X) shouldn't be replaced with X*RSQRT(X).

Reimplemented in llvm::AMDGPUTargetLowering.

Definition at line 314 of file TargetLowering.h.

Referenced by isFMulNegTwo().

◆ isIndexedLoadLegal()

bool llvm::TargetLoweringBase::isIndexedLoadLegal ( unsigned  IdxMode,
EVT  VT 
) const
inline

Return true if the specified indexed load is legal on this target.

Definition at line 945 of file TargetLowering.h.

References llvm::EVT::getSimpleVT(), and llvm::EVT::isSimple().

Referenced by canFoldInAddressingMode().

◆ isIndexedStoreLegal()

bool llvm::TargetLoweringBase::isIndexedStoreLegal ( unsigned  IdxMode,
EVT  VT 
) const
inline

Return true if the specified indexed load is legal on this target.

Definition at line 963 of file TargetLowering.h.

References llvm::EVT::getSimpleVT(), and llvm::EVT::isSimple().

Referenced by canFoldInAddressingMode().

◆ isIntDivCheap()

virtual bool llvm::TargetLoweringBase::isIntDivCheap ( EVT  VT,
AttributeList  Attr 
) const
inlinevirtual

Return true if integer divide is usually cheaper than a sequence of several shifts, adds, and multiplies for this target.

The definition of "cheaper" may depend on whether we're optimizing for speed or for size.

Reimplemented in llvm::X86TargetLowering, and llvm::AArch64TargetLowering.

Definition at line 306 of file TargetLowering.h.

Referenced by llvm::TargetLowering::BuildSDIVPow2(), and simplifyDivRem().

◆ isJumpExpensive()

bool llvm::TargetLoweringBase::isJumpExpensive ( ) const
inline

Return true if Flow Control is an expensive operation that should be avoided.

Definition at line 361 of file TargetLowering.h.

Referenced by scaleWeights(), and llvm::SelectionDAGBuilder::ShouldEmitAsBranches().

◆ isJumpTableRelative()

virtual bool llvm::TargetLoweringBase::isJumpTableRelative ( ) const
inlinevirtual

◆ isLegalAddImmediate()

virtual bool llvm::TargetLoweringBase::isLegalAddImmediate ( int64_t  ) const
inlinevirtual

Return true if the specified immediate is legal add immediate, that is the target has add instructions which can add a register with the immediate without having to materialize the immediate into a register.

Reimplemented in llvm::X86TargetLowering, llvm::PPCTargetLowering, llvm::SystemZTargetLowering, llvm::ARMTargetLowering, and llvm::AArch64TargetLowering.

Definition at line 1917 of file TargetLowering.h.

Referenced by canFoldInAddressingMode(), llvm::BasicTTIImplBase< AMDGPUTTIImpl >::isLegalAddImmediate(), and simplifyDivRem().

◆ isLegalAddressingMode()

bool TargetLoweringBase::isLegalAddressingMode ( const DataLayout DL,
const AddrMode AM,
Type Ty,
unsigned  AS,
Instruction I = nullptr 
) const
virtual

Return true if the addressing mode represented by AM is legal for this target, for a load/store of the specified type.

isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target, for a load/store of the specified type.

The type may be VoidTy, in which case only return true if the addressing mode is legal for a load/store of any legal type. TODO: Handle pre/postinc as well.

If the address space cannot be determined, it will be -1.

TODO: Remove default argument

Reimplemented in llvm::X86TargetLowering, llvm::PPCTargetLowering, llvm::NVPTXTargetLowering, llvm::SystemZTargetLowering, llvm::AArch64TargetLowering, llvm::ARMTargetLowering, llvm::HexagonTargetLowering, llvm::SITargetLowering, llvm::XCoreTargetLowering, llvm::AVRTargetLowering, and llvm::ARCTargetLowering.

Definition at line 1501 of file TargetLoweringBase.cpp.

References llvm::TargetLoweringBase::AddrMode::BaseGV, llvm::TargetLoweringBase::AddrMode::BaseOffs, llvm::TargetLoweringBase::AddrMode::HasBaseReg, and llvm::TargetLoweringBase::AddrMode::Scale.

Referenced by canFoldInAddressingMode(), llvm::BasicTTIImplBase< AMDGPUTTIImpl >::isLegalAddressingMode(), and isPromotedInstructionLegal().

◆ isLegalICmpImmediate()

virtual bool llvm::TargetLoweringBase::isLegalICmpImmediate ( int64_t  ) const
inlinevirtual

Return true if the specified immediate is legal icmp immediate, that is the target has icmp instructions which can compare a register against the immediate without having to materialize the immediate into a register.

Reimplemented in llvm::X86TargetLowering, llvm::PPCTargetLowering, llvm::SystemZTargetLowering, llvm::ARMTargetLowering, llvm::AArch64TargetLowering, and llvm::HexagonTargetLowering.

Definition at line 1910 of file TargetLowering.h.

Referenced by llvm::BasicTTIImplBase< AMDGPUTTIImpl >::isLegalICmpImmediate(), and llvm::TargetLowering::SimplifySetCC().

◆ isLegalRC()

bool TargetLoweringBase::isLegalRC ( const TargetRegisterInfo TRI,
const TargetRegisterClass RC 
) const
protected

Return true if the value types that can be represented by the specified register class are all legal.

isLegalRC - Return true if the value types that can be represented by the specified register class are all legal.

Definition at line 855 of file TargetLoweringBase.cpp.

References I, isTypeLegal(), llvm::TargetRegisterInfo::legalclasstypes_begin(), and llvm::MVT::Other.

Referenced by findRepresentativeClass(), and llvm::TargetLowering::getRegForInlineAsmConstraint().

◆ isLoadBitCastBeneficial()

virtual bool llvm::TargetLoweringBase::isLoadBitCastBeneficial ( EVT  LoadVT,
EVT  BitcastVT 
) const
inlinevirtual

Return true if the following transform is beneficial: fold (conv (load x)) -> (load (conv*)x) On architectures that don't natively support some vector loads efficiently, casting the load to a smaller vector of larger types and loading is more efficient, however, this can be undone by optimizations in dag combiner.

Reimplemented in llvm::AMDGPUTargetLowering.

Definition at line 379 of file TargetLowering.h.

References llvm::EVT::getSimpleVT(), llvm::EVT::isSimple(), and llvm::ISD::LOAD.

Referenced by foldBitcastedFPLogic().

◆ isLoadExtLegal()

bool llvm::TargetLoweringBase::isLoadExtLegal ( unsigned  ExtType,
EVT  ValVT,
EVT  MemVT 
) const
inline

Return true if the specified load with extension is legal on this target.

Definition at line 896 of file TargetLowering.h.

Referenced by ExtendUsesToFormExtLoad(), FoldIntToFPToInt(), llvm::BasicTTIImplBase< AMDGPUTTIImpl >::getCastInstrCost(), hasSameExtUse(), isTruncateOf(), matchBinaryPredicate(), peekThroughBitcast(), and simplifyDivRem().

◆ isLoadExtLegalOrCustom()

bool llvm::TargetLoweringBase::isLoadExtLegalOrCustom ( unsigned  ExtType,
EVT  ValVT,
EVT  MemVT 
) const
inline

Return true if the specified load with extension is legal or custom on this target.

Definition at line 902 of file TargetLowering.h.

Referenced by ExtendUsesToFormExtLoad().

◆ isMaskAndCmp0FoldingBeneficial()

virtual bool llvm::TargetLoweringBase::isMaskAndCmp0FoldingBeneficial ( const Instruction AndI) const
inlinevirtual

Return if the target supports combining a chain like:

%andResult = and %val1, #mask
%icmpResult = icmp %andResult, 0

into a single machine instruction of a form like:

cc = test %register, #mask

Reimplemented in llvm::X86TargetLowering, and llvm::AArch64TargetLowering.

Definition at line 463 of file TargetLowering.h.

Referenced by sinkAndCmp0Expression().

◆ isMultiStoresCheaperThanBitsMerge()

virtual bool llvm::TargetLoweringBase::isMultiStoresCheaperThanBitsMerge ( EVT  LTy,
EVT  HTy 
) const
inlinevirtual

Return true if it is cheaper to split the store of a merged int val from a pair of smaller values into multiple stores.

Reimplemented in llvm::X86TargetLowering.

Definition at line 449 of file TargetLowering.h.

Referenced by peekThroughBitcast(), and splitMergedValStore().

◆ isNarrowingProfitable()

virtual bool llvm::TargetLoweringBase::isNarrowingProfitable ( EVT  ,
EVT   
) const
inlinevirtual

Return true if it's profitable to narrow operations of type VT1 to VT2.

e.g. on x86, it's profitable to narrow from i32 to i8 but not from i32 to i16.

Reimplemented in llvm::X86TargetLowering, and llvm::AMDGPUTargetLowering.

Definition at line 2172 of file TargetLowering.h.

Referenced by isTruncateOf(), ShrinkLoadReplaceStoreWithStore(), and simplifyDivRem().

◆ isNoopAddrSpaceCast()

virtual bool llvm::TargetLoweringBase::isNoopAddrSpaceCast ( unsigned  SrcAS,
unsigned  DestAS 
) const
inlinevirtual

◆ isOperationCustom()

bool llvm::TargetLoweringBase::isOperationCustom ( unsigned  Op,
EVT  VT 
) const
inline

Return true if the operation uses custom lowering, regardless of whether the type is legal or not.

Definition at line 796 of file TargetLowering.h.

Referenced by isDivRemLibcallAvailable().

◆ isOperationExpand()

bool llvm::TargetLoweringBase::isOperationExpand ( unsigned  Op,
EVT  VT 
) const
inline

Return true if the specified operation is illegal on this target or unlikely to be made legal with custom lowering.

This is used to help guide high-level lowering decisions.

Definition at line 871 of file TargetLowering.h.

Referenced by llvm::BasicTTIImplBase< AMDGPUTTIImpl >::getArithmeticInstrCost(), llvm::BasicTTIImplBase< AMDGPUTTIImpl >::getCastInstrCost(), llvm::BasicTTIImplBase< AMDGPUTTIImpl >::getCmpSelInstrCost(), llvm::BasicTTIImplBase< AMDGPUTTIImpl >::getIntrinsicInstrCost(), peekThroughBitcast(), and llvm::X86TargetLowering::X86TargetLowering().

◆ isOperationLegal()

bool llvm::TargetLoweringBase::isOperationLegal ( unsigned  Op,
EVT  VT 
) const
inline

◆ isOperationLegalOrCustom()

bool llvm::TargetLoweringBase::isOperationLegalOrCustom ( unsigned  Op,
EVT  VT 
) const
inline

Return true if the specified operation is legal on this target or can be made legal with custom lowering.

This is used to help guide high-level lowering decisions.

Definition at line 769 of file TargetLowering.h.

References llvm::MVT::Other.

Referenced by buildFromShuffleMostly(), llvm::TargetLowering::BuildSDIV(), llvm::TargetLowering::BuildUDIV(), calculateByteProvider(), CanCombineFCOPYSIGN_EXTEND_ROUND(), combineMinNumMaxNum(), combineSelect(), combineShuffleOfSplat(), combineShuffleToVectorExtend(), ConvertSelectToConcatVector(), createBSWAPShuffleMask(), llvm::TargetLowering::expandMUL_LOHI(), llvm::TargetLowering::expandUnalignedLoad(), llvm::TargetLowering::expandUnalignedStore(), ExtendUsesToFormExtLoad(), FindOptimalMemOpLowering(), FoldIntToFPToInt(), getAsCarry(), getExpandedMinMaxOps(), getUnderlyingArgReg(), llvm::BasicTTIImplBase< AMDGPUTTIImpl >::haveFastSqrt(), isBroadcastShuffle(), isBSwapHWordElement(), isContractable(), isDivRemLibcallAvailable(), llvm::ARMTargetLowering::isExtractSubvectorCheap(), llvm::X86TargetLowering::isExtractSubvectorCheap(), llvm::HexagonTargetLowering::isFMAFasterThanFMulAndFAdd(), isFMulNegTwo(), isNegatibleForFree(), llvm::AArch64TargetLowering::isProfitableToHoist(), isPromotedInstructionLegal(), isTruncateOf(), LowerBUILD_VECTORAsVariablePermute(), LowerExtendedLoad(), makeBitReverse(), matchRotateSub(), peekThroughBitcast(), PrepareCall(), llvm::BasicTTIImplBase< AMDGPUTTIImpl >::shouldBuildLookupTables(), ShrinkLoadReplaceStoreWithStore(), llvm::TargetLowering::SimplifyDemandedBits(), simplifyDivRem(), SinkShiftAndTruncate(), and XFormVExtractWithShuffleIntoLoad().

◆ isOperationLegalOrCustomOrPromote()

bool llvm::TargetLoweringBase::isOperationLegalOrCustomOrPromote ( unsigned  Op,
EVT  VT 
) const
inline

Return true if the specified operation is legal on this target or can be made legal with custom lowering or using promotion.

This is used to help guide high-level lowering decisions.

Definition at line 787 of file TargetLowering.h.

References llvm::MVT::Other.

Referenced by createBSWAPShuffleMask(), and narrowExtractedVectorLoad().

◆ isOperationLegalOrPromote()

bool llvm::TargetLoweringBase::isOperationLegalOrPromote ( unsigned  Op,
EVT  VT 
) const
inline

Return true if the specified operation is legal on this target or can be made legal using promotion.

This is used to help guide high-level lowering decisions.

Definition at line 778 of file TargetLowering.h.

References llvm::MVT::Other.

Referenced by combineTruncatedArithmetic(), llvm::BasicTTIImplBase< AMDGPUTTIImpl >::getArithmeticInstrCost(), llvm::BasicTTIImplBase< AMDGPUTTIImpl >::getCastInstrCost(), llvm::BasicTTIImplBase< AMDGPUTTIImpl >::getIntrinsicInstrCost(), lowerBuildVectorToBitOp(), and WidenMaskArithmetic().

◆ isPredictableSelectExpensive()

bool llvm::TargetLoweringBase::isPredictableSelectExpensive ( ) const
inline

Return true if selects are only cheaper than branches if the branch is unlikely to be predicted right.

Definition at line 365 of file TargetLowering.h.

Referenced by isFormingBranchFromSelectProfitable().

◆ isProfitableToHoist()

virtual bool llvm::TargetLoweringBase::isProfitableToHoist ( Instruction I) const
inlinevirtual

◆ isSafeMemOpType()

virtual bool llvm::TargetLoweringBase::isSafeMemOpType ( MVT  ) const
inlinevirtual

Returns true if it's safe to use load / store of the specified type to expand memcpy / memset inline.

This is mostly true for all types except for some special cases. For example, on X86 targets without SSE2 f64 load / store are done with fldl / fstpl which also does type conversion. Note the specified type doesn't have to be legal as the hook is used before type legalization.

Reimplemented in llvm::X86TargetLowering.

Definition at line 1264 of file TargetLowering.h.

Referenced by FindOptimalMemOpLowering().

◆ isSelectSupported()

virtual bool llvm::TargetLoweringBase::isSelectSupported ( SelectSupportKind  ) const
inlinevirtual

Reimplemented in llvm::ARMTargetLowering, and llvm::AMDGPUTargetLowering.

Definition at line 265 of file TargetLowering.h.

Referenced by getTrueOrFalseValue().

◆ isShuffleMaskLegal()

virtual bool llvm::TargetLoweringBase::isShuffleMaskLegal ( ArrayRef< int >  ,
EVT   
) const
inlinevirtual

Targets can use this to indicate that they only support some VECTOR_SHUFFLE operations, those with specific masks.

By default, if a target supports the VECTOR_SHUFFLE node, all mask values are assumed to be legal.

Reimplemented in llvm::X86TargetLowering, llvm::ARMTargetLowering, llvm::AArch64TargetLowering, llvm::SITargetLowering, llvm::HexagonTargetLowering, and llvm::MipsSETargetLowering.

Definition at line 737 of file TargetLowering.h.

Referenced by combineConcatVectorOfExtracts(), combineShuffleOfSplat(), createBSWAPShuffleMask(), ExpandBVWithShuffles(), foldBitcastedFPLogic(), isBSwapHWordElement(), and peekThroughBitcast().

◆ isSlowDivBypassed()

bool llvm::TargetLoweringBase::isSlowDivBypassed ( ) const
inline

Returns true if target has indicated at least one type should be bypassed.

Definition at line 351 of file TargetLowering.h.

◆ isStoreBitCastBeneficial()

virtual bool llvm::TargetLoweringBase::isStoreBitCastBeneficial ( EVT  StoreVT,
EVT  BitcastVT 
) const
inlinevirtual

Return true if the following transform is beneficial: (store (y (conv x)), y*)) -> (store x, (x*))

Definition at line 399 of file TargetLowering.h.

Referenced by peekThroughBitcast().

◆ isSuitableForBitTests()

bool llvm::TargetLoweringBase::isSuitableForBitTests ( unsigned  NumDests,
unsigned  NumCmps,
const APInt Low,
const APInt High,
const DataLayout DL 
) const
inline

Return true if lowering to a bit test is suitable for a set of case clusters which contains NumDests unique destinations, Low and High as its lowest and highest case values, and expects NumCmps case value comparisons.

Check if the number of destinations, comparison metric, and range are all suitable.

Definition at line 846 of file TargetLowering.h.

Referenced by llvm::BasicTTIImplBase< AMDGPUTTIImpl >::getEstimatedNumberOfCaseClusters(), and tryToElideArgumentCopy().

◆ isSuitableForJumpTable()

bool llvm::TargetLoweringBase::isSuitableForJumpTable ( const SwitchInst SI,
uint64_t  NumCases,
uint64_t  Range 
) const
inline

Return true if lowering to a jump table is suitable for a set of case clusters which may contain NumCases cases, Range range of values.

FIXME: This function check the maximum table size and density, but the minimum size is not checked. It would be nice if the the minimum size is also combined within this function. Currently, the minimum size check is performed in findJumpTable() in SelectionDAGBuiler and getEstimatedNumberOfCaseClusters() in BasicTTIImpl.

Definition at line 825 of file TargetLowering.h.

References llvm::Instruction::getParent(), llvm::BasicBlock::getParent(), and llvm::Function::optForSize().

Referenced by llvm::BasicTTIImplBase< AMDGPUTTIImpl >::getEstimatedNumberOfCaseClusters(), and tryToElideArgumentCopy().

◆ isTruncateFree() [1/2]

virtual bool llvm::TargetLoweringBase::isTruncateFree ( Type FromTy,
Type ToTy 
) const
inlinevirtual

◆ isTruncateFree() [2/2]

virtual bool llvm::TargetLoweringBase::isTruncateFree ( EVT  FromVT,
EVT  ToVT 
) const
inlinevirtual

◆ isTruncStoreLegal()

bool llvm::TargetLoweringBase::isTruncStoreLegal ( EVT  ValVT,
EVT  MemVT 
) const
inline

Return true if the specified store with truncation is legal on this target.

Definition at line 921 of file TargetLowering.h.

Referenced by combineMaskedStore(), and peekThroughBitcast().

◆ isTruncStoreLegalOrCustom()

bool llvm::TargetLoweringBase::isTruncStoreLegalOrCustom ( EVT  ValVT,
EVT  MemVT 
) const
inline

Return true if the specified store with truncation has solution on this target.

Definition at line 927 of file TargetLowering.h.

◆ isTypeLegal()

bool llvm::TargetLoweringBase::isTypeLegal ( EVT  VT) const
inline

Return true if the target has native support for the specified value type.

This means that it has a register that directly holds it without promotions or expansions.

Definition at line 609 of file TargetLowering.h.

References llvm::array_lengthof(), assert(), llvm::EVT::getSimpleVT(), llvm::EVT::isSimple(), and llvm::MVT::SimpleTy.

Referenced by llvm::ARMTargetLowering::allowTruncateForTailCall(), llvm::X86TargetLowering::allowTruncateForTailCall(), llvm::TargetLowering::BuildSDIV(), llvm::TargetLowering::BuildUDIV(), canFoldInAddressingMode(), canOpTrap(), combineConcatVectorOfExtracts(), combineConcatVectorOfScalars(), combineFMA(), combineFneg(), combineMaskedLoad(), combineMaskedStore(), combineSelect(), combineSelectOfTwoConstants(), combineShuffle(), combineShuffleOfSplat(), combineShuffleToVectorExtend(), combineSIntToFP(), combineToExtendVectorInReg(), combineTruncateWithUSat(), combineVSelectWithAllOnesOrZeros(), combineX86ShuffleChain(), computeRegisterProperties(), convertBuildVectorCastElt(), countOperands(), EltsFromConsecutiveLoads(), emitRemovedIntrinsicError(), ExpandBITCAST(), llvm::TargetLowering::expandUnalignedLoad(), llvm::TargetLowering::expandUnalignedStore(), llvm::FastISel::fastEmitZExtFromI1(), FindMemType(), FindOptimalMemOpLowering(), foldBitcastedFPLogic(), getConstVector(), getCopyFromPartsVector(), getCopyToParts(), getExpandedMinMaxOps(), llvm::AArch64TTIImpl::getExtractWithExtendCost(), getMemCmpLoad(), getPromotedVectorElementType(), llvm::SITargetLowering::getRegForInlineAsmConstraint(), llvm::FastISel::getRegForValue(), llvm::X86TargetLowering::getSetCCResultType(), getVectorTypeBreakdown(), getVectorTypeBreakdownMVT(), llvm::SITargetLowering::hasBitPreservingFPLogic(), llvm::SystemZTTIImpl::hasDivRemOp(), llvm::X86TargetLowering::hasFastEqualityCompare(), llvm::BasicTTIImplBase< AMDGPUTTIImpl >::haveFastSqrt(), llvm::GenericScheduler::initPolicy(), isBSwapHWordElement(), isDivRemLibcallAvailable(), isFloatingPointZero(), isLegalRC(), isNoopBitcast(), isSETCCorConvertedSETCC(), llvm::X86TargetLowering::isShuffleMaskLegal(), llvm::X86TargetLowering::isTypeDesirableForOp(), llvm::BasicTTIImplBase< AMDGPUTTIImpl >::isTypeLegal(), llvm::ARMTargetLowering::isVectorLoadExtDesirable(), LowerADDC_ADDE_SUBC_SUBE(), LowerADDSUBCARRY(), LowerATOMIC_STORE(), LowerExtendedLoad(), LowerFP_TO_SINT(), LowerFP_TO_UINT(), llvm::ARMTargetLowering::lowerInterleavedLoad(), llvm::ARMTargetLowering::lowerInterleavedStore(), LowerShiftParts(), LowerSINT_TO_FP(), llvm::AMDGPUTargetLowering::LowerUDIVREM64(), llvm::SparcTargetLowering::LowerUINT_TO_FP(), lowerVectorShuffle(), lowerVectorShuffleAsElementInsertion(), lowerVectorShuffleAsShift(), LowerXALUO(), LowerXOR(), matchRotateSub(), mayTailCallThisCC(), narrowExtractedVectorLoad(), OptimizeExtractBits(), peekThroughBitcast(), PerformANDCombine(), performExtendCombine(), PerformExtendCombine(), llvm::AMDGPUTargetLowering::performLoadCombine(), PerformLOADCombine(), performORCombine(), PerformORCombine(), performSelectCombine(), PerformShiftCombine(), llvm::AMDGPUTargetLowering::performShlCombine(), llvm::AMDGPUTargetLowering::performStoreCombine(), PerformSTORECombine(), PerformVECTOR_SHUFFLECombine(), PerformXORCombine(), llvm::ResourcePriorityQueue::rawRegPressureDelta(), llvm::X86TargetLowering::ReplaceNodeResults(), llvm::ResourcePriorityQueue::ResourcePriorityQueue(), llvm::DAGTypeLegalizer::run(), llvm::ResourcePriorityQueue::scheduledNode(), llvm::FastISel::selectBinaryOp(), llvm::FastISel::selectBitCast(), llvm::FastISel::selectCast(), llvm::FastISel::selectExtractValue(), llvm::FastISel::selectFNeg(), llvm::AMDGPUTargetLowering::shouldCombineMemoryType(), simplifyDivRem(), llvm::TargetLowering::SimplifySetCC(), llvm::SystemZTargetLowering::SystemZTargetLowering(), tryToFoldExtendOfConstant(), and llvm::SelectionDAGBuilder::visitBitTestHeader().

◆ isVectorClearMaskLegal()

virtual bool llvm::TargetLoweringBase::isVectorClearMaskLegal ( const SmallVectorImpl< int > &  ,
EVT   
) const
inlinevirtual

Similar to isShuffleMaskLegal.

This is used by Targets can use this to indicate if there is a suitable VECTOR_SHUFFLE that can be used to replace a VAND with a constant pool entry.

Reimplemented in llvm::X86TargetLowering.

Definition at line 750 of file TargetLowering.h.

Referenced by combineShuffleOfSplat().

◆ isVectorLoadExtDesirable()

virtual bool llvm::TargetLoweringBase::isVectorLoadExtDesirable ( SDValue  ExtVal) const
inlinevirtual

Return true if folding a vector load into ExtVal (a sign, zero, or any extend node) is profitable.

Reimplemented in llvm::X86TargetLowering, and llvm::ARMTargetLowering.

Definition at line 2141 of file TargetLowering.h.

Referenced by ExtendUsesToFormExtLoad(), and isTruncateOf().

◆ isVectorShiftByScalarCheap()

virtual bool llvm::TargetLoweringBase::isVectorShiftByScalarCheap ( Type Ty) const
inlinevirtual

Return true if it's significantly cheaper to shift a vector by a uniform scalar than by an amount which will vary across each lane.

On x86, for example, there is a "psllw" instruction for the former case, but no simple instruction for a general "a << b" operation on vectors.

Reimplemented in llvm::X86TargetLowering.

Definition at line 1925 of file TargetLowering.h.

Referenced by isBroadcastShuffle().

◆ isZExtFree() [1/3]

virtual bool llvm::TargetLoweringBase::isZExtFree ( Type FromTy,
Type ToTy 
) const
inlinevirtual

Return true if any actual instruction that defines a value of type FromTy implicitly zero-extends the value to ToTy in the result register.

The function should return true when it is likely that the truncate can be freely folded with an instruction defining a value of FromTy. If the defining instruction is unknown (because you're looking at a function argument, PHI, etc.) then the target may require an explicit truncate, which is not necessarily free, but this function does not deal with those cases. Targets must return false when FromTy >= ToTy.

Reimplemented in llvm::X86TargetLowering, llvm::AArch64TargetLowering, llvm::AMDGPUTargetLowering, and llvm::MSP430TargetLowering.

Definition at line 2051 of file TargetLowering.h.

Referenced by combineShuffleOfScalars(), FoldCONCAT_VECTORS(), llvm::BasicTTIImplBase< AMDGPUTTIImpl >::getCastInstrCost(), llvm::RegsForValue::getCopyToRegs(), llvm::BasicTTIImplBase< AMDGPUTTIImpl >::getOperationCost(), hasSameExtUse(), isTruncateOf(), llvm::PPCTargetLowering::isZExtFree(), llvm::TargetLowering::ShrinkDemandedOp(), and simplifyDivRem().

◆ isZExtFree() [2/3]

virtual bool llvm::TargetLoweringBase::isZExtFree ( EVT  FromTy,
EVT  ToTy 
) const
inlinevirtual

◆ isZExtFree() [3/3]

virtual bool llvm::TargetLoweringBase::isZExtFree ( SDValue  Val,
EVT  VT2 
) const
inlinevirtual

Return true if zero-extending the specific node Val to type VT2 is free (either because it's implicitly zero-extended such as ARM ldrb / ldrh or because it's folded such as X86 zero-extending loads).

Reimplemented in llvm::X86TargetLowering, llvm::PPCTargetLowering, llvm::ARMTargetLowering, llvm::AArch64TargetLowering, llvm::AMDGPUTargetLowering, llvm::MSP430TargetLowering, and llvm::XCoreTargetLowering.

Definition at line 2117 of file TargetLowering.h.

References llvm::SDValue::getValueType().

◆ lowerIdempotentRMWIntoFencedLoad()

virtual LoadInst* llvm::TargetLoweringBase::lowerIdempotentRMWIntoFencedLoad ( AtomicRMWInst RMWI) const
inlinevirtual

On some platforms, an AtomicRMW that never actually modifies the value (such as fetch_add of 0) can be turned into a fence followed by an atomic load.

This may sound useless, but it makes it possible for the processor to keep the cacheline shared, dramatically improving performance. And such idempotent RMWs are useful for implementing some kinds of locks, see for example (justification + benchmarks): http://www.hpl.hp.com/techreports/2012/HPL-2012-68.pdf This method tries doing that transformation, returning the atomic load if it succeeds, and nullptr otherwise. If shouldExpandAtomicLoadInIR returns true on that load, it will undergo another round of expansion.

Definition at line 1561 of file TargetLowering.h.

◆ lowerInterleavedLoad()

virtual bool llvm::TargetLoweringBase::lowerInterleavedLoad ( LoadInst LI,
ArrayRef< ShuffleVectorInst *>  Shuffles,
ArrayRef< unsigned Indices,
unsigned  Factor 
) const
inlinevirtual

Lower an interleaved load to target specific intrinsics.

Return true on success.

LI is the vector load instruction. Shuffles is the shufflevector list to DE-interleave the loaded vector. Indices is the corresponding indices for each shufflevector. Factor is the interleave factor.

Reimplemented in llvm::X86TargetLowering, llvm::ARMTargetLowering, and llvm::AArch64TargetLowering.

Definition at line 2096 of file TargetLowering.h.

◆ lowerInterleavedStore()

virtual bool llvm::TargetLoweringBase::lowerInterleavedStore ( StoreInst SI,
ShuffleVectorInst SVI,
unsigned  Factor 
) const
inlinevirtual

Lower an interleaved store to target specific intrinsics.

Return true on success.

SI is the vector store instruction. SVI is the shufflevector to RE-interleave the stored vector. Factor is the interleave factor.

Reimplemented in llvm::X86TargetLowering, llvm::ARMTargetLowering, and llvm::AArch64TargetLowering.

Definition at line 2109 of file TargetLowering.h.

◆ markLibCallAttributes()

virtual void llvm::TargetLoweringBase::markLibCallAttributes ( MachineFunction MF,
unsigned  CC,
ArgListTy Args 
) const
inlinevirtual

◆ mergeStoresAfterLegalization()

virtual bool llvm::TargetLoweringBase::mergeStoresAfterLegalization ( ) const
inlinevirtual

Allow store merging after legalization in addition to before legalization.

This may catch stores that do not exist earlier (eg, stores created from intrinsics).

Reimplemented in llvm::X86TargetLowering.

Definition at line 416 of file TargetLowering.h.

Referenced by peekThroughBitcast().

◆ needsFixedCatchObjects()

virtual bool llvm::TargetLoweringBase::needsFixedCatchObjects ( ) const
inlinevirtual

Reimplemented in llvm::X86TargetLowering.

Definition at line 1312 of file TargetLowering.h.

References llvm::report_fatal_error().

◆ operator=()

TargetLoweringBase& llvm::TargetLoweringBase::operator= ( const TargetLoweringBase )
delete

◆ rangeFitsInWord()

bool llvm::TargetLoweringBase::rangeFitsInWord ( const APInt Low,
const APInt High,
const DataLayout DL 
) const
inline

Check whether the range [Low,High] fits in a machine word.

Definition at line 810 of file TargetLowering.h.

References llvm::DataLayout::getPointerSizeInBits().

Referenced by tryToElideArgumentCopy().

◆ setBooleanContents() [1/2]

void llvm::TargetLoweringBase::setBooleanContents ( BooleanContent  Ty)
inlineprotected

◆ setBooleanContents() [2/2]

void llvm::TargetLoweringBase::setBooleanContents ( BooleanContent  IntTy,
BooleanContent  FloatTy 
)
inlineprotected

Specify how the target extends the result of integer and floating point boolean values from i1 to a wider type.

See getBooleanContents.

Definition at line 1612 of file TargetLowering.h.

◆ setBooleanVectorContents()

void llvm::TargetLoweringBase::setBooleanVectorContents ( BooleanContent  Ty)
inlineprotected

◆ setCmpLibcallCC()

void llvm::TargetLoweringBase::setCmpLibcallCC ( RTLIB::Libcall  Call,
ISD::CondCode  CC 
)
inline

Override the default CondCode to be used to test the result of the comparison libcall against zero.

Definition at line 2217 of file TargetLowering.h.

Referenced by llvm::ARMTargetLowering::ARMTargetLowering(), and llvm::MSP430TargetLowering::MSP430TargetLowering().

◆ setCondCodeAction()

void llvm::TargetLoweringBase::setCondCodeAction ( ISD::CondCode  CC,
MVT  VT,
LegalizeAction  Action 
)
inlineprotected

Indicate that the specified condition code is or isn't supported on the target and indicate what to do about it.

The lower 3 bits of the SimpleTy index into Nth 4bit set from the 32-bit value and the upper 29 bits index into the second dimension of the array to select what 32-bit value to use.

Definition at line 1762 of file TargetLowering.h.

References llvm::array_lengthof(), assert(), llvm::MVT::isValid(), and llvm::MVT::SimpleTy.

Referenced by llvm::MipsSETargetLowering::addMSAFloatType(), llvm::MipsSETargetLowering::addMSAIntType(), llvm::HexagonTargetLowering::HexagonTargetLowering(), llvm::MipsSETargetLowering::MipsSETargetLowering(), llvm::PPCTargetLowering::PPCTargetLowering(), llvm::R600TargetLowering::R600TargetLowering(), llvm::WebAssemblyTargetLowering::WebAssemblyTargetLowering(), and llvm::X86TargetLowering::X86TargetLowering().

◆ setHasExtractBitsInsn()

void llvm::TargetLoweringBase::setHasExtractBitsInsn ( bool  hasExtractInsn = true)
inlineprotected

Tells the code generator that the target has BitExtract instructions.

The code generator will aggressively sink "shift"s into the blocks of their users if the users will generate "and" instructions which can be combined with "shift" to BitExtract instructions.

Definition at line 1666 of file TargetLowering.h.

Referenced by llvm::AArch64TargetLowering::AArch64TargetLowering(), and llvm::AMDGPUTargetLowering::AMDGPUTargetLowering().

◆ setHasFloatingPointExceptions()

void llvm::TargetLoweringBase::setHasFloatingPointExceptions ( bool  FPExceptions = true)
inlineprotected

Tells the code generator that this target supports floating point exceptions and cares about preserving floating point exception behavior.

Definition at line 1677 of file TargetLowering.h.

Referenced by llvm::AMDGPUTargetLowering::AMDGPUTargetLowering(), and llvm::WebAssemblyTargetLowering::WebAssemblyTargetLowering().

◆ setHasMultipleConditionRegisters()

void llvm::TargetLoweringBase::setHasMultipleConditionRegisters ( bool  hasManyRegs = true)
inlineprotected

Tells the code generator that the target has multiple (allocatable) condition registers that can be used to store the results of comparisons for use by selects and conditional branches.

With multiple condition registers, the code generator will not aggressively sink comparisons into the blocks of their users.

Definition at line 1658 of file TargetLowering.h.

Referenced by llvm::AMDGPUTargetLowering::AMDGPUTargetLowering(), and llvm::PPCTargetLowering::PPCTargetLowering().

◆ setIndexedLoadAction()

void llvm::TargetLoweringBase::setIndexedLoadAction ( unsigned  IdxMode,
MVT  VT,
LegalizeAction  Action 
)
inlineprotected

◆ setIndexedStoreAction()

void llvm::TargetLoweringBase::setIndexedStoreAction ( unsigned  IdxMode,
MVT  VT,
LegalizeAction  Action 
)
inlineprotected

Indicate that the specified indexed store does or does not work with the specified type and indicate what to do about it.

NOTE: All indexed mode stores are initialized to Expand in TargetLowering.cpp

Definition at line 1751 of file TargetLowering.h.

References assert(), llvm::MVT::isValid(), llvm::ISD::LAST_INDEXED_MODE, and llvm::MVT::SimpleTy.

Referenced by llvm::AArch64TargetLowering::AArch64TargetLowering(), llvm::ARMTargetLowering::ARMTargetLowering(), llvm::AVRTargetLowering::AVRTargetLowering(), llvm::HexagonTargetLowering::HexagonTargetLowering(), initActions(), and llvm::PPCTargetLowering::PPCTargetLowering().

◆ setJumpBufAlignment()

void llvm::TargetLoweringBase::setJumpBufAlignment ( unsigned  Align)
inlineprotected

Set the target's required jmp_buf buffer alignment (in bytes); default is 0.

Definition at line 1805 of file TargetLowering.h.

References llvm::AMDGPU::HSAMD::Kernel::Arg::Key::Align.

◆ setJumpBufSize()

void llvm::TargetLoweringBase::setJumpBufSize ( unsigned  Size)
inlineprotected

Set the target's required jmp_buf buffer size (in bytes); default is 200.

Definition at line 1799 of file TargetLowering.h.

References llvm::AMDGPU::HSAMD::Kernel::Arg::Key::Size.

◆ setJumpIsExpensive()

void TargetLoweringBase::setJumpIsExpensive ( bool  isExpensive = true)
protected

◆ setLibcallCallingConv()

void llvm::TargetLoweringBase::setLibcallCallingConv ( RTLIB::Libcall  Call,
CallingConv::ID  CC 
)
inline

◆ setLibcallName()

void llvm::TargetLoweringBase::setLibcallName ( RTLIB::Libcall  Call,
const char Name 
)
inline

◆ setLoadExtAction()

void llvm::TargetLoweringBase::setLoadExtAction ( unsigned  ExtType,
MVT  ValVT,
MVT  MemVT,
LegalizeAction  Action 
)
inlineprotected

◆ setMaxAtomicSizeInBitsSupported()

void llvm::TargetLoweringBase::setMaxAtomicSizeInBitsSupported ( unsigned  SizeInBits)
inlineprotected

Set the maximum atomic operation size supported by the backend.

Atomic operations greater than this size (as well as ones that are not naturally aligned), will be expanded by AtomicExpandPass into an __atomic_* library call.

Definition at line 1838 of file TargetLowering.h.

Referenced by llvm::HexagonTargetLowering::HexagonTargetLowering(), llvm::SparcTargetLowering::SparcTargetLowering(), and llvm::WebAssemblyTargetLowering::WebAssemblyTargetLowering().

◆ setMaximumJumpTableSize()

void TargetLoweringBase::setMaximumJumpTableSize ( unsigned  Val)
protected

Indicate the maximum number of entries in jump tables.

Set to zero to generate unlimited jump tables.

Definition at line 1583 of file TargetLoweringBase.cpp.

References MaximumJumpTableSize.

Referenced by llvm::AArch64TargetLowering::AArch64TargetLowering().

◆ setMinCmpXchgSizeInBits()

void llvm::TargetLoweringBase::setMinCmpXchgSizeInBits ( unsigned  SizeInBits)
inlineprotected

◆ setMinFunctionAlignment()

void llvm::TargetLoweringBase::setMinFunctionAlignment ( unsigned  Align)
inlineprotected

◆ setMinimumJumpTableEntries()

void TargetLoweringBase::setMinimumJumpTableEntries ( unsigned  Val)
protected

◆ setMinStackArgumentAlignment()

void llvm::TargetLoweringBase::setMinStackArgumentAlignment ( unsigned  Align)
inlineprotected

Set the minimum stack alignment of an argument (in log2(bytes)).

Definition at line 1830 of file TargetLowering.h.

References llvm::AMDGPU::HSAMD::Kernel::Arg::Key::Align.

Referenced by llvm::ARMTargetLowering::ARMTargetLowering(), llvm::MipsTargetLowering::MipsTargetLowering(), and llvm::PPCTargetLowering::PPCTargetLowering().

◆ setOperationAction()

void llvm::TargetLoweringBase::setOperationAction ( unsigned  Op,
MVT  VT,
LegalizeAction  Action 
)
inlineprotected

Indicate that the specified operation does not work with the specified type and indicate what to do about it.

Note that VT may refer to either the type of a result or that of an operand of Op.

Definition at line 1706 of file TargetLowering.h.

References llvm::array_lengthof(), assert(), and llvm::MVT::SimpleTy.

Referenced by llvm::AArch64TargetLowering::AArch64TargetLowering(), llvm::MipsSETargetLowering::addMSAFloatType(), llvm::MipsSETargetLowering::addMSAIntType(), llvm::AMDGPUTargetLowering::AMDGPUTargetLowering(), llvm::ARCTargetLowering::ARCTargetLowering(), llvm::ARMTargetLowering::ARMTargetLowering(), llvm::AVRTargetLowering::AVRTargetLowering(), llvm::BPFTargetLowering::BPFTargetLowering(), llvm::HexagonTargetLowering::HexagonTargetLowering(), initActions(), llvm::LanaiTargetLowering::LanaiTargetLowering(), llvm::Mips16TargetLowering::Mips16TargetLowering(), llvm::MipsSETargetLowering::MipsSETargetLowering(), llvm::MipsTargetLowering::MipsTargetLowering(), llvm::MSP430TargetLowering::MSP430TargetLowering(), llvm::NVPTXTargetLowering::NVPTXTargetLowering(), llvm::PPCTargetLowering::PPCTargetLowering(), llvm::R600TargetLowering::R600TargetLowering(), llvm::RISCVTargetLowering::RISCVTargetLowering(), llvm::SITargetLowering::SITargetLowering(), llvm::SparcTargetLowering::SparcTargetLowering(), llvm::SystemZTargetLowering::SystemZTargetLowering(), llvm::WebAssemblyTargetLowering::WebAssemblyTargetLowering(), llvm::X86TargetLowering::X86TargetLowering(), and llvm::XCoreTargetLowering::XCoreTargetLowering().

◆ setOperationPromotedToType()

void llvm::TargetLoweringBase::setOperationPromotedToType ( unsigned  Opc,
MVT  OrigVT,
MVT  DestVT 
)
inlineprotected

Convenience method to set an operation to Promote and specify the type in a single call.

Definition at line 1785 of file TargetLowering.h.

Referenced by llvm::X86TargetLowering::X86TargetLowering().

◆ setPrefFunctionAlignment()

void llvm::TargetLoweringBase::setPrefFunctionAlignment ( unsigned  Align)
inlineprotected

◆ setPrefLoopAlignment()

void llvm::TargetLoweringBase::setPrefLoopAlignment ( unsigned  Align)
inlineprotected

Set the target's preferred loop alignment.

Default alignment is zero, it means the target does not care about loop alignment. The alignment is specified in log2(bytes). The target may also override getPrefLoopAlignment to provide per-loop values.

Definition at line 1825 of file TargetLowering.h.

References llvm::AMDGPU::HSAMD::Kernel::Arg::Key::Align.

Referenced by llvm::AArch64TargetLowering::AArch64TargetLowering(), llvm::HexagonTargetLowering::HexagonTargetLowering(), llvm::PPCTargetLowering::PPCTargetLowering(), and llvm::X86TargetLowering::X86TargetLowering().

◆ setSchedulingPreference()

void llvm::TargetLoweringBase::setSchedulingPreference ( Sched::Preference  Pref)
inlineprotected

◆ setStackPointerRegisterToSaveRestore()

void llvm::TargetLoweringBase::setStackPointerRegisterToSaveRestore ( unsigned  R)
inlineprotected

◆ setTargetDAGCombine()

void llvm::TargetLoweringBase::setTargetDAGCombine ( ISD::NodeType  NT)
inlineprotected

◆ setTruncStoreAction()

void llvm::TargetLoweringBase::setTruncStoreAction ( MVT  ValVT,
MVT  MemVT,
LegalizeAction  Action 
)
inlineprotected

◆ setUseUnderscoreLongJmp()

void llvm::TargetLoweringBase::setUseUnderscoreLongJmp ( bool  Val)
inlineprotected

Indicate whether this target prefers to use _longjmp to implement llvm.longjmp or the version without _.

Defaults to false.

Definition at line 1636 of file TargetLowering.h.

Referenced by llvm::PPCTargetLowering::PPCTargetLowering(), and llvm::X86TargetLowering::X86TargetLowering().

◆ setUseUnderscoreSetJmp()

void llvm::TargetLoweringBase::setUseUnderscoreSetJmp ( bool  Val)
inlineprotected

Indicate whether this target prefers to use _setjmp to implement llvm.setjmp or the version without _.

Defaults to false.

Definition at line 1630 of file TargetLowering.h.

Referenced by llvm::PPCTargetLowering::PPCTargetLowering(), and llvm::X86TargetLowering::X86TargetLowering().

◆ shouldAlignPointerArgs()

virtual bool llvm::TargetLoweringBase::shouldAlignPointerArgs ( CallInst ,
unsigned ,
unsigned  
) const
inlinevirtual

Return true if the pointer arguments to CI should be aligned by aligning the object whose address is being passed.

If so then MinSize is set to the minimum size the object must be to be aligned and PrefAlign is set to the preferred alignment.

Reimplemented in llvm::ARMTargetLowering.

Definition at line 1398 of file TargetLowering.h.

◆ shouldConvertConstantLoadToIntImm()

virtual bool llvm::TargetLoweringBase::shouldConvertConstantLoadToIntImm ( const APInt Imm,
Type Ty 
) const
inlinevirtual

Return true if it is beneficial to convert a load of a constant to just the constant itself.

On some targets it might be more efficient to use a combination of arithmetic instructions to materialize the constant instead of loading it from a constant pool.

Reimplemented in llvm::X86TargetLowering, llvm::PPCTargetLowering, llvm::ARMTargetLowering, llvm::AArch64TargetLowering, and llvm::SITargetLowering.

Definition at line 2181 of file TargetLowering.h.

Referenced by getMemsetStringVal().

◆ shouldExpandAtomicCmpXchgInIR()

virtual bool llvm::TargetLoweringBase::shouldExpandAtomicCmpXchgInIR ( AtomicCmpXchgInst AI) const
inlinevirtual

Returns true if the given atomic cmpxchg should be expanded by the IR-level AtomicExpand pass into a load-linked/store-conditional sequence (through emitLoadLinked() and emitStoreConditional()).

Reimplemented in llvm::ARMTargetLowering, llvm::AArch64TargetLowering, and llvm::HexagonTargetLowering.

Definition at line 1539 of file TargetLowering.h.

◆ shouldExpandAtomicLoadInIR()

virtual AtomicExpansionKind llvm::TargetLoweringBase::shouldExpandAtomicLoadInIR ( LoadInst LI) const
inlinevirtual

Returns how the given (atomic) load should be expanded by the IR-level AtomicExpand pass.

Reimplemented in llvm::ARMTargetLowering, llvm::AArch64TargetLowering, and llvm::HexagonTargetLowering.

Definition at line 1532 of file TargetLowering.h.

References llvm::None.

◆ shouldExpandAtomicRMWInIR()

virtual AtomicExpansionKind llvm::TargetLoweringBase::shouldExpandAtomicRMWInIR ( AtomicRMWInst ) const
inlinevirtual

Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW, if at all.

Default is to never expand.

Reimplemented in llvm::ARMTargetLowering, llvm::AArch64TargetLowering, llvm::HexagonTargetLowering, and llvm::SparcTargetLowering.

Definition at line 1545 of file TargetLowering.h.

References llvm::None.

◆ shouldExpandAtomicStoreInIR()

virtual bool llvm::TargetLoweringBase::shouldExpandAtomicStoreInIR ( StoreInst SI) const
inlinevirtual

Returns true if the given (atomic) store should be expanded by the IR-level AtomicExpand pass into an "atomic xchg" which ignores its input.

Reimplemented in llvm::ARMTargetLowering, llvm::AArch64TargetLowering, and llvm::HexagonTargetLowering.

Definition at line 1521 of file TargetLowering.h.

◆ shouldExpandBuildVectorWithShuffles()

virtual bool llvm::TargetLoweringBase::shouldExpandBuildVectorWithShuffles ( EVT  ,
unsigned  DefinedValues 
) const
inlinevirtual

◆ shouldInsertFencesForAtomic()

virtual bool llvm::TargetLoweringBase::shouldInsertFencesForAtomic ( const Instruction I) const
inlinevirtual

Whether AtomicExpandPass should automatically insert fences and reduce ordering for this atomic.

This should be true for most architectures with weak memory ordering. Defaults to false.

Reimplemented in llvm::PPCTargetLowering, llvm::ARMTargetLowering, and llvm::SparcTargetLowering.

Definition at line 1440 of file TargetLowering.h.

◆ shouldNormalizeToSelectSequence()

virtual bool llvm::TargetLoweringBase::shouldNormalizeToSelectSequence ( LLVMContext Context,
EVT  VT 
) const
inlinevirtual

Returns true if we should normalize select(N0&N1, X, Y) => select(N0, select(N1, X, Y), Y) and select(N0|N1, X, Y) => select(N0, select(N1, X, Y, Y)) if it is likely that it saves us from materializing N0 and N1 in an integer register.

Targets that are able to perform and/or on flags should return false here.

Definition at line 1578 of file TargetLowering.h.

Referenced by combineMinNumMaxNum().

◆ shouldReduceLoadWidth()

virtual bool llvm::TargetLoweringBase::shouldReduceLoadWidth ( SDNode Load,
ISD::LoadExtType  ExtTy,
EVT  NewVT 
) const
inlinevirtual

Reimplemented in llvm::X86TargetLowering, and llvm::AMDGPUTargetLowering.

Definition at line 1144 of file TargetLowering.h.

Referenced by isTruncateOf(), peekThroughBitcast(), and simplifyDivRem().

◆ ShouldShrinkFPConstant()

virtual bool llvm::TargetLoweringBase::ShouldShrinkFPConstant ( EVT  ) const
inlinevirtual

If true, then instruction selection should seek to shrink the FP constant of the specified type to a smaller type in order to save space and / or reduce runtime.

Reimplemented in llvm::X86TargetLowering, llvm::SparcTargetLowering, and llvm::AMDGPUTargetLowering.

Definition at line 1138 of file TargetLowering.h.

◆ shouldSignExtendTypeInLibCall()

virtual bool llvm::TargetLoweringBase::shouldSignExtendTypeInLibCall ( EVT  Type,
bool  IsSigned 
) const
inlinevirtual

Returns true if arguments should be sign-extended in lib calls.

Definition at line 1526 of file TargetLowering.h.

Referenced by llvm::TargetLowering::makeLibCall().

◆ storeOfVectorConstantIsCheap()

virtual bool llvm::TargetLoweringBase::storeOfVectorConstantIsCheap ( EVT  MemVT,
unsigned  NumElem,
unsigned  AddrSpace 
) const
inlinevirtual

Return true if it is expected to be cheaper to do a store of a non-zero vector constant with the given size and type for the address space than to store the individual scalar element constants.

Reimplemented in llvm::X86TargetLowering, and llvm::AMDGPUTargetLowering.

Definition at line 407 of file TargetLowering.h.

Referenced by peekThroughBitcast().

◆ useSoftFloat()

virtual bool llvm::TargetLoweringBase::useSoftFloat ( ) const
inlinevirtual

◆ usesUnderscoreLongJmp()

bool llvm::TargetLoweringBase::usesUnderscoreLongJmp ( ) const
inline

Determine if we should use _longjmp or longjmp to implement llvm.longjmp.

Definition at line 1272 of file TargetLowering.h.

Referenced by getUnderlyingArgReg().

◆ usesUnderscoreSetJmp()

bool llvm::TargetLoweringBase::usesUnderscoreSetJmp ( ) const
inline

Determine if we should use _setjmp or setjmp to implement llvm.setjmp.

Definition at line 1267 of file TargetLowering.h.

Referenced by getUnderlyingArgReg().

Member Data Documentation

◆ EnableExtLdPromotion

bool llvm::TargetLoweringBase::EnableExtLdPromotion
protected

◆ GatherAllAliasesMaxDepth

unsigned llvm::TargetLoweringBase::GatherAllAliasesMaxDepth
protected

Depth that GatherAllAliases should should continue looking for chain dependencies when trying to find a more preferable chain.

As an approximation, this should be more than the number of consecutive stores expected to be merged.

Definition at line 2432 of file TargetLowering.h.

Referenced by llvm::AMDGPUTargetLowering::AMDGPUTargetLowering(), and TargetLoweringBase().

◆ MaxLoadsPerMemcmp

unsigned llvm::TargetLoweringBase::MaxLoadsPerMemcmp
protected

◆ MaxLoadsPerMemcmpOptSize

unsigned llvm::TargetLoweringBase::MaxLoadsPerMemcmpOptSize
protected

◆ MaxStoresPerMemcpy

unsigned llvm::TargetLoweringBase::MaxStoresPerMemcpy
protected

Specify maximum bytes of store instructions per memcpy call.

When lowering @llvm.memcpy this field specifies the maximum number of store operations that may be substituted for a call to memcpy. Targets must set this value based on the cost threshold for that target. Targets should assume that the memcpy will be done using as many of the largest store operations first, followed by smaller ones, if necessary, per alignment restrictions. For example, storing 7 bytes on a 32-bit machine with 32-bit alignment would result in one 4-byte store, a one 2-byte store and one 1-byte store. This only applies to copying a constant array of constant size.

Definition at line 2461 of file TargetLowering.h.

Referenced by llvm::AArch64TargetLowering::AArch64TargetLowering(), llvm::AMDGPUTargetLowering::AMDGPUTargetLowering(), llvm::ARMTargetLowering::ARMTargetLowering(), llvm::BPFTargetLowering::BPFTargetLowering(), llvm::HexagonTargetLowering::HexagonTargetLowering(), llvm::LanaiTargetLowering::LanaiTargetLowering(), llvm::MipsTargetLowering::MipsTargetLowering(), llvm::NVPTXTargetLowering::NVPTXTargetLowering(), llvm::PPCTargetLowering::PPCTargetLowering(), llvm::SystemZTargetLowering::SystemZTargetLowering(), TargetLoweringBase(), llvm::X86TargetLowering::X86TargetLowering(), and llvm::XCoreTargetLowering::XCoreTargetLowering().

◆ MaxStoresPerMemcpyOptSize

unsigned llvm::TargetLoweringBase::MaxStoresPerMemcpyOptSize
protected

◆ MaxStoresPerMemmove

unsigned llvm::TargetLoweringBase::MaxStoresPerMemmove
protected

Specify maximum bytes of store instructions per memmove call.

When lowering @llvm.memmove this field specifies the maximum number of store instructions that may be substituted for a call to memmove. Targets must set this value based on the cost threshold for that target. Targets should assume that the memmove will be done using as many of the largest store operations first, followed by smaller ones, if necessary, per alignment restrictions. For example, moving 9 bytes on a 32-bit machine with 8-bit alignment would result in nine 1-byte stores. This only applies to copying a constant array of constant size.

Definition at line 2479 of file TargetLowering.h.

Referenced by llvm::AArch64TargetLowering::AArch64TargetLowering(), llvm::AMDGPUTargetLowering::AMDGPUTargetLowering(), llvm::ARMTargetLowering::ARMTargetLowering(), llvm::BPFTargetLowering::BPFTargetLowering(), llvm::HexagonTargetLowering::HexagonTargetLowering(), llvm::LanaiTargetLowering::LanaiTargetLowering(), llvm::NVPTXTargetLowering::NVPTXTargetLowering(), llvm::PPCTargetLowering::PPCTargetLowering(), TargetLoweringBase(), llvm::X86TargetLowering::X86TargetLowering(), and llvm::XCoreTargetLowering::XCoreTargetLowering().

◆ MaxStoresPerMemmoveOptSize

unsigned llvm::TargetLoweringBase::MaxStoresPerMemmoveOptSize
protected

◆ MaxStoresPerMemset

unsigned llvm::TargetLoweringBase::MaxStoresPerMemset
protected

Specify maximum number of store instructions per memset call.

When lowering @llvm.memset this field specifies the maximum number of store operations that may be substituted for the call to memset. Targets must set this value based on the cost threshold for that target. Targets should assume that the memset will be done using as many of the largest store operations first, followed by smaller ones, if necessary, per alignment restrictions. For example, storing 9 bytes on a 32-bit machine with 16-bit alignment would result in four 2-byte stores and one 1-byte store. This only applies to setting a constant array of a constant size.

Definition at line 2444 of file TargetLowering.h.

Referenced by llvm::AArch64TargetLowering::AArch64TargetLowering(), llvm::AMDGPUTargetLowering::AMDGPUTargetLowering(), llvm::ARMTargetLowering::ARMTargetLowering(), llvm::BPFTargetLowering::BPFTargetLowering(), llvm::HexagonTargetLowering::HexagonTargetLowering(), llvm::LanaiTargetLowering::LanaiTargetLowering(), llvm::NVPTXTargetLowering::NVPTXTargetLowering(), llvm::PPCTargetLowering::PPCTargetLowering(), llvm::SystemZTargetLowering::SystemZTargetLowering(), TargetLoweringBase(), llvm::X86TargetLowering::X86TargetLowering(), and llvm::XCoreTargetLowering::XCoreTargetLowering().

◆ MaxStoresPerMemsetOptSize

unsigned llvm::TargetLoweringBase::MaxStoresPerMemsetOptSize
protected

◆ PredictableSelectIsExpensive

bool llvm::TargetLoweringBase::PredictableSelectIsExpensive
protected

Tells the code generator that select is more expensive than a branch if the branch is usually predicted right.

Definition at line 2487 of file TargetLowering.h.

Referenced by llvm::AArch64TargetLowering::AArch64TargetLowering(), llvm::AMDGPUTargetLowering::AMDGPUTargetLowering(), llvm::ARMTargetLowering::ARMTargetLowering(), TargetLoweringBase(), and llvm::X86TargetLowering::X86TargetLowering().

◆ ValueTypeActions

ValueTypeActionImpl llvm::TargetLoweringBase::ValueTypeActions
protected

The documentation for this class was generated from the following files: