LLVM  9.0.0svn
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1 //===-- R600ISelLowering.h - R600 DAG Lowering Interface -*- C++ -*--------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 /// R600 DAG Lowering interface definition
11 //
12 //===----------------------------------------------------------------------===//
17 #include "AMDGPUISelLowering.h"
19 namespace llvm {
21 class R600InstrInfo;
22 class R600Subtarget;
26  const R600Subtarget *Subtarget;
27 public:
28  R600TargetLowering(const TargetMachine &TM, const R600Subtarget &STI);
30  const R600Subtarget *getSubtarget() const;
34  MachineBasicBlock *BB) const override;
35  SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
36  SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
37  void ReplaceNodeResults(SDNode * N,
39  SelectionDAG &DAG) const override;
40  CCAssignFn *CCAssignFnForCall(CallingConv::ID CC, bool IsVarArg) const;
42  bool isVarArg,
44  const SDLoc &DL, SelectionDAG &DAG,
45  SmallVectorImpl<SDValue> &InVals) const override;
47  EVT VT) const override;
49  bool canMergeStoresTo(unsigned AS, EVT MemVT,
50  const SelectionDAG &DAG) const override;
52  bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS,
53  unsigned Align,
54  bool *IsFast) const override;
56 private:
57  unsigned Gen;
58  /// Each OpenCL kernel has nine implicit parameters that are stored in the
59  /// first nine dwords of a Vertex Buffer. These implicit parameters are
60  /// lowered to load instructions which retrieve the values from the Vertex
61  /// Buffer.
62  SDValue LowerImplicitParameter(SelectionDAG &DAG, EVT VT, const SDLoc &DL,
63  unsigned DwordOffset) const;
65  void lowerImplicitParameter(MachineInstr *MI, MachineBasicBlock &BB,
66  MachineRegisterInfo & MRI, unsigned dword_offset) const;
67  SDValue OptimizeSwizzle(SDValue BuildVector, SDValue Swz[], SelectionDAG &DAG,
68  const SDLoc &DL) const;
69  SDValue vectorToVerticalVector(SelectionDAG &DAG, SDValue Vector) const;
71  SDValue lowerFrameIndex(SDValue Op, SelectionDAG &DAG) const;
72  SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
73  SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
74  SDValue LowerGlobalAddress(AMDGPUMachineFunction *MFI, SDValue Op,
75  SelectionDAG &DAG) const override;
76  SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
78  SDValue lowerPrivateTruncStore(StoreSDNode *Store, SelectionDAG &DAG) const;
79  SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
80  SDValue lowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG) const;
81  SDValue lowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const;
83  SDValue lowerPrivateExtLoad(SDValue Op, SelectionDAG &DAG) const;
84  SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
85  SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
86  SDValue LowerTrig(SDValue Op, SelectionDAG &DAG) const;
87  SDValue LowerSHLParts(SDValue Op, SelectionDAG &DAG) const;
88  SDValue LowerSRXParts(SDValue Op, SelectionDAG &DAG) const;
89  SDValue LowerUADDSUBO(SDValue Op, SelectionDAG &DAG,
90  unsigned mainop, unsigned ovf) const;
92  SDValue stackPtrToRegIndex(SDValue Ptr, unsigned StackWidth,
93  SelectionDAG &DAG) const;
94  void getStackAddress(unsigned StackWidth, unsigned ElemIdx,
95  unsigned &Channel, unsigned &PtrIncr) const;
96  bool isZero(SDValue Op) const;
97  bool isHWTrueValue(SDValue Op) const;
98  bool isHWFalseValue(SDValue Op) const;
100  bool FoldOperand(SDNode *ParentNode, unsigned SrcIdx, SDValue &Src,
101  SDValue &Neg, SDValue &Abs, SDValue &Sel, SDValue &Imm,
102  SelectionDAG &DAG) const;
103  SDValue constBufferLoad(LoadSDNode *LoadNode, int Block,
104  SelectionDAG &DAG) const;
106  SDNode *PostISelFolding(MachineSDNode *N, SelectionDAG &DAG) const override;
107 };
109 } // End namespace llvm;
111 #endif
A parsed version of the target data layout string in and methods for querying it. ...
Definition: DataLayout.h:110
constexpr char Align[]
Key for Kernel::Arg::Metadata::mAlign.
This class represents lattice values for constants.
Definition: AllocatorList.h:23
bool canMergeStoresTo(unsigned AS, EVT MemVT, const SelectionDAG &DAG) const override
Returns if it&#39;s reasonable to merge stores to MemVT size.
bool CCAssignFn(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
CCAssignFn - This function assigns a location for Val, updating State to reflect the change...
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *BB) const override
This method should be implemented by targets that mark instructions with the &#39;usesCustomInserter&#39; fla...
Function Alias Analysis Results
CCAssignFn * CCAssignFnForCall(CallingConv::ID CC, bool IsVarArg) const
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:41
const R600Subtarget * getSubtarget() const
This class is used to represent ISD::STORE nodes.
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
This callback is invoked for operations that are unsupported by the target, which are registered to u...
unsigned const MachineRegisterInfo * MRI
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:68
SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::InputArg > &Ins, const SDLoc &DL, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals) const override
XXX Only kernel functions are supported, so we can assume for now that every function is a kernel fun...
Extended Value Type.
Definition: ValueTypes.h:33
void ReplaceNodeResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
This callback is invoked when a node result type is illegal for the target, and the operation was reg...
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:221
Interface definition of the TargetLowering class that is common to all AMD GPUs.
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override
This method will be invoked for all target nodes and for any target-independent nodes that the target...
An SDNode that represents everything that will be needed to construct a MachineInstr.
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Represents one node in the SelectionDAG.
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
Representation of each machine instruction.
Definition: MachineInstr.h:63
R600TargetLowering(const TargetMachine &TM, const R600Subtarget &STI)
#define N
bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS, unsigned Align, bool *IsFast) const override
Determine if the target supports unaligned memory accesses.
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:58
IRTranslator LLVM IR MI
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation...
EVT getSetCCResultType(const DataLayout &DL, LLVMContext &, EVT VT) const override
Return the ValueType of the result of SETCC operations.
This class is used to represent ISD::LOAD nodes.