LLVM  7.0.0svn
Public Types | Public Member Functions | Friends | List of all members
llvm::MachineInstr Class Reference

Representation of each machine instruction. More...

#include "llvm/CodeGen/MachineInstr.h"

Inheritance diagram for llvm::MachineInstr:
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Public Types

enum  CommentFlag { ReloadReuse = 0x1, NoSchedComment = 0x2, TAsmComments = 0x4 }
 Flags to specify different kinds of comments to output in assembly code. More...
 
enum  MIFlag {
  NoFlags = 0, FrameSetup = 1 << 0, FrameDestroy = 1 << 1, BundledPred = 1 << 2,
  BundledSucc = 1 << 3
}
 
enum  QueryType { IgnoreBundle, AnyInBundle, AllInBundle }
 API for querying MachineInstr properties. More...
 
enum  MICheckType { CheckDefs, CheckKillDead, IgnoreDefs, IgnoreVRegDefs }
 
using mmo_iterator = MachineMemOperand **
 
using mop_iterator = MachineOperand *
 iterator/begin/end - Iterate over all operands of a machine instruction. More...
 
using const_mop_iterator = const MachineOperand *
 

Public Member Functions

 MachineInstr (const MachineInstr &)=delete
 
MachineInstroperator= (const MachineInstr &)=delete
 
 ~MachineInstr ()=delete
 
const MachineBasicBlockgetParent () const
 
MachineBasicBlockgetParent ()
 
const MachineFunctiongetMF () const
 Return the function that contains the basic block that this instruction belongs to. More...
 
MachineFunctiongetMF ()
 
uint8_t getAsmPrinterFlags () const
 Return the asm printer flags bitvector. More...
 
void clearAsmPrinterFlags ()
 Clear the AsmPrinter bitvector. More...
 
bool getAsmPrinterFlag (CommentFlag Flag) const
 Return whether an AsmPrinter flag is set. More...
 
void setAsmPrinterFlag (uint8_t Flag)
 Set a flag for the AsmPrinter. More...
 
void clearAsmPrinterFlag (CommentFlag Flag)
 Clear specific AsmPrinter flags. More...
 
uint8_t getFlags () const
 Return the MI flags bitvector. More...
 
bool getFlag (MIFlag Flag) const
 Return whether an MI flag is set. More...
 
void setFlag (MIFlag Flag)
 Set a MI flag. More...
 
void setFlags (unsigned flags)
 
void clearFlag (MIFlag Flag)
 clearFlag - Clear a MI flag. More...
 
bool isInsideBundle () const
 Return true if MI is in a bundle (but not the first MI in a bundle). More...
 
bool isBundled () const
 Return true if this instruction part of a bundle. More...
 
bool isBundledWithPred () const
 Return true if this instruction is part of a bundle, and it is not the first instruction in the bundle. More...
 
bool isBundledWithSucc () const
 Return true if this instruction is part of a bundle, and it is not the last instruction in the bundle. More...
 
void bundleWithPred ()
 Bundle this instruction with its predecessor. More...
 
void bundleWithSucc ()
 Bundle this instruction with its successor. More...
 
void unbundleFromPred ()
 Break bundle above this instruction. More...
 
void unbundleFromSucc ()
 Break bundle below this instruction. More...
 
const DebugLocgetDebugLoc () const
 Returns the debug location id of this MachineInstr. More...
 
const DILocalVariablegetDebugVariable () const
 Return the debug variable referenced by this DBG_VALUE instruction. More...
 
const DIExpressiongetDebugExpression () const
 Return the complex address expression referenced by this DBG_VALUE instruction. More...
 
void emitError (StringRef Msg) const
 Emit an error referring to the source location of this instruction. More...
 
const MCInstrDescgetDesc () const
 Returns the target instruction descriptor of this MachineInstr. More...
 
unsigned getOpcode () const
 Returns the opcode of this MachineInstr. More...
 
unsigned getNumOperands () const
 Access to explicit operands of the instruction. More...
 
const MachineOperandgetOperand (unsigned i) const
 
MachineOperandgetOperand (unsigned i)
 
bool isOperandSubregIdx (unsigned OpIdx) const
 Return true if operand OpIdx is a subregister index. More...
 
unsigned getNumExplicitOperands () const
 Returns the number of non-implicit operands. More...
 
mop_iterator operands_begin ()
 
mop_iterator operands_end ()
 
const_mop_iterator operands_begin () const
 
const_mop_iterator operands_end () const
 
iterator_range< mop_iteratoroperands ()
 
iterator_range< const_mop_iteratoroperands () const
 
iterator_range< mop_iteratorexplicit_operands ()
 
iterator_range< const_mop_iteratorexplicit_operands () const
 
iterator_range< mop_iteratorimplicit_operands ()
 
iterator_range< const_mop_iteratorimplicit_operands () const
 
iterator_range< mop_iteratordefs ()
 Returns a range over all explicit operands that are register definitions. More...
 
iterator_range< const_mop_iteratordefs () const
 Returns a range over all explicit operands that are register definitions. More...
 
iterator_range< mop_iteratoruses ()
 Returns a range that includes all operands that are register uses. More...
 
iterator_range< const_mop_iteratoruses () const
 Returns a range that includes all operands that are register uses. More...
 
iterator_range< mop_iteratorexplicit_uses ()
 
iterator_range< const_mop_iteratorexplicit_uses () const
 
unsigned getOperandNo (const_mop_iterator I) const
 Returns the number of the operand iterator I points to. More...
 
mmo_iterator memoperands_begin () const
 Access to memory operands of the instruction. More...
 
mmo_iterator memoperands_end () const
 
bool memoperands_empty () const
 Return true if we don't have any memory operands which described the memory access done by this instruction. More...
 
iterator_range< mmo_iteratormemoperands ()
 
iterator_range< mmo_iteratormemoperands () const
 
bool hasOneMemOperand () const
 Return true if this instruction has exactly one MachineMemOperand. More...
 
unsigned getNumMemOperands () const
 Return the number of memory operands. More...
 
bool hasProperty (unsigned MCFlag, QueryType Type=AnyInBundle) const
 Return true if the instruction (or in the case of a bundle, the instructions inside the bundle) has the specified property. More...
 
bool isVariadic (QueryType Type=IgnoreBundle) const
 Return true if this instruction can have a variable number of operands. More...
 
bool hasOptionalDef (QueryType Type=IgnoreBundle) const
 Set if this instruction has an optional definition, e.g. More...
 
bool isPseudo (QueryType Type=IgnoreBundle) const
 Return true if this is a pseudo instruction that doesn't correspond to a real machine instruction. More...
 
bool isReturn (QueryType Type=AnyInBundle) const
 
bool isCall (QueryType Type=AnyInBundle) const
 
bool isBarrier (QueryType Type=AnyInBundle) const
 Returns true if the specified instruction stops control flow from executing the instruction immediately following it. More...
 
bool isTerminator (QueryType Type=AnyInBundle) const
 Returns true if this instruction part of the terminator for a basic block. More...
 
bool isBranch (QueryType Type=AnyInBundle) const
 Returns true if this is a conditional, unconditional, or indirect branch. More...
 
bool isIndirectBranch (QueryType Type=AnyInBundle) const
 Return true if this is an indirect branch, such as a branch through a register. More...
 
bool isConditionalBranch (QueryType Type=AnyInBundle) const
 Return true if this is a branch which may fall through to the next instruction or may transfer control flow to some other block. More...
 
bool isUnconditionalBranch (QueryType Type=AnyInBundle) const
 Return true if this is a branch which always transfers control flow to some other block. More...
 
bool isPredicable (QueryType Type=AllInBundle) const
 Return true if this instruction has a predicate operand that controls execution. More...
 
bool isCompare (QueryType Type=IgnoreBundle) const
 Return true if this instruction is a comparison. More...
 
bool isMoveImmediate (QueryType Type=IgnoreBundle) const
 Return true if this instruction is a move immediate (including conditional moves) instruction. More...
 
bool isBitcast (QueryType Type=IgnoreBundle) const
 Return true if this instruction is a bitcast instruction. More...
 
bool isSelect (QueryType Type=IgnoreBundle) const
 Return true if this instruction is a select instruction. More...
 
bool isNotDuplicable (QueryType Type=AnyInBundle) const
 Return true if this instruction cannot be safely duplicated. More...
 
bool isConvergent (QueryType Type=AnyInBundle) const
 Return true if this instruction is convergent. More...
 
bool hasDelaySlot (QueryType Type=AnyInBundle) const
 Returns true if the specified instruction has a delay slot which must be filled by the code generator. More...
 
bool canFoldAsLoad (QueryType Type=IgnoreBundle) const
 Return true for instructions that can be folded as memory operands in other instructions. More...
 
bool isRegSequenceLike (QueryType Type=IgnoreBundle) const
 Return true if this instruction behaves the same way as the generic REG_SEQUENCE instructions. More...
 
bool isExtractSubregLike (QueryType Type=IgnoreBundle) const
 Return true if this instruction behaves the same way as the generic EXTRACT_SUBREG instructions. More...
 
bool isInsertSubregLike (QueryType Type=IgnoreBundle) const
 Return true if this instruction behaves the same way as the generic INSERT_SUBREG instructions. More...
 
bool mayLoad (QueryType Type=AnyInBundle) const
 Return true if this instruction could possibly read memory. More...
 
bool mayStore (QueryType Type=AnyInBundle) const
 Return true if this instruction could possibly modify memory. More...
 
bool mayLoadOrStore (QueryType Type=AnyInBundle) const
 Return true if this instruction could possibly read or modify memory. More...
 
bool isCommutable (QueryType Type=IgnoreBundle) const
 Return true if this may be a 2- or 3-address instruction (of the form "X = op Y, Z, ..."), which produces the same result if Y and Z are exchanged. More...
 
bool isConvertibleTo3Addr (QueryType Type=IgnoreBundle) const
 Return true if this is a 2-address instruction which can be changed into a 3-address instruction if needed. More...
 
bool usesCustomInsertionHook (QueryType Type=IgnoreBundle) const
 Return true if this instruction requires custom insertion support when the DAG scheduler is inserting it into a machine basic block. More...
 
bool hasPostISelHook (QueryType Type=IgnoreBundle) const
 Return true if this instruction requires adjustment after instruction selection by calling a target hook. More...
 
bool isRematerializable (QueryType Type=AllInBundle) const
 Returns true if this instruction is a candidate for remat. More...
 
bool isAsCheapAsAMove (QueryType Type=AllInBundle) const
 Returns true if this instruction has the same cost (or less) than a move instruction. More...
 
bool hasExtraSrcRegAllocReq (QueryType Type=AnyInBundle) const
 Returns true if this instruction source operands have special register allocation requirements that are not captured by the operand register classes. More...
 
bool hasExtraDefRegAllocReq (QueryType Type=AnyInBundle) const
 Returns true if this instruction def operands have special register allocation requirements that are not captured by the operand register classes. More...
 
bool isIdenticalTo (const MachineInstr &Other, MICheckType Check=CheckDefs) const
 Return true if this instruction is identical to Other. More...
 
MachineInstrremoveFromParent ()
 Unlink 'this' from the containing basic block, and return it without deleting it. More...
 
MachineInstrremoveFromBundle ()
 Unlink this instruction from its basic block and return it without deleting it. More...
 
void eraseFromParent ()
 Unlink 'this' from the containing basic block and delete it. More...
 
void eraseFromParentAndMarkDBGValuesForRemoval ()
 Unlink 'this' from the containing basic block and delete it. More...
 
void eraseFromBundle ()
 Unlink 'this' form its basic block and delete it. More...
 
bool isEHLabel () const
 
bool isGCLabel () const
 
bool isAnnotationLabel () const
 
bool isLabel () const
 Returns true if the MachineInstr represents a label. More...
 
bool isCFIInstruction () const
 
bool isPosition () const
 
bool isDebugValue () const
 
bool isIndirectDebugValue () const
 A DBG_VALUE is indirect iff the first operand is a register and the second operand is an immediate. More...
 
bool isPHI () const
 
bool isKill () const
 
bool isImplicitDef () const
 
bool isInlineAsm () const
 
bool isMSInlineAsm () const
 
bool isStackAligningInlineAsm () const
 
InlineAsm::AsmDialect getInlineAsmDialect () const
 
bool isInsertSubreg () const
 
bool isSubregToReg () const
 
bool isRegSequence () const
 
bool isBundle () const
 
bool isCopy () const
 
bool isFullCopy () const
 
bool isExtractSubreg () const
 
bool isCopyLike () const
 Return true if the instruction behaves like a copy. More...
 
bool isIdentityCopy () const
 Return true is the instruction is an identity copy. More...
 
bool isMetaInstruction () const
 Return true if this instruction doesn't produce any output in the form of executable instructions. More...
 
bool isTransient () const
 Return true if this is a transient instruction that is either very likely to be eliminated during register allocation (such as copy-like instructions), or if this instruction doesn't have an execution-time cost. More...
 
unsigned getBundleSize () const
 Return the number of instructions inside the MI bundle, excluding the bundle header. More...
 
bool readsRegister (unsigned Reg, const TargetRegisterInfo *TRI=nullptr) const
 Return true if the MachineInstr reads the specified register. More...
 
bool readsVirtualRegister (unsigned Reg) const
 Return true if the MachineInstr reads the specified virtual register. More...
 
std::pair< bool, boolreadsWritesVirtualRegister (unsigned Reg, SmallVectorImpl< unsigned > *Ops=nullptr) const
 Return a pair of bools (reads, writes) indicating if this instruction reads or writes Reg. More...
 
bool killsRegister (unsigned Reg, const TargetRegisterInfo *TRI=nullptr) const
 Return true if the MachineInstr kills the specified register. More...
 
bool definesRegister (unsigned Reg, const TargetRegisterInfo *TRI=nullptr) const
 Return true if the MachineInstr fully defines the specified register. More...
 
bool modifiesRegister (unsigned Reg, const TargetRegisterInfo *TRI) const
 Return true if the MachineInstr modifies (fully define or partially define) the specified register. More...
 
bool registerDefIsDead (unsigned Reg, const TargetRegisterInfo *TRI=nullptr) const
 Returns true if the register is dead in this machine instruction. More...
 
bool hasRegisterImplicitUseOperand (unsigned Reg) const
 Returns true if the MachineInstr has an implicit-use operand of exactly the given register (not considering sub/super-registers). More...
 
int findRegisterUseOperandIdx (unsigned Reg, bool isKill=false, const TargetRegisterInfo *TRI=nullptr) const
 Returns the operand index that is a use of the specific register or -1 if it is not found. More...
 
MachineOperandfindRegisterUseOperand (unsigned Reg, bool isKill=false, const TargetRegisterInfo *TRI=nullptr)
 Wrapper for findRegisterUseOperandIdx, it returns a pointer to the MachineOperand rather than an index. More...
 
const MachineOperandfindRegisterUseOperand (unsigned Reg, bool isKill=false, const TargetRegisterInfo *TRI=nullptr) const
 
int findRegisterDefOperandIdx (unsigned Reg, bool isDead=false, bool Overlap=false, const TargetRegisterInfo *TRI=nullptr) const
 Returns the operand index that is a def of the specified register or -1 if it is not found. More...
 
MachineOperandfindRegisterDefOperand (unsigned Reg, bool isDead=false, const TargetRegisterInfo *TRI=nullptr)
 Wrapper for findRegisterDefOperandIdx, it returns a pointer to the MachineOperand rather than an index. More...
 
int findFirstPredOperandIdx () const
 Find the index of the first operand in the operand list that is used to represent the predicate. More...
 
int findInlineAsmFlagIdx (unsigned OpIdx, unsigned *GroupNo=nullptr) const
 Find the index of the flag word operand that corresponds to operand OpIdx on an inline asm instruction. More...
 
const TargetRegisterClassgetRegClassConstraint (unsigned OpIdx, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const
 Compute the static register class constraint for operand OpIdx. More...
 
const TargetRegisterClassgetRegClassConstraintEffectForVReg (unsigned Reg, const TargetRegisterClass *CurRC, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI, bool ExploreBundle=false) const
 Applies the constraints (def/use) implied by this MI on Reg to the given CurRC. More...
 
const TargetRegisterClassgetRegClassConstraintEffect (unsigned OpIdx, const TargetRegisterClass *CurRC, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const
 Applies the constraints (def/use) implied by the OpIdx operand to the given CurRC. More...
 
void tieOperands (unsigned DefIdx, unsigned UseIdx)
 Add a tie between the register operands at DefIdx and UseIdx. More...
 
unsigned findTiedOperandIdx (unsigned OpIdx) const
 Given the index of a tied register operand, find the operand it is tied to. More...
 
bool isRegTiedToUseOperand (unsigned DefOpIdx, unsigned *UseOpIdx=nullptr) const
 Given the index of a register def operand, check if the register def is tied to a source operand, due to either two-address elimination or inline assembly constraints. More...
 
bool isRegTiedToDefOperand (unsigned UseOpIdx, unsigned *DefOpIdx=nullptr) const
 Return true if the use operand of the specified index is tied to a def operand. More...
 
void clearKillInfo ()
 Clears kill flags on all operands. More...
 
void substituteRegister (unsigned FromReg, unsigned ToReg, unsigned SubIdx, const TargetRegisterInfo &RegInfo)
 Replace all occurrences of FromReg with ToReg:SubIdx, properly composing subreg indices where necessary. More...
 
bool addRegisterKilled (unsigned IncomingReg, const TargetRegisterInfo *RegInfo, bool AddIfNotFound=false)
 We have determined MI kills a register. More...
 
void clearRegisterKills (unsigned Reg, const TargetRegisterInfo *RegInfo)
 Clear all kill flags affecting Reg. More...
 
bool addRegisterDead (unsigned Reg, const TargetRegisterInfo *RegInfo, bool AddIfNotFound=false)
 We have determined MI defined a register without a use. More...
 
void clearRegisterDeads (unsigned Reg)
 Clear all dead flags on operands defining register Reg. More...
 
void setRegisterDefReadUndef (unsigned Reg, bool IsUndef=true)
 Mark all subregister defs of register Reg with the undef flag. More...
 
void addRegisterDefined (unsigned Reg, const TargetRegisterInfo *RegInfo=nullptr)
 We have determined MI defines a register. More...
 
void setPhysRegsDeadExcept (ArrayRef< unsigned > UsedRegs, const TargetRegisterInfo &TRI)
 Mark every physreg used by this instruction as dead except those in the UsedRegs list. More...
 
bool isSafeToMove (AliasAnalysis *AA, bool &SawStore) const
 Return true if it is safe to move this instruction. More...
 
bool mayAlias (AliasAnalysis *AA, MachineInstr &Other, bool UseTBAA)
 Returns true if this instruction's memory access aliases the memory access of Other. More...
 
bool hasOrderedMemoryRef () const
 Return true if this instruction may have an ordered or volatile memory reference, or if the information describing the memory reference is not available. More...
 
bool isDereferenceableInvariantLoad (AliasAnalysis *AA) const
 Return true if this load instruction never traps and points to a memory location whose value doesn't change during the execution of this function. More...
 
unsigned isConstantValuePHI () const
 If the specified instruction is a PHI that always merges together the same virtual register, return the register, otherwise return 0. More...
 
bool hasUnmodeledSideEffects () const
 Return true if this instruction has side effects that are not modeled by mayLoad / mayStore, etc. More...
 
bool isLoadFoldBarrier () const
 Returns true if it is illegal to fold a load across this instruction. More...
 
bool allDefsAreDead () const
 Return true if all the defs of this instruction are dead. More...
 
void copyImplicitOps (MachineFunction &MF, const MachineInstr &MI)
 Copy implicit register operands from specified instruction to this instruction. More...
 
void addOperand (MachineFunction &MF, const MachineOperand &Op)
 Add the specified operand to the instruction. More...
 
void addOperand (const MachineOperand &Op)
 Add an operand without providing an MF reference. More...
 
void setDesc (const MCInstrDesc &tid)
 Replace the instruction descriptor (thus opcode) of the current instruction with a new one. More...
 
void setDebugLoc (DebugLoc dl)
 Replace current source information with new such. More...
 
void RemoveOperand (unsigned i)
 Erase an operand from an instruction, leaving it with one fewer operand than it started with. More...
 
void addMemOperand (MachineFunction &MF, MachineMemOperand *MO)
 Add a MachineMemOperand to the machine instruction. More...
 
void setMemRefs (mmo_iterator NewMemRefs, mmo_iterator NewMemRefsEnd)
 Assign this MachineInstr's memory reference descriptor list. More...
 
void setMemRefs (std::pair< mmo_iterator, unsigned > NewMemRefs)
 Assign this MachineInstr's memory reference descriptor list. More...
 
std::pair< mmo_iterator, unsignedmergeMemRefsWith (const MachineInstr &Other)
 Return a set of memrefs (begin iterator, size) which conservatively describe the memory behavior of both MachineInstrs. More...
 
uint8_t mergeFlagsWith (const MachineInstr &Other) const
 Return the MIFlags which represent both MachineInstrs. More...
 
void dropMemRefs ()
 Clear this MachineInstr's memory reference descriptor list. More...
 
void untieRegOperand (unsigned OpIdx)
 Break any tie involving OpIdx. More...
 
void addImplicitDefUseOperands (MachineFunction &MF)
 Add all implicit def and use operands to this instruction. More...
 
LLT getTypeToPrint (unsigned OpIdx, SmallBitVector &PrintedTypes, const MachineRegisterInfo &MRI) const
 Debugging supportDetermine the generic type to be printed (if needed) on uses and defs. More...
 
bool hasComplexRegisterTies () const
 Return true when an instruction has tied register that can't be determined by the instruction's descriptor. More...
 
void print (raw_ostream &OS, bool IsStandalone=true, bool SkipOpers=false, bool SkipDebugLoc=false, bool AddNewLine=true, const TargetInstrInfo *TII=nullptr) const
 Print this MI to OS. More...
 
void print (raw_ostream &OS, ModuleSlotTracker &MST, bool IsStandalone=true, bool SkipOpers=false, bool SkipDebugLoc=false, bool AddNewLine=true, const TargetInstrInfo *TII=nullptr) const
 
void dump () const
 
- Public Member Functions inherited from llvm::ilist_node_with_parent< MachineInstr, MachineBasicBlock, ilist_sentinel_tracking< true > >
MachineInstrgetPrevNode ()
 
const MachineInstrgetPrevNode () const
 Get the previous node, or nullptr for the list head. More...
 
MachineInstrgetNextNode ()
 Get the next node, or nullptr for the list tail. More...
 
const MachineInstrgetNextNode () const
 Get the next node, or nullptr for the list tail. More...
 
- Public Member Functions inherited from llvm::ilist_node_impl< ilist_detail::compute_node_options< MachineInstr, Options... >::type >
self_iterator getIterator ()
 
const_self_iterator getIterator () const
 
reverse_self_iterator getReverseIterator ()
 
const_reverse_self_iterator getReverseIterator () const
 
bool isSentinel () const
 Check whether this is the sentinel node. More...
 

Friends

struct ilist_traits< MachineInstr >
 
struct ilist_callback_traits< MachineBasicBlock >
 
class MachineFunction
 

Additional Inherited Members

- Protected Types inherited from llvm::ilist_node_impl< ilist_detail::compute_node_options< MachineInstr, Options... >::type >
using self_iterator = ilist_iterator< ilist_detail::compute_node_options< MachineInstr, Options... >::type, false, false >
 
using const_self_iterator = ilist_iterator< ilist_detail::compute_node_options< MachineInstr, Options... >::type, false, true >
 
using reverse_self_iterator = ilist_iterator< ilist_detail::compute_node_options< MachineInstr, Options... >::type, true, false >
 
using const_reverse_self_iterator = ilist_iterator< ilist_detail::compute_node_options< MachineInstr, Options... >::type, true, true >
 
- Protected Member Functions inherited from llvm::ilist_node_with_parent< MachineInstr, MachineBasicBlock, ilist_sentinel_tracking< true > >
 ilist_node_with_parent ()=default
 
- Protected Member Functions inherited from llvm::ilist_node_impl< ilist_detail::compute_node_options< MachineInstr, Options... >::type >
 ilist_node_impl ()=default
 

Detailed Description

Representation of each machine instruction.

This class isn't a POD type, but it must have a trivial destructor. When a MachineFunction is deleted, all the contained MachineInstrs are deallocated without having their destructor called.

Definition at line 60 of file MachineInstr.h.

Member Typedef Documentation

◆ const_mop_iterator

Definition at line 327 of file MachineInstr.h.

◆ mmo_iterator

Definition at line 64 of file MachineInstr.h.

◆ mop_iterator

iterator/begin/end - Iterate over all operands of a machine instruction.

Definition at line 326 of file MachineInstr.h.

Member Enumeration Documentation

◆ CommentFlag

Flags to specify different kinds of comments to output in assembly code.

These flags carry semantic information not otherwise easily derivable from the IR text.

Enumerator
ReloadReuse 
NoSchedComment 
TAsmComments 

Definition at line 70 of file MachineInstr.h.

◆ MICheckType

Enumerator
CheckDefs 
CheckKillDead 
IgnoreDefs 
IgnoreVRegDefs 

Definition at line 753 of file MachineInstr.h.

◆ MIFlag

Enumerator
NoFlags 
FrameSetup 
FrameDestroy 
BundledPred 
BundledSucc 

Definition at line 76 of file MachineInstr.h.

◆ QueryType

API for querying MachineInstr properties.

They are the same as MCInstrDesc queries but they are bundle aware.

Enumerator
IgnoreBundle 
AnyInBundle 
AllInBundle 

Definition at line 417 of file MachineInstr.h.

Constructor & Destructor Documentation

◆ MachineInstr()

llvm::MachineInstr::MachineInstr ( const MachineInstr )
delete

◆ ~MachineInstr()

llvm::MachineInstr::~MachineInstr ( )
delete

Member Function Documentation

◆ addImplicitDefUseOperands()

void MachineInstr::addImplicitDefUseOperands ( MachineFunction MF)

◆ addMemOperand()

void MachineInstr::addMemOperand ( MachineFunction MF,
MachineMemOperand MO 
)

Add a MachineMemOperand to the machine instruction.

addMemOperand - Add a MachineMemOperand to the machine instruction.

This function should be used only occasionally. The setMemRefs function is the primary method for setting up a MachineInstr's MemRefs list.

Definition at line 320 of file MachineInstr.cpp.

References llvm::MachineFunction::allocateMemRefsArray(), llvm::copy(), and setMemRefs().

Referenced by llvm::MachineInstrBuilder::addMemOperand(), computeBytesPoppedByCalleeForSRet(), llvm::TargetLoweringBase::emitPatchPoint(), llvm::TargetInstrInfo::foldMemoryOperand(), getStoreTarget(), getX86SSEConditionCode(), profitImm(), and setDebugLoc().

◆ addOperand() [1/2]

void MachineInstr::addOperand ( MachineFunction MF,
const MachineOperand Op 
)

Add the specified operand to the instruction.

addOperand - Add the specified operand to the instruction.

If it is an implicit operand, it is added to the end of the operand list. If it is an explicit operand it is added at the end of the explicit operand list (before the first implicit operand).

MF must be the machine function that was used to allocate this instruction.

MachineInstrBuilder provides a more convenient interface for creating instructions and adding operands.

If it is an implicit operand, it is added to the end of the operand list. If it is an explicit operand it is added at the end of the explicit operand list (before the first implicit operand).

Definition at line 198 of file MachineInstr.cpp.

References llvm::MachineRegisterInfo::addRegOperandToUseList(), llvm::MachineFunction::allocateOperandArray(), assert(), llvm::MachineFunction::deallocateOperandArray(), llvm::MCOI::EARLY_CLOBBER, llvm::MCInstrDesc::getNumOperands(), getNumOperands(), llvm::MCInstrDesc::getOperandConstraint(), llvm::MachineOperand::getType(), llvm::MachineOperand::isImplicit(), isInlineAsm(), isReg(), llvm::MachineOperand::isReg(), llvm::MachineOperand::isRegMask(), llvm::MachineOperand::isUse(), llvm::MCInstrDesc::isVariadic(), llvm::MachineOperand::MO_Metadata, moveOperands(), llvm::MachineOperand::Reg, llvm::MachineOperand::setIsEarlyClobber(), llvm::MCOI::TIED_TO, and tieOperands().

Referenced by llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addBlockAddress(), llvm::MachineInstrBuilder::addCFIIndex(), llvm::MachineInstrBuilder::addCImm(), llvm::MachineInstrBuilder::addConstantPoolIndex(), llvm::MachineInstrBuilder::addExternalSymbol(), llvm::MachineInstrBuilder::addFPImm(), llvm::MachineInstrBuilder::addFrameIndex(), llvm::MachineInstrBuilder::addGlobalAddress(), llvm::MachineInstrBuilder::addImm(), addImplicitDefUseOperands(), llvm::MachineInstrBuilder::addIntrinsicID(), llvm::MachineInstrBuilder::addJumpTableIndex(), llvm::MachineInstrBuilder::addMBB(), llvm::MachineInstrBuilder::addMetadata(), addOperand(), llvm::MachineInstrBuilder::addPredicate(), llvm::MachineInstrBuilder::addReg(), addRegisterDead(), addRegisterDefined(), addRegisterKilled(), llvm::MachineInstrBuilder::addRegMask(), llvm::MachineInstrBuilder::addSym(), llvm::MachineInstrBuilder::addTargetIndex(), llvm::ARMTargetLowering::AdjustInstrPostInstrSelection(), llvm::SIInstrInfo::buildExtractSubRegOrImm(), changeFCMPPredToAArch64CC(), ConvertImplicitDefToConstZero(), copyExtraImplicitOps(), copyImplicitOps(), llvm::createSIFixWWMLivenessPass(), llvm::XCoreFrameLowering::emitEpilogue(), llvm::PPCTargetLowering::EmitInstrWithCustomInserter(), llvm::HexagonFrameLowering::emitPrologue(), forceReg(), llvm::HexagonFrameLowering::getAlignaInstr(), getLeaOP(), llvm::LiveVariables::HandleVirtRegDef(), ImposeStackOrdering(), INITIALIZE_PASS(), isCopy(), isImmValidForOpcode(), isRegTiedToDefOperand(), isSimpleIf(), llvm::SIInstrInfo::moveToVALU(), llvm::PPCInstrInfo::optimizeCompareInstr(), llvm::HexagonInstrInfo::PredicateInstruction(), profitImm(), readsVCCZ(), llvm::rewriteT2FrameIndex(), swapMIOperands(), and toString().

◆ addOperand() [2/2]

void MachineInstr::addOperand ( const MachineOperand Op)

Add an operand without providing an MF reference.

This only works for instructions that are inserted in a basic block.

MachineInstrBuilder and the two-argument addOperand(MF, MO) should be preferred.

Definition at line 175 of file MachineInstr.cpp.

References addOperand(), assert(), getParent(), and llvm::MachineBasicBlock::getParent().

◆ addRegisterDead()

bool MachineInstr::addRegisterDead ( unsigned  Reg,
const TargetRegisterInfo RegInfo,
bool  AddIfNotFound = false 
)

◆ addRegisterDefined()

void MachineInstr::addRegisterDefined ( unsigned  Reg,
const TargetRegisterInfo RegInfo = nullptr 
)

◆ addRegisterKilled()

bool MachineInstr::addRegisterKilled ( unsigned  IncomingReg,
const TargetRegisterInfo RegInfo,
bool  AddIfNotFound = false 
)

We have determined MI kills a register.

Look for the operand that uses it and mark it as IsKill. If AddIfNotFound is true, add a implicit operand if it's not found. Returns true if the operand exists / is added.

Definition at line 1494 of file MachineInstr.cpp.

References addOperand(), llvm::SmallVectorTemplateCommon< T, typename >::back(), llvm::MachineOperand::CreateReg(), llvm::SmallVectorBase::empty(), getNumOperands(), getOperand(), llvm::MachineOperand::getReg(), llvm::MachineOperand::isDebug(), llvm::MachineOperand::isKill(), llvm::TargetRegisterInfo::isPhysicalRegister(), llvm::MachineOperand::isReg(), isRegTiedToDefOperand(), llvm::MCRegisterInfo::isSubRegister(), llvm::MCRegisterInfo::isSuperRegister(), llvm::MachineOperand::isUndef(), llvm::MachineOperand::isUse(), llvm::MCRegAliasIterator::isValid(), llvm::SmallVectorTemplateBase< T, isPodLike >::pop_back(), llvm::SmallVectorTemplateBase< T, isPodLike >::push_back(), RemoveOperand(), and llvm::MachineOperand::setIsKill().

Referenced by addExclusiveRegPair(), llvm::LiveIntervals::addKillFlags(), llvm::LiveVariables::addVirtualRegisterKilled(), llvm::ARMBaseInstrInfo::breakPartialRegDependency(), llvm::X86InstrInfo::breakPartialRegDependency(), llvm::SparcInstrInfo::copyPhysReg(), llvm::ARMBaseInstrInfo::copyPhysReg(), emitAlignedDPRCS2Restores(), emitAlignedDPRCS2Spills(), llvm::XCoreFrameLowering::emitPrologue(), llvm::ARMBaseInstrInfo::expandPostRAPseudo(), llvm::LiveVariables::HandleVirtRegDef(), INITIALIZE_PASS(), isRegTiedToDefOperand(), ReplaceDominatedUses(), and UseReg().

◆ allDefsAreDead()

bool MachineInstr::allDefsAreDead ( ) const

Return true if all the defs of this instruction are dead.

allDefsAreDead - Return true if all the defs of this instruction are dead.

Definition at line 1173 of file MachineInstr.cpp.

References operands().

Referenced by llvm::LiveRangeEdit::eraseVirtReg(), INITIALIZE_PASS(), isFullCopyOf(), isRegTiedToDefOperand(), removeDeadSegment(), and llvm::LiveIntervals::shrinkToUses().

◆ bundleWithPred()

void MachineInstr::bundleWithPred ( )

◆ bundleWithSucc()

void MachineInstr::bundleWithSucc ( )

Bundle this instruction with its successor.

This can be an unbundled instruction, or it can be the last instruction in a bundle.

Definition at line 545 of file MachineInstr.cpp.

References assert(), BundledPred, BundledSucc, llvm::ilist_node_impl< ilist_detail::compute_node_options< MachineInstr, Options... >::type >::getIterator(), isBundledWithSucc(), and setFlag().

Referenced by llvm::MIBundleBuilder::insert(), and isBundledWithSucc().

◆ canFoldAsLoad()

bool llvm::MachineInstr::canFoldAsLoad ( QueryType  Type = IgnoreBundle) const
inline

Return true for instructions that can be folded as memory operands in other instructions.

The most common use for this is instructions that are simple loads from memory that don't modify the loaded value in any way, but it can also be used for instructions that can be expressed as constant-pool loads, such as V_SETALLONES on x86, to allow them to be folded when it is beneficial. This should only be set on instructions that return a value in their only virtual register definition.

Definition at line 575 of file MachineInstr.h.

References llvm::MCID::FoldableAsLoad, and hasProperty().

Referenced by llvm::LiveRangeEdit::eraseVirtReg(), llvm::TargetInstrInfo::foldMemoryOperand(), getNewSource(), isCopyFeedingInvariantStore(), and isFullCopyOf().

◆ clearAsmPrinterFlag()

void llvm::MachineInstr::clearAsmPrinterFlag ( CommentFlag  Flag)
inline

Clear specific AsmPrinter flags.

Definition at line 173 of file MachineInstr.h.

◆ clearAsmPrinterFlags()

void llvm::MachineInstr::clearAsmPrinterFlags ( )
inline

Clear the AsmPrinter bitvector.

Definition at line 160 of file MachineInstr.h.

◆ clearFlag()

void llvm::MachineInstr::clearFlag ( MIFlag  Flag)
inline

clearFlag - Clear a MI flag.

Definition at line 199 of file MachineInstr.h.

Referenced by moveInstrOut(), llvm::MachineBasicBlock::remove_instr(), unbundleFromPred(), and unbundleFromSucc().

◆ clearKillInfo()

void MachineInstr::clearKillInfo ( )

Clears kill flags on all operands.

clearKillInfo - Clears kill flags on all operands.

Definition at line 930 of file MachineInstr.cpp.

References operands().

Referenced by INITIALIZE_PASS(), isRegTiedToDefOperand(), llvm::LanaiInstrInfo::optimizeSelect(), llvm::ARMBaseInstrInfo::optimizeSelect(), and llvm::rdf::Liveness::resetKills().

◆ clearRegisterDeads()

void MachineInstr::clearRegisterDeads ( unsigned  Reg)

Clear all dead flags on operands defining register Reg.

Definition at line 1625 of file MachineInstr.cpp.

References operands().

Referenced by isRegTiedToDefOperand(), and llvm::PPCInstrInfo::optimizeCompareInstr().

◆ clearRegisterKills()

void MachineInstr::clearRegisterKills ( unsigned  Reg,
const TargetRegisterInfo RegInfo 
)

Clear all kill flags affecting Reg.

If RegInfo is provided, this includes all aliasing registers.

Definition at line 1560 of file MachineInstr.cpp.

References llvm::TargetRegisterInfo::isPhysicalRegister(), operands(), and llvm::TargetRegisterInfo::regsOverlap().

Referenced by llvm::LiveIntervals::addKillFlags(), and isRegTiedToDefOperand().

◆ copyImplicitOps()

void MachineInstr::copyImplicitOps ( MachineFunction MF,
const MachineInstr MI 
)

Copy implicit register operands from specified instruction to this instruction.

copyImplicitOps - Copy implicit register operands from specified instruction to this instruction.

Definition at line 1185 of file MachineInstr.cpp.

References addOperand(), getDesc(), llvm::MCInstrDesc::getNumOperands(), getNumOperands(), getOperand(), llvm::MachineOperand::isImplicit(), llvm::MachineOperand::isReg(), and llvm::MachineOperand::isRegMask().

Referenced by llvm::MachineInstrBuilder::copyImplicitOps(), llvm::HexagonFrameLowering::emitPrologue(), llvm::HexagonFrameLowering::getFrameIndexReference(), InsertLDR_STR(), and isRegTiedToDefOperand().

◆ definesRegister()

bool llvm::MachineInstr::definesRegister ( unsigned  Reg,
const TargetRegisterInfo TRI = nullptr 
) const
inline

◆ defs() [1/2]

iterator_range<mop_iterator> llvm::MachineInstr::defs ( )
inline

Returns a range over all explicit operands that are register definitions.

Implicit definition are not included!

Definition at line 357 of file MachineInstr.h.

References getDesc(), llvm::make_range(), and operands_begin().

Referenced by addRegsToSet(), AnyAliasLiveIn(), llvm::createSIFixWWMLivenessPass(), llvm::createSIWholeQuadModePass(), llvm::SplitEditor::dump(), findSingleRegDef(), isCrossCopy(), llvm::WebAssemblyMCInstLower::Lower(), llvm::GCNUpwardRPTracker::recede(), and false::Chain::str().

◆ defs() [2/2]

iterator_range<const_mop_iterator> llvm::MachineInstr::defs ( ) const
inline

Returns a range over all explicit operands that are register definitions.

Implicit definition are not included!

Definition at line 362 of file MachineInstr.h.

References getDesc(), llvm::make_range(), and operands_begin().

◆ dropMemRefs()

void llvm::MachineInstr::dropMemRefs ( )
inline

Clear this MachineInstr's memory reference descriptor list.

This resets the memrefs to their most conservative state. This should be used only as a last resort since it greatly pessimizes our knowledge of the memory access performed by the instruction.

Definition at line 1330 of file MachineInstr.h.

Referenced by INITIALIZE_PASS(), and removePhis().

◆ dump()

LLVM_DUMP_METHOD void MachineInstr::dump ( ) const

◆ emitError()

void MachineInstr::emitError ( StringRef  Msg) const

Emit an error referring to the source location of this instruction.

This should only be used for inline assembly that is somehow impossible to compile. Other errors should have been handled much earlier.

If this method returns, the caller should try to recover from the error.

Definition at line 1700 of file MachineInstr.cpp.

References llvm::LLVMContext::emitError(), llvm::Module::getContext(), llvm::MachineFunction::getMMI(), llvm::MachineModuleInfo::getModule(), getNumOperands(), llvm::MDNode::getNumOperands(), getOperand(), llvm::MDNode::getOperand(), getParent(), and llvm::report_fatal_error().

Referenced by llvm::RegAllocBase::allocatePhysRegs(), getDebugLoc(), INITIALIZE_PASS(), and llvm::LowerARMMachineInstrToMCInst().

◆ eraseFromBundle()

void MachineInstr::eraseFromBundle ( )

Unlink 'this' form its basic block and delete it.

If the instruction is part of a bundle, the other instructions in the bundle remain bundled.

Definition at line 516 of file MachineInstr.cpp.

References assert(), llvm::MachineBasicBlock::erase_instr(), and getParent().

Referenced by VerifyLowRegs().

◆ eraseFromParent()

void MachineInstr::eraseFromParent ( )

Unlink 'this' from the containing basic block and delete it.

If this instruction is the header of a bundle, the whole bundle is erased. This function can not be used for instructions inside a bundle, use eraseFromBundle() to erase individual bundled instructions.

Definition at line 491 of file MachineInstr.cpp.

References assert(), llvm::MachineBasicBlock::erase(), and getParent().

Referenced by addExclusiveRegPair(), llvm::AMDGPUInstructionSelector::AMDGPUInstructionSelector(), llvm::analyzeArguments(), llvm::ARCInstrInfo::analyzeBranch(), llvm::SparcInstrInfo::analyzeBranch(), llvm::MipsInstrInfo::analyzeBranch(), llvm::ARMBaseInstrInfo::analyzeBranch(), llvm::AArch64InstrInfo::analyzeBranch(), canInstrSubstituteCmpInstr(), llvm::TailDuplicator::canTailDuplicate(), canTurnIntoCOPY(), changeFCMPPredToAArch64CC(), computeBytesPoppedByCalleeForSRet(), llvm::createHexagonHardwareLoops(), createPHIsForCMOVsInSinkBB(), llvm::createR600ExpandSpecialInstrsPass(), llvm::createSILowerI1CopiesPass(), llvm::createSIWholeQuadModePass(), llvm::createSystemZLDCleanupPass(), llvm::createX86GlobalBaseRegPass(), llvm::createX86OptimizeLEAs(), llvm::createXCoreFrameToArgsOffsetEliminationPass(), definesFullReg(), dumpMachineInstrRangeWithSlotIndex(), llvm::BPFRegisterInfo::eliminateFrameIndex(), llvm::LanaiRegisterInfo::eliminateFrameIndex(), emitBuildPairF64Pseudo(), emitClzero(), llvm::SparcTargetLowering::emitEHSjLjLongJmp(), llvm::PPCTargetLowering::emitEHSjLjLongJmp(), llvm::SparcTargetLowering::emitEHSjLjSetJmp(), llvm::PPCTargetLowering::emitEHSjLjSetJmp(), llvm::AArch64TargetLowering::EmitF128CSEL(), emitIndirectDst(), emitIndirectSrc(), llvm::R600TargetLowering::EmitInstrWithCustomInserter(), llvm::RISCVTargetLowering::EmitInstrWithCustomInserter(), llvm::BPFTargetLowering::EmitInstrWithCustomInserter(), llvm::AVRTargetLowering::EmitInstrWithCustomInserter(), llvm::XCoreTargetLowering::EmitInstrWithCustomInserter(), llvm::MSP430TargetLowering::EmitInstrWithCustomInserter(), llvm::SITargetLowering::EmitInstrWithCustomInserter(), llvm::ARMTargetLowering::EmitInstrWithCustomInserter(), llvm::MipsTargetLowering::EmitInstrWithCustomInserter(), llvm::PPCTargetLowering::EmitInstrWithCustomInserter(), llvm::X86TargetLowering::EmitInstrWithCustomInserter(), emitMonitor(), llvm::TargetLoweringBase::emitPatchPoint(), emitPCMPSTRI(), emitPCMPSTRM(), emitPostSt(), emitRDPKRU(), llvm::MSP430TargetLowering::EmitShiftInstr(), emitSplitF64Pseudo(), emitWRPKRU(), emitXBegin(), llvm::TargetLoweringBase::emitXRayCustomEvent(), llvm::TargetLoweringBase::emitXRayTypedEvent(), llvm::rdf::DeadCodeElimination::erase(), eraseFromParentAndMarkDBGValuesForRemoval(), eraseIfDead(), llvm::LiveRangeEdit::eraseVirtReg(), llvm::SIInstrInfo::expandPostRAPseudo(), llvm::R600InstrInfo::expandPostRAPseudo(), llvm::SparcTargetLowering::expandSelectCC(), llvm::LegalizerHelper::fewerElementsVector(), findSingleRegDef(), FindStartOfTree(), llvm::fixStackStores(), llvm::foldFrameOffset(), llvm::SystemZInstrInfo::FoldImmediate(), llvm::PPCInstrInfo::FoldImmediate(), llvm::SIInstrInfo::FoldImmediate(), llvm::ARMBaseInstrInfo::FoldImmediate(), foldImmediates(), llvm::X86InstrInfo::foldMemoryOperandImpl(), foldVGPRCopyIntoRegSequence(), forceReg(), llvm::HexagonInstrInfo::genAllInsnTimingClasses(), getAdjustedCmp(), getBranchDebugLoc(), getCmpForPseudo(), getComparePred(), getCompareSourceReg(), GetDSubRegs(), getMappedOp(), getNewSource(), getNewValueJumpOpcode(), getOModValue(), getRegsUsedByPHIs(), getRetpolineSymbol(), getSmrdOpcode(), getStartOrEndSlot(), getSubOpcode(), getUnconditionalBrDisp(), llvm::MachineSSAUpdater::GetValueInMiddleOfBlock(), llvm::MipsTargetLowering::HandleByVal(), HandleVRSaveUpdate(), hasOneNonDBGUseInst(), hasUseAfterLoop(), hoistAndMergeSGPRInits(), INITIALIZE_PASS(), llvm::X86FrameLowering::inlineStackProbe(), insertCopy(), isCompareZero(), isCopyFeedingInvariantStore(), isDebug(), isDefInSubRange(), isFpMulInstruction(), isFullCopyOf(), isFullUndefDef(), isInRage(), isLiveOut(), isPHIRegionIndex(), isRegUsedByPhiNodes(), isSExtLoad(), isSimpleIf(), isSimpleIndexCalc(), isVirtualRegisterOperand(), llvm::AArch64LegalizerInfo::legalizeCustom(), llvm::ARMLegalizerInfo::legalizeCustom(), llvm::LegalizerHelper::libcall(), llvm::LegalizerHelper::lower(), LowerFPToInt(), lowerVECTOR_SHUFFLE_VSHF(), makeImplicit(), Mips16WhichOp8uOr16simm(), llvm::SIInstrInfo::moveToVALU(), llvm::LegalizerHelper::narrowScalar(), opcodeEmitsNoInsts(), llvm::LanaiInstrInfo::optimizeCompareInstr(), llvm::AArch64InstrInfo::optimizeCompareInstr(), llvm::ARMBaseInstrInfo::optimizeCompareInstr(), llvm::PPCInstrInfo::optimizeCompareInstr(), llvm::X86InstrInfo::optimizeCompareInstr(), llvm::AArch64InstrInfo::optimizeCondBranch(), llvm::LanaiInstrInfo::optimizeSelect(), llvm::ARMBaseInstrInfo::optimizeSelect(), llvm::SplitEditor::overlapIntv(), parseCond(), llvm::HexagonInstrInfo::reduceLoopCount(), registerDefinedBetween(), regOverlapsSet(), RematerializeCheapDef(), RemoveDeadAddBetweenLEAAndJT(), llvm::FastISel::removeDeadCode(), removeExternalCFGEdges(), removeIPMBasedCompare(), RemoveVRSaveCode(), llvm::ARMTargetLowering::ReplaceNodeResults(), llvm::rewriteAArch64FrameIndex(), llvm::FastISel::selectPatchpoint(), shrinkScalarCompare(), splitBlock(), splitMBB(), llvm::SystemZInstrInfo::SystemZInstrInfo(), llvm::TailDuplicator::tailDuplicateAndUpdate(), llvm::CombinerHelper::tryCombineCopy(), tryOptimizeLEAtoMOV(), tryOrrMovk(), trySequenceOfOnes(), tryToreplicateChunks(), UseReg(), and llvm::LegalizerHelper::widenScalar().

◆ eraseFromParentAndMarkDBGValuesForRemoval()

void MachineInstr::eraseFromParentAndMarkDBGValuesForRemoval ( )

◆ explicit_operands() [1/2]

iterator_range<mop_iterator> llvm::MachineInstr::explicit_operands ( )
inline

◆ explicit_operands() [2/2]

iterator_range<const_mop_iterator> llvm::MachineInstr::explicit_operands ( ) const
inline

Definition at line 345 of file MachineInstr.h.

References getNumExplicitOperands(), llvm::make_range(), and operands_begin().

◆ explicit_uses() [1/2]

iterator_range<mop_iterator> llvm::MachineInstr::explicit_uses ( )
inline

◆ explicit_uses() [2/2]

iterator_range<const_mop_iterator> llvm::MachineInstr::explicit_uses ( ) const
inline

◆ findFirstPredOperandIdx()

int MachineInstr::findFirstPredOperandIdx ( ) const

◆ findInlineAsmFlagIdx()

int MachineInstr::findInlineAsmFlagIdx ( unsigned  OpIdx,
unsigned GroupNo = nullptr 
) const

Find the index of the flag word operand that corresponds to operand OpIdx on an inline asm instruction.

Returns -1 if getOperand(OpIdx) does not belong to an inline asm operand group.

If GroupNo is not NULL, it will receive the number of the operand group containing OpIdx.

The flag operand is an immediate that can be decoded with methods like InlineAsm::hasRegClassConstraint().

Definition at line 587 of file MachineInstr.cpp.

References assert(), llvm::MachineOperand::getImm(), llvm::InlineAsm::getNumOperandRegisters(), getNumOperands(), getOperand(), llvm::MachineOperand::isImm(), isInlineAsm(), and llvm::InlineAsm::MIOp_FirstOperand.

Referenced by findRegisterDefOperand(), and getRegClassConstraint().

◆ findRegisterDefOperand()

MachineOperand* llvm::MachineInstr::findRegisterDefOperand ( unsigned  Reg,
bool  isDead = false,
const TargetRegisterInfo TRI = nullptr 
)
inline

◆ findRegisterDefOperandIdx()

int MachineInstr::findRegisterDefOperandIdx ( unsigned  Reg,
bool  isDead = false,
bool  Overlap = false,
const TargetRegisterInfo TRI = nullptr 
) const

Returns the operand index that is a def of the specified register or -1 if it is not found.

findRegisterDefOperandIdx() - Returns the operand index that is a def of the specified register or -1 if it is not found.

If isDead is true, defs that are not dead are skipped. If Overlap is true, then it also looks for defs that merely overlap the specified register. If TargetRegisterInfo is non-null, then it also checks if there is a def of a super-register. This may also return a register mask operand when Overlap is true.

If isDead is true, defs that are not dead are skipped. If TargetRegisterInfo is non-null, then it also checks if there is a def of a super-register.

Definition at line 789 of file MachineInstr.cpp.

References llvm::MachineOperand::clobbersPhysReg(), getNumOperands(), getOperand(), llvm::MachineOperand::getReg(), llvm::MachineOperand::isDead(), llvm::MachineOperand::isDef(), llvm::TargetRegisterInfo::isPhysicalRegister(), llvm::MachineOperand::isReg(), llvm::MachineOperand::isRegMask(), llvm::MCRegisterInfo::isSubRegister(), and llvm::TargetRegisterInfo::regsOverlap().

Referenced by addSegmentsWithValNo(), canFoldIntoCSel(), CriticalPathStep(), llvm::R600InstrInfo::definesAddressRegister(), definesRegister(), llvm::ARMBaseInstrInfo::expandPostRAPseudo(), findRegisterDefOperand(), findRegisterUseOperand(), getCompareSourceReg(), getMaddPatterns(), llvm::HexagonInstrInfo::getOperandLatency(), modifiesRegister(), llvm::AArch64InstrInfo::optimizeCompareInstr(), llvm::AArch64InstrInfo::optimizeCondBranch(), and registerDefIsDead().

◆ findRegisterUseOperand() [1/2]

MachineOperand* llvm::MachineInstr::findRegisterUseOperand ( unsigned  Reg,
bool  isKill = false,
const TargetRegisterInfo TRI = nullptr 
)
inline

Wrapper for findRegisterUseOperandIdx, it returns a pointer to the MachineOperand rather than an index.

Definition at line 994 of file MachineInstr.h.

References findRegisterUseOperandIdx(), getOperand(), and isKill().

Referenced by addEpilogOnlyR10(), findRegisterUseOperand(), isCopy(), llvm::AggressiveAntiDepBreaker::Observe(), regOverlapsSet(), splitBlock(), and UpdateCPSRUse().

◆ findRegisterUseOperand() [2/2]

const MachineOperand* llvm::MachineInstr::findRegisterUseOperand ( unsigned  Reg,
bool  isKill = false,
const TargetRegisterInfo TRI = nullptr 
) const
inline

Definition at line 1000 of file MachineInstr.h.

References findRegisterDefOperandIdx(), findRegisterUseOperand(), and isKill().

◆ findRegisterUseOperandIdx()

int MachineInstr::findRegisterUseOperandIdx ( unsigned  Reg,
bool  isKill = false,
const TargetRegisterInfo TRI = nullptr 
) const

◆ findTiedOperandIdx()

unsigned MachineInstr::findTiedOperandIdx ( unsigned  OpIdx) const

◆ getAsmPrinterFlag()

bool llvm::MachineInstr::getAsmPrinterFlag ( CommentFlag  Flag) const
inline

Return whether an AsmPrinter flag is set.

Definition at line 163 of file MachineInstr.h.

Referenced by emitComments(), and llvm::X86AsmPrinter::EmitInstruction().

◆ getAsmPrinterFlags()

uint8_t llvm::MachineInstr::getAsmPrinterFlags ( ) const
inline

Return the asm printer flags bitvector.

Definition at line 157 of file MachineInstr.h.

Referenced by llvm::X86AsmPrinter::EmitInstruction().

◆ getBundleSize()

unsigned MachineInstr::getBundleSize ( ) const

Return the number of instructions inside the MI bundle, excluding the bundle header.

Return the number of instructions inside the MI bundle, not counting the header instruction.

This is the number of instructions that MachineBasicBlock::iterator skips, 0 for unbundled instructions.

Definition at line 714 of file MachineInstr.cpp.

References llvm::ilist_node_impl< ilist_detail::compute_node_options< MachineInstr, Options... >::type >::getIterator(), I, and llvm::AMDGPU::HSAMD::Kernel::Arg::Key::Size.

Referenced by INITIALIZE_PASS(), and isTransient().

◆ getDebugExpression()

const DIExpression * MachineInstr::getDebugExpression ( ) const

◆ getDebugLoc()

const DebugLoc& llvm::MachineInstr::getDebugLoc ( ) const
inline

Returns the debug location id of this MachineInstr.

Definition at line 271 of file MachineInstr.h.

References emitError(), getDebugExpression(), and getDebugVariable().

Referenced by addEpilog(), addEpilogLeaf(), addEpilogOnlyR10(), addExclusiveRegPair(), addImplicitDefUseOperands(), addSegmentsWithValNo(), llvm::SITargetLowering::AdjustInstrPostInstrSelection(), llvm::AMDGPUInstructionSelector::AMDGPUInstructionSelector(), llvm::analyzeArguments(), llvm::HexagonFrameLowering::assignCalleeSavedSpillSlots(), attachMEMCPYScratchRegs(), llvm::CodeViewDebug::beginInstruction(), llvm::DwarfDebug::beginInstruction(), llvm::ARMBaseInstrInfo::breakPartialRegDependency(), llvm::X86InstrInfo::breakPartialRegDependency(), llvm::buildDbgValueForSpill(), canTurnIntoCOPY(), changeFCMPPredToAArch64CC(), llvm::X86InstrInfo::classifyLEAReg(), CombineCVTAToLocal(), llvm::PPCInstrInfo::commuteInstructionImpl(), computeExprForSpill(), llvm::constrainRegToClass(), ContainsReg(), llvm::ARMBaseInstrInfo::convertToThreeAddress(), llvm::SystemZInstrInfo::convertToThreeAddress(), llvm::X86InstrInfo::convertToThreeAddress(), llvm::SIInstrInfo::convertToThreeAddress(), llvm::createHexagonHardwareLoops(), createPHIsForCMOVsInSinkBB(), llvm::createSILowerI1CopiesPass(), llvm::createSIWholeQuadModePass(), llvm::createSystemZLDCleanupPass(), llvm::createX86FixupBWInsts(), llvm::createX86FixupSetCC(), llvm::createX86GlobalBaseRegPass(), llvm::createX86OptimizeLEAs(), definesFullReg(), llvm::ARMFrameLowering::determineCalleeSaves(), llvm::HexagonFrameLowering::determineCalleeSaves(), llvm::MSP430FrameLowering::eliminateCallFramePseudoInstr(), llvm::Thumb1FrameLowering::eliminateCallFramePseudoInstr(), llvm::XCoreFrameLowering::eliminateCallFramePseudoInstr(), llvm::ARCFrameLowering::eliminateCallFramePseudoInstr(), llvm::BPFRegisterInfo::eliminateFrameIndex(), llvm::MSP430RegisterInfo::eliminateFrameIndex(), llvm::RISCVRegisterInfo::eliminateFrameIndex(), llvm::LanaiRegisterInfo::eliminateFrameIndex(), llvm::SparcRegisterInfo::eliminateFrameIndex(), llvm::AVRRegisterInfo::eliminateFrameIndex(), llvm::HexagonRegisterInfo::eliminateFrameIndex(), llvm::ThumbRegisterInfo::eliminateFrameIndex(), llvm::AArch64RegisterInfo::eliminateFrameIndex(), llvm::PPCRegisterInfo::eliminateFrameIndex(), llvm::ARMBaseRegisterInfo::eliminateFrameIndex(), llvm::PPCTargetLowering::EmitAtomicBinary(), emitBuildPairF64Pseudo(), emitClzero(), llvm::SparcTargetLowering::emitEHSjLjLongJmp(), llvm::PPCTargetLowering::emitEHSjLjLongJmp(), llvm::SparcTargetLowering::emitEHSjLjSetJmp(), llvm::PPCTargetLowering::emitEHSjLjSetJmp(), llvm::AArch64TargetLowering::EmitF128CSEL(), emitIndirectDst(), emitIndirectSrc(), llvm::HexagonHazardRecognizer::EmitInstruction(), llvm::RISCVTargetLowering::EmitInstrWithCustomInserter(), llvm::BPFTargetLowering::EmitInstrWithCustomInserter(), llvm::AVRTargetLowering::EmitInstrWithCustomInserter(), llvm::XCoreTargetLowering::EmitInstrWithCustomInserter(), llvm::MSP430TargetLowering::EmitInstrWithCustomInserter(), llvm::SITargetLowering::EmitInstrWithCustomInserter(), llvm::ARMTargetLowering::EmitInstrWithCustomInserter(), llvm::MipsTargetLowering::EmitInstrWithCustomInserter(), llvm::PPCTargetLowering::EmitInstrWithCustomInserter(), llvm::X86TargetLowering::EmitInstrWithCustomInserter(), emitMonitor(), llvm::PPCTargetLowering::EmitPartwordAtomicBinary(), llvm::TargetLoweringBase::emitPatchPoint(), emitPCMPSTRI(), emitPCMPSTRM(), emitPostSt(), emitRDPKRU(), llvm::MSP430TargetLowering::EmitShiftInstr(), emitSplitF64Pseudo(), emitWRPKRU(), emitXBegin(), llvm::TargetLoweringBase::emitXRayCustomEvent(), llvm::TargetLoweringBase::emitXRayTypedEvent(), expandLoadStackGuard(), expandMOV32r1(), ExpandMOVImmSExti8(), llvm::Nios2InstrInfo::expandPostRAPseudo(), llvm::HexagonInstrInfo::expandPostRAPseudo(), llvm::AArch64InstrInfo::expandPostRAPseudo(), llvm::PPCInstrInfo::expandPostRAPseudo(), llvm::SparcTargetLowering::expandSelectCC(), findIncDecAfter(), findPotentialBlockers(), findSingleRegDef(), FindStartOfTree(), llvm::fixStackStores(), fixupRegionExits(), llvm::ARMBaseInstrInfo::FoldImmediate(), llvm::SystemZInstrInfo::foldMemoryOperandImpl(), foldPatchpoint(), foldVGPRCopyIntoRegSequence(), forceReg(), FuseInst(), FuseTwoAddrInst(), llvm::AArch64InstrInfo::genAlternativeCodeSequence(), genFusedMultiply(), genMaddR(), getAdjustedCmp(), getCmpForPseudo(), GetDSubRegs(), llvm::HexagonHazardRecognizer::getHazardType(), getMappedOp(), getNewSource(), getNewValueJumpOpcode(), getPostIndexedLoadStoreOpcode(), getRegClassFromGRPhysReg(), getRegsUsedByPHIs(), getRetpolineSymbol(), getSmrdOpcode(), getSubOpcode(), getTag(), llvm::BPFTargetLowering::getTargetNodeName(), getUnconditionalBrDisp(), llvm::MipsTargetLowering::HandleByVal(), HandleVRSaveUpdate(), hasUseAfterLoop(), ImmInRange(), INITIALIZE_PASS(), llvm::DbgVariable::initializeDbgValue(), insertCopy(), insertDivByZeroTrap(), InsertFPConstInst(), InsertFPImmInst(), insertNopBeforeInstruction(), insertPHI(), InsertSPConstInst(), InsertSPImmInst(), isCopy(), llvm::isCopyMulResult(), isDbgValueDescribedByReg(), isDebug(), isFpMulInstruction(), isFullCopyOf(), isFunctionEntryBlock(), isIdenticalTo(), isInRage(), isLEASimpleIncOrDec(), isLiveOut(), isPHIRegionIndex(), IsSafeAndProfitableToMove(), isSimpleIf(), isSourceDefinedByImplicitDef(), llvm::SIInstrInfo::legalizeOperands(), llvm::SIInstrInfo::legalizeOperandsVOP2(), loadM0FromVGPR(), llvm::PPCRegisterInfo::lowerCRBitRestore(), llvm::PPCRegisterInfo::lowerCRBitSpilling(), llvm::PPCRegisterInfo::lowerCRRestore(), llvm::PPCRegisterInfo::lowerCRSpilling(), llvm::PPCRegisterInfo::lowerDynamicAlloc(), llvm::PPCRegisterInfo::lowerDynamicAreaOffset(), LowerFPToInt(), lowerVECTOR_SHUFFLE_VSHF(), llvm::PPCRegisterInfo::lowerVRSAVERestore(), llvm::PPCRegisterInfo::lowerVRSAVESpilling(), makeImplicit(), MakeM0Inst(), MaybeRewriteToFallthrough(), Mips16WhichOp8uOr16simm(), MoveAndTeeForMultiUse(), llvm::SIInstrInfo::moveToVALU(), opcodeEmitsNoInsts(), llvm::PPCInstrInfo::optimizeCompareInstr(), llvm::AArch64InstrInfo::optimizeCondBranch(), llvm::LanaiInstrInfo::optimizeSelect(), llvm::ARMBaseInstrInfo::optimizeSelect(), parseCond(), llvm::HexagonInstrInfo::PredicateInstruction(), llvm::MIPrinter::print(), print(), printExtendedName(), profitImm(), llvm::SIInstrInfo::readlaneVGPRToSGPR(), readsVCCZ(), llvm::TargetInstrInfo::reassociateOps(), llvm::HexagonInstrInfo::reduceLoopCount(), registerDefinedBetween(), regOverlapsSet(), llvm::ARMBaseInstrInfo::reMaterialize(), llvm::X86InstrInfo::reMaterialize(), ReplaceFrameIndex(), llvm::ARMTargetLowering::ReplaceNodeResults(), llvm::reportGISelFailure(), llvm::rewriteAArch64FrameIndex(), llvm::ThumbRegisterInfo::rewriteFrameIndex(), llvm::SelectionDAGISel::runOnMachineFunction(), selectCopy(), selectFP16CopyFromGPR32(), llvm::ARMBaseInstrInfo::setExecutionDomain(), setM0ToIndexFromSGPR(), shrinkScalarCompare(), SinkingPreventsImplicitNullCheck(), llvm::X86FrameLowering::spillCalleeSavedRegisters(), splitBlock(), splitMBB(), llvm::SystemZInstrInfo::SystemZInstrInfo(), tryOptimizeLEAtoMOV(), tryOrrMovk(), trySequenceOfOnes(), tryToreplicateChunks(), llvm::X86InstrInfo::unfoldMemoryOperand(), validThroughout(), and VerifyLowRegs().

◆ getDebugVariable()

const DILocalVariable * MachineInstr::getDebugVariable ( ) const

◆ getDesc()

const MCInstrDesc& llvm::MachineInstr::getDesc ( ) const
inline

Returns the target instruction descriptor of this MachineInstr.

Definition at line 290 of file MachineInstr.h.

Referenced by llvm::addFrameReference(), addImplicitDefUseOperands(), addLiveInRegs(), addRegsToSet(), llvm::ARMTargetLowering::AdjustInstrPostInstrSelection(), llvm::TargetInstrInfo::analyzeSelect(), AnyAliasLiveIn(), llvm::ARMBaseInstrInfo::breakPartialRegDependency(), llvm::buildDbgValueForSpill(), llvm::HexagonPacketizerList::canPromoteToDotNew(), llvm::HexagonPacketizerList::canPromoteToNewValueStore(), llvm::DFAPacketizer::canReserveResources(), llvm::TargetInstrInfo::commuteInstructionImpl(), llvm::PPCInstrInfo::commuteInstructionImpl(), commuteVPTERNLOG(), computeBytesPoppedByCalleeForSRet(), llvm::TargetSchedModel::computeOperandLatency(), llvm::TargetSchedModel::computeReciprocalThroughput(), llvm::constrainSelectedInstRegOperands(), llvm::ARMBaseInstrInfo::convertToThreeAddress(), copyExtraImplicitOps(), copyImplicitOps(), countOperands(), llvm::createBreakFalseDeps(), llvm::createHexagonHardwareLoops(), llvm::createX86OptimizeLEAs(), CriticalPathStep(), definesFullReg(), defs(), llvm::HexagonFrameLowering::determineCalleeSaves(), llvm::ARMBaseRegisterInfo::eliminateFrameIndex(), llvm::TargetLoweringBase::emitPatchPoint(), llvm::TargetLoweringBase::emitXRayCustomEvent(), llvm::TargetLoweringBase::emitXRayTypedEvent(), llvm::LiveRangeEdit::eraseVirtReg(), llvm::Nios2InstrInfo::expandPostRAPseudo(), llvm::MipsSEInstrInfo::expandPostRAPseudo(), llvm::Mips16InstrInfo::expandPostRAPseudo(), explicit_uses(), llvm::MipsInstrInfo::findCommutedOpIndices(), llvm::X86InstrInfo::findCommutedOpIndices(), llvm::TargetInstrInfo::findCommutedOpIndices(), findFirstPredOperandIdx(), llvm::X86InstrInfo::findFMA3CommutedOpIndices(), findPotentialBlockers(), FindStartOfTree(), llvm::PPCInstrInfo::FoldImmediate(), llvm::ARMBaseInstrInfo::FoldImmediate(), llvm::X86InstrInfo::foldMemoryOperandImpl(), FuseTwoAddrInst(), llvm::HexagonInstrInfo::genAllInsnTimingClasses(), llvm::LegalizerInfo::getAction(), llvm::HexagonInstrInfo::getAddrMode(), getAddrOffset(), llvm::RISCVInstrInfo::getBranchDestBlock(), llvm::HexagonInstrInfo::getCExtOpNum(), llvm::SIInstrInfo::getClampMask(), getCompareSourceReg(), GetDSubRegs(), llvm::ARMBaseInstrInfo::getExecutionDomain(), llvm::X86InstrInfo::getExecutionDomain(), llvm::ARMBaseInstrInfo::getExtractSubregLikeInputs(), llvm::X86InstrInfo::getFMA3OpcodeToCommuteOperands(), getFPReg(), llvm::ARMBaseRegisterInfo::getFrameIndexInstrOffset(), llvm::ARMHazardRecognizer::getHazardType(), llvm::ARMBaseInstrInfo::getInsertSubregLikeInputs(), llvm::ScheduleDAG::getInstrDesc(), llvm::PPCInstrInfo::getInstrLatency(), llvm::TargetInstrInfo::getInstrLatency(), llvm::HexagonInstrInfo::getInstrTimingClassLatency(), llvm::AArch64InstrInfo::getInstSizeInBytes(), llvm::ARCInstrInfo::getInstSizeInBytes(), llvm::MSP430InstrInfo::getInstSizeInBytes(), llvm::MipsInstrInfo::getInstSizeInBytes(), llvm::ARMBaseInstrInfo::getInstSizeInBytes(), llvm::SystemZInstrInfo::getInstSizeInBytes(), llvm::ARMBaseInstrInfo::getLDMVariableDefsSize(), getLSMultipleTransferSize(), llvm::HexagonInstrInfo::getMaxValue(), llvm::HexagonInstrInfo::getMemAccessSize(), llvm::X86InstrInfo::getMemOpBaseRegImmOfs(), getMemoryOpOffset(), llvm::HexagonInstrInfo::getMinValue(), getNewSource(), getNewValueJumpOpcode(), llvm::HexagonInstrInfo::getNonExtOpcode(), llvm::TargetSchedModel::getNumMicroOps(), llvm::ARMBaseInstrInfo::getNumMicroOps(), llvm::TargetInstrInfo::getNumMicroOps(), getNumMicroOpsSwiftLdSt(), llvm::ARMBaseInstrInfo::getOperandLatency(), llvm::TargetInstrInfo::getOperandLatency(), llvm::X86InstrInfo::getOutliningType(), getPostIncrementOperand(), getRegClassConstraint(), llvm::ARMBaseInstrInfo::getRegSequenceLikeInputs(), llvm::HexagonInstrInfo::getSize(), getTargetMBB(), getTruncatedShiftCount(), llvm::HexagonInstrInfo::getType(), getTypeToPrint(), getUnconditionalBrDisp(), getUnderlyingObjects(), llvm::HexagonInstrInfo::getUnits(), getX86SSEConditionCode(), hasComplexRegisterTies(), llvm::MipsInstrInfo::HasForbiddenSlot(), llvm::SIInstrInfo::hasFPClamp(), llvm::SIInstrInfo::hasIntClamp(), llvm::TargetInstrInfo::hasLowDefLatency(), llvm::HexagonInstrInfo::hasNonExtEquivalent(), hasProperty(), hasRAWHazard(), llvm::HexagonPacketizerList::ignorePseudoInstruction(), INITIALIZE_PASS(), insertPHI(), llvm::HexagonInstrInfo::isAccumulator(), llvm::HexagonInstrInfo::isAddrModeWithOffset(), llvm::SIInstrInfo::isBufferSMRD(), llvm::HexagonInstrInfo::isComplex(), llvm::HexagonInstrInfo::isConstExtended(), isControlFlow(), isCopy(), isCopyFeedingInvariantStore(), isCrossCopy(), llvm::SIInstrInfo::isD16(), llvm::HexagonInstrInfo::isDependent(), llvm::SIInstrInfo::isDisableWQM(), llvm::SIInstrInfo::isDPP(), llvm::SIInstrInfo::isDS(), llvm::HexagonInstrInfo::isEarlySourceInstr(), llvm::SIInstrInfo::isEXP(), llvm::HexagonInstrInfo::isExtendable(), llvm::HexagonInstrInfo::isExtended(), llvm::rdf::TargetOperandInfo::isFixedReg(), llvm::SIInstrInfo::isFixedSize(), llvm::SIInstrInfo::isFLAT(), llvm::SIInstrInfo::isFoldableCopy(), isFpMulInstruction(), llvm::AArch64InstrInfo::isFPRCopy(), llvm::ARMBaseRegisterInfo::isFrameOffsetLegal(), llvm::SIInstrInfo::isGather4(), llvm::AArch64InstrInfo::isGPRCopy(), llvm::AArch64InstrInfo::isGPRZero(), isHighLatencyCPSR(), isImmValidForOpcode(), llvm::SIInstrInfo::isInlineConstant(), llvm::HexagonInstrInfo::isLateResultInstr(), isLEASimpleIncOrDec(), llvm::NVPTXInstrInfo::isLoadInstr(), llvm::SIInstrInfo::isMIMG(), llvm::NVPTXInstrInfo::isMoveInstr(), llvm::SIInstrInfo::isMTBUF(), llvm::SIInstrInfo::isMUBUF(), isMulPowOf2(), llvm::HexagonInstrInfo::isNewValue(), llvm::HexagonInstrInfo::isNewValueStore(), llvm::HexagonInstrInfo::isOperandExtended(), isOperandKill(), llvm::SIInstrInfo::isOperandLegal(), llvm::ARMBaseInstrInfo::isPredicable(), llvm::HexagonInstrInfo::isPredicable(), llvm::TargetInstrInfo::isPredicable(), llvm::HexagonInstrInfo::isPredicated(), llvm::HexagonInstrInfo::isPredicatedNew(), llvm::HexagonInstrInfo::isPredicatedTrue(), llvm::SIInstrInfo::isSALU(), llvm::SIInstrInfo::isScalarStore(), llvm::SIInstrInfo::isScalarUnit(), llvm::HexagonInstrInfo::isSchedulingBoundary(), llvm::SIInstrInfo::isSDWA(), llvm::SIInstrInfo::isSegmentSpecificFLAT(), llvm::SIInstrInfo::isSGPRSpill(), isSimpleBD12Move(), isSimpleMove(), llvm::SIInstrInfo::isSMRD(), llvm::HexagonInstrInfo::isSolo(), llvm::SIInstrInfo::isSOP1(), llvm::SIInstrInfo::isSOP2(), llvm::SIInstrInfo::isSOPC(), llvm::SIInstrInfo::isSOPK(), llvm::SIInstrInfo::isSOPP(), llvm::NVPTXInstrInfo::isStoreInstr(), llvm::HexagonInstrInfo::isTC1(), llvm::HexagonInstrInfo::isTC2(), llvm::HexagonInstrInfo::isTC2Early(), llvm::HexagonInstrInfo::isTC4x(), llvm::TargetInstrInfo::isTriviallyReMaterializable(), isUseSafeToFold(), llvm::SIInstrInfo::isVALU(), llvm::SIInstrInfo::isVGPRSpill(), llvm::SIInstrInfo::isVINTRP(), isVirtualRegisterOperand(), llvm::SIInstrInfo::isVOP1(), llvm::SIInstrInfo::isVOP2(), llvm::SIInstrInfo::isVOP3(), llvm::SIInstrInfo::isVOP3P(), llvm::SIInstrInfo::isVOPC(), llvm::SIInstrInfo::isWQM(), llvm::WebAssemblyMCInstLower::Lower(), MakeM0Inst(), matchPair(), llvm::HexagonInstrInfo::mayBeCurLoad(), llvm::HexagonInstrInfo::mayBeNewStore(), llvm::SIInstrInfo::moveToVALU(), OneUseDominatesOtherUses(), llvm::SystemZInstrInfo::optimizeCompareInstr(), llvm::LanaiInstrInfo::optimizeSelect(), llvm::ARMBaseInstrInfo::optimizeSelect(), parseCondBranch(), performCustomAdjustments(), llvm::TargetInstrInfo::PredicateInstruction(), readsVCCZ(), registerDefinedBetween(), regOverlapsSet(), llvm::DFAPacketizer::reserveResources(), llvm::PPCRegisterInfo::resolveFrameIndex(), llvm::TargetSchedModel::resolveSchedClass(), llvm::rewriteARMFrameIndex(), llvm::ThumbRegisterInfo::rewriteFrameIndex(), RewriteP2Align(), llvm::rewriteT2FrameIndex(), llvm::Localizer::runOnMachineFunction(), llvm::MipsInstrInfo::SafeInForbiddenSlot(), llvm::ARMBaseInstrInfo::setExecutionDomain(), llvm::X86InstrInfo::setExecutionDomain(), llvm::X86InstrInfo::setExecutionDomainCustom(), llvm::SIInstrInfo::sopkIsZext(), stripExtraCopyOperands(), stripRegisterPrefix(), tieOpsIfNeeded(), updateOperand(), usedAsAddr(), uses(), llvm::SIInstrInfo::usesLGKM_CNT(), llvm::SIInstrInfo::usesVM_CNT(), llvm::SIInstrInfo::verifyInstruction(), VerifyLowRegs(), and VisitGlobalVariableForEmission().

◆ getFlag()

bool llvm::MachineInstr::getFlag ( MIFlag  Flag) const
inline

◆ getFlags()

uint8_t llvm::MachineInstr::getFlags ( ) const
inline

Return the MI flags bitvector.

Definition at line 178 of file MachineInstr.h.

Referenced by ImmInRange(), mergeFlagsWith(), and VerifyLowRegs().

◆ getInlineAsmDialect()

InlineAsm::AsmDialect MachineInstr::getInlineAsmDialect ( ) const

◆ getMF() [1/2]

const MachineFunction * MachineInstr::getMF ( ) const

◆ getMF() [2/2]

MachineFunction* llvm::MachineInstr::getMF ( )
inline

Definition at line 151 of file MachineInstr.h.

References getMF().

◆ getNumExplicitOperands()

unsigned MachineInstr::getNumExplicitOperands ( ) const

◆ getNumMemOperands()

unsigned llvm::MachineInstr::getNumMemOperands ( ) const
inline

Return the number of memory operands.

Definition at line 412 of file MachineInstr.h.

◆ getNumOperands()

unsigned llvm::MachineInstr::getNumOperands ( ) const
inline

Access to explicit operands of the instruction.

Definition at line 296 of file MachineInstr.h.

Referenced by addImplicitDefUseOperands(), addLiveInRegs(), addOperand(), addRegisterDead(), addRegisterKilled(), addRegsToSet(), llvm::ARMTargetLowering::AdjustInstrPostInstrSelection(), llvm::HexagonSubtarget::adjustSchedDependency(), llvm::X86InstrInfo::analyzeBranchPredicate(), llvm::AArch64InstrInfo::analyzeCompare(), llvm::LiveRangeEdit::anyRematerializable(), llvm::HexagonSubtarget::CallMutation::apply(), AssignProtectedObjSet(), BBIsJumpedOver(), llvm::CriticalAntiDepBreaker::BreakAntiDependencies(), llvm::ScheduleDAGInstrs::buildSchedGraph(), llvm::EHStreamer::callToNoUnwindFunction(), canCombine(), llvm::HexagonInstrInfo::canExecuteInBundle(), canFoldCopy(), canFoldIntoMOVCC(), canFoldIntoSelect(), llvm::HexagonPacketizerList::canPromoteToNewValueStore(), canTurnIntoCOPY(), changeFCMPPredToAArch64CC(), clobbersCTR(), collectDebugValues(), llvm::X86InstrInfo::commuteInstructionImpl(), commuteVPTERNLOG(), llvm::HexagonEvaluator::composeWithSubRegIndex(), llvm::PPCInstrInfo::convertToImmediateForm(), llvm::ARMBaseInstrInfo::convertToThreeAddress(), llvm::SystemZInstrInfo::convertToThreeAddress(), llvm::X86InstrInfo::convertToThreeAddress(), copyExtraImplicitOps(), copyImplicitOps(), countersNonZero(), countOperands(), llvm::createBreakFalseDeps(), llvm::createHexagonHardwareLoops(), llvm::createX86FixupBWInsts(), llvm::createX86FixupLEAs(), llvm::createX86OptimizeLEAs(), CriticalPathStep(), definesFullReg(), llvm::ARMBaseInstrInfo::DefinesPredicate(), llvm::HexagonInstrInfo::DefinesPredicate(), llvm::PPCInstrInfo::DefinesPredicate(), doCandidateWalk(), dumpMachineInstrRangeWithSlotIndex(), llvm::BPFRegisterInfo::eliminateFrameIndex(), emitClzero(), llvm::InstrEmitter::EmitDbgValue(), emitDebugValueComment(), emitError(), EmitGCCInlineAsmStr(), llvm::X86AsmPrinter::EmitInstruction(), llvm::R600TargetLowering::EmitInstrWithCustomInserter(), llvm::SITargetLowering::EmitInstrWithCustomInserter(), llvm::ARMTargetLowering::EmitInstrWithCustomInserter(), llvm::ARMAsmPrinter::EmitJumpTableTBInst(), emitKill(), EmitMSInlineAsmStr(), EmitNops(), llvm::TargetLoweringBase::emitPatchPoint(), emitPCMPSTRI(), emitPCMPSTRM(), llvm::TargetLoweringBase::emitXRayCustomEvent(), llvm::TargetLoweringBase::emitXRayTypedEvent(), eraseGPOpnd(), llvm::LiveRangeEdit::eraseVirtReg(), llvm::BitTracker::MachineEvaluator::evaluate(), findCorrespondingPred(), findFirstPredOperandIdx(), findIncDecAfter(), findInlineAsmFlagIdx(), findRegisterDefOperandIdx(), findRegisterUseOperandIdx(), findSingleRegDef(), findTiedOperandIdx(), finishConvertToThreeAddress(), llvm::PPCInstrInfo::FoldImmediate(), foldPatchpoint(), foldVGPRCopyIntoRegSequence(), FuseInst(), FuseTwoAddrInst(), getCallTargetRegOpnd(), getCompareSourceReg(), getDebugLocValue(), getEquivalentCallShort(), llvm::X86InstrInfo::getExecutionDomainCustom(), getFPReg(), getFrameIndexOperandNum(), llvm::MachineInstrExpressionTrait::getHashValue(), llvm::HexagonHazardRecognizer::getHazardType(), getInitPhiReg(), llvm::X86RegisterBankInfo::getInstrAlternativeMappings(), llvm::AArch64RegisterBankInfo::getInstrAlternativeMappings(), llvm::PPCInstrInfo::getInstrLatency(), llvm::ARMRegisterBankInfo::getInstrMapping(), llvm::MipsRegisterBankInfo::getInstrMapping(), llvm::AMDGPURegisterBankInfo::getInstrMapping(), llvm::X86RegisterBankInfo::getInstrMapping(), llvm::AArch64RegisterBankInfo::getInstrMapping(), llvm::RegisterBankInfo::getInstrMappingImpl(), getInstrVecReg(), llvm::ARMBaseInstrInfo::getLDMVariableDefsSize(), getLoopPhiReg(), getLSMultipleTransferSize(), llvm::LanaiInstrInfo::getMemOpBaseRegImmOfsWidth(), getNewValueJumpOpcode(), llvm::PatchPointOpers::getNextScratchIdx(), llvm::rdf::DataFlowGraph::getNextShadow(), getNumExplicitOperands(), llvm::ARMBaseInstrInfo::getNumMicroOps(), getOperand(), llvm::X86GenRegisterBankInfo::getPartialMappingIdx(), getPHIDeps(), getPHINumInputs(), getPhiRegs(), getPHISrcRegOpIdx(), getRegClassFromGRPhysReg(), llvm::TargetInstrInfo::getRegSequenceInputs(), getRegsUsedByPHIs(), llvm::HexagonInstrInfo::getSize(), getStoreValueOperand(), getTag(), getTypeFromTypeIdx(), getUnconditionalBrDisp(), getX86SSEConditionCode(), llvm::LiveVariables::HandleVirtRegDef(), HandleVRSaveUpdate(), hasComplexRegisterTies(), HashMachineInstr(), llvm::X86InstrInfo::hasLiveCondCodeDef(), llvm::X86InstrInfo::hasReassociableOperands(), hasRegisterDependency(), hasRegisterImplicitUseOperand(), hasVGPROperands(), llvm::HexagonLowerToMC(), INITIALIZE_PASS(), InsertLDR_STR(), llvm::Mips16RegisterInfo::intRegClass(), llvm::HexagonInstrInfo::invertAndChangeJumpTarget(), isBinary(), llvm::WebAssembly::isChild(), isConstantValuePHI(), isCopyFeedingInvariantStore(), isCSRestore(), isDbgValueDescribedByReg(), isDebug(), isDescribedByReg(), llvm::SIInstrInfo::isFoldableCopy(), llvm::ARMBaseRegisterInfo::isFrameOffsetLegal(), isFullCopyOf(), isFullUndefDef(), isIdenticalTo(), isImmValidForOpcode(), isImplicitlyDef(), isInstrUniform(), isInvariantStore(), llvm::ARMBaseInstrInfo::isLDMBaseRegInList(), llvm::isLeaMem(), llvm::isMem(), isNullary(), llvm::SIInstrInfo::isOperandLegal(), isPreISelGenericFloatingPointOpcode(), llvm::PPCInstrInfo::isSignOrZeroExtended(), isSourceDefinedByImplicitDef(), llvm::ARMBaseInstrInfo::isSwiftFastImmShift(), llvm::HexagonInstrInfo::isToBeScheduledASAP(), isTwoAddrUse(), isVirtualRegisterOperand(), llvm::SIInstrInfo::legalizeOperands(), lookupCandidateBaseReg(), llvm::XCoreMCInstLower::Lower(), llvm::SystemZMCInstLower::lower(), llvm::MSP430MCInstLower::Lower(), llvm::ARCMCInstLower::Lower(), llvm::BPFMCInstLower::Lower(), llvm::LanaiMCInstLower::Lower(), llvm::MipsMCInstLower::Lower(), llvm::WebAssemblyMCInstLower::Lower(), llvm::LowerNios2MachineInstToMCInst(), llvm::LowerPPCMachineInstrToMCInst(), llvm::LowerSparcMachineInstrToMCInst(), lowerVECTOR_SHUFFLE_VSHF(), MakeM0Inst(), llvm::MIPatternMatch::BinaryOp_match< LHS_P, RHS_P, Opcode, Commutable >::match(), llvm::MIPatternMatch::UnaryOp_match< SrcTy, Opcode >::match(), matchPair(), llvm::DebugLocEntry::MergeValues(), llvm::SIInstrInfo::moveToVALU(), multipleIterations(), llvm::AggressiveAntiDepBreaker::Observe(), false::IntervalSorter::operator()(), llvm::LanaiInstrInfo::optimizeCompareInstr(), llvm::ARMBaseInstrInfo::optimizeCompareInstr(), llvm::X86InstrInfo::optimizeCompareInstr(), llvm::X86InstrInfo::optimizeLoadInstr(), llvm::LanaiInstrInfo::optimizeSelect(), llvm::ARMBaseInstrInfo::optimizeSelect(), parseOperands(), llvm::PatchPointOpers::PatchPointOpers(), phiHasBreakDef(), phiHasVGPROperands(), populateCandidates(), llvm::HexagonInstrInfo::PredicateInstruction(), llvm::TargetInstrInfo::PredicateInstruction(), llvm::MIPrinter::print(), print(), llvm::MipsAsmPrinter::PrintAsmMemoryOperand(), llvm::ARMAsmPrinter::PrintAsmOperand(), llvm::MipsAsmPrinter::PrintAsmOperand(), printExtendedName(), llvm::MipsAsmPrinter::printMemOperand(), llvm::MipsAsmPrinter::printRegisterList(), llvm::ARMBaseInstrInfo::produceSameValue(), readsVCCZ(), readsWritesVirtualRegister(), regOverlapsSet(), removeKillInfo(), RemoveOperand(), removeOperands(), removePhis(), llvm::LiveVariables::removeVirtualRegisterDead(), llvm::LiveVariables::removeVirtualRegisterKilled(), llvm::LiveVariables::removeVirtualRegistersKilled(), llvm::PPCInstrInfo::replaceInstrWithLI(), llvm::ThumbRegisterInfo::resolveFrameIndex(), llvm::AArch64RegisterInfo::resolveFrameIndex(), llvm::PPCRegisterInfo::resolveFrameIndex(), llvm::ARMBaseRegisterInfo::resolveFrameIndex(), resultTests(), llvm::rewriteT2FrameIndex(), llvm::DetectRoundChange::runOnMachineFunction(), llvm::X86InstrInfo::setExecutionDomainCustom(), llvm::X86InstrInfo::setSpecialOperandAttr(), simpleLibcall(), SinkingPreventsImplicitNullCheck(), sizeOfSPAdjustment(), llvm::StackMapOpers::StackMapOpers(), stripExtraCopyOperands(), stripRegisterPrefix(), swapMIOperands(), llvm::SystemZInstrInfo::SystemZInstrInfo(), TrackDefUses(), llvm::TargetInstrInfo::trackRegDefsUses(), llvm::MachineBasicBlock::transferSuccessorsAndUpdatePHIs(), llvm::LegalizationArtifactCombiner::tryCombineMerges(), llvm::tryFoldSPUpdateIntoPushPop(), llvm::X86InstrInfo::unfoldMemoryOperand(), UpdateOperandRegClass(), usedAsAddr(), llvm::HexagonSubtarget::usePredicatedCalls(), llvm::SSAUpdaterTraits< MachineSSAUpdater >::ValueIsNewPHI(), llvm::RegisterBankInfo::InstructionMapping::verify(), llvm::SIInstrInfo::verifyInstruction(), VerifyLowRegs(), llvm::MachineRegisterInfo::verifyUseList(), VisitGlobalVariableForEmission(), and llvm::LegalizerHelper::widenScalar().

◆ getOpcode()

unsigned llvm::MachineInstr::getOpcode ( ) const
inline

Returns the opcode of this MachineInstr.

Definition at line 293 of file MachineInstr.h.

References llvm::MCInstrDesc::Opcode.

Referenced by addExclusiveRegPair(), llvm::R600InstrInfo::addFlag(), addRegsToSet(), llvm::SITargetLowering::AdjustInstrPostInstrSelection(), llvm::ARMTargetLowering::AdjustInstrPostInstrSelection(), llvm::analyzeArguments(), llvm::XCoreInstrInfo::analyzeBranch(), llvm::NVPTXInstrInfo::analyzeBranch(), llvm::SparcInstrInfo::analyzeBranch(), llvm::MipsInstrInfo::analyzeBranch(), llvm::HexagonInstrInfo::analyzeBranch(), llvm::R600InstrInfo::analyzeBranch(), llvm::AArch64InstrInfo::analyzeBranch(), llvm::PPCInstrInfo::analyzeBranch(), llvm::X86InstrInfo::analyzeBranchPredicate(), llvm::LanaiInstrInfo::analyzeCompare(), llvm::AArch64InstrInfo::analyzeCompare(), llvm::HexagonInstrInfo::analyzeCompare(), llvm::ARMBaseInstrInfo::analyzeCompare(), llvm::PPCInstrInfo::analyzeCompare(), llvm::X86InstrInfo::analyzeCompare(), llvm::LanaiInstrInfo::analyzeSelect(), llvm::ARMBaseInstrInfo::analyzeSelect(), AnyAliasLiveIn(), llvm::HexagonSubtarget::HVXMemLatencyMutation::apply(), areCandidatesToMergeOrPair(), areCombinableOperations(), llvm::HexagonFrameLowering::assignCalleeSavedSpillSlots(), AssignProtectedObjSet(), BBHasFallthrough(), BBIsJumpedOver(), branchTargetOperand(), llvm::R600InstrInfo::buildSlotOfVectorInstruction(), llvm::R600InstrInfo::canBeConsideredALU(), canCombine(), canCompareBeNewValueJump(), canDefBePartOfLOH(), llvm::HexagonInstrInfo::canExecuteInBundle(), canFoldIntoCSel(), canInstrSubstituteCmpInstr(), llvm::X86InstrInfo::canMakeTailCallConditional(), canMoveInstsAcrossMemOp(), cannotCoexistAsymm(), llvm::SIInstrInfo::canReadVGPR(), canShrink(), canTurnIntoCOPY(), llvm::HexagonInstrInfo::changeAddrMode_abs_io(), llvm::HexagonInstrInfo::changeAddrMode_io_abs(), llvm::HexagonInstrInfo::changeAddrMode_io_rr(), llvm::HexagonInstrInfo::changeAddrMode_rr_io(), llvm::HexagonInstrInfo::changeAddrMode_rr_ur(), llvm::HexagonInstrInfo::changeAddrMode_ur_rr(), changeFCMPPredToAArch64CC(), changesVGPRIndexingMode(), llvm::R600InstrInfo::clearFlag(), llvm::ARMBaseInstrInfo::commuteInstructionImpl(), llvm::SIInstrInfo::commuteInstructionImpl(), llvm::PPCInstrInfo::commuteInstructionImpl(), llvm::SystemZInstrInfo::commuteInstructionImpl(), llvm::X86InstrInfo::commuteInstructionImpl(), llvm::SIInstrInfo::commuteOpcode(), computeBranchTargetAndInversion(), llvm::constrainSelectedInstRegOperands(), ContainsReg(), conversionLibcall(), ConvertImplicitDefToConstZero(), llvm::PPCInstrInfo::convertToImmediateForm(), convertToNonFlagSettingOpc(), llvm::ARMBaseInstrInfo::convertToThreeAddress(), llvm::SystemZInstrInfo::convertToThreeAddress(), llvm::X86InstrInfo::convertToThreeAddress(), llvm::SIInstrInfo::convertToThreeAddress(), llvm::createHexagonHardwareLoops(), createPHIsForCMOVsInSinkBB(), llvm::createR600ExpandSpecialInstrsPass(), llvm::createSIFixWWMLivenessPass(), llvm::createSILowerI1CopiesPass(), llvm::createSIWholeQuadModePass(), llvm::createX86FixupBWInsts(), llvm::createX86FixupSetCC(), llvm::TargetInstrInfo::defaultDefLatency(), llvm::R600InstrInfo::DefinesPredicate(), llvm::ARMFrameLowering::determineCalleeSaves(), doesNotGeneratecode(), llvm::HexagonInstrInfo::doesNotReturn(), dumpMachineInstrRangeWithSlotIndex(), llvm::SystemZHazardRecognizer::dumpSU(), llvm::SparcFrameLowering::eliminateCallFramePseudoInstr(), llvm::MSP430FrameLowering::eliminateCallFramePseudoInstr(), llvm::Thumb1FrameLowering::eliminateCallFramePseudoInstr(), llvm::XCoreFrameLowering::eliminateCallFramePseudoInstr(), llvm::ARCFrameLowering::eliminateCallFramePseudoInstr(), llvm::HexagonFrameLowering::eliminateCallFramePseudoInstr(), llvm::BPFRegisterInfo::eliminateFrameIndex(), llvm::MSP430RegisterInfo::eliminateFrameIndex(), llvm::WebAssemblyRegisterInfo::eliminateFrameIndex(), llvm::SparcRegisterInfo::eliminateFrameIndex(), llvm::LanaiRegisterInfo::eliminateFrameIndex(), llvm::AVRRegisterInfo::eliminateFrameIndex(), llvm::HexagonRegisterInfo::eliminateFrameIndex(), llvm::ThumbRegisterInfo::eliminateFrameIndex(), llvm::AArch64RegisterInfo::eliminateFrameIndex(), llvm::PPCRegisterInfo::eliminateFrameIndex(), llvm::X86RegisterInfo::eliminateFrameIndex(), emitBuildPairF64Pseudo(), EmitHiLo(), llvm::SystemZAsmPrinter::EmitInstruction(), llvm::WebAssemblyAsmPrinter::EmitInstruction(), llvm::HexagonHazardRecognizer::EmitInstruction(), llvm::PPCHazardRecognizer970::EmitInstruction(), llvm::ARMAsmPrinter::EmitInstruction(), llvm::X86AsmPrinter::EmitInstruction(), llvm::MipsAsmPrinter::EmitInstruction(), llvm::AMDGPUAsmPrinter::EmitInstruction(), llvm::Mips16TargetLowering::EmitInstrWithCustomInserter(), llvm::R600TargetLowering::EmitInstrWithCustomInserter(), llvm::RISCVTargetLowering::EmitInstrWithCustomInserter(), llvm::MipsSETargetLowering::EmitInstrWithCustomInserter(), llvm::BPFTargetLowering::EmitInstrWithCustomInserter(), llvm::SparcTargetLowering::EmitInstrWithCustomInserter(), llvm::AVRTargetLowering::EmitInstrWithCustomInserter(), llvm::XCoreTargetLowering::EmitInstrWithCustomInserter(), llvm::MSP430TargetLowering::EmitInstrWithCustomInserter(), llvm::SITargetLowering::EmitInstrWithCustomInserter(), llvm::AArch64TargetLowering::EmitInstrWithCustomInserter(), llvm::ARMTargetLowering::EmitInstrWithCustomInserter(), llvm::MipsTargetLowering::EmitInstrWithCustomInserter(), llvm::SystemZTargetLowering::EmitInstrWithCustomInserter(), llvm::PPCTargetLowering::EmitInstrWithCustomInserter(), llvm::X86TargetLowering::EmitInstrWithCustomInserter(), llvm::ARMAsmPrinter::EmitJumpTableTBInst(), llvm::TargetLoweringBase::emitPatchPoint(), emitPCMPSTRI(), emitPCMPSTRM(), llvm::HexagonFrameLowering::emitPrologue(), llvm::MSP430TargetLowering::EmitShiftInstr(), emitSplitF64Pseudo(), llvm::TargetLoweringBase::emitXRayCustomEvent(), llvm::TargetLoweringBase::emitXRayTypedEvent(), llvm::HexagonEvaluator::evaluate(), llvm::BitTracker::MachineEvaluator::evaluate(), ExpandMOVImmSExti8(), llvm::SparcInstrInfo::expandPostRAPseudo(), llvm::SIInstrInfo::expandPostRAPseudo(), llvm::R600InstrInfo::expandPostRAPseudo(), llvm::ARMBaseInstrInfo::expandPostRAPseudo(), llvm::HexagonInstrInfo::expandPostRAPseudo(), llvm::AArch64InstrInfo::expandPostRAPseudo(), llvm::SystemZInstrInfo::expandPostRAPseudo(), llvm::PPCInstrInfo::expandPostRAPseudo(), llvm::X86InstrInfo::expandPostRAPseudo(), llvm::PPCInstrInfo::expandVSXMemPseudo(), expandXorFP(), llvm::LegalizerHelper::fewerElementsVector(), llvm::MipsInstrInfo::findCommutedOpIndices(), llvm::PPCInstrInfo::findCommutedOpIndices(), llvm::SIInstrInfo::findCommutedOpIndices(), llvm::X86InstrInfo::findCommutedOpIndices(), findCondCodeUsedByInstr(), findFirstPredicateSetterFrom(), findIncDecAfter(), findPotentialBlockers(), findSingleRegDef(), FindStartOfTree(), llvm::R600InstrInfo::fitsConstReadLimitations(), fixupCalleeSaveRestoreStackOffset(), llvm::foldFrameOffset(), llvm::SystemZInstrInfo::FoldImmediate(), llvm::PPCInstrInfo::FoldImmediate(), llvm::SIInstrInfo::FoldImmediate(), llvm::ARMBaseInstrInfo::FoldImmediate(), foldImmediates(), llvm::TargetInstrInfo::foldMemoryOperand(), llvm::SystemZInstrInfo::foldMemoryOperandImpl(), llvm::X86InstrInfo::foldMemoryOperandImpl(), foldPatchpoint(), fuseInstructionPair(), llvm::HexagonInstrInfo::genAllInsnTimingClasses(), llvm::LegalizerInfo::getAction(), getAdjustedCmp(), llvm::HexagonFrameLowering::getAlignaInstr(), llvm::AVRInstrInfo::getBranchDestBlock(), llvm::AArch64InstrInfo::getBranchDestBlock(), llvm::SIInstrInfo::getBranchDestBlock(), llvm::SystemZInstrInfo::getBranchInfo(), getBRccForPseudo(), getCmpForPseudo(), getComparePred(), getCompareSourceReg(), llvm::HexagonInstrInfo::getCompoundCandidateGroup(), llvm::HexagonInstrInfo::getCompoundOpcode(), llvm::getConstantFPVRegVal(), llvm::getConstantVRegVal(), getCopyRewriter(), llvm::HexagonInstrInfo::getDotCurOp(), llvm::HexagonInstrInfo::getDotNewOp(), llvm::HexagonInstrInfo::getDotNewPredJumpOp(), llvm::HexagonInstrInfo::getDotNewPredOp(), llvm::HexagonInstrInfo::getDotOldOp(), GetDSubRegs(), llvm::HexagonInstrInfo::getDuplexCandidateGroup(), llvm::HexagonInstrInfo::getEquivalentHWInstr(), llvm::ARMBaseInstrInfo::getExecutionDomain(), llvm::X86InstrInfo::getExecutionDomain(), llvm::X86InstrInfo::getExecutionDomainCustom(), llvm::ARMBaseInstrInfo::getExtractSubregLikeInputs(), llvm::R600InstrInfo::getFlagOp(), llvm::X86InstrInfo::getFMA3OpcodeToCommuteOperands(), getFMAPatterns(), llvm::SIRegisterInfo::getFrameIndexInstrOffset(), llvm::MachineInstrExpressionTrait::getHashValue(), llvm::ARMHazardRecognizer::getHazardType(), llvm::HexagonHazardRecognizer::getHazardType(), llvm::PPCHazardRecognizer970::getHazardType(), llvm::GCNHazardRecognizer::getHazardType(), llvm::HexagonInstrInfo::getIncrementValue(), llvm::ARMBaseInstrInfo::getInsertSubregLikeInputs(), llvm::AMDGPURegisterBankInfo::getInstrAlternativeMappings(), llvm::X86RegisterBankInfo::getInstrAlternativeMappings(), llvm::AArch64RegisterBankInfo::getInstrAlternativeMappings(), llvm::ARMRegisterBankInfo::getInstrMapping(), llvm::MipsRegisterBankInfo::getInstrMapping(), llvm::AMDGPURegisterBankInfo::getInstrMapping(), llvm::X86RegisterBankInfo::getInstrMapping(), llvm::AArch64RegisterBankInfo::getInstrMapping(), llvm::AArch64InstrInfo::getInstSizeInBytes(), llvm::RISCVInstrInfo::getInstSizeInBytes(), llvm::ARCInstrInfo::getInstSizeInBytes(), llvm::MSP430InstrInfo::getInstSizeInBytes(), llvm::AVRInstrInfo::getInstSizeInBytes(), llvm::MipsInstrInfo::getInstSizeInBytes(), llvm::ARMBaseInstrInfo::getInstSizeInBytes(), llvm::SystemZInstrInfo::getInstSizeInBytes(), llvm::PPCInstrInfo::getInstSizeInBytes(), llvm::SIInstrInfo::getInstSizeInBytes(), llvm::getITInstrPredicate(), getLeaOP(), getLoadInfo(), getLoadStoreOffsetAlign(), getLSMultipleTransferSize(), getMaddPatterns(), getMappedOp(), llvm::LanaiInstrInfo::getMemOpBaseRegImmOfs(), llvm::SIInstrInfo::getMemOpBaseRegImmOfs(), llvm::LanaiInstrInfo::getMemOpBaseRegImmOfsWidth(), llvm::AArch64InstrInfo::getMemOpBaseRegImmOfsWidth(), getMemoryOpOffset(), getMemScale(), llvm::SIRegisterInfo::getMUBUFInstrOffset(), llvm::SIInstrInfo::getNamedImmOperand(), llvm::SIInstrInfo::getNamedOperand(), getNewValueJumpOpcode(), llvm::HexagonInstrInfo::getNonDotCurOp(), llvm::HexagonInstrInfo::getNonExtOpcode(), GetNonPseudoCallIndirectOpcode(), llvm::ARMBaseInstrInfo::getNumMicroOps(), getNumMicroOpsSwiftLdSt(), llvm::SIInstrInfo::getNumWaitStates(), getOffsetONFromFION(), getOModValue(), llvm::getOpcodeDef(), llvm::R600InstrInfo::getOperandIdx(), llvm::ARMBaseInstrInfo::getOperandLatency(), llvm::SIInstrInfo::getOpRegClass(), llvm::AArch64InstrInfo::getOutliningType(), llvm::ARMBaseInstrInfo::getPartialRegUpdateClearance(), llvm::X86InstrInfo::getPartialRegUpdateClearance(), getPostIndexedLoadStoreOpcode(), llvm::HexagonInstrInfo::getPseudoInstrPair(), getReassignedChan(), getRegClassFromGRPhysReg(), llvm::HexagonInstrInfo::getRegForm(), llvm::ARMBaseInstrInfo::getRegSequenceLikeInputs(), getRetOpcode(), getRetpolineSymbol(), llvm::HexagonInstrInfo::getSize(), llvm::TargetInstrInfo::getSPAdjust(), llvm::X86InstrInfo::getSPAdjust(), getSrcFromCopy(), llvm::R600InstrInfo::getSrcs(), getStartOrEndSlot(), getStoreOffset(), getStoreTarget(), getTypeFromTypeIdx(), getUnconditionalBrDisp(), llvm::X86InstrInfo::getUndefRegClearance(), getUnderlyingObjects(), llvm::SIInstrInfo::getVALUOp(), getVariantKind(), getWinAllocaAmount(), handleMiddleInst(), handleUse(), llvm::AArch64InstrInfo::hasExtendedReg(), llvm::X86InstrInfo::hasHighOperandLatency(), HashMachineInstr(), llvm::HexagonInstrInfo::hasNonExtEquivalent(), llvm::HexagonInstrInfo::hasPseudoInstrPair(), llvm::TargetInstrInfo::hasReassociableSibling(), llvm::AArch64InstrInfo::hasShiftedReg(), llvm::HexagonLowerToMC(), hoistAndMergeSGPRInits(), llvm::NVPTXAsmPrinter::ignoreLoc(), ImmInRange(), INITIALIZE_PASS(), insertCopy(), InsertFPConstInst(), InsertFPImmInst(), InsertLDR_STR(), InsertSPConstInst(), InsertSPImmInst(), llvm::PPCInstrInfo::instrHasImmForm(), llvm::rdf::CopyPropagation::interpretAsCopy(), llvm::Mips16RegisterInfo::intRegClass(), llvm::HexagonInstrInfo::invertAndChangeJumpTarget(), llvm::isAArch64FrameOffsetLegal(), llvm::HexagonInstrInfo::isAddrModeWithOffset(), isAnnotationLabel(), llvm::WebAssembly::isArgument(), isArtifact(), llvm::AArch64InstrInfo::isAsCheapAsAMove(), llvm::PPCInstrInfo::isAssociativeAndCommutative(), llvm::AArch64InstrInfo::isAssociativeAndCommutative(), llvm::X86InstrInfo::isAssociativeAndCommutative(), llvm::InstructionSelector::isBaseWithConstantOffset(), llvm::SIInstrInfo::isBasicBlockPrologue(), llvm::AMDGPUAsmPrinter::isBlockOnlyReachableByFallthrough(), isBranchRetTrap(), isBRccPseudo(), llvm::SIInstrInfo::isBufferSMRD(), isBundle(), llvm::WebAssembly::isCallIndirect(), isCandidateLoad(), isCandidateStore(), llvm::AArch64InstrInfo::isCandidateToMergeOrPair(), isCFIInstruction(), isCMOVPseudo(), llvm::AArch64InstrInfo::isCoalescableExtInstr(), llvm::PPCInstrInfo::isCoalescableExtInstr(), llvm::X86InstrInfo::isCoalescableExtInstr(), isCombineInstrCandidateFP(), isCompareZero(), isConstant(), llvm::WebAssembly::isCopy(), isCopy(), isCopy(), isCopyFeedingInvariantStore(), isCopyLike(), isCopyToExec(), isCrossCopy(), isCSRestore(), isCVTAToLocalCombinationCandidate(), llvm::HexagonInstrInfo::isDeallocRet(), isDebug(), isDebugValue(), isDefConvertible(), isDirectJump(), llvm::HexagonInstrInfo::isDotCurInst(), isEHLabel(), isEligibleForITBlock(), isEndCF(), llvm::HexagonInstrInfo::isExtendable(), isExtractSubreg(), llvm::AArch64InstrInfo::isExynosResetFast(), llvm::AArch64InstrInfo::isExynosShiftLeftFast(), llvm::AArch64InstrInfo::isFalkorShiftExtFast(), isFirstInstructionInSequence(), llvm::HexagonInstrInfo::isFloat(), llvm::SIInstrInfo::isFoldableCopy(), isFpMulInstruction(), llvm::AArch64InstrInfo::isFPRCopy(), llvm::TargetInstrInfo::isFrameInstr(), llvm::PPCRegisterInfo::isFrameOffsetLegal(), llvm::TargetInstrInfo::isFrameSetup(), isFuncletReturnInstr(), isGCLabel(), llvm::AArch64InstrInfo::isGPRCopy(), llvm::AArch64InstrInfo::isGPRZero(), isGreaterThanNBitTFRI(), isHardwareLoop(), isHighLatencyCPSR(), llvm::SIInstrInfo::isHighLatencyInstruction(), isIdenticalTo(), llvm::SIInstrInfo::isImmOperandLegal(), isImmValidForOpcode(), isImplicitDef(), isImplicitlyDef(), isIncrementOrDecrement(), llvm::HexagonInstrInfo::isIndirectCall(), llvm::HexagonInstrInfo::isIndirectL4Return(), isInlineAsm(), isInlineConstantIfFolded(), isInsertSubreg(), llvm::HexagonInstrInfo::isJumpR(), llvm::HexagonInstrInfo::isJumpWithinBranchRange(), isKill(), llvm::HexagonInstrInfo::isLateResultInstr(), isLEA(), isLEASimpleIncOrDec(), llvm::HexagonPacketizerList::isLegalToPacketizeTogether(), isLiveOut(), isLoadAbsSet(), isLoadAndTestAsCmp(), llvm::MipsSEInstrInfo::isLoadFromStackSlot(), llvm::ARCInstrInfo::isLoadFromStackSlot(), llvm::XCoreInstrInfo::isLoadFromStackSlot(), llvm::LanaiInstrInfo::isLoadFromStackSlot(), llvm::SparcInstrInfo::isLoadFromStackSlot(), llvm::HexagonInstrInfo::isLoadFromStackSlot(), llvm::AArch64InstrInfo::isLoadFromStackSlot(), llvm::AVRInstrInfo::isLoadFromStackSlot(), llvm::ARMBaseInstrInfo::isLoadFromStackSlot(), llvm::PPCInstrInfo::isLoadFromStackSlot(), llvm::X86InstrInfo::isLoadFromStackSlot(), llvm::LanaiInstrInfo::isLoadFromStackSlotPostFE(), llvm::X86InstrInfo::isLoadFromStackSlotPostFE(), isLogicalOpOnExec(), llvm::HexagonInstrInfo::isLoopN(), llvm::SIInstrInfo::isLowLatencyInstruction(), isMatchingStore(), llvm::HexagonInstrInfo::isMemOp(), isMemoryOp(), isMergeableLdStUpdate(), isMetaInstruction(), isMla(), isMSInlineAsm(), isMul(), isNonFoldablePartialRegisterLoad(), llvm::SIInstrInfo::isNonUniformBranchInstr(), isOptimizeCompareCandidate(), llvm::AArch64InstrInfo::isPairableLdStInst(), isPairedLdSt(), isPHI(), isPhysicalRegCopy(), llvm::R600InstrInfo::isPredicable(), llvm::SystemZInstrInfo::isPredicable(), llvm::HexagonInstrInfo::isPredicable(), llvm::PPCInstrInfo::isPredicable(), isPreISelGenericFloatingPointOpcode(), llvm::ARMBaseInstrInfo::isProfitableToIfCvt(), isPromotableLoadFromStore(), isPromotableZeroStoreInst(), isPushPop(), llvm::WebAssemblyInstrInfo::isReallyTriviallyReMaterializable(), llvm::SIInstrInfo::isReallyTriviallyReMaterializable(), llvm::PPCInstrInfo::isReallyTriviallyReMaterializable(), llvm::X86InstrInfo::isReallyTriviallyReMaterializable(), isRedundantFlagInstr(), llvm::R600InstrInfo::isRegisterLoad(), llvm::R600InstrInfo::isRegisterStore(), isRegSequence(), llvm::VLIWResourceModel::isResourceAvailable(), IsSafeAndProfitableToMove(), isSafeToFoldImmIntoCopy(), llvm::HexagonInstrInfo::isSaveCalleeSavedRegsCall(), llvm::AArch64InstrInfo::isScaledAddr(), isSchedBarrier(), llvm::SIInstrInfo::isSchedulingBoundary(), isSecondInstructionInSequence(), isSendMsgTraceDataOrGDS(), isSExtLoad(), isShift(), llvm::HexagonInstrInfo::isSignExtendingLoad(), isSignExtendingOp(), llvm::PPCInstrInfo::isSignOrZeroExtended(), isSimpleIf(), isSimpleIndexCalc(), llvm::HexagonPacketizerList::isSoloInstruction(), llvm::HexagonInstrInfo::isSpillPredRegOp(), llvm::SystemZInstrInfo::isStackSlotCopy(), llvm::MipsSEInstrInfo::isStoreToStackSlot(), llvm::LanaiInstrInfo::isStoreToStackSlot(), llvm::ARCInstrInfo::isStoreToStackSlot(), llvm::XCoreInstrInfo::isStoreToStackSlot(), llvm::AArch64InstrInfo::isStoreToStackSlot(), llvm::SparcInstrInfo::isStoreToStackSlot(), llvm::HexagonInstrInfo::isStoreToStackSlot(), llvm::AVRInstrInfo::isStoreToStackSlot(), llvm::ARMBaseInstrInfo::isStoreToStackSlot(), llvm::PPCInstrInfo::isStoreToStackSlot(), llvm::X86InstrInfo::isStoreToStackSlot(), llvm::X86InstrInfo::isStoreToStackSlotPostFE(), isSubregToReg(), isSuitableForMask(), isSystemInstr(), llvm::WebAssembly::isTee(), llvm::HexagonInstrInfo::isToBeScheduledASAP(), isTransformable(), isTransient(), llvm::R600InstrInfo::isTransOnly(), llvm::TargetInstrInfo::isTriviallyReMaterializable(), IsUnconditionalJump(), llvm::X86InstrInfo::isUnconditionalTailCall(), llvm::AArch64InstrInfo::isUnscaledLdSt(), isUseDefConvertible(), llvm::HexagonInstrInfo::isVecALU(), llvm::R600InstrInfo::isVector(), llvm::R600InstrInfo::isVectorOnly(), llvm::HexagonInstrInfo::isZeroExtendingLoad(), isZeroExtendingOp(), isZExtLoad(), llvm::AArch64LegalizerInfo::legalizeCustom(), llvm::ARMLegalizerInfo::legalizeCustom(), llvm::SIInstrInfo::legalizeOperands(), llvm::SIInstrInfo::legalizeOperandsVOP2(), llvm::SIInstrInfo::legalizeOperandsVOP3(), llvm::SIInstrInfo::legalizeOpWithMove(), llvm::LegalizerHelper::libcall(), llvm::XCoreMCInstLower::Lower(), llvm::SystemZMCInstLower::lower(), llvm::MSP430MCInstLower::Lower(), llvm::ARCMCInstLower::Lower(), llvm::LanaiMCInstLower::Lower(), llvm::BPFMCInstLower::Lower(), llvm::MipsMCInstLower::Lower(), llvm::AArch64MCInstLower::Lower(), llvm::AMDGPUMCInstLower::lower(), llvm::WebAssemblyMCInstLower::Lower(), llvm::LegalizerHelper::lower(), llvm::LowerARMMachineInstrToMCInst(), LowerFPToInt(), llvm::AVRMCInstLower::lowerInstruction(), llvm::LowerNios2MachineInstToMCInst(), llvm::MipsMCInstLower::LowerOperand(), llvm::LowerPPCMachineInstrToMCInst(), llvm::LowerRISCVMachineInstrToMCInst(), llvm::LowerSparcMachineInstrToMCInst(), makeImplicit(), MakeM0Inst(), llvm::MIPatternMatch::BinaryOp_match< LHS_P, RHS_P, Opcode, Commutable >::match(), llvm::MIPatternMatch::UnaryOp_match< SrcTy, Opcode >::match(), MatchingStackOffset(), matchPair(), mayCombineMisaligned(), llvm::mayOptimizeThumb2Instruction(), MoveAndTeeForMultiUse(), llvm::SIInstrInfo::moveToVALU(), llvm::LegalizerHelper::narrowScalar(), llvm::PPCRegisterInfo::needsFrameBaseReg(), llvm::ARMBaseRegisterInfo::needsFrameBaseReg(), needsStackFrame(), offsetMinAlign(), opcodeEmitsNoInsts(), llvm::rdf::operator<<(), llvm::LanaiInstrInfo::optimizeCompareInstr(), llvm::AArch64InstrInfo::optimizeCompareInstr(), llvm::ARMBaseInstrInfo::optimizeCompareInstr(), llvm::PPCInstrInfo::optimizeCompareInstr(), llvm::X86InstrInfo::optimizeCompareInstr(), llvm::AArch64InstrInfo::optimizeCondBranch(), llvm::LanaiInstrInfo::optimizeSelect(), llvm::ARMBaseInstrInfo::optimizeSelect(), packCmovGroup(), parseCond(), parseCondBranch(), performCustomAdjustments(), phiHasBreakDef(), llvm::HexagonInstrInfo::predCanBeUsedAsDotNew(), llvm::ARMBaseInstrInfo::PredicateInstruction(), llvm::R600InstrInfo::PredicateInstruction(), llvm::SystemZInstrInfo::PredicateInstruction(), llvm::HexagonInstrInfo::PredicateInstruction(), llvm::PPCInstrInfo::PredicateInstruction(), llvm::GCNHazardRecognizer::PreEmitNoops(), preservesValueOf(), llvm::MIPrinter::print(), print(), printConstant(), llvm::MipsAsmPrinter::printMemOperand(), llvm::ARMBaseInstrInfo::produceSameValue(), profitImm(), Query(), llvm::R600InstrInfo::readsLDSSrcReg(), readsVCCZ(), llvm::TargetInstrInfo::reassociateOps(), llvm::StackMaps::recordPatchPoint(), llvm::StackMaps::recordStackMap(), llvm::StackMaps::recordStatepoint(), llvm::HexagonInstrInfo::reduceLoopCount(), regIsPICBase(), registerDefinedBetween(), regOverlapsSet(), llvm::R600SchedStrategy::releaseBottomNode(), llvm::ARMBaseInstrInfo::reMaterialize(), llvm::X86InstrInfo::reMaterialize(), removeIPMBasedCompare(), removeModOperands(), removePhis(), removeRedundantBlockingStores(), removeTerminatorBit(), llvm::X86InstrInfo::replaceBranchWithTailCall(), ReplaceFrameIndex(), llvm::PPCInstrInfo::replaceInstrWithLI(), llvm::VLIWResourceModel::reserveResources(), llvm::HexagonInstrInfo::reversePredSense(), llvm::rewriteAArch64FrameIndex(), llvm::rewriteARMFrameIndex(), llvm::ThumbRegisterInfo::rewriteFrameIndex(), RewriteP2Align(), llvm::rewriteT2FrameIndex(), llvm::InstructionSelect::runOnMachineFunction(), llvm::InsertNOPLoad::runOnMachineFunction(), llvm::Legalizer::runOnMachineFunction(), llvm::DetectRoundChange::runOnMachineFunction(), llvm::FixAllFDIVSQRT::runOnMachineFunction(), llvm::RegBankSelect::runOnMachineFunction(), llvm::AMDGPUInstructionSelector::select(), selectCopy(), llvm::ARMBaseInstrInfo::setExecutionDomain(), llvm::X86InstrInfo::setExecutionDomain(), llvm::X86InstrInfo::setExecutionDomainCustom(), sForm(), llvm::AArch64InstrInfo::shouldClusterMemOps(), shouldReadExec(), shouldScheduleAdjacent(), llvm::shouldScheduleAdjacent(), shrinkScalarCompare(), simpleLibcall(), llvm::SIScheduleDAGMI::SIScheduleDAGMI(), sizeOfSPAdjustment(), splitBlock(), llvm::SITargetLowering::splitKillBlock(), splitMBB(), stripRegisterPrefix(), supportLoadFromLiteral(), swapMIOperands(), tieOpsIfNeeded(), tryAddToFoldList(), tryChangeVGPRtoSGPRinCopy(), llvm::LegalizationArtifactCombiner::tryCombineAnyExt(), llvm::CombinerHelper::tryCombineCopy(), llvm::LegalizationArtifactCombiner::tryCombineInstruction(), llvm::LegalizationArtifactCombiner::tryCombineMerges(), llvm::LegalizationArtifactCombiner::tryCombineSExt(), llvm::LegalizationArtifactCombiner::tryCombineZExt(), tryConstantFoldOp(), llvm::LegalizationArtifactCombiner::tryFoldImplicitDef(), tryFoldInst(), llvm::tryFoldSPUpdateIntoPushPop(), trySequenceOfOnes(), llvm::X86InstrInfo::unfoldMemoryOperand(), UpdateCPSRUse(), updateKillStatus(), updateOperand(), llvm::HexagonPacketizerList::useCalleesSP(), llvm::HexagonPacketizerList::useCallersSP(), usedAsAddr(), llvm::R600InstrInfo::usesTextureCache(), llvm::R600InstrInfo::usesVertexCache(), llvm::MipsInstrInfo::verifyInstruction(), llvm::SIInstrInfo::verifyInstruction(), VerifyLowRegs(), VisitGlobalVariableForEmission(), llvm::LegalizerHelper::widenScalar(), and X86SelectAddress().

◆ getOperand() [1/2]

const MachineOperand& llvm::MachineInstr::getOperand ( unsigned  i) const
inline

Definition at line 298 of file MachineInstr.h.

References assert(), and getNumOperands().

Referenced by addExclusiveRegPair(), addLiveInRegs(), llvm::ScheduleDAGInstrs::addPhysRegDataDeps(), llvm::ScheduleDAGInstrs::addPhysRegDeps(), addRegisterDead(), addRegisterKilled(), addRegsToSet(), addSegmentsWithValNo(), llvm::MachineIRBuilderBase::addUseFromArg(), llvm::ScheduleDAGInstrs::addVRegDefDeps(), llvm::ScheduleDAGInstrs::addVRegUseDeps(), adjustDefLatency(), adjustDown(), llvm::SITargetLowering::AdjustInstrPostInstrSelection(), llvm::ARMTargetLowering::AdjustInstrPostInstrSelection(), llvm::HexagonSubtarget::adjustSchedDependency(), llvm::AMDGPUInstructionSelector::AMDGPUInstructionSelector(), llvm::analyzeArguments(), llvm::XCoreInstrInfo::analyzeBranch(), llvm::NVPTXInstrInfo::analyzeBranch(), llvm::SparcInstrInfo::analyzeBranch(), llvm::MipsInstrInfo::analyzeBranch(), llvm::HexagonInstrInfo::analyzeBranch(), llvm::R600InstrInfo::analyzeBranch(), llvm::AArch64InstrInfo::analyzeBranch(), llvm::PPCInstrInfo::analyzeBranch(), llvm::X86InstrInfo::analyzeBranchPredicate(), llvm::LanaiInstrInfo::analyzeCompare(), llvm::AArch64InstrInfo::analyzeCompare(), llvm::SystemZInstrInfo::analyzeCompare(), llvm::HexagonInstrInfo::analyzeCompare(), llvm::ARMBaseInstrInfo::analyzeCompare(), llvm::PPCInstrInfo::analyzeCompare(), llvm::X86InstrInfo::analyzeCompare(), llvm::LanaiInstrInfo::analyzeSelect(), llvm::ARMBaseInstrInfo::analyzeSelect(), llvm::LiveRangeEdit::anyRematerializable(), llvm::HexagonSubtarget::CallMutation::apply(), llvm::RegisterBankInfo::applyDefaultMapping(), areCandidatesToMergeOrPair(), areCombinableOperations(), llvm::HexagonInstrInfo::areMemAccessesTriviallyDisjoint(), llvm::HexagonFrameLowering::assignCalleeSavedSpillSlots(), AssignProtectedObjSet(), attachMEMCPYScratchRegs(), BBHasFallthrough(), BBIsJumpedOver(), llvm::biasPhysRegCopy(), llvm::CriticalAntiDepBreaker::BreakAntiDependencies(), llvm::ARMBaseInstrInfo::breakPartialRegDependency(), llvm::X86InstrInfo::breakPartialRegDependency(), llvm::SIInstrInfo::buildExtractSubRegOrImm(), BuildInstOrderMap(), llvm::ScheduleDAGInstrs::buildSchedGraph(), llvm::R600InstrInfo::buildSlotOfVectorInstruction(), calculateSetFPREG(), llvm::EHStreamer::callToNoUnwindFunction(), canBeExpandedToORR(), canCombine(), canCompareBeNewValueJump(), canDefBePartOfLOH(), llvm::HexagonInstrInfo::canExecuteInBundle(), canFoldCopy(), canFoldIntoCSel(), canFoldIntoMOVCC(), canFoldIntoSelect(), llvm::X86InstrInfo::canMakeTailCallConditional(), llvm::HexagonPacketizerList::canPromoteToDotCur(), llvm::HexagonPacketizerList::canPromoteToNewValueStore(), canTurnIntoCOPY(), changeFCMPPredToAArch64CC(), checkRegOnlyPHIInputs(), llvm::X86InstrInfo::classifyLEAReg(), llvm::HexagonPacketizerList::cleanUpDotCur(), clearKillFlags(), clobbersCTR(), collectDebugValues(), CombineCVTAToLocal(), llvm::WebAssemblyInstrInfo::commuteInstructionImpl(), llvm::ARMBaseInstrInfo::commuteInstructionImpl(), llvm::SIInstrInfo::commuteInstructionImpl(), llvm::TargetInstrInfo::commuteInstructionImpl(), llvm::PPCInstrInfo::commuteInstructionImpl(), llvm::X86InstrInfo::commuteInstructionImpl(), commuteVPTERNLOG(), CompareMBBNumbers(), llvm::HexagonEvaluator::composeWithSubRegIndex(), computeBranchTargetAndInversion(), computeExprForSpill(), llvm::TargetSchedModel::computeOperandLatency(), llvm::TargetSchedModel::computeOutputLatency(), llvm::InstructionSelector::constrainOperandRegToRegClass(), llvm::constrainSelectedInstRegOperands(), conversionLibcall(), ConvertImplicitDefToConstZero(), llvm::PPCInstrInfo::convertToImmediateForm(), llvm::ARMBaseInstrInfo::convertToThreeAddress(), llvm::SystemZInstrInfo::convertToThreeAddress(), llvm::X86InstrInfo::convertToThreeAddress(), llvm::SIInstrInfo::convertToThreeAddress(), copyExtraImplicitOps(), copyHint(), copyImplicitOps(), llvm::R600InstrInfo::copyPhysReg(), countersNonZero(), countOperands(), llvm::createBreakFalseDeps(), llvm::createCopyConstrainDAGMutation(), llvm::LiveRangeCalc::createDeadDefs(), llvm::SSAUpdaterTraits< MachineSSAUpdater >::CreateEmptyPHI(), llvm::createHexagonHardwareLoops(), createPHIsForCMOVsInSinkBB(), llvm::createR600ExpandSpecialInstrsPass(), llvm::createSILowerI1CopiesPass(), llvm::createSIWholeQuadModePass(), llvm::createX86FixupBWInsts(), llvm::createX86FixupLEAs(), llvm::createX86FixupSetCC(), llvm::createX86OptimizeLEAs(), llvm::createXCoreFrameToArgsOffsetEliminationPass(), CriticalPathStep(), definesFullReg(), llvm::ARMBaseInstrInfo::DefinesPredicate(), llvm::HexagonInstrInfo::DefinesPredicate(), llvm::PPCInstrInfo::DefinesPredicate(), llvm::ARMFrameLowering::determineCalleeSaves(), llvm::HexagonFrameLowering::determineCalleeSaves(), doCandidateWalk(), dumpMachineInstrRangeWithSlotIndex(), llvm::SparcFrameLowering::eliminateCallFramePseudoInstr(), llvm::MSP430FrameLowering::eliminateCallFramePseudoInstr(), llvm::AVRFrameLowering::eliminateCallFramePseudoInstr(), llvm::XCoreFrameLowering::eliminateCallFramePseudoInstr(), llvm::ARCFrameLowering::eliminateCallFramePseudoInstr(), llvm::BPFRegisterInfo::eliminateFrameIndex(), llvm::MSP430RegisterInfo::eliminateFrameIndex(), llvm::RISCVRegisterInfo::eliminateFrameIndex(), llvm::WebAssemblyRegisterInfo::eliminateFrameIndex(), llvm::LanaiRegisterInfo::eliminateFrameIndex(), llvm::SparcRegisterInfo::eliminateFrameIndex(), llvm::AVRRegisterInfo::eliminateFrameIndex(), llvm::NVPTXRegisterInfo::eliminateFrameIndex(), llvm::ARCRegisterInfo::eliminateFrameIndex(), llvm::HexagonRegisterInfo::eliminateFrameIndex(), llvm::XCoreRegisterInfo::eliminateFrameIndex(), llvm::ThumbRegisterInfo::eliminateFrameIndex(), llvm::MipsRegisterInfo::eliminateFrameIndex(), llvm::AArch64RegisterInfo::eliminateFrameIndex(), llvm::PPCRegisterInfo::eliminateFrameIndex(), llvm::X86RegisterInfo::eliminateFrameIndex(), llvm::ARMBaseRegisterInfo::eliminateFrameIndex(), llvm::PPCTargetLowering::EmitAtomicBinary(), emitBuildPairF64Pseudo(), llvm::AsmPrinter::emitCFIInstruction(), emitClzero(), emitDebugValueComment(), llvm::SparcTargetLowering::emitEHSjLjLongJmp(), llvm::PPCTargetLowering::emitEHSjLjLongJmp(), llvm::SparcTargetLowering::emitEHSjLjSetJmp(), llvm::PPCTargetLowering::emitEHSjLjSetJmp(), llvm::AVRFrameLowering::emitEpilogue(), llvm::MSP430FrameLowering::emitEpilogue(), emitError(), llvm::AArch64TargetLowering::EmitF128CSEL(), llvm::AsmPrinter::emitFrameAlloc(), EmitGCCInlineAsmStr(), EmitHiLo(), llvm::AsmPrinter::emitImplicitDef(), emitIncrement(), emitIndirectDst(), emitIndirectSrc(), llvm::SystemZAsmPrinter::EmitInstruction(), llvm::WebAssemblyAsmPrinter::EmitInstruction(), llvm::ARMAsmPrinter::EmitInstruction(), llvm::X86AsmPrinter::EmitInstruction(), llvm::MipsAsmPrinter::EmitInstruction(), llvm::AMDGPUAsmPrinter::EmitInstruction(), llvm::R600TargetLowering::EmitInstrWithCustomInserter(), llvm::RISCVTargetLowering::EmitInstrWithCustomInserter(), llvm::BPFTargetLowering::EmitInstrWithCustomInserter(), llvm::AVRTargetLowering::EmitInstrWithCustomInserter(), llvm::XCoreTargetLowering::EmitInstrWithCustomInserter(), llvm::MSP430TargetLowering::EmitInstrWithCustomInserter(), llvm::SITargetLowering::EmitInstrWithCustomInserter(), llvm::ARMTargetLowering::EmitInstrWithCustomInserter(), llvm::MipsTargetLowering::EmitInstrWithCustomInserter(), llvm::PPCTargetLowering::EmitInstrWithCustomInserter(), llvm::X86TargetLowering::EmitInstrWithCustomInserter(), llvm::ARMAsmPrinter::EmitJumpTableAddrs(), llvm::ARMAsmPrinter::EmitJumpTableInsts(), llvm::ARMAsmPrinter::EmitJumpTableTBInst(), emitKill(), emitLoadM0FromVGPRLoop(), emitMonitor(), EmitMSInlineAsmStr(), EmitNop(), EmitNops(), llvm::PPCTargetLowering::EmitPartwordAtomicBinary(), llvm::TargetLoweringBase::emitPatchPoint(), emitPCMPSTRI(), emitPCMPSTRM(), emitPostSt(), llvm::AVRFrameLowering::emitPrologue(), llvm::MSP430FrameLowering::emitPrologue(), emitRDPKRU(), llvm::MSP430TargetLowering::EmitShiftInstr(), emitSplitF64Pseudo(), llvm::X86FrameLowering::emitSPUpdate(), emitWRPKRU(), emitXBegin(), llvm::TargetLoweringBase::emitXRayCustomEvent(), llvm::TargetLoweringBase::emitXRayTypedEvent(), llvm::WinException::endFunclet(), eraseGPOpnd(), eraseIfDead(), llvm::LiveRangeEdit::eraseVirtReg(), llvm::HexagonEvaluator::evaluate(), llvm::BitTracker::MachineEvaluator::evaluate(), Expand2AddrUndef(), expandLoadStackGuard(), expandMOV32r1(), ExpandMOVImmSExti8(), expandNOVLXLoad(), expandNOVLXStore(), llvm::SIInstrInfo::expandPostRAPseudo(), llvm::R600InstrInfo::expandPostRAPseudo(), llvm::HexagonInstrInfo::expandPostRAPseudo(), llvm::ARMBaseInstrInfo::expandPostRAPseudo(), llvm::AArch64InstrInfo::expandPostRAPseudo(), llvm::SystemZInstrInfo::expandPostRAPseudo(), llvm::PPCInstrInfo::expandPostRAPseudo(), llvm::SparcTargetLowering::expandSelectCC(), llvm::PPCInstrInfo::expandVSXMemPseudo(), llvm::CallLowering::ValueHandler::extendRegister(), llvm::DbgVariableLocation::extractFromMachineInstruction(), llvm::LegalizerHelper::fewerElementsVector(), llvm::MipsInstrInfo::findCommutedOpIndices(), llvm::X86InstrInfo::findCommutedOpIndices(), llvm::TargetInstrInfo::findCommutedOpIndices(), findCondCodeUsedByInstr(), findCorrespondingPred(), findDefIdx(), llvm::X86InstrInfo::findFMA3CommutedOpIndices(), findIncDecAfter(), findInlineAsmFlagIdx(), findRegisterDefOperand(), findRegisterDefOperandIdx(), findRegisterUseOperand(), findRegisterUseOperandIdx(), findSingleRegDef(), FindStartOfTree(), findTiedOperandIdx(), findUseIdx(), finishConvertToThreeAddress(), llvm::fixStackStores(), fixupCalleeSaveRestoreStackOffset(), llvm::foldFrameOffset(), llvm::SystemZInstrInfo::FoldImmediate(), llvm::PPCInstrInfo::FoldImmediate(), llvm::SIInstrInfo::FoldImmediate(), llvm::ARMBaseInstrInfo::FoldImmediate(), foldImmediates(), llvm::TargetInstrInfo::foldMemoryOperand(), llvm::AArch64InstrInfo::foldMemoryOperandImpl(), llvm::SystemZInstrInfo::foldMemoryOperandImpl(), llvm::X86InstrInfo::foldMemoryOperandImpl(), foldPatchpoint(), foldVGPRCopyIntoRegSequence(), forceReg(), FuseInst(), FuseTwoAddrInst(), llvm::AArch64InstrInfo::genAlternativeCodeSequence(), llvm::TargetInstrInfo::genAlternativeCodeSequence(), genFusedMultiply(), genMaddR(), getAbsSetOperand(), llvm::getAddressFromInstr(), getAdjustedCmp(), llvm::HexagonFrameLowering::getAlignaInstr(), llvm::RegBankSelect::getAnalysisUsage(), llvm::HexagonInstrInfo::getBaseAndOffset(), llvm::HexagonInstrInfo::getBaseAndOffsetPosition(), getBaseOperand(), llvm::RISCVInstrInfo::getBranchDestBlock(), llvm::AVRInstrInfo::getBranchDestBlock(), llvm::AArch64InstrInfo::getBranchDestBlock(), llvm::SIInstrInfo::getBranchDestBlock(), llvm::SystemZInstrInfo::getBranchInfo(), llvm::HexagonInstrInfo::getBundleNoShuf(), getCallTargetRegOpnd(), getCmpForPseudo(), getComparePred(), getCompareSourceReg(), llvm::HexagonInstrInfo::getCompoundCandidateGroup(), llvm::HexagonInstrInfo::getCompoundOpcode(), llvm::getConstantFPVRegVal(), llvm::getConstantVRegVal(), getCopyRegClasses(), getDebugExpression(), getDebugLocValue(), getDebugVariable(), getDispOperand(), llvm::HexagonInstrInfo::getDotNewPredJumpOp(), GetDSubRegs(), llvm::HexagonInstrInfo::getDuplexCandidateGroup(), llvm::X86InstrInfo::getExecutionDomainCustom(), llvm::TargetInstrInfo::getExtractSubregInputs(), llvm::ARMBaseInstrInfo::getExtractSubregLikeInputs(), llvm::R600InstrInfo::getFlagOp(), getFMAPatterns(), getFPReg(), llvm::X86InstrInfo::getFrameAdjustment(), llvm::ARMBaseRegisterInfo::getFrameIndexInstrOffset(), getFrameIndexOperandNum(), llvm::MSP430InstrInfo::getFramePoppedByCallee(), llvm::ARMBaseInstrInfo::getFramePred(), llvm::TargetInstrInfo::getFrameSize(), llvm::TargetInstrInfo::getFrameTotalSize(), llvm::SystemZInstrInfo::getFusedCompare(), llvm::HexagonHazardRecognizer::getHazardType(), llvm::StackMapOpers::getID(), GetImm(), getImmOrMaterializedImm(), llvm::SSAUpdaterTraits< MachineSSAUpdater >::PHI_iterator::getIncomingBlock(), llvm::SSAUpdaterTraits< MachineSSAUpdater >::PHI_iterator::getIncomingValue(), llvm::HexagonInstrInfo::getIncrementValue(), getInitPhiReg(), getInlineAsmDialect(), llvm::TargetInstrInfo::getInsertSubregInputs(), llvm::ARMBaseInstrInfo::getInsertSubregLikeInputs(), llvm::AMDGPURegisterBankInfo::getInstrAlternativeMappings(), llvm::X86RegisterBankInfo::getInstrAlternativeMappings(), llvm::AArch64RegisterBankInfo::getInstrAlternativeMappings(), llvm::PPCInstrInfo::getInstrLatency(), llvm::ARMRegisterBankInfo::getInstrMapping(), llvm::AMDGPURegisterBankInfo::getInstrMapping(), llvm::X86RegisterBankInfo::getInstrMapping(), llvm::AArch64RegisterBankInfo::getInstrMapping(), llvm::RegisterBankInfo::getInstrMappingImpl(), llvm::getInstrPredicate(), getInstrVecReg(), llvm::AArch64InstrInfo::getInstSizeInBytes(), llvm::RISCVInstrInfo::getInstSizeInBytes(), llvm::ARCInstrInfo::getInstSizeInBytes(), llvm::MSP430InstrInfo::getInstSizeInBytes(), llvm::AVRInstrInfo::getInstSizeInBytes(), llvm::MipsInstrInfo::getInstSizeInBytes(), llvm::ARMBaseInstrInfo::getInstSizeInBytes(), llvm::SystemZInstrInfo::getInstSizeInBytes(), llvm::PPCInstrInfo::getInstSizeInBytes(), llvm::SIInstrInfo::getInstSizeInBytes(), getLdStBaseOp(), llvm::NVPTXInstrInfo::getLdStCodeAddrSpace(), getLdStOffsetOp(), getLdStRegOp(), getLeaOP(), getLoadInfo(), getLoadStoreBaseOp(), getLoadStoreOffsetAlign(), getLoadStoreRegOp(), getLoopPhiReg(), getMaddPatterns(), getMappedOp(), llvm::X86InstrInfo::getMemOpBaseRegImmOfs(), llvm::AArch64InstrInfo::getMemOpBaseRegImmOfsOffsetOperand(), llvm::LanaiInstrInfo::getMemOpBaseRegImmOfsWidth(), llvm::AArch64InstrInfo::getMemOpBaseRegImmOfsWidth(), llvm::MipsInstrInfo::GetMemOperand(), getMemOpKey(), getMemoryOpOffset(), llvm::SIRegisterInfo::getMUBUFInstrOffset(), llvm::SIInstrInfo::getNamedImmOperand(), llvm::SIInstrInfo::getNamedOperand(), getNewSource(), getNewValueJumpOpcode(), llvm::PatchPointOpers::getNextScratchIdx(), llvm::rdf::DataFlowGraph::getNextShadow(), llvm::PatchPointOpers::getNumCallArgs(), getNumExplicitOperands(), getNumMicroOpsSwiftLdSt(), llvm::StackMapOpers::getNumPatchBytes(), llvm::SIInstrInfo::getNumWaitStates(), getOModValue(), llvm::getOpcodeDef(), llvm::PPCInstrInfo::getOperandLatency(), llvm::ARMBaseInstrInfo::getOperandLatency(), llvm::HexagonInstrInfo::getOperandLatency(), llvm::MachineRegisterInfo::defusechain_iterator< ReturnUses, ReturnDefs, SkipDebug, ByOperand, ByInstr, ByBundle >::getOperandNo(), llvm::SIInstrInfo::getOpRegClass(), llvm::X86GenRegisterBankInfo::getPartialMappingIdx(), llvm::ARMBaseInstrInfo::getPartialRegUpdateClearance(), llvm::X86InstrInfo::getPartialRegUpdateClearance(), getPHIDeps(), getPHIDestReg(), getPHIPred(), getPhiRegs(), getPHISourceReg(), getPHISrcRegOpIdx(), llvm::SSAUpdaterTraits< MachineSSAUpdater >::GetPHIValue(), getPostIncrementOperand(), getPostIndexedLoadStoreOpcode(), llvm::ARMBaseInstrInfo::getPredicate(), getReassignedChan(), getRegClassConstraint(), getRegClassConstraintEffect(), getRegClassConstraintEffectForVReg(), getRegClassFromGRPhysReg(), llvm::MachineIRBuilderBase::getRegFromArg(), llvm::TargetInstrInfo::getRegSequenceInputs(), llvm::ARMBaseInstrInfo::getRegSequenceLikeInputs(), getRegsUsedByPHIs(), getRetOpcode(), getRetpolineSymbol(), getShuffleComment(), getSingleDef(), llvm::HexagonInstrInfo::getSize(), getSmrdOpcode(), llvm::X86InstrInfo::getSPAdjust(), getSrcFromCopy(), llvm::R600InstrInfo::getSrcs(), getStartOrEndSlot(), getStoreOffset(), getStoreTarget(), getStoreValueOperand(), getSubOpcode(), getTag(), getTargetMBB(), getTruncatedShiftCount(), getTypeFromTypeIdx(), getTypeToPrint(), getUnconditionalBrDisp(), llvm::X86InstrInfo::getUndefRegClearance(), llvm::SSAUpdaterTraits< MachineSSAUpdater >::GetUndefVal(), getUnderlyingObjects(), llvm::MachineSSAUpdater::GetValueInMiddleOfBlock(), llvm::SIInstrInfo::getVALUOp(), getWinAllocaAmount(), llvm::MipsTargetLowering::HandleByVal(), handleMiddleInst(), handleUse(), llvm::LiveVariables::HandleVirtRegDef(), HandleVRSaveUpdate(), hasComplexRegisterTies(), llvm::AArch64InstrInfo::hasExtendedReg(), HashMachineInstr(), llvm::X86InstrInfo::hasLiveCondCodeDef(), hasOneNonDBGUseInst(), hasRAWHazard(), llvm::X86InstrInfo::hasReassociableOperands(), llvm::TargetInstrInfo::hasReassociableOperands(), llvm::TargetInstrInfo::hasReassociableSibling(), hasRegisterDependency(), hasRegisterImplicitUseOperand(), llvm::AArch64InstrInfo::hasShiftedReg(), hasUnmodeledSideEffects(), hasUseAfterLoop(), hasVGPROperands(), llvm::HexagonLowerToMC(), hoistAndMergeSGPRInits(), llvm::NVPTXAsmPrinter::ignoreLoc(), llvm::HexagonInstrInfo::immediateExtend(), ImmInRange(), INITIALIZE_PASS(), llvm::HexagonInstrInfo::insertBranch(), llvm::R600InstrInfo::insertBranch(), llvm::SIInstrInfo::insertBranch(), insertCopy(), insertDivByZeroTrap(), InsertFPConstInst(), InsertFPImmInst(), InsertLDR_STR(), insertPHI(), llvm::SIInstrInfo::insertSelect(), InsertSPConstInst(), InsertSPImmInst(), llvm::rdf::CopyPropagation::interpretAsCopy(), llvm::Mips16RegisterInfo::intRegClass(), llvm::HexagonInstrInfo::invertAndChangeJumpTarget(), llvm::isAArch64FrameOffsetLegal(), llvm::ARMBaseInstrInfo::isAddrMode3OpImm(), llvm::ARMBaseInstrInfo::isAddrMode3OpMinusReg(), llvm::ARMBaseInstrInfo::isAm2ScaledReg(), llvm::AArch64InstrInfo::isAsCheapAsAMove(), llvm::InstructionSelector::isBaseWithConstantOffset(), isCandidateLoad(), isCandidateStore(), llvm::AArch64InstrInfo::isCandidateToMergeOrPair(), llvm::WebAssembly::isChild(), llvm::rdf::TargetOperandInfo::isClobbering(), llvm::CoalescerPair::isCoalescable(), llvm::AArch64InstrInfo::isCoalescableExtInstr(), llvm::PPCInstrInfo::isCoalescableExtInstr(), llvm::X86InstrInfo::isCoalescableExtInstr(), isCompareZero(), isConstant(), isConstantValuePHI(), llvm::HexagonInstrInfo::isConstExtended(), isConvergent(), isCopy(), isCopyFeedingInvariantStore(), isCopyToExec(), isCopyToReg(), isCrossCopy(), isCSRestore(), isCVTAToLocalCombinationCandidate(), isDbgValueDescribedByReg(), isDebug(), isDefInSubRange(), isDescribedByReg(), llvm::AArch64InstrInfo::isExynosResetFast(), llvm::AArch64InstrInfo::isExynosShiftLeftFast(), llvm::AArch64InstrInfo::isFalkorShiftExtFast(), llvm::rdf::TargetOperandInfo::isFixedReg(), isFpMulInstruction(), llvm::AArch64InstrInfo::isFPRCopy(), llvm::PPCRegisterInfo::isFrameOffsetLegal(), llvm::ARMBaseRegisterInfo::isFrameOffsetLegal(), isFullCopy(), isFullCopyOf(), isFullExecCopy(), isFullUndefDef(), llvm::AArch64InstrInfo::isGPRCopy(), llvm::AArch64InstrInfo::isGPRZero(), isGreaterThanNBitTFRI(), isIdenticalTo(), isIdentityCopy(), isImmValidForOpcode(), isImplicitlyDef(), isIncrementOrDecrement(), isIndirectDebugValue(), llvm::SIInstrInfo::isInlineConstant(), isInstrUniform(), llvm::ARMBaseInstrInfo::isLDMBaseRegInList(), llvm::ARMBaseInstrInfo::isLdstScaledReg(), llvm::ARMBaseInstrInfo::isLdstScaledRegNotPlusLsl2(), llvm::ARMBaseInstrInfo::isLdstSoMinusReg(), llvm::isLeaMem(), isLEASimpleIncOrDec(), llvm::HexagonPacketizerList::isLegalToPacketizeTogether(), llvm::SIInstrInfo::isLiteralConstant(), isLiveOut(), isLoadAndTestAsCmp(), llvm::MipsSEInstrInfo::isLoadFromStackSlot(), llvm::ARCInstrInfo::isLoadFromStackSlot(), llvm::XCoreInstrInfo::isLoadFromStackSlot(), llvm::LanaiInstrInfo::isLoadFromStackSlot(), llvm::SparcInstrInfo::isLoadFromStackSlot(), llvm::HexagonInstrInfo::isLoadFromStackSlot(), llvm::AArch64InstrInfo::isLoadFromStackSlot(), llvm::AVRInstrInfo::isLoadFromStackSlot(), llvm::ARMBaseInstrInfo::isLoadFromStackSlot(), llvm::PPCInstrInfo::isLoadFromStackSlot(), llvm::X86InstrInfo::isLoadFromStackSlot(), isLocalCopy(), isLogicalOpOnExec(), llvm::isMem(), isMemoryOp(), isMergeableLdStUpdate(), llvm::NVPTXInstrInfo::isMoveInstr(), isNonFoldablePartialRegisterLoad(), isOperandKill(), llvm::SIInstrInfo::isOperandLegal(), isOperandSubregIdx(), isPhysicalRegCopy(), llvm::R600InstrInfo::isPredicable(), llvm::ARMBaseInstrInfo::isPredicated(), llvm::R600InstrInfo::isPredicated(), isPreISelGenericFloatingPointOpcode(), llvm::X86InstrInfo::isReallyTriviallyReMaterializable(), isRedundantFlagInstr(), isRegTiedToDefOperand(), isRegTiedToUseOperand(), isRelevantAddressingMode(), isRematerializable(), IsSafeAndProfitableToMove(), isSafeToFoldImmIntoCopy(), llvm::AArch64InstrInfo::isScaledAddr(), isSecondInstructionInSequence(), isSExtLoad(), isShift(), isSignExtendingOp(), llvm::PPCInstrInfo::isSignOrZeroExtended(), isSimpleBD12Move(), isSimpleIf(), isSimpleIndexCalc(), isSimpleMove(), isSourceDefinedByImplicitDef(), isStackAligningInlineAsm(), llvm::SystemZInstrInfo::isStackSlotCopy(), llvm::MipsSEInstrInfo::isStoreToStackSlot(), llvm::LanaiInstrInfo::isStoreToStackSlot(), llvm::ARCInstrInfo::isStoreToStackSlot(), llvm::XCoreInstrInfo::isStoreToStackSlot(), llvm::AArch64InstrInfo::isStoreToStackSlot(), llvm::SparcInstrInfo::isStoreToStackSlot(), llvm::HexagonInstrInfo::isStoreToStackSlot(), llvm::AVRInstrInfo::isStoreToStackSlot(), llvm::ARMBaseInstrInfo::isStoreToStackSlot(), llvm::PPCInstrInfo::isStoreToStackSlot(), llvm::X86InstrInfo::isStoreToStackSlot(), isSuitableForMask(), llvm::ARMBaseInstrInfo::isSwiftFastImmShift(), llvm::HexagonInstrInfo::isToBeScheduledASAP(), llvm::PPCInstrInfo::isTOCSaveMI(), isTransformable(), isTwoAddrUse(), IsUnconditionalJump(), isUseSafeToFold(), llvm::SIInstrInfo::isVGPRCopy(), isVirtualRegisterOperand(), isZeroExtendingOp(), llvm::AArch64LegalizerInfo::legalizeCustom(), llvm::ARMLegalizerInfo::legalizeCustom(), llvm::SIInstrInfo::legalizeOperands(), llvm::SIInstrInfo::legalizeOperandsVOP2(), llvm::SIInstrInfo::legalizeOperandsVOP3(), llvm::SIInstrInfo::legalizeOpWithMove(), llvm::LegalizerHelper::libcall(), loadM0FromVGPR(), llvm::TargetRegisterInfo::lookThruCopyLike(), lookupCandidateBaseReg(), llvm::XCoreMCInstLower::Lower(), llvm::SystemZMCInstLower::lower(), llvm::MSP430MCInstLower::Lower(), llvm::ARCMCInstLower::Lower(), llvm::LanaiMCInstLower::Lower(), llvm::BPFMCInstLower::Lower(), llvm::MipsMCInstLower::Lower(), llvm::AMDGPUMCInstLower::lower(), llvm::WebAssemblyMCInstLower::Lower(), llvm::LegalizerHelper::lower(), llvm::X86CallLowering::lowerCall(), llvm::AArch64CallLowering::lowerCall(), llvm::PPCRegisterInfo::lowerCRBitRestore(), llvm::PPCRegisterInfo::lowerCRBitSpilling(), llvm::PPCRegisterInfo::lowerCRRestore(), llvm::PPCRegisterInfo::lowerCRSpilling(), llvm::PPCRegisterInfo::lowerDynamicAlloc(), llvm::PPCRegisterInfo::lowerDynamicAreaOffset(), LowerFPToInt(), llvm::LowerNios2MachineInstToMCInst(), llvm::MipsMCInstLower::LowerOperand(), llvm::LowerPPCMachineInstrToMCInst(), lowerRIEfLow(), lowerRIHigh(), lowerRILow(), llvm::LowerSparcMachineInstrToMCInst(), lowerSubvectorLoad(), lowerSubvectorStore(), lowerVECTOR_SHUFFLE_VSHF(), llvm::PPCRegisterInfo::lowerVRSAVERestore(), llvm::PPCRegisterInfo::lowerVRSAVESpilling(), makeImplicit(), MakeM0Inst(), llvm::MachineRegisterInfo::markUsesInDebugValueAsUndef(), llvm::MIPatternMatch::BinaryOp_match< LHS_P, RHS_P, Opcode, Commutable >::match(), llvm::MIPatternMatch::UnaryOp_match< SrcTy, Opcode >::match(), MatchingStackOffset(), matchPair(), MaybeRewriteToFallthrough(), mayLoad(), mayStore(), llvm::DebugLocEntry::MergeValues(), Mips16WhichOp8uOr16simm(), MoveAndTeeForMultiUse(), MoveForSingleUse(), llvm::SIInstrInfo::moveToVALU(), multipleIterations(), llvm::LegalizerHelper::narrowScalar(), llvm::AArch64RegisterInfo::needsFrameBaseReg(), llvm::PPCRegisterInfo::needsFrameBaseReg(), llvm::ARMBaseRegisterInfo::needsFrameBaseReg(), llvm::AggressiveAntiDepBreaker::Observe(), OneUseDominatesOtherUses(), opcodeEmitsNoInsts(), false::IntervalSorter::operator()(), optimizeCall(), llvm::LanaiInstrInfo::optimizeCompareInstr(), llvm::AArch64InstrInfo::optimizeCompareInstr(), llvm::ARMBaseInstrInfo::optimizeCompareInstr(), llvm::PPCInstrInfo::optimizeCompareInstr(), llvm::X86InstrInfo::optimizeCompareInstr(), llvm::AArch64InstrInfo::optimizeCondBranch(), llvm::X86InstrInfo::optimizeLoadInstr(), llvm::LanaiInstrInfo::optimizeSelect(), llvm::ARMBaseInstrInfo::optimizeSelect(), parseCond(), parseCondBranch(), parseOperands(), llvm::PatchPointOpers::PatchPointOpers(), performCustomAdjustments(), phiHasBreakDef(), phiHasVGPROperands(), populateCandidates(), llvm::ARMBaseInstrInfo::PredicateInstruction(), llvm::R600InstrInfo::PredicateInstruction(), llvm::SystemZInstrInfo::PredicateInstruction(), llvm::HexagonInstrInfo::PredicateInstruction(), llvm::PPCInstrInfo::PredicateInstruction(), llvm::TargetInstrInfo::PredicateInstruction(), preservesValueOf(), llvm::MIPrinter::print(), print(), llvm::SystemZAsmPrinter::PrintAsmMemoryOperand(), llvm::AVRAsmPrinter::PrintAsmMemoryOperand(), llvm::HexagonAsmPrinter::PrintAsmMemoryOperand(), llvm::ARMAsmPrinter::PrintAsmMemoryOperand(), llvm::MipsAsmPrinter::PrintAsmMemoryOperand(), llvm::SystemZAsmPrinter::PrintAsmOperand(), llvm::AVRAsmPrinter::PrintAsmOperand(), llvm::HexagonAsmPrinter::PrintAsmOperand(), llvm::WebAssemblyAsmPrinter::PrintAsmOperand(), llvm::ARMAsmPrinter::PrintAsmOperand(), llvm::X86AsmPrinter::PrintAsmOperand(), llvm::MipsAsmPrinter::PrintAsmOperand(), llvm::AMDGPUAsmPrinter::PrintAsmOperand(), llvm::AsmPrinter::PrintAsmOperand(), printConstant(), printExtendedName(), llvm::MipsAsmPrinter::printFCCOperand(), printIntelMemReference(), printLeaMemReference(), printMemReference(), llvm::AVRAsmPrinter::printOperand(), llvm::HexagonAsmPrinter::printOperand(), llvm::ARMAsmPrinter::printOperand(), llvm::MipsAsmPrinter::printOperand(), printOperand(), printPCRelImm(), llvm::ARMBaseInstrInfo::produceSameValue(), profitImm(), pushDepHeight(), QueryCallee(), readsVCCZ(), readsWritesVirtualRegister(), llvm::TargetInstrInfo::reassociateOps(), llvm::MachineRegisterInfo::recomputeRegClass(), llvm::StackMaps::recordStackMap(), llvm::HexagonInstrInfo::reduceLoopCount(), registerDefinedBetween(), regOverlapsSet(), llvm::R600SchedStrategy::releaseBottomNode(), llvm::ARMBaseInstrInfo::reMaterialize(), llvm::X86InstrInfo::reMaterialize(), llvm::TargetInstrInfo::reMaterialize(), removeCopies(), RemoveDeadAddBetweenLEAAndJT(), removeIPMBasedCompare(), removeKillInfo(), removePhis(), llvm::LiveVariables::removeVirtualRegisterDead(), llvm::LiveVariables::removeVirtualRegisterKilled(), llvm::LiveVariables::removeVirtualRegistersKilled(), llvm::RegBankSelect::RepairingPlacement::RepairingPlacement(), llvm::X86InstrInfo::replaceBranchWithTailCall(), ReplaceDominatedUses(), replaceFI(), ReplaceFrameIndex(), llvm::PPCInstrInfo::replaceInstrWithLI(), llvm::ThumbRegisterInfo::resolveFrameIndex(), llvm::AArch64RegisterInfo::resolveFrameIndex(), llvm::PPCRegisterInfo::resolveFrameIndex(), llvm::ARMBaseRegisterInfo::resolveFrameIndex(), llvm::X86FrameLowering::restoreWin32EHStackPointers(), resultTests(), llvm::rewriteAArch64FrameIndex(), llvm::rewriteARMFrameIndex(), llvm::ThumbRegisterInfo::rewriteFrameIndex(), RewriteP2Align(), llvm::rewriteT2FrameIndex(), runOnBasicBlock(), llvm::InstructionSelect::runOnMachineFunction(), llvm::DetectRoundChange::runOnMachineFunction(), llvm::Localizer::runOnMachineFunction(), llvm::SelectionDAGISel::runOnMachineFunction(), llvm::MipsAsmPrinter::runOnMachineFunction(), llvm::NVPTXAsmPrinter::runOnMachineFunction(), selectCopy(), selectFP16CopyFromGPR32(), selectMergeValues(), selectUnmergeValues(), llvm::setDirectAddressInInstr(), llvm::ARMBaseInstrInfo::setExecutionDomain(), llvm::X86InstrInfo::setExecutionDomainCustom(), llvm::X86InstrInfo::setFrameAdjustment(), llvm::R600InstrInfo::setImmOperand(), setM0ToIndexFromSGPR(), setPhiPred(), llvm::X86InstrInfo::setSpecialOperandAttr(), llvm::AArch64InstrInfo::shouldClusterMemOps(), llvm::SystemZRegisterInfo::shouldCoalesce(), shrinkScalarCompare(), simpleLibcall(), SinkingPreventsImplicitNullCheck(), smallData(), llvm::X86FrameLowering::spillCalleeSavedRegisters(), splitBlock(), splitMBB(), false::Chain::str(), stripRegisterPrefix(), swapMIOperands(), llvm::SystemZInstrInfo::SystemZInstrInfo(), llvm::TailDuplicator::tailDuplicateAndUpdate(), tieOperands(), tieOpsIfNeeded(), TrackDefUses(), llvm::TargetInstrInfo::trackRegDefsUses(), llvm::MachineBasicBlock::transferSuccessorsAndUpdatePHIs(), tryAddToFoldList(), tryChangeVGPRtoSGPRinCopy(), llvm::LegalizationArtifactCombiner::tryCombineAnyExt(), llvm::CombinerHelper::tryCombineCopy(), llvm::LegalizationArtifactCombiner::tryCombineInstruction(), llvm::LegalizationArtifactCombiner::tryCombineMerges(), llvm::LegalizationArtifactCombiner::tryCombineSExt(), llvm::LegalizationArtifactCombiner::tryCombineZExt(), tryConstantFoldOp(), llvm::LegalizationArtifactCombiner::tryFoldImplicitDef(), tryFoldInst(), llvm::tryFoldSPUpdateIntoPushPop(), tryOptimizeLEAtoMOV(), tryOrrMovk(), trySequenceOfOnes(), tryToreplicateChunks(), llvm::HexagonPacketizerList::undoChangedOffset(), llvm::X86InstrInfo::unfoldMemoryOperand(), unsupportedBinOp(), untieRegOperand(), llvm::AntiDepBreaker::UpdateDbgValue(), llvm::updateDbgValueForSpill(), updateLiveIn(), llvm::HexagonPacketizerList::updateOffset(), updateOperand(), UpdateOperandRegClass(), updatePhysDepsDownwards(), updatePhysDepsUpwards(), llvm::HexagonPacketizerList::useCalleesSP(), llvm::HexagonPacketizerList::useCallersSP(), usedAsAddr(), llvm::HexagonSubtarget::usePredicatedCalls(), UseReg(), validThroughout(), llvm::RegisterBankInfo::InstructionMapping::verify(), llvm::MachineFunction::verify(), verifyInsExtInstruction(), llvm::SIInstrInfo::verifyInstruction(), VerifyLowRegs(), llvm::MachineRegisterInfo::verifyUseList(), VisitGlobalVariableForEmission(), llvm::LegalizerHelper::widenScalar(), llvm::X86CallLowering::X86CallLowering(), and X86SelectAddress().

◆ getOperand() [2/2]

MachineOperand& llvm::MachineInstr::getOperand ( unsigned  i)
inline

Definition at line 302 of file MachineInstr.h.

References assert(), and getNumOperands().

◆ getOperandNo()

unsigned llvm::MachineInstr::getOperandNo ( const_mop_iterator  I) const
inline

◆ getParent() [1/2]

const MachineBasicBlock* llvm::MachineInstr::getParent ( ) const
inline

Definition at line 142 of file MachineInstr.h.

Referenced by addExclusiveRegPair(), llvm::addFrameReference(), addImplicitDefUseOperands(), addLiveInRegs(), addOperand(), addSegmentsWithValNo(), llvm::LiveIntervals::addSegmentToEndOfBlock(), llvm::HexagonPacketizerList::addToPacket(), llvm::SITargetLowering::AdjustInstrPostInstrSelection(), BlockSplitInfo::allInstrsInSameMBB(), llvm::AMDGPUInstructionSelector::AMDGPUInstructionSelector(), areCandidatesToMergeOrPair(), attachMEMCPYScratchRegs(), BBHasFallthrough(), llvm::CodeViewDebug::beginInstruction(), llvm::DwarfDebug::beginInstruction(), branchMaxOffsets(), llvm::ARMBaseInstrInfo::breakPartialRegDependency(), llvm::X86InstrInfo::breakPartialRegDependency(), canCombine(), canInstrSubstituteCmpInstr(), llvm::X86InstrInfo::canMakeTailCallConditional(), cannotCoexistAsymm(), canTurnIntoCOPY(), changeFCMPPredToAArch64CC(), checkEFLAGSLive(), llvm::X86InstrInfo::classifyLEAReg(), collectDebugValues(), CombineCVTAToLocal(), llvm::WebAssemblyInstrInfo::commuteInstructionImpl(), llvm::PPCInstrInfo::commuteInstructionImpl(), llvm::SystemZInstrInfo::commuteInstructionImpl(), llvm::X86InstrInfo::commuteInstructionImpl(), CompareMBBNumbers(), computeBranchTargetAndInversion(), llvm::InstructionSelector::constrainOperandRegToRegClass(), llvm::constrainRegToClass(), llvm::constrainSelectedInstRegOperands(), ContainsReg(), llvm::PPCInstrInfo::convertToImmediateForm(), llvm::ARMBaseInstrInfo::convertToThreeAddress(), llvm::SystemZInstrInfo::convertToThreeAddress(), llvm::X86InstrInfo::convertToThreeAddress(), createBBSelectReg(), llvm::createHexagonHardwareLoops(), llvm::createSIFixWWMLivenessPass(), llvm::createSILowerI1CopiesPass(), llvm::createSIWholeQuadModePass(), llvm::createSystemZLDCleanupPass(), llvm::createX86FixupSetCC(), llvm::createX86GlobalBaseRegPass(), llvm::createX86OptimizeLEAs(), CriticalPathStep(), definesFullReg(), llvm::HexagonFrameLowering::determineCalleeSaves(), doCandidateWalk(), doesModifyCalleeSavedReg(), llvm::MachineDominatorTree::dominates(), llvm::BPFRegisterInfo::eliminateFrameIndex(), llvm::MSP430RegisterInfo::eliminateFrameIndex(), llvm::RISCVRegisterInfo::eliminateFrameIndex(), llvm::WebAssemblyRegisterInfo::eliminateFrameIndex(), llvm::LanaiRegisterInfo::eliminateFrameIndex(), llvm::SparcRegisterInfo::eliminateFrameIndex(), llvm::AVRRegisterInfo::eliminateFrameIndex(), llvm::NVPTXRegisterInfo::eliminateFrameIndex(), llvm::ARCRegisterInfo::eliminateFrameIndex(), llvm::XCoreRegisterInfo::eliminateFrameIndex(), llvm::HexagonRegisterInfo::eliminateFrameIndex(), llvm::ThumbRegisterInfo::eliminateFrameIndex(), llvm::MipsRegisterInfo::eliminateFrameIndex(), llvm::AArch64RegisterInfo::eliminateFrameIndex(), llvm::PPCRegisterInfo::eliminateFrameIndex(), llvm::X86RegisterInfo::eliminateFrameIndex(), llvm::ARMBaseRegisterInfo::eliminateFrameIndex(), llvm::AsmPrinter::emitCFIInstruction(), emitError(), EmitHiLo(), llvm::HexagonAsmPrinter::EmitInstruction(), llvm::HexagonHazardRecognizer::EmitInstruction(), llvm::ARMAsmPrinter::EmitInstruction(), llvm::MipsAsmPrinter::EmitInstruction(), llvm::AMDGPUAsmPrinter::EmitInstruction(), llvm::AVRTargetLowering::EmitInstrWithCustomInserter(), llvm::ARMAsmPrinter::EmitJumpTableTBInst(), EmitNop(), llvm::ScheduleDAGSDNodes::EmitSchedule(), llvm::DbgValueHistoryMap::endInstrRange(), llvm::DebugHandlerBase::endInstruction(), llvm::SplitEditor::enterIntvAfter(), llvm::SplitEditor::enterIntvBefore(), eraseFromBundle(), eraseFromParent(), eraseFromParentAndMarkDBGValuesForRemoval(), eraseGPOpnd(), llvm::BitTracker::MachineEvaluator::evaluate(), expandLoadStackGuard(), expandMOV32r1(), ExpandMOVImmSExti8(), llvm::Nios2InstrInfo::expandPostRAPseudo(), llvm::MipsSEInstrInfo::expandPostRAPseudo(), llvm::Mips16InstrInfo::expandPostRAPseudo(), llvm::SparcInstrInfo::expandPostRAPseudo(), llvm::SIInstrInfo::expandPostRAPseudo(), llvm::R600InstrInfo::expandPostRAPseudo(), llvm::ARMBaseInstrInfo::expandPostRAPseudo(), llvm::HexagonInstrInfo::expandPostRAPseudo(), llvm::AArch64InstrInfo::expandPostRAPseudo(), llvm::PPCInstrInfo::expandPostRAPseudo(), llvm::X86InstrInfo::expandPostRAPseudo(), expandXorFP(), findIncDecAfter(), findOnlyInterestingUse(), findPotentialBlockers(), findSingleRegDef(), findSingleRegUse(), FindSplitPointForStackProtector(), llvm::SIInstrInfo::FoldImmediate(), llvm::ARMBaseInstrInfo::FoldImmediate(), llvm::TargetInstrInfo::foldMemoryOperand(), llvm::AArch64InstrInfo::foldMemoryOperandImpl(), foldVGPRCopyIntoRegSequence(), forceReg(), llvm::RegBankSelect::InstrInsertPoint::frequency(), llvm::AArch64InstrInfo::genAlternativeCodeSequence(), getAdjustedCmp(), llvm::IRTranslator::getAnalysisUsage(), llvm::RegBankSelect::getAnalysisUsage(), getBundledUseMI(), getCmpForPseudo(), getCompareSourceReg(), getConstantFromPool(), llvm::HexagonInstrInfo::getDotNewPredJumpOp(), GetDSubRegs(), getFMAPatterns(), getFoldableImm(), llvm::ARMHazardRecognizer::getHazardType(), llvm::HexagonHazardRecognizer::getHazardType(), getImplicitSPRUseForDPRUse(), llvm::SlotIndexes::getIndexAfter(), llvm::SlotIndexes::getIndexBefore(), llvm::SIInstrInfo::getInstBundleSize(), llvm::AMDGPURegisterBankInfo::getInstrAlternativeMappings(), llvm::X86RegisterBankInfo::getInstrAlternativeMappings(), llvm::AArch64RegisterBankInfo::getInstrAlternativeMappings(), llvm::ARMRegisterBankInfo::getInstrMapping(), llvm::AMDGPURegisterBankInfo::getInstrMapping(), llvm::X86RegisterBankInfo::getInstrMapping(), llvm::AArch64RegisterBankInfo::getInstrMapping(), llvm::MachineTraceMetrics::Trace::getInstrSlack(), llvm::AArch64InstrInfo::getInstSizeInBytes(), llvm::RISCVInstrInfo::getInstSizeInBytes(), llvm::ARCInstrInfo::getInstSizeInBytes(), llvm::MSP430InstrInfo::getInstSizeInBytes(), llvm::AVRInstrInfo::getInstSizeInBytes(), llvm::MipsInstrInfo::getInstSizeInBytes(), llvm::ARMBaseInstrInfo::getInstSizeInBytes(), llvm::SystemZInstrInfo::getInstSizeInBytes(), llvm::PPCInstrInfo::getInstSizeInBytes(), llvm::SIInstrInfo::getInstSizeInBytes(), llvm::getLiveRegsAfter(), getLiveRegsAt(), llvm::getLiveRegsBefore(), getLoadStoreOffsetAlign(), getLoadStoreOffsetSizeInBits(), llvm::PPCInstrInfo::getMachineCombinerPatterns(), getMaddPatterns(), getMappedOp(), getMF(), getMFIfAvailable(), getNewSource(), getNewValueJumpOpcode(), getNonDebugInstr(), llvm::PPCInstrInfo::getOperandLatency(), llvm::ARMBaseInstrInfo::getOperandLatency(), llvm::SIInstrInfo::getOpRegClass(), llvm::AArch64InstrInfo::getOutliningType(), llvm::X86InstrInfo::getOutliningType(), llvm::X86GenRegisterBankInfo::getPartialMappingIdx(), getPostIndexedLoadStoreOpcode(), llvm::ReachingDefAnalysis::getReachingDef(), getRegClassConstraint(), getRegClassFromGRPhysReg(), getSingleDef(), llvm::HexagonInstrInfo::getSize(), getSmrdOpcode(), llvm::X86InstrInfo::getSPAdjust(), llvm::LiveIntervals::getSpillWeight(), getStoreTarget(), getSubOpcode(), GetSymbolRef(), getUnconditionalBrDisp(), getUnderlyingObjects(), llvm::LiveIntervals::handleMove(), llvm::LiveVariables::HandleVirtRegDef(), HandleVRSaveUpdate(), llvm::HexagonInstrInfo::hasLoadFromStackSlot(), llvm::TargetInstrInfo::hasReassociableOperands(), llvm::TargetInstrInfo::hasReassociableSibling(), llvm::HexagonInstrInfo::hasStoreToStackSlot(), hasUseAfterLoop(), hasVGPROperands(), llvm::HexagonAsmPrinter::HexagonProcessInstruction(), hoistAndMergeSGPRInits(), ImmInRange(), INITIALIZE_PASS(), insertCopy(), InsertFPConstInst(), InsertFPImmInst(), llvm::SlotIndexes::insertMachineInstrInMaps(), insertNopBeforeInstruction(), insertPHI(), InsertSPConstInst(), InsertSPImmInst(), InstructionStoresToFI(), llvm::Mips16RegisterInfo::intRegClass(), llvm::AArch64InstrInfo::isAssociativeAndCommutative(), llvm::X86InstrInfo::isAssociativeAndCommutative(), llvm::CoalescerPair::isCoalescable(), isCombineInstrCandidateFP(), isCompareZero(), isConstant(), isCopy(), isCopyFeedingInvariantStore(), isCVTAToLocalCombinationCandidate(), isDebug(), llvm::MachineTraceMetrics::Trace::isDepInTrace(), isDereferenceableInvariantLoad(), isFpMulInstruction(), isFullCopyOf(), isFullUndefDef(), isInstrUniform(), llvm::LiveVariables::VarInfo::isLiveIn(), isNoReturnDef(), llvm::InstructionSelector::isObviouslySafeToFold(), llvm::SIInstrInfo::isOperandLegal(), isPHIRegionIndex(), llvm::ARMBaseInstrInfo::isPredicable(), llvm::R600InstrInfo::isPredicable(), llvm::ARMBaseInstrInfo::isPredicated(), isPreISelGenericFloatingPointOpcode(), isReachable(), llvm::X86InstrInfo::isReallyTriviallyReMaterializable(), llvm::TargetInstrInfo::isReassociationCandidate(), llvm::VLIWResourceModel::isResourceAvailable(), IsSafeToMove(), llvm::PPCInstrInfo::isSignOrZeroExtended(), isSimpleIf(), isSimpleIndexCalc(), llvm::SystemZInstrInfo::isStackSlotCopy(), isTerminalReg(), IsUnconditionalJump(), isUseSafeToFold(), llvm::SIInstrInfo::isVGPRCopy(), jumpTableFollowsTB(), llvm::SplitEditor::leaveIntvAfter(), llvm::SplitEditor::leaveIntvBefore(), llvm::SIInstrInfo::legalizeOperands(), llvm::SIInstrInfo::legalizeOperandsVOP2(), llvm::SIInstrInfo::legalizeOpWithMove(), llvm::AMDGPUMCInstLower::lower(), llvm::WebAssemblyMCInstLower::Lower(), llvm::LowerARMMachineInstrToMCInst(), llvm::PPCRegisterInfo::lowerCRBitRestore(), llvm::PPCRegisterInfo::lowerCRBitSpilling(), llvm::PPCRegisterInfo::lowerCRRestore(), llvm::PPCRegisterInfo::lowerCRSpilling(), llvm::PPCRegisterInfo::lowerDynamicAlloc(), llvm::PPCRegisterInfo::lowerDynamicAreaOffset(), llvm::AMDGPUMCInstLower::lowerOperand(), llvm::PPCRegisterInfo::lowerVRSAVERestore(), llvm::PPCRegisterInfo::lowerVRSAVESpilling(), llvm::MachineOperandIteratorBase::MachineOperandIteratorBase(), matchPair(), memOpsHaveSameBasePtr(), MoveAndTeeForMultiUse(), moveInstrOut(), llvm::SIInstrInfo::moveToVALU(), multipleIterations(), llvm::AArch64RegisterInfo::needsFrameBaseReg(), llvm::PPCRegisterInfo::needsFrameBaseReg(), llvm::ARMBaseRegisterInfo::needsFrameBaseReg(), OneUseDominatesOtherUses(), opcodeEmitsNoInsts(), llvm::LanaiInstrInfo::optimizeCompareInstr(), llvm::AArch64InstrInfo::optimizeCompareInstr(), llvm::ARMBaseInstrInfo::optimizeCompareInstr(), llvm::PPCInstrInfo::optimizeCompareInstr(), llvm::X86InstrInfo::optimizeCompareInstr(), llvm::AArch64InstrInfo::optimizeCondBranch(), llvm::LanaiInstrInfo::optimizeSelect(), llvm::ARMBaseInstrInfo::optimizeSelect(), llvm::SplitEditor::overlapIntv(), packCmovGroup(), populateCandidates(), llvm::ARMBaseInstrInfo::PredicateInstruction(), llvm::R600InstrInfo::PredicateInstruction(), llvm::SystemZInstrInfo::PredicateInstruction(), llvm::HexagonInstrInfo::PredicateInstruction(), llvm::PPCInstrInfo::PredicateInstruction(), llvm::RegisterBankInfo::OperandsMapper::print(), llvm::HexagonAsmPrinter::PrintAsmOperand(), llvm::ARMAsmPrinter::PrintAsmOperand(), printExtendedName(), llvm::printMBBReference(), llvm::ARMAsmPrinter::printOperand(), llvm::ARMBaseInstrInfo::produceSameValue(), llvm::HexagonPacketizerList::producesStall(), profitImm(), llvm::rdf::DataFlowGraph::pushAllDefs(), pushDepHeight(), llvm::SIInstrInfo::readlaneVGPRToSGPR(), readsVCCZ(), registerDefinedBetween(), regOverlapsSet(), removeDeadSegment(), removeExternalCFGEdges(), removeFromBundle(), removeFromParent(), removeIPMBasedCompare(), removePhis(), RemoveVRSaveCode(), llvm::RegBankSelect::RepairingPlacement::RepairingPlacement(), replaceFI(), ReplaceFrameIndex(), llvm::PPCInstrInfo::replaceInstrWithLI(), replaceRegUsesAfterLoop(), llvm::reportGISelFailure(), rescheduleCanonically(), llvm::GCNUpwardRPTracker::reset(), llvm::GCNDownwardRPTracker::reset(), llvm::ThumbRegisterInfo::resolveFrameIndex(), llvm::AArch64RegisterInfo::resolveFrameIndex(), llvm::SIRegisterInfo::resolveFrameIndex(), llvm::PPCRegisterInfo::resolveFrameIndex(), llvm::ARMBaseRegisterInfo::resolveFrameIndex(), llvm::rewriteAArch64FrameIndex(), llvm::ThumbRegisterInfo::rewriteFrameIndex(), llvm::rewriteT2FrameIndex(), llvm::MachineSSAUpdater::RewriteUse(), llvm::SelectionDAGISel::runOnMachineFunction(), selectCopy(), selectFP16CopyFromGPR32(), llvm::ARMBaseInstrInfo::setExecutionDomain(), llvm::MachineIRBuilderBase::setInstr(), setM0ToIndexFromSGPR(), llvm::SIInstrInfo::shouldClusterMemOps(), llvm::SystemZRegisterInfo::shouldCoalesce(), llvm::ARMBaseRegisterInfo::shouldCoalesce(), llvm::ARMBaseInstrInfo::shouldSink(), SinkingPreventsImplicitNullCheck(), splitBlock(), splitMBB(), stripRegisterPrefix(), swapMIOperands(), llvm::SystemZInstrInfo::SystemZInstrInfo(), llvm::TailDuplicator::tailDuplicateAndUpdate(), tieOpsIfNeeded(), tryChangeVGPRtoSGPRinCopy(), tryFoldInst(), llvm::tryFoldSPUpdateIntoPushPop(), tryOptimizeLEAtoMOV(), llvm::FastISel::tryToFoldLoad(), updateKillStatus(), UpdateOperandRegClass(), updatePHIs(), updatePhysDepsDownwards(), UseReg(), llvm::R600InstrInfo::usesTextureCache(), llvm::R600InstrInfo::usesVertexCache(), validThroughout(), llvm::RegisterBankInfo::InstructionMapping::verify(), llvm::MachineFunction::verify(), llvm::SIInstrInfo::verifyInstruction(), llvm::VirtRegAuxInfo::weightCalcHelper(), and llvm::LegalizerHelper::widenScalar().

◆ getParent() [2/2]

MachineBasicBlock* llvm::MachineInstr::getParent ( )
inline

Definition at line 143 of file MachineInstr.h.

References getMF().

◆ getRegClassConstraint()

const TargetRegisterClass * MachineInstr::getRegClassConstraint ( unsigned  OpIdx,
const TargetInstrInfo TII,
const TargetRegisterInfo TRI 
) const

◆ getRegClassConstraintEffect()

const TargetRegisterClass * MachineInstr::getRegClassConstraintEffect ( unsigned  OpIdx,
const TargetRegisterClass CurRC,
const TargetInstrInfo TII,
const TargetRegisterInfo TRI 
) const

Applies the constraints (def/use) implied by the OpIdx operand to the given CurRC.

Returns the register class that satisfies both CurRC and the constraints set by OpIdx MI. Returns NULL if such a register class does not exist.

Precondition
CurRC must not be NULL.
The operand at OpIdx must be a register.

Definition at line 694 of file MachineInstr.cpp.

References assert(), llvm::TargetRegisterInfo::getCommonSubClass(), llvm::TargetRegisterInfo::getMatchingSuperRegClass(), getOperand(), getRegClassConstraint(), llvm::TargetRegisterInfo::getSubClassWithSubReg(), llvm::MachineOperand::getSubReg(), and llvm::MachineOperand::isReg().

Referenced by findRegisterDefOperand(), getRegClassConstraintEffectForVReg(), and llvm::MachineRegisterInfo::recomputeRegClass().

◆ getRegClassConstraintEffectForVReg()

const TargetRegisterClass * MachineInstr::getRegClassConstraintEffectForVReg ( unsigned  Reg,
const TargetRegisterClass CurRC,
const TargetInstrInfo TII,
const TargetRegisterInfo TRI,
bool  ExploreBundle = false 
) const

Applies the constraints (def/use) implied by this MI on Reg to the given CurRC.

If ExploreBundle is set and MI is part of a bundle, all the instructions inside the bundle will be taken into account. In other words, this method accumulates all the constraints of the operand of this MI and the related bundle if MI is a bundle or inside a bundle.

Returns the register class that satisfies both CurRC and the constraints set by MI. Returns NULL if such a register class does not exist.

Precondition
CurRC must not be NULL.

Definition at line 665 of file MachineInstr.cpp.

References assert(), getOperand(), llvm::MachineOperand::getReg(), getRegClassConstraintEffect(), llvm::MachineOperand::isReg(), llvm::MachineOperandIteratorBase::isValid(), and TII.

Referenced by findRegisterDefOperand(), and getNumAllocatableRegsForConstraints().

◆ getTypeToPrint()

LLT MachineInstr::getTypeToPrint ( unsigned  OpIdx,
SmallBitVector PrintedTypes,
const MachineRegisterInfo MRI 
) const

◆ hasComplexRegisterTies()

bool MachineInstr::hasComplexRegisterTies ( ) const

Return true when an instruction has tied register that can't be determined by the instruction's descriptor.

This is useful for MIR printing, to determine whether we need to print the ties or not.

Definition at line 1195 of file MachineInstr.cpp.

References E, findTiedOperandIdx(), getDesc(), getNumOperands(), getOperand(), llvm::MCInstrDesc::getOperandConstraint(), I, and llvm::MCOI::TIED_TO.

Referenced by isRegTiedToDefOperand(), llvm::MIPrinter::print(), and print().

◆ hasDelaySlot()

bool llvm::MachineInstr::hasDelaySlot ( QueryType  Type = AnyInBundle) const
inline

Returns true if the specified instruction has a delay slot which must be filled by the code generator.

Definition at line 563 of file MachineInstr.h.

References llvm::MCID::DelaySlot, and hasProperty().

Referenced by hasUnoccupiedSlot().

◆ hasExtraDefRegAllocReq()

bool llvm::MachineInstr::hasExtraDefRegAllocReq ( QueryType  Type = AnyInBundle) const
inline

Returns true if this instruction def operands have special register allocation requirements that are not captured by the operand register classes.

e.g. ARM::LDRD's two def registers must be an even / odd pair, ARM::LDM registers have to be in ascending order. Post-register allocation passes should not attempt to change allocations for definitions of instructions with this flag.

Definition at line 749 of file MachineInstr.h.

References llvm::MCID::ExtraDefRegAllocReq, and hasProperty().

Referenced by llvm::CriticalAntiDepBreaker::BreakAntiDependencies(), CriticalPathStep(), and llvm::MachineOperand::isRenamable().

◆ hasExtraSrcRegAllocReq()

bool llvm::MachineInstr::hasExtraSrcRegAllocReq ( QueryType  Type = AnyInBundle) const
inline

Returns true if this instruction source operands have special register allocation requirements that are not captured by the operand register classes.

e.g. ARM::STRD's two source registers must be an even / odd pair, ARM::STM registers have to be in ascending order. Post-register allocation passes should not attempt to change allocations for sources of instructions with this flag.

Definition at line 739 of file MachineInstr.h.

References llvm::MCID::ExtraSrcRegAllocReq, and hasProperty().

Referenced by CriticalPathStep(), and llvm::MachineOperand::isRenamable().

◆ hasOneMemOperand()

bool llvm::MachineInstr::hasOneMemOperand ( ) const
inline

◆ hasOptionalDef()

bool llvm::MachineInstr::hasOptionalDef ( QueryType  Type = IgnoreBundle) const
inline

Set if this instruction has an optional definition, e.g.

ARM instructions which can set condition code if 's' bit is set.

Definition at line 447 of file MachineInstr.h.

References llvm::MCID::HasOptionalDef, and hasProperty().

Referenced by llvm::ARMTargetLowering::AdjustInstrPostInstrSelection(), isCopy(), and llvm::ARMBaseInstrInfo::optimizeSelect().

◆ hasOrderedMemoryRef()

bool MachineInstr::hasOrderedMemoryRef ( ) const

Return true if this instruction may have an ordered or volatile memory reference, or if the information describing the memory reference is not available.

hasOrderedMemoryRef - Return true if this instruction may have an ordered or volatile memory reference, or if the information describing the memory reference is not available.

Return false if it is known to have no ordered or volatile memory references.

Return false if it is known to have no ordered memory references.

Definition at line 1078 of file MachineInstr.cpp.

References llvm::any_of(), hasUnmodeledSideEffects(), isCall(), llvm::MachineMemOperand::isUnordered(), mayLoad(), mayStore(), memoperands(), and memoperands_empty().

Referenced by addLiveInRegs(), areCandidatesToMergeOrPair(), llvm::LanaiInstrInfo::areMemAccessesTriviallyDisjoint(), llvm::AArch64InstrInfo::areMemAccessesTriviallyDisjoint(), llvm::SIInstrInfo::areMemAccessesTriviallyDisjoint(), llvm::HexagonInstrInfo::areMemAccessesTriviallyDisjoint(), canMoveInstsAcrossMemOp(), getStoreTarget(), llvm::AArch64InstrInfo::isCandidateToMergeOrPair(), isDependenceBarrier(), isGlobalMemoryObject(), llvm::HexagonPacketizerList::isLegalToPacketizeTogether(), isRegTiedToDefOperand(), isSafeToMove(), DeadCodeElimination::SetQueue< T >::push_back(), Query(), and removePhis().

◆ hasPostISelHook()

bool llvm::MachineInstr::hasPostISelHook ( QueryType  Type = IgnoreBundle) const
inline

Return true if this instruction requires adjustment after instruction selection by calling a target hook.

For example, this can be used to fill in ARM 's' optional operand depending on whether the conditional flag register is used.

Definition at line 708 of file MachineInstr.h.

References llvm::MCID::HasPostISelHook, and hasProperty().

Referenced by llvm::TargetLowering::AdjustInstrPostInstrSelection().

◆ hasProperty()

bool llvm::MachineInstr::hasProperty ( unsigned  MCFlag,
QueryType  Type = AnyInBundle 
) const
inline

Return true if the instruction (or in the case of a bundle, the instructions inside the bundle) has the specified property.

The first argument is the property being queried. The second argument indicates whether the query should look inside instruction bundles.

Definition at line 428 of file MachineInstr.h.

References getDesc(), llvm::MCInstrDesc::getFlags(), IgnoreBundle, isBundled(), and isBundledWithPred().

Referenced by canFoldAsLoad(), hasDelaySlot(), hasExtraDefRegAllocReq(), hasExtraSrcRegAllocReq(), hasOptionalDef(), hasPostISelHook(), hasUnmodeledSideEffects(), isAsCheapAsAMove(), isBarrier(), isBitcast(), isBranch(), isCall(), isCommutable(), isCompare(), isConvergent(), isConvertibleTo3Addr(), isExtractSubregLike(), isIndirectBranch(), isInsertSubregLike(), isMoveImmediate(), isNotDuplicable(), isPredicable(), isPseudo(), isRegSequenceLike(), isRematerializable(), isReturn(), isSelect(), isTerminator(), isVariadic(), mayLoad(), mayStore(), and usesCustomInsertionHook().

◆ hasRegisterImplicitUseOperand()

bool MachineInstr::hasRegisterImplicitUseOperand ( unsigned  Reg) const

Returns true if the MachineInstr has an implicit-use operand of exactly the given register (not considering sub/super-registers).

Definition at line 726 of file MachineInstr.cpp.

References getNumOperands(), getOperand(), llvm::MachineOperand::getReg(), llvm::MachineOperand::isImplicit(), llvm::MachineOperand::isReg(), and llvm::MachineOperand::isUse().

Referenced by addEpilogOnlyR10(), registerDefIsDead(), and llvm::SIInstrInfo::verifyInstruction().

◆ hasUnmodeledSideEffects()

bool MachineInstr::hasUnmodeledSideEffects ( ) const

◆ implicit_operands() [1/2]

iterator_range<mop_iterator> llvm::MachineInstr::implicit_operands ( )
inline

◆ implicit_operands() [2/2]

iterator_range<const_mop_iterator> llvm::MachineInstr::implicit_operands ( ) const
inline

◆ isAnnotationLabel()

bool llvm::MachineInstr::isAnnotationLabel ( ) const
inline

Definition at line 803 of file MachineInstr.h.

References llvm::ISD::ANNOTATION_LABEL, and getOpcode().

Referenced by isLabel().

◆ isAsCheapAsAMove()

bool llvm::MachineInstr::isAsCheapAsAMove ( QueryType  Type = AllInBundle) const
inline

Returns true if this instruction has the same cost (or less) than a move instruction.

This is useful during certain types of optimizations (e.g., remat during two-address conversion or machine licm) where we would like to remat or hoist the instruction, but not if it costs more than moving the instruction into the appropriate register. Note, we are not marking copies from and to the same register class with this flag.

Definition at line 728 of file MachineInstr.h.

References llvm::MCID::CheapAsAMove, and hasProperty().

Referenced by llvm::AArch64InstrInfo::isAsCheapAsAMove(), llvm::TargetInstrInfo::isAsCheapAsAMove(), and ShouldRematerialize().

◆ isBarrier()

bool llvm::MachineInstr::isBarrier ( QueryType  Type = AnyInBundle) const
inline

◆ isBitcast()

bool llvm::MachineInstr::isBitcast ( QueryType  Type = IgnoreBundle) const
inline

Return true if this instruction is a bitcast instruction.

Definition at line 533 of file MachineInstr.h.

References llvm::MCID::Bitcast, and hasProperty().

Referenced by getCopyRewriter().

◆ isBranch()

bool llvm::MachineInstr::isBranch ( QueryType  Type = AnyInBundle) const
inline

◆ isBundle()

bool llvm::MachineInstr::isBundle ( ) const
inline

◆ isBundled()

bool llvm::MachineInstr::isBundled ( ) const
inline

Return true if this instruction part of a bundle.

This is true if either itself or its following instruction is marked "InsideBundle".

Definition at line 244 of file MachineInstr.h.

References isBundledWithPred(), and isBundledWithSucc().

Referenced by dumpMachineInstrRangeWithSlotIndex(), llvm::LiveRangeEdit::eraseVirtReg(), llvm::LiveIntervals::handleMove(), hasProperty(), and llvm::X86FrameLowering::inlineStackProbe().

◆ isBundledWithPred()

bool llvm::MachineInstr::isBundledWithPred ( ) const
inline

◆ isBundledWithSucc()

bool llvm::MachineInstr::isBundledWithSucc ( ) const
inline

◆ isCall()

bool llvm::MachineInstr::isCall ( QueryType  Type = AnyInBundle) const
inline

Definition at line 461 of file MachineInstr.h.

References llvm::MCID::Call, and hasProperty().

Referenced by addEpilogOnlyR10(), addLiveInRegs(), llvm::ScheduleDAGInstrs::addSchedBarrierDeps(), areCandidatesToMergeOrPair(), llvm::CriticalAntiDepBreaker::BreakAntiDependencies(), callHasRegMask(), llvm::EHStreamer::callToNoUnwindFunction(), CanMovePastDMB(), cannotCoexistAsymm(), CriticalPathStep(), llvm::X86AsmPrinter::EmitInstruction(), llvm::SystemZHazardRecognizer::emitInstruction(), llvm::WinException::endFunclet(), eraseGPOpnd(), getEquivalentCallShort(), getFPReg(), llvm::rdf::DataFlowGraph::getNextShadow(), llvm::AArch64InstrInfo::getOutliningType(), llvm::AArch64InstrInfo::getOutlininingCandidateInfo(), llvm::X86InstrInfo::getSPAdjust(), getStoreTarget(), llvm::HexagonPacketizerList::hasControlDependence(), llvm::HexagonPacketizerList::hasDeadDependence(), hasOrderedMemoryRef(), hasRegisterDependency(), llvm::HexagonPacketizerList::hasRegMaskDependence(), hasYmmOrZmmReg(), INITIALIZE_PASS(), llvm::rdf::TargetOperandInfo::isClobbering(), llvm::HexagonInstrInfo::isComplex(), llvm::HexagonInstrInfo::isConstExtended(), isDependenceBarrier(), llvm::rdf::TargetOperandInfo::isFixedReg(), isGlobalMemoryObject(), llvm::HexagonPacketizerList::isLegalToPacketizeTogether(), isLoadFoldBarrier(), isNoReturnDef(), llvm::HexagonInstrInfo::isPredicable(), IsSafeAndProfitableToMove(), isSafeToMove(), llvm::ARMBaseInstrInfo::isSchedulingBoundary(), llvm::HexagonInstrInfo::isSchedulingBoundary(), llvm::PPCInstrInfo::isSignOrZeroExtended(), llvm::TargetInstrInfo::isTailCall(), mayAlias(), needsStackFrame(), llvm::rdf::operator<<(), DeadCodeElimination::SetQueue< T >::push_back(), Query(), regOverlapsSet(), llvm::TailDuplicator::shouldTailDuplicate(), and UpdateCPSRUse().

◆ isCFIInstruction()

bool llvm::MachineInstr::isCFIInstruction ( ) const
inline

◆ isCommutable()

bool llvm::MachineInstr::isCommutable ( QueryType  Type = IgnoreBundle) const
inline

Return true if this may be a 2- or 3-address instruction (of the form "X = op Y, Z, ..."), which produces the same result if Y and Z are exchanged.

If this flag is set, then the TargetInstrInfo::commuteInstruction method may be used to hack on the instruction.

Note that this flag may be set on instructions that are only commutable sometimes. In these cases, the call to commuteInstruction will fail. Also note that some instructions require non-trivial modification to commute them.

Definition at line 670 of file MachineInstr.h.

References llvm::MCID::Commutable, and hasProperty().

Referenced by addSegmentsWithValNo(), llvm::TargetInstrInfo::commuteInstruction(), llvm::SIInstrInfo::findCommutedOpIndices(), foldImmediates(), isLiveOut(), llvm::SIInstrInfo::legalizeOperandsVOP2(), regOverlapsSet(), shrinkScalarCompare(), and tryConstantFoldOp().

◆ isCompare()

bool llvm::MachineInstr::isCompare ( QueryType  Type = IgnoreBundle) const
inline

◆ isConditionalBranch()

bool llvm::MachineInstr::isConditionalBranch ( QueryType  Type = AnyInBundle) const
inline

Return true if this is a branch which may fall through to the next instruction or may transfer control flow to some other block.

The TargetInstrInfo::AnalyzeBranch method can be used to get more information about this branch.

Definition at line 499 of file MachineInstr.h.

References isBarrier(), isBranch(), and isIndirectBranch().

Referenced by llvm::HexagonInstrInfo::getDotNewPredJumpOp(), and isVirtualRegisterOperand().

◆ isConstantValuePHI()

unsigned MachineInstr::isConstantValuePHI ( ) const

If the specified instruction is a PHI that always merges together the same virtual register, return the register, otherwise return 0.

isConstantValuePHI - If the specified instruction is a PHI that always merges together the same virtual register, return the register, otherwise return 0.

Definition at line 1142 of file MachineInstr.cpp.

References assert(), getNumOperands(), getOperand(), llvm::MachineOperand::getReg(), getReg(), and isPHI().

Referenced by llvm::MachineSSAUpdater::GetValueInMiddleOfBlock(), and isRegTiedToDefOperand().

◆ isConvergent()

bool llvm::MachineInstr::isConvergent ( QueryType  Type = AnyInBundle) const
inline

Return true if this instruction is convergent.

Convergent instructions can not be made control-dependent on any additional values.

Definition at line 552 of file MachineInstr.h.

References llvm::MCID::Convergent, llvm::InlineAsm::Extra_IsConvergent, llvm::MachineOperand::getImm(), getOperand(), hasProperty(), isInlineAsm(), and llvm::InlineAsm::MIOp_ExtraInfo.

Referenced by llvm::TailDuplicator::shouldTailDuplicate(), and SinkingPreventsImplicitNullCheck().

◆ isConvertibleTo3Addr()

bool llvm::MachineInstr::isConvertibleTo3Addr ( QueryType  Type = IgnoreBundle) const
inline

Return true if this is a 2-address instruction which can be changed into a 3-address instruction if needed.

Doing this transformation can be profitable in the register allocator, because it means that the instruction can use a 2-address form if possible, but degrade into a less efficient form if the source and dest register cannot be assigned to the same register. For example, this allows the x86 backend to turn a "shl reg, 3" instruction into an LEA instruction, which is the same speed as the shift but has bigger code size.

If this returns true, then the target must implement the TargetInstrInfo::convertToThreeAddress method for this instruction, which is allowed to fail if the transformation isn't valid for this specific instruction (e.g. shl reg, 4 on x86).

Definition at line 688 of file MachineInstr.h.

References llvm::MCID::ConvertibleTo3Addr, and hasProperty().

Referenced by regOverlapsSet().

◆ isCopy()

bool llvm::MachineInstr::isCopy ( ) const
inline

Definition at line 860 of file MachineInstr.h.

References getOpcode().

Referenced by addSegmentsWithValNo(), llvm::HexagonSubtarget::adjustSchedDependency(), llvm::HexagonSubtarget::CallMutation::apply(), llvm::biasPhysRegCopy(), BuildInstOrderMap(), canFoldCopy(), changeFCMPPredToAArch64CC(), computeBranchTargetAndInversion(), llvm::createCopyConstrainDAGMutation(), llvm::createHexagonHardwareLoops(), dumpMachineInstrRangeWithSlotIndex(), llvm::LiveRangeEdit::eraseVirtReg(), llvm::HexagonEvaluator::evaluate(), llvm::ARMBaseInstrInfo::expandPostRAPseudo(), llvm::TargetInstrInfo::foldMemoryOperand(), llvm::AArch64InstrInfo::foldMemoryOperandImpl(), llvm::X86InstrInfo::foldMemoryOperandImpl(), foldVGPRCopyIntoRegSequence(), getFPReg(), getNewSource(), getRegClassFromGRPhysReg(), getSingleDef(), getSubOpcode(), getWinAllocaAmount(), hasRegisterDependency(), INITIALIZE_PASS(), insertPHI(), InstructionStoresToFI(), isCopyFeedingInvariantStore(), isCopyLike(), isCopyLike(), isCopyToReg(), isDebug(), isDefInSubRange(), isFpMulInstruction(), isFullCopy(), isFullCopyOf(), isIdentityCopy(), llvm::SIInstrInfo::isInlineConstant(), isLocalCopy(), isUseSafeToFold(), llvm::SIInstrInfo::isVGPRCopy(), isVirtualRegisterOperand(), llvm::TargetRegisterInfo::lookThruCopyLike(), MIIsInTerminatorSequence(), llvm::SIInstrInfo::moveToVALU(), llvm::AArch64InstrInfo::optimizeCondBranch(), printExtendedName(), regOverlapsSet(), llvm::GenericScheduler::reschedulePhysRegCopies(), llvm::SelectionDAGISel::runOnMachineFunction(), selectCopy(), llvm::SystemZRegisterInfo::shouldCoalesce(), llvm::TailDuplicator::tailDuplicateAndUpdate(), and llvm::VirtRegAuxInfo::weightCalcHelper().

◆ isCopyLike()

bool llvm::MachineInstr::isCopyLike ( ) const
inline

Return true if the instruction behaves like a copy.

This does not include native copy instructions.

Definition at line 874 of file MachineInstr.h.

References isCopy(), and isSubregToReg().

Referenced by definesFullReg(), llvm::ARMBaseInstrInfo::getOperandLatency(), INITIALIZE_PASS(), isCopyFeedingInvariantStore(), isSplitEdge(), isTerminalReg(), llvm::TargetRegisterInfo::lookThruCopyLike(), and regOverlapsSet().

◆ isDebugValue()

bool llvm::MachineInstr::isDebugValue ( ) const
inline

Definition at line 819 of file MachineInstr.h.

References getOpcode().

Referenced by llvm::MachineInstrBuilder::addMetadata(), addRegsToSet(), addSegmentsWithValNo(), AssignProtectedObjSet(), llvm::CodeViewDebug::beginInstruction(), llvm::CriticalAntiDepBreaker::BreakAntiDependencies(), llvm::AggressiveAntiDepBreaker::BreakAntiDependencies(), BuildInstOrderMap(), llvm::ScheduleDAGInstrs::buildSchedGraph(), llvm::RegPressureTracker::bumpDownwardPressure(), llvm::RegPressureTracker::bumpUpwardPressure(), llvm::createBreakFalseDeps(), llvm::createX86OptimizeLEAs(), llvm::ConnectedVNInfoEqClasses::Distribute(), llvm::ARCRegisterInfo::eliminateFrameIndex(), llvm::XCoreRegisterInfo::eliminateFrameIndex(), llvm::ThumbRegisterInfo::eliminateFrameIndex(), llvm::AArch64RegisterInfo::eliminateFrameIndex(), llvm::ARMBaseRegisterInfo::eliminateFrameIndex(), llvm::ARMHazardRecognizer::EmitInstruction(), llvm::PPCHazardRecognizer970::EmitInstruction(), llvm::MipsAsmPrinter::EmitInstruction(), llvm::RegScavenger::enterBasicBlockEnd(), llvm::BitTracker::MachineEvaluator::evaluate(), llvm::DbgVariableLocation::extractFromMachineInstruction(), FindStartOfTree(), getDataDeps(), getDebugExpression(), getDebugVariable(), llvm::ARMHazardRecognizer::getHazardType(), llvm::PPCHazardRecognizer970::getHazardType(), getLoadStoreOffsetAlign(), getNewValueJumpOpcode(), llvm::AArch64InstrInfo::getOutliningType(), llvm::X86InstrInfo::getOutliningType(), getRetpolineSymbol(), getSchedRegions(), getSingleDef(), llvm::HexagonInstrInfo::getSize(), getStartOrEndSlot(), llvm::LiveIntervals::handleMoveIntoBundle(), llvm::LiveVariables::HandleVirtRegDef(), llvm::HexagonPacketizerList::ignorePseudoInstruction(), INITIALIZE_PASS(), llvm::SlotIndexes::insertMachineInstrInMaps(), llvm::Mips16RegisterInfo::intRegClass(), isDbgValueDescribedByReg(), isDefBetween(), isDescribedByReg(), isFullCopyOf(), isFullUndefDef(), isIdenticalTo(), isIndirectDebugValue(), IsSafeAndProfitableToMove(), isSafeToMove(), llvm::ARMBaseInstrInfo::isSchedulingBoundary(), llvm::HexagonInstrInfo::isSchedulingBoundary(), isVirtualRegisterOperand(), llvm::MachineRegisterInfo::markUsesInDebugValueAsUndef(), matchPair(), MaySpeculate(), llvm::DebugLocEntry::MergeValues(), MIIsInTerminatorSequence(), needsReferenceType(), llvm::CriticalAntiDepBreaker::Observe(), false::IntervalSorter::operator()(), print(), Query(), readsVCCZ(), llvm::GCNUpwardRPTracker::recede(), removeDeadSegment(), llvm::SlotIndexes::repairIndexesInRange(), llvm::LiveIntervals::repairIntervalsInRange(), llvm::rdf::Liveness::resetKills(), llvm::SelectionDAGISel::runOnMachineFunction(), llvm::DbgValueHistoryMap::startInstrRange(), llvm::TailDuplicator::tailDuplicateAndUpdate(), llvm::HexagonPacketizerList::unpacketizeSoloInstrs(), llvm::RegScavenger::unprocess(), UpdateCPSRUse(), llvm::AntiDepBreaker::UpdateDbgValue(), UseReg(), validThroughout(), and llvm::VirtRegAuxInfo::weightCalcHelper().

◆ isDereferenceableInvariantLoad()

bool MachineInstr::isDereferenceableInvariantLoad ( AliasAnalysis AA) const

Return true if this load instruction never traps and points to a memory location whose value doesn't change during the execution of this function.

isDereferenceableInvariantLoad - Return true if this instruction will never trap and is loading from a location whose value is invariant across a run of this function.

Examples include loading a value from the constant pool or from the argument area of a function (if it does not change). If the instruction does multiple loads, this returns true only if all of the loads are dereferenceable and invariant.

Definition at line 1100 of file MachineInstr.cpp.

References llvm::MachineFunction::getFrameInfo(), getParent(), llvm::MachineBasicBlock::getParent(), mayLoad(), memoperands(), memoperands_empty(), and llvm::AAResults::pointsToConstantMemory().

Referenced by llvm::ScheduleDAGInstrs::buildSchedGraph(), isCopyFeedingInvariantStore(), isDependenceBarrier(), isGlobalMemoryObject(), llvm::X86InstrInfo::isReallyTriviallyReMaterializable(), isRegTiedToDefOperand(), isSafeToMove(), Query(), and llvm::TargetInstrInfo::trackRegDefsUses().

◆ isEHLabel()

bool llvm::MachineInstr::isEHLabel ( ) const
inline

◆ isExtractSubreg()

bool llvm::MachineInstr::isExtractSubreg ( ) const
inline

◆ isExtractSubregLike()

bool llvm::MachineInstr::isExtractSubregLike ( QueryType  Type = IgnoreBundle) const
inline

Return true if this instruction behaves the same way as the generic EXTRACT_SUBREG instructions.

E.g., on ARM, rX, rY VMOVRRD dZ is equivalent to two EXTRACT_SUBREG: rX = EXTRACT_SUBREG dZ, ssub_0 rY = EXTRACT_SUBREG dZ, ssub_1

Note that for the optimizers to be able to take advantage of this property, TargetInstrInfo::getExtractSubregLikeInputs has to be override accordingly.

Definition at line 604 of file MachineInstr.h.

References llvm::MCID::ExtractSubreg, and hasProperty().

Referenced by getCopyRewriter(), llvm::TargetInstrInfo::getExtractSubregInputs(), and llvm::ARMBaseInstrInfo::getExtractSubregLikeInputs().

◆ isFullCopy()

bool llvm::MachineInstr::isFullCopy ( ) const
inline

◆ isGCLabel()

bool llvm::MachineInstr::isGCLabel ( ) const
inline

Definition at line 802 of file MachineInstr.h.

References getOpcode().

Referenced by isLabel().

◆ isIdenticalTo()

bool MachineInstr::isIdenticalTo ( const MachineInstr Other,
MICheckType  Check = CheckDefs 
) const

◆ isIdentityCopy()

bool llvm::MachineInstr::isIdentityCopy ( ) const
inline

Return true is the instruction is an identity copy.

Definition at line 879 of file MachineInstr.h.

References getOperand(), llvm::MachineOperand::getReg(), llvm::MachineOperand::getSubReg(), and isCopy().

Referenced by llvm::VirtRegAuxInfo::weightCalcHelper().

◆ isImplicitDef()

bool llvm::MachineInstr::isImplicitDef ( ) const
inline

◆ isIndirectBranch()

bool llvm::MachineInstr::isIndirectBranch ( QueryType  Type = AnyInBundle) const
inline

◆ isIndirectDebugValue()

bool llvm::MachineInstr::isIndirectDebugValue ( ) const
inline

◆ isInlineAsm()

bool llvm::MachineInstr::isInlineAsm ( ) const
inline

◆ isInsertSubreg()

bool llvm::MachineInstr::isInsertSubreg ( ) const
inline

◆ isInsertSubregLike()

bool llvm::MachineInstr::isInsertSubregLike ( QueryType  Type = IgnoreBundle) const
inline

Return true if this instruction behaves the same way as the generic INSERT_SUBREG instructions.

E.g., on ARM, dX = VSETLNi32 dY, rZ, Imm is equivalent to a INSERT_SUBREG: dX = INSERT_SUBREG dY, rZ, translateImmToSubIdx(Imm)

Note that for the optimizers to be able to take advantage of this property, TargetInstrInfo::getInsertSubregLikeInputs has to be override accordingly.

Definition at line 618 of file MachineInstr.h.

References hasProperty(), and llvm::MCID::InsertSubreg.

Referenced by getCopyRewriter(), llvm::TargetInstrInfo::getInsertSubregInputs(), and llvm::ARMBaseInstrInfo::getInsertSubregLikeInputs().

◆ isInsideBundle()

bool llvm::MachineInstr::isInsideBundle ( ) const
inline

Return true if MI is in a bundle (but not the first MI in a bundle).

A bundle looks like this before it's finalized:

| MI |

|

| MI * |

|

| MI * |

In this case, the first MI starts a bundle but is not inside a bundle, the next 2 MIs are considered "inside" the bundle.

After a bundle is finalized, it looks like this:

| Bundle |

|

| MI * |

|

| MI * |

|

| MI * |

The first instruction has the special opcode "BUNDLE". It's not "inside" a bundle, but the next three MIs are.

Definition at line 238 of file MachineInstr.h.

References BundledPred, and getFlag().

Referenced by llvm::BuildMI(), llvm::SlotIndexes::insertMachineInstrInMaps(), matchPair(), llvm::MIPrinter::print(), llvm::MachineBasicBlock::print(), llvm::HexagonPacketizerList::unpacketizeSoloInstrs(), and UpdateCPSRUse().

◆ isKill()

bool llvm::MachineInstr::isKill ( ) const
inline

◆ isLabel()

bool llvm::MachineInstr::isLabel ( ) const
inline

Returns true if the MachineInstr represents a label.

Definition at line 808 of file MachineInstr.h.

References isAnnotationLabel(), isEHLabel(), and isGCLabel().

Referenced by FindStartOfTree(), and isPosition().

◆ isLoadFoldBarrier()

bool MachineInstr::isLoadFoldBarrier ( ) const

Returns true if it is illegal to fold a load across this instruction.

Definition at line 1167 of file MachineInstr.cpp.

References hasUnmodeledSideEffects(), isCall(), and mayStore().

Referenced by isRegTiedToDefOperand(), and isVirtualRegisterOperand().

◆ isMetaInstruction()

bool llvm::MachineInstr::isMetaInstruction ( ) const
inline

◆ isMoveImmediate()

bool llvm::MachineInstr::isMoveImmediate ( QueryType  Type = IgnoreBundle) const
inline

Return true if this instruction is a move immediate (including conditional moves) instruction.

Definition at line 528 of file MachineInstr.h.

References hasProperty(), and llvm::MCID::MoveImm.

Referenced by foldImmediates(), getImmOrMaterializedImm(), getNewSource(), isSafeToFoldImmIntoCopy(), and llvm::SIInstrInfo::legalizeGenericOperand().

◆ isMSInlineAsm()

bool llvm::MachineInstr::isMSInlineAsm ( ) const
inline

◆ isNotDuplicable()

bool llvm::MachineInstr::isNotDuplicable ( QueryType  Type = AnyInBundle) const
inline

Return true if this instruction cannot be safely duplicated.

For example, if the instruction has a unique labels attached to it, duplicating it would cause multiple definition errors.

Definition at line 545 of file MachineInstr.h.

References hasProperty(), and llvm::MCID::NotDuplicable.

Referenced by llvm::TargetInstrInfo::duplicate(), llvm::TailDuplicator::shouldTailDuplicate(), and llvm::TargetInstrInfo::trackRegDefsUses().

◆ isOperandSubregIdx()

bool llvm::MachineInstr::isOperandSubregIdx ( unsigned  OpIdx) const
inline

Return true if operand OpIdx is a subregister index.

Definition at line 308 of file MachineInstr.h.

References assert(), getNumExplicitOperands(), getOperand(), getType(), isExtractSubreg(), isInsertSubreg(), isRegSequence(), isSubregToReg(), and llvm::MachineOperand::MO_Immediate.

Referenced by llvm::MIPrinter::print(), and print().

◆ isPHI()

bool llvm::MachineInstr::isPHI ( ) const
inline

◆ isPosition()

bool llvm::MachineInstr::isPosition ( ) const
inline

◆ isPredicable()

bool llvm::MachineInstr::isPredicable ( QueryType  Type = AllInBundle) const
inline

Return true if this instruction has a predicate operand that controls execution.

It may be set to 'always', or may be set to other values. There are various methods in TargetInstrInfo that can be used to control and modify the predicate in this instruction.

Definition at line 515 of file MachineInstr.h.

References hasProperty(), and llvm::MCID::Predicable.

Referenced by AnyAliasLiveIn(), canFoldIntoMOVCC(), canFoldIntoSelect(), llvm::ThumbRegisterInfo::eliminateFrameIndex(), llvm::ARMBaseInstrInfo::isPredicable(), llvm::MSP430InstrInfo::isUnpredicatedTerminator(), llvm::X86InstrInfo::isUnpredicatedTerminator(), llvm::TargetInstrInfo::isUnpredicatedTerminator(), llvm::TargetInstrInfo::PredicateInstruction(), registerDefinedBetween(), and SinkingPreventsImplicitNullCheck().

◆ isPseudo()

bool llvm::MachineInstr::isPseudo ( QueryType  Type = IgnoreBundle) const
inline

Return true if this is a pseudo instruction that doesn't correspond to a real machine instruction.

Definition at line 453 of file MachineInstr.h.

References hasProperty(), and llvm::MCID::Pseudo.

Referenced by llvm::TargetSubtargetInfo::getSchedInfoStr(), INITIALIZE_PASS(), insertNopBeforeInstruction(), and llvm::ConvergingVLIWScheduler::SchedulingCost().

◆ isRegSequence()

bool llvm::MachineInstr::isRegSequence ( ) const
inline

◆ isRegSequenceLike()

bool llvm::MachineInstr::isRegSequenceLike ( QueryType  Type = IgnoreBundle) const
inline

Return true if this instruction behaves the same way as the generic REG_SEQUENCE instructions.

E.g., on ARM, dX VMOVDRR rY, rZ is equivalent to dX = REG_SEQUENCE rY, ssub_0, rZ, ssub_1.

Note that for the optimizers to be able to take advantage of this property, TargetInstrInfo::getRegSequenceLikeInputs has to be override accordingly.

Definition at line 589 of file MachineInstr.h.

References hasProperty(), and llvm::MCID::RegSequence.

Referenced by getCopyRewriter(), llvm::TargetInstrInfo::getRegSequenceInputs(), and llvm::ARMBaseInstrInfo::getRegSequenceLikeInputs().

◆ isRegTiedToDefOperand()

bool llvm::MachineInstr::isRegTiedToDefOperand ( unsigned  UseOpIdx,
unsigned DefOpIdx = nullptr 
) const
inline

◆ isRegTiedToUseOperand()

bool llvm::MachineInstr::isRegTiedToUseOperand ( unsigned  DefOpIdx,
unsigned UseOpIdx = nullptr 
) const
inline

Given the index of a register def operand, check if the register def is tied to a source operand, due to either two-address elimination or inline assembly constraints.

Returns the first tied use operand index by reference if UseOpIdx is not null.

Definition at line 1100 of file MachineInstr.h.

References findTiedOperandIdx(), getOperand(), llvm::MachineOperand::isDef(), llvm::MachineOperand::isReg(), and llvm::MachineOperand::isTied().

Referenced by addSegmentsWithValNo(), llvm::constrainSelectedInstRegOperands(), CriticalPathStep(), INITIALIZE_PASS(), isVirtualRegisterOperand(), multipleIterations(), llvm::AggressiveAntiDepBreaker::Observe(), removePhis(), and llvm::SIInstrInfo::verifyInstruction().

◆ isRematerializable()

bool llvm::MachineInstr::isRematerializable ( QueryType  Type = AllInBundle) const
inline

Returns true if this instruction is a candidate for remat.

This flag is deprecated, please don't use it anymore. If this flag is set, the isReallyTriviallyReMaterializable() method is called to verify the instruction is really rematable.

Definition at line 716 of file MachineInstr.h.

References hasProperty(), and llvm::MCID::Rematerializable.

◆ isReturn()

bool llvm::MachineInstr::isReturn ( QueryType  Type = AnyInBundle) const
inline

◆ isSafeToMove()

bool MachineInstr::isSafeToMove ( AliasAnalysis AA,
bool SawStore 
) const

Return true if it is safe to move this instruction.

isSafeToMove - Return true if it is safe to move this instruction.

If SawStore is set to true, it means that there is a store (or call) between the instruction's location and its intended destination.

Definition at line 960 of file MachineInstr.cpp.

References hasOrderedMemoryRef(), hasUnmodeledSideEffects(), isCall(), isDebugValue(), isDereferenceableInvariantLoad(), isPHI(), isPosition(), isTerminator(), mayLoad(), and mayStore().

Referenced by BuildInstOrderMap(), canFoldIntoMOVCC(), canFoldIntoSelect(), definesFullReg(), llvm::LiveRangeEdit::eraseVirtReg(), findSinkableLocalRegDef(), isCopyFeedingInvariantStore(), isDebug(), isRegTiedToDefOperand(), llvm::isTriviallyDead(), MaySpeculate(), llvm::X86InstrInfo::optimizeLoadInstr(), regOverlapsSet(), and SinkingPreventsImplicitNullCheck().

◆ isSelect()

bool llvm::MachineInstr::isSelect ( QueryType  Type = IgnoreBundle) const
inline

Return true if this instruction is a select instruction.

Definition at line 538 of file MachineInstr.h.

References hasProperty(), and llvm::MCID::Select.

Referenced by isVirtualRegisterOperand().

◆ isStackAligningInlineAsm()

bool MachineInstr::isStackAligningInlineAsm ( ) const

◆ isSubregToReg()

bool llvm::MachineInstr::isSubregToReg ( ) const
inline

◆ isTerminator()

bool llvm::MachineInstr::isTerminator ( QueryType  Type = AnyInBundle) const
inline

◆ isTransient()

bool llvm::MachineInstr::isTransient ( ) const
inline

Return true if this is a transient instruction that is either very likely to be eliminated during register allocation (such as copy-like instructions), or if this instruction doesn't have an execution-time cost.

Definition at line 905 of file MachineInstr.h.

References getBundleSize(), getOpcode(), and isMetaInstruction().

Referenced by areCandidatesToMergeOrPair(), llvm::TargetSchedModel::computeOperandLatency(), llvm::createSIWholeQuadModePass(), llvm::TargetInstrInfo::defaultDefLatency(), llvm::HexagonInstrInfo::getInstrTimingClassLatency(), llvm::TargetSchedModel::getNumMicroOps(), ImmInRange(), mayAlias(), updatePhysDepsUpwards(), llvm::SchedDFSImpl::visitPostorderNode(), and llvm::SchedDFSImpl::visitPreorder().

◆ isUnconditionalBranch()

bool llvm::MachineInstr::isUnconditionalBranch ( QueryType  Type = AnyInBundle) const
inline

Return true if this is a branch which always transfers control flow to some other block.

The TargetInstrInfo::AnalyzeBranch method can be used to get more information about this branch.

Definition at line 507 of file MachineInstr.h.

References isBarrier(), isBranch(), and isIndirectBranch().

Referenced by llvm::MipsInstrInfo::analyzeBranch(), llvm::RegBankSelect::getAnalysisUsage(), getUnconditionalBrDisp(), INITIALIZE_PASS(), and isSplitEdge().

◆ isVariadic()

bool llvm::MachineInstr::isVariadic ( QueryType  Type = IgnoreBundle) const
inline

Return true if this instruction can have a variable number of operands.

In this case, the variable operands will be after the normal operands but before the implicit definitions and uses (if any are present).

Definition at line 441 of file MachineInstr.h.

References hasProperty(), and llvm::MCID::Variadic.

Referenced by llvm::createBreakFalseDeps(), llvm::SIInstrInfo::getOpRegClass(), getTypeToPrint(), INITIALIZE_PASS(), and matchPair().

◆ killsRegister()

bool llvm::MachineInstr::killsRegister ( unsigned  Reg,
const TargetRegisterInfo TRI = nullptr 
) const
inline

Return true if the MachineInstr kills the specified register.

If TargetRegisterInfo is passed, then it also checks if there is a kill of a super-register.

Definition at line 953 of file MachineInstr.h.

References findRegisterUseOperandIdx().

Referenced by llvm::X86InstrInfo::breakPartialRegDependency(), checkEFLAGSLive(), ContainsReg(), createPHIsForCMOVsInSinkBB(), isPlainlyKilled(), llvm::X86InstrInfo::optimizeCompareInstr(), UpdateCPSRUse(), and UseReg().

◆ mayAlias()

bool MachineInstr::mayAlias ( AliasAnalysis AA,
MachineInstr Other,
bool  UseTBAA 
)

Returns true if this instruction's memory access aliases the memory access of Other.

Assumes any physical registers used to compute addresses have the same value for both instructions. Returns false if neither instruction writes to memory.

Parameters
AAOptional alias analysis, used to compare memory operands.
OtherMachineInstr to check aliasing against.
UseTBAAWhether to pass TBAA information to alias analysis.

Definition at line 989 of file MachineInstr.cpp.

References llvm::AAResults::alias(), llvm::TargetInstrInfo::areMemAccessesTriviallyDisjoint(), assert(), llvm::MachineMemOperand::getAAInfo(), llvm::MachineFunction::getFrameInfo(), llvm::TargetSubtargetInfo::getInstrInfo(), getMF(), llvm::MachineMemOperand::getOffset(), llvm::MachineMemOperand::getPseudoValue(), llvm::MachineMemOperand::getSize(), llvm::MachineFunction::getSubtarget(), llvm::MachineMemOperand::getValue(), hasOneMemOperand(), llvm::max(), llvm::PseudoSourceValue::mayAlias(), mayStore(), memoperands_begin(), and llvm::NoAlias.

Referenced by llvm::ScheduleDAGInstrs::addChainDependency(), isRegTiedToDefOperand(), and mayAlias().

◆ mayLoad()

bool llvm::MachineInstr::mayLoad ( QueryType  Type = AnyInBundle) const
inline

Return true if this instruction could possibly read memory.

Instructions with this flag set are not necessarily simple load instructions, they may load a value and modify it, for example.

Definition at line 629 of file MachineInstr.h.

References llvm::InlineAsm::Extra_MayLoad, llvm::MachineOperand::getImm(), getOperand(), hasProperty(), isInlineAsm(), llvm::MCID::MayLoad, and llvm::InlineAsm::MIOp_ExtraInfo.

Referenced by addLiveInRegs(), AnyAliasLiveIn(), llvm::HexagonSubtarget::HVXMemLatencyMutation::apply(), llvm::HexagonSubtarget::BankConflictMutation::apply(), areCandidatesToMergeOrPair(), llvm::SIInstrInfo::areMemAccessesTriviallyDisjoint(), llvm::HexagonInstrInfo::areMemAccessesTriviallyDisjoint(), llvm::TargetInstrInfo::areMemAccessesTriviallyDisjoint(), llvm::ScheduleDAGInstrs::buildSchedGraph(), CanMovePastDMB(), llvm::HexagonPacketizerList::canPromoteToNewValueStore(), llvm::createStoreClusterDAGMutation(), llvm::TargetInstrInfo::defaultDefLatency(), llvm::HexagonFrameLowering::determineCalleeSaves(), llvm::WebAssemblyRegisterInfo::eliminateFrameIndex(), llvm::ThumbRegisterInfo::eliminateFrameIndex(), llvm::HexagonHazardRecognizer::EmitInstruction(), llvm::TargetLoweringBase::emitPatchPoint(), eraseGPOpnd(), llvm::HexagonEvaluator::evaluate(), llvm::TargetInstrInfo::foldMemoryOperand(), llvm::HexagonInstrInfo::getBaseAndOffsetPosition(), llvm::TargetInstrInfo::getInstrLatency(), llvm::SISubtarget::getMaxNumVGPRs(), llvm::SIInstrInfo::getMemOpBaseRegImmOfs(), getNewSource(), llvm::ARMBaseInstrInfo::getOperandLatency(), getPostIncrementOperand(), getStoreTarget(), getUnderlyingObjects(), hasOrderedMemoryRef(), INITIALIZE_PASS(), isCopyFeedingInvariantStore(), isDependenceBarrier(), isDereferenceableInvariantLoad(), llvm::HexagonInstrInfo::isEarlySourceInstr(), llvm::HexagonInstrInfo::isHVXMemWithAIndirect(), llvm::HexagonPacketizerList::isLegalToPacketizeTogether(), llvm::SIInstrInfo::isLoadFromStackSlot(), llvm::ARMBaseInstrInfo::isLoadFromStackSlotPostFE(), isSafeToMove(), matchPair(), mayLoadFromGOTOrConstantPool(), mayLoadOrStore(), llvm::AArch64RegisterInfo::needsFrameBaseReg(), packCmovGroup(), profitImm(), Query(), readsVCCZ(), regOverlapsSet(), removePhis(), llvm::HexagonHazardRecognizer::ShouldPreferAnother(), SinkingPreventsImplicitNullCheck(), and llvm::TargetInstrInfo::trackRegDefsUses().

◆ mayLoadOrStore()

bool llvm::MachineInstr::mayLoadOrStore ( QueryType  Type = AnyInBundle) const
inline

◆ mayStore()

bool llvm::MachineInstr::mayStore ( QueryType  Type = AnyInBundle) const
inline

Return true if this instruction could possibly modify memory.

Instructions with this flag set are not necessarily simple store instructions, they may store a modified value based on their operands, or may not actually modify anything, for example.

Definition at line 642 of file MachineInstr.h.

References llvm::InlineAsm::Extra_MayStore, llvm::MachineOperand::getImm(), getOperand(), hasProperty(), isInlineAsm(), llvm::MCID::MayStore, and llvm::InlineAsm::MIOp_ExtraInfo.

Referenced by addLiveInRegs(), llvm::SUnit::addPredBarrier(), addRegsToSet(), AnyAliasLiveIn(), llvm::HexagonSubtarget::HVXMemLatencyMutation::apply(), llvm::HexagonSubtarget::BankConflictMutation::apply(), llvm::SIInstrInfo::areMemAccessesTriviallyDisjoint(), llvm::TargetInstrInfo::areMemAccessesTriviallyDisjoint(), BuildInstOrderMap(), llvm::ScheduleDAGInstrs::buildSchedGraph(), llvm::HexagonInstrInfo::canExecuteInBundle(), CanMovePastDMB(), llvm::HexagonPacketizerList::canPromoteToNewValueStore(), llvm::ARMBaseInstrInfo::convertToThreeAddress(), llvm::createSIWholeQuadModePass(), llvm::createStoreClusterDAGMutation(), llvm::HexagonFrameLowering::determineCalleeSaves(), llvm::WebAssemblyRegisterInfo::eliminateFrameIndex(), llvm::ThumbRegisterInfo::eliminateFrameIndex(), llvm::HexagonHazardRecognizer::EmitInstruction(), llvm::ARMAsmPrinter::EmitJumpTableTBInst(), llvm::TargetInstrInfo::foldMemoryOperand(), llvm::HexagonInstrInfo::getBaseAndOffsetPosition(), getInstrVecReg(), llvm::SISubtarget::getMaxNumVGPRs(), llvm::SIInstrInfo::getMemOpBaseRegImmOfs(), getStoreTarget(), getUnderlyingObjects(), hasOrderedMemoryRef(), hasRAWHazard(), llvm::HexagonPacketizerList::hasV4SpecificDependence(), INITIALIZE_PASS(), isCopyFeedingInvariantStore(), llvm::HexagonInstrInfo::isEarlySourceInstr(), isFullCopyOf(), llvm::HexagonInstrInfo::isHVXMemWithAIndirect(), isInvariantStore(), llvm::HexagonPacketizerList::isLegalToPacketizeTogether(), isLoadFoldBarrier(), llvm::HexagonPacketizerList::isNewifiable(), isSafeToMove(), llvm::SIInstrInfo::isStoreToStackSlot(), llvm::ARMBaseInstrInfo::isStoreToStackSlotPostFE(), matchPair(), mayAlias(), mayAlias(), mayLoadOrStore(), llvm::AArch64RegisterInfo::needsFrameBaseReg(), populateCandidates(), DeadCodeElimination::SetQueue< T >::push_back(), Query(), readsVCCZ(), removePhis(), splitBlock(), llvm::TargetInstrInfo::trackRegDefsUses(), and llvm::SIInstrInfo::verifyInstruction().

◆ memoperands() [1/2]

iterator_range<mmo_iterator> llvm::MachineInstr::memoperands ( )
inline

◆ memoperands() [2/2]

iterator_range<mmo_iterator> llvm::MachineInstr::memoperands ( ) const
inline

Definition at line 402 of file MachineInstr.h.

References llvm::make_range(), memoperands_begin(), and memoperands_end().

◆ memoperands_begin()

mmo_iterator llvm::MachineInstr::memoperands_begin ( ) const
inline

Access to memory operands of the instruction.

Definition at line 392 of file MachineInstr.h.

Referenced by addExclusiveRegPair(), addLiveInRegs(), AnyAliasLiveIn(), llvm::SIInstrInfo::areMemAccessesTriviallyDisjoint(), llvm::SystemZInstrInfo::areMemAccessesTriviallyDisjoint(), llvm::HexagonFrameLowering::assignCalleeSavedSpillSlots(), changeFCMPPredToAArch64CC(), llvm::createX86FixupBWInsts(), emitClzero(), emitComments(), llvm::PPCTargetLowering::emitEHSjLjLongJmp(), llvm::PPCTargetLowering::emitEHSjLjSetJmp(), llvm::PPCHazardRecognizer970::EmitInstruction(), llvm::SITargetLowering::EmitInstrWithCustomInserter(), llvm::ARMTargetLowering::EmitInstrWithCustomInserter(), llvm::TargetLoweringBase::emitPatchPoint(), emitPCMPSTRI(), emitPCMPSTRM(), eraseGPOpnd(), expandLoadStackGuard(), llvm::HexagonInstrInfo::expandPostRAPseudo(), llvm::AArch64InstrInfo::expandPostRAPseudo(), findIncDecAfter(), findPotentialBlockers(), llvm::TargetInstrInfo::foldMemoryOperand(), llvm::SystemZInstrInfo::foldMemoryOperandImpl(), llvm::X86InstrInfo::foldMemoryOperandImpl(), forceReg(), GetDSubRegs(), llvm::PPCHazardRecognizer970::getHazardType(), llvm::ARMBaseInstrInfo::getNumLDMAddresses(), llvm::ARMBaseInstrInfo::getNumMicroOps(), llvm::ARMBaseInstrInfo::getOperandLatency(), getPostIndexedLoadStoreOpcode(), getRetpolineSymbol(), getSmrdOpcode(), getStoreTarget(), getUnderlyingObjects(), hasIdenticalMMOs(), llvm::TargetInstrInfo::hasLoadFromStackSlot(), llvm::TargetInstrInfo::hasStoreToStackSlot(), INITIALIZE_PASS(), InsertFPConstInst(), InsertFPImmInst(), InsertSPConstInst(), InsertSPImmInst(), isInstrUniform(), isMemoryOp(), IsSafeAndProfitableToMove(), llvm::SIInstrInfo::isStackAccess(), llvm::SIInstrInfo::legalizeOperands(), llvm::LegalizerHelper::lower(), lowerVECTOR_SHUFFLE_VSHF(), makeImplicit(), matchPair(), mayAlias(), memoperands(), memOpsHaveSameBasePtr(), mergeMemRefsWith(), llvm::SIInstrInfo::moveToVALU(), llvm::LegalizerHelper::narrowScalar(), offsetsDoNotOverlap(), false::IntervalSorter::operator()(), llvm::ARMBaseInstrInfo::reMaterialize(), removePhis(), ReplaceFrameIndex(), RewriteP2Align(), splitBlock(), llvm::AArch64InstrInfo::suppressLdStPair(), llvm::X86InstrInfo::unfoldMemoryOperand(), updateKillStatus(), VerifyLowRegs(), llvm::LegalizerHelper::widenScalar(), and X86SelectAddress().

◆ memoperands_empty()

bool llvm::MachineInstr::memoperands_empty ( ) const
inline

◆ memoperands_end()

mmo_iterator llvm::MachineInstr::memoperands_end ( ) const
inline

◆ mergeFlagsWith()

uint8_t MachineInstr::mergeFlagsWith ( const MachineInstr Other) const

Return the MIFlags which represent both MachineInstrs.

This should be used when merging two MachineInstrs into one. This routine does not modify the MIFlags of this MachineInstr.

Definition at line 384 of file MachineInstr.cpp.

References AllInBundle, AnyInBundle, assert(), getFlags(), llvm::ilist_node_impl< ilist_detail::compute_node_options< MachineInstr, Options... >::type >::getIterator(), isBundledWithPred(), and llvm::BitmaskEnumDetail::Mask().

Referenced by setMemRefs().

◆ mergeMemRefsWith()

std::pair< MachineInstr::mmo_iterator, unsigned > MachineInstr::mergeMemRefsWith ( const MachineInstr Other)

Return a set of memrefs (begin iterator, size) which conservatively describe the memory behavior of both MachineInstrs.

This is appropriate for use when merging two MachineInstrs into one. This routine does not modify the memrefs of the this MachineInstr.

Definition at line 348 of file MachineInstr.cpp.

References llvm::MachineFunction::allocateMemRefsArray(), assert(), llvm::copy(), getMF(), hasIdenticalMMOs(), memoperands_begin(), memoperands_empty(), and memoperands_end().

Referenced by IsSafeAndProfitableToMove(), and setMemRefs().

◆ modifiesRegister()

bool llvm::MachineInstr::modifiesRegister ( unsigned  Reg,
const TargetRegisterInfo TRI 
) const
inline

◆ operands() [1/2]

iterator_range<mop_iterator> llvm::MachineInstr::operands ( )
inline

Definition at line 335 of file MachineInstr.h.

References llvm::make_range(), operands_begin(), and operands_end().

Referenced by addDefsUsesToList(), addImplicitDefUseOperands(), llvm::LiveIntervals::addKillFlags(), addRegisterDefined(), llvm::ScheduleDAGInstrs::addSchedBarrierDeps(), addToListsIfDependent(), allDefsAreDead(), AnyAliasLiveIn(), BuildInstOrderMap(), callHasRegMask(), llvm::HexagonPacketizerList::canPromoteToNewValueStore(), ClearKillFlags(), clearKillInfo(), clearRegisterDeads(), clearRegisterKills(), collectVirtualRegUses(), llvm::ScheduleDAGMILive::collectVRegUses(), computeLiveOuts(), llvm::createBreakFalseDeps(), definesFullReg(), llvm::HexagonHazardRecognizer::EmitInstruction(), llvm::RegScavenger::enterBasicBlockEnd(), eraseFromParentAndMarkDBGValuesForRemoval(), llvm::HexagonEvaluator::evaluate(), llvm::BitTracker::MachineEvaluator::evaluate(), findCalledFunction(), findSinkableLocalRegDef(), findSurvivorBackwards(), getCalledFunction(), llvm::MachineInstrExpressionTrait::getHashValue(), getNewValueJumpOpcode(), llvm::rdf::DataFlowGraph::getNextShadow(), llvm::AArch64InstrInfo::getOutliningType(), llvm::X86InstrInfo::getOutliningType(), getPostIncrementOperand(), getPredicatedRegister(), getRetOpcode(), getRetpolineSymbol(), getStartOrEndSlot(), handleNormalInst(), llvm::HexagonPacketizerList::hasDeadDependence(), llvm::HexagonPacketizerList::hasRegMaskDependence(), hasWriteToReadDep(), hasYmmOrZmmReg(), INITIALIZE_PASS(), InstructionStoresToFI(), llvm::HexagonPacketizerList::isCallDependent(), isCopyFeedingInvariantStore(), llvm::ARMBaseInstrInfo::isCPSRDefined(), isCrossCopy(), isDebug(), llvm::HexagonInstrInfo::isExtended(), llvm::rdf::TargetOperandInfo::isFixedReg(), isHighLatencyCPSR(), isImplicitDependency(), isInvariantStore(), IsSafeToMove(), llvm::HexagonInstrInfo::isTailCall(), llvm::isTriviallyDead(), isVirtualRegisterOperand(), llvm::AArch64MCInstLower::Lower(), llvm::LowerARMMachineInstrToMCInst(), llvm::AVRMCInstLower::lowerInstruction(), llvm::LowerRISCVMachineInstrToMCInst(), matchPair(), MaySpeculate(), needsStackFrame(), llvm::rdf::operator<<(), llvm::HexagonInstrInfo::predCanBeUsedAsDotNew(), profitImm(), DeadCodeElimination::SetQueue< T >::push_back(), regOverlapsSet(), llvm::X86InstrInfo::reMaterialize(), llvm::rdf::Liveness::resetKills(), llvm::SIRegisterInfo::resolveFrameIndex(), scavengeFrameVirtualRegsInBlock(), llvm::RegScavenger::scavengeRegister(), setPhysRegsDeadExcept(), setRegisterDefReadUndef(), SinkingPreventsImplicitNullCheck(), substituteRegister(), toggleKills(), llvm::TargetInstrInfo::trackRegDefsUses(), unsupportedBinOp(), llvm::LiveIntervals::HMEditor::updateAllRanges(), UpdateCPSRDef(), and UpdateCPSRUse().

◆ operands() [2/2]

iterator_range<const_mop_iterator> llvm::MachineInstr::operands ( ) const
inline

Definition at line 338 of file MachineInstr.h.

References llvm::make_range(), operands_begin(), and operands_end().

◆ operands_begin() [1/2]

mop_iterator llvm::MachineInstr::operands_begin ( )
inline

◆ operands_begin() [2/2]

const_mop_iterator llvm::MachineInstr::operands_begin ( ) const
inline

Definition at line 332 of file MachineInstr.h.

◆ operands_end() [1/2]

mop_iterator llvm::MachineInstr::operands_end ( )
inline

◆ operands_end() [2/2]

const_mop_iterator llvm::MachineInstr::operands_end ( ) const
inline

Definition at line 333 of file MachineInstr.h.

◆ operator=()

MachineInstr& llvm::MachineInstr::operator= ( const MachineInstr )
delete

◆ print() [1/2]

void MachineInstr::print ( raw_ostream OS,
bool  IsStandalone = true,
bool  SkipOpers = false,
bool  SkipDebugLoc = false,
bool  AddNewLine = true,
const TargetInstrInfo TII = nullptr 
) const

Print this MI to OS.

Don't print information that can be inferred from other instructions if IsStandalone is false. It is usually true when only a fragment of the function is printed. Only print the defs and the opcode if SkipOpers is true. Otherwise, also print operands if SkipDebugLoc is true. Otherwise, also print the debug loc, with a terminating newline. TII is used to print the opcode name. If it's not present, but the MI is in a function, the opcode will be printed using the function's TII.

Definition at line 1237 of file MachineInstr.cpp.

References F(), llvm::MachineFunction::getFunction(), llvm::TargetSubtargetInfo::getInstrInfo(), getMFIfAvailable(), llvm::GlobalValue::getParent(), llvm::MachineFunction::getSubtarget(), and llvm::ModuleSlotTracker::incorporateFunction().

Referenced by dump(), llvm::XCoreRegisterInfo::eliminateFrameIndex(), llvm::AMDGPUAsmPrinter::EmitInstruction(), llvm::ARMTargetLowering::EmitInstrWithCustomInserter(), llvm::ARMAsmPrinter::EmitJumpTableTBInst(), llvm::ScheduleDAGInstrs::getGraphNodeLabel(), getRegClassFromGRPhysReg(), getRetOpcode(), llvm::HexagonLowerToMC(), INITIALIZE_PASS(), isRegTiedToDefOperand(), llvm::LegalizerHelper::legalizeInstrStep(), llvm::MSP430MCInstLower::Lower(), llvm::BPFMCInstLower::Lower(), llvm::LanaiMCInstLower::Lower(), llvm::WebAssemblyMCInstLower::Lower(), llvm::AVRMCInstLower::lowerInstruction(), llvm::DiagnosticInfoMIROptimization::MachineArgument::MachineArgument(), multipleIterations(), llvm::operator<<(), llvm::MachineBasicBlock::print(), readsVCCZ(), false::Chain::str(), and llvm::MachineFunction::verify().

◆ print() [2/2]

void MachineInstr::print ( raw_ostream OS,
ModuleSlotTracker MST,
bool  IsStandalone = true,
bool  SkipOpers = false,
bool  SkipDebugLoc = false,
bool  AddNewLine = true,
const TargetInstrInfo TII = nullptr 
) const

Definition at line 1255 of file MachineInstr.cpp.

References llvm::InlineAsm::AD_ATT, llvm::InlineAsm::AD_Intel, assert(), llvm::InlineAsm::Constraint_es, llvm::InlineAsm::Constraint_i, llvm::InlineAsm::Constraint_m, llvm::InlineAsm::Constraint_o, llvm::InlineAsm::Constraint_Q, llvm::InlineAsm::Constraint_R, llvm::InlineAsm::Constraint_S, llvm::InlineAsm::Constraint_T, llvm::InlineAsm::Constraint_Um, llvm::InlineAsm::Constraint_Un, llvm::InlineAsm::Constraint_Uq, llvm::InlineAsm::Constraint_Us, llvm::InlineAsm::Constraint_Ut, llvm::InlineAsm::Constraint_Uv, llvm::InlineAsm::Constraint_Uy, llvm::InlineAsm::Constraint_v, llvm::InlineAsm::Constraint_X, llvm::InlineAsm::Constraint_Z, llvm::InlineAsm::Constraint_ZC, llvm::InlineAsm::Constraint_Zy, Context, llvm::dyn_cast(), llvm::InlineAsm::Extra_HasSideEffects, llvm::InlineAsm::Extra_IsAlignStack, llvm::InlineAsm::Extra_IsConvergent, llvm::InlineAsm::Extra_MayLoad, llvm::InlineAsm::Extra_MayStore, findTiedOperandIdx(), FrameDestroy, FrameSetup, llvm::Function::getContext(), getDebugLoc(), getFlag(), llvm::MachineFunction::getFrameInfo(), llvm::MachineFunction::getFunction(), llvm::MachineOperand::getImm(), getInlineAsmDialect(), llvm::InlineAsm::getKind(), llvm::InlineAsm::getMemoryConstraintID(), llvm::MachineOperand::getMetadata(), getMFIfAvailable(), llvm::MCInstrInfo::getName(), llvm::InlineAsm::getNumOperandRegisters(), getNumOperands(), getOpcode(), getOperand(), llvm::TargetRegisterInfo::getRegClass(), llvm::TargetRegisterInfo::getRegClassName(), getTypeToPrint(), hasComplexRegisterTies(), llvm::InlineAsm::hasRegClassConstraint(), isCFIInstruction(), isDebugValue(), llvm::MachineOperand::isDef(), llvm::MachineOperand::isImm(), llvm::InlineAsm::isImmKind(), llvm::MachineOperand::isImplicit(), isIndirectDebugValue(), isInlineAsm(), llvm::InlineAsm::isMemKind(), llvm::MachineOperand::isMetadata(), isOperandSubregIdx(), llvm::MachineOperand::isReg(), llvm::MachineOperand::isTied(), llvm::InlineAsm::isUseOperandTiedToDef(), llvm::InlineAsm::Kind_Clobber, llvm::InlineAsm::Kind_Imm, llvm::InlineAsm::Kind_Mem, llvm::InlineAsm::Kind_RegDef, llvm::InlineAsm::Kind_RegDefEarlyClobber, llvm::InlineAsm::Kind_RegUse, memoperands(), memoperands_empty(), llvm::InlineAsm::MIOp_AsmString, llvm::InlineAsm::MIOp_ExtraInfo, llvm::InlineAsm::MIOp_FirstOperand, llvm::DebugLoc::print(), llvm::MachineOperand::print(), llvm::MachineOperand::printSubRegIdx(), and tryToGetTargetInfo().

◆ readsRegister()

bool llvm::MachineInstr::readsRegister ( unsigned  Reg,
const TargetRegisterInfo TRI = nullptr 
) const
inline

◆ readsVirtualRegister()

bool llvm::MachineInstr::readsVirtualRegister ( unsigned  Reg) const
inline

Return true if the MachineInstr reads the specified virtual register.

Take into account that a partial define is a read-modify-write operation.

Definition at line 940 of file MachineInstr.h.

References readsWritesVirtualRegister().

Referenced by llvm::LiveRangeEdit::eraseVirtReg(), llvm::ARMBaseInstrInfo::getPartialRegUpdateClearance(), llvm::X86InstrInfo::getPartialRegUpdateClearance(), INITIALIZE_PASS(), llvm::SplitEditor::leaveIntvAfter(), and llvm::TargetInstrInfo::trackRegDefsUses().

◆ readsWritesVirtualRegister()

std::pair< bool, bool > MachineInstr::readsWritesVirtualRegister ( unsigned  Reg,
SmallVectorImpl< unsigned > *  Ops = nullptr 
) const

Return a pair of bools (reads, writes) indicating if this instruction reads or writes Reg.

readsWritesVirtualRegister - Return a pair of bools (reads, writes) indicating if this instruction reads or writes Reg.

This also considers partial defines. If Ops is not null, all operand indices for Reg are added.

This also considers partial defines.

Definition at line 760 of file MachineInstr.cpp.

References getNumOperands(), getOperand(), llvm::MachineOperand::getReg(), llvm::MachineOperand::getSubReg(), llvm::MachineOperand::isReg(), llvm::MachineOperand::isUndef(), llvm::MachineOperand::isUse(), and llvm::SmallVectorTemplateBase< T, isPodLike >::push_back().

Referenced by llvm::LiveRangeEdit::eraseVirtReg(), readsVirtualRegister(), and llvm::VirtRegAuxInfo::weightCalcHelper().

◆ registerDefIsDead()

bool llvm::MachineInstr::registerDefIsDead ( unsigned  Reg,
const TargetRegisterInfo TRI = nullptr 
) const
inline

Returns true if the register is dead in this machine instruction.

If TargetRegisterInfo is passed, then it also checks if there is a dead def of a super-register.

Definition at line 977 of file MachineInstr.h.

References findRegisterDefOperandIdx(), findRegisterUseOperandIdx(), hasRegisterImplicitUseOperand(), and isKill().

Referenced by llvm::ScheduleDAGInstrs::addPhysRegDeps(), forceReg(), llvm::X86InstrInfo::optimizeCompareInstr(), and transferDeadCC().

◆ removeFromBundle()

MachineInstr * MachineInstr::removeFromBundle ( )

Unlink this instruction from its basic block and return it without deleting it.

If the instruction is part of a bundle, the other instructions in the bundle remain bundled.

Definition at line 486 of file MachineInstr.cpp.

References assert(), getParent(), and llvm::MachineBasicBlock::remove_instr().

◆ removeFromParent()

MachineInstr * MachineInstr::removeFromParent ( )

Unlink 'this' from the containing basic block, and return it without deleting it.

This function can not be used on bundled instructions, use removeFromBundle() to remove individual instructions from a bundle.

Definition at line 481 of file MachineInstr.cpp.

References assert(), getParent(), and llvm::MachineBasicBlock::remove().

Referenced by llvm::createX86OptimizeLEAs(), HasArgumentDef(), llvm::SIInstrInfo::legalizeOperands(), llvm::ARMBaseInstrInfo::optimizeCompareInstr(), and readsVCCZ().

◆ RemoveOperand()

void MachineInstr::RemoveOperand ( unsigned  i)

Erase an operand from an instruction, leaving it with one fewer operand than it started with.

RemoveOperand - Erase an operand from an instruction, leaving it with one fewer operand than it started with.

Definition at line 293 of file MachineInstr.cpp.

References assert(), getNumOperands(), isReg(), moveOperands(), N, llvm::MachineRegisterInfo::removeRegOperandFromUseList(), and untieRegOperand().

Referenced by addRegisterDead(), addRegisterKilled(), llvm::SITargetLowering::AdjustInstrPostInstrSelection(), llvm::ARMTargetLowering::AdjustInstrPostInstrSelection(), llvm::SIInstrInfo::buildExtractSubRegOrImm(), llvm::createSIWholeQuadModePass(), dumpMachineInstrRangeWithSlotIndex(), llvm::HexagonRegisterInfo::eliminateFrameIndex(), eraseGPOpnd(), llvm::LiveRangeEdit::eraseVirtReg(), llvm::ARMBaseInstrInfo::expandPostRAPseudo(), llvm::PPCInstrInfo::expandPostRAPseudo(), llvm::X86InstrInfo::expandPostRAPseudo(), llvm::SIInstrInfo::FoldImmediate(), llvm::MipsInstrInfo::genInstrWithNewOpc(), getCompareSourceReg(), getLeaOP(), getRegsUsedByPHIs(), INITIALIZE_PASS(), isCompareZero(), isImmValidForOpcode(), isSimpleIf(), llvm::SIInstrInfo::moveToVALU(), llvm::AArch64InstrInfo::optimizeCompareInstr(), llvm::PPCInstrInfo::optimizeCompareInstr(), llvm::X86InstrInfo::optimizeCompareInstr(), llvm::SystemZInstrInfo::PredicateInstruction(), llvm::HexagonInstrInfo::PredicateInstruction(), llvm::PPCInstrInfo::PredicateInstruction(), regOverlapsSet(), removeModOperands(), removeOperands(), llvm::PPCInstrInfo::replaceInstrWithLI(), llvm::rewriteARMFrameIndex(), llvm::rewriteT2FrameIndex(), setDebugLoc(), llvm::ARMBaseInstrInfo::setExecutionDomain(), stripExtraCopyOperands(), swapMIOperands(), tieOpsIfNeeded(), tryConstantFoldOp(), tryFoldInst(), llvm::tryFoldSPUpdateIntoPushPop(), and X86SelectAddress().

◆ setAsmPrinterFlag()

void llvm::MachineInstr::setAsmPrinterFlag ( uint8_t  Flag)
inline

Set a flag for the AsmPrinter.

Definition at line 168 of file MachineInstr.h.

Referenced by llvm::AsmPrinter::EmitFunctionBody(), and performCustomAdjustments().

◆ setDebugLoc()

void llvm::MachineInstr::setDebugLoc ( DebugLoc  dl)
inline

Replace current source information with new such.

Avoid using this, the constructor argument is preferable.

Definition at line 1284 of file MachineInstr.h.

References addMemOperand(), assert(), llvm::DebugLoc::hasTrivialDestructor(), and RemoveOperand().

Referenced by definesFullReg(), expandLoadStackGuard(), INITIALIZE_PASS(), isCopyFeedingInvariantStore(), isRegUsedByPhiNodes(), and SinkingPreventsImplicitNullCheck().

◆ setDesc()

void llvm::MachineInstr::setDesc ( const MCInstrDesc tid)
inline

Replace the instruction descriptor (thus opcode) of the current instruction with a new one.

Definition at line 1280 of file MachineInstr.h.

Referenced by llvm::SITargetLowering::AdjustInstrPostInstrSelection(), llvm::ARMTargetLowering::AdjustInstrPostInstrSelection(), llvm::AMDGPUInstructionSelector::AMDGPUInstructionSelector(), BBIsJumpedOver(), canInstrSubstituteCmpInstr(), canTurnIntoCOPY(), changeFCMPPredToAArch64CC(), llvm::HexagonPacketizerList::cleanUpDotCur(), llvm::SIInstrInfo::commuteInstructionImpl(), ConvertImplicitDefToConstZero(), llvm::createSIWholeQuadModePass(), llvm::HexagonPacketizerList::demoteToDotOld(), llvm::MSP430RegisterInfo::eliminateFrameIndex(), llvm::SparcRegisterInfo::eliminateFrameIndex(), llvm::LanaiRegisterInfo::eliminateFrameIndex(), llvm::AVRRegisterInfo::eliminateFrameIndex(), llvm::HexagonRegisterInfo::eliminateFrameIndex(), llvm::ThumbRegisterInfo::eliminateFrameIndex(), llvm::PPCRegisterInfo::eliminateFrameIndex(), llvm::ARMTargetLowering::EmitInstrWithCustomInserter(), llvm::LiveRangeEdit::eraseVirtReg(), Expand2AddrKreg(), Expand2AddrUndef(), expandLoadStackGuard(), expandMOV32r1(), ExpandMOVImmSExti8(), expandNOVLXLoad(), expandNOVLXStore(), llvm::SparcInstrInfo::expandPostRAPseudo(), llvm::SIInstrInfo::expandPostRAPseudo(), llvm::HexagonInstrInfo::expandPostRAPseudo(), llvm::ARMBaseInstrInfo::expandPostRAPseudo(), llvm::SystemZInstrInfo::expandPostRAPseudo(), llvm::PPCInstrInfo::expandPostRAPseudo(), llvm::X86InstrInfo::expandPostRAPseudo(), llvm::PPCInstrInfo::expandVSXMemPseudo(), expandXorFP(), llvm::fixStackStores(), llvm::SystemZInstrInfo::FoldImmediate(), llvm::SIInstrInfo::FoldImmediate(), llvm::ARMBaseInstrInfo::FoldImmediate(), llvm::X86InstrInfo::foldMemoryOperandImpl(), forceReg(), getCompareSourceReg(), getLeaOP(), getRegClassFromGRPhysReg(), getRetpolineSymbol(), getUnconditionalBrDisp(), hoistAndMergeSGPRInits(), ImmInRange(), INITIALIZE_PASS(), InsertLDR_STR(), llvm::HexagonInstrInfo::invertAndChangeJumpTarget(), isCompareZero(), isFullCopyOf(), isSimpleIf(), IsUnconditionalJump(), isUseSafeToFold(), llvm::SIInstrInfo::legalizeOperandsVOP2(), MaybeRewriteToFallthrough(), llvm::SIInstrInfo::moveToVALU(), mutateCopyOp(), llvm::LanaiInstrInfo::optimizeCompareInstr(), llvm::AArch64InstrInfo::optimizeCompareInstr(), llvm::PPCInstrInfo::optimizeCompareInstr(), llvm::X86InstrInfo::optimizeCompareInstr(), performCustomAdjustments(), llvm::ARMBaseInstrInfo::PredicateInstruction(), llvm::SystemZInstrInfo::PredicateInstruction(), llvm::HexagonInstrInfo::PredicateInstruction(), llvm::PPCInstrInfo::PredicateInstruction(), llvm::HexagonPacketizerList::promoteToDotCur(), llvm::HexagonPacketizerList::promoteToDotNew(), registerDefinedBetween(), regOverlapsSet(), removeTerminatorBit(), llvm::PPCInstrInfo::replaceInstrWithLI(), llvm::HexagonInstrInfo::reversePredSense(), llvm::rewriteAArch64FrameIndex(), llvm::rewriteARMFrameIndex(), llvm::ThumbRegisterInfo::rewriteFrameIndex(), llvm::rewriteT2FrameIndex(), selectCopy(), selectMergeValues(), selectUnmergeValues(), llvm::ARMBaseInstrInfo::setExecutionDomain(), llvm::X86InstrInfo::setExecutionDomain(), llvm::X86InstrInfo::setExecutionDomainCustom(), shrinkScalarCompare(), splitBlock(), llvm::SITargetLowering::splitKillBlock(), swapMIOperands(), llvm::SystemZInstrInfo::SystemZInstrInfo(), tieOpsIfNeeded(), tryAddToFoldList(), llvm::X86InstrInfo::unfoldMemoryOperand(), and X86SelectAddress().

◆ setFlag()

void llvm::MachineInstr::setFlag ( MIFlag  Flag)
inline

◆ setFlags()

void llvm::MachineInstr::setFlags ( unsigned  flags)
inline

◆ setMemRefs() [1/2]

void llvm::MachineInstr::setMemRefs ( mmo_iterator  NewMemRefs,
mmo_iterator  NewMemRefsEnd 
)
inline

◆ setMemRefs() [2/2]

void llvm::MachineInstr::setMemRefs ( std::pair< mmo_iterator, unsigned NewMemRefs)
inline

Assign this MachineInstr's memory reference descriptor list.

First element in the pair is the begin iterator/pointer to the array; the second is the number of MemoryOperands. This does not transfer ownership of the underlying memory.

Definition at line 1308 of file MachineInstr.h.

References assert(), mergeFlagsWith(), and mergeMemRefsWith().

◆ setPhysRegsDeadExcept()

void MachineInstr::setPhysRegsDeadExcept ( ArrayRef< unsigned UsedRegs,
const TargetRegisterInfo TRI 
)

Mark every physreg used by this instruction as dead except those in the UsedRegs list.

On instructions with register mask operands, also add implicit-def operands for all registers in UsedRegs.

Definition at line 1659 of file MachineInstr.cpp.

References addRegisterDefined(), llvm::ArrayRef< T >::begin(), E, llvm::ArrayRef< T >::end(), I, llvm::TargetRegisterInfo::isPhysicalRegister(), llvm::none_of(), operands(), and llvm::TargetRegisterInfo::regsOverlap().

Referenced by isRegTiedToDefOperand(), llvm::FastISel::lowerCallTo(), and llvm::FastISel::selectPatchpoint().

◆ setRegisterDefReadUndef()

void MachineInstr::setRegisterDefReadUndef ( unsigned  Reg,
bool  IsUndef = true 
)

Mark all subregister defs of register Reg with the undef flag.

This function is used when we determined to have a subregister def in an otherwise undefined super register.

Definition at line 1633 of file MachineInstr.cpp.

References operands().

Referenced by llvm::RegisterOperands::adjustLaneLiveness(), isRegTiedToDefOperand(), and llvm::LiveIntervals::shrinkToUses().

◆ substituteRegister()

void MachineInstr::substituteRegister ( unsigned  FromReg,
unsigned  ToReg,
unsigned  SubIdx,
const TargetRegisterInfo RegInfo 
)

◆ tieOperands()

void MachineInstr::tieOperands ( unsigned  DefIdx,
unsigned  UseIdx 
)

Add a tie between the register operands at DefIdx and UseIdx.

tieOperands - Mark operands at DefIdx and UseIdx as tied to each other.

The tie will cause the register allocator to ensure that the two operands are assigned the same physical register.

Tied operands are managed automatically for explicit operands in the MCInstrDesc. This method is for exceptional cases like inline asm.

Use and def operands can be tied together, indicated by a non-zero TiedTo field. TiedTo can have these values:

0: Operand is not tied to anything. 1 to TiedMax-1: Tied to getOperand(TiedTo-1). TiedMax: Tied to an operand >= TiedMax-1.

The tied def must be one of the first TiedMax operands on a normal instruction. INLINEASM instructions allow more tied defs.

Definition at line 848 of file MachineInstr.cpp.

References assert(), getOperand(), llvm::MachineOperand::isDef(), isInlineAsm(), llvm::MachineOperand::isTied(), llvm::MachineOperand::isUse(), and TiedMax.

Referenced by addOperand(), llvm::ARMTargetLowering::AdjustInstrPostInstrSelection(), llvm::constrainSelectedInstRegOperands(), llvm::InstrEmitter::EmitDbgValue(), findRegisterDefOperand(), findSingleRegDef(), isImplicitOperandIn(), llvm::LanaiInstrInfo::optimizeSelect(), llvm::ARMBaseInstrInfo::optimizeSelect(), removePhis(), shrinkScalarCompare(), llvm::SystemZInstrInfo::SystemZInstrInfo(), and tieOpsIfNeeded().

◆ unbundleFromPred()

void MachineInstr::unbundleFromPred ( )

◆ unbundleFromSucc()

void MachineInstr::unbundleFromSucc ( )

◆ untieRegOperand()

void llvm::MachineInstr::untieRegOperand ( unsigned  OpIdx)
inline

◆ uses() [1/2]

iterator_range<mop_iterator> llvm::MachineInstr::uses ( )
inline

Returns a range that includes all operands that are register uses.

This may include unrelated operands which are not register uses.

Definition at line 368 of file MachineInstr.h.

References getDesc(), llvm::make_range(), operands_begin(), and operands_end().

Referenced by addRegsToSet(), AnyAliasLiveIn(), ContainsReg(), llvm::createSIWholeQuadModePass(), findSingleRegDef(), handleNormalInst(), isCrossCopy(), matchPair(), split(), and false::Chain::str().

◆ uses() [2/2]

iterator_range<const_mop_iterator> llvm::MachineInstr::uses ( ) const
inline

Returns a range that includes all operands that are register uses.

This may include unrelated operands which are not register uses.

Definition at line 373 of file MachineInstr.h.

References getDesc(), llvm::make_range(), operands_begin(), and operands_end().

◆ usesCustomInsertionHook()

bool llvm::MachineInstr::usesCustomInsertionHook ( QueryType  Type = IgnoreBundle) const
inline

Return true if this instruction requires custom insertion support when the DAG scheduler is inserting it into a machine basic block.

If this is true for the instruction, it basically means that it is a pseudo instruction used at SelectionDAG time that is expanded out into magic code by the target when MachineInstrs are formed.

If this is true, the TargetLoweringInfo::InsertAtEndOfBasicBlock method is used to insert this into the MachineBasicBlock.

Definition at line 700 of file MachineInstr.h.

References hasProperty(), and llvm::MCID::UsesCustomInserter.

Referenced by INITIALIZE_PASS().

Friends And Related Function Documentation

◆ ilist_callback_traits< MachineBasicBlock >

friend struct ilist_callback_traits< MachineBasicBlock >
friend

Definition at line 120 of file MachineInstr.h.

◆ ilist_traits< MachineInstr >

friend struct ilist_traits< MachineInstr >
friend

Definition at line 119 of file MachineInstr.h.

◆ MachineFunction

friend class MachineFunction
friend

Definition at line 134 of file MachineInstr.h.


The documentation for this class was generated from the following files: