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SystemZInstrInfo.cpp
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1 //===-- SystemZInstrInfo.cpp - SystemZ instruction information ------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the SystemZ implementation of the TargetInstrInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "SystemZInstrInfo.h"
16 #include "SystemZ.h"
17 #include "SystemZInstrBuilder.h"
18 #include "SystemZSubtarget.h"
19 #include "llvm/ADT/Statistic.h"
33 #include "llvm/MC/MCInstrDesc.h"
34 #include "llvm/MC/MCRegisterInfo.h"
39 #include <cassert>
40 #include <cstdint>
41 #include <iterator>
42 
43 using namespace llvm;
44 
45 #define GET_INSTRINFO_CTOR_DTOR
46 #define GET_INSTRMAP_INFO
47 #include "SystemZGenInstrInfo.inc"
48 
49 #define DEBUG_TYPE "systemz-II"
50 STATISTIC(LOCRMuxJumps, "Number of LOCRMux jump-sequences (lower is better)");
51 
52 // Return a mask with Count low bits set.
53 static uint64_t allOnes(unsigned int Count) {
54  return Count == 0 ? 0 : (uint64_t(1) << (Count - 1) << 1) - 1;
55 }
56 
57 // Reg should be a 32-bit GPR. Return true if it is a high register rather
58 // than a low register.
59 static bool isHighReg(unsigned int Reg) {
60  if (SystemZ::GRH32BitRegClass.contains(Reg))
61  return true;
62  assert(SystemZ::GR32BitRegClass.contains(Reg) && "Invalid GRX32");
63  return false;
64 }
65 
66 // Pin the vtable to this file.
67 void SystemZInstrInfo::anchor() {}
68 
70  : SystemZGenInstrInfo(SystemZ::ADJCALLSTACKDOWN, SystemZ::ADJCALLSTACKUP),
71  RI(), STI(sti) {
72 }
73 
74 // MI is a 128-bit load or store. Split it into two 64-bit loads or stores,
75 // each having the opcode given by NewOpcode.
76 void SystemZInstrInfo::splitMove(MachineBasicBlock::iterator MI,
77  unsigned NewOpcode) const {
78  MachineBasicBlock *MBB = MI->getParent();
79  MachineFunction &MF = *MBB->getParent();
80 
81  // Get two load or store instructions. Use the original instruction for one
82  // of them (arbitrarily the second here) and create a clone for the other.
83  MachineInstr *EarlierMI = MF.CloneMachineInstr(&*MI);
84  MBB->insert(MI, EarlierMI);
85 
86  // Set up the two 64-bit registers and remember super reg and its flags.
87  MachineOperand &HighRegOp = EarlierMI->getOperand(0);
88  MachineOperand &LowRegOp = MI->getOperand(0);
89  unsigned Reg128 = LowRegOp.getReg();
90  unsigned Reg128Killed = getKillRegState(LowRegOp.isKill());
91  unsigned Reg128Undef = getUndefRegState(LowRegOp.isUndef());
92  HighRegOp.setReg(RI.getSubReg(HighRegOp.getReg(), SystemZ::subreg_h64));
93  LowRegOp.setReg(RI.getSubReg(LowRegOp.getReg(), SystemZ::subreg_l64));
94 
95  if (MI->mayStore()) {
96  // Add implicit uses of the super register in case one of the subregs is
97  // undefined. We could track liveness and skip storing an undefined
98  // subreg, but this is hopefully rare (discovered with llvm-stress).
99  // If Reg128 was killed, set kill flag on MI.
100  unsigned Reg128UndefImpl = (Reg128Undef | RegState::Implicit);
101  MachineInstrBuilder(MF, EarlierMI).addReg(Reg128, Reg128UndefImpl);
102  MachineInstrBuilder(MF, MI).addReg(Reg128, (Reg128UndefImpl | Reg128Killed));
103  }
104 
105  // The address in the first (high) instruction is already correct.
106  // Adjust the offset in the second (low) instruction.
107  MachineOperand &HighOffsetOp = EarlierMI->getOperand(2);
108  MachineOperand &LowOffsetOp = MI->getOperand(2);
109  LowOffsetOp.setImm(LowOffsetOp.getImm() + 8);
110 
111  // Clear the kill flags on the registers in the first instruction.
112  if (EarlierMI->getOperand(0).isReg() && EarlierMI->getOperand(0).isUse())
113  EarlierMI->getOperand(0).setIsKill(false);
114  EarlierMI->getOperand(1).setIsKill(false);
115  EarlierMI->getOperand(3).setIsKill(false);
116 
117  // Set the opcodes.
118  unsigned HighOpcode = getOpcodeForOffset(NewOpcode, HighOffsetOp.getImm());
119  unsigned LowOpcode = getOpcodeForOffset(NewOpcode, LowOffsetOp.getImm());
120  assert(HighOpcode && LowOpcode && "Both offsets should be in range");
121 
122  EarlierMI->setDesc(get(HighOpcode));
123  MI->setDesc(get(LowOpcode));
124 }
125 
126 // Split ADJDYNALLOC instruction MI.
127 void SystemZInstrInfo::splitAdjDynAlloc(MachineBasicBlock::iterator MI) const {
128  MachineBasicBlock *MBB = MI->getParent();
129  MachineFunction &MF = *MBB->getParent();
130  MachineFrameInfo &MFFrame = MF.getFrameInfo();
131  MachineOperand &OffsetMO = MI->getOperand(2);
132 
133  uint64_t Offset = (MFFrame.getMaxCallFrameSize() +
135  OffsetMO.getImm());
136  unsigned NewOpcode = getOpcodeForOffset(SystemZ::LA, Offset);
137  assert(NewOpcode && "No support for huge argument lists yet");
138  MI->setDesc(get(NewOpcode));
139  OffsetMO.setImm(Offset);
140 }
141 
142 // MI is an RI-style pseudo instruction. Replace it with LowOpcode
143 // if the first operand is a low GR32 and HighOpcode if the first operand
144 // is a high GR32. ConvertHigh is true if LowOpcode takes a signed operand
145 // and HighOpcode takes an unsigned 32-bit operand. In those cases,
146 // MI has the same kind of operand as LowOpcode, so needs to be converted
147 // if HighOpcode is used.
148 void SystemZInstrInfo::expandRIPseudo(MachineInstr &MI, unsigned LowOpcode,
149  unsigned HighOpcode,
150  bool ConvertHigh) const {
151  unsigned Reg = MI.getOperand(0).getReg();
152  bool IsHigh = isHighReg(Reg);
153  MI.setDesc(get(IsHigh ? HighOpcode : LowOpcode));
154  if (IsHigh && ConvertHigh)
155  MI.getOperand(1).setImm(uint32_t(MI.getOperand(1).getImm()));
156 }
157 
158 // MI is a three-operand RIE-style pseudo instruction. Replace it with
159 // LowOpcodeK if the registers are both low GR32s, otherwise use a move
160 // followed by HighOpcode or LowOpcode, depending on whether the target
161 // is a high or low GR32.
162 void SystemZInstrInfo::expandRIEPseudo(MachineInstr &MI, unsigned LowOpcode,
163  unsigned LowOpcodeK,
164  unsigned HighOpcode) const {
165  unsigned DestReg = MI.getOperand(0).getReg();
166  unsigned SrcReg = MI.getOperand(1).getReg();
167  bool DestIsHigh = isHighReg(DestReg);
168  bool SrcIsHigh = isHighReg(SrcReg);
169  if (!DestIsHigh && !SrcIsHigh)
170  MI.setDesc(get(LowOpcodeK));
171  else {
172  emitGRX32Move(*MI.getParent(), MI, MI.getDebugLoc(), DestReg, SrcReg,
173  SystemZ::LR, 32, MI.getOperand(1).isKill(),
174  MI.getOperand(1).isUndef());
175  MI.setDesc(get(DestIsHigh ? HighOpcode : LowOpcode));
176  MI.getOperand(1).setReg(DestReg);
177  MI.tieOperands(0, 1);
178  }
179 }
180 
181 // MI is an RXY-style pseudo instruction. Replace it with LowOpcode
182 // if the first operand is a low GR32 and HighOpcode if the first operand
183 // is a high GR32.
184 void SystemZInstrInfo::expandRXYPseudo(MachineInstr &MI, unsigned LowOpcode,
185  unsigned HighOpcode) const {
186  unsigned Reg = MI.getOperand(0).getReg();
187  unsigned Opcode = getOpcodeForOffset(isHighReg(Reg) ? HighOpcode : LowOpcode,
188  MI.getOperand(2).getImm());
189  MI.setDesc(get(Opcode));
190 }
191 
192 // MI is a load-on-condition pseudo instruction with a single register
193 // (source or destination) operand. Replace it with LowOpcode if the
194 // register is a low GR32 and HighOpcode if the register is a high GR32.
195 void SystemZInstrInfo::expandLOCPseudo(MachineInstr &MI, unsigned LowOpcode,
196  unsigned HighOpcode) const {
197  unsigned Reg = MI.getOperand(0).getReg();
198  unsigned Opcode = isHighReg(Reg) ? HighOpcode : LowOpcode;
199  MI.setDesc(get(Opcode));
200 }
201 
202 // MI is a load-register-on-condition pseudo instruction. Replace it with
203 // LowOpcode if source and destination are both low GR32s and HighOpcode if
204 // source and destination are both high GR32s.
205 void SystemZInstrInfo::expandLOCRPseudo(MachineInstr &MI, unsigned LowOpcode,
206  unsigned HighOpcode) const {
207  unsigned DestReg = MI.getOperand(0).getReg();
208  unsigned SrcReg = MI.getOperand(2).getReg();
209  bool DestIsHigh = isHighReg(DestReg);
210  bool SrcIsHigh = isHighReg(SrcReg);
211 
212  if (!DestIsHigh && !SrcIsHigh)
213  MI.setDesc(get(LowOpcode));
214  else if (DestIsHigh && SrcIsHigh)
215  MI.setDesc(get(HighOpcode));
216  else
217  LOCRMuxJumps++;
218 
219  // If we were unable to implement the pseudo with a single instruction, we
220  // need to convert it back into a branch sequence. This cannot be done here
221  // since the caller of expandPostRAPseudo does not handle changes to the CFG
222  // correctly. This change is defered to the SystemZExpandPseudo pass.
223 }
224 
225 // MI is an RR-style pseudo instruction that zero-extends the low Size bits
226 // of one GRX32 into another. Replace it with LowOpcode if both operands
227 // are low registers, otherwise use RISB[LH]G.
228 void SystemZInstrInfo::expandZExtPseudo(MachineInstr &MI, unsigned LowOpcode,
229  unsigned Size) const {
230  MachineInstrBuilder MIB =
231  emitGRX32Move(*MI.getParent(), MI, MI.getDebugLoc(),
232  MI.getOperand(0).getReg(), MI.getOperand(1).getReg(), LowOpcode,
233  Size, MI.getOperand(1).isKill(), MI.getOperand(1).isUndef());
234 
235  // Keep the remaining operands as-is.
236  for (unsigned I = 2; I < MI.getNumOperands(); ++I)
237  MIB.add(MI.getOperand(I));
238 
239  MI.eraseFromParent();
240 }
241 
242 void SystemZInstrInfo::expandLoadStackGuard(MachineInstr *MI) const {
243  MachineBasicBlock *MBB = MI->getParent();
244  MachineFunction &MF = *MBB->getParent();
245  const unsigned Reg64 = MI->getOperand(0).getReg();
246  const unsigned Reg32 = RI.getSubReg(Reg64, SystemZ::subreg_l32);
247 
248  // EAR can only load the low subregister so us a shift for %a0 to produce
249  // the GR containing %a0 and %a1.
250 
251  // ear <reg>, %a0
252  BuildMI(*MBB, MI, MI->getDebugLoc(), get(SystemZ::EAR), Reg32)
253  .addReg(SystemZ::A0)
255 
256  // sllg <reg>, <reg>, 32
257  BuildMI(*MBB, MI, MI->getDebugLoc(), get(SystemZ::SLLG), Reg64)
258  .addReg(Reg64)
259  .addReg(0)
260  .addImm(32);
261 
262  // ear <reg>, %a1
263  BuildMI(*MBB, MI, MI->getDebugLoc(), get(SystemZ::EAR), Reg32)
264  .addReg(SystemZ::A1);
265 
266  // lg <reg>, 40(<reg>)
267  MI->setDesc(get(SystemZ::LG));
268  MachineInstrBuilder(MF, MI).addReg(Reg64).addImm(40).addReg(0);
269 }
270 
271 // Emit a zero-extending move from 32-bit GPR SrcReg to 32-bit GPR
272 // DestReg before MBBI in MBB. Use LowLowOpcode when both DestReg and SrcReg
273 // are low registers, otherwise use RISB[LH]G. Size is the number of bits
274 // taken from the low end of SrcReg (8 for LLCR, 16 for LLHR and 32 for LR).
275 // KillSrc is true if this move is the last use of SrcReg.
277 SystemZInstrInfo::emitGRX32Move(MachineBasicBlock &MBB,
279  const DebugLoc &DL, unsigned DestReg,
280  unsigned SrcReg, unsigned LowLowOpcode,
281  unsigned Size, bool KillSrc,
282  bool UndefSrc) const {
283  unsigned Opcode;
284  bool DestIsHigh = isHighReg(DestReg);
285  bool SrcIsHigh = isHighReg(SrcReg);
286  if (DestIsHigh && SrcIsHigh)
287  Opcode = SystemZ::RISBHH;
288  else if (DestIsHigh && !SrcIsHigh)
289  Opcode = SystemZ::RISBHL;
290  else if (!DestIsHigh && SrcIsHigh)
291  Opcode = SystemZ::RISBLH;
292  else {
293  return BuildMI(MBB, MBBI, DL, get(LowLowOpcode), DestReg)
294  .addReg(SrcReg, getKillRegState(KillSrc) | getUndefRegState(UndefSrc));
295  }
296  unsigned Rotate = (DestIsHigh != SrcIsHigh ? 32 : 0);
297  return BuildMI(MBB, MBBI, DL, get(Opcode), DestReg)
298  .addReg(DestReg, RegState::Undef)
299  .addReg(SrcReg, getKillRegState(KillSrc) | getUndefRegState(UndefSrc))
300  .addImm(32 - Size).addImm(128 + 31).addImm(Rotate);
301 }
302 
304  bool NewMI,
305  unsigned OpIdx1,
306  unsigned OpIdx2) const {
307  auto cloneIfNew = [NewMI](MachineInstr &MI) -> MachineInstr & {
308  if (NewMI)
309  return *MI.getParent()->getParent()->CloneMachineInstr(&MI);
310  return MI;
311  };
312 
313  switch (MI.getOpcode()) {
314  case SystemZ::LOCRMux:
315  case SystemZ::LOCFHR:
316  case SystemZ::LOCR:
317  case SystemZ::LOCGR: {
318  auto &WorkingMI = cloneIfNew(MI);
319  // Invert condition.
320  unsigned CCValid = WorkingMI.getOperand(3).getImm();
321  unsigned CCMask = WorkingMI.getOperand(4).getImm();
322  WorkingMI.getOperand(4).setImm(CCMask ^ CCValid);
323  return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
324  OpIdx1, OpIdx2);
325  }
326  default:
327  return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
328  }
329 }
330 
331 // If MI is a simple load or store for a frame object, return the register
332 // it loads or stores and set FrameIndex to the index of the frame object.
333 // Return 0 otherwise.
334 //
335 // Flag is SimpleBDXLoad for loads and SimpleBDXStore for stores.
336 static int isSimpleMove(const MachineInstr &MI, int &FrameIndex,
337  unsigned Flag) {
338  const MCInstrDesc &MCID = MI.getDesc();
339  if ((MCID.TSFlags & Flag) && MI.getOperand(1).isFI() &&
340  MI.getOperand(2).getImm() == 0 && MI.getOperand(3).getReg() == 0) {
341  FrameIndex = MI.getOperand(1).getIndex();
342  return MI.getOperand(0).getReg();
343  }
344  return 0;
345 }
346 
348  int &FrameIndex) const {
349  return isSimpleMove(MI, FrameIndex, SystemZII::SimpleBDXLoad);
350 }
351 
353  int &FrameIndex) const {
354  return isSimpleMove(MI, FrameIndex, SystemZII::SimpleBDXStore);
355 }
356 
358  int &DestFrameIndex,
359  int &SrcFrameIndex) const {
360  // Check for MVC 0(Length,FI1),0(FI2)
361  const MachineFrameInfo &MFI = MI.getParent()->getParent()->getFrameInfo();
362  if (MI.getOpcode() != SystemZ::MVC || !MI.getOperand(0).isFI() ||
363  MI.getOperand(1).getImm() != 0 || !MI.getOperand(3).isFI() ||
364  MI.getOperand(4).getImm() != 0)
365  return false;
366 
367  // Check that Length covers the full slots.
368  int64_t Length = MI.getOperand(2).getImm();
369  unsigned FI1 = MI.getOperand(0).getIndex();
370  unsigned FI2 = MI.getOperand(3).getIndex();
371  if (MFI.getObjectSize(FI1) != Length ||
372  MFI.getObjectSize(FI2) != Length)
373  return false;
374 
375  DestFrameIndex = FI1;
376  SrcFrameIndex = FI2;
377  return true;
378 }
379 
381  MachineBasicBlock *&TBB,
382  MachineBasicBlock *&FBB,
384  bool AllowModify) const {
385  // Most of the code and comments here are boilerplate.
386 
387  // Start from the bottom of the block and work up, examining the
388  // terminator instructions.
390  while (I != MBB.begin()) {
391  --I;
392  if (I->isDebugValue())
393  continue;
394 
395  // Working from the bottom, when we see a non-terminator instruction, we're
396  // done.
397  if (!isUnpredicatedTerminator(*I))
398  break;
399 
400  // A terminator that isn't a branch can't easily be handled by this
401  // analysis.
402  if (!I->isBranch())
403  return true;
404 
405  // Can't handle indirect branches.
407  if (!Branch.Target->isMBB())
408  return true;
409 
410  // Punt on compound branches.
411  if (Branch.Type != SystemZII::BranchNormal)
412  return true;
413 
414  if (Branch.CCMask == SystemZ::CCMASK_ANY) {
415  // Handle unconditional branches.
416  if (!AllowModify) {
417  TBB = Branch.Target->getMBB();
418  continue;
419  }
420 
421  // If the block has any instructions after a JMP, delete them.
422  while (std::next(I) != MBB.end())
423  std::next(I)->eraseFromParent();
424 
425  Cond.clear();
426  FBB = nullptr;
427 
428  // Delete the JMP if it's equivalent to a fall-through.
429  if (MBB.isLayoutSuccessor(Branch.Target->getMBB())) {
430  TBB = nullptr;
431  I->eraseFromParent();
432  I = MBB.end();
433  continue;
434  }
435 
436  // TBB is used to indicate the unconditinal destination.
437  TBB = Branch.Target->getMBB();
438  continue;
439  }
440 
441  // Working from the bottom, handle the first conditional branch.
442  if (Cond.empty()) {
443  // FIXME: add X86-style branch swap
444  FBB = TBB;
445  TBB = Branch.Target->getMBB();
448  continue;
449  }
450 
451  // Handle subsequent conditional branches.
452  assert(Cond.size() == 2 && TBB && "Should have seen a conditional branch");
453 
454  // Only handle the case where all conditional branches branch to the same
455  // destination.
456  if (TBB != Branch.Target->getMBB())
457  return true;
458 
459  // If the conditions are the same, we can leave them alone.
460  unsigned OldCCValid = Cond[0].getImm();
461  unsigned OldCCMask = Cond[1].getImm();
462  if (OldCCValid == Branch.CCValid && OldCCMask == Branch.CCMask)
463  continue;
464 
465  // FIXME: Try combining conditions like X86 does. Should be easy on Z!
466  return false;
467  }
468 
469  return false;
470 }
471 
473  int *BytesRemoved) const {
474  assert(!BytesRemoved && "code size not handled");
475 
476  // Most of the code and comments here are boilerplate.
478  unsigned Count = 0;
479 
480  while (I != MBB.begin()) {
481  --I;
482  if (I->isDebugValue())
483  continue;
484  if (!I->isBranch())
485  break;
486  if (!getBranchInfo(*I).Target->isMBB())
487  break;
488  // Remove the branch.
489  I->eraseFromParent();
490  I = MBB.end();
491  ++Count;
492  }
493 
494  return Count;
495 }
496 
499  assert(Cond.size() == 2 && "Invalid condition");
500  Cond[1].setImm(Cond[1].getImm() ^ Cond[0].getImm());
501  return false;
502 }
503 
505  MachineBasicBlock *TBB,
506  MachineBasicBlock *FBB,
508  const DebugLoc &DL,
509  int *BytesAdded) const {
510  // In this function we output 32-bit branches, which should always
511  // have enough range. They can be shortened and relaxed by later code
512  // in the pipeline, if desired.
513 
514  // Shouldn't be a fall through.
515  assert(TBB && "insertBranch must not be told to insert a fallthrough");
516  assert((Cond.size() == 2 || Cond.size() == 0) &&
517  "SystemZ branch conditions have one component!");
518  assert(!BytesAdded && "code size not handled");
519 
520  if (Cond.empty()) {
521  // Unconditional branch?
522  assert(!FBB && "Unconditional branch with multiple successors!");
523  BuildMI(&MBB, DL, get(SystemZ::J)).addMBB(TBB);
524  return 1;
525  }
526 
527  // Conditional branch.
528  unsigned Count = 0;
529  unsigned CCValid = Cond[0].getImm();
530  unsigned CCMask = Cond[1].getImm();
531  BuildMI(&MBB, DL, get(SystemZ::BRC))
532  .addImm(CCValid).addImm(CCMask).addMBB(TBB);
533  ++Count;
534 
535  if (FBB) {
536  // Two-way Conditional branch. Insert the second branch.
537  BuildMI(&MBB, DL, get(SystemZ::J)).addMBB(FBB);
538  ++Count;
539  }
540  return Count;
541 }
542 
543 bool SystemZInstrInfo::analyzeCompare(const MachineInstr &MI, unsigned &SrcReg,
544  unsigned &SrcReg2, int &Mask,
545  int &Value) const {
546  assert(MI.isCompare() && "Caller should have checked for a comparison");
547 
548  if (MI.getNumExplicitOperands() == 2 && MI.getOperand(0).isReg() &&
549  MI.getOperand(1).isImm()) {
550  SrcReg = MI.getOperand(0).getReg();
551  SrcReg2 = 0;
552  Value = MI.getOperand(1).getImm();
553  Mask = ~0;
554  return true;
555  }
556 
557  return false;
558 }
559 
560 // If Reg is a virtual register, return its definition, otherwise return null.
561 static MachineInstr *getDef(unsigned Reg,
562  const MachineRegisterInfo *MRI) {
564  return nullptr;
565  return MRI->getUniqueVRegDef(Reg);
566 }
567 
568 // Return true if MI is a shift of type Opcode by Imm bits.
569 static bool isShift(MachineInstr *MI, unsigned Opcode, int64_t Imm) {
570  return (MI->getOpcode() == Opcode &&
571  !MI->getOperand(2).getReg() &&
572  MI->getOperand(3).getImm() == Imm);
573 }
574 
575 // If the destination of MI has no uses, delete it as dead.
577  if (MRI->use_nodbg_empty(MI->getOperand(0).getReg()))
578  MI->eraseFromParent();
579 }
580 
581 // Compare compares SrcReg against zero. Check whether SrcReg contains
582 // the result of an IPM sequence whose input CC survives until Compare,
583 // and whether Compare is therefore redundant. Delete it and return
584 // true if so.
585 static bool removeIPMBasedCompare(MachineInstr &Compare, unsigned SrcReg,
586  const MachineRegisterInfo *MRI,
587  const TargetRegisterInfo *TRI) {
588  MachineInstr *LGFR = nullptr;
589  MachineInstr *RLL = getDef(SrcReg, MRI);
590  if (RLL && RLL->getOpcode() == SystemZ::LGFR) {
591  LGFR = RLL;
592  RLL = getDef(LGFR->getOperand(1).getReg(), MRI);
593  }
594  if (!RLL || !isShift(RLL, SystemZ::RLL, 31))
595  return false;
596 
597  MachineInstr *SRL = getDef(RLL->getOperand(1).getReg(), MRI);
598  if (!SRL || !isShift(SRL, SystemZ::SRL, SystemZ::IPM_CC))
599  return false;
600 
601  MachineInstr *IPM = getDef(SRL->getOperand(1).getReg(), MRI);
602  if (!IPM || IPM->getOpcode() != SystemZ::IPM)
603  return false;
604 
605  // Check that there are no assignments to CC between the IPM and Compare,
606  if (IPM->getParent() != Compare.getParent())
607  return false;
608  MachineBasicBlock::iterator MBBI = IPM, MBBE = Compare.getIterator();
609  for (++MBBI; MBBI != MBBE; ++MBBI) {
610  MachineInstr &MI = *MBBI;
611  if (MI.modifiesRegister(SystemZ::CC, TRI))
612  return false;
613  }
614 
615  Compare.eraseFromParent();
616  if (LGFR)
617  eraseIfDead(LGFR, MRI);
618  eraseIfDead(RLL, MRI);
619  eraseIfDead(SRL, MRI);
620  eraseIfDead(IPM, MRI);
621 
622  return true;
623 }
624 
626  MachineInstr &Compare, unsigned SrcReg, unsigned SrcReg2, int Mask,
627  int Value, const MachineRegisterInfo *MRI) const {
628  assert(!SrcReg2 && "Only optimizing constant comparisons so far");
629  bool IsLogical = (Compare.getDesc().TSFlags & SystemZII::IsLogical) != 0;
630  return Value == 0 && !IsLogical &&
631  removeIPMBasedCompare(Compare, SrcReg, MRI, &RI);
632 }
633 
636  unsigned TrueReg, unsigned FalseReg,
637  int &CondCycles, int &TrueCycles,
638  int &FalseCycles) const {
639  // Not all subtargets have LOCR instructions.
640  if (!STI.hasLoadStoreOnCond())
641  return false;
642  if (Pred.size() != 2)
643  return false;
644 
645  // Check register classes.
646  const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
647  const TargetRegisterClass *RC =
648  RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
649  if (!RC)
650  return false;
651 
652  // We have LOCR instructions for 32 and 64 bit general purpose registers.
653  if ((STI.hasLoadStoreOnCond2() &&
654  SystemZ::GRX32BitRegClass.hasSubClassEq(RC)) ||
655  SystemZ::GR32BitRegClass.hasSubClassEq(RC) ||
656  SystemZ::GR64BitRegClass.hasSubClassEq(RC)) {
657  CondCycles = 2;
658  TrueCycles = 2;
659  FalseCycles = 2;
660  return true;
661  }
662 
663  // Can't do anything else.
664  return false;
665 }
666 
669  const DebugLoc &DL, unsigned DstReg,
671  unsigned TrueReg,
672  unsigned FalseReg) const {
674  const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
675 
676  assert(Pred.size() == 2 && "Invalid condition");
677  unsigned CCValid = Pred[0].getImm();
678  unsigned CCMask = Pred[1].getImm();
679 
680  unsigned Opc;
681  if (SystemZ::GRX32BitRegClass.hasSubClassEq(RC)) {
682  if (STI.hasLoadStoreOnCond2())
683  Opc = SystemZ::LOCRMux;
684  else {
685  Opc = SystemZ::LOCR;
686  MRI.constrainRegClass(DstReg, &SystemZ::GR32BitRegClass);
687  unsigned TReg = MRI.createVirtualRegister(&SystemZ::GR32BitRegClass);
688  unsigned FReg = MRI.createVirtualRegister(&SystemZ::GR32BitRegClass);
689  BuildMI(MBB, I, DL, get(TargetOpcode::COPY), TReg).addReg(TrueReg);
690  BuildMI(MBB, I, DL, get(TargetOpcode::COPY), FReg).addReg(FalseReg);
691  TrueReg = TReg;
692  FalseReg = FReg;
693  }
694  } else if (SystemZ::GR64BitRegClass.hasSubClassEq(RC))
695  Opc = SystemZ::LOCGR;
696  else
697  llvm_unreachable("Invalid register class");
698 
699  BuildMI(MBB, I, DL, get(Opc), DstReg)
700  .addReg(FalseReg).addReg(TrueReg)
701  .addImm(CCValid).addImm(CCMask);
702 }
703 
705  unsigned Reg,
706  MachineRegisterInfo *MRI) const {
707  unsigned DefOpc = DefMI.getOpcode();
708  if (DefOpc != SystemZ::LHIMux && DefOpc != SystemZ::LHI &&
709  DefOpc != SystemZ::LGHI)
710  return false;
711  if (DefMI.getOperand(0).getReg() != Reg)
712  return false;
713  int32_t ImmVal = (int32_t)DefMI.getOperand(1).getImm();
714 
715  unsigned UseOpc = UseMI.getOpcode();
716  unsigned NewUseOpc;
717  unsigned UseIdx;
718  int CommuteIdx = -1;
719  switch (UseOpc) {
720  case SystemZ::LOCRMux:
721  if (!STI.hasLoadStoreOnCond2())
722  return false;
723  NewUseOpc = SystemZ::LOCHIMux;
724  if (UseMI.getOperand(2).getReg() == Reg)
725  UseIdx = 2;
726  else if (UseMI.getOperand(1).getReg() == Reg)
727  UseIdx = 2, CommuteIdx = 1;
728  else
729  return false;
730  break;
731  case SystemZ::LOCGR:
732  if (!STI.hasLoadStoreOnCond2())
733  return false;
734  NewUseOpc = SystemZ::LOCGHI;
735  if (UseMI.getOperand(2).getReg() == Reg)
736  UseIdx = 2;
737  else if (UseMI.getOperand(1).getReg() == Reg)
738  UseIdx = 2, CommuteIdx = 1;
739  else
740  return false;
741  break;
742  default:
743  return false;
744  }
745 
746  if (CommuteIdx != -1)
747  if (!commuteInstruction(UseMI, false, CommuteIdx, UseIdx))
748  return false;
749 
750  bool DeleteDef = MRI->hasOneNonDBGUse(Reg);
751  UseMI.setDesc(get(NewUseOpc));
752  UseMI.getOperand(UseIdx).ChangeToImmediate(ImmVal);
753  if (DeleteDef)
754  DefMI.eraseFromParent();
755 
756  return true;
757 }
758 
760  unsigned Opcode = MI.getOpcode();
761  if (Opcode == SystemZ::Return ||
762  Opcode == SystemZ::Trap ||
763  Opcode == SystemZ::CallJG ||
764  Opcode == SystemZ::CallBR)
765  return true;
766  return false;
767 }
768 
771  unsigned NumCycles, unsigned ExtraPredCycles,
772  BranchProbability Probability) const {
773  // Avoid using conditional returns at the end of a loop (since then
774  // we'd need to emit an unconditional branch to the beginning anyway,
775  // making the loop body longer). This doesn't apply for low-probability
776  // loops (eg. compare-and-swap retry), so just decide based on branch
777  // probability instead of looping structure.
778  // However, since Compare and Trap instructions cost the same as a regular
779  // Compare instruction, we should allow the if conversion to convert this
780  // into a Conditional Compare regardless of the branch probability.
781  if (MBB.getLastNonDebugInstr()->getOpcode() != SystemZ::Trap &&
782  MBB.succ_empty() && Probability < BranchProbability(1, 8))
783  return false;
784  // For now only convert single instructions.
785  return NumCycles == 1;
786 }
787 
790  unsigned NumCyclesT, unsigned ExtraPredCyclesT,
791  MachineBasicBlock &FMBB,
792  unsigned NumCyclesF, unsigned ExtraPredCyclesF,
793  BranchProbability Probability) const {
794  // For now avoid converting mutually-exclusive cases.
795  return false;
796 }
797 
800  BranchProbability Probability) const {
801  // For now only duplicate single instructions.
802  return NumCycles == 1;
803 }
804 
806  MachineInstr &MI, ArrayRef<MachineOperand> Pred) const {
807  assert(Pred.size() == 2 && "Invalid condition");
808  unsigned CCValid = Pred[0].getImm();
809  unsigned CCMask = Pred[1].getImm();
810  assert(CCMask > 0 && CCMask < 15 && "Invalid predicate");
811  unsigned Opcode = MI.getOpcode();
812  if (Opcode == SystemZ::Trap) {
813  MI.setDesc(get(SystemZ::CondTrap));
815  .addImm(CCValid).addImm(CCMask)
816  .addReg(SystemZ::CC, RegState::Implicit);
817  return true;
818  }
819  if (Opcode == SystemZ::Return) {
820  MI.setDesc(get(SystemZ::CondReturn));
822  .addImm(CCValid).addImm(CCMask)
823  .addReg(SystemZ::CC, RegState::Implicit);
824  return true;
825  }
826  if (Opcode == SystemZ::CallJG) {
827  MachineOperand FirstOp = MI.getOperand(0);
828  const uint32_t *RegMask = MI.getOperand(1).getRegMask();
829  MI.RemoveOperand(1);
830  MI.RemoveOperand(0);
831  MI.setDesc(get(SystemZ::CallBRCL));
833  .addImm(CCValid)
834  .addImm(CCMask)
835  .add(FirstOp)
836  .addRegMask(RegMask)
837  .addReg(SystemZ::CC, RegState::Implicit);
838  return true;
839  }
840  if (Opcode == SystemZ::CallBR) {
841  const uint32_t *RegMask = MI.getOperand(0).getRegMask();
842  MI.RemoveOperand(0);
843  MI.setDesc(get(SystemZ::CallBCR));
845  .addImm(CCValid).addImm(CCMask)
846  .addRegMask(RegMask)
847  .addReg(SystemZ::CC, RegState::Implicit);
848  return true;
849  }
850  return false;
851 }
852 
855  const DebugLoc &DL, unsigned DestReg,
856  unsigned SrcReg, bool KillSrc) const {
857  // Split 128-bit GPR moves into two 64-bit moves. Add implicit uses of the
858  // super register in case one of the subregs is undefined.
859  // This handles ADDR128 too.
860  if (SystemZ::GR128BitRegClass.contains(DestReg, SrcReg)) {
861  copyPhysReg(MBB, MBBI, DL, RI.getSubReg(DestReg, SystemZ::subreg_h64),
862  RI.getSubReg(SrcReg, SystemZ::subreg_h64), KillSrc);
863  MachineInstrBuilder(*MBB.getParent(), std::prev(MBBI))
864  .addReg(SrcReg, RegState::Implicit);
865  copyPhysReg(MBB, MBBI, DL, RI.getSubReg(DestReg, SystemZ::subreg_l64),
866  RI.getSubReg(SrcReg, SystemZ::subreg_l64), KillSrc);
867  MachineInstrBuilder(*MBB.getParent(), std::prev(MBBI))
868  .addReg(SrcReg, (getKillRegState(KillSrc) | RegState::Implicit));
869  return;
870  }
871 
872  if (SystemZ::GRX32BitRegClass.contains(DestReg, SrcReg)) {
873  emitGRX32Move(MBB, MBBI, DL, DestReg, SrcReg, SystemZ::LR, 32, KillSrc,
874  false);
875  return;
876  }
877 
878  // Move 128-bit floating-point values between VR128 and FP128.
879  if (SystemZ::VR128BitRegClass.contains(DestReg) &&
880  SystemZ::FP128BitRegClass.contains(SrcReg)) {
881  unsigned SrcRegHi =
882  RI.getMatchingSuperReg(RI.getSubReg(SrcReg, SystemZ::subreg_h64),
883  SystemZ::subreg_r64, &SystemZ::VR128BitRegClass);
884  unsigned SrcRegLo =
885  RI.getMatchingSuperReg(RI.getSubReg(SrcReg, SystemZ::subreg_l64),
886  SystemZ::subreg_r64, &SystemZ::VR128BitRegClass);
887 
888  BuildMI(MBB, MBBI, DL, get(SystemZ::VMRHG), DestReg)
889  .addReg(SrcRegHi, getKillRegState(KillSrc))
890  .addReg(SrcRegLo, getKillRegState(KillSrc));
891  return;
892  }
893  if (SystemZ::FP128BitRegClass.contains(DestReg) &&
894  SystemZ::VR128BitRegClass.contains(SrcReg)) {
895  unsigned DestRegHi =
896  RI.getMatchingSuperReg(RI.getSubReg(DestReg, SystemZ::subreg_h64),
897  SystemZ::subreg_r64, &SystemZ::VR128BitRegClass);
898  unsigned DestRegLo =
899  RI.getMatchingSuperReg(RI.getSubReg(DestReg, SystemZ::subreg_l64),
900  SystemZ::subreg_r64, &SystemZ::VR128BitRegClass);
901 
902  if (DestRegHi != SrcReg)
903  copyPhysReg(MBB, MBBI, DL, DestRegHi, SrcReg, false);
904  BuildMI(MBB, MBBI, DL, get(SystemZ::VREPG), DestRegLo)
905  .addReg(SrcReg, getKillRegState(KillSrc)).addImm(1);
906  return;
907  }
908 
909  // Everything else needs only one instruction.
910  unsigned Opcode;
911  if (SystemZ::GR64BitRegClass.contains(DestReg, SrcReg))
912  Opcode = SystemZ::LGR;
913  else if (SystemZ::FP32BitRegClass.contains(DestReg, SrcReg))
914  // For z13 we prefer LDR over LER to avoid partial register dependencies.
915  Opcode = STI.hasVector() ? SystemZ::LDR32 : SystemZ::LER;
916  else if (SystemZ::FP64BitRegClass.contains(DestReg, SrcReg))
917  Opcode = SystemZ::LDR;
918  else if (SystemZ::FP128BitRegClass.contains(DestReg, SrcReg))
919  Opcode = SystemZ::LXR;
920  else if (SystemZ::VR32BitRegClass.contains(DestReg, SrcReg))
921  Opcode = SystemZ::VLR32;
922  else if (SystemZ::VR64BitRegClass.contains(DestReg, SrcReg))
923  Opcode = SystemZ::VLR64;
924  else if (SystemZ::VR128BitRegClass.contains(DestReg, SrcReg))
925  Opcode = SystemZ::VLR;
926  else if (SystemZ::AR32BitRegClass.contains(DestReg, SrcReg))
927  Opcode = SystemZ::CPYA;
928  else if (SystemZ::AR32BitRegClass.contains(DestReg) &&
929  SystemZ::GR32BitRegClass.contains(SrcReg))
930  Opcode = SystemZ::SAR;
931  else if (SystemZ::GR32BitRegClass.contains(DestReg) &&
932  SystemZ::AR32BitRegClass.contains(SrcReg))
933  Opcode = SystemZ::EAR;
934  else
935  llvm_unreachable("Impossible reg-to-reg copy");
936 
937  BuildMI(MBB, MBBI, DL, get(Opcode), DestReg)
938  .addReg(SrcReg, getKillRegState(KillSrc));
939 }
940 
942  MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg,
943  bool isKill, int FrameIdx, const TargetRegisterClass *RC,
944  const TargetRegisterInfo *TRI) const {
945  DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
946 
947  // Callers may expect a single instruction, so keep 128-bit moves
948  // together for now and lower them after register allocation.
949  unsigned LoadOpcode, StoreOpcode;
950  getLoadStoreOpcodes(RC, LoadOpcode, StoreOpcode);
951  addFrameReference(BuildMI(MBB, MBBI, DL, get(StoreOpcode))
952  .addReg(SrcReg, getKillRegState(isKill)),
953  FrameIdx);
954 }
955 
957  MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg,
958  int FrameIdx, const TargetRegisterClass *RC,
959  const TargetRegisterInfo *TRI) const {
960  DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
961 
962  // Callers may expect a single instruction, so keep 128-bit moves
963  // together for now and lower them after register allocation.
964  unsigned LoadOpcode, StoreOpcode;
965  getLoadStoreOpcodes(RC, LoadOpcode, StoreOpcode);
966  addFrameReference(BuildMI(MBB, MBBI, DL, get(LoadOpcode), DestReg),
967  FrameIdx);
968 }
969 
970 // Return true if MI is a simple load or store with a 12-bit displacement
971 // and no index. Flag is SimpleBDXLoad for loads and SimpleBDXStore for stores.
972 static bool isSimpleBD12Move(const MachineInstr *MI, unsigned Flag) {
973  const MCInstrDesc &MCID = MI->getDesc();
974  return ((MCID.TSFlags & Flag) &&
975  isUInt<12>(MI->getOperand(2).getImm()) &&
976  MI->getOperand(3).getReg() == 0);
977 }
978 
979 namespace {
980 
981 struct LogicOp {
982  LogicOp() = default;
983  LogicOp(unsigned regSize, unsigned immLSB, unsigned immSize)
984  : RegSize(regSize), ImmLSB(immLSB), ImmSize(immSize) {}
985 
986  explicit operator bool() const { return RegSize; }
987 
988  unsigned RegSize = 0;
989  unsigned ImmLSB = 0;
990  unsigned ImmSize = 0;
991 };
992 
993 } // end anonymous namespace
994 
995 static LogicOp interpretAndImmediate(unsigned Opcode) {
996  switch (Opcode) {
997  case SystemZ::NILMux: return LogicOp(32, 0, 16);
998  case SystemZ::NIHMux: return LogicOp(32, 16, 16);
999  case SystemZ::NILL64: return LogicOp(64, 0, 16);
1000  case SystemZ::NILH64: return LogicOp(64, 16, 16);
1001  case SystemZ::NIHL64: return LogicOp(64, 32, 16);
1002  case SystemZ::NIHH64: return LogicOp(64, 48, 16);
1003  case SystemZ::NIFMux: return LogicOp(32, 0, 32);
1004  case SystemZ::NILF64: return LogicOp(64, 0, 32);
1005  case SystemZ::NIHF64: return LogicOp(64, 32, 32);
1006  default: return LogicOp();
1007  }
1008 }
1009 
1010 static void transferDeadCC(MachineInstr *OldMI, MachineInstr *NewMI) {
1011  if (OldMI->registerDefIsDead(SystemZ::CC)) {
1012  MachineOperand *CCDef = NewMI->findRegisterDefOperand(SystemZ::CC);
1013  if (CCDef != nullptr)
1014  CCDef->setIsDead(true);
1015  }
1016 }
1017 
1018 // Used to return from convertToThreeAddress after replacing two-address
1019 // instruction OldMI with three-address instruction NewMI.
1021  MachineInstr *NewMI,
1022  LiveVariables *LV) {
1023  if (LV) {
1024  unsigned NumOps = OldMI->getNumOperands();
1025  for (unsigned I = 1; I < NumOps; ++I) {
1026  MachineOperand &Op = OldMI->getOperand(I);
1027  if (Op.isReg() && Op.isKill())
1028  LV->replaceKillInstruction(Op.getReg(), *OldMI, *NewMI);
1029  }
1030  }
1031  transferDeadCC(OldMI, NewMI);
1032  return NewMI;
1033 }
1034 
1036  MachineFunction::iterator &MFI, MachineInstr &MI, LiveVariables *LV) const {
1037  MachineBasicBlock *MBB = MI.getParent();
1038  MachineFunction *MF = MBB->getParent();
1040 
1041  unsigned Opcode = MI.getOpcode();
1042  unsigned NumOps = MI.getNumOperands();
1043 
1044  // Try to convert something like SLL into SLLK, if supported.
1045  // We prefer to keep the two-operand form where possible both
1046  // because it tends to be shorter and because some instructions
1047  // have memory forms that can be used during spilling.
1048  if (STI.hasDistinctOps()) {
1049  MachineOperand &Dest = MI.getOperand(0);
1050  MachineOperand &Src = MI.getOperand(1);
1051  unsigned DestReg = Dest.getReg();
1052  unsigned SrcReg = Src.getReg();
1053  // AHIMux is only really a three-operand instruction when both operands
1054  // are low registers. Try to constrain both operands to be low if
1055  // possible.
1056  if (Opcode == SystemZ::AHIMux &&
1059  MRI.getRegClass(DestReg)->contains(SystemZ::R1L) &&
1060  MRI.getRegClass(SrcReg)->contains(SystemZ::R1L)) {
1061  MRI.constrainRegClass(DestReg, &SystemZ::GR32BitRegClass);
1062  MRI.constrainRegClass(SrcReg, &SystemZ::GR32BitRegClass);
1063  }
1064  int ThreeOperandOpcode = SystemZ::getThreeOperandOpcode(Opcode);
1065  if (ThreeOperandOpcode >= 0) {
1066  // Create three address instruction without adding the implicit
1067  // operands. Those will instead be copied over from the original
1068  // instruction by the loop below.
1069  MachineInstrBuilder MIB(
1070  *MF, MF->CreateMachineInstr(get(ThreeOperandOpcode), MI.getDebugLoc(),
1071  /*NoImplicit=*/true));
1072  MIB.add(Dest);
1073  // Keep the kill state, but drop the tied flag.
1074  MIB.addReg(Src.getReg(), getKillRegState(Src.isKill()), Src.getSubReg());
1075  // Keep the remaining operands as-is.
1076  for (unsigned I = 2; I < NumOps; ++I)
1077  MIB.add(MI.getOperand(I));
1078  MBB->insert(MI, MIB);
1079  return finishConvertToThreeAddress(&MI, MIB, LV);
1080  }
1081  }
1082 
1083  // Try to convert an AND into an RISBG-type instruction.
1084  if (LogicOp And = interpretAndImmediate(Opcode)) {
1085  uint64_t Imm = MI.getOperand(2).getImm() << And.ImmLSB;
1086  // AND IMMEDIATE leaves the other bits of the register unchanged.
1087  Imm |= allOnes(And.RegSize) & ~(allOnes(And.ImmSize) << And.ImmLSB);
1088  unsigned Start, End;
1089  if (isRxSBGMask(Imm, And.RegSize, Start, End)) {
1090  unsigned NewOpcode;
1091  if (And.RegSize == 64) {
1092  NewOpcode = SystemZ::RISBG;
1093  // Prefer RISBGN if available, since it does not clobber CC.
1094  if (STI.hasMiscellaneousExtensions())
1095  NewOpcode = SystemZ::RISBGN;
1096  } else {
1097  NewOpcode = SystemZ::RISBMux;
1098  Start &= 31;
1099  End &= 31;
1100  }
1101  MachineOperand &Dest = MI.getOperand(0);
1102  MachineOperand &Src = MI.getOperand(1);
1103  MachineInstrBuilder MIB =
1104  BuildMI(*MBB, MI, MI.getDebugLoc(), get(NewOpcode))
1105  .add(Dest)
1106  .addReg(0)
1107  .addReg(Src.getReg(), getKillRegState(Src.isKill()),
1108  Src.getSubReg())
1109  .addImm(Start)
1110  .addImm(End + 128)
1111  .addImm(0);
1112  return finishConvertToThreeAddress(&MI, MIB, LV);
1113  }
1114  }
1115  return nullptr;
1116 }
1117 
1121  LiveIntervals *LIS) const {
1122  const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
1123  const MachineFrameInfo &MFI = MF.getFrameInfo();
1124  unsigned Size = MFI.getObjectSize(FrameIndex);
1125  unsigned Opcode = MI.getOpcode();
1126 
1127  if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
1128  if (LIS != nullptr && (Opcode == SystemZ::LA || Opcode == SystemZ::LAY) &&
1129  isInt<8>(MI.getOperand(2).getImm()) && !MI.getOperand(3).getReg()) {
1130 
1131  // Check CC liveness, since new instruction introduces a dead
1132  // def of CC.
1133  MCRegUnitIterator CCUnit(SystemZ::CC, TRI);
1134  LiveRange &CCLiveRange = LIS->getRegUnit(*CCUnit);
1135  ++CCUnit;
1136  assert(!CCUnit.isValid() && "CC only has one reg unit.");
1137  SlotIndex MISlot =
1139  if (!CCLiveRange.liveAt(MISlot)) {
1140  // LA(Y) %reg, CONST(%reg) -> AGSI %mem, CONST
1141  MachineInstr *BuiltMI = BuildMI(*InsertPt->getParent(), InsertPt,
1142  MI.getDebugLoc(), get(SystemZ::AGSI))
1143  .addFrameIndex(FrameIndex)
1144  .addImm(0)
1145  .addImm(MI.getOperand(2).getImm());
1146  BuiltMI->findRegisterDefOperand(SystemZ::CC)->setIsDead(true);
1147  CCLiveRange.createDeadDef(MISlot, LIS->getVNInfoAllocator());
1148  return BuiltMI;
1149  }
1150  }
1151  return nullptr;
1152  }
1153 
1154  // All other cases require a single operand.
1155  if (Ops.size() != 1)
1156  return nullptr;
1157 
1158  unsigned OpNum = Ops[0];
1159  assert(Size * 8 ==
1160  TRI->getRegSizeInBits(*MF.getRegInfo()
1161  .getRegClass(MI.getOperand(OpNum).getReg())) &&
1162  "Invalid size combination");
1163 
1164  if ((Opcode == SystemZ::AHI || Opcode == SystemZ::AGHI) && OpNum == 0 &&
1165  isInt<8>(MI.getOperand(2).getImm())) {
1166  // A(G)HI %reg, CONST -> A(G)SI %mem, CONST
1167  Opcode = (Opcode == SystemZ::AHI ? SystemZ::ASI : SystemZ::AGSI);
1168  MachineInstr *BuiltMI =
1169  BuildMI(*InsertPt->getParent(), InsertPt, MI.getDebugLoc(), get(Opcode))
1170  .addFrameIndex(FrameIndex)
1171  .addImm(0)
1172  .addImm(MI.getOperand(2).getImm());
1173  transferDeadCC(&MI, BuiltMI);
1174  return BuiltMI;
1175  }
1176 
1177  if (Opcode == SystemZ::LGDR || Opcode == SystemZ::LDGR) {
1178  bool Op0IsGPR = (Opcode == SystemZ::LGDR);
1179  bool Op1IsGPR = (Opcode == SystemZ::LDGR);
1180  // If we're spilling the destination of an LDGR or LGDR, store the
1181  // source register instead.
1182  if (OpNum == 0) {
1183  unsigned StoreOpcode = Op1IsGPR ? SystemZ::STG : SystemZ::STD;
1184  return BuildMI(*InsertPt->getParent(), InsertPt, MI.getDebugLoc(),
1185  get(StoreOpcode))
1186  .add(MI.getOperand(1))
1187  .addFrameIndex(FrameIndex)
1188  .addImm(0)
1189  .addReg(0);
1190  }
1191  // If we're spilling the source of an LDGR or LGDR, load the
1192  // destination register instead.
1193  if (OpNum == 1) {
1194  unsigned LoadOpcode = Op0IsGPR ? SystemZ::LG : SystemZ::LD;
1195  return BuildMI(*InsertPt->getParent(), InsertPt, MI.getDebugLoc(),
1196  get(LoadOpcode))
1197  .add(MI.getOperand(0))
1198  .addFrameIndex(FrameIndex)
1199  .addImm(0)
1200  .addReg(0);
1201  }
1202  }
1203 
1204  // Look for cases where the source of a simple store or the destination
1205  // of a simple load is being spilled. Try to use MVC instead.
1206  //
1207  // Although MVC is in practice a fast choice in these cases, it is still
1208  // logically a bytewise copy. This means that we cannot use it if the
1209  // load or store is volatile. We also wouldn't be able to use MVC if
1210  // the two memories partially overlap, but that case cannot occur here,
1211  // because we know that one of the memories is a full frame index.
1212  //
1213  // For performance reasons, we also want to avoid using MVC if the addresses
1214  // might be equal. We don't worry about that case here, because spill slot
1215  // coloring happens later, and because we have special code to remove
1216  // MVCs that turn out to be redundant.
1217  if (OpNum == 0 && MI.hasOneMemOperand()) {
1218  MachineMemOperand *MMO = *MI.memoperands_begin();
1219  if (MMO->getSize() == Size && !MMO->isVolatile()) {
1220  // Handle conversion of loads.
1222  return BuildMI(*InsertPt->getParent(), InsertPt, MI.getDebugLoc(),
1223  get(SystemZ::MVC))
1224  .addFrameIndex(FrameIndex)
1225  .addImm(0)
1226  .addImm(Size)
1227  .add(MI.getOperand(1))
1228  .addImm(MI.getOperand(2).getImm())
1229  .addMemOperand(MMO);
1230  }
1231  // Handle conversion of stores.
1233  return BuildMI(*InsertPt->getParent(), InsertPt, MI.getDebugLoc(),
1234  get(SystemZ::MVC))
1235  .add(MI.getOperand(1))
1236  .addImm(MI.getOperand(2).getImm())
1237  .addImm(Size)
1238  .addFrameIndex(FrameIndex)
1239  .addImm(0)
1240  .addMemOperand(MMO);
1241  }
1242  }
1243  }
1244 
1245  // If the spilled operand is the final one, try to change <INSN>R
1246  // into <INSN>.
1247  int MemOpcode = SystemZ::getMemOpcode(Opcode);
1248  if (MemOpcode >= 0) {
1249  unsigned NumOps = MI.getNumExplicitOperands();
1250  if (OpNum == NumOps - 1) {
1251  const MCInstrDesc &MemDesc = get(MemOpcode);
1252  uint64_t AccessBytes = SystemZII::getAccessSize(MemDesc.TSFlags);
1253  assert(AccessBytes != 0 && "Size of access should be known");
1254  assert(AccessBytes <= Size && "Access outside the frame index");
1255  uint64_t Offset = Size - AccessBytes;
1256  MachineInstrBuilder MIB = BuildMI(*InsertPt->getParent(), InsertPt,
1257  MI.getDebugLoc(), get(MemOpcode));
1258  for (unsigned I = 0; I < OpNum; ++I)
1259  MIB.add(MI.getOperand(I));
1260  MIB.addFrameIndex(FrameIndex).addImm(Offset);
1261  if (MemDesc.TSFlags & SystemZII::HasIndex)
1262  MIB.addReg(0);
1263  transferDeadCC(&MI, MIB);
1264  return MIB;
1265  }
1266  }
1267 
1268  return nullptr;
1269 }
1270 
1273  MachineBasicBlock::iterator InsertPt, MachineInstr &LoadMI,
1274  LiveIntervals *LIS) const {
1275  return nullptr;
1276 }
1277 
1279  switch (MI.getOpcode()) {
1280  case SystemZ::L128:
1281  splitMove(MI, SystemZ::LG);
1282  return true;
1283 
1284  case SystemZ::ST128:
1285  splitMove(MI, SystemZ::STG);
1286  return true;
1287 
1288  case SystemZ::LX:
1289  splitMove(MI, SystemZ::LD);
1290  return true;
1291 
1292  case SystemZ::STX:
1293  splitMove(MI, SystemZ::STD);
1294  return true;
1295 
1296  case SystemZ::LBMux:
1297  expandRXYPseudo(MI, SystemZ::LB, SystemZ::LBH);
1298  return true;
1299 
1300  case SystemZ::LHMux:
1301  expandRXYPseudo(MI, SystemZ::LH, SystemZ::LHH);
1302  return true;
1303 
1304  case SystemZ::LLCRMux:
1305  expandZExtPseudo(MI, SystemZ::LLCR, 8);
1306  return true;
1307 
1308  case SystemZ::LLHRMux:
1309  expandZExtPseudo(MI, SystemZ::LLHR, 16);
1310  return true;
1311 
1312  case SystemZ::LLCMux:
1313  expandRXYPseudo(MI, SystemZ::LLC, SystemZ::LLCH);
1314  return true;
1315 
1316  case SystemZ::LLHMux:
1317  expandRXYPseudo(MI, SystemZ::LLH, SystemZ::LLHH);
1318  return true;
1319 
1320  case SystemZ::LMux:
1321  expandRXYPseudo(MI, SystemZ::L, SystemZ::LFH);
1322  return true;
1323 
1324  case SystemZ::LOCMux:
1325  expandLOCPseudo(MI, SystemZ::LOC, SystemZ::LOCFH);
1326  return true;
1327 
1328  case SystemZ::LOCHIMux:
1329  expandLOCPseudo(MI, SystemZ::LOCHI, SystemZ::LOCHHI);
1330  return true;
1331 
1332  case SystemZ::LOCRMux:
1333  expandLOCRPseudo(MI, SystemZ::LOCR, SystemZ::LOCFHR);
1334  return true;
1335 
1336  case SystemZ::STCMux:
1337  expandRXYPseudo(MI, SystemZ::STC, SystemZ::STCH);
1338  return true;
1339 
1340  case SystemZ::STHMux:
1341  expandRXYPseudo(MI, SystemZ::STH, SystemZ::STHH);
1342  return true;
1343 
1344  case SystemZ::STMux:
1345  expandRXYPseudo(MI, SystemZ::ST, SystemZ::STFH);
1346  return true;
1347 
1348  case SystemZ::STOCMux:
1349  expandLOCPseudo(MI, SystemZ::STOC, SystemZ::STOCFH);
1350  return true;
1351 
1352  case SystemZ::LHIMux:
1353  expandRIPseudo(MI, SystemZ::LHI, SystemZ::IIHF, true);
1354  return true;
1355 
1356  case SystemZ::IIFMux:
1357  expandRIPseudo(MI, SystemZ::IILF, SystemZ::IIHF, false);
1358  return true;
1359 
1360  case SystemZ::IILMux:
1361  expandRIPseudo(MI, SystemZ::IILL, SystemZ::IIHL, false);
1362  return true;
1363 
1364  case SystemZ::IIHMux:
1365  expandRIPseudo(MI, SystemZ::IILH, SystemZ::IIHH, false);
1366  return true;
1367 
1368  case SystemZ::NIFMux:
1369  expandRIPseudo(MI, SystemZ::NILF, SystemZ::NIHF, false);
1370  return true;
1371 
1372  case SystemZ::NILMux:
1373  expandRIPseudo(MI, SystemZ::NILL, SystemZ::NIHL, false);
1374  return true;
1375 
1376  case SystemZ::NIHMux:
1377  expandRIPseudo(MI, SystemZ::NILH, SystemZ::NIHH, false);
1378  return true;
1379 
1380  case SystemZ::OIFMux:
1381  expandRIPseudo(MI, SystemZ::OILF, SystemZ::OIHF, false);
1382  return true;
1383 
1384  case SystemZ::OILMux:
1385  expandRIPseudo(MI, SystemZ::OILL, SystemZ::OIHL, false);
1386  return true;
1387 
1388  case SystemZ::OIHMux:
1389  expandRIPseudo(MI, SystemZ::OILH, SystemZ::OIHH, false);
1390  return true;
1391 
1392  case SystemZ::XIFMux:
1393  expandRIPseudo(MI, SystemZ::XILF, SystemZ::XIHF, false);
1394  return true;
1395 
1396  case SystemZ::TMLMux:
1397  expandRIPseudo(MI, SystemZ::TMLL, SystemZ::TMHL, false);
1398  return true;
1399 
1400  case SystemZ::TMHMux:
1401  expandRIPseudo(MI, SystemZ::TMLH, SystemZ::TMHH, false);
1402  return true;
1403 
1404  case SystemZ::AHIMux:
1405  expandRIPseudo(MI, SystemZ::AHI, SystemZ::AIH, false);
1406  return true;
1407 
1408  case SystemZ::AHIMuxK:
1409  expandRIEPseudo(MI, SystemZ::AHI, SystemZ::AHIK, SystemZ::AIH);
1410  return true;
1411 
1412  case SystemZ::AFIMux:
1413  expandRIPseudo(MI, SystemZ::AFI, SystemZ::AIH, false);
1414  return true;
1415 
1416  case SystemZ::CHIMux:
1417  expandRIPseudo(MI, SystemZ::CHI, SystemZ::CIH, false);
1418  return true;
1419 
1420  case SystemZ::CFIMux:
1421  expandRIPseudo(MI, SystemZ::CFI, SystemZ::CIH, false);
1422  return true;
1423 
1424  case SystemZ::CLFIMux:
1425  expandRIPseudo(MI, SystemZ::CLFI, SystemZ::CLIH, false);
1426  return true;
1427 
1428  case SystemZ::CMux:
1429  expandRXYPseudo(MI, SystemZ::C, SystemZ::CHF);
1430  return true;
1431 
1432  case SystemZ::CLMux:
1433  expandRXYPseudo(MI, SystemZ::CL, SystemZ::CLHF);
1434  return true;
1435 
1436  case SystemZ::RISBMux: {
1437  bool DestIsHigh = isHighReg(MI.getOperand(0).getReg());
1438  bool SrcIsHigh = isHighReg(MI.getOperand(2).getReg());
1439  if (SrcIsHigh == DestIsHigh)
1440  MI.setDesc(get(DestIsHigh ? SystemZ::RISBHH : SystemZ::RISBLL));
1441  else {
1442  MI.setDesc(get(DestIsHigh ? SystemZ::RISBHL : SystemZ::RISBLH));
1443  MI.getOperand(5).setImm(MI.getOperand(5).getImm() ^ 32);
1444  }
1445  return true;
1446  }
1447 
1448  case SystemZ::ADJDYNALLOC:
1449  splitAdjDynAlloc(MI);
1450  return true;
1451 
1452  case TargetOpcode::LOAD_STACK_GUARD:
1453  expandLoadStackGuard(&MI);
1454  return true;
1455 
1456  default:
1457  return false;
1458  }
1459 }
1460 
1462  if (MI.getOpcode() == TargetOpcode::INLINEASM) {
1463  const MachineFunction *MF = MI.getParent()->getParent();
1464  const char *AsmStr = MI.getOperand(0).getSymbolName();
1465  return getInlineAsmLength(AsmStr, *MF->getTarget().getMCAsmInfo());
1466  }
1467  return MI.getDesc().getSize();
1468 }
1469 
1472  switch (MI.getOpcode()) {
1473  case SystemZ::BR:
1474  case SystemZ::BI:
1475  case SystemZ::J:
1476  case SystemZ::JG:
1479 
1480  case SystemZ::BRC:
1481  case SystemZ::BRCL:
1483  MI.getOperand(1).getImm(), &MI.getOperand(2));
1484 
1485  case SystemZ::BRCT:
1486  case SystemZ::BRCTH:
1489 
1490  case SystemZ::BRCTG:
1493 
1494  case SystemZ::CIJ:
1495  case SystemZ::CRJ:
1497  MI.getOperand(2).getImm(), &MI.getOperand(3));
1498 
1499  case SystemZ::CLIJ:
1500  case SystemZ::CLRJ:
1502  MI.getOperand(2).getImm(), &MI.getOperand(3));
1503 
1504  case SystemZ::CGIJ:
1505  case SystemZ::CGRJ:
1507  MI.getOperand(2).getImm(), &MI.getOperand(3));
1508 
1509  case SystemZ::CLGIJ:
1510  case SystemZ::CLGRJ:
1512  MI.getOperand(2).getImm(), &MI.getOperand(3));
1513 
1514  default:
1515  llvm_unreachable("Unrecognized branch opcode");
1516  }
1517 }
1518 
1520  unsigned &LoadOpcode,
1521  unsigned &StoreOpcode) const {
1522  if (RC == &SystemZ::GR32BitRegClass || RC == &SystemZ::ADDR32BitRegClass) {
1523  LoadOpcode = SystemZ::L;
1524  StoreOpcode = SystemZ::ST;
1525  } else if (RC == &SystemZ::GRH32BitRegClass) {
1526  LoadOpcode = SystemZ::LFH;
1527  StoreOpcode = SystemZ::STFH;
1528  } else if (RC == &SystemZ::GRX32BitRegClass) {
1529  LoadOpcode = SystemZ::LMux;
1530  StoreOpcode = SystemZ::STMux;
1531  } else if (RC == &SystemZ::GR64BitRegClass ||
1532  RC == &SystemZ::ADDR64BitRegClass) {
1533  LoadOpcode = SystemZ::LG;
1534  StoreOpcode = SystemZ::STG;
1535  } else if (RC == &SystemZ::GR128BitRegClass ||
1536  RC == &SystemZ::ADDR128BitRegClass) {
1537  LoadOpcode = SystemZ::L128;
1538  StoreOpcode = SystemZ::ST128;
1539  } else if (RC == &SystemZ::FP32BitRegClass) {
1540  LoadOpcode = SystemZ::LE;
1541  StoreOpcode = SystemZ::STE;
1542  } else if (RC == &SystemZ::FP64BitRegClass) {
1543  LoadOpcode = SystemZ::LD;
1544  StoreOpcode = SystemZ::STD;
1545  } else if (RC == &SystemZ::FP128BitRegClass) {
1546  LoadOpcode = SystemZ::LX;
1547  StoreOpcode = SystemZ::STX;
1548  } else if (RC == &SystemZ::VR32BitRegClass) {
1549  LoadOpcode = SystemZ::VL32;
1550  StoreOpcode = SystemZ::VST32;
1551  } else if (RC == &SystemZ::VR64BitRegClass) {
1552  LoadOpcode = SystemZ::VL64;
1553  StoreOpcode = SystemZ::VST64;
1554  } else if (RC == &SystemZ::VF128BitRegClass ||
1555  RC == &SystemZ::VR128BitRegClass) {
1556  LoadOpcode = SystemZ::VL;
1557  StoreOpcode = SystemZ::VST;
1558  } else
1559  llvm_unreachable("Unsupported regclass to load or store");
1560 }
1561 
1562 unsigned SystemZInstrInfo::getOpcodeForOffset(unsigned Opcode,
1563  int64_t Offset) const {
1564  const MCInstrDesc &MCID = get(Opcode);
1565  int64_t Offset2 = (MCID.TSFlags & SystemZII::Is128Bit ? Offset + 8 : Offset);
1566  if (isUInt<12>(Offset) && isUInt<12>(Offset2)) {
1567  // Get the instruction to use for unsigned 12-bit displacements.
1568  int Disp12Opcode = SystemZ::getDisp12Opcode(Opcode);
1569  if (Disp12Opcode >= 0)
1570  return Disp12Opcode;
1571 
1572  // All address-related instructions can use unsigned 12-bit
1573  // displacements.
1574  return Opcode;
1575  }
1576  if (isInt<20>(Offset) && isInt<20>(Offset2)) {
1577  // Get the instruction to use for signed 20-bit displacements.
1578  int Disp20Opcode = SystemZ::getDisp20Opcode(Opcode);
1579  if (Disp20Opcode >= 0)
1580  return Disp20Opcode;
1581 
1582  // Check whether Opcode allows signed 20-bit displacements.
1584  return Opcode;
1585  }
1586  return 0;
1587 }
1588 
1589 unsigned SystemZInstrInfo::getLoadAndTest(unsigned Opcode) const {
1590  switch (Opcode) {
1591  case SystemZ::L: return SystemZ::LT;
1592  case SystemZ::LY: return SystemZ::LT;
1593  case SystemZ::LG: return SystemZ::LTG;
1594  case SystemZ::LGF: return SystemZ::LTGF;
1595  case SystemZ::LR: return SystemZ::LTR;
1596  case SystemZ::LGFR: return SystemZ::LTGFR;
1597  case SystemZ::LGR: return SystemZ::LTGR;
1598  case SystemZ::LER: return SystemZ::LTEBR;
1599  case SystemZ::LDR: return SystemZ::LTDBR;
1600  case SystemZ::LXR: return SystemZ::LTXBR;
1601  case SystemZ::LCDFR: return SystemZ::LCDBR;
1602  case SystemZ::LPDFR: return SystemZ::LPDBR;
1603  case SystemZ::LNDFR: return SystemZ::LNDBR;
1604  case SystemZ::LCDFR_32: return SystemZ::LCEBR;
1605  case SystemZ::LPDFR_32: return SystemZ::LPEBR;
1606  case SystemZ::LNDFR_32: return SystemZ::LNEBR;
1607  // On zEC12 we prefer to use RISBGN. But if there is a chance to
1608  // actually use the condition code, we may turn it back into RISGB.
1609  // Note that RISBG is not really a "load-and-test" instruction,
1610  // but sets the same condition code values, so is OK to use here.
1611  case SystemZ::RISBGN: return SystemZ::RISBG;
1612  default: return 0;
1613  }
1614 }
1615 
1616 // Return true if Mask matches the regexp 0*1+0*, given that zero masks
1617 // have already been filtered out. Store the first set bit in LSB and
1618 // the number of set bits in Length if so.
1619 static bool isStringOfOnes(uint64_t Mask, unsigned &LSB, unsigned &Length) {
1620  unsigned First = findFirstSet(Mask);
1621  uint64_t Top = (Mask >> First) + 1;
1622  if ((Top & -Top) == Top) {
1623  LSB = First;
1624  Length = findFirstSet(Top);
1625  return true;
1626  }
1627  return false;
1628 }
1629 
1630 bool SystemZInstrInfo::isRxSBGMask(uint64_t Mask, unsigned BitSize,
1631  unsigned &Start, unsigned &End) const {
1632  // Reject trivial all-zero masks.
1633  Mask &= allOnes(BitSize);
1634  if (Mask == 0)
1635  return false;
1636 
1637  // Handle the 1+0+ or 0+1+0* cases. Start then specifies the index of
1638  // the msb and End specifies the index of the lsb.
1639  unsigned LSB, Length;
1640  if (isStringOfOnes(Mask, LSB, Length)) {
1641  Start = 63 - (LSB + Length - 1);
1642  End = 63 - LSB;
1643  return true;
1644  }
1645 
1646  // Handle the wrap-around 1+0+1+ cases. Start then specifies the msb
1647  // of the low 1s and End specifies the lsb of the high 1s.
1648  if (isStringOfOnes(Mask ^ allOnes(BitSize), LSB, Length)) {
1649  assert(LSB > 0 && "Bottom bit must be set");
1650  assert(LSB + Length < BitSize && "Top bit must be set");
1651  Start = 63 - (LSB - 1);
1652  End = 63 - (LSB + Length);
1653  return true;
1654  }
1655 
1656  return false;
1657 }
1658 
1659 unsigned SystemZInstrInfo::getFusedCompare(unsigned Opcode,
1661  const MachineInstr *MI) const {
1662  switch (Opcode) {
1663  case SystemZ::CHI:
1664  case SystemZ::CGHI:
1665  if (!(MI && isInt<8>(MI->getOperand(1).getImm())))
1666  return 0;
1667  break;
1668  case SystemZ::CLFI:
1669  case SystemZ::CLGFI:
1670  if (!(MI && isUInt<8>(MI->getOperand(1).getImm())))
1671  return 0;
1672  break;
1673  case SystemZ::CL:
1674  case SystemZ::CLG:
1675  if (!STI.hasMiscellaneousExtensions())
1676  return 0;
1677  if (!(MI && MI->getOperand(3).getReg() == 0))
1678  return 0;
1679  break;
1680  }
1681  switch (Type) {
1683  switch (Opcode) {
1684  case SystemZ::CR:
1685  return SystemZ::CRJ;
1686  case SystemZ::CGR:
1687  return SystemZ::CGRJ;
1688  case SystemZ::CHI:
1689  return SystemZ::CIJ;
1690  case SystemZ::CGHI:
1691  return SystemZ::CGIJ;
1692  case SystemZ::CLR:
1693  return SystemZ::CLRJ;
1694  case SystemZ::CLGR:
1695  return SystemZ::CLGRJ;
1696  case SystemZ::CLFI:
1697  return SystemZ::CLIJ;
1698  case SystemZ::CLGFI:
1699  return SystemZ::CLGIJ;
1700  default:
1701  return 0;
1702  }
1704  switch (Opcode) {
1705  case SystemZ::CR:
1706  return SystemZ::CRBReturn;
1707  case SystemZ::CGR:
1708  return SystemZ::CGRBReturn;
1709  case SystemZ::CHI:
1710  return SystemZ::CIBReturn;
1711  case SystemZ::CGHI:
1712  return SystemZ::CGIBReturn;
1713  case SystemZ::CLR:
1714  return SystemZ::CLRBReturn;
1715  case SystemZ::CLGR:
1716  return SystemZ::CLGRBReturn;
1717  case SystemZ::CLFI:
1718  return SystemZ::CLIBReturn;
1719  case SystemZ::CLGFI:
1720  return SystemZ::CLGIBReturn;
1721  default:
1722  return 0;
1723  }
1725  switch (Opcode) {
1726  case SystemZ::CR:
1727  return SystemZ::CRBCall;
1728  case SystemZ::CGR:
1729  return SystemZ::CGRBCall;
1730  case SystemZ::CHI:
1731  return SystemZ::CIBCall;
1732  case SystemZ::CGHI:
1733  return SystemZ::CGIBCall;
1734  case SystemZ::CLR:
1735  return SystemZ::CLRBCall;
1736  case SystemZ::CLGR:
1737  return SystemZ::CLGRBCall;
1738  case SystemZ::CLFI:
1739  return SystemZ::CLIBCall;
1740  case SystemZ::CLGFI:
1741  return SystemZ::CLGIBCall;
1742  default:
1743  return 0;
1744  }
1746  switch (Opcode) {
1747  case SystemZ::CR:
1748  return SystemZ::CRT;
1749  case SystemZ::CGR:
1750  return SystemZ::CGRT;
1751  case SystemZ::CHI:
1752  return SystemZ::CIT;
1753  case SystemZ::CGHI:
1754  return SystemZ::CGIT;
1755  case SystemZ::CLR:
1756  return SystemZ::CLRT;
1757  case SystemZ::CLGR:
1758  return SystemZ::CLGRT;
1759  case SystemZ::CLFI:
1760  return SystemZ::CLFIT;
1761  case SystemZ::CLGFI:
1762  return SystemZ::CLGIT;
1763  case SystemZ::CL:
1764  return SystemZ::CLT;
1765  case SystemZ::CLG:
1766  return SystemZ::CLGT;
1767  default:
1768  return 0;
1769  }
1770  }
1771  return 0;
1772 }
1773 
1774 unsigned SystemZInstrInfo::getLoadAndTrap(unsigned Opcode) const {
1775  if (!STI.hasLoadAndTrap())
1776  return 0;
1777  switch (Opcode) {
1778  case SystemZ::L:
1779  case SystemZ::LY:
1780  return SystemZ::LAT;
1781  case SystemZ::LG:
1782  return SystemZ::LGAT;
1783  case SystemZ::LFH:
1784  return SystemZ::LFHAT;
1785  case SystemZ::LLGF:
1786  return SystemZ::LLGFAT;
1787  case SystemZ::LLGT:
1788  return SystemZ::LLGTAT;
1789  }
1790  return 0;
1791 }
1792 
1795  unsigned Reg, uint64_t Value) const {
1796  DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
1797  unsigned Opcode;
1798  if (isInt<16>(Value))
1799  Opcode = SystemZ::LGHI;
1800  else if (SystemZ::isImmLL(Value))
1801  Opcode = SystemZ::LLILL;
1802  else if (SystemZ::isImmLH(Value)) {
1803  Opcode = SystemZ::LLILH;
1804  Value >>= 16;
1805  } else {
1806  assert(isInt<32>(Value) && "Huge values not handled yet");
1807  Opcode = SystemZ::LGFI;
1808  }
1809  BuildMI(MBB, MBBI, DL, get(Opcode), Reg).addImm(Value);
1810 }
1811 
1812 bool SystemZInstrInfo::
1814  AliasAnalysis *AA) const {
1815 
1816  if (!MIa.hasOneMemOperand() || !MIb.hasOneMemOperand())
1817  return false;
1818 
1819  // If mem-operands show that the same address Value is used by both
1820  // instructions, check for non-overlapping offsets and widths. Not
1821  // sure if a register based analysis would be an improvement...
1822 
1823  MachineMemOperand *MMOa = *MIa.memoperands_begin();
1824  MachineMemOperand *MMOb = *MIb.memoperands_begin();
1825  const Value *VALa = MMOa->getValue();
1826  const Value *VALb = MMOb->getValue();
1827  bool SameVal = (VALa && VALb && (VALa == VALb));
1828  if (!SameVal) {
1829  const PseudoSourceValue *PSVa = MMOa->getPseudoValue();
1830  const PseudoSourceValue *PSVb = MMOb->getPseudoValue();
1831  if (PSVa && PSVb && (PSVa == PSVb))
1832  SameVal = true;
1833  }
1834  if (SameVal) {
1835  int OffsetA = MMOa->getOffset(), OffsetB = MMOb->getOffset();
1836  int WidthA = MMOa->getSize(), WidthB = MMOb->getSize();
1837  int LowOffset = OffsetA < OffsetB ? OffsetA : OffsetB;
1838  int HighOffset = OffsetA < OffsetB ? OffsetB : OffsetA;
1839  int LowWidth = (LowOffset == OffsetA) ? WidthA : WidthB;
1840  if (LowOffset + LowWidth <= HighOffset)
1841  return true;
1842  }
1843 
1844  return false;
1845 }
uint64_t CallInst * C
void loadImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned Reg, uint64_t Value) const
const MachineInstrBuilder & add(const MachineOperand &MO) const
void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, unsigned DstReg, ArrayRef< MachineOperand > Cond, unsigned TrueReg, unsigned FalseReg) const override
bool expandPostRAPseudo(MachineInstr &MBBI) const override
bool modifiesRegister(unsigned Reg, const TargetRegisterInfo *TRI) const
Return true if the MachineInstr modifies (fully define or partially define) the specified register...
Definition: MachineInstr.h:965
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
bool use_nodbg_empty(unsigned RegNo) const
use_nodbg_empty - Return true if there are no non-Debug instructions using the specified register...
bool contains(unsigned Reg) const
Return true if the specified register is included in this register class.
MachineBasicBlock * getMBB() const
const int64_t CallFrameSize
const TargetRegisterClass * getRegClass(unsigned Reg) const
Return the register class of the specified virtual register.
SystemZInstrInfo(SystemZSubtarget &STI)
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
MachineOperand * findRegisterDefOperand(unsigned Reg, bool isDead=false, const TargetRegisterInfo *TRI=nullptr)
Wrapper for findRegisterDefOperandIdx, it returns a pointer to the MachineOperand rather than an inde...
LLVM_ATTRIBUTE_ALWAYS_INLINE size_type size() const
Definition: SmallVector.h:136
MachineInstr * foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, int FrameIndex, LiveIntervals *LIS=nullptr) const override
bool analyzeCompare(const MachineInstr &MI, unsigned &SrcReg, unsigned &SrcReg2, int &Mask, int &Value) const override
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
unsigned createVirtualRegister(const TargetRegisterClass *RegClass)
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:268
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:163
unsigned getReg() const
getReg - Returns the register number.
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
unsigned getSubReg() const
bool hasLoadStoreOnCond() const
static void eraseIfDead(MachineInstr *MI, const MachineRegisterInfo *MRI)
constexpr bool isInt< 8 >(int64_t x)
Definition: MathExtras.h:295
uint64_t getSize() const
Return the size in bytes of the memory reference.
bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, unsigned ExtraPredCycles, BranchProbability Probability) const override
constexpr bool isInt< 16 >(int64_t x)
Definition: MathExtras.h:298
STATISTIC(NumFunctions, "Total number of functions")
A debug info location.
Definition: DebugLoc.h:34
void setIsDead(bool Val=true)
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
unsigned isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override
MachineInstr * CreateMachineInstr(const MCInstrDesc &MCID, const DebugLoc &DL, bool NoImp=false)
CreateMachineInstr - Allocate a new MachineInstr.
const unsigned CCMASK_ICMP
Definition: SystemZ.h:47
bool PredicateInstruction(MachineInstr &MI, ArrayRef< MachineOperand > Pred) const override
bool FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, unsigned Reg, MachineRegisterInfo *MRI) const override
return AArch64::GPR64RegClass contains(Reg)
static uint64_t allOnes(unsigned int Count)
This class represents the liveness of a register, stack slot, etc.
Definition: LiveInterval.h:157
bool areMemAccessesTriviallyDisjoint(MachineInstr &MIa, MachineInstr &MIb, AliasAnalysis *AA=nullptr) const override
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const override
static bool removeIPMBasedCompare(MachineInstr &Compare, unsigned SrcReg, const MachineRegisterInfo *MRI, const TargetRegisterInfo *TRI)
void eraseFromParent()
This method unlinks &#39;this&#39; from the containing function and deletes it.
A description of a memory reference used in the backend.
unsigned getNumOperands() const
Access to explicit operands of the instruction.
Definition: MachineInstr.h:293
const TargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
VNInfo::Allocator & getVNInfoAllocator()
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
void eraseFromParent()
Unlink &#39;this&#39; from the containing basic block and delete it.
Reg
All possible values of the reg field in the ModR/M byte.
SlotIndex getInstructionIndex(const MachineInstr &MI) const
Returns the base index for the given instruction.
Definition: SlotIndexes.h:414
unsigned getLoadAndTest(unsigned Opcode) const
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:290
const char * getSymbolName() const
unsigned getLoadAndTrap(unsigned Opcode) const
INLINEASM - Represents an inline asm block.
Definition: ISDOpcodes.h:634
bool optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg, unsigned SrcReg2, int Mask, int Value, const MachineRegisterInfo *MRI) const override
void RemoveOperand(unsigned i)
Erase an operand from an instruction, leaving it with one fewer operand than it started with...
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
Definition: MachineInstr.h:287
static LogicOp interpretAndImmediate(unsigned Opcode)
SlotIndex getRegSlot(bool EC=false) const
Returns the register use/def slot in the current instruction for a normal or early-clobber def...
Definition: SlotIndexes.h:255
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
bool isPredicable(const MachineInstr &MI) const override
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:33
const MachineOperand * Target
iterator getLastNonDebugInstr()
Returns an iterator to the last non-debug instruction in the basic block, or end().
const unsigned CCMASK_ANY
Definition: SystemZ.h:31
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
unsigned getUndefRegState(bool B)
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
bool isStackSlotCopy(const MachineInstr &MI, int &DestFrameIndex, int &SrcFrameIndex) const override
const TargetRegisterClass * constrainRegClass(unsigned Reg, const TargetRegisterClass *RC, unsigned MinNumRegs=0)
constrainRegClass - Constrain the register class of the specified virtual register to be a common sub...
unsigned getKillRegState(bool B)
void ChangeToImmediate(int64_t ImmVal)
ChangeToImmediate - Replace this operand with a new immediate operand of the specified value...
Flag
These should be considered private to the implementation of the MCInstrDesc class.
Definition: MCInstrDesc.h:121
const Value * getValue() const
Return the base address of the memory access.
MachineInstr * commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned CommuteOpIdx1, unsigned CommuteOpIdx2) const override
Commutes the operands in the given instruction by changing the operands order and/or changing the ins...
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
virtual MachineInstr * commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned OpIdx1, unsigned OpIdx2) const
This method commutes the operands of the given machine instruction MI.
static void transferDeadCC(MachineInstr *OldMI, MachineInstr *NewMI)
Control flow instructions. These all have token chains.
Definition: ISDOpcodes.h:596
constexpr bool isUInt< 8 >(uint64_t x)
Definition: MathExtras.h:335
unsigned const MachineRegisterInfo * MRI
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:46
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
static unsigned getAccessSize(unsigned int Flags)
bool isCompare(QueryType Type=IgnoreBundle) const
Return true if this instruction is a comparison.
Definition: MachineInstr.h:519
bool liveAt(SlotIndex index) const
Definition: LiveInterval.h:389
bool registerDefIsDead(unsigned Reg, const TargetRegisterInfo *TRI=nullptr) const
Returns true if the register is dead in this machine instruction.
Definition: MachineInstr.h:972
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
MachineInstrBuilder & UseMI
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:149
unsigned getOpcodeForOffset(unsigned Opcode, int64_t Offset) const
const MCAsmInfo * getMCAsmInfo() const
Return target specific asm information.
bool hasOneMemOperand() const
Return true if this instruction has exactly one MachineMemOperand.
Definition: MachineInstr.h:404
const MachineInstrBuilder & addRegMask(const uint32_t *Mask) const
bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, BranchProbability Probability) const override
const PseudoSourceValue * getPseudoValue() const
static const unsigned End
void setImm(int64_t immVal)
self_iterator getIterator()
Definition: ilist_node.h:82
const MachineInstrBuilder & addFrameIndex(int Idx) const
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg, int FrameIdx, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
static bool isImmLH(uint64_t Val)
Definition: SystemZ.h:150
T findFirstSet(T Val, ZeroBehavior ZB=ZB_Max)
Get the index of the first set bit starting from the least significant bit.
Definition: MathExtras.h:195
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
unsigned getNumExplicitOperands() const
Returns the number of non-implicit operands.
void setIsKill(bool Val=true)
static const MachineInstrBuilder & addFrameReference(const MachineInstrBuilder &MIB, int FI, int Offset=0, bool mem=true)
addFrameReference - This function is used to add a reference to the base of an abstract object on the...
static bool isHighReg(unsigned int Reg)
Iterator for intrusive lists based on ilist_node.
void replaceKillInstruction(unsigned Reg, MachineInstr &OldMI, MachineInstr &NewMI)
replaceKillInstruction - Update register kill info by replacing a kill instruction with a new one...
void setDesc(const MCInstrDesc &tid)
Replace the instruction descriptor (thus opcode) of the current instruction with a new one...
constexpr bool isInt< 32 >(int64_t x)
Definition: MathExtras.h:301
unsigned getMaxCallFrameSize() const
Return the maximum size of a call frame that must be allocated for an outgoing function call...
mmo_iterator memoperands_begin() const
Access to memory operands of the instruction.
Definition: MachineInstr.h:389
MachineInstr * CloneMachineInstr(const MachineInstr *Orig)
Create a new MachineInstr which is a copy of Orig, identical in all ways except the instruction has n...
MachineOperand class - Representation of each machine instruction operand.
MachineInstrBuilder MachineInstrBuilder & DefMI
static bool isStringOfOnes(uint64_t Mask, unsigned &LSB, unsigned &Length)
const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const
const unsigned CCMASK_CMP_NE
Definition: SystemZ.h:38
MachineInstr * convertToThreeAddress(MachineFunction::iterator &MFI, MachineInstr &MI, LiveVariables *LV) const override
int64_t getImm() const
bool isLayoutSuccessor(const MachineBasicBlock *MBB) const
Return true if the specified MBB will be emitted immediately after this block, such that if this bloc...
MachineInstr * getUniqueVRegDef(unsigned Reg) const
getUniqueVRegDef - Return the unique machine instr that defines the specified virtual register or nul...
const uint32_t * getRegMask() const
getRegMask - Returns a bit mask of registers preserved by this RegMask operand.
Special value supplied for machine level alias analysis.
bool isValid() const
isValid - returns true if this iterator is not yet at the end.
static MachineInstr * finishConvertToThreeAddress(MachineInstr *OldMI, MachineInstr *NewMI, LiveVariables *LV)
static int isSimpleMove(const MachineInstr &MI, int &FrameIndex, unsigned Flag)
bool canInsertSelect(const MachineBasicBlock &, ArrayRef< MachineOperand > Cond, unsigned, unsigned, int &, int &, int &) const override
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:139
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
void getLoadStoreOpcodes(const TargetRegisterClass *RC, unsigned &LoadOpcode, unsigned &StoreOpcode) const
Representation of each machine instruction.
Definition: MachineInstr.h:59
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
static MachineInstr * getDef(unsigned Reg, const MachineRegisterInfo *MRI)
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
unsigned getInstSizeInBytes(const MachineInstr &MI) const override
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
LLVM_NODISCARD bool empty() const
Definition: SmallVector.h:61
VNInfo * createDeadDef(SlotIndex Def, VNInfo::Allocator &VNInfoAllocator)
createDeadDef - Make sure the range has a value defined at Def.
unsigned getFusedCompare(unsigned Opcode, SystemZII::FusedCompareType Type, const MachineInstr *MI=nullptr) const
void setReg(unsigned Reg)
Change the register this operand corresponds to.
static MachineOperand CreateImm(int64_t Val)
#define I(x, y, z)
Definition: MD5.cpp:58
bool isFI() const
isFI - Tests if this is a MO_FrameIndex operand.
static bool isSimpleBD12Move(const MachineInstr *MI, unsigned Flag)
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
bool hasOneNonDBGUse(unsigned RegNo) const
hasOneNonDBGUse - Return true if there is exactly one non-Debug instruction using the specified regis...
SlotIndexes * getSlotIndexes() const
bool isReg() const
isReg - Tests if this is a MO_Register operand.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
SystemZII::Branch getBranchInfo(const MachineInstr &MI) const
int64_t getOffset() const
For normal values, this is a byte offset added to the base address.
LLVM Value Representation.
Definition: Value.h:73
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
static bool isShift(MachineInstr *MI, unsigned Opcode, int64_t Imm)
constexpr char Size[]
Key for Kernel::Arg::Metadata::mSize.
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E&#39;s largest value.
Definition: BitmaskEnum.h:81
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
static bool isImmLL(uint64_t Val)
Definition: SystemZ.h:145
bool isRxSBGMask(uint64_t Mask, unsigned BitSize, unsigned &Start, unsigned &End) const
IRTranslator LLVM IR MI
bool isMBB() const
isMBB - Tests if this is a MO_MachineBasicBlock operand.
unsigned getRegSizeInBits(const TargetRegisterClass &RC) const
Return the size in bits of a register from class RC.
const unsigned IPM_CC
Definition: SystemZ.h:96
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned char TargetFlags=0) const
bool hasLoadStoreOnCond2() const
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:295
unsigned isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override
SlotIndex - An opaque wrapper around machine indexes.
Definition: SlotIndexes.h:84
LiveRange & getRegUnit(unsigned Unit)
Return the live range for register unit Unit.
bool empty() const
empty - Check if the array is empty.
Definition: ArrayRef.h:144
unsigned getSize() const
Return the number of bytes in the encoding of this instruction, or zero if the encoding size cannot b...
Definition: MCInstrDesc.h:569
void tieOperands(unsigned DefIdx, unsigned UseIdx)
Add a tie between the register operands at DefIdx and UseIdx.