LLVM  9.0.0svn
SystemZInstrInfo.cpp
Go to the documentation of this file.
1 //===-- SystemZInstrInfo.cpp - SystemZ instruction information ------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the SystemZ implementation of the TargetInstrInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "SystemZInstrInfo.h"
15 #include "SystemZ.h"
16 #include "SystemZInstrBuilder.h"
17 #include "SystemZSubtarget.h"
18 #include "llvm/ADT/Statistic.h"
32 #include "llvm/MC/MCInstrDesc.h"
33 #include "llvm/MC/MCRegisterInfo.h"
38 #include <cassert>
39 #include <cstdint>
40 #include <iterator>
41 
42 using namespace llvm;
43 
44 #define GET_INSTRINFO_CTOR_DTOR
45 #define GET_INSTRMAP_INFO
46 #include "SystemZGenInstrInfo.inc"
47 
48 #define DEBUG_TYPE "systemz-II"
49 STATISTIC(LOCRMuxJumps, "Number of LOCRMux jump-sequences (lower is better)");
50 
51 // Return a mask with Count low bits set.
52 static uint64_t allOnes(unsigned int Count) {
53  return Count == 0 ? 0 : (uint64_t(1) << (Count - 1) << 1) - 1;
54 }
55 
56 // Reg should be a 32-bit GPR. Return true if it is a high register rather
57 // than a low register.
58 static bool isHighReg(unsigned int Reg) {
59  if (SystemZ::GRH32BitRegClass.contains(Reg))
60  return true;
61  assert(SystemZ::GR32BitRegClass.contains(Reg) && "Invalid GRX32");
62  return false;
63 }
64 
65 // Pin the vtable to this file.
66 void SystemZInstrInfo::anchor() {}
67 
69  : SystemZGenInstrInfo(SystemZ::ADJCALLSTACKDOWN, SystemZ::ADJCALLSTACKUP),
70  RI(), STI(sti) {
71 }
72 
73 // MI is a 128-bit load or store. Split it into two 64-bit loads or stores,
74 // each having the opcode given by NewOpcode.
75 void SystemZInstrInfo::splitMove(MachineBasicBlock::iterator MI,
76  unsigned NewOpcode) const {
77  MachineBasicBlock *MBB = MI->getParent();
78  MachineFunction &MF = *MBB->getParent();
79 
80  // Get two load or store instructions. Use the original instruction for one
81  // of them (arbitrarily the second here) and create a clone for the other.
82  MachineInstr *EarlierMI = MF.CloneMachineInstr(&*MI);
83  MBB->insert(MI, EarlierMI);
84 
85  // Set up the two 64-bit registers and remember super reg and its flags.
86  MachineOperand &HighRegOp = EarlierMI->getOperand(0);
87  MachineOperand &LowRegOp = MI->getOperand(0);
88  unsigned Reg128 = LowRegOp.getReg();
89  unsigned Reg128Killed = getKillRegState(LowRegOp.isKill());
90  unsigned Reg128Undef = getUndefRegState(LowRegOp.isUndef());
91  HighRegOp.setReg(RI.getSubReg(HighRegOp.getReg(), SystemZ::subreg_h64));
92  LowRegOp.setReg(RI.getSubReg(LowRegOp.getReg(), SystemZ::subreg_l64));
93 
94  if (MI->mayStore()) {
95  // Add implicit uses of the super register in case one of the subregs is
96  // undefined. We could track liveness and skip storing an undefined
97  // subreg, but this is hopefully rare (discovered with llvm-stress).
98  // If Reg128 was killed, set kill flag on MI.
99  unsigned Reg128UndefImpl = (Reg128Undef | RegState::Implicit);
100  MachineInstrBuilder(MF, EarlierMI).addReg(Reg128, Reg128UndefImpl);
101  MachineInstrBuilder(MF, MI).addReg(Reg128, (Reg128UndefImpl | Reg128Killed));
102  }
103 
104  // The address in the first (high) instruction is already correct.
105  // Adjust the offset in the second (low) instruction.
106  MachineOperand &HighOffsetOp = EarlierMI->getOperand(2);
107  MachineOperand &LowOffsetOp = MI->getOperand(2);
108  LowOffsetOp.setImm(LowOffsetOp.getImm() + 8);
109 
110  // Clear the kill flags on the registers in the first instruction.
111  if (EarlierMI->getOperand(0).isReg() && EarlierMI->getOperand(0).isUse())
112  EarlierMI->getOperand(0).setIsKill(false);
113  EarlierMI->getOperand(1).setIsKill(false);
114  EarlierMI->getOperand(3).setIsKill(false);
115 
116  // Set the opcodes.
117  unsigned HighOpcode = getOpcodeForOffset(NewOpcode, HighOffsetOp.getImm());
118  unsigned LowOpcode = getOpcodeForOffset(NewOpcode, LowOffsetOp.getImm());
119  assert(HighOpcode && LowOpcode && "Both offsets should be in range");
120 
121  EarlierMI->setDesc(get(HighOpcode));
122  MI->setDesc(get(LowOpcode));
123 }
124 
125 // Split ADJDYNALLOC instruction MI.
126 void SystemZInstrInfo::splitAdjDynAlloc(MachineBasicBlock::iterator MI) const {
127  MachineBasicBlock *MBB = MI->getParent();
128  MachineFunction &MF = *MBB->getParent();
129  MachineFrameInfo &MFFrame = MF.getFrameInfo();
130  MachineOperand &OffsetMO = MI->getOperand(2);
131 
132  uint64_t Offset = (MFFrame.getMaxCallFrameSize() +
134  OffsetMO.getImm());
135  unsigned NewOpcode = getOpcodeForOffset(SystemZ::LA, Offset);
136  assert(NewOpcode && "No support for huge argument lists yet");
137  MI->setDesc(get(NewOpcode));
138  OffsetMO.setImm(Offset);
139 }
140 
141 // MI is an RI-style pseudo instruction. Replace it with LowOpcode
142 // if the first operand is a low GR32 and HighOpcode if the first operand
143 // is a high GR32. ConvertHigh is true if LowOpcode takes a signed operand
144 // and HighOpcode takes an unsigned 32-bit operand. In those cases,
145 // MI has the same kind of operand as LowOpcode, so needs to be converted
146 // if HighOpcode is used.
147 void SystemZInstrInfo::expandRIPseudo(MachineInstr &MI, unsigned LowOpcode,
148  unsigned HighOpcode,
149  bool ConvertHigh) const {
150  unsigned Reg = MI.getOperand(0).getReg();
151  bool IsHigh = isHighReg(Reg);
152  MI.setDesc(get(IsHigh ? HighOpcode : LowOpcode));
153  if (IsHigh && ConvertHigh)
154  MI.getOperand(1).setImm(uint32_t(MI.getOperand(1).getImm()));
155 }
156 
157 // MI is a three-operand RIE-style pseudo instruction. Replace it with
158 // LowOpcodeK if the registers are both low GR32s, otherwise use a move
159 // followed by HighOpcode or LowOpcode, depending on whether the target
160 // is a high or low GR32.
161 void SystemZInstrInfo::expandRIEPseudo(MachineInstr &MI, unsigned LowOpcode,
162  unsigned LowOpcodeK,
163  unsigned HighOpcode) const {
164  unsigned DestReg = MI.getOperand(0).getReg();
165  unsigned SrcReg = MI.getOperand(1).getReg();
166  bool DestIsHigh = isHighReg(DestReg);
167  bool SrcIsHigh = isHighReg(SrcReg);
168  if (!DestIsHigh && !SrcIsHigh)
169  MI.setDesc(get(LowOpcodeK));
170  else {
171  emitGRX32Move(*MI.getParent(), MI, MI.getDebugLoc(), DestReg, SrcReg,
172  SystemZ::LR, 32, MI.getOperand(1).isKill(),
173  MI.getOperand(1).isUndef());
174  MI.setDesc(get(DestIsHigh ? HighOpcode : LowOpcode));
175  MI.getOperand(1).setReg(DestReg);
176  MI.tieOperands(0, 1);
177  }
178 }
179 
180 // MI is an RXY-style pseudo instruction. Replace it with LowOpcode
181 // if the first operand is a low GR32 and HighOpcode if the first operand
182 // is a high GR32.
183 void SystemZInstrInfo::expandRXYPseudo(MachineInstr &MI, unsigned LowOpcode,
184  unsigned HighOpcode) const {
185  unsigned Reg = MI.getOperand(0).getReg();
186  unsigned Opcode = getOpcodeForOffset(isHighReg(Reg) ? HighOpcode : LowOpcode,
187  MI.getOperand(2).getImm());
188  MI.setDesc(get(Opcode));
189 }
190 
191 // MI is a load-on-condition pseudo instruction with a single register
192 // (source or destination) operand. Replace it with LowOpcode if the
193 // register is a low GR32 and HighOpcode if the register is a high GR32.
194 void SystemZInstrInfo::expandLOCPseudo(MachineInstr &MI, unsigned LowOpcode,
195  unsigned HighOpcode) const {
196  unsigned Reg = MI.getOperand(0).getReg();
197  unsigned Opcode = isHighReg(Reg) ? HighOpcode : LowOpcode;
198  MI.setDesc(get(Opcode));
199 }
200 
201 // MI is a load-register-on-condition pseudo instruction. Replace it with
202 // LowOpcode if source and destination are both low GR32s and HighOpcode if
203 // source and destination are both high GR32s.
204 void SystemZInstrInfo::expandLOCRPseudo(MachineInstr &MI, unsigned LowOpcode,
205  unsigned HighOpcode) const {
206  unsigned DestReg = MI.getOperand(0).getReg();
207  unsigned SrcReg = MI.getOperand(2).getReg();
208  bool DestIsHigh = isHighReg(DestReg);
209  bool SrcIsHigh = isHighReg(SrcReg);
210 
211  if (!DestIsHigh && !SrcIsHigh)
212  MI.setDesc(get(LowOpcode));
213  else if (DestIsHigh && SrcIsHigh)
214  MI.setDesc(get(HighOpcode));
215  else
216  LOCRMuxJumps++;
217 
218  // If we were unable to implement the pseudo with a single instruction, we
219  // need to convert it back into a branch sequence. This cannot be done here
220  // since the caller of expandPostRAPseudo does not handle changes to the CFG
221  // correctly. This change is defered to the SystemZExpandPseudo pass.
222 }
223 
224 // MI is an RR-style pseudo instruction that zero-extends the low Size bits
225 // of one GRX32 into another. Replace it with LowOpcode if both operands
226 // are low registers, otherwise use RISB[LH]G.
227 void SystemZInstrInfo::expandZExtPseudo(MachineInstr &MI, unsigned LowOpcode,
228  unsigned Size) const {
229  MachineInstrBuilder MIB =
230  emitGRX32Move(*MI.getParent(), MI, MI.getDebugLoc(),
231  MI.getOperand(0).getReg(), MI.getOperand(1).getReg(), LowOpcode,
232  Size, MI.getOperand(1).isKill(), MI.getOperand(1).isUndef());
233 
234  // Keep the remaining operands as-is.
235  for (unsigned I = 2; I < MI.getNumOperands(); ++I)
236  MIB.add(MI.getOperand(I));
237 
238  MI.eraseFromParent();
239 }
240 
241 void SystemZInstrInfo::expandLoadStackGuard(MachineInstr *MI) const {
242  MachineBasicBlock *MBB = MI->getParent();
243  MachineFunction &MF = *MBB->getParent();
244  const unsigned Reg64 = MI->getOperand(0).getReg();
245  const unsigned Reg32 = RI.getSubReg(Reg64, SystemZ::subreg_l32);
246 
247  // EAR can only load the low subregister so us a shift for %a0 to produce
248  // the GR containing %a0 and %a1.
249 
250  // ear <reg>, %a0
251  BuildMI(*MBB, MI, MI->getDebugLoc(), get(SystemZ::EAR), Reg32)
252  .addReg(SystemZ::A0)
254 
255  // sllg <reg>, <reg>, 32
256  BuildMI(*MBB, MI, MI->getDebugLoc(), get(SystemZ::SLLG), Reg64)
257  .addReg(Reg64)
258  .addReg(0)
259  .addImm(32);
260 
261  // ear <reg>, %a1
262  BuildMI(*MBB, MI, MI->getDebugLoc(), get(SystemZ::EAR), Reg32)
263  .addReg(SystemZ::A1);
264 
265  // lg <reg>, 40(<reg>)
266  MI->setDesc(get(SystemZ::LG));
267  MachineInstrBuilder(MF, MI).addReg(Reg64).addImm(40).addReg(0);
268 }
269 
270 // Emit a zero-extending move from 32-bit GPR SrcReg to 32-bit GPR
271 // DestReg before MBBI in MBB. Use LowLowOpcode when both DestReg and SrcReg
272 // are low registers, otherwise use RISB[LH]G. Size is the number of bits
273 // taken from the low end of SrcReg (8 for LLCR, 16 for LLHR and 32 for LR).
274 // KillSrc is true if this move is the last use of SrcReg.
276 SystemZInstrInfo::emitGRX32Move(MachineBasicBlock &MBB,
278  const DebugLoc &DL, unsigned DestReg,
279  unsigned SrcReg, unsigned LowLowOpcode,
280  unsigned Size, bool KillSrc,
281  bool UndefSrc) const {
282  unsigned Opcode;
283  bool DestIsHigh = isHighReg(DestReg);
284  bool SrcIsHigh = isHighReg(SrcReg);
285  if (DestIsHigh && SrcIsHigh)
286  Opcode = SystemZ::RISBHH;
287  else if (DestIsHigh && !SrcIsHigh)
288  Opcode = SystemZ::RISBHL;
289  else if (!DestIsHigh && SrcIsHigh)
290  Opcode = SystemZ::RISBLH;
291  else {
292  return BuildMI(MBB, MBBI, DL, get(LowLowOpcode), DestReg)
293  .addReg(SrcReg, getKillRegState(KillSrc) | getUndefRegState(UndefSrc));
294  }
295  unsigned Rotate = (DestIsHigh != SrcIsHigh ? 32 : 0);
296  return BuildMI(MBB, MBBI, DL, get(Opcode), DestReg)
297  .addReg(DestReg, RegState::Undef)
298  .addReg(SrcReg, getKillRegState(KillSrc) | getUndefRegState(UndefSrc))
299  .addImm(32 - Size).addImm(128 + 31).addImm(Rotate);
300 }
301 
303  bool NewMI,
304  unsigned OpIdx1,
305  unsigned OpIdx2) const {
306  auto cloneIfNew = [NewMI](MachineInstr &MI) -> MachineInstr & {
307  if (NewMI)
308  return *MI.getParent()->getParent()->CloneMachineInstr(&MI);
309  return MI;
310  };
311 
312  switch (MI.getOpcode()) {
313  case SystemZ::LOCRMux:
314  case SystemZ::LOCFHR:
315  case SystemZ::LOCR:
316  case SystemZ::LOCGR: {
317  auto &WorkingMI = cloneIfNew(MI);
318  // Invert condition.
319  unsigned CCValid = WorkingMI.getOperand(3).getImm();
320  unsigned CCMask = WorkingMI.getOperand(4).getImm();
321  WorkingMI.getOperand(4).setImm(CCMask ^ CCValid);
322  return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
323  OpIdx1, OpIdx2);
324  }
325  default:
326  return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
327  }
328 }
329 
330 // If MI is a simple load or store for a frame object, return the register
331 // it loads or stores and set FrameIndex to the index of the frame object.
332 // Return 0 otherwise.
333 //
334 // Flag is SimpleBDXLoad for loads and SimpleBDXStore for stores.
335 static int isSimpleMove(const MachineInstr &MI, int &FrameIndex,
336  unsigned Flag) {
337  const MCInstrDesc &MCID = MI.getDesc();
338  if ((MCID.TSFlags & Flag) && MI.getOperand(1).isFI() &&
339  MI.getOperand(2).getImm() == 0 && MI.getOperand(3).getReg() == 0) {
340  FrameIndex = MI.getOperand(1).getIndex();
341  return MI.getOperand(0).getReg();
342  }
343  return 0;
344 }
345 
347  int &FrameIndex) const {
348  return isSimpleMove(MI, FrameIndex, SystemZII::SimpleBDXLoad);
349 }
350 
352  int &FrameIndex) const {
353  return isSimpleMove(MI, FrameIndex, SystemZII::SimpleBDXStore);
354 }
355 
357  int &DestFrameIndex,
358  int &SrcFrameIndex) const {
359  // Check for MVC 0(Length,FI1),0(FI2)
360  const MachineFrameInfo &MFI = MI.getParent()->getParent()->getFrameInfo();
361  if (MI.getOpcode() != SystemZ::MVC || !MI.getOperand(0).isFI() ||
362  MI.getOperand(1).getImm() != 0 || !MI.getOperand(3).isFI() ||
363  MI.getOperand(4).getImm() != 0)
364  return false;
365 
366  // Check that Length covers the full slots.
367  int64_t Length = MI.getOperand(2).getImm();
368  unsigned FI1 = MI.getOperand(0).getIndex();
369  unsigned FI2 = MI.getOperand(3).getIndex();
370  if (MFI.getObjectSize(FI1) != Length ||
371  MFI.getObjectSize(FI2) != Length)
372  return false;
373 
374  DestFrameIndex = FI1;
375  SrcFrameIndex = FI2;
376  return true;
377 }
378 
380  MachineBasicBlock *&TBB,
381  MachineBasicBlock *&FBB,
383  bool AllowModify) const {
384  // Most of the code and comments here are boilerplate.
385 
386  // Start from the bottom of the block and work up, examining the
387  // terminator instructions.
389  while (I != MBB.begin()) {
390  --I;
391  if (I->isDebugInstr())
392  continue;
393 
394  // Working from the bottom, when we see a non-terminator instruction, we're
395  // done.
396  if (!isUnpredicatedTerminator(*I))
397  break;
398 
399  // A terminator that isn't a branch can't easily be handled by this
400  // analysis.
401  if (!I->isBranch())
402  return true;
403 
404  // Can't handle indirect branches.
406  if (!Branch.Target->isMBB())
407  return true;
408 
409  // Punt on compound branches.
410  if (Branch.Type != SystemZII::BranchNormal)
411  return true;
412 
413  if (Branch.CCMask == SystemZ::CCMASK_ANY) {
414  // Handle unconditional branches.
415  if (!AllowModify) {
416  TBB = Branch.Target->getMBB();
417  continue;
418  }
419 
420  // If the block has any instructions after a JMP, delete them.
421  while (std::next(I) != MBB.end())
422  std::next(I)->eraseFromParent();
423 
424  Cond.clear();
425  FBB = nullptr;
426 
427  // Delete the JMP if it's equivalent to a fall-through.
428  if (MBB.isLayoutSuccessor(Branch.Target->getMBB())) {
429  TBB = nullptr;
430  I->eraseFromParent();
431  I = MBB.end();
432  continue;
433  }
434 
435  // TBB is used to indicate the unconditinal destination.
436  TBB = Branch.Target->getMBB();
437  continue;
438  }
439 
440  // Working from the bottom, handle the first conditional branch.
441  if (Cond.empty()) {
442  // FIXME: add X86-style branch swap
443  FBB = TBB;
444  TBB = Branch.Target->getMBB();
447  continue;
448  }
449 
450  // Handle subsequent conditional branches.
451  assert(Cond.size() == 2 && TBB && "Should have seen a conditional branch");
452 
453  // Only handle the case where all conditional branches branch to the same
454  // destination.
455  if (TBB != Branch.Target->getMBB())
456  return true;
457 
458  // If the conditions are the same, we can leave them alone.
459  unsigned OldCCValid = Cond[0].getImm();
460  unsigned OldCCMask = Cond[1].getImm();
461  if (OldCCValid == Branch.CCValid && OldCCMask == Branch.CCMask)
462  continue;
463 
464  // FIXME: Try combining conditions like X86 does. Should be easy on Z!
465  return false;
466  }
467 
468  return false;
469 }
470 
472  int *BytesRemoved) const {
473  assert(!BytesRemoved && "code size not handled");
474 
475  // Most of the code and comments here are boilerplate.
477  unsigned Count = 0;
478 
479  while (I != MBB.begin()) {
480  --I;
481  if (I->isDebugInstr())
482  continue;
483  if (!I->isBranch())
484  break;
485  if (!getBranchInfo(*I).Target->isMBB())
486  break;
487  // Remove the branch.
488  I->eraseFromParent();
489  I = MBB.end();
490  ++Count;
491  }
492 
493  return Count;
494 }
495 
498  assert(Cond.size() == 2 && "Invalid condition");
499  Cond[1].setImm(Cond[1].getImm() ^ Cond[0].getImm());
500  return false;
501 }
502 
504  MachineBasicBlock *TBB,
505  MachineBasicBlock *FBB,
507  const DebugLoc &DL,
508  int *BytesAdded) const {
509  // In this function we output 32-bit branches, which should always
510  // have enough range. They can be shortened and relaxed by later code
511  // in the pipeline, if desired.
512 
513  // Shouldn't be a fall through.
514  assert(TBB && "insertBranch must not be told to insert a fallthrough");
515  assert((Cond.size() == 2 || Cond.size() == 0) &&
516  "SystemZ branch conditions have one component!");
517  assert(!BytesAdded && "code size not handled");
518 
519  if (Cond.empty()) {
520  // Unconditional branch?
521  assert(!FBB && "Unconditional branch with multiple successors!");
522  BuildMI(&MBB, DL, get(SystemZ::J)).addMBB(TBB);
523  return 1;
524  }
525 
526  // Conditional branch.
527  unsigned Count = 0;
528  unsigned CCValid = Cond[0].getImm();
529  unsigned CCMask = Cond[1].getImm();
530  BuildMI(&MBB, DL, get(SystemZ::BRC))
531  .addImm(CCValid).addImm(CCMask).addMBB(TBB);
532  ++Count;
533 
534  if (FBB) {
535  // Two-way Conditional branch. Insert the second branch.
536  BuildMI(&MBB, DL, get(SystemZ::J)).addMBB(FBB);
537  ++Count;
538  }
539  return Count;
540 }
541 
542 bool SystemZInstrInfo::analyzeCompare(const MachineInstr &MI, unsigned &SrcReg,
543  unsigned &SrcReg2, int &Mask,
544  int &Value) const {
545  assert(MI.isCompare() && "Caller should have checked for a comparison");
546 
547  if (MI.getNumExplicitOperands() == 2 && MI.getOperand(0).isReg() &&
548  MI.getOperand(1).isImm()) {
549  SrcReg = MI.getOperand(0).getReg();
550  SrcReg2 = 0;
551  Value = MI.getOperand(1).getImm();
552  Mask = ~0;
553  return true;
554  }
555 
556  return false;
557 }
558 
561  unsigned TrueReg, unsigned FalseReg,
562  int &CondCycles, int &TrueCycles,
563  int &FalseCycles) const {
564  // Not all subtargets have LOCR instructions.
565  if (!STI.hasLoadStoreOnCond())
566  return false;
567  if (Pred.size() != 2)
568  return false;
569 
570  // Check register classes.
571  const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
572  const TargetRegisterClass *RC =
573  RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
574  if (!RC)
575  return false;
576 
577  // We have LOCR instructions for 32 and 64 bit general purpose registers.
578  if ((STI.hasLoadStoreOnCond2() &&
579  SystemZ::GRX32BitRegClass.hasSubClassEq(RC)) ||
580  SystemZ::GR32BitRegClass.hasSubClassEq(RC) ||
581  SystemZ::GR64BitRegClass.hasSubClassEq(RC)) {
582  CondCycles = 2;
583  TrueCycles = 2;
584  FalseCycles = 2;
585  return true;
586  }
587 
588  // Can't do anything else.
589  return false;
590 }
591 
594  const DebugLoc &DL, unsigned DstReg,
596  unsigned TrueReg,
597  unsigned FalseReg) const {
599  const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
600 
601  assert(Pred.size() == 2 && "Invalid condition");
602  unsigned CCValid = Pred[0].getImm();
603  unsigned CCMask = Pred[1].getImm();
604 
605  unsigned Opc;
606  if (SystemZ::GRX32BitRegClass.hasSubClassEq(RC)) {
607  if (STI.hasLoadStoreOnCond2())
608  Opc = SystemZ::LOCRMux;
609  else {
610  Opc = SystemZ::LOCR;
611  MRI.constrainRegClass(DstReg, &SystemZ::GR32BitRegClass);
612  unsigned TReg = MRI.createVirtualRegister(&SystemZ::GR32BitRegClass);
613  unsigned FReg = MRI.createVirtualRegister(&SystemZ::GR32BitRegClass);
614  BuildMI(MBB, I, DL, get(TargetOpcode::COPY), TReg).addReg(TrueReg);
615  BuildMI(MBB, I, DL, get(TargetOpcode::COPY), FReg).addReg(FalseReg);
616  TrueReg = TReg;
617  FalseReg = FReg;
618  }
619  } else if (SystemZ::GR64BitRegClass.hasSubClassEq(RC))
620  Opc = SystemZ::LOCGR;
621  else
622  llvm_unreachable("Invalid register class");
623 
624  BuildMI(MBB, I, DL, get(Opc), DstReg)
625  .addReg(FalseReg).addReg(TrueReg)
626  .addImm(CCValid).addImm(CCMask);
627 }
628 
630  unsigned Reg,
631  MachineRegisterInfo *MRI) const {
632  unsigned DefOpc = DefMI.getOpcode();
633  if (DefOpc != SystemZ::LHIMux && DefOpc != SystemZ::LHI &&
634  DefOpc != SystemZ::LGHI)
635  return false;
636  if (DefMI.getOperand(0).getReg() != Reg)
637  return false;
638  int32_t ImmVal = (int32_t)DefMI.getOperand(1).getImm();
639 
640  unsigned UseOpc = UseMI.getOpcode();
641  unsigned NewUseOpc;
642  unsigned UseIdx;
643  int CommuteIdx = -1;
644  switch (UseOpc) {
645  case SystemZ::LOCRMux:
646  if (!STI.hasLoadStoreOnCond2())
647  return false;
648  NewUseOpc = SystemZ::LOCHIMux;
649  if (UseMI.getOperand(2).getReg() == Reg)
650  UseIdx = 2;
651  else if (UseMI.getOperand(1).getReg() == Reg)
652  UseIdx = 2, CommuteIdx = 1;
653  else
654  return false;
655  break;
656  case SystemZ::LOCGR:
657  if (!STI.hasLoadStoreOnCond2())
658  return false;
659  NewUseOpc = SystemZ::LOCGHI;
660  if (UseMI.getOperand(2).getReg() == Reg)
661  UseIdx = 2;
662  else if (UseMI.getOperand(1).getReg() == Reg)
663  UseIdx = 2, CommuteIdx = 1;
664  else
665  return false;
666  break;
667  default:
668  return false;
669  }
670 
671  if (CommuteIdx != -1)
672  if (!commuteInstruction(UseMI, false, CommuteIdx, UseIdx))
673  return false;
674 
675  bool DeleteDef = MRI->hasOneNonDBGUse(Reg);
676  UseMI.setDesc(get(NewUseOpc));
677  UseMI.getOperand(UseIdx).ChangeToImmediate(ImmVal);
678  if (DeleteDef)
679  DefMI.eraseFromParent();
680 
681  return true;
682 }
683 
685  unsigned Opcode = MI.getOpcode();
686  if (Opcode == SystemZ::Return ||
687  Opcode == SystemZ::Trap ||
688  Opcode == SystemZ::CallJG ||
689  Opcode == SystemZ::CallBR)
690  return true;
691  return false;
692 }
693 
696  unsigned NumCycles, unsigned ExtraPredCycles,
697  BranchProbability Probability) const {
698  // Avoid using conditional returns at the end of a loop (since then
699  // we'd need to emit an unconditional branch to the beginning anyway,
700  // making the loop body longer). This doesn't apply for low-probability
701  // loops (eg. compare-and-swap retry), so just decide based on branch
702  // probability instead of looping structure.
703  // However, since Compare and Trap instructions cost the same as a regular
704  // Compare instruction, we should allow the if conversion to convert this
705  // into a Conditional Compare regardless of the branch probability.
706  if (MBB.getLastNonDebugInstr()->getOpcode() != SystemZ::Trap &&
707  MBB.succ_empty() && Probability < BranchProbability(1, 8))
708  return false;
709  // For now only convert single instructions.
710  return NumCycles == 1;
711 }
712 
715  unsigned NumCyclesT, unsigned ExtraPredCyclesT,
716  MachineBasicBlock &FMBB,
717  unsigned NumCyclesF, unsigned ExtraPredCyclesF,
718  BranchProbability Probability) const {
719  // For now avoid converting mutually-exclusive cases.
720  return false;
721 }
722 
725  BranchProbability Probability) const {
726  // For now only duplicate single instructions.
727  return NumCycles == 1;
728 }
729 
731  MachineInstr &MI, ArrayRef<MachineOperand> Pred) const {
732  assert(Pred.size() == 2 && "Invalid condition");
733  unsigned CCValid = Pred[0].getImm();
734  unsigned CCMask = Pred[1].getImm();
735  assert(CCMask > 0 && CCMask < 15 && "Invalid predicate");
736  unsigned Opcode = MI.getOpcode();
737  if (Opcode == SystemZ::Trap) {
738  MI.setDesc(get(SystemZ::CondTrap));
740  .addImm(CCValid).addImm(CCMask)
741  .addReg(SystemZ::CC, RegState::Implicit);
742  return true;
743  }
744  if (Opcode == SystemZ::Return) {
745  MI.setDesc(get(SystemZ::CondReturn));
747  .addImm(CCValid).addImm(CCMask)
748  .addReg(SystemZ::CC, RegState::Implicit);
749  return true;
750  }
751  if (Opcode == SystemZ::CallJG) {
752  MachineOperand FirstOp = MI.getOperand(0);
753  const uint32_t *RegMask = MI.getOperand(1).getRegMask();
754  MI.RemoveOperand(1);
755  MI.RemoveOperand(0);
756  MI.setDesc(get(SystemZ::CallBRCL));
758  .addImm(CCValid)
759  .addImm(CCMask)
760  .add(FirstOp)
761  .addRegMask(RegMask)
762  .addReg(SystemZ::CC, RegState::Implicit);
763  return true;
764  }
765  if (Opcode == SystemZ::CallBR) {
766  const uint32_t *RegMask = MI.getOperand(0).getRegMask();
767  MI.RemoveOperand(0);
768  MI.setDesc(get(SystemZ::CallBCR));
770  .addImm(CCValid).addImm(CCMask)
771  .addRegMask(RegMask)
772  .addReg(SystemZ::CC, RegState::Implicit);
773  return true;
774  }
775  return false;
776 }
777 
780  const DebugLoc &DL, unsigned DestReg,
781  unsigned SrcReg, bool KillSrc) const {
782  // Split 128-bit GPR moves into two 64-bit moves. Add implicit uses of the
783  // super register in case one of the subregs is undefined.
784  // This handles ADDR128 too.
785  if (SystemZ::GR128BitRegClass.contains(DestReg, SrcReg)) {
786  copyPhysReg(MBB, MBBI, DL, RI.getSubReg(DestReg, SystemZ::subreg_h64),
787  RI.getSubReg(SrcReg, SystemZ::subreg_h64), KillSrc);
788  MachineInstrBuilder(*MBB.getParent(), std::prev(MBBI))
789  .addReg(SrcReg, RegState::Implicit);
790  copyPhysReg(MBB, MBBI, DL, RI.getSubReg(DestReg, SystemZ::subreg_l64),
791  RI.getSubReg(SrcReg, SystemZ::subreg_l64), KillSrc);
792  MachineInstrBuilder(*MBB.getParent(), std::prev(MBBI))
793  .addReg(SrcReg, (getKillRegState(KillSrc) | RegState::Implicit));
794  return;
795  }
796 
797  if (SystemZ::GRX32BitRegClass.contains(DestReg, SrcReg)) {
798  emitGRX32Move(MBB, MBBI, DL, DestReg, SrcReg, SystemZ::LR, 32, KillSrc,
799  false);
800  return;
801  }
802 
803  // Move 128-bit floating-point values between VR128 and FP128.
804  if (SystemZ::VR128BitRegClass.contains(DestReg) &&
805  SystemZ::FP128BitRegClass.contains(SrcReg)) {
806  unsigned SrcRegHi =
807  RI.getMatchingSuperReg(RI.getSubReg(SrcReg, SystemZ::subreg_h64),
808  SystemZ::subreg_h64, &SystemZ::VR128BitRegClass);
809  unsigned SrcRegLo =
810  RI.getMatchingSuperReg(RI.getSubReg(SrcReg, SystemZ::subreg_l64),
811  SystemZ::subreg_h64, &SystemZ::VR128BitRegClass);
812 
813  BuildMI(MBB, MBBI, DL, get(SystemZ::VMRHG), DestReg)
814  .addReg(SrcRegHi, getKillRegState(KillSrc))
815  .addReg(SrcRegLo, getKillRegState(KillSrc));
816  return;
817  }
818  if (SystemZ::FP128BitRegClass.contains(DestReg) &&
819  SystemZ::VR128BitRegClass.contains(SrcReg)) {
820  unsigned DestRegHi =
821  RI.getMatchingSuperReg(RI.getSubReg(DestReg, SystemZ::subreg_h64),
822  SystemZ::subreg_h64, &SystemZ::VR128BitRegClass);
823  unsigned DestRegLo =
824  RI.getMatchingSuperReg(RI.getSubReg(DestReg, SystemZ::subreg_l64),
825  SystemZ::subreg_h64, &SystemZ::VR128BitRegClass);
826 
827  if (DestRegHi != SrcReg)
828  copyPhysReg(MBB, MBBI, DL, DestRegHi, SrcReg, false);
829  BuildMI(MBB, MBBI, DL, get(SystemZ::VREPG), DestRegLo)
830  .addReg(SrcReg, getKillRegState(KillSrc)).addImm(1);
831  return;
832  }
833 
834  // Move CC value from/to a GR32.
835  if (SrcReg == SystemZ::CC) {
836  auto MIB = BuildMI(MBB, MBBI, DL, get(SystemZ::IPM), DestReg);
837  if (KillSrc) {
838  const MachineFunction *MF = MBB.getParent();
840  MIB->addRegisterKilled(SrcReg, TRI);
841  }
842  return;
843  }
844  if (DestReg == SystemZ::CC) {
845  BuildMI(MBB, MBBI, DL, get(SystemZ::TMLH))
846  .addReg(SrcReg, getKillRegState(KillSrc))
847  .addImm(3 << (SystemZ::IPM_CC - 16));
848  return;
849  }
850 
851  // Everything else needs only one instruction.
852  unsigned Opcode;
853  if (SystemZ::GR64BitRegClass.contains(DestReg, SrcReg))
854  Opcode = SystemZ::LGR;
855  else if (SystemZ::FP32BitRegClass.contains(DestReg, SrcReg))
856  // For z13 we prefer LDR over LER to avoid partial register dependencies.
857  Opcode = STI.hasVector() ? SystemZ::LDR32 : SystemZ::LER;
858  else if (SystemZ::FP64BitRegClass.contains(DestReg, SrcReg))
859  Opcode = SystemZ::LDR;
860  else if (SystemZ::FP128BitRegClass.contains(DestReg, SrcReg))
861  Opcode = SystemZ::LXR;
862  else if (SystemZ::VR32BitRegClass.contains(DestReg, SrcReg))
863  Opcode = SystemZ::VLR32;
864  else if (SystemZ::VR64BitRegClass.contains(DestReg, SrcReg))
865  Opcode = SystemZ::VLR64;
866  else if (SystemZ::VR128BitRegClass.contains(DestReg, SrcReg))
867  Opcode = SystemZ::VLR;
868  else if (SystemZ::AR32BitRegClass.contains(DestReg, SrcReg))
869  Opcode = SystemZ::CPYA;
870  else if (SystemZ::AR32BitRegClass.contains(DestReg) &&
871  SystemZ::GR32BitRegClass.contains(SrcReg))
872  Opcode = SystemZ::SAR;
873  else if (SystemZ::GR32BitRegClass.contains(DestReg) &&
874  SystemZ::AR32BitRegClass.contains(SrcReg))
875  Opcode = SystemZ::EAR;
876  else
877  llvm_unreachable("Impossible reg-to-reg copy");
878 
879  BuildMI(MBB, MBBI, DL, get(Opcode), DestReg)
880  .addReg(SrcReg, getKillRegState(KillSrc));
881 }
882 
884  MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg,
885  bool isKill, int FrameIdx, const TargetRegisterClass *RC,
886  const TargetRegisterInfo *TRI) const {
887  DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
888 
889  // Callers may expect a single instruction, so keep 128-bit moves
890  // together for now and lower them after register allocation.
891  unsigned LoadOpcode, StoreOpcode;
892  getLoadStoreOpcodes(RC, LoadOpcode, StoreOpcode);
893  addFrameReference(BuildMI(MBB, MBBI, DL, get(StoreOpcode))
894  .addReg(SrcReg, getKillRegState(isKill)),
895  FrameIdx);
896 }
897 
899  MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg,
900  int FrameIdx, const TargetRegisterClass *RC,
901  const TargetRegisterInfo *TRI) const {
902  DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
903 
904  // Callers may expect a single instruction, so keep 128-bit moves
905  // together for now and lower them after register allocation.
906  unsigned LoadOpcode, StoreOpcode;
907  getLoadStoreOpcodes(RC, LoadOpcode, StoreOpcode);
908  addFrameReference(BuildMI(MBB, MBBI, DL, get(LoadOpcode), DestReg),
909  FrameIdx);
910 }
911 
912 // Return true if MI is a simple load or store with a 12-bit displacement
913 // and no index. Flag is SimpleBDXLoad for loads and SimpleBDXStore for stores.
914 static bool isSimpleBD12Move(const MachineInstr *MI, unsigned Flag) {
915  const MCInstrDesc &MCID = MI->getDesc();
916  return ((MCID.TSFlags & Flag) &&
917  isUInt<12>(MI->getOperand(2).getImm()) &&
918  MI->getOperand(3).getReg() == 0);
919 }
920 
921 namespace {
922 
923 struct LogicOp {
924  LogicOp() = default;
925  LogicOp(unsigned regSize, unsigned immLSB, unsigned immSize)
926  : RegSize(regSize), ImmLSB(immLSB), ImmSize(immSize) {}
927 
928  explicit operator bool() const { return RegSize; }
929 
930  unsigned RegSize = 0;
931  unsigned ImmLSB = 0;
932  unsigned ImmSize = 0;
933 };
934 
935 } // end anonymous namespace
936 
937 static LogicOp interpretAndImmediate(unsigned Opcode) {
938  switch (Opcode) {
939  case SystemZ::NILMux: return LogicOp(32, 0, 16);
940  case SystemZ::NIHMux: return LogicOp(32, 16, 16);
941  case SystemZ::NILL64: return LogicOp(64, 0, 16);
942  case SystemZ::NILH64: return LogicOp(64, 16, 16);
943  case SystemZ::NIHL64: return LogicOp(64, 32, 16);
944  case SystemZ::NIHH64: return LogicOp(64, 48, 16);
945  case SystemZ::NIFMux: return LogicOp(32, 0, 32);
946  case SystemZ::NILF64: return LogicOp(64, 0, 32);
947  case SystemZ::NIHF64: return LogicOp(64, 32, 32);
948  default: return LogicOp();
949  }
950 }
951 
952 static void transferDeadCC(MachineInstr *OldMI, MachineInstr *NewMI) {
953  if (OldMI->registerDefIsDead(SystemZ::CC)) {
954  MachineOperand *CCDef = NewMI->findRegisterDefOperand(SystemZ::CC);
955  if (CCDef != nullptr)
956  CCDef->setIsDead(true);
957  }
958 }
959 
962  MachineBasicBlock *MBB = MI.getParent();
963 
964  // Try to convert an AND into an RISBG-type instruction.
965  // TODO: It might be beneficial to select RISBG and shorten to AND instead.
966  if (LogicOp And = interpretAndImmediate(MI.getOpcode())) {
967  uint64_t Imm = MI.getOperand(2).getImm() << And.ImmLSB;
968  // AND IMMEDIATE leaves the other bits of the register unchanged.
969  Imm |= allOnes(And.RegSize) & ~(allOnes(And.ImmSize) << And.ImmLSB);
970  unsigned Start, End;
971  if (isRxSBGMask(Imm, And.RegSize, Start, End)) {
972  unsigned NewOpcode;
973  if (And.RegSize == 64) {
974  NewOpcode = SystemZ::RISBG;
975  // Prefer RISBGN if available, since it does not clobber CC.
976  if (STI.hasMiscellaneousExtensions())
977  NewOpcode = SystemZ::RISBGN;
978  } else {
979  NewOpcode = SystemZ::RISBMux;
980  Start &= 31;
981  End &= 31;
982  }
983  MachineOperand &Dest = MI.getOperand(0);
984  MachineOperand &Src = MI.getOperand(1);
985  MachineInstrBuilder MIB =
986  BuildMI(*MBB, MI, MI.getDebugLoc(), get(NewOpcode))
987  .add(Dest)
988  .addReg(0)
989  .addReg(Src.getReg(), getKillRegState(Src.isKill()),
990  Src.getSubReg())
991  .addImm(Start)
992  .addImm(End + 128)
993  .addImm(0);
994  if (LV) {
995  unsigned NumOps = MI.getNumOperands();
996  for (unsigned I = 1; I < NumOps; ++I) {
997  MachineOperand &Op = MI.getOperand(I);
998  if (Op.isReg() && Op.isKill())
999  LV->replaceKillInstruction(Op.getReg(), MI, *MIB);
1000  }
1001  }
1002  transferDeadCC(&MI, MIB);
1003  return MIB;
1004  }
1005  }
1006  return nullptr;
1007 }
1008 
1012  LiveIntervals *LIS, VirtRegMap *VRM) const {
1014  const MachineFrameInfo &MFI = MF.getFrameInfo();
1015  unsigned Size = MFI.getObjectSize(FrameIndex);
1016  unsigned Opcode = MI.getOpcode();
1017 
1018  if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
1019  if (LIS != nullptr && (Opcode == SystemZ::LA || Opcode == SystemZ::LAY) &&
1020  isInt<8>(MI.getOperand(2).getImm()) && !MI.getOperand(3).getReg()) {
1021 
1022  // Check CC liveness, since new instruction introduces a dead
1023  // def of CC.
1024  MCRegUnitIterator CCUnit(SystemZ::CC, TRI);
1025  LiveRange &CCLiveRange = LIS->getRegUnit(*CCUnit);
1026  ++CCUnit;
1027  assert(!CCUnit.isValid() && "CC only has one reg unit.");
1028  SlotIndex MISlot =
1030  if (!CCLiveRange.liveAt(MISlot)) {
1031  // LA(Y) %reg, CONST(%reg) -> AGSI %mem, CONST
1032  MachineInstr *BuiltMI = BuildMI(*InsertPt->getParent(), InsertPt,
1033  MI.getDebugLoc(), get(SystemZ::AGSI))
1034  .addFrameIndex(FrameIndex)
1035  .addImm(0)
1036  .addImm(MI.getOperand(2).getImm());
1037  BuiltMI->findRegisterDefOperand(SystemZ::CC)->setIsDead(true);
1038  CCLiveRange.createDeadDef(MISlot, LIS->getVNInfoAllocator());
1039  return BuiltMI;
1040  }
1041  }
1042  return nullptr;
1043  }
1044 
1045  // All other cases require a single operand.
1046  if (Ops.size() != 1)
1047  return nullptr;
1048 
1049  unsigned OpNum = Ops[0];
1050  assert(Size * 8 ==
1051  TRI->getRegSizeInBits(*MF.getRegInfo()
1052  .getRegClass(MI.getOperand(OpNum).getReg())) &&
1053  "Invalid size combination");
1054 
1055  if ((Opcode == SystemZ::AHI || Opcode == SystemZ::AGHI) && OpNum == 0 &&
1056  isInt<8>(MI.getOperand(2).getImm())) {
1057  // A(G)HI %reg, CONST -> A(G)SI %mem, CONST
1058  Opcode = (Opcode == SystemZ::AHI ? SystemZ::ASI : SystemZ::AGSI);
1059  MachineInstr *BuiltMI =
1060  BuildMI(*InsertPt->getParent(), InsertPt, MI.getDebugLoc(), get(Opcode))
1061  .addFrameIndex(FrameIndex)
1062  .addImm(0)
1063  .addImm(MI.getOperand(2).getImm());
1064  transferDeadCC(&MI, BuiltMI);
1065  return BuiltMI;
1066  }
1067 
1068  if ((Opcode == SystemZ::ALFI && OpNum == 0 &&
1069  isInt<8>((int32_t)MI.getOperand(2).getImm())) ||
1070  (Opcode == SystemZ::ALGFI && OpNum == 0 &&
1071  isInt<8>((int64_t)MI.getOperand(2).getImm()))) {
1072  // AL(G)FI %reg, CONST -> AL(G)SI %mem, CONST
1073  Opcode = (Opcode == SystemZ::ALFI ? SystemZ::ALSI : SystemZ::ALGSI);
1074  MachineInstr *BuiltMI =
1075  BuildMI(*InsertPt->getParent(), InsertPt, MI.getDebugLoc(), get(Opcode))
1076  .addFrameIndex(FrameIndex)
1077  .addImm(0)
1078  .addImm((int8_t)MI.getOperand(2).getImm());
1079  transferDeadCC(&MI, BuiltMI);
1080  return BuiltMI;
1081  }
1082 
1083  if ((Opcode == SystemZ::SLFI && OpNum == 0 &&
1084  isInt<8>((int32_t)-MI.getOperand(2).getImm())) ||
1085  (Opcode == SystemZ::SLGFI && OpNum == 0 &&
1086  isInt<8>((int64_t)-MI.getOperand(2).getImm()))) {
1087  // SL(G)FI %reg, CONST -> AL(G)SI %mem, -CONST
1088  Opcode = (Opcode == SystemZ::SLFI ? SystemZ::ALSI : SystemZ::ALGSI);
1089  MachineInstr *BuiltMI =
1090  BuildMI(*InsertPt->getParent(), InsertPt, MI.getDebugLoc(), get(Opcode))
1091  .addFrameIndex(FrameIndex)
1092  .addImm(0)
1093  .addImm((int8_t)-MI.getOperand(2).getImm());
1094  transferDeadCC(&MI, BuiltMI);
1095  return BuiltMI;
1096  }
1097 
1098  if (Opcode == SystemZ::LGDR || Opcode == SystemZ::LDGR) {
1099  bool Op0IsGPR = (Opcode == SystemZ::LGDR);
1100  bool Op1IsGPR = (Opcode == SystemZ::LDGR);
1101  // If we're spilling the destination of an LDGR or LGDR, store the
1102  // source register instead.
1103  if (OpNum == 0) {
1104  unsigned StoreOpcode = Op1IsGPR ? SystemZ::STG : SystemZ::STD;
1105  return BuildMI(*InsertPt->getParent(), InsertPt, MI.getDebugLoc(),
1106  get(StoreOpcode))
1107  .add(MI.getOperand(1))
1108  .addFrameIndex(FrameIndex)
1109  .addImm(0)
1110  .addReg(0);
1111  }
1112  // If we're spilling the source of an LDGR or LGDR, load the
1113  // destination register instead.
1114  if (OpNum == 1) {
1115  unsigned LoadOpcode = Op0IsGPR ? SystemZ::LG : SystemZ::LD;
1116  return BuildMI(*InsertPt->getParent(), InsertPt, MI.getDebugLoc(),
1117  get(LoadOpcode))
1118  .add(MI.getOperand(0))
1119  .addFrameIndex(FrameIndex)
1120  .addImm(0)
1121  .addReg(0);
1122  }
1123  }
1124 
1125  // Look for cases where the source of a simple store or the destination
1126  // of a simple load is being spilled. Try to use MVC instead.
1127  //
1128  // Although MVC is in practice a fast choice in these cases, it is still
1129  // logically a bytewise copy. This means that we cannot use it if the
1130  // load or store is volatile. We also wouldn't be able to use MVC if
1131  // the two memories partially overlap, but that case cannot occur here,
1132  // because we know that one of the memories is a full frame index.
1133  //
1134  // For performance reasons, we also want to avoid using MVC if the addresses
1135  // might be equal. We don't worry about that case here, because spill slot
1136  // coloring happens later, and because we have special code to remove
1137  // MVCs that turn out to be redundant.
1138  if (OpNum == 0 && MI.hasOneMemOperand()) {
1139  MachineMemOperand *MMO = *MI.memoperands_begin();
1140  if (MMO->getSize() == Size && !MMO->isVolatile() && !MMO->isAtomic()) {
1141  // Handle conversion of loads.
1143  return BuildMI(*InsertPt->getParent(), InsertPt, MI.getDebugLoc(),
1144  get(SystemZ::MVC))
1145  .addFrameIndex(FrameIndex)
1146  .addImm(0)
1147  .addImm(Size)
1148  .add(MI.getOperand(1))
1149  .addImm(MI.getOperand(2).getImm())
1150  .addMemOperand(MMO);
1151  }
1152  // Handle conversion of stores.
1154  return BuildMI(*InsertPt->getParent(), InsertPt, MI.getDebugLoc(),
1155  get(SystemZ::MVC))
1156  .add(MI.getOperand(1))
1157  .addImm(MI.getOperand(2).getImm())
1158  .addImm(Size)
1159  .addFrameIndex(FrameIndex)
1160  .addImm(0)
1161  .addMemOperand(MMO);
1162  }
1163  }
1164  }
1165 
1166  // If the spilled operand is the final one or the instruction is
1167  // commutable, try to change <INSN>R into <INSN>.
1168  unsigned NumOps = MI.getNumExplicitOperands();
1169  int MemOpcode = SystemZ::getMemOpcode(Opcode);
1170 
1171  // See if this is a 3-address instruction that is convertible to 2-address
1172  // and suitable for folding below. Only try this with virtual registers
1173  // and a provided VRM (during regalloc).
1174  bool NeedsCommute = false;
1175  if (SystemZ::getTwoOperandOpcode(Opcode) != -1 && MemOpcode != -1) {
1176  if (VRM == nullptr)
1177  MemOpcode = -1;
1178  else {
1179  assert(NumOps == 3 && "Expected two source registers.");
1180  unsigned DstReg = MI.getOperand(0).getReg();
1181  unsigned DstPhys =
1182  (TRI->isVirtualRegister(DstReg) ? VRM->getPhys(DstReg) : DstReg);
1183  unsigned SrcReg = (OpNum == 2 ? MI.getOperand(1).getReg()
1184  : ((OpNum == 1 && MI.isCommutable())
1185  ? MI.getOperand(2).getReg()
1186  : 0));
1187  if (DstPhys && !SystemZ::GRH32BitRegClass.contains(DstPhys) && SrcReg &&
1188  TRI->isVirtualRegister(SrcReg) && DstPhys == VRM->getPhys(SrcReg))
1189  NeedsCommute = (OpNum == 1);
1190  else
1191  MemOpcode = -1;
1192  }
1193  }
1194 
1195  if (MemOpcode >= 0) {
1196  if ((OpNum == NumOps - 1) || NeedsCommute) {
1197  const MCInstrDesc &MemDesc = get(MemOpcode);
1198  uint64_t AccessBytes = SystemZII::getAccessSize(MemDesc.TSFlags);
1199  assert(AccessBytes != 0 && "Size of access should be known");
1200  assert(AccessBytes <= Size && "Access outside the frame index");
1201  uint64_t Offset = Size - AccessBytes;
1202  MachineInstrBuilder MIB = BuildMI(*InsertPt->getParent(), InsertPt,
1203  MI.getDebugLoc(), get(MemOpcode));
1204  MIB.add(MI.getOperand(0));
1205  if (NeedsCommute)
1206  MIB.add(MI.getOperand(2));
1207  else
1208  for (unsigned I = 1; I < OpNum; ++I)
1209  MIB.add(MI.getOperand(I));
1210  MIB.addFrameIndex(FrameIndex).addImm(Offset);
1211  if (MemDesc.TSFlags & SystemZII::HasIndex)
1212  MIB.addReg(0);
1213  transferDeadCC(&MI, MIB);
1214  return MIB;
1215  }
1216  }
1217 
1218  return nullptr;
1219 }
1220 
1223  MachineBasicBlock::iterator InsertPt, MachineInstr &LoadMI,
1224  LiveIntervals *LIS) const {
1225  return nullptr;
1226 }
1227 
1229  switch (MI.getOpcode()) {
1230  case SystemZ::L128:
1231  splitMove(MI, SystemZ::LG);
1232  return true;
1233 
1234  case SystemZ::ST128:
1235  splitMove(MI, SystemZ::STG);
1236  return true;
1237 
1238  case SystemZ::LX:
1239  splitMove(MI, SystemZ::LD);
1240  return true;
1241 
1242  case SystemZ::STX:
1243  splitMove(MI, SystemZ::STD);
1244  return true;
1245 
1246  case SystemZ::LBMux:
1247  expandRXYPseudo(MI, SystemZ::LB, SystemZ::LBH);
1248  return true;
1249 
1250  case SystemZ::LHMux:
1251  expandRXYPseudo(MI, SystemZ::LH, SystemZ::LHH);
1252  return true;
1253 
1254  case SystemZ::LLCRMux:
1255  expandZExtPseudo(MI, SystemZ::LLCR, 8);
1256  return true;
1257 
1258  case SystemZ::LLHRMux:
1259  expandZExtPseudo(MI, SystemZ::LLHR, 16);
1260  return true;
1261 
1262  case SystemZ::LLCMux:
1263  expandRXYPseudo(MI, SystemZ::LLC, SystemZ::LLCH);
1264  return true;
1265 
1266  case SystemZ::LLHMux:
1267  expandRXYPseudo(MI, SystemZ::LLH, SystemZ::LLHH);
1268  return true;
1269 
1270  case SystemZ::LMux:
1271  expandRXYPseudo(MI, SystemZ::L, SystemZ::LFH);
1272  return true;
1273 
1274  case SystemZ::LOCMux:
1275  expandLOCPseudo(MI, SystemZ::LOC, SystemZ::LOCFH);
1276  return true;
1277 
1278  case SystemZ::LOCHIMux:
1279  expandLOCPseudo(MI, SystemZ::LOCHI, SystemZ::LOCHHI);
1280  return true;
1281 
1282  case SystemZ::LOCRMux:
1283  expandLOCRPseudo(MI, SystemZ::LOCR, SystemZ::LOCFHR);
1284  return true;
1285 
1286  case SystemZ::STCMux:
1287  expandRXYPseudo(MI, SystemZ::STC, SystemZ::STCH);
1288  return true;
1289 
1290  case SystemZ::STHMux:
1291  expandRXYPseudo(MI, SystemZ::STH, SystemZ::STHH);
1292  return true;
1293 
1294  case SystemZ::STMux:
1295  expandRXYPseudo(MI, SystemZ::ST, SystemZ::STFH);
1296  return true;
1297 
1298  case SystemZ::STOCMux:
1299  expandLOCPseudo(MI, SystemZ::STOC, SystemZ::STOCFH);
1300  return true;
1301 
1302  case SystemZ::LHIMux:
1303  expandRIPseudo(MI, SystemZ::LHI, SystemZ::IIHF, true);
1304  return true;
1305 
1306  case SystemZ::IIFMux:
1307  expandRIPseudo(MI, SystemZ::IILF, SystemZ::IIHF, false);
1308  return true;
1309 
1310  case SystemZ::IILMux:
1311  expandRIPseudo(MI, SystemZ::IILL, SystemZ::IIHL, false);
1312  return true;
1313 
1314  case SystemZ::IIHMux:
1315  expandRIPseudo(MI, SystemZ::IILH, SystemZ::IIHH, false);
1316  return true;
1317 
1318  case SystemZ::NIFMux:
1319  expandRIPseudo(MI, SystemZ::NILF, SystemZ::NIHF, false);
1320  return true;
1321 
1322  case SystemZ::NILMux:
1323  expandRIPseudo(MI, SystemZ::NILL, SystemZ::NIHL, false);
1324  return true;
1325 
1326  case SystemZ::NIHMux:
1327  expandRIPseudo(MI, SystemZ::NILH, SystemZ::NIHH, false);
1328  return true;
1329 
1330  case SystemZ::OIFMux:
1331  expandRIPseudo(MI, SystemZ::OILF, SystemZ::OIHF, false);
1332  return true;
1333 
1334  case SystemZ::OILMux:
1335  expandRIPseudo(MI, SystemZ::OILL, SystemZ::OIHL, false);
1336  return true;
1337 
1338  case SystemZ::OIHMux:
1339  expandRIPseudo(MI, SystemZ::OILH, SystemZ::OIHH, false);
1340  return true;
1341 
1342  case SystemZ::XIFMux:
1343  expandRIPseudo(MI, SystemZ::XILF, SystemZ::XIHF, false);
1344  return true;
1345 
1346  case SystemZ::TMLMux:
1347  expandRIPseudo(MI, SystemZ::TMLL, SystemZ::TMHL, false);
1348  return true;
1349 
1350  case SystemZ::TMHMux:
1351  expandRIPseudo(MI, SystemZ::TMLH, SystemZ::TMHH, false);
1352  return true;
1353 
1354  case SystemZ::AHIMux:
1355  expandRIPseudo(MI, SystemZ::AHI, SystemZ::AIH, false);
1356  return true;
1357 
1358  case SystemZ::AHIMuxK:
1359  expandRIEPseudo(MI, SystemZ::AHI, SystemZ::AHIK, SystemZ::AIH);
1360  return true;
1361 
1362  case SystemZ::AFIMux:
1363  expandRIPseudo(MI, SystemZ::AFI, SystemZ::AIH, false);
1364  return true;
1365 
1366  case SystemZ::CHIMux:
1367  expandRIPseudo(MI, SystemZ::CHI, SystemZ::CIH, false);
1368  return true;
1369 
1370  case SystemZ::CFIMux:
1371  expandRIPseudo(MI, SystemZ::CFI, SystemZ::CIH, false);
1372  return true;
1373 
1374  case SystemZ::CLFIMux:
1375  expandRIPseudo(MI, SystemZ::CLFI, SystemZ::CLIH, false);
1376  return true;
1377 
1378  case SystemZ::CMux:
1379  expandRXYPseudo(MI, SystemZ::C, SystemZ::CHF);
1380  return true;
1381 
1382  case SystemZ::CLMux:
1383  expandRXYPseudo(MI, SystemZ::CL, SystemZ::CLHF);
1384  return true;
1385 
1386  case SystemZ::RISBMux: {
1387  bool DestIsHigh = isHighReg(MI.getOperand(0).getReg());
1388  bool SrcIsHigh = isHighReg(MI.getOperand(2).getReg());
1389  if (SrcIsHigh == DestIsHigh)
1390  MI.setDesc(get(DestIsHigh ? SystemZ::RISBHH : SystemZ::RISBLL));
1391  else {
1392  MI.setDesc(get(DestIsHigh ? SystemZ::RISBHL : SystemZ::RISBLH));
1393  MI.getOperand(5).setImm(MI.getOperand(5).getImm() ^ 32);
1394  }
1395  return true;
1396  }
1397 
1398  case SystemZ::ADJDYNALLOC:
1399  splitAdjDynAlloc(MI);
1400  return true;
1401 
1402  case TargetOpcode::LOAD_STACK_GUARD:
1403  expandLoadStackGuard(&MI);
1404  return true;
1405 
1406  default:
1407  return false;
1408  }
1409 }
1410 
1412  if (MI.isInlineAsm()) {
1413  const MachineFunction *MF = MI.getParent()->getParent();
1414  const char *AsmStr = MI.getOperand(0).getSymbolName();
1415  return getInlineAsmLength(AsmStr, *MF->getTarget().getMCAsmInfo());
1416  }
1417  return MI.getDesc().getSize();
1418 }
1419 
1422  switch (MI.getOpcode()) {
1423  case SystemZ::BR:
1424  case SystemZ::BI:
1425  case SystemZ::J:
1426  case SystemZ::JG:
1429 
1430  case SystemZ::BRC:
1431  case SystemZ::BRCL:
1433  MI.getOperand(1).getImm(), &MI.getOperand(2));
1434 
1435  case SystemZ::BRCT:
1436  case SystemZ::BRCTH:
1439 
1440  case SystemZ::BRCTG:
1443 
1444  case SystemZ::CIJ:
1445  case SystemZ::CRJ:
1447  MI.getOperand(2).getImm(), &MI.getOperand(3));
1448 
1449  case SystemZ::CLIJ:
1450  case SystemZ::CLRJ:
1452  MI.getOperand(2).getImm(), &MI.getOperand(3));
1453 
1454  case SystemZ::CGIJ:
1455  case SystemZ::CGRJ:
1457  MI.getOperand(2).getImm(), &MI.getOperand(3));
1458 
1459  case SystemZ::CLGIJ:
1460  case SystemZ::CLGRJ:
1462  MI.getOperand(2).getImm(), &MI.getOperand(3));
1463 
1464  default:
1465  llvm_unreachable("Unrecognized branch opcode");
1466  }
1467 }
1468 
1470  unsigned &LoadOpcode,
1471  unsigned &StoreOpcode) const {
1472  if (RC == &SystemZ::GR32BitRegClass || RC == &SystemZ::ADDR32BitRegClass) {
1473  LoadOpcode = SystemZ::L;
1474  StoreOpcode = SystemZ::ST;
1475  } else if (RC == &SystemZ::GRH32BitRegClass) {
1476  LoadOpcode = SystemZ::LFH;
1477  StoreOpcode = SystemZ::STFH;
1478  } else if (RC == &SystemZ::GRX32BitRegClass) {
1479  LoadOpcode = SystemZ::LMux;
1480  StoreOpcode = SystemZ::STMux;
1481  } else if (RC == &SystemZ::GR64BitRegClass ||
1482  RC == &SystemZ::ADDR64BitRegClass) {
1483  LoadOpcode = SystemZ::LG;
1484  StoreOpcode = SystemZ::STG;
1485  } else if (RC == &SystemZ::GR128BitRegClass ||
1486  RC == &SystemZ::ADDR128BitRegClass) {
1487  LoadOpcode = SystemZ::L128;
1488  StoreOpcode = SystemZ::ST128;
1489  } else if (RC == &SystemZ::FP32BitRegClass) {
1490  LoadOpcode = SystemZ::LE;
1491  StoreOpcode = SystemZ::STE;
1492  } else if (RC == &SystemZ::FP64BitRegClass) {
1493  LoadOpcode = SystemZ::LD;
1494  StoreOpcode = SystemZ::STD;
1495  } else if (RC == &SystemZ::FP128BitRegClass) {
1496  LoadOpcode = SystemZ::LX;
1497  StoreOpcode = SystemZ::STX;
1498  } else if (RC == &SystemZ::VR32BitRegClass) {
1499  LoadOpcode = SystemZ::VL32;
1500  StoreOpcode = SystemZ::VST32;
1501  } else if (RC == &SystemZ::VR64BitRegClass) {
1502  LoadOpcode = SystemZ::VL64;
1503  StoreOpcode = SystemZ::VST64;
1504  } else if (RC == &SystemZ::VF128BitRegClass ||
1505  RC == &SystemZ::VR128BitRegClass) {
1506  LoadOpcode = SystemZ::VL;
1507  StoreOpcode = SystemZ::VST;
1508  } else
1509  llvm_unreachable("Unsupported regclass to load or store");
1510 }
1511 
1512 unsigned SystemZInstrInfo::getOpcodeForOffset(unsigned Opcode,
1513  int64_t Offset) const {
1514  const MCInstrDesc &MCID = get(Opcode);
1515  int64_t Offset2 = (MCID.TSFlags & SystemZII::Is128Bit ? Offset + 8 : Offset);
1516  if (isUInt<12>(Offset) && isUInt<12>(Offset2)) {
1517  // Get the instruction to use for unsigned 12-bit displacements.
1518  int Disp12Opcode = SystemZ::getDisp12Opcode(Opcode);
1519  if (Disp12Opcode >= 0)
1520  return Disp12Opcode;
1521 
1522  // All address-related instructions can use unsigned 12-bit
1523  // displacements.
1524  return Opcode;
1525  }
1526  if (isInt<20>(Offset) && isInt<20>(Offset2)) {
1527  // Get the instruction to use for signed 20-bit displacements.
1528  int Disp20Opcode = SystemZ::getDisp20Opcode(Opcode);
1529  if (Disp20Opcode >= 0)
1530  return Disp20Opcode;
1531 
1532  // Check whether Opcode allows signed 20-bit displacements.
1534  return Opcode;
1535  }
1536  return 0;
1537 }
1538 
1539 unsigned SystemZInstrInfo::getLoadAndTest(unsigned Opcode) const {
1540  switch (Opcode) {
1541  case SystemZ::L: return SystemZ::LT;
1542  case SystemZ::LY: return SystemZ::LT;
1543  case SystemZ::LG: return SystemZ::LTG;
1544  case SystemZ::LGF: return SystemZ::LTGF;
1545  case SystemZ::LR: return SystemZ::LTR;
1546  case SystemZ::LGFR: return SystemZ::LTGFR;
1547  case SystemZ::LGR: return SystemZ::LTGR;
1548  case SystemZ::LER: return SystemZ::LTEBR;
1549  case SystemZ::LDR: return SystemZ::LTDBR;
1550  case SystemZ::LXR: return SystemZ::LTXBR;
1551  case SystemZ::LCDFR: return SystemZ::LCDBR;
1552  case SystemZ::LPDFR: return SystemZ::LPDBR;
1553  case SystemZ::LNDFR: return SystemZ::LNDBR;
1554  case SystemZ::LCDFR_32: return SystemZ::LCEBR;
1555  case SystemZ::LPDFR_32: return SystemZ::LPEBR;
1556  case SystemZ::LNDFR_32: return SystemZ::LNEBR;
1557  // On zEC12 we prefer to use RISBGN. But if there is a chance to
1558  // actually use the condition code, we may turn it back into RISGB.
1559  // Note that RISBG is not really a "load-and-test" instruction,
1560  // but sets the same condition code values, so is OK to use here.
1561  case SystemZ::RISBGN: return SystemZ::RISBG;
1562  default: return 0;
1563  }
1564 }
1565 
1566 // Return true if Mask matches the regexp 0*1+0*, given that zero masks
1567 // have already been filtered out. Store the first set bit in LSB and
1568 // the number of set bits in Length if so.
1569 static bool isStringOfOnes(uint64_t Mask, unsigned &LSB, unsigned &Length) {
1570  unsigned First = findFirstSet(Mask);
1571  uint64_t Top = (Mask >> First) + 1;
1572  if ((Top & -Top) == Top) {
1573  LSB = First;
1574  Length = findFirstSet(Top);
1575  return true;
1576  }
1577  return false;
1578 }
1579 
1580 bool SystemZInstrInfo::isRxSBGMask(uint64_t Mask, unsigned BitSize,
1581  unsigned &Start, unsigned &End) const {
1582  // Reject trivial all-zero masks.
1583  Mask &= allOnes(BitSize);
1584  if (Mask == 0)
1585  return false;
1586 
1587  // Handle the 1+0+ or 0+1+0* cases. Start then specifies the index of
1588  // the msb and End specifies the index of the lsb.
1589  unsigned LSB, Length;
1590  if (isStringOfOnes(Mask, LSB, Length)) {
1591  Start = 63 - (LSB + Length - 1);
1592  End = 63 - LSB;
1593  return true;
1594  }
1595 
1596  // Handle the wrap-around 1+0+1+ cases. Start then specifies the msb
1597  // of the low 1s and End specifies the lsb of the high 1s.
1598  if (isStringOfOnes(Mask ^ allOnes(BitSize), LSB, Length)) {
1599  assert(LSB > 0 && "Bottom bit must be set");
1600  assert(LSB + Length < BitSize && "Top bit must be set");
1601  Start = 63 - (LSB - 1);
1602  End = 63 - (LSB + Length);
1603  return true;
1604  }
1605 
1606  return false;
1607 }
1608 
1609 unsigned SystemZInstrInfo::getFusedCompare(unsigned Opcode,
1611  const MachineInstr *MI) const {
1612  switch (Opcode) {
1613  case SystemZ::CHI:
1614  case SystemZ::CGHI:
1615  if (!(MI && isInt<8>(MI->getOperand(1).getImm())))
1616  return 0;
1617  break;
1618  case SystemZ::CLFI:
1619  case SystemZ::CLGFI:
1620  if (!(MI && isUInt<8>(MI->getOperand(1).getImm())))
1621  return 0;
1622  break;
1623  case SystemZ::CL:
1624  case SystemZ::CLG:
1625  if (!STI.hasMiscellaneousExtensions())
1626  return 0;
1627  if (!(MI && MI->getOperand(3).getReg() == 0))
1628  return 0;
1629  break;
1630  }
1631  switch (Type) {
1633  switch (Opcode) {
1634  case SystemZ::CR:
1635  return SystemZ::CRJ;
1636  case SystemZ::CGR:
1637  return SystemZ::CGRJ;
1638  case SystemZ::CHI:
1639  return SystemZ::CIJ;
1640  case SystemZ::CGHI:
1641  return SystemZ::CGIJ;
1642  case SystemZ::CLR:
1643  return SystemZ::CLRJ;
1644  case SystemZ::CLGR:
1645  return SystemZ::CLGRJ;
1646  case SystemZ::CLFI:
1647  return SystemZ::CLIJ;
1648  case SystemZ::CLGFI:
1649  return SystemZ::CLGIJ;
1650  default:
1651  return 0;
1652  }
1654  switch (Opcode) {
1655  case SystemZ::CR:
1656  return SystemZ::CRBReturn;
1657  case SystemZ::CGR:
1658  return SystemZ::CGRBReturn;
1659  case SystemZ::CHI:
1660  return SystemZ::CIBReturn;
1661  case SystemZ::CGHI:
1662  return SystemZ::CGIBReturn;
1663  case SystemZ::CLR:
1664  return SystemZ::CLRBReturn;
1665  case SystemZ::CLGR:
1666  return SystemZ::CLGRBReturn;
1667  case SystemZ::CLFI:
1668  return SystemZ::CLIBReturn;
1669  case SystemZ::CLGFI:
1670  return SystemZ::CLGIBReturn;
1671  default:
1672  return 0;
1673  }
1675  switch (Opcode) {
1676  case SystemZ::CR:
1677  return SystemZ::CRBCall;
1678  case SystemZ::CGR:
1679  return SystemZ::CGRBCall;
1680  case SystemZ::CHI:
1681  return SystemZ::CIBCall;
1682  case SystemZ::CGHI:
1683  return SystemZ::CGIBCall;
1684  case SystemZ::CLR:
1685  return SystemZ::CLRBCall;
1686  case SystemZ::CLGR:
1687  return SystemZ::CLGRBCall;
1688  case SystemZ::CLFI:
1689  return SystemZ::CLIBCall;
1690  case SystemZ::CLGFI:
1691  return SystemZ::CLGIBCall;
1692  default:
1693  return 0;
1694  }
1696  switch (Opcode) {
1697  case SystemZ::CR:
1698  return SystemZ::CRT;
1699  case SystemZ::CGR:
1700  return SystemZ::CGRT;
1701  case SystemZ::CHI:
1702  return SystemZ::CIT;
1703  case SystemZ::CGHI:
1704  return SystemZ::CGIT;
1705  case SystemZ::CLR:
1706  return SystemZ::CLRT;
1707  case SystemZ::CLGR:
1708  return SystemZ::CLGRT;
1709  case SystemZ::CLFI:
1710  return SystemZ::CLFIT;
1711  case SystemZ::CLGFI:
1712  return SystemZ::CLGIT;
1713  case SystemZ::CL:
1714  return SystemZ::CLT;
1715  case SystemZ::CLG:
1716  return SystemZ::CLGT;
1717  default:
1718  return 0;
1719  }
1720  }
1721  return 0;
1722 }
1723 
1724 unsigned SystemZInstrInfo::getLoadAndTrap(unsigned Opcode) const {
1725  if (!STI.hasLoadAndTrap())
1726  return 0;
1727  switch (Opcode) {
1728  case SystemZ::L:
1729  case SystemZ::LY:
1730  return SystemZ::LAT;
1731  case SystemZ::LG:
1732  return SystemZ::LGAT;
1733  case SystemZ::LFH:
1734  return SystemZ::LFHAT;
1735  case SystemZ::LLGF:
1736  return SystemZ::LLGFAT;
1737  case SystemZ::LLGT:
1738  return SystemZ::LLGTAT;
1739  }
1740  return 0;
1741 }
1742 
1745  unsigned Reg, uint64_t Value) const {
1746  DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
1747  unsigned Opcode;
1748  if (isInt<16>(Value))
1749  Opcode = SystemZ::LGHI;
1750  else if (SystemZ::isImmLL(Value))
1751  Opcode = SystemZ::LLILL;
1752  else if (SystemZ::isImmLH(Value)) {
1753  Opcode = SystemZ::LLILH;
1754  Value >>= 16;
1755  } else {
1756  assert(isInt<32>(Value) && "Huge values not handled yet");
1757  Opcode = SystemZ::LGFI;
1758  }
1759  BuildMI(MBB, MBBI, DL, get(Opcode), Reg).addImm(Value);
1760 }
1761 
1762 bool SystemZInstrInfo::
1764  const MachineInstr &MIb,
1765  AliasAnalysis *AA) const {
1766 
1767  if (!MIa.hasOneMemOperand() || !MIb.hasOneMemOperand())
1768  return false;
1769 
1770  // If mem-operands show that the same address Value is used by both
1771  // instructions, check for non-overlapping offsets and widths. Not
1772  // sure if a register based analysis would be an improvement...
1773 
1774  MachineMemOperand *MMOa = *MIa.memoperands_begin();
1775  MachineMemOperand *MMOb = *MIb.memoperands_begin();
1776  const Value *VALa = MMOa->getValue();
1777  const Value *VALb = MMOb->getValue();
1778  bool SameVal = (VALa && VALb && (VALa == VALb));
1779  if (!SameVal) {
1780  const PseudoSourceValue *PSVa = MMOa->getPseudoValue();
1781  const PseudoSourceValue *PSVb = MMOb->getPseudoValue();
1782  if (PSVa && PSVb && (PSVa == PSVb))
1783  SameVal = true;
1784  }
1785  if (SameVal) {
1786  int OffsetA = MMOa->getOffset(), OffsetB = MMOb->getOffset();
1787  int WidthA = MMOa->getSize(), WidthB = MMOb->getSize();
1788  int LowOffset = OffsetA < OffsetB ? OffsetA : OffsetB;
1789  int HighOffset = OffsetA < OffsetB ? OffsetB : OffsetA;
1790  int LowWidth = (LowOffset == OffsetA) ? WidthA : WidthB;
1791  if (LowOffset + LowWidth <= HighOffset)
1792  return true;
1793  }
1794 
1795  return false;
1796 }
uint64_t CallInst * C
void loadImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned Reg, uint64_t Value) const
const MachineInstrBuilder & add(const MachineOperand &MO) const
MachineOperand * findRegisterDefOperand(unsigned Reg, bool isDead=false, bool Overlap=false, const TargetRegisterInfo *TRI=nullptr)
Wrapper for findRegisterDefOperandIdx, it returns a pointer to the MachineOperand rather than an inde...
void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, unsigned DstReg, ArrayRef< MachineOperand > Cond, unsigned TrueReg, unsigned FalseReg) const override
bool expandPostRAPseudo(MachineInstr &MBBI) const override
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
MachineBasicBlock * getMBB() const
const int64_t CallFrameSize
const TargetRegisterClass * getRegClass(unsigned Reg) const
Return the register class of the specified virtual register.
SystemZInstrInfo(SystemZSubtarget &STI)
This class represents lattice values for constants.
Definition: AllocatorList.h:23
bool analyzeCompare(const MachineInstr &MI, unsigned &SrcReg, unsigned &SrcReg2, int &Mask, int &Value) const override
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:384
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:164
unsigned getReg() const
getReg - Returns the register number.
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
unsigned Reg
unsigned getSubReg() const
bool isInlineAsm() const
bool hasLoadStoreOnCond() const
constexpr bool isInt< 8 >(int64_t x)
Definition: MathExtras.h:302
uint64_t getSize() const
Return the size in bytes of the memory reference.
bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, unsigned ExtraPredCycles, BranchProbability Probability) const override
constexpr bool isInt< 16 >(int64_t x)
Definition: MathExtras.h:305
STATISTIC(NumFunctions, "Total number of functions")
unsigned const TargetRegisterInfo * TRI
A debug info location.
Definition: DebugLoc.h:33
void setIsDead(bool Val=true)
bool areMemAccessesTriviallyDisjoint(const MachineInstr &MIa, const MachineInstr &MIb, AliasAnalysis *AA=nullptr) const override
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
unsigned isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override
const unsigned CCMASK_ICMP
Definition: SystemZ.h:46
bool PredicateInstruction(MachineInstr &MI, ArrayRef< MachineOperand > Pred) const override
bool FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, unsigned Reg, MachineRegisterInfo *MRI) const override
return AArch64::GPR64RegClass contains(Reg)
static uint64_t allOnes(unsigned int Count)
This class represents the liveness of a register, stack slot, etc.
Definition: LiveInterval.h:156
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const override
bool isAtomic() const
Returns true if this operation has an atomic ordering requirement of unordered or higher...
void eraseFromParent()
This method unlinks &#39;this&#39; from the containing function and deletes it.
A description of a memory reference used in the backend.
unsigned getNumOperands() const
Retuns the total number of operands.
Definition: MachineInstr.h:413
VNInfo::Allocator & getVNInfoAllocator()
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:41
void eraseFromParent()
Unlink &#39;this&#39; from the containing basic block and delete it.
SlotIndex getInstructionIndex(const MachineInstr &MI) const
Returns the base index for the given instruction.
Definition: SlotIndexes.h:411
unsigned getLoadAndTest(unsigned Opcode) const
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:410
const char * getSymbolName() const
unsigned getLoadAndTrap(unsigned Opcode) const
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
Definition: MachineInstr.h:407
static LogicOp interpretAndImmediate(unsigned Opcode)
SlotIndex getRegSlot(bool EC=false) const
Returns the register use/def slot in the current instruction for a normal or early-clobber def...
Definition: SlotIndexes.h:254
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
bool isPredicable(const MachineInstr &MI) const override
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:32
const MachineOperand * Target
iterator getLastNonDebugInstr()
Returns an iterator to the last non-debug instruction in the basic block, or end().
const unsigned CCMASK_ANY
Definition: SystemZ.h:30
int getTwoOperandOpcode(uint16_t Opcode)
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
unsigned getUndefRegState(bool B)
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
bool isStackSlotCopy(const MachineInstr &MI, int &DestFrameIndex, int &SrcFrameIndex) const override
VNInfo * createDeadDef(SlotIndex Def, VNInfo::Allocator &VNIAlloc)
createDeadDef - Make sure the range has a value defined at Def.
const TargetRegisterClass * constrainRegClass(unsigned Reg, const TargetRegisterClass *RC, unsigned MinNumRegs=0)
constrainRegClass - Constrain the register class of the specified virtual register to be a common sub...
BasicBlockListType::iterator iterator
unsigned getKillRegState(bool B)
void ChangeToImmediate(int64_t ImmVal)
ChangeToImmediate - Replace this operand with a new immediate operand of the specified value...
Flag
These should be considered private to the implementation of the MCInstrDesc class.
Definition: MCInstrDesc.h:117
const Value * getValue() const
Return the base address of the memory access.
MachineInstr * commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned CommuteOpIdx1, unsigned CommuteOpIdx2) const override
Commutes the operands in the given instruction by changing the operands order and/or changing the ins...
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
virtual MachineInstr * commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned OpIdx1, unsigned OpIdx2) const
This method commutes the operands of the given machine instruction MI.
static void transferDeadCC(MachineInstr *OldMI, MachineInstr *NewMI)
Control flow instructions. These all have token chains.
Definition: ISDOpcodes.h:657
constexpr bool isUInt< 8 >(uint64_t x)
Definition: MathExtras.h:342
unsigned const MachineRegisterInfo * MRI
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:45
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
static unsigned getAccessSize(unsigned int Flags)
bool isCompare(QueryType Type=IgnoreBundle) const
Return true if this instruction is a comparison.
Definition: MachineInstr.h:695
bool liveAt(SlotIndex index) const
Definition: LiveInterval.h:388
bool registerDefIsDead(unsigned Reg, const TargetRegisterInfo *TRI=nullptr) const
Returns true if the register is dead in this machine instruction.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
MachineInstrBuilder & UseMI
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:148
unsigned getOpcodeForOffset(unsigned Opcode, int64_t Offset) const
const MCAsmInfo * getMCAsmInfo() const
Return target specific asm information.
bool hasOneMemOperand() const
Return true if this instruction has exactly one MachineMemOperand.
Definition: MachineInstr.h:550
const MachineInstrBuilder & addRegMask(const uint32_t *Mask) const
bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, BranchProbability Probability) const override
const PseudoSourceValue * getPseudoValue() const
void setImm(int64_t immVal)
const MachineInstrBuilder & addFrameIndex(int Idx) const
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg, int FrameIdx, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
size_t size() const
Definition: SmallVector.h:52
static bool isImmLH(uint64_t Val)
Definition: SystemZ.h:165
T findFirstSet(T Val, ZeroBehavior ZB=ZB_Max)
Get the index of the first set bit starting from the least significant bit.
Definition: MathExtras.h:202
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
unsigned getNumExplicitOperands() const
Returns the number of non-implicit operands.
void setIsKill(bool Val=true)
static const MachineInstrBuilder & addFrameReference(const MachineInstrBuilder &MIB, int FI, int Offset=0, bool mem=true)
addFrameReference - This function is used to add a reference to the base of an abstract object on the...
static bool isHighReg(unsigned int Reg)
void replaceKillInstruction(unsigned Reg, MachineInstr &OldMI, MachineInstr &NewMI)
replaceKillInstruction - Update register kill info by replacing a kill instruction with a new one...
void setDesc(const MCInstrDesc &tid)
Replace the instruction descriptor (thus opcode) of the current instruction with a new one...
constexpr bool isInt< 32 >(int64_t x)
Definition: MathExtras.h:308
unsigned getMaxCallFrameSize() const
Return the maximum size of a call frame that must be allocated for an outgoing function call...
mmo_iterator memoperands_begin() const
Access to memory operands of the instruction.
Definition: MachineInstr.h:535
MachineInstr * CloneMachineInstr(const MachineInstr *Orig)
Create a new MachineInstr which is a copy of Orig, identical in all ways except the instruction has n...
MachineOperand class - Representation of each machine instruction operand.
MachineInstrBuilder MachineInstrBuilder & DefMI
static bool isStringOfOnes(uint64_t Mask, unsigned &LSB, unsigned &Length)
const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const
const unsigned CCMASK_CMP_NE
Definition: SystemZ.h:37
MachineInstr * convertToThreeAddress(MachineFunction::iterator &MFI, MachineInstr &MI, LiveVariables *LV) const override
int64_t getImm() const
bool isLayoutSuccessor(const MachineBasicBlock *MBB) const
Return true if the specified MBB will be emitted immediately after this block, such that if this bloc...
const uint32_t * getRegMask() const
getRegMask - Returns a bit mask of registers preserved by this RegMask operand.
Special value supplied for machine level alias analysis.
bool isValid() const
isValid - returns true if this iterator is not yet at the end.
static int isSimpleMove(const MachineInstr &MI, int &FrameIndex, unsigned Flag)
bool canInsertSelect(const MachineBasicBlock &, ArrayRef< MachineOperand > Cond, unsigned, unsigned, int &, int &, int &) const override
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:255
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
void getLoadStoreOpcodes(const TargetRegisterClass *RC, unsigned &LoadOpcode, unsigned &StoreOpcode) const
Representation of each machine instruction.
Definition: MachineInstr.h:63
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
unsigned getInstSizeInBytes(const MachineInstr &MI) const override
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
LLVM_NODISCARD bool empty() const
Definition: SmallVector.h:55
unsigned getFusedCompare(unsigned Opcode, SystemZII::FusedCompareType Type, const MachineInstr *MI=nullptr) const
void setReg(unsigned Reg)
Change the register this operand corresponds to.
static MachineOperand CreateImm(int64_t Val)
#define I(x, y, z)
Definition: MD5.cpp:58
bool isFI() const
isFI - Tests if this is a MO_FrameIndex operand.
static bool isSimpleBD12Move(const MachineInstr *MI, unsigned Flag)
uint32_t Size
Definition: Profile.cpp:46
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
unsigned getPhys(unsigned virtReg) const
returns the physical register mapped to the specified virtual register
Definition: VirtRegMap.h:100
bool hasOneNonDBGUse(unsigned RegNo) const
hasOneNonDBGUse - Return true if there is exactly one non-Debug instruction using the specified regis...
SlotIndexes * getSlotIndexes() const
bool isReg() const
isReg - Tests if this is a MO_Register operand.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
SystemZII::Branch getBranchInfo(const MachineInstr &MI) const
int64_t getOffset() const
For normal values, this is a byte offset added to the base address.
LLVM Value Representation.
Definition: Value.h:72
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E&#39;s largest value.
Definition: BitmaskEnum.h:80
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
static bool isImmLL(uint64_t Val)
Definition: SystemZ.h:160
bool isRxSBGMask(uint64_t Mask, unsigned BitSize, unsigned &Start, unsigned &End) const
IRTranslator LLVM IR MI
bool isMBB() const
isMBB - Tests if this is a MO_MachineBasicBlock operand.
void RemoveOperand(unsigned OpNo)
Erase an operand from an instruction, leaving it with one fewer operand than it started with...
unsigned getRegSizeInBits(const TargetRegisterClass &RC) const
Return the size in bits of a register from class RC.
const unsigned IPM_CC
Definition: SystemZ.h:111
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned char TargetFlags=0) const
MachineInstr * foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, int FrameIndex, LiveIntervals *LIS=nullptr, VirtRegMap *VRM=nullptr) const override
bool hasLoadStoreOnCond2() const
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:415
unsigned isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override
SlotIndex - An opaque wrapper around machine indexes.
Definition: SlotIndexes.h:83
bool isCommutable(QueryType Type=IgnoreBundle) const
Return true if this may be a 2- or 3-address instruction (of the form "X = op Y, Z, ..."), which produces the same result if Y and Z are exchanged.
Definition: MachineInstr.h:860
LiveRange & getRegUnit(unsigned Unit)
Return the live range for register unit Unit.
unsigned createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
bool empty() const
empty - Check if the array is empty.
Definition: ArrayRef.h:143
unsigned getSize() const
Return the number of bytes in the encoding of this instruction, or zero if the encoding size cannot b...
Definition: MCInstrDesc.h:586
void tieOperands(unsigned DefIdx, unsigned UseIdx)
Add a tie between the register operands at DefIdx and UseIdx.