LLVM  6.0.0svn
MachineRegisterInfo.h
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1 //===- llvm/CodeGen/MachineRegisterInfo.h -----------------------*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines the MachineRegisterInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_CODEGEN_MACHINEREGISTERINFO_H
15 #define LLVM_CODEGEN_MACHINEREGISTERINFO_H
16 
17 #include "llvm/ADT/ArrayRef.h"
18 #include "llvm/ADT/BitVector.h"
19 #include "llvm/ADT/DenseMap.h"
20 #include "llvm/ADT/IndexedMap.h"
21 #include "llvm/ADT/PointerUnion.h"
22 #include "llvm/ADT/SmallVector.h"
30 #include "llvm/MC/LaneBitmask.h"
33 #include <cassert>
34 #include <cstddef>
35 #include <cstdint>
36 #include <iterator>
37 #include <memory>
38 #include <utility>
39 #include <vector>
40 
41 namespace llvm {
42 
43 class PSetIterator;
44 
45 /// Convenient type to represent either a register class or a register bank.
46 using RegClassOrRegBank =
48 
49 /// MachineRegisterInfo - Keep track of information for virtual and physical
50 /// registers, including vreg register classes, use/def chains for registers,
51 /// etc.
53 public:
54  class Delegate {
55  virtual void anchor();
56 
57  public:
58  virtual ~Delegate() = default;
59 
60  virtual void MRI_NoteNewVirtualRegister(unsigned Reg) = 0;
61  };
62 
63 private:
64  MachineFunction *MF;
65  Delegate *TheDelegate = nullptr;
66 
67  /// True if subregister liveness is tracked.
68  const bool TracksSubRegLiveness;
69 
70  /// VRegInfo - Information we keep for each virtual register.
71  ///
72  /// Each element in this list contains the register class of the vreg and the
73  /// start of the use/def list for the register.
76  VRegInfo;
77 
78  /// The flag is true upon \p UpdatedCSRs initialization
79  /// and false otherwise.
80  bool IsUpdatedCSRsInitialized;
81 
82  /// Contains the updated callee saved register list.
83  /// As opposed to the static list defined in register info,
84  /// all registers that were disabled are removed from the list.
85  SmallVector<MCPhysReg, 16> UpdatedCSRs;
86 
87  /// RegAllocHints - This vector records register allocation hints for virtual
88  /// registers. For each virtual register, it keeps a register and hint type
89  /// pair making up the allocation hint. Hint type is target specific except
90  /// for the value 0 which means the second value of the pair is the preferred
91  /// register for allocation. For example, if the hint is <0, 1024>, it means
92  /// the allocator should prefer the physical register allocated to the virtual
93  /// register of the hint.
95 
96  /// PhysRegUseDefLists - This is an array of the head of the use/def list for
97  /// physical registers.
98  std::unique_ptr<MachineOperand *[]> PhysRegUseDefLists;
99 
100  /// getRegUseDefListHead - Return the head pointer for the register use/def
101  /// list for the specified virtual or physical register.
102  MachineOperand *&getRegUseDefListHead(unsigned RegNo) {
104  return VRegInfo[RegNo].second;
105  return PhysRegUseDefLists[RegNo];
106  }
107 
108  MachineOperand *getRegUseDefListHead(unsigned RegNo) const {
110  return VRegInfo[RegNo].second;
111  return PhysRegUseDefLists[RegNo];
112  }
113 
114  /// Get the next element in the use-def chain.
115  static MachineOperand *getNextOperandForReg(const MachineOperand *MO) {
116  assert(MO && MO->isReg() && "This is not a register operand!");
117  return MO->Contents.Reg.Next;
118  }
119 
120  /// UsedPhysRegMask - Additional used physregs including aliases.
121  /// This bit vector represents all the registers clobbered by function calls.
122  BitVector UsedPhysRegMask;
123 
124  /// ReservedRegs - This is a bit vector of reserved registers. The target
125  /// may change its mind about which registers should be reserved. This
126  /// vector is the frozen set of reserved registers when register allocation
127  /// started.
128  BitVector ReservedRegs;
129 
131  /// Map generic virtual registers to their actual size.
132  mutable std::unique_ptr<VRegToTypeMap> VRegToType;
133 
134  /// Keep track of the physical registers that are live in to the function.
135  /// Live in values are typically arguments in registers. LiveIn values are
136  /// allowed to have virtual registers associated with them, stored in the
137  /// second element.
138  std::vector<std::pair<unsigned, unsigned>> LiveIns;
139 
140 public:
141  explicit MachineRegisterInfo(MachineFunction *MF);
142  MachineRegisterInfo(const MachineRegisterInfo &) = delete;
144 
146  return MF->getSubtarget().getRegisterInfo();
147  }
148 
149  void resetDelegate(Delegate *delegate) {
150  // Ensure another delegate does not take over unless the current
151  // delegate first unattaches itself. If we ever need to multicast
152  // notifications, we will need to change to using a list.
153  assert(TheDelegate == delegate &&
154  "Only the current delegate can perform reset!");
155  TheDelegate = nullptr;
156  }
157 
158  void setDelegate(Delegate *delegate) {
159  assert(delegate && !TheDelegate &&
160  "Attempted to set delegate to null, or to change it without "
161  "first resetting it!");
162 
163  TheDelegate = delegate;
164  }
165 
166  //===--------------------------------------------------------------------===//
167  // Function State
168  //===--------------------------------------------------------------------===//
169 
170  // isSSA - Returns true when the machine function is in SSA form. Early
171  // passes require the machine function to be in SSA form where every virtual
172  // register has a single defining instruction.
173  //
174  // The TwoAddressInstructionPass and PHIElimination passes take the machine
175  // function out of SSA form when they introduce multiple defs per virtual
176  // register.
177  bool isSSA() const {
178  return MF->getProperties().hasProperty(
180  }
181 
182  // leaveSSA - Indicates that the machine function is no longer in SSA form.
183  void leaveSSA() {
185  }
186 
187  /// tracksLiveness - Returns true when tracking register liveness accurately.
188  /// (see MachineFUnctionProperties::Property description for details)
189  bool tracksLiveness() const {
190  return MF->getProperties().hasProperty(
192  }
193 
194  /// invalidateLiveness - Indicates that register liveness is no longer being
195  /// tracked accurately.
196  ///
197  /// This should be called by late passes that invalidate the liveness
198  /// information.
200  MF->getProperties().reset(
202  }
203 
204  /// Returns true if liveness for register class @p RC should be tracked at
205  /// the subregister level.
208  }
209  bool shouldTrackSubRegLiveness(unsigned VReg) const {
210  assert(TargetRegisterInfo::isVirtualRegister(VReg) && "Must pass a VReg");
211  return shouldTrackSubRegLiveness(*getRegClass(VReg));
212  }
213  bool subRegLivenessEnabled() const {
214  return TracksSubRegLiveness;
215  }
216 
217  //===--------------------------------------------------------------------===//
218  // Register Info
219  //===--------------------------------------------------------------------===//
220 
221  /// Returns true if the updated CSR list was initialized and false otherwise.
222  bool isUpdatedCSRsInitialized() const { return IsUpdatedCSRsInitialized; }
223 
224  /// Disables the register from the list of CSRs.
225  /// I.e. the register will not appear as part of the CSR mask.
226  /// \see UpdatedCalleeSavedRegs.
227  void disableCalleeSavedRegister(unsigned Reg);
228 
229  /// Returns list of callee saved registers.
230  /// The function returns the updated CSR list (after taking into account
231  /// registers that are disabled from the CSR list).
232  const MCPhysReg *getCalleeSavedRegs() const;
233 
234  /// Sets the updated Callee Saved Registers list.
235  /// Notice that it will override ant previously disabled/saved CSRs.
237 
238  // Strictly for use by MachineInstr.cpp.
240 
241  // Strictly for use by MachineInstr.cpp.
243 
244  // Strictly for use by MachineInstr.cpp.
245  void moveOperands(MachineOperand *Dst, MachineOperand *Src, unsigned NumOps);
246 
247  /// Verify the sanity of the use list for Reg.
248  void verifyUseList(unsigned Reg) const;
249 
250  /// Verify the use list of all registers.
251  void verifyUseLists() const;
252 
253  /// reg_begin/reg_end - Provide iteration support to walk over all definitions
254  /// and uses of a register within the MachineFunction that corresponds to this
255  /// MachineRegisterInfo object.
256  template<bool Uses, bool Defs, bool SkipDebug,
257  bool ByOperand, bool ByInstr, bool ByBundle>
259  template<bool Uses, bool Defs, bool SkipDebug,
260  bool ByOperand, bool ByInstr, bool ByBundle>
262 
263  // Make it a friend so it can access getNextOperandForReg().
264  template<bool, bool, bool, bool, bool, bool>
265  friend class defusechain_iterator;
266  template<bool, bool, bool, bool, bool, bool>
268 
269  /// reg_iterator/reg_begin/reg_end - Walk all defs and uses of the specified
270  /// register.
271  using reg_iterator =
273  reg_iterator reg_begin(unsigned RegNo) const {
274  return reg_iterator(getRegUseDefListHead(RegNo));
275  }
276  static reg_iterator reg_end() { return reg_iterator(nullptr); }
277 
278  inline iterator_range<reg_iterator> reg_operands(unsigned Reg) const {
279  return make_range(reg_begin(Reg), reg_end());
280  }
281 
282  /// reg_instr_iterator/reg_instr_begin/reg_instr_end - Walk all defs and uses
283  /// of the specified register, stepping by MachineInstr.
284  using reg_instr_iterator =
286  reg_instr_iterator reg_instr_begin(unsigned RegNo) const {
287  return reg_instr_iterator(getRegUseDefListHead(RegNo));
288  }
290  return reg_instr_iterator(nullptr);
291  }
292 
294  reg_instructions(unsigned Reg) const {
295  return make_range(reg_instr_begin(Reg), reg_instr_end());
296  }
297 
298  /// reg_bundle_iterator/reg_bundle_begin/reg_bundle_end - Walk all defs and uses
299  /// of the specified register, stepping by bundle.
300  using reg_bundle_iterator =
302  reg_bundle_iterator reg_bundle_begin(unsigned RegNo) const {
303  return reg_bundle_iterator(getRegUseDefListHead(RegNo));
304  }
306  return reg_bundle_iterator(nullptr);
307  }
308 
311  }
312 
313  /// reg_empty - Return true if there are no instructions using or defining the
314  /// specified register (it may be live-in).
315  bool reg_empty(unsigned RegNo) const { return reg_begin(RegNo) == reg_end(); }
316 
317  /// reg_nodbg_iterator/reg_nodbg_begin/reg_nodbg_end - Walk all defs and uses
318  /// of the specified register, skipping those marked as Debug.
319  using reg_nodbg_iterator =
321  reg_nodbg_iterator reg_nodbg_begin(unsigned RegNo) const {
322  return reg_nodbg_iterator(getRegUseDefListHead(RegNo));
323  }
325  return reg_nodbg_iterator(nullptr);
326  }
327 
329  reg_nodbg_operands(unsigned Reg) const {
330  return make_range(reg_nodbg_begin(Reg), reg_nodbg_end());
331  }
332 
333  /// reg_instr_nodbg_iterator/reg_instr_nodbg_begin/reg_instr_nodbg_end - Walk
334  /// all defs and uses of the specified register, stepping by MachineInstr,
335  /// skipping those marked as Debug.
339  return reg_instr_nodbg_iterator(getRegUseDefListHead(RegNo));
340  }
342  return reg_instr_nodbg_iterator(nullptr);
343  }
344 
346  reg_nodbg_instructions(unsigned Reg) const {
348  }
349 
350  /// reg_bundle_nodbg_iterator/reg_bundle_nodbg_begin/reg_bundle_nodbg_end - Walk
351  /// all defs and uses of the specified register, stepping by bundle,
352  /// skipping those marked as Debug.
356  return reg_bundle_nodbg_iterator(getRegUseDefListHead(RegNo));
357  }
359  return reg_bundle_nodbg_iterator(nullptr);
360  }
361 
363  reg_nodbg_bundles(unsigned Reg) const {
365  }
366 
367  /// reg_nodbg_empty - Return true if the only instructions using or defining
368  /// Reg are Debug instructions.
369  bool reg_nodbg_empty(unsigned RegNo) const {
370  return reg_nodbg_begin(RegNo) == reg_nodbg_end();
371  }
372 
373  /// def_iterator/def_begin/def_end - Walk all defs of the specified register.
374  using def_iterator =
376  def_iterator def_begin(unsigned RegNo) const {
377  return def_iterator(getRegUseDefListHead(RegNo));
378  }
379  static def_iterator def_end() { return def_iterator(nullptr); }
380 
381  inline iterator_range<def_iterator> def_operands(unsigned Reg) const {
382  return make_range(def_begin(Reg), def_end());
383  }
384 
385  /// def_instr_iterator/def_instr_begin/def_instr_end - Walk all defs of the
386  /// specified register, stepping by MachineInst.
387  using def_instr_iterator =
389  def_instr_iterator def_instr_begin(unsigned RegNo) const {
390  return def_instr_iterator(getRegUseDefListHead(RegNo));
391  }
393  return def_instr_iterator(nullptr);
394  }
395 
397  def_instructions(unsigned Reg) const {
398  return make_range(def_instr_begin(Reg), def_instr_end());
399  }
400 
401  /// def_bundle_iterator/def_bundle_begin/def_bundle_end - Walk all defs of the
402  /// specified register, stepping by bundle.
403  using def_bundle_iterator =
405  def_bundle_iterator def_bundle_begin(unsigned RegNo) const {
406  return def_bundle_iterator(getRegUseDefListHead(RegNo));
407  }
409  return def_bundle_iterator(nullptr);
410  }
411 
414  }
415 
416  /// def_empty - Return true if there are no instructions defining the
417  /// specified register (it may be live-in).
418  bool def_empty(unsigned RegNo) const { return def_begin(RegNo) == def_end(); }
419 
420  /// Return true if there is exactly one operand defining the specified
421  /// register.
422  bool hasOneDef(unsigned RegNo) const {
423  def_iterator DI = def_begin(RegNo);
424  if (DI == def_end())
425  return false;
426  return ++DI == def_end();
427  }
428 
429  /// use_iterator/use_begin/use_end - Walk all uses of the specified register.
430  using use_iterator =
432  use_iterator use_begin(unsigned RegNo) const {
433  return use_iterator(getRegUseDefListHead(RegNo));
434  }
435  static use_iterator use_end() { return use_iterator(nullptr); }
436 
437  inline iterator_range<use_iterator> use_operands(unsigned Reg) const {
438  return make_range(use_begin(Reg), use_end());
439  }
440 
441  /// use_instr_iterator/use_instr_begin/use_instr_end - Walk all uses of the
442  /// specified register, stepping by MachineInstr.
443  using use_instr_iterator =
445  use_instr_iterator use_instr_begin(unsigned RegNo) const {
446  return use_instr_iterator(getRegUseDefListHead(RegNo));
447  }
449  return use_instr_iterator(nullptr);
450  }
451 
453  use_instructions(unsigned Reg) const {
454  return make_range(use_instr_begin(Reg), use_instr_end());
455  }
456 
457  /// use_bundle_iterator/use_bundle_begin/use_bundle_end - Walk all uses of the
458  /// specified register, stepping by bundle.
459  using use_bundle_iterator =
461  use_bundle_iterator use_bundle_begin(unsigned RegNo) const {
462  return use_bundle_iterator(getRegUseDefListHead(RegNo));
463  }
465  return use_bundle_iterator(nullptr);
466  }
467 
470  }
471 
472  /// use_empty - Return true if there are no instructions using the specified
473  /// register.
474  bool use_empty(unsigned RegNo) const { return use_begin(RegNo) == use_end(); }
475 
476  /// hasOneUse - Return true if there is exactly one instruction using the
477  /// specified register.
478  bool hasOneUse(unsigned RegNo) const {
479  use_iterator UI = use_begin(RegNo);
480  if (UI == use_end())
481  return false;
482  return ++UI == use_end();
483  }
484 
485  /// use_nodbg_iterator/use_nodbg_begin/use_nodbg_end - Walk all uses of the
486  /// specified register, skipping those marked as Debug.
487  using use_nodbg_iterator =
489  use_nodbg_iterator use_nodbg_begin(unsigned RegNo) const {
490  return use_nodbg_iterator(getRegUseDefListHead(RegNo));
491  }
493  return use_nodbg_iterator(nullptr);
494  }
495 
497  use_nodbg_operands(unsigned Reg) const {
498  return make_range(use_nodbg_begin(Reg), use_nodbg_end());
499  }
500 
501  /// use_instr_nodbg_iterator/use_instr_nodbg_begin/use_instr_nodbg_end - Walk
502  /// all uses of the specified register, stepping by MachineInstr, skipping
503  /// those marked as Debug.
507  return use_instr_nodbg_iterator(getRegUseDefListHead(RegNo));
508  }
510  return use_instr_nodbg_iterator(nullptr);
511  }
512 
514  use_nodbg_instructions(unsigned Reg) const {
516  }
517 
518  /// use_bundle_nodbg_iterator/use_bundle_nodbg_begin/use_bundle_nodbg_end - Walk
519  /// all uses of the specified register, stepping by bundle, skipping
520  /// those marked as Debug.
524  return use_bundle_nodbg_iterator(getRegUseDefListHead(RegNo));
525  }
527  return use_bundle_nodbg_iterator(nullptr);
528  }
529 
531  use_nodbg_bundles(unsigned Reg) const {
533  }
534 
535  /// use_nodbg_empty - Return true if there are no non-Debug instructions
536  /// using the specified register.
537  bool use_nodbg_empty(unsigned RegNo) const {
538  return use_nodbg_begin(RegNo) == use_nodbg_end();
539  }
540 
541  /// hasOneNonDBGUse - Return true if there is exactly one non-Debug
542  /// instruction using the specified register.
543  bool hasOneNonDBGUse(unsigned RegNo) const;
544 
545  /// replaceRegWith - Replace all instances of FromReg with ToReg in the
546  /// machine function. This is like llvm-level X->replaceAllUsesWith(Y),
547  /// except that it also changes any definitions of the register as well.
548  ///
549  /// Note that it is usually necessary to first constrain ToReg's register
550  /// class to match the FromReg constraints using:
551  ///
552  /// constrainRegClass(ToReg, getRegClass(FromReg))
553  ///
554  /// That function will return NULL if the virtual registers have incompatible
555  /// constraints.
556  ///
557  /// Note that if ToReg is a physical register the function will replace and
558  /// apply sub registers to ToReg in order to obtain a final/proper physical
559  /// register.
560  void replaceRegWith(unsigned FromReg, unsigned ToReg);
561 
562  /// getVRegDef - Return the machine instr that defines the specified virtual
563  /// register or null if none is found. This assumes that the code is in SSA
564  /// form, so there should only be one definition.
565  MachineInstr *getVRegDef(unsigned Reg) const;
566 
567  /// getUniqueVRegDef - Return the unique machine instr that defines the
568  /// specified virtual register or null if none is found. If there are
569  /// multiple definitions or no definition, return null.
570  MachineInstr *getUniqueVRegDef(unsigned Reg) const;
571 
572  /// clearKillFlags - Iterate over all the uses of the given register and
573  /// clear the kill flag from the MachineOperand. This function is used by
574  /// optimization passes which extend register lifetimes and need only
575  /// preserve conservative kill flag information.
576  void clearKillFlags(unsigned Reg) const;
577 
578  void dumpUses(unsigned RegNo) const;
579 
580  /// Returns true if PhysReg is unallocatable and constant throughout the
581  /// function. Writing to a constant register has no effect.
582  bool isConstantPhysReg(unsigned PhysReg) const;
583 
584  /// Get an iterator over the pressure sets affected by the given physical or
585  /// virtual register. If RegUnit is physical, it must be a register unit (from
586  /// MCRegUnitIterator).
587  PSetIterator getPressureSets(unsigned RegUnit) const;
588 
589  //===--------------------------------------------------------------------===//
590  // Virtual Register Info
591  //===--------------------------------------------------------------------===//
592 
593  /// Return the register class of the specified virtual register.
594  /// This shouldn't be used directly unless \p Reg has a register class.
595  /// \see getRegClassOrNull when this might happen.
596  const TargetRegisterClass *getRegClass(unsigned Reg) const {
597  assert(VRegInfo[Reg].first.is<const TargetRegisterClass *>() &&
598  "Register class not set, wrong accessor");
599  return VRegInfo[Reg].first.get<const TargetRegisterClass *>();
600  }
601 
602  /// Return the register class of \p Reg, or null if Reg has not been assigned
603  /// a register class yet.
604  ///
605  /// \note A null register class can only happen when these two
606  /// conditions are met:
607  /// 1. Generic virtual registers are created.
608  /// 2. The machine function has not completely been through the
609  /// instruction selection process.
610  /// None of this condition is possible without GlobalISel for now.
611  /// In other words, if GlobalISel is not used or if the query happens after
612  /// the select pass, using getRegClass is safe.
613  const TargetRegisterClass *getRegClassOrNull(unsigned Reg) const {
614  const RegClassOrRegBank &Val = VRegInfo[Reg].first;
615  return Val.dyn_cast<const TargetRegisterClass *>();
616  }
617 
618  /// Return the register bank of \p Reg, or null if Reg has not been assigned
619  /// a register bank or has been assigned a register class.
620  /// \note It is possible to get the register bank from the register class via
621  /// RegisterBankInfo::getRegBankFromRegClass.
622  const RegisterBank *getRegBankOrNull(unsigned Reg) const {
623  const RegClassOrRegBank &Val = VRegInfo[Reg].first;
624  return Val.dyn_cast<const RegisterBank *>();
625  }
626 
627  /// Return the register bank or register class of \p Reg.
628  /// \note Before the register bank gets assigned (i.e., before the
629  /// RegBankSelect pass) \p Reg may not have either.
630  const RegClassOrRegBank &getRegClassOrRegBank(unsigned Reg) const {
631  return VRegInfo[Reg].first;
632  }
633 
634  /// setRegClass - Set the register class of the specified virtual register.
635  void setRegClass(unsigned Reg, const TargetRegisterClass *RC);
636 
637  /// Set the register bank to \p RegBank for \p Reg.
638  void setRegBank(unsigned Reg, const RegisterBank &RegBank);
639 
640  void setRegClassOrRegBank(unsigned Reg,
641  const RegClassOrRegBank &RCOrRB){
642  VRegInfo[Reg].first = RCOrRB;
643  }
644 
645  /// constrainRegClass - Constrain the register class of the specified virtual
646  /// register to be a common subclass of RC and the current register class,
647  /// but only if the new class has at least MinNumRegs registers. Return the
648  /// new register class, or NULL if no such class exists.
649  /// This should only be used when the constraint is known to be trivial, like
650  /// GR32 -> GR32_NOSP. Beware of increasing register pressure.
651  const TargetRegisterClass *constrainRegClass(unsigned Reg,
652  const TargetRegisterClass *RC,
653  unsigned MinNumRegs = 0);
654 
655  /// recomputeRegClass - Try to find a legal super-class of Reg's register
656  /// class that still satisfies the constraints from the instructions using
657  /// Reg. Returns true if Reg was upgraded.
658  ///
659  /// This method can be used after constraints have been removed from a
660  /// virtual register, for example after removing instructions or splitting
661  /// the live range.
662  bool recomputeRegClass(unsigned Reg);
663 
664  /// createVirtualRegister - Create and return a new virtual register in the
665  /// function with the specified register class.
666  unsigned createVirtualRegister(const TargetRegisterClass *RegClass);
667 
668  /// Accessor for VRegToType. This accessor should only be used
669  /// by global-isel related work.
671  if (!VRegToType)
672  VRegToType.reset(new VRegToTypeMap);
673  return *VRegToType.get();
674  }
675 
676  /// Get the low-level type of \p VReg or LLT{} if VReg is not a generic
677  /// (target independent) virtual register.
678  LLT getType(unsigned VReg) const;
679 
680  /// Set the low-level type of \p VReg to \p Ty.
681  void setType(unsigned VReg, LLT Ty);
682 
683  /// Create and return a new generic virtual register with low-level
684  /// type \p Ty.
685  unsigned createGenericVirtualRegister(LLT Ty);
686 
687  /// Remove all types associated to virtual registers (after instruction
688  /// selection and constraining of all generic virtual registers).
689  void clearVirtRegTypes();
690 
691  /// Creates a new virtual register that has no register class, register bank
692  /// or size assigned yet. This is only allowed to be used
693  /// temporarily while constructing machine instructions. Most operations are
694  /// undefined on an incomplete register until one of setRegClass(),
695  /// setRegBank() or setSize() has been called on it.
697 
698  /// getNumVirtRegs - Return the number of virtual registers created.
699  unsigned getNumVirtRegs() const { return VRegInfo.size(); }
700 
701  /// clearVirtRegs - Remove all virtual registers (after physreg assignment).
702  void clearVirtRegs();
703 
704  /// setRegAllocationHint - Specify a register allocation hint for the
705  /// specified virtual register.
706  void setRegAllocationHint(unsigned VReg, unsigned Type, unsigned PrefReg) {
708  RegAllocHints[VReg].first = Type;
709  RegAllocHints[VReg].second = PrefReg;
710  }
711 
712  /// Specify the preferred register allocation hint for the specified virtual
713  /// register.
714  void setSimpleHint(unsigned VReg, unsigned PrefReg) {
715  setRegAllocationHint(VReg, /*Type=*/0, PrefReg);
716  }
717 
718  /// getRegAllocationHint - Return the register allocation hint for the
719  /// specified virtual register.
720  std::pair<unsigned, unsigned>
721  getRegAllocationHint(unsigned VReg) const {
723  return RegAllocHints[VReg];
724  }
725 
726  /// getSimpleHint - Return the preferred register allocation hint, or 0 if a
727  /// standard simple hint (Type == 0) is not set.
728  unsigned getSimpleHint(unsigned VReg) const {
730  std::pair<unsigned, unsigned> Hint = getRegAllocationHint(VReg);
731  return Hint.first ? 0 : Hint.second;
732  }
733 
734  /// markUsesInDebugValueAsUndef - Mark every DBG_VALUE referencing the
735  /// specified register as undefined which causes the DBG_VALUE to be
736  /// deleted during LiveDebugVariables analysis.
737  void markUsesInDebugValueAsUndef(unsigned Reg) const;
738 
739  /// Return true if the specified register is modified in this function.
740  /// This checks that no defining machine operands exist for the register or
741  /// any of its aliases. Definitions found on functions marked noreturn are
742  /// ignored, to consider them pass 'true' for optional parameter
743  /// SkipNoReturnDef. The register is also considered modified when it is set
744  /// in the UsedPhysRegMask.
745  bool isPhysRegModified(unsigned PhysReg, bool SkipNoReturnDef = false) const;
746 
747  /// Return true if the specified register is modified or read in this
748  /// function. This checks that no machine operands exist for the register or
749  /// any of its aliases. The register is also considered used when it is set
750  /// in the UsedPhysRegMask.
751  bool isPhysRegUsed(unsigned PhysReg) const;
752 
753  /// addPhysRegsUsedFromRegMask - Mark any registers not in RegMask as used.
754  /// This corresponds to the bit mask attached to register mask operands.
755  void addPhysRegsUsedFromRegMask(const uint32_t *RegMask) {
756  UsedPhysRegMask.setBitsNotInMask(RegMask);
757  }
758 
759  const BitVector &getUsedPhysRegsMask() const { return UsedPhysRegMask; }
760 
761  //===--------------------------------------------------------------------===//
762  // Reserved Register Info
763  //===--------------------------------------------------------------------===//
764  //
765  // The set of reserved registers must be invariant during register
766  // allocation. For example, the target cannot suddenly decide it needs a
767  // frame pointer when the register allocator has already used the frame
768  // pointer register for something else.
769  //
770  // These methods can be used by target hooks like hasFP() to avoid changing
771  // the reserved register set during register allocation.
772 
773  /// freezeReservedRegs - Called by the register allocator to freeze the set
774  /// of reserved registers before allocation begins.
775  void freezeReservedRegs(const MachineFunction&);
776 
777  /// reservedRegsFrozen - Returns true after freezeReservedRegs() was called
778  /// to ensure the set of reserved registers stays constant.
779  bool reservedRegsFrozen() const {
780  return !ReservedRegs.empty();
781  }
782 
783  /// canReserveReg - Returns true if PhysReg can be used as a reserved
784  /// register. Any register can be reserved before freezeReservedRegs() is
785  /// called.
786  bool canReserveReg(unsigned PhysReg) const {
787  return !reservedRegsFrozen() || ReservedRegs.test(PhysReg);
788  }
789 
790  /// getReservedRegs - Returns a reference to the frozen set of reserved
791  /// registers. This method should always be preferred to calling
792  /// TRI::getReservedRegs() when possible.
793  const BitVector &getReservedRegs() const {
795  "Reserved registers haven't been frozen yet. "
796  "Use TRI::getReservedRegs().");
797  return ReservedRegs;
798  }
799 
800  /// isReserved - Returns true when PhysReg is a reserved register.
801  ///
802  /// Reserved registers may belong to an allocatable register class, but the
803  /// target has explicitly requested that they are not used.
804  bool isReserved(unsigned PhysReg) const {
805  return getReservedRegs().test(PhysReg);
806  }
807 
808  /// Returns true when the given register unit is considered reserved.
809  ///
810  /// Register units are considered reserved when for at least one of their
811  /// root registers, the root register and all super registers are reserved.
812  /// This currently iterates the register hierarchy and may be slower than
813  /// expected.
814  bool isReservedRegUnit(unsigned Unit) const;
815 
816  /// isAllocatable - Returns true when PhysReg belongs to an allocatable
817  /// register class and it hasn't been reserved.
818  ///
819  /// Allocatable registers may show up in the allocation order of some virtual
820  /// register, so a register allocator needs to track its liveness and
821  /// availability.
822  bool isAllocatable(unsigned PhysReg) const {
823  return getTargetRegisterInfo()->isInAllocatableClass(PhysReg) &&
824  !isReserved(PhysReg);
825  }
826 
827  //===--------------------------------------------------------------------===//
828  // LiveIn Management
829  //===--------------------------------------------------------------------===//
830 
831  /// addLiveIn - Add the specified register as a live-in. Note that it
832  /// is an error to add the same register to the same set more than once.
833  void addLiveIn(unsigned Reg, unsigned vreg = 0) {
834  LiveIns.push_back(std::make_pair(Reg, vreg));
835  }
836 
837  // Iteration support for the live-ins set. It's kept in sorted order
838  // by register number.
839  using livein_iterator =
840  std::vector<std::pair<unsigned,unsigned>>::const_iterator;
841  livein_iterator livein_begin() const { return LiveIns.begin(); }
842  livein_iterator livein_end() const { return LiveIns.end(); }
843  bool livein_empty() const { return LiveIns.empty(); }
844 
846  return LiveIns;
847  }
848 
849  bool isLiveIn(unsigned Reg) const;
850 
851  /// getLiveInPhysReg - If VReg is a live-in virtual register, return the
852  /// corresponding live-in physical register.
853  unsigned getLiveInPhysReg(unsigned VReg) const;
854 
855  /// getLiveInVirtReg - If PReg is a live-in physical register, return the
856  /// corresponding live-in physical register.
857  unsigned getLiveInVirtReg(unsigned PReg) const;
858 
859  /// EmitLiveInCopies - Emit copies to initialize livein virtual registers
860  /// into the given entry block.
861  void EmitLiveInCopies(MachineBasicBlock *EntryMBB,
862  const TargetRegisterInfo &TRI,
863  const TargetInstrInfo &TII);
864 
865  /// Returns a mask covering all bits that can appear in lane masks of
866  /// subregisters of the virtual register @p Reg.
867  LaneBitmask getMaxLaneMaskForVReg(unsigned Reg) const;
868 
869  /// defusechain_iterator - This class provides iterator support for machine
870  /// operands in the function that use or define a specific register. If
871  /// ReturnUses is true it returns uses of registers, if ReturnDefs is true it
872  /// returns defs. If neither are true then you are silly and it always
873  /// returns end(). If SkipDebug is true it skips uses marked Debug
874  /// when incrementing.
875  template<bool ReturnUses, bool ReturnDefs, bool SkipDebug,
876  bool ByOperand, bool ByInstr, bool ByBundle>
878  : public std::iterator<std::forward_iterator_tag, MachineInstr, ptrdiff_t> {
879  friend class MachineRegisterInfo;
880 
881  MachineOperand *Op = nullptr;
882 
883  explicit defusechain_iterator(MachineOperand *op) : Op(op) {
884  // If the first node isn't one we're interested in, advance to one that
885  // we are interested in.
886  if (op) {
887  if ((!ReturnUses && op->isUse()) ||
888  (!ReturnDefs && op->isDef()) ||
889  (SkipDebug && op->isDebug()))
890  advance();
891  }
892  }
893 
894  void advance() {
895  assert(Op && "Cannot increment end iterator!");
896  Op = getNextOperandForReg(Op);
897 
898  // All defs come before the uses, so stop def_iterator early.
899  if (!ReturnUses) {
900  if (Op) {
901  if (Op->isUse())
902  Op = nullptr;
903  else
904  assert(!Op->isDebug() && "Can't have debug defs");
905  }
906  } else {
907  // If this is an operand we don't care about, skip it.
908  while (Op && ((!ReturnDefs && Op->isDef()) ||
909  (SkipDebug && Op->isDebug())))
910  Op = getNextOperandForReg(Op);
911  }
912  }
913 
914  public:
915  using reference = std::iterator<std::forward_iterator_tag,
917  using pointer = std::iterator<std::forward_iterator_tag,
919 
920  defusechain_iterator() = default;
921 
922  bool operator==(const defusechain_iterator &x) const {
923  return Op == x.Op;
924  }
925  bool operator!=(const defusechain_iterator &x) const {
926  return !operator==(x);
927  }
928 
929  /// atEnd - return true if this iterator is equal to reg_end() on the value.
930  bool atEnd() const { return Op == nullptr; }
931 
932  // Iterator traversal: forward iteration only
933  defusechain_iterator &operator++() { // Preincrement
934  assert(Op && "Cannot increment end iterator!");
935  if (ByOperand)
936  advance();
937  else if (ByInstr) {
938  MachineInstr *P = Op->getParent();
939  do {
940  advance();
941  } while (Op && Op->getParent() == P);
942  } else if (ByBundle) {
945  do {
946  advance();
947  } while (Op && getBundleStart(Op->getParent()->getIterator()) == P);
948  }
949 
950  return *this;
951  }
952  defusechain_iterator operator++(int) { // Postincrement
953  defusechain_iterator tmp = *this; ++*this; return tmp;
954  }
955 
956  /// getOperandNo - Return the operand # of this MachineOperand in its
957  /// MachineInstr.
958  unsigned getOperandNo() const {
959  assert(Op && "Cannot dereference end iterator!");
960  return Op - &Op->getParent()->getOperand(0);
961  }
962 
963  // Retrieve a reference to the current operand.
965  assert(Op && "Cannot dereference end iterator!");
966  return *Op;
967  }
968 
970  assert(Op && "Cannot dereference end iterator!");
971  return Op;
972  }
973  };
974 
975  /// defusechain_iterator - This class provides iterator support for machine
976  /// operands in the function that use or define a specific register. If
977  /// ReturnUses is true it returns uses of registers, if ReturnDefs is true it
978  /// returns defs. If neither are true then you are silly and it always
979  /// returns end(). If SkipDebug is true it skips uses marked Debug
980  /// when incrementing.
981  template<bool ReturnUses, bool ReturnDefs, bool SkipDebug,
982  bool ByOperand, bool ByInstr, bool ByBundle>
984  : public std::iterator<std::forward_iterator_tag, MachineInstr, ptrdiff_t> {
985  friend class MachineRegisterInfo;
986 
987  MachineOperand *Op = nullptr;
988 
989  explicit defusechain_instr_iterator(MachineOperand *op) : Op(op) {
990  // If the first node isn't one we're interested in, advance to one that
991  // we are interested in.
992  if (op) {
993  if ((!ReturnUses && op->isUse()) ||
994  (!ReturnDefs && op->isDef()) ||
995  (SkipDebug && op->isDebug()))
996  advance();
997  }
998  }
999 
1000  void advance() {
1001  assert(Op && "Cannot increment end iterator!");
1002  Op = getNextOperandForReg(Op);
1003 
1004  // All defs come before the uses, so stop def_iterator early.
1005  if (!ReturnUses) {
1006  if (Op) {
1007  if (Op->isUse())
1008  Op = nullptr;
1009  else
1010  assert(!Op->isDebug() && "Can't have debug defs");
1011  }
1012  } else {
1013  // If this is an operand we don't care about, skip it.
1014  while (Op && ((!ReturnDefs && Op->isDef()) ||
1015  (SkipDebug && Op->isDebug())))
1016  Op = getNextOperandForReg(Op);
1017  }
1018  }
1019 
1020  public:
1021  using reference = std::iterator<std::forward_iterator_tag,
1023  using pointer = std::iterator<std::forward_iterator_tag,
1025 
1026  defusechain_instr_iterator() = default;
1027 
1029  return Op == x.Op;
1030  }
1032  return !operator==(x);
1033  }
1034 
1035  /// atEnd - return true if this iterator is equal to reg_end() on the value.
1036  bool atEnd() const { return Op == nullptr; }
1037 
1038  // Iterator traversal: forward iteration only
1040  assert(Op && "Cannot increment end iterator!");
1041  if (ByOperand)
1042  advance();
1043  else if (ByInstr) {
1044  MachineInstr *P = Op->getParent();
1045  do {
1046  advance();
1047  } while (Op && Op->getParent() == P);
1048  } else if (ByBundle) {
1051  do {
1052  advance();
1053  } while (Op && getBundleStart(Op->getParent()->getIterator()) == P);
1054  }
1055 
1056  return *this;
1057  }
1058  defusechain_instr_iterator operator++(int) { // Postincrement
1059  defusechain_instr_iterator tmp = *this; ++*this; return tmp;
1060  }
1061 
1062  // Retrieve a reference to the current operand.
1064  assert(Op && "Cannot dereference end iterator!");
1065  if (ByBundle)
1066  return *getBundleStart(Op->getParent()->getIterator());
1067  return *Op->getParent();
1068  }
1069 
1070  MachineInstr *operator->() const { return &operator*(); }
1071  };
1072 };
1073 
1074 /// Iterate over the pressure sets affected by the given physical or virtual
1075 /// register. If Reg is physical, it must be a register unit (from
1076 /// MCRegUnitIterator).
1078  const int *PSet = nullptr;
1079  unsigned Weight = 0;
1080 
1081 public:
1082  PSetIterator() = default;
1083 
1084  PSetIterator(unsigned RegUnit, const MachineRegisterInfo *MRI) {
1085  const TargetRegisterInfo *TRI = MRI->getTargetRegisterInfo();
1087  const TargetRegisterClass *RC = MRI->getRegClass(RegUnit);
1088  PSet = TRI->getRegClassPressureSets(RC);
1089  Weight = TRI->getRegClassWeight(RC).RegWeight;
1090  }
1091  else {
1092  PSet = TRI->getRegUnitPressureSets(RegUnit);
1093  Weight = TRI->getRegUnitWeight(RegUnit);
1094  }
1095  if (*PSet == -1)
1096  PSet = nullptr;
1097  }
1098 
1099  bool isValid() const { return PSet; }
1100 
1101  unsigned getWeight() const { return Weight; }
1102 
1103  unsigned operator*() const { return *PSet; }
1104 
1105  void operator++() {
1106  assert(isValid() && "Invalid PSetIterator.");
1107  ++PSet;
1108  if (*PSet == -1)
1109  PSet = nullptr;
1110  }
1111 };
1112 
1114 getPressureSets(unsigned RegUnit) const {
1115  return PSetIterator(RegUnit, this);
1116 }
1117 
1118 } // end namespace llvm
1119 
1120 #endif // LLVM_CODEGEN_MACHINEREGISTERINFO_H
bool operator!=(const defusechain_iterator &x) const
bool reg_nodbg_empty(unsigned RegNo) const
reg_nodbg_empty - Return true if the only instructions using or defining Reg are Debug instructions...
defusechain_instr_iterator< true, false, false, false, true, false > use_instr_iterator
use_instr_iterator/use_instr_begin/use_instr_end - Walk all uses of the specified register...
defusechain_instr_iterator< true, true, false, false, true, false > reg_instr_iterator
reg_instr_iterator/reg_instr_begin/reg_instr_end - Walk all defs and uses of the specified register...
iterator_range< reg_instr_nodbg_iterator > reg_nodbg_instructions(unsigned Reg) const
A common definition of LaneBitmask for use in TableGen and CodeGen.
void EmitLiveInCopies(MachineBasicBlock *EntryMBB, const TargetRegisterInfo &TRI, const TargetInstrInfo &TII)
EmitLiveInCopies - Emit copies to initialize livein virtual registers into the given entry block...
defusechain_iterator< false, true, false, true, false, false > def_iterator
def_iterator/def_begin/def_end - Walk all defs of the specified register.
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
iterator_range< def_bundle_iterator > def_bundles(unsigned Reg) const
use_bundle_iterator use_bundle_begin(unsigned RegNo) const
bool use_nodbg_empty(unsigned RegNo) const
use_nodbg_empty - Return true if there are no non-Debug instructions using the specified register...
const TargetRegisterClass * getRegClass(unsigned Reg) const
Return the register class of the specified virtual register.
livein_iterator livein_begin() const
StorageT::size_type size() const
Definition: IndexedMap.h:78
void removeRegOperandFromUseList(MachineOperand *MO)
Remove MO from its use-def list.
bool isAllocatable(unsigned PhysReg) const
isAllocatable - Returns true when PhysReg belongs to an allocatable register class and it hasn&#39;t been...
void clearVirtRegTypes()
Remove all types associated to virtual registers (after instruction selection and constraining of all...
LaneBitmask getMaxLaneMaskForVReg(unsigned Reg) const
Returns a mask covering all bits that can appear in lane masks of subregisters of the virtual registe...
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
MachineFunctionProperties & reset(Property P)
bool empty() const
empty - Tests whether there are no bits in this bitvector.
Definition: BitVector.h:167
PointerUnion< const TargetRegisterClass *, const RegisterBank * > RegClassOrRegBank
Convenient type to represent either a register class or a register bank.
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
unsigned createVirtualRegister(const TargetRegisterClass *RegClass)
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
void addLiveIn(unsigned Reg, unsigned vreg=0)
addLiveIn - Add the specified register as a live-in.
const MachineFunctionProperties & getProperties() const
Get the function properties.
bool isPhysRegModified(unsigned PhysReg, bool SkipNoReturnDef=false) const
Return true if the specified register is modified in this function.
This provides a very simple, boring adaptor for a begin and end iterator into a range type...
iterator_range< use_nodbg_iterator > use_nodbg_operands(unsigned Reg) const
iterator_range< use_bundle_iterator > use_bundles(unsigned Reg) const
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
iterator_range< reg_nodbg_iterator > reg_nodbg_operands(unsigned Reg) const
bool test(unsigned Idx) const
Definition: BitVector.h:502
iterator_range< reg_iterator > reg_operands(unsigned Reg) const
void setBitsNotInMask(const uint32_t *Mask, unsigned MaskWords=~0u)
setBitsNotInMask - Add a bit to this vector for every &#39;0&#39; bit in Mask.
Definition: BitVector.h:771
virtual const int * getRegClassPressureSets(const TargetRegisterClass *RC) const =0
Get the dimensions of register pressure impacted by this register class.
bool hasOneDef(unsigned RegNo) const
Return true if there is exactly one operand defining the specified register.
reg_nodbg_iterator reg_nodbg_begin(unsigned RegNo) const
defusechain_instr_iterator< false, true, false, false, false, true > def_bundle_iterator
def_bundle_iterator/def_bundle_begin/def_bundle_end - Walk all defs of the specified register...
void setRegBank(unsigned Reg, const RegisterBank &RegBank)
Set the register bank to RegBank for Reg.
bool reservedRegsFrozen() const
reservedRegsFrozen - Returns true after freezeReservedRegs() was called to ensure the set of reserved...
#define op(i)
unsigned createGenericVirtualRegister(LLT Ty)
Create and return a new generic virtual register with low-level type Ty.
use_nodbg_iterator use_nodbg_begin(unsigned RegNo) const
void verifyUseLists() const
Verify the use list of all registers.
static use_nodbg_iterator use_nodbg_end()
defusechain_instr_iterator< true, false, true, false, false, true > use_bundle_nodbg_iterator
use_bundle_nodbg_iterator/use_bundle_nodbg_begin/use_bundle_nodbg_end - Walk all uses of the specifie...
void clearVirtRegs()
clearVirtRegs - Remove all virtual registers (after physreg assignment).
bool operator==(const defusechain_iterator &x) const
virtual unsigned getRegUnitWeight(unsigned RegUnit) const =0
Get the weight in units of pressure for this register unit.
std::iterator< std::forward_iterator_tag, MachineInstr, ptrdiff_t >::reference reference
static use_iterator use_end()
iterator_range< reg_bundle_nodbg_iterator > reg_nodbg_bundles(unsigned Reg) const
reg_instr_nodbg_iterator reg_instr_nodbg_begin(unsigned RegNo) const
const HexagonInstrInfo * TII
defusechain_instr_iterator< true, true, true, false, true, false > reg_instr_nodbg_iterator
reg_instr_nodbg_iterator/reg_instr_nodbg_begin/reg_instr_nodbg_end - Walk all defs and uses of the sp...
void freezeReservedRegs(const MachineFunction &)
freezeReservedRegs - Called by the register allocator to freeze the set of reserved registers before ...
Reg
All possible values of the reg field in the ModR/M byte.
defusechain_instr_iterator< true, true, false, false, false, true > reg_bundle_iterator
reg_bundle_iterator/reg_bundle_begin/reg_bundle_end - Walk all defs and uses of the specified registe...
def_iterator def_begin(unsigned RegNo) const
defusechain_iterator< true, true, true, true, false, false > reg_nodbg_iterator
reg_nodbg_iterator/reg_nodbg_begin/reg_nodbg_end - Walk all defs and uses of the specified register...
APInt operator*(APInt a, uint64_t RHS)
Definition: APInt.h:2070
unsigned getLiveInPhysReg(unsigned VReg) const
getLiveInPhysReg - If VReg is a live-in virtual register, return the corresponding live-in physical r...
static reg_instr_iterator reg_instr_end()
MachineInstr * getVRegDef(unsigned Reg) const
getVRegDef - Return the machine instr that defines the specified virtual register or null if none is ...
defusechain_iterator - This class provides iterator support for machine operands in the function that...
MachineBasicBlock::instr_iterator getBundleStart(MachineBasicBlock::instr_iterator I)
Returns an iterator to the first instruction in the bundle containing I.
defusechain_iterator< true, false, true, true, false, false > use_nodbg_iterator
use_nodbg_iterator/use_nodbg_begin/use_nodbg_end - Walk all uses of the specified register...
void clearKillFlags(unsigned Reg) const
clearKillFlags - Iterate over all the uses of the given register and clear the kill flag from the Mac...
const RegClassOrRegBank & getRegClassOrRegBank(unsigned Reg) const
Return the register bank or register class of Reg.
use_bundle_nodbg_iterator use_bundle_nodbg_begin(unsigned RegNo) const
iterator_range< def_iterator > def_operands(unsigned Reg) const
livein_iterator livein_end() const
static def_instr_iterator def_instr_end()
PSetIterator(unsigned RegUnit, const MachineRegisterInfo *MRI)
bool canReserveReg(unsigned PhysReg) const
canReserveReg - Returns true if PhysReg can be used as a reserved register.
defusechain_instr_iterator< false, true, false, false, true, false > def_instr_iterator
def_instr_iterator/def_instr_begin/def_instr_end - Walk all defs of the specified register...
std::iterator< std::forward_iterator_tag, MachineInstr, ptrdiff_t >::pointer pointer
void disableCalleeSavedRegister(unsigned Reg)
Disables the register from the list of CSRs.
const TargetRegisterClass * constrainRegClass(unsigned Reg, const TargetRegisterClass *RC, unsigned MinNumRegs=0)
constrainRegClass - Constrain the register class of the specified virtual register to be a common sub...
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
TargetInstrInfo - Interface to description of machine instruction set.
#define P(N)
reg_bundle_iterator reg_bundle_begin(unsigned RegNo) const
const TargetRegisterInfo * getTargetRegisterInfo() const
unsigned const MachineRegisterInfo * MRI
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:46
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
void setType(unsigned VReg, LLT Ty)
Set the low-level type of VReg to Ty.
unsigned createIncompleteVirtualRegister()
Creates a new virtual register that has no register class, register bank or size assigned yet...
use_instr_iterator use_instr_begin(unsigned RegNo) const
VRegToTypeMap & getVRegToType() const
Accessor for VRegToType.
defusechain_iterator< true, false, false, true, false, false > use_iterator
use_iterator/use_begin/use_end - Walk all uses of the specified register.
bool def_empty(unsigned RegNo) const
def_empty - Return true if there are no instructions defining the specified register (it may be live-...
bool atEnd() const
atEnd - return true if this iterator is equal to reg_end() on the value.
const RegisterBank * getRegBankOrNull(unsigned Reg) const
Return the register bank of Reg, or null if Reg has not been assigned a register bank or has been ass...
self_iterator getIterator()
Definition: ilist_node.h:82
void setCalleeSavedRegs(ArrayRef< MCPhysReg > CSRs)
Sets the updated Callee Saved Registers list.
unsigned getNumVirtRegs() const
getNumVirtRegs - Return the number of virtual registers created.
T dyn_cast() const
Returns the current pointer if it is of the specified pointer type, otherwises returns null...
Definition: PointerUnion.h:142
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
std::iterator< std::forward_iterator_tag, MachineInstr, ptrdiff_t >::reference reference
bool isConstantPhysReg(unsigned PhysReg) const
Returns true if PhysReg is unallocatable and constant throughout the function.
unsigned first
const bool HasDisjunctSubRegs
Whether the class supports two (or more) disjunct subregister indices.
iterator_range< T > make_range(T x, T y)
Convenience function for iterating over sub-ranges.
static use_bundle_nodbg_iterator use_bundle_nodbg_end()
defusechain_iterator< true, true, false, true, false, false > reg_iterator
reg_iterator/reg_begin/reg_end - Walk all defs and uses of the specified register.
iterator_range< use_iterator > use_operands(unsigned Reg) const
MachineOperand class - Representation of each machine instruction operand.
virtual const RegClassWeight & getRegClassWeight(const TargetRegisterClass *RC) const =0
Get the weight in units of pressure for this register class.
void setRegAllocationHint(unsigned VReg, unsigned Type, unsigned PrefReg)
setRegAllocationHint - Specify a register allocation hint for the specified virtual register...
bool isInAllocatableClass(unsigned RegNo) const
Return true if the register is in the allocation of any register class.
bool atEnd() const
atEnd - return true if this iterator is equal to reg_end() on the value.
static reg_bundle_iterator reg_bundle_end()
bool isReservedRegUnit(unsigned Unit) const
Returns true when the given register unit is considered reserved.
reg_iterator reg_begin(unsigned RegNo) const
void invalidateLiveness()
invalidateLiveness - Indicates that register liveness is no longer being tracked accurately.
This class implements the register bank concept.
Definition: RegisterBank.h:29
const BitVector & getUsedPhysRegsMask() const
bool recomputeRegClass(unsigned Reg)
recomputeRegClass - Try to find a legal super-class of Reg&#39;s register class that still satisfies the ...
void resetDelegate(Delegate *delegate)
MachineInstr * getUniqueVRegDef(unsigned Reg) const
getUniqueVRegDef - Return the unique machine instr that defines the specified virtual register or nul...
static reg_bundle_nodbg_iterator reg_bundle_nodbg_end()
bool isPhysRegUsed(unsigned PhysReg) const
Return true if the specified register is modified or read in this function.
A range adaptor for a pair of iterators.
iterator_range< reg_bundle_iterator > reg_bundles(unsigned Reg) const
ArrayRef< std::pair< unsigned, unsigned > > liveins() const
iterator_range< use_bundle_nodbg_iterator > use_nodbg_bundles(unsigned Reg) const
void verifyUseList(unsigned Reg) const
Verify the sanity of the use list for Reg.
bool use_empty(unsigned RegNo) const
use_empty - Return true if there are no instructions using the specified register.
void dumpUses(unsigned RegNo) const
def_instr_iterator def_instr_begin(unsigned RegNo) const
defusechain_instr_iterator< true, true, true, false, false, true > reg_bundle_nodbg_iterator
reg_bundle_nodbg_iterator/reg_bundle_nodbg_begin/reg_bundle_nodbg_end - Walk all defs and uses of the...
void replaceRegWith(unsigned FromReg, unsigned ToReg)
replaceRegWith - Replace all instances of FromReg with ToReg in the machine function.
const BitVector & getReservedRegs() const
getReservedRegs - Returns a reference to the frozen set of reserved registers.
bool operator!=(const defusechain_instr_iterator &x) const
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
bool isLiveIn(unsigned Reg) const
Representation of each machine instruction.
Definition: MachineInstr.h:59
std::vector< std::pair< unsigned, unsigned > >::const_iterator livein_iterator
unsigned getOperandNo() const
getOperandNo - Return the operand # of this MachineOperand in its MachineInstr.
static reg_instr_nodbg_iterator reg_instr_nodbg_end()
static use_bundle_iterator use_bundle_end()
std::pair< unsigned, unsigned > getRegAllocationHint(unsigned VReg) const
getRegAllocationHint - Return the register allocation hint for the specified virtual register...
bool isUpdatedCSRsInitialized() const
Returns true if the updated CSR list was initialized and false otherwise.
bool hasOneUse(unsigned RegNo) const
hasOneUse - Return true if there is exactly one instruction using the specified register.
use_iterator use_begin(unsigned RegNo) const
Iterate over the pressure sets affected by the given physical or virtual register.
unsigned operator*() const
PSetIterator getPressureSets(unsigned RegUnit) const
Get an iterator over the pressure sets affected by the given physical or virtual register.
bool shouldTrackSubRegLiveness(unsigned VReg) const
LLT getType(unsigned VReg) const
Get the low-level type of VReg or LLT{} if VReg is not a generic (target independent) virtual registe...
virtual const int * getRegUnitPressureSets(unsigned RegUnit) const =0
Get the dimensions of register pressure impacted by this register unit.
void addPhysRegsUsedFromRegMask(const uint32_t *RegMask)
addPhysRegsUsedFromRegMask - Mark any registers not in RegMask as used.
defusechain_instr_iterator< true, false, true, false, true, false > use_instr_nodbg_iterator
use_instr_nodbg_iterator/use_instr_nodbg_begin/use_instr_nodbg_end - Walk all uses of the specified r...
bool tracksLiveness() const
tracksLiveness - Returns true when tracking register liveness accurately.
void markUsesInDebugValueAsUndef(unsigned Reg) const
markUsesInDebugValueAsUndef - Mark every DBG_VALUE referencing the specified register as undefined wh...
bool hasOneNonDBGUse(unsigned RegNo) const
hasOneNonDBGUse - Return true if there is exactly one non-Debug instruction using the specified regis...
void setSimpleHint(unsigned VReg, unsigned PrefReg)
Specify the preferred register allocation hint for the specified virtual register.
bool shouldTrackSubRegLiveness(const TargetRegisterClass &RC) const
Returns true if liveness for register class RC should be tracked at the subregister level...
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Instructions::iterator instr_iterator
static reg_nodbg_iterator reg_nodbg_end()
iterator_range< reg_instr_iterator > reg_instructions(unsigned Reg) const
iterator_range< use_instr_iterator > use_instructions(unsigned Reg) const
static use_instr_nodbg_iterator use_instr_nodbg_end()
const TargetRegisterClass * getRegClassOrNull(unsigned Reg) const
Return the register class of Reg, or null if Reg has not been assigned a register class yet...
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
bool hasProperty(Property P) const
static def_iterator def_end()
use_instr_nodbg_iterator use_instr_nodbg_begin(unsigned RegNo) const
bool operator==(const defusechain_instr_iterator &x) const
MachineRegisterInfo(MachineFunction *MF)
reg_bundle_nodbg_iterator reg_bundle_nodbg_begin(unsigned RegNo) const
void moveOperands(MachineOperand *Dst, MachineOperand *Src, unsigned NumOps)
Move NumOps operands from Src to Dst, updating use-def lists as needed.
static use_instr_iterator use_instr_end()
iterator_range< def_instr_iterator > def_instructions(unsigned Reg) const
const MCPhysReg * getCalleeSavedRegs() const
Returns list of callee saved registers.
bool reg_empty(unsigned RegNo) const
reg_empty - Return true if there are no instructions using or defining the specified register (it may...
def_bundle_iterator def_bundle_begin(unsigned RegNo) const
void setRegClass(unsigned Reg, const TargetRegisterClass *RC)
setRegClass - Set the register class of the specified virtual register.
void setDelegate(Delegate *delegate)
virtual void MRI_NoteNewVirtualRegister(unsigned Reg)=0
bool operator==(uint64_t V1, const APInt &V2)
Definition: APInt.h:1946
unsigned getWeight() const
defusechain_instr_iterator< true, false, false, false, false, true > use_bundle_iterator
use_bundle_iterator/use_bundle_begin/use_bundle_end - Walk all uses of the specified register...
unsigned getSimpleHint(unsigned VReg) const
getSimpleHint - Return the preferred register allocation hint, or 0 if a standard simple hint (Type =...
void setRegClassOrRegBank(unsigned Reg, const RegClassOrRegBank &RCOrRB)
static reg_iterator reg_end()
unsigned getLiveInVirtReg(unsigned PReg) const
getLiveInVirtReg - If PReg is a live-in physical register, return the corresponding live-in physical ...
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:295
iterator_range< use_instr_nodbg_iterator > use_nodbg_instructions(unsigned Reg) const
reg_begin/reg_end - Provide iteration support to walk over all definitions and uses of a register wit...
MachineRegisterInfo & operator=(const MachineRegisterInfo &)=delete
struct llvm::MachineOperand::@142::@144 Reg
reg_instr_iterator reg_instr_begin(unsigned RegNo) const
static def_bundle_iterator def_bundle_end()
std::iterator< std::forward_iterator_tag, MachineInstr, ptrdiff_t >::pointer pointer
bool isReserved(unsigned PhysReg) const
isReserved - Returns true when PhysReg is a reserved register.
A discriminated union of two pointer types, with the discriminator in the low bit of the pointer...
Definition: PointerUnion.h:87
void addRegOperandToUseList(MachineOperand *MO)
Add MO to the linked list of operands for its register.