LLVM  8.0.0svn
MachineRegisterInfo.h
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1 //===- llvm/CodeGen/MachineRegisterInfo.h -----------------------*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines the MachineRegisterInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_CODEGEN_MACHINEREGISTERINFO_H
15 #define LLVM_CODEGEN_MACHINEREGISTERINFO_H
16 
17 #include "llvm/ADT/ArrayRef.h"
18 #include "llvm/ADT/BitVector.h"
19 #include "llvm/ADT/DenseMap.h"
20 #include "llvm/ADT/IndexedMap.h"
21 #include "llvm/ADT/PointerUnion.h"
22 #include "llvm/ADT/SmallVector.h"
23 #include "llvm/ADT/StringSet.h"
33 #include "llvm/MC/LaneBitmask.h"
34 #include <cassert>
35 #include <cstddef>
36 #include <cstdint>
37 #include <iterator>
38 #include <memory>
39 #include <utility>
40 #include <vector>
41 
42 namespace llvm {
43 
44 class PSetIterator;
45 
46 /// Convenient type to represent either a register class or a register bank.
47 using RegClassOrRegBank =
49 
50 /// MachineRegisterInfo - Keep track of information for virtual and physical
51 /// registers, including vreg register classes, use/def chains for registers,
52 /// etc.
54 public:
55  class Delegate {
56  virtual void anchor();
57 
58  public:
59  virtual ~Delegate() = default;
60 
61  virtual void MRI_NoteNewVirtualRegister(unsigned Reg) = 0;
62  };
63 
64 private:
65  MachineFunction *MF;
66  Delegate *TheDelegate = nullptr;
67 
68  /// True if subregister liveness is tracked.
69  const bool TracksSubRegLiveness;
70 
71  /// VRegInfo - Information we keep for each virtual register.
72  ///
73  /// Each element in this list contains the register class of the vreg and the
74  /// start of the use/def list for the register.
77  VRegInfo;
78 
79  /// Map for recovering vreg name from vreg number.
80  /// This map is used by the MIR Printer.
82 
83  /// StringSet that is used to unique vreg names.
84  StringSet<> VRegNames;
85 
86  /// The flag is true upon \p UpdatedCSRs initialization
87  /// and false otherwise.
88  bool IsUpdatedCSRsInitialized;
89 
90  /// Contains the updated callee saved register list.
91  /// As opposed to the static list defined in register info,
92  /// all registers that were disabled are removed from the list.
93  SmallVector<MCPhysReg, 16> UpdatedCSRs;
94 
95  /// RegAllocHints - This vector records register allocation hints for
96  /// virtual registers. For each virtual register, it keeps a pair of hint
97  /// type and hints vector making up the allocation hints. Only the first
98  /// hint may be target specific, and in that case this is reflected by the
99  /// first member of the pair being non-zero. If the hinted register is
100  /// virtual, it means the allocator should prefer the physical register
101  /// allocated to it if any.
103  VirtReg2IndexFunctor> RegAllocHints;
104 
105  /// PhysRegUseDefLists - This is an array of the head of the use/def list for
106  /// physical registers.
107  std::unique_ptr<MachineOperand *[]> PhysRegUseDefLists;
108 
109  /// getRegUseDefListHead - Return the head pointer for the register use/def
110  /// list for the specified virtual or physical register.
111  MachineOperand *&getRegUseDefListHead(unsigned RegNo) {
113  return VRegInfo[RegNo].second;
114  return PhysRegUseDefLists[RegNo];
115  }
116 
117  MachineOperand *getRegUseDefListHead(unsigned RegNo) const {
119  return VRegInfo[RegNo].second;
120  return PhysRegUseDefLists[RegNo];
121  }
122 
123  /// Get the next element in the use-def chain.
124  static MachineOperand *getNextOperandForReg(const MachineOperand *MO) {
125  assert(MO && MO->isReg() && "This is not a register operand!");
126  return MO->Contents.Reg.Next;
127  }
128 
129  /// UsedPhysRegMask - Additional used physregs including aliases.
130  /// This bit vector represents all the registers clobbered by function calls.
131  BitVector UsedPhysRegMask;
132 
133  /// ReservedRegs - This is a bit vector of reserved registers. The target
134  /// may change its mind about which registers should be reserved. This
135  /// vector is the frozen set of reserved registers when register allocation
136  /// started.
137  BitVector ReservedRegs;
138 
140  /// Map generic virtual registers to their low-level type.
141  VRegToTypeMap VRegToType;
142 
143  /// Keep track of the physical registers that are live in to the function.
144  /// Live in values are typically arguments in registers. LiveIn values are
145  /// allowed to have virtual registers associated with them, stored in the
146  /// second element.
147  std::vector<std::pair<unsigned, unsigned>> LiveIns;
148 
149 public:
150  explicit MachineRegisterInfo(MachineFunction *MF);
151  MachineRegisterInfo(const MachineRegisterInfo &) = delete;
153 
155  return MF->getSubtarget().getRegisterInfo();
156  }
157 
158  void resetDelegate(Delegate *delegate) {
159  // Ensure another delegate does not take over unless the current
160  // delegate first unattaches itself. If we ever need to multicast
161  // notifications, we will need to change to using a list.
162  assert(TheDelegate == delegate &&
163  "Only the current delegate can perform reset!");
164  TheDelegate = nullptr;
165  }
166 
167  void setDelegate(Delegate *delegate) {
168  assert(delegate && !TheDelegate &&
169  "Attempted to set delegate to null, or to change it without "
170  "first resetting it!");
171 
172  TheDelegate = delegate;
173  }
174 
175  //===--------------------------------------------------------------------===//
176  // Function State
177  //===--------------------------------------------------------------------===//
178 
179  // isSSA - Returns true when the machine function is in SSA form. Early
180  // passes require the machine function to be in SSA form where every virtual
181  // register has a single defining instruction.
182  //
183  // The TwoAddressInstructionPass and PHIElimination passes take the machine
184  // function out of SSA form when they introduce multiple defs per virtual
185  // register.
186  bool isSSA() const {
187  return MF->getProperties().hasProperty(
189  }
190 
191  // leaveSSA - Indicates that the machine function is no longer in SSA form.
192  void leaveSSA() {
194  }
195 
196  /// tracksLiveness - Returns true when tracking register liveness accurately.
197  /// (see MachineFUnctionProperties::Property description for details)
198  bool tracksLiveness() const {
199  return MF->getProperties().hasProperty(
201  }
202 
203  /// invalidateLiveness - Indicates that register liveness is no longer being
204  /// tracked accurately.
205  ///
206  /// This should be called by late passes that invalidate the liveness
207  /// information.
209  MF->getProperties().reset(
211  }
212 
213  /// Returns true if liveness for register class @p RC should be tracked at
214  /// the subregister level.
217  }
218  bool shouldTrackSubRegLiveness(unsigned VReg) const {
219  assert(TargetRegisterInfo::isVirtualRegister(VReg) && "Must pass a VReg");
220  return shouldTrackSubRegLiveness(*getRegClass(VReg));
221  }
222  bool subRegLivenessEnabled() const {
223  return TracksSubRegLiveness;
224  }
225 
226  //===--------------------------------------------------------------------===//
227  // Register Info
228  //===--------------------------------------------------------------------===//
229 
230  /// Returns true if the updated CSR list was initialized and false otherwise.
231  bool isUpdatedCSRsInitialized() const { return IsUpdatedCSRsInitialized; }
232 
233  /// Disables the register from the list of CSRs.
234  /// I.e. the register will not appear as part of the CSR mask.
235  /// \see UpdatedCalleeSavedRegs.
236  void disableCalleeSavedRegister(unsigned Reg);
237 
238  /// Returns list of callee saved registers.
239  /// The function returns the updated CSR list (after taking into account
240  /// registers that are disabled from the CSR list).
241  const MCPhysReg *getCalleeSavedRegs() const;
242 
243  /// Sets the updated Callee Saved Registers list.
244  /// Notice that it will override ant previously disabled/saved CSRs.
246 
247  // Strictly for use by MachineInstr.cpp.
249 
250  // Strictly for use by MachineInstr.cpp.
252 
253  // Strictly for use by MachineInstr.cpp.
254  void moveOperands(MachineOperand *Dst, MachineOperand *Src, unsigned NumOps);
255 
256  /// Verify the sanity of the use list for Reg.
257  void verifyUseList(unsigned Reg) const;
258 
259  /// Verify the use list of all registers.
260  void verifyUseLists() const;
261 
262  /// reg_begin/reg_end - Provide iteration support to walk over all definitions
263  /// and uses of a register within the MachineFunction that corresponds to this
264  /// MachineRegisterInfo object.
265  template<bool Uses, bool Defs, bool SkipDebug,
266  bool ByOperand, bool ByInstr, bool ByBundle>
268  template<bool Uses, bool Defs, bool SkipDebug,
269  bool ByOperand, bool ByInstr, bool ByBundle>
271 
272  // Make it a friend so it can access getNextOperandForReg().
273  template<bool, bool, bool, bool, bool, bool>
274  friend class defusechain_iterator;
275  template<bool, bool, bool, bool, bool, bool>
277 
278  /// reg_iterator/reg_begin/reg_end - Walk all defs and uses of the specified
279  /// register.
280  using reg_iterator =
282  reg_iterator reg_begin(unsigned RegNo) const {
283  return reg_iterator(getRegUseDefListHead(RegNo));
284  }
285  static reg_iterator reg_end() { return reg_iterator(nullptr); }
286 
287  inline iterator_range<reg_iterator> reg_operands(unsigned Reg) const {
288  return make_range(reg_begin(Reg), reg_end());
289  }
290 
291  /// reg_instr_iterator/reg_instr_begin/reg_instr_end - Walk all defs and uses
292  /// of the specified register, stepping by MachineInstr.
293  using reg_instr_iterator =
295  reg_instr_iterator reg_instr_begin(unsigned RegNo) const {
296  return reg_instr_iterator(getRegUseDefListHead(RegNo));
297  }
299  return reg_instr_iterator(nullptr);
300  }
301 
303  reg_instructions(unsigned Reg) const {
304  return make_range(reg_instr_begin(Reg), reg_instr_end());
305  }
306 
307  /// reg_bundle_iterator/reg_bundle_begin/reg_bundle_end - Walk all defs and uses
308  /// of the specified register, stepping by bundle.
309  using reg_bundle_iterator =
311  reg_bundle_iterator reg_bundle_begin(unsigned RegNo) const {
312  return reg_bundle_iterator(getRegUseDefListHead(RegNo));
313  }
315  return reg_bundle_iterator(nullptr);
316  }
317 
320  }
321 
322  /// reg_empty - Return true if there are no instructions using or defining the
323  /// specified register (it may be live-in).
324  bool reg_empty(unsigned RegNo) const { return reg_begin(RegNo) == reg_end(); }
325 
326  /// reg_nodbg_iterator/reg_nodbg_begin/reg_nodbg_end - Walk all defs and uses
327  /// of the specified register, skipping those marked as Debug.
328  using reg_nodbg_iterator =
330  reg_nodbg_iterator reg_nodbg_begin(unsigned RegNo) const {
331  return reg_nodbg_iterator(getRegUseDefListHead(RegNo));
332  }
334  return reg_nodbg_iterator(nullptr);
335  }
336 
338  reg_nodbg_operands(unsigned Reg) const {
339  return make_range(reg_nodbg_begin(Reg), reg_nodbg_end());
340  }
341 
342  /// reg_instr_nodbg_iterator/reg_instr_nodbg_begin/reg_instr_nodbg_end - Walk
343  /// all defs and uses of the specified register, stepping by MachineInstr,
344  /// skipping those marked as Debug.
348  return reg_instr_nodbg_iterator(getRegUseDefListHead(RegNo));
349  }
351  return reg_instr_nodbg_iterator(nullptr);
352  }
353 
355  reg_nodbg_instructions(unsigned Reg) const {
357  }
358 
359  /// reg_bundle_nodbg_iterator/reg_bundle_nodbg_begin/reg_bundle_nodbg_end - Walk
360  /// all defs and uses of the specified register, stepping by bundle,
361  /// skipping those marked as Debug.
365  return reg_bundle_nodbg_iterator(getRegUseDefListHead(RegNo));
366  }
368  return reg_bundle_nodbg_iterator(nullptr);
369  }
370 
372  reg_nodbg_bundles(unsigned Reg) const {
374  }
375 
376  /// reg_nodbg_empty - Return true if the only instructions using or defining
377  /// Reg are Debug instructions.
378  bool reg_nodbg_empty(unsigned RegNo) const {
379  return reg_nodbg_begin(RegNo) == reg_nodbg_end();
380  }
381 
382  /// def_iterator/def_begin/def_end - Walk all defs of the specified register.
383  using def_iterator =
385  def_iterator def_begin(unsigned RegNo) const {
386  return def_iterator(getRegUseDefListHead(RegNo));
387  }
388  static def_iterator def_end() { return def_iterator(nullptr); }
389 
390  inline iterator_range<def_iterator> def_operands(unsigned Reg) const {
391  return make_range(def_begin(Reg), def_end());
392  }
393 
394  /// def_instr_iterator/def_instr_begin/def_instr_end - Walk all defs of the
395  /// specified register, stepping by MachineInst.
396  using def_instr_iterator =
398  def_instr_iterator def_instr_begin(unsigned RegNo) const {
399  return def_instr_iterator(getRegUseDefListHead(RegNo));
400  }
402  return def_instr_iterator(nullptr);
403  }
404 
406  def_instructions(unsigned Reg) const {
407  return make_range(def_instr_begin(Reg), def_instr_end());
408  }
409 
410  /// def_bundle_iterator/def_bundle_begin/def_bundle_end - Walk all defs of the
411  /// specified register, stepping by bundle.
412  using def_bundle_iterator =
414  def_bundle_iterator def_bundle_begin(unsigned RegNo) const {
415  return def_bundle_iterator(getRegUseDefListHead(RegNo));
416  }
418  return def_bundle_iterator(nullptr);
419  }
420 
423  }
424 
425  /// def_empty - Return true if there are no instructions defining the
426  /// specified register (it may be live-in).
427  bool def_empty(unsigned RegNo) const { return def_begin(RegNo) == def_end(); }
428 
429  StringRef getVRegName(unsigned Reg) const {
430  return VReg2Name.inBounds(Reg) ? StringRef(VReg2Name[Reg]) : "";
431  }
432 
433  void insertVRegByName(StringRef Name, unsigned Reg) {
434  assert((Name.empty() || VRegNames.find(Name) == VRegNames.end()) &&
435  "Named VRegs Must be Unique.");
436  if (!Name.empty()) {
437  VRegNames.insert(Name);
438  VReg2Name.grow(Reg);
439  VReg2Name[Reg] = Name.str();
440  }
441  }
442 
443  /// Return true if there is exactly one operand defining the specified
444  /// register.
445  bool hasOneDef(unsigned RegNo) const {
446  def_iterator DI = def_begin(RegNo);
447  if (DI == def_end())
448  return false;
449  return ++DI == def_end();
450  }
451 
452  /// use_iterator/use_begin/use_end - Walk all uses of the specified register.
453  using use_iterator =
455  use_iterator use_begin(unsigned RegNo) const {
456  return use_iterator(getRegUseDefListHead(RegNo));
457  }
458  static use_iterator use_end() { return use_iterator(nullptr); }
459 
460  inline iterator_range<use_iterator> use_operands(unsigned Reg) const {
461  return make_range(use_begin(Reg), use_end());
462  }
463 
464  /// use_instr_iterator/use_instr_begin/use_instr_end - Walk all uses of the
465  /// specified register, stepping by MachineInstr.
466  using use_instr_iterator =
468  use_instr_iterator use_instr_begin(unsigned RegNo) const {
469  return use_instr_iterator(getRegUseDefListHead(RegNo));
470  }
472  return use_instr_iterator(nullptr);
473  }
474 
476  use_instructions(unsigned Reg) const {
477  return make_range(use_instr_begin(Reg), use_instr_end());
478  }
479 
480  /// use_bundle_iterator/use_bundle_begin/use_bundle_end - Walk all uses of the
481  /// specified register, stepping by bundle.
482  using use_bundle_iterator =
484  use_bundle_iterator use_bundle_begin(unsigned RegNo) const {
485  return use_bundle_iterator(getRegUseDefListHead(RegNo));
486  }
488  return use_bundle_iterator(nullptr);
489  }
490 
493  }
494 
495  /// use_empty - Return true if there are no instructions using the specified
496  /// register.
497  bool use_empty(unsigned RegNo) const { return use_begin(RegNo) == use_end(); }
498 
499  /// hasOneUse - Return true if there is exactly one instruction using the
500  /// specified register.
501  bool hasOneUse(unsigned RegNo) const {
502  use_iterator UI = use_begin(RegNo);
503  if (UI == use_end())
504  return false;
505  return ++UI == use_end();
506  }
507 
508  /// use_nodbg_iterator/use_nodbg_begin/use_nodbg_end - Walk all uses of the
509  /// specified register, skipping those marked as Debug.
510  using use_nodbg_iterator =
512  use_nodbg_iterator use_nodbg_begin(unsigned RegNo) const {
513  return use_nodbg_iterator(getRegUseDefListHead(RegNo));
514  }
516  return use_nodbg_iterator(nullptr);
517  }
518 
520  use_nodbg_operands(unsigned Reg) const {
521  return make_range(use_nodbg_begin(Reg), use_nodbg_end());
522  }
523 
524  /// use_instr_nodbg_iterator/use_instr_nodbg_begin/use_instr_nodbg_end - Walk
525  /// all uses of the specified register, stepping by MachineInstr, skipping
526  /// those marked as Debug.
530  return use_instr_nodbg_iterator(getRegUseDefListHead(RegNo));
531  }
533  return use_instr_nodbg_iterator(nullptr);
534  }
535 
537  use_nodbg_instructions(unsigned Reg) const {
539  }
540 
541  /// use_bundle_nodbg_iterator/use_bundle_nodbg_begin/use_bundle_nodbg_end - Walk
542  /// all uses of the specified register, stepping by bundle, skipping
543  /// those marked as Debug.
547  return use_bundle_nodbg_iterator(getRegUseDefListHead(RegNo));
548  }
550  return use_bundle_nodbg_iterator(nullptr);
551  }
552 
554  use_nodbg_bundles(unsigned Reg) const {
556  }
557 
558  /// use_nodbg_empty - Return true if there are no non-Debug instructions
559  /// using the specified register.
560  bool use_nodbg_empty(unsigned RegNo) const {
561  return use_nodbg_begin(RegNo) == use_nodbg_end();
562  }
563 
564  /// hasOneNonDBGUse - Return true if there is exactly one non-Debug
565  /// instruction using the specified register.
566  bool hasOneNonDBGUse(unsigned RegNo) const;
567 
568  /// replaceRegWith - Replace all instances of FromReg with ToReg in the
569  /// machine function. This is like llvm-level X->replaceAllUsesWith(Y),
570  /// except that it also changes any definitions of the register as well.
571  ///
572  /// Note that it is usually necessary to first constrain ToReg's register
573  /// class and register bank to match the FromReg constraints using one of the
574  /// methods:
575  ///
576  /// constrainRegClass(ToReg, getRegClass(FromReg))
577  /// constrainRegAttrs(ToReg, FromReg)
578  /// RegisterBankInfo::constrainGenericRegister(ToReg,
579  /// *MRI.getRegClass(FromReg), MRI)
580  ///
581  /// These functions will return a falsy result if the virtual registers have
582  /// incompatible constraints.
583  ///
584  /// Note that if ToReg is a physical register the function will replace and
585  /// apply sub registers to ToReg in order to obtain a final/proper physical
586  /// register.
587  void replaceRegWith(unsigned FromReg, unsigned ToReg);
588 
589  /// getVRegDef - Return the machine instr that defines the specified virtual
590  /// register or null if none is found. This assumes that the code is in SSA
591  /// form, so there should only be one definition.
592  MachineInstr *getVRegDef(unsigned Reg) const;
593 
594  /// getUniqueVRegDef - Return the unique machine instr that defines the
595  /// specified virtual register or null if none is found. If there are
596  /// multiple definitions or no definition, return null.
597  MachineInstr *getUniqueVRegDef(unsigned Reg) const;
598 
599  /// clearKillFlags - Iterate over all the uses of the given register and
600  /// clear the kill flag from the MachineOperand. This function is used by
601  /// optimization passes which extend register lifetimes and need only
602  /// preserve conservative kill flag information.
603  void clearKillFlags(unsigned Reg) const;
604 
605  void dumpUses(unsigned RegNo) const;
606 
607  /// Returns true if PhysReg is unallocatable and constant throughout the
608  /// function. Writing to a constant register has no effect.
609  bool isConstantPhysReg(unsigned PhysReg) const;
610 
611  /// Returns true if either isConstantPhysReg or TRI->isCallerPreservedPhysReg
612  /// returns true. This is a utility member function.
613  bool isCallerPreservedOrConstPhysReg(unsigned PhysReg) const;
614 
615  /// Get an iterator over the pressure sets affected by the given physical or
616  /// virtual register. If RegUnit is physical, it must be a register unit (from
617  /// MCRegUnitIterator).
618  PSetIterator getPressureSets(unsigned RegUnit) const;
619 
620  //===--------------------------------------------------------------------===//
621  // Virtual Register Info
622  //===--------------------------------------------------------------------===//
623 
624  /// Return the register class of the specified virtual register.
625  /// This shouldn't be used directly unless \p Reg has a register class.
626  /// \see getRegClassOrNull when this might happen.
627  const TargetRegisterClass *getRegClass(unsigned Reg) const {
628  assert(VRegInfo[Reg].first.is<const TargetRegisterClass *>() &&
629  "Register class not set, wrong accessor");
630  return VRegInfo[Reg].first.get<const TargetRegisterClass *>();
631  }
632 
633  /// Return the register class of \p Reg, or null if Reg has not been assigned
634  /// a register class yet.
635  ///
636  /// \note A null register class can only happen when these two
637  /// conditions are met:
638  /// 1. Generic virtual registers are created.
639  /// 2. The machine function has not completely been through the
640  /// instruction selection process.
641  /// None of this condition is possible without GlobalISel for now.
642  /// In other words, if GlobalISel is not used or if the query happens after
643  /// the select pass, using getRegClass is safe.
644  const TargetRegisterClass *getRegClassOrNull(unsigned Reg) const {
645  const RegClassOrRegBank &Val = VRegInfo[Reg].first;
646  return Val.dyn_cast<const TargetRegisterClass *>();
647  }
648 
649  /// Return the register bank of \p Reg, or null if Reg has not been assigned
650  /// a register bank or has been assigned a register class.
651  /// \note It is possible to get the register bank from the register class via
652  /// RegisterBankInfo::getRegBankFromRegClass.
653  const RegisterBank *getRegBankOrNull(unsigned Reg) const {
654  const RegClassOrRegBank &Val = VRegInfo[Reg].first;
655  return Val.dyn_cast<const RegisterBank *>();
656  }
657 
658  /// Return the register bank or register class of \p Reg.
659  /// \note Before the register bank gets assigned (i.e., before the
660  /// RegBankSelect pass) \p Reg may not have either.
661  const RegClassOrRegBank &getRegClassOrRegBank(unsigned Reg) const {
662  return VRegInfo[Reg].first;
663  }
664 
665  /// setRegClass - Set the register class of the specified virtual register.
666  void setRegClass(unsigned Reg, const TargetRegisterClass *RC);
667 
668  /// Set the register bank to \p RegBank for \p Reg.
669  void setRegBank(unsigned Reg, const RegisterBank &RegBank);
670 
671  void setRegClassOrRegBank(unsigned Reg,
672  const RegClassOrRegBank &RCOrRB){
673  VRegInfo[Reg].first = RCOrRB;
674  }
675 
676  /// constrainRegClass - Constrain the register class of the specified virtual
677  /// register to be a common subclass of RC and the current register class,
678  /// but only if the new class has at least MinNumRegs registers. Return the
679  /// new register class, or NULL if no such class exists.
680  /// This should only be used when the constraint is known to be trivial, like
681  /// GR32 -> GR32_NOSP. Beware of increasing register pressure.
682  ///
683  /// \note Assumes that the register has a register class assigned.
684  /// Use RegisterBankInfo::constrainGenericRegister in GlobalISel's
685  /// InstructionSelect pass and constrainRegAttrs in every other pass,
686  /// including non-select passes of GlobalISel, instead.
687  const TargetRegisterClass *constrainRegClass(unsigned Reg,
688  const TargetRegisterClass *RC,
689  unsigned MinNumRegs = 0);
690 
691  /// Constrain the register class or the register bank of the virtual register
692  /// \p Reg to be a common subclass and a common bank of both registers
693  /// provided respectively. Do nothing if any of the attributes (classes,
694  /// banks, or low-level types) of the registers are deemed incompatible, or if
695  /// the resulting register will have a class smaller than before and of size
696  /// less than \p MinNumRegs. Return true if such register attributes exist,
697  /// false otherwise.
698  ///
699  /// \note Assumes that each register has either a low-level type or a class
700  /// assigned, but not both. Use this method instead of constrainRegClass and
701  /// RegisterBankInfo::constrainGenericRegister everywhere but SelectionDAG
702  /// ISel / FastISel and GlobalISel's InstructionSelect pass respectively.
703  bool constrainRegAttrs(unsigned Reg, unsigned ConstrainingReg,
704  unsigned MinNumRegs = 0);
705 
706  /// recomputeRegClass - Try to find a legal super-class of Reg's register
707  /// class that still satisfies the constraints from the instructions using
708  /// Reg. Returns true if Reg was upgraded.
709  ///
710  /// This method can be used after constraints have been removed from a
711  /// virtual register, for example after removing instructions or splitting
712  /// the live range.
713  bool recomputeRegClass(unsigned Reg);
714 
715  /// createVirtualRegister - Create and return a new virtual register in the
716  /// function with the specified register class.
717  unsigned createVirtualRegister(const TargetRegisterClass *RegClass,
718  StringRef Name = "");
719 
720  /// Create and return a new virtual register in the function with the same
721  /// attributes as the given register.
722  unsigned cloneVirtualRegister(unsigned VReg, StringRef Name = "");
723 
724  /// Get the low-level type of \p Reg or LLT{} if Reg is not a generic
725  /// (target independent) virtual register.
726  LLT getType(unsigned Reg) const {
727  if (TargetRegisterInfo::isVirtualRegister(Reg) && VRegToType.inBounds(Reg))
728  return VRegToType[Reg];
729  return LLT{};
730  }
731 
732  /// Set the low-level type of \p VReg to \p Ty.
733  void setType(unsigned VReg, LLT Ty);
734 
735  /// Create and return a new generic virtual register with low-level
736  /// type \p Ty.
737  unsigned createGenericVirtualRegister(LLT Ty, StringRef Name = "");
738 
739  /// Remove all types associated to virtual registers (after instruction
740  /// selection and constraining of all generic virtual registers).
741  void clearVirtRegTypes();
742 
743  /// Creates a new virtual register that has no register class, register bank
744  /// or size assigned yet. This is only allowed to be used
745  /// temporarily while constructing machine instructions. Most operations are
746  /// undefined on an incomplete register until one of setRegClass(),
747  /// setRegBank() or setSize() has been called on it.
749 
750  /// getNumVirtRegs - Return the number of virtual registers created.
751  unsigned getNumVirtRegs() const { return VRegInfo.size(); }
752 
753  /// clearVirtRegs - Remove all virtual registers (after physreg assignment).
754  void clearVirtRegs();
755 
756  /// setRegAllocationHint - Specify a register allocation hint for the
757  /// specified virtual register. This is typically used by target, and in case
758  /// of an earlier hint it will be overwritten.
759  void setRegAllocationHint(unsigned VReg, unsigned Type, unsigned PrefReg) {
761  RegAllocHints[VReg].first = Type;
762  RegAllocHints[VReg].second.clear();
763  RegAllocHints[VReg].second.push_back(PrefReg);
764  }
765 
766  /// addRegAllocationHint - Add a register allocation hint to the hints
767  /// vector for VReg.
768  void addRegAllocationHint(unsigned VReg, unsigned PrefReg) {
770  RegAllocHints[VReg].second.push_back(PrefReg);
771  }
772 
773  /// Specify the preferred (target independent) register allocation hint for
774  /// the specified virtual register.
775  void setSimpleHint(unsigned VReg, unsigned PrefReg) {
776  setRegAllocationHint(VReg, /*Type=*/0, PrefReg);
777  }
778 
779  void clearSimpleHint(unsigned VReg) {
780  assert (RegAllocHints[VReg].first == 0 &&
781  "Expected to clear a non-target hint!");
782  RegAllocHints[VReg].second.clear();
783  }
784 
785  /// getRegAllocationHint - Return the register allocation hint for the
786  /// specified virtual register. If there are many hints, this returns the
787  /// one with the greatest weight.
788  std::pair<unsigned, unsigned>
789  getRegAllocationHint(unsigned VReg) const {
791  unsigned BestHint = (RegAllocHints[VReg].second.size() ?
792  RegAllocHints[VReg].second[0] : 0);
793  return std::pair<unsigned, unsigned>(RegAllocHints[VReg].first, BestHint);
794  }
795 
796  /// getSimpleHint - same as getRegAllocationHint except it will only return
797  /// a target independent hint.
798  unsigned getSimpleHint(unsigned VReg) const {
800  std::pair<unsigned, unsigned> Hint = getRegAllocationHint(VReg);
801  return Hint.first ? 0 : Hint.second;
802  }
803 
804  /// getRegAllocationHints - Return a reference to the vector of all
805  /// register allocation hints for VReg.
806  const std::pair<unsigned, SmallVector<unsigned, 4>>
807  &getRegAllocationHints(unsigned VReg) const {
809  return RegAllocHints[VReg];
810  }
811 
812  /// markUsesInDebugValueAsUndef - Mark every DBG_VALUE referencing the
813  /// specified register as undefined which causes the DBG_VALUE to be
814  /// deleted during LiveDebugVariables analysis.
815  void markUsesInDebugValueAsUndef(unsigned Reg) const;
816 
817  /// Return true if the specified register is modified in this function.
818  /// This checks that no defining machine operands exist for the register or
819  /// any of its aliases. Definitions found on functions marked noreturn are
820  /// ignored, to consider them pass 'true' for optional parameter
821  /// SkipNoReturnDef. The register is also considered modified when it is set
822  /// in the UsedPhysRegMask.
823  bool isPhysRegModified(unsigned PhysReg, bool SkipNoReturnDef = false) const;
824 
825  /// Return true if the specified register is modified or read in this
826  /// function. This checks that no machine operands exist for the register or
827  /// any of its aliases. The register is also considered used when it is set
828  /// in the UsedPhysRegMask.
829  bool isPhysRegUsed(unsigned PhysReg) const;
830 
831  /// addPhysRegsUsedFromRegMask - Mark any registers not in RegMask as used.
832  /// This corresponds to the bit mask attached to register mask operands.
833  void addPhysRegsUsedFromRegMask(const uint32_t *RegMask) {
834  UsedPhysRegMask.setBitsNotInMask(RegMask);
835  }
836 
837  const BitVector &getUsedPhysRegsMask() const { return UsedPhysRegMask; }
838 
839  //===--------------------------------------------------------------------===//
840  // Reserved Register Info
841  //===--------------------------------------------------------------------===//
842  //
843  // The set of reserved registers must be invariant during register
844  // allocation. For example, the target cannot suddenly decide it needs a
845  // frame pointer when the register allocator has already used the frame
846  // pointer register for something else.
847  //
848  // These methods can be used by target hooks like hasFP() to avoid changing
849  // the reserved register set during register allocation.
850 
851  /// freezeReservedRegs - Called by the register allocator to freeze the set
852  /// of reserved registers before allocation begins.
853  void freezeReservedRegs(const MachineFunction&);
854 
855  /// reservedRegsFrozen - Returns true after freezeReservedRegs() was called
856  /// to ensure the set of reserved registers stays constant.
857  bool reservedRegsFrozen() const {
858  return !ReservedRegs.empty();
859  }
860 
861  /// canReserveReg - Returns true if PhysReg can be used as a reserved
862  /// register. Any register can be reserved before freezeReservedRegs() is
863  /// called.
864  bool canReserveReg(unsigned PhysReg) const {
865  return !reservedRegsFrozen() || ReservedRegs.test(PhysReg);
866  }
867 
868  /// getReservedRegs - Returns a reference to the frozen set of reserved
869  /// registers. This method should always be preferred to calling
870  /// TRI::getReservedRegs() when possible.
871  const BitVector &getReservedRegs() const {
873  "Reserved registers haven't been frozen yet. "
874  "Use TRI::getReservedRegs().");
875  return ReservedRegs;
876  }
877 
878  /// isReserved - Returns true when PhysReg is a reserved register.
879  ///
880  /// Reserved registers may belong to an allocatable register class, but the
881  /// target has explicitly requested that they are not used.
882  bool isReserved(unsigned PhysReg) const {
883  return getReservedRegs().test(PhysReg);
884  }
885 
886  /// Returns true when the given register unit is considered reserved.
887  ///
888  /// Register units are considered reserved when for at least one of their
889  /// root registers, the root register and all super registers are reserved.
890  /// This currently iterates the register hierarchy and may be slower than
891  /// expected.
892  bool isReservedRegUnit(unsigned Unit) const;
893 
894  /// isAllocatable - Returns true when PhysReg belongs to an allocatable
895  /// register class and it hasn't been reserved.
896  ///
897  /// Allocatable registers may show up in the allocation order of some virtual
898  /// register, so a register allocator needs to track its liveness and
899  /// availability.
900  bool isAllocatable(unsigned PhysReg) const {
901  return getTargetRegisterInfo()->isInAllocatableClass(PhysReg) &&
902  !isReserved(PhysReg);
903  }
904 
905  //===--------------------------------------------------------------------===//
906  // LiveIn Management
907  //===--------------------------------------------------------------------===//
908 
909  /// addLiveIn - Add the specified register as a live-in. Note that it
910  /// is an error to add the same register to the same set more than once.
911  void addLiveIn(unsigned Reg, unsigned vreg = 0) {
912  LiveIns.push_back(std::make_pair(Reg, vreg));
913  }
914 
915  // Iteration support for the live-ins set. It's kept in sorted order
916  // by register number.
917  using livein_iterator =
918  std::vector<std::pair<unsigned,unsigned>>::const_iterator;
919  livein_iterator livein_begin() const { return LiveIns.begin(); }
920  livein_iterator livein_end() const { return LiveIns.end(); }
921  bool livein_empty() const { return LiveIns.empty(); }
922 
924  return LiveIns;
925  }
926 
927  bool isLiveIn(unsigned Reg) const;
928 
929  /// getLiveInPhysReg - If VReg is a live-in virtual register, return the
930  /// corresponding live-in physical register.
931  unsigned getLiveInPhysReg(unsigned VReg) const;
932 
933  /// getLiveInVirtReg - If PReg is a live-in physical register, return the
934  /// corresponding live-in physical register.
935  unsigned getLiveInVirtReg(unsigned PReg) const;
936 
937  /// EmitLiveInCopies - Emit copies to initialize livein virtual registers
938  /// into the given entry block.
939  void EmitLiveInCopies(MachineBasicBlock *EntryMBB,
940  const TargetRegisterInfo &TRI,
941  const TargetInstrInfo &TII);
942 
943  /// Returns a mask covering all bits that can appear in lane masks of
944  /// subregisters of the virtual register @p Reg.
945  LaneBitmask getMaxLaneMaskForVReg(unsigned Reg) const;
946 
947  /// defusechain_iterator - This class provides iterator support for machine
948  /// operands in the function that use or define a specific register. If
949  /// ReturnUses is true it returns uses of registers, if ReturnDefs is true it
950  /// returns defs. If neither are true then you are silly and it always
951  /// returns end(). If SkipDebug is true it skips uses marked Debug
952  /// when incrementing.
953  template<bool ReturnUses, bool ReturnDefs, bool SkipDebug,
954  bool ByOperand, bool ByInstr, bool ByBundle>
956  : public std::iterator<std::forward_iterator_tag, MachineInstr, ptrdiff_t> {
957  friend class MachineRegisterInfo;
958 
959  MachineOperand *Op = nullptr;
960 
961  explicit defusechain_iterator(MachineOperand *op) : Op(op) {
962  // If the first node isn't one we're interested in, advance to one that
963  // we are interested in.
964  if (op) {
965  if ((!ReturnUses && op->isUse()) ||
966  (!ReturnDefs && op->isDef()) ||
967  (SkipDebug && op->isDebug()))
968  advance();
969  }
970  }
971 
972  void advance() {
973  assert(Op && "Cannot increment end iterator!");
974  Op = getNextOperandForReg(Op);
975 
976  // All defs come before the uses, so stop def_iterator early.
977  if (!ReturnUses) {
978  if (Op) {
979  if (Op->isUse())
980  Op = nullptr;
981  else
982  assert(!Op->isDebug() && "Can't have debug defs");
983  }
984  } else {
985  // If this is an operand we don't care about, skip it.
986  while (Op && ((!ReturnDefs && Op->isDef()) ||
987  (SkipDebug && Op->isDebug())))
988  Op = getNextOperandForReg(Op);
989  }
990  }
991 
992  public:
993  using reference = std::iterator<std::forward_iterator_tag,
995  using pointer = std::iterator<std::forward_iterator_tag,
997 
998  defusechain_iterator() = default;
999 
1000  bool operator==(const defusechain_iterator &x) const {
1001  return Op == x.Op;
1002  }
1003  bool operator!=(const defusechain_iterator &x) const {
1004  return !operator==(x);
1005  }
1006 
1007  /// atEnd - return true if this iterator is equal to reg_end() on the value.
1008  bool atEnd() const { return Op == nullptr; }
1009 
1010  // Iterator traversal: forward iteration only
1011  defusechain_iterator &operator++() { // Preincrement
1012  assert(Op && "Cannot increment end iterator!");
1013  if (ByOperand)
1014  advance();
1015  else if (ByInstr) {
1016  MachineInstr *P = Op->getParent();
1017  do {
1018  advance();
1019  } while (Op && Op->getParent() == P);
1020  } else if (ByBundle) {
1023  do {
1024  advance();
1025  } while (Op && getBundleStart(Op->getParent()->getIterator()) == P);
1026  }
1027 
1028  return *this;
1029  }
1030  defusechain_iterator operator++(int) { // Postincrement
1031  defusechain_iterator tmp = *this; ++*this; return tmp;
1032  }
1033 
1034  /// getOperandNo - Return the operand # of this MachineOperand in its
1035  /// MachineInstr.
1036  unsigned getOperandNo() const {
1037  assert(Op && "Cannot dereference end iterator!");
1038  return Op - &Op->getParent()->getOperand(0);
1039  }
1040 
1041  // Retrieve a reference to the current operand.
1043  assert(Op && "Cannot dereference end iterator!");
1044  return *Op;
1045  }
1046 
1048  assert(Op && "Cannot dereference end iterator!");
1049  return Op;
1050  }
1051  };
1052 
1053  /// defusechain_iterator - This class provides iterator support for machine
1054  /// operands in the function that use or define a specific register. If
1055  /// ReturnUses is true it returns uses of registers, if ReturnDefs is true it
1056  /// returns defs. If neither are true then you are silly and it always
1057  /// returns end(). If SkipDebug is true it skips uses marked Debug
1058  /// when incrementing.
1059  template<bool ReturnUses, bool ReturnDefs, bool SkipDebug,
1060  bool ByOperand, bool ByInstr, bool ByBundle>
1062  : public std::iterator<std::forward_iterator_tag, MachineInstr, ptrdiff_t> {
1063  friend class MachineRegisterInfo;
1064 
1065  MachineOperand *Op = nullptr;
1066 
1067  explicit defusechain_instr_iterator(MachineOperand *op) : Op(op) {
1068  // If the first node isn't one we're interested in, advance to one that
1069  // we are interested in.
1070  if (op) {
1071  if ((!ReturnUses && op->isUse()) ||
1072  (!ReturnDefs && op->isDef()) ||
1073  (SkipDebug && op->isDebug()))
1074  advance();
1075  }
1076  }
1077 
1078  void advance() {
1079  assert(Op && "Cannot increment end iterator!");
1080  Op = getNextOperandForReg(Op);
1081 
1082  // All defs come before the uses, so stop def_iterator early.
1083  if (!ReturnUses) {
1084  if (Op) {
1085  if (Op->isUse())
1086  Op = nullptr;
1087  else
1088  assert(!Op->isDebug() && "Can't have debug defs");
1089  }
1090  } else {
1091  // If this is an operand we don't care about, skip it.
1092  while (Op && ((!ReturnDefs && Op->isDef()) ||
1093  (SkipDebug && Op->isDebug())))
1094  Op = getNextOperandForReg(Op);
1095  }
1096  }
1097 
1098  public:
1099  using reference = std::iterator<std::forward_iterator_tag,
1101  using pointer = std::iterator<std::forward_iterator_tag,
1103 
1104  defusechain_instr_iterator() = default;
1105 
1107  return Op == x.Op;
1108  }
1110  return !operator==(x);
1111  }
1112 
1113  /// atEnd - return true if this iterator is equal to reg_end() on the value.
1114  bool atEnd() const { return Op == nullptr; }
1115 
1116  // Iterator traversal: forward iteration only
1118  assert(Op && "Cannot increment end iterator!");
1119  if (ByOperand)
1120  advance();
1121  else if (ByInstr) {
1122  MachineInstr *P = Op->getParent();
1123  do {
1124  advance();
1125  } while (Op && Op->getParent() == P);
1126  } else if (ByBundle) {
1129  do {
1130  advance();
1131  } while (Op && getBundleStart(Op->getParent()->getIterator()) == P);
1132  }
1133 
1134  return *this;
1135  }
1136  defusechain_instr_iterator operator++(int) { // Postincrement
1137  defusechain_instr_iterator tmp = *this; ++*this; return tmp;
1138  }
1139 
1140  // Retrieve a reference to the current operand.
1142  assert(Op && "Cannot dereference end iterator!");
1143  if (ByBundle)
1144  return *getBundleStart(Op->getParent()->getIterator());
1145  return *Op->getParent();
1146  }
1147 
1148  MachineInstr *operator->() const { return &operator*(); }
1149  };
1150 };
1151 
1152 /// Iterate over the pressure sets affected by the given physical or virtual
1153 /// register. If Reg is physical, it must be a register unit (from
1154 /// MCRegUnitIterator).
1156  const int *PSet = nullptr;
1157  unsigned Weight = 0;
1158 
1159 public:
1160  PSetIterator() = default;
1161 
1162  PSetIterator(unsigned RegUnit, const MachineRegisterInfo *MRI) {
1163  const TargetRegisterInfo *TRI = MRI->getTargetRegisterInfo();
1165  const TargetRegisterClass *RC = MRI->getRegClass(RegUnit);
1166  PSet = TRI->getRegClassPressureSets(RC);
1167  Weight = TRI->getRegClassWeight(RC).RegWeight;
1168  }
1169  else {
1170  PSet = TRI->getRegUnitPressureSets(RegUnit);
1171  Weight = TRI->getRegUnitWeight(RegUnit);
1172  }
1173  if (*PSet == -1)
1174  PSet = nullptr;
1175  }
1176 
1177  bool isValid() const { return PSet; }
1178 
1179  unsigned getWeight() const { return Weight; }
1180 
1181  unsigned operator*() const { return *PSet; }
1182 
1183  void operator++() {
1184  assert(isValid() && "Invalid PSetIterator.");
1185  ++PSet;
1186  if (*PSet == -1)
1187  PSet = nullptr;
1188  }
1189 };
1190 
1192 getPressureSets(unsigned RegUnit) const {
1193  return PSetIterator(RegUnit, this);
1194 }
1195 
1196 } // end namespace llvm
1197 
1198 #endif // LLVM_CODEGEN_MACHINEREGISTERINFO_H
bool operator!=(const defusechain_iterator &x) const
bool reg_nodbg_empty(unsigned RegNo) const
reg_nodbg_empty - Return true if the only instructions using or defining Reg are Debug instructions...
defusechain_instr_iterator< true, false, false, false, true, false > use_instr_iterator
use_instr_iterator/use_instr_begin/use_instr_end - Walk all uses of the specified register...
defusechain_instr_iterator< true, true, false, false, true, false > reg_instr_iterator
reg_instr_iterator/reg_instr_begin/reg_instr_end - Walk all defs and uses of the specified register...
iterator_range< reg_instr_nodbg_iterator > reg_nodbg_instructions(unsigned Reg) const
Type
MessagePack types as defined in the standard, with the exception of Integer being divided into a sign...
Definition: MsgPackReader.h:49
A common definition of LaneBitmask for use in TableGen and CodeGen.
void EmitLiveInCopies(MachineBasicBlock *EntryMBB, const TargetRegisterInfo &TRI, const TargetInstrInfo &TII)
EmitLiveInCopies - Emit copies to initialize livein virtual registers into the given entry block...
defusechain_iterator< false, true, false, true, false, false > def_iterator
def_iterator/def_begin/def_end - Walk all defs of the specified register.
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
iterator_range< def_bundle_iterator > def_bundles(unsigned Reg) const
use_bundle_iterator use_bundle_begin(unsigned RegNo) const
bool use_nodbg_empty(unsigned RegNo) const
use_nodbg_empty - Return true if there are no non-Debug instructions using the specified register...
LLVM_NODISCARD std::string str() const
str - Get the contents as an std::string.
Definition: StringRef.h:228
const TargetRegisterClass * getRegClass(unsigned Reg) const
Return the register class of the specified virtual register.
livein_iterator livein_begin() const
StorageT::size_type size() const
Definition: IndexedMap.h:78
void removeRegOperandFromUseList(MachineOperand *MO)
Remove MO from its use-def list.
bool isAllocatable(unsigned PhysReg) const
isAllocatable - Returns true when PhysReg belongs to an allocatable register class and it hasn&#39;t been...
void clearVirtRegTypes()
Remove all types associated to virtual registers (after instruction selection and constraining of all...
LaneBitmask getMaxLaneMaskForVReg(unsigned Reg) const
Returns a mask covering all bits that can appear in lane masks of subregisters of the virtual registe...
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
MachineFunctionProperties & reset(Property P)
bool empty() const
empty - Tests whether there are no bits in this bitvector.
Definition: BitVector.h:167
PointerUnion< const TargetRegisterClass *, const RegisterBank * > RegClassOrRegBank
Convenient type to represent either a register class or a register bank.
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
void addLiveIn(unsigned Reg, unsigned vreg=0)
addLiveIn - Add the specified register as a live-in.
const MachineFunctionProperties & getProperties() const
Get the function properties.
bool isPhysRegModified(unsigned PhysReg, bool SkipNoReturnDef=false) const
Return true if the specified register is modified in this function.
This provides a very simple, boring adaptor for a begin and end iterator into a range type...
iterator_range< use_nodbg_iterator > use_nodbg_operands(unsigned Reg) const
iterator_range< use_bundle_iterator > use_bundles(unsigned Reg) const
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
iterator_range< reg_nodbg_iterator > reg_nodbg_operands(unsigned Reg) const
unsigned Reg
bool test(unsigned Idx) const
Definition: BitVector.h:502
iterator_range< reg_iterator > reg_operands(unsigned Reg) const
iterator find(StringRef Key)
Definition: StringMap.h:333
bool constrainRegAttrs(unsigned Reg, unsigned ConstrainingReg, unsigned MinNumRegs=0)
Constrain the register class or the register bank of the virtual register Reg to be a common subclass...
void setBitsNotInMask(const uint32_t *Mask, unsigned MaskWords=~0u)
setBitsNotInMask - Add a bit to this vector for every &#39;0&#39; bit in Mask.
Definition: BitVector.h:788
LLT getType(unsigned Reg) const
Get the low-level type of Reg or LLT{} if Reg is not a generic (target independent) virtual register...
virtual const int * getRegClassPressureSets(const TargetRegisterClass *RC) const =0
Get the dimensions of register pressure impacted by this register class.
unsigned const TargetRegisterInfo * TRI
bool hasOneDef(unsigned RegNo) const
Return true if there is exactly one operand defining the specified register.
reg_nodbg_iterator reg_nodbg_begin(unsigned RegNo) const
defusechain_instr_iterator< false, true, false, false, false, true > def_bundle_iterator
def_bundle_iterator/def_bundle_begin/def_bundle_end - Walk all defs of the specified register...
void setRegBank(unsigned Reg, const RegisterBank &RegBank)
Set the register bank to RegBank for Reg.
bool reservedRegsFrozen() const
reservedRegsFrozen - Returns true after freezeReservedRegs() was called to ensure the set of reserved...
#define op(i)
use_nodbg_iterator use_nodbg_begin(unsigned RegNo) const
void verifyUseLists() const
Verify the use list of all registers.
static use_nodbg_iterator use_nodbg_end()
defusechain_instr_iterator< true, false, true, false, false, true > use_bundle_nodbg_iterator
use_bundle_nodbg_iterator/use_bundle_nodbg_begin/use_bundle_nodbg_end - Walk all uses of the specifie...
void clearVirtRegs()
clearVirtRegs - Remove all virtual registers (after physreg assignment).
bool operator==(const defusechain_iterator &x) const
virtual unsigned getRegUnitWeight(unsigned RegUnit) const =0
Get the weight in units of pressure for this register unit.
std::iterator< std::forward_iterator_tag, MachineInstr, ptrdiff_t >::reference reference
amdgpu Simplify well known AMD library false Value Value const Twine & Name
static use_iterator use_end()
iterator_range< reg_bundle_nodbg_iterator > reg_nodbg_bundles(unsigned Reg) const
reg_instr_nodbg_iterator reg_instr_nodbg_begin(unsigned RegNo) const
const HexagonInstrInfo * TII
defusechain_instr_iterator< true, true, true, false, true, false > reg_instr_nodbg_iterator
reg_instr_nodbg_iterator/reg_instr_nodbg_begin/reg_instr_nodbg_end - Walk all defs and uses of the sp...
void freezeReservedRegs(const MachineFunction &)
freezeReservedRegs - Called by the register allocator to freeze the set of reserved registers before ...
defusechain_instr_iterator< true, true, false, false, false, true > reg_bundle_iterator
reg_bundle_iterator/reg_bundle_begin/reg_bundle_end - Walk all defs and uses of the specified registe...
def_iterator def_begin(unsigned RegNo) const
defusechain_iterator< true, true, true, true, false, false > reg_nodbg_iterator
reg_nodbg_iterator/reg_nodbg_begin/reg_nodbg_end - Walk all defs and uses of the specified register...
APInt operator*(APInt a, uint64_t RHS)
Definition: APInt.h:2085
unsigned getLiveInPhysReg(unsigned VReg) const
getLiveInPhysReg - If VReg is a live-in virtual register, return the corresponding live-in physical r...
static reg_instr_iterator reg_instr_end()
MachineInstr * getVRegDef(unsigned Reg) const
getVRegDef - Return the machine instr that defines the specified virtual register or null if none is ...
defusechain_iterator - This class provides iterator support for machine operands in the function that...
void insertVRegByName(StringRef Name, unsigned Reg)
MachineBasicBlock::instr_iterator getBundleStart(MachineBasicBlock::instr_iterator I)
Returns an iterator to the first instruction in the bundle containing I.
defusechain_iterator< true, false, true, true, false, false > use_nodbg_iterator
use_nodbg_iterator/use_nodbg_begin/use_nodbg_end - Walk all uses of the specified register...
void clearKillFlags(unsigned Reg) const
clearKillFlags - Iterate over all the uses of the given register and clear the kill flag from the Mac...
const RegClassOrRegBank & getRegClassOrRegBank(unsigned Reg) const
Return the register bank or register class of Reg.
use_bundle_nodbg_iterator use_bundle_nodbg_begin(unsigned RegNo) const
iterator_range< def_iterator > def_operands(unsigned Reg) const
livein_iterator livein_end() const
static def_instr_iterator def_instr_end()
PSetIterator(unsigned RegUnit, const MachineRegisterInfo *MRI)
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:133
bool canReserveReg(unsigned PhysReg) const
canReserveReg - Returns true if PhysReg can be used as a reserved register.
defusechain_instr_iterator< false, true, false, false, true, false > def_instr_iterator
def_instr_iterator/def_instr_begin/def_instr_end - Walk all defs of the specified register...
std::iterator< std::forward_iterator_tag, MachineInstr, ptrdiff_t >::pointer pointer
void disableCalleeSavedRegister(unsigned Reg)
Disables the register from the list of CSRs.
bool inBounds(IndexT n) const
Definition: IndexedMap.h:74
const TargetRegisterClass * constrainRegClass(unsigned Reg, const TargetRegisterClass *RC, unsigned MinNumRegs=0)
constrainRegClass - Constrain the register class of the specified virtual register to be a common sub...
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
TargetInstrInfo - Interface to description of machine instruction set.
#define P(N)
reg_bundle_iterator reg_bundle_begin(unsigned RegNo) const
const TargetRegisterInfo * getTargetRegisterInfo() const
unsigned const MachineRegisterInfo * MRI
bool isCallerPreservedOrConstPhysReg(unsigned PhysReg) const
Returns true if either isConstantPhysReg or TRI->isCallerPreservedPhysReg returns true...
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:46
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
void setType(unsigned VReg, LLT Ty)
Set the low-level type of VReg to Ty.
use_instr_iterator use_instr_begin(unsigned RegNo) const
defusechain_iterator< true, false, false, true, false, false > use_iterator
use_iterator/use_begin/use_end - Walk all uses of the specified register.
bool def_empty(unsigned RegNo) const
def_empty - Return true if there are no instructions defining the specified register (it may be live-...
bool atEnd() const
atEnd - return true if this iterator is equal to reg_end() on the value.
const RegisterBank * getRegBankOrNull(unsigned Reg) const
Return the register bank of Reg, or null if Reg has not been assigned a register bank or has been ass...
self_iterator getIterator()
Definition: ilist_node.h:82
void setCalleeSavedRegs(ArrayRef< MCPhysReg > CSRs)
Sets the updated Callee Saved Registers list.
unsigned getNumVirtRegs() const
getNumVirtRegs - Return the number of virtual registers created.
T dyn_cast() const
Returns the current pointer if it is of the specified pointer type, otherwises returns null...
Definition: PointerUnion.h:142
struct llvm::MachineOperand::@153::@155 Reg
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
std::iterator< std::forward_iterator_tag, MachineInstr, ptrdiff_t >::reference reference
std::pair< typename base::iterator, bool > insert(StringRef Key)
Definition: StringSet.h:38
bool isConstantPhysReg(unsigned PhysReg) const
Returns true if PhysReg is unallocatable and constant throughout the function.
unsigned first
const bool HasDisjunctSubRegs
Whether the class supports two (or more) disjunct subregister indices.
unsigned createGenericVirtualRegister(LLT Ty, StringRef Name="")
Create and return a new generic virtual register with low-level type Ty.
iterator_range< T > make_range(T x, T y)
Convenience function for iterating over sub-ranges.
static use_bundle_nodbg_iterator use_bundle_nodbg_end()
unsigned createIncompleteVirtualRegister(StringRef Name="")
Creates a new virtual register that has no register class, register bank or size assigned yet...
defusechain_iterator< true, true, false, true, false, false > reg_iterator
reg_iterator/reg_begin/reg_end - Walk all defs and uses of the specified register.
iterator_range< use_iterator > use_operands(unsigned Reg) const
MachineOperand class - Representation of each machine instruction operand.
virtual const RegClassWeight & getRegClassWeight(const TargetRegisterClass *RC) const =0
Get the weight in units of pressure for this register class.
void setRegAllocationHint(unsigned VReg, unsigned Type, unsigned PrefReg)
setRegAllocationHint - Specify a register allocation hint for the specified virtual register...
bool isInAllocatableClass(unsigned RegNo) const
Return true if the register is in the allocation of any register class.
bool atEnd() const
atEnd - return true if this iterator is equal to reg_end() on the value.
static reg_bundle_iterator reg_bundle_end()
bool isReservedRegUnit(unsigned Unit) const
Returns true when the given register unit is considered reserved.
reg_iterator reg_begin(unsigned RegNo) const
void clearSimpleHint(unsigned VReg)
void invalidateLiveness()
invalidateLiveness - Indicates that register liveness is no longer being tracked accurately.
This class implements the register bank concept.
Definition: RegisterBank.h:29
const BitVector & getUsedPhysRegsMask() const
bool recomputeRegClass(unsigned Reg)
recomputeRegClass - Try to find a legal super-class of Reg&#39;s register class that still satisfies the ...
void resetDelegate(Delegate *delegate)
MachineInstr * getUniqueVRegDef(unsigned Reg) const
getUniqueVRegDef - Return the unique machine instr that defines the specified virtual register or nul...
static reg_bundle_nodbg_iterator reg_bundle_nodbg_end()
bool isPhysRegUsed(unsigned PhysReg) const
Return true if the specified register is modified or read in this function.
A range adaptor for a pair of iterators.
iterator_range< reg_bundle_iterator > reg_bundles(unsigned Reg) const
ArrayRef< std::pair< unsigned, unsigned > > liveins() const
unsigned cloneVirtualRegister(unsigned VReg, StringRef Name="")
Create and return a new virtual register in the function with the same attributes as the given regist...
iterator_range< use_bundle_nodbg_iterator > use_nodbg_bundles(unsigned Reg) const
void verifyUseList(unsigned Reg) const
Verify the sanity of the use list for Reg.
bool use_empty(unsigned RegNo) const
use_empty - Return true if there are no instructions using the specified register.
void dumpUses(unsigned RegNo) const
def_instr_iterator def_instr_begin(unsigned RegNo) const
defusechain_instr_iterator< true, true, true, false, false, true > reg_bundle_nodbg_iterator
reg_bundle_nodbg_iterator/reg_bundle_nodbg_begin/reg_bundle_nodbg_end - Walk all defs and uses of the...
void replaceRegWith(unsigned FromReg, unsigned ToReg)
replaceRegWith - Replace all instances of FromReg with ToReg in the machine function.
const BitVector & getReservedRegs() const
getReservedRegs - Returns a reference to the frozen set of reserved registers.
bool operator!=(const defusechain_instr_iterator &x) const
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
bool isLiveIn(unsigned Reg) const
Representation of each machine instruction.
Definition: MachineInstr.h:64
std::vector< std::pair< unsigned, unsigned > >::const_iterator livein_iterator
unsigned getOperandNo() const
getOperandNo - Return the operand # of this MachineOperand in its MachineInstr.
static reg_instr_nodbg_iterator reg_instr_nodbg_end()
static use_bundle_iterator use_bundle_end()
std::pair< unsigned, unsigned > getRegAllocationHint(unsigned VReg) const
getRegAllocationHint - Return the register allocation hint for the specified virtual register...
bool isUpdatedCSRsInitialized() const
Returns true if the updated CSR list was initialized and false otherwise.
bool hasOneUse(unsigned RegNo) const
hasOneUse - Return true if there is exactly one instruction using the specified register.
use_iterator use_begin(unsigned RegNo) const
Iterate over the pressure sets affected by the given physical or virtual register.
unsigned operator*() const
PSetIterator getPressureSets(unsigned RegUnit) const
Get an iterator over the pressure sets affected by the given physical or virtual register.
bool shouldTrackSubRegLiveness(unsigned VReg) const
virtual const int * getRegUnitPressureSets(unsigned RegUnit) const =0
Get the dimensions of register pressure impacted by this register unit.
void addPhysRegsUsedFromRegMask(const uint32_t *RegMask)
addPhysRegsUsedFromRegMask - Mark any registers not in RegMask as used.
defusechain_instr_iterator< true, false, true, false, true, false > use_instr_nodbg_iterator
use_instr_nodbg_iterator/use_instr_nodbg_begin/use_instr_nodbg_end - Walk all uses of the specified r...
bool tracksLiveness() const
tracksLiveness - Returns true when tracking register liveness accurately.
void markUsesInDebugValueAsUndef(unsigned Reg) const
markUsesInDebugValueAsUndef - Mark every DBG_VALUE referencing the specified register as undefined wh...
bool hasOneNonDBGUse(unsigned RegNo) const
hasOneNonDBGUse - Return true if there is exactly one non-Debug instruction using the specified regis...
void setSimpleHint(unsigned VReg, unsigned PrefReg)
Specify the preferred (target independent) register allocation hint for the specified virtual registe...
bool shouldTrackSubRegLiveness(const TargetRegisterClass &RC) const
Returns true if liveness for register class RC should be tracked at the subregister level...
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Instructions::iterator instr_iterator
static reg_nodbg_iterator reg_nodbg_end()
iterator_range< reg_instr_iterator > reg_instructions(unsigned Reg) const
iterator_range< use_instr_iterator > use_instructions(unsigned Reg) const
void grow(IndexT n)
Definition: IndexedMap.h:68
static use_instr_nodbg_iterator use_instr_nodbg_end()
const TargetRegisterClass * getRegClassOrNull(unsigned Reg) const
Return the register class of Reg, or null if Reg has not been assigned a register class yet...
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
bool hasProperty(Property P) const
static def_iterator def_end()
void addRegAllocationHint(unsigned VReg, unsigned PrefReg)
addRegAllocationHint - Add a register allocation hint to the hints vector for VReg.
use_instr_nodbg_iterator use_instr_nodbg_begin(unsigned RegNo) const
bool operator==(const defusechain_instr_iterator &x) const
MachineRegisterInfo(MachineFunction *MF)
reg_bundle_nodbg_iterator reg_bundle_nodbg_begin(unsigned RegNo) const
const std::pair< unsigned, SmallVector< unsigned, 4 > > & getRegAllocationHints(unsigned VReg) const
getRegAllocationHints - Return a reference to the vector of all register allocation hints for VReg...
void moveOperands(MachineOperand *Dst, MachineOperand *Src, unsigned NumOps)
Move NumOps operands from Src to Dst, updating use-def lists as needed.
static use_instr_iterator use_instr_end()
iterator_range< def_instr_iterator > def_instructions(unsigned Reg) const
const MCPhysReg * getCalleeSavedRegs() const
Returns list of callee saved registers.
bool reg_empty(unsigned RegNo) const
reg_empty - Return true if there are no instructions using or defining the specified register (it may...
def_bundle_iterator def_bundle_begin(unsigned RegNo) const
StringSet - A wrapper for StringMap that provides set-like functionality.
Definition: StringSet.h:28
void setRegClass(unsigned Reg, const TargetRegisterClass *RC)
setRegClass - Set the register class of the specified virtual register.
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:49
void setDelegate(Delegate *delegate)
virtual void MRI_NoteNewVirtualRegister(unsigned Reg)=0
bool operator==(uint64_t V1, const APInt &V2)
Definition: APInt.h:1961
unsigned getWeight() const
defusechain_instr_iterator< true, false, false, false, false, true > use_bundle_iterator
use_bundle_iterator/use_bundle_begin/use_bundle_end - Walk all uses of the specified register...
unsigned getSimpleHint(unsigned VReg) const
getSimpleHint - same as getRegAllocationHint except it will only return a target independent hint...
void setRegClassOrRegBank(unsigned Reg, const RegClassOrRegBank &RCOrRB)
static reg_iterator reg_end()
unsigned getLiveInVirtReg(unsigned PReg) const
getLiveInVirtReg - If PReg is a live-in physical register, return the corresponding live-in physical ...
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:414
iterator_range< use_instr_nodbg_iterator > use_nodbg_instructions(unsigned Reg) const
reg_begin/reg_end - Provide iteration support to walk over all definitions and uses of a register wit...
MachineRegisterInfo & operator=(const MachineRegisterInfo &)=delete
reg_instr_iterator reg_instr_begin(unsigned RegNo) const
static def_bundle_iterator def_bundle_end()
StringRef getVRegName(unsigned Reg) const
unsigned createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
std::iterator< std::forward_iterator_tag, MachineInstr, ptrdiff_t >::pointer pointer
bool isReserved(unsigned PhysReg) const
isReserved - Returns true when PhysReg is a reserved register.
A discriminated union of two pointer types, with the discriminator in the low bit of the pointer...
Definition: PointerUnion.h:87
void addRegOperandToUseList(MachineOperand *MO)
Add MO to the linked list of operands for its register.