13 #ifndef LLVM_CODEGEN_MACHINEREGISTERINFO_H 14 #define LLVM_CODEGEN_MACHINEREGISTERINFO_H 55 virtual void anchor();
68 const bool TracksSubRegLiveness;
87 bool IsUpdatedCSRsInitialized;
106 std::unique_ptr<MachineOperand *[]> PhysRegUseDefLists;
112 return VRegInfo[RegNo.
id()].second;
113 return PhysRegUseDefLists[RegNo.
id()];
118 return VRegInfo[RegNo.
id()].second;
119 return PhysRegUseDefLists[RegNo.
id()];
124 assert(MO && MO->
isReg() &&
"This is not a register operand!");
125 return MO->Contents.
Reg.Next;
146 std::vector<std::pair<unsigned, unsigned>> LiveIns;
161 assert(TheDelegate == delegate &&
162 "Only the current delegate can perform reset!");
163 TheDelegate =
nullptr;
167 assert(delegate && !TheDelegate &&
168 "Attempted to set delegate to null, or to change it without " 169 "first resetting it!");
171 TheDelegate = delegate;
222 return TracksSubRegLiveness;
264 template<
bool Uses,
bool Defs,
bool SkipDebug,
265 bool ByOperand,
bool ByInstr,
bool ByBundle>
267 template<
bool Uses,
bool Defs,
bool SkipDebug,
268 bool ByOperand,
bool ByInstr,
bool ByBundle>
272 template<
bool,
bool,
bool,
bool,
bool,
bool>
274 template<
bool,
bool,
bool,
bool,
bool,
bool>
434 "Named VRegs Must be Unique.");
438 VReg2Name[
Reg] = Name.
str();
609 void dumpUses(
unsigned RegNo)
const;
633 "Register class not set, wrong accessor");
666 return VRegInfo[
Reg].first;
677 VRegInfo[
Reg].first = RCOrRB;
693 unsigned MinNumRegs = 0);
707 unsigned MinNumRegs = 0);
731 return VRegToType[Reg];
764 RegAllocHints[VReg].first =
Type;
765 RegAllocHints[VReg].second.
clear();
766 RegAllocHints[VReg].second.push_back(PrefReg);
773 RegAllocHints[VReg].second.push_back(PrefReg);
784 "Expected to clear a non-target hint!");
785 RegAllocHints[VReg].second.
clear();
791 std::pair<unsigned, unsigned>
794 unsigned BestHint = (RegAllocHints[VReg.
id()].second.
size() ?
795 RegAllocHints[VReg.
id()].second[0] : 0);
796 return std::pair<unsigned, unsigned>(RegAllocHints[VReg.
id()].first,
805 return Hint.first ? 0 : Hint.second;
810 const std::pair<unsigned, SmallVector<unsigned, 4>>
813 return RegAllocHints[VReg];
828 MI->getOperand(0).setReg(Reg);
873 return !ReservedRegs.
empty();
888 "Reserved registers haven't been frozen yet. " 889 "Use TRI::getReservedRegs().");
927 LiveIns.push_back(std::make_pair(Reg, vreg));
968 template<
bool ReturnUses,
bool ReturnDefs,
bool SkipDebug,
969 bool ByOperand,
bool ByInstr,
bool ByBundle>
971 :
public std::iterator<std::forward_iterator_tag, MachineInstr, ptrdiff_t> {
980 if ((!ReturnUses && op->
isUse()) ||
981 (!ReturnDefs && op->
isDef()) ||
988 assert(Op &&
"Cannot increment end iterator!");
989 Op = getNextOperandForReg(Op);
1001 while (Op && ((!ReturnDefs && Op->
isDef()) ||
1002 (SkipDebug && Op->
isDebug())))
1003 Op = getNextOperandForReg(Op);
1008 using reference = std::iterator<std::forward_iterator_tag,
1010 using pointer = std::iterator<std::forward_iterator_tag,
1023 bool atEnd()
const {
return Op ==
nullptr; }
1027 assert(Op &&
"Cannot increment end iterator!");
1035 }
else if (ByBundle) {
1052 assert(Op &&
"Cannot dereference end iterator!");
1058 assert(Op &&
"Cannot dereference end iterator!");
1063 assert(Op &&
"Cannot dereference end iterator!");
1074 template<
bool ReturnUses,
bool ReturnDefs,
bool SkipDebug,
1075 bool ByOperand,
bool ByInstr,
bool ByBundle>
1077 :
public std::iterator<std::forward_iterator_tag, MachineInstr, ptrdiff_t> {
1086 if ((!ReturnUses && op->
isUse()) ||
1087 (!ReturnDefs && op->
isDef()) ||
1094 assert(Op &&
"Cannot increment end iterator!");
1095 Op = getNextOperandForReg(Op);
1107 while (Op && ((!ReturnDefs && Op->
isDef()) ||
1108 (SkipDebug && Op->
isDebug())))
1109 Op = getNextOperandForReg(Op);
1114 using reference = std::iterator<std::forward_iterator_tag,
1116 using pointer = std::iterator<std::forward_iterator_tag,
1129 bool atEnd()
const {
return Op ==
nullptr; }
1133 assert(Op &&
"Cannot increment end iterator!");
1141 }
else if (ByBundle) {
1157 assert(Op &&
"Cannot dereference end iterator!");
1171 const int *PSet =
nullptr;
1172 unsigned Weight = 0;
1199 assert(isValid() &&
"Invalid PSetIterator.");
1213 #endif // LLVM_CODEGEN_MACHINEREGISTERINFO_H bool operator!=(const defusechain_iterator &x) const
defusechain_instr_iterator< true, false, false, false, true, false > use_instr_iterator
use_instr_iterator/use_instr_begin/use_instr_end - Walk all uses of the specified register...
bool hasOneNonDBGUser(unsigned RegNo) const
hasOneNonDBGUse - Return true if there is exactly one non-Debug instruction using the specified regis...
defusechain_instr_iterator< true, true, false, false, true, false > reg_instr_iterator
reg_instr_iterator/reg_instr_begin/reg_instr_end - Walk all defs and uses of the specified register...
iterator_range< reg_instr_nodbg_iterator > reg_nodbg_instructions(unsigned Reg) const
A common definition of LaneBitmask for use in TableGen and CodeGen.
void EmitLiveInCopies(MachineBasicBlock *EntryMBB, const TargetRegisterInfo &TRI, const TargetInstrInfo &TII)
EmitLiveInCopies - Emit copies to initialize livein virtual registers into the given entry block...
defusechain_iterator< false, true, false, true, false, false > def_iterator
def_iterator/def_begin/def_end - Walk all defs of the specified register.
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
iterator_range< def_bundle_iterator > def_bundles(unsigned Reg) const
use_bundle_iterator use_bundle_begin(unsigned RegNo) const
bool use_nodbg_empty(unsigned RegNo) const
use_nodbg_empty - Return true if there are no non-Debug instructions using the specified register...
LLVM_NODISCARD std::string str() const
str - Get the contents as an std::string.
bool isReserved(Register PhysReg) const
isReserved - Returns true when PhysReg is a reserved register.
livein_iterator livein_begin() const
MachineInstr & operator*() const
bool livein_empty() const
StorageT::size_type size() const
void removeRegOperandFromUseList(MachineOperand *MO)
Remove MO from its use-def list.
bool isAllocatable(unsigned PhysReg) const
isAllocatable - Returns true when PhysReg belongs to an allocatable register class and it hasn't been...
void clearVirtRegTypes()
Remove all types associated to virtual registers (after instruction selection and constraining of all...
LaneBitmask getMaxLaneMaskForVReg(unsigned Reg) const
Returns a mask covering all bits that can appear in lane masks of subregisters of the virtual registe...
This class represents lattice values for constants.
MachineFunctionProperties & reset(Property P)
bool empty() const
empty - Tests whether there are no bits in this bitvector.
PointerUnion< const TargetRegisterClass *, const RegisterBank * > RegClassOrRegBank
Convenient type to represent either a register class or a register bank.
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
amdgpu Simplify well known AMD library false FunctionCallee Value const Twine & Name
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
void addLiveIn(unsigned Reg, unsigned vreg=0)
addLiveIn - Add the specified register as a live-in.
const MachineFunctionProperties & getProperties() const
Get the function properties.
bool isPhysRegModified(unsigned PhysReg, bool SkipNoReturnDef=false) const
Return true if the specified register is modified in this function.
This provides a very simple, boring adaptor for a begin and end iterator into a range type...
iterator_range< use_nodbg_iterator > use_nodbg_operands(unsigned Reg) const
iterator_range< use_bundle_iterator > use_bundles(unsigned Reg) const
iterator_range< reg_nodbg_iterator > reg_nodbg_operands(unsigned Reg) const
bool test(unsigned Idx) const
iterator_range< reg_iterator > reg_operands(unsigned Reg) const
iterator find(StringRef Key)
bool constrainRegAttrs(unsigned Reg, unsigned ConstrainingReg, unsigned MinNumRegs=0)
Constrain the register class or the register bank of the virtual register Reg (and low-level type) to...
void setBitsNotInMask(const uint32_t *Mask, unsigned MaskWords=~0u)
setBitsNotInMask - Add a bit to this vector for every '0' bit in Mask.
LLT getType(unsigned Reg) const
Get the low-level type of Reg or LLT{} if Reg is not a generic (target independent) virtual register...
virtual const int * getRegClassPressureSets(const TargetRegisterClass *RC) const =0
Get the dimensions of register pressure impacted by this register class.
unsigned const TargetRegisterInfo * TRI
bool hasOneDef(unsigned RegNo) const
Return true if there is exactly one operand defining the specified register.
defusechain_instr_iterator< false, true, false, false, false, true > def_bundle_iterator
def_bundle_iterator/def_bundle_begin/def_bundle_end - Walk all defs of the specified register...
void setRegBank(unsigned Reg, const RegisterBank &RegBank)
Set the register bank to RegBank for Reg.
iv Induction Variable Users
bool reservedRegsFrozen() const
reservedRegsFrozen - Returns true after freezeReservedRegs() was called to ensure the set of reserved...
bool shouldTrackSubRegLiveness(Register VReg) const
use_nodbg_iterator use_nodbg_begin(unsigned RegNo) const
void verifyUseLists() const
Verify the use list of all registers.
static use_nodbg_iterator use_nodbg_end()
defusechain_instr_iterator< true, false, true, false, false, true > use_bundle_nodbg_iterator
use_bundle_nodbg_iterator/use_bundle_nodbg_begin/use_bundle_nodbg_end - Walk all uses of the specifie...
void clearVirtRegs()
clearVirtRegs - Remove all virtual registers (after physreg assignment).
bool operator==(const defusechain_iterator &x) const
const TargetRegisterClass * getRegClass(Register Reg) const
Return the register class of the specified virtual register.
virtual unsigned getRegUnitWeight(unsigned RegUnit) const =0
Get the weight in units of pressure for this register unit.
std::iterator< std::forward_iterator_tag, MachineInstr, ptrdiff_t >::reference reference
T dyn_cast() const
Returns the current pointer if it is of the specified pointer type, otherwises returns null...
static use_iterator use_end()
iterator_range< reg_bundle_nodbg_iterator > reg_nodbg_bundles(unsigned Reg) const
reg_instr_nodbg_iterator reg_instr_nodbg_begin(unsigned RegNo) const
const HexagonInstrInfo * TII
defusechain_instr_iterator< true, true, true, false, true, false > reg_instr_nodbg_iterator
reg_instr_nodbg_iterator/reg_instr_nodbg_begin/reg_instr_nodbg_end - Walk all defs and uses of the sp...
void freezeReservedRegs(const MachineFunction &)
freezeReservedRegs - Called by the register allocator to freeze the set of reserved registers before ...
defusechain_instr_iterator< true, true, false, false, false, true > reg_bundle_iterator
reg_bundle_iterator/reg_bundle_begin/reg_bundle_end - Walk all defs and uses of the specified registe...
def_iterator def_begin(unsigned RegNo) const
LLVM_NODISCARD bool empty() const
empty - Check if the string is empty.
defusechain_iterator< true, true, true, true, false, false > reg_nodbg_iterator
reg_nodbg_iterator/reg_nodbg_begin/reg_nodbg_end - Walk all defs and uses of the specified register...
APInt operator*(APInt a, uint64_t RHS)
unsigned getLiveInPhysReg(unsigned VReg) const
getLiveInPhysReg - If VReg is a live-in virtual register, return the corresponding live-in physical r...
static reg_instr_iterator reg_instr_end()
MachineInstr * getVRegDef(unsigned Reg) const
getVRegDef - Return the machine instr that defines the specified virtual register or null if none is ...
defusechain_iterator - This class provides iterator support for machine operands in the function that...
void insertVRegByName(StringRef Name, unsigned Reg)
MachineBasicBlock::instr_iterator getBundleStart(MachineBasicBlock::instr_iterator I)
Returns an iterator to the first instruction in the bundle containing I.
defusechain_iterator< true, false, true, true, false, false > use_nodbg_iterator
use_nodbg_iterator/use_nodbg_begin/use_nodbg_end - Walk all uses of the specified register...
void clearKillFlags(unsigned Reg) const
clearKillFlags - Iterate over all the uses of the given register and clear the kill flag from the Mac...
const RegClassOrRegBank & getRegClassOrRegBank(unsigned Reg) const
Return the register bank or register class of Reg.
use_bundle_nodbg_iterator use_bundle_nodbg_begin(unsigned RegNo) const
iterator_range< def_iterator > def_operands(unsigned Reg) const
livein_iterator livein_end() const
static def_instr_iterator def_instr_end()
PSetIterator(unsigned RegUnit, const MachineRegisterInfo *MRI)
bool canReserveReg(unsigned PhysReg) const
canReserveReg - Returns true if PhysReg can be used as a reserved register.
defusechain_instr_iterator< false, true, false, false, true, false > def_instr_iterator
def_instr_iterator/def_instr_begin/def_instr_end - Walk all defs of the specified register...
bool isVirtual() const
Return true if the specified register number is in the virtual register namespace.
friend class defusechain_iterator
defusechain_iterator & operator++()
std::iterator< std::forward_iterator_tag, MachineInstr, ptrdiff_t >::pointer pointer
void disableCalleeSavedRegister(unsigned Reg)
Disables the register from the list of CSRs.
bool inBounds(IndexT n) const
const TargetRegisterClass * constrainRegClass(unsigned Reg, const TargetRegisterClass *RC, unsigned MinNumRegs=0)
constrainRegClass - Constrain the register class of the specified virtual register to be a common sub...
defusechain_instr_iterator & operator++()
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
TargetInstrInfo - Interface to description of machine instruction set.
bool subRegLivenessEnabled() const
reg_bundle_iterator reg_bundle_begin(unsigned RegNo) const
const TargetRegisterInfo * getTargetRegisterInfo() const
unsigned const MachineRegisterInfo * MRI
bool isCallerPreservedOrConstPhysReg(unsigned PhysReg) const
Returns true if either isConstantPhysReg or TRI->isCallerPreservedPhysReg returns true...
The instances of the Type class are immutable: once they are created, they are never changed...
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineOperand * operator->() const
void setType(unsigned VReg, LLT Ty)
Set the low-level type of VReg to Ty.
use_instr_iterator use_instr_begin(unsigned RegNo) const
defusechain_iterator< true, false, false, true, false, false > use_iterator
use_iterator/use_begin/use_end - Walk all uses of the specified register.
bool reg_nodbg_empty(Register RegNo) const
reg_nodbg_empty - Return true if the only instructions using or defining Reg are Debug instructions...
friend class defusechain_instr_iterator
bool def_empty(unsigned RegNo) const
def_empty - Return true if there are no instructions defining the specified register (it may be live-...
bool atEnd() const
atEnd - return true if this iterator is equal to reg_end() on the value.
const RegisterBank * getRegBankOrNull(unsigned Reg) const
Return the register bank of Reg, or null if Reg has not been assigned a register bank or has been ass...
self_iterator getIterator()
void setCalleeSavedRegs(ArrayRef< MCPhysReg > CSRs)
Sets the updated Callee Saved Registers list.
virtual ~Delegate()=default
unsigned getNumVirtRegs() const
getNumVirtRegs - Return the number of virtual registers created.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
std::iterator< std::forward_iterator_tag, MachineInstr, ptrdiff_t >::reference reference
std::pair< typename base::iterator, bool > insert(StringRef Key)
bool isConstantPhysReg(unsigned PhysReg) const
Returns true if PhysReg is unallocatable and constant throughout the function.
const bool HasDisjunctSubRegs
Whether the class supports two (or more) disjunct subregister indices.
MachineInstr * operator->() const
struct llvm::MachineOperand::@173::@175 Reg
iterator_range< T > make_range(T x, T y)
Convenience function for iterating over sub-ranges.
static use_bundle_nodbg_iterator use_bundle_nodbg_end()
unsigned createIncompleteVirtualRegister(StringRef Name="")
Creates a new virtual register that has no register class, register bank or size assigned yet...
defusechain_iterator< true, true, false, true, false, false > reg_iterator
reg_iterator/reg_begin/reg_end - Walk all defs and uses of the specified register.
std::pair< unsigned, unsigned > getRegAllocationHint(Register VReg) const
getRegAllocationHint - Return the register allocation hint for the specified virtual register...
iterator_range< use_iterator > use_operands(unsigned Reg) const
MachineOperand class - Representation of each machine instruction operand.
virtual const RegClassWeight & getRegClassWeight(const TargetRegisterClass *RC) const =0
Get the weight in units of pressure for this register class.
void setRegAllocationHint(unsigned VReg, unsigned Type, unsigned PrefReg)
setRegAllocationHint - Specify a register allocation hint for the specified virtual register...
bool isInAllocatableClass(unsigned RegNo) const
Return true if the register is in the allocation of any register class.
bool atEnd() const
atEnd - return true if this iterator is equal to reg_end() on the value.
static reg_bundle_iterator reg_bundle_end()
bool isReservedRegUnit(unsigned Unit) const
Returns true when the given register unit is considered reserved.
reg_iterator reg_begin(unsigned RegNo) const
void clearSimpleHint(unsigned VReg)
Register cloneVirtualRegister(Register VReg, StringRef Name="")
Create and return a new virtual register in the function with the same attributes as the given regist...
void invalidateLiveness()
invalidateLiveness - Indicates that register liveness is no longer being tracked accurately.
This class implements the register bank concept.
const BitVector & getUsedPhysRegsMask() const
bool recomputeRegClass(unsigned Reg)
recomputeRegClass - Try to find a legal super-class of Reg's register class that still satisfies the ...
void resetDelegate(Delegate *delegate)
MachineInstr * getUniqueVRegDef(unsigned Reg) const
getUniqueVRegDef - Return the unique machine instr that defines the specified virtual register or nul...
static reg_bundle_nodbg_iterator reg_bundle_nodbg_end()
bool isPhysRegUsed(unsigned PhysReg) const
Return true if the specified register is modified or read in this function.
A range adaptor for a pair of iterators.
iterator_range< reg_bundle_iterator > reg_bundles(unsigned Reg) const
ArrayRef< std::pair< unsigned, unsigned > > liveins() const
iterator_range< use_bundle_nodbg_iterator > use_nodbg_bundles(unsigned Reg) const
void verifyUseList(unsigned Reg) const
Verify the sanity of the use list for Reg.
bool use_empty(unsigned RegNo) const
use_empty - Return true if there are no instructions using the specified register.
void dumpUses(unsigned RegNo) const
def_instr_iterator def_instr_begin(unsigned RegNo) const
defusechain_instr_iterator< true, true, true, false, false, true > reg_bundle_nodbg_iterator
reg_bundle_nodbg_iterator/reg_bundle_nodbg_begin/reg_bundle_nodbg_end - Walk all defs and uses of the...
void replaceRegWith(unsigned FromReg, unsigned ToReg)
replaceRegWith - Replace all instances of FromReg with ToReg in the machine function.
const BitVector & getReservedRegs() const
getReservedRegs - Returns a reference to the frozen set of reserved registers.
bool operator!=(const defusechain_instr_iterator &x) const
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
bool isLiveIn(unsigned Reg) const
Representation of each machine instruction.
std::vector< std::pair< unsigned, unsigned > >::const_iterator livein_iterator
unsigned getOperandNo() const
getOperandNo - Return the operand # of this MachineOperand in its MachineInstr.
static reg_instr_nodbg_iterator reg_instr_nodbg_end()
static use_bundle_iterator use_bundle_end()
bool isUpdatedCSRsInitialized() const
Returns true if the updated CSR list was initialized and false otherwise.
void updateDbgUsersToReg(unsigned Reg, ArrayRef< MachineInstr *> Users) const
updateDbgUsersToReg - Update a collection of DBG_VALUE instructions to refer to the designated regist...
reg_nodbg_iterator reg_nodbg_begin(Register RegNo) const
bool hasOneUse(unsigned RegNo) const
hasOneUse - Return true if there is exactly one instruction using the specified register.
use_iterator use_begin(unsigned RegNo) const
Iterate over the pressure sets affected by the given physical or virtual register.
unsigned operator*() const
PSetIterator getPressureSets(unsigned RegUnit) const
Get an iterator over the pressure sets affected by the given physical or virtual register.
virtual const int * getRegUnitPressureSets(unsigned RegUnit) const =0
Get the dimensions of register pressure impacted by this register unit.
void addPhysRegsUsedFromRegMask(const uint32_t *RegMask)
addPhysRegsUsedFromRegMask - Mark any registers not in RegMask as used.
defusechain_instr_iterator< true, false, true, false, true, false > use_instr_nodbg_iterator
use_instr_nodbg_iterator/use_instr_nodbg_begin/use_instr_nodbg_end - Walk all uses of the specified r...
bool tracksLiveness() const
tracksLiveness - Returns true when tracking register liveness accurately.
void markUsesInDebugValueAsUndef(unsigned Reg) const
markUsesInDebugValueAsUndef - Mark every DBG_VALUE referencing the specified register as undefined wh...
bool hasOneNonDBGUse(unsigned RegNo) const
hasOneNonDBGUse - Return true if there is exactly one non-Debug use of the specified register...
void setSimpleHint(unsigned VReg, unsigned PrefReg)
Specify the preferred (target independent) register allocation hint for the specified virtual registe...
bool shouldTrackSubRegLiveness(const TargetRegisterClass &RC) const
Returns true if liveness for register class RC should be tracked at the subregister level...
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Instructions::iterator instr_iterator
static reg_nodbg_iterator reg_nodbg_end()
iterator_range< reg_instr_iterator > reg_instructions(unsigned Reg) const
iterator_range< use_instr_iterator > use_instructions(unsigned Reg) const
MachineOperand & operator*() const
static use_instr_nodbg_iterator use_instr_nodbg_end()
const TargetRegisterClass * getRegClassOrNull(unsigned Reg) const
Return the register class of Reg, or null if Reg has not been assigned a register class yet...
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
bool hasProperty(Property P) const
static def_iterator def_end()
void addRegAllocationHint(unsigned VReg, unsigned PrefReg)
addRegAllocationHint - Add a register allocation hint to the hints vector for VReg.
use_instr_nodbg_iterator use_instr_nodbg_begin(unsigned RegNo) const
bool operator==(const defusechain_instr_iterator &x) const
MachineRegisterInfo(MachineFunction *MF)
reg_bundle_nodbg_iterator reg_bundle_nodbg_begin(unsigned RegNo) const
const std::pair< unsigned, SmallVector< unsigned, 4 > > & getRegAllocationHints(unsigned VReg) const
getRegAllocationHints - Return a reference to the vector of all register allocation hints for VReg...
void moveOperands(MachineOperand *Dst, MachineOperand *Src, unsigned NumOps)
Move NumOps operands from Src to Dst, updating use-def lists as needed.
static use_instr_iterator use_instr_end()
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
iterator_range< def_instr_iterator > def_instructions(unsigned Reg) const
const MCPhysReg * getCalleeSavedRegs() const
Returns list of callee saved registers.
bool reg_empty(unsigned RegNo) const
reg_empty - Return true if there are no instructions using or defining the specified register (it may...
def_bundle_iterator def_bundle_begin(unsigned RegNo) const
StringSet - A wrapper for StringMap that provides set-like functionality.
defusechain_instr_iterator operator++(int)
void setRegClass(unsigned Reg, const TargetRegisterClass *RC)
setRegClass - Set the register class of the specified virtual register.
StringRef - Represent a constant reference to a string, i.e.
void setDelegate(Delegate *delegate)
virtual void MRI_NoteNewVirtualRegister(unsigned Reg)=0
Register createGenericVirtualRegister(LLT Ty, StringRef Name="")
Create and return a new generic virtual register with low-level type Ty.
bool operator==(uint64_t V1, const APInt &V2)
unsigned getWeight() const
defusechain_instr_iterator< true, false, false, false, false, true > use_bundle_iterator
use_bundle_iterator/use_bundle_begin/use_bundle_end - Walk all uses of the specified register...
void setRegClassOrRegBank(unsigned Reg, const RegClassOrRegBank &RCOrRB)
static reg_iterator reg_end()
unsigned getLiveInVirtReg(unsigned PReg) const
getLiveInVirtReg - If PReg is a live-in physical register, return the corresponding live-in physical ...
const MachineOperand & getOperand(unsigned i) const
Register getSimpleHint(Register VReg) const
getSimpleHint - same as getRegAllocationHint except it will only return a target independent hint...
iterator_range< use_instr_nodbg_iterator > use_nodbg_instructions(unsigned Reg) const
reg_begin/reg_end - Provide iteration support to walk over all definitions and uses of a register wit...
MachineRegisterInfo & operator=(const MachineRegisterInfo &)=delete
reg_instr_iterator reg_instr_begin(unsigned RegNo) const
static def_bundle_iterator def_bundle_end()
StringRef getVRegName(unsigned Reg) const
std::iterator< std::forward_iterator_tag, MachineInstr, ptrdiff_t >::pointer pointer
Wrapper class representing virtual and physical registers.
A discriminated union of two or more pointer types, with the discriminator in the low bit of the poin...
defusechain_iterator operator++(int)
void addRegOperandToUseList(MachineOperand *MO)
Add MO to the linked list of operands for its register.