LLVM  9.0.0svn
TargetInstrInfo.h
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1 //===- llvm/CodeGen/TargetInstrInfo.h - Instruction Info --------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file describes the target machine instruction set to the code generator.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_TARGET_TARGETINSTRINFO_H
14 #define LLVM_TARGET_TARGETINSTRINFO_H
15 
16 #include "llvm/ADT/ArrayRef.h"
17 #include "llvm/ADT/DenseMap.h"
18 #include "llvm/ADT/DenseMapInfo.h"
19 #include "llvm/ADT/None.h"
30 #include "llvm/MC/MCInstrInfo.h"
33 #include <cassert>
34 #include <cstddef>
35 #include <cstdint>
36 #include <utility>
37 #include <vector>
38 
39 namespace llvm {
40 
41 class DFAPacketizer;
42 class InstrItineraryData;
43 class LiveIntervals;
44 class LiveVariables;
45 class MachineMemOperand;
46 class MachineRegisterInfo;
47 class MCAsmInfo;
48 class MCInst;
49 struct MCSchedModel;
50 class Module;
51 class ScheduleDAG;
52 class ScheduleHazardRecognizer;
53 class SDNode;
54 class SelectionDAG;
55 class RegScavenger;
56 class TargetRegisterClass;
57 class TargetRegisterInfo;
58 class TargetSchedModel;
59 class TargetSubtargetInfo;
60 
61 template <class T> class SmallVectorImpl;
62 
63 //---------------------------------------------------------------------------
64 ///
65 /// TargetInstrInfo - Interface to description of machine instruction set
66 ///
67 class TargetInstrInfo : public MCInstrInfo {
68 public:
69  TargetInstrInfo(unsigned CFSetupOpcode = ~0u, unsigned CFDestroyOpcode = ~0u,
70  unsigned CatchRetOpcode = ~0u, unsigned ReturnOpcode = ~0u)
71  : CallFrameSetupOpcode(CFSetupOpcode),
72  CallFrameDestroyOpcode(CFDestroyOpcode), CatchRetOpcode(CatchRetOpcode),
73  ReturnOpcode(ReturnOpcode) {}
74  TargetInstrInfo(const TargetInstrInfo &) = delete;
75  TargetInstrInfo &operator=(const TargetInstrInfo &) = delete;
76  virtual ~TargetInstrInfo();
77 
78  static bool isGenericOpcode(unsigned Opc) {
79  return Opc <= TargetOpcode::GENERIC_OP_END;
80  }
81 
82  /// Given a machine instruction descriptor, returns the register
83  /// class constraint for OpNum, or NULL.
84  const TargetRegisterClass *getRegClass(const MCInstrDesc &MCID, unsigned OpNum,
85  const TargetRegisterInfo *TRI,
86  const MachineFunction &MF) const;
87 
88  /// Return true if the instruction is trivially rematerializable, meaning it
89  /// has no side effects and requires no operands that aren't always available.
90  /// This means the only allowed uses are constants and unallocatable physical
91  /// registers so that the instructions result is independent of the place
92  /// in the function.
94  AliasAnalysis *AA = nullptr) const {
95  return MI.getOpcode() == TargetOpcode::IMPLICIT_DEF ||
96  (MI.getDesc().isRematerializable() &&
98  isReallyTriviallyReMaterializableGeneric(MI, AA)));
99  }
100 
101 protected:
102  /// For instructions with opcodes for which the M_REMATERIALIZABLE flag is
103  /// set, this hook lets the target specify whether the instruction is actually
104  /// trivially rematerializable, taking into consideration its operands. This
105  /// predicate must return false if the instruction has any side effects other
106  /// than producing a value, or if it requres any address registers that are
107  /// not always available.
108  /// Requirements must be check as stated in isTriviallyReMaterializable() .
110  AliasAnalysis *AA) const {
111  return false;
112  }
113 
114  /// This method commutes the operands of the given machine instruction MI.
115  /// The operands to be commuted are specified by their indices OpIdx1 and
116  /// OpIdx2.
117  ///
118  /// If a target has any instructions that are commutable but require
119  /// converting to different instructions or making non-trivial changes
120  /// to commute them, this method can be overloaded to do that.
121  /// The default implementation simply swaps the commutable operands.
122  ///
123  /// If NewMI is false, MI is modified in place and returned; otherwise, a
124  /// new machine instruction is created and returned.
125  ///
126  /// Do not call this method for a non-commutable instruction.
127  /// Even though the instruction is commutable, the method may still
128  /// fail to commute the operands, null pointer is returned in such cases.
129  virtual MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI,
130  unsigned OpIdx1,
131  unsigned OpIdx2) const;
132 
133  /// Assigns the (CommutableOpIdx1, CommutableOpIdx2) pair of commutable
134  /// operand indices to (ResultIdx1, ResultIdx2).
135  /// One or both input values of the pair: (ResultIdx1, ResultIdx2) may be
136  /// predefined to some indices or be undefined (designated by the special
137  /// value 'CommuteAnyOperandIndex').
138  /// The predefined result indices cannot be re-defined.
139  /// The function returns true iff after the result pair redefinition
140  /// the fixed result pair is equal to or equivalent to the source pair of
141  /// indices: (CommutableOpIdx1, CommutableOpIdx2). It is assumed here that
142  /// the pairs (x,y) and (y,x) are equivalent.
143  static bool fixCommutedOpIndices(unsigned &ResultIdx1, unsigned &ResultIdx2,
144  unsigned CommutableOpIdx1,
145  unsigned CommutableOpIdx2);
146 
147 private:
148  /// For instructions with opcodes for which the M_REMATERIALIZABLE flag is
149  /// set and the target hook isReallyTriviallyReMaterializable returns false,
150  /// this function does target-independent tests to determine if the
151  /// instruction is really trivially rematerializable.
152  bool isReallyTriviallyReMaterializableGeneric(const MachineInstr &MI,
153  AliasAnalysis *AA) const;
154 
155 public:
156  /// These methods return the opcode of the frame setup/destroy instructions
157  /// if they exist (-1 otherwise). Some targets use pseudo instructions in
158  /// order to abstract away the difference between operating with a frame
159  /// pointer and operating without, through the use of these two instructions.
160  ///
161  unsigned getCallFrameSetupOpcode() const { return CallFrameSetupOpcode; }
162  unsigned getCallFrameDestroyOpcode() const { return CallFrameDestroyOpcode; }
163 
164  /// Returns true if the argument is a frame pseudo instruction.
165  bool isFrameInstr(const MachineInstr &I) const {
166  return I.getOpcode() == getCallFrameSetupOpcode() ||
168  }
169 
170  /// Returns true if the argument is a frame setup pseudo instruction.
171  bool isFrameSetup(const MachineInstr &I) const {
172  return I.getOpcode() == getCallFrameSetupOpcode();
173  }
174 
175  /// Returns size of the frame associated with the given frame instruction.
176  /// For frame setup instruction this is frame that is set up space set up
177  /// after the instruction. For frame destroy instruction this is the frame
178  /// freed by the caller.
179  /// Note, in some cases a call frame (or a part of it) may be prepared prior
180  /// to the frame setup instruction. It occurs in the calls that involve
181  /// inalloca arguments. This function reports only the size of the frame part
182  /// that is set up between the frame setup and destroy pseudo instructions.
183  int64_t getFrameSize(const MachineInstr &I) const {
184  assert(isFrameInstr(I) && "Not a frame instruction");
185  assert(I.getOperand(0).getImm() >= 0);
186  return I.getOperand(0).getImm();
187  }
188 
189  /// Returns the total frame size, which is made up of the space set up inside
190  /// the pair of frame start-stop instructions and the space that is set up
191  /// prior to the pair.
192  int64_t getFrameTotalSize(const MachineInstr &I) const {
193  if (isFrameSetup(I)) {
194  assert(I.getOperand(1).getImm() >= 0 &&
195  "Frame size must not be negative");
196  return getFrameSize(I) + I.getOperand(1).getImm();
197  }
198  return getFrameSize(I);
199  }
200 
201  unsigned getCatchReturnOpcode() const { return CatchRetOpcode; }
202  unsigned getReturnOpcode() const { return ReturnOpcode; }
203 
204  /// Returns the actual stack pointer adjustment made by an instruction
205  /// as part of a call sequence. By default, only call frame setup/destroy
206  /// instructions adjust the stack, but targets may want to override this
207  /// to enable more fine-grained adjustment, or adjust by a different value.
208  virtual int getSPAdjust(const MachineInstr &MI) const;
209 
210  /// Return true if the instruction is a "coalescable" extension instruction.
211  /// That is, it's like a copy where it's legal for the source to overlap the
212  /// destination. e.g. X86::MOVSX64rr32. If this returns true, then it's
213  /// expected the pre-extension value is available as a subreg of the result
214  /// register. This also returns the sub-register index in SubIdx.
215  virtual bool isCoalescableExtInstr(const MachineInstr &MI, unsigned &SrcReg,
216  unsigned &DstReg, unsigned &SubIdx) const {
217  return false;
218  }
219 
220  /// If the specified machine instruction is a direct
221  /// load from a stack slot, return the virtual or physical register number of
222  /// the destination along with the FrameIndex of the loaded stack slot. If
223  /// not, return 0. This predicate must return 0 if the instruction has
224  /// any side effects other than loading from the stack slot.
225  virtual unsigned isLoadFromStackSlot(const MachineInstr &MI,
226  int &FrameIndex) const {
227  return 0;
228  }
229 
230  /// Optional extension of isLoadFromStackSlot that returns the number of
231  /// bytes loaded from the stack. This must be implemented if a backend
232  /// supports partial stack slot spills/loads to further disambiguate
233  /// what the load does.
234  virtual unsigned isLoadFromStackSlot(const MachineInstr &MI,
235  int &FrameIndex,
236  unsigned &MemBytes) const {
237  MemBytes = 0;
238  return isLoadFromStackSlot(MI, FrameIndex);
239  }
240 
241  /// Check for post-frame ptr elimination stack locations as well.
242  /// This uses a heuristic so it isn't reliable for correctness.
243  virtual unsigned isLoadFromStackSlotPostFE(const MachineInstr &MI,
244  int &FrameIndex) const {
245  return 0;
246  }
247 
248  /// If the specified machine instruction has a load from a stack slot,
249  /// return true along with the FrameIndices of the loaded stack slot and the
250  /// machine mem operands containing the reference.
251  /// If not, return false. Unlike isLoadFromStackSlot, this returns true for
252  /// any instructions that loads from the stack. This is just a hint, as some
253  /// cases may be missed.
254  virtual bool hasLoadFromStackSlot(
255  const MachineInstr &MI,
257 
258  /// If the specified machine instruction is a direct
259  /// store to a stack slot, return the virtual or physical register number of
260  /// the source reg along with the FrameIndex of the loaded stack slot. If
261  /// not, return 0. This predicate must return 0 if the instruction has
262  /// any side effects other than storing to the stack slot.
263  virtual unsigned isStoreToStackSlot(const MachineInstr &MI,
264  int &FrameIndex) const {
265  return 0;
266  }
267 
268  /// Optional extension of isStoreToStackSlot that returns the number of
269  /// bytes stored to the stack. This must be implemented if a backend
270  /// supports partial stack slot spills/loads to further disambiguate
271  /// what the store does.
272  virtual unsigned isStoreToStackSlot(const MachineInstr &MI,
273  int &FrameIndex,
274  unsigned &MemBytes) const {
275  MemBytes = 0;
276  return isStoreToStackSlot(MI, FrameIndex);
277  }
278 
279  /// Check for post-frame ptr elimination stack locations as well.
280  /// This uses a heuristic, so it isn't reliable for correctness.
281  virtual unsigned isStoreToStackSlotPostFE(const MachineInstr &MI,
282  int &FrameIndex) const {
283  return 0;
284  }
285 
286  /// If the specified machine instruction has a store to a stack slot,
287  /// return true along with the FrameIndices of the loaded stack slot and the
288  /// machine mem operands containing the reference.
289  /// If not, return false. Unlike isStoreToStackSlot,
290  /// this returns true for any instructions that stores to the
291  /// stack. This is just a hint, as some cases may be missed.
292  virtual bool hasStoreToStackSlot(
293  const MachineInstr &MI,
295 
296  /// Return true if the specified machine instruction
297  /// is a copy of one stack slot to another and has no other effect.
298  /// Provide the identity of the two frame indices.
299  virtual bool isStackSlotCopy(const MachineInstr &MI, int &DestFrameIndex,
300  int &SrcFrameIndex) const {
301  return false;
302  }
303 
304  /// Compute the size in bytes and offset within a stack slot of a spilled
305  /// register or subregister.
306  ///
307  /// \param [out] Size in bytes of the spilled value.
308  /// \param [out] Offset in bytes within the stack slot.
309  /// \returns true if both Size and Offset are successfully computed.
310  ///
311  /// Not all subregisters have computable spill slots. For example,
312  /// subregisters registers may not be byte-sized, and a pair of discontiguous
313  /// subregisters has no single offset.
314  ///
315  /// Targets with nontrivial bigendian implementations may need to override
316  /// this, particularly to support spilled vector registers.
317  virtual bool getStackSlotRange(const TargetRegisterClass *RC, unsigned SubIdx,
318  unsigned &Size, unsigned &Offset,
319  const MachineFunction &MF) const;
320 
321  /// Returns the size in bytes of the specified MachineInstr, or ~0U
322  /// when this function is not implemented by a target.
323  virtual unsigned getInstSizeInBytes(const MachineInstr &MI) const {
324  return ~0U;
325  }
326 
327  /// Return true if the instruction is as cheap as a move instruction.
328  ///
329  /// Targets for different archs need to override this, and different
330  /// micro-architectures can also be finely tuned inside.
331  virtual bool isAsCheapAsAMove(const MachineInstr &MI) const {
332  return MI.isAsCheapAsAMove();
333  }
334 
335  /// Return true if the instruction should be sunk by MachineSink.
336  ///
337  /// MachineSink determines on its own whether the instruction is safe to sink;
338  /// this gives the target a hook to override the default behavior with regards
339  /// to which instructions should be sunk.
340  virtual bool shouldSink(const MachineInstr &MI) const { return true; }
341 
342  /// Re-issue the specified 'original' instruction at the
343  /// specific location targeting a new destination register.
344  /// The register in Orig->getOperand(0).getReg() will be substituted by
345  /// DestReg:SubIdx. Any existing subreg index is preserved or composed with
346  /// SubIdx.
347  virtual void reMaterialize(MachineBasicBlock &MBB,
348  MachineBasicBlock::iterator MI, unsigned DestReg,
349  unsigned SubIdx, const MachineInstr &Orig,
350  const TargetRegisterInfo &TRI) const;
351 
352  /// Clones instruction or the whole instruction bundle \p Orig and
353  /// insert into \p MBB before \p InsertBefore. The target may update operands
354  /// that are required to be unique.
355  ///
356  /// \p Orig must not return true for MachineInstr::isNotDuplicable().
358  MachineBasicBlock::iterator InsertBefore,
359  const MachineInstr &Orig) const;
360 
361  /// This method must be implemented by targets that
362  /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
363  /// may be able to convert a two-address instruction into one or more true
364  /// three-address instructions on demand. This allows the X86 target (for
365  /// example) to convert ADD and SHL instructions into LEA instructions if they
366  /// would require register copies due to two-addressness.
367  ///
368  /// This method returns a null pointer if the transformation cannot be
369  /// performed, otherwise it returns the last new instruction.
370  ///
372  MachineInstr &MI,
373  LiveVariables *LV) const {
374  return nullptr;
375  }
376 
377  // This constant can be used as an input value of operand index passed to
378  // the method findCommutedOpIndices() to tell the method that the
379  // corresponding operand index is not pre-defined and that the method
380  // can pick any commutable operand.
381  static const unsigned CommuteAnyOperandIndex = ~0U;
382 
383  /// This method commutes the operands of the given machine instruction MI.
384  ///
385  /// The operands to be commuted are specified by their indices OpIdx1 and
386  /// OpIdx2. OpIdx1 and OpIdx2 arguments may be set to a special value
387  /// 'CommuteAnyOperandIndex', which means that the method is free to choose
388  /// any arbitrarily chosen commutable operand. If both arguments are set to
389  /// 'CommuteAnyOperandIndex' then the method looks for 2 different commutable
390  /// operands; then commutes them if such operands could be found.
391  ///
392  /// If NewMI is false, MI is modified in place and returned; otherwise, a
393  /// new machine instruction is created and returned.
394  ///
395  /// Do not call this method for a non-commutable instruction or
396  /// for non-commuable operands.
397  /// Even though the instruction is commutable, the method may still
398  /// fail to commute the operands, null pointer is returned in such cases.
399  MachineInstr *
400  commuteInstruction(MachineInstr &MI, bool NewMI = false,
401  unsigned OpIdx1 = CommuteAnyOperandIndex,
402  unsigned OpIdx2 = CommuteAnyOperandIndex) const;
403 
404  /// Returns true iff the routine could find two commutable operands in the
405  /// given machine instruction.
406  /// The 'SrcOpIdx1' and 'SrcOpIdx2' are INPUT and OUTPUT arguments.
407  /// If any of the INPUT values is set to the special value
408  /// 'CommuteAnyOperandIndex' then the method arbitrarily picks a commutable
409  /// operand, then returns its index in the corresponding argument.
410  /// If both of INPUT values are set to 'CommuteAnyOperandIndex' then method
411  /// looks for 2 commutable operands.
412  /// If INPUT values refer to some operands of MI, then the method simply
413  /// returns true if the corresponding operands are commutable and returns
414  /// false otherwise.
415  ///
416  /// For example, calling this method this way:
417  /// unsigned Op1 = 1, Op2 = CommuteAnyOperandIndex;
418  /// findCommutedOpIndices(MI, Op1, Op2);
419  /// can be interpreted as a query asking to find an operand that would be
420  /// commutable with the operand#1.
421  virtual bool findCommutedOpIndices(MachineInstr &MI, unsigned &SrcOpIdx1,
422  unsigned &SrcOpIdx2) const;
423 
424  /// A pair composed of a register and a sub-register index.
425  /// Used to give some type checking when modeling Reg:SubReg.
426  struct RegSubRegPair {
427  unsigned Reg;
428  unsigned SubReg;
429 
430  RegSubRegPair(unsigned Reg = 0, unsigned SubReg = 0)
431  : Reg(Reg), SubReg(SubReg) {}
432 
433  bool operator==(const RegSubRegPair& P) const {
434  return Reg == P.Reg && SubReg == P.SubReg;
435  }
436  bool operator!=(const RegSubRegPair& P) const {
437  return !(*this == P);
438  }
439  };
440 
441  /// A pair composed of a pair of a register and a sub-register index,
442  /// and another sub-register index.
443  /// Used to give some type checking when modeling Reg:SubReg1, SubReg2.
445  unsigned SubIdx;
446 
447  RegSubRegPairAndIdx(unsigned Reg = 0, unsigned SubReg = 0,
448  unsigned SubIdx = 0)
449  : RegSubRegPair(Reg, SubReg), SubIdx(SubIdx) {}
450  };
451 
452  /// Build the equivalent inputs of a REG_SEQUENCE for the given \p MI
453  /// and \p DefIdx.
454  /// \p [out] InputRegs of the equivalent REG_SEQUENCE. Each element of
455  /// the list is modeled as <Reg:SubReg, SubIdx>. Operands with the undef
456  /// flag are not added to this list.
457  /// E.g., REG_SEQUENCE %1:sub1, sub0, %2, sub1 would produce
458  /// two elements:
459  /// - %1:sub1, sub0
460  /// - %2<:0>, sub1
461  ///
462  /// \returns true if it is possible to build such an input sequence
463  /// with the pair \p MI, \p DefIdx. False otherwise.
464  ///
465  /// \pre MI.isRegSequence() or MI.isRegSequenceLike().
466  ///
467  /// \note The generic implementation does not provide any support for
468  /// MI.isRegSequenceLike(). In other words, one has to override
469  /// getRegSequenceLikeInputs for target specific instructions.
470  bool
471  getRegSequenceInputs(const MachineInstr &MI, unsigned DefIdx,
472  SmallVectorImpl<RegSubRegPairAndIdx> &InputRegs) const;
473 
474  /// Build the equivalent inputs of a EXTRACT_SUBREG for the given \p MI
475  /// and \p DefIdx.
476  /// \p [out] InputReg of the equivalent EXTRACT_SUBREG.
477  /// E.g., EXTRACT_SUBREG %1:sub1, sub0, sub1 would produce:
478  /// - %1:sub1, sub0
479  ///
480  /// \returns true if it is possible to build such an input sequence
481  /// with the pair \p MI, \p DefIdx and the operand has no undef flag set.
482  /// False otherwise.
483  ///
484  /// \pre MI.isExtractSubreg() or MI.isExtractSubregLike().
485  ///
486  /// \note The generic implementation does not provide any support for
487  /// MI.isExtractSubregLike(). In other words, one has to override
488  /// getExtractSubregLikeInputs for target specific instructions.
489  bool getExtractSubregInputs(const MachineInstr &MI, unsigned DefIdx,
490  RegSubRegPairAndIdx &InputReg) const;
491 
492  /// Build the equivalent inputs of a INSERT_SUBREG for the given \p MI
493  /// and \p DefIdx.
494  /// \p [out] BaseReg and \p [out] InsertedReg contain
495  /// the equivalent inputs of INSERT_SUBREG.
496  /// E.g., INSERT_SUBREG %0:sub0, %1:sub1, sub3 would produce:
497  /// - BaseReg: %0:sub0
498  /// - InsertedReg: %1:sub1, sub3
499  ///
500  /// \returns true if it is possible to build such an input sequence
501  /// with the pair \p MI, \p DefIdx and the operand has no undef flag set.
502  /// False otherwise.
503  ///
504  /// \pre MI.isInsertSubreg() or MI.isInsertSubregLike().
505  ///
506  /// \note The generic implementation does not provide any support for
507  /// MI.isInsertSubregLike(). In other words, one has to override
508  /// getInsertSubregLikeInputs for target specific instructions.
509  bool getInsertSubregInputs(const MachineInstr &MI, unsigned DefIdx,
510  RegSubRegPair &BaseReg,
511  RegSubRegPairAndIdx &InsertedReg) const;
512 
513  /// Return true if two machine instructions would produce identical values.
514  /// By default, this is only true when the two instructions
515  /// are deemed identical except for defs. If this function is called when the
516  /// IR is still in SSA form, the caller can pass the MachineRegisterInfo for
517  /// aggressive checks.
518  virtual bool produceSameValue(const MachineInstr &MI0,
519  const MachineInstr &MI1,
520  const MachineRegisterInfo *MRI = nullptr) const;
521 
522  /// \returns true if a branch from an instruction with opcode \p BranchOpc
523  /// bytes is capable of jumping to a position \p BrOffset bytes away.
524  virtual bool isBranchOffsetInRange(unsigned BranchOpc,
525  int64_t BrOffset) const {
526  llvm_unreachable("target did not implement");
527  }
528 
529  /// \returns The block that branch instruction \p MI jumps to.
531  llvm_unreachable("target did not implement");
532  }
533 
534  /// Insert an unconditional indirect branch at the end of \p MBB to \p
535  /// NewDestBB. \p BrOffset indicates the offset of \p NewDestBB relative to
536  /// the offset of the position to insert the new branch.
537  ///
538  /// \returns The number of bytes added to the block.
540  MachineBasicBlock &NewDestBB,
541  const DebugLoc &DL,
542  int64_t BrOffset = 0,
543  RegScavenger *RS = nullptr) const {
544  llvm_unreachable("target did not implement");
545  }
546 
547  /// Analyze the branching code at the end of MBB, returning
548  /// true if it cannot be understood (e.g. it's a switch dispatch or isn't
549  /// implemented for a target). Upon success, this returns false and returns
550  /// with the following information in various cases:
551  ///
552  /// 1. If this block ends with no branches (it just falls through to its succ)
553  /// just return false, leaving TBB/FBB null.
554  /// 2. If this block ends with only an unconditional branch, it sets TBB to be
555  /// the destination block.
556  /// 3. If this block ends with a conditional branch and it falls through to a
557  /// successor block, it sets TBB to be the branch destination block and a
558  /// list of operands that evaluate the condition. These operands can be
559  /// passed to other TargetInstrInfo methods to create new branches.
560  /// 4. If this block ends with a conditional branch followed by an
561  /// unconditional branch, it returns the 'true' destination in TBB, the
562  /// 'false' destination in FBB, and a list of operands that evaluate the
563  /// condition. These operands can be passed to other TargetInstrInfo
564  /// methods to create new branches.
565  ///
566  /// Note that removeBranch and insertBranch must be implemented to support
567  /// cases where this method returns success.
568  ///
569  /// If AllowModify is true, then this routine is allowed to modify the basic
570  /// block (e.g. delete instructions after the unconditional branch).
571  ///
572  /// The CFG information in MBB.Predecessors and MBB.Successors must be valid
573  /// before calling this function.
575  MachineBasicBlock *&FBB,
577  bool AllowModify = false) const {
578  return true;
579  }
580 
581  /// Represents a predicate at the MachineFunction level. The control flow a
582  /// MachineBranchPredicate represents is:
583  ///
584  /// Reg = LHS `Predicate` RHS == ConditionDef
585  /// if Reg then goto TrueDest else goto FalseDest
586  ///
589  PRED_EQ, // True if two values are equal
590  PRED_NE, // True if two values are not equal
591  PRED_INVALID // Sentinel value
592  };
593 
594  ComparePredicate Predicate = PRED_INVALID;
597  MachineBasicBlock *TrueDest = nullptr;
598  MachineBasicBlock *FalseDest = nullptr;
599  MachineInstr *ConditionDef = nullptr;
600 
601  /// SingleUseCondition is true if ConditionDef is dead except for the
602  /// branch(es) at the end of the basic block.
603  ///
604  bool SingleUseCondition = false;
605 
606  explicit MachineBranchPredicate() = default;
607  };
608 
609  /// Analyze the branching code at the end of MBB and parse it into the
610  /// MachineBranchPredicate structure if possible. Returns false on success
611  /// and true on failure.
612  ///
613  /// If AllowModify is true, then this routine is allowed to modify the basic
614  /// block (e.g. delete instructions after the unconditional branch).
615  ///
618  bool AllowModify = false) const {
619  return true;
620  }
621 
622  /// Remove the branching code at the end of the specific MBB.
623  /// This is only invoked in cases where AnalyzeBranch returns success. It
624  /// returns the number of instructions that were removed.
625  /// If \p BytesRemoved is non-null, report the change in code size from the
626  /// removed instructions.
627  virtual unsigned removeBranch(MachineBasicBlock &MBB,
628  int *BytesRemoved = nullptr) const {
629  llvm_unreachable("Target didn't implement TargetInstrInfo::removeBranch!");
630  }
631 
632  /// Insert branch code into the end of the specified MachineBasicBlock. The
633  /// operands to this method are the same as those returned by AnalyzeBranch.
634  /// This is only invoked in cases where AnalyzeBranch returns success. It
635  /// returns the number of instructions inserted. If \p BytesAdded is non-null,
636  /// report the change in code size from the added instructions.
637  ///
638  /// It is also invoked by tail merging to add unconditional branches in
639  /// cases where AnalyzeBranch doesn't apply because there was no original
640  /// branch to analyze. At least this much must be implemented, else tail
641  /// merging needs to be disabled.
642  ///
643  /// The CFG information in MBB.Predecessors and MBB.Successors must be valid
644  /// before calling this function.
645  virtual unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
646  MachineBasicBlock *FBB,
648  const DebugLoc &DL,
649  int *BytesAdded = nullptr) const {
650  llvm_unreachable("Target didn't implement TargetInstrInfo::insertBranch!");
651  }
652 
654  MachineBasicBlock *DestBB,
655  const DebugLoc &DL,
656  int *BytesAdded = nullptr) const {
657  return insertBranch(MBB, DestBB, nullptr, ArrayRef<MachineOperand>(), DL,
658  BytesAdded);
659  }
660 
661  /// Analyze the loop code, return true if it cannot be understoo. Upon
662  /// success, this function returns false and returns information about the
663  /// induction variable and compare instruction used at the end.
664  virtual bool analyzeLoop(MachineLoop &L, MachineInstr *&IndVarInst,
665  MachineInstr *&CmpInst) const {
666  return true;
667  }
668 
669  /// Generate code to reduce the loop iteration by one and check if the loop
670  /// is finished. Return the value/register of the new loop count. We need
671  /// this function when peeling off one or more iterations of a loop. This
672  /// function assumes the nth iteration is peeled first.
673  virtual unsigned reduceLoopCount(MachineBasicBlock &MBB,
674  MachineBasicBlock &PreHeader,
675  MachineInstr *IndVar, MachineInstr &Cmp,
678  unsigned Iter, unsigned MaxIter) const {
679  llvm_unreachable("Target didn't implement ReduceLoopCount");
680  }
681 
682  /// Delete the instruction OldInst and everything after it, replacing it with
683  /// an unconditional branch to NewDest. This is used by the tail merging pass.
685  MachineBasicBlock *NewDest) const;
686 
687  /// Return true if it's legal to split the given basic
688  /// block at the specified instruction (i.e. instruction would be the start
689  /// of a new basic block).
691  MachineBasicBlock::iterator MBBI) const {
692  return true;
693  }
694 
695  /// Return true if it's profitable to predicate
696  /// instructions with accumulated instruction latency of "NumCycles"
697  /// of the specified basic block, where the probability of the instructions
698  /// being executed is given by Probability, and Confidence is a measure
699  /// of our confidence that it will be properly predicted.
700  virtual bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
701  unsigned ExtraPredCycles,
702  BranchProbability Probability) const {
703  return false;
704  }
705 
706  /// Second variant of isProfitableToIfCvt. This one
707  /// checks for the case where two basic blocks from true and false path
708  /// of a if-then-else (diamond) are predicated on mutally exclusive
709  /// predicates, where the probability of the true path being taken is given
710  /// by Probability, and Confidence is a measure of our confidence that it
711  /// will be properly predicted.
712  virtual bool isProfitableToIfCvt(MachineBasicBlock &TMBB, unsigned NumTCycles,
713  unsigned ExtraTCycles,
714  MachineBasicBlock &FMBB, unsigned NumFCycles,
715  unsigned ExtraFCycles,
716  BranchProbability Probability) const {
717  return false;
718  }
719 
720  /// Return true if it's profitable for if-converter to duplicate instructions
721  /// of specified accumulated instruction latencies in the specified MBB to
722  /// enable if-conversion.
723  /// The probability of the instructions being executed is given by
724  /// Probability, and Confidence is a measure of our confidence that it
725  /// will be properly predicted.
727  unsigned NumCycles,
728  BranchProbability Probability) const {
729  return false;
730  }
731 
732  /// Return true if it's profitable to unpredicate
733  /// one side of a 'diamond', i.e. two sides of if-else predicated on mutually
734  /// exclusive predicates.
735  /// e.g.
736  /// subeq r0, r1, #1
737  /// addne r0, r1, #1
738  /// =>
739  /// sub r0, r1, #1
740  /// addne r0, r1, #1
741  ///
742  /// This may be profitable is conditional instructions are always executed.
744  MachineBasicBlock &FMBB) const {
745  return false;
746  }
747 
748  /// Return true if it is possible to insert a select
749  /// instruction that chooses between TrueReg and FalseReg based on the
750  /// condition code in Cond.
751  ///
752  /// When successful, also return the latency in cycles from TrueReg,
753  /// FalseReg, and Cond to the destination register. In most cases, a select
754  /// instruction will be 1 cycle, so CondCycles = TrueCycles = FalseCycles = 1
755  ///
756  /// Some x86 implementations have 2-cycle cmov instructions.
757  ///
758  /// @param MBB Block where select instruction would be inserted.
759  /// @param Cond Condition returned by AnalyzeBranch.
760  /// @param TrueReg Virtual register to select when Cond is true.
761  /// @param FalseReg Virtual register to select when Cond is false.
762  /// @param CondCycles Latency from Cond+Branch to select output.
763  /// @param TrueCycles Latency from TrueReg to select output.
764  /// @param FalseCycles Latency from FalseReg to select output.
765  virtual bool canInsertSelect(const MachineBasicBlock &MBB,
766  ArrayRef<MachineOperand> Cond, unsigned TrueReg,
767  unsigned FalseReg, int &CondCycles,
768  int &TrueCycles, int &FalseCycles) const {
769  return false;
770  }
771 
772  /// Insert a select instruction into MBB before I that will copy TrueReg to
773  /// DstReg when Cond is true, and FalseReg to DstReg when Cond is false.
774  ///
775  /// This function can only be called after canInsertSelect() returned true.
776  /// The condition in Cond comes from AnalyzeBranch, and it can be assumed
777  /// that the same flags or registers required by Cond are available at the
778  /// insertion point.
779  ///
780  /// @param MBB Block where select instruction should be inserted.
781  /// @param I Insertion point.
782  /// @param DL Source location for debugging.
783  /// @param DstReg Virtual register to be defined by select instruction.
784  /// @param Cond Condition as computed by AnalyzeBranch.
785  /// @param TrueReg Virtual register to copy when Cond is true.
786  /// @param FalseReg Virtual register to copy when Cons is false.
787  virtual void insertSelect(MachineBasicBlock &MBB,
789  unsigned DstReg, ArrayRef<MachineOperand> Cond,
790  unsigned TrueReg, unsigned FalseReg) const {
791  llvm_unreachable("Target didn't implement TargetInstrInfo::insertSelect!");
792  }
793 
794  /// Analyze the given select instruction, returning true if
795  /// it cannot be understood. It is assumed that MI->isSelect() is true.
796  ///
797  /// When successful, return the controlling condition and the operands that
798  /// determine the true and false result values.
799  ///
800  /// Result = SELECT Cond, TrueOp, FalseOp
801  ///
802  /// Some targets can optimize select instructions, for example by predicating
803  /// the instruction defining one of the operands. Such targets should set
804  /// Optimizable.
805  ///
806  /// @param MI Select instruction to analyze.
807  /// @param Cond Condition controlling the select.
808  /// @param TrueOp Operand number of the value selected when Cond is true.
809  /// @param FalseOp Operand number of the value selected when Cond is false.
810  /// @param Optimizable Returned as true if MI is optimizable.
811  /// @returns False on success.
812  virtual bool analyzeSelect(const MachineInstr &MI,
814  unsigned &TrueOp, unsigned &FalseOp,
815  bool &Optimizable) const {
816  assert(MI.getDesc().isSelect() && "MI must be a select instruction");
817  return true;
818  }
819 
820  /// Given a select instruction that was understood by
821  /// analyzeSelect and returned Optimizable = true, attempt to optimize MI by
822  /// merging it with one of its operands. Returns NULL on failure.
823  ///
824  /// When successful, returns the new select instruction. The client is
825  /// responsible for deleting MI.
826  ///
827  /// If both sides of the select can be optimized, PreferFalse is used to pick
828  /// a side.
829  ///
830  /// @param MI Optimizable select instruction.
831  /// @param NewMIs Set that record all MIs in the basic block up to \p
832  /// MI. Has to be updated with any newly created MI or deleted ones.
833  /// @param PreferFalse Try to optimize FalseOp instead of TrueOp.
834  /// @returns Optimized instruction or NULL.
837  bool PreferFalse = false) const {
838  // This function must be implemented if Optimizable is ever set.
839  llvm_unreachable("Target must implement TargetInstrInfo::optimizeSelect!");
840  }
841 
842  /// Emit instructions to copy a pair of physical registers.
843  ///
844  /// This function should support copies within any legal register class as
845  /// well as any cross-class copies created during instruction selection.
846  ///
847  /// The source and destination registers may overlap, which may require a
848  /// careful implementation when multiple copy instructions are required for
849  /// large registers. See for example the ARM target.
850  virtual void copyPhysReg(MachineBasicBlock &MBB,
852  unsigned DestReg, unsigned SrcReg,
853  bool KillSrc) const {
854  llvm_unreachable("Target didn't implement TargetInstrInfo::copyPhysReg!");
855  }
856 
857 protected:
858  /// Target-dependent implemenation for IsCopyInstr.
859  /// If the specific machine instruction is a instruction that moves/copies
860  /// value from one register to another register return true along with
861  /// @Source machine operand and @Destination machine operand.
862  virtual bool isCopyInstrImpl(const MachineInstr &MI,
863  const MachineOperand *&Source,
864  const MachineOperand *&Destination) const {
865  return false;
866  }
867 
868 public:
869  /// If the specific machine instruction is a instruction that moves/copies
870  /// value from one register to another register return true along with
871  /// @Source machine operand and @Destination machine operand.
872  /// For COPY-instruction the method naturally returns true, for all other
873  /// instructions the method calls target-dependent implementation.
875  const MachineOperand *&Destination) const {
876  if (MI.isCopy()) {
877  Destination = &MI.getOperand(0);
878  Source = &MI.getOperand(1);
879  return true;
880  }
881  return isCopyInstrImpl(MI, Source, Destination);
882  }
883 
884  /// Store the specified register of the given register class to the specified
885  /// stack frame index. The store instruction is to be added to the given
886  /// machine basic block before the specified machine instruction. If isKill
887  /// is true, the register operand is the last use and must be marked kill.
890  unsigned SrcReg, bool isKill, int FrameIndex,
891  const TargetRegisterClass *RC,
892  const TargetRegisterInfo *TRI) const {
893  llvm_unreachable("Target didn't implement "
894  "TargetInstrInfo::storeRegToStackSlot!");
895  }
896 
897  /// Load the specified register of the given register class from the specified
898  /// stack frame index. The load instruction is to be added to the given
899  /// machine basic block before the specified machine instruction.
902  unsigned DestReg, int FrameIndex,
903  const TargetRegisterClass *RC,
904  const TargetRegisterInfo *TRI) const {
905  llvm_unreachable("Target didn't implement "
906  "TargetInstrInfo::loadRegFromStackSlot!");
907  }
908 
909  /// This function is called for all pseudo instructions
910  /// that remain after register allocation. Many pseudo instructions are
911  /// created to help register allocation. This is the place to convert them
912  /// into real instructions. The target can edit MI in place, or it can insert
913  /// new instructions and erase MI. The function should return true if
914  /// anything was changed.
915  virtual bool expandPostRAPseudo(MachineInstr &MI) const { return false; }
916 
917  /// Check whether the target can fold a load that feeds a subreg operand
918  /// (or a subreg operand that feeds a store).
919  /// For example, X86 may want to return true if it can fold
920  /// movl (%esp), %eax
921  /// subb, %al, ...
922  /// Into:
923  /// subb (%esp), ...
924  ///
925  /// Ideally, we'd like the target implementation of foldMemoryOperand() to
926  /// reject subregs - but since this behavior used to be enforced in the
927  /// target-independent code, moving this responsibility to the targets
928  /// has the potential of causing nasty silent breakage in out-of-tree targets.
929  virtual bool isSubregFoldable() const { return false; }
930 
931  /// Attempt to fold a load or store of the specified stack
932  /// slot into the specified machine instruction for the specified operand(s).
933  /// If this is possible, a new instruction is returned with the specified
934  /// operand folded, otherwise NULL is returned.
935  /// The new instruction is inserted before MI, and the client is responsible
936  /// for removing the old instruction.
937  /// If VRM is passed, the assigned physregs can be inspected by target to
938  /// decide on using an opcode (note that those assignments can still change).
940  int FI,
941  LiveIntervals *LIS = nullptr,
942  VirtRegMap *VRM = nullptr) const;
943 
944  /// Same as the previous version except it allows folding of any load and
945  /// store from / to any address, not just from a specific stack slot.
947  MachineInstr &LoadMI,
948  LiveIntervals *LIS = nullptr) const;
949 
950  /// Return true when there is potentially a faster code sequence
951  /// for an instruction chain ending in \p Root. All potential patterns are
952  /// returned in the \p Pattern vector. Pattern should be sorted in priority
953  /// order since the pattern evaluator stops checking as soon as it finds a
954  /// faster sequence.
955  /// \param Root - Instruction that could be combined with one of its operands
956  /// \param Patterns - Vector of possible combination patterns
957  virtual bool getMachineCombinerPatterns(
958  MachineInstr &Root,
960 
961  /// Return true when a code sequence can improve throughput. It
962  /// should be called only for instructions in loops.
963  /// \param Pattern - combiner pattern
964  virtual bool isThroughputPattern(MachineCombinerPattern Pattern) const;
965 
966  /// Return true if the input \P Inst is part of a chain of dependent ops
967  /// that are suitable for reassociation, otherwise return false.
968  /// If the instruction's operands must be commuted to have a previous
969  /// instruction of the same type define the first source operand, \P Commuted
970  /// will be set to true.
971  bool isReassociationCandidate(const MachineInstr &Inst, bool &Commuted) const;
972 
973  /// Return true when \P Inst is both associative and commutative.
974  virtual bool isAssociativeAndCommutative(const MachineInstr &Inst) const {
975  return false;
976  }
977 
978  /// Return true when \P Inst has reassociable operands in the same \P MBB.
979  virtual bool hasReassociableOperands(const MachineInstr &Inst,
980  const MachineBasicBlock *MBB) const;
981 
982  /// Return true when \P Inst has reassociable sibling.
983  bool hasReassociableSibling(const MachineInstr &Inst, bool &Commuted) const;
984 
985  /// When getMachineCombinerPatterns() finds patterns, this function generates
986  /// the instructions that could replace the original code sequence. The client
987  /// has to decide whether the actual replacement is beneficial or not.
988  /// \param Root - Instruction that could be combined with one of its operands
989  /// \param Pattern - Combination pattern for Root
990  /// \param InsInstrs - Vector of new instructions that implement P
991  /// \param DelInstrs - Old instructions, including Root, that could be
992  /// replaced by InsInstr
993  /// \param InstIdxForVirtReg - map of virtual register to instruction in
994  /// InsInstr that defines it
995  virtual void genAlternativeCodeSequence(
996  MachineInstr &Root, MachineCombinerPattern Pattern,
999  DenseMap<unsigned, unsigned> &InstIdxForVirtReg) const;
1000 
1001  /// Attempt to reassociate \P Root and \P Prev according to \P Pattern to
1002  /// reduce critical path length.
1003  void reassociateOps(MachineInstr &Root, MachineInstr &Prev,
1004  MachineCombinerPattern Pattern,
1007  DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const;
1008 
1009  /// This is an architecture-specific helper function of reassociateOps.
1010  /// Set special operand attributes for new instructions after reassociation.
1011  virtual void setSpecialOperandAttr(MachineInstr &OldMI1, MachineInstr &OldMI2,
1012  MachineInstr &NewMI1,
1013  MachineInstr &NewMI2) const {}
1014 
1015  /// Return true when a target supports MachineCombiner.
1016  virtual bool useMachineCombiner() const { return false; }
1017 
1018  /// Return true if the given SDNode can be copied during scheduling
1019  /// even if it has glue.
1020  virtual bool canCopyGluedNodeDuringSchedule(SDNode *N) const { return false; }
1021 
1022 protected:
1023  /// Target-dependent implementation for foldMemoryOperand.
1024  /// Target-independent code in foldMemoryOperand will
1025  /// take care of adding a MachineMemOperand to the newly created instruction.
1026  /// The instruction and any auxiliary instructions necessary will be inserted
1027  /// at InsertPt.
1028  virtual MachineInstr *
1030  ArrayRef<unsigned> Ops,
1032  LiveIntervals *LIS = nullptr,
1033  VirtRegMap *VRM = nullptr) const {
1034  return nullptr;
1035  }
1036 
1037  /// Target-dependent implementation for foldMemoryOperand.
1038  /// Target-independent code in foldMemoryOperand will
1039  /// take care of adding a MachineMemOperand to the newly created instruction.
1040  /// The instruction and any auxiliary instructions necessary will be inserted
1041  /// at InsertPt.
1044  MachineBasicBlock::iterator InsertPt, MachineInstr &LoadMI,
1045  LiveIntervals *LIS = nullptr) const {
1046  return nullptr;
1047  }
1048 
1049  /// Target-dependent implementation of getRegSequenceInputs.
1050  ///
1051  /// \returns true if it is possible to build the equivalent
1052  /// REG_SEQUENCE inputs with the pair \p MI, \p DefIdx. False otherwise.
1053  ///
1054  /// \pre MI.isRegSequenceLike().
1055  ///
1056  /// \see TargetInstrInfo::getRegSequenceInputs.
1058  const MachineInstr &MI, unsigned DefIdx,
1059  SmallVectorImpl<RegSubRegPairAndIdx> &InputRegs) const {
1060  return false;
1061  }
1062 
1063  /// Target-dependent implementation of getExtractSubregInputs.
1064  ///
1065  /// \returns true if it is possible to build the equivalent
1066  /// EXTRACT_SUBREG inputs with the pair \p MI, \p DefIdx. False otherwise.
1067  ///
1068  /// \pre MI.isExtractSubregLike().
1069  ///
1070  /// \see TargetInstrInfo::getExtractSubregInputs.
1072  unsigned DefIdx,
1073  RegSubRegPairAndIdx &InputReg) const {
1074  return false;
1075  }
1076 
1077  /// Target-dependent implementation of getInsertSubregInputs.
1078  ///
1079  /// \returns true if it is possible to build the equivalent
1080  /// INSERT_SUBREG inputs with the pair \p MI, \p DefIdx. False otherwise.
1081  ///
1082  /// \pre MI.isInsertSubregLike().
1083  ///
1084  /// \see TargetInstrInfo::getInsertSubregInputs.
1085  virtual bool
1086  getInsertSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx,
1087  RegSubRegPair &BaseReg,
1088  RegSubRegPairAndIdx &InsertedReg) const {
1089  return false;
1090  }
1091 
1092 public:
1093  /// getAddressSpaceForPseudoSourceKind - Given the kind of memory
1094  /// (e.g. stack) the target returns the corresponding address space.
1095  virtual unsigned
1097  return 0;
1098  }
1099 
1100  /// unfoldMemoryOperand - Separate a single instruction which folded a load or
1101  /// a store or a load and a store into two or more instruction. If this is
1102  /// possible, returns true as well as the new instructions by reference.
1103  virtual bool
1105  bool UnfoldLoad, bool UnfoldStore,
1106  SmallVectorImpl<MachineInstr *> &NewMIs) const {
1107  return false;
1108  }
1109 
1111  SmallVectorImpl<SDNode *> &NewNodes) const {
1112  return false;
1113  }
1114 
1115  /// Returns the opcode of the would be new
1116  /// instruction after load / store are unfolded from an instruction of the
1117  /// specified opcode. It returns zero if the specified unfolding is not
1118  /// possible. If LoadRegIndex is non-null, it is filled in with the operand
1119  /// index of the operand which will hold the register holding the loaded
1120  /// value.
1121  virtual unsigned
1122  getOpcodeAfterMemoryUnfold(unsigned Opc, bool UnfoldLoad, bool UnfoldStore,
1123  unsigned *LoadRegIndex = nullptr) const {
1124  return 0;
1125  }
1126 
1127  /// This is used by the pre-regalloc scheduler to determine if two loads are
1128  /// loading from the same base address. It should only return true if the base
1129  /// pointers are the same and the only differences between the two addresses
1130  /// are the offset. It also returns the offsets by reference.
1131  virtual bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
1132  int64_t &Offset1,
1133  int64_t &Offset2) const {
1134  return false;
1135  }
1136 
1137  /// This is a used by the pre-regalloc scheduler to determine (in conjunction
1138  /// with areLoadsFromSameBasePtr) if two loads should be scheduled together.
1139  /// On some targets if two loads are loading from
1140  /// addresses in the same cache line, it's better if they are scheduled
1141  /// together. This function takes two integers that represent the load offsets
1142  /// from the common base address. It returns true if it decides it's desirable
1143  /// to schedule the two loads together. "NumLoads" is the number of loads that
1144  /// have already been scheduled after Load1.
1145  virtual bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
1146  int64_t Offset1, int64_t Offset2,
1147  unsigned NumLoads) const {
1148  return false;
1149  }
1150 
1151  /// Get the base operand and byte offset of an instruction that reads/writes
1152  /// memory.
1153  virtual bool getMemOperandWithOffset(const MachineInstr &MI,
1154  const MachineOperand *&BaseOp,
1155  int64_t &Offset,
1156  const TargetRegisterInfo *TRI) const {
1157  return false;
1158  }
1159 
1160  /// Return true if the instruction contains a base register and offset. If
1161  /// true, the function also sets the operand position in the instruction
1162  /// for the base register and offset.
1163  virtual bool getBaseAndOffsetPosition(const MachineInstr &MI,
1164  unsigned &BasePos,
1165  unsigned &OffsetPos) const {
1166  return false;
1167  }
1168 
1169  /// If the instruction is an increment of a constant value, return the amount.
1170  virtual bool getIncrementValue(const MachineInstr &MI, int &Value) const {
1171  return false;
1172  }
1173 
1174  /// Returns true if the two given memory operations should be scheduled
1175  /// adjacent. Note that you have to add:
1176  /// DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
1177  /// or
1178  /// DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
1179  /// to TargetPassConfig::createMachineScheduler() to have an effect.
1180  virtual bool shouldClusterMemOps(const MachineOperand &BaseOp1,
1181  const MachineOperand &BaseOp2,
1182  unsigned NumLoads) const {
1183  llvm_unreachable("target did not implement shouldClusterMemOps()");
1184  }
1185 
1186  /// Reverses the branch condition of the specified condition list,
1187  /// returning false on success and true if it cannot be reversed.
1188  virtual bool
1190  return true;
1191  }
1192 
1193  /// Insert a noop into the instruction stream at the specified point.
1194  virtual void insertNoop(MachineBasicBlock &MBB,
1195  MachineBasicBlock::iterator MI) const;
1196 
1197  /// Return the noop instruction to use for a noop.
1198  virtual void getNoop(MCInst &NopInst) const;
1199 
1200  /// Return true for post-incremented instructions.
1201  virtual bool isPostIncrement(const MachineInstr &MI) const { return false; }
1202 
1203  /// Returns true if the instruction is already predicated.
1204  virtual bool isPredicated(const MachineInstr &MI) const { return false; }
1205 
1206  /// Returns true if the instruction is a
1207  /// terminator instruction that has not been predicated.
1208  virtual bool isUnpredicatedTerminator(const MachineInstr &MI) const;
1209 
1210  /// Returns true if MI is an unconditional tail call.
1211  virtual bool isUnconditionalTailCall(const MachineInstr &MI) const {
1212  return false;
1213  }
1214 
1215  /// Returns true if the tail call can be made conditional on BranchCond.
1217  const MachineInstr &TailCall) const {
1218  return false;
1219  }
1220 
1221  /// Replace the conditional branch in MBB with a conditional tail call.
1224  const MachineInstr &TailCall) const {
1225  llvm_unreachable("Target didn't implement replaceBranchWithTailCall!");
1226  }
1227 
1228  /// Convert the instruction into a predicated instruction.
1229  /// It returns true if the operation was successful.
1230  virtual bool PredicateInstruction(MachineInstr &MI,
1231  ArrayRef<MachineOperand> Pred) const;
1232 
1233  /// Returns true if the first specified predicate
1234  /// subsumes the second, e.g. GE subsumes GT.
1236  ArrayRef<MachineOperand> Pred2) const {
1237  return false;
1238  }
1239 
1240  /// If the specified instruction defines any predicate
1241  /// or condition code register(s) used for predication, returns true as well
1242  /// as the definition predicate(s) by reference.
1243  virtual bool DefinesPredicate(MachineInstr &MI,
1244  std::vector<MachineOperand> &Pred) const {
1245  return false;
1246  }
1247 
1248  /// Return true if the specified instruction can be predicated.
1249  /// By default, this returns true for every instruction with a
1250  /// PredicateOperand.
1251  virtual bool isPredicable(const MachineInstr &MI) const {
1252  return MI.getDesc().isPredicable();
1253  }
1254 
1255  /// Return true if it's safe to move a machine
1256  /// instruction that defines the specified register class.
1257  virtual bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
1258  return true;
1259  }
1260 
1261  /// Test if the given instruction should be considered a scheduling boundary.
1262  /// This primarily includes labels and terminators.
1263  virtual bool isSchedulingBoundary(const MachineInstr &MI,
1264  const MachineBasicBlock *MBB,
1265  const MachineFunction &MF) const;
1266 
1267  /// Measure the specified inline asm to determine an approximation of its
1268  /// length.
1269  virtual unsigned getInlineAsmLength(
1270  const char *Str, const MCAsmInfo &MAI,
1271  const TargetSubtargetInfo *STI = nullptr) const;
1272 
1273  /// Allocate and return a hazard recognizer to use for this target when
1274  /// scheduling the machine instructions before register allocation.
1275  virtual ScheduleHazardRecognizer *
1277  const ScheduleDAG *DAG) const;
1278 
1279  /// Allocate and return a hazard recognizer to use for this target when
1280  /// scheduling the machine instructions before register allocation.
1281  virtual ScheduleHazardRecognizer *
1283  const ScheduleDAG *DAG) const;
1284 
1285  /// Allocate and return a hazard recognizer to use for this target when
1286  /// scheduling the machine instructions after register allocation.
1287  virtual ScheduleHazardRecognizer *
1289  const ScheduleDAG *DAG) const;
1290 
1291  /// Allocate and return a hazard recognizer to use for by non-scheduling
1292  /// passes.
1293  virtual ScheduleHazardRecognizer *
1295  return nullptr;
1296  }
1297 
1298  /// Provide a global flag for disabling the PreRA hazard recognizer that
1299  /// targets may choose to honor.
1300  bool usePreRAHazardRecognizer() const;
1301 
1302  /// For a comparison instruction, return the source registers
1303  /// in SrcReg and SrcReg2 if having two register operands, and the value it
1304  /// compares against in CmpValue. Return true if the comparison instruction
1305  /// can be analyzed.
1306  virtual bool analyzeCompare(const MachineInstr &MI, unsigned &SrcReg,
1307  unsigned &SrcReg2, int &Mask, int &Value) const {
1308  return false;
1309  }
1310 
1311  /// See if the comparison instruction can be converted
1312  /// into something more efficient. E.g., on ARM most instructions can set the
1313  /// flags register, obviating the need for a separate CMP.
1314  virtual bool optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg,
1315  unsigned SrcReg2, int Mask, int Value,
1316  const MachineRegisterInfo *MRI) const {
1317  return false;
1318  }
1319  virtual bool optimizeCondBranch(MachineInstr &MI) const { return false; }
1320 
1321  /// Try to remove the load by folding it to a register operand at the use.
1322  /// We fold the load instructions if and only if the
1323  /// def and use are in the same BB. We only look at one load and see
1324  /// whether it can be folded into MI. FoldAsLoadDefReg is the virtual register
1325  /// defined by the load we are trying to fold. DefMI returns the machine
1326  /// instruction that defines FoldAsLoadDefReg, and the function returns
1327  /// the machine instruction generated due to folding.
1329  const MachineRegisterInfo *MRI,
1330  unsigned &FoldAsLoadDefReg,
1331  MachineInstr *&DefMI) const {
1332  return nullptr;
1333  }
1334 
1335  /// 'Reg' is known to be defined by a move immediate instruction,
1336  /// try to fold the immediate into the use instruction.
1337  /// If MRI->hasOneNonDBGUse(Reg) is true, and this function returns true,
1338  /// then the caller may assume that DefMI has been erased from its parent
1339  /// block. The caller may assume that it will not be erased by this
1340  /// function otherwise.
1342  unsigned Reg, MachineRegisterInfo *MRI) const {
1343  return false;
1344  }
1345 
1346  /// Return the number of u-operations the given machine
1347  /// instruction will be decoded to on the target cpu. The itinerary's
1348  /// IssueWidth is the number of microops that can be dispatched each
1349  /// cycle. An instruction with zero microops takes no dispatch resources.
1350  virtual unsigned getNumMicroOps(const InstrItineraryData *ItinData,
1351  const MachineInstr &MI) const;
1352 
1353  /// Return true for pseudo instructions that don't consume any
1354  /// machine resources in their current form. These are common cases that the
1355  /// scheduler should consider free, rather than conservatively handling them
1356  /// as instructions with no itinerary.
1357  bool isZeroCost(unsigned Opcode) const {
1358  return Opcode <= TargetOpcode::COPY;
1359  }
1360 
1361  virtual int getOperandLatency(const InstrItineraryData *ItinData,
1362  SDNode *DefNode, unsigned DefIdx,
1363  SDNode *UseNode, unsigned UseIdx) const;
1364 
1365  /// Compute and return the use operand latency of a given pair of def and use.
1366  /// In most cases, the static scheduling itinerary was enough to determine the
1367  /// operand latency. But it may not be possible for instructions with variable
1368  /// number of defs / uses.
1369  ///
1370  /// This is a raw interface to the itinerary that may be directly overridden
1371  /// by a target. Use computeOperandLatency to get the best estimate of
1372  /// latency.
1373  virtual int getOperandLatency(const InstrItineraryData *ItinData,
1374  const MachineInstr &DefMI, unsigned DefIdx,
1375  const MachineInstr &UseMI,
1376  unsigned UseIdx) const;
1377 
1378  /// Compute the instruction latency of a given instruction.
1379  /// If the instruction has higher cost when predicated, it's returned via
1380  /// PredCost.
1381  virtual unsigned getInstrLatency(const InstrItineraryData *ItinData,
1382  const MachineInstr &MI,
1383  unsigned *PredCost = nullptr) const;
1384 
1385  virtual unsigned getPredicationCost(const MachineInstr &MI) const;
1386 
1387  virtual int getInstrLatency(const InstrItineraryData *ItinData,
1388  SDNode *Node) const;
1389 
1390  /// Return the default expected latency for a def based on its opcode.
1391  unsigned defaultDefLatency(const MCSchedModel &SchedModel,
1392  const MachineInstr &DefMI) const;
1393 
1394  int computeDefOperandLatency(const InstrItineraryData *ItinData,
1395  const MachineInstr &DefMI) const;
1396 
1397  /// Return true if this opcode has high latency to its result.
1398  virtual bool isHighLatencyDef(int opc) const { return false; }
1399 
1400  /// Compute operand latency between a def of 'Reg'
1401  /// and a use in the current loop. Return true if the target considered
1402  /// it 'high'. This is used by optimization passes such as machine LICM to
1403  /// determine whether it makes sense to hoist an instruction out even in a
1404  /// high register pressure situation.
1405  virtual bool hasHighOperandLatency(const TargetSchedModel &SchedModel,
1406  const MachineRegisterInfo *MRI,
1407  const MachineInstr &DefMI, unsigned DefIdx,
1408  const MachineInstr &UseMI,
1409  unsigned UseIdx) const {
1410  return false;
1411  }
1412 
1413  /// Compute operand latency of a def of 'Reg'. Return true
1414  /// if the target considered it 'low'.
1415  virtual bool hasLowDefLatency(const TargetSchedModel &SchedModel,
1416  const MachineInstr &DefMI,
1417  unsigned DefIdx) const;
1418 
1419  /// Perform target-specific instruction verification.
1420  virtual bool verifyInstruction(const MachineInstr &MI,
1421  StringRef &ErrInfo) const {
1422  return true;
1423  }
1424 
1425  /// Return the current execution domain and bit mask of
1426  /// possible domains for instruction.
1427  ///
1428  /// Some micro-architectures have multiple execution domains, and multiple
1429  /// opcodes that perform the same operation in different domains. For
1430  /// example, the x86 architecture provides the por, orps, and orpd
1431  /// instructions that all do the same thing. There is a latency penalty if a
1432  /// register is written in one domain and read in another.
1433  ///
1434  /// This function returns a pair (domain, mask) containing the execution
1435  /// domain of MI, and a bit mask of possible domains. The setExecutionDomain
1436  /// function can be used to change the opcode to one of the domains in the
1437  /// bit mask. Instructions whose execution domain can't be changed should
1438  /// return a 0 mask.
1439  ///
1440  /// The execution domain numbers don't have any special meaning except domain
1441  /// 0 is used for instructions that are not associated with any interesting
1442  /// execution domain.
1443  ///
1444  virtual std::pair<uint16_t, uint16_t>
1446  return std::make_pair(0, 0);
1447  }
1448 
1449  /// Change the opcode of MI to execute in Domain.
1450  ///
1451  /// The bit (1 << Domain) must be set in the mask returned from
1452  /// getExecutionDomain(MI).
1453  virtual void setExecutionDomain(MachineInstr &MI, unsigned Domain) const {}
1454 
1455  /// Returns the preferred minimum clearance
1456  /// before an instruction with an unwanted partial register update.
1457  ///
1458  /// Some instructions only write part of a register, and implicitly need to
1459  /// read the other parts of the register. This may cause unwanted stalls
1460  /// preventing otherwise unrelated instructions from executing in parallel in
1461  /// an out-of-order CPU.
1462  ///
1463  /// For example, the x86 instruction cvtsi2ss writes its result to bits
1464  /// [31:0] of the destination xmm register. Bits [127:32] are unaffected, so
1465  /// the instruction needs to wait for the old value of the register to become
1466  /// available:
1467  ///
1468  /// addps %xmm1, %xmm0
1469  /// movaps %xmm0, (%rax)
1470  /// cvtsi2ss %rbx, %xmm0
1471  ///
1472  /// In the code above, the cvtsi2ss instruction needs to wait for the addps
1473  /// instruction before it can issue, even though the high bits of %xmm0
1474  /// probably aren't needed.
1475  ///
1476  /// This hook returns the preferred clearance before MI, measured in
1477  /// instructions. Other defs of MI's operand OpNum are avoided in the last N
1478  /// instructions before MI. It should only return a positive value for
1479  /// unwanted dependencies. If the old bits of the defined register have
1480  /// useful values, or if MI is determined to otherwise read the dependency,
1481  /// the hook should return 0.
1482  ///
1483  /// The unwanted dependency may be handled by:
1484  ///
1485  /// 1. Allocating the same register for an MI def and use. That makes the
1486  /// unwanted dependency identical to a required dependency.
1487  ///
1488  /// 2. Allocating a register for the def that has no defs in the previous N
1489  /// instructions.
1490  ///
1491  /// 3. Calling breakPartialRegDependency() with the same arguments. This
1492  /// allows the target to insert a dependency breaking instruction.
1493  ///
1494  virtual unsigned
1495  getPartialRegUpdateClearance(const MachineInstr &MI, unsigned OpNum,
1496  const TargetRegisterInfo *TRI) const {
1497  // The default implementation returns 0 for no partial register dependency.
1498  return 0;
1499  }
1500 
1501  /// Return the minimum clearance before an instruction that reads an
1502  /// unused register.
1503  ///
1504  /// For example, AVX instructions may copy part of a register operand into
1505  /// the unused high bits of the destination register.
1506  ///
1507  /// vcvtsi2sdq %rax, undef %xmm0, %xmm14
1508  ///
1509  /// In the code above, vcvtsi2sdq copies %xmm0[127:64] into %xmm14 creating a
1510  /// false dependence on any previous write to %xmm0.
1511  ///
1512  /// This hook works similarly to getPartialRegUpdateClearance, except that it
1513  /// does not take an operand index. Instead sets \p OpNum to the index of the
1514  /// unused register.
1515  virtual unsigned getUndefRegClearance(const MachineInstr &MI, unsigned &OpNum,
1516  const TargetRegisterInfo *TRI) const {
1517  // The default implementation returns 0 for no undef register dependency.
1518  return 0;
1519  }
1520 
1521  /// Insert a dependency-breaking instruction
1522  /// before MI to eliminate an unwanted dependency on OpNum.
1523  ///
1524  /// If it wasn't possible to avoid a def in the last N instructions before MI
1525  /// (see getPartialRegUpdateClearance), this hook will be called to break the
1526  /// unwanted dependency.
1527  ///
1528  /// On x86, an xorps instruction can be used as a dependency breaker:
1529  ///
1530  /// addps %xmm1, %xmm0
1531  /// movaps %xmm0, (%rax)
1532  /// xorps %xmm0, %xmm0
1533  /// cvtsi2ss %rbx, %xmm0
1534  ///
1535  /// An <imp-kill> operand should be added to MI if an instruction was
1536  /// inserted. This ties the instructions together in the post-ra scheduler.
1537  ///
1538  virtual void breakPartialRegDependency(MachineInstr &MI, unsigned OpNum,
1539  const TargetRegisterInfo *TRI) const {}
1540 
1541  /// Create machine specific model for scheduling.
1542  virtual DFAPacketizer *
1544  return nullptr;
1545  }
1546 
1547  /// Sometimes, it is possible for the target
1548  /// to tell, even without aliasing information, that two MIs access different
1549  /// memory addresses. This function returns true if two MIs access different
1550  /// memory addresses and false otherwise.
1551  ///
1552  /// Assumes any physical registers used to compute addresses have the same
1553  /// value for both instructions. (This is the most useful assumption for
1554  /// post-RA scheduling.)
1555  ///
1556  /// See also MachineInstr::mayAlias, which is implemented on top of this
1557  /// function.
1558  virtual bool
1560  const MachineInstr &MIb,
1561  AliasAnalysis *AA = nullptr) const {
1562  assert((MIa.mayLoad() || MIa.mayStore()) &&
1563  "MIa must load from or modify a memory location");
1564  assert((MIb.mayLoad() || MIb.mayStore()) &&
1565  "MIb must load from or modify a memory location");
1566  return false;
1567  }
1568 
1569  /// Return the value to use for the MachineCSE's LookAheadLimit,
1570  /// which is a heuristic used for CSE'ing phys reg defs.
1571  virtual unsigned getMachineCSELookAheadLimit() const {
1572  // The default lookahead is small to prevent unprofitable quadratic
1573  // behavior.
1574  return 5;
1575  }
1576 
1577  /// Return an array that contains the ids of the target indices (used for the
1578  /// TargetIndex machine operand) and their names.
1579  ///
1580  /// MIR Serialization is able to serialize only the target indices that are
1581  /// defined by this method.
1584  return None;
1585  }
1586 
1587  /// Decompose the machine operand's target flags into two values - the direct
1588  /// target flag value and any of bit flags that are applied.
1589  virtual std::pair<unsigned, unsigned>
1590  decomposeMachineOperandsTargetFlags(unsigned /*TF*/) const {
1591  return std::make_pair(0u, 0u);
1592  }
1593 
1594  /// Return an array that contains the direct target flag values and their
1595  /// names.
1596  ///
1597  /// MIR Serialization is able to serialize only the target flags that are
1598  /// defined by this method.
1601  return None;
1602  }
1603 
1604  /// Return an array that contains the bitmask target flag values and their
1605  /// names.
1606  ///
1607  /// MIR Serialization is able to serialize only the target flags that are
1608  /// defined by this method.
1611  return None;
1612  }
1613 
1614  /// Return an array that contains the MMO target flag values and their
1615  /// names.
1616  ///
1617  /// MIR Serialization is able to serialize only the MMO target flags that are
1618  /// defined by this method.
1621  return None;
1622  }
1623 
1624  /// Determines whether \p Inst is a tail call instruction. Override this
1625  /// method on targets that do not properly set MCID::Return and MCID::Call on
1626  /// tail call instructions."
1627  virtual bool isTailCall(const MachineInstr &Inst) const {
1628  return Inst.isReturn() && Inst.isCall();
1629  }
1630 
1631  /// True if the instruction is bound to the top of its basic block and no
1632  /// other instructions shall be inserted before it. This can be implemented
1633  /// to prevent register allocator to insert spills before such instructions.
1634  virtual bool isBasicBlockPrologue(const MachineInstr &MI) const {
1635  return false;
1636  }
1637 
1638  /// Returns a \p outliner::OutlinedFunction struct containing target-specific
1639  /// information for a set of outlining candidates.
1641  std::vector<outliner::Candidate> &RepeatedSequenceLocs) const {
1643  "Target didn't implement TargetInstrInfo::getOutliningCandidateInfo!");
1644  }
1645 
1646  /// Returns how or if \p MI should be outlined.
1647  virtual outliner::InstrType
1648  getOutliningType(MachineBasicBlock::iterator &MIT, unsigned Flags) const {
1650  "Target didn't implement TargetInstrInfo::getOutliningType!");
1651  }
1652 
1653  /// Optional target hook that returns true if \p MBB is safe to outline from,
1654  /// and returns any target-specific information in \p Flags.
1656  unsigned &Flags) const {
1657  return true;
1658  }
1659 
1660  /// Insert a custom frame for outlined functions.
1662  const outliner::OutlinedFunction &OF) const {
1664  "Target didn't implement TargetInstrInfo::buildOutlinedFrame!");
1665  }
1666 
1667  /// Insert a call to an outlined function into the program.
1668  /// Returns an iterator to the spot where we inserted the call. This must be
1669  /// implemented by the target.
1673  const outliner::Candidate &C) const {
1675  "Target didn't implement TargetInstrInfo::insertOutlinedCall!");
1676  }
1677 
1678  /// Return true if the function can safely be outlined from.
1679  /// A function \p MF is considered safe for outlining if an outlined function
1680  /// produced from instructions in F will produce a program which produces the
1681  /// same output for any set of given inputs.
1683  bool OutlineFromLinkOnceODRs) const {
1684  llvm_unreachable("Target didn't implement "
1685  "TargetInstrInfo::isFunctionSafeToOutlineFrom!");
1686  }
1687 
1688  /// Return true if the function should be outlined from by default.
1690  return false;
1691  }
1692 
1693 private:
1694  unsigned CallFrameSetupOpcode, CallFrameDestroyOpcode;
1695  unsigned CatchRetOpcode;
1696  unsigned ReturnOpcode;
1697 };
1698 
1699 /// Provide DenseMapInfo for TargetInstrInfo::RegSubRegPair.
1702 
1704  return TargetInstrInfo::RegSubRegPair(RegInfo::getEmptyKey(),
1705  RegInfo::getEmptyKey());
1706  }
1707 
1709  return TargetInstrInfo::RegSubRegPair(RegInfo::getTombstoneKey(),
1710  RegInfo::getTombstoneKey());
1711  }
1712 
1713  /// Reuse getHashValue implementation from
1714  /// std::pair<unsigned, unsigned>.
1715  static unsigned getHashValue(const TargetInstrInfo::RegSubRegPair &Val) {
1716  std::pair<unsigned, unsigned> PairVal = std::make_pair(Val.Reg, Val.SubReg);
1717  return DenseMapInfo<std::pair<unsigned, unsigned>>::getHashValue(PairVal);
1718  }
1719 
1720  static bool isEqual(const TargetInstrInfo::RegSubRegPair &LHS,
1721  const TargetInstrInfo::RegSubRegPair &RHS) {
1722  return RegInfo::isEqual(LHS.Reg, RHS.Reg) &&
1723  RegInfo::isEqual(LHS.SubReg, RHS.SubReg);
1724  }
1725 };
1726 
1727 } // end namespace llvm
1728 
1729 #endif // LLVM_TARGET_TARGETINSTRINFO_H
virtual std::pair< unsigned, unsigned > decomposeMachineOperandsTargetFlags(unsigned) const
Decompose the machine operand&#39;s target flags into two values - the direct target flag value and any o...
uint64_t CallInst * C
This class is the base class for the comparison instructions.
Definition: InstrTypes.h:722
virtual bool expandPostRAPseudo(MachineInstr &MI) const
This function is called for all pseudo instructions that remain after register allocation.
static unsigned getHashValue(const TargetInstrInfo::RegSubRegPair &Val)
Reuse getHashValue implementation from std::pair<unsigned, unsigned>.
virtual bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1, int64_t &Offset2) const
This is used by the pre-regalloc scheduler to determine if two loads are loading from the same base a...
virtual bool canInsertSelect(const MachineBasicBlock &MBB, ArrayRef< MachineOperand > Cond, unsigned TrueReg, unsigned FalseReg, int &CondCycles, int &TrueCycles, int &FalseCycles) const
Return true if it is possible to insert a select instruction that chooses between TrueReg and FalseRe...
bool isCall(QueryType Type=AnyInBundle) const
Definition: MachineInstr.h:634
static TargetInstrInfo::RegSubRegPair getTombstoneKey()
virtual void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, unsigned DstReg, ArrayRef< MachineOperand > Cond, unsigned TrueReg, unsigned FalseReg) const
Insert a select instruction into MBB before I that will copy TrueReg to DstReg when Cond is true...
virtual bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const
Return true if it&#39;s safe to move a machine instruction that defines the specified register class...
virtual bool isCopyInstrImpl(const MachineInstr &MI, const MachineOperand *&Source, const MachineOperand *&Destination) const
Target-dependent implemenation for IsCopyInstr.
virtual unsigned reduceLoopCount(MachineBasicBlock &MBB, MachineBasicBlock &PreHeader, MachineInstr *IndVar, MachineInstr &Cmp, SmallVectorImpl< MachineOperand > &Cond, SmallVectorImpl< MachineInstr *> &PrevInsts, unsigned Iter, unsigned MaxIter) const
Generate code to reduce the loop iteration by one and check if the loop is finished.
This class represents lattice values for constants.
Definition: AllocatorList.h:23
RegSubRegPair(unsigned Reg=0, unsigned SubReg=0)
A Module instance is used to store all the information related to an LLVM module. ...
Definition: Module.h:65
virtual void setExecutionDomain(MachineInstr &MI, unsigned Domain) const
Change the opcode of MI to execute in Domain.
virtual bool DefinesPredicate(MachineInstr &MI, std::vector< MachineOperand > &Pred) const
If the specified instruction defines any predicate or condition code register(s) used for predication...
virtual bool optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg, unsigned SrcReg2, int Mask, int Value, const MachineRegisterInfo *MRI) const
See if the comparison instruction can be converted into something more efficient. ...
virtual bool isThroughputPattern(MachineCombinerPattern Pattern) const
Return true when a code sequence can improve throughput.
virtual bool isReallyTriviallyReMaterializable(const MachineInstr &MI, AliasAnalysis *AA) const
For instructions with opcodes for which the M_REMATERIALIZABLE flag is set, this hook lets the target...
int64_t getFrameTotalSize(const MachineInstr &I) const
Returns the total frame size, which is made up of the space set up inside the pair of frame start-sto...
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:164
virtual bool analyzeSelect(const MachineInstr &MI, SmallVectorImpl< MachineOperand > &Cond, unsigned &TrueOp, unsigned &FalseOp, bool &Optimizable) const
Analyze the given select instruction, returning true if it cannot be understood.
virtual bool getIncrementValue(const MachineInstr &MI, int &Value) const
If the instruction is an increment of a constant value, return the amount.
virtual MachineInstr & duplicate(MachineBasicBlock &MBB, MachineBasicBlock::iterator InsertBefore, const MachineInstr &Orig) const
Clones instruction or the whole instruction bundle Orig and insert into MBB before InsertBefore...
MachineInstr * commuteInstruction(MachineInstr &MI, bool NewMI=false, unsigned OpIdx1=CommuteAnyOperandIndex, unsigned OpIdx2=CommuteAnyOperandIndex) const
This method commutes the operands of the given machine instruction MI.
virtual bool hasReassociableOperands(const MachineInstr &Inst, const MachineBasicBlock *MBB) const
Return true when Inst has reassociable operands in the same MBB.
TargetInstrInfo(unsigned CFSetupOpcode=~0u, unsigned CFDestroyOpcode=~0u, unsigned CatchRetOpcode=~0u, unsigned ReturnOpcode=~0u)
virtual unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const
Insert branch code into the end of the specified MachineBasicBlock.
virtual bool useMachineCombiner() const
Return true when a target supports MachineCombiner.
virtual bool getExtractSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx, RegSubRegPairAndIdx &InputReg) const
Target-dependent implementation of getExtractSubregInputs.
unsigned const TargetRegisterInfo * TRI
A debug info location.
Definition: DebugLoc.h:33
unsigned getCallFrameDestroyOpcode() const
virtual MachineInstr * foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, int FrameIndex, LiveIntervals *LIS=nullptr, VirtRegMap *VRM=nullptr) const
Target-dependent implementation for foldMemoryOperand.
unsigned defaultDefLatency(const MCSchedModel &SchedModel, const MachineInstr &DefMI) const
Return the default expected latency for a def based on its opcode.
static bool isGenericOpcode(unsigned Opc)
virtual unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const
Remove the branching code at the end of the specific MBB.
An individual sequence of instructions to be replaced with a call to an outlined function.
virtual bool isHighLatencyDef(int opc) const
Return true if this opcode has high latency to its result.
Represents a predicate at the MachineFunction level.
virtual bool isUnpredicatedTerminator(const MachineInstr &MI) const
Returns true if the instruction is a terminator instruction that has not been predicated.
A templated base class for SmallPtrSet which provides the typesafe interface that is common across al...
Definition: SmallPtrSet.h:343
virtual unsigned getMachineCSELookAheadLimit() const
Return the value to use for the MachineCSE&#39;s LookAheadLimit, which is a heuristic used for CSE&#39;ing ph...
virtual unsigned isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex, unsigned &MemBytes) const
Optional extension of isLoadFromStackSlot that returns the number of bytes loaded from the stack...
virtual ArrayRef< std::pair< unsigned, const char * > > getSerializableBitmaskMachineOperandTargetFlags() const
Return an array that contains the bitmask target flag values and their names.
virtual unsigned getInstSizeInBytes(const MachineInstr &MI) const
Returns the size in bytes of the specified MachineInstr, or ~0U when this function is not implemented...
virtual void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, unsigned SubIdx, const MachineInstr &Orig, const TargetRegisterInfo &TRI) const
Re-issue the specified &#39;original&#39; instruction at the specific location targeting a new destination re...
virtual MachineBasicBlock::iterator insertOutlinedCall(Module &M, MachineBasicBlock &MBB, MachineBasicBlock::iterator &It, MachineFunction &MF, const outliner::Candidate &C) const
Insert a call to an outlined function into the program.
virtual unsigned getPartialRegUpdateClearance(const MachineInstr &MI, unsigned OpNum, const TargetRegisterInfo *TRI) const
Returns the preferred minimum clearance before an instruction with an unwanted partial register updat...
Provide an instruction scheduling machine model to CodeGen passes.
const TargetRegisterClass * getRegClass(const MCInstrDesc &MCID, unsigned OpNum, const TargetRegisterInfo *TRI, const MachineFunction &MF) const
Given a machine instruction descriptor, returns the register class constraint for OpNum...
virtual MachineInstr * foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, MachineInstr &LoadMI, LiveIntervals *LIS=nullptr) const
Target-dependent implementation for foldMemoryOperand.
virtual bool FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, unsigned Reg, MachineRegisterInfo *MRI) const
&#39;Reg&#39; is known to be defined by a move immediate instruction, try to fold the immediate into the use ...
virtual DFAPacketizer * CreateTargetScheduleState(const TargetSubtargetInfo &) const
Create machine specific model for scheduling.
virtual bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr &MI, unsigned Reg, bool UnfoldLoad, bool UnfoldStore, SmallVectorImpl< MachineInstr *> &NewMIs) const
unfoldMemoryOperand - Separate a single instruction which folded a load or a store or a load and a st...
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:41
bool operator!=(const RegSubRegPair &P) const
virtual bool hasLowDefLatency(const TargetSchedModel &SchedModel, const MachineInstr &DefMI, unsigned DefIdx) const
Compute operand latency of a def of &#39;Reg&#39;.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:410
virtual MachineInstr * convertToThreeAddress(MachineFunction::iterator &MFI, MachineInstr &MI, LiveVariables *LV) const
This method must be implemented by targets that set the M_CONVERTIBLE_TO_3_ADDR flag.
virtual bool isBasicBlockPrologue(const MachineInstr &MI) const
True if the instruction is bound to the top of its basic block and no other instructions shall be ins...
unsigned getCatchReturnOpcode() const
virtual bool shouldClusterMemOps(const MachineOperand &BaseOp1, const MachineOperand &BaseOp2, unsigned NumLoads) const
Returns true if the two given memory operations should be scheduled adjacent.
bool isSelect() const
Return true if this is a select instruction.
Definition: MCInstrDesc.h:321
virtual ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags() const
Return an array that contains the direct target flag values and their names.
virtual void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const
Emit instructions to copy a pair of physical registers.
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
Definition: MachineInstr.h:407
static bool isEqual(const Function &Caller, const Function &Callee)
virtual unsigned getInstrLatency(const InstrItineraryData *ItinData, const MachineInstr &MI, unsigned *PredCost=nullptr) const
Compute the instruction latency of a given instruction.
virtual bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N, SmallVectorImpl< SDNode *> &NewNodes) const
bool isRematerializable() const
Returns true if this instruction is a candidate for remat.
Definition: MCInstrDesc.h:486
virtual bool getMachineCombinerPatterns(MachineInstr &Root, SmallVectorImpl< MachineCombinerPattern > &Patterns) const
Return true when there is potentially a faster code sequence for an instruction chain ending in Root...
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:32
virtual bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, unsigned ExtraPredCycles, BranchProbability Probability) const
Return true if it&#39;s profitable to predicate instructions with accumulated instruction latency of "Num...
virtual unsigned isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const
If the specified machine instruction is a direct store to a stack slot, return the virtual or physica...
Itinerary data supplied by a subtarget to be used by a target.
virtual bool getBaseAndOffsetPosition(const MachineInstr &MI, unsigned &BasePos, unsigned &OffsetPos) const
Return true if the instruction contains a base register and offset.
virtual ArrayRef< std::pair< MachineMemOperand::Flags, const char * > > getSerializableMachineMemOperandTargetFlags() const
Return an array that contains the MMO target flag values and their names.
RegSubRegPairAndIdx(unsigned Reg=0, unsigned SubReg=0, unsigned SubIdx=0)
virtual unsigned getInlineAsmLength(const char *Str, const MCAsmInfo &MAI, const TargetSubtargetInfo *STI=nullptr) const
Measure the specified inline asm to determine an approximation of its length.
TargetInstrInfo & operator=(const TargetInstrInfo &)=delete
virtual MachineInstr * optimizeSelect(MachineInstr &MI, SmallPtrSetImpl< MachineInstr *> &NewMIs, bool PreferFalse=false) const
Given a select instruction that was understood by analyzeSelect and returned Optimizable = true...
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:158
BasicBlockListType::iterator iterator
virtual bool isFunctionSafeToOutlineFrom(MachineFunction &MF, bool OutlineFromLinkOnceODRs) const
Return true if the function can safely be outlined from.
TargetInstrInfo - Interface to description of machine instruction set.
bool isReturn(QueryType Type=AnyInBundle) const
Definition: MachineInstr.h:624
virtual void getNoop(MCInst &NopInst) const
Return the noop instruction to use for a noop.
This class is intended to be used as a base class for asm properties and features specific to the tar...
Definition: MCAsmInfo.h:56
virtual unsigned isStoreToStackSlotPostFE(const MachineInstr &MI, int &FrameIndex) const
Check for post-frame ptr elimination stack locations as well.
TargetInstrInfo::RegSubRegPair RegSubRegPair
virtual bool shouldOutlineFromFunctionByDefault(MachineFunction &MF) const
Return true if the function should be outlined from by default.
bool usePreRAHazardRecognizer() const
Provide a global flag for disabling the PreRA hazard recognizer that targets may choose to honor...
bool operator==(const RegSubRegPair &P) const
static const unsigned CommuteAnyOperandIndex
bool mayStore(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly modify memory.
Definition: MachineInstr.h:821
#define P(N)
virtual MachineInstr * commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned OpIdx1, unsigned OpIdx2) const
This method commutes the operands of the given machine instruction MI.
virtual void ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail, MachineBasicBlock *NewDest) const
Delete the instruction OldInst and everything after it, replacing it with an unconditional branch to ...
unsigned const MachineRegisterInfo * MRI
virtual bool isBranchOffsetInRange(unsigned BranchOpc, int64_t BrOffset) const
virtual unsigned getPredicationCost(const MachineInstr &MI) const
HazardRecognizer - This determines whether or not an instruction can be issued this cycle...
InstrType
Represents how an instruction should be mapped by the outliner.
virtual bool getInsertSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx, RegSubRegPair &BaseReg, RegSubRegPairAndIdx &InsertedReg) const
Target-dependent implementation of getInsertSubregInputs.
unsigned insertUnconditionalBranch(MachineBasicBlock &MBB, MachineBasicBlock *DestBB, const DebugLoc &DL, int *BytesAdded=nullptr) const
MachineInstrBuilder & UseMI
virtual bool isLegalToSplitMBBAt(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) const
Return true if it&#39;s legal to split the given basic block at the specified instruction (i...
virtual unsigned isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex, unsigned &MemBytes) const
Optional extension of isStoreToStackSlot that returns the number of bytes stored to the stack...
The information necessary to create an outlined function for some class of candidate.
virtual outliner::InstrType getOutliningType(MachineBasicBlock::iterator &MIT, unsigned Flags) const
Returns how or if MI should be outlined.
virtual unsigned getNumMicroOps(const InstrItineraryData *ItinData, const MachineInstr &MI) const
Return the number of u-operations the given machine instruction will be decoded to on the target cpu...
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:23
Contains all data structures shared between the outliner implemented in MachineOutliner.cpp and target implementations of the outliner.
virtual bool verifyInstruction(const MachineInstr &MI, StringRef &ErrInfo) const
Perform target-specific instruction verification.
unsigned getCallFrameSetupOpcode() const
These methods return the opcode of the frame setup/destroy instructions if they exist (-1 otherwise)...
virtual bool isMBBSafeToOutlineFrom(MachineBasicBlock &MBB, unsigned &Flags) const
Optional target hook that returns true if MBB is safe to outline from, and returns any target-specifi...
virtual ScheduleHazardRecognizer * CreateTargetPostRAHazardRecognizer(const MachineFunction &MF) const
Allocate and return a hazard recognizer to use for by non-scheduling passes.
bool isReassociationCandidate(const MachineInstr &Inst, bool &Commuted) const
Return true if the input Inst is part of a chain of dependent ops that are suitable for reassociatio...
virtual void setSpecialOperandAttr(MachineInstr &OldMI1, MachineInstr &OldMI2, MachineInstr &NewMI1, MachineInstr &NewMI2) const
This is an architecture-specific helper function of reassociateOps.
A set of register units.
bool isPredicable() const
Return true if this instruction has a predicate operand that controls execution.
Definition: MCInstrDesc.h:308
virtual bool shouldSink(const MachineInstr &MI) const
Return true if the instruction should be sunk by MachineSink.
MachineCombinerPattern
These are instruction patterns matched by the machine combiner pass.
virtual bool getStackSlotRange(const TargetRegisterClass *RC, unsigned SubIdx, unsigned &Size, unsigned &Offset, const MachineFunction &MF) const
Compute the size in bytes and offset within a stack slot of a spilled register or subregister...
bool isCopy() const
virtual bool PredicateInstruction(MachineInstr &MI, ArrayRef< MachineOperand > Pred) const
Convert the instruction into a predicated instruction.
virtual bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify=false) const
Analyze the branching code at the end of MBB, returning true if it cannot be understood (e...
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
virtual bool canMakeTailCallConditional(SmallVectorImpl< MachineOperand > &Cond, const MachineInstr &TailCall) const
Returns true if the tail call can be made conditional on BranchCond.
virtual bool isPredicated(const MachineInstr &MI) const
Returns true if the instruction is already predicated.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
virtual bool analyzeCompare(const MachineInstr &MI, unsigned &SrcReg, unsigned &SrcReg2, int &Mask, int &Value) const
For a comparison instruction, return the source registers in SrcReg and SrcReg2 if having two registe...
virtual bool isStackSlotCopy(const MachineInstr &MI, int &DestFrameIndex, int &SrcFrameIndex) const
Return true if the specified machine instruction is a copy of one stack slot to another and has no ot...
virtual bool isAsCheapAsAMove(const MachineInstr &MI) const
Return true if the instruction is as cheap as a move instruction.
virtual bool getMemOperandWithOffset(const MachineInstr &MI, const MachineOperand *&BaseOp, int64_t &Offset, const TargetRegisterInfo *TRI) const
Get the base operand and byte offset of an instruction that reads/writes memory.
virtual unsigned getAddressSpaceForPseudoSourceKind(unsigned Kind) const
getAddressSpaceForPseudoSourceKind - Given the kind of memory (e.g.
virtual bool hasLoadFromStackSlot(const MachineInstr &MI, SmallVectorImpl< const MachineMemOperand *> &Accesses) const
If the specified machine instruction has a load from a stack slot, return true along with the FrameIn...
virtual bool isSchedulingBoundary(const MachineInstr &MI, const MachineBasicBlock *MBB, const MachineFunction &MF) const
Test if the given instruction should be considered a scheduling boundary.
MachineInstr * foldMemoryOperand(MachineInstr &MI, ArrayRef< unsigned > Ops, int FI, LiveIntervals *LIS=nullptr, VirtRegMap *VRM=nullptr) const
Attempt to fold a load or store of the specified stack slot into the specified machine instruction fo...
virtual bool optimizeCondBranch(MachineInstr &MI) const
virtual void buildOutlinedFrame(MachineBasicBlock &MBB, MachineFunction &MF, const outliner::OutlinedFunction &OF) const
Insert a custom frame for outlined functions.
void reassociateOps(MachineInstr &Root, MachineInstr &Prev, MachineCombinerPattern Pattern, SmallVectorImpl< MachineInstr *> &InsInstrs, SmallVectorImpl< MachineInstr *> &DelInstrs, DenseMap< unsigned, unsigned > &InstrIdxForVirtReg) const
Attempt to reassociate Root and Prev according to Pattern to reduce critical path length...
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:221
MachineOperand class - Representation of each machine instruction operand.
A pair composed of a register and a sub-register index.
virtual bool hasHighOperandLatency(const TargetSchedModel &SchedModel, const MachineRegisterInfo *MRI, const MachineInstr &DefMI, unsigned DefIdx, const MachineInstr &UseMI, unsigned UseIdx) const
Compute operand latency between a def of &#39;Reg&#39; and a use in the current loop.
MachineInstrBuilder MachineInstrBuilder & DefMI
Predicate
Predicate - These are "(BI << 5) | BO" for various predicates.
Definition: PPCPredicates.h:26
bool isFrameInstr(const MachineInstr &I) const
Returns true if the argument is a frame pseudo instruction.
virtual bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, BranchProbability Probability) const
Return true if it&#39;s profitable for if-converter to duplicate instructions of specified accumulated in...
virtual bool isCoalescableExtInstr(const MachineInstr &MI, unsigned &SrcReg, unsigned &DstReg, unsigned &SubIdx) const
Return true if the instruction is a "coalescable" extension instruction.
Represents one node in the SelectionDAG.
virtual unsigned insertIndirectBranch(MachineBasicBlock &MBB, MachineBasicBlock &NewDestBB, const DebugLoc &DL, int64_t BrOffset=0, RegScavenger *RS=nullptr) const
Insert an unconditional indirect branch at the end of MBB to NewDestBB.
virtual bool isTailCall(const MachineInstr &Inst) const
Determines whether Inst is a tail call instruction.
int64_t getFrameSize(const MachineInstr &I) const
Returns size of the frame associated with the given frame instruction.
int64_t getImm() const
bool getRegSequenceInputs(const MachineInstr &MI, unsigned DefIdx, SmallVectorImpl< RegSubRegPairAndIdx > &InputRegs) const
Build the equivalent inputs of a REG_SEQUENCE for the given MI and DefIdx.
virtual bool findCommutedOpIndices(MachineInstr &MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) const
Returns true iff the routine could find two commutable operands in the given machine instruction...
virtual bool areMemAccessesTriviallyDisjoint(const MachineInstr &MIa, const MachineInstr &MIb, AliasAnalysis *AA=nullptr) const
Sometimes, it is possible for the target to tell, even without aliasing information, that two MIs access different memory addresses.
virtual bool isPredicable(const MachineInstr &MI) const
Return true if the specified instruction can be predicated.
unsigned getReturnOpcode() const
virtual void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const
Store the specified register of the given register class to the specified stack frame index...
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
TargetSubtargetInfo - Generic base class for all target subtargets.
virtual void insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const
Insert a noop into the instruction stream at the specified point.
Representation of each machine instruction.
Definition: MachineInstr.h:63
static TargetInstrInfo::RegSubRegPair getEmptyKey()
virtual ArrayRef< std::pair< int, const char * > > getSerializableTargetIndices() const
Return an array that contains the ids of the target indices (used for the TargetIndex machine operand...
virtual bool analyzeLoop(MachineLoop &L, MachineInstr *&IndVarInst, MachineInstr *&CmpInst) const
Analyze the loop code, return true if it cannot be understoo.
static bool fixCommutedOpIndices(unsigned &ResultIdx1, unsigned &ResultIdx2, unsigned CommutableOpIdx1, unsigned CommutableOpIdx2)
Assigns the (CommutableOpIdx1, CommutableOpIdx2) pair of commutable operand indices to (ResultIdx1...
bool isCopyInstr(const MachineInstr &MI, const MachineOperand *&Source, const MachineOperand *&Destination) const
If the specific machine instruction is a instruction that moves/copies value from one register to ano...
virtual bool hasStoreToStackSlot(const MachineInstr &MI, SmallVectorImpl< const MachineMemOperand *> &Accesses) const
If the specified machine instruction has a store to a stack slot, return true along with the FrameInd...
virtual bool SubsumesPredicate(ArrayRef< MachineOperand > Pred1, ArrayRef< MachineOperand > Pred2) const
Returns true if the first specified predicate subsumes the second, e.g.
virtual void breakPartialRegDependency(MachineInstr &MI, unsigned OpNum, const TargetRegisterInfo *TRI) const
Insert a dependency-breaking instruction before MI to eliminate an unwanted dependency on OpNum...
virtual ScheduleHazardRecognizer * CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI, const ScheduleDAG *DAG) const
Allocate and return a hazard recognizer to use for this target when scheduling the machine instructio...
virtual unsigned isLoadFromStackSlotPostFE(const MachineInstr &MI, int &FrameIndex) const
Check for post-frame ptr elimination stack locations as well.
virtual bool analyzeBranchPredicate(MachineBasicBlock &MBB, MachineBranchPredicate &MBP, bool AllowModify=false) const
Analyze the branching code at the end of MBB and parse it into the MachineBranchPredicate structure i...
virtual void genAlternativeCodeSequence(MachineInstr &Root, MachineCombinerPattern Pattern, SmallVectorImpl< MachineInstr *> &InsInstrs, SmallVectorImpl< MachineInstr *> &DelInstrs, DenseMap< unsigned, unsigned > &InstIdxForVirtReg) const
When getMachineCombinerPatterns() finds patterns, this function generates the instructions that could...
virtual unsigned isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const
If the specified machine instruction is a direct load from a stack slot, return the virtual or physic...
static MachineOperand CreateImm(int64_t Val)
#define I(x, y, z)
Definition: MD5.cpp:58
#define N
virtual bool produceSameValue(const MachineInstr &MI0, const MachineInstr &MI1, const MachineRegisterInfo *MRI=nullptr) const
Return true if two machine instructions would produce identical values.
bool isZeroCost(unsigned Opcode) const
Return true for pseudo instructions that don&#39;t consume any machine resources in their current form...
virtual std::pair< uint16_t, uint16_t > getExecutionDomain(const MachineInstr &MI) const
Return the current execution domain and bit mask of possible domains for instruction.
uint32_t Size
Definition: Profile.cpp:46
virtual MachineInstr * optimizeLoadInstr(MachineInstr &MI, const MachineRegisterInfo *MRI, unsigned &FoldAsLoadDefReg, MachineInstr *&DefMI) const
Try to remove the load by folding it to a register operand at the use.
virtual bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const
Reverses the branch condition of the specified condition list, returning false on success and true if...
virtual bool isSubregFoldable() const
Check whether the target can fold a load that feeds a subreg operand (or a subreg operand that feeds ...
bool mayLoad(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read memory.
Definition: MachineInstr.h:808
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
bool isFrameSetup(const MachineInstr &I) const
Returns true if the argument is a frame setup pseudo instruction.
virtual bool isProfitableToIfCvt(MachineBasicBlock &TMBB, unsigned NumTCycles, unsigned ExtraTCycles, MachineBasicBlock &FMBB, unsigned NumFCycles, unsigned ExtraFCycles, BranchProbability Probability) const
Second variant of isProfitableToIfCvt.
LLVM Value Representation.
Definition: Value.h:72
virtual MachineBasicBlock * getBranchDestBlock(const MachineInstr &MI) const
bool hasReassociableSibling(const MachineInstr &Inst, bool &Commuted) const
Return true when Inst has reassociable sibling.
virtual ScheduleHazardRecognizer * CreateTargetMIHazardRecognizer(const InstrItineraryData *, const ScheduleDAG *DAG) const
Allocate and return a hazard recognizer to use for this target when scheduling the machine instructio...
virtual bool isAssociativeAndCommutative(const MachineInstr &Inst) const
Return true when Inst is both associative and commutative.
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E&#39;s largest value.
Definition: BitmaskEnum.h:80
virtual void replaceBranchWithTailCall(MachineBasicBlock &MBB, SmallVectorImpl< MachineOperand > &Cond, const MachineInstr &TailCall) const
Replace the conditional branch in MBB with a conditional tail call.
IRTranslator LLVM IR MI
virtual bool isPostIncrement(const MachineInstr &MI) const
Return true for post-incremented instructions.
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:48
virtual bool isUnconditionalTailCall(const MachineInstr &MI) const
Returns true if MI is an unconditional tail call.
virtual bool getRegSequenceLikeInputs(const MachineInstr &MI, unsigned DefIdx, SmallVectorImpl< RegSubRegPairAndIdx > &InputRegs) const
Target-dependent implementation of getRegSequenceInputs.
bool getExtractSubregInputs(const MachineInstr &MI, unsigned DefIdx, RegSubRegPairAndIdx &InputReg) const
Build the equivalent inputs of a EXTRACT_SUBREG for the given MI and DefIdx.
virtual bool canCopyGluedNodeDuringSchedule(SDNode *N) const
Return true if the given SDNode can be copied during scheduling even if it has glue.
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:415
bool isTriviallyReMaterializable(const MachineInstr &MI, AliasAnalysis *AA=nullptr) const
Return true if the instruction is trivially rematerializable, meaning it has no side effects and requ...
virtual outliner::OutlinedFunction getOutliningCandidateInfo(std::vector< outliner::Candidate > &RepeatedSequenceLocs) const
Returns a outliner::OutlinedFunction struct containing target-specific information for a set of outli...
Machine model for scheduling, bundling, and heuristics.
Definition: MCSchedule.h:244
static bool isEqual(const TargetInstrInfo::RegSubRegPair &LHS, const TargetInstrInfo::RegSubRegPair &RHS)
bool getInsertSubregInputs(const MachineInstr &MI, unsigned DefIdx, RegSubRegPair &BaseReg, RegSubRegPairAndIdx &InsertedReg) const
Build the equivalent inputs of a INSERT_SUBREG for the given MI and DefIdx.
virtual ScheduleHazardRecognizer * CreateTargetPostRAHazardRecognizer(const InstrItineraryData *, const ScheduleDAG *DAG) const
Allocate and return a hazard recognizer to use for this target when scheduling the machine instructio...
virtual bool isProfitableToUnpredicate(MachineBasicBlock &TMBB, MachineBasicBlock &FMBB) const
Return true if it&#39;s profitable to unpredicate one side of a &#39;diamond&#39;, i.e.
int computeDefOperandLatency(const InstrItineraryData *ItinData, const MachineInstr &DefMI) const
If we can determine the operand latency from the def only, without itinerary lookup, do so.
virtual unsigned getOpcodeAfterMemoryUnfold(unsigned Opc, bool UnfoldLoad, bool UnfoldStore, unsigned *LoadRegIndex=nullptr) const
Returns the opcode of the would be new instruction after load / store are unfolded from an instructio...
virtual int getOperandLatency(const InstrItineraryData *ItinData, SDNode *DefNode, unsigned DefIdx, SDNode *UseNode, unsigned UseIdx) const
virtual void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const
Load the specified register of the given register class from the specified stack frame index...
bool isAsCheapAsAMove(QueryType Type=AllInBundle) const
Returns true if this instruction has the same cost (or less) than a move instruction.
Definition: MachineInstr.h:918
virtual bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, int64_t Offset1, int64_t Offset2, unsigned NumLoads) const
This is a used by the pre-regalloc scheduler to determine (in conjunction with areLoadsFromSameBasePt...
virtual int getSPAdjust(const MachineInstr &MI) const
Returns the actual stack pointer adjustment made by an instruction as part of a call sequence...
virtual unsigned getUndefRegClearance(const MachineInstr &MI, unsigned &OpNum, const TargetRegisterInfo *TRI) const
Return the minimum clearance before an instruction that reads an unused register. ...
A pair composed of a pair of a register and a sub-register index, and another sub-register index...