LLVM  7.0.0svn
TargetInstrInfo.h
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1 //===- llvm/CodeGen/TargetInstrInfo.h - Instruction Info --------*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file describes the target machine instruction set to the code generator.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_TARGET_TARGETINSTRINFO_H
15 #define LLVM_TARGET_TARGETINSTRINFO_H
16 
17 #include "llvm/ADT/ArrayRef.h"
18 #include "llvm/ADT/DenseMap.h"
19 #include "llvm/ADT/DenseMapInfo.h"
20 #include "llvm/ADT/None.h"
28 #include "llvm/MC/MCInstrInfo.h"
31 #include <cassert>
32 #include <cstddef>
33 #include <cstdint>
34 #include <utility>
35 #include <vector>
36 
37 namespace llvm {
38 
39 class DFAPacketizer;
40 class InstrItineraryData;
41 class LiveIntervals;
42 class LiveVariables;
43 class MachineMemOperand;
44 class MachineRegisterInfo;
45 class MCAsmInfo;
46 class MCInst;
47 struct MCSchedModel;
48 class Module;
49 class ScheduleDAG;
50 class ScheduleHazardRecognizer;
51 class SDNode;
52 class SelectionDAG;
53 class RegScavenger;
54 class TargetRegisterClass;
55 class TargetRegisterInfo;
56 class TargetSchedModel;
57 class TargetSubtargetInfo;
58 
59 template <class T> class SmallVectorImpl;
60 
61 //---------------------------------------------------------------------------
62 ///
63 /// TargetInstrInfo - Interface to description of machine instruction set
64 ///
65 class TargetInstrInfo : public MCInstrInfo {
66 public:
67  TargetInstrInfo(unsigned CFSetupOpcode = ~0u, unsigned CFDestroyOpcode = ~0u,
68  unsigned CatchRetOpcode = ~0u, unsigned ReturnOpcode = ~0u)
69  : CallFrameSetupOpcode(CFSetupOpcode),
70  CallFrameDestroyOpcode(CFDestroyOpcode), CatchRetOpcode(CatchRetOpcode),
71  ReturnOpcode(ReturnOpcode) {}
72  TargetInstrInfo(const TargetInstrInfo &) = delete;
73  TargetInstrInfo &operator=(const TargetInstrInfo &) = delete;
74  virtual ~TargetInstrInfo();
75 
76  static bool isGenericOpcode(unsigned Opc) {
77  return Opc <= TargetOpcode::GENERIC_OP_END;
78  }
79 
80  /// Given a machine instruction descriptor, returns the register
81  /// class constraint for OpNum, or NULL.
82  const TargetRegisterClass *getRegClass(const MCInstrDesc &TID, unsigned OpNum,
83  const TargetRegisterInfo *TRI,
84  const MachineFunction &MF) const;
85 
86  /// Return true if the instruction is trivially rematerializable, meaning it
87  /// has no side effects and requires no operands that aren't always available.
88  /// This means the only allowed uses are constants and unallocatable physical
89  /// registers so that the instructions result is independent of the place
90  /// in the function.
92  AliasAnalysis *AA = nullptr) const {
93  return MI.getOpcode() == TargetOpcode::IMPLICIT_DEF ||
94  (MI.getDesc().isRematerializable() &&
96  isReallyTriviallyReMaterializableGeneric(MI, AA)));
97  }
98 
99 protected:
100  /// For instructions with opcodes for which the M_REMATERIALIZABLE flag is
101  /// set, this hook lets the target specify whether the instruction is actually
102  /// trivially rematerializable, taking into consideration its operands. This
103  /// predicate must return false if the instruction has any side effects other
104  /// than producing a value, or if it requres any address registers that are
105  /// not always available.
106  /// Requirements must be check as stated in isTriviallyReMaterializable() .
108  AliasAnalysis *AA) const {
109  return false;
110  }
111 
112  /// This method commutes the operands of the given machine instruction MI.
113  /// The operands to be commuted are specified by their indices OpIdx1 and
114  /// OpIdx2.
115  ///
116  /// If a target has any instructions that are commutable but require
117  /// converting to different instructions or making non-trivial changes
118  /// to commute them, this method can be overloaded to do that.
119  /// The default implementation simply swaps the commutable operands.
120  ///
121  /// If NewMI is false, MI is modified in place and returned; otherwise, a
122  /// new machine instruction is created and returned.
123  ///
124  /// Do not call this method for a non-commutable instruction.
125  /// Even though the instruction is commutable, the method may still
126  /// fail to commute the operands, null pointer is returned in such cases.
127  virtual MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI,
128  unsigned OpIdx1,
129  unsigned OpIdx2) const;
130 
131  /// Assigns the (CommutableOpIdx1, CommutableOpIdx2) pair of commutable
132  /// operand indices to (ResultIdx1, ResultIdx2).
133  /// One or both input values of the pair: (ResultIdx1, ResultIdx2) may be
134  /// predefined to some indices or be undefined (designated by the special
135  /// value 'CommuteAnyOperandIndex').
136  /// The predefined result indices cannot be re-defined.
137  /// The function returns true iff after the result pair redefinition
138  /// the fixed result pair is equal to or equivalent to the source pair of
139  /// indices: (CommutableOpIdx1, CommutableOpIdx2). It is assumed here that
140  /// the pairs (x,y) and (y,x) are equivalent.
141  static bool fixCommutedOpIndices(unsigned &ResultIdx1, unsigned &ResultIdx2,
142  unsigned CommutableOpIdx1,
143  unsigned CommutableOpIdx2);
144 
145 private:
146  /// For instructions with opcodes for which the M_REMATERIALIZABLE flag is
147  /// set and the target hook isReallyTriviallyReMaterializable returns false,
148  /// this function does target-independent tests to determine if the
149  /// instruction is really trivially rematerializable.
150  bool isReallyTriviallyReMaterializableGeneric(const MachineInstr &MI,
151  AliasAnalysis *AA) const;
152 
153 public:
154  /// These methods return the opcode of the frame setup/destroy instructions
155  /// if they exist (-1 otherwise). Some targets use pseudo instructions in
156  /// order to abstract away the difference between operating with a frame
157  /// pointer and operating without, through the use of these two instructions.
158  ///
159  unsigned getCallFrameSetupOpcode() const { return CallFrameSetupOpcode; }
160  unsigned getCallFrameDestroyOpcode() const { return CallFrameDestroyOpcode; }
161 
162  /// Returns true if the argument is a frame pseudo instruction.
163  bool isFrameInstr(const MachineInstr &I) const {
164  return I.getOpcode() == getCallFrameSetupOpcode() ||
166  }
167 
168  /// Returns true if the argument is a frame setup pseudo instruction.
169  bool isFrameSetup(const MachineInstr &I) const {
170  return I.getOpcode() == getCallFrameSetupOpcode();
171  }
172 
173  /// Returns size of the frame associated with the given frame instruction.
174  /// For frame setup instruction this is frame that is set up space set up
175  /// after the instruction. For frame destroy instruction this is the frame
176  /// freed by the caller.
177  /// Note, in some cases a call frame (or a part of it) may be prepared prior
178  /// to the frame setup instruction. It occurs in the calls that involve
179  /// inalloca arguments. This function reports only the size of the frame part
180  /// that is set up between the frame setup and destroy pseudo instructions.
181  int64_t getFrameSize(const MachineInstr &I) const {
182  assert(isFrameInstr(I) && "Not a frame instruction");
183  assert(I.getOperand(0).getImm() >= 0);
184  return I.getOperand(0).getImm();
185  }
186 
187  /// Returns the total frame size, which is made up of the space set up inside
188  /// the pair of frame start-stop instructions and the space that is set up
189  /// prior to the pair.
190  int64_t getFrameTotalSize(const MachineInstr &I) const {
191  if (isFrameSetup(I)) {
192  assert(I.getOperand(1).getImm() >= 0 &&
193  "Frame size must not be negative");
194  return getFrameSize(I) + I.getOperand(1).getImm();
195  }
196  return getFrameSize(I);
197  }
198 
199  unsigned getCatchReturnOpcode() const { return CatchRetOpcode; }
200  unsigned getReturnOpcode() const { return ReturnOpcode; }
201 
202  /// Returns the actual stack pointer adjustment made by an instruction
203  /// as part of a call sequence. By default, only call frame setup/destroy
204  /// instructions adjust the stack, but targets may want to override this
205  /// to enable more fine-grained adjustment, or adjust by a different value.
206  virtual int getSPAdjust(const MachineInstr &MI) const;
207 
208  /// Return true if the instruction is a "coalescable" extension instruction.
209  /// That is, it's like a copy where it's legal for the source to overlap the
210  /// destination. e.g. X86::MOVSX64rr32. If this returns true, then it's
211  /// expected the pre-extension value is available as a subreg of the result
212  /// register. This also returns the sub-register index in SubIdx.
213  virtual bool isCoalescableExtInstr(const MachineInstr &MI, unsigned &SrcReg,
214  unsigned &DstReg, unsigned &SubIdx) const {
215  return false;
216  }
217 
218  /// If the specified machine instruction is a direct
219  /// load from a stack slot, return the virtual or physical register number of
220  /// the destination along with the FrameIndex of the loaded stack slot. If
221  /// not, return 0. This predicate must return 0 if the instruction has
222  /// any side effects other than loading from the stack slot.
223  virtual unsigned isLoadFromStackSlot(const MachineInstr &MI,
224  int &FrameIndex) const {
225  return 0;
226  }
227 
228  /// Check for post-frame ptr elimination stack locations as well.
229  /// This uses a heuristic so it isn't reliable for correctness.
230  virtual unsigned isLoadFromStackSlotPostFE(const MachineInstr &MI,
231  int &FrameIndex) const {
232  return 0;
233  }
234 
235  /// If the specified machine instruction has a load from a stack slot,
236  /// return true along with the FrameIndex of the loaded stack slot and the
237  /// machine mem operand containing the reference.
238  /// If not, return false. Unlike isLoadFromStackSlot, this returns true for
239  /// any instructions that loads from the stack. This is just a hint, as some
240  /// cases may be missed.
241  virtual bool hasLoadFromStackSlot(const MachineInstr &MI,
242  const MachineMemOperand *&MMO,
243  int &FrameIndex) const;
244 
245  /// If the specified machine instruction is a direct
246  /// store to a stack slot, return the virtual or physical register number of
247  /// the source reg along with the FrameIndex of the loaded stack slot. If
248  /// not, return 0. This predicate must return 0 if the instruction has
249  /// any side effects other than storing to the stack slot.
250  virtual unsigned isStoreToStackSlot(const MachineInstr &MI,
251  int &FrameIndex) const {
252  return 0;
253  }
254 
255  /// Check for post-frame ptr elimination stack locations as well.
256  /// This uses a heuristic, so it isn't reliable for correctness.
257  virtual unsigned isStoreToStackSlotPostFE(const MachineInstr &MI,
258  int &FrameIndex) const {
259  return 0;
260  }
261 
262  /// If the specified machine instruction has a store to a stack slot,
263  /// return true along with the FrameIndex of the loaded stack slot and the
264  /// machine mem operand containing the reference.
265  /// If not, return false. Unlike isStoreToStackSlot,
266  /// this returns true for any instructions that stores to the
267  /// stack. This is just a hint, as some cases may be missed.
268  virtual bool hasStoreToStackSlot(const MachineInstr &MI,
269  const MachineMemOperand *&MMO,
270  int &FrameIndex) const;
271 
272  /// Return true if the specified machine instruction
273  /// is a copy of one stack slot to another and has no other effect.
274  /// Provide the identity of the two frame indices.
275  virtual bool isStackSlotCopy(const MachineInstr &MI, int &DestFrameIndex,
276  int &SrcFrameIndex) const {
277  return false;
278  }
279 
280  /// Compute the size in bytes and offset within a stack slot of a spilled
281  /// register or subregister.
282  ///
283  /// \param [out] Size in bytes of the spilled value.
284  /// \param [out] Offset in bytes within the stack slot.
285  /// \returns true if both Size and Offset are successfully computed.
286  ///
287  /// Not all subregisters have computable spill slots. For example,
288  /// subregisters registers may not be byte-sized, and a pair of discontiguous
289  /// subregisters has no single offset.
290  ///
291  /// Targets with nontrivial bigendian implementations may need to override
292  /// this, particularly to support spilled vector registers.
293  virtual bool getStackSlotRange(const TargetRegisterClass *RC, unsigned SubIdx,
294  unsigned &Size, unsigned &Offset,
295  const MachineFunction &MF) const;
296 
297  /// Returns the size in bytes of the specified MachineInstr, or ~0U
298  /// when this function is not implemented by a target.
299  virtual unsigned getInstSizeInBytes(const MachineInstr &MI) const {
300  return ~0U;
301  }
302 
303  /// Return true if the instruction is as cheap as a move instruction.
304  ///
305  /// Targets for different archs need to override this, and different
306  /// micro-architectures can also be finely tuned inside.
307  virtual bool isAsCheapAsAMove(const MachineInstr &MI) const {
308  return MI.isAsCheapAsAMove();
309  }
310 
311  /// Return true if the instruction should be sunk by MachineSink.
312  ///
313  /// MachineSink determines on its own whether the instruction is safe to sink;
314  /// this gives the target a hook to override the default behavior with regards
315  /// to which instructions should be sunk.
316  virtual bool shouldSink(const MachineInstr &MI) const { return true; }
317 
318  /// Re-issue the specified 'original' instruction at the
319  /// specific location targeting a new destination register.
320  /// The register in Orig->getOperand(0).getReg() will be substituted by
321  /// DestReg:SubIdx. Any existing subreg index is preserved or composed with
322  /// SubIdx.
323  virtual void reMaterialize(MachineBasicBlock &MBB,
324  MachineBasicBlock::iterator MI, unsigned DestReg,
325  unsigned SubIdx, const MachineInstr &Orig,
326  const TargetRegisterInfo &TRI) const;
327 
328  /// \brief Clones instruction or the whole instruction bundle \p Orig and
329  /// insert into \p MBB before \p InsertBefore. The target may update operands
330  /// that are required to be unique.
331  ///
332  /// \p Orig must not return true for MachineInstr::isNotDuplicable().
334  MachineBasicBlock::iterator InsertBefore,
335  const MachineInstr &Orig) const;
336 
337  /// This method must be implemented by targets that
338  /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
339  /// may be able to convert a two-address instruction into one or more true
340  /// three-address instructions on demand. This allows the X86 target (for
341  /// example) to convert ADD and SHL instructions into LEA instructions if they
342  /// would require register copies due to two-addressness.
343  ///
344  /// This method returns a null pointer if the transformation cannot be
345  /// performed, otherwise it returns the last new instruction.
346  ///
348  MachineInstr &MI,
349  LiveVariables *LV) const {
350  return nullptr;
351  }
352 
353  // This constant can be used as an input value of operand index passed to
354  // the method findCommutedOpIndices() to tell the method that the
355  // corresponding operand index is not pre-defined and that the method
356  // can pick any commutable operand.
357  static const unsigned CommuteAnyOperandIndex = ~0U;
358 
359  /// This method commutes the operands of the given machine instruction MI.
360  ///
361  /// The operands to be commuted are specified by their indices OpIdx1 and
362  /// OpIdx2. OpIdx1 and OpIdx2 arguments may be set to a special value
363  /// 'CommuteAnyOperandIndex', which means that the method is free to choose
364  /// any arbitrarily chosen commutable operand. If both arguments are set to
365  /// 'CommuteAnyOperandIndex' then the method looks for 2 different commutable
366  /// operands; then commutes them if such operands could be found.
367  ///
368  /// If NewMI is false, MI is modified in place and returned; otherwise, a
369  /// new machine instruction is created and returned.
370  ///
371  /// Do not call this method for a non-commutable instruction or
372  /// for non-commuable operands.
373  /// Even though the instruction is commutable, the method may still
374  /// fail to commute the operands, null pointer is returned in such cases.
375  MachineInstr *
376  commuteInstruction(MachineInstr &MI, bool NewMI = false,
377  unsigned OpIdx1 = CommuteAnyOperandIndex,
378  unsigned OpIdx2 = CommuteAnyOperandIndex) const;
379 
380  /// Returns true iff the routine could find two commutable operands in the
381  /// given machine instruction.
382  /// The 'SrcOpIdx1' and 'SrcOpIdx2' are INPUT and OUTPUT arguments.
383  /// If any of the INPUT values is set to the special value
384  /// 'CommuteAnyOperandIndex' then the method arbitrarily picks a commutable
385  /// operand, then returns its index in the corresponding argument.
386  /// If both of INPUT values are set to 'CommuteAnyOperandIndex' then method
387  /// looks for 2 commutable operands.
388  /// If INPUT values refer to some operands of MI, then the method simply
389  /// returns true if the corresponding operands are commutable and returns
390  /// false otherwise.
391  ///
392  /// For example, calling this method this way:
393  /// unsigned Op1 = 1, Op2 = CommuteAnyOperandIndex;
394  /// findCommutedOpIndices(MI, Op1, Op2);
395  /// can be interpreted as a query asking to find an operand that would be
396  /// commutable with the operand#1.
397  virtual bool findCommutedOpIndices(MachineInstr &MI, unsigned &SrcOpIdx1,
398  unsigned &SrcOpIdx2) const;
399 
400  /// A pair composed of a register and a sub-register index.
401  /// Used to give some type checking when modeling Reg:SubReg.
402  struct RegSubRegPair {
403  unsigned Reg;
404  unsigned SubReg;
405 
406  RegSubRegPair(unsigned Reg = 0, unsigned SubReg = 0)
407  : Reg(Reg), SubReg(SubReg) {}
408  };
409 
410  /// A pair composed of a pair of a register and a sub-register index,
411  /// and another sub-register index.
412  /// Used to give some type checking when modeling Reg:SubReg1, SubReg2.
414  unsigned SubIdx;
415 
416  RegSubRegPairAndIdx(unsigned Reg = 0, unsigned SubReg = 0,
417  unsigned SubIdx = 0)
418  : RegSubRegPair(Reg, SubReg), SubIdx(SubIdx) {}
419  };
420 
421  /// Build the equivalent inputs of a REG_SEQUENCE for the given \p MI
422  /// and \p DefIdx.
423  /// \p [out] InputRegs of the equivalent REG_SEQUENCE. Each element of
424  /// the list is modeled as <Reg:SubReg, SubIdx>. Operands with the undef
425  /// flag are not added to this list.
426  /// E.g., REG_SEQUENCE %1:sub1, sub0, %2, sub1 would produce
427  /// two elements:
428  /// - %1:sub1, sub0
429  /// - %2<:0>, sub1
430  ///
431  /// \returns true if it is possible to build such an input sequence
432  /// with the pair \p MI, \p DefIdx. False otherwise.
433  ///
434  /// \pre MI.isRegSequence() or MI.isRegSequenceLike().
435  ///
436  /// \note The generic implementation does not provide any support for
437  /// MI.isRegSequenceLike(). In other words, one has to override
438  /// getRegSequenceLikeInputs for target specific instructions.
439  bool
440  getRegSequenceInputs(const MachineInstr &MI, unsigned DefIdx,
441  SmallVectorImpl<RegSubRegPairAndIdx> &InputRegs) const;
442 
443  /// Build the equivalent inputs of a EXTRACT_SUBREG for the given \p MI
444  /// and \p DefIdx.
445  /// \p [out] InputReg of the equivalent EXTRACT_SUBREG.
446  /// E.g., EXTRACT_SUBREG %1:sub1, sub0, sub1 would produce:
447  /// - %1:sub1, sub0
448  ///
449  /// \returns true if it is possible to build such an input sequence
450  /// with the pair \p MI, \p DefIdx and the operand has no undef flag set.
451  /// False otherwise.
452  ///
453  /// \pre MI.isExtractSubreg() or MI.isExtractSubregLike().
454  ///
455  /// \note The generic implementation does not provide any support for
456  /// MI.isExtractSubregLike(). In other words, one has to override
457  /// getExtractSubregLikeInputs for target specific instructions.
458  bool getExtractSubregInputs(const MachineInstr &MI, unsigned DefIdx,
459  RegSubRegPairAndIdx &InputReg) const;
460 
461  /// Build the equivalent inputs of a INSERT_SUBREG for the given \p MI
462  /// and \p DefIdx.
463  /// \p [out] BaseReg and \p [out] InsertedReg contain
464  /// the equivalent inputs of INSERT_SUBREG.
465  /// E.g., INSERT_SUBREG %0:sub0, %1:sub1, sub3 would produce:
466  /// - BaseReg: %0:sub0
467  /// - InsertedReg: %1:sub1, sub3
468  ///
469  /// \returns true if it is possible to build such an input sequence
470  /// with the pair \p MI, \p DefIdx and the operand has no undef flag set.
471  /// False otherwise.
472  ///
473  /// \pre MI.isInsertSubreg() or MI.isInsertSubregLike().
474  ///
475  /// \note The generic implementation does not provide any support for
476  /// MI.isInsertSubregLike(). In other words, one has to override
477  /// getInsertSubregLikeInputs for target specific instructions.
478  bool getInsertSubregInputs(const MachineInstr &MI, unsigned DefIdx,
479  RegSubRegPair &BaseReg,
480  RegSubRegPairAndIdx &InsertedReg) const;
481 
482  /// Return true if two machine instructions would produce identical values.
483  /// By default, this is only true when the two instructions
484  /// are deemed identical except for defs. If this function is called when the
485  /// IR is still in SSA form, the caller can pass the MachineRegisterInfo for
486  /// aggressive checks.
487  virtual bool produceSameValue(const MachineInstr &MI0,
488  const MachineInstr &MI1,
489  const MachineRegisterInfo *MRI = nullptr) const;
490 
491  /// \returns true if a branch from an instruction with opcode \p BranchOpc
492  /// bytes is capable of jumping to a position \p BrOffset bytes away.
493  virtual bool isBranchOffsetInRange(unsigned BranchOpc,
494  int64_t BrOffset) const {
495  llvm_unreachable("target did not implement");
496  }
497 
498  /// \returns The block that branch instruction \p MI jumps to.
500  llvm_unreachable("target did not implement");
501  }
502 
503  /// Insert an unconditional indirect branch at the end of \p MBB to \p
504  /// NewDestBB. \p BrOffset indicates the offset of \p NewDestBB relative to
505  /// the offset of the position to insert the new branch.
506  ///
507  /// \returns The number of bytes added to the block.
509  MachineBasicBlock &NewDestBB,
510  const DebugLoc &DL,
511  int64_t BrOffset = 0,
512  RegScavenger *RS = nullptr) const {
513  llvm_unreachable("target did not implement");
514  }
515 
516  /// Analyze the branching code at the end of MBB, returning
517  /// true if it cannot be understood (e.g. it's a switch dispatch or isn't
518  /// implemented for a target). Upon success, this returns false and returns
519  /// with the following information in various cases:
520  ///
521  /// 1. If this block ends with no branches (it just falls through to its succ)
522  /// just return false, leaving TBB/FBB null.
523  /// 2. If this block ends with only an unconditional branch, it sets TBB to be
524  /// the destination block.
525  /// 3. If this block ends with a conditional branch and it falls through to a
526  /// successor block, it sets TBB to be the branch destination block and a
527  /// list of operands that evaluate the condition. These operands can be
528  /// passed to other TargetInstrInfo methods to create new branches.
529  /// 4. If this block ends with a conditional branch followed by an
530  /// unconditional branch, it returns the 'true' destination in TBB, the
531  /// 'false' destination in FBB, and a list of operands that evaluate the
532  /// condition. These operands can be passed to other TargetInstrInfo
533  /// methods to create new branches.
534  ///
535  /// Note that removeBranch and insertBranch must be implemented to support
536  /// cases where this method returns success.
537  ///
538  /// If AllowModify is true, then this routine is allowed to modify the basic
539  /// block (e.g. delete instructions after the unconditional branch).
540  ///
541  /// The CFG information in MBB.Predecessors and MBB.Successors must be valid
542  /// before calling this function.
544  MachineBasicBlock *&FBB,
546  bool AllowModify = false) const {
547  return true;
548  }
549 
550  /// Represents a predicate at the MachineFunction level. The control flow a
551  /// MachineBranchPredicate represents is:
552  ///
553  /// Reg = LHS `Predicate` RHS == ConditionDef
554  /// if Reg then goto TrueDest else goto FalseDest
555  ///
558  PRED_EQ, // True if two values are equal
559  PRED_NE, // True if two values are not equal
560  PRED_INVALID // Sentinel value
561  };
562 
563  ComparePredicate Predicate = PRED_INVALID;
566  MachineBasicBlock *TrueDest = nullptr;
567  MachineBasicBlock *FalseDest = nullptr;
568  MachineInstr *ConditionDef = nullptr;
569 
570  /// SingleUseCondition is true if ConditionDef is dead except for the
571  /// branch(es) at the end of the basic block.
572  ///
573  bool SingleUseCondition = false;
574 
575  explicit MachineBranchPredicate() = default;
576  };
577 
578  /// Analyze the branching code at the end of MBB and parse it into the
579  /// MachineBranchPredicate structure if possible. Returns false on success
580  /// and true on failure.
581  ///
582  /// If AllowModify is true, then this routine is allowed to modify the basic
583  /// block (e.g. delete instructions after the unconditional branch).
584  ///
587  bool AllowModify = false) const {
588  return true;
589  }
590 
591  /// Remove the branching code at the end of the specific MBB.
592  /// This is only invoked in cases where AnalyzeBranch returns success. It
593  /// returns the number of instructions that were removed.
594  /// If \p BytesRemoved is non-null, report the change in code size from the
595  /// removed instructions.
596  virtual unsigned removeBranch(MachineBasicBlock &MBB,
597  int *BytesRemoved = nullptr) const {
598  llvm_unreachable("Target didn't implement TargetInstrInfo::removeBranch!");
599  }
600 
601  /// Insert branch code into the end of the specified MachineBasicBlock. The
602  /// operands to this method are the same as those returned by AnalyzeBranch.
603  /// This is only invoked in cases where AnalyzeBranch returns success. It
604  /// returns the number of instructions inserted. If \p BytesAdded is non-null,
605  /// report the change in code size from the added instructions.
606  ///
607  /// It is also invoked by tail merging to add unconditional branches in
608  /// cases where AnalyzeBranch doesn't apply because there was no original
609  /// branch to analyze. At least this much must be implemented, else tail
610  /// merging needs to be disabled.
611  ///
612  /// The CFG information in MBB.Predecessors and MBB.Successors must be valid
613  /// before calling this function.
614  virtual unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
615  MachineBasicBlock *FBB,
617  const DebugLoc &DL,
618  int *BytesAdded = nullptr) const {
619  llvm_unreachable("Target didn't implement TargetInstrInfo::insertBranch!");
620  }
621 
623  MachineBasicBlock *DestBB,
624  const DebugLoc &DL,
625  int *BytesAdded = nullptr) const {
626  return insertBranch(MBB, DestBB, nullptr, ArrayRef<MachineOperand>(), DL,
627  BytesAdded);
628  }
629 
630  /// Analyze the loop code, return true if it cannot be understoo. Upon
631  /// success, this function returns false and returns information about the
632  /// induction variable and compare instruction used at the end.
633  virtual bool analyzeLoop(MachineLoop &L, MachineInstr *&IndVarInst,
634  MachineInstr *&CmpInst) const {
635  return true;
636  }
637 
638  /// Generate code to reduce the loop iteration by one and check if the loop is
639  /// finished. Return the value/register of the the new loop count. We need
640  /// this function when peeling off one or more iterations of a loop. This
641  /// function assumes the nth iteration is peeled first.
642  virtual unsigned reduceLoopCount(MachineBasicBlock &MBB, MachineInstr *IndVar,
643  MachineInstr &Cmp,
646  unsigned Iter, unsigned MaxIter) const {
647  llvm_unreachable("Target didn't implement ReduceLoopCount");
648  }
649 
650  /// Delete the instruction OldInst and everything after it, replacing it with
651  /// an unconditional branch to NewDest. This is used by the tail merging pass.
653  MachineBasicBlock *NewDest) const;
654 
655  /// Return true if it's legal to split the given basic
656  /// block at the specified instruction (i.e. instruction would be the start
657  /// of a new basic block).
659  MachineBasicBlock::iterator MBBI) const {
660  return true;
661  }
662 
663  /// Return true if it's profitable to predicate
664  /// instructions with accumulated instruction latency of "NumCycles"
665  /// of the specified basic block, where the probability of the instructions
666  /// being executed is given by Probability, and Confidence is a measure
667  /// of our confidence that it will be properly predicted.
668  virtual bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
669  unsigned ExtraPredCycles,
670  BranchProbability Probability) const {
671  return false;
672  }
673 
674  /// Second variant of isProfitableToIfCvt. This one
675  /// checks for the case where two basic blocks from true and false path
676  /// of a if-then-else (diamond) are predicated on mutally exclusive
677  /// predicates, where the probability of the true path being taken is given
678  /// by Probability, and Confidence is a measure of our confidence that it
679  /// will be properly predicted.
680  virtual bool isProfitableToIfCvt(MachineBasicBlock &TMBB, unsigned NumTCycles,
681  unsigned ExtraTCycles,
682  MachineBasicBlock &FMBB, unsigned NumFCycles,
683  unsigned ExtraFCycles,
684  BranchProbability Probability) const {
685  return false;
686  }
687 
688  /// Return true if it's profitable for if-converter to duplicate instructions
689  /// of specified accumulated instruction latencies in the specified MBB to
690  /// enable if-conversion.
691  /// The probability of the instructions being executed is given by
692  /// Probability, and Confidence is a measure of our confidence that it
693  /// will be properly predicted.
695  unsigned NumCycles,
696  BranchProbability Probability) const {
697  return false;
698  }
699 
700  /// Return true if it's profitable to unpredicate
701  /// one side of a 'diamond', i.e. two sides of if-else predicated on mutually
702  /// exclusive predicates.
703  /// e.g.
704  /// subeq r0, r1, #1
705  /// addne r0, r1, #1
706  /// =>
707  /// sub r0, r1, #1
708  /// addne r0, r1, #1
709  ///
710  /// This may be profitable is conditional instructions are always executed.
712  MachineBasicBlock &FMBB) const {
713  return false;
714  }
715 
716  /// Return true if it is possible to insert a select
717  /// instruction that chooses between TrueReg and FalseReg based on the
718  /// condition code in Cond.
719  ///
720  /// When successful, also return the latency in cycles from TrueReg,
721  /// FalseReg, and Cond to the destination register. In most cases, a select
722  /// instruction will be 1 cycle, so CondCycles = TrueCycles = FalseCycles = 1
723  ///
724  /// Some x86 implementations have 2-cycle cmov instructions.
725  ///
726  /// @param MBB Block where select instruction would be inserted.
727  /// @param Cond Condition returned by AnalyzeBranch.
728  /// @param TrueReg Virtual register to select when Cond is true.
729  /// @param FalseReg Virtual register to select when Cond is false.
730  /// @param CondCycles Latency from Cond+Branch to select output.
731  /// @param TrueCycles Latency from TrueReg to select output.
732  /// @param FalseCycles Latency from FalseReg to select output.
733  virtual bool canInsertSelect(const MachineBasicBlock &MBB,
734  ArrayRef<MachineOperand> Cond, unsigned TrueReg,
735  unsigned FalseReg, int &CondCycles,
736  int &TrueCycles, int &FalseCycles) const {
737  return false;
738  }
739 
740  /// Insert a select instruction into MBB before I that will copy TrueReg to
741  /// DstReg when Cond is true, and FalseReg to DstReg when Cond is false.
742  ///
743  /// This function can only be called after canInsertSelect() returned true.
744  /// The condition in Cond comes from AnalyzeBranch, and it can be assumed
745  /// that the same flags or registers required by Cond are available at the
746  /// insertion point.
747  ///
748  /// @param MBB Block where select instruction should be inserted.
749  /// @param I Insertion point.
750  /// @param DL Source location for debugging.
751  /// @param DstReg Virtual register to be defined by select instruction.
752  /// @param Cond Condition as computed by AnalyzeBranch.
753  /// @param TrueReg Virtual register to copy when Cond is true.
754  /// @param FalseReg Virtual register to copy when Cons is false.
755  virtual void insertSelect(MachineBasicBlock &MBB,
757  unsigned DstReg, ArrayRef<MachineOperand> Cond,
758  unsigned TrueReg, unsigned FalseReg) const {
759  llvm_unreachable("Target didn't implement TargetInstrInfo::insertSelect!");
760  }
761 
762  /// Analyze the given select instruction, returning true if
763  /// it cannot be understood. It is assumed that MI->isSelect() is true.
764  ///
765  /// When successful, return the controlling condition and the operands that
766  /// determine the true and false result values.
767  ///
768  /// Result = SELECT Cond, TrueOp, FalseOp
769  ///
770  /// Some targets can optimize select instructions, for example by predicating
771  /// the instruction defining one of the operands. Such targets should set
772  /// Optimizable.
773  ///
774  /// @param MI Select instruction to analyze.
775  /// @param Cond Condition controlling the select.
776  /// @param TrueOp Operand number of the value selected when Cond is true.
777  /// @param FalseOp Operand number of the value selected when Cond is false.
778  /// @param Optimizable Returned as true if MI is optimizable.
779  /// @returns False on success.
780  virtual bool analyzeSelect(const MachineInstr &MI,
782  unsigned &TrueOp, unsigned &FalseOp,
783  bool &Optimizable) const {
784  assert(MI.getDesc().isSelect() && "MI must be a select instruction");
785  return true;
786  }
787 
788  /// Given a select instruction that was understood by
789  /// analyzeSelect and returned Optimizable = true, attempt to optimize MI by
790  /// merging it with one of its operands. Returns NULL on failure.
791  ///
792  /// When successful, returns the new select instruction. The client is
793  /// responsible for deleting MI.
794  ///
795  /// If both sides of the select can be optimized, PreferFalse is used to pick
796  /// a side.
797  ///
798  /// @param MI Optimizable select instruction.
799  /// @param NewMIs Set that record all MIs in the basic block up to \p
800  /// MI. Has to be updated with any newly created MI or deleted ones.
801  /// @param PreferFalse Try to optimize FalseOp instead of TrueOp.
802  /// @returns Optimized instruction or NULL.
805  bool PreferFalse = false) const {
806  // This function must be implemented if Optimizable is ever set.
807  llvm_unreachable("Target must implement TargetInstrInfo::optimizeSelect!");
808  }
809 
810  /// Emit instructions to copy a pair of physical registers.
811  ///
812  /// This function should support copies within any legal register class as
813  /// well as any cross-class copies created during instruction selection.
814  ///
815  /// The source and destination registers may overlap, which may require a
816  /// careful implementation when multiple copy instructions are required for
817  /// large registers. See for example the ARM target.
818  virtual void copyPhysReg(MachineBasicBlock &MBB,
820  unsigned DestReg, unsigned SrcReg,
821  bool KillSrc) const {
822  llvm_unreachable("Target didn't implement TargetInstrInfo::copyPhysReg!");
823  }
824 
825  /// Store the specified register of the given register class to the specified
826  /// stack frame index. The store instruction is to be added to the given
827  /// machine basic block before the specified machine instruction. If isKill
828  /// is true, the register operand is the last use and must be marked kill.
831  unsigned SrcReg, bool isKill, int FrameIndex,
832  const TargetRegisterClass *RC,
833  const TargetRegisterInfo *TRI) const {
834  llvm_unreachable("Target didn't implement "
835  "TargetInstrInfo::storeRegToStackSlot!");
836  }
837 
838  /// Load the specified register of the given register class from the specified
839  /// stack frame index. The load instruction is to be added to the given
840  /// machine basic block before the specified machine instruction.
843  unsigned DestReg, int FrameIndex,
844  const TargetRegisterClass *RC,
845  const TargetRegisterInfo *TRI) const {
846  llvm_unreachable("Target didn't implement "
847  "TargetInstrInfo::loadRegFromStackSlot!");
848  }
849 
850  /// This function is called for all pseudo instructions
851  /// that remain after register allocation. Many pseudo instructions are
852  /// created to help register allocation. This is the place to convert them
853  /// into real instructions. The target can edit MI in place, or it can insert
854  /// new instructions and erase MI. The function should return true if
855  /// anything was changed.
856  virtual bool expandPostRAPseudo(MachineInstr &MI) const { return false; }
857 
858  /// Check whether the target can fold a load that feeds a subreg operand
859  /// (or a subreg operand that feeds a store).
860  /// For example, X86 may want to return true if it can fold
861  /// movl (%esp), %eax
862  /// subb, %al, ...
863  /// Into:
864  /// subb (%esp), ...
865  ///
866  /// Ideally, we'd like the target implementation of foldMemoryOperand() to
867  /// reject subregs - but since this behavior used to be enforced in the
868  /// target-independent code, moving this responsibility to the targets
869  /// has the potential of causing nasty silent breakage in out-of-tree targets.
870  virtual bool isSubregFoldable() const { return false; }
871 
872  /// Attempt to fold a load or store of the specified stack
873  /// slot into the specified machine instruction for the specified operand(s).
874  /// If this is possible, a new instruction is returned with the specified
875  /// operand folded, otherwise NULL is returned.
876  /// The new instruction is inserted before MI, and the client is responsible
877  /// for removing the old instruction.
879  int FrameIndex,
880  LiveIntervals *LIS = nullptr) const;
881 
882  /// Same as the previous version except it allows folding of any load and
883  /// store from / to any address, not just from a specific stack slot.
885  MachineInstr &LoadMI,
886  LiveIntervals *LIS = nullptr) const;
887 
888  /// Return true when there is potentially a faster code sequence
889  /// for an instruction chain ending in \p Root. All potential patterns are
890  /// returned in the \p Pattern vector. Pattern should be sorted in priority
891  /// order since the pattern evaluator stops checking as soon as it finds a
892  /// faster sequence.
893  /// \param Root - Instruction that could be combined with one of its operands
894  /// \param Patterns - Vector of possible combination patterns
895  virtual bool getMachineCombinerPatterns(
896  MachineInstr &Root,
898 
899  /// Return true when a code sequence can improve throughput. It
900  /// should be called only for instructions in loops.
901  /// \param Pattern - combiner pattern
902  virtual bool isThroughputPattern(MachineCombinerPattern Pattern) const;
903 
904  /// Return true if the input \P Inst is part of a chain of dependent ops
905  /// that are suitable for reassociation, otherwise return false.
906  /// If the instruction's operands must be commuted to have a previous
907  /// instruction of the same type define the first source operand, \P Commuted
908  /// will be set to true.
909  bool isReassociationCandidate(const MachineInstr &Inst, bool &Commuted) const;
910 
911  /// Return true when \P Inst is both associative and commutative.
912  virtual bool isAssociativeAndCommutative(const MachineInstr &Inst) const {
913  return false;
914  }
915 
916  /// Return true when \P Inst has reassociable operands in the same \P MBB.
917  virtual bool hasReassociableOperands(const MachineInstr &Inst,
918  const MachineBasicBlock *MBB) const;
919 
920  /// Return true when \P Inst has reassociable sibling.
921  bool hasReassociableSibling(const MachineInstr &Inst, bool &Commuted) const;
922 
923  /// When getMachineCombinerPatterns() finds patterns, this function generates
924  /// the instructions that could replace the original code sequence. The client
925  /// has to decide whether the actual replacement is beneficial or not.
926  /// \param Root - Instruction that could be combined with one of its operands
927  /// \param Pattern - Combination pattern for Root
928  /// \param InsInstrs - Vector of new instructions that implement P
929  /// \param DelInstrs - Old instructions, including Root, that could be
930  /// replaced by InsInstr
931  /// \param InstrIdxForVirtReg - map of virtual register to instruction in
932  /// InsInstr that defines it
933  virtual void genAlternativeCodeSequence(
934  MachineInstr &Root, MachineCombinerPattern Pattern,
937  DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const;
938 
939  /// Attempt to reassociate \P Root and \P Prev according to \P Pattern to
940  /// reduce critical path length.
941  void reassociateOps(MachineInstr &Root, MachineInstr &Prev,
942  MachineCombinerPattern Pattern,
945  DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const;
946 
947  /// This is an architecture-specific helper function of reassociateOps.
948  /// Set special operand attributes for new instructions after reassociation.
949  virtual void setSpecialOperandAttr(MachineInstr &OldMI1, MachineInstr &OldMI2,
950  MachineInstr &NewMI1,
951  MachineInstr &NewMI2) const {}
952 
953  /// Return true when a target supports MachineCombiner.
954  virtual bool useMachineCombiner() const { return false; }
955 
956 protected:
957  /// Target-dependent implementation for foldMemoryOperand.
958  /// Target-independent code in foldMemoryOperand will
959  /// take care of adding a MachineMemOperand to the newly created instruction.
960  /// The instruction and any auxiliary instructions necessary will be inserted
961  /// at InsertPt.
962  virtual MachineInstr *
964  ArrayRef<unsigned> Ops,
965  MachineBasicBlock::iterator InsertPt, int FrameIndex,
966  LiveIntervals *LIS = nullptr) const {
967  return nullptr;
968  }
969 
970  /// Target-dependent implementation for foldMemoryOperand.
971  /// Target-independent code in foldMemoryOperand will
972  /// take care of adding a MachineMemOperand to the newly created instruction.
973  /// The instruction and any auxiliary instructions necessary will be inserted
974  /// at InsertPt.
977  MachineBasicBlock::iterator InsertPt, MachineInstr &LoadMI,
978  LiveIntervals *LIS = nullptr) const {
979  return nullptr;
980  }
981 
982  /// \brief Target-dependent implementation of getRegSequenceInputs.
983  ///
984  /// \returns true if it is possible to build the equivalent
985  /// REG_SEQUENCE inputs with the pair \p MI, \p DefIdx. False otherwise.
986  ///
987  /// \pre MI.isRegSequenceLike().
988  ///
989  /// \see TargetInstrInfo::getRegSequenceInputs.
991  const MachineInstr &MI, unsigned DefIdx,
992  SmallVectorImpl<RegSubRegPairAndIdx> &InputRegs) const {
993  return false;
994  }
995 
996  /// \brief Target-dependent implementation of getExtractSubregInputs.
997  ///
998  /// \returns true if it is possible to build the equivalent
999  /// EXTRACT_SUBREG inputs with the pair \p MI, \p DefIdx. False otherwise.
1000  ///
1001  /// \pre MI.isExtractSubregLike().
1002  ///
1003  /// \see TargetInstrInfo::getExtractSubregInputs.
1005  unsigned DefIdx,
1006  RegSubRegPairAndIdx &InputReg) const {
1007  return false;
1008  }
1009 
1010  /// \brief Target-dependent implementation of getInsertSubregInputs.
1011  ///
1012  /// \returns true if it is possible to build the equivalent
1013  /// INSERT_SUBREG inputs with the pair \p MI, \p DefIdx. False otherwise.
1014  ///
1015  /// \pre MI.isInsertSubregLike().
1016  ///
1017  /// \see TargetInstrInfo::getInsertSubregInputs.
1018  virtual bool
1019  getInsertSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx,
1020  RegSubRegPair &BaseReg,
1021  RegSubRegPairAndIdx &InsertedReg) const {
1022  return false;
1023  }
1024 
1025 public:
1026  /// getAddressSpaceForPseudoSourceKind - Given the kind of memory
1027  /// (e.g. stack) the target returns the corresponding address space.
1028  virtual unsigned
1030  return 0;
1031  }
1032 
1033  /// unfoldMemoryOperand - Separate a single instruction which folded a load or
1034  /// a store or a load and a store into two or more instruction. If this is
1035  /// possible, returns true as well as the new instructions by reference.
1036  virtual bool
1038  bool UnfoldLoad, bool UnfoldStore,
1039  SmallVectorImpl<MachineInstr *> &NewMIs) const {
1040  return false;
1041  }
1042 
1044  SmallVectorImpl<SDNode *> &NewNodes) const {
1045  return false;
1046  }
1047 
1048  /// Returns the opcode of the would be new
1049  /// instruction after load / store are unfolded from an instruction of the
1050  /// specified opcode. It returns zero if the specified unfolding is not
1051  /// possible. If LoadRegIndex is non-null, it is filled in with the operand
1052  /// index of the operand which will hold the register holding the loaded
1053  /// value.
1054  virtual unsigned
1055  getOpcodeAfterMemoryUnfold(unsigned Opc, bool UnfoldLoad, bool UnfoldStore,
1056  unsigned *LoadRegIndex = nullptr) const {
1057  return 0;
1058  }
1059 
1060  /// This is used by the pre-regalloc scheduler to determine if two loads are
1061  /// loading from the same base address. It should only return true if the base
1062  /// pointers are the same and the only differences between the two addresses
1063  /// are the offset. It also returns the offsets by reference.
1064  virtual bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
1065  int64_t &Offset1,
1066  int64_t &Offset2) const {
1067  return false;
1068  }
1069 
1070  /// This is a used by the pre-regalloc scheduler to determine (in conjunction
1071  /// with areLoadsFromSameBasePtr) if two loads should be scheduled together.
1072  /// On some targets if two loads are loading from
1073  /// addresses in the same cache line, it's better if they are scheduled
1074  /// together. This function takes two integers that represent the load offsets
1075  /// from the common base address. It returns true if it decides it's desirable
1076  /// to schedule the two loads together. "NumLoads" is the number of loads that
1077  /// have already been scheduled after Load1.
1078  virtual bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
1079  int64_t Offset1, int64_t Offset2,
1080  unsigned NumLoads) const {
1081  return false;
1082  }
1083 
1084  /// Get the base register and byte offset of an instruction that reads/writes
1085  /// memory.
1086  virtual bool getMemOpBaseRegImmOfs(MachineInstr &MemOp, unsigned &BaseReg,
1087  int64_t &Offset,
1088  const TargetRegisterInfo *TRI) const {
1089  return false;
1090  }
1091 
1092  /// Return true if the instruction contains a base register and offset. If
1093  /// true, the function also sets the operand position in the instruction
1094  /// for the base register and offset.
1095  virtual bool getBaseAndOffsetPosition(const MachineInstr &MI,
1096  unsigned &BasePos,
1097  unsigned &OffsetPos) const {
1098  return false;
1099  }
1100 
1101  /// If the instruction is an increment of a constant value, return the amount.
1102  virtual bool getIncrementValue(const MachineInstr &MI, int &Value) const {
1103  return false;
1104  }
1105 
1106  /// Returns true if the two given memory operations should be scheduled
1107  /// adjacent. Note that you have to add:
1108  /// DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
1109  /// or
1110  /// DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
1111  /// to TargetPassConfig::createMachineScheduler() to have an effect.
1112  virtual bool shouldClusterMemOps(MachineInstr &FirstLdSt, unsigned BaseReg1,
1113  MachineInstr &SecondLdSt, unsigned BaseReg2,
1114  unsigned NumLoads) const {
1115  llvm_unreachable("target did not implement shouldClusterMemOps()");
1116  }
1117 
1118  /// Reverses the branch condition of the specified condition list,
1119  /// returning false on success and true if it cannot be reversed.
1120  virtual bool
1122  return true;
1123  }
1124 
1125  /// Insert a noop into the instruction stream at the specified point.
1126  virtual void insertNoop(MachineBasicBlock &MBB,
1127  MachineBasicBlock::iterator MI) const;
1128 
1129  /// Return the noop instruction to use for a noop.
1130  virtual void getNoop(MCInst &NopInst) const;
1131 
1132  /// Return true for post-incremented instructions.
1133  virtual bool isPostIncrement(const MachineInstr &MI) const { return false; }
1134 
1135  /// Returns true if the instruction is already predicated.
1136  virtual bool isPredicated(const MachineInstr &MI) const { return false; }
1137 
1138  /// Returns true if the instruction is a
1139  /// terminator instruction that has not been predicated.
1140  virtual bool isUnpredicatedTerminator(const MachineInstr &MI) const;
1141 
1142  /// Returns true if MI is an unconditional tail call.
1143  virtual bool isUnconditionalTailCall(const MachineInstr &MI) const {
1144  return false;
1145  }
1146 
1147  /// Returns true if the tail call can be made conditional on BranchCond.
1149  const MachineInstr &TailCall) const {
1150  return false;
1151  }
1152 
1153  /// Replace the conditional branch in MBB with a conditional tail call.
1156  const MachineInstr &TailCall) const {
1157  llvm_unreachable("Target didn't implement replaceBranchWithTailCall!");
1158  }
1159 
1160  /// Convert the instruction into a predicated instruction.
1161  /// It returns true if the operation was successful.
1162  virtual bool PredicateInstruction(MachineInstr &MI,
1163  ArrayRef<MachineOperand> Pred) const;
1164 
1165  /// Returns true if the first specified predicate
1166  /// subsumes the second, e.g. GE subsumes GT.
1168  ArrayRef<MachineOperand> Pred2) const {
1169  return false;
1170  }
1171 
1172  /// If the specified instruction defines any predicate
1173  /// or condition code register(s) used for predication, returns true as well
1174  /// as the definition predicate(s) by reference.
1175  virtual bool DefinesPredicate(MachineInstr &MI,
1176  std::vector<MachineOperand> &Pred) const {
1177  return false;
1178  }
1179 
1180  /// Return true if the specified instruction can be predicated.
1181  /// By default, this returns true for every instruction with a
1182  /// PredicateOperand.
1183  virtual bool isPredicable(const MachineInstr &MI) const {
1184  return MI.getDesc().isPredicable();
1185  }
1186 
1187  /// Return true if it's safe to move a machine
1188  /// instruction that defines the specified register class.
1189  virtual bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
1190  return true;
1191  }
1192 
1193  /// Test if the given instruction should be considered a scheduling boundary.
1194  /// This primarily includes labels and terminators.
1195  virtual bool isSchedulingBoundary(const MachineInstr &MI,
1196  const MachineBasicBlock *MBB,
1197  const MachineFunction &MF) const;
1198 
1199  /// Measure the specified inline asm to determine an approximation of its
1200  /// length.
1201  virtual unsigned getInlineAsmLength(const char *Str,
1202  const MCAsmInfo &MAI) const;
1203 
1204  /// Allocate and return a hazard recognizer to use for this target when
1205  /// scheduling the machine instructions before register allocation.
1206  virtual ScheduleHazardRecognizer *
1208  const ScheduleDAG *DAG) const;
1209 
1210  /// Allocate and return a hazard recognizer to use for this target when
1211  /// scheduling the machine instructions before register allocation.
1212  virtual ScheduleHazardRecognizer *
1214  const ScheduleDAG *DAG) const;
1215 
1216  /// Allocate and return a hazard recognizer to use for this target when
1217  /// scheduling the machine instructions after register allocation.
1218  virtual ScheduleHazardRecognizer *
1220  const ScheduleDAG *DAG) const;
1221 
1222  /// Allocate and return a hazard recognizer to use for by non-scheduling
1223  /// passes.
1224  virtual ScheduleHazardRecognizer *
1226  return nullptr;
1227  }
1228 
1229  /// Provide a global flag for disabling the PreRA hazard recognizer that
1230  /// targets may choose to honor.
1231  bool usePreRAHazardRecognizer() const;
1232 
1233  /// For a comparison instruction, return the source registers
1234  /// in SrcReg and SrcReg2 if having two register operands, and the value it
1235  /// compares against in CmpValue. Return true if the comparison instruction
1236  /// can be analyzed.
1237  virtual bool analyzeCompare(const MachineInstr &MI, unsigned &SrcReg,
1238  unsigned &SrcReg2, int &Mask, int &Value) const {
1239  return false;
1240  }
1241 
1242  /// See if the comparison instruction can be converted
1243  /// into something more efficient. E.g., on ARM most instructions can set the
1244  /// flags register, obviating the need for a separate CMP.
1245  virtual bool optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg,
1246  unsigned SrcReg2, int Mask, int Value,
1247  const MachineRegisterInfo *MRI) const {
1248  return false;
1249  }
1250  virtual bool optimizeCondBranch(MachineInstr &MI) const { return false; }
1251 
1252  /// Try to remove the load by folding it to a register operand at the use.
1253  /// We fold the load instructions if and only if the
1254  /// def and use are in the same BB. We only look at one load and see
1255  /// whether it can be folded into MI. FoldAsLoadDefReg is the virtual register
1256  /// defined by the load we are trying to fold. DefMI returns the machine
1257  /// instruction that defines FoldAsLoadDefReg, and the function returns
1258  /// the machine instruction generated due to folding.
1260  const MachineRegisterInfo *MRI,
1261  unsigned &FoldAsLoadDefReg,
1262  MachineInstr *&DefMI) const {
1263  return nullptr;
1264  }
1265 
1266  /// 'Reg' is known to be defined by a move immediate instruction,
1267  /// try to fold the immediate into the use instruction.
1268  /// If MRI->hasOneNonDBGUse(Reg) is true, and this function returns true,
1269  /// then the caller may assume that DefMI has been erased from its parent
1270  /// block. The caller may assume that it will not be erased by this
1271  /// function otherwise.
1273  unsigned Reg, MachineRegisterInfo *MRI) const {
1274  return false;
1275  }
1276 
1277  /// Return the number of u-operations the given machine
1278  /// instruction will be decoded to on the target cpu. The itinerary's
1279  /// IssueWidth is the number of microops that can be dispatched each
1280  /// cycle. An instruction with zero microops takes no dispatch resources.
1281  virtual unsigned getNumMicroOps(const InstrItineraryData *ItinData,
1282  const MachineInstr &MI) const;
1283 
1284  /// Return true for pseudo instructions that don't consume any
1285  /// machine resources in their current form. These are common cases that the
1286  /// scheduler should consider free, rather than conservatively handling them
1287  /// as instructions with no itinerary.
1288  bool isZeroCost(unsigned Opcode) const {
1289  return Opcode <= TargetOpcode::COPY;
1290  }
1291 
1292  virtual int getOperandLatency(const InstrItineraryData *ItinData,
1293  SDNode *DefNode, unsigned DefIdx,
1294  SDNode *UseNode, unsigned UseIdx) const;
1295 
1296  /// Compute and return the use operand latency of a given pair of def and use.
1297  /// In most cases, the static scheduling itinerary was enough to determine the
1298  /// operand latency. But it may not be possible for instructions with variable
1299  /// number of defs / uses.
1300  ///
1301  /// This is a raw interface to the itinerary that may be directly overridden
1302  /// by a target. Use computeOperandLatency to get the best estimate of
1303  /// latency.
1304  virtual int getOperandLatency(const InstrItineraryData *ItinData,
1305  const MachineInstr &DefMI, unsigned DefIdx,
1306  const MachineInstr &UseMI,
1307  unsigned UseIdx) const;
1308 
1309  /// Compute the instruction latency of a given instruction.
1310  /// If the instruction has higher cost when predicated, it's returned via
1311  /// PredCost.
1312  virtual unsigned getInstrLatency(const InstrItineraryData *ItinData,
1313  const MachineInstr &MI,
1314  unsigned *PredCost = nullptr) const;
1315 
1316  virtual unsigned getPredicationCost(const MachineInstr &MI) const;
1317 
1318  virtual int getInstrLatency(const InstrItineraryData *ItinData,
1319  SDNode *Node) const;
1320 
1321  /// Return the default expected latency for a def based on its opcode.
1322  unsigned defaultDefLatency(const MCSchedModel &SchedModel,
1323  const MachineInstr &DefMI) const;
1324 
1325  int computeDefOperandLatency(const InstrItineraryData *ItinData,
1326  const MachineInstr &DefMI) const;
1327 
1328  /// Return true if this opcode has high latency to its result.
1329  virtual bool isHighLatencyDef(int opc) const { return false; }
1330 
1331  /// Compute operand latency between a def of 'Reg'
1332  /// and a use in the current loop. Return true if the target considered
1333  /// it 'high'. This is used by optimization passes such as machine LICM to
1334  /// determine whether it makes sense to hoist an instruction out even in a
1335  /// high register pressure situation.
1336  virtual bool hasHighOperandLatency(const TargetSchedModel &SchedModel,
1337  const MachineRegisterInfo *MRI,
1338  const MachineInstr &DefMI, unsigned DefIdx,
1339  const MachineInstr &UseMI,
1340  unsigned UseIdx) const {
1341  return false;
1342  }
1343 
1344  /// Compute operand latency of a def of 'Reg'. Return true
1345  /// if the target considered it 'low'.
1346  virtual bool hasLowDefLatency(const TargetSchedModel &SchedModel,
1347  const MachineInstr &DefMI,
1348  unsigned DefIdx) const;
1349 
1350  /// Perform target-specific instruction verification.
1351  virtual bool verifyInstruction(const MachineInstr &MI,
1352  StringRef &ErrInfo) const {
1353  return true;
1354  }
1355 
1356  /// Return the current execution domain and bit mask of
1357  /// possible domains for instruction.
1358  ///
1359  /// Some micro-architectures have multiple execution domains, and multiple
1360  /// opcodes that perform the same operation in different domains. For
1361  /// example, the x86 architecture provides the por, orps, and orpd
1362  /// instructions that all do the same thing. There is a latency penalty if a
1363  /// register is written in one domain and read in another.
1364  ///
1365  /// This function returns a pair (domain, mask) containing the execution
1366  /// domain of MI, and a bit mask of possible domains. The setExecutionDomain
1367  /// function can be used to change the opcode to one of the domains in the
1368  /// bit mask. Instructions whose execution domain can't be changed should
1369  /// return a 0 mask.
1370  ///
1371  /// The execution domain numbers don't have any special meaning except domain
1372  /// 0 is used for instructions that are not associated with any interesting
1373  /// execution domain.
1374  ///
1375  virtual std::pair<uint16_t, uint16_t>
1377  return std::make_pair(0, 0);
1378  }
1379 
1380  /// Change the opcode of MI to execute in Domain.
1381  ///
1382  /// The bit (1 << Domain) must be set in the mask returned from
1383  /// getExecutionDomain(MI).
1384  virtual void setExecutionDomain(MachineInstr &MI, unsigned Domain) const {}
1385 
1386  /// Returns the preferred minimum clearance
1387  /// before an instruction with an unwanted partial register update.
1388  ///
1389  /// Some instructions only write part of a register, and implicitly need to
1390  /// read the other parts of the register. This may cause unwanted stalls
1391  /// preventing otherwise unrelated instructions from executing in parallel in
1392  /// an out-of-order CPU.
1393  ///
1394  /// For example, the x86 instruction cvtsi2ss writes its result to bits
1395  /// [31:0] of the destination xmm register. Bits [127:32] are unaffected, so
1396  /// the instruction needs to wait for the old value of the register to become
1397  /// available:
1398  ///
1399  /// addps %xmm1, %xmm0
1400  /// movaps %xmm0, (%rax)
1401  /// cvtsi2ss %rbx, %xmm0
1402  ///
1403  /// In the code above, the cvtsi2ss instruction needs to wait for the addps
1404  /// instruction before it can issue, even though the high bits of %xmm0
1405  /// probably aren't needed.
1406  ///
1407  /// This hook returns the preferred clearance before MI, measured in
1408  /// instructions. Other defs of MI's operand OpNum are avoided in the last N
1409  /// instructions before MI. It should only return a positive value for
1410  /// unwanted dependencies. If the old bits of the defined register have
1411  /// useful values, or if MI is determined to otherwise read the dependency,
1412  /// the hook should return 0.
1413  ///
1414  /// The unwanted dependency may be handled by:
1415  ///
1416  /// 1. Allocating the same register for an MI def and use. That makes the
1417  /// unwanted dependency identical to a required dependency.
1418  ///
1419  /// 2. Allocating a register for the def that has no defs in the previous N
1420  /// instructions.
1421  ///
1422  /// 3. Calling breakPartialRegDependency() with the same arguments. This
1423  /// allows the target to insert a dependency breaking instruction.
1424  ///
1425  virtual unsigned
1426  getPartialRegUpdateClearance(const MachineInstr &MI, unsigned OpNum,
1427  const TargetRegisterInfo *TRI) const {
1428  // The default implementation returns 0 for no partial register dependency.
1429  return 0;
1430  }
1431 
1432  /// \brief Return the minimum clearance before an instruction that reads an
1433  /// unused register.
1434  ///
1435  /// For example, AVX instructions may copy part of a register operand into
1436  /// the unused high bits of the destination register.
1437  ///
1438  /// vcvtsi2sdq %rax, undef %xmm0, %xmm14
1439  ///
1440  /// In the code above, vcvtsi2sdq copies %xmm0[127:64] into %xmm14 creating a
1441  /// false dependence on any previous write to %xmm0.
1442  ///
1443  /// This hook works similarly to getPartialRegUpdateClearance, except that it
1444  /// does not take an operand index. Instead sets \p OpNum to the index of the
1445  /// unused register.
1446  virtual unsigned getUndefRegClearance(const MachineInstr &MI, unsigned &OpNum,
1447  const TargetRegisterInfo *TRI) const {
1448  // The default implementation returns 0 for no undef register dependency.
1449  return 0;
1450  }
1451 
1452  /// Insert a dependency-breaking instruction
1453  /// before MI to eliminate an unwanted dependency on OpNum.
1454  ///
1455  /// If it wasn't possible to avoid a def in the last N instructions before MI
1456  /// (see getPartialRegUpdateClearance), this hook will be called to break the
1457  /// unwanted dependency.
1458  ///
1459  /// On x86, an xorps instruction can be used as a dependency breaker:
1460  ///
1461  /// addps %xmm1, %xmm0
1462  /// movaps %xmm0, (%rax)
1463  /// xorps %xmm0, %xmm0
1464  /// cvtsi2ss %rbx, %xmm0
1465  ///
1466  /// An <imp-kill> operand should be added to MI if an instruction was
1467  /// inserted. This ties the instructions together in the post-ra scheduler.
1468  ///
1469  virtual void breakPartialRegDependency(MachineInstr &MI, unsigned OpNum,
1470  const TargetRegisterInfo *TRI) const {}
1471 
1472  /// Create machine specific model for scheduling.
1473  virtual DFAPacketizer *
1475  return nullptr;
1476  }
1477 
1478  /// Sometimes, it is possible for the target
1479  /// to tell, even without aliasing information, that two MIs access different
1480  /// memory addresses. This function returns true if two MIs access different
1481  /// memory addresses and false otherwise.
1482  ///
1483  /// Assumes any physical registers used to compute addresses have the same
1484  /// value for both instructions. (This is the most useful assumption for
1485  /// post-RA scheduling.)
1486  ///
1487  /// See also MachineInstr::mayAlias, which is implemented on top of this
1488  /// function.
1489  virtual bool
1491  AliasAnalysis *AA = nullptr) const {
1492  assert((MIa.mayLoad() || MIa.mayStore()) &&
1493  "MIa must load from or modify a memory location");
1494  assert((MIb.mayLoad() || MIb.mayStore()) &&
1495  "MIb must load from or modify a memory location");
1496  return false;
1497  }
1498 
1499  /// \brief Return the value to use for the MachineCSE's LookAheadLimit,
1500  /// which is a heuristic used for CSE'ing phys reg defs.
1501  virtual unsigned getMachineCSELookAheadLimit() const {
1502  // The default lookahead is small to prevent unprofitable quadratic
1503  // behavior.
1504  return 5;
1505  }
1506 
1507  /// Return an array that contains the ids of the target indices (used for the
1508  /// TargetIndex machine operand) and their names.
1509  ///
1510  /// MIR Serialization is able to serialize only the target indices that are
1511  /// defined by this method.
1514  return None;
1515  }
1516 
1517  /// Decompose the machine operand's target flags into two values - the direct
1518  /// target flag value and any of bit flags that are applied.
1519  virtual std::pair<unsigned, unsigned>
1520  decomposeMachineOperandsTargetFlags(unsigned /*TF*/) const {
1521  return std::make_pair(0u, 0u);
1522  }
1523 
1524  /// Return an array that contains the direct target flag values and their
1525  /// names.
1526  ///
1527  /// MIR Serialization is able to serialize only the target flags that are
1528  /// defined by this method.
1531  return None;
1532  }
1533 
1534  /// Return an array that contains the bitmask target flag values and their
1535  /// names.
1536  ///
1537  /// MIR Serialization is able to serialize only the target flags that are
1538  /// defined by this method.
1541  return None;
1542  }
1543 
1544  /// Return an array that contains the MMO target flag values and their
1545  /// names.
1546  ///
1547  /// MIR Serialization is able to serialize only the MMO target flags that are
1548  /// defined by this method.
1551  return None;
1552  }
1553 
1554  /// Determines whether \p Inst is a tail call instruction. Override this
1555  /// method on targets that do not properly set MCID::Return and MCID::Call on
1556  /// tail call instructions."
1557  virtual bool isTailCall(const MachineInstr &Inst) const {
1558  return Inst.isReturn() && Inst.isCall();
1559  }
1560 
1561  /// True if the instruction is bound to the top of its basic block and no
1562  /// other instructions shall be inserted before it. This can be implemented
1563  /// to prevent register allocator to insert spills before such instructions.
1564  virtual bool isBasicBlockPrologue(const MachineInstr &MI) const {
1565  return false;
1566  }
1567 
1568  /// \brief Describes the number of instructions that it will take to call and
1569  /// construct a frame for a given outlining candidate.
1571  /// Number of instructions to call an outlined function for this candidate.
1572  unsigned CallOverhead;
1573 
1574  /// \brief Number of instructions to construct an outlined function frame
1575  /// for this candidate.
1576  unsigned FrameOverhead;
1577 
1578  /// \brief Represents the specific instructions that must be emitted to
1579  /// construct a call to this candidate.
1581 
1582  /// \brief Represents the specific instructions that must be emitted to
1583  /// construct a frame for this candidate's outlined function.
1585 
1587  MachineOutlinerInfo(unsigned CallOverhead, unsigned FrameOverhead,
1588  unsigned CallConstructionID,
1589  unsigned FrameConstructionID)
1590  : CallOverhead(CallOverhead), FrameOverhead(FrameOverhead),
1591  CallConstructionID(CallConstructionID),
1592  FrameConstructionID(FrameConstructionID) {}
1593  };
1594 
1595  /// \brief Returns a \p MachineOutlinerInfo struct containing target-specific
1596  /// information for a set of outlining candidates.
1598  std::vector<
1599  std::pair<MachineBasicBlock::iterator, MachineBasicBlock::iterator>>
1600  &RepeatedSequenceLocs) const {
1602  "Target didn't implement TargetInstrInfo::getOutliningOverhead!");
1603  }
1604 
1605  /// Represents how an instruction should be mapped by the outliner.
1606  /// \p Legal instructions are those which are safe to outline.
1607  /// \p Illegal instructions are those which cannot be outlined.
1608  /// \p Invisible instructions are instructions which can be outlined, but
1609  /// shouldn't actually impact the outlining result.
1611 
1612  /// Returns how or if \p MI should be outlined.
1613  virtual MachineOutlinerInstrType
1614  getOutliningType(MachineBasicBlock::iterator &MIT, unsigned Flags) const {
1616  "Target didn't implement TargetInstrInfo::getOutliningType!");
1617  }
1618 
1619  /// \brief Returns target-defined flags defining properties of the MBB for
1620  /// the outliner.
1621  virtual unsigned getMachineOutlinerMBBFlags(MachineBasicBlock &MBB) const {
1622  return 0x0;
1623  }
1624 
1625  /// Insert a custom epilogue for outlined functions.
1626  /// This may be empty, in which case no epilogue or return statement will be
1627  /// emitted.
1629  MachineFunction &MF,
1630  const MachineOutlinerInfo &MInfo) const {
1632  "Target didn't implement TargetInstrInfo::insertOutlinerEpilogue!");
1633  }
1634 
1635  /// Insert a call to an outlined function into the program.
1636  /// Returns an iterator to the spot where we inserted the call. This must be
1637  /// implemented by the target.
1641  const MachineOutlinerInfo &MInfo) const {
1643  "Target didn't implement TargetInstrInfo::insertOutlinedCall!");
1644  }
1645 
1646  /// Insert a custom prologue for outlined functions.
1647  /// This may be empty, in which case no prologue will be emitted.
1649  MachineFunction &MF,
1650  const MachineOutlinerInfo &MInfo) const {
1652  "Target didn't implement TargetInstrInfo::insertOutlinerPrologue!");
1653  }
1654 
1655  /// Return true if the function can safely be outlined from.
1656  /// A function \p MF is considered safe for outlining if an outlined function
1657  /// produced from instructions in F will produce a program which produces the
1658  /// same output for any set of given inputs.
1660  bool OutlineFromLinkOnceODRs) const {
1661  llvm_unreachable("Target didn't implement "
1662  "TargetInstrInfo::isFunctionSafeToOutlineFrom!");
1663  }
1664 
1665 private:
1666  unsigned CallFrameSetupOpcode, CallFrameDestroyOpcode;
1667  unsigned CatchRetOpcode;
1668  unsigned ReturnOpcode;
1669 };
1670 
1671 /// \brief Provide DenseMapInfo for TargetInstrInfo::RegSubRegPair.
1674 
1676  return TargetInstrInfo::RegSubRegPair(RegInfo::getEmptyKey(),
1677  RegInfo::getEmptyKey());
1678  }
1679 
1681  return TargetInstrInfo::RegSubRegPair(RegInfo::getTombstoneKey(),
1682  RegInfo::getTombstoneKey());
1683  }
1684 
1685  /// \brief Reuse getHashValue implementation from
1686  /// std::pair<unsigned, unsigned>.
1687  static unsigned getHashValue(const TargetInstrInfo::RegSubRegPair &Val) {
1688  std::pair<unsigned, unsigned> PairVal = std::make_pair(Val.Reg, Val.SubReg);
1689  return DenseMapInfo<std::pair<unsigned, unsigned>>::getHashValue(PairVal);
1690  }
1691 
1692  static bool isEqual(const TargetInstrInfo::RegSubRegPair &LHS,
1693  const TargetInstrInfo::RegSubRegPair &RHS) {
1694  return RegInfo::isEqual(LHS.Reg, RHS.Reg) &&
1695  RegInfo::isEqual(LHS.SubReg, RHS.SubReg);
1696  }
1697 };
1698 
1699 } // end namespace llvm
1700 
1701 #endif // LLVM_TARGET_TARGETINSTRINFO_H
virtual std::pair< unsigned, unsigned > decomposeMachineOperandsTargetFlags(unsigned) const
Decompose the machine operand&#39;s target flags into two values - the direct target flag value and any o...
virtual void genAlternativeCodeSequence(MachineInstr &Root, MachineCombinerPattern Pattern, SmallVectorImpl< MachineInstr *> &InsInstrs, SmallVectorImpl< MachineInstr *> &DelInstrs, DenseMap< unsigned, unsigned > &InstrIdxForVirtReg) const
When getMachineCombinerPatterns() finds patterns, this function generates the instructions that could...
This class is the base class for the comparison instructions.
Definition: InstrTypes.h:843
virtual bool expandPostRAPseudo(MachineInstr &MI) const
This function is called for all pseudo instructions that remain after register allocation.
static unsigned getHashValue(const TargetInstrInfo::RegSubRegPair &Val)
Reuse getHashValue implementation from std::pair<unsigned, unsigned>.
virtual bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1, int64_t &Offset2) const
This is used by the pre-regalloc scheduler to determine if two loads are loading from the same base a...
virtual bool canInsertSelect(const MachineBasicBlock &MBB, ArrayRef< MachineOperand > Cond, unsigned TrueReg, unsigned FalseReg, int &CondCycles, int &TrueCycles, int &FalseCycles) const
Return true if it is possible to insert a select instruction that chooses between TrueReg and FalseRe...
bool isCall(QueryType Type=AnyInBundle) const
Definition: MachineInstr.h:461
static TargetInstrInfo::RegSubRegPair getTombstoneKey()
virtual void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, unsigned DstReg, ArrayRef< MachineOperand > Cond, unsigned TrueReg, unsigned FalseReg) const
Insert a select instruction into MBB before I that will copy TrueReg to DstReg when Cond is true...
virtual bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const
Return true if it&#39;s safe to move a machine instruction that defines the specified register class...
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
RegSubRegPair(unsigned Reg=0, unsigned SubReg=0)
A Module instance is used to store all the information related to an LLVM module. ...
Definition: Module.h:63
virtual void setExecutionDomain(MachineInstr &MI, unsigned Domain) const
Change the opcode of MI to execute in Domain.
virtual bool DefinesPredicate(MachineInstr &MI, std::vector< MachineOperand > &Pred) const
If the specified instruction defines any predicate or condition code register(s) used for predication...
virtual bool optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg, unsigned SrcReg2, int Mask, int Value, const MachineRegisterInfo *MRI) const
See if the comparison instruction can be converted into something more efficient. ...
virtual bool isThroughputPattern(MachineCombinerPattern Pattern) const
Return true when a code sequence can improve throughput.
virtual bool isReallyTriviallyReMaterializable(const MachineInstr &MI, AliasAnalysis *AA) const
For instructions with opcodes for which the M_REMATERIALIZABLE flag is set, this hook lets the target...
int64_t getFrameTotalSize(const MachineInstr &I) const
Returns the total frame size, which is made up of the space set up inside the pair of frame start-sto...
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:163
virtual bool analyzeSelect(const MachineInstr &MI, SmallVectorImpl< MachineOperand > &Cond, unsigned &TrueOp, unsigned &FalseOp, bool &Optimizable) const
Analyze the given select instruction, returning true if it cannot be understood.
virtual bool getIncrementValue(const MachineInstr &MI, int &Value) const
If the instruction is an increment of a constant value, return the amount.
virtual MachineInstr & duplicate(MachineBasicBlock &MBB, MachineBasicBlock::iterator InsertBefore, const MachineInstr &Orig) const
Clones instruction or the whole instruction bundle Orig and insert into MBB before InsertBefore...
MachineInstr * commuteInstruction(MachineInstr &MI, bool NewMI=false, unsigned OpIdx1=CommuteAnyOperandIndex, unsigned OpIdx2=CommuteAnyOperandIndex) const
This method commutes the operands of the given machine instruction MI.
virtual bool hasReassociableOperands(const MachineInstr &Inst, const MachineBasicBlock *MBB) const
Return true when Inst has reassociable operands in the same MBB.
TargetInstrInfo(unsigned CFSetupOpcode=~0u, unsigned CFDestroyOpcode=~0u, unsigned CatchRetOpcode=~0u, unsigned ReturnOpcode=~0u)
virtual unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const
Insert branch code into the end of the specified MachineBasicBlock.
virtual bool useMachineCombiner() const
Return true when a target supports MachineCombiner.
virtual bool getExtractSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx, RegSubRegPairAndIdx &InputReg) const
Target-dependent implementation of getExtractSubregInputs.
A debug info location.
Definition: DebugLoc.h:34
MachineInstr * foldMemoryOperand(MachineInstr &MI, ArrayRef< unsigned > Ops, int FrameIndex, LiveIntervals *LIS=nullptr) const
Attempt to fold a load or store of the specified stack slot into the specified machine instruction fo...
unsigned getCallFrameDestroyOpcode() const
unsigned defaultDefLatency(const MCSchedModel &SchedModel, const MachineInstr &DefMI) const
Return the default expected latency for a def based on its opcode.
static bool isGenericOpcode(unsigned Opc)
virtual unsigned reduceLoopCount(MachineBasicBlock &MBB, MachineInstr *IndVar, MachineInstr &Cmp, SmallVectorImpl< MachineOperand > &Cond, SmallVectorImpl< MachineInstr *> &PrevInsts, unsigned Iter, unsigned MaxIter) const
Generate code to reduce the loop iteration by one and check if the loop is finished.
virtual unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const
Remove the branching code at the end of the specific MBB.
virtual bool isHighLatencyDef(int opc) const
Return true if this opcode has high latency to its result.
Represents a predicate at the MachineFunction level.
virtual bool isUnpredicatedTerminator(const MachineInstr &MI) const
Returns true if the instruction is a terminator instruction that has not been predicated.
A templated base class for SmallPtrSet which provides the typesafe interface that is common across al...
Definition: SmallPtrSet.h:344
virtual unsigned getMachineCSELookAheadLimit() const
Return the value to use for the MachineCSE&#39;s LookAheadLimit, which is a heuristic used for CSE&#39;ing ph...
virtual ArrayRef< std::pair< unsigned, const char * > > getSerializableBitmaskMachineOperandTargetFlags() const
Return an array that contains the bitmask target flag values and their names.
virtual unsigned getInstSizeInBytes(const MachineInstr &MI) const
Returns the size in bytes of the specified MachineInstr, or ~0U when this function is not implemented...
A description of a memory reference used in the backend.
virtual void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, unsigned SubIdx, const MachineInstr &Orig, const TargetRegisterInfo &TRI) const
Re-issue the specified &#39;original&#39; instruction at the specific location targeting a new destination re...
virtual unsigned getPartialRegUpdateClearance(const MachineInstr &MI, unsigned OpNum, const TargetRegisterInfo *TRI) const
Returns the preferred minimum clearance before an instruction with an unwanted partial register updat...
Provide an instruction scheduling machine model to CodeGen passes.
virtual MachineInstr * foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, MachineInstr &LoadMI, LiveIntervals *LIS=nullptr) const
Target-dependent implementation for foldMemoryOperand.
virtual bool FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, unsigned Reg, MachineRegisterInfo *MRI) const
&#39;Reg&#39; is known to be defined by a move immediate instruction, try to fold the immediate into the use ...
virtual DFAPacketizer * CreateTargetScheduleState(const TargetSubtargetInfo &) const
Create machine specific model for scheduling.
virtual void insertOutlinerEpilogue(MachineBasicBlock &MBB, MachineFunction &MF, const MachineOutlinerInfo &MInfo) const
Insert a custom epilogue for outlined functions.
virtual bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr &MI, unsigned Reg, bool UnfoldLoad, bool UnfoldStore, SmallVectorImpl< MachineInstr *> &NewMIs) const
unfoldMemoryOperand - Separate a single instruction which folded a load or a store or a load and a st...
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
MachineOutlinerInstrType
Represents how an instruction should be mapped by the outliner.
virtual bool hasLowDefLatency(const TargetSchedModel &SchedModel, const MachineInstr &DefMI, unsigned DefIdx) const
Compute operand latency of a def of &#39;Reg&#39;.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:293
virtual MachineInstr * convertToThreeAddress(MachineFunction::iterator &MFI, MachineInstr &MI, LiveVariables *LV) const
This method must be implemented by targets that set the M_CONVERTIBLE_TO_3_ADDR flag.
virtual bool isBasicBlockPrologue(const MachineInstr &MI) const
True if the instruction is bound to the top of its basic block and no other instructions shall be ins...
unsigned getCatchReturnOpcode() const
bool isSelect() const
Return true if this is a select instruction.
Definition: MCInstrDesc.h:314
virtual ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags() const
Return an array that contains the direct target flag values and their names.
virtual void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const
Emit instructions to copy a pair of physical registers.
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
Definition: MachineInstr.h:290
virtual MachineInstr * foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, int FrameIndex, LiveIntervals *LIS=nullptr) const
Target-dependent implementation for foldMemoryOperand.
static bool isEqual(const Function &Caller, const Function &Callee)
virtual unsigned getInstrLatency(const InstrItineraryData *ItinData, const MachineInstr &MI, unsigned *PredCost=nullptr) const
Compute the instruction latency of a given instruction.
const TargetRegisterClass * getRegClass(const MCInstrDesc &TID, unsigned OpNum, const TargetRegisterInfo *TRI, const MachineFunction &MF) const
Given a machine instruction descriptor, returns the register class constraint for OpNum...
virtual bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N, SmallVectorImpl< SDNode *> &NewNodes) const
bool isRematerializable() const
Returns true if this instruction is a candidate for remat.
Definition: MCInstrDesc.h:469
virtual bool getMachineCombinerPatterns(MachineInstr &Root, SmallVectorImpl< MachineCombinerPattern > &Patterns) const
Return true when there is potentially a faster code sequence for an instruction chain ending in Root...
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:33
virtual bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, unsigned ExtraPredCycles, BranchProbability Probability) const
Return true if it&#39;s profitable to predicate instructions with accumulated instruction latency of "Num...
virtual unsigned isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const
If the specified machine instruction is a direct store to a stack slot, return the virtual or physica...
Itinerary data supplied by a subtarget to be used by a target.
virtual bool getBaseAndOffsetPosition(const MachineInstr &MI, unsigned &BasePos, unsigned &OffsetPos) const
Return true if the instruction contains a base register and offset.
virtual ArrayRef< std::pair< MachineMemOperand::Flags, const char * > > getSerializableMachineMemOperandTargetFlags() const
Return an array that contains the MMO target flag values and their names.
RegSubRegPairAndIdx(unsigned Reg=0, unsigned SubReg=0, unsigned SubIdx=0)
TargetInstrInfo & operator=(const TargetInstrInfo &)=delete
virtual MachineInstr * optimizeSelect(MachineInstr &MI, SmallPtrSetImpl< MachineInstr *> &NewMIs, bool PreferFalse=false) const
Given a select instruction that was understood by analyzeSelect and returned Optimizable = true...
virtual bool areMemAccessesTriviallyDisjoint(MachineInstr &MIa, MachineInstr &MIb, AliasAnalysis *AA=nullptr) const
Sometimes, it is possible for the target to tell, even without aliasing information, that two MIs access different memory addresses.
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:159
BasicBlockListType::iterator iterator
virtual bool isFunctionSafeToOutlineFrom(MachineFunction &MF, bool OutlineFromLinkOnceODRs) const
Return true if the function can safely be outlined from.
TargetInstrInfo - Interface to description of machine instruction set.
bool isReturn(QueryType Type=AnyInBundle) const
Definition: MachineInstr.h:457
virtual void getNoop(MCInst &NopInst) const
Return the noop instruction to use for a noop.
This class is intended to be used as a base class for asm properties and features specific to the tar...
Definition: MCAsmInfo.h:56
virtual unsigned isStoreToStackSlotPostFE(const MachineInstr &MI, int &FrameIndex) const
Check for post-frame ptr elimination stack locations as well.
TargetInstrInfo::RegSubRegPair RegSubRegPair
bool usePreRAHazardRecognizer() const
Provide a global flag for disabling the PreRA hazard recognizer that targets may choose to honor...
static const unsigned CommuteAnyOperandIndex
bool mayStore(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly modify memory.
Definition: MachineInstr.h:642
virtual MachineInstr * commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned OpIdx1, unsigned OpIdx2) const
This method commutes the operands of the given machine instruction MI.
virtual void ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail, MachineBasicBlock *NewDest) const
Delete the instruction OldInst and everything after it, replacing it with an unconditional branch to ...
Describes the number of instructions that it will take to call and construct a frame for a given outl...
unsigned const MachineRegisterInfo * MRI
virtual bool isBranchOffsetInRange(unsigned BranchOpc, int64_t BrOffset) const
virtual unsigned getPredicationCost(const MachineInstr &MI) const
HazardRecognizer - This determines whether or not an instruction can be issued this cycle...
virtual bool getMemOpBaseRegImmOfs(MachineInstr &MemOp, unsigned &BaseReg, int64_t &Offset, const TargetRegisterInfo *TRI) const
Get the base register and byte offset of an instruction that reads/writes memory. ...
virtual bool getInsertSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx, RegSubRegPair &BaseReg, RegSubRegPairAndIdx &InsertedReg) const
Target-dependent implementation of getInsertSubregInputs.
unsigned insertUnconditionalBranch(MachineBasicBlock &MBB, MachineBasicBlock *DestBB, const DebugLoc &DL, int *BytesAdded=nullptr) const
MachineInstrBuilder & UseMI
virtual bool isLegalToSplitMBBAt(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) const
Return true if it&#39;s legal to split the given basic block at the specified instruction (i...
unsigned CallConstructionID
Represents the specific instructions that must be emitted to construct a call to this candidate...
virtual unsigned getNumMicroOps(const InstrItineraryData *ItinData, const MachineInstr &MI) const
Return the number of u-operations the given machine instruction will be decoded to on the target cpu...
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:24
virtual bool verifyInstruction(const MachineInstr &MI, StringRef &ErrInfo) const
Perform target-specific instruction verification.
unsigned getCallFrameSetupOpcode() const
These methods return the opcode of the frame setup/destroy instructions if they exist (-1 otherwise)...
virtual ScheduleHazardRecognizer * CreateTargetPostRAHazardRecognizer(const MachineFunction &MF) const
Allocate and return a hazard recognizer to use for by non-scheduling passes.
bool isReassociationCandidate(const MachineInstr &Inst, bool &Commuted) const
Return true if the input Inst is part of a chain of dependent ops that are suitable for reassociatio...
virtual void insertOutlinerPrologue(MachineBasicBlock &MBB, MachineFunction &MF, const MachineOutlinerInfo &MInfo) const
Insert a custom prologue for outlined functions.
virtual void setSpecialOperandAttr(MachineInstr &OldMI1, MachineInstr &OldMI2, MachineInstr &NewMI1, MachineInstr &NewMI2) const
This is an architecture-specific helper function of reassociateOps.
unsigned FrameOverhead
Number of instructions to construct an outlined function frame for this candidate.
bool isPredicable() const
Return true if this instruction has a predicate operand that controls execution.
Definition: MCInstrDesc.h:301
virtual MachineOutlinerInfo getOutlininingCandidateInfo(std::vector< std::pair< MachineBasicBlock::iterator, MachineBasicBlock::iterator >> &RepeatedSequenceLocs) const
Returns a MachineOutlinerInfo struct containing target-specific information for a set of outlining ca...
virtual bool shouldSink(const MachineInstr &MI) const
Return true if the instruction should be sunk by MachineSink.
virtual unsigned getInlineAsmLength(const char *Str, const MCAsmInfo &MAI) const
Measure the specified inline asm to determine an approximation of its length.
MachineCombinerPattern
These are instruction patterns matched by the machine combiner pass.
virtual bool getStackSlotRange(const TargetRegisterClass *RC, unsigned SubIdx, unsigned &Size, unsigned &Offset, const MachineFunction &MF) const
Compute the size in bytes and offset within a stack slot of a spilled register or subregister...
virtual MachineOutlinerInstrType getOutliningType(MachineBasicBlock::iterator &MIT, unsigned Flags) const
Returns how or if MI should be outlined.
virtual bool PredicateInstruction(MachineInstr &MI, ArrayRef< MachineOperand > Pred) const
Convert the instruction into a predicated instruction.
virtual bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify=false) const
Analyze the branching code at the end of MBB, returning true if it cannot be understood (e...
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
virtual bool canMakeTailCallConditional(SmallVectorImpl< MachineOperand > &Cond, const MachineInstr &TailCall) const
Returns true if the tail call can be made conditional on BranchCond.
virtual bool isPredicated(const MachineInstr &MI) const
Returns true if the instruction is already predicated.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
virtual bool analyzeCompare(const MachineInstr &MI, unsigned &SrcReg, unsigned &SrcReg2, int &Mask, int &Value) const
For a comparison instruction, return the source registers in SrcReg and SrcReg2 if having two registe...
virtual bool isStackSlotCopy(const MachineInstr &MI, int &DestFrameIndex, int &SrcFrameIndex) const
Return true if the specified machine instruction is a copy of one stack slot to another and has no ot...
virtual bool isAsCheapAsAMove(const MachineInstr &MI) const
Return true if the instruction is as cheap as a move instruction.
virtual bool isSchedulingBoundary(const MachineInstr &MI, const MachineBasicBlock *MBB, const MachineFunction &MF) const
Test if the given instruction should be considered a scheduling boundary.
virtual bool optimizeCondBranch(MachineInstr &MI) const
virtual unsigned getAddressSpaceForPseudoSourceKind(PseudoSourceValue::PSVKind Kind) const
getAddressSpaceForPseudoSourceKind - Given the kind of memory (e.g.
virtual bool hasLoadFromStackSlot(const MachineInstr &MI, const MachineMemOperand *&MMO, int &FrameIndex) const
If the specified machine instruction has a load from a stack slot, return true along with the FrameIn...
void reassociateOps(MachineInstr &Root, MachineInstr &Prev, MachineCombinerPattern Pattern, SmallVectorImpl< MachineInstr *> &InsInstrs, SmallVectorImpl< MachineInstr *> &DelInstrs, DenseMap< unsigned, unsigned > &InstrIdxForVirtReg) const
Attempt to reassociate Root and Prev according to Pattern to reduce critical path length...
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:210
MachineOperand class - Representation of each machine instruction operand.
A pair composed of a register and a sub-register index.
virtual bool hasHighOperandLatency(const TargetSchedModel &SchedModel, const MachineRegisterInfo *MRI, const MachineInstr &DefMI, unsigned DefIdx, const MachineInstr &UseMI, unsigned UseIdx) const
Compute operand latency between a def of &#39;Reg&#39; and a use in the current loop.
MachineInstrBuilder MachineInstrBuilder & DefMI
Predicate
Predicate - These are "(BI << 5) | BO" for various predicates.
Definition: PPCPredicates.h:27
bool isFrameInstr(const MachineInstr &I) const
Returns true if the argument is a frame pseudo instruction.
virtual bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, BranchProbability Probability) const
Return true if it&#39;s profitable for if-converter to duplicate instructions of specified accumulated in...
virtual bool isCoalescableExtInstr(const MachineInstr &MI, unsigned &SrcReg, unsigned &DstReg, unsigned &SubIdx) const
Return true if the instruction is a "coalescable" extension instruction.
Represents one node in the SelectionDAG.
virtual unsigned insertIndirectBranch(MachineBasicBlock &MBB, MachineBasicBlock &NewDestBB, const DebugLoc &DL, int64_t BrOffset=0, RegScavenger *RS=nullptr) const
Insert an unconditional indirect branch at the end of MBB to NewDestBB.
virtual bool isTailCall(const MachineInstr &Inst) const
Determines whether Inst is a tail call instruction.
int64_t getFrameSize(const MachineInstr &I) const
Returns size of the frame associated with the given frame instruction.
int64_t getImm() const
bool getRegSequenceInputs(const MachineInstr &MI, unsigned DefIdx, SmallVectorImpl< RegSubRegPairAndIdx > &InputRegs) const
Build the equivalent inputs of a REG_SEQUENCE for the given MI and DefIdx.
virtual bool findCommutedOpIndices(MachineInstr &MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) const
Returns true iff the routine could find two commutable operands in the given machine instruction...
MachineOutlinerInfo(unsigned CallOverhead, unsigned FrameOverhead, unsigned CallConstructionID, unsigned FrameConstructionID)
virtual bool isPredicable(const MachineInstr &MI) const
Return true if the specified instruction can be predicated.
virtual bool hasStoreToStackSlot(const MachineInstr &MI, const MachineMemOperand *&MMO, int &FrameIndex) const
If the specified machine instruction has a store to a stack slot, return true along with the FrameInd...
unsigned getReturnOpcode() const
virtual void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const
Store the specified register of the given register class to the specified stack frame index...
virtual bool shouldClusterMemOps(MachineInstr &FirstLdSt, unsigned BaseReg1, MachineInstr &SecondLdSt, unsigned BaseReg2, unsigned NumLoads) const
Returns true if the two given memory operations should be scheduled adjacent.
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
TargetSubtargetInfo - Generic base class for all target subtargets.
virtual void insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const
Insert a noop into the instruction stream at the specified point.
Representation of each machine instruction.
Definition: MachineInstr.h:60
static TargetInstrInfo::RegSubRegPair getEmptyKey()
virtual ArrayRef< std::pair< int, const char * > > getSerializableTargetIndices() const
Return an array that contains the ids of the target indices (used for the TargetIndex machine operand...
virtual bool analyzeLoop(MachineLoop &L, MachineInstr *&IndVarInst, MachineInstr *&CmpInst) const
Analyze the loop code, return true if it cannot be understoo.
static bool fixCommutedOpIndices(unsigned &ResultIdx1, unsigned &ResultIdx2, unsigned CommutableOpIdx1, unsigned CommutableOpIdx2)
Assigns the (CommutableOpIdx1, CommutableOpIdx2) pair of commutable operand indices to (ResultIdx1...
virtual bool SubsumesPredicate(ArrayRef< MachineOperand > Pred1, ArrayRef< MachineOperand > Pred2) const
Returns true if the first specified predicate subsumes the second, e.g.
virtual void breakPartialRegDependency(MachineInstr &MI, unsigned OpNum, const TargetRegisterInfo *TRI) const
Insert a dependency-breaking instruction before MI to eliminate an unwanted dependency on OpNum...
virtual ScheduleHazardRecognizer * CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI, const ScheduleDAG *DAG) const
Allocate and return a hazard recognizer to use for this target when scheduling the machine instructio...
virtual unsigned isLoadFromStackSlotPostFE(const MachineInstr &MI, int &FrameIndex) const
Check for post-frame ptr elimination stack locations as well.
virtual bool analyzeBranchPredicate(MachineBasicBlock &MBB, MachineBranchPredicate &MBP, bool AllowModify=false) const
Analyze the branching code at the end of MBB and parse it into the MachineBranchPredicate structure i...
virtual MachineBasicBlock::iterator insertOutlinedCall(Module &M, MachineBasicBlock &MBB, MachineBasicBlock::iterator &It, MachineFunction &MF, const MachineOutlinerInfo &MInfo) const
Insert a call to an outlined function into the program.
virtual unsigned isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const
If the specified machine instruction is a direct load from a stack slot, return the virtual or physic...
static MachineOperand CreateImm(int64_t Val)
#define I(x, y, z)
Definition: MD5.cpp:58
#define N
virtual bool produceSameValue(const MachineInstr &MI0, const MachineInstr &MI1, const MachineRegisterInfo *MRI=nullptr) const
Return true if two machine instructions would produce identical values.
bool isZeroCost(unsigned Opcode) const
Return true for pseudo instructions that don&#39;t consume any machine resources in their current form...
virtual std::pair< uint16_t, uint16_t > getExecutionDomain(const MachineInstr &MI) const
Return the current execution domain and bit mask of possible domains for instruction.
virtual MachineInstr * optimizeLoadInstr(MachineInstr &MI, const MachineRegisterInfo *MRI, unsigned &FoldAsLoadDefReg, MachineInstr *&DefMI) const
Try to remove the load by folding it to a register operand at the use.
unsigned CallOverhead
Number of instructions to call an outlined function for this candidate.
const unsigned Kind
virtual bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const
Reverses the branch condition of the specified condition list, returning false on success and true if...
virtual bool isSubregFoldable() const
Check whether the target can fold a load that feeds a subreg operand (or a subreg operand that feeds ...
bool mayLoad(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read memory.
Definition: MachineInstr.h:629
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
bool isFrameSetup(const MachineInstr &I) const
Returns true if the argument is a frame setup pseudo instruction.
virtual bool isProfitableToIfCvt(MachineBasicBlock &TMBB, unsigned NumTCycles, unsigned ExtraTCycles, MachineBasicBlock &FMBB, unsigned NumFCycles, unsigned ExtraFCycles, BranchProbability Probability) const
Second variant of isProfitableToIfCvt.
LLVM Value Representation.
Definition: Value.h:73
virtual MachineBasicBlock * getBranchDestBlock(const MachineInstr &MI) const
bool hasReassociableSibling(const MachineInstr &Inst, bool &Commuted) const
Return true when Inst has reassociable sibling.
constexpr char Size[]
Key for Kernel::Arg::Metadata::mSize.
virtual ScheduleHazardRecognizer * CreateTargetMIHazardRecognizer(const InstrItineraryData *, const ScheduleDAG *DAG) const
Allocate and return a hazard recognizer to use for this target when scheduling the machine instructio...
virtual bool isAssociativeAndCommutative(const MachineInstr &Inst) const
Return true when Inst is both associative and commutative.
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E&#39;s largest value.
Definition: BitmaskEnum.h:81
unsigned FrameConstructionID
Represents the specific instructions that must be emitted to construct a frame for this candidate&#39;s o...
virtual void replaceBranchWithTailCall(MachineBasicBlock &MBB, SmallVectorImpl< MachineOperand > &Cond, const MachineInstr &TailCall) const
Replace the conditional branch in MBB with a conditional tail call.
IRTranslator LLVM IR MI
virtual bool isPostIncrement(const MachineInstr &MI) const
Return true for post-incremented instructions.
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:49
virtual bool isUnconditionalTailCall(const MachineInstr &MI) const
Returns true if MI is an unconditional tail call.
virtual bool getRegSequenceLikeInputs(const MachineInstr &MI, unsigned DefIdx, SmallVectorImpl< RegSubRegPairAndIdx > &InputRegs) const
Target-dependent implementation of getRegSequenceInputs.
bool getExtractSubregInputs(const MachineInstr &MI, unsigned DefIdx, RegSubRegPairAndIdx &InputReg) const
Build the equivalent inputs of a EXTRACT_SUBREG for the given MI and DefIdx.
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:298
virtual unsigned getMachineOutlinerMBBFlags(MachineBasicBlock &MBB) const
Returns target-defined flags defining properties of the MBB for the outliner.
bool isTriviallyReMaterializable(const MachineInstr &MI, AliasAnalysis *AA=nullptr) const
Return true if the instruction is trivially rematerializable, meaning it has no side effects and requ...
Machine model for scheduling, bundling, and heuristics.
Definition: MCSchedule.h:136
static bool isEqual(const TargetInstrInfo::RegSubRegPair &LHS, const TargetInstrInfo::RegSubRegPair &RHS)
bool getInsertSubregInputs(const MachineInstr &MI, unsigned DefIdx, RegSubRegPair &BaseReg, RegSubRegPairAndIdx &InsertedReg) const
Build the equivalent inputs of a INSERT_SUBREG for the given MI and DefIdx.
virtual ScheduleHazardRecognizer * CreateTargetPostRAHazardRecognizer(const InstrItineraryData *, const ScheduleDAG *DAG) const
Allocate and return a hazard recognizer to use for this target when scheduling the machine instructio...
virtual bool isProfitableToUnpredicate(MachineBasicBlock &TMBB, MachineBasicBlock &FMBB) const
Return true if it&#39;s profitable to unpredicate one side of a &#39;diamond&#39;, i.e.
int computeDefOperandLatency(const InstrItineraryData *ItinData, const MachineInstr &DefMI) const
If we can determine the operand latency from the def only, without itinerary lookup, do so.
virtual unsigned getOpcodeAfterMemoryUnfold(unsigned Opc, bool UnfoldLoad, bool UnfoldStore, unsigned *LoadRegIndex=nullptr) const
Returns the opcode of the would be new instruction after load / store are unfolded from an instructio...
virtual int getOperandLatency(const InstrItineraryData *ItinData, SDNode *DefNode, unsigned DefIdx, SDNode *UseNode, unsigned UseIdx) const
virtual void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const
Load the specified register of the given register class from the specified stack frame index...
bool isAsCheapAsAMove(QueryType Type=AllInBundle) const
Returns true if this instruction has the same cost (or less) than a move instruction.
Definition: MachineInstr.h:728
virtual bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, int64_t Offset1, int64_t Offset2, unsigned NumLoads) const
This is a used by the pre-regalloc scheduler to determine (in conjunction with areLoadsFromSameBasePt...
virtual int getSPAdjust(const MachineInstr &MI) const
Returns the actual stack pointer adjustment made by an instruction as part of a call sequence...
virtual unsigned getUndefRegClearance(const MachineInstr &MI, unsigned &OpNum, const TargetRegisterInfo *TRI) const
Return the minimum clearance before an instruction that reads an unused register. ...
A pair composed of a pair of a register and a sub-register index, and another sub-register index...