LLVM  6.0.0svn
Public Types | Public Member Functions | Public Attributes | List of all members
llvm::TargetRegisterClass Class Reference

#include "llvm/CodeGen/TargetRegisterInfo.h"

Collaboration diagram for llvm::TargetRegisterClass:
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Public Types

using iterator = const MCPhysReg *
 
using const_iterator = const MCPhysReg *
 
using sc_iterator = const TargetRegisterClass *const *
 

Public Member Functions

unsigned getID () const
 Return the register class ID number. More...
 
iterator begin () const
 begin/end - Return all of the registers in this class. More...
 
iterator end () const
 
unsigned getNumRegs () const
 Return the number of registers in this class. More...
 
iterator_range< SmallVectorImpl< MCPhysReg >::const_iteratorgetRegisters () const
 
unsigned getRegister (unsigned i) const
 Return the specified register in the class. More...
 
bool contains (unsigned Reg) const
 Return true if the specified register is included in this register class. More...
 
bool contains (unsigned Reg1, unsigned Reg2) const
 Return true if both registers are in this class. More...
 
int getCopyCost () const
 Return the cost of copying a value between two registers in this class. More...
 
bool isAllocatable () const
 Return true if this register class may be used to create virtual registers. More...
 
bool hasSubClass (const TargetRegisterClass *RC) const
 Return true if the specified TargetRegisterClass is a proper sub-class of this TargetRegisterClass. More...
 
bool hasSubClassEq (const TargetRegisterClass *RC) const
 Returns true if RC is a sub-class of or equal to this class. More...
 
bool hasSuperClass (const TargetRegisterClass *RC) const
 Return true if the specified TargetRegisterClass is a proper super-class of this TargetRegisterClass. More...
 
bool hasSuperClassEq (const TargetRegisterClass *RC) const
 Returns true if RC is a super-class of or equal to this class. More...
 
const uint32_tgetSubClassMask () const
 Returns a bit vector of subclasses, including this one. More...
 
const uint16_t * getSuperRegIndices () const
 Returns a 0-terminated list of sub-register indices that project some super-register class into this register class. More...
 
sc_iterator getSuperClasses () const
 Returns a NULL-terminated list of super-classes. More...
 
bool isASubClass () const
 Return true if this TargetRegisterClass is a subset class of at least one other TargetRegisterClass. More...
 
ArrayRef< MCPhysReggetRawAllocationOrder (const MachineFunction &MF) const
 Returns the preferred order for allocating registers from this register class in MF. More...
 
LaneBitmask getLaneMask () const
 Returns the combination of all lane masks of register in this class. More...
 

Public Attributes

const MCRegisterClassMC
 
const uint32_tSubClassMask
 
const uint16_t * SuperRegIndices
 
const LaneBitmask LaneMask
 
const uint8_t AllocationPriority
 Classes with a higher priority value are assigned first by register allocators using a greedy heuristic. More...
 
const bool HasDisjunctSubRegs
 Whether the class supports two (or more) disjunct subregister indices. More...
 
const bool CoveredBySubRegs
 Whether a combination of subregisters can cover every register in the class. More...
 
const sc_iterator SuperClasses
 
ArrayRef< MCPhysReg >(* OrderFunc )(const MachineFunction &)
 

Detailed Description

Definition at line 45 of file TargetRegisterInfo.h.

Member Typedef Documentation

◆ const_iterator

Definition at line 48 of file TargetRegisterInfo.h.

◆ iterator

Definition at line 47 of file TargetRegisterInfo.h.

◆ sc_iterator

Definition at line 49 of file TargetRegisterInfo.h.

Member Function Documentation

◆ begin()

iterator llvm::TargetRegisterClass::begin ( ) const
inline

◆ contains() [1/2]

bool llvm::TargetRegisterClass::contains ( unsigned  Reg) const
inline

◆ contains() [2/2]

bool llvm::TargetRegisterClass::contains ( unsigned  Reg1,
unsigned  Reg2 
) const
inline

Return true if both registers are in this class.

Definition at line 95 of file TargetRegisterInfo.h.

References llvm::MCRegisterClass::contains().

◆ end()

iterator llvm::TargetRegisterClass::end ( ) const
inline

◆ getCopyCost()

int llvm::TargetRegisterClass::getCopyCost ( ) const
inline

Return the cost of copying a value between two registers in this class.

A negative number means the register class is very expensive to copy e.g. status flag register classes.

Definition at line 102 of file TargetRegisterInfo.h.

References llvm::MCRegisterClass::getCopyCost().

Referenced by CheckForPhysRegDependency(), and countOperands().

◆ getID()

unsigned llvm::TargetRegisterClass::getID ( ) const
inline

◆ getLaneMask()

LaneBitmask llvm::TargetRegisterClass::getLaneMask ( ) const
inline

Returns the combination of all lane masks of register in this class.

The lane masks of the registers are the combination of all lane masks of their subregisters. Returns 1 if there are no subregisters.

Definition at line 195 of file TargetRegisterInfo.h.

References LaneMask.

Referenced by llvm::ScheduleDAGInstrs::getLaneMaskForMO(), and llvm::MachineRegisterInfo::getMaxLaneMaskForVReg().

◆ getNumRegs()

unsigned llvm::TargetRegisterClass::getNumRegs ( ) const
inline

◆ getRawAllocationOrder()

ArrayRef<MCPhysReg> llvm::TargetRegisterClass::getRawAllocationOrder ( const MachineFunction MF) const
inline

Returns the preferred order for allocating registers from this register class in MF.

The raw order comes directly from the .td file and may include reserved registers that are not allocatable. Register allocators should also make sure to allocate callee-saved registers only after all the volatiles are used. The RegisterClassInfo class provides filtered allocation orders with callee-saved registers moved to the end.

The MachineFunction argument can be used to tune the allocatable registers based on the characteristics of the function, subtarget, or other criteria.

By default, this method returns all registers in the class.

Definition at line 188 of file TargetRegisterInfo.h.

References begin(), getNumRegs(), llvm::makeArrayRef(), and OrderFunc.

Referenced by llvm::HexagonFrameLowering::determineCalleeSaves(), getAllocatableSetForRC(), isACalleeSavedRegister(), llvm::RegisterClassInfo::runOnMachineFunction(), and llvm::RegScavenger::scavengeRegisterBackwards().

◆ getRegister()

unsigned llvm::TargetRegisterClass::getRegister ( unsigned  i) const
inline

◆ getRegisters()

iterator_range<SmallVectorImpl<MCPhysReg>::const_iterator> llvm::TargetRegisterClass::getRegisters ( ) const
inline

◆ getSubClassMask()

const uint32_t* llvm::TargetRegisterClass::getSubClassMask ( ) const
inline

Returns a bit vector of subclasses, including this one.

The vector is indexed by class IDs.

To use it, consider the returned array as a chunk of memory that contains an array of bits of size NumRegClasses. Each 32-bit chunk contains a bitset of the ID of the subclasses in big-endian style. I.e., the representation of the memory from left to right at the bit level looks like: [31 30 ... 1 0] [ 63 62 ... 33 32] ... [ XXX NumRegClasses NumRegClasses - 1 ... ] Where the number represents the class ID and XXX bits that should be ignored.

See the implementation of hasSubClassEq for an example of how it can be used.

Definition at line 147 of file TargetRegisterInfo.h.

References SubClassMask.

Referenced by llvm::TargetRegisterInfo::getAllocatableClass(), llvm::TargetRegisterInfo::getCommonSubClass(), and llvm::TargetRegisterInfo::getMatchingSuperRegClass().

◆ getSuperClasses()

sc_iterator llvm::TargetRegisterClass::getSuperClasses ( ) const
inline

Returns a NULL-terminated list of super-classes.

The classes are ordered by ID which is also a topological ordering from large to small classes. The list does NOT include the current class.

Definition at line 165 of file TargetRegisterInfo.h.

References SuperClasses.

Referenced by llvm::HexagonRegisterInfo::getHexagonSubRegIndex(), llvm::X86RegisterInfo::getLargestLegalSuperClass(), and llvm::ARMBaseRegisterInfo::getLargestLegalSuperClass().

◆ getSuperRegIndices()

const uint16_t* llvm::TargetRegisterClass::getSuperRegIndices ( ) const
inline

Returns a 0-terminated list of sub-register indices that project some super-register class into this register class.

The list has an entry for each Idx such that:

There exists SuperRC where: For all Reg in SuperRC: this->contains(Reg:Idx)

Definition at line 158 of file TargetRegisterInfo.h.

References SuperRegIndices.

◆ hasSubClass()

bool llvm::TargetRegisterClass::hasSubClass ( const TargetRegisterClass RC) const
inline

Return true if the specified TargetRegisterClass is a proper sub-class of this TargetRegisterClass.

Definition at line 110 of file TargetRegisterInfo.h.

References hasSubClassEq().

Referenced by llvm::TargetRegisterInfo::getMinimalPhysRegClass(), and hasSuperClass().

◆ hasSubClassEq()

bool llvm::TargetRegisterClass::hasSubClassEq ( const TargetRegisterClass RC) const
inline

◆ hasSuperClass()

bool llvm::TargetRegisterClass::hasSuperClass ( const TargetRegisterClass RC) const
inline

Return true if the specified TargetRegisterClass is a proper super-class of this TargetRegisterClass.

Definition at line 122 of file TargetRegisterInfo.h.

References hasSubClass().

◆ hasSuperClassEq()

bool llvm::TargetRegisterClass::hasSuperClassEq ( const TargetRegisterClass RC) const
inline

Returns true if RC is a super-class of or equal to this class.

Definition at line 127 of file TargetRegisterInfo.h.

References hasSubClassEq().

Referenced by getComparePred(), llvm::PPCInstrInfo::getOperandLatency(), isFPR64(), isFRClass(), isGRClass(), matchPair(), llvm::SystemZRegisterInfo::shouldCoalesce(), and swapMIOperands().

◆ isAllocatable()

bool llvm::TargetRegisterClass::isAllocatable ( ) const
inline

◆ isASubClass()

bool llvm::TargetRegisterClass::isASubClass ( ) const
inline

Return true if this TargetRegisterClass is a subset class of at least one other TargetRegisterClass.

Definition at line 171 of file TargetRegisterInfo.h.

Member Data Documentation

◆ AllocationPriority

const uint8_t llvm::TargetRegisterClass::AllocationPriority

Classes with a higher priority value are assigned first by register allocators using a greedy heuristic.

The value is in the range [0,63].

Definition at line 58 of file TargetRegisterInfo.h.

Referenced by llvm::createGreedyRegisterAllocator().

◆ CoveredBySubRegs

const bool llvm::TargetRegisterClass::CoveredBySubRegs

Whether a combination of subregisters can cover every register in the class.

See also the CoveredBySubRegs description in Target.td.

Definition at line 63 of file TargetRegisterInfo.h.

Referenced by isCrossCopy().

◆ HasDisjunctSubRegs

const bool llvm::TargetRegisterClass::HasDisjunctSubRegs

Whether the class supports two (or more) disjunct subregister indices.

Definition at line 60 of file TargetRegisterInfo.h.

Referenced by llvm::ScheduleDAGInstrs::getLaneMaskForMO(), and llvm::MachineRegisterInfo::shouldTrackSubRegLiveness().

◆ LaneMask

const LaneBitmask llvm::TargetRegisterClass::LaneMask

◆ MC

const MCRegisterClass* llvm::TargetRegisterClass::MC

◆ OrderFunc

ArrayRef<MCPhysReg>(* llvm::TargetRegisterClass::OrderFunc) (const MachineFunction &)

Definition at line 65 of file TargetRegisterInfo.h.

Referenced by getRawAllocationOrder().

◆ SubClassMask

const uint32_t* llvm::TargetRegisterClass::SubClassMask

Definition at line 53 of file TargetRegisterInfo.h.

Referenced by getSubClassMask().

◆ SuperClasses

const sc_iterator llvm::TargetRegisterClass::SuperClasses

Definition at line 64 of file TargetRegisterInfo.h.

Referenced by getSuperClasses().

◆ SuperRegIndices

const uint16_t* llvm::TargetRegisterClass::SuperRegIndices

Definition at line 54 of file TargetRegisterInfo.h.

Referenced by getSuperRegIndices().


The documentation for this class was generated from the following file: