LLVM  9.0.0svn
SelectionDAGBuilder.cpp
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1 //===- SelectionDAGBuilder.cpp - Selection-DAG building -------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This implements routines for translating from LLVM IR into SelectionDAG IR.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "SelectionDAGBuilder.h"
14 #include "SDNodeDbgValue.h"
15 #include "llvm/ADT/APFloat.h"
16 #include "llvm/ADT/APInt.h"
17 #include "llvm/ADT/ArrayRef.h"
18 #include "llvm/ADT/BitVector.h"
19 #include "llvm/ADT/DenseMap.h"
20 #include "llvm/ADT/None.h"
21 #include "llvm/ADT/Optional.h"
22 #include "llvm/ADT/STLExtras.h"
23 #include "llvm/ADT/SmallPtrSet.h"
24 #include "llvm/ADT/SmallSet.h"
25 #include "llvm/ADT/SmallVector.h"
26 #include "llvm/ADT/StringRef.h"
27 #include "llvm/ADT/Triple.h"
28 #include "llvm/ADT/Twine.h"
33 #include "llvm/Analysis/Loads.h"
38 #include "llvm/CodeGen/Analysis.h"
56 #include "llvm/CodeGen/StackMaps.h"
66 #include "llvm/IR/Argument.h"
67 #include "llvm/IR/Attributes.h"
68 #include "llvm/IR/BasicBlock.h"
69 #include "llvm/IR/CFG.h"
70 #include "llvm/IR/CallSite.h"
71 #include "llvm/IR/CallingConv.h"
72 #include "llvm/IR/Constant.h"
73 #include "llvm/IR/ConstantRange.h"
74 #include "llvm/IR/Constants.h"
75 #include "llvm/IR/DataLayout.h"
77 #include "llvm/IR/DebugLoc.h"
78 #include "llvm/IR/DerivedTypes.h"
79 #include "llvm/IR/Function.h"
81 #include "llvm/IR/InlineAsm.h"
82 #include "llvm/IR/InstrTypes.h"
83 #include "llvm/IR/Instruction.h"
84 #include "llvm/IR/Instructions.h"
85 #include "llvm/IR/IntrinsicInst.h"
86 #include "llvm/IR/Intrinsics.h"
87 #include "llvm/IR/LLVMContext.h"
88 #include "llvm/IR/Metadata.h"
89 #include "llvm/IR/Module.h"
90 #include "llvm/IR/Operator.h"
91 #include "llvm/IR/PatternMatch.h"
92 #include "llvm/IR/Statepoint.h"
93 #include "llvm/IR/Type.h"
94 #include "llvm/IR/User.h"
95 #include "llvm/IR/Value.h"
96 #include "llvm/MC/MCContext.h"
97 #include "llvm/MC/MCSymbol.h"
100 #include "llvm/Support/Casting.h"
101 #include "llvm/Support/CodeGen.h"
103 #include "llvm/Support/Compiler.h"
104 #include "llvm/Support/Debug.h"
107 #include "llvm/Support/MathExtras.h"
113 #include <algorithm>
114 #include <cassert>
115 #include <cstddef>
116 #include <cstdint>
117 #include <cstring>
118 #include <iterator>
119 #include <limits>
120 #include <numeric>
121 #include <tuple>
122 #include <utility>
123 #include <vector>
124 
125 using namespace llvm;
126 using namespace PatternMatch;
127 using namespace SwitchCG;
128 
129 #define DEBUG_TYPE "isel"
130 
131 /// LimitFloatPrecision - Generate low-precision inline sequences for
132 /// some float libcalls (6, 8 or 12 bits).
133 static unsigned LimitFloatPrecision;
134 
136  LimitFPPrecision("limit-float-precision",
137  cl::desc("Generate low-precision inline sequences "
138  "for some float libcalls"),
139  cl::location(LimitFloatPrecision), cl::Hidden,
140  cl::init(0));
141 
143  "switch-peel-threshold", cl::Hidden, cl::init(66),
144  cl::desc("Set the case probability threshold for peeling the case from a "
145  "switch statement. A value greater than 100 will void this "
146  "optimization"));
147 
148 // Limit the width of DAG chains. This is important in general to prevent
149 // DAG-based analysis from blowing up. For example, alias analysis and
150 // load clustering may not complete in reasonable time. It is difficult to
151 // recognize and avoid this situation within each individual analysis, and
152 // future analyses are likely to have the same behavior. Limiting DAG width is
153 // the safe approach and will be especially important with global DAGs.
154 //
155 // MaxParallelChains default is arbitrarily high to avoid affecting
156 // optimization, but could be lowered to improve compile time. Any ld-ld-st-st
157 // sequence over this should have been converted to llvm.memcpy by the
158 // frontend. It is easy to induce this behavior with .ll code such as:
159 // %buffer = alloca [4096 x i8]
160 // %data = load [4096 x i8]* %argPtr
161 // store [4096 x i8] %data, [4096 x i8]* %buffer
162 static const unsigned MaxParallelChains = 64;
163 
164 // Return the calling convention if the Value passed requires ABI mangling as it
165 // is a parameter to a function or a return value from a function which is not
166 // an intrinsic.
168  if (auto *R = dyn_cast<ReturnInst>(V))
169  return R->getParent()->getParent()->getCallingConv();
170 
171  if (auto *CI = dyn_cast<CallInst>(V)) {
172  const bool IsInlineAsm = CI->isInlineAsm();
173  const bool IsIndirectFunctionCall =
174  !IsInlineAsm && !CI->getCalledFunction();
175 
176  // It is possible that the call instruction is an inline asm statement or an
177  // indirect function call in which case the return value of
178  // getCalledFunction() would be nullptr.
179  const bool IsInstrinsicCall =
180  !IsInlineAsm && !IsIndirectFunctionCall &&
181  CI->getCalledFunction()->getIntrinsicID() != Intrinsic::not_intrinsic;
182 
183  if (!IsInlineAsm && !IsInstrinsicCall)
184  return CI->getCallingConv();
185  }
186 
187  return None;
188 }
189 
190 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, const SDLoc &DL,
191  const SDValue *Parts, unsigned NumParts,
192  MVT PartVT, EVT ValueVT, const Value *V,
194 
195 /// getCopyFromParts - Create a value that contains the specified legal parts
196 /// combined into the value they represent. If the parts combine to a type
197 /// larger than ValueVT then AssertOp can be used to specify whether the extra
198 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
199 /// (ISD::AssertSext).
201  const SDValue *Parts, unsigned NumParts,
202  MVT PartVT, EVT ValueVT, const Value *V,
203  Optional<CallingConv::ID> CC = None,
204  Optional<ISD::NodeType> AssertOp = None) {
205  if (ValueVT.isVector())
206  return getCopyFromPartsVector(DAG, DL, Parts, NumParts, PartVT, ValueVT, V,
207  CC);
208 
209  assert(NumParts > 0 && "No parts to assemble!");
210  const TargetLowering &TLI = DAG.getTargetLoweringInfo();
211  SDValue Val = Parts[0];
212 
213  if (NumParts > 1) {
214  // Assemble the value from multiple parts.
215  if (ValueVT.isInteger()) {
216  unsigned PartBits = PartVT.getSizeInBits();
217  unsigned ValueBits = ValueVT.getSizeInBits();
218 
219  // Assemble the power of 2 part.
220  unsigned RoundParts =
221  (NumParts & (NumParts - 1)) ? 1 << Log2_32(NumParts) : NumParts;
222  unsigned RoundBits = PartBits * RoundParts;
223  EVT RoundVT = RoundBits == ValueBits ?
224  ValueVT : EVT::getIntegerVT(*DAG.getContext(), RoundBits);
225  SDValue Lo, Hi;
226 
227  EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), RoundBits/2);
228 
229  if (RoundParts > 2) {
230  Lo = getCopyFromParts(DAG, DL, Parts, RoundParts / 2,
231  PartVT, HalfVT, V);
232  Hi = getCopyFromParts(DAG, DL, Parts + RoundParts / 2,
233  RoundParts / 2, PartVT, HalfVT, V);
234  } else {
235  Lo = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[0]);
236  Hi = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[1]);
237  }
238 
239  if (DAG.getDataLayout().isBigEndian())
240  std::swap(Lo, Hi);
241 
242  Val = DAG.getNode(ISD::BUILD_PAIR, DL, RoundVT, Lo, Hi);
243 
244  if (RoundParts < NumParts) {
245  // Assemble the trailing non-power-of-2 part.
246  unsigned OddParts = NumParts - RoundParts;
247  EVT OddVT = EVT::getIntegerVT(*DAG.getContext(), OddParts * PartBits);
248  Hi = getCopyFromParts(DAG, DL, Parts + RoundParts, OddParts, PartVT,
249  OddVT, V, CC);
250 
251  // Combine the round and odd parts.
252  Lo = Val;
253  if (DAG.getDataLayout().isBigEndian())
254  std::swap(Lo, Hi);
255  EVT TotalVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
256  Hi = DAG.getNode(ISD::ANY_EXTEND, DL, TotalVT, Hi);
257  Hi =
258  DAG.getNode(ISD::SHL, DL, TotalVT, Hi,
259  DAG.getConstant(Lo.getValueSizeInBits(), DL,
260  TLI.getPointerTy(DAG.getDataLayout())));
261  Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, TotalVT, Lo);
262  Val = DAG.getNode(ISD::OR, DL, TotalVT, Lo, Hi);
263  }
264  } else if (PartVT.isFloatingPoint()) {
265  // FP split into multiple FP parts (for ppcf128)
266  assert(ValueVT == EVT(MVT::ppcf128) && PartVT == MVT::f64 &&
267  "Unexpected split");
268  SDValue Lo, Hi;
269  Lo = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[0]);
270  Hi = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[1]);
271  if (TLI.hasBigEndianPartOrdering(ValueVT, DAG.getDataLayout()))
272  std::swap(Lo, Hi);
273  Val = DAG.getNode(ISD::BUILD_PAIR, DL, ValueVT, Lo, Hi);
274  } else {
275  // FP split into integer parts (soft fp)
276  assert(ValueVT.isFloatingPoint() && PartVT.isInteger() &&
277  !PartVT.isVector() && "Unexpected split");
278  EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits());
279  Val = getCopyFromParts(DAG, DL, Parts, NumParts, PartVT, IntVT, V, CC);
280  }
281  }
282 
283  // There is now one part, held in Val. Correct it to match ValueVT.
284  // PartEVT is the type of the register class that holds the value.
285  // ValueVT is the type of the inline asm operation.
286  EVT PartEVT = Val.getValueType();
287 
288  if (PartEVT == ValueVT)
289  return Val;
290 
291  if (PartEVT.isInteger() && ValueVT.isFloatingPoint() &&
292  ValueVT.bitsLT(PartEVT)) {
293  // For an FP value in an integer part, we need to truncate to the right
294  // width first.
295  PartEVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits());
296  Val = DAG.getNode(ISD::TRUNCATE, DL, PartEVT, Val);
297  }
298 
299  // Handle types that have the same size.
300  if (PartEVT.getSizeInBits() == ValueVT.getSizeInBits())
301  return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
302 
303  // Handle types with different sizes.
304  if (PartEVT.isInteger() && ValueVT.isInteger()) {
305  if (ValueVT.bitsLT(PartEVT)) {
306  // For a truncate, see if we have any information to
307  // indicate whether the truncated bits will always be
308  // zero or sign-extension.
309  if (AssertOp.hasValue())
310  Val = DAG.getNode(*AssertOp, DL, PartEVT, Val,
311  DAG.getValueType(ValueVT));
312  return DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
313  }
314  return DAG.getNode(ISD::ANY_EXTEND, DL, ValueVT, Val);
315  }
316 
317  if (PartEVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
318  // FP_ROUND's are always exact here.
319  if (ValueVT.bitsLT(Val.getValueType()))
320  return DAG.getNode(
321  ISD::FP_ROUND, DL, ValueVT, Val,
322  DAG.getTargetConstant(1, DL, TLI.getPointerTy(DAG.getDataLayout())));
323 
324  return DAG.getNode(ISD::FP_EXTEND, DL, ValueVT, Val);
325  }
326 
327  // Handle MMX to a narrower integer type by bitcasting MMX to integer and
328  // then truncating.
329  if (PartEVT == MVT::x86mmx && ValueVT.isInteger() &&
330  ValueVT.bitsLT(PartEVT)) {
331  Val = DAG.getNode(ISD::BITCAST, DL, MVT::i64, Val);
332  return DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
333  }
334 
335  report_fatal_error("Unknown mismatch in getCopyFromParts!");
336 }
337 
339  const Twine &ErrMsg) {
340  const Instruction *I = dyn_cast_or_null<Instruction>(V);
341  if (!V)
342  return Ctx.emitError(ErrMsg);
343 
344  const char *AsmError = ", possible invalid constraint for vector type";
345  if (const CallInst *CI = dyn_cast<CallInst>(I))
346  if (isa<InlineAsm>(CI->getCalledValue()))
347  return Ctx.emitError(I, ErrMsg + AsmError);
348 
349  return Ctx.emitError(I, ErrMsg);
350 }
351 
352 /// getCopyFromPartsVector - Create a value that contains the specified legal
353 /// parts combined into the value they represent. If the parts combine to a
354 /// type larger than ValueVT then AssertOp can be used to specify whether the
355 /// extra bits are known to be zero (ISD::AssertZext) or sign extended from
356 /// ValueVT (ISD::AssertSext).
358  const SDValue *Parts, unsigned NumParts,
359  MVT PartVT, EVT ValueVT, const Value *V,
360  Optional<CallingConv::ID> CallConv) {
361  assert(ValueVT.isVector() && "Not a vector value");
362  assert(NumParts > 0 && "No parts to assemble!");
363  const bool IsABIRegCopy = CallConv.hasValue();
364 
365  const TargetLowering &TLI = DAG.getTargetLoweringInfo();
366  SDValue Val = Parts[0];
367 
368  // Handle a multi-element vector.
369  if (NumParts > 1) {
370  EVT IntermediateVT;
371  MVT RegisterVT;
372  unsigned NumIntermediates;
373  unsigned NumRegs;
374 
375  if (IsABIRegCopy) {
377  *DAG.getContext(), CallConv.getValue(), ValueVT, IntermediateVT,
378  NumIntermediates, RegisterVT);
379  } else {
380  NumRegs =
381  TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, IntermediateVT,
382  NumIntermediates, RegisterVT);
383  }
384 
385  assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
386  NumParts = NumRegs; // Silence a compiler warning.
387  assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
388  assert(RegisterVT.getSizeInBits() ==
389  Parts[0].getSimpleValueType().getSizeInBits() &&
390  "Part type sizes don't match!");
391 
392  // Assemble the parts into intermediate operands.
393  SmallVector<SDValue, 8> Ops(NumIntermediates);
394  if (NumIntermediates == NumParts) {
395  // If the register was not expanded, truncate or copy the value,
396  // as appropriate.
397  for (unsigned i = 0; i != NumParts; ++i)
398  Ops[i] = getCopyFromParts(DAG, DL, &Parts[i], 1,
399  PartVT, IntermediateVT, V);
400  } else if (NumParts > 0) {
401  // If the intermediate type was expanded, build the intermediate
402  // operands from the parts.
403  assert(NumParts % NumIntermediates == 0 &&
404  "Must expand into a divisible number of parts!");
405  unsigned Factor = NumParts / NumIntermediates;
406  for (unsigned i = 0; i != NumIntermediates; ++i)
407  Ops[i] = getCopyFromParts(DAG, DL, &Parts[i * Factor], Factor,
408  PartVT, IntermediateVT, V);
409  }
410 
411  // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the
412  // intermediate operands.
413  EVT BuiltVectorTy =
414  EVT::getVectorVT(*DAG.getContext(), IntermediateVT.getScalarType(),
415  (IntermediateVT.isVector()
416  ? IntermediateVT.getVectorNumElements() * NumParts
417  : NumIntermediates));
418  Val = DAG.getNode(IntermediateVT.isVector() ? ISD::CONCAT_VECTORS
420  DL, BuiltVectorTy, Ops);
421  }
422 
423  // There is now one part, held in Val. Correct it to match ValueVT.
424  EVT PartEVT = Val.getValueType();
425 
426  if (PartEVT == ValueVT)
427  return Val;
428 
429  if (PartEVT.isVector()) {
430  // If the element type of the source/dest vectors are the same, but the
431  // parts vector has more elements than the value vector, then we have a
432  // vector widening case (e.g. <2 x float> -> <4 x float>). Extract the
433  // elements we want.
434  if (PartEVT.getVectorElementType() == ValueVT.getVectorElementType()) {
435  assert(PartEVT.getVectorNumElements() > ValueVT.getVectorNumElements() &&
436  "Cannot narrow, it would be a lossy transformation");
437  return DAG.getNode(
438  ISD::EXTRACT_SUBVECTOR, DL, ValueVT, Val,
439  DAG.getConstant(0, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
440  }
441 
442  // Vector/Vector bitcast.
443  if (ValueVT.getSizeInBits() == PartEVT.getSizeInBits())
444  return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
445 
446  assert(PartEVT.getVectorNumElements() == ValueVT.getVectorNumElements() &&
447  "Cannot handle this kind of promotion");
448  // Promoted vector extract
449  return DAG.getAnyExtOrTrunc(Val, DL, ValueVT);
450 
451  }
452 
453  // Trivial bitcast if the types are the same size and the destination
454  // vector type is legal.
455  if (PartEVT.getSizeInBits() == ValueVT.getSizeInBits() &&
456  TLI.isTypeLegal(ValueVT))
457  return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
458 
459  if (ValueVT.getVectorNumElements() != 1) {
460  // Certain ABIs require that vectors are passed as integers. For vectors
461  // are the same size, this is an obvious bitcast.
462  if (ValueVT.getSizeInBits() == PartEVT.getSizeInBits()) {
463  return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
464  } else if (ValueVT.getSizeInBits() < PartEVT.getSizeInBits()) {
465  // Bitcast Val back the original type and extract the corresponding
466  // vector we want.
467  unsigned Elts = PartEVT.getSizeInBits() / ValueVT.getScalarSizeInBits();
468  EVT WiderVecType = EVT::getVectorVT(*DAG.getContext(),
469  ValueVT.getVectorElementType(), Elts);
470  Val = DAG.getBitcast(WiderVecType, Val);
471  return DAG.getNode(
472  ISD::EXTRACT_SUBVECTOR, DL, ValueVT, Val,
473  DAG.getConstant(0, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
474  }
475 
477  *DAG.getContext(), V, "non-trivial scalar-to-vector conversion");
478  return DAG.getUNDEF(ValueVT);
479  }
480 
481  // Handle cases such as i8 -> <1 x i1>
482  EVT ValueSVT = ValueVT.getVectorElementType();
483  if (ValueVT.getVectorNumElements() == 1 && ValueSVT != PartEVT)
484  Val = ValueVT.isFloatingPoint() ? DAG.getFPExtendOrRound(Val, DL, ValueSVT)
485  : DAG.getAnyExtOrTrunc(Val, DL, ValueSVT);
486 
487  return DAG.getBuildVector(ValueVT, DL, Val);
488 }
489 
490 static void getCopyToPartsVector(SelectionDAG &DAG, const SDLoc &dl,
491  SDValue Val, SDValue *Parts, unsigned NumParts,
492  MVT PartVT, const Value *V,
493  Optional<CallingConv::ID> CallConv);
494 
495 /// getCopyToParts - Create a series of nodes that contain the specified value
496 /// split into legal parts. If the parts contain more bits than Val, then, for
497 /// integers, ExtendKind can be used to specify how to generate the extra bits.
498 static void getCopyToParts(SelectionDAG &DAG, const SDLoc &DL, SDValue Val,
499  SDValue *Parts, unsigned NumParts, MVT PartVT,
500  const Value *V,
501  Optional<CallingConv::ID> CallConv = None,
502  ISD::NodeType ExtendKind = ISD::ANY_EXTEND) {
503  EVT ValueVT = Val.getValueType();
504 
505  // Handle the vector case separately.
506  if (ValueVT.isVector())
507  return getCopyToPartsVector(DAG, DL, Val, Parts, NumParts, PartVT, V,
508  CallConv);
509 
510  unsigned PartBits = PartVT.getSizeInBits();
511  unsigned OrigNumParts = NumParts;
512  assert(DAG.getTargetLoweringInfo().isTypeLegal(PartVT) &&
513  "Copying to an illegal type!");
514 
515  if (NumParts == 0)
516  return;
517 
518  assert(!ValueVT.isVector() && "Vector case handled elsewhere");
519  EVT PartEVT = PartVT;
520  if (PartEVT == ValueVT) {
521  assert(NumParts == 1 && "No-op copy with multiple parts!");
522  Parts[0] = Val;
523  return;
524  }
525 
526  if (NumParts * PartBits > ValueVT.getSizeInBits()) {
527  // If the parts cover more bits than the value has, promote the value.
528  if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
529  assert(NumParts == 1 && "Do not know what to promote to!");
530  Val = DAG.getNode(ISD::FP_EXTEND, DL, PartVT, Val);
531  } else {
532  if (ValueVT.isFloatingPoint()) {
533  // FP values need to be bitcast, then extended if they are being put
534  // into a larger container.
535  ValueVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits());
536  Val = DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
537  }
538  assert((PartVT.isInteger() || PartVT == MVT::x86mmx) &&
539  ValueVT.isInteger() &&
540  "Unknown mismatch!");
541  ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
542  Val = DAG.getNode(ExtendKind, DL, ValueVT, Val);
543  if (PartVT == MVT::x86mmx)
544  Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
545  }
546  } else if (PartBits == ValueVT.getSizeInBits()) {
547  // Different types of the same size.
548  assert(NumParts == 1 && PartEVT != ValueVT);
549  Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
550  } else if (NumParts * PartBits < ValueVT.getSizeInBits()) {
551  // If the parts cover less bits than value has, truncate the value.
552  assert((PartVT.isInteger() || PartVT == MVT::x86mmx) &&
553  ValueVT.isInteger() &&
554  "Unknown mismatch!");
555  ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
556  Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
557  if (PartVT == MVT::x86mmx)
558  Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
559  }
560 
561  // The value may have changed - recompute ValueVT.
562  ValueVT = Val.getValueType();
563  assert(NumParts * PartBits == ValueVT.getSizeInBits() &&
564  "Failed to tile the value with PartVT!");
565 
566  if (NumParts == 1) {
567  if (PartEVT != ValueVT) {
569  "scalar-to-vector conversion failed");
570  Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
571  }
572 
573  Parts[0] = Val;
574  return;
575  }
576 
577  // Expand the value into multiple parts.
578  if (NumParts & (NumParts - 1)) {
579  // The number of parts is not a power of 2. Split off and copy the tail.
580  assert(PartVT.isInteger() && ValueVT.isInteger() &&
581  "Do not know what to expand to!");
582  unsigned RoundParts = 1 << Log2_32(NumParts);
583  unsigned RoundBits = RoundParts * PartBits;
584  unsigned OddParts = NumParts - RoundParts;
585  SDValue OddVal = DAG.getNode(ISD::SRL, DL, ValueVT, Val,
586  DAG.getShiftAmountConstant(RoundBits, ValueVT, DL, /*LegalTypes*/false));
587 
588  getCopyToParts(DAG, DL, OddVal, Parts + RoundParts, OddParts, PartVT, V,
589  CallConv);
590 
591  if (DAG.getDataLayout().isBigEndian())
592  // The odd parts were reversed by getCopyToParts - unreverse them.
593  std::reverse(Parts + RoundParts, Parts + NumParts);
594 
595  NumParts = RoundParts;
596  ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
597  Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
598  }
599 
600  // The number of parts is a power of 2. Repeatedly bisect the value using
601  // EXTRACT_ELEMENT.
602  Parts[0] = DAG.getNode(ISD::BITCAST, DL,
604  ValueVT.getSizeInBits()),
605  Val);
606 
607  for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) {
608  for (unsigned i = 0; i < NumParts; i += StepSize) {
609  unsigned ThisBits = StepSize * PartBits / 2;
610  EVT ThisVT = EVT::getIntegerVT(*DAG.getContext(), ThisBits);
611  SDValue &Part0 = Parts[i];
612  SDValue &Part1 = Parts[i+StepSize/2];
613 
614  Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
615  ThisVT, Part0, DAG.getIntPtrConstant(1, DL));
616  Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
617  ThisVT, Part0, DAG.getIntPtrConstant(0, DL));
618 
619  if (ThisBits == PartBits && ThisVT != PartVT) {
620  Part0 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part0);
621  Part1 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part1);
622  }
623  }
624  }
625 
626  if (DAG.getDataLayout().isBigEndian())
627  std::reverse(Parts, Parts + OrigNumParts);
628 }
629 
631  SDValue Val, const SDLoc &DL, EVT PartVT) {
632  if (!PartVT.isVector())
633  return SDValue();
634 
635  EVT ValueVT = Val.getValueType();
636  unsigned PartNumElts = PartVT.getVectorNumElements();
637  unsigned ValueNumElts = ValueVT.getVectorNumElements();
638  if (PartNumElts > ValueNumElts &&
639  PartVT.getVectorElementType() == ValueVT.getVectorElementType()) {
640  EVT ElementVT = PartVT.getVectorElementType();
641  // Vector widening case, e.g. <2 x float> -> <4 x float>. Shuffle in
642  // undef elements.
644  DAG.ExtractVectorElements(Val, Ops);
645  SDValue EltUndef = DAG.getUNDEF(ElementVT);
646  for (unsigned i = ValueNumElts, e = PartNumElts; i != e; ++i)
647  Ops.push_back(EltUndef);
648 
649  // FIXME: Use CONCAT for 2x -> 4x.
650  return DAG.getBuildVector(PartVT, DL, Ops);
651  }
652 
653  return SDValue();
654 }
655 
656 /// getCopyToPartsVector - Create a series of nodes that contain the specified
657 /// value split into legal parts.
658 static void getCopyToPartsVector(SelectionDAG &DAG, const SDLoc &DL,
659  SDValue Val, SDValue *Parts, unsigned NumParts,
660  MVT PartVT, const Value *V,
661  Optional<CallingConv::ID> CallConv) {
662  EVT ValueVT = Val.getValueType();
663  assert(ValueVT.isVector() && "Not a vector");
664  const TargetLowering &TLI = DAG.getTargetLoweringInfo();
665  const bool IsABIRegCopy = CallConv.hasValue();
666 
667  if (NumParts == 1) {
668  EVT PartEVT = PartVT;
669  if (PartEVT == ValueVT) {
670  // Nothing to do.
671  } else if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) {
672  // Bitconvert vector->vector case.
673  Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
674  } else if (SDValue Widened = widenVectorToPartType(DAG, Val, DL, PartVT)) {
675  Val = Widened;
676  } else if (PartVT.isVector() &&
677  PartEVT.getVectorElementType().bitsGE(
678  ValueVT.getVectorElementType()) &&
679  PartEVT.getVectorNumElements() == ValueVT.getVectorNumElements()) {
680 
681  // Promoted vector extract
682  Val = DAG.getAnyExtOrTrunc(Val, DL, PartVT);
683  } else {
684  if (ValueVT.getVectorNumElements() == 1) {
685  Val = DAG.getNode(
686  ISD::EXTRACT_VECTOR_ELT, DL, PartVT, Val,
687  DAG.getConstant(0, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
688  } else {
689  assert(PartVT.getSizeInBits() > ValueVT.getSizeInBits() &&
690  "lossy conversion of vector to scalar type");
691  EVT IntermediateType =
692  EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits());
693  Val = DAG.getBitcast(IntermediateType, Val);
694  Val = DAG.getAnyExtOrTrunc(Val, DL, PartVT);
695  }
696  }
697 
698  assert(Val.getValueType() == PartVT && "Unexpected vector part value type");
699  Parts[0] = Val;
700  return;
701  }
702 
703  // Handle a multi-element vector.
704  EVT IntermediateVT;
705  MVT RegisterVT;
706  unsigned NumIntermediates;
707  unsigned NumRegs;
708  if (IsABIRegCopy) {
709  NumRegs = TLI.getVectorTypeBreakdownForCallingConv(
710  *DAG.getContext(), CallConv.getValue(), ValueVT, IntermediateVT,
711  NumIntermediates, RegisterVT);
712  } else {
713  NumRegs =
714  TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, IntermediateVT,
715  NumIntermediates, RegisterVT);
716  }
717 
718  assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
719  NumParts = NumRegs; // Silence a compiler warning.
720  assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
721 
722  unsigned IntermediateNumElts = IntermediateVT.isVector() ?
723  IntermediateVT.getVectorNumElements() : 1;
724 
725  // Convert the vector to the appropiate type if necessary.
726  unsigned DestVectorNoElts = NumIntermediates * IntermediateNumElts;
727 
728  EVT BuiltVectorTy = EVT::getVectorVT(
729  *DAG.getContext(), IntermediateVT.getScalarType(), DestVectorNoElts);
730  MVT IdxVT = TLI.getVectorIdxTy(DAG.getDataLayout());
731  if (ValueVT != BuiltVectorTy) {
732  if (SDValue Widened = widenVectorToPartType(DAG, Val, DL, BuiltVectorTy))
733  Val = Widened;
734 
735  Val = DAG.getNode(ISD::BITCAST, DL, BuiltVectorTy, Val);
736  }
737 
738  // Split the vector into intermediate operands.
739  SmallVector<SDValue, 8> Ops(NumIntermediates);
740  for (unsigned i = 0; i != NumIntermediates; ++i) {
741  if (IntermediateVT.isVector()) {
742  Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, IntermediateVT, Val,
743  DAG.getConstant(i * IntermediateNumElts, DL, IdxVT));
744  } else {
745  Ops[i] = DAG.getNode(
746  ISD::EXTRACT_VECTOR_ELT, DL, IntermediateVT, Val,
747  DAG.getConstant(i, DL, IdxVT));
748  }
749  }
750 
751  // Split the intermediate operands into legal parts.
752  if (NumParts == NumIntermediates) {
753  // If the register was not expanded, promote or copy the value,
754  // as appropriate.
755  for (unsigned i = 0; i != NumParts; ++i)
756  getCopyToParts(DAG, DL, Ops[i], &Parts[i], 1, PartVT, V, CallConv);
757  } else if (NumParts > 0) {
758  // If the intermediate type was expanded, split each the value into
759  // legal parts.
760  assert(NumIntermediates != 0 && "division by zero");
761  assert(NumParts % NumIntermediates == 0 &&
762  "Must expand into a divisible number of parts!");
763  unsigned Factor = NumParts / NumIntermediates;
764  for (unsigned i = 0; i != NumIntermediates; ++i)
765  getCopyToParts(DAG, DL, Ops[i], &Parts[i * Factor], Factor, PartVT, V,
766  CallConv);
767  }
768 }
769 
771  EVT valuevt, Optional<CallingConv::ID> CC)
772  : ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs),
773  RegCount(1, regs.size()), CallConv(CC) {}
774 
776  const DataLayout &DL, unsigned Reg, Type *Ty,
778  ComputeValueVTs(TLI, DL, Ty, ValueVTs);
779 
780  CallConv = CC;
781 
782  for (EVT ValueVT : ValueVTs) {
783  unsigned NumRegs =
784  isABIMangled()
785  ? TLI.getNumRegistersForCallingConv(Context, CC.getValue(), ValueVT)
786  : TLI.getNumRegisters(Context, ValueVT);
787  MVT RegisterVT =
788  isABIMangled()
789  ? TLI.getRegisterTypeForCallingConv(Context, CC.getValue(), ValueVT)
790  : TLI.getRegisterType(Context, ValueVT);
791  for (unsigned i = 0; i != NumRegs; ++i)
792  Regs.push_back(Reg + i);
793  RegVTs.push_back(RegisterVT);
794  RegCount.push_back(NumRegs);
795  Reg += NumRegs;
796  }
797 }
798 
800  FunctionLoweringInfo &FuncInfo,
801  const SDLoc &dl, SDValue &Chain,
802  SDValue *Flag, const Value *V) const {
803  // A Value with type {} or [0 x %t] needs no registers.
804  if (ValueVTs.empty())
805  return SDValue();
806 
807  const TargetLowering &TLI = DAG.getTargetLoweringInfo();
808 
809  // Assemble the legal parts into the final values.
810  SmallVector<SDValue, 4> Values(ValueVTs.size());
812  for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
813  // Copy the legal parts from the registers.
814  EVT ValueVT = ValueVTs[Value];
815  unsigned NumRegs = RegCount[Value];
816  MVT RegisterVT = isABIMangled() ? TLI.getRegisterTypeForCallingConv(
817  *DAG.getContext(),
818  CallConv.getValue(), RegVTs[Value])
819  : RegVTs[Value];
820 
821  Parts.resize(NumRegs);
822  for (unsigned i = 0; i != NumRegs; ++i) {
823  SDValue P;
824  if (!Flag) {
825  P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT);
826  } else {
827  P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT, *Flag);
828  *Flag = P.getValue(2);
829  }
830 
831  Chain = P.getValue(1);
832  Parts[i] = P;
833 
834  // If the source register was virtual and if we know something about it,
835  // add an assert node.
837  !RegisterVT.isInteger())
838  continue;
839 
841  FuncInfo.GetLiveOutRegInfo(Regs[Part+i]);
842  if (!LOI)
843  continue;
844 
845  unsigned RegSize = RegisterVT.getScalarSizeInBits();
846  unsigned NumSignBits = LOI->NumSignBits;
847  unsigned NumZeroBits = LOI->Known.countMinLeadingZeros();
848 
849  if (NumZeroBits == RegSize) {
850  // The current value is a zero.
851  // Explicitly express that as it would be easier for
852  // optimizations to kick in.
853  Parts[i] = DAG.getConstant(0, dl, RegisterVT);
854  continue;
855  }
856 
857  // FIXME: We capture more information than the dag can represent. For
858  // now, just use the tightest assertzext/assertsext possible.
859  bool isSExt;
860  EVT FromVT(MVT::Other);
861  if (NumZeroBits) {
862  FromVT = EVT::getIntegerVT(*DAG.getContext(), RegSize - NumZeroBits);
863  isSExt = false;
864  } else if (NumSignBits > 1) {
865  FromVT =
866  EVT::getIntegerVT(*DAG.getContext(), RegSize - NumSignBits + 1);
867  isSExt = true;
868  } else {
869  continue;
870  }
871  // Add an assertion node.
872  assert(FromVT != MVT::Other);
873  Parts[i] = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl,
874  RegisterVT, P, DAG.getValueType(FromVT));
875  }
876 
877  Values[Value] = getCopyFromParts(DAG, dl, Parts.begin(), NumRegs,
878  RegisterVT, ValueVT, V, CallConv);
879  Part += NumRegs;
880  Parts.clear();
881  }
882 
883  return DAG.getNode(ISD::MERGE_VALUES, dl, DAG.getVTList(ValueVTs), Values);
884 }
885 
887  const SDLoc &dl, SDValue &Chain, SDValue *Flag,
888  const Value *V,
889  ISD::NodeType PreferredExtendType) const {
890  const TargetLowering &TLI = DAG.getTargetLoweringInfo();
891  ISD::NodeType ExtendKind = PreferredExtendType;
892 
893  // Get the list of the values's legal parts.
894  unsigned NumRegs = Regs.size();
895  SmallVector<SDValue, 8> Parts(NumRegs);
896  for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
897  unsigned NumParts = RegCount[Value];
898 
899  MVT RegisterVT = isABIMangled() ? TLI.getRegisterTypeForCallingConv(
900  *DAG.getContext(),
901  CallConv.getValue(), RegVTs[Value])
902  : RegVTs[Value];
903 
904  if (ExtendKind == ISD::ANY_EXTEND && TLI.isZExtFree(Val, RegisterVT))
905  ExtendKind = ISD::ZERO_EXTEND;
906 
907  getCopyToParts(DAG, dl, Val.getValue(Val.getResNo() + Value), &Parts[Part],
908  NumParts, RegisterVT, V, CallConv, ExtendKind);
909  Part += NumParts;
910  }
911 
912  // Copy the parts into the registers.
913  SmallVector<SDValue, 8> Chains(NumRegs);
914  for (unsigned i = 0; i != NumRegs; ++i) {
915  SDValue Part;
916  if (!Flag) {
917  Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i]);
918  } else {
919  Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i], *Flag);
920  *Flag = Part.getValue(1);
921  }
922 
923  Chains[i] = Part.getValue(0);
924  }
925 
926  if (NumRegs == 1 || Flag)
927  // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is
928  // flagged to it. That is the CopyToReg nodes and the user are considered
929  // a single scheduling unit. If we create a TokenFactor and return it as
930  // chain, then the TokenFactor is both a predecessor (operand) of the
931  // user as well as a successor (the TF operands are flagged to the user).
932  // c1, f1 = CopyToReg
933  // c2, f2 = CopyToReg
934  // c3 = TokenFactor c1, c2
935  // ...
936  // = op c3, ..., f2
937  Chain = Chains[NumRegs-1];
938  else
939  Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
940 }
941 
942 void RegsForValue::AddInlineAsmOperands(unsigned Code, bool HasMatching,
943  unsigned MatchingIdx, const SDLoc &dl,
944  SelectionDAG &DAG,
945  std::vector<SDValue> &Ops) const {
946  const TargetLowering &TLI = DAG.getTargetLoweringInfo();
947 
948  unsigned Flag = InlineAsm::getFlagWord(Code, Regs.size());
949  if (HasMatching)
950  Flag = InlineAsm::getFlagWordForMatchingOp(Flag, MatchingIdx);
951  else if (!Regs.empty() &&
953  // Put the register class of the virtual registers in the flag word. That
954  // way, later passes can recompute register class constraints for inline
955  // assembly as well as normal instructions.
956  // Don't do this for tied operands that can use the regclass information
957  // from the def.
959  const TargetRegisterClass *RC = MRI.getRegClass(Regs.front());
960  Flag = InlineAsm::getFlagWordForRegClass(Flag, RC->getID());
961  }
962 
963  SDValue Res = DAG.getTargetConstant(Flag, dl, MVT::i32);
964  Ops.push_back(Res);
965 
966  if (Code == InlineAsm::Kind_Clobber) {
967  // Clobbers should always have a 1:1 mapping with registers, and may
968  // reference registers that have illegal (e.g. vector) types. Hence, we
969  // shouldn't try to apply any sort of splitting logic to them.
970  assert(Regs.size() == RegVTs.size() && Regs.size() == ValueVTs.size() &&
971  "No 1:1 mapping from clobbers to regs?");
972  unsigned SP = TLI.getStackPointerRegisterToSaveRestore();
973  (void)SP;
974  for (unsigned I = 0, E = ValueVTs.size(); I != E; ++I) {
975  Ops.push_back(DAG.getRegister(Regs[I], RegVTs[I]));
976  assert(
977  (Regs[I] != SP ||
979  "If we clobbered the stack pointer, MFI should know about it.");
980  }
981  return;
982  }
983 
984  for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) {
985  unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVTs[Value]);
986  MVT RegisterVT = RegVTs[Value];
987  for (unsigned i = 0; i != NumRegs; ++i) {
988  assert(Reg < Regs.size() && "Mismatch in # registers expected");
989  unsigned TheReg = Regs[Reg++];
990  Ops.push_back(DAG.getRegister(TheReg, RegisterVT));
991  }
992  }
993 }
994 
998  unsigned I = 0;
999  for (auto CountAndVT : zip_first(RegCount, RegVTs)) {
1000  unsigned RegCount = std::get<0>(CountAndVT);
1001  MVT RegisterVT = std::get<1>(CountAndVT);
1002  unsigned RegisterSize = RegisterVT.getSizeInBits();
1003  for (unsigned E = I + RegCount; I != E; ++I)
1004  OutVec.push_back(std::make_pair(Regs[I], RegisterSize));
1005  }
1006  return OutVec;
1007 }
1008 
1010  const TargetLibraryInfo *li) {
1011  AA = aa;
1012  GFI = gfi;
1013  LibInfo = li;
1014  DL = &DAG.getDataLayout();
1015  Context = DAG.getContext();
1016  LPadToCallSiteMap.clear();
1017  SL->init(DAG.getTargetLoweringInfo(), TM, DAG.getDataLayout());
1018 }
1019 
1021  NodeMap.clear();
1022  UnusedArgNodeMap.clear();
1023  PendingLoads.clear();
1024  PendingExports.clear();
1025  CurInst = nullptr;
1026  HasTailCall = false;
1027  SDNodeOrder = LowestSDNodeOrder;
1028  StatepointLowering.clear();
1029 }
1030 
1032  DanglingDebugInfoMap.clear();
1033 }
1034 
1036  if (PendingLoads.empty())
1037  return DAG.getRoot();
1038 
1039  if (PendingLoads.size() == 1) {
1040  SDValue Root = PendingLoads[0];
1041  DAG.setRoot(Root);
1042  PendingLoads.clear();
1043  return Root;
1044  }
1045 
1046  // Otherwise, we have to make a token factor node.
1047  SDValue Root = DAG.getTokenFactor(getCurSDLoc(), PendingLoads);
1048  PendingLoads.clear();
1049  DAG.setRoot(Root);
1050  return Root;
1051 }
1052 
1054  SDValue Root = DAG.getRoot();
1055 
1056  if (PendingExports.empty())
1057  return Root;
1058 
1059  // Turn all of the CopyToReg chains into one factored node.
1060  if (Root.getOpcode() != ISD::EntryToken) {
1061  unsigned i = 0, e = PendingExports.size();
1062  for (; i != e; ++i) {
1063  assert(PendingExports[i].getNode()->getNumOperands() > 1);
1064  if (PendingExports[i].getNode()->getOperand(0) == Root)
1065  break; // Don't add the root if we already indirectly depend on it.
1066  }
1067 
1068  if (i == e)
1069  PendingExports.push_back(Root);
1070  }
1071 
1072  Root = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
1073  PendingExports);
1074  PendingExports.clear();
1075  DAG.setRoot(Root);
1076  return Root;
1077 }
1078 
1080  // Set up outgoing PHI node register values before emitting the terminator.
1081  if (I.isTerminator()) {
1082  HandlePHINodesInSuccessorBlocks(I.getParent());
1083  }
1084 
1085  // Increase the SDNodeOrder if dealing with a non-debug instruction.
1086  if (!isa<DbgInfoIntrinsic>(I))
1087  ++SDNodeOrder;
1088 
1089  CurInst = &I;
1090 
1091  visit(I.getOpcode(), I);
1092 
1093  if (auto *FPMO = dyn_cast<FPMathOperator>(&I)) {
1094  // Propagate the fast-math-flags of this IR instruction to the DAG node that
1095  // maps to this instruction.
1096  // TODO: We could handle all flags (nsw, etc) here.
1097  // TODO: If an IR instruction maps to >1 node, only the final node will have
1098  // flags set.
1099  if (SDNode *Node = getNodeForIRValue(&I)) {
1100  SDNodeFlags IncomingFlags;
1101  IncomingFlags.copyFMF(*FPMO);
1102  if (!Node->getFlags().isDefined())
1103  Node->setFlags(IncomingFlags);
1104  else
1105  Node->intersectFlagsWith(IncomingFlags);
1106  }
1107  }
1108 
1109  if (!I.isTerminator() && !HasTailCall &&
1110  !isStatepoint(&I)) // statepoints handle their exports internally
1111  CopyToExportRegsIfNeeded(&I);
1112 
1113  CurInst = nullptr;
1114 }
1115 
1116 void SelectionDAGBuilder::visitPHI(const PHINode &) {
1117  llvm_unreachable("SelectionDAGBuilder shouldn't visit PHI nodes!");
1118 }
1119 
1120 void SelectionDAGBuilder::visit(unsigned Opcode, const User &I) {
1121  // Note: this doesn't use InstVisitor, because it has to work with
1122  // ConstantExpr's in addition to instructions.
1123  switch (Opcode) {
1124  default: llvm_unreachable("Unknown instruction type encountered!");
1125  // Build the switch statement using the Instruction.def file.
1126 #define HANDLE_INST(NUM, OPCODE, CLASS) \
1127  case Instruction::OPCODE: visit##OPCODE((const CLASS&)I); break;
1128 #include "llvm/IR/Instruction.def"
1129  }
1130 }
1131 
1133  const DIExpression *Expr) {
1134  auto isMatchingDbgValue = [&](DanglingDebugInfo &DDI) {
1135  const DbgValueInst *DI = DDI.getDI();
1136  DIVariable *DanglingVariable = DI->getVariable();
1137  DIExpression *DanglingExpr = DI->getExpression();
1138  if (DanglingVariable == Variable && Expr->fragmentsOverlap(DanglingExpr)) {
1139  LLVM_DEBUG(dbgs() << "Dropping dangling debug info for " << *DI << "\n");
1140  return true;
1141  }
1142  return false;
1143  };
1144 
1145  for (auto &DDIMI : DanglingDebugInfoMap) {
1146  DanglingDebugInfoVector &DDIV = DDIMI.second;
1147 
1148  // If debug info is to be dropped, run it through final checks to see
1149  // whether it can be salvaged.
1150  for (auto &DDI : DDIV)
1151  if (isMatchingDbgValue(DDI))
1152  salvageUnresolvedDbgValue(DDI);
1153 
1154  DDIV.erase(remove_if(DDIV, isMatchingDbgValue), DDIV.end());
1155  }
1156 }
1157 
1158 // resolveDanglingDebugInfo - if we saw an earlier dbg_value referring to V,
1159 // generate the debug data structures now that we've seen its definition.
1161  SDValue Val) {
1162  auto DanglingDbgInfoIt = DanglingDebugInfoMap.find(V);
1163  if (DanglingDbgInfoIt == DanglingDebugInfoMap.end())
1164  return;
1165 
1166  DanglingDebugInfoVector &DDIV = DanglingDbgInfoIt->second;
1167  for (auto &DDI : DDIV) {
1168  const DbgValueInst *DI = DDI.getDI();
1169  assert(DI && "Ill-formed DanglingDebugInfo");
1170  DebugLoc dl = DDI.getdl();
1171  unsigned ValSDNodeOrder = Val.getNode()->getIROrder();
1172  unsigned DbgSDNodeOrder = DDI.getSDNodeOrder();
1173  DILocalVariable *Variable = DI->getVariable();
1174  DIExpression *Expr = DI->getExpression();
1175  assert(Variable->isValidLocationForIntrinsic(dl) &&
1176  "Expected inlined-at fields to agree");
1177  SDDbgValue *SDV;
1178  if (Val.getNode()) {
1179  // FIXME: I doubt that it is correct to resolve a dangling DbgValue as a
1180  // FuncArgumentDbgValue (it would be hoisted to the function entry, and if
1181  // we couldn't resolve it directly when examining the DbgValue intrinsic
1182  // in the first place we should not be more successful here). Unless we
1183  // have some test case that prove this to be correct we should avoid
1184  // calling EmitFuncArgumentDbgValue here.
1185  if (!EmitFuncArgumentDbgValue(V, Variable, Expr, dl, false, Val)) {
1186  LLVM_DEBUG(dbgs() << "Resolve dangling debug info [order="
1187  << DbgSDNodeOrder << "] for:\n " << *DI << "\n");
1188  LLVM_DEBUG(dbgs() << " By mapping to:\n "; Val.dump());
1189  // Increase the SDNodeOrder for the DbgValue here to make sure it is
1190  // inserted after the definition of Val when emitting the instructions
1191  // after ISel. An alternative could be to teach
1192  // ScheduleDAGSDNodes::EmitSchedule to delay the insertion properly.
1193  LLVM_DEBUG(if (ValSDNodeOrder > DbgSDNodeOrder) dbgs()
1194  << "changing SDNodeOrder from " << DbgSDNodeOrder << " to "
1195  << ValSDNodeOrder << "\n");
1196  SDV = getDbgValue(Val, Variable, Expr, dl,
1197  std::max(DbgSDNodeOrder, ValSDNodeOrder));
1198  DAG.AddDbgValue(SDV, Val.getNode(), false);
1199  } else
1200  LLVM_DEBUG(dbgs() << "Resolved dangling debug info for " << *DI
1201  << "in EmitFuncArgumentDbgValue\n");
1202  } else {
1203  LLVM_DEBUG(dbgs() << "Dropping debug info for " << *DI << "\n");
1204  auto Undef =
1205  UndefValue::get(DDI.getDI()->getVariableLocation()->getType());
1206  auto SDV =
1207  DAG.getConstantDbgValue(Variable, Expr, Undef, dl, DbgSDNodeOrder);
1208  DAG.AddDbgValue(SDV, nullptr, false);
1209  }
1210  }
1211  DDIV.clear();
1212 }
1213 
1215  Value *V = DDI.getDI()->getValue();
1216  DILocalVariable *Var = DDI.getDI()->getVariable();
1217  DIExpression *Expr = DDI.getDI()->getExpression();
1218  DebugLoc DL = DDI.getdl();
1219  DebugLoc InstDL = DDI.getDI()->getDebugLoc();
1220  unsigned SDOrder = DDI.getSDNodeOrder();
1221 
1222  // Currently we consider only dbg.value intrinsics -- we tell the salvager
1223  // that DW_OP_stack_value is desired.
1224  assert(isa<DbgValueInst>(DDI.getDI()));
1225  bool StackValue = true;
1226 
1227  // Can this Value can be encoded without any further work?
1228  if (handleDebugValue(V, Var, Expr, DL, InstDL, SDOrder))
1229  return;
1230 
1231  // Attempt to salvage back through as many instructions as possible. Bail if
1232  // a non-instruction is seen, such as a constant expression or global
1233  // variable. FIXME: Further work could recover those too.
1234  while (isa<Instruction>(V)) {
1235  Instruction &VAsInst = *cast<Instruction>(V);
1236  DIExpression *NewExpr = salvageDebugInfoImpl(VAsInst, Expr, StackValue);
1237 
1238  // If we cannot salvage any further, and haven't yet found a suitable debug
1239  // expression, bail out.
1240  if (!NewExpr)
1241  break;
1242 
1243  // New value and expr now represent this debuginfo.
1244  V = VAsInst.getOperand(0);
1245  Expr = NewExpr;
1246 
1247  // Some kind of simplification occurred: check whether the operand of the
1248  // salvaged debug expression can be encoded in this DAG.
1249  if (handleDebugValue(V, Var, Expr, DL, InstDL, SDOrder)) {
1250  LLVM_DEBUG(dbgs() << "Salvaged debug location info for:\n "
1251  << DDI.getDI() << "\nBy stripping back to:\n " << V);
1252  return;
1253  }
1254  }
1255 
1256  // This was the final opportunity to salvage this debug information, and it
1257  // couldn't be done. Place an undef DBG_VALUE at this location to terminate
1258  // any earlier variable location.
1259  auto Undef = UndefValue::get(DDI.getDI()->getVariableLocation()->getType());
1260  auto SDV = DAG.getConstantDbgValue(Var, Expr, Undef, DL, SDNodeOrder);
1261  DAG.AddDbgValue(SDV, nullptr, false);
1262 
1263  LLVM_DEBUG(dbgs() << "Dropping debug value info for:\n " << DDI.getDI()
1264  << "\n");
1265  LLVM_DEBUG(dbgs() << " Last seen at:\n " << *DDI.getDI()->getOperand(0)
1266  << "\n");
1267 }
1268 
1270  DIExpression *Expr, DebugLoc dl,
1271  DebugLoc InstDL, unsigned Order) {
1272  const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1273  SDDbgValue *SDV;
1274  if (isa<ConstantInt>(V) || isa<ConstantFP>(V) || isa<UndefValue>(V) ||
1275  isa<ConstantPointerNull>(V)) {
1276  SDV = DAG.getConstantDbgValue(Var, Expr, V, dl, SDNodeOrder);
1277  DAG.AddDbgValue(SDV, nullptr, false);
1278  return true;
1279  }
1280 
1281  // If the Value is a frame index, we can create a FrameIndex debug value
1282  // without relying on the DAG at all.
1283  if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
1284  auto SI = FuncInfo.StaticAllocaMap.find(AI);
1285  if (SI != FuncInfo.StaticAllocaMap.end()) {
1286  auto SDV =
1287  DAG.getFrameIndexDbgValue(Var, Expr, SI->second,
1288  /*IsIndirect*/ false, dl, SDNodeOrder);
1289  // Do not attach the SDNodeDbgValue to an SDNode: this variable location
1290  // is still available even if the SDNode gets optimized out.
1291  DAG.AddDbgValue(SDV, nullptr, false);
1292  return true;
1293  }
1294  }
1295 
1296  // Do not use getValue() in here; we don't want to generate code at
1297  // this point if it hasn't been done yet.
1298  SDValue N = NodeMap[V];
1299  if (!N.getNode() && isa<Argument>(V)) // Check unused arguments map.
1300  N = UnusedArgNodeMap[V];
1301  if (N.getNode()) {
1302  if (EmitFuncArgumentDbgValue(V, Var, Expr, dl, false, N))
1303  return true;
1304  SDV = getDbgValue(N, Var, Expr, dl, SDNodeOrder);
1305  DAG.AddDbgValue(SDV, N.getNode(), false);
1306  return true;
1307  }
1308 
1309  // Special rules apply for the first dbg.values of parameter variables in a
1310  // function. Identify them by the fact they reference Argument Values, that
1311  // they're parameters, and they are parameters of the current function. We
1312  // need to let them dangle until they get an SDNode.
1313  bool IsParamOfFunc = isa<Argument>(V) && Var->isParameter() &&
1314  !InstDL.getInlinedAt();
1315  if (!IsParamOfFunc) {
1316  // The value is not used in this block yet (or it would have an SDNode).
1317  // We still want the value to appear for the user if possible -- if it has
1318  // an associated VReg, we can refer to that instead.
1319  auto VMI = FuncInfo.ValueMap.find(V);
1320  if (VMI != FuncInfo.ValueMap.end()) {
1321  unsigned Reg = VMI->second;
1322  // If this is a PHI node, it may be split up into several MI PHI nodes
1323  // (in FunctionLoweringInfo::set).
1324  RegsForValue RFV(V->getContext(), TLI, DAG.getDataLayout(), Reg,
1325  V->getType(), None);
1326  if (RFV.occupiesMultipleRegs()) {
1327  unsigned Offset = 0;
1328  unsigned BitsToDescribe = 0;
1329  if (auto VarSize = Var->getSizeInBits())
1330  BitsToDescribe = *VarSize;
1331  if (auto Fragment = Expr->getFragmentInfo())
1332  BitsToDescribe = Fragment->SizeInBits;
1333  for (auto RegAndSize : RFV.getRegsAndSizes()) {
1334  unsigned RegisterSize = RegAndSize.second;
1335  // Bail out if all bits are described already.
1336  if (Offset >= BitsToDescribe)
1337  break;
1338  unsigned FragmentSize = (Offset + RegisterSize > BitsToDescribe)
1339  ? BitsToDescribe - Offset
1340  : RegisterSize;
1341  auto FragmentExpr = DIExpression::createFragmentExpression(
1342  Expr, Offset, FragmentSize);
1343  if (!FragmentExpr)
1344  continue;
1345  SDV = DAG.getVRegDbgValue(Var, *FragmentExpr, RegAndSize.first,
1346  false, dl, SDNodeOrder);
1347  DAG.AddDbgValue(SDV, nullptr, false);
1348  Offset += RegisterSize;
1349  }
1350  } else {
1351  SDV = DAG.getVRegDbgValue(Var, Expr, Reg, false, dl, SDNodeOrder);
1352  DAG.AddDbgValue(SDV, nullptr, false);
1353  }
1354  return true;
1355  }
1356  }
1357 
1358  return false;
1359 }
1360 
1362  // Try to fixup any remaining dangling debug info -- and drop it if we can't.
1363  for (auto &Pair : DanglingDebugInfoMap)
1364  for (auto &DDI : Pair.second)
1365  salvageUnresolvedDbgValue(DDI);
1366  clearDanglingDebugInfo();
1367 }
1368 
1369 /// getCopyFromRegs - If there was virtual register allocated for the value V
1370 /// emit CopyFromReg of the specified type Ty. Return empty SDValue() otherwise.
1372  DenseMap<const Value *, unsigned>::iterator It = FuncInfo.ValueMap.find(V);
1373  SDValue Result;
1374 
1375  if (It != FuncInfo.ValueMap.end()) {
1376  unsigned InReg = It->second;
1377 
1378  RegsForValue RFV(*DAG.getContext(), DAG.getTargetLoweringInfo(),
1379  DAG.getDataLayout(), InReg, Ty,
1380  None); // This is not an ABI copy.
1381  SDValue Chain = DAG.getEntryNode();
1382  Result = RFV.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(), Chain, nullptr,
1383  V);
1384  resolveDanglingDebugInfo(V, Result);
1385  }
1386 
1387  return Result;
1388 }
1389 
1390 /// getValue - Return an SDValue for the given Value.
1392  // If we already have an SDValue for this value, use it. It's important
1393  // to do this first, so that we don't create a CopyFromReg if we already
1394  // have a regular SDValue.
1395  SDValue &N = NodeMap[V];
1396  if (N.getNode()) return N;
1397 
1398  // If there's a virtual register allocated and initialized for this
1399  // value, use it.
1400  if (SDValue copyFromReg = getCopyFromRegs(V, V->getType()))
1401  return copyFromReg;
1402 
1403  // Otherwise create a new SDValue and remember it.
1404  SDValue Val = getValueImpl(V);
1405  NodeMap[V] = Val;
1406  resolveDanglingDebugInfo(V, Val);
1407  return Val;
1408 }
1409 
1410 // Return true if SDValue exists for the given Value
1412  return (NodeMap.find(V) != NodeMap.end()) ||
1413  (FuncInfo.ValueMap.find(V) != FuncInfo.ValueMap.end());
1414 }
1415 
1416 /// getNonRegisterValue - Return an SDValue for the given Value, but
1417 /// don't look in FuncInfo.ValueMap for a virtual register.
1419  // If we already have an SDValue for this value, use it.
1420  SDValue &N = NodeMap[V];
1421  if (N.getNode()) {
1422  if (isa<ConstantSDNode>(N) || isa<ConstantFPSDNode>(N)) {
1423  // Remove the debug location from the node as the node is about to be used
1424  // in a location which may differ from the original debug location. This
1425  // is relevant to Constant and ConstantFP nodes because they can appear
1426  // as constant expressions inside PHI nodes.
1427  N->setDebugLoc(DebugLoc());
1428  }
1429  return N;
1430  }
1431 
1432  // Otherwise create a new SDValue and remember it.
1433  SDValue Val = getValueImpl(V);
1434  NodeMap[V] = Val;
1435  resolveDanglingDebugInfo(V, Val);
1436  return Val;
1437 }
1438 
1439 /// getValueImpl - Helper function for getValue and getNonRegisterValue.
1440 /// Create an SDValue for the given value.
1442  const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1443 
1444  if (const Constant *C = dyn_cast<Constant>(V)) {
1445  EVT VT = TLI.getValueType(DAG.getDataLayout(), V->getType(), true);
1446 
1447  if (const ConstantInt *CI = dyn_cast<ConstantInt>(C))
1448  return DAG.getConstant(*CI, getCurSDLoc(), VT);
1449 
1450  if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
1451  return DAG.getGlobalAddress(GV, getCurSDLoc(), VT);
1452 
1453  if (isa<ConstantPointerNull>(C)) {
1454  unsigned AS = V->getType()->getPointerAddressSpace();
1455  return DAG.getConstant(0, getCurSDLoc(),
1456  TLI.getPointerTy(DAG.getDataLayout(), AS));
1457  }
1458 
1459  if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
1460  return DAG.getConstantFP(*CFP, getCurSDLoc(), VT);
1461 
1462  if (isa<UndefValue>(C) && !V->getType()->isAggregateType())
1463  return DAG.getUNDEF(VT);
1464 
1465  if (const ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
1466  visit(CE->getOpcode(), *CE);
1467  SDValue N1 = NodeMap[V];
1468  assert(N1.getNode() && "visit didn't populate the NodeMap!");
1469  return N1;
1470  }
1471 
1472  if (isa<ConstantStruct>(C) || isa<ConstantArray>(C)) {
1474  for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end();
1475  OI != OE; ++OI) {
1476  SDNode *Val = getValue(*OI).getNode();
1477  // If the operand is an empty aggregate, there are no values.
1478  if (!Val) continue;
1479  // Add each leaf value from the operand to the Constants list
1480  // to form a flattened list of all the values.
1481  for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
1482  Constants.push_back(SDValue(Val, i));
1483  }
1484 
1485  return DAG.getMergeValues(Constants, getCurSDLoc());
1486  }
1487 
1488  if (const ConstantDataSequential *CDS =
1489  dyn_cast<ConstantDataSequential>(C)) {
1491  for (unsigned i = 0, e = CDS->getNumElements(); i != e; ++i) {
1492  SDNode *Val = getValue(CDS->getElementAsConstant(i)).getNode();
1493  // Add each leaf value from the operand to the Constants list
1494  // to form a flattened list of all the values.
1495  for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
1496  Ops.push_back(SDValue(Val, i));
1497  }
1498 
1499  if (isa<ArrayType>(CDS->getType()))
1500  return DAG.getMergeValues(Ops, getCurSDLoc());
1501  return NodeMap[V] = DAG.getBuildVector(VT, getCurSDLoc(), Ops);
1502  }
1503 
1504  if (C->getType()->isStructTy() || C->getType()->isArrayTy()) {
1505  assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&
1506  "Unknown struct or array constant!");
1507 
1509  ComputeValueVTs(TLI, DAG.getDataLayout(), C->getType(), ValueVTs);
1510  unsigned NumElts = ValueVTs.size();
1511  if (NumElts == 0)
1512  return SDValue(); // empty struct
1514  for (unsigned i = 0; i != NumElts; ++i) {
1515  EVT EltVT = ValueVTs[i];
1516  if (isa<UndefValue>(C))
1517  Constants[i] = DAG.getUNDEF(EltVT);
1518  else if (EltVT.isFloatingPoint())
1519  Constants[i] = DAG.getConstantFP(0, getCurSDLoc(), EltVT);
1520  else
1521  Constants[i] = DAG.getConstant(0, getCurSDLoc(), EltVT);
1522  }
1523 
1524  return DAG.getMergeValues(Constants, getCurSDLoc());
1525  }
1526 
1527  if (const BlockAddress *BA = dyn_cast<BlockAddress>(C))
1528  return DAG.getBlockAddress(BA, VT);
1529 
1530  VectorType *VecTy = cast<VectorType>(V->getType());
1531  unsigned NumElements = VecTy->getNumElements();
1532 
1533  // Now that we know the number and type of the elements, get that number of
1534  // elements into the Ops array based on what kind of constant it is.
1536  if (const ConstantVector *CV = dyn_cast<ConstantVector>(C)) {
1537  for (unsigned i = 0; i != NumElements; ++i)
1538  Ops.push_back(getValue(CV->getOperand(i)));
1539  } else {
1540  assert(isa<ConstantAggregateZero>(C) && "Unknown vector constant!");
1541  EVT EltVT =
1542  TLI.getValueType(DAG.getDataLayout(), VecTy->getElementType());
1543 
1544  SDValue Op;
1545  if (EltVT.isFloatingPoint())
1546  Op = DAG.getConstantFP(0, getCurSDLoc(), EltVT);
1547  else
1548  Op = DAG.getConstant(0, getCurSDLoc(), EltVT);
1549  Ops.assign(NumElements, Op);
1550  }
1551 
1552  // Create a BUILD_VECTOR node.
1553  return NodeMap[V] = DAG.getBuildVector(VT, getCurSDLoc(), Ops);
1554  }
1555 
1556  // If this is a static alloca, generate it as the frameindex instead of
1557  // computation.
1558  if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
1560  FuncInfo.StaticAllocaMap.find(AI);
1561  if (SI != FuncInfo.StaticAllocaMap.end())
1562  return DAG.getFrameIndex(SI->second,
1563  TLI.getFrameIndexTy(DAG.getDataLayout()));
1564  }
1565 
1566  // If this is an instruction which fast-isel has deferred, select it now.
1567  if (const Instruction *Inst = dyn_cast<Instruction>(V)) {
1568  unsigned InReg = FuncInfo.InitializeRegForValue(Inst);
1569 
1570  RegsForValue RFV(*DAG.getContext(), TLI, DAG.getDataLayout(), InReg,
1571  Inst->getType(), getABIRegCopyCC(V));
1572  SDValue Chain = DAG.getEntryNode();
1573  return RFV.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(), Chain, nullptr, V);
1574  }
1575 
1576  llvm_unreachable("Can't get register for value!");
1577 }
1578 
1579 void SelectionDAGBuilder::visitCatchPad(const CatchPadInst &I) {
1580  auto Pers = classifyEHPersonality(FuncInfo.Fn->getPersonalityFn());
1581  bool IsMSVCCXX = Pers == EHPersonality::MSVC_CXX;
1582  bool IsCoreCLR = Pers == EHPersonality::CoreCLR;
1583  bool IsSEH = isAsynchronousEHPersonality(Pers);
1584  bool IsWasmCXX = Pers == EHPersonality::Wasm_CXX;
1585  MachineBasicBlock *CatchPadMBB = FuncInfo.MBB;
1586  if (!IsSEH)
1587  CatchPadMBB->setIsEHScopeEntry();
1588  // In MSVC C++ and CoreCLR, catchblocks are funclets and need prologues.
1589  if (IsMSVCCXX || IsCoreCLR)
1590  CatchPadMBB->setIsEHFuncletEntry();
1591  // Wasm does not need catchpads anymore
1592  if (!IsWasmCXX)
1593  DAG.setRoot(DAG.getNode(ISD::CATCHPAD, getCurSDLoc(), MVT::Other,
1594  getControlRoot()));
1595 }
1596 
1597 void SelectionDAGBuilder::visitCatchRet(const CatchReturnInst &I) {
1598  // Update machine-CFG edge.
1599  MachineBasicBlock *TargetMBB = FuncInfo.MBBMap[I.getSuccessor()];
1600  FuncInfo.MBB->addSuccessor(TargetMBB);
1601 
1602  auto Pers = classifyEHPersonality(FuncInfo.Fn->getPersonalityFn());
1603  bool IsSEH = isAsynchronousEHPersonality(Pers);
1604  if (IsSEH) {
1605  // If this is not a fall-through branch or optimizations are switched off,
1606  // emit the branch.
1607  if (TargetMBB != NextBlock(FuncInfo.MBB) ||
1608  TM.getOptLevel() == CodeGenOpt::None)
1609  DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other,
1610  getControlRoot(), DAG.getBasicBlock(TargetMBB)));
1611  return;
1612  }
1613 
1614  // Figure out the funclet membership for the catchret's successor.
1615  // This will be used by the FuncletLayout pass to determine how to order the
1616  // BB's.
1617  // A 'catchret' returns to the outer scope's color.
1618  Value *ParentPad = I.getCatchSwitchParentPad();
1619  const BasicBlock *SuccessorColor;
1620  if (isa<ConstantTokenNone>(ParentPad))
1621  SuccessorColor = &FuncInfo.Fn->getEntryBlock();
1622  else
1623  SuccessorColor = cast<Instruction>(ParentPad)->getParent();
1624  assert(SuccessorColor && "No parent funclet for catchret!");
1625  MachineBasicBlock *SuccessorColorMBB = FuncInfo.MBBMap[SuccessorColor];
1626  assert(SuccessorColorMBB && "No MBB for SuccessorColor!");
1627 
1628  // Create the terminator node.
1629  SDValue Ret = DAG.getNode(ISD::CATCHRET, getCurSDLoc(), MVT::Other,
1630  getControlRoot(), DAG.getBasicBlock(TargetMBB),
1631  DAG.getBasicBlock(SuccessorColorMBB));
1632  DAG.setRoot(Ret);
1633 }
1634 
1635 void SelectionDAGBuilder::visitCleanupPad(const CleanupPadInst &CPI) {
1636  // Don't emit any special code for the cleanuppad instruction. It just marks
1637  // the start of an EH scope/funclet.
1638  FuncInfo.MBB->setIsEHScopeEntry();
1639  auto Pers = classifyEHPersonality(FuncInfo.Fn->getPersonalityFn());
1640  if (Pers != EHPersonality::Wasm_CXX) {
1641  FuncInfo.MBB->setIsEHFuncletEntry();
1642  FuncInfo.MBB->setIsCleanupFuncletEntry();
1643  }
1644 }
1645 
1646 // For wasm, there's alwyas a single catch pad attached to a catchswitch, and
1647 // the control flow always stops at the single catch pad, as it does for a
1648 // cleanup pad. In case the exception caught is not of the types the catch pad
1649 // catches, it will be rethrown by a rethrow.
1651  FunctionLoweringInfo &FuncInfo, const BasicBlock *EHPadBB,
1652  BranchProbability Prob,
1653  SmallVectorImpl<std::pair<MachineBasicBlock *, BranchProbability>>
1654  &UnwindDests) {
1655  while (EHPadBB) {
1656  const Instruction *Pad = EHPadBB->getFirstNonPHI();
1657  if (isa<CleanupPadInst>(Pad)) {
1658  // Stop on cleanup pads.
1659  UnwindDests.emplace_back(FuncInfo.MBBMap[EHPadBB], Prob);
1660  UnwindDests.back().first->setIsEHScopeEntry();
1661  break;
1662  } else if (auto *CatchSwitch = dyn_cast<CatchSwitchInst>(Pad)) {
1663  // Add the catchpad handlers to the possible destinations. We don't
1664  // continue to the unwind destination of the catchswitch for wasm.
1665  for (const BasicBlock *CatchPadBB : CatchSwitch->handlers()) {
1666  UnwindDests.emplace_back(FuncInfo.MBBMap[CatchPadBB], Prob);
1667  UnwindDests.back().first->setIsEHScopeEntry();
1668  }
1669  break;
1670  } else {
1671  continue;
1672  }
1673  }
1674 }
1675 
1676 /// When an invoke or a cleanupret unwinds to the next EH pad, there are
1677 /// many places it could ultimately go. In the IR, we have a single unwind
1678 /// destination, but in the machine CFG, we enumerate all the possible blocks.
1679 /// This function skips over imaginary basic blocks that hold catchswitch
1680 /// instructions, and finds all the "real" machine
1681 /// basic block destinations. As those destinations may not be successors of
1682 /// EHPadBB, here we also calculate the edge probability to those destinations.
1683 /// The passed-in Prob is the edge probability to EHPadBB.
1685  FunctionLoweringInfo &FuncInfo, const BasicBlock *EHPadBB,
1686  BranchProbability Prob,
1687  SmallVectorImpl<std::pair<MachineBasicBlock *, BranchProbability>>
1688  &UnwindDests) {
1689  EHPersonality Personality =
1691  bool IsMSVCCXX = Personality == EHPersonality::MSVC_CXX;
1692  bool IsCoreCLR = Personality == EHPersonality::CoreCLR;
1693  bool IsWasmCXX = Personality == EHPersonality::Wasm_CXX;
1694  bool IsSEH = isAsynchronousEHPersonality(Personality);
1695 
1696  if (IsWasmCXX) {
1697  findWasmUnwindDestinations(FuncInfo, EHPadBB, Prob, UnwindDests);
1698  assert(UnwindDests.size() <= 1 &&
1699  "There should be at most one unwind destination for wasm");
1700  return;
1701  }
1702 
1703  while (EHPadBB) {
1704  const Instruction *Pad = EHPadBB->getFirstNonPHI();
1705  BasicBlock *NewEHPadBB = nullptr;
1706  if (isa<LandingPadInst>(Pad)) {
1707  // Stop on landingpads. They are not funclets.
1708  UnwindDests.emplace_back(FuncInfo.MBBMap[EHPadBB], Prob);
1709  break;
1710  } else if (isa<CleanupPadInst>(Pad)) {
1711  // Stop on cleanup pads. Cleanups are always funclet entries for all known
1712  // personalities.
1713  UnwindDests.emplace_back(FuncInfo.MBBMap[EHPadBB], Prob);
1714  UnwindDests.back().first->setIsEHScopeEntry();
1715  UnwindDests.back().first->setIsEHFuncletEntry();
1716  break;
1717  } else if (auto *CatchSwitch = dyn_cast<CatchSwitchInst>(Pad)) {
1718  // Add the catchpad handlers to the possible destinations.
1719  for (const BasicBlock *CatchPadBB : CatchSwitch->handlers()) {
1720  UnwindDests.emplace_back(FuncInfo.MBBMap[CatchPadBB], Prob);
1721  // For MSVC++ and the CLR, catchblocks are funclets and need prologues.
1722  if (IsMSVCCXX || IsCoreCLR)
1723  UnwindDests.back().first->setIsEHFuncletEntry();
1724  if (!IsSEH)
1725  UnwindDests.back().first->setIsEHScopeEntry();
1726  }
1727  NewEHPadBB = CatchSwitch->getUnwindDest();
1728  } else {
1729  continue;
1730  }
1731 
1732  BranchProbabilityInfo *BPI = FuncInfo.BPI;
1733  if (BPI && NewEHPadBB)
1734  Prob *= BPI->getEdgeProbability(EHPadBB, NewEHPadBB);
1735  EHPadBB = NewEHPadBB;
1736  }
1737 }
1738 
1739 void SelectionDAGBuilder::visitCleanupRet(const CleanupReturnInst &I) {
1740  // Update successor info.
1742  auto UnwindDest = I.getUnwindDest();
1743  BranchProbabilityInfo *BPI = FuncInfo.BPI;
1744  BranchProbability UnwindDestProb =
1745  (BPI && UnwindDest)
1746  ? BPI->getEdgeProbability(FuncInfo.MBB->getBasicBlock(), UnwindDest)
1748  findUnwindDestinations(FuncInfo, UnwindDest, UnwindDestProb, UnwindDests);
1749  for (auto &UnwindDest : UnwindDests) {
1750  UnwindDest.first->setIsEHPad();
1751  addSuccessorWithProb(FuncInfo.MBB, UnwindDest.first, UnwindDest.second);
1752  }
1753  FuncInfo.MBB->normalizeSuccProbs();
1754 
1755  // Create the terminator node.
1756  SDValue Ret =
1757  DAG.getNode(ISD::CLEANUPRET, getCurSDLoc(), MVT::Other, getControlRoot());
1758  DAG.setRoot(Ret);
1759 }
1760 
1761 void SelectionDAGBuilder::visitCatchSwitch(const CatchSwitchInst &CSI) {
1762  report_fatal_error("visitCatchSwitch not yet implemented!");
1763 }
1764 
1765 void SelectionDAGBuilder::visitRet(const ReturnInst &I) {
1766  const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1767  auto &DL = DAG.getDataLayout();
1768  SDValue Chain = getControlRoot();
1770  SmallVector<SDValue, 8> OutVals;
1771 
1772  // Calls to @llvm.experimental.deoptimize don't generate a return value, so
1773  // lower
1774  //
1775  // %val = call <ty> @llvm.experimental.deoptimize()
1776  // ret <ty> %val
1777  //
1778  // differently.
1780  LowerDeoptimizingReturn();
1781  return;
1782  }
1783 
1784  if (!FuncInfo.CanLowerReturn) {
1785  unsigned DemoteReg = FuncInfo.DemoteRegister;
1786  const Function *F = I.getParent()->getParent();
1787 
1788  // Emit a store of the return value through the virtual register.
1789  // Leave Outs empty so that LowerReturn won't try to load return
1790  // registers the usual way.
1791  SmallVector<EVT, 1> PtrValueVTs;
1792  ComputeValueVTs(TLI, DL,
1795  PtrValueVTs);
1796 
1797  SDValue RetPtr = DAG.getCopyFromReg(DAG.getEntryNode(), getCurSDLoc(),
1798  DemoteReg, PtrValueVTs[0]);
1799  SDValue RetOp = getValue(I.getOperand(0));
1800 
1801  SmallVector<EVT, 4> ValueVTs, MemVTs;
1803  ComputeValueVTs(TLI, DL, I.getOperand(0)->getType(), ValueVTs, &MemVTs,
1804  &Offsets);
1805  unsigned NumValues = ValueVTs.size();
1806 
1807  SmallVector<SDValue, 4> Chains(NumValues);
1808  for (unsigned i = 0; i != NumValues; ++i) {
1809  // An aggregate return value cannot wrap around the address space, so
1810  // offsets to its parts don't wrap either.
1811  SDValue Ptr = DAG.getObjectPtrOffset(getCurSDLoc(), RetPtr, Offsets[i]);
1812 
1813  SDValue Val = RetOp.getValue(i);
1814  if (MemVTs[i] != ValueVTs[i])
1815  Val = DAG.getPtrExtOrTrunc(Val, getCurSDLoc(), MemVTs[i]);
1816  Chains[i] = DAG.getStore(Chain, getCurSDLoc(), Val,
1817  // FIXME: better loc info would be nice.
1819  }
1820 
1821  Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(),
1822  MVT::Other, Chains);
1823  } else if (I.getNumOperands() != 0) {
1825  ComputeValueVTs(TLI, DL, I.getOperand(0)->getType(), ValueVTs);
1826  unsigned NumValues = ValueVTs.size();
1827  if (NumValues) {
1828  SDValue RetOp = getValue(I.getOperand(0));
1829 
1830  const Function *F = I.getParent()->getParent();
1831 
1832  bool NeedsRegBlock = TLI.functionArgumentNeedsConsecutiveRegisters(
1833  I.getOperand(0)->getType(), F->getCallingConv(),
1834  /*IsVarArg*/ false);
1835 
1836  ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
1837  if (F->getAttributes().hasAttribute(AttributeList::ReturnIndex,
1838  Attribute::SExt))
1839  ExtendKind = ISD::SIGN_EXTEND;
1840  else if (F->getAttributes().hasAttribute(AttributeList::ReturnIndex,
1841  Attribute::ZExt))
1842  ExtendKind = ISD::ZERO_EXTEND;
1843 
1844  LLVMContext &Context = F->getContext();
1845  bool RetInReg = F->getAttributes().hasAttribute(
1846  AttributeList::ReturnIndex, Attribute::InReg);
1847 
1848  for (unsigned j = 0; j != NumValues; ++j) {
1849  EVT VT = ValueVTs[j];
1850 
1851  if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger())
1852  VT = TLI.getTypeForExtReturn(Context, VT, ExtendKind);
1853 
1854  CallingConv::ID CC = F->getCallingConv();
1855 
1856  unsigned NumParts = TLI.getNumRegistersForCallingConv(Context, CC, VT);
1857  MVT PartVT = TLI.getRegisterTypeForCallingConv(Context, CC, VT);
1858  SmallVector<SDValue, 4> Parts(NumParts);
1859  getCopyToParts(DAG, getCurSDLoc(),
1860  SDValue(RetOp.getNode(), RetOp.getResNo() + j),
1861  &Parts[0], NumParts, PartVT, &I, CC, ExtendKind);
1862 
1863  // 'inreg' on function refers to return value
1864  ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
1865  if (RetInReg)
1866  Flags.setInReg();
1867 
1868  if (I.getOperand(0)->getType()->isPointerTy()) {
1869  Flags.setPointer();
1870  Flags.setPointerAddrSpace(
1871  cast<PointerType>(I.getOperand(0)->getType())->getAddressSpace());
1872  }
1873 
1874  if (NeedsRegBlock) {
1875  Flags.setInConsecutiveRegs();
1876  if (j == NumValues - 1)
1877  Flags.setInConsecutiveRegsLast();
1878  }
1879 
1880  // Propagate extension type if any
1881  if (ExtendKind == ISD::SIGN_EXTEND)
1882  Flags.setSExt();
1883  else if (ExtendKind == ISD::ZERO_EXTEND)
1884  Flags.setZExt();
1885 
1886  for (unsigned i = 0; i < NumParts; ++i) {
1887  Outs.push_back(ISD::OutputArg(Flags, Parts[i].getValueType(),
1888  VT, /*isfixed=*/true, 0, 0));
1889  OutVals.push_back(Parts[i]);
1890  }
1891  }
1892  }
1893  }
1894 
1895  // Push in swifterror virtual register as the last element of Outs. This makes
1896  // sure swifterror virtual register will be returned in the swifterror
1897  // physical register.
1898  const Function *F = I.getParent()->getParent();
1899  if (TLI.supportSwiftError() &&
1900  F->getAttributes().hasAttrSomewhere(Attribute::SwiftError)) {
1901  assert(SwiftError.getFunctionArg() && "Need a swift error argument");
1902  ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
1903  Flags.setSwiftError();
1904  Outs.push_back(ISD::OutputArg(Flags, EVT(TLI.getPointerTy(DL)) /*vt*/,
1905  EVT(TLI.getPointerTy(DL)) /*argvt*/,
1906  true /*isfixed*/, 1 /*origidx*/,
1907  0 /*partOffs*/));
1908  // Create SDNode for the swifterror virtual register.
1909  OutVals.push_back(
1910  DAG.getRegister(SwiftError.getOrCreateVRegUseAt(
1911  &I, FuncInfo.MBB, SwiftError.getFunctionArg()),
1912  EVT(TLI.getPointerTy(DL))));
1913  }
1914 
1915  bool isVarArg = DAG.getMachineFunction().getFunction().isVarArg();
1916  CallingConv::ID CallConv =
1918  Chain = DAG.getTargetLoweringInfo().LowerReturn(
1919  Chain, CallConv, isVarArg, Outs, OutVals, getCurSDLoc(), DAG);
1920 
1921  // Verify that the target's LowerReturn behaved as expected.
1922  assert(Chain.getNode() && Chain.getValueType() == MVT::Other &&
1923  "LowerReturn didn't return a valid chain!");
1924 
1925  // Update the DAG with the new chain value resulting from return lowering.
1926  DAG.setRoot(Chain);
1927 }
1928 
1929 /// CopyToExportRegsIfNeeded - If the given value has virtual registers
1930 /// created for it, emit nodes to copy the value into the virtual
1931 /// registers.
1933  // Skip empty types
1934  if (V->getType()->isEmptyTy())
1935  return;
1936 
1937  DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
1938  if (VMI != FuncInfo.ValueMap.end()) {
1939  assert(!V->use_empty() && "Unused value assigned virtual registers!");
1940  CopyValueToVirtualRegister(V, VMI->second);
1941  }
1942 }
1943 
1944 /// ExportFromCurrentBlock - If this condition isn't known to be exported from
1945 /// the current basic block, add it to ValueMap now so that we'll get a
1946 /// CopyTo/FromReg.
1948  // No need to export constants.
1949  if (!isa<Instruction>(V) && !isa<Argument>(V)) return;
1950 
1951  // Already exported?
1952  if (FuncInfo.isExportedInst(V)) return;
1953 
1954  unsigned Reg = FuncInfo.InitializeRegForValue(V);
1955  CopyValueToVirtualRegister(V, Reg);
1956 }
1957 
1959  const BasicBlock *FromBB) {
1960  // The operands of the setcc have to be in this block. We don't know
1961  // how to export them from some other block.
1962  if (const Instruction *VI = dyn_cast<Instruction>(V)) {
1963  // Can export from current BB.
1964  if (VI->getParent() == FromBB)
1965  return true;
1966 
1967  // Is already exported, noop.
1968  return FuncInfo.isExportedInst(V);
1969  }
1970 
1971  // If this is an argument, we can export it if the BB is the entry block or
1972  // if it is already exported.
1973  if (isa<Argument>(V)) {
1974  if (FromBB == &FromBB->getParent()->getEntryBlock())
1975  return true;
1976 
1977  // Otherwise, can only export this if it is already exported.
1978  return FuncInfo.isExportedInst(V);
1979  }
1980 
1981  // Otherwise, constants can always be exported.
1982  return true;
1983 }
1984 
1985 /// Return branch probability calculated by BranchProbabilityInfo for IR blocks.
1987 SelectionDAGBuilder::getEdgeProbability(const MachineBasicBlock *Src,
1988  const MachineBasicBlock *Dst) const {
1989  BranchProbabilityInfo *BPI = FuncInfo.BPI;
1990  const BasicBlock *SrcBB = Src->getBasicBlock();
1991  const BasicBlock *DstBB = Dst->getBasicBlock();
1992  if (!BPI) {
1993  // If BPI is not available, set the default probability as 1 / N, where N is
1994  // the number of successors.
1995  auto SuccSize = std::max<uint32_t>(succ_size(SrcBB), 1);
1996  return BranchProbability(1, SuccSize);
1997  }
1998  return BPI->getEdgeProbability(SrcBB, DstBB);
1999 }
2000 
2001 void SelectionDAGBuilder::addSuccessorWithProb(MachineBasicBlock *Src,
2002  MachineBasicBlock *Dst,
2003  BranchProbability Prob) {
2004  if (!FuncInfo.BPI)
2005  Src->addSuccessorWithoutProb(Dst);
2006  else {
2007  if (Prob.isUnknown())
2008  Prob = getEdgeProbability(Src, Dst);
2009  Src->addSuccessor(Dst, Prob);
2010  }
2011 }
2012 
2013 static bool InBlock(const Value *V, const BasicBlock *BB) {
2014  if (const Instruction *I = dyn_cast<Instruction>(V))
2015  return I->getParent() == BB;
2016  return true;
2017 }
2018 
2019 /// EmitBranchForMergedCondition - Helper method for FindMergedConditions.
2020 /// This function emits a branch and is used at the leaves of an OR or an
2021 /// AND operator tree.
2022 void
2024  MachineBasicBlock *TBB,
2025  MachineBasicBlock *FBB,
2026  MachineBasicBlock *CurBB,
2027  MachineBasicBlock *SwitchBB,
2028  BranchProbability TProb,
2029  BranchProbability FProb,
2030  bool InvertCond) {
2031  const BasicBlock *BB = CurBB->getBasicBlock();
2032 
2033  // If the leaf of the tree is a comparison, merge the condition into
2034  // the caseblock.
2035  if (const CmpInst *BOp = dyn_cast<CmpInst>(Cond)) {
2036  // The operands of the cmp have to be in this block. We don't know
2037  // how to export them from some other block. If this is the first block
2038  // of the sequence, no exporting is needed.
2039  if (CurBB == SwitchBB ||
2040  (isExportableFromCurrentBlock(BOp->getOperand(0), BB) &&
2041  isExportableFromCurrentBlock(BOp->getOperand(1), BB))) {
2042  ISD::CondCode Condition;
2043  if (const ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) {
2044  ICmpInst::Predicate Pred =
2045  InvertCond ? IC->getInversePredicate() : IC->getPredicate();
2046  Condition = getICmpCondCode(Pred);
2047  } else {
2048  const FCmpInst *FC = cast<FCmpInst>(Cond);
2049  FCmpInst::Predicate Pred =
2050  InvertCond ? FC->getInversePredicate() : FC->getPredicate();
2051  Condition = getFCmpCondCode(Pred);
2052  if (TM.Options.NoNaNsFPMath)
2053  Condition = getFCmpCodeWithoutNaN(Condition);
2054  }
2055 
2056  CaseBlock CB(Condition, BOp->getOperand(0), BOp->getOperand(1), nullptr,
2057  TBB, FBB, CurBB, getCurSDLoc(), TProb, FProb);
2058  SL->SwitchCases.push_back(CB);
2059  return;
2060  }
2061  }
2062 
2063  // Create a CaseBlock record representing this branch.
2064  ISD::CondCode Opc = InvertCond ? ISD::SETNE : ISD::SETEQ;
2065  CaseBlock CB(Opc, Cond, ConstantInt::getTrue(*DAG.getContext()),
2066  nullptr, TBB, FBB, CurBB, getCurSDLoc(), TProb, FProb);
2067  SL->SwitchCases.push_back(CB);
2068 }
2069 
2071  MachineBasicBlock *TBB,
2072  MachineBasicBlock *FBB,
2073  MachineBasicBlock *CurBB,
2074  MachineBasicBlock *SwitchBB,
2076  BranchProbability TProb,
2077  BranchProbability FProb,
2078  bool InvertCond) {
2079  // Skip over not part of the tree and remember to invert op and operands at
2080  // next level.
2081  Value *NotCond;
2082  if (match(Cond, m_OneUse(m_Not(m_Value(NotCond)))) &&
2083  InBlock(NotCond, CurBB->getBasicBlock())) {
2084  FindMergedConditions(NotCond, TBB, FBB, CurBB, SwitchBB, Opc, TProb, FProb,
2085  !InvertCond);
2086  return;
2087  }
2088 
2089  const Instruction *BOp = dyn_cast<Instruction>(Cond);
2090  // Compute the effective opcode for Cond, taking into account whether it needs
2091  // to be inverted, e.g.
2092  // and (not (or A, B)), C
2093  // gets lowered as
2094  // and (and (not A, not B), C)
2095  unsigned BOpc = 0;
2096  if (BOp) {
2097  BOpc = BOp->getOpcode();
2098  if (InvertCond) {
2099  if (BOpc == Instruction::And)
2100  BOpc = Instruction::Or;
2101  else if (BOpc == Instruction::Or)
2102  BOpc = Instruction::And;
2103  }
2104  }
2105 
2106  // If this node is not part of the or/and tree, emit it as a branch.
2107  if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) ||
2108  BOpc != unsigned(Opc) || !BOp->hasOneUse() ||
2109  BOp->getParent() != CurBB->getBasicBlock() ||
2110  !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) ||
2111  !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) {
2112  EmitBranchForMergedCondition(Cond, TBB, FBB, CurBB, SwitchBB,
2113  TProb, FProb, InvertCond);
2114  return;
2115  }
2116 
2117  // Create TmpBB after CurBB.
2118  MachineFunction::iterator BBI(CurBB);
2119  MachineFunction &MF = DAG.getMachineFunction();
2121  CurBB->getParent()->insert(++BBI, TmpBB);
2122 
2123  if (Opc == Instruction::Or) {
2124  // Codegen X | Y as:
2125  // BB1:
2126  // jmp_if_X TBB
2127  // jmp TmpBB
2128  // TmpBB:
2129  // jmp_if_Y TBB
2130  // jmp FBB
2131  //
2132 
2133  // We have flexibility in setting Prob for BB1 and Prob for TmpBB.
2134  // The requirement is that
2135  // TrueProb for BB1 + (FalseProb for BB1 * TrueProb for TmpBB)
2136  // = TrueProb for original BB.
2137  // Assuming the original probabilities are A and B, one choice is to set
2138  // BB1's probabilities to A/2 and A/2+B, and set TmpBB's probabilities to
2139  // A/(1+B) and 2B/(1+B). This choice assumes that
2140  // TrueProb for BB1 == FalseProb for BB1 * TrueProb for TmpBB.
2141  // Another choice is to assume TrueProb for BB1 equals to TrueProb for
2142  // TmpBB, but the math is more complicated.
2143 
2144  auto NewTrueProb = TProb / 2;
2145  auto NewFalseProb = TProb / 2 + FProb;
2146  // Emit the LHS condition.
2147  FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, SwitchBB, Opc,
2148  NewTrueProb, NewFalseProb, InvertCond);
2149 
2150  // Normalize A/2 and B to get A/(1+B) and 2B/(1+B).
2151  SmallVector<BranchProbability, 2> Probs{TProb / 2, FProb};
2152  BranchProbability::normalizeProbabilities(Probs.begin(), Probs.end());
2153  // Emit the RHS condition into TmpBB.
2154  FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc,
2155  Probs[0], Probs[1], InvertCond);
2156  } else {
2157  assert(Opc == Instruction::And && "Unknown merge op!");
2158  // Codegen X & Y as:
2159  // BB1:
2160  // jmp_if_X TmpBB
2161  // jmp FBB
2162  // TmpBB:
2163  // jmp_if_Y TBB
2164  // jmp FBB
2165  //
2166  // This requires creation of TmpBB after CurBB.
2167 
2168  // We have flexibility in setting Prob for BB1 and Prob for TmpBB.
2169  // The requirement is that
2170  // FalseProb for BB1 + (TrueProb for BB1 * FalseProb for TmpBB)
2171  // = FalseProb for original BB.
2172  // Assuming the original probabilities are A and B, one choice is to set
2173  // BB1's probabilities to A+B/2 and B/2, and set TmpBB's probabilities to
2174  // 2A/(1+A) and B/(1+A). This choice assumes that FalseProb for BB1 ==
2175  // TrueProb for BB1 * FalseProb for TmpBB.
2176 
2177  auto NewTrueProb = TProb + FProb / 2;
2178  auto NewFalseProb = FProb / 2;
2179  // Emit the LHS condition.
2180  FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, SwitchBB, Opc,
2181  NewTrueProb, NewFalseProb, InvertCond);
2182 
2183  // Normalize A and B/2 to get 2A/(1+A) and B/(1+A).
2184  SmallVector<BranchProbability, 2> Probs{TProb, FProb / 2};
2185  BranchProbability::normalizeProbabilities(Probs.begin(), Probs.end());
2186  // Emit the RHS condition into TmpBB.
2187  FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc,
2188  Probs[0], Probs[1], InvertCond);
2189  }
2190 }
2191 
2192 /// If the set of cases should be emitted as a series of branches, return true.
2193 /// If we should emit this as a bunch of and/or'd together conditions, return
2194 /// false.
2195 bool
2196 SelectionDAGBuilder::ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases) {
2197  if (Cases.size() != 2) return true;
2198 
2199  // If this is two comparisons of the same values or'd or and'd together, they
2200  // will get folded into a single comparison, so don't emit two blocks.
2201  if ((Cases[0].CmpLHS == Cases[1].CmpLHS &&
2202  Cases[0].CmpRHS == Cases[1].CmpRHS) ||
2203  (Cases[0].CmpRHS == Cases[1].CmpLHS &&
2204  Cases[0].CmpLHS == Cases[1].CmpRHS)) {
2205  return false;
2206  }
2207 
2208  // Handle: (X != null) | (Y != null) --> (X|Y) != 0
2209  // Handle: (X == null) & (Y == null) --> (X|Y) == 0
2210  if (Cases[0].CmpRHS == Cases[1].CmpRHS &&
2211  Cases[0].CC == Cases[1].CC &&
2212  isa<Constant>(Cases[0].CmpRHS) &&
2213  cast<Constant>(Cases[0].CmpRHS)->isNullValue()) {
2214  if (Cases[0].CC == ISD::SETEQ && Cases[0].TrueBB == Cases[1].ThisBB)
2215  return false;
2216  if (Cases[0].CC == ISD::SETNE && Cases[0].FalseBB == Cases[1].ThisBB)
2217  return false;
2218  }
2219 
2220  return true;
2221 }
2222 
2223 void SelectionDAGBuilder::visitBr(const BranchInst &I) {
2224  MachineBasicBlock *BrMBB = FuncInfo.MBB;
2225 
2226  // Update machine-CFG edges.
2227  MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
2228 
2229  if (I.isUnconditional()) {
2230  // Update machine-CFG edges.
2231  BrMBB->addSuccessor(Succ0MBB);
2232 
2233  // If this is not a fall-through branch or optimizations are switched off,
2234  // emit the branch.
2235  if (Succ0MBB != NextBlock(BrMBB) || TM.getOptLevel() == CodeGenOpt::None)
2236  DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(),
2237  MVT::Other, getControlRoot(),
2238  DAG.getBasicBlock(Succ0MBB)));
2239 
2240  return;
2241  }
2242 
2243  // If this condition is one of the special cases we handle, do special stuff
2244  // now.
2245  const Value *CondVal = I.getCondition();
2246  MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
2247 
2248  // If this is a series of conditions that are or'd or and'd together, emit
2249  // this as a sequence of branches instead of setcc's with and/or operations.
2250  // As long as jumps are not expensive, this should improve performance.
2251  // For example, instead of something like:
2252  // cmp A, B
2253  // C = seteq
2254  // cmp D, E
2255  // F = setle
2256  // or C, F
2257  // jnz foo
2258  // Emit:
2259  // cmp A, B
2260  // je foo
2261  // cmp D, E
2262  // jle foo
2263  if (const BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) {
2264  Instruction::BinaryOps Opcode = BOp->getOpcode();
2265  if (!DAG.getTargetLoweringInfo().isJumpExpensive() && BOp->hasOneUse() &&
2267  (Opcode == Instruction::And || Opcode == Instruction::Or)) {
2268  FindMergedConditions(BOp, Succ0MBB, Succ1MBB, BrMBB, BrMBB,
2269  Opcode,
2270  getEdgeProbability(BrMBB, Succ0MBB),
2271  getEdgeProbability(BrMBB, Succ1MBB),
2272  /*InvertCond=*/false);
2273  // If the compares in later blocks need to use values not currently
2274  // exported from this block, export them now. This block should always
2275  // be the first entry.
2276  assert(SL->SwitchCases[0].ThisBB == BrMBB && "Unexpected lowering!");
2277 
2278  // Allow some cases to be rejected.
2279  if (ShouldEmitAsBranches(SL->SwitchCases)) {
2280  for (unsigned i = 1, e = SL->SwitchCases.size(); i != e; ++i) {
2281  ExportFromCurrentBlock(SL->SwitchCases[i].CmpLHS);
2282  ExportFromCurrentBlock(SL->SwitchCases[i].CmpRHS);
2283  }
2284 
2285  // Emit the branch for this block.
2286  visitSwitchCase(SL->SwitchCases[0], BrMBB);
2287  SL->SwitchCases.erase(SL->SwitchCases.begin());
2288  return;
2289  }
2290 
2291  // Okay, we decided not to do this, remove any inserted MBB's and clear
2292  // SwitchCases.
2293  for (unsigned i = 1, e = SL->SwitchCases.size(); i != e; ++i)
2294  FuncInfo.MF->erase(SL->SwitchCases[i].ThisBB);
2295 
2296  SL->SwitchCases.clear();
2297  }
2298  }
2299 
2300  // Create a CaseBlock record representing this branch.
2301  CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(*DAG.getContext()),
2302  nullptr, Succ0MBB, Succ1MBB, BrMBB, getCurSDLoc());
2303 
2304  // Use visitSwitchCase to actually insert the fast branch sequence for this
2305  // cond branch.
2306  visitSwitchCase(CB, BrMBB);
2307 }
2308 
2309 /// visitSwitchCase - Emits the necessary code to represent a single node in
2310 /// the binary search tree resulting from lowering a switch instruction.
2312  MachineBasicBlock *SwitchBB) {
2313  SDValue Cond;
2314  SDValue CondLHS = getValue(CB.CmpLHS);
2315  SDLoc dl = CB.DL;
2316 
2317  if (CB.CC == ISD::SETTRUE) {
2318  // Branch or fall through to TrueBB.
2319  addSuccessorWithProb(SwitchBB, CB.TrueBB, CB.TrueProb);
2320  SwitchBB->normalizeSuccProbs();
2321  if (CB.TrueBB != NextBlock(SwitchBB)) {
2322  DAG.setRoot(DAG.getNode(ISD::BR, dl, MVT::Other, getControlRoot(),
2323  DAG.getBasicBlock(CB.TrueBB)));
2324  }
2325  return;
2326  }
2327 
2328  auto &TLI = DAG.getTargetLoweringInfo();
2329  EVT MemVT = TLI.getMemValueType(DAG.getDataLayout(), CB.CmpLHS->getType());
2330 
2331  // Build the setcc now.
2332  if (!CB.CmpMHS) {
2333  // Fold "(X == true)" to X and "(X == false)" to !X to
2334  // handle common cases produced by branch lowering.
2335  if (CB.CmpRHS == ConstantInt::getTrue(*DAG.getContext()) &&
2336  CB.CC == ISD::SETEQ)
2337  Cond = CondLHS;
2338  else if (CB.CmpRHS == ConstantInt::getFalse(*DAG.getContext()) &&
2339  CB.CC == ISD::SETEQ) {
2340  SDValue True = DAG.getConstant(1, dl, CondLHS.getValueType());
2341  Cond = DAG.getNode(ISD::XOR, dl, CondLHS.getValueType(), CondLHS, True);
2342  } else {
2343  SDValue CondRHS = getValue(CB.CmpRHS);
2344 
2345  // If a pointer's DAG type is larger than its memory type then the DAG
2346  // values are zero-extended. This breaks signed comparisons so truncate
2347  // back to the underlying type before doing the compare.
2348  if (CondLHS.getValueType() != MemVT) {
2349  CondLHS = DAG.getPtrExtOrTrunc(CondLHS, getCurSDLoc(), MemVT);
2350  CondRHS = DAG.getPtrExtOrTrunc(CondRHS, getCurSDLoc(), MemVT);
2351  }
2352  Cond = DAG.getSetCC(dl, MVT::i1, CondLHS, CondRHS, CB.CC);
2353  }
2354  } else {
2355  assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now");
2356 
2357  const APInt& Low = cast<ConstantInt>(CB.CmpLHS)->getValue();
2358  const APInt& High = cast<ConstantInt>(CB.CmpRHS)->getValue();
2359 
2360  SDValue CmpOp = getValue(CB.CmpMHS);
2361  EVT VT = CmpOp.getValueType();
2362 
2363  if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) {
2364  Cond = DAG.getSetCC(dl, MVT::i1, CmpOp, DAG.getConstant(High, dl, VT),
2365  ISD::SETLE);
2366  } else {
2367  SDValue SUB = DAG.getNode(ISD::SUB, dl,
2368  VT, CmpOp, DAG.getConstant(Low, dl, VT));
2369  Cond = DAG.getSetCC(dl, MVT::i1, SUB,
2370  DAG.getConstant(High-Low, dl, VT), ISD::SETULE);
2371  }
2372  }
2373 
2374  // Update successor info
2375  addSuccessorWithProb(SwitchBB, CB.TrueBB, CB.TrueProb);
2376  // TrueBB and FalseBB are always different unless the incoming IR is
2377  // degenerate. This only happens when running llc on weird IR.
2378  if (CB.TrueBB != CB.FalseBB)
2379  addSuccessorWithProb(SwitchBB, CB.FalseBB, CB.FalseProb);
2380  SwitchBB->normalizeSuccProbs();
2381 
2382  // If the lhs block is the next block, invert the condition so that we can
2383  // fall through to the lhs instead of the rhs block.
2384  if (CB.TrueBB == NextBlock(SwitchBB)) {
2385  std::swap(CB.TrueBB, CB.FalseBB);
2386  SDValue True = DAG.getConstant(1, dl, Cond.getValueType());
2387  Cond = DAG.getNode(ISD::XOR, dl, Cond.getValueType(), Cond, True);
2388  }
2389 
2390  SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
2391  MVT::Other, getControlRoot(), Cond,
2392  DAG.getBasicBlock(CB.TrueBB));
2393 
2394  // Insert the false branch. Do this even if it's a fall through branch,
2395  // this makes it easier to do DAG optimizations which require inverting
2396  // the branch condition.
2397  BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond,
2398  DAG.getBasicBlock(CB.FalseBB));
2399 
2400  DAG.setRoot(BrCond);
2401 }
2402 
2403 /// visitJumpTable - Emit JumpTable node in the current MBB
2405  // Emit the code for the jump table
2406  assert(JT.Reg != -1U && "Should lower JT Header first!");
2408  SDValue Index = DAG.getCopyFromReg(getControlRoot(), getCurSDLoc(),
2409  JT.Reg, PTy);
2410  SDValue Table = DAG.getJumpTable(JT.JTI, PTy);
2411  SDValue BrJumpTable = DAG.getNode(ISD::BR_JT, getCurSDLoc(),
2412  MVT::Other, Index.getValue(1),
2413  Table, Index);
2414  DAG.setRoot(BrJumpTable);
2415 }
2416 
2417 /// visitJumpTableHeader - This function emits necessary code to produce index
2418 /// in the JumpTable from switch case.
2420  JumpTableHeader &JTH,
2421  MachineBasicBlock *SwitchBB) {
2422  SDLoc dl = getCurSDLoc();
2423 
2424  // Subtract the lowest switch case value from the value being switched on.
2425  SDValue SwitchOp = getValue(JTH.SValue);
2426  EVT VT = SwitchOp.getValueType();
2427  SDValue Sub = DAG.getNode(ISD::SUB, dl, VT, SwitchOp,
2428  DAG.getConstant(JTH.First, dl, VT));
2429 
2430  // The SDNode we just created, which holds the value being switched on minus
2431  // the smallest case value, needs to be copied to a virtual register so it
2432  // can be used as an index into the jump table in a subsequent basic block.
2433  // This value may be smaller or larger than the target's pointer type, and
2434  // therefore require extension or truncating.
2435  const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2436  SwitchOp = DAG.getZExtOrTrunc(Sub, dl, TLI.getPointerTy(DAG.getDataLayout()));
2437 
2438  unsigned JumpTableReg =
2439  FuncInfo.CreateReg(TLI.getPointerTy(DAG.getDataLayout()));
2440  SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), dl,
2441  JumpTableReg, SwitchOp);
2442  JT.Reg = JumpTableReg;
2443 
2444  if (!JTH.OmitRangeCheck) {
2445  // Emit the range check for the jump table, and branch to the default block
2446  // for the switch statement if the value being switched on exceeds the
2447  // largest case in the switch.
2448  SDValue CMP = DAG.getSetCC(
2449  dl, TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(),
2450  Sub.getValueType()),
2451  Sub, DAG.getConstant(JTH.Last - JTH.First, dl, VT), ISD::SETUGT);
2452 
2453  SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
2454  MVT::Other, CopyTo, CMP,
2455  DAG.getBasicBlock(JT.Default));
2456 
2457  // Avoid emitting unnecessary branches to the next block.
2458  if (JT.MBB != NextBlock(SwitchBB))
2459  BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond,
2460  DAG.getBasicBlock(JT.MBB));
2461 
2462  DAG.setRoot(BrCond);
2463  } else {
2464  // Avoid emitting unnecessary branches to the next block.
2465  if (JT.MBB != NextBlock(SwitchBB))
2466  DAG.setRoot(DAG.getNode(ISD::BR, dl, MVT::Other, CopyTo,
2467  DAG.getBasicBlock(JT.MBB)));
2468  else
2469  DAG.setRoot(CopyTo);
2470  }
2471 }
2472 
2473 /// Create a LOAD_STACK_GUARD node, and let it carry the target specific global
2474 /// variable if there exists one.
2476  SDValue &Chain) {
2477  const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2478  EVT PtrTy = TLI.getPointerTy(DAG.getDataLayout());
2479  EVT PtrMemTy = TLI.getPointerMemTy(DAG.getDataLayout());
2480  MachineFunction &MF = DAG.getMachineFunction();
2481  Value *Global = TLI.getSDagStackGuard(*MF.getFunction().getParent());
2482  MachineSDNode *Node =
2483  DAG.getMachineNode(TargetOpcode::LOAD_STACK_GUARD, DL, PtrTy, Chain);
2484  if (Global) {
2485  MachinePointerInfo MPInfo(Global);
2489  MPInfo, Flags, PtrTy.getSizeInBits() / 8, DAG.getEVTAlignment(PtrTy));
2490  DAG.setNodeMemRefs(Node, {MemRef});
2491  }
2492  if (PtrTy != PtrMemTy)
2493  return DAG.getPtrExtOrTrunc(SDValue(Node, 0), DL, PtrMemTy);
2494  return SDValue(Node, 0);
2495 }
2496 
2497 /// Codegen a new tail for a stack protector check ParentMBB which has had its
2498 /// tail spliced into a stack protector check success bb.
2499 ///
2500 /// For a high level explanation of how this fits into the stack protector
2501 /// generation see the comment on the declaration of class
2502 /// StackProtectorDescriptor.
2503 void SelectionDAGBuilder::visitSPDescriptorParent(StackProtectorDescriptor &SPD,
2504  MachineBasicBlock *ParentBB) {
2505 
2506  // First create the loads to the guard/stack slot for the comparison.
2507  const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2508  EVT PtrTy = TLI.getPointerTy(DAG.getDataLayout());
2509  EVT PtrMemTy = TLI.getPointerMemTy(DAG.getDataLayout());
2510 
2511  MachineFrameInfo &MFI = ParentBB->getParent()->getFrameInfo();
2512  int FI = MFI.getStackProtectorIndex();
2513 
2514  SDValue Guard;
2515  SDLoc dl = getCurSDLoc();
2516  SDValue StackSlotPtr = DAG.getFrameIndex(FI, PtrTy);
2517  const Module &M = *ParentBB->getParent()->getFunction().getParent();
2518  unsigned Align = DL->getPrefTypeAlignment(Type::getInt8PtrTy(M.getContext()));
2519 
2520  // Generate code to load the content of the guard slot.
2521  SDValue GuardVal = DAG.getLoad(
2522  PtrMemTy, dl, DAG.getEntryNode(), StackSlotPtr,
2525 
2526  if (TLI.useStackGuardXorFP())
2527  GuardVal = TLI.emitStackGuardXorFP(DAG, GuardVal, dl);
2528 
2529  // Retrieve guard check function, nullptr if instrumentation is inlined.
2530  if (const Function *GuardCheckFn = TLI.getSSPStackGuardCheck(M)) {
2531  // The target provides a guard check function to validate the guard value.
2532  // Generate a call to that function with the content of the guard slot as
2533  // argument.
2534  FunctionType *FnTy = GuardCheckFn->getFunctionType();
2535  assert(FnTy->getNumParams() == 1 && "Invalid function signature");
2536 
2539  Entry.Node = GuardVal;
2540  Entry.Ty = FnTy->getParamType(0);
2541  if (GuardCheckFn->hasAttribute(1, Attribute::AttrKind::InReg))
2542  Entry.IsInReg = true;
2543  Args.push_back(Entry);
2544 
2546  CLI.setDebugLoc(getCurSDLoc())
2547  .setChain(DAG.getEntryNode())
2548  .setCallee(GuardCheckFn->getCallingConv(), FnTy->getReturnType(),
2549  getValue(GuardCheckFn), std::move(Args));
2550 
2551  std::pair<SDValue, SDValue> Result = TLI.LowerCallTo(CLI);
2552  DAG.setRoot(Result.second);
2553  return;
2554  }
2555 
2556  // If useLoadStackGuardNode returns true, generate LOAD_STACK_GUARD.
2557  // Otherwise, emit a volatile load to retrieve the stack guard value.
2558  SDValue Chain = DAG.getEntryNode();
2559  if (TLI.useLoadStackGuardNode()) {
2560  Guard = getLoadStackGuard(DAG, dl, Chain);
2561  } else {
2562  const Value *IRGuard = TLI.getSDagStackGuard(M);
2563  SDValue GuardPtr = getValue(IRGuard);
2564 
2565  Guard = DAG.getLoad(PtrMemTy, dl, Chain, GuardPtr,
2566  MachinePointerInfo(IRGuard, 0), Align,
2568  }
2569 
2570  // Perform the comparison via a subtract/getsetcc.
2571  EVT VT = Guard.getValueType();
2572  SDValue Sub = DAG.getNode(ISD::SUB, dl, VT, Guard, GuardVal);
2573 
2574  SDValue Cmp = DAG.getSetCC(dl, TLI.getSetCCResultType(DAG.getDataLayout(),
2575  *DAG.getContext(),
2576  Sub.getValueType()),
2577  Sub, DAG.getConstant(0, dl, VT), ISD::SETNE);
2578 
2579  // If the sub is not 0, then we know the guard/stackslot do not equal, so
2580  // branch to failure MBB.
2581  SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
2582  MVT::Other, GuardVal.getOperand(0),
2583  Cmp, DAG.getBasicBlock(SPD.getFailureMBB()));
2584  // Otherwise branch to success MBB.
2585  SDValue Br = DAG.getNode(ISD::BR, dl,
2586  MVT::Other, BrCond,
2587  DAG.getBasicBlock(SPD.getSuccessMBB()));
2588 
2589  DAG.setRoot(Br);
2590 }
2591 
2592 /// Codegen the failure basic block for a stack protector check.
2593 ///
2594 /// A failure stack protector machine basic block consists simply of a call to
2595 /// __stack_chk_fail().
2596 ///
2597 /// For a high level explanation of how this fits into the stack protector
2598 /// generation see the comment on the declaration of class
2599 /// StackProtectorDescriptor.
2600 void
2601 SelectionDAGBuilder::visitSPDescriptorFailure(StackProtectorDescriptor &SPD) {
2602  const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2603  SDValue Chain =
2604  TLI.makeLibCall(DAG, RTLIB::STACKPROTECTOR_CHECK_FAIL, MVT::isVoid,
2605  None, false, getCurSDLoc(), false, false).second;
2606  // On PS4, the "return address" must still be within the calling function,
2607  // even if it's at the very end, so emit an explicit TRAP here.
2608  // Passing 'true' for doesNotReturn above won't generate the trap for us.
2609  if (TM.getTargetTriple().isPS4CPU())
2610  Chain = DAG.getNode(ISD::TRAP, getCurSDLoc(), MVT::Other, Chain);
2611 
2612  DAG.setRoot(Chain);
2613 }
2614 
2615 /// visitBitTestHeader - This function emits necessary code to produce value
2616 /// suitable for "bit tests"
2618  MachineBasicBlock *SwitchBB) {
2619  SDLoc dl = getCurSDLoc();
2620 
2621  // Subtract the minimum value
2622  SDValue SwitchOp = getValue(B.SValue);
2623  EVT VT = SwitchOp.getValueType();
2624  SDValue Sub = DAG.getNode(ISD::SUB, dl, VT, SwitchOp,
2625  DAG.getConstant(B.First, dl, VT));
2626 
2627  // Check range
2628  const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2629  SDValue RangeCmp = DAG.getSetCC(
2630  dl, TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(),
2631  Sub.getValueType()),
2632  Sub, DAG.getConstant(B.Range, dl, VT), ISD::SETUGT);
2633 
2634  // Determine the type of the test operands.
2635  bool UsePtrType = false;
2636  if (!TLI.isTypeLegal(VT))
2637  UsePtrType = true;
2638  else {
2639  for (unsigned i = 0, e = B.Cases.size(); i != e; ++i)
2640  if (!isUIntN(VT.getSizeInBits(), B.Cases[i].Mask)) {
2641  // Switch table case range are encoded into series of masks.
2642  // Just use pointer type, it's guaranteed to fit.
2643  UsePtrType = true;
2644  break;
2645  }
2646  }
2647  if (UsePtrType) {
2648  VT = TLI.getPointerTy(DAG.getDataLayout());
2649  Sub = DAG.getZExtOrTrunc(Sub, dl, VT);
2650  }
2651 
2652  B.RegVT = VT.getSimpleVT();
2653  B.Reg = FuncInfo.CreateReg(B.RegVT);
2654  SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), dl, B.Reg, Sub);
2655 
2656  MachineBasicBlock* MBB = B.Cases[0].ThisBB;
2657 
2658  addSuccessorWithProb(SwitchBB, B.Default, B.DefaultProb);
2659  addSuccessorWithProb(SwitchBB, MBB, B.Prob);
2660  SwitchBB->normalizeSuccProbs();
2661 
2662  SDValue BrRange = DAG.getNode(ISD::BRCOND, dl,
2663  MVT::Other, CopyTo, RangeCmp,
2664  DAG.getBasicBlock(B.Default));
2665 
2666  // Avoid emitting unnecessary branches to the next block.
2667  if (MBB != NextBlock(SwitchBB))
2668  BrRange = DAG.getNode(ISD::BR, dl, MVT::Other, BrRange,
2669  DAG.getBasicBlock(MBB));
2670 
2671  DAG.setRoot(BrRange);
2672 }
2673 
2674 /// visitBitTestCase - this function produces one "bit test"
2676  MachineBasicBlock* NextMBB,
2677  BranchProbability BranchProbToNext,
2678  unsigned Reg,
2679  BitTestCase &B,
2680  MachineBasicBlock *SwitchBB) {
2681  SDLoc dl = getCurSDLoc();
2682  MVT VT = BB.RegVT;
2683  SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), dl, Reg, VT);
2684  SDValue Cmp;
2685  unsigned PopCount = countPopulation(B.Mask);
2686  const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2687  if (PopCount == 1) {
2688  // Testing for a single bit; just compare the shift count with what it
2689  // would need to be to shift a 1 bit in that position.
2690  Cmp = DAG.getSetCC(
2691  dl, TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT),
2692  ShiftOp, DAG.getConstant(countTrailingZeros(B.Mask), dl, VT),
2693  ISD::SETEQ);
2694  } else if (PopCount == BB.Range) {
2695  // There is only one zero bit in the range, test for it directly.
2696  Cmp = DAG.getSetCC(
2697  dl, TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT),
2698  ShiftOp, DAG.getConstant(countTrailingOnes(B.Mask), dl, VT),
2699  ISD::SETNE);
2700  } else {
2701  // Make desired shift
2702  SDValue SwitchVal = DAG.getNode(ISD::SHL, dl, VT,
2703  DAG.getConstant(1, dl, VT), ShiftOp);
2704 
2705  // Emit bit tests and jumps
2706  SDValue AndOp = DAG.getNode(ISD::AND, dl,
2707  VT, SwitchVal, DAG.getConstant(B.Mask, dl, VT));
2708  Cmp = DAG.getSetCC(
2709  dl, TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT),
2710  AndOp, DAG.getConstant(0, dl, VT), ISD::SETNE);
2711  }
2712 
2713  // The branch probability from SwitchBB to B.TargetBB is B.ExtraProb.
2714  addSuccessorWithProb(SwitchBB, B.TargetBB, B.ExtraProb);
2715  // The branch probability from SwitchBB to NextMBB is BranchProbToNext.
2716  addSuccessorWithProb(SwitchBB, NextMBB, BranchProbToNext);
2717  // It is not guaranteed that the sum of B.ExtraProb and BranchProbToNext is
2718  // one as they are relative probabilities (and thus work more like weights),
2719  // and hence we need to normalize them to let the sum of them become one.
2720  SwitchBB->normalizeSuccProbs();
2721 
2722  SDValue BrAnd = DAG.getNode(ISD::BRCOND, dl,
2723  MVT::Other, getControlRoot(),
2724  Cmp, DAG.getBasicBlock(B.TargetBB));
2725 
2726  // Avoid emitting unnecessary branches to the next block.
2727  if (NextMBB != NextBlock(SwitchBB))
2728  BrAnd = DAG.getNode(ISD::BR, dl, MVT::Other, BrAnd,
2729  DAG.getBasicBlock(NextMBB));
2730 
2731  DAG.setRoot(BrAnd);
2732 }
2733 
2734 void SelectionDAGBuilder::visitInvoke(const InvokeInst &I) {
2735  MachineBasicBlock *InvokeMBB = FuncInfo.MBB;
2736 
2737  // Retrieve successors. Look through artificial IR level blocks like
2738  // catchswitch for successors.
2739  MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)];
2740  const BasicBlock *EHPadBB = I.getSuccessor(1);
2741 
2742  // Deopt bundles are lowered in LowerCallSiteWithDeoptBundle, and we don't
2743  // have to do anything here to lower funclet bundles.
2745  {LLVMContext::OB_deopt, LLVMContext::OB_funclet}) &&
2746  "Cannot lower invokes with arbitrary operand bundles yet!");
2747 
2748  const Value *Callee(I.getCalledValue());
2749  const Function *Fn = dyn_cast<Function>(Callee);
2750  if (isa<InlineAsm>(Callee))
2751  visitInlineAsm(&I);
2752  else if (Fn && Fn->isIntrinsic()) {
2753  switch (Fn->getIntrinsicID()) {
2754  default:
2755  llvm_unreachable("Cannot invoke this intrinsic");
2756  case Intrinsic::donothing:
2757  // Ignore invokes to @llvm.donothing: jump directly to the next BB.
2758  break;
2759  case Intrinsic::experimental_patchpoint_void:
2760  case Intrinsic::experimental_patchpoint_i64:
2761  visitPatchpoint(&I, EHPadBB);
2762  break;
2763  case Intrinsic::experimental_gc_statepoint:
2764  LowerStatepoint(ImmutableStatepoint(&I), EHPadBB);
2765  break;
2766  case Intrinsic::wasm_rethrow_in_catch: {
2767  // This is usually done in visitTargetIntrinsic, but this intrinsic is
2768  // special because it can be invoked, so we manually lower it to a DAG
2769  // node here.
2771  Ops.push_back(getRoot()); // inchain
2772  const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2773  Ops.push_back(
2774  DAG.getTargetConstant(Intrinsic::wasm_rethrow_in_catch, getCurSDLoc(),
2775  TLI.getPointerTy(DAG.getDataLayout())));
2776  SDVTList VTs = DAG.getVTList(ArrayRef<EVT>({MVT::Other})); // outchain
2777  DAG.setRoot(DAG.getNode(ISD::INTRINSIC_VOID, getCurSDLoc(), VTs, Ops));
2778  break;
2779  }
2780  }
2782  // Currently we do not lower any intrinsic calls with deopt operand bundles.
2783  // Eventually we will support lowering the @llvm.experimental.deoptimize
2784  // intrinsic, and right now there are no plans to support other intrinsics
2785  // with deopt state.
2786  LowerCallSiteWithDeoptBundle(&I, getValue(Callee), EHPadBB);
2787  } else {
2788  LowerCallTo(&I, getValue(Callee), false, EHPadBB);
2789  }
2790 
2791  // If the value of the invoke is used outside of its defining block, make it
2792  // available as a virtual register.
2793  // We already took care of the exported value for the statepoint instruction
2794  // during call to the LowerStatepoint.
2795  if (!isStatepoint(I)) {
2796  CopyToExportRegsIfNeeded(&I);
2797  }
2798 
2800  BranchProbabilityInfo *BPI = FuncInfo.BPI;
2801  BranchProbability EHPadBBProb =
2802  BPI ? BPI->getEdgeProbability(InvokeMBB->getBasicBlock(), EHPadBB)
2804  findUnwindDestinations(FuncInfo, EHPadBB, EHPadBBProb, UnwindDests);
2805 
2806  // Update successor info.
2807  addSuccessorWithProb(InvokeMBB, Return);
2808  for (auto &UnwindDest : UnwindDests) {
2809  UnwindDest.first->setIsEHPad();
2810  addSuccessorWithProb(InvokeMBB, UnwindDest.first, UnwindDest.second);
2811  }
2812  InvokeMBB->normalizeSuccProbs();
2813 
2814  // Drop into normal successor.
2815  DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other, getControlRoot(),
2816  DAG.getBasicBlock(Return)));
2817 }
2818 
2819 void SelectionDAGBuilder::visitCallBr(const CallBrInst &I) {
2820  MachineBasicBlock *CallBrMBB = FuncInfo.MBB;
2821 
2822  // Deopt bundles are lowered in LowerCallSiteWithDeoptBundle, and we don't
2823  // have to do anything here to lower funclet bundles.
2825  {LLVMContext::OB_deopt, LLVMContext::OB_funclet}) &&
2826  "Cannot lower callbrs with arbitrary operand bundles yet!");
2827 
2828  assert(isa<InlineAsm>(I.getCalledValue()) &&
2829  "Only know how to handle inlineasm callbr");
2830  visitInlineAsm(&I);
2831 
2832  // Retrieve successors.
2833  MachineBasicBlock *Return = FuncInfo.MBBMap[I.getDefaultDest()];
2834 
2835  // Update successor info.
2836  addSuccessorWithProb(CallBrMBB, Return);
2837  for (unsigned i = 0, e = I.getNumIndirectDests(); i < e; ++i) {
2838  MachineBasicBlock *Target = FuncInfo.MBBMap[I.getIndirectDest(i)];
2839  addSuccessorWithProb(CallBrMBB, Target);
2840  }
2841  CallBrMBB->normalizeSuccProbs();
2842 
2843  // Drop into default successor.
2844  DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(),
2845  MVT::Other, getControlRoot(),
2846  DAG.getBasicBlock(Return)));
2847 }
2848 
2849 void SelectionDAGBuilder::visitResume(const ResumeInst &RI) {
2850  llvm_unreachable("SelectionDAGBuilder shouldn't visit resume instructions!");
2851 }
2852 
2853 void SelectionDAGBuilder::visitLandingPad(const LandingPadInst &LP) {
2854  assert(FuncInfo.MBB->isEHPad() &&
2855  "Call to landingpad not in landing pad!");
2856 
2857  // If there aren't registers to copy the values into (e.g., during SjLj
2858  // exceptions), then don't bother to create these DAG nodes.
2859  const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2860  const Constant *PersonalityFn = FuncInfo.Fn->getPersonalityFn();
2861  if (TLI.getExceptionPointerRegister(PersonalityFn) == 0 &&
2862  TLI.getExceptionSelectorRegister(PersonalityFn) == 0)
2863  return;
2864 
2865  // If landingpad's return type is token type, we don't create DAG nodes
2866  // for its exception pointer and selector value. The extraction of exception
2867  // pointer or selector value from token type landingpads is not currently
2868  // supported.
2869  if (LP.getType()->isTokenTy())
2870  return;
2871 
2873  SDLoc dl = getCurSDLoc();
2874  ComputeValueVTs(TLI, DAG.getDataLayout(), LP.getType(), ValueVTs);
2875  assert(ValueVTs.size() == 2 && "Only two-valued landingpads are supported");
2876 
2877  // Get the two live-in registers as SDValues. The physregs have already been
2878  // copied into virtual registers.
2879  SDValue Ops[2];
2880  if (FuncInfo.ExceptionPointerVirtReg) {
2881  Ops[0] = DAG.getZExtOrTrunc(
2882  DAG.getCopyFromReg(DAG.getEntryNode(), dl,
2883  FuncInfo.ExceptionPointerVirtReg,
2884  TLI.getPointerTy(DAG.getDataLayout())),
2885  dl, ValueVTs[0]);
2886  } else {
2887  Ops[0] = DAG.getConstant(0, dl, TLI.getPointerTy(DAG.getDataLayout()));
2888  }
2889  Ops[1] = DAG.getZExtOrTrunc(
2890  DAG.getCopyFromReg(DAG.getEntryNode(), dl,
2891  FuncInfo.ExceptionSelectorVirtReg,
2892  TLI.getPointerTy(DAG.getDataLayout())),
2893  dl, ValueVTs[1]);
2894 
2895  // Merge into one.
2896  SDValue Res = DAG.getNode(ISD::MERGE_VALUES, dl,
2897  DAG.getVTList(ValueVTs), Ops);
2898  setValue(&LP, Res);
2899 }
2900 
2902  MachineBasicBlock *Last) {
2903  // Update JTCases.
2904  for (unsigned i = 0, e = SL->JTCases.size(); i != e; ++i)
2905  if (SL->JTCases[i].first.HeaderBB == First)
2906  SL->JTCases[i].first.HeaderBB = Last;
2907 
2908  // Update BitTestCases.
2909  for (unsigned i = 0, e = SL->BitTestCases.size(); i != e; ++i)
2910  if (SL->BitTestCases[i].Parent == First)
2911  SL->BitTestCases[i].Parent = Last;
2912 }
2913 
2914 void SelectionDAGBuilder::visitIndirectBr(const IndirectBrInst &I) {
2915  MachineBasicBlock *IndirectBrMBB = FuncInfo.MBB;
2916 
2917  // Update machine-CFG edges with unique successors.
2919  for (unsigned i = 0, e = I.getNumSuccessors(); i != e; ++i) {
2920  BasicBlock *BB = I.getSuccessor(i);
2921  bool Inserted = Done.insert(BB).second;
2922  if (!Inserted)
2923  continue;
2924 
2925  MachineBasicBlock *Succ = FuncInfo.MBBMap[BB];
2926  addSuccessorWithProb(IndirectBrMBB, Succ);
2927  }
2928  IndirectBrMBB->normalizeSuccProbs();
2929 
2930  DAG.setRoot(DAG.getNode(ISD::BRIND, getCurSDLoc(),
2931  MVT::Other, getControlRoot(),
2932  getValue(I.getAddress())));
2933 }
2934 
2935 void SelectionDAGBuilder::visitUnreachable(const UnreachableInst &I) {
2936  if (!DAG.getTarget().Options.TrapUnreachable)
2937  return;
2938 
2939  // We may be able to ignore unreachable behind a noreturn call.
2941  const BasicBlock &BB = *I.getParent();
2942  if (&I != &BB.front()) {
2944  std::prev(BasicBlock::const_iterator(&I));
2945  if (const CallInst *Call = dyn_cast<CallInst>(&*PredI)) {
2946  if (Call->doesNotReturn())
2947  return;
2948  }
2949  }
2950  }
2951 
2952  DAG.setRoot(DAG.getNode(ISD::TRAP, getCurSDLoc(), MVT::Other, DAG.getRoot()));
2953 }
2954 
2955 void SelectionDAGBuilder::visitFSub(const User &I) {
2956  // -0.0 - X --> fneg
2957  Type *Ty = I.getType();
2958  if (isa<Constant>(I.getOperand(0)) &&
2960  SDValue Op2 = getValue(I.getOperand(1));
2961  setValue(&I, DAG.getNode(ISD::FNEG, getCurSDLoc(),
2962  Op2.getValueType(), Op2));
2963  return;
2964  }
2965 
2966  visitBinary(I, ISD::FSUB);
2967 }
2968 
2969 /// Checks if the given instruction performs a vector reduction, in which case
2970 /// we have the freedom to alter the elements in the result as long as the
2971 /// reduction of them stays unchanged.
2972 static bool isVectorReductionOp(const User *I) {
2973  const Instruction *Inst = dyn_cast<Instruction>(I);
2974  if (!Inst || !Inst->getType()->isVectorTy())
2975  return false;
2976 
2977  auto OpCode = Inst->getOpcode();
2978  switch (OpCode) {
2979  case Instruction::Add:
2980  case Instruction::Mul:
2981  case Instruction::And:
2982  case Instruction::Or:
2983  case Instruction::Xor:
2984  break;
2985  case Instruction::FAdd:
2986  case Instruction::FMul:
2987  if (const FPMathOperator *FPOp = dyn_cast<const FPMathOperator>(Inst))
2988  if (FPOp->getFastMathFlags().isFast())
2989  break;
2991  default:
2992  return false;
2993  }
2994 
2995  unsigned ElemNum = Inst->getType()->getVectorNumElements();
2996  // Ensure the reduction size is a power of 2.
2997  if (!isPowerOf2_32(ElemNum))
2998  return false;
2999 
3000  unsigned ElemNumToReduce = ElemNum;
3001 
3002  // Do DFS search on the def-use chain from the given instruction. We only
3003  // allow four kinds of operations during the search until we reach the
3004  // instruction that extracts the first element from the vector:
3005  //
3006  // 1. The reduction operation of the same opcode as the given instruction.
3007  //
3008  // 2. PHI node.
3009  //
3010  // 3. ShuffleVector instruction together with a reduction operation that
3011  // does a partial reduction.
3012  //
3013  // 4. ExtractElement that extracts the first element from the vector, and we
3014  // stop searching the def-use chain here.
3015  //
3016  // 3 & 4 above perform a reduction on all elements of the vector. We push defs
3017  // from 1-3 to the stack to continue the DFS. The given instruction is not
3018  // a reduction operation if we meet any other instructions other than those
3019  // listed above.
3020 
3021  SmallVector<const User *, 16> UsersToVisit{Inst};
3023  bool ReduxExtracted = false;
3024 
3025  while (!UsersToVisit.empty()) {
3026  auto User = UsersToVisit.back();
3027  UsersToVisit.pop_back();
3028  if (!Visited.insert(User).second)
3029  continue;
3030 
3031  for (const auto &U : User->users()) {
3032  auto Inst = dyn_cast<Instruction>(U);
3033  if (!Inst)
3034  return false;
3035 
3036  if (Inst->getOpcode() == OpCode || isa<PHINode>(U)) {
3037  if (const FPMathOperator *FPOp = dyn_cast<const FPMathOperator>(Inst))
3038  if (!isa<PHINode>(FPOp) && !FPOp->getFastMathFlags().isFast())
3039  return false;
3040  UsersToVisit.push_back(U);
3041  } else if (const ShuffleVectorInst *ShufInst =
3042  dyn_cast<ShuffleVectorInst>(U)) {
3043  // Detect the following pattern: A ShuffleVector instruction together
3044  // with a reduction that do partial reduction on the first and second
3045  // ElemNumToReduce / 2 elements, and store the result in
3046  // ElemNumToReduce / 2 elements in another vector.
3047 
3048  unsigned ResultElements = ShufInst->getType()->getVectorNumElements();
3049  if (ResultElements < ElemNum)
3050  return false;
3051 
3052  if (ElemNumToReduce == 1)
3053  return false;
3054  if (!isa<UndefValue>(U->getOperand(1)))
3055  return false;
3056  for (unsigned i = 0; i < ElemNumToReduce / 2; ++i)
3057  if (ShufInst->getMaskValue(i) != int(i + ElemNumToReduce / 2))
3058  return false;
3059  for (unsigned i = ElemNumToReduce / 2; i < ElemNum; ++i)
3060  if (ShufInst->getMaskValue(i) != -1)
3061  return false;
3062 
3063  // There is only one user of this ShuffleVector instruction, which
3064  // must be a reduction operation.
3065  if (!U->hasOneUse())
3066  return false;
3067 
3068  auto U2 = dyn_cast<Instruction>(*U->user_begin());
3069  if (!U2 || U2->getOpcode() != OpCode)
3070  return false;
3071 
3072  // Check operands of the reduction operation.
3073  if ((U2->getOperand(0) == U->getOperand(0) && U2->getOperand(1) == U) ||
3074  (U2->getOperand(1) == U->getOperand(0) && U2->getOperand(0) == U)) {
3075  UsersToVisit.push_back(U2);
3076  ElemNumToReduce /= 2;
3077  } else
3078  return false;
3079  } else if (isa<ExtractElementInst>(U)) {
3080  // At this moment we should have reduced all elements in the vector.
3081  if (ElemNumToReduce != 1)
3082  return false;
3083 
3084  const ConstantInt *Val = dyn_cast<ConstantInt>(U->getOperand(1));
3085  if (!Val || !Val->isZero())
3086  return false;
3087 
3088  ReduxExtracted = true;
3089  } else
3090  return false;
3091  }
3092  }
3093  return ReduxExtracted;
3094 }
3095 
3096 void SelectionDAGBuilder::visitUnary(const User &I, unsigned Opcode) {
3097  SDNodeFlags Flags;
3098 
3099  SDValue Op = getValue(I.getOperand(0));
3100  SDValue UnNodeValue = DAG.getNode(Opcode, getCurSDLoc(), Op.getValueType(),
3101  Op, Flags);
3102  setValue(&I, UnNodeValue);
3103 }
3104 
3105 void SelectionDAGBuilder::visitBinary(const User &I, unsigned Opcode) {
3106  SDNodeFlags Flags;
3107  if (auto *OFBinOp = dyn_cast<OverflowingBinaryOperator>(&I)) {
3108  Flags.setNoSignedWrap(OFBinOp->hasNoSignedWrap());
3109  Flags.setNoUnsignedWrap(OFBinOp->hasNoUnsignedWrap());
3110  }
3111  if (auto *ExactOp = dyn_cast<PossiblyExactOperator>(&I)) {
3112  Flags.setExact(ExactOp->isExact());
3113  }
3114  if (isVectorReductionOp(&I)) {
3115  Flags.setVectorReduction(true);
3116  LLVM_DEBUG(dbgs() << "Detected a reduction operation:" << I << "\n");
3117  }
3118 
3119  SDValue Op1 = getValue(I.getOperand(0));
3120  SDValue Op2 = getValue(I.getOperand(1));
3121  SDValue BinNodeValue = DAG.getNode(Opcode, getCurSDLoc(), Op1.getValueType(),
3122  Op1, Op2, Flags);
3123  setValue(&I, BinNodeValue);
3124 }
3125 
3126 void SelectionDAGBuilder::visitShift(const User &I, unsigned Opcode) {
3127  SDValue Op1 = getValue(I.getOperand(0));
3128  SDValue Op2 = getValue(I.getOperand(1));
3129 
3130  EVT ShiftTy = DAG.getTargetLoweringInfo().getShiftAmountTy(
3131  Op1.getValueType(), DAG.getDataLayout());
3132 
3133  // Coerce the shift amount to the right type if we can.
3134  if (!I.getType()->isVectorTy() && Op2.getValueType() != ShiftTy) {
3135  unsigned ShiftSize = ShiftTy.getSizeInBits();
3136  unsigned Op2Size = Op2.getValueSizeInBits();
3137  SDLoc DL = getCurSDLoc();
3138 
3139  // If the operand is smaller than the shift count type, promote it.
3140  if (ShiftSize > Op2Size)
3141  Op2 = DAG.getNode(ISD::ZERO_EXTEND, DL, ShiftTy, Op2);
3142 
3143  // If the operand is larger than the shift count type but the shift
3144  // count type has enough bits to represent any shift value, truncate
3145  // it now. This is a common case and it exposes the truncate to
3146  // optimization early.
3147  else if (ShiftSize >= Log2_32_Ceil(Op2.getValueSizeInBits()))
3148  Op2 = DAG.getNode(ISD::TRUNCATE, DL, ShiftTy, Op2);
3149  // Otherwise we'll need to temporarily settle for some other convenient
3150  // type. Type legalization will make adjustments once the shiftee is split.
3151  else
3152  Op2 = DAG.getZExtOrTrunc(Op2, DL, MVT::i32);
3153  }
3154 
3155  bool nuw = false;
3156  bool nsw = false;
3157  bool exact = false;
3158 
3159  if (Opcode == ISD::SRL || Opcode == ISD::SRA || Opcode == ISD::SHL) {
3160 
3161  if (const OverflowingBinaryOperator *OFBinOp =
3162  dyn_cast<const OverflowingBinaryOperator>(&I)) {
3163  nuw = OFBinOp->hasNoUnsignedWrap();
3164  nsw = OFBinOp->hasNoSignedWrap();
3165  }
3166  if (const PossiblyExactOperator *ExactOp =
3167  dyn_cast<const PossiblyExactOperator>(&I))
3168  exact = ExactOp->isExact();
3169  }
3170  SDNodeFlags Flags;
3171  Flags.setExact(exact);
3172  Flags.setNoSignedWrap(nsw);
3173  Flags.setNoUnsignedWrap(nuw);
3174  SDValue Res = DAG.getNode(Opcode, getCurSDLoc(), Op1.getValueType(), Op1, Op2,
3175  Flags);
3176  setValue(&I, Res);
3177 }
3178 
3179 void SelectionDAGBuilder::visitSDiv(const User &I) {
3180  SDValue Op1 = getValue(I.getOperand(0));
3181  SDValue Op2 = getValue(I.getOperand(1));
3182 
3183  SDNodeFlags Flags;
3184  Flags.setExact(isa<PossiblyExactOperator>(&I) &&
3185  cast<PossiblyExactOperator>(&I)->isExact());
3186  setValue(&I, DAG.getNode(ISD::SDIV, getCurSDLoc(), Op1.getValueType(), Op1,
3187  Op2, Flags));
3188 }
3189 
3190 void SelectionDAGBuilder::visitICmp(const User &I) {
3192  if (const ICmpInst *IC = dyn_cast<ICmpInst>(&I))
3193  predicate = IC->getPredicate();
3194  else if (const ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
3195  predicate = ICmpInst::Predicate(IC->getPredicate());
3196  SDValue Op1 = getValue(I.getOperand(0));
3197  SDValue Op2 = getValue(I.getOperand(1));
3198  ISD::CondCode Opcode = getICmpCondCode(predicate);
3199 
3200  auto &TLI = DAG.getTargetLoweringInfo();
3201  EVT MemVT =
3202  TLI.getMemValueType(DAG.getDataLayout(), I.getOperand(0)->getType());
3203 
3204  // If a pointer's DAG type is larger than its memory type then the DAG values
3205  // are zero-extended. This breaks signed comparisons so truncate back to the
3206  // underlying type before doing the compare.
3207  if (Op1.getValueType() != MemVT) {
3208  Op1 = DAG.getPtrExtOrTrunc(Op1, getCurSDLoc(), MemVT);
3209  Op2 = DAG.getPtrExtOrTrunc(Op2, getCurSDLoc(), MemVT);
3210  }
3211 
3212  EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
3213  I.getType());
3214  setValue(&I, DAG.getSetCC(getCurSDLoc(), DestVT, Op1, Op2, Opcode));
3215 }
3216 
3217 void SelectionDAGBuilder::visitFCmp(const User &I) {
3219  if (const FCmpInst *FC = dyn_cast<FCmpInst>(&I))
3220  predicate = FC->getPredicate();
3221  else if (const ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
3222  predicate = FCmpInst::Predicate(FC->getPredicate());
3223  SDValue Op1 = getValue(I.getOperand(0));
3224  SDValue Op2 = getValue(I.getOperand(1));
3225 
3226  ISD::CondCode Condition = getFCmpCondCode(predicate);
3227  auto *FPMO = dyn_cast<FPMathOperator>(&I);
3228  if ((FPMO && FPMO->hasNoNaNs()) || TM.Options.NoNaNsFPMath)
3229  Condition = getFCmpCodeWithoutNaN(Condition);
3230 
3231  EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
3232  I.getType());
3233  setValue(&I, DAG.getSetCC(getCurSDLoc(), DestVT, Op1, Op2, Condition));
3234 }
3235 
3236 // Check if the condition of the select has one use or two users that are both
3237 // selects with the same condition.
3238 static bool hasOnlySelectUsers(const Value *Cond) {
3239  return llvm::all_of(Cond->users(), [](const Value *V) {
3240  return isa<SelectInst>(V);
3241  });
3242 }
3243 
3244 void SelectionDAGBuilder::visitSelect(const User &I) {
3247  ValueVTs);
3248  unsigned NumValues = ValueVTs.size();
3249  if (NumValues == 0) return;
3250 
3251  SmallVector<SDValue, 4> Values(NumValues);
3252  SDValue Cond = getValue(I.getOperand(0));
3253  SDValue LHSVal = getValue(I.getOperand(1));
3254  SDValue RHSVal = getValue(I.getOperand(2));
3255  auto BaseOps = {Cond};
3256  ISD::NodeType OpCode = Cond.getValueType().isVector() ?
3258 
3259  bool IsUnaryAbs = false;
3260 
3261  // Min/max matching is only viable if all output VTs are the same.
3262  if (is_splat(ValueVTs)) {
3263  EVT VT = ValueVTs[0];
3264  LLVMContext &Ctx = *DAG.getContext();
3265  auto &TLI = DAG.getTargetLoweringInfo();
3266 
3267  // We care about the legality of the operation after it has been type
3268  // legalized.
3269  while (TLI.getTypeAction(Ctx, VT) != TargetLoweringBase::TypeLegal &&
3270  VT != TLI.getTypeToTransformTo(Ctx, VT))
3271  VT = TLI.getTypeToTransformTo(Ctx, VT);
3272 
3273  // If the vselect is legal, assume we want to leave this as a vector setcc +
3274  // vselect. Otherwise, if this is going to be scalarized, we want to see if
3275  // min/max is legal on the scalar type.
3276  bool UseScalarMinMax = VT.isVector() &&
3277  !TLI.isOperationLegalOrCustom(ISD::VSELECT, VT);
3278 
3279  Value *LHS, *RHS;
3280  auto SPR = matchSelectPattern(const_cast<User*>(&I), LHS, RHS);
3282  switch (SPR.Flavor) {
3283  case SPF_UMAX: Opc = ISD::UMAX; break;
3284  case SPF_UMIN: Opc = ISD::UMIN; break;
3285  case SPF_SMAX: Opc = ISD::SMAX; break;
3286  case SPF_SMIN: Opc = ISD::SMIN; break;
3287  case SPF_FMINNUM:
3288  switch (SPR.NaNBehavior) {
3289  case SPNB_NA: llvm_unreachable("No NaN behavior for FP op?");
3290  case SPNB_RETURNS_NAN: Opc = ISD::FMINIMUM; break;
3291  case SPNB_RETURNS_OTHER: Opc = ISD::FMINNUM; break;
3292  case SPNB_RETURNS_ANY: {
3293  if (TLI.isOperationLegalOrCustom(ISD::FMINNUM, VT))
3294  Opc = ISD::FMINNUM;
3295  else if (TLI.isOperationLegalOrCustom(ISD::FMINIMUM, VT))
3296  Opc = ISD::FMINIMUM;
3297  else if (UseScalarMinMax)
3298  Opc = TLI.isOperationLegalOrCustom(ISD::FMINNUM, VT.getScalarType()) ?
3300  break;
3301  }
3302  }
3303  break;
3304  case SPF_FMAXNUM:
3305  switch (SPR.NaNBehavior) {
3306  case SPNB_NA: llvm_unreachable("No NaN behavior for FP op?");
3307  case SPNB_RETURNS_NAN: Opc = ISD::FMAXIMUM; break;
3308  case SPNB_RETURNS_OTHER: Opc = ISD::FMAXNUM; break;
3309  case SPNB_RETURNS_ANY:
3310 
3311  if (TLI.isOperationLegalOrCustom(ISD::FMAXNUM, VT))
3312  Opc = ISD::FMAXNUM;
3313  else if (TLI.isOperationLegalOrCustom(ISD::FMAXIMUM, VT))
3314  Opc = ISD::FMAXIMUM;
3315  else if (UseScalarMinMax)
3316  Opc = TLI.isOperationLegalOrCustom(ISD::FMAXNUM, VT.getScalarType()) ?
3318  break;
3319  }
3320  break;
3321  case SPF_ABS:
3322  IsUnaryAbs = true;
3323  Opc = ISD::ABS;
3324  break;
3325  case SPF_NABS:
3326  // TODO: we need to produce sub(0, abs(X)).
3327  default: break;
3328  }
3329 
3330  if (!IsUnaryAbs && Opc != ISD::DELETED_NODE &&
3331  (TLI.isOperationLegalOrCustom(Opc, VT) ||
3332  (UseScalarMinMax &&
3333  TLI.isOperationLegalOrCustom(Opc, VT.getScalarType()))) &&
3334  // If the underlying comparison instruction is used by any other
3335  // instruction, the consumed instructions won't be destroyed, so it is
3336  // not profitable to convert to a min/max.
3337  hasOnlySelectUsers(cast<SelectInst>(I).getCondition())) {
3338  OpCode = Opc;
3339  LHSVal = getValue(LHS);
3340  RHSVal = getValue(RHS);
3341  BaseOps = {};
3342  }
3343 
3344  if (IsUnaryAbs) {
3345  OpCode = Opc;
3346  LHSVal = getValue(LHS);
3347  BaseOps = {};
3348  }
3349  }
3350 
3351  if (IsUnaryAbs) {
3352  for (unsigned i = 0; i != NumValues; ++i) {
3353  Values[i] =
3354  DAG.getNode(OpCode, getCurSDLoc(),
3355  LHSVal.getNode()->getValueType(LHSVal.getResNo() + i),
3356  SDValue(LHSVal.getNode(), LHSVal.getResNo() + i));
3357  }
3358  } else {
3359  for (unsigned i = 0; i != NumValues; ++i) {
3360  SmallVector<SDValue, 3> Ops(BaseOps.begin(), BaseOps.end());
3361  Ops.push_back(SDValue(LHSVal.getNode(), LHSVal.getResNo() + i));
3362  Ops.push_back(SDValue(RHSVal.getNode(), RHSVal.getResNo() + i));
3363  Values[i] = DAG.getNode(
3364  OpCode, getCurSDLoc(),
3365  LHSVal.getNode()->getValueType(LHSVal.getResNo() + i), Ops);
3366  }
3367  }
3368 
3369  setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
3370  DAG.getVTList(ValueVTs), Values));
3371 }
3372 
3373 void SelectionDAGBuilder::visitTrunc(const User &I) {
3374  // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest).
3375  SDValue N = getValue(I.getOperand(0));
3376  EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
3377  I.getType());
3378  setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), DestVT, N));
3379 }
3380 
3381 void SelectionDAGBuilder::visitZExt(const User &I) {
3382  // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
3383  // ZExt also can't be a cast to bool for same reason. So, nothing much to do
3384  SDValue N = getValue(I.getOperand(0));
3385  EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
3386  I.getType());
3387  setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurSDLoc(), DestVT, N));
3388 }
3389 
3390 void SelectionDAGBuilder::visitSExt(const User &I) {
3391  // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
3392  // SExt also can't be a cast to bool for same reason. So, nothing much to do
3393  SDValue N = getValue(I.getOperand(0));
3394  EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
3395  I.getType());
3396  setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurSDLoc(), DestVT, N));
3397 }
3398 
3399 void SelectionDAGBuilder::visitFPTrunc(const User &I) {
3400  // FPTrunc is never a no-op cast, no need to check
3401  SDValue N = getValue(I.getOperand(0));
3402  SDLoc dl = getCurSDLoc();
3403  const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3404  EVT DestVT = TLI.getValueType(DAG.getDataLayout(), I.getType());
3405  setValue(&I, DAG.getNode(ISD::FP_ROUND, dl, DestVT, N,
3406  DAG.getTargetConstant(
3407  0, dl, TLI.getPointerTy(DAG.getDataLayout()))));
3408 }
3409 
3410 void SelectionDAGBuilder::visitFPExt(const User &I) {
3411  // FPExt is never a no-op cast, no need to check
3412  SDValue N = getValue(I.getOperand(0));
3413  EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
3414  I.getType());
3415  setValue(&I, DAG.getNode(ISD::FP_EXTEND, getCurSDLoc(), DestVT, N));
3416 }
3417 
3418 void SelectionDAGBuilder::visitFPToUI(const User &I) {
3419  // FPToUI is never a no-op cast, no need to check
3420  SDValue N = getValue(I.getOperand(0));
3421  EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
3422  I.getType());
3423  setValue(&I, DAG.getNode(ISD::FP_TO_UINT, getCurSDLoc(), DestVT, N));
3424 }
3425 
3426 void SelectionDAGBuilder::visitFPToSI(const User &I) {
3427  // FPToSI is never a no-op cast, no need to check
3428  SDValue N = getValue(I.getOperand(0));
3429  EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
3430  I.getType());
3431  setValue(&I, DAG.getNode(ISD::FP_TO_SINT, getCurSDLoc(), DestVT, N));
3432 }
3433 
3434 void SelectionDAGBuilder::visitUIToFP(const User &I) {
3435  // UIToFP is never a no-op cast, no need to check
3436  SDValue N = getValue(I.getOperand(0));
3437  EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
3438  I.getType());
3439  setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurSDLoc(), DestVT, N));
3440 }
3441 
3442 void SelectionDAGBuilder::visitSIToFP(const User &I) {
3443  // SIToFP is never a no-op cast, no need to check
3444  SDValue N = getValue(I.getOperand(0));
3445  EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
3446  I.getType());
3447  setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurSDLoc(), DestVT, N));
3448 }
3449 
3450 void SelectionDAGBuilder::visitPtrToInt(const User &I) {
3451  // What to do depends on the size of the integer and the size of the pointer.
3452  // We can either truncate, zero extend, or no-op, accordingly.
3453  SDValue N = getValue(I.getOperand(0));
3454  auto &TLI = DAG.getTargetLoweringInfo();
3455  EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
3456  I.getType());
3457  EVT PtrMemVT =
3458  TLI.getMemValueType(DAG.getDataLayout(), I.getOperand(0)->getType());
3459  N = DAG.getPtrExtOrTrunc(N, getCurSDLoc(), PtrMemVT);
3460  N = DAG.getZExtOrTrunc(N, getCurSDLoc(), DestVT);
3461  setValue(&I, N);
3462 }
3463 
3464 void SelectionDAGBuilder::visitIntToPtr(const User &I) {
3465  // What to do depends on the size of the integer and the size of the pointer.
3466  // We can either truncate, zero extend, or no-op, accordingly.
3467  SDValue N = getValue(I.getOperand(0));
3468  auto &TLI = DAG.getTargetLoweringInfo();
3469  EVT DestVT = TLI.getValueType(DAG.getDataLayout(), I.getType());
3470  EVT PtrMemVT = TLI.getMemValueType(DAG.getDataLayout(), I.getType());
3471  N = DAG.getZExtOrTrunc(N, getCurSDLoc(), PtrMemVT);
3472  N = DAG.getPtrExtOrTrunc(N, getCurSDLoc(), DestVT);
3473  setValue(&I, N);
3474 }
3475 
3476 void SelectionDAGBuilder::visitBitCast(const User &I) {
3477  SDValue N = getValue(I.getOperand(0));
3478  SDLoc dl = getCurSDLoc();
3479  EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
3480  I.getType());
3481 
3482  // BitCast assures us that source and destination are the same size so this is
3483  // either a BITCAST or a no-op.
3484  if (DestVT != N.getValueType())
3485  setValue(&I, DAG.getNode(ISD::BITCAST, dl,
3486  DestVT, N)); // convert types.
3487  // Check if the original LLVM IR Operand was a ConstantInt, because getValue()
3488  // might fold any kind of constant expression to an integer constant and that
3489  // is not what we are looking for. Only recognize a bitcast of a genuine
3490  // constant integer as an opaque constant.
3491  else if(ConstantInt *C = dyn_cast<ConstantInt>(I.getOperand(0)))
3492  setValue(&I, DAG.getConstant(C->getValue(), dl, DestVT, /*isTarget=*/false,
3493  /*isOpaque*/true));
3494  else
3495  setValue(&I, N); // noop cast.
3496 }
3497 
3498 void SelectionDAGBuilder::visitAddrSpaceCast(const User &I) {
3499  const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3500  const Value *SV = I.getOperand(0);
3501  SDValue N = getValue(SV);
3502  EVT DestVT = TLI.getValueType(DAG.getDataLayout(), I.getType());
3503 
3504  unsigned SrcAS = SV->getType()->getPointerAddressSpace();
3505  unsigned DestAS = I.getType()->getPointerAddressSpace();
3506 
3507  if (!TLI.isNoopAddrSpaceCast(SrcAS, DestAS))
3508  N = DAG.getAddrSpaceCast(getCurSDLoc(), DestVT, N, SrcAS, DestAS);
3509 
3510  setValue(&I, N);
3511 }
3512 
3513 void SelectionDAGBuilder::visitInsertElement(const User &I) {
3514  const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3515  SDValue InVec = getValue(I.getOperand(0));
3516  SDValue InVal = getValue(I.getOperand(1));
3517  SDValue InIdx = DAG.getSExtOrTrunc(getValue(I.getOperand(2)), getCurSDLoc(),
3518  TLI.getVectorIdxTy(DAG.getDataLayout()));
3519  setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, getCurSDLoc(),
3520  TLI.getValueType(DAG.getDataLayout(), I.getType()),
3521  InVec, InVal, InIdx));
3522 }
3523 
3524 void SelectionDAGBuilder::visitExtractElement(const User &I) {
3525  const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3526  SDValue InVec = getValue(I.getOperand(0));
3527  SDValue InIdx = DAG.getSExtOrTrunc(getValue(I.getOperand(1)), getCurSDLoc(),
3528  TLI.getVectorIdxTy(DAG.getDataLayout()));
3529  setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurSDLoc(),
3530  TLI.getValueType(DAG.getDataLayout(), I.getType()),
3531  InVec, InIdx));
3532 }
3533 
3534 void SelectionDAGBuilder::visitShuffleVector(const User &I) {
3535  SDValue Src1 = getValue(I.getOperand(0));
3536  SDValue Src2 = getValue(I.getOperand(1));
3537  SDLoc DL = getCurSDLoc();
3538 
3540  ShuffleVectorInst::getShuffleMask(cast<Constant>(I.getOperand(2)), Mask);
3541  unsigned MaskNumElts = Mask.size();
3542 
3543  const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3544  EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
3545  EVT SrcVT = Src1.getValueType();
3546  unsigned SrcNumElts = SrcVT.getVectorNumElements();
3547 
3548  if (SrcNumElts == MaskNumElts) {
3549  setValue(&I, DAG.getVectorShuffle(VT, DL, Src1, Src2, Mask));
3550  return;
3551  }
3552 
3553  // Normalize the shuffle vector since mask and vector length don't match.
3554  if (SrcNumElts < MaskNumElts) {
3555  // Mask is longer than the source vectors. We can use concatenate vector to
3556  // make the mask and vectors lengths match.
3557 
3558  if (MaskNumElts % SrcNumElts == 0) {
3559  // Mask length is a multiple of the source vector length.
3560  // Check if the shuffle is some kind of concatenation of the input
3561  // vectors.
3562  unsigned NumConcat = MaskNumElts / SrcNumElts;
3563  bool IsConcat = true;
3564  SmallVector<int, 8> ConcatSrcs(NumConcat, -1);
3565  for (unsigned i = 0; i != MaskNumElts; ++i) {
3566  int Idx = Mask[i];
3567  if (Idx < 0)
3568  continue;
3569  // Ensure the indices in each SrcVT sized piece are sequential and that
3570  // the same source is used for the whole piece.
3571  if ((Idx % SrcNumElts != (i % SrcNumElts)) ||
3572  (ConcatSrcs[i / SrcNumElts] >= 0 &&
3573  ConcatSrcs[i / SrcNumElts] != (int)(Idx / SrcNumElts))) {
3574  IsConcat = false;
3575  break;
3576  }
3577  // Remember which source this index came from.
3578  ConcatSrcs[i / SrcNumElts] = Idx / SrcNumElts;
3579  }
3580 
3581  // The shuffle is concatenating multiple vectors together. Just emit
3582  // a CONCAT_VECTORS operation.
3583  if (IsConcat) {
3584  SmallVector<SDValue, 8> ConcatOps;
3585  for (auto Src : ConcatSrcs) {
3586  if (Src < 0)
3587  ConcatOps.push_back(DAG.getUNDEF(SrcVT));
3588  else if (Src == 0)
3589  ConcatOps.push_back(Src1);
3590  else
3591  ConcatOps.push_back(Src2);
3592  }
3593  setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, ConcatOps));
3594  return;
3595  }
3596  }
3597 
3598  unsigned PaddedMaskNumElts = alignTo(MaskNumElts, SrcNumElts);
3599  unsigned NumConcat = PaddedMaskNumElts / SrcNumElts;
3600  EVT PaddedVT = EVT::getVectorVT(*DAG.getContext(), VT.getScalarType(),
3601  PaddedMaskNumElts);
3602 
3603  // Pad both vectors with undefs to make them the same length as the mask.
3604  SDValue UndefVal = DAG.getUNDEF(SrcVT);
3605 
3606  SmallVector<SDValue, 8> MOps1(NumConcat, UndefVal);
3607  SmallVector<SDValue, 8> MOps2(NumConcat, UndefVal);
3608  MOps1[0] = Src1;
3609  MOps2[0] = Src2;
3610 
3611  Src1 = DAG.getNode(ISD::CONCAT_VECTORS, DL, PaddedVT, MOps1);
3612  Src2 = DAG.getNode(ISD::CONCAT_VECTORS, DL, PaddedVT, MOps2);
3613 
3614  // Readjust mask for new input vector length.
3615  SmallVector<int, 8> MappedOps(PaddedMaskNumElts, -1);
3616  for (unsigned i = 0; i != MaskNumElts; ++i) {
3617  int Idx = Mask[i];
3618  if (Idx >= (int)SrcNumElts)
3619  Idx -= SrcNumElts - PaddedMaskNumElts;
3620  MappedOps[i] = Idx;
3621  }
3622 
3623  SDValue Result = DAG.getVectorShuffle(PaddedVT, DL, Src1, Src2, MappedOps);
3624 
3625  // If the concatenated vector was padded, extract a subvector with the
3626  // correct number of elements.
3627  if (MaskNumElts != PaddedMaskNumElts)
3628  Result = DAG.getNode(
3629  ISD::EXTRACT_SUBVECTOR, DL, VT, Result,
3630  DAG.getConstant(0, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
3631 
3632  setValue(&I, Result);
3633  return;
3634  }
3635 
3636  if (SrcNumElts > MaskNumElts) {
3637  // Analyze the access pattern of the vector to see if we can extract
3638  // two subvectors and do the shuffle.
3639  int StartIdx[2] = { -1, -1 }; // StartIdx to extract from
3640  bool CanExtract = true;
3641  for (int Idx : Mask) {
3642  unsigned Input = 0;
3643  if (Idx < 0)
3644  continue;
3645 
3646  if (Idx >= (int)SrcNumElts) {
3647  Input = 1;
3648  Idx -= SrcNumElts;
3649  }
3650 
3651  // If all the indices come from the same MaskNumElts sized portion of
3652  // the sources we can use extract. Also make sure the extract wouldn't
3653  // extract past the end of the source.
3654  int NewStartIdx = alignDown(Idx, MaskNumElts);
3655  if (NewStartIdx + MaskNumElts > SrcNumElts ||
3656  (StartIdx[Input] >= 0 && StartIdx[Input] != NewStartIdx))
3657  CanExtract = false;
3658  // Make sure we always update StartIdx as we use it to track if all
3659  // elements are undef.
3660  StartIdx[Input] = NewStartIdx;
3661  }
3662 
3663  if (StartIdx[0] < 0 && StartIdx[1] < 0) {
3664  setValue(&I, DAG.getUNDEF(VT)); // Vectors are not used.
3665  return;
3666  }
3667  if (CanExtract) {
3668  // Extract appropriate subvector and generate a vector shuffle
3669  for (unsigned Input = 0; Input < 2; ++Input) {
3670  SDValue &Src = Input == 0 ? Src1 : Src2;
3671  if (StartIdx[Input] < 0)
3672  Src = DAG.getUNDEF(VT);
3673  else {
3674  Src = DAG.getNode(
3675  ISD::EXTRACT_SUBVECTOR, DL, VT, Src,
3676  DAG.getConstant(StartIdx[Input], DL,
3677  TLI.getVectorIdxTy(DAG.getDataLayout())));
3678  }
3679  }
3680 
3681  // Calculate new mask.
3682  SmallVector<int, 8> MappedOps(Mask.begin(), Mask.end());
3683  for (int &Idx : MappedOps) {
3684  if (Idx >= (int)SrcNumElts)
3685  Idx -= SrcNumElts + StartIdx[1] - MaskNumElts;
3686  else if (Idx >= 0)
3687  Idx -= StartIdx[0];
3688  }
3689 
3690  setValue(&I, DAG.getVectorShuffle(VT, DL, Src1, Src2, MappedOps));
3691  return;
3692  }
3693  }
3694 
3695  // We can't use either concat vectors or extract subvectors so fall back to
3696  // replacing the shuffle with extract and build vector.
3697  // to insert and build vector.
3698  EVT EltVT = VT.getVectorElementType();
3699  EVT IdxVT = TLI.getVectorIdxTy(DAG.getDataLayout());
3701  for (int Idx : Mask) {
3702  SDValue Res;
3703 
3704  if (Idx < 0) {
3705  Res = DAG.getUNDEF(EltVT);
3706  } else {
3707  SDValue &Src = Idx < (int)SrcNumElts ? Src1 : Src2;
3708  if (Idx >= (int)SrcNumElts) Idx -= SrcNumElts;
3709 
3710  Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
3711  EltVT, Src, DAG.getConstant(Idx, DL, IdxVT));
3712  }
3713 
3714  Ops.push_back(Res);
3715  }
3716 
3717  setValue(&I, DAG.getBuildVector(VT, DL, Ops));
3718 }
3719 
3720 void SelectionDAGBuilder::visitInsertValue(const User &I) {
3721  ArrayRef<unsigned> Indices;
3722  if (const InsertValueInst *IV = dyn_cast<InsertValueInst>(&I))
3723  Indices = IV->getIndices();
3724  else
3725  Indices = cast<ConstantExpr>(&I)->getIndices();
3726 
3727  const Value *Op0 = I.getOperand(0);
3728  const Value *Op1 = I.getOperand(1);
3729  Type *AggTy = I.getType();
3730  Type *ValTy = Op1->getType();
3731  bool IntoUndef = isa<UndefValue>(Op0);
3732  bool FromUndef = isa<UndefValue>(Op1);
3733 
3734  unsigned LinearIndex = ComputeLinearIndex(AggTy, Indices);
3735 
3736  const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3737  SmallVector<EVT, 4> AggValueVTs;
3738  ComputeValueVTs(TLI, DAG.getDataLayout(), AggTy, AggValueVTs);
3739  SmallVector<EVT, 4> ValValueVTs;
3740  ComputeValueVTs(TLI, DAG.getDataLayout(), ValTy, ValValueVTs);
3741 
3742  unsigned NumAggValues = AggValueVTs.size();
3743  unsigned NumValValues = ValValueVTs.size();
3744  SmallVector<SDValue, 4> Values(NumAggValues);
3745 
3746  // Ignore an insertvalue that produces an empty object
3747  if (!NumAggValues) {
3748  setValue(&I, DAG.getUNDEF(MVT(MVT::Other)));
3749  return;
3750  }
3751 
3752  SDValue Agg = getValue(Op0);
3753  unsigned i = 0;
3754  // Copy the beginning value(s) from the original aggregate.
3755  for (; i != LinearIndex; ++i)
3756  Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
3757  SDValue(Agg.getNode(), Agg.getResNo() + i);
3758  // Copy values from the inserted value(s).
3759  if (NumValValues) {
3760  SDValue Val = getValue(Op1);
3761  for (; i != LinearIndex + NumValValues; ++i)
3762  Values[i] = FromUndef ? DAG.getUNDEF(AggValueVTs[i]) :
3763  SDValue(Val.getNode(), Val.getResNo() + i - LinearIndex);
3764  }
3765  // Copy remaining value(s) from the original aggregate.
3766  for (; i != NumAggValues; ++i)
3767  Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
3768  SDValue(Agg.getNode(), Agg.getResNo() + i);
3769 
3770  setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
3771  DAG.getVTList(AggValueVTs), Values));
3772 }
3773 
3774 void SelectionDAGBuilder::visitExtractValue(const User &I) {
3775  ArrayRef<unsigned> Indices;
3776  if (const ExtractValueInst *EV = dyn_cast<ExtractValueInst>(&I))
3777  Indices = EV->getIndices();
3778  else
3779  Indices = cast<ConstantExpr>(&I)->getIndices();
3780 
3781  const Value *Op0 = I.getOperand(0);
3782  Type *AggTy = Op0->getType();
3783  Type *ValTy = I.getType();
3784  bool OutOfUndef = isa<UndefValue>(Op0);
3785 
3786  unsigned LinearIndex = ComputeLinearIndex(AggTy, Indices);
3787 
3788  const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3789  SmallVector<EVT, 4> ValValueVTs;
3790  ComputeValueVTs(TLI, DAG.getDataLayout(), ValTy, ValValueVTs);
3791 
3792  unsigned NumValValues = ValValueVTs.size();
3793 
3794  // Ignore a extractvalue that produces an empty object
3795  if (!NumValValues) {
3796  setValue(&I, DAG.getUNDEF(MVT(MVT::Other)));
3797  return;
3798  }
3799 
3800  SmallVector<SDValue, 4> Values(NumValValues);
3801 
3802  SDValue Agg = getValue(Op0);
3803  // Copy out the selected value(s).
3804  for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i)
3805  Values[i - LinearIndex] =
3806  OutOfUndef ?
3807  DAG.getUNDEF(Agg.getNode()->getValueType(Agg.getResNo() + i)) :
3808  SDValue(Agg.getNode(), Agg.getResNo() + i);
3809 
3810  setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
3811  DAG.getVTList(ValValueVTs), Values));
3812 }
3813 
3814 void SelectionDAGBuilder::visitGetElementPtr(const User &I) {
3815  Value *Op0 = I.getOperand(0);
3816  // Note that the pointer operand may be a vector of pointers. Take the scalar
3817  // element which holds a pointer.
3818  unsigned AS = Op0->getType()->getScalarType()->getPointerAddressSpace();
3819  SDValue N = getValue(Op0);
3820  SDLoc dl = getCurSDLoc();
3821  auto &TLI = DAG.getTargetLoweringInfo();
3822  MVT PtrTy = TLI.getPointerTy(DAG.getDataLayout(), AS);
3823  MVT PtrMemTy = TLI.getPointerMemTy(DAG.getDataLayout(), AS);
3824 
3825  // Normalize Vector GEP - all scalar operands should be converted to the
3826  // splat vector.
3827  unsigned VectorWidth = I.getType()->isVectorTy() ?
3828  cast<VectorType>(I.getType())->getVectorNumElements() : 0;
3829 
3830  if (VectorWidth && !N.getValueType().isVector()) {
3831  LLVMContext &Context = *DAG.getContext();
3832  EVT VT = EVT::getVectorVT(Context, N.getValueType(), VectorWidth);
3833  N = DAG.getSplatBuildVector(VT, dl, N);
3834  }
3835 
3836  for (gep_type_iterator GTI = gep_type_begin(&I), E = gep_type_end(&I);
3837  GTI != E; ++GTI) {
3838  const Value *Idx = GTI.getOperand();
3839  if (StructType *StTy = GTI.getStructTypeOrNull()) {
3840  unsigned Field = cast<Constant>(Idx)->getUniqueInteger().getZExtValue();
3841  if (Field) {
3842  // N = N + Offset
3843  uint64_t Offset = DL->getStructLayout(StTy)->getElementOffset(Field);
3844 
3845  // In an inbounds GEP with an offset that is nonnegative even when
3846  // interpreted as signed, assume there is no unsigned overflow.
3847  SDNodeFlags Flags;
3848  if (int64_t(Offset) >= 0 && cast<GEPOperator>(I).isInBounds())
3849  Flags.setNoUnsignedWrap(true);
3850 
3851  N = DAG.getNode(ISD::ADD, dl, N.getValueType(), N,
3852  DAG.getConstant(Offset, dl, N.getValueType()), Flags);
3853  }
3854  } else {
3855  unsigned IdxSize = DAG.getDataLayout().getIndexSizeInBits(AS);
3856  MVT IdxTy = MVT::getIntegerVT(IdxSize);
3857  APInt ElementSize(IdxSize, DL->getTypeAllocSize(GTI.getIndexedType()));
3858 
3859  // If this is a scalar constant or a splat vector of constants,
3860  // handle it quickly.
3861  const auto *CI = dyn_cast<ConstantInt>(Idx);
3862  if (!CI && isa<ConstantDataVector>(Idx) &&
3863  cast<ConstantDataVector>(Idx)->getSplatValue())
3864  CI = cast<ConstantInt>(cast<ConstantDataVector>(Idx)->getSplatValue());
3865 
3866  if (CI) {
3867  if (CI->isZero())
3868  continue;
3869  APInt Offs = ElementSize * CI->getValue().sextOrTrunc(IdxSize);
3870  LLVMContext &Context = *DAG.getContext();
3871  SDValue OffsVal = VectorWidth ?
3872  DAG.getConstant(Offs, dl, EVT::getVectorVT(Context, IdxTy, VectorWidth)) :
3873  DAG.getConstant(Offs, dl, IdxTy);
3874 
3875  // In an inbouds GEP with an offset that is nonnegative even when
3876  // interpreted as signed, assume there is no unsigned overflow.
3877  SDNodeFlags Flags;
3878  if (Offs.isNonNegative() && cast<GEPOperator>(I).isInBounds())
3879  Flags.setNoUnsignedWrap(true);
3880 
3881  OffsVal = DAG.getSExtOrTrunc(OffsVal, dl, N.getValueType());
3882 
3883  N = DAG.getNode(ISD::ADD, dl, N.getValueType(), N, OffsVal, Flags);
3884  continue;
3885  }
3886 
3887  // N = N + Idx * ElementSize;
3888  SDValue IdxN = getValue(Idx);
3889 
3890  if (!IdxN.getValueType().isVector() && VectorWidth) {
3891  EVT VT = EVT::getVectorVT(*Context, IdxN.getValueType(), VectorWidth);
3892  IdxN = DAG.getSplatBuildVector(VT, dl, IdxN);
3893  }
3894 
3895  // If the index is smaller or larger than intptr_t, truncate or extend
3896  // it.
3897  IdxN = DAG.getSExtOrTrunc(IdxN, dl, N.getValueType());
3898 
3899  // If this is a multiply by a power of two, turn it into a shl
3900  // immediately. This is a very common case.
3901  if (ElementSize != 1) {
3902  if (ElementSize.isPowerOf2()) {
3903  unsigned Amt = ElementSize.logBase2();
3904  IdxN = DAG.getNode(ISD::SHL, dl,
3905  N.getValueType(), IdxN,
3906  DAG.getConstant(Amt, dl, IdxN.getValueType()));
3907  } else {
3908  SDValue Scale = DAG.getConstant(ElementSize.getZExtValue(), dl,
3909  IdxN.getValueType());
3910  IdxN = DAG.getNode(ISD::MUL, dl,
3911  N.getValueType(), IdxN, Scale);
3912  }
3913  }
3914 
3915  N = DAG.getNode(ISD::ADD, dl,
3916  N.getValueType(), N, IdxN);
3917  }
3918  }
3919 
3920  if (PtrMemTy != PtrTy && !cast<GEPOperator>(I).isInBounds())
3921  N = DAG.getPtrExtendInReg(N, dl, PtrMemTy);
3922 
3923  setValue(&I, N);
3924 }
3925 
3926 void SelectionDAGBuilder::visitAlloca(const AllocaInst &I) {
3927  // If this is a fixed sized alloca in the entry block of the function,
3928  // allocate it statically on the stack.
3929  if (FuncInfo.StaticAllocaMap.count(&I))
3930  return; // getValue will auto-populate this.
3931 
3932  SDLoc dl = getCurSDLoc();
3933  Type *Ty = I.getAllocatedType();
3934  const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3935  auto &DL = DAG.getDataLayout();
3936  uint64_t TySize = DL.getTypeAllocSize(Ty);
3937  unsigned Align =
3938  std::max((unsigned)DL.getPrefTypeAlignment(Ty), I.getAlignment());
3939 
3940  SDValue AllocSize = getValue(I.getArraySize());
3941 
3942  EVT IntPtr = TLI.getPointerTy(DAG.getDataLayout(), DL.getAllocaAddrSpace());
3943  if (AllocSize.getValueType() != IntPtr)
3944  AllocSize = DAG.getZExtOrTrunc(AllocSize, dl, IntPtr);
3945 
3946  AllocSize = DAG.getNode(ISD::MUL, dl, IntPtr,
3947  AllocSize,
3948  DAG.getConstant(TySize, dl, IntPtr));
3949 
3950  // Handle alignment. If the requested alignment is less than or equal to
3951  // the stack alignment, ignore it. If the size is greater than or equal to
3952  // the stack alignment, we note this in the DYNAMIC_STACKALLOC node.
3953  unsigned StackAlign =
3955  if (Align <= StackAlign)
3956  Align = 0;
3957 
3958  // Round the size of the allocation up to the stack alignment size
3959  // by add SA-1 to the size. This doesn't overflow because we're computing
3960  // an address inside an alloca.
3961  SDNodeFlags Flags;
3962  Flags.setNoUnsignedWrap(true);
3963  AllocSize = DAG.getNode(ISD::ADD, dl, AllocSize.getValueType(), AllocSize,
3964  DAG.getConstant(StackAlign - 1, dl, IntPtr), Flags);
3965 
3966  // Mask out the low bits for alignment purposes.
3967  AllocSize =
3968  DAG.getNode(ISD::AND, dl, AllocSize.getValueType(), AllocSize,
3969  DAG.getConstant(~(uint64_t)(StackAlign - 1), dl, IntPtr));
3970 
3971  SDValue Ops[] = {getRoot(), AllocSize, DAG.getConstant(Align, dl, IntPtr)};
3972  SDVTList VTs = DAG.getVTList(AllocSize.getValueType(), MVT::Other);
3973  SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, dl, VTs, Ops);
3974  setValue(&I, DSA);
3975  DAG.setRoot(DSA.getValue(1));
3976 
3977  assert(FuncInfo.MF->getFrameInfo().hasVarSizedObjects());
3978 }
3979 
3980 void SelectionDAGBuilder::visitLoad(const LoadInst &I) {
3981  if (I.isAtomic())
3982  return visitAtomicLoad(I);
3983 
3984  const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3985  const Value *SV = I.getOperand(0);
3986  if (TLI.supportSwiftError()) {
3987  // Swifterror values can come from either a function parameter with
3988  // swifterror attribute or an alloca with swifterror attribute.
3989  if (const Argument *Arg = dyn_cast<Argument>(SV)) {
3990  if (Arg->hasSwiftErrorAttr())
3991  return visitLoadFromSwiftError(I);
3992  }
3993 
3994  if (const AllocaInst *Alloca = dyn_cast<AllocaInst>(SV)) {
3995  if (Alloca->isSwiftError())
3996  return visitLoadFromSwiftError(I);
3997  }
3998  }
3999 
4000  SDValue Ptr = getValue(SV);
4001 
4002  Type *Ty = I.getType();
4003 
4004  bool isVolatile = I.isVolatile();
4005  bool isNonTemporal = I.getMetadata(LLVMContext::MD_nontemporal) != nullptr;
4006  bool isInvariant = I.getMetadata(LLVMContext::MD_invariant_load) != nullptr;
4007  bool isDereferenceable = isDereferenceablePointer(SV, DAG.getDataLayout());
4008  unsigned Alignment = I.getAlignment();
4009 
4010  AAMDNodes AAInfo;
4011  I.getAAMetadata(AAInfo);
4012  const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range);
4013 
4014  SmallVector<EVT, 4> ValueVTs, MemVTs;
4016  ComputeValueVTs(TLI, DAG.getDataLayout(), Ty, ValueVTs, &MemVTs, &Offsets);
4017  unsigned NumValues = ValueVTs.size();
4018  if (NumValues == 0)
4019  return;
4020 
4021  SDValue Root;
4022  bool ConstantMemory = false;
4023  if (isVolatile || NumValues > MaxParallelChains)
4024  // Serialize volatile loads with other side effects.
4025  Root = getRoot();
4026  else if (AA &&
4027  AA->pointsToConstantMemory(MemoryLocation(
4028  SV,
4030  AAInfo))) {
4031  // Do not serialize (non-volatile) loads of constant memory with anything.
4032  Root = DAG.getEntryNode();
4033  ConstantMemory = true;
4034  } else {
4035  // Do not serialize non-volatile loads against each other.
4036  Root = DAG.getRoot();
4037  }
4038 
4039  SDLoc dl = getCurSDLoc();
4040 
4041  if (isVolatile)
4042  Root = TLI.prepareVolatileOrAtomicLoad(Root, dl, DAG);
4043 
4044  // An aggregate load cannot wrap around the address space, so offsets to its
4045  // parts don't wrap either.
4046  SDNodeFlags Flags;
4047  Flags.setNoUnsignedWrap(true);
4048 
4049  SmallVector<SDValue, 4> Values(NumValues);
4050  SmallVector<SDValue, 4> Chains(std::min(MaxParallelChains, NumValues));
4051  EVT PtrVT = Ptr.getValueType();
4052  unsigned ChainI = 0;
4053  for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
4054  // Serializing loads here may result in excessive register pressure, and
4055  // TokenFactor places arbitrary choke points on the scheduler. SD scheduling
4056  // could recover a bit by hoisting nodes upward in the chain by recognizing
4057  // they are side-effect free or do not alias. The optimizer should really
4058  // avoid this case by converting large object/array copies to llvm.memcpy
4059  // (MaxParallelChains should always remain as failsafe).
4060  if (ChainI == MaxParallelChains) {
4061  assert(PendingLoads.empty() && "PendingLoads must be serialized first");
4062  SDValue Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
4063  makeArrayRef(Chains.data(), ChainI));
4064  Root = Chain;
4065  ChainI = 0;
4066  }
4067  SDValue A = DAG.getNode(ISD::ADD, dl,
4068  PtrVT, Ptr,
4069  DAG.getConstant(Offsets[i], dl, PtrVT),
4070  Flags);
4071  auto MMOFlags = MachineMemOperand::MONone;
4072  if (isVolatile)
4073  MMOFlags |= MachineMemOperand::MOVolatile;
4074  if (isNonTemporal)
4076  if (isInvariant)
4077  MMOFlags |= MachineMemOperand::MOInvariant;
4078  if (isDereferenceable)
4080  MMOFlags |= TLI.getMMOFlags(I);
4081 
4082  SDValue L = DAG.getLoad(MemVTs[i], dl, Root, A,
4083  MachinePointerInfo(SV, Offsets[i]), Alignment,
4084  MMOFlags, AAInfo, Ranges);
4085  Chains[ChainI] = L.getValue(1);
4086 
4087  if (MemVTs[i] != ValueVTs[i])
4088  L = DAG.getZExtOrTrunc(L, dl, ValueVTs[i]);
4089 
4090  Values[i] = L;
4091  }
4092 
4093  if (!ConstantMemory) {
4094  SDValue Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
4095  makeArrayRef(Chains.data(), ChainI));
4096  if (isVolatile)
4097  DAG.setRoot(Chain);
4098  else
4099  PendingLoads.push_back(Chain);
4100  }
4101 
4102  setValue(&I, DAG.getNode(ISD::MERGE_VALUES, dl,
4103  DAG.getVTList(ValueVTs), Values));
4104 }
4105 
4106 void SelectionDAGBuilder::visitStoreToSwiftError(const StoreInst &I) {
4108  "call visitStoreToSwiftError when backend supports swifterror");
4109 
4112  const Value *SrcV = I.getOperand(0);
4114  SrcV->getType(), ValueVTs, &Offsets);
4115  assert(ValueVTs.size() == 1 && Offsets[0] == 0 &&
4116  "expect a single EVT for swifterror");
4117 
4118  SDValue Src = getValue(SrcV);
4119  // Create a virtual register, then update the virtual register.
4120  unsigned VReg =
4121  SwiftError.getOrCreateVRegDefAt(&I, FuncInfo.MBB, I.getPointerOperand());
4122  // Chain, DL, Reg, N or Chain, DL, Reg, N, Glue
4123  // Chain can be getRoot or getControlRoot.
4124  SDValue CopyNode = DAG.getCopyToReg(getRoot(), getCurSDLoc(), VReg,
4125  SDValue(Src.getNode(), Src.getResNo()));
4126  DAG.setRoot(CopyNode);
4127 }
4128 
4129 void SelectionDAGBuilder::visitLoadFromSwiftError(const LoadInst &I) {
4131  "call visitLoadFromSwiftError when backend supports swifterror");
4132 
4133  assert(!I.isVolatile() &&
4134  I.getMetadata(LLVMContext::MD_nontemporal) == nullptr &&
4136  "Support volatile, non temporal, invariant for load_from_swift_error");
4137 
4138  const Value *SV = I.getOperand(0);
4139  Type *Ty = I.getType();
4140  AAMDNodes AAInfo;
4141  I.getAAMetadata(AAInfo);
4142  assert(
4143  (!AA ||
4144  !AA->pointsToConstantMemory(MemoryLocation(
4146  AAInfo))) &&
4147  "load_from_swift_error should not be constant memory");
4148 
4152  ValueVTs, &Offsets);
4153  assert(ValueVTs.size() == 1 && Offsets[0] == 0 &&
4154  "expect a single EVT for swifterror");
4155 
4156  // Chain, DL, Reg, VT, Glue or Chain, DL, Reg, VT
4157  SDValue L = DAG.getCopyFromReg(
4158  getRoot(), getCurSDLoc(),
4159  SwiftError.getOrCreateVRegUseAt(&I, FuncInfo.MBB, SV), ValueVTs[0]);
4160 
4161  setValue(&I, L);
4162 }
4163 
4164 void SelectionDAGBuilder::visitStore(const StoreInst &I) {
4165  if (I.isAtomic())
4166  return visitAtomicStore(I);
4167 
4168  const Value *SrcV = I.getOperand(0);
4169  const Value *PtrV = I.getOperand(1);
4170 
4171  const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4172  if (TLI.supportSwiftError()) {
4173  // Swifterror values can come from either a function parameter with
4174  // swifterror attribute or an alloca with swifterror attribute.
4175  if (const Argument *Arg = dyn_cast<Argument>(PtrV)) {
4176  if (Arg->hasSwiftErrorAttr())
4177  return visitStoreToSwiftError(I);
4178  }
4179 
4180  if (const AllocaInst *Alloca = dyn_cast<AllocaInst>(PtrV)) {
4181  if (Alloca->isSwiftError())
4182  return visitStoreToSwiftError(I);
4183  }
4184  }
4185 
4186  SmallVector<EVT, 4> ValueVTs, MemVTs;
4189  SrcV->getType(), ValueVTs, &MemVTs, &Offsets);
4190  unsigned NumValues = ValueVTs.size();
4191  if (NumValues == 0)
4192  return;
4193 
4194  // Get the lowered operands. Note that we do this after
4195  // checking if NumResults is zero, because with zero results
4196  // the operands won't have values in the map.
4197  SDValue Src = getValue(SrcV);
4198  SDValue Ptr = getValue(PtrV);
4199 
4200  SDValue Root = getRoot();
4201  SmallVector<SDValue, 4> Chains(std::min(MaxParallelChains, NumValues));
4202  SDLoc dl = getCurSDLoc();
4203  EVT PtrVT = Ptr.getValueType();
4204  unsigned Alignment = I.getAlignment();
4205  AAMDNodes AAInfo;
4206  I.getAAMetadata(AAInfo);
4207 
4208  auto MMOFlags = MachineMemOperand::MONone;
4209  if (I.isVolatile())
4210  MMOFlags |= MachineMemOperand::MOVolatile;
4211  if (I.getMetadata(LLVMContext::MD_nontemporal) != nullptr)
4213  MMOFlags |= TLI.getMMOFlags(I);
4214 
4215  // An aggregate load cannot wrap around the address space, so offsets to its
4216  // parts don't wrap either.
4217  SDNodeFlags Flags;
4218  Flags.setNoUnsignedWrap(true);
4219 
4220  unsigned ChainI = 0;
4221  for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
4222  // See visitLoad comments.
4223  if (ChainI == MaxParallelChains) {
4224  SDValue Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
4225  makeArrayRef(Chains.data(), ChainI));
4226  Root = Chain;
4227  ChainI = 0;
4228  }
4229  SDValue Add = DAG.getNode(ISD::ADD, dl, PtrVT, Ptr,
4230  DAG.getConstant(Offsets[i], dl, PtrVT), Flags);
4231  SDValue Val = SDValue(Src.getNode(), Src.getResNo() + i);
4232  if (MemVTs[i] != ValueVTs[i])
4233  Val = DAG.getPtrExtOrTrunc(Val, dl, MemVTs[i]);
4234  SDValue St =
4235  DAG.getStore(Root, dl, Val, Add, MachinePointerInfo(PtrV, Offsets[i]),
4236  Alignment, MMOFlags, AAInfo);
4237  Chains[ChainI] = St;
4238  }
4239 
4240  SDValue StoreNode = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
4241  makeArrayRef(Chains.data(), ChainI));
4242  DAG.setRoot(StoreNode);
4243 }
4244 
4245 void SelectionDAGBuilder::visitMaskedStore(const CallInst &I,
4246  bool IsCompressing) {
4247  SDLoc sdl = getCurSDLoc();
4248 
4249  auto getMaskedStoreOps = [&](Value* &Ptr, Value* &Mask, Value* &Src0,
4250  unsigned& Alignment) {
4251  // llvm.masked.store.*(Src0, Ptr, alignment, Mask)
4252  Src0 = I.getArgOperand(0);
4253  Ptr = I.getArgOperand(1);
4254  Alignment = cast<ConstantInt>(I.getArgOperand(2))->getZExtValue();
4255  Mask = I.getArgOperand(3);
4256  };
4257  auto getCompressingStoreOps = [&](Value* &Ptr, Value* &Mask, Value* &Src0,
4258  unsigned& Alignment) {
4259  // llvm.masked.compressstore.*(Src0, Ptr, Mask)
4260  Src0 = I.getArgOperand(0);
4261  Ptr = I.getArgOperand(1);
4262  Mask = I.getArgOperand(2);
4263  Alignment = 0;
4264  };
4265 
4266  Value *PtrOperand, *MaskOperand, *Src0Operand;
4267  unsigned Alignment;
4268  if (IsCompressing)
4269  getCompressingStoreOps(PtrOperand, MaskOperand, Src0Operand, Alignment);
4270  else
4271  getMaskedStoreOps(PtrOperand, MaskOperand, Src0Operand, Alignment);
4272 
4273  SDValue Ptr = getValue(PtrOperand);
4274  SDValue Src0 = getValue(Src0Operand);
4275  SDValue Mask = getValue(MaskOperand);
4276 
4277  EVT VT = Src0.getValueType();
4278  if (!Alignment)
4279  Alignment = DAG.getEVTAlignment(VT);
4280 
4281  AAMDNodes AAInfo;
4282  I.getAAMetadata(AAInfo);
4283 
4284  MachineMemOperand *MMO =
4285  DAG.getMachineFunction().
4288  Alignment, AAInfo);
4289  SDValue StoreNode = DAG.getMaskedStore(getRoot(), sdl, Src0, Ptr, Mask, VT,
4290  MMO, false /* Truncating */,
4291  IsCompressing);
4292  DAG.setRoot(StoreNode);
4293  setValue(&I, StoreNode);
4294 }
4295 
4296 // Get a uniform base for the Gather/Scatter intrinsic.
4297 // The first argument of the Gather/Scatter intrinsic is a vector of pointers.
4298 // We try to represent it as a base pointer + vector of indices.
4299 // Usually, the vector of pointers comes from a 'getelementptr' instruction.
4300 // The first operand of the GEP may be a single pointer or a vector of pointers
4301 // Example:
4302 // %gep.ptr = getelementptr i32, <8 x i32*> %vptr, <8 x i32> %ind
4303 // or
4304 // %gep.ptr = getelementptr i32, i32* %ptr, <8 x i32> %ind
4305 // %res = call <8 x i32> @llvm.masked.gather.v8i32(<8 x i32*> %gep.ptr, ..
4306 //
4307 // When the first GEP operand is a single pointer - it is the uniform base we
4308 // are looking for. If first operand of the GEP is a splat vector - we
4309 // extract the splat value and use it as a uniform base.
4310 // In all other cases the function returns 'false'.
4311 static bool getUniformBase(const Value* &Ptr, SDValue& Base, SDValue& Index,
4312  SDValue &Scale, SelectionDAGBuilder* SDB) {
4313  SelectionDAG& DAG = SDB->DAG;
4314  LLVMContext &Context = *DAG.getContext();
4315 
4316  assert(Ptr->getType()->isVectorTy() && "Uexpected pointer type");
4318  if (!GEP)
4319  return false;
4320 
4321  const Value *GEPPtr = GEP->getPointerOperand();
4322  if (!GEPPtr->getType()->isVectorTy())
4323  Ptr = GEPPtr;
4324  else if (!(Ptr = getSplatValue(GEPPtr)))
4325  return false;
4326 
4327  unsigned FinalIndex = GEP->getNumOperands() - 1;
4328  Value *IndexVal = GEP->getOperand(FinalIndex);
4329 
4330  // Ensure all the other indices are 0.
4331  for (unsigned i = 1; i < FinalIndex; ++i) {
4332  auto *C = dyn_cast<ConstantInt>(GEP->getOperand(i));
4333  if (!C || !C->isZero())
4334  return false;
4335  }
4336 
4337  // The operands of the GEP may be defined in another basic block.
4338  // In this case we'll not find nodes for the operands.
4339  if (!SDB->findValue(Ptr) || !SDB->findValue(IndexVal))
4340  return false;
4341 
4342  const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4343  const DataLayout &DL = DAG.getDataLayout();
4344  Scale = DAG.getTargetConstant(DL.getTypeAllocSize(GEP->getResultElementType()),
4345  SDB->getCurSDLoc(), TLI.getPointerTy(DL));
4346  Base = SDB->getValue(Ptr);
4347  Index = SDB->getValue(IndexVal);
4348 
4349  if (!Index.getValueType().isVector()) {
4350  unsigned GEPWidth = GEP->getType()->getVectorNumElements();
4351  EVT VT = EVT::getVectorVT(Context, Index.getValueType(), GEPWidth);
4352  Index = DAG.getSplatBuildVector(VT, SDLoc(Index), Index);
4353  }
4354  return true;
4355 }
4356 
4357 void SelectionDAGBuilder::visitMaskedScatter(const CallInst &I) {
4358  SDLoc sdl = getCurSDLoc();
4359 
4360  // llvm.masked.scatter.*(Src0, Ptrs, alignemt, Mask)
4361  const Value *Ptr = I.getArgOperand(1);
4362  SDValue Src0 = getValue(I.getArgOperand(0));
4363  SDValue Mask = getValue(I.getArgOperand(3));
4364  EVT VT = Src0.getValueType();
4365  unsigned Alignment = (cast<ConstantInt>(I.getArgOperand(2)))->getZExtValue();
4366  if (!Alignment)
4367  Alignment = DAG.getEVTAlignment(VT);
4368  const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4369 
4370  AAMDNodes AAInfo;
4371  I.getAAMetadata(AAInfo);
4372 
4373  SDValue Base;
4374  SDValue Index;
4375  SDValue Scale;
4376  const Value *BasePtr = Ptr;
4377  bool UniformBase = getUniformBase(BasePtr, Base, Index, Scale, this);
4378 
4379  const Value *MemOpBasePtr = UniformBase ? BasePtr : nullptr;
4382  MachineMemOperand::MOStore, VT.getStoreSize(),
4383  Alignment, AAInfo);
4384  if (!UniformBase) {
4385  Base = DAG.getConstant(0, sdl, TLI.getPointerTy(DAG.getDataLayout()));
4386  Index = getValue(Ptr);
4387  Scale = DAG.getTargetConstant(1, sdl, TLI.getPointerTy(DAG.getDataLayout()));
4388  }
4389  SDValue Ops[] = { getRoot(), Src0, Mask, Base, Index, Scale };
4390  SDValue Scatter = DAG.getMaskedScatter(DAG.getVTList(MVT::Other), VT, sdl,
4391  Ops, MMO);
4392  DAG.setRoot(Scatter);
4393  setValue(&I, Scatter);
4394 }
4395 
4396 void SelectionDAGBuilder::visitMaskedLoad(const CallInst &I, bool IsExpanding) {
4397  SDLoc sdl = getCurSDLoc();
4398 
4399  auto getMaskedLoadOps = [&](Value* &Ptr, Value* &Mask, Value* &Src0,
4400  unsigned& Alignment) {
4401  // @llvm.masked.load.*(Ptr, alignment, Mask, Src0)
4402  Ptr = I.getArgOperand(0);
4403  Alignment = cast<ConstantInt>(I.getArgOperand(1))->getZExtValue();
4404  Mask = I.getArgOperand(2);
4405  Src0 = I.getArgOperand(3);
4406  };
4407  auto getExpandingLoadOps = [&](Value* &Ptr, Value* &Mask, Value* &Src0,
4408  unsigned& Alignment) {
4409  // @llvm.masked.expandload.*(Ptr, Mask, Src0)
4410  Ptr = I.getArgOperand(0);
4411  Alignment = 0;
4412  Mask = I.getArgOperand(1);
4413  Src0 = I.getArgOperand(2);
4414  };
4415 
4416  Value *PtrOperand, *MaskOperand, *Src0Operand;
4417  unsigned Alignment;
4418  if (IsExpanding)
4419  getExpandingLoadOps(PtrOperand, MaskOperand, Src0Operand, Alignment);
4420  else
4421  getMaskedLoadOps(PtrOperand, MaskOperand, Src0Operand, Alignment);
4422 
4423  SDValue Ptr = getValue(PtrOperand);
4424  SDValue Src0 = getValue(Src0Operand);
4425  SDValue Mask = getValue(MaskOperand);
4426 
4427  EVT VT = Src0.getValueType();
4428  if (!Alignment)
4429  Alignment = DAG.getEVTAlignment(VT);
4430 
4431  AAMDNodes AAInfo;
4432  I.getAAMetadata(AAInfo);
4433  const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range);
4434 
4435  // Do not serialize masked loads of constant memory with anything.
4436  bool AddToChain =
4437  !AA || !AA->pointsToConstantMemory(MemoryLocation(
4438  PtrOperand,
4441  AAInfo));
4442  SDValue InChain = AddToChain ? DAG.getRoot() : DAG.getEntryNode();
4443 
4444  MachineMemOperand *MMO =
4445  DAG.getMachineFunction().
4448  Alignment, AAInfo, Ranges);
4449 
4450  SDValue Load = DAG.getMaskedLoad(VT, sdl, InChain, Ptr, Mask, Src0, VT, MMO,
4451  ISD::NON_EXTLOAD, IsExpanding);
4452  if (AddToChain)
4453  PendingLoads.push_back(Load.getValue(1));
4454  setValue(&I, Load);
4455 }
4456 
4457 void SelectionDAGBuilder::visitMaskedGather(const CallInst &I) {
4458  SDLoc sdl = getCurSDLoc();
4459 
4460  // @llvm.masked.gather.*(Ptrs, alignment, Mask, Src0)
4461  const Value *Ptr = I.getArgOperand(0);
4462  SDValue Src0 = getValue(I.getArgOperand(3));
4463  SDValue Mask = getValue(I.getArgOperand(2));
4464 
4465  const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4466  EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
4467  unsigned Alignment = (cast<ConstantInt>(I.getArgOperand(1)))->getZExtValue();
4468  if (!Alignment)
4469  Alignment = DAG.getEVTAlignment(VT);
4470 
4471  AAMDNodes AAInfo;
4472  I.getAAMetadata(AAInfo);
4473  const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range);
4474 
4475  SDValue Root = DAG.getRoot();
4476  SDValue Base;
4477  SDValue Index;
4478  SDValue Scale;
4479  const Value *BasePtr = Ptr;
4480  bool UniformBase = getUniformBase(BasePtr, Base, Index, Scale, this);
4481  bool ConstantMemory = false;
4482  if (UniformBase && AA &&
4483  AA->pointsToConstantMemory(
4484  MemoryLocation(BasePtr,
4487  AAInfo))) {
4488  // Do not serialize (non-volatile) loads of constant memory with anything.
4489  Root = DAG.getEntryNode();
4490  ConstantMemory = true;
4491  }
4492 
4493  MachineMemOperand *MMO =
4494  DAG.getMachineFunction().
4495  getMachineMemOperand(MachinePointerInfo(UniformBase ? BasePtr : nullptr),
4497  Alignment, AAInfo, Ranges);
4498 
4499  if (!UniformBase) {
4500  Base = DAG.getConstant(0, sdl, TLI.getPointerTy(DAG.getDataLayout()));
4501  Index = getValue(Ptr);
4502  Scale = DAG.getTargetConstant(1, sdl, TLI.getPointerTy(DAG.getDataLayout()));
4503  }
4504  SDValue Ops[] = { Root, Src0, Mask, Base, Index, Scale };
4505  SDValue Gather = DAG.getMaskedGather(DAG.getVTList(VT, MVT::Other), VT, sdl,
4506  Ops, MMO);
4507 
4508  SDValue OutChain = Gather.getValue(1);
4509  if (!ConstantMemory)
4510  PendingLoads.push_back(OutChain);
4511  setValue(&I, Gather);
4512 }
4513 
4514 void SelectionDAGBuilder::visitAtomicCmpXchg(const AtomicCmpXchgInst &I) {
4515  SDLoc dl = getCurSDLoc();
4516  AtomicOrdering SuccessOrdering = I.getSuccessOrdering();
4517  AtomicOrdering FailureOrdering = I.getFailureOrdering();
4518  SyncScope::ID SSID = I.getSyncScopeID();
4519 
4520  SDValue InChain = getRoot();
4521 
4522  MVT MemVT = getValue(I.getCompareOperand()).getSimpleValueType();
4523  SDVTList VTs = DAG.getVTList(MemVT, MVT::i1, MVT::Other);
4524 
4525  auto Alignment = DAG.getEVTAlignment(MemVT);
4526 
4528  if (I.isVolatile())
4530  Flags |= DAG.getTargetLoweringInfo().getMMOFlags(I);
4531 
4532  MachineFunction &MF = DAG.getMachineFunction();
4533  MachineMemOperand *MMO =
4535  Flags, MemVT.getStoreSize(), Alignment,
4536  AAMDNodes(), nullptr, SSID, SuccessOrdering,
4537  FailureOrdering);
4538 
4540  dl, MemVT, VTs, InChain,
4541  getValue(I.getPointerOperand()),
4542  getValue(I.getCompareOperand()),
4543  getValue(I.getNewValOperand()), MMO);
4544 
4545  SDValue OutChain = L.getValue(2);
4546 
4547  setValue(&I, L);
4548  DAG.setRoot(OutChain);
4549 }
4550 
4551 void SelectionDAGBuilder::visitAtomicRMW(const AtomicRMWInst &I) {
4552  SDLoc dl = getCurSDLoc();
4553  ISD::NodeType NT;
4554  switch (I.getOperation()) {
4555  default: llvm_unreachable("Unknown atomicrmw operation");
4556  case AtomicRMWInst::Xchg: NT = ISD::ATOMIC_SWAP; break;
4557  case AtomicRMWInst::Add: NT = ISD::ATOMIC_LOAD_ADD; break;
4558  case AtomicRMWInst::Sub: NT = ISD::ATOMIC_LOAD_SUB; break;
4559  case AtomicRMWInst::And: NT = ISD::ATOMIC_LOAD_AND; break;
4560  case AtomicRMWInst::Nand: NT = ISD::ATOMIC_LOAD_NAND; break;
4561  case AtomicRMWInst::Or: NT = ISD::ATOMIC_LOAD_OR; break;
4562  case AtomicRMWInst::Xor: NT = ISD::ATOMIC_LOAD_XOR; break;
4563  case AtomicRMWInst::Max: NT = ISD::ATOMIC_LOAD_MAX; break;
4564  case AtomicRMWInst::Min: NT = ISD::ATOMIC_LOAD_MIN; break;
4565  case AtomicRMWInst::UMax: NT = ISD::ATOMIC_LOAD_UMAX; break;
4566  case AtomicRMWInst::UMin: NT = ISD::ATOMIC_LOAD_UMIN; break;
4567  case AtomicRMWInst::FAdd: NT = ISD::ATOMIC_LOAD_FADD; break;
4568  case AtomicRMWInst::FSub: NT = ISD::ATOMIC_LOAD_FSUB; break;
4569  }
4570  AtomicOrdering Ordering = I.getOrdering();
4571  SyncScope::ID SSID = I.getSyncScopeID();
4572 
4573  SDValue InChain = getRoot();
4574 
4575  auto MemVT = getValue(I.getValOperand()).getSimpleValueType();
4576  auto Alignment = DAG.getEVTAlignment(MemVT);
4577 
4579  if (I.isVolatile())
4581  Flags |= DAG.getTargetLoweringInfo().getMMOFlags(I);
4582 
4583  MachineFunction &MF = DAG.getMachineFunction();
4584  MachineMemOperand *MMO =
4586  MemVT.getStoreSize(), Alignment, AAMDNodes(),
4587  nullptr, SSID, Ordering);
4588 
4589  SDValue L =
4590  DAG.getAtomic(NT, dl, MemVT, InChain,
4591  getValue(I.getPointerOperand()), getValue(I.getValOperand()),
4592  MMO);
4593 
4594  SDValue OutChain = L.getValue(1);
4595 
4596  setValue(&I, L);
4597  DAG.setRoot(OutChain);
4598 }
4599 
4600 void SelectionDAGBuilder::visitFence(const FenceInst &I) {
4601  SDLoc dl = getCurSDLoc();
4602  const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4603  SDValue Ops[3];
4604  Ops[0] = getRoot();
4605  Ops[1] = DAG.getConstant((unsigned)I.getOrdering(), dl,
4606  TLI.getFenceOperandTy(DAG.getDataLayout()));
4607  Ops[2] = DAG.getConstant(I.getSyncScopeID(), dl,
4608  TLI.getFenceOperandTy(DAG.getDataLayout()));
4609  DAG.setRoot(DAG.getNode(ISD::ATOMIC_FENCE, dl, MVT::Other, Ops));
4610 }
4611 
4612 void SelectionDAGBuilder::visitAtomicLoad(const LoadInst &I) {
4613  SDLoc dl = getCurSDLoc();
4614  AtomicOrdering Order = I.getOrdering();
4615  SyncScope::ID SSID = I.getSyncScopeID();
4616 
4617  SDValue InChain = getRoot();
4618 
4619  const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4620  EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
4621  EVT MemVT = TLI.getMemValueType(DAG.getDataLayout(), I.getType());
4622 
4623  if (!TLI.supportsUnalignedAtomics() &&
4624  I.getAlignment() < MemVT.getSizeInBits() / 8)
4625  report_fatal_error("Cannot generate unaligned atomic load");
4626 
4627  auto Flags = MachineMemOperand::MOLoad;
4628  if (I.isVolatile())
4630  if (I.getMetadata(LLVMContext::MD_invariant_load) != nullptr)
4634 
4635  Flags |= TLI.getMMOFlags(I);
4636 
4637  MachineMemOperand *MMO =
4638  DAG.getMachineFunction().
4640  Flags, MemVT.getStoreSize(),
4641  I.getAlignment() ? I.getAlignment() :
4642  DAG.getEVTAlignment(MemVT),
4643  AAMDNodes(), nullptr, SSID, Order);
4644 
4645  InChain = TLI.prepareVolatileOrAtomicLoad(InChain, dl, DAG);
4646  SDValue L =
4647  DAG.getAtomic(ISD::ATOMIC_LOAD, dl, MemVT, MemVT, InChain,
4648  getValue(I.getPointerOperand()), MMO);
4649 
4650  SDValue OutChain = L.getValue(1);
4651  if (MemVT != VT)
4652  L = DAG.getPtrExtOrTrunc(L, dl, VT);
4653 
4654  setValue(&I, L);
4655  DAG.setRoot(OutChain);
4656 }
4657 
4658 void SelectionDAGBuilder::visitAtomicStore(const StoreInst &I) {
4659  SDLoc dl = getCurSDLoc();
4660 
4661  AtomicOrdering Ordering = I.getOrdering();
4662  SyncScope::ID SSID = I.getSyncScopeID();
4663 
4664  SDValue InChain = getRoot();
4665 
4666  const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4667  EVT MemVT =
4669 
4670  if (I.getAlignment() < MemVT.getSizeInBits() / 8)
4671  report_fatal_error("Cannot generate unaligned atomic store");
4672 
4673  auto Flags = MachineMemOperand::MOStore;
4674  if (I.isVolatile())
4676  Flags |= TLI.getMMOFlags(I);
4677 
4678  MachineFunction &MF = DAG.getMachineFunction();
4679  MachineMemOperand *MMO =
4681  MemVT.getStoreSize(), I.getAlignment(), AAMDNodes(),
4682  nullptr, SSID, Ordering);
4683 
4684  SDValue Val = getValue(I.getValueOperand());
4685  if (Val.getValueType() != MemVT)
4686  Val = DAG.getPtrExtOrTrunc(Val, dl, MemVT);
4687 
4688  SDValue OutChain = DAG.getAtomic(ISD::ATOMIC_STORE, dl, MemVT, InChain,
4689  getValue(I.getPointerOperand()), Val, MMO);
4690 
4691 
4692  DAG.setRoot(OutChain);
4693 }
4694 
4695 /// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
4696 /// node.
4697 void SelectionDAGBuilder::visitTargetIntrinsic(const CallInst &I,
4698  unsigned Intrinsic) {
4699  // Ignore the callsite's attributes. A specific call site may be marked with
4700  // readnone, but the lowering code will expect the chain based on the
4701  // definition.
4702  const Function *F = I.getCalledFunction();
4703  bool HasChain = !F->doesNotAccessMemory();
4704  bool OnlyLoad = HasChain && F->onlyReadsMemory();
4705 
4706  // Build the operand list.
4708  if (HasChain) { // If this intrinsic has side-effects, chainify it.
4709  if (OnlyLoad) {
4710  // We don't need to serialize loads against other loads.
4711  Ops.push_back(DAG.getRoot());
4712  } else {
4713  Ops.push_back(getRoot());
4714  }
4715  }
4716 
4717  // Info is set by getTgtMemInstrinsic
4718  TargetLowering::IntrinsicInfo Info;
4719  const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4720  bool IsTgtIntrinsic = TLI.getTgtMemIntrinsic(Info, I,
4721  DAG.getMachineFunction(),
4722  Intrinsic);
4723 
4724  // Add the intrinsic ID as an integer operand if it's not a target intrinsic.
4725  if (!IsTgtIntrinsic || Info.opc == ISD::INTRINSIC_VOID ||
4726  Info.opc == ISD::INTRINSIC_W_CHAIN)
4727  Ops.push_back(DAG.getTargetConstant(Intrinsic, getCurSDLoc(),
4728  TLI.getPointerTy(DAG.getDataLayout())));
4729 
4730  // Add all operands of the call to the operand list.
4731  for (unsigned i = 0, e = I.getNumArgOperands(); i != e; ++i) {
4732  SDValue Op = getValue(I.getArgOperand(i));
4733  Ops.push_back(Op);
4734  }
4735 
4737  ComputeValueVTs(TLI, DAG.getDataLayout(), I.getType(), ValueVTs);
4738 
4739  if (HasChain)
4740  ValueVTs.push_back(MVT::Other);
4741 
4742  SDVTList VTs = DAG.getVTList(ValueVTs);
4743 
4744  // Create the node.
4745  SDValue Result;
4746  if (IsTgtIntrinsic) {
4747  // This is target intrinsic that touches memory
4748  Result = DAG.getMemIntrinsicNode(Info.opc, getCurSDLoc(), VTs,
4749  Ops, Info.memVT,
4750  MachinePointerInfo(Info.ptrVal, Info.offset), Info.align,
4751  Info.flags, Info.size);
4752  } else if (!HasChain) {
4753  Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, getCurSDLoc(), VTs, Ops);
4754  } else if (!I.getType()->isVoidTy()) {
4755  Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, getCurSDLoc(), VTs, Ops);
4756  } else {
4757  Result = DAG.getNode(ISD::INTRINSIC_VOID, getCurSDLoc(), VTs, Ops);
4758  }
4759 
4760  if (HasChain) {
4761  SDValue Chain = Result.getValue(Result.getNode()->getNumValues()-1);
4762  if (OnlyLoad)
4763  PendingLoads.push_back(Chain);
4764  else
4765  DAG.setRoot(Chain);
4766  }
4767 
4768  if (!I.getType()->isVoidTy()) {
4769  if (VectorType *PTy = dyn_cast<VectorType>(I.getType())) {
4770  EVT VT = TLI.getValueType(DAG.getDataLayout(), PTy);
4771  Result = DAG.getNode(ISD::BITCAST, getCurSDLoc(), VT, Result);
4772  } else
4773  Result = lowerRangeToAssertZExt(DAG, I, Result);
4774 
4775  setValue(&I, Result);
4776  }
4777 }
4778 
4779 /// GetSignificand - Get the significand and build it into a floating-point
4780 /// number with exponent of 1:
4781 ///
4782 /// Op = (Op & 0x007fffff) | 0x3f800000;
4783 ///
4784 /// where Op is the hexadecimal representation of floating point value.
4786  SDValue t1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
4787  DAG.getConstant(0x007fffff, dl, MVT::i32));
4788  SDValue t2 = DAG.getNode(ISD::OR, dl, MVT::i32, t1,
4789  DAG.getConstant(0x3f800000, dl, MVT::i32));
4790  return DAG.getNode(ISD::BITCAST, dl, MVT::f32, t2);
4791 }
4792 
4793 /// GetExponent - Get the exponent:
4794 ///
4795 /// (float)(int)(((Op & 0x7f800000) >> 23) - 127);
4796 ///
4797 /// where Op is the hexadecimal representation of floating point value.
4799  const TargetLowering &TLI, const SDLoc &dl) {
4800  SDValue t0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
4801  DAG.getConstant(0x7f800000, dl, MVT::i32));
4802  SDValue t1 = DAG.getNode(
4803  ISD::SRL, dl, MVT::i32, t0,
4804  DAG.getConstant(23, dl, TLI.getPointerTy(DAG.getDataLayout())));
4805  SDValue t2 = DAG.getNode(ISD::SUB, dl, MVT::i32, t1,
4806  DAG.getConstant(127, dl, MVT::i32));
4807  return DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, t2);
4808 }
4809 
4810 /// getF32Constant - Get 32-bit floating point constant.
4811 static SDValue getF32Constant(SelectionDAG &DAG, unsigned Flt,
4812  const SDLoc &dl) {
4813  return DAG.getConstantFP(APFloat(APFloat::IEEEsingle(), APInt(32, Flt)), dl,
4814  MVT::f32);
4815 }
4816 
4818  SelectionDAG &DAG) {
4819  // TODO: What fast-math-flags should be set on the floating-point nodes?
4820 
4821  // IntegerPartOfX = ((int32_t)(t0);
4822  SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
4823 
4824  // FractionalPartOfX = t0 - (float)IntegerPartOfX;
4825  SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
4826  SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
4827 
4828  // IntegerPartOfX <<= 23;
4829  IntegerPartOfX = DAG.getNode(
4830  ISD::SHL, dl, MVT::i32, IntegerPartOfX,
4832  DAG.getDataLayout())));
4833 
4834  SDValue TwoToFractionalPartOfX;
4835  if (LimitFloatPrecision <= 6) {
4836  // For floating-point precision of 6:
4837  //
4838  // TwoToFractionalPartOfX =
4839  // 0.997535578f +
4840  // (0.735607626f + 0.252464424f * x) * x;
4841  //
4842  // error 0.0144103317, which is 6 bits
4843  SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4844  getF32Constant(DAG, 0x3e814304, dl));
4845  SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4846  getF32Constant(DAG, 0x3f3c50c8, dl));
4847  SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4848  TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4849  getF32Constant(DAG, 0x3f7f5e7e, dl));
4850  } else if (LimitFloatPrecision <= 12) {
4851  // For floating-point precision of 12:
4852  //
4853  // TwoToFractionalPartOfX =
4854  // 0.999892986f +
4855  // (0.696457318f +
4856  // (0.224338339f + 0.792043434e-1f * x) * x) * x;
4857  //
4858  // error 0.000107046256, which is 13 to 14 bits
4859  SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4860  getF32Constant(DAG, 0x3da235e3, dl));
4861  SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4862  getF32Constant(DAG, 0x3e65b8f3, dl));
4863  SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4864  SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4865  getF32Constant(DAG, 0x3f324b07, dl));
4866  SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4867  TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4868  getF32Constant(DAG, 0x3f7ff8fd, dl));
4869  } else { // LimitFloatPrecision <= 18
4870  // For floating-point precision of 18:
4871  //
4872  // TwoToFractionalPartOfX =
4873  // 0.999999982f +
4874  // (0.693148872f +
4875  // (0.240227044f +
4876  // (0.554906021e-1f +
4877  // (0.961591928e-2f +
4878  // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
4879  // error 2.47208000*10^(-7), which is better than 18 bits
4880  SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4881  getF32Constant(DAG, 0x3924b03e, dl));
4882  SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4883  getF32Constant(DAG, 0x3ab24b87, dl));
4884  SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4885  SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4886  getF32Constant(DAG, 0x3c1d8c17, dl));
4887  SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4888  SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4889  getF32Constant(DAG, 0x3d634a1d, dl));
4890  SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4891  SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
4892  getF32Constant(DAG, 0x3e75fe14, dl));
4893  SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
4894  SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
4895  getF32Constant(DAG, 0x3f317234, dl));
4896  SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
4897  TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
4898  getF32Constant(DAG, 0x3f800000, dl));
4899  }
4900 
4901  // Add the exponent into the result in integer domain.
4902  SDValue t13 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, TwoToFractionalPartOfX);
4903  return DAG.getNode(ISD::BITCAST, dl, MVT::f32,
4904  DAG.getNode(ISD::ADD, dl, MVT::i32, t13, IntegerPartOfX));
4905 }
4906 
4907 /// expandExp - Lower an exp intrinsic. Handles the special sequences for
4908 /// limited-precision mode.
4909 static SDValue expandExp(const SDLoc &dl, SDValue Op, SelectionDAG &DAG,
4910  const TargetLowering &TLI) {
4911  if (Op.getValueType() == MVT::f32 &&
4912  LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4913 
4914  // Put the exponent in the right bit position for later addition to the
4915  // final result:
4916  //
4917  // #define LOG2OFe 1.4426950f
4918  // t0 = Op * LOG2OFe
4919 
4920  // TODO: What fast-math-flags should be set here?
4921  SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
4922  getF32Constant(DAG, 0x3fb8aa3b, dl));
4923  return getLimitedPrecisionExp2(t0, dl, DAG);
4924  }
4925 
4926  // No special expansion.
4927  return DAG.getNode(ISD::FEXP, dl, Op.getValueType(), Op);
4928 }
4929 
4930 /// expandLog - Lower a log intrinsic. Handles the special sequences for
4931 /// limited-precision mode.
4932 static SDValue expandLog(const SDLoc &dl, SDValue Op, SelectionDAG &DAG,
4933  const TargetLowering &TLI) {
4934  // TODO: What fast-math-flags should be set on the floating-point nodes?
4935 
4936  if (Op.getValueType() == MVT::f32 &&
4937  LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4938  SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
4939 
4940  // Scale the exponent by log(2) [0.69314718f].
4941  SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
4942  SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
4943  getF32Constant(DAG, 0x3f317218, dl));
4944 
4945  // Get the significand and build it into a floating-point number with
4946  // exponent of 1.
4947  SDValue X = GetSignificand(DAG, Op1, dl);
4948 
4949  SDValue LogOfMantissa;
4950  if (LimitFloatPrecision <= 6) {
4951  // For floating-point precision of 6:
4952  //
4953  // LogofMantissa =
4954  // -1.1609546f +
4955  // (1.4034025f - 0.23903021f * x) * x;
4956  //
4957  // error 0.0034276066, which is better than 8 bits
4958  SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4959  getF32Constant(DAG, 0xbe74c456, dl));
4960  SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4961  getF32Constant(DAG, 0x3fb3a2b1, dl));
4962  SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4963  LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4964  getF32Constant(DAG, 0x3f949a29, dl));
4965  } else if (LimitFloatPrecision <= 12) {
4966  // For floating-point precision of 12:
4967  //
4968  // LogOfMantissa =
4969  // -1.7417939f +
4970  // (2.8212026f +
4971  // (-1.4699568f +
4972  // (0.44717955f - 0.56570851e-1f * x) * x) * x) * x;
4973  //
4974  // error 0.000061011436, which is 14 bits
4975  SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4976  getF32Constant(DAG, 0xbd67b6d6, dl));
4977  SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4978  getF32Constant(DAG, 0x3ee4f4b8, dl));
4979  SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4980  SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4981  getF32Constant(DAG, 0x3fbc278b, dl));
4982  SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4983  SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4984  getF32Constant(DAG, 0x40348e95, dl));
4985  SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4986  LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
4987  getF32Constant(DAG, 0x3fdef31a, dl));
4988  } else { // LimitFloatPrecision <= 18
4989  // For floating-point precision of 18:
4990  //
4991  // LogOfMantissa =
4992  // -2.1072184f +
4993  // (4.2372794f +
4994  // (-3.7029485f +
4995  // (2.2781945f +
4996  // (-0.87823314f +
4997  // (0.19073739f - 0.17809712e-1f * x) * x) * x) * x) * x)*x;
4998  //
4999  // error 0.0000023660568, which is better than 18 bits
5000  SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
5001  getF32Constant(DAG, 0xbc91e5ac, dl));
5002  SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
5003  getF32Constant(DAG, 0x3e4350aa, dl));
5004  SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
5005  SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
5006  getF32Constant(DAG, 0x3f60d3e3, dl));
5007  SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
5008  SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
5009  getF32Constant(DAG, 0x4011cdf0, dl));
5010  SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
5011  SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
5012  getF32Constant(DAG, 0x406cfd1c, dl));
5013  SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
5014  SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
5015  getF32Constant(DAG, 0x408797cb, dl));
5016  SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
5017  LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
5018  getF32Constant(DAG, 0x4006dcab, dl));
5019  }
5020 
5021  return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, LogOfMantissa);
5022  }
5023 
5024  // No special expansion.
5025  return DAG.getNode(ISD::FLOG, dl, Op.getValueType(), Op);
5026 }
5027 
5028 /// expandLog2 - Lower a log2 intrinsic. Handles the special sequences for
5029 /// limited-precision mode.
5030 static SDValue expandLog2(const SDLoc &dl, SDValue Op, SelectionDAG &DAG,
5031  const TargetLowering &TLI) {
5032  // TODO: What fast-math-flags should be set on the floating-point nodes?
5033 
5034  if (Op.getValueType() == MVT::f32 &&
5035  LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
5036  SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
5037 
5038  // Get the exponent.
5039  SDValue LogOfExponent = GetExponent(DAG, Op1, TLI, dl);
5040 
5041  // Get the significand and build it into a floating-point number with
5042  // exponent of 1.
5043  SDValue X = GetSignificand(DAG, Op1, dl);
5044 
5045  // Different possible minimax approximations of significand in
5046  // floating-point for various degrees of accuracy over [1,2].
5047  SDValue Log2ofMantissa;
5048  if (LimitFloatPrecision <= 6) {
5049  // For floating-point precision of 6:
5050  //
5051  // Log2ofMantissa = -1.6749035f + (2.0246817f - .34484768f * x) * x;
5052  //
5053  // error 0.0049451742, which is more than 7 bits
5054  SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
5055  getF32Constant(DAG, 0xbeb08fe0, dl));
5056  SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
5057