LLVM  6.0.0svn
SIInstrInfo.h
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1 //===- SIInstrInfo.h - SI Instruction Info Interface ------------*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file
11 /// \brief Interface definition for SIInstrInfo.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #ifndef LLVM_LIB_TARGET_AMDGPU_SIINSTRINFO_H
16 #define LLVM_LIB_TARGET_AMDGPU_SIINSTRINFO_H
17 
18 #include "AMDGPUInstrInfo.h"
19 #include "SIDefines.h"
20 #include "SIRegisterInfo.h"
21 #include "Utils/AMDGPUBaseInfo.h"
22 #include "llvm/ADT/ArrayRef.h"
23 #include "llvm/ADT/SetVector.h"
29 #include "llvm/MC/MCInstrDesc.h"
30 #include "llvm/Support/Compiler.h"
31 #include <cassert>
32 #include <cstdint>
33 
34 namespace llvm {
35 
36 class APInt;
37 class MachineRegisterInfo;
38 class RegScavenger;
39 class SISubtarget;
40 class TargetRegisterClass;
41 
42 class SIInstrInfo final : public AMDGPUInstrInfo {
43 private:
44  const SIRegisterInfo RI;
45  const SISubtarget &ST;
46 
47  // The the inverse predicate should have the negative value.
48  enum BranchPredicate {
49  INVALID_BR = 0,
50  SCC_TRUE = 1,
51  SCC_FALSE = -1,
52  VCCNZ = 2,
53  VCCZ = -2,
54  EXECNZ = -3,
55  EXECZ = 3
56  };
57 
59 
60  static unsigned getBranchOpcode(BranchPredicate Cond);
61  static BranchPredicate getBranchPredicate(unsigned Opcode);
62 
63 public:
66  MachineOperand &SuperReg,
67  const TargetRegisterClass *SuperRC,
68  unsigned SubIdx,
69  const TargetRegisterClass *SubRC) const;
72  MachineOperand &SuperReg,
73  const TargetRegisterClass *SuperRC,
74  unsigned SubIdx,
75  const TargetRegisterClass *SubRC) const;
76 private:
77  void swapOperands(MachineInstr &Inst) const;
78 
79  void lowerScalarAbs(SetVectorType &Worklist,
80  MachineInstr &Inst) const;
81 
82  void lowerScalarXnor(SetVectorType &Worklist,
83  MachineInstr &Inst) const;
84 
85  void splitScalar64BitUnaryOp(SetVectorType &Worklist,
86  MachineInstr &Inst, unsigned Opcode) const;
87 
88  void splitScalar64BitAddSub(SetVectorType &Worklist,
89  MachineInstr &Inst) const;
90 
91  void splitScalar64BitBinaryOp(SetVectorType &Worklist,
92  MachineInstr &Inst, unsigned Opcode) const;
93 
94  void splitScalar64BitBCNT(SetVectorType &Worklist,
95  MachineInstr &Inst) const;
96  void splitScalar64BitBFE(SetVectorType &Worklist,
97  MachineInstr &Inst) const;
98  void movePackToVALU(SetVectorType &Worklist,
100  MachineInstr &Inst) const;
101 
102  void addUsersToMoveToVALUWorklist(unsigned Reg, MachineRegisterInfo &MRI,
103  SetVectorType &Worklist) const;
104 
105  void
106  addSCCDefUsersToVALUWorklist(MachineInstr &SCCDefInst,
107  SetVectorType &Worklist) const;
108 
109  const TargetRegisterClass *
110  getDestEquivalentVGPRClass(const MachineInstr &Inst) const;
111 
112  bool checkInstOffsetsDoNotOverlap(MachineInstr &MIa, MachineInstr &MIb) const;
113 
114  unsigned findUsedSGPR(const MachineInstr &MI, int OpIndices[3]) const;
115 
116 protected:
118  MachineOperand &Src0, unsigned Src0OpName,
119  MachineOperand &Src1, unsigned Src1OpName) const;
120 
122  unsigned OpIdx0,
123  unsigned OpIdx1) const override;
124 
125 public:
127  MO_MASK = 0x7,
128 
129  MO_NONE = 0,
130  // MO_GOTPCREL -> symbol@GOTPCREL -> R_AMDGPU_GOTPCREL.
132  // MO_GOTPCREL32_LO -> symbol@gotpcrel32@lo -> R_AMDGPU_GOTPCREL32_LO.
135  // MO_GOTPCREL32_HI -> symbol@gotpcrel32@hi -> R_AMDGPU_GOTPCREL32_HI.
137  // MO_REL32_LO -> symbol@rel32@lo -> R_AMDGPU_REL32_LO.
138  MO_REL32 = 4,
140  // MO_REL32_HI -> symbol@rel32@hi -> R_AMDGPU_REL32_HI.
142  };
143 
144  explicit SIInstrInfo(const SISubtarget &ST);
145 
147  return RI;
148  }
149 
151  AliasAnalysis *AA) const override;
152 
153  bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
154  int64_t &Offset1,
155  int64_t &Offset2) const override;
156 
157  bool getMemOpBaseRegImmOfs(MachineInstr &LdSt, unsigned &BaseReg,
158  int64_t &Offset,
159  const TargetRegisterInfo *TRI) const final;
160 
161  bool shouldClusterMemOps(MachineInstr &FirstLdSt, unsigned BaseReg1,
162  MachineInstr &SecondLdSt, unsigned BaseReg2,
163  unsigned NumLoads) const final;
164 
166  const DebugLoc &DL, unsigned DestReg, unsigned SrcReg,
167  bool KillSrc) const override;
168 
170  RegScavenger *RS, unsigned TmpReg,
171  unsigned Offset, unsigned Size) const;
172 
175  const DebugLoc &DL,
176  unsigned DestReg,
177  int64_t Value) const;
178 
180  unsigned Size) const;
181 
182  unsigned insertNE(MachineBasicBlock *MBB,
184  unsigned SrcReg, int Value) const;
185 
186  unsigned insertEQ(MachineBasicBlock *MBB,
188  unsigned SrcReg, int Value) const;
189 
191  MachineBasicBlock::iterator MI, unsigned SrcReg,
192  bool isKill, int FrameIndex,
193  const TargetRegisterClass *RC,
194  const TargetRegisterInfo *TRI) const override;
195 
197  MachineBasicBlock::iterator MI, unsigned DestReg,
198  int FrameIndex, const TargetRegisterClass *RC,
199  const TargetRegisterInfo *TRI) const override;
200 
201  bool expandPostRAPseudo(MachineInstr &MI) const override;
202 
203  // \brief Returns an opcode that can be used to move a value to a \p DstRC
204  // register. If there is no hardware instruction that can store to \p
205  // DstRC, then AMDGPU::COPY is returned.
206  unsigned getMovOpcode(const TargetRegisterClass *DstRC) const;
207 
209  int commuteOpcode(unsigned Opc) const;
210 
212  inline int commuteOpcode(const MachineInstr &MI) const {
213  return commuteOpcode(MI.getOpcode());
214  }
215 
216  bool findCommutedOpIndices(MachineInstr &MI, unsigned &SrcOpIdx1,
217  unsigned &SrcOpIdx2) const override;
218 
219  bool isBranchOffsetInRange(unsigned BranchOpc,
220  int64_t BrOffset) const override;
221 
222  MachineBasicBlock *getBranchDestBlock(const MachineInstr &MI) const override;
223 
225  MachineBasicBlock &NewDestBB,
226  const DebugLoc &DL,
227  int64_t BrOffset,
228  RegScavenger *RS = nullptr) const override;
229 
232  MachineBasicBlock *&TBB,
233  MachineBasicBlock *&FBB,
235  bool AllowModify) const;
236 
238  MachineBasicBlock *&FBB,
240  bool AllowModify = false) const override;
241 
242  unsigned removeBranch(MachineBasicBlock &MBB,
243  int *BytesRemoved = nullptr) const override;
244 
247  const DebugLoc &DL,
248  int *BytesAdded = nullptr) const override;
249 
251  SmallVectorImpl<MachineOperand> &Cond) const override;
252 
253  bool canInsertSelect(const MachineBasicBlock &MBB,
255  unsigned TrueReg, unsigned FalseReg,
256  int &CondCycles,
257  int &TrueCycles, int &FalseCycles) const override;
258 
261  unsigned DstReg, ArrayRef<MachineOperand> Cond,
262  unsigned TrueReg, unsigned FalseReg) const override;
263 
266  unsigned DstReg, ArrayRef<MachineOperand> Cond,
267  unsigned TrueReg, unsigned FalseReg) const;
268 
270  PseudoSourceValue::PSVKind Kind) const override;
271 
272  bool
274  AliasAnalysis *AA = nullptr) const override;
275 
276  bool isFoldableCopy(const MachineInstr &MI) const;
277 
278  bool FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, unsigned Reg,
279  MachineRegisterInfo *MRI) const final;
280 
281  unsigned getMachineCSELookAheadLimit() const override { return 500; }
282 
284  MachineInstr &MI,
285  LiveVariables *LV) const override;
286 
287  bool isSchedulingBoundary(const MachineInstr &MI,
288  const MachineBasicBlock *MBB,
289  const MachineFunction &MF) const override;
290 
291  static bool isSALU(const MachineInstr &MI) {
292  return MI.getDesc().TSFlags & SIInstrFlags::SALU;
293  }
294 
295  bool isSALU(uint16_t Opcode) const {
296  return get(Opcode).TSFlags & SIInstrFlags::SALU;
297  }
298 
299  static bool isVALU(const MachineInstr &MI) {
300  return MI.getDesc().TSFlags & SIInstrFlags::VALU;
301  }
302 
303  bool isVALU(uint16_t Opcode) const {
304  return get(Opcode).TSFlags & SIInstrFlags::VALU;
305  }
306 
307  static bool isVMEM(const MachineInstr &MI) {
308  return isMUBUF(MI) || isMTBUF(MI) || isMIMG(MI);
309  }
310 
311  bool isVMEM(uint16_t Opcode) const {
312  return isMUBUF(Opcode) || isMTBUF(Opcode) || isMIMG(Opcode);
313  }
314 
315  static bool isSOP1(const MachineInstr &MI) {
316  return MI.getDesc().TSFlags & SIInstrFlags::SOP1;
317  }
318 
319  bool isSOP1(uint16_t Opcode) const {
320  return get(Opcode).TSFlags & SIInstrFlags::SOP1;
321  }
322 
323  static bool isSOP2(const MachineInstr &MI) {
324  return MI.getDesc().TSFlags & SIInstrFlags::SOP2;
325  }
326 
327  bool isSOP2(uint16_t Opcode) const {
328  return get(Opcode).TSFlags & SIInstrFlags::SOP2;
329  }
330 
331  static bool isSOPC(const MachineInstr &MI) {
332  return MI.getDesc().TSFlags & SIInstrFlags::SOPC;
333  }
334 
335  bool isSOPC(uint16_t Opcode) const {
336  return get(Opcode).TSFlags & SIInstrFlags::SOPC;
337  }
338 
339  static bool isSOPK(const MachineInstr &MI) {
340  return MI.getDesc().TSFlags & SIInstrFlags::SOPK;
341  }
342 
343  bool isSOPK(uint16_t Opcode) const {
344  return get(Opcode).TSFlags & SIInstrFlags::SOPK;
345  }
346 
347  static bool isSOPP(const MachineInstr &MI) {
348  return MI.getDesc().TSFlags & SIInstrFlags::SOPP;
349  }
350 
351  bool isSOPP(uint16_t Opcode) const {
352  return get(Opcode).TSFlags & SIInstrFlags::SOPP;
353  }
354 
355  static bool isVOP1(const MachineInstr &MI) {
356  return MI.getDesc().TSFlags & SIInstrFlags::VOP1;
357  }
358 
359  bool isVOP1(uint16_t Opcode) const {
360  return get(Opcode).TSFlags & SIInstrFlags::VOP1;
361  }
362 
363  static bool isVOP2(const MachineInstr &MI) {
364  return MI.getDesc().TSFlags & SIInstrFlags::VOP2;
365  }
366 
367  bool isVOP2(uint16_t Opcode) const {
368  return get(Opcode).TSFlags & SIInstrFlags::VOP2;
369  }
370 
371  static bool isVOP3(const MachineInstr &MI) {
372  return MI.getDesc().TSFlags & SIInstrFlags::VOP3;
373  }
374 
375  bool isVOP3(uint16_t Opcode) const {
376  return get(Opcode).TSFlags & SIInstrFlags::VOP3;
377  }
378 
379  static bool isSDWA(const MachineInstr &MI) {
380  return MI.getDesc().TSFlags & SIInstrFlags::SDWA;
381  }
382 
383  bool isSDWA(uint16_t Opcode) const {
384  return get(Opcode).TSFlags & SIInstrFlags::SDWA;
385  }
386 
387  static bool isVOPC(const MachineInstr &MI) {
388  return MI.getDesc().TSFlags & SIInstrFlags::VOPC;
389  }
390 
391  bool isVOPC(uint16_t Opcode) const {
392  return get(Opcode).TSFlags & SIInstrFlags::VOPC;
393  }
394 
395  static bool isMUBUF(const MachineInstr &MI) {
396  return MI.getDesc().TSFlags & SIInstrFlags::MUBUF;
397  }
398 
399  bool isMUBUF(uint16_t Opcode) const {
400  return get(Opcode).TSFlags & SIInstrFlags::MUBUF;
401  }
402 
403  static bool isMTBUF(const MachineInstr &MI) {
404  return MI.getDesc().TSFlags & SIInstrFlags::MTBUF;
405  }
406 
407  bool isMTBUF(uint16_t Opcode) const {
408  return get(Opcode).TSFlags & SIInstrFlags::MTBUF;
409  }
410 
411  static bool isSMRD(const MachineInstr &MI) {
412  return MI.getDesc().TSFlags & SIInstrFlags::SMRD;
413  }
414 
415  bool isSMRD(uint16_t Opcode) const {
416  return get(Opcode).TSFlags & SIInstrFlags::SMRD;
417  }
418 
419  bool isBufferSMRD(const MachineInstr &MI) const {
420  if (!isSMRD(MI))
421  return false;
422 
423  // Check that it is using a buffer resource.
424  int Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::sbase);
425  if (Idx == -1) // e.g. s_memtime
426  return false;
427 
428  const auto RCID = MI.getDesc().OpInfo[Idx].RegClass;
429  return RCID == AMDGPU::SReg_128RegClassID;
430  }
431 
432  static bool isDS(const MachineInstr &MI) {
433  return MI.getDesc().TSFlags & SIInstrFlags::DS;
434  }
435 
436  bool isDS(uint16_t Opcode) const {
437  return get(Opcode).TSFlags & SIInstrFlags::DS;
438  }
439 
440  static bool isMIMG(const MachineInstr &MI) {
441  return MI.getDesc().TSFlags & SIInstrFlags::MIMG;
442  }
443 
444  bool isMIMG(uint16_t Opcode) const {
445  return get(Opcode).TSFlags & SIInstrFlags::MIMG;
446  }
447 
448  static bool isGather4(const MachineInstr &MI) {
449  return MI.getDesc().TSFlags & SIInstrFlags::Gather4;
450  }
451 
452  bool isGather4(uint16_t Opcode) const {
453  return get(Opcode).TSFlags & SIInstrFlags::Gather4;
454  }
455 
456  static bool isFLAT(const MachineInstr &MI) {
457  return MI.getDesc().TSFlags & SIInstrFlags::FLAT;
458  }
459 
460  // Is a FLAT encoded instruction which accesses a specific segment,
461  // i.e. global_* or scratch_*.
462  static bool isSegmentSpecificFLAT(const MachineInstr &MI) {
463  auto Flags = MI.getDesc().TSFlags;
464  return (Flags & SIInstrFlags::FLAT) && !(Flags & SIInstrFlags::LGKM_CNT);
465  }
466 
467  // Any FLAT encoded instruction, including global_* and scratch_*.
468  bool isFLAT(uint16_t Opcode) const {
469  return get(Opcode).TSFlags & SIInstrFlags::FLAT;
470  }
471 
472  static bool isEXP(const MachineInstr &MI) {
473  return MI.getDesc().TSFlags & SIInstrFlags::EXP;
474  }
475 
476  bool isEXP(uint16_t Opcode) const {
477  return get(Opcode).TSFlags & SIInstrFlags::EXP;
478  }
479 
480  static bool isWQM(const MachineInstr &MI) {
481  return MI.getDesc().TSFlags & SIInstrFlags::WQM;
482  }
483 
484  bool isWQM(uint16_t Opcode) const {
485  return get(Opcode).TSFlags & SIInstrFlags::WQM;
486  }
487 
488  static bool isDisableWQM(const MachineInstr &MI) {
490  }
491 
492  bool isDisableWQM(uint16_t Opcode) const {
493  return get(Opcode).TSFlags & SIInstrFlags::DisableWQM;
494  }
495 
496  static bool isVGPRSpill(const MachineInstr &MI) {
498  }
499 
500  bool isVGPRSpill(uint16_t Opcode) const {
501  return get(Opcode).TSFlags & SIInstrFlags::VGPRSpill;
502  }
503 
504  static bool isSGPRSpill(const MachineInstr &MI) {
506  }
507 
508  bool isSGPRSpill(uint16_t Opcode) const {
509  return get(Opcode).TSFlags & SIInstrFlags::SGPRSpill;
510  }
511 
512  static bool isDPP(const MachineInstr &MI) {
513  return MI.getDesc().TSFlags & SIInstrFlags::DPP;
514  }
515 
516  bool isDPP(uint16_t Opcode) const {
517  return get(Opcode).TSFlags & SIInstrFlags::DPP;
518  }
519 
520  static bool isVOP3P(const MachineInstr &MI) {
521  return MI.getDesc().TSFlags & SIInstrFlags::VOP3P;
522  }
523 
524  bool isVOP3P(uint16_t Opcode) const {
525  return get(Opcode).TSFlags & SIInstrFlags::VOP3P;
526  }
527 
528  static bool isVINTRP(const MachineInstr &MI) {
529  return MI.getDesc().TSFlags & SIInstrFlags::VINTRP;
530  }
531 
532  bool isVINTRP(uint16_t Opcode) const {
533  return get(Opcode).TSFlags & SIInstrFlags::VINTRP;
534  }
535 
536  static bool isScalarUnit(const MachineInstr &MI) {
538  }
539 
540  static bool usesVM_CNT(const MachineInstr &MI) {
541  return MI.getDesc().TSFlags & SIInstrFlags::VM_CNT;
542  }
543 
544  static bool usesLGKM_CNT(const MachineInstr &MI) {
545  return MI.getDesc().TSFlags & SIInstrFlags::LGKM_CNT;
546  }
547 
548  static bool sopkIsZext(const MachineInstr &MI) {
550  }
551 
552  bool sopkIsZext(uint16_t Opcode) const {
553  return get(Opcode).TSFlags & SIInstrFlags::SOPK_ZEXT;
554  }
555 
556  /// \returns true if this is an s_store_dword* instruction. This is more
557  /// specific than than isSMEM && mayStore.
558  static bool isScalarStore(const MachineInstr &MI) {
560  }
561 
562  bool isScalarStore(uint16_t Opcode) const {
563  return get(Opcode).TSFlags & SIInstrFlags::SCALAR_STORE;
564  }
565 
566  static bool isFixedSize(const MachineInstr &MI) {
568  }
569 
570  bool isFixedSize(uint16_t Opcode) const {
571  return get(Opcode).TSFlags & SIInstrFlags::FIXED_SIZE;
572  }
573 
574  static bool hasFPClamp(const MachineInstr &MI) {
575  return MI.getDesc().TSFlags & SIInstrFlags::FPClamp;
576  }
577 
578  bool hasFPClamp(uint16_t Opcode) const {
579  return get(Opcode).TSFlags & SIInstrFlags::FPClamp;
580  }
581 
582  static bool hasIntClamp(const MachineInstr &MI) {
583  return MI.getDesc().TSFlags & SIInstrFlags::IntClamp;
584  }
585 
586  uint64_t getClampMask(const MachineInstr &MI) const {
587  const uint64_t ClampFlags = SIInstrFlags::FPClamp |
591  return MI.getDesc().TSFlags & ClampFlags;
592  }
593 
594  bool isVGPRCopy(const MachineInstr &MI) const {
595  assert(MI.isCopy());
596  unsigned Dest = MI.getOperand(0).getReg();
597  const MachineFunction &MF = *MI.getParent()->getParent();
598  const MachineRegisterInfo &MRI = MF.getRegInfo();
599  return !RI.isSGPRReg(MRI, Dest);
600  }
601 
602  bool isInlineConstant(const APInt &Imm) const;
603 
604  bool isInlineConstant(const MachineOperand &MO, uint8_t OperandType) const;
605 
607  const MCOperandInfo &OpInfo) const {
608  return isInlineConstant(MO, OpInfo.OperandType);
609  }
610 
611  /// \p returns true if \p UseMO is substituted with \p DefMO in \p MI it would
612  /// be an inline immediate.
614  const MachineOperand &UseMO,
615  const MachineOperand &DefMO) const {
616  assert(UseMO.getParent() == &MI);
617  int OpIdx = MI.getOperandNo(&UseMO);
618  if (!MI.getDesc().OpInfo || OpIdx >= MI.getDesc().NumOperands) {
619  return false;
620  }
621 
622  return isInlineConstant(DefMO, MI.getDesc().OpInfo[OpIdx]);
623  }
624 
625  /// \p returns true if the operand \p OpIdx in \p MI is a valid inline
626  /// immediate.
627  bool isInlineConstant(const MachineInstr &MI, unsigned OpIdx) const {
628  const MachineOperand &MO = MI.getOperand(OpIdx);
629  return isInlineConstant(MO, MI.getDesc().OpInfo[OpIdx].OperandType);
630  }
631 
632  bool isInlineConstant(const MachineInstr &MI, unsigned OpIdx,
633  const MachineOperand &MO) const {
634  if (!MI.getDesc().OpInfo || OpIdx >= MI.getDesc().NumOperands)
635  return false;
636 
637  if (MI.isCopy()) {
638  unsigned Size = getOpSize(MI, OpIdx);
639  assert(Size == 8 || Size == 4);
640 
641  uint8_t OpType = (Size == 8) ?
643  return isInlineConstant(MO, OpType);
644  }
645 
646  return isInlineConstant(MO, MI.getDesc().OpInfo[OpIdx].OperandType);
647  }
648 
649  bool isInlineConstant(const MachineOperand &MO) const {
650  const MachineInstr *Parent = MO.getParent();
651  return isInlineConstant(*Parent, Parent->getOperandNo(&MO));
652  }
653 
655  const MCOperandInfo &OpInfo) const {
656  return MO.isImm() && !isInlineConstant(MO, OpInfo.OperandType);
657  }
658 
659  bool isLiteralConstant(const MachineInstr &MI, int OpIdx) const {
660  const MachineOperand &MO = MI.getOperand(OpIdx);
661  return MO.isImm() && !isInlineConstant(MI, OpIdx);
662  }
663 
664  // Returns true if this operand could potentially require a 32-bit literal
665  // operand, but not necessarily. A FrameIndex for example could resolve to an
666  // inline immediate value that will not require an additional 4-bytes; this
667  // assumes that it will.
668  bool isLiteralConstantLike(const MachineOperand &MO,
669  const MCOperandInfo &OpInfo) const;
670 
671  bool isImmOperandLegal(const MachineInstr &MI, unsigned OpNo,
672  const MachineOperand &MO) const;
673 
674  /// \brief Return true if this 64-bit VALU instruction has a 32-bit encoding.
675  /// This function will return false if you pass it a 32-bit instruction.
676  bool hasVALU32BitEncoding(unsigned Opcode) const;
677 
678  /// \brief Returns true if this operand uses the constant bus.
679  bool usesConstantBus(const MachineRegisterInfo &MRI,
680  const MachineOperand &MO,
681  const MCOperandInfo &OpInfo) const;
682 
683  /// \brief Return true if this instruction has any modifiers.
684  /// e.g. src[012]_mod, omod, clamp.
685  bool hasModifiers(unsigned Opcode) const;
686 
687  bool hasModifiersSet(const MachineInstr &MI,
688  unsigned OpName) const;
689  bool hasAnyModifiersSet(const MachineInstr &MI) const;
690 
691  bool verifyInstruction(const MachineInstr &MI,
692  StringRef &ErrInfo) const override;
693 
694  static unsigned getVALUOp(const MachineInstr &MI);
695 
696  bool isSALUOpSupportedOnVALU(const MachineInstr &MI) const;
697 
698  /// \brief Return the correct register class for \p OpNo. For target-specific
699  /// instructions, this will return the register class that has been defined
700  /// in tablegen. For generic instructions, like REG_SEQUENCE it will return
701  /// the register class of its machine operand.
702  /// to infer the correct register class base on the other operands.
704  unsigned OpNo) const;
705 
706  /// \brief Return the size in bytes of the operand OpNo on the given
707  // instruction opcode.
708  unsigned getOpSize(uint16_t Opcode, unsigned OpNo) const {
709  const MCOperandInfo &OpInfo = get(Opcode).OpInfo[OpNo];
710 
711  if (OpInfo.RegClass == -1) {
712  // If this is an immediate operand, this must be a 32-bit literal.
714  return 4;
715  }
716 
717  return RI.getRegSizeInBits(*RI.getRegClass(OpInfo.RegClass)) / 8;
718  }
719 
720  /// \brief This form should usually be preferred since it handles operands
721  /// with unknown register classes.
722  unsigned getOpSize(const MachineInstr &MI, unsigned OpNo) const {
723  return RI.getRegSizeInBits(*getOpRegClass(MI, OpNo)) / 8;
724  }
725 
726  /// \returns true if it is legal for the operand at index \p OpNo
727  /// to read a VGPR.
728  bool canReadVGPR(const MachineInstr &MI, unsigned OpNo) const;
729 
730  /// \brief Legalize the \p OpIndex operand of this instruction by inserting
731  /// a MOV. For example:
732  /// ADD_I32_e32 VGPR0, 15
733  /// to
734  /// MOV VGPR1, 15
735  /// ADD_I32_e32 VGPR0, VGPR1
736  ///
737  /// If the operand being legalized is a register, then a COPY will be used
738  /// instead of MOV.
739  void legalizeOpWithMove(MachineInstr &MI, unsigned OpIdx) const;
740 
741  /// \brief Check if \p MO is a legal operand if it was the \p OpIdx Operand
742  /// for \p MI.
743  bool isOperandLegal(const MachineInstr &MI, unsigned OpIdx,
744  const MachineOperand *MO = nullptr) const;
745 
746  /// \brief Check if \p MO would be a valid operand for the given operand
747  /// definition \p OpInfo. Note this does not attempt to validate constant bus
748  /// restrictions (e.g. literal constant usage).
749  bool isLegalVSrcOperand(const MachineRegisterInfo &MRI,
750  const MCOperandInfo &OpInfo,
751  const MachineOperand &MO) const;
752 
753  /// \brief Check if \p MO (a register operand) is a legal register for the
754  /// given operand description.
755  bool isLegalRegOperand(const MachineRegisterInfo &MRI,
756  const MCOperandInfo &OpInfo,
757  const MachineOperand &MO) const;
758 
759  /// \brief Legalize operands in \p MI by either commuting it or inserting a
760  /// copy of src1.
762 
763  /// \brief Fix operands in \p MI to satisfy constant bus requirements.
765 
766  /// Copy a value from a VGPR (\p SrcReg) to SGPR. This function can only
767  /// be used when it is know that the value in SrcReg is same across all
768  /// threads in the wave.
769  /// \returns The SGPR register that \p SrcReg was copied to.
770  unsigned readlaneVGPRToSGPR(unsigned SrcReg, MachineInstr &UseMI,
771  MachineRegisterInfo &MRI) const;
772 
774 
777  const TargetRegisterClass *DstRC,
779  const DebugLoc &DL) const;
780 
781  /// \brief Legalize all operands in this instruction. This function may
782  /// create new instruction and insert them before \p MI.
783  void legalizeOperands(MachineInstr &MI) const;
784 
785  /// \brief Replace this instruction's opcode with the equivalent VALU
786  /// opcode. This function will also move the users of \p MI to the
787  /// VALU if necessary.
788  void moveToVALU(MachineInstr &MI) const;
789 
791  int Count) const;
792 
793  void insertNoop(MachineBasicBlock &MBB,
794  MachineBasicBlock::iterator MI) const override;
795 
796  void insertReturn(MachineBasicBlock &MBB) const;
797  /// \brief Return the number of wait states that result from executing this
798  /// instruction.
799  unsigned getNumWaitStates(const MachineInstr &MI) const;
800 
801  /// \brief Returns the operand named \p Op. If \p MI does not have an
802  /// operand named \c Op, this function returns nullptr.
804  MachineOperand *getNamedOperand(MachineInstr &MI, unsigned OperandName) const;
805 
808  unsigned OpName) const {
809  return getNamedOperand(const_cast<MachineInstr &>(MI), OpName);
810  }
811 
812  /// Get required immediate operand
813  int64_t getNamedImmOperand(const MachineInstr &MI, unsigned OpName) const {
814  int Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), OpName);
815  return MI.getOperand(Idx).getImm();
816  }
817 
818  uint64_t getDefaultRsrcDataFormat() const;
819  uint64_t getScratchRsrcWords23() const;
820 
821  bool isLowLatencyInstruction(const MachineInstr &MI) const;
822  bool isHighLatencyInstruction(const MachineInstr &MI) const;
823 
824  /// \brief Return the descriptor of the target-specific machine instruction
825  /// that corresponds to the specified pseudo or native opcode.
826  const MCInstrDesc &getMCOpcodeFromPseudo(unsigned Opcode) const {
827  return get(pseudoToMCOpcode(Opcode));
828  }
829 
830  unsigned isStackAccess(const MachineInstr &MI, int &FrameIndex) const;
831  unsigned isSGPRStackAccess(const MachineInstr &MI, int &FrameIndex) const;
832 
833  unsigned isLoadFromStackSlot(const MachineInstr &MI,
834  int &FrameIndex) const override;
835  unsigned isStoreToStackSlot(const MachineInstr &MI,
836  int &FrameIndex) const override;
837 
838  unsigned getInstBundleSize(const MachineInstr &MI) const;
839  unsigned getInstSizeInBytes(const MachineInstr &MI) const override;
840 
841  bool mayAccessFlatAddressSpace(const MachineInstr &MI) const;
842 
843  bool isNonUniformBranchInstr(MachineInstr &Instr) const;
844 
846  MachineBasicBlock *IfEnd) const;
847 
849  MachineBasicBlock *LoopEnd) const;
850 
851  std::pair<unsigned, unsigned>
852  decomposeMachineOperandsTargetFlags(unsigned TF) const override;
853 
855  getSerializableTargetIndices() const override;
856 
859 
862  const ScheduleDAG *DAG) const override;
863 
865  CreateTargetPostRAHazardRecognizer(const MachineFunction &MF) const override;
866 
867  bool isBasicBlockPrologue(const MachineInstr &MI) const override;
868 
869  /// \brief Return a partially built integer add instruction without carry.
870  /// Caller must add source operands.
871  /// For pre-GFX9 it will generate unused carry destination operand.
872  /// TODO: After GFX9 it should return a no-carry operation.
875  const DebugLoc &DL,
876  unsigned DestReg) const;
877 
878  static bool isKillTerminator(unsigned Opcode);
879  const MCInstrDesc &getKillTerminatorFromPseudo(unsigned Opcode) const;
880 
881  static bool isLegalMUBUFImmOffset(unsigned Imm) {
882  return isUInt<12>(Imm);
883  }
884 };
885 
886 namespace AMDGPU {
887 
889  int getVOPe64(uint16_t Opcode);
890 
892  int getVOPe32(uint16_t Opcode);
893 
895  int getSDWAOp(uint16_t Opcode);
896 
898  int getBasicFromSDWAOp(uint16_t Opcode);
899 
901  int getCommuteRev(uint16_t Opcode);
902 
904  int getCommuteOrig(uint16_t Opcode);
905 
907  int getAddr64Inst(uint16_t Opcode);
908 
910  int getAtomicRetOp(uint16_t Opcode);
911 
913  int getAtomicNoRetOp(uint16_t Opcode);
914 
916  int getSOPKOp(uint16_t Opcode);
917 
918  const uint64_t RSRC_DATA_FORMAT = 0xf00000000000LL;
919  const uint64_t RSRC_ELEMENT_SIZE_SHIFT = (32 + 19);
920  const uint64_t RSRC_INDEX_STRIDE_SHIFT = (32 + 21);
921  const uint64_t RSRC_TID_ENABLE = UINT64_C(1) << (32 + 23);
922 
923  // For MachineOperands.
924  enum TargetFlags {
927  };
928 
929 } // end namespace AMDGPU
930 
931 namespace SI {
932 namespace KernelInputOffsets {
933 
934 /// Offsets in bytes from the start of the input buffer
935 enum Offsets {
945 };
946 
947 } // end namespace KernelInputOffsets
948 } // end namespace SI
949 
950 } // end namespace llvm
951 
952 #endif // LLVM_LIB_TARGET_AMDGPU_SIINSTRINFO_H
bool isFLAT(uint16_t Opcode) const
Definition: SIInstrInfo.h:468
bool isLegalRegOperand(const MachineRegisterInfo &MRI, const MCOperandInfo &OpInfo, const MachineOperand &MO) const
Check if MO (a register operand) is a legal register for the given operand description.
unsigned buildExtractSubReg(MachineBasicBlock::iterator MI, MachineRegisterInfo &MRI, MachineOperand &SuperReg, const TargetRegisterClass *SuperRC, unsigned SubIdx, const TargetRegisterClass *SubRC) const
bool analyzeBranchImpl(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const
void legalizeOperands(MachineInstr &MI) const
Legalize all operands in this instruction.
static bool isSGPRSpill(const MachineInstr &MI)
Definition: SIInstrInfo.h:504
Interface definition for SIRegisterInfo.
bool sopkIsZext(uint16_t Opcode) const
Definition: SIInstrInfo.h:552
void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, unsigned DstReg, ArrayRef< MachineOperand > Cond, unsigned TrueReg, unsigned FalseReg) const override
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
bool canReadVGPR(const MachineInstr &MI, unsigned OpNo) const
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify=false) const override
bool isVGPRCopy(const MachineInstr &MI) const
Definition: SIInstrInfo.h:594
int pseudoToMCOpcode(int Opcode) const
Return a target-specific opcode if Opcode is a pseudo instruction.
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
static bool isScalarStore(const MachineInstr &MI)
Definition: SIInstrInfo.h:558
static bool sopkIsZext(const MachineInstr &MI)
Definition: SIInstrInfo.h:548
uint64_t getDefaultRsrcDataFormat() const
bool isOperandLegal(const MachineInstr &MI, unsigned OpIdx, const MachineOperand *MO=nullptr) const
Check if MO is a legal operand if it was the OpIdx Operand for MI.
bool isSOPK(uint16_t Opcode) const
Definition: SIInstrInfo.h:343
bool canInsertSelect(const MachineBasicBlock &MBB, ArrayRef< MachineOperand > Cond, unsigned TrueReg, unsigned FalseReg, int &CondCycles, int &TrueCycles, int &FalseCycles) const override
bool usesConstantBus(const MachineRegisterInfo &MRI, const MachineOperand &MO, const MCOperandInfo &OpInfo) const
Returns true if this operand uses the constant bus.
bool mayAccessFlatAddressSpace(const MachineInstr &MI) const
unsigned calculateLDSSpillAddress(MachineBasicBlock &MBB, MachineInstr &MI, RegScavenger *RS, unsigned TmpReg, unsigned Offset, unsigned Size) const
bool hasModifiersSet(const MachineInstr &MI, unsigned OpName) const
const TargetRegisterClass * getOpRegClass(const MachineInstr &MI, unsigned OpNo) const
Return the correct register class for OpNo.
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:163
unsigned getReg() const
getReg - Returns the register number.
static bool isVINTRP(const MachineInstr &MI)
Definition: SIInstrInfo.h:528
unsigned getOperandNo(const_mop_iterator I) const
Returns the number of the operand iterator I points to.
Definition: MachineInstr.h:384
unsigned insertNE(MachineBasicBlock *MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, unsigned SrcReg, int Value) const
unsigned isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override
static bool isSOPK(const MachineInstr &MI)
Definition: SIInstrInfo.h:339
void legalizeOperandsVOP2(MachineRegisterInfo &MRI, MachineInstr &MI) const
Legalize operands in MI by either commuting it or inserting a copy of src1.
unsigned isSGPRStackAccess(const MachineInstr &MI, int &FrameIndex) const
Offsets
Offsets in bytes from the start of the input buffer.
Definition: SIInstrInfo.h:935
bool isMIMG(uint16_t Opcode) const
Definition: SIInstrInfo.h:444
int64_t getNamedImmOperand(const MachineInstr &MI, unsigned OpName) const
Get required immediate operand.
Definition: SIInstrInfo.h:813
A debug info location.
Definition: DebugLoc.h:34
bool isSALUOpSupportedOnVALU(const MachineInstr &MI) const
bool isDPP(uint16_t Opcode) const
Definition: SIInstrInfo.h:516
bool isGather4(uint16_t Opcode) const
Definition: SIInstrInfo.h:452
static bool isSOPP(const MachineInstr &MI)
Definition: SIInstrInfo.h:347
LLVM_READONLY int getAtomicNoRetOp(uint16_t Opcode)
bool isInlineConstant(const APInt &Imm) const
bool isMUBUF(uint16_t Opcode) const
Definition: SIInstrInfo.h:399
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const override
static bool isSOPC(const MachineInstr &MI)
Definition: SIInstrInfo.h:331
bool hasAnyModifiersSet(const MachineInstr &MI) const
static bool isSMRD(const MachineInstr &MI)
Definition: SIInstrInfo.h:411
const SIRegisterInfo & getRegisterInfo() const
Definition: SIInstrInfo.h:146
LLVM_READONLY int getVOPe64(uint16_t Opcode)
static bool isFixedSize(const MachineInstr &MI)
Definition: SIInstrInfo.h:566
LLVM_READONLY int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx)
bool verifyInstruction(const MachineInstr &MI, StringRef &ErrInfo) const override
static bool isDS(const MachineInstr &MI)
Definition: SIInstrInfo.h:432
bool isEXP(uint16_t Opcode) const
Definition: SIInstrInfo.h:476
bool isSOPP(uint16_t Opcode) const
Definition: SIInstrInfo.h:351
std::pair< unsigned, unsigned > decomposeMachineOperandsTargetFlags(unsigned TF) const override
LLVM_READONLY int getAtomicRetOp(uint16_t Opcode)
static bool isFLAT(const MachineInstr &MI)
Definition: SIInstrInfo.h:456
unsigned getInstSizeInBytes(const MachineInstr &MI) const override
uint64_t getScratchRsrcWords23() const
bool isSGPRReg(const MachineRegisterInfo &MRI, unsigned Reg) const
static bool isGather4(const MachineInstr &MI)
Definition: SIInstrInfo.h:448
static bool isMIMG(const MachineInstr &MI)
Definition: SIInstrInfo.h:440
bool isVINTRP(uint16_t Opcode) const
Definition: SIInstrInfo.h:532
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
MachineOperand buildExtractSubRegOrImm(MachineBasicBlock::iterator MI, MachineRegisterInfo &MRI, MachineOperand &SuperReg, const TargetRegisterClass *SuperRC, unsigned SubIdx, const TargetRegisterClass *SubRC) const
Reg
All possible values of the reg field in the ModR/M byte.
void insertWaitStates(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, int Count) const
LLVM_READONLY int getCommuteOrig(uint16_t Opcode)
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:290
bool isLiteralConstant(const MachineInstr &MI, int OpIdx) const
Definition: SIInstrInfo.h:659
const MCInstrDesc & getMCOpcodeFromPseudo(unsigned Opcode) const
Return the descriptor of the target-specific machine instruction that corresponds to the specified ps...
Definition: SIInstrInfo.h:826
static bool isVALU(const MachineInstr &MI)
Definition: SIInstrInfo.h:299
unsigned getAddressSpaceForPseudoSourceKind(PseudoSourceValue::PSVKind Kind) const override
void legalizeOperandsVOP3(MachineRegisterInfo &MRI, MachineInstr &MI) const
Fix operands in MI to satisfy constant bus requirements.
unsigned getOpSize(uint16_t Opcode, unsigned OpNo) const
Return the size in bytes of the operand OpNo on the given.
Definition: SIInstrInfo.h:708
uint8_t OperandType
Information about the type of the operand.
Definition: MCInstrDesc.h:82
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
Definition: MachineInstr.h:287
unsigned getInstBundleSize(const MachineInstr &MI) const
static bool isMUBUF(const MachineInstr &MI)
Definition: SIInstrInfo.h:395
LLVM_READONLY MachineOperand * getNamedOperand(MachineInstr &MI, unsigned OperandName) const
Returns the operand named Op.
void convertNonUniformLoopRegion(MachineBasicBlock *LoopEntry, MachineBasicBlock *LoopEnd) const
const uint64_t RSRC_DATA_FORMAT
Definition: SIInstrInfo.h:918
MachineInstr * commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned OpIdx0, unsigned OpIdx1) const override
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:33
bool isSGPRSpill(uint16_t Opcode) const
Definition: SIInstrInfo.h:508
bool isSDWA(uint16_t Opcode) const
Definition: SIInstrInfo.h:383
Itinerary data supplied by a subtarget to be used by a target.
bool isBasicBlockPrologue(const MachineInstr &MI) const override
bool isInlineConstant(const MachineOperand &MO) const
Definition: SIInstrInfo.h:649
unsigned short NumOperands
Definition: MCInstrDesc.h:166
bool isVOP1(uint16_t Opcode) const
Definition: SIInstrInfo.h:359
LLVM_READONLY int getSDWAOp(uint16_t Opcode)
static bool isDPP(const MachineInstr &MI)
Definition: SIInstrInfo.h:512
bool isSOPC(uint16_t Opcode) const
Definition: SIInstrInfo.h:335
bool getMemOpBaseRegImmOfs(MachineInstr &LdSt, unsigned &BaseReg, int64_t &Offset, const TargetRegisterInfo *TRI) const final
bool isInlineConstant(const MachineOperand &MO, const MCOperandInfo &OpInfo) const
Definition: SIInstrInfo.h:606
unsigned const MachineRegisterInfo * MRI
const MCInstrDesc & getKillTerminatorFromPseudo(unsigned Opcode) const
bool isFoldableCopy(const MachineInstr &MI) const
static bool usesVM_CNT(const MachineInstr &MI)
Definition: SIInstrInfo.h:540
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
const TargetRegisterClass * getPreferredSelectRegClass(unsigned Size) const
SIInstrInfo(const SISubtarget &ST)
Definition: SIInstrInfo.cpp:72
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
HazardRecognizer - This determines whether or not an instruction can be issued this cycle...
MachineInstrBuilder & UseMI
bool isReallyTriviallyReMaterializable(const MachineInstr &MI, AliasAnalysis *AA) const override
bool isSchedulingBoundary(const MachineInstr &MI, const MachineBasicBlock *MBB, const MachineFunction &MF) const override
bool isInlineConstant(const MachineInstr &MI, unsigned OpIdx, const MachineOperand &MO) const
Definition: SIInstrInfo.h:632
void insertVectorSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, unsigned DstReg, ArrayRef< MachineOperand > Cond, unsigned TrueReg, unsigned FalseReg) const
static bool hasFPClamp(const MachineInstr &MI)
Definition: SIInstrInfo.h:574
bool expandPostRAPseudo(MachineInstr &MI) const override
bool isFixedSize(uint16_t Opcode) const
Definition: SIInstrInfo.h:570
void insertReturn(MachineBasicBlock &MBB) const
bool isDS(uint16_t Opcode) const
Definition: SIInstrInfo.h:436
LLVM_READONLY int commuteOpcode(unsigned Opc) const
bool isVOPC(uint16_t Opcode) const
Definition: SIInstrInfo.h:391
unsigned insertEQ(MachineBasicBlock *MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, unsigned SrcReg, int Value) const
LLVM_READONLY int getSOPKOp(uint16_t Opcode)
bool isImmOperandLegal(const MachineInstr &MI, unsigned OpNo, const MachineOperand &MO) const
bool isSOP1(uint16_t Opcode) const
Definition: SIInstrInfo.h:319
bool hasVALU32BitEncoding(unsigned Opcode) const
Return true if this 64-bit VALU instruction has a 32-bit encoding.
static bool isSOP2(const MachineInstr &MI)
Definition: SIInstrInfo.h:323
void materializeImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, unsigned DestReg, int64_t Value) const
ScheduleHazardRecognizer * CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II, const ScheduleDAG *DAG) const override
This is used by the post-RA scheduler (SchedulePostRAList.cpp).
unsigned insertIndirectBranch(MachineBasicBlock &MBB, MachineBasicBlock &NewDestBB, const DebugLoc &DL, int64_t BrOffset, RegScavenger *RS=nullptr) const override
bool isWQM(uint16_t Opcode) const
Definition: SIInstrInfo.h:484
bool hasFPClamp(uint16_t Opcode) const
Definition: SIInstrInfo.h:578
static bool isVOP2(const MachineInstr &MI)
Definition: SIInstrInfo.h:363
bool isSMRD(uint16_t Opcode) const
Definition: SIInstrInfo.h:415
bool isCopy() const
Definition: MachineInstr.h:857
unsigned isStackAccess(const MachineInstr &MI, int &FrameIndex) const
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
LLVM_READONLY int getBasicFromSDWAOp(uint16_t Opcode)
bool swapSourceModifiers(MachineInstr &MI, MachineOperand &Src0, unsigned Src0OpName, MachineOperand &Src1, unsigned Src1OpName) const
static bool isVOP3P(const MachineInstr &MI)
Definition: SIInstrInfo.h:520
bool isSOP2(uint16_t Opcode) const
Definition: SIInstrInfo.h:327
const uint64_t RSRC_TID_ENABLE
Definition: SIInstrInfo.h:921
static bool isWQM(const MachineInstr &MI)
Definition: SIInstrInfo.h:480
bool FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, unsigned Reg, MachineRegisterInfo *MRI) const final
static bool isEXP(const MachineInstr &MI)
Definition: SIInstrInfo.h:472
bool shouldClusterMemOps(MachineInstr &FirstLdSt, unsigned BaseReg1, MachineInstr &SecondLdSt, unsigned BaseReg2, unsigned NumLoads) const final
bool isScalarStore(uint16_t Opcode) const
Definition: SIInstrInfo.h:562
unsigned getNumWaitStates(const MachineInstr &MI) const
Return the number of wait states that result from executing this instruction.
bool isVOP2(uint16_t Opcode) const
Definition: SIInstrInfo.h:367
A SetVector that performs no allocations if smaller than a certain size.
Definition: SetVector.h:298
Iterator for intrusive lists based on ilist_node.
LLVM_READONLY int getVOPe32(uint16_t Opcode)
static bool isSALU(const MachineInstr &MI)
Definition: SIInstrInfo.h:291
MachineOperand class - Representation of each machine instruction operand.
bool isLiteralConstantLike(const MachineOperand &MO, const MCOperandInfo &OpInfo) const
MachineInstrBuilder MachineInstrBuilder & DefMI
uint64_t getClampMask(const MachineInstr &MI) const
Definition: SIInstrInfo.h:586
bool areMemAccessesTriviallyDisjoint(MachineInstr &MIa, MachineInstr &MIb, AliasAnalysis *AA=nullptr) const override
MachineInstrBuilder getAddNoCarry(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, unsigned DestReg) const
Return a partially built integer add instruction without carry.
bool isLegalVSrcOperand(const MachineRegisterInfo &MRI, const MCOperandInfo &OpInfo, const MachineOperand &MO) const
Check if MO would be a valid operand for the given operand definition OpInfo.
const uint64_t RSRC_INDEX_STRIDE_SHIFT
Definition: SIInstrInfo.h:920
bool isMTBUF(uint16_t Opcode) const
Definition: SIInstrInfo.h:407
Represents one node in the SelectionDAG.
int64_t getImm() const
ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags() const override
bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1, int64_t &Offset2) const override
Class for arbitrary precision integers.
Definition: APInt.h:69
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
bool isDisableWQM(uint16_t Opcode) const
Definition: SIInstrInfo.h:492
bool hasModifiers(unsigned Opcode) const
Return true if this instruction has any modifiers.
static bool isSegmentSpecificFLAT(const MachineInstr &MI)
Definition: SIInstrInfo.h:462
static bool isVOP3(const MachineInstr &MI)
Definition: SIInstrInfo.h:371
bool isLiteralConstant(const MachineOperand &MO, const MCOperandInfo &OpInfo) const
Definition: SIInstrInfo.h:654
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:139
Contains the definition of a TargetInstrInfo class that is common to all AMD GPUs.
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
bool isInlineConstant(const MachineInstr &MI, unsigned OpIdx) const
returns true if the operand OpIdx in MI is a valid inline immediate.
Definition: SIInstrInfo.h:627
Representation of each machine instruction.
Definition: MachineInstr.h:59
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
static bool isMTBUF(const MachineInstr &MI)
Definition: SIInstrInfo.h:403
OperandType
Types of operands to CF instructions.
bool isBranchOffsetInRange(unsigned BranchOpc, int64_t BrOffset) const override
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
static bool isVOPC(const MachineInstr &MI)
Definition: SIInstrInfo.h:387
int16_t RegClass
This specifies the register class enumeration of the operand if the operand is a register.
Definition: MCInstrDesc.h:76
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
#define I(x, y, z)
Definition: MD5.cpp:58
static bool isVMEM(const MachineInstr &MI)
Definition: SIInstrInfo.h:307
MachineBasicBlock * getBranchDestBlock(const MachineInstr &MI) const override
bool isHighLatencyInstruction(const MachineInstr &MI) const
LLVM_READONLY int commuteOpcode(const MachineInstr &MI) const
Definition: SIInstrInfo.h:212
bool isLowLatencyInstruction(const MachineInstr &MI) const
#define LLVM_READONLY
Definition: Compiler.h:168
bool isSALU(uint16_t Opcode) const
Definition: SIInstrInfo.h:295
ArrayRef< std::pair< int, const char * > > getSerializableTargetIndices() const override
unsigned getMovOpcode(const TargetRegisterClass *DstRC) const
bool isVMEM(uint16_t Opcode) const
Definition: SIInstrInfo.h:311
bool isVOP3P(uint16_t Opcode) const
Definition: SIInstrInfo.h:524
static unsigned getVALUOp(const MachineInstr &MI)
Operands with register or 32-bit immediate.
Definition: SIDefines.h:110
unsigned isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override
void moveToVALU(MachineInstr &MI) const
Replace this instruction&#39;s opcode with the equivalent VALU opcode.
const unsigned Kind
bool isBufferSMRD(const MachineInstr &MI) const
Definition: SIInstrInfo.h:419
bool isNonUniformBranchInstr(MachineInstr &Instr) const
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static bool isSOP1(const MachineInstr &MI)
Definition: SIInstrInfo.h:315
void legalizeOperandsSMRD(MachineRegisterInfo &MRI, MachineInstr &MI) const
static bool isLegalMUBUFImmOffset(unsigned Imm)
Definition: SIInstrInfo.h:881
const uint64_t RSRC_ELEMENT_SIZE_SHIFT
Definition: SIInstrInfo.h:919
static bool isScalarUnit(const MachineInstr &MI)
Definition: SIInstrInfo.h:536
unsigned readlaneVGPRToSGPR(unsigned SrcReg, MachineInstr &UseMI, MachineRegisterInfo &MRI) const
Copy a value from a VGPR (SrcReg) to SGPR.
static bool hasIntClamp(const MachineInstr &MI)
Definition: SIInstrInfo.h:582
LLVM Value Representation.
Definition: Value.h:73
static bool isSDWA(const MachineInstr &MI)
Definition: SIInstrInfo.h:379
void legalizeOpWithMove(MachineInstr &MI, unsigned OpIdx) const
Legalize the OpIndex operand of this instruction by inserting a MOV.
MachineInstr * convertToThreeAddress(MachineFunction::iterator &MBB, MachineInstr &MI, LiveVariables *LV) const override
constexpr char Size[]
Key for Kernel::Arg::Metadata::mSize.
static bool isVGPRSpill(const MachineInstr &MI)
Definition: SIInstrInfo.h:496
unsigned getOpSize(const MachineInstr &MI, unsigned OpNo) const
This form should usually be preferred since it handles operands with unknown register classes...
Definition: SIInstrInfo.h:722
unsigned getMachineCSELookAheadLimit() const override
Definition: SIInstrInfo.h:281
const MCOperandInfo * OpInfo
Definition: MCInstrDesc.h:174
void insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const override
IRTranslator LLVM IR MI
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:49
bool isInlineConstant(const MachineInstr &MI, const MachineOperand &UseMO, const MachineOperand &DefMO) const
returns true if UseMO is substituted with DefMO in MI it would be an inline immediate.
Definition: SIInstrInfo.h:613
void legalizeGenericOperand(MachineBasicBlock &InsertMBB, MachineBasicBlock::iterator I, const TargetRegisterClass *DstRC, MachineOperand &Op, MachineRegisterInfo &MRI, const DebugLoc &DL) const
bool isVOP3(uint16_t Opcode) const
Definition: SIInstrInfo.h:375
static bool isKillTerminator(unsigned Opcode)
LLVM_READONLY int getAddr64Inst(uint16_t Opcode)
This holds information about one operand of a machine instruction, indicating the register class for ...
Definition: MCInstrDesc.h:70
static bool usesLGKM_CNT(const MachineInstr &MI)
Definition: SIInstrInfo.h:544
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:295
static bool isVOP1(const MachineInstr &MI)
Definition: SIInstrInfo.h:355
void convertNonUniformIfRegion(MachineBasicBlock *IfEntry, MachineBasicBlock *IfEnd) const
static bool isDisableWQM(const MachineInstr &MI)
Definition: SIInstrInfo.h:488
bool findCommutedOpIndices(MachineInstr &MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) const override
bool isVALU(uint16_t Opcode) const
Definition: SIInstrInfo.h:303
LLVM_READONLY int getCommuteRev(uint16_t Opcode)
LLVM_READONLY const MachineOperand * getNamedOperand(const MachineInstr &MI, unsigned OpName) const
Definition: SIInstrInfo.h:807
bool isVGPRSpill(uint16_t Opcode) const
Definition: SIInstrInfo.h:500