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SIInstrInfo.h
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1 //===- SIInstrInfo.h - SI Instruction Info Interface ------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 /// Interface definition for SIInstrInfo.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_AMDGPU_SIINSTRINFO_H
15 #define LLVM_LIB_TARGET_AMDGPU_SIINSTRINFO_H
16 
17 #include "AMDGPUInstrInfo.h"
18 #include "SIDefines.h"
19 #include "SIRegisterInfo.h"
20 #include "Utils/AMDGPUBaseInfo.h"
21 #include "llvm/ADT/ArrayRef.h"
22 #include "llvm/ADT/SetVector.h"
28 #include "llvm/MC/MCInstrDesc.h"
29 #include "llvm/Support/Compiler.h"
30 #include <cassert>
31 #include <cstdint>
32 
33 #define GET_INSTRINFO_HEADER
34 #include "AMDGPUGenInstrInfo.inc"
35 
36 namespace llvm {
37 
38 class APInt;
39 class MachineDominatorTree;
40 class MachineRegisterInfo;
41 class RegScavenger;
42 class GCNSubtarget;
43 class TargetRegisterClass;
44 
45 class SIInstrInfo final : public AMDGPUGenInstrInfo {
46 private:
47  const SIRegisterInfo RI;
48  const GCNSubtarget &ST;
49 
50  // The inverse predicate should have the negative value.
51  enum BranchPredicate {
52  INVALID_BR = 0,
53  SCC_TRUE = 1,
54  SCC_FALSE = -1,
55  VCCNZ = 2,
56  VCCZ = -2,
57  EXECNZ = -3,
58  EXECZ = 3
59  };
60 
62 
63  static unsigned getBranchOpcode(BranchPredicate Cond);
64  static BranchPredicate getBranchPredicate(unsigned Opcode);
65 
66 public:
69  MachineOperand &SuperReg,
70  const TargetRegisterClass *SuperRC,
71  unsigned SubIdx,
72  const TargetRegisterClass *SubRC) const;
75  MachineOperand &SuperReg,
76  const TargetRegisterClass *SuperRC,
77  unsigned SubIdx,
78  const TargetRegisterClass *SubRC) const;
79 private:
80  void swapOperands(MachineInstr &Inst) const;
81 
82  bool moveScalarAddSub(SetVectorType &Worklist, MachineInstr &Inst,
83  MachineDominatorTree *MDT = nullptr) const;
84 
85  void lowerScalarAbs(SetVectorType &Worklist,
86  MachineInstr &Inst) const;
87 
88  void lowerScalarXnor(SetVectorType &Worklist,
89  MachineInstr &Inst) const;
90 
91  void splitScalarNotBinop(SetVectorType &Worklist,
92  MachineInstr &Inst,
93  unsigned Opcode) const;
94 
95  void splitScalarBinOpN2(SetVectorType &Worklist,
96  MachineInstr &Inst,
97  unsigned Opcode) const;
98 
99  void splitScalar64BitUnaryOp(SetVectorType &Worklist,
100  MachineInstr &Inst, unsigned Opcode) const;
101 
102  void splitScalar64BitAddSub(SetVectorType &Worklist, MachineInstr &Inst,
103  MachineDominatorTree *MDT = nullptr) const;
104 
105  void splitScalar64BitBinaryOp(SetVectorType &Worklist, MachineInstr &Inst,
106  unsigned Opcode,
107  MachineDominatorTree *MDT = nullptr) const;
108 
109  void splitScalar64BitXnor(SetVectorType &Worklist, MachineInstr &Inst,
110  MachineDominatorTree *MDT = nullptr) const;
111 
112  void splitScalar64BitBCNT(SetVectorType &Worklist,
113  MachineInstr &Inst) const;
114  void splitScalar64BitBFE(SetVectorType &Worklist,
115  MachineInstr &Inst) const;
116  void movePackToVALU(SetVectorType &Worklist,
117  MachineRegisterInfo &MRI,
118  MachineInstr &Inst) const;
119 
120  void addUsersToMoveToVALUWorklist(unsigned Reg, MachineRegisterInfo &MRI,
121  SetVectorType &Worklist) const;
122 
123  void addSCCDefUsersToVALUWorklist(MachineOperand &Op,
124  MachineInstr &SCCDefInst,
125  SetVectorType &Worklist) const;
126 
127  const TargetRegisterClass *
128  getDestEquivalentVGPRClass(const MachineInstr &Inst) const;
129 
130  bool checkInstOffsetsDoNotOverlap(const MachineInstr &MIa,
131  const MachineInstr &MIb) const;
132 
133  unsigned findUsedSGPR(const MachineInstr &MI, int OpIndices[3]) const;
134 
135 protected:
137  MachineOperand &Src0, unsigned Src0OpName,
138  MachineOperand &Src1, unsigned Src1OpName) const;
139 
141  unsigned OpIdx0,
142  unsigned OpIdx1) const override;
143 
144 public:
146  MO_MASK = 0xf,
147 
148  MO_NONE = 0,
149  // MO_GOTPCREL -> symbol@GOTPCREL -> R_AMDGPU_GOTPCREL.
151  // MO_GOTPCREL32_LO -> symbol@gotpcrel32@lo -> R_AMDGPU_GOTPCREL32_LO.
154  // MO_GOTPCREL32_HI -> symbol@gotpcrel32@hi -> R_AMDGPU_GOTPCREL32_HI.
156  // MO_REL32_LO -> symbol@rel32@lo -> R_AMDGPU_REL32_LO.
157  MO_REL32 = 4,
159  // MO_REL32_HI -> symbol@rel32@hi -> R_AMDGPU_REL32_HI.
161 
164 
167  };
168 
169  explicit SIInstrInfo(const GCNSubtarget &ST);
170 
172  return RI;
173  }
174 
176  AliasAnalysis *AA) const override;
177 
178  bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
179  int64_t &Offset1,
180  int64_t &Offset2) const override;
181 
182  bool getMemOperandWithOffset(const MachineInstr &LdSt,
183  const MachineOperand *&BaseOp,
184  int64_t &Offset,
185  const TargetRegisterInfo *TRI) const final;
186 
187  bool shouldClusterMemOps(const MachineOperand &BaseOp1,
188  const MachineOperand &BaseOp2,
189  unsigned NumLoads) const override;
190 
191  bool shouldScheduleLoadsNear(SDNode *Load0, SDNode *Load1, int64_t Offset0,
192  int64_t Offset1, unsigned NumLoads) const override;
193 
195  const DebugLoc &DL, unsigned DestReg, unsigned SrcReg,
196  bool KillSrc) const override;
197 
199  RegScavenger *RS, unsigned TmpReg,
200  unsigned Offset, unsigned Size) const;
201 
204  const DebugLoc &DL,
205  unsigned DestReg,
206  int64_t Value) const;
207 
209  unsigned Size) const;
210 
211  unsigned insertNE(MachineBasicBlock *MBB,
213  unsigned SrcReg, int Value) const;
214 
215  unsigned insertEQ(MachineBasicBlock *MBB,
217  unsigned SrcReg, int Value) const;
218 
220  MachineBasicBlock::iterator MI, unsigned SrcReg,
221  bool isKill, int FrameIndex,
222  const TargetRegisterClass *RC,
223  const TargetRegisterInfo *TRI) const override;
224 
226  MachineBasicBlock::iterator MI, unsigned DestReg,
227  int FrameIndex, const TargetRegisterClass *RC,
228  const TargetRegisterInfo *TRI) const override;
229 
230  bool expandPostRAPseudo(MachineInstr &MI) const override;
231 
232  // Returns an opcode that can be used to move a value to a \p DstRC
233  // register. If there is no hardware instruction that can store to \p
234  // DstRC, then AMDGPU::COPY is returned.
235  unsigned getMovOpcode(const TargetRegisterClass *DstRC) const;
236 
238  int commuteOpcode(unsigned Opc) const;
239 
241  inline int commuteOpcode(const MachineInstr &MI) const {
242  return commuteOpcode(MI.getOpcode());
243  }
244 
245  bool findCommutedOpIndices(MachineInstr &MI, unsigned &SrcOpIdx1,
246  unsigned &SrcOpIdx2) const override;
247 
248  bool findCommutedOpIndices(MCInstrDesc Desc, unsigned & SrcOpIdx0,
249  unsigned & SrcOpIdx1) const;
250 
251  bool isBranchOffsetInRange(unsigned BranchOpc,
252  int64_t BrOffset) const override;
253 
254  MachineBasicBlock *getBranchDestBlock(const MachineInstr &MI) const override;
255 
257  MachineBasicBlock &NewDestBB,
258  const DebugLoc &DL,
259  int64_t BrOffset,
260  RegScavenger *RS = nullptr) const override;
261 
264  MachineBasicBlock *&TBB,
265  MachineBasicBlock *&FBB,
267  bool AllowModify) const;
268 
270  MachineBasicBlock *&FBB,
272  bool AllowModify = false) const override;
273 
274  unsigned removeBranch(MachineBasicBlock &MBB,
275  int *BytesRemoved = nullptr) const override;
276 
279  const DebugLoc &DL,
280  int *BytesAdded = nullptr) const override;
281 
283  SmallVectorImpl<MachineOperand> &Cond) const override;
284 
285  bool canInsertSelect(const MachineBasicBlock &MBB,
287  unsigned TrueReg, unsigned FalseReg,
288  int &CondCycles,
289  int &TrueCycles, int &FalseCycles) const override;
290 
293  unsigned DstReg, ArrayRef<MachineOperand> Cond,
294  unsigned TrueReg, unsigned FalseReg) const override;
295 
298  unsigned DstReg, ArrayRef<MachineOperand> Cond,
299  unsigned TrueReg, unsigned FalseReg) const;
300 
302  unsigned Kind) const override;
303 
304  bool
306  const MachineInstr &MIb,
307  AliasAnalysis *AA = nullptr) const override;
308 
309  bool isFoldableCopy(const MachineInstr &MI) const;
310 
311  bool FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, unsigned Reg,
312  MachineRegisterInfo *MRI) const final;
313 
314  unsigned getMachineCSELookAheadLimit() const override { return 500; }
315 
317  MachineInstr &MI,
318  LiveVariables *LV) const override;
319 
320  bool isSchedulingBoundary(const MachineInstr &MI,
321  const MachineBasicBlock *MBB,
322  const MachineFunction &MF) const override;
323 
324  static bool isSALU(const MachineInstr &MI) {
325  return MI.getDesc().TSFlags & SIInstrFlags::SALU;
326  }
327 
328  bool isSALU(uint16_t Opcode) const {
329  return get(Opcode).TSFlags & SIInstrFlags::SALU;
330  }
331 
332  static bool isVALU(const MachineInstr &MI) {
333  return MI.getDesc().TSFlags & SIInstrFlags::VALU;
334  }
335 
336  bool isVALU(uint16_t Opcode) const {
337  return get(Opcode).TSFlags & SIInstrFlags::VALU;
338  }
339 
340  static bool isVMEM(const MachineInstr &MI) {
341  return isMUBUF(MI) || isMTBUF(MI) || isMIMG(MI);
342  }
343 
344  bool isVMEM(uint16_t Opcode) const {
345  return isMUBUF(Opcode) || isMTBUF(Opcode) || isMIMG(Opcode);
346  }
347 
348  static bool isSOP1(const MachineInstr &MI) {
349  return MI.getDesc().TSFlags & SIInstrFlags::SOP1;
350  }
351 
352  bool isSOP1(uint16_t Opcode) const {
353  return get(Opcode).TSFlags & SIInstrFlags::SOP1;
354  }
355 
356  static bool isSOP2(const MachineInstr &MI) {
357  return MI.getDesc().TSFlags & SIInstrFlags::SOP2;
358  }
359 
360  bool isSOP2(uint16_t Opcode) const {
361  return get(Opcode).TSFlags & SIInstrFlags::SOP2;
362  }
363 
364  static bool isSOPC(const MachineInstr &MI) {
365  return MI.getDesc().TSFlags & SIInstrFlags::SOPC;
366  }
367 
368  bool isSOPC(uint16_t Opcode) const {
369  return get(Opcode).TSFlags & SIInstrFlags::SOPC;
370  }
371 
372  static bool isSOPK(const MachineInstr &MI) {
373  return MI.getDesc().TSFlags & SIInstrFlags::SOPK;
374  }
375 
376  bool isSOPK(uint16_t Opcode) const {
377  return get(Opcode).TSFlags & SIInstrFlags::SOPK;
378  }
379 
380  static bool isSOPP(const MachineInstr &MI) {
381  return MI.getDesc().TSFlags & SIInstrFlags::SOPP;
382  }
383 
384  bool isSOPP(uint16_t Opcode) const {
385  return get(Opcode).TSFlags & SIInstrFlags::SOPP;
386  }
387 
388  static bool isPacked(const MachineInstr &MI) {
389  return MI.getDesc().TSFlags & SIInstrFlags::IsPacked;
390  }
391 
392  bool isPacked(uint16_t Opcode) const {
393  return get(Opcode).TSFlags & SIInstrFlags::IsPacked;
394  }
395 
396  static bool isVOP1(const MachineInstr &MI) {
397  return MI.getDesc().TSFlags & SIInstrFlags::VOP1;
398  }
399 
400  bool isVOP1(uint16_t Opcode) const {
401  return get(Opcode).TSFlags & SIInstrFlags::VOP1;
402  }
403 
404  static bool isVOP2(const MachineInstr &MI) {
405  return MI.getDesc().TSFlags & SIInstrFlags::VOP2;
406  }
407 
408  bool isVOP2(uint16_t Opcode) const {
409  return get(Opcode).TSFlags & SIInstrFlags::VOP2;
410  }
411 
412  static bool isVOP3(const MachineInstr &MI) {
413  return MI.getDesc().TSFlags & SIInstrFlags::VOP3;
414  }
415 
416  bool isVOP3(uint16_t Opcode) const {
417  return get(Opcode).TSFlags & SIInstrFlags::VOP3;
418  }
419 
420  static bool isSDWA(const MachineInstr &MI) {
421  return MI.getDesc().TSFlags & SIInstrFlags::SDWA;
422  }
423 
424  bool isSDWA(uint16_t Opcode) const {
425  return get(Opcode).TSFlags & SIInstrFlags::SDWA;
426  }
427 
428  static bool isVOPC(const MachineInstr &MI) {
429  return MI.getDesc().TSFlags & SIInstrFlags::VOPC;
430  }
431 
432  bool isVOPC(uint16_t Opcode) const {
433  return get(Opcode).TSFlags & SIInstrFlags::VOPC;
434  }
435 
436  static bool isMUBUF(const MachineInstr &MI) {
437  return MI.getDesc().TSFlags & SIInstrFlags::MUBUF;
438  }
439 
440  bool isMUBUF(uint16_t Opcode) const {
441  return get(Opcode).TSFlags & SIInstrFlags::MUBUF;
442  }
443 
444  static bool isMTBUF(const MachineInstr &MI) {
445  return MI.getDesc().TSFlags & SIInstrFlags::MTBUF;
446  }
447 
448  bool isMTBUF(uint16_t Opcode) const {
449  return get(Opcode).TSFlags & SIInstrFlags::MTBUF;
450  }
451 
452  static bool isSMRD(const MachineInstr &MI) {
453  return MI.getDesc().TSFlags & SIInstrFlags::SMRD;
454  }
455 
456  bool isSMRD(uint16_t Opcode) const {
457  return get(Opcode).TSFlags & SIInstrFlags::SMRD;
458  }
459 
460  bool isBufferSMRD(const MachineInstr &MI) const;
461 
462  static bool isDS(const MachineInstr &MI) {
463  return MI.getDesc().TSFlags & SIInstrFlags::DS;
464  }
465 
466  bool isDS(uint16_t Opcode) const {
467  return get(Opcode).TSFlags & SIInstrFlags::DS;
468  }
469 
470  bool isAlwaysGDS(uint16_t Opcode) const;
471 
472  static bool isMIMG(const MachineInstr &MI) {
473  return MI.getDesc().TSFlags & SIInstrFlags::MIMG;
474  }
475 
476  bool isMIMG(uint16_t Opcode) const {
477  return get(Opcode).TSFlags & SIInstrFlags::MIMG;
478  }
479 
480  static bool isGather4(const MachineInstr &MI) {
481  return MI.getDesc().TSFlags & SIInstrFlags::Gather4;
482  }
483 
484  bool isGather4(uint16_t Opcode) const {
485  return get(Opcode).TSFlags & SIInstrFlags::Gather4;
486  }
487 
488  static bool isFLAT(const MachineInstr &MI) {
489  return MI.getDesc().TSFlags & SIInstrFlags::FLAT;
490  }
491 
492  // Is a FLAT encoded instruction which accesses a specific segment,
493  // i.e. global_* or scratch_*.
494  static bool isSegmentSpecificFLAT(const MachineInstr &MI) {
495  auto Flags = MI.getDesc().TSFlags;
496  return (Flags & SIInstrFlags::FLAT) && !(Flags & SIInstrFlags::LGKM_CNT);
497  }
498 
499  // Any FLAT encoded instruction, including global_* and scratch_*.
500  bool isFLAT(uint16_t Opcode) const {
501  return get(Opcode).TSFlags & SIInstrFlags::FLAT;
502  }
503 
504  static bool isEXP(const MachineInstr &MI) {
505  return MI.getDesc().TSFlags & SIInstrFlags::EXP;
506  }
507 
508  bool isEXP(uint16_t Opcode) const {
509  return get(Opcode).TSFlags & SIInstrFlags::EXP;
510  }
511 
512  static bool isWQM(const MachineInstr &MI) {
513  return MI.getDesc().TSFlags & SIInstrFlags::WQM;
514  }
515 
516  bool isWQM(uint16_t Opcode) const {
517  return get(Opcode).TSFlags & SIInstrFlags::WQM;
518  }
519 
520  static bool isDisableWQM(const MachineInstr &MI) {
522  }
523 
524  bool isDisableWQM(uint16_t Opcode) const {
525  return get(Opcode).TSFlags & SIInstrFlags::DisableWQM;
526  }
527 
528  static bool isVGPRSpill(const MachineInstr &MI) {
530  }
531 
532  bool isVGPRSpill(uint16_t Opcode) const {
533  return get(Opcode).TSFlags & SIInstrFlags::VGPRSpill;
534  }
535 
536  static bool isSGPRSpill(const MachineInstr &MI) {
538  }
539 
540  bool isSGPRSpill(uint16_t Opcode) const {
541  return get(Opcode).TSFlags & SIInstrFlags::SGPRSpill;
542  }
543 
544  static bool isDPP(const MachineInstr &MI) {
545  return MI.getDesc().TSFlags & SIInstrFlags::DPP;
546  }
547 
548  bool isDPP(uint16_t Opcode) const {
549  return get(Opcode).TSFlags & SIInstrFlags::DPP;
550  }
551 
552  static bool isVOP3P(const MachineInstr &MI) {
553  return MI.getDesc().TSFlags & SIInstrFlags::VOP3P;
554  }
555 
556  bool isVOP3P(uint16_t Opcode) const {
557  return get(Opcode).TSFlags & SIInstrFlags::VOP3P;
558  }
559 
560  static bool isVINTRP(const MachineInstr &MI) {
561  return MI.getDesc().TSFlags & SIInstrFlags::VINTRP;
562  }
563 
564  bool isVINTRP(uint16_t Opcode) const {
565  return get(Opcode).TSFlags & SIInstrFlags::VINTRP;
566  }
567 
568  static bool isScalarUnit(const MachineInstr &MI) {
570  }
571 
572  static bool usesVM_CNT(const MachineInstr &MI) {
573  return MI.getDesc().TSFlags & SIInstrFlags::VM_CNT;
574  }
575 
576  static bool usesLGKM_CNT(const MachineInstr &MI) {
577  return MI.getDesc().TSFlags & SIInstrFlags::LGKM_CNT;
578  }
579 
580  static bool sopkIsZext(const MachineInstr &MI) {
582  }
583 
584  bool sopkIsZext(uint16_t Opcode) const {
585  return get(Opcode).TSFlags & SIInstrFlags::SOPK_ZEXT;
586  }
587 
588  /// \returns true if this is an s_store_dword* instruction. This is more
589  /// specific than than isSMEM && mayStore.
590  static bool isScalarStore(const MachineInstr &MI) {
592  }
593 
594  bool isScalarStore(uint16_t Opcode) const {
595  return get(Opcode).TSFlags & SIInstrFlags::SCALAR_STORE;
596  }
597 
598  static bool isFixedSize(const MachineInstr &MI) {
600  }
601 
602  bool isFixedSize(uint16_t Opcode) const {
603  return get(Opcode).TSFlags & SIInstrFlags::FIXED_SIZE;
604  }
605 
606  static bool hasFPClamp(const MachineInstr &MI) {
607  return MI.getDesc().TSFlags & SIInstrFlags::FPClamp;
608  }
609 
610  bool hasFPClamp(uint16_t Opcode) const {
611  return get(Opcode).TSFlags & SIInstrFlags::FPClamp;
612  }
613 
614  static bool hasIntClamp(const MachineInstr &MI) {
615  return MI.getDesc().TSFlags & SIInstrFlags::IntClamp;
616  }
617 
618  uint64_t getClampMask(const MachineInstr &MI) const {
619  const uint64_t ClampFlags = SIInstrFlags::FPClamp |
623  return MI.getDesc().TSFlags & ClampFlags;
624  }
625 
626  static bool usesFPDPRounding(const MachineInstr &MI) {
628  }
629 
630  bool usesFPDPRounding(uint16_t Opcode) const {
631  return get(Opcode).TSFlags & SIInstrFlags::FPDPRounding;
632  }
633 
634  bool isVGPRCopy(const MachineInstr &MI) const {
635  assert(MI.isCopy());
636  unsigned Dest = MI.getOperand(0).getReg();
637  const MachineFunction &MF = *MI.getParent()->getParent();
638  const MachineRegisterInfo &MRI = MF.getRegInfo();
639  return !RI.isSGPRReg(MRI, Dest);
640  }
641 
642  /// Whether we must prevent this instruction from executing with EXEC = 0.
643  bool hasUnwantedEffectsWhenEXECEmpty(const MachineInstr &MI) const;
644 
645  /// Returns true if the instruction could potentially depend on the value of
646  /// exec. If false, exec dependencies may safely be ignored.
647  bool mayReadEXEC(const MachineRegisterInfo &MRI, const MachineInstr &MI) const;
648 
649  bool isInlineConstant(const APInt &Imm) const;
650 
651  bool isInlineConstant(const MachineOperand &MO, uint8_t OperandType) const;
652 
654  const MCOperandInfo &OpInfo) const {
655  return isInlineConstant(MO, OpInfo.OperandType);
656  }
657 
658  /// \p returns true if \p UseMO is substituted with \p DefMO in \p MI it would
659  /// be an inline immediate.
661  const MachineOperand &UseMO,
662  const MachineOperand &DefMO) const {
663  assert(UseMO.getParent() == &MI);
664  int OpIdx = MI.getOperandNo(&UseMO);
665  if (!MI.getDesc().OpInfo || OpIdx >= MI.getDesc().NumOperands) {
666  return false;
667  }
668 
669  return isInlineConstant(DefMO, MI.getDesc().OpInfo[OpIdx]);
670  }
671 
672  /// \p returns true if the operand \p OpIdx in \p MI is a valid inline
673  /// immediate.
674  bool isInlineConstant(const MachineInstr &MI, unsigned OpIdx) const {
675  const MachineOperand &MO = MI.getOperand(OpIdx);
676  return isInlineConstant(MO, MI.getDesc().OpInfo[OpIdx].OperandType);
677  }
678 
679  bool isInlineConstant(const MachineInstr &MI, unsigned OpIdx,
680  const MachineOperand &MO) const {
681  if (!MI.getDesc().OpInfo || OpIdx >= MI.getDesc().NumOperands)
682  return false;
683 
684  if (MI.isCopy()) {
685  unsigned Size = getOpSize(MI, OpIdx);
686  assert(Size == 8 || Size == 4);
687 
688  uint8_t OpType = (Size == 8) ?
690  return isInlineConstant(MO, OpType);
691  }
692 
693  return isInlineConstant(MO, MI.getDesc().OpInfo[OpIdx].OperandType);
694  }
695 
696  bool isInlineConstant(const MachineOperand &MO) const {
697  const MachineInstr *Parent = MO.getParent();
698  return isInlineConstant(*Parent, Parent->getOperandNo(&MO));
699  }
700 
702  const MCOperandInfo &OpInfo) const {
703  return MO.isImm() && !isInlineConstant(MO, OpInfo.OperandType);
704  }
705 
706  bool isLiteralConstant(const MachineInstr &MI, int OpIdx) const {
707  const MachineOperand &MO = MI.getOperand(OpIdx);
708  return MO.isImm() && !isInlineConstant(MI, OpIdx);
709  }
710 
711  // Returns true if this operand could potentially require a 32-bit literal
712  // operand, but not necessarily. A FrameIndex for example could resolve to an
713  // inline immediate value that will not require an additional 4-bytes; this
714  // assumes that it will.
715  bool isLiteralConstantLike(const MachineOperand &MO,
716  const MCOperandInfo &OpInfo) const;
717 
718  bool isImmOperandLegal(const MachineInstr &MI, unsigned OpNo,
719  const MachineOperand &MO) const;
720 
721  /// Return true if this 64-bit VALU instruction has a 32-bit encoding.
722  /// This function will return false if you pass it a 32-bit instruction.
723  bool hasVALU32BitEncoding(unsigned Opcode) const;
724 
725  /// Returns true if this operand uses the constant bus.
726  bool usesConstantBus(const MachineRegisterInfo &MRI,
727  const MachineOperand &MO,
728  const MCOperandInfo &OpInfo) const;
729 
730  /// Return true if this instruction has any modifiers.
731  /// e.g. src[012]_mod, omod, clamp.
732  bool hasModifiers(unsigned Opcode) const;
733 
734  bool hasModifiersSet(const MachineInstr &MI,
735  unsigned OpName) const;
736  bool hasAnyModifiersSet(const MachineInstr &MI) const;
737 
738  bool canShrink(const MachineInstr &MI,
739  const MachineRegisterInfo &MRI) const;
740 
742  unsigned NewOpcode) const;
743 
744  bool verifyInstruction(const MachineInstr &MI,
745  StringRef &ErrInfo) const override;
746 
747  unsigned getVALUOp(const MachineInstr &MI) const;
748 
749  /// Return the correct register class for \p OpNo. For target-specific
750  /// instructions, this will return the register class that has been defined
751  /// in tablegen. For generic instructions, like REG_SEQUENCE it will return
752  /// the register class of its machine operand.
753  /// to infer the correct register class base on the other operands.
755  unsigned OpNo) const;
756 
757  /// Return the size in bytes of the operand OpNo on the given
758  // instruction opcode.
759  unsigned getOpSize(uint16_t Opcode, unsigned OpNo) const {
760  const MCOperandInfo &OpInfo = get(Opcode).OpInfo[OpNo];
761 
762  if (OpInfo.RegClass == -1) {
763  // If this is an immediate operand, this must be a 32-bit literal.
765  return 4;
766  }
767 
768  return RI.getRegSizeInBits(*RI.getRegClass(OpInfo.RegClass)) / 8;
769  }
770 
771  /// This form should usually be preferred since it handles operands
772  /// with unknown register classes.
773  unsigned getOpSize(const MachineInstr &MI, unsigned OpNo) const {
774  const MachineOperand &MO = MI.getOperand(OpNo);
775  if (MO.isReg()) {
776  if (unsigned SubReg = MO.getSubReg()) {
777  assert(RI.getRegSizeInBits(*RI.getSubClassWithSubReg(
778  MI.getParent()->getParent()->getRegInfo().
779  getRegClass(MO.getReg()), SubReg)) >= 32 &&
780  "Sub-dword subregs are not supported");
781  return RI.getSubRegIndexLaneMask(SubReg).getNumLanes() * 4;
782  }
783  }
784  return RI.getRegSizeInBits(*getOpRegClass(MI, OpNo)) / 8;
785  }
786 
787  /// Legalize the \p OpIndex operand of this instruction by inserting
788  /// a MOV. For example:
789  /// ADD_I32_e32 VGPR0, 15
790  /// to
791  /// MOV VGPR1, 15
792  /// ADD_I32_e32 VGPR0, VGPR1
793  ///
794  /// If the operand being legalized is a register, then a COPY will be used
795  /// instead of MOV.
796  void legalizeOpWithMove(MachineInstr &MI, unsigned OpIdx) const;
797 
798  /// Check if \p MO is a legal operand if it was the \p OpIdx Operand
799  /// for \p MI.
800  bool isOperandLegal(const MachineInstr &MI, unsigned OpIdx,
801  const MachineOperand *MO = nullptr) const;
802 
803  /// Check if \p MO would be a valid operand for the given operand
804  /// definition \p OpInfo. Note this does not attempt to validate constant bus
805  /// restrictions (e.g. literal constant usage).
806  bool isLegalVSrcOperand(const MachineRegisterInfo &MRI,
807  const MCOperandInfo &OpInfo,
808  const MachineOperand &MO) const;
809 
810  /// Check if \p MO (a register operand) is a legal register for the
811  /// given operand description.
812  bool isLegalRegOperand(const MachineRegisterInfo &MRI,
813  const MCOperandInfo &OpInfo,
814  const MachineOperand &MO) const;
815 
816  /// Legalize operands in \p MI by either commuting it or inserting a
817  /// copy of src1.
819 
820  /// Fix operands in \p MI to satisfy constant bus requirements.
822 
823  /// Copy a value from a VGPR (\p SrcReg) to SGPR. This function can only
824  /// be used when it is know that the value in SrcReg is same across all
825  /// threads in the wave.
826  /// \returns The SGPR register that \p SrcReg was copied to.
827  unsigned readlaneVGPRToSGPR(unsigned SrcReg, MachineInstr &UseMI,
828  MachineRegisterInfo &MRI) const;
829 
831 
834  const TargetRegisterClass *DstRC,
836  const DebugLoc &DL) const;
837 
838  /// Legalize all operands in this instruction. This function may create new
839  /// instructions and control-flow around \p MI. If present, \p MDT is
840  /// updated.
842  MachineDominatorTree *MDT = nullptr) const;
843 
844  /// Replace this instruction's opcode with the equivalent VALU
845  /// opcode. This function will also move the users of \p MI to the
846  /// VALU if necessary. If present, \p MDT is updated.
847  void moveToVALU(MachineInstr &MI, MachineDominatorTree *MDT = nullptr) const;
848 
850  int Count) const;
851 
852  void insertNoop(MachineBasicBlock &MBB,
853  MachineBasicBlock::iterator MI) const override;
854 
855  void insertReturn(MachineBasicBlock &MBB) const;
856  /// Return the number of wait states that result from executing this
857  /// instruction.
858  static unsigned getNumWaitStates(const MachineInstr &MI);
859 
860  /// Returns the operand named \p Op. If \p MI does not have an
861  /// operand named \c Op, this function returns nullptr.
863  MachineOperand *getNamedOperand(MachineInstr &MI, unsigned OperandName) const;
864 
867  unsigned OpName) const {
868  return getNamedOperand(const_cast<MachineInstr &>(MI), OpName);
869  }
870 
871  /// Get required immediate operand
872  int64_t getNamedImmOperand(const MachineInstr &MI, unsigned OpName) const {
873  int Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), OpName);
874  return MI.getOperand(Idx).getImm();
875  }
876 
877  uint64_t getDefaultRsrcDataFormat() const;
878  uint64_t getScratchRsrcWords23() const;
879 
880  bool isLowLatencyInstruction(const MachineInstr &MI) const;
881  bool isHighLatencyInstruction(const MachineInstr &MI) const;
882 
883  /// Return the descriptor of the target-specific machine instruction
884  /// that corresponds to the specified pseudo or native opcode.
885  const MCInstrDesc &getMCOpcodeFromPseudo(unsigned Opcode) const {
886  return get(pseudoToMCOpcode(Opcode));
887  }
888 
889  unsigned isStackAccess(const MachineInstr &MI, int &FrameIndex) const;
890  unsigned isSGPRStackAccess(const MachineInstr &MI, int &FrameIndex) const;
891 
892  unsigned isLoadFromStackSlot(const MachineInstr &MI,
893  int &FrameIndex) const override;
894  unsigned isStoreToStackSlot(const MachineInstr &MI,
895  int &FrameIndex) const override;
896 
897  unsigned getInstBundleSize(const MachineInstr &MI) const;
898  unsigned getInstSizeInBytes(const MachineInstr &MI) const override;
899 
900  bool mayAccessFlatAddressSpace(const MachineInstr &MI) const;
901 
902  bool isNonUniformBranchInstr(MachineInstr &Instr) const;
903 
905  MachineBasicBlock *IfEnd) const;
906 
908  MachineBasicBlock *LoopEnd) const;
909 
910  std::pair<unsigned, unsigned>
911  decomposeMachineOperandsTargetFlags(unsigned TF) const override;
912 
914  getSerializableTargetIndices() const override;
915 
918 
921  const ScheduleDAG *DAG) const override;
922 
924  CreateTargetPostRAHazardRecognizer(const MachineFunction &MF) const override;
925 
926  bool isBasicBlockPrologue(const MachineInstr &MI) const override;
927 
928  /// Return a partially built integer add instruction without carry.
929  /// Caller must add source operands.
930  /// For pre-GFX9 it will generate unused carry destination operand.
931  /// TODO: After GFX9 it should return a no-carry operation.
934  const DebugLoc &DL,
935  unsigned DestReg) const;
936 
937  static bool isKillTerminator(unsigned Opcode);
938  const MCInstrDesc &getKillTerminatorFromPseudo(unsigned Opcode) const;
939 
940  static bool isLegalMUBUFImmOffset(unsigned Imm) {
941  return isUInt<12>(Imm);
942  }
943 
944  /// \brief Return a target-specific opcode if Opcode is a pseudo instruction.
945  /// Return -1 if the target-specific opcode for the pseudo instruction does
946  /// not exist. If Opcode is not a pseudo instruction, this is identity.
947  int pseudoToMCOpcode(int Opcode) const;
948 
949  void fixImplicitOperands(MachineInstr &MI) const;
950 };
951 
952 /// \brief Returns true if a reg:subreg pair P has a TRC class
954  const TargetRegisterClass &TRC,
956  auto *RC = MRI.getRegClass(P.Reg);
957  if (!P.SubReg)
958  return RC == &TRC;
959  auto *TRI = MRI.getTargetRegisterInfo();
960  return RC == TRI->getMatchingSuperRegClass(RC, &TRC, P.SubReg);
961 }
962 
963 /// \brief Create RegSubRegPair from a register MachineOperand
964 inline
966  assert(O.isReg());
968 }
969 
970 /// \brief Return the SubReg component from REG_SEQUENCE
972  unsigned SubReg);
973 
974 /// \brief Return the defining instruction for a given reg:subreg pair
975 /// skipping copy like instructions and subreg-manipulation pseudos.
976 /// Following another subreg of a reg:subreg isn't supported.
979 
980 /// \brief Return false if EXEC is not changed between the def of \p VReg at \p
981 /// DefMI and uses. If \p UseMI is not specified, this checks all uses of \p
982 /// VReg. Should be run on SSA. Currently does not attempt to track between
983 /// blocks.
985  unsigned VReg,
986  const MachineInstr &DefMI,
987  const MachineInstr *UseMI = nullptr);
988 
989 namespace AMDGPU {
990 
992  int getVOPe64(uint16_t Opcode);
993 
995  int getVOPe32(uint16_t Opcode);
996 
998  int getSDWAOp(uint16_t Opcode);
999 
1001  int getDPPOp32(uint16_t Opcode);
1002 
1004  int getBasicFromSDWAOp(uint16_t Opcode);
1005 
1007  int getCommuteRev(uint16_t Opcode);
1008 
1010  int getCommuteOrig(uint16_t Opcode);
1011 
1013  int getAddr64Inst(uint16_t Opcode);
1014 
1015  /// Check if \p Opcode is an Addr64 opcode.
1016  ///
1017  /// \returns \p Opcode if it is an Addr64 opcode, otherwise -1.
1019  int getIfAddr64Inst(uint16_t Opcode);
1020 
1022  int getMUBUFNoLdsInst(uint16_t Opcode);
1023 
1025  int getAtomicRetOp(uint16_t Opcode);
1026 
1028  int getAtomicNoRetOp(uint16_t Opcode);
1029 
1031  int getSOPKOp(uint16_t Opcode);
1032 
1034  int getGlobalSaddrOp(uint16_t Opcode);
1035 
1037  int getVCMPXNoSDstOp(uint16_t Opcode);
1038 
1039  const uint64_t RSRC_DATA_FORMAT = 0xf00000000000LL;
1040  const uint64_t RSRC_ELEMENT_SIZE_SHIFT = (32 + 19);
1041  const uint64_t RSRC_INDEX_STRIDE_SHIFT = (32 + 21);
1042  const uint64_t RSRC_TID_ENABLE = UINT64_C(1) << (32 + 23);
1043 
1044 } // end namespace AMDGPU
1045 
1046 namespace SI {
1047 namespace KernelInputOffsets {
1048 
1049 /// Offsets in bytes from the start of the input buffer
1050 enum Offsets {
1060 };
1061 
1062 } // end namespace KernelInputOffsets
1063 } // end namespace SI
1064 
1065 } // end namespace llvm
1066 
1067 #endif // LLVM_LIB_TARGET_AMDGPU_SIINSTRINFO_H
bool isFLAT(uint16_t Opcode) const
Definition: SIInstrInfo.h:500
bool isLegalRegOperand(const MachineRegisterInfo &MRI, const MCOperandInfo &OpInfo, const MachineOperand &MO) const
Check if MO (a register operand) is a legal register for the given operand description.
unsigned buildExtractSubReg(MachineBasicBlock::iterator MI, MachineRegisterInfo &MRI, MachineOperand &SuperReg, const TargetRegisterClass *SuperRC, unsigned SubIdx, const TargetRegisterClass *SubRC) const
bool analyzeBranchImpl(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const
unsigned getVALUOp(const MachineInstr &MI) const
TargetInstrInfo::RegSubRegPair getRegSequenceSubReg(MachineInstr &MI, unsigned SubReg)
Return the SubReg component from REG_SEQUENCE.
static bool isSGPRSpill(const MachineInstr &MI)
Definition: SIInstrInfo.h:536
Interface definition for SIRegisterInfo.
bool sopkIsZext(uint16_t Opcode) const
Definition: SIInstrInfo.h:584
void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, unsigned DstReg, ArrayRef< MachineOperand > Cond, unsigned TrueReg, unsigned FalseReg) const override
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify=false) const override
bool isVGPRCopy(const MachineInstr &MI) const
Definition: SIInstrInfo.h:634
const TargetRegisterClass * getRegClass(unsigned Reg) const
Return the register class of the specified virtual register.
This class represents lattice values for constants.
Definition: AllocatorList.h:23
MachineInstr * getVRegSubRegDef(const TargetInstrInfo::RegSubRegPair &P, MachineRegisterInfo &MRI)
Return the defining instruction for a given reg:subreg pair skipping copy like instructions and subre...
static bool isScalarStore(const MachineInstr &MI)
Definition: SIInstrInfo.h:590
static bool sopkIsZext(const MachineInstr &MI)
Definition: SIInstrInfo.h:580
uint64_t getDefaultRsrcDataFormat() const
bool isOfRegClass(const TargetInstrInfo::RegSubRegPair &P, const TargetRegisterClass &TRC, MachineRegisterInfo &MRI)
Returns true if a reg:subreg pair P has a TRC class.
Definition: SIInstrInfo.h:953
bool isOperandLegal(const MachineInstr &MI, unsigned OpIdx, const MachineOperand *MO=nullptr) const
Check if MO is a legal operand if it was the OpIdx Operand for MI.
bool execMayBeModifiedBeforeUse(const MachineRegisterInfo &MRI, unsigned VReg, const MachineInstr &DefMI, const MachineInstr *UseMI=nullptr)
Return false if EXEC is not changed between the def of VReg at DefMI and uses.
bool isSOPK(uint16_t Opcode) const
Definition: SIInstrInfo.h:376
bool canInsertSelect(const MachineBasicBlock &MBB, ArrayRef< MachineOperand > Cond, unsigned TrueReg, unsigned FalseReg, int &CondCycles, int &TrueCycles, int &FalseCycles) const override
bool usesConstantBus(const MachineRegisterInfo &MRI, const MachineOperand &MO, const MCOperandInfo &OpInfo) const
Returns true if this operand uses the constant bus.
bool mayAccessFlatAddressSpace(const MachineInstr &MI) const
unsigned calculateLDSSpillAddress(MachineBasicBlock &MBB, MachineInstr &MI, RegScavenger *RS, unsigned TmpReg, unsigned Offset, unsigned Size) const
bool hasModifiersSet(const MachineInstr &MI, unsigned OpName) const
const TargetRegisterClass * getOpRegClass(const MachineInstr &MI, unsigned OpNo) const
Return the correct register class for OpNo.
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:164
unsigned getReg() const
getReg - Returns the register number.
static bool isVINTRP(const MachineInstr &MI)
Definition: SIInstrInfo.h:560
unsigned getOperandNo(const_mop_iterator I) const
Returns the number of the operand iterator I points to.
Definition: MachineInstr.h:510
unsigned insertNE(MachineBasicBlock *MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, unsigned SrcReg, int Value) const
unsigned getAddressSpaceForPseudoSourceKind(unsigned Kind) const override
unsigned Reg
unsigned isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override
unsigned getSubReg() const
static bool isSOPK(const MachineInstr &MI)
Definition: SIInstrInfo.h:372
void legalizeOperandsVOP2(MachineRegisterInfo &MRI, MachineInstr &MI) const
Legalize operands in MI by either commuting it or inserting a copy of src1.
unsigned isSGPRStackAccess(const MachineInstr &MI, int &FrameIndex) const
Offsets
Offsets in bytes from the start of the input buffer.
Definition: SIInstrInfo.h:1050
bool isMIMG(uint16_t Opcode) const
Definition: SIInstrInfo.h:476
int64_t getNamedImmOperand(const MachineInstr &MI, unsigned OpName) const
Get required immediate operand.
Definition: SIInstrInfo.h:872
unsigned const TargetRegisterInfo * TRI
A debug info location.
Definition: DebugLoc.h:33
bool isDPP(uint16_t Opcode) const
Definition: SIInstrInfo.h:548
bool isGather4(uint16_t Opcode) const
Definition: SIInstrInfo.h:484
static bool isSOPP(const MachineInstr &MI)
Definition: SIInstrInfo.h:380
LLVM_READONLY int getAtomicNoRetOp(uint16_t Opcode)
bool isInlineConstant(const APInt &Imm) const
bool isMUBUF(uint16_t Opcode) const
Definition: SIInstrInfo.h:440
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const override
static bool isSOPC(const MachineInstr &MI)
Definition: SIInstrInfo.h:364
bool hasAnyModifiersSet(const MachineInstr &MI) const
static bool isSMRD(const MachineInstr &MI)
Definition: SIInstrInfo.h:452
void legalizeOperands(MachineInstr &MI, MachineDominatorTree *MDT=nullptr) const
Legalize all operands in this instruction.
const SIRegisterInfo & getRegisterInfo() const
Definition: SIInstrInfo.h:171
LLVM_READONLY int getVOPe64(uint16_t Opcode)
static bool isFixedSize(const MachineInstr &MI)
Definition: SIInstrInfo.h:598
LLVM_READONLY int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx)
bool verifyInstruction(const MachineInstr &MI, StringRef &ErrInfo) const override
static bool isDS(const MachineInstr &MI)
Definition: SIInstrInfo.h:462
bool isEXP(uint16_t Opcode) const
Definition: SIInstrInfo.h:508
bool isSOPP(uint16_t Opcode) const
Definition: SIInstrInfo.h:384
std::pair< unsigned, unsigned > decomposeMachineOperandsTargetFlags(unsigned TF) const override
LLVM_READONLY int getAtomicRetOp(uint16_t Opcode)
static bool isFLAT(const MachineInstr &MI)
Definition: SIInstrInfo.h:488
unsigned getInstSizeInBytes(const MachineInstr &MI) const override
uint64_t getScratchRsrcWords23() const
bool isAlwaysGDS(uint16_t Opcode) const
bool isSGPRReg(const MachineRegisterInfo &MRI, unsigned Reg) const
static bool isGather4(const MachineInstr &MI)
Definition: SIInstrInfo.h:480
static bool isMIMG(const MachineInstr &MI)
Definition: SIInstrInfo.h:472
bool isVINTRP(uint16_t Opcode) const
Definition: SIInstrInfo.h:564
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:41
unsigned SubReg
MachineOperand buildExtractSubRegOrImm(MachineBasicBlock::iterator MI, MachineRegisterInfo &MRI, MachineOperand &SuperReg, const TargetRegisterClass *SuperRC, unsigned SubIdx, const TargetRegisterClass *SubRC) const
static int getRegClass(RegisterKind Is, unsigned RegWidth)
void insertWaitStates(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, int Count) const
LLVM_READONLY int getCommuteOrig(uint16_t Opcode)
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:410
bool isLiteralConstant(const MachineInstr &MI, int OpIdx) const
Definition: SIInstrInfo.h:706
const MCInstrDesc & getMCOpcodeFromPseudo(unsigned Opcode) const
Return the descriptor of the target-specific machine instruction that corresponds to the specified ps...
Definition: SIInstrInfo.h:885
static bool isVALU(const MachineInstr &MI)
Definition: SIInstrInfo.h:332
void legalizeOperandsVOP3(MachineRegisterInfo &MRI, MachineInstr &MI) const
Fix operands in MI to satisfy constant bus requirements.
unsigned getOpSize(uint16_t Opcode, unsigned OpNo) const
Return the size in bytes of the operand OpNo on the given.
Definition: SIInstrInfo.h:759
uint8_t OperandType
Information about the type of the operand.
Definition: MCInstrDesc.h:78
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
Definition: MachineInstr.h:407
unsigned getInstBundleSize(const MachineInstr &MI) const
static bool isMUBUF(const MachineInstr &MI)
Definition: SIInstrInfo.h:436
LLVM_READONLY MachineOperand * getNamedOperand(MachineInstr &MI, unsigned OperandName) const
Returns the operand named Op.
void convertNonUniformLoopRegion(MachineBasicBlock *LoopEntry, MachineBasicBlock *LoopEnd) const
const uint64_t RSRC_DATA_FORMAT
Definition: SIInstrInfo.h:1039
MachineInstr * commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned OpIdx0, unsigned OpIdx1) const override
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:32
bool isSGPRSpill(uint16_t Opcode) const
Definition: SIInstrInfo.h:540
bool isSDWA(uint16_t Opcode) const
Definition: SIInstrInfo.h:424
Itinerary data supplied by a subtarget to be used by a target.
bool isBasicBlockPrologue(const MachineInstr &MI) const override
bool isInlineConstant(const MachineOperand &MO) const
Definition: SIInstrInfo.h:696
BasicBlockListType::iterator iterator
unsigned short NumOperands
Definition: MCInstrDesc.h:167
LLVM_READONLY int getDPPOp32(uint16_t Opcode)
bool isVOP1(uint16_t Opcode) const
Definition: SIInstrInfo.h:400
TargetInstrInfo::RegSubRegPair RegSubRegPair
LLVM_READONLY int getSDWAOp(uint16_t Opcode)
static bool isDPP(const MachineInstr &MI)
Definition: SIInstrInfo.h:544
bool isSOPC(uint16_t Opcode) const
Definition: SIInstrInfo.h:368
#define P(N)
bool isInlineConstant(const MachineOperand &MO, const MCOperandInfo &OpInfo) const
Definition: SIInstrInfo.h:653
const TargetRegisterInfo * getTargetRegisterInfo() const
unsigned const MachineRegisterInfo * MRI
const MCInstrDesc & getKillTerminatorFromPseudo(unsigned Opcode) const
bool isFoldableCopy(const MachineInstr &MI) const
static bool usesVM_CNT(const MachineInstr &MI)
Definition: SIInstrInfo.h:572
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
const TargetRegisterClass * getPreferredSelectRegClass(unsigned Size) const
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
HazardRecognizer - This determines whether or not an instruction can be issued this cycle...
MachineInstrBuilder & UseMI
bool isReallyTriviallyReMaterializable(const MachineInstr &MI, AliasAnalysis *AA) const override
void fixImplicitOperands(MachineInstr &MI) const
LLVM_READONLY int getGlobalSaddrOp(uint16_t Opcode)
bool isSchedulingBoundary(const MachineInstr &MI, const MachineBasicBlock *MBB, const MachineFunction &MF) const override
bool usesFPDPRounding(uint16_t Opcode) const
Definition: SIInstrInfo.h:630
bool isInlineConstant(const MachineInstr &MI, unsigned OpIdx, const MachineOperand &MO) const
Definition: SIInstrInfo.h:679
void insertVectorSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, unsigned DstReg, ArrayRef< MachineOperand > Cond, unsigned TrueReg, unsigned FalseReg) const
static bool hasFPClamp(const MachineInstr &MI)
Definition: SIInstrInfo.h:606
bool canShrink(const MachineInstr &MI, const MachineRegisterInfo &MRI) const
bool expandPostRAPseudo(MachineInstr &MI) const override
bool isFixedSize(uint16_t Opcode) const
Definition: SIInstrInfo.h:602
void insertReturn(MachineBasicBlock &MBB) const
LLVM_READONLY int getIfAddr64Inst(uint16_t Opcode)
Check if Opcode is an Addr64 opcode.
bool isDS(uint16_t Opcode) const
Definition: SIInstrInfo.h:466
LLVM_READONLY int commuteOpcode(unsigned Opc) const
bool isVOPC(uint16_t Opcode) const
Definition: SIInstrInfo.h:432
unsigned insertEQ(MachineBasicBlock *MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, unsigned SrcReg, int Value) const
LLVM_READONLY int getSOPKOp(uint16_t Opcode)
bool isImmOperandLegal(const MachineInstr &MI, unsigned OpNo, const MachineOperand &MO) const
bool isSOP1(uint16_t Opcode) const
Definition: SIInstrInfo.h:352
bool hasVALU32BitEncoding(unsigned Opcode) const
Return true if this 64-bit VALU instruction has a 32-bit encoding.
static bool isSOP2(const MachineInstr &MI)
Definition: SIInstrInfo.h:356
void materializeImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, unsigned DestReg, int64_t Value) const
ScheduleHazardRecognizer * CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II, const ScheduleDAG *DAG) const override
This is used by the post-RA scheduler (SchedulePostRAList.cpp).
unsigned insertIndirectBranch(MachineBasicBlock &MBB, MachineBasicBlock &NewDestBB, const DebugLoc &DL, int64_t BrOffset, RegScavenger *RS=nullptr) const override
bool isWQM(uint16_t Opcode) const
Definition: SIInstrInfo.h:516
bool hasFPClamp(uint16_t Opcode) const
Definition: SIInstrInfo.h:610
static bool isVOP2(const MachineInstr &MI)
Definition: SIInstrInfo.h:404
bool isSMRD(uint16_t Opcode) const
Definition: SIInstrInfo.h:456
bool isCopy() const
unsigned isStackAccess(const MachineInstr &MI, int &FrameIndex) const
static unsigned getNumWaitStates(const MachineInstr &MI)
Return the number of wait states that result from executing this instruction.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
bool getMemOperandWithOffset(const MachineInstr &LdSt, const MachineOperand *&BaseOp, int64_t &Offset, const TargetRegisterInfo *TRI) const final
LLVM_READONLY int getBasicFromSDWAOp(uint16_t Opcode)
bool swapSourceModifiers(MachineInstr &MI, MachineOperand &Src0, unsigned Src0OpName, MachineOperand &Src1, unsigned Src1OpName) const
bool areMemAccessesTriviallyDisjoint(const MachineInstr &MIa, const MachineInstr &MIb, AliasAnalysis *AA=nullptr) const override
static bool isVOP3P(const MachineInstr &MI)
Definition: SIInstrInfo.h:552
bool isSOP2(uint16_t Opcode) const
Definition: SIInstrInfo.h:360
const uint64_t RSRC_TID_ENABLE
Definition: SIInstrInfo.h:1042
bool mayReadEXEC(const MachineRegisterInfo &MRI, const MachineInstr &MI) const
Returns true if the instruction could potentially depend on the value of exec.
static bool isWQM(const MachineInstr &MI)
Definition: SIInstrInfo.h:512
bool FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, unsigned Reg, MachineRegisterInfo *MRI) const final
bool isPacked(uint16_t Opcode) const
Definition: SIInstrInfo.h:392
static bool isEXP(const MachineInstr &MI)
Definition: SIInstrInfo.h:504
bool isScalarStore(uint16_t Opcode) const
Definition: SIInstrInfo.h:594
static bool usesFPDPRounding(const MachineInstr &MI)
Definition: SIInstrInfo.h:626
int pseudoToMCOpcode(int Opcode) const
Return a target-specific opcode if Opcode is a pseudo instruction.
bool isVOP2(uint16_t Opcode) const
Definition: SIInstrInfo.h:408
A SetVector that performs no allocations if smaller than a certain size.
Definition: SetVector.h:297
LLVM_READONLY int getMUBUFNoLdsInst(uint16_t Opcode)
LLVM_READONLY int getVOPe32(uint16_t Opcode)
TargetInstrInfo::RegSubRegPair getRegSubRegPair(const MachineOperand &O)
Create RegSubRegPair from a register MachineOperand.
Definition: SIInstrInfo.h:965
static bool isSALU(const MachineInstr &MI)
Definition: SIInstrInfo.h:324
MachineOperand class - Representation of each machine instruction operand.
Operands with register or 32-bit immediate.
Definition: SIDefines.h:118
bool isLiteralConstantLike(const MachineOperand &MO, const MCOperandInfo &OpInfo) const
A pair composed of a register and a sub-register index.
MachineInstrBuilder MachineInstrBuilder & DefMI
uint64_t getClampMask(const MachineInstr &MI) const
Definition: SIInstrInfo.h:618
MachineInstrBuilder getAddNoCarry(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, unsigned DestReg) const
Return a partially built integer add instruction without carry.
bool isLegalVSrcOperand(const MachineRegisterInfo &MRI, const MCOperandInfo &OpInfo, const MachineOperand &MO) const
Check if MO would be a valid operand for the given operand definition OpInfo.
const uint64_t RSRC_INDEX_STRIDE_SHIFT
Definition: SIInstrInfo.h:1041
bool isMTBUF(uint16_t Opcode) const
Definition: SIInstrInfo.h:448
bool shouldClusterMemOps(const MachineOperand &BaseOp1, const MachineOperand &BaseOp2, unsigned NumLoads) const override
Represents one node in the SelectionDAG.
LLVM_READONLY int getVCMPXNoSDstOp(uint16_t Opcode)
int64_t getImm() const
ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags() const override
bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1, int64_t &Offset2) const override
Class for arbitrary precision integers.
Definition: APInt.h:69
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
bool isDisableWQM(uint16_t Opcode) const
Definition: SIInstrInfo.h:524
bool hasModifiers(unsigned Opcode) const
Return true if this instruction has any modifiers.
static bool isSegmentSpecificFLAT(const MachineInstr &MI)
Definition: SIInstrInfo.h:494
static bool isVOP3(const MachineInstr &MI)
Definition: SIInstrInfo.h:412
bool isLiteralConstant(const MachineOperand &MO, const MCOperandInfo &OpInfo) const
Definition: SIInstrInfo.h:701
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:255
Contains the definition of a TargetInstrInfo class that is common to all AMD GPUs.
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
bool isInlineConstant(const MachineInstr &MI, unsigned OpIdx) const
returns true if the operand OpIdx in MI is a valid inline immediate.
Definition: SIInstrInfo.h:674
Representation of each machine instruction.
Definition: MachineInstr.h:63
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
OperandType
Operands are tagged with one of the values of this enum.
Definition: MCInstrDesc.h:43
static bool isMTBUF(const MachineInstr &MI)
Definition: SIInstrInfo.h:444
void moveToVALU(MachineInstr &MI, MachineDominatorTree *MDT=nullptr) const
Replace this instruction&#39;s opcode with the equivalent VALU opcode.
bool isBranchOffsetInRange(unsigned BranchOpc, int64_t BrOffset) const override
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
static bool isVOPC(const MachineInstr &MI)
Definition: SIInstrInfo.h:428
int16_t RegClass
This specifies the register class enumeration of the operand if the operand is a register.
Definition: MCInstrDesc.h:72
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
#define I(x, y, z)
Definition: MD5.cpp:58
static bool isVMEM(const MachineInstr &MI)
Definition: SIInstrInfo.h:340
MachineBasicBlock * getBranchDestBlock(const MachineInstr &MI) const override
bool hasUnwantedEffectsWhenEXECEmpty(const MachineInstr &MI) const
Whether we must prevent this instruction from executing with EXEC = 0.
bool isHighLatencyInstruction(const MachineInstr &MI) const
LLVM_READONLY int commuteOpcode(const MachineInstr &MI) const
Definition: SIInstrInfo.h:241
bool isLowLatencyInstruction(const MachineInstr &MI) const
uint32_t Size
Definition: Profile.cpp:46
#define LLVM_READONLY
Definition: Compiler.h:183
bool isSALU(uint16_t Opcode) const
Definition: SIInstrInfo.h:328
ArrayRef< std::pair< int, const char * > > getSerializableTargetIndices() const override
unsigned getMovOpcode(const TargetRegisterClass *DstRC) const
bool isVMEM(uint16_t Opcode) const
Definition: SIInstrInfo.h:344
bool isVOP3P(uint16_t Opcode) const
Definition: SIInstrInfo.h:556
bool isReg() const
isReg - Tests if this is a MO_Register operand.
SIInstrInfo(const GCNSubtarget &ST)
Definition: SIInstrInfo.cpp:86
unsigned isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override
static bool isPacked(const MachineInstr &MI)
Definition: SIInstrInfo.h:388
bool isNonUniformBranchInstr(MachineInstr &Instr) const
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static bool isSOP1(const MachineInstr &MI)
Definition: SIInstrInfo.h:348
void legalizeOperandsSMRD(MachineRegisterInfo &MRI, MachineInstr &MI) const
static bool isLegalMUBUFImmOffset(unsigned Imm)
Definition: SIInstrInfo.h:940
const uint64_t RSRC_ELEMENT_SIZE_SHIFT
Definition: SIInstrInfo.h:1040
static bool isScalarUnit(const MachineInstr &MI)
Definition: SIInstrInfo.h:568
unsigned readlaneVGPRToSGPR(unsigned SrcReg, MachineInstr &UseMI, MachineRegisterInfo &MRI) const
Copy a value from a VGPR (SrcReg) to SGPR.
static bool hasIntClamp(const MachineInstr &MI)
Definition: SIInstrInfo.h:614
LLVM Value Representation.
Definition: Value.h:72
static bool isSDWA(const MachineInstr &MI)
Definition: SIInstrInfo.h:420
const TargetRegisterClass * getRegClass(unsigned RCID) const
void legalizeOpWithMove(MachineInstr &MI, unsigned OpIdx) const
Legalize the OpIndex operand of this instruction by inserting a MOV.
MachineInstr * convertToThreeAddress(MachineFunction::iterator &MBB, MachineInstr &MI, LiveVariables *LV) const override
static bool isVGPRSpill(const MachineInstr &MI)
Definition: SIInstrInfo.h:528
unsigned getOpSize(const MachineInstr &MI, unsigned OpNo) const
This form should usually be preferred since it handles operands with unknown register classes...
Definition: SIInstrInfo.h:773
unsigned getMachineCSELookAheadLimit() const override
Definition: SIInstrInfo.h:314
const MCOperandInfo * OpInfo
Definition: MCInstrDesc.h:175
bool shouldScheduleLoadsNear(SDNode *Load0, SDNode *Load1, int64_t Offset0, int64_t Offset1, unsigned NumLoads) const override
void insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const override
IRTranslator LLVM IR MI
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:48
bool isInlineConstant(const MachineInstr &MI, const MachineOperand &UseMO, const MachineOperand &DefMO) const
returns true if UseMO is substituted with DefMO in MI it would be an inline immediate.
Definition: SIInstrInfo.h:660
void legalizeGenericOperand(MachineBasicBlock &InsertMBB, MachineBasicBlock::iterator I, const TargetRegisterClass *DstRC, MachineOperand &Op, MachineRegisterInfo &MRI, const DebugLoc &DL) const
bool isVOP3(uint16_t Opcode) const
Definition: SIInstrInfo.h:416
static bool isKillTerminator(unsigned Opcode)
LLVM_READONLY int getAddr64Inst(uint16_t Opcode)
This holds information about one operand of a machine instruction, indicating the register class for ...
Definition: MCInstrDesc.h:66
static bool usesLGKM_CNT(const MachineInstr &MI)
Definition: SIInstrInfo.h:576
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:415
static bool isVOP1(const MachineInstr &MI)
Definition: SIInstrInfo.h:396
MachineInstr * buildShrunkInst(MachineInstr &MI, unsigned NewOpcode) const
void convertNonUniformIfRegion(MachineBasicBlock *IfEntry, MachineBasicBlock *IfEnd) const
DominatorTree Class - Concrete subclass of DominatorTreeBase that is used to compute a normal dominat...
bool isBufferSMRD(const MachineInstr &MI) const
static bool isDisableWQM(const MachineInstr &MI)
Definition: SIInstrInfo.h:520
bool findCommutedOpIndices(MachineInstr &MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) const override
bool isVALU(uint16_t Opcode) const
Definition: SIInstrInfo.h:336
LLVM_READONLY int getCommuteRev(uint16_t Opcode)
LLVM_READONLY const MachineOperand * getNamedOperand(const MachineInstr &MI, unsigned OpName) const
Definition: SIInstrInfo.h:866
bool isVGPRSpill(uint16_t Opcode) const
Definition: SIInstrInfo.h:532