LLVM  8.0.0svn
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llvm::AMDGPU Namespace Reference

Namespaces

 DPP
 
 EncValues
 
 HSAMD
 
 Hwreg
 
 IsaInfo
 
 PALMD
 
 SDWA
 
 SendMsg
 
 Swizzle
 

Classes

struct  D16ImageDimIntrinsic
 
struct  ImageDimIntrinsicInfo
 
struct  IsaVersion
 Instruction set architecture version. More...
 
struct  MIMGBaseOpcodeInfo
 
struct  MIMGDimInfo
 
struct  MIMGInfo
 
struct  MIMGLZMappingInfo
 
struct  RsrcIntrinsic
 

Enumerations

enum  GPUKind : uint32_t {
  GK_NONE = 0, GK_R600 = 1, GK_R630 = 2, GK_RS880 = 3,
  GK_RV670 = 4, GK_RV710 = 5, GK_RV730 = 6, GK_RV770 = 7,
  GK_CEDAR = 8, GK_CYPRESS = 9, GK_JUNIPER = 10, GK_REDWOOD = 11,
  GK_SUMO = 12, GK_BARTS = 13, GK_CAICOS = 14, GK_CAYMAN = 15,
  GK_TURKS = 16, GK_R600_FIRST = GK_R600, GK_R600_LAST = GK_TURKS, GK_GFX600 = 32,
  GK_GFX601 = 33, GK_GFX700 = 40, GK_GFX701 = 41, GK_GFX702 = 42,
  GK_GFX703 = 43, GK_GFX704 = 44, GK_GFX801 = 50, GK_GFX802 = 51,
  GK_GFX803 = 52, GK_GFX810 = 53, GK_GFX900 = 60, GK_GFX902 = 61,
  GK_GFX904 = 62, GK_GFX906 = 63, GK_GFX909 = 65, GK_AMDGCN_FIRST = GK_GFX600,
  GK_AMDGCN_LAST = GK_GFX909
}
 GPU kinds supported by the AMDGPU target. More...
 
enum  ArchFeatureKind : uint32_t {
  FEATURE_NONE = 0, FEATURE_FMA = 1 << 1, FEATURE_LDEXP = 1 << 2, FEATURE_FP64 = 1 << 3,
  FEATURE_FAST_FMA_F32 = 1 << 4, FEATURE_FAST_DENORMAL_F32 = 1 << 5
}
 
enum  TargetIndex {
  TI_CONSTDATA_START, TI_SCRATCH_RSRC_DWORD0, TI_SCRATCH_RSRC_DWORD1, TI_SCRATCH_RSRC_DWORD2,
  TI_SCRATCH_RSRC_DWORD3
}
 
enum  Fixups { fixup_si_sopp_br = FirstTargetFixupKind, LastTargetFixupKind, NumTargetFixupKinds = LastTargetFixupKind - FirstTargetFixupKind }
 
enum  OperandType {
  OPERAND_REG_IMM_INT32 = MCOI::OPERAND_FIRST_TARGET, OPERAND_REG_IMM_INT64, OPERAND_REG_IMM_INT16, OPERAND_REG_IMM_FP32,
  OPERAND_REG_IMM_FP64, OPERAND_REG_IMM_FP16, OPERAND_REG_INLINE_C_INT16, OPERAND_REG_INLINE_C_INT32,
  OPERAND_REG_INLINE_C_INT64, OPERAND_REG_INLINE_C_FP16, OPERAND_REG_INLINE_C_FP32, OPERAND_REG_INLINE_C_FP64,
  OPERAND_REG_INLINE_C_V2FP16, OPERAND_REG_INLINE_C_V2INT16, OPERAND_REG_IMM_FIRST = OPERAND_REG_IMM_INT32, OPERAND_REG_IMM_LAST = OPERAND_REG_IMM_FP16,
  OPERAND_REG_INLINE_C_FIRST = OPERAND_REG_INLINE_C_INT16, OPERAND_REG_INLINE_C_LAST = OPERAND_REG_INLINE_C_V2INT16, OPERAND_SRC_FIRST = OPERAND_REG_IMM_INT32, OPERAND_SRC_LAST = OPERAND_REG_INLINE_C_LAST,
  OPERAND_INPUT_MODS, OPERAND_SDWA_VOPC_DST, OPERAND_KIMM32, OPERAND_KIMM16
}
 
enum  TargetFlags { TF_LONG_BRANCH_FORWARD = 1 << 0, TF_LONG_BRANCH_BACKWARD = 1 << 1 }
 

Functions

StringRef getArchNameAMDGCN (GPUKind AK)
 
StringRef getArchNameR600 (GPUKind AK)
 
StringRef getCanonicalArchName (StringRef Arch)
 
GPUKind parseArchAMDGCN (StringRef CPU)
 
GPUKind parseArchR600 (StringRef CPU)
 
unsigned getArchAttrAMDGCN (GPUKind AK)
 
unsigned getArchAttrR600 (GPUKind AK)
 
void fillValidArchListAMDGCN (SmallVectorImpl< StringRef > &Values)
 
void fillValidArchListR600 (SmallVectorImpl< StringRef > &Values)
 
IsaVersion getIsaVersion (StringRef GPU)
 
const RsrcIntrinsiclookupRsrcIntrinsic (unsigned Intr)
 
const D16ImageDimIntrinsiclookupD16ImageDimIntrinsic (unsigned Intr)
 
const ImageDimIntrinsicInfogetImageDimIntrinsicInfo (unsigned Intr)
 
LLVM_READONLY int getVOPe64 (uint16_t Opcode)
 
LLVM_READONLY int getVOPe32 (uint16_t Opcode)
 
LLVM_READONLY int getSDWAOp (uint16_t Opcode)
 
LLVM_READONLY int getBasicFromSDWAOp (uint16_t Opcode)
 
LLVM_READONLY int getCommuteRev (uint16_t Opcode)
 
LLVM_READONLY int getCommuteOrig (uint16_t Opcode)
 
LLVM_READONLY int getAddr64Inst (uint16_t Opcode)
 
LLVM_READONLY int getIfAddr64Inst (uint16_t Opcode)
 Check if Opcode is an Addr64 opcode. More...
 
LLVM_READONLY int getMUBUFNoLdsInst (uint16_t Opcode)
 
LLVM_READONLY int getAtomicRetOp (uint16_t Opcode)
 
LLVM_READONLY int getAtomicNoRetOp (uint16_t Opcode)
 
LLVM_READONLY int getSOPKOp (uint16_t Opcode)
 
int getMIMGOpcode (unsigned BaseOpcode, unsigned MIMGEncoding, unsigned VDataDwords, unsigned VAddrDwords)
 
int getMaskedMIMGOp (unsigned Opc, unsigned NewChannels)
 
int getMCOpcode (uint16_t Opcode, unsigned Gen)
 
void initDefaultAMDKernelCodeT (amd_kernel_code_t &Header, const MCSubtargetInfo *STI)
 
amdhsa::kernel_descriptor_t getDefaultAmdhsaKernelDescriptor ()
 
bool isGroupSegment (const GlobalValue *GV)
 
bool isGlobalSegment (const GlobalValue *GV)
 
bool isReadOnlySegment (const GlobalValue *GV)
 
bool shouldEmitConstantsToTextSection (const Triple &TT)
 
int getIntegerAttribute (const Function &F, StringRef Name, int Default)
 
std::pair< int, int > getIntegerPairAttribute (const Function &F, StringRef Name, std::pair< int, int > Default, bool OnlyFirstRequired)
 
unsigned getVmcntBitMask (const IsaVersion &Version)
 
unsigned getExpcntBitMask (const IsaVersion &Version)
 
unsigned getLgkmcntBitMask (const IsaVersion &Version)
 
unsigned getWaitcntBitMask (const IsaVersion &Version)
 
unsigned decodeVmcnt (const IsaVersion &Version, unsigned Waitcnt)
 
unsigned decodeExpcnt (const IsaVersion &Version, unsigned Waitcnt)
 
unsigned decodeLgkmcnt (const IsaVersion &Version, unsigned Waitcnt)
 
void decodeWaitcnt (const IsaVersion &Version, unsigned Waitcnt, unsigned &Vmcnt, unsigned &Expcnt, unsigned &Lgkmcnt)
 Decodes Vmcnt, Expcnt and Lgkmcnt from given Waitcnt for given isa Version, and writes decoded values into Vmcnt, Expcnt and Lgkmcnt respectively. More...
 
unsigned encodeVmcnt (const IsaVersion &Version, unsigned Waitcnt, unsigned Vmcnt)
 
unsigned encodeExpcnt (const IsaVersion &Version, unsigned Waitcnt, unsigned Expcnt)
 
unsigned encodeLgkmcnt (const IsaVersion &Version, unsigned Waitcnt, unsigned Lgkmcnt)
 
unsigned encodeWaitcnt (const IsaVersion &Version, unsigned Vmcnt, unsigned Expcnt, unsigned Lgkmcnt)
 Encodes Vmcnt, Expcnt and Lgkmcnt into Waitcnt for given isa Version. More...
 
unsigned getInitialPSInputAddr (const Function &F)
 
bool isShader (CallingConv::ID cc)
 
bool isCompute (CallingConv::ID cc)
 
bool isEntryFunctionCC (CallingConv::ID CC)
 
bool hasXNACK (const MCSubtargetInfo &STI)
 
bool hasSRAMECC (const MCSubtargetInfo &STI)
 
bool hasMIMG_R128 (const MCSubtargetInfo &STI)
 
bool hasPackedD16 (const MCSubtargetInfo &STI)
 
bool isSI (const MCSubtargetInfo &STI)
 
bool isCI (const MCSubtargetInfo &STI)
 
bool isVI (const MCSubtargetInfo &STI)
 
bool isGFX9 (const MCSubtargetInfo &STI)
 
bool isGCN3Encoding (const MCSubtargetInfo &STI)
 
bool isSGPR (unsigned Reg, const MCRegisterInfo *TRI)
 Is Reg - scalar register. More...
 
bool isRegIntersect (unsigned Reg0, unsigned Reg1, const MCRegisterInfo *TRI)
 Is there any intersection between registers. More...
 
unsigned getMCReg (unsigned Reg, const MCSubtargetInfo &STI)
 If Reg is a pseudo reg, return the correct hardware register given STI otherwise return Reg. More...
 
unsigned mc2PseudoReg (unsigned Reg)
 Convert hardware register Reg to a pseudo register. More...
 
bool isSISrcOperand (const MCInstrDesc &Desc, unsigned OpNo)
 Can this operand also contain immediate values? More...
 
bool isSISrcFPOperand (const MCInstrDesc &Desc, unsigned OpNo)
 Is this floating-point operand? More...
 
bool isSISrcInlinableOperand (const MCInstrDesc &Desc, unsigned OpNo)
 Does this opearnd support only inlinable literals? More...
 
unsigned getRegBitWidth (unsigned RCID)
 Get the size in bits of a register from the register class RC. More...
 
unsigned getRegBitWidth (const MCRegisterClass &RC)
 Get the size in bits of a register from the register class RC. More...
 
unsigned getRegOperandSize (const MCRegisterInfo *MRI, const MCInstrDesc &Desc, unsigned OpNo)
 Get size of register operand. More...
 
bool isInlinableLiteral64 (int64_t Literal, bool HasInv2Pi)
 Is this literal inlinable. More...
 
bool isInlinableLiteral32 (int32_t Literal, bool HasInv2Pi)
 
bool isInlinableLiteral16 (int16_t Literal, bool HasInv2Pi)
 
bool isInlinableLiteralV216 (int32_t Literal, bool HasInv2Pi)
 
bool isArgPassedInSGPR (const Argument *A)
 
int64_t getSMRDEncodedOffset (const MCSubtargetInfo &ST, int64_t ByteOffset)
 
bool isLegalSMRDImmOffset (const MCSubtargetInfo &ST, int64_t ByteOffset)
 
bool splitMUBUFOffset (uint32_t Imm, uint32_t &SOffset, uint32_t &ImmOffset, const GCNSubtarget *Subtarget)
 
bool isIntrinsicSourceOfDivergence (unsigned IntrID)
 
LLVM_READONLY int16_t getNamedOperandIdx (uint16_t Opcode, uint16_t NamedIdx)
 
LLVM_READONLY const MIMGBaseOpcodeInfogetMIMGBaseOpcodeInfo (unsigned BaseOpcode)
 
LLVM_READONLY const MIMGDimInfogetMIMGDimInfo (unsigned Dim)
 
LLVM_READONLY const MIMGLZMappingInfogetMIMGLZMappingInfo (unsigned L)
 
LLVM_READNONE bool isKernel (CallingConv::ID CC)
 
LLVM_READNONE unsigned getOperandSize (const MCOperandInfo &OpInfo)
 
LLVM_READNONE unsigned getOperandSize (const MCInstrDesc &Desc, unsigned OpNo)
 

Variables

const uint64_t RSRC_DATA_FORMAT = 0xf00000000000LL
 
const uint64_t RSRC_ELEMENT_SIZE_SHIFT = (32 + 19)
 
const uint64_t RSRC_INDEX_STRIDE_SHIFT = (32 + 21)
 
const uint64_t RSRC_TID_ENABLE = UINT64_C(1) << (32 + 23)
 

Enumeration Type Documentation

◆ ArchFeatureKind

Enumerator
FEATURE_NONE 
FEATURE_FMA 
FEATURE_LDEXP 
FEATURE_FP64 
FEATURE_FAST_FMA_F32 
FEATURE_FAST_DENORMAL_F32 

Definition at line 335 of file TargetParser.h.

◆ Fixups

Enumerator
fixup_si_sopp_br 

16-bit PC relative fixup for SOPP branch instructions.

LastTargetFixupKind 
NumTargetFixupKinds 

Definition at line 17 of file AMDGPUFixupKinds.h.

◆ GPUKind

GPU kinds supported by the AMDGPU target.

Enumerator
GK_NONE 
GK_R600 
GK_R630 
GK_RS880 
GK_RV670 
GK_RV710 
GK_RV730 
GK_RV770 
GK_CEDAR 
GK_CYPRESS 
GK_JUNIPER 
GK_REDWOOD 
GK_SUMO 
GK_BARTS 
GK_CAICOS 
GK_CAYMAN 
GK_TURKS 
GK_R600_FIRST 
GK_R600_LAST 
GK_GFX600 
GK_GFX601 
GK_GFX700 
GK_GFX701 
GK_GFX702 
GK_GFX703 
GK_GFX704 
GK_GFX801 
GK_GFX802 
GK_GFX803 
GK_GFX810 
GK_GFX900 
GK_GFX902 
GK_GFX904 
GK_GFX906 
GK_GFX909 
GK_AMDGCN_FIRST 
GK_AMDGCN_LAST 

Definition at line 276 of file TargetParser.h.

◆ OperandType

Enumerator
OPERAND_REG_IMM_INT32 

Operands with register or 32-bit immediate.

OPERAND_REG_IMM_INT64 
OPERAND_REG_IMM_INT16 
OPERAND_REG_IMM_FP32 
OPERAND_REG_IMM_FP64 
OPERAND_REG_IMM_FP16 
OPERAND_REG_INLINE_C_INT16 

Operands with register or inline constant.

OPERAND_REG_INLINE_C_INT32 
OPERAND_REG_INLINE_C_INT64 
OPERAND_REG_INLINE_C_FP16 
OPERAND_REG_INLINE_C_FP32 
OPERAND_REG_INLINE_C_FP64 
OPERAND_REG_INLINE_C_V2FP16 
OPERAND_REG_INLINE_C_V2INT16 
OPERAND_REG_IMM_FIRST 
OPERAND_REG_IMM_LAST 
OPERAND_REG_INLINE_C_FIRST 
OPERAND_REG_INLINE_C_LAST 
OPERAND_SRC_FIRST 
OPERAND_SRC_LAST 
OPERAND_INPUT_MODS 
OPERAND_SDWA_VOPC_DST 
OPERAND_KIMM32 

Operand with 32-bit immediate that uses the constant bus.

OPERAND_KIMM16 

Definition at line 111 of file SIDefines.h.

◆ TargetFlags

Enumerator
TF_LONG_BRANCH_FORWARD 
TF_LONG_BRANCH_BACKWARD 

Definition at line 963 of file SIInstrInfo.h.

◆ TargetIndex

Enumerator
TI_CONSTDATA_START 
TI_SCRATCH_RSRC_DWORD0 
TI_SCRATCH_RSRC_DWORD1 
TI_SCRATCH_RSRC_DWORD2 
TI_SCRATCH_RSRC_DWORD3 

Definition at line 217 of file AMDGPU.h.

Function Documentation

◆ decodeExpcnt()

unsigned llvm::AMDGPU::decodeExpcnt ( const IsaVersion Version,
unsigned  Waitcnt 
)
Returns
Decoded Expcnt from given Waitcnt for given isa Version.

Definition at line 509 of file AMDGPUBaseInfo.cpp.

Referenced by decodeWaitcnt(), encodeCnt(), and readsVCCZ().

◆ decodeLgkmcnt()

unsigned llvm::AMDGPU::decodeLgkmcnt ( const IsaVersion Version,
unsigned  Waitcnt 
)
Returns
Decoded Lgkmcnt from given Waitcnt for given isa Version.

Definition at line 513 of file AMDGPUBaseInfo.cpp.

Referenced by decodeWaitcnt(), encodeCnt(), and readsVCCZ().

◆ decodeVmcnt()

unsigned llvm::AMDGPU::decodeVmcnt ( const IsaVersion Version,
unsigned  Waitcnt 
)
Returns
Decoded Vmcnt from given Waitcnt for given isa Version.

Definition at line 497 of file AMDGPUBaseInfo.cpp.

References llvm::AMDGPU::IsaVersion::Major.

Referenced by decodeWaitcnt(), encodeCnt(), and readsVCCZ().

◆ decodeWaitcnt()

void llvm::AMDGPU::decodeWaitcnt ( const IsaVersion Version,
unsigned  Waitcnt,
unsigned Vmcnt,
unsigned Expcnt,
unsigned Lgkmcnt 
)

Decodes Vmcnt, Expcnt and Lgkmcnt from given Waitcnt for given isa Version, and writes decoded values into Vmcnt, Expcnt and Lgkmcnt respectively.

Vmcnt, Expcnt and Lgkmcnt are decoded as follows: Vmcnt = Waitcnt[3:0] (pre-gfx9 only) Vmcnt = Waitcnt[3:0] | Waitcnt[15:14] (gfx9+ only) Expcnt = Waitcnt[6:4] Lgkmcnt = Waitcnt[11:8]

Definition at line 517 of file AMDGPUBaseInfo.cpp.

References decodeExpcnt(), decodeLgkmcnt(), and decodeVmcnt().

Referenced by llvm::AMDGPUInstPrinter::printWaitFlag().

◆ encodeExpcnt()

unsigned llvm::AMDGPU::encodeExpcnt ( const IsaVersion Version,
unsigned  Waitcnt,
unsigned  Expcnt 
)
Returns
Waitcnt with encoded Expcnt for given isa Version.

Definition at line 535 of file AMDGPUBaseInfo.cpp.

Referenced by encodeCnt(), and encodeWaitcnt().

◆ encodeLgkmcnt()

unsigned llvm::AMDGPU::encodeLgkmcnt ( const IsaVersion Version,
unsigned  Waitcnt,
unsigned  Lgkmcnt 
)
Returns
Waitcnt with encoded Lgkmcnt for given isa Version.

Definition at line 540 of file AMDGPUBaseInfo.cpp.

Referenced by encodeCnt(), and encodeWaitcnt().

◆ encodeVmcnt()

unsigned llvm::AMDGPU::encodeVmcnt ( const IsaVersion Version,
unsigned  Waitcnt,
unsigned  Vmcnt 
)
Returns
Waitcnt with encoded Vmcnt for given isa Version.

Definition at line 524 of file AMDGPUBaseInfo.cpp.

References llvm::AMDGPU::IsaVersion::Major.

Referenced by encodeCnt(), and encodeWaitcnt().

◆ encodeWaitcnt()

unsigned llvm::AMDGPU::encodeWaitcnt ( const IsaVersion Version,
unsigned  Vmcnt,
unsigned  Expcnt,
unsigned  Lgkmcnt 
)

Encodes Vmcnt, Expcnt and Lgkmcnt into Waitcnt for given isa Version.

Vmcnt, Expcnt and Lgkmcnt are encoded as follows: Waitcnt[3:0] = Vmcnt (pre-gfx9 only) Waitcnt[3:0] = Vmcnt[3:0] (gfx9+ only) Waitcnt[6:4] = Expcnt Waitcnt[11:8] = Lgkmcnt Waitcnt[15:14] = Vmcnt[5:4] (gfx9+ only)

Returns
Waitcnt with encoded Vmcnt, Expcnt and Lgkmcnt for given isa Version.

Definition at line 545 of file AMDGPUBaseInfo.cpp.

References encodeExpcnt(), encodeLgkmcnt(), encodeVmcnt(), and getWaitcntBitMask().

Referenced by readsVCCZ().

◆ fillValidArchListAMDGCN()

void llvm::AMDGPU::fillValidArchListAMDGCN ( SmallVectorImpl< StringRef > &  Values)

◆ fillValidArchListR600()

void llvm::AMDGPU::fillValidArchListR600 ( SmallVectorImpl< StringRef > &  Values)

◆ getAddr64Inst()

LLVM_READONLY int llvm::AMDGPU::getAddr64Inst ( uint16_t  Opcode)

◆ getArchAttrAMDGCN()

unsigned llvm::AMDGPU::getArchAttrAMDGCN ( GPUKind  AK)

Definition at line 1081 of file TargetParser.cpp.

References FEATURE_NONE.

◆ getArchAttrR600()

unsigned llvm::AMDGPU::getArchAttrR600 ( GPUKind  AK)

Definition at line 1087 of file TargetParser.cpp.

References FEATURE_NONE.

◆ getArchNameAMDGCN()

StringRef llvm::AMDGPU::getArchNameAMDGCN ( GPUKind  AK)

◆ getArchNameR600()

StringRef llvm::AMDGPU::getArchNameR600 ( GPUKind  AK)

◆ getAtomicNoRetOp()

LLVM_READONLY int llvm::AMDGPU::getAtomicNoRetOp ( uint16_t  Opcode)

◆ getAtomicRetOp()

LLVM_READONLY int llvm::AMDGPU::getAtomicRetOp ( uint16_t  Opcode)

◆ getBasicFromSDWAOp()

LLVM_READONLY int llvm::AMDGPU::getBasicFromSDWAOp ( uint16_t  Opcode)

◆ getCanonicalArchName()

StringRef llvm::AMDGPU::getCanonicalArchName ( StringRef  Arch)

◆ getCommuteOrig()

LLVM_READONLY int llvm::AMDGPU::getCommuteOrig ( uint16_t  Opcode)

◆ getCommuteRev()

LLVM_READONLY int llvm::AMDGPU::getCommuteRev ( uint16_t  Opcode)

◆ getDefaultAmdhsaKernelDescriptor()

amdhsa::kernel_descriptor_t llvm::AMDGPU::getDefaultAmdhsaKernelDescriptor ( )

◆ getExpcntBitMask()

unsigned llvm::AMDGPU::getExpcntBitMask ( const IsaVersion Version)
Returns
Expcnt bit mask for given isa Version.

Definition at line 477 of file AMDGPUBaseInfo.cpp.

Referenced by llvm::AMDGPUInstPrinter::printWaitFlag(), and readsVCCZ().

◆ getIfAddr64Inst()

LLVM_READONLY int llvm::AMDGPU::getIfAddr64Inst ( uint16_t  Opcode)

Check if Opcode is an Addr64 opcode.

Returns
Opcode if it is an Addr64 opcode, otherwise -1.

Referenced by llvm::SIInstrInfo::isLegalMUBUFImmOffset(), and llvm::SIInstrInfo::legalizeOperands().

◆ getImageDimIntrinsicInfo()

const ImageDimIntrinsicInfo* llvm::AMDGPU::getImageDimIntrinsicInfo ( unsigned  Intr)

◆ getInitialPSInputAddr()

unsigned llvm::AMDGPU::getInitialPSInputAddr ( const Function F)

◆ getIntegerAttribute()

int llvm::AMDGPU::getIntegerAttribute ( const Function F,
StringRef  Name,
int  Default 
)

◆ getIntegerPairAttribute()

std::pair< int, int > llvm::AMDGPU::getIntegerPairAttribute ( const Function F,
StringRef  Name,
std::pair< int, int >  Default,
bool  OnlyFirstRequired = false 
)
Returns
A pair of integer values requested using F's Name attribute in "first[,second]" format ("second" is optional unless OnlyFirstRequired is false).
Default if attribute is not present.
Default and emits error if one of the requested values cannot be converted to integer, or OnlyFirstRequired is false and "second" value is not present.

Definition at line 443 of file AMDGPUBaseInfo.cpp.

References llvm::LLVMContext::emitError(), llvm::Function::getContext(), llvm::Function::getFnAttribute(), llvm::Attribute::getValueAsString(), llvm::Attribute::isStringAttribute(), and llvm::StringRef::split().

Referenced by llvm::AMDGPUSubtarget::getFlatWorkGroupSizes(), and llvm::AMDGPUSubtarget::getWavesPerEU().

◆ getIsaVersion()

AMDGPU::IsaVersion llvm::AMDGPU::getIsaVersion ( StringRef  GPU)

◆ getLgkmcntBitMask()

unsigned llvm::AMDGPU::getLgkmcntBitMask ( const IsaVersion Version)
Returns
Lgkmcnt bit mask for given isa Version.

Definition at line 481 of file AMDGPUBaseInfo.cpp.

Referenced by llvm::AMDGPUInstPrinter::printWaitFlag(), and readsVCCZ().

◆ getMaskedMIMGOp()

LLVM_READONLY int llvm::AMDGPU::getMaskedMIMGOp ( unsigned  Opc,
unsigned  NewChannels 
)

◆ getMCOpcode()

LLVM_READONLY int llvm::AMDGPU::getMCOpcode ( uint16_t  Opcode,
unsigned  Gen 
)

Definition at line 134 of file AMDGPUBaseInfo.cpp.

Referenced by llvm::SIInstrInfo::pseudoToMCOpcode().

◆ getMCReg()

unsigned llvm::AMDGPU::getMCReg ( unsigned  Reg,
const MCSubtargetInfo STI 
)

If Reg is a pseudo reg, return the correct hardware register given STI otherwise return Reg.

Definition at line 692 of file AMDGPUBaseInfo.cpp.

References llvm::Triple::getArch(), llvm::MCSubtargetInfo::getTargetTriple(), MAP_REG2REG, and llvm::Triple::r600.

Referenced by llvm::AMDGPUDisassembler::createRegOperand(), getVariantKind(), and isKernel().

◆ getMIMGBaseOpcodeInfo()

LLVM_READONLY const MIMGBaseOpcodeInfo* llvm::AMDGPU::getMIMGBaseOpcodeInfo ( unsigned  BaseOpcode)

Referenced by parseCachePolicy().

◆ getMIMGDimInfo()

LLVM_READONLY const MIMGDimInfo* llvm::AMDGPU::getMIMGDimInfo ( unsigned  Dim)

Referenced by parseCachePolicy().

◆ getMIMGLZMappingInfo()

LLVM_READONLY const MIMGLZMappingInfo* llvm::AMDGPU::getMIMGLZMappingInfo ( unsigned  L)

Referenced by parseCachePolicy().

◆ getMIMGOpcode()

LLVM_READONLY int llvm::AMDGPU::getMIMGOpcode ( unsigned  BaseOpcode,
unsigned  MIMGEncoding,
unsigned  VDataDwords,
unsigned  VAddrDwords 
)

Definition at line 116 of file AMDGPUBaseInfo.cpp.

References llvm::AMDGPU::MIMGInfo::Opcode.

Referenced by parseCachePolicy().

◆ getMUBUFNoLdsInst()

LLVM_READONLY int llvm::AMDGPU::getMUBUFNoLdsInst ( uint16_t  Opcode)

◆ getNamedOperandIdx()

LLVM_READONLY int16_t llvm::AMDGPU::getNamedOperandIdx ( uint16_t  Opcode,
uint16_t  NamedIdx 
)

◆ getOperandSize() [1/2]

LLVM_READNONE unsigned llvm::AMDGPU::getOperandSize ( const MCOperandInfo OpInfo)
inline

◆ getOperandSize() [2/2]

LLVM_READNONE unsigned llvm::AMDGPU::getOperandSize ( const MCInstrDesc Desc,
unsigned  OpNo 
)
inline

◆ getRegBitWidth() [1/2]

unsigned llvm::AMDGPU::getRegBitWidth ( unsigned  RCID)

◆ getRegBitWidth() [2/2]

unsigned llvm::AMDGPU::getRegBitWidth ( const MCRegisterClass RC)

Get the size in bits of a register from the register class RC.

Definition at line 775 of file AMDGPUBaseInfo.cpp.

References llvm::MCRegisterClass::getID(), and getRegBitWidth().

◆ getRegOperandSize()

unsigned llvm::AMDGPU::getRegOperandSize ( const MCRegisterInfo MRI,
const MCInstrDesc Desc,
unsigned  OpNo 
)

◆ getSDWAOp()

LLVM_READONLY int llvm::AMDGPU::getSDWAOp ( uint16_t  Opcode)

◆ getSMRDEncodedOffset()

int64_t llvm::AMDGPU::getSMRDEncodedOffset ( const MCSubtargetInfo ST,
int64_t  ByteOffset 
)
Returns
The encoding that will be used for ByteOffset in the SMRD offset field.

Definition at line 882 of file AMDGPUBaseInfo.cpp.

References isGCN3Encoding().

Referenced by canMoveInstsAcrossMemOp(), getOperandSize(), getSmrdOpcode(), isLegalSMRDImmOffset(), and isStackPtrRelative().

◆ getSOPKOp()

LLVM_READONLY int llvm::AMDGPU::getSOPKOp ( uint16_t  Opcode)

◆ getVmcntBitMask()

unsigned llvm::AMDGPU::getVmcntBitMask ( const IsaVersion Version)
Returns
Vmcnt bit mask for given isa Version.

Definition at line 468 of file AMDGPUBaseInfo.cpp.

References llvm::AMDGPU::IsaVersion::Major.

Referenced by llvm::AMDGPUInstPrinter::printWaitFlag(), and readsVCCZ().

◆ getVOPe32()

LLVM_READONLY int llvm::AMDGPU::getVOPe32 ( uint16_t  Opcode)

◆ getVOPe64()

LLVM_READONLY int llvm::AMDGPU::getVOPe64 ( uint16_t  Opcode)

◆ getWaitcntBitMask()

unsigned llvm::AMDGPU::getWaitcntBitMask ( const IsaVersion Version)
Returns
Waitcnt bit mask for given isa Version.

Definition at line 485 of file AMDGPUBaseInfo.cpp.

References llvm::AMDGPU::IsaVersion::Major.

Referenced by encodeCnt(), and encodeWaitcnt().

◆ hasMIMG_R128()

bool llvm::AMDGPU::hasMIMG_R128 ( const MCSubtargetInfo STI)

Definition at line 602 of file AMDGPUBaseInfo.cpp.

References llvm::MCSubtargetInfo::getFeatureBits().

Referenced by isKernel().

◆ hasPackedD16()

bool llvm::AMDGPU::hasPackedD16 ( const MCSubtargetInfo STI)

◆ hasSRAMECC()

bool llvm::AMDGPU::hasSRAMECC ( const MCSubtargetInfo STI)

◆ hasXNACK()

bool llvm::AMDGPU::hasXNACK ( const MCSubtargetInfo STI)

◆ initDefaultAMDKernelCodeT()

void llvm::AMDGPU::initDefaultAMDKernelCodeT ( amd_kernel_code_t Header,
const MCSubtargetInfo STI 
)

◆ isArgPassedInSGPR()

bool llvm::AMDGPU::isArgPassedInSGPR ( const Argument A)

◆ isCI()

bool llvm::AMDGPU::isCI ( const MCSubtargetInfo STI)

◆ isCompute()

LLVM_READNONE bool llvm::AMDGPU::isCompute ( CallingConv::ID  cc)

◆ isEntryFunctionCC()

LLVM_READNONE bool llvm::AMDGPU::isEntryFunctionCC ( CallingConv::ID  CC)

◆ isGCN3Encoding()

bool llvm::AMDGPU::isGCN3Encoding ( const MCSubtargetInfo STI)

◆ isGFX9()

bool llvm::AMDGPU::isGFX9 ( const MCSubtargetInfo STI)

Definition at line 622 of file AMDGPUBaseInfo.cpp.

References llvm::MCSubtargetInfo::getFeatureBits().

Referenced by isKernel().

◆ isGlobalSegment()

bool llvm::AMDGPU::isGlobalSegment ( const GlobalValue GV)

◆ isGroupSegment()

bool llvm::AMDGPU::isGroupSegment ( const GlobalValue GV)

◆ isInlinableLiteral16()

LLVM_READNONE bool llvm::AMDGPU::isInlinableLiteral16 ( int16_t  Literal,
bool  HasInv2Pi 
)

◆ isInlinableLiteral32()

LLVM_READNONE bool llvm::AMDGPU::isInlinableLiteral32 ( int32_t  Literal,
bool  HasInv2Pi 
)

◆ isInlinableLiteral64()

LLVM_READNONE bool llvm::AMDGPU::isInlinableLiteral64 ( int64_t  Literal,
bool  HasInv2Pi 
)

Is this literal inlinable.

Definition at line 786 of file AMDGPUBaseInfo.cpp.

References llvm::DoubleToBits().

Referenced by getOperandSize(), getSpecialRegForName(), and llvm::SIInstrInfo::isInlineConstant().

◆ isInlinableLiteralV216()

LLVM_READNONE bool llvm::AMDGPU::isInlinableLiteralV216 ( int32_t  Literal,
bool  HasInv2Pi 
)

◆ isIntrinsicSourceOfDivergence()

bool llvm::AMDGPU::isIntrinsicSourceOfDivergence ( unsigned  IntrID)
Returns
true if the intrinsic is divergent

Definition at line 949 of file AMDGPUBaseInfo.cpp.

Referenced by getOperandSize(), llvm::SITargetLowering::isSDNodeSourceOfDivergence(), and llvm::GCNTTIImpl::isSourceOfDivergence().

◆ isKernel()

LLVM_READNONE bool llvm::AMDGPU::isKernel ( CallingConv::ID  CC)
inline

◆ isLegalSMRDImmOffset()

bool llvm::AMDGPU::isLegalSMRDImmOffset ( const MCSubtargetInfo ST,
int64_t  ByteOffset 
)
Returns
true if this offset is small enough to fit in the SMRD offset field. ByteOffset should be the offset in bytes and not the encoded offset.

Definition at line 888 of file AMDGPUBaseInfo.cpp.

References getSMRDEncodedOffset(), isGCN3Encoding(), and llvm::isUInt< 8 >().

Referenced by getOperandSize(), getSmrdOpcode(), and isStackPtrRelative().

◆ isReadOnlySegment()

bool llvm::AMDGPU::isReadOnlySegment ( const GlobalValue GV)

◆ isRegIntersect()

bool llvm::AMDGPU::isRegIntersect ( unsigned  Reg0,
unsigned  Reg1,
const MCRegisterInfo TRI 
)

Is there any intersection between registers.

Definition at line 637 of file AMDGPUBaseInfo.cpp.

Referenced by getSpecialRegForName(), and isKernel().

◆ isSGPR()

bool llvm::AMDGPU::isSGPR ( unsigned  Reg,
const MCRegisterInfo TRI 
)

◆ isShader()

LLVM_READNONE bool llvm::AMDGPU::isShader ( CallingConv::ID  cc)

◆ isSI()

bool llvm::AMDGPU::isSI ( const MCSubtargetInfo STI)

◆ isSISrcFPOperand()

bool llvm::AMDGPU::isSISrcFPOperand ( const MCInstrDesc Desc,
unsigned  OpNo 
)

◆ isSISrcInlinableOperand()

bool llvm::AMDGPU::isSISrcInlinableOperand ( const MCInstrDesc Desc,
unsigned  OpNo 
)

Does this opearnd support only inlinable literals?

Definition at line 736 of file AMDGPUBaseInfo.cpp.

References assert(), llvm::MCInstrDesc::NumOperands, OPERAND_REG_INLINE_C_FIRST, OPERAND_REG_INLINE_C_LAST, llvm::MCOperandInfo::OperandType, and llvm::MCInstrDesc::OpInfo.

Referenced by isKernel().

◆ isSISrcOperand()

bool llvm::AMDGPU::isSISrcOperand ( const MCInstrDesc Desc,
unsigned  OpNo 
)

◆ isVI()

bool llvm::AMDGPU::isVI ( const MCSubtargetInfo STI)

◆ lookupD16ImageDimIntrinsic()

const D16ImageDimIntrinsic* llvm::AMDGPU::lookupD16ImageDimIntrinsic ( unsigned  Intr)

◆ lookupRsrcIntrinsic()

const RsrcIntrinsic* llvm::AMDGPU::lookupRsrcIntrinsic ( unsigned  Intr)

◆ mc2PseudoReg()

LLVM_READNONE unsigned llvm::AMDGPU::mc2PseudoReg ( unsigned  Reg)

Convert hardware register Reg to a pseudo register.

Definition at line 704 of file AMDGPUBaseInfo.cpp.

References MAP_REG2REG.

Referenced by getLit64Encoding(), getSpecialRegForName(), and isKernel().

◆ parseArchAMDGCN()

AMDGPU::GPUKind llvm::AMDGPU::parseArchAMDGCN ( StringRef  CPU)

Definition at line 1063 of file TargetParser.cpp.

References C, and GK_NONE.

Referenced by llvm::AMDGPUTargetStreamer::getElfMach(), and getIsaVersion().

◆ parseArchR600()

AMDGPU::GPUKind llvm::AMDGPU::parseArchR600 ( StringRef  CPU)

Definition at line 1072 of file TargetParser.cpp.

References C, and GK_NONE.

Referenced by llvm::AMDGPUTargetStreamer::getElfMach().

◆ shouldEmitConstantsToTextSection()

bool llvm::AMDGPU::shouldEmitConstantsToTextSection ( const Triple TT)
Returns
True if constants should be emitted to .text section for given target triple TT, false otherwise.

Definition at line 424 of file AMDGPUBaseInfo.cpp.

References llvm::Triple::AMDHSA, and llvm::Triple::getOS().

Referenced by findUser(), and llvm::AMDGPUTargetObjectFile::SelectSectionForGlobal().

◆ splitMUBUFOffset()

bool llvm::AMDGPU::splitMUBUFOffset ( uint32_t  Imm,
uint32_t SOffset,
uint32_t ImmOffset,
const GCNSubtarget Subtarget 
)

Variable Documentation

◆ RSRC_DATA_FORMAT

const uint64_t llvm::AMDGPU::RSRC_DATA_FORMAT = 0xf00000000000LL

◆ RSRC_ELEMENT_SIZE_SHIFT

const uint64_t llvm::AMDGPU::RSRC_ELEMENT_SIZE_SHIFT = (32 + 19)

Definition at line 958 of file SIInstrInfo.h.

Referenced by llvm::SIInstrInfo::getScratchRsrcWords23().

◆ RSRC_INDEX_STRIDE_SHIFT

const uint64_t llvm::AMDGPU::RSRC_INDEX_STRIDE_SHIFT = (32 + 21)

Definition at line 959 of file SIInstrInfo.h.

Referenced by llvm::SIInstrInfo::getScratchRsrcWords23().

◆ RSRC_TID_ENABLE

const uint64_t llvm::AMDGPU::RSRC_TID_ENABLE = UINT64_C(1) << (32 + 23)

Definition at line 960 of file SIInstrInfo.h.

Referenced by llvm::SIInstrInfo::getScratchRsrcWords23().