LLVM  7.0.0svn
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llvm::AMDGPU Namespace Reference

Namespaces

 DPP
 
 EncValues
 
 HSAMD
 
 Hwreg
 
 IsaInfo
 
 PALMD
 
 SDWA
 
 SendMsg
 
 Swizzle
 

Classes

struct  D16ImageDimIntrinsic
 
struct  RsrcIntrinsic
 

Enumerations

enum  TargetIndex {
  TI_CONSTDATA_START, TI_SCRATCH_RSRC_DWORD0, TI_SCRATCH_RSRC_DWORD1, TI_SCRATCH_RSRC_DWORD2,
  TI_SCRATCH_RSRC_DWORD3
}
 
enum  Fixups { fixup_si_sopp_br = FirstTargetFixupKind, LastTargetFixupKind, NumTargetFixupKinds = LastTargetFixupKind - FirstTargetFixupKind }
 
enum  OperandType {
  OPERAND_REG_IMM_INT32 = MCOI::OPERAND_FIRST_TARGET, OPERAND_REG_IMM_INT64, OPERAND_REG_IMM_INT16, OPERAND_REG_IMM_FP32,
  OPERAND_REG_IMM_FP64, OPERAND_REG_IMM_FP16, OPERAND_REG_INLINE_C_INT16, OPERAND_REG_INLINE_C_INT32,
  OPERAND_REG_INLINE_C_INT64, OPERAND_REG_INLINE_C_FP16, OPERAND_REG_INLINE_C_FP32, OPERAND_REG_INLINE_C_FP64,
  OPERAND_REG_INLINE_C_V2FP16, OPERAND_REG_INLINE_C_V2INT16, OPERAND_REG_IMM_FIRST = OPERAND_REG_IMM_INT32, OPERAND_REG_IMM_LAST = OPERAND_REG_IMM_FP16,
  OPERAND_REG_INLINE_C_FIRST = OPERAND_REG_INLINE_C_INT16, OPERAND_REG_INLINE_C_LAST = OPERAND_REG_INLINE_C_V2INT16, OPERAND_SRC_FIRST = OPERAND_REG_IMM_INT32, OPERAND_SRC_LAST = OPERAND_REG_INLINE_C_LAST,
  OPERAND_INPUT_MODS, OPERAND_SDWA_VOPC_DST, OPERAND_KIMM32, OPERAND_KIMM16
}
 
enum  TargetFlags { TF_LONG_BRANCH_FORWARD = 1 << 0, TF_LONG_BRANCH_BACKWARD = 1 << 1 }
 

Functions

AMDGPUAS getAMDGPUAS (const Module &M)
 
AMDGPUAS getAMDGPUAS (const TargetMachine &TM)
 
AMDGPUAS getAMDGPUAS (Triple T)
 
const RsrcIntrinsiclookupRsrcIntrinsicByIntr (unsigned Intr)
 
const D16ImageDimIntrinsiclookupD16ImageDimIntrinsicByIntr (unsigned Intr)
 
int getLDSNoRetOp (uint16_t Opcode)
 
LLVM_READONLY int getVOPe64 (uint16_t Opcode)
 
LLVM_READONLY int getVOPe32 (uint16_t Opcode)
 
LLVM_READONLY int getSDWAOp (uint16_t Opcode)
 
LLVM_READONLY int getBasicFromSDWAOp (uint16_t Opcode)
 
LLVM_READONLY int getCommuteRev (uint16_t Opcode)
 
LLVM_READONLY int getCommuteOrig (uint16_t Opcode)
 
LLVM_READONLY int getAddr64Inst (uint16_t Opcode)
 
LLVM_READONLY int getMUBUFNoLdsInst (uint16_t Opcode)
 
LLVM_READONLY int getAtomicRetOp (uint16_t Opcode)
 
LLVM_READONLY int getAtomicNoRetOp (uint16_t Opcode)
 
LLVM_READONLY int getSOPKOp (uint16_t Opcode)
 
static LLVM_READNONE Channels indexToChannel (unsigned Channel)
 
static unsigned rcToChannels (unsigned RCID)
 
int getMaskedMIMGOp (const MCInstrInfo &MII, unsigned Opc, unsigned NewChannels)
 
int getMaskedMIMGAtomicOp (const MCInstrInfo &MII, unsigned Opc, unsigned NewChannels)
 
int getMCOpcode (uint16_t Opcode, unsigned Gen)
 
void initDefaultAMDKernelCodeT (amd_kernel_code_t &Header, const FeatureBitset &Features)
 
bool isGroupSegment (const GlobalValue *GV)
 
bool isGlobalSegment (const GlobalValue *GV)
 
bool isReadOnlySegment (const GlobalValue *GV)
 
bool shouldEmitConstantsToTextSection (const Triple &TT)
 
int getIntegerAttribute (const Function &F, StringRef Name, int Default)
 
std::pair< int, int > getIntegerPairAttribute (const Function &F, StringRef Name, std::pair< int, int > Default, bool OnlyFirstRequired)
 
unsigned getVmcntBitMask (const IsaInfo::IsaVersion &Version)
 
unsigned getExpcntBitMask (const IsaInfo::IsaVersion &Version)
 
unsigned getLgkmcntBitMask (const IsaInfo::IsaVersion &Version)
 
unsigned getWaitcntBitMask (const IsaInfo::IsaVersion &Version)
 
unsigned decodeVmcnt (const IsaInfo::IsaVersion &Version, unsigned Waitcnt)
 
unsigned decodeExpcnt (const IsaInfo::IsaVersion &Version, unsigned Waitcnt)
 
unsigned decodeLgkmcnt (const IsaInfo::IsaVersion &Version, unsigned Waitcnt)
 
void decodeWaitcnt (const IsaInfo::IsaVersion &Version, unsigned Waitcnt, unsigned &Vmcnt, unsigned &Expcnt, unsigned &Lgkmcnt)
 Decodes Vmcnt, Expcnt and Lgkmcnt from given Waitcnt for given isa Version, and writes decoded values into Vmcnt, Expcnt and Lgkmcnt respectively. More...
 
unsigned encodeVmcnt (const IsaInfo::IsaVersion &Version, unsigned Waitcnt, unsigned Vmcnt)
 
unsigned encodeExpcnt (const IsaInfo::IsaVersion &Version, unsigned Waitcnt, unsigned Expcnt)
 
unsigned encodeLgkmcnt (const IsaInfo::IsaVersion &Version, unsigned Waitcnt, unsigned Lgkmcnt)
 
unsigned encodeWaitcnt (const IsaInfo::IsaVersion &Version, unsigned Vmcnt, unsigned Expcnt, unsigned Lgkmcnt)
 Encodes Vmcnt, Expcnt and Lgkmcnt into Waitcnt for given isa Version. More...
 
unsigned getInitialPSInputAddr (const Function &F)
 
bool isShader (CallingConv::ID cc)
 
bool isCompute (CallingConv::ID cc)
 
bool isEntryFunctionCC (CallingConv::ID CC)
 
bool hasXNACK (const MCSubtargetInfo &STI)
 
bool hasMIMG_R128 (const MCSubtargetInfo &STI)
 
bool hasPackedD16 (const MCSubtargetInfo &STI)
 
bool isSI (const MCSubtargetInfo &STI)
 
bool isCI (const MCSubtargetInfo &STI)
 
bool isVI (const MCSubtargetInfo &STI)
 
bool isGFX9 (const MCSubtargetInfo &STI)
 
bool isGCN3Encoding (const MCSubtargetInfo &STI)
 
bool isSGPR (unsigned Reg, const MCRegisterInfo *TRI)
 Is Reg - scalar register. More...
 
bool isRegIntersect (unsigned Reg0, unsigned Reg1, const MCRegisterInfo *TRI)
 Is there any intersection between registers. More...
 
unsigned getMCReg (unsigned Reg, const MCSubtargetInfo &STI)
 If Reg is a pseudo reg, return the correct hardware register given STI otherwise return Reg. More...
 
unsigned mc2PseudoReg (unsigned Reg)
 Convert hardware register Reg to a pseudo register. More...
 
bool isSISrcOperand (const MCInstrDesc &Desc, unsigned OpNo)
 Can this operand also contain immediate values? More...
 
bool isSISrcFPOperand (const MCInstrDesc &Desc, unsigned OpNo)
 Is this floating-point operand? More...
 
bool isSISrcInlinableOperand (const MCInstrDesc &Desc, unsigned OpNo)
 Does this opearnd support only inlinable literals? More...
 
unsigned getRegBitWidth (unsigned RCID)
 Get the size in bits of a register from the register class RC. More...
 
unsigned getRegBitWidth (const MCRegisterClass &RC)
 Get the size in bits of a register from the register class RC. More...
 
unsigned getRegOperandSize (const MCRegisterInfo *MRI, const MCInstrDesc &Desc, unsigned OpNo)
 Get size of register operand. More...
 
bool isInlinableLiteral64 (int64_t Literal, bool HasInv2Pi)
 Is this literal inlinable. More...
 
bool isInlinableLiteral32 (int32_t Literal, bool HasInv2Pi)
 
bool isInlinableLiteral16 (int16_t Literal, bool HasInv2Pi)
 
bool isInlinableLiteralV216 (int32_t Literal, bool HasInv2Pi)
 
bool isArgPassedInSGPR (const Argument *A)
 
int64_t getSMRDEncodedOffset (const MCSubtargetInfo &ST, int64_t ByteOffset)
 
bool isLegalSMRDImmOffset (const MCSubtargetInfo &ST, int64_t ByteOffset)
 
bool isIntrinsicSourceOfDivergence (unsigned IntrID)
 
LLVM_READONLY int16_t getNamedOperandIdx (uint16_t Opcode, uint16_t NamedIdx)
 
LLVM_READNONE bool isKernel (CallingConv::ID CC)
 
LLVM_READNONE unsigned getOperandSize (const MCOperandInfo &OpInfo)
 
LLVM_READNONE unsigned getOperandSize (const MCInstrDesc &Desc, unsigned OpNo)
 
bool laneDominates (MachineBasicBlock *A, MachineBasicBlock *B)
 

Variables

const uint64_t RSRC_DATA_FORMAT = 0xf00000000000LL
 
const uint64_t RSRC_ELEMENT_SIZE_SHIFT = (32 + 19)
 
const uint64_t RSRC_INDEX_STRIDE_SHIFT = (32 + 21)
 
const uint64_t RSRC_TID_ENABLE = UINT64_C(1) << (32 + 23)
 

Enumeration Type Documentation

◆ Fixups

Enumerator
fixup_si_sopp_br 

16-bit PC relative fixup for SOPP branch instructions.

LastTargetFixupKind 
NumTargetFixupKinds 

Definition at line 17 of file AMDGPUFixupKinds.h.

◆ OperandType

Enumerator
OPERAND_REG_IMM_INT32 

Operands with register or 32-bit immediate.

OPERAND_REG_IMM_INT64 
OPERAND_REG_IMM_INT16 
OPERAND_REG_IMM_FP32 
OPERAND_REG_IMM_FP64 
OPERAND_REG_IMM_FP16 
OPERAND_REG_INLINE_C_INT16 

Operands with register or inline constant.

OPERAND_REG_INLINE_C_INT32 
OPERAND_REG_INLINE_C_INT64 
OPERAND_REG_INLINE_C_FP16 
OPERAND_REG_INLINE_C_FP32 
OPERAND_REG_INLINE_C_FP64 
OPERAND_REG_INLINE_C_V2FP16 
OPERAND_REG_INLINE_C_V2INT16 
OPERAND_REG_IMM_FIRST 
OPERAND_REG_IMM_LAST 
OPERAND_REG_INLINE_C_FIRST 
OPERAND_REG_INLINE_C_LAST 
OPERAND_SRC_FIRST 
OPERAND_SRC_LAST 
OPERAND_INPUT_MODS 
OPERAND_SDWA_VOPC_DST 
OPERAND_KIMM32 

Operand with 32-bit immediate that uses the constant bus.

OPERAND_KIMM16 

Definition at line 111 of file SIDefines.h.

◆ TargetFlags

Enumerator
TF_LONG_BRANCH_FORWARD 
TF_LONG_BRANCH_BACKWARD 

Definition at line 925 of file SIInstrInfo.h.

◆ TargetIndex

Enumerator
TI_CONSTDATA_START 
TI_SCRATCH_RSRC_DWORD0 
TI_SCRATCH_RSRC_DWORD1 
TI_SCRATCH_RSRC_DWORD2 
TI_SCRATCH_RSRC_DWORD3 

Definition at line 203 of file AMDGPU.h.

Function Documentation

◆ decodeExpcnt()

unsigned llvm::AMDGPU::decodeExpcnt ( const IsaInfo::IsaVersion Version,
unsigned  Waitcnt 
)
Returns
Decoded Expcnt from given Waitcnt for given isa Version.

Definition at line 547 of file AMDGPUBaseInfo.cpp.

Referenced by decodeWaitcnt(), encodeCnt(), and readsVCCZ().

◆ decodeLgkmcnt()

unsigned llvm::AMDGPU::decodeLgkmcnt ( const IsaInfo::IsaVersion Version,
unsigned  Waitcnt 
)
Returns
Decoded Lgkmcnt from given Waitcnt for given isa Version.

Definition at line 551 of file AMDGPUBaseInfo.cpp.

Referenced by decodeWaitcnt(), encodeCnt(), and readsVCCZ().

◆ decodeVmcnt()

unsigned llvm::AMDGPU::decodeVmcnt ( const IsaInfo::IsaVersion Version,
unsigned  Waitcnt 
)
Returns
Decoded Vmcnt from given Waitcnt for given isa Version.

Definition at line 535 of file AMDGPUBaseInfo.cpp.

References llvm::AMDGPU::IsaInfo::IsaVersion::Major.

Referenced by decodeWaitcnt(), encodeCnt(), and readsVCCZ().

◆ decodeWaitcnt()

void llvm::AMDGPU::decodeWaitcnt ( const IsaInfo::IsaVersion Version,
unsigned  Waitcnt,
unsigned Vmcnt,
unsigned Expcnt,
unsigned Lgkmcnt 
)

Decodes Vmcnt, Expcnt and Lgkmcnt from given Waitcnt for given isa Version, and writes decoded values into Vmcnt, Expcnt and Lgkmcnt respectively.

Vmcnt, Expcnt and Lgkmcnt are decoded as follows: Vmcnt = Waitcnt[3:0] (pre-gfx9 only) Vmcnt = Waitcnt[3:0] | Waitcnt[15:14] (gfx9+ only) Expcnt = Waitcnt[6:4] Lgkmcnt = Waitcnt[11:8]

Definition at line 555 of file AMDGPUBaseInfo.cpp.

References decodeExpcnt(), decodeLgkmcnt(), and decodeVmcnt().

Referenced by llvm::AMDGPUInstPrinter::printWaitFlag().

◆ encodeExpcnt()

unsigned llvm::AMDGPU::encodeExpcnt ( const IsaInfo::IsaVersion Version,
unsigned  Waitcnt,
unsigned  Expcnt 
)
Returns
Waitcnt with encoded Expcnt for given isa Version.

Definition at line 573 of file AMDGPUBaseInfo.cpp.

Referenced by encodeCnt(), and encodeWaitcnt().

◆ encodeLgkmcnt()

unsigned llvm::AMDGPU::encodeLgkmcnt ( const IsaInfo::IsaVersion Version,
unsigned  Waitcnt,
unsigned  Lgkmcnt 
)
Returns
Waitcnt with encoded Lgkmcnt for given isa Version.

Definition at line 578 of file AMDGPUBaseInfo.cpp.

Referenced by encodeCnt(), and encodeWaitcnt().

◆ encodeVmcnt()

unsigned llvm::AMDGPU::encodeVmcnt ( const IsaInfo::IsaVersion Version,
unsigned  Waitcnt,
unsigned  Vmcnt 
)
Returns
Waitcnt with encoded Vmcnt for given isa Version.

Definition at line 562 of file AMDGPUBaseInfo.cpp.

References llvm::AMDGPU::IsaInfo::IsaVersion::Major.

Referenced by encodeCnt(), and encodeWaitcnt().

◆ encodeWaitcnt()

unsigned llvm::AMDGPU::encodeWaitcnt ( const IsaInfo::IsaVersion Version,
unsigned  Vmcnt,
unsigned  Expcnt,
unsigned  Lgkmcnt 
)

Encodes Vmcnt, Expcnt and Lgkmcnt into Waitcnt for given isa Version.

Vmcnt, Expcnt and Lgkmcnt are encoded as follows: Waitcnt[3:0] = Vmcnt (pre-gfx9 only) Waitcnt[3:0] = Vmcnt[3:0] (gfx9+ only) Waitcnt[6:4] = Expcnt Waitcnt[11:8] = Lgkmcnt Waitcnt[15:14] = Vmcnt[5:4] (gfx9+ only)

Returns
Waitcnt with encoded Vmcnt, Expcnt and Lgkmcnt for given isa Version.

Definition at line 583 of file AMDGPUBaseInfo.cpp.

References encodeExpcnt(), encodeLgkmcnt(), encodeVmcnt(), and getWaitcntBitMask().

Referenced by readsVCCZ().

◆ getAddr64Inst()

LLVM_READONLY int llvm::AMDGPU::getAddr64Inst ( uint16_t  Opcode)

◆ getAMDGPUAS() [1/3]

AMDGPUAS llvm::AMDGPU::getAMDGPUAS ( const Module M)

◆ getAMDGPUAS() [2/3]

AMDGPUAS llvm::AMDGPU::getAMDGPUAS ( const TargetMachine TM)

Definition at line 941 of file AMDGPUBaseInfo.cpp.

References getAMDGPUAS(), and llvm::TargetMachine::getTargetTriple().

◆ getAMDGPUAS() [3/3]

AMDGPUAS llvm::AMDGPU::getAMDGPUAS ( Triple  T)

◆ getAtomicNoRetOp()

LLVM_READONLY int llvm::AMDGPU::getAtomicNoRetOp ( uint16_t  Opcode)

◆ getAtomicRetOp()

LLVM_READONLY int llvm::AMDGPU::getAtomicRetOp ( uint16_t  Opcode)

◆ getBasicFromSDWAOp()

LLVM_READONLY int llvm::AMDGPU::getBasicFromSDWAOp ( uint16_t  Opcode)

◆ getCommuteOrig()

LLVM_READONLY int llvm::AMDGPU::getCommuteOrig ( uint16_t  Opcode)

◆ getCommuteRev()

LLVM_READONLY int llvm::AMDGPU::getCommuteRev ( uint16_t  Opcode)

◆ getExpcntBitMask()

unsigned llvm::AMDGPU::getExpcntBitMask ( const IsaInfo::IsaVersion Version)
Returns
Expcnt bit mask for given isa Version.

Definition at line 515 of file AMDGPUBaseInfo.cpp.

Referenced by llvm::AMDGPUInstPrinter::printWaitFlag(), and readsVCCZ().

◆ getInitialPSInputAddr()

unsigned llvm::AMDGPU::getInitialPSInputAddr ( const Function F)

◆ getIntegerAttribute()

int llvm::AMDGPU::getIntegerAttribute ( const Function F,
StringRef  Name,
int  Default 
)

◆ getIntegerPairAttribute()

std::pair< int, int > llvm::AMDGPU::getIntegerPairAttribute ( const Function F,
StringRef  Name,
std::pair< int, int >  Default,
bool  OnlyFirstRequired = false 
)
Returns
A pair of integer values requested using F's Name attribute in "first[,second]" format ("second" is optional unless OnlyFirstRequired is false).
Default if attribute is not present.
Default and emits error if one of the requested values cannot be converted to integer, or OnlyFirstRequired is false and "second" value is not present.

Definition at line 481 of file AMDGPUBaseInfo.cpp.

References llvm::LLVMContext::emitError(), llvm::Function::getContext(), llvm::Function::getFnAttribute(), llvm::Attribute::getValueAsString(), llvm::Attribute::isStringAttribute(), and llvm::StringRef::split().

Referenced by llvm::AMDGPUSubtarget::getFlatWorkGroupSizes(), and llvm::AMDGPUSubtarget::getWavesPerEU().

◆ getLDSNoRetOp()

int llvm::AMDGPU::getLDSNoRetOp ( uint16_t  Opcode)

◆ getLgkmcntBitMask()

unsigned llvm::AMDGPU::getLgkmcntBitMask ( const IsaInfo::IsaVersion Version)
Returns
Lgkmcnt bit mask for given isa Version.

Definition at line 519 of file AMDGPUBaseInfo.cpp.

Referenced by llvm::AMDGPUInstPrinter::printWaitFlag(), and readsVCCZ().

◆ getMaskedMIMGAtomicOp()

LLVM_READONLY int llvm::AMDGPU::getMaskedMIMGAtomicOp ( const MCInstrInfo MII,
unsigned  Opc,
unsigned  NewChannels 
)

◆ getMaskedMIMGOp()

LLVM_READONLY int llvm::AMDGPU::getMaskedMIMGOp ( const MCInstrInfo MII,
unsigned  Opc,
unsigned  NewChannels 
)

◆ getMCOpcode()

LLVM_READONLY int llvm::AMDGPU::getMCOpcode ( uint16_t  Opcode,
unsigned  Gen 
)

Definition at line 180 of file AMDGPUBaseInfo.cpp.

Referenced by llvm::AMDGPUInstrInfo::pseudoToMCOpcode().

◆ getMCReg()

unsigned llvm::AMDGPU::getMCReg ( unsigned  Reg,
const MCSubtargetInfo STI 
)

If Reg is a pseudo reg, return the correct hardware register given STI otherwise return Reg.

Definition at line 726 of file AMDGPUBaseInfo.cpp.

References MAP_REG2REG.

Referenced by llvm::AMDGPUDisassembler::createRegOperand(), getVariantKind(), and isKernel().

◆ getMUBUFNoLdsInst()

LLVM_READONLY int llvm::AMDGPU::getMUBUFNoLdsInst ( uint16_t  Opcode)

◆ getNamedOperandIdx()

LLVM_READONLY int16_t llvm::AMDGPU::getNamedOperandIdx ( uint16_t  Opcode,
uint16_t  NamedIdx 
)

◆ getOperandSize() [1/2]

LLVM_READNONE unsigned llvm::AMDGPU::getOperandSize ( const MCOperandInfo OpInfo)
inline

◆ getOperandSize() [2/2]

LLVM_READNONE unsigned llvm::AMDGPU::getOperandSize ( const MCInstrDesc Desc,
unsigned  OpNo 
)
inline

◆ getRegBitWidth() [1/2]

unsigned llvm::AMDGPU::getRegBitWidth ( unsigned  RCID)

◆ getRegBitWidth() [2/2]

unsigned llvm::AMDGPU::getRegBitWidth ( const MCRegisterClass RC)

Get the size in bits of a register from the register class RC.

Definition at line 807 of file AMDGPUBaseInfo.cpp.

References llvm::MCRegisterClass::getID(), and getRegBitWidth().

◆ getRegOperandSize()

unsigned llvm::AMDGPU::getRegOperandSize ( const MCRegisterInfo MRI,
const MCInstrDesc Desc,
unsigned  OpNo 
)

◆ getSDWAOp()

LLVM_READONLY int llvm::AMDGPU::getSDWAOp ( uint16_t  Opcode)

◆ getSMRDEncodedOffset()

int64_t llvm::AMDGPU::getSMRDEncodedOffset ( const MCSubtargetInfo ST,
int64_t  ByteOffset 
)
Returns
The encoding that will be used for ByteOffset in the SMRD offset field.

Definition at line 914 of file AMDGPUBaseInfo.cpp.

References isGCN3Encoding().

Referenced by canMoveInstsAcrossMemOp(), getOperandSize(), getSmrdOpcode(), isLegalSMRDImmOffset(), and isStackPtrRelative().

◆ getSOPKOp()

LLVM_READONLY int llvm::AMDGPU::getSOPKOp ( uint16_t  Opcode)

◆ getVmcntBitMask()

unsigned llvm::AMDGPU::getVmcntBitMask ( const IsaInfo::IsaVersion Version)
Returns
Vmcnt bit mask for given isa Version.

Definition at line 506 of file AMDGPUBaseInfo.cpp.

References llvm::AMDGPU::IsaInfo::IsaVersion::Major.

Referenced by llvm::AMDGPUInstPrinter::printWaitFlag(), and readsVCCZ().

◆ getVOPe32()

LLVM_READONLY int llvm::AMDGPU::getVOPe32 ( uint16_t  Opcode)

◆ getVOPe64()

LLVM_READONLY int llvm::AMDGPU::getVOPe64 ( uint16_t  Opcode)

◆ getWaitcntBitMask()

unsigned llvm::AMDGPU::getWaitcntBitMask ( const IsaInfo::IsaVersion Version)
Returns
Waitcnt bit mask for given isa Version.

Definition at line 523 of file AMDGPUBaseInfo.cpp.

References llvm::AMDGPU::IsaInfo::IsaVersion::Major.

Referenced by encodeCnt(), and encodeWaitcnt().

◆ hasMIMG_R128()

bool llvm::AMDGPU::hasMIMG_R128 ( const MCSubtargetInfo STI)

Definition at line 636 of file AMDGPUBaseInfo.cpp.

References llvm::MCSubtargetInfo::getFeatureBits().

Referenced by getSpecialRegForName(), and isKernel().

◆ hasPackedD16()

bool llvm::AMDGPU::hasPackedD16 ( const MCSubtargetInfo STI)

◆ hasXNACK()

bool llvm::AMDGPU::hasXNACK ( const MCSubtargetInfo STI)

◆ indexToChannel()

static LLVM_READNONE Channels llvm::AMDGPU::indexToChannel ( unsigned  Channel)
inlinestatic

Definition at line 103 of file AMDGPUBaseInfo.cpp.

References llvm_unreachable.

Referenced by getMaskedMIMGOp().

◆ initDefaultAMDKernelCodeT()

void llvm::AMDGPU::initDefaultAMDKernelCodeT ( amd_kernel_code_t Header,
const FeatureBitset Features 
)

◆ isArgPassedInSGPR()

bool llvm::AMDGPU::isArgPassedInSGPR ( const Argument A)

◆ isCI()

bool llvm::AMDGPU::isCI ( const MCSubtargetInfo STI)

◆ isCompute()

LLVM_READNONE bool llvm::AMDGPU::isCompute ( CallingConv::ID  cc)

◆ isEntryFunctionCC()

LLVM_READNONE bool llvm::AMDGPU::isEntryFunctionCC ( CallingConv::ID  CC)

◆ isGCN3Encoding()

bool llvm::AMDGPU::isGCN3Encoding ( const MCSubtargetInfo STI)

◆ isGFX9()

bool llvm::AMDGPU::isGFX9 ( const MCSubtargetInfo STI)

Definition at line 656 of file AMDGPUBaseInfo.cpp.

References llvm::MCSubtargetInfo::getFeatureBits().

Referenced by getSpecialRegForName(), and isKernel().

◆ isGlobalSegment()

bool llvm::AMDGPU::isGlobalSegment ( const GlobalValue GV)

◆ isGroupSegment()

bool llvm::AMDGPU::isGroupSegment ( const GlobalValue GV)

◆ isInlinableLiteral16()

LLVM_READNONE bool llvm::AMDGPU::isInlinableLiteral16 ( int16_t  Literal,
bool  HasInv2Pi 
)

◆ isInlinableLiteral32()

LLVM_READNONE bool llvm::AMDGPU::isInlinableLiteral32 ( int32_t  Literal,
bool  HasInv2Pi 
)

◆ isInlinableLiteral64()

LLVM_READNONE bool llvm::AMDGPU::isInlinableLiteral64 ( int64_t  Literal,
bool  HasInv2Pi 
)

Is this literal inlinable.

Definition at line 818 of file AMDGPUBaseInfo.cpp.

References llvm::DoubleToBits().

Referenced by getOperandSize(), getSpecialRegForName(), and llvm::SIInstrInfo::isInlineConstant().

◆ isInlinableLiteralV216()

LLVM_READNONE bool llvm::AMDGPU::isInlinableLiteralV216 ( int32_t  Literal,
bool  HasInv2Pi 
)

◆ isIntrinsicSourceOfDivergence()

bool llvm::AMDGPU::isIntrinsicSourceOfDivergence ( unsigned  IntrID)
Returns
true if the intrinsic is divergent

Definition at line 961 of file AMDGPUBaseInfo.cpp.

Referenced by getOperandSize(), llvm::SITargetLowering::isSDNodeSourceOfDivergence(), and llvm::GCNTTIImpl::isSourceOfDivergence().

◆ isKernel()

LLVM_READNONE bool llvm::AMDGPU::isKernel ( CallingConv::ID  CC)
inline

◆ isLegalSMRDImmOffset()

bool llvm::AMDGPU::isLegalSMRDImmOffset ( const MCSubtargetInfo ST,
int64_t  ByteOffset 
)
Returns
true if this offset is small enough to fit in the SMRD offset field. ByteOffset should be the offset in bytes and not the encoded offset.

Definition at line 920 of file AMDGPUBaseInfo.cpp.

References getSMRDEncodedOffset(), isGCN3Encoding(), and llvm::isUInt< 8 >().

Referenced by getOperandSize(), getSmrdOpcode(), and isStackPtrRelative().

◆ isReadOnlySegment()

bool llvm::AMDGPU::isReadOnlySegment ( const GlobalValue GV)

◆ isRegIntersect()

bool llvm::AMDGPU::isRegIntersect ( unsigned  Reg0,
unsigned  Reg1,
const MCRegisterInfo TRI 
)

Is there any intersection between registers.

Definition at line 671 of file AMDGPUBaseInfo.cpp.

Referenced by getSpecialRegForName(), and isKernel().

◆ isSGPR()

bool llvm::AMDGPU::isSGPR ( unsigned  Reg,
const MCRegisterInfo TRI 
)

◆ isShader()

LLVM_READNONE bool llvm::AMDGPU::isShader ( CallingConv::ID  cc)

◆ isSI()

bool llvm::AMDGPU::isSI ( const MCSubtargetInfo STI)

◆ isSISrcFPOperand()

bool llvm::AMDGPU::isSISrcFPOperand ( const MCInstrDesc Desc,
unsigned  OpNo 
)

◆ isSISrcInlinableOperand()

bool llvm::AMDGPU::isSISrcInlinableOperand ( const MCInstrDesc Desc,
unsigned  OpNo 
)

Does this opearnd support only inlinable literals?

Definition at line 768 of file AMDGPUBaseInfo.cpp.

References assert(), llvm::MCInstrDesc::NumOperands, OPERAND_REG_INLINE_C_FIRST, OPERAND_REG_INLINE_C_LAST, llvm::MCOperandInfo::OperandType, and llvm::MCInstrDesc::OpInfo.

Referenced by isKernel().

◆ isSISrcOperand()

bool llvm::AMDGPU::isSISrcOperand ( const MCInstrDesc Desc,
unsigned  OpNo 
)

◆ isVI()

bool llvm::AMDGPU::isVI ( const MCSubtargetInfo STI)

◆ laneDominates()

bool llvm::AMDGPU::laneDominates ( MachineBasicBlock A,
MachineBasicBlock B 
)

◆ lookupD16ImageDimIntrinsicByIntr()

const D16ImageDimIntrinsic* llvm::AMDGPU::lookupD16ImageDimIntrinsicByIntr ( unsigned  Intr)

◆ lookupRsrcIntrinsicByIntr()

const RsrcIntrinsic* llvm::AMDGPU::lookupRsrcIntrinsicByIntr ( unsigned  Intr)

◆ mc2PseudoReg()

LLVM_READNONE unsigned llvm::AMDGPU::mc2PseudoReg ( unsigned  Reg)

Convert hardware register Reg to a pseudo register.

Definition at line 736 of file AMDGPUBaseInfo.cpp.

References MAP_REG2REG.

Referenced by getLit64Encoding(), getSpecialRegForName(), and isKernel().

◆ rcToChannels()

static unsigned llvm::AMDGPU::rcToChannels ( unsigned  RCID)
static

Definition at line 120 of file AMDGPUBaseInfo.cpp.

References llvm_unreachable.

Referenced by getMaskedMIMGAtomicOp(), and getMaskedMIMGOp().

◆ shouldEmitConstantsToTextSection()

bool llvm::AMDGPU::shouldEmitConstantsToTextSection ( const Triple TT)
Returns
True if constants should be emitted to .text section for given target triple TT, false otherwise.

Definition at line 462 of file AMDGPUBaseInfo.cpp.

References llvm::Triple::AMDHSA, and llvm::Triple::getOS().

Referenced by findUser(), and llvm::AMDGPUTargetObjectFile::SelectSectionForGlobal().

Variable Documentation

◆ RSRC_DATA_FORMAT

const uint64_t llvm::AMDGPU::RSRC_DATA_FORMAT = 0xf00000000000LL

◆ RSRC_ELEMENT_SIZE_SHIFT

const uint64_t llvm::AMDGPU::RSRC_ELEMENT_SIZE_SHIFT = (32 + 19)

Definition at line 920 of file SIInstrInfo.h.

Referenced by llvm::SIInstrInfo::getScratchRsrcWords23().

◆ RSRC_INDEX_STRIDE_SHIFT

const uint64_t llvm::AMDGPU::RSRC_INDEX_STRIDE_SHIFT = (32 + 21)

Definition at line 921 of file SIInstrInfo.h.

Referenced by llvm::SIInstrInfo::getScratchRsrcWords23().

◆ RSRC_TID_ENABLE

const uint64_t llvm::AMDGPU::RSRC_TID_ENABLE = UINT64_C(1) << (32 + 23)

Definition at line 922 of file SIInstrInfo.h.

Referenced by llvm::SIInstrInfo::getScratchRsrcWords23().